diff -Nru a/Documentation/ia64/README b/Documentation/ia64/README --- a/Documentation/ia64/README Wed Jan 15 16:57:29 2003 +++ b/Documentation/ia64/README Wed Jan 15 16:57:29 2003 @@ -4,40 +4,40 @@ platform. This document provides information specific to IA-64 ONLY, to get additional information about the Linux kernel also read the original Linux README provided with the kernel. - + INSTALLING the kernel: - IA-64 kernel installation is the same as the other platforms, see original README for details. - - + + SOFTWARE REQUIREMENTS Compiling and running this kernel requires an IA-64 compliant GCC compiler. And various software packages also compiled with an IA-64 compliant GCC compiler. - + CONFIGURING the kernel: Configuration is the same, see original README for details. - - + + COMPILING the kernel: - Compiling this kernel doesn't differ from other platform so read the original README for details BUT make sure you have an IA-64 compliant GCC compiler. - + IA-64 SPECIFICS - General issues: - + o Hardly any performance tuning has been done. Obvious targets include the library routines (IP checksum, etc.). Less obvious targets include making sure we don't flush the TLB needlessly, etc. - + o SMP locks cleanup/optimization - + o IA32 support. Currently experimental. It mostly works. diff -Nru a/Documentation/ia64/fsys.txt b/Documentation/ia64/fsys.txt --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/Documentation/ia64/fsys.txt Wed Jan 15 16:57:29 2003 @@ -0,0 +1,230 @@ +-*-Mode: outline-*- + + Light-weight System Calls for IA-64 + ----------------------------------- + + Started: 13-Jan-2002 + Last update: 15-Jan-2002 + + David Mosberger-Tang + + +Using the "epc" instruction effectively introduces a new mode of +execution to the ia64 linux kernel. We call this mode the +"fsys-mode". To recap, the normal states of execution are: + + - kernel mode: + Both the register stack and the memory stack have been + switched over to kernel memory. The user-level state is saved + in a pt-regs structure at the top of the kernel memory stack. + + - user mode: + Both the register stack and the kernel stack are in + user memory. The user-level state is contained in the + CPU registers. + + - bank 0 interruption-handling mode: + This is the non-interruptible state which all + interruption-handlers start execution in. The user-level + state remains in the CPU registers and some kernel state may + be stored in bank 0 of registers r16-r31. + +In contrast, fsys-mode has the following special properties: + + - execution is at privilege level 0 (most-privileged) + + - CPU registers may contain a mixture of user-level and kernel-level + state (it is the responsibility of the kernel to ensure that no + security-sensitive kernel-level state is leaked back to + user-level) + + - execution is interruptible and preemptible (an fsys-mode handler + can disable interrupts and avoid all other interruption-sources + to avoid preemption) + + - neither the memory nor the register stack can be trusted while + in fsys-mode (they point to the user-level stacks, which may + be invalid) + +In summary, fsys-mode is much more similar to running in user-mode +than it is to running in kernel-mode. Of course, given that the +privilege level is at level 0, this means that fsys-mode requires some +care (see below). + + +* How to tell fsys-mode + +Linux operates in fsys-mode when (a) the privilege level is 0 (most +privileged) and (b) the stacks have NOT been switched to kernel memory +yet. For convenience, the header file provides +three macros: + + user_mode(regs) + user_stack(task,regs) + fsys_mode(task,regs) + +The "regs" argument is a pointer to a pt_regs structure. The "task" +argument is a pointer to the task structure to which the "regs" +pointer belongs to. user_mode() returns TRUE if the CPU state pointed +to by "regs" was executing in user mode (privilege level 3). +user_stack() returns TRUE if the state pointed to by "regs" was +executing on the user-level stack(s). Finally, fsys_mode() returns +TRUE if the CPU state pointed to by "regs" was executing in fsys-mode. +The fsys_mode() macro is equivalent to the expression: + + !user_mode(regs) && user_stack(task,regs) + +* How to write an fsyscall handler + +The file arch/ia64/kernel/fsys.S contains a table of fsyscall-handlers +(fsyscall_table). This table contains one entry for each system call. +By default, a system call is handled by fsys_fallback_syscall(). This +routine takes care of entering (full) kernel mode and calling the +normal Linux system call handler. For performance-critical system +calls, it is possible to write a hand-tuned fsyscall_handler. For +example, fsys.S contains fsys_getpid(), which is a hand-tuned version +of the getpid() system call. + +The entry and exit-state of an fsyscall handler is as follows: + +** Machine state on entry to fsyscall handler: + + - r11 = saved ar.pfs (a user-level value) + - r15 = system call number + - r16 = "current" task pointer (in normal kernel-mode, this is in r13) + - r32-r39 = system call arguments + - b6 = return address (a user-level value) + - ar.pfs = previous frame-state (a user-level value) + - PSR.be = cleared to zero (i.e., little-endian byte order is in effect) + - all other registers may contain values passed in from user-mode + +** Required machine state on exit to fsyscall handler: + + - r11 = saved ar.pfs (as passed into the fsyscall handler) + - r15 = system call number (as passed into the fsyscall handler) + - r32-r39 = system call arguments (as passed into the fsyscall handler) + - b6 = return address (as passed into the fsyscall handler) + - ar.pfs = previous frame-state (as passed into the fsyscall handler) + +Fsyscall handlers can execute with very little overhead, but with that +speed comes a set of restrictions: + + o Fsyscall-handlers MUST check for any pending work in the flags + member of the thread-info structure and if any of the + TIF_ALLWORK_MASK flags are set, the handler needs to fall back on + doing a full system call (by calling fsys_fallback_syscall). + + o Fsyscall-handlers MUST preserve incoming arguments (r32-r39, r11, + r15, b6, and ar.pfs) because they will be needed in case of a + system call restart. Of course, all "preserved" registers also + must be preserved, in accordance to the normal calling conventions. + + o Fsyscall-handlers MUST check argument registers for containing a + NaT value before using them in any way that could trigger a + NaT-consumption fault. If a system call argument is found to + contain a NaT value, an fsyscall-handler may return immediately + with r8=EINVAL, r10=-1. + + o Fsyscall-handlers MUST NOT use the "alloc" instruction or perform + any other operation that would trigger mandatory RSE + (register-stack engine) traffic. + + o Fsyscall-handlers MUST NOT write to any stacked registers because + it is not safe to assume that user-level called a handler with the + proper number of arguments. + + o Fsyscall-handlers need to be careful when accessing per-CPU variables: + unless proper safe-guards are taken (e.g., interruptions are avoided), + execution may be pre-empted and resumed on another CPU at any given + time. + + o Fsyscall-handlers must be careful not to leak sensitive kernel' + information back to user-level. In particular, before returning to + user-level, care needs to be taken to clear any scratch registers + that could contain sensitive information (note that the current + task pointer is not considered sensitive: it's already exposed + through ar.k6). + +The above restrictions may seem draconian, but remember that it's +possible to trade off some of the restrictions by paying a slightly +higher overhead. For example, if an fsyscall-handler could benefit +from the shadow register bank, it could temporarily disable PSR.i and +PSR.ic, switch to bank 0 (bsw.0) and then use the shadow registers as +needed. In other words, following the above rules yields extremely +fast system call execution (while fully preserving system call +semantics), but there is also a lot of flexibility in handling more +complicated cases. + +* Signal handling + +The delivery of (asynchronous) signals must be delayed until fsys-mode +is exited. This is acomplished with the help of the lower-privilege +transfer trap: arch/ia64/kernel/process.c:do_notify_resume_user() +checks whether the interrupted task was in fsys-mode and, if so, sets +PSR.lp and returns immediately. When fsys-mode is exited via the +"br.ret" instruction that lowers the privilege level, a trap will +occur. The trap handler clears PSR.lp again and returns immediately. +The kernel exit path then checks for and delivers any pending signals. + +* PSR Handling + +The "epc" instruction doesn't change the contents of PSR at all. This +is in contrast to a regular interruption, which clears almost all +bits. Because of that, some care needs to be taken to ensure things +work as expected. The following discussion describes how each PSR bit +is handled. + +PSR.be Cleared when entering fsys-mode. A srlz.d instruction is used + to ensure the CPU is in little-endian mode before the first + load/store instruction is executed. PSR.be is normally NOT + restored upon return from an fsys-mode handler. In other + words, user-level code must not rely on PSR.be being preserved + across a system call. +PSR.up Unchanged. +PSR.ac Unchanged. +PSR.mfl Unchanged. Note: fsys-mode handlers must not write-registers! +PSR.mfh Unchanged. Note: fsys-mode handlers must not write-registers! +PSR.ic Unchanged. Note: fsys-mode handlers can clear the bit, if needed. +PSR.i Unchanged. Note: fsys-mode handlers can clear the bit, if needed. +PSR.pk Unchanged. +PSR.dt Unchanged. +PSR.dfl Unchanged. Note: fsys-mode handlers must not write-registers! +PSR.dfh Unchanged. Note: fsys-mode handlers must not write-registers! +PSR.sp Unchanged. +PSR.pp Unchanged. +PSR.di Unchanged. +PSR.si Unchanged. +PSR.db Unchanged. The kernel prevents user-level from setting a hardware + breakpoint that triggers at any privilege level other than 3 (user-mode). +PSR.lp Unchanged. +PSR.tb Lazy redirect. If a taken-branch trap occurs while in + fsys-mode, the trap-handler modifies the saved machine state + such that execution resumes in the gate page at + syscall_via_break(), with privilege level 3. Note: the + taken branch would occur on the branch invoking the + fsyscall-handler, at which point, by definition, a syscall + restart is still safe. If the system call number is invalid, + the fsys-mode handler will return directly to user-level. This + return will trigger a taken-branch trap, but since the trap is + taken _after_ restoring the privilege level, the CPU has already + left fsys-mode, so no special treatment is needed. +PSR.rt Unchanged. +PSR.cpl Cleared to 0. +PSR.is Unchanged (guaranteed to be 0 on entry to the gate page). +PSR.mc Unchanged. +PSR.it Unchanged (guaranteed to be 1). +PSR.id Unchanged. Note: the ia64 linux kernel never sets this bit. +PSR.da Unchanged. Note: the ia64 linux kernel never sets this bit. +PSR.dd Unchanged. Note: the ia64 linux kernel never sets this bit. +PSR.ss Lazy redirect. If set, "epc" will cause a Single Step Trap to + be taken. The trap handler then modifies the saved machine + state such that execution resumes in the gate page at + syscall_via_break(), with privilege level 3. +PSR.ri Unchanged. +PSR.ed Unchanged. Note: This bit could only have an effect if an fsys-mode + handler performed a speculative load that gets NaTted. If so, this + would be the normal & expected behavior, so no special treatment is + needed. +PSR.bn Unchanged. Note: fsys-mode handlers may clear the bit, if needed. + Doing so requires clearing PSR.i and PSR.ic as well. +PSR.ia Unchanged. Note: the ia64 linux kernel never sets this bit. diff -Nru a/Documentation/mmio_barrier.txt b/Documentation/mmio_barrier.txt --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/Documentation/mmio_barrier.txt Wed Jan 15 16:57:29 2003 @@ -0,0 +1,15 @@ +On some platforms, so-called memory-mapped I/O is weakly ordered. For +example, the following might occur: + +CPU A writes 0x1 to Device #1 +CPU B writes 0x2 to Device #1 +Device #1 sees 0x2 +Device #1 sees 0x1 + +On such platforms, driver writers are responsible for ensuring that I/O +writes to memory-mapped addresses on their device arrive in the order +intended. The mmiob() macro is provided for this purpose. A typical use +of this macro might be immediately prior to the exit of a critical +section of code proteced by spinlocks. This would ensure that subsequent +writes to I/O space arrived only after all prior writes (much like a +typical memory barrier op, mb(), only with respect to I/O). diff -Nru a/Makefile b/Makefile --- a/Makefile Wed Jan 15 16:57:28 2003 +++ b/Makefile Wed Jan 15 16:57:28 2003 @@ -170,7 +170,7 @@ NOSTDINC_FLAGS = -nostdinc -iwithprefix include CPPFLAGS := -D__KERNEL__ -Iinclude -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \ +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -g -O2 \ -fno-strict-aliasing -fno-common AFLAGS := -D__ASSEMBLY__ $(CPPFLAGS) @@ -854,7 +854,7 @@ # FIXME Should go into a make.lib or something # =========================================================================== -a_flags = -Wp,-MD,$(depfile) $(AFLAGS) $(NOSTDINC_FLAGS) \ +a_flags = -Wp,-MD,$(depfile) $(AFLAGS) $(AFLAGS_KERNEL) $(NOSTDINC_FLAGS) \ $(modkern_aflags) $(EXTRA_AFLAGS) $(AFLAGS_$(*F).o) quiet_cmd_as_s_S = CPP $@ diff -Nru a/arch/ia64/Kconfig b/arch/ia64/Kconfig --- a/arch/ia64/Kconfig Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/Kconfig Wed Jan 15 16:57:29 2003 @@ -1,3 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see Documentation/kbuild/kconfig-language.txt. +# + mainmenu "IA-64 Linux Kernel Configuration" source "init/Kconfig" @@ -215,6 +220,22 @@ Access). This option is for configuring high-end multiprocessor server systems. If in doubt, say N. +choice + prompt "Maximum Memory per NUMA Node" if NUMA && IA64_DIG + depends on NUMA && IA64_DIG + default IA64_NODESIZE_16GB + +config IA64_NODESIZE_16GB + bool "16GB" + +config IA64_NODESIZE_64GB + bool "64GB" + +config IA64_NODESIZE_256GB + bool "256GB" + +endchoice + config DISCONTIGMEM bool depends on IA64_SGI_SN1 || IA64_SGI_SN2 || (IA64_GENERIC || IA64_DIG || IA64_HP_ZX1) && NUMA @@ -225,6 +246,21 @@ or have huge holes in the physical address space for other reasons. See for more. +config VIRTUAL_MEM_MAP + bool "Enable Virtual Mem Map" + depends on !NUMA + default y if IA64_GENERIC || IA64_DIG || IA64_HP_ZX1 + help + Say Y to compile the kernel with support for a virtual mem map. + This is an alternate method of supporting large holes in the + physical address space on non NUMA machines. Since the DISCONTIGMEM + option is not supported on machines with the ZX1 chipset, this is + the only way of supporting more than 1 Gb of memory on those + machines. This code also only takes effect if a memory hole of + greater than 1 Gb is found during boot, so it is safe to enable + unless you require the DISCONTIGMEM option for your machine. If you + are unsure, say Y. + config IA64_MCA bool "Enable IA-64 Machine Check Abort" if IA64_GENERIC || IA64_DIG || IA64_HP_ZX1 default y if IA64_SGI_SN1 || IA64_SGI_SN2 @@ -397,6 +433,11 @@ run IA-32 Linux binaries on an IA-64 Linux system. If in doubt, say Y. +config COMPAT + bool + depends on IA32_SUPPORT + default y + config PERFMON bool "Performance monitor support" help @@ -764,6 +805,9 @@ menu "Kernel hacking" + +config FSYS + bool "Light-weight system-call support (via epc)" choice prompt "Physical memory granularity" diff -Nru a/arch/ia64/Makefile b/arch/ia64/Makefile --- a/arch/ia64/Makefile Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/Makefile Wed Jan 15 16:57:28 2003 @@ -5,76 +5,69 @@ # License. See the file "COPYING" in the main directory of this archive # for more details. # -# Copyright (C) 1998-2001 by David Mosberger-Tang +# Copyright (C) 1998-2002 by David Mosberger-Tang # NM := $(CROSS_COMPILE)nm -B -AWK := awk export AWK -OBJCOPYFLAGS := --strip-all -LDFLAGS_vmlinux := -static -AFLAGS_KERNEL := -mconstant-gp -EXTRA = - -CFLAGS := $(CFLAGS) -pipe $(EXTRA) -ffixed-r13 -mfixed-range=f10-f15,f32-f127 \ - -falign-functions=32 -# -ffunction-sections -CFLAGS_KERNEL := -mconstant-gp +OBJCOPYFLAGS := --strip-all +LDFLAGS_vmlinux := -static +AFLAGS_KERNEL := -mconstant-gp +EXTRA := + +cflags-y := -pipe $(EXTRA) -ffixed-r13 -mfixed-range=f10-f15,f32-f127 \ + -falign-functions=32 +CFLAGS_KERNEL := -mconstant-gp GCC_VERSION=$(shell $(CC) -v 2>&1 | fgrep 'gcc version' | cut -f3 -d' ' | cut -f1 -d'.') ifneq ($(GCC_VERSION),2) - CFLAGS += -frename-registers --param max-inline-insns=5000 + cflags-y += -frename-registers --param max-inline-insns=5000 endif -ifeq ($(CONFIG_ITANIUM_BSTEP_SPECIFIC),y) - CFLAGS += -mb-step -endif - -HEAD := arch/$(ARCH)/kernel/head.o arch/$(ARCH)/kernel/init_task.o - -libs-y += arch/$(ARCH)/lib/ -core-y += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ -core-$(CONFIG_IA32_SUPPORT) += arch/$(ARCH)/ia32/ -core-$(CONFIG_IA64_DIG) += arch/$(ARCH)/dig/ -core-$(CONFIG_IA64_GENERIC) += arch/$(ARCH)/dig/ arch/$(ARCH)/hp/common/ arch/$(ARCH)/hp/zx1/ \ - arch/$(ARCH)/hp/sim/ -core-$(CONFIG_IA64_HP_ZX1) += arch/$(ARCH)/dig/ -core-$(CONFIG_IA64_SGI_SN) += arch/$(ARCH)/sn/kernel arch/$(ARCH)/sn/io \ - arch/$(ARCH)/sn/fakeprom -drivers-$(CONFIG_PCI) += arch/$(ARCH)/pci/ -drivers-$(CONFIG_IA64_HP_SIM) += arch/$(ARCH)/hp/sim/ -drivers-$(CONFIG_IA64_HP_ZX1) += arch/$(ARCH)/hp/common/ arch/$(ARCH)/hp/zx1/ - -ifdef CONFIG_IA64_SGI_SN - CFLAGS += -DBRINGUP - SUBDIRS += arch/$(ARCH)/sn/fakeprom -endif +cflags-$(CONFIG_ITANIUM_BSTEP_SPECIFIC) += -mb-step +cflags-$(CONFIG_IA64_SGI_SN) += -DBRINGUP -makeboot = $(call descend,arch/ia64/boot,$(1)) -maketool = $(call descend,arch/ia64/tools,$(1)) +CFLAGS += $(cflags-y) +HEAD := arch/ia64/kernel/head.o arch/ia64/kernel/init_task.o -.PHONY: compressed archclean archmrproper $(TOPDIR)/include/asm-ia64/offsets.h +libs-y += arch/ia64/lib/ +core-y += arch/ia64/kernel/ arch/ia64/mm/ +core-$(CONFIG_IA32_SUPPORT) += arch/ia64/ia32/ +core-$(CONFIG_IA64_DIG) += arch/ia64/dig/ +core-$(CONFIG_IA64_GENERIC) += arch/ia64/dig/ arch/ia64/hp/common/ arch/ia64/hp/zx1/ \ + arch/ia64/hp/sim/ +core-$(CONFIG_IA64_HP_ZX1) += arch/ia64/dig/ +core-$(CONFIG_IA64_SGI_SN) += arch/ia64/sn/kernel/ \ + arch/ia64/sn/io/ \ + arch/ia64/sn/kernel/sn2/ +drivers-$(CONFIG_PCI) += arch/ia64/pci/ +drivers-$(CONFIG_IA64_HP_SIM) += arch/ia64/hp/sim/ +drivers-$(CONFIG_IA64_HP_ZX1) += arch/ia64/hp/common/ arch/ia64/hp/zx1/ +drivers-$(CONFIG_IA64_SGI_SN) += arch/ia64/sn/fakeprom/ + +makeboot =$(Q)$(MAKE) -f scripts/Makefile.build obj=arch/ia64/boot $(1) +maketool =$(Q)$(MAKE) -f scripts/Makefile.build obj=arch/ia64/tools $(1) -all: compressed boot +.PHONY: boot compressed archclean archmrproper include/asm-ia64/offsets.h -boot: vmlinux - +@$(call makeboot,all) +all compressed: vmlinux.gz -compressed: vmlinux - $(OBJCOPY) $(OBJCOPYFLAGS) vmlinux vmlinux-tmp - gzip vmlinux-tmp - mv vmlinux-tmp.gz vmlinux.gz +vmlinux.gz: vmlinux + $(call makeboot,vmlinux.gz) +archmrproper: archclean: - $(MAKE) -rR -f scripts/Makefile.clean obj=arch/$(ARCH)/boot + $(Q)$(MAKE) -f scripts/Makefile.clean obj=arch/ia64/boot -archmrproper: +CLEAN_FILES += include/asm-ia64/offsets.h vmlinux.gz bootloader + +prepare: include/asm-ia64/offsets.h -prepare: $(TOPDIR)/include/asm-ia64/offsets.h +boot: lib/lib.a vmlinux + $(call makeboot,$@) -$(TOPDIR)/include/asm-ia64/offsets.h: include/asm include/linux/version.h \ - include/config/MARKER - +@$(call maketool,$@) +include/asm-ia64/offsets.h: include/asm include/linux/version.h include/config/MARKER + $(call maketool,$@) diff -Nru a/arch/ia64/boot/Makefile b/arch/ia64/boot/Makefile --- a/arch/ia64/boot/Makefile Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/boot/Makefile Wed Jan 15 16:57:29 2003 @@ -8,20 +8,33 @@ # Copyright (C) 1998 by David Mosberger-Tang # -LINKFLAGS = -static -T $(src)/bootloader.lds +EXTRA_TARGETS := vmlinux.bin vmlinux.gz -OBJS = $(obj)/bootloader.o +targets-$(CONFIG_IA64_HP_SIM) += bootloader +targets-$(CONFIG_IA64_GENERIC) += bootloader +EXTRA_TARGETS += $(sort $(targets-y)) -targets-$(CONFIG_IA64_HP_SIM) += bootloader -targets-$(CONFIG_IA64_GENERIC) += bootloader +quiet_cmd_cptotop = LN $@ + cmd_cptotop = ln -f $< $@ -CFLAGS := $(CFLAGS) $(CFLAGS_KERNEL) +vmlinux.gz: $(obj)/vmlinux.gz $(targets-y) + $(call cmd,cptotop) + @echo ' Kernel: $@ is ready' -all: $(targets-y) +boot: bootloader -bootloader: $(OBJS) - $(LD) $(LINKFLAGS) $(OBJS) $(TOPDIR)/lib/lib.a $(TOPDIR)/arch/$(ARCH)/lib/lib.a \ - -o bootloader +bootloader: $(obj)/bootloader + $(call cmd,cptotop) -clean: - rm -f $(TARGETS) +$(obj)/vmlinux.gz: $(obj)/vmlinux.bin FORCE + $(call if_changed,gzip) + +$(obj)/vmlinux.bin: vmlinux FORCE + $(call if_changed,objcopy) + + +LDFLAGS_bootloader = -static -T + +$(obj)/bootloader: $(src)/bootloader.lds $(obj)/bootloader.o \ + lib/lib.a arch/ia64/lib/lib.a FORCE + $(call if_changed,ld) diff -Nru a/arch/ia64/boot/bootloader.c b/arch/ia64/boot/bootloader.c --- a/arch/ia64/boot/bootloader.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/boot/bootloader.c Wed Jan 15 16:57:29 2003 @@ -3,12 +3,14 @@ * * Loads an ELF kernel. * - * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co - * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang - * Copyright (C) 1998, 1999 Stephane Eranian + * Copyright (C) 1998-2002 Hewlett-Packard Co + * David Mosberger-Tang + * Stephane Eranian * * 01/07/99 S.Eranian modified to pass command line arguments to kernel */ +struct task_struct; /* forward declaration for elf.h */ + #include #include #include @@ -53,6 +55,15 @@ #include "../kernel/fw-emu.c" +/* + * Set a break point on this function so that symbols are available to set breakpoints in + * the kernel being debugged. + */ +static void +debug_break (void) +{ +} + static void cons_write (const char *buf) { @@ -187,6 +198,7 @@ ssc(0, (long) kpath, 0, 0, SSC_LOAD_SYMBOLS); + debug_break(); asm volatile ("mov sp=%2; mov r28=%1; br.sptk.few %0" :: "b"(e_entry), "r"(bp), "r"(__pa(&stack))); diff -Nru a/arch/ia64/hp/sim/simscsi.c b/arch/ia64/hp/sim/simscsi.c --- a/arch/ia64/hp/sim/simscsi.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/hp/sim/simscsi.c Wed Jan 15 16:57:29 2003 @@ -23,7 +23,7 @@ #include "../drivers/scsi/hosts.h" #include "simscsi.h" -#define DEBUG_SIMSCSI 1 +#define DEBUG_SIMSCSI 0 /* Simulator system calls: */ @@ -377,6 +377,12 @@ return 0; } +int +simscsi_host_reset (Scsi_Cmnd *sc) +{ + printk ("simscsi_host_reset: not implemented\n"); + return 0; +} static Scsi_Host_Template driver_template = SIMSCSI; diff -Nru a/arch/ia64/hp/sim/simscsi.h b/arch/ia64/hp/sim/simscsi.h --- a/arch/ia64/hp/sim/simscsi.h Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/hp/sim/simscsi.h Wed Jan 15 16:57:28 2003 @@ -1,7 +1,7 @@ /* * Simulated SCSI driver. * - * Copyright (C) 1999 Hewlett-Packard Co + * Copyright (C) 1999, 2002 Hewlett-Packard Co * David Mosberger-Tang */ #ifndef SIMSCSI_H @@ -21,14 +21,17 @@ sector_t, int[]); #define SIMSCSI { \ + .name = "simscsi", \ .detect = simscsi_detect, \ .release = simscsi_release, \ .info = simscsi_info, \ .queuecommand = simscsi_queuecommand, \ + .eh_host_reset_handler = simscsi_host_reset, \ .bios_param = simscsi_biosparam, \ .can_queue = SIMSCSI_REQ_QUEUE_LEN, \ .this_id = -1, \ .sg_tablesize = SG_ALL, \ + .max_sectors = 1024, \ .cmd_per_lun = SIMSCSI_REQ_QUEUE_LEN, \ .present = 0, \ .unchecked_isa_dma = 0, \ diff -Nru a/arch/ia64/hp/zx1/hpzx1_misc.c b/arch/ia64/hp/zx1/hpzx1_misc.c --- a/arch/ia64/hp/zx1/hpzx1_misc.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/hp/zx1/hpzx1_misc.c Wed Jan 15 16:57:29 2003 @@ -180,7 +180,6 @@ list_add_tail(&dev->bus_list, &bus->devices); list_add_tail(&dev->global_list, &pci_devices); - strcpy(dev->dev.name, dev->name); strcpy(dev->dev.bus_id, dev->slot_name); ret = device_register(&dev->dev); if (ret < 0) @@ -335,7 +334,7 @@ extern void sba_init(void); -static void +static int hpzx1_init (void) { /* zx1 has a hardware I/O TLB which lets us DMA from any device to any address */ @@ -343,6 +342,7 @@ hpzx1_acpi_dev_init(); sba_init(); + return 0; } subsys_initcall(hpzx1_init); diff -Nru a/arch/ia64/ia32/Makefile b/arch/ia64/ia32/Makefile --- a/arch/ia64/ia32/Makefile Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/ia32/Makefile Wed Jan 15 16:57:29 2003 @@ -2,5 +2,5 @@ # Makefile for the ia32 kernel emulation subsystem. # -obj-y := ia32_entry.o sys_ia32.o ia32_ioctl.o ia32_signal.o ia32_support.o ia32_traps.o \ - binfmt_elf32.o ia32_ldt.o +obj-y := ia32_entry.o sys_ia32.o ia32_ioctl.o ia32_signal.o \ + ia32_support.o ia32_traps.o binfmt_elf32.o ia32_ldt.o diff -Nru a/arch/ia64/ia32/binfmt_elf32.c b/arch/ia64/ia32/binfmt_elf32.c --- a/arch/ia64/ia32/binfmt_elf32.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/ia32/binfmt_elf32.c Wed Jan 15 16:57:29 2003 @@ -162,9 +162,11 @@ { unsigned long stack_base; struct vm_area_struct *mpnt; + struct mm_struct *mm = current->mm; int i; stack_base = IA32_STACK_TOP - MAX_ARG_PAGES*PAGE_SIZE; + mm->arg_start = bprm->p + stack_base; bprm->p += stack_base; if (bprm->loader) @@ -174,6 +176,11 @@ mpnt = kmem_cache_alloc(vm_area_cachep, SLAB_KERNEL); if (!mpnt) return -ENOMEM; + + if (!vm_enough_memory((IA32_STACK_TOP - (PAGE_MASK & (unsigned long) bprm->p))>>PAGE_SHIFT)) { + kmem_cache_free(vm_area_cachep, mpnt); + return -ENOMEM; + } down_write(¤t->mm->mmap_sem); { diff -Nru a/arch/ia64/ia32/ia32_entry.S b/arch/ia64/ia32/ia32_entry.S --- a/arch/ia64/ia32/ia32_entry.S Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/ia32/ia32_entry.S Wed Jan 15 16:57:29 2003 @@ -196,7 +196,7 @@ data8 sys32_fork data8 sys_read data8 sys_write - data8 sys_open /* 5 */ + data8 sys32_open /* 5 */ data8 sys_close data8 sys32_waitpid data8 sys_creat @@ -221,7 +221,7 @@ data8 sys32_alarm data8 sys32_ni_syscall data8 sys32_pause - data8 sys32_utime /* 30 */ + data8 compat_sys_utime /* 30 */ data8 sys32_ni_syscall /* old stty syscall holder */ data8 sys32_ni_syscall /* old gtty syscall holder */ data8 sys_access @@ -234,7 +234,7 @@ data8 sys_rmdir /* 40 */ data8 sys_dup data8 sys32_pipe - data8 sys32_times + data8 compat_sys_times data8 sys32_ni_syscall /* old prof syscall holder */ data8 sys32_brk /* 45 */ data8 sys_setgid /* 16-bit version */ @@ -295,11 +295,11 @@ data8 sys32_ioperm data8 sys32_socketcall data8 sys_syslog - data8 sys32_setitimer - data8 sys32_getitimer /* 105 */ - data8 sys32_newstat - data8 sys32_newlstat - data8 sys32_newfstat + data8 compat_sys_setitimer + data8 compat_sys_getitimer /* 105 */ + data8 compat_sys_newstat + data8 compat_sys_newlstat + data8 compat_sys_newfstat data8 sys32_ni_syscall data8 sys32_iopl /* 110 */ data8 sys_vhangup @@ -353,7 +353,7 @@ data8 sys_sched_get_priority_max data8 sys_sched_get_priority_min /* 160 */ data8 sys32_sched_rr_get_interval - data8 sys32_nanosleep + data8 compat_sys_nanosleep data8 sys_mremap data8 sys_setresuid /* 16-bit version */ data8 sys32_getresuid16 /* 16-bit version */ /* 165 */ diff -Nru a/arch/ia64/ia32/ia32_signal.c b/arch/ia64/ia32/ia32_signal.c --- a/arch/ia64/ia32/ia32_signal.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/ia32/ia32_signal.c Wed Jan 15 16:57:28 2003 @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -165,10 +166,10 @@ * sw ar.fsr(0:15) * tag ar.fsr(16:31) with odd numbered bits not used * (read returns 0, writes ignored) - * ipoff ar.fir(0:31) RO - * cssel ar.fir(32:47) RO - * dataoff ar.fdr(0:31) RO - * datasel ar.fdr(32:47) RO + * ipoff ar.fir(0:31) + * cssel ar.fir(32:47) + * dataoff ar.fdr(0:31) + * datasel ar.fdr(32:47) * * _st[(0+TOS)%8] f8 * _st[(1+TOS)%8] f9 (f8, f9 from ptregs) @@ -328,7 +329,7 @@ unsigned long num64, mxcsr; struct _fpreg_ia32 *fpregp; char buf[32]; - unsigned long fsr, fcr; + unsigned long fsr, fcr, fir, fdr; int fp_tos, fr8_st_map; if (!access_ok(VERIFY_READ, save, sizeof(*save))) @@ -345,6 +346,8 @@ */ asm volatile ( "mov %0=ar.fsr;" : "=r"(fsr)); asm volatile ( "mov %0=ar.fcr;" : "=r"(fcr)); + asm volatile ( "mov %0=ar.fir;" : "=r"(fir)); + asm volatile ( "mov %0=ar.fdr;" : "=r"(fdr)); __get_user(mxcsr, (unsigned int *)&save->mxcsr); /* setting bits 0..5 8..12 with cw and 39..47 from mxcsr */ @@ -355,14 +358,34 @@ /* setting bits 0..31 with sw and tag and 32..37 from mxcsr */ __get_user(lo, (unsigned int *)&save->sw); + /* set bits 15,7 (fsw.b, fsw.es) to reflect the current error status */ + if ( !(lo & 0x7f) ) + lo &= (~0x8080); __get_user(hi, (unsigned int *)&save->tag); num64 = mxcsr & 0x3f; num64 = (num64 << 16) | (hi & 0xffff); num64 = (num64 << 16) | (lo & 0xffff); fsr = (fsr & (~0x3fffffffff)) | num64; + /* setting bits 0..47 with cssel and ipoff */ + __get_user(lo, (unsigned int *)&save->ipoff); + __get_user(hi, (unsigned int *)&save->cssel); + num64 = hi & 0xffff; + num64 = (num64 << 32) | lo; + fir = (fir & (~0xffffffffffff)) | num64; + + /* setting bits 0..47 with datasel and dataoff */ + __get_user(lo, (unsigned int *)&save->dataoff); + __get_user(hi, (unsigned int *)&save->datasel); + num64 = hi & 0xffff; + num64 = (num64 << 32) | lo; + fdr = (fdr & (~0xffffffffffff)) | num64; + asm volatile ( "mov ar.fsr=%0;" :: "r"(fsr)); asm volatile ( "mov ar.fcr=%0;" :: "r"(fcr)); + asm volatile ( "mov ar.fir=%0;" :: "r"(fir)); + asm volatile ( "mov ar.fdr=%0;" :: "r"(fdr)); + /* * restore f8, f9 onto pt_regs * restore f10..f15 onto live registers @@ -570,8 +593,8 @@ } asmlinkage long -sys32_rt_sigtimedwait (sigset32_t *uthese, siginfo_t32 *uinfo, struct timespec32 *uts, - unsigned int sigsetsize) +sys32_rt_sigtimedwait (sigset32_t *uthese, siginfo_t32 *uinfo, + struct compat_timespec *uts, unsigned int sigsetsize) { extern asmlinkage long sys_rt_sigtimedwait (const sigset_t *, siginfo_t *, const struct timespec *, size_t); diff -Nru a/arch/ia64/ia32/sys_ia32.c b/arch/ia64/ia32/sys_ia32.c --- a/arch/ia64/ia32/sys_ia32.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/ia32/sys_ia32.c Wed Jan 15 16:57:29 2003 @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -38,7 +37,6 @@ #include #include #include -#include #include #include #include @@ -49,6 +47,7 @@ #include #include #include +#include #include #include @@ -175,8 +174,7 @@ return r; } -static inline int -putstat (struct stat32 *ubuf, struct kstat *stat) +int cp_compat_stat(struct kstat *stat, struct compat_stat *ubuf) { int err; @@ -194,50 +192,17 @@ err |= __put_user(high2lowgid(stat->gid), &ubuf->st_gid); err |= __put_user(stat->rdev, &ubuf->st_rdev); err |= __put_user(stat->size, &ubuf->st_size); - err |= __put_user(stat->atime, &ubuf->st_atime); - err |= __put_user(stat->mtime, &ubuf->st_mtime); - err |= __put_user(stat->ctime, &ubuf->st_ctime); + err |= __put_user(stat->atime.tv_sec, &ubuf->st_atime); + err |= __put_user(stat->atime.tv_nsec, &ubuf->st_atime_nsec); + err |= __put_user(stat->mtime.tv_sec, &ubuf->st_mtime); + err |= __put_user(stat->mtime.tv_nsec, &ubuf->st_mtime_nsec); + err |= __put_user(stat->ctime.tv_sec, &ubuf->st_ctime); + err |= __put_user(stat->ctime.tv_nsec, &ubuf->st_ctime_nsec); err |= __put_user(stat->blksize, &ubuf->st_blksize); err |= __put_user(stat->blocks, &ubuf->st_blocks); return err; } -asmlinkage long -sys32_newstat (char *filename, struct stat32 *statbuf) -{ - struct kstat stat; - int ret = vfs_stat(filename, &stat); - - if (!ret) - ret = putstat(statbuf, &stat); - - return ret; -} - -asmlinkage long -sys32_newlstat (char *filename, struct stat32 *statbuf) -{ - struct kstat stat; - int ret = vfs_lstat(filename, &stat); - - if (!ret) - ret = putstat(statbuf, &stat); - - return ret; -} - -asmlinkage long -sys32_newfstat (unsigned int fd, struct stat32 *statbuf) -{ - struct kstat stat; - int ret = vfs_fstat(fd, &stat); - - if (!ret) - ret = putstat(statbuf, &stat); - - return ret; -} - #if PAGE_SHIFT > IA32_PAGE_SHIFT @@ -616,7 +581,8 @@ /* end address is 4KB aligned but not page aligned. */ retval = mprotect_subpage(PAGE_START(end), prot); if (retval < 0) - return retval; + goto out; + end = PAGE_START(end); } retval = sys_mprotect(start, end - start, prot); @@ -697,90 +663,20 @@ return ret; } -struct timeval32 -{ - int tv_sec, tv_usec; -}; - -struct itimerval32 -{ - struct timeval32 it_interval; - struct timeval32 it_value; -}; - static inline long -get_tv32 (struct timeval *o, struct timeval32 *i) +get_tv32 (struct timeval *o, struct compat_timeval *i) { return (!access_ok(VERIFY_READ, i, sizeof(*i)) || (__get_user(o->tv_sec, &i->tv_sec) | __get_user(o->tv_usec, &i->tv_usec))); } static inline long -put_tv32 (struct timeval32 *o, struct timeval *i) +put_tv32 (struct compat_timeval *o, struct timeval *i) { return (!access_ok(VERIFY_WRITE, o, sizeof(*o)) || (__put_user(i->tv_sec, &o->tv_sec) | __put_user(i->tv_usec, &o->tv_usec))); } -static inline long -get_it32 (struct itimerval *o, struct itimerval32 *i) -{ - return (!access_ok(VERIFY_READ, i, sizeof(*i)) || - (__get_user(o->it_interval.tv_sec, &i->it_interval.tv_sec) | - __get_user(o->it_interval.tv_usec, &i->it_interval.tv_usec) | - __get_user(o->it_value.tv_sec, &i->it_value.tv_sec) | - __get_user(o->it_value.tv_usec, &i->it_value.tv_usec))); -} - -static inline long -put_it32 (struct itimerval32 *o, struct itimerval *i) -{ - return (!access_ok(VERIFY_WRITE, o, sizeof(*o)) || - (__put_user(i->it_interval.tv_sec, &o->it_interval.tv_sec) | - __put_user(i->it_interval.tv_usec, &o->it_interval.tv_usec) | - __put_user(i->it_value.tv_sec, &o->it_value.tv_sec) | - __put_user(i->it_value.tv_usec, &o->it_value.tv_usec))); -} - -extern int do_getitimer (int which, struct itimerval *value); - -asmlinkage long -sys32_getitimer (int which, struct itimerval32 *it) -{ - struct itimerval kit; - int error; - - error = do_getitimer(which, &kit); - if (!error && put_it32(it, &kit)) - error = -EFAULT; - - return error; -} - -extern int do_setitimer (int which, struct itimerval *, struct itimerval *); - -asmlinkage long -sys32_setitimer (int which, struct itimerval32 *in, struct itimerval32 *out) -{ - struct itimerval kin, kout; - int error; - - if (in) { - if (get_it32(&kin, in)) - return -EFAULT; - } else - memset(&kin, 0, sizeof(kin)); - - error = do_setitimer(which, &kin, out ? &kout : NULL); - if (error || !out) - return error; - if (put_it32(out, &kout)) - return -EFAULT; - - return 0; - -} - asmlinkage unsigned long sys32_alarm (unsigned int seconds) { @@ -802,42 +698,11 @@ /* Translations due to time_t size differences. Which affects all sorts of things, like timeval and itimerval. */ -struct utimbuf_32 { - int atime; - int mtime; -}; - -extern asmlinkage long sys_utimes(char * filename, struct timeval * utimes); -extern asmlinkage long sys_gettimeofday (struct timeval *tv, struct timezone *tz); - -asmlinkage long -sys32_utime (char *filename, struct utimbuf_32 *times32) -{ - mm_segment_t old_fs = get_fs(); - struct timeval tv[2], *tvp; - long ret; - - if (times32) { - if (get_user(tv[0].tv_sec, ×32->atime)) - return -EFAULT; - tv[0].tv_usec = 0; - if (get_user(tv[1].tv_sec, ×32->mtime)) - return -EFAULT; - tv[1].tv_usec = 0; - set_fs(KERNEL_DS); - tvp = tv; - } else - tvp = NULL; - ret = sys_utimes(filename, tvp); - set_fs(old_fs); - return ret; -} - extern struct timezone sys_tz; extern int do_sys_settimeofday (struct timeval *tv, struct timezone *tz); asmlinkage long -sys32_gettimeofday (struct timeval32 *tv, struct timezone *tz) +sys32_gettimeofday (struct compat_timeval *tv, struct timezone *tz) { if (tv) { struct timeval ktv; @@ -853,7 +718,7 @@ } asmlinkage long -sys32_settimeofday (struct timeval32 *tv, struct timezone *tz) +sys32_settimeofday (struct compat_timeval *tv, struct timezone *tz) { struct timeval ktv; struct timezone ktz; @@ -1003,7 +868,7 @@ #define ROUND_UP_TIME(x,y) (((x)+(y)-1)/(y)) asmlinkage long -sys32_select (int n, fd_set *inp, fd_set *outp, fd_set *exp, struct timeval32 *tvp32) +sys32_select (int n, fd_set *inp, fd_set *outp, fd_set *exp, struct compat_timeval *tvp32) { fd_set_bits fds; char *bits; @@ -1110,28 +975,7 @@ if (copy_from_user(&a, arg, sizeof(a))) return -EFAULT; return sys32_select(a.n, (fd_set *) A(a.inp), (fd_set *) A(a.outp), (fd_set *) A(a.exp), - (struct timeval32 *) A(a.tvp)); -} - -extern asmlinkage long sys_nanosleep (struct timespec *rqtp, struct timespec *rmtp); - -asmlinkage long -sys32_nanosleep (struct timespec32 *rqtp, struct timespec32 *rmtp) -{ - struct timespec t; - int ret; - mm_segment_t old_fs = get_fs(); - - if (get_user (t.tv_sec, &rqtp->tv_sec) || get_user (t.tv_nsec, &rqtp->tv_nsec)) - return -EFAULT; - set_fs(KERNEL_DS); - ret = sys_nanosleep(&t, rmtp ? &t : NULL); - set_fs(old_fs); - if (rmtp && ret == -EINTR) { - if (put_user(t.tv_sec, &rmtp->tv_sec) || put_user(t.tv_nsec, &rmtp->tv_nsec)) - return -EFAULT; - } - return ret; + (struct compat_timeval *) A(a.tvp)); } struct iovec32 { unsigned int iov_base; int iov_len; }; @@ -1304,7 +1148,7 @@ }; struct cmsghdr32 { - __kernel_size_t32 cmsg_len; + compat_size_t cmsg_len; int cmsg_level; int cmsg_type; }; @@ -1369,7 +1213,7 @@ { struct cmsghdr *kcmsg, *kcmsg_base; __kernel_size_t kcmlen, tmp; - __kernel_size_t32 ucmlen; + compat_size_t ucmlen; struct cmsghdr32 *ucmsg; long err; @@ -1893,10 +1737,10 @@ extern asmlinkage long sys_getpeername(int fd, struct sockaddr *usockaddr, int *usockaddr_len); extern asmlinkage long sys_send(int fd, void *buff, size_t len, unsigned flags); -extern asmlinkage long sys_sendto(int fd, u32 buff, __kernel_size_t32 len, +extern asmlinkage long sys_sendto(int fd, u32 buff, compat_size_t len, unsigned flags, u32 addr, int addr_len); extern asmlinkage long sys_recv(int fd, void *ubuf, size_t size, unsigned flags); -extern asmlinkage long sys_recvfrom(int fd, u32 ubuf, __kernel_size_t32 size, +extern asmlinkage long sys_recvfrom(int fd, u32 ubuf, compat_size_t size, unsigned flags, u32 addr, u32 addr_len); extern asmlinkage long sys_setsockopt(int fd, int level, int optname, char *optval, int optlen); @@ -1994,11 +1838,11 @@ struct ipc_perm32 { key_t key; - __kernel_uid_t32 uid; - __kernel_gid_t32 gid; - __kernel_uid_t32 cuid; - __kernel_gid_t32 cgid; - __kernel_mode_t32 mode; + compat_uid_t uid; + compat_gid_t gid; + compat_uid_t cuid; + compat_gid_t cgid; + compat_mode_t mode; unsigned short seq; }; @@ -2008,7 +1852,7 @@ __kernel_gid32_t32 gid; __kernel_uid32_t32 cuid; __kernel_gid32_t32 cgid; - __kernel_mode_t32 mode; + compat_mode_t mode; unsigned short __pad1; unsigned short seq; unsigned short __pad2; @@ -2018,8 +1862,8 @@ struct semid_ds32 { struct ipc_perm32 sem_perm; /* permissions .. see ipc.h */ - __kernel_time_t32 sem_otime; /* last semop time */ - __kernel_time_t32 sem_ctime; /* last change time */ + compat_time_t sem_otime; /* last semop time */ + compat_time_t sem_ctime; /* last change time */ u32 sem_base; /* ptr to first semaphore in array */ u32 sem_pending; /* pending operations to be processed */ u32 sem_pending_last; /* last pending operation */ @@ -2029,9 +1873,9 @@ struct semid64_ds32 { struct ipc64_perm32 sem_perm; - __kernel_time_t32 sem_otime; + compat_time_t sem_otime; unsigned int __unused1; - __kernel_time_t32 sem_ctime; + compat_time_t sem_ctime; unsigned int __unused2; unsigned int sem_nsems; unsigned int __unused3; @@ -2042,9 +1886,9 @@ struct ipc_perm32 msg_perm; u32 msg_first; u32 msg_last; - __kernel_time_t32 msg_stime; - __kernel_time_t32 msg_rtime; - __kernel_time_t32 msg_ctime; + compat_time_t msg_stime; + compat_time_t msg_rtime; + compat_time_t msg_ctime; u32 wwait; u32 rwait; unsigned short msg_cbytes; @@ -2056,17 +1900,17 @@ struct msqid64_ds32 { struct ipc64_perm32 msg_perm; - __kernel_time_t32 msg_stime; + compat_time_t msg_stime; unsigned int __unused1; - __kernel_time_t32 msg_rtime; + compat_time_t msg_rtime; unsigned int __unused2; - __kernel_time_t32 msg_ctime; + compat_time_t msg_ctime; unsigned int __unused3; unsigned int msg_cbytes; unsigned int msg_qnum; unsigned int msg_qbytes; - __kernel_pid_t32 msg_lspid; - __kernel_pid_t32 msg_lrpid; + compat_pid_t msg_lspid; + compat_pid_t msg_lrpid; unsigned int __unused4; unsigned int __unused5; }; @@ -2074,9 +1918,9 @@ struct shmid_ds32 { struct ipc_perm32 shm_perm; int shm_segsz; - __kernel_time_t32 shm_atime; - __kernel_time_t32 shm_dtime; - __kernel_time_t32 shm_ctime; + compat_time_t shm_atime; + compat_time_t shm_dtime; + compat_time_t shm_ctime; __kernel_ipc_pid_t32 shm_cpid; __kernel_ipc_pid_t32 shm_lpid; unsigned short shm_nattch; @@ -2084,15 +1928,15 @@ struct shmid64_ds32 { struct ipc64_perm shm_perm; - __kernel_size_t32 shm_segsz; - __kernel_time_t32 shm_atime; + compat_size_t shm_segsz; + compat_time_t shm_atime; unsigned int __unused1; - __kernel_time_t32 shm_dtime; + compat_time_t shm_dtime; unsigned int __unused2; - __kernel_time_t32 shm_ctime; + compat_time_t shm_ctime; unsigned int __unused3; - __kernel_pid_t32 shm_cpid; - __kernel_pid_t32 shm_lpid; + compat_pid_t shm_cpid; + compat_pid_t shm_lpid; unsigned int shm_nattch; unsigned int __unused4; unsigned int __unused5; @@ -2166,6 +2010,10 @@ else fourth.__pad = (void *)A(pad); switch (third) { + default: + err = -EINVAL; + break; + case IPC_INFO: case IPC_RMID: case IPC_SET: @@ -2615,8 +2463,8 @@ } struct rusage32 { - struct timeval32 ru_utime; - struct timeval32 ru_stime; + struct compat_timeval ru_utime; + struct compat_timeval ru_stime; int ru_maxrss; int ru_ixrss; int ru_idrss; @@ -2708,37 +2556,6 @@ return ret; } -struct tms32 { - __kernel_clock_t32 tms_utime; - __kernel_clock_t32 tms_stime; - __kernel_clock_t32 tms_cutime; - __kernel_clock_t32 tms_cstime; -}; - -extern asmlinkage long sys_times (struct tms * tbuf); - -asmlinkage long -sys32_times (struct tms32 *tbuf) -{ - mm_segment_t old_fs = get_fs(); - struct tms t; - long ret; - int err; - - set_fs(KERNEL_DS); - ret = sys_times(tbuf ? &t : NULL); - set_fs(old_fs); - if (tbuf) { - err = put_user (IA32_TICK(t.tms_utime), &tbuf->tms_utime); - err |= put_user (IA32_TICK(t.tms_stime), &tbuf->tms_stime); - err |= put_user (IA32_TICK(t.tms_cutime), &tbuf->tms_cutime); - err |= put_user (IA32_TICK(t.tms_cstime), &tbuf->tms_cstime); - if (err) - ret = -EFAULT; - } - return IA32_TICK(ret); -} - static unsigned int ia32_peek (struct pt_regs *regs, struct task_struct *child, unsigned long addr, unsigned int *val) { @@ -2899,57 +2716,152 @@ } static int -save_ia32_fpstate (struct task_struct *tsk, struct _fpstate_ia32 *save) +save_ia32_fpstate (struct task_struct *tsk, struct ia32_user_i387_struct *save) { struct switch_stack *swp; struct pt_regs *ptp; int i, tos; if (!access_ok(VERIFY_WRITE, save, sizeof(*save))) - return -EIO; - __put_user(tsk->thread.fcr, &save->cw); - __put_user(tsk->thread.fsr, &save->sw); - __put_user(tsk->thread.fsr >> 32, &save->tag); - __put_user(tsk->thread.fir, &save->ipoff); - __put_user(__USER_CS, &save->cssel); - __put_user(tsk->thread.fdr, &save->dataoff); - __put_user(__USER_DS, &save->datasel); + return -EFAULT; + + __put_user(tsk->thread.fcr & 0xffff, &save->cwd); + __put_user(tsk->thread.fsr & 0xffff, &save->swd); + __put_user((tsk->thread.fsr>>16) & 0xffff, &save->twd); + __put_user(tsk->thread.fir, &save->fip); + __put_user((tsk->thread.fir>>32) & 0xffff, &save->fcs); + __put_user(tsk->thread.fdr, &save->foo); + __put_user((tsk->thread.fdr>>32) & 0xffff, &save->fos); + /* * Stack frames start with 16-bytes of temp space */ swp = (struct switch_stack *)(tsk->thread.ksp + 16); ptp = ia64_task_regs(tsk); - tos = (tsk->thread.fsr >> 11) & 3; + tos = (tsk->thread.fsr >> 11) & 7; for (i = 0; i < 8; i++) - put_fpreg(i, &save->_st[i], ptp, swp, tos); + put_fpreg(i, (struct _fpreg_ia32 *)&save->st_space[4*i], ptp, swp, tos); return 0; } static int -restore_ia32_fpstate (struct task_struct *tsk, struct _fpstate_ia32 *save) +restore_ia32_fpstate (struct task_struct *tsk, struct ia32_user_i387_struct *save) { struct switch_stack *swp; struct pt_regs *ptp; - int i, tos, ret; - int fsrlo, fsrhi; + int i, tos; + unsigned int fsrlo, fsrhi, num32; if (!access_ok(VERIFY_READ, save, sizeof(*save))) - return(-EIO); - ret = __get_user(tsk->thread.fcr, (unsigned int *)&save->cw); - ret |= __get_user(fsrlo, (unsigned int *)&save->sw); - ret |= __get_user(fsrhi, (unsigned int *)&save->tag); - tsk->thread.fsr = ((long)fsrhi << 32) | (long)fsrlo; - ret |= __get_user(tsk->thread.fir, (unsigned int *)&save->ipoff); - ret |= __get_user(tsk->thread.fdr, (unsigned int *)&save->dataoff); + return(-EFAULT); + + __get_user(num32, (unsigned int *)&save->cwd); + tsk->thread.fcr = (tsk->thread.fcr & (~0x1f3f)) | (num32 & 0x1f3f); + __get_user(fsrlo, (unsigned int *)&save->swd); + __get_user(fsrhi, (unsigned int *)&save->twd); + num32 = (fsrhi << 16) | fsrlo; + tsk->thread.fsr = (tsk->thread.fsr & (~0xffffffff)) | num32; + __get_user(num32, (unsigned int *)&save->fip); + tsk->thread.fir = (tsk->thread.fir & (~0xffffffff)) | num32; + __get_user(num32, (unsigned int *)&save->foo); + tsk->thread.fdr = (tsk->thread.fdr & (~0xffffffff)) | num32; + /* * Stack frames start with 16-bytes of temp space */ swp = (struct switch_stack *)(tsk->thread.ksp + 16); ptp = ia64_task_regs(tsk); - tos = (tsk->thread.fsr >> 11) & 3; + tos = (tsk->thread.fsr >> 11) & 7; for (i = 0; i < 8; i++) - get_fpreg(i, &save->_st[i], ptp, swp, tos); - return ret ? -EFAULT : 0; + get_fpreg(i, (struct _fpreg_ia32 *)&save->st_space[4*i], ptp, swp, tos); + return 0; +} + +static int +save_ia32_fpxstate (struct task_struct *tsk, struct ia32_user_fxsr_struct *save) +{ + struct switch_stack *swp; + struct pt_regs *ptp; + int i, tos; + unsigned long mxcsr=0; + unsigned long num128[2]; + + if (!access_ok(VERIFY_WRITE, save, sizeof(*save))) + return -EFAULT; + + __put_user(tsk->thread.fcr & 0xffff, &save->cwd); + __put_user(tsk->thread.fsr & 0xffff, &save->swd); + __put_user((tsk->thread.fsr>>16) & 0xffff, &save->twd); + __put_user(tsk->thread.fir, &save->fip); + __put_user((tsk->thread.fir>>32) & 0xffff, &save->fcs); + __put_user(tsk->thread.fdr, &save->foo); + __put_user((tsk->thread.fdr>>32) & 0xffff, &save->fos); + + /* + * Stack frames start with 16-bytes of temp space + */ + swp = (struct switch_stack *)(tsk->thread.ksp + 16); + ptp = ia64_task_regs(tsk); + tos = (tsk->thread.fsr >> 11) & 7; + for (i = 0; i < 8; i++) + put_fpreg(i, (struct _fpreg_ia32 *)&save->st_space[4*i], ptp, swp, tos); + + mxcsr = ((tsk->thread.fcr>>32) & 0xff80) | ((tsk->thread.fsr>>32) & 0x3f); + __put_user(mxcsr & 0xffff, &save->mxcsr); + for (i = 0; i < 8; i++) { + memcpy(&(num128[0]), &(swp->f16) + i*2, sizeof(unsigned long)); + memcpy(&(num128[1]), &(swp->f17) + i*2, sizeof(unsigned long)); + copy_to_user(&save->xmm_space[0] + 4*i, num128, sizeof(struct _xmmreg_ia32)); + } + return 0; +} + +static int +restore_ia32_fpxstate (struct task_struct *tsk, struct ia32_user_fxsr_struct *save) +{ + struct switch_stack *swp; + struct pt_regs *ptp; + int i, tos; + unsigned int fsrlo, fsrhi, num32; + int mxcsr; + unsigned long num64; + unsigned long num128[2]; + + if (!access_ok(VERIFY_READ, save, sizeof(*save))) + return(-EFAULT); + + __get_user(num32, (unsigned int *)&save->cwd); + tsk->thread.fcr = (tsk->thread.fcr & (~0x1f3f)) | (num32 & 0x1f3f); + __get_user(fsrlo, (unsigned int *)&save->swd); + __get_user(fsrhi, (unsigned int *)&save->twd); + num32 = (fsrhi << 16) | fsrlo; + tsk->thread.fsr = (tsk->thread.fsr & (~0xffffffff)) | num32; + __get_user(num32, (unsigned int *)&save->fip); + tsk->thread.fir = (tsk->thread.fir & (~0xffffffff)) | num32; + __get_user(num32, (unsigned int *)&save->foo); + tsk->thread.fdr = (tsk->thread.fdr & (~0xffffffff)) | num32; + + /* + * Stack frames start with 16-bytes of temp space + */ + swp = (struct switch_stack *)(tsk->thread.ksp + 16); + ptp = ia64_task_regs(tsk); + tos = (tsk->thread.fsr >> 11) & 7; + for (i = 0; i < 8; i++) + get_fpreg(i, (struct _fpreg_ia32 *)&save->st_space[4*i], ptp, swp, tos); + + __get_user(mxcsr, (unsigned int *)&save->mxcsr); + num64 = mxcsr & 0xff10; + tsk->thread.fcr = (tsk->thread.fcr & (~0xff1000000000)) | (num64<<32); + num64 = mxcsr & 0x3f; + tsk->thread.fsr = (tsk->thread.fsr & (~0x3f00000000)) | (num64<<32); + + for (i = 0; i < 8; i++) { + copy_from_user(num128, &save->xmm_space[0] + 4*i, sizeof(struct _xmmreg_ia32)); + memcpy(&(swp->f16) + i*2, &(num128[0]), sizeof(unsigned long)); + memcpy(&(swp->f17) + i*2, &(num128[1]), sizeof(unsigned long)); + } + return 0; } extern asmlinkage long sys_ptrace (long, pid_t, unsigned long, unsigned long, long, long, long, @@ -3061,11 +2973,19 @@ break; case IA32_PTRACE_GETFPREGS: - ret = save_ia32_fpstate(child, (struct _fpstate_ia32 *) A(data)); + ret = save_ia32_fpstate(child, (struct ia32_user_i387_struct *) A(data)); + break; + + case IA32_PTRACE_GETFPXREGS: + ret = save_ia32_fpxstate(child, (struct ia32_user_fxsr_struct *) A(data)); break; case IA32_PTRACE_SETFPREGS: - ret = restore_ia32_fpstate(child, (struct _fpstate_ia32 *) A(data)); + ret = restore_ia32_fpstate(child, (struct ia32_user_i387_struct *) A(data)); + break; + + case IA32_PTRACE_SETFPXREGS: + ret = restore_ia32_fpxstate(child, (struct ia32_user_fxsr_struct *) A(data)); break; case PTRACE_SYSCALL: /* continue, stop after next syscall */ @@ -3535,9 +3455,12 @@ err |= __put_user(kbuf->rdev, &ubuf->st_rdev); err |= __put_user(kbuf->size, &ubuf->st_size_lo); err |= __put_user((kbuf->size >> 32), &ubuf->st_size_hi); - err |= __put_user(kbuf->atime, &ubuf->st_atime); - err |= __put_user(kbuf->mtime, &ubuf->st_mtime); - err |= __put_user(kbuf->ctime, &ubuf->st_ctime); + err |= __put_user(kbuf->atime.tv_sec, &ubuf->st_atime); + err |= __put_user(kbuf->atime.tv_nsec, &ubuf->st_atime_nsec); + err |= __put_user(kbuf->mtime.tv_sec, &ubuf->st_mtime); + err |= __put_user(kbuf->mtime.tv_nsec, &ubuf->st_mtime_nsec); + err |= __put_user(kbuf->ctime.tv_sec, &ubuf->st_ctime); + err |= __put_user(kbuf->ctime.tv_nsec, &ubuf->st_ctime_nsec); err |= __put_user(kbuf->blksize, &ubuf->st_blksize); err |= __put_user(kbuf->blocks, &ubuf->st_blocks); return err; @@ -3624,7 +3547,7 @@ } asmlinkage long -sys32_sched_rr_get_interval (pid_t pid, struct timespec32 *interval) +sys32_sched_rr_get_interval (pid_t pid, struct compat_timespec *interval) { extern asmlinkage long sys_sched_rr_get_interval (pid_t, struct timespec *); mm_segment_t old_fs = get_fs(); @@ -3701,21 +3624,52 @@ return ret; } +/* + * Exactly like fs/open.c:sys_open(), except that it doesn't set the O_LARGEFILE flag. + */ +asmlinkage long +sys32_open (const char * filename, int flags, int mode) +{ + char * tmp; + int fd, error; + + tmp = getname(filename); + fd = PTR_ERR(tmp); + if (!IS_ERR(tmp)) { + fd = get_unused_fd(); + if (fd >= 0) { + struct file *f = filp_open(tmp, flags, mode); + error = PTR_ERR(f); + if (IS_ERR(f)) + goto out_error; + fd_install(fd, f); + } +out: + putname(tmp); + } + return fd; + +out_error: + put_unused_fd(fd); + fd = error; + goto out; +} + #ifdef NOTYET /* UNTESTED FOR IA64 FROM HERE DOWN */ struct ncp_mount_data32 { int version; unsigned int ncp_fd; - __kernel_uid_t32 mounted_uid; + compat_uid_t mounted_uid; int wdog_pid; unsigned char mounted_vol[NCP_VOLNAME_LEN + 1]; unsigned int time_out; unsigned int retry_count; unsigned int flags; - __kernel_uid_t32 uid; - __kernel_gid_t32 gid; - __kernel_mode_t32 file_mode; - __kernel_mode_t32 dir_mode; + compat_uid_t uid; + compat_gid_t gid; + compat_mode_t file_mode; + compat_mode_t dir_mode; }; static void * @@ -3737,11 +3691,11 @@ struct smb_mount_data32 { int version; - __kernel_uid_t32 mounted_uid; - __kernel_uid_t32 uid; - __kernel_gid_t32 gid; - __kernel_mode_t32 file_mode; - __kernel_mode_t32 dir_mode; + compat_uid_t mounted_uid; + compat_uid_t uid; + compat_gid_t gid; + compat_mode_t file_mode; + compat_mode_t dir_mode; }; static void * @@ -3859,52 +3813,52 @@ extern asmlinkage long sys_setreuid(uid_t ruid, uid_t euid); -asmlinkage long sys32_setreuid(__kernel_uid_t32 ruid, __kernel_uid_t32 euid) +asmlinkage long sys32_setreuid(compat_uid_t ruid, compat_uid_t euid) { uid_t sruid, seuid; - sruid = (ruid == (__kernel_uid_t32)-1) ? ((uid_t)-1) : ((uid_t)ruid); - seuid = (euid == (__kernel_uid_t32)-1) ? ((uid_t)-1) : ((uid_t)euid); + sruid = (ruid == (compat_uid_t)-1) ? ((uid_t)-1) : ((uid_t)ruid); + seuid = (euid == (compat_uid_t)-1) ? ((uid_t)-1) : ((uid_t)euid); return sys_setreuid(sruid, seuid); } extern asmlinkage long sys_setresuid(uid_t ruid, uid_t euid, uid_t suid); asmlinkage long -sys32_setresuid(__kernel_uid_t32 ruid, __kernel_uid_t32 euid, - __kernel_uid_t32 suid) +sys32_setresuid(compat_uid_t ruid, compat_uid_t euid, + compat_uid_t suid) { uid_t sruid, seuid, ssuid; - sruid = (ruid == (__kernel_uid_t32)-1) ? ((uid_t)-1) : ((uid_t)ruid); - seuid = (euid == (__kernel_uid_t32)-1) ? ((uid_t)-1) : ((uid_t)euid); - ssuid = (suid == (__kernel_uid_t32)-1) ? ((uid_t)-1) : ((uid_t)suid); + sruid = (ruid == (compat_uid_t)-1) ? ((uid_t)-1) : ((uid_t)ruid); + seuid = (euid == (compat_uid_t)-1) ? ((uid_t)-1) : ((uid_t)euid); + ssuid = (suid == (compat_uid_t)-1) ? ((uid_t)-1) : ((uid_t)suid); return sys_setresuid(sruid, seuid, ssuid); } extern asmlinkage long sys_setregid(gid_t rgid, gid_t egid); asmlinkage long -sys32_setregid(__kernel_gid_t32 rgid, __kernel_gid_t32 egid) +sys32_setregid(compat_gid_t rgid, compat_gid_t egid) { gid_t srgid, segid; - srgid = (rgid == (__kernel_gid_t32)-1) ? ((gid_t)-1) : ((gid_t)rgid); - segid = (egid == (__kernel_gid_t32)-1) ? ((gid_t)-1) : ((gid_t)egid); + srgid = (rgid == (compat_gid_t)-1) ? ((gid_t)-1) : ((gid_t)rgid); + segid = (egid == (compat_gid_t)-1) ? ((gid_t)-1) : ((gid_t)egid); return sys_setregid(srgid, segid); } extern asmlinkage long sys_setresgid(gid_t rgid, gid_t egid, gid_t sgid); asmlinkage long -sys32_setresgid(__kernel_gid_t32 rgid, __kernel_gid_t32 egid, - __kernel_gid_t32 sgid) +sys32_setresgid(compat_gid_t rgid, compat_gid_t egid, + compat_gid_t sgid) { gid_t srgid, segid, ssgid; - srgid = (rgid == (__kernel_gid_t32)-1) ? ((gid_t)-1) : ((gid_t)rgid); - segid = (egid == (__kernel_gid_t32)-1) ? ((gid_t)-1) : ((gid_t)egid); - ssgid = (sgid == (__kernel_gid_t32)-1) ? ((gid_t)-1) : ((gid_t)sgid); + srgid = (rgid == (compat_gid_t)-1) ? ((gid_t)-1) : ((gid_t)rgid); + segid = (egid == (compat_gid_t)-1) ? ((gid_t)-1) : ((gid_t)egid); + ssgid = (sgid == (compat_gid_t)-1) ? ((gid_t)-1) : ((gid_t)sgid); return sys_setresgid(srgid, segid, ssgid); } @@ -3926,27 +3880,27 @@ struct nfsctl_export32 { s8 ex32_client[NFSCLNT_IDMAX+1]; s8 ex32_path[NFS_MAXPATHLEN+1]; - __kernel_dev_t32 ex32_dev; - __kernel_ino_t32 ex32_ino; + compat_dev_t ex32_dev; + compat_ino_t ex32_ino; s32 ex32_flags; - __kernel_uid_t32 ex32_anon_uid; - __kernel_gid_t32 ex32_anon_gid; + compat_uid_t ex32_anon_uid; + compat_gid_t ex32_anon_gid; }; struct nfsctl_uidmap32 { u32 ug32_ident; /* char * */ - __kernel_uid_t32 ug32_uidbase; + compat_uid_t ug32_uidbase; s32 ug32_uidlen; u32 ug32_udimap; /* uid_t * */ - __kernel_uid_t32 ug32_gidbase; + compat_uid_t ug32_gidbase; s32 ug32_gidlen; u32 ug32_gdimap; /* gid_t * */ }; struct nfsctl_fhparm32 { struct sockaddr gf32_addr; - __kernel_dev_t32 gf32_dev; - __kernel_ino_t32 gf32_ino; + compat_dev_t gf32_dev; + compat_ino_t gf32_ino; s32 gf32_version; }; @@ -4066,7 +4020,7 @@ return -ENOMEM; for(i = 0; i < karg->ca_umap.ug_uidlen; i++) err |= __get_user(karg->ca_umap.ug_udimap[i], - &(((__kernel_uid_t32 *)A(uaddr))[i])); + &(((compat_uid_t *)A(uaddr))[i])); err |= __get_user(karg->ca_umap.ug_gidbase, &arg32->ca32_umap.ug32_gidbase); err |= __get_user(karg->ca_umap.ug_uidlen, @@ -4081,7 +4035,7 @@ return -ENOMEM; for(i = 0; i < karg->ca_umap.ug_gidlen; i++) err |= __get_user(karg->ca_umap.ug_gdimap[i], - &(((__kernel_gid_t32 *)A(uaddr))[i])); + &(((compat_gid_t *)A(uaddr))[i])); return err; } @@ -4193,7 +4147,7 @@ u32 modes; s32 offset, freq, maxerror, esterror; s32 status, constant, precision, tolerance; - struct timeval32 time; + struct compat_timeval time; s32 tick; s32 ppsfreq, jitter, shift, stabil; s32 jitcnt, calcnt, errcnt, stbcnt; diff -Nru a/arch/ia64/kernel/Makefile b/arch/ia64/kernel/Makefile --- a/arch/ia64/kernel/Makefile Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/Makefile Wed Jan 15 16:57:29 2003 @@ -6,9 +6,13 @@ export-objs := ia64_ksyms.o -obj-y := acpi.o entry.o gate.o efi.o efi_stub.o ia64_ksyms.o irq.o irq_ia64.o irq_lsapic.o ivt.o \ - machvec.o pal.o process.o perfmon.o ptrace.o sal.o semaphore.o setup.o \ +obj-y := acpi.o entry.o gate.o efi.o efi_stub.o ia64_ksyms.o \ + irq.o irq_ia64.o irq_lsapic.o ivt.o \ + machvec.o pal.o process.o perfmon.o ptrace.o sal.o \ + semaphore.o setup.o \ signal.o sys_ia64.o traps.o time.o unaligned.o unwind.o + +obj-$(CONFIG_FSYS) += fsys.o obj-$(CONFIG_IOSAPIC) += iosapic.o obj-$(CONFIG_IA64_PALINFO) += palinfo.o obj-$(CONFIG_EFI_VARS) += efivars.o diff -Nru a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c --- a/arch/ia64/kernel/acpi.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/acpi.c Wed Jan 15 16:57:29 2003 @@ -888,4 +888,26 @@ return gsi_to_vector(irq); } +int __init +acpi_register_irq (u32 gsi, u32 polarity, u32 trigger) +{ + int vector = 0; + u32 irq_base; + char *iosapic_address; + + if (acpi_madt->flags.pcat_compat && (gsi < 16)) + return isa_irq_to_vector(gsi); + + if (!iosapic_register_intr) + return 0; + + /* Find the IOSAPIC */ + if (!acpi_find_iosapic(gsi, &irq_base, &iosapic_address)) { + /* Turn it on */ + vector = iosapic_register_intr (gsi, polarity, trigger, + irq_base, iosapic_address); + } + return vector; +} + #endif /* CONFIG_ACPI_BOOT */ diff -Nru a/arch/ia64/kernel/efi.c b/arch/ia64/kernel/efi.c --- a/arch/ia64/kernel/efi.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/kernel/efi.c Wed Jan 15 16:57:28 2003 @@ -306,7 +306,7 @@ u64 start; u64 end; } prev, curr; - void *efi_map_start, *efi_map_end, *p, *q; + void *efi_map_start, *efi_map_end, *p, *q, *r; efi_memory_desc_t *md, *check_md; u64 efi_desc_size, start, end, granule_addr, first_non_wb_addr = 0; @@ -351,11 +351,10 @@ if (!(first_non_wb_addr > granule_addr)) continue; /* couldn't find enough contiguous memory */ - } - - /* BUG_ON((md->phys_addr >> IA64_GRANULE_SHIFT) < first_non_wb_addr); */ - trim_top(md, first_non_wb_addr); + for (r = p; r < q; r += efi_desc_size) + trim_top(r, first_non_wb_addr); + } if (is_available_memory(md)) { if (md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT) > mem_limit) { diff -Nru a/arch/ia64/kernel/efivars.c b/arch/ia64/kernel/efivars.c --- a/arch/ia64/kernel/efivars.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/efivars.c Wed Jan 15 16:57:29 2003 @@ -29,6 +29,9 @@ * * Changelog: * + * 10 Dec 2002 - Matt Domsch + * fix locking per Peter Chubb's findings + * * 25 Mar 2002 - Matt Domsch * move uuid_unparse() to include/asm-ia64/efi.h:efi_guid_unparse() * @@ -73,7 +76,7 @@ MODULE_DESCRIPTION("/proc interface to EFI Variables"); MODULE_LICENSE("GPL"); -#define EFIVARS_VERSION "0.05 2002-Mar-26" +#define EFIVARS_VERSION "0.06 2002-Dec-10" static int efivar_read(char *page, char **start, off_t off, @@ -106,6 +109,14 @@ struct list_head list; } efivar_entry_t; +/* + efivars_lock protects two things: + 1) efivar_list - adds, removals, reads, writes + 2) efi.[gs]et_variable() calls. + It must not be held when creating proc entries or calling kmalloc. + efi.get_next_variable() is only called from efivars_init(), + which is protected by the BKL, so that path is safe. +*/ static spinlock_t efivars_lock = SPIN_LOCK_UNLOCKED; static LIST_HEAD(efivar_list); static struct proc_dir_entry *efi_vars_dir = NULL; @@ -150,6 +161,7 @@ * variable_name_size = number of bytes required to hold * variable_name (not counting the NULL * character at the end. + * efivars_lock is not held on entry or exit. * Returns 1 on failure, 0 on success */ static int @@ -160,10 +172,12 @@ int i, short_name_size = variable_name_size / sizeof(efi_char16_t) + 38; - char *short_name = kmalloc(short_name_size+1, - GFP_KERNEL); - efivar_entry_t *new_efivar = kmalloc(sizeof(efivar_entry_t), - GFP_KERNEL); + char *short_name; + efivar_entry_t *new_efivar; + + short_name = kmalloc(short_name_size+1, GFP_KERNEL); + new_efivar = kmalloc(sizeof(efivar_entry_t), GFP_KERNEL); + if (!short_name || !new_efivar) { if (short_name) kfree(short_name); if (new_efivar) kfree(new_efivar); @@ -188,20 +202,19 @@ *(short_name + strlen(short_name)) = '-'; efi_guid_unparse(vendor_guid, short_name + strlen(short_name)); - /* Create the entry in proc */ new_efivar->entry = create_proc_entry(short_name, 0600, efi_vars_dir); kfree(short_name); short_name = NULL; if (!new_efivar->entry) return 1; - new_efivar->entry->owner = THIS_MODULE; new_efivar->entry->data = new_efivar; new_efivar->entry->read_proc = efivar_read; new_efivar->entry->write_proc = efivar_write; - list_add(&new_efivar->list, &efivar_list); - + spin_lock(&efivars_lock); + list_add(&new_efivar->list, &efivar_list); + spin_unlock(&efivars_lock); return 0; } @@ -319,6 +332,8 @@ kfree(efivar); } + spin_unlock(&efivars_lock); + /* If this is a new variable, set up the proc entry for it. */ if (!found) { efivar_create_proc_entry(utf8_strsize(var_data->VariableName, @@ -328,7 +343,6 @@ } kfree(var_data); - spin_unlock(&efivars_lock); return size; } @@ -343,8 +357,6 @@ efi_char16_t *variable_name = kmalloc(1024, GFP_KERNEL); unsigned long variable_name_size = 1024; - spin_lock(&efivars_lock); - printk(KERN_INFO "EFI Variables Facility v%s\n", EFIVARS_VERSION); /* Since efi.c happens before procfs is available, @@ -357,8 +369,6 @@ efi_vars_dir = proc_mkdir("vars", efi_dir); - - /* Per EFI spec, the maximum storage allocated for both the variable name and variable data is 1024 bytes. */ @@ -390,7 +400,6 @@ } while (status != EFI_NOT_FOUND); kfree(variable_name); - spin_unlock(&efivars_lock); return 0; } @@ -400,17 +409,16 @@ struct list_head *pos, *n; efivar_entry_t *efivar; - spin_lock(&efivars_lock); - + spin_lock(&efivars_lock); list_for_each_safe(pos, n, &efivar_list) { efivar = efivar_entry(pos); remove_proc_entry(efivar->entry->name, efi_vars_dir); list_del(&efivar->list); kfree(efivar); } - remove_proc_entry(efi_vars_dir->name, efi_dir); spin_unlock(&efivars_lock); + remove_proc_entry(efi_vars_dir->name, efi_dir); } module_init(efivars_init); diff -Nru a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S --- a/arch/ia64/kernel/entry.S Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/kernel/entry.S Wed Jan 15 16:57:28 2003 @@ -3,7 +3,7 @@ * * Kernel entry points. * - * Copyright (C) 1998-2002 Hewlett-Packard Co + * Copyright (C) 1998-2003 Hewlett-Packard Co * David Mosberger-Tang * Copyright (C) 1999 VA Linux Systems * Copyright (C) 1999 Walt Drummond @@ -22,8 +22,8 @@ /* * Global (preserved) predicate usage on syscall entry/exit path: * - * pKern: See entry.h. - * pUser: See entry.h. + * pKStk: See entry.h. + * pUStk: See entry.h. * pSys: See entry.h. * pNonSys: !pSys */ @@ -63,7 +63,7 @@ sxt4 r8=r8 // return 64-bit result ;; stf.spill [sp]=f0 -(p6) cmp.ne pKern,pUser=r0,r0 // a successful execve() lands us in user-mode... +(p6) cmp.ne pKStk,pUStk=r0,r0 // a successful execve() lands us in user-mode... mov rp=loc0 (p6) mov ar.pfs=r0 // clear ar.pfs on success (p7) br.ret.sptk.many rp @@ -91,11 +91,12 @@ END(ia64_execve) /* - * sys_clone2(u64 flags, u64 ustack_base, u64 ustack_size, u64 user_tid, u64 tls) + * sys_clone2(u64 flags, u64 ustack_base, u64 ustack_size, u64 child_tidptr, u64 parent_tidptr, + * u64 tls) */ GLOBAL_ENTRY(sys_clone2) .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2) - alloc r16=ar.pfs,5,2,5,0 + alloc r16=ar.pfs,6,2,6,0 DO_SAVE_SWITCH_STACK adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp mov loc0=rp @@ -104,9 +105,10 @@ mov out1=in1 mov out3=in2 tbit.nz p6,p0=in0,CLONE_SETTLS_BIT - mov out4=in3 // valid only w/CLONE_SETTID and/or CLONE_CLEARTID + mov out4=in3 // child_tidptr: valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID ;; -(p6) st8 [r2]=in4 // store TLS in r13 (tp) +(p6) st8 [r2]=in5 // store TLS in r16 for copy_thread() + mov out5=in4 // parent_tidptr: valid only w/CLONE_PARENT_SETTID adds out2=IA64_SWITCH_STACK_SIZE+16,sp // out2 = ®s dep out0=0,in0,CLONE_IDLETASK_BIT,1 // out0 = clone_flags & ~CLONE_IDLETASK br.call.sptk.many rp=do_fork @@ -191,7 +193,7 @@ ;; (p6) srlz.d ld8 sp=[r21] // load kernel stack pointer of new task - mov IA64_KR(CURRENT)=r20 // update "current" application register + mov IA64_KR(CURRENT)=in0 // update "current" application register mov r8=r13 // return pointer to previously running task mov r13=in0 // set "current" pointer ;; @@ -535,7 +537,6 @@ GLOBAL_ENTRY(ia64_ret_from_clone) PT_REGS_UNWIND_INFO(0) -#if defined(CONFIG_SMP) || defined(CONFIG_PREEMPT) /* * We need to call schedule_tail() to complete the scheduling process. * Called by ia64_switch_to() after do_fork()->copy_thread(). r8 contains the @@ -543,7 +544,6 @@ */ br.call.sptk.many rp=ia64_invoke_schedule_tail .ret8: -#endif adds r2=TI_FLAGS+IA64_TASK_SIZE,r13 ;; ld4 r2=[r2] @@ -569,11 +569,12 @@ // fall through GLOBAL_ENTRY(ia64_leave_kernel) PT_REGS_UNWIND_INFO(0) - // work.need_resched etc. mustn't get changed by this CPU before it returns to userspace: -(pUser) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUser -(pUser) rsm psr.i + // work.need_resched etc. mustn't get changed by this CPU before it returns to + // user- or fsys-mode: +(pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk +(pUStk) rsm psr.i ;; -(pUser) adds r17=TI_FLAGS+IA64_TASK_SIZE,r13 +(pUStk) adds r17=TI_FLAGS+IA64_TASK_SIZE,r13 ;; .work_processed: (p6) ld4 r18=[r17] // load current_thread_info()->flags @@ -635,9 +636,9 @@ ;; srlz.i // ensure interruption collection is off mov b7=r15 + bsw.0 // switch back to bank 0 (no stop bit required beforehand...) ;; - bsw.0 // switch back to bank 0 - ;; +(pUStk) mov r18=IA64_KR(CURRENT) // Itanium 2: 12 cycle read latency adds r16=16,r12 adds r17=24,r12 ;; @@ -665,16 +666,21 @@ ;; ld8.fill r12=[r16],16 ld8.fill r13=[r17],16 +(pUStk) adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18 ;; ld8.fill r14=[r16] ld8.fill r15=[r17] +(pUStk) mov r17=1 + ;; +(pUStk) st1 [r18]=r17 // restore current->thread.on_ustack shr.u r18=r19,16 // get byte size of existing "dirty" partition ;; mov r16=ar.bsp // get existing backing store pointer movl r17=THIS_CPU(ia64_phys_stacked_size_p8) ;; ld4 r17=[r17] // r17 = cpu_data->phys_stacked_size_p8 -(pKern) br.cond.dpnt skip_rbs_switch +(pKStk) br.cond.dpnt skip_rbs_switch + /* * Restore user backing store. * @@ -788,12 +794,12 @@ skip_rbs_switch: mov b6=rB6 mov ar.pfs=rARPFS -(pUser) mov ar.bspstore=rARBSPSTORE +(pUStk) mov ar.bspstore=rARBSPSTORE (p9) mov cr.ifs=rCRIFS mov cr.ipsr=rCRIPSR mov cr.iip=rCRIIP ;; -(pUser) mov ar.rnat=rARRNAT // must happen with RSE in lazy mode +(pUStk) mov ar.rnat=rARRNAT // must happen with RSE in lazy mode mov ar.rsc=rARRSC mov ar.unat=rARUNAT mov pr=rARPR,-1 @@ -844,7 +850,6 @@ br.cond.sptk ia64_leave_kernel END(handle_syscall_error) -#ifdef CONFIG_SMP /* * Invoke schedule_tail(task) while preserving in0-in7, which may be needed * in case a system call gets restarted. @@ -861,8 +866,6 @@ br.ret.sptk.many rp END(ia64_invoke_schedule_tail) -#endif /* CONFIG_SMP */ - #if __GNUC__ < 3 /* @@ -1129,18 +1132,18 @@ data8 ia64_ni_syscall /* was: ia64_oldfstat */ data8 sys_vhangup data8 sys_lchown - data8 sys_vm86 // 1125 + data8 sys_remap_file_pages // 1125 data8 sys_wait4 data8 sys_sysinfo data8 sys_clone data8 sys_setdomainname data8 sys_newuname // 1130 data8 sys_adjtimex - data8 ia64_create_module + data8 ia64_ni_syscall /* was: ia64_create_module */ data8 sys_init_module data8 sys_delete_module - data8 sys_get_kernel_syms // 1135 - data8 sys_query_module + data8 ia64_ni_syscall // 1135 /* was: sys_get_kernel_syms */ + data8 ia64_ni_syscall /* was: sys_query_module */ data8 sys_quotactl data8 sys_bdflush data8 sys_sysfs @@ -1160,7 +1163,7 @@ data8 sys_mlock data8 sys_mlockall data8 sys_mprotect // 1155 - data8 sys_mremap + data8 ia64_mremap data8 sys_msync data8 sys_munlock data8 sys_munlockall @@ -1173,11 +1176,7 @@ data8 sys_sched_get_priority_min data8 sys_sched_rr_get_interval data8 sys_nanosleep -#if defined(CONFIG_NFSD) || defined(CONFIG_NFSD_MODULE) data8 sys_nfsservctl -#else - data8 sys_ni_syscall -#endif data8 sys_prctl // 1170 data8 sys_getpagesize data8 sys_mmap2 @@ -1241,7 +1240,7 @@ data8 sys_futex // 1230 data8 sys_sched_setaffinity data8 sys_sched_getaffinity - data8 sys_ni_syscall + data8 sys_set_tid_address data8 sys_alloc_hugepages data8 sys_free_hugepages // 1235 data8 sys_exit_group @@ -1254,8 +1253,8 @@ data8 sys_epoll_create data8 sys_epoll_ctl data8 sys_epoll_wait // 1245 + data8 sys_restart_syscall data8 sys_semtimedop - data8 ia64_ni_syscall data8 ia64_ni_syscall data8 ia64_ni_syscall data8 ia64_ni_syscall // 1250 diff -Nru a/arch/ia64/kernel/entry.h b/arch/ia64/kernel/entry.h --- a/arch/ia64/kernel/entry.h Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/entry.h Wed Jan 15 16:57:29 2003 @@ -4,8 +4,8 @@ * Preserved registers that are shared between code in ivt.S and entry.S. Be * careful not to step on these! */ -#define pKern p2 /* will leave_kernel return to kernel-mode? */ -#define pUser p3 /* will leave_kernel return to user-mode? */ +#define pKStk p2 /* will leave_kernel return to kernel-stacks? */ +#define pUStk p3 /* will leave_kernel return to user-stacks? */ #define pSys p4 /* are we processing a (synchronous) system call? */ #define pNonSys p5 /* complement of pSys */ diff -Nru a/arch/ia64/kernel/fsys.S b/arch/ia64/kernel/fsys.S --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/ia64/kernel/fsys.S Wed Jan 15 16:57:29 2003 @@ -0,0 +1,293 @@ +/* + * This file contains the light-weight system call handlers (fsyscall-handlers). + * + * Copyright (C) 2003 Hewlett-Packard Co + * David Mosberger-Tang + */ + +#include +#include +#include +#include + +ENTRY(fsys_ni_syscall) + mov r8=ENOSYS + mov r10=-1 + MCKINLEY_E7_WORKAROUND + br.ret.sptk.many b6 +END(fsys_ni_syscall) + +ENTRY(fsys_getpid) + add r9=TI_FLAGS+IA64_TASK_SIZE,r16 + ;; + ld4 r9=[r9] + add r8=IA64_TASK_TGID_OFFSET,r16 + ;; + and r9=TIF_ALLWORK_MASK,r9 + ld4 r8=[r8] + ;; + cmp.ne p8,p0=0,r9 +(p8) br.spnt.many fsys_fallback_syscall + MCKINLEY_E7_WORKAROUND + br.ret.sptk.many b6 +END(fsys_getpid) + + .rodata + .align 8 + .globl fsyscall_table +fsyscall_table: + data8 fsys_ni_syscall + data8 fsys_fallback_syscall // exit // 1025 + data8 fsys_fallback_syscall // read + data8 fsys_fallback_syscall // write + data8 fsys_fallback_syscall // open + data8 fsys_fallback_syscall // close + data8 fsys_fallback_syscall // creat // 1030 + data8 fsys_fallback_syscall // link + data8 fsys_fallback_syscall // unlink + data8 fsys_fallback_syscall // execve + data8 fsys_fallback_syscall // chdir + data8 fsys_fallback_syscall // fchdir // 1035 + data8 fsys_fallback_syscall // utimes + data8 fsys_fallback_syscall // mknod + data8 fsys_fallback_syscall // chmod + data8 fsys_fallback_syscall // chown + data8 fsys_fallback_syscall // lseek // 1040 + data8 fsys_getpid + data8 fsys_fallback_syscall // getppid + data8 fsys_fallback_syscall // mount + data8 fsys_fallback_syscall // umount + data8 fsys_fallback_syscall // setuid // 1045 + data8 fsys_fallback_syscall // getuid + data8 fsys_fallback_syscall // geteuid + data8 fsys_fallback_syscall // ptrace + data8 fsys_fallback_syscall // access + data8 fsys_fallback_syscall // sync // 1050 + data8 fsys_fallback_syscall // fsync + data8 fsys_fallback_syscall // fdatasync + data8 fsys_fallback_syscall // kill + data8 fsys_fallback_syscall // rename + data8 fsys_fallback_syscall // mkdir // 1055 + data8 fsys_fallback_syscall // rmdir + data8 fsys_fallback_syscall // dup + data8 fsys_fallback_syscall // pipe + data8 fsys_fallback_syscall // times + data8 fsys_fallback_syscall // brk // 1060 + data8 fsys_fallback_syscall // setgid + data8 fsys_fallback_syscall // getgid + data8 fsys_fallback_syscall // getegid + data8 fsys_fallback_syscall // acct + data8 fsys_fallback_syscall // ioctl // 1065 + data8 fsys_fallback_syscall // fcntl + data8 fsys_fallback_syscall // umask + data8 fsys_fallback_syscall // chroot + data8 fsys_fallback_syscall // ustat + data8 fsys_fallback_syscall // dup2 // 1070 + data8 fsys_fallback_syscall // setreuid + data8 fsys_fallback_syscall // setregid + data8 fsys_fallback_syscall // getresuid + data8 fsys_fallback_syscall // setresuid + data8 fsys_fallback_syscall // getresgid // 1075 + data8 fsys_fallback_syscall // setresgid + data8 fsys_fallback_syscall // getgroups + data8 fsys_fallback_syscall // setgroups + data8 fsys_fallback_syscall // getpgid + data8 fsys_fallback_syscall // setpgid // 1080 + data8 fsys_fallback_syscall // setsid + data8 fsys_fallback_syscall // getsid + data8 fsys_fallback_syscall // sethostname + data8 fsys_fallback_syscall // setrlimit + data8 fsys_fallback_syscall // getrlimit // 1085 + data8 fsys_fallback_syscall // getrusage + data8 fsys_fallback_syscall // gettimeofday + data8 fsys_fallback_syscall // settimeofday + data8 fsys_fallback_syscall // select + data8 fsys_fallback_syscall // poll // 1090 + data8 fsys_fallback_syscall // symlink + data8 fsys_fallback_syscall // readlink + data8 fsys_fallback_syscall // uselib + data8 fsys_fallback_syscall // swapon + data8 fsys_fallback_syscall // swapoff // 1095 + data8 fsys_fallback_syscall // reboot + data8 fsys_fallback_syscall // truncate + data8 fsys_fallback_syscall // ftruncate + data8 fsys_fallback_syscall // fchmod + data8 fsys_fallback_syscall // fchown // 1100 + data8 fsys_fallback_syscall // getpriority + data8 fsys_fallback_syscall // setpriority + data8 fsys_fallback_syscall // statfs + data8 fsys_fallback_syscall // fstatfs + data8 fsys_fallback_syscall // gettid // 1105 + data8 fsys_fallback_syscall // semget + data8 fsys_fallback_syscall // semop + data8 fsys_fallback_syscall // semctl + data8 fsys_fallback_syscall // msgget + data8 fsys_fallback_syscall // msgsnd // 1110 + data8 fsys_fallback_syscall // msgrcv + data8 fsys_fallback_syscall // msgctl + data8 fsys_fallback_syscall // shmget + data8 fsys_fallback_syscall // shmat + data8 fsys_fallback_syscall // shmdt // 1115 + data8 fsys_fallback_syscall // shmctl + data8 fsys_fallback_syscall // syslog + data8 fsys_fallback_syscall // setitimer + data8 fsys_fallback_syscall // getitimer + data8 fsys_fallback_syscall // 1120 + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall // vhangup + data8 fsys_fallback_syscall // lchown + data8 fsys_fallback_syscall // remap_file_pages // 1125 + data8 fsys_fallback_syscall // wait4 + data8 fsys_fallback_syscall // sysinfo + data8 fsys_fallback_syscall // clone + data8 fsys_fallback_syscall // setdomainname + data8 fsys_fallback_syscall // newuname // 1130 + data8 fsys_fallback_syscall // adjtimex + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall // init_module + data8 fsys_fallback_syscall // delete_module + data8 fsys_fallback_syscall // 1135 + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall // quotactl + data8 fsys_fallback_syscall // bdflush + data8 fsys_fallback_syscall // sysfs + data8 fsys_fallback_syscall // personality // 1140 + data8 fsys_fallback_syscall // afs_syscall + data8 fsys_fallback_syscall // setfsuid + data8 fsys_fallback_syscall // setfsgid + data8 fsys_fallback_syscall // getdents + data8 fsys_fallback_syscall // flock // 1145 + data8 fsys_fallback_syscall // readv + data8 fsys_fallback_syscall // writev + data8 fsys_fallback_syscall // pread64 + data8 fsys_fallback_syscall // pwrite64 + data8 fsys_fallback_syscall // sysctl // 1150 + data8 fsys_fallback_syscall // mmap + data8 fsys_fallback_syscall // munmap + data8 fsys_fallback_syscall // mlock + data8 fsys_fallback_syscall // mlockall + data8 fsys_fallback_syscall // mprotect // 1155 + data8 fsys_fallback_syscall // mremap + data8 fsys_fallback_syscall // msync + data8 fsys_fallback_syscall // munlock + data8 fsys_fallback_syscall // munlockall + data8 fsys_fallback_syscall // sched_getparam // 1160 + data8 fsys_fallback_syscall // sched_setparam + data8 fsys_fallback_syscall // sched_getscheduler + data8 fsys_fallback_syscall // sched_setscheduler + data8 fsys_fallback_syscall // sched_yield + data8 fsys_fallback_syscall // sched_get_priority_max // 1165 + data8 fsys_fallback_syscall // sched_get_priority_min + data8 fsys_fallback_syscall // sched_rr_get_interval + data8 fsys_fallback_syscall // nanosleep + data8 fsys_fallback_syscall // nfsservctl + data8 fsys_fallback_syscall // prctl // 1170 + data8 fsys_fallback_syscall // getpagesize + data8 fsys_fallback_syscall // mmap2 + data8 fsys_fallback_syscall // pciconfig_read + data8 fsys_fallback_syscall // pciconfig_write + data8 fsys_fallback_syscall // perfmonctl // 1175 + data8 fsys_fallback_syscall // sigaltstack + data8 fsys_fallback_syscall // rt_sigaction + data8 fsys_fallback_syscall // rt_sigpending + data8 fsys_fallback_syscall // rt_sigprocmask + data8 fsys_fallback_syscall // rt_sigqueueinfo // 1180 + data8 fsys_fallback_syscall // rt_sigreturn + data8 fsys_fallback_syscall // rt_sigsuspend + data8 fsys_fallback_syscall // rt_sigtimedwait + data8 fsys_fallback_syscall // getcwd + data8 fsys_fallback_syscall // capget // 1185 + data8 fsys_fallback_syscall // capset + data8 fsys_fallback_syscall // sendfile + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall // socket // 1190 + data8 fsys_fallback_syscall // bind + data8 fsys_fallback_syscall // connect + data8 fsys_fallback_syscall // listen + data8 fsys_fallback_syscall // accept + data8 fsys_fallback_syscall // getsockname // 1195 + data8 fsys_fallback_syscall // getpeername + data8 fsys_fallback_syscall // socketpair + data8 fsys_fallback_syscall // send + data8 fsys_fallback_syscall // sendto + data8 fsys_fallback_syscall // recv // 1200 + data8 fsys_fallback_syscall // recvfrom + data8 fsys_fallback_syscall // shutdown + data8 fsys_fallback_syscall // setsockopt + data8 fsys_fallback_syscall // getsockopt + data8 fsys_fallback_syscall // sendmsg // 1205 + data8 fsys_fallback_syscall // recvmsg + data8 fsys_fallback_syscall // pivot_root + data8 fsys_fallback_syscall // mincore + data8 fsys_fallback_syscall // madvise + data8 fsys_fallback_syscall // newstat // 1210 + data8 fsys_fallback_syscall // newlstat + data8 fsys_fallback_syscall // newfstat + data8 fsys_fallback_syscall // clone2 + data8 fsys_fallback_syscall // getdents64 + data8 fsys_fallback_syscall // getunwind // 1215 + data8 fsys_fallback_syscall // readahead + data8 fsys_fallback_syscall // setxattr + data8 fsys_fallback_syscall // lsetxattr + data8 fsys_fallback_syscall // fsetxattr + data8 fsys_fallback_syscall // getxattr // 1220 + data8 fsys_fallback_syscall // lgetxattr + data8 fsys_fallback_syscall // fgetxattr + data8 fsys_fallback_syscall // listxattr + data8 fsys_fallback_syscall // llistxattr + data8 fsys_fallback_syscall // flistxattr // 1225 + data8 fsys_fallback_syscall // removexattr + data8 fsys_fallback_syscall // lremovexattr + data8 fsys_fallback_syscall // fremovexattr + data8 fsys_fallback_syscall // tkill + data8 fsys_fallback_syscall // futex // 1230 + data8 fsys_fallback_syscall // sched_setaffinity + data8 fsys_fallback_syscall // sched_getaffinity + data8 fsys_fallback_syscall // set_tid_address + data8 fsys_fallback_syscall // alloc_hugepages + data8 fsys_fallback_syscall // free_hugepages // 1235 + data8 fsys_fallback_syscall // exit_group + data8 fsys_fallback_syscall // lookup_dcookie + data8 fsys_fallback_syscall // io_setup + data8 fsys_fallback_syscall // io_destroy + data8 fsys_fallback_syscall // io_getevents // 1240 + data8 fsys_fallback_syscall // io_submit + data8 fsys_fallback_syscall // io_cancel + data8 fsys_fallback_syscall // epoll_create + data8 fsys_fallback_syscall // epoll_ctl + data8 fsys_fallback_syscall // epoll_wait // 1245 + data8 fsys_fallback_syscall // restart_syscall + data8 fsys_fallback_syscall // semtimedop + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall // 1250 + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall // 1255 + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall // 1260 + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall // 1265 + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall // 1270 + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall // 1275 + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall + data8 fsys_fallback_syscall diff -Nru a/arch/ia64/kernel/fw-emu.c b/arch/ia64/kernel/fw-emu.c --- a/arch/ia64/kernel/fw-emu.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/kernel/fw-emu.c Wed Jan 15 16:57:28 2003 @@ -20,7 +20,13 @@ #define MB (1024*1024UL) -#define NUM_MEM_DESCS 3 +#define SIMPLE_MEMMAP 1 + +#if SIMPLE_MEMMAP +# define NUM_MEM_DESCS 4 +#else +# define NUM_MEM_DESCS 16 +#endif static char fw_mem[( sizeof(struct ia64_boot_param) + sizeof(efi_system_table_t) @@ -379,6 +385,17 @@ struct ia64_boot_param *bp; unsigned char checksum = 0; char *cp, *cmd_line; + int i = 0; +# define MAKE_MD(typ, attr, start, end) \ + do { \ + md = efi_memmap + i++; \ + md->type = typ; \ + md->pad = 0; \ + md->phys_addr = start; \ + md->virt_addr = 0; \ + md->num_pages = (end - start) >> 12; \ + md->attribute = attr; \ + } while (0) memset(fw_mem, 0, sizeof(fw_mem)); @@ -464,47 +481,29 @@ sal_systab->checksum = -checksum; +#if SIMPLE_MEMMAP /* simulate free memory at physical address zero */ - md = &efi_memmap[0]; - md->type = EFI_BOOT_SERVICES_DATA; - md->pad = 0; - md->phys_addr = 0*MB; - md->virt_addr = 0; - md->num_pages = (1*MB) >> 12; /* 1MB (in 4KB pages) */ - md->attribute = EFI_MEMORY_WB; - - /* fill in a memory descriptor: */ - md = &efi_memmap[1]; - md->type = EFI_CONVENTIONAL_MEMORY; - md->pad = 0; - md->phys_addr = 2*MB; - md->virt_addr = 0; - md->num_pages = (128*MB) >> 12; /* 128MB (in 4KB pages) */ - md->attribute = EFI_MEMORY_WB; - - /* descriptor for firmware emulator: */ - md = &efi_memmap[2]; - md->type = EFI_PAL_CODE; - md->pad = 0; - md->phys_addr = 1*MB; - md->virt_addr = 1*MB; - md->num_pages = (1*MB) >> 12; /* 1MB (in 4KB pages) */ - md->attribute = EFI_MEMORY_WB; - -#if 0 - /* - * XXX bootmem is broken for now... (remember to NUM_MEM_DESCS - * if you re-enable this!) - */ - - /* descriptor for high memory (>4GB): */ - md = &efi_memmap[3]; - md->type = EFI_CONVENTIONAL_MEMORY; - md->pad = 0; - md->phys_addr = 4096*MB; - md->virt_addr = 0; - md->num_pages = (32*MB) >> 12; /* 32MB (in 4KB pages) */ - md->attribute = EFI_MEMORY_WB; + MAKE_MD(EFI_BOOT_SERVICES_DATA, EFI_MEMORY_WB, 0*MB, 1*MB); + MAKE_MD(EFI_PAL_CODE, EFI_MEMORY_WB, 1*MB, 2*MB); + MAKE_MD(EFI_CONVENTIONAL_MEMORY, EFI_MEMORY_WB, 2*MB, 130*MB); + MAKE_MD(EFI_CONVENTIONAL_MEMORY, EFI_MEMORY_WB, 4096*MB, 4128*MB); +#else + MAKE_MD( 4, 0x9, 0x0000000000000000, 0x0000000000001000); + MAKE_MD( 7, 0x9, 0x0000000000001000, 0x000000000008a000); + MAKE_MD( 4, 0x9, 0x000000000008a000, 0x00000000000a0000); + MAKE_MD( 5, 0x8000000000000009, 0x00000000000c0000, 0x0000000000100000); + MAKE_MD( 7, 0x9, 0x0000000000100000, 0x0000000004400000); + MAKE_MD( 2, 0x9, 0x0000000004400000, 0x0000000004be5000); + MAKE_MD( 7, 0x9, 0x0000000004be5000, 0x000000007f77e000); + MAKE_MD( 6, 0x8000000000000009, 0x000000007f77e000, 0x000000007fb94000); + MAKE_MD( 6, 0x8000000000000009, 0x000000007fb94000, 0x000000007fb95000); + MAKE_MD( 6, 0x8000000000000009, 0x000000007fb95000, 0x000000007fc00000); + MAKE_MD(13, 0x8000000000000009, 0x000000007fc00000, 0x000000007fc3a000); + MAKE_MD( 7, 0x9, 0x000000007fc3a000, 0x000000007fea0000); + MAKE_MD( 5, 0x8000000000000009, 0x000000007fea0000, 0x000000007fea8000); + MAKE_MD( 7, 0x9, 0x000000007fea8000, 0x000000007feab000); + MAKE_MD( 5, 0x8000000000000009, 0x000000007feab000, 0x000000007ffff000); + MAKE_MD( 7, 0x9, 0x00000000ff400000, 0x0000000104000000); #endif bp->efi_systab = __pa(&fw_mem); diff -Nru a/arch/ia64/kernel/gate.S b/arch/ia64/kernel/gate.S --- a/arch/ia64/kernel/gate.S Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/gate.S Wed Jan 15 16:57:29 2003 @@ -2,7 +2,7 @@ * This file contains the code that gets mapped at the upper end of each task's text * region. For now, it contains the signal trampoline code only. * - * Copyright (C) 1999-2002 Hewlett-Packard Co + * Copyright (C) 1999-2003 Hewlett-Packard Co * David Mosberger-Tang */ @@ -14,6 +14,87 @@ #include .section .text.gate, "ax" +.start_gate: + + +#if CONFIG_FSYS + +#include + +/* + * On entry: + * r11 = saved ar.pfs + * r15 = system call # + * b0 = saved return address + * b6 = return address + * On exit: + * r11 = saved ar.pfs + * r15 = system call # + * b0 = saved return address + * all other "scratch" registers: undefined + * all "preserved" registers: same as on entry + */ +GLOBAL_ENTRY(syscall_via_epc) + .prologue + .altrp b6 + .body +{ + /* + * Note: the kernel cannot assume that the first two instructions in this + * bundle get executed. The remaining code must be safe even if + * they do not get executed. + */ + adds r17=-1024,r15 + mov r10=0 // default to successful syscall execution + epc +} + ;; + rsm psr.be + movl r18=fsyscall_table + + mov r16=IA64_KR(CURRENT) + mov r19=255 + ;; + shladd r18=r17,3,r18 + cmp.geu p6,p0=r19,r17 // (syscall > 0 && syscall <= 1024+255)? + ;; + srlz.d // ensure little-endian byteorder is in effect +(p6) ld8 r18=[r18] + ;; +(p6) mov b7=r18 +(p6) br.sptk.many b7 + + mov r10=-1 + mov r8=ENOSYS + MCKINLEY_E7_WORKAROUND + br.ret.sptk.many b6 +END(syscall_via_epc) + +GLOBAL_ENTRY(syscall_via_break) + .prologue + .altrp b6 + .body + break 0x100000 + br.ret.sptk.many b6 +END(syscall_via_break) + +GLOBAL_ENTRY(fsys_fallback_syscall) + /* + * It would be better/fsyser to do the SAVE_MIN magic directly here, but for now + * we simply fall back on doing a system-call via break. Good enough + * to get started. (Note: we have to do this through the gate page again, since + * the br.ret will switch us back to user-level privilege.) + * + * XXX Move this back to fsys.S after changing it over to avoid break 0x100000. + */ + movl r2=(syscall_via_break - .start_gate) + GATE_ADDR + ;; + MCKINLEY_E7_WORKAROUND + mov b7=r2 + br.ret.sptk.many b7 +END(fsys_fallback_syscall) + +#endif /* CONFIG_FSYS */ # define ARG0_OFF (16 + IA64_SIGFRAME_ARG0_OFFSET) # define ARG1_OFF (16 + IA64_SIGFRAME_ARG1_OFFSET) diff -Nru a/arch/ia64/kernel/head.S b/arch/ia64/kernel/head.S --- a/arch/ia64/kernel/head.S Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/head.S Wed Jan 15 16:57:29 2003 @@ -5,7 +5,7 @@ * to set up the kernel's global pointer and jump to the kernel * entry point. * - * Copyright (C) 1998-2001 Hewlett-Packard Co + * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co * David Mosberger-Tang * Stephane Eranian * Copyright (C) 1999 VA Linux Systems @@ -143,17 +143,14 @@ movl r2=init_thread_union cmp.eq isBP,isAP=r0,r0 #endif - ;; - extr r3=r2,0,61 // r3 == phys addr of task struct mov r16=KERNEL_TR_PAGE_NUM ;; // load the "current" pointer (r13) and ar.k6 with the current task - mov r13=r2 - mov IA64_KR(CURRENT)=r3 // Physical address - + mov IA64_KR(CURRENT)=r2 // virtual address // initialize k4 to a safe value (64-128MB is mapped by TR_KERNEL) mov IA64_KR(CURRENT_STACK)=r16 + mov r13=r2 /* * Reserve space at the top of the stack for "struct pt_regs". Kernel threads * don't store interesting values in that structure, but the space still needs diff -Nru a/arch/ia64/kernel/ia64_ksyms.c b/arch/ia64/kernel/ia64_ksyms.c --- a/arch/ia64/kernel/ia64_ksyms.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/ia64_ksyms.c Wed Jan 15 16:57:29 2003 @@ -56,6 +56,12 @@ #include EXPORT_SYMBOL(clear_page); +#ifdef CONFIG_VIRTUAL_MEM_MAP +#include +EXPORT_SYMBOL(vmalloc_end); +EXPORT_SYMBOL(ia64_pfn_valid); +#endif + #include # ifndef CONFIG_NUMA EXPORT_SYMBOL(cpu_info__per_cpu); @@ -86,7 +92,7 @@ EXPORT_SYMBOL(ia64_cpu_to_sapicid); #else /* !CONFIG_SMP */ -EXPORT_SYMBOL(__flush_tlb_all); +EXPORT_SYMBOL(local_flush_tlb_all); #endif /* !CONFIG_SMP */ diff -Nru a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S --- a/arch/ia64/kernel/ivt.S Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/kernel/ivt.S Wed Jan 15 16:57:28 2003 @@ -192,7 +192,7 @@ rfi END(vhpt_miss) - .align 1024 + .org ia64_ivt+0x400 ///////////////////////////////////////////////////////////////////////////////////////// // 0x0400 Entry 1 (size 64 bundles) ITLB (21) ENTRY(itlb_miss) @@ -206,7 +206,7 @@ mov r16=cr.ifa // get virtual address mov r29=b0 // save b0 mov r31=pr // save predicates -itlb_fault: +.itlb_fault: mov r17=cr.iha // get virtual address of L3 PTE movl r30=1f // load nested fault continuation point ;; @@ -230,7 +230,7 @@ rfi END(itlb_miss) - .align 1024 + .org ia64_ivt+0x0800 ///////////////////////////////////////////////////////////////////////////////////////// // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48) ENTRY(dtlb_miss) @@ -268,7 +268,7 @@ rfi END(dtlb_miss) - .align 1024 + .org ia64_ivt+0x0c00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19) ENTRY(alt_itlb_miss) @@ -288,7 +288,7 @@ ;; (p8) mov cr.iha=r17 (p8) mov r29=b0 // save b0 -(p8) br.cond.dptk itlb_fault +(p8) br.cond.dptk .itlb_fault #endif extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl and r19=r19,r16 // clear ed, reserved bits, and PTE control bits @@ -306,7 +306,7 @@ rfi END(alt_itlb_miss) - .align 1024 + .org ia64_ivt+0x1000 ///////////////////////////////////////////////////////////////////////////////////////// // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46) ENTRY(alt_dtlb_miss) @@ -379,7 +379,7 @@ br.call.sptk.many b6=ia64_do_page_fault // ignore return address END(page_fault) - .align 1024 + .org ia64_ivt+0x1400 ///////////////////////////////////////////////////////////////////////////////////////// // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45) ENTRY(nested_dtlb_miss) @@ -440,7 +440,7 @@ br.sptk.many b0 // return to continuation point END(nested_dtlb_miss) - .align 1024 + .org ia64_ivt+0x1800 ///////////////////////////////////////////////////////////////////////////////////////// // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24) ENTRY(ikey_miss) @@ -448,7 +448,7 @@ FAULT(6) END(ikey_miss) - .align 1024 + .org ia64_ivt+0x1c00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51) ENTRY(dkey_miss) @@ -456,7 +456,7 @@ FAULT(7) END(dkey_miss) - .align 1024 + .org ia64_ivt+0x2000 ///////////////////////////////////////////////////////////////////////////////////////// // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54) ENTRY(dirty_bit) @@ -512,7 +512,7 @@ rfi END(idirty_bit) - .align 1024 + .org ia64_ivt+0x2400 ///////////////////////////////////////////////////////////////////////////////////////// // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27) ENTRY(iaccess_bit) @@ -571,7 +571,7 @@ rfi END(iaccess_bit) - .align 1024 + .org ia64_ivt+0x2800 ///////////////////////////////////////////////////////////////////////////////////////// // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55) ENTRY(daccess_bit) @@ -618,7 +618,7 @@ rfi END(daccess_bit) - .align 1024 + .org ia64_ivt+0x2c00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33) ENTRY(break_fault) @@ -690,7 +690,7 @@ // NOT REACHED END(break_fault) -ENTRY(demine_args) +ENTRY_MIN_ALIGN(demine_args) alloc r2=ar.pfs,8,0,0,0 tnat.nz p8,p0=in0 tnat.nz p9,p0=in1 @@ -719,7 +719,7 @@ br.ret.sptk.many rp END(demine_args) - .align 1024 + .org ia64_ivt+0x3000 ///////////////////////////////////////////////////////////////////////////////////////// // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4) ENTRY(interrupt) @@ -746,19 +746,19 @@ br.call.sptk.many b6=ia64_handle_irq END(interrupt) - .align 1024 + .org ia64_ivt+0x3400 ///////////////////////////////////////////////////////////////////////////////////////// // 0x3400 Entry 13 (size 64 bundles) Reserved DBG_FAULT(13) FAULT(13) - .align 1024 + .org ia64_ivt+0x3800 ///////////////////////////////////////////////////////////////////////////////////////// // 0x3800 Entry 14 (size 64 bundles) Reserved DBG_FAULT(14) FAULT(14) - .align 1024 + .org ia64_ivt+0x3c00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x3c00 Entry 15 (size 64 bundles) Reserved DBG_FAULT(15) @@ -803,7 +803,7 @@ br.sptk.many ia64_leave_kernel END(dispatch_illegal_op_fault) - .align 1024 + .org ia64_ivt+0x4000 ///////////////////////////////////////////////////////////////////////////////////////// // 0x4000 Entry 16 (size 64 bundles) Reserved DBG_FAULT(16) @@ -893,7 +893,7 @@ #endif /* CONFIG_IA32_SUPPORT */ - .align 1024 + .org ia64_ivt+0x4400 ///////////////////////////////////////////////////////////////////////////////////////// // 0x4400 Entry 17 (size 64 bundles) Reserved DBG_FAULT(17) @@ -925,7 +925,7 @@ br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr END(non_syscall) - .align 1024 + .org ia64_ivt+0x4800 ///////////////////////////////////////////////////////////////////////////////////////// // 0x4800 Entry 18 (size 64 bundles) Reserved DBG_FAULT(18) @@ -959,7 +959,7 @@ br.sptk.many ia64_prepare_handle_unaligned END(dispatch_unaligned_handler) - .align 1024 + .org ia64_ivt+0x4c00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x4c00 Entry 19 (size 64 bundles) Reserved DBG_FAULT(19) @@ -1005,7 +1005,7 @@ // --- End of long entries, Beginning of short entries // - .align 1024 + .org ia64_ivt+0x5000 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49) ENTRY(page_not_present) @@ -1025,7 +1025,7 @@ br.sptk.many page_fault END(page_not_present) - .align 256 + .org ia64_ivt+0x5100 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52) ENTRY(key_permission) @@ -1038,7 +1038,7 @@ br.sptk.many page_fault END(key_permission) - .align 256 + .org ia64_ivt+0x5200 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26) ENTRY(iaccess_rights) @@ -1051,7 +1051,7 @@ br.sptk.many page_fault END(iaccess_rights) - .align 256 + .org ia64_ivt+0x5300 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53) ENTRY(daccess_rights) @@ -1064,7 +1064,7 @@ br.sptk.many page_fault END(daccess_rights) - .align 256 + .org ia64_ivt+0x5400 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39) ENTRY(general_exception) @@ -1079,7 +1079,7 @@ br.sptk.many dispatch_to_fault_handler END(general_exception) - .align 256 + .org ia64_ivt+0x5500 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35) ENTRY(disabled_fp_reg) @@ -1092,7 +1092,7 @@ br.sptk.many dispatch_to_fault_handler END(disabled_fp_reg) - .align 256 + .org ia64_ivt+0x5600 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50) ENTRY(nat_consumption) @@ -1100,7 +1100,7 @@ FAULT(26) END(nat_consumption) - .align 256 + .org ia64_ivt+0x5700 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5700 Entry 27 (size 16 bundles) Speculation (40) ENTRY(speculation_vector) @@ -1137,13 +1137,13 @@ rfi // and go back END(speculation_vector) - .align 256 + .org ia64_ivt+0x5800 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5800 Entry 28 (size 16 bundles) Reserved DBG_FAULT(28) FAULT(28) - .align 256 + .org ia64_ivt+0x5900 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56) ENTRY(debug_vector) @@ -1151,7 +1151,7 @@ FAULT(29) END(debug_vector) - .align 256 + .org ia64_ivt+0x5a00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57) ENTRY(unaligned_access) @@ -1162,91 +1162,103 @@ br.sptk.many dispatch_unaligned_handler END(unaligned_access) - .align 256 + .org ia64_ivt+0x5b00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57) +ENTRY(unsupported_data_reference) DBG_FAULT(31) FAULT(31) +END(unsupported_data_reference) - .align 256 + .org ia64_ivt+0x5c00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64) +ENTRY(floating_point_fault) DBG_FAULT(32) FAULT(32) +END(floating_point_fault) - .align 256 + .org ia64_ivt+0x5d00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66) +ENTRY(floating_point_trap) DBG_FAULT(33) FAULT(33) +END(floating_point_trap) - .align 256 + .org ia64_ivt+0x5e00 ///////////////////////////////////////////////////////////////////////////////////////// -// 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Tranfer Trap (66) +// 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66) +ENTRY(lower_privilege_trap) DBG_FAULT(34) FAULT(34) +END(lower_privilege_trap) - .align 256 + .org ia64_ivt+0x5f00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68) +ENTRY(taken_branch_trap) DBG_FAULT(35) FAULT(35) +END(taken_branch_trap) - .align 256 + .org ia64_ivt+0x6000 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69) +ENTRY(single_step_trap) DBG_FAULT(36) FAULT(36) +END(single_step_trap) - .align 256 + .org ia64_ivt+0x6100 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6100 Entry 37 (size 16 bundles) Reserved DBG_FAULT(37) FAULT(37) - .align 256 + .org ia64_ivt+0x6200 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6200 Entry 38 (size 16 bundles) Reserved DBG_FAULT(38) FAULT(38) - .align 256 + .org ia64_ivt+0x6300 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6300 Entry 39 (size 16 bundles) Reserved DBG_FAULT(39) FAULT(39) - .align 256 + .org ia64_ivt+0x6400 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6400 Entry 40 (size 16 bundles) Reserved DBG_FAULT(40) FAULT(40) - .align 256 + .org ia64_ivt+0x6500 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6500 Entry 41 (size 16 bundles) Reserved DBG_FAULT(41) FAULT(41) - .align 256 + .org ia64_ivt+0x6600 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6600 Entry 42 (size 16 bundles) Reserved DBG_FAULT(42) FAULT(42) - .align 256 + .org ia64_ivt+0x6700 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6700 Entry 43 (size 16 bundles) Reserved DBG_FAULT(43) FAULT(43) - .align 256 + .org ia64_ivt+0x6800 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6800 Entry 44 (size 16 bundles) Reserved DBG_FAULT(44) FAULT(44) - .align 256 + .org ia64_ivt+0x6900 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77) ENTRY(ia32_exception) @@ -1254,7 +1266,7 @@ FAULT(45) END(ia32_exception) - .align 256 + .org ia64_ivt+0x6a00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71) ENTRY(ia32_intercept) @@ -1284,7 +1296,7 @@ FAULT(46) END(ia32_intercept) - .align 256 + .org ia64_ivt+0x6b00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74) ENTRY(ia32_interrupt) @@ -1297,121 +1309,121 @@ #endif END(ia32_interrupt) - .align 256 + .org ia64_ivt+0x6c00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6c00 Entry 48 (size 16 bundles) Reserved DBG_FAULT(48) FAULT(48) - .align 256 + .org ia64_ivt+0x6d00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6d00 Entry 49 (size 16 bundles) Reserved DBG_FAULT(49) FAULT(49) - .align 256 + .org ia64_ivt+0x6e00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6e00 Entry 50 (size 16 bundles) Reserved DBG_FAULT(50) FAULT(50) - .align 256 + .org ia64_ivt+0x6f00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x6f00 Entry 51 (size 16 bundles) Reserved DBG_FAULT(51) FAULT(51) - .align 256 + .org ia64_ivt+0x7000 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7000 Entry 52 (size 16 bundles) Reserved DBG_FAULT(52) FAULT(52) - .align 256 + .org ia64_ivt+0x7100 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7100 Entry 53 (size 16 bundles) Reserved DBG_FAULT(53) FAULT(53) - .align 256 + .org ia64_ivt+0x7200 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7200 Entry 54 (size 16 bundles) Reserved DBG_FAULT(54) FAULT(54) - .align 256 + .org ia64_ivt+0x7300 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7300 Entry 55 (size 16 bundles) Reserved DBG_FAULT(55) FAULT(55) - .align 256 + .org ia64_ivt+0x7400 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7400 Entry 56 (size 16 bundles) Reserved DBG_FAULT(56) FAULT(56) - .align 256 + .org ia64_ivt+0x7500 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7500 Entry 57 (size 16 bundles) Reserved DBG_FAULT(57) FAULT(57) - .align 256 + .org ia64_ivt+0x7600 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7600 Entry 58 (size 16 bundles) Reserved DBG_FAULT(58) FAULT(58) - .align 256 + .org ia64_ivt+0x7700 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7700 Entry 59 (size 16 bundles) Reserved DBG_FAULT(59) FAULT(59) - .align 256 + .org ia64_ivt+0x7800 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7800 Entry 60 (size 16 bundles) Reserved DBG_FAULT(60) FAULT(60) - .align 256 + .org ia64_ivt+0x7900 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7900 Entry 61 (size 16 bundles) Reserved DBG_FAULT(61) FAULT(61) - .align 256 + .org ia64_ivt+0x7a00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7a00 Entry 62 (size 16 bundles) Reserved DBG_FAULT(62) FAULT(62) - .align 256 + .org ia64_ivt+0x7b00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7b00 Entry 63 (size 16 bundles) Reserved DBG_FAULT(63) FAULT(63) - .align 256 + .org ia64_ivt+0x7c00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7c00 Entry 64 (size 16 bundles) Reserved DBG_FAULT(64) FAULT(64) - .align 256 + .org ia64_ivt+0x7d00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7d00 Entry 65 (size 16 bundles) Reserved DBG_FAULT(65) FAULT(65) - .align 256 + .org ia64_ivt+0x7e00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7e00 Entry 66 (size 16 bundles) Reserved DBG_FAULT(66) FAULT(66) - .align 256 + .org ia64_ivt+0x7f00 ///////////////////////////////////////////////////////////////////////////////////////// // 0x7f00 Entry 67 (size 16 bundles) Reserved DBG_FAULT(67) diff -Nru a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c --- a/arch/ia64/kernel/mca.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/mca.c Wed Jan 15 16:57:29 2003 @@ -69,10 +69,10 @@ u64 ia64_mca_bspstore[1024]; u64 ia64_init_stack[KERNEL_STACK_SIZE] __attribute__((aligned(16))); u64 ia64_mca_sal_data_area[1356]; -u64 ia64_mca_min_state_save_info; u64 ia64_tlb_functional; u64 ia64_os_mca_recovery_successful; - +/* TODO: need to assign min-state structure to UC memory */ +u64 ia64_mca_min_state_save_info[MIN_STATE_AREA_SIZE] __attribute__((aligned(512))); static void ia64_mca_wakeup_ipi_wait(void); static void ia64_mca_wakeup(int cpu); static void ia64_mca_wakeup_all(void); @@ -116,7 +116,7 @@ * Outputs : platform error status */ int -ia64_mca_log_sal_error_record(int sal_info_type) +ia64_mca_log_sal_error_record(int sal_info_type, int called_from_init) { int platform_err = 0; @@ -131,7 +131,10 @@ */ platform_err = ia64_log_print(sal_info_type, (prfunc_t)printk); - ia64_sal_clear_state_info(sal_info_type); + /* temporary: only clear SAL logs on hardware-corrected errors + or if we're logging an error after an MCA-initiated reboot */ + if ((sal_info_type > 1) || (called_from_init)) + ia64_sal_clear_state_info(sal_info_type); return platform_err; } @@ -152,7 +155,7 @@ IA64_MCA_DEBUG("ia64_mca_cpe_int_handler: received interrupt. vector = %#x\n", cpe_irq); /* Get the CMC error record and log it */ - ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE); + ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE, 0); } /* @@ -199,13 +202,15 @@ * * Outputs : None */ -void +int ia64_mca_check_errors (void) { /* * If there is an MCA error record pending, get it and log it. */ - ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA); + ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA, 1); + + return 0; } device_initcall(ia64_mca_check_errors); @@ -237,49 +242,26 @@ #endif /* PLATFORM_MCA_HANDLERS */ -static char *min_state_labels[] = { - "nat", - "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", - "r9", "r10","r11", "r12","r13","r14", "r15", - "b0r16","b0r17", "b0r18", "b0r19", "b0r20", - "b0r21", "b0r22","b0r23", "b0r24", "b0r25", - "b0r26", "b0r27", "b0r28","b0r29", "b0r30", "b0r31", - "r16", "r17", "r18","r19", "r20", "r21","r22", - "r23", "r24","r25", "r26", "r27","r28", "r29", "r30","r31", - "preds", "br0", "rsc", - "iip", "ipsr", "ifs", - "xip", "xpsr", "xfs" -}; - -int ia64_pmss_dump_bank0=0; /* dump bank 0 ? */ - /* * routine to process and prepare to dump min_state_save * information for debugging purposes. * */ void -ia64_process_min_state_save (pal_min_state_area_t *pmss, struct pt_regs *ptregs) +ia64_process_min_state_save (pal_min_state_area_t *pmss) { - int i, max=57; - u64 *tpmss_ptr=(u64 *)pmss; + int i, max = MIN_STATE_AREA_SIZE; + u64 *tpmss_ptr = (u64 *)pmss; + u64 *return_min_state_ptr = ia64_mca_min_state_save_info; /* dump out the min_state_area information */ for (i=0;iproc_err; - ia64_process_min_state_save(&proc_ptr->processor_static_info.min_state_area, - regs); + ia64_process_min_state_save(&proc_ptr->processor_static_info.min_state_area); /* Clear the INIT SAL logs now that they have been saved in the OS buffer */ ia64_sal_clear_state_info(SAL_INFO_TYPE_INIT); @@ -1676,6 +1654,9 @@ /* Print processor static info if any */ if (slpi->valid.psi_static_struct) { spsi = (sal_processor_static_info_t *)p_data; + + /* copy interrupted context PAL min-state info */ + ia64_process_min_state_save(&spsi->min_state_area); /* Print branch register contents if valid */ if (spsi->valid.br) diff -Nru a/arch/ia64/kernel/minstate.h b/arch/ia64/kernel/minstate.h --- a/arch/ia64/kernel/minstate.h Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/minstate.h Wed Jan 15 16:57:29 2003 @@ -30,25 +30,23 @@ * on interrupts. */ #define MINSTATE_START_SAVE_MIN_VIRT \ -(pUser) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \ - dep r1=-1,r1,61,3; /* r1 = current (virtual) */ \ +(pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \ ;; \ -(pUser) mov.m rARRNAT=ar.rnat; \ -(pUser) addl rKRBS=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \ -(pKern) mov r1=sp; /* get sp */ \ - ;; \ -(pUser) lfetch.fault.excl.nt1 [rKRBS]; \ -(pUser) mov rARBSPSTORE=ar.bspstore; /* save ar.bspstore */ \ -(pUser) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \ +(pUStk) mov.m rARRNAT=ar.rnat; \ +(pUStk) addl rKRBS=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \ +(pKStk) mov r1=sp; /* get sp */ \ ;; \ -(pUser) mov ar.bspstore=rKRBS; /* switch to kernel RBS */ \ -(pKern) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \ +(pUStk) lfetch.fault.excl.nt1 [rKRBS]; \ +(pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \ +(pUStk) mov rARBSPSTORE=ar.bspstore; /* save ar.bspstore */ \ ;; \ -(pUser) mov r18=ar.bsp; \ -(pUser) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \ +(pUStk) mov ar.bspstore=rKRBS; /* switch to kernel RBS */ \ +(pKStk) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \ + ;; \ +(pUStk) mov r18=ar.bsp; \ +(pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \ #define MINSTATE_END_SAVE_MIN_VIRT \ - or r13=r13,r14; /* make `current' a kernel virtual address */ \ bsw.1; /* switch back to bank 1 (must be last in insn group) */ \ ;; @@ -57,21 +55,21 @@ * go virtual and dont want to destroy the iip or ipsr. */ #define MINSTATE_START_SAVE_MIN_PHYS \ -(pKern) movl sp=ia64_init_stack+IA64_STK_OFFSET-IA64_PT_REGS_SIZE; \ -(pUser) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \ -(pUser) addl rKRBS=IA64_RBS_OFFSET,r1; /* compute base of register backing store */ \ - ;; \ -(pUser) mov rARRNAT=ar.rnat; \ -(pKern) dep r1=0,sp,61,3; /* compute physical addr of sp */ \ -(pUser) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \ -(pUser) mov rARBSPSTORE=ar.bspstore; /* save ar.bspstore */ \ -(pUser) dep rKRBS=-1,rKRBS,61,3; /* compute kernel virtual addr of RBS */\ +(pKStk) movl sp=ia64_init_stack+IA64_STK_OFFSET-IA64_PT_REGS_SIZE; \ +(pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \ +(pUStk) addl rKRBS=IA64_RBS_OFFSET,r1; /* compute base of register backing store */ \ + ;; \ +(pUStk) mov rARRNAT=ar.rnat; \ +(pKStk) dep r1=0,sp,61,3; /* compute physical addr of sp */ \ +(pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \ +(pUStk) mov rARBSPSTORE=ar.bspstore; /* save ar.bspstore */ \ +(pUStk) dep rKRBS=-1,rKRBS,61,3; /* compute kernel virtual addr of RBS */\ ;; \ -(pKern) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \ -(pUser) mov ar.bspstore=rKRBS; /* switch to kernel RBS */ \ +(pKStk) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \ +(pUStk) mov ar.bspstore=rKRBS; /* switch to kernel RBS */ \ ;; \ -(pUser) mov r18=ar.bsp; \ -(pUser) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \ +(pUStk) mov r18=ar.bsp; \ +(pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \ #define MINSTATE_END_SAVE_MIN_PHYS \ or r12=r12,r14; /* make sp a kernel virtual address */ \ @@ -79,11 +77,13 @@ ;; #ifdef MINSTATE_VIRT +# define MINSTATE_GET_CURRENT(reg) mov reg=IA64_KR(CURRENT) # define MINSTATE_START_SAVE_MIN MINSTATE_START_SAVE_MIN_VIRT # define MINSTATE_END_SAVE_MIN MINSTATE_END_SAVE_MIN_VIRT #endif #ifdef MINSTATE_PHYS +# define MINSTATE_GET_CURRENT(reg) mov reg=IA64_KR(CURRENT);; dep reg=0,reg,61,3 # define MINSTATE_START_SAVE_MIN MINSTATE_START_SAVE_MIN_PHYS # define MINSTATE_END_SAVE_MIN MINSTATE_END_SAVE_MIN_PHYS #endif @@ -110,23 +110,26 @@ * we can pass interruption state as arguments to a handler. */ #define DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \ - mov rARRSC=ar.rsc; \ - mov rARPFS=ar.pfs; \ - mov rR1=r1; \ - mov rARUNAT=ar.unat; \ - mov rCRIPSR=cr.ipsr; \ - mov rB6=b6; /* rB6 = branch reg 6 */ \ - mov rCRIIP=cr.iip; \ - mov r1=IA64_KR(CURRENT); /* r1 = current (physical) */ \ - COVER; \ + mov rARRSC=ar.rsc; /* M */ \ + mov rARUNAT=ar.unat; /* M */ \ + mov rR1=r1; /* A */ \ + MINSTATE_GET_CURRENT(r1); /* M (or M;;I) */ \ + mov rCRIPSR=cr.ipsr; /* M */ \ + mov rARPFS=ar.pfs; /* I */ \ + mov rCRIIP=cr.iip; /* M */ \ + mov rB6=b6; /* I */ /* rB6 = branch reg 6 */ \ + COVER; /* B;; (or nothing) */ \ ;; \ - invala; \ - extr.u r16=rCRIPSR,32,2; /* extract psr.cpl */ \ + adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r1; \ ;; \ - cmp.eq pKern,pUser=r0,r16; /* are we in kernel mode already? (psr.cpl==0) */ \ + ld1 r17=[r16]; /* load current->thread.on_ustack flag */ \ + st1 [r16]=r0; /* clear current->thread.on_ustack flag */ \ /* switch from user to kernel RBS: */ \ ;; \ + invala; /* M */ \ SAVE_IFS; \ + cmp.eq pKStk,pUStk=r0,r17; /* are we in kernel mode already? (psr.cpl==0) */ \ + ;; \ MINSTATE_START_SAVE_MIN \ add r17=L1_CACHE_BYTES,r1 /* really: biggest cache-line size */ \ ;; \ @@ -138,23 +141,23 @@ ;; \ lfetch.fault.excl.nt1 [r17]; \ adds r17=8,r1; /* initialize second base pointer */ \ -(pKern) mov r18=r0; /* make sure r18 isn't NaT */ \ +(pKStk) mov r18=r0; /* make sure r18 isn't NaT */ \ ;; \ st8 [r17]=rCRIIP,16; /* save cr.iip */ \ st8 [r16]=rCRIFS,16; /* save cr.ifs */ \ -(pUser) sub r18=r18,rKRBS; /* r18=RSE.ndirty*8 */ \ +(pUStk) sub r18=r18,rKRBS; /* r18=RSE.ndirty*8 */ \ ;; \ st8 [r17]=rARUNAT,16; /* save ar.unat */ \ st8 [r16]=rARPFS,16; /* save ar.pfs */ \ shl r18=r18,16; /* compute ar.rsc to be used for "loadrs" */ \ ;; \ st8 [r17]=rARRSC,16; /* save ar.rsc */ \ -(pUser) st8 [r16]=rARRNAT,16; /* save ar.rnat */ \ -(pKern) adds r16=16,r16; /* skip over ar_rnat field */ \ +(pUStk) st8 [r16]=rARRNAT,16; /* save ar.rnat */ \ +(pKStk) adds r16=16,r16; /* skip over ar_rnat field */ \ ;; /* avoid RAW on r16 & r17 */ \ -(pUser) st8 [r17]=rARBSPSTORE,16; /* save ar.bspstore */ \ +(pUStk) st8 [r17]=rARBSPSTORE,16; /* save ar.bspstore */ \ st8 [r16]=rARPR,16; /* save predicates */ \ -(pKern) adds r17=16,r17; /* skip over ar_bspstore field */ \ +(pKStk) adds r17=16,r17; /* skip over ar_bspstore field */ \ ;; \ st8 [r17]=rB6,16; /* save b6 */ \ st8 [r16]=r18,16; /* save ar.rsc value for "loadrs" */ \ diff -Nru a/arch/ia64/kernel/pal.S b/arch/ia64/kernel/pal.S --- a/arch/ia64/kernel/pal.S Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/pal.S Wed Jan 15 16:57:29 2003 @@ -4,7 +4,7 @@ * * Copyright (C) 1999 Don Dugger * Copyright (C) 1999 Walt Drummond - * Copyright (C) 1999-2001 Hewlett-Packard Co + * Copyright (C) 1999-2001, 2003 Hewlett-Packard Co * David Mosberger * Stephane Eranian * @@ -114,7 +114,7 @@ ;; rsm psr.i mov b7 = loc2 - ;; + ;; br.call.sptk.many rp=b7 // now make the call .ret0: mov psr.l = loc3 mov ar.pfs = loc1 @@ -131,15 +131,15 @@ * in0 Index of PAL service * in2 - in3 Remaning PAL arguments * - * PSR_DB, PSR_LP, PSR_TB, PSR_ID, PSR_DA are never set by the kernel. + * PSR_LP, PSR_TB, PSR_ID, PSR_DA are never set by the kernel. * So we don't need to clear them. */ -#define PAL_PSR_BITS_TO_CLEAR \ - (IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT | IA64_PSR_RT | \ - IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED | \ +#define PAL_PSR_BITS_TO_CLEAR \ + (IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT | IA64_PSR_DB | IA64_PSR_RT | \ + IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED | \ IA64_PSR_DFL | IA64_PSR_DFH) -#define PAL_PSR_BITS_TO_SET \ +#define PAL_PSR_BITS_TO_SET \ (IA64_PSR_BN) @@ -161,7 +161,7 @@ ;; mov loc3 = psr // save psr adds r8 = 1f-1b,r8 // calculate return address for call - ;; + ;; mov loc4=ar.rsc // save RSE configuration dep.z loc2=loc2,0,61 // convert pal entry point to physical dep.z r8=r8,0,61 // convert rp to physical @@ -275,7 +275,6 @@ * Inputs: * in0 Address of stack storage for fp regs */ - GLOBAL_ENTRY(ia64_load_scratch_fpregs) alloc r3=ar.pfs,1,0,0,0 add r2=16,in0 diff -Nru a/arch/ia64/kernel/palinfo.c b/arch/ia64/kernel/palinfo.c --- a/arch/ia64/kernel/palinfo.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/kernel/palinfo.c Wed Jan 15 16:57:28 2003 @@ -101,26 +101,15 @@ #define RSE_HINTS_COUNT (sizeof(rse_hints)/sizeof(const char *)) -/* - * The current revision of the Volume 2 (July 2000) of - * IA-64 Architecture Software Developer's Manual is wrong. - * Table 4-10 has invalid information concerning the ma field: - * Correct table is: - * bit 0 - 001 - UC - * bit 4 - 100 - UC - * bit 5 - 101 - UCE - * bit 6 - 110 - WC - * bit 7 - 111 - NatPage - */ static const char *mem_attrib[]={ - "Write Back (WB)", /* 000 */ - "Uncacheable (UC)", /* 001 */ - "Reserved", /* 010 */ - "Reserved", /* 011 */ - "Uncacheable (UC)", /* 100 */ - "Uncacheable Exported (UCE)", /* 101 */ - "Write Coalescing (WC)", /* 110 */ - "NaTPage" /* 111 */ + "WB", /* 000 */ + "SW", /* 001 */ + "010", /* 010 */ + "011", /* 011 */ + "UC", /* 100 */ + "UCE", /* 101 */ + "WC", /* 110 */ + "NaTPage" /* 111 */ }; /* @@ -315,6 +304,7 @@ pal_vm_info_2_u_t vm_info_2; pal_tc_info_u_t tc_info; ia64_ptce_info_t ptce; + const char *sep; int i, j; s64 status; @@ -339,7 +329,15 @@ if (ia64_pal_mem_attrib(&attrib) != 0) return 0; - p += sprintf(p, "Supported memory attributes : %s\n", mem_attrib[attrib&0x7]); + p += sprintf(p, "Supported memory attributes : "); + sep = ""; + for (i = 0; i < 8; i++) { + if (attrib & (1 << i)) { + p += sprintf(p, "%s%s", sep, mem_attrib[i]); + sep = ", "; + } + } + p += sprintf(p, "\n"); if ((status=ia64_pal_vm_page_size(&tr_pages, &vw_pages)) !=0) { printk("ia64_pal_vm_page_size=%ld\n", status); diff -Nru a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c --- a/arch/ia64/kernel/process.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/process.c Wed Jan 15 16:57:29 2003 @@ -1,7 +1,7 @@ /* * Architecture-specific setup. * - * Copyright (C) 1998-2002 Hewlett-Packard Co + * Copyright (C) 1998-2003 Hewlett-Packard Co * David Mosberger-Tang */ #define __KERNEL_SYSCALLS__ /* see */ @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -95,7 +96,7 @@ { unsigned long ip = regs->cr_iip + ia64_psr(regs)->ri; - printk("\nPid: %d, comm: %20s\n", current->pid, current->comm); + printk("\nPid: %d, CPU %d, comm: %20s\n", current->pid, smp_processor_id(), current->comm); printk("psr : %016lx ifs : %016lx ip : [<%016lx>] %s\n", regs->cr_ipsr, regs->cr_ifs, ip, print_tainted()); print_symbol("ip is at %s\n", ip); @@ -143,6 +144,13 @@ void do_notify_resume_user (sigset_t *oldset, struct sigscratch *scr, long in_syscall) { + if (fsys_mode(current, &scr->pt)) { + /* defer signal-handling etc. until we return to privilege-level 0. */ + if (!ia64_psr(&scr->pt)->lp) + ia64_psr(&scr->pt)->lp = 1; + return; + } + #ifdef CONFIG_PERFMON if (current->thread.pfm_ovfl_block_reset) pfm_ovfl_block_reset(); @@ -376,36 +384,12 @@ /* clear list of sampling buffer to free for new task */ p->thread.pfm_smpl_buf_list = NULL; - if (current->thread.pfm_context) retval = pfm_inherit(p, child_ptregs); + if (current->thread.pfm_context) + retval = pfm_inherit(p, child_ptregs); #endif return retval; } -void -do_copy_regs (struct unw_frame_info *info, void *arg) -{ - do_copy_task_regs(current, info, arg); -} - -void -do_dump_fpu (struct unw_frame_info *info, void *arg) -{ - do_dump_task_fpu(current, info, arg); -} - -void -ia64_elf_core_copy_regs (struct pt_regs *pt, elf_gregset_t dst) -{ - unw_init_running(do_copy_regs, dst); -} - -int -dump_fpu (struct pt_regs *pt, elf_fpregset_t dst) -{ - unw_init_running(do_dump_fpu, dst); - return 1; /* f0-f31 are always valid so we always return 1 */ -} - static void do_copy_task_regs (struct task_struct *task, struct unw_frame_info *info, void *arg) { @@ -497,36 +481,59 @@ memcpy(dst + 32, task->thread.fph, 96*16); } -int dump_task_regs(struct task_struct *task, elf_gregset_t *regs) +void +do_copy_regs (struct unw_frame_info *info, void *arg) +{ + do_copy_task_regs(current, info, arg); +} + +void +do_dump_fpu (struct unw_frame_info *info, void *arg) +{ + do_dump_task_fpu(current, info, arg); +} + +int +dump_task_regs(struct task_struct *task, elf_gregset_t *regs) { struct unw_frame_info tcore_info; - if(current == task) { + if (current == task) { unw_init_running(do_copy_regs, regs); - } - else { - memset(&tcore_info, 0, sizeof(tcore_info)); + } else { + memset(&tcore_info, 0, sizeof(tcore_info)); unw_init_from_blocked_task(&tcore_info, task); do_copy_task_regs(task, &tcore_info, regs); } - return 1; } -int dump_task_fpu (struct task_struct *task, elf_fpregset_t *dst) +void +ia64_elf_core_copy_regs (struct pt_regs *pt, elf_gregset_t dst) +{ + unw_init_running(do_copy_regs, dst); +} + +int +dump_task_fpu (struct task_struct *task, elf_fpregset_t *dst) { struct unw_frame_info tcore_info; - if(current == task) { + if (current == task) { unw_init_running(do_dump_fpu, dst); - } - else { - memset(&tcore_info, 0, sizeof(tcore_info)); + } else { + memset(&tcore_info, 0, sizeof(tcore_info)); unw_init_from_blocked_task(&tcore_info, task); do_dump_task_fpu(task, &tcore_info, dst); } + return 1; +} - return 1; +int +dump_fpu (struct pt_regs *pt, elf_fpregset_t dst) +{ + unw_init_running(do_dump_fpu, dst); + return 1; /* f0-f31 are always valid so we always return 1 */ } asmlinkage long diff -Nru a/arch/ia64/kernel/ptrace.c b/arch/ia64/kernel/ptrace.c --- a/arch/ia64/kernel/ptrace.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/ptrace.c Wed Jan 15 16:57:29 2003 @@ -1,7 +1,7 @@ /* * Kernel support for the ptrace() and syscall tracing interfaces. * - * Copyright (C) 1999-2001 Hewlett-Packard Co + * Copyright (C) 1999-2002 Hewlett-Packard Co * David Mosberger-Tang * * Derived from the x86 and Alpha versions. Most of the code in here @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -460,6 +461,60 @@ pt->loadrs = 0; } +static inline void +sync_user_rbs_one_thread (struct task_struct *p, int make_writable) +{ + struct switch_stack *sw; + unsigned long urbs_end; + struct pt_regs *pt; + + sw = (struct switch_stack *) (p->thread.ksp + 16); + pt = ia64_task_regs(p); + urbs_end = ia64_get_user_rbs_end(p, pt, NULL); + ia64_sync_user_rbs(p, sw, pt->ar_bspstore, urbs_end); + if (make_writable) + user_flushrs(p, pt); +} + +struct task_list { + struct task_list *next; + struct task_struct *task; +}; + +#ifdef CONFIG_SMP + +static inline void +collect_task (struct task_list **listp, struct task_struct *p, int make_writable) +{ + struct task_list *e; + + e = kmalloc(sizeof(*e), GFP_KERNEL); + if (!e) + /* oops, can't collect more: finish at least what we collected so far... */ + return; + + get_task_struct(p); + e->task = p; + e->next = *listp; + *listp = e; +} + +static inline struct task_list * +finish_task (struct task_list *list, int make_writable) +{ + struct task_list *next = list->next; + + sync_user_rbs_one_thread(list->task, make_writable); + put_task_struct(list->task); + kfree(list); + return next; +} + +#else +# define collect_task(list, p, make_writable) sync_user_rbs_one_thread(p, make_writable) +# define finish_task(list, make_writable) (NULL) +#endif + /* * Synchronize the RSE backing store of CHILD and all tasks that share the address space * with it. CHILD_URBS_END is the address of the end of the register backing store of @@ -473,7 +528,6 @@ threads_sync_user_rbs (struct task_struct *child, unsigned long child_urbs_end, int make_writable) { struct switch_stack *sw; - unsigned long urbs_end; struct task_struct *g, *p; struct mm_struct *mm; struct pt_regs *pt; @@ -493,20 +547,27 @@ if (make_writable) user_flushrs(child, pt); } else { + /* + * Note: we can't call ia64_sync_user_rbs() while holding the + * tasklist_lock because that may cause a dead-lock: ia64_sync_user_rbs() + * may indirectly call tlb_flush_all(), which triggers an IPI. + * Furthermore, tasklist_lock is acquired by fork() with interrupts + * disabled, so with the right timing, the IPI never completes, hence + * tasklist_lock never gets released, hence fork() never completes... + */ + struct task_list *list = NULL; + read_lock(&tasklist_lock); { do_each_thread(g, p) { - if (p->mm == mm && p->state != TASK_RUNNING) { - sw = (struct switch_stack *) (p->thread.ksp + 16); - pt = ia64_task_regs(p); - urbs_end = ia64_get_user_rbs_end(p, pt, NULL); - ia64_sync_user_rbs(p, sw, pt->ar_bspstore, urbs_end); - if (make_writable) - user_flushrs(p, pt); - } + if (p->mm == mm && p->state != TASK_RUNNING) + collect_task(&list, p, make_writable); } while_each_thread(g, p); } read_unlock(&tasklist_lock); + + while (list) + list = finish_task(list, make_writable); } child->thread.flags |= IA64_THREAD_KRBS_SYNCED; /* set the flag in the child thread only */ } @@ -772,21 +833,19 @@ return -1; } #ifdef CONFIG_PERFMON - /* - * Check if debug registers are used - * by perfmon. This test must be done once we know that we can - * do the operation, i.e. the arguments are all valid, but before - * we start modifying the state. + /* + * Check if debug registers are used by perfmon. This test must be done + * once we know that we can do the operation, i.e. the arguments are all + * valid, but before we start modifying the state. * - * Perfmon needs to keep a count of how many processes are - * trying to modify the debug registers for system wide monitoring - * sessions. + * Perfmon needs to keep a count of how many processes are trying to + * modify the debug registers for system wide monitoring sessions. * - * We also include read access here, because they may cause - * the PMU-installed debug register state (dbr[], ibr[]) to - * be reset. The two arrays are also used by perfmon, but - * we do not use IA64_THREAD_DBG_VALID. The registers are restored - * by the PMU context switch code. + * We also include read access here, because they may cause the + * PMU-installed debug register state (dbr[], ibr[]) to be reset. The two + * arrays are also used by perfmon, but we do not use + * IA64_THREAD_DBG_VALID. The registers are restored by the PMU context + * switch code. */ if (pfm_use_debug_registers(child)) return -1; #endif diff -Nru a/arch/ia64/kernel/sal.c b/arch/ia64/kernel/sal.c --- a/arch/ia64/kernel/sal.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/sal.c Wed Jan 15 16:57:29 2003 @@ -77,7 +77,7 @@ return str; } -static void __init +void __init ia64_sal_handler_init (void *entry_point, void *gpval) { /* fill in the SAL procedure descriptor and point ia64_sal to it: */ diff -Nru a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c --- a/arch/ia64/kernel/setup.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/kernel/setup.c Wed Jan 15 16:57:28 2003 @@ -364,11 +364,13 @@ #ifdef CONFIG_ACPI_BOOT /* Initialize the ACPI boot-time table parser */ acpi_table_init(*cmdline_p); - -#ifdef CONFIG_ACPI_NUMA +# ifdef CONFIG_ACPI_NUMA acpi_numa_init(); -#endif - +# endif +#else +# ifdef CONFIG_SMP + smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */ +# endif #endif /* CONFIG_APCI_BOOT */ find_memory(); @@ -421,7 +423,7 @@ #ifdef CONFIG_ACPI_BOOT acpi_boot_init(*cmdline_p); #endif -#ifdef CONFIG_SERIAL_HCDP +#ifdef CONFIG_SERIAL_8250_HCDP if (efi.hcdp) { void setup_serial_hcdp(void *); @@ -469,9 +471,18 @@ # define lpj loops_per_jiffy # define cpunum 0 #endif - char family[32], features[128], *cp; + static struct { + unsigned long mask; + const char *feature_name; + } feature_bits[] = { + { 1UL << 0, "branchlong" }, + { 1UL << 1, "spontaneous deferral"}, + { 1UL << 2, "16-byte atomic ops" } + }; + char family[32], features[128], *cp, sep; struct cpuinfo_ia64 *c = v; unsigned long mask; + int i; mask = c->features; @@ -484,13 +495,24 @@ /* build the feature string: */ memcpy(features, " standard", 10); cp = features; - if (mask & 1) { - strcpy(cp, " branchlong"); - cp = strchr(cp, '\0'); - mask &= ~1UL; + sep = 0; + for (i = 0; i < sizeof(feature_bits)/sizeof(feature_bits[0]); ++i) { + if (mask & feature_bits[i].mask) { + if (sep) + *cp++ = sep; + sep = ','; + *cp++ = ' '; + strcpy(cp, feature_bits[i].feature_name); + cp += strlen(feature_bits[i].feature_name); + mask &= ~feature_bits[i].mask; + } } - if (mask) + if (mask) { + /* print unknown features as a hex value: */ + if (sep) + *cp++ = sep; sprintf(cp, " 0x%lx", mask); + } seq_printf(m, "processor : %d\n" @@ -630,9 +652,8 @@ * "NR_CPUS" pages for all CPUs to avoid that AP calls get_zeroed_page(). */ if (smp_processor_id() == 0) { - cpu_data = (unsigned long) __alloc_bootmem(PERCPU_PAGE_SIZE * NR_CPUS, - PERCPU_PAGE_SIZE, - __pa(MAX_DMA_ADDRESS)); + cpu_data = __alloc_bootmem(PERCPU_PAGE_SIZE * NR_CPUS, PERCPU_PAGE_SIZE, + __pa(MAX_DMA_ADDRESS)); for (cpu = 0; cpu < NR_CPUS; cpu++) { memcpy(cpu_data, __phys_per_cpu_start, __per_cpu_end - __per_cpu_start); __per_cpu_offset[cpu] = (char *) cpu_data - __per_cpu_start; diff -Nru a/arch/ia64/kernel/signal.c b/arch/ia64/kernel/signal.c --- a/arch/ia64/kernel/signal.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/signal.c Wed Jan 15 16:57:29 2003 @@ -385,15 +385,14 @@ frame = (void *) scr->pt.r12; tramp_addr = GATE_ADDR + (ia64_sigtramp - __start_gate_section); - if (ka->sa.sa_flags & SA_ONSTACK) { + if ((ka->sa.sa_flags & SA_ONSTACK) && sas_ss_flags((unsigned long) frame) == 0) { + frame = (void *) ((current->sas_ss_sp + current->sas_ss_size) + & ~(STACK_ALIGN - 1)); /* - * We need to check the memory and register stacks separately, because - * they're switched separately (memory stack is switched in the kernel, - * register stack is switched in the signal trampoline). + * We need to check for the register stack being on the signal stack + * separately, because it's switched separately (memory stack is switched + * in the kernel, register stack is switched in the signal trampoline). */ - if (!on_sig_stack((unsigned long) frame)) - frame = (void *) ((current->sas_ss_sp + current->sas_ss_size) - & ~(STACK_ALIGN - 1)); if (!rbs_on_sig_stack(scr->pt.ar_bspstore)) new_rbs = (current->sas_ss_sp + sizeof(long) - 1) & ~(sizeof(long) - 1); } @@ -453,16 +452,14 @@ handle_signal (unsigned long sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *oldset, struct sigscratch *scr) { -#ifdef CONFIG_IA32_SUPPORT if (IS_IA32_PROCESS(&scr->pt)) { /* send signal to IA-32 process */ if (!ia32_setup_frame1(sig, ka, info, oldset, &scr->pt)) return 0; } else -#endif - /* send signal to IA-64 process */ - if (!setup_frame(sig, ka, info, oldset, scr)) - return 0; + /* send signal to IA-64 process */ + if (!setup_frame(sig, ka, info, oldset, scr)) + return 0; if (ka->sa.sa_flags & SA_ONESHOT) ka->sa.sa_handler = SIG_DFL; @@ -490,6 +487,7 @@ siginfo_t info; long restart = in_syscall; long errno = scr->pt.r8; +# define ERR_CODE(c) (IS_IA32_PROCESS(&scr->pt) ? -(c) : (c)) /* * In the ia64_leave_kernel code path, we want the common case to go fast, which @@ -502,7 +500,6 @@ if (!oldset) oldset = ¤t->blocked; -#ifdef CONFIG_IA32_SUPPORT if (IS_IA32_PROCESS(&scr->pt)) { if (in_syscall) { if (errno >= 0) @@ -510,9 +507,7 @@ else errno = -errno; } - } else -#endif - if (scr->pt.r10 != -1) + } else if (scr->pt.r10 != -1) /* * A system calls has to be restarted only if one of the error codes * ERESTARTNOHAND, ERESTARTSYS, or ERESTARTNOINTR is returned. If r10 @@ -531,25 +526,24 @@ if (restart) { switch (errno) { + case ERESTART_RESTARTBLOCK: + current_thread_info()->restart_block.fn = do_no_restart_syscall; + case ERESTARTNOHAND: + scr->pt.r8 = ERR_CODE(EINTR); + /* note: scr->pt.r10 is already -1 */ + break; + case ERESTARTSYS: if ((ka->sa.sa_flags & SA_RESTART) == 0) { - case ERESTARTNOHAND: -#ifdef CONFIG_IA32_SUPPORT - if (IS_IA32_PROCESS(&scr->pt)) - scr->pt.r8 = -EINTR; - else -#endif - scr->pt.r8 = EINTR; + scr->pt.r8 = ERR_CODE(EINTR); /* note: scr->pt.r10 is already -1 */ break; } case ERESTARTNOINTR: -#ifdef CONFIG_IA32_SUPPORT if (IS_IA32_PROCESS(&scr->pt)) { scr->pt.r8 = scr->pt.r1; scr->pt.cr_iip -= 2; } else -#endif ia64_decrement_ip(&scr->pt); } } @@ -565,19 +559,26 @@ /* Did we come from a system call? */ if (restart) { /* Restart the system call - no handlers present */ - if (errno == ERESTARTNOHAND || errno == ERESTARTSYS || errno == ERESTARTNOINTR) { -#ifdef CONFIG_IA32_SUPPORT + if (errno == ERESTARTNOHAND || errno == ERESTARTSYS || errno == ERESTARTNOINTR + || errno == ERESTART_RESTARTBLOCK) + { if (IS_IA32_PROCESS(&scr->pt)) { scr->pt.r8 = scr->pt.r1; scr->pt.cr_iip -= 2; - } else -#endif - /* - * Note: the syscall number is in r15 which is saved in pt_regs so - * all we need to do here is adjust ip so that the "break" - * instruction gets re-executed. - */ - ia64_decrement_ip(&scr->pt); + if (errno == ERESTART_RESTARTBLOCK) { + scr->pt.r8 = 0; /* x86 version of __NR_restart_syscall */ + scr->pt.cr_iip -= 2; + } + } else { + /* + * Note: the syscall number is in r15 which is saved in + * pt_regs so all we need to do here is adjust ip so that + * the "break" instruction gets re-executed. + */ + ia64_decrement_ip(&scr->pt); + if (errno == ERESTART_RESTARTBLOCK) + scr->pt.r15 = __NR_restart_syscall; + } } } return 0; diff -Nru a/arch/ia64/kernel/smp.c b/arch/ia64/kernel/smp.c --- a/arch/ia64/kernel/smp.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/smp.c Wed Jan 15 16:57:29 2003 @@ -206,8 +206,27 @@ void smp_flush_tlb_all (void) { - smp_call_function((void (*)(void *))__flush_tlb_all, 0, 1, 1); - __flush_tlb_all(); + smp_call_function((void (*)(void *))local_flush_tlb_all, 0, 1, 1); + local_flush_tlb_all(); +} + +void +smp_flush_tlb_mm (struct mm_struct *mm) +{ + local_finish_flush_tlb_mm(mm); + + /* this happens for the common case of a single-threaded fork(): */ + if (likely(mm == current->active_mm && atomic_read(&mm->mm_users) == 1)) + return; + + /* + * We could optimize this further by using mm->cpu_vm_mask to track which CPUs + * have been running in the address space. It's not clear that this is worth the + * trouble though: to avoid races, we have to raise the IPI on the target CPU + * anyhow, and once a CPU is interrupted, the cost of local_flush_tlb_all() is + * rather trivial. + */ + smp_call_function((void (*)(void *))local_finish_flush_tlb_mm, mm, 1, 1); } /* diff -Nru a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c --- a/arch/ia64/kernel/smpboot.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/kernel/smpboot.c Wed Jan 15 16:57:28 2003 @@ -337,7 +337,7 @@ * don't care about the eip and regs settings since we'll never reschedule the * forked task. */ - return do_fork(CLONE_VM|CLONE_IDLETASK, 0, 0, 0, NULL); + return do_fork(CLONE_VM|CLONE_IDLETASK, 0, 0, 0, NULL, NULL); } static int __init @@ -499,7 +499,7 @@ /* * If SMP should be disabled, then really disable it! */ - if (!max_cpus || (max_cpus < -1)) { + if (!max_cpus) { printk(KERN_INFO "SMP mode deactivated.\n"); cpu_online_map = phys_cpu_present_map = 1; return; diff -Nru a/arch/ia64/kernel/sys_ia64.c b/arch/ia64/kernel/sys_ia64.c --- a/arch/ia64/kernel/sys_ia64.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/sys_ia64.c Wed Jan 15 16:57:29 2003 @@ -12,6 +12,7 @@ #include #include #include +#include #include /* doh, must come after sched.h... */ #include #include @@ -317,22 +318,26 @@ #endif /* !CONFIG_HUGETLB_PAGE */ -asmlinkage long -sys_vm86 (long arg0, long arg1, long arg2, long arg3) -{ - printk(KERN_ERR "sys_vm86(%lx, %lx, %lx, %lx)!\n", arg0, arg1, arg2, arg3); - return -ENOSYS; -} - asmlinkage unsigned long -ia64_create_module (const char *name_user, size_t size) +ia64_mremap (unsigned long addr, unsigned long old_len, unsigned long new_len, unsigned long flags, + unsigned long new_addr) { - extern unsigned long sys_create_module (const char *, size_t); - unsigned long addr; + extern unsigned long do_mremap (unsigned long addr, + unsigned long old_len, + unsigned long new_len, + unsigned long flags, + unsigned long new_addr); - addr = sys_create_module (name_user, size); - if (!IS_ERR((void *) addr)) - force_successful_syscall_return(); + down_write(¤t->mm->mmap_sem); + { + addr = do_mremap(addr, old_len, new_len, flags, new_addr); + } + up_write(¤t->mm->mmap_sem); + + if (IS_ERR((void *) addr)) + return addr; + + force_successful_syscall_return(); return addr; } diff -Nru a/arch/ia64/kernel/traps.c b/arch/ia64/kernel/traps.c --- a/arch/ia64/kernel/traps.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/traps.c Wed Jan 15 16:57:29 2003 @@ -1,7 +1,7 @@ /* * Architecture-specific trap handling. * - * Copyright (C) 1998-2002 Hewlett-Packard Co + * Copyright (C) 1998-2003 Hewlett-Packard Co * David Mosberger-Tang * * 05/12/00 grao : added isr in siginfo for SIGFPE @@ -524,6 +524,23 @@ case 29: /* Debug */ case 35: /* Taken Branch Trap */ case 36: /* Single Step Trap */ + if (fsys_mode(current, regs)) { + extern char syscall_via_break[], __start_gate_section[]; + /* + * Got a trap in fsys-mode: Taken Branch Trap and Single Step trap + * need special handling; Debug trap is not supposed to happen. + */ + if (unlikely(vector == 29)) { + die("Got debug trap in fsys-mode---not supposed to happen!", + regs, 0); + return; + } + /* re-do the system call via break 0x100000: */ + regs->cr_iip = GATE_ADDR + (syscall_via_break - __start_gate_section); + ia64_psr(regs)->ri = 0; + ia64_psr(regs)->cpl = 3; + return; + } switch (vector) { case 29: siginfo.si_code = TRAP_HWBKPT; @@ -563,19 +580,31 @@ } return; - case 34: /* Unimplemented Instruction Address Trap */ - if (user_mode(regs)) { - siginfo.si_signo = SIGILL; - siginfo.si_code = ILL_BADIADDR; - siginfo.si_errno = 0; - siginfo.si_flags = 0; - siginfo.si_isr = 0; - siginfo.si_imm = 0; - siginfo.si_addr = (void *) (regs->cr_iip + ia64_psr(regs)->ri); - force_sig_info(SIGILL, &siginfo, current); + case 34: + if (isr & 0x2) { + /* Lower-Privilege Transfer Trap */ + /* + * Just clear PSR.lp and then return immediately: all the + * interesting work (e.g., signal delivery is done in the kernel + * exit path). + */ + ia64_psr(regs)->lp = 0; return; + } else { + /* Unimplemented Instr. Address Trap */ + if (user_mode(regs)) { + siginfo.si_signo = SIGILL; + siginfo.si_code = ILL_BADIADDR; + siginfo.si_errno = 0; + siginfo.si_flags = 0; + siginfo.si_isr = 0; + siginfo.si_imm = 0; + siginfo.si_addr = (void *) (regs->cr_iip + ia64_psr(regs)->ri); + force_sig_info(SIGILL, &siginfo, current); + return; + } + sprintf(buf, "Unimplemented Instruction Address fault"); } - sprintf(buf, "Unimplemented Instruction Address fault"); break; case 45: diff -Nru a/arch/ia64/kernel/unaligned.c b/arch/ia64/kernel/unaligned.c --- a/arch/ia64/kernel/unaligned.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/kernel/unaligned.c Wed Jan 15 16:57:29 2003 @@ -5,6 +5,10 @@ * Stephane Eranian * David Mosberger-Tang * + * 2002/12/09 Fix rotating register handling (off-by-1 error, missing fr-rotation). Fix + * get_rse_reg() to not leak kernel bits to user-level (reading an out-of-frame + * stacked register returns an undefined value; it does NOT trigger a + * "rsvd register fault"). * 2001/10/11 Fix unaligned access to rotating registers in s/w pipelined loops. * 2001/08/13 Correct size of extended floats (float_fsz) from 16 to 10 bytes. * 2001/01/17 Add support emulation of unaligned kernel accesses. @@ -276,6 +280,15 @@ # undef F } +static inline unsigned long +rotate_reg (unsigned long sor, unsigned long rrb, unsigned long reg) +{ + reg += rrb; + if (reg >= sor) + reg -= sor; + return reg; +} + static void set_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long val, int nat) { @@ -287,26 +300,22 @@ long sof = (regs->cr_ifs) & 0x7f; long sor = 8 * ((regs->cr_ifs >> 14) & 0xf); long rrb_gr = (regs->cr_ifs >> 18) & 0x7f; - long ridx; - - if ((r1 - 32) > sor) - ridx = -sof + (r1 - 32); - else if ((r1 - 32) < (sor - rrb_gr)) - ridx = -sof + (r1 - 32) + rrb_gr; - else - ridx = -sof + (r1 - 32) - (sor - rrb_gr); - - DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n", - r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx); + long ridx = r1 - 32; - if ((r1 - 32) >= sof) { + if (ridx >= sof) { /* this should never happen, as the "rsvd register fault" has higher priority */ DPRINT("ignoring write to r%lu; only %lu registers are allocated!\n", r1, sof); return; } + if (ridx < sor) + ridx = rotate_reg(sor, rrb_gr, ridx); + + DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n", + r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx); + on_kbs = ia64_rse_num_regs(kbs, (unsigned long *) sw->ar_bspstore); - addr = ia64_rse_skip_regs((unsigned long *) sw->ar_bspstore, ridx); + addr = ia64_rse_skip_regs((unsigned long *) sw->ar_bspstore, -sof + ridx); if (addr >= kbs) { /* the register is on the kernel backing store: easy... */ rnat_addr = ia64_rse_rnat_addr(addr); @@ -322,19 +331,15 @@ return; } - /* - * Avoid using user_mode() here: with "epc", we cannot use the privilege level to - * infer whether the interrupt task was running on the kernel backing store. - */ - if (regs->r12 >= TASK_SIZE) { - DPRINT("ignoring kernel write to r%lu; register isn't on the RBS!", r1); + if (!user_stack(current, regs)) { + DPRINT("ignoring kernel write to r%lu; register isn't on the kernel RBS!", r1); return; } bspstore = (unsigned long *)regs->ar_bspstore; ubs_end = ia64_rse_skip_regs(bspstore, on_kbs); bsp = ia64_rse_skip_regs(ubs_end, -sof); - addr = ia64_rse_skip_regs(bsp, ridx + sof); + addr = ia64_rse_skip_regs(bsp, ridx); DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr); @@ -368,26 +373,22 @@ long sof = (regs->cr_ifs) & 0x7f; long sor = 8 * ((regs->cr_ifs >> 14) & 0xf); long rrb_gr = (regs->cr_ifs >> 18) & 0x7f; - long ridx; + long ridx = r1 - 32; - if ((r1 - 32) > sor) - ridx = -sof + (r1 - 32); - else if ((r1 - 32) < (sor - rrb_gr)) - ridx = -sof + (r1 - 32) + rrb_gr; - else - ridx = -sof + (r1 - 32) - (sor - rrb_gr); + if (ridx >= sof) { + /* read of out-of-frame register returns an undefined value; 0 in our case. */ + DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof); + goto fail; + } + + if (ridx < sor) + ridx = rotate_reg(sor, rrb_gr, ridx); DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n", r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx); - if ((r1 - 32) >= sof) { - /* this should never happen, as the "rsvd register fault" has higher priority */ - DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof); - return; - } - on_kbs = ia64_rse_num_regs(kbs, (unsigned long *) sw->ar_bspstore); - addr = ia64_rse_skip_regs((unsigned long *) sw->ar_bspstore, ridx); + addr = ia64_rse_skip_regs((unsigned long *) sw->ar_bspstore, -sof + ridx); if (addr >= kbs) { /* the register is on the kernel backing store: easy... */ *val = *addr; @@ -401,19 +402,15 @@ return; } - /* - * Avoid using user_mode() here: with "epc", we cannot use the privilege level to - * infer whether the interrupt task was running on the kernel backing store. - */ - if (regs->r12 >= TASK_SIZE) { + if (!user_stack(current, regs)) { DPRINT("ignoring kernel read of r%lu; register isn't on the RBS!", r1); - return; + goto fail; } bspstore = (unsigned long *)regs->ar_bspstore; ubs_end = ia64_rse_skip_regs(bspstore, on_kbs); bsp = ia64_rse_skip_regs(ubs_end, -sof); - addr = ia64_rse_skip_regs(bsp, ridx + sof); + addr = ia64_rse_skip_regs(bsp, ridx); DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr); @@ -428,6 +425,13 @@ ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, &rnats); *nat = (rnats & nat_mask) != 0; } + return; + + fail: + *val = 0; + if (nat) + *nat = 0; + return; } @@ -486,7 +490,16 @@ DPRINT("*0x%lx=0x%lx NaT=%d new unat: %p=%lx\n", addr, val, nat, (void *) unat,*unat); } -#define IA64_FPH_OFFS(r) (r - IA64_FIRST_ROTATING_FR) +/* + * Return the (rotated) index for floating point register REGNUM (REGNUM must be in the + * range from 32-127, result is in the range from 0-95. + */ +static inline unsigned long +fph_index (struct pt_regs *regs, long regnum) +{ + unsigned long rrb_fr = (regs->cr_ifs >> 25) & 0x7f; + return rotate_reg(96, rrb_fr, (regnum - IA64_FIRST_ROTATING_FR)); +} static void setfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs) @@ -507,7 +520,7 @@ */ if (regnum >= IA64_FIRST_ROTATING_FR) { ia64_sync_fph(current); - current->thread.fph[IA64_FPH_OFFS(regnum)] = *fpval; + current->thread.fph[fph_index(regs, regnum)] = *fpval; } else { /* * pt_regs or switch_stack ? @@ -566,7 +579,7 @@ */ if (regnum >= IA64_FIRST_ROTATING_FR) { ia64_flush_fph(current); - *fpval = current->thread.fph[IA64_FPH_OFFS(regnum)]; + *fpval = current->thread.fph[fph_index(regs, regnum)]; } else { /* * f0 = 0.0, f1= 1.0. Those registers are constant and are thus @@ -651,8 +664,8 @@ * just in case. */ if (ld.x6_op == 1 || ld.x6_op == 3) { - printk("%s %s: register update on speculative load, error\n", KERN_ERR, __FUNCTION__); - die_if_kernel("unaligned reference on specualtive load with register update\n", + printk(KERN_ERR "%s: register update on speculative load, error\n", __FUNCTION__); + die_if_kernel("unaligned reference on speculative load with register update\n", regs, 30); } @@ -1081,8 +1094,8 @@ * For this reason we keep this sanity check */ if (ld.x6_op == 1 || ld.x6_op == 3) - printk("%s %s: register update on speculative load pair, " - "error\n",KERN_ERR, __FUNCTION__); + printk(KERN_ERR "%s: register update on speculative load pair, error\n", + __FUNCTION__); setreg(ld.r3, ifa, 0, regs); } diff -Nru a/arch/ia64/mm/Makefile b/arch/ia64/mm/Makefile --- a/arch/ia64/mm/Makefile Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/mm/Makefile Wed Jan 15 16:57:28 2003 @@ -1,13 +1,9 @@ # # Makefile for the ia64-specific parts of the memory manager. # -# Note! Dependencies are done automagically by 'make dep', which also -# removes any old dependencies. DON'T put your own dependencies here -# unless it's something special (ie not a .c file). -# -# Note 2! The CFLAGS definition is now in the main makefile... -obj-y := init.o fault.o tlb.o extable.o +obj-y := init.o fault.o tlb.o extable.o + obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o -obj-$(CONFIG_NUMA) += numa.o +obj-$(CONFIG_NUMA) += numa.o obj-$(CONFIG_DISCONTIGMEM) += discontig.o diff -Nru a/arch/ia64/mm/fault.c b/arch/ia64/mm/fault.c --- a/arch/ia64/mm/fault.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/mm/fault.c Wed Jan 15 16:57:29 2003 @@ -58,6 +58,18 @@ if (in_interrupt() || !mm) goto no_context; +#ifdef CONFIG_VIRTUAL_MEM_MAP + /* + * If fault is in region 5 and we are in the kernel, we may already + * have the mmap_sem (pfn_valid macro is called during mmap). There + * is no vma for region 5 addr's anyway, so skip getting the semaphore + * and go directly to the exception handling code. + */ + + if ((REGION_NUMBER(address) == 5) && !user_mode(regs)) + goto bad_area_no_up; +#endif + down_read(&mm->mmap_sem); vma = find_vma_prev(mm, address, &prev_vma); @@ -96,13 +108,13 @@ * fault. */ switch (handle_mm_fault(mm, vma, address, (mask & VM_WRITE) != 0)) { - case 1: + case VM_FAULT_MINOR: ++current->min_flt; break; - case 2: + case VM_FAULT_MAJOR: ++current->maj_flt; break; - case 0: + case VM_FAULT_SIGBUS: /* * We ran out of memory, or some other thing happened * to us that made us unable to handle the page fault @@ -110,8 +122,10 @@ */ signal = SIGBUS; goto bad_area; - default: + case VM_FAULT_OOM: goto out_of_memory; + default: + BUG(); } up_read(&mm->mmap_sem); return; @@ -137,6 +151,9 @@ bad_area: up_read(&mm->mmap_sem); +#ifdef CONFIG_VIRTUAL_MEM_MAP + bad_area_no_up: +#endif if ((isr & IA64_ISR_SP) || ((isr & IA64_ISR_NA) && (isr & IA64_ISR_CODE_MASK) == IA64_ISR_CODE_LFETCH)) { diff -Nru a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c --- a/arch/ia64/mm/init.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/mm/init.c Wed Jan 15 16:57:29 2003 @@ -38,6 +38,13 @@ unsigned long MAX_DMA_ADDRESS = PAGE_OFFSET + 0x100000000UL; +#ifdef CONFIG_VIRTUAL_MEM_MAP +# define LARGE_GAP 0x40000000 /* Use virtual mem map if hole is > than this */ + unsigned long vmalloc_end = VMALLOC_END_INIT; + static struct page *vmem_map; + static unsigned long num_dma_physpages; +#endif + static int pgt_cache_water[2] = { 25, 50 }; void @@ -338,6 +345,144 @@ ia64_tlb_init(); } +#ifdef CONFIG_VIRTUAL_MEM_MAP + +static int +create_mem_map_page_table (u64 start, u64 end, void *arg) +{ + unsigned long address, start_page, end_page; + struct page *map_start, *map_end; + pgd_t *pgd; + pmd_t *pmd; + pte_t *pte; + + map_start = vmem_map + (__pa(start) >> PAGE_SHIFT); + map_end = vmem_map + (__pa(end) >> PAGE_SHIFT); + + start_page = (unsigned long) map_start & PAGE_MASK; + end_page = PAGE_ALIGN((unsigned long) map_end); + + for (address = start_page; address < end_page; address += PAGE_SIZE) { + pgd = pgd_offset_k(address); + if (pgd_none(*pgd)) + pgd_populate(&init_mm, pgd, alloc_bootmem_pages(PAGE_SIZE)); + pmd = pmd_offset(pgd, address); + + if (pmd_none(*pmd)) + pmd_populate_kernel(&init_mm, pmd, alloc_bootmem_pages(PAGE_SIZE)); + pte = pte_offset_kernel(pmd, address); + + if (pte_none(*pte)) + set_pte(pte, pfn_pte(__pa(alloc_bootmem_pages(PAGE_SIZE)) >> PAGE_SHIFT, + PAGE_KERNEL)); + } + return 0; +} + +struct memmap_init_callback_data { + memmap_init_callback_t *memmap_init; + struct page *start; + struct page *end; + int nid; + unsigned long zone; +}; + +static int +virtual_memmap_init (u64 start, u64 end, void *arg) +{ + struct memmap_init_callback_data *args; + struct page *map_start, *map_end; + + args = (struct memmap_init_callback_data *) arg; + + map_start = vmem_map + (__pa(start) >> PAGE_SHIFT); + map_end = vmem_map + (__pa(end) >> PAGE_SHIFT); + + if (map_start < args->start) + map_start = args->start; + if (map_end > args->end) + map_end = args->end; + + /* + * We have to initialize "out of bounds" struct page elements + * that fit completely on the same pages that were allocated + * for the "in bounds" elements because they may be referenced + * later (and found to be "reserved"). + */ + + map_start -= ((unsigned long) map_start & (PAGE_SIZE - 1)) / sizeof(struct page); + map_end += ((PAGE_ALIGN((unsigned long) map_end) - (unsigned long) map_end) + / sizeof(struct page)); + + if (map_start < map_end) + (*args->memmap_init)(map_start, (unsigned long)(map_end - map_start), + args->nid,args->zone,page_to_pfn(map_start)); + return 0; +} + +void +arch_memmap_init (memmap_init_callback_t *memmap_init, + struct page *start, unsigned long size, int nid, + unsigned long zone, unsigned long start_pfn) +{ + if (!vmem_map) + memmap_init(start,size,nid,zone,start_pfn); + else { + struct memmap_init_callback_data args; + + args.memmap_init = memmap_init; + args.start = start; + args.end = start + size; + args.nid = nid; + args.zone = zone; + + efi_memmap_walk(virtual_memmap_init, &args); + } +} + +int +ia64_pfn_valid (unsigned long pfn) +{ + char byte; + + return __get_user(byte, (char *) pfn_to_page(pfn)) == 0; +} + +static int +count_dma_pages (u64 start, u64 end, void *arg) +{ + unsigned long *count = arg; + + if (end <= MAX_DMA_ADDRESS) + *count += (end - start) >> PAGE_SHIFT; + return 0; +} + +static int +find_largest_hole (u64 start, u64 end, void *arg) +{ + u64 *max_gap = arg; + + static u64 last_end = PAGE_OFFSET; + + /* NOTE: this algorithm assumes efi memmap table is ordered */ + + if (*max_gap < (start - last_end)) + *max_gap = start - last_end; + last_end = end; + return 0; +} +#endif /* CONFIG_VIRTUAL_MEM_MAP */ + +static int +count_pages (u64 start, u64 end, void *arg) +{ + unsigned long *count = arg; + + *count += (end - start) >> PAGE_SHIFT; + return 0; +} + /* * Set up the page tables. */ @@ -356,18 +501,71 @@ extern void discontig_paging_init(void); discontig_paging_init(); + efi_memmap_walk(count_pages, &num_physpages); } #else /* !CONFIG_DISCONTIGMEM */ void paging_init (void) { - unsigned long max_dma, zones_size[MAX_NR_ZONES]; + unsigned long max_dma; + unsigned long zones_size[MAX_NR_ZONES]; +# ifdef CONFIG_VIRTUAL_MEM_MAP + unsigned long zholes_size[MAX_NR_ZONES]; + unsigned long max_gap; +# endif /* initialize mem_map[] */ memset(zones_size, 0, sizeof(zones_size)); + num_physpages = 0; + efi_memmap_walk(count_pages, &num_physpages); + max_dma = virt_to_phys((void *) MAX_DMA_ADDRESS) >> PAGE_SHIFT; + +# ifdef CONFIG_VIRTUAL_MEM_MAP + memset(zholes_size, 0, sizeof(zholes_size)); + + num_dma_physpages = 0; + efi_memmap_walk(count_dma_pages, &num_dma_physpages); + + if (max_low_pfn < max_dma) { + zones_size[ZONE_DMA] = max_low_pfn; + zholes_size[ZONE_DMA] = max_low_pfn - num_dma_physpages; + } + else { + zones_size[ZONE_DMA] = max_dma; + zholes_size[ZONE_DMA] = max_dma - num_dma_physpages; + if (num_physpages > num_dma_physpages) { + zones_size[ZONE_NORMAL] = max_low_pfn - max_dma; + zholes_size[ZONE_NORMAL] = ((max_low_pfn - max_dma) + - (num_physpages - num_dma_physpages)); + } + } + + max_gap = 0; + efi_memmap_walk(find_largest_hole, (u64 *)&max_gap); + if (max_gap < LARGE_GAP) { + vmem_map = (struct page *) 0; + free_area_init_node(0, &contig_page_data, NULL, zones_size, 0, zholes_size); + mem_map = contig_page_data.node_mem_map; + } + else { + unsigned long map_size; + + /* allocate virtual_mem_map */ + + map_size = PAGE_ALIGN(max_low_pfn * sizeof(struct page)); + vmalloc_end -= map_size; + vmem_map = (struct page *) vmalloc_end; + efi_memmap_walk(create_mem_map_page_table, 0); + + free_area_init_node(0, &contig_page_data, vmem_map, zones_size, 0, zholes_size); + + mem_map = contig_page_data.node_mem_map; + printk("Virtual mem_map starts at 0x%p\n", mem_map); + } +# else /* !CONFIG_VIRTUAL_MEM_MAP */ if (max_low_pfn < max_dma) zones_size[ZONE_DMA] = max_low_pfn; else { @@ -375,19 +573,11 @@ zones_size[ZONE_NORMAL] = max_low_pfn - max_dma; } free_area_init(zones_size); +# endif /* !CONFIG_VIRTUAL_MEM_MAP */ } #endif /* !CONFIG_DISCONTIGMEM */ static int -count_pages (u64 start, u64 end, void *arg) -{ - unsigned long *count = arg; - - *count += (end - start) >> PAGE_SHIFT; - return 0; -} - -static int count_reserved_pages (u64 start, u64 end, void *arg) { unsigned long num_reserved = 0; @@ -422,9 +612,6 @@ BUG(); max_mapnr = max_low_pfn; #endif - - num_physpages = 0; - efi_memmap_walk(count_pages, &num_physpages); high_memory = __va(max_low_pfn * PAGE_SIZE); diff -Nru a/arch/ia64/mm/tlb.c b/arch/ia64/mm/tlb.c --- a/arch/ia64/mm/tlb.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/mm/tlb.c Wed Jan 15 16:57:29 2003 @@ -84,7 +84,7 @@ for (i = 0; i < NR_CPUS; ++i) if (i != smp_processor_id()) per_cpu(ia64_need_tlb_flush, i) = 1; - __flush_tlb_all(); + local_flush_tlb_all(); } void @@ -108,7 +108,7 @@ } void -__flush_tlb_all (void) +local_flush_tlb_all (void) { unsigned long i, j, flags, count0, count1, stride0, stride1, addr; @@ -194,5 +194,5 @@ local_cpu_data->ptce_stride[0] = ptce_info.stride[0]; local_cpu_data->ptce_stride[1] = ptce_info.stride[1]; - __flush_tlb_all(); /* nuke left overs from bootstrapping... */ + local_flush_tlb_all(); /* nuke left overs from bootstrapping... */ } diff -Nru a/arch/ia64/pci/Makefile b/arch/ia64/pci/Makefile --- a/arch/ia64/pci/Makefile Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/pci/Makefile Wed Jan 15 16:57:29 2003 @@ -1 +1,4 @@ +# +# Makefile for the ia64-specific parts of the pci bus +# obj-y := pci.o diff -Nru a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c --- a/arch/ia64/pci/pci.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/pci/pci.c Wed Jan 15 16:57:29 2003 @@ -44,10 +44,6 @@ #define DBG(x...) #endif -#ifdef CONFIG_IA64_MCA -extern void ia64_mca_check_errors( void ); -#endif - struct pci_fixup pcibios_fixups[1]; /* diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-bigsur-mp b/arch/ia64/sn/configs/sn1/defconfig-bigsur-mp --- a/arch/ia64/sn/configs/sn1/defconfig-bigsur-mp Wed Jan 15 16:57:28 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,765 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -# CONFIG_IA64_GENERIC is not set -CONFIG_IA64_DIG=y -# CONFIG_IA64_HP_SIM is not set -# CONFIG_IA64_SGI_SN1 is not set -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=6 -# CONFIG_NUMA is not set -# CONFIG_IA64_MCA is not set -CONFIG_PM=y -CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_DEBUG=y -CONFIG_KCORE_ELF=y -CONFIG_SMP=y -CONFIG_IA32_SUPPORT=y -CONFIG_PERFMON=y -CONFIG_IA64_PALINFO=y -# CONFIG_EFI_VARS is not set -CONFIG_NET=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Networking options -# -# CONFIG_PACKET is not set -# CONFIG_NETLINK is not set -# CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_INET_ECN is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set - -# -# -# -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_LLC is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_FASTROUTE is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set -# CONFIG_PNPBIOS is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_LAN is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDETAPE is not set -CONFIG_BLK_DEV_IDEFLOPPY=y -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDEPCI_SHARE_IRQ is not set -CONFIG_BLK_DEV_IDEDMA_PCI=y -CONFIG_BLK_DEV_ADMA=y -# CONFIG_BLK_DEV_OFFBOARD is not set -# CONFIG_IDEDMA_PCI_AUTO is not set -CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set -# CONFIG_BLK_DEV_AEC62XX is not set -# CONFIG_AEC62XX_TUNING is not set -# CONFIG_BLK_DEV_ALI15X3 is not set -# CONFIG_WDC_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set -# CONFIG_AMD74XX_OVERRIDE is not set -# CONFIG_BLK_DEV_CMD64X is not set -# CONFIG_BLK_DEV_CY82C693 is not set -# CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set -# CONFIG_HPT34X_AUTODMA is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_PIIX is not set -# CONFIG_PIIX_TUNING is not set -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_OPTI621 is not set -# CONFIG_BLK_DEV_PDC202XX is not set -# CONFIG_PDC202XX_BURST is not set -# CONFIG_PDC202XX_FORCE is not set -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SIS5513 is not set -# CONFIG_BLK_DEV_TRM290 is not set -# CONFIG_BLK_DEV_VIA82CXXX is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_IDEDMA_IVB is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -# CONFIG_XSCSI is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_NCR53C8XX is not set -# CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -# CONFIG_SCSI_QLOGIC_FC is not set -CONFIG_SCSI_QLOGIC_1280=y -# CONFIG_SCSI_QLOGIC_QLA2100 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set -CONFIG_DUMMY=y -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_SUNLANCE is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_APRICOT is not set -# CONFIG_CS89x0 is not set -# CONFIG_TULIP is not set -# CONFIG_DE4X5 is not set -# CONFIG_DGRS is not set -# CONFIG_DM9102 is not set -CONFIG_EEPRO100=y -# CONFIG_LNE390 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_NE3210 is not set -# CONFIG_ES3210 is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_8139TOO_PIO is not set -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139TOO_8129 is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_NET_POCKET is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_SERIAL_CONSOLE=y -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -CONFIG_MOUSE=y -CONFIG_PSMOUSE=y -# CONFIG_82C710_MOUSE is not set -# CONFIG_PC110_PAD is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_EFI_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -# CONFIG_QUOTA is not set -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -# CONFIG_UMSDOS_FS is not set -CONFIG_VFAT_FS=y -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_MOUNT=y -CONFIG_DEVFS_DEBUG=y -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_XFS_SUPPORT is not set - -# -# Network File Systems -# -# CONFIG_CODA_FS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_ROOT_NFS is not set -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -CONFIG_SUNRPC=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -# CONFIG_SMB_FS is not set -# CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -CONFIG_NLS=y - -# -# Native Language Support -# -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Console drivers -# -CONFIG_VGA_CONSOLE=y - -# -# Frame-buffer support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# IEEE 1394 (FireWire) support (EXPERIMENTAL) -# -# CONFIG_IEEE1394 is not set - -# -# Bluetooth support -# -# CONFIG_BT is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -CONFIG_KDB=y -CONFIG_KDB_MODULES=y -# CONFIG_KDB_OFF is not set - -# -# Load all symbols for debugging is required for KDB -# -CONFIG_KALLSYMS=y diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-bigsur-sp b/arch/ia64/sn/configs/sn1/defconfig-bigsur-sp --- a/arch/ia64/sn/configs/sn1/defconfig-bigsur-sp Wed Jan 15 16:57:28 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,760 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -# CONFIG_IA64_GENERIC is not set -CONFIG_IA64_DIG=y -# CONFIG_IA64_HP_SIM is not set -# CONFIG_IA64_SGI_SN1 is not set -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=6 -# CONFIG_NUMA is not set -# CONFIG_IA64_MCA is not set -CONFIG_PM=y -CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_DEBUG=y -CONFIG_KCORE_ELF=y -# CONFIG_SMP is not set -CONFIG_IA32_SUPPORT=y -CONFIG_PERFMON=y -CONFIG_IA64_PALINFO=y -# CONFIG_EFI_VARS is not set -CONFIG_NET=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Networking options -# -# CONFIG_PACKET is not set -# CONFIG_NETLINK is not set -# CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_INET_ECN is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set - -# -# -# -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_LLC is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_FASTROUTE is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set -# CONFIG_PNPBIOS is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_LAN is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -CONFIG_BLK_DEV_IDECD=y -# CONFIG_BLK_DEV_IDETAPE is not set -CONFIG_BLK_DEV_IDEFLOPPY=y -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDEPCI_SHARE_IRQ is not set -CONFIG_BLK_DEV_IDEDMA_PCI=y -CONFIG_BLK_DEV_ADMA=y -# CONFIG_BLK_DEV_OFFBOARD is not set -# CONFIG_IDEDMA_PCI_AUTO is not set -CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set -# CONFIG_BLK_DEV_AEC62XX is not set -# CONFIG_AEC62XX_TUNING is not set -# CONFIG_BLK_DEV_ALI15X3 is not set -# CONFIG_WDC_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set -# CONFIG_AMD74XX_OVERRIDE is not set -# CONFIG_BLK_DEV_CMD64X is not set -# CONFIG_BLK_DEV_CY82C693 is not set -# CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set -# CONFIG_HPT34X_AUTODMA is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_PIIX is not set -# CONFIG_PIIX_TUNING is not set -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_OPTI621 is not set -# CONFIG_BLK_DEV_PDC202XX is not set -# CONFIG_PDC202XX_BURST is not set -# CONFIG_PDC202XX_FORCE is not set -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SIS5513 is not set -# CONFIG_BLK_DEV_TRM290 is not set -# CONFIG_BLK_DEV_VIA82CXXX is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_IDEDMA_IVB is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -# CONFIG_XSCSI is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_NCR53C8XX is not set -# CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -# CONFIG_SCSI_QLOGIC_FC is not set -CONFIG_SCSI_QLOGIC_1280=y -# CONFIG_SCSI_QLOGIC_QLA2100 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set -CONFIG_DUMMY=y -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_SUNLANCE is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_APRICOT is not set -# CONFIG_CS89x0 is not set -# CONFIG_TULIP is not set -# CONFIG_DE4X5 is not set -# CONFIG_DGRS is not set -# CONFIG_DM9102 is not set -CONFIG_EEPRO100=y -# CONFIG_LNE390 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_NE3210 is not set -# CONFIG_ES3210 is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_8139TOO_PIO is not set -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139TOO_8129 is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_NET_POCKET is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_SERIAL_CONSOLE=y -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -CONFIG_MOUSE=y -CONFIG_PSMOUSE=y -# CONFIG_82C710_MOUSE is not set -# CONFIG_PC110_PAD is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_EFI_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -# CONFIG_QUOTA is not set -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -# CONFIG_UMSDOS_FS is not set -CONFIG_VFAT_FS=y -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_MOUNT=y -CONFIG_DEVFS_DEBUG=y -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_XFS_SUPPORT is not set - -# -# Network File Systems -# -# CONFIG_CODA_FS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_ROOT_NFS is not set -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -CONFIG_SUNRPC=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -# CONFIG_SMB_FS is not set -# CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -CONFIG_NLS=y - -# -# Native Language Support -# -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Console drivers -# -CONFIG_VGA_CONSOLE=y - -# -# Frame-buffer support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# IEEE 1394 (FireWire) support (EXPERIMENTAL) -# -# CONFIG_IEEE1394 is not set - -# -# Bluetooth support -# -# CONFIG_BT is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_KDB is not set -# CONFIG_KDB_MODULES is not set -# CONFIG_KALLSYMS is not set diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-dig-mp b/arch/ia64/sn/configs/sn1/defconfig-dig-mp --- a/arch/ia64/sn/configs/sn1/defconfig-dig-mp Wed Jan 15 16:57:29 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,449 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -# CONFIG_EXPERIMENTAL is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -# CONFIG_IA64_GENERIC is not set -CONFIG_IA64_DIG=y -# CONFIG_IA64_HP_SIM is not set -# CONFIG_IA64_SGI_SN1 is not set -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=6 -# CONFIG_NUMA is not set -# CONFIG_IA64_MCA is not set -CONFIG_PM=y -CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y -# CONFIG_DEVFS_FS is not set -CONFIG_KCORE_ELF=y -CONFIG_SMP=y -# CONFIG_IA32_SUPPORT is not set -# CONFIG_PERFMON is not set -# CONFIG_IA64_PALINFO is not set -# CONFIG_EFI_VARS is not set -# CONFIG_NET is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -# CONFIG_XSCSI is not set - -# -# SCSI support -# -# CONFIG_SCSI is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_SERIAL is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_EFI_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_XFS_SUPPORT is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_SMB_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set - -# -# Console drivers -# -CONFIG_VGA_CONSOLE=y - -# -# Frame-buffer support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# - -# -# Networking support is needed for USB Networking device support -# - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_KDB is not set -# CONFIG_KDB_MODULES is not set -# CONFIG_KALLSYMS is not set diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-dig-sp b/arch/ia64/sn/configs/sn1/defconfig-dig-sp --- a/arch/ia64/sn/configs/sn1/defconfig-dig-sp Wed Jan 15 16:57:29 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,449 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -# CONFIG_EXPERIMENTAL is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -# CONFIG_IA64_GENERIC is not set -CONFIG_IA64_DIG=y -# CONFIG_IA64_HP_SIM is not set -# CONFIG_IA64_SGI_SN1 is not set -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=6 -# CONFIG_NUMA is not set -# CONFIG_IA64_MCA is not set -CONFIG_PM=y -CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y -# CONFIG_DEVFS_FS is not set -CONFIG_KCORE_ELF=y -# CONFIG_SMP is not set -# CONFIG_IA32_SUPPORT is not set -# CONFIG_PERFMON is not set -# CONFIG_IA64_PALINFO is not set -# CONFIG_EFI_VARS is not set -# CONFIG_NET is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -# CONFIG_XSCSI is not set - -# -# SCSI support -# -# CONFIG_SCSI is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_SERIAL is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_EFI_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_XFS_SUPPORT is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_SMB_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set - -# -# Console drivers -# -CONFIG_VGA_CONSOLE=y - -# -# Frame-buffer support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# - -# -# Networking support is needed for USB Networking device support -# - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_KDB is not set -# CONFIG_KDB_MODULES is not set -# CONFIG_KALLSYMS is not set diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-generic-mp b/arch/ia64/sn/configs/sn1/defconfig-generic-mp --- a/arch/ia64/sn/configs/sn1/defconfig-generic-mp Wed Jan 15 16:57:29 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,450 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -# CONFIG_EXPERIMENTAL is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -CONFIG_IA64_GENERIC=y -# CONFIG_IA64_DIG is not set -# CONFIG_IA64_HP_SIM is not set -# CONFIG_IA64_SGI_SN1 is not set -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=6 -CONFIG_KCORE_ELF=y -CONFIG_SMP=y -# CONFIG_IA32_SUPPORT is not set -CONFIG_PERFMON=y -CONFIG_IA64_PALINFO=y -# CONFIG_EFI_VARS is not set -# CONFIG_NET is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -# CONFIG_XSCSI is not set - -# -# SCSI support -# -# CONFIG_SCSI is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_SERIAL is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_EFI_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_XFS_SUPPORT is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_SMB_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set - -# -# Console drivers -# -CONFIG_VGA_CONSOLE=y - -# -# Frame-buffer support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# - -# -# Networking support is needed for USB Networking device support -# - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# Simulated drivers -# -# CONFIG_SIMETH is not set -# CONFIG_SIM_SERIAL is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_KDB is not set -# CONFIG_KDB_MODULES is not set -# CONFIG_KALLSYMS is not set diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-generic-sp b/arch/ia64/sn/configs/sn1/defconfig-generic-sp --- a/arch/ia64/sn/configs/sn1/defconfig-generic-sp Wed Jan 15 16:57:29 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,450 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -# CONFIG_EXPERIMENTAL is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -CONFIG_IA64_GENERIC=y -# CONFIG_IA64_DIG is not set -# CONFIG_IA64_HP_SIM is not set -# CONFIG_IA64_SGI_SN1 is not set -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=6 -CONFIG_KCORE_ELF=y -# CONFIG_SMP is not set -# CONFIG_IA32_SUPPORT is not set -CONFIG_PERFMON=y -CONFIG_IA64_PALINFO=y -# CONFIG_EFI_VARS is not set -# CONFIG_NET is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -# CONFIG_XSCSI is not set - -# -# SCSI support -# -# CONFIG_SCSI is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_SERIAL is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_EFI_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_XFS_SUPPORT is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_SMB_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set - -# -# Console drivers -# -CONFIG_VGA_CONSOLE=y - -# -# Frame-buffer support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# - -# -# Networking support is needed for USB Networking device support -# - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# Simulated drivers -# -# CONFIG_SIMETH is not set -# CONFIG_SIM_SERIAL is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_KDB is not set -# CONFIG_KDB_MODULES is not set -# CONFIG_KALLSYMS is not set diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-hp-sp b/arch/ia64/sn/configs/sn1/defconfig-hp-sp --- a/arch/ia64/sn/configs/sn1/defconfig-hp-sp Wed Jan 15 16:57:29 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,335 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -# CONFIG_EXPERIMENTAL is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -# CONFIG_IA64_GENERIC is not set -# CONFIG_IA64_DIG is not set -CONFIG_IA64_HP_SIM=y -# CONFIG_IA64_SGI_SN1 is not set -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=6 -CONFIG_KCORE_ELF=y -# CONFIG_SMP is not set -# CONFIG_IA32_SUPPORT is not set -# CONFIG_PERFMON is not set -# CONFIG_IA64_PALINFO is not set -# CONFIG_EFI_VARS is not set -CONFIG_NET=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set - -# -# Networking options -# -# CONFIG_PACKET is not set -# CONFIG_NETLINK is not set -# CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_INET_ECN is not set -# CONFIG_SYN_COOKIES is not set - -# -# -# -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -# CONFIG_XSCSI is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_PPA is not set -# CONFIG_SCSI_IMM is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_SERIAL is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 -# CONFIG_PRINTER is not set -# CONFIG_PPDEV is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -CONFIG_EFI_RTC=y -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_XFS_SUPPORT is not set - -# -# Network File Systems -# -# CONFIG_CODA_FS is not set -# CONFIG_NFS_FS is not set -# CONFIG_NFS_V3 is not set -# CONFIG_ROOT_NFS is not set -# CONFIG_NFSD is not set -# CONFIG_NFSD_V3 is not set -# CONFIG_SUNRPC is not set -# CONFIG_LOCKD is not set -# CONFIG_SMB_FS is not set -# CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set - -# -# Console drivers -# -CONFIG_VGA_CONSOLE=y - -# -# Frame-buffer support -# -# CONFIG_FB is not set - -# -# Simulated drivers -# -CONFIG_SIMETH=y -CONFIG_SIM_SERIAL=y -CONFIG_SCSI_SIM=y - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_KDB is not set -# CONFIG_KDB_MODULES is not set -# CONFIG_KALLSYMS is not set diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-prom-medusa b/arch/ia64/sn/configs/sn1/defconfig-prom-medusa --- a/arch/ia64/sn/configs/sn1/defconfig-prom-medusa Wed Jan 15 16:57:29 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,519 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -# CONFIG_IA64_GENERIC is not set -# CONFIG_IA64_DIG is not set -# CONFIG_IA64_HP_SIM is not set -CONFIG_IA64_SGI_SN1=y -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=7 -CONFIG_IA64_SGI_SN=y -CONFIG_IA64_SGI_SN_DEBUG=y -CONFIG_IA64_SGI_SN_SIM=y -CONFIG_IA64_SGI_AUTOTEST=y -CONFIG_DEVFS_FS=y -# CONFIG_DEVFS_DEBUG is not set -CONFIG_SERIAL_SGI_L1_PROTOCOL=y -CONFIG_DISCONTIGMEM=y -CONFIG_IA64_MCA=y -CONFIG_NUMA=y -CONFIG_PERCPU_IRQ=y -CONFIG_PCIBA=y -CONFIG_KCORE_ELF=y -CONFIG_SMP=y -# CONFIG_IA32_SUPPORT is not set -CONFIG_PERFMON=y -CONFIG_IA64_PALINFO=y -# CONFIG_EFI_VARS is not set -# CONFIG_NET is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set -# CONFIG_PNPBIOS is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -# CONFIG_XSCSI is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_NCR53C8XX is not set -# CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -CONFIG_SCSI_QLOGIC_FC=y -# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLOGIC_QLA2100 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -# CONFIG_VT is not set -CONFIG_SERIAL=y -# CONFIG_SERIAL_CONSOLE is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_EFI_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -CONFIG_DEVFS_FS=y -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_XFS_SUPPORT is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_SMB_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# - -# -# Networking support is needed for USB Networking device support -# - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# IEEE 1394 (FireWire) support (EXPERIMENTAL) -# -# CONFIG_IEEE1394 is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_KDB is not set -# CONFIG_KDB_MODULES is not set -# CONFIG_KALLSYMS is not set diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-sn1-mp b/arch/ia64/sn/configs/sn1/defconfig-sn1-mp --- a/arch/ia64/sn/configs/sn1/defconfig-sn1-mp Wed Jan 15 16:57:29 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,726 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -# CONFIG_IA64_GENERIC is not set -# CONFIG_IA64_DIG is not set -# CONFIG_IA64_HP_SIM is not set -CONFIG_IA64_SGI_SN1=y -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=7 -CONFIG_IA64_SGI_SN=y -CONFIG_IA64_SGI_SN_DEBUG=y -CONFIG_IA64_SGI_SN_SIM=y -CONFIG_IA64_SGI_AUTOTEST=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_DEBUG=y -CONFIG_SERIAL_SGI_L1_PROTOCOL=y -CONFIG_DISCONTIGMEM=y -CONFIG_IA64_MCA=y -CONFIG_NUMA=y -CONFIG_PERCPU_IRQ=y -CONFIG_PCIBA=y -CONFIG_KCORE_ELF=y -CONFIG_SMP=y -CONFIG_IA32_SUPPORT=y -CONFIG_PERFMON=y -CONFIG_IA64_PALINFO=y -# CONFIG_EFI_VARS is not set -CONFIG_NET=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK=y -CONFIG_RTNETLINK=y -CONFIG_NETLINK_DEV=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_DEBUG=y -CONFIG_FILTER=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_INET_ECN is not set -CONFIG_SYN_COOKIES=y - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_COMPAT_IPCHAINS is not set -# CONFIG_IP_NF_COMPAT_IPFWADM is not set -# CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set - -# -# -# -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_LLC is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_FASTROUTE is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set -# CONFIG_PNPBIOS is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_LAN is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -CONFIG_XSCSI=y - -# -# Alternate SCSI support -# -CONFIG_XSCSI_DKSC=y -# CONFIG_XSCSI_QLFC is not set -# CONFIG_XSCSI_QL is not set -# CONFIG_XSCSI_SBP2 is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_NCR53C8XX is not set -# CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -CONFIG_SCSI_QLOGIC_FC=y -# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLOGIC_QLA2100 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_SGI_IOC3_ETH=y -# CONFIG_SUNLANCE is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -# CONFIG_VT is not set -CONFIG_SERIAL=y -# CONFIG_SERIAL_CONSOLE is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -CONFIG_EFI_RTC=y -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -CONFIG_QUOTA=y -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -# CONFIG_UMSDOS_FS is not set -CONFIG_VFAT_FS=y -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_MOUNT=y -CONFIG_DEVFS_DEBUG=y -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -CONFIG_XFS_SUPPORT=y - -# -# Network File Systems -# -# CONFIG_CODA_FS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_ROOT_NFS is not set -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -CONFIG_SUNRPC=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -# CONFIG_SMB_FS is not set -# CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -CONFIG_NLS=y - -# -# Native Language Support -# -CONFIG_NLS_DEFAULT="n" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# IEEE 1394 (FireWire) support (EXPERIMENTAL) -# -# CONFIG_IEEE1394 is not set - -# -# Bluetooth support -# -# CONFIG_BT is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -CONFIG_KDB=y -CONFIG_KDB_MODULES=y -# CONFIG_KDB_OFF is not set - -# -# Load all symbols for debugging is required for KDB -# -CONFIG_KALLSYMS=y diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-modules b/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-modules --- a/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-modules Wed Jan 15 16:57:29 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,728 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y - -# -# Loadable module support -# -CONFIG_MODULES=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -# CONFIG_IA64_GENERIC is not set -# CONFIG_IA64_DIG is not set -# CONFIG_IA64_HP_SIM is not set -CONFIG_IA64_SGI_SN1=y -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=7 -CONFIG_IA64_SGI_SN=y -CONFIG_IA64_SGI_SN_DEBUG=y -CONFIG_IA64_SGI_SN_SIM=y -CONFIG_IA64_SGI_AUTOTEST=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_DEBUG=y -CONFIG_SERIAL_SGI_L1_PROTOCOL=y -CONFIG_DISCONTIGMEM=y -CONFIG_IA64_MCA=y -CONFIG_NUMA=y -CONFIG_PERCPU_IRQ=y -CONFIG_PCIBA=y -CONFIG_KCORE_ELF=y -CONFIG_SMP=y -CONFIG_IA32_SUPPORT=y -CONFIG_PERFMON=y -CONFIG_IA64_PALINFO=y -# CONFIG_EFI_VARS is not set -CONFIG_NET=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK=y -CONFIG_RTNETLINK=y -CONFIG_NETLINK_DEV=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_DEBUG=y -CONFIG_FILTER=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_INET_ECN is not set -CONFIG_SYN_COOKIES=y - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_COMPAT_IPCHAINS is not set -# CONFIG_IP_NF_COMPAT_IPFWADM is not set -# CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set - -# -# -# -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_LLC is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_FASTROUTE is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set -# CONFIG_PNPBIOS is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_LAN is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -CONFIG_XSCSI=y - -# -# Alternate SCSI support -# -CONFIG_XSCSI_DKSC=y -# CONFIG_XSCSI_QLFC is not set -# CONFIG_XSCSI_QL is not set -# CONFIG_XSCSI_SBP2 is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_NCR53C8XX is not set -# CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -CONFIG_SCSI_QLOGIC_FC=y -# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLOGIC_QLA2100 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_SGI_IOC3_ETH=y -# CONFIG_SUNLANCE is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -# CONFIG_VT is not set -CONFIG_SERIAL=y -# CONFIG_SERIAL_CONSOLE is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -CONFIG_EFI_RTC=y -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -CONFIG_QUOTA=y -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -# CONFIG_UMSDOS_FS is not set -CONFIG_VFAT_FS=y -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_MOUNT=y -CONFIG_DEVFS_DEBUG=y -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -CONFIG_XFS_SUPPORT=y - -# -# Network File Systems -# -# CONFIG_CODA_FS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_ROOT_NFS is not set -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -CONFIG_SUNRPC=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -# CONFIG_SMB_FS is not set -# CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -CONFIG_NLS=y - -# -# Native Language Support -# -CONFIG_NLS_DEFAULT="n" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# IEEE 1394 (FireWire) support (EXPERIMENTAL) -# -# CONFIG_IEEE1394 is not set - -# -# Bluetooth support -# -# CONFIG_BT is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -CONFIG_KDB=y -CONFIG_KDB_MODULES=y -# CONFIG_KDB_OFF is not set - -# -# Load all symbols for debugging is required for KDB -# -CONFIG_KALLSYMS=y diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-syn1-0 b/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-syn1-0 --- a/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-syn1-0 Wed Jan 15 16:57:29 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,726 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -# CONFIG_IA64_GENERIC is not set -# CONFIG_IA64_DIG is not set -# CONFIG_IA64_HP_SIM is not set -CONFIG_IA64_SGI_SN1=y -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=7 -CONFIG_IA64_SGI_SN=y -CONFIG_IA64_SGI_SN_DEBUG=y -CONFIG_IA64_SGI_SN_SIM=y -CONFIG_IA64_SGI_AUTOTEST=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_DEBUG=y -CONFIG_SERIAL_SGI_L1_PROTOCOL=y -CONFIG_DISCONTIGMEM=y -CONFIG_IA64_MCA=y -CONFIG_NUMA=y -CONFIG_PERCPU_IRQ=y -CONFIG_PCIBA=y -CONFIG_KCORE_ELF=y -CONFIG_SMP=y -CONFIG_IA32_SUPPORT=y -CONFIG_PERFMON=y -CONFIG_IA64_PALINFO=y -# CONFIG_EFI_VARS is not set -CONFIG_NET=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK=y -CONFIG_RTNETLINK=y -CONFIG_NETLINK_DEV=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_DEBUG=y -CONFIG_FILTER=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_INET_ECN is not set -CONFIG_SYN_COOKIES=y - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_COMPAT_IPCHAINS is not set -# CONFIG_IP_NF_COMPAT_IPFWADM is not set -# CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set - -# -# -# -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_LLC is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_FASTROUTE is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set -# CONFIG_PNPBIOS is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_LAN is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -CONFIG_XSCSI=y - -# -# Alternate SCSI support -# -CONFIG_XSCSI_DKSC=y -# CONFIG_XSCSI_QLFC is not set -# CONFIG_XSCSI_QL is not set -# CONFIG_XSCSI_SBP2 is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_NCR53C8XX is not set -# CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -CONFIG_SCSI_QLOGIC_FC=y -# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLOGIC_QLA2100 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_SGI_IOC3_ETH=y -# CONFIG_SUNLANCE is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -# CONFIG_VT is not set -CONFIG_SERIAL=y -# CONFIG_SERIAL_CONSOLE is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -CONFIG_EFI_RTC=y -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -CONFIG_QUOTA=y -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -# CONFIG_UMSDOS_FS is not set -CONFIG_VFAT_FS=y -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_MOUNT=y -CONFIG_DEVFS_DEBUG=y -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -CONFIG_XFS_SUPPORT=y - -# -# Network File Systems -# -# CONFIG_CODA_FS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_ROOT_NFS is not set -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -CONFIG_SUNRPC=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -# CONFIG_SMB_FS is not set -# CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -CONFIG_NLS=y - -# -# Native Language Support -# -CONFIG_NLS_DEFAULT="n" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# IEEE 1394 (FireWire) support (EXPERIMENTAL) -# -# CONFIG_IEEE1394 is not set - -# -# Bluetooth support -# -# CONFIG_BT is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -CONFIG_KDB=y -CONFIG_KDB_MODULES=y -# CONFIG_KDB_OFF is not set - -# -# Load all symbols for debugging is required for KDB -# -CONFIG_KALLSYMS=y diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-sn1-sp b/arch/ia64/sn/configs/sn1/defconfig-sn1-sp --- a/arch/ia64/sn/configs/sn1/defconfig-sn1-sp Wed Jan 15 16:57:28 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,726 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -# CONFIG_IA64_GENERIC is not set -# CONFIG_IA64_DIG is not set -# CONFIG_IA64_HP_SIM is not set -CONFIG_IA64_SGI_SN1=y -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=7 -CONFIG_IA64_SGI_SN=y -CONFIG_IA64_SGI_SN_DEBUG=y -CONFIG_IA64_SGI_SN_SIM=y -CONFIG_IA64_SGI_AUTOTEST=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_DEBUG=y -CONFIG_SERIAL_SGI_L1_PROTOCOL=y -CONFIG_DISCONTIGMEM=y -CONFIG_IA64_MCA=y -CONFIG_NUMA=y -CONFIG_PERCPU_IRQ=y -CONFIG_PCIBA=y -CONFIG_KCORE_ELF=y -# CONFIG_SMP is not set -CONFIG_IA32_SUPPORT=y -CONFIG_PERFMON=y -CONFIG_IA64_PALINFO=y -# CONFIG_EFI_VARS is not set -CONFIG_NET=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK=y -CONFIG_RTNETLINK=y -CONFIG_NETLINK_DEV=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_DEBUG=y -CONFIG_FILTER=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_INET_ECN is not set -CONFIG_SYN_COOKIES=y - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_COMPAT_IPCHAINS is not set -# CONFIG_IP_NF_COMPAT_IPFWADM is not set -# CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set - -# -# -# -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_LLC is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_FASTROUTE is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set -# CONFIG_PNPBIOS is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_LAN is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -CONFIG_XSCSI=y - -# -# Alternate SCSI support -# -CONFIG_XSCSI_DKSC=y -# CONFIG_XSCSI_QLFC is not set -# CONFIG_XSCSI_QL is not set -# CONFIG_XSCSI_SBP2 is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_NCR53C8XX is not set -# CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -CONFIG_SCSI_QLOGIC_FC=y -# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLOGIC_QLA2100 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_SGI_IOC3_ETH=y -# CONFIG_SUNLANCE is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -# CONFIG_VT is not set -CONFIG_SERIAL=y -# CONFIG_SERIAL_CONSOLE is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -CONFIG_EFI_RTC=y -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -CONFIG_QUOTA=y -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -# CONFIG_UMSDOS_FS is not set -CONFIG_VFAT_FS=y -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_MOUNT=y -CONFIG_DEVFS_DEBUG=y -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -CONFIG_XFS_SUPPORT=y - -# -# Network File Systems -# -# CONFIG_CODA_FS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_ROOT_NFS is not set -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -CONFIG_SUNRPC=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -# CONFIG_SMB_FS is not set -# CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -CONFIG_NLS=y - -# -# Native Language Support -# -CONFIG_NLS_DEFAULT="n" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# IEEE 1394 (FireWire) support (EXPERIMENTAL) -# -# CONFIG_IEEE1394 is not set - -# -# Bluetooth support -# -# CONFIG_BT is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -CONFIG_KDB=y -CONFIG_KDB_MODULES=y -# CONFIG_KDB_OFF is not set - -# -# Load all symbols for debugging is required for KDB -# -CONFIG_KALLSYMS=y diff -Nru a/arch/ia64/sn/configs/sn2/defconfig-dig-numa b/arch/ia64/sn/configs/sn2/defconfig-dig-numa --- a/arch/ia64/sn/configs/sn2/defconfig-dig-numa Wed Jan 15 16:57:28 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,450 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -# CONFIG_EXPERIMENTAL is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -# CONFIG_IA64_GENERIC is not set -CONFIG_IA64_DIG=y -# CONFIG_IA64_HP_SIM is not set -# CONFIG_IA64_SGI_SN1 is not set -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=6 -CONFIG_NUMA=y -CONFIG_DISCONTIGMEM=y -# CONFIG_IA64_MCA is not set -CONFIG_PM=y -CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y -# CONFIG_DEVFS_FS is not set -CONFIG_KCORE_ELF=y -CONFIG_SMP=y -# CONFIG_IA32_SUPPORT is not set -# CONFIG_PERFMON is not set -# CONFIG_IA64_PALINFO is not set -# CONFIG_EFI_VARS is not set -# CONFIG_NET is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -# CONFIG_XSCSI is not set - -# -# SCSI support -# -# CONFIG_SCSI is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_SERIAL is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_EFI_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_XFS_SUPPORT is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_SMB_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set - -# -# Console drivers -# -CONFIG_VGA_CONSOLE=y - -# -# Frame-buffer support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# - -# -# Networking support is needed for USB Networking device support -# - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_KDB is not set -# CONFIG_KDB_MODULES is not set -# CONFIG_KALLSYMS is not set diff -Nru a/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-mp b/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-mp --- a/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-mp Wed Jan 15 16:57:29 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,449 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -# CONFIG_EXPERIMENTAL is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -# CONFIG_IA64_GENERIC is not set -CONFIG_IA64_DIG=y -# CONFIG_IA64_HP_SIM is not set -# CONFIG_IA64_SGI_SN1 is not set -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=6 -# CONFIG_NUMA is not set -# CONFIG_IA64_MCA is not set -CONFIG_PM=y -CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y -# CONFIG_DEVFS_FS is not set -CONFIG_KCORE_ELF=y -CONFIG_SMP=y -# CONFIG_IA32_SUPPORT is not set -# CONFIG_PERFMON is not set -# CONFIG_IA64_PALINFO is not set -# CONFIG_EFI_VARS is not set -# CONFIG_NET is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -# CONFIG_XSCSI is not set - -# -# SCSI support -# -# CONFIG_SCSI is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_SERIAL is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_EFI_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_XFS_SUPPORT is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_SMB_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set - -# -# Console drivers -# -CONFIG_VGA_CONSOLE=y - -# -# Frame-buffer support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# - -# -# Networking support is needed for USB Networking device support -# - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_KDB is not set -# CONFIG_KDB_MODULES is not set -# CONFIG_KALLSYMS is not set diff -Nru a/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-sp b/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-sp --- a/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-sp Wed Jan 15 16:57:29 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,449 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -# CONFIG_EXPERIMENTAL is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set -# CONFIG_IA64_GENERIC is not set -CONFIG_IA64_DIG=y -# CONFIG_IA64_HP_SIM is not set -# CONFIG_IA64_SGI_SN1 is not set -# CONFIG_IA64_SGI_SN2 is not set -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_BRL_EMU=y -CONFIG_ITANIUM_BSTEP_SPECIFIC=y -CONFIG_IA64_L1_CACHE_SHIFT=6 -# CONFIG_NUMA is not set -# CONFIG_IA64_MCA is not set -CONFIG_PM=y -CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y -# CONFIG_DEVFS_FS is not set -CONFIG_KCORE_ELF=y -# CONFIG_SMP is not set -# CONFIG_IA32_SUPPORT is not set -# CONFIG_PERFMON is not set -# CONFIG_IA64_PALINFO is not set -# CONFIG_EFI_VARS is not set -# CONFIG_NET is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -# CONFIG_XSCSI is not set - -# -# SCSI support -# -# CONFIG_SCSI is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_SERIAL is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_EFI_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_XFS_SUPPORT is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_SMB_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set - -# -# Console drivers -# -CONFIG_VGA_CONSOLE=y - -# -# Frame-buffer support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# - -# -# Networking support is needed for USB Networking device support -# - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_KDB is not set -# CONFIG_KDB_MODULES is not set -# CONFIG_KALLSYMS is not set diff -Nru a/arch/ia64/sn/configs/sn2/defconfig-sn2-mp b/arch/ia64/sn/configs/sn2/defconfig-sn2-mp --- a/arch/ia64/sn/configs/sn2/defconfig-sn2-mp Wed Jan 15 16:57:28 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,720 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -# CONFIG_ITANIUM is not set -CONFIG_MCKINLEY=y -# CONFIG_IA64_GENERIC is not set -# CONFIG_IA64_DIG is not set -# CONFIG_IA64_HP_SIM is not set -# CONFIG_IA64_SGI_SN1 is not set -CONFIG_IA64_SGI_SN2=y -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_L1_CACHE_SHIFT=7 -CONFIG_MCKINLEY_ASTEP_SPECIFIC=y -CONFIG_MCKINLEY_A0_SPECIFIC=y -CONFIG_IA64_SGI_SN=y -CONFIG_IA64_SGI_SN_DEBUG=y -CONFIG_IA64_SGI_SN_SIM=y -CONFIG_IA64_SGI_AUTOTEST=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_DEBUG=y -CONFIG_SERIAL_SGI_L1_PROTOCOL=y -CONFIG_DISCONTIGMEM=y -CONFIG_IA64_MCA=y -CONFIG_NUMA=y -CONFIG_PERCPU_IRQ=y -CONFIG_PCIBA=y -CONFIG_KCORE_ELF=y -CONFIG_SMP=y -CONFIG_IA32_SUPPORT=y -CONFIG_PERFMON=y -CONFIG_IA64_PALINFO=y -# CONFIG_EFI_VARS is not set -CONFIG_NET=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK=y -CONFIG_RTNETLINK=y -CONFIG_NETLINK_DEV=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_DEBUG=y -CONFIG_FILTER=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_INET_ECN is not set -CONFIG_SYN_COOKIES=y - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_COMPAT_IPCHAINS is not set -# CONFIG_IP_NF_COMPAT_IPFWADM is not set -# CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set - -# -# -# -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_LLC is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_FASTROUTE is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set -# CONFIG_PNPBIOS is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_LAN is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -CONFIG_XSCSI=y - -# -# Alternate SCSI support -# -CONFIG_XSCSI_DKSC=y -# CONFIG_XSCSI_QLFC is not set -# CONFIG_XSCSI_QL is not set -# CONFIG_XSCSI_SBP2 is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_NCR53C8XX is not set -# CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -CONFIG_SCSI_QLOGIC_FC=y -# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLOGIC_QLA2100 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_SUNLANCE is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -# CONFIG_VT is not set -CONFIG_SERIAL=y -# CONFIG_SERIAL_CONSOLE is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -CONFIG_EFI_RTC=y -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -CONFIG_QUOTA=y -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -# CONFIG_UMSDOS_FS is not set -CONFIG_VFAT_FS=y -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_MOUNT=y -CONFIG_DEVFS_DEBUG=y -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -CONFIG_XFS_SUPPORT=y - -# -# Network File Systems -# -# CONFIG_CODA_FS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_ROOT_NFS is not set -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -CONFIG_SUNRPC=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -# CONFIG_SMB_FS is not set -# CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -CONFIG_NLS=y - -# -# Native Language Support -# -CONFIG_NLS_DEFAULT="n" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# IEEE 1394 (FireWire) support (EXPERIMENTAL) -# -# CONFIG_IEEE1394 is not set - -# -# Bluetooth support -# -# CONFIG_BT is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_KDB is not set -# CONFIG_KDB_MODULES is not set -CONFIG_KALLSYMS=y diff -Nru a/arch/ia64/sn/configs/sn2/defconfig-sn2-mp-modules b/arch/ia64/sn/configs/sn2/defconfig-sn2-mp-modules --- a/arch/ia64/sn/configs/sn2/defconfig-sn2-mp-modules Wed Jan 15 16:57:29 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,722 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y - -# -# Loadable module support -# -CONFIG_MODULES=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -# CONFIG_ITANIUM is not set -CONFIG_MCKINLEY=y -# CONFIG_IA64_GENERIC is not set -# CONFIG_IA64_DIG is not set -# CONFIG_IA64_HP_SIM is not set -# CONFIG_IA64_SGI_SN1 is not set -CONFIG_IA64_SGI_SN2=y -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_L1_CACHE_SHIFT=7 -CONFIG_MCKINLEY_ASTEP_SPECIFIC=y -CONFIG_MCKINLEY_A0_SPECIFIC=y -CONFIG_IA64_SGI_SN=y -CONFIG_IA64_SGI_SN_DEBUG=y -CONFIG_IA64_SGI_SN_SIM=y -CONFIG_IA64_SGI_AUTOTEST=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_DEBUG=y -# CONFIG_SERIAL_SGI_L1_PROTOCOL is not set -CONFIG_DISCONTIGMEM=y -CONFIG_IA64_MCA=y -CONFIG_NUMA=y -CONFIG_PERCPU_IRQ=y -CONFIG_PCIBA=y -CONFIG_KCORE_ELF=y -CONFIG_SMP=y -CONFIG_IA32_SUPPORT=y -CONFIG_PERFMON=y -CONFIG_IA64_PALINFO=y -# CONFIG_EFI_VARS is not set -CONFIG_NET=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK=y -CONFIG_RTNETLINK=y -CONFIG_NETLINK_DEV=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_DEBUG=y -CONFIG_FILTER=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_INET_ECN is not set -CONFIG_SYN_COOKIES=y - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_COMPAT_IPCHAINS is not set -# CONFIG_IP_NF_COMPAT_IPFWADM is not set -# CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set - -# -# -# -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_LLC is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_FASTROUTE is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set -# CONFIG_PNPBIOS is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_LAN is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -CONFIG_XSCSI=y - -# -# Alternate SCSI support -# -CONFIG_XSCSI_DKSC=y -# CONFIG_XSCSI_QLFC is not set -# CONFIG_XSCSI_QL is not set -# CONFIG_XSCSI_SBP2 is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_NCR53C8XX is not set -# CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -CONFIG_SCSI_QLOGIC_FC=y -# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLOGIC_QLA2100 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_SUNLANCE is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -# CONFIG_VT is not set -CONFIG_SERIAL=y -# CONFIG_SERIAL_CONSOLE is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -CONFIG_EFI_RTC=y -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -CONFIG_QUOTA=y -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -# CONFIG_UMSDOS_FS is not set -CONFIG_VFAT_FS=y -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_MOUNT=y -CONFIG_DEVFS_DEBUG=y -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -CONFIG_XFS_SUPPORT=y - -# -# Network File Systems -# -# CONFIG_CODA_FS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_ROOT_NFS is not set -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -CONFIG_SUNRPC=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -# CONFIG_SMB_FS is not set -# CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -CONFIG_NLS=y - -# -# Native Language Support -# -CONFIG_NLS_DEFAULT="n" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# IEEE 1394 (FireWire) support (EXPERIMENTAL) -# -# CONFIG_IEEE1394 is not set - -# -# Bluetooth support -# -# CONFIG_BT is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_KDB is not set -# CONFIG_KDB_MODULES is not set -CONFIG_KALLSYMS=y diff -Nru a/arch/ia64/sn/configs/sn2/defconfig-sn2-prom-medusa b/arch/ia64/sn/configs/sn2/defconfig-sn2-prom-medusa --- a/arch/ia64/sn/configs/sn2/defconfig-sn2-prom-medusa Wed Jan 15 16:57:29 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,527 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -# CONFIG_ITANIUM is not set -CONFIG_MCKINLEY=y -# CONFIG_IA64_GENERIC is not set -# CONFIG_IA64_DIG is not set -# CONFIG_IA64_HP_SIM is not set -# CONFIG_IA64_SGI_SN1 is not set -CONFIG_IA64_SGI_SN2=y -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_L1_CACHE_SHIFT=7 -CONFIG_MCKINLEY_ASTEP_SPECIFIC=y -CONFIG_MCKINLEY_A0_SPECIFIC=y -CONFIG_IA64_SGI_SN=y -CONFIG_IA64_SGI_SN_DEBUG=y -CONFIG_IA64_SGI_SN_SIM=y -CONFIG_IA64_SGI_AUTOTEST=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_DEBUG=y -CONFIG_SERIAL_SGI_L1_PROTOCOL=y -CONFIG_DISCONTIGMEM=y -CONFIG_IA64_MCA=y -CONFIG_NUMA=y -CONFIG_PERCPU_IRQ=y -CONFIG_PCIBA=y -CONFIG_KCORE_ELF=y -CONFIG_SMP=y -# CONFIG_IA32_SUPPORT is not set -CONFIG_PERFMON=y -CONFIG_IA64_PALINFO=y -# CONFIG_EFI_VARS is not set -# CONFIG_NET is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set -# CONFIG_PNPBIOS is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -CONFIG_XSCSI=y - -# -# Alternate SCSI support -# -CONFIG_XSCSI_DKSC=y -# CONFIG_XSCSI_QLFC is not set -# CONFIG_XSCSI_QL is not set -# CONFIG_XSCSI_SBP2 is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_NCR53C8XX is not set -# CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -CONFIG_SCSI_QLOGIC_FC=y -# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLOGIC_QLA2100 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -# CONFIG_VT is not set -CONFIG_SERIAL=y -# CONFIG_SERIAL_CONSOLE is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_EFI_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_MOUNT=y -CONFIG_DEVFS_DEBUG=y -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -CONFIG_XFS_SUPPORT=y -# CONFIG_NCPFS_NLS is not set -# CONFIG_SMB_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# - -# -# Networking support is needed for USB Networking device support -# - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# IEEE 1394 (FireWire) support (EXPERIMENTAL) -# -# CONFIG_IEEE1394 is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_KDB is not set -# CONFIG_KDB_MODULES is not set -# CONFIG_KALLSYMS is not set diff -Nru a/arch/ia64/sn/configs/sn2/defconfig-sn2-sp b/arch/ia64/sn/configs/sn2/defconfig-sn2-sp --- a/arch/ia64/sn/configs/sn2/defconfig-sn2-sp Wed Jan 15 16:57:28 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,720 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y - -# -# Loadable module support -# -# CONFIG_MODULES is not set - -# -# General setup -# -CONFIG_IA64=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_ACPI=y -CONFIG_ACPI_EFI=y -CONFIG_ACPI_INTERPRETER=y -CONFIG_ACPI_KERNEL_CONFIG=y -# CONFIG_ITANIUM is not set -CONFIG_MCKINLEY=y -# CONFIG_IA64_GENERIC is not set -# CONFIG_IA64_DIG is not set -# CONFIG_IA64_HP_SIM is not set -# CONFIG_IA64_SGI_SN1 is not set -CONFIG_IA64_SGI_SN2=y -# CONFIG_IA64_PAGE_SIZE_4KB is not set -# CONFIG_IA64_PAGE_SIZE_8KB is not set -CONFIG_IA64_PAGE_SIZE_16KB=y -# CONFIG_IA64_PAGE_SIZE_64KB is not set -CONFIG_IA64_L1_CACHE_SHIFT=7 -CONFIG_MCKINLEY_ASTEP_SPECIFIC=y -CONFIG_MCKINLEY_A0_SPECIFIC=y -CONFIG_IA64_SGI_SN=y -CONFIG_IA64_SGI_SN_DEBUG=y -CONFIG_IA64_SGI_SN_SIM=y -CONFIG_IA64_SGI_AUTOTEST=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_DEBUG=y -CONFIG_SERIAL_SGI_L1_PROTOCOL=y -CONFIG_DISCONTIGMEM=y -CONFIG_IA64_MCA=y -CONFIG_NUMA=y -CONFIG_PERCPU_IRQ=y -CONFIG_PCIBA=y -CONFIG_KCORE_ELF=y -# CONFIG_SMP is not set -CONFIG_IA32_SUPPORT=y -CONFIG_PERFMON=y -CONFIG_IA64_PALINFO=y -# CONFIG_EFI_VARS is not set -CONFIG_NET=y -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_BUSMGR is not set -# CONFIG_ACPI_SYS is not set -# CONFIG_ACPI_CPU is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_AC is not set -# CONFIG_ACPI_EC is not set -# CONFIG_ACPI_CMBATT is not set -# CONFIG_ACPI_THERMAL is not set -CONFIG_PCI=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_NETLINK=y -CONFIG_RTNETLINK=y -CONFIG_NETLINK_DEV=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_DEBUG=y -CONFIG_FILTER=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_INET_ECN is not set -CONFIG_SYN_COOKIES=y - -# -# IP: Netfilter Configuration -# -# CONFIG_IP_NF_CONNTRACK is not set -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_COMPAT_IPCHAINS is not set -# CONFIG_IP_NF_COMPAT_IPFWADM is not set -# CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set - -# -# -# -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_LLC is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_FASTROUTE is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Plug and Play configuration -# -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set -# CONFIG_PNPBIOS is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set - -# -# I2O device support -# -# CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_LAN is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# Alternate 1394 support -# -# CONFIG_X1394 is not set - -# -# Alternate SCSI support -# -CONFIG_XSCSI=y - -# -# Alternate SCSI support -# -CONFIG_XSCSI_DKSC=y -# CONFIG_XSCSI_QLFC is not set -# CONFIG_XSCSI_QL is not set -# CONFIG_XSCSI_SBP2 is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_NCR53C8XX is not set -# CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -CONFIG_SCSI_QLOGIC_FC=y -# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLOGIC_QLA2100 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Network device support -# -CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_ETHERTAP is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -# CONFIG_SUNLANCE is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set - -# -# Ethernet (1000 Mbit) -# -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Token Ring devices -# -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set -# CONFIG_SHAPER is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# CD-ROM drivers (not for SCSI or IDE/ATAPI drives) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Character devices -# -# CONFIG_VT is not set -CONFIG_SERIAL=y -# CONFIG_SERIAL_CONSOLE is not set -# CONFIG_SERIAL_EXTENDED is not set -# CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -CONFIG_EFI_RTC=y -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set -# CONFIG_MWAVE is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -CONFIG_QUOTA=y -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -# CONFIG_UMSDOS_FS is not set -CONFIG_VFAT_FS=y -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_MOUNT=y -CONFIG_DEVFS_DEBUG=y -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -CONFIG_XFS_SUPPORT=y - -# -# Network File Systems -# -# CONFIG_CODA_FS is not set -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_ROOT_NFS is not set -CONFIG_NFSD=y -CONFIG_NFSD_V3=y -CONFIG_SUNRPC=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -# CONFIG_SMB_FS is not set -# CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -CONFIG_NLS=y - -# -# Native Language Support -# -CONFIG_NLS_DEFAULT="n" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_HP8200e is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# - -# -# USB Network adaptors -# -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_RIO500 is not set - -# -# IEEE 1394 (FireWire) support (EXPERIMENTAL) -# -# CONFIG_IEEE1394 is not set - -# -# Bluetooth support -# -# CONFIG_BT is not set - -# -# Kernel hacking -# -CONFIG_DEBUG_KERNEL=y -CONFIG_IA64_PRINT_HAZARDS=y -# CONFIG_DISABLE_VHPT is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_IA64_DEBUG_CMPXCHG is not set -# CONFIG_IA64_DEBUG_IRQ is not set -# CONFIG_KDB is not set -# CONFIG_KDB_MODULES is not set -CONFIG_KALLSYMS=y diff -Nru a/arch/ia64/sn/fakeprom/Makefile b/arch/ia64/sn/fakeprom/Makefile --- a/arch/ia64/sn/fakeprom/Makefile Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/fakeprom/Makefile Wed Jan 15 16:57:29 2003 @@ -6,15 +6,15 @@ # Copyright (c) 2000-2001 Silicon Graphics, Inc. All rights reserved. # -TOPDIR=../../../.. - -LIB = ../../lib/lib.a - -OBJ=fpromasm.o main.o fw-emu.o fpmem.o klgraph_init.o -obj-y=fprom +obj-y=fpromasm.o main.o fw-emu.o fpmem.o klgraph_init.o fprom: $(OBJ) $(LD) -static -Tfprom.lds -o fprom $(OBJ) $(LIB) + +.S.o: + $(CC) -D__ASSEMBLY__ $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $< +.c.o: + $(CC) $(CFLAGS) $(CFLAGS_KERNEL) -c -o $*.o $< clean: rm -f *.o fprom diff -Nru a/arch/ia64/sn/fakeprom/README b/arch/ia64/sn/fakeprom/README --- a/arch/ia64/sn/fakeprom/README Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/fakeprom/README Wed Jan 15 16:57:29 2003 @@ -71,7 +71,7 @@ 1GB*, where dn is the digit number. The amount of memory is 8MB*2**. (If = 0, the memory size is 0). - SN1 doesn't support dimms this small but small memory systems + SN1 doesnt support dimms this small but small memory systems boot faster on Medusa. diff -Nru a/arch/ia64/sn/fakeprom/fpmem.c b/arch/ia64/sn/fakeprom/fpmem.c --- a/arch/ia64/sn/fakeprom/fpmem.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/fakeprom/fpmem.c Wed Jan 15 16:57:29 2003 @@ -54,10 +54,10 @@ #define PROMRESERVED_SIZE (1*MB) #ifdef CONFIG_IA64_SGI_SN1 -#define PHYS_ADDRESS(_n, _x) (((long)_n<<33L) | (long)_x) +#define PHYS_ADDRESS(_n, _x) (((long)_n<<33) | (long)_x) #define MD_BANK_SHFT 30 #else -#define PHYS_ADDRESS(_n, _x) (((long)_n<<38L) | (long)_x | 0x3000000000UL) +#define PHYS_ADDRESS(_n, _x) (((long)_n<<38) | (long)_x | 0x3000000000UL) #define MD_BANK_SHFT 34 #endif @@ -94,7 +94,7 @@ int IsCpuPresent(int cnode, int cpu) { - return sn_memmap[cnode].cpuconfig & (1< 128*1024*1024) { + numbytes -= 1000; + } /* * Check for the node 0 hole. Since banks cant diff -Nru a/arch/ia64/sn/fakeprom/fpmem.h b/arch/ia64/sn/fakeprom/fpmem.h --- a/arch/ia64/sn/fakeprom/fpmem.h Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/fakeprom/fpmem.h Wed Jan 15 16:57:29 2003 @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #include @@ -71,7 +71,8 @@ } node_memmap_t ; #define SN2_BANK_SIZE_SHIFT (MBSHIFT+6) /* 64 MB */ -#define BankSizeBytes(bsize) (1UL<<((bsize)+SN2_BANK_SIZE_SHIFT)) +#define BankPresent(bsize) (bsize<6) +#define BankSizeBytes(bsize) (BankPresent(bsize) ? 1UL<<((bsize)+SN2_BANK_SIZE_SHIFT) : 0) #endif typedef struct sn_memmap_s diff -Nru a/arch/ia64/sn/fakeprom/fpromasm.S b/arch/ia64/sn/fakeprom/fpromasm.S --- a/arch/ia64/sn/fakeprom/fpromasm.S Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/fakeprom/fpromasm.S Wed Jan 15 16:57:28 2003 @@ -180,7 +180,7 @@ // Now call main & pass it the current LID value. - alloc r0=ar.pfs,0,0,2,0 + alloc r2=ar.pfs,0,0,2,0 mov r32=r26 mov r33=r8;; br.call.sptk.few rp=fmain diff -Nru a/arch/ia64/sn/fakeprom/fw-emu.c b/arch/ia64/sn/fakeprom/fw-emu.c --- a/arch/ia64/sn/fakeprom/fw-emu.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/fakeprom/fw-emu.c Wed Jan 15 16:57:29 2003 @@ -36,6 +36,7 @@ * http://oss.sgi.com/projects/GenInfo/NoticeExplan */ #include +#include #include #include #include @@ -46,10 +47,26 @@ #include #include #endif -#include +#include #include "fpmem.h" -#define zzACPI_1_0 1 /* Include ACPI 1.0 tables */ +#define RSDP_NAME "RSDP" +#define RSDP_SIG "RSD PTR " /* RSDT Pointer signature */ +#define APIC_SIG "APIC" /* Multiple APIC Description Table */ +#define DSDT_SIG "DSDT" /* Differentiated System Description Table */ +#define FADT_SIG "FACP" /* Fixed ACPI Description Table */ +#define FACS_SIG "FACS" /* Firmware ACPI Control Structure */ +#define PSDT_SIG "PSDT" /* Persistent System Description Table */ +#define RSDT_SIG "RSDT" /* Root System Description Table */ +#define XSDT_SIG "XSDT" /* Extended System Description Table */ +#define SSDT_SIG "SSDT" /* Secondary System Description Table */ +#define SBST_SIG "SBST" /* Smart Battery Specification Table */ +#define SPIC_SIG "SPIC" /* IOSAPIC table */ +#define SRAT_SIG "SRAT" /* SRAT table */ +#define SLIT_SIG "SLIT" /* SLIT table */ +#define BOOT_SIG "BOOT" /* Boot table */ +#define ACPI_SRAT_REVISION 1 +#define ACPI_SLIT_REVISION 1 #define OEMID "SGI" #ifdef CONFIG_IA64_SGI_SN1 @@ -77,11 +94,7 @@ #define CPUS_PER_FSB 2 #define CPUS_PER_FSB_MASK (CPUS_PER_FSB-1) -#ifdef ACPI_1_0 -#define NUM_EFI_DESCS 3 -#else #define NUM_EFI_DESCS 2 -#endif #define RSDP_CHECKSUM_LENGTH 20 @@ -139,22 +152,16 @@ + sizeof(struct ia64_sal_systab) + sizeof(struct ia64_sal_desc_entry_point) + sizeof(struct ia64_sal_desc_ap_wakeup) -#ifdef ACPI_1_0 - + sizeof(acpi_rsdp_t) - + sizeof(acpi_rsdt_t) - + sizeof(acpi_sapic_t) - + MAX_LSAPICS*(sizeof(acpi_entry_lsapic_t)) -#endif - + sizeof(acpi20_rsdp_t) - + sizeof(acpi_xsdt_t) - + sizeof(acpi_slit_t) + + sizeof(struct acpi20_table_rsdp) + + sizeof(struct acpi_table_xsdt) + + sizeof(struct acpi_table_slit) + MAX_SN_NODES*MAX_SN_NODES+8 - + sizeof(acpi_madt_t) + + sizeof(struct acpi_table_madt) + 16*MAX_CPUS + (1+8*MAX_SN_NODES)*(sizeof(efi_memory_desc_t)) - + sizeof(acpi_srat_t) - + MAX_CPUS*sizeof(srat_cpu_affinity_t) - + MAX_SN_NODES*sizeof(srat_memory_affinity_t) + + sizeof(struct acpi_table_srat) + + MAX_CPUS*sizeof(struct acpi_table_processor_affinity) + + MAX_SN_NODES*sizeof(struct acpi_table_memory_affinity) + sizeof(ia64_sal_desc_ptc_t) + + MAX_SN_NODES*sizeof(ia64_sal_ptc_domain_info_t) + + MAX_CPUS*sizeof(ia64_sal_ptc_domain_proc_entry_t) + @@ -280,6 +287,7 @@ } else if (index == SAL_GET_STATE_INFO) { ; } else if (index == SAL_GET_STATE_INFO_SIZE) { + r9 = 10000; ; } else if (index == SAL_CLEAR_STATE_INFO) { ; @@ -328,6 +336,14 @@ } } else if (index == SN_SAL_GET_KLCONFIG_ADDR) { r9 = 0x30000; + } else if (index == SN_SAL_CONSOLE_PUTC) { + status = -1; + } else if (index == SN_SAL_CONSOLE_GETC) { + status = -1; + } else if (index == SN_SAL_CONSOLE_POLL) { + status = -1; + } else if (index == SN_SAL_SYSCTL_IOBRICK_MODULE_GET) { + status = -1; } else { status = -1; } @@ -396,7 +412,7 @@ } void -acpi_table_init(acpi_desc_table_hdr_t *p, char *sig, int siglen, int revision, int oem_revision) +acpi_table_initx(struct acpi_table_header *p, char *sig, int siglen, int revision, int oem_revision) { memcpy(p->signature, sig, siglen); memcpy(p->oem_id, OEMID, 6); @@ -404,12 +420,12 @@ memcpy(p->oem_table_id+4, PRODUCT, 4); p->revision = revision; p->oem_revision = (revision<<16) + oem_revision; - p->creator_id = 1; - p->creator_revision = 1; + memcpy(p->asl_compiler_id, "FPRM", 4); + p->asl_compiler_revision = 1; } void -acpi_checksum(acpi_desc_table_hdr_t *p, int length) +acpi_checksum(struct acpi_table_header *p, int length) { u8 *cp, *cpe, checksum; @@ -422,16 +438,22 @@ } void -acpi_checksum_rsdp20(acpi20_rsdp_t *p, int length) +acpi_checksum_rsdp20(struct acpi20_table_rsdp *p, int length) { u8 *cp, *cpe, checksum; p->checksum = 0; + p->ext_checksum = 0; p->length = length; checksum = 0; - for (cp=(u8*)p, cpe=cp+RSDP_CHECKSUM_LENGTH; cpchecksum = -checksum; + + checksum = 0; + for (cp=(u8*)p, cpe=cp+length; cpext_checksum = -checksum; } int @@ -456,21 +478,15 @@ static ia64_sal_desc_ptc_t *sal_ptc; static ia64_sal_ptc_domain_info_t *sal_ptcdi; static ia64_sal_ptc_domain_proc_entry_t *sal_ptclid; -#ifdef ACPI_1_0 - static acpi_rsdp_t *acpi_rsdp; - static acpi_rsdt_t *acpi_rsdt; - static acpi_sapic_t *acpi_sapic; - static acpi_entry_lsapic_t *acpi_lsapic; -#endif - static acpi20_rsdp_t *acpi20_rsdp; - static acpi_xsdt_t *acpi_xsdt; - static acpi_slit_t *acpi_slit; - static acpi_madt_t *acpi_madt; - static acpi20_entry_lsapic_t *lsapic20; + static struct acpi20_table_rsdp *acpi20_rsdp; + static struct acpi_table_xsdt *acpi_xsdt; + static struct acpi_table_slit *acpi_slit; + static struct acpi_table_madt *acpi_madt; + static struct acpi_table_lsapic *lsapic20; static struct ia64_sal_systab *sal_systab; - static acpi_srat_t *acpi_srat; - static srat_cpu_affinity_t *srat_cpu_affinity; - static srat_memory_affinity_t *srat_memory_affinity; + static struct acpi_table_srat *acpi_srat; + static struct acpi_table_processor_affinity *srat_cpu_affinity; + static struct acpi_table_memory_affinity *srat_memory_affinity; static efi_memory_desc_t *efi_memmap, *md; static unsigned long *pal_desc, *sal_desc; static struct ia64_sal_desc_entry_point *sal_ed; @@ -519,16 +535,10 @@ acpi_xsdt = (void *) cp; cp += ALIGN8(sizeof(*acpi_xsdt) + 64); /* save space for more OS defined table pointers. */ -#ifdef ACPI_1_0 - acpi_rsdp = (void *) cp; cp += ALIGN8(sizeof(*acpi_rsdp)); - acpi_rsdt = (void *) cp; cp += ALIGN8(sizeof(*acpi_rsdt)); - acpi_sapic = (void *) cp; cp += sizeof(*acpi_sapic); - acpi_lsapic = (void *) cp; cp += num_cpus*sizeof(*acpi_lsapic); -#endif acpi_slit = (void *) cp; cp += ALIGN8(sizeof(*acpi_slit) + 8 + (max_nasid+1)*(max_nasid+1)); - acpi_madt = (void *) cp; cp += ALIGN8(sizeof(*acpi_madt) + 8 * num_cpus+ 8); - acpi_srat = (void *) cp; cp += ALIGN8(sizeof(acpi_srat_t)); - cp += sizeof(srat_cpu_affinity_t)*num_cpus + sizeof(srat_memory_affinity_t)*num_nodes; + acpi_madt = (void *) cp; cp += ALIGN8(sizeof(*acpi_madt) + sizeof(struct acpi_table_lsapic) * (num_cpus+1)); + acpi_srat = (void *) cp; cp += ALIGN8(sizeof(struct acpi_table_srat)); + cp += sizeof(struct acpi_table_processor_affinity)*num_cpus + sizeof(struct acpi_table_memory_affinity)*num_nodes; vendor = (char *) cp; cp += ALIGN8(40); efi_memmap = (void *) cp; cp += ALIGN8(8*32*sizeof(*efi_memmap)); sal_ptcdi = (void *) cp; cp += ALIGN8(CPUS_PER_FSB*(1+num_nodes)*sizeof(*sal_ptcdi)); @@ -547,8 +557,9 @@ * For now, just bring up bash. * If you want to execute all the startup scripts, delete the "init=..". * You can also edit this line to pass other arguments to the kernel. + * Note: disable kernel text replication. */ - strcpy(cmd_line, "init=/bin/bash"); + strcpy(cmd_line, "init=/bin/bash ktreplicate=0"); memset(efi_systab, 0, sizeof(efi_systab)); efi_systab->hdr.signature = EFI_SYSTEM_TABLE_SIGNATURE; @@ -578,11 +589,6 @@ efi_tables->guid = SAL_SYSTEM_TABLE_GUID; efi_tables->table = __fwtab_pa(base_nasid, sal_systab); efi_tables++; -#ifdef ACPI_1_0 - efi_tables->guid = ACPI_TABLE_GUID; - efi_tables->table = __fwtab_pa(base_nasid, acpi_rsdp); - efi_tables++; -#endif efi_tables->guid = ACPI_20_TABLE_GUID; efi_tables->table = __fwtab_pa(base_nasid, acpi20_rsdp); efi_tables++; @@ -593,65 +599,32 @@ fix_function_pointer(&efi_reset_system); fix_function_pointer(&efi_set_virtual_address_map); -#ifdef ACPI_1_0 - /* fill in the ACPI system table - has a pointer to the ACPI table header */ - memcpy(acpi_rsdp->signature, "RSD PTR ", 8); - acpi_rsdp->rsdt = (struct acpi_rsdt*)__fwtab_pa(base_nasid, acpi_rsdt); - - acpi_table_init(&acpi_rsdt->header, ACPI_RSDT_SIG, ACPI_RSDT_SIG_LEN, 1, 1); - acpi_rsdt->header.length = sizeof(acpi_rsdt_t); - acpi_rsdt->entry_ptrs[0] = __fwtab_pa(base_nasid, acpi_sapic); - - memcpy(acpi_sapic->header.signature, "SPIC ", 4); - acpi_sapic->header.length = sizeof(acpi_sapic_t)+num_cpus*sizeof(acpi_entry_lsapic_t); - - for (cnode=0; cnodetype = ACPI_ENTRY_LOCAL_SAPIC; - acpi_lsapic->length = sizeof(acpi_entry_lsapic_t); - acpi_lsapic->acpi_processor_id = cnode*4+cpu; - acpi_lsapic->flags = LSAPIC_ENABLED|LSAPIC_PRESENT; -#if defined(CONFIG_IA64_SGI_SN1) - acpi_lsapic->eid = cpu; - acpi_lsapic->id = nasid; -#else - acpi_lsapic->eid = nasid&0xffff; - acpi_lsapic->id = (cpu<<4) | (nasid>>16); -#endif - acpi_lsapic++; - } - } -#endif - /* fill in the ACPI20 system table - has a pointer to the ACPI table header */ memcpy(acpi20_rsdp->signature, "RSD PTR ", 8); - acpi20_rsdp->xsdt = (struct acpi_xsdt*)__fwtab_pa(base_nasid, acpi_xsdt); + acpi20_rsdp->xsdt_address = (u64)__fwtab_pa(base_nasid, acpi_xsdt); acpi20_rsdp->revision = 2; - acpi_checksum_rsdp20(acpi20_rsdp, sizeof(acpi20_rsdp_t)); + acpi_checksum_rsdp20(acpi20_rsdp, sizeof(struct acpi20_table_rsdp)); /* Set up the XSDT table - contains pointers to the other ACPI tables */ - acpi_table_init(&acpi_xsdt->header, ACPI_XSDT_SIG, ACPI_XSDT_SIG_LEN, 1, 1); - acpi_xsdt->entry_ptrs[0] = __fwtab_pa(base_nasid, acpi_madt); - acpi_xsdt->entry_ptrs[1] = __fwtab_pa(base_nasid, acpi_slit); - acpi_xsdt->entry_ptrs[2] = __fwtab_pa(base_nasid, acpi_srat); - acpi_checksum(&acpi_xsdt->header, sizeof(acpi_xsdt_t) + 16); - - /* Set up the MADT table */ - acpi_table_init(&acpi_madt->header, ACPI_MADT_SIG, ACPI_MADT_SIG_LEN, 1, 1); - lsapic20 = (acpi20_entry_lsapic_t*) (acpi_madt + 1); + acpi_table_initx(&acpi_xsdt->header, XSDT_SIG, 4, 1, 1); + acpi_xsdt->entry[0] = __fwtab_pa(base_nasid, acpi_madt); + acpi_xsdt->entry[1] = __fwtab_pa(base_nasid, acpi_slit); + acpi_xsdt->entry[2] = __fwtab_pa(base_nasid, acpi_srat); + acpi_checksum(&acpi_xsdt->header, sizeof(struct acpi_table_xsdt) + 16); + + /* Set up the APIC table */ + acpi_table_initx(&acpi_madt->header, APIC_SIG, 4, 1, 1); + lsapic20 = (struct acpi_table_lsapic*) (acpi_madt + 1); for (cnode=0; cnodetype = ACPI20_ENTRY_LOCAL_SAPIC; - lsapic20->length = sizeof(acpi_entry_lsapic_t); - lsapic20->acpi_processor_id = cnode*4+cpu; - lsapic20->flags = LSAPIC_ENABLED|LSAPIC_PRESENT; + lsapic20->header.type = ACPI_MADT_LSAPIC; + lsapic20->header.length = sizeof(struct acpi_table_lsapic); + lsapic20->acpi_id = cnode*4+cpu; + lsapic20->flags.enabled = 1; #if defined(CONFIG_IA64_SGI_SN1) lsapic20->eid = cpu; lsapic20->id = nasid; @@ -659,20 +632,20 @@ lsapic20->eid = nasid&0xffff; lsapic20->id = (cpu<<4) | (nasid>>16); #endif - lsapic20 = (acpi20_entry_lsapic_t*) ((long)lsapic20+sizeof(acpi_entry_lsapic_t)); + lsapic20 = (struct acpi_table_lsapic*) ((long)lsapic20+sizeof(struct acpi_table_lsapic)); } } acpi_checksum(&acpi_madt->header, (char*)lsapic20 - (char*)acpi_madt); /* Set up the SRAT table */ - acpi_table_init(&acpi_srat->header, ACPI_SRAT_SIG, ACPI_SRAT_SIG_LEN, ACPI_SRAT_REVISION, 1); + acpi_table_initx(&acpi_srat->header, SRAT_SIG, 4, ACPI_SRAT_REVISION, 1); ptr = acpi_srat+1; for (cnode=0; cnodetype = SRAT_MEMORY_STRUCTURE; - srat_memory_affinity->length = sizeof(srat_memory_affinity_t); + srat_memory_affinity->header.type = ACPI_SRAT_MEMORY_AFFINITY; + srat_memory_affinity->header.length = sizeof(struct acpi_table_memory_affinity); srat_memory_affinity->proximity_domain = PROXIMITY_DOMAIN(nasid); srat_memory_affinity->base_addr_lo = 0; srat_memory_affinity->length_lo = 0; @@ -684,7 +657,7 @@ srat_memory_affinity->length_hi = SN2_NODE_SIZE>>32; #endif srat_memory_affinity->memory_type = ACPI_ADDRESS_RANGE_MEMORY; - srat_memory_affinity->flags = SRAT_MEMORY_FLAGS_ENABLED; + srat_memory_affinity->flags.enabled = 1; } for (cnode=0; cnodetype = SRAT_CPU_STRUCTURE; - srat_cpu_affinity->length = sizeof(srat_cpu_affinity_t); + srat_cpu_affinity->header.type = ACPI_SRAT_PROCESSOR_AFFINITY; + srat_cpu_affinity->header.length = sizeof(struct acpi_table_processor_affinity); srat_cpu_affinity->proximity_domain = PROXIMITY_DOMAIN(nasid); - srat_cpu_affinity->flags = SRAT_CPU_FLAGS_ENABLED; + srat_cpu_affinity->flags.enabled = 1; #if defined(CONFIG_IA64_SGI_SN1) srat_cpu_affinity->apic_id = nasid; - srat_cpu_affinity->local_sapic_eid = cpu; + srat_cpu_affinity->lsapic_eid = cpu; #else - srat_cpu_affinity->local_sapic_eid = nasid&0xffff; + srat_cpu_affinity->lsapic_eid = nasid&0xffff; srat_cpu_affinity->apic_id = (cpu<<4) | (nasid>>16); #endif } @@ -711,9 +684,9 @@ /* Set up the SLIT table */ - acpi_table_init(&acpi_slit->header, ACPI_SLIT_SIG, ACPI_SLIT_SIG_LEN, ACPI_SLIT_REVISION, 1); + acpi_table_initx(&acpi_slit->header, SLIT_SIG, 4, ACPI_SLIT_REVISION, 1); acpi_slit->localities = PROXIMITY_DOMAIN(max_nasid)+1; - cp=acpi_slit->entries; + cp=acpi_slit->entry; memset(cp, 255, acpi_slit->localities*acpi_slit->localities); for (i=0; i<=max_nasid; i++) @@ -721,7 +694,7 @@ if (nasid_present(i) && nasid_present(j)) *(cp+PROXIMITY_DOMAIN(i)*acpi_slit->localities+PROXIMITY_DOMAIN(j)) = 10 + MIN(254, 5*ABS(i-j)); - cp = acpi_slit->entries + acpi_slit->localities*acpi_slit->localities; + cp = acpi_slit->entry + acpi_slit->localities*acpi_slit->localities; acpi_checksum(&acpi_slit->header, cp - (char*)acpi_slit); @@ -731,6 +704,8 @@ sal_systab->sal_rev_minor = 1; sal_systab->sal_rev_major = 0; sal_systab->entry_count = 3; + sal_systab->sal_b_rev_major = 0x1; /* set the SN SAL rev to */ + sal_systab->sal_b_rev_minor = 0x0; /* 1.00 */ strcpy(sal_systab->oem_id, "SGI"); strcpy(sal_systab->product_id, "SN1"); @@ -785,11 +760,6 @@ * table. We dont build enough table & the kernel aborts. * Note that the PROM hasd thhhe same problem!! */ -#ifdef DOESNT_WORK - for (checksum=0, cp=(char*)acpi_rsdp, cpe=cp+RSDP_CHECKSUM_LENGTH; cpchecksum = -checksum; -#endif md = &efi_memmap[0]; num_memmd = build_efi_memmap((void *)md, mdsize) ; diff -Nru a/arch/ia64/sn/fakeprom/klgraph_init.c b/arch/ia64/sn/fakeprom/klgraph_init.c --- a/arch/ia64/sn/fakeprom/klgraph_init.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/fakeprom/klgraph_init.c Wed Jan 15 16:57:28 2003 @@ -1,4 +1,4 @@ -/* $Id: klgraph_init.c,v 1.2 2001/12/05 16:58:41 jh Exp $ +/* $Id: klgraph_init.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -49,8 +49,9 @@ klgraph_init(void) { - u64 *temp; - +#ifdef CONFIG_IA64_SGI_SN1 + u64 *temp; +#endif /* * Initialize some hub/xbow registers that allows access to * Xbridge etc. These are normally done in PROM. @@ -109,6 +110,8 @@ // [PI] *(volatile u32 *)0xc00000080f000288L = 0xba98; #endif /* CONFIG_IA64_SGI_SN1 */ +#ifdef CONFIG_IA64_SGI_SN1 + /* * kldir entries initialization - mankato */ @@ -282,6 +285,7 @@ convert(0x8000000000002560, 0xffffffffffffffff, 0xffffffffffffffff); convert(0x8000000000002570, 0xffffffffffffffff, 0xffffffffffffffff); convert(0x8000000000002580, 0x000000000000ffff, 0x0000000000000000); +#endif } diff -Nru a/arch/ia64/sn/fakeprom/main.c b/arch/ia64/sn/fakeprom/main.c --- a/arch/ia64/sn/fakeprom/main.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/fakeprom/main.c Wed Jan 15 16:57:29 2003 @@ -98,7 +98,7 @@ /* * Enable all FSB flashed interrupts. - * ZZZ - I'd really like defines for this...... + * I'd really like defines for this...... */ base = (long*)0x80000e0000000000LL; /* base of synergy regs */ for (off = 0x2a0; off < 0x2e0; off+=8) /* offset for VEC_MASK_{0-3}_A/B */ diff -Nru a/arch/ia64/sn/io/Makefile b/arch/ia64/sn/io/Makefile --- a/arch/ia64/sn/io/Makefile Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/io/Makefile Wed Jan 15 16:57:28 2003 @@ -5,35 +5,20 @@ # # Copyright (C) 2000-2002 Silicon Graphics, Inc. All Rights Reserved. # -# -# Makefile for the linux kernel. -# -# Note! Dependencies are done automagically by 'make dep', which also -# removes any old dependencies. DON'T put your own dependencies here -# unless it's something special (ie not a .c file). -# +# Makefile for the sn kernel routines. EXTRA_CFLAGS := -DLITTLE_ENDIAN -export-objs = pciio.o hcl.o +ifdef CONFIG_IA64_SGI_SN2 +EXTRA_CFLAGS += -DSHUB_SWAP_WAR +endif + +export-objs := hcl.o pci_dma.o + +obj-$(CONFIG_IA64_SGI_SN) += stubs.o sgi_if.o xswitch.o klgraph_hack.o \ + hcl.o labelcl.o invent.o sgi_io_sim.o \ + klgraph_hack.o hcl_util.o cdl.o hubdev.o hubspc.o \ + alenlist.o pci.o pci_dma.o ate_utils.o \ + ifconfig_net.o io.o ifconfig_bus.o -obj-y := stubs.o sgi_if.o pciio.o xtalk.o xbow.o xswitch.o klgraph_hack.o \ - hcl.o labelcl.o invent.o klgraph.o klconflib.o sgi_io_sim.o \ - module.o sgi_io_init.o klgraph_hack.o ml_SN_init.o \ - ml_iograph.o hcl_util.o cdl.o hubdev.o hubspc.o \ - alenlist.o pci_bus_cvlink.o \ - eeprom.o pci.o pci_dma.o l1.o l1_command.o ate_utils.o \ - ifconfig_net.o efi-rtc.o io.o - -obj-$(CONFIG_IA64_SGI_SN1) += sn1/ml_SN_intr.o sn1/mem_refcnt.o sn1/hubcounters.o \ - sn1/ip37.o sn1/huberror.o sn1/hub_intr.o sn1/pcibr.o - -obj-$(CONFIG_IA64_SGI_SN2) += sn2/ml_SN_intr.o sn2/shub_intr.o sn2/shuberror.o \ - sn2/bte_error.o \ - sn2/pcibr/pcibr_dvr.o sn2/pcibr/pcibr_ate.o \ - sn2/pcibr/pcibr_config.o sn2/pcibr/pcibr_dvr.o \ - sn2/pcibr/pcibr_hints.o \ - sn2/pcibr/pcibr_idbg.o sn2/pcibr/pcibr_intr.o \ - sn2/pcibr/pcibr_rrb.o sn2/pcibr/pcibr_slot.o - -obj-$(CONFIG_PCIBA) += pciba.o +obj-$(CONFIG_PCIBA) += pciba.o diff -Nru a/arch/ia64/sn/io/alenlist.c b/arch/ia64/sn/io/alenlist.c --- a/arch/ia64/sn/io/alenlist.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/alenlist.c Wed Jan 15 16:57:29 2003 @@ -192,9 +192,9 @@ #define AL_FIXED_SIZE 0x1 /* List is pre-allocated, and of fixed size */ -zone_t *alenlist_zone = NULL; -zone_t *alenlist_chunk_zone = NULL; -zone_t *alenlist_cursor_zone = NULL; +struct zone *alenlist_zone = NULL; +struct zone *alenlist_chunk_zone = NULL; +struct zone *alenlist_cursor_zone = NULL; #if DEBUG int alenlist_count=0; /* Currently allocated Lists */ diff -Nru a/arch/ia64/sn/io/ate_utils.c b/arch/ia64/sn/io/ate_utils.c --- a/arch/ia64/sn/io/ate_utils.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/ate_utils.c Wed Jan 15 16:57:29 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: ate_utils.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff -Nru a/arch/ia64/sn/io/cdl.c b/arch/ia64/sn/io/cdl.c --- a/arch/ia64/sn/io/cdl.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/io/cdl.c Wed Jan 15 16:57:28 2003 @@ -7,6 +7,7 @@ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ +#include #include #include #include @@ -19,6 +20,8 @@ /* these get called directly in cdl_add_connpt in fops bypass hack */ extern int pcibr_attach(devfs_handle_t); extern int xbow_attach(devfs_handle_t); +extern int pic_attach(devfs_handle_t); + /* * cdl: Connection and Driver List @@ -35,13 +38,24 @@ int (*attach) (devfs_handle_t); } dummy_reg; +#ifdef CONFIG_IA64_SGI_SN1 #define MAX_SGI_IO_INFRA_DRVR 4 -struct cdl sgi_infrastructure_drivers[MAX_SGI_IO_INFRA_DRVR] = +#else +#define MAX_SGI_IO_INFRA_DRVR 7 +#endif +static struct cdl sgi_infrastructure_drivers[MAX_SGI_IO_INFRA_DRVR] = { { XBRIDGE_WIDGET_PART_NUM, XBRIDGE_WIDGET_MFGR_NUM, pcibr_attach /* &pcibr_fops */}, { BRIDGE_WIDGET_PART_NUM, BRIDGE_WIDGET_MFGR_NUM, pcibr_attach /* &pcibr_fops */}, +#ifndef CONFIG_IA64_SGI_SN1 + { PIC_WIDGET_PART_NUM_BUS0, PIC_WIDGET_MFGR_NUM, pic_attach /* &pic_fops */}, + { PIC_WIDGET_PART_NUM_BUS1, PIC_WIDGET_MFGR_NUM, pic_attach /* &pic_fops */}, +#endif { XXBOW_WIDGET_PART_NUM, XXBOW_WIDGET_MFGR_NUM, xbow_attach /* &xbow_fops */}, { XBOW_WIDGET_PART_NUM, XBOW_WIDGET_MFGR_NUM, xbow_attach /* &xbow_fops */}, +#ifndef CONFIG_IA64_SGI_SN1 + { PXBOW_WIDGET_PART_NUM, XXBOW_WIDGET_MFGR_NUM, xbow_attach /* &xbow_fops */}, +#endif }; /* diff -Nru a/arch/ia64/sn/io/hcl.c b/arch/ia64/sn/io/hcl.c --- a/arch/ia64/sn/io/hcl.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/hcl.c Wed Jan 15 16:57:29 2003 @@ -6,7 +6,7 @@ * * hcl - SGI's Hardware Graph compatibility layer. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #include @@ -155,7 +155,7 @@ /* * Create the hwgraph_root on devfs. */ - rv = hwgraph_path_add(NULL, "hw", &hwgraph_root); + rv = hwgraph_path_add(NULL, EDGE_LBL_HW, &hwgraph_root); if (rv) printk ("WARNING: init_hcl: Failed to create hwgraph_root. Error = %d.\n", rv); @@ -183,9 +183,9 @@ /* * Create the directory that links Linux bus numbers to our Xwidget. */ - rv = hwgraph_path_add(hwgraph_root, "linux/busnum", &linux_busnum); + rv = hwgraph_path_add(hwgraph_root, EDGE_LBL_LINUX_BUS, &linux_busnum); if (linux_busnum == NULL) { - panic("HCL: Unable to create hw/linux/busnum\n"); + panic("HCL: Unable to create %s\n", EDGE_LBL_LINUX_BUS); return(0); } @@ -674,7 +674,6 @@ */ namelen = (int) strlen(name); target_handle = devfs_get_handle(from, name, 1); /* Yes traverse symbolic links */ - devfs_put(target_handle); /* Assume we're the owner */ if (target_handle == NULL) return(-1); else @@ -955,7 +954,6 @@ *vertex_handle_ptr = devfs_get_handle(start_vertex_handle, /* start dir */ lookup_path, /* path */ 1); /* traverse symlinks */ - devfs_put(*vertex_handle_ptr); /* Assume we're the owner */ if (*vertex_handle_ptr == NULL) return(-1); else @@ -963,20 +961,19 @@ } /* - * hwgraph_traverse - Find and return the devfs handle starting from dir. + * hwgraph_traverse - Find and return the devfs handle starting from de. * */ graph_error_t -hwgraph_traverse(devfs_handle_t dir, char *path, devfs_handle_t *found) +hwgraph_traverse(devfs_handle_t de, char *path, devfs_handle_t *found) { /* * get the directory entry (path should end in a directory) */ - *found = devfs_get_handle(dir, /* start dir */ + *found = devfs_get_handle(de, /* start dir */ path, /* path */ 1); /* traverse symlinks */ - devfs_put(*found); /* Assume we're the owner */ if (*found == NULL) return(GRAPH_NOT_FOUND); else @@ -990,13 +987,9 @@ devfs_handle_t hwgraph_path_to_vertex(char *path) { - devfs_handle_t de; - - de = devfs_get_handle(NULL, /* start dir */ + return(devfs_get_handle(NULL, /* start dir */ path, /* path */ - 1); - devfs_put(de); /* Assume we're the owner */ - return(de); + 1)); /* traverse symlinks */ } /* @@ -1014,34 +1007,26 @@ /* * hwgraph_block_device_get - return the handle of the block device file. - * The assumption here is that dir is a directory. + * The assumption here is that de is a directory. */ devfs_handle_t -hwgraph_block_device_get(devfs_handle_t dir) +hwgraph_block_device_get(devfs_handle_t de) { - devfs_handle_t de; - - de = devfs_get_handle(dir, /* start dir */ + return(devfs_get_handle(de, /* start dir */ "block", /* path */ - 1); /* traverse symlinks */ - devfs_put(de); /* Assume we're the owner */ - return(de); + 1)); /* traverse symlinks */ } /* * hwgraph_char_device_get - return the handle of the char device file. - * The assumption here is that dir is a directory. + * The assumption here is that de is a directory. */ devfs_handle_t -hwgraph_char_device_get(devfs_handle_t dir) +hwgraph_char_device_get(devfs_handle_t de) { - devfs_handle_t de; - - de = devfs_get_handle(dir, /* start dir */ + return(devfs_get_handle(de, /* start dir */ "char", /* path */ - 1); /* traverse symlinks */ - devfs_put(de); /* Assume we're the owner */ - return(de); + 1)); /* traverse symlinks */ } /* diff -Nru a/arch/ia64/sn/io/hcl_util.c b/arch/ia64/sn/io/hcl_util.c --- a/arch/ia64/sn/io/hcl_util.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/hcl_util.c Wed Jan 15 16:57:29 2003 @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #include @@ -93,6 +93,33 @@ } vhdl = master; + } +} + +static devfs_handle_t hwgraph_all_cpuids = GRAPH_VERTEX_NONE; +extern int maxcpus; + +void +mark_cpuvertex_as_cpu(devfs_handle_t vhdl, cpuid_t cpuid) +{ + if (cpuid == CPU_NONE) + return; + + (void)labelcl_info_add_LBL(vhdl, INFO_LBL_CPUID, INFO_DESC_EXPORT, + (arbitrary_info_t)cpuid); + { + char cpuid_buffer[10]; + + if (hwgraph_all_cpuids == GRAPH_VERTEX_NONE) { + (void)hwgraph_path_add( hwgraph_root, + EDGE_LBL_CPUNUM, + &hwgraph_all_cpuids); + } + + sprintf(cpuid_buffer, "%ld", cpuid); + (void)hwgraph_edge_add( hwgraph_all_cpuids, + vhdl, + cpuid_buffer); } } diff -Nru a/arch/ia64/sn/io/hubdev.c b/arch/ia64/sn/io/hubdev.c --- a/arch/ia64/sn/io/hubdev.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/hubdev.c Wed Jan 15 16:57:29 2003 @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #include diff -Nru a/arch/ia64/sn/io/hubspc.c b/arch/ia64/sn/io/hubspc.c --- a/arch/ia64/sn/io/hubspc.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/hubspc.c Wed Jan 15 16:57:29 2003 @@ -52,7 +52,7 @@ }cpuprom_info_t; static cpuprom_info_t *cpuprom_head; -spinlock_t cpuprom_spinlock; +static spinlock_t cpuprom_spinlock; #define PROM_LOCK() mutex_spinlock(&cpuprom_spinlock) #define PROM_UNLOCK(s) mutex_spinunlock(&cpuprom_spinlock, (s)) @@ -161,69 +161,8 @@ sizeof(invent_miscinfo_t)); } -#define FPROM_CONFIG_ADDR MD_JUNK_BUS_TIMING -#define FPROM_ENABLE_MASK MJT_FPROM_ENABLE_MASK -#define FPROM_ENABLE_SHFT MJT_FPROM_ENABLE_SHFT -#define FPROM_SETUP_MASK MJT_FPROM_SETUP_MASK -#define FPROM_SETUP_SHFT MJT_FPROM_SETUP_SHFT +#endif /* CONFIG_IA64_SGI_SN1 */ -/*ARGSUSED*/ -int -cpuprom_map(devfs_handle_t dev, vhandl_t *vt, off_t addr, size_t len) -{ - int errcode = 0; - caddr_t kvaddr; - devfs_handle_t node; - cnodeid_t cnode; - - node = prominfo_nodeget(dev); - - if (!node) - return EIO; - - - kvaddr = hubdev_prombase_get(node); - cnode = hubdev_cnodeid_get(node); -#ifdef HUBSPC_DEBUG - printk("cpuprom_map: hubnode %d kvaddr 0x%x\n", node, kvaddr); -#endif - - if (len > RBOOT_SIZE) - len = RBOOT_SIZE; - /* - * Map in the prom space - */ - errcode = v_mapphys(vt, kvaddr, len); - - if (errcode == 0 ){ - /* - * Set the MD configuration registers suitably. - */ - nasid_t nasid; - uint64_t value; - volatile hubreg_t *regaddr; - - nasid = COMPACT_TO_NASID_NODEID(cnode); - regaddr = REMOTE_HUB_ADDR(nasid, FPROM_CONFIG_ADDR); - value = HUB_L(regaddr); - value &= ~(FPROM_SETUP_MASK | FPROM_ENABLE_MASK); - { - value |= (((long)CONFIG_FPROM_SETUP << FPROM_SETUP_SHFT) | - ((long)CONFIG_FPROM_ENABLE << FPROM_ENABLE_SHFT)); - } - HUB_S(regaddr, value); - - } - return (errcode); -} -#endif /* CONFIG_IA64_SGI_SN1 */ - -/*ARGSUSED*/ -int -cpuprom_unmap(devfs_handle_t dev, vhandl_t *vt) -{ - return 0; -} /***********************************************************************/ /* Base Hub Space Driver */ @@ -245,15 +184,14 @@ hubdev_register(mem_refcnt_attach); #endif -#if defined(CONFIG_SERIAL_SGI_L1_PROTOCOL) +#ifdef CONFIG_IA64_SGI_SN1 /* L1 system controller link */ if ( !IS_RUNNING_ON_SIMULATOR() ) { /* initialize the L1 link */ extern void l1_init(void); l1_init(); } -#endif - +#endif /* CONFIG_IA64_SGI_SN1 */ #ifdef HUBSPC_DEBUG printk("hubspc_init: Completed\n"); #endif /* HUBSPC_DEBUG */ @@ -285,7 +223,7 @@ /* check validity of request */ if( len == 0 ) { - return ENXIO; + return -ENXIO; } return errcode; diff -Nru a/arch/ia64/sn/io/ifconfig_net.c b/arch/ia64/sn/io/ifconfig_net.c --- a/arch/ia64/sn/io/ifconfig_net.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/io/ifconfig_net.c Wed Jan 15 16:57:28 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: ifconfig_net.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -202,30 +202,16 @@ * Read in the header and see how big of a buffer we really need to * allocate. */ - ifname_num = kmalloc(sizeof(struct ifname_num), GFP_KERNEL); - if (!ifname_num) - return -ENOMEM; - if (copy_from_user(ifname_num, (char *)arg, - sizeof(struct ifname_num))) { - kfree(ifname_num); - return -EFAULT; - } + ifname_num = (struct ifname_num *) kmalloc(sizeof(struct ifname_num), + GFP_KERNEL); + copy_from_user( ifname_num, (char *) arg, sizeof(struct ifname_num)); size = ifname_num->size; kfree(ifname_num); - ifname_num = kmalloc(size, GFP_KERNEL); - if (!ifname_num) - return -ENOMEM; + ifname_num = (struct ifname_num *) kmalloc(size, GFP_KERNEL); ifname_MAC = (struct ifname_MAC *) ((char *)ifname_num + (sizeof(struct ifname_num)) ); - if (copy_from_user(ifname_num, (char *)arg, size)) { - kfree(ifname_num); - return -EFAULT; - } + copy_from_user( ifname_num, (char *) arg, size); new_devices = kmalloc(size - sizeof(struct ifname_num), GFP_KERNEL); - if (!new_devices) { - kfree(ifname_num); - return -EFAULT; - } temp_new_devices = new_devices; memset(new_devices, 0, size - sizeof(struct ifname_num)); @@ -271,17 +257,17 @@ /* * Copy back to the User Buffer area any new devices encountered. */ - if (copy_to_user((char *)arg + (sizeof(struct ifname_num)), - new_devices, size - sizeof(struct ifname_num))) - return -EFAULT; + copy_to_user((char *)arg + (sizeof(struct ifname_num)), new_devices, + size - sizeof(struct ifname_num)); + return(0); } struct file_operations ifconfig_net_fops = { - .ioctl =ifconfig_net_ioctl, /* ioctl */ - .open =ifconfig_net_open, /* open */ - .release =ifconfig_net_close /* release */ + ioctl:ifconfig_net_ioctl, /* ioctl */ + open:ifconfig_net_open, /* open */ + release:ifconfig_net_close /* release */ }; diff -Nru a/arch/ia64/sn/io/invent.c b/arch/ia64/sn/io/invent.c --- a/arch/ia64/sn/io/invent.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/invent.c Wed Jan 15 16:57:29 2003 @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ /* diff -Nru a/arch/ia64/sn/io/io.c b/arch/ia64/sn/io/io.c --- a/arch/ia64/sn/io/io.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/io.c Wed Jan 15 16:57:29 2003 @@ -7,6 +7,7 @@ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc. All Rights Reserved. */ +#include #include #include #include @@ -31,21 +32,6 @@ extern void hub_intr_init(devfs_handle_t hubv); -/* - * hub_device_desc_update - * Update the passed in device descriptor with the actual the - * target cpu number and interrupt priority level. - * NOTE : These might be the same as the ones passed in thru - * the descriptor. - */ -void -hub_device_desc_update(device_desc_t dev_desc, - ilvl_t intr_swlevel, - cpuid_t cpu) -{ -} - - /* * Perform any initializations needed to support hub-based I/O. * Called once during startup. @@ -53,11 +39,6 @@ void hubio_init(void) { -#ifdef LATER - /* This isn't needed unless we port the entire sio driver ... */ - extern void early_brl1_port_init( void ); - early_brl1_port_init(); -#endif } /* @@ -149,6 +130,10 @@ nasid_t nasid; volatile hubreg_t junk; unsigned long s; + caddr_t kvaddr; +#ifdef PIOMAP_UNC_ACC_SPACE + uint64_t addr; +#endif /* sanity check */ if (byte_count_max > byte_count) @@ -159,8 +144,19 @@ /* If xtalk_addr range is mapped by a small window, we don't have * to do much */ - if (xtalk_addr + byte_count <= SWIN_SIZE) - return(hubinfo_swin_piomap_get(hubinfo, (int)widget)); + if (xtalk_addr + byte_count <= SWIN_SIZE) { + hub_piomap_t piomap; + + piomap = hubinfo_swin_piomap_get(hubinfo, (int)widget); +#ifdef PIOMAP_UNC_ACC_SPACE + if (flags & PIOMAP_UNC_ACC) { + addr = (uint64_t)piomap->hpio_xtalk_info.xp_kvaddr; + addr |= PIOMAP_UNC_ACC_SPACE; + piomap->hpio_xtalk_info.xp_kvaddr = (caddr_t)addr; + } +#endif + return piomap; + } /* We need to use a big window mapping. */ @@ -257,7 +253,15 @@ bw_piomap->hpio_xtalk_info.xp_dev = dev; bw_piomap->hpio_xtalk_info.xp_target = widget; bw_piomap->hpio_xtalk_info.xp_xtalk_addr = xtalk_addr; - bw_piomap->hpio_xtalk_info.xp_kvaddr = (caddr_t)NODE_BWIN_BASE(nasid, free_bw_index); + kvaddr = (caddr_t)NODE_BWIN_BASE(nasid, free_bw_index); +#ifdef PIOMAP_UNC_ACC_SPACE + if (flags & PIOMAP_UNC_ACC) { + addr = (uint64_t)kvaddr; + addr |= PIOMAP_UNC_ACC_SPACE; + kvaddr = (caddr_t)addr; + } +#endif + bw_piomap->hpio_xtalk_info.xp_kvaddr = kvaddr; bw_piomap->hpio_holdcnt++; bw_piomap->hpio_bigwin_num = free_bw_index; @@ -378,12 +382,22 @@ devfs_handle_t hubv = xwidget_info_master_get(widget_info); hub_piomap_t hub_piomap; hubinfo_t hubinfo; + caddr_t addr; hubinfo_get(hubv, &hubinfo); if (xtalk_addr + byte_count <= SWIN_SIZE) { hub_piomap = hubinfo_swin_piomap_get(hubinfo, (int)widget); - return(hub_piomap_addr(hub_piomap, xtalk_addr, byte_count)); + addr = hub_piomap_addr(hub_piomap, xtalk_addr, byte_count); +#ifdef PIOMAP_UNC_ACC_SPACE + if (flags & PIOMAP_UNC_ACC) { + uint64_t iaddr; + iaddr = (uint64_t)addr; + iaddr |= PIOMAP_UNC_ACC_SPACE; + addr = (caddr_t)iaddr; + } +#endif + return(addr); } else return(0); } @@ -392,19 +406,6 @@ /* DMA MANAGEMENT */ /* Mapping from crosstalk space to system physical space */ -/* - * There's not really very much to do here, since crosstalk maps - * directly to system physical space. It's quite possible that this - * DMA layer will be bypassed in performance kernels. - */ - - -/* ARGSUSED */ -void -hub_dma_init(devfs_handle_t hubv) -{ -} - /* * Allocate resources needed to set up DMA mappings up to a specified size @@ -478,7 +479,12 @@ } /* There isn't actually any DMA mapping hardware on the hub. */ - return(paddr); +#ifdef CONFIG_IA64_SGI_SN2 + return( (PHYS_TO_DMA(paddr)) ); +#else + /* no translation needed */ + return(paddr); +#endif } /* @@ -549,8 +555,12 @@ size_t byte_count, /* length */ unsigned flags) /* defined in dma.h */ { +#ifdef CONFIG_IA64_SGI_SN2 + return( (PHYS_TO_DMA(paddr)) ); +#else /* no translation needed */ return(paddr); +#endif } /* @@ -565,6 +575,7 @@ alenlist_t palenlist, /* system address/length list */ unsigned flags) /* defined in dma.h */ { + BUG(); /* no translation needed */ return(palenlist); } @@ -603,11 +614,9 @@ void hub_provider_startup(devfs_handle_t hubv) { - extern void hub_dma_init(devfs_handle_t hubv); extern void hub_pio_init(devfs_handle_t hubv); hub_pio_init(hubv); - hub_dma_init(hubv); hub_intr_init(hubv); } @@ -707,14 +716,12 @@ { iprb_t prb; int prb_offset; -#ifdef LATER extern int force_fire_and_forget; extern volatile int ignore_conveyor_override; if (force_fire_and_forget && !ignore_conveyor_override) if (conveyor == HUB_PIO_CONVEYOR) conveyor = HUB_PIO_FIRE_N_FORGET; -#endif /* * Get the current register value. diff -Nru a/arch/ia64/sn/io/klgraph_hack.c b/arch/ia64/sn/io/klgraph_hack.c --- a/arch/ia64/sn/io/klgraph_hack.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/klgraph_hack.c Wed Jan 15 16:57:29 2003 @@ -13,13 +13,16 @@ * initial klgraph information that is normally provided by prom. */ +#include #include #include #include #include #include #include +#include +extern u64 klgraph_addr[]; void * real_port; void * real_io_base; void * real_addr; @@ -45,10 +48,15 @@ #define HUBREG ((char *)0xc0000a0001e00000) #define WIDGET0 ((char *)0xc0000a0000000000) +#define convert(a,b,c) temp = (u64 *)a; *temp = b; temp++; *temp = c + void klgraph_hack_init(void) { + u64 *temp; + +#ifdef CONFIG_IA64_SGI_SN1 /* * We need to know whether we are booting from PROM or * boot from disk. @@ -59,6 +67,139 @@ } else { panic("klgraph_hack_init: Unable to locate KLCONFIG TABLE\n"); } + + convert(0x0000000000030000, 0x00000000beedbabe, 0x0000004800000000); + +#else + + if (IS_RUNNING_ON_SIMULATOR()) { + printk("Creating FAKE Klconfig Structure for Embeded Kernel\n"); + klgraph_addr[0] = 0xe000003000030000; + + /* + * klconfig entries initialization - mankato + */ + convert(0xe000003000030000, 0x00000000beedbabe, 0x0000004800000000); + convert(0xe000003000030010, 0x0003007000000018, 0x800002000f820178); + convert(0xe000003000030020, 0x80000a000f024000, 0x800002000f800000); + convert(0xe000003000030030, 0x0300fafa00012580, 0x00000000040f0000); + convert(0xe000003000030040, 0x0000000000000000, 0x0003097000030070); + convert(0xe000003000030050, 0x00030970000303b0, 0x0003181000033f70); + convert(0xe000003000030060, 0x0003d51000037570, 0x0000000000038330); + convert(0xe000003000030070, 0x0203110100030140, 0x0001000000000101); + convert(0xe000003000030080, 0x0900000000000000, 0x000000004e465e67); + convert(0xe000003000030090, 0x0003097000000000, 0x00030b1000030a40); + convert(0xe0000030000300a0, 0x00030cb000030be0, 0x000315a0000314d0); + convert(0xe0000030000300b0, 0x0003174000031670, 0x0000000000000000); + convert(0xe000003000030100, 0x000000000000001a, 0x3350490000000000); + convert(0xe000003000030110, 0x0000000000000037, 0x0000000000000000); + convert(0xe000003000030140, 0x0002420100030210, 0x0001000000000101); + convert(0xe000003000030150, 0x0100000000000000, 0xffffffffffffffff); + convert(0xe000003000030160, 0x00030d8000000000, 0x0000000000030e50); + convert(0xe0000030000301c0, 0x0000000000000000, 0x0000000000030070); + convert(0xe0000030000301d0, 0x0000000000000025, 0x424f490000000000); + convert(0xe0000030000301e0, 0x000000004b434952, 0x0000000000000000); + convert(0xe000003000030210, 0x00027101000302e0, 0x00010000000e4101); + convert(0xe000003000030220, 0x0200000000000000, 0xffffffffffffffff); + convert(0xe000003000030230, 0x00030f2000000000, 0x0000000000030ff0); + convert(0xe000003000030290, 0x0000000000000000, 0x0000000000030140); + convert(0xe0000030000302a0, 0x0000000000000026, 0x7262490000000000); + convert(0xe0000030000302b0, 0x00000000006b6369, 0x0000000000000000); + convert(0xe0000030000302e0, 0x0002710100000000, 0x00010000000f3101); + convert(0xe0000030000302f0, 0x0500000000000000, 0xffffffffffffffff); + convert(0xe000003000030300, 0x000310c000000000, 0x0003126000031190); + convert(0xe000003000030310, 0x0003140000031330, 0x0000000000000000); + convert(0xe000003000030360, 0x0000000000000000, 0x0000000000030140); + convert(0xe000003000030370, 0x0000000000000029, 0x7262490000000000); + convert(0xe000003000030380, 0x00000000006b6369, 0x0000000000000000); + convert(0xe000003000030970, 0x0000000002010102, 0x0000000000000000); + convert(0xe000003000030980, 0x000000004e465e67, 0xffffffff00000000); + /* convert(0x00000000000309a0, 0x0000000000037570, 0x0000000100000000); */ + convert(0xe0000030000309a0, 0x0000000000037570, 0xffffffff00000000); + convert(0xe0000030000309b0, 0x0000000000030070, 0x0000000000000000); + convert(0xe0000030000309c0, 0x000000000003f420, 0x0000000000000000); + convert(0xe000003000030a40, 0x0000000002010125, 0x0000000000000000); + convert(0xe000003000030a50, 0xffffffffffffffff, 0xffffffff00000000); + convert(0xe000003000030a70, 0x0000000000037b78, 0x0000000000000000); + convert(0xe000003000030b10, 0x0000000002010125, 0x0000000000000000); + convert(0xe000003000030b20, 0xffffffffffffffff, 0xffffffff00000000); + convert(0xe000003000030b40, 0x0000000000037d30, 0x0000000000000001); + convert(0xe000003000030be0, 0x00000000ff010203, 0x0000000000000000); + convert(0xe000003000030bf0, 0xffffffffffffffff, 0xffffffff000000ff); + convert(0xe000003000030c10, 0x0000000000037ee8, 0x0100010000000200); + convert(0xe000003000030cb0, 0x00000000ff310111, 0x0000000000000000); + convert(0xe000003000030cc0, 0xffffffffffffffff, 0x0000000000000000); + convert(0xe000003000030d80, 0x0000000002010104, 0x0000000000000000); + convert(0xe000003000030d90, 0xffffffffffffffff, 0x00000000000000ff); + convert(0xe000003000030db0, 0x0000000000037f18, 0x0000000000000000); + convert(0xe000003000030dc0, 0x0000000000000000, 0x0003007000060000); + convert(0xe000003000030de0, 0x0000000000000000, 0x0003021000050000); + convert(0xe000003000030df0, 0x000302e000050000, 0x0000000000000000); + convert(0xe000003000030e30, 0x0000000000000000, 0x000000000000000a); + convert(0xe000003000030e50, 0x00000000ff00011a, 0x0000000000000000); + convert(0xe000003000030e60, 0xffffffffffffffff, 0x0000000000000000); + convert(0xe000003000030e80, 0x0000000000037fe0, 0x9e6e9e9e9e9e9e9e); + convert(0xe000003000030e90, 0x000000000000bc6e, 0x0000000000000000); + convert(0xe000003000030f20, 0x0000000002010205, 0x00000000d0020000); + convert(0xe000003000030f30, 0xffffffffffffffff, 0x0000000e0000000e); + convert(0xe000003000030f40, 0x000000000000000e, 0x0000000000000000); + convert(0xe000003000030f50, 0x0000000000038010, 0x00000000000007ff); + convert(0xe000003000030f70, 0x0000000000000000, 0x0000000022001077); + convert(0xe000003000030fa0, 0x0000000000000000, 0x000000000003f4a8); + convert(0xe000003000030ff0, 0x0000000000310120, 0x0000000000000000); + convert(0xe000003000031000, 0xffffffffffffffff, 0xffffffff00000002); + convert(0xe000003000031010, 0x000000000000000e, 0x0000000000000000); + convert(0xe000003000031020, 0x0000000000038088, 0x0000000000000000); + convert(0xe0000030000310c0, 0x0000000002010205, 0x00000000d0020000); + convert(0xe0000030000310d0, 0xffffffffffffffff, 0x0000000f0000000f); + convert(0xe0000030000310e0, 0x000000000000000f, 0x0000000000000000); + convert(0xe0000030000310f0, 0x00000000000380b8, 0x00000000000007ff); + convert(0xe000003000031120, 0x0000000022001077, 0x00000000000310a9); + convert(0xe000003000031130, 0x00000000580211c1, 0x000000008009104c); + convert(0xe000003000031140, 0x0000000000000000, 0x000000000003f4c0); + convert(0xe000003000031190, 0x0000000000310120, 0x0000000000000000); + convert(0xe0000030000311a0, 0xffffffffffffffff, 0xffffffff00000003); + convert(0xe0000030000311b0, 0x000000000000000f, 0x0000000000000000); + convert(0xe0000030000311c0, 0x0000000000038130, 0x0000000000000000); + convert(0xe000003000031260, 0x0000000000110106, 0x0000000000000000); + convert(0xe000003000031270, 0xffffffffffffffff, 0xffffffff00000004); + convert(0xe000003000031270, 0xffffffffffffffff, 0xffffffff00000004); + convert(0xe000003000031280, 0x000000000000000f, 0x0000000000000000); + convert(0xe0000030000312a0, 0x00000000ff110013, 0x0000000000000000); + convert(0xe0000030000312b0, 0xffffffffffffffff, 0xffffffff00000000); + convert(0xe0000030000312c0, 0x000000000000000f, 0x0000000000000000); + convert(0xe0000030000312e0, 0x0000000000110012, 0x0000000000000000); + convert(0xe0000030000312f0, 0xffffffffffffffff, 0xffffffff00000000); + convert(0xe000003000031300, 0x000000000000000f, 0x0000000000000000); + convert(0xe000003000031310, 0x0000000000038160, 0x0000000000000000); + convert(0xe000003000031330, 0x00000000ff310122, 0x0000000000000000); + convert(0xe000003000031340, 0xffffffffffffffff, 0xffffffff00000005); + convert(0xe000003000031350, 0x000000000000000f, 0x0000000000000000); + convert(0xe000003000031360, 0x0000000000038190, 0x0000000000000000); + convert(0xe000003000031400, 0x0000000000310121, 0x0000000000000000); + convert(0xe000003000031400, 0x0000000000310121, 0x0000000000000000); + convert(0xe000003000031410, 0xffffffffffffffff, 0xffffffff00000006); + convert(0xe000003000031420, 0x000000000000000f, 0x0000000000000000); + convert(0xe000003000031430, 0x00000000000381c0, 0x0000000000000000); + convert(0xe0000030000314d0, 0x00000000ff010201, 0x0000000000000000); + convert(0xe0000030000314e0, 0xffffffffffffffff, 0xffffffff00000000); + convert(0xe000003000031500, 0x00000000000381f0, 0x000030430000ffff); + convert(0xe000003000031510, 0x000000000000ffff, 0x0000000000000000); + convert(0xe0000030000315a0, 0x00000020ff000201, 0x0000000000000000); + convert(0xe0000030000315b0, 0xffffffffffffffff, 0xffffffff00000001); + convert(0xe0000030000315d0, 0x0000000000038240, 0x00003f3f0000ffff); + convert(0xe0000030000315e0, 0x000000000000ffff, 0x0000000000000000); + convert(0xe000003000031670, 0x00000000ff010201, 0x0000000000000000); + convert(0xe000003000031680, 0xffffffffffffffff, 0x0000000100000002); + convert(0xe0000030000316a0, 0x0000000000038290, 0x000030430000ffff); + convert(0xe0000030000316b0, 0x000000000000ffff, 0x0000000000000000); + convert(0xe000003000031740, 0x00000020ff000201, 0x0000000000000000); + convert(0xe000003000031750, 0xffffffffffffffff, 0x0000000500000003); + convert(0xe000003000031770, 0x00000000000382e0, 0x00003f3f0000ffff); + convert(0xe000003000031780, 0x000000000000ffff, 0x0000000000000000); +} + +#endif } diff -Nru a/arch/ia64/sn/io/labelcl.c b/arch/ia64/sn/io/labelcl.c --- a/arch/ia64/sn/io/labelcl.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/labelcl.c Wed Jan 15 16:57:29 2003 @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. */ #include diff -Nru a/arch/ia64/sn/io/pci.c b/arch/ia64/sn/io/pci.c --- a/arch/ia64/sn/io/pci.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/io/pci.c Wed Jan 15 16:57:28 2003 @@ -6,7 +6,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1997, 1998, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 1997, 1998, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #include #include @@ -44,21 +44,22 @@ extern devfs_handle_t devfn_to_vertex(unsigned char bus, unsigned char devfn); /* - * snia64_read - Read from the config area of the device. + * snia64_read_config_byte - Read a byte from the config area of the device. */ -static int snia64_read (struct pci_bus *bus, unsigned char devfn, - int where, int size, unsigned char *val) +static int snia64_read_config_byte (struct pci_dev *dev, + int where, unsigned char *val) { unsigned long res = 0; + unsigned size = 1; devfs_handle_t device_vertex; - if ( (bus == NULL) || (val == (unsigned char *)0) ) { + if ( (dev == (struct pci_dev *)0) || (val == (unsigned char *)0) ) { return PCIBIOS_DEVICE_NOT_FOUND; } - device_vertex = devfn_to_vertex(bus->number, devfn); + device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn); if (!device_vertex) { DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n", - __FUNCTION__, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); + __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); return(-1); } res = pciio_config_get(device_vertex, (unsigned) where, size); @@ -67,49 +68,169 @@ } /* - * snia64_write - Writes to the config area of the device. + * snia64_read_config_word - Read 2 bytes from the config area of the device. */ -static int snia64_write (struct pci_bus *bus, unsigned char devfn, - int where, int size, unsigned char val) +static int snia64_read_config_word (struct pci_dev *dev, + int where, unsigned short *val) { + unsigned long res = 0; + unsigned size = 2; /* 2 bytes */ devfs_handle_t device_vertex; - if ( bus == NULL) { + if ( (dev == (struct pci_dev *)0) || (val == (unsigned short *)0) ) { + return PCIBIOS_DEVICE_NOT_FOUND; + } + device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn); + if (!device_vertex) { + DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n", + __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); + return(-1); + } + res = pciio_config_get(device_vertex, (unsigned) where, size); + *val = (unsigned short) res; + return PCIBIOS_SUCCESSFUL; +} + +/* + * snia64_read_config_dword - Read 4 bytes from the config area of the device. + */ +static int snia64_read_config_dword (struct pci_dev *dev, + int where, unsigned int *val) +{ + unsigned long res = 0; + unsigned size = 4; /* 4 bytes */ + devfs_handle_t device_vertex; + + if (where & 3) { + return PCIBIOS_BAD_REGISTER_NUMBER; + } + if ( (dev == (struct pci_dev *)0) || (val == (unsigned int *)0) ) { + return PCIBIOS_DEVICE_NOT_FOUND; + } + + device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn); + if (!device_vertex) { + DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n", + __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); + return(-1); + } + res = pciio_config_get(device_vertex, (unsigned) where, size); + *val = (unsigned int) res; + return PCIBIOS_SUCCESSFUL; +} + +/* + * snia64_write_config_byte - Writes 1 byte to the config area of the device. + */ +static int snia64_write_config_byte (struct pci_dev *dev, + int where, unsigned char val) +{ + devfs_handle_t device_vertex; + + if ( dev == (struct pci_dev *)0 ) { return PCIBIOS_DEVICE_NOT_FOUND; } /* * if it's an IOC3 then we bail out, we special * case them with pci_fixup_ioc3 */ - /* Starting 2.5.32 struct pci_dev is not passed down */ - /*if (dev->vendor == PCI_VENDOR_ID_SGI && + if (dev->vendor == PCI_VENDOR_ID_SGI && dev->device == PCI_DEVICE_ID_SGI_IOC3 ) return PCIBIOS_SUCCESSFUL; - */ - device_vertex = devfn_to_vertex(bus->number, devfn); + device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn); + if (!device_vertex) { + DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n", + __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); + return(-1); + } + pciio_config_set( device_vertex, (unsigned)where, 1, (uint64_t) val); + + return PCIBIOS_SUCCESSFUL; +} + +/* + * snia64_write_config_word - Writes 2 bytes to the config area of the device. + */ +static int snia64_write_config_word (struct pci_dev *dev, + int where, unsigned short val) +{ + devfs_handle_t device_vertex = NULL; + + if (where & 1) { + return PCIBIOS_BAD_REGISTER_NUMBER; + } + if ( dev == (struct pci_dev *)0 ) { + return PCIBIOS_DEVICE_NOT_FOUND; + } + /* + * if it's an IOC3 then we bail out, we special + * case them with pci_fixup_ioc3 + */ + if (dev->vendor == PCI_VENDOR_ID_SGI && + dev->device == PCI_DEVICE_ID_SGI_IOC3) + return PCIBIOS_SUCCESSFUL; + + device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn); if (!device_vertex) { DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n", - __FUNCTION__, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); + __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); return(-1); } - pciio_config_set( device_vertex, (unsigned)where, size, (uint64_t) val); + pciio_config_set( device_vertex, (unsigned)where, 2, (uint64_t) val); + + return PCIBIOS_SUCCESSFUL; +} + +/* + * snia64_write_config_dword - Writes 4 bytes to the config area of the device. + */ +static int snia64_write_config_dword (struct pci_dev *dev, + int where, unsigned int val) +{ + devfs_handle_t device_vertex; + + if (where & 3) { + return PCIBIOS_BAD_REGISTER_NUMBER; + } + if ( dev == (struct pci_dev *)0 ) { + return PCIBIOS_DEVICE_NOT_FOUND; + } + /* + * if it's an IOC3 then we bail out, we special + * case them with pci_fixup_ioc3 + */ + if (dev->vendor == PCI_VENDOR_ID_SGI && + dev->device == PCI_DEVICE_ID_SGI_IOC3) + return PCIBIOS_SUCCESSFUL; + + device_vertex = devfn_to_vertex(dev->bus->number, dev->devfn); + if (!device_vertex) { + DBG("%s : nonexistent device: bus= 0x%x slot= 0x%x func= 0x%x\n", + __FUNCTION__, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); + return(-1); + } + pciio_config_set( device_vertex, (unsigned)where, 4, (uint64_t) val); return PCIBIOS_SUCCESSFUL; } static struct pci_ops snia64_pci_ops = { - .read = snia64_read, - .write = snia64_write, + snia64_read_config_byte, + snia64_read_config_word, + snia64_read_config_dword, + snia64_write_config_byte, + snia64_write_config_word, + snia64_write_config_dword }; /* * snia64_pci_find_bios - SNIA64 pci_find_bios() platform specific code. */ void __init -sn1_pci_find_bios(void) +sn_pci_find_bios(void) { - extern struct pci_ops pci_conf; + extern struct pci_ops *pci_root_ops; /* * Go initialize our IO Infrastructure .. */ @@ -117,8 +238,8 @@ sgi_master_io_infr_init(); - /* sn1_io_infrastructure_init(); */ - pci_conf = snia64_pci_ops; + /* sn_io_infrastructure_init(); */ + pci_root_ops = &snia64_pci_ops; } void @@ -155,22 +276,16 @@ d->resource[i].flags = 0UL; } - /* - * Hardcode Device 4 register(IOC3 is in Slot 4) to set the - * DEV_DIRECT bit. This will not work if IOC3 is not on Slot - * 4. - */ - DBG("pci_fixup_ioc3: FIXME .. need to take NASID into account when setting IOC3 devreg 0x%x\n", *(volatile u32 *)0xc0000a000f000220); - - *(volatile u32 *)0xc0000a000f000220 |= 0x90000; - +#ifdef CONFIG_IA64_SGI_SN1 + *(volatile u32 *)0xc0000a000f000220 |= 0x90000; +#endif d->subsystem_vendor = 0; d->subsystem_device = 0; } #else -void sn1_pci_find_bios(void) {} +void sn_pci_find_bios(void) {} void pci_fixup_ioc3(struct pci_dev *d) {} struct list_head pci_root_buses; struct list_head pci_root_buses; diff -Nru a/arch/ia64/sn/io/pci_dma.c b/arch/ia64/sn/io/pci_dma.c --- a/arch/ia64/sn/io/pci_dma.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/io/pci_dma.c Wed Jan 15 16:57:28 2003 @@ -9,6 +9,7 @@ * a description of how these routines should be used. */ +#include #include #include #include @@ -31,232 +32,316 @@ #include #include +/* + * For ATE allocations + */ pciio_dmamap_t get_free_pciio_dmamap(devfs_handle_t); void free_pciio_dmamap(pcibr_dmamap_t); -struct sn1_dma_maps_s *find_sn1_dma_map(dma_addr_t, unsigned char); +static struct sn_dma_maps_s *find_sn_dma_map(dma_addr_t, unsigned char); + +/* + * Toplogy stuff + */ extern devfs_handle_t busnum_to_pcibr_vhdl[]; extern nasid_t busnum_to_nid[]; extern void * busnum_to_atedmamaps[]; -/* - * Get a free pciio_dmamap_t entry. +/** + * get_free_pciio_dmamap - find and allocate an ATE + * @pci_bus: PCI bus to get an entry for + * + * Finds and allocates an ATE on the PCI bus specified + * by @pci_bus. */ pciio_dmamap_t get_free_pciio_dmamap(devfs_handle_t pci_bus) { int i; - struct sn1_dma_maps_s *sn1_dma_map = NULL; + struct sn_dma_maps_s *sn_dma_map = NULL; /* * Darn, we need to get the maps allocated for this bus. */ for (i = 0; i < MAX_PCI_XWIDGET; i++) { if (busnum_to_pcibr_vhdl[i] == pci_bus) { - sn1_dma_map = busnum_to_atedmamaps[i]; + sn_dma_map = busnum_to_atedmamaps[i]; } } /* * Now get a free dmamap entry from this list. */ - for (i=0; idma_addr) { - sn1_dma_map->dma_addr = -1; - return( (pciio_dmamap_t) sn1_dma_map ); + for (i = 0; i < MAX_ATE_MAPS; i++, sn_dma_map++) { + if (!sn_dma_map->dma_addr) { + sn_dma_map->dma_addr = -1; + return( (pciio_dmamap_t) sn_dma_map ); } } - return(NULL); - + return NULL; } -/* - * Free pciio_dmamap_t entry. +/** + * free_pciio_dmamap - free an ATE + * @dma_map: ATE to free + * + * Frees the ATE specified by @dma_map. */ void free_pciio_dmamap(pcibr_dmamap_t dma_map) { - struct sn1_dma_maps_s *sn1_dma_map; + struct sn_dma_maps_s *sn_dma_map; + + sn_dma_map = (struct sn_dma_maps_s *) dma_map; + sn_dma_map->dma_addr = 0; +} + +/** + * find_sn_dma_map - find an ATE associated with @dma_addr and @busnum + * @dma_addr: DMA address to look for + * @busnum: PCI bus to look on + * + * Finds the ATE associated with @dma_addr and @busnum. + */ +static struct sn_dma_maps_s * +find_sn_dma_map(dma_addr_t dma_addr, unsigned char busnum) +{ - sn1_dma_map = (struct sn1_dma_maps_s *) dma_map; - sn1_dma_map->dma_addr = 0; + struct sn_dma_maps_s *sn_dma_map = NULL; + int i; + + sn_dma_map = busnum_to_atedmamaps[busnum]; + + for (i = 0; i < MAX_ATE_MAPS; i++, sn_dma_map++) { + if (sn_dma_map->dma_addr == dma_addr) { + return sn_dma_map; + } + } + return NULL; } -/* - * sn_dma_sync: This routine flushes all DMA buffers for the device into the II. - * This does not mean that the data is in the "Coherence Domain". But it - * is very close. +/** + * sn_dma_sync - try to flush DMA buffers into the coherence domain + * @hwdev: device to flush + * + * This routine flushes all DMA buffers for the device into the II of + * the destination hub. + * + * NOTE!: this does not mean that the data is in the "coherence domain", + * but it is very close. In other words, this routine *does not work* + * as advertised due to hardware bugs. That said, it should be good enough for + * most situations. */ void -sn_dma_sync( struct pci_dev *hwdev ) +sn_dma_sync(struct pci_dev *hwdev) { - struct sn1_device_sysdata *device_sysdata; +#ifdef SN_DMA_SYNC + + struct sn_device_sysdata *device_sysdata; volatile unsigned long dummy; /* - * It is expected that on IA64 platform, a DMA sync ensures that all - * the DMA (dma_handle) are complete and coherent. - * 1. Flush Write Buffers from Bridge. - * 2. Flush Xbow Port. + * A DMA sync is supposed to ensure that + * all the DMA from a particular device + * is complete and coherent. We + * try to do this by + * 1. flushing the write wuffers from Bridge + * 2. flushing the Xbow port. + * Unfortunately, this only gets the DMA transactions 'very close' to + * the coherence domain, but not quite in it. */ - device_sysdata = (struct sn1_device_sysdata *)hwdev->sysdata; + device_sysdata = (struct sn_device_sysdata *)hwdev->sysdata; dummy = (volatile unsigned long ) *device_sysdata->dma_buf_sync; /* - * For the Xbow Port flush, we maybe denied the request because - * someone else may be flushing the Port .. try again. + * For the Xbow port flush, we may be denied the request because + * someone else may be flushing the port .. try again. */ while((volatile unsigned long ) *device_sysdata->xbow_buf_sync) { udelay(2); } +#endif } - -struct sn1_dma_maps_s * -find_sn1_dma_map(dma_addr_t dma_addr, unsigned char busnum) -{ - - struct sn1_dma_maps_s *sn1_dma_map = NULL; - int i; - - sn1_dma_map = busnum_to_atedmamaps[busnum]; - - for (i=0; idma_addr == dma_addr) { - return( sn1_dma_map ); - } - } - -printk("find_pciio_dmamap: Unable find the corresponding dma map\n"); - - return(NULL); - -} - -/* - * sn1 platform specific pci_alloc_consistent() +/** + * sn_pci_alloc_consistent - allocate memory for coherent DMA + * @hwdev: device to allocate for + * @size: size of the region + * @dma_handle: DMA (bus) address + * + * pci_alloc_consistent() returns a pointer to a memory region suitable for + * coherent DMA traffic to/from a PCI device. On SN platforms, this means + * that @dma_handle will have the %PCIIO_DMA_CMD flag set. + * + * This interface is usually used for "command" streams (e.g. the command + * queue for a SCSI controller). See Documentation/DMA-mapping.txt for + * more information. Note that this routine will always put a 32 bit + * DMA address into @dma_handle. This is because most devices + * that are capable of 64 bit PCI DMA transactions can't do 64 bit _coherent_ + * DMAs, and unfortunately this interface has to cater to the LCD. Oh well. * - * this interface is meant for "command" streams, i.e. called only - * once for initializing a device, so we don't want prefetching or - * write gathering turned on, hence the PCIIO_DMA_CMD flag + * Also known as platform_pci_alloc_consistent() by the IA64 machvec code. */ void * -sn1_pci_alloc_consistent (struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle) +sn_pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle) { - void *ret; - int gfp = GFP_ATOMIC; - devfs_handle_t vhdl; - struct sn1_device_sysdata *device_sysdata; - paddr_t temp_ptr; + void *cpuaddr; + devfs_handle_t vhdl; + struct sn_device_sysdata *device_sysdata; + unsigned long phys_addr; + pciio_dmamap_t dma_map = 0; + struct sn_dma_maps_s *sn_dma_map; - *dma_handle = (dma_addr_t) NULL; + *dma_handle = 0; + + /* We can't easily support < 32 bit devices */ + if (IS_PCI32L(hwdev)) + return NULL; /* - * get vertex for the device + * Get hwgraph vertex for the device */ - device_sysdata = (struct sn1_device_sysdata *) hwdev->sysdata; + device_sysdata = (struct sn_device_sysdata *) hwdev->sysdata; vhdl = device_sysdata->vhdl; - if ( (ret = (void *)__get_free_pages(gfp, get_order(size))) ) { - memset(ret, 0, size); - } else { - return(NULL); - } + /* + * Allocate the memory. FIXME: if we're allocating for + * two devices on the same bus, we should at least try to + * allocate memory in the same 2 GB window to avoid using + * ATEs for the translation. See the comment above about the + * 32 bit requirement for this function. + */ + if(!(cpuaddr = (void *)__get_free_pages(GFP_ATOMIC, get_order(size)))) + return NULL; - temp_ptr = (paddr_t) __pa(ret); - if (IS_PCIA64(hwdev)) { + memset(cpuaddr, 0, size); /* have to zero it out */ - /* - * This device supports 64bits DMA addresses. - */ + /* physical addr. of the memory we just got */ + phys_addr = __pa(cpuaddr); + + /* + * This will try to use a Direct Map register to do the + * 32 bit DMA mapping, but it may not succeed if another + * device on the same bus is already mapped with different + * attributes or to a different memory region. + */ #ifdef CONFIG_IA64_SGI_SN1 - *dma_handle = pciio_dmatrans_addr(vhdl, NULL, temp_ptr, size, - PCIBR_BARRIER | PCIIO_BYTE_STREAM | PCIIO_DMA_CMD - | PCIIO_DMA_A64 ); -#else /* SN2 */ - *dma_handle = pciio_dmatrans_addr(vhdl, NULL, temp_ptr, size, - PCIBR_BARRIER | PCIIO_DMA_CMD | PCIIO_DMA_A64 ); + *dma_handle = pciio_dmatrans_addr(vhdl, NULL, phys_addr, size, + PCIIO_BYTE_STREAM | + PCIIO_DMA_CMD); +#elif defined(CONFIG_IA64_SGI_SN2) + *dma_handle = pciio_dmatrans_addr(vhdl, NULL, phys_addr, size, + ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) | + PCIIO_DMA_CMD); +#else +#error unsupported platform #endif - return (ret); - } - /* - * Devices that supports 32 Bits upto 63 Bits DMA Address gets - * 32 Bits DMA addresses. - * - * First try to get 32 Bit Direct Map Support. + * It is a 32 bit card and we cannot do direct mapping, + * so we try to use an ATE. */ - if (IS_PCI32G(hwdev)) { + if (!(*dma_handle)) { #ifdef CONFIG_IA64_SGI_SN1 - *dma_handle = pciio_dmatrans_addr(vhdl, NULL, temp_ptr, size, - PCIBR_BARRIER | PCIIO_BYTE_STREAM | PCIIO_DMA_CMD); -#else /* SN2 */ - *dma_handle = pciio_dmatrans_addr(vhdl, NULL, temp_ptr, size, - PCIBR_BARRIER | PCIIO_DMA_CMD); + dma_map = pciio_dmamap_alloc(vhdl, NULL, size, + PCIIO_BYTE_STREAM | + PCIIO_DMA_CMD); +#elif defined(CONFIG_IA64_SGI_SN2) + dma_map = pciio_dmamap_alloc(vhdl, NULL, size, + ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) | + PCIIO_DMA_CMD); +#else +#error unsupported platform #endif - - if (dma_handle) { - return (ret); - } else { - /* - * We need to map this request by using ATEs. - */ - printk("sn1_pci_alloc_consistent: 32Bits DMA Page Map support not available yet!"); + if (!dma_map) { + printk(KERN_ERR "sn_pci_alloc_consistent: Unable to " + "allocate anymore 32 bit page map entries.\n"); BUG(); } + *dma_handle = (dma_addr_t) pciio_dmamap_addr(dma_map,phys_addr, + size); + sn_dma_map = (struct sn_dma_maps_s *)dma_map; + sn_dma_map->dma_addr = *dma_handle; } - if (IS_PCI32L(hwdev)) { - /* - * SNIA64 cannot support DMA Addresses smaller than 32 bits. - */ - return (NULL); - } - - return NULL; + return cpuaddr; } +/** + * sn_pci_free_consistent - free memory associated with coherent DMAable region + * @hwdev: device to free for + * @size: size to free + * @vaddr: kernel virtual address to free + * @dma_handle: DMA address associated with this region + * + * Frees the memory allocated by pci_alloc_consistent(). Also known + * as platform_pci_free_consistent() by the IA64 machvec code. + */ void -sn1_pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle) +sn_pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle) { + struct sn_dma_maps_s *sn_dma_map = NULL; + + /* + * Get the sn_dma_map entry. + */ + if (IS_PCI32_MAPPED(dma_handle)) + sn_dma_map = find_sn_dma_map(dma_handle, hwdev->bus->number); + + /* + * and free it if necessary... + */ + if (sn_dma_map) { + pciio_dmamap_done((pciio_dmamap_t)sn_dma_map); + pciio_dmamap_free((pciio_dmamap_t)sn_dma_map); + sn_dma_map->dma_addr = (dma_addr_t)NULL; + } free_pages((unsigned long) vaddr, get_order(size)); } -/* - * On sn1 we use the page entry of the scatterlist to store - * the physical address corresponding to the given virtual address +/** + * sn_pci_map_sg - map a scatter-gather list for DMA + * @hwdev: device to map for + * @sg: scatterlist to map + * @nents: number of entries + * @direction: direction of the DMA transaction + * + * Maps each entry of @sg for DMA. Also known as platform_pci_map_sg by the + * IA64 machvec code. */ int -sn1_pci_map_sg (struct pci_dev *hwdev, - struct scatterlist *sg, int nents, int direction) +sn_pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction) { int i; - devfs_handle_t vhdl; + devfs_handle_t vhdl; dma_addr_t dma_addr; - paddr_t temp_ptr; - struct sn1_device_sysdata *device_sysdata; + unsigned long phys_addr; + struct sn_device_sysdata *device_sysdata; pciio_dmamap_t dma_map; - - + /* can't go anywhere w/o a direction in life */ if (direction == PCI_DMA_NONE) BUG(); /* - * Handle 64 bit cards. + * Get the hwgraph vertex for the device */ - device_sysdata = (struct sn1_device_sysdata *) hwdev->sysdata; + device_sysdata = (struct sn_device_sysdata *) hwdev->sysdata; vhdl = device_sysdata->vhdl; + + /* + * Setup a DMA address for each entry in the + * scatterlist. + */ for (i = 0; i < nents; i++, sg++) { /* this catches incorrectly written drivers that attempt to map scatterlists that they have previously mapped. we print a warning and continue, but the driver should be fixed */ - switch (((u64)sg->address) >> 60) { + switch (((u64)sg->dma_address) >> 60) { case 0xa: case 0xb: #ifdef DEBUG @@ -264,54 +349,53 @@ NAG("A PCI driver (for device at%8s) has attempted to " "map a scatterlist that was previously mapped at " "%p - this is currently being worked around.\n", - hwdev->slot_name, (void *)sg->address); -#endif - temp_ptr = (u64)sg->address & TO_PHYS_MASK; + hwdev->slot_name, (void *)sg->dma_address); + phys_addr = (u64)sg->dma_address & TO_PHYS_MASK; break; - case 0xe: /* a good address, we now map it. */ - temp_ptr = (paddr_t) __pa(sg->address); +#endif + default: /* not previously mapped, get the phys. addr */ + phys_addr = __pa(sg->dma_address); break; - default: - printk(KERN_ERR - "Very bad address (%p) passed to sn1_pci_map_sg\n", - (void *)sg->address); - BUG(); } - sg->page = (char *)NULL; + sg->page = NULL; dma_addr = 0; /* - * Handle the most common case 64Bit cards. + * Handle the most common case: 64 bit cards. This + * call should always succeed. */ if (IS_PCIA64(hwdev)) { -#ifdef CONFIG_IA64_SGI_SN1 - dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL, - temp_ptr, sg->length, - PCIIO_BYTE_STREAM | PCIIO_DMA_DATA | - PCIIO_DMA_A64 ); -#else - dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL, - temp_ptr, sg->length, - PCIIO_DMA_DATA | PCIIO_DMA_A64 ); -#endif - sg->address = (char *)dma_addr; + dma_addr = pciio_dmatrans_addr(vhdl, NULL, phys_addr, + sg->length, + ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) | + PCIIO_DMA_DATA | + PCIIO_DMA_A64); + sg->dma_address = (char *)dma_addr; continue; } /* - * Handle 32Bits and greater cards. + * Handle 32-63 bit cards via direct mapping */ if (IS_PCI32G(hwdev)) { #ifdef CONFIG_IA64_SGI_SN1 - dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL, - temp_ptr, sg->length, - PCIIO_BYTE_STREAM | PCIIO_DMA_DATA); + dma_addr = pciio_dmatrans_addr(vhdl, NULL, phys_addr, + sg->length, + PCIIO_BYTE_STREAM | + PCIIO_DMA_DATA); +#elif defined(CONFIG_IA64_SGI_SN2) + dma_addr = pciio_dmatrans_addr(vhdl, NULL, phys_addr, + sg->length, + ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) | + PCIIO_DMA_DATA); #else - dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL, - temp_ptr, sg->length, PCIIO_DMA_DATA); +#error unsupported platform #endif + /* + * See if we got a direct map entry + */ if (dma_addr) { - sg->address = (char *)dma_addr; + sg->dma_address = (char *)dma_addr; continue; } @@ -322,16 +406,25 @@ * so we use an ATE. */ dma_map = 0; +#ifdef CONFIG_IA64_SGI_SN1 + dma_map = pciio_dmamap_alloc(vhdl, NULL, sg->length, + PCIIO_BYTE_STREAM | + PCIIO_DMA_DATA); +#elif defined(CONFIG_IA64_SGI_SN2) dma_map = pciio_dmamap_alloc(vhdl, NULL, sg->length, - DMA_DATA_FLAGS); + ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) | + PCIIO_DMA_DATA); +#else +#error unsupported platform +#endif if (!dma_map) { printk(KERN_ERR "sn_pci_map_sg: Unable to allocate " "anymore 32 bit page map entries.\n"); BUG(); } dma_addr = pciio_dmamap_addr(dma_map, phys_addr, sg->length); - sg->address = (char *)dma_addr; - sg->page = (char *)dma_map; + sg->dma_address = (char *)dma_addr; + sg->page = (struct page *)dma_map; } @@ -339,34 +432,38 @@ } -/* - * Unmap a set of streaming mode DMA translations. - * Again, cpu read rules concerning calls here are the same as for - * pci_unmap_single() above. +/** + * sn_pci_unmap_sg - unmap a scatter-gather list + * @hwdev: device to unmap + * @sg: scatterlist to unmap + * @nents: number of scatterlist entries + * @direction: DMA direction + * + * Unmap a set of streaming mode DMA translations. Again, cpu read rules + * concerning calls here are the same as for pci_unmap_single() below. Also + * known as sn_pci_unmap_sg() by the IA64 machvec code. */ void -sn1_pci_unmap_sg (struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction) +sn_pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction) { int i; - struct sn1_dma_maps_s *sn1_dma_map; - + struct sn_dma_maps_s *sn_dma_map; + /* can't go anywhere w/o a direction in life */ if (direction == PCI_DMA_NONE) BUG(); - for (i = 0; i < nelems; i++, sg++) + for (i = 0; i < nents; i++, sg++) if (sg->page) { /* * We maintain the DMA Map pointer in sg->page if * it is ever allocated. */ - /* phys_to_virt((dma_addr_t)sg->address | ~0x80000000); */ - /* sg->address = sg->page; */ - sg->address = (char *)-1; - sn1_dma_map = (struct sn1_dma_maps_s *)sg->page; - pciio_dmamap_done((pciio_dmamap_t)sn1_dma_map); - pciio_dmamap_free((pciio_dmamap_t)sn1_dma_map); - sn1_dma_map->dma_addr = 0; + sg->dma_address = 0; + sn_dma_map = (struct sn_dma_maps_s *)sg->page; + pciio_dmamap_done((pciio_dmamap_t)sn_dma_map); + pciio_dmamap_free((pciio_dmamap_t)sn_dma_map); + sn_dma_map->dma_addr = 0; sg->page = 0; } @@ -392,146 +489,212 @@ * get rid of dev_desc and vhdl (seems redundant given a pci_dev); * figure out how to save dmamap handle so can use two step. */ -dma_addr_t sn1_pci_map_single (struct pci_dev *hwdev, - void *ptr, size_t size, int direction) +dma_addr_t +sn_pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction) { - devfs_handle_t vhdl; + devfs_handle_t vhdl; dma_addr_t dma_addr; - paddr_t temp_ptr; - struct sn1_device_sysdata *device_sysdata; + unsigned long phys_addr; + struct sn_device_sysdata *device_sysdata; pciio_dmamap_t dma_map = NULL; - struct sn1_dma_maps_s *sn1_dma_map; - + struct sn_dma_maps_s *sn_dma_map; if (direction == PCI_DMA_NONE) BUG(); + /* SN cannot support DMA addresses smaller than 32 bits. */ + if (IS_PCI32L(hwdev)) + return 0; /* * find vertex for the device */ - device_sysdata = (struct sn1_device_sysdata *)hwdev->sysdata; + device_sysdata = (struct sn_device_sysdata *)hwdev->sysdata; vhdl = device_sysdata->vhdl; /* * Call our dmamap interface */ dma_addr = 0; - temp_ptr = (paddr_t) __pa(ptr); + phys_addr = __pa(ptr); if (IS_PCIA64(hwdev)) { - /* - * This device supports 64bits DMA addresses. - */ -#ifdef CONFIG_IA64_SGI_SN1 - dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL, - temp_ptr, size, - PCIIO_BYTE_STREAM | PCIIO_DMA_DATA | PCIIO_DMA_A64 ); -#else - dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL, - temp_ptr, size, PCIIO_DMA_DATA | PCIIO_DMA_A64 ); -#endif - return (dma_addr); + /* This device supports 64 bit DMA addresses. */ + dma_addr = pciio_dmatrans_addr(vhdl, NULL, phys_addr, size, + ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) | + PCIIO_DMA_DATA | + PCIIO_DMA_A64); + return dma_addr; } /* - * Devices that supports 32 Bits upto 63 Bits DMA Address gets - * 32 Bits DMA addresses. + * Devices that support 32 bit to 63 bit DMA addresses get + * 32 bit DMA addresses. * - * First try to get 32 Bit Direct Map Support. + * First try to get a 32 bit direct map register. */ if (IS_PCI32G(hwdev)) { #ifdef CONFIG_IA64_SGI_SN1 - dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL, - temp_ptr, size, - PCIIO_BYTE_STREAM | PCIIO_DMA_DATA); + dma_addr = pciio_dmatrans_addr(vhdl, NULL, phys_addr, size, + PCIIO_BYTE_STREAM | + PCIIO_DMA_DATA); +#elif defined(CONFIG_IA64_SGI_SN2) + dma_addr = pciio_dmatrans_addr(vhdl, NULL, phys_addr, size, + ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) | + PCIIO_DMA_DATA); #else - dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL, - temp_ptr, size, PCIIO_DMA_DATA); +#error unsupported platform #endif - if (dma_addr) { - return (dma_addr); - } + if (dma_addr) + return dma_addr; } - if (IS_PCI32L(hwdev)) { - /* - * SNIA64 cannot support DMA Addresses smaller than 32 bits. - */ - return ((dma_addr_t) NULL); - } - /* - * It is a 32bit card and we cannot do Direct mapping. - * Let's 32Bit Page map the request. + * It's a 32 bit card and we cannot do direct mapping so + * let's use the PMU instead. */ dma_map = NULL; #ifdef CONFIG_IA64_SGI_SN1 - dma_map = pciio_dmamap_alloc(vhdl, NULL, size, PCIIO_BYTE_STREAM | + dma_map = pciio_dmamap_alloc(vhdl, NULL, size, PCIIO_BYTE_STREAM | PCIIO_DMA_DATA); +#elif defined(CONFIG_IA64_SGI_SN2) + dma_map = pciio_dmamap_alloc(vhdl, NULL, size, + ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) | + PCIIO_DMA_DATA); #else - dma_map = pciio_dmamap_alloc(vhdl, NULL, size, PCIIO_DMA_DATA); +#error unsupported platform #endif + if (!dma_map) { - printk("pci_map_single: Unable to allocate anymore 32Bits Page Map entries.\n"); + printk(KERN_ERR "pci_map_single: Unable to allocate anymore " + "32 bit page map entries.\n"); BUG(); } - dma_addr = (dma_addr_t) pciio_dmamap_addr(dma_map, temp_ptr, size); - /* printk("pci_map_single: dma_map 0x%p Phys Addr 0x%p dma_addr 0x%p\n", dma_map, - temp_ptr, dma_addr); */ - sn1_dma_map = (struct sn1_dma_maps_s *)dma_map; - sn1_dma_map->dma_addr = dma_addr; + dma_addr = (dma_addr_t) pciio_dmamap_addr(dma_map, phys_addr, size); + sn_dma_map = (struct sn_dma_maps_s *)dma_map; + sn_dma_map->dma_addr = dma_addr; return ((dma_addr_t)dma_addr); } +/** + * sn_pci_unmap_single - unmap a region used for DMA + * @hwdev: device to unmap + * @dma_addr: DMA address to unmap + * @size: size of region + * @direction: DMA direction + * + * Unmaps the region pointed to by @dma_addr. Also known as + * platform_pci_unmap_single() by the IA64 machvec code. + */ void -sn1_pci_unmap_single (struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction) +sn_pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction) { - - struct sn1_dma_maps_s *sn1_dma_map = NULL; + struct sn_dma_maps_s *sn_dma_map = NULL; if (direction == PCI_DMA_NONE) BUG(); /* - * Get the sn1_dma_map entry. + * Get the sn_dma_map entry. */ if (IS_PCI32_MAPPED(dma_addr)) - sn1_dma_map = find_sn1_dma_map(dma_addr, hwdev->bus->number); + sn_dma_map = find_sn_dma_map(dma_addr, hwdev->bus->number); - if (sn1_dma_map) { - pciio_dmamap_done((pciio_dmamap_t)sn1_dma_map); - pciio_dmamap_free((pciio_dmamap_t)sn1_dma_map); - sn1_dma_map->dma_addr = (dma_addr_t)NULL; + /* + * and free it if necessary... + */ + if (sn_dma_map) { + pciio_dmamap_done((pciio_dmamap_t)sn_dma_map); + pciio_dmamap_free((pciio_dmamap_t)sn_dma_map); + sn_dma_map->dma_addr = (dma_addr_t)NULL; } - } +/** + * sn_pci_dma_sync_single - make sure all DMAs have completed + * @hwdev: device to sync + * @dma_handle: DMA address to sync + * @size: size of region + * @direction: DMA direction + * + * This routine is supposed to sync the DMA region specified + * by @dma_handle into the 'coherence domain'. See sn_dma_sync() + * above for more information. Also known as + * platform_pci_dma_sync_single() by the IA64 machvec code. + */ void -sn1_pci_dma_sync_single (struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction) +sn_pci_dma_sync_single(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction) { - - if (direction == PCI_DMA_NONE) + if (direction == PCI_DMA_NONE) BUG(); sn_dma_sync(hwdev); - } +/** + * sn_pci_dma_sync_sg - make sure all DMAs have completed + * @hwdev: device to sync + * @sg: scatterlist to sync + * @nents: number of entries in the scatterlist + * @direction: DMA direction + * + * This routine is supposed to sync the DMA regions specified + * by @sg into the 'coherence domain'. See sn_dma_sync() + * above for more information. Also known as + * platform_pci_dma_sync_sg() by the IA64 machvec code. + */ void -sn1_pci_dma_sync_sg (struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction) +sn_pci_dma_sync_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction) { if (direction == PCI_DMA_NONE) BUG(); sn_dma_sync(hwdev); - } +/** + * sn_dma_address - get the DMA address for the first entry of a scatterlist + * @sg: sg to look at + * + * Gets the DMA address for the scatterlist @sg. Also known as + * platform_dma_address() by the IA64 machvec code. + */ unsigned long -sn1_dma_address (struct scatterlist *sg) +sn_dma_address(struct scatterlist *sg) { - return ((unsigned long)sg->address); + return ((unsigned long)sg->dma_address); } + +/** + * sn_dma_supported - test a DMA mask + * @hwdev: device to test + * @mask: DMA mask to test + * + * Return whether the given PCI device DMA address mask can be supported + * properly. For example, if your device can only drive the low 24-bits + * during PCI bus mastering, then you would pass 0x00ffffff as the mask to + * this function. Of course, SN only supports devices that have 32 or more + * address bits when using the PMU. We could theoretically support <32 bit + * cards using direct mapping, but we'll worry about that later--on the off + * chance that someone actually wants to use such a card. + */ +int +sn_pci_dma_supported(struct pci_dev *hwdev, u64 mask) +{ + if (mask < 0xffffffff) + return 0; + return 1; +} + +EXPORT_SYMBOL(sn_pci_unmap_single); +EXPORT_SYMBOL(sn_pci_map_single); +EXPORT_SYMBOL(sn_pci_dma_sync_single); +EXPORT_SYMBOL(sn_pci_map_sg); +EXPORT_SYMBOL(sn_pci_unmap_sg); +EXPORT_SYMBOL(sn_pci_alloc_consistent); +EXPORT_SYMBOL(sn_pci_free_consistent); +EXPORT_SYMBOL(sn_dma_address); +EXPORT_SYMBOL(sn_pci_dma_supported); + diff -Nru a/arch/ia64/sn/io/pciba.c b/arch/ia64/sn/io/pciba.c --- a/arch/ia64/sn/io/pciba.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/io/pciba.c Wed Jan 15 16:57:28 2003 @@ -210,31 +210,31 @@ /* file operations for each type of node */ static struct file_operations rom_fops = { - .owner = THIS_MODULE, - .mmap = rom_mmap, - .open = generic_open, - .release = rom_release + owner: THIS_MODULE, + mmap: rom_mmap, + open: generic_open, + release: rom_release }; static struct file_operations base_fops = { - .owner = THIS_MODULE, - .mmap = base_mmap, - .open = generic_open + owner: THIS_MODULE, + mmap: base_mmap, + open: generic_open }; static struct file_operations config_fops = { - .owner = THIS_MODULE, - .ioctl = config_ioctl, - .open = generic_open + owner: THIS_MODULE, + ioctl: config_ioctl, + open: generic_open }; static struct file_operations dma_fops = { - .owner = THIS_MODULE, - .ioctl = dma_ioctl, - .mmap = dma_mmap, - .open = generic_open + owner: THIS_MODULE, + ioctl: dma_ioctl, + mmap: dma_mmap, + open: generic_open }; @@ -346,9 +346,6 @@ return success; } - -#endif /* CONFIG_IA64_SGI_SN1 */ - static void __exit unregister_with_devfs(void) diff -Nru a/arch/ia64/sn/io/sgi_if.c b/arch/ia64/sn/io/sgi_if.c --- a/arch/ia64/sn/io/sgi_if.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/sgi_if.c Wed Jan 15 16:57:29 2003 @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #include @@ -20,14 +20,50 @@ #include #include +unsigned char Is_pic_on_this_nasid[512]; /* non-0 when this is a pic shub */ + void * snia_kmem_zalloc(size_t size, int flag) { void *ptr = kmalloc(size, GFP_KERNEL); - BZERO(ptr, size); - return ptr; + if ( ptr ) + BZERO(ptr, size); + return(ptr); } +void +snia_kmem_free(void *ptr, size_t size) +{ + kfree(ptr); +} + +int +nic_vertex_info_match(devfs_handle_t v, char *s) +{ + /* we don't support this */ + return(0); +} + +/* + * the alloc/free_node routines do a simple kmalloc for now .. + */ +void * +snia_kmem_alloc_node(register size_t size, register int flags, cnodeid_t node) +{ + /* someday will Allocate on node 'node' */ + return(kmalloc(size, GFP_KERNEL)); +} + +void * +snia_kmem_zalloc_node(register size_t size, register int flags, cnodeid_t node) +{ + void *ptr = kmalloc(size, GFP_KERNEL); + if ( ptr ) + BZERO(ptr, size); + return(ptr); +} + + #define xtod(c) ((c) <= '9' ? '0' - (c) : 'a' - (c) - 10) long atoi(register char *p) @@ -66,4 +102,112 @@ } } return (neg ? n : -n); +} + +char * +strtok_r(char *string, const char *sepset, char **lasts) +{ + register char *q, *r; + + /*first or subsequent call*/ + if (string == NULL) + string = *lasts; + + if(string == 0) /* return if no tokens remaining */ + return(NULL); + + q = string + strspn(string, sepset); /* skip leading separators */ + + if(*q == '\0') { /* return if no tokens remaining */ + *lasts = 0; /* indicate this is last token */ + return(NULL); + } + + if((r = strpbrk(q, sepset)) == NULL) /* move past token */ + *lasts = 0; /* indicate this is last token */ + else { + *r = '\0'; + *lasts = r+1; + } + return(q); +} + +/* + * print_register() allows formatted printing of bit fields. individual + * bit fields are described by a struct reg_desc, multiple bit fields within + * a single word can be described by multiple reg_desc structures. + * %r outputs a string of the format "" + * %R outputs a string of the format "0x%x" + * + * The fields in a reg_desc are: + * unsigned long long rd_mask; An appropriate mask to isolate the bit field + * within a word, and'ed with val + * + * int rd_shift; A shift amount to be done to the isolated + * bit field. done before printing the isolate + * bit field with rd_format and before searching + * for symbolic value names in rd_values + * + * char *rd_name; If non-null, a bit field name to label any + * out from rd_format or searching rd_values. + * if neither rd_format or rd_values is non-null + * rd_name is printed only if the isolated + * bit field is non-null. + * + * char *rd_format; If non-null, the shifted bit field value + * is printed using this format. + * + * struct reg_values *rd_values; If non-null, a pointer to a table + * matching numeric values with symbolic names. + * rd_values are searched and the symbolic + * value is printed if a match is found, if no + * match is found "???" is printed. + * + */ + +void +print_register(unsigned long long reg, struct reg_desc *addr) +{ + register struct reg_desc *rd; + register struct reg_values *rv; + unsigned long long field; + int any; + + printk("<"); + any = 0; + for (rd = addr; rd->rd_mask; rd++) { + field = reg & rd->rd_mask; + field = (rd->rd_shift > 0) ? field << rd->rd_shift : field >> -rd->rd_shift; + if (any && (rd->rd_format || rd->rd_values || (rd->rd_name && field))) + printk(","); + if (rd->rd_name) { + if (rd->rd_format || rd->rd_values || field) { + printk("%s", rd->rd_name); + any = 1; + } + if (rd->rd_format || rd->rd_values) { + printk("="); + any = 1; + } + } + /* You can have any format so long as it is %x */ + if (rd->rd_format) { + printk("%llx", field); + any = 1; + if (rd->rd_values) + printk(":"); + } + if (rd->rd_values) { + any = 1; + for (rv = rd->rd_values; rv->rv_name; rv++) { + if (field == rv->rv_value) { + printk("%s", rv->rv_name); + break; + } + } + if (rv->rv_name == NULL) + printk("???"); + } + } + printk(">\n"); } diff -Nru a/arch/ia64/sn/io/sgi_io_sim.c b/arch/ia64/sn/io/sgi_io_sim.c --- a/arch/ia64/sn/io/sgi_io_sim.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/io/sgi_io_sim.c Wed Jan 15 16:57:28 2003 @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #include @@ -71,6 +71,9 @@ */ static __psunsigned_t master_bridge_base = (__psunsigned_t)NULL; nasid_t console_nasid = (nasid_t)-1; +#if !defined(CONFIG_IA64_SGI_SN1) +char master_baseio_wid; +#endif static char console_wid; static char console_pcislot; @@ -92,6 +95,7 @@ return 0; } +#if defined(CONFIG_IA64_SGI_SN1) int is_master_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid) { @@ -111,6 +115,29 @@ return 0; } } +#else +int +is_master_baseio_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid) +{ + extern nasid_t master_baseio_nasid; + + /* + * If the widget numbers are different, we're not the master. + */ + if (test_wid != (xwidgetnum_t)master_baseio_wid) { + return 0; + } + + /* + * If the NASIDs are the same or equivalent, we're the master. + */ + if (check_nasid_equiv(test_nasid, master_baseio_nasid)) { + return 1; + } else { + return 0; + } +} +#endif /* CONFIG_IA64_SGI_SN1 */ /* * Routines provided by ml/SN/nvram.c diff -Nru a/arch/ia64/sn/io/sn1/hub_intr.c b/arch/ia64/sn/io/sn1/hub_intr.c --- a/arch/ia64/sn/io/sn1/hub_intr.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/sn1/hub_intr.c Wed Jan 15 16:57:29 2003 @@ -1,4 +1,4 @@ -/* $Id: io.c,v 1.2 2001/06/26 14:02:43 pfg Exp $ +/* $Id: hub_intr.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff -Nru a/arch/ia64/sn/io/sn1/hubcounters.c b/arch/ia64/sn/io/sn1/hubcounters.c --- a/arch/ia64/sn/io/sn1/hubcounters.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/io/sn1/hubcounters.c Wed Jan 15 16:57:28 2003 @@ -1,10 +1,10 @@ -/* $Id:$ +/* $Id: hubcounters.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 - 2001 Silicon Graphics, Inc. + * Copyright (C) 1992-1997,2000-2002 Silicon Graphics, Inc. * All rights reserved. */ #include @@ -24,7 +24,7 @@ static int hubstats_ioctl(struct inode *, struct file *, unsigned int, unsigned long); struct file_operations hub_mon_fops = { - .ioctl = hubstats_ioctl, + ioctl: hubstats_ioctl, }; #define HUB_CAPTURE_TICKS (2 * HZ) diff -Nru a/arch/ia64/sn/io/sn1/huberror.c b/arch/ia64/sn/io/sn1/huberror.c --- a/arch/ia64/sn/io/sn1/huberror.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/io/sn1/huberror.c Wed Jan 15 16:57:28 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: huberror.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff -Nru a/arch/ia64/sn/io/sn1/mem_refcnt.c b/arch/ia64/sn/io/sn1/mem_refcnt.c --- a/arch/ia64/sn/io/sn1/mem_refcnt.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/io/sn1/mem_refcnt.c Wed Jan 15 16:57:28 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: mem_refcnt.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -7,7 +7,6 @@ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#include #include #include #include @@ -43,7 +42,7 @@ int mem_refcnt_attach(devfs_handle_t hub) { -#ifndef CONFIG_IA64_SGI_SN +#if 0 devfs_handle_t refcnt_dev; hwgraph_char_device_add(hub, diff -Nru a/arch/ia64/sn/io/sn1/ml_SN_intr.c b/arch/ia64/sn/io/sn1/ml_SN_intr.c --- a/arch/ia64/sn/io/sn1/ml_SN_intr.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/sn1/ml_SN_intr.c Wed Jan 15 16:57:29 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: ml_SN_intr.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -13,7 +13,7 @@ * handle interrupts on an IP27 board. */ -#ident "$Revision: 1.167 $" +#ident "$Revision: 1.1 $" #include #include @@ -987,13 +987,12 @@ char subnode_done[NUM_SUBNODES]; // cpu = cnodetocpu(cnode); - for (cpu = 0; cpu < NR_CPUS; cpu++) { - if (!cpu_online(cpu)) continue; + for (cpu = 0; cpu < smp_num_cpus; cpu++) { if (cpuid_to_cnodeid(cpu) == cnode) { break; } } - if (cpu == NR_CPUS) cpu = CPU_NONE; + if (cpu == smp_num_cpus) cpu = CPU_NONE; if (cpu == CPU_NONE) { printk("Node %d has no CPUs", cnode); return; @@ -1002,7 +1001,7 @@ for (i=0; i -#include #include #include #include @@ -307,22 +306,22 @@ * appropriate function name below. */ struct file_operations pcibr_fops = { - .owner = THIS_MODULE, - .llseek = NULL, - .read = NULL, - .write = NULL, - .readdir = NULL, - .poll = NULL, - .ioctl = NULL, - .mmap = NULL, - .open = NULL, - .flush = NULL, - .release = NULL, - .fsync = NULL, - .fasync = NULL, - .lock = NULL, - .readv = NULL, - .writev = NULL + owner: THIS_MODULE, + llseek: NULL, + read: NULL, + write: NULL, + readdir: NULL, + poll: NULL, + ioctl: NULL, + mmap: NULL, + open: NULL, + flush: NULL, + release: NULL, + fsync: NULL, + fasync: NULL, + lock: NULL, + readv: NULL, + writev: NULL }; extern devfs_handle_t hwgraph_root; @@ -332,7 +331,6 @@ extern void rmfree(struct map *mp, size_t size, uint64_t a); extern int hwgraph_vertex_name_get(devfs_handle_t vhdl, char *buf, uint buflen); extern long atoi(register char *p); -extern void *swap_ptr(void **loc, void *new); extern char *dev_to_name(devfs_handle_t dev, char *buf, uint buflen); extern cnodeid_t nodevertex_to_cnodeid(devfs_handle_t vhdl); extern graph_error_t hwgraph_edge_remove(devfs_handle_t from, char *name, devfs_handle_t *toptr); @@ -1628,243 +1626,6 @@ "BAD"}; -#ifdef LATER - -void -pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh, - int func, - pcibr_slot_func_info_resp_t funcp) -{ - pcibr_info_t pcibr_info = pcibr_infoh[func]; - int win; - - funcp->resp_f_status = 0; - - if (!pcibr_info) { - return; - } - - funcp->resp_f_status |= FUNC_IS_VALID; -#ifdef SUPPORT_PRINTING_V_FORMAT - sprintf(funcp->resp_f_slot_name, "%v", pcibr_info->f_vertex); -#else - sprintf(funcp->resp_f_slot_name, "%x", pcibr_info->f_vertex); -#endif - - if(is_sys_critical_vertex(pcibr_info->f_vertex)) { - funcp->resp_f_status |= FUNC_IS_SYS_CRITICAL; - } - - funcp->resp_f_bus = pcibr_info->f_bus; - funcp->resp_f_slot = pcibr_info->f_slot; - funcp->resp_f_func = pcibr_info->f_func; -#ifdef SUPPORT_PRINTING_V_FORMAT - sprintf(funcp->resp_f_master_name, "%v", pcibr_info->f_master); -#else - sprintf(funcp->resp_f_master_name, "%x", pcibr_info->f_master); -#endif - funcp->resp_f_pops = pcibr_info->f_pops; - funcp->resp_f_efunc = pcibr_info->f_efunc; - funcp->resp_f_einfo = pcibr_info->f_einfo; - - funcp->resp_f_vendor = pcibr_info->f_vendor; - funcp->resp_f_device = pcibr_info->f_device; - - for(win = 0 ; win < 6 ; win++) { - funcp->resp_f_window[win].resp_w_base = - pcibr_info->f_window[win].w_base; - funcp->resp_f_window[win].resp_w_size = - pcibr_info->f_window[win].w_size; - sprintf(funcp->resp_f_window[win].resp_w_space, - "%s", - pci_space_name[pcibr_info->f_window[win].w_space]); - } - - funcp->resp_f_rbase = pcibr_info->f_rbase; - funcp->resp_f_rsize = pcibr_info->f_rsize; - - for (win = 0 ; win < 4; win++) { - funcp->resp_f_ibit[win] = pcibr_info->f_ibit[win]; - } - - funcp->resp_f_att_det_error = pcibr_info->f_att_det_error; - -} - -int -pcibr_slot_info_return(pcibr_soft_t pcibr_soft, - pciio_slot_t slot, - pcibr_slot_info_resp_t respp) -{ - pcibr_soft_slot_t pss; - int func; - bridge_t *bridge = pcibr_soft->bs_base; - reg_p b_respp; - pcibr_slot_info_resp_t slotp; - pcibr_slot_func_info_resp_t funcp; - - slotp = snia_kmem_zalloc(sizeof(*slotp), KM_SLEEP); - if (slotp == NULL) { - return(ENOMEM); - } - - pss = &pcibr_soft->bs_slot[slot]; - - printk("\nPCI INFRASTRUCTURAL INFO FOR SLOT %d\n\n", slot); - - slotp->resp_has_host = pss->has_host; - slotp->resp_host_slot = pss->host_slot; -#ifdef SUPPORT_PRINTING_V_FORMAT - sprintf(slotp->resp_slot_conn_name, "%v", pss->slot_conn); -#else - sprintf(slotp->resp_slot_conn_name, "%x", pss->slot_conn); -#endif - slotp->resp_slot_status = pss->slot_status; - slotp->resp_l1_bus_num = io_path_map_widget(pcibr_soft->bs_vhdl); - - if (is_sys_critical_vertex(pss->slot_conn)) { - slotp->resp_slot_status |= SLOT_IS_SYS_CRITICAL; - } - - slotp->resp_bss_ninfo = pss->bss_ninfo; - - for (func = 0; func < pss->bss_ninfo; func++) { - funcp = &(slotp->resp_func[func]); - pcibr_slot_func_info_return(pss->bss_infos, func, funcp); - } - - sprintf(slotp->resp_bss_devio_bssd_space, "%s", - pci_space_name[pss->bss_devio.bssd_space]); - slotp->resp_bss_devio_bssd_base = pss->bss_devio.bssd_base; - slotp->resp_bss_device = pss->bss_device; - - slotp->resp_bss_pmu_uctr = pss->bss_pmu_uctr; - slotp->resp_bss_d32_uctr = pss->bss_d32_uctr; - slotp->resp_bss_d64_uctr = pss->bss_d64_uctr; - - slotp->resp_bss_d64_base = pss->bss_d64_base; - slotp->resp_bss_d64_flags = pss->bss_d64_flags; - slotp->resp_bss_d32_base = pss->bss_d32_base; - slotp->resp_bss_d32_flags = pss->bss_d32_flags; - - slotp->resp_bss_ext_ates_active = atomic_read(&pss->bss_ext_ates_active); - - slotp->resp_bss_cmd_pointer = pss->bss_cmd_pointer; - slotp->resp_bss_cmd_shadow = pss->bss_cmd_shadow; - - slotp->resp_bs_rrb_valid = pcibr_soft->bs_rrb_valid[slot]; - slotp->resp_bs_rrb_valid_v = pcibr_soft->bs_rrb_valid[slot + - PCIBR_RRB_SLOT_VIRTUAL]; - slotp->resp_bs_rrb_res = pcibr_soft->bs_rrb_res[slot]; - - if (slot & 1) { - b_respp = &bridge->b_odd_resp; - } else { - b_respp = &bridge->b_even_resp; - } - - slotp->resp_b_resp = *b_respp; - - slotp->resp_b_int_device = bridge->b_int_device; - slotp->resp_b_int_enable = bridge->b_int_enable; - slotp->resp_b_int_host = bridge->b_int_addr[slot].addr; - - if (COPYOUT(slotp, respp, sizeof(*respp))) { - return(EFAULT); - } - - snia_kmem_free(slotp, sizeof(*slotp)); - - return(0); -} - -/* - * pcibr_slot_query - * Return information about the PCI slot maintained by the infrastructure. - * Information is requested in the request structure. - * - * Information returned in the response structure: - * Slot hwgraph name - * Vendor/Device info - * Base register info - * Interrupt mapping from device pins to the bridge pins - * Devio register - * Software RRB info - * RRB register info - * Host/Gues info - * PCI Bus #,slot #, function # - * Slot provider hwgraph name - * Provider Functions - * Error handler - * DMA mapping usage counters - * DMA direct translation info - * External SSRAM workaround info - */ -int -pcibr_slot_query(devfs_handle_t pcibr_vhdl, pcibr_slot_info_req_t reqp) -{ - pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl); - pciio_slot_t slot = reqp->req_slot; - pciio_slot_t tmp_slot; - pcibr_slot_info_resp_t respp = (pcibr_slot_info_resp_t) reqp->req_respp; - int size = reqp->req_size; - int error; - - /* Make sure that we are dealing with a bridge device vertex */ - if (!pcibr_soft) { - return(EINVAL); - } - - /* Make sure that we have a valid PCI slot number or PCIIO_SLOT_NONE */ - if ((!PCIBR_VALID_SLOT(slot)) && (slot != PCIIO_SLOT_NONE)) { - return(EINVAL); - } - - /* Return information for the requested PCI slot */ - if (slot != PCIIO_SLOT_NONE) { - if (size < sizeof(*respp)) { - return(EINVAL); - } - - /* Acquire read access to the slot */ - mrlock(pcibr_soft->bs_slot[slot].slot_lock, MR_ACCESS, PZERO); - - error = pcibr_slot_info_return(pcibr_soft, slot, respp); - - /* Release the slot lock */ - mrunlock(pcibr_soft->bs_slot[slot].slot_lock); - - return(error); - } - - /* Return information for all the slots */ - for (tmp_slot = 0; tmp_slot < 8; tmp_slot++) { - - if (size < sizeof(*respp)) { - return(EINVAL); - } - - /* Acquire read access to the slot */ - mrlock(pcibr_soft->bs_slot[tmp_slot].slot_lock, MR_ACCESS, PZERO); - - error = pcibr_slot_info_return(pcibr_soft, tmp_slot, respp); - - /* Release the slot lock */ - mrunlock(pcibr_soft->bs_slot[tmp_slot].slot_lock); - - if (error) { - return(error); - } - - ++respp; - size -= sizeof(*respp); - } - - return(error); -} -#endif /* LATER */ - - /*ARGSUSED */ int pcibr_ioctl(devfs_handle_t dev, @@ -3617,7 +3378,7 @@ self->bl_soft = pcibr_soft; self->bl_vhdl = pcibr_vhdl; self->bl_next = pcibr_list; - self->bl_next = swap_ptr((void **) &pcibr_list, (void *)self); + pcibr_list = self; } #endif @@ -6455,9 +6216,7 @@ intr_bit = (short) xtalk_intr_vector_get(xtalk_intr); cpu = cpuvertex_to_cpuid(xtalk_intr_cpu_get(xtalk_intr)); -#if defined(CONFIG_IA64_SGI_SN1) REMOTE_CPU_SEND_INTR(cpu, intr_bit); -#endif } } @@ -6822,13 +6581,8 @@ bridgereg_t *int_addr = (bridgereg_t *) xtalk_intr_sfarg_get(xtalk_intr); -#ifdef CONFIG_IA64_SGI_SN2 - *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 26)) | - (BRIDGE_INT_ADDR_FLD & vect)); -#elif CONFIG_IA64_SGI_SN1 *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) | (BRIDGE_INT_ADDR_FLD & vect)); -#endif } /*ARGSUSED */ @@ -7485,7 +7239,7 @@ #ifdef LITTLE_ENDIAN /* - * on sn-ia we need to twiddle the addresses going out + * on sn-ia we need to twiddle the the addresses going out * the pci bus because we use the unswizzled synergy space * (the alternative is to use the swizzled synergy space * and byte swap the data) diff -Nru a/arch/ia64/sn/io/sn2/bte_error.c b/arch/ia64/sn/io/sn2/bte_error.c --- a/arch/ia64/sn/io/sn2/bte_error.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/sn2/bte_error.c Wed Jan 15 16:57:29 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: bte_error.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -54,96 +54,14 @@ * * ************************************************************************/ -#ifdef BTE_ERROR -// This routine is not called. Yet. It may be someday. It probably -// *should* be someday. Until then, ifdef it out. -bte_result_t -bte_error_handler(bte_handle_t *bh) -/* - * Function: bte_error_handler - * Purpose: Process a BTE error after a transfer has failed. - * Parameters: bh - bte handle of bte that failed. - * Returns: The BTE error type. - * Notes: +/* + * >>> bte_crb_error_handler needs to be broken into two parts. The + * first should cleanup the CRB. The second should wait until all bte + * related CRB's are complete and then do the error reset. */ -{ - devfs_handle_t hub_v; - hubinfo_t hinfo; - int il; - hubreg_t iidsr, imem, ieclr; - hubreg_t bte_status; - - bh->bh_bte->bte_error_count++; - - /* - * Process any CRB logs - we know that the bte_context contains - * the BTE completion status, but to avoid a race with error - * processing, we force a call to pick up any CRB errors pending. - * After this call, we know that we have any CRB errors related to - * this BTE transfer in the context. - */ - hub_v = cnodeid_to_vertex(bh->bh_bte->bte_cnode); - hubinfo_get(hub_v, &hinfo); - (void)hubiio_crb_error_handler(hub_v, hinfo); - - /* Be sure BTE is stopped */ - - (void)BTE_LOAD(bh->bh_bte->bte_base, BTEOFF_CTRL); - - /* - * Now clear up the rest of the error - be sure to hold crblock - * to avoid race with other cpu on this node. - */ - imem = REMOTE_HUB_L(hinfo->h_nasid, IIO_IMEM); - ieclr = REMOTE_HUB_L(hinfo->h_nasid, IIO_IECLR); - if (bh->bh_bte->bte_num == 0) { - imem |= IIO_IMEM_W0ESD | IIO_IMEM_B0ESD; - ieclr|= IECLR_BTE0; - } else { - imem |= IIO_IMEM_W0ESD | IIO_IMEM_B1ESD; - ieclr|= IECLR_BTE1; - } - - REMOTE_HUB_S(hinfo->h_nasid, IIO_IMEM, imem); - REMOTE_HUB_S(hinfo->h_nasid, IIO_IECLR, ieclr); - - iidsr = REMOTE_HUB_L(hinfo->h_nasid, IIO_IIDSR); - iidsr &= ~IIO_IIDSR_SENT_MASK; - iidsr |= IIO_IIDSR_ENB_MASK; - REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, iidsr); - mutex_spinunlock(&hinfo->h_crblock, il); - - bte_status = BTE_LOAD(bh->bh_bte->bte_base, BTEOFF_STAT); - BTE_STORE(bh->bh_bte->bte_base, BTEOFF_STAT, bte_status & ~IBLS_BUSY); - ASSERT(!BTE_IS_BUSY(BTE_LOAD(bh->bh_bte->bte_base, BTEOFF_STAT))); - - switch(bh->bh_error) { - case IIO_ICRB_ECODE_PERR: - return(BTEFAIL_POISON); - case IIO_ICRB_ECODE_WERR: - return(BTEFAIL_PROT); - case IIO_ICRB_ECODE_AERR: - return(BTEFAIL_ACCESS); - case IIO_ICRB_ECODE_TOUT: - return(BTEFAIL_TOUT); - case IIO_ICRB_ECODE_XTERR: - return(BTEFAIL_ERROR); - case IIO_ICRB_ECODE_DERR: - return(BTEFAIL_DIR); - case IIO_ICRB_ECODE_PWERR: - case IIO_ICRB_ECODE_PRERR: - /* NO BREAK */ - default: - printk("BTE failure (%d) unexpected\n", - bh->bh_error); - return(BTEFAIL_ERROR); - } -} -#endif // BTE_ERROR - void bte_crb_error_handler(devfs_handle_t hub_v, int btenum, - int crbnum, ioerror_t *ioe) + int crbnum, ioerror_t *ioe, int bteop) /* * Function: bte_crb_error_handler * Purpose: Process a CRB for a specific HUB/BTE @@ -162,29 +80,70 @@ icrba_t crba; icrbb_t crbb; nasid_t n; + hubreg_t iidsr, imem, ieclr; hubinfo_get(hub_v, &hinfo); n = hinfo->h_nasid; - /* Step 1 */ - crba.ii_icrb0_a_regval = REMOTE_HUB_L(n, IIO_ICRB_A(crbnum)); - crbb.ii_icrb0_b_regval = REMOTE_HUB_L(n, IIO_ICRB_B(crbnum)); + /* + * The following 10 lines (or so) are adapted from IRIXs + * bte_crb_error function. No clear documentation tells + * why the crb needs to complete normally in order for + * the BTE to resume normal operations. This first step + * appears vital! + */ - /* Zero error and error code to prevent error_dump complaining - * about these CRBs. + /* + * Zero error and error code to prevent error_dump complaining + * about these CRBs. Copy the CRB to the notification line. + * The crb address is in shub format (physical address shifted + * right by cacheline size). */ + crbb.ii_icrb0_b_regval = REMOTE_HUB_L(n, IIO_ICRB_B(crbnum)); crbb.b_error=0; crbb.b_ecode=0; + REMOTE_HUB_S(n, IIO_ICRB_B(crbnum), crbb.ii_icrb0_b_regval); - /* Step 2 */ + crba.ii_icrb0_a_regval = REMOTE_HUB_L(n, IIO_ICRB_A(crbnum)); + crba.a_addr = TO_PHYS((u64)&nodepda->bte_if[btenum].notify) >> 3; + crba.a_valid = 1; REMOTE_HUB_S(n, IIO_ICRB_A(crbnum), crba.ii_icrb0_a_regval); - /* Step 3 */ + REMOTE_HUB_S(n, IIO_ICCR, IIO_ICCR_PENDING | IIO_ICCR_CMD_FLUSH | crbnum); + while (REMOTE_HUB_L(n, IIO_ICCR) & IIO_ICCR_PENDING) ; + + + /* Terminate the BTE. */ + /* >>> The other bte transfer will need to be restarted. */ + HUB_L((shubreg_t *)((nodepda->bte_if[btenum].bte_base_addr + + IIO_IBCT0 - IIO_IBLS0))); + + imem = REMOTE_HUB_L(n, IIO_IMEM); + ieclr = REMOTE_HUB_L(n, IIO_IECLR); + if (btenum == 0) { + imem |= IIO_IMEM_W0ESD | IIO_IMEM_B0ESD; + ieclr|= IECLR_BTE0; + } else { + imem |= IIO_IMEM_W0ESD | IIO_IMEM_B1ESD; + ieclr|= IECLR_BTE1; + } + REMOTE_HUB_S(n, IIO_IMEM, imem); + REMOTE_HUB_S(n, IIO_IECLR, ieclr); + + iidsr = REMOTE_HUB_L(n, IIO_IIDSR); + iidsr &= ~IIO_IIDSR_SENT_MASK; + iidsr |= IIO_IIDSR_ENB_MASK; + REMOTE_HUB_S(n, IIO_IIDSR, iidsr); + + + bte_reset_nasid(n); + + *nodepda->bte_if[btenum].most_rcnt_na = IBLS_ERROR; } diff -Nru a/arch/ia64/sn/io/sn2/ml_SN_intr.c b/arch/ia64/sn/io/sn2/ml_SN_intr.c --- a/arch/ia64/sn/io/sn2/ml_SN_intr.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/sn2/ml_SN_intr.c Wed Jan 15 16:57:29 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: ml_SN_intr.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -13,7 +13,7 @@ * handle interrupts on an IPXX board. */ -#ident "$Revision: 1.167 $" +#ident "$Revision: 1.1 $" #include #include @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -51,24 +52,15 @@ int sn) { int nasid = cnodeid_to_nasid(node); - nasid_t console_nasid; sh_ii_int0_config_u_t ii_int_config; cpuid_t cpu; cpuid_t cpu0, cpu1; nodepda_t *lnodepda; sh_ii_int0_enable_u_t ii_int_enable; - sh_local_int0_config_u_t local_int_config; - sh_local_int0_enable_u_t local_int_enable; - sh_fsb_system_agent_config_u_t fsb_system_agent; sh_int_node_id_config_u_t node_id_config; - int is_console; + extern void sn_init_cpei_timer(void); + static int timer_added = 0; - console_nasid = get_console_nasid(); - if (console_nasid < 0) { - console_nasid = master_nasid; - } - - is_console = nasid == console_nasid; if (is_headless_node(node) ) { int cnode; @@ -95,13 +87,15 @@ } // Get the physical id's of the cpu's on this node. - cpu0 = id_eid_to_cpu_physical_id(nasid, 0); - cpu1 = id_eid_to_cpu_physical_id(nasid, 1); + cpu0 = nasid_slice_to_cpu_physical_id(nasid, 0); + cpu1 = nasid_slice_to_cpu_physical_id(nasid, 2); HUB_S( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_PI_ERROR_MASK), 0); HUB_S( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_PI_CRBP_ERROR_MASK), 0); + // The II_INT_CONFIG register for cpu 0. + ii_int_config.sh_ii_int0_config_regval = 0; ii_int_config.sh_ii_int0_config_s.type = 0; ii_int_config.sh_ii_int0_config_s.agt = 0; ii_int_config.sh_ii_int0_config_s.pid = cpu0; @@ -110,7 +104,9 @@ HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT0_CONFIG), ii_int_config.sh_ii_int0_config_regval); + // The II_INT_CONFIG register for cpu 1. + ii_int_config.sh_ii_int0_config_regval = 0; ii_int_config.sh_ii_int0_config_s.type = 0; ii_int_config.sh_ii_int0_config_s.agt = 0; ii_int_config.sh_ii_int0_config_s.pid = cpu1; @@ -119,101 +115,28 @@ HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT1_CONFIG), ii_int_config.sh_ii_int0_config_regval); + // Enable interrupts for II_INT0 and 1. + ii_int_enable.sh_ii_int0_enable_regval = 0; ii_int_enable.sh_ii_int0_enable_s.ii_enable = 1; +#ifdef BUS_INT_WAR + /* Dont enable any ints from II. We will poll for interrupts. */ + ii_int_enable.sh_ii_int0_enable_s.ii_enable = 0; + + /* Enable IPIs. We use them ONLY for send INITs to hung cpus */ + *(volatile long*)GLOBAL_MMR_ADDR(nasid, SH_IPI_INT_ENABLE) = 1; +#endif HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT0_ENABLE), ii_int_enable.sh_ii_int0_enable_regval); HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT1_ENABLE), ii_int_enable.sh_ii_int0_enable_regval); - // init error regs - // LOCAL_INT0 is for the UART only. - - local_int_config.sh_local_int0_config_s.type = 0; - local_int_config.sh_local_int0_config_s.agt = 0; - local_int_config.sh_local_int0_config_s.pid = cpu; - local_int_config.sh_local_int0_config_s.base = 0; - local_int_config.sh_local_int0_config_s.idx = SGI_UART_VECTOR; - - HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT0_CONFIG), - local_int_config.sh_local_int0_config_regval); - - // LOCAL_INT1 is for all hardware errors. - // It will send a BERR, which will result in an MCA. - local_int_config.sh_local_int0_config_s.idx = 0; - - HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT1_CONFIG), - local_int_config.sh_local_int0_config_regval); - - // Clear the LOCAL_INT_ENABLE register. - local_int_enable.sh_local_int0_enable_regval = 0; - - if (is_console) { - // Enable the UART interrupt. Only applies to the console nasid. - local_int_enable.sh_local_int0_enable_s.uart_int = 1; - - HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT0_ENABLE), - local_int_enable.sh_local_int0_enable_regval); - } - - // Enable all the error interrupts. - local_int_enable.sh_local_int0_enable_s.uart_int = 0; - local_int_enable.sh_local_int0_enable_s.pi_hw_int = 1; - local_int_enable.sh_local_int0_enable_s.md_hw_int = 1; - local_int_enable.sh_local_int0_enable_s.xn_hw_int = 1; - local_int_enable.sh_local_int0_enable_s.lb_hw_int = 1; - local_int_enable.sh_local_int0_enable_s.ii_hw_int = 1; - local_int_enable.sh_local_int0_enable_s.pi_uce_int = 1; - local_int_enable.sh_local_int0_enable_s.md_uce_int = 1; - local_int_enable.sh_local_int0_enable_s.xn_uce_int = 1; - local_int_enable.sh_local_int0_enable_s.system_shutdown_int = 1; - local_int_enable.sh_local_int0_enable_s.l1_nmi_int = 1; - local_int_enable.sh_local_int0_enable_s.stop_clock = 1; - - - // Send BERR, rather than an interrupt, for shub errors. - local_int_config.sh_local_int0_config_s.agt = 1; - HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT1_CONFIG), - local_int_config.sh_local_int0_config_regval); - - HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT1_ENABLE), - local_int_enable.sh_local_int0_enable_regval); - - // Make sure BERR is enabled. - fsb_system_agent.sh_fsb_system_agent_config_regval = - HUB_L( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_FSB_SYSTEM_AGENT_CONFIG) ); - fsb_system_agent.sh_fsb_system_agent_config_s.berr_assert_en = 1; - HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_FSB_SYSTEM_AGENT_CONFIG), - fsb_system_agent.sh_fsb_system_agent_config_regval); - - // Set LOCAL_INT2 to field CEs - - local_int_enable.sh_local_int0_enable_regval = 0; - - local_int_config.sh_local_int0_config_s.agt = 0; - local_int_config.sh_local_int0_config_s.idx = SGI_SHUB_ERROR_VECTOR; - HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT2_CONFIG), - local_int_config.sh_local_int0_config_regval); - - local_int_enable.sh_local_int0_enable_s.pi_ce_int = 1; - local_int_enable.sh_local_int0_enable_s.md_ce_int = 1; - local_int_enable.sh_local_int0_enable_s.xn_ce_int = 1; - - HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT2_ENABLE), - local_int_enable.sh_local_int0_enable_regval); - - // Make sure all the rest of the LOCAL_INT regs are disabled. - local_int_enable.sh_local_int0_enable_regval = 0; - HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT3_ENABLE), - local_int_enable.sh_local_int0_enable_regval); - - HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT4_ENABLE), - local_int_enable.sh_local_int0_enable_regval); - - HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT5_ENABLE), - local_int_enable.sh_local_int0_enable_regval); + if (!timer_added) { // can only init the timer once. + timer_added = 1; + sn_init_cpei_timer(); + } } // (Un)Reserve an irq on this cpu. @@ -393,31 +316,40 @@ int *resp_bit) { cpuid_t cpuid; - cnodeid_t candidate = -1; + cpuid_t candidate = CPU_NONE; + cnodeid_t candidate_node; devfs_handle_t pconn_vhdl; pcibr_soft_t pcibr_soft; + int bit; /* SN2 + pcibr addressing limitation */ /* Due to this limitation, all interrupts from a given bridge must go to the name node.*/ +/* The interrupt must also be targetted for the same processor. */ /* This limitation does not exist on PIC. */ +/* But, the processor limitation will stay. The limitation will be similar to */ +/* the bedrock/xbridge limit regarding PI's */ if ( (hwgraph_edge_get(dev, EDGE_LBL_PCI, &pconn_vhdl) == GRAPH_SUCCESS) && ( (pcibr_soft = pcibr_soft_get(pconn_vhdl) ) != NULL) ) { if (pcibr_soft->bsi_err_intr) { - candidate = cpuid_to_cnodeid( ((hub_intr_t)pcibr_soft->bsi_err_intr)->i_cpuid); + candidate = ((hub_intr_t)pcibr_soft->bsi_err_intr)->i_cpuid; } } - if (candidate >= 0) { - // The node was chosen already when we assigned the error interrupt. - cpuid = intr_bit_reserve_test(CPU_NONE, - 0, - candidate, - req_bit, - 0, - owner_dev, - name, - resp_bit); + + if (candidate != CPU_NONE) { + // The cpu was chosen already when we assigned the error interrupt. + bit = intr_reserve_level(candidate, + req_bit, + resflags, + owner_dev, + name); + if (bit < 0) { + cpuid = CPU_NONE; + } else { + cpuid = candidate; + *resp_bit = bit; + } } else { // Need to choose one. Try the controlling c-brick first. cpuid = intr_bit_reserve_test(CPU_NONE, @@ -434,10 +366,9 @@ return cpuid; } - if (candidate >= 0) { - printk("Cannot target interrupt to target node (%d).\n",candidate); - return CPU_NONE; - } else { + if (candidate != CPU_NONE) { + printk("Cannot target interrupt to target node (%ld).\n",candidate); + return CPU_NONE; } else { printk("Cannot target interrupt to closest node (%d) 0x%p\n", master_node_get(dev), (void *)owner_dev); } @@ -448,11 +379,11 @@ { static cnodeid_t last_node = -1; if (last_node >= numnodes) last_node = 0; - for (candidate = last_node + 1; candidate != last_node; candidate++) { - if (candidate == numnodes) candidate = 0; + for (candidate_node = last_node + 1; candidate_node != last_node; candidate_node++) { + if (candidate_node == numnodes) candidate_node = 0; cpuid = intr_bit_reserve_test(CPU_NONE, 0, - candidate, + candidate_node, req_bit, 0, owner_dev, diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c Wed Jan 15 16:57:28 2003 @@ -44,24 +44,6 @@ #endif -#ifdef LATER -#if (PCIBR_FREEZE_TIME) || PCIBR_ATE_DEBUG -LOCAL struct reg_desc ate_bits[] = -{ - {0xFFFF000000000000ull, -48, "RMF", "%x"}, - {~(IOPGSIZE - 1) & /* may trim off some low bits */ - 0x0000FFFFFFFFF000ull, 0, "XIO", "%x"}, - {0x0000000000000F00ull, -8, "port", "%x"}, - {0x0000000000000010ull, 0, "Barrier"}, - {0x0000000000000008ull, 0, "Prefetch"}, - {0x0000000000000004ull, 0, "Precise"}, - {0x0000000000000002ull, 0, "Coherent"}, - {0x0000000000000001ull, 0, "Valid"}, - {0} -}; -#endif -#endif /* LATER */ - #ifndef LOCAL #define LOCAL static #endif @@ -79,7 +61,7 @@ unsigned *freeze_time_ptr, #endif unsigned *cmd_regs); -void ate_write(bridge_ate_p ate_ptr, int ate_count, bridge_ate_t ate); +void ate_write(pcibr_soft_t pcibr_soft, bridge_ate_p ate_ptr, int ate_count, bridge_ate_t ate); void ate_thaw(pcibr_dmamap_t pcibr_dmamap, int ate_index, #if PCIBR_FREEZE_TIME @@ -119,26 +101,73 @@ int i, j; bridgereg_t old_enable, new_enable; int s; + int this_is_pic = is_pic(bridge); /* Probe SSRAM to determine its size. */ - old_enable = bridge->b_int_enable; - new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT; - bridge->b_int_enable = new_enable; + if ( this_is_pic ) { + old_enable = bridge->b_int_enable; + new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT; + bridge->b_int_enable = new_enable; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + old_enable = BRIDGE_REG_GET32((&bridge->b_int_enable)); + new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT; + BRIDGE_REG_SET32((&bridge->b_int_enable)) = new_enable; + } + else { + old_enable = bridge->b_int_enable; + new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT; + bridge->b_int_enable = new_enable; + } + } for (i = 1; i < ATE_NUM_SIZES; i++) { /* Try writing a value */ - bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE; + if ( this_is_pic ) { + bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) + bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = __swab64(ATE_PROBE_VALUE); + else + bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE; + } /* Guard against wrap */ for (j = 1; j < i; j++) bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(j) - 1] = 0; /* See if value was written */ - if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE) - largest_working_size = i; + if ( this_is_pic ) { + if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE) + largest_working_size = i; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == __swab64(ATE_PROBE_VALUE)) + largest_working_size = i; + else { + if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE) + largest_working_size = i; + } + } + } + } + if ( this_is_pic ) { + bridge->b_int_enable = old_enable; + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_SET32((&bridge->b_int_enable)) = old_enable; + BRIDGE_REG_GET32((&bridge->b_wid_tflush)); /* wait until Bridge PIO complete */ + } + else { + bridge->b_int_enable = old_enable; + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } } - bridge->b_int_enable = old_enable; - bridge->b_wid_tflush; /* wait until Bridge PIO complete */ /* * ensure that we write and read without any interruption. @@ -146,20 +175,41 @@ */ s = splhi(); - bridge->b_wid_control = (bridge->b_wid_control - & ~BRIDGE_CTRL_SSRAM_SIZE_MASK) - | BRIDGE_CTRL_SSRAM_SIZE(largest_working_size); - bridge->b_wid_control; /* inval addr bug war */ + if ( this_is_pic ) { + bridge->b_wid_control = (bridge->b_wid_control + & ~BRIDGE_CTRL_SSRAM_SIZE_MASK) + | BRIDGE_CTRL_SSRAM_SIZE(largest_working_size); + bridge->b_wid_control; /* inval addr bug war */ + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_SET32((&(bridge->b_wid_control))) = + __swab32((BRIDGE_REG_GET32((&bridge->b_wid_control)) + & ~BRIDGE_CTRL_SSRAM_SIZE_MASK) + | BRIDGE_CTRL_SSRAM_SIZE(largest_working_size)); + BRIDGE_REG_GET32((&bridge->b_wid_control));/* inval addr bug war */ + } + else { + bridge->b_wid_control = (bridge->b_wid_control & ~BRIDGE_CTRL_SSRAM_SIZE_MASK) + | BRIDGE_CTRL_SSRAM_SIZE(largest_working_size); + bridge->b_wid_control; /* inval addr bug war */ + } + } splx(s); num_entries = ATE_NUM_ENTRIES(largest_working_size); -#if PCIBR_ATE_DEBUG - if (num_entries) - printk("bridge at 0x%x: clearing %d external ATEs\n", bridge, num_entries); - else - printk("bridge at 0x%x: no external ATE RAM found\n", bridge); -#endif + if (pcibr_debug_mask & PCIBR_DEBUG_ATE) { + if (num_entries) { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATE, NULL, + "bridge at 0x%x: clearing %d external ATEs\n", + bridge, num_entries)); + } else { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATE, NULL, + "bridge at 0x%x: no external ATE RAM found\n", + bridge)); + } + } /* Initialize external mapping entries */ for (entry = 0; entry < num_entries; entry++) @@ -339,7 +389,8 @@ #endif cmd_lwa = 0; - for (slot = 0; slot < 8; ++slot) + for (slot = pcibr_soft->bs_min_slot; + slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) { cmd_reg = pcibr_soft-> bs_slot[slot]. @@ -366,28 +417,54 @@ cmd_lwa[0]; /* Flush all the write buffers in the bridge */ - for (slot = 0; slot < 8; ++slot) + for (slot = pcibr_soft->bs_min_slot; + slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) { if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) { /* Flush the write buffer associated with this * PCI device which might be using dma map RAM. */ - bridge->b_wr_req_buf[slot].reg; + if ( is_pic(bridge) ) { + bridge->b_wr_req_buf[slot].reg; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge)) ) { + BRIDGE_REG_GET32((&bridge->b_wr_req_buf[slot].reg)); + } + else + bridge->b_wr_req_buf[slot].reg; + } } + } } return s; } -#define ATE_WRITE() ate_write(ate_ptr, ate_count, ate) - void -ate_write(bridge_ate_p ate_ptr, +ate_write(pcibr_soft_t pcibr_soft, + bridge_ate_p ate_ptr, int ate_count, bridge_ate_t ate) { - while (ate_count-- > 0) { - *ate_ptr++ = ate; - ate += IOPGSIZE; - } + if (IS_PIC_SOFT(pcibr_soft) ) { + while (ate_count-- > 0) { + *ate_ptr++ = ate; + ate += IOPGSIZE; + } + } + else { + if (io_get_sh_swapper(NASID_GET(ate_ptr))) { + while (ate_count-- > 0) { + *ate_ptr++ = __swab64(ate); + ate += IOPGSIZE; + } + } + else { + while (ate_count-- > 0) { + *ate_ptr++ = ate; + ate += IOPGSIZE; + } + } + } } #if PCIBR_FREEZE_TIME @@ -425,10 +502,24 @@ return; /* restore cmd regs */ - for (slot = 0; slot < 8; ++slot) - if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER) - bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg; - + for (slot = pcibr_soft->bs_min_slot; + slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) { + if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER) { + if ( IS_PIC_SOFT(pcibr_soft) ) { + pcibr_slot_config_set(bridge, slot, PCI_CFG_COMMAND/4, cmd_reg); + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = __swab32(cmd_reg); + } + else { +// BUG(); /* Does this really work if called when io_get_sh_swapper = 0? */ +// bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg; + pcibr_slot_config_set(bridge, slot, PCI_CFG_COMMAND/4, cmd_reg); + } + } + } + } pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_BUSY; atomic_inc(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active)); @@ -442,7 +533,7 @@ if (max_ate_total < ate_total) max_ate_total = ate_total; pcibr_unlock(pcibr_soft, s); - printk("%s: pci freeze time %d usec for %d ATEs\n" + printk( "%s: pci freeze time %d usec for %d ATEs\n" "\tfirst ate: %R\n", pcibr_soft->bs_name, freeze_time * 1000 / 1250, diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c Wed Jan 15 16:57:29 2003 @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -34,64 +35,233 @@ extern pcibr_info_t pcibr_info_get(devfs_handle_t); uint64_t pcibr_config_get(devfs_handle_t, unsigned, unsigned); -uint64_t do_pcibr_config_get(cfg_p, unsigned, unsigned); +uint64_t do_pcibr_config_get(int, cfg_p, unsigned, unsigned); void pcibr_config_set(devfs_handle_t, unsigned, unsigned, uint64_t); -void do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t); +void do_pcibr_config_set(int, cfg_p, unsigned, unsigned, uint64_t); +static void swap_do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t); +#ifdef LITTLE_ENDIAN +/* + * on sn-ia we need to twiddle the the addresses going out + * the pci bus because we use the unswizzled synergy space + * (the alternative is to use the swizzled synergy space + * and byte swap the data) + */ +#define CB(b,r) (((volatile uint8_t *) b)[((r)^4)]) +#define CS(b,r) (((volatile uint16_t *) b)[((r^4)/2)]) +#define CW(b,r) (((volatile uint32_t *) b)[((r^4)/4)]) + +#define CBP(b,r) (((volatile uint8_t *) b)[(r)^3]) +#define CSP(b,r) (((volatile uint16_t *) b)[((r)/2)^1]) +#define CWP(b,r) (((volatile uint32_t *) b)[(r)/4]) + +#define SCB(b,r) (((volatile uint8_t *) b)[((r)^3)]) +#define SCS(b,r) (((volatile uint16_t *) b)[((r^2)/2)]) +#define SCW(b,r) (((volatile uint32_t *) b)[((r)/4)]) +#else #define CB(b,r) (((volatile uint8_t *) cfgbase)[(r)^3]) #define CS(b,r) (((volatile uint16_t *) cfgbase)[((r)/2)^1]) #define CW(b,r) (((volatile uint32_t *) cfgbase)[(r)/4]) +#endif +/* + * Return a config space address for given slot / func / offset. Note the + * returned pointer is a 32bit word (ie. cfg_p) aligned pointer pointing to + * the 32bit word that contains the "offset" byte. + */ +cfg_p +pcibr_func_config_addr(bridge_t *bridge, pciio_bus_t bus, pciio_slot_t slot, + pciio_function_t func, int offset) +{ + /* + * Type 1 config space + */ + if (bus > 0) { + bridge->b_pci_cfg = ((bus << 16) | (slot << 11)); + return &bridge->b_type1_cfg.f[func].l[(offset)]; + } + + /* + * Type 0 config space + */ + if (is_pic(bridge)) + slot++; + return &bridge->b_type0_cfg_dev[slot].f[func].l[offset]; +} + +/* + * Return config space address for given slot / offset. Note the returned + * pointer is a 32bit word (ie. cfg_p) aligned pointer pointing to the + * 32bit word that contains the "offset" byte. + */ +cfg_p +pcibr_slot_config_addr(bridge_t *bridge, pciio_slot_t slot, int offset) +{ + return pcibr_func_config_addr(bridge, 0, slot, 0, offset); +} + +/* + * Return config space data for given slot / offset + */ +unsigned +pcibr_slot_config_get(bridge_t *bridge, pciio_slot_t slot, int offset) +{ + cfg_p cfg_base; + + cfg_base = pcibr_slot_config_addr(bridge, slot, 0); + return (do_pcibr_config_get(is_pic(bridge), cfg_base, offset, sizeof(unsigned))); +} + +/* + * Return config space data for given slot / func / offset + */ +unsigned +pcibr_func_config_get(bridge_t *bridge, pciio_slot_t slot, + pciio_function_t func, int offset) +{ + cfg_p cfg_base; + + cfg_base = pcibr_func_config_addr(bridge, 0, slot, func, 0); + return (do_pcibr_config_get(is_pic(bridge), cfg_base, offset, sizeof(unsigned))); +} + +/* + * Set config space data for given slot / offset + */ +void +pcibr_slot_config_set(bridge_t *bridge, pciio_slot_t slot, + int offset, unsigned val) +{ + cfg_p cfg_base; + + cfg_base = pcibr_slot_config_addr(bridge, slot, 0); + do_pcibr_config_set(is_pic(bridge), cfg_base, offset, sizeof(unsigned), val); +} + +/* + * Set config space data for given slot / func / offset + */ +void +pcibr_func_config_set(bridge_t *bridge, pciio_slot_t slot, + pciio_function_t func, int offset, unsigned val) +{ + cfg_p cfg_base; + + cfg_base = pcibr_func_config_addr(bridge, 0, slot, func, 0); + do_pcibr_config_set(is_pic(bridge), cfg_base, offset, sizeof(unsigned), val); +} + +int pcibr_config_debug = 0; cfg_p pcibr_config_addr(devfs_handle_t conn, unsigned reg) { pcibr_info_t pcibr_info; + pciio_bus_t pciio_bus; pciio_slot_t pciio_slot; pciio_function_t pciio_func; pcibr_soft_t pcibr_soft; bridge_t *bridge; cfg_p cfgbase = (cfg_p)0; + pciio_info_t pciio_info; + pciio_info = pciio_info_get(conn); pcibr_info = pcibr_info_get(conn); - pciio_slot = pcibr_info->f_slot; + /* + * Determine the PCI bus/slot/func to generate a config address for. + */ + + if (pciio_info_type1_get(pciio_info)) { + /* + * Conn is a vhdl which uses TYPE 1 addressing explicitly passed + * in reg. + */ + pciio_bus = PCI_TYPE1_BUS(reg); + pciio_slot = PCI_TYPE1_SLOT(reg); + pciio_func = PCI_TYPE1_FUNC(reg); + + ASSERT(pciio_bus != 0); +#if 0 + } else if (conn != pciio_info_hostdev_get(pciio_info)) { + /* + * Conn is on a subordinate bus, so get bus/slot/func directly from + * its pciio_info_t structure. + */ + pciio_bus = pciio_info->c_bus; + pciio_slot = pciio_info->c_slot; + pciio_func = pciio_info->c_func; + if (pciio_func == PCIIO_FUNC_NONE) { + pciio_func = 0; + } +#endif + } else { + /* + * Conn is directly connected to the host bus. PCI bus number is + * hardcoded to 0 (even though it may have a logical bus number != 0) + * and slot/function are derived from the pcibr_info_t associated + * with the device. + */ + pciio_bus = 0; + + pciio_slot = PCIBR_INFO_SLOT_GET_INT(pcibr_info); if (pciio_slot == PCIIO_SLOT_NONE) pciio_slot = PCI_TYPE1_SLOT(reg); pciio_func = pcibr_info->f_func; if (pciio_func == PCIIO_FUNC_NONE) pciio_func = PCI_TYPE1_FUNC(reg); + } pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast; bridge = pcibr_soft->bs_base; - cfgbase = bridge->b_type0_cfg_dev[pciio_slot].f[pciio_func].l; + cfgbase = pcibr_func_config_addr(bridge, + pciio_bus, pciio_slot, pciio_func, 0); return cfgbase; } +extern unsigned char Is_pic_on_this_nasid[]; uint64_t pcibr_config_get(devfs_handle_t conn, unsigned reg, unsigned size) { - return do_pcibr_config_get(pcibr_config_addr(conn, reg), - PCI_TYPE1_REG(reg), size); + if ( !Is_pic_on_this_nasid[ NASID_GET((pcibr_config_addr(conn, reg)))] ) + return do_pcibr_config_get(0, pcibr_config_addr(conn, reg), + PCI_TYPE1_REG(reg), size); + else + return do_pcibr_config_get(1, pcibr_config_addr(conn, reg), + PCI_TYPE1_REG(reg), size); } uint64_t do_pcibr_config_get( + int pic, cfg_p cfgbase, unsigned reg, unsigned size) { unsigned value; - value = CW(cfgbase, reg); - + if ( pic ) { + value = CWP(cfgbase, reg); + } + else { + if ( io_get_sh_swapper(NASID_GET(cfgbase)) ) { + /* + * Shub Swapper on - 0 returns PCI Offset 0 but byte swapped! + * Do not swizzle address and byte swap the result. + */ + value = SCW(cfgbase, reg); + value = __swab32(value); + } else { + value = CW(cfgbase, reg); + } + } if (reg & 3) value >>= 8 * (reg & 3); if (size < 4) @@ -105,39 +275,103 @@ unsigned size, uint64_t value) { - do_pcibr_config_set(pcibr_config_addr(conn, reg), + if ( Is_pic_on_this_nasid[ NASID_GET((pcibr_config_addr(conn, reg)))] ) + do_pcibr_config_set(1, pcibr_config_addr(conn, reg), + PCI_TYPE1_REG(reg), size, value); + else + swap_do_pcibr_config_set(pcibr_config_addr(conn, reg), PCI_TYPE1_REG(reg), size, value); } void -do_pcibr_config_set(cfg_p cfgbase, +do_pcibr_config_set(int pic, + cfg_p cfgbase, unsigned reg, unsigned size, uint64_t value) { + if ( pic ) { + switch (size) { + case 1: + CBP(cfgbase, reg) = value; + break; + case 2: + if (reg & 1) { + CBP(cfgbase, reg) = value; + CBP(cfgbase, reg + 1) = value >> 8; + } else + CSP(cfgbase, reg) = value; + break; + case 3: + if (reg & 1) { + CBP(cfgbase, reg) = value; + CSP(cfgbase, (reg + 1)) = value >> 8; + } else { + CSP(cfgbase, reg) = value; + CBP(cfgbase, reg + 2) = value >> 16; + } + break; + case 4: + CWP(cfgbase, reg) = value; + break; + } + } + else { + switch (size) { + case 1: + CB(cfgbase, reg) = value; + break; + case 2: + if (reg & 1) { + CB(cfgbase, reg) = value; + CB(cfgbase, reg + 1) = value >> 8; + } else + CS(cfgbase, reg) = value; + break; + case 3: + if (reg & 1) { + CB(cfgbase, reg) = value; + CS(cfgbase, (reg + 1)) = value >> 8; + } else { + CS(cfgbase, reg) = value; + CB(cfgbase, reg + 2) = value >> 16; + } + break; + case 4: + CW(cfgbase, reg) = value; + break; + } + } +} + +void +swap_do_pcibr_config_set(cfg_p cfgbase, + unsigned reg, + unsigned size, + uint64_t value) +{ + + uint64_t temp_value = 0; + switch (size) { case 1: - CB(cfgbase, reg) = value; - break; + SCB(cfgbase, reg) = value; + break; case 2: - if (reg & 1) { - CB(cfgbase, reg) = value; - CB(cfgbase, reg + 1) = value >> 8; - } else - CS(cfgbase, reg) = value; - break; + temp_value = __swab16(value); + if (reg & 1) { + SCB(cfgbase, reg) = temp_value; + SCB(cfgbase, reg + 1) = temp_value >> 8; + } else + SCS(cfgbase, reg) = temp_value; + break; case 3: - if (reg & 1) { - CB(cfgbase, reg) = value; - CS(cfgbase, (reg + 1)) = value >> 8; - } else { - CS(cfgbase, reg) = value; - CB(cfgbase, reg + 2) = value >> 16; - } - break; + BUG(); + break; case 4: - CW(cfgbase, reg) = value; - break; + temp_value = __swab32(value); + SCW(cfgbase, reg) = temp_value; + break; } } diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c Wed Jan 15 16:57:29 2003 @@ -7,7 +7,6 @@ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved. */ - #include #include #include @@ -40,6 +39,25 @@ #endif /* + * global variables to toggle the different levels of pcibr debugging. + * -pcibr_debug_mask is the mask of the different types of debugging + * you want to enable. See sys/PCI/pcibr_private.h + * -pcibr_debug_module is the module you want to trace. By default + * all modules are trace. For IP35 this value has the format of + * something like "001c10". For IP27 this value is a node number, + * i.e. "1", "2"... For IP30 this is undefined and should be set to + * 'all'. + * -pcibr_debug_widget is the widget you want to trace. For IP27 + * the widget isn't exposed in the hwpath so use the xio slot num. + * i.e. for 'io2' set pcibr_debug_widget to "2". + * -pcibr_debug_slot is the pci slot you want to trace. + */ +uint32_t pcibr_debug_mask = 0x0; /* 0x00000000 to disable */ +char *pcibr_debug_module = "all"; /* 'all' for all modules */ +int pcibr_debug_widget = -1; /* '-1' for all widgets */ +int pcibr_debug_slot = -1; /* '-1' for all slots */ + +/* * Macros related to the Lucent USS 302/312 usb timeout workaround. It * appears that if the lucent part can get into a retry loop if it sees a * DAC on the bus during a pio read retry. The loop is broken after about @@ -64,62 +82,24 @@ * appropriate function name below. */ struct file_operations pcibr_fops = { - .owner =THIS_MODULE, - .llseek = NULL, - .read = NULL, - .write = NULL, - .readdir = NULL, - .poll = NULL, - .ioctl = NULL, - .mmap = NULL, - .open = NULL, - .flush = NULL, - .release = NULL, - .fsync = NULL, - .fasync = NULL, - .lock = NULL, - .readv = NULL, - .writev = NULL -}; - -#ifdef LATER - -#if PCIBR_ATE_DEBUG -static struct reg_values ssram_sizes[] = -{ - {BRIDGE_CTRL_SSRAM_512K, "512k"}, - {BRIDGE_CTRL_SSRAM_128K, "128k"}, - {BRIDGE_CTRL_SSRAM_64K, "64k"}, - {BRIDGE_CTRL_SSRAM_1K, "1k"}, - {0} + owner: THIS_MODULE, + llseek: NULL, + read: NULL, + write: NULL, + readdir: NULL, + poll: NULL, + ioctl: NULL, + mmap: NULL, + open: NULL, + flush: NULL, + release: NULL, + fsync: NULL, + fasync: NULL, + lock: NULL, + readv: NULL, + writev: NULL }; -static struct reg_desc control_bits[] = -{ - {BRIDGE_CTRL_FLASH_WR_EN, 0, "FLASH_WR_EN"}, - {BRIDGE_CTRL_EN_CLK50, 0, "EN_CLK50"}, - {BRIDGE_CTRL_EN_CLK40, 0, "EN_CLK40"}, - {BRIDGE_CTRL_EN_CLK33, 0, "EN_CLK33"}, - {BRIDGE_CTRL_RST_MASK, -24, "RST", "%x"}, - {BRIDGE_CTRL_IO_SWAP, 0, "IO_SWAP"}, - {BRIDGE_CTRL_MEM_SWAP, 0, "MEM_SWAP"}, - {BRIDGE_CTRL_PAGE_SIZE, 0, "PAGE_SIZE"}, - {BRIDGE_CTRL_SS_PAR_BAD, 0, "SS_PAR_BAD"}, - {BRIDGE_CTRL_SS_PAR_EN, 0, "SS_PAR_EN"}, - {BRIDGE_CTRL_SSRAM_SIZE_MASK, 0, "SSRAM_SIZE", 0, ssram_sizes}, - {BRIDGE_CTRL_F_BAD_PKT, 0, "F_BAD_PKT"}, - {BRIDGE_CTRL_LLP_XBAR_CRD_MASK, -12, "LLP_XBAR_CRD", "%d"}, - {BRIDGE_CTRL_CLR_RLLP_CNT, 0, "CLR_RLLP_CNT"}, - {BRIDGE_CTRL_CLR_TLLP_CNT, 0, "CLR_TLLP_CNT"}, - {BRIDGE_CTRL_SYS_END, 0, "SYS_END"}, - - {BRIDGE_CTRL_BUS_SPEED_MASK, -4, "BUS_SPEED", "%d"}, - {BRIDGE_CTRL_WIDGET_ID_MASK, 0, "WIDGET_ID", "%x"}, - {0} -}; -#endif -#endif /* LATER */ - /* kbrick widgetnum-to-bus layout */ int p_busnum[MAX_PORT_NUM] = { /* widget# */ 0, 0, 0, 0, 0, 0, 0, 0, /* 0x0 - 0x7 */ @@ -132,18 +112,6 @@ 3, /* 0xf */ }; -/* - * Additional PIO spaces per slot are - * recorded in this structure. - */ -struct pciio_piospace_s { - pciio_piospace_t next; /* another space for this device */ - char free; /* 1 if free, 0 if in use */ - pciio_space_t space; /* Which space is in use */ - iopaddr_t start; /* Starting address of the PIO space */ - size_t count; /* size of PIO space */ -}; - #if PCIBR_SOFT_LIST pcibr_list_p pcibr_list = 0; #endif @@ -152,15 +120,15 @@ extern int hub_device_flags_set(devfs_handle_t widget_dev, hub_widget_flags_t flags); extern long atoi(register char *p); extern cnodeid_t nodevertex_to_cnodeid(devfs_handle_t vhdl); -extern void *swap_ptr(void **loc, void *new); extern char *dev_to_name(devfs_handle_t dev, char *buf, uint buflen); extern struct map *atemapalloc(uint64_t); extern void atefree(struct map *, size_t, uint64_t); extern void atemapfree(struct map *); extern pciio_dmamap_t get_free_pciio_dmamap(devfs_handle_t); extern void free_pciio_dmamap(pcibr_dmamap_t); +extern void xwidget_error_register(devfs_handle_t, error_handler_f *, error_handler_arg_t); -#define ATE_WRITE() ate_write(ate_ptr, ate_count, ate) +#define ATE_WRITE() ate_write(pcibr_soft, ate_ptr, ate_count, ate) #if PCIBR_FREEZE_TIME #define ATE_FREEZE() s = ate_freeze(pcibr_dmamap, &freeze_time, cmd_regs) #else @@ -173,7 +141,6 @@ #define ATE_THAW() ate_thaw(pcibr_dmamap, ate_index, cmd_regs, s) #endif - /* ===================================================================== * Function Table of Contents * @@ -183,58 +150,54 @@ * perhaps bust this file into smaller chunks. */ -extern void do_pcibr_rrb_clear(bridge_t *, int); -extern void do_pcibr_rrb_flush(bridge_t *, int); -extern int do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t); -extern int do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t); -extern int do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int); -extern int do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int); - -extern void do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int); +extern int do_pcibr_rrb_free_all(pcibr_soft_t, bridge_t *, pciio_slot_t); +extern void do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int, int); extern int pcibr_wrb_flush(devfs_handle_t); extern int pcibr_rrb_alloc(devfs_handle_t, int *, int *); -extern int pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *); -extern int pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int); extern void pcibr_rrb_flush(devfs_handle_t); static int pcibr_try_set_device(pcibr_soft_t, pciio_slot_t, unsigned, bridgereg_t); void pcibr_release_device(pcibr_soft_t, pciio_slot_t, bridgereg_t); -extern void pcibr_clearwidint(bridge_t *); extern void pcibr_setwidint(xtalk_intr_t); +extern void pcibr_clearwidint(bridge_t *); + +extern iopaddr_t pcibr_bus_addr_alloc(pcibr_soft_t, pciio_win_info_t, + pciio_space_t, int, int, int); void pcibr_init(void); int pcibr_attach(devfs_handle_t); +int pcibr_attach2(devfs_handle_t, bridge_t *, devfs_handle_t, + int, pcibr_soft_t *); int pcibr_detach(devfs_handle_t); int pcibr_open(devfs_handle_t *, int, int, cred_t *); int pcibr_close(devfs_handle_t, int, int, cred_t *); int pcibr_map(devfs_handle_t, vhandl_t *, off_t, size_t, uint); int pcibr_unmap(devfs_handle_t, vhandl_t *); int pcibr_ioctl(devfs_handle_t, int, void *, int, struct cred *, int *); - -void pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t); - +int pcibr_pcix_rbars_calc(pcibr_soft_t); extern int pcibr_init_ext_ate_ram(bridge_t *); extern int pcibr_ate_alloc(pcibr_soft_t, int); extern void pcibr_ate_free(pcibr_soft_t, int, int); +extern int pcibr_widget_to_bus(devfs_handle_t pcibr_vhdl); -extern unsigned ate_freeze(pcibr_dmamap_t pcibr_dmamap, +extern unsigned ate_freeze(pcibr_dmamap_t pcibr_dmamap, #if PCIBR_FREEZE_TIME unsigned *freeze_time_ptr, #endif - unsigned *cmd_regs); -extern void ate_write(bridge_ate_p ate_ptr, int ate_count, bridge_ate_t ate); -extern void ate_thaw(pcibr_dmamap_t pcibr_dmamap, int ate_index, + unsigned *cmd_regs); +extern void ate_write(pcibr_soft_t pcibr_soft, bridge_ate_p ate_ptr, int ate_count, bridge_ate_t ate); +extern void ate_thaw(pcibr_dmamap_t pcibr_dmamap, int ate_index, #if PCIBR_FREEZE_TIME - bridge_ate_t ate, - int ate_total, - unsigned freeze_time_start, + bridge_ate_t ate, + int ate_total, + unsigned freeze_time_start, #endif - unsigned *cmd_regs, - unsigned s); + unsigned *cmd_regs, + unsigned s); -pcibr_info_t pcibr_info_get(devfs_handle_t); +pcibr_info_t pcibr_info_get(devfs_handle_t); static iopaddr_t pcibr_addr_pci_to_xio(devfs_handle_t, pciio_slot_t, pciio_space_t, iopaddr_t, size_t, unsigned); @@ -264,23 +227,23 @@ void pcibr_dmalist_drain(devfs_handle_t, alenlist_t); iopaddr_t pcibr_dmamap_pciaddr_get(pcibr_dmamap_t); -extern unsigned pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines); +extern unsigned pcibr_intr_bits(pciio_info_t info, + pciio_intr_line_t lines, int nslots); extern pcibr_intr_t pcibr_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t); extern void pcibr_intr_free(pcibr_intr_t); extern void pcibr_setpciint(xtalk_intr_t); -extern int pcibr_intr_connect(pcibr_intr_t); +extern int pcibr_intr_connect(pcibr_intr_t, intr_func_t, intr_arg_t); extern void pcibr_intr_disconnect(pcibr_intr_t); extern devfs_handle_t pcibr_intr_cpu_get(pcibr_intr_t); -extern void pcibr_xintr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t); extern void pcibr_intr_func(intr_arg_t); extern void print_bridge_errcmd(uint32_t, char *); extern void pcibr_error_dump(pcibr_soft_t); -extern uint32_t pcibr_errintr_group(uint32_t); +extern uint32_t pcibr_errintr_group(uint32_t); extern void pcibr_pioerr_check(pcibr_soft_t); -extern void pcibr_error_intr_handler(intr_arg_t); +extern void pcibr_error_intr_handler(int, void *, struct pt_regs *); extern int pcibr_addr_toslot(pcibr_soft_t, iopaddr_t, pciio_space_t *, iopaddr_t *, pciio_function_t *); extern void pcibr_error_cleanup(pcibr_soft_t, int); @@ -289,8 +252,7 @@ extern int pcibr_dmard_error(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *); extern int pcibr_dmawr_error(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *); extern int pcibr_error_handler(error_handler_arg_t, int, ioerror_mode_t, ioerror_t *); -extern int pcibr_error_devenable(devfs_handle_t, int); - +extern int pcibr_error_handler_wrapper(error_handler_arg_t, int, ioerror_mode_t, ioerror_t *); void pcibr_provider_startup(devfs_handle_t); void pcibr_provider_shutdown(devfs_handle_t); @@ -303,7 +265,6 @@ extern cfg_p pcibr_config_addr(devfs_handle_t, unsigned); extern uint64_t pcibr_config_get(devfs_handle_t, unsigned, unsigned); extern void pcibr_config_set(devfs_handle_t, unsigned, unsigned, uint64_t); -extern void do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t); extern pcibr_hints_t pcibr_hints_get(devfs_handle_t, int); extern void pcibr_hints_fix_rrbs(devfs_handle_t); @@ -313,38 +274,31 @@ extern void pcibr_hints_handsoff(devfs_handle_t); extern void pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, uint64_t); -#ifdef BRIDGE_B_DATACORR_WAR -extern int ql_bridge_rev_b_war(devfs_handle_t); -extern int bridge_rev_b_data_check_disable; -char *rev_b_datacorr_warning = -"***************************** WARNING! ******************************\n"; -char *rev_b_datacorr_mesg = -"UNRECOVERABLE IO LINK ERROR. CONTACT SERVICE PROVIDER\n"; -#endif - extern int pcibr_slot_reset(devfs_handle_t,pciio_slot_t); extern int pcibr_slot_info_init(devfs_handle_t,pciio_slot_t); extern int pcibr_slot_info_free(devfs_handle_t,pciio_slot_t); +extern int pcibr_slot_info_return(pcibr_soft_t, pciio_slot_t, + pcibr_slot_info_resp_t); +extern void pcibr_slot_func_info_return(pcibr_info_h, int, + pcibr_slot_func_info_resp_t); extern int pcibr_slot_addr_space_init(devfs_handle_t,pciio_slot_t); +extern int pcibr_slot_pcix_rbar_init(pcibr_soft_t, pciio_slot_t); extern int pcibr_slot_device_init(devfs_handle_t, pciio_slot_t); extern int pcibr_slot_guest_info_init(devfs_handle_t,pciio_slot_t); -extern int pcibr_slot_call_device_attach(devfs_handle_t, pciio_slot_t, int); -extern int pcibr_slot_call_device_detach(devfs_handle_t, pciio_slot_t, int); -extern int pcibr_slot_attach(devfs_handle_t, pciio_slot_t, int, char *, int *); -extern int pcibr_slot_detach(devfs_handle_t, pciio_slot_t, int); +extern int pcibr_slot_call_device_attach(devfs_handle_t, + pciio_slot_t, int); +extern int pcibr_slot_call_device_detach(devfs_handle_t, + pciio_slot_t, int); +extern int pcibr_slot_attach(devfs_handle_t, pciio_slot_t, int, + char *, int *); +extern int pcibr_slot_detach(devfs_handle_t, pciio_slot_t, int, + char *, int *); extern int pcibr_is_slot_sys_critical(devfs_handle_t, pciio_slot_t); -#ifdef LATER -extern int pcibr_slot_startup(devfs_handle_t, pcibr_slot_req_t); -extern int pcibr_slot_shutdown(devfs_handle_t, pcibr_slot_req_t); -extern int pcibr_slot_query(devfs_handle_t, pcibr_slot_req_t); -#endif - extern int pcibr_slot_initial_rrb_alloc(devfs_handle_t, pciio_slot_t); extern int pcibr_initial_rrb(devfs_handle_t, pciio_slot_t, pciio_slot_t); - /* ===================================================================== * Device(x) register management */ @@ -377,7 +331,7 @@ bridgereg_t xmask; xmask = mask; - if (pcibr_soft->bs_xbridge) { + if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) { if (mask == BRIDGE_DEV_PMU_BITS) xmask = XBRIDGE_DEV_PMU_BITS; if (mask == BRIDGE_DEV_D64_BITS) @@ -464,10 +418,10 @@ new &= ~BRIDGE_DEV_WRGA_BITS; if (flags & PCIIO_BYTE_STREAM) - new |= (pcibr_soft->bs_xbridge) ? + new |= (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) ? BRIDGE_DEV_SWAP_DIR : BRIDGE_DEV_SWAP_BITS; if (flags & PCIIO_WORD_VALUES) - new &= (pcibr_soft->bs_xbridge) ? + new &= (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) ? ~BRIDGE_DEV_SWAP_DIR : ~BRIDGE_DEV_SWAP_BITS; /* Provider-specific flags @@ -492,13 +446,28 @@ if (flags & PCIBR_NO64BIT) new &= ~BRIDGE_DEV_DEV_SIZE; + /* + * PIC BRINGUP WAR (PV# 855271): + * Allow setting BRIDGE_DEV_VIRTUAL_EN on PIC iff we're a 64-bit + * device. The bit is only intended for 64-bit devices and, on + * PIC, can cause problems for 32-bit devices. + */ + if (IS_PIC_SOFT(pcibr_soft) && mask == BRIDGE_DEV_D64_BITS && + PCIBR_WAR_ENABLED(PV855271, pcibr_soft)) { + if (flags & PCIBR_VCHAN1) { + new |= BRIDGE_DEV_VIRTUAL_EN; + xmask |= BRIDGE_DEV_VIRTUAL_EN; + } + } + + chg = old ^ new; /* what are we changing, */ chg &= xmask; /* of the interesting bits */ if (chg) { badd32 = slotp->bss_d32_uctr ? (BRIDGE_DEV_D32_BITS & chg) : 0; - if (pcibr_soft->bs_xbridge) { + if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) { badpmu = slotp->bss_pmu_uctr ? (XBRIDGE_DEV_PMU_BITS & chg) : 0; badd64 = slotp->bss_d64_uctr ? (XBRIDGE_DEV_D64_BITS & chg) : 0; } else { @@ -517,7 +486,7 @@ * the new stream at all. */ if ( (fix = bad & (BRIDGE_DEV_PRECISE | - BRIDGE_DEV_BARRIER)) ){ + BRIDGE_DEV_BARRIER)) ) { bad &= ~fix; /* don't change these bits if * they are already set in "old" @@ -546,8 +515,10 @@ */ if (bad) { pcibr_unlock(pcibr_soft, s); -#if (DEBUG && PCIBR_DEV_DEBUG) - printk("pcibr_try_set_device: mod blocked by %R\n", bad, device_bits); +#ifdef PIC_LATER + PCIBR_DEBUG((PCIBR_DEBUG_DEVREG, pcibr_soft->bs_vhdl, + "pcibr_try_set_device: mod blocked by %x\n", + bad, device_bits)); #endif return bad; } @@ -571,14 +542,31 @@ pcibr_unlock(pcibr_soft, s); return 0; } - bridge->b_device[slot].reg = new; - slotp->bss_device = new; - bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + if ( IS_PIC_SOFT(pcibr_soft) ) { + bridge->b_device[slot].reg = new; + slotp->bss_device = new; + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_SET32((&bridge->b_device[slot].reg)) = __swab32(new); + slotp->bss_device = new; + BRIDGE_REG_GET32((&bridge->b_wid_tflush)); /* wait until Bridge PIO complete */ + } else { + bridge->b_device[slot].reg = new; + slotp->bss_device = new; + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } + } pcibr_unlock(pcibr_soft, s); -#if DEBUG && PCIBR_DEV_DEBUG - printk("pcibr Device(%d): 0x%p\n", slot, bridge->b_device[slot].reg); -#endif +#ifdef PIC_LATER + PCIBR_DEBUG((PCIBR_DEBUG_DEVREG, pcibr_soft->bs_vhdl, + "pcibr_try_set_device: Device(%d): %x\n", + slot, new, device_bits)); +#else + printk("pcibr_try_set_device: Device(%d): %x\n", slot, new); +#endif return 0; } @@ -616,7 +604,17 @@ volatile uint32_t wrf; s = pcibr_lock(pcibr_soft); bridge = pcibr_soft->bs_base; - wrf = bridge->b_wr_req_buf[slot].reg; + + if ( IS_PIC_SOFT(pcibr_soft) ) { + wrf = bridge->b_wr_req_buf[slot].reg; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + wrf = BRIDGE_REG_GET32((&bridge->b_wr_req_buf[slot].reg)); + } else { + wrf = bridge->b_wr_req_buf[slot].reg; + } + } pcibr_unlock(pcibr_soft, s); } @@ -637,9 +635,7 @@ void pcibr_init(void) { -#if DEBUG && ATTACH_DEBUG - printk("pcibr_init\n"); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INIT, NULL, "pcibr_init()\n")); xwidget_driver_register(XBRIDGE_WIDGET_PART_NUM, XBRIDGE_WIDGET_MFGR_NUM, @@ -700,7 +696,7 @@ * XXX- deprecate this in favor of using the * real flash driver ... */ - if (!error && + if (IS_BRIDGE_SOFT(pcibr_soft) && !error && ((off == BRIDGE_EXTERNAL_FLASH) || (len > BRIDGE_EXTERNAL_FLASH))) { int s; @@ -710,11 +706,16 @@ * The read following the write is required for the Bridge war */ s = splhi(); - bridge->b_wid_control |= BRIDGE_CTRL_FLASH_WR_EN; - bridge->b_wid_control; /* inval addr bug war */ + + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_SET32((&bridge->b_wid_control)) |= __swab32(BRIDGE_CTRL_FLASH_WR_EN); + BRIDGE_REG_GET32((&bridge->b_wid_control)); /* inval addr bug war */ + } else { + bridge->b_wid_control |= BRIDGE_CTRL_FLASH_WR_EN; + bridge->b_wid_control; /* inval addr bug war */ + } splx(s); } - return error; } @@ -728,21 +729,53 @@ hwgraph_vertex_unref(pcibr_vhdl); - /* - * If flashprom write was enabled, disable it, as - * this is the last unmap. - */ - if (bridge->b_wid_control & BRIDGE_CTRL_FLASH_WR_EN) { - int s; - + if ( IS_PIC_SOFT(pcibr_soft) ) { /* - * ensure that we write and read without any interruption. - * The read following the write is required for the Bridge war + * If flashprom write was enabled, disable it, as + * this is the last unmap. */ - s = splhi(); - bridge->b_wid_control &= ~BRIDGE_CTRL_FLASH_WR_EN; - bridge->b_wid_control; /* inval addr bug war */ - splx(s); + if (IS_BRIDGE_SOFT(pcibr_soft) && + (bridge->b_wid_control & BRIDGE_CTRL_FLASH_WR_EN)) { + int s; + + /* + * ensure that we write and read without any interruption. + * The read following the write is required for the Bridge war + */ + s = splhi(); + bridge->b_wid_control &= ~BRIDGE_CTRL_FLASH_WR_EN; + bridge->b_wid_control; /* inval addr bug war */ + splx(s); + } + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + if (BRIDGE_REG_GET32((&bridge->b_wid_control)) & BRIDGE_CTRL_FLASH_WR_EN) { + int s; + + /* + * ensure that we write and read without any interruption. + * The read following the write is required for the Bridge war + */ + s = splhi(); + BRIDGE_REG_SET32((&bridge->b_wid_control)) &= __swab32((unsigned int)~BRIDGE_CTRL_FLASH_WR_EN); + BRIDGE_REG_GET32((&bridge->b_wid_control)); /* inval addr bug war */ + splx(s); + } else { + if (bridge->b_wid_control & BRIDGE_CTRL_FLASH_WR_EN) { + int s; + + /* + * ensure that we write and read without any interruption. + * The read following the write is required for the Bridge war + */ + s = splhi(); + bridge->b_wid_control &= ~BRIDGE_CTRL_FLASH_WR_EN; + bridge->b_wid_control; /* inval addr bug war */ + splx(s); + } + } + } } return 0; } @@ -768,7 +801,7 @@ while (tdev != GRAPH_VERTEX_NONE) { pciio_info = pciio_info_chk(tdev); if (pciio_info) { - slot = pciio_info_slot_get(pciio_info); + slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); break; } hwgraph_vertex_unref(tdev); @@ -788,167 +821,7 @@ struct cred *cr, int *rvalp) { - devfs_handle_t pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t)dev); -#ifdef LATER - pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl); -#endif - int error = 0; - - hwgraph_vertex_unref(pcibr_vhdl); - - switch (cmd) { -#ifdef LATER - case GIOCSETBW: - { - grio_ioctl_info_t info; - pciio_slot_t slot = 0; - - if (!cap_able((uint64_t)CAP_DEVICE_MGT)) { - error = EPERM; - break; - } - if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) { - error = EFAULT; - break; - } -#ifdef GRIO_DEBUG - printk("pcibr:: prev_vhdl: %d reqbw: %lld\n", - info.prev_vhdl, info.reqbw); -#endif /* GRIO_DEBUG */ - - if ((slot = pcibr_device_slot_get(info.prev_vhdl)) == - PCIIO_SLOT_NONE) { - error = EIO; - break; - } - if (info.reqbw) - pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_HIGH); - break; - } - - case GIOCRELEASEBW: - { - grio_ioctl_info_t info; - pciio_slot_t slot = 0; - - if (!cap_able(CAP_DEVICE_MGT)) { - error = EPERM; - break; - } - if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) { - error = EFAULT; - break; - } -#ifdef GRIO_DEBUG - printk("pcibr:: prev_vhdl: %d reqbw: %lld\n", - info.prev_vhdl, info.reqbw); -#endif /* GRIO_DEBUG */ - - if ((slot = pcibr_device_slot_get(info.prev_vhdl)) == - PCIIO_SLOT_NONE) { - error = EIO; - break; - } - if (info.reqbw) - pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_LOW); - break; - } - - case PCIBR_SLOT_STARTUP: - { - struct pcibr_slot_req_s req; - - if (!cap_able(CAP_DEVICE_MGT)) { - error = EPERM; - break; - } - - if (COPYIN(arg, &req, sizeof(req))) { - error = EFAULT; - break; - } - - error = pcibr_slot_startup(pcibr_vhdl, &req); - break; - } - case PCIBR_SLOT_SHUTDOWN: - { - struct pcibr_slot_req_s req; - - if (!cap_able(CAP_DEVICE_MGT)) { - error = EPERM; - break; - } - - if (COPYIN(arg, &req, sizeof(req))) { - error = EFAULT; - break; - } - - error = pcibr_slot_shutdown(pcibr_vhdl, &req); - break; - } - case PCIBR_SLOT_QUERY: - { - struct pcibr_slot_req_s req; - - if (!cap_able(CAP_DEVICE_MGT)) { - error = EPERM; - break; - } - - if (COPYIN(arg, &req, sizeof(req))) { - error = EFAULT; - break; - } - - error = pcibr_slot_query(pcibr_vhdl, &req); - break; - } -#endif /* LATER */ - default: - break; - - } - - return error; -} - -void -pcibr_freeblock_sub(iopaddr_t *free_basep, - iopaddr_t *free_lastp, - iopaddr_t base, - size_t size) -{ - iopaddr_t free_base = *free_basep; - iopaddr_t free_last = *free_lastp; - iopaddr_t last = base + size - 1; - - if ((last < free_base) || (base > free_last)); /* free block outside arena */ - - else if ((base <= free_base) && (last >= free_last)) - /* free block contains entire arena */ - *free_basep = *free_lastp = 0; - - else if (base <= free_base) - /* free block is head of arena */ - *free_basep = last + 1; - - else if (last >= free_last) - /* free block is tail of arena */ - *free_lastp = base - 1; - - /* - * We are left with two regions: the free area - * in the arena "below" the block, and the free - * area in the arena "above" the block. Keep - * the one that is bigger. - */ - - else if ((base - free_base) > (free_last - last)) - *free_lastp = base - 1; /* keep lower chunk */ - else - *free_basep = last + 1; /* keep upper chunk */ + return 0; } pcibr_info_t @@ -971,16 +844,22 @@ func = (rfunc == PCIIO_FUNC_NONE) ? 0 : rfunc; + /* + * Create a pciio_info_s for this device. pciio_device_info_new() + * will set the c_slot (which is suppose to represent the external + * slot (i.e the slot number silk screened on the back of the I/O + * brick)). So for PIC we need to adjust this "internal slot" num + * passed into us, into it's external representation. See comment + * for the PCIBR_DEVICE_TO_SLOT macro for more information. + */ NEW(pcibr_info); + pciio_device_info_new(&pcibr_info->f_c, pcibr_soft->bs_vhdl, + PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), + rfunc, vendor, device); + pcibr_info->f_dev = slot; - pciio_device_info_new(&pcibr_info->f_c, - pcibr_soft->bs_vhdl, - slot, rfunc, - vendor, device); - -/* pfg - this is new ..... */ /* Set PCI bus number */ - pcibr_info->f_bus = io_path_map_widget(pcibr_soft->bs_vhdl); + pcibr_info->f_bus = pcibr_widget_to_bus(pcibr_soft->bs_vhdl); if (slot != PCIIO_SLOT_NONE) { @@ -1016,30 +895,6 @@ } -/* FIXME: for now this is needed by both pcibr.c and - * pcibr_slot.c. Need to find a better way, the least - * of which would be to move it to pcibr_private.h - */ - -/* - * PCI_ADDR_SPACE_LIMITS_STORE - * Sets the current values of - * pci io base, - * pci io last, - * pci low memory base, - * pci low memory last, - * pci high memory base, - * pci high memory last - */ -#define PCI_ADDR_SPACE_LIMITS_STORE() \ - pcibr_soft->bs_spinfo.pci_io_base = pci_io_fb; \ - pcibr_soft->bs_spinfo.pci_io_last = pci_io_fl; \ - pcibr_soft->bs_spinfo.pci_swin_base = pci_lo_fb; \ - pcibr_soft->bs_spinfo.pci_swin_last = pci_lo_fl; \ - pcibr_soft->bs_spinfo.pci_mem_base = pci_hi_fb; \ - pcibr_soft->bs_spinfo.pci_mem_last = pci_hi_fl; - - /* * pcibr_device_unregister * This frees up any hardware resources reserved for this PCI device @@ -1062,7 +917,7 @@ pciio_info = pciio_info_get(pconn_vhdl); pcibr_vhdl = pciio_info_master_get(pciio_info); - slot = pciio_info_slot_get(pciio_info); + slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_soft = pcibr_soft_get(pcibr_vhdl); bridge = pcibr_soft->bs_base; @@ -1077,27 +932,24 @@ * If the RRB configuration for this slot has changed, set it * back to the boot-time default */ - if (pcibr_soft->bs_rrb_valid_dflt[slot] >= 0) { + if (pcibr_soft->bs_rrb_valid_dflt[slot][VCHAN0] >= 0) { s = pcibr_lock(pcibr_soft); - /* Free the rrbs allocated to this slot */ - error_call = do_pcibr_rrb_free(bridge, slot, - pcibr_soft->bs_rrb_valid[slot] + - pcibr_soft->bs_rrb_valid[slot + - PCIBR_RRB_SLOT_VIRTUAL]); - - if (error_call) - error = ERANGE; - - pcibr_soft->bs_rrb_res[slot] = pcibr_soft->bs_rrb_res[slot] + - pcibr_soft->bs_rrb_valid[slot] + - pcibr_soft->bs_rrb_valid[slot + - PCIBR_RRB_SLOT_VIRTUAL]; - - count_vchan0 = pcibr_soft->bs_rrb_valid_dflt[slot]; - count_vchan1 = pcibr_soft->bs_rrb_valid_dflt[slot + - PCIBR_RRB_SLOT_VIRTUAL]; + /* PIC NOTE: If this is a BRIDGE, VCHAN2 & VCHAN3 will be zero so + * no need to conditionalize this (ie. "if (IS_PIC_SOFT())" ). + */ + pcibr_soft->bs_rrb_res[slot] = pcibr_soft->bs_rrb_res[slot] + + pcibr_soft->bs_rrb_valid[slot][VCHAN0] + + pcibr_soft->bs_rrb_valid[slot][VCHAN1] + + pcibr_soft->bs_rrb_valid[slot][VCHAN2] + + pcibr_soft->bs_rrb_valid[slot][VCHAN3]; + + /* Free the rrbs allocated to this slot, both the normal & virtual */ + do_pcibr_rrb_free_all(pcibr_soft, bridge, slot); + + count_vchan0 = pcibr_soft->bs_rrb_valid_dflt[slot][VCHAN0]; + count_vchan1 = pcibr_soft->bs_rrb_valid_dflt[slot][VCHAN1]; pcibr_unlock(pcibr_soft, s); @@ -1147,12 +999,14 @@ pcibr_info = pcibr_info_get(pconn_vhdl); pcibr_vhdl = pciio_info_master_get(pciio_info); - slot = pciio_info_slot_get(pciio_info); + slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_soft = pcibr_soft_get(pcibr_vhdl); +#ifdef PIC_LATER /* This may be a loadable driver so lock out any pciconfig actions */ mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO); +#endif pcibr_info->f_att_det_error = error; @@ -1164,9 +1018,10 @@ pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT; } +#ifdef PIC_LATER /* Release the bus lock */ mrunlock(pcibr_soft->bs_bus_lock); - +#endif } /* @@ -1195,12 +1050,14 @@ pcibr_info = pcibr_info_get(pconn_vhdl); pcibr_vhdl = pciio_info_master_get(pciio_info); - slot = pciio_info_slot_get(pciio_info); + slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_soft = pcibr_soft_get(pcibr_vhdl); +#ifdef PIC_LATER /* This may be a loadable driver so lock out any pciconfig actions */ mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO); +#endif pcibr_info->f_att_det_error = error; @@ -1211,10 +1068,11 @@ } else { pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT; } - + +#ifdef PIC_LATER /* Release the bus lock */ mrunlock(pcibr_soft->bs_bus_lock); - +#endif } /* @@ -1226,7 +1084,7 @@ * depends on hwgraph separator == '/' */ int -pcibr_bus_cnvlink(devfs_handle_t f_c, int slot) +pcibr_bus_cnvlink(devfs_handle_t f_c) { char dst[MAXDEVNAME]; char *dp = dst; @@ -1236,16 +1094,7 @@ devfs_handle_t nvtx, svtx; int rv; -#if DEBUG - printk("pcibr_bus_cnvlink: slot= %d f_c= %p\n", - slot, f_c); - { - int pos; - char dname[256]; - pos = devfs_generate_path(f_c, dname, 256); - printk("%s : path= %s\n", __FUNCTION__, &dname[pos]); - } -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATTACH, f_c, "pcibr_bus_cnvlink\n")); if (GRAPH_SUCCESS != hwgraph_vertex_name_get(f_c, dst, MAXDEVNAME)) return 0; @@ -1261,7 +1110,7 @@ return 0; /* remove "/pci/direct" from path */ - cp = strstr(dst, "/" EDGE_LBL_PCI "/" "direct"); + cp = strstr(dst, "/" EDGE_LBL_PCI "/" EDGE_LBL_DIRECT); if (cp == NULL) return 0; *cp = (char)NULL; @@ -1275,7 +1124,8 @@ /* dst example now == /hw/module/001c02/Pbrick */ /* get the bus number */ - strcat(dst, "/bus"); + strcat(dst, "/"); + strcat(dst, EDGE_LBL_BUS); sprintf(pcibus, "%d", p_busnum[widgetnum]); /* link to bus to widget */ @@ -1300,75 +1150,74 @@ /* REFERENCED */ graph_error_t rc; devfs_handle_t pcibr_vhdl; + bridge_t *bridge; + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATTACH, xconn_vhdl, "pcibr_attach\n")); + + bridge = (bridge_t *) + xtalk_piotrans_addr(xconn_vhdl, NULL, + 0, sizeof(bridge_t), 0); + /* + * Create the vertex for the PCI bus, which we + * will also use to hold the pcibr_soft and + * which will be the "master" vertex for all the + * pciio connection points we will hang off it. + * This needs to happen before we call nic_bridge_vertex_info + * as we are some of the *_vmc functions need access to the edges. + * + * Opening this vertex will provide access to + * the Bridge registers themselves. + */ + rc = hwgraph_path_add(xconn_vhdl, EDGE_LBL_PCI, &pcibr_vhdl); + ASSERT(rc == GRAPH_SUCCESS); + + pciio_provider_register(pcibr_vhdl, &pcibr_provider); + pciio_provider_startup(pcibr_vhdl); + + return pcibr_attach2(xconn_vhdl, bridge, pcibr_vhdl, 0, NULL); +} + + +/*ARGSUSED */ +int +pcibr_attach2(devfs_handle_t xconn_vhdl, bridge_t *bridge, + devfs_handle_t pcibr_vhdl, int busnum, pcibr_soft_t *ret_softp) +{ + /* REFERENCED */ devfs_handle_t ctlr_vhdl; - bridge_t *bridge = NULL; bridgereg_t id; int rev; pcibr_soft_t pcibr_soft; pcibr_info_t pcibr_info; xwidget_info_t info; xtalk_intr_t xtalk_intr; - device_desc_t dev_desc = (device_desc_t)0; int slot; int ibit; devfs_handle_t noslot_conn; char devnm[MAXDEVNAME], *s; pcibr_hints_t pcibr_hints; - bridgereg_t b_int_enable; + uint64_t int_enable; + bridgereg_t int_enable_32; + picreg_t int_enable_64; unsigned rrb_fixed = 0; - iopaddr_t pci_io_fb, pci_io_fl; - iopaddr_t pci_lo_fb, pci_lo_fl; - iopaddr_t pci_hi_fb, pci_hi_fl; - int spl_level; -#ifdef LATER - char *nicinfo = (char *)0; -#endif #if PCI_FBBE int fast_back_to_back_enable; #endif - l1sc_t *scp; nasid_t nasid; + int iobrick_type_get_nasid(nasid_t nasid); + int iobrick_module_get_nasid(nasid_t nasid); + extern unsigned char Is_pic_on_this_nasid[512]; - async_attach_t aa = NULL; - aa = async_attach_get_info(xconn_vhdl); - -#if DEBUG && ATTACH_DEBUG - printk("pcibr_attach: xconn_vhdl= %p\n", xconn_vhdl); - { - int pos; - char dname[256]; - pos = devfs_generate_path(xconn_vhdl, dname, 256); - printk("%s : path= %s \n", __FUNCTION__, &dname[pos]); - } -#endif + async_attach_t aa = NULL; - /* Setup the PRB for the bridge in CONVEYOR BELT - * mode. PRBs are setup in default FIRE-AND-FORGET - * mode during the initialization. - */ - hub_device_flags_set(xconn_vhdl, HUB_PIO_CONVEYOR); + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATTACH, pcibr_vhdl, + "pcibr_attach2: bridge=0x%p, busnum=%d\n", bridge, busnum)); - bridge = (bridge_t *) - xtalk_piotrans_addr(xconn_vhdl, NULL, - 0, sizeof(bridge_t), 0); - - /* - * Create the vertex for the PCI bus, which we - * will also use to hold the pcibr_soft and - * which will be the "master" vertex for all the - * pciio connection points we will hang off it. - * This needs to happen before we call nic_bridge_vertex_info - * as we are some of the *_vmc functions need access to the edges. - * - * Opening this vertex will provide access to - * the Bridge registers themselves. - */ - rc = hwgraph_path_add(xconn_vhdl, EDGE_LBL_PCI, &pcibr_vhdl); - ASSERT(rc == GRAPH_SUCCESS); + aa = async_attach_get_info(xconn_vhdl); ctlr_vhdl = NULL; ctlr_vhdl = hwgraph_register(pcibr_vhdl, EDGE_LBL_CONTROLLER, @@ -1380,15 +1229,6 @@ ASSERT(ctlr_vhdl != NULL); /* - * decode the nic, and hang its stuff off our - * connection point where other drivers can get - * at it. - */ -#ifdef LATER - nicinfo = BRIDGE_VERTEX_MFG_INFO(xconn_vhdl, (nic_data_t) & bridge->b_nic); -#endif - - /* * Get the hint structure; if some NIC callback * marked this vertex as "hands-off" then we * just return here, before doing anything else. @@ -1408,26 +1248,63 @@ * fields, and hook it up to our vertex. */ NEW(pcibr_soft); + if (ret_softp) + *ret_softp = pcibr_soft; BZERO(pcibr_soft, sizeof *pcibr_soft); pcibr_soft_set(pcibr_vhdl, pcibr_soft); - pcibr_soft->bs_conn = xconn_vhdl; pcibr_soft->bs_vhdl = pcibr_vhdl; pcibr_soft->bs_base = bridge; pcibr_soft->bs_rev_num = rev; - pcibr_soft->bs_intr_bits = pcibr_intr_bits; + pcibr_soft->bs_intr_bits = (pcibr_intr_bits_f *)pcibr_intr_bits; + + pcibr_soft->bs_min_slot = 0; /* lowest possible slot# */ + pcibr_soft->bs_max_slot = 7; /* highest possible slot# */ + pcibr_soft->bs_busnum = busnum; if (is_xbridge(bridge)) { - pcibr_soft->bs_int_ate_size = XBRIDGE_INTERNAL_ATES; - pcibr_soft->bs_xbridge = 1; + pcibr_soft->bs_bridge_type = PCIBR_BRIDGETYPE_XBRIDGE; + } else if (is_pic(bridge)) { + pcibr_soft->bs_bridge_type = PCIBR_BRIDGETYPE_PIC; } else { + pcibr_soft->bs_bridge_type = PCIBR_BRIDGETYPE_BRIDGE; + } + switch(pcibr_soft->bs_bridge_type) { + case PCIBR_BRIDGETYPE_BRIDGE: pcibr_soft->bs_int_ate_size = BRIDGE_INTERNAL_ATES; - pcibr_soft->bs_xbridge = 0; + pcibr_soft->bs_bridge_mode = 0; /* speed is not available in bridge */ + break; + case PCIBR_BRIDGETYPE_PIC: + pcibr_soft->bs_min_slot = 0; + pcibr_soft->bs_max_slot = 3; + pcibr_soft->bs_int_ate_size = XBRIDGE_INTERNAL_ATES; + pcibr_soft->bs_bridge_mode = + (((bridge->p_wid_stat_64 & PIC_STAT_PCIX_SPEED) >> 33) | + ((bridge->p_wid_stat_64 & PIC_STAT_PCIX_ACTIVE) >> 33)); + + /* We have to clear PIC's write request buffer to avoid parity + * errors. See PV#854845. + */ + { + int i; + + for (i=0; i < PIC_WR_REQ_BUFSIZE; i++) { + bridge->p_wr_req_lower[i] = 0; + bridge->p_wr_req_upper[i] = 0; + bridge->p_wr_req_parity[i] = 0; + } + } + + break; + case PCIBR_BRIDGETYPE_XBRIDGE: + pcibr_soft->bs_int_ate_size = XBRIDGE_INTERNAL_ATES; + pcibr_soft->bs_bridge_mode = + ((bridge->b_wid_control & BRIDGE_CTRL_PCI_SPEED) >> 3); + break; } - nasid = NASID_GET(bridge); - scp = &NODEPDA( NASID_TO_COMPACT_NODEID(nasid) )->module->elsc; - pcibr_soft->bs_l1sc = scp; - pcibr_soft->bs_moduleid = iobrick_module_get(scp); + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATTACH, pcibr_vhdl, + "pcibr_attach2: pcibr_soft=0x%x, mode=0x%x\n", + pcibr_soft, pcibr_soft->bs_bridge_mode)); pcibr_soft->bsi_err_intr = 0; /* Bridges up through REV C @@ -1439,6 +1316,9 @@ pcibr_soft->bs_pio_end_mem = PCIIO_WORD_VALUES; } #if PCIBR_SOFT_LIST + /* + * link all the pcibr_soft structs + */ { pcibr_list_p self; @@ -1446,9 +1326,9 @@ self->bl_soft = pcibr_soft; self->bl_vhdl = pcibr_vhdl; self->bl_next = pcibr_list; - self->bl_next = swap_ptr((void **) &pcibr_list, (void *)self); + pcibr_list = self; } -#endif +#endif /* PCIBR_SOFT_LIST */ /* * get the name of this bridge vertex and keep the info. Use this @@ -1458,45 +1338,114 @@ pcibr_soft->bs_name = kmalloc(strlen(s) + 1, GFP_KERNEL); strcpy(pcibr_soft->bs_name, s); -#if SHOW_REVS || DEBUG -#if !DEBUG - if (kdebug) -#endif - printk("%sBridge ASIC: rev %s (code=0x%x) at %s\n", - is_xbridge(bridge) ? "X" : "", - (rev == BRIDGE_PART_REV_A) ? "A" : - (rev == BRIDGE_PART_REV_B) ? "B" : - (rev == BRIDGE_PART_REV_C) ? "C" : - (rev == BRIDGE_PART_REV_D) ? "D" : - (rev == XBRIDGE_PART_REV_A) ? "A" : - (rev == XBRIDGE_PART_REV_B) ? "B" : - "unknown", - rev, pcibr_soft->bs_name); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATTACH, pcibr_vhdl, + "pcibr_attach2: %s ASIC: rev %s (code=0x%x)\n", + IS_XBRIDGE_SOFT(pcibr_soft) ? "XBridge" : + IS_PIC_SOFT(pcibr_soft) ? "PIC" : "Bridge", + (rev == BRIDGE_PART_REV_A) ? "A" : + (rev == BRIDGE_PART_REV_B) ? "B" : + (rev == BRIDGE_PART_REV_C) ? "C" : + (rev == BRIDGE_PART_REV_D) ? "D" : + (rev == XBRIDGE_PART_REV_A) ? "A" : + (rev == XBRIDGE_PART_REV_B) ? "B" : + (IS_PIC_PART_REV_A(rev)) ? "A" : + "unknown", rev, pcibr_soft->bs_name)); info = xwidget_info_get(xconn_vhdl); pcibr_soft->bs_xid = xwidget_info_id_get(info); pcibr_soft->bs_master = xwidget_info_master_get(info); pcibr_soft->bs_mxid = xwidget_info_masterid_get(info); + pcibr_soft->bs_first_slot = pcibr_soft->bs_min_slot; + pcibr_soft->bs_last_slot = pcibr_soft->bs_max_slot; /* - * Init bridge lock. + * Bridge can only reset slots 0, 1, 2, and 3. Ibrick internal + * slots 4, 5, 6, and 7 must be reset as a group, so do not + * reset them. */ - spin_lock_init(&pcibr_soft->bs_lock); + pcibr_soft->bs_last_reset = 3; + + nasid = NASID_GET(bridge); + + /* set whether it is a PIC or not */ + Is_pic_on_this_nasid[nasid] = (IS_PIC_SOFT(pcibr_soft)) ? 1 : 0; + + + if ((pcibr_soft->bs_bricktype = iobrick_type_get_nasid(nasid)) < 0) + printk(KERN_WARNING "0x%p: Unknown bricktype : 0x%x\n", (void *)xconn_vhdl, + (unsigned int)pcibr_soft->bs_bricktype); + + pcibr_soft->bs_moduleid = iobrick_module_get_nasid(nasid); + + if (pcibr_soft->bs_bricktype > 0) { + switch (pcibr_soft->bs_bricktype) { + case MODULE_PXBRICK: + pcibr_soft->bs_first_slot = 0; + pcibr_soft->bs_last_slot = 1; + pcibr_soft->bs_last_reset = 1; + break; + case MODULE_PEBRICK: + case MODULE_PBRICK: + pcibr_soft->bs_first_slot = 1; + pcibr_soft->bs_last_slot = 2; + pcibr_soft->bs_last_reset = 2; + break; + + case MODULE_IBRICK: + /* + * Here's the current baseio layout for SN1 style systems: + * + * 0 1 2 3 4 5 6 7 slot# + * + * x scsi x x ioc3 usb x x O300 Ibrick + * + * x == never occupied + * E == external (add-in) slot + * + */ + pcibr_soft->bs_first_slot = 1; /* Ibrick first slot == 1 */ + if (pcibr_soft->bs_xid == 0xe) { + pcibr_soft->bs_last_slot = 2; + pcibr_soft->bs_last_reset = 2; + } else { + pcibr_soft->bs_last_slot = 6; + } + break; + default: + break; + } + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATTACH, pcibr_vhdl, + "pcibr_attach2: %cbrick, slots %d-%d\n", + MODULE_GET_BTCHAR(pcibr_soft->bs_moduleid), + pcibr_soft->bs_first_slot, pcibr_soft->bs_last_slot)); + } /* + * Initialize bridge and bus locks + */ + spin_lock_init(&pcibr_soft->bs_lock); +#ifdef PIC_LATER + mrinit(pcibr_soft->bs_bus_lock, "bus_lock"); +#endif + /* * If we have one, process the hints structure. */ if (pcibr_hints) { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_HINTS, pcibr_vhdl, + "pcibr_attach2: pcibr_hints=0x%x\n", pcibr_hints)); + rrb_fixed = pcibr_hints->ph_rrb_fixed; pcibr_soft->bs_rrb_fixed = rrb_fixed; - if (pcibr_hints->ph_intr_bits) + if (pcibr_hints->ph_intr_bits) { pcibr_soft->bs_intr_bits = pcibr_hints->ph_intr_bits; + } - for (slot = 0; slot < 8; ++slot) { - int hslot = pcibr_hints->ph_host_slot[slot] - 1; + for (slot = pcibr_soft->bs_min_slot; + slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) { + int hslot = pcibr_hints->ph_host_slot[slot] - 1; if (hslot < 0) { pcibr_soft->bs_slot[slot].host_slot = slot; @@ -1507,13 +1456,16 @@ } } /* - * set up initial values for state fields + * Set-up initial values for state fields */ - for (slot = 0; slot < 8; ++slot) { + for (slot = pcibr_soft->bs_min_slot; + slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) { pcibr_soft->bs_slot[slot].bss_devio.bssd_space = PCIIO_SPACE_NONE; + pcibr_soft->bs_slot[slot].bss_devio.bssd_ref_cnt = 0; pcibr_soft->bs_slot[slot].bss_d64_base = PCIBR_D64_BASE_UNSET; pcibr_soft->bs_slot[slot].bss_d32_base = PCIBR_D32_BASE_UNSET; pcibr_soft->bs_slot[slot].bss_ext_ates_active = ATOMIC_INIT(0); + pcibr_soft->bs_rrb_valid_dflt[slot][VCHAN0] = -1; } for (ibit = 0; ibit < 8; ++ibit) { @@ -1522,15 +1474,31 @@ pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_list = NULL; pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_stat = &(bridge->b_int_status); + pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_ibit = ibit; pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_hdlrcnt = 0; pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_shared = 0; pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_connected = 0; } /* + * connect up our error handler. PIC has 2 busses (thus resulting in 2 + * pcibr_soft structs under 1 widget), so only register a xwidget error + * handler for PIC's bus0. NOTE: for PIC pcibr_error_handler_wrapper() + * is a wrapper routine we register that will call the real error handler + * pcibr_error_handler() with the correct pcibr_soft struct. + */ + if (IS_PIC_SOFT(pcibr_soft)) { + if (busnum == 0) { + xwidget_error_register(xconn_vhdl, pcibr_error_handler_wrapper, pcibr_soft); + } + } else { + xwidget_error_register(xconn_vhdl, pcibr_error_handler, pcibr_soft); + } + + /* * Initialize various Bridge registers. */ - + /* * On pre-Rev.D bridges, set the PCI_RETRY_CNT * to zero to avoid dropping stores. (#475347) @@ -1543,12 +1511,43 @@ */ bridge->b_int_rst_stat = (BRIDGE_IRR_ALL_CLR); + /* Initialize some PIC specific registers. */ + if (IS_PIC_SOFT(pcibr_soft)) { + picreg_t pic_ctrl_reg = bridge->p_wid_control_64; + + /* Bridges Requester ID: bus = busnum, dev = 0, func = 0 */ + pic_ctrl_reg &= ~PIC_CTRL_BUS_NUM_MASK; + pic_ctrl_reg |= PIC_CTRL_BUS_NUM(busnum); + pic_ctrl_reg &= ~PIC_CTRL_DEV_NUM_MASK; + pic_ctrl_reg &= ~PIC_CTRL_FUN_NUM_MASK; + + pic_ctrl_reg &= ~PIC_CTRL_NO_SNOOP; + pic_ctrl_reg &= ~PIC_CTRL_RELAX_ORDER; + + /* enable parity checking on PICs internal RAM */ + pic_ctrl_reg |= PIC_CTRL_PAR_EN_RESP; + pic_ctrl_reg |= PIC_CTRL_PAR_EN_ATE; + /* PIC BRINGUP WAR (PV# 862253): dont enable write request + * parity checking. + */ + if (!PCIBR_WAR_ENABLED(PV862253, pcibr_soft)) { + pic_ctrl_reg |= PIC_CTRL_PAR_EN_REQ; + } + + bridge->p_wid_control_64 = pic_ctrl_reg; + } + /* * Until otherwise set up, * assume all interrupts are - * from slot 7. + * from slot 7(Bridge/Xbridge) or 3(PIC). + * XXX. Not sure why we're doing this, made change for PIC + * just to avoid setting reserved bits. */ - bridge->b_int_device = (uint32_t) 0xffffffff; + if (IS_PIC_SOFT(pcibr_soft)) + bridge->b_int_device = (uint32_t) 0x006db6db; + else + bridge->b_int_device = (uint32_t) 0xffffffff; { bridgereg_t dirmap; @@ -1560,6 +1559,11 @@ int entry; cnodeid_t cnodeid; nasid_t nasid; +#ifdef PIC_LATER + char *node_val; + devfs_handle_t node_vhdl; + char vname[MAXDEVNAME]; +#endif /* Set the Bridge's 32-bit PCI to XTalk * Direct Map register to the most useful @@ -1578,6 +1582,30 @@ */ cnodeid = 0; /* default node id */ + /* + * Determine the base address node id to be used for all 32-bit + * Direct Mapping I/O. The default is node 0, but this can be changed + * via a DEVICE_ADMIN directive and the PCIBUS_DMATRANS_NODE + * attribute in the irix.sm config file. A device driver can obtain + * this node value via a call to pcibr_get_dmatrans_node(). + */ +#ifdef PIC_LATER +// This probably needs to be addressed - pfg + node_val = device_admin_info_get(pcibr_vhdl, ADMIN_LBL_DMATRANS_NODE); + if (node_val != NULL) { + node_vhdl = hwgraph_path_to_vertex(node_val); + if (node_vhdl != GRAPH_VERTEX_NONE) { + cnodeid = nodevertex_to_cnodeid(node_vhdl); + } + if ((node_vhdl == GRAPH_VERTEX_NONE) || (cnodeid == CNODEID_NONE)) { + cnodeid = 0; + vertex_to_name(pcibr_vhdl, vname, sizeof(vname)); + printk(KERN_WARNING "Invalid hwgraph node path specified:\n" + " DEVICE_ADMIN: %s %s=%s\n", + vname, ADMIN_LBL_DMATRANS_NODE, node_val); + } + } +#endif /* PIC_LATER */ nasid = COMPACT_TO_NASID_NODEID(cnodeid); paddr = NODE_OFFSET(nasid) + 0; @@ -1619,9 +1647,17 @@ */ spl_level = splhi(); #if IOPGSIZE == 4096 - bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE; + if (IS_PIC_SOFT(pcibr_soft)) { + bridge->p_wid_control_64 &= ~BRIDGE_CTRL_PAGE_SIZE; + } else { + bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE; + } #elif IOPGSIZE == 16384 - bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE; + if (IS_PIC_SOFT(pcibr_soft)) { + bridge->p_wid_control_64 |= BRIDGE_CTRL_PAGE_SIZE; + } else { + bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE; + } #else <<>>; #endif @@ -1652,7 +1688,8 @@ * recomparing against BRIDGE_INTERNAL_ATES every * time. */ - if (is_xbridge(bridge)) + + if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) num_entries = 0; else num_entries = pcibr_init_ext_ate_ram(bridge); @@ -1662,9 +1699,6 @@ */ pcibr_soft->bs_int_ate_map = rmallocmap(pcibr_soft->bs_int_ate_size); pcibr_ate_free(pcibr_soft, 0, pcibr_soft->bs_int_ate_size); -#if PCIBR_ATE_DEBUG - printk("pcibr_attach: %d INTERNAL ATEs\n", pcibr_soft->bs_int_ate_size); -#endif if (num_entries > pcibr_soft->bs_int_ate_size) { #if PCIBR_ATE_NOTBOTH /* for debug -- forces us to use external ates */ @@ -1674,11 +1708,12 @@ pcibr_soft->bs_ext_ate_map = rmallocmap(num_entries); pcibr_ate_free(pcibr_soft, pcibr_soft->bs_int_ate_size, num_entries - pcibr_soft->bs_int_ate_size); -#if PCIBR_ATE_DEBUG - printk("pcibr_attach: %d EXTERNAL ATEs\n", - num_entries - pcibr_soft->bs_int_ate_size); -#endif } + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATE, pcibr_vhdl, + "pcibr_attach2: %d ATEs, %d internal & %d external\n", + num_entries ? num_entries : pcibr_soft->bs_int_ate_size, + pcibr_soft->bs_int_ate_size, + num_entries ? num_entries-pcibr_soft->bs_int_ate_size : 0)); } { @@ -1727,7 +1762,7 @@ * knows to do this. */ - xtalk_intr = xtalk_intr_alloc(xconn_vhdl, dev_desc, pcibr_vhdl); + xtalk_intr = xtalk_intr_alloc(xconn_vhdl, (device_desc_t)0, pcibr_vhdl); ASSERT(xtalk_intr != NULL); pcibr_soft->bsi_err_intr = xtalk_intr; @@ -1740,17 +1775,124 @@ */ pcibr_clearwidint(bridge); - xtalk_intr_connect(xtalk_intr, (xtalk_intr_setfunc_t)pcibr_setwidint, (void *)bridge); + xtalk_intr_connect(xtalk_intr, (intr_func_t) pcibr_error_intr_handler, + (intr_arg_t) pcibr_soft, (xtalk_intr_setfunc_t)pcibr_setwidint, (void *)bridge); + +#ifdef BUS_INT_WAR_NOT_YET + request_irq(CPU_VECTOR_TO_IRQ(((hub_intr_t)xtalk_intr)->i_cpuid, + ((hub_intr_t)xtalk_intr)->i_bit), + (intr_func_t)pcibr_error_intr_handler, 0, "PCIBR error", + (intr_arg_t) pcibr_soft); +#endif + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pcibr_vhdl, + "pcibr_setwidint: b_wid_int_upper=0x%x, b_wid_int_lower=0x%x\n", + bridge->b_wid_int_upper, bridge->b_wid_int_lower)); /* * now we can start handling error interrupts; * enable all of them. * NOTE: some PCI ints may already be enabled. */ - b_int_enable = bridge->b_int_enable | BRIDGE_ISR_ERRORS; + /* We read the INT_ENABLE register as a 64bit picreg_t for PIC and a + * 32bit bridgereg_t for BRIDGE, but always process the result as a + * 64bit value so the code can be "common" for both PIC and BRIDGE... + */ + if (IS_PIC_SOFT(pcibr_soft)) { + int_enable_64 = bridge->p_int_enable_64 | BRIDGE_ISR_ERRORS; + int_enable = (uint64_t)int_enable_64; + } else { + int_enable_32 = bridge->b_int_enable | (BRIDGE_ISR_ERRORS & 0xffffffff); + int_enable = ((uint64_t)int_enable_32 & 0xffffffff); + } +#ifdef BUS_INT_WAR_NOT_YET + { + extern void sn_add_polled_interrupt(int irq, int interval); + + sn_add_polled_interrupt(CPU_VECTOR_TO_IRQ(((hub_intr_t)xtalk_intr)->i_cpuid, + ((hub_intr_t)xtalk_intr)->i_bit), 20000); + } +#endif + + +#if BRIDGE_ERROR_INTR_WAR + if (pcibr_soft->bs_rev_num == BRIDGE_PART_REV_A) { + /* + * We commonly get master timeouts when talking to ql. + * We also see RESP_XTALK_ERROR and LLP_TX_RETRY interrupts. + * Insure that these are all disabled for now. + */ + int_enable &= ~(BRIDGE_IMR_PCI_MST_TIMEOUT | + BRIDGE_ISR_RESP_XTLK_ERR | + BRIDGE_ISR_LLP_TX_RETRY); + } + if (pcibr_soft->bs_rev_num < BRIDGE_PART_REV_C) { + int_enable &= ~BRIDGE_ISR_BAD_XRESP_PKT; + } +#endif /* BRIDGE_ERROR_INTR_WAR */ + +#ifdef QL_SCSI_CTRL_WAR /* for IP30 only */ + /* Really a QL rev A issue, but all newer hearts have newer QLs. + * Forces all IO6/MSCSI to be new. + */ + if (heart_rev() == HEART_REV_A) + int_enable &= ~BRIDGE_IMR_PCI_MST_TIMEOUT; +#endif + +#ifdef BRIDGE1_TIMEOUT_WAR + if (pcibr_soft->bs_rev_num == BRIDGE_PART_REV_A) { + /* + * Turn off these interrupts. They can't be trusted in bridge 1 + */ + int_enable &= ~(BRIDGE_IMR_XREAD_REQ_TIMEOUT | + BRIDGE_IMR_UNEXP_RESP); + } +#endif + +#ifdef BRIDGE_B_DATACORR_WAR + + /* WAR panic for Rev B silent data corruption. + * PIOERR turned off here because there is a problem + * with not re-arming it in pcibr_error_intr_handler. + * We don't get LLP error interrupts if we don't + * re-arm PIOERR interrupts! Just disable them here + */ + + if (pcibr_soft->bs_rev_num == BRIDGE_PART_REV_B) { + int_enable |= BRIDGE_IMR_LLP_REC_CBERR; + int_enable &= ~BRIDGE_ISR_PCIBUS_PIOERR; + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATTACH, pcibr_vhdl, + "Turning on LLP_REC_CBERR for Rev B Bridge.\n")); + } +#endif - bridge->b_int_enable = b_int_enable; + /* PIC BRINGUP WAR (PV# 856864 & 856865): allow the tnums that are + * locked out to be freed up sooner (by timing out) so that the + * read tnums are never completely used up. + */ + if (IS_PIC_SOFT(pcibr_soft) && PCIBR_WAR_ENABLED(PV856864, pcibr_soft)) { + int_enable &= ~PIC_ISR_PCIX_REQ_TOUT; + int_enable &= ~BRIDGE_ISR_XREAD_REQ_TIMEOUT; + + bridge->b_wid_req_timeout = 0x750; + } + + /* + * PIC BRINGUP WAR (PV# 856866, 859504, 861476, 861478): Don't use + * RRB0, RRB8, RRB1, and RRB9. Assign them to DEVICE[2|3]--VCHAN3 + * so they are not used + */ + if (IS_PIC_SOFT(pcibr_soft) && PCIBR_WAR_ENABLED(PV856866, pcibr_soft)) { + bridge->b_even_resp |= 0x000f000f; + bridge->b_odd_resp |= 0x000f000f; + } + + if (IS_PIC_SOFT(pcibr_soft)) { + bridge->p_int_enable_64 = (picreg_t)int_enable; + } else { + bridge->b_int_enable = (bridgereg_t)int_enable; + } bridge->b_int_mode = 0; /* do not send "clear interrupt" packets */ bridge->b_wid_tflush; /* wait until Bridge PIO complete */ @@ -1788,20 +1930,59 @@ (BRIDGE_WIDGET_PART_NUM << 4 | pcibr_wg_enable_rev)) pcibr_soft->bs_dma_flags |= PCIBR_NOWRITE_GATHER; - pciio_provider_register(pcibr_vhdl, &pcibr_provider); - pciio_provider_startup(pcibr_vhdl); - - pci_io_fb = 0x00000004; /* I/O FreeBlock Base */ - pci_io_fl = 0xFFFFFFFF; /* I/O FreeBlock Last */ - - pci_lo_fb = 0x00000010; /* Low Memory FreeBlock Base */ - pci_lo_fl = 0x001FFFFF; /* Low Memory FreeBlock Last */ + /* PIC only supports 64-bit direct mapping in PCI-X mode. Since + * all PCI-X devices that initiate memory transactions must be + * capable of generating 64-bit addressed, we force 64-bit DMAs. + */ + if (IS_PCIX(pcibr_soft)) { + pcibr_soft->bs_dma_flags |= PCIIO_DMA_A64; + } - pci_hi_fb = 0x00200000; /* High Memory FreeBlock Base */ - pci_hi_fl = 0x3FFFFFFF; /* High Memory FreeBlock Last */ + { + pciio_win_map_t win_map_p; + iopaddr_t prom_base_addr = pcibr_soft->bs_xid << 24; + int prom_base_size = 0x1000000; + iopaddr_t prom_base_limit = prom_base_addr + prom_base_size; + + /* Allocate resource maps based on bus page size; for I/O and memory + * space, free all pages except those in the base area and in the + * range set by the PROM. + * + * PROM creates BAR addresses in this format: 0x0ws00000 where w is + * the widget number and s is the device register offset for the slot. + */ - PCI_ADDR_SPACE_LIMITS_STORE(); + win_map_p = &pcibr_soft->bs_io_win_map; + pciio_device_win_map_new(win_map_p, + PCIBR_BUS_IO_MAX + 1, + PCIBR_BUS_IO_PAGE); + pciio_device_win_populate(win_map_p, + PCIBR_BUS_IO_BASE, + prom_base_addr - PCIBR_BUS_IO_BASE); + pciio_device_win_populate(win_map_p, + prom_base_limit, + (PCIBR_BUS_IO_MAX + 1) - prom_base_limit); + + win_map_p = &pcibr_soft->bs_swin_map; + pciio_device_win_map_new(win_map_p, + PCIBR_BUS_SWIN_MAX + 1, + PCIBR_BUS_SWIN_PAGE); + pciio_device_win_populate(win_map_p, + PCIBR_BUS_SWIN_BASE, + (PCIBR_BUS_SWIN_MAX + 1) - PCIBR_BUS_SWIN_PAGE); + + win_map_p = &pcibr_soft->bs_mem_win_map; + pciio_device_win_map_new(win_map_p, + PCIBR_BUS_MEM_MAX + 1, + PCIBR_BUS_MEM_PAGE); + pciio_device_win_populate(win_map_p, + PCIBR_BUS_MEM_BASE, + prom_base_addr - PCIBR_BUS_MEM_BASE); + pciio_device_win_populate(win_map_p, + prom_base_limit, + (PCIBR_BUS_MEM_MAX + 1) - prom_base_limit); + } /* build "no-slot" connection point */ @@ -1830,59 +2011,91 @@ } #endif -#ifdef LATER - /* If the bridge has been reset then there is no need to reset - * the individual PCI slots. - */ - for (slot = 0; slot < 8; ++slot) - /* Reset all the slots */ - (void)pcibr_slot_reset(pcibr_vhdl, slot); -#endif - - for (slot = 0; slot < 8; ++slot) + for (slot = pcibr_soft->bs_min_slot; + slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) { /* Find out what is out there */ (void)pcibr_slot_info_init(pcibr_vhdl,slot); + } + for (slot = pcibr_soft->bs_min_slot; + slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) + /* Set up the address space for this slot in the PCI land */ + (void)pcibr_slot_addr_space_init(pcibr_vhdl, slot); - for (slot = 0; slot < 8; ++slot) - /* Set up the address space for this slot in the pci land */ - (void)pcibr_slot_addr_space_init(pcibr_vhdl,slot); - - for (slot = 0; slot < 8; ++slot) + for (slot = pcibr_soft->bs_min_slot; + slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) /* Setup the device register */ (void)pcibr_slot_device_init(pcibr_vhdl, slot); - for (slot = 0; slot < 8; ++slot) - /* Setup host/guest relations */ - (void)pcibr_slot_guest_info_init(pcibr_vhdl,slot); - - for (slot = 0; slot < 8; ++slot) - /* Initial RRB management */ - (void)pcibr_slot_initial_rrb_alloc(pcibr_vhdl,slot); + if (IS_PCIX(pcibr_soft)) { + pcibr_soft->bs_pcix_rbar_inuse = 0; + pcibr_soft->bs_pcix_rbar_avail = NUM_RBAR; + pcibr_soft->bs_pcix_rbar_percent_allowed = + pcibr_pcix_rbars_calc(pcibr_soft); + + for (slot = pcibr_soft->bs_min_slot; + slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) + /* Setup the PCI-X Read Buffer Attribute Registers (RBARs) */ + (void)pcibr_slot_pcix_rbar_init(pcibr_soft, slot); + } + + /* Set up convenience links */ + if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) + pcibr_bus_cnvlink(pcibr_soft->bs_vhdl); - /* driver attach routines should be called out from generic linux code */ - for (slot = 0; slot < 8; ++slot) - /* Call the device attach */ - (void)pcibr_slot_call_device_attach(pcibr_vhdl, slot, 0); + for (slot = pcibr_soft->bs_min_slot; + slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) + /* Setup host/guest relations */ + (void)pcibr_slot_guest_info_init(pcibr_vhdl, slot); + /* Handle initial RRB management for Bridge and Xbridge */ + pcibr_initial_rrb(pcibr_vhdl, + pcibr_soft->bs_first_slot, pcibr_soft->bs_last_slot); + +{ /* Before any drivers get called that may want to re-allocate + * RRB's, let's get some special cases pre-allocated. Drivers + * may override these pre-allocations, but by doing pre-allocations + * now we're assured not to step all over what the driver intended. + * + * Note: Someday this should probably be moved over to pcibr_rrb.c + */ /* * Each Pbrick PCI bus only has slots 1 and 2. Similarly for * widget 0xe on Ibricks. Allocate RRB's accordingly. */ - if (pcibr_soft->bs_moduleid > 0) { - switch (MODULE_GET_BTCHAR(pcibr_soft->bs_moduleid)) { - case 'p': /* Pbrick */ - do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8); - do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8); + if (pcibr_soft->bs_bricktype > 0) { + switch (pcibr_soft->bs_bricktype) { + case MODULE_PXBRICK: + /* + * If the IO9 is in the PXBrick (bus1, slot1) allocate + * RRBs to all the devices + */ + if ((pcibr_widget_to_bus(pcibr_vhdl) == 1) && + (pcibr_soft->bs_slot[0].bss_vendor_id == 0x10A9) && + (pcibr_soft->bs_slot[0].bss_device_id == 0x100A)) { + do_pcibr_rrb_autoalloc(pcibr_soft, 0, VCHAN0, 4); + do_pcibr_rrb_autoalloc(pcibr_soft, 1, VCHAN0, 4); + do_pcibr_rrb_autoalloc(pcibr_soft, 2, VCHAN0, 4); + do_pcibr_rrb_autoalloc(pcibr_soft, 3, VCHAN0, 4); + } else { + do_pcibr_rrb_autoalloc(pcibr_soft, 0, VCHAN0, 8); + do_pcibr_rrb_autoalloc(pcibr_soft, 1, VCHAN0, 8); + } + break; - case 'i': /* Ibrick */ + case MODULE_PEBRICK: + case MODULE_PBRICK: + do_pcibr_rrb_autoalloc(pcibr_soft, 1, VCHAN0, 8); + do_pcibr_rrb_autoalloc(pcibr_soft, 2, VCHAN0, 8); + break; + case MODULE_IBRICK: /* port 0xe on the Ibrick only has slots 1 and 2 */ if (pcibr_soft->bs_xid == 0xe) { - do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8); - do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8); + do_pcibr_rrb_autoalloc(pcibr_soft, 1, VCHAN0, 8); + do_pcibr_rrb_autoalloc(pcibr_soft, 2, VCHAN0, 8); } else { /* allocate one RRB for the serial port */ - do_pcibr_rrb_autoalloc(pcibr_soft, 0, 1); + do_pcibr_rrb_autoalloc(pcibr_soft, 0, VCHAN0, 1); } break; } /* switch */ @@ -1890,33 +2103,80 @@ #ifdef LATER if (strstr(nicinfo, XTALK_PCI_PART_NUM)) { - do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8); -#if PCIBR_RRB_DEBUG - printf("\n\nFound XTALK_PCI (030-1275) at %v\n", xconn_vhdl); - - printf("pcibr_attach: %v Shoebox RRB MANAGEMENT: %d+%d free\n", - pcibr_vhdl, - pcibr_soft->bs_rrb_avail[0], - pcibr_soft->bs_rrb_avail[1]); - - for (slot = 0; slot < 8; ++slot) - printf("\t%d+%d+%d", - 0xFFF & pcibr_soft->bs_rrb_valid[slot], - 0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL], - pcibr_soft->bs_rrb_res[slot]); - - printf("\n"); + do_pcibr_rrb_autoalloc(pcibr_soft, 1, VCHAN0, 8); + } #endif +} /* OK Special RRB allocations are done. */ + + for (slot = pcibr_soft->bs_min_slot; + slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) + /* Call the device attach */ + (void)pcibr_slot_call_device_attach(pcibr_vhdl, slot, 0); + +#ifdef PIC_LATER +#if (defined(USS302_TIMEOUT_WAR)) + /* + * If this bridge holds a Lucent USS-302 or USS-312 pci/usb controller, + * increase the Bridge PCI retry backoff interval. This part seems + * to go away for long periods of time if a DAC appears on the bus during + * a read command that is being retried. + */ + +{ + ii_ixtt_u_t ixtt; + + for (slot = pcibr_soft->bs_min_slot; + slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) { + if (pcibr_soft->bs_slot[slot].bss_vendor_id == + LUCENT_USBHC_VENDOR_ID_NUM && + (pcibr_soft->bs_slot[slot].bss_device_id == + LUCENT_USBHC302_DEVICE_ID_NUM || + pcibr_soft->bs_slot[slot].bss_device_id == + LUCENT_USBHC312_DEVICE_ID_NUM)) { + printk(KERN_NOTICE + "pcibr_attach: %x Bus holds a usb part - setting" + "bridge PCI_RETRY_HLD to %d\n", + pcibr_vhdl, USS302_BRIDGE_TIMEOUT_HLD); + + bridge->b_bus_timeout &= ~BRIDGE_BUS_PCI_RETRY_HLD_MASK; + bridge->b_bus_timeout |= + BRIDGE_BUS_PCI_RETRY_HLD(USS302_BRIDGE_TIMEOUT_HLD); + + /* + * Have to consider the read response timer in the hub II as well + */ + + hubii_ixtt_get(xconn_vhdl, &ixtt); + + /* + * bump rrsp_ps to allow at least 1ms for read + * responses from this widget + */ + + ixtt.ii_ixtt_fld_s.i_rrsp_ps = 20000; + hubii_ixtt_set(xconn_vhdl, &ixtt); + + /* + * print the current setting + */ + + hubii_ixtt_get(xconn_vhdl, &ixtt); + printk( "Setting hub ixtt.rrsp_ps field to 0x%x\n", + ixtt.ii_ixtt_fld_s.i_rrsp_ps); + + break; /* only need to do it once */ + } } +} +#endif /* (defined(USS302_TIMEOUT_WAR)) */ #else FIXME("pcibr_attach: Call do_pcibr_rrb_autoalloc nicinfo\n"); -#endif +#endif /* PIC_LATER */ if (aa) async_attach_add_info(noslot_conn, aa); - pciio_device_attach(noslot_conn, 0); - + pciio_device_attach(noslot_conn, (int)0); /* * Tear down pointer to async attach info -- async threads for @@ -1927,11 +2187,13 @@ return 0; } + /* * pcibr_detach: * Detach the bridge device from the hwgraph after cleaning out all the * underlying vertices. */ + int pcibr_detach(devfs_handle_t xconn) { @@ -1939,6 +2201,9 @@ devfs_handle_t pcibr_vhdl; pcibr_soft_t pcibr_soft; bridge_t *bridge; + unsigned s; + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DETACH, xconn, "pcibr_detach\n")); /* Get the bridge vertex from its xtalk connection point */ if (hwgraph_traverse(xconn, EDGE_LBL_PCI, &pcibr_vhdl) != GRAPH_SUCCESS) @@ -1947,16 +2212,20 @@ pcibr_soft = pcibr_soft_get(pcibr_vhdl); bridge = pcibr_soft->bs_base; + + s = pcibr_lock(pcibr_soft); /* Disable the interrupts from the bridge */ - bridge->b_int_enable = 0; + if (IS_PIC_SOFT(pcibr_soft)) { + bridge->p_int_enable_64 = 0; + } else { + bridge->b_int_enable = 0; + } + pcibr_unlock(pcibr_soft, s); /* Detach all the PCI devices talking to this bridge */ - for(slot = 0; slot < 8; slot++) { -#ifdef DEBUG - printk("pcibr_device_detach called for %p/%d\n", - pcibr_vhdl,slot); -#endif - pcibr_slot_detach(pcibr_vhdl, slot, 0); + for (slot = pcibr_soft->bs_min_slot; + slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) { + pcibr_slot_detach(pcibr_vhdl, slot, 0, (char *)NULL, (int *)NULL); } /* Unregister the no-slot connection point */ @@ -1998,17 +2267,29 @@ int pcibr_asic_rev(devfs_handle_t pconn_vhdl) { - devfs_handle_t pcibr_vhdl; + devfs_handle_t pcibr_vhdl; + int tmp_vhdl; arbitrary_info_t ainfo; if (GRAPH_SUCCESS != hwgraph_traverse(pconn_vhdl, EDGE_LBL_MASTER, &pcibr_vhdl)) return -1; - if (GRAPH_SUCCESS != - hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &ainfo)) - return -1; + tmp_vhdl = hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &ainfo); + /* + * Any hwgraph function that returns a vertex handle will implicity + * increment that vertex's reference count. The caller must explicity + * decrement the vertex's referece count after the last reference to + * that vertex. + * + * Decrement reference count incremented by call to hwgraph_traverse(). + * + */ + hwgraph_vertex_unref(pcibr_vhdl); + + if (tmp_vhdl != GRAPH_SUCCESS) + return -1; return (int) ainfo; } @@ -2018,7 +2299,7 @@ pciio_info_t pciio_info = pciio_info_get(pconn_vhdl); pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info); pciio_slot_t slot; - slot = pciio_info_slot_get(pciio_info); + slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_device_write_gather_flush(pcibr_soft, slot); return 0; } @@ -2048,11 +2329,13 @@ size_t wsize; /* size of device decode on PCI */ int try; /* DevIO(x) window scanning order control */ + int maxtry, halftry; int win; /* which DevIO(x) window is being used */ pciio_space_t mspace; /* target space for devio(x) register */ iopaddr_t mbase; /* base of devio(x) mapped area on PCI */ size_t msize; /* size of devio(x) mapped area on PCI */ size_t mmask; /* addr bits stored in Device(x) */ + char tmp_str[512]; unsigned long s; @@ -2061,6 +2344,17 @@ if (pcibr_soft->bs_slot[slot].has_host) { slot = pcibr_soft->bs_slot[slot].host_slot; pcibr_info = pcibr_soft->bs_slot[slot].bss_infos[0]; + + /* + * Special case for dual-slot pci devices such as ioc3 on IP27 + * baseio. In these cases, pconn_vhdl should never be for a pci + * function on a subordiate PCI bus, so we can safely reset pciio_info + * to be the info struct embedded in pcibr_info. Failure to do this + * results in using a bogus pciio_info_t for calculations done later + * in this routine. + */ + + pciio_info = &pcibr_info->f_c; } if (space == PCIIO_SPACE_NONE) goto done; @@ -2080,7 +2374,7 @@ */ if (((flags & PCIIO_BYTE_STREAM) == 0) && ((pci_addr + req_size) <= BRIDGE_TYPE0_CFG_FUNC_OFF)) - xio_addr = pci_addr + BRIDGE_TYPE0_CFG_DEV(slot); + xio_addr = pci_addr + PCIBR_TYPE0_CFG_DEV(pcibr_soft, slot); goto done; } @@ -2090,8 +2384,8 @@ * enabling and disabling * decodes properly. */ - wbase = pcibr_info->f_rbase; - wsize = pcibr_info->f_rsize; + wbase = pciio_info->c_rbase; + wsize = pciio_info->c_rsize; /* * While the driver should know better @@ -2113,13 +2407,13 @@ */ bar = space - PCIIO_SPACE_WIN0; if (bar < 6) { - wspace = pcibr_info->f_window[bar].w_space; + wspace = pciio_info->c_window[bar].w_space; if (wspace == PCIIO_SPACE_NONE) goto done; /* get PCI base and size */ - wbase = pcibr_info->f_window[bar].w_base; - wsize = pcibr_info->f_window[bar].w_size; + wbase = pciio_info->c_window[bar].w_base; + wsize = pciio_info->c_window[bar].w_size; /* * While the driver should know better @@ -2147,11 +2441,15 @@ * We will not attempt to satisfy a single request * by concatinating multiple windows. */ - for (try = 0; try < 16; ++try) { + maxtry = PCIBR_NUM_SLOTS(pcibr_soft) * 2; + halftry = PCIBR_NUM_SLOTS(pcibr_soft) - 1; + for (try = 0; try < maxtry; ++try) { bridgereg_t devreg; unsigned offset; - win = (try + slot) % 8; + /* calculate win based on slot, attempt, and max possible + devices on bus */ + win = (try + slot) % PCIBR_NUM_SLOTS(pcibr_soft); /* If this DevIO(x) mapping area can provide * a mapping to this address, use it. @@ -2176,7 +2474,7 @@ * (only check this the second time through) */ mspace = pcibr_soft->bs_slot[win].bss_devio.bssd_space; - if ((try > 7) && (mspace == PCIIO_SPACE_NONE)) { + if ((try > halftry) && (mspace == PCIIO_SPACE_NONE)) { /* If this is the primary DevIO(x) window * for some other device, skip it. @@ -2214,25 +2512,61 @@ devreg &= ~BRIDGE_DEV_DEV_SWAP; if (pcibr_soft->bs_slot[win].bss_device != devreg) { - bridge->b_device[win].reg = devreg; - pcibr_soft->bs_slot[win].bss_device = devreg; - bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + if ( IS_PIC_SOFT(pcibr_soft) ) { + bridge->b_device[win].reg = devreg; + pcibr_soft->bs_slot[win].bss_device = devreg; + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_SET32((&bridge->b_device[win].reg)) = __swab32(devreg); + pcibr_soft->bs_slot[win].bss_device = devreg; + BRIDGE_REG_GET32((&bridge->b_wid_tflush)); /* wait until Bridge PIO complete */ + } else { + bridge->b_device[win].reg = devreg; + pcibr_soft->bs_slot[win].bss_device = devreg; + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } + } -#if DEBUG && PCI_DEBUG - printk("pcibr Device(%d): 0x%lx\n", win, bridge->b_device[win].reg); +#ifdef PCI_LATER + PCIBR_DEBUG((PCIBR_DEBUG_DEVREG, pconn_vhdl, + "pcibr_addr_pci_to_xio: Device(%d): %x\n", + win, devreg, device_bits)); +#else + printk("pcibr_addr_pci_to_xio: Device(%d): %x\n", win, devreg); #endif } pcibr_soft->bs_slot[win].bss_devio.bssd_space = space; pcibr_soft->bs_slot[win].bss_devio.bssd_base = mbase; - xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase); + xio_addr = PCIBR_BRIDGE_DEVIO(pcibr_soft, win) + (pci_addr - mbase); -#if DEBUG && PCI_DEBUG - printk("%s LINE %d map to space %d space desc 0x%x[%lx..%lx] for slot %d allocates DevIO(%d) devreg 0x%x\n", - __FUNCTION__, __LINE__, space, space_desc, - pci_addr, pci_addr + req_size - 1, - slot, win, devreg); -#endif + /* Increment this DevIO's use count */ + pcibr_soft->bs_slot[win].bss_devio.bssd_ref_cnt++; + /* Save the DevIO register index used to access this BAR */ + if (bar != -1) + pcibr_info->f_window[bar].w_devio_index = win; + + /* + * The kernel only allows functions to have so many variable args, + * attempting to call PCIBR_DEBUG_ALWAYS() with more than 5 printk + * arguments fails so sprintf() it into a temporary string. + */ + if (pcibr_debug_mask & PCIBR_DEBUG_PIOMAP) { +#ifdef PIC_LATER + sprintf(tmp_str, "pcibr_addr_pci_to_xio: map to %x[%x..%x] for " + "slot %d allocates DevIO(%d) Device(%d) set to %x\n", + space, space_desc, pci_addr, pci_addr + req_size - 1, + slot, win, win, devreg, device_bits); +#else + sprintf(tmp_str, "pcibr_addr_pci_to_xio: map to [%lx..%lx] for " + "slot %d allocates DevIO(%d) Device(%d) set to %lx\n", + (unsigned long)pci_addr, (unsigned long)(pci_addr + req_size - 1), + (unsigned int)slot, win, win, (unsigned long)devreg); +#endif + PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl, "%s", tmp_str)); + } goto done; } /* endif DevIO(x) not pointed */ mbase = pcibr_soft->bs_slot[win].bss_devio.bssd_base; @@ -2251,12 +2585,23 @@ * final XIO address, release the lock and * return. */ - xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase); + xio_addr = PCIBR_BRIDGE_DEVIO(pcibr_soft, win) + (pci_addr - mbase); + + /* Increment this DevIO's use count */ + pcibr_soft->bs_slot[win].bss_devio.bssd_ref_cnt++; -#if DEBUG && PCI_DEBUG - printk("%s LINE %d map to space %d [0x%p..0x%p] for slot %d uses DevIO(%d)\n", - __FUNCTION__, __LINE__, space, pci_addr, pci_addr + req_size - 1, slot, win); + /* Save the DevIO register index used to access this BAR */ + if (bar != -1) + pcibr_info->f_window[bar].w_devio_index = win; + + if (pcibr_debug_mask & PCIBR_DEBUG_PIOMAP) { +#ifdef PIC_LATER + sprintf(tmp_str, "pcibr_addr_pci_to_xio: map to %x[%x..%x] for " + "slot %d uses DevIO(%d)\n", space, space_desc, pci_addr, + pci_addr + req_size - 1, slot, win); #endif + PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl, "%s", tmp_str)); + } goto done; } @@ -2322,33 +2667,55 @@ if (bfn == bfo) { /* we already match. */ ; } else if (bfo != 0) { /* we have a conflict. */ -#if DEBUG && PCI_DEBUG - printk("pcibr_addr_pci_to_xio: swap conflict in space %d , was%s%s, want%s%s\n", - space, - bfo & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "", - bfo & PCIIO_WORD_VALUES ? " WORD_VALUES" : "", - bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "", - bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : ""); + if (pcibr_debug_mask & PCIBR_DEBUG_PIOMAP) { +#ifdef PIC_LATER + sprintf(tmp_str, "pcibr_addr_pci_to_xio: swap conflict in %x, " + "was%s%s, want%s%s\n", space, space_desc, + bfo & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "", + bfo & PCIIO_WORD_VALUES ? " WORD_VALUES" : "", + bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "", + bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : ""); #endif + PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl, "%s", tmp_str)); + } xio_addr = XIO_NOWHERE; } else { /* OK to make the change. */ - bridgereg_t octl, nctl; - swb = (space == PCIIO_SPACE_IO) ? BRIDGE_CTRL_IO_SWAP : BRIDGE_CTRL_MEM_SWAP; - octl = bridge->b_wid_control; - nctl = bst ? octl | swb : octl & ~swb; + if ( IS_PIC_SOFT(pcibr_soft) ) { + picreg_t octl, nctl; + octl = bridge->p_wid_control_64; + nctl = bst ? octl | (uint64_t)swb : octl & ((uint64_t)~swb); - if (octl != nctl) /* make the change if any */ - bridge->b_wid_control = nctl; + if (octl != nctl) /* make the change if any */ + bridge->b_wid_control = nctl; + } + else { + picreg_t octl, nctl; + if (io_get_sh_swapper(NASID_GET(bridge))) { + octl = BRIDGE_REG_GET32((&bridge->b_wid_control)); + nctl = bst ? octl | swb : octl & ~swb; + + if (octl != nctl) /* make the change if any */ + BRIDGE_REG_SET32((&bridge->b_wid_control)) = __swab32(nctl); + } else { + octl = bridge->b_wid_control; + nctl = bst ? octl | swb : octl & ~swb; + if (octl != nctl) /* make the change if any */ + bridge->b_wid_control = nctl; + } + } *bfp = bfn; /* record the assignment */ -#if DEBUG && PCI_DEBUG - printk("pcibr_addr_pci_to_xio: swap for space %d set to%s%s\n", - space, - bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "", - bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : ""); + if (pcibr_debug_mask & PCIBR_DEBUG_PIOMAP) { +#ifdef PIC_LATER + sprintf(tmp_str, "pcibr_addr_pci_to_xio: swap for %x set " + "to%s%s\n", space, space_desc, + bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "", + bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : ""); #endif + PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl, "%s", tmp_str)); + } } } done: @@ -2368,7 +2735,7 @@ { pcibr_info_t pcibr_info = pcibr_info_get(pconn_vhdl); pciio_info_t pciio_info = &pcibr_info->f_c; - pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info); + pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info); devfs_handle_t xconn_vhdl = pcibr_soft->bs_conn; @@ -2380,8 +2747,11 @@ unsigned long s; /* Make sure that the req sizes are non-zero */ - if ((req_size < 1) || (req_size_max < 1)) + if ((req_size < 1) || (req_size_max < 1)) { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_PIOMAP, pconn_vhdl, + "pcibr_piomap_alloc: req_size | req_size_max < 1\n")); return NULL; + } /* * Code to translate slot/space/addr @@ -2390,8 +2760,11 @@ */ xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags); - if (xio_addr == XIO_NOWHERE) + if (xio_addr == XIO_NOWHERE) { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_PIOMAP, pconn_vhdl, + "pcibr_piomap_alloc: xio_addr == XIO_NOWHERE\n")); return NULL; + } /* Check the piomap list to see if there is already an allocated * piomap entry but not in use. If so use that one. Otherwise @@ -2415,7 +2788,7 @@ } pcibr_piomap->bp_dev = pconn_vhdl; - pcibr_piomap->bp_slot = pciio_slot; + pcibr_piomap->bp_slot = PCIBR_DEVICE_TO_SLOT(pcibr_soft, pciio_slot); pcibr_piomap->bp_flags = flags; pcibr_piomap->bp_space = space; pcibr_piomap->bp_pciaddr = pci_addr; @@ -2446,6 +2819,10 @@ pcibr_piomap = 0; } } + + PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl, + "pcibr_piomap_alloc: map=0x%x\n", pcibr_piomap)); + return pcibr_piomap; } @@ -2453,6 +2830,9 @@ void pcibr_piomap_free(pcibr_piomap_t pcibr_piomap) { + PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pcibr_piomap->bp_dev, + "pcibr_piomap_free: map=0x%x\n", pcibr_piomap)); + xtalk_piomap_free(pcibr_piomap->bp_xtalk_pio); pcibr_piomap->bp_xtalk_pio = 0; pcibr_piomap->bp_mapsz = 0; @@ -2464,16 +2844,24 @@ iopaddr_t pci_addr, size_t req_size) { - return xtalk_piomap_addr(pcibr_piomap->bp_xtalk_pio, + caddr_t addr; + addr = xtalk_piomap_addr(pcibr_piomap->bp_xtalk_pio, pcibr_piomap->bp_xtalk_addr + pci_addr - pcibr_piomap->bp_pciaddr, req_size); + PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pcibr_piomap->bp_dev, + "pcibr_piomap_free: map=0x%x, addr=0x%x\n", + pcibr_piomap, addr)); + + return(addr); } /*ARGSUSED */ void pcibr_piomap_done(pcibr_piomap_t pcibr_piomap) { + PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pcibr_piomap->bp_dev, + "pcibr_piomap_done: map=0x%x\n", pcibr_piomap)); xtalk_piomap_done(pcibr_piomap->bp_xtalk_pio); } @@ -2487,26 +2875,34 @@ unsigned flags) { pciio_info_t pciio_info = pciio_info_get(pconn_vhdl); - pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info); + pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info); devfs_handle_t xconn_vhdl = pcibr_soft->bs_conn; iopaddr_t xio_addr; + caddr_t addr; xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags); - if (xio_addr == XIO_NOWHERE) + if (xio_addr == XIO_NOWHERE) { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_PIODIR, pconn_vhdl, + "pcibr_piotrans_addr: xio_addr == XIO_NOWHERE\n")); return NULL; + } - return xtalk_piotrans_addr(xconn_vhdl, 0, xio_addr, req_size, flags & PIOMAP_FLAGS); + addr = xtalk_piotrans_addr(xconn_vhdl, 0, xio_addr, req_size, flags & PIOMAP_FLAGS); + PCIBR_DEBUG((PCIBR_DEBUG_PIODIR, pconn_vhdl, + "pcibr_piotrans_addr: xio_addr=0x%x, addr=0x%x\n", + xio_addr, addr)); + return(addr); } /* * PIO Space allocation and management. * Allocate and Manage the PCI PIO space (mem and io space) * This routine is pretty simplistic at this time, and - * does pretty trivial management of allocation and freeing.. - * The current scheme is prone for fragmentation.. + * does pretty trivial management of allocation and freeing. + * The current scheme is prone for fragmentation. * Change the scheme to use bitmaps. */ @@ -2525,7 +2921,6 @@ pciio_piospace_t piosp; unsigned long s; - iopaddr_t *pciaddr, *pcilast; iopaddr_t start_addr; size_t align_mask; @@ -2559,38 +2954,43 @@ } ASSERT(!piosp); + /* + * Allocate PCI bus address, usually for the Universe chip driver; + * do not pass window info since the actual PCI bus address + * space will never be freed. The space may be reused after it + * is logically released by pcibr_piospace_free(). + */ switch (space) { case PCIIO_SPACE_IO: - pciaddr = &pcibr_soft->bs_spinfo.pci_io_base; - pcilast = &pcibr_soft->bs_spinfo.pci_io_last; + start_addr = pcibr_bus_addr_alloc(pcibr_soft, NULL, + PCIIO_SPACE_IO, + 0, req_size, alignment); break; + case PCIIO_SPACE_MEM: case PCIIO_SPACE_MEM32: - pciaddr = &pcibr_soft->bs_spinfo.pci_mem_base; - pcilast = &pcibr_soft->bs_spinfo.pci_mem_last; + start_addr = pcibr_bus_addr_alloc(pcibr_soft, NULL, + PCIIO_SPACE_MEM32, + 0, req_size, alignment); break; + default: ASSERT(0); pcibr_unlock(pcibr_soft, s); + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_PIOMAP, pconn_vhdl, + "pcibr_piospace_alloc: unknown space %d\n", space)); return 0; } - start_addr = *pciaddr; - /* - * Align start_addr. + * If too big a request, reject it. */ - if (start_addr & align_mask) - start_addr = (start_addr + align_mask) & ~align_mask; - - if ((start_addr + req_size) > *pcilast) { - /* - * If too big a request, reject it. - */ + if (!start_addr) { pcibr_unlock(pcibr_soft, s); + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_PIOMAP, pconn_vhdl, + "pcibr_piospace_alloc: request 0x%x to big\n", req_size)); return 0; } - *pciaddr = (start_addr + req_size); NEW(piosp); piosp->free = 0; @@ -2601,6 +3001,10 @@ pcibr_info->f_piospace = piosp; pcibr_unlock(pcibr_soft, s); + + PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl, + "pcibr_piospace_alloc: piosp=0x%x\n", piosp)); + return start_addr; } @@ -2612,7 +3016,9 @@ size_t req_size) { pcibr_info_t pcibr_info = pcibr_info_get(pconn_vhdl); +#ifdef PIC_LATER pcibr_soft_t pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast; +#endif pciio_piospace_t piosp; unsigned long s; @@ -2655,6 +3061,9 @@ } piosp->free = 1; pcibr_unlock(pcibr_soft, s); + + PCIBR_DEBUG((PCIBR_DEBUG_PIOMAP, pconn_vhdl, + "pcibr_piospace_free: piosp=0x%x\n", piosp)); return; } @@ -2713,7 +3122,7 @@ attributes &= ~PCI64_ATTR_PREF; /* the swap bit is in the address attributes for xbridge */ - if (pcibr_soft->bs_xbridge) { + if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) { if (flags & PCIIO_BYTE_STREAM) attributes |= PCI64_ATTR_SWAP; if (flags & PCIIO_WORD_VALUES) @@ -2742,6 +3151,11 @@ if (flags & PCIBR_VCHAN0) attributes &= ~PCI64_ATTR_VIRTUAL; + /* PIC in PCI-X mode only supports barrier & swap */ + if (IS_PCIX(pcibr_soft)) { + attributes &= (PCI64_ATTR_BAR | PCI64_ATTR_SWAP); + } + return (attributes); } @@ -2762,6 +3176,7 @@ pcibr_dmamap_t pcibr_dmamap; int ate_count; int ate_index; + int vchan = VCHAN0; /* merge in forced flags */ flags |= pcibr_soft->bs_dma_flags; @@ -2778,17 +3193,16 @@ xtalk_dmamap = xtalk_dmamap_alloc(xconn_vhdl, dev_desc, req_size_max, flags & DMAMAP_FLAGS); if (!xtalk_dmamap) { -#if PCIBR_ATE_DEBUG - printk("pcibr_attach: xtalk_dmamap_alloc failed\n"); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMAMAP, pconn_vhdl, + "pcibr_dmamap_alloc: xtalk_dmamap_alloc failed\n")); free_pciio_dmamap(pcibr_dmamap); return 0; } xio_port = pcibr_soft->bs_mxid; - slot = pciio_info_slot_get(pciio_info); + slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_dmamap->bd_dev = pconn_vhdl; - pcibr_dmamap->bd_slot = slot; + pcibr_dmamap->bd_slot = PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot); pcibr_dmamap->bd_soft = pcibr_soft; pcibr_dmamap->bd_xtalk = xtalk_dmamap; pcibr_dmamap->bd_max_size = req_size_max; @@ -2812,29 +3226,37 @@ pcibr_dmamap->bd_xio_addr = 0; pcibr_dmamap->bd_pci_addr = pci_addr; - /* Make sure we have an RRB (or two). + /* If in PCI mode, make sure we have an RRB (or two). */ - if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) { + if (IS_PCI(pcibr_soft) && + !(pcibr_soft->bs_rrb_fixed & (1 << slot))) { if (flags & PCIBR_VCHAN1) - slot += PCIBR_RRB_SLOT_VIRTUAL; - have_rrbs = pcibr_soft->bs_rrb_valid[slot]; + vchan = VCHAN1; + have_rrbs = pcibr_soft->bs_rrb_valid[slot][vchan]; if (have_rrbs < 2) { if (pci_addr & PCI64_ATTR_PREF) min_rrbs = 2; else min_rrbs = 1; if (have_rrbs < min_rrbs) - do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs); + do_pcibr_rrb_autoalloc(pcibr_soft, slot, vchan, + min_rrbs - have_rrbs); } } -#if PCIBR_ATE_DEBUG - printk("pcibr_dmamap_alloc: using direct64\n"); -#endif + PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP | PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmamap_alloc: using direct64, map=0x%x\n", + pcibr_dmamap)); return pcibr_dmamap; } -#if PCIBR_ATE_DEBUG - printk("pcibr_dmamap_alloc: unable to use direct64\n"); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMAMAP | PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmamap_alloc: unable to use direct64\n")); + + /* PIC only supports 64-bit direct mapping in PCI-X mode. */ + if (IS_PCIX(pcibr_soft)) { + DEL(pcibr_dmamap); + return 0; + } + flags &= ~PCIIO_DMA_A64; } if (flags & PCIIO_FIXED) { @@ -2849,17 +3271,17 @@ * Mapping calls may fail if target * is outside the direct32 range. */ -#if PCIBR_ATE_DEBUG - printk("pcibr_dmamap_alloc: using direct32\n"); -#endif + PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP | PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmamap_alloc: using direct32, map=0x%x\n", + pcibr_dmamap)); pcibr_dmamap->bd_flags = flags; pcibr_dmamap->bd_xio_addr = pcibr_soft->bs_dir_xbase; pcibr_dmamap->bd_pci_addr = PCI32_DIRECT_BASE; return pcibr_dmamap; } -#if PCIBR_ATE_DEBUG - printk("pcibr_dmamap_alloc: unable to use direct32\n"); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMAMAP | PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmamap_alloc: unable to use direct32\n")); + /* If the user demands FIXED and we can't * give it to him, fail. */ @@ -2892,9 +3314,9 @@ int have_rrbs; int min_rrbs; -#if PCIBR_ATE_DEBUG - printk("pcibr_dmamap_alloc: using PMU\n"); -#endif + PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP, pconn_vhdl, + "pcibr_dmamap_alloc: using PMU, ate_index=%d, " + "pcibr_dmamap=0x%x\n", ate_index, pcibr_dmamap)); ate_proto = pcibr_flags_to_ate(flags); @@ -2904,7 +3326,7 @@ /* * for xbridge the byte-swap bit == bit 29 of PCI address */ - if (pcibr_soft->bs_xbridge) { + if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) { if (flags & PCIIO_BYTE_STREAM) ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr); /* @@ -2926,18 +3348,19 @@ /* Make sure we have an RRB (or two). */ if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) { - have_rrbs = pcibr_soft->bs_rrb_valid[slot]; + have_rrbs = pcibr_soft->bs_rrb_valid[slot][vchan]; if (have_rrbs < 2) { if (ate_proto & ATE_PREF) min_rrbs = 2; else min_rrbs = 1; if (have_rrbs < min_rrbs) - do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs); + do_pcibr_rrb_autoalloc(pcibr_soft, slot, vchan, + min_rrbs - have_rrbs); } } if (ate_index >= pcibr_soft->bs_int_ate_size && - !pcibr_soft->bs_xbridge) { + !IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) { bridge_t *bridge = pcibr_soft->bs_base; volatile unsigned *cmd_regp; unsigned cmd_reg; @@ -2946,27 +3369,35 @@ pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_SSRAM; s = pcibr_lock(pcibr_soft); - cmd_regp = &(bridge-> - b_type0_cfg_dev[slot]. - l[PCI_CFG_COMMAND / 4]); - cmd_reg = *cmd_regp; + cmd_regp = pcibr_slot_config_addr(bridge, slot, + PCI_CFG_COMMAND/4); + if ( IS_PIC_SOFT(pcibr_soft) ) { + cmd_reg = pcibr_slot_config_get(bridge, slot, PCI_CFG_COMMAND/4); + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_SET32((&cmd_reg)) = __swab32(*cmd_regp); + } else { + cmd_reg = pcibr_slot_config_get(bridge, slot, PCI_CFG_COMMAND/4); + } + } pcibr_soft->bs_slot[slot].bss_cmd_pointer = cmd_regp; pcibr_soft->bs_slot[slot].bss_cmd_shadow = cmd_reg; pcibr_unlock(pcibr_soft, s); } return pcibr_dmamap; } -#if PCIBR_ATE_DEBUG - printk("pcibr_dmamap_alloc: unable to use PMU\n"); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMAMAP, pconn_vhdl, + "pcibr_dmamap_alloc: PMU use failed, ate_index=%d\n", + ate_index)); + pcibr_ate_free(pcibr_soft, ate_index, ate_count); } /* total failure: sorry, you just can't * get from here to there that way. */ -#if PCIBR_ATE_DEBUG - printk("pcibr_dmamap_alloc: complete failure.\n"); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMAMAP, pconn_vhdl, + "pcibr_dmamap_alloc: complete failure.\n")); xtalk_dmamap_free(xtalk_dmamap); free_pciio_dmamap(pcibr_dmamap); return 0; @@ -2977,7 +3408,8 @@ pcibr_dmamap_free(pcibr_dmamap_t pcibr_dmamap) { pcibr_soft_t pcibr_soft = pcibr_dmamap->bd_soft; - pciio_slot_t slot = pcibr_dmamap->bd_slot; + pciio_slot_t slot = PCIBR_SLOT_TO_DEVICE(pcibr_soft, + pcibr_dmamap->bd_slot); unsigned flags = pcibr_dmamap->bd_flags; @@ -3001,6 +3433,9 @@ pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_PMU_BITS); } + PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev, + "pcibr_dmamap_free: pcibr_dmamap=0x%x\n", pcibr_dmamap)); + free_pciio_dmamap(pcibr_dmamap); } @@ -3029,15 +3464,15 @@ pci_addr = xio_addr - BRIDGE_PCI_MEM64_BASE; return pci_addr; } - for (slot = 0; slot < 8; ++slot) - if ((xio_addr >= BRIDGE_DEVIO(slot)) && - (xio_lim < BRIDGE_DEVIO(slot + 1))) { + for (slot = soft->bs_min_slot; slot < PCIBR_NUM_SLOTS(soft); ++slot) + if ((xio_addr >= PCIBR_BRIDGE_DEVIO(soft, slot)) && + (xio_lim < PCIBR_BRIDGE_DEVIO(soft, slot + 1))) { bridgereg_t dev; dev = soft->bs_slot[slot].bss_device; pci_addr = dev & BRIDGE_DEV_OFF_MASK; pci_addr <<= BRIDGE_DEV_OFF_ADDR_SHFT; - pci_addr += xio_addr - BRIDGE_DEVIO(slot); + pci_addr += xio_addr - PCIBR_BRIDGE_DEVIO(soft, slot); return (dev & BRIDGE_DEV_DEV_IO_MEM) ? pci_addr : PCI_NOWHERE; } return 0; @@ -3070,7 +3505,7 @@ } else xio_port = pcibr_dmamap->bd_xio_port; - /* If this DMA is to an address that + /* If this DMA is to an addres that * refers back to this Bridge chip, * reduce it back to the correct * PCI MEM address. @@ -3099,14 +3534,12 @@ if (flags & PCIBR_NOPREFETCH) pci_addr &= ~PCI64_ATTR_PREF; -#if DEBUG && PCIBR_DMA_DEBUG - printk("pcibr_dmamap_addr (direct64):\n" - "\twanted paddr [0x%x..0x%x]\n" - "\tXIO port 0x%x offset 0x%x\n" - "\treturning PCI 0x%x\n", - paddr, paddr + req_size - 1, - xio_port, xio_addr, pci_addr); -#endif + PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP | PCIBR_DEBUG_DMADIR, + pcibr_dmamap->bd_dev, + "pcibr_dmamap_addr: (direct64): wanted paddr [0x%x..0x%x] " + "XIO port 0x%x offset 0x%x, returning PCI 0x%x\n", + paddr, paddr + req_size - 1, xio_port, xio_addr, pci_addr)); + } else if (flags & PCIIO_FIXED) { /* A32 direct DMA: * always use 32-bit direct mapping, @@ -3126,14 +3559,12 @@ pci_addr = pcibr_dmamap->bd_pci_addr + xio_addr - pcibr_dmamap->bd_xio_addr; -#if DEBUG && PCIBR_DMA_DEBUG - printk("pcibr_dmamap_addr (direct32):\n" - "\twanted paddr [0x%x..0x%x]\n" - "\tXIO port 0x%x offset 0x%x\n" - "\treturning PCI 0x%x\n", - paddr, paddr + req_size - 1, - xio_port, xio_addr, pci_addr); -#endif + PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP | PCIBR_DEBUG_DMADIR, + pcibr_dmamap->bd_dev, + "pcibr_dmamap_addr (direct32): wanted paddr [0x%x..0x%x] " + "XIO port 0x%x offset 0x%x, returning PCI 0x%x\n", + paddr, paddr + req_size - 1, xio_port, xio_addr, pci_addr)); + } else { bridge_t *bridge = pcibr_soft->bs_base; iopaddr_t offset = IOPGOFF(xio_addr); @@ -3148,14 +3579,6 @@ int ate_total = ate_count; unsigned freeze_time; #endif - -#if PCIBR_ATE_DEBUG - bridge_ate_t ate_cmp; - bridge_ate_p ate_cptr; - unsigned ate_lo, ate_hi; - int ate_bad = 0; - int ate_rbc = 0; -#endif bridge_ate_p ate_ptr = pcibr_dmamap->bd_ate_ptr; bridge_ate_t ate; @@ -3183,7 +3606,21 @@ ATE_FREEZE(); ATE_WRITE(); ATE_THAW(); - bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + if ( IS_PIC_SOFT(pcibr_soft) ) { + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_GET32((&bridge->b_wid_tflush)); + } else { + bridge->b_wid_tflush; + } + } + PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev, + "pcibr_dmamap_addr (PMU) : wanted paddr " + "[0x%x..0x%x] returning PCI 0x%x\n", + paddr, paddr + req_size - 1, pci_addr)); + } else { /* The number of ATE's required is greater than the number * allocated for this map. One way this can happen is if @@ -3193,14 +3630,12 @@ * The other possibility is that the map is just plain too * small to handle the requested target area. */ -#if PCIBR_ATE_DEBUG - printk(KERN_WARNING "pcibr_dmamap_addr :\n" - "\twanted paddr [0x%x..0x%x]\n" - "\tate_count 0x%x bd_ate_count 0x%x\n" - "\tATE's required > number allocated\n", - paddr, paddr + req_size - 1, - ate_count, pcibr_dmamap->bd_ate_count); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev, + "pcibr_dmamap_addr (PMU) : wanted paddr " + "[0x%x..0x%x] ate_count 0x%x bd_ate_count 0x%x " + "ATE's required > number allocated\n", + paddr, paddr + req_size - 1, + ate_count, pcibr_dmamap->bd_ate_count)); pci_addr = 0; } @@ -3250,17 +3685,24 @@ xtalk_alenlist = xtalk_dmamap_list(pcibr_dmamap->bd_xtalk, palenlist, flags & DMAMAP_FLAGS); - if (!xtalk_alenlist) + if (!xtalk_alenlist) { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev, + "pcibr_dmamap_list: xtalk_dmamap_list() failed, " + "pcibr_dmamap=0x%x\n", pcibr_dmamap)); goto fail; - + } alenlist_cursor_init(xtalk_alenlist, 0, NULL); if (inplace) { pciio_alenlist = xtalk_alenlist; } else { pciio_alenlist = alenlist_create(al_flags); - if (!pciio_alenlist) + if (!pciio_alenlist) { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev, + "pcibr_dmamap_list: alenlist_create() failed, " + "pcibr_dmamap=0x%lx\n", (unsigned long)pcibr_dmamap)); goto fail; + } } direct64 = pcibr_dmamap->bd_flags & PCIIO_DMA_A64; @@ -3286,8 +3728,12 @@ if (xio_port == pcibr_soft->bs_xid) { new_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, length); - if (new_addr == PCI_NOWHERE) + if (new_addr == PCI_NOWHERE) { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev, + "pcibr_dmamap_list: pcibr_addr_xio_to_pci failed, " + "pcibr_dmamap=0x%x\n", pcibr_dmamap)); goto fail; + } } else if (direct64) { new_addr = pci_addr | xio_addr | ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT); @@ -3318,9 +3764,8 @@ | (xio_port << ATE_TIDSHIFT) | (xio_addr - offset); if (ate == ate_prev) { -#if PCIBR_ATE_DEBUG - printk("pcibr_dmamap_list: ATE share\n"); -#endif + PCIBR_DEBUG((PCIBR_DEBUG_ATE, pcibr_dmamap->bd_dev, + "pcibr_dmamap_list: ATE share\n")); ate_ptr--; ate_index--; pci_addr -= IOPGSIZE; @@ -3335,14 +3780,13 @@ /* Ensure that this map contains enough ATE's */ if (ate_total > pcibr_dmamap->bd_ate_count) { -#if PCIBR_ATE_DEBUG - printk(KERN_WARNING "pcibr_dmamap_list :\n" - "\twanted xio_addr [0x%x..0x%x]\n" - "\tate_total 0x%x bd_ate_count 0x%x\n" - "\tATE's required > number allocated\n", - xio_addr, xio_addr + length - 1, - ate_total, pcibr_dmamap->bd_ate_count); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ATE, pcibr_dmamap->bd_dev, + "pcibr_dmamap_list :\n" + "\twanted xio_addr [0x%x..0x%x]\n" + "\tate_total 0x%x bd_ate_count 0x%x\n" + "\tATE's required > number allocated\n", + xio_addr, xio_addr + length - 1, + ate_total, pcibr_dmamap->bd_ate_count)); goto fail; } @@ -3362,13 +3806,22 @@ if (inplace) { if (ALENLIST_SUCCESS != alenlist_replace(pciio_alenlist, NULL, - &new_addr, &length, al_flags)) + &new_addr, &length, al_flags)) { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev, + "pcibr_dmamap_list: alenlist_replace() failed, " + "pcibr_dmamap=0x%x\n", pcibr_dmamap)); + goto fail; + } } else { if (ALENLIST_SUCCESS != alenlist_append(pciio_alenlist, - new_addr, length, al_flags)) + new_addr, length, al_flags)) { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev, + "pcibr_dmamap_list: alenlist_append() failed, " + "pcibr_dmamap=0x%x\n", pcibr_dmamap)); goto fail; + } } } if (!inplace) @@ -3386,8 +3839,21 @@ */ if (ate_freeze_done) { ATE_THAW(); - bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + if ( IS_PIC_SOFT(pcibr_soft) ) { + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_GET32((&bridge->b_wid_tflush)); + } else { + bridge->b_wid_tflush; + } + } } + PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev, + "pcibr_dmamap_list: pcibr_dmamap=0x%x, pciio_alenlist=0x%x\n", + pcibr_dmamap, pciio_alenlist)); + return pciio_alenlist; fail: @@ -3398,7 +3864,16 @@ */ if (ate_freeze_done) { ATE_THAW(); - bridge->b_wid_tflush; + if ( IS_PIC_SOFT(pcibr_soft) ) { + bridge->b_wid_tflush; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_GET32((&bridge->b_wid_tflush)); + } else { + bridge->b_wid_tflush; + } + } } if (pciio_alenlist && !inplace) alenlist_destroy(pciio_alenlist); @@ -3409,6 +3884,10 @@ void pcibr_dmamap_done(pcibr_dmamap_t pcibr_dmamap) { +#ifdef PIC_LATER + pcibr_soft_t pcibr_soft = pcibr_dmamap->bd_soft; + pciio_slot_t slot = PCIBR_SLOT_TO_DEVICE(pcibr_soft, +#endif /* * We could go through and invalidate ATEs here; * for performance reasons, we don't. @@ -3423,6 +3902,9 @@ atomic_dec(&(pcibr_dmamap->bd_soft->bs_slot[pcibr_dmamap->bd_slot]. bss_ext_ates_active)); } xtalk_dmamap_done(pcibr_dmamap->bd_xtalk); + + PCIBR_DEBUG((PCIBR_DEBUG_DMAMAP, pcibr_dmamap->bd_dev, + "pcibr_dmamap_done: pcibr_dmamap=0x%x\n", pcibr_dmamap)); } @@ -3455,7 +3937,7 @@ pciio_info_t pciio_info = pciio_info_get(pconn_vhdl); pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info); devfs_handle_t xconn_vhdl = pcibr_soft->bs_conn; - pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info); + pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_soft_slot_t slotp = &pcibr_soft->bs_slot[pciio_slot]; xwidgetnum_t xio_port; @@ -3464,24 +3946,18 @@ int have_rrbs; int min_rrbs; + int vchan = VCHAN0; /* merge in forced flags */ flags |= pcibr_soft->bs_dma_flags; xio_addr = xtalk_dmatrans_addr(xconn_vhdl, 0, paddr, req_size, flags & DMAMAP_FLAGS); - if (!xio_addr) { -#if PCIBR_DMA_DEBUG - printk("pcibr_dmatrans_addr:\n" - "\tpciio connection point %v\n" - "\txtalk connection point %v\n" - "\twanted paddr [0x%x..0x%x]\n" - "\txtalk_dmatrans_addr returned 0x%x\n", - pconn_vhdl, xconn_vhdl, - paddr, paddr + req_size - 1, - xio_addr); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], " + "xtalk_dmatrans_addr failed with 0x%x\n", + paddr, paddr + req_size - 1, xio_addr)); return 0; } /* @@ -3489,16 +3965,10 @@ */ if (XIO_PACKED(xio_addr)) { if (xio_addr == XIO_NOWHERE) { -#if PCIBR_DMA_DEBUG - printk("pcibr_dmatrans_addr:\n" - "\tpciio connection point %v\n" - "\txtalk connection point %v\n" - "\twanted paddr [0x%x..0x%x]\n" - "\txtalk_dmatrans_addr returned 0x%x\n", - pconn_vhdl, xconn_vhdl, - paddr, paddr + req_size - 1, - xio_addr); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], " + "xtalk_dmatrans_addr failed with XIO_NOWHERE\n", + paddr, paddr + req_size - 1)); return 0; } xio_port = XIO_PORT(xio_addr); @@ -3516,6 +3986,10 @@ */ if (xio_port == pcibr_soft->bs_xid) { pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size); + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], " + "xio_port=0x%x, pci_addr=0x%x\n", + paddr, paddr + req_size - 1, xio_port, pci_addr)); return pci_addr; } /* If the caller can use A64, try to @@ -3532,82 +4006,65 @@ if ((pci_addr != PCIBR_D64_BASE_UNSET) && (flags == slotp->bss_d64_flags)) { - pci_addr |= xio_addr + pci_addr |= xio_addr | ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT); -#if DEBUG && PCIBR_DMA_DEBUG #if HWG_PERF_CHECK if (xio_addr != 0x20000000) #endif - printk("pcibr_dmatrans_addr: [reuse]\n" - "\tpciio connection point %v\n" - "\txtalk connection point %v\n" - "\twanted paddr [0x%x..0x%x]\n" - "\txtalk_dmatrans_addr returned 0x%x\n" - "\tdirect 64bit address is 0x%x\n", - pconn_vhdl, xconn_vhdl, - paddr, paddr + req_size - 1, - xio_addr, pci_addr); -#endif + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], " + "xio_port=0x%x, direct64: pci_addr=0x%x\n", + paddr, paddr + req_size - 1, xio_addr, pci_addr)); return (pci_addr); } if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS)) { pci_addr = pcibr_flags_to_d64(flags, pcibr_soft); slotp->bss_d64_flags = flags; slotp->bss_d64_base = pci_addr; - pci_addr |= xio_addr + pci_addr |= xio_addr | ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT); - /* Make sure we have an RRB (or two). + /* If in PCI mode, make sure we have an RRB (or two). */ - if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) { + if (IS_PCI(pcibr_soft) && + !(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) { if (flags & PCIBR_VCHAN1) - pciio_slot += PCIBR_RRB_SLOT_VIRTUAL; - have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot]; + vchan = VCHAN1; + have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot][vchan]; if (have_rrbs < 2) { if (pci_addr & PCI64_ATTR_PREF) min_rrbs = 2; else min_rrbs = 1; if (have_rrbs < min_rrbs) - do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs); + do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, vchan, + min_rrbs - have_rrbs); } } -#if PCIBR_DMA_DEBUG #if HWG_PERF_CHECK if (xio_addr != 0x20000000) #endif - printk("pcibr_dmatrans_addr:\n" - "\tpciio connection point %v\n" - "\txtalk connection point %v\n" - "\twanted paddr [0x%x..0x%x]\n" - "\txtalk_dmatrans_addr returned 0x%x\n" - "\tdirect 64bit address is 0x%x\n" - "\tnew flags: 0x%x\n", - pconn_vhdl, xconn_vhdl, - paddr, paddr + req_size - 1, - xio_addr, pci_addr, (uint64_t) flags); -#endif + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], " + "xio_port=0x%x, direct64: pci_addr=0x%x, " + "new flags: 0x%x\n", paddr, paddr + req_size - 1, + xio_addr, pci_addr, (uint64_t) flags)); return (pci_addr); } - /* our flags conflict with Device(x). - */ - flags = flags - & ~PCIIO_DMA_A64 - & ~PCIBR_VCHAN0 - ; -#if PCIBR_DMA_DEBUG - printk("pcibr_dmatrans_addr:\n" - "\tpciio connection point %v\n" - "\txtalk connection point %v\n" - "\twanted paddr [0x%x..0x%x]\n" - "\txtalk_dmatrans_addr returned 0x%x\n" - "\tUnable to set Device(x) bits for Direct-64\n", - pconn_vhdl, xconn_vhdl, - paddr, paddr + req_size - 1, - xio_addr); -#endif + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], " + "xio_port=0x%x, Unable to set direct64 Device(x) bits\n", + paddr, paddr + req_size - 1, xio_addr)); + + /* PIC only supports 64-bit direct mapping in PCI-X mode */ + if (IS_PCIX(pcibr_soft)) { + return 0; + } + + /* our flags conflict with Device(x). try direct32*/ + flags = flags & ~(PCIIO_DMA_A64 | PCIBR_VCHAN0); } /* Try to satisfy the request with the 32-bit direct * map. This can fail if the configuration bits in @@ -3624,17 +4081,11 @@ (xio_addr < xio_base) || (xio_port != pcibr_soft->bs_dir_xport) || (endoff > map_size)) { -#if PCIBR_DMA_DEBUG - printk("pcibr_dmatrans_addr:\n" - "\tpciio connection point %v\n" - "\txtalk connection point %v\n" - "\twanted paddr [0x%x..0x%x]\n" - "\txtalk_dmatrans_addr returned 0x%x\n" - "\txio region outside direct32 target\n", - pconn_vhdl, xconn_vhdl, - paddr, paddr + req_size - 1, - xio_addr); -#endif + + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], " + "xio_port=0x%x, xio region outside direct32 target\n", + paddr, paddr + req_size - 1, xio_addr)); } else { pci_addr = slotp->bss_d32_base; if ((pci_addr != PCIBR_D32_BASE_UNSET) && @@ -3642,18 +4093,11 @@ pci_addr |= offset; -#if DEBUG && PCIBR_DMA_DEBUG - printk("pcibr_dmatrans_addr: [reuse]\n" - "\tpciio connection point %v\n" - "\txtalk connection point %v\n" - "\twanted paddr [0x%x..0x%x]\n" - "\txtalk_dmatrans_addr returned 0x%x\n" - "\tmapped via direct32 offset 0x%x\n" - "\twill DMA via pci addr 0x%x\n", - pconn_vhdl, xconn_vhdl, - paddr, paddr + req_size - 1, - xio_addr, offset, pci_addr); -#endif + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], " + "xio_port=0x%x, direct32: pci_addr=0x%x\n", + paddr, paddr + req_size - 1, xio_addr, pci_addr)); + return (pci_addr); } if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS)) { @@ -3666,61 +4110,41 @@ /* Make sure we have an RRB (or two). */ if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) { - have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot]; + have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot][vchan]; if (have_rrbs < 2) { if (slotp->bss_device & BRIDGE_DEV_PREF) min_rrbs = 2; else min_rrbs = 1; if (have_rrbs < min_rrbs) - do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs); + do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, + vchan, min_rrbs - have_rrbs); } } -#if PCIBR_DMA_DEBUG #if HWG_PERF_CHECK if (xio_addr != 0x20000000) #endif - printk("pcibr_dmatrans_addr:\n" - "\tpciio connection point %v\n" - "\txtalk connection point %v\n" - "\twanted paddr [0x%x..0x%x]\n" - "\txtalk_dmatrans_addr returned 0x%x\n" - "\tmapped via direct32 offset 0x%x\n" - "\twill DMA via pci addr 0x%x\n" - "\tnew flags: 0x%x\n", - pconn_vhdl, xconn_vhdl, - paddr, paddr + req_size - 1, - xio_addr, offset, pci_addr, (uint64_t) flags); -#endif + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], " + "xio_port=0x%x, direct32: pci_addr=0x%x, " + "new flags: 0x%x\n", paddr, paddr + req_size - 1, + xio_addr, pci_addr, (uint64_t) flags)); + return (pci_addr); } /* our flags conflict with Device(x). */ -#if PCIBR_DMA_DEBUG - printk("pcibr_dmatrans_addr:\n" - "\tpciio connection point %v\n" - "\txtalk connection point %v\n" - "\twanted paddr [0x%x..0x%x]\n" - "\txtalk_dmatrans_addr returned 0x%x\n" - "\tUnable to set Device(x) bits for Direct-32\n", - pconn_vhdl, xconn_vhdl, - paddr, paddr + req_size - 1, - xio_addr); -#endif + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], " + "xio_port=0x%x, Unable to set direct32 Device(x) bits\n", + paddr, paddr + req_size - 1, xio_port)); } } -#if PCIBR_DMA_DEBUG - printk("pcibr_dmatrans_addr:\n" - "\tpciio connection point %v\n" - "\txtalk connection point %v\n" - "\twanted paddr [0x%x..0x%x]\n" - "\txtalk_dmatrans_addr returned 0x%x\n" - "\tno acceptable PCI address found or constructable\n", - pconn_vhdl, xconn_vhdl, - paddr, paddr + req_size - 1, - xio_addr); -#endif + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_addr: wanted paddr [0x%x..0x%x], " + "xio_port=0x%x, No acceptable PCI address found\n", + paddr, paddr + req_size - 1, xio_port)); return 0; } @@ -3735,7 +4159,7 @@ pciio_info_t pciio_info = pciio_info_get(pconn_vhdl); pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info); devfs_handle_t xconn_vhdl = pcibr_soft->bs_conn; - pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info); + pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_soft_slot_t slotp = &pcibr_soft->bs_slot[pciio_slot]; xwidgetnum_t xio_port; @@ -3772,6 +4196,9 @@ /* reuse previous base info */ } else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS) < 0) { /* DMA configuration conflict */ + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_list: DMA configuration conflict " + "for direct64, flags=0x%x\n", flags)); goto fail; } else { relbits = BRIDGE_DEV_D64_BITS; @@ -3787,6 +4214,9 @@ /* reuse previous base info */ } else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS) < 0) { /* DMA configuration conflict */ + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_list: DMA configuration conflict " + "for direct32, flags=0x%x\n", flags)); goto fail; } else { relbits = BRIDGE_DEV_D32_BITS; @@ -3796,8 +4226,12 @@ xtalk_alenlist = xtalk_dmatrans_list(xconn_vhdl, 0, palenlist, flags & DMAMAP_FLAGS); - if (!xtalk_alenlist) + if (!xtalk_alenlist) { + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_list: xtalk_dmatrans_list failed " + "xtalk_alenlist=0x%x\n", xtalk_alenlist)); goto fail; + } alenlist_cursor_init(xtalk_alenlist, 0, NULL); @@ -3805,8 +4239,12 @@ pciio_alenlist = xtalk_alenlist; } else { pciio_alenlist = alenlist_create(al_flags); - if (!pciio_alenlist) + if (!pciio_alenlist) { + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_list: alenlist_create failed with " + " 0x%x\n", pciio_alenlist)); goto fail; + } } while (ALENLIST_SUCCESS == @@ -3818,16 +4256,8 @@ */ if (XIO_PACKED(xio_addr)) { if (xio_addr == XIO_NOWHERE) { -#if PCIBR_DMA_DEBUG - printk("pcibr_dmatrans_addr:\n" - "\tpciio connection point %v\n" - "\txtalk connection point %v\n" - "\twanted paddr [0x%x..0x%x]\n" - "\txtalk_dmatrans_addr returned 0x%x\n", - pconn_vhdl, xconn_vhdl, - paddr, paddr + req_size - 1, - xio_addr); -#endif + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_list: xio_addr == XIO_NOWHERE\n")); return 0; } xio_port = XIO_PORT(xio_addr); @@ -3844,8 +4274,12 @@ */ if (xio_port == pcibr_soft->bs_xid) { pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, xio_size); - if ( (pci_addr == (alenaddr_t)NULL) ) + if (pci_addr == (alenaddr_t)NULL) { + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_list: pcibr_addr_xio_to_pci failed " + "xio_addr=0x%x, xio_size=0x%x\n", xio_addr, xio_size)); goto fail; + } } else if (direct64) { ASSERT(xio_port != 0); pci_addr = pci_base | xio_addr @@ -3857,8 +4291,14 @@ if ((xio_size > map_size) || (xio_addr < xio_base) || (xio_port != pcibr_soft->bs_dir_xport) || - (endoff > map_size)) + (endoff > map_size)) { + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_list: xio_size > map_size fail\n" + "xio_addr=0x%x, xio_size=0x%x. map_size=0x%x, " + "xio_port=0x%x, endoff=0x%x\n", + xio_addr, xio_size, map_size, xio_port, endoff)); goto fail; + } pci_addr = pci_base + (xio_addr - xio_base); } @@ -3869,13 +4309,19 @@ if (inplace) { if (ALENLIST_SUCCESS != alenlist_replace(pciio_alenlist, NULL, - &pci_addr, &xio_size, al_flags)) + &pci_addr, &xio_size, al_flags)) { + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_list: alenlist_replace failed\n")); goto fail; + } } else { if (ALENLIST_SUCCESS != alenlist_append(pciio_alenlist, - pci_addr, xio_size, al_flags)) + pci_addr, xio_size, al_flags)) { + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_list: alenlist_append failed\n")); goto fail; + } } } @@ -3895,6 +4341,11 @@ * to the caller. */ alenlist_cursor_init(pciio_alenlist, 0, NULL); + + PCIBR_DEBUG((PCIBR_DEBUG_DMADIR, pconn_vhdl, + "pcibr_dmatrans_list: pciio_alenlist=0x%x\n", + pciio_alenlist)); + return pciio_alenlist; fail: @@ -3964,8 +4415,9 @@ int pcibr_reset(devfs_handle_t conn) { +#ifdef PIC_LATER pciio_info_t pciio_info = pciio_info_get(conn); - pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info); + pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info); bridge_t *bridge = pcibr_soft->bs_base; bridgereg_t ctlreg; @@ -3975,42 +4427,59 @@ pcibr_info_h pcibr_infoh; pcibr_info_t pcibr_info; int win; + int error = 0; +#endif /* PIC_LATER */ + BUG(); +#ifdef PIC_LATER if (pcibr_soft->bs_slot[pciio_slot].has_host) { pciio_slot = pcibr_soft->bs_slot[pciio_slot].host_slot; pcibr_info = pcibr_soft->bs_slot[pciio_slot].bss_infos[0]; } - if (pciio_slot < 4) { + + if ((pciio_slot >= pcibr_soft->bs_first_slot) && + (pciio_slot <= pcibr_soft->bs_last_reset)) { s = pcibr_lock(pcibr_soft); nf = pcibr_soft->bs_slot[pciio_slot].bss_ninfo; pcibr_infoh = pcibr_soft->bs_slot[pciio_slot].bss_infos; for (f = 0; f < nf; ++f) if (pcibr_infoh[f]) - cfgctl[f] = bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4]; + cfgctl[f] = pcibr_func_config_get(bridge, pciio_slot, f, + PCI_CFG_COMMAND/4); + + error = iobrick_pci_slot_rst(pcibr_soft->bs_l1sc, + pcibr_widget_to_bus(pcibr_soft->bs_vhdl), + PCIBR_DEVICE_TO_SLOT(pcibr_soft,pciio_slot), + NULL); ctlreg = bridge->b_wid_control; - bridge->b_wid_control = ctlreg | BRIDGE_CTRL_RST(pciio_slot); - /* XXX delay? */ - bridge->b_wid_control = ctlreg; - /* XXX delay? */ + bridge->b_wid_control = ctlreg & ~BRIDGE_CTRL_RST_PIN(pciio_slot); + nano_delay(&ts); + bridge->b_wid_control = ctlreg | BRIDGE_CTRL_RST_PIN(pciio_slot); + nano_delay(&ts); for (f = 0; f < nf; ++f) if ((pcibr_info = pcibr_infoh[f])) for (win = 0; win < 6; ++win) if (pcibr_info->f_window[win].w_base != 0) - bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_BASE_ADDR(win) / 4] = - pcibr_info->f_window[win].w_base; + pcibr_func_config_set(bridge, pciio_slot, f, + PCI_CFG_BASE_ADDR(win) / 4, + pcibr_info->f_window[win].w_base); for (f = 0; f < nf; ++f) if (pcibr_infoh[f]) - bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4] = cfgctl[f]; + pcibr_func_config_set(bridge, pciio_slot, f, + PCI_CFG_COMMAND / 4, + cfgctl[f]); pcibr_unlock(pcibr_soft, s); + if (error) + return(-1); + return 0; } -#ifdef SUPPORT_PRINTING_V_FORMAT - printk(KERN_WARNING "%v: pcibr_reset unimplemented for slot %d\n", - conn, pciio_slot); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DETACH, conn, + "pcibr_reset unimplemented for slot %d\n", conn, pciio_slot)); +#endif /* PIC_LATER */ return -1; } @@ -4020,7 +4489,7 @@ pciio_endian_t desired_end) { pciio_info_t pciio_info = pciio_info_get(pconn_vhdl); - pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info); + pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info); bridgereg_t devreg; unsigned long s; @@ -4044,16 +4513,32 @@ if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) { bridge_t *bridge = pcibr_soft->bs_base; - bridge->b_device[pciio_slot].reg = devreg; - pcibr_soft->bs_slot[pciio_slot].bss_device = devreg; - bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + if ( IS_PIC_SOFT(pcibr_soft) ) { + bridge->b_device[pciio_slot].reg = devreg; + pcibr_soft->bs_slot[pciio_slot].bss_device = devreg; + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_SET32((&bridge->b_device[pciio_slot].reg)) = __swab32(devreg); + pcibr_soft->bs_slot[pciio_slot].bss_device = devreg; + BRIDGE_REG_GET32((&bridge->b_wid_tflush));/* wait until Bridge PIO complete */ + } else { + bridge->b_device[pciio_slot].reg = devreg; + pcibr_soft->bs_slot[pciio_slot].bss_device = devreg; + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } + } } pcibr_unlock(pcibr_soft, s); -#if DEBUG && PCIBR_DEV_DEBUG - printk("pcibr Device(%d): 0x%p\n", pciio_slot, bridge->b_device[pciio_slot].reg); +#ifdef PIC_LATER + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DEVREG, pconn_vhdl, + "pcibr_endian_set: Device(%d): %x\n", + pciio_slot, devreg, device_bits)); +#else + printk("pcibr_endian_set: Device(%d): %x\n", pciio_slot, devreg); #endif - return desired_end; } @@ -4121,9 +4606,22 @@ if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) { bridge_t *bridge = pcibr_soft->bs_base; - bridge->b_device[pciio_slot].reg = devreg; - pcibr_soft->bs_slot[pciio_slot].bss_device = devreg; - bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + if ( IS_PIC_SOFT(pcibr_soft) ) { + bridge->b_device[pciio_slot].reg = devreg; + pcibr_soft->bs_slot[pciio_slot].bss_device = devreg; + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_SET32((&bridge->b_device[pciio_slot].reg)) = __swab32(devreg); + pcibr_soft->bs_slot[pciio_slot].bss_device = devreg; + BRIDGE_REG_GET32((&bridge->b_wid_tflush));/* wait until Bridge PIO complete */ + } else { + bridge->b_device[pciio_slot].reg = devreg; + pcibr_soft->bs_slot[pciio_slot].bss_device = devreg; + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } + } } pcibr_unlock(pcibr_soft, s); @@ -4135,7 +4633,7 @@ pciio_priority_t device_prio) { pciio_info_t pciio_info = pciio_info_get(pconn_vhdl); - pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info); + pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info); (void) pcibr_priority_bits_set(pcibr_soft, pciio_slot, device_prio); @@ -4159,7 +4657,7 @@ pcibr_device_flags_t flags) { pciio_info_t pciio_info = pciio_info_get(pconn_vhdl); - pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info); + pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info); bridgereg_t set = 0; bridgereg_t clr = 0; @@ -4206,18 +4704,81 @@ if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) { bridge_t *bridge = pcibr_soft->bs_base; - bridge->b_device[pciio_slot].reg = devreg; - pcibr_soft->bs_slot[pciio_slot].bss_device = devreg; - bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + if ( IS_PIC_SOFT(pcibr_soft) ) { + bridge->b_device[pciio_slot].reg = devreg; + pcibr_soft->bs_slot[pciio_slot].bss_device = devreg; + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_SET32((&bridge->b_device[pciio_slot].reg)) = __swab32(devreg); + pcibr_soft->bs_slot[pciio_slot].bss_device = devreg; + BRIDGE_REG_GET32((&bridge->b_wid_tflush));/* wait until Bridge PIO complete */ + } else { + bridge->b_device[pciio_slot].reg = devreg; + pcibr_soft->bs_slot[pciio_slot].bss_device = devreg; + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } + } } pcibr_unlock(pcibr_soft, s); -#if DEBUG && PCIBR_DEV_DEBUG - printk("pcibr Device(%d): %R\n", pciio_slot, bridge->b_device[pciio_slot].regbridge->b_device[pciio_slot].reg, device_bits); +#ifdef PIC_LATER + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DEVREG, pconn_vhdl, + "pcibr_device_flags_set: Device(%d): %x\n", + pciio_slot, devreg, device_bits)); +#else + printk("pcibr_device_flags_set: Device(%d): %x\n", pciio_slot, devreg); #endif } return (1); } +/* + * PIC has 16 RBARs per bus; meaning it can have a total of 16 outstanding + * split transactions. If the functions on the bus have requested a total + * of 16 or less, then we can give them what they requested (ie. 100%). + * Otherwise we have make sure each function can get at least one buffer + * and then divide the rest of the buffers up among the functions as ``A + * PERCENTAGE OF WHAT THEY REQUESTED'' (i.e. 0% - 100% of a function's + * pcix_type0_status.max_out_split). This percentage does not include the + * one RBAR that all functions get by default. + */ +int +pcibr_pcix_rbars_calc(pcibr_soft_t pcibr_soft) +{ + /* 'percent_allowed' is the percentage of requested RBARs that functions + * are allowed, ***less the 1 RBAR that all functions get by default*** + */ + int percent_allowed; + + if (pcibr_soft->bs_pcix_num_funcs) { + if (pcibr_soft->bs_pcix_num_funcs > NUM_RBAR) { + printk(KERN_WARNING + "%lx: Must oversubscribe Read Buffer Attribute Registers" + "(RBAR). Bus has %d RBARs but %d funcs need them.\n", + (unsigned long)pcibr_soft->bs_vhdl, NUM_RBAR, pcibr_soft->bs_pcix_num_funcs); + percent_allowed = 0; + } else { + percent_allowed = (((NUM_RBAR-pcibr_soft->bs_pcix_num_funcs)*100) / + pcibr_soft->bs_pcix_split_tot); + + /* +1 to percentage to solve rounding errors that occur because + * we're not doing fractional math. (ie. ((3 * 66%) / 100) = 1) + * but should be "2" if doing true fractional math. NOTE: Since + * the greatest number of outstanding transactions a function + * can request is 32, this "+1" will always work (i.e. we won't + * accidentally oversubscribe the RBARs because of this rounding + * of the percentage). + */ + percent_allowed=(percent_allowed > 100) ? 100 : percent_allowed+1; + } + } else { + return(ENODEV); + } + + return(percent_allowed); +} + pciio_provider_t pcibr_provider = { (pciio_piomap_alloc_f *) pcibr_piomap_alloc, @@ -4253,17 +4814,17 @@ (pciio_priority_set_f *) pcibr_priority_set, (pciio_config_get_f *) pcibr_config_get, (pciio_config_set_f *) pcibr_config_set, - - (pciio_error_devenable_f *) 0, - (pciio_error_extract_f *) 0, - -#ifdef LATER +#ifdef PIC_LATER + (pciio_error_devenable_f *) pcibr_error_devenable, + (pciio_error_extract_f *) pcibr_error_extract, (pciio_driver_reg_callback_f *) pcibr_driver_reg_callback, (pciio_driver_unreg_callback_f *) pcibr_driver_unreg_callback, #else + (pciio_error_devenable_f *) 0, + (pciio_error_extract_f *) 0, (pciio_driver_reg_callback_f *) 0, (pciio_driver_unreg_callback_f *) 0, -#endif +#endif /* PIC_LATER */ (pciio_device_unregister_f *) pcibr_device_unregister, (pciio_dma_enabled_f *) pcibr_dma_enabled, }; @@ -4276,4 +4837,84 @@ return xtalk_dma_enabled(pcibr_soft->bs_conn); +} + + +/* + * pcibr_debug() is used to print pcibr debug messages to the console. A + * user enables tracing by setting the following global variables: + * + * pcibr_debug_mask -Bitmask of what to trace. see pcibr_private.h + * pcibr_debug_module -Module to trace. 'all' means trace all modules + * pcibr_debug_widget -Widget to trace. '-1' means trace all widgets + * pcibr_debug_slot -Slot to trace. '-1' means trace all slots + * + * 'type' is the type of debugging that the current PCIBR_DEBUG macro is + * tracing. 'vhdl' (which can be NULL) is the vhdl associated with the + * debug statement. If there is a 'vhdl' associated with this debug + * statement, it is parsed to obtain the module, widget, and slot. If the + * globals above match the PCIBR_DEBUG params, then the debug info in the + * parameter 'format' is sent to the console. + */ +void +pcibr_debug(uint32_t type, devfs_handle_t vhdl, char *format, ...) +{ + char hwpath[MAXDEVNAME] = "\0"; + char copy_of_hwpath[MAXDEVNAME]; + char *module = "all"; + short widget = -1; + short slot = -1; + va_list ap; + char *strtok_r(char *string, const char *sepset, char **lasts); + + if (pcibr_debug_mask & type) { + if (vhdl) { + if (!hwgraph_vertex_name_get(vhdl, hwpath, MAXDEVNAME)) { + char *cp; + + if (strcmp(module, pcibr_debug_module)) { + /* strtok_r() wipes out string, use a copy */ + (void)strcpy(copy_of_hwpath, hwpath); + cp = strstr(copy_of_hwpath, "/module/"); + if (cp) { + char *last = NULL; + cp += strlen("/module"); + module = strtok_r(cp, "/", &last); + } + } + if (pcibr_debug_widget != -1) { + cp = strstr(hwpath, "/xtalk/"); + if (cp) { + cp += strlen("/xtalk/"); + widget = atoi(cp); + } + } + if (pcibr_debug_slot != -1) { + cp = strstr(hwpath, "/pci/"); + if (cp) { + cp += strlen("/pci/"); + slot = atoi(cp); + } + } + } + } + if ((vhdl == NULL) || + (!strcmp(module, pcibr_debug_module) && + (widget == pcibr_debug_widget) && + (slot == pcibr_debug_slot))) { +#ifdef LATER + printk("PCIBR_DEBUG<%d>\t: %s :", cpuid(), hwpath); +#else + printk("PCIBR_DEBUG\t: %s :", hwpath); +#endif + /* + * Kernel printk translates to this 3 line sequence. + * Since we have a variable length argument list, we + * need to call printk this way rather than directly + */ + va_start(ap, format); + printk(format, ap); + va_end(ap); + } + } } diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c Wed Jan 15 16:57:28 2003 @@ -39,6 +39,14 @@ #endif extern int hubii_check_widget_disabled(nasid_t, int); +#ifdef BRIDGE_B_DATACORR_WAR +extern int ql_bridge_rev_b_war(devfs_handle_t); +extern int bridge_rev_b_data_check_disable; +char *rev_b_datacorr_warning = +"***************************** WARNING! ******************************\n"; +char *rev_b_datacorr_mesg = +"UNRECOVERABLE IO LINK ERROR. CONTACT SERVICE PROVIDER\n"; +#endif /* ===================================================================== * ERROR HANDLING @@ -54,15 +62,18 @@ #define BRIDGE_PIOERR_TIMEOUT 1 /* Timeout in non-debug mode */ #endif +/* PIC has 64bit interrupt error registers, but BRIDGE has 32bit registers. + * Thus 'bridge_errors_to_dump needs' to default to the larger of the two. + */ #ifdef DEBUG #ifdef ERROR_DEBUG -bridgereg_t bridge_errors_to_dump = ~BRIDGE_ISR_INT_MSK; +uint64_t bridge_errors_to_dump = ~BRIDGE_ISR_INT_MSK; #else -bridgereg_t bridge_errors_to_dump = BRIDGE_ISR_ERROR_DUMP; +uint64_t bridge_errors_to_dump = BRIDGE_ISR_ERROR_DUMP; #endif #else -bridgereg_t bridge_errors_to_dump = BRIDGE_ISR_ERROR_FATAL | - BRIDGE_ISR_PCIBUS_PIOERR; +uint64_t bridge_errors_to_dump = BRIDGE_ISR_ERROR_FATAL | + BRIDGE_ISR_PCIBUS_PIOERR; #endif #if defined (PCIBR_LLP_CONTROL_WAR) @@ -71,8 +82,6 @@ /* FIXME: can these arrays be local ? */ -#ifdef LATER - struct reg_values xio_cmd_pactyp[] = { {0x0, "RdReq"}, @@ -113,7 +122,21 @@ struct reg_desc bridge_int_status_desc[] = { - F(31, "MULTI_ERR"), + F(45, "PCI_X_SPLIT_MES_PE"),/* PIC ONLY */ + F(44, "PCI_X_SPLIT_EMES"), /* PIC ONLY */ + F(43, "PCI_X_SPLIT_TO"), /* PIC ONLY */ + F(42, "PCI_X_UNEX_COMP"), /* PIC ONLY */ + F(41, "INT_RAM_PERR"), /* PIC ONLY */ + F(40, "PCI_X_ARB_ERR"), /* PIC ONLY */ + F(39, "PCI_X_REQ_TOUT"), /* PIC ONLY */ + F(38, "PCI_X_TABORT"), /* PIC ONLY */ + F(37, "PCI_X_PERR"), /* PIC ONLY */ + F(36, "PCI_X_SERR"), /* PIC ONLY */ + F(35, "PCI_X_MRETRY"), /* PIC ONLY */ + F(34, "PCI_X_MTOUT"), /* PIC ONLY */ + F(33, "PCI_X_DA_PARITY"), /* PIC ONLY */ + F(32, "PCI_X_AD_PARITY"), /* PIC ONLY */ + F(31, "MULTI_ERR"), /* BRIDGE ONLY */ F(30, "PMU_ESIZE_EFAULT"), F(29, "UNEXPECTED_RESP"), F(28, "BAD_XRESP_PACKET"), @@ -128,7 +151,7 @@ F(19, "LLP_RCTY"), F(18, "LLP_TX_RETRY"), F(17, "LLP_TCTY"), - F(16, "SSRAM_PERR"), + F(16, "SSRAM_PERR"), /* BRIDGE ONLY */ F(15, "PCI_ABORT"), F(14, "PCI_PARITY"), F(13, "PCI_SERR"), @@ -136,7 +159,7 @@ F(11, "PCI_MASTER_TOUT"), F(10, "PCI_RETRY_CNT"), F(9, "XREAD_REQ_TOUT"), - F(8, "GIO_BENABLE_ERR"), + F(8, "GIO_BENABLE_ERR"), /* BRIDGE ONLY */ F(7, "INT7"), F(6, "INT6"), F(5, "INT5"), @@ -195,20 +218,17 @@ {0} }; -#endif /* LATER */ - void print_bridge_errcmd(uint32_t cmdword, char *errtype) { - printk( - "\t Bridge %s Error Command Word Register %R\n", - errtype, cmdword, xio_cmd_bits); + printk("\t Bridge %s Error Command Word Register ", errtype); + print_register(cmdword, xio_cmd_bits); } char *pcibr_isr_errs[] = { "", "", "", "", "", "", "", "", - "08: GIO non-contiguous byte enable in crosstalk packet", + "08: GIO non-contiguous byte enable in crosstalk packet", /* BRIDGE ONLY */ "09: PCI to Crosstalk read request timeout", "10: PCI retry operation count exhausted.", "11: PCI bus device select timeout", @@ -216,7 +236,7 @@ "13: PCI Address/Cmd parity error ", "14: PCI Bridge detected parity error", "15: PCI abort condition", - "16: SSRAM parity error", + "16: SSRAM parity error", /* BRIDGE ONLY */ "17: LLP Transmitter Retry count wrapped", "18: LLP Transmitter side required Retry", "19: LLP Receiver retry count wrapped", @@ -231,13 +251,29 @@ "28: Framing error, response cmd data size does not match actual", "29: Unexpected response arrived", "30: PMU Access Fault", - "31: Multiple errors occurred", + "31: Multiple errors occurred", /* BRIDGE ONLY */ + + /* bits 32-45 are PIC ONLY */ + "32: PCI-X address or attribute cycle parity error", + "33: PCI-X data cycle parity error", + "34: PCI-X master timeout (ie. master abort)", + "35: PCI-X pio retry counter exhausted", + "36: PCI-X SERR", + "37: PCI-X PERR", + "38: PCI-X target abort", + "39: PCI-X read request timeout", + "40: PCI / PCI-X device requestin arbitration error", + "41: internal RAM parity error", + "42: PCI-X unexpected completion cycle to master", + "43: PCI-X split completion timeout", + "44: PCI-X split completion error message", + "45: PCI-X split completion message parity error", }; #define BEM_ADD_STR(s) printk("%s", (s)) -#define BEM_ADD_VAR(v) printk("\t%20s: 0x%x\n", #v, (v)) -#define BEM_ADD_REG(r) printk("\t%20s: %R\n", #r, (r), r ## _desc) -#define BEM_ADD_NSPC(n,s) printk("\t%20s: %R\n", n, s, space_desc) +#define BEM_ADD_VAR(v) printk("\t%20s: 0x%llx\n", #v, ((unsigned long long)v)) +#define BEM_ADD_REG(r) printk("\t%20s: ", #r); print_register((r), r ## _desc) +#define BEM_ADD_NSPC(n,s) printk("\t%20s: ", n); print_register(s, space_desc) #define BEM_ADD_SPC(s) BEM_ADD_NSPC(#s, s) /* @@ -246,6 +282,7 @@ void pcibr_show_dir_state(paddr_t paddr, char *prefix) { +#ifdef LATER int state; uint64_t vec_ptr; hubreg_t elo; @@ -254,8 +291,9 @@ get_dir_ent(paddr, &state, &vec_ptr, &elo); - printf("%saddr 0x%x: state 0x%x owner 0x%x (%s)\n", + printk("%saddr 0x%lx: state 0x%x owner 0x%lx (%s)\n", prefix, paddr, state, vec_ptr, dir_state_str[state]); +#endif } @@ -267,40 +305,70 @@ pcibr_error_dump(pcibr_soft_t pcibr_soft) { bridge_t *bridge = pcibr_soft->bs_base; - bridgereg_t int_status; - bridgereg_t mult_int; - int bit; + uint64_t int_status; + bridgereg_t int_status_32; + picreg_t int_status_64; + uint64_t mult_int; + bridgereg_t mult_int_32; + picreg_t mult_int_64; + uint64_t bit; + int number_bits; int i; char *reg_desc; - paddr_t addr; + paddr_t addr = (paddr_t)0; + + /* We read the INT_STATUS register as a 64bit picreg_t for PIC and a + * 32bit bridgereg_t for BRIDGE, but always process the result as a + * 64bit value so the code can be "common" for both PIC and BRIDGE... + */ + if (IS_PIC_SOFT(pcibr_soft)) { + int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK); + int_status = (uint64_t)int_status_64; + number_bits = PCIBR_ISR_MAX_ERRS_PIC; + } else { + int_status_32 = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK); + int_status = ((uint64_t)int_status_32) & 0xffffffff; + number_bits = PCIBR_ISR_MAX_ERRS_BRIDGE; + } - int_status = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK); if (!int_status) { /* No error bits set */ return; } /* Check if dumping the same error information multiple times */ - if (test_and_set_int((int *) &pcibr_soft->bs_errinfo.bserr_intstat, - int_status) == int_status) { + if ( pcibr_soft->bs_errinfo.bserr_intstat == int_status ) return; - } + pcibr_soft->bs_errinfo.bserr_intstat = int_status; - printk(KERN_ALERT "PCI BRIDGE ERROR: int_status is 0x%X for %s\n" - " Dumping relevant %sBridge registers for each bit set...\n", + printk(KERN_ALERT "PCI BRIDGE ERROR: int_status is 0x%lx for %s\n" + " Dumping relevant %s registers for each bit set...\n", int_status, pcibr_soft->bs_name, - (is_xbridge(bridge) ? "X" : "")); + (IS_PIC_SOFT(pcibr_soft) ? "PIC" : + (IS_BRIDGE_SOFT(pcibr_soft) ? "BRIDGE" : "XBRIDGE"))); - for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++) { - bit = 1 << i; + for (i = PCIBR_ISR_ERR_START; i < number_bits; i++) { + bit = 1ull << i; /* * A number of int_status bits are only defined for Bridge. - * Ignore them in the case of an XBridge. + * Ignore them in the case of an XBridge or PIC. */ - if (is_xbridge(bridge) && ((bit == BRIDGE_ISR_MULTI_ERR) || - (bit == BRIDGE_ISR_SSRAM_PERR) || - (bit == BRIDGE_ISR_GIO_B_ENBL_ERR))) { + if ((IS_XBRIDGE_SOFT(pcibr_soft) || IS_PIC_SOFT(pcibr_soft)) && + ((bit == BRIDGE_ISR_MULTI_ERR) || + (bit == BRIDGE_ISR_SSRAM_PERR) || + (bit == BRIDGE_ISR_GIO_B_ENBL_ERR))) { + continue; + } + + /* A number of int_status bits are only valid for PIC's bus0 */ + if ((IS_PIC_SOFT(pcibr_soft) && (pcibr_soft->bs_busnum != 0)) && + ((bit == BRIDGE_ISR_UNSUPPORTED_XOP) || + (bit == BRIDGE_ISR_LLP_REC_SNERR) || + (bit == BRIDGE_ISR_LLP_REC_CBERR) || + (bit == BRIDGE_ISR_LLP_RCTY) || + (bit == BRIDGE_ISR_LLP_TX_RETRY) || + (bit == BRIDGE_ISR_LLP_TCTY))) { continue; } @@ -308,91 +376,241 @@ printk("\t%s\n", pcibr_isr_errs[i]); switch (bit) { - case BRIDGE_ISR_PAGE_FAULT: /* PMU_PAGE_FAULT (XBridge) */ -/* case BRIDGE_ISR_PMU_ESIZE_FAULT: PMU_ESIZE_FAULT (Bridge) */ - if (is_xbridge(bridge)) + + case PIC_ISR_INT_RAM_PERR: /* bit41 INT_RAM_PERR */ + /* XXX: should breakdown meaning of bits in reg */ + printk( "\t Internal RAM Parity Error: 0x%lx\n", + bridge->p_ate_parity_err_64); + break; + + case PIC_ISR_PCIX_ARB_ERR: /* bit40 PCI_X_ARB_ERR */ + /* XXX: should breakdown meaning of bits in reg */ + printk( "\t Arbitration Reg: 0x%x\n", + bridge->b_arb); + break; + + case PIC_ISR_PCIX_REQ_TOUT: /* bit39 PCI_X_REQ_TOUT */ + /* XXX: should breakdown meaning of attribute bit */ + printk( + "\t PCI-X DMA Request Error Address Reg: 0x%lx\n" + "\t PCI-X DMA Request Error Attribute Reg: 0x%lx\n", + bridge->p_pcix_dma_req_err_addr_64, + bridge->p_pcix_dma_req_err_attr_64); + break; + + case PIC_ISR_PCIX_SPLIT_MSG_PE: /* bit45 PCI_X_SPLIT_MES_PE */ + case PIC_ISR_PCIX_SPLIT_EMSG: /* bit44 PCI_X_SPLIT_EMESS */ + case PIC_ISR_PCIX_SPLIT_TO: /* bit43 PCI_X_SPLIT_TO */ + /* XXX: should breakdown meaning of attribute bit */ + printk( + "\t PCI-X Split Request Address Reg: 0x%lx\n" + "\t PCI-X Split Request Attribute Reg: 0x%lx\n", + bridge->p_pcix_pio_split_addr_64, + bridge->p_pcix_pio_split_attr_64); + /* FALL THRU */ + + case PIC_ISR_PCIX_UNEX_COMP: /* bit42 PCI_X_UNEX_COMP */ + case PIC_ISR_PCIX_TABORT: /* bit38 PCI_X_TABORT */ + case PIC_ISR_PCIX_PERR: /* bit37 PCI_X_PERR */ + case PIC_ISR_PCIX_SERR: /* bit36 PCI_X_SERR */ + case PIC_ISR_PCIX_MRETRY: /* bit35 PCI_X_MRETRY */ + case PIC_ISR_PCIX_MTOUT: /* bit34 PCI_X_MTOUT */ + case PIC_ISR_PCIX_DA_PARITY: /* bit33 PCI_X_DA_PARITY */ + case PIC_ISR_PCIX_AD_PARITY: /* bit32 PCI_X_AD_PARITY */ + /* XXX: should breakdown meaning of attribute bit */ + printk( + "\t PCI-X Bus Error Address Reg: 0x%lx\n" + "\t PCI-X Bus Error Attribute Reg: 0x%lx\n" + "\t PCI-X Bus Error Data Reg: 0x%lx\n", + bridge->p_pcix_bus_err_addr_64, + bridge->p_pcix_bus_err_attr_64, + bridge->p_pcix_bus_err_data_64); + break; + + case BRIDGE_ISR_PAGE_FAULT: /* bit30 PMU_PAGE_FAULT */ +/* case BRIDGE_ISR_PMU_ESIZE_FAULT: bit30 PMU_ESIZE_FAULT */ + if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) reg_desc = "Map Fault Address"; else reg_desc = "SSRAM Parity Error"; - printk("\t %s Register: 0x%x\n", reg_desc, + printk( "\t %s Register: 0x%x\n", reg_desc, bridge->b_ram_perr_or_map_fault); break; - case BRIDGE_ISR_UNEXP_RESP: /* UNEXPECTED_RESP */ - print_bridge_errcmd(bridge->b_wid_aux_err, "Aux"); - break; + case BRIDGE_ISR_UNEXP_RESP: /* bit29 UNEXPECTED_RESP */ + print_bridge_errcmd(bridge->b_wid_aux_err, "Aux "); - case BRIDGE_ISR_BAD_XRESP_PKT: /* BAD_RESP_PACKET */ - case BRIDGE_ISR_RESP_XTLK_ERR: /* RESP_XTALK_ERROR */ - case BRIDGE_ISR_XREAD_REQ_TIMEOUT: /* XREAD_REQ_TOUT */ + /* PIC in PCI-X mode, dump the PCIX DMA Request registers */ + if (IS_PIC_SOFT(pcibr_soft) && IS_PCIX(pcibr_soft)) { + /* XXX: should breakdown meaning of attr bit */ + printk( + "\t PCI-X DMA Request Error Addr Reg: 0x%lx\n" + "\t PCI-X DMA Request Error Attr Reg: 0x%lx\n", + bridge->p_pcix_dma_req_err_addr_64, + bridge->p_pcix_dma_req_err_attr_64); + } + break; - addr = (((uint64_t) (bridge->b_wid_resp_upper & 0xFFFF) << 32) - | bridge->b_wid_resp_lower); - printk( - "\t Bridge Response Buffer Error Upper Address Register: 0x%x\n" - "\t Bridge Response Buffer Error Lower Address Register: 0x%x\n" - "\t dev-num %d buff-num %d addr 0x%x\n", - bridge->b_wid_resp_upper, bridge->b_wid_resp_lower, - ((bridge->b_wid_resp_upper >> 20) & 0x3), - ((bridge->b_wid_resp_upper >> 16) & 0xF), - addr); + case BRIDGE_ISR_BAD_XRESP_PKT: /* bit28 BAD_RESP_PACKET */ + case BRIDGE_ISR_RESP_XTLK_ERR: /* bit26 RESP_XTALK_ERROR */ + if (IS_PIC_SOFT(pcibr_soft)) { + print_bridge_errcmd(bridge->b_wid_aux_err, "Aux "); + } + + /* If PIC in PCI-X mode, DMA Request Error registers are + * valid. But PIC in PCI mode, Response Buffer Address + * register are valid. + */ + if (IS_PCIX(pcibr_soft)) { + /* XXX: should breakdown meaning of attribute bit */ + printk( + "\t PCI-X DMA Request Error Addr Reg: 0x%lx\n" + "\t PCI-X DMA Request Error Attribute Reg: 0x%lx\n", + bridge->p_pcix_dma_req_err_addr_64, + bridge->p_pcix_dma_req_err_attr_64); + } else { + addr= (((uint64_t)(bridge->b_wid_resp_upper & 0xFFFF)<<32) + | bridge->b_wid_resp_lower); + printk("\t Bridge Response Buf Error Upper Addr Reg: 0x%x\n" + "\t Bridge Response Buf Error Lower Addr Reg: 0x%x\n" + "\t dev-num %d buff-num %d addr 0x%lx\n", + bridge->b_wid_resp_upper, bridge->b_wid_resp_lower, + ((bridge->b_wid_resp_upper >> 20) & 0x3), + ((bridge->b_wid_resp_upper >> 16) & 0xF), + addr); + } if (bit == BRIDGE_ISR_RESP_XTLK_ERR) { /* display memory directory associated with cacheline */ pcibr_show_dir_state(addr, "\t "); } break; - case BRIDGE_ISR_BAD_XREQ_PKT: /* BAD_XREQ_PACKET */ - case BRIDGE_ISR_REQ_XTLK_ERR: /* REQ_XTALK_ERROR */ - case BRIDGE_ISR_INVLD_ADDR: /* INVALID_ADDRESS */ - case BRIDGE_ISR_UNSUPPORTED_XOP: /* UNSUPPORTED_XOP */ - print_bridge_errcmd(bridge->b_wid_aux_err, ""); - printk("\t Bridge Error Upper Address Register: 0x%x\n" - "\t Bridge Error Lower Address Register: 0x%x\n" - "\t Bridge Error Address: 0x%x\n", + case BRIDGE_ISR_BAD_XREQ_PKT: /* bit27 BAD_XREQ_PACKET */ + case BRIDGE_ISR_REQ_XTLK_ERR: /* bit25 REQ_XTALK_ERROR */ + case BRIDGE_ISR_INVLD_ADDR: /* bit24 INVALID_ADDRESS */ + print_bridge_errcmd(bridge->b_wid_err_cmdword, ""); + printk( + "\t Bridge Error Upper Address Register: 0x%lx\n" + "\t Bridge Error Lower Address Register: 0x%lx\n" + "\t Bridge Error Address: 0x%lx\n", (uint64_t) bridge->b_wid_err_upper, (uint64_t) bridge->b_wid_err_lower, (((uint64_t) bridge->b_wid_err_upper << 32) | bridge->b_wid_err_lower)); break; - case BRIDGE_ISR_SSRAM_PERR: /* SSRAM_PERR */ - if (!is_xbridge(bridge)) { /* only defined on Bridge */ + case BRIDGE_ISR_UNSUPPORTED_XOP:/* bit23 UNSUPPORTED_XOP */ + if (IS_PIC_SOFT(pcibr_soft)) { + print_bridge_errcmd(bridge->b_wid_aux_err, "Aux "); + printk( + "\t Address Holding Link Side Error Reg: 0x%lx\n", + bridge->p_addr_lkerr_64); + } else { + print_bridge_errcmd(bridge->b_wid_err_cmdword, ""); + printk( + "\t Bridge Error Upper Address Register: 0x%lx\n" + "\t Bridge Error Lower Address Register: 0x%lx\n" + "\t Bridge Error Address: 0x%lx\n", + (uint64_t) bridge->b_wid_err_upper, + (uint64_t) bridge->b_wid_err_lower, + (((uint64_t) bridge->b_wid_err_upper << 32) | + bridge->b_wid_err_lower)); + } + break; + + case BRIDGE_ISR_XREQ_FIFO_OFLOW:/* bit22 XREQ_FIFO_OFLOW */ + /* Link side error registers are only valid for PIC */ + if (IS_PIC_SOFT(pcibr_soft)) { + print_bridge_errcmd(bridge->b_wid_aux_err, "Aux "); + printk( + "\t Address Holding Link Side Error Reg: 0x%lx\n", + bridge->p_addr_lkerr_64); + } + break; + + case BRIDGE_ISR_SSRAM_PERR: /* bit16 SSRAM_PERR */ + if (IS_BRIDGE_SOFT(pcibr_soft)) { printk( "\t Bridge SSRAM Parity Error Register: 0x%x\n", bridge->b_ram_perr); } break; - case BRIDGE_ISR_PCI_ABORT: /* PCI_ABORT */ - case BRIDGE_ISR_PCI_PARITY: /* PCI_PARITY */ - case BRIDGE_ISR_PCI_SERR: /* PCI_SERR */ - case BRIDGE_ISR_PCI_PERR: /* PCI_PERR */ - case BRIDGE_ISR_PCI_MST_TIMEOUT: /* PCI_MASTER_TOUT */ - case BRIDGE_ISR_PCI_RETRY_CNT: /* PCI_RETRY_CNT */ - case BRIDGE_ISR_GIO_B_ENBL_ERR: /* GIO BENABLE_ERR */ - printk("\t PCI Error Upper Address Register: 0x%x\n" - "\t PCI Error Lower Address Register: 0x%x\n" - "\t PCI Error Address: 0x%x\n", + case BRIDGE_ISR_PCI_ABORT: /* bit15 PCI_ABORT */ + case BRIDGE_ISR_PCI_PARITY: /* bit14 PCI_PARITY */ + case BRIDGE_ISR_PCI_SERR: /* bit13 PCI_SERR */ + case BRIDGE_ISR_PCI_PERR: /* bit12 PCI_PERR */ + case BRIDGE_ISR_PCI_MST_TIMEOUT:/* bit11 PCI_MASTER_TOUT */ + case BRIDGE_ISR_PCI_RETRY_CNT: /* bit10 PCI_RETRY_CNT */ + case BRIDGE_ISR_GIO_B_ENBL_ERR: /* bit08 GIO BENABLE_ERR */ + printk( + "\t PCI Error Upper Address Register: 0x%lx\n" + "\t PCI Error Lower Address Register: 0x%lx\n" + "\t PCI Error Address: 0x%lx\n", (uint64_t) bridge->b_pci_err_upper, (uint64_t) bridge->b_pci_err_lower, (((uint64_t) bridge->b_pci_err_upper << 32) | bridge->b_pci_err_lower)); break; + + case BRIDGE_ISR_XREAD_REQ_TIMEOUT: /* bit09 XREAD_REQ_TOUT */ + addr = (((uint64_t)(bridge->b_wid_resp_upper & 0xFFFF) << 32) + | bridge->b_wid_resp_lower); + printk( + "\t Bridge Response Buf Error Upper Addr Reg: 0x%x\n" + "\t Bridge Response Buf Error Lower Addr Reg: 0x%x\n" + "\t dev-num %d buff-num %d addr 0x%lx\n", + bridge->b_wid_resp_upper, bridge->b_wid_resp_lower, + ((bridge->b_wid_resp_upper >> 20) & 0x3), + ((bridge->b_wid_resp_upper >> 16) & 0xF), + addr); + break; } } } - if (is_xbridge(bridge) && (bridge->b_mult_int & ~BRIDGE_ISR_INT_MSK)) { - mult_int = bridge->b_mult_int; - printk(" XBridge Multiple Interrupt Register is 0x%x\n", - mult_int); - for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++) { - if (mult_int & (1 << i)) - printk("\t%s\n", pcibr_isr_errs[i]); - } + /* We read the INT_MULT register as a 64bit picreg_t for PIC and a + * 32bit bridgereg_t for BRIDGE, but always process the result as a + * 64bit value so the code can be "common" for both PIC and BRIDGE... + */ + if (IS_PIC_SOFT(pcibr_soft)) { + mult_int_64 = (bridge->p_mult_int_64 & ~BRIDGE_ISR_INT_MSK); + mult_int = (uint64_t)mult_int_64; + number_bits = PCIBR_ISR_MAX_ERRS_PIC; + } else { + mult_int_32 = (bridge->b_mult_int & ~BRIDGE_ISR_INT_MSK); + mult_int = ((uint64_t)mult_int_32) & 0xffffffff; + number_bits = PCIBR_ISR_MAX_ERRS_BRIDGE; + } + + if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)&&(mult_int & ~BRIDGE_ISR_INT_MSK)) { + printk( " %s Multiple Interrupt Register is 0x%lx\n", + IS_PIC_SOFT(pcibr_soft) ? "PIC" : "XBridge", mult_int); + for (i = PCIBR_ISR_ERR_START; i < number_bits; i++) { + if (mult_int & (1ull << i)) + printk( "\t%s\n", pcibr_isr_errs[i]); } + } + +#if BRIDGE_ERROR_INTR_WAR + if (pcibr_soft->bs_rev_num == BRIDGE_PART_REV_A) { /* known bridge bug */ + /* + * Should never receive interrupts for these reasons on Rev 1 bridge + * as they are not enabled. Assert for it. + */ + ASSERT((int_status & (BRIDGE_IMR_PCI_MST_TIMEOUT | + BRIDGE_ISR_RESP_XTLK_ERR | + BRIDGE_ISR_LLP_TX_RETRY)) == 0); + } + if (pcibr_soft->bs_rev_num < BRIDGE_PART_REV_C) { /* known bridge bug */ + /* + * This interrupt is turned off at init time. So, should never + * see this interrupt. + */ + ASSERT((int_status & BRIDGE_ISR_BAD_XRESP_PKT) == 0); + } +#endif } #define PCIBR_ERRINTR_GROUP(error) \ @@ -430,9 +648,11 @@ pcibr_pioerr_check(pcibr_soft_t soft) { bridge_t *bridge; - bridgereg_t b_int_status; - bridgereg_t b_pci_err_lower; - bridgereg_t b_pci_err_upper; + uint64_t int_status; + bridgereg_t int_status_32; + picreg_t int_status_64; + bridgereg_t pci_err_lower; + bridgereg_t pci_err_upper; iopaddr_t pci_addr; pciio_slot_t slot; pcibr_piomap_t map; @@ -442,40 +662,48 @@ int func; bridge = soft->bs_base; - b_int_status = bridge->b_int_status; - if (b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) { - b_pci_err_lower = bridge->b_pci_err_lower; - b_pci_err_upper = bridge->b_pci_err_upper; - b_int_status = bridge->b_int_status; - if (b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) { - - pci_addr = b_pci_err_upper & BRIDGE_ERRUPPR_ADDRMASK; - pci_addr = (pci_addr << 32) | b_pci_err_lower; - - slot = 8; - while (slot-- > 0) { - int nfunc = soft->bs_slot[slot].bss_ninfo; - pcibr_info_h pcibr_infoh = soft->bs_slot[slot].bss_infos; - - for (func = 0; func < nfunc; func++) { - pcibr_info_t pcibr_info = pcibr_infoh[func]; - - if (!pcibr_info) - continue; - - for (map = pcibr_info->f_piomap; - map != NULL; map = map->bp_next) { - base = map->bp_pciaddr; - size = map->bp_mapsz; - win = map->bp_space - PCIIO_SPACE_WIN(0); - if (win < 6) - base += - soft->bs_slot[slot].bss_window[win].bssw_base; - else if (map->bp_space == PCIIO_SPACE_ROM) - base += pcibr_info->f_rbase; - if ((pci_addr >= base) && (pci_addr < (base + size))) - atomicAddInt(map->bp_toc, 1); - } + + /* We read the INT_STATUS register as a 64bit picreg_t for PIC and a + * 32bit bridgereg_t for BRIDGE, but always process the result as a + * 64bit value so the code can be "common" for both PIC and BRIDGE... + */ + if (IS_PIC_SOFT(soft)) { + int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK); + int_status = (uint64_t)int_status_64; + } else { + int_status_32 = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK); + int_status = ((uint64_t)int_status_32) & 0xffffffff; + } + + if (int_status & BRIDGE_ISR_PCIBUS_PIOERR) { + pci_err_lower = bridge->b_pci_err_lower; + pci_err_upper = bridge->b_pci_err_upper; + + pci_addr = pci_err_upper & BRIDGE_ERRUPPR_ADDRMASK; + pci_addr = (pci_addr << 32) | pci_err_lower; + + slot = PCIBR_NUM_SLOTS(soft); + while (slot-- > 0) { + int nfunc = soft->bs_slot[slot].bss_ninfo; + pcibr_info_h pcibr_infoh = soft->bs_slot[slot].bss_infos; + + for (func = 0; func < nfunc; func++) { + pcibr_info_t pcibr_info = pcibr_infoh[func]; + + if (!pcibr_info) + continue; + + for (map = pcibr_info->f_piomap; + map != NULL; map = map->bp_next) { + base = map->bp_pciaddr; + size = map->bp_mapsz; + win = map->bp_space - PCIIO_SPACE_WIN(0); + if (win < 6) + base += soft->bs_slot[slot].bss_window[win].bssw_base; + else if (map->bp_space == PCIIO_SPACE_ROM) + base += pcibr_info->f_rbase; + if ((pci_addr >= base) && (pci_addr < (base + size))) + atomic_inc(&map->bp_toc[0]); } } } @@ -502,25 +730,33 @@ * due to read or write error!. */ - void -pcibr_error_intr_handler(intr_arg_t arg) +pcibr_error_intr_handler(int irq, void *arg, struct pt_regs *ep) { pcibr_soft_t pcibr_soft; bridge_t *bridge; - bridgereg_t int_status; - bridgereg_t err_status; + uint64_t int_status; + uint64_t err_status; + bridgereg_t int_status_32; + picreg_t int_status_64; + int number_bits; int i; /* REFERENCED */ - bridgereg_t disable_errintr_mask = 0; + uint64_t disable_errintr_mask = 0; +#ifdef EHE_ENABLE int rv; int error_code = IOECODE_DMA | IOECODE_READ; ioerror_mode_t mode = MODE_DEVERROR; ioerror_t ioe; +#endif /* EHE_ENABLE */ nasid_t nasid; + #if PCIBR_SOFT_LIST + /* + * Defensive code for linked pcibr_soft structs + */ { extern pcibr_list_p pcibr_list; pcibr_list_p entry; @@ -528,17 +764,14 @@ entry = pcibr_list; while (1) { if (entry == NULL) { - PRINT_PANIC( - "pcibr_error_intr_handler:\n" - "\tmy parameter (0x%x) is not a pcibr_soft!", - arg); + PRINT_PANIC("pcibr_error_intr_handler:\tmy parameter (0x%p) is not a pcibr_soft!", arg); } if ((intr_arg_t) entry->bl_soft == arg) break; entry = entry->bl_next; } } -#endif +#endif /* PCIBR_SOFT_LIST */ pcibr_soft = (pcibr_soft_t) arg; bridge = pcibr_soft->bs_base; @@ -568,16 +801,37 @@ nasid = NASID_GET(bridge); if (hubii_check_widget_disabled(nasid, pcibr_soft->bs_xid)) { - timeout(pcibr_error_intr_handler, pcibr_soft, BRIDGE_PIOERR_TIMEOUT); + DECLARE_WAIT_QUEUE_HEAD(wq); + sleep_on_timeout(&wq, BRIDGE_PIOERR_TIMEOUT*HZ ); /* sleep */ pcibr_soft->bs_errinfo.bserr_toutcnt++; + /* Let's go recursive */ + return(pcibr_error_intr_handler(irq, arg, ep)); +#ifdef LATER + timeout(pcibr_error_intr_handler, pcibr_soft, BRIDGE_PIOERR_TIMEOUT); +#endif return; } + /* We read the INT_STATUS register as a 64bit picreg_t for PIC and a + * 32bit bridgereg_t for BRIDGE, but always process the result as a + * 64bit value so the code can be "common" for both PIC and BRIDGE... + */ + if (IS_PIC_SOFT(pcibr_soft)) { + int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK); + int_status = (uint64_t)int_status_64; + number_bits = PCIBR_ISR_MAX_ERRS_PIC; + } else { + int_status_32 = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK); + int_status = ((uint64_t)int_status_32) & 0xffffffff; + number_bits = PCIBR_ISR_MAX_ERRS_BRIDGE; + } + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ERROR, pcibr_soft->bs_conn, + "pcibr_error_intr_handler: int_status=0x%x\n", int_status)); + /* int_status is which bits we have to clear; * err_status is the bits we haven't handled yet. */ - - int_status = bridge->b_int_status & ~BRIDGE_ISR_INT_MSK; err_status = int_status & ~BRIDGE_ISR_MULTI_ERR; if (!(int_status & ~BRIDGE_ISR_INT_MSK)) { @@ -593,11 +847,29 @@ pcibr_pioerr_check(pcibr_soft); } +#ifdef BRIDGE_B_DATACORR_WAR + if ((pcibr_soft->bs_rev_num == BRIDGE_PART_REV_B) && + (err_status & BRIDGE_IMR_LLP_REC_CBERR)) { + if (bridge_rev_b_data_check_disable) + printk(KERN_WARNING "\n%s%s: %s%s\n", rev_b_datacorr_warning, + pcibr_soft->bs_name, rev_b_datacorr_mesg, + rev_b_datacorr_warning); + else { + ql_bridge_rev_b_war(pcibr_soft->bs_vhdl); + PRINT_PANIC( "\n%s%s: %s%s\n", rev_b_datacorr_warning, + pcibr_soft->bs_name, rev_b_datacorr_mesg, + rev_b_datacorr_warning); + } + + err_status &= ~BRIDGE_IMR_LLP_REC_CBERR; + } +#endif /* BRIDGE_B_DATACORR_WAR */ + if (err_status) { struct bs_errintr_stat_s *bs_estat = pcibr_soft->bs_errintr_stat; - for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++, bs_estat++) { - if (err_status & (1 << i)) { + for (i = PCIBR_ISR_ERR_START; i < number_bits; i++, bs_estat++) { + if (err_status & (1ull << i)) { uint32_t errrate = 0; uint32_t errcount = 0; uint32_t errinterval = 0, current_tick = 0; @@ -606,12 +878,14 @@ bs_estat->bs_errcount_total++; - current_tick = lbolt; + current_tick = jiffies; errinterval = (current_tick - bs_estat->bs_lasterr_timestamp); errcount = (bs_estat->bs_errcount_total - bs_estat->bs_lasterr_snapshot); - is_llp_tx_retry_intr = (BRIDGE_ISR_LLP_TX_RETRY == (1 << i)); + /* LLP interrrupt errors are only valid on BUS0 of the PIC */ + if (pcibr_soft->bs_busnum == 0) + is_llp_tx_retry_intr = (BRIDGE_ISR_LLP_TX_RETRY==(1ull << i)); /* Check for the divide by zero condition while * calculating the error rates. @@ -698,6 +972,15 @@ bs_estat->bs_errcount_total; } } + /* PIC BRINGUP WAR (PV# 856155): + * Dont disable PCI_X_ARB_ERR interrupts, we need the + * interrupt inorder to clear the DEV_BROKE bits in + * b_arb register to re-enable the device. + */ + if (IS_PIC_SOFT(pcibr_soft) && + !(err_status & PIC_ISR_PCIX_ARB_ERR) && + PCIBR_WAR_ENABLED(PV856155, pcibr_soft)) { + if (bs_estat->bs_errcount_total > PCIBR_ERRINTR_DISABLE_LEVEL) { /* * We have seen a fairly large number of errors of @@ -709,18 +992,26 @@ pcibr_soft->bs_name, pcibr_isr_errs[i], bs_estat->bs_errcount_total); - disable_errintr_mask |= (1 << i); + disable_errintr_mask |= (1ull << i); } + } /* PIC: WAR for PV 856155 end-of-if */ } } } if (disable_errintr_mask) { + unsigned s; /* * Disable some high frequency errors as they * could eat up too much cpu time. */ - bridge->b_int_enable &= ~disable_errintr_mask; + s = pcibr_lock(pcibr_soft); + if (IS_PIC_SOFT(pcibr_soft)) { + bridge->p_int_enable_64 &= (picreg_t)(~disable_errintr_mask); + } else { + bridge->b_int_enable &= (bridgereg_t)(~disable_errintr_mask); + } + pcibr_unlock(pcibr_soft, s); } /* * If we leave the PROM cacheable, T5 might @@ -783,15 +1074,34 @@ if (rv != IOERROR_HANDLED) { #endif /* EHE_ENABLE */ + bridge_errors_to_dump |= BRIDGE_ISR_PCIBUS_PIOERR; + /* Dump/Log Bridge error interrupt info */ if (err_status & bridge_errors_to_dump) { - printk("BRIDGE ERR_STATUS 0x%x\n", err_status); + printk("BRIDGE ERR_STATUS 0x%lx\n", err_status); pcibr_error_dump(pcibr_soft); } + /* PIC BRINGUP WAR (PV# 867308): + * Make BRIDGE_ISR_LLP_REC_SNERR & BRIDGE_ISR_LLP_REC_CBERR fatal errors + * so we know we've hit the problem defined in PV 867308 that we believe + * has only been seen in simulation + */ + if (IS_PIC_SOFT(pcibr_soft) && PCIBR_WAR_ENABLED(PV867308, pcibr_soft) && + (err_status & (BRIDGE_ISR_LLP_REC_SNERR | BRIDGE_ISR_LLP_REC_CBERR))) { + printk("BRIDGE ERR_STATUS 0x%x\n", err_status); + pcibr_error_dump(pcibr_soft); +#ifdef LATER + machine_error_dump(""); +#endif + PRINT_PANIC("PCI Bridge Error interrupt killed the system"); + } + if (err_status & BRIDGE_ISR_ERROR_FATAL) { +#ifdef LATER machine_error_dump(""); - cmn_err_tag(14, CE_PANIC, "PCI Bridge Error interrupt killed the system"); +#endif + PRINT_PANIC("PCI Bridge Error interrupt killed the system"); /*NOTREACHED */ } @@ -804,11 +1114,27 @@ * it would cause problems for devices like IOC3 (Lost * interrupts ?.). So, just cleanup the interrupt, and * use saved values later.. + * + * PIC doesn't require groups of interrupts to be cleared... */ - bridge->b_int_rst_stat = pcibr_errintr_group(int_status); + if (IS_PIC_SOFT(pcibr_soft)) { + bridge->p_int_rst_stat_64 = (picreg_t)(int_status | BRIDGE_IRR_MULTI_CLR); + } else { + bridge->b_int_rst_stat = (bridgereg_t)pcibr_errintr_group(int_status); + } + + /* PIC BRINGUP WAR (PV# 856155): + * On a PCI_X_ARB_ERR error interrupt clear the DEV_BROKE bits from + * the b_arb register to re-enable the device. + */ + if (IS_PIC_SOFT(pcibr_soft) && + (err_status & PIC_ISR_PCIX_ARB_ERR) && + PCIBR_WAR_ENABLED(PV856155, pcibr_soft)) { + bridge->b_arb |= (0xf << 20); + } /* Zero out bserr_intstat field */ - test_and_set_int((int *) &pcibr_soft->bs_errinfo.bserr_intstat, 0); + pcibr_soft->bs_errinfo.bserr_intstat = 0; } /* @@ -832,7 +1158,7 @@ iopaddr_t *offsetp, pciio_function_t *funcp) { - int s, f, w; + int s, f = 0, w; iopaddr_t base; size_t size; pciio_piospace_t piosp; @@ -864,7 +1190,7 @@ return s; } - for (s = 0; s < 8; s++) { + for (s = pcibr_soft->bs_min_slot; s < PCIBR_NUM_SLOTS(pcibr_soft); ++s) { int nf = pcibr_soft->bs_slot[s].bss_ninfo; pcibr_info_h pcibr_infoh = pcibr_soft->bs_slot[s].bss_infos; @@ -874,8 +1200,7 @@ if (!pcibr_info) continue; for (w = 0; w < 6; w++) { - if (pcibr_info->f_window[w].w_space - == PCIIO_SPACE_NONE) { + if (pcibr_info->f_window[w].w_space == PCIIO_SPACE_NONE) { continue; } base = pcibr_info->f_window[w].w_base; @@ -898,7 +1223,7 @@ * Check if the address was allocated as part of the * pcibr_piospace_alloc calls. */ - for (s = 0; s < 8; s++) { + for (s = pcibr_soft->bs_min_slot; s < PCIBR_NUM_SLOTS(pcibr_soft); ++s) { int nf = pcibr_soft->bs_slot[s].bss_ninfo; pcibr_info_h pcibr_infoh = pcibr_soft->bs_slot[s].bss_infos; @@ -950,8 +1275,14 @@ ASSERT(error_code & IOECODE_PIO); error_code = error_code; - bridge->b_int_rst_stat = - (BRIDGE_IRR_PCI_GRP_CLR | BRIDGE_IRR_MULTI_CLR); + if (IS_PIC_SOFT(pcibr_soft)) { + bridge->p_int_rst_stat_64 = BRIDGE_IRR_PCI_GRP_CLR | + PIC_PCIX_GRP_CLR | + BRIDGE_IRR_MULTI_CLR; + } else { + bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR | BRIDGE_IRR_MULTI_CLR; + } + (void) bridge->b_wid_tflush; /* flushbus */ } @@ -1040,13 +1371,6 @@ * associated with this device. */ -#define BEM_ADD_STR(s) printk("%s", (s)) -#define BEM_ADD_VAR(v) printk("\t%20s: 0x%x\n", #v, (v)) -#define BEM_ADD_REG(r) printk("\t%20s: %R\n", #r, (r), r ## _desc) - -#define BEM_ADD_NSPC(n,s) printk("\t%20s: %R\n", n, s, space_desc) -#define BEM_ADD_SPC(s) BEM_ADD_NSPC(#s, s) - /* BEM_ADD_IOE doesn't dump the whole ioerror, it just * decodes the PCI specific portions -- we count on our * callers to dump the raw IOE data. @@ -1054,40 +1378,38 @@ #define BEM_ADD_IOE(ioe) \ do { \ if (IOERROR_FIELDVALID(ioe, busspace)) { \ - unsigned spc; \ - unsigned win; \ + iopaddr_t spc; \ + iopaddr_t win; \ + short widdev; \ + iopaddr_t busaddr; \ \ - spc = IOERROR_GETVALUE(ioe, busspace); \ + IOERROR_GETVALUE(spc, ioe, busspace); \ win = spc - PCIIO_SPACE_WIN(0); \ + IOERROR_GETVALUE(busaddr, ioe, busaddr); \ + IOERROR_GETVALUE(widdev, ioe, widgetdev); \ \ switch (spc) { \ case PCIIO_SPACE_CFG: \ - printk( \ - "\tPCI Slot %d Func %d CFG space Offset 0x%x\n", \ - pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, widgetdev)), \ - pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, widgetdev)), \ - IOERROR_GETVALUE(ioe, busaddr)); \ + printk("\tPCI Slot %d Func %d CFG space Offset 0x%lx\n",\ + pciio_widgetdev_slot_get(widdev), \ + pciio_widgetdev_func_get(widdev), \ + busaddr); \ break; \ case PCIIO_SPACE_IO: \ - printk( \ - "\tPCI I/O space Offset 0x%x\n", \ - IOERROR_GETVALUE(ioe, busaddr)); \ + printk("\tPCI I/O space Offset 0x%lx\n", busaddr); \ break; \ case PCIIO_SPACE_MEM: \ case PCIIO_SPACE_MEM32: \ case PCIIO_SPACE_MEM64: \ - printk( \ - "\tPCI MEM space Offset 0x%x\n", \ - IOERROR_GETVALUE(ioe, busaddr)); \ + printk("\tPCI MEM space Offset 0x%lx\n", busaddr); \ break; \ default: \ if (win < 6) { \ - printk( \ - "\tPCI Slot %d Func %d Window %d Offset 0x%x\n",\ - pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, widgetdev)), \ - pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, widgetdev)), \ - win, \ - IOERROR_GETVALUE(ioe, busaddr)); \ + printk("\tPCI Slot %d Func %d Window %ld Offset 0x%lx\n",\ + pciio_widgetdev_slot_get(widdev), \ + pciio_widgetdev_func_get(widdev), \ + win, \ + busaddr); \ } \ break; \ } \ @@ -1129,34 +1451,38 @@ * and need to construct the slot/space/offset. */ - bad_xaddr = IOERROR_GETVALUE(ioe, xtalkaddr); + IOERROR_GETVALUE(bad_xaddr, ioe, xtalkaddr); + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ERROR_HDLR, pcibr_soft->bs_conn, + "pcibr_pioerror: pcibr_soft=0x%x, bad_xaddr=0x%x\n", + pcibr_soft, bad_xaddr)); slot = PCIIO_SLOT_NONE; func = PCIIO_FUNC_NONE; raw_space = PCIIO_SPACE_NONE; raw_paddr = 0; - if ((bad_xaddr >= BRIDGE_TYPE0_CFG_DEV0) && - (bad_xaddr < BRIDGE_TYPE1_CFG)) { - raw_paddr = bad_xaddr - BRIDGE_TYPE0_CFG_DEV0; + if ((bad_xaddr >= PCIBR_BUS_TYPE0_CFG_DEV0(pcibr_soft)) && + (bad_xaddr < PCIBR_TYPE1_CFG(pcibr_soft))) { + raw_paddr = bad_xaddr - PCIBR_BUS_TYPE0_CFG_DEV0(pcibr_soft); slot = raw_paddr / BRIDGE_TYPE0_CFG_SLOT_OFF; raw_paddr = raw_paddr % BRIDGE_TYPE0_CFG_SLOT_OFF; raw_space = PCIIO_SPACE_CFG; } - if ((bad_xaddr >= BRIDGE_TYPE1_CFG) && - (bad_xaddr < (BRIDGE_TYPE1_CFG + 0x1000))) { + if ((bad_xaddr >= PCIBR_TYPE1_CFG(pcibr_soft)) && + (bad_xaddr < (PCIBR_TYPE1_CFG(pcibr_soft) + 0x1000))) { /* Type 1 config space: * slot and function numbers not known. * Perhaps we can read them back? */ - raw_paddr = bad_xaddr - BRIDGE_TYPE1_CFG; + raw_paddr = bad_xaddr - PCIBR_TYPE1_CFG(pcibr_soft); raw_space = PCIIO_SPACE_CFG; } - if ((bad_xaddr >= BRIDGE_DEVIO0) && - (bad_xaddr < BRIDGE_DEVIO(BRIDGE_DEV_CNT))) { + if ((bad_xaddr >= PCIBR_BRIDGE_DEVIO0(pcibr_soft)) && + (bad_xaddr < PCIBR_BRIDGE_DEVIO(pcibr_soft, BRIDGE_DEV_CNT))) { int x; - raw_paddr = bad_xaddr - BRIDGE_DEVIO0; + raw_paddr = bad_xaddr - PCIBR_BRIDGE_DEVIO0(pcibr_soft); x = raw_paddr / BRIDGE_DEVIO_OFF; raw_paddr %= BRIDGE_DEVIO_OFF; /* first two devio windows are double-sized */ @@ -1223,7 +1549,9 @@ * going on (no guessing). */ - for (cs = 0; (cs < 8) && (slot == PCIIO_SLOT_NONE); cs++) { + for (cs = pcibr_soft->bs_min_slot; + (cs < PCIBR_NUM_SLOTS(pcibr_soft)) && + (slot == PCIIO_SLOT_NONE); cs++) { int nf = pcibr_soft->bs_slot[cs].bss_ninfo; pcibr_info_h pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos; @@ -1283,7 +1611,8 @@ * strict count, the excess counts are not a * problem. */ - for (cs = 0; cs < 8; ++cs) { + for (cs = pcibr_soft->bs_min_slot; + cs < PCIBR_NUM_SLOTS(pcibr_soft); ++cs) { int nf = pcibr_soft->bs_slot[cs].bss_ninfo; pcibr_info_h pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos; @@ -1313,7 +1642,7 @@ wx = PCIIO_SPACE_MEM; wl = wb + ws; if ((wx == raw_space) && (raw_paddr >= wb) && (raw_paddr < wl)) { - atomicAddInt(map->bp_toc, 1); + atomic_inc(&map->bp_toc[0]); if (slot == PCIIO_SLOT_NONE) { slot = cs; space = map->bp_space; @@ -1325,15 +1654,21 @@ } } + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ERROR_HDLR, pcibr_soft->bs_conn, + "pcibr_pioerror: offset=0x%x, slot=0x%x, func=0x%x\n", + offset, slot, func)); + if (space != PCIIO_SPACE_NONE) { - if (slot != PCIIO_SLOT_NONE) - if (func != PCIIO_FUNC_NONE) + if (slot != PCIIO_SLOT_NONE) { + if (func != PCIIO_FUNC_NONE) { IOERROR_SETVALUE(ioe, widgetdev, pciio_widgetdev_create(slot,func)); - else + } + else { IOERROR_SETVALUE(ioe, widgetdev, pciio_widgetdev_create(slot,0)); - + } + } IOERROR_SETVALUE(ioe, busspace, space); IOERROR_SETVALUE(ioe, busaddr, offset); } @@ -1360,7 +1695,7 @@ if (space == PCIIO_SPACE_NONE) { printk("XIO Bus Error at %s\n" - "\taccess to XIO bus offset 0x%x\n" + "\taccess to XIO bus offset 0x%lx\n" "\tdoes not correspond to any PCI address\n", pcibr_soft->bs_name, bad_xaddr); @@ -1434,17 +1769,21 @@ */ BEM_ADD_STR("Raw info from Bridge/PCI layer:\n"); - if (bridge->b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) - pcibr_error_dump(pcibr_soft); + if (IS_PIC_SOFT(pcibr_soft)) { + if (bridge->p_int_status_64 & (picreg_t)BRIDGE_ISR_PCIBUS_PIOERR) + pcibr_error_dump(pcibr_soft); + } else { + if (bridge->b_int_status & (bridgereg_t)BRIDGE_ISR_PCIBUS_PIOERR) + pcibr_error_dump(pcibr_soft); + } BEM_ADD_SPC(raw_space); BEM_ADD_VAR(raw_paddr); if (IOERROR_FIELDVALID(ioe, widgetdev)) { - - slot = pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, - widgetdev)); - func = pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, - widgetdev)); - if (slot < 8) { + short widdev; + IOERROR_GETVALUE(widdev, ioe, widgetdev); + slot = pciio_widgetdev_slot_get(widdev); + func = pciio_widgetdev_func_get(widdev); + if (slot < PCIBR_NUM_SLOTS(pcibr_soft)) { bridgereg_t device = bridge->b_device[slot].reg; BEM_ADD_VAR(slot); @@ -1472,11 +1811,12 @@ * Need a way to ensure we don't inadvertently clear some * other errors. */ - if (IOERROR_FIELDVALID(ioe, widgetdev)) - pcibr_device_disable(pcibr_soft, - pciio_widgetdev_slot_get( - IOERROR_GETVALUE(ioe, widgetdev))); - + if (IOERROR_FIELDVALID(ioe, widgetdev)) { + short widdev; + IOERROR_GETVALUE(widdev, ioe, widgetdev); + pcibr_device_disable(pcibr_soft, + pciio_widgetdev_slot_get(widdev)); + } if (mode == MODE_DEVUSERERROR) pcibr_error_cleanup(pcibr_soft, error_code); } @@ -1490,8 +1830,6 @@ * and try to invoke the appropriate bus service to handle this. */ -#define BRIDGE_DMA_READ_ERROR (BRIDGE_ISR_RESP_XTLK_ERR|BRIDGE_ISR_XREAD_REQ_TIMEOUT) - int pcibr_dmard_error( pcibr_soft_t pcibr_soft, @@ -1511,7 +1849,11 @@ * Look up the address, in the bridge error registers, and * take appropriate action */ - ASSERT(IOERROR_GETVALUE(ioe, widgetnum) == pcibr_soft->bs_xid); + { + short tmp; + IOERROR_GETVALUE(tmp, ioe, widgetnum); + ASSERT(tmp == pcibr_soft->bs_xid); + } ASSERT(bridge); /* @@ -1540,10 +1882,11 @@ */ retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe); - if (retval != IOERROR_HANDLED) - pcibr_device_disable(pcibr_soft, - pciio_widgetdev_slot_get( - IOERROR_GETVALUE(ioe,widgetdev))); + if (retval != IOERROR_HANDLED) { + short tmp; + IOERROR_GETVALUE(tmp, ioe, widgetdev); + pcibr_device_disable(pcibr_soft, pciio_widgetdev_slot_get(tmp)); + } /* * Re-enable bridge to interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR @@ -1609,10 +1952,10 @@ retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe); if (retval != IOERROR_HANDLED) { - pcibr_device_disable(pcibr_soft, - pciio_widgetdev_slot_get( - IOERROR_GETVALUE(ioe, widgetdev))); + short tmp; + IOERROR_GETVALUE(tmp, ioe, widgetdev); + pcibr_device_disable(pcibr_soft, pciio_widgetdev_slot_get(tmp)); } return retval; } @@ -1646,6 +1989,10 @@ pcibr_soft = (pcibr_soft_t) einfo; + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ERROR_HDLR, pcibr_soft->bs_conn, + "pcibr_error_handler: pcibr_soft=0x%x, error_code=0x%x\n", + pcibr_soft, error_code)); + #ifdef EHE_ENABLE xconn_vhdl = pcibr_soft->bs_conn; pcibr_vhdl = pcibr_soft->bs_vhdl; @@ -1664,7 +2011,7 @@ #endif /* EHE_ENABLE */ #if DEBUG && ERROR_DEBUG - printk("%s: pcibr_error_handler\n", pcibr_soft->bs_name); + printk( "%s: pcibr_error_handler\n", pcibr_soft->bs_name); #endif ASSERT(pcibr_soft != NULL); @@ -1704,6 +2051,159 @@ } /* + * PIC has 2 busses under a single widget so pcibr_attach2 registers this + * wrapper function rather than pcibr_error_handler() for PIC. It's upto + * this wrapper to call pcibr_error_handler() with the correct pcibr_soft + * struct (ie. the pcibr_soft struct for the bus that saw the error). + * + * NOTE: this wrapper function is only registered for PIC ASICs and will + * only be called for a PIC + */ +int +pcibr_error_handler_wrapper( + error_handler_arg_t einfo, + int error_code, + ioerror_mode_t mode, + ioerror_t *ioe) +{ + pcibr_soft_t pcibr_soft = (pcibr_soft_t) einfo; + int pio_retval = -1; + int dma_retval = -1; + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_ERROR_HDLR, pcibr_soft->bs_conn, + "pcibr_error_handler_wrapper: pcibr_soft=0x%x, " + "error_code=0x%x\n", pcibr_soft, error_code)); + + /* + * It is possible that both a IOECODE_PIO and a IOECODE_DMA, and both + * IOECODE_READ and IOECODE_WRITE could be set in error_code so we must + * process all. Since we are a wrapper for pcibr_error_handler(), and + * will be calling it several times within this routine, we turn off the + * error_code bits we don't want it to be processing during that call. + */ + /* + * If the error was a result of a PIO, we tell what bus on the PIC saw + * the error from the PIO address. + */ + +#if 0 + if (mode == MODE_DEVPROBE) + pio_retval = IOERROR_HANDLED; + else { +#endif + if (error_code & IOECODE_PIO) { + iopaddr_t bad_xaddr; + /* + * PIC bus0 PIO space 0x000000 - 0x7fffff or 0x40000000 - 0xbfffffff + * bus1 PIO space 0x800000 - 0xffffff or 0xc0000000 - 0x13fffffff + */ + IOERROR_GETVALUE(bad_xaddr, ioe, xtalkaddr); + if ((bad_xaddr <= 0x7fffff) || + ((bad_xaddr >= 0x40000000) && (bad_xaddr <= 0xbfffffff))) { + /* bus 0 saw the error */ + pio_retval = pcibr_error_handler((error_handler_arg_t)pcibr_soft, + (error_code & ~IOECODE_DMA), mode, ioe); + } else if (((bad_xaddr >= 0x800000) && (bad_xaddr <= 0xffffff)) || + ((bad_xaddr >= 0xc0000000) && (bad_xaddr <= 0x13fffffff))) { + /* bus 1 saw the error */ + pcibr_soft = pcibr_soft->bs_peers_soft; + if (!pcibr_soft) { +#if DEBUG + printk(KERN_WARNING "pcibr_error_handler: " + "bs_peers_soft==NULL. bad_xaddr= 0x%x mode= 0x%x\n", + bad_xaddr, mode); +#endif + pio_retval = IOERROR_HANDLED; + } else + pio_retval= pcibr_error_handler((error_handler_arg_t)pcibr_soft, + (error_code & ~IOECODE_DMA), mode, ioe); + } else { + printk(KERN_WARNING "pcibr_error_handler_wrapper(): IOECODE_PIO: " + "saw an invalid pio address: 0x%lx\n", bad_xaddr); + pio_retval = IOERROR_UNHANDLED; + } + } +#if 0 + } /* MODE_DEVPROBE */ +#endif + + /* + * If the error was a result of a DMA Write, we tell what bus on the PIC + * saw the error by looking at tnum. + */ + if ((error_code & IOECODE_DMA) && (error_code & IOECODE_WRITE)) { + short tmp; + /* + * For DMA writes [X]Bridge encodes the TNUM field of a Xtalk + * packet like this: + * bits value + * 4:3 10b + * 2:0 device number + * + * BUT PIC needs the bus number so it does this: + * bits value + * 4:3 10b + * 2 busnumber + * 1:0 device number + * + * Pull out the bus number from `tnum' and reset the `widgetdev' + * since when hubiio_crb_error_handler() set `widgetdev' it had + * no idea if it was a PIC or a BRIDGE ASIC so it set it based + * off bits 2:0 + */ + IOERROR_GETVALUE(tmp, ioe, tnum); + IOERROR_SETVALUE(ioe, widgetdev, (tmp & 0x3)); + if ((tmp & 0x4) == 0) { + /* bus 0 saw the error. */ + dma_retval = pcibr_error_handler((error_handler_arg_t)pcibr_soft, + (error_code & ~(IOECODE_PIO|IOECODE_READ)), mode, ioe); + } else { + /* bus 1 saw the error */ + pcibr_soft = pcibr_soft->bs_peers_soft; + dma_retval = pcibr_error_handler((error_handler_arg_t)pcibr_soft, + (error_code & ~(IOECODE_PIO|IOECODE_READ)), mode, ioe); + } + } + + /* + * If the error was a result of a DMA READ, XXX ??? + */ + if ((error_code & IOECODE_DMA) && (error_code & IOECODE_READ)) { + /* + * A DMA Read error will result in a BRIDGE_ISR_RESP_XTLK_ERR + * or BRIDGE_ISR_BAD_XRESP_PKT bridge error interrupt which + * are fatal interrupts (ie. BRIDGE_ISR_ERROR_FATAL) causing + * pcibr_error_intr_handler() to panic the system. So is the + * error handler even going to get called??? It appears that + * the pcibr_dmard_error() attempts to clear the interrupts + * so pcibr_error_intr_handler() won't see them, but there + * appears to be nothing to prevent pcibr_error_intr_handler() + * from running before pcibr_dmard_error() has a chance to + * clear the interrupt. + * + * Since we'll be panicing anyways, don't bother handling the + * error for now until we can fix this race condition mentioned + * above. + */ + dma_retval = IOERROR_UNHANDLED; + } + + /* XXX: pcibr_error_handler() should probably do the same thing, it over- + * write it's return value as it processes the different "error_code"s. + */ + if ((pio_retval == -1) && (dma_retval == -1)) { + return IOERROR_BADERRORCODE; + } else if (dma_retval != IOERROR_HANDLED) { + return dma_retval; + } else if (pio_retval != IOERROR_HANDLED) { + return pio_retval; + } else { + return IOERROR_HANDLED; + } +} + + +/* * Reenable a device after handling the error. * This is called by the lower layers when they wish to be reenabled * after an error. @@ -1715,7 +2215,7 @@ pcibr_error_devenable(devfs_handle_t pconn_vhdl, int error_code) { pciio_info_t pciio_info = pciio_info_get(pconn_vhdl); - pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info); + pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info); ASSERT(error_code & IOECODE_PIO); diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c Wed Jan 15 16:57:29 2003 @@ -85,11 +85,9 @@ if (hint) hint->ph_rrb_fixed = mask; -#if DEBUG else - printk("pcibr_hints_fix_rrbs: pcibr_hints_get failed at\n" - "\t%p\n", xconn_vhdl); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_HINTS, xconn_vhdl, + "pcibr_hints_fix_rrbs: pcibr_hints_get failed\n")); } void @@ -107,11 +105,9 @@ if (hint) hint->ph_host_slot[guest] = host + 1; -#if DEBUG else - printk("pcibr_hints_dualslot: pcibr_hints_get failed at\n" - "\t%p\n", xconn_vhdl); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_HINTS, xconn_vhdl, + "pcibr_hints_dualslot: pcibr_hints_get failed\n")); } void @@ -122,11 +118,9 @@ if (hint) hint->ph_intr_bits = xxx_intr_bits; -#if DEBUG else - printk("pcibr_hints_intr_bits: pcibr_hints_get failed at\n" - "\t%p\n", xconn_vhdl); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_HINTS, xconn_vhdl, + "pcibr_hints_intr_bits: pcibr_hints_get failed\n")); } void @@ -145,11 +139,9 @@ if (hint) hint->ph_hands_off = 1; -#if DEBUG else - printk("pcibr_hints_handsoff: pcibr_hints_get failed at\n" - "\t%p\n", xconn_vhdl); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_HINTS, xconn_vhdl, + "pcibr_hints_handsoff: pcibr_hints_get failed\n")); } void @@ -161,13 +153,11 @@ char sdname[16]; devfs_handle_t pconn_vhdl = GRAPH_VERTEX_NONE; - sprintf(sdname, "pci/%d", slot); + sprintf(sdname, "%s/%d", EDGE_LBL_PCI, slot); (void) hwgraph_path_add(xconn_vhdl, sdname, &pconn_vhdl); if (pconn_vhdl == GRAPH_VERTEX_NONE) { -#if DEBUG - printk("pcibr_hints_subdevs: hwgraph_path_create failed at\n" - "\t%p (seeking %s)\n", xconn_vhdl, sdname); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_HINTS, xconn_vhdl, + "pcibr_hints_subdevs: hwgraph_path_create failed\n")); return; } hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo); @@ -176,10 +166,8 @@ NEW(subdevp); if (!subdevp) { -#if DEBUG - printk("pcibr_hints_subdevs: subdev ptr alloc failed at\n" - "\t%p\n", pconn_vhdl); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_HINTS, xconn_vhdl, + "pcibr_hints_subdevs: subdev ptr alloc failed\n")); return; } *subdevp = subdevs; @@ -189,16 +177,12 @@ return; DEL(subdevp); if (ainfo == (arbitrary_info_t) NULL) { -#if DEBUG - printk("pcibr_hints_subdevs: null subdevs ptr at\n" - "\t%p\n", pconn_vhdl); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_HINTS, xconn_vhdl, + "pcibr_hints_subdevs: null subdevs ptr\n")); return; } -#if DEBUG - printk("pcibr_subdevs_get: dup subdev add_LBL at\n" - "\t%p\n", pconn_vhdl); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_HINTS, xconn_vhdl, + "pcibr_subdevs_get: dup subdev add_LBL\n")); } *(uint64_t *) ainfo = subdevs; } diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c Wed Jan 15 16:57:29 2003 @@ -4,11 +4,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved. */ #include -#include #include #include #include @@ -39,11 +38,11 @@ #define rmalloc atealloc #endif -unsigned pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines); +unsigned pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines, int nslots); pcibr_intr_t pcibr_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t); void pcibr_intr_free(pcibr_intr_t); void pcibr_setpciint(xtalk_intr_t); -int pcibr_intr_connect(pcibr_intr_t); +int pcibr_intr_connect(pcibr_intr_t, intr_func_t, intr_arg_t); void pcibr_intr_disconnect(pcibr_intr_t); devfs_handle_t pcibr_intr_cpu_get(pcibr_intr_t); @@ -58,9 +57,9 @@ unsigned pcibr_intr_bits(pciio_info_t info, - pciio_intr_line_t lines) + pciio_intr_line_t lines, int nslots) { - pciio_slot_t slot = pciio_info_slot_get(info); + pciio_slot_t slot = PCIBR_INFO_SLOT_GET_INT(info); unsigned bbits = 0; /* @@ -79,7 +78,7 @@ * 7 7 3 7 3 */ - if (slot < 8) { + if (slot < nslots) { if (lines & (PCIIO_INTR_LINE_A| PCIIO_INTR_LINE_C)) bbits |= 1 << slot; if (lines & (PCIIO_INTR_LINE_B| PCIIO_INTR_LINE_D)) @@ -165,20 +164,26 @@ * to check if a specific Bridge b_int_status bit is set, and if so, * cause the setting of the corresponding interrupt bit. * - * On a XBridge (IP35), we do this by writing the appropriate Bridge Force - * Interrupt register. + * On a XBridge (SN1), we do this by writing the appropriate Bridge Force + * Interrupt register. On SN0, or SN1 with an older Bridge, the Bridge + * Force Interrupt register does not exist, so we write the Hub + * INT_PEND_MOD register directly. Likewise for Octane, where we write the + * Heart Set Interrupt Status register directly. */ void pcibr_force_interrupt(pcibr_intr_wrap_t wrap) { +#ifdef PIC_LATER unsigned bit; pcibr_soft_t pcibr_soft = wrap->iw_soft; bridge_t *bridge = pcibr_soft->bs_base; - cpuid_t cpuvertex_to_cpuid(devfs_handle_t vhdl); - bit = wrap->iw_intr; + bit = wrap->iw_ibit; - if (pcibr_soft->bs_xbridge) { + PCIBR_DEBUG((PCIBR_DEBUG_INTR, pcibr_soft->bs_vhdl, + "pcibr_force_interrupt: bit=0x%x\n", bit)); + + if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) { bridge->b_force_pin[bit].intr = 1; } else if ((1 << bit) & *wrap->iw_stat) { cpuid_t cpu; @@ -187,11 +192,10 @@ pcibr_soft->bs_intr[bit].bsi_xtalk_intr; intr_bit = (short) xtalk_intr_vector_get(xtalk_intr); - cpu = cpuvertex_to_cpuid(xtalk_intr_cpu_get(xtalk_intr)); -#if defined(CONFIG_IA64_SGI_SN1) + cpu = xtalk_intr_cpuid_get(xtalk_intr); REMOTE_CPU_SEND_INTR(cpu, intr_bit); -#endif } +#endif /* PIC_LATER */ } /*ARGSUSED */ @@ -202,12 +206,11 @@ devfs_handle_t owner_dev) { pcibr_info_t pcibr_info = pcibr_info_get(pconn_vhdl); - pciio_slot_t pciio_slot = pcibr_info->f_slot; + pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pcibr_info); pcibr_soft_t pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast; devfs_handle_t xconn_vhdl = pcibr_soft->bs_conn; bridge_t *bridge = pcibr_soft->bs_base; int is_threaded = 0; - int thread_swlevel; xtalk_intr_t *xtalk_intr_p; pcibr_intr_t *pcibr_intr_p; @@ -222,41 +225,32 @@ pcibr_intr_list_t intr_list; bridgereg_t int_dev; -#if DEBUG && INTR_DEBUG - printk("%v: pcibr_intr_alloc\n" - "%v:%s%s%s%s%s\n", - owner_dev, pconn_vhdl, - !(lines & 15) ? " No INTs?" : "", - lines & 1 ? " INTA" : "", - lines & 2 ? " INTB" : "", - lines & 4 ? " INTC" : "", - lines & 8 ? " INTD" : ""); -#endif + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pconn_vhdl, + "pcibr_intr_alloc: %s%s%s%s%s\n", + !(lines & 15) ? " No INTs?" : "", + lines & 1 ? " INTA" : "", + lines & 2 ? " INTB" : "", + lines & 4 ? " INTC" : "", + lines & 8 ? " INTD" : "")); NEW(pcibr_intr); if (!pcibr_intr) return NULL; - if (dev_desc) { - cpuid_t intr_target_from_desc(device_desc_t, int); - } else { - extern int default_intr_pri; - - is_threaded = 1; /* PCI interrupts are threaded, by default */ - thread_swlevel = default_intr_pri; - } - pcibr_intr->bi_dev = pconn_vhdl; pcibr_intr->bi_lines = lines; pcibr_intr->bi_soft = pcibr_soft; pcibr_intr->bi_ibits = 0; /* bits will be added below */ + pcibr_intr->bi_func = 0; /* unset until connect */ + pcibr_intr->bi_arg = 0; /* unset until connect */ pcibr_intr->bi_flags = is_threaded ? 0 : PCIIO_INTR_NOTHREAD; pcibr_intr->bi_mustruncpu = CPU_NONE; pcibr_intr->bi_ibuf.ib_in = 0; pcibr_intr->bi_ibuf.ib_out = 0; mutex_spinlock_init(&pcibr_intr->bi_ibuf.ib_lock); - - pcibr_int_bits = pcibr_soft->bs_intr_bits((pciio_info_t)pcibr_info, lines); + pcibr_int_bits = pcibr_soft->bs_intr_bits((pciio_info_t)pcibr_info, lines, + PCIBR_NUM_SLOTS(pcibr_soft)); /* @@ -265,9 +259,8 @@ * to, and make sure there are xtalk resources * allocated for it. */ -#if DEBUG && INTR_DEBUG - printk("pcibr_int_bits: 0x%X\n", pcibr_int_bits); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pconn_vhdl, + "pcibr_intr_alloc: pcibr_int_bits: 0x%x\n", pcibr_int_bits)); for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit ++) { if (pcibr_int_bits & (1 << pcibr_int_bit)) { xtalk_intr_p = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr; @@ -282,10 +275,9 @@ * ordering problems with DMA, completion interrupts, and error * interrupts. (Use of xconn_vhdl forces this.) * - * 2) On IP35, addressing constraints on IP35 and Bridge force + * 2) On SN1, addressing constraints on SN1 and Bridge force * us to use a single PI number for all interrupts from a - * single Bridge. (IP35-specific code forces this, and we - * verify in pcibr_setwidint.) + * single Bridge. (SN1-specific code forces this). */ /* @@ -298,9 +290,9 @@ */ xtalk_intr = xtalk_intr_alloc_nothd(xconn_vhdl, dev_desc, owner_dev); -#if DEBUG && INTR_DEBUG - printk("%v: xtalk_intr=0x%X\n", xconn_vhdl, xtalk_intr); -#endif + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pconn_vhdl, + "pcibr_intr_alloc: xtalk_intr=0x%x\n", xtalk_intr)); /* both an assert and a runtime check on this: * we need to check in non-DEBUG kernels, and @@ -338,10 +330,9 @@ int_dev |= pciio_slot << BRIDGE_INT_DEV_SHFT(pcibr_int_bit); bridge->b_int_device = int_dev; /* XXXMP */ -#if DEBUG && INTR_DEBUG - printk("%v: bridge intr bit %d clears my wrb\n", - pconn_vhdl, pcibr_int_bit); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pconn_vhdl, + "bridge intr bit %d clears my wrb\n", + pcibr_int_bit)); } else { /* someone else got one allocated first; * free the one we just created, and @@ -373,25 +364,17 @@ intr_entry->il_wrbf = &(bridge->b_wr_req_buf[pciio_slot].reg); intr_list_p = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list; -#if DEBUG && INTR_DEBUG -#if defined(SUPPORT_PRINTING_V_FORMAT) - printk("0x%x: Bridge bit %d wrap=0x%x\n", - pconn_vhdl, pcibr_int_bit, - pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap); -#else - printk("%v: Bridge bit %d wrap=0x%x\n", - pconn_vhdl, pcibr_int_bit, - pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap); -#endif -#endif + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pconn_vhdl, + "Bridge bit 0x%x wrap=0x%x\n", pcibr_int_bit, + pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap)); if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) { /* we are the first interrupt on this bridge bit. */ -#if DEBUG && INTR_DEBUG - printk("%v INT 0x%x (bridge bit %d) allocated [FIRST]\n", - pconn_vhdl, pcibr_int_bits, pcibr_int_bit); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pconn_vhdl, + "INT 0x%x (bridge bit %d) allocated [FIRST]\n", + pcibr_int_bits, pcibr_int_bit)); continue; } intr_list = *intr_list_p; @@ -402,10 +385,9 @@ * don't need our intr_entry. */ DEL(intr_entry); -#if DEBUG && INTR_DEBUG - printk("%v INT 0x%x (bridge bit %d) replaces erased first\n", - pconn_vhdl, pcibr_int_bits, pcibr_int_bit); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pconn_vhdl, + "INT 0x%x (bridge bit %d) replaces erased first\n", + pcibr_int_bits, pcibr_int_bit)); continue; } intr_list_p = &intr_list->il_next; @@ -413,10 +395,9 @@ /* we are the new second interrupt on this bit. */ pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared = 1; -#if DEBUG && INTR_DEBUG - printk("%v INT 0x%x (bridge bit %d) is new SECOND\n", - pconn_vhdl, pcibr_int_bits, pcibr_int_bit); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pconn_vhdl, + "INT 0x%x (bridge bit %d) is new SECOND\n", + pcibr_int_bits, pcibr_int_bit)); continue; } while (1) { @@ -427,20 +408,19 @@ * don't need our intr_entry. */ DEL(intr_entry); -#if DEBUG && INTR_DEBUG - printk("%v INT 0x%x (bridge bit %d) replaces erased Nth\n", - pconn_vhdl, pcibr_int_bits, pcibr_int_bit); -#endif + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pconn_vhdl, + "INT 0x%x (bridge bit %d) replaces erase Nth\n", + pcibr_int_bits, pcibr_int_bit)); break; } intr_list_p = &intr_list->il_next; if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) { /* entry appended to share list */ -#if DEBUG && INTR_DEBUG - printk("%v INT 0x%x (bridge bit %d) is new Nth\n", - pconn_vhdl, pcibr_int_bits, pcibr_int_bit); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pconn_vhdl, + "INT 0x%x (bridge bit %d) is new Nth\n", + pcibr_int_bits, pcibr_int_bit)); break; } /* step to next record in chain @@ -479,10 +459,11 @@ if (compare_and_swap_ptr((void **) &intr_list->il_intr, pcibr_intr, NULL)) { -#if DEBUG && INTR_DEBUG - printk("%s: cleared a handler from bit %d\n", - pcibr_soft->bs_name, pcibr_int_bit); -#endif + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, + pcibr_intr->bi_dev, + "pcibr_intr_free: cleared hdlr from bit 0x%x\n", + pcibr_int_bit)); } /* If this interrupt line is not being shared between multiple * devices release the xtalk interrupt resources. @@ -515,34 +496,49 @@ void pcibr_setpciint(xtalk_intr_t xtalk_intr) { - iopaddr_t addr = xtalk_intr_addr_get(xtalk_intr); - xtalk_intr_vector_t vect = xtalk_intr_vector_get(xtalk_intr); - bridgereg_t *int_addr = (bridgereg_t *) - xtalk_intr_sfarg_get(xtalk_intr); - - *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) | - (BRIDGE_INT_ADDR_FLD & vect)); + iopaddr_t addr; + xtalk_intr_vector_t vect; + devfs_handle_t vhdl; + bridge_t *bridge; + + addr = xtalk_intr_addr_get(xtalk_intr); + vect = xtalk_intr_vector_get(xtalk_intr); + vhdl = xtalk_intr_dev_get(xtalk_intr); + bridge = (bridge_t *)xtalk_piotrans_addr(vhdl, 0, 0, sizeof(bridge_t), 0); + + if (is_pic(bridge)) { + picreg_t *int_addr; + int_addr = (picreg_t *)xtalk_intr_sfarg_get(xtalk_intr); + *int_addr = ((PIC_INT_ADDR_FLD & ((uint64_t)vect << 48)) | + (PIC_INT_ADDR_HOST & addr)); + } else { + bridgereg_t *int_addr; + int_addr = (bridgereg_t *)xtalk_intr_sfarg_get(xtalk_intr); + *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) | + (BRIDGE_INT_ADDR_FLD & vect)); + } } /*ARGSUSED */ int -pcibr_intr_connect(pcibr_intr_t pcibr_intr) +pcibr_intr_connect(pcibr_intr_t pcibr_intr, intr_func_t intr_func, intr_arg_t intr_arg) { pcibr_soft_t pcibr_soft = pcibr_intr->bi_soft; bridge_t *bridge = pcibr_soft->bs_base; unsigned pcibr_int_bits = pcibr_intr->bi_ibits; unsigned pcibr_int_bit; - bridgereg_t b_int_enable; + uint64_t int_enable; unsigned long s; if (pcibr_intr == NULL) return -1; -#if DEBUG && INTR_DEBUG - printk("%v: pcibr_intr_connect\n", - pcibr_intr->bi_dev); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pcibr_intr->bi_dev, + "pcibr_intr_connect: intr_func=0x%x\n", + pcibr_intr)); + pcibr_intr->bi_func = intr_func; + pcibr_intr->bi_arg = intr_arg; *((volatile unsigned *)&pcibr_intr->bi_flags) |= PCIIO_INTR_CONNECTED; /* @@ -553,9 +549,12 @@ */ for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++) if (pcibr_int_bits & (1 << pcibr_int_bit)) { + pcibr_intr_wrap_t intr_wrap; xtalk_intr_t xtalk_intr; + void *int_addr; xtalk_intr = pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr; + intr_wrap = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap; /* * If this interrupt line is being shared and the connect has @@ -569,21 +568,43 @@ * Use the pcibr wrapper function to handle all Bridge interrupts * regardless of whether the interrupt line is shared or not. */ - xtalk_intr_connect(xtalk_intr, (xtalk_intr_setfunc_t) pcibr_setpciint, - (void *)&(bridge->b_int_addr[pcibr_int_bit].addr)); + if (IS_PIC_SOFT(pcibr_soft)) + int_addr = (void *)&(bridge->p_int_addr_64[pcibr_int_bit]); + else + int_addr = (void *)&(bridge->b_int_addr[pcibr_int_bit].addr); + + xtalk_intr_connect(xtalk_intr, pcibr_intr_func, (intr_arg_t) intr_wrap, + (xtalk_intr_setfunc_t) pcibr_setpciint, + (void *)int_addr); + pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 1; -#if DEBUG && INTR_DEBUG - printk("%v bridge bit %d wrapper connected\n", - pcibr_intr->bi_dev, pcibr_int_bit); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pcibr_intr->bi_dev, + "pcibr_setpciint: int_addr=0x%x, *int_addr=0x%x, " + "pcibr_int_bit=0x%x\n", int_addr, + (is_pic(bridge) ? + *(picreg_t *)int_addr : *(bridgereg_t *)int_addr), + pcibr_int_bit)); } - s = pcibr_lock(pcibr_soft); - b_int_enable = bridge->b_int_enable; - b_int_enable |= pcibr_int_bits; - bridge->b_int_enable = b_int_enable; - bridge->b_wid_tflush; /* wait until Bridge PIO complete */ - pcibr_unlock(pcibr_soft, s); + + /* PIC WAR. PV# 854697 + * On PIC we must write 64-bit MMRs with 64-bit stores + */ + s = pcibr_lock(pcibr_soft); + if (IS_PIC_SOFT(pcibr_soft) && + PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) { + int_enable = bridge->p_int_enable_64; + int_enable |= pcibr_int_bits; + bridge->p_int_enable_64 = int_enable; + } else { + bridgereg_t int_enable; + + int_enable = bridge->b_int_enable; + int_enable |= pcibr_int_bits; + bridge->b_int_enable = int_enable; + } + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + pcibr_unlock(pcibr_soft, s); return 0; } @@ -596,13 +617,15 @@ bridge_t *bridge = pcibr_soft->bs_base; unsigned pcibr_int_bits = pcibr_intr->bi_ibits; unsigned pcibr_int_bit; - bridgereg_t b_int_enable; + pcibr_intr_wrap_t intr_wrap; + uint64_t int_enable; unsigned long s; /* Stop calling the function. Now. */ *((volatile unsigned *)&pcibr_intr->bi_flags) &= ~PCIIO_INTR_CONNECTED; - + pcibr_intr->bi_func = 0; + pcibr_intr->bi_arg = 0; /* * For each PCI interrupt line requested, figure * out which Bridge PCI Interrupt Line it maps @@ -619,15 +642,30 @@ if (!pcibr_int_bits) return; + /* PIC WAR. PV# 854697 + * On PIC we must write 64-bit MMRs with 64-bit stores + */ s = pcibr_lock(pcibr_soft); - b_int_enable = bridge->b_int_enable; - b_int_enable &= ~pcibr_int_bits; - bridge->b_int_enable = b_int_enable; + if (IS_PIC_SOFT(pcibr_soft) && PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) { + int_enable = bridge->p_int_enable_64; + int_enable &= ~pcibr_int_bits; + bridge->p_int_enable_64 = int_enable; + } else { + int_enable = (uint64_t)bridge->b_int_enable; + int_enable &= ~pcibr_int_bits; + bridge->b_int_enable = (bridgereg_t)int_enable; + } bridge->b_wid_tflush; /* wait until Bridge PIO complete */ pcibr_unlock(pcibr_soft, s); + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pcibr_intr->bi_dev, + "pcibr_intr_disconnect: disabled int_bits=0x%x\n", + pcibr_int_bits)); + for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++) if (pcibr_int_bits & (1 << pcibr_int_bit)) { + void *int_addr; + /* if the interrupt line is now shared, * do not disconnect it. */ @@ -637,10 +675,9 @@ xtalk_intr_disconnect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr); pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 0; -#if DEBUG && INTR_DEBUG - printk("%s: xtalk disconnect done for Bridge bit %d\n", - pcibr_soft->bs_name, pcibr_int_bit); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pcibr_intr->bi_dev, + "pcibr_intr_disconnect: disconnect int_bits=0x%x\n", + pcibr_int_bits)); /* if we are sharing the interrupt line, * connect us up; this closes the hole @@ -650,9 +687,22 @@ if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared) continue; + intr_wrap = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap; + if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared) + continue; + + if (IS_PIC_SOFT(pcibr_soft)) + int_addr = (void *)&(bridge->p_int_addr_64[pcibr_int_bit]); + else + int_addr = (void *)&(bridge->b_int_addr[pcibr_int_bit].addr); + xtalk_intr_connect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr, + pcibr_intr_func, (intr_arg_t) intr_wrap, (xtalk_intr_setfunc_t)pcibr_setpciint, - (void *) &(bridge->b_int_addr[pcibr_int_bit].addr)); + (void *)pcibr_int_bit); + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_INTR_ALLOC, pcibr_intr->bi_dev, + "pcibr_intr_disconnect: now-sharing int_bits=0x%x\n", + pcibr_int_bit)); } } @@ -729,6 +779,10 @@ bridge->b_wid_int_upper = NEW_b_wid_int_upper; bridge->b_wid_int_lower = NEW_b_wid_int_lower; bridge->b_int_host_err = vect; + +printk("pcibr_setwidint: b_wid_int_upper 0x%x b_wid_int_lower 0x%x b_int_host_err 0x%x\n", + NEW_b_wid_int_upper, NEW_b_wid_int_lower, vect); + } /* @@ -752,6 +806,9 @@ XTALK_ADDR_TO_UPPER(addr)); bridge->b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr); bridge->b_int_host_err = vect; +printk("pcibr_xintr_preset: b_wid_int_upper 0x%lx b_wid_int_lower 0x%lx b_int_host_err 0x%x\n", + ( (0x000F0000 & (targ << 16)) | XTALK_ADDR_TO_UPPER(addr)), + XTALK_ADDR_TO_LOWER(addr), vect); /* turn on all interrupts except * the PCI interrupt requests, @@ -794,12 +851,37 @@ { pcibr_intr_wrap_t wrap = (pcibr_intr_wrap_t) arg; reg_p wrbf; + intr_func_t func; pcibr_intr_t intr; pcibr_intr_list_t list; int clearit; int do_nonthreaded = 1; int is_threaded = 0; int x = 0; + pcibr_soft_t pcibr_soft = wrap->iw_soft; + bridge_t *bridge = pcibr_soft->bs_base; + uint64_t p_enable = pcibr_soft->bs_int_enable; + int bit = wrap->iw_ibit; + + /* + * PIC WAR. PV#855272 + * Early attempt at a workaround for the runaway + * interrupt problem. Briefly disable the enable bit for + * this device. + */ + if (IS_PIC_SOFT(pcibr_soft) && + PCIBR_WAR_ENABLED(PV855272, pcibr_soft)) { + unsigned s; + + /* disable-enable interrupts for this bridge pin */ + + p_enable &= ~(1 << bit); + s = pcibr_lock(pcibr_soft); + bridge->p_int_enable_64 = p_enable; + p_enable |= (1 << bit); + bridge->p_int_enable_64 = p_enable; + pcibr_unlock(pcibr_soft, s); + } /* * If any handler is still running from a previous interrupt @@ -821,35 +903,31 @@ clearit = 1; while (do_nonthreaded) { for (list = wrap->iw_list; list != NULL; list = list->il_next) { - if ((intr = list->il_intr) && - (intr->bi_flags & PCIIO_INTR_CONNECTED)) { + if ((intr = list->il_intr) && (intr->bi_flags & PCIIO_INTR_CONNECTED)) { - /* - * This device may have initiated write - * requests since the bridge last saw - * an edge on this interrupt input; flushing - * the buffer prior to invoking the handler - * should help but may not be sufficient if we - * get more requests after the flush, followed - * by the card deciding it wants service, before - * the interrupt handler checks to see if things need - * to be done. - * - * There is a similar race condition if - * an interrupt handler loops around and - * notices further service is required. - * Perhaps we need to have an explicit - * call that interrupt handlers need to - * do between noticing that DMA to memory - * has completed, but before observing the - * contents of memory? - */ - - if ((do_nonthreaded) && (!is_threaded)) { - /* Non-threaded. - * Call the interrupt handler at interrupt level - */ + /* + * This device may have initiated write + * requests since the bridge last saw + * an edge on this interrupt input; flushing + * the buffer prior to invoking the handler + * should help but may not be sufficient if we + * get more requests after the flush, followed + * by the card deciding it wants service, before + * the interrupt handler checks to see if things need + * to be done. + * + * There is a similar race condition if + * an interrupt handler loops around and + * notices further service is required. + * Perhaps we need to have an explicit + * call that interrupt handlers need to + * do between noticing that DMA to memory + * has completed, but before observing the + * contents of memory? + */ + if ((do_nonthreaded) && (!is_threaded)) { + /* Non-threaded - Call the interrupt handler at interrupt level */ /* Only need to flush write buffers if sharing */ if ((wrap->iw_shared) && (wrbf = list->il_wrbf)) { @@ -864,21 +942,23 @@ (void *)list->il_intr->bi_dev, (long) wrbf); #endif } + func = intr->bi_func; + if ( func ) + func(intr->bi_arg); } - clearit = 0; } } + do_nonthreaded = 0; - do_nonthreaded = 0; - /* - * If the non-threaded handler was the last to complete, - * (i.e., no threaded handlers still running) force an - * interrupt to avoid a potential deadlock situation. - */ - if (wrap->iw_hdlrcnt == 0) { - pcibr_force_interrupt(wrap); - } + /* + * If the non-threaded handler was the last to complete, + * (i.e., no threaded handlers still running) force an + * interrupt to avoid a potential deadlock situation. + */ + if (wrap->iw_hdlrcnt == 0) { + pcibr_force_interrupt(wrap); + } } /* If there were no handlers, @@ -892,14 +972,24 @@ if (clearit) { pcibr_soft_t pcibr_soft = wrap->iw_soft; bridge_t *bridge = pcibr_soft->bs_base; - bridgereg_t b_int_enable; - bridgereg_t mask = 1 << wrap->iw_intr; + bridgereg_t int_enable; + bridgereg_t mask = 1 << wrap->iw_ibit; unsigned long s; + /* PIC BRINUGP WAR (PV# 854697): + * On PIC we must write 64-bit MMRs with 64-bit stores + */ s = pcibr_lock(pcibr_soft); - b_int_enable = bridge->b_int_enable; - b_int_enable &= ~mask; - bridge->b_int_enable = b_int_enable; + if (IS_PIC_SOFT(pcibr_soft) && + PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) { + int_enable = bridge->p_int_enable_64; + int_enable &= ~mask; + bridge->p_int_enable_64 = int_enable; + } else { + int_enable = (uint64_t)bridge->b_int_enable; + int_enable &= ~mask; + bridge->b_int_enable = (bridgereg_t)int_enable; + } bridge->b_wid_tflush; /* wait until Bridge PIO complete */ pcibr_unlock(pcibr_soft, s); return; diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c Wed Jan 15 16:57:29 2003 @@ -33,259 +33,478 @@ void do_pcibr_rrb_clear(bridge_t *, int); void do_pcibr_rrb_flush(bridge_t *, int); -int do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t); +int do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t, int); int do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t); -int do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int); -int do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int); +int do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int, int); +int do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int, int); +void do_pcibr_rrb_free_all(pcibr_soft_t, bridge_t *, pciio_slot_t); -void do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int); +void do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int, int); int pcibr_wrb_flush(devfs_handle_t); int pcibr_rrb_alloc(devfs_handle_t, int *, int *); int pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *); -int pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int); void pcibr_rrb_flush(devfs_handle_t); int pcibr_slot_initial_rrb_alloc(devfs_handle_t,pciio_slot_t); -/* - * RRB Management - */ - -#define LSBIT(word) ((word) &~ ((word)-1)) - -void -do_pcibr_rrb_clear(bridge_t *bridge, int rrb) -{ - bridgereg_t status; - - /* bridge_lock must be held; - * this RRB must be disabled. - */ - - /* wait until RRB has no outstanduing XIO packets. */ - while ((status = bridge->b_resp_status) & BRIDGE_RRB_INUSE(rrb)) { - ; /* XXX- beats on bridge. bad idea? */ - } - - /* if the RRB has data, drain it. */ - if (status & BRIDGE_RRB_VALID(rrb)) { - bridge->b_resp_clear = BRIDGE_RRB_CLEAR(rrb); - - /* wait until RRB is no longer valid. */ - while ((status = bridge->b_resp_status) & BRIDGE_RRB_VALID(rrb)) { - ; /* XXX- beats on bridge. bad idea? */ - } - } -} - -void -do_pcibr_rrb_flush(bridge_t *bridge, int rrbn) -{ - reg_p rrbp = &bridge->b_rrb_map[rrbn & 1].reg; - bridgereg_t rrbv; - int shft = 4 * (rrbn >> 1); - unsigned ebit = BRIDGE_RRB_EN << shft; - - rrbv = *rrbp; - if (rrbv & ebit) - *rrbp = rrbv & ~ebit; - - do_pcibr_rrb_clear(bridge, rrbn); - - if (rrbv & ebit) - *rrbp = rrbv; -} +void pcibr_rrb_debug(char *, pcibr_soft_t); /* - * pcibr_rrb_count_valid: count how many RRBs are - * marked valid for the specified PCI slot on this - * bridge. - * - * NOTE: The "slot" parameter for all pcibr_rrb - * management routines must include the "virtual" - * bit; when manageing both the normal and the - * virtual channel, separate calls to these - * routines must be made. To denote the virtual - * channel, add PCIBR_RRB_SLOT_VIRTUAL to the slot - * number. - * - * IMPL NOTE: The obvious algorithm is to iterate - * through the RRB fields, incrementing a count if - * the RRB is valid and matches the slot. However, - * it is much simpler to use an algorithm derived - * from the "partitioned add" idea. First, XOR in a - * pattern such that the fields that match this - * slot come up "all ones" and all other fields - * have zeros in the mismatching bits. Then AND - * together the bits in the field, so we end up - * with one bit turned on for each field that - * matched. Now we need to count these bits. This - * can be done either with a series of shift/add - * instructions or by using "tmp % 15"; I expect - * that the cascaded shift/add will be faster. - */ - + * RRB Management + * + * All the do_pcibr_rrb_ routines manipulate the Read Response Buffer (rrb) + * registers within the Bridge. Two 32 registers (b_rrb_map[2] also known + * as the b_even_resp & b_odd_resp registers) are used to allocate the 16 + * rrbs to devices. The b_even_resp register represents even num devices, + * and b_odd_resp represent odd number devices. Each rrb is represented by + * 4-bits within a register. + * BRIDGE & XBRIDGE: 1 enable bit, 1 virtual channel bit, 2 device bits + * PIC: 1 enable bit, 2 virtual channel bits, 1 device bit + * PIC has 4 devices per bus, and 4 virtual channels (1 normal & 3 virtual) + * per device. BRIDGE & XBRIDGE have 8 devices per bus and 2 virtual + * channels (1 normal & 1 virtual) per device. See the BRIDGE and PIC ASIC + * Programmers Reference guides for more information. + */ + +#define RRB_MASK (0xf) /* mask a single rrb within reg */ +#define RRB_SIZE (4) /* sizeof rrb within reg (bits) */ + +#define RRB_ENABLE_BIT(bridge) (0x8) /* [BRIDGE | PIC]_RRB_EN */ +#define NUM_PDEV_BITS(bridge) (is_pic((bridge)) ? 1 : 2) +#define NUM_VDEV_BITS(bridge) (is_pic((bridge)) ? 2 : 1) +#define NUMBER_VCHANNELS(bridge) (is_pic((bridge)) ? 4 : 2) +#define SLOT_2_PDEV(bridge, slot) ((slot) >> 1) +#define SLOT_2_RRB_REG(bridge, slot) ((slot) & 0x1) + +/* validate that the slot and virtual channel are valid for a given bridge */ +#define VALIDATE_SLOT_n_VCHAN(bridge, s, v) \ + (is_pic((bridge)) ? \ + (((((s) != PCIIO_SLOT_NONE) && ((s) <= (pciio_slot_t)3)) && (((v) >= 0) && ((v) <= 3))) ? 1 : 0) : \ + (((((s) != PCIIO_SLOT_NONE) && ((s) <= (pciio_slot_t)7)) && (((v) >= 0) && ((v) <= 1))) ? 1 : 0)) + +/* + * Count how many RRBs are marked valid for the specified PCI slot + * and virtual channel. Return the count. + */ int do_pcibr_rrb_count_valid(bridge_t *bridge, - pciio_slot_t slot) + pciio_slot_t slot, + int vchan) { - bridgereg_t tmp; + bridgereg_t tmp; + uint16_t enable_bit, vchan_bits, pdev_bits, rrb_bits; + int rrb_index, cnt=0; + + if (!VALIDATE_SLOT_n_VCHAN(bridge, slot, vchan)) { + printk(KERN_WARNING "do_pcibr_rrb_count_valid() invalid slot/vchan [%d/%d]\n", slot, vchan); + return 0; + } + + enable_bit = RRB_ENABLE_BIT(bridge); + vchan_bits = vchan << NUM_PDEV_BITS(bridge); + pdev_bits = SLOT_2_PDEV(bridge, slot); + rrb_bits = enable_bit | vchan_bits | pdev_bits; + + if ( is_pic(bridge) ) { + tmp = bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + tmp = BRIDGE_REG_GET32((&bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg)); + } else { + tmp = bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg; + } + } - tmp = bridge->b_rrb_map[slot & 1].reg; - tmp ^= 0x11111111 * (7 - slot / 2); - tmp &= (0xCCCCCCCC & tmp) >> 2; - tmp &= (0x22222222 & tmp) >> 1; - tmp += tmp >> 4; - tmp += tmp >> 8; - tmp += tmp >> 16; - return tmp & 15; + for (rrb_index = 0; rrb_index < 8; rrb_index++) { + if ((tmp & RRB_MASK) == rrb_bits) + cnt++; + tmp = (tmp >> RRB_SIZE); + } + return cnt; } - -/* - * do_pcibr_rrb_count_avail: count how many RRBs are - * available to be allocated for the specified slot. - * - * IMPL NOTE: similar to the above, except we are - * just counting how many fields have the valid bit - * turned off. - */ + + +/* + * Count how many RRBs are available to be allocated to the specified + * slot. Return the count. + */ int do_pcibr_rrb_count_avail(bridge_t *bridge, pciio_slot_t slot) { - bridgereg_t tmp; + bridgereg_t tmp; + uint16_t enable_bit; + int rrb_index, cnt=0; + + if (!VALIDATE_SLOT_n_VCHAN(bridge, slot, 0)) { + printk(KERN_WARNING "do_pcibr_rrb_count_avail() invalid slot/vchan"); + return 0; + } + + enable_bit = RRB_ENABLE_BIT(bridge); + + if ( is_pic(bridge) ) { + tmp = bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + tmp = BRIDGE_REG_GET32((&bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg)); + } else { + tmp = bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg; + } + } - tmp = bridge->b_rrb_map[slot & 1].reg; - tmp = (0x88888888 & ~tmp) >> 3; - tmp += tmp >> 4; - tmp += tmp >> 8; - tmp += tmp >> 16; - return tmp & 15; + for (rrb_index = 0; rrb_index < 8; rrb_index++) { + if ((tmp & enable_bit) != enable_bit) + cnt++; + tmp = (tmp >> RRB_SIZE); + } + return cnt; } - -/* - * do_pcibr_rrb_alloc: allocate some additional RRBs - * for the specified slot. Returns -1 if there were - * insufficient free RRBs to satisfy the request, - * or 0 if the request was fulfilled. - * - * Note that if a request can be partially filled, - * it will be, even if we return failure. - * - * IMPL NOTE: again we avoid iterating across all - * the RRBs; instead, we form up a word containing - * one bit for each free RRB, then peel the bits - * off from the low end. - */ + + +/* + * Allocate some additional RRBs for the specified slot and the specified + * virtual channel. Returns -1 if there were insufficient free RRBs to + * satisfy the request, or 0 if the request was fulfilled. + * + * Note that if a request can be partially filled, it will be, even if + * we return failure. + */ int do_pcibr_rrb_alloc(bridge_t *bridge, pciio_slot_t slot, + int vchan, int more) { - int rv = 0; - bridgereg_t reg, tmp, bit; + bridgereg_t reg, tmp = (bridgereg_t)0; + uint16_t enable_bit, vchan_bits, pdev_bits, rrb_bits; + int rrb_index; + + if (!VALIDATE_SLOT_n_VCHAN(bridge, slot, vchan)) { + printk(KERN_WARNING "do_pcibr_rrb_alloc() invalid slot/vchan"); + return -1; + } + + enable_bit = RRB_ENABLE_BIT(bridge); + vchan_bits = vchan << NUM_PDEV_BITS(bridge); + pdev_bits = SLOT_2_PDEV(bridge, slot); + rrb_bits = enable_bit | vchan_bits | pdev_bits; + + if ( is_pic(bridge) ) { + reg = tmp = bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + reg = tmp = BRIDGE_REG_GET32((&bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg)); + } else { + reg = tmp = bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg; + } + } + + for (rrb_index = 0; ((rrb_index < 8) && (more > 0)); rrb_index++) { + if ((tmp & enable_bit) != enable_bit) { + /* clear the rrb and OR in the new rrb into 'reg' */ + reg = reg & ~(RRB_MASK << (RRB_SIZE * rrb_index)); + reg = reg | (rrb_bits << (RRB_SIZE * rrb_index)); + more--; + } + tmp = (tmp >> RRB_SIZE); + } - reg = bridge->b_rrb_map[slot & 1].reg; - tmp = (0x88888888 & ~reg) >> 3; - while (more-- > 0) { - bit = LSBIT(tmp); - if (!bit) { - rv = -1; - break; + if ( is_pic(bridge) ) { + bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg = reg; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_SET32((&bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg)) = reg; + } else { + bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg = reg; } - tmp &= ~bit; - reg = ((reg & ~(bit * 15)) | (bit * (8 + slot / 2))); } - bridge->b_rrb_map[slot & 1].reg = reg; - return rv; + return (more ? -1 : 0); } - -/* - * do_pcibr_rrb_free: release some of the RRBs that - * have been allocated for the specified - * slot. Returns zero for success, or negative if - * it was unable to free that many RRBs. - * - * IMPL NOTE: We form up a bit for each RRB - * allocated to the slot, aligned with the VALID - * bitfield this time; then we peel bits off one at - * a time, releasing the corresponding RRB. - */ + + +/* + * Release some of the RRBs that have been allocated for the specified + * slot. Returns zero for success, or negative if it was unable to free + * that many RRBs. + * + * Note that if a request can be partially fulfilled, it will be, even + * if we return failure. + */ int do_pcibr_rrb_free(bridge_t *bridge, pciio_slot_t slot, + int vchan, int less) { - int rv = 0; - bridgereg_t reg, tmp, clr, bit; - int i; + bridgereg_t reg, tmp = (bridgereg_t)0, clr = 0; + uint16_t enable_bit, vchan_bits, pdev_bits, rrb_bits; + int rrb_index; + + if (!VALIDATE_SLOT_n_VCHAN(bridge, slot, vchan)) { + printk(KERN_WARNING "do_pcibr_rrb_free() invalid slot/vchan"); + return -1; + } + + enable_bit = RRB_ENABLE_BIT(bridge); + vchan_bits = vchan << NUM_PDEV_BITS(bridge); + pdev_bits = SLOT_2_PDEV(bridge, slot); + rrb_bits = enable_bit | vchan_bits | pdev_bits; + + if ( is_pic(bridge) ) { + reg = tmp = bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + reg = BRIDGE_REG_GET32((&bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg)); + } else { + reg = tmp = bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg; + } + } + + for (rrb_index = 0; ((rrb_index < 8) && (less > 0)); rrb_index++) { + if ((tmp & RRB_MASK) == rrb_bits) { + /* + * the old do_pcibr_rrb_free() code only clears the enable bit + * but I say we should clear the whole rrb (ie): + * reg = reg & ~(RRB_MASK << (RRB_SIZE * rrb_index)); + * But to be compatable with old code we'll only clear enable. + */ + reg = reg & ~(RRB_ENABLE_BIT(bridge) << (RRB_SIZE * rrb_index)); + clr = clr | (enable_bit << (RRB_SIZE * rrb_index)); + less--; + } + tmp = (tmp >> RRB_SIZE); + } - clr = 0; - reg = bridge->b_rrb_map[slot & 1].reg; + if ( is_pic(bridge) ) { + bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg = reg; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_SET32((&bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg)) = reg; + } else { + bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg = reg; + } + } - /* This needs to be done otherwise the rrb's on the virtual channel - * for this slot won't be freed !! + /* call do_pcibr_rrb_clear() for all the rrbs we've freed */ + for (rrb_index = 0; rrb_index < 8; rrb_index++) { + int evn_odd = SLOT_2_RRB_REG(bridge, slot); + if (clr & (enable_bit << (RRB_SIZE * rrb_index))) + do_pcibr_rrb_clear(bridge, (2 * rrb_index) + evn_odd); + } + + return (less ? -1 : 0); +} + + +/* + * free all the rrbs (both the normal and virtual channels) for the + * specified slot. + */ +void +do_pcibr_rrb_free_all(pcibr_soft_t pcibr_soft, + bridge_t *bridge, + pciio_slot_t slot) +{ + int vchan; + int vchan_total = NUMBER_VCHANNELS(bridge); + + /* pretend we own all 8 rrbs and just ignore the return value */ + for (vchan = 0; vchan < vchan_total; vchan++) { + (void)do_pcibr_rrb_free(bridge, slot, vchan, 8); + pcibr_soft->bs_rrb_valid[slot][vchan] = 0; + } +} + + +/* + * Wait for the the specified rrb to have no outstanding XIO pkts + * and for all data to be drained. Mark the rrb as no longer being + * valid. + */ +void +do_pcibr_rrb_clear(bridge_t *bridge, int rrb) +{ + bridgereg_t status; + + /* bridge_lock must be held; + * this RRB must be disabled. */ - tmp = reg & 0xbbbbbbbb; - tmp ^= (0x11111111 * (7 - slot / 2)); - tmp &= (0x33333333 & tmp) << 2; - tmp &= (0x44444444 & tmp) << 1; - while (less-- > 0) { - bit = LSBIT(tmp); - if (!bit) { - rv = -1; - break; + if ( is_pic(bridge) ) { + /* wait until RRB has no outstanduing XIO packets. */ + while ((status = bridge->b_resp_status) & BRIDGE_RRB_INUSE(rrb)) { + ; /* XXX- beats on bridge. bad idea? */ + } + + /* if the RRB has data, drain it. */ + if (status & BRIDGE_RRB_VALID(rrb)) { + bridge->b_resp_clear = BRIDGE_RRB_CLEAR(rrb); + + /* wait until RRB is no longer valid. */ + while ((status = bridge->b_resp_status) & BRIDGE_RRB_VALID(rrb)) { + ; /* XXX- beats on bridge. bad idea? */ + } + } + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + while ((status = BRIDGE_REG_GET32((&bridge->b_resp_status))) & BRIDGE_RRB_INUSE(rrb)) { + ; /* XXX- beats on bridge. bad idea? */ + } + + /* if the RRB has data, drain it. */ + if (status & BRIDGE_RRB_VALID(rrb)) { + BRIDGE_REG_SET32((&bridge->b_resp_clear)) = __swab32(BRIDGE_RRB_CLEAR(rrb)); + + /* wait until RRB is no longer valid. */ + while ((status = BRIDGE_REG_GET32((&bridge->b_resp_status))) & BRIDGE_RRB_VALID(rrb)) { + ; /* XXX- beats on bridge. bad idea? */ + } + } + } else { /* io_get_sh_swapper(NASID_GET(bridge)) */ + while ((status = bridge->b_resp_status) & BRIDGE_RRB_INUSE(rrb)) { + ; /* XXX- beats on bridge. bad idea? */ + } + + /* if the RRB has data, drain it. */ + if (status & BRIDGE_RRB_VALID(rrb)) { + bridge->b_resp_clear = BRIDGE_RRB_CLEAR(rrb); + /* wait until RRB is no longer valid. */ + while ((status = bridge->b_resp_status) & BRIDGE_RRB_VALID(rrb)) { + ; /* XXX- beats on bridge. bad idea? */ + } + } + } + } +} + + +/* + * Flush the specified rrb by calling do_pcibr_rrb_clear(). This + * routine is just a wrapper to make sure the rrb is disabled + * before calling do_pcibr_rrb_clear(). + */ +void +do_pcibr_rrb_flush(bridge_t *bridge, int rrbn) +{ + reg_p rrbp = &bridge->b_rrb_map[rrbn & 1].reg; + bridgereg_t rrbv; + int shft = (RRB_SIZE * (rrbn >> 1)); + unsigned long ebit = RRB_ENABLE_BIT(bridge) << shft; + + if ( is_pic(bridge) ) { + rrbv = *rrbp; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + rrbv = BRIDGE_REG_GET32((&rrbp)); + } else { + rrbv = *rrbp; + } + } + + if (rrbv & ebit) { + if ( is_pic(bridge) ) { + *rrbp = rrbv & ~ebit; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_SET32((&rrbp)) = __swab32((rrbv & ~ebit)); + } else { + *rrbp = rrbv & ~ebit; + } } - tmp &= ~bit; - reg &= ~bit; - clr |= bit; } - bridge->b_rrb_map[slot & 1].reg = reg; - for (i = 0; i < 8; i++) - if (clr & (8 << (4 * i))) - do_pcibr_rrb_clear(bridge, (2 * i) + (slot & 1)); + do_pcibr_rrb_clear(bridge, rrbn); - return rv; + if (rrbv & ebit) { + if ( is_pic(bridge) ) { + *rrbp = rrbv; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + BRIDGE_REG_SET32((&rrbp)) = __swab32(rrbv); + } else { + *rrbp = rrbv; + } + } + } } + void do_pcibr_rrb_autoalloc(pcibr_soft_t pcibr_soft, int slot, + int vchan, int more_rrbs) { bridge_t *bridge = pcibr_soft->bs_base; int got; for (got = 0; got < more_rrbs; ++got) { - if (pcibr_soft->bs_rrb_res[slot & 7] > 0) - pcibr_soft->bs_rrb_res[slot & 7]--; + if (pcibr_soft->bs_rrb_res[slot] > 0) + pcibr_soft->bs_rrb_res[slot]--; else if (pcibr_soft->bs_rrb_avail[slot & 1] > 0) pcibr_soft->bs_rrb_avail[slot & 1]--; else break; - if (do_pcibr_rrb_alloc(bridge, slot, 1) < 0) + if (do_pcibr_rrb_alloc(bridge, slot, vchan, 1) < 0) break; -#if PCIBR_RRB_DEBUG - printk("do_pcibr_rrb_autoalloc: add one to slot %d%s\n", - slot & 7, slot & 8 ? "v" : ""); -#endif - pcibr_soft->bs_rrb_valid[slot]++; - } -#if PCIBR_RRB_DEBUG - printk("%s: %d+%d free RRBs. Allocation list:\n", pcibr_soft->bs_name, - pcibr_soft->bs_rrb_avail[0], - pcibr_soft->bs_rrb_avail[1]); - for (slot = 0; slot < 8; ++slot) - printk("\t%d+%d+%d", - 0xFFF & pcibr_soft->bs_rrb_valid[slot], - 0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL], - pcibr_soft->bs_rrb_res[slot]); - printk("\n"); -#endif + + pcibr_soft->bs_rrb_valid[slot][vchan]++; + } + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl, + "do_pcibr_rrb_autoalloc: added %d (of %d requested) RRBs " + "to slot %d, vchan %d\n", got, more_rrbs, + PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), vchan)); + + pcibr_rrb_debug("do_pcibr_rrb_autoalloc", pcibr_soft); } + +/* + * Flush all the rrb's assigned to the specified connection point. + */ +void +pcibr_rrb_flush(devfs_handle_t pconn_vhdl) +{ + pciio_info_t pciio_info = pciio_info_get(pconn_vhdl); + pcibr_soft_t pcibr_soft = (pcibr_soft_t)pciio_info_mfast_get(pciio_info); + pciio_slot_t slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); + bridge_t *bridge = pcibr_soft->bs_base; + + bridgereg_t tmp; + uint16_t enable_bit, pdev_bits, rrb_bits, rrb_mask; + int rrb_index; + unsigned long s; + + enable_bit = RRB_ENABLE_BIT(bridge); + pdev_bits = SLOT_2_PDEV(bridge, slot); + rrb_bits = enable_bit | pdev_bits; + rrb_mask = enable_bit | ((NUM_PDEV_BITS(bridge) << 1) - 1); + + tmp = bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg; + + s = pcibr_lock(pcibr_soft); + for (rrb_index = 0; rrb_index < 8; rrb_index++) { + int evn_odd = SLOT_2_RRB_REG(bridge, slot); + if ((tmp & rrb_mask) == rrb_bits) + do_pcibr_rrb_flush(bridge, (2 * rrb_index) + evn_odd); + tmp = (tmp >> RRB_SIZE); + } + pcibr_unlock(pcibr_soft, s); +} + + /* * Device driver interface to flush the write buffers for a specified * device hanging off the bridge. @@ -294,14 +513,24 @@ pcibr_wrb_flush(devfs_handle_t pconn_vhdl) { pciio_info_t pciio_info = pciio_info_get(pconn_vhdl); - pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info); + pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info); bridge_t *bridge = pcibr_soft->bs_base; volatile bridgereg_t *wrb_flush; wrb_flush = &(bridge->b_wr_req_buf[pciio_slot].reg); - while (*wrb_flush); - + if ( IS_PIC_SOFT(pcibr_soft) ) { + while (*wrb_flush) + ; + } + else { + if (io_get_sh_swapper(NASID_GET(bridge))) { + while (BRIDGE_REG_GET32((wrb_flush))); + } else { + while (*wrb_flush) + ; + } + } return(0); } @@ -322,7 +551,7 @@ int *count_vchan1) { pciio_info_t pciio_info = pciio_info_get(pconn_vhdl); - pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info); + pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info); bridge_t *bridge = pcibr_soft->bs_base; int desired_vchan0; @@ -335,7 +564,9 @@ int final_vchan1; int avail_rrbs; int res_rrbs; - unsigned long s; + int vchan_total; + int vchan; + unsigned long s; int error; /* @@ -352,20 +583,21 @@ s = pcibr_lock(pcibr_soft); + vchan_total = NUMBER_VCHANNELS(bridge); + /* Save the boot-time RRB configuration for this slot */ - if (pcibr_soft->bs_rrb_valid_dflt[pciio_slot] < 0) { - pcibr_soft->bs_rrb_valid_dflt[pciio_slot] = - pcibr_soft->bs_rrb_valid[pciio_slot]; - pcibr_soft->bs_rrb_valid_dflt[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL] = - pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL]; + if (pcibr_soft->bs_rrb_valid_dflt[pciio_slot][VCHAN0] < 0) { + for (vchan = 0; vchan < vchan_total; vchan++) + pcibr_soft->bs_rrb_valid_dflt[pciio_slot][vchan] = + pcibr_soft->bs_rrb_valid[pciio_slot][vchan]; pcibr_soft->bs_rrb_res_dflt[pciio_slot] = pcibr_soft->bs_rrb_res[pciio_slot]; } /* How many RRBs do we own? */ - orig_vchan0 = pcibr_soft->bs_rrb_valid[pciio_slot]; - orig_vchan1 = pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL]; + orig_vchan0 = pcibr_soft->bs_rrb_valid[pciio_slot][VCHAN0]; + orig_vchan1 = pcibr_soft->bs_rrb_valid[pciio_slot][VCHAN1]; /* How many RRBs do we want? */ desired_vchan0 = count_vchan0 ? *count_vchan0 : orig_vchan0; @@ -417,14 +649,14 @@ /* Commit the allocations: free, then alloc. */ if (delta_vchan0 < 0) - (void) do_pcibr_rrb_free(bridge, pciio_slot, -delta_vchan0); + (void) do_pcibr_rrb_free(bridge, pciio_slot, VCHAN0, -delta_vchan0); if (delta_vchan1 < 0) - (void) do_pcibr_rrb_free(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, -delta_vchan1); + (void) do_pcibr_rrb_free(bridge, pciio_slot, VCHAN1, -delta_vchan1); if (delta_vchan0 > 0) - (void) do_pcibr_rrb_alloc(bridge, pciio_slot, delta_vchan0); + (void) do_pcibr_rrb_alloc(bridge, pciio_slot, VCHAN0, delta_vchan0); if (delta_vchan1 > 0) - (void) do_pcibr_rrb_alloc(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, delta_vchan1); + (void) do_pcibr_rrb_alloc(bridge, pciio_slot, VCHAN1, delta_vchan1); /* Return final values to caller. */ @@ -442,8 +674,8 @@ * number of available RRBs. */ - pcibr_soft->bs_rrb_valid[pciio_slot] = final_vchan0; - pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL] = final_vchan1; + pcibr_soft->bs_rrb_valid[pciio_slot][VCHAN0] = final_vchan0; + pcibr_soft->bs_rrb_valid[pciio_slot][VCHAN1] = final_vchan1; pcibr_soft->bs_rrb_avail[pciio_slot & 1] = pcibr_soft->bs_rrb_avail[pciio_slot & 1] + pcibr_soft->bs_rrb_res[pciio_slot] @@ -455,34 +687,21 @@ * Reserve enough RRBs so this slot's RRB configuration can be * reset to its boot-time default following a hot-plug shut-down */ - res_rrbs = (pcibr_soft->bs_rrb_valid_dflt[pciio_slot] - - pcibr_soft->bs_rrb_valid[pciio_slot]) - + (pcibr_soft->bs_rrb_valid_dflt[pciio_slot + - PCIBR_RRB_SLOT_VIRTUAL] - - pcibr_soft->bs_rrb_valid[pciio_slot + - PCIBR_RRB_SLOT_VIRTUAL]) - + (pcibr_soft->bs_rrb_res_dflt[pciio_slot] - - pcibr_soft->bs_rrb_res[pciio_slot]); - - if (res_rrbs > 0) { - pcibr_soft->bs_rrb_res[pciio_slot] = res_rrbs; - pcibr_soft->bs_rrb_avail[pciio_slot & 1] = - pcibr_soft->bs_rrb_avail[pciio_slot & 1] - - res_rrbs; - } - -#if PCIBR_RRB_DEBUG - printk("pcibr_rrb_alloc: slot %d set to %d+%d; %d+%d free\n", - pciio_slot, final_vchan0, final_vchan1, - pcibr_soft->bs_rrb_avail[0], - pcibr_soft->bs_rrb_avail[1]); - for (pciio_slot = 0; pciio_slot < 8; ++pciio_slot) - printk("\t%d+%d+%d", - 0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot], - 0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL], + res_rrbs = (pcibr_soft->bs_rrb_res_dflt[pciio_slot] - pcibr_soft->bs_rrb_res[pciio_slot]); - printk("\n"); -#endif + for (vchan = 0; vchan < vchan_total; vchan++) { + res_rrbs += (pcibr_soft->bs_rrb_valid_dflt[pciio_slot][vchan] - + pcibr_soft->bs_rrb_valid[pciio_slot][vchan]); + } + + if (res_rrbs > 0) { + pcibr_soft->bs_rrb_res[pciio_slot] = res_rrbs; + pcibr_soft->bs_rrb_avail[pciio_slot & 1] = + pcibr_soft->bs_rrb_avail[pciio_slot & 1] + - res_rrbs; + } + + pcibr_rrb_debug("pcibr_rrb_alloc", pcibr_soft); error = 0; } @@ -543,22 +762,22 @@ pciio_info_t pciio_info; pciio_slot_t pciio_slot; pcibr_soft_t pcibr_soft; - unsigned long s; + unsigned long s; int error = -1; if ((pciio_info = pciio_info_get(pconn_vhdl)) && (pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info)) && - ((pciio_slot = pciio_info_slot_get(pciio_info)) < 8)) { + ((pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info)) < PCIBR_NUM_SLOTS(pcibr_soft))) { s = pcibr_lock(pcibr_soft); if (count_vchan0) *count_vchan0 = - pcibr_soft->bs_rrb_valid[pciio_slot]; + pcibr_soft->bs_rrb_valid[pciio_slot][VCHAN0]; if (count_vchan1) *count_vchan1 = - pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL]; + pcibr_soft->bs_rrb_valid[pciio_slot][VCHAN1]; if (count_reserved) *count_reserved = @@ -575,159 +794,6 @@ return error; } -/* pcibr_alloc_all_rrbs allocates all the rrbs available in the quantities - * requested for each of the devices. The evn_odd argument indicates whether - * allocation is for the odd or even rrbs. The next group of four argument - * pairs indicate the amount of rrbs to be assigned to each device. The first - * argument of each pair indicate the total number of rrbs to allocate for that - * device. The second argument of each pair indicates how many rrb's from the - * first argument should be assigned to the virtual channel. The total of all - * of the first arguments should be <= 8. The second argument should be <= the - * first argument. - * if even_odd = 0 the devices in order are 0, 2, 4, 6 - * if even_odd = 1 the devices in order are 1, 3, 5, 7 - * returns 0 if no errors else returns -1 - */ - -int -pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd, - int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2, - int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4) -{ - devfs_handle_t pcibr_vhdl; - pcibr_soft_t pcibr_soft = (pcibr_soft_t)0; - bridge_t *bridge = NULL; - - uint32_t rrb_setting = 0; - int rrb_shift = 7; - uint32_t cur_rrb; - int dev_rrbs[4]; - int virt[4]; - int i, j; - unsigned long s; - - if (GRAPH_SUCCESS == - hwgraph_traverse(vhdl, EDGE_LBL_PCI, &pcibr_vhdl)) { - pcibr_soft = pcibr_soft_get(pcibr_vhdl); - if (pcibr_soft) - bridge = pcibr_soft->bs_base; - hwgraph_vertex_unref(pcibr_vhdl); - } - if (bridge == NULL) - bridge = (bridge_t *) xtalk_piotrans_addr - (vhdl, NULL, 0, sizeof(bridge_t), 0); - - even_odd &= 1; - - dev_rrbs[0] = dev_1_rrbs; - dev_rrbs[1] = dev_2_rrbs; - dev_rrbs[2] = dev_3_rrbs; - dev_rrbs[3] = dev_4_rrbs; - - virt[0] = virt1; - virt[1] = virt2; - virt[2] = virt3; - virt[3] = virt4; - - if ((dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs) > 8) { - return -1; - } - if ((dev_1_rrbs < 0) || (dev_2_rrbs < 0) || (dev_3_rrbs < 0) || (dev_4_rrbs < 0)) { - return -1; - } - /* walk through rrbs */ - for (i = 0; i < 4; i++) { - if (virt[i]) { - for( j = 0; j < virt[i]; j++) { - cur_rrb = i | 0xc; - cur_rrb = cur_rrb << (rrb_shift * 4); - rrb_shift--; - rrb_setting = rrb_setting | cur_rrb; - dev_rrbs[i] = dev_rrbs[i] - 1; - } - } - for (j = 0; j < dev_rrbs[i]; j++) { - cur_rrb = i | 0x8; - cur_rrb = cur_rrb << (rrb_shift * 4); - rrb_shift--; - rrb_setting = rrb_setting | cur_rrb; - } - } - - if (pcibr_soft) - s = pcibr_lock(pcibr_soft); - - bridge->b_rrb_map[even_odd].reg = rrb_setting; - - if (pcibr_soft) { - - pcibr_soft->bs_rrb_fixed |= 0x55 << even_odd; - - /* since we've "FIXED" the allocations - * for these slots, we probably can dispense - * with tracking avail/res/valid data, but - * keeping it up to date helps debugging. - */ - - pcibr_soft->bs_rrb_avail[even_odd] = - 8 - (dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs); - - pcibr_soft->bs_rrb_res[even_odd + 0] = 0; - pcibr_soft->bs_rrb_res[even_odd + 2] = 0; - pcibr_soft->bs_rrb_res[even_odd + 4] = 0; - pcibr_soft->bs_rrb_res[even_odd + 6] = 0; - - pcibr_soft->bs_rrb_valid[even_odd + 0] = dev_1_rrbs - virt1; - pcibr_soft->bs_rrb_valid[even_odd + 2] = dev_2_rrbs - virt2; - pcibr_soft->bs_rrb_valid[even_odd + 4] = dev_3_rrbs - virt3; - pcibr_soft->bs_rrb_valid[even_odd + 6] = dev_4_rrbs - virt4; - - pcibr_soft->bs_rrb_valid[even_odd + 0 + PCIBR_RRB_SLOT_VIRTUAL] = virt1; - pcibr_soft->bs_rrb_valid[even_odd + 2 + PCIBR_RRB_SLOT_VIRTUAL] = virt2; - pcibr_soft->bs_rrb_valid[even_odd + 4 + PCIBR_RRB_SLOT_VIRTUAL] = virt3; - pcibr_soft->bs_rrb_valid[even_odd + 6 + PCIBR_RRB_SLOT_VIRTUAL] = virt4; - - pcibr_unlock(pcibr_soft, s); - } - return 0; -} - -/* - * pcibr_rrb_flush: chase down all the RRBs assigned - * to the specified connection point, and flush - * them. - */ -void -pcibr_rrb_flush(devfs_handle_t pconn_vhdl) -{ - pciio_info_t pciio_info = pciio_info_get(pconn_vhdl); - pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info); - pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info); - bridge_t *bridge = pcibr_soft->bs_base; - unsigned long s; - reg_p rrbp; - unsigned rrbm; - int i; - int rrbn; - unsigned sval; - unsigned mask; - - sval = BRIDGE_RRB_EN | (pciio_slot >> 1); - mask = BRIDGE_RRB_EN | BRIDGE_RRB_PDEV; - rrbn = pciio_slot & 1; - rrbp = &bridge->b_rrb_map[rrbn].reg; - - s = pcibr_lock(pcibr_soft); - rrbm = *rrbp; - for (i = 0; i < 8; ++i) { - if ((rrbm & mask) == sval) - do_pcibr_rrb_flush(bridge, rrbn); - rrbm >>= 4; - rrbn += 2; - } - pcibr_unlock(pcibr_soft, s); -} - /* * pcibr_slot_initial_rrb_alloc * Allocate a default number of rrbs for this slot on @@ -743,75 +809,82 @@ pcibr_info_h pcibr_infoh; pcibr_info_t pcibr_info; bridge_t *bridge; - int c0, c1, r; + int vchan_total; + int vchan; + int chan[4]; pcibr_soft = pcibr_soft_get(pcibr_vhdl); - if (!pcibr_soft || !PCIBR_VALID_SLOT(slot)) + if (!pcibr_soft) return(EINVAL); - bridge = pcibr_soft->bs_base; + if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) + return(EINVAL); - /* How may RRBs are on this slot? - */ - c0 = do_pcibr_rrb_count_valid(bridge, slot); - c1 = do_pcibr_rrb_count_valid(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL); + bridge = pcibr_soft->bs_base; -#if PCIBR_RRB_DEBUG - printk( + /* How many RRBs are on this slot? */ + vchan_total = NUMBER_VCHANNELS(bridge); + for (vchan = 0; vchan < vchan_total; vchan++) + chan[vchan] = do_pcibr_rrb_count_valid(bridge, slot, vchan); + + if (IS_PIC_SOFT(pcibr_soft)) { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_vhdl, + "pcibr_slot_initial_rrb_alloc: slot %d started with %d+%d+%d+%d\n", + PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), + chan[VCHAN0], chan[VCHAN1], chan[VCHAN2], chan[VCHAN3])); + } else { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_vhdl, "pcibr_slot_initial_rrb_alloc: slot %d started with %d+%d\n", - slot, c0, c1); -#endif + PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), + chan[VCHAN0], chan[VCHAN1])); + } /* Do we really need any? */ pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos; pcibr_info = pcibr_infoh[0]; - if ((pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) && - !pcibr_soft->bs_slot[slot].has_host) { - if (c0 > 0) - do_pcibr_rrb_free(bridge, slot, c0); - if (c1 > 0) - do_pcibr_rrb_free(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL, c1); - pcibr_soft->bs_rrb_valid[slot] = 0x1000; - pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0x1000; - return(ENODEV); - } - pcibr_soft->bs_rrb_avail[slot & 1] -= c0 + c1; - pcibr_soft->bs_rrb_valid[slot] = c0; - pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = c1; - - pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(bridge, 0); - pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(bridge, 1); + if (PCIBR_WAR_ENABLED(PV856866, pcibr_soft) && IS_PIC_SOFT(pcibr_soft) && + (slot == 2 || slot == 3) && + (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) && + !pcibr_soft->bs_slot[slot].has_host) { + + for (vchan = 0; vchan < 2; vchan++) { + do_pcibr_rrb_free(bridge, slot, vchan, 8); + pcibr_soft->bs_rrb_valid[slot][vchan] = 0; + } - r = 3 - (c0 + c1); + pcibr_soft->bs_rrb_valid[slot][3] = chan[3]; - if (r > 0) { - pcibr_soft->bs_rrb_res[slot] = r; - pcibr_soft->bs_rrb_avail[slot & 1] -= r; + return(ENODEV); } -#if PCIBR_RRB_DEBUG - printk("\t%d+%d+%d", - 0xFFF & pcibr_soft->bs_rrb_valid[slot], - 0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL], - pcibr_soft->bs_rrb_res[slot]); - printk("\n"); -#endif + for (vchan = 0; vchan < vchan_total; vchan++) + pcibr_soft->bs_rrb_valid[slot][vchan] = chan[vchan]; return(0); } +void +rrb_reserved_free(pcibr_soft_t pcibr_soft, int slot) +{ + int res = pcibr_soft->bs_rrb_res[slot]; + + if (res) { + pcibr_soft->bs_rrb_avail[slot & 1] += res; + pcibr_soft->bs_rrb_res[slot] = 0; + } +} + /* * pcibr_initial_rrb * Assign an equal total number of RRBs to all candidate slots, * where the total is the sum of the number of RRBs assigned to * the normal channel, the number of RRBs assigned to the virtual - * channel, and the number of RRBs assigned as reserved. + * channels, and the number of RRBs assigned as reserved. * - * A candidate slot is a populated slot on a non-SN1 system or - * any existing (populated or empty) slot on an SN1 system. + * A candidate slot is any existing (populated or empty) slot. * Empty SN1 slots need RRBs to support hot-plug operations. */ @@ -822,7 +895,9 @@ pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl); bridge_t *bridge = pcibr_soft->bs_base; pciio_slot_t slot; - int c0, c1; + int rrb_total; + int vchan_total; + int vchan; int have[2][3]; int res[2]; int eo; @@ -831,16 +906,21 @@ have[1][0] = have[1][1] = have[1][2] = 0; res[0] = res[1] = 0; - for (slot = 0; slot < 8; ++slot) { + vchan_total = NUMBER_VCHANNELS(bridge); + + for (slot = pcibr_soft->bs_min_slot; + slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) { /* Initial RRB management; give back RRBs in all non-existent slots */ (void) pcibr_slot_initial_rrb_alloc(pcibr_vhdl, slot); /* Base calculations only on existing slots */ if ((slot >= first) && (slot <= last)) { - c0 = pcibr_soft->bs_rrb_valid[slot]; - c1 = pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL]; - if ((c0 + c1) < 3) - have[slot & 1][c0 + c1]++; + rrb_total = 0; + for (vchan = 0; vchan < vchan_total; vchan++) + rrb_total += pcibr_soft->bs_rrb_valid[slot][vchan]; + + if (rrb_total < 3) + have[slot & 1][rrb_total]++; } } @@ -867,30 +947,70 @@ for (slot = first; slot <= last; ++slot) { int r; - c0 = pcibr_soft->bs_rrb_valid[slot]; - c1 = pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL]; - r = res[slot & 1] - (c0 + c1); + rrb_total = 0; + for (vchan = 0; vchan < vchan_total; vchan++) + rrb_total += pcibr_soft->bs_rrb_valid[slot][vchan]; + + r = res[slot & 1] - (rrb_total); if (r > 0) { pcibr_soft->bs_rrb_res[slot] = r; pcibr_soft->bs_rrb_avail[slot & 1] -= r; - } + } } -#if PCIBR_RRB_DEBUG - printk("%v RRB MANAGEMENT: %d+%d free\n", - pcibr_vhdl, - pcibr_soft->bs_rrb_avail[0], - pcibr_soft->bs_rrb_avail[1]); - for (slot = first; slot <= last; ++slot) - printk("\tslot %d: %d+%d+%d", slot, - 0xFFF & pcibr_soft->bs_rrb_valid[slot], - 0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL], - pcibr_soft->bs_rrb_res[slot]); - printk("\n"); -#endif + pcibr_rrb_debug("pcibr_initial_rrb", pcibr_soft); return 0; } +/* + * Dump the pcibr_soft_t RRB state variable + */ +void +pcibr_rrb_debug(char *calling_func, pcibr_soft_t pcibr_soft) +{ + pciio_slot_t slot; + char tmp_str[256]; + + if (pcibr_debug_mask & PCIBR_DEBUG_RRB) { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl, + "%s: rrbs available, even=%d, odd=%d\n", calling_func, + pcibr_soft->bs_rrb_avail[0], pcibr_soft->bs_rrb_avail[1])); + + if (IS_PIC_SOFT(pcibr_soft)) { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl, + "\tslot\tvchan0\tvchan1\tvchan2\tvchan3\treserved\n")); + } else { + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl, + "\tslot\tvchan0\tvchan1\treserved\n")); + } + + for (slot=0; slot < PCIBR_NUM_SLOTS(pcibr_soft); slot++) { + /* + * The kernel only allows functions to have so many variable args, + * attempting to call PCIBR_DEBUG_ALWAYS() with more than 5 printf + * arguments fails so sprintf() it into a temporary string. + */ + if (IS_PIC_SOFT(pcibr_soft)) { + sprintf(tmp_str, "\t %d\t %d\t %d\t %d\t %d\t %d\n", + PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), + 0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN0], + 0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN1], + 0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN2], + 0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN3], + pcibr_soft->bs_rrb_res[slot]); + } else { + sprintf(tmp_str, "\t %d\t %d\t %d\t %d\n", + PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), + 0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN0], + 0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN1], + pcibr_soft->bs_rrb_res[slot]); + } + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl, + "%s", tmp_str)); + } + } +} diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c Wed Jan 15 16:57:29 2003 @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -30,70 +31,90 @@ #include #include #include +#include + +#ifdef __ia64 +#define rmallocmap atemapalloc +#define rmfreemap atemapfree +#define rmfree atefree +#define rmalloc atealloc +#endif + extern pcibr_info_t pcibr_info_get(devfs_handle_t); -extern int pcibr_widget_to_bus(int); +extern int pcibr_widget_to_bus(devfs_handle_t pcibr_vhdl); extern pcibr_info_t pcibr_device_info_new(pcibr_soft_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t); -extern void pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t); extern int pcibr_slot_initial_rrb_alloc(devfs_handle_t,pciio_slot_t); -#if 0 -int pcibr_slot_reset(devfs_handle_t pcibr_vhdl, pciio_slot_t slot); -#endif +extern int pcibr_pcix_rbars_calc(pcibr_soft_t); int pcibr_slot_info_init(devfs_handle_t pcibr_vhdl, pciio_slot_t slot); int pcibr_slot_info_free(devfs_handle_t pcibr_vhdl, pciio_slot_t slot); int pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl, pciio_slot_t slot); +int pcibr_slot_pcix_rbar_init(pcibr_soft_t pcibr_soft, pciio_slot_t slot); int pcibr_slot_device_init(devfs_handle_t pcibr_vhdl, pciio_slot_t slot); int pcibr_slot_guest_info_init(devfs_handle_t pcibr_vhdl, pciio_slot_t slot); int pcibr_slot_call_device_attach(devfs_handle_t pcibr_vhdl, pciio_slot_t slot, int drv_flags); int pcibr_slot_call_device_detach(devfs_handle_t pcibr_vhdl, pciio_slot_t slot, int drv_flags); -int pcibr_slot_detach(devfs_handle_t pcibr_vhdl, pciio_slot_t slot, int drv_flags); +int pcibr_slot_detach(devfs_handle_t pcibr_vhdl, pciio_slot_t slot, + int drv_flags, char *l1_msg, int *sub_errorp); int pcibr_is_slot_sys_critical(devfs_handle_t pcibr_vhdl, pciio_slot_t slot); -int pcibr_probe_slot(bridge_t *, cfg_p, unsigned int *); -void pcibr_device_info_free(devfs_handle_t, pciio_slot_t); -extern uint64_t do_pcibr_config_get(cfg_p, unsigned, unsigned); +static int pcibr_probe_slot(bridge_t *, cfg_p, unsigned int *); +void pcibr_device_info_free(devfs_handle_t, pciio_slot_t); +iopaddr_t pcibr_bus_addr_alloc(pcibr_soft_t, pciio_win_info_t, + pciio_space_t, int, int, int); +void pciibr_bus_addr_free(pcibr_soft_t, pciio_win_info_t); +cfg_p pcibr_find_capability(cfg_p, unsigned); +extern uint64_t do_pcibr_config_get(int, cfg_p, unsigned, unsigned); +void do_pcibr_config_set(int, cfg_p, unsigned, unsigned, uint64_t); -#ifdef LATER int pcibr_slot_attach(devfs_handle_t pcibr_vhdl, pciio_slot_t slot, int drv_flags, char *l1_msg, int *sub_errorp); -int pcibr_slot_pwr(devfs_handle_t, pciio_slot_t, int, char *); -int pcibr_slot_startup(devfs_handle_t, pcibr_slot_req_t); -int pcibr_slot_shutdown(devfs_handle_t, pcibr_slot_req_t); -void pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh, int func, - pcibr_slot_func_info_resp_t funcp); + int pcibr_slot_info_return(pcibr_soft_t pcibr_soft, pciio_slot_t slot, pcibr_slot_info_resp_t respp); -int pcibr_slot_query(devfs_handle_t, pcibr_slot_req_t); -#endif /* LATER */ extern devfs_handle_t baseio_pci_vhdl; int scsi_ctlr_nums_add(devfs_handle_t, devfs_handle_t); + /* For now .... */ /* * PCI Hot-Plug Capability Flags + */ #define D_PCI_HOT_PLUG_ATTACH 0x200 /* Driver supports PCI hot-plug attach */ #define D_PCI_HOT_PLUG_DETACH 0x400 /* Driver supports PCI hot-plug detach */ +/* + * PCI-X Max Outstanding Split Transactions translation array and Max Memory + * Read Byte Count translation array, as defined in the PCI-X Specification. + * Section 7.2.3 & 7.2.4 of PCI-X Specification - rev 1.0 + */ +#define MAX_SPLIT_TABLE 8 +#define MAX_READCNT_TABLE 4 +int max_splittrans_to_numbuf[MAX_SPLIT_TABLE] = {1, 2, 3, 4, 8, 12, 16, 32}; +int max_readcount_to_bufsize[MAX_READCNT_TABLE] = {512, 1024, 2048, 4096 }; + + /*========================================================================== * BRIDGE PCI SLOT RELATED IOCTLs */ -#ifdef LATER - /* * pcibr_slot_startup * Software start-up the PCI slot. */ + +#ifdef PIC_LATER + int pcibr_slot_startup(devfs_handle_t pcibr_vhdl, pcibr_slot_req_t reqp) { pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl); - pciio_slot_t slot = reqp->req_slot; + pciio_slot_t slot; int error = 0; char l1_msg[BRL1_QSIZE+1]; struct pcibr_slot_up_resp_s tmp_up_resp; @@ -103,17 +124,22 @@ return(PCI_NOT_A_BRIDGE); } + /* req_slot is the 'external' slot number, convert for internal use */ + slot = PCIBR_SLOT_TO_DEVICE(pcibr_soft, reqp->req_slot); + /* Do not allow start-up of a slot in a shoehorn */ if(nic_vertex_info_match(pcibr_soft->bs_conn, XTALK_PCI_PART_NUM)) { return(PCI_SLOT_IN_SHOEHORN); } /* Check for the valid slot */ - if (!PCIBR_VALID_SLOT(slot)) + if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) return(PCI_NOT_A_SLOT); +#ifdef PIC_LATER /* Acquire update access to the bus */ mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO); +#endif if (pcibr_soft->bs_slot[slot].slot_status & SLOT_STARTUP_CMPLT) { error = PCI_SLOT_ALREADY_UP; @@ -132,9 +158,10 @@ startup_unlock: +#ifdef PIC_LATER /* Release the bus lock */ mrunlock(pcibr_soft->bs_bus_lock); - +#endif return(error); } @@ -147,7 +174,7 @@ { pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl); bridge_t *bridge; - pciio_slot_t slot = reqp->req_slot; + pciio_slot_t slot; int error = 0; char l1_msg[BRL1_QSIZE+1]; struct pcibr_slot_down_resp_s tmp_down_resp; @@ -158,10 +185,13 @@ return(PCI_NOT_A_BRIDGE); } + /* req_slot is the 'external' slot number, convert for internal use */ + slot = PCIBR_SLOT_TO_DEVICE(pcibr_soft, reqp->req_slot); + bridge = pcibr_soft->bs_base; /* Check for valid slot */ - if (!PCIBR_VALID_SLOT(slot)) + if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) return(PCI_NOT_A_SLOT); /* Do not allow shut-down of a slot in a shoehorn */ @@ -169,8 +199,10 @@ return(PCI_SLOT_IN_SHOEHORN); } +#ifdef PIC_LATER /* Acquire update access to the bus */ mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO); +#endif if ((pcibr_soft->bs_slot[slot].slot_status & SLOT_SHUTDOWN_CMPLT) || ((pcibr_soft->bs_slot[slot].slot_status & SLOT_STATUS_MASK) == 0)) { @@ -182,6 +214,13 @@ goto shutdown_unlock; } + /* Do not allow a multi-function card to be hot-plug removed */ + if (pcibr_soft->bs_slot[slot].bss_ninfo > 1) { + tmp_down_resp.resp_sub_errno = EPERM; + error = PCI_MULTI_FUNC_ERR; + goto shutdown_copyout; + } + /* Do not allow the last 33 MHz card to be removed */ if ((bridge->b_wid_control & BRIDGE_CTRL_BUS_SPEED_MASK) == BRIDGE_CTRL_BUS_SPEED_33) { @@ -204,17 +243,22 @@ strncpy(tmp_down_resp.resp_l1_msg, l1_msg, L1_QSIZE); tmp_down_resp.resp_l1_msg[L1_QSIZE] = '\0'; + shutdown_copyout: + if (COPYOUT(&tmp_down_resp, reqp->req_respp.down, reqp->req_size)) { return(EFAULT); } shutdown_unlock: +#ifdef PIC_LATER /* Release the bus lock */ mrunlock(pcibr_soft->bs_bus_lock); +#endif return(error); } +#endif /* PIC_LATER */ char *pci_space_name[] = {"NONE", "ROM", @@ -240,6 +284,7 @@ { pcibr_info_t pcibr_info = pcibr_infoh[func]; int win; + boolean_t is_sys_critical_vertex(devfs_handle_t); funcp->resp_f_status = 0; @@ -248,16 +293,19 @@ } funcp->resp_f_status |= FUNC_IS_VALID; +#if defined(SUPPORT_PRINTING_V_FORMAT) sprintf(funcp->resp_f_slot_name, "%v", pcibr_info->f_vertex); - +#endif if(is_sys_critical_vertex(pcibr_info->f_vertex)) { funcp->resp_f_status |= FUNC_IS_SYS_CRITICAL; } funcp->resp_f_bus = pcibr_info->f_bus; - funcp->resp_f_slot = pcibr_info->f_slot; + funcp->resp_f_slot = PCIBR_INFO_SLOT_GET_EXT(pcibr_info); funcp->resp_f_func = pcibr_info->f_func; +#if defined(SUPPORT_PRINTING_V_FORMAT) sprintf(funcp->resp_f_master_name, "%v", pcibr_info->f_master); +#endif funcp->resp_f_pops = pcibr_info->f_pops; funcp->resp_f_efunc = pcibr_info->f_efunc; funcp->resp_f_einfo = pcibr_info->f_einfo; @@ -297,20 +345,29 @@ reg_p b_respp; pcibr_slot_info_resp_t slotp; pcibr_slot_func_info_resp_t funcp; + boolean_t is_sys_critical_vertex(devfs_handle_t); + extern void snia_kmem_free(void *, int); - slotp = kmem_zalloc(sizeof(*slotp), KM_SLEEP); + slotp = snia_kmem_zalloc(sizeof(*slotp), 0); if (slotp == NULL) { return(ENOMEM); } pss = &pcibr_soft->bs_slot[slot]; + slotp->resp_bs_bridge_mode = pcibr_soft->bs_bridge_mode; + slotp->resp_bs_bridge_type = pcibr_soft->bs_bridge_type; + slotp->resp_has_host = pss->has_host; slotp->resp_host_slot = pss->host_slot; +#if defined(SUPPORT_PRINTING_V_FORMAT) sprintf(slotp->resp_slot_conn_name, "%v", pss->slot_conn); +#else + sprintf(slotp->resp_slot_conn_name, "%p", (void *)pss->slot_conn); +#endif slotp->resp_slot_status = pss->slot_status; - slotp->resp_l1_bus_num = io_path_map_widget(pcibr_soft->bs_vhdl); + slotp->resp_l1_bus_num = pcibr_widget_to_bus(pcibr_soft->bs_vhdl); if (is_sys_critical_vertex(pss->slot_conn)) { slotp->resp_slot_status |= SLOT_IS_SYS_CRITICAL; @@ -342,9 +399,10 @@ slotp->resp_bss_cmd_pointer = pss->bss_cmd_pointer; slotp->resp_bss_cmd_shadow = pss->bss_cmd_shadow; - slotp->resp_bs_rrb_valid = pcibr_soft->bs_rrb_valid[slot]; - slotp->resp_bs_rrb_valid_v = pcibr_soft->bs_rrb_valid[slot + - PCIBR_RRB_SLOT_VIRTUAL]; + slotp->resp_bs_rrb_valid = pcibr_soft->bs_rrb_valid[slot][VCHAN0]; + slotp->resp_bs_rrb_valid_v1 = pcibr_soft->bs_rrb_valid[slot][VCHAN1]; + slotp->resp_bs_rrb_valid_v2 = pcibr_soft->bs_rrb_valid[slot][VCHAN2]; + slotp->resp_bs_rrb_valid_v3 = pcibr_soft->bs_rrb_valid[slot][VCHAN3]; slotp->resp_bs_rrb_res = pcibr_soft->bs_rrb_res[slot]; if (slot & 1) { @@ -355,16 +413,21 @@ slotp->resp_b_resp = *b_respp; - slotp->resp_b_wid_control = bridge->b_wid_control; slotp->resp_b_int_device = bridge->b_int_device; - slotp->resp_b_int_enable = bridge->b_int_enable; - slotp->resp_b_int_host = bridge->b_int_addr[slot].addr; + + if (IS_PIC_SOFT(pcibr_soft)) { + slotp->resp_p_int_enable = bridge->p_int_enable_64; + slotp->resp_p_int_host = bridge->p_int_addr_64[slot]; + } else { + slotp->resp_b_int_enable = bridge->b_int_enable; + slotp->resp_b_int_host = bridge->b_int_addr[slot].addr; + } if (COPYOUT(slotp, respp, sizeof(*respp))) { return(EFAULT); } - kmem_free(slotp, sizeof(*slotp)); + snia_kmem_free(slotp, sizeof(*slotp)); return(0); } @@ -395,19 +458,26 @@ pcibr_slot_query(devfs_handle_t pcibr_vhdl, pcibr_slot_req_t reqp) { pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl); - pciio_slot_t slot = reqp->req_slot; + pciio_slot_t slot; pciio_slot_t tmp_slot; pcibr_slot_info_resp_t respp = reqp->req_respp.query; int size = reqp->req_size; - int error; + int error = 0; /* Make sure that we are dealing with a bridge device vertex */ if (!pcibr_soft) { return(PCI_NOT_A_BRIDGE); } + /* req_slot is the 'external' slot number, convert for internal use */ + slot = PCIBR_SLOT_TO_DEVICE(pcibr_soft, reqp->req_slot); + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_HOTPLUG, pcibr_vhdl, + "pcibr_slot_query: pcibr_soft=0x%x, slot=%d, reqp=0x%x\n", + pcibr_soft, slot, reqp)); + /* Make sure that we have a valid PCI slot number or PCIIO_SLOT_NONE */ - if ((!PCIBR_VALID_SLOT(slot)) && (slot != PCIIO_SLOT_NONE)) { + if ((!PCIBR_VALID_SLOT(pcibr_soft, slot)) && (slot != PCIIO_SLOT_NONE)) { return(PCI_NOT_A_SLOT); } @@ -422,32 +492,37 @@ return(PCI_RESP_AREA_TOO_SMALL); } +#ifdef PIC_LATER /* Acquire read access to the bus */ mrlock(pcibr_soft->bs_bus_lock, MR_ACCESS, PZERO); - +#endif error = pcibr_slot_info_return(pcibr_soft, slot, respp); +#ifdef PIC_LATER /* Release the bus lock */ mrunlock(pcibr_soft->bs_bus_lock); - +#endif return(error); } /* Return information for all the slots */ - for (tmp_slot = 0; tmp_slot < 8; tmp_slot++) { + for (tmp_slot = pcibr_soft->bs_min_slot; + tmp_slot < PCIBR_NUM_SLOTS(pcibr_soft); tmp_slot++) { if (size < sizeof(*respp)) { return(PCI_RESP_AREA_TOO_SMALL); } +#ifdef PIC_LATER /* Acquire read access to the bus */ mrlock(pcibr_soft->bs_bus_lock, MR_ACCESS, PZERO); - +#endif error = pcibr_slot_info_return(pcibr_soft, tmp_slot, respp); +#ifdef PCI_LATER /* Release the bus lock */ mrunlock(pcibr_soft->bs_bus_lock); - +#endif if (error) { return(error); } @@ -458,60 +533,92 @@ return(error); } -#endif /* LATER */ -/* FIXME: there should be a better way to do this. - * pcibr_attach() needs PCI_ADDR_SPACE_LIMITS_STORE +#if 0 +/* + * pcibr_slot_reset + * Reset the PCI device in the particular slot. + * + * The Xbridge does not comply with the PCI Specification + * when resetting an indiviaudl slot. An individual slot is + * is reset by toggling the slot's bit in the Xbridge Control + * Register. The Xbridge will assert the target slot's + * (non-bussed) RST signal, but does not assert the (bussed) + * REQ64 signal as required by the specification. As + * designed, the Xbridge cannot assert the REQ64 signal + * becuase it may interfere with a bus transaction in progress. + * The practical effects of this Xbridge implementation is + * device dependent; it probably will not adversely effect + * 32-bit cards, but may disable 64-bit data transfers by those + * cards that normally support 64-bit data transfers. + * + * The Xbridge will assert REQ64 when all four slots are reset + * by simultaneously toggling all four slot reset bits in the + * Xbridge Control Register. This is basically a PCI bus reset + * and asserting the (bussed) REQ64 signal will not interfere + * with any bus transactions in progress. + * + * The Xbridge (and the SN0 Bridge) support resetting only + * four PCI bus slots via the (X)bridge Control Register. + * + * To reset an individual slot for the PCI Hot-Plug feature + * use the L1 console commands to power-down and then + * power-up the slot, or use the kernel infrastructure + * functions to power-down/up the slot when they are + * implemented for SN1. */ +int +pcibr_slot_reset(devfs_handle_t pcibr_vhdl, pciio_slot_t slot) +{ + pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl); + bridge_t *bridge; + bridgereg_t ctrlreg,tmp; + volatile bridgereg_t *wrb_flush; -/* - * PCI_ADDR_SPACE_LIMITS_LOAD - * Gets the current values of - * pci io base, - * pci io last, - * pci low memory base, - * pci low memory last, - * pci high memory base, - * pci high memory last - */ -#define PCI_ADDR_SPACE_LIMITS_LOAD() \ - pci_io_fb = pcibr_soft->bs_spinfo.pci_io_base; \ - pci_io_fl = pcibr_soft->bs_spinfo.pci_io_last; \ - pci_lo_fb = pcibr_soft->bs_spinfo.pci_swin_base; \ - pci_lo_fl = pcibr_soft->bs_spinfo.pci_swin_last; \ - pci_hi_fb = pcibr_soft->bs_spinfo.pci_mem_base; \ - pci_hi_fl = pcibr_soft->bs_spinfo.pci_mem_last; -/* - * PCI_ADDR_SPACE_LIMITS_STORE - * Sets the current values of - * pci io base, - * pci io last, - * pci low memory base, - * pci low memory last, - * pci high memory base, - * pci high memory last - */ -#define PCI_ADDR_SPACE_LIMITS_STORE() \ - pcibr_soft->bs_spinfo.pci_io_base = pci_io_fb; \ - pcibr_soft->bs_spinfo.pci_io_last = pci_io_fl; \ - pcibr_soft->bs_spinfo.pci_swin_base = pci_lo_fb; \ - pcibr_soft->bs_spinfo.pci_swin_last = pci_lo_fl; \ - pcibr_soft->bs_spinfo.pci_mem_base = pci_hi_fb; \ - pcibr_soft->bs_spinfo.pci_mem_last = pci_hi_fl; - -#define PCI_ADDR_SPACE_LIMITS_PRINT() \ - printf("+++++++++++++++++++++++\n" \ - "IO base 0x%x last 0x%x\n" \ - "SWIN base 0x%x last 0x%x\n" \ - "MEM base 0x%x last 0x%x\n" \ - "+++++++++++++++++++++++\n", \ - pcibr_soft->bs_spinfo.pci_io_base, \ - pcibr_soft->bs_spinfo.pci_io_last, \ - pcibr_soft->bs_spinfo.pci_swin_base, \ - pcibr_soft->bs_spinfo.pci_swin_last, \ - pcibr_soft->bs_spinfo.pci_mem_base, \ - pcibr_soft->bs_spinfo.pci_mem_last); + if (!pcibr_soft) + return(EINVAL); + + if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) + return(EINVAL); + + /* Enable the DMA operations from this device of the xtalk widget + * (PCI host bridge in this case). + */ + xtalk_widgetdev_enable(pcibr_soft->bs_conn, slot); + + /* Set the reset slot bit in the bridge's wid control register + * to reset the PCI slot + */ + bridge = pcibr_soft->bs_base; + + /* Read the bridge widget control and clear out the reset pin + * bit for the corresponding slot. + */ + tmp = ctrlreg = bridge->b_wid_control; + + tmp &= ~BRIDGE_CTRL_RST_PIN(slot); + + bridge->b_wid_control = tmp; + tmp = bridge->b_wid_control; + + /* Restore the old control register back. + * NOTE : PCI card gets reset when the reset pin bit + * changes from 0 (set above) to 1 (going to be set now). + */ + + bridge->b_wid_control = ctrlreg; + /* Flush the write buffers if any !! */ + wrb_flush = &(bridge->b_wr_req_buf[slot].reg); + while (*wrb_flush); + + return(0); +} +#endif + +#define PROBE_LOCK 0 /* FIXME: we're attempting to lock around accesses + * to b_int_enable. This hangs pcibr_probe_slot() + */ /* * pcibr_slot_info_init @@ -534,12 +641,12 @@ pciio_vendor_id_t vendor; pciio_device_id_t device; unsigned htype; + unsigned lt_time; + int nbars; cfg_p wptr; + cfg_p pcix_cap; int win; pciio_space_t space; - iopaddr_t pci_io_fb, pci_io_fl; - iopaddr_t pci_lo_fb, pci_lo_fl; - iopaddr_t pci_hi_fb, pci_hi_fl; int nfunc; pciio_function_t rfunc; int func; @@ -552,7 +659,7 @@ return(EINVAL); bridge = pcibr_soft->bs_base; - if (!PCIBR_VALID_SLOT(slot)) + if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) return(EINVAL); /* If we have a host slot (eg:- IOC3 has 2 PCI slots and the initialization @@ -566,28 +673,35 @@ if (pcibr_is_slot_sys_critical(pcibr_vhdl, slot)) return(EPERM); - /* Load the current values of allocated PCI address spaces */ - PCI_ADDR_SPACE_LIMITS_LOAD(); - /* Try to read the device-id/vendor-id from the config space */ - cfgw = bridge->b_type0_cfg_dev[slot].l; + cfgw = pcibr_slot_config_addr(bridge, slot, 0); +#if PROBE_LOCK + s = pcibr_lock(pcibr_soft); +#endif if (pcibr_probe_slot(bridge, cfgw, &idword)) return(ENODEV); +#if PROBE_LOCK + pcibr_unlock(pcibr_soft, s); +#endif slotp = &pcibr_soft->bs_slot[slot]; slotp->slot_status |= SLOT_POWER_UP; vendor = 0xFFFF & idword; + device = 0xFFFF & (idword >> 16); + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_PROBE, pcibr_vhdl, + "pcibr_slot_info_init: slot=%d, vendor=0x%x, device=0x%x\n", + PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), vendor, device)); + /* If the vendor id is not valid then the slot is not populated * and we are done. */ if (vendor == 0xFFFF) return(ENODEV); - device = 0xFFFF & (idword >> 16); - htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1); - + htype = do_pcibr_config_get(IS_PIC_SOFT(pcibr_soft), cfgw, PCI_CFG_HEADER_TYPE, 1); nfunc = 1; rfunc = PCIIO_FUNC_NONE; pfail = 0; @@ -599,11 +713,17 @@ if (htype & 0x80) { /* MULTIFUNCTION */ for (func = 1; func < 8; ++func) { - cfgw = bridge->b_type0_cfg_dev[slot].f[func].l; + cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0); +#if PROBE_LOCK + s = pcibr_lock(pcibr_soft); +#endif if (pcibr_probe_slot(bridge, cfgw, &idwords[func])) { pfail |= 1 << func; continue; } +#if PROBE_LOCK + pcibr_unlock(pcibr_soft, s); +#endif vendor = 0xFFFF & idwords[func]; if (vendor == 0xFFFF) { pfail |= 1 << func; @@ -612,7 +732,7 @@ nfunc = func + 1; rfunc = 0; } - cfgw = bridge->b_type0_cfg_dev[slot].l; + cfgw = pcibr_slot_config_addr(bridge, slot, 0); } NEWA(pcibr_infoh, nfunc); @@ -627,39 +747,162 @@ continue; idword = idwords[func]; - cfgw = bridge->b_type0_cfg_dev[slot].f[func].l; + cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0); device = 0xFFFF & (idword >> 16); - htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1); + htype = do_pcibr_config_get(IS_PIC_SOFT(pcibr_soft), cfgw, PCI_CFG_HEADER_TYPE, 1); rfunc = func; } htype &= 0x7f; if (htype != 0x00) { - printk(KERN_WARNING "%s pcibr: pci slot %d func %d has strange header type 0x%x\n", + printk(KERN_WARNING + "%s pcibr: pci slot %d func %d has strange header type 0x%x\n", pcibr_soft->bs_name, slot, func, htype); - continue; + nbars = 2; + } else { + nbars = PCI_CFG_BASE_ADDRS; + } + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_CONFIG, pcibr_vhdl, + "pcibr_slot_info_init: slot=%d, func=%d, cfgw=0x%x\n", + PCIBR_DEVICE_TO_SLOT(pcibr_soft,slot), func, cfgw)); + +#ifdef PIC_LATER + /* + * Check for a Quad ATM PCI "card" and return all the PCI bus + * memory and I/O space. This will work-around an apparent + * hardware problem with the Quad ATM XIO card handling large + * PIO addresses. Releasing all the space for use by the card + * will lower the PIO addresses with the PCI bus address space. + * This is OK since the PROM did not assign any BAR addresses. + * + * Only release all the PCI bus addresses once. + * + */ + if ((vendor == LINC_VENDOR_ID_NUM) && (device == LINC_DEVICE_ID_NUM)) { + iopaddr_t prom_base_addr = pcibr_soft->bs_xid << 24; + int prom_base_size = 0x1000000; + + if (!(pcibr_soft->bs_bus_addr_status & PCIBR_BUS_ADDR_MEM_FREED)) { + pciio_device_win_populate(&pcibr_soft->bs_mem_win_map, + prom_base_addr, prom_base_size); + pcibr_soft->bs_bus_addr_status |= PCIBR_BUS_ADDR_MEM_FREED; + } + + if (!(pcibr_soft->bs_bus_addr_status & PCIBR_BUS_ADDR_IO_FREED)) { + pciio_device_win_populate(&pcibr_soft->bs_io_win_map, + prom_base_addr, prom_base_size); + pcibr_soft->bs_bus_addr_status |= PCIBR_BUS_ADDR_IO_FREED; + } + } +#endif /* PIC_LATER */ + + /* + * If the latency timer has already been set, by prom or by the + * card itself, use that value. Otherwise look at the device's + * 'min_gnt' and attempt to calculate a latency time. + * + * NOTE: For now if the device is on the 'real time' arbitration + * ring we dont set the latency timer. + * + * WAR: SGI's IOC3 and RAD devices target abort if you write a + * single byte into their config space. So don't set the Latency + * Timer for these devices + */ + + lt_time = do_pcibr_config_get(IS_PIC_SOFT(pcibr_soft), cfgw, PCI_CFG_LATENCY_TIMER, 1); + + if ((lt_time == 0) && !(bridge->b_device[slot].reg & BRIDGE_DEV_RT) && + !((vendor == IOC3_VENDOR_ID_NUM) && + ( +#ifdef PIC_LATER + (device == IOC3_DEVICE_ID_NUM) || + (device == LINC_DEVICE_ID_NUM) || +#endif + (device == 0x5 /* RAD_DEV */)))) { + unsigned min_gnt; + unsigned min_gnt_mult; + + /* 'min_gnt' indicates how long of a burst period a device + * needs in increments of 250ns. But latency timer is in + * PCI clock cycles, so a conversion is needed. + */ + min_gnt = do_pcibr_config_get(IS_PIC_SOFT(pcibr_soft), cfgw, PCI_MIN_GNT, 1); + + if (IS_133MHZ(pcibr_soft)) + min_gnt_mult = 32; /* 250ns @ 133MHz in clocks */ + else if (IS_100MHZ(pcibr_soft)) + min_gnt_mult = 24; /* 250ns @ 100MHz in clocks */ + else if (IS_66MHZ(pcibr_soft)) + min_gnt_mult = 16; /* 250ns @ 66MHz, in clocks */ + else + min_gnt_mult = 8; /* 250ns @ 33MHz, in clocks */ + + if ((min_gnt != 0) && ((min_gnt * min_gnt_mult) < 256)) + lt_time = (min_gnt * min_gnt_mult); + else + lt_time = 4 * min_gnt_mult; /* 1 micro second */ + + do_pcibr_config_set(IS_PIC_SOFT(pcibr_soft), cfgw, PCI_CFG_LATENCY_TIMER, 1, lt_time); + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_CONFIG, pcibr_vhdl, + "pcibr_slot_info_init: set Latency Timer for slot=%d, " + "func=%d, to 0x%x\n", + PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func, lt_time)); + } + + /* Get the PCI-X capability if running in PCI-X mode. If the func + * doesnt have a pcix capability, allocate a PCIIO_VENDOR_ID_NONE + * pcibr_info struct so the device driver for that function is not + * called. + */ + if (IS_PCIX(pcibr_soft)) { + if (!(pcix_cap = pcibr_find_capability(cfgw, PCI_CAP_PCIX))) { + printk(KERN_WARNING +#if defined(SUPPORT_PRINTING_V_FORMAT) + "%v: Bus running in PCI-X mode, But card in slot %d, " + "func %d not PCI-X capable\n", pcibr_vhdl, slot, func); +#else + "0x%lx: Bus running in PCI-X mode, But card in slot %d, " + "func %d not PCI-X capable\n", (unsigned long)pcibr_vhdl, slot, func); +#endif + pcibr_device_info_new(pcibr_soft, slot, PCIIO_FUNC_NONE, + PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE); + continue; + } + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_CONFIG, pcibr_vhdl, + "pcibr_slot_info_init: PCI-X capability at 0x%x for " + "slot=%d, func=%d\n", + pcix_cap, PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func)); + } else { + pcix_cap = NULL; } -#if DEBUG && ATTACH_DEBUG - printk(KERN_NOTICE - "%s pcibr: pci slot %d func %d: vendor 0x%x device 0x%x", - pcibr_soft->bs_name, slot, func, vendor, device); -#endif pcibr_info = pcibr_device_info_new (pcibr_soft, slot, rfunc, vendor, device); + + /* Keep a running total of the number of PIC-X functions on the bus + * and the number of max outstanding split trasnactions that they + * have requested. NOTE: "pcix_cap != NULL" implies IS_PCIX() + */ + pcibr_info->f_pcix_cap = (cap_pcix_type0_t *)pcix_cap; + if (pcibr_info->f_pcix_cap) { + int max_out; /* max outstanding splittrans from status reg */ + + pcibr_soft->bs_pcix_num_funcs++; + max_out = pcibr_info->f_pcix_cap->pcix_type0_status.max_out_split; + pcibr_soft->bs_pcix_split_tot += max_splittrans_to_numbuf[max_out]; + } + conn_vhdl = pciio_device_info_register(pcibr_vhdl, &pcibr_info->f_c); if (func == 0) slotp->slot_conn = conn_vhdl; -#ifdef LITTLE_ENDIAN - cmd_reg = cfgw[(PCI_CFG_COMMAND ^ 4) / 4]; -#else - cmd_reg = cfgw[PCI_CFG_COMMAND / 4]; -#endif + cmd_reg = do_pcibr_config_get(IS_PIC_SOFT(pcibr_soft), cfgw, PCI_CFG_COMMAND, 4); wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4; - for (win = 0; win < PCI_CFG_BASE_ADDRS; ++win) { + for (win = 0; win < nbars; ++win) { iopaddr_t base, mask, code; size_t size; @@ -706,11 +949,7 @@ * this could be pushed up into pciio, when we * start supporting more PCI providers. */ -#ifdef LITTLE_ENDIAN - base = wptr[((win*4)^4)/4]; -#else - base = wptr[win]; -#endif + base = do_pcibr_config_get(IS_PIC_SOFT(pcibr_soft), wptr, (win * 4), 4); if (base & PCI_BA_IO_SPACE) { /* BASE is in I/O space. */ @@ -736,11 +975,7 @@ } else if (base & 0xC0000000) { base = 0; /* outside permissable range */ } else if ((code == PCI_BA_MEM_64BIT) && -#ifdef LITTLE_ENDIAN - (wptr[(((win + 1)*4)^4)/4] != 0)) { -#else - (wptr[win + 1] != 0)) { -#endif /* LITTLE_ENDIAN */ + (do_pcibr_config_get(IS_PIC_SOFT(pcibr_soft), wptr, ((win + 1)*4), 4) != 0)) { base = 0; /* outside permissable range */ } } @@ -748,13 +983,8 @@ if (base != 0) { /* estimate size */ size = base & -base; } else { /* calculate size */ -#ifdef LITTLE_ENDIAN - wptr[((win*4)^4)/4] = ~0; /* turn on all bits */ - size = wptr[((win*4)^4)/4]; /* get stored bits */ -#else - wptr[win] = ~0; /* turn on all bits */ - size = wptr[win]; /* get stored bits */ -#endif /* LITTLE_ENDIAN */ + do_pcibr_config_set(IS_PIC_SOFT(pcibr_soft), wptr, (win * 4), 4, ~0); /* write 1's */ + size = do_pcibr_config_get(IS_PIC_SOFT(pcibr_soft), wptr, (win * 4), 4); /* read back */ size &= mask; /* keep addr */ size &= -size; /* keep lsbit */ if (size == 0) @@ -765,28 +995,6 @@ pcibr_info->f_window[win].w_base = base; pcibr_info->f_window[win].w_size = size; - /* - * If this window already has PCI space - * allocated for it, "subtract" that space from - * our running freeblocks. Don't worry about - * overlaps in existing allocated windows; we - * may be overstating their sizes anyway. - */ - - if (base && size) { - if (space == PCIIO_SPACE_IO) { - pcibr_freeblock_sub(&pci_io_fb, - &pci_io_fl, - base, size); - } else { - pcibr_freeblock_sub(&pci_lo_fb, - &pci_lo_fl, - base, size); - pcibr_freeblock_sub(&pci_hi_fb, - &pci_hi_fl, - base, size); - } - } #if defined(IOC3_VENDOR_ID_NUM) && defined(IOC3_DEVICE_ID_NUM) /* * IOC3 BASE_ADDR* BUG WORKAROUND @@ -825,21 +1033,55 @@ #endif if (code == PCI_BA_MEM_64BIT) { win++; /* skip upper half */ -#ifdef LITTLE_ENDIAN - wptr[((win*4)^4)/4] = 0; /* which must be zero */ -#else - wptr[win] = 0; /* which must be zero */ -#endif /* LITTLE_ENDIAN */ + do_pcibr_config_set(IS_PIC_SOFT(pcibr_soft), wptr, (win * 4), 4, 0); /* must be zero */ } } /* next win */ } /* next func */ - /* Store back the values for allocated PCI address spaces */ - PCI_ADDR_SPACE_LIMITS_STORE(); return(0); } /* + * pcibr_find_capability + * Walk the list of capabilities (if it exists) looking for + * the requested capability. Return a cfg_p pointer to the + * capability if found, else return NULL + */ +cfg_p +pcibr_find_capability(cfg_p cfgw, + unsigned capability) +{ + unsigned cap_nxt; + unsigned cap_id; + int defend_against_circular_linkedlist = 0; + + /* Check to see if there is a capabilities pointer in the cfg header */ + if (!(do_pcibr_config_get(1, cfgw, PCI_CFG_STATUS, 2) & PCI_STAT_CAP_LIST)) { + return (NULL); + } + + /* + * Read up the capabilities head pointer from the configuration header. + * Capabilities are stored as a linked list in the lower 48 dwords of + * config space and are dword aligned. (Note: spec states the least two + * significant bits of the next pointer must be ignored, so we mask + * with 0xfc). + */ + cap_nxt = (do_pcibr_config_get(1, cfgw, PCI_CAPABILITIES_PTR, 1) & 0xfc); + + while (cap_nxt && (defend_against_circular_linkedlist <= 48)) { + cap_id = do_pcibr_config_get(1, cfgw, cap_nxt, 1); + if (cap_id == capability) { + return ((cfg_p)((char *)cfgw + cap_nxt)); + } + cap_nxt = (do_pcibr_config_get(1, cfgw, cap_nxt+1, 1) & 0xfc); + defend_against_circular_linkedlist++; + } + + return (NULL); +} + +/* * pcibr_slot_info_free * Remove all the PCI infrastructural information associated * with a particular PCI device. @@ -854,7 +1096,10 @@ pcibr_soft = pcibr_soft_get(pcibr_vhdl); - if (!pcibr_soft || !PCIBR_VALID_SLOT(slot)) + if (!pcibr_soft) + return(EINVAL); + + if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) return(EINVAL); nfunc = pcibr_soft->bs_slot[slot].bss_ninfo; @@ -868,6 +1113,109 @@ return(0); } +/* + * pcibr_slot_pcix_rbar_init + * Allocate RBARs to the PCI-X functions on a given device + */ +int +pcibr_slot_pcix_rbar_init(pcibr_soft_t pcibr_soft, + pciio_slot_t slot) +{ + pcibr_info_h pcibr_infoh; + pcibr_info_t pcibr_info; + char tmp_str[256]; + int nfunc; + int func; + + if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) + return(EINVAL); + + if ((nfunc = pcibr_soft->bs_slot[slot].bss_ninfo) < 1) + return(EINVAL); + + if (!(pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos)) + return(EINVAL); + + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RBAR, pcibr_soft->bs_vhdl, + "pcibr_slot_pcix_rbar_init for slot %d\n", + PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot))); + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RBAR, pcibr_soft->bs_vhdl, + "\tslot/func\trequested\tgiven\tinuse\tavail\n")); + + for (func = 0; func < nfunc; ++func) { + cap_pcix_type0_t *pcix_cap_p; + cap_pcix_stat_reg_t *pcix_statreg_p; + cap_pcix_cmd_reg_t *pcix_cmdreg_p; + int num_rbar; + + if (!(pcibr_info = pcibr_infoh[func])) + continue; + + if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) + continue; + + if (!(pcix_cap_p = pcibr_info->f_pcix_cap)) + continue; + + pcix_statreg_p = &pcix_cap_p->pcix_type0_status; + pcix_cmdreg_p = &pcix_cap_p->pcix_type0_command; + + /* If there are enough RBARs to satify the number of "max outstanding + * transactions" each function requested (bs_pcix_rbar_percent_allowed + * is 100%), then give each function what it requested, otherwise give + * the functions a "percentage of what they requested". + */ + if (pcibr_soft->bs_pcix_rbar_percent_allowed >= 100) { + pcix_cmdreg_p->max_split = pcix_statreg_p->max_out_split; + num_rbar = max_splittrans_to_numbuf[pcix_cmdreg_p->max_split]; + pcibr_soft->bs_pcix_rbar_inuse += num_rbar; + pcibr_soft->bs_pcix_rbar_avail -= num_rbar; + pcix_cmdreg_p->max_mem_read_cnt = pcix_statreg_p->max_mem_read_cnt; + } else { + int index; /* index into max_splittrans_to_numbuf table */ + int max_out; /* max outstanding transactions given to func */ + + /* Calculate the percentage of RBARs this function can have. + * NOTE: Every function gets at least 1 RBAR (thus the "+1"). + * bs_pcix_rbar_percent_allowed is the percentage of what was + * requested less this 1 RBAR that all functions automatically + * gets + */ + max_out = ((max_splittrans_to_numbuf[pcix_statreg_p->max_out_split] + * pcibr_soft->bs_pcix_rbar_percent_allowed) / 100) + 1; + + /* round down the newly caclulated max_out to a valid number in + * max_splittrans_to_numbuf[] + */ + for (index = 0; index < MAX_SPLIT_TABLE-1; index++) + if (max_splittrans_to_numbuf[index + 1] > max_out) + break; + + pcix_cmdreg_p->max_split = index; + num_rbar = max_splittrans_to_numbuf[pcix_cmdreg_p->max_split]; + pcibr_soft->bs_pcix_rbar_inuse += num_rbar; + pcibr_soft->bs_pcix_rbar_avail -= num_rbar; + pcix_cmdreg_p->max_mem_read_cnt = pcix_statreg_p->max_mem_read_cnt; + } + /* + * The kernel only allows functions to have so many variable args, + * attempting to call PCIBR_DEBUG_ALWAYS() with more than 5 printf + * arguments fails so sprintf() it into a temporary string. + */ + if (pcibr_debug_mask & PCIBR_DEBUG_RBAR) { + sprintf(tmp_str,"\t %d/%d \t %d \t %d \t %d \t %d\n", + PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func, + max_splittrans_to_numbuf[pcix_statreg_p->max_out_split], + max_splittrans_to_numbuf[pcix_cmdreg_p->max_split], + pcibr_soft->bs_pcix_rbar_inuse, + pcibr_soft->bs_pcix_rbar_avail); + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RBAR, pcibr_soft->bs_vhdl, + "%s", tmp_str)); + } + } + return(0); +} + int as_debug = 0; /* * pcibr_slot_addr_space_init @@ -878,34 +1226,27 @@ pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl, pciio_slot_t slot) { - pcibr_soft_t pcibr_soft; - pcibr_info_h pcibr_infoh; - pcibr_info_t pcibr_info; + pcibr_soft_t pcibr_soft; + pcibr_info_h pcibr_infoh; + pcibr_info_t pcibr_info; bridge_t *bridge; - iopaddr_t pci_io_fb, pci_io_fl; - iopaddr_t pci_lo_fb, pci_lo_fl; - iopaddr_t pci_hi_fb, pci_hi_fl; - size_t align; - iopaddr_t mask; - int nbars; - int nfunc; - int func; - int win; + size_t align_slot; + iopaddr_t mask; + int nbars; + int nfunc; + int func; + int win; + int rc = 0; pcibr_soft = pcibr_soft_get(pcibr_vhdl); - if (!pcibr_soft || !PCIBR_VALID_SLOT(slot)) + if (!pcibr_soft) return(EINVAL); - bridge = pcibr_soft->bs_base; - - /* Get the current values for the allocated PCI address spaces */ - PCI_ADDR_SPACE_LIMITS_LOAD(); + if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) + return(EINVAL); - if (as_debug) -#ifdef LATER - PCI_ADDR_SPACE_LIMITS_PRINT(); -#endif + bridge = pcibr_soft->bs_base; /* allocate address space, * for windows that have not been @@ -934,10 +1275,7 @@ * the entire "lo" area is only a * megabyte, total ... */ - align = (slot < 2) ? 0x200000 : 0x100000; - mask = -align; - pci_io_fb = (pci_io_fb + align - 1) & mask; - pci_hi_fb = (pci_hi_fb + align - 1) & mask; + align_slot = (slot < 2) ? 0x200000 : 0x100000; for (func = 0; func < nfunc; ++func) { cfg_p cfgw; @@ -945,7 +1283,9 @@ pciio_space_t space; iopaddr_t base; size_t size; - cfg_p pci_cfg_cmd_reg_p; +#ifdef PCI_LATER + char tmp_str[256]; +#endif unsigned pci_cfg_cmd_reg; unsigned pci_cfg_cmd_reg_add = 0; @@ -957,13 +1297,15 @@ if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) continue; - cfgw = bridge->b_type0_cfg_dev[slot].f[func].l; + cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0); wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4; - nbars = PCI_CFG_BASE_ADDRS; + if ((do_pcibr_config_get(IS_PIC_SOFT(pcibr_soft), cfgw, PCI_CFG_HEADER_TYPE, 1) & 0x7f) != 0) + nbars = 2; + else + nbars = PCI_CFG_BASE_ADDRS; for (win = 0; win < nbars; ++win) { - space = pcibr_info->f_window[win].w_space; base = pcibr_info->f_window[win].w_base; size = pcibr_info->f_window[win].w_size; @@ -972,77 +1314,93 @@ continue; if (base >= size) { -#if DEBUG && PCI_DEBUG - printk("pcibr: slot %d func %d window %d is in %d[0x%x..0x%x], alloc by prom\n", - slot, func, win, space, base, base + size - 1); -#endif + /* + * The kernel only allows functions to have so many variable + * args attempting to call PCIBR_DEBUG_ALWAYS() with more than + * 5 printf arguments fails so sprintf() it into a temporary + * string (tmp_str). + */ +#if defined(SUPPORT_PRINTING_R_FORMAT) + if (pcibr_debug_mask & PCIBR_DEBUG_BAR) { + sprintf(tmp_str, "pcibr_slot_addr_space_init: slot=%d, " + "func=%d win %d is in %r [0x%x..0x%x], allocated by " + "prom\n", PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), + func, win, space, space_desc, base, base + size - 1); + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl, + "%s",tmp_str)); + } +#endif /* SUPPORT_PRINTING_R_FORMAT */ continue; /* already allocated */ } - align = size; /* ie. 0x00001000 */ - if (align < _PAGESZ) - align = _PAGESZ; /* ie. 0x00004000 */ - mask = -align; /* ie. 0xFFFFC000 */ switch (space) { case PCIIO_SPACE_IO: - base = (pci_io_fb + align - 1) & mask; - if ((base + size) > pci_io_fl) { - base = 0; - break; - } - pci_io_fb = base + size; + base = pcibr_bus_addr_alloc(pcibr_soft, + &pcibr_info->f_window[win], + PCIIO_SPACE_IO, + 0, size, align_slot); + if (!base) + rc = ENOSPC; break; case PCIIO_SPACE_MEM: -#ifdef LITTLE_ENDIAN - if ((wptr[((win*4)^4)/4] & PCI_BA_MEM_LOCATION) == -#else - if ((wptr[win] & PCI_BA_MEM_LOCATION) == -#endif /* LITTLE_ENDIAN */ - PCI_BA_MEM_1MEG) { + if ((do_pcibr_config_get(IS_PIC_SOFT(pcibr_soft), wptr, (win * 4), 4) & + PCI_BA_MEM_LOCATION) == PCI_BA_MEM_1MEG) { + int align = size; /* ie. 0x00001000 */ + + if (align < _PAGESZ) + align = _PAGESZ; /* ie. 0x00004000 */ + /* allocate from 20-bit PCI space */ - base = (pci_lo_fb + align - 1) & mask; - if ((base + size) > pci_lo_fl) { - base = 0; - break; - } - pci_lo_fb = base + size; + base = pcibr_bus_addr_alloc(pcibr_soft, + &pcibr_info->f_window[win], + PCIIO_SPACE_MEM, + 0, size, align); + if (!base) + rc = ENOSPC; } else { /* allocate from 32-bit or 64-bit PCI space */ - base = (pci_hi_fb + align - 1) & mask; - if ((base + size) > pci_hi_fl) { - base = 0; - break; - } - pci_hi_fb = base + size; + base = pcibr_bus_addr_alloc(pcibr_soft, + &pcibr_info->f_window[win], + PCIIO_SPACE_MEM32, + 0, size, align_slot); + if (!base) + rc = ENOSPC; } break; default: base = 0; -#if DEBUG && PCI_DEBUG - printk("pcibr: slot %d window %d had bad space code %d\n", - slot, win, space); -#endif + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl, + "pcibr_slot_addr_space_init: slot=%d, window %d " + "had bad space code %d\n", + PCIBR_DEVICE_TO_SLOT(pcibr_soft,slot), win, space)); } pcibr_info->f_window[win].w_base = base; -#ifdef LITTLE_ENDIAN - wptr[((win*4)^4)/4] = base; -#if DEBUG && PCI_DEBUG - printk("Setting base address 0x%p base 0x%x\n", &(wptr[((win*4)^4)/4]), base); -#endif -#else - wptr[win] = base; -#endif /* LITTLE_ENDIAN */ + do_pcibr_config_set(IS_PIC_SOFT(pcibr_soft), wptr, (win * 4), 4, base); -#if DEBUG && PCI_DEBUG - if (base >= size) - printk("pcibr: slot %d func %d window %d is in %d [0x%x..0x%x], alloc by pcibr\n", - slot, func, win, space, base, base + size - 1); - else - printk("pcibr: slot %d func %d window %d, unable to alloc 0x%x in 0x%p\n", - slot, func, win, size, space); -#endif +#if defined(SUPPORT_PRINTING_R_FORMAT) + if (pcibr_debug_mask & PCIBR_DEBUG_BAR) { + if (base >= size) { + sprintf(tmp_str,"pcibr_slot_addr_space_init: slot=%d, func=" + "%d, win %d is in %r[0x%x..0x%x], " + "allocated by pcibr\n", + PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), + func, win, space, space_desc, base, + base + size - 1); + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl, + "%s",tmp_str)); + } + else { + sprintf(tmp_str,"pcibr_slot_addr_space_init: slot=%d, func=" + "%d, win %d, unable to alloc 0x%x in %r\n", + PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), + func, win, size, space, space_desc); + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl, + "%s",tmp_str)); + } + } +#endif /* SUPPORT_PRINTING_R_FORMAT */ } /* next base */ /* @@ -1055,34 +1413,23 @@ (pcibr_soft->bs_slot[slot].bss_device_id != IOC3_DEVICE_ID_NUM)) { wptr = cfgw + PCI_EXPANSION_ROM / 4; -#ifdef LITTLE_ENDIAN - wptr[1] = 0xFFFFF000; - mask = wptr[1]; -#else - *wptr = 0xFFFFF000; - mask = *wptr; -#endif /* LITTLE_ENDIAN */ + do_pcibr_config_set(IS_PIC_SOFT(pcibr_soft), wptr, 0, 4, 0xFFFFF000); + mask = do_pcibr_config_get(IS_PIC_SOFT(pcibr_soft), wptr, 0, 4); if (mask & 0xFFFFF000) { size = mask & -mask; - align = size; - if (align < _PAGESZ) - align = _PAGESZ; - mask = -align; - base = (pci_hi_fb + align - 1) & mask; - if ((base + size) > pci_hi_fl) - base = size = 0; + base = pcibr_bus_addr_alloc(pcibr_soft, + &pcibr_info->f_rwindow, + PCIIO_SPACE_MEM32, + 0, size, align_slot); + if (!base) + rc = ENOSPC; else { - pci_hi_fb = base + size; -#ifdef LITTLE_ENDIAN - wptr[1] = base; -#else - *wptr = base; -#endif /* LITTLE_ENDIAN */ -#if DEBUG && PCI_DEBUG - printk("%s/%d ROM in 0x%lx..0x%lx (alloc by pcibr)\n", - pcibr_soft->bs_name, slot, - base, base + size - 1); -#endif + do_pcibr_config_set(IS_PIC_SOFT(pcibr_soft), wptr, 0, 4, base); + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl, + "pcibr_slot_addr_space_init: slot=%d, func=%d, " + "ROM in [0x%X..0x%X], allocated by pcibr\n", + PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), + func, base, base + size - 1)); } } } @@ -1116,30 +1463,25 @@ pci_cfg_cmd_reg_add |= PCI_CMD_BUS_MASTER; - pci_cfg_cmd_reg_p = cfgw + PCI_CFG_COMMAND / 4; - pci_cfg_cmd_reg = *pci_cfg_cmd_reg_p; + pci_cfg_cmd_reg = do_pcibr_config_get(IS_PIC_SOFT(pcibr_soft), cfgw, PCI_CFG_COMMAND, 4); + #if PCI_FBBE /* XXX- check here to see if dev can do fast-back-to-back */ if (!((pci_cfg_cmd_reg >> 16) & PCI_STAT_F_BK_BK_CAP)) fast_back_to_back_enable = 0; #endif pci_cfg_cmd_reg &= 0xFFFF; if (pci_cfg_cmd_reg_add & ~pci_cfg_cmd_reg) - *pci_cfg_cmd_reg_p = pci_cfg_cmd_reg | pci_cfg_cmd_reg_add; - + do_pcibr_config_set(IS_PIC_SOFT(pcibr_soft), cfgw, PCI_CFG_COMMAND, 4, + pci_cfg_cmd_reg | pci_cfg_cmd_reg_add); } /* next func */ - - /* Now that we have allocated new chunks of PCI address spaces to this - * card we need to update the bookkeeping values which indicate - * the current PCI address space allocations. - */ - PCI_ADDR_SPACE_LIMITS_STORE(); - return(0); + return(rc); } /* * pcibr_slot_device_init * Setup the device register in the bridge for this PCI slot. */ + int pcibr_slot_device_init(devfs_handle_t pcibr_vhdl, pciio_slot_t slot) @@ -1150,7 +1492,10 @@ pcibr_soft = pcibr_soft_get(pcibr_vhdl); - if (!pcibr_soft || !PCIBR_VALID_SLOT(slot)) + if (!pcibr_soft) + return(EINVAL); + + if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) return(EINVAL); bridge = pcibr_soft->bs_base; @@ -1161,21 +1506,28 @@ */ devreg = bridge->b_device[slot].reg; devreg &= ~BRIDGE_DEV_PAGE_CHK_DIS; - devreg |= BRIDGE_DEV_COH | BRIDGE_DEV_VIRTUAL_EN; -#ifdef LITTLE_ENDIAN - devreg |= BRIDGE_DEV_DEV_SWAP; -#endif + + /* + * PIC WAR. PV# 855271 + * Don't enable virtual channels in the PIC by default. + * Can cause problems with 32-bit devices. (The bit is only intended + * for 64-bit devices). We set the bit in pcibr_try_set_device() + * if we're 64-bit and requesting virtual channels. + */ + if (IS_PIC_SOFT(pcibr_soft) && PCIBR_WAR_ENABLED(PV855271, pcibr_soft)) + devreg |= BRIDGE_DEV_COH; + else + devreg |= BRIDGE_DEV_COH | BRIDGE_DEV_VIRTUAL_EN; pcibr_soft->bs_slot[slot].bss_device = devreg; bridge->b_device[slot].reg = devreg; -#if DEBUG && PCI_DEBUG - printk("pcibr Device(%d): 0x%lx\n", slot, bridge->b_device[slot].reg); -#endif - -#if DEBUG && PCI_DEBUG - printk("pcibr: PCI space allocation done.\n"); +#ifdef PIC_LATER + PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DEVREG, pcibr_vhdl, + "pcibr_slot_device_init: Device(%d): %R\n", + slot, devreg, device_bits)); +#else + printk("pcibr_slot_device_init: Device(%d) 0x%x\n", slot, devreg); #endif - return(0); } @@ -1194,7 +1546,10 @@ pcibr_soft = pcibr_soft_get(pcibr_vhdl); - if (!pcibr_soft || !PCIBR_VALID_SLOT(slot)) + if (!pcibr_soft) + return(EINVAL); + + if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) return(EINVAL); slotp = &pcibr_soft->bs_slot[slot]; @@ -1259,17 +1614,25 @@ pcibr_info_t pcibr_info; async_attach_t aa = NULL; int func; - devfs_handle_t xconn_vhdl,conn_vhdl; + devfs_handle_t xconn_vhdl, conn_vhdl; +#ifdef PIC_LATER + devfs_handle_t scsi_vhdl; +#endif int nfunc; int error_func; int error_slot = 0; int error = ENODEV; +#ifdef PIC_LATER + int hwg_err; +#endif pcibr_soft = pcibr_soft_get(pcibr_vhdl); - if (!pcibr_soft || !PCIBR_VALID_SLOT(slot)) + if (!pcibr_soft) return(EINVAL); + if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) + return(EINVAL); if (pcibr_soft->bs_slot[slot].has_host) { return(EPERM); @@ -1303,6 +1666,40 @@ error_func = pciio_device_attach(conn_vhdl, drv_flags); +#ifdef PIC_LATER + /* + * Try to assign well-known SCSI controller numbers for hot-plug + * insert + */ + if (drv_flags) { + + hwg_err = hwgraph_path_lookup(conn_vhdl, EDGE_LBL_SCSI_CTLR "/0", + &scsi_vhdl, NULL); + + if (hwg_err == GRAPH_SUCCESS) + scsi_ctlr_nums_add(baseio_pci_vhdl, scsi_vhdl); + + /* scsi_vhdl will be the final vertex in either the complete path + * on success or a partial path on failure; in either case, + * unreference that vertex. + */ + hwgraph_vertex_unref(scsi_vhdl); + + hwg_err = hwgraph_path_lookup(conn_vhdl, EDGE_LBL_SCSI_CTLR "/1", + &scsi_vhdl, NULL); + + if (hwg_err == GRAPH_SUCCESS) + scsi_ctlr_nums_add(baseio_pci_vhdl, scsi_vhdl); + + /* scsi_vhdl will be the final vertex in either the complete path + * on success or a partial path on failure; in either case, + * unreference that vertex. + */ + hwgraph_vertex_unref(scsi_vhdl); + + } +#endif /* PIC_LATER */ + pcibr_info->f_att_det_error = error_func; if (error_func) @@ -1313,9 +1710,12 @@ } /* next func */ if (error) { - if ((error != ENODEV) && (error != EUNATCH)) + if ((error != ENODEV) && (error != EUNATCH) && (error != EPERM)) { + pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK; pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT; + } } else { + pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK; pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT; } @@ -1344,16 +1744,15 @@ pcibr_soft = pcibr_soft_get(pcibr_vhdl); - if (!pcibr_soft || !PCIBR_VALID_SLOT(slot)) + if (!pcibr_soft) + return(EINVAL); + + if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) return(EINVAL); if (pcibr_soft->bs_slot[slot].has_host) return(EPERM); - /* Make sure that we do not detach a system critical function vertex */ - if(pcibr_is_slot_sys_critical(pcibr_vhdl, slot)) - return(EPERM); - nfunc = pcibr_soft->bs_slot[slot].bss_ninfo; pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos; @@ -1367,6 +1766,14 @@ if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) continue; + if (IS_PCIX(pcibr_soft) && pcibr_info->f_pcix_cap) { + int max_out; + + pcibr_soft->bs_pcix_num_funcs--; + max_out = pcibr_info->f_pcix_cap->pcix_type0_status.max_out_split; + pcibr_soft->bs_pcix_split_tot -= max_splittrans_to_numbuf[max_out]; + } + conn_vhdl = pcibr_info->f_vertex; error_func = pciio_device_detach(conn_vhdl, drv_flags); @@ -1380,22 +1787,22 @@ } /* next func */ - pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK; if (error) { - if ((error != ENODEV) && (error != EUNATCH)) + if ((error != ENODEV) && (error != EUNATCH) && (error != EPERM)) { + pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK; pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT; + } } else { if (conn_vhdl != GRAPH_VERTEX_NONE) pcibr_device_unregister(conn_vhdl); + pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK; pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT; } return(error); } -#ifdef LATER - /* * pcibr_slot_attach * This is a place holder routine to keep track of all the @@ -1411,81 +1818,16 @@ int *sub_errorp) { pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl); +#ifdef PIC_LATER timespec_t ts; - int error; - - if (!(pcibr_soft->bs_slot[slot].slot_status & SLOT_POWER_UP)) { - /* Power-up the slot */ - error = pcibr_slot_pwr(pcibr_vhdl, slot, L1_REQ_PCI_UP, l1_msg); - if (error) { - if (sub_errorp) - *sub_errorp = error; - return(PCI_L1_ERR); - } else { - pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_POWER_MASK; - pcibr_soft->bs_slot[slot].slot_status |= SLOT_POWER_UP; - } - -#ifdef LATER - /* - * Allow cards like the Alteon Gigabit Ethernet Adapter to complete - * on-card initialization following the slot reset - */ - ts.tv_sec = 0; /* 0 secs */ - ts.tv_nsec = 500 * (1000 * 1000); /* 500 msecs */ - nano_delay(&ts); -#else #endif -#if 0 - /* Reset the slot */ - error = pcibr_slot_reset(pcibr_vhdl, slot) - if (error) { - if (sub_errorp) - *sub_errorp = error; - return(PCI_SLOT_RESET_ERR); - } -#endif - - /* Find out what is out there */ - error = pcibr_slot_info_init(pcibr_vhdl, slot); - if (error) { - if (sub_errorp) - *sub_errorp = error; - return(PCI_SLOT_INFO_INIT_ERR); - } - - /* Set up the address space for this slot in the PCI land */ - error = pcibr_slot_addr_space_init(pcibr_vhdl, slot); - if (error) { - if (sub_errorp) - *sub_errorp = error; - return(PCI_SLOT_ADDR_INIT_ERR); - } - - /* Setup the device register */ - error = pcibr_slot_device_init(pcibr_vhdl, slot); - if (error) { - if (sub_errorp) - *sub_errorp = error; - return(PCI_SLOT_DEV_INIT_ERR); - } - - /* Setup host/guest relations */ - error = pcibr_slot_guest_info_init(pcibr_vhdl, slot); - if (error) { - if (sub_errorp) - *sub_errorp = error; - return(PCI_SLOT_GUEST_INIT_ERR); - } - - /* Initial RRB management */ - error = pcibr_slot_initial_rrb_alloc(pcibr_vhdl, slot); - if (error) { - if (sub_errorp) - *sub_errorp = error; - return(PCI_SLOT_RRB_ALLOC_ERR); - } + int error; + /* Do not allow a multi-function card to be hot-plug inserted */ + if (pcibr_soft->bs_slot[slot].bss_ninfo > 1) { + if (sub_errorp) + *sub_errorp = EPERM; + return(PCI_MULTI_FUNC_ERR); } /* Call the device attach */ @@ -1501,7 +1843,6 @@ return(0); } -#endif /* LATER */ /* * pcibr_slot_detach @@ -1511,13 +1852,42 @@ int pcibr_slot_detach(devfs_handle_t pcibr_vhdl, pciio_slot_t slot, - int drv_flags) + int drv_flags, + char *l1_msg, + int *sub_errorp) { + pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl); int error; + /* Make sure that we do not detach a system critical function vertex */ + if(pcibr_is_slot_sys_critical(pcibr_vhdl, slot)) + return(PCI_IS_SYS_CRITICAL); + /* Call the device detach function */ error = (pcibr_slot_call_device_detach(pcibr_vhdl, slot, drv_flags)); - return (error); + if (error) { + if (sub_errorp) + *sub_errorp = error; + return(PCI_SLOT_DRV_DETACH_ERR); + } + + /* Recalculate the RBARs for all the devices on the bus since we've + * just freed some up and some of the devices could use them. + */ + if (IS_PCIX(pcibr_soft)) { + int tmp_slot; + + pcibr_soft->bs_pcix_rbar_inuse = 0; + pcibr_soft->bs_pcix_rbar_avail = NUM_RBAR; + pcibr_soft->bs_pcix_rbar_percent_allowed = + pcibr_pcix_rbars_calc(pcibr_soft); + + for (tmp_slot = pcibr_soft->bs_min_slot; + tmp_slot < PCIBR_NUM_SLOTS(pcibr_soft); ++tmp_slot) + (void)pcibr_slot_pcix_rbar_init(pcibr_soft, tmp_slot); + } + + return (0); } @@ -1540,11 +1910,14 @@ devfs_handle_t conn_vhdl = GRAPH_VERTEX_NONE; int nfunc; int func; - boolean_t is_sys_critical_vertex(devfs_handle_t); + boolean_t is_sys_critical_vertex(devfs_handle_t); pcibr_soft = pcibr_soft_get(pcibr_vhdl); - if (!pcibr_soft || !PCIBR_VALID_SLOT(slot)) - return(0); + if (!pcibr_soft) + return(EINVAL); + + if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) + return(EINVAL); nfunc = pcibr_soft->bs_slot[slot].bss_ninfo; pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos; @@ -1574,57 +1947,112 @@ } /* - * pcibr_probe_slot: read a config space word - * while trapping any errors; reutrn zero if + * pcibr_probe_slot_pic: read a config space word + * while trapping any errors; return zero if * all went OK, or nonzero if there was an error. * The value read, if any, is passed back * through the valp parameter. */ -int -pcibr_probe_slot(bridge_t *bridge, - cfg_p cfg, - unsigned *valp) +static int +pcibr_probe_slot_pic(bridge_t *bridge, + cfg_p cfg, + unsigned *valp) { - int rv; - bridgereg_t old_enable, new_enable; - int badaddr_val(volatile void *, int, volatile void *); - - old_enable = bridge->b_int_enable; - new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT; + int rv; + picreg_t p_old_enable = (picreg_t)0, p_new_enable; + extern int badaddr_val(volatile void *, int, volatile void *); + + p_old_enable = bridge->p_int_enable_64; + p_new_enable = p_old_enable & ~(BRIDGE_IMR_PCI_MST_TIMEOUT | PIC_ISR_PCIX_MTOUT); + bridge->p_int_enable_64 = p_new_enable; + + if (bridge->p_err_int_view_64 & (BRIDGE_ISR_PCI_MST_TIMEOUT | PIC_ISR_PCIX_MTOUT)) + bridge->p_int_rst_stat_64 = BRIDGE_IRR_MULTI_CLR; + + if (bridge->p_int_status_64 & (BRIDGE_IRR_PCI_GRP | PIC_PCIX_GRP_CLR)) { + bridge->p_int_rst_stat_64 = (BRIDGE_IRR_PCI_GRP_CLR | PIC_PCIX_GRP_CLR); + (void) bridge->b_wid_tflush; /* flushbus */ + } + rv = badaddr_val((void *) cfg, 4, valp); + if (bridge->p_err_int_view_64 & (BRIDGE_ISR_PCI_MST_TIMEOUT | PIC_ISR_PCIX_MTOUT)) { + bridge->p_int_rst_stat_64 = BRIDGE_IRR_MULTI_CLR; + rv = 1; /* unoccupied slot */ + } + bridge->p_int_enable_64 = p_old_enable; + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + return(rv); +} - bridge->b_int_enable = new_enable; +/* + * pcibr_probe_slot_non_pic: read a config space word + * while trapping any errors; return zero if + * all went OK, or nonzero if there was an error. + * The value read, if any, is passed back + * through the valp parameter. + */ +static int +pcibr_probe_slot_non_pic(bridge_t *bridge, + cfg_p cfg, + unsigned *valp) +{ + int rv; + bridgereg_t b_old_enable = (bridgereg_t)0, b_new_enable = (bridgereg_t)0; + extern int badaddr_val(volatile void *, int, volatile void *); + + b_old_enable = bridge->b_int_enable; + b_new_enable = b_old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT; + bridge->b_int_enable = b_new_enable; /* * The xbridge doesn't clear b_err_int_view unless * multi-err is cleared... */ - if (is_xbridge(bridge)) - if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) { + if (is_xbridge(bridge)) { + if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR; - } - - if (bridge->b_int_status & BRIDGE_IRR_PCI_GRP) { - bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR; - (void) bridge->b_wid_tflush; /* flushbus */ - } - rv = badaddr_val((void *) cfg, 4, valp); + } + if (bridge->b_int_status & BRIDGE_IRR_PCI_GRP) { + bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR; + (void) bridge->b_wid_tflush; /* flushbus */ + } + rv = badaddr_val((void *) (((uint64_t)cfg) ^ 4), 4, valp); /* * The xbridge doesn't set master timeout in b_int_status * here. Fortunately it's in error_interrupt_view. */ - if (is_xbridge(bridge)) + if (is_xbridge(bridge)) { if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) { bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR; rv = 1; /* unoccupied slot */ } + } + bridge->b_int_enable = b_old_enable; + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + + return(rv); +} - bridge->b_int_enable = old_enable; - bridge->b_wid_tflush; /* wait until Bridge PIO complete */ - return rv; +/* + * pcibr_probe_slot: read a config space word + * while trapping any errors; return zero if + * all went OK, or nonzero if there was an error. + * The value read, if any, is passed back + * through the valp parameter. + */ +static int +pcibr_probe_slot(bridge_t *bridge, + cfg_p cfg, + unsigned *valp) +{ + if ( is_pic(bridge) ) + return(pcibr_probe_slot_pic(bridge, cfg, valp)); + else + return(pcibr_probe_slot_non_pic(bridge, cfg, valp)); } + void pcibr_device_info_free(devfs_handle_t pcibr_vhdl, pciio_slot_t slot) { @@ -1632,10 +2060,13 @@ pcibr_info_t pcibr_info; pciio_function_t func; pcibr_soft_slot_t slotp = &pcibr_soft->bs_slot[slot]; + bridge_t *bridge = pcibr_soft->bs_base; + cfg_p cfgw; int nfunc = slotp->bss_ninfo; int bar; int devio_index; int s; + unsigned cmd_reg; for (func = 0; func < nfunc; func++) { @@ -1646,10 +2077,19 @@ s = pcibr_lock(pcibr_soft); + /* Disable memory and I/O BARs */ + cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0); + cmd_reg = do_pcibr_config_get(IS_PIC_SOFT(pcibr_soft), cfgw, PCI_CFG_COMMAND, 4); + cmd_reg &= (PCI_CMD_MEM_SPACE | PCI_CMD_IO_SPACE); + do_pcibr_config_set(IS_PIC_SOFT(pcibr_soft), cfgw, PCI_CFG_COMMAND, 4, cmd_reg); + for (bar = 0; bar < PCI_CFG_BASE_ADDRS; bar++) { if (pcibr_info->f_window[bar].w_space == PCIIO_SPACE_NONE) continue; + /* Free the PCI bus space */ + pciibr_bus_addr_free(pcibr_soft, &pcibr_info->f_window[bar]); + /* Get index of the DevIO(x) register used to access this BAR */ devio_index = pcibr_info->f_window[bar].w_devio_index; @@ -1664,6 +2104,11 @@ } } + /* Free the Expansion ROM PCI bus space */ + if(pcibr_info->f_rbase && pcibr_info->f_rsize) { + pciibr_bus_addr_free(pcibr_soft, &pcibr_info->f_rwindow); + } + pcibr_unlock(pcibr_soft, s); slotp->bss_infos[func] = 0; @@ -1689,4 +2134,69 @@ slotp->bss_cmd_pointer = 0; slotp->bss_cmd_shadow = 0; +} + + +iopaddr_t +pcibr_bus_addr_alloc(pcibr_soft_t pcibr_soft, pciio_win_info_t win_info_p, + pciio_space_t space, int start, int size, int align) +{ + pciio_win_map_t win_map_p; + + switch (space) { + + case PCIIO_SPACE_IO: + win_map_p = &pcibr_soft->bs_io_win_map; + break; + + case PCIIO_SPACE_MEM: + win_map_p = &pcibr_soft->bs_swin_map; + break; + + case PCIIO_SPACE_MEM32: + win_map_p = &pcibr_soft->bs_mem_win_map; + break; + + default: + return 0; + + } + return pciio_device_win_alloc(win_map_p, + win_info_p + ? &win_info_p->w_win_alloc + : NULL, + start, size, align); +} + + +void +pciibr_bus_addr_free(pcibr_soft_t pcibr_soft, pciio_win_info_t win_info_p) +{ + pciio_device_win_free(&win_info_p->w_win_alloc); +} + +/* + * given a vertex_hdl to the pcibr_vhdl, return the brick's bus number + * associated with that vertex_hdl. The true mapping happens from the + * io_brick_tab[] array defined in ml/SN/iograph.c + */ +int +pcibr_widget_to_bus(devfs_handle_t pcibr_vhdl) +{ + pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl); + xwidgetnum_t widget = pcibr_soft->bs_xid; + int bricktype = pcibr_soft->bs_bricktype; + int bus = pcibr_soft->bs_busnum; + + /* + * For PIC there are 2 busses per widget and pcibr_soft->bs_busnum + * will be 0 or 1. For [X]BRIDGE there is 1 bus per widget and + * pcibr_soft->bs_busnum will always be zero. So we add bs_busnum + * to what io_brick_map_widget returns to get the bus number. + */ + if ((bus += io_brick_map_widget(bricktype, widget)) > 0) { + return bus; + } else { + return 0; + } } diff -Nru a/arch/ia64/sn/io/sn2/shub_intr.c b/arch/ia64/sn/io/sn2/shub_intr.c --- a/arch/ia64/sn/io/sn2/shub_intr.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/sn2/shub_intr.c Wed Jan 15 16:57:29 2003 @@ -1,4 +1,4 @@ -/* $Id: shub_intr.c,v 1.2 2001/06/26 14:02:43 pfg Exp $ +/* $Id: shub_intr.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -25,21 +25,13 @@ #include #include #include +#include #include -extern void hub_device_desc_update(device_desc_t, ilvl_t, cpuid_t); - /* ARGSUSED */ void hub_intr_init(devfs_handle_t hubv) { - extern void sn_cpei_handler(int, void *, struct pt_regs *); - extern void sn_init_cpei_timer(void); - - if (request_irq(SGI_SHUB_ERROR_VECTOR, sn_cpei_handler, 0, "SN hub error", NULL) ) { - printk("hub_intr_init: Couldn't register SGI_SHUB_ERROR_VECTOR = %x\n",SGI_SHUB_ERROR_VECTOR); - } - sn_init_cpei_timer(); } xwidgetnum_t @@ -79,14 +71,12 @@ cpuphys = cpu_physical_id(cpu); slice = cpu_physical_id_to_slice(cpuphys); nasid = cpu_physical_id_to_nasid(cpuphys); - cnode = cpuid_to_cnodeid(cpu); + cnode = cpu_to_node_map[cpu]; if (slice) { - xtalk_addr = SH_II_INT1 | GLOBAL_MMR_SPACE | - ((unsigned long)nasid << 36) | (1UL << 47); + xtalk_addr = SH_II_INT1 | ((unsigned long)nasid << 36) | (1UL << 47); } else { - xtalk_addr = SH_II_INT0 | GLOBAL_MMR_SPACE | - ((unsigned long)nasid << 36) | (1UL << 47); + xtalk_addr = SH_II_INT0 | ((unsigned long)nasid << 36) | (1UL << 47); } intr_hdl = snia_kmem_alloc_node(sizeof(struct hub_intr_s), KM_NOSLEEP, cnode); @@ -107,7 +97,6 @@ intr_hdl->i_bit = vector; intr_hdl->i_flags |= HUB_INTR_IS_ALLOCED; - hub_device_desc_update(dev_desc, intr_swlevel, cpu); return(intr_hdl); } @@ -136,7 +125,7 @@ if (intr_hdl->i_flags & HUB_INTR_IS_CONNECTED) { xtalk_info = &intr_hdl->i_xtalk_info; - xtalk_info->xi_dev = NODEV; + xtalk_info->xi_dev = 0; xtalk_info->xi_vector = 0; xtalk_info->xi_addr = 0; hub_intr_disconnect(intr_hdl); @@ -150,6 +139,8 @@ int hub_intr_connect(hub_intr_t intr_hdl, + intr_func_t intr_func, /* xtalk intr handler */ + void *intr_arg, /* arg to intr handler */ xtalk_intr_setfunc_t setfunc, void *setfunc_arg) { @@ -160,7 +151,6 @@ ASSERT(intr_hdl->i_flags & HUB_INTR_IS_ALLOCED); rv = intr_connect_level(cpu, vector, intr_hdl->i_swlevel, NULL); - if (rv < 0) { return rv; } diff -Nru a/arch/ia64/sn/io/sn2/shuberror.c b/arch/ia64/sn/io/sn2/shuberror.c --- a/arch/ia64/sn/io/sn2/shuberror.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/sn2/shuberror.c Wed Jan 15 16:57:29 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: shuberror.c,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -10,6 +10,8 @@ #include #include +#include +#include #include #include #include @@ -34,12 +36,18 @@ extern void hubii_eint_handler (int irq, void *arg, struct pt_regs *ep); int hubiio_crb_error_handler(devfs_handle_t hub_v, hubinfo_t hinfo); int hubiio_prb_error_handler(devfs_handle_t hub_v, hubinfo_t hinfo); -extern void bte_crb_error_handler(devfs_handle_t hub_v, int btenum, int crbnum, ioerror_t *ioe); +extern void bte_crb_error_handler(devfs_handle_t hub_v, int btenum, int crbnum, ioerror_t *ioe, int bteop); extern int maxcpus; #define HUB_ERROR_PERIOD (120 * HZ) /* 2 minutes */ +#ifdef BUS_INT_WAR +void sn_add_polled_interrupt(int irq, int interval); +void sn_delete_polled_interrupt(int irq); +extern int bus_int_war_ide_irq; +#endif + void hub_error_clear(nasid_t nasid) @@ -118,9 +126,7 @@ hubinfo_t hinfo; cpuid_t intr_cpu; devfs_handle_t hub_v; - ii_ilcsr_u_t ilcsr; int bit_pos_to_irq(int bit); - int synergy_intr_connect(int bit, int cpuid); hub_v = (devfs_handle_t)cnodeid_to_vertex(cnode); @@ -130,17 +136,6 @@ ASSERT(hinfo); ASSERT(hinfo->h_cnodeid == cnode); - ilcsr.ii_ilcsr_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_ILCSR); - - if ((ilcsr.ii_ilcsr_fld_s.i_llp_stat & 0x2) == 0) { - /* - * HUB II link is not up. - * Just disable LLP, and don't connect any interrupts. - */ - ilcsr.ii_ilcsr_fld_s.i_llp_en = 0; - REMOTE_HUB_S(hinfo->h_nasid, IIO_ILCSR, ilcsr.ii_ilcsr_regval); - return; - } /* Select a possible interrupt target where there is a free interrupt * bit and also reserve the interrupt bit for this IO error interrupt */ @@ -152,7 +147,11 @@ } rv = intr_connect_level(intr_cpu, bit, 0, NULL); - request_irq(bit + (intr_cpu << 8), hubii_eint_handler, 0, "SN hub error", (void *)hub_v); + request_irq(bit + (intr_cpu << 8), hubii_eint_handler, 0, "SN_hub_error", (void *)hub_v); + irq_desc(bit + (intr_cpu << 8))->status |= SN2_IRQ_PER_HUB; +#ifdef BUS_INT_WAR + sn_add_polled_interrupt(bit + (intr_cpu << 8), (0.01 * HZ)); +#endif ASSERT_ALWAYS(rv >= 0); hubio_eint.ii_iidsr_regval = 0; hubio_eint.ii_iidsr_fld_s.i_enable = 1; @@ -257,15 +256,16 @@ void hubiio_crb_free(hubinfo_t hinfo, int crbnum) { - ii_icrb0_a_u_t icrba; + ii_icrb0_b_u_t icrbb; /* * The hardware does NOT clear the mark bit, so it must get cleared * here to be sure the error is not processed twice. */ - icrba.ii_icrb0_a_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_ICRB_A(crbnum)); - icrba.a_valid = 0; - REMOTE_HUB_S(hinfo->h_nasid, IIO_ICRB_A(crbnum), icrba.ii_icrb0_a_regval); + icrbb.ii_icrb0_b_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_ICRB_B(crbnum)); + icrbb.b_mark = 0; + REMOTE_HUB_S(hinfo->h_nasid, IIO_ICRB_B(crbnum), icrbb.ii_icrb0_b_regval); + /* * Deallocate the register. */ @@ -325,9 +325,11 @@ ii_icrb0_b_u_t icrbb; /* II CRB Register B */ ii_icrb0_c_u_t icrbc; /* II CRB Register C */ ii_icrb0_d_u_t icrbd; /* II CRB Register D */ + ii_icrb0_e_u_t icrbe; /* II CRB Register D */ int i; int num_errors = 0; /* Num of errors handled */ ioerror_t ioerror; + int rc; nasid = hinfo->h_nasid; cnode = NASID_TO_COMPACT_NODEID(nasid); @@ -337,16 +339,24 @@ * in any of the CRBs marked. */ for (i = 0; i < IIO_NUM_CRBS; i++) { + /* Check this crb entry to see if it is in error. */ + icrbb.ii_icrb0_b_regval = REMOTE_HUB_L(nasid, IIO_ICRB_B(i)); + + if (icrbb.b_mark == 0) { + continue; + } + icrba.ii_icrb0_a_regval = REMOTE_HUB_L(nasid, IIO_ICRB_A(i)); IOERROR_INIT(&ioerror); /* read other CRB error registers. */ - icrbb.ii_icrb0_b_regval = REMOTE_HUB_L(nasid, IIO_ICRB_B(i)); icrbc.ii_icrb0_c_regval = REMOTE_HUB_L(nasid, IIO_ICRB_C(i)); icrbd.ii_icrb0_d_regval = REMOTE_HUB_L(nasid, IIO_ICRB_D(i)); + icrbe.ii_icrb0_e_regval = REMOTE_HUB_L(nasid, IIO_ICRB_E(i)); IOERROR_SETVALUE(&ioerror,errortype,icrbb.b_ecode); + /* Check if this error is due to BTE operation, * and handle it separately. */ @@ -363,8 +373,15 @@ else /* b_initiator bit 2 gives BTE number */ bte_num = (icrbb.b_initiator & 0x4) >> 2; + /* >>> bte_crb_error_handler needs to be + * broken into two parts. The first should + * cleanup the CRB. The second should wait + * until all bte related CRB's are complete + * and then do the error reset. + */ bte_crb_error_handler(hub_v, bte_num, - i, &ioerror); + i, &ioerror, + icrbd.d_bteop); hubiio_crb_free(hinfo, i); num_errors++; continue; @@ -401,11 +418,142 @@ */ IOERROR_SETVALUE(&ioerror,widgetdev, TNUM_TO_WIDGET_DEV(icrba.a_tnum)); + /* + * The encoding of TNUM (see comments above) is + * different for PIC. So we'll save TNUM here and + * deal with the differences later when we can + * determine if we're using a Bridge or the PIC. + * + * XXX: We may be able to remove saving the widgetdev + * above and just sort it out of TNUM later. + */ + IOERROR_SETVALUE(&ioerror, tnum, icrba.a_tnum); + + } + + if (icrbb.b_error) { + /* + * CRB 'i' has some error. Identify the type of error, + * and try to handle it. + */ + switch(icrbb.b_ecode) { + case IIO_ICRB_ECODE_PERR: + case IIO_ICRB_ECODE_WERR: + case IIO_ICRB_ECODE_AERR: + case IIO_ICRB_ECODE_PWERR: + + printk("%s on hub cnodeid: %d", + hubiio_crb_errors[icrbb.b_ecode], cnode); + /* + * Any sort of write error is mostly due + * bad programming (Note it's not a timeout.) + * So, invoke hub_iio_error_handler with + * appropriate information. + */ + IOERROR_SETVALUE(&ioerror,errortype,icrbb.b_ecode); + + rc = hub_ioerror_handler( + hub_v, + DMA_WRITE_ERROR, + MODE_DEVERROR, + &ioerror); + + if (rc == IOERROR_HANDLED) { + rc = hub_ioerror_handler( + hub_v, + DMA_WRITE_ERROR, + MODE_DEVREENABLE, + &ioerror); + ASSERT(rc == IOERROR_HANDLED); + }else { + + panic("Unable to handle %s on hub %d", + hubiio_crb_errors[icrbb.b_ecode], + cnode); + /*NOTREACHED*/ + } + /* Go to Next error */ + hubiio_crb_free(hinfo, i); + continue; + + case IIO_ICRB_ECODE_PRERR: + + case IIO_ICRB_ECODE_TOUT: + case IIO_ICRB_ECODE_XTERR: + + case IIO_ICRB_ECODE_DERR: + panic("Fatal %s on hub : %d", + hubiio_crb_errors[icrbb.b_ecode], cnode); + /*NOTREACHED*/ + + default: + panic("Fatal error (code : %d) on hub : %d", + cnode); + /*NOTREACHED*/ + + } + } /* if (icrbb.b_error) */ + /* + * Error is not indicated via the errcode field + * Check other error indications in this register. + */ + + if (icrbb.b_xerr) { + panic("Xtalk Packet with error bit set to hub %d", + cnode); + /*NOTREACHED*/ + } + + if (icrbb.b_lnetuce) { + panic("Uncorrectable data error detected on data " + " from Craylink to node %d", + cnode); + /*NOTREACHED*/ } } return num_errors; +} + +/* + * hubii_check_widget_disabled + * + * Check if PIO access to the specified widget is disabled due + * to any II errors that are currently set. + * + * The specific error bits checked are: + * IPRBx register: SPUR_RD (51) + * SPUR_WR (50) + * RD_TO (49) + * ERROR (48) + * + * WSTAT register: CRAZY (32) + */ + +int +hubii_check_widget_disabled(nasid_t nasid, int wnum) +{ + iprb_t iprb; + ii_wstat_u_t wstat; + + iprb.iprb_regval = REMOTE_HUB_L(nasid, IIO_IOPRB(wnum)); + if (iprb.iprb_regval & (IIO_PRB_SPUR_RD | IIO_PRB_SPUR_WR | + IIO_PRB_RD_TO | IIO_PRB_ERROR)) { +#ifdef DEBUG + printk(KERN_WARNING "II error, IPRB%x=0x%lx\n", wnum, iprb.iprb_regval); +#endif + return(1); + } + + wstat.ii_wstat_regval = REMOTE_HUB_L(nasid, IIO_WSTAT); + if (wstat.ii_wstat_regval & IIO_WSTAT_ECRAZY) { +#ifdef DEBUG + printk(KERN_WARNING "II error, WSTAT=0x%lx\n", wstat.ii_wstat_regval); +#endif + return(1); + } + return(0); } /*ARGSUSED*/ diff -Nru a/arch/ia64/sn/io/stubs.c b/arch/ia64/sn/io/stubs.c --- a/arch/ia64/sn/io/stubs.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/io/stubs.c Wed Jan 15 16:57:29 2003 @@ -9,8 +9,9 @@ #include #include -#include +#include #include +#include #include #include #include @@ -28,8 +29,8 @@ int pcibr_prefetch_enable_rev, pcibr_wg_enable_rev; int default_intr_pri; -int force_fire_and_forget; -int ignore_conveyor_override; +int force_fire_and_forget = 1; +int ignore_conveyor_override = 0; devfs_handle_t dummy_vrtx; /* Needed for cpuid_to_vertex() in hack.h */ @@ -53,54 +54,24 @@ return(0); } -char * -nic_bridge_vertex_info(devfs_handle_t v, nic_data_t mcr) -{ - FIXME("nic_bridge_vertex_info : returns NULL"); - return((char *)0); -} - -void * -snia_kmem_alloc_node(register size_t size, register int flags, cnodeid_t node) -{ - /* Allocates on node 'node' */ - FIXME("snia_kmem_alloc_node : use kmalloc"); - return(kmalloc(size, GFP_KERNEL)); -} - -void * -snia_kmem_zalloc_node(register size_t size, register int flags, cnodeid_t node) -{ - FIXME("snia_kmem_zalloc_node : use kmalloc"); - return(kmalloc(size, GFP_KERNEL)); -} - -void -snia_kmem_free(void *where, int size) -{ - FIXME("snia_kmem_free : use kfree"); - return(kfree(where)); -} - - void * -snia_kmem_zone_alloc(register zone_t *zone, int flags) +snia_kmem_zone_alloc(register struct zone *zone, int flags) { FIXME("snia_kmem_zone_alloc : return null"); return((void *)0); } void -snia_kmem_zone_free(register zone_t *zone, void *ptr) +snia_kmem_zone_free(register struct zone *zone, void *ptr) { FIXME("snia_kmem_zone_free : no-op"); } -zone_t * +struct zone * snia_kmem_zone_init(register int size, char *zone_name) { FIXME("snia_kmem_zone_free : returns NULL"); - return((zone_t *)0); + return((struct zone *)0); } int @@ -115,13 +86,6 @@ return(0); } -void * -swap_ptr(void **loc, void *new) -{ - FIXME("swap_ptr : returns null"); - return((void *)0); -} - /* For ml/SN/SN1/slots.c */ /* ARGSUSED */ slotid_t get_widget_slotnum(int xbow, int widget) @@ -153,10 +117,8 @@ char * nic_vertex_info_get(devfs_handle_t v) { - FIXME("nic_vertex_info_get\n"); return(NULL); - } int diff -Nru a/arch/ia64/sn/io/xswitch.c b/arch/ia64/sn/io/xswitch.c --- a/arch/ia64/sn/io/xswitch.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/io/xswitch.c Wed Jan 15 16:57:28 2003 @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992-1997,2000-2002 Silicon Graphics, Inc. All rights reserved. */ #include diff -Nru a/arch/ia64/sn/kernel/Makefile b/arch/ia64/sn/kernel/Makefile --- a/arch/ia64/sn/kernel/Makefile Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/kernel/Makefile Wed Jan 15 16:57:28 2003 @@ -1,4 +1,4 @@ -# arch/ia64/sn/Makefile +# arch/ia64/sn/kernel/Makefile # # Copyright (C) 1999,2001-2002 Silicon Graphics, Inc. All Rights Reserved. # @@ -33,11 +33,17 @@ EXTRA_CFLAGS := -DLITTLE_ENDIAN -export-objs := sn_ksyms.o +.S.s: + $(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -o $*.s $< +.S.o: + $(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $< -obj-y = probe.o setup.o sn_asm.o sv.o bte.o -obj-$(CONFIG_IA64_SGI_SN1) += irq.o mca.o sn1/ -obj-$(CONFIG_IA64_SGI_SN2) += irq.o mca.o sn2/ +export-objs = sn_ksyms.o iomv.o + +obj-y = probe.o setup.o sn_asm.o sv.o bte.o iomv.o +obj-$(CONFIG_IA64_SGI_SN1) += irq.o mca.o +obj-$(CONFIG_IA64_SGI_SN2) += irq.o mca.o obj-$(CONFIG_IA64_SGI_AUTOTEST) += llsc4.o misctest.o obj-$(CONFIG_IA64_GENERIC) += machvec.o obj-$(CONFIG_MODULES) += sn_ksyms.o +obj-$(CONFIG_IA64_SGI_SN_BRT) += bte_regr_test.o diff -Nru a/arch/ia64/sn/kernel/bte.c b/arch/ia64/sn/kernel/bte.c --- a/arch/ia64/sn/kernel/bte.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/kernel/bte.c Wed Jan 15 16:57:29 2003 @@ -1,18 +1,49 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * + * + * Copyright (c) 2000-2002 Silicon Graphics, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Further, this software is distributed without any warranty that it is + * free of the rightful claim of any third person regarding infringement + * or the like. Any license provided herein, whether implied or + * otherwise, applies only to this software file. Patent licenses, if + * any, provided herein do not apply to combinations of this program with + * other software, or any other product whatsoever. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, + * Mountain View, CA 94043, or: + * + * http://www.sgi.com * - * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + * For further information regarding this notice, see: + * + * http://oss.sgi.com/projects/GenInfo/NoticeExplan */ +#include #include #include #include #include #include +#ifdef CONFIG_IA64_SGI_SN2 +#include +#endif #include +#include #include #include @@ -26,12 +57,16 @@ * Initialize the nodepda structure with BTE base addresses and * spinlocks. * + * NOTE: The kernel parameter btetest will cause the initialization + * code to reserve blocks of physically contiguous memory to be + * used by the bte test module. */ void -bte_init_node(nodepda_t * mynodepda, cnodeid_t cNode) +bte_init_node(nodepda_t * mynodepda, cnodeid_t cnode) { int i; + /* * Indicate that all the block transfer engines on this node * are available. @@ -39,27 +74,76 @@ for (i = 0; i < BTES_PER_NODE; i++) { #ifdef CONFIG_IA64_SGI_SN2 /* >>> Don't know why the 0x1800000L is here. Robin */ - mynodepda->node_bte_info[i].bte_base_addr = + mynodepda->bte_if[i].bte_base_addr = (char *)LOCAL_MMR_ADDR(bte_offsets[i] | 0x1800000L); + #elif CONFIG_IA64_SGI_SN1 - mynodepda->node_bte_info[i].bte_base_addr = + mynodepda->bte_if[i].bte_base_addr = (char *)LOCAL_HUB_ADDR(bte_offsets[i]); #else #error BTE Not defined for this hardware platform. #endif + /* + * Initialize the notification and spinlock + * so the first transfer can occur. + */ + mynodepda->bte_if[i].most_rcnt_na = + &(mynodepda->bte_if[i].notify); + mynodepda->bte_if[i].notify = 0L; #ifdef CONFIG_IA64_SGI_BTE_LOCKING - /* Initialize the notification and spinlock */ - /* so the first transfer can occur. */ - mynodepda->node_bte_info[i].mostRecentNotification = - &(mynodepda->node_bte_info[i].notify); - mynodepda->node_bte_info[i].notify = 0L; - spin_lock_init(&mynodepda->node_bte_info[i].spinlock); + spin_lock_init(&mynodepda->bte_if[i].spinlock); #endif /* CONFIG_IA64_SGI_BTE_LOCKING */ + mynodepda->bte_if[i].bte_test_buf = + alloc_bootmem_node(NODE_DATA(cnode), BTE_MAX_XFER); + } + +} + + +/* + * bte_reset_nasid(nasid_t) + * + * Does a soft reset of the BTEs on the specified nasid. + * This is followed by a one-line transfer from each of the + * virtual interfaces. + */ +void +bte_reset_nasid(nasid_t n) +{ + ii_ibcr_u_t ibcr; + + ibcr.ii_ibcr_regval = REMOTE_HUB_L(n, IIO_IBCR); + ibcr.ii_ibcr_fld_s.i_soft_reset = 1; + REMOTE_HUB_S(n, IIO_IBCR, ibcr.ii_ibcr_regval); + + /* One line transfer on virtual interface 0 */ + REMOTE_HUB_S(n, IIO_IBLS_0, IBLS_BUSY | 1); + REMOTE_HUB_S(n, IIO_IBSA_0, TO_PHYS(__pa(&nodepda->bte_cleanup))); + REMOTE_HUB_S(n, IIO_IBDA_0, + TO_PHYS(__pa(&nodepda->bte_cleanup[4*L1_CACHE_BYTES]))); + REMOTE_HUB_S(n, IIO_IBNA_0, + TO_PHYS(__pa(&nodepda->bte_cleanup[4*L1_CACHE_BYTES]))); + REMOTE_HUB_S(n, IIO_IBCT_0, BTE_NOTIFY); + while (REMOTE_HUB_L(n, IIO_IBLS0)) { + /* >>> Need some way out in case of hang... */ + } + + /* One line transfer on virtual interface 1 */ + REMOTE_HUB_S(n, IIO_IBLS_1, IBLS_BUSY | 1); + REMOTE_HUB_S(n, IIO_IBSA_1, TO_PHYS(__pa(nodepda->bte_cleanup))); + REMOTE_HUB_S(n, IIO_IBDA_1, + TO_PHYS(__pa(nodepda->bte_cleanup[4 * L1_CACHE_BYTES]))); + REMOTE_HUB_S(n, IIO_IBNA_1, + TO_PHYS(__pa(nodepda->bte_cleanup[5 * L1_CACHE_BYTES]))); + REMOTE_HUB_S(n, IIO_IBCT_1, BTE_NOTIFY); + while (REMOTE_HUB_L(n, IIO_IBLS1)) { + /* >>> Need some way out in case of hang... */ } } + /* * bte_init_cpu() * @@ -70,14 +154,8 @@ void bte_init_cpu(void) { - /* Called by setup.c as each cpu is being added to the nodepda */ - if (local_node_data->active_cpu_count & 0x1) { - pda.cpubte[0] = &(nodepda->node_bte_info[0]); - pda.cpubte[1] = &(nodepda->node_bte_info[1]); - } else { - pda.cpubte[0] = &(nodepda->node_bte_info[1]); - pda.cpubte[1] = &(nodepda->node_bte_info[0]); - } + pda->cpu_bte_if[0] = &(nodepda->bte_if[1]); + pda->cpu_bte_if[1] = &(nodepda->bte_if[0]); } @@ -93,14 +171,12 @@ * len - number of bytes to transfer from source to dest. * mode - hardware defined. See reference information * for IBCT0/1 in the SGI documentation. - * bteBlock - kernel virtual address of a temporary - * buffer used during unaligned transfers. * * NOTE: If the source, dest, and len are all cache line aligned, * then it would be _FAR_ preferrable to use bte_copy instead. */ bte_result_t -bte_unaligned_copy(u64 src, u64 dest, u64 len, u64 mode, char *bteBlock) +bte_unaligned_copy(u64 src, u64 dest, u64 len, u64 mode) { int destFirstCacheOffset; u64 headBteSource; @@ -113,10 +189,18 @@ u64 footBcopyDest; u64 footBcopyLen; bte_result_t rv; + char *bteBlock; if (len == 0) { return (BTE_SUCCESS); } + +#ifdef CONFIG_IA64_SGI_BTE_LOCKING +#error bte_unaligned_copy() assumes single BTE selection in bte_copy(). +#else + /* temporary buffer used during unaligned transfers */ + bteBlock = pda->cpu_bte_if[0]->bte_test_buf; +#endif headBcopySrcOffset = src & L1_CACHE_MASK; destFirstCacheOffset = dest & L1_CACHE_MASK; diff -Nru a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c --- a/arch/ia64/sn/kernel/irq.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/kernel/irq.c Wed Jan 15 16:57:28 2003 @@ -59,34 +59,33 @@ #include #include #include +#include int irq_to_bit_pos(int irq); - - static unsigned int -sn1_startup_irq(unsigned int irq) +sn_startup_irq(unsigned int irq) { return(0); } static void -sn1_shutdown_irq(unsigned int irq) +sn_shutdown_irq(unsigned int irq) { } static void -sn1_disable_irq(unsigned int irq) +sn_disable_irq(unsigned int irq) { } static void -sn1_enable_irq(unsigned int irq) +sn_enable_irq(unsigned int irq) { } static void -sn1_ack_irq(unsigned int irq) +sn_ack_irq(unsigned int irq) { #ifdef CONFIG_IA64_SGI_SN1 int bit = -1; @@ -149,7 +148,7 @@ } static void -sn1_end_irq(unsigned int irq) +sn_end_irq(unsigned int irq) { #ifdef CONFIG_IA64_SGI_SN1 unsigned long long intpend_val, mask = 0x70L; @@ -187,87 +186,82 @@ } static void -sn1_set_affinity_irq(unsigned int irq, unsigned long mask) +sn_set_affinity_irq(unsigned int irq, unsigned long mask) { } struct hw_interrupt_type irq_type_iosapic_level = { "SN hub", - sn1_startup_irq, - sn1_shutdown_irq, - sn1_enable_irq, - sn1_disable_irq, - sn1_ack_irq, - sn1_end_irq, - sn1_set_affinity_irq + sn_startup_irq, + sn_shutdown_irq, + sn_enable_irq, + sn_disable_irq, + sn_ack_irq, + sn_end_irq, + sn_set_affinity_irq }; -#define irq_type_sn1 irq_type_iosapic_level -struct irq_desc *_sn1_irq_desc[NR_CPUS]; +#define irq_type_sn irq_type_iosapic_level +struct irq_desc *_sn_irq_desc[NR_CPUS]; struct irq_desc * -sn1_irq_desc(unsigned int irq) { +sn_irq_desc(unsigned int irq) { int cpu = irq >> 8; irq = irq & 0xff; - return(_sn1_irq_desc[cpu] + irq); + return(_sn_irq_desc[cpu] + irq); } u8 -sn1_irq_to_vector(u8 irq) { +sn_irq_to_vector(u8 irq) { return(irq & 0xff); } -unsigned int -sn1_local_vector_to_irq(u8 vector) { - return ( (smp_processor_id() << 8) + vector); +int gsi_to_vector(u32 irq) { + return irq & 0xff; } -int -sn1_valid_irq(u8 irq) { +int gsi_to_irq(u32 irq) { + return irq & 0xff; +} - return( ((irq & 0xff) < NR_IRQS) && ((irq >> 8) < NR_CPUS) ); +unsigned int +sn_local_vector_to_irq(u8 vector) { + return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector)); } void *kmalloc(size_t, int); void -sn1_irq_init (void) +sn_irq_init (void) { int i; irq_desc_t *base_desc = _irq_desc; - for (i=IA64_FIRST_DEVICE_VECTOR; i @@ -113,7 +113,8 @@ * PORTING NOTE: revisit this statement. On hardware we put mbase at 0 and * the rest of the tables have to start at 1MB to skip PROM tables. */ -#define THREADPRIVATE(t) ((threadprivate_t*)(((long)mbase)+1024*1024+t*((sizeof(threadprivate_t)+511)/512*512))) +#define THREADPRIVATESZ() ((sizeof(threadprivate_t)+511)/512*512) +#define THREADPRIVATE(t) ((threadprivate_t*)(((long)mbase)+4096+t*THREADPRIVATESZ())) #define k_capture mbase->sk_capture #define k_go mbase->sk_go @@ -797,27 +798,31 @@ k_threadprivate[cpuid]->threadstate = state; } +#define MINBLK (16*1024*1024) static int build_mem_map(unsigned long start, unsigned long end, void *arg) { - long lstart; + long lstart, lend; long align = 8*MB; - /* - * HACK - skip the kernel on the first node - */ - printk ("LLSC memmap: start 0x%lx, end 0x%lx, (0x%lx - 0x%lx)\n", start, end, (long) virt_to_page(start), (long) virt_to_page(end-PAGE_SIZE)); - if (memmapx >= MAPCHUNKS) + if (memmapx >= MAPCHUNKS || (end-start) < MINBLK) return 0; - while (end > start && (PageReserved(virt_to_page(end-PAGE_SIZE)) || virt_to_page(end-PAGE_SIZE)->count.counter > 0)) - end -= PAGE_SIZE; - lstart = end; - while (lstart > start && (!PageReserved(virt_to_page(lstart-PAGE_SIZE)) && virt_to_page(lstart-PAGE_SIZE)->count.counter == 0)) + /* + * Start in the middle of the range & find the first non-free page in both directions + * from the midpoint. This is likely to be the bigest free block. + */ + lend = lstart = start + (end-start)/2; + while (lend < end && !PageReserved(virt_to_page(lend)) && virt_to_page(lend)->count.counter == 0) + lend += PAGE_SIZE; + lend -= PAGE_SIZE; + + while (lstart >= start && !PageReserved(virt_to_page(lstart)) && virt_to_page(lstart)->count.counter == 0) lstart -= PAGE_SIZE; + lstart += PAGE_SIZE; lstart = (lstart + align -1) /align * align; end = end / align * align; @@ -834,7 +839,7 @@ void int_test(void); int -llsc_main (int cpuid, long mbasex) +llsc_main (int cpuid) { int i, cpu, is_master, repeatcnt=0; unsigned int preverr=0, errs=0, pass=0; @@ -856,10 +861,11 @@ if (is_master) { + mbase = (control_t*) __get_free_pages(GFP_KERNEL, get_order(4096+THREADPRIVATESZ()*LLSC_MAXCPUS)); + printk("LLSC: mbase 0x%lx\n", (long)mbase); print_params(); if(!IS_RUNNING_ON_SIMULATOR()) spin(10); - mbase = (control_t*)mbasex; k_currentpass = 0; k_go = ST_IDLE; k_passes = DEF_PASSES; @@ -882,6 +888,7 @@ memset(k_threadprivate[i], 0, sizeof(*k_threadprivate[i])); init_private[i] = i; } + mb(); initialized = 1; } else { while (initialized == 0) @@ -1005,15 +1012,14 @@ printk("Testing cross interrupts\n"); - while (control_cpu != NR_CPUS) { - if (mycpu == control_cpu) { - for (cpu=0; cpu + +#ifdef CONFIG_IA64_SGI_SN1 #define MACHVEC_PLATFORM_NAME sn1 +#else CONFIG_IA64_SGI_SN1 +#define MACHVEC_PLATFORM_NAME sn2 +#else +#error "unknown platform" +#endif + #include #include #include void* -sn1_mk_io_addr_MACRO +sn_mk_io_addr_MACRO dma_addr_t -sn1_pci_map_single_MACRO +sn_pci_map_single_MACRO int -sn1_pci_map_sg_MACRO +sn_pci_map_sg_MACRO unsigned long -sn1_virt_to_phys_MACRO +sn_virt_to_phys_MACRO void * -sn1_phys_to_virt_MACRO +sn_phys_to_virt_MACRO diff -Nru a/arch/ia64/sn/kernel/misctest.c b/arch/ia64/sn/kernel/misctest.c --- a/arch/ia64/sn/kernel/misctest.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/kernel/misctest.c Wed Jan 15 16:57:29 2003 @@ -4,119 +4,368 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #include #include #include +#include #include #include #include #include - +#include +#include +#include +#include +#include +#include +#include extern int autotest_enabled; -int mcatest=0; - +long mcatest=0, debug0, debug1, debug2, debug3; +#define HDELAY(t) (IS_RUNNING_ON_SIMULATOR() ? udelay(1) : udelay(t)) /* * mcatest - * 1 = expected MCA - * 2 = unexpected MCA - * 3 = expected MCA + unexpected MCA - * 4 = INIT - * 5 = speculative load to garbage memory address - * 6 = speculative load with ld8.s (needs poison hack in PROM) - * 7 = speculative load from mis-predicted branch (needs poison hack in PROM) + * mactest contains a decimal number (RPTT) where + * R - flag, if non zero, run forever + * + * P - identifies when to run the test + * 0 execute test at cpu 0 early init + * 1 execute test at cpu 0 idle + * 2 execute test at last (highest numbered) cpu idle + * 3 execute test on all cpus at idle + * + * TT- identifies test to run + * 01 = MCA via dup TLB dropin + * 02 = MCA via garbage address + * 03 = lfetch via garbage address + * 05 = INIT self + * 06 = INIT other cpu + * 07 = INIT non-existent cpu + * 10 = IPI stress test. Target cpu 0 + * 11 = IPI stress test. Target all cpus + * 12 = TLB stress test + * 13 = Park cpu (spinloop) + * 14 = One shot TLB test with tlb spinlock + * 15 = One shot TLB test + * 16 = One shot TLB test sync'ed with RTC + * 20 = set led to the cpuid & spin. + * 21 = Try mixed cache/uncached refs & see what happens + * 22 = Call SAL reboot + * 23 = Call PAL halt */ static int __init set_mcatest(char *str) { - get_option(&str, &mcatest); + int val; + get_option(&str, &val); + mcatest = val; return 1; } - __setup("mcatest=", set_mcatest); +static int __init set_debug0(char *str) +{ + int val; + get_option(&str, &val); + debug0 = val; + return 1; +} +__setup("debug0=", set_debug0); + +static int __init set_debug1(char *str) +{ + int val; + get_option(&str, &val); + debug1 = val; + return 1; +} +__setup("debug1=", set_debug1); + +static int __init set_debug2(char *str) +{ + int val; + get_option(&str, &val); + debug2 = val; + return 1; +} +__setup("debug2=", set_debug2); + +static int __init set_debug3(char *str) +{ + int val; + get_option(&str, &val); + debug3 = val; + return 1; +} +__setup("debug3=", set_debug3); + +static volatile int go; + +static void +do_sync(int pos) { + if (pos != 3) + return; + else if (smp_processor_id() == 0) + go = 1; + else + while (!go); +} + +static void +sgi_mcatest_bkpt(void) +{ +} + + +/* + * Optional test + * pos - 0 called from early init + * pos - called when cpu about to go idle (fully initialized + */ void -sgi_mcatest(void) +sgi_mcatest(int pos) { - if (mcatest == 1 || mcatest == 3) { - long *p, result, adrs[] = {0xc0000a000f021004UL, 0xc0000a000f026004UL, 0x800000000, 0x500000, 0}; - long size[] = {1,2,4,8}; - int r, i, j; - p = (long*)0xc000000000000000UL; - ia64_fc(p); - *p = 0x0123456789abcdefL; - for (i=0; i<5; i++) { - for (j=0; j<4; j++) { - printk("Probing 0x%lx, size %ld\n", adrs[i], size[j]); - result = -1; - r = ia64_sn_probe_io_slot (adrs[i], size[j], &result); - printk(" status %d, val 0x%lx\n", r, result); + long spos, test, repeat; + int cpu, curcpu, i, n; + + //if (IS_RUNNING_ON_SIMULATOR()) mcatest=1323; + repeat = mcatest/1000; + spos = (mcatest/100)%10; + test = mcatest % 100; + curcpu = smp_processor_id(); + + if ( mcatest == 0 || !((pos == 0 && spos == 0) || + (pos == 1 && spos == 3) || + (pos == 1 && spos == 1 && curcpu == 0) || + (pos == 1 && spos == 2 && curcpu == smp_num_cpus-1))) + return; + +again: + if (test == 1 || test == 2 || test == 3) { + void zzzmca(int); + printk("CPU %d: About to cause unexpected MCA\n", curcpu); + HDELAY(100000); + sgi_mcatest_bkpt(); + do_sync(spos); + + zzzmca(test-1); + + HDELAY(100000); + } + + if (test == 4) { + long result, adrs[] = {0xe0021000009821e0UL, 0xc0003f3000000000UL, 0xc0000081101c0000UL, 0xc00000180e021004UL, 0xc00000180e022004UL, 0xc00000180e023004UL }; + long size[] = {1,2,4,8}; + int r, i, j, k; + + for (k=0; k<2; k++) { + for (i=0; i<6; i++) { + for (j=0; j<4; j++) { + printk("Probing 0x%lx, size %ld\n", adrs[i], size[j]); + result = -1; + r = ia64_sn_probe_io_slot (adrs[i], size[j], &result); + printk(" status %d, val 0x%lx\n", r, result); + udelay(100000); + } } } + } - if (mcatest == 2 || mcatest == 3) { - void zzzmca(int, int, int); - printk("About to cause unexpected MCA\n"); - zzzmca(mcatest, 0x32dead, 0x33dead); - } - if (mcatest == 4) { - long *p; - int delivery_mode = 5; - printk("About to try to cause an INIT on cpu 0\n"); - p = (long*)((0xc0000a0000000000LL | ((long)get_nasid())<<33) | 0x1800080); - *p = (delivery_mode << 8); - udelay(10000); - printk("Returned from INIT\n"); - } - if (mcatest == 5) { - int zzzspec(long); - int i; - long psr, dcr, res, val, addr=0xff00000000UL; - - dcr = ia64_get_dcr(); - for (i=0; i<5; i++) { - printk("Default DCR: 0x%lx\n", ia64_get_dcr()); - printk("zzzspec: 0x%x\n", zzzspec(addr)); - ia64_set_dcr(0); - printk("New DCR: 0x%lx\n", ia64_get_dcr()); - printk("zzzspec: 0x%x\n", zzzspec(addr)); - ia64_set_dcr(dcr); - res = ia64_sn_probe_io_slot(0xff00000000UL, 8, &val); - printk("zzzspec: probe %ld, 0x%lx\n", res, val); - psr = ia64_clear_ic(); - ia64_itc(0x2, 0xe00000ff00000000UL, - pte_val(pfn_pte(0xff00000000UL >> PAGE_SHIFT, - __pgprot(__DIRTY_BITS|_PAGE_PL_0|_PAGE_AR_RW))), _PAGE_SIZE_256M); - ia64_set_psr(psr); - ia64_srlz_i (); - } + if (test == 5) { + cpu = curcpu; + printk("CPU %d: About to send INIT to self (cpu %d)\n", curcpu, cpu); + HDELAY(100000); + sgi_mcatest_bkpt(); + do_sync(spos); + + platform_send_ipi(cpu, 0, IA64_IPI_DM_INIT, 0); + + HDELAY(100000); + printk("CPU %d: Returned from INIT\n", curcpu); } - if (mcatest == 6) { - int zzzspec(long); - int i; - long dcr, addr=0xe000000008000000UL; - - dcr = ia64_get_dcr(); - for (i=0; i<5; i++) { - printk("zzzspec: 0x%x\n", zzzspec(addr)); - ia64_set_dcr(0); - } - ia64_set_dcr(dcr); - } - if (mcatest == 7) { - int zzzspec2(long, long); - int i; - long addr=0xe000000008000000UL; - long addr2=0xe000000007000000UL; - - for (i=0; i<5; i++) { - printk("zzzspec2\n"); - zzzspec2(addr, addr2); + + if (test == 6) { + cpu = curcpu ^ 1; + printk("CPU %d: About to send INIT to other cpu (cpu %d)\n", curcpu, cpu); + HDELAY(100000); + sgi_mcatest_bkpt(); + do_sync(spos); + + platform_send_ipi(cpu, 0, IA64_IPI_DM_INIT, 0); + + HDELAY(100000); + printk("CPU %d: Done\n", curcpu); + } + + if (test == 7) { + printk("CPU %d: About to send INIT to non-existent cpu\n", curcpu); + HDELAY(100000); + sgi_mcatest_bkpt(); + do_sync(spos); + + sn_send_IPI_phys(0xffff, 0, IA64_IPI_DM_INIT); + + HDELAY(100000); + printk("CPU %d: Done\n", curcpu); + } + + if (test == 10) { + n = IS_RUNNING_ON_SIMULATOR() ? 10 : 10000000; + cpu = 0; + printk("CPU %d: IPI stress test. Target cpu 0\n", curcpu); + HDELAY(100000); + sgi_mcatest_bkpt(); + do_sync(spos); + + for (i=0; i 2 && cpu != curcpu) + platform_send_ipi(cpu, IA64_IPI_RESCHEDULE, IA64_IPI_DM_INT, 0); + + HDELAY(100000); + printk("CPU %d: Done\n", curcpu); + } + + if (test == 12) { + long adr = 0xe002200000000000UL; + n = IS_RUNNING_ON_SIMULATOR() ? 1000 : 100000; + printk("CPU %d: TLB flush stress test\n", curcpu); + HDELAY(100000); + sgi_mcatest_bkpt(); + do_sync(spos); + + for (i=0; i= smp_num_cpus-2) { + printk("Parking cpu %d\n", curcpu); + local_irq_disable(); + while(1); + } else { + printk("Waiting cpu %d\n", curcpu); + HDELAY(1000000); + } + HDELAY(1000000); + inited = 1; + } + if (test == 16 || test == 17) { + unsigned long t, shift, mask; + mask = (smp_num_cpus > 16) ? 0x1f : 0xf; + shift = 25-debug1; + do { + t = get_cycles(); + if (IS_RUNNING_ON_SIMULATOR()) + t = (t>>8); + else + t = (t>>shift); + t = t & mask; + } while (t == curcpu); + do { + t = get_cycles(); + if (IS_RUNNING_ON_SIMULATOR()) + t = (t>>8); + else + t = (t>>shift); + t = t & mask; + } while (t != curcpu); + } + if(debug3) printk("CPU %d: One TLB start\n", curcpu); + if (test != 17) platform_global_tlb_purge(adr, adr+PAGE_SIZE*debug0, 14); + if(debug3) printk("CPU %d: One TLB flush done\n", curcpu); + } + if (test == 20) { + local_irq_disable(); + set_led_bits(smp_processor_id(), 0xff); + while(1); + } + if (test == 21) { + extern long ia64_mca_stack[]; + int i, n; + volatile long *p, *up; + p = (volatile long*)__imva(ia64_mca_stack); + up = (volatile long*)(__pa(p) | __IA64_UNCACHED_OFFSET); + + if(!IS_RUNNING_ON_SIMULATOR()) printk("ZZZ get data in cache\n"); + for (n=0, i=0; i<100; i++) + n += *(p+i); + if(!IS_RUNNING_ON_SIMULATOR()) printk("ZZZ Make uncached refs to same data\n"); + for (n=0, i=0; i<100; i++) + n += *(up+i); + if(!IS_RUNNING_ON_SIMULATOR()) printk("ZZZ dirty the data via cached refs\n"); + for (n=0, i=0; i<100; i++) + *(p+i) = i; + if(!IS_RUNNING_ON_SIMULATOR()) printk("ZZZ Make uncached refs to same data\n"); + for (n=0, i=0; i<100; i++) + n += *(up+i); + if(!IS_RUNNING_ON_SIMULATOR()) printk("ZZZ Flushing cache\n"); + for (n=0, i=0; i<100; i++) + ia64_fc((void*)(p+i)); + printk("ZZZ done\n"); + } + if (test == 21) { + int i; + volatile long tb, t[10]; + for (i=0; i<10; i++) { + tb = debug3+ia64_get_itc(); + sgi_mcatest_bkpt(); + t[i] = ia64_get_itc() - tb; + } + for (i=0; i<10; i++) { + printk("ZZZ NULL 0x%lx\n", t[i]); + } + for (i=0; i<10; i++) { + tb = debug3+ia64_get_itc(); + ia64_pal_call_static(PAL_MC_DRAIN, 0, 0, 0, 0); + t[i] = ia64_get_itc() - tb; } + for (i=0; i<10; i++) { + printk("ZZZ DRAIN 0x%lx\n", t[i]); + } + } + if (test == 22) { + extern void machine_restart(char*); + printk("ZZZ machine_restart\n"); + machine_restart(0); } + if (test == 23) { + printk("ZZZ ia64_pal_halt_light\n"); + ia64_pal_halt_light(); + } + if (repeat) + goto again; + } diff -Nru a/arch/ia64/sn/kernel/setup.c b/arch/ia64/sn/kernel/setup.c --- a/arch/ia64/sn/kernel/setup.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/kernel/setup.c Wed Jan 15 16:57:28 2003 @@ -47,15 +47,14 @@ #include #include #include -#include +#include +#include +#include #include #include #include #include -#ifdef CONFIG_IA64_MCA -#include -#endif #include #include #include @@ -68,15 +67,24 @@ #include #include #include +#include +#include #ifdef CONFIG_IA64_SGI_SN2 #include #endif +DEFINE_PER_CPU(struct pda_s, pda_percpu); + extern void bte_init_node (nodepda_t *, cnodeid_t); extern void bte_init_cpu (void); -long sn_rtc_cycles_per_second; +unsigned long sn_rtc_cycles_per_second; +unsigned long sn_rtc_usec_per_cyc; + +partid_t sn_partid = -1; +char sn_system_serial_number_string[128]; +u64 sn_partition_serial_number; /* * This is the address of the RRegs in the HSpace of the global @@ -88,9 +96,9 @@ */ u64 master_node_bedrock_address = 0UL; -static void sn_init_pdas(void); +static void sn_init_pdas(char **); -extern struct irq_desc *_sn1_irq_desc[]; +extern struct irq_desc *_sn_irq_desc[]; #if defined(CONFIG_IA64_SGI_SN1) extern synergy_da_t *Synergy_da_indr[]; @@ -108,15 +116,15 @@ * code. This is just enough to make the console code think we're on a * VGA color display. */ -struct screen_info sn1_screen_info = { - .orig_x = 0, - .orig_y = 0, - .orig_video_mode = 3, - .orig_video_cols = 80, - .orig_video_ega_bx = 3, - .orig_video_lines = 25, - .orig_video_isVGA = 1, - .orig_video_points = 16 +struct screen_info sn_screen_info = { + orig_x: 0, + orig_y: 0, + orig_video_mode: 3, + orig_video_cols: 80, + orig_video_ega_bx: 3, + orig_video_lines: 25, + orig_video_isVGA: 1, + orig_video_points: 16 }; /* @@ -130,59 +138,81 @@ char drive_info[4*16]; /** - * sn1_map_nr - return the mem_map entry for a given kernel address + * sn_map_nr - return the mem_map entry for a given kernel address * @addr: kernel address to query * * Finds the mem_map entry for the kernel address given. Used by * virt_to_page() (asm-ia64/page.h), among other things. */ unsigned long -sn1_map_nr (unsigned long addr) +sn_map_nr (unsigned long addr) { - return MAP_NR_DISCONTIG(addr); + return BANK_MAP_NR(addr); } /** - * early_sn1_setup - early setup routine for SN platforms + * early_sn_setup - early setup routine for SN platforms * * Sets up an intial console to aid debugging. Intended primarily * for bringup, it's only called if %BRINGUP and %CONFIG_IA64_EARLY_PRINTK * are turned on. See start_kernel() in init/main.c. */ #if defined(CONFIG_IA64_EARLY_PRINTK) + void __init -early_sn1_setup(void) +early_sn_setup(void) { -#if defined(CONFIG_SERIAL_SGI_L1_PROTOCOL) - if ( IS_RUNNING_ON_SIMULATOR() ) -#endif - { -#ifdef CONFIG_IA64_SGI_SN2 - master_node_bedrock_address = (u64)REMOTE_HUB(get_nasid(), SH_JUNK_BUS_UART0); -#else + void ia64_sal_handler_init (void *entry_point, void *gpval); + efi_system_table_t *efi_systab; + efi_config_table_t *config_tables; + struct ia64_sal_systab *sal_systab; + struct ia64_sal_desc_entry_point *ep; + char *p; + int i; + + /* + * Parse enough of the SAL tables to locate the SAL entry point. Since, console + * IO on SN2 is done via SAL calls, early_printk wont work without this. + * + * This code duplicates some of the ACPI table parsing that is in efi.c & sal.c. + * Any changes to those file may have to be made hereas well. + */ + efi_systab = (efi_system_table_t*)__va(ia64_boot_param->efi_systab); + config_tables = __va(efi_systab->tables); + for (i = 0; i < efi_systab->nr_tables; i++) { + if (efi_guidcmp(config_tables[i].guid, SAL_SYSTEM_TABLE_GUID) == 0) { + sal_systab = __va(config_tables[i].table); + p = (char*)(sal_systab+1); + for (i = 0; i < sal_systab->entry_count; i++) { + if (*p == SAL_DESC_ENTRY_POINT) { + ep = (struct ia64_sal_desc_entry_point *) p; + ia64_sal_handler_init(__va(ep->sal_proc), __va(ep->gp)); + break; + } + p += SAL_DESC_SIZE(*p); + } + } + } + + if ( IS_RUNNING_ON_SIMULATOR() ) { +#if defined(CONFIG_IA64_SGI_SN1) master_node_bedrock_address = (u64)REMOTE_HSPEC_ADDR(get_nasid(), 0); +#else + master_node_bedrock_address = (u64)REMOTE_HUB(get_nasid(), SH_JUNK_BUS_UART0); #endif - printk(KERN_DEBUG "early_sn1_setup: setting master_node_bedrock_address to 0x%lx\n", master_node_bedrock_address); + printk(KERN_DEBUG "early_sn_setup: setting master_node_bedrock_address to 0x%lx\n", master_node_bedrock_address); } } -#endif /* CONFIG_IA64_EARLY_PRINTK */ +#endif /* CONFIG_IA64_SGI_SN1 */ -#ifdef NOT_YET_CONFIG_IA64_MCA -extern void ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs); -static struct irqaction mca_cpe_irqaction = { - .handler = ia64_mca_cpe_int_handler, - .flags = SA_INTERRUPT, - .name = "cpe_hndlr" -}; -#endif #ifdef CONFIG_IA64_MCA -extern int platform_irq_list[]; +extern int platform_intr_list[]; #endif extern nasid_t master_nasid; /** - * sn1_setup - SN platform setup routine + * sn_setup - SN platform setup routine * @cmdline_p: kernel command line * * Handles platform setup for SN machines. This includes determining @@ -190,82 +220,77 @@ * setting up per-node data areas. The console is also initialized here. */ void __init -sn1_setup(char **cmdline_p) +sn_setup(char **cmdline_p) { long status, ticks_per_sec, drift; int i; + int major = sn_sal_rev_major(), minor = sn_sal_rev_minor(); -#if defined(CONFIG_SERIAL) && !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL) - struct serial_struct req; + printk("SGI SAL version %x.%02x\n", major, minor); + + /* + * Confirm the SAL we're running on is recent enough... + */ + if ((major < SN_SAL_MIN_MAJOR) || (major == SN_SAL_MIN_MAJOR && + minor < SN_SAL_MIN_MINOR)) { + printk(KERN_ERR "This kernel needs SGI SAL version >= " + "%x.%02x\n", SN_SAL_MIN_MAJOR, SN_SAL_MIN_MINOR); + panic("PROM version too old\n"); + } + +#ifdef CONFIG_IA64_SGI_SN2 + { + extern void io_sh_swapper(int, int); + io_sh_swapper(get_nasid(), 0); + } #endif master_nasid = get_nasid(); (void)get_console_nasid(); +#ifndef CONFIG_IA64_SGI_SN1 + { + extern nasid_t get_master_baseio_nasid(void); + (void)get_master_baseio_nasid(); + } +#endif status = ia64_sal_freq_base(SAL_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec, &drift); - if (status != 0 || ticks_per_sec < 100000) - printk(KERN_WARNING "unable to determine platform RTC clock frequency\n"); + if (status != 0 || ticks_per_sec < 100000) { + printk(KERN_WARNING "unable to determine platform RTC clock frequency, guessing.\n"); + /* PROM gives wrong value for clock freq. so guess */ + sn_rtc_cycles_per_second = 1000000000000UL/30000UL; + } else sn_rtc_cycles_per_second = ticks_per_sec; + +#ifdef CONFIG_IA64_SGI_SN1 + /* PROM has wrong value on SN1 */ + sn_rtc_cycles_per_second = 990177; +#endif + sn_rtc_usec_per_cyc = ((1000000UL< PAGE_SIZE) + if ( (((unsigned long)pda & ~PAGE_MASK) + sizeof(pda_t)) > PAGE_SIZE) panic("overflow of cpu_data page"); /* @@ -348,11 +373,7 @@ void __init sn_cpu_init(void) { - int cpuid; - int cpuphyid; - int nasid; - int slice; - int cnode; + int cpuid, cpuphyid, nasid, nodeid, slice; /* * The boot cpu makes this call again after platform initialization is @@ -364,77 +385,104 @@ cpuid = smp_processor_id(); cpuphyid = ((ia64_get_lid() >> 16) & 0xffff); nasid = cpu_physical_id_to_nasid(cpuphyid); - cnode = nasid_to_cnodeid(nasid); + nodeid = cpu_to_node_map[cpuphyid]; slice = cpu_physical_id_to_slice(cpuphyid); - pda.p_nodepda = nodepdaindr[cnode]; - pda.led_address = (long*) (LED0 + (slice<active_cpu_count == 1) - nodepda->node_first_cpu = cpuid; - -#ifdef CONFIG_IA64_SGI_SN1 - { - int synergy; - synergy = cpu_physical_id_to_synergy(cpuphyid); - pda.p_subnodepda = &nodepdaindr[cnode]->snpda[synergy]; + memset(pda, 0, sizeof(pda_t)); + pda->p_nodepda = nodepdaindr[nodeid]; + pda->hb_count = HZ/2; + pda->hb_state = 0; + pda->idle_flag = 0; + pda->pio_write_status_addr = (volatile unsigned long *) + LOCAL_MMR_ADDR((slice < 2 ? SH_PIO_WRITE_STATUS_0 : SH_PIO_WRITE_STATUS_1 ) ); + pda->mem_write_status_addr = (volatile u64 *) + LOCAL_MMR_ADDR((slice < 2 ? SH_MEMORY_WRITE_STATUS_0 : SH_MEMORY_WRITE_STATUS_1 ) ); + + if (nodepda->node_first_cpu == cpuid) { + int buddy_nasid; + buddy_nasid = cnodeid_to_nasid(local_nodeid == numnodes - 1 ? 0 : local_nodeid + 1); + pda->pio_shub_war_cam_addr = (volatile unsigned long*)GLOBAL_MMR_ADDR(nasid, SH_PI_CAM_CONTROL); } -#endif -#ifdef CONFIG_IA64_SGI_SN2 + bte_init_cpu(); +} - /* - * We must use different memory allocators for first cpu (bootmem - * allocator) than for the other cpus (regular allocator). - */ - if (cpuid == 0) - irqpdaindr[cpuid] = alloc_bootmem_node(NODE_DATA(cpuid_to_cnodeid(cpuid)),sizeof(irqpda_t)); - else - irqpdaindr[cpuid] = page_address(alloc_pages_node(local_cnodeid(), GFP_KERNEL, get_order(sizeof(irqpda_t)))); - memset(irqpdaindr[cpuid], 0, sizeof(irqpda_t)); - pda.p_irqpda = irqpdaindr[cpuid]; - pda.pio_write_status_addr = (volatile unsigned long *)LOCAL_MMR_ADDR((slice < 2 ? SH_PIO_WRITE_STATUS_0 : SH_PIO_WRITE_STATUS_1 ) ); +#ifdef II_PRTE_TLB_WAR +long iiprt_lock[16*64] __cacheline_aligned; /* allow for NASIDs up to 64 */ #endif -#ifdef CONFIG_IA64_SGI_SN1 - pda.bedrock_rev_id = (volatile unsigned long *) LOCAL_HUB(LB_REV_ID); - if (cpuid_to_synergy(cpuid)) - /* CPU B */ - pda.pio_write_status_addr = (volatile unsigned long *) GBL_PERF_B_ADDR; - else - /* CPU A */ - pda.pio_write_status_addr = (volatile unsigned long *) GBL_PERF_A_ADDR; -#endif +#ifdef BUS_INT_WAR + +#include +#include + +void ia64_handle_irq (ia64_vector vector, struct pt_regs *regs); + +static spinlock_t irq_lock = SPIN_LOCK_UNLOCKED; + +#define IRQCPU(irq) ((irq)>>8) + +void +sn_add_polled_interrupt(int irq, int interval) +{ + unsigned long flags, irq_cnt; + sn_poll_entry_t *irq_list; + + irq_list = pdacpu(IRQCPU(irq)).pda_poll_entries;; + + spin_lock_irqsave(&irq_lock, flags); + irq_cnt = pdacpu(IRQCPU(irq)).pda_poll_entry_count; + irq_list[irq_cnt].irq = irq; + irq_list[irq_cnt].interval = interval; + irq_list[irq_cnt].tick = interval; + pdacpu(IRQCPU(irq)).pda_poll_entry_count++; + spin_unlock_irqrestore(&irq_lock, flags); - bte_init_cpu(); } +void +sn_delete_polled_interrupt(int irq) +{ + unsigned long flags, i, irq_cnt; + sn_poll_entry_t *irq_list; -/** - * cnodeid_to_cpuid - convert a cnode to a cpuid of a cpu on the node. - * @cnode: node to get a cpuid from - * - * Returns -1 if no cpus exist on the node. - * NOTE:BRINGUP ZZZ This is NOT a good way to find cpus on the node. - * Need a better way!! - */ -int -cnodeid_to_cpuid(int cnode) { - int cpu; - - for (cpu = 0; cpu < NR_CPUS; cpu++) { - if (!cpu_online(cpu)) continue; - if (cpuid_to_cnodeid(cpu) == cnode) + irq_list = pdacpu(IRQCPU(irq)).pda_poll_entries; + + spin_lock_irqsave(&irq_lock, flags); + irq_cnt = pdacpu(IRQCPU(irq)).pda_poll_entry_count; + for (i=0; ipda_poll_entries; + + for (i=0; ipda_poll_entry_count; i++, irq_list++) { + if (--irq_list->tick <= 0) { + irq_list->tick = irq_list->interval; + local_irq_save(flags); + ia64_handle_irq(irq_to_vector(irq_list->irq), 0); + local_irq_restore(flags); + } + } +} + +#endif diff -Nru a/arch/ia64/sn/kernel/sn1/Makefile b/arch/ia64/sn/kernel/sn1/Makefile --- a/arch/ia64/sn/kernel/sn1/Makefile Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/kernel/sn1/Makefile Wed Jan 15 16:57:29 2003 @@ -1,5 +1,5 @@ # -# ia64/platform/sn/sn1/Makefile +# arch/ia64/sn/kernel/sn1/Makefile # # Copyright (C) 1999,2001-2002 Silicon Graphics, Inc. All rights reserved. # @@ -32,6 +32,14 @@ # http://oss.sgi.com/projects/GenInfo/NoticeExplan # -obj-y := cache.o error.o iomv.o synergy.o sn1_smp.o -EXTRA_CFLAGS := -DLITTLE_ENDIAN +EXTRA_CFLAGS := -DLITTLE_ENDIAN + +.S.s: + $(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -o $*.s $< +.S.o: + $(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $< + +O_TARGET = sn1.o + +obj-y = cache.o error.o iomv.o synergy.o sn1_smp.o diff -Nru a/arch/ia64/sn/kernel/sn1/iomv.c b/arch/ia64/sn/kernel/sn1/iomv.c --- a/arch/ia64/sn/kernel/sn1/iomv.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/kernel/sn1/iomv.c Wed Jan 15 16:57:29 2003 @@ -3,17 +3,25 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#include #include +#include #include -#include #include +#include -static inline void * -sn1_io_addr(unsigned long port) +/** + * sn_io_addr - convert an in/out port to an i/o address + * @port: port to convert + * + * Legacy in/out instructions are converted to ld/st instructions + * on IA64. This routine will convert a port number into a valid + * SN i/o address. Used by sn_in*() and sn_out*(). + */ +void * +sn_io_addr(unsigned long port) { if (!IS_RUNNING_ON_SIMULATOR()) { return( (void *) (port | __IA64_UNCACHED_OFFSET)); @@ -38,182 +46,20 @@ } /** - * sn1_inb - read a byte from a port - * @port: port to read from - * - * Reads a byte from @port and returns it to the caller. - */ -unsigned int -sn1_inb (unsigned long port) -{ -return __ia64_inb ( port ); -} - -/** - * sn1_inw - read a word from a port - * @port: port to read from + * sn1_mmiob - I/O space memory barrier * - * Reads a word from @port and returns it to the caller. - */ -unsigned int -sn1_inw (unsigned long port) -{ -return __ia64_inw ( port ); -} - -/** - * sn1_inl - read a word from a port - * @port: port to read from - * - * Reads a word from @port and returns it to the caller. - */ -unsigned int -sn1_inl (unsigned long port) -{ -return __ia64_inl ( port ); -} - -/** - * sn1_outb - write a byte to a port - * @port: port to write to - * @val: value to write - * - * Writes @val to @port. - */ -void -sn1_outb (unsigned char val, unsigned long port) -{ -return __ia64_outb ( val, port ); -} - -/** - * sn1_outw - write a word to a port - * @port: port to write to - * @val: value to write - * - * Writes @val to @port. - */ -void -sn1_outw (unsigned short val, unsigned long port) -{ -return __ia64_outw ( val, port ); -} - -/** - * sn1_outl - write a word to a port - * @port: port to write to - * @val: value to write - * - * Writes @val to @port. - */ -void -sn1_outl (unsigned int val, unsigned long port) -{ -return __ia64_outl ( val, port ); -} - -/** - * sn1_inb - read a byte from a port - * @port: port to read from + * Acts as a memory mapped I/O barrier for platforms that queue writes to + * I/O space. This ensures that subsequent writes to I/O space arrive after + * all previous writes. For most ia64 platforms, this is a simple + * 'mf.a' instruction. For other platforms, mmiob() may have to read + * a chipset register to ensure ordering. * - * Reads a byte from @port and returns it to the caller. + * On SN1, we wait for the PIO_WRITE_STATUS Bedrock register to clear. */ -unsigned int -sn1_inb (unsigned long port) -{ - volatile unsigned char *addr = sn1_io_addr(port); - unsigned char ret; - - ret = *addr; - __ia64_mf_a(); - return ret; -} - -/** - * sn1_inw - read a word from a port - * 2port: port to read from - * - * Reads a word from @port and returns it to the caller. - */ -unsigned int -sn1_inw (unsigned long port) -{ - volatile unsigned short *addr = sn1_io_addr(port); - unsigned short ret; - - ret = *addr; - __ia64_mf_a(); - return ret; -} - -/** - * sn1_inl - read a word from a port - * @port: port to read from - * - * Reads a word from @port and returns it to the caller. - */ -unsigned int -sn1_inl (unsigned long port) -{ - volatile unsigned int *addr = sn1_io_addr(port); - unsigned int ret; - - ret = *addr; - __ia64_mf_a(); - return ret; -} - -/** - * sn1_outb - write a byte to a port - * @port: port to write to - * @val: value to write - * - * Writes @val to @port. - */ -void -sn1_outb (unsigned char val, unsigned long port) -{ - volatile unsigned char *addr = sn1_io_addr(port); - - *addr = val; - __ia64_mf_a(); -} - -/** - * sn1_outw - write a word to a port - * @port: port to write to - * @val: value to write - * - * Writes @val to @port. - */ -void -sn1_outw (unsigned short val, unsigned long port) -{ - volatile unsigned short *addr = sn1_io_addr(port); - - *addr = val; - __ia64_mf_a(); -} - -/** - * sn1_outl - write a word to a port - * @port: port to write to - * @val: value to write - * - * Writes @val to @port. - */ -void -sn1_outl (unsigned int val, unsigned long port) -{ - volatile unsigned int *addr = sn1_io_addr(port); - - *addr = val; - __ia64_mf_a(); -} -#endif /* SN1_IOPORTS */ - void -sn_mmiob () +sn1_mmiob (void) { - PIO_FLUSH(); + (volatile unsigned long) (*pda.bedrock_rev_id); + while (!(volatile unsigned long) (*pda.pio_write_status_addr)) + udelay(5); } diff -Nru a/arch/ia64/sn/kernel/sn1/sn1_smp.c b/arch/ia64/sn/kernel/sn1/sn1_smp.c --- a/arch/ia64/sn/kernel/sn1/sn1_smp.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/kernel/sn1/sn1_smp.c Wed Jan 15 16:57:29 2003 @@ -59,11 +59,16 @@ * to other cpus for flushing TLB ranges. */ typedef struct { - unsigned long start; - unsigned long end; - unsigned long nbits; - unsigned int rid; - atomic_t unfinished_count; + union { + struct { + unsigned long start; + unsigned long end; + unsigned long nbits; + unsigned int rid; + atomic_t unfinished_count; + } ptc; + char pad[SMP_CACHE_BYTES]; + }; } ptc_params_t; #define NUMPTC 512 @@ -149,11 +154,11 @@ return; do { - start = ptcParams->start; + start = ptcParams->ptc.start; saved_rid = (unsigned int) ia64_get_rr(start); - end = ptcParams->end; - nbits = ptcParams->nbits; - rid = ptcParams->rid; + end = ptcParams->ptc.end; + nbits = ptcParams->ptc.nbits; + rid = ptcParams->ptc.rid; if (saved_rid != rid) { ia64_set_rr(start, (unsigned long)rid); @@ -167,7 +172,7 @@ ia64_srlz_i(); - result = atomic_dec(&ptcParams->unfinished_count); + result = atomic_dec(&ptcParams->ptc.unfinished_count); #ifdef PTCDEBUG { int i = ptcParams-&ptcParamArray[0]; @@ -203,7 +208,7 @@ int backlog = 0; #endif - if (num_online_cpus() == 1) { + if (smp_num_cpus == 1) { sn1_ptc_l_range(start, end, nbits); return; } @@ -256,7 +261,7 @@ /* check the current pointer to the beginning */ ptr = params; while(--ptr >= &ptcParamArray[0]) { - if (atomic_read(&ptr->unfinished_count) == 0) + if (atomic_read(&ptr->ptc.unfinished_count) == 0) break; ++backlog; } @@ -265,7 +270,7 @@ /* check the end of the array */ ptr = &ptcParamArray[NUMPTC]; while (--ptr > params) { - if (atomic_read(&ptr->unfinished_count) == 0) + if (atomic_read(&ptr->ptc.unfinished_count) == 0) break; ++backlog; } @@ -275,12 +280,12 @@ #endif /* PTCDEBUG */ /* wait for the next entry to clear...should be rare */ - if (atomic_read(&next->unfinished_count) > 0) { + if (atomic_read(&next->ptc.unfinished_count) > 0) { #ifdef PTCDEBUG ptcParamsAllBusy++; - if (atomic_read(&nextnext->unfinished_count) == 0) { - if (atomic_read(&next->unfinished_count) > 0) { + if (atomic_read(&nextnext->ptc.unfinished_count) == 0) { + if (atomic_read(&next->ptc.unfinished_count) > 0) { panic("\nnonzero next zero nextnext %lx %lx\n", (long)next, (long)nextnext); } @@ -293,16 +298,16 @@ local_irq_restore(irqflags); /* now we know it's not this cpu, so just wait */ - while (atomic_read(&next->unfinished_count) > 0) { + while (atomic_read(&next->ptc.unfinished_count) > 0) { barrier(); } } - params->start = start; - params->end = end; - params->nbits = nbits; - params->rid = (unsigned int) ia64_get_rr(start); - atomic_set(¶ms->unfinished_count, num_online_cpus()); + params->ptc.start = start; + params->ptc.end = end; + params->ptc.nbits = nbits; + params->ptc.rid = (unsigned int) ia64_get_rr(start); + atomic_set(¶ms->ptc.unfinished_count, smp_num_cpus); /* The atomic_set above can hit memory *after* the update * to ptcParamsEmpty below, which opens a timing window @@ -335,25 +340,24 @@ * shouldn't be using user TLB entries. To change this to wait * for all the flushes to complete, enable the following code. */ -#ifdef SN1_SYNCHRONOUS_GLOBAL_TLB_PURGE +#if defined(SN1_SYNCHRONOUS_GLOBAL_TLB_PURGE) || defined(BUS_INT_WAR) /* this code is not tested */ /* wait for the flush to complete */ - while (atomic_read(¶ms.unfinished_count) > 1) + while (atomic_read(¶ms->ptc.unfinished_count) > 0) barrier(); - - atomic_set(¶ms->unfinished_count, 0); #endif } /** - * sn1_send_IPI - send an IPI to a processor - * @cpuid: target of the IPI + * sn_send_IPI_phys - send an IPI to a Nasid and slice + * @physid: physical cpuid to receive the interrupt. * @vector: command to send * @delivery_mode: delivery mechanism - * @redirect: redirect the IPI? * * Sends an IPI (interprocessor interrupt) to the processor specified by - * @cpuid. @delivery_mode can be one of the following + * @physid + * + * @delivery_mode can be one of the following * * %IA64_IPI_DM_INT - pend an interrupt * %IA64_IPI_DM_PMI - pend a PMI @@ -361,30 +365,53 @@ * %IA64_IPI_DM_INIT - pend an INIT interrupt */ void -sn1_send_IPI(int cpuid, int vector, int delivery_mode, int redirect) +sn_send_IPI_phys(long physid, int vector, int delivery_mode) { - long *p, nasid, slice; - static int off[4] = {0x1800080, 0x1800088, 0x1a00080, 0x1a00088}; + long *p; + long nasid, slice; - /* - * ZZZ - Replace with standard macros when available. - */ - nasid = cpuid_to_nasid(cpuid); - slice = cpuid_to_slice(cpuid); - p = (long*)(0xc0000a0000000000LL | (nasid<<33) | off[slice]); + static int off[4] = {0x1800080, 0x1800088, 0x1a00080, 0x1a00088}; -#if defined(ZZZBRINGUP) - { - static int count=0; - if (count++ < 10) printk("ZZ sendIPI 0x%x->0x%x, vec %d, nasid 0x%lx, slice %ld, adr 0x%lx\n", - smp_processor_id(), cpuid, vector, nasid, slice, (long)p); +#ifdef BUS_INT_WAR + if (vector != ap_wakeup_vector) { + return; } #endif + + nasid = cpu_physical_id_to_nasid(physid); + slice = cpu_physical_id_to_slice(physid); + + p = (long*)(0xc0000a0000000000LL | (nasid<<33) | off[slice]); + mb(); *p = (delivery_mode << 8) | (vector & 0xff); } +/** + * sn1_send_IPI - send an IPI to a processor + * @cpuid: target of the IPI + * @vector: command to send + * @delivery_mode: delivery mechanism + * @redirect: redirect the IPI? + * + * Sends an IPI (interprocessor interrupt) to the processor specified by + * @cpuid. @delivery_mode can be one of the following + * + * %IA64_IPI_DM_INT - pend an interrupt + * %IA64_IPI_DM_PMI - pend a PMI + * %IA64_IPI_DM_NMI - pend an NMI + * %IA64_IPI_DM_INIT - pend an INIT interrupt + */ +void +sn1_send_IPI(int cpuid, int vector, int delivery_mode, int redirect) +{ + long physid; + + physid = cpu_physical_id(cpuid); + + sn_send_IPI_phys(physid, vector, delivery_mode); +} #ifdef CONFIG_SMP #ifdef PTC_NOTYET @@ -425,7 +452,7 @@ { if (!ia64_ptc_domain_info) { printk("SMP: Can't find PTC domain info. Forcing UP mode\n"); - cpu_online_map = 1; + smp_num_cpus = 1; return; } diff -Nru a/arch/ia64/sn/kernel/sn1/synergy.c b/arch/ia64/sn/kernel/sn1/synergy.c --- a/arch/ia64/sn/kernel/sn1/synergy.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/kernel/sn1/synergy.c Wed Jan 15 16:57:29 2003 @@ -240,6 +240,7 @@ synergy_perf_t *p; int checked = 0; int err = 0; + unsigned long flags; /* bit 45 is enable */ modesel |= (1UL << 45); @@ -279,7 +280,7 @@ memset(p, 0, sizeof(synergy_perf_t)); p->modesel = modesel; - spin_lock_irq(&npdap->synergy_perf_lock); + spin_lock_irqsave(&npdap->synergy_perf_lock, flags); if (npdap->synergy_perf_data == NULL) { /* circular list */ p->next = p; @@ -290,7 +291,7 @@ p->next = npdap->synergy_perf_data->next; npdap->synergy_perf_data->next = p; } - spin_unlock_irq(&npdap->synergy_perf_lock); + spin_unlock_irqrestore(&npdap->synergy_perf_lock, flags); } } diff -Nru a/arch/ia64/sn/kernel/sn2/Makefile b/arch/ia64/sn/kernel/sn2/Makefile --- a/arch/ia64/sn/kernel/sn2/Makefile Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/kernel/sn2/Makefile Wed Jan 15 16:57:29 2003 @@ -1,5 +1,5 @@ # -# ia64/platform/sn/sn1/Makefile +# arch/ia64/sn/kernel/sn2/Makefile # # Copyright (C) 1999,2001-2002 Silicon Graphics, Inc. All rights reserved. # @@ -32,6 +32,5 @@ # http://oss.sgi.com/projects/GenInfo/NoticeExplan # -obj-y := cache.o iomv.o sn2_smp.o EXTRA_CFLAGS := -DLITTLE_ENDIAN diff -Nru a/arch/ia64/sn/kernel/sn2/iomv.c b/arch/ia64/sn/kernel/sn2/iomv.c --- a/arch/ia64/sn/kernel/sn2/iomv.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/kernel/sn2/iomv.c Wed Jan 15 16:57:29 2003 @@ -6,22 +6,23 @@ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#include #include -#include +#include +#include #include +#include +#include -#ifdef Colin /* Use the same calls as Generic IA64 defined in io.h */ /** - * sn1_io_addr - convert a in/out port to an i/o address + * sn_io_addr - convert an in/out port to an i/o address * @port: port to convert * * Legacy in/out instructions are converted to ld/st instructions * on IA64. This routine will convert a port number into a valid - * SN i/o address. Used by sn1_in*() and sn1_out*(). + * SN i/o address. Used by sn_in*() and sn_out*(). */ -static inline void * -sn1_io_addr(unsigned long port) +void * +sn_io_addr(unsigned long port) { if (!IS_RUNNING_ON_SIMULATOR()) { return( (void *) (port | __IA64_UNCACHED_OFFSET)); @@ -46,177 +47,22 @@ } /** - * sn1_inb - read a byte from a port - * @port: port to read from - * - * Reads a byte from @port and returns it to the caller. - */ -unsigned int -sn1_inb (unsigned long port) -{ -return __ia64_inb ( port ); -} - -/** - * sn1_inw - read a word from a port - * @port: port to read from - * - * Reads a word from @port and returns it to the caller. - */ -unsigned int -sn1_inw (unsigned long port) -{ -return __ia64_inw ( port ); -} - -/** - * sn1_inl - read a word from a port - * @port: port to read from - * - * Reads a word from @port and returns it to the caller. - */ -unsigned int -sn1_inl (unsigned long port) -{ -return __ia64_inl ( port ); -} - -/** - * sn1_outb - write a byte to a port - * @port: port to write to - * @val: value to write - * - * Writes @val to @port. - */ -void -sn1_outb (unsigned char val, unsigned long port) -{ -return __ia64_outb ( val, port ); -} - -/** - * sn1_outw - write a word to a port - * @port: port to write to - * @val: value to write - * - * Writes @val to @port. - */ -void -sn1_outw (unsigned short val, unsigned long port) -{ -return __ia64_outw ( val, port ); -} - -/** - * sn1_outl - write a word to a port - * @port: port to write to - * @val: value to write - * - * Writes @val to @port. - */ -void -sn1_outl (unsigned int val, unsigned long port) -{ -return __ia64_outl ( val, port ); -} - -/** - * sn1_inb - read a byte from a port - * @port: port to read from - * - * Reads a byte from @port and returns it to the caller. - */ -unsigned int -sn1_inb (unsigned long port) -{ - volatile unsigned char *addr = sn1_io_addr(port); - unsigned char ret; - - ret = *addr; - __ia64_mf_a(); - return ret; -} - -/** - * sn1_inw - read a word from a port - * 2port: port to read from - * - * Reads a word from @port and returns it to the caller. - */ -unsigned int -sn1_inw (unsigned long port) -{ - volatile unsigned short *addr = sn1_io_addr(port); - unsigned short ret; - - ret = *addr; - __ia64_mf_a(); - return ret; -} - -/** - * sn1_inl - read a word from a port - * @port: port to read from - * - * Reads a word from @port and returns it to the caller. - */ -unsigned int -sn1_inl (unsigned long port) -{ - volatile unsigned int *addr = sn1_io_addr(port); - unsigned int ret; - - ret = *addr; - __ia64_mf_a(); - return ret; -} - -/** - * sn1_outb - write a byte to a port - * @port: port to write to - * @val: value to write + * sn2_mmiob - I/O space memory barrier * - * Writes @val to @port. - */ -void -sn1_outb (unsigned char val, unsigned long port) -{ - volatile unsigned char *addr = sn1_io_addr(port); - - *addr = val; - __ia64_mf_a(); -} - -/** - * sn1_outw - write a word to a port - * @port: port to write to - * @val: value to write + * Acts as a memory mapped I/O barrier for platforms that queue writes to + * I/O space. This ensures that subsequent writes to I/O space arrive after + * all previous writes. For most ia64 platforms, this is a simple + * 'mf.a' instruction. For other platforms, mmiob() may have to read + * a chipset register to ensure ordering. * - * Writes @val to @port. - */ -void -sn1_outw (unsigned short val, unsigned long port) -{ - volatile unsigned short *addr = sn1_io_addr(port); - - *addr = val; - __ia64_mf_a(); -} - -/** - * sn1_outl - write a word to a port - * @port: port to write to - * @val: value to write + * On SN2, we wait for the PIO_WRITE_STATUS SHub register to clear. + * See PV 871084 for details about the WAR about zero value. * - * Writes @val to @port. */ void -sn1_outl (unsigned int val, unsigned long port) +sn2_mmiob (void) { - volatile unsigned int *addr = sn1_io_addr(port); - - *addr = val; - __ia64_mf_a(); + while ((((volatile unsigned long) (*pda->pio_write_status_addr)) & SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK) != + SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK) + udelay(1); } - -#endif diff -Nru a/arch/ia64/sn/kernel/sn2/sn2_smp.c b/arch/ia64/sn/kernel/sn2/sn2_smp.c --- a/arch/ia64/sn/kernel/sn2/sn2_smp.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/kernel/sn2/sn2_smp.c Wed Jan 15 16:57:29 2003 @@ -46,6 +46,7 @@ #include #include #include +#include #include #include #include @@ -53,6 +54,310 @@ #include #include #include +#include +#include + +void sn2_ptc_deadlock_recovery(unsigned long data0, unsigned long data1); + + +static spinlock_t sn2_global_ptc_lock __cacheline_aligned = SPIN_LOCK_UNLOCKED; + +static unsigned long sn2_ptc_deadlock_count; + + +static inline unsigned long +wait_piowc(void) +{ + volatile unsigned long *piows; + unsigned long ws; + + piows = pda->pio_write_status_addr; + do { + __asm__ __volatile__ ("mf.a" ::: "memory"); + } while (((ws = *piows) & SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK) != + SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK); + return ws; +} + +#ifdef PTCG_WAR +/* + * The following structure is used to pass params thru smp_call_function + * to other cpus for flushing TLB ranges. + */ +typedef struct { + unsigned long start; + unsigned long end; + unsigned long nbits; + unsigned int rid; + atomic_t unfinished_count; + char fill[96]; +} ptc_params_t; + +#define NUMPTC 512 + +static ptc_params_t ptcParamArray[NUMPTC] __attribute__((__aligned__(128))); + +/* use separate cache lines on ptcParamsNextByCpu to avoid false sharing */ +static ptc_params_t *ptcParamsNextByCpu[NR_CPUS*16] __attribute__((__aligned__(128))); +static volatile ptc_params_t *ptcParamsEmpty __cacheline_aligned; + +/*REFERENCED*/ +static spinlock_t ptcParamsLock __cacheline_aligned = SPIN_LOCK_UNLOCKED; + +static int ptcInit = 0; +#ifdef PTCDEBUG +static int ptcParamsAllBusy = 0; /* debugging/statistics */ +static int ptcCountBacklog = 0; +static int ptcBacklog[NUMPTC+1]; +static char ptcParamsCounts[NR_CPUS][NUMPTC] __attribute__((__aligned__(128))); +static char ptcParamsResults[NR_CPUS][NUMPTC] __attribute__((__aligned__(128))); +#endif + +/* + * Make smp_send_flush_tlbsmp_send_flush_tlb() a weak reference, + * so that we get a clean compile with the ia64 patch without the + * actual SN1 specific code in arch/ia64/kernel/smp.c. + */ +extern void smp_send_flush_tlb (void) __attribute((weak)); + + +/** + * sn1_ptc_l_range - purge local translation cache + * @start: start of virtual address range + * @end: end of virtual address range + * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc)) + * + * Purges the range specified from the local processor's translation cache + * (as opposed to the translation registers). Note that more than the specified + * range *may* be cleared from the cache by some processors. + * + * This is probably not good enough, but I don't want to try to make it better + * until I get some statistics on a running system. At a minimum, we should only + * send IPIs to 1 processor in each TLB domain & have it issue a ptc.g on it's + * own FSB. Also, we only have to serialize per FSB, not globally. + * + * More likely, we will have to do some work to reduce the frequency of calls to + * this routine. + */ +static inline void +sn1_ptc_l_range(unsigned long start, unsigned long end, unsigned long nbits) +{ + do { + __asm__ __volatile__ ("ptc.l %0,%1" :: "r"(start), "r"(nbits<<2) : "memory"); + start += (1UL << nbits); + } while (start < end); + ia64_srlz_d(); +} + +/** + * sn1_received_flush_tlb - cpu tlb flush routine + * + * Flushes the TLB of a given processor. + */ +void +sn1_received_flush_tlb(void) +{ + unsigned long start, end, nbits; + unsigned int rid, saved_rid; + int cpu = smp_processor_id(); + int result; + ptc_params_t *ptcParams; + + ptcParams = ptcParamsNextByCpu[cpu*16]; + if (ptcParams == ptcParamsEmpty) + return; + + do { + start = ptcParams->start; + saved_rid = (unsigned int) ia64_get_rr(start); + end = ptcParams->end; + nbits = ptcParams->nbits; + rid = ptcParams->rid; + + if (saved_rid != rid) { + ia64_set_rr(start, (unsigned long)rid); + ia64_srlz_d(); + } + + sn1_ptc_l_range(start, end, nbits); + + if (saved_rid != rid) + ia64_set_rr(start, (unsigned long)saved_rid); + + ia64_srlz_i(); + + result = atomic_dec(&ptcParams->unfinished_count); +#ifdef PTCDEBUG + { + int i = ptcParams-&ptcParamArray[0]; + ptcParamsResults[cpu][i] = (char) result; + ptcParamsCounts[cpu][i]++; + } +#endif /* PTCDEBUG */ + + if (++ptcParams == &ptcParamArray[NUMPTC]) + ptcParams = &ptcParamArray[0]; + + } while (ptcParams != ptcParamsEmpty); + + ptcParamsNextByCpu[cpu*16] = ptcParams; +} + +/** + * sn1_global_tlb_purge - flush a translation cache range on all processors + * @start: start of virtual address range to flush + * @end: end of virtual address range + * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc)) + * + * Flushes the translation cache of all processors from @start to @end. + */ +void +sn1_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbits) +{ + ptc_params_t *params; + ptc_params_t *next; + unsigned long irqflags; +#ifdef PTCDEBUG + ptc_params_t *nextnext; + int backlog = 0; +#endif + + if (smp_num_cpus == 1) { + sn1_ptc_l_range(start, end, nbits); + return; + } + + if (in_interrupt()) { + /* + * If at interrupt level and cannot get spinlock, + * then do something useful by flushing own tlbflush queue + * so as to avoid a possible deadlock. + */ + while (!spin_trylock(&ptcParamsLock)) { + local_irq_save(irqflags); + sn1_received_flush_tlb(); + local_irq_restore(irqflags); + udelay(10); /* take it easier on the bus */ + } + } else { + spin_lock(&ptcParamsLock); + } + + if (!ptcInit) { + int cpu; + ptcInit = 1; + memset(ptcParamArray, 0, sizeof(ptcParamArray)); + ptcParamsEmpty = &ptcParamArray[0]; + for (cpu=0; cpu= &ptcParamArray[0]) { + if (atomic_read(&ptr->unfinished_count) == 0) + break; + ++backlog; + } + + if (backlog) { + /* check the end of the array */ + ptr = &ptcParamArray[NUMPTC]; + while (--ptr > params) { + if (atomic_read(&ptr->unfinished_count) == 0) + break; + ++backlog; + } + } + ptcBacklog[backlog]++; + } +#endif /* PTCDEBUG */ + + /* wait for the next entry to clear...should be rare */ + if (atomic_read(&next->unfinished_count) > 0) { +#ifdef PTCDEBUG + ptcParamsAllBusy++; + + if (atomic_read(&nextnext->unfinished_count) == 0) { + if (atomic_read(&next->unfinished_count) > 0) { + panic("\nnonzero next zero nextnext %lx %lx\n", + (long)next, (long)nextnext); + } + } +#endif + + /* it could be this cpu that is behind */ + local_irq_save(irqflags); + sn1_received_flush_tlb(); + local_irq_restore(irqflags); + + /* now we know it's not this cpu, so just wait */ + while (atomic_read(&next->unfinished_count) > 0) { + barrier(); + } + } + + params->start = start; + params->end = end; + params->nbits = nbits; + params->rid = (unsigned int) ia64_get_rr(start); + atomic_set(¶ms->unfinished_count, smp_num_cpus); + + /* The atomic_set above can hit memory *after* the update + * to ptcParamsEmpty below, which opens a timing window + * that other cpus can squeeze into! + */ + mb(); + + /* everything is ready to process: + * -- global lock is held + * -- new entry + 1 is free + * -- new entry is set up + * so now: + * -- update the global next pointer + * -- unlock the global lock + * -- send IPI to notify other cpus + * -- process the data ourselves + */ + ptcParamsEmpty = next; + spin_unlock(&ptcParamsLock); + smp_send_flush_tlb(); + + local_irq_save(irqflags); + sn1_received_flush_tlb(); + local_irq_restore(irqflags); + + /* + * Since IPIs are polled event (for now), we need to wait til the + * TLB flush has started. + * wait for the flush to complete + */ + while (atomic_read(¶ms->unfinished_count) > 0) + barrier(); +} + +#endif /* PTCG_WAR */ + /** * sn2_global_tlb_purge - globally purge translation cache of virtual address range @@ -63,54 +368,111 @@ * Purges the translation caches of all processors of the given virtual address * range. */ + void sn2_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbits) { - int cnode, nasid; - volatile long *ptc0, *ptc1, *piows; - unsigned long ws, next, data0, data1; - - piows = (long*)LOCAL_MMR_ADDR(get_slice() ? SH_PIO_WRITE_STATUS_1 : SH_PIO_WRITE_STATUS_0); + int cnode, mycnode, nasid; + volatile unsigned long *ptc0, *ptc1; + unsigned long flags=0, data0, data1; + + /* + * Special case 1 cpu & 1 node. Use local purges. + */ +#ifdef PTCG_WAR + sn1_global_tlb_purge(start, end, nbits); + return; +#endif /* PTCG_WAR */ + data0 = (1UL<>8)<pio_write_status_addr; + + mycnode = local_nodeid; + + for (cnode = 0; cnode < numnodes; cnode++) { + if (is_headless_node(cnode) || cnode == mycnode) + continue; + nasid = cnodeid_to_nasid(cnode); + ptc0 = CHANGE_NASID(nasid, ptc0); + ptc1 = CHANGE_NASID(nasid, ptc1); + sn2_ptc_deadlock_recovery_core(ptc0, data0, ptc1, data1, piows); + } } /** - * sn2_send_IPI - send an IPI to a processor - * @cpuid: target of the IPI + * sn_send_IPI_phys - send an IPI to a Nasid and slice + * @physid: physical cpuid to receive the interrupt. * @vector: command to send * @delivery_mode: delivery mechanism - * @redirect: redirect the IPI? * - * Sends an IPI (InterProcessor Interrupt) to the processor specified by - * @cpuid. @vector specifies the command to send, while @delivery_mode can - * be one of the following + * Sends an IPI (interprocessor interrupt) to the processor specified by + * @physid + * + * @delivery_mode can be one of the following * * %IA64_IPI_DM_INT - pend an interrupt * %IA64_IPI_DM_PMI - pend a PMI @@ -118,42 +480,60 @@ * %IA64_IPI_DM_INIT - pend an INIT interrupt */ void -sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect) +sn_send_IPI_phys(long physid, int vector, int delivery_mode) { - long *p, val; - long physid; long nasid, slice; + long val; + volatile long *p; + +#ifdef BUS_INT_WAR + if (vector != ap_wakeup_vector && delivery_mode == IA64_IPI_DM_INT) { + return; + } +#endif - physid = cpu_physical_id(cpuid); nasid = cpu_physical_id_to_nasid(physid); slice = cpu_physical_id_to_slice(physid); - p = (long*)GLOBAL_MMR_ADDR(nasid, SH_IPI_INT); + p = (long*)GLOBAL_MMR_PHYS_ADDR(nasid, SH_IPI_INT); val = (1UL<0x%x, vec %d, nasid 0x%lx, slice %ld, adr 0x%lx, val 0x%lx\n", - smp_processor_id(), cpuid, vector, nasid, slice, (long)p, val); - } -#endif mb(); - *p = val; - + pio_phys_write_mmr(p, val); + +#ifndef CONFIG_SHUB_1_0_SPECIFIC + /* doesnt work on shub 1.0 */ + wait_piowc(); +#endif } /** - * init_sn2_smp_config - initialize SN2 smp configuration + * sn2_send_IPI - send an IPI to a processor + * @cpuid: target of the IPI + * @vector: command to send + * @delivery_mode: delivery mechanism + * @redirect: redirect the IPI? * - * currently a NOP. + * Sends an IPI (InterProcessor Interrupt) to the processor specified by + * @cpuid. @vector specifies the command to send, while @delivery_mode can + * be one of the following + * + * %IA64_IPI_DM_INT - pend an interrupt + * %IA64_IPI_DM_PMI - pend a PMI + * %IA64_IPI_DM_NMI - pend an NMI + * %IA64_IPI_DM_INIT - pend an INIT interrupt */ -void __init -init_sn2_smp_config(void) +void +sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect) { + long physid; + physid = cpu_physical_id(cpuid); + + sn_send_IPI_phys(physid, vector, delivery_mode); } + diff -Nru a/arch/ia64/sn/kernel/sn_asm.S b/arch/ia64/sn/kernel/sn_asm.S --- a/arch/ia64/sn/kernel/sn_asm.S Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/kernel/sn_asm.S Wed Jan 15 16:57:28 2003 @@ -1,6 +1,33 @@ - /* - * Copyright (c) 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2000-2002 Silicon Graphics, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Further, this software is distributed without any warranty that it is + * free of the rightful claim of any third person regarding infringement + * or the like. Any license provided herein, whether implied or + * otherwise, applies only to this software file. Patent licenses, if + * any, provided herein do not apply to combinations of this program with + * other software, or any other product whatsoever. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, + * Mountain View, CA 94043, or: + * + * http://www.sgi.com + * + * For further information regarding this notice, see: + * + * http://oss.sgi.com/projects/GenInfo/NoticeExplan */ #include @@ -8,9 +35,10 @@ // Testing only. // Routine will cause MCAs -// zzzmsa(n) +// zzzmca(n) // n=0 MCA via duplicate TLB dropin -// n=0 MCA via read of garbage address +// n=1 MCA via read of garbage address +// n=2 MCA via lfetch read of garbage address // #define ITIR(key, ps) ((key<<8) | (ps<<2)) @@ -45,20 +73,30 @@ rsm 0x2000;; srlz.d; - mov r11 = 1 + mov r11 = 5 mov r3 = ITIR(0,TLB_PAGESIZE);; mov cr.itir = r3 mov r10 = 0;; itr.d dtr[r11] = r10;; - mov r11 = 2 + mov r11 = 6 itr.d dtr[r11] = r10;; br 9f -1: movl r8=0xfe00000048;; - ld8 r9=[r8];; +1: + cmp.eq p6,p7=1,r32 +#ifdef CONFIG_IA64_SGI_SN1 + movl r8=0xe00000fe00000048;; +#else + movl r8=0xe0007fb000000048;; +#endif + (p6) ld8 r9=[r8] + (p7) lfetch.fault.nt2 [r8] + ;; mf + ;; mf.a + ;; srlz.d 9: mov ar.pfs=loc4 @@ -66,83 +104,4 @@ .endp zzzmca - .global zzzspec - .proc zzzspec -zzzspec: - mov r8=r32 - movl r9=0xe000000000000000 - movl r10=0x4000;; - ld8.s r16=[r8];; - ld8.s r17=[r9];; - add r8=r8,r10;; - ld8.s r18=[r8];; - add r8=r8,r10;; - ld8.s r19=[r8];; - add r8=r8,r10;; - ld8.s r20=[r8];; - mov r8=r0 - tnat.nz p6,p0=r16 - tnat.nz p7,p0=r17 - tnat.nz p8,p0=r18 - tnat.nz p9,p0=r19 - tnat.nz p10,p0=r20;; - (p6) dep r8=-1,r8,0,1;; - (p7) dep r8=-1,r8,1,1;; - (p8) dep r8=-1,r8,2,1;; - (p9) dep r8=-1,r8,3,1;; - (p10) dep r8=-1,r8,4,1;; - br.ret.sptk rp - .endp zzzspec - - .global zzzspec2 - .proc zzzspec2 -zzzspec2: - cmp.eq p6,p7=r2,r2 - movl r16=0xc0000a0001000020 - ;; - mf - ;; - ld8 r9=[r16] - (p6) br.spnt 1f - ld8 r10=[r32] - ;; - 1: mf.a - mf - - ld8 r9=[r16];; - cmp.ne p6,p7=r9,r16 - (p6) br.spnt 1f - ld8 r10=[r32] - ;; - 1: mf.a - mf - - ld8 r9=[r33];; - cmp.ne p6,p7=r9,r33 - (p6) br.spnt 1f - ld8 r10=[r32] - ;; - 1: mf.a - mf - - tpa r23=r32 - add r20=512,r33 - add r21=1024,r33;; - ld8 r9=[r20] - ld8 r10=[r21];; - nop.i 0 - { .mib - nop.m 0 - cmp.ne p6,p7=r10,r33 - (p6) br.spnt 1f - } - ld8 r10=[r32] - ;; - 1: mf.a - mf - br.ret.sptk rp - - .endp zzzspec - #endif - diff -Nru a/arch/ia64/sn/kernel/sn_ksyms.c b/arch/ia64/sn/kernel/sn_ksyms.c --- a/arch/ia64/sn/kernel/sn_ksyms.c Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/sn/kernel/sn_ksyms.c Wed Jan 15 16:57:29 2003 @@ -15,15 +15,8 @@ #include #include - -/* - * other stuff (more to be added later, cleanup then) - */ -EXPORT_SYMBOL(sn1_pci_map_sg); -EXPORT_SYMBOL(sn1_pci_unmap_sg); -EXPORT_SYMBOL(sn1_pci_alloc_consistent); -EXPORT_SYMBOL(sn1_pci_free_consistent); -EXPORT_SYMBOL(sn1_dma_address); +#include +#include #include #include @@ -52,13 +45,39 @@ EXPORT_SYMBOL(hwgraph_edge_add); EXPORT_SYMBOL(pciio_info_master_get); EXPORT_SYMBOL(pciio_info_get); + #ifdef CONFIG_IA64_SGI_SN_DEBUG EXPORT_SYMBOL(__pa_debug); EXPORT_SYMBOL(__va_debug); #endif +/* Support IPIs for loaded modules. */ +EXPORT_SYMBOL(sn_send_IPI_phys); + +/* symbols referenced by partitioning modules */ +#include +EXPORT_SYMBOL(bte_unaligned_copy); +#include +EXPORT_SYMBOL(ia64_sal); + +#ifdef CONFIG_IA64_SGI_SN2 +#include +EXPORT_SYMBOL(sal_lock); +EXPORT_SYMBOL(sn_partid); +EXPORT_SYMBOL(sn_local_partid); +EXPORT_SYMBOL(sn_system_serial_number_string); +EXPORT_SYMBOL(sn_partition_serial_number); +#endif + /* added by tduffy 04.08.01 to fix depmod issues */ #include -EXPORT_SYMBOL(sn1_pci_unmap_single); -EXPORT_SYMBOL(sn1_pci_map_single); -EXPORT_SYMBOL(sn1_pci_dma_sync_single); + +#ifdef BUS_INT_WAR +extern void sn_add_polled_interrupt(int, int); +extern void sn_delete_polled_interrupt(int); +EXPORT_SYMBOL(sn_add_polled_interrupt); +EXPORT_SYMBOL(sn_delete_polled_interrupt); +#endif + +extern nasid_t master_nasid; +EXPORT_SYMBOL(master_nasid); diff -Nru a/arch/ia64/sn/kernel/sv.c b/arch/ia64/sn/kernel/sv.c --- a/arch/ia64/sn/kernel/sv.c Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/kernel/sv.c Wed Jan 15 16:57:28 2003 @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved + * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved * * This implemenation of synchronization variables is heavily based on * one done by Steve Lord @@ -210,7 +210,7 @@ */ /* don't need the _irqsave part, but there is no wq_write_lock() */ - wq_write_lock_irqsave(&sv->sv_waiters.lock, flags); + write_lock_irqsave(&sv->sv_waiters.lock, flags); #ifdef EXCLUSIVE_IN_QUEUE wait.flags |= WQ_FLAG_EXCLUSIVE; @@ -228,7 +228,7 @@ (void *)sv, sv->sv_flags); BUG(); } - wq_write_unlock_irqrestore(&sv->sv_waiters.lock, flags); + write_unlock_irqrestore(&sv->sv_waiters.lock, flags); if(sv_wait_flags & SV_WAIT_SIG) set_current_state(TASK_EXCLUSIVE | TASK_INTERRUPTIBLE ); diff -Nru a/arch/ia64/sn/tools/make_textsym b/arch/ia64/sn/tools/make_textsym --- a/arch/ia64/sn/tools/make_textsym Wed Jan 15 16:57:28 2003 +++ b/arch/ia64/sn/tools/make_textsym Wed Jan 15 16:57:28 2003 @@ -44,7 +44,7 @@ [ -f $VMLINUX ] || help -$OBJDUMP -t $LINUX | sort > $TMPSYM +$OBJDUMP -t $LINUX | egrep -v '__ks' | sort > $TMPSYM SN1=`egrep "dig_setup|Synergy_da_indr" $TMPSYM|wc -l` # Dataprefix and textprefix correspond to the VGLOBAL_BASE and VPERNODE_BASE. @@ -58,74 +58,74 @@ # pipe everything thru sort echo "TEXTSYM V1.0" (cat < * * Note that this file has dual use: when building the kernel @@ -53,7 +53,9 @@ { "UNW_FRAME_INFO_SIZE", sizeof (struct unw_frame_info) }, { "", 0 }, /* spacer */ { "IA64_TASK_THREAD_KSP_OFFSET", offsetof (struct task_struct, thread.ksp) }, + { "IA64_TASK_THREAD_ON_USTACK_OFFSET", offsetof (struct task_struct, thread.on_ustack) }, { "IA64_TASK_PID_OFFSET", offsetof (struct task_struct, pid) }, + { "IA64_TASK_TGID_OFFSET", offsetof (struct task_struct, tgid) }, { "IA64_PT_REGS_CR_IPSR_OFFSET", offsetof (struct pt_regs, cr_ipsr) }, { "IA64_PT_REGS_CR_IIP_OFFSET", offsetof (struct pt_regs, cr_iip) }, { "IA64_PT_REGS_CR_IFS_OFFSET", offsetof (struct pt_regs, cr_ifs) }, diff -Nru a/arch/ia64/vmlinux.lds.S b/arch/ia64/vmlinux.lds.S --- a/arch/ia64/vmlinux.lds.S Wed Jan 15 16:57:29 2003 +++ b/arch/ia64/vmlinux.lds.S Wed Jan 15 16:57:29 2003 @@ -97,6 +97,12 @@ .init.data : AT(ADDR(.init.data) - PAGE_OFFSET) { *(.init.data) } + + __initramfs_start = .; + .init.ramfs : AT(ADDR(.init.ramfs) - PAGE_OFFSET) + { *(.init.ramfs) } + __initramfs_end = .; + . = ALIGN(16); __setup_start = .; .init.setup : AT(ADDR(.init.setup) - PAGE_OFFSET) @@ -135,10 +141,6 @@ . = ALIGN(SMP_CACHE_BYTES); .data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - PAGE_OFFSET) { *(.data.cacheline_aligned) } - - /* Kernel symbol names for modules: */ - .kstrtab : AT(ADDR(.kstrtab) - PAGE_OFFSET) - { *(.kstrtab) } /* Per-cpu data: */ . = ALIGN(PERCPU_PAGE_SIZE); diff -Nru a/drivers/acpi/osl.c b/drivers/acpi/osl.c --- a/drivers/acpi/osl.c Wed Jan 15 16:57:29 2003 +++ b/drivers/acpi/osl.c Wed Jan 15 16:57:29 2003 @@ -223,7 +223,14 @@ acpi_os_install_interrupt_handler(u32 irq, OSD_HANDLER handler, void *context) { #ifdef CONFIG_IA64 - irq = gsi_to_vector(irq); + int vector; + + vector = acpi_irq_to_vector(irq); + if (vector < 0) { + printk(KERN_ERR PREFIX "SCI (IRQ%d) not registerd\n", irq); + return AE_OK; + } + irq = vector; #endif acpi_irq_irq = irq; acpi_irq_handler = handler; @@ -241,7 +248,7 @@ { if (acpi_irq_handler) { #ifdef CONFIG_IA64 - irq = gsi_to_vector(irq); + irq = acpi_irq_to_vector(irq); #endif free_irq(irq, acpi_irq); acpi_irq_handler = NULL; diff -Nru a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c --- a/drivers/acpi/pci_irq.c Wed Jan 15 16:57:29 2003 +++ b/drivers/acpi/pci_irq.c Wed Jan 15 16:57:29 2003 @@ -36,6 +36,9 @@ #ifdef CONFIG_X86_IO_APIC #include #endif +#ifdef CONFIG_IOSAPIC +# include +#endif #include "acpi_bus.h" #include "acpi_drivers.h" @@ -250,6 +253,8 @@ return_VALUE(0); } + entry->irq = entry->link.index; + if (!entry->irq && entry->link.handle) { entry->irq = acpi_pci_link_get_irq(entry->link.handle, entry->link.index); if (!entry->irq) { @@ -355,7 +360,7 @@ return_VALUE(0); } - dev->irq = irq; + dev->irq = gsi_to_irq(irq); ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device %s using IRQ %d\n", dev->slot_name, dev->irq)); diff -Nru a/drivers/char/agp/Kconfig b/drivers/char/agp/Kconfig --- a/drivers/char/agp/Kconfig Wed Jan 15 16:57:29 2003 +++ b/drivers/char/agp/Kconfig Wed Jan 15 16:57:29 2003 @@ -29,8 +29,11 @@ bool "/dev/agpgart (AGP Support)" depends on GART_IOMMU +config AGP3 + bool "AGP 3.0 compliance (EXPERIMENTAL)" + config AGP_INTEL - bool "Intel 440LX/BX/GX and I815/I820/I830M/I830MP/I840/I845/I850/I860 support" + tristate "Intel 440LX/BX/GX and I815/I820/I830M/I830MP/I840/I845/I850/I860 support" depends on AGP help This option gives you AGP support for the GLX component of the @@ -40,7 +43,7 @@ use GLX or DRI. If unsure, say N. #config AGP_I810 -# bool "Intel I810/I815/I830M (on-board) support" +# tristate "Intel I810/I815/I830M (on-board) support" # depends on AGP # help # This option gives you AGP support for the Xserver on the Intel 810 @@ -48,7 +51,7 @@ # is required to do any useful video modes with these boards. config AGP_VIA - bool "VIA chipset support" + tristate "VIA chipset support" depends on AGP help This option gives you AGP support for the GLX component of the @@ -58,7 +61,7 @@ use GLX or DRI. If unsure, say N. config AGP_AMD - bool "AMD Irongate, 761, and 762 support" + tristate "AMD Irongate, 761, and 762 support" depends on AGP help This option gives you AGP support for the GLX component of the @@ -68,7 +71,7 @@ use GLX or DRI. If unsure, say N. config AGP_SIS - bool "Generic SiS support" + tristate "Generic SiS support" depends on AGP help This option gives you AGP support for the GLX component of the "soon @@ -81,7 +84,7 @@ use GLX or DRI. If unsure, say N. config AGP_ALI - bool "ALI chipset support" + tristate "ALI chipset support" depends on AGP ---help--- This option gives you AGP support for the GLX component of the @@ -99,14 +102,14 @@ use GLX or DRI. If unsure, say N. config AGP_SWORKS - bool "Serverworks LE/HE support" + tristate "Serverworks LE/HE support" depends on AGP help Say Y here to support the Serverworks AGP card. See for product descriptions and images. config AGP_AMD_8151 - bool "AMD 8151 support" + tristate "AMD 8151 support" depends on AGP default GART_IOMMU help @@ -114,16 +117,28 @@ GART on the AMD Athlon64/Opteron ("Hammer") CPUs. config AGP_I460 - bool "Intel 460GX support" + tristate "Intel 460GX support" depends on AGP && IA64 help This option gives you AGP GART support for the Intel 460GX chipset for IA64 processors. config AGP_HP_ZX1 - bool "HP ZX1 AGP support" + tristate "HP ZX1 AGP support" depends on AGP && IA64 help This option gives you AGP GART support for the HP ZX1 chipset for IA64 processors. + +# Put AGP 3.0 entries below here. + +config AGP_I7505 + tristate "Intel 7205/7505 support (AGP 3.0)" + depends on AGP3 + help + This option gives you AGP support for the GLX component of the + XFree86 4.x on Intel I7505 chipsets. + + You should say Y here if you use XFree86 3.3.6 or 4.x and want to + use GLX or DRI. If unsure, say N diff -Nru a/drivers/char/agp/Makefile b/drivers/char/agp/Makefile --- a/drivers/char/agp/Makefile Wed Jan 15 16:57:28 2003 +++ b/drivers/char/agp/Makefile Wed Jan 15 16:57:28 2003 @@ -8,6 +8,7 @@ agpgart-y := backend.o frontend.o generic.o agpgart-objs := $(agpgart-y) obj-$(CONFIG_AGP) += agpgart.o +obj-$(CONFIG_AGP3) += generic-3.0.o obj-$(CONFIG_AGP_INTEL) += intel-agp.o obj-$(CONFIG_AGP_VIA) += via-agp.o @@ -18,4 +19,6 @@ obj-$(CONFIG_AGP_I460) += i460-agp.o obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o obj-$(CONFIG_AGP_AMD_8151) += amd-k8-agp.o + +obj-$(CONFIG_AGP_I7x05) += i7x05-agp.o diff -Nru a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h --- a/drivers/char/agp/agp.h Wed Jan 15 16:57:29 2003 +++ b/drivers/char/agp/agp.h Wed Jan 15 16:57:29 2003 @@ -46,28 +46,6 @@ void agp_generic_resume(void); void agp_free_key(int key); -/* chipset specific init routines. */ -/* -int __init ali_generic_setup (struct pci_dev *pdev); -int __init amd_irongate_setup (struct pci_dev *pdev); -int __init amd_8151_setup (struct pci_dev *pdev); -int __init hp_zx1_setup (struct pci_dev *pdev); -int __init intel_i460_setup (struct pci_dev *pdev); -int __init intel_generic_setup (struct pci_dev *pdev); -int __init intel_i810_setup(struct pci_dev *i810_dev); -int __init intel_815_setup(struct pci_dev *pdev); -int __init intel_i830_setup(struct pci_dev *i830_dev); -int __init intel_820_setup (struct pci_dev *pdev); -int __init intel_830mp_setup (struct pci_dev *pdev); -int __init intel_840_setup (struct pci_dev *pdev); -int __init intel_845_setup (struct pci_dev *pdev); -int __init intel_850_setup (struct pci_dev *pdev); -int __init intel_860_setup (struct pci_dev *pdev); -int __init serverworks_setup (struct pci_dev *pdev); -int __init sis_generic_setup (struct pci_dev *pdev); -int __init via_generic_setup (struct pci_dev *pdev); -*/ - #define PFX "agpgart: " int agp_register_driver (struct pci_dev *dev); @@ -86,7 +64,7 @@ flush_agp_cache(); } #else -static void global_cache_flush(void) +static void __attribute__((unused)) global_cache_flush(void) { flush_agp_cache(); } diff -Nru a/drivers/char/agp/amd-k7-agp.c b/drivers/char/agp/amd-k7-agp.c --- a/drivers/char/agp/amd-k7-agp.c Wed Jan 15 16:57:29 2003 +++ b/drivers/char/agp/amd-k7-agp.c Wed Jan 15 16:57:29 2003 @@ -138,8 +138,8 @@ return retval; } - agp_bridge.gatt_table_real = (u32 *)page_dir.real; - agp_bridge.gatt_table = (u32 *)page_dir.remapped; + agp_bridge.gatt_table_real = (unsigned long *)page_dir.real; + agp_bridge.gatt_table = (unsigned long *)page_dir.remapped; agp_bridge.gatt_bus_addr = virt_to_phys(page_dir.real); /* Get the address for the gart region. @@ -165,8 +165,8 @@ { struct amd_page_map page_dir; - page_dir.real = (u32 *)agp_bridge.gatt_table_real; - page_dir.remapped = (u32 *)agp_bridge.gatt_table; + page_dir.real = (unsigned long *)agp_bridge.gatt_table_real; + page_dir.remapped = (unsigned long *)agp_bridge.gatt_table; amd_free_gatt_pages(); amd_free_page_map(&page_dir); @@ -308,7 +308,7 @@ for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr; cur_gatt = GET_GATT(addr); - cur_gatt[GET_GATT_OFF(addr)] = mem->memory[i]; + cur_gatt[GET_GATT_OFF(addr)] = agp_bridge.mask_memory(mem->memory[i], mem->type); } agp_bridge.tlb_flush(mem); return 0; diff -Nru a/drivers/char/agp/amd-k8-agp.c b/drivers/char/agp/amd-k8-agp.c --- a/drivers/char/agp/amd-k8-agp.c Wed Jan 15 16:57:29 2003 +++ b/drivers/char/agp/amd-k8-agp.c Wed Jan 15 16:57:29 2003 @@ -151,7 +151,7 @@ } -static void inline flush_x86_64_tlb(struct pci_dev *dev) +static void flush_x86_64_tlb(struct pci_dev *dev) { u32 tmp; diff -Nru a/drivers/char/agp/backend.c b/drivers/char/agp/backend.c --- a/drivers/char/agp/backend.c Wed Jan 15 16:57:29 2003 +++ b/drivers/char/agp/backend.c Wed Jan 15 16:57:29 2003 @@ -26,6 +26,7 @@ * TODO: * - Allocate more than order 0 pages to avoid too much linear map splitting. */ + #include #include #include @@ -34,10 +35,14 @@ #include #include #include +#include #include "agp.h" -#define AGPGART_VERSION_MAJOR 1 -#define AGPGART_VERSION_MINOR 0 +/* Due to XFree86 brain-damage, we can't go to 1.0 until they + * fix some real stupidity. It's only by chance we can bump + * past 0.99 at all due to some boolean logic error. */ +#define AGPGART_VERSION_MAJOR 0 +#define AGPGART_VERSION_MINOR 100 struct agp_bridge_data agp_bridge = { .type = NOT_SUPPORTED }; @@ -258,7 +263,7 @@ return 0; } -int __exit agp_unregister_driver(void) +int agp_unregister_driver(void) { agp_bridge.type = NOT_SUPPORTED; pm_unregister_all(agp_power); @@ -269,8 +274,23 @@ return 0; } +int __exit agp_exit(void) +{ + if (agp_count==0) + return -EBUSY; + + return 0; +} + int __init agp_init(void) { + static int already_initialised=0; + + if (already_initialised!=0) + return 0; + + already_initialised = 1; + memset(&agp_bridge, 0, sizeof(struct agp_bridge_data)); agp_bridge.type = NOT_SUPPORTED; @@ -281,11 +301,13 @@ #ifndef CONFIG_GART_IOMMU module_init(agp_init); +module_exit(agp_exit); #endif EXPORT_SYMBOL(agp_backend_acquire); EXPORT_SYMBOL(agp_backend_release); EXPORT_SYMBOL_GPL(agp_register_driver); +EXPORT_SYMBOL_GPL(agp_unregister_driver); MODULE_AUTHOR("Dave Jones "); MODULE_LICENSE("GPL and additional rights"); diff -Nru a/drivers/char/agp/frontend.c b/drivers/char/agp/frontend.c --- a/drivers/char/agp/frontend.c Wed Jan 15 16:57:28 2003 +++ b/drivers/char/agp/frontend.c Wed Jan 15 16:57:28 2003 @@ -1062,9 +1062,9 @@ static struct miscdevice agp_miscdev = { - AGPGART_MINOR, - "agpgart", - &agp_fops + .minor = AGPGART_MINOR, + .name = "agpgart", + .fops = &agp_fops }; int __init agp_frontend_initialize(void) @@ -1079,7 +1079,7 @@ return 0; } -void __exit agp_frontend_cleanup(void) +void agp_frontend_cleanup(void) { misc_deregister(&agp_miscdev); } diff -Nru a/drivers/char/agp/generic-3.0.c b/drivers/char/agp/generic-3.0.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/drivers/char/agp/generic-3.0.c Wed Jan 15 16:57:29 2003 @@ -0,0 +1,556 @@ +#include +#include + + +//#include +//#include +//#include +#include + +#include "agp.h" + +/* Generic AGP 3.0 enabling routines */ + +struct agp_3_0_dev { + struct list_head list; + u8 capndx; + u32 maxbw; + struct pci_dev *dev; +}; + +static int agp_3_0_dev_list_insert(struct list_head *head, struct list_head *new) +{ + struct agp_3_0_dev *cur, *n = list_entry(new, struct agp_3_0_dev, list); + struct list_head *pos; + + list_for_each(pos, head) { + cur = list_entry(pos, struct agp_3_0_dev, list); + if(cur->maxbw > n->maxbw) + break; + } + list_add_tail(new, pos); + + return 0; +} + +static int agp_3_0_dev_list_sort(struct agp_3_0_dev *list, unsigned int ndevs) +{ + struct agp_3_0_dev *cur; + struct pci_dev *dev; + struct list_head *pos, *tmp, *head = &list->list, *start = head->next; + u32 nistat; + + INIT_LIST_HEAD(head); + + for(pos = start; pos != head;) { + cur = list_entry(pos, struct agp_3_0_dev, list); + dev = cur->dev; + + pci_read_config_dword(dev, cur->capndx + 0x0c, &nistat); + cur->maxbw = (nistat >> 16) & 0xff; + + tmp = pos; + pos = pos->next; + agp_3_0_dev_list_insert(head, tmp); + } + return 0; +} + +/* + * Initialize all isochronous transfer parameters for an AGP 3.0 + * node (i.e. a host bridge in combination with the adapters + * lying behind it...) + */ + +static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigned int ndevs) +{ + /* + * Convenience structure to make the calculations clearer + * here. The field names come straight from the AGP 3.0 spec. + */ + struct isoch_data { + u32 maxbw; + u32 n; + u32 y; + u32 l; + u32 rq; + struct agp_3_0_dev *dev; + }; + + struct pci_dev *td = agp_bridge.dev, *dev; + struct list_head *head = &dev_list->list, *pos; + struct agp_3_0_dev *cur; + struct isoch_data *master, target; + unsigned int cdev = 0; + u32 mnistat, tnistat, tstatus, mcmd; + u16 tnicmd, mnicmd; + u8 mcapndx; + u32 tot_bw = 0, tot_n = 0, tot_rq = 0, y_max, rq_isoch, rq_async; + u32 step, rem, rem_isoch, rem_async; + int ret = 0; + + /* + * We'll work with an array of isoch_data's (one for each + * device in dev_list) throughout this function. + */ + if((master = kmalloc(ndevs * sizeof(*master), GFP_KERNEL)) == NULL) { + ret = -ENOMEM; + goto get_out; + } + + /* + * Sort the device list by maxbw. We need to do this because the + * spec suggests that the devices with the smallest requirements + * have their resources allocated first, with all remaining resources + * falling to the device with the largest requirement. + * + * We don't exactly do this, we divide target resources by ndevs + * and split them amongst the AGP 3.0 devices. The remainder of such + * division operations are dropped on the last device, sort of like + * the spec mentions it should be done. + * + * We can't do this sort when we initially construct the dev_list + * because we don't know until this function whether isochronous + * transfers are enabled and consequently whether maxbw will mean + * anything. + */ + if((ret = agp_3_0_dev_list_sort(dev_list, ndevs)) != 0) + goto free_and_exit; + + pci_read_config_dword(td, agp_bridge.capndx + 0x0c, &tnistat); + pci_read_config_dword(td, agp_bridge.capndx + 0x04, &tstatus); + + /* Extract power-on defaults from the target */ + target.maxbw = (tnistat >> 16) & 0xff; + target.n = (tnistat >> 8) & 0xff; + target.y = (tnistat >> 6) & 0x3; + target.l = (tnistat >> 3) & 0x7; + target.rq = (tstatus >> 24) & 0xff; + + y_max = target.y; + + /* + * Extract power-on defaults for each device in dev_list. Along + * the way, calculate the total isochronous bandwidth required + * by these devices and the largest requested payload size. + */ + list_for_each(pos, head) { + cur = list_entry(pos, struct agp_3_0_dev, list); + dev = cur->dev; + + mcapndx = cur->capndx; + + pci_read_config_dword(dev, cur->capndx + 0x0c, &mnistat); + + master[cdev].maxbw = (mnistat >> 16) & 0xff; + master[cdev].n = (mnistat >> 8) & 0xff; + master[cdev].y = (mnistat >> 6) & 0x3; + master[cdev].dev = cur; + + tot_bw += master[cdev].maxbw; + y_max = max(y_max, master[cdev].y); + + cdev++; + } + + /* Check if this configuration has any chance of working */ + if(tot_bw > target.maxbw) { + printk(KERN_ERR PFX "isochronous bandwidth required " + "by AGP 3.0 devices exceeds that which is supported by " + "the AGP 3.0 bridge!\n"); + ret = -ENODEV; + goto free_and_exit; + } + + target.y = y_max; + + /* + * Write the calculated payload size into the target's NICMD + * register. Doing this directly effects the ISOCH_N value + * in the target's NISTAT register, so we need to do this now + * to get an accurate value for ISOCH_N later. + */ + pci_read_config_word(td, agp_bridge.capndx + 0x20, &tnicmd); + tnicmd &= ~(0x3 << 6); + tnicmd |= target.y << 6; + pci_write_config_word(td, agp_bridge.capndx + 0x20, tnicmd); + + /* Reread the target's ISOCH_N */ + pci_read_config_dword(td, agp_bridge.capndx + 0x0c, &tnistat); + target.n = (tnistat >> 8) & 0xff; + + /* Calculate the minimum ISOCH_N needed by each master */ + for(cdev = 0; cdev < ndevs; cdev++) { + master[cdev].y = target.y; + master[cdev].n = master[cdev].maxbw / (master[cdev].y + 1); + + tot_n += master[cdev].n; + } + + /* Exit if the minimal ISOCH_N allocation among the masters is more + * than the target can handle. */ + if(tot_n > target.n) { + printk(KERN_ERR PFX "number of isochronous " + "transactions per period required by AGP 3.0 devices " + "exceeds that which is supported by the AGP 3.0 " + "bridge!\n"); + ret = -ENODEV; + goto free_and_exit; + } + + /* Calculate left over ISOCH_N capability in the target. We'll give + * this to the hungriest device (as per the spec) */ + rem = target.n - tot_n; + + /* + * Calculate the minimum isochronous RQ depth needed by each master. + * Along the way, distribute the extra ISOCH_N capability calculated + * above. + */ + for(cdev = 0; cdev < ndevs; cdev++) { + /* + * This is a little subtle. If ISOCH_Y > 64B, then ISOCH_Y + * byte isochronous writes will be broken into 64B pieces. + * This means we need to budget more RQ depth to account for + * these kind of writes (each isochronous write is actually + * many writes on the AGP bus). + */ + master[cdev].rq = master[cdev].n; + if(master[cdev].y > 0x1) { + master[cdev].rq *= (1 << (master[cdev].y - 1)); + } + + tot_rq += master[cdev].rq; + + if(cdev == ndevs - 1) + master[cdev].n += rem; + } + + /* Figure the number of isochronous and asynchronous RQ slots the + * target is providing. */ + rq_isoch = (target.y > 0x1) ? target.n * (1 << (target.y - 1)) : target.n; + rq_async = target.rq - rq_isoch; + + /* Exit if the minimal RQ needs of the masters exceeds what the target + * can provide. */ + if(tot_rq > rq_isoch) { + printk(KERN_ERR PFX "number of request queue slots " + "required by the isochronous bandwidth requested by " + "AGP 3.0 devices exceeds the number provided by the " + "AGP 3.0 bridge!\n"); + ret = -ENODEV; + goto free_and_exit; + } + + /* Calculate asynchronous RQ capability in the target (per master) as + * well as the total number of leftover isochronous RQ slots. */ + step = rq_async / ndevs; + rem_async = step + (rq_async % ndevs); + rem_isoch = rq_isoch - tot_rq; + + /* Distribute the extra RQ slots calculated above and write our + * isochronous settings out to the actual devices. */ + for(cdev = 0; cdev < ndevs; cdev++) { + cur = master[cdev].dev; + dev = cur->dev; + + mcapndx = cur->capndx; + + master[cdev].rq += (cdev == ndevs - 1) + ? (rem_async + rem_isoch) : step; + + pci_read_config_word(dev, cur->capndx + 0x20, &mnicmd); + pci_read_config_dword(dev, cur->capndx + 0x08, &mcmd); + + mnicmd &= ~(0xff << 8); + mnicmd &= ~(0x3 << 6); + mcmd &= ~(0xff << 24); + + mnicmd |= master[cdev].n << 8; + mnicmd |= master[cdev].y << 6; + mcmd |= master[cdev].rq << 24; + + pci_write_config_dword(dev, cur->capndx + 0x08, mcmd); + pci_write_config_word(dev, cur->capndx + 0x20, mnicmd); + } + +free_and_exit: + kfree(master); + +get_out: + return ret; +} + +/* + * This function basically allocates request queue slots among the + * AGP 3.0 systems in nonisochronous nodes. The algorithm is + * pretty stupid, divide the total number of RQ slots provided by the + * target by ndevs. Distribute this many slots to each AGP 3.0 device, + * giving any left over slots to the last device in dev_list. + */ +static int agp_3_0_nonisochronous_node_enable(struct agp_3_0_dev *dev_list, unsigned int ndevs) +{ + struct agp_3_0_dev *cur; + struct list_head *head = &dev_list->list, *pos; + u32 tstatus, mcmd; + u32 trq, mrq, rem; + unsigned int cdev = 0; + + pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 0x04, &tstatus); + + trq = (tstatus >> 24) & 0xff; + mrq = trq / ndevs; + + rem = mrq + (trq % ndevs); + + for(pos = head->next; cdev < ndevs; cdev++, pos = pos->next) { + cur = list_entry(pos, struct agp_3_0_dev, list); + + pci_read_config_dword(cur->dev, cur->capndx + 0x08, &mcmd); + mcmd &= ~(0xff << 24); + mcmd |= ((cdev == ndevs - 1) ? rem : mrq) << 24; + pci_write_config_dword(cur->dev, cur->capndx + 0x08, mcmd); + } + + return 0; +} + +/* + * Fully configure and enable an AGP 3.0 host bridge and all the devices + * lying behind it. + */ +static int agp_3_0_node_enable(u32 mode, u32 minor) +{ + struct pci_dev *td = agp_bridge.dev, *dev; + u8 bus_num, mcapndx; + u32 isoch, arqsz, cal_cycle, tmp, rate; + u32 tstatus, tcmd, mcmd, mstatus, ncapid; + u32 mmajor, mminor; + u16 mpstat; + struct agp_3_0_dev *dev_list, *cur; + struct list_head *head, *pos; + unsigned int ndevs = 0; + int ret = 0; + + /* + * Allocate a head for our AGP 3.0 device list (multiple AGP 3.0 + * devices are allowed behind a single bridge). + */ + if((dev_list = kmalloc(sizeof(*dev_list), GFP_KERNEL)) == NULL) { + ret = -ENOMEM; + goto get_out; + } + head = &dev_list->list; + INIT_LIST_HEAD(head); + + /* + * Find all the devices on this bridge's secondary bus and add them + * to dev_list. + */ + pci_read_config_byte(td, PCI_SECONDARY_BUS, &bus_num); + pci_for_each_dev(dev) { + if(dev->bus->number == bus_num) { + if((cur = kmalloc(sizeof(*cur), GFP_KERNEL)) == NULL) { + ret = -ENOMEM; + goto free_and_exit; + } + + cur->dev = dev; + + pos = &cur->list; + list_add(pos, head); + ndevs++; + } + } + + /* Extract some power-on defaults from the target */ + pci_read_config_dword(td, agp_bridge.capndx + 0x04, &tstatus); + isoch = (tstatus >> 17) & 0x1; + arqsz = (tstatus >> 13) & 0x7; + cal_cycle = (tstatus >> 10) & 0x7; + rate = tstatus & 0x7; + + /* + * Take an initial pass through the devices lying behind our host + * bridge. Make sure each one is actually an AGP 3.0 device, otherwise + * exit with an error message. Along the way store the AGP 3.0 + * cap_ptr for each device, the minimum supported cal_cycle, and the + * minimum supported data rate. + */ + list_for_each(pos, head) { + cur = list_entry(pos, struct agp_3_0_dev, list); + dev = cur->dev; + + pci_read_config_word(dev, PCI_STATUS, &mpstat); + if((mpstat & PCI_STATUS_CAP_LIST) == 0) + continue; + + pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &mcapndx); + if (mcapndx != 0x00) { + do { + pci_read_config_dword(dev, mcapndx, &ncapid); + if ((ncapid & 0xff) != 0x02) + mcapndx = (ncapid >> 8) & 0xff; + } + while (((ncapid & 0xff) != 0x02) && (mcapndx != 0x00)); + } + + if(mcapndx == 0) { + printk(KERN_ERR PFX "woah! Non-AGP device " + "found on the secondary bus of an AGP 3.0 " + "bridge!\n"); + ret = -ENODEV; + goto free_and_exit; + } + + mmajor = (ncapid >> 20) & 0xf; + mminor = (ncapid >> 16) & 0xf; + + if(mmajor < 3) { + printk(KERN_ERR PFX "woah! AGP 2.0 device " + "found on the secondary bus of an AGP 3.0 " + "bridge operating with AGP 3.0 electricals!\n"); + ret = -ENODEV; + goto free_and_exit; + } + + cur->capndx = mcapndx; + + pci_read_config_dword(dev, cur->capndx + 0x04, &mstatus); + + if(((mstatus >> 3) & 0x1) == 0) { + printk(KERN_ERR PFX "woah! AGP 3.0 device " + "not operating in AGP 3.0 mode found on the " + "secondary bus of an AGP 3.0 bridge operating " + "with AGP 3.0 electricals!\n"); + ret = -ENODEV; + goto free_and_exit; + } + + tmp = (mstatus >> 10) & 0x7; + cal_cycle = min(cal_cycle, tmp); + + /* figure the lesser rate */ + tmp = mstatus & 0x7; + if(tmp < rate) + rate = tmp; + + } + + /* Turn rate into something we can actually write out to AGPCMD */ + switch(rate) { + case 0x1: + case 0x2: + break; + case 0x3: + rate = 0x2; + break; + default: + printk(KERN_ERR PFX "woah! Bogus AGP rate " + "value found advertised behind an AGP 3.0 " + "bridge!\n"); + ret = -ENODEV; + goto free_and_exit; + } + + /* + * Call functions to divide target resources amongst the AGP 3.0 + * masters. This process is dramatically different depending on + * whether isochronous transfers are supported. + */ + if(isoch != 0) { + if((ret = agp_3_0_isochronous_node_enable(dev_list, + ndevs)) != 0) + goto free_and_exit; + } else { + if((ret = agp_3_0_nonisochronous_node_enable(dev_list, + ndevs)) != 0) + goto free_and_exit; + } + + /* + * Set the calculated minimum supported cal_cycle and minimum + * supported transfer rate in the target's AGPCMD register. + * Also set the AGP_ENABLE bit, effectively 'turning on' the + * target (this has to be done _before_ turning on the masters). + */ + pci_read_config_dword(td, agp_bridge.capndx + 0x08, &tcmd); + + tcmd &= ~(0x7 << 10); + tcmd &= ~0x7; + + tcmd |= cal_cycle << 10; + tcmd |= 0x1 << 8; + tcmd |= rate; + + pci_write_config_dword(td, agp_bridge.capndx + 0x08, tcmd); + + /* + * Set the target's advertised arqsz value, the minimum supported + * transfer rate, and the AGP_ENABLE bit in each master's AGPCMD + * register. + */ + list_for_each(pos, head) { + cur = list_entry(pos, struct agp_3_0_dev, list); + dev = cur->dev; + + mcapndx = cur->capndx; + + pci_read_config_dword(dev, cur->capndx + 0x08, &mcmd); + + mcmd &= ~(0x7 << 13); + mcmd &= ~0x7; + + mcmd |= arqsz << 13; + mcmd |= 0x1 << 8; + mcmd |= rate; + + pci_write_config_dword(dev, cur->capndx + 0x08, mcmd); + } + +free_and_exit: + /* Be sure to free the dev_list */ + for(pos = head->next; pos != head;) { + cur = list_entry(pos, struct agp_3_0_dev, list); + + pos = pos->next; + kfree(cur); + } + kfree(dev_list); + +get_out: + return ret; +} + +/* + * Entry point to AGP 3.0 host bridge init. Check to see if we + * have an AGP 3.0 device operating in 3.0 mode. Call + * agp_3_0_node_enable or agp_generic_agp_enable if we don't + * (AGP 3.0 devices are required to operate as AGP 2.0 devices + * when not using 3.0 electricals. + */ +void agp_generic_agp_3_0_enable(u32 mode) +{ + u32 ncapid, major, minor, agp_3_0; + + pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx, &ncapid); + + major = (ncapid >> 20) & 0xf; + minor = (ncapid >> 16) & 0xf; + + printk(KERN_INFO PFX "Found an AGP %d.%d compliant device.\n", + major, minor); + + if(major >= 3) { + pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 0x4, &agp_3_0); + /* + * Check to see if we are operating in 3.0 mode + */ + if((agp_3_0 >> 3) & 0x1) { + agp_3_0_node_enable(mode, minor); + return; + } + } + agp_generic_agp_enable(mode); +} + diff -Nru a/drivers/char/agp/generic.c b/drivers/char/agp/generic.c --- a/drivers/char/agp/generic.c Wed Jan 15 16:57:28 2003 +++ b/drivers/char/agp/generic.c Wed Jan 15 16:57:28 2003 @@ -469,7 +469,7 @@ for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) SetPageReserved(page); - agp_bridge.gatt_table_real = (u32 *) table; + agp_bridge.gatt_table_real = (unsigned long *) table; agp_gatt_table = (void *)table; CACHE_FLUSH(); agp_bridge.gatt_table = ioremap_nocache(virt_to_phys(table), @@ -693,7 +693,23 @@ EXPORT_SYMBOL(agp_free_memory); EXPORT_SYMBOL(agp_allocate_memory); EXPORT_SYMBOL(agp_copy_info); +EXPORT_SYMBOL(agp_create_memory); EXPORT_SYMBOL(agp_bind_memory); EXPORT_SYMBOL(agp_unbind_memory); +EXPORT_SYMBOL(agp_free_key); EXPORT_SYMBOL(agp_enable); +EXPORT_SYMBOL(agp_bridge); + +EXPORT_SYMBOL(agp_generic_alloc_page); +EXPORT_SYMBOL(agp_generic_destroy_page); +EXPORT_SYMBOL(agp_generic_suspend); +EXPORT_SYMBOL(agp_generic_resume); +EXPORT_SYMBOL(agp_generic_agp_enable); +EXPORT_SYMBOL(agp_generic_create_gatt_table); +EXPORT_SYMBOL(agp_generic_free_gatt_table); +EXPORT_SYMBOL(agp_generic_insert_memory); +EXPORT_SYMBOL(agp_generic_remove_memory); +EXPORT_SYMBOL(agp_generic_alloc_by_type); +EXPORT_SYMBOL(agp_generic_free_by_type); +EXPORT_SYMBOL(global_cache_flush); diff -Nru a/drivers/char/agp/hp-agp.c b/drivers/char/agp/hp-agp.c --- a/drivers/char/agp/hp-agp.c Wed Jan 15 16:57:29 2003 +++ b/drivers/char/agp/hp-agp.c Wed Jan 15 16:57:29 2003 @@ -18,8 +18,7 @@ #define HP_ZX1_SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL #define HP_ZX1_PDIR_VALID_BIT 0x8000000000000000UL -#define HP_ZX1_IOVA_TO_PDIR(va) ((va - hp_private.iova_base) >> \ - hp_private.io_tlb_shift) +#define HP_ZX1_IOVA_TO_PDIR(va) ((va - hp_private.iova_base) >> hp_private.io_tlb_shift) static struct aper_size_info_fixed hp_zx1_sizes[] = { @@ -217,8 +216,7 @@ { struct _hp_private *hp = &hp_private; - OUTREG64(hp->registers, HP_ZX1_PCOM, - hp->gart_base | log2(hp->gart_size)); + OUTREG64(hp->registers, HP_ZX1_PCOM, hp->gart_base | log2(hp->gart_size)); INREG64(hp->registers, HP_ZX1_PCOM); } @@ -252,7 +250,7 @@ static int hp_zx1_free_gatt_table(void) { struct _hp_private *hp = &hp_private; - + if (hp->io_pdir_owner) free_pages((unsigned long) hp->io_pdir, get_order(hp->io_pdir_size)); @@ -330,12 +328,7 @@ return HP_ZX1_PDIR_VALID_BIT | addr; } -static unsigned long hp_zx1_unmask_memory(unsigned long addr) -{ - return addr & ~(HP_ZX1_PDIR_VALID_BIT); -} - -int __init hp_zx1_setup (struct pci_dev *pdev) +int __init hp_zx1_setup (struct pci_dev *pdev __attribute__((unused))) { agp_bridge.masks = hp_zx1_masks; agp_bridge.num_of_masks = 1; @@ -347,7 +340,6 @@ agp_bridge.cleanup = hp_zx1_cleanup; agp_bridge.tlb_flush = hp_zx1_tlbflush; agp_bridge.mask_memory = hp_zx1_mask_memory; - agp_bridge.unmask_memory = hp_zx1_unmask_memory; agp_bridge.agp_enable = agp_generic_agp_enable; agp_bridge.cache_flush = global_cache_flush; agp_bridge.create_gatt_table = hp_zx1_create_gatt_table; @@ -377,21 +369,20 @@ return -ENODEV; } - static int agp_hp_probe (struct pci_dev *dev, const struct pci_device_id *ent) { if (agp_find_supported_device(dev) == 0) { agp_register_driver(dev); return 0; } - return -ENODEV; + return -ENODEV; } static struct pci_device_id agp_hp_pci_table[] __initdata = { { .class = (PCI_CLASS_BRIDGE_HOST << 8), .class_mask = ~0, - .vendor_id = PCI_VENDOR_ID_HP, + .vendor = PCI_VENDOR_ID_HP, .device = PCI_DEVICE_ID_HP_ZX1_LBA, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, @@ -421,7 +412,7 @@ static void __exit agp_hp_cleanup(void) { agp_unregister_driver(); - pci_unregister_driver(&agp_pci_driver); + pci_unregister_driver(&agp_hp_pci_driver); } module_init(agp_hp_init); diff -Nru a/drivers/char/agp/i460-agp.c b/drivers/char/agp/i460-agp.c --- a/drivers/char/agp/i460-agp.c Wed Jan 15 16:57:29 2003 +++ b/drivers/char/agp/i460-agp.c Wed Jan 15 16:57:29 2003 @@ -1,47 +1,95 @@ /* - * FIXME: Nothing ever calls this stuff! + * For documentation on the i460 AGP interface, see Chapter 7 (AGP Subsystem) of + * the "Intel 460GTX Chipset Software Developer's Manual": + * http://developer.intel.com/design/itanium/downloads/24870401s.htm + */ +/* + * 460GX support by Chris Ahna + * Clean up & simplification by David Mosberger-Tang */ - #include #include #include #include -#include "agp.h" -/* BIOS configures the chipset so that one of two apbase registers are used */ -static u8 intel_i460_dynamic_apbase = 0x10; +#include "agp.h" -/* 460 supports multiple GART page sizes, so GART pageshift is dynamic */ -static u8 intel_i460_pageshift = 12; -static u32 intel_i460_pagesize; - -/* Keep track of which is larger, chipset or kernel page size. */ -static u32 intel_i460_cpk = 1; - -/* Structure for tracking partial use of 4MB GART pages */ -static u32 **i460_pg_detail = NULL; -static u32 *i460_pg_count = NULL; +/* + * The i460 can operate with large (4MB) pages, but there is no sane way to support this + * within the current kernel/DRM environment, so we disable the relevant code for now. + * See also comments in ia64_alloc_page()... + */ +#define I460_LARGE_IO_PAGES 0 -#define I460_CPAGES_PER_KPAGE (PAGE_SIZE >> intel_i460_pageshift) -#define I460_KPAGES_PER_CPAGE ((1 << intel_i460_pageshift) >> PAGE_SHIFT) +#if I460_LARGE_IO_PAGES +# define I460_IO_PAGE_SHIFT i460.io_page_shift +#else +# define I460_IO_PAGE_SHIFT 12 +#endif +#define I460_IOPAGES_PER_KPAGE (PAGE_SIZE >> I460_IO_PAGE_SHIFT) +#define I460_KPAGES_PER_IOPAGE (1 << (I460_IO_PAGE_SHIFT - PAGE_SHIFT)) #define I460_SRAM_IO_DISABLE (1 << 4) #define I460_BAPBASE_ENABLE (1 << 3) #define I460_AGPSIZ_MASK 0x7 #define I460_4M_PS (1 << 1) -#define log2(x) ffz(~(x)) +/* Control bits for Out-Of-GART coherency and Burst Write Combining */ +#define I460_GXBCTL_OOG (1UL << 0) +#define I460_GXBCTL_BWC (1UL << 2) + +/* + * gatt_table entries are 32-bits wide on the i460; the generic code ought to declare the + * gatt_table and gatt_table_real pointers a "void *"... + */ +#define RD_GATT(index) readl((u32 *) i460.gatt + (index)) +#define WR_GATT(index, val) writel((val), (u32 *) i460.gatt + (index)) +/* + * The 460 spec says we have to read the last location written to make sure that all + * writes have taken effect + */ +#define WR_FLUSH_GATT(index) RD_GATT(index) + +#define log2(x) ffz(~(x)) + +static struct { + void *gatt; /* ioremap'd GATT area */ + + /* i460 supports multiple GART page sizes, so GART pageshift is dynamic: */ + u8 io_page_shift; + + /* BIOS configures chipset to one of 2 possible apbase values: */ + u8 dynamic_apbase; -static inline void intel_i460_read_back (volatile u32 *entry) + /* structure for tracking partial use of 4MB GART pages: */ + struct lp_desc { + unsigned long *alloced_map; /* bitmap of kernel-pages in use */ + int refcount; /* number of kernel pages using the large page */ + u64 paddr; /* physical address of large page */ + } *lp_desc; +} i460; + +static const struct aper_size_info_8 i460_sizes[3] = { /* - * The 460 spec says we have to read the last location written to - * make sure that all writes have taken effect + * The 32GB aperture is only available with a 4M GART page size. Due to the + * dynamic GART page size, we can't figure out page_order or num_entries until + * runtime. */ - *entry; -} + {32768, 0, 0, 4}, + {1024, 0, 0, 2}, + {256, 0, 0, 1} +}; -static int intel_i460_fetch_size(void) +static struct gatt_mask i460_masks[] = +{ + { + .mask = INTEL_I460_GATT_VALID | INTEL_I460_GATT_COHERENT, + .type = 0 + } +}; + +static int i460_fetch_size (void) { int i; u8 temp; @@ -49,8 +97,15 @@ /* Determine the GART page size */ pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &temp); - intel_i460_pageshift = (temp & I460_4M_PS) ? 22 : 12; - intel_i460_pagesize = 1UL << intel_i460_pageshift; + i460.io_page_shift = (temp & I460_4M_PS) ? 22 : 12; + pr_debug("i460_fetch_size: io_page_shift=%d\n", i460.io_page_shift); + + if (i460.io_page_shift != I460_IO_PAGE_SHIFT) { + printk(KERN_ERR PFX + "I/O (GART) page-size %ZuKB doesn't match expected size %ZuKB\n", + 1UL << (i460.io_page_shift - 10), 1UL << (I460_IO_PAGE_SHIFT)); + return 0; + } values = A_SIZE_8(agp_bridge.aperture_sizes); @@ -64,16 +119,16 @@ } /* Make sure we don't try to create an 2 ^ 23 entry GATT */ - if ((intel_i460_pageshift == 0) && ((temp & I460_AGPSIZ_MASK) == 4)) { + if ((i460.io_page_shift == 0) && ((temp & I460_AGPSIZ_MASK) == 4)) { printk(KERN_ERR PFX "We can't have a 32GB aperture with 4KB GART pages\n"); return 0; } /* Determine the proper APBASE register */ if (temp & I460_BAPBASE_ENABLE) - intel_i460_dynamic_apbase = INTEL_I460_BAPBASE; + i460.dynamic_apbase = INTEL_I460_BAPBASE; else - intel_i460_dynamic_apbase = INTEL_I460_APBASE; + i460.dynamic_apbase = INTEL_I460_APBASE; for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { /* @@ -81,7 +136,7 @@ * the define aperture sizes. Take care not to shift off the end of * values[i].size. */ - values[i].num_entries = (values[i].size << 8) >> (intel_i460_pageshift - 12); + values[i].num_entries = (values[i].size << 8) >> (I460_IO_PAGE_SHIFT - 12); values[i].page_order = log2((sizeof(u32)*values[i].num_entries) >> PAGE_SHIFT); } @@ -98,7 +153,7 @@ } /* There isn't anything to do here since 460 has no GART TLB. */ -static void intel_i460_tlb_flush(agp_memory * mem) +static void i460_tlb_flush (agp_memory * mem) { return; } @@ -107,7 +162,7 @@ * This utility function is needed to prevent corruption of the control bits * which are stored along with the aperture size in 460's AGPSIZ register */ -static void intel_i460_write_agpsiz(u8 size_value) +static void i460_write_agpsiz (u8 size_value) { u8 temp; @@ -116,47 +171,39 @@ ((temp & ~I460_AGPSIZ_MASK) | size_value)); } -static void intel_i460_cleanup(void) +static void i460_cleanup (void) { struct aper_size_info_8 *previous_size; previous_size = A_SIZE_8(agp_bridge.previous_size); - intel_i460_write_agpsiz(previous_size->size_value); + i460_write_agpsiz(previous_size->size_value); - if (intel_i460_cpk == 0) { - vfree(i460_pg_detail); - vfree(i460_pg_count); - } + if (I460_IO_PAGE_SHIFT > PAGE_SHIFT) + kfree(i460.lp_desc); } - -/* Control bits for Out-Of-GART coherency and Burst Write Combining */ -#define I460_GXBCTL_OOG (1UL << 0) -#define I460_GXBCTL_BWC (1UL << 2) - -static int intel_i460_configure(void) +static int i460_configure (void) { union { u32 small[2]; u64 large; } temp; + size_t size; u8 scratch; - int i; - struct aper_size_info_8 *current_size; temp.large = 0; current_size = A_SIZE_8(agp_bridge.current_size); - intel_i460_write_agpsiz(current_size->size_value); + i460_write_agpsiz(current_size->size_value); /* * Do the necessary rigmarole to read all eight bytes of APBASE. * This has to be done since the AGP aperture can be above 4GB on * 460 based systems. */ - pci_read_config_dword(agp_bridge.dev, intel_i460_dynamic_apbase, &(temp.small[0])); - pci_read_config_dword(agp_bridge.dev, intel_i460_dynamic_apbase + 4, &(temp.small[1])); + pci_read_config_dword(agp_bridge.dev, i460.dynamic_apbase, &(temp.small[0])); + pci_read_config_dword(agp_bridge.dev, i460.dynamic_apbase + 4, &(temp.small[1])); /* Clear BAR control bits */ agp_bridge.gart_bus_addr = temp.large & ~((1UL << 3) - 1); @@ -166,403 +213,347 @@ (scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC); /* - * Initialize partial allocation trackers if a GART page is bigger than - * a kernel page. + * Initialize partial allocation trackers if a GART page is bigger than a kernel + * page. */ - if (I460_CPAGES_PER_KPAGE >= 1) { - intel_i460_cpk = 1; - } else { - intel_i460_cpk = 0; - - i460_pg_detail = vmalloc(sizeof(*i460_pg_detail) * current_size->num_entries); - i460_pg_count = vmalloc(sizeof(*i460_pg_count) * current_size->num_entries); - - for (i = 0; i < current_size->num_entries; i++) { - i460_pg_count[i] = 0; - i460_pg_detail[i] = NULL; - } + if (I460_IO_PAGE_SHIFT > PAGE_SHIFT) { + size = current_size->num_entries * sizeof(i460.lp_desc[0]); + i460.lp_desc = kmalloc(size, GFP_KERNEL); + if (!i460.lp_desc) + return -ENOMEM; + memset(i460.lp_desc, 0, size); } return 0; } -static int intel_i460_create_gatt_table(void) +static int i460_create_gatt_table (void) { - char *table; - int i; - int page_order; - int num_entries; + int page_order, num_entries, i; void *temp; /* - * Load up the fixed address of the GART SRAMS which hold our - * GATT table. + * Load up the fixed address of the GART SRAMS which hold our GATT table. */ - table = (char *) __va(INTEL_I460_ATTBASE); - temp = agp_bridge.current_size; page_order = A_SIZE_8(temp)->page_order; num_entries = A_SIZE_8(temp)->num_entries; - agp_bridge.gatt_table_real = (u32 *) table; - agp_bridge.gatt_table = ioremap_nocache(virt_to_phys(table), - (PAGE_SIZE * (1 << page_order))); - agp_bridge.gatt_bus_addr = virt_to_phys(agp_bridge.gatt_table_real); - - for (i = 0; i < num_entries; i++) { - agp_bridge.gatt_table[i] = 0; - } + i460.gatt = ioremap(INTEL_I460_ATTBASE, PAGE_SIZE << page_order); - intel_i460_read_back(agp_bridge.gatt_table + i - 1); + /* These are no good, the should be removed from the agp_bridge strucure... */ + agp_bridge.gatt_table_real = NULL; + agp_bridge.gatt_table = NULL; + agp_bridge.gatt_bus_addr = 0; + + for (i = 0; i < num_entries; ++i) + WR_GATT(i, 0); + WR_FLUSH_GATT(i - 1); return 0; } -static int intel_i460_free_gatt_table(void) +static int i460_free_gatt_table (void) { - int num_entries; - int i; + int num_entries, i; void *temp; temp = agp_bridge.current_size; num_entries = A_SIZE_8(temp)->num_entries; - for (i = 0; i < num_entries; i++) { - agp_bridge.gatt_table[i] = 0; - } - - intel_i460_read_back(agp_bridge.gatt_table + i - 1); + for (i = 0; i < num_entries; ++i) + WR_GATT(i, 0); + WR_FLUSH_GATT(num_entries - 1); - iounmap(agp_bridge.gatt_table); + iounmap(i460.gatt); return 0; } -/* These functions are called when PAGE_SIZE exceeds the GART page size */ +/* + * The following functions are called when the I/O (GART) page size is smaller than + * PAGE_SIZE. + */ -static int intel_i460_insert_memory_cpk(agp_memory * mem, off_t pg_start, int type) +static int i460_insert_memory_small_io_page (agp_memory *mem, off_t pg_start, int type) { + unsigned long paddr, io_pg_start, io_page_size; int i, j, k, num_entries; void *temp; - unsigned long paddr; - /* - * The rest of the kernel will compute page offsets in terms of - * PAGE_SIZE. - */ - pg_start = I460_CPAGES_PER_KPAGE * pg_start; + pr_debug("i460_insert_memory_small_io_page(mem=%p, pg_start=%ld, type=%d, paddr0=0x%lx)\n", + mem, pg_start, type, mem->memory[0]); + + io_pg_start = I460_IOPAGES_PER_KPAGE * pg_start; temp = agp_bridge.current_size; num_entries = A_SIZE_8(temp)->num_entries; - if ((pg_start + I460_CPAGES_PER_KPAGE * mem->page_count) > num_entries) { + if ((io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count) > num_entries) { printk(KERN_ERR PFX "Looks like we're out of AGP memory\n"); return -EINVAL; } - j = pg_start; - while (j < (pg_start + I460_CPAGES_PER_KPAGE * mem->page_count)) { - if (!PGE_EMPTY(agp_bridge.gatt_table[j])) { + j = io_pg_start; + while (j < (io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count)) { + if (!PGE_EMPTY(RD_GATT(j))) { + pr_debug("i460_insert_memory_small_io_page: GATT[%d]=0x%x is busy\n", + j, RD_GATT(j)); return -EBUSY; } j++; } -#if 0 - /* not necessary since 460 GART is operated in coherent mode... */ - if (mem->is_flushed == FALSE) { - CACHE_FLUSH(); - mem->is_flushed = TRUE; - } -#endif - - for (i = 0, j = pg_start; i < mem->page_count; i++) { + io_page_size = 1UL << I460_IO_PAGE_SHIFT; + for (i = 0, j = io_pg_start; i < mem->page_count; i++) { paddr = mem->memory[i]; - for (k = 0; k < I460_CPAGES_PER_KPAGE; k++, j++, paddr += intel_i460_pagesize) - agp_bridge.gatt_table[j] = (u32) agp_bridge.mask_memory(paddr, mem->type); + for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size) + WR_GATT(j, agp_bridge.mask_memory(paddr, mem->type)); } - - intel_i460_read_back(agp_bridge.gatt_table + j - 1); + WR_FLUSH_GATT(j - 1); return 0; } -static int intel_i460_remove_memory_cpk(agp_memory * mem, off_t pg_start, int type) +static int i460_remove_memory_small_io_page(agp_memory * mem, off_t pg_start, int type) { int i; - pg_start = I460_CPAGES_PER_KPAGE * pg_start; + pr_debug("i460_remove_memory_small_io_page(mem=%p, pg_start=%ld, type=%d)\n", + mem, pg_start, type); - for (i = pg_start; i < (pg_start + I460_CPAGES_PER_KPAGE * mem->page_count); i++) - agp_bridge.gatt_table[i] = 0; + pg_start = I460_IOPAGES_PER_KPAGE * pg_start; - intel_i460_read_back(agp_bridge.gatt_table + i - 1); + for (i = pg_start; i < (pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count); i++) + WR_GATT(i, 0); + WR_FLUSH_GATT(i - 1); return 0; } +#if I460_LARGE_IO_PAGES + /* - * These functions are called when the GART page size exceeds PAGE_SIZE. + * These functions are called when the I/O (GART) page size exceeds PAGE_SIZE. * - * This situation is interesting since AGP memory allocations that are - * smaller than a single GART page are possible. The structures i460_pg_count - * and i460_pg_detail track partial allocation of the large GART pages to - * work around this issue. + * This situation is interesting since AGP memory allocations that are smaller than a + * single GART page are possible. The i460.lp_desc array tracks partial allocation of the + * large GART pages to work around this issue. * - * i460_pg_count[pg_num] tracks the number of kernel pages in use within - * GART page pg_num. i460_pg_detail[pg_num] is an array containing a - * psuedo-GART entry for each of the aforementioned kernel pages. The whole - * of i460_pg_detail is equivalent to a giant GATT with page size equal to - * that of the kernel. + * i460.lp_desc[pg_num].refcount tracks the number of kernel pages in use within GART page + * pg_num. i460.lp_desc[pg_num].paddr is the physical address of the large page and + * i460.lp_desc[pg_num].alloced_map is a bitmap of kernel pages that are in use (allocated). */ -static void *intel_i460_alloc_large_page(int pg_num) +static int i460_alloc_large_page (struct lp_desc *lp) { - int i; - void *bp, *bp_end; - struct page *page; - - i460_pg_detail[pg_num] = (void *) vmalloc(sizeof(u32) * I460_KPAGES_PER_CPAGE); - if (i460_pg_detail[pg_num] == NULL) { - printk(KERN_ERR PFX "Out of memory, we're in trouble...\n"); - return NULL; - } - - for (i = 0; i < I460_KPAGES_PER_CPAGE; i++) - i460_pg_detail[pg_num][i] = 0; + unsigned long order = I460_IO_PAGE_SHIFT - PAGE_SHIFT; + size_t map_size; + void *lpage; - bp = (void *) __get_free_pages(GFP_KERNEL, intel_i460_pageshift - PAGE_SHIFT); - if (bp == NULL) { + lpage = (void *) __get_free_pages(GFP_KERNEL, order); + if (!lpage) { printk(KERN_ERR PFX "Couldn't alloc 4M GART page...\n"); - return NULL; + return -ENOMEM; } - bp_end = bp + ((PAGE_SIZE * (1 << (intel_i460_pageshift - PAGE_SHIFT))) - 1); - - for (page = virt_to_page(bp); page <= virt_to_page(bp_end); page++) { - atomic_inc(&agp_bridge.current_memory_agp); + map_size = ((I460_KPAGES_PER_IOPAGE + BITS_PER_LONG - 1) & -BITS_PER_LONG)/8; + lp->alloced_map = kmalloc(map_size, GFP_KERNEL); + if (!lp->alloced_map) { + free_pages((unsigned long) lpage, order); + printk(KERN_ERR PFX "Out of memory, we're in trouble...\n"); + return -ENOMEM; } - return bp; + memset(lp->alloced_map, 0, map_size); + + lp->paddr = virt_to_phys(lpage); + lp->refcount = 0; + atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge.current_memory_agp); + return 0; } -static void intel_i460_free_large_page(int pg_num, unsigned long addr) +static void i460_free_large_page (struct lp_desc *lp) { - struct page *page; - void *bp, *bp_end; - - bp = (void *) __va(addr); - bp_end = bp + (PAGE_SIZE * (1 << (intel_i460_pageshift - PAGE_SHIFT))); + kfree(lp->alloced_map); + lp->alloced_map = NULL; - vfree(i460_pg_detail[pg_num]); - i460_pg_detail[pg_num] = NULL; - - for (page = virt_to_page(bp); page < virt_to_page(bp_end); page++) { - atomic_dec(&agp_bridge.current_memory_agp); - } - - free_pages((unsigned long) bp, intel_i460_pageshift - PAGE_SHIFT); + free_pages((unsigned long) phys_to_virt(lp->paddr), I460_IO_PAGE_SHIFT - PAGE_SHIFT); + atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge.current_memory_agp); } -static int intel_i460_insert_memory_kpc(agp_memory * mem, off_t pg_start, int type) +static int i460_insert_memory_large_io_page (agp_memory * mem, off_t pg_start, int type) { - int i, pg, start_pg, end_pg, start_offset, end_offset, idx; - int num_entries; + int i, start_offset, end_offset, idx, pg, num_entries; + struct lp_desc *start, *end, *lp; void *temp; - unsigned long paddr; temp = agp_bridge.current_size; num_entries = A_SIZE_8(temp)->num_entries; /* Figure out what pg_start means in terms of our large GART pages */ - start_pg = pg_start / I460_KPAGES_PER_CPAGE; - start_offset = pg_start % I460_KPAGES_PER_CPAGE; - end_pg = (pg_start + mem->page_count - 1) / I460_KPAGES_PER_CPAGE; - end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_CPAGE; + start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE]; + end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE]; + start_offset = pg_start % I460_KPAGES_PER_IOPAGE; + end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE; - if (end_pg > num_entries) { + if (end > i460.lp_desc + num_entries) { printk(KERN_ERR PFX "Looks like we're out of AGP memory\n"); return -EINVAL; } /* Check if the requested region of the aperture is free */ - for (pg = start_pg; pg <= end_pg; pg++) { - /* Allocate new GART pages if necessary */ - if (i460_pg_detail[pg] == NULL) { - temp = intel_i460_alloc_large_page(pg); - if (temp == NULL) - return -ENOMEM; - agp_bridge.gatt_table[pg] = agp_bridge.mask_memory((unsigned long) temp, - 0); - intel_i460_read_back(agp_bridge.gatt_table + pg); - } + for (lp = start; lp <= end; ++lp) { + if (!lp->alloced_map) + continue; /* OK, the entire large page is available... */ - for (idx = ((pg == start_pg) ? start_offset : 0); - idx < ((pg == end_pg) ? (end_offset + 1) : I460_KPAGES_PER_CPAGE); + for (idx = ((lp == start) ? start_offset : 0); + idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE); idx++) { - if (i460_pg_detail[pg][idx] != 0) + if (test_bit(idx, lp->alloced_map)) return -EBUSY; } } -#if 0 - /* not necessary since 460 GART is operated in coherent mode... */ - if (mem->is_flushed == FALSE) { - CACHE_FLUSH(); - mem->is_flushed = TRUE; - } -#endif + for (lp = start, i = 0; lp <= end; ++lp) { + if (!lp->alloced_map) { + /* Allocate new GART pages... */ + if (i460_alloc_large_page(lp) < 0) + return -ENOMEM; + pg = lp - i460.lp_desc; + WR_GATT(pg, agp_bridge.mask_memory(lp->paddr, 0)); + WR_FLUSH_GATT(pg); + } - for (pg = start_pg, i = 0; pg <= end_pg; pg++) { - paddr = agp_bridge.unmask_memory(agp_bridge.gatt_table[pg]); - for (idx = ((pg == start_pg) ? start_offset : 0); - idx < ((pg == end_pg) ? (end_offset + 1) : I460_KPAGES_PER_CPAGE); + for (idx = ((lp == start) ? start_offset : 0); + idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE); idx++, i++) { - mem->memory[i] = paddr + (idx * PAGE_SIZE); - i460_pg_detail[pg][idx] = agp_bridge.mask_memory(mem->memory[i], - mem->type); - i460_pg_count[pg]++; + mem->memory[i] = lp->paddr + idx*PAGE_SIZE; + __set_bit(idx, lp->alloced_map); + ++lp->refcount; } } - return 0; } -static int intel_i460_remove_memory_kpc(agp_memory * mem, off_t pg_start, int type) +static int i460_remove_memory_large_io_page (agp_memory * mem, off_t pg_start, int type) { - int i, pg, start_pg, end_pg, start_offset, end_offset, idx; - int num_entries; + int i, pg, start_offset, end_offset, idx, num_entries; + struct lp_desc *start, *end, *lp; void *temp; - unsigned long paddr; temp = agp_bridge.current_size; num_entries = A_SIZE_8(temp)->num_entries; /* Figure out what pg_start means in terms of our large GART pages */ - start_pg = pg_start / I460_KPAGES_PER_CPAGE; - start_offset = pg_start % I460_KPAGES_PER_CPAGE; - end_pg = (pg_start + mem->page_count - 1) / I460_KPAGES_PER_CPAGE; - end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_CPAGE; - - for (i = 0, pg = start_pg; pg <= end_pg; pg++) { - for (idx = ((pg == start_pg) ? start_offset : 0); - idx < ((pg == end_pg) ? (end_offset + 1) : I460_KPAGES_PER_CPAGE); - idx++, i++) + start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE]; + end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE]; + start_offset = pg_start % I460_KPAGES_PER_IOPAGE; + end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE; + + for (i = 0, lp = start; lp <= end; ++lp) { + for (idx = ((lp == start) ? start_offset : 0); + idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE); + idx++, i++) { mem->memory[i] = 0; - i460_pg_detail[pg][idx] = 0; - i460_pg_count[pg]--; + __clear_bit(idx, lp->alloced_map); + --lp->refcount; } /* Free GART pages if they are unused */ - if (i460_pg_count[pg] == 0) { - paddr = agp_bridge.unmask_memory(agp_bridge.gatt_table[pg]); - agp_bridge.gatt_table[pg] = agp_bridge.scratch_page; - intel_i460_read_back(agp_bridge.gatt_table + pg); - intel_i460_free_large_page(pg, paddr); + if (lp->refcount == 0) { + pg = lp - i460.lp_desc; + WR_GATT(pg, 0); + WR_FLUSH_GATT(pg); + i460_free_large_page(lp); } } return 0; } -/* Dummy routines to call the approriate {cpk,kpc} function */ +/* Wrapper routines to call the approriate {small_io_page,large_io_page} function */ -static int intel_i460_insert_memory(agp_memory * mem, off_t pg_start, int type) +static int i460_insert_memory (agp_memory * mem, off_t pg_start, int type) { - if (intel_i460_cpk) - return intel_i460_insert_memory_cpk(mem, pg_start, type); + if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) + return i460_insert_memory_small_io_page(mem, pg_start, type); else - return intel_i460_insert_memory_kpc(mem, pg_start, type); + return i460_insert_memory_large_io_page(mem, pg_start, type); } -static int intel_i460_remove_memory(agp_memory * mem, off_t pg_start, int type) +static int i460_remove_memory (agp_memory * mem, off_t pg_start, int type) { - if (intel_i460_cpk) - return intel_i460_remove_memory_cpk(mem, pg_start, type); + if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) + return i460_remove_memory_small_io_page(mem, pg_start, type); else - return intel_i460_remove_memory_kpc(mem, pg_start, type); + return i460_remove_memory_large_io_page(mem, pg_start, type); } /* - * If the kernel page size is smaller that the chipset page size, we don't - * want to allocate memory until we know where it is to be bound in the - * aperture (a multi-kernel-page alloc might fit inside of an already - * allocated GART page). Consequently, don't allocate or free anything - * if i460_cpk (meaning chipset pages per kernel page) isn't set. + * If the I/O (GART) page size is bigger than the kernel page size, we don't want to + * allocate memory until we know where it is to be bound in the aperture (a + * multi-kernel-page alloc might fit inside of an already allocated GART page). * - * Let's just hope nobody counts on the allocated AGP memory being there - * before bind time (I don't think current drivers do)... + * Let's just hope nobody counts on the allocated AGP memory being there before bind time + * (I don't think current drivers do)... */ -static void * intel_i460_alloc_page(void) +static void *i460_alloc_page (void) { - if (intel_i460_cpk) - return agp_generic_alloc_page(); + void *page; - /* Returning NULL would cause problems */ - /* AK: really dubious code. */ - return (void *)~0UL; + if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) + page = agp_generic_alloc_page(); + else + /* Returning NULL would cause problems */ + /* AK: really dubious code. */ + page = (void *)~0UL; + return page; } -static void intel_i460_destroy_page(void *page) +static void i460_destroy_page (void *page) { - if (intel_i460_cpk) + if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) agp_generic_destroy_page(page); } -static struct gatt_mask intel_i460_masks[] = -{ - { - .mask = INTEL_I460_GATT_VALID | INTEL_I460_GATT_COHERENT, - .type = 0 - } -}; +#endif /* I460_LARGE_IO_PAGES */ -static unsigned long intel_i460_mask_memory(unsigned long addr, int type) +static unsigned long i460_mask_memory (unsigned long addr, int type) { /* Make sure the returned address is a valid GATT entry */ return (agp_bridge.masks[0].mask - | (((addr & ~((1 << intel_i460_pageshift) - 1)) & 0xffffff000) >> 12)); + | (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xffffff000) >> 12)); } -static unsigned long intel_i460_unmask_memory(unsigned long addr) -{ - /* Turn a GATT entry into a physical address */ - return ((addr & 0xffffff) << 12); -} - -static struct aper_size_info_8 intel_i460_sizes[3] = -{ - /* - * The 32GB aperture is only available with a 4M GART page size. - * Due to the dynamic GART page size, we can't figure out page_order - * or num_entries until runtime. - */ - {32768, 0, 0, 4}, - {1024, 0, 0, 2}, - {256, 0, 0, 1} -}; - int __init intel_i460_setup (struct pci_dev *pdev __attribute__((unused))) { - agp_bridge.masks = intel_i460_masks; - agp_bridge.aperture_sizes = (void *) intel_i460_sizes; + agp_bridge.num_of_masks = 1; + agp_bridge.masks = i460_masks; + agp_bridge.aperture_sizes = (void *) i460_sizes; agp_bridge.size_type = U8_APER_SIZE; agp_bridge.num_aperture_sizes = 3; agp_bridge.dev_private_data = NULL; agp_bridge.needs_scratch_page = FALSE; - agp_bridge.configure = intel_i460_configure; - agp_bridge.fetch_size = intel_i460_fetch_size; - agp_bridge.cleanup = intel_i460_cleanup; - agp_bridge.tlb_flush = intel_i460_tlb_flush; - agp_bridge.mask_memory = intel_i460_mask_memory; - agp_bridge.unmask_memory = intel_i460_unmask_memory; + agp_bridge.configure = i460_configure; + agp_bridge.fetch_size = i460_fetch_size; + agp_bridge.cleanup = i460_cleanup; + agp_bridge.tlb_flush = i460_tlb_flush; + agp_bridge.mask_memory = i460_mask_memory; agp_bridge.agp_enable = agp_generic_agp_enable; agp_bridge.cache_flush = global_cache_flush; - agp_bridge.create_gatt_table = intel_i460_create_gatt_table; - agp_bridge.free_gatt_table = intel_i460_free_gatt_table; - agp_bridge.insert_memory = intel_i460_insert_memory; - agp_bridge.remove_memory = intel_i460_remove_memory; + agp_bridge.create_gatt_table = i460_create_gatt_table; + agp_bridge.free_gatt_table = i460_free_gatt_table; +#if I460_LARGE_IO_PAGES + agp_bridge.insert_memory = i460_insert_memory; + agp_bridge.remove_memory = i460_remove_memory; + agp_bridge.agp_alloc_page = i460_alloc_page; + agp_bridge.agp_destroy_page = i460_destroy_page; +#else + agp_bridge.insert_memory = i460_insert_memory_small_io_page; + agp_bridge.remove_memory = i460_remove_memory_small_io_page; + agp_bridge.agp_alloc_page = agp_generic_alloc_page; + agp_bridge.agp_destroy_page = agp_generic_destroy_page; +#endif agp_bridge.alloc_by_type = agp_generic_alloc_by_type; agp_bridge.free_by_type = agp_generic_free_by_type; - agp_bridge.agp_alloc_page = intel_i460_alloc_page; - agp_bridge.agp_destroy_page = intel_i460_destroy_page; agp_bridge.suspend = agp_generic_suspend; agp_bridge.resume = agp_generic_resume; agp_bridge.cant_use_aperture = 1; @@ -584,7 +575,7 @@ .class = (PCI_CLASS_BRIDGE_HOST << 8), .class_mask = ~0, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_460GX, + .device = PCI_DEVICE_ID_INTEL_84460GX, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, }, @@ -596,7 +587,7 @@ static struct pci_driver agp_i460_pci_driver = { .name = "agpgart-intel-i460", .id_table = agp_i460_pci_table, - .probe = agp_i460_probe, + .probe = agp_intel_i460_probe, }; static int __init agp_i460_init(void) @@ -619,6 +610,5 @@ module_init(agp_i460_init); module_exit(agp_i460_cleanup); -MODULE_AUTHOR("Bjorn Helgaas "); +MODULE_AUTHOR("Chris Ahna "); MODULE_LICENSE("GPL and additional rights"); - diff -Nru a/drivers/char/agp/i7x05-agp.c b/drivers/char/agp/i7x05-agp.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/drivers/char/agp/i7x05-agp.c Wed Jan 15 16:57:29 2003 @@ -0,0 +1,227 @@ +#include +#include +#include +#include +#include "agp.h" + +static int intel_7505_fetch_size(void) +{ + int i; + u16 tmp; + aper_size_info_16 *values; + + /* + * For AGP 3.0 APSIZE is now 16 bits + */ + pci_read_config_word (agp_bridge.dev, INTEL_I7505_APSIZE, &tmp); + tmp = (tmp & 0xfff); + + values = A_SIZE_16(agp_bridge.aperture_sizes); + + for (i=0; i < agp_bridge.num_aperture_sizes; i++) { + if (tmp == values[i].size_value) { + agp_bridge.previous_size = agp_bridge.current_size = + (void *)(values + i); + agp_bridge.aperture_size_idx = i; + return values[i].size; + } + } + return 0; +} + + +static void intel_7505_tlbflush(agp_memory *mem) +{ + u32 temp; + pci_read_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, &temp); + pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, temp & ~(1 << 7)); + pci_read_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, &temp); + pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, temp | (1 << 7)); +} + +static void intel_7505_cleanup(void) +{ + aper_size_info_16 *previous_size; + + previous_size = A_SIZE_16(agp_bridge.previous_size); + pci_write_config_byte(agp_bridge.dev, INTEL_I7505_APSIZE, + previous_size->size_value); +} + + +static int intel_7505_configure(void) +{ + u32 temp; + aper_size_info_16 *current_size; + + current_size = A_SIZE_16(agp_bridge.current_size); + + /* aperture size */ + pci_write_config_word(agp_bridge.dev, INTEL_I7505_APSIZE, + current_size->size_value); + + /* address to map to */ + pci_read_config_dword(agp_bridge.dev, INTEL_I7505_NAPBASELO, &temp); + agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); + + /* attbase */ + pci_write_config_dword(agp_bridge.dev, INTEL_I7505_ATTBASE, + agp_bridge.gatt_bus_addr); + + /* agpctrl */ + pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, 0x0000); + + /* clear error registers */ + pci_write_config_byte(agp_bridge.dev, INTEL_I7505_ERRSTS, 0xff); + return 0; +} + +static aper_size_info_16 intel_7505_sizes[7] = +{ + {256, 65536, 6, 0xf00}, + {128, 32768, 5, 0xf20}, + {64, 16384, 4, 0xf30}, + {32, 8192, 3, 0xf38}, + {16, 4096, 2, 0xf3c}, + {8, 2048, 1, 0xf3e}, + {4, 1024, 0, 0xf3f} +}; + + +static int __init intel_7505_setup (struct pci_dev *pdev) +{ + agp_bridge.masks = intel_generic_masks; + agp_bridge.num_of_masks = 1; + agp_bridge.aperture_sizes = (void *) intel_7505_sizes; + agp_bridge.size_type = U16_APER_SIZE; + agp_bridge.num_aperture_sizes = 7; + agp_bridge.dev_private_data = NULL; + agp_bridge.needs_scratch_page = FALSE; + agp_bridge.configure = intel_7505_configure; + agp_bridge.fetch_size = intel_7505_fetch_size; + agp_bridge.cleanup = intel_7505_cleanup; + agp_bridge.tlb_flush = intel_7505_tlbflush; + agp_bridge.mask_memory = intel_mask_memory; + agp_bridge.agp_enable = agp_generic_agp_3_0_enable; + agp_bridge.cache_flush = global_cache_flush; + agp_bridge.create_gatt_table = agp_generic_create_gatt_table; + agp_bridge.free_gatt_table = agp_generic_free_gatt_table; + agp_bridge.insert_memory = agp_generic_insert_memory; + agp_bridge.remove_memory = agp_generic_remove_memory; + agp_bridge.alloc_by_type = agp_generic_alloc_by_type; + agp_bridge.free_by_type = agp_generic_free_by_type; + agp_bridge.agp_alloc_page = agp_generic_alloc_page; + agp_bridge.agp_destroy_page = agp_generic_destroy_page; + agp_bridge.suspend = agp_generic_suspend; + agp_bridge.resume = agp_generic_resume; + agp_bridge.cant_use_aperture = 0; + return 0; +} + +struct agp_device_ids i7x05_agp_device_ids[] __initdata = +{ + { + .device_id = PCI_DEVICE_ID_INTEL_7505_0, + .chipset = INTEL_I7505, + .chipset_name = "i7505", + }, + { + .device_id = PCI_DEVICE_ID_INTEL_7205_0, + .chipset = INTEL_I7505, + .chipset_name = "i7205", + }, + { }, /* dummy final entry, always present */ +}; + +/* scan table above for supported devices */ +static int __init agp_lookup_host_bridge (struct pci_dev *pdev) +{ + int j=0; + struct agp_device_ids *devs; + + devs = i7x05_agp_device_ids; + + while (devs[j].chipset_name != NULL) { + if (pdev->device == devs[j].device_id) { + printk (KERN_INFO PFX "Detected Intel %s chipset\n", + devs[j].chipset_name); + agp_bridge.type = devs[j].chipset; + + if (devs[j].chipset_setup != NULL) + return devs[j].chipset_setup(pdev); + else + return intel_7505_setup(pdev); + } + j++; + } + + printk(KERN_ERR PFX "Unsupported Intel chipset (device id: %04x),", + pdev->device); + return -ENODEV; +} + + +static int __init agp_find_supported_device(struct pci_dev *dev) +{ + agp_bridge.dev = dev; + + if (pci_find_capability(dev, PCI_CAP_ID_AGP)==0) + return -ENODEV; + + /* probe for known chipsets */ + return agp_lookup_host_bridge(dev); +} + + +static int agp_i7x05_probe (struct pci_dev *dev, const struct pci_device_id *ent) +{ + if (agp_find_supported_device(dev) == 0) { + agp_register_driver(dev); + return 0; + } + return -ENODEV; +} + +static struct pci_device_id agp_i7x05_pci_table[] __initdata = { + { + .class = (PCI_CLASS_BRIDGE_HOST << 8), + .class_mask = ~0, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_ANY_ID, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + }, + { } +}; + +MODULE_DEVICE_TABLE(pci, agp_i7x05_pci_table); + +static struct pci_driver agp_i7x05_pci_driver = { + .name = "agpgart-i7x05", + .id_table = agp_i7x05_pci_table, + .probe = agp_i7x05_probe, +}; + +int __init agp_i7x05_init(void) +{ + int ret_val; + + ret_val = pci_module_init(&agp_i7x05_pci_driver); + if (ret_val) + agp_bridge.type = NOT_SUPPORTED; + + return ret_val; +} + +static void __exit agp_i7x05_cleanup(void) +{ + agp_unregister_driver(); + pci_unregister_driver(&agp_i7x05_pci_driver); +} + +module_init(agp_i7x05_init); +module_exit(agp_i7x05_cleanup); + +MODULE_AUTHOR("Matthew E Tolentino "); +MODULE_LICENSE("GPL and additional rights"); + diff -Nru a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c --- a/drivers/char/agp/intel-agp.c Wed Jan 15 16:57:29 2003 +++ b/drivers/char/agp/intel-agp.c Wed Jan 15 16:57:29 2003 @@ -1473,6 +1473,11 @@ static int __init agp_intel_init(void) { int ret_val; + static int agp_initialised=0; + + if (agp_initialised==1) + return 0; + agp_initialised=1; ret_val = pci_module_init(&agp_intel_pci_driver); if (ret_val) diff -Nru a/drivers/char/agp/sworks-agp.c b/drivers/char/agp/sworks-agp.c --- a/drivers/char/agp/sworks-agp.c Wed Jan 15 16:57:29 2003 +++ b/drivers/char/agp/sworks-agp.c Wed Jan 15 16:57:29 2003 @@ -383,7 +383,7 @@ for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr; cur_gatt = SVRWRKS_GET_GATT(addr); - cur_gatt[GET_GATT_OFF(addr)] = mem->memory[i]; + cur_gatt[GET_GATT_OFF(addr)] = agp_bridge.mask_memory(mem->memory[i], mem->type); } agp_bridge.tlb_flush(mem); return 0; diff -Nru a/drivers/char/drm/drmP.h b/drivers/char/drm/drmP.h --- a/drivers/char/drm/drmP.h Wed Jan 15 16:57:29 2003 +++ b/drivers/char/drm/drmP.h Wed Jan 15 16:57:29 2003 @@ -230,16 +230,16 @@ if (len > DRM_PROC_LIMIT) { ret; *eof = 1; return len - offset; } /* Mapping helper macros */ -#define DRM_IOREMAP(map) \ - (map)->handle = DRM(ioremap)( (map)->offset, (map)->size ) +#define DRM_IOREMAP(map, dev) \ + (map)->handle = DRM(ioremap)( (map)->offset, (map)->size, (dev) ) -#define DRM_IOREMAP_NOCACHE(map) \ - (map)->handle = DRM(ioremap_nocache)((map)->offset, (map)->size) +#define DRM_IOREMAP_NOCACHE(map, dev) \ + (map)->handle = DRM(ioremap_nocache)((map)->offset, (map)->size, (dev)) -#define DRM_IOREMAPFREE(map) \ - do { \ - if ( (map)->handle && (map)->size ) \ - DRM(ioremapfree)( (map)->handle, (map)->size ); \ +#define DRM_IOREMAPFREE(map, dev) \ + do { \ + if ( (map)->handle && (map)->size ) \ + DRM(ioremapfree)( (map)->handle, (map)->size, (dev) ); \ } while (0) #define DRM_FIND_MAP(_map, _o) \ @@ -681,9 +681,10 @@ extern unsigned long DRM(alloc_pages)(int order, int area); extern void DRM(free_pages)(unsigned long address, int order, int area); -extern void *DRM(ioremap)(unsigned long offset, unsigned long size); -extern void *DRM(ioremap_nocache)(unsigned long offset, unsigned long size); -extern void DRM(ioremapfree)(void *pt, unsigned long size); +extern void *DRM(ioremap)(unsigned long offset, unsigned long size, drm_device_t *dev); +extern void *DRM(ioremap_nocache)(unsigned long offset, unsigned long size, + drm_device_t *dev); +extern void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev); #if __REALLY_HAVE_AGP extern agp_memory *DRM(alloc_agp)(int pages, u32 type); diff -Nru a/drivers/char/drm/drm_bufs.h b/drivers/char/drm/drm_bufs.h --- a/drivers/char/drm/drm_bufs.h Wed Jan 15 16:57:28 2003 +++ b/drivers/char/drm/drm_bufs.h Wed Jan 15 16:57:28 2003 @@ -107,7 +107,7 @@ switch ( map->type ) { case _DRM_REGISTERS: case _DRM_FRAME_BUFFER: -#if !defined(__sparc__) && !defined(__alpha__) +#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) if ( map->offset + map->size < map->offset || map->offset < virt_to_phys(high_memory) ) { DRM(free)( map, sizeof(*map), DRM_MEM_MAPS ); @@ -124,7 +124,7 @@ MTRR_TYPE_WRCOMB, 1 ); } #endif - map->handle = DRM(ioremap)( map->offset, map->size ); + map->handle = DRM(ioremap)( map->offset, map->size, dev ); break; case _DRM_SHM: @@ -246,7 +246,7 @@ DRM_DEBUG("mtrr_del = %d\n", retcode); } #endif - DRM(ioremapfree)(map->handle, map->size); + DRM(ioremapfree)(map->handle, map->size, dev); break; case _DRM_SHM: vfree(map->handle); diff -Nru a/drivers/char/drm/drm_drv.h b/drivers/char/drm/drm_drv.h --- a/drivers/char/drm/drm_drv.h Wed Jan 15 16:57:29 2003 +++ b/drivers/char/drm/drm_drv.h Wed Jan 15 16:57:29 2003 @@ -443,7 +443,7 @@ DRM_DEBUG( "mtrr_del=%d\n", retcode ); } #endif - DRM(ioremapfree)( map->handle, map->size ); + DRM(ioremapfree)( map->handle, map->size, dev ); break; case _DRM_SHM: vfree(map->handle); diff -Nru a/drivers/char/drm/drm_memory.h b/drivers/char/drm/drm_memory.h --- a/drivers/char/drm/drm_memory.h Wed Jan 15 16:57:28 2003 +++ b/drivers/char/drm/drm_memory.h Wed Jan 15 16:57:28 2003 @@ -33,6 +33,10 @@ #include #include "drmP.h" #include +#include + +#include +#include typedef struct drm_mem_stats { const char *name; @@ -291,17 +295,122 @@ } } -void *DRM(ioremap)(unsigned long offset, unsigned long size) +#if __REALLY_HAVE_AGP + +/* + * Find the drm_map that covers the range [offset, offset+size). + */ +static inline drm_map_t * +drm_lookup_map (unsigned long offset, unsigned long size, drm_device_t *dev) { + struct list_head *list; + drm_map_list_t *r_list; + drm_map_t *map; + + list_for_each(list, &dev->maplist->head) { + r_list = (drm_map_list_t *) list; + map = r_list->map; + if (!map) + continue; + if (map->offset <= offset && (offset + size) <= (map->offset + map->size)) + return map; + } + return NULL; +} + +static inline void * +agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev) +{ + unsigned long *phys_addr_map, i, num_pages = PAGE_ALIGN(size) / PAGE_SIZE; + struct page **page_map, **page_map_ptr; + struct drm_agp_mem *agpmem; + struct vm_struct *area; + + + size = PAGE_ALIGN(size); + + for (agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) + if (agpmem->bound <= offset + && (agpmem->bound + (agpmem->pages << PAGE_SHIFT)) >= (offset + size)) + break; + if (!agpmem) + return NULL; + + /* + * OK, we're mapping AGP space on a chipset/platform on which memory accesses by + * the CPU do not get remapped by the GART. We fix this by using the kernel's + * page-table instead (that's probably faster anyhow...). + */ + area = get_vm_area(size, VM_IOREMAP); + if (!area) + return NULL; + + flush_cache_all(); + + /* note: use vmalloc() because num_pages could be large... */ + page_map = vmalloc(num_pages * sizeof(struct page *)); + if (!page_map) + return NULL; + + phys_addr_map = agpmem->memory->memory + (offset - agpmem->bound) / PAGE_SIZE; + for (i = 0; i < num_pages; ++i) + page_map[i] = pfn_to_page(phys_addr_map[i] >> PAGE_SHIFT); + page_map_ptr = page_map; + if (map_vm_area(area, PAGE_AGP, &page_map_ptr) < 0) { + vunmap(area->addr); + vfree(page_map); + return NULL; + } + vfree(page_map); + + flush_tlb_kernel_range(area->addr, area->addr + size); + return area->addr; +} + +static inline unsigned long +drm_follow_page (void *vaddr) +{ +printk("drm_follow_page: vaddr=%p\n", vaddr); + pgd_t *pgd = pgd_offset_k((unsigned long) vaddr); +printk(" pgd=%p\n", pgd); + pmd_t *pmd = pmd_offset(pgd, (unsigned long) vaddr); +printk(" pmd=%p\n", pmd); + pte_t *ptep = pte_offset_kernel(pmd, (unsigned long) vaddr); +printk(" ptep=%p\n", ptep); +printk(" page=0x%lx\n", pte_pfn(*ptep) << PAGE_SHIFT); + return pte_pfn(*ptep) << PAGE_SHIFT; +} + +#else /* !__REALLY_HAVE_AGP */ + +static inline void * +agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev) { return NULL; } + +#endif /* !__REALLY_HAVE_AGP */ + +void *DRM(ioremap)(unsigned long offset, unsigned long size, drm_device_t *dev) +{ + int remap_aperture = 0; void *pt; if (!size) { - DRM_MEM_ERROR(DRM_MEM_MAPPINGS, - "Mapping 0 bytes at 0x%08lx\n", offset); + DRM_MEM_ERROR(DRM_MEM_MAPPINGS, "Mapping 0 bytes at 0x%08lx\n", offset); return NULL; } - if (!(pt = ioremap(offset, size))) { +#if __REALLY_HAVE_AGP + if (dev->agp->cant_use_aperture) { + drm_map_t *map = drm_lookup_map(offset, size, dev); + + if (map && map->type == _DRM_AGP) + remap_aperture = 1; + } +#endif + if (remap_aperture) + pt = agp_remap(offset, size, dev); + else + pt = ioremap(offset, size); + if (!pt) { spin_lock(&DRM(mem_lock)); ++DRM(mem_stats)[DRM_MEM_MAPPINGS].fail_count; spin_unlock(&DRM(mem_lock)); @@ -314,8 +423,9 @@ return pt; } -void *DRM(ioremap_nocache)(unsigned long offset, unsigned long size) +void *DRM(ioremap_nocache)(unsigned long offset, unsigned long size, drm_device_t *dev) { + int remap_aperture = 0; void *pt; if (!size) { @@ -324,7 +434,19 @@ return NULL; } - if (!(pt = ioremap_nocache(offset, size))) { +#if __REALLY_HAVE_AGP + if (dev->agp->cant_use_aperture) { + drm_map_t *map = drm_lookup_map(offset, size, dev); + + if (map && map->type == _DRM_AGP) + remap_aperture = 1; + } +#endif + if (remap_aperture) + pt = agp_remap(offset, size, dev); + else + pt = ioremap_nocache(offset, size); + if (!pt) { spin_lock(&DRM(mem_lock)); ++DRM(mem_stats)[DRM_MEM_MAPPINGS].fail_count; spin_unlock(&DRM(mem_lock)); @@ -337,16 +459,40 @@ return pt; } -void DRM(ioremapfree)(void *pt, unsigned long size) +void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev) { int alloc_count; int free_count; +printk("ioremapfree(pt=%p)\n", pt); if (!pt) DRM_MEM_ERROR(DRM_MEM_MAPPINGS, "Attempt to free NULL pointer\n"); - else - iounmap(pt); + else { + int unmap_aperture = 0; +#if __REALLY_HAVE_AGP + /* + * This is rather ugly. It would be much cleaner if the DRM API would use + * separate routines for handling mappings in the AGP space. Hopefully this + * can be done in a future revision of the interface... + */ + if (dev->agp->cant_use_aperture + && ((unsigned long) pt >= VMALLOC_START && (unsigned long) pt < VMALLOC_END)) + { + unsigned long offset = (drm_follow_page(pt) + | ((unsigned long) pt & ~PAGE_MASK)); +printk("offset=0x%lx\n", offset); + drm_map_t *map = drm_lookup_map(offset, size, dev); +printk("map=%p\n", map); + if (map && map->type == _DRM_AGP) + unmap_aperture = 1; + } +#endif + if (unmap_aperture) + vunmap(pt); + else + iounmap(pt); + } spin_lock(&DRM(mem_lock)); DRM(mem_stats)[DRM_MEM_MAPPINGS].bytes_freed += size; diff -Nru a/drivers/char/drm/drm_vm.h b/drivers/char/drm/drm_vm.h --- a/drivers/char/drm/drm_vm.h Wed Jan 15 16:57:29 2003 +++ b/drivers/char/drm/drm_vm.h Wed Jan 15 16:57:29 2003 @@ -108,12 +108,12 @@ * Get the page, inc the use count, and return it */ offset = (baddr - agpmem->bound) >> PAGE_SHIFT; - agpmem->memory->memory[offset] &= dev->agp->page_mask; page = virt_to_page(__va(agpmem->memory->memory[offset])); get_page(page); - DRM_DEBUG("baddr = 0x%lx page = 0x%p, offset = 0x%lx\n", - baddr, __va(agpmem->memory->memory[offset]), offset); + DRM_DEBUG("baddr = 0x%lx page = 0x%p, offset = 0x%lx, count=%d\n", + baddr, __va(agpmem->memory->memory[offset]), offset, + atomic_read(&page->count)); return page; } @@ -207,7 +207,7 @@ DRM_DEBUG("mtrr_del = %d\n", retcode); } #endif - DRM(ioremapfree)(map->handle, map->size); + DRM(ioremapfree)(map->handle, map->size, dev); break; case _DRM_SHM: vfree(map->handle); @@ -421,15 +421,16 @@ switch (map->type) { case _DRM_AGP: -#if defined(__alpha__) +#if __REALLY_HAVE_AGP + if (dev->agp->cant_use_aperture) { /* - * On Alpha we can't talk to bus dma address from the - * CPU, so for memory of type DRM_AGP, we'll deal with - * sorting out the real physical pages and mappings - * in nopage() + * On some platforms we can't talk to bus dma address from the CPU, so for + * memory of type DRM_AGP, we'll deal with sorting out the real physical + * pages and mappings in nopage() */ vma->vm_ops = &DRM(vm_ops); break; + } #endif /* fall through to _DRM_FRAME_BUFFER... */ case _DRM_FRAME_BUFFER: @@ -440,15 +441,15 @@ pgprot_val(vma->vm_page_prot) |= _PAGE_PCD; pgprot_val(vma->vm_page_prot) &= ~_PAGE_PWT; } -#elif defined(__ia64__) - if (map->type != _DRM_AGP) - vma->vm_page_prot = - pgprot_writecombine(vma->vm_page_prot); #elif defined(__powerpc__) pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE | _PAGE_GUARDED; #endif vma->vm_flags |= VM_IO; /* not in core dump */ } +#if defined(__ia64__) + if (map->type != _DRM_AGP) + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); +#endif offset = DRIVER_GET_REG_OFS(); #ifdef __sparc__ if (io_remap_page_range(DRM_RPR_ARG(vma) vma->vm_start, diff -Nru a/drivers/char/drm/gamma_dma.c b/drivers/char/drm/gamma_dma.c --- a/drivers/char/drm/gamma_dma.c Wed Jan 15 16:57:29 2003 +++ b/drivers/char/drm/gamma_dma.c Wed Jan 15 16:57:29 2003 @@ -637,7 +637,7 @@ } else { DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset ); - DRM_IOREMAP( dev_priv->buffers ); + DRM_IOREMAP( dev_priv->buffers, dev ); buf = dma->buflist[GLINT_DRI_BUF_COUNT]; pgt = buf->address; @@ -667,7 +667,7 @@ if ( dev->dev_private ) { drm_gamma_private_t *dev_priv = dev->dev_private; - DRM_IOREMAPFREE( dev_priv->buffers ); + DRM_IOREMAPFREE( dev_priv->buffers, dev ); DRM(free)( dev->dev_private, sizeof(drm_gamma_private_t), DRM_MEM_DRIVER ); diff -Nru a/drivers/char/drm/i810_dma.c b/drivers/char/drm/i810_dma.c --- a/drivers/char/drm/i810_dma.c Wed Jan 15 16:57:28 2003 +++ b/drivers/char/drm/i810_dma.c Wed Jan 15 16:57:28 2003 @@ -275,7 +275,7 @@ if(dev_priv->ring.virtual_start) { DRM(ioremapfree)((void *) dev_priv->ring.virtual_start, - dev_priv->ring.Size); + dev_priv->ring.Size, dev); } if(dev_priv->hw_status_page != 0UL) { pci_free_consistent(dev->pdev, PAGE_SIZE, @@ -291,7 +291,7 @@ for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[ i ]; drm_i810_buf_priv_t *buf_priv = buf->dev_private; - DRM(ioremapfree)(buf_priv->kernel_virtual, buf->total); + DRM(ioremapfree)(buf_priv->kernel_virtual, buf->total, dev); } } return 0; @@ -361,7 +361,7 @@ *buf_priv->in_use = I810_BUF_FREE; buf_priv->kernel_virtual = DRM(ioremap)(buf->bus_address, - buf->total); + buf->total, dev); } return 0; } @@ -414,7 +414,7 @@ dev_priv->ring.virtual_start = DRM(ioremap)(dev->agp->base + init->ring_start, - init->ring_size); + init->ring_size, dev); if (dev_priv->ring.virtual_start == NULL) { dev->dev_private = (void *) dev_priv; diff -Nru a/drivers/char/drm/i830_dma.c b/drivers/char/drm/i830_dma.c --- a/drivers/char/drm/i830_dma.c Wed Jan 15 16:57:28 2003 +++ b/drivers/char/drm/i830_dma.c Wed Jan 15 16:57:28 2003 @@ -283,7 +283,7 @@ if(dev_priv->ring.virtual_start) { DRM(ioremapfree)((void *) dev_priv->ring.virtual_start, - dev_priv->ring.Size); + dev_priv->ring.Size, dev); } if(dev_priv->hw_status_page != 0UL) { pci_free_consistent(dev->pdev, PAGE_SIZE, @@ -299,7 +299,7 @@ for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[ i ]; drm_i830_buf_priv_t *buf_priv = buf->dev_private; - DRM(ioremapfree)(buf_priv->kernel_virtual, buf->total); + DRM(ioremapfree)(buf_priv->kernel_virtual, buf->total, dev); } } return 0; @@ -371,7 +371,7 @@ *buf_priv->in_use = I830_BUF_FREE; buf_priv->kernel_virtual = DRM(ioremap)(buf->bus_address, - buf->total); + buf->total, dev); } return 0; } @@ -425,7 +425,7 @@ dev_priv->ring.virtual_start = DRM(ioremap)(dev->agp->base + init->ring_start, - init->ring_size); + init->ring_size, dev); if (dev_priv->ring.virtual_start == NULL) { dev->dev_private = (void *) dev_priv; diff -Nru a/drivers/char/drm/mga_dma.c b/drivers/char/drm/mga_dma.c --- a/drivers/char/drm/mga_dma.c Wed Jan 15 16:57:29 2003 +++ b/drivers/char/drm/mga_dma.c Wed Jan 15 16:57:29 2003 @@ -554,9 +554,9 @@ (drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle + init->sarea_priv_offset); - DRM_IOREMAP( dev_priv->warp ); - DRM_IOREMAP( dev_priv->primary ); - DRM_IOREMAP( dev_priv->buffers ); + DRM_IOREMAP( dev_priv->warp, dev ); + DRM_IOREMAP( dev_priv->primary, dev ); + DRM_IOREMAP( dev_priv->buffers, dev ); if(!dev_priv->warp->handle || !dev_priv->primary->handle || @@ -642,9 +642,9 @@ if ( dev->dev_private ) { drm_mga_private_t *dev_priv = dev->dev_private; - DRM_IOREMAPFREE( dev_priv->warp ); - DRM_IOREMAPFREE( dev_priv->primary ); - DRM_IOREMAPFREE( dev_priv->buffers ); + DRM_IOREMAPFREE( dev_priv->warp, dev ); + DRM_IOREMAPFREE( dev_priv->primary, dev ); + DRM_IOREMAPFREE( dev_priv->buffers, dev ); if ( dev_priv->head != NULL ) { mga_freelist_cleanup( dev ); diff -Nru a/drivers/char/drm/mga_drv.h b/drivers/char/drm/mga_drv.h --- a/drivers/char/drm/mga_drv.h Wed Jan 15 16:57:29 2003 +++ b/drivers/char/drm/mga_drv.h Wed Jan 15 16:57:29 2003 @@ -238,7 +238,7 @@ if ( MGA_VERBOSE ) { \ DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \ (n), __FUNCTION__ ); \ - DRM_INFO( " space=0x%x req=0x%x\n", \ + DRM_INFO( " space=0x%x req=0x%Zx\n", \ dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \ } \ prim = dev_priv->prim.start; \ @@ -288,7 +288,7 @@ #define DMA_WRITE( offset, val ) \ do { \ if ( MGA_VERBOSE ) { \ - DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04x\n", \ + DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \ (u32)(val), write + (offset) * sizeof(u32) ); \ } \ *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ diff -Nru a/drivers/char/drm/r128_cce.c b/drivers/char/drm/r128_cce.c --- a/drivers/char/drm/r128_cce.c Wed Jan 15 16:57:28 2003 +++ b/drivers/char/drm/r128_cce.c Wed Jan 15 16:57:28 2003 @@ -350,8 +350,8 @@ R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR, entry->busaddr[page_ofs]); - DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n", - entry->busaddr[page_ofs], + DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n", + (unsigned long) entry->busaddr[page_ofs], entry->handle + tmp_ofs ); } @@ -540,9 +540,9 @@ init->sarea_priv_offset); if ( !dev_priv->is_pci ) { - DRM_IOREMAP( dev_priv->cce_ring ); - DRM_IOREMAP( dev_priv->ring_rptr ); - DRM_IOREMAP( dev_priv->buffers ); + DRM_IOREMAP( dev_priv->cce_ring, dev ); + DRM_IOREMAP( dev_priv->ring_rptr, dev ); + DRM_IOREMAP( dev_priv->buffers, dev ); if(!dev_priv->cce_ring->handle || !dev_priv->ring_rptr->handle || !dev_priv->buffers->handle) { @@ -618,9 +618,9 @@ #if __REALLY_HAVE_SG if ( !dev_priv->is_pci ) { #endif - DRM_IOREMAPFREE( dev_priv->cce_ring ); - DRM_IOREMAPFREE( dev_priv->ring_rptr ); - DRM_IOREMAPFREE( dev_priv->buffers ); + DRM_IOREMAPFREE( dev_priv->cce_ring, dev ); + DRM_IOREMAPFREE( dev_priv->ring_rptr, dev ); + DRM_IOREMAPFREE( dev_priv->buffers, dev ); #if __REALLY_HAVE_SG } else { if (!DRM(ati_pcigart_cleanup)( dev, diff -Nru a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c --- a/drivers/char/drm/radeon_cp.c Wed Jan 15 16:57:28 2003 +++ b/drivers/char/drm/radeon_cp.c Wed Jan 15 16:57:28 2003 @@ -904,8 +904,8 @@ RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); - DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n", - entry->busaddr[page_ofs], + DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n", + (unsigned long) entry->busaddr[page_ofs], entry->handle + tmp_ofs ); } @@ -1157,9 +1157,9 @@ init->sarea_priv_offset); if ( !dev_priv->is_pci ) { - DRM_IOREMAP( dev_priv->cp_ring ); - DRM_IOREMAP( dev_priv->ring_rptr ); - DRM_IOREMAP( dev_priv->buffers ); + DRM_IOREMAP( dev_priv->cp_ring, dev ); + DRM_IOREMAP( dev_priv->ring_rptr, dev ); + DRM_IOREMAP( dev_priv->buffers, dev ); if(!dev_priv->cp_ring->handle || !dev_priv->ring_rptr->handle || !dev_priv->buffers->handle) { @@ -1278,9 +1278,9 @@ drm_radeon_private_t *dev_priv = dev->dev_private; if ( !dev_priv->is_pci ) { - DRM_IOREMAPFREE( dev_priv->cp_ring ); - DRM_IOREMAPFREE( dev_priv->ring_rptr ); - DRM_IOREMAPFREE( dev_priv->buffers ); + DRM_IOREMAPFREE( dev_priv->cp_ring, dev ); + DRM_IOREMAPFREE( dev_priv->ring_rptr, dev ); + DRM_IOREMAPFREE( dev_priv->buffers, dev ); } else { #if __REALLY_HAVE_SG if (!DRM(ati_pcigart_cleanup)( dev, diff -Nru a/drivers/char/efirtc.c b/drivers/char/efirtc.c --- a/drivers/char/efirtc.c Wed Jan 15 16:57:29 2003 +++ b/drivers/char/efirtc.c Wed Jan 15 16:57:29 2003 @@ -40,7 +40,7 @@ #include #include -#define EFI_RTC_VERSION "0.3" +#define EFI_RTC_VERSION "0.4" #define EFI_ISDST (EFI_TIME_ADJUST_DAYLIGHT|EFI_TIME_IN_DAYLIGHT) /* @@ -315,14 +315,14 @@ spin_unlock_irqrestore(&efi_rtc_lock,flags); p += sprintf(p, - "Time : %u:%u:%u.%09u\n" - "Date : %u-%u-%u\n" - "Daylight : %u\n", + "Time : %u:%u:%u.%09u\n" + "Date : %u-%u-%u\n" + "Daylight : %u\n", eft.hour, eft.minute, eft.second, eft.nanosecond, eft.year, eft.month, eft.day, eft.daylight); - if ( eft.timezone == EFI_UNSPECIFIED_TIMEZONE) + if (eft.timezone == EFI_UNSPECIFIED_TIMEZONE) p += sprintf(p, "Timezone : unspecified\n"); else /* XXX fixme: convert to string? */ @@ -341,7 +341,7 @@ enabled == 1 ? "yes" : "no", pending == 1 ? "yes" : "no"); - if ( eft.timezone == EFI_UNSPECIFIED_TIMEZONE) + if (eft.timezone == EFI_UNSPECIFIED_TIMEZONE) p += sprintf(p, "Timezone : unspecified\n"); else /* XXX fixme: convert to string? */ @@ -375,17 +375,25 @@ static int __init efi_rtc_init(void) { - int ret =0; + int ret; + struct proc_dir_entry *dir; + printk(KERN_INFO "EFI Time Services Driver v%s\n", EFI_RTC_VERSION); ret = misc_register(&efi_rtc_dev); if (ret) { - printk(KERN_ERR "driver/efirtc: can't misc_register on minor=%d\n", EFI_RTC_MINOR); + printk(KERN_ERR "efirtc: can't misc_register on minor=%d\n", + EFI_RTC_MINOR); return ret; } - create_proc_read_entry ("driver/efirtc", 0, NULL, efi_rtc_read_proc, NULL); - + dir = create_proc_read_entry ("driver/efirtc", 0, NULL, + efi_rtc_read_proc, NULL); + if (dir == NULL) { + printk(KERN_ERR "efirtc: can't create /proc/driver/efirtc.\n"); + misc_deregister(&efi_rtc_dev); + return -1; + } return 0; } diff -Nru a/drivers/char/mem.c b/drivers/char/mem.c --- a/drivers/char/mem.c Wed Jan 15 16:57:29 2003 +++ b/drivers/char/mem.c Wed Jan 15 16:57:29 2003 @@ -531,10 +531,12 @@ case 0: file->f_pos = offset; ret = file->f_pos; + force_successful_syscall_return(); break; case 1: file->f_pos += offset; ret = file->f_pos; + force_successful_syscall_return(); break; default: ret = -EINVAL; diff -Nru a/drivers/md/dm-ioctl.c b/drivers/md/dm-ioctl.c --- a/drivers/md/dm-ioctl.c Wed Jan 15 16:57:28 2003 +++ b/drivers/md/dm-ioctl.c Wed Jan 15 16:57:28 2003 @@ -986,6 +986,10 @@ static int validate_params(uint cmd, struct dm_ioctl *param) { + /* Ignores parameters */ + if (cmd == DM_REMOVE_ALL_CMD) + return 0; + /* Unless creating, either name of uuid but not both */ if (cmd != DM_DEV_CREATE_CMD) { if ((!*param->uuid && !*param->name) || diff -Nru a/drivers/md/dm-linear.c b/drivers/md/dm-linear.c --- a/drivers/md/dm-linear.c Wed Jan 15 16:57:29 2003 +++ b/drivers/md/dm-linear.c Wed Jan 15 16:57:29 2003 @@ -43,7 +43,7 @@ goto bad; } - if (dm_get_device(ti, argv[0], ti->begin, ti->len, + if (dm_get_device(ti, argv[0], lc->start, ti->len, dm_table_get_mode(ti->table), &lc->dev)) { ti->error = "dm-linear: Device lookup failed"; goto bad; diff -Nru a/drivers/md/dm-stripe.c b/drivers/md/dm-stripe.c --- a/drivers/md/dm-stripe.c Wed Jan 15 16:57:29 2003 +++ b/drivers/md/dm-stripe.c Wed Jan 15 16:57:29 2003 @@ -117,12 +117,29 @@ return -EINVAL; } + /* + * chunk_size is a power of two + */ + if (!chunk_size || (chunk_size & (chunk_size - 1))) { + ti->error = "dm-stripe: Invalid chunk size"; + return -EINVAL; + } + if (!multiple(ti->len, stripes, &width)) { ti->error = "dm-stripe: Target length not divisable by " "number of stripes"; return -EINVAL; } + /* + * Do we have enough arguments for that many stripes ? + */ + if (argc != (2 + 2 * stripes)) { + ti->error = "dm-stripe: Not enough destinations " + "specified"; + return -EINVAL; + } + sc = alloc_context(stripes); if (!sc) { ti->error = "dm-stripe: Memory allocation for striped context " @@ -134,15 +151,6 @@ sc->stripe_width = width; ti->split_io = chunk_size; - /* - * chunk_size is a power of two - */ - if (!chunk_size || (chunk_size & (chunk_size - 1))) { - ti->error = "dm-stripe: Invalid chunk size"; - kfree(sc); - return -EINVAL; - } - sc->chunk_mask = ((sector_t) chunk_size) - 1; for (sc->chunk_shift = 0; chunk_size; sc->chunk_shift++) chunk_size >>= 1; @@ -152,13 +160,6 @@ * Get the stripe destinations. */ for (i = 0; i < stripes; i++) { - if (argc < 2) { - ti->error = "dm-stripe: Not enough destinations " - "specified"; - kfree(sc); - return -EINVAL; - } - argv += 2; r = get_stripe(ti, sc, i, argv); diff -Nru a/drivers/md/dm-table.c b/drivers/md/dm-table.c --- a/drivers/md/dm-table.c Wed Jan 15 16:57:29 2003 +++ b/drivers/md/dm-table.c Wed Jan 15 16:57:29 2003 @@ -312,7 +312,7 @@ } if (!S_ISBLK(inode->i_mode)) { - r = -EINVAL; + r = -ENOTBLK; goto out; } @@ -356,7 +356,7 @@ return -ENOMEM; r = blkdev_get(d->bdev, d->mode, 0, BDEV_RAW); - if (!r) + if (r) return r; r = bd_claim(d->bdev, _claim_ptr); @@ -388,7 +388,7 @@ static int check_device_area(struct dm_dev *dd, sector_t start, sector_t len) { sector_t dev_size; - dev_size = dd->bdev->bd_inode->i_size; + dev_size = dd->bdev->bd_inode->i_size >> SECTOR_SHIFT; return ((start < dev_size) && (len <= (dev_size - start))); } diff -Nru a/drivers/md/dm.c b/drivers/md/dm.c --- a/drivers/md/dm.c Wed Jan 15 16:57:29 2003 +++ b/drivers/md/dm.c Wed Jan 15 16:57:29 2003 @@ -16,7 +16,6 @@ static const char *_name = DM_NAME; #define MAX_DEVICES (1 << KDEV_MINOR_BITS) -#define SECTOR_SHIFT 9 static int major = 0; static int _major = 0; @@ -59,11 +58,15 @@ * The current mapping. */ struct dm_table *map; + + /* + * io objects are allocated from here. + */ + mempool_t *io_pool; }; #define MIN_IOS 256 static kmem_cache_t *_io_cache; -static mempool_t *_io_pool; static __init int local_init(void) { @@ -75,18 +78,10 @@ if (!_io_cache) return -ENOMEM; - _io_pool = mempool_create(MIN_IOS, mempool_alloc_slab, - mempool_free_slab, _io_cache); - if (!_io_pool) { - kmem_cache_destroy(_io_cache); - return -ENOMEM; - } - _major = major; r = register_blkdev(_major, _name, &dm_blk_dops); if (r < 0) { DMERR("register_blkdev failed"); - mempool_destroy(_io_pool); kmem_cache_destroy(_io_cache); return r; } @@ -99,7 +94,6 @@ static void local_exit(void) { - mempool_destroy(_io_pool); kmem_cache_destroy(_io_cache); if (unregister_blkdev(_major, _name) < 0) @@ -179,14 +173,14 @@ return 0; } -static inline struct dm_io *alloc_io(void) +static inline struct dm_io *alloc_io(struct mapped_device *md) { - return mempool_alloc(_io_pool, GFP_NOIO); + return mempool_alloc(md->io_pool, GFP_NOIO); } -static inline void free_io(struct dm_io *io) +static inline void free_io(struct mapped_device *md, struct dm_io *io) { - mempool_free(io, _io_pool); + mempool_free(io, md->io_pool); } static inline struct deferred_io *alloc_deferred(void) @@ -212,7 +206,7 @@ down_write(&md->lock); - if (!test_bit(DMF_SUSPENDED, &md->flags)) { + if (!test_bit(DMF_BLOCK_IO, &md->flags)) { up_write(&md->lock); free_deferred(di); return 1; @@ -234,6 +228,15 @@ * interests of getting something for people to use I give * you this clearly demarcated crap. *---------------------------------------------------------------*/ +static inline sector_t to_sector(unsigned int bytes) +{ + return bytes >> SECTOR_SHIFT; +} + +static inline unsigned int to_bytes(sector_t sector) +{ + return sector << SECTOR_SHIFT; +} /* * Decrements the number of outstanding ios that a bio has been @@ -244,18 +247,19 @@ static spinlock_t _uptodate_lock = SPIN_LOCK_UNLOCKED; unsigned long flags; - spin_lock_irqsave(&_uptodate_lock, flags); - if (error) + if (error) { + spin_lock_irqsave(&_uptodate_lock, flags); io->error = error; - spin_unlock_irqrestore(&_uptodate_lock, flags); + spin_unlock_irqrestore(&_uptodate_lock, flags); + } if (atomic_dec_and_test(&io->io_count)) { if (atomic_dec_and_test(&io->md->pending)) /* nudge anyone waiting on suspend queue */ wake_up(&io->md->wait); - bio_endio(io->bio, io->error ? 0 : io->bio->bi_size, io->error); - free_io(io); + bio_endio(io->bio, io->bio->bi_size, io->error); + free_io(io->md, io); } } @@ -263,16 +267,11 @@ { struct dm_io *io = bio->bi_private; - /* - * Only call dec_pending if the clone has completely - * finished. If a partial io errors I'm assuming it won't - * be requeued. FIXME: check this. - */ - if (error || !bio->bi_size) { - dec_pending(io, error); - bio_put(bio); - } + if (bio->bi_size) + return 1; + dec_pending(io, error); + bio_put(bio); return 0; } @@ -280,16 +279,17 @@ static sector_t max_io_len(struct mapped_device *md, sector_t sector, struct dm_target *ti) { - sector_t len = ti->len; + sector_t offset = sector - ti->begin; + sector_t len = ti->len - offset; /* FIXME: obey io_restrictions ! */ + /* * Does the target need to split even further ? */ if (ti->split_io) { sector_t boundary; - sector_t offset = sector - ti->begin; boundary = dm_round_up(offset + 1, ti->split_io) - offset; if (len > boundary) @@ -299,23 +299,23 @@ return len; } -static void __map_bio(struct dm_target *ti, struct bio *clone) +static void __map_bio(struct dm_target *ti, struct bio *clone, struct dm_io *io) { - struct dm_io *io = clone->bi_private; int r; /* * Sanity checks. */ - if (!clone->bi_size) - BUG(); + BUG_ON(!clone->bi_size); + + clone->bi_end_io = clone_endio; + clone->bi_private = io; /* * Map the clone. If r == 0 we don't need to do * anything, the target has assumed ownership of * this io. */ - atomic_inc(&io->md->pending); atomic_inc(&io->io_count); r = ti->type->map(ti, clone); if (r > 0) @@ -337,77 +337,125 @@ }; /* - * Issues a little bio that just does the back end of a split page. + * Creates a little bio that is just does part of a bvec. */ -static void __split_page(struct clone_info *ci, unsigned int len) +static struct bio *split_bvec(struct bio *bio, sector_t sector, + unsigned short idx, unsigned int offset, + unsigned int len) { - struct dm_target *ti = dm_table_find_target(ci->md->map, ci->sector); - struct bio *clone, *bio = ci->bio; - struct bio_vec *bv = bio->bi_io_vec + (bio->bi_vcnt - 1); + struct bio *clone; + struct bio_vec *bv = bio->bi_io_vec + idx; - DMWARN("splitting page"); + clone = bio_alloc(GFP_NOIO, 1); - if (len > ci->sector_count) - len = ci->sector_count; + if (clone) { + memcpy(clone->bi_io_vec, bv, sizeof(*bv)); - clone = bio_alloc(GFP_NOIO, 1); - memcpy(clone->bi_io_vec, bv, sizeof(*bv)); + clone->bi_sector = sector; + clone->bi_bdev = bio->bi_bdev; + clone->bi_rw = bio->bi_rw; + clone->bi_vcnt = 1; + clone->bi_size = to_bytes(len); + clone->bi_io_vec->bv_offset = offset; + clone->bi_io_vec->bv_len = clone->bi_size; + } - clone->bi_sector = ci->sector; - clone->bi_bdev = bio->bi_bdev; - clone->bi_flags = bio->bi_flags | (1 << BIO_SEG_VALID); - clone->bi_rw = bio->bi_rw; - clone->bi_size = len << SECTOR_SHIFT; - clone->bi_end_io = clone_endio; - clone->bi_private = ci->io; + return clone; +} + +/* + * Creates a bio that consists of range of complete bvecs. + */ +static struct bio *clone_bio(struct bio *bio, sector_t sector, + unsigned short idx, unsigned short bv_count, + unsigned int len) +{ + struct bio *clone; - ci->sector += len; - ci->sector_count -= len; + clone = bio_clone(bio, GFP_NOIO); + clone->bi_sector = sector; + clone->bi_idx = idx; + clone->bi_vcnt = idx + bv_count; + clone->bi_size = to_bytes(len); - __map_bio(ti, clone); + return clone; } static void __clone_and_map(struct clone_info *ci) { struct bio *clone, *bio = ci->bio; struct dm_target *ti = dm_table_find_target(ci->md->map, ci->sector); - sector_t len = max_io_len(ci->md, bio->bi_sector, ti); + sector_t len = 0, max = max_io_len(ci->md, ci->sector, ti); - /* shorter than current target ? */ - if (ci->sector_count < len) - len = ci->sector_count; - - /* create the clone */ - clone = bio_clone(ci->bio, GFP_NOIO); - clone->bi_sector = ci->sector; - clone->bi_idx = ci->idx; - clone->bi_size = len << SECTOR_SHIFT; - clone->bi_end_io = clone_endio; - clone->bi_private = ci->io; + if (ci->sector_count <= max) { + /* + * Optimise for the simple case where we can do all of + * the remaining io with a single clone. + */ + clone = clone_bio(bio, ci->sector, ci->idx, + bio->bi_vcnt - ci->idx, ci->sector_count); + __map_bio(ti, clone, ci->io); + ci->sector_count = 0; - /* adjust the remaining io */ - ci->sector += len; - ci->sector_count -= len; - __map_bio(ti, clone); + } else if (to_sector(bio->bi_io_vec[ci->idx].bv_len) <= max) { + /* + * There are some bvecs that don't span targets. + * Do as many of these as possible. + */ + int i; + sector_t remaining = max; + sector_t bv_len; - /* - * If we are not performing all remaining io in this - * clone then we need to calculate ci->idx for the next - * time round. - */ - if (ci->sector_count) { - while (len) { - struct bio_vec *bv = clone->bi_io_vec + ci->idx; - sector_t bv_len = bv->bv_len >> SECTOR_SHIFT; - if (bv_len <= len) - len -= bv_len; - - else { - __split_page(ci, bv_len - len); - len = 0; - } - ci->idx++; + for (i = ci->idx; remaining && (i < bio->bi_vcnt); i++) { + bv_len = to_sector(bio->bi_io_vec[i].bv_len); + + if (bv_len > remaining) + break; + + remaining -= bv_len; + len += bv_len; + } + + clone = clone_bio(bio, ci->sector, ci->idx, i - ci->idx, len); + __map_bio(ti, clone, ci->io); + + ci->sector += len; + ci->sector_count -= len; + ci->idx = i; + + } else { + /* + * Create two copy bios to deal with io that has + * been split across a target. + */ + struct bio_vec *bv = bio->bi_io_vec + ci->idx; + + clone = split_bvec(bio, ci->sector, ci->idx, + bv->bv_offset, max); + if (!clone) { + dec_pending(ci->io, -ENOMEM); + return; + } + + __map_bio(ti, clone, ci->io); + + ci->sector += max; + ci->sector_count -= max; + ti = dm_table_find_target(ci->md->map, ci->sector); + + len = to_sector(bv->bv_len) - max; + clone = split_bvec(bio, ci->sector, ci->idx, + bv->bv_offset + to_bytes(max), len); + if (!clone) { + dec_pending(ci->io, -ENOMEM); + return; } + + __map_bio(ti, clone, ci->io); + + ci->sector += len; + ci->sector_count -= len; + ci->idx++; } } @@ -420,7 +468,7 @@ ci.md = md; ci.bio = bio; - ci.io = alloc_io(); + ci.io = alloc_io(md); ci.io->error = 0; atomic_set(&ci.io->io_count, 1); ci.io->bio = bio; @@ -429,6 +477,7 @@ ci.sector_count = bio_sectors(bio); ci.idx = 0; + atomic_inc(&md->pending); while (ci.sector_count) __clone_and_map(&ci); @@ -459,13 +508,13 @@ up_read(&md->lock); if (bio_rw(bio) == READA) { - bio_io_error(bio, 0); + bio_io_error(bio, bio->bi_size); return 0; } r = queue_io(md, bio); if (r < 0) { - bio_io_error(bio, 0); + bio_io_error(bio, bio->bi_size); return 0; } else if (r == 0) @@ -559,8 +608,17 @@ md->queue.queuedata = md; blk_queue_make_request(&md->queue, dm_request); + md->io_pool = mempool_create(MIN_IOS, mempool_alloc_slab, + mempool_free_slab, _io_cache); + if (!md->io_pool) { + free_minor(md->disk->first_minor); + kfree(md); + return NULL; + } + md->disk = alloc_disk(1); if (!md->disk) { + mempool_destroy(md->io_pool); free_minor(md->disk->first_minor); kfree(md); return NULL; @@ -582,6 +640,7 @@ static void free_dev(struct mapped_device *md) { free_minor(md->disk->first_minor); + mempool_destroy(md->io_pool); del_gendisk(md->disk); put_disk(md->disk); kfree(md); @@ -711,15 +770,14 @@ } set_bit(DMF_BLOCK_IO, &md->flags); + add_wait_queue(&md->wait, &wait); up_write(&md->lock); /* * Then we wait for the already mapped ios to * complete. */ - down_read(&md->lock); - - add_wait_queue(&md->wait, &wait); + blk_run_queues(); while (1) { set_current_state(TASK_INTERRUPTIBLE); @@ -730,11 +788,11 @@ } current->state = TASK_RUNNING; - remove_wait_queue(&md->wait, &wait); - up_read(&md->lock); - /* set_bit is atomic */ + down_write(&md->lock); + remove_wait_queue(&md->wait, &wait); set_bit(DMF_SUSPENDED, &md->flags); + up_write(&md->lock); return 0; } diff -Nru a/drivers/md/dm.h b/drivers/md/dm.h --- a/drivers/md/dm.h Wed Jan 15 16:57:29 2003 +++ b/drivers/md/dm.h Wed Jan 15 16:57:29 2003 @@ -29,6 +29,8 @@ #define SECTOR_FORMAT "%lu" #endif +#define SECTOR_SHIFT 9 + extern struct block_device_operations dm_blk_dops; /* diff -Nru a/drivers/media/radio/Makefile b/drivers/media/radio/Makefile --- a/drivers/media/radio/Makefile Wed Jan 15 16:57:29 2003 +++ b/drivers/media/radio/Makefile Wed Jan 15 16:57:29 2003 @@ -5,6 +5,8 @@ # All of the (potential) objects that export symbols. # This list comes from 'grep -l EXPORT_SYMBOL *.[hc]'. +obj-y := dummy.o + export-objs := miropcm20-rds-core.o miropcm20-objs := miropcm20-rds-core.o miropcm20-radio.o diff -Nru a/drivers/media/radio/dummy.c b/drivers/media/radio/dummy.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/drivers/media/radio/dummy.c Wed Jan 15 16:57:29 2003 @@ -0,0 +1 @@ +/* just so the linker knows what kind of object files it's deadling with... */ diff -Nru a/drivers/media/video/Makefile b/drivers/media/video/Makefile --- a/drivers/media/video/Makefile Wed Jan 15 16:57:29 2003 +++ b/drivers/media/video/Makefile Wed Jan 15 16:57:29 2003 @@ -12,6 +12,8 @@ bttv-risc.o bttv-vbi.o zoran-objs := zr36120.o zr36120_i2c.o zr36120_mem.o +obj-y := dummy.o + obj-$(CONFIG_VIDEO_DEV) += videodev.o v4l2-common.o obj-$(CONFIG_VIDEO_BT848) += bttv.o msp3400.o tvaudio.o \ diff -Nru a/drivers/media/video/dummy.c b/drivers/media/video/dummy.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/drivers/media/video/dummy.c Wed Jan 15 16:57:29 2003 @@ -0,0 +1 @@ +/* just so the linker knows what kind of object files it's deadling with... */ diff -Nru a/drivers/message/fusion/linux_compat.h b/drivers/message/fusion/linux_compat.h --- a/drivers/message/fusion/linux_compat.h Wed Jan 15 16:57:28 2003 +++ b/drivers/message/fusion/linux_compat.h Wed Jan 15 16:57:28 2003 @@ -246,41 +246,30 @@ #endif /* - * We use our new error handling code if the kernel version is 2.5.1 or newer. + * We use our new error handling code if the kernel version is 2.4.18 or newer. */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,1) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,18) #define MPT_SCSI_USE_NEW_EH #endif -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,28) -#define mptscsih_lock(iocp, flags) \ - spin_lock_irqsave(&iocp->FreeQlock, flags) -#else -#define mptscsih_lock(iocp, flags) \ -({ save_flags(flags); \ - cli(); \ -}) -#endif - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,28) -#define mptscsih_unlock(iocp, flags) \ - spin_unlock_irqrestore(&iocp->FreeQlock, flags) -#else -#define mptscsih_unlock(iocp, flags) restore_flags(flags); -#endif - - #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,41) -#define mpt_work_struct work_struct +#define mpt_work_struct work_struct #define MPT_INIT_WORK(_task, _func, _data) INIT_WORK(_task, _func, _data) #else -#define mpt_work_struct tq_struct +#define mpt_work_struct tq_struct #define MPT_INIT_WORK(_task, _func, _data) \ ({ (_task)->sync = 0; \ (_task)->routine = (_func); \ (_task)->data = (void *) (_data); \ }) #endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,28) +#define mptscsih_sync_irq(_irq) synchronize_irq(_irq) +#else +#define mptscsih_sync_irq(_irq) synchronize_irq() +#endif + /*}-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ diff -Nru a/drivers/message/fusion/mptbase.c b/drivers/message/fusion/mptbase.c --- a/drivers/message/fusion/mptbase.c Wed Jan 15 16:57:28 2003 +++ b/drivers/message/fusion/mptbase.c Wed Jan 15 16:57:28 2003 @@ -49,7 +49,7 @@ * (mailto:sjralston1@netscape.net) * (mailto:Pam.Delaney@lsil.com) * - * $Id: mptbase.c,v 1.123 2002/10/17 20:15:56 pdelaney Exp $ + * $Id: mptbase.c,v 1.125 2002/12/03 21:26:32 pdelaney Exp $ */ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* @@ -208,6 +208,7 @@ static int mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum); static int mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum); static int mpt_findImVolumes(MPT_ADAPTER *ioc); +static void mpt_read_ioc_pg_1(MPT_ADAPTER *ioc); static void mpt_timer_expired(unsigned long data); static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch); static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp); @@ -443,7 +444,7 @@ */ if ((mf) && ((mf >= MPT_INDEX_2_MFPTR(ioc, ioc->req_depth)) || (mf < ioc->req_frames)) ) { - printk(MYIOC_s_WARN_FMT + printk(MYIOC_s_WARN_FMT "mpt_interrupt: Invalid mf (%p) req_idx (%d)!\n", ioc->name, (void *)mf, req_idx); cb_idx = 0; pa = 0; @@ -451,14 +452,14 @@ } if ((pa) && (mr) && ((mr >= MPT_INDEX_2_RFPTR(ioc, ioc->req_depth)) || (mr < ioc->reply_frames)) ) { - printk(MYIOC_s_WARN_FMT + printk(MYIOC_s_WARN_FMT "mpt_interrupt: Invalid rf (%p)!\n", ioc->name, (void *)mr); cb_idx = 0; pa = 0; freeme = 0; } if (cb_idx > (MPT_MAX_PROTOCOL_DRIVERS-1)) { - printk(MYIOC_s_WARN_FMT + printk(MYIOC_s_WARN_FMT "mpt_interrupt: Invalid cb_idx (%d)!\n", ioc->name, cb_idx); cb_idx = 0; pa = 0; @@ -576,9 +577,11 @@ CONFIGPARMS *pCfg; unsigned long flags; - dprintk((MYIOC_s_INFO_FMT "config_complete (mf=%p,mr=%p)\n", + dcprintk((MYIOC_s_INFO_FMT "config_complete (mf=%p,mr=%p)\n", ioc->name, mf, reply)); + DBG_DUMP_REPLY_FRAME(reply) + pCfg = * ((CONFIGPARMS **)((u8 *) mf + ioc->req_sz - sizeof(void *))); if (pCfg) { @@ -599,7 +602,7 @@ u16 status; status = le16_to_cpu(pReply->IOCStatus) & MPI_IOCSTATUS_MASK; - dprintk((KERN_NOTICE " IOCStatus=%04xh, IOCLogInfo=%08xh\n", + dcprintk((KERN_NOTICE " IOCStatus=%04xh, IOCLogInfo=%08xh\n", status, le32_to_cpu(pReply->IOCLogInfo))); pCfg->status = status; @@ -943,7 +946,7 @@ * mpt_add_sge - Place a simple SGE at address pAddr. * @pAddr: virtual address for SGE * @flagslength: SGE flags and data transfer length - * @dma_addr: Physical address + * @dma_addr: Physical address * * This routine places a MPT request frame back on the MPT adapter's * FreeQ. @@ -973,7 +976,7 @@ * @pAddr: virtual address for SGE * @next: nextChainOffset value (u32's) * @length: length of next SGL segment - * @dma_addr: Physical address + * @dma_addr: Physical address * * This routine places a MPT request frame back on the MPT adapter's * FreeQ. @@ -986,7 +989,7 @@ u32 tmp = dma_addr & 0xFFFFFFFF; pChain->Length = cpu_to_le16(length); - pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT | mpt_addr_size(); + pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT | mpt_addr_size(); pChain->NextChainOffset = next; @@ -1283,7 +1286,7 @@ return r; if (!pci_set_dma_mask(pdev, mask)) { - dprintk((KERN_INFO MYNAM + dprintk((KERN_INFO MYNAM ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n")); } else if (pci_set_dma_mask(pdev, (u64) 0xffffffff)) { printk(KERN_WARNING MYNAM ": 32 BIT PCI BUS DMA ADDRESSING NOT SUPPORTED\n"); @@ -1470,6 +1473,12 @@ ioc->active = 0; CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); + /* tack onto tail of our MPT adapter list */ + Q_ADD_TAIL(&MptAdapters, ioc, MPT_ADAPTER); + + /* Set lookup ptr. */ + mpt_adapters[ioc->id] = ioc; + ioc->pci_irq = -1; if (pdev->irq) { r = request_irq(pdev->irq, mpt_interrupt, SA_SHIRQ, ioc->name, ioc); @@ -1482,6 +1491,8 @@ printk(MYIOC_s_ERR_FMT "Unable to allocate interrupt %s!\n", ioc->name, __irq_itoa(pdev->irq)); #endif + Q_DEL_ITEM(ioc); + mpt_adapters[ioc->id] = NULL; iounmap(mem); kfree(ioc); return -EBUSY; @@ -1498,16 +1509,10 @@ #endif } - /* tack onto tail of our MPT adapter list */ - Q_ADD_TAIL(&MptAdapters, ioc, MPT_ADAPTER); - - /* Set lookup ptr. */ - mpt_adapters[ioc->id] = ioc; - /* NEW! 20010220 -sralston * Check for "bound ports" (929, 929X, 1030, 1035) to reduce redundant resets. */ - if ((ioc->chip_type == FC929) || (ioc->chip_type == C1030) + if ((ioc->chip_type == FC929) || (ioc->chip_type == C1030) || (ioc->chip_type == C1035) || (ioc->chip_type == FC929X)) mpt_detect_bound_ports(ioc, pdev); @@ -1638,6 +1643,9 @@ printk(KERN_WARNING MYNAM ": firmware upload failure!\n"); /* Handle the alt IOC too */ if ((alt_ioc_ready) && (ioc->alt_ioc->upload_fw)){ + ddlprintk((MYIOC_s_INFO_FMT + "Alt-ioc firmware upload required!\n", + ioc->name)); r = mpt_do_upload(ioc->alt_ioc, sleepFlag); if (r != 0) printk(KERN_WARNING MYNAM ": firmware upload failure!\n"); @@ -1706,14 +1714,18 @@ */ mpt_GetScsiPortSettings(ioc, 0); - /* Get version and length of SDP 1 + /* Get version and length of SDP 1 */ mpt_readScsiDevicePageHeaders(ioc, 0); - /* Find IM volumes + /* Find IM volumes */ if (ioc->facts.MsgVersion >= 0x0102) mpt_findImVolumes(ioc); + + /* Check, and possibly reset, the coalescing value + */ + mpt_read_ioc_pg_1(ioc); } GetIoUnitPage2(ioc); @@ -1819,7 +1831,7 @@ ddlprintk((KERN_INFO MYNAM ": Pushing FW onto adapter\n")); if ((state = mpt_downloadboot(this, NO_SLEEP)) < 0) { - printk(KERN_WARNING MYNAM + printk(KERN_WARNING MYNAM ": firmware downloadboot failure (%d)!\n", state); } } @@ -1919,6 +1931,11 @@ sz_first = this->alloc_total; + if (this->alt_ioc != NULL) { + this->alt_ioc->alt_ioc = NULL; + this->alt_ioc = NULL; + } + mpt_adapter_disable(this, 1); if (this->pci_irq != -1) { @@ -1998,8 +2015,8 @@ * * Returns: * 1 - DIAG reset and READY - * 0 - READY initially OR soft reset and READY - * -1 - Any failure on KickStart + * 0 - READY initially OR soft reset and READY + * -1 - Any failure on KickStart * -2 - Msg Unit Reset Failed * -3 - IO Unit Reset Failed * -4 - IOC owned by a PEER @@ -2042,7 +2059,7 @@ else statefault = 4; } - } + } /* * Check to see if IOC is in FAULT state. @@ -2244,7 +2261,7 @@ facts->RequestFrameSize = le16_to_cpu(facts->RequestFrameSize); /* - * FC f/w version changed between 1.1 and 1.2 + * FC f/w version changed between 1.1 and 1.2 * Old: u16{Major(4),Minor(4),SubMinor(8)} * New: u32{Major(8),Minor(8),Unit(8),Dev(8)} */ @@ -2417,10 +2434,10 @@ if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT) { if ((ioc->cached_fw) || (ioc->alt_ioc && ioc->alt_ioc->cached_fw)) ioc_init.Flags = MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE; - else + else ioc->upload_fw = 1; } - ddlprintk((MYIOC_s_INFO_FMT "flags %d, upload_fw %d \n", + ddlprintk((MYIOC_s_INFO_FMT "flags %d, upload_fw %d \n", ioc->name, ioc_init.Flags, ioc->upload_fw)); if ((int)ioc->chip_type <= (int)FC929) { @@ -2554,8 +2571,8 @@ * Outputs: frags - number of fragments needed * Return NULL if failed. */ -void * -mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size, int *frags, int *alloc_sz) +void * +mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size, int *frags, int *alloc_sz) { fw_image_t **cached_fw = NULL; u8 *mem = NULL; @@ -2564,7 +2581,7 @@ int bytes_left, bytes, num_frags; int sz, ii; - /* cached_fw + /* cached_fw */ sz = ioc->num_fw_frags * sizeof(void *); mem = kmalloc(sz, GFP_ATOMIC); @@ -2721,8 +2738,8 @@ ioc->num_fw_frags = ioc->req_sz - sizeof(FWUpload_t) + sizeof(dma_addr_t) + sizeof(u32) -1; ioc->num_fw_frags /= sizeof(dma_addr_t) + sizeof(u32); - ioc->cached_fw = (fw_image_t **) mpt_alloc_fw_memory(ioc, - ioc->facts.FWImageSize, &num_frags, &alloc_sz); + ioc->cached_fw = (fw_image_t **) mpt_alloc_fw_memory(ioc, + ioc->facts.FWImageSize, &num_frags, &alloc_sz); if (ioc->cached_fw == NULL) { /* Major Failure. @@ -2769,8 +2786,8 @@ sgeoffset += sizeof(u32) + sizeof(dma_addr_t); } - mpt_add_sge(&request[sgeoffset], - MPT_SGE_FLAGS_SSIMPLE_READ |(u32) ioc->cached_fw[ii]->size, + mpt_add_sge(&request[sgeoffset], + MPT_SGE_FLAGS_SSIMPLE_READ |(u32) ioc->cached_fw[ii]->size, ioc->cached_fw[ii]->fw_dma); sgeoffset += sizeof(u32) + sizeof(dma_addr_t); @@ -3117,8 +3134,8 @@ * 0 - no reset due to History bit, READY * -1 - no reset due to History bit but not READY * OR reset but failed to come READY - * -2 - no reset, could not enter DIAG mode - * -3 - reset but bad FW bit + * -2 - no reset, could not enter DIAG mode + * -3 - reset but bad FW bit */ static int KickStart(MPT_ADAPTER *ioc, int force, int sleepFlag) @@ -3254,18 +3271,14 @@ ioc->name, diag0val, diag1val)); #endif /* Write the PreventIocBoot bit */ -#if 1 if ((ioc->cached_fw) || (ioc->alt_ioc && ioc->alt_ioc->cached_fw)) { -#else - if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT) { -#endif diag0val |= MPI_DIAG_PREVENT_IOC_BOOT; CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val); } /* * Disable the ARM (Bug fix) - * + * */ CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM); mdelay (1); @@ -3304,11 +3317,7 @@ /* FIXME? Examine results here? */ } -#if 1 if ((ioc->cached_fw) || (ioc->alt_ioc && ioc->alt_ioc->cached_fw)) { -#else - if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT) { -#endif /* If the DownloadBoot operation fails, the * IOC will be left unusable. This is a fatal error * case. _diag_reset will return < 0 @@ -3318,7 +3327,7 @@ #ifdef MPT_DEBUG if (ioc->alt_ioc) diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); - dprintk((MYIOC_s_INFO_FMT + dprintk((MYIOC_s_INFO_FMT "DbG2b: diag0=%08x, diag1=%08x\n", ioc->name, diag0val, diag1val)); #endif @@ -3335,7 +3344,7 @@ } } if ((count = mpt_downloadboot(ioc, sleepFlag)) < 0) { - printk(KERN_WARNING MYNAM + printk(KERN_WARNING MYNAM ": firmware downloadboot failure (%d)!\n", count); } @@ -3467,7 +3476,7 @@ if ((r = WaitForDoorbellAck(ioc, 2, sleepFlag)) < 0) return r; - /* FW ACK'd request, wait for READY state + /* FW ACK'd request, wait for READY state */ cntdn = HZ * 15; count = 0; @@ -3631,6 +3640,9 @@ } spin_unlock_irqrestore(&ioc->FreeQlock, flags); +#ifdef MFCNT + ioc->mfcnt = 0; +#endif if (ioc->sense_buf_pool == NULL) { sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC); @@ -4267,7 +4279,7 @@ int ii; int data, rc = 0; - /* Allocate memory + /* Allocate memory */ if (!ioc->spi_data.nvram) { int sz; @@ -4446,12 +4458,17 @@ ioc->spi_data.sdp0version = cfg.hdr->PageVersion; ioc->spi_data.sdp0length = cfg.hdr->PageLength; + dcprintk((MYIOC_s_INFO_FMT "Headers: 0: version %d length %d\n", + ioc->name, ioc->spi_data.sdp0version, ioc->spi_data.sdp0length)); + + dcprintk((MYIOC_s_INFO_FMT "Headers: 1: version %d length %d\n", + ioc->name, ioc->spi_data.sdp1version, ioc->spi_data.sdp1length)); return 0; } /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /** - * mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes + * mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes * @ioc: Pointer to a Adapter Strucutre * @portnum: IOC port number * @@ -4464,17 +4481,13 @@ mpt_findImVolumes(MPT_ADAPTER *ioc) { IOCPage2_t *pIoc2 = NULL; - IOCPage3_t *pIoc3 = NULL; ConfigPageIoc2RaidVol_t *pIocRv = NULL; - u8 *mem; dma_addr_t ioc2_dma; - dma_addr_t ioc3_dma; CONFIGPARMS cfg; ConfigPageHeader_t header; int jj; int rc = 0; int iocpage2sz; - int iocpage3sz = 0; u8 nVols, nPhys; u8 vid, vbus, vioc; @@ -4541,44 +4554,7 @@ /* No physical disks. Done. */ } else { - /* There is at least one physical disk. - * Read and save IOC Page 3 - */ - header.PageVersion = 0; - header.PageLength = 0; - header.PageNumber = 3; - header.PageType = MPI_CONFIG_PAGETYPE_IOC; - cfg.hdr = &header; - cfg.physAddr = -1; - cfg.pageAddr = 0; - cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; - cfg.dir = 0; - cfg.timeout = 0; - if (mpt_config(ioc, &cfg) != 0) - goto done_and_free; - - if (header.PageLength == 0) - goto done_and_free; - - /* Read Header good, alloc memory - */ - iocpage3sz = header.PageLength * 4; - pIoc3 = pci_alloc_consistent(ioc->pcidev, iocpage3sz, &ioc3_dma); - if (!pIoc3) - goto done_and_free; - - /* Read the Page and save the data - * into malloc'd memory. - */ - cfg.physAddr = ioc3_dma; - cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; - if (mpt_config(ioc, &cfg) == 0) { - mem = kmalloc(iocpage3sz, GFP_ATOMIC); - if (mem) { - memcpy(mem, (u8 *)pIoc3, iocpage3sz); - ioc->spi_data.pIocPg3 = (IOCPage3_t *) mem; - } - } + mpt_read_ioc_pg_3(ioc); } done_and_free: @@ -4587,14 +4563,159 @@ pIoc2 = NULL; } + return rc; +} + +int +mpt_read_ioc_pg_3(MPT_ADAPTER *ioc) +{ + IOCPage3_t *pIoc3 = NULL; + u8 *mem; + CONFIGPARMS cfg; + ConfigPageHeader_t header; + dma_addr_t ioc3_dma; + int iocpage3sz = 0; + + /* Free the old page + */ + if (ioc->spi_data.pIocPg3) { + kfree(ioc->spi_data.pIocPg3); + ioc->spi_data.pIocPg3 = NULL; + } + + /* There is at least one physical disk. + * Read and save IOC Page 3 + */ + header.PageVersion = 0; + header.PageLength = 0; + header.PageNumber = 3; + header.PageType = MPI_CONFIG_PAGETYPE_IOC; + cfg.hdr = &header; + cfg.physAddr = -1; + cfg.pageAddr = 0; + cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; + cfg.dir = 0; + cfg.timeout = 0; + if (mpt_config(ioc, &cfg) != 0) + return 0; + + if (header.PageLength == 0) + return 0; + + /* Read Header good, alloc memory + */ + iocpage3sz = header.PageLength * 4; + pIoc3 = pci_alloc_consistent(ioc->pcidev, iocpage3sz, &ioc3_dma); + if (!pIoc3) + return 0; + + /* Read the Page and save the data + * into malloc'd memory. + */ + cfg.physAddr = ioc3_dma; + cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; + if (mpt_config(ioc, &cfg) == 0) { + mem = kmalloc(iocpage3sz, GFP_ATOMIC); + if (mem) { + memcpy(mem, (u8 *)pIoc3, iocpage3sz); + ioc->spi_data.pIocPg3 = (IOCPage3_t *) mem; + } + } + if (pIoc3) { pci_free_consistent(ioc->pcidev, iocpage3sz, pIoc3, ioc3_dma); pIoc3 = NULL; } - return rc; + return 0; } +static void +mpt_read_ioc_pg_1(MPT_ADAPTER *ioc) +{ + IOCPage1_t *pIoc1 = NULL; + CONFIGPARMS cfg; + ConfigPageHeader_t header; + dma_addr_t ioc1_dma; + int iocpage1sz = 0; + u32 tmp; + + /* Check the Coalescing Timeout in IOC Page 1 + */ + header.PageVersion = 0; + header.PageLength = 0; + header.PageNumber = 1; + header.PageType = MPI_CONFIG_PAGETYPE_IOC; + cfg.hdr = &header; + cfg.physAddr = -1; + cfg.pageAddr = 0; + cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; + cfg.dir = 0; + cfg.timeout = 0; + if (mpt_config(ioc, &cfg) != 0) + return; + + if (header.PageLength == 0) + return; + + /* Read Header good, alloc memory + */ + iocpage1sz = header.PageLength * 4; + pIoc1 = pci_alloc_consistent(ioc->pcidev, iocpage1sz, &ioc1_dma); + if (!pIoc1) + return; + + /* Read the Page and check coalescing timeout + */ + cfg.physAddr = ioc1_dma; + cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; + if (mpt_config(ioc, &cfg) == 0) { + + tmp = le32_to_cpu(pIoc1->Flags) & MPI_IOCPAGE1_REPLY_COALESCING; + if (tmp == MPI_IOCPAGE1_REPLY_COALESCING) { + tmp = le32_to_cpu(pIoc1->CoalescingTimeout); + + dprintk((MYIOC_s_INFO_FMT "Coalescing Enabled Timeout = %d\n", + ioc->name, tmp)); + + if (tmp > MPT_COALESCING_TIMEOUT) { + pIoc1->CoalescingTimeout = cpu_to_le32(MPT_COALESCING_TIMEOUT); + + /* Write NVRAM and current + */ + cfg.dir = 1; + cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT; + if (mpt_config(ioc, &cfg) == 0) { + dprintk((MYIOC_s_INFO_FMT "Reset Current Coalescing Timeout to = %d\n", + ioc->name, MPT_COALESCING_TIMEOUT)); + + cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM; + if (mpt_config(ioc, &cfg) == 0) { + dprintk((MYIOC_s_INFO_FMT "Reset NVRAM Coalescing Timeout to = %d\n", + ioc->name, MPT_COALESCING_TIMEOUT)); + } else { + dprintk((MYIOC_s_INFO_FMT "Reset NVRAM Coalescing Timeout Failed\n", + ioc->name)); + } + + } else { + dprintk((MYIOC_s_WARN_FMT "Reset of Current Coalescing Timeout Failed!\n", + ioc->name)); + } + } + + } else { + dprintk((MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name)); + } + } + + if (pIoc1) { + pci_free_consistent(ioc->pcidev, iocpage1sz, pIoc1, ioc1_dma); + pIoc1 = NULL; + } + + return; +} /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* @@ -4690,7 +4811,7 @@ */ in_isr = in_interrupt(); if (in_isr) { - dprintk((MYIOC_s_WARN_FMT "Config request not allowed in ISR context!\n", + dcprintk((MYIOC_s_WARN_FMT "Config request not allowed in ISR context!\n", ioc->name)); return -EPERM; } @@ -4698,7 +4819,7 @@ /* Get and Populate a free Frame */ if ((mf = mpt_get_msg_frame(mpt_base_index, ioc->id)) == NULL) { - dprintk((MYIOC_s_WARN_FMT "mpt_config: no msg frames!\n", + dcprintk((MYIOC_s_WARN_FMT "mpt_config: no msg frames!\n", ioc->name)); return -EAGAIN; } @@ -4731,7 +4852,7 @@ mpt_add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr); - dprintk((MYIOC_s_INFO_FMT "Sending Config request type %d, page %d and action %d\n", + dcprintk((MYIOC_s_INFO_FMT "Sending Config request type %d, page %d and action %d\n", ioc->name, pReq->Header.PageType, pReq->Header.PageNumber, pReq->Action)); /* Append pCfg pointer to end of mf @@ -4778,7 +4899,7 @@ { MPT_ADAPTER *ioc = (MPT_ADAPTER *) data; - dprintk((MYIOC_s_WARN_FMT "mpt_timer_expired! \n", ioc->name)); + dcprintk((MYIOC_s_WARN_FMT "mpt_timer_expired! \n", ioc->name)); /* Perform a FW reload */ if (mpt_HardResetHandler(ioc, NO_SLEEP) < 0) @@ -4788,7 +4909,7 @@ * Hard reset clean-up will wake up * process and free all resources. */ - dprintk((MYIOC_s_WARN_FMT "mpt_timer_expired complete!\n", ioc->name)); + dcprintk((MYIOC_s_WARN_FMT "mpt_timer_expired complete!\n", ioc->name)); return; } @@ -4829,7 +4950,7 @@ } else { CONFIGPARMS *pNext; - /* Search the configQ for internal commands. + /* Search the configQ for internal commands. * Flush the Q, and wake up all suspended threads. */ #if 1 @@ -5096,8 +5217,7 @@ */ if (isense_idx == ii) len += sprintf(buf+len, " Fusion MPT isense driver\n"); - } else - break; + } } MPT_PROC_READ_RETURN(buf,start,offset,request,eof,len); @@ -5774,6 +5894,7 @@ EXPORT_SYMBOL(mpt_stm_index); EXPORT_SYMBOL(mpt_HardResetHandler); EXPORT_SYMBOL(mpt_config); +EXPORT_SYMBOL(mpt_read_ioc_pg_3); EXPORT_SYMBOL(mpt_alloc_fw_memory); EXPORT_SYMBOL(mpt_free_fw_memory); @@ -5843,6 +5964,7 @@ fusion_exit(void) { MPT_ADAPTER *this; + struct pci_dev *pdev = NULL; dprintk((KERN_INFO MYNAM ": fusion_exit() called!\n")); @@ -5861,8 +5983,13 @@ this->active = 0; + pdev = (struct pci_dev *)this->pcidev; + mptscsih_sync_irq(pdev->irq); + /* Clear any lingering interrupt */ CHIPREG_WRITE32(&this->chip->IntStatus, 0); + + CHIPREG_READ32(&this->chip->IntStatus); Q_DEL_ITEM(this); mpt_adapter_dispose(this); diff -Nru a/drivers/message/fusion/mptbase.h b/drivers/message/fusion/mptbase.h --- a/drivers/message/fusion/mptbase.h Wed Jan 15 16:57:28 2003 +++ b/drivers/message/fusion/mptbase.h Wed Jan 15 16:57:28 2003 @@ -13,7 +13,7 @@ * (mailto:sjralston1@netscape.net) * (mailto:Pam.Delaney@lsil.com) * - * $Id: mptbase.h,v 1.136 2002/10/21 13:51:54 pdelaney Exp $ + * $Id: mptbase.h,v 1.141 2002/12/03 21:26:32 pdelaney Exp $ */ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* @@ -80,8 +80,8 @@ #define COPYRIGHT "Copyright (c) 1999-2002 " MODULEAUTHOR #endif -#define MPT_LINUX_VERSION_COMMON "2.03.00.02" -#define MPT_LINUX_PACKAGE_NAME "@(#)mptlinux-2.03.00.02" +#define MPT_LINUX_VERSION_COMMON "2.03.01.01" +#define MPT_LINUX_PACKAGE_NAME "@(#)mptlinux-2.03.01.01" #define WHAT_MAGIC_STRING "@" "(" "#" ")" #define show_mptmod_ver(s,ver) \ @@ -134,8 +134,10 @@ #define CAN_SLEEP 1 #define NO_SLEEP 0 -/* - * SCSI transfer rate defines. +#define MPT_COALESCING_TIMEOUT 0x10 + +/* + * SCSI transfer rate defines. */ #define MPT_ULTRA320 0x08 #define MPT_ULTRA160 0x09 @@ -524,7 +526,7 @@ #define MPT_SCSICFG_DV_PENDING 0x04 /* DV on this physical id pending */ #define MPT_SCSICFG_DV_NOT_DONE 0x08 /* DV has not been performed */ #define MPT_SCSICFG_BLK_NEGO 0x10 /* WriteSDP1 with WDTR and SDTR disabled */ - +#define MPT_SCSICFG_RELOAD_IOC_PG3 0x20 /* IOC Pg 3 data is obsolete */ /* Args passed to writeSDP1: */ #define MPT_SCSICFG_USE_NVRAM 0x01 /* WriteSDP1 using NVRAM */ #define MPT_SCSICFG_ALL_IDS 0x02 /* WriteSDP1 to all IDS */ @@ -756,6 +758,12 @@ #define nehprintk(x) #endif +#if defined(MPT_DEBUG_CONFIG) || defined(MPT_DEBUG) +#define dcprintk(x) printk x +#else +#define dcprintk(x) +#endif + #define MPT_INDEX_2_MFPTR(ioc,idx) \ (MPT_FRAME_HDR*)( (u8*)(ioc)->req_frames + (ioc)->req_sz * (idx) ) @@ -1009,6 +1017,7 @@ extern int mpt_config(MPT_ADAPTER *ioc, CONFIGPARMS *cfg); extern void *mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size, int *frags, int *alloc_sz); extern void mpt_free_fw_memory(MPT_ADAPTER *ioc, fw_image_t **alt_img); +extern int mpt_read_ioc_pg_3(MPT_ADAPTER *ioc); /* * Public data decl's... diff -Nru a/drivers/message/fusion/mptctl.c b/drivers/message/fusion/mptctl.c --- a/drivers/message/fusion/mptctl.c Wed Jan 15 16:57:28 2003 +++ b/drivers/message/fusion/mptctl.c Wed Jan 15 16:57:28 2003 @@ -34,7 +34,7 @@ * (mailto:sjralston1@netscape.net) * (mailto:Pam.Delaney@lsil.com) * - * $Id: mptctl.c,v 1.61 2002/10/17 20:15:57 pdelaney Exp $ + * $Id: mptctl.c,v 1.63 2002/12/03 21:26:33 pdelaney Exp $ */ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* @@ -2911,9 +2911,9 @@ #endif /*} sparc */ /* Register this device */ - if (misc_register(&mptctl_miscdev) == -1) { + err = misc_register(&mptctl_miscdev); + if (err < 0) { printk(KERN_ERR MYNAM ": Can't register misc device [minor=%d].\n", MPT_MINOR); - err = -EBUSY; goto out_fail; } printk(KERN_INFO MYNAM ": Registered with Fusion MPT base driver\n"); diff -Nru a/drivers/message/fusion/mptctl.h b/drivers/message/fusion/mptctl.h --- a/drivers/message/fusion/mptctl.h Wed Jan 15 16:57:29 2003 +++ b/drivers/message/fusion/mptctl.h Wed Jan 15 16:57:29 2003 @@ -20,7 +20,7 @@ * (mailto:sjralston1@netscape.net) * (mailto:Pam.Delaney@lsil.com) * - * $Id: mptctl.h,v 1.12 2002/10/17 20:15:58 pdelaney Exp $ + * $Id: mptctl.h,v 1.13 2002/12/03 21:26:33 pdelaney Exp $ */ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* diff -Nru a/drivers/message/fusion/mptscsih.c b/drivers/message/fusion/mptscsih.c --- a/drivers/message/fusion/mptscsih.c Wed Jan 15 16:57:29 2003 +++ b/drivers/message/fusion/mptscsih.c Wed Jan 15 16:57:29 2003 @@ -26,7 +26,7 @@ * (mailto:sjralston1@netscape.net) * (mailto:Pam.Delaney@lsil.com) * - * $Id: mptscsih.c,v 1.103 2002/10/17 20:15:59 pdelaney Exp $ + * $Id: mptscsih.c,v 1.104 2002/12/03 21:26:34 pdelaney Exp $ */ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* @@ -159,11 +159,9 @@ static int mptscsih_io_done(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf, MPT_FRAME_HDR *r); static void mptscsih_report_queue_full(Scsi_Cmnd *sc, SCSIIOReply_t *pScsiReply, SCSIIORequest_t *pScsiReq); static int mptscsih_taskmgmt_complete(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf, MPT_FRAME_HDR *r); -static int mptscsih_io_direction(Scsi_Cmnd *cmd); static int mptscsih_AddSGE(MPT_SCSI_HOST *hd, Scsi_Cmnd *SCpnt, SCSIIORequest_t *pReq, int req_idx); -static int mptscsih_getFreeChainBuffer(MPT_SCSI_HOST *hd, int *retIndex); static void mptscsih_freeChainBuffers(MPT_SCSI_HOST *hd, int req_idx); static int mptscsih_initChainBuffers (MPT_SCSI_HOST *hd, int init); static void copy_sense_data(Scsi_Cmnd *sc, MPT_SCSI_HOST *hd, MPT_FRAME_HDR *mf, SCSIIOReply_t *pScsiReply); @@ -274,6 +272,436 @@ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* + * Private inline routines... + */ +/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +/* 19991030 -sralston + * Return absolute SCSI data direction: + * 1 = _DATA_OUT + * 0 = _DIR_NONE + * -1 = _DATA_IN + * + * Changed: 3-20-2002 pdelaney to use the default data + * direction and the defines set up in the + * 2.4 kernel series + * 1 = _DATA_OUT changed to SCSI_DATA_WRITE (1) + * 0 = _DIR_NONE changed to SCSI_DATA_NONE (3) + * -1 = _DATA_IN changed to SCSI_DATA_READ (2) + * If the direction is unknown, fall through to original code. + * + * Mid-layer bug fix(): sg interface generates the wrong data + * direction in some cases. Set the direction the hard way for + * the most common commands. + */ +static inline int +mptscsih_io_direction(Scsi_Cmnd *cmd) +{ + switch (cmd->cmnd[0]) { + case WRITE_6: + case WRITE_10: + return SCSI_DATA_WRITE; + break; + case READ_6: + case READ_10: + return SCSI_DATA_READ; + break; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + if (cmd->sc_data_direction != SCSI_DATA_UNKNOWN) + return cmd->sc_data_direction; +#endif + switch (cmd->cmnd[0]) { + /* _DATA_OUT commands */ + case WRITE_6: case WRITE_10: case WRITE_12: + case WRITE_LONG: case WRITE_SAME: case WRITE_BUFFER: + case WRITE_VERIFY: case WRITE_VERIFY_12: + case COMPARE: case COPY: case COPY_VERIFY: + case SEARCH_EQUAL: case SEARCH_HIGH: case SEARCH_LOW: + case SEARCH_EQUAL_12: case SEARCH_HIGH_12: case SEARCH_LOW_12: + case MODE_SELECT: case MODE_SELECT_10: case LOG_SELECT: + case SEND_DIAGNOSTIC: case CHANGE_DEFINITION: case UPDATE_BLOCK: + case SET_WINDOW: case MEDIUM_SCAN: case SEND_VOLUME_TAG: + case REASSIGN_BLOCKS: + case PERSISTENT_RESERVE_OUT: + case 0xea: + case 0xa3: + return SCSI_DATA_WRITE; + + /* No data transfer commands */ + case SEEK_6: case SEEK_10: + case RESERVE: case RELEASE: + case TEST_UNIT_READY: + case START_STOP: + case ALLOW_MEDIUM_REMOVAL: + return SCSI_DATA_NONE; + + /* Conditional data transfer commands */ + case FORMAT_UNIT: + if (cmd->cmnd[1] & 0x10) /* FmtData (data out phase)? */ + return SCSI_DATA_WRITE; + else + return SCSI_DATA_NONE; + + case VERIFY: + if (cmd->cmnd[1] & 0x02) /* VERIFY:BYTCHK (data out phase)? */ + return SCSI_DATA_WRITE; + else + return SCSI_DATA_NONE; + + case RESERVE_10: + if (cmd->cmnd[1] & 0x03) /* RESERVE:{LongID|Extent} (data out phase)? */ + return SCSI_DATA_WRITE; + else + return SCSI_DATA_NONE; + + /* Must be data _IN! */ + default: + return SCSI_DATA_READ; + } +} /* mptscsih_io_direction() */ + +/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +/** + * mptscsih_add_sge - Place a simple SGE at address pAddr. + * @pAddr: virtual address for SGE + * @flagslength: SGE flags and data transfer length + * @dma_addr: Physical address + * + * This routine places a MPT request frame back on the MPT adapter's + * FreeQ. + */ +static inline void +mptscsih_add_sge(char *pAddr, u32 flagslength, dma_addr_t dma_addr) +{ + if (sizeof(dma_addr_t) == sizeof(u64)) { + SGESimple64_t *pSge = (SGESimple64_t *) pAddr; + u32 tmp = dma_addr & 0xFFFFFFFF; + + pSge->FlagsLength = cpu_to_le32(flagslength); + pSge->Address.Low = cpu_to_le32(tmp); + tmp = (u32) ((u64)dma_addr >> 32); + pSge->Address.High = cpu_to_le32(tmp); + + } else { + SGESimple32_t *pSge = (SGESimple32_t *) pAddr; + pSge->FlagsLength = cpu_to_le32(flagslength); + pSge->Address = cpu_to_le32(dma_addr); + } +} /* mptscsih_add_sge() */ + +/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +/** + * mptscsih_add_chain - Place a chain SGE at address pAddr. + * @pAddr: virtual address for SGE + * @next: nextChainOffset value (u32's) + * @length: length of next SGL segment + * @dma_addr: Physical address + * + * This routine places a MPT request frame back on the MPT adapter's + * FreeQ. + */ +static inline void +mptscsih_add_chain(char *pAddr, u8 next, u16 length, dma_addr_t dma_addr) +{ + if (sizeof(dma_addr_t) == sizeof(u64)) { + SGEChain64_t *pChain = (SGEChain64_t *) pAddr; + u32 tmp = dma_addr & 0xFFFFFFFF; + + pChain->Length = cpu_to_le16(length); + pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT | mpt_addr_size(); + + pChain->NextChainOffset = next; + + pChain->Address.Low = cpu_to_le32(tmp); + tmp = (u32) ((u64)dma_addr >> 32); + pChain->Address.High = cpu_to_le32(tmp); + } else { + SGEChain32_t *pChain = (SGEChain32_t *) pAddr; + pChain->Length = cpu_to_le16(length); + pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT | mpt_addr_size(); + pChain->NextChainOffset = next; + pChain->Address = cpu_to_le32(dma_addr); + } +} /* mptscsih_add_chain() */ + +/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +/* + * mptscsih_getFreeChainBuffes - Function to get a free chain + * from the MPT_SCSI_HOST FreeChainQ. + * @hd: Pointer to the MPT_SCSI_HOST instance + * @req_idx: Index of the SCSI IO request frame. (output) + * + * return SUCCESS or FAILED + */ +static inline int +mptscsih_getFreeChainBuffer(MPT_SCSI_HOST *hd, int *retIndex) +{ + MPT_FRAME_HDR *chainBuf = NULL; + unsigned long flags; + int rc = FAILED; + int chain_idx = MPT_HOST_NO_CHAIN; + + spin_lock_irqsave(&hd->ioc->FreeQlock, flags); + if (!Q_IS_EMPTY(&hd->FreeChainQ)) { + + int offset; + + chainBuf = hd->FreeChainQ.head; + Q_DEL_ITEM(&chainBuf->u.frame.linkage); + offset = (u8 *)chainBuf - (u8 *)hd->ChainBuffer; + chain_idx = offset / hd->ioc->req_sz; + rc = SUCCESS; + } + spin_unlock_irqrestore(&hd->ioc->FreeQlock, flags); + + + *retIndex = chain_idx; + + dsgprintk((MYIOC_s_INFO_FMT "getFreeChainBuffer (index %d), got buf=%p\n", + hd->ioc->name, *retIndex, chainBuf)); + + return rc; +} /* mptscsih_getFreeChainBuffer() */ + +/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +/* + * mptscsih_AddSGE - Add a SGE (plus chain buffers) to the + * SCSIIORequest_t Message Frame. + * @hd: Pointer to MPT_SCSI_HOST structure + * @SCpnt: Pointer to Scsi_Cmnd structure + * @pReq: Pointer to SCSIIORequest_t structure + * + * Returns ... + */ +static int +mptscsih_AddSGE(MPT_SCSI_HOST *hd, Scsi_Cmnd *SCpnt, + SCSIIORequest_t *pReq, int req_idx) +{ + char *psge; + char *chainSge; + struct scatterlist *sg; + int frm_sz; + int sges_left, sg_done; + int chain_idx = MPT_HOST_NO_CHAIN; + int sgeOffset; + int numSgeSlots, numSgeThisFrame; + u32 sgflags, sgdir, thisxfer = 0; + int chain_dma_off = 0; + int newIndex; + int ii; + dma_addr_t v2; + + sgdir = le32_to_cpu(pReq->Control) & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK; + if (sgdir == MPI_SCSIIO_CONTROL_WRITE) { + sgdir = MPT_TRANSFER_HOST_TO_IOC; + } else { + sgdir = MPT_TRANSFER_IOC_TO_HOST; + } + + psge = (char *) &pReq->SGL; + frm_sz = hd->ioc->req_sz; + + /* Map the data portion, if any. + * sges_left = 0 if no data transfer. + */ + sges_left = SCpnt->use_sg; + if (SCpnt->use_sg) { + sges_left = pci_map_sg(hd->ioc->pcidev, + (struct scatterlist *) SCpnt->request_buffer, + SCpnt->use_sg, + scsi_to_pci_dma_dir(SCpnt->sc_data_direction)); + } else if (SCpnt->request_bufflen) { + dma_addr_t buf_dma_addr; + scPrivate *my_priv; + + buf_dma_addr = pci_map_single(hd->ioc->pcidev, + SCpnt->request_buffer, + SCpnt->request_bufflen, + scsi_to_pci_dma_dir(SCpnt->sc_data_direction)); + + /* We hide it here for later unmap. */ + my_priv = (scPrivate *) &SCpnt->SCp; + my_priv->p1 = (void *)(ulong) buf_dma_addr; + + dsgprintk((MYIOC_s_INFO_FMT "SG: non-SG for %p, len=%d\n", + hd->ioc->name, SCpnt, SCpnt->request_bufflen)); + + mptscsih_add_sge((char *) &pReq->SGL, + 0xD1000000|MPT_SGE_FLAGS_ADDRESSING|sgdir|SCpnt->request_bufflen, + buf_dma_addr); + + return SUCCESS; + } + + /* Handle the SG case. + */ + sg = (struct scatterlist *) SCpnt->request_buffer; + sg_done = 0; + sgeOffset = sizeof(SCSIIORequest_t) - sizeof(SGE_IO_UNION); + chainSge = NULL; + + /* Prior to entering this loop - the following must be set + * current MF: sgeOffset (bytes) + * chainSge (Null if original MF is not a chain buffer) + * sg_done (num SGE done for this MF) + */ + +nextSGEset: + numSgeSlots = ((frm_sz - sgeOffset) / (sizeof(u32) + sizeof(dma_addr_t)) ); + numSgeThisFrame = (sges_left < numSgeSlots) ? sges_left : numSgeSlots; + + sgflags = MPT_SGE_FLAGS_SIMPLE_ELEMENT | MPT_SGE_FLAGS_ADDRESSING | sgdir; + + /* Get first (num - 1) SG elements + * Skip any SG entries with a length of 0 + * NOTE: at finish, sg and psge pointed to NEXT data/location positions + */ + for (ii=0; ii < (numSgeThisFrame-1); ii++) { + thisxfer = sg_dma_len(sg); + if (thisxfer == 0) { + sg ++; /* Get next SG element from the OS */ + sg_done++; + continue; + } + + v2 = sg_dma_address(sg); + mptscsih_add_sge(psge, sgflags | thisxfer, v2); + + sg++; /* Get next SG element from the OS */ + psge += (sizeof(u32) + sizeof(dma_addr_t)); + sgeOffset += (sizeof(u32) + sizeof(dma_addr_t)); + sg_done++; + } + + if (numSgeThisFrame == sges_left) { + /* Add last element, end of buffer and end of list flags. + */ + sgflags |= MPT_SGE_FLAGS_LAST_ELEMENT | + MPT_SGE_FLAGS_END_OF_BUFFER | + MPT_SGE_FLAGS_END_OF_LIST; + + /* Add last SGE and set termination flags. + * Note: Last SGE may have a length of 0 - which should be ok. + */ + thisxfer = sg_dma_len(sg); + + v2 = sg_dma_address(sg); + mptscsih_add_sge(psge, sgflags | thisxfer, v2); + /* + sg++; + psge += (sizeof(u32) + sizeof(dma_addr_t)); + */ + sgeOffset += (sizeof(u32) + sizeof(dma_addr_t)); + sg_done++; + + if (chainSge) { + /* The current buffer is a chain buffer, + * but there is not another one. + * Update the chain element + * Offset and Length fields. + */ + mptscsih_add_chain((char *)chainSge, 0, sgeOffset, hd->ChainBufferDMA + chain_dma_off); + } else { + /* The current buffer is the original MF + * and there is no Chain buffer. + */ + pReq->ChainOffset = 0; + } + } else { + /* At least one chain buffer is needed. + * Complete the first MF + * - last SGE element, set the LastElement bit + * - set ChainOffset (words) for orig MF + * (OR finish previous MF chain buffer) + * - update MFStructPtr ChainIndex + * - Populate chain element + * Also + * Loop until done. + */ + + dsgprintk((MYIOC_s_INFO_FMT "SG: Chain Required! sg done %d\n", + hd->ioc->name, sg_done)); + + /* Set LAST_ELEMENT flag for last non-chain element + * in the buffer. Since psge points at the NEXT + * SGE element, go back one SGE element, update the flags + * and reset the pointer. (Note: sgflags & thisxfer are already + * set properly). + */ + if (sg_done) { + u32 *ptmp = (u32 *) (psge - (sizeof(u32) + sizeof(dma_addr_t))); + sgflags = le32_to_cpu(*ptmp); + sgflags |= MPT_SGE_FLAGS_LAST_ELEMENT; + *ptmp = cpu_to_le32(sgflags); + } + + if (chainSge) { + /* The current buffer is a chain buffer. + * chainSge points to the previous Chain Element. + * Update its chain element Offset and Length (must + * include chain element size) fields. + * Old chain element is now complete. + */ + u8 nextChain = (u8) (sgeOffset >> 2); + sgeOffset += (sizeof(u32) + sizeof(dma_addr_t)); + mptscsih_add_chain((char *)chainSge, nextChain, sgeOffset, hd->ChainBufferDMA + chain_dma_off); + } else { + /* The original MF buffer requires a chain buffer - + * set the offset. + * Last element in this MF is a chain element. + */ + pReq->ChainOffset = (u8) (sgeOffset >> 2); + } + + sges_left -= sg_done; + + + /* NOTE: psge points to the beginning of the chain element + * in current buffer. Get a chain buffer. + */ + if ((mptscsih_getFreeChainBuffer(hd, &newIndex)) == FAILED) + return FAILED; + + /* Update the tracking arrays. + * If chainSge == NULL, update ReqToChain, else ChainToChain + */ + if (chainSge) { + hd->ChainToChain[chain_idx] = newIndex; + } else { + hd->ReqToChain[req_idx] = newIndex; + } + chain_idx = newIndex; + chain_dma_off = hd->ioc->req_sz * chain_idx; + + /* Populate the chainSGE for the current buffer. + * - Set chain buffer pointer to psge and fill + * out the Address and Flags fields. + */ + chainSge = (char *) psge; + dsgprintk((KERN_INFO " Current buff @ %p (index 0x%x)", + psge, req_idx)); + + /* Start the SGE for the next buffer + */ + psge = (char *) (hd->ChainBuffer + chain_dma_off); + sgeOffset = 0; + sg_done = 0; + + dsgprintk((KERN_INFO " Chain buff @ %p (index 0x%x)\n", + psge, chain_idx)); + + /* Start the SGE for the next buffer + */ + + goto nextSGEset; + } + + return SUCCESS; +} /* mptscsih_AddSGE() */ + +/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +/* * mptscsih_io_done - Main SCSI IO callback routine registered to * Fusion MPT (base) driver * @ioc: Pointer to MPT_ADAPTER structure @@ -294,7 +722,7 @@ MPT_SCSI_HOST *hd; SCSIIORequest_t *pScsiReq; SCSIIOReply_t *pScsiReply; -#ifndef MPT_SCSI_USE_NEW_EH +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0) unsigned long flags; #endif u16 req_idx; @@ -305,7 +733,6 @@ (mf >= MPT_INDEX_2_MFPTR(ioc, ioc->req_depth))) { printk(MYIOC_s_ERR_FMT "%s req frame ptr! (=%p)!\n", ioc->name, mf?"BAD":"NULL", (void *) mf); - /* return 1; CHECKME SteveR. Don't free. */ return 0; } @@ -411,12 +838,12 @@ #ifndef MPT_SCSI_USE_NEW_EH search_taskQ_for_cmd(sc, hd); #endif - /* Linux handles an unsolicited DID_RESET better + /* Linux handles an unsolicited DID_RESET better * than an unsolicited DID_ABORT. */ sc->result = DID_RESET << 16; - /* GEM Workaround. */ + /* GEM Workaround. */ if (hd->is_spi) mptscsih_no_negotiate(hd, sc->target); break; @@ -428,7 +855,7 @@ #endif sc->result = DID_RESET << 16; - /* GEM Workaround. */ + /* GEM Workaround. */ if (hd->is_spi) mptscsih_no_negotiate(hd, sc->target); break; @@ -506,7 +933,7 @@ ; } else if (scsi_state & MPI_SCSI_STATE_AUTOSENSE_VALID) { /* - * If running agains circa 200003dd 909 MPT f/w, + * If running against circa 200003dd 909 MPT f/w, * may get this (AUTOSENSE_VALID) for actual TASK_SET_FULL * (QUEUE_FULL) returned from device! --> get 0x0000?128 * and with SenseBytes set to 0. @@ -625,7 +1052,9 @@ hd->ScsiLookup[req_idx] = NULL; - sc->host_scribble = NULL; /* CHECKME! - Do we need to clear this??? */ +#ifndef MPT_SCSI_USE_NEW_EH + sc->host_scribble = NULL; +#endif MPT_HOST_LOCK(flags); sc->scsi_done(sc); /* Issue the command callback */ @@ -894,7 +1323,7 @@ int ii; int max = hd->ioc->req_depth; -#ifndef MPT_SCSI_USE_NEW_EH +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0) unsigned long flags; #endif @@ -911,7 +1340,7 @@ search_taskQ_for_cmd(SCpnt, hd); #endif - /* Search pendingQ, if found, + /* Search pendingQ, if found, * delete from Q. If found, do not decrement * queue_depth, command never posted. */ @@ -1061,7 +1490,7 @@ * of chain buffers to be allocated. * index = chain_idx * - * Calculate the number of chain buffers needed(plus 1) per I/O + * Calculate the number of chain buffers needed(plus 1) per I/O * then multiply the the maximum number of simultaneous cmds * * num_sge = num sge in request frame + last chain buffer @@ -1175,6 +1604,7 @@ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ static int BeenHereDoneThat = 0; +static char *info_kbuf = NULL; /* SCSI host fops start here... */ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ @@ -1263,9 +1693,10 @@ #if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0) tpnt->proc_dir = &proc_mpt_scsihost; #endif + tpnt->proc_info = mptscsih_proc_info; sh = scsi_register(tpnt, sizeof(MPT_SCSI_HOST)); if (sh != NULL) { - mptscsih_lock(this, flags); + spin_lock_irqsave(&this->FreeQlock, flags); sh->io_port = 0; sh->n_io_port = 0; sh->irq = 0; @@ -1326,7 +1757,7 @@ } else { numSGE = 1 + (scale - 1) * (this->facts.MaxChainDepth-1) + scale + (this->req_sz - 64) / (sizeof(dma_addr_t) + sizeof(u32)); - } + } if (numSGE < sh->sg_tablesize) { /* Reset this value */ @@ -1340,7 +1771,7 @@ */ scsi_set_pci_device(sh, this->pcidev); - mptscsih_unlock(this, flags); + spin_unlock_irqrestore(&this->FreeQlock, flags); hd = (MPT_SCSI_HOST *) sh->hostdata; hd->ioc = this; @@ -1503,12 +1934,25 @@ done: if (mpt_scsi_hosts > 0) register_reboot_notifier(&mptscsih_notifier); + else { + mpt_reset_deregister(ScsiDoneCtx); + dprintk((KERN_INFO MYNAM ": Deregistered for IOC reset notifications\n")); + + mpt_event_deregister(ScsiDoneCtx); + dprintk((KERN_INFO MYNAM ": Deregistered for IOC event notifications\n")); + + mpt_deregister(ScsiScanDvCtx); + mpt_deregister(ScsiTaskCtx); + mpt_deregister(ScsiDoneCtx); + + if (info_kbuf != NULL) + kfree(info_kbuf); + } return mpt_scsi_hosts; } /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ - static char *info_kbuf = NULL; /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /** * mptscsih_release - Unregister SCSI host from linux scsi mid-layer @@ -1731,7 +2175,7 @@ const char * mptscsih_info(struct Scsi_Host *SChost) { - MPT_SCSI_HOST *h; + MPT_SCSI_HOST *h = NULL; int size = 0; if (info_kbuf == NULL) @@ -1740,12 +2184,307 @@ h = (MPT_SCSI_HOST *)SChost->hostdata; info_kbuf[0] = '\0'; - mpt_print_ioc_summary(h->ioc, info_kbuf, &size, 0, 0); - info_kbuf[size-1] = '\0'; + if (h) { + mpt_print_ioc_summary(h->ioc, info_kbuf, &size, 0, 0); + info_kbuf[size-1] = '\0'; + } return info_kbuf; } +struct info_str { + char *buffer; + int length; + int offset; + int pos; +}; + +static void copy_mem_info(struct info_str *info, char *data, int len) +{ + if (info->pos + len > info->length) + len = info->length - info->pos; + + if (info->pos + len < info->offset) { + info->pos += len; + return; + } + + if (info->pos < info->offset) { + data += (info->offset - info->pos); + len -= (info->offset - info->pos); + } + + if (len > 0) { + memcpy(info->buffer + info->pos, data, len); + info->pos += len; + } +} + +static int copy_info(struct info_str *info, char *fmt, ...) +{ + va_list args; + char buf[81]; + int len; + + va_start(args, fmt); + len = vsprintf(buf, fmt, args); + va_end(args); + + copy_mem_info(info, buf, len); + return len; +} + +static int mptscsih_host_info(MPT_ADAPTER *ioc, char *pbuf, off_t offset, int len) +{ + struct info_str info; + + info.buffer = pbuf; + info.length = len; + info.offset = offset; + info.pos = 0; + + copy_info(&info, "%s: %s, ", ioc->name, ioc->prod_name); + copy_info(&info, "%s%08xh, ", MPT_FW_REV_MAGIC_ID_STRING, ioc->facts.FWVersion.Word); + copy_info(&info, "Ports=%d, ", ioc->facts.NumberOfPorts); + copy_info(&info, "MaxQ=%d\n", ioc->req_depth); + + return ((info.pos > info.offset) ? info.pos - info.offset : 0); +} + +struct mptscsih_usrcmd { + ulong target; + ulong lun; + ulong data; + ulong cmd; +}; + +#define UC_GET_SPEED 0x10 + +static void mptscsih_exec_user_cmd(MPT_ADAPTER *ioc, struct mptscsih_usrcmd *uc) +{ + CONFIGPARMS cfg; + dma_addr_t cfg_dma_addr = -1; + ConfigPageHeader_t header; + + dprintk(("exec_user_command: ioc %p cmd %ld target=%ld\n", + ioc, uc->cmd, uc->target)); + + switch (uc->cmd) { + case UC_GET_SPEED: + { + SCSIDevicePage0_t *pData = NULL; + + if (ioc->spi_data.sdp0length == 0) + return; + + pData = (SCSIDevicePage0_t *)pci_alloc_consistent(ioc->pcidev, + ioc->spi_data.sdp0length * 4, &cfg_dma_addr); + + if (pData == NULL) + return; + + header.PageVersion = ioc->spi_data.sdp0version; + header.PageLength = ioc->spi_data.sdp0length; + header.PageNumber = 0; + header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE; + + cfg.hdr = &header; + cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; + cfg.dir = 0; + cfg.pageAddr = (u32) uc->target; /* bus << 8 | target */ + cfg.physAddr = cfg_dma_addr; + + if (mpt_config(ioc, &cfg) == 0) { + u32 np = le32_to_cpu(pData->NegotiatedParameters); + u32 tmp = np & MPI_SCSIDEVPAGE0_NP_WIDE; + + printk("Target %d: %s;", + (u32) uc->target, + tmp ? "Wide" : "Narrow"); + + tmp = np & MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK; + if (tmp) { + u32 speed = 0; + printk(" Synchronous"); + tmp = (tmp >> 16); + printk(" (Offset=0x%x", tmp); + tmp = np & MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK; + tmp = (tmp >> 8); + printk(" Factor=0x%x)", tmp); + if (tmp <= MPT_ULTRA320) + speed=160; + else if (tmp <= MPT_ULTRA160) + speed=80; + else if (tmp <= MPT_ULTRA2) + speed=40; + else if (tmp <= MPT_ULTRA) + speed=20; + else if (tmp <= MPT_FAST) + speed=10; + else if (tmp <= MPT_SCSI) + speed=5; + + if (np & MPI_SCSIDEVPAGE0_NP_WIDE) + speed*=2; + + printk(" %dMB/sec\n", speed); + + } else + printk(" Asynchronous.\n"); + } else { + printk("failed\n" ); + } + + pci_free_consistent(ioc->pcidev, ioc->spi_data.sdp0length * 4, + pData, cfg_dma_addr); + } + break; + } +} + +#define is_digit(c) ((c) >= '0' && (c) <= '9') +#define digit_to_bin(c) ((c) - '0') +#define is_space(c) ((c) == ' ' || (c) == '\t') + +static int skip_spaces(char *ptr, int len) +{ + int cnt, c; + + for (cnt = len; cnt > 0 && (c = *ptr++) && is_space(c); cnt --); + + return (len - cnt); +} + +static int get_int_arg(char *ptr, int len, ulong *pv) +{ + int cnt, c; + ulong v; + for (v = 0, cnt = len; cnt > 0 && (c=*ptr++) && is_digit(c); cnt --) { + v = (v * 10) + digit_to_bin(c); + } + + if (pv) + *pv = v; + + return (len - cnt); +} + + +static int is_keyword(char *ptr, int len, char *verb) +{ + int verb_len = strlen(verb); + + if (len >= strlen(verb) && !memcmp(verb, ptr, verb_len)) + return verb_len; + else + return 0; +} + +#define SKIP_SPACES(min_spaces) \ + if ((arg_len = skip_spaces(ptr,len)) < (min_spaces)) \ + return -EINVAL; \ + ptr += arg_len; \ + len -= arg_len; + +#define GET_INT_ARG(v) \ + if (!(arg_len = get_int_arg(ptr,len, &(v)))) \ + return -EINVAL; \ + ptr += arg_len; \ + len -= arg_len; + +static int mptscsih_user_command(MPT_ADAPTER *ioc, char *buffer, int length) +{ + char *ptr = buffer; + struct mptscsih_usrcmd cmd, *uc = &cmd; + ulong target; + int arg_len; + int len = length; + + uc->target = uc->cmd = uc->lun = uc->data = 0; + + if ((len > 0) && (ptr[len -1] == '\n')) + --len; + + if ((arg_len = is_keyword(ptr, len, "getspeed")) != 0) + uc->cmd = UC_GET_SPEED; + else + arg_len = 0; + + dprintk(("user_command: arg_len=%d, cmd=%ld\n", arg_len, uc->cmd)); + + if (!arg_len) + return -EINVAL; + + ptr += arg_len; + len -= arg_len; + + switch(uc->cmd) { + case UC_GET_SPEED: + SKIP_SPACES(1); + GET_INT_ARG(target); + uc->target = target; + break; + } + + dprintk(("user_command: target=%ld len=%d\n", uc->target, len)); + + if (len) + return -EINVAL; + else { + /* process this command ... + */ + mptscsih_exec_user_cmd(ioc, uc); + } + /* Not yet implemented */ + return length; +} + +/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ +/** + * mptscsih_proc_info - Return information about MPT adapter + * + * (linux Scsi_Host_Template.info routine) + * + * buffer: if write, user data; if read, buffer for user + * length: if write, return length; + * offset: if write, 0; if read, the current offset into the buffer from + * the previous read. + * hostno: scsi host number + * func: if write = 1; if read = 0 + */ +int mptscsih_proc_info(char *buffer, char **start, off_t offset, + int length, int hostno, int func) +{ + MPT_ADAPTER *ioc = NULL; + MPT_SCSI_HOST *hd = NULL; + int size = 0; + + dprintk(("Called mptscsih_proc_info: hostno=%d, func=%d\n", hostno, func)); + dprintk(("buffer %p, start=%p (%p) offset=%ld length = %d\n", + buffer, start, *start, offset, length)); + + for (ioc = mpt_adapter_find_first(); ioc != NULL; ioc = mpt_adapter_find_next(ioc)) { + if ((ioc->sh) && (ioc->sh->host_no == hostno)) { + hd = (MPT_SCSI_HOST *)ioc->sh->hostdata; + break; + } + } + if ((ioc == NULL) || (ioc->sh == NULL) || (hd == NULL)) + return 0; + + if (func) { + size = mptscsih_user_command(ioc, buffer, length); + } else { + if (start) + *start = buffer; + + size = mptscsih_host_info(ioc, buffer, offset, length); + } + + return size; +} + + /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ static int max_qd = 1; #if 0 @@ -1777,16 +2516,16 @@ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* * mptscsih_put_msgframe - Wrapper routine to post message frame to F/W. - * @context: Call back context (ScsiDoneCtx, ScsiScanDvCtx) - * @id: IOC id number - * @mf: Pointer to message frame + * @context: Call back context (ScsiDoneCtx, ScsiScanDvCtx) + * @id: IOC id number + * @mf: Pointer to message frame * - * Handles the call to mptbase for posting request and queue depth + * Handles the call to mptbase for posting request and queue depth * tracking. * * Returns none. */ -static void +static inline void mptscsih_put_msgframe(int context, int id, MPT_FRAME_HDR *mf) { /* Main banana... */ @@ -1973,12 +2712,11 @@ /* * Write SCSI CDB into the message + * Should write from cmd_len up to 16, but skip for performance reasons. */ cmd_len = SCpnt->cmd_len; for (ii=0; ii < cmd_len; ii++) pScsiReq->CDB[ii] = SCpnt->cmnd[ii]; - for (ii=cmd_len; ii < 16; ii++) - pScsiReq->CDB[ii] = 0; /* DataLength */ pScsiReq->DataLength = cpu_to_le32(datalen); @@ -1993,7 +2731,7 @@ rc = SUCCESS; if (datalen == 0) { /* Add a NULL SGE */ - mpt_add_sge((char *)&pScsiReq->SGL, MPT_SGE_FLAGS_SSIMPLE_READ | 0, + mptscsih_add_sge((char *)&pScsiReq->SGL, MPT_SGE_FLAGS_SSIMPLE_READ | 0, (dma_addr_t) -1); } else { /* Add a 32 or 64 bit SGE */ @@ -2057,24 +2795,25 @@ } #ifndef MPTSCSIH_DISABLE_DOMAIN_VALIDATION - if ((dvStatus & MPT_SCSICFG_NEED_DV) || hd->ioc->spi_data.forceDv) { + if ((dvStatus & MPT_SCSICFG_NEED_DV) || + (hd->ioc->spi_data.forceDv & MPT_SCSICFG_NEED_DV)) { unsigned long lflags; /* Schedule DV if necessary */ spin_lock_irqsave(&dvtaskQ_lock, lflags); if (!dvtaskQ_active) { dvtaskQ_active = 1; spin_unlock_irqrestore(&dvtaskQ_lock, lflags); - MPT_INIT_WORK(&mptscsih_dvTask, mptscsih_domainValidation, (void *) hd); + MPT_INIT_WORK(&mptscsih_dvTask, mptscsih_domainValidation, (void *) hd); SCHEDULE_TASK(&mptscsih_dvTask); } else { spin_unlock_irqrestore(&dvtaskQ_lock, lflags); } - hd->ioc->spi_data.forceDv = 0; + hd->ioc->spi_data.forceDv &= ~MPT_SCSICFG_NEED_DV; } /* Trying to do DV to this target, extend timeout. - * Wait to issue intil flag is clear + * Wait to issue intil flag is clear */ if (dvStatus & MPT_SCSICFG_DV_PENDING) { mod_timer(&SCpnt->eh_timeout, jiffies + 40 * HZ); @@ -2153,283 +2892,6 @@ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* - * mptscsih_AddSGE - Add a SGE (plus chain buffers) to the - * SCSIIORequest_t Message Frame. - * @hd: Pointer to MPT_SCSI_HOST structure - * @SCpnt: Pointer to Scsi_Cmnd structure - * @pReq: Pointer to SCSIIORequest_t structure - * - * Returns ... - */ -static int -mptscsih_AddSGE(MPT_SCSI_HOST *hd, Scsi_Cmnd *SCpnt, - SCSIIORequest_t *pReq, int req_idx) -{ - char *psge; - char *chainSge; - struct scatterlist *sg; - int frm_sz; - int sges_left, sg_done; - int chain_idx = MPT_HOST_NO_CHAIN; - int sgeOffset; - int numSgeSlots, numSgeThisFrame; - u32 sgflags, sgdir, thisxfer = 0; - int chain_dma_off = 0; - int newIndex; - int ii; - dma_addr_t v2; - - sgdir = le32_to_cpu(pReq->Control) & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK; - if (sgdir == MPI_SCSIIO_CONTROL_WRITE) { - sgdir = MPT_TRANSFER_HOST_TO_IOC; - } else { - sgdir = MPT_TRANSFER_IOC_TO_HOST; - } - - psge = (char *) &pReq->SGL; - frm_sz = hd->ioc->req_sz; - - /* Map the data portion, if any. - * sges_left = 0 if no data transfer. - */ - sges_left = SCpnt->use_sg; - if (SCpnt->use_sg) { - sges_left = pci_map_sg(hd->ioc->pcidev, - (struct scatterlist *) SCpnt->request_buffer, - SCpnt->use_sg, - scsi_to_pci_dma_dir(SCpnt->sc_data_direction)); - } else if (SCpnt->request_bufflen) { - dma_addr_t buf_dma_addr; - scPrivate *my_priv; - - buf_dma_addr = pci_map_single(hd->ioc->pcidev, - SCpnt->request_buffer, - SCpnt->request_bufflen, - scsi_to_pci_dma_dir(SCpnt->sc_data_direction)); - - /* We hide it here for later unmap. */ - my_priv = (scPrivate *) &SCpnt->SCp; - my_priv->p1 = (void *)(ulong) buf_dma_addr; - - dsgprintk((MYIOC_s_INFO_FMT "SG: non-SG for %p, len=%d\n", - hd->ioc->name, SCpnt, SCpnt->request_bufflen)); - - mpt_add_sge((char *) &pReq->SGL, - 0xD1000000|MPT_SGE_FLAGS_ADDRESSING|sgdir|SCpnt->request_bufflen, - buf_dma_addr); - - return SUCCESS; - } - - /* Handle the SG case. - */ - sg = (struct scatterlist *) SCpnt->request_buffer; - sg_done = 0; - sgeOffset = sizeof(SCSIIORequest_t) - sizeof(SGE_IO_UNION); - chainSge = NULL; - - /* Prior to entering this loop - the following must be set - * current MF: sgeOffset (bytes) - * chainSge (Null if original MF is not a chain buffer) - * sg_done (num SGE done for this MF) - */ - -nextSGEset: - numSgeSlots = ((frm_sz - sgeOffset) / (sizeof(u32) + sizeof(dma_addr_t)) ); - numSgeThisFrame = (sges_left < numSgeSlots) ? sges_left : numSgeSlots; - - sgflags = MPT_SGE_FLAGS_SIMPLE_ELEMENT | MPT_SGE_FLAGS_ADDRESSING | sgdir; - - /* Get first (num - 1) SG elements - * Skip any SG entries with a length of 0 - * NOTE: at finish, sg and psge pointed to NEXT data/location positions - */ - for (ii=0; ii < (numSgeThisFrame-1); ii++) { - thisxfer = sg_dma_len(sg); - if (thisxfer == 0) { - sg ++; /* Get next SG element from the OS */ - sg_done++; - continue; - } - - v2 = sg_dma_address(sg); - mpt_add_sge(psge, sgflags | thisxfer, v2); - - sg++; /* Get next SG element from the OS */ - psge += (sizeof(u32) + sizeof(dma_addr_t)); - sgeOffset += (sizeof(u32) + sizeof(dma_addr_t)); - sg_done++; - } - - if (numSgeThisFrame == sges_left) { - /* Add last element, end of buffer and end of list flags. - */ - sgflags |= MPT_SGE_FLAGS_LAST_ELEMENT | - MPT_SGE_FLAGS_END_OF_BUFFER | - MPT_SGE_FLAGS_END_OF_LIST; - - /* Add last SGE and set termination flags. - * Note: Last SGE may have a length of 0 - which should be ok. - */ - thisxfer = sg_dma_len(sg); - - v2 = sg_dma_address(sg); - mpt_add_sge(psge, sgflags | thisxfer, v2); - /* - sg++; - psge += (sizeof(u32) + sizeof(dma_addr_t)); - */ - sgeOffset += (sizeof(u32) + sizeof(dma_addr_t)); - sg_done++; - - if (chainSge) { - /* The current buffer is a chain buffer, - * but there is not another one. - * Update the chain element - * Offset and Length fields. - */ - mpt_add_chain((char *)chainSge, 0, sgeOffset, hd->ChainBufferDMA + chain_dma_off); - } else { - /* The current buffer is the original MF - * and there is no Chain buffer. - */ - pReq->ChainOffset = 0; - } - } else { - /* At least one chain buffer is needed. - * Complete the first MF - * - last SGE element, set the LastElement bit - * - set ChainOffset (words) for orig MF - * (OR finish previous MF chain buffer) - * - update MFStructPtr ChainIndex - * - Populate chain element - * Also - * Loop until done. - */ - - dsgprintk((MYIOC_s_INFO_FMT "SG: Chain Required! sg done %d\n", - hd->ioc->name, sg_done)); - - /* Set LAST_ELEMENT flag for last non-chain element - * in the buffer. Since psge points at the NEXT - * SGE element, go back one SGE element, update the flags - * and reset the pointer. (Note: sgflags & thisxfer are already - * set properly). - */ - if (sg_done) { - u32 *ptmp = (u32 *) (psge - (sizeof(u32) + sizeof(dma_addr_t))); - sgflags = le32_to_cpu(*ptmp); - sgflags |= MPT_SGE_FLAGS_LAST_ELEMENT; - *ptmp = cpu_to_le32(sgflags); - } - - if (chainSge) { - /* The current buffer is a chain buffer. - * chainSge points to the previous Chain Element. - * Update its chain element Offset and Length (must - * include chain element size) fields. - * Old chain element is now complete. - */ - u8 nextChain = (u8) (sgeOffset >> 2); - sgeOffset += (sizeof(u32) + sizeof(dma_addr_t)); - mpt_add_chain((char *)chainSge, nextChain, sgeOffset, hd->ChainBufferDMA + chain_dma_off); - } else { - /* The original MF buffer requires a chain buffer - - * set the offset. - * Last element in this MF is a chain element. - */ - pReq->ChainOffset = (u8) (sgeOffset >> 2); - } - - sges_left -= sg_done; - - - /* NOTE: psge points to the beginning of the chain element - * in current buffer. Get a chain buffer. - */ - if ((mptscsih_getFreeChainBuffer(hd, &newIndex)) == FAILED) - return FAILED; - - /* Update the tracking arrays. - * If chainSge == NULL, update ReqToChain, else ChainToChain - */ - if (chainSge) { - hd->ChainToChain[chain_idx] = newIndex; - } else { - hd->ReqToChain[req_idx] = newIndex; - } - chain_idx = newIndex; - chain_dma_off = hd->ioc->req_sz * chain_idx; - - /* Populate the chainSGE for the current buffer. - * - Set chain buffer pointer to psge and fill - * out the Address and Flags fields. - */ - chainSge = (char *) psge; - dsgprintk((KERN_INFO " Current buff @ %p (index 0x%x)", - psge, req_idx)); - - /* Start the SGE for the next buffer - */ - psge = (char *) (hd->ChainBuffer + chain_dma_off); - sgeOffset = 0; - sg_done = 0; - - dsgprintk((KERN_INFO " Chain buff @ %p (index 0x%x)\n", - psge, chain_idx)); - - /* Start the SGE for the next buffer - */ - - goto nextSGEset; - } - - return SUCCESS; -} - -/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ -/* - * mptscsih_getFreeChainBuffes - Function to get a free chain - * from the MPT_SCSI_HOST FreeChainQ. - * @hd: Pointer to the MPT_SCSI_HOST instance - * @req_idx: Index of the SCSI IO request frame. (output) - * - * return SUCCESS or FAILED - */ -static int -mptscsih_getFreeChainBuffer(MPT_SCSI_HOST *hd, int *retIndex) -{ - MPT_FRAME_HDR *chainBuf = NULL; - unsigned long flags; - int rc = FAILED; - int chain_idx = MPT_HOST_NO_CHAIN; - - //spin_lock_irqsave(&hd->FreeChainQlock, flags); - spin_lock_irqsave(&hd->ioc->FreeQlock, flags); - if (!Q_IS_EMPTY(&hd->FreeChainQ)) { - - int offset; - - chainBuf = hd->FreeChainQ.head; - Q_DEL_ITEM(&chainBuf->u.frame.linkage); - offset = (u8 *)chainBuf - (u8 *)hd->ChainBuffer; - chain_idx = offset / hd->ioc->req_sz; - rc = SUCCESS; - } - //spin_unlock_irqrestore(&hd->FreeChainQlock, flags); - spin_unlock_irqrestore(&hd->ioc->FreeQlock, flags); - - - *retIndex = chain_idx; - - dsgprintk((MYIOC_s_INFO_FMT "getFreeChainBuffer (index %d), got buf=%p\n", - hd->ioc->name, *retIndex, chainBuf)); - - return rc; -} - -/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ -/* * mptscsih_freeChainBuffers - Function to free chain buffers associated * with a SCSI IO request * @hd: Pointer to the MPT_SCSI_HOST instance @@ -2547,8 +3009,8 @@ #ifdef MPT_DEBUG_RESET if ((ioc_raw_state & MPI_IOC_STATE_MASK) != MPI_IOC_STATE_OPERATIONAL) { - printk(MYIOC_s_WARN_FMT - "TM Handler: IOC Not operational! state 0x%x Calling HardResetHandler\n", + printk(MYIOC_s_WARN_FMT + "TM Handler: IOC Not operational! state 0x%x Calling HardResetHandler\n", hd->ioc->name, ioc_raw_state); } #endif @@ -2765,7 +3227,7 @@ hd->abortSCpnt = SCpnt; if (mptscsih_TMHandler(hd, MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK, - SCpnt->target, SCpnt->lun, ctx2abort, NO_SLEEP) + SCpnt->target, SCpnt->lun, ctx2abort, NO_SLEEP) < 0) { /* The TM request failed and the subsequent FW-reload failed! @@ -2830,7 +3292,7 @@ } if (mptscsih_TMHandler(hd, MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET, - SCpnt->target, 0, 0, NO_SLEEP) + SCpnt->target, 0, 0, NO_SLEEP) < 0){ /* The TM request failed and the subsequent FW-reload failed! * Fatal error case. @@ -2889,13 +3351,13 @@ /* We are now ready to execute the task management request. */ if (mptscsih_TMHandler(hd, MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS, - 0, 0, 0, NO_SLEEP) + 0, 0, 0, NO_SLEEP) < 0){ /* The TM request failed and the subsequent FW-reload failed! * Fatal error case. */ - printk(MYIOC_s_WARN_FMT + printk(MYIOC_s_WARN_FMT "Error processing TaskMgmt request (sc=%p)\n", hd->ioc->name, SCpnt); hd->tmPending = 0; @@ -2941,8 +3403,8 @@ if (mpt_HardResetHandler(hd->ioc, NO_SLEEP) < 0){ status = FAILED; } else { - /* Make sure TM pending is cleared and TM state is set to - * NONE. + /* Make sure TM pending is cleared and TM state is set to + * NONE. */ hd->tmPending = 0; hd->tmState = TM_STATE_NONE; @@ -2958,7 +3420,7 @@ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /** - * mptscsih_tm_pending_wait - wait for pending task management request to + * mptscsih_tm_pending_wait - wait for pending task management request to * complete. * @hd: Pointer to MPT host structure. * @@ -3114,7 +3576,7 @@ * (bottom/unused portion of) MPT request frame. */ ptaskfoo = (struct mpt_work_struct *) &mptscsih_ptaskfoo; - MPT_INIT_WORK(&mptscsih_ptaskfoo, mptscsih_taskmgmt_bh, (void *) SCpnt); + MPT_INIT_WORK(&mptscsih_ptaskfoo, mptscsih_taskmgmt_bh, (void *) SCpnt); SCHEDULE_TASK(ptaskfoo); } else { @@ -3245,7 +3707,7 @@ * (bottom/unused portion of) MPT request frame. */ ptaskfoo = (struct mpt_work_struct *) &mptscsih_ptaskfoo; - MPT_INIT_WORK(&mptscsih_ptaskfoo, mptscsih_taskmgmt_bh, (void *) SCpnt); + MPT_INIT_WORK(&mptscsih_ptaskfoo, mptscsih_taskmgmt_bh, (void *) SCpnt); SCHEDULE_TASK(ptaskfoo); } else { @@ -3599,7 +4061,7 @@ * Called once per device the bus scan. Use it to force the queue_depth * member to 1 if a device does not support Q tags. */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,44) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52) int mptscsih_slave_configure(Scsi_Device *device) { @@ -3614,15 +4076,21 @@ if (!device->tagged_supported || !(pTarget->tflags & MPT_TARGET_FLAGS_Q_YES)) { scsi_adjust_queue_depth(device, 0, 1); + + } else if ((pTarget->tflags & MPT_TARGET_FLAGS_VALID_INQUIRY) + && (pTarget->inq_data[0] & 0x1f) == 0x00 + && (pTarget->minSyncFactor <= MPT_ULTRA160 || !hd->is_spi)) { + scsi_adjust_queue_depth(device, MSG_SIMPLE_TAG, + MPT_SCSI_CMD_PER_DEV_HIGH); } else { - scsi_adjust_queue_depth(device, MSG_SIMPLE_TAG, - device->host->can_queue >> 1); + scsi_adjust_queue_depth(device, MSG_SIMPLE_TAG, + MPT_SCSI_CMD_PER_DEV_LOW); } } } return 0; } -#else /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,44) */ +#else /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52) */ void mptscsih_select_queue_depths(struct Scsi_Host *sh, Scsi_Device *sdList) { @@ -3648,113 +4116,32 @@ for (ii=0; ii < max; ii++) { pTarget = hd->Targets[ii]; - if (pTarget && !(pTarget->tflags & MPT_TARGET_FLAGS_Q_YES)) { + if (pTarget == NULL) { + continue; + } + if (!(pTarget->tflags & MPT_TARGET_FLAGS_Q_YES)) { device->queue_depth = 1; + } else if ((pTarget->tflags & MPT_TARGET_FLAGS_VALID_INQUIRY) + && (pTarget->inq_data[0] & 0x1f) == 0x00 + && (pTarget->minSyncFactor <= MPT_ULTRA160 || !hd->is_spi)) { + device->queue_depth = MPT_SCSI_CMD_PER_DEV_HIGH; + } else { + device->queue_depth = MPT_SCSI_CMD_PER_DEV_LOW; } + dprintk((MYIOC_s_INFO_FMT + "target = %d, sync factor = %#x, queue depth = %d\n", + hd->ioc->name, pTarget->target_id, + pTarget->minSyncFactor, device->queue_depth)); } } } } -#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,44) */ +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52) */ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* * Private routines... */ -/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ -/* 19991030 -sralston - * Return absolute SCSI data direction: - * 1 = _DATA_OUT - * 0 = _DIR_NONE - * -1 = _DATA_IN - * - * Changed: 3-20-2002 pdelaney to use the default data - * direction and the defines set up in the - * 2.4 kernel series - * 1 = _DATA_OUT changed to SCSI_DATA_WRITE (1) - * 0 = _DIR_NONE changed to SCSI_DATA_NONE (3) - * -1 = _DATA_IN changed to SCSI_DATA_READ (2) - * If the direction is unknown, fall through to original code. - * - * Mid-layer bug fix(): sg interface generates the wrong data - * direction in some cases. Set the direction the hard way for - * the most common commands. - */ -static int -mptscsih_io_direction(Scsi_Cmnd *cmd) -{ - switch (cmd->cmnd[0]) { - case WRITE_6: - case WRITE_10: - return SCSI_DATA_WRITE; - break; - case READ_6: - case READ_10: - return SCSI_DATA_READ; - break; - } - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) - if (cmd->sc_data_direction != SCSI_DATA_UNKNOWN) - return cmd->sc_data_direction; -#endif - switch (cmd->cmnd[0]) { - /* _DATA_OUT commands */ - case WRITE_6: case WRITE_10: case WRITE_12: - case WRITE_LONG: case WRITE_SAME: case WRITE_BUFFER: - case WRITE_VERIFY: case WRITE_VERIFY_12: - case COMPARE: case COPY: case COPY_VERIFY: - case SEARCH_EQUAL: case SEARCH_HIGH: case SEARCH_LOW: - case SEARCH_EQUAL_12: case SEARCH_HIGH_12: case SEARCH_LOW_12: - case MODE_SELECT: case MODE_SELECT_10: case LOG_SELECT: - case SEND_DIAGNOSTIC: case CHANGE_DEFINITION: case UPDATE_BLOCK: - case SET_WINDOW: case MEDIUM_SCAN: case SEND_VOLUME_TAG: - case REASSIGN_BLOCKS: - case PERSISTENT_RESERVE_OUT: - case 0xea: - case 0xa3: - return SCSI_DATA_WRITE; - - /* No data transfer commands */ - case SEEK_6: case SEEK_10: - case RESERVE: case RELEASE: - case TEST_UNIT_READY: - case START_STOP: - case ALLOW_MEDIUM_REMOVAL: - return SCSI_DATA_NONE; - - /* Conditional data transfer commands */ - case FORMAT_UNIT: - if (cmd->cmnd[1] & 0x10) /* FmtData (data out phase)? */ - return SCSI_DATA_WRITE; - else - return SCSI_DATA_NONE; - - case VERIFY: - if (cmd->cmnd[1] & 0x02) /* VERIFY:BYTCHK (data out phase)? */ - return SCSI_DATA_WRITE; - else - return SCSI_DATA_NONE; - - case RESERVE_10: - if (cmd->cmnd[1] & 0x03) /* RESERVE:{LongID|Extent} (data out phase)? */ - return SCSI_DATA_WRITE; - else - return SCSI_DATA_NONE; - -#if 0 - case REZERO_UNIT: /* (or REWIND) */ - case SPACE: - case ERASE: case ERASE_10: - case SYNCHRONIZE_CACHE: - case LOCK_UNLOCK_CACHE: -#endif - - /* Must be data _IN! */ - default: - return SCSI_DATA_READ; - } -} /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* Utility function to copy sense data from the scsi_cmnd buffer @@ -3803,7 +4190,7 @@ #ifdef ABORT_FIX if (sz >= SCSI_STD_SENSE_BYTES) { - if ((sense_data[02] == ABORTED_COMMAND) && + if ((sense_data[02] == ABORTED_COMMAND) && (sense_data[12] == 0x47) && (sense_data[13] == 0x00)){ target->numAborts++; if ((target->raidVolume == 0) && (target->numAborts > 5)) { @@ -3896,7 +4283,7 @@ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* Search the pendingQ for a command with specific index. - * If found, delete and return mf pointer + * If found, delete and return mf pointer * If not found, return NULL */ static MPT_FRAME_HDR * @@ -4126,6 +4513,13 @@ dtmprintk((MYIOC_s_WARN_FMT "Post-Reset handling complete.\n", ioc->name)); + + + /* 8. Set flag to force DV and re-read IOC Page 3 + */ + ioc->spi_data.forceDv = MPT_SCSICFG_NEED_DV | MPT_SCSICFG_RELOAD_IOC_PG3; + ddvtprintk(("Set reload IOC Pg3 Flag\n")); + } return 1; /* currently means nothing really */ @@ -4172,7 +4566,7 @@ case MPI_EVENT_INTEGRATED_RAID: /* 0B */ #ifndef MPTSCSIH_DISABLE_DOMAIN_VALIDATION - /* negoNvram set to 0 if DV enabled and to USE_NVRAM if + /* negoNvram set to 0 if DV enabled and to USE_NVRAM if * if DV disabled. Need to check for target mode. */ hd = NULL; @@ -4188,11 +4582,12 @@ reason = (le32_to_cpu(pEvReply->Data[0]) & 0x00FF0000) >> 16; if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) { - /* New or replaced disk. + /* New or replaced disk. * Set DV flag and schedule DV. */ pSpi = &ioc->spi_data; physDiskNum = (le32_to_cpu(pEvReply->Data[0]) & 0xFF000000) >> 24; + ddvtprintk(("DV requested for phys disk id %d\n", physDiskNum)); if (pSpi->pIocPg3) { pPDisk = pSpi->pIocPg3->PhysDisk; numPDisk =pSpi->pIocPg3->NumPhysDisks; @@ -4207,6 +4602,16 @@ pPDisk++; numPDisk--; } + + if (numPDisk == 0) { + /* The physical disk that needs DV was not found + * in the stored IOC Page 3. The driver must reload + * this page. DV routine will set the NEED_DV flag for + * all phys disks that have DV_NOT_DONE set. + */ + pSpi->forceDv = MPT_SCSICFG_NEED_DV | MPT_SCSICFG_RELOAD_IOC_PG3; + ddvtprintk(("phys disk %d not found. Setting reload IOC Pg3 Flag\n", physDiskNum)); + } } } } @@ -4670,7 +5075,7 @@ if (ioop->cdbPtr == NULL) { return 0; } else if ((ioop->cdbPtr[0] == CMD_TestUnitReady) || - (ioop->cdbPtr[0] == CMD_ReadCapacity) || + (ioop->cdbPtr[0] == CMD_ReadCapacity) || (ioop->cdbPtr[0] == 0x43)) { return 0; } @@ -4794,7 +5199,7 @@ } if (vdev && data) { - if ((!(vdev->tflags & MPT_TARGET_FLAGS_VALID_INQUIRY)) || + if ((!(vdev->tflags & MPT_TARGET_FLAGS_VALID_INQUIRY)) || ((dlen > 56) && (!(vdev->tflags & MPT_TARGET_FLAGS_VALID_56)))) { /* Copy the inquiry data - if we haven't yet. @@ -4877,7 +5282,7 @@ factor = MPT_ULTRA320; /* If RAID, never disable QAS - * else if non RAID, do not disable + * else if non RAID, do not disable * QAS if bit 1 is set * bit 1 QAS support, non-raid only * bit 0 IU support @@ -5000,8 +5405,8 @@ #endif /* If DV disabled (negoNvram set to USE_NVARM) or if not LUN 0, return. - * Else set the NEED_DV flag after Read Capacity Issued (disks) - * or Mode Sense (cdroms). + * Else set the NEED_DV flag after Read Capacity Issued (disks) + * or Mode Sense (cdroms). * * Tapes, initTarget will set this flag on completion of Inquiry command. * Called only if DV_NOT_DONE flag is set @@ -5037,7 +5442,7 @@ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* - * If no Target, bus reset on 1st I/O. Set the flag to + * If no Target, bus reset on 1st I/O. Set the flag to * prevent any future negotiations to this device. */ static void mptscsih_no_negotiate(MPT_SCSI_HOST *hd, int target_id) @@ -5286,9 +5691,9 @@ pData->Reserved = 0; pData->Configuration = cpu_to_le32(configuration); - dprintk((MYIOC_s_INFO_FMT + dprintk((MYIOC_s_INFO_FMT "write SDP1: id %d pgaddr 0x%x req 0x%x config 0x%x\n", - ioc->name, id, (id | (bus<<8)), + ioc->name, id, (id | (bus<<8)), requested, configuration)); mptscsih_put_msgframe(ScsiDoneCtx, ioc->id, mf); @@ -5327,8 +5732,8 @@ /* Because we have reset the IOC, no TM requests can be * pending. So let's make sure the tmPending flag is reset. */ - nehprintk((KERN_WARNING MYNAM - ": %s: mptscsih_taskmgmt_timeout\n", + nehprintk((KERN_WARNING MYNAM + ": %s: mptscsih_taskmgmt_timeout\n", hd->ioc->name)); hd->tmPending = 0; } @@ -5566,7 +5971,7 @@ if (hd->tmPending) { spin_unlock_irqrestore(&hd->ioc->FreeQlock, flags); return; - } else + } else hd->tmPending = 1; spin_unlock_irqrestore(&hd->ioc->FreeQlock, flags); @@ -5645,7 +6050,7 @@ pReq->ActionDataWord = 0; /* Reserved for this action */ //pReq->ActionDataSGE = 0; - mpt_add_sge((char *)&pReq->ActionDataSGE, + mpt_add_sge((char *)&pReq->ActionDataSGE, MPT_SGE_FLAGS_SSIMPLE_READ | 0, (dma_addr_t) -1); ddvprintk((MYIOC_s_INFO_FMT "RAID Volume action %x id %d\n", @@ -5974,7 +6379,7 @@ if (id == hostId) id++; - /* Write SDP1 for all SCSI devices + /* Write SDP1 for all SCSI devices * Alloc memory and set up config buffer */ if (hd->is_spi) { @@ -6097,7 +6502,7 @@ spin_unlock_irqrestore(&dvtaskQ_lock, flags); /* For this ioc, loop through all devices and do dv to each device. - * When complete with this ioc, search through the ioc list, and + * When complete with this ioc, search through the ioc list, and * for each scsi ioc found, do dv for all devices. Exit when no * device needs dv. */ @@ -6128,6 +6533,23 @@ if (hd == NULL) continue; + if ((ioc->spi_data.forceDv & MPT_SCSICFG_RELOAD_IOC_PG3) != 0) { + mpt_read_ioc_pg_3(ioc); + if (ioc->spi_data.pIocPg3) { + Ioc3PhysDisk_t *pPDisk = ioc->spi_data.pIocPg3->PhysDisk; + int numPDisk = ioc->spi_data.pIocPg3->NumPhysDisks; + + while (numPDisk) { + if (ioc->spi_data.dvStatus[pPDisk->PhysDiskID] & MPT_SCSICFG_DV_NOT_DONE) + ioc->spi_data.dvStatus[pPDisk->PhysDiskID] |= MPT_SCSICFG_NEED_DV; + + pPDisk++; + numPDisk--; + } + } + ioc->spi_data.forceDv &= ~MPT_SCSICFG_RELOAD_IOC_PG3; + } + maxid = MIN (ioc->sh->max_id, MPT_MAX_SCSI_DEVICES); for (id = 0; id < maxid; id++) { @@ -6318,7 +6740,7 @@ lun = 0; bus = 0; - ddvtprintk((MYIOC_s_NOTE_FMT + ddvtprintk((MYIOC_s_NOTE_FMT "DV started: numIOs %d bus=%d, id %d dv @ %p\n", ioc->name, atomic_read(&queue_depth), bus, id, &dv)); @@ -6423,7 +6845,7 @@ /* Skip this ID? Set cfg.hdr to force config page write */ if ((ioc->spi_data.nvram[id] != MPT_HOST_NVRAM_INVALID) && - (!(ioc->spi_data.nvram[id] & MPT_NVRAM_ID_SCAN_ENABLE))) { + (!(ioc->spi_data.nvram[id] & MPT_NVRAM_ID_SCAN_ENABLE))) { ddvprintk((MYIOC_s_NOTE_FMT "DV Skipped: bus, id, lun (%d, %d, %d)\n", ioc->name, bus, id, lun)); @@ -6495,11 +6917,11 @@ /* Wide - narrow - wide workaround case */ - if ((rc == MPT_SCANDV_ISSUE_SENSE) && dv.max.width) { + if ((rc == MPT_SCANDV_ISSUE_SENSE) && dv.max.width) { /* Send an untagged command to reset disk Qs corrupted * when a parity error occurs on a Request Sense. */ - if ((hd->ioc->facts.FWVersion.Word >= 0x01000600) || + if ((hd->ioc->facts.FWVersion.Word >= 0x01000600) || ((hd->ioc->facts.FWVersion.Word >= 0x01010000) && (hd->ioc->facts.FWVersion.Word < 0x01010B00)) ) { @@ -6535,7 +6957,11 @@ rc = hd->pLocal->completion; if (rc == MPT_SCANDV_GOOD) { if (hd->pLocal->scsiStatus == STS_BUSY) { - retcode = 1; + if ((iocmd.flags & MPT_ICFLAG_TAGGED_CMD) == 0) + retcode = 1; + else + retcode = 0; + goto target_done; } } else if (rc == MPT_SCANDV_SENSE) { @@ -6607,7 +7033,7 @@ * Fujitsu: PPR U320 -> Msg Reject and Ultra2 and wide * Resetart with a request for U160. */ - if ((dv.now.factor == MPT_ULTRA320) && (sdp0_nego == MPT_ULTRA2)) { + if ((dv.now.factor == MPT_ULTRA320) && (sdp0_nego == MPT_ULTRA2)) { doFallback = 1; } else { dv.cmd = MPT_UPDATE_MAX; @@ -6631,7 +7057,7 @@ } - } else if (rc == MPT_SCANDV_ISSUE_SENSE) + } else if (rc == MPT_SCANDV_ISSUE_SENSE) doFallback = 1; /* set fallback flag */ else if ((rc == MPT_SCANDV_DID_RESET) || (rc == MPT_SCANDV_SENSE)) doFallback = 1; /* set fallback flag */ @@ -6871,7 +7297,7 @@ mdelay (2000); notDone++; } else { - ddvprintk((MYIOC_s_INFO_FMT + ddvprintk((MYIOC_s_INFO_FMT "DV: Reserved Failed.", ioc->name)); goto target_done; } @@ -6935,7 +7361,7 @@ patt = -1; continue; } - } + } goto target_done; } else @@ -7048,7 +7474,7 @@ if (hd->pLocal->completion == MPT_SCANDV_GOOD) iocmd.flags &= ~MPT_ICFLAG_RESERVED; } else { - printk(MYIOC_s_INFO_FMT "DV: Release failed. id %d", + printk(MYIOC_s_INFO_FMT "DV: Release failed. id %d", ioc->name, id); } } @@ -7066,7 +7492,7 @@ mptscsih_dv_parms(hd, &dv, (void *)pcfg1Data); #if 0 - /* Double writes to SDP1 can cause problems, + /* Double writes to SDP1 can cause problems, * skip here since unnecessary */ /* Save the final negotiated settings to @@ -7222,7 +7648,7 @@ case MPT_SET_MIN: ddvprintk((MYIOC_s_NOTE_FMT "Setting Min: ", hd->ioc->name)); - /* Set page to asynchronous and narrow + /* Set page to asynchronous and narrow * Do not update now, breaks fallback routine. */ width = MPT_NARROW; offset = 0; @@ -7244,7 +7670,7 @@ case MPT_FALLBACK: ddvprintk((MYIOC_s_NOTE_FMT "Fallback: Start: offset %d, factor %x, width %d \n", - hd->ioc->name, dv->now.offset, + hd->ioc->name, dv->now.offset, dv->now.factor, dv->now.width)); width = dv->now.width; offset = dv->now.offset; diff -Nru a/drivers/message/fusion/mptscsih.h b/drivers/message/fusion/mptscsih.h --- a/drivers/message/fusion/mptscsih.h Wed Jan 15 16:57:29 2003 +++ b/drivers/message/fusion/mptscsih.h Wed Jan 15 16:57:29 2003 @@ -20,7 +20,7 @@ * (mailto:netscape.net) * (mailto:Pam.Delaney@lsil.com) * - * $Id: mptscsih.h,v 1.20 2002/10/17 20:16:00 pdelaney Exp $ + * $Id: mptscsih.h,v 1.21 2002/12/03 21:26:35 pdelaney Exp $ */ /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* @@ -73,9 +73,16 @@ * Try to keep these at 2^N-1 */ #define MPT_FC_CAN_QUEUE 63 -//#define MPT_SCSI_CAN_QUEUE 31 -#define MPT_SCSI_CAN_QUEUE MPT_FC_CAN_QUEUE -#define MPT_SCSI_CMD_PER_LUN 7 +#if defined MPT_SCSI_USE_NEW_EH + #define MPT_SCSI_CAN_QUEUE 127 +#else + #define MPT_SCSI_CAN_QUEUE 63 +#endif + +#define MPT_SCSI_CMD_PER_DEV_HIGH 31 +#define MPT_SCSI_CMD_PER_DEV_LOW 7 + +#define MPT_SCSI_CMD_PER_LUN 7 #define MPT_SCSI_MAX_SECTORS 8192 @@ -206,11 +213,16 @@ #define x_scsi_dev_reset mptscsih_dev_reset #define x_scsi_host_reset mptscsih_host_reset #define x_scsi_bios_param mptscsih_bios_param -#define x_scsi_slave_configure mptscsih_slave_configure #define x_scsi_taskmgmt_bh mptscsih_taskmgmt_bh #define x_scsi_old_abort mptscsih_old_abort #define x_scsi_old_reset mptscsih_old_reset +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52) +#define x_scsi_slave_configure mptscsih_slave_configure +#else +#define x_scsi_select_queue_depths mptscsih_select_queue_depths +#endif +#define x_scsi_proc_info mptscsih_proc_info /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ /* @@ -237,8 +249,14 @@ #else extern int x_scsi_bios_param(Disk *, kdev_t, int *); #endif -extern int x_scsi_slave_configure(Scsi_Device *); extern void x_scsi_taskmgmt_bh(void *); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52) +extern int x_scsi_slave_configure(Scsi_Device *); +#else +extern void x_scsi_select_queue_depths(struct Scsi_Host *, Scsi_Device *); +#endif + +extern int x_scsi_proc_info(char *, char **, off_t, int, int, int); #if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0) #define PROC_SCSI_DECL @@ -248,14 +266,19 @@ #ifdef MPT_SCSI_USE_NEW_EH -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,44) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52) #define MPT_SCSIHOST { \ PROC_SCSI_DECL \ + .proc_info = x_scsi_proc_info, \ .name = "MPT SCSI Host", \ .detect = x_scsi_detect, \ .release = x_scsi_release, \ .info = x_scsi_info, \ + .command = NULL, \ + .queuecommand = x_scsi_queuecommand, \ + .slave_configure = x_scsi_slave_configure, \ + .eh_strategy_handler = NULL, \ .eh_abort_handler = x_scsi_abort, \ .eh_device_reset_handler = x_scsi_dev_reset, \ .eh_bus_reset_handler = x_scsi_bus_reset, \ @@ -275,6 +298,7 @@ #define MPT_SCSIHOST { \ .next = NULL, \ PROC_SCSI_DECL \ + .proc_info = x_scsi_proc_info, \ .name = "MPT SCSI Host", \ .detect = x_scsi_detect, \ .release = x_scsi_release, \ diff -Nru a/drivers/net/tulip/media.c b/drivers/net/tulip/media.c --- a/drivers/net/tulip/media.c Wed Jan 15 16:57:28 2003 +++ b/drivers/net/tulip/media.c Wed Jan 15 16:57:28 2003 @@ -278,6 +278,10 @@ for (i = 0; i < init_length; i++) outl(init_sequence[i], ioaddr + CSR12); } + + (void) inl(ioaddr + CSR6); /* flush CSR12 writes */ + udelay(500); /* Give MII time to recover */ + tmp_info = get_u16(&misc_info[1]); if (tmp_info) tp->advertising[phy_num] = tmp_info | 1; diff -Nru a/drivers/scsi/megaraid.c b/drivers/scsi/megaraid.c --- a/drivers/scsi/megaraid.c Wed Jan 15 16:57:28 2003 +++ b/drivers/scsi/megaraid.c Wed Jan 15 16:57:28 2003 @@ -2045,7 +2045,7 @@ return; mbox = (mega_mailbox *) pScb->mboxData; - printk ("%u cmd:%x id:%x #scts:%x lba:%x addr:%x logdrv:%x #sg:%x\n", + printk ("%lu cmd:%x id:%x #scts:%x lba:%x addr:%x logdrv:%x #sg:%x\n", pScb->SCpnt->pid, mbox->cmd, mbox->cmdid, mbox->numsectors, mbox->lba, mbox->xferaddr, mbox->logdrv, mbox->numsgelements); @@ -3351,9 +3351,13 @@ mbox[0] = IS_BIOS_ENABLED; mbox[2] = GET_BIOS; - mboxpnt->xferaddr = virt_to_bus ((void *) megacfg->mega_buffer); + mboxpnt->xferaddr = pci_map_single(megacfg->dev, + (void *) megacfg->mega_buffer, (2 * 1024L), + PCI_DMA_FROMDEVICE); ret = megaIssueCmd (megacfg, mbox, NULL, 0); + + pci_unmap_single(megacfg->dev, mboxpnt->xferaddr, 2 * 1024L, PCI_DMA_FROMDEVICE); return (*(char *) megacfg->mega_buffer); } diff -Nru a/drivers/scsi/scsi_ioctl.c b/drivers/scsi/scsi_ioctl.c --- a/drivers/scsi/scsi_ioctl.c Wed Jan 15 16:57:29 2003 +++ b/drivers/scsi/scsi_ioctl.c Wed Jan 15 16:57:29 2003 @@ -219,6 +219,9 @@ unsigned int needed, buf_needed; int timeout, retries, result; int data_direction, gfp_mask = GFP_KERNEL; +#if __GNUC__ < 3 + int foo; +#endif if (!sic) return -EINVAL; @@ -232,11 +235,21 @@ if (verify_area(VERIFY_READ, sic, sizeof(Scsi_Ioctl_Command))) return -EFAULT; +#if __GNUC__ < 3 + foo = __get_user(inlen, &sic->inlen); + if (foo) + return -EFAULT; + + foo = __get_user(outlen, &sic->outlen); + if (foo) + return -EFAULT; +#else if(__get_user(inlen, &sic->inlen)) return -EFAULT; if(__get_user(outlen, &sic->outlen)) return -EFAULT; +#endif /* * We do not transfer more than MAX_BUF with this interface. diff -Nru a/drivers/scsi/sym53c8xx_2/sym_glue.c b/drivers/scsi/sym53c8xx_2/sym_glue.c --- a/drivers/scsi/sym53c8xx_2/sym_glue.c Wed Jan 15 16:57:29 2003 +++ b/drivers/scsi/sym53c8xx_2/sym_glue.c Wed Jan 15 16:57:29 2003 @@ -295,11 +295,7 @@ #ifndef SYM_LINUX_DYNAMIC_DMA_MAPPING typedef u_long bus_addr_t; #else -#if SYM_CONF_DMA_ADDRESSING_MODE > 0 -typedef dma64_addr_t bus_addr_t; -#else typedef dma_addr_t bus_addr_t; -#endif #endif /* diff -Nru a/drivers/scsi/sym53c8xx_2/sym_malloc.c b/drivers/scsi/sym53c8xx_2/sym_malloc.c --- a/drivers/scsi/sym53c8xx_2/sym_malloc.c Wed Jan 15 16:57:29 2003 +++ b/drivers/scsi/sym53c8xx_2/sym_malloc.c Wed Jan 15 16:57:29 2003 @@ -143,12 +143,14 @@ a = (m_addr_t) ptr; while (1) { -#ifdef SYM_MEM_FREE_UNUSED if (s == SYM_MEM_CLUSTER_SIZE) { +#ifdef SYM_MEM_FREE_UNUSED M_FREE_MEM_CLUSTER(a); - break; - } +#else + ((m_link_p) a)->next = h[i].next; + h[i].next = (m_link_p) a; #endif + } b = a ^ s; q = &h[i]; while (q->next && q->next != (m_link_p) b) { diff -Nru a/drivers/serial/8250.c b/drivers/serial/8250.c --- a/drivers/serial/8250.c Wed Jan 15 16:57:28 2003 +++ b/drivers/serial/8250.c Wed Jan 15 16:57:28 2003 @@ -1987,9 +1987,11 @@ return __register_serial(req, -1); } -int __init early_serial_setup(struct serial_struct *req) +int __init early_serial_setup(struct uart_port *port) { - __register_serial(req, req->line); + serial8250_isa_init_ports(); + serial8250_ports[port->line].port = *port; + serial8250_ports[port->line].port.ops = &serial8250_pops; return 0; } diff -Nru a/drivers/serial/8250_acpi.c b/drivers/serial/8250_acpi.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/drivers/serial/8250_acpi.c Wed Jan 15 16:57:29 2003 @@ -0,0 +1,178 @@ +/* + * linux/drivers/char/acpi_serial.c + * + * Copyright (C) 2000, 2002 Hewlett-Packard Co. + * Khalid Aziz + * + * Detect and initialize the headless console serial port defined in SPCR table and debug + * serial port defined in DBGP table. + * + * 2002/08/29 davidm Adjust it to new 2.5 serial driver infrastructure. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#undef SERIAL_DEBUG_ACPI + +#define ACPI_SERIAL_CONSOLE_PORT 0 +#define ACPI_SERIAL_DEBUG_PORT 5 + +/* + * Query ACPI tables for a debug and a headless console serial port. If found, add them to + * rs_table[]. A pointer to either SPCR or DBGP table is passed as parameter. This + * function should be called before serial_console_init() is called to make sure the SPCR + * serial console will be available for use. IA-64 kernel calls this function from within + * acpi.c when it encounters SPCR or DBGP tables as it parses the ACPI 2.0 tables during + * bootup. + */ +void __init +setup_serial_acpi (void *tablep) +{ + acpi_ser_t *acpi_ser_p; + struct uart_port port; + unsigned long iobase; + int gsi; + +#ifdef SERIAL_DEBUG_ACPI + printk("Entering setup_serial_acpi()\n"); +#endif + + /* Now get the table */ + if (!tablep) + return; + + memset(&port, 0, sizeof(port)); + + acpi_ser_p = (acpi_ser_t *) tablep; + + /* + * Perform a sanity check on the table. Table should have a signature of "SPCR" or + * "DBGP" and it should be atleast 52 bytes long. + */ + if (strncmp(acpi_ser_p->signature, ACPI_SPCRT_SIGNATURE, ACPI_SIG_LEN) != 0 && + strncmp(acpi_ser_p->signature, ACPI_DBGPT_SIGNATURE, ACPI_SIG_LEN) != 0) + return; + if (acpi_ser_p->length < 52) + return; + + iobase = (((u64) acpi_ser_p->base_addr.addrh) << 32) | acpi_ser_p->base_addr.addrl; + gsi = ( (acpi_ser_p->global_int[3] << 24) | (acpi_ser_p->global_int[2] << 16) + | (acpi_ser_p->global_int[1] << 8) | (acpi_ser_p->global_int[0] << 0)); + +#ifdef SERIAL_DEBUG_ACPI + printk("setup_serial_acpi(): table pointer = 0x%p\n", acpi_ser_p); + printk(" sig = '%c%c%c%c'\n", acpi_ser_p->signature[0], + acpi_ser_p->signature[1], acpi_ser_p->signature[2], acpi_ser_p->signature[3]); + printk(" length = %d\n", acpi_ser_p->length); + printk(" Rev = %d\n", acpi_ser_p->rev); + printk(" Interface type = %d\n", acpi_ser_p->intfc_type); + printk(" Base address = 0x%lX\n", iobase); + printk(" IRQ = %d\n", acpi_ser_p->irq); + printk(" Global System Int = %d\n", gsi); + printk(" Baud rate = "); + switch (acpi_ser_p->baud) { + case ACPI_SERIAL_BAUD_9600: + printk("9600\n"); + break; + + case ACPI_SERIAL_BAUD_19200: + printk("19200\n"); + break; + + case ACPI_SERIAL_BAUD_57600: + printk("57600\n"); + break; + + case ACPI_SERIAL_BAUD_115200: + printk("115200\n"); + break; + + default: + printk("Huh (%d)\n", acpi_ser_p->baud); + break; + } + if (acpi_ser_p->base_addr.space_id == ACPI_SERIAL_PCICONF_SPACE) { + printk(" PCI serial port:\n"); + printk(" Bus %d, Device %d, Vendor ID 0x%x, Dev ID 0x%x\n", + acpi_ser_p->pci_bus, acpi_ser_p->pci_dev, + acpi_ser_p->pci_vendor_id, acpi_ser_p->pci_dev_id); + } +#endif + /* + * Now build a serial_req structure to update the entry in rs_table for the + * headless console port. + */ + switch (acpi_ser_p->intfc_type) { + case ACPI_SERIAL_INTFC_16550: + port.type = PORT_16550; + port.uartclk = BASE_BAUD * 16; + break; + + case ACPI_SERIAL_INTFC_16450: + port.type = PORT_16450; + port.uartclk = BASE_BAUD * 16; + break; + + default: + port.type = PORT_UNKNOWN; + break; + } + if (strncmp(acpi_ser_p->signature, ACPI_SPCRT_SIGNATURE, ACPI_SIG_LEN) == 0) + port.line = ACPI_SERIAL_CONSOLE_PORT; + else if (strncmp(acpi_ser_p->signature, ACPI_DBGPT_SIGNATURE, ACPI_SIG_LEN) == 0) + port.line = ACPI_SERIAL_DEBUG_PORT; + /* + * Check if this is an I/O mapped address or a memory mapped address + */ + if (acpi_ser_p->base_addr.space_id == ACPI_SERIAL_MEM_SPACE) { + port.iobase = 0; + port.mapbase = iobase; + port.membase = ioremap(iobase, 64); + port.iotype = SERIAL_IO_MEM; + } else if (acpi_ser_p->base_addr.space_id == ACPI_SERIAL_IO_SPACE) { + port.iobase = iobase; + port.mapbase = 0; + port.membase = NULL; + port.iotype = SERIAL_IO_PORT; + } else if (acpi_ser_p->base_addr.space_id == ACPI_SERIAL_PCICONF_SPACE) { + printk("WARNING: No support for PCI serial console\n"); + return; + } + + /* + * If the table does not have IRQ information, use 0 for IRQ. This will force + * rs_init() to probe for IRQ. + */ + if (acpi_ser_p->length < 53) + port.irq = 0; + else { + port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_AUTO_IRQ; + if (acpi_ser_p->int_type & (ACPI_SERIAL_INT_APIC | ACPI_SERIAL_INT_SAPIC)) + port.irq = gsi; + else if (acpi_ser_p->int_type & ACPI_SERIAL_INT_PCAT) + port.irq = acpi_ser_p->irq; + else + /* + * IRQ type not being set would mean UART will run in polling + * mode. Do not probe for IRQ in that case. + */ + port.flags &= UPF_AUTO_IRQ; + } + if (early_serial_setup(&port) < 0) { + printk("early_serial_setup() for ACPI serial console port failed\n"); + return; + } + +#ifdef SERIAL_DEBUG_ACPI + printk("Leaving setup_serial_acpi()\n"); +#endif +} diff -Nru a/drivers/serial/8250_hcdp.c b/drivers/serial/8250_hcdp.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/drivers/serial/8250_hcdp.c Wed Jan 15 16:57:29 2003 @@ -0,0 +1,215 @@ +/* + * linux/drivers/char/hcdp_serial.c + * + * Copyright (C) 2002 Hewlett-Packard Co. + * Khalid Aziz + * + * Parse the EFI HCDP table to locate serial console and debug ports and initialize them. + * + * 2002/08/29 davidm Adjust it to new 2.5 serial driver infrastructure (untested). + */ +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "8250_hcdp.h" + +#undef SERIAL_DEBUG_HCDP + +/* + * Parse the HCDP table to find descriptions for headless console and debug serial ports + * and add them to rs_table[]. A pointer to HCDP table is passed as parameter. This + * function should be called before serial_console_init() is called to make sure the HCDP + * serial console will be available for use. IA-64 kernel calls this function from + * setup_arch() after the EFI and ACPI tables have been parsed. + */ +void __init +setup_serial_hcdp (void *tablep) +{ + hcdp_dev_t *hcdp_dev; + struct uart_port port; + unsigned long iobase; + hcdp_t hcdp; + int gsi, nr; +#if 0 + static int shift_once = 1; +#endif + +#ifdef SERIAL_DEBUG_HCDP + printk("Entering setup_serial_hcdp()\n"); +#endif + + /* Verify we have a valid table pointer */ + if (!tablep) + return; + + memset(&port, 0, sizeof(port)); + + /* + * Don't trust firmware to give us a table starting at an aligned address. Make a + * local copy of the HCDP table with aligned structures. + */ + memcpy(&hcdp, tablep, sizeof(hcdp)); + + /* + * Perform a sanity check on the table. Table should have a signature of "HCDP" + * and it should be atleast 82 bytes long to have any useful information. + */ + if ((strncmp(hcdp.signature, HCDP_SIGNATURE, HCDP_SIG_LEN) != 0)) + return; + if (hcdp.len < 82) + return; + +#ifdef SERIAL_DEBUG_HCDP + printk("setup_serial_hcdp(): table pointer = 0x%p, sig = '%.4s'\n", + tablep, hcdp.signature); + printk(" length = %d, rev = %d, ", hcdp.len, hcdp.rev); + printk("OEM ID = %.6s, # of entries = %d\n", hcdp.oemid, hcdp.num_entries); +#endif + + /* + * Parse each device entry + */ + for (nr = 0; nr < hcdp.num_entries; nr++) { + hcdp_dev = hcdp.hcdp_dev + nr; + /* + * We will parse only the primary console device which is the first entry + * for these devices. We will ignore rest of the entries for the same type + * device that has already been parsed and initialized + */ + if (hcdp_dev->type != HCDP_DEV_CONSOLE) + continue; + + iobase = ((u64) hcdp_dev->base_addr.addrhi << 32) | hcdp_dev->base_addr.addrlo; + gsi = hcdp_dev->global_int; + + /* See PCI spec v2.2, Appendix D (Class Codes): */ + switch (hcdp_dev->pci_prog_intfc) { + case 0x00: port.type = PORT_8250; break; + case 0x01: port.type = PORT_16450; break; + case 0x02: port.type = PORT_16550; break; + case 0x03: port.type = PORT_16650; break; + case 0x04: port.type = PORT_16750; break; + case 0x05: port.type = PORT_16850; break; + case 0x06: port.type = PORT_16C950; break; + default: + printk(KERN_WARNING"warning: EFI HCDP table reports unknown serial " + "programming interface 0x%02x; will autoprobe.\n", + hcdp_dev->pci_prog_intfc); + port.type = PORT_UNKNOWN; + break; + } + +#ifdef SERIAL_DEBUG_HCDP + printk(" type = %s, uart = %d\n", ((hcdp_dev->type == HCDP_DEV_CONSOLE) + ? "Headless Console" : ((hcdp_dev->type == HCDP_DEV_DEBUG) + ? "Debug port" : "Huh????")), + port.type); + printk(" base address space = %s, base address = 0x%lx\n", + ((hcdp_dev->base_addr.space_id == ACPI_MEM_SPACE) + ? "Memory Space" : ((hcdp_dev->base_addr.space_id == ACPI_IO_SPACE) + ? "I/O space" : "PCI space")), + iobase); + printk(" gsi = %d, baud rate = %lu, bits = %d, clock = %d\n", + gsi, (unsigned long) hcdp_dev->baud, hcdp_dev->bits, hcdp_dev->clock_rate); + if (hcdp_dev->base_addr.space_id == ACPI_PCICONF_SPACE) + printk(" PCI id: %02x:%02x:%02x, vendor ID=0x%x, dev ID=0x%x\n", + hcdp_dev->pci_seg, hcdp_dev->pci_bus, hcdp_dev->pci_dev, + hcdp_dev->pci_vendor_id, hcdp_dev->pci_dev_id); +#endif + /* + * Now fill in a port structure to update the 8250 port table.. + */ + if (hcdp_dev->clock_rate) + port.uartclk = hcdp_dev->clock_rate; + else + port.uartclk = BASE_BAUD * 16; + + /* + * Check if this is an I/O mapped address or a memory mapped address + */ + if (hcdp_dev->base_addr.space_id == ACPI_MEM_SPACE) { + port.iobase = 0; + port.mapbase = iobase; + port.membase = ioremap(iobase, 64); + port.iotype = SERIAL_IO_MEM; + } else if (hcdp_dev->base_addr.space_id == ACPI_IO_SPACE) { + port.iobase = iobase; + port.mapbase = 0; + port.membase = NULL; + port.iotype = SERIAL_IO_PORT; + } else if (hcdp_dev->base_addr.space_id == ACPI_PCICONF_SPACE) { + printk(KERN_WARNING"warning: No support for PCI serial console\n"); + return; + } + port.irq = gsi; + port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF; + if (gsi) + port.flags |= ASYNC_AUTO_IRQ; + + /* + * Note: the above memset() initializes port.line to 0, so we register + * this port as ttyS0. + */ + if (early_serial_setup(&port) < 0) { + printk("setup_serial_hcdp(): early_serial_setup() for HCDP serial " + "console port failed. Will try any additional consoles in HCDP.\n"); + continue; + } + break; + } + +#ifdef SERIAL_DEBUG_HCDP + printk("Leaving setup_serial_hcdp()\n"); +#endif +} + +#ifdef CONFIG_IA64_EARLY_PRINTK_UART +unsigned long +hcdp_early_uart (void) +{ + efi_system_table_t *systab; + efi_config_table_t *config_tables; + unsigned long addr = 0; + hcdp_t *hcdp = 0; + hcdp_dev_t *dev; + int i; + + systab = (efi_system_table_t *) ia64_boot_param->efi_systab; + if (!systab) + return 0; + systab = __va(systab); + + config_tables = (efi_config_table_t *) systab->tables; + if (!config_tables) + return 0; + config_tables = __va(config_tables); + + for (i = 0; i < systab->nr_tables; i++) { + if (efi_guidcmp(config_tables[i].guid, HCDP_TABLE_GUID) == 0) { + hcdp = (hcdp_t *) config_tables[i].table; + break; + } + } + if (!hcdp) + return 0; + hcdp = __va(hcdp); + + for (i = 0, dev = hcdp->hcdp_dev; i < hcdp->num_entries; i++, dev++) { + if (dev->type == HCDP_DEV_CONSOLE) { + addr = (u64) dev->base_addr.addrhi << 32 | dev->base_addr.addrlo; + break; + } + } + return addr; +} +#endif /* CONFIG_IA64_EARLY_PRINTK_UART */ diff -Nru a/drivers/serial/8250_hcdp.h b/drivers/serial/8250_hcdp.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/drivers/serial/8250_hcdp.h Wed Jan 15 16:57:29 2003 @@ -0,0 +1,79 @@ +/* + * drivers/serial/8250_hcdp.h + * + * Copyright (C) 2002 Hewlett-Packard Co. + * Khalid Aziz + * + * Definitions for HCDP defined serial ports (Serial console and debug + * ports) + */ + +/* ACPI table signatures */ +#define HCDP_SIG_LEN 4 +#define HCDP_SIGNATURE "HCDP" + +/* Space ID as defined in ACPI generic address structure */ +#define ACPI_MEM_SPACE 0 +#define ACPI_IO_SPACE 1 +#define ACPI_PCICONF_SPACE 2 + +/* + * Maximum number of HCDP devices we want to read in + */ +#define MAX_HCDP_DEVICES 6 + +/* + * Default UART clock rate if clock rate is 0 in HCDP table. + */ +#define DEFAULT_UARTCLK 115200 + +/* + * ACPI Generic Address Structure + */ +typedef struct { + u8 space_id; + u8 bit_width; + u8 bit_offset; + u8 resv; + u32 addrlo; + u32 addrhi; +} acpi_gen_addr; + +/* HCDP Device descriptor entry types */ +#define HCDP_DEV_CONSOLE 0 +#define HCDP_DEV_DEBUG 1 + +/* HCDP Device descriptor type */ +typedef struct { + u8 type; + u8 bits; + u8 parity; + u8 stop_bits; + u8 pci_seg; + u8 pci_bus; + u8 pci_dev; + u8 pci_func; + u64 baud; + acpi_gen_addr base_addr; + u16 pci_dev_id; + u16 pci_vendor_id; + u32 global_int; + u32 clock_rate; + u8 pci_prog_intfc; + u8 resv; +} hcdp_dev_t; + +/* HCDP Table format */ +typedef struct { + u8 signature[4]; + u32 len; + u8 rev; + u8 chksum; + u8 oemid[6]; + u8 oem_tabid[8]; + u32 oem_rev; + u8 creator_id[4]; + u32 creator_rev; + u32 num_entries; + hcdp_dev_t hcdp_dev[MAX_HCDP_DEVICES]; +} hcdp_t; diff -Nru a/drivers/serial/Kconfig b/drivers/serial/Kconfig --- a/drivers/serial/Kconfig Wed Jan 15 16:57:29 2003 +++ b/drivers/serial/Kconfig Wed Jan 15 16:57:29 2003 @@ -39,6 +39,13 @@ Most people will say Y or M here, so that they can use serial mice, modems and similar devices connecting to the standard serial ports. +config SERIAL_8250_ACPI + tristate "8250/16550 device discovery support via ACPI SPCR/DBGP tables" + depends on IA64 + help + Locate serial ports via the Microsoft proprietary ACPI SPCR/DBGP tables. + This table has been superseded by the EFI HCDP table. + config SERIAL_8250_CONSOLE bool "Console on 8250/16550 and compatible serial port (EXPERIMENTAL)" depends on SERIAL_8250=y @@ -76,6 +83,15 @@ The module will be called serial_cs.o. If you want to compile it as a module, say M here and read . If unsure, say N. + +config SERIAL_8250_HCDP + bool "8250/16550 device discovery support via EFI HCDP table" + depends on IA64 + ---help--- + If you wish to make the serial console port described by the EFI + HCDP table available for use as serial console or general + purpose port, say Y here. See + . config SERIAL_8250_EXTENDED bool "Extended 8250/16550 serial driver options" diff -Nru a/drivers/serial/Makefile b/drivers/serial/Makefile --- a/drivers/serial/Makefile Wed Jan 15 16:57:29 2003 +++ b/drivers/serial/Makefile Wed Jan 15 16:57:29 2003 @@ -10,6 +10,8 @@ serial-8250-$(CONFIG_GSC) += 8250_gsc.o serial-8250-$(CONFIG_PCI) += 8250_pci.o serial-8250-$(CONFIG_PNP) += 8250_pnp.o +serial-8250-$(CONFIG_SERIAL_8250_ACPI) += acpi.o 8250_acpi.o +serial-8250-$(CONFIG_SERIAL_8250_HCDP) += 8250_hcdp.o obj-$(CONFIG_SERIAL_CORE) += core.o obj-$(CONFIG_SERIAL_21285) += 21285.o obj-$(CONFIG_SERIAL_8250) += 8250.o $(serial-8250-y) diff -Nru a/drivers/serial/acpi.c b/drivers/serial/acpi.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/drivers/serial/acpi.c Wed Jan 15 16:57:29 2003 @@ -0,0 +1,110 @@ +/* + * serial/acpi.c + * Copyright (c) 2002 Matthew Wilcox for Hewlett-Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include "../acpi/acpi_bus.h" + +static void acpi_serial_address(struct serial_struct *req, + acpi_resource_address32 *addr32) +{ + unsigned long size; + + size = addr32->max_address_range - addr32->min_address_range + 1; + req->iomap_base = addr32->min_address_range; + req->iomem_base = ioremap(req->iomap_base, size); + req->io_type = SERIAL_IO_MEM; +} + +static void acpi_serial_irq(struct serial_struct *req, + acpi_resource_ext_irq *ext_irq) +{ + if (ext_irq->number_of_interrupts > 0) { +#ifdef CONFIG_IA64 + req->irq = acpi_register_irq(ext_irq->interrupts[0], + ext_irq->active_high_low == ACPI_ACTIVE_HIGH, + ext_irq->edge_level == ACPI_EDGE_SENSITIVE); +#else + req->irq = ext_irq->interrupts[0]; +#endif + } +} + +static int acpi_serial_add(struct acpi_device *device) +{ + acpi_status result; + acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + struct serial_struct serial_req; + int line, offset = 0; + + memset(&serial_req, 0, sizeof(serial_req)); + result = acpi_get_current_resources(device->handle, &buffer); + if (ACPI_FAILURE(result)) { + result = -ENODEV; + goto out; + } + + while (offset <= buffer.length) { + acpi_resource *res = buffer.pointer + offset; + if (res->length == 0) + break; + offset += res->length; + if (res->id == ACPI_RSTYPE_ADDRESS32) { + acpi_serial_address(&serial_req, &res->data.address32); + } else if (res->id == ACPI_RSTYPE_EXT_IRQ) { + acpi_serial_irq(&serial_req, &res->data.extended_irq); + } + } + + serial_req.baud_base = BASE_BAUD; + serial_req.flags = ASYNC_SKIP_TEST|ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ; + + result = 0; + line = register_serial(&serial_req); + if (line < 0) + result = -ENODEV; + + out: + acpi_os_free(buffer.pointer); + return result; +} + +static int acpi_serial_remove(struct acpi_device *device, int type) +{ + return 0; +} + +static struct acpi_driver acpi_serial_driver = { + .name = "serial", + .class = "", + .ids = "PNP0501", + .ops = { + .add = acpi_serial_add, + .remove = acpi_serial_remove, + }, +}; + +static int __init acpi_serial_init(void) +{ + acpi_bus_register_driver(&acpi_serial_driver); + return 0; +} + +static void __exit acpi_serial_exit(void) +{ + acpi_bus_unregister_driver(&acpi_serial_driver); +} + +module_init(acpi_serial_init); +module_exit(acpi_serial_exit); diff -Nru a/drivers/video/radeonfb.c b/drivers/video/radeonfb.c --- a/drivers/video/radeonfb.c Wed Jan 15 16:57:29 2003 +++ b/drivers/video/radeonfb.c Wed Jan 15 16:57:29 2003 @@ -726,7 +726,6 @@ radeon_set_backlight_level }; #endif /* CONFIG_PMAC_BACKLIGHT */ - #endif /* CONFIG_ALL_PPC */ diff -Nru a/fs/afs/file.c b/fs/afs/file.c --- a/fs/afs/file.c Wed Jan 15 16:57:29 2003 +++ b/fs/afs/file.c Wed Jan 15 16:57:29 2003 @@ -37,7 +37,7 @@ struct file_operations afs_file_file_operations = { .read = generic_file_read, .write = afs_file_write, - .mmap = generic_file_mmap, + .mmap = generic_file_readonly_mmap, #if 0 .open = afs_file_open, .release = afs_file_release, diff -Nru a/fs/befs/linuxvfs.c b/fs/befs/linuxvfs.c --- a/fs/befs/linuxvfs.c Wed Jan 15 16:57:29 2003 +++ b/fs/befs/linuxvfs.c Wed Jan 15 16:57:29 2003 @@ -74,7 +74,7 @@ struct file_operations befs_file_operations = { .llseek = default_llseek, .read = generic_file_read, - .mmap = generic_file_mmap, + .mmap = generic_file_readonly_mmap, }; struct address_space_operations befs_aops = { diff -Nru a/fs/exec.c b/fs/exec.c --- a/fs/exec.c Wed Jan 15 16:57:29 2003 +++ b/fs/exec.c Wed Jan 15 16:57:29 2003 @@ -402,7 +402,7 @@ mpnt->vm_start = PAGE_MASK & (unsigned long) bprm->p; mpnt->vm_end = STACK_TOP; #endif - mpnt->vm_page_prot = PAGE_COPY; + mpnt->vm_page_prot = protection_map[VM_STACK_FLAGS & 0x7]; mpnt->vm_flags = VM_STACK_FLAGS; mpnt->vm_ops = NULL; mpnt->vm_pgoff = 0; diff -Nru a/fs/fcntl.c b/fs/fcntl.c --- a/fs/fcntl.c Wed Jan 15 16:57:28 2003 +++ b/fs/fcntl.c Wed Jan 15 16:57:28 2003 @@ -320,6 +320,7 @@ * to fix this will be in libc. */ err = filp->f_owner.pid; + force_successful_syscall_return(); break; case F_SETOWN: err = f_setown(filp, arg, 1); diff -Nru a/fs/jffs/inode-v23.c b/fs/jffs/inode-v23.c --- a/fs/jffs/inode-v23.c Wed Jan 15 16:57:29 2003 +++ b/fs/jffs/inode-v23.c Wed Jan 15 16:57:29 2003 @@ -1641,7 +1641,7 @@ .read = generic_file_read, .write = generic_file_write, .ioctl = jffs_ioctl, - .mmap = generic_file_mmap, + .mmap = generic_file_readonly_mmap, .fsync = jffs_fsync, .sendfile = generic_file_sendfile, }; diff -Nru a/fs/jffs2/file.c b/fs/jffs2/file.c --- a/fs/jffs2/file.c Wed Jan 15 16:57:29 2003 +++ b/fs/jffs2/file.c Wed Jan 15 16:57:29 2003 @@ -58,7 +58,7 @@ .read = generic_file_read, .write = generic_file_write, .ioctl = jffs2_ioctl, - .mmap = generic_file_mmap, + .mmap = generic_file_readonly_mmap, .fsync = jffs2_fsync, #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,29) .sendfile = generic_file_sendfile diff -Nru a/fs/proc/base.c b/fs/proc/base.c --- a/fs/proc/base.c Wed Jan 15 16:57:29 2003 +++ b/fs/proc/base.c Wed Jan 15 16:57:29 2003 @@ -531,7 +531,24 @@ } #endif +static loff_t mem_lseek(struct file * file, loff_t offset, int orig) +{ + switch (orig) { + case 0: + file->f_pos = offset; + break; + case 1: + file->f_pos += offset; + break; + default: + return -EINVAL; + } + force_successful_syscall_return(); + return file->f_pos; +} + static struct file_operations proc_mem_operations = { + .llseek = mem_lseek, .read = mem_read, .write = mem_write, .open = mem_open, diff -Nru a/fs/read_write.c b/fs/read_write.c --- a/fs/read_write.c Wed Jan 15 16:57:29 2003 +++ b/fs/read_write.c Wed Jan 15 16:57:29 2003 @@ -19,7 +19,7 @@ struct file_operations generic_ro_fops = { .llseek = generic_file_llseek, .read = generic_file_read, - .mmap = generic_file_mmap, + .mmap = generic_file_readonly_mmap, .sendfile = generic_file_sendfile, }; diff -Nru a/fs/select.c b/fs/select.c --- a/fs/select.c Wed Jan 15 16:57:28 2003 +++ b/fs/select.c Wed Jan 15 16:57:28 2003 @@ -176,7 +176,7 @@ { struct poll_wqueues table; poll_table *wait; - int retval, i, off; + int retval, i; long __timeout = *timeout; read_lock(¤t->files->file_lock); @@ -193,38 +193,53 @@ wait = NULL; retval = 0; for (;;) { + unsigned long *rinp, *routp, *rexp, *inp, *outp, *exp; set_current_state(TASK_INTERRUPTIBLE); - for (i = 0 ; i < n; i++) { - unsigned long bit = BIT(i); - unsigned long mask; - struct file *file; - off = i / __NFDBITS; - if (!(bit & BITS(fds, off))) + inp = fds->in; outp = fds->out; exp = fds->ex; + rinp = fds->res_in; routp = fds->res_out; rexp = fds->res_ex; + + for (i = 0; i < n; ++rinp, ++routp, ++rexp) { + unsigned long in, out, ex, all_bits, bit = 1, mask, j; + unsigned long res_in = 0, res_out = 0, res_ex = 0; + struct file_operations *f_op = NULL; + struct file *file = NULL; + + in = *inp++; out = *outp++; ex = *exp++; + all_bits = in | out | ex; + if (all_bits == 0) continue; - file = fget(i); - mask = POLLNVAL; - if (file) { + + for (j = 0; j < __NFDBITS; ++j, ++i, bit <<= 1) { + if (i >= n) + break; + if (!(bit & all_bits)) + continue; + file = fget(i); + if (file) + f_op = file->f_op; mask = DEFAULT_POLLMASK; - if (file->f_op && file->f_op->poll) - mask = file->f_op->poll(file, wait); - fput(file); - } - if ((mask & POLLIN_SET) && ISSET(bit, __IN(fds,off))) { - SET(bit, __RES_IN(fds,off)); - retval++; - wait = NULL; - } - if ((mask & POLLOUT_SET) && ISSET(bit, __OUT(fds,off))) { - SET(bit, __RES_OUT(fds,off)); - retval++; - wait = NULL; - } - if ((mask & POLLEX_SET) && ISSET(bit, __EX(fds,off))) { - SET(bit, __RES_EX(fds,off)); - retval++; - wait = NULL; + if (file) { + if (f_op && f_op->poll) + mask = (*f_op->poll)(file, retval ? NULL : wait); + fput(file); + if ((mask & POLLIN_SET) && (in & bit)) { + res_in |= bit; + retval++; + } + if ((mask & POLLOUT_SET) && (out & bit)) { + res_out |= bit; + retval++; + } + if ((mask & POLLEX_SET) && (ex & bit)) { + res_ex |= bit; + retval++; + } + } } + if (res_in) *rinp = res_in; + if (res_out) *routp = res_out; + if (res_ex) *rexp = res_ex; } wait = NULL; if (retval || !__timeout || signal_pending(current)) diff -Nru a/include/asm-alpha/agp.h b/include/asm-alpha/agp.h --- a/include/asm-alpha/agp.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-alpha/agp.h Wed Jan 15 16:57:28 2003 @@ -8,4 +8,11 @@ #define flush_agp_mappings() #define flush_agp_cache() mb() +/* + * Page-protection value to be used for AGP memory mapped into kernel space. For + * platforms which use coherent AGP DMA, this can be PAGE_KERNEL. For others, it needs to + * be an uncached mapping (such as write-combining). + */ +#define PAGE_AGP PAGE_KERNEL_NOCACHE /* XXX fix me */ + #endif diff -Nru a/include/asm-i386/agp.h b/include/asm-i386/agp.h --- a/include/asm-i386/agp.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-i386/agp.h Wed Jan 15 16:57:28 2003 @@ -20,4 +20,11 @@ worth it. Would need a page for it. */ #define flush_agp_cache() asm volatile("wbinvd":::"memory") +/* + * Page-protection value to be used for AGP memory mapped into kernel space. For + * platforms which use coherent AGP DMA, this can be PAGE_KERNEL. For others, it needs to + * be an uncached mapping (such as write-combining). + */ +#define PAGE_AGP PAGE_KERNEL_NOCACHE + #endif diff -Nru a/include/asm-i386/hw_irq.h b/include/asm-i386/hw_irq.h --- a/include/asm-i386/hw_irq.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-i386/hw_irq.h Wed Jan 15 16:57:29 2003 @@ -140,4 +140,6 @@ static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {} #endif +extern irq_desc_t irq_desc [NR_IRQS]; + #endif /* _ASM_HW_IRQ_H */ diff -Nru a/include/asm-i386/ptrace.h b/include/asm-i386/ptrace.h --- a/include/asm-i386/ptrace.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-i386/ptrace.h Wed Jan 15 16:57:28 2003 @@ -54,6 +54,7 @@ #ifdef __KERNEL__ #define user_mode(regs) ((VM_MASK & (regs)->eflags) || (3 & (regs)->xcs)) #define instruction_pointer(regs) ((regs)->eip) +#define force_successful_syscall_return() do { } while (0) #endif #endif diff -Nru a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h --- a/include/asm-ia64/acpi.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/acpi.h Wed Jan 15 16:57:29 2003 @@ -56,7 +56,7 @@ #define ACPI_ACQUIRE_GLOBAL_LOCK(GLptr, Acq) \ do { \ - __asm__ volatile ("1: ld4 r29=%1\n" \ + __asm__ volatile ("1: ld4 r29=[%1]\n" \ ";;\n" \ "mov ar.ccv=r29\n" \ "mov r2=r29\n" \ @@ -68,7 +68,7 @@ ";;\n" \ "add r29=r29,r30\n" \ ";;\n" \ - "cmpxchg4.acq r30=%1,r29,ar.ccv\n" \ + "cmpxchg4.acq r30=[%1],r29,ar.ccv\n" \ ";;\n" \ "cmp.eq p6,p7=r2,r30\n" \ "(p7) br.dpnt.few 1b\n" \ @@ -76,24 +76,24 @@ ";;\n" \ "(p8) mov %0=-1\n" \ "(p9) mov %0=r0\n" \ - :"=r"(Acq):"m"(GLptr):"r2","r29","r30","memory"); \ + :"=r"(Acq):"r"(GLptr):"r2","r29","r30","memory"); \ } while (0) #define ACPI_RELEASE_GLOBAL_LOCK(GLptr, Acq) \ do { \ - __asm__ volatile ("1: ld4 r29=%1\n" \ + __asm__ volatile ("1: ld4 r29=[%1]\n" \ ";;\n" \ "mov ar.ccv=r29\n" \ "mov r2=r29\n" \ "and r29=-4,r29\n" \ ";;\n" \ - "cmpxchg4.acq r30=%1,r29,ar.ccv\n" \ + "cmpxchg4.acq r30=[%1],r29,ar.ccv\n" \ ";;\n" \ "cmp.eq p6,p7=r2,r30\n" \ "(p7) br.dpnt.few 1b\n" \ "and %0=1,r2\n" \ ";;\n" \ - :"=r"(Acq):"m"(GLptr):"r2","r29","r30","memory"); \ + :"=r"(Acq):"r"(GLptr):"r2","r29","r30","memory"); \ } while (0) const char *acpi_get_sysname (void); diff -Nru a/include/asm-ia64/asmmacro.h b/include/asm-ia64/asmmacro.h --- a/include/asm-ia64/asmmacro.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/asmmacro.h Wed Jan 15 16:57:28 2003 @@ -2,15 +2,22 @@ #define _ASM_IA64_ASMMACRO_H /* - * Copyright (C) 2000-2001 Hewlett-Packard Co + * Copyright (C) 2000-2001, 2003 Hewlett-Packard Co * David Mosberger-Tang */ +#include + #define ENTRY(name) \ .align 32; \ .proc name; \ name: +#define ENTRY_MIN_ALIGN(name) \ + .align 16; \ + .proc name; \ +name: + #define GLOBAL_ENTRY(name) \ .global name; \ ENTRY(name) @@ -50,6 +57,15 @@ # define EXCLR(y,x...) \ .xdata4 "__ex_table", @gprel(99f), @gprel(y)+4; \ 99: x +#endif + +#ifdef CONFIG_MCKINLEY +/* workaround for Itanium 2 Errata 7: */ +# define MCKINLEY_E7_WORKAROUND \ + br.call.sptk.many b7=1f;; \ +1: +#else +# define MCKINLEY_E7_WORKAROUND #endif #endif /* _ASM_IA64_ASMMACRO_H */ diff -Nru a/include/asm-ia64/atomic.h b/include/asm-ia64/atomic.h --- a/include/asm-ia64/atomic.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/atomic.h Wed Jan 15 16:57:28 2003 @@ -14,7 +14,7 @@ */ #include -#include +#include /* * On IA-64, counter must always be volatile to ensure that that the diff -Nru a/include/asm-ia64/bitops.h b/include/asm-ia64/bitops.h --- a/include/asm-ia64/bitops.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/bitops.h Wed Jan 15 16:57:29 2003 @@ -9,9 +9,10 @@ * scheduler patch */ +#include #include -#include +#include /** * set_bit - Atomically set a bit in memory diff -Nru a/include/asm-ia64/compat.h b/include/asm-ia64/compat.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-ia64/compat.h Wed Jan 15 16:57:29 2003 @@ -0,0 +1,56 @@ +#ifndef _ASM_IA64_COMPAT_H +#define _ASM_IA64_COMPAT_H +/* + * Architecture specific compatibility types + */ +#include + +#define COMPAT_USER_HZ 100 + +typedef u32 compat_size_t; +typedef s32 compat_ssize_t; +typedef s32 compat_time_t; +typedef s32 compat_clock_t; +typedef s32 compat_pid_t; +typedef u16 compat_uid_t; +typedef u16 compat_gid_t; +typedef u16 compat_mode_t; +typedef u32 compat_ino_t; +typedef u16 compat_dev_t; +typedef s32 compat_off_t; +typedef u16 compat_nlink_t; + +struct compat_timespec { + compat_time_t tv_sec; + s32 tv_nsec; +}; + +struct compat_timeval { + compat_time_t tv_sec; + s32 tv_usec; +}; + +struct compat_stat { + compat_dev_t st_dev; + u16 __pad1; + compat_ino_t st_ino; + compat_mode_t st_mode; + compat_nlink_t st_nlink; + compat_uid_t st_uid; + compat_gid_t st_gid; + compat_dev_t st_rdev; + u16 __pad2; + u32 st_size; + u32 st_blksize; + u32 st_blocks; + u32 st_atime; + u32 st_atime_nsec; + u32 st_mtime; + u32 st_mtime_nsec; + u32 st_ctime; + u32 st_ctime_nsec; + u32 __unused4; + u32 __unused5; +}; + +#endif /* _ASM_IA64_COMPAT_H */ diff -Nru a/include/asm-ia64/elf.h b/include/asm-ia64/elf.h --- a/include/asm-ia64/elf.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/elf.h Wed Jan 15 16:57:29 2003 @@ -4,10 +4,12 @@ /* * ELF-specific definitions. * - * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co + * Copyright (C) 1998-1999, 2002-2003 Hewlett-Packard Co * David Mosberger-Tang */ +#include + #include #include @@ -88,6 +90,11 @@ relevant until we have real hardware to play with... */ #define ELF_PLATFORM 0 +/* + * This should go into linux/elf.h... + */ +#define AT_SYSINFO 32 + #ifdef __KERNEL__ struct elf64_hdr; extern void ia64_set_personality (struct elf64_hdr *elf_ex, int ibcs2_interpreter); @@ -99,7 +106,14 @@ #define ELF_CORE_COPY_TASK_REGS(tsk, elf_gregs) dump_task_regs(tsk, elf_gregs) #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs) - +#ifdef CONFIG_FSYS +#define ARCH_DLINFO \ +do { \ + extern int syscall_via_epc; \ + NEW_AUX_ENT(AT_SYSINFO, syscall_via_epc); \ +} while (0) #endif + +#endif /* __KERNEL__ */ #endif /* _ASM_IA64_ELF_H */ diff -Nru a/include/asm-ia64/ia32.h b/include/asm-ia64/ia32.h --- a/include/asm-ia64/ia32.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/ia32.h Wed Jan 15 16:57:29 2003 @@ -6,30 +6,19 @@ #ifdef CONFIG_IA32_SUPPORT #include +#include /* * 32 bit structures for IA32 support. */ /* 32bit compatibility types */ -typedef unsigned int __kernel_size_t32; -typedef int __kernel_ssize_t32; -typedef int __kernel_ptrdiff_t32; -typedef int __kernel_time_t32; -typedef int __kernel_clock_t32; -typedef int __kernel_pid_t32; typedef unsigned short __kernel_ipc_pid_t32; -typedef unsigned short __kernel_uid_t32; typedef unsigned int __kernel_uid32_t32; -typedef unsigned short __kernel_gid_t32; typedef unsigned int __kernel_gid32_t32; -typedef unsigned short __kernel_dev_t32; -typedef unsigned int __kernel_ino_t32; -typedef unsigned short __kernel_mode_t32; typedef unsigned short __kernel_umode_t32; typedef short __kernel_nlink_t32; typedef int __kernel_daddr_t32; -typedef int __kernel_off_t32; typedef unsigned int __kernel_caddr_t32; typedef long __kernel_loff_t32; typedef __kernel_fsid_t __kernel_fsid_t32; @@ -39,20 +28,14 @@ #define IA32_PAGE_MASK (~(IA32_PAGE_SIZE - 1)) #define IA32_PAGE_ALIGN(addr) (((addr) + IA32_PAGE_SIZE - 1) & IA32_PAGE_MASK) #define IA32_CLOCKS_PER_SEC 100 /* Cast in stone for IA32 Linux */ -#define IA32_TICK(tick) ((unsigned long long)(tick) * IA32_CLOCKS_PER_SEC / CLOCKS_PER_SEC) - -struct timespec32 { - int tv_sec; - int tv_nsec; -}; /* fcntl.h */ struct flock32 { short l_type; short l_whence; - __kernel_off_t32 l_start; - __kernel_off_t32 l_len; - __kernel_pid_t32 l_pid; + compat_off_t l_start; + compat_off_t l_len; + compat_pid_t l_pid; }; #define F_GETLK64 12 @@ -130,6 +113,44 @@ unsigned int cr2; }; +/* user.h */ +/* + * IA32 (Pentium III/4) FXSR, SSE support + * + * Provide support for the GDB 5.0+ PTRACE_{GET|SET}FPXREGS requests for + * interacting with the FXSR-format floating point environment. Floating + * point data can be accessed in the regular format in the usual manner, + * and both the standard and SIMD floating point data can be accessed via + * the new ptrace requests. In either case, changes to the FPU environment + * will be reflected in the task's state as expected. + */ +struct ia32_user_i387_struct { + int cwd; + int swd; + int twd; + int fip; + int fcs; + int foo; + int fos; + int st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */ +}; + +struct ia32_user_fxsr_struct { + unsigned short cwd; + unsigned short swd; + unsigned short twd; + unsigned short fop; + int fip; + int fcs; + int foo; + int fos; + int mxcsr; + int reserved; + int st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ + int xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */ + int padding[56]; +}; + /* signal.h */ #define _IA32_NSIG 64 #define _IA32_NSIG_BPW 32 @@ -177,29 +198,6 @@ sigset_t uc_sigmask; /* mask last for extensibility */ }; -struct stat32 { - unsigned short st_dev; - unsigned short __pad1; - unsigned int st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned short st_rdev; - unsigned short __pad2; - unsigned int st_size; - unsigned int st_blksize; - unsigned int st_blocks; - unsigned int st_atime; - unsigned int __unused1; - unsigned int st_mtime; - unsigned int __unused2; - unsigned int st_ctime; - unsigned int __unused3; - unsigned int __unused4; - unsigned int __unused5; -}; - struct stat64 { unsigned short st_dev; unsigned char __pad0[10]; @@ -216,11 +214,11 @@ unsigned int st_blocks; /* Number 512-byte blocks allocated. */ unsigned int __pad4; /* future possible st_blocks high bits */ unsigned int st_atime; - unsigned int __pad5; + unsigned int st_atime_nsec; unsigned int st_mtime; - unsigned int __pad6; + unsigned int st_mtime_nsec; unsigned int st_ctime; - unsigned int __pad7; /* will be high 32 bits of ctime someday */ + unsigned int st_ctime_nsec; unsigned int st_ino_lo; unsigned int st_ino_hi; }; @@ -275,8 +273,8 @@ unsigned int _pid; /* which child */ unsigned int _uid; /* sender's uid */ int _status; /* exit code */ - __kernel_clock_t32 _utime; - __kernel_clock_t32 _stime; + compat_clock_t _utime; + compat_clock_t _stime; } _sigchld; /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ @@ -462,6 +460,8 @@ #define IA32_PTRACE_SETREGS 13 #define IA32_PTRACE_GETFPREGS 14 #define IA32_PTRACE_SETFPREGS 15 +#define IA32_PTRACE_GETFPXREGS 18 +#define IA32_PTRACE_SETFPXREGS 19 #define ia32_start_thread(regs,new_ip,new_sp) do { \ set_fs(USER_DS); \ diff -Nru a/include/asm-ia64/intrinsics.h b/include/asm-ia64/intrinsics.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-ia64/intrinsics.h Wed Jan 15 16:57:29 2003 @@ -0,0 +1,176 @@ +#ifndef _ASM_IA64_INTRINSICS_H +#define _ASM_IA64_INTRINSICS_H + +/* + * Compiler-dependent intrinsics. + * + * Copyright (C) 2002-2003 Hewlett-Packard Co + * David Mosberger-Tang + */ + +#include + +/* + * Force an unresolved reference if someone tries to use + * ia64_fetch_and_add() with a bad value. + */ +extern unsigned long __bad_size_for_ia64_fetch_and_add (void); +extern unsigned long __bad_increment_for_ia64_fetch_and_add (void); + +#define IA64_FETCHADD(tmp,v,n,sz) \ +({ \ + switch (sz) { \ + case 4: \ + __asm__ __volatile__ ("fetchadd4.rel %0=[%1],%2" \ + : "=r"(tmp) : "r"(v), "i"(n) : "memory"); \ + break; \ + \ + case 8: \ + __asm__ __volatile__ ("fetchadd8.rel %0=[%1],%2" \ + : "=r"(tmp) : "r"(v), "i"(n) : "memory"); \ + break; \ + \ + default: \ + __bad_size_for_ia64_fetch_and_add(); \ + } \ +}) + +#define ia64_fetch_and_add(i,v) \ +({ \ + __u64 _tmp; \ + volatile __typeof__(*(v)) *_v = (v); \ + switch (i) { \ + case -16: IA64_FETCHADD(_tmp, _v, -16, sizeof(*(v))); break; \ + case -8: IA64_FETCHADD(_tmp, _v, -8, sizeof(*(v))); break; \ + case -4: IA64_FETCHADD(_tmp, _v, -4, sizeof(*(v))); break; \ + case -1: IA64_FETCHADD(_tmp, _v, -1, sizeof(*(v))); break; \ + case 1: IA64_FETCHADD(_tmp, _v, 1, sizeof(*(v))); break; \ + case 4: IA64_FETCHADD(_tmp, _v, 4, sizeof(*(v))); break; \ + case 8: IA64_FETCHADD(_tmp, _v, 8, sizeof(*(v))); break; \ + case 16: IA64_FETCHADD(_tmp, _v, 16, sizeof(*(v))); break; \ + default: \ + _tmp = __bad_increment_for_ia64_fetch_and_add(); \ + break; \ + } \ + (__typeof__(*(v))) (_tmp + (i)); /* return new value */ \ +}) + +/* + * This function doesn't exist, so you'll get a linker error if + * something tries to do an invalid xchg(). + */ +extern void __xchg_called_with_bad_pointer (void); + +static __inline__ unsigned long +__xchg (unsigned long x, volatile void *ptr, int size) +{ + unsigned long result; + + switch (size) { + case 1: + __asm__ __volatile ("xchg1 %0=[%1],%2" : "=r" (result) + : "r" (ptr), "r" (x) : "memory"); + return result; + + case 2: + __asm__ __volatile ("xchg2 %0=[%1],%2" : "=r" (result) + : "r" (ptr), "r" (x) : "memory"); + return result; + + case 4: + __asm__ __volatile ("xchg4 %0=[%1],%2" : "=r" (result) + : "r" (ptr), "r" (x) : "memory"); + return result; + + case 8: + __asm__ __volatile ("xchg8 %0=[%1],%2" : "=r" (result) + : "r" (ptr), "r" (x) : "memory"); + return result; + } + __xchg_called_with_bad_pointer(); + return x; +} + +#define xchg(ptr,x) \ + ((__typeof__(*(ptr))) __xchg ((unsigned long) (x), (ptr), sizeof(*(ptr)))) + +/* + * Atomic compare and exchange. Compare OLD with MEM, if identical, + * store NEW in MEM. Return the initial value in MEM. Success is + * indicated by comparing RETURN with OLD. + */ + +#define __HAVE_ARCH_CMPXCHG 1 + +/* + * This function doesn't exist, so you'll get a linker error + * if something tries to do an invalid cmpxchg(). + */ +extern long __cmpxchg_called_with_bad_pointer(void); + +#define ia64_cmpxchg(sem,ptr,old,new,size) \ +({ \ + __typeof__(ptr) _p_ = (ptr); \ + __typeof__(new) _n_ = (new); \ + __u64 _o_, _r_; \ + \ + switch (size) { \ + case 1: _o_ = (__u8 ) (long) (old); break; \ + case 2: _o_ = (__u16) (long) (old); break; \ + case 4: _o_ = (__u32) (long) (old); break; \ + case 8: _o_ = (__u64) (long) (old); break; \ + default: break; \ + } \ + __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(_o_)); \ + switch (size) { \ + case 1: \ + __asm__ __volatile__ ("cmpxchg1."sem" %0=[%1],%2,ar.ccv" \ + : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ + break; \ + \ + case 2: \ + __asm__ __volatile__ ("cmpxchg2."sem" %0=[%1],%2,ar.ccv" \ + : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ + break; \ + \ + case 4: \ + __asm__ __volatile__ ("cmpxchg4."sem" %0=[%1],%2,ar.ccv" \ + : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ + break; \ + \ + case 8: \ + __asm__ __volatile__ ("cmpxchg8."sem" %0=[%1],%2,ar.ccv" \ + : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ + break; \ + \ + default: \ + _r_ = __cmpxchg_called_with_bad_pointer(); \ + break; \ + } \ + (__typeof__(old)) _r_; \ +}) + +#define cmpxchg_acq(ptr,o,n) ia64_cmpxchg("acq", (ptr), (o), (n), sizeof(*(ptr))) +#define cmpxchg_rel(ptr,o,n) ia64_cmpxchg("rel", (ptr), (o), (n), sizeof(*(ptr))) + +/* for compatibility with other platforms: */ +#define cmpxchg(ptr,o,n) cmpxchg_acq(ptr,o,n) + +#ifdef CONFIG_IA64_DEBUG_CMPXCHG +# define CMPXCHG_BUGCHECK_DECL int _cmpxchg_bugcheck_count = 128; +# define CMPXCHG_BUGCHECK(v) \ + do { \ + if (_cmpxchg_bugcheck_count-- <= 0) { \ + void *ip; \ + extern int printk(const char *fmt, ...); \ + asm ("mov %0=ip" : "=r"(ip)); \ + printk("CMPXCHG_BUGCHECK: stuck at %p on word %p\n", ip, (v)); \ + break; \ + } \ + } while (0) +#else /* !CONFIG_IA64_DEBUG_CMPXCHG */ +# define CMPXCHG_BUGCHECK_DECL +# define CMPXCHG_BUGCHECK(v) +#endif /* !CONFIG_IA64_DEBUG_CMPXCHG */ + +#endif /* _ASM_IA64_INTRINSICS_H */ diff -Nru a/include/asm-ia64/machvec_sn2.h b/include/asm-ia64/machvec_sn2.h --- a/include/asm-ia64/machvec_sn2.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/machvec_sn2.h Wed Jan 15 16:57:29 2003 @@ -33,34 +33,33 @@ #ifndef _ASM_IA64_MACHVEC_SN2_H #define _ASM_IA64_MACHVEC_SN2_H -extern ia64_mv_setup_t sn1_setup; +extern ia64_mv_setup_t sn_setup; extern ia64_mv_cpu_init_t sn_cpu_init; -extern ia64_mv_irq_init_t sn1_irq_init; +extern ia64_mv_irq_init_t sn_irq_init; extern ia64_mv_map_nr_t sn2_map_nr; extern ia64_mv_send_ipi_t sn2_send_IPI; extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge; -extern ia64_mv_irq_desc sn1_irq_desc; -extern ia64_mv_irq_to_vector sn1_irq_to_vector; -extern ia64_mv_local_vector_to_irq sn1_local_vector_to_irq; -extern ia64_mv_valid_irq sn1_valid_irq; -extern ia64_mv_pci_fixup_t sn1_pci_fixup; -#ifdef Colin /* We are using the same is Generic IA64 calls defined in io.h */ -extern ia64_mv_inb_t sn1_inb; -extern ia64_mv_inw_t sn1_inw; -extern ia64_mv_inl_t sn1_inl; -extern ia64_mv_outb_t sn1_outb; -extern ia64_mv_outw_t sn1_outw; -extern ia64_mv_outl_t sn1_outl; -#endif -extern ia64_mv_pci_alloc_consistent sn1_pci_alloc_consistent; -extern ia64_mv_pci_free_consistent sn1_pci_free_consistent; -extern ia64_mv_pci_map_single sn1_pci_map_single; -extern ia64_mv_pci_unmap_single sn1_pci_unmap_single; -extern ia64_mv_pci_map_sg sn1_pci_map_sg; -extern ia64_mv_pci_unmap_sg sn1_pci_unmap_sg; -extern ia64_mv_pci_dma_sync_single sn1_pci_dma_sync_single; -extern ia64_mv_pci_dma_sync_sg sn1_pci_dma_sync_sg; -extern ia64_mv_pci_dma_address sn1_dma_address; +extern ia64_mv_irq_desc sn_irq_desc; +extern ia64_mv_irq_to_vector sn_irq_to_vector; +extern ia64_mv_local_vector_to_irq sn_local_vector_to_irq; +extern ia64_mv_pci_fixup_t sn_pci_fixup; +extern ia64_mv_inb_t sn_inb; +extern ia64_mv_inw_t sn_inw; +extern ia64_mv_inl_t sn_inl; +extern ia64_mv_outb_t sn_outb; +extern ia64_mv_outw_t sn_outw; +extern ia64_mv_outl_t sn_outl; +extern ia64_mv_mmiob_t sn2_mmiob; +extern ia64_mv_pci_alloc_consistent sn_pci_alloc_consistent; +extern ia64_mv_pci_free_consistent sn_pci_free_consistent; +extern ia64_mv_pci_map_single sn_pci_map_single; +extern ia64_mv_pci_unmap_single sn_pci_unmap_single; +extern ia64_mv_pci_map_sg sn_pci_map_sg; +extern ia64_mv_pci_unmap_sg sn_pci_unmap_sg; +extern ia64_mv_pci_dma_sync_single sn_pci_dma_sync_single; +extern ia64_mv_pci_dma_sync_sg sn_pci_dma_sync_sg; +extern ia64_mv_pci_dma_address sn_dma_address; +extern ia64_mv_pci_dma_supported sn_pci_dma_supported; /* * This stuff has dual use! @@ -69,33 +68,34 @@ * platform's machvec structure. When compiling a non-generic kernel, * the macros are used directly. */ -#define platform_name "sn2" -#define platform_setup sn1_setup -#define platform_cpu_init sn_cpu_init -#define platform_irq_init sn1_irq_init -#define platform_send_ipi sn2_send_IPI +#define platform_name "sn2" +#define platform_setup sn_setup +#define platform_cpu_init sn_cpu_init +#define platform_irq_init sn_irq_init +#define platform_map_nr sn2_map_nr +#define platform_send_ipi sn2_send_IPI #define platform_global_tlb_purge sn2_global_tlb_purge -#ifdef Colin /* We are using the same is Generic IA64 calls defined in io.h */ -#define platform_inb sn1_inb -#define platform_inw sn1_inw -#define platform_inl sn1_inl -#define platform_outb sn1_outb -#define platform_outw sn1_outw -#define platform_outl sn1_outl -#endif -#define platform_irq_desc sn1_irq_desc -#define platform_irq_to_vector sn1_irq_to_vector -#define platform_local_vector_to_irq sn1_local_vector_to_irq -#define platform_valid_irq sn1_valid_irq -#define platform_pci_dma_init machvec_noop -#define platform_pci_alloc_consistent sn1_pci_alloc_consistent -#define platform_pci_free_consistent sn1_pci_free_consistent -#define platform_pci_map_single sn1_pci_map_single -#define platform_pci_unmap_single sn1_pci_unmap_single -#define platform_pci_map_sg sn1_pci_map_sg -#define platform_pci_unmap_sg sn1_pci_unmap_sg -#define platform_pci_dma_sync_single sn1_pci_dma_sync_single -#define platform_pci_dma_sync_sg sn1_pci_dma_sync_sg -#define platform_pci_dma_address sn1_dma_address +#define platform_pci_fixup sn_pci_fixup +#define platform_inb sn_inb +#define platform_inw sn_inw +#define platform_inl sn_inl +#define platform_outb sn_outb +#define platform_outw sn_outw +#define platform_outl sn_outl +#define platform_mmiob sn2_mmiob +#define platform_irq_desc sn_irq_desc +#define platform_irq_to_vector sn_irq_to_vector +#define platform_local_vector_to_irq sn_local_vector_to_irq +#define platform_pci_dma_init machvec_noop +#define platform_pci_alloc_consistent sn_pci_alloc_consistent +#define platform_pci_free_consistent sn_pci_free_consistent +#define platform_pci_map_single sn_pci_map_single +#define platform_pci_unmap_single sn_pci_unmap_single +#define platform_pci_map_sg sn_pci_map_sg +#define platform_pci_unmap_sg sn_pci_unmap_sg +#define platform_pci_dma_sync_single sn_pci_dma_sync_single +#define platform_pci_dma_sync_sg sn_pci_dma_sync_sg +#define platform_pci_dma_address sn_dma_address +#define platform_pci_dma_supported sn_pci_dma_supported #endif /* _ASM_IA64_MACHVEC_SN2_H */ diff -Nru a/include/asm-ia64/mca.h b/include/asm-ia64/mca.h --- a/include/asm-ia64/mca.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/mca.h Wed Jan 15 16:57:28 2003 @@ -103,6 +103,8 @@ IA64_MCA_NEW_CONTEXT = -1 /* SAL to return to new context */ }; +#define MIN_STATE_AREA_SIZE 57 + typedef struct ia64_mca_os_to_sal_state_s { u64 imots_os_status; /* OS status to SAL as to what happened * with the MCA handling. @@ -133,7 +135,7 @@ extern void ia64_mca_cpe_int_handler(int,void *,struct pt_regs *); extern int ia64_log_print(int,prfunc_t); extern void ia64_mca_cmc_vector_setup(void); -extern void ia64_mca_check_errors( void ); +extern int ia64_mca_check_errors(void); extern u64 ia64_log_get(int, prfunc_t); #define PLATFORM_CALL(fn, args) printk("Platform call TBD\n") diff -Nru a/include/asm-ia64/mca_asm.h b/include/asm-ia64/mca_asm.h --- a/include/asm-ia64/mca_asm.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/mca_asm.h Wed Jan 15 16:57:29 2003 @@ -16,6 +16,7 @@ #define PSR_I 14 #define PSR_DT 17 #define PSR_RT 27 +#define PSR_MC 35 #define PSR_IT 36 #define PSR_BN 44 @@ -106,6 +107,8 @@ dep temp1 = 0, temp1, PSR_I, 1; \ ;; \ dep temp1 = 0, temp1, PSR_IC, 1; \ + ;; \ + dep temp1 = -1, temp1, PSR_MC, 1; \ ;; \ movl temp2 = start_addr; \ mov cr.ipsr = temp1; \ diff -Nru a/include/asm-ia64/mman.h b/include/asm-ia64/mman.h --- a/include/asm-ia64/mman.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/mman.h Wed Jan 15 16:57:29 2003 @@ -18,12 +18,14 @@ #define MAP_FIXED 0x10 /* Interpret addr exactly */ #define MAP_ANONYMOUS 0x20 /* don't use a file */ -#define MAP_GROWSDOWN 0x0100 /* stack-like segment */ -#define MAP_GROWSUP 0x0200 /* register stack-like segment */ -#define MAP_DENYWRITE 0x0800 /* ETXTBSY */ -#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ -#define MAP_LOCKED 0x2000 /* pages are locked */ -#define MAP_NORESERVE 0x4000 /* don't check for reservations */ +#define MAP_GROWSDOWN 0x00100 /* stack-like segment */ +#define MAP_GROWSUP 0x00200 /* register stack-like segment */ +#define MAP_DENYWRITE 0x00800 /* ETXTBSY */ +#define MAP_EXECUTABLE 0x01000 /* mark it as an executable */ +#define MAP_LOCKED 0x02000 /* pages are locked */ +#define MAP_NORESERVE 0x04000 /* don't check for reservations */ +#define MAP_POPULATE 0x08000 /* populate (prefault) pagetables */ +#define MAP_NONBLOCK 0x10000 /* do not block on IO */ #define MS_ASYNC 1 /* sync memory asynchronously */ #define MS_INVALIDATE 2 /* invalidate the caches */ diff -Nru a/include/asm-ia64/mmu.h b/include/asm-ia64/mmu.h --- a/include/asm-ia64/mmu.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/mmu.h Wed Jan 15 16:57:28 2003 @@ -1,7 +1,11 @@ #ifndef __MMU_H #define __MMU_H -/* Default "unsigned long" context */ -typedef unsigned long mm_context_t; +/* + * Type for a context number. We declare it volatile to ensure proper ordering when it's + * accessed outside of spinlock'd critical sections (e.g., as done in activate_mm() and + * init_new_context()). + */ +typedef volatile unsigned long mm_context_t; #endif diff -Nru a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h --- a/include/asm-ia64/mmu_context.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/mmu_context.h Wed Jan 15 16:57:28 2003 @@ -28,6 +28,36 @@ #include +#define MMU_CONTEXT_DEBUG 0 + +#if MMU_CONTEXT_DEBUG + +#include + +extern struct mmu_trace_entry { + char op; + u8 cpu; + u32 context; + void *mm; +} mmu_tbuf[1024]; + +extern volatile int mmu_tbuf_index; + +# define MMU_TRACE(_op,_cpu,_mm,_ctx) \ +do { \ + int i = __sync_fetch_and_add(&mmu_tbuf_index, 1) % ARRAY_SIZE(mmu_tbuf); \ + struct mmu_trace_entry e; \ + e.op = (_op); \ + e.cpu = (_cpu); \ + e.mm = (_mm); \ + e.context = (_ctx); \ + mmu_tbuf[i] = e; \ +} while (0) + +#else +# define MMU_TRACE(op,cpu,mm,ctx) do { ; } while (0) +#endif + struct ia64_ctx { spinlock_t lock; unsigned int next; /* next context number to use */ @@ -54,36 +84,44 @@ static inline void delayed_tlb_flush (void) { - extern void __flush_tlb_all (void); + extern void local_flush_tlb_all (void); if (unlikely(__get_cpu_var(ia64_need_tlb_flush))) { - __flush_tlb_all(); + local_flush_tlb_all(); __get_cpu_var(ia64_need_tlb_flush) = 0; } } -static inline void -get_new_mmu_context (struct mm_struct *mm) +static inline mm_context_t +get_mmu_context (struct mm_struct *mm) { + mm_context_t context = mm->context; + + if (context) + return context; + spin_lock(&ia64_ctx.lock); { - if (ia64_ctx.next >= ia64_ctx.limit) - wrap_mmu_context(mm); - mm->context = ia64_ctx.next++; + /* re-check, now that we've got the lock: */ + context = mm->context; + if (context == 0) { + if (ia64_ctx.next >= ia64_ctx.limit) + wrap_mmu_context(mm); + mm->context = context = ia64_ctx.next++; + } } spin_unlock(&ia64_ctx.lock); + return context; } -static inline void -get_mmu_context (struct mm_struct *mm) -{ - if (mm->context == 0) - get_new_mmu_context(mm); -} - +/* + * Initialize context number to some sane value. MM is guaranteed to be a brand-new + * address-space, so no TLB flushing is needed, ever. + */ static inline int init_new_context (struct task_struct *p, struct mm_struct *mm) { + MMU_TRACE('N', smp_processor_id(), mm, 0); mm->context = 0; return 0; } @@ -92,16 +130,17 @@ destroy_context (struct mm_struct *mm) { /* Nothing to do. */ + MMU_TRACE('D', smp_processor_id(), mm, mm->context); } static inline void -reload_context (struct mm_struct *mm) +reload_context (mm_context_t context) { unsigned long rid; unsigned long rid_incr = 0; unsigned long rr0, rr1, rr2, rr3, rr4; - rid = mm->context << 3; /* make space for encoding the region number */ + rid = context << 3; /* make space for encoding the region number */ rid_incr = 1 << 8; /* encode the region id, preferred page size, and VHPT enable bit: */ @@ -124,6 +163,20 @@ ia64_insn_group_barrier(); } +static inline void +activate_context (struct mm_struct *mm) +{ + mm_context_t context; + + do { + context = get_mmu_context(mm); + MMU_TRACE('A', smp_processor_id(), mm, context); + reload_context(context); + MMU_TRACE('a', smp_processor_id(), mm, context); + /* in the unlikely event of a TLB-flush by another thread, redo the load: */ + } while (unlikely(context != mm->context)); +} + /* * Switch from address space PREV to address space NEXT. */ @@ -133,12 +186,11 @@ delayed_tlb_flush(); /* - * We may get interrupts here, but that's OK because interrupt - * handlers cannot touch user-space. + * We may get interrupts here, but that's OK because interrupt handlers cannot + * touch user-space. */ ia64_set_kr(IA64_KR_PT_BASE, __pa(next->pgd)); - get_mmu_context(next); - reload_context(next); + activate_context(next); } #define switch_mm(prev_mm,next_mm,next_task,cpu) activate_mm(prev_mm, next_mm) diff -Nru a/include/asm-ia64/mmzone.h b/include/asm-ia64/mmzone.h --- a/include/asm-ia64/mmzone.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/mmzone.h Wed Jan 15 16:57:29 2003 @@ -104,12 +104,22 @@ /* * Bank definitions. - * Current settings for DIG: 512MB/bank, 16GB/node. + * Configurable settings for DIG: 512MB/bank: 16GB/node, + * 2048MB/bank: 64GB/node, + * 8192MB/bank: 256GB/node. */ #define NR_BANKS_PER_NODE 32 -#define BANK_OFFSET(addr) ((unsigned long)(addr) & (BANKSIZE-1)) -#define DIG_BANKSHIFT 29 +#if defined(CONFIG_IA64_NODESIZE_16GB) +# define DIG_BANKSHIFT 29 +#elif defined(CONFIG_IA64_NODESIZE_64GB) +# define DIG_BANKSHIFT 31 +#elif defined(CONFIG_IA64_NODESIZE_256GB) +# define DIG_BANKSHIFT 33 +#else +# error Unsupported bank and nodesize! +#endif #define BANKSIZE (1UL << DIG_BANKSHIFT) +#define BANK_OFFSET(addr) ((unsigned long)(addr) & (BANKSIZE-1)) #define NR_BANKS (NR_BANKS_PER_NODE * NR_NODES) /* diff -Nru a/include/asm-ia64/module.h b/include/asm-ia64/module.h --- a/include/asm-ia64/module.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/module.h Wed Jan 15 16:57:28 2003 @@ -1,111 +1,6 @@ #ifndef _ASM_IA64_MODULE_H #define _ASM_IA64_MODULE_H -/* - * This file contains the ia64 architecture specific module code. - * - * Copyright (C) 2000 Intel Corporation. - * Copyright (C) 2000 Mike Stephens - */ -#include -#include -#include - -#define module_map(x) vmalloc(x) -#define module_unmap(x) ia64_module_unmap(x) -#define module_arch_init(x) ia64_module_init(x) - -/* - * This must match in size and layout the data created by - * modutils/obj/obj-ia64.c - */ -struct archdata { - const char *unw_table; - const char *segment_base; - const char *unw_start; - const char *unw_end; - const char *gp; -}; - -static inline void -arch_init_modules (struct module *kmod) -{ - static struct archdata archdata; - register char *kernel_gp asm ("gp"); - - archdata.gp = kernel_gp; - kmod->archdata_start = (const char *) &archdata; - kmod->archdata_end = (const char *) (&archdata + 1); -} - -/* - * functions to add/remove a modules unwind info when - * it is loaded or unloaded. - */ -static inline int -ia64_module_init (struct module *mod) -{ - struct archdata *archdata; - - if (!mod_member_present(mod, archdata_start) || !mod->archdata_start) - return 0; - archdata = (struct archdata *)(mod->archdata_start); - - if (archdata->unw_start == 0) - return 0; - - /* - * Make sure the unwind pointers are sane. - */ - - if (archdata->unw_table) { - printk(KERN_ERR "module_arch_init: archdata->unw_table must be zero.\n"); - return 1; - } - if (!mod_bound(archdata->gp, 0, mod)) { - printk(KERN_ERR "module_arch_init: archdata->gp out of bounds.\n"); - return 1; - } - if (!mod_bound(archdata->unw_start, 0, mod)) { - printk(KERN_ERR "module_arch_init: archdata->unw_start out of bounds.\n"); - return 1; - } - if (!mod_bound(archdata->unw_end, 0, mod)) { - printk(KERN_ERR "module_arch_init: archdata->unw_end out of bounds.\n"); - return 1; - } - if (!mod_bound(archdata->segment_base, 0, mod)) { - printk(KERN_ERR "module_arch_init: archdata->segment_base out of bounds.\n"); - return 1; - } - - /* - * Pointers are reasonable, add the module unwind table - */ - archdata->unw_table = unw_add_unwind_table(mod->name, - (unsigned long) archdata->segment_base, - (unsigned long) archdata->gp, - archdata->unw_start, archdata->unw_end); - return 0; -} - -static inline void -ia64_module_unmap (void * addr) -{ - struct module *mod = (struct module *) addr; - struct archdata *archdata; - - /* - * Before freeing the module memory remove the unwind table entry - */ - if (mod_member_present(mod, archdata_start) && mod->archdata_start) { - archdata = (struct archdata *)(mod->archdata_start); - - if (archdata->unw_table != NULL) - unw_remove_unwind_table((void *) archdata->unw_table); - } - - vfree(addr); -} +/* Module support currently broken (due to in-kernel module loader). */ #endif /* _ASM_IA64_MODULE_H */ diff -Nru a/include/asm-ia64/numa.h b/include/asm-ia64/numa.h --- a/include/asm-ia64/numa.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/numa.h Wed Jan 15 16:57:28 2003 @@ -62,6 +62,8 @@ extern int paddr_to_nid(unsigned long paddr); +#define local_nodeid (cpu_to_node_map[smp_processor_id()]) + #endif /* CONFIG_NUMA */ #endif /* _ASM_IA64_NUMA_H */ diff -Nru a/include/asm-ia64/page.h b/include/asm-ia64/page.h --- a/include/asm-ia64/page.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/page.h Wed Jan 15 16:57:28 2003 @@ -88,7 +88,12 @@ #define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) #ifndef CONFIG_DISCONTIGMEM -#define pfn_valid(pfn) ((pfn) < max_mapnr) +# ifdef CONFIG_VIRTUAL_MEM_MAP + extern int ia64_pfn_valid (unsigned long pfn); +# define pfn_valid(pfn) (((pfn) < max_mapnr) && ia64_pfn_valid(pfn)) +# else +# define pfn_valid(pfn) ((pfn) < max_mapnr) +# endif #define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) #define page_to_pfn(page) ((unsigned long) (page - mem_map)) #define pfn_to_page(pfn) (mem_map + (pfn)) diff -Nru a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h --- a/include/asm-ia64/pgtable.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/pgtable.h Wed Jan 15 16:57:28 2003 @@ -204,7 +204,13 @@ #define VMALLOC_START (0xa000000000000000 + 3*PERCPU_PAGE_SIZE) #define VMALLOC_VMADDR(x) ((unsigned long)(x)) -#define VMALLOC_END (0xa000000000000000 + (1UL << (4*PAGE_SHIFT - 9))) +#ifdef CONFIG_VIRTUAL_MEM_MAP +# define VMALLOC_END_INIT (0xa000000000000000 + (1UL << (4*PAGE_SHIFT - 9))) +# define VMALLOC_END vmalloc_end + extern unsigned long vmalloc_end; +#else +# define VMALLOC_END (0xa000000000000000 + (1UL << (4*PAGE_SHIFT - 9))) +#endif /* * Conversion functions: convert page frame number (pfn) and a protection value to a page @@ -422,6 +428,18 @@ typedef pte_t *pte_addr_t; +# ifdef CONFIG_VIRTUAL_MEM_MAP + + /* arch mem_map init routine is needed due to holes in a virtual mem_map */ +# define HAVE_ARCH_MEMMAP_INIT + + typedef void memmap_init_callback_t (struct page *start, unsigned long size, + int nid, unsigned long zone, unsigned long start_pfn); + + extern void arch_memmap_init (memmap_init_callback_t *callback, struct page *start, + unsigned long size, int nid, unsigned long zone, + unsigned long start_pfn); +# endif /* CONFIG_VIRTUAL_MEM_MAP */ # endif /* !__ASSEMBLY__ */ /* diff -Nru a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h --- a/include/asm-ia64/processor.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/processor.h Wed Jan 15 16:57:29 2003 @@ -2,7 +2,7 @@ #define _ASM_IA64_PROCESSOR_H /* - * Copyright (C) 1998-2002 Hewlett-Packard Co + * Copyright (C) 1998-2003 Hewlett-Packard Co * David Mosberger-Tang * Stephane Eranian * Copyright (C) 1999 Asit Mallick @@ -17,7 +17,6 @@ #include #include -#include #include #define IA64_NUM_DBG_REGS 8 @@ -79,12 +78,12 @@ #include #include -#include #include #include #include #include +#include #include #include #include @@ -224,7 +223,10 @@ struct siginfo; struct thread_struct { - __u64 flags; /* various thread flags (see IA64_THREAD_*) */ + __u32 flags; /* various thread flags (see IA64_THREAD_*) */ + /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */ + __u8 on_ustack; /* executing on user-stacks? */ + __u8 pad[3]; __u64 ksp; /* kernel stack pointer */ __u64 map_base; /* base address for get_unmapped_area() */ __u64 task_size; /* limit for task size */ @@ -278,6 +280,7 @@ #define INIT_THREAD { \ .flags = 0, \ + .on_ustack = 0, \ .ksp = 0, \ .map_base = DEFAULT_MAP_BASE, \ .task_size = DEFAULT_TASK_SIZE, \ diff -Nru a/include/asm-ia64/ptrace.h b/include/asm-ia64/ptrace.h --- a/include/asm-ia64/ptrace.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/ptrace.h Wed Jan 15 16:57:29 2003 @@ -2,7 +2,7 @@ #define _ASM_IA64_PTRACE_H /* - * Copyright (C) 1998-2002 Hewlett-Packard Co + * Copyright (C) 1998-2003 Hewlett-Packard Co * David Mosberger-Tang * Stephane Eranian * @@ -218,6 +218,13 @@ # define ia64_task_regs(t) (((struct pt_regs *) ((char *) (t) + IA64_STK_OFFSET)) - 1) # define ia64_psr(regs) ((struct ia64_psr *) &(regs)->cr_ipsr) # define user_mode(regs) (((struct ia64_psr *) &(regs)->cr_ipsr)->cpl != 0) +# define user_stack(task,regs) ((long) regs - (long) task == IA64_STK_OFFSET - sizeof(*regs)) +# define fsys_mode(task,regs) \ + ({ \ + struct task_struct *_task = (task); \ + struct pt_regs *_regs = (regs); \ + !user_mode(regs) && user_stack(task, regs); \ + }) struct task_struct; /* forward decl */ diff -Nru a/include/asm-ia64/serial.h b/include/asm-ia64/serial.h --- a/include/asm-ia64/serial.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/serial.h Wed Jan 15 16:57:29 2003 @@ -59,7 +59,6 @@ { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ - #ifdef CONFIG_SERIAL_MANY_PORTS #define EXTRA_SERIAL_PORT_DEFNS \ { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \ diff -Nru a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h --- a/include/asm-ia64/sn/addrs.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/addrs.h Wed Jan 15 16:57:29 2003 @@ -58,14 +58,14 @@ #define NODE_OFFSET(_n) (UINT64_CAST (_n) << NODE_SIZE_BITS) #endif -#define NODE_CAC_BASE(_n) (CAC_BASE + NODE_OFFSET(_n)) +#define NODE_CAC_BASE(_n) (CAC_BASE + NODE_OFFSET(_n)) #define NODE_HSPEC_BASE(_n) (HSPEC_BASE + NODE_OFFSET(_n)) #define NODE_IO_BASE(_n) (IO_BASE + NODE_OFFSET(_n)) #define NODE_MSPEC_BASE(_n) (MSPEC_BASE + NODE_OFFSET(_n)) #define NODE_UNCAC_BASE(_n) (UNCAC_BASE + NODE_OFFSET(_n)) #define TO_NODE(_n, _x) (NODE_OFFSET(_n) | ((_x) )) -#define TO_NODE_CAC(_n, _x) (NODE_CAC_BASE(_n) | ((_x) & TO_PHYS_MASK)) +#define TO_NODE_CAC(_n, _x) (NODE_CAC_BASE(_n) | ((_x) & TO_PHYS_MASK)) #define TO_NODE_UNCAC(_n, _x) (NODE_UNCAC_BASE(_n) | ((_x) & TO_PHYS_MASK)) #define TO_NODE_MSPEC(_n, _x) (NODE_MSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK)) #define TO_NODE_HSPEC(_n, _x) (NODE_HSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK)) @@ -227,8 +227,8 @@ #ifndef __ASSEMBLY__ -#define HUB_L(_a) *(_a) -#define HUB_S(_a, _d) *(_a) = (_d) +#define HUB_L(_a) (*((volatile typeof(*_a) *)_a)) +#define HUB_S(_a, _d) (*((volatile typeof(*_a) *)_a) = (_d)) #define LOCAL_HUB_L(_r) HUB_L(LOCAL_HUB_ADDR(_r)) #define LOCAL_HUB_S(_r, _d) HUB_S(LOCAL_HUB_ADDR(_r), (_d)) @@ -326,7 +326,7 @@ #define GDA_SIZE(nasid) KLD_GDA(nasid)->size #define NODE_OFFSET_TO_K0(_nasid, _off) \ - (PAGE_OFFSET | NODE_OFFSET(_nasid) | (_off)) + (CACHEABLE_MEM_SPACE | NODE_OFFSET(_nasid) | (_off)) #endif /* __ASSEMBLY__ */ diff -Nru a/include/asm-ia64/sn/alenlist.h b/include/asm-ia64/sn/alenlist.h --- a/include/asm-ia64/sn/alenlist.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/alenlist.h Wed Jan 15 16:57:29 2003 @@ -15,7 +15,7 @@ /* * An Address/Length List is used when setting up for an I/O DMA operation. - * A driver creates an Address/Length List that describes to the DMA + * A driver creates an Address/Length List that describes to the the DMA * interface where in memory the DMA should go. The bus interface sets up * mapping registers, if required, and returns a suitable list of "physical * addresses" or "I/O address" to the driver. The driver then uses these diff -Nru a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h --- a/include/asm-ia64/sn/arch.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/arch.h Wed Jan 15 16:57:29 2003 @@ -33,6 +33,7 @@ typedef u64 hubreg_t; typedef u64 mmr_t; typedef u64 nic_t; +typedef char cnodeid_t; #define CNODE_TO_CPU_BASE(_cnode) (NODEPDA(_cnode)->node_first_cpu) @@ -43,6 +44,7 @@ #define INVALID_NASID ((nasid_t)-1) #define INVALID_CNODEID ((cnodeid_t)-1) #define INVALID_PNODEID ((pnodeid_t)-1) +#define INVALID_SLAB (slabid_t)-1 #define INVALID_MODULE ((moduleid_t)-1) #define INVALID_PARTID ((partid_t)-1) diff -Nru a/include/asm-ia64/sn/ate_utils.h b/include/asm-ia64/sn/ate_utils.h --- a/include/asm-ia64/sn/ate_utils.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/ate_utils.h Wed Jan 15 16:57:29 2003 @@ -1,7 +1,7 @@ #ifndef _ASM_IA64_SN_ATE_UTILS_H #define _ASM_IA64_SN_ATE_UTILS_H -/* $Id$ +/* $Id: ate_utils.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff -Nru a/include/asm-ia64/sn/bte.h b/include/asm-ia64/sn/bte.h --- a/include/asm-ia64/sn/bte.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/bte.h Wed Jan 15 16:57:29 2003 @@ -1,26 +1,52 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * + * + * Copyright (c) 2000-2002 Silicon Graphics, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Further, this software is distributed without any warranty that it is + * free of the rightful claim of any third person regarding infringement + * or the like. Any license provided herein, whether implied or + * otherwise, applies only to this software file. Patent licenses, if + * any, provided herein do not apply to combinations of this program with + * other software, or any other product whatsoever. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, + * Mountain View, CA 94043, or: * - * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + * http://www.sgi.com + * + * For further information regarding this notice, see: + * + * http://oss.sgi.com/projects/GenInfo/NoticeExplan */ + #ifndef _ASM_IA64_SN_BTE_H #define _ASM_IA64_SN_BTE_H -#ident "$Revision: $" +#ident "$Revision: 1.1 $" #include #include #include -#define L1_CACHE_MASK (L1_CACHE_BYTES - 1) /* Mask to retrieve - * the offset into this - * cache line.*/ - /* BTE status register only supports 16 bits for length field */ -#define BTE_LEN_MASK ((1 << 16) - 1) +#define BTE_LEN_BITS (16) +#define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1) +#define BTE_MAX_XFER ((1 << BTE_LEN_BITS) * L1_CACHE_BYTES) + /* * Constants used in determining the best and worst case transfer @@ -68,13 +94,14 @@ u64 volatile notify ____cacheline_aligned; char *bte_base_addr ____cacheline_aligned; spinlock_t spinlock; - u64 idealTransferTimeout; - u64 idealTransferTimeoutReached; - u64 mostRecentSrc; - u64 mostRecentDest; - u64 mostRecentLen; - u64 mostRecentMode; - u64 volatile *mostRecentNotification; + u64 ideal_xfr_tmo; /* Time out */ + u64 ideal_xfr_tmo_cnt; + /* u64 most_recent_src; + * u64 most_recent_dest; + * u64 most_recent_len; + * u64 most_recent_mode; */ + u64 volatile *most_rcnt_na; + void *bte_test_buf; } bteinfo_t; /* Possible results from bte_copy and bte_unaligned_copy */ @@ -84,5 +111,7 @@ BTEFAIL_ERROR, /* Generic error */ BTEFAIL_DIR /* Diretory error */ } bte_result_t; + +void bte_reset_nasid(nasid_t); #endif /* _ASM_IA64_SN_BTE_H */ diff -Nru a/include/asm-ia64/sn/bte_copy.h b/include/asm-ia64/sn/bte_copy.h --- a/include/asm-ia64/sn/bte_copy.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/bte_copy.h Wed Jan 15 16:57:29 2003 @@ -1,31 +1,79 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * + * + * Copyright (c) 2000-2002 Silicon Graphics, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Further, this software is distributed without any warranty that it is + * free of the rightful claim of any third person regarding infringement + * or the like. Any license provided herein, whether implied or + * otherwise, applies only to this software file. Patent licenses, if + * any, provided herein do not apply to combinations of this program with + * other software, or any other product whatsoever. * - * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + * You should have received a copy of the GNU General Public + * License along with this program; if not, write the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, + * Mountain View, CA 94043, or: + * + * http://www.sgi.com + * + * For further information regarding this notice, see: + * + * http://oss.sgi.com/projects/GenInfo/NoticeExplan */ #ifndef _ASM_IA64_SN_BTE_COPY_H #define _ASM_IA64_SN_BTE_COPY_H -#ident "$Revision: $" +#ident "$Revision: 1.1 $" +#include +#include #include #include #include #include +#define L1_CACHE_MASK (L1_CACHE_BYTES - 1) + /* - * BTE_LOCKING support - Undefining the following line will - * adapt the bte_copy code to support one bte per cpu in + * BTE_LOCKING support - When CONFIG_IA64_SGI_BTE_LOCKING is + * not defined, the bte_copy code supports one bte per cpu in * synchronous mode. Even if bte_copy is called with a * notify address, the bte will spin and wait for the transfer * to complete. By defining the following, spin_locks and * busy checks are placed around the initiation of a BTE * transfer and multiple bte's per cpu are supported. */ +#if 0 #define CONFIG_IA64_SGI_BTE_LOCKING 1 +#endif + +/* + * Handle locking of the bte interfaces. + * + * All transfers spinlock the interface before setting up the SHUB + * registers. Sync transfers hold the lock until all processing is + * complete. Async transfers release the lock as soon as the transfer + * is initiated. + * + * To determine if an interface is available, we must check both the + * busy bit and the spinlock for that interface. + */ +#define BTE_LOCK_IF_AVAIL(_x) (\ + (*pda.cpu_bte_if[_x]->most_rcnt_na & IBLS_BUSY) && \ + (!(spin_trylock(&(pda.cpu_bte_if[_x]->spinlock)))) \ + ) /* * Some macros to simplify reading. @@ -33,39 +81,71 @@ * Start with macros to locate the BTE control registers. */ -#define BTEREG_LNSTAT_ADDR (bte->bte_base_addr) -#define BTEREG_SOURCE_ADDR (bte->bte_base_addr + IIO_IBSA0 - IIO_IBLS0) -#define BTEREG_DEST_ADDR (bte->bte_base_addr + IIO_IBDA0 - IIO_IBLS0) -#define BTEREG_CTRL_ADDR (bte->bte_base_addr + IIO_IBCT0 - IIO_IBLS0) -#define BTEREG_NOTIF_ADDR (bte->bte_base_addr + IIO_IBNA0 - IIO_IBLS0) +#define BTEREG_LNSTAT_ADDR ((u64 *)(bte->bte_base_addr)) +#define BTEREG_SRC_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_SRC)) +#define BTEREG_DEST_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_DEST)) +#define BTEREG_CTRL_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_CTRL)) +#define BTEREG_NOTIF_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_NOTIFY)) /* Some macros to force the IBCT0 value valid. */ #define BTE_VALID_MODES BTE_NOTIFY #define BTE_VLD_MODE(x) (x & BTE_VALID_MODES) -// #define DEBUG_BTE -// #define DEBUG_BTE_VERBOSE -// #define DEBUG_TIME_BTE - -#ifdef DEBUG_BTE -# define DPRINTK(x) printk x // Terse -# ifdef DEBUG_BTE_VERBOSE -# define DPRINTKV(x) printk x // Verbose +// #define BTE_DEBUG +// #define BTE_DEBUG_VERBOSE +// #define BTE_TIME + +#ifdef BTE_DEBUG +# define BTE_PRINTK(x) printk x /* Terse */ +# ifdef BTE_DEBUG_VERBOSE +# define BTE_PRINTKV(x) printk x /* Verbose */ # else -# define DPRINTKV(x) -# endif +# define BTE_PRINTKV(x) +# endif /* BTE_DEBUG_VERBOSE */ #else -# define DPRINTK(x) -# define DPRINTKV(x) -#endif - -#ifdef DEBUG_TIME_BTE -extern u64 BteSetupTime; -extern u64 BteTransferTime; -extern u64 BteTeardownTime; -extern u64 BteExecuteTime; -#endif +# define BTE_PRINTK(x) +# define BTE_PRINTKV(x) +#endif /* BTE_DEBUG */ + +#define BTE_IDEAL_TMO(x) (jiffies + \ + (HZ / BTE_MAXT_LINES_PER_SECOND * x)) + +#ifdef BTE_TIME +volatile extern u64 bte_setup_time; +volatile extern u64 bte_transfer_time; +volatile extern u64 bte_tear_down_time; +volatile extern u64 bte_execute_time; + +#define BTE_TIME_DECLARE() \ + u64 btcp_strt_tm = 0; \ + u64 btcp_cplt_tm = 0; \ + u64 xfr_strt_tm = 0; \ + u64 xfr_cplt_tm = 0; \ + +#define BTE_TIME_START() \ + btcp_strt_tm = xfr_strt_tm = xfr_cplt_tm = ia64_get_itc(); + +#define BTE_TIME_XFR_START() \ + xfr_strt_tm = ia64_get_itc(); + +#define BTE_TIME_XFR_STOP() \ + xfr_cplt_tm = ia64_get_itc(); + +#define BTE_TIME_STOP() \ + btcp_cplt_tm = ia64_get_itc(); \ + bte_setup_time = xfr_strt_tm - btcp_strt_tm; \ + bte_transfer_time = xfr_cplt_tm - xfr_strt_tm; \ + bte_tear_down_time = btcp_cplt_tm - xfr_cplt_tm; \ + bte_execute_time = btcp_cplt_tm - btcp_strt_tm; \ + +#else /* BTE_TIME */ +#define BTE_TIME_DECLARE() +#define BTE_TIME_START() +#define BTE_TIME_XFR_START() +#define BTE_TIME_XFR_STOP() +#define BTE_TIME_STOP() +#endif /* BTE_TIME */ /* * bte_copy(src, dest, len, mode, notification) @@ -91,25 +171,19 @@ { #ifdef CONFIG_IA64_SGI_BTE_LOCKING int bte_to_use; -#endif - -#ifdef DEBUG_TIME_BTE - u64 invokeTime = 0; - u64 completeTime = 0; - u64 xferStartTime = 0; - u64 xferCompleteTime = 0; -#endif - u64 transferSize; +#endif /* CONFIG_IA64_SGI_BTE_LOCKING */ + u64 transfer_size; + u64 lines_remaining; bteinfo_t *bte; + BTE_TIME_DECLARE(); -#ifdef DEBUG_TIME_BTE - invokeTime = ia64_get_itc(); -#endif + BTE_TIME_START(); - DPRINTK(("bte_copy (0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx)\n", - src, dest, len, mode, notification)); + BTE_PRINTK(("bte_copy (0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx)\n", + src, dest, len, mode, notification)); if (len == 0) { + BTE_TIME_STOP(); return (BTE_SUCCESS); } @@ -123,17 +197,15 @@ bte_to_use = 0; /* Attempt to lock one of the BTE interfaces */ - while ((*pda.cpubte[bte_to_use]-> - mostRecentNotification & IBLS_BUSY) - && - (!(spin_trylock - (&(pda.cpubte[bte_to_use]->spinlock)))) - && (bte_to_use < BTES_PER_NODE)) { + while ((bte_to_use < BTES_PER_NODE) && + BTE_LOCK_IF_AVAIL(bte_to_use)) { + bte_to_use++; } if ((bte_to_use >= BTES_PER_NODE) && !(mode & BTE_WACQUIRE)) { + BTE_TIME_STOP(); return (BTEFAIL_NOTAVAIL); } @@ -141,12 +213,12 @@ } while (bte_to_use >= BTES_PER_NODE); - bte = pda.cpubte[bte_to_use]; - DPRINTKV(("Got a lock on bte %d\n", bte_to_use)); + bte = pda.cpu_bte_if[bte_to_use]; + BTE_PRINTKV(("Got a lock on bte %d\n", bte_to_use)); #else /* Assuming one BTE per CPU. */ - bte = pda.cpubte[0]; -#endif + bte = pda->cpu_bte_if[0]; +#endif /* CONFIG_IA64_SGI_BTE_LOCKING */ /* * The following are removed for optimization but is @@ -160,65 +232,51 @@ */ if (notification == NULL) { /* User does not want to be notified. */ - bte->mostRecentNotification = &bte->notify; + bte->most_rcnt_na = &bte->notify; } else { - bte->mostRecentNotification = notification; + bte->most_rcnt_na = notification; } /* Calculate the number of cache lines to transfer. */ - transferSize = ((len >> L1_CACHE_SHIFT) & BTE_LEN_MASK); + transfer_size = ((len >> L1_CACHE_SHIFT) & BTE_LEN_MASK); - DPRINTKV(("Calculated transfer size of %d cache lines\n", - transferSize)); + BTE_PRINTKV(("Calculated transfer size of %d cache lines\n", + transfer_size)); /* Initialize the notification to a known value. */ - *bte->mostRecentNotification = -1L; + *bte->most_rcnt_na = -1L; - DPRINTKV(("Before, status is 0x%lx and notify is 0x%lx\n", - HUB_L(BTEREG_LNSTAT_ADDR), - *bte->mostRecentNotification)); + BTE_PRINTKV(("Before, status is 0x%lx and notify is 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + *bte->most_rcnt_na)); /* Set the status reg busy bit and transfer length */ - DPRINTKV(("IBLS - HUB_S(0x%lx, 0x%lx)\n", - BTEREG_LNSTAT_ADDR, IBLS_BUSY | transferSize)); - HUB_S(BTEREG_LNSTAT_ADDR, IBLS_BUSY | transferSize); - - - DPRINTKV(("After setting status, status is 0x%lx and notify is 0x%lx\n", HUB_L(BTEREG_LNSTAT_ADDR), *bte->mostRecentNotification)); + BTE_PRINTKV(("IBLS - HUB_S(0x%lx, 0x%lx)\n", + BTEREG_LNSTAT_ADDR, IBLS_BUSY | transfer_size)); + HUB_S(BTEREG_LNSTAT_ADDR, (IBLS_BUSY | transfer_size)); /* Set the source and destination registers */ - DPRINTKV(("IBSA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_SOURCE_ADDR, - src)); - HUB_S(BTEREG_SOURCE_ADDR, src); - DPRINTKV(("IBDA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_DEST_ADDR, dest)); - HUB_S(BTEREG_DEST_ADDR, dest); - + BTE_PRINTKV(("IBSA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_SRC_ADDR, + (TO_PHYS(src)))); + HUB_S(BTEREG_SRC_ADDR, (TO_PHYS(src))); + BTE_PRINTKV(("IBDA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_DEST_ADDR, + (TO_PHYS(dest)))); + HUB_S(BTEREG_DEST_ADDR, (TO_PHYS(dest))); /* Set the notification register */ - DPRINTKV(("IBNA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_NOTIF_ADDR, - __pa(bte->mostRecentNotification))); - HUB_S(BTEREG_NOTIF_ADDR, (__pa(bte->mostRecentNotification))); - - - DPRINTKV(("Set Notify, status is 0x%lx and notify is 0x%lx\n", - HUB_L(BTEREG_LNSTAT_ADDR), - *bte->mostRecentNotification)); + BTE_PRINTKV(("IBNA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_NOTIF_ADDR, + (TO_PHYS(__pa(bte->most_rcnt_na))))); + HUB_S(BTEREG_NOTIF_ADDR, (TO_PHYS(__pa(bte->most_rcnt_na)))); /* Initiate the transfer */ - DPRINTKV(("IBCT - HUB_S(0x%lx, 0x%lx)\n", BTEREG_CTRL_ADDR, mode)); -#ifdef DEBUG_TIME_BTE - xferStartTime = ia64_get_itc(); -#endif + BTE_PRINTKV(("IBCT - HUB_S(0x%lx, 0x%lx)\n", BTEREG_CTRL_ADDR, mode)); + BTE_TIME_XFR_START(); HUB_S(BTEREG_CTRL_ADDR, BTE_VLD_MODE(mode)); - DPRINTKV(("Initiated, status is 0x%lx and notify is 0x%lx\n", - HUB_L(BTEREG_LNSTAT_ADDR), - *bte->mostRecentNotification)); - - // >>> Temporarily work around not getting a notification - // from medusa. - // *bte->mostRecentNotification = HUB_L(bte->bte_base_addr); + BTE_PRINTKV(("Initiated, status is 0x%lx and notify is 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + *bte->most_rcnt_na)); if (notification == NULL) { /* @@ -240,56 +298,75 @@ * delay from hardware completing our request and * our detecting the failure. */ - bte->idealTransferTimeout = jiffies + - (HZ / BTE_MAXT_LINES_PER_SECOND * transferSize); + bte->ideal_xfr_tmo = BTE_IDEAL_TMO(transfer_size); - while ((IBLS_BUSY & bte->notify)) { + while (bte->notify == -1UL) { /* * Notification Workaround: When the max * theoretical time has elapsed, read the hub * status register into the notification area. * This fakes the shub performing the copy. */ - if (time_after(jiffies, bte->idealTransferTimeout)) { - bte->notify = HUB_L(bte->bte_base_addr); - bte->idealTransferTimeoutReached++; - bte->idealTransferTimeout = jiffies + - (HZ / BTE_MAXT_LINES_PER_SECOND * - (bte->notify & BTE_LEN_MASK)); + BTE_PRINTKV((" Timing. IBLS = 0x%lx, " + "notify= 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + bte->notify)); + if (time_after(jiffies, bte->ideal_xfr_tmo)) { + lines_remaining = HUB_L(BTEREG_LNSTAT_ADDR) & + BTE_LEN_MASK; + bte->ideal_xfr_tmo_cnt++; + bte->ideal_xfr_tmo = + BTE_IDEAL_TMO(lines_remaining); + + BTE_PRINTKV((" Timeout. cpu %d " + "IBLS = 0x%lx, " + "notify= 0x%lx, " + "Lines remaining = %d. " + "New timeout = %d.\n", + smp_processor_id(), + HUB_L(BTEREG_LNSTAT_ADDR), + bte->notify, + lines_remaining, + bte->ideal_xfr_tmo)); } } -#ifdef DEBUG_TIME_BTE - xferCompleteTime = ia64_get_itc(); -#endif + BTE_PRINTKV((" Delay Done. IBLS = 0x%lx, notify= 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + bte->notify)); + BTE_TIME_XFR_STOP(); if (bte->notify & IBLS_ERROR) { /* >>> Need to do real error checking. */ - transferSize = 0; + transfer_size = 0; #ifdef CONFIG_IA64_SGI_BTE_LOCKING spin_unlock(&(bte->spinlock)); -#endif +#endif /* CONFIG_IA64_SGI_BTE_LOCKING */ + BTE_PRINTKV(("Erroring status is 0x%lx and " + "notify is 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + bte->notify)); + + BTE_TIME_STOP(); + bte->notify = 0L; return (BTEFAIL_ERROR); } } #ifdef CONFIG_IA64_SGI_BTE_LOCKING spin_unlock(&(bte->spinlock)); -#endif -#ifdef DEBUG_TIME_BTE - completeTime = ia64_get_itc(); +#endif /* CONFIG_IA64_SGI_BTE_LOCKING */ + BTE_TIME_STOP(); + BTE_PRINTKV(("Returning status is 0x%lx and notify is 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + *bte->most_rcnt_na)); - BteSetupTime = xferStartTime - invokeTime; - BteTransferTime = xferCompleteTime - xferStartTime; - BteTeardownTime = completeTime - xferCompleteTime; - BteExecuteTime = completeTime - invokeTime; -#endif return (BTE_SUCCESS); } /* * Define the bte_unaligned_copy as an extern. */ -extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64, char *); +extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64); /* * The following is the prefered way of calling bte_unaligned_copy @@ -299,13 +376,10 @@ * until the transfer is complete. In order to get the asynch * version of bte_copy, you must perform this check yourself. */ -#define BTE_UNALIGNED_COPY(src, dest, len, mode, bteBlock) \ - if ((len & L1_CACHE_MASK) || \ - (src & L1_CACHE_MASK) || \ - (dest & L1_CACHE_MASK)) { \ - bte_unaligned_copy (src, dest, len, mode, bteBlock); \ - } else { \ - bte_copy(src, dest, len, mode, NULL); \ - } +#define BTE_UNALIGNED_COPY(src, dest, len, mode) \ + (((len & L1_CACHE_MASK) || (src & L1_CACHE_MASK) || \ + (dest & L1_CACHE_MASK)) ? \ + bte_unaligned_copy(src, dest, len, mode) : \ + bte_copy(src, dest, len, mode, NULL)) -#endif /* _ASM_IA64_SN_BTE_COPY_H */ +#endif /* _ASM_IA64_SN_BTE_COPY_H */ diff -Nru a/include/asm-ia64/sn/clksupport.h b/include/asm-ia64/sn/clksupport.h --- a/include/asm-ia64/sn/clksupport.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/clksupport.h Wed Jan 15 16:57:29 2003 @@ -29,22 +29,30 @@ #include typedef long clkreg_t; -extern long sn_rtc_cycles_per_second; +extern unsigned long sn_rtc_cycles_per_second; #if defined(CONFIG_IA64_SGI_SN1) #include #include + +extern nasid_t master_nasid; + +#define RTC_MASK (0x007fffffffffffff) /* clocks are not synchronized yet on SN1 - used node 0 (problem if no NASID 0) */ -#define RTC_COUNTER_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_COUNTER)) -#define RTC_COMPARE_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_COMPARE_A)) -#define RTC_COMPARE_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_COMPARE_B)) -#define RTC_INT_PENDING_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_PEND_A)) -#define RTC_INT_PENDING_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_PEND_B)) -#define RTC_INT_ENABLED_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_EN_A)) -#define RTC_INT_ENABLED_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_EN_B)) -#else +#define RTC_COUNTER_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_COUNTER)) +#define RTC_COMPARE_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_COMPARE_A)) +#define RTC_COMPARE_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_COMPARE_B)) +#define RTC_INT_PENDING_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_INT_PEND_A)) +#define RTC_INT_PENDING_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_INT_PEND_B)) +#define RTC_INT_ENABLED_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_INT_EN_A)) +#define RTC_INT_ENABLED_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_INT_EN_B)) +#else /* !CONFIG_IA64_SGI_SN1 */ +#include +#include +#include #include +#define RTC_MASK (SH_RTC_MASK) #define RTC_COUNTER_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) #define RTC_COMPARE_A_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) #define RTC_COMPARE_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) @@ -52,7 +60,7 @@ #define RTC_INT_PENDING_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) #define RTC_INT_ENABLED_A_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) #define RTC_INT_ENABLED_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) -#endif +#endif /* CONFIG_IA64_SGI_SN1 */ #define GET_RTC_COUNTER() (*RTC_COUNTER_ADDR) diff -Nru a/include/asm-ia64/sn/eeprom.h b/include/asm-ia64/sn/eeprom.h --- a/include/asm-ia64/sn/eeprom.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/eeprom.h Wed Jan 15 16:57:29 2003 @@ -11,6 +11,7 @@ #ifndef _ASM_IA64_SN_EEPROM_H #define _ASM_IA64_SN_EEPROM_H +#include #include #include #include @@ -291,6 +292,8 @@ /* functions & macros for obtaining "NIC-like" strings from EEPROMs */ +#ifdef CONFIG_IA64_SGI_SN1 + int eeprom_str( char *nic_str, nasid_t nasid, int component ); int vector_eeprom_str( char *nic_str, nasid_t nasid, int component, net_vec_t path ); @@ -300,6 +303,7 @@ #define RBRICK_EEPROM_STR(s,n,p) vector_eeprom_str((s),(n),R_BRICK,p) #define VECTOR_EEPROM_STR(s,n,p) vector_eeprom_str((s),(n),VECTOR,p) +#endif /* CONFIG_IA64_SGI_SN1 */ /* functions for obtaining formatted records from EEPROMs @@ -313,13 +317,6 @@ net_vec_t path, int component ); -/* functions providing unique id's for duplonet and i/o discovery - */ - -int cbrick_uid_get( nasid_t nasid, uint64_t *uid ); -int rbrick_uid_get( nasid_t nasid, net_vec_t path, uint64_t *uid ); -int iobrick_uid_get( nasid_t nasid, uint64_t *uid ); - /* retrieve the ethernet MAC address for an I-brick */ @@ -383,9 +380,5 @@ ( IS_IOBRICK((r)) ? eeprom_vertex_info_set \ ( IO_BRICK, NASID_GET((r)), (v), 0 ) \ : nic_bridge_vertex_info((v), (r)) ) - -#define HUB_UID_GET(n,v,p) cbrick_uid_get((n),(p)) -#define ROUTER_UID_GET(d,p) rbrick_uid_get(get_nasid(),(d),(p)) -#define XBOW_UID_GET(n,p) iobrick_uid_get((n),(p)) #endif /* _ASM_IA64_SN_EEPROM_H */ diff -Nru a/include/asm-ia64/sn/fetchop.h b/include/asm-ia64/sn/fetchop.h --- a/include/asm-ia64/sn/fetchop.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/fetchop.h Wed Jan 15 16:57:29 2003 @@ -7,10 +7,11 @@ * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. */ - #ifndef _ASM_IA64_SN_FETCHOP_H #define _ASM_IA64_SN_FETCHOP_H +#include + #define FETCHOP_BASENAME "sgi_fetchop" #define FETCHOP_FULLNAME "/dev/sgi_fetchop" @@ -30,11 +31,71 @@ #define FETCHOP_CLEAR_CACHE 56 #define FETCHOP_LOAD_OP(addr, op) ( \ - *(long *)((char*) (addr) + (op))) + *(volatile long *)((char*) (addr) + (op))) #define FETCHOP_STORE_OP(addr, op, x) ( \ - *(long *)((char*) (addr) + (op)) = \ - (long) (x)) + *(volatile long *)((char*) (addr) + (op)) = (long) (x)) + +#ifdef __KERNEL__ + +/* + * Initialize a FETCHOP line. The argument should point to the beginning + * of the line. + * SN1 - region mask is in word 0, data in word 1 + * SN2 - no region mask. Data in word 0 + */ +#ifdef CONFIG_IA64_SGI_SN1 +#define FETCHOP_INIT_LINE(p) *(p) = 0xffffffffffffffffUL +#elif CONFIG_IA64_SGI_SN2 +#define FETCHOP_INIT_LINE(p) +#endif + +/* + * Convert a region 7 (kaddr) address to the address of the fetchop variable + */ +#define FETCHOP_KADDR_TO_MSPEC_ADDR(kaddr) TO_MSPEC(kaddr) + +/* + * Convert a page struct (page) address to the address of the first + * fetchop variable in the page + */ +#define FETCHOP_PAGE_TO_MSPEC_ADDR(page) FETCHOP_KADDR_TO_MSPEC_ADDR(__pa(page_address(page))) + + +/* + * Each Atomic Memory Operation (AMO formerly known as fetchop) + * variable is 64 bytes long. The first 8 bytes are used. The + * remaining 56 bytes are unaddressable due to the operation taking + * that portion of the address. + * + * NOTE: The AMO_t _MUST_ be placed in either the first or second half + * of the cache line. The cache line _MUST NOT_ be used for anything + * other than additional AMO_t entries. This is because there are two + * addresses which reference the same physical cache line. One will + * be a cached entry with the memory type bits all set. This address + * may be loaded into processor cache. The AMO_t will be referenced + * uncached via the memory special memory type. If any portion of the + * cached cache-line is modified, when that line is flushed, it will + * overwrite the uncached value in physical memory and lead to + * inconsistency. + */ +typedef struct { + +#ifdef CONFIG_IA64_SGI_SN1 + u64 permissions; +#endif + u64 variable; + +#ifdef CONFIG_IA64_SGI_SN1 + u64 unused[6]; +#else + u64 unused[7]; +#endif + +} AMO_t; + + +#endif /* __KERNEL__ */ #endif /* _ASM_IA64_SN_FETCHOP_H */ diff -Nru a/include/asm-ia64/sn/hack.h b/include/asm-ia64/sn/hack.h --- a/include/asm-ia64/sn/hack.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/hack.h Wed Jan 15 16:57:28 2003 @@ -11,6 +11,8 @@ #ifndef _ASM_IA64_SN_HACK_H #define _ASM_IA64_SN_HACK_H +#include +#include #include #include /* for copy_??_user */ @@ -22,9 +24,6 @@ struct cred { int x; }; -#define mrlock(_s, _t, _u) -#define mrunlock(_s) - /* * Hardware Graph routines that are currently stubbed! */ @@ -60,9 +59,9 @@ extern void * snia_kmem_alloc_node(register size_t, register int, cnodeid_t); extern void * snia_kmem_zalloc(size_t, int); extern void * snia_kmem_zalloc_node(register size_t, register int, cnodeid_t ); -extern void * snia_kmem_zone_alloc(register zone_t *, int); -extern zone_t * snia_kmem_zone_init(register int , char *); -extern void snia_kmem_zone_free(register zone_t *, void *); +extern void * snia_kmem_zone_alloc(register struct zone *, int); +extern struct zone * snia_kmem_zone_init(register int , char *); +extern void snia_kmem_zone_free(register struct zone *, void *); extern int is_specified(char *); extern int cap_able(uint64_t); extern int compare_and_swap_ptr(void **, void *, void *); diff -Nru a/include/asm-ia64/sn/idle.h b/include/asm-ia64/sn/idle.h --- a/include/asm-ia64/sn/idle.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/idle.h Wed Jan 15 16:57:29 2003 @@ -15,13 +15,13 @@ static __inline__ void snidle(void) { - +#if 0 #ifdef CONFIG_IA64_SGI_AUTOTEST { extern int autotest_enabled; if (autotest_enabled) { - extern void llsc_main(int, long, long); - llsc_main(smp_processor_id(), 0xe000000000000000LL, 0xe000000001000000LL); + extern void llsc_main(int); + llsc_main(smp_processor_id()); } } #endif @@ -39,16 +39,19 @@ #endif pda.idle_flag = 1; +#endif } static __inline__ void snidleoff(void) { +#if 0 /* * Turn the activity LED on. */ set_led_bits(LED_CPU_ACTIVITY, LED_CPU_ACTIVITY); pda.idle_flag = 0; +#endif } #endif /* _ASM_IA64_SN_IDLE_H */ diff -Nru a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h --- a/include/asm-ia64/sn/intr.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/intr.h Wed Jan 15 16:57:28 2003 @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_INTR_H #define _ASM_IA64_SN_INTR_H @@ -16,5 +16,9 @@ #elif defined(CONFIG_IA64_SGI_SN2) #include #endif + +extern void sn_send_IPI_phys(long, int, int); + +#define CPU_VECTOR_TO_IRQ(cpuid,vector) ((cpuid) << 8 | (vector)) #endif /* _ASM_IA64_SN_INTR_H */ diff -Nru a/include/asm-ia64/sn/ioerror.h b/include/asm-ia64/sn/ioerror.h --- a/include/asm-ia64/sn/ioerror.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/ioerror.h Wed Jan 15 16:57:28 2003 @@ -121,7 +121,7 @@ */ typedef struct io_error_s { - /* Bit fields indicating which sturcture fields are valid */ + /* Bit fields indicating which structure fields are valid */ union { struct { unsigned ievb_errortype:1; @@ -138,6 +138,7 @@ unsigned ievb_memaddr:1; unsigned ievb_epc:1; unsigned ievb_ef:1; + unsigned ievb_tnum:1; } iev_b; unsigned iev_a; } ie_v; @@ -156,13 +157,14 @@ paddr_t ie_memaddr; /* Physical memory address */ caddr_t ie_epc; /* pc when error reported */ caddr_t ie_ef; /* eframe when error reported */ - + short ie_tnum; /* Xtalk TNUM field */ } ioerror_t; #define IOERROR_INIT(e) do { (e)->ie_v.iev_a = 0; } while (0) #define IOERROR_SETVALUE(e,f,v) do { (e)->ie_ ## f = (v); (e)->ie_v.iev_b.ievb_ ## f = 1; } while (0) -#define IOERROR_FIELDVALID(e,f) (((e)->ie_v.iev_b.ievb_ ## f) != 0) -#define IOERROR_GETVALUE(e,f) (ASSERT(IOERROR_FIELDVALID(e,f)),((e)->ie_ ## f)) +#define IOERROR_FIELDVALID(e,f) ((unsigned long long)((e)->ie_v.iev_b.ievb_ ## f) != (unsigned long long) 0) +#define IOERROR_NOGETVALUE(e,f) (ASSERT(IOERROR_FIELDVALID(e,f)), ((e)->ie_ ## f)) +#define IOERROR_GETVALUE(p,e,f) ASSERT(IOERROR_FIELDVALID(e,f)); p=((e)->ie_ ## f) /* hub code likes to call the SysAD address "hubaddr" ... */ #define ie_hubaddr ie_sysioaddr diff -Nru a/include/asm-ia64/sn/iograph.h b/include/asm-ia64/sn/iograph.h --- a/include/asm-ia64/sn/iograph.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/iograph.h Wed Jan 15 16:57:28 2003 @@ -32,6 +32,7 @@ #define EDGE_LBL_CONTROLLER "controller" #define EDGE_LBL_CPU "cpu" #define EDGE_LBL_CPUNUM "cpunum" +#define EDGE_LBL_DIRECT "direct" #define EDGE_LBL_DISABLED "disabled" #define EDGE_LBL_DISK "disk" #define EDGE_LBL_DMA_ENGINE "dma_engine" /* Only available on @@ -67,6 +68,7 @@ #define EDGE_LBL_HPC "hpc" #define EDGE_LBL_GFX "gfx" #define EDGE_LBL_HUB "hub" /* For SN0 */ +#define EDGE_LBL_HW "hw" #define EDGE_LBL_SYNERGY "synergy" /* For SNIA only */ #define EDGE_LBL_IBUS "ibus" /* For EVEREST */ #define EDGE_LBL_INTERCONNECT "link" @@ -74,6 +76,8 @@ #define EDGE_LBL_IO4 "io4" /* For EVEREST */ #define EDGE_LBL_IOC3 "ioc3" #define EDGE_LBL_LUN "lun" +#define EDGE_LBL_LINUX "linux" +#define EDGE_LBL_LINUX_BUS EDGE_LBL_LINUX "/busnum" #define EDGE_LBL_MACE "mace" /* O2 mace */ #define EDGE_LBL_MACHDEP "machdep" /* Platform depedent devices */ #define EDGE_LBL_MASTER ".master" @@ -86,6 +90,9 @@ #define EDGE_LBL_NVRAM "nvram" #define EDGE_LBL_PARTITION "partition" #define EDGE_LBL_PCI "pci" +#define EDGE_LBL_PCIX "pci-x" +#define EDGE_LBL_PCIX_0 EDGE_LBL_PCIX "/0" +#define EDGE_LBL_PCIX_1 EDGE_LBL_PCIX "/1" #define EDGE_LBL_PORT "port" #define EDGE_LBL_PROM "prom" #define EDGE_LBL_RACK "rack" @@ -112,6 +119,7 @@ #define EDGE_LBL_XPLINK "xplink" /* Cross partition */ #define EDGE_LBL_XPLINK_NET "net" /* XP network devs */ #define EDGE_LBL_XPLINK_RAW "raw" /* XP Raw devs */ +#define EDGE_LBL_SLAB "slab" /* Slab of a module */ #define EDGE_LBL_XPLINK_KERNEL "kernel" /* XP kernel devs */ #define EDGE_LBL_XPLINK_ADMIN "admin" /* Partition admin */ #define EDGE_LBL_KAIO "kaio" /* Kernel async i/o poll */ @@ -202,7 +210,7 @@ #include /* For get MAX_PORT_NUM */ -int io_brick_map_widget(char, int); +int io_brick_map_widget(int, int); int io_path_map_widget(devfs_handle_t); /* @@ -210,8 +218,7 @@ */ struct io_brick_map_s { - char ibm_type; /* brick type, e.g. */ - /* 'I' for Ibrick */ + int ibm_type; /* brick type */ int ibm_map_wid[MAX_PORT_NUM]; /* wid to int map */ }; diff -Nru a/include/asm-ia64/sn/klclock.h b/include/asm-ia64/sn/klclock.h --- a/include/asm-ia64/sn/klclock.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/klclock.h Wed Jan 15 16:57:29 2003 @@ -10,6 +10,7 @@ #define _ASM_IA64_SN_KLCLOCK_H #include +#include #define RTC_BASE_ADDR (unsigned char *)(nvram_base) diff -Nru a/include/asm-ia64/sn/klconfig.h b/include/asm-ia64/sn/klconfig.h --- a/include/asm-ia64/sn/klconfig.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/klconfig.h Wed Jan 15 16:57:28 2003 @@ -55,6 +55,10 @@ #include #endif +#ifdef CONFIG_IA64_SGI_SN2 +#include +#endif + #define KLCFGINFO_MAGIC 0xbeedbabe typedef s32 klconf_off_t; @@ -335,8 +339,8 @@ #define KLCLASS_IOBRICK 0x70 /* IP35 iobrick */ -#define KLCLASS_MAX 7 /* Bump this if a new CLASS is added */ -#define KLTYPE_MAX 10 /* Bump this if a new CLASS is added */ +#define KLCLASS_MAX 8 /* Bump this if a new CLASS is added */ +#define KLTYPE_MAX 11 /* Bump this if a new CLASS is added */ #define KLCLASS_UNKNOWN 0xf0 @@ -353,7 +357,7 @@ #define KLTYPE_WEIRDCPU (KLCLASS_CPU | 0x0) #define KLTYPE_SNIA (KLCLASS_CPU | 0x1) -#define KLTYPE_WEIRDIO (KLCLASS_IO | 0x0) +#define KLTYPE_WEIRDIO (KLCLASS_IOBRICK | 0x0) #define KLTYPE_BASEIO (KLCLASS_IO | 0x1) /* IOC3, SuperIO, Bridge, SCSI */ #define KLTYPE_IO6 KLTYPE_BASEIO /* Additional name */ #define KLTYPE_4CHSCSI (KLCLASS_IO | 0x2) @@ -433,7 +437,11 @@ unsigned char brd_flags; /* Enabled, Disabled etc */ unsigned char brd_slot; /* slot number */ unsigned short brd_debugsw; /* Debug switches */ +#ifdef CONFIG_IA64_SGI_SN2 + geoid_t brd_geoid; /* geo id */ +#else moduleid_t brd_module; /* module to which it belongs */ +#endif partid_t brd_partition; /* Partition number */ unsigned short brd_diagval; /* diagnostic value */ unsigned short brd_diagparm; /* diagnostic parameter */ @@ -448,6 +456,9 @@ confidence_t brd_confidence; /* confidence that the board is bad */ nasid_t brd_owner; /* who owns this board */ unsigned char brd_nic_flags; /* To handle 8 more NICs */ +#ifdef CONFIG_IA64_SGI_SN2 + char pad[32]; /* future expansion */ +#endif char brd_name[32]; } lboard_t; @@ -570,6 +581,10 @@ #define KLSTRUCT_USB 34 #define KLSTRUCT_USBKBD 35 #define KLSTRUCT_USBMS 36 +#define KLSTRUCT_SCSI_CTLR 37 +#define KLSTRUCT_PEBRICK 38 +#define KLSTRUCT_GIGE 39 +#define KLSTRUCT_IDE 40 /* * These are the indices of various components within a lboard structure. @@ -611,6 +626,9 @@ nasid_t port_nasid; unsigned char port_flag; klconf_off_t port_offset; +#ifdef CONFIG_IA64_SGI_SN2 + short port_num; +#endif } klport_t; typedef struct klcpu_s { /* CPU */ @@ -620,6 +638,9 @@ unsigned short cpu_speed; /* Speed in MHZ */ unsigned short cpu_scachesz; /* secondary cache size in MB */ unsigned short cpu_scachespeed;/* secondary cache speed in MHz */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klcpu_t ; #define CPU_STRUCT_VERSION 2 @@ -627,16 +648,28 @@ typedef struct klhub_s { /* HUB */ klinfo_t hub_info; uint hub_flags; /* PCFG_HUB_xxx flags */ +#ifdef CONFIG_IA64_SGI_SN2 +#define MAX_NI_PORTS 2 + klport_t hub_port[MAX_NI_PORTS + 1];/* hub is connected to this */ +#else klport_t hub_port; /* hub is connected to this */ +#endif nic_t hub_box_nic; /* nic of containing box */ klconf_off_t hub_mfg_nic; /* MFG NIC string */ u64 hub_speed; /* Speed of hub in HZ */ +#ifdef CONFIG_IA64_SGI_SN2 + moduleid_t hub_io_module; /* attached io module */ + unsigned long pad; +#endif } klhub_t ; typedef struct klhub_uart_s { /* HUB */ klinfo_t hubuart_info; uint hubuart_flags; /* PCFG_HUB_xxx flags */ nic_t hubuart_box_nic; /* nic of containing box */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klhub_uart_t ; #define MEMORY_STRUCT_VERSION 2 @@ -647,6 +680,9 @@ short membnk_dimm_select; /* bank to physical addr mapping*/ short membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */ short membnk_attr; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klmembnk_t ; #define KLCONFIG_MEMBNK_SIZE(_info, _bank) \ @@ -665,6 +701,9 @@ char snum_str[MAX_SERIAL_NUM_SIZE]; unsigned long long snum_int; } snum; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klmod_serial_num_t; /* Macros needed to access serial number structure in lboard_t. @@ -682,6 +721,9 @@ klport_t xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */ int xbow_master_hub_link; /* type of brd connected+component struct ptr+flags */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klxbow_t ; #define MAX_PCI_SLOTS 8 @@ -700,6 +742,9 @@ pci_t pci_specific ; /* PCI Board config info */ klpci_device_t bri_devices[MAX_PCI_DEVS] ; /* PCI IDs */ klconf_off_t bri_mfg_nic ; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klbri_t ; #define MAX_IOC3_TTY 2 @@ -713,6 +758,9 @@ klinfo_t ioc3_enet ; klconf_off_t ioc3_enet_off ; klconf_off_t ioc3_kbd_off ; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klioc3_t ; #define MAX_VME_SLOTS 8 @@ -721,12 +769,18 @@ klinfo_t vmeb_info ; vmeb_t vmeb_specific ; klconf_off_t vmeb_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klvmeb_t ; typedef struct klvmed_s { /* VME DEVICE - VME BOARD */ klinfo_t vmed_info ; vmed_t vmed_specific ; klconf_off_t vmed_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klvmed_t ; #define ROUTER_VECTOR_VERS 2 @@ -739,6 +793,9 @@ klport_t rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */ klconf_off_t rou_mfg_nic ; /* MFG NIC string */ u64 rou_vector; /* vector from master node */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klrou_t ; /* @@ -763,16 +820,25 @@ graphics_t gfx_specific; klconf_off_t pad0; /* for compatibility with older proms */ klconf_off_t gfx_mfg_nic; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klgfx_t; typedef struct klxthd_s { klinfo_t xthd_info ; klconf_off_t xthd_mfg_nic ; /* MFG NIC string */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klxthd_t ; typedef struct kltpu_s { /* TPU board */ klinfo_t tpu_info ; klconf_off_t tpu_mfg_nic ; /* MFG NIC string */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } kltpu_t ; typedef struct klgsn_s { /* GSN board */ @@ -789,36 +855,64 @@ * that as the size to be klmalloced. */ -typedef struct klscsi_s { /* SCSI Controller */ +typedef struct klscsi_s { /* SCSI Bus */ klinfo_t scsi_info ; scsi_t scsi_specific ; unsigned char scsi_numdevs ; klconf_off_t scsi_devinfo[MAX_SCSI_DEVS] ; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klscsi_t ; +typedef struct klscctl_s { /* SCSI Controller */ + klinfo_t scsi_info ; + uint type; + uint scsi_buscnt; /* # busses this cntlr */ + void *scsi_bus[2]; /* Pointer to 2 klscsi_t's */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif +} klscctl_t ; + typedef struct klscdev_s { /* SCSI device */ klinfo_t scdev_info ; struct scsidisk_data *scdev_cfg ; /* driver fills up this */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klscdev_t ; typedef struct klttydev_s { /* TTY device */ klinfo_t ttydev_info ; struct terminal_data *ttydev_cfg ; /* driver fills up this */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klttydev_t ; typedef struct klenetdev_s { /* ENET device */ klinfo_t enetdev_info ; struct net_data *enetdev_cfg ; /* driver fills up this */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klenetdev_t ; typedef struct klkbddev_s { /* KBD device */ klinfo_t kbddev_info ; struct keyboard_data *kbddev_cfg ; /* driver fills up this */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klkbddev_t ; typedef struct klmsdev_s { /* mouse device */ klinfo_t msdev_info ; void *msdev_cfg ; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klmsdev_t ; #define MAX_FDDI_DEVS 10 /* XXX Is this true */ @@ -827,11 +921,17 @@ klinfo_t fddi_info ; fddi_t fddi_specific ; klconf_off_t fddi_devinfo[MAX_FDDI_DEVS] ; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klfddi_t ; typedef struct klmio_s { /* MIO */ klinfo_t mio_info ; mio_t mio_specific ; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klmio_t ; /* @@ -842,6 +942,9 @@ klinfo_t usb_info; /* controller info */ void *usb_bus; /* handle to usb_bus_t */ uint64_t usb_controller; /* ptr to controller info */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klusb_t ; typedef union klcomp_s { @@ -856,6 +959,7 @@ klrou_t kc_rou; klgfx_t kc_gfx; klscsi_t kc_scsi; + klscctl_t kc_scsi_ctl; klscdev_t kc_scsi_dev; klfddi_t kc_fddi; klmio_t kc_mio; @@ -929,26 +1033,38 @@ extern lboard_t *find_gfxpipe(int pipenum); extern void setup_gfxpipe_link(devfs_handle_t vhdl,int pipenum); extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class); +#ifdef CONFIG_IA64_SGI_SN2 +extern lboard_t *find_lboard_module_class(lboard_t *start, geoid_t geoid, + unsigned char brd_class); +#else extern lboard_t *find_lboard_module_class(lboard_t *start, moduleid_t mod, unsigned char brd_class); +#endif extern lboard_t *find_nic_lboard(lboard_t *, nic_t); extern lboard_t *find_nic_type_lboard(nasid_t, unsigned char, nic_t); +#ifdef CONFIG_IA64_SGI_SN2 +extern lboard_t *find_lboard_modslot(lboard_t *start, geoid_t geoid); +extern lboard_t *find_lboard_module(lboard_t *start, geoid_t geoid); +extern lboard_t *get_board_name(nasid_t nasid, geoid_t geoid, slotid_t slot, char *name); +#else extern lboard_t *find_lboard_modslot(lboard_t *start, moduleid_t mod, slotid_t slot); extern lboard_t *find_lboard_module(lboard_t *start, moduleid_t mod); extern lboard_t *get_board_name(nasid_t nasid, moduleid_t mod, slotid_t slot, char *name); +#endif extern int config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**); extern int config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**); extern int config_find_xbow(nasid_t, lboard_t **, klxbow_t**); extern int update_klcfg_cpuinfo(nasid_t, int); extern void board_to_path(lboard_t *brd, char *path); +#ifdef CONFIG_IA64_SGI_SN2 extern moduleid_t get_module_id(nasid_t nasid); +#endif extern void nic_name_convert(char *old_name, char *new_name); extern int module_brds(nasid_t nasid, lboard_t **module_brds, int n); extern lboard_t *brd_from_key(uint64_t key); extern void device_component_canonical_name_get(lboard_t *,klinfo_t *, char *); extern int board_serial_number_get(lboard_t *,char *); -extern int is_master_baseio(nasid_t,moduleid_t,slotid_t); extern nasid_t get_actual_nasid(lboard_t *brd) ; extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int); diff -Nru a/include/asm-ia64/sn/ksys/elsc.h b/include/asm-ia64/sn/ksys/elsc.h --- a/include/asm-ia64/sn/ksys/elsc.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/ksys/elsc.h Wed Jan 15 16:57:29 2003 @@ -9,8 +9,11 @@ #ifndef _ASM_SN_KSYS_ELSC_H #define _ASM_SN_KSYS_ELSC_H +#include #include +#ifdef CONFIG_IA64_SGI_SN1 + #define ELSC_ACP_MAX 86 /* 84+cr+lf */ #define ELSC_LINE_MAX (ELSC_ACP_MAX - 2) @@ -73,7 +76,6 @@ int elsc_power_cycle(elsc_t *e); int elsc_system_reset(elsc_t *e); int elsc_dip_switches(elsc_t *e); -int elsc_nic_get(elsc_t *e, uint64_t *nic, int verbose); int _elsc_hbt(elsc_t *e, int ival, int rdly); @@ -82,6 +84,9 @@ #define elsc_hbt_send(e) _elsc_hbt(e, 0, 1) elsc_t *get_elsc(void); + +#endif /* CONFIG_IA64_SGI_SN1 */ + /* * Error codes diff -Nru a/include/asm-ia64/sn/ksys/l1.h b/include/asm-ia64/sn/ksys/l1.h --- a/include/asm-ia64/sn/ksys/l1.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/ksys/l1.h Wed Jan 15 16:57:28 2003 @@ -10,11 +10,15 @@ #ifndef _ASM_SN_KSYS_L1_H #define _ASM_SN_KSYS_L1_H +#include #include #include #include #include + +#ifdef CONFIG_IA64_SGI_SN1 + #define BRL1_QSIZE 128 /* power of 2 is more efficient */ #define BRL1_BUFSZ 264 /* needs to be large enough * to hold 2 flags, escaped @@ -109,8 +113,6 @@ #define BRL1_RESET 7 -#ifndef __ASSEMBLY__ - /* * l1sc_t structure-- tracks protocol state, open subchannels, etc. */ @@ -148,7 +150,6 @@ sc_cq_t garbage_q; /* a place to put unsolicited packets */ sc_cq_t oq[BRL1_OQS]; /* elscuart output queues */ - } l1sc_t; @@ -169,6 +170,7 @@ #define SC_TIMEDOUT (-9) #define SC_NSUBCH (-10) +#endif /* CONFIG_IA64_SGI_SN1 */ /* L1 Target Addresses */ /* @@ -179,21 +181,38 @@ * id (L1 functionality is divided into several independent "tasks" * that can each receive command requests and transmit responses) */ +#ifdef CONFIG_IA64_SGI_SN1 #define L1_ADDR_TYPE_SHFT 28 #define L1_ADDR_TYPE_MASK 0xF0000000 +#else +#define L1_ADDR_TYPE_SHFT 8 +#define L1_ADDR_TYPE_MASK 0xFF00 +#endif /* CONFIG_IA64_SGI_SN1 */ #define L1_ADDR_TYPE_L1 0x00 /* L1 system controller */ #define L1_ADDR_TYPE_L2 0x01 /* L2 system controller */ #define L1_ADDR_TYPE_L3 0x02 /* L3 system controller */ #define L1_ADDR_TYPE_CBRICK 0x03 /* attached C brick */ #define L1_ADDR_TYPE_IOBRICK 0x04 /* attached I/O brick */ +#ifdef CONFIG_IA64_SGI_SN1 #define L1_ADDR_RACK_SHFT 18 #define L1_ADDR_RACK_MASK 0x0FFC0000 #define L1_ADDR_RACK_LOCAL 0x3ff /* local brick's rack */ +#else +#define L1_ADDR_RACK_SHFT 16 +#define L1_ADDR_RACK_MASK 0xFFFF00 +#define L1_ADDR_RACK_LOCAL 0xffff /* local brick's rack */ +#endif /* CONFIG_IA64_SGI_SN1 */ +#ifdef CONFIG_IA64_SGI_SN1 #define L1_ADDR_BAY_SHFT 12 #define L1_ADDR_BAY_MASK 0x0003F000 #define L1_ADDR_BAY_LOCAL 0x3f /* local brick's bay */ +#else +#define L1_ADDR_BAY_SHFT 0 +#define L1_ADDR_BAY_MASK 0xFF +#define L1_ADDR_BAY_LOCAL 0xff /* local brick's bay */ +#endif /* CONFIG_IA64_SGI_SN1 */ #define L1_ADDR_TASK_SHFT 0 #define L1_ADDR_TASK_MASK 0x0000001F @@ -268,13 +287,16 @@ #define L1_REQ_EXEC_CMD 0x0000 /* interpret and execute an ASCII command string */ - /* brick type response codes */ -#define L1_BRICKTYPE_C 0x43 -#define L1_BRICKTYPE_I 0x49 -#define L1_BRICKTYPE_P 0x50 -#define L1_BRICKTYPE_R 0x52 -#define L1_BRICKTYPE_X 0x58 +#define L1_BRICKTYPE_IP45 0x34 /* 4 */ +#define L1_BRICKTYPE_C 0x43 /* C */ +#define L1_BRICKTYPE_I 0x49 /* I */ +#define L1_BRICKTYPE_P 0x50 /* P */ +#define L1_BRICKTYPE_R 0x52 /* R */ +#define L1_BRICKTYPE_X 0x58 /* X */ +#define L1_BRICKTYPE_X2 0x59 /* Y */ +#define L1_BRICKTYPE_N 0x4e /* N */ +#define L1_BRICKTYPE_PX 0x23 /* # */ /* EEPROM codes (for the "read EEPROM" request) */ /* c brick */ @@ -306,7 +328,6 @@ (*(l1addr_t *)(addr) = (l1addr_t)(trb) | \ ((l1addr_t)(tsk) << L1_ADDR_TASK_SHFT)) - #define L1_DISPLAY_LINE_LENGTH 12 /* L1 display characters/line */ #ifdef L1_DISP_2LINES @@ -316,10 +337,12 @@ * to system software */ #endif -#define SC_EVENT_CLASS_MASK ((unsigned short)0xff00) - #define bzero(d, n) memset((d), 0, (n)) +#ifdef CONFIG_IA64_SGI_SN1 + +#define SC_EVENT_CLASS_MASK ((unsigned short)0xff00) + /* public interfaces to L1 system controller */ int sc_open( l1sc_t *sc, uint target ); @@ -348,15 +371,18 @@ #define get_l1sc get_elsc #define get_master_l1sc get_l1sc -int router_module_get( nasid_t nasid, net_vec_t path ); - int iobrick_rack_bay_type_get( l1sc_t *sc, uint *rack, uint *bay, uint *brick_type ); int iobrick_module_get( l1sc_t *sc ); int iobrick_pci_slot_pwr( l1sc_t *sc, int bus, int slot, int up ); int iobrick_pci_bus_pwr( l1sc_t *sc, int bus, int up ); int iobrick_sc_version( l1sc_t *sc, char *result ); +#else +int elsc_display_line(nasid_t nasid, char *line, int lnum); +int iobrick_rack_bay_type_get( nasid_t nasid, uint *rack, + uint *bay, uint *brick_type ); +int iobrick_module_get( nasid_t nasid ); +#endif /* CONFIG_IA64_SGI_SN1 */ -#endif /* !__ASSEMBLY__ */ #endif /* _ASM_SN_KSYS_L1_H */ diff -Nru a/include/asm-ia64/sn/leds.h b/include/asm-ia64/sn/leds.h --- a/include/asm-ia64/sn/leds.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/leds.h Wed Jan 15 16:57:28 2003 @@ -5,7 +5,7 @@ * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. - * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #include @@ -15,7 +15,7 @@ #include #ifdef CONFIG_IA64_SGI_SN1 -#define LED0 0xc0000b00100000c0LL /* ZZZ fixme */ +#define LED0 0xc0000b00100000c0LL #define LED_CPU_SHIFT 3 #else #include @@ -25,7 +25,13 @@ #define LED_CPU_HEARTBEAT 0x01 #define LED_CPU_ACTIVITY 0x02 +#ifdef LED_WAR +#define LED_ALWAYS_SET 0x64 /* SN2 hw workaround: always set 0x60 */ +#define LED_MASK_AUTOTEST 0x9e +#else /* LED_WAR */ +#define LED_ALWAYS_SET 0x00 #define LED_MASK_AUTOTEST 0xfe +#endif /* LED_WAR */ /* * Basic macros for flashing the LEDS on an SGI, SN1. @@ -34,8 +40,14 @@ static __inline__ void set_led_bits(u8 value, u8 mask) { +#if 0 pda.led_state = (pda.led_state & ~mask) | (value & mask); +#ifdef CONFIG_IA64_SGI_SN1 *pda.led_address = (long) pda.led_state; +#else + *pda.led_address = (short) pda.led_state; +#endif +#endif } #endif /* _ASM_IA64_SN_LEDS_H */ diff -Nru a/include/asm-ia64/sn/module.h b/include/asm-ia64/sn/module.h --- a/include/asm-ia64/sn/module.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/module.h Wed Jan 15 16:57:28 2003 @@ -13,12 +13,13 @@ #endif +#include #include #include #include #define MODULE_MAX 128 -#define MODULE_MAX_NODES 1 +#define MODULE_MAX_NODES 2 #define MODULE_HIST_CNT 16 #define MAX_MODULE_LEN 16 @@ -32,6 +33,127 @@ #define MODULE_FORMAT_LONG 2 +#ifdef CONFIG_IA64_SGI_SN2 + +/* + * Module id format + * + * 31-16 Rack ID (encoded class, group, number - 16-bit unsigned int) + * 15-8 Brick type (8-bit ascii character) + * 7-0 Bay (brick position in rack (0-63) - 8-bit unsigned int) + * + */ + +/* + * Macros for getting the brick type + */ +#define MODULE_BTYPE_MASK 0xff00 +#define MODULE_BTYPE_SHFT 8 +#define MODULE_GET_BTYPE(_m) (((_m) & MODULE_BTYPE_MASK) >> MODULE_BTYPE_SHFT) +#define MODULE_BT_TO_CHAR(_b) ((char)(_b)) +#define MODULE_GET_BTCHAR(_m) (MODULE_BT_TO_CHAR(MODULE_GET_BTYPE(_m))) + +/* + * Macros for getting the rack ID. + */ +#define MODULE_RACK_MASK 0xffff0000 +#define MODULE_RACK_SHFT 16 +#define MODULE_GET_RACK(_m) (((_m) & MODULE_RACK_MASK) >> MODULE_RACK_SHFT) + +/* + * Macros for getting the brick position + */ +#define MODULE_BPOS_MASK 0x00ff +#define MODULE_BPOS_SHFT 0 +#define MODULE_GET_BPOS(_m) (((_m) & MODULE_BPOS_MASK) >> MODULE_BPOS_SHFT) + +/* + * Macros for constructing moduleid_t's + */ +#define RBT_TO_MODULE(_r, _b, _t) ((_r) << MODULE_RACK_SHFT | \ + (_b) << MODULE_BPOS_SHFT | \ + (_t) << MODULE_BTYPE_SHFT) + +/* + * Macros for encoding and decoding rack IDs + * A rack number consists of three parts: + * class (0==CPU/mixed, 1==I/O), group, number + * + * Rack number is stored just as it is displayed on the screen: + * a 3-decimal-digit number. + */ +#define RACK_CLASS_DVDR 100 +#define RACK_GROUP_DVDR 10 +#define RACK_NUM_DVDR 1 + +#define RACK_CREATE_RACKID(_c, _g, _n) ((_c) * RACK_CLASS_DVDR + \ + (_g) * RACK_GROUP_DVDR + (_n) * RACK_NUM_DVDR) + +#define RACK_GET_CLASS(_r) ((_r) / RACK_CLASS_DVDR) +#define RACK_GET_GROUP(_r) (((_r) - RACK_GET_CLASS(_r) * \ + RACK_CLASS_DVDR) / RACK_GROUP_DVDR) +#define RACK_GET_NUM(_r) (((_r) - RACK_GET_CLASS(_r) * \ + RACK_CLASS_DVDR - RACK_GET_GROUP(_r) * \ + RACK_GROUP_DVDR) / RACK_NUM_DVDR) + +/* + * Macros for encoding and decoding rack IDs + * A rack number consists of three parts: + * class 1 bit, 0==CPU/mixed, 1==I/O + * group 2 bits for CPU/mixed, 3 bits for I/O + * number 3 bits for CPU/mixed, 2 bits for I/O (1 based) + */ +#define RACK_GROUP_BITS(_r) (RACK_GET_CLASS(_r) ? 3 : 2) +#define RACK_NUM_BITS(_r) (RACK_GET_CLASS(_r) ? 2 : 3) + +#define RACK_CLASS_MASK(_r) 0x20 +#define RACK_CLASS_SHFT(_r) 5 +#define RACK_ADD_CLASS(_r, _c) \ + ((_r) |= (_c) << RACK_CLASS_SHFT(_r) & RACK_CLASS_MASK(_r)) + +#define RACK_GROUP_SHFT(_r) RACK_NUM_BITS(_r) +#define RACK_GROUP_MASK(_r) \ + ( (((unsigned)1< to access subnode PDA for cnodeid/subnode */ -#define nodepda pda.p_nodepda /* Ptr to this node's PDA */ +#define nodepda pda->p_nodepda /* Ptr to this node's PDA */ #define NODEPDA(cnode) (nodepda->pernode_pdaindr[cnode]) #if defined(CONFIG_IA64_SGI_SN1) @@ -160,7 +166,11 @@ /* * Macros to access data structures inside nodepda */ +#ifdef CONFIG_IA64_SGI_SN2 +#define NODE_MODULEID(cnode) geo_module((NODEPDA(cnode)->geoid)) +#else #define NODE_MODULEID(cnode) (NODEPDA(cnode)->module_id) +#endif #define NODE_SLOTID(cnode) (NODEPDA(cnode)->slotdesc) @@ -174,8 +184,8 @@ * Check if given a compact node id the corresponding node has all the * cpus disabled. */ -#define is_headless_node(cnode) ((cnode == CNODEID_NONE) || \ - (node_data(cnode)->active_cpu_count == 0)) +#define is_headless_node(cnode) 0 /*((cnode == CNODEID_NONE) || \ + (node_data(cnode)->active_cpu_count == 0)) */ /* * Check if given a node vertex handle the corresponding node has all the diff -Nru a/include/asm-ia64/sn/pci/bridge.h b/include/asm-ia64/sn/pci/bridge.h --- a/include/asm-ia64/sn/pci/bridge.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/pci/bridge.h Wed Jan 15 16:57:28 2003 @@ -12,9 +12,40 @@ /* * bridge.h - header file for bridge chip and bridge portion of xbridge chip + * + * Also including offsets for unique PIC registers. + * The PIC asic is a follow-on to Xbridge and most of it's registers are + * identical to those of Xbridge. PIC is different than Xbridge in that + * it will accept 64 bit register access and that, in some cases, data + * is kept in bits 63:32. PIC registers that are identical to Xbridge + * may be accessed identically to the Xbridge registers, allowing for lots + * of code reuse. Here are the access rules as described in the PIC + * manual: + * + * o Read a word on a DW boundary returns D31:00 of reg. + * o Read a DW on a DW boundary returns D63:00 of reg. + * o Write a word on a DW boundary loads D31:00 of reg. + * o Write a DW on a DW boundary loads D63:00 of reg. + * o No support for word boundary access that is not double word + * aligned. + * + * So we can reuse a lot of bridge_s for PIC. In bridge_s are included + * #define tags and unions for 64 bit access to PIC registers. + * For a detailed PIC register layout see pic.h. */ +#include #include +#ifndef CONFIG_IA64_SGI_SN1 +#include + +extern int io_get_sh_swapper(nasid_t); +#define BRIDGE_REG_GET32(reg) \ + __swab32( *(volatile uint32_t *) (((uint64_t)reg)^4) ) + +#define BRIDGE_REG_SET32(reg) \ + *(volatile uint32_t *) (((uint64_t)reg)^4) +#endif /* CONFIG_IA64_SGI_SN1 */ /* I/O page size */ @@ -36,6 +67,8 @@ #define BRIDGE_ATE_RAM_SIZE (BRIDGE_INTERNAL_ATES<<3) /* 1kB ATE */ #define XBRIDGE_ATE_RAM_SIZE (XBRIDGE_INTERNAL_ATES<<3) /* 8kB ATE */ +#define PIC_WR_REQ_BUFSIZE 256 + #define BRIDGE_CONFIG_BASE 0x20000 /* start of bridge's */ /* map to each device's */ /* config space */ @@ -78,7 +111,502 @@ * Generated from Bridge spec dated 04oct95 */ -#ifdef LITTLE_ENDIAN +#ifndef CONFIG_IA64_SGI_SN1 + +/* + * pic_widget_cfg_s is a local definition of widget_cfg_t but with + * a union of 64bit & 32bit registers, since PIC has 64bit widget + * registers but BRIDGE and XBRIDGE have 32bit. PIC registers that + * have valid bits (ie. not just reserved) in the upper 32bits are + * defined as a union so we can access them as 64bit for PIC and + * as 32bit for BRIDGE and XBRIDGE. + */ +typedef volatile struct pic_widget_cfg_s { + bridgereg_t _b_wid_id; /* 0x000004 */ + bridgereg_t _pad_000000; + + union { + picreg_t _p_wid_stat; /* 0x000008 */ + struct { + bridgereg_t _b_wid_stat; /* 0x00000C */ + bridgereg_t _b_pad_000008; + } _b; + } u_wid_stat; + #define __p_wid_stat_64 u_wid_stat._p_wid_stat + #define __b_wid_stat u_wid_stat._b._b_wid_stat + + bridgereg_t _b_wid_err_upper; /* 0x000014 */ + bridgereg_t _pad_000010; + + union { + picreg_t _p_wid_err_lower; /* 0x000018 */ + struct { + bridgereg_t _b_wid_err_lower; /* 0x00001C */ + bridgereg_t _b_pad_000018; + } _b; + } u_wid_err_lower; + #define __p_wid_err_64 u_wid_err_lower._p_wid_err_lower + #define __b_wid_err_lower u_wid_err_lower._b._b_wid_err_lower + + union { + picreg_t _p_wid_control; /* 0x000020 */ + struct { + bridgereg_t _b_wid_control; /* 0x000024 */ + bridgereg_t _b_pad_000020; + } _b; + } u_wid_control; + #define __p_wid_control_64 u_wid_control._p_wid_control + #define __b_wid_control u_wid_control._b._b_wid_control + + bridgereg_t _b_wid_req_timeout; /* 0x00002C */ + bridgereg_t _pad_000028; + + bridgereg_t _b_wid_int_upper; /* 0x000034 */ + bridgereg_t _pad_000030; + + union { + picreg_t _p_wid_int_lower; /* 0x000038 */ + struct { + bridgereg_t _b_wid_int_lower; /* 0x00003C */ + bridgereg_t _b_pad_000038; + } _b; + } u_wid_int_lower; + #define __p_wid_int_64 u_wid_int_lower._p_wid_int_lower + #define __b_wid_int_lower u_wid_int_lower._b._b_wid_int_lower + + bridgereg_t _b_wid_err_cmdword; /* 0x000044 */ + bridgereg_t _pad_000040; + + bridgereg_t _b_wid_llp; /* 0x00004C */ + bridgereg_t _pad_000048; + + bridgereg_t _b_wid_tflush; /* 0x000054 */ + bridgereg_t _pad_000050; +} pic_widget_cfg_t; + +/* + * BRIDGE, XBRIDGE, PIC register definitions. NOTE: Prior to PIC, registers + * were a 32bit quantity and double word aligned (and only accessable as a + * 32bit word. PIC registers are 64bits and accessable as words or double + * words. PIC registers that have valid bits (ie. not just reserved) in the + * upper 32bits are defined as a union of one 64bit picreg_t and two 32bit + * bridgereg_t so we can access them both ways. + * + * It is generally preferred that hardware registers on the bridge are + * located from C code via this structure. + * + * Generated from Bridge spec dated 04oct95 + */ + +typedef volatile struct bridge_s { + + /* 0x000000-0x00FFFF -- Local Registers */ + + /* 0x000000-0x000057 -- Standard Widget Configuration */ + union { + widget_cfg_t xtalk_widget_def; /* 0x000000 */ + pic_widget_cfg_t local_widget_def; /* 0x000000 */ + } u_wid; + + /* 32bit widget register access via the widget_cfg_t */ + #define b_widget u_wid.xtalk_widget_def + + /* 32bit widget register access via the pic_widget_cfg_t */ + #define b_wid_id u_wid.local_widget_def._b_wid_id + #define b_wid_stat u_wid.local_widget_def.__b_wid_stat + #define b_wid_err_upper u_wid.local_widget_def._b_wid_err_upper + #define b_wid_err_lower u_wid.local_widget_def.__b_wid_err_lower + #define b_wid_control u_wid.local_widget_def.__b_wid_control + #define b_wid_req_timeout u_wid.local_widget_def._b_wid_req_timeout + #define b_wid_int_upper u_wid.local_widget_def._b_wid_int_upper + #define b_wid_int_lower u_wid.local_widget_def.__b_wid_int_lower + #define b_wid_err_cmdword u_wid.local_widget_def._b_wid_err_cmdword + #define b_wid_llp u_wid.local_widget_def._b_wid_llp + #define b_wid_tflush u_wid.local_widget_def._b_wid_tflush + + /* 64bit widget register access via the pic_widget_cfg_t */ + #define p_wid_stat_64 u_wid.local_widget_def.__p_wid_stat_64 + #define p_wid_err_64 u_wid.local_widget_def.__p_wid_err_64 + #define p_wid_control_64 u_wid.local_widget_def.__p_wid_control_64 + #define p_wid_int_64 u_wid.local_widget_def.__p_wid_int_64 + + /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */ + bridgereg_t b_wid_aux_err; /* 0x00005C */ + bridgereg_t _pad_000058; + + bridgereg_t b_wid_resp_upper; /* 0x000064 */ + bridgereg_t _pad_000060; + + union { + picreg_t _p_wid_resp_lower; /* 0x000068 */ + struct { + bridgereg_t _b_wid_resp_lower; /* 0x00006C */ + bridgereg_t _b_pad_000068; + } _b; + } u_wid_resp_lower; + #define p_wid_resp_64 u_wid_resp_lower._p_wid_resp_lower + #define b_wid_resp_lower u_wid_resp_lower._b._b_wid_resp_lower + + bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */ + bridgereg_t _pad_000070; + + union { + picreg_t _p_addr_lkerr; /* 0x000078 */ + struct { + bridgereg_t _b_pad_00007C; + bridgereg_t _b_pad_000078; + } _b; + } u_addr_lkerr; + #define p_addr_lkerr_64 u_addr_lkerr._p_addr_lkerr + + /* 0x000080-0x00008F -- PMU */ + bridgereg_t b_dir_map; /* 0x000084 */ + bridgereg_t _pad_000080; + + bridgereg_t _pad_00008C; + bridgereg_t _pad_000088; + + /* 0x000090-0x00009F -- SSRAM */ + bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */ + bridgereg_t _pad_000090; + #define b_ram_perr b_ram_perr_or_map_fault /* Bridge */ + #define b_map_fault b_ram_perr_or_map_fault /* Xbridge & PIC */ + + bridgereg_t _pad_00009C; + bridgereg_t _pad_000098; + + /* 0x0000A0-0x0000AF -- Arbitration */ + bridgereg_t b_arb; /* 0x0000A4 */ + bridgereg_t _pad_0000A0; + + bridgereg_t _pad_0000AC; + bridgereg_t _pad_0000A8; + + /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */ + union { + picreg_t _p_ate_parity_err; /* 0x0000B0 */ + struct { + bridgereg_t _b_nic; /* 0x0000B4 */ + bridgereg_t _b_pad_0000B0; + } _b; + } u_ate_parity_err_or_nic; + #define p_ate_parity_err_64 u_ate_parity_err_or_nic._p_ate_parity_err + #define b_nic u_ate_parity_err_or_nic._b._b_nic + + bridgereg_t _pad_0000BC; + bridgereg_t _pad_0000B8; + + /* 0x0000C0-0x0000FF -- PCI/GIO */ + bridgereg_t b_bus_timeout; /* 0x0000C4 */ + bridgereg_t _pad_0000C0; + #define b_pci_bus_timeout b_bus_timeout + + bridgereg_t b_pci_cfg; /* 0x0000CC */ + bridgereg_t _pad_0000C8; + + bridgereg_t b_pci_err_upper; /* 0x0000D4 */ + bridgereg_t _pad_0000D0; + #define b_gio_err_upper b_pci_err_upper + + union { + picreg_t _p_pci_err_lower; /* 0x0000D8 */ + struct { + bridgereg_t _b_pci_err_lower; /* 0x0000DC */ + bridgereg_t _b_pad_0000D8; + } _b; + } u_pci_err_lower; + #define p_pci_err_64 u_pci_err_lower._p_pci_err_lower + #define b_pci_err_lower u_pci_err_lower._b._b_pci_err_lower + #define b_gio_err_lower b_pci_err_lower + + bridgereg_t _pad_0000E0[8]; + + /* 0x000100-0x0001FF -- Interrupt */ + union { + picreg_t _p_int_status; /* 0x000100 */ + struct { + bridgereg_t _b_int_status; /* 0x000104 */ + bridgereg_t _b_pad_000100; + } _b; + } u_int_status; + #define p_int_status_64 u_int_status._p_int_status + #define b_int_status u_int_status._b._b_int_status + + union { + picreg_t _p_int_enable; /* 0x000108 */ + struct { + bridgereg_t _b_int_enable; /* 0x00010C */ + bridgereg_t _b_pad_000108; + } _b; + } u_int_enable; + #define p_int_enable_64 u_int_enable._p_int_enable + #define b_int_enable u_int_enable._b._b_int_enable + + union { + picreg_t _p_int_rst_stat; /* 0x000110 */ + struct { + bridgereg_t _b_int_rst_stat; /* 0x000114 */ + bridgereg_t _b_pad_000110; + } _b; + } u_int_rst_stat; + #define p_int_rst_stat_64 u_int_rst_stat._p_int_rst_stat + #define b_int_rst_stat u_int_rst_stat._b._b_int_rst_stat + + bridgereg_t b_int_mode; /* 0x00011C */ + bridgereg_t _pad_000118; + + bridgereg_t b_int_device; /* 0x000124 */ + bridgereg_t _pad_000120; + + bridgereg_t b_int_host_err; /* 0x00012C */ + bridgereg_t _pad_000128; + + union { + picreg_t _p_int_addr[8]; /* 0x0001{30,,,68} */ + struct { + bridgereg_t addr; /* 0x0001{34,,,6C} */ + bridgereg_t _b_pad; + } _b[8]; + } u_int_addr; + #define p_int_addr_64 u_int_addr._p_int_addr + #define b_int_addr u_int_addr._b + + union { + picreg_t _p_err_int_view; /* 0x000170 */ + struct { + bridgereg_t _b_err_int_view; /* 0x000174 */ + bridgereg_t _b_pad_000170; + } _b; + } u_err_int_view; + #define p_err_int_view_64 u_err_int_view._p_err_int_view + #define b_err_int_view u_err_int_view._b._b_err_int_view + + union { + picreg_t _p_mult_int; /* 0x000178 */ + struct { + bridgereg_t _b_mult_int; /* 0x00017C */ + bridgereg_t _b_pad_000178; + } _b; + } u_mult_int; + #define p_mult_int_64 u_mult_int._p_mult_int + #define b_mult_int u_mult_int._b._b_mult_int + + struct { + bridgereg_t intr; /* 0x0001{84,,,BC} */ + bridgereg_t __pad; + } b_force_always[8]; + + struct { + bridgereg_t intr; /* 0x0001{C4,,,FC} */ + bridgereg_t __pad; + } b_force_pin[8]; + + /* 0x000200-0x0003FF -- Device */ + struct { + bridgereg_t reg; /* 0x0002{04,,,3C} */ + bridgereg_t __pad; + } b_device[8]; + + struct { + bridgereg_t reg; /* 0x0002{44,,,7C} */ + bridgereg_t __pad; + } b_wr_req_buf[8]; + + struct { + bridgereg_t reg; /* 0x0002{84,,,8C} */ + bridgereg_t __pad; + } b_rrb_map[2]; + #define b_even_resp b_rrb_map[0].reg /* 0x000284 */ + #define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ + + bridgereg_t b_resp_status; /* 0x000294 */ + bridgereg_t _pad_000290; + + bridgereg_t b_resp_clear; /* 0x00029C */ + bridgereg_t _pad_000298; + + bridgereg_t _pad_0002A0[24]; + + /* Xbridge/PIC only */ + union { + struct { + picreg_t lower; /* 0x0003{08,,,F8} */ + picreg_t upper; /* 0x0003{00,,,F0} */ + } _p[16]; + struct { + bridgereg_t upper; /* 0x0003{04,,,F4} */ + bridgereg_t _b_pad1; + bridgereg_t lower; /* 0x0003{0C,,,FC} */ + bridgereg_t _b_pad2; + } _b[16]; + } u_buf_addr_match; + #define p_buf_addr_match_64 u_buf_addr_match._p + #define b_buf_addr_match u_buf_addr_match._b + + /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */ + struct { + bridgereg_t flush_w_touch; /* 0x000{404,,,5C4} */ + bridgereg_t __pad1; + bridgereg_t flush_wo_touch; /* 0x000{40C,,,5CC} */ + bridgereg_t __pad2; + bridgereg_t inflight; /* 0x000{414,,,5D4} */ + bridgereg_t __pad3; + bridgereg_t prefetch; /* 0x000{41C,,,5DC} */ + bridgereg_t __pad4; + bridgereg_t total_pci_retry; /* 0x000{424,,,5E4} */ + bridgereg_t __pad5; + bridgereg_t max_pci_retry; /* 0x000{42C,,,5EC} */ + bridgereg_t __pad6; + bridgereg_t max_latency; /* 0x000{434,,,5F4} */ + bridgereg_t __pad7; + bridgereg_t clear_all; /* 0x000{43C,,,5FC} */ + bridgereg_t __pad8; + } b_buf_count[8]; + + /* + * "PCI/X registers that are specific to PIC". See pic.h. + */ + + /* 0x000600-0x0009FF -- PCI/X registers */ + picreg_t p_pcix_bus_err_addr_64; /* 0x000600 */ + picreg_t p_pcix_bus_err_attr_64; /* 0x000608 */ + picreg_t p_pcix_bus_err_data_64; /* 0x000610 */ + picreg_t p_pcix_pio_split_addr_64; /* 0x000618 */ + picreg_t p_pcix_pio_split_attr_64; /* 0x000620 */ + picreg_t p_pcix_dma_req_err_attr_64; /* 0x000628 */ + picreg_t p_pcix_dma_req_err_addr_64; /* 0x000630 */ + picreg_t p_pcix_timeout_64; /* 0x000638 */ + + picreg_t _pad_000600[120]; + + /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */ + struct { + picreg_t p_buf_attr; /* 0X000{A08,,,AF8} */ + picreg_t p_buf_addr; /* 0x000{A00,,,AF0} */ + } p_pcix_read_buf_64[16]; + + struct { + picreg_t p_buf_attr; /* 0x000{B08,,,BE8} */ + picreg_t p_buf_addr; /* 0x000{B00,,,BE0} */ + picreg_t __pad1; /* 0x000{B18,,,BF8} */ + picreg_t p_buf_valid; /* 0x000{B10,,,BF0} */ + } p_pcix_write_buf_64[8]; + + /* + * end "PCI/X registers that are specific to PIC" + */ + + char _pad_000c00[0x010000 - 0x000c00]; + + /* 0x010000-0x011fff -- Internal Address Translation Entry RAM */ + /* + * Xbridge and PIC have 1024 internal ATE's and the Bridge has 128. + * Make enough room for the Xbridge/PIC ATE's and depend on runtime + * checks to limit access to bridge ATE's. + * + * In [X]bridge the internal ATE Ram is writen as double words only, + * but due to internal design issues it is read back as single words. + * i.e: + * b_int_ate_ram[index].hi.rd << 32 | xb_int_ate_ram_lo[index].rd + */ + union { + bridge_ate_t wr; /* write-only */ /* 0x01{0000,,,1FF8} */ + struct { + bridgereg_t rd; /* read-only */ /* 0x01{0004,,,1FFC} */ + bridgereg_t _p_pad; + } hi; + } b_int_ate_ram[XBRIDGE_INTERNAL_ATES]; + #define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd + + /* 0x012000-0x013fff -- Internal Address Translation Entry RAM LOW */ + struct { + bridgereg_t rd; /* read-only */ /* 0x01{2004,,,3FFC} */ + bridgereg_t _p_pad; + } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES]; + + char _pad_014000[0x18000 - 0x014000]; + + /* 0x18000-0x197F8 -- PIC Write Request Ram */ + /* 0x18000 - 0x187F8 */ + picreg_t p_wr_req_lower[PIC_WR_REQ_BUFSIZE]; + /* 0x18800 - 0x18FF8 */ + picreg_t p_wr_req_upper[PIC_WR_REQ_BUFSIZE]; + /* 0x19000 - 0x197F8 */ + picreg_t p_wr_req_parity[PIC_WR_REQ_BUFSIZE]; + + char _pad_019800[0x20000 - 0x019800]; + + /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */ + union { /* make all access sizes available. */ + uchar_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ + uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ + uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ + uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ + union { + uchar_t c[0x100 / 1]; + uint16_t s[0x100 / 2]; + uint32_t l[0x100 / 4]; + uint64_t d[0x100 / 8]; + } f[8]; + } b_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */ + + /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */ + union { /* make all access sizes available. */ + uchar_t c[0x1000 / 1]; + uint16_t s[0x1000 / 2]; + uint32_t l[0x1000 / 4]; + uint64_t d[0x1000 / 8]; + union { + uchar_t c[0x100 / 1]; + uint16_t s[0x100 / 2]; + uint32_t l[0x100 / 4]; + uint64_t d[0x100 / 8]; + } f[8]; + } b_type1_cfg; /* 0x028000-0x029000 */ + + char _pad_029000[0x007000]; /* 0x029000-0x030000 */ + + /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */ + union { + uchar_t c[8 / 1]; + uint16_t s[8 / 2]; + uint32_t l[8 / 4]; + uint64_t d[8 / 8]; + } b_pci_iack; /* 0x030000-0x030007 */ + + uchar_t _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ + + /* 0x080000-0x0FFFFF -- External Address Translation Entry RAM */ + bridge_ate_t b_ext_ate_ram[0x10000]; + + /* 0x100000-0x1FFFFF -- Reserved */ + char _pad_100000[0x200000-0x100000]; + + /* 0x200000-0xBFFFFF -- PCI/GIO Device Spaces */ + union { /* make all access sizes available. */ + uchar_t c[0x100000 / 1]; + uint16_t s[0x100000 / 2]; + uint32_t l[0x100000 / 4]; + uint64_t d[0x100000 / 8]; + } b_devio_raw[10]; + + /* b_devio macro is a bit strange; it reflects the + * fact that the Bridge ASIC provides 2M for the + * first two DevIO windows and 1M for the other six. + */ + #define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)] + + /* 0xC00000-0xFFFFFF -- External Flash Proms 1,0 */ + union { /* make all access sizes available. */ + uchar_t c[0x400000 / 1]; /* read-only */ + uint16_t s[0x400000 / 2]; /* read-write */ + uint32_t l[0x400000 / 4]; /* read-only */ + uint64_t d[0x400000 / 8]; /* read-only */ + } b_external_flash; +} bridge_t; + +#else /* CONFIG_IA64_SGI_SN1 */ + typedef volatile struct bridge_s { @@ -311,6 +839,12 @@ uint16_t s[0x1000 / 2]; uint32_t l[0x1000 / 4]; uint64_t d[0x1000 / 8]; + union { + uchar_t c[0x100 / 1]; + uint16_t s[0x100 / 2]; + uint32_t l[0x100 / 4]; + uint64_t d[0x100 / 8]; + } f[8]; } b_type1_cfg; /* 0x028000-0x029000 */ char _pad_029000[0x007000]; /* 0x029000-0x030000 */ @@ -354,286 +888,7 @@ } b_external_flash; /* 0xC00000 */ } bridge_t; -#else - -/* - * Field formats for Error Command Word and Auxillary Error Command Word - * of bridge. - */ -typedef struct bridge_err_cmdword_s { - union { - uint32_t cmd_word; - struct { - uint32_t didn:4, /* Destination ID */ - sidn:4, /* SOurce ID */ - pactyp:4, /* Packet type */ - tnum:5, /* Trans Number */ - coh:1, /* Coh Transacti */ - ds:2, /* Data size */ - gbr:1, /* GBR enable */ - vbpm:1, /* VBPM message */ - error:1, /* Error occurred */ - barr:1, /* Barrier op */ - rsvd:8; - } berr_st; - } berr_un; -} bridge_err_cmdword_t; - -typedef volatile struct bridge_s { - - /* Local Registers 0x000000-0x00FFFF */ - - /* standard widget configuration 0x000000-0x000057 */ - widget_cfg_t b_widget; /* 0x000000 */ - - /* helper fieldnames for accessing bridge widget */ - -#define b_wid_id b_widget.w_id -#define b_wid_stat b_widget.w_status -#define b_wid_err_upper b_widget.w_err_upper_addr -#define b_wid_err_lower b_widget.w_err_lower_addr -#define b_wid_control b_widget.w_control -#define b_wid_req_timeout b_widget.w_req_timeout -#define b_wid_int_upper b_widget.w_intdest_upper_addr -#define b_wid_int_lower b_widget.w_intdest_lower_addr -#define b_wid_err_cmdword b_widget.w_err_cmd_word -#define b_wid_llp b_widget.w_llp_cfg -#define b_wid_tflush b_widget.w_tflush - - /* bridge-specific widget configuration 0x000058-0x00007F */ - bridgereg_t _pad_000058; - bridgereg_t b_wid_aux_err; /* 0x00005C */ - bridgereg_t _pad_000060; - bridgereg_t b_wid_resp_upper; /* 0x000064 */ - bridgereg_t _pad_000068; - bridgereg_t b_wid_resp_lower; /* 0x00006C */ - bridgereg_t _pad_000070; - bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */ - bridgereg_t _pad_000078[2]; - - /* PMU & Map 0x000080-0x00008F */ - bridgereg_t _pad_000080; - bridgereg_t b_dir_map; /* 0x000084 */ - bridgereg_t _pad_000088[2]; - - /* SSRAM 0x000090-0x00009F */ - bridgereg_t _pad_000090; - bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */ -#define b_ram_perr b_ram_perr_or_map_fault /* Bridge */ -#define b_map_fault b_ram_perr_or_map_fault /* Xbridge */ - bridgereg_t _pad_000098[2]; - - /* Arbitration 0x0000A0-0x0000AF */ - bridgereg_t _pad_0000A0; - bridgereg_t b_arb; /* 0x0000A4 */ - bridgereg_t _pad_0000A8[2]; - - /* Number In A Can 0x0000B0-0x0000BF */ - bridgereg_t _pad_0000B0; - bridgereg_t b_nic; /* 0x0000B4 */ - bridgereg_t _pad_0000B8[2]; - - /* PCI/GIO 0x0000C0-0x0000FF */ - bridgereg_t _pad_0000C0; - bridgereg_t b_bus_timeout; /* 0x0000C4 */ -#define b_pci_bus_timeout b_bus_timeout - - bridgereg_t _pad_0000C8; - bridgereg_t b_pci_cfg; /* 0x0000CC */ - bridgereg_t _pad_0000D0; - bridgereg_t b_pci_err_upper; /* 0x0000D4 */ - bridgereg_t _pad_0000D8; - bridgereg_t b_pci_err_lower; /* 0x0000DC */ - bridgereg_t _pad_0000E0[8]; -#define b_gio_err_lower b_pci_err_lower -#define b_gio_err_upper b_pci_err_upper - - /* Interrupt 0x000100-0x0001FF */ - bridgereg_t _pad_000100; - bridgereg_t b_int_status; /* 0x000104 */ - bridgereg_t _pad_000108; - bridgereg_t b_int_enable; /* 0x00010C */ - bridgereg_t _pad_000110; - bridgereg_t b_int_rst_stat; /* 0x000114 */ - bridgereg_t _pad_000118; - bridgereg_t b_int_mode; /* 0x00011C */ - bridgereg_t _pad_000120; - bridgereg_t b_int_device; /* 0x000124 */ - bridgereg_t _pad_000128; - bridgereg_t b_int_host_err; /* 0x00012C */ - - struct { - bridgereg_t __pad; /* 0x0001{30,,,68} */ - bridgereg_t addr; /* 0x0001{34,,,6C} */ - } b_int_addr[8]; /* 0x000130 */ - - bridgereg_t _pad_000170; - bridgereg_t b_err_int_view; /* 0x000174 */ - bridgereg_t _pad_000178; - bridgereg_t b_mult_int; /* 0x00017c */ - - struct { - bridgereg_t __pad; /* 0x0001{80,,,B8} */ - bridgereg_t intr; /* 0x0001{84,,,BC} */ - } b_force_always[8]; /* 0x000180 */ - - struct { - bridgereg_t __pad; /* 0x0001{C0,,,F8} */ - bridgereg_t intr; /* 0x0001{C4,,,FC} */ - } b_force_pin[8]; /* 0x0001C0 */ - - /* Device 0x000200-0x0003FF */ - struct { - bridgereg_t __pad; /* 0x0002{00,,,38} */ - bridgereg_t reg; /* 0x0002{04,,,3C} */ - } b_device[8]; /* 0x000200 */ - - struct { - bridgereg_t __pad; /* 0x0002{40,,,78} */ - bridgereg_t reg; /* 0x0002{44,,,7C} */ - } b_wr_req_buf[8]; /* 0x000240 */ - - struct { - bridgereg_t __pad; /* 0x0002{80,,,88} */ - bridgereg_t reg; /* 0x0002{84,,,8C} */ - } b_rrb_map[2]; /* 0x000280 */ -#define b_even_resp b_rrb_map[0].reg /* 0x000284 */ -#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ - - bridgereg_t _pad_000290; - bridgereg_t b_resp_status; /* 0x000294 */ - bridgereg_t _pad_000298; - bridgereg_t b_resp_clear; /* 0x00029C */ - - bridgereg_t _pad_0002A0[24]; - - /* Xbridge only */ - struct { - bridgereg_t __pad1; /* 0x0003{00,,,F0} */ - bridgereg_t upper; /* 0x0003{04,,,F4} */ - bridgereg_t __pad2; /* 0x0003{08,,,F8} */ - bridgereg_t lower; /* 0x0003{0C,,,FC} */ - } b_buf_addr_match[16]; - - /* Performance Monitor Registers (even only) */ - struct { - bridgereg_t __pad1; /* 0x000400,,,5C0 */ - bridgereg_t flush_w_touch; /* 0x000404,,,5C4 */ - bridgereg_t __pad2; /* 0x000408,,,5C8 */ - bridgereg_t flush_wo_touch; /* 0x00040C,,,5CC */ - bridgereg_t __pad3; /* 0x000410,,,5D0 */ - bridgereg_t inflight; /* 0x000414,,,5D4 */ - bridgereg_t __pad4; /* 0x000418,,,5D8 */ - bridgereg_t prefetch; /* 0x00041C,,,5DC */ - bridgereg_t __pad5; /* 0x000420,,,5E0 */ - bridgereg_t total_pci_retry; /* 0x000424,,,5E4 */ - bridgereg_t __pad6; /* 0x000428,,,5E8 */ - bridgereg_t max_pci_retry; /* 0x00042C,,,5EC */ - bridgereg_t __pad7; /* 0x000430,,,5F0 */ - bridgereg_t max_latency; /* 0x000434,,,5F4 */ - bridgereg_t __pad8; /* 0x000438,,,5F8 */ - bridgereg_t clear_all; /* 0x00043C,,,5FC */ - } b_buf_count[8]; - - char _pad_000600[0x010000 - 0x000600]; - - /* - * The Xbridge has 1024 internal ATE's and the Bridge has 128. - * Make enough room for the Xbridge ATE's and depend on runtime - * checks to limit access to bridge ATE's. - */ - - /* Internal Address Translation Entry RAM 0x010000-0x011fff */ - union { - bridge_ate_t wr; /* write-only */ - struct { - bridgereg_t _p_pad; - bridgereg_t rd; /* read-only */ - } hi; - } b_int_ate_ram[XBRIDGE_INTERNAL_ATES]; - -#define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd - - /* the xbridge read path for internal ates starts at 0x12000. - * I don't believe we ever try to read the ates. - */ - /* Internal Address Translation Entry RAM LOW 0x012000-0x013fff */ - struct { - bridgereg_t _p_pad; - bridgereg_t rd; /* read-only */ - } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES]; - - char _pad_014000[0x20000 - 0x014000]; - - /* PCI Device Configuration Spaces 0x020000-0x027FFF */ - union { /* make all access sizes available. */ - uchar_t c[0x1000 / 1]; - uint16_t s[0x1000 / 2]; - uint32_t l[0x1000 / 4]; - uint64_t d[0x1000 / 8]; - union { - uchar_t c[0x100 / 1]; - uint16_t s[0x100 / 2]; - uint32_t l[0x100 / 4]; - uint64_t d[0x100 / 8]; - } f[8]; - } b_type0_cfg_dev[8]; /* 0x020000 */ - - - /* PCI Type 1 Configuration Space 0x028000-0x028FFF */ - union { /* make all access sizes available. */ - uchar_t c[0x1000 / 1]; - uint16_t s[0x1000 / 2]; - uint32_t l[0x1000 / 4]; - uint64_t d[0x1000 / 8]; - } b_type1_cfg; /* 0x028000-0x029000 */ - - char _pad_029000[0x007000]; /* 0x029000-0x030000 */ - - /* PCI Interrupt Acknowledge Cycle 0x030000 */ - union { - uchar_t c[8 / 1]; - uint16_t s[8 / 2]; - uint32_t l[8 / 4]; - uint64_t d[8 / 8]; - } b_pci_iack; /* 0x030000 */ - - uchar_t _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ - - /* External Address Translation Entry RAM 0x080000-0x0FFFFF */ - bridge_ate_t b_ext_ate_ram[0x10000]; - - /* Reserved 0x100000-0x1FFFFF */ - char _pad_100000[0x200000-0x100000]; - - /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */ - union { /* make all access sizes available. */ - uchar_t c[0x100000 / 1]; - uint16_t s[0x100000 / 2]; - uint32_t l[0x100000 / 4]; - uint64_t d[0x100000 / 8]; - } b_devio_raw[10]; /* 0x200000 */ - - /* b_devio macro is a bit strange; it reflects the - * fact that the Bridge ASIC provides 2M for the - * first two DevIO windows and 1M for the other six. - */ -#define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)] - - /* External Flash Proms 1,0 0xC00000-0xFFFFFF */ - union { /* make all access sizes available. */ - uchar_t c[0x400000 / 1]; /* read-only */ - uint16_t s[0x400000 / 2]; /* read-write */ - uint32_t l[0x400000 / 4]; /* read-only */ - uint64_t d[0x400000 / 8]; /* read-only */ - } b_external_flash; /* 0xC00000 */ -} bridge_t; - -#endif - - - - +#endif /* CONFIG_IA64_SGI_SN1 */ #define berr_field berr_un.berr_st @@ -873,7 +1128,12 @@ /* end of Performance Monitor Registers */ -/* Byte offset macros for Bridge I/O space */ +/* Byte offset macros for Bridge I/O space. + * + * NOTE: Where applicable please use the PCIBR_xxx or PCIBRIDGE_xxx + * macros (below) as they will handle [X]Bridge and PIC. For example, + * PCIBRIDGE_TYPE0_CFG_DEV0() vs BRIDGE_TYPE0_CFG_DEV0 + */ #define BRIDGE_ATE_RAM 0x00010000 /* Internal Addr Xlat Ram */ @@ -905,7 +1165,55 @@ #ifndef __ASSEMBLY__ #define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB) -#endif /* __ASSEMBLY__ */ + +/* + * The device space macros for PIC are more complicated because the PIC has + * two PCI/X bridges under the same widget. For PIC bus 0, the addresses are + * basically the same as for the [X]Bridge. For PIC bus 1, the addresses are + * offset by 0x800000. Here are two sets of macros. They are + * "PCIBRIDGE_xxx" that return the address based on the supplied bus number + * and also equivalent "PCIBR_xxx" macros that may be used with a + * pcibr_soft_s structure. Both should work with all bridges. + */ +#define PIC_BUS1_OFFSET 0x800000 + +#define PCIBRIDGE_TYPE0_CFG_DEV0(busnum) \ + ((busnum) ? BRIDGE_TYPE0_CFG_DEV0 + PIC_BUS1_OFFSET : \ + BRIDGE_TYPE0_CFG_DEV0) +#define PCIBRIDGE_TYPE1_CFG(busnum) \ + ((busnum) ? BRIDGE_TYPE1_CFG + PIC_BUS1_OFFSET : BRIDGE_TYPE1_CFG) +#define PCIBRIDGE_TYPE0_CFG_DEV(busnum, s) \ + (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\ + (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) +#define PCIBRIDGE_TYPE0_CFG_DEVF(busnum, s, f) \ + (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\ + (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\ + (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) +#define PCIBRIDGE_DEVIO0(busnum) ((busnum) ? \ + (BRIDGE_DEVIO0 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO0) +#define PCIBRIDGE_DEVIO1(busnum) ((busnum) ? \ + (BRIDGE_DEVIO1 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO1) +#define PCIBRIDGE_DEVIO2(busnum) ((busnum) ? \ + (BRIDGE_DEVIO2 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO2) +#define PCIBRIDGE_DEVIO(busnum, x) \ + ((x)<=1 ? PCIBRIDGE_DEVIO0(busnum)+(x)*BRIDGE_DEVIO_2MB : \ + PCIBRIDGE_DEVIO2(busnum)+((x)-2)*BRIDGE_DEVIO_1MB) + +#define PCIBR_BRIDGE_DEVIO0(ps) PCIBRIDGE_DEVIO0((ps)->bs_busnum) +#define PCIBR_BRIDGE_DEVIO1(ps) PCIBRIDGE_DEVIO1((ps)->bs_busnum) +#define PCIBR_BRIDGE_DEVIO2(ps) PCIBRIDGE_DEVIO2((ps)->bs_busnum) +#define PCIBR_BRIDGE_DEVIO(ps, s) PCIBRIDGE_DEVIO((ps)->bs_busnum, s) + +#define PCIBR_TYPE1_CFG(ps) PCIBRIDGE_TYPE1_CFG((ps)->bs_busnum) +#define PCIBR_BUS_TYPE0_CFG_DEV0(ps) PCIBR_TYPE0_CFG_DEV(ps, 0) +#define PCIBR_TYPE0_CFG_DEV(ps, s) \ + ((IS_PIC_SOFT(ps)) ? PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s+1) : \ + PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s)) +#define PCIBR_BUS_TYPE0_CFG_DEVF(ps,s,f) \ + ((IS_PIC_SOFT(ps)) ? PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,(s+1),f) : \ + PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,s,f)) + +#endif /* LANGUAGE_C */ #define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */ @@ -929,6 +1237,17 @@ #define XBRIDGE_REV_A 0x1 #define XBRIDGE_REV_B 0x2 +/* macros to determine bridge type. 'wid' == widget identification */ +#define IS_BRIDGE(wid) (XWIDGET_PART_NUM(wid) == BRIDGE_WIDGET_PART_NUM && \ + XWIDGET_MFG_NUM(wid) == BRIDGE_WIDGET_MFGR_NUM) +#define IS_XBRIDGE(wid) (XWIDGET_PART_NUM(wid) == XBRIDGE_WIDGET_PART_NUM && \ + XWIDGET_MFG_NUM(wid) == XBRIDGE_WIDGET_MFGR_NUM) +#define IS_PIC_BUS0(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS0 && \ + XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM) +#define IS_PIC_BUS1(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS1 && \ + XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM) +#define IS_PIC_BRIDGE(wid) (IS_PIC_BUS0(wid) || IS_PIC_BUS1(wid)) + /* Part + Rev numbers allows distinction and acscending sequence */ #define BRIDGE_PART_REV_A (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_A) #define BRIDGE_PART_REV_B (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_B) @@ -938,7 +1257,8 @@ #define XBRIDGE_PART_REV_B (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_B) /* Bridge widget status register bits definition */ - +#define PIC_STAT_PCIX_SPEED (0x3ull << 34) +#define PIC_STAT_PCIX_ACTIVE (0x1ull << 33) #define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24) #define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16) #define BRIDGE_STAT_FLASH_SELECT (0x1 << 6) @@ -946,7 +1266,18 @@ #define BRIDGE_STAT_PENDING (0x1F << 0) /* Bridge widget control register bits definition */ -#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31) +#define PIC_CTRL_NO_SNOOP (0x1ull << 62) +#define PIC_CTRL_RELAX_ORDER (0x1ull << 61) +#define PIC_CTRL_BUS_NUM(x) ((unsigned long long)(x) << 48) +#define PIC_CTRL_BUS_NUM_MASK (PIC_CTRL_BUS_NUM(0xff)) +#define PIC_CTRL_DEV_NUM(x) ((unsigned long long)(x) << 43) +#define PIC_CTRL_DEV_NUM_MASK (PIC_CTRL_DEV_NUM(0x1f)) +#define PIC_CTRL_FUN_NUM(x) ((unsigned long long)(x) << 40) +#define PIC_CTRL_FUN_NUM_MASK (PIC_CTRL_FUN_NUM(0x7)) +#define PIC_CTRL_PAR_EN_REQ (0x1ull << 29) +#define PIC_CTRL_PAR_EN_RESP (0x1ull << 30) +#define PIC_CTRL_PAR_EN_ATE (0x1ull << 31) +#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31) /* bridge only */ #define BRIDGE_CTRL_EN_CLK50 (0x1 << 30) #define BRIDGE_CTRL_EN_CLK40 (0x1 << 29) #define BRIDGE_CTRL_EN_CLK33 (0x1 << 28) @@ -970,6 +1301,8 @@ #define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11) #define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10) #define BRIDGE_CTRL_SYS_END (0x1 << 9) +#define BRIDGE_CTRL_PCI_SPEED (0x3 << 4) + #define BRIDGE_CTRL_BUS_SPEED(n) ((n) << 4) #define BRIDGE_CTRL_BUS_SPEED_MASK (BRIDGE_CTRL_BUS_SPEED(0x3)) #define BRIDGE_CTRL_BUS_SPEED_33 0x00 @@ -1023,6 +1356,20 @@ #define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff) /* Bridge interrupt status register bits definition */ +#define PIC_ISR_PCIX_SPLIT_MSG_PE (0x1ull << 45) +#define PIC_ISR_PCIX_SPLIT_EMSG (0x1ull << 44) +#define PIC_ISR_PCIX_SPLIT_TO (0x1ull << 43) +#define PIC_ISR_PCIX_UNEX_COMP (0x1ull << 42) +#define PIC_ISR_INT_RAM_PERR (0x1ull << 41) +#define PIC_ISR_PCIX_ARB_ERR (0x1ull << 40) +#define PIC_ISR_PCIX_REQ_TOUT (0x1ull << 39) +#define PIC_ISR_PCIX_TABORT (0x1ull << 38) +#define PIC_ISR_PCIX_PERR (0x1ull << 37) +#define PIC_ISR_PCIX_SERR (0x1ull << 36) +#define PIC_ISR_PCIX_MRETRY (0x1ull << 35) +#define PIC_ISR_PCIX_MTOUT (0x1ull << 34) +#define PIC_ISR_PCIX_DA_PARITY (0x1ull << 33) +#define PIC_ISR_PCIX_AD_PARITY (0x1ull << 32) #define BRIDGE_ISR_MULTI_ERR (0x1u << 31) /* bridge only */ #define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30) /* bridge only */ #define BRIDGE_ISR_PAGE_FAULT (0x1 << 30) /* xbridge only */ @@ -1058,12 +1405,18 @@ BRIDGE_ISR_LLP_TCTY) #define BRIDGE_ISR_PCIBUS_PIOERR \ - (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT) + (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT| \ + PIC_ISR_PCIX_MTOUT|PIC_ISR_PCIX_TABORT) #define BRIDGE_ISR_PCIBUS_ERROR \ (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| \ BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| \ - BRIDGE_ISR_PCI_PARITY) + BRIDGE_ISR_PCI_PARITY|PIC_ISR_PCIX_PERR| \ + PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_MRETRY| \ + PIC_ISR_PCIX_AD_PARITY|PIC_ISR_PCIX_DA_PARITY| \ + PIC_ISR_PCIX_REQ_TOUT|PIC_ISR_PCIX_UNEX_COMP| \ + PIC_ISR_PCIX_SPLIT_TO|PIC_ISR_PCIX_SPLIT_EMSG| \ + PIC_ISR_PCIX_SPLIT_MSG_PE) #define BRIDGE_ISR_XTALK_ERROR \ (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\ @@ -1075,20 +1428,39 @@ #define BRIDGE_ISR_ERRORS \ (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \ BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ - BRIDGE_ISR_PMU_ESIZE_FAULT) + BRIDGE_ISR_PMU_ESIZE_FAULT|PIC_ISR_PCIX_ARB_ERR| \ + PIC_ISR_INT_RAM_PERR) /* * List of Errors which are fatal and kill the sytem */ #define BRIDGE_ISR_ERROR_FATAL \ ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\ - BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY ) + BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY| \ + PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_AD_PARITY| \ + PIC_ISR_PCIX_DA_PARITY| \ + PIC_ISR_INT_RAM_PERR|PIC_ISR_PCIX_SPLIT_MSG_PE ) #define BRIDGE_ISR_ERROR_DUMP \ (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| \ - BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR) + BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ + PIC_ISR_PCIX_ARB_ERR|PIC_ISR_INT_RAM_PERR) /* Bridge interrupt enable register bits definition */ +#define PIC_IMR_PCIX_SPLIT_MSG_PE PIC_ISR_PCIX_SPLIT_MSG_PE +#define PIC_IMR_PCIX_SPLIT_EMSG PIC_ISR_PCIX_SPLIT_EMSG +#define PIC_IMR_PCIX_SPLIT_TO PIC_ISR_PCIX_SPLIT_TO +#define PIC_IMR_PCIX_UNEX_COMP PIC_ISR_PCIX_UNEX_COMP +#define PIC_IMR_INT_RAM_PERR PIC_ISR_INT_RAM_PERR +#define PIC_IMR_PCIX_ARB_ERR PIC_ISR_PCIX_ARB_ERR +#define PIC_IMR_PCIX_REQ_TOUR PIC_ISR_PCIX_REQ_TOUT +#define PIC_IMR_PCIX_TABORT PIC_ISR_PCIX_TABORT +#define PIC_IMR_PCIX_PERR PIC_ISR_PCIX_PERR +#define PIC_IMR_PCIX_SERR PIC_ISR_PCIX_SERR +#define PIC_IMR_PCIX_MRETRY PIC_ISR_PCIX_MRETRY +#define PIC_IMR_PCIX_MTOUT PIC_ISR_PCIX_MTOUT +#define PIC_IMR_PCIX_DA_PARITY PIC_ISR_PCIX_DA_PARITY +#define PIC_IMR_PCIX_AD_PARITY PIC_ISR_PCIX_AD_PARITY #define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP #define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT #define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT @@ -1116,7 +1488,46 @@ #define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK #define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x) -/* Bridge interrupt reset register bits definition */ +/* + * Bridge interrupt reset register bits definition. Note, PIC can + * reset indiviual error interrupts, BRIDGE & XBRIDGE can only do + * groups of them. + */ +#define PIC_IRR_PCIX_SPLIT_MSG_PE PIC_ISR_PCIX_SPLIT_MSG_PE +#define PIC_IRR_PCIX_SPLIT_EMSG PIC_ISR_PCIX_SPLIT_EMSG +#define PIC_IRR_PCIX_SPLIT_TO PIC_ISR_PCIX_SPLIT_TO +#define PIC_IRR_PCIX_UNEX_COMP PIC_ISR_PCIX_UNEX_COMP +#define PIC_IRR_INT_RAM_PERR PIC_ISR_INT_RAM_PERR +#define PIC_IRR_PCIX_ARB_ERR PIC_ISR_PCIX_ARB_ERR +#define PIC_IRR_PCIX_REQ_TOUT PIC_ISR_PCIX_REQ_TOUT +#define PIC_IRR_PCIX_TABORT PIC_ISR_PCIX_TABORT +#define PIC_IRR_PCIX_PERR PIC_ISR_PCIX_PERR +#define PIC_IRR_PCIX_SERR PIC_ISR_PCIX_SERR +#define PIC_IRR_PCIX_MRETRY PIC_ISR_PCIX_MRETRY +#define PIC_IRR_PCIX_MTOUT PIC_ISR_PCIX_MTOUT +#define PIC_IRR_PCIX_DA_PARITY PIC_ISR_PCIX_DA_PARITY +#define PIC_IRR_PCIX_AD_PARITY PIC_ISR_PCIX_AD_PARITY +#define PIC_IRR_PAGE_FAULT BRIDGE_ISR_PAGE_FAULT +#define PIC_IRR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP +#define PIC_IRR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT +#define PIC_IRR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT +#define PIC_IRR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR +#define PIC_IRR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR +#define PIC_IRR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR +#define PIC_IRR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP +#define PIC_IRR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW +#define PIC_IRR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR +#define PIC_IRR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR +#define PIC_IRR_LLP_RCTY BRIDGE_ISR_LLP_RCTY +#define PIC_IRR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY +#define PIC_IRR_LLP_TCTY BRIDGE_ISR_LLP_TCTY +#define PIC_IRR_PCI_ABORT BRIDGE_ISR_PCI_ABORT +#define PIC_IRR_PCI_PARITY BRIDGE_ISR_PCI_PARITY +#define PIC_IRR_PCI_SERR BRIDGE_ISR_PCI_SERR +#define PIC_IRR_PCI_PERR BRIDGE_ISR_PCI_PERR +#define PIC_IRR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT +#define PIC_IRR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT +#define PIC_IRR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT #define BRIDGE_IRR_MULTI_CLR (0x1 << 6) #define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5) #define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4) @@ -1153,6 +1564,21 @@ #define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | \ BRIDGE_ISR_GIO_MST_TIMEOUT) +#define PIC_IRR_RAM_GRP PIC_ISR_INT_RAM_PERR + +#define PIC_PCIX_GRP_CLR (PIC_IRR_PCIX_AD_PARITY | \ + PIC_IRR_PCIX_DA_PARITY | \ + PIC_IRR_PCIX_MTOUT | \ + PIC_IRR_PCIX_MRETRY | \ + PIC_IRR_PCIX_SERR | \ + PIC_IRR_PCIX_PERR | \ + PIC_IRR_PCIX_TABORT | \ + PIC_ISR_PCIX_REQ_TOUT | \ + PIC_ISR_PCIX_UNEX_COMP | \ + PIC_ISR_PCIX_SPLIT_TO | \ + PIC_ISR_PCIX_SPLIT_EMSG | \ + PIC_ISR_PCIX_SPLIT_MSG_PE) + /* Bridge INT_DEV register bits definition */ #define BRIDGE_INT_DEV_SHFT(n) ((n)*3) #define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n)) @@ -1162,6 +1588,10 @@ #define BRIDGE_INT_ADDR_HOST 0x0003FF00 #define BRIDGE_INT_ADDR_FLD 0x000000FF +/* PIC interrupt(x) register bits definition */ +#define PIC_INT_ADDR_FLD 0x00FF000000000000 +#define PIC_INT_ADDR_HOST 0x0000FFFFFFFFFFFF + #define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000 #define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000 #define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff @@ -1239,8 +1669,13 @@ /* RRB assignment register */ #define BRIDGE_RRB_EN 0x8 /* after shifting down */ #define BRIDGE_RRB_DEV 0x7 /* after shifting down */ -#define BRIDGE_RRB_VDEV 0x4 /* after shifting down */ -#define BRIDGE_RRB_PDEV 0x3 /* after shifting down */ +#define BRIDGE_RRB_VDEV 0x4 /* after shifting down, 2 virtual channels */ +#define BRIDGE_RRB_PDEV 0x3 /* after shifting down, 8 devices */ + +#define PIC_RRB_EN 0x8 /* after shifting down */ +#define PIC_RRB_DEV 0x7 /* after shifting down */ +#define PIC_RRB_VDEV 0x6 /* after shifting down, 4 virtual channels */ +#define PIC_RRB_PDEV 0x1 /* after shifting down, 4 devices */ /* RRB status register */ #define BRIDGE_RRB_VALID(r) (0x00010000<<(r)) @@ -1249,6 +1684,15 @@ /* RRB clear register */ #define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r)) +/* Defines for the virtual channels so we dont hardcode 0-3 within code */ +#define VCHAN0 0 /* virtual channel 0 (ie. the "normal" channel) */ +#define VCHAN1 1 /* virtual channel 1 */ +#define VCHAN2 2 /* virtual channel 2 - PIC only */ +#define VCHAN3 3 /* virtual channel 3 - PIC only */ + +/* PIC: PCI-X Read Buffer Attribute Register (RBAR) */ +#define NUM_RBAR 16 /* number of RBAR registers */ + /* xbox system controller declarations */ #define XBOX_BRIDGE_WID 8 #define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */ @@ -1401,8 +1845,10 @@ #define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT)) #define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT)) -#define is_xbridge(bridge) \ - (XWIDGET_PART_NUM(bridge->b_wid_id) == XBRIDGE_WIDGET_PART_NUM) +#define is_xbridge(bridge) IS_XBRIDGE(bridge->b_wid_id) +#define is_pic(bridge) IS_PIC_BRIDGE(bridge->b_wid_id) + +/* extern declarations */ #ifndef __ASSEMBLY__ diff -Nru a/include/asm-ia64/sn/pci/pci_bus_cvlink.h b/include/asm-ia64/sn/pci/pci_bus_cvlink.h --- a/include/asm-ia64/sn/pci/pci_bus_cvlink.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/pci/pci_bus_cvlink.h Wed Jan 15 16:57:29 2003 @@ -35,30 +35,33 @@ #define MAX_ATE_MAPS 1024 #define SET_PCIA64(dev) \ - (((struct sn1_device_sysdata *)((dev)->sysdata))->isa64) = 1 + (((struct sn_device_sysdata *)((dev)->sysdata))->isa64) = 1 #define IS_PCIA64(dev) (((dev)->dma_mask == 0xffffffffffffffffUL) || \ - (((struct sn1_device_sysdata *)((dev)->sysdata))->isa64)) + (((struct sn_device_sysdata *)((dev)->sysdata))->isa64)) #define IS_PCI32G(dev) ((dev)->dma_mask >= 0xffffffff) #define IS_PCI32L(dev) ((dev)->dma_mask < 0xffffffff) +#define IS_PIC_DEVICE(dev) ((struct sn_device_sysdata *)dev->sysdata)->isPIC + #define PCIDEV_VERTEX(pci_dev) \ - (((struct sn1_device_sysdata *)((pci_dev)->sysdata))->vhdl) + (((struct sn_device_sysdata *)((pci_dev)->sysdata))->vhdl) #define PCIBUS_VERTEX(pci_bus) \ - (((struct sn1_widget_sysdata *)((pci_bus)->sysdata))->vhdl) + (((struct sn_widget_sysdata *)((pci_bus)->sysdata))->vhdl) -struct sn1_widget_sysdata { +struct sn_widget_sysdata { devfs_handle_t vhdl; }; -struct sn1_device_sysdata { +struct sn_device_sysdata { devfs_handle_t vhdl; int isa64; + int isPIC; volatile unsigned int *dma_buf_sync; volatile unsigned int *xbow_buf_sync; }; -struct sn1_dma_maps_s{ +struct sn_dma_maps_s{ struct pcibr_dmamap_s dma_map; dma_addr_t dma_addr; }; diff -Nru a/include/asm-ia64/sn/pci/pci_defs.h b/include/asm-ia64/sn/pci/pci_defs.h --- a/include/asm-ia64/sn/pci/pci_defs.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/pci/pci_defs.h Wed Jan 15 16:57:28 2003 @@ -39,7 +39,7 @@ * the PCI spec. */ #define PCI_TYPE1_BUS_MASK 0x00FF0000 -#define PCI_TYPE1_SLOT_MASK 0x0000F100 +#define PCI_TYPE1_SLOT_MASK 0x0000F800 #define PCI_TYPE1_FUNC_MASK 0x00000700 #define PCI_TYPE1_REG_MASK 0x000000FF @@ -68,14 +68,14 @@ /* NOTE: if you are using a C "switch" statement to * differentiate between the Config space registers, be - * aware that PCI_CFG_CLASS_CODE and PCI_CFG_BASE_CLASS + * aware that PCI_CFG_CLASS_CODE and PCI_CFG_PROG_IF * are the same offset. */ #define PCI_CFG_REV_ID 0x08 /* Revision Id (1 byte) */ #define PCI_CFG_CLASS_CODE 0x09 /* Class Code (3 bytes) */ -#define PCI_CFG_BASE_CLASS 0x09 /* Base Class (1 byte) */ +#define PCI_CFG_PROG_IF 0x09 /* Prog Interface (1 byte) */ #define PCI_CFG_SUB_CLASS 0x0A /* Sub Class (1 byte) */ -#define PCI_CFG_PROG_IF 0x0B /* Prog Interface (1 byte) */ +#define PCI_CFG_BASE_CLASS 0x0B /* Base Class (1 byte) */ #define PCI_CFG_CACHE_LINE 0x0C /* Cache line size (1 byte) */ #define PCI_CFG_LATENCY_TIMER 0x0D /* Latency Timer (1 byte) */ @@ -99,11 +99,10 @@ #define PCI_CFG_SUBSYS_ID 0x2E /* Subsystem ID */ #define PCI_EXPANSION_ROM 0x30 /* Expansion Rom Base (4B) */ +#define PCI_CAPABILITIES_PTR 0x34 /* Capabilities Pointer */ #define PCI_INTR_LINE 0x3C /* Interrupt Line (1B) */ #define PCI_INTR_PIN 0x3D /* Interrupt Pin (1B) */ -#define PCI_MIN_GNT 0x3E /* Minimum Grant (1B) */ -#define PCI_MAX_LAT 0x3F /* Maximum Latency (1B) */ #define PCI_CFG_VEND_SPECIFIC 0x40 /* first vendor specific reg */ @@ -126,6 +125,8 @@ #define PCI_CFG_PPB_IOLIMHI 0x32 /* IO Limit Addr bits 16..31 */ #define PCI_CFG_PPB_SUB_VENDOR 0x34 /* Subsystem Vendor ID */ #define PCI_CFG_PPB_SUB_DEVICE 0x36 /* Subsystem Device ID */ +#define PCI_CFG_PPB_ROM_BASE 0x38 /* ROM base address */ +#define PCI_CFG_PPB_INT_LINE 0x3C /* Interrupt Line */ #define PCI_CFG_PPB_INT_PIN 0x3D /* Interrupt Pin */ #define PCI_CFG_PPB_BRIDGE_CTRL 0x3E /* Bridge Control */ /* XXX- these might be DEC 21152 specific */ @@ -165,6 +166,7 @@ #define PCI_STAT_F_BK_BK_CAP 0x0080 /* Fast Back-to-Back Capable */ #define PCI_STAT_UDF_SUPP 0x0040 /* UDF Supported */ #define PCI_STAT_66MHZ_CAP 0x0020 /* 66 MHz Capable */ +#define PCI_STAT_CAP_LIST 0x0010 /* Capabilities List */ /* BIST Register Layout (0x0F) */ #define PCI_BIST_BIST_CAP 0x80 /* BIST Capable */ @@ -173,13 +175,63 @@ #define PCI_BIST_CMPL_OK 0x00 /* 0 value is completion OK */ /* Base Address Register 0x10 */ +#define PCI_BA_IO_CODEMASK 0x3 /* bottom 2 bits encode I/O BAR type */ #define PCI_BA_IO_SPACE 0x1 /* I/O Space Marker */ + +#define PCI_BA_MEM_CODEMASK 0xf /* bottom 4 bits encode MEM BAR type */ #define PCI_BA_MEM_LOCATION 0x6 /* 2 bits for location avail */ #define PCI_BA_MEM_32BIT 0x0 /* Anywhere in 32bit space */ #define PCI_BA_MEM_1MEG 0x2 /* Locate below 1 Meg */ #define PCI_BA_MEM_64BIT 0x4 /* Anywhere in 64bit space */ #define PCI_BA_PREFETCH 0x8 /* Prefetchable, no side effect */ +#define PCI_BA_ROM_CODEMASK 0x1 /* bottom bit control expansion ROM enable */ +#define PCI_BA_ROM_ENABLE 0x1 /* enable expansion ROM */ + +/* Bridge Control Register 0x3e */ +#define PCI_BCTRL_DTO_SERR 0x0800 /* Discard Timer timeout generates SERR on primary bus */ +#define PCI_BCTRL_DTO 0x0400 /* Discard Timer timeout status */ +#define PCI_BCTRL_DTO_SEC 0x0200 /* Secondary Discard Timer: 0 => 2^15 PCI clock cycles, 1 => 2^10 */ +#define PCI_BCTRL_DTO_PRI 0x0100 /* Primary Discard Timer: 0 => 2^15 PCI clock cycles, 1 => 2^10 */ +#define PCI_BCTRL_F_BK_BK_ENABLE 0x0080 /* Enable Fast Back-to-Back on secondary bus */ +#define PCI_BCTRL_RESET_SEC 0x0040 /* Reset Secondary bus */ +#define PCI_BCTRL_MSTR_ABT_MODE 0x0020 /* Master Abort Mode: 0 => do not report Master-Aborts */ +#define PCI_BCTRL_VGA_AF_ENABLE 0x0008 /* Enable VGA Address Forwarding */ +#define PCI_BCTRL_ISA_AF_ENABLE 0x0004 /* Enable ISA Address Forwarding */ +#define PCI_BCTRL_SERR_ENABLE 0x0002 /* Enable forwarding of SERR from secondary bus to primary bus */ +#define PCI_BCTRL_PAR_ERR_RESP 0x0001 /* Enable Parity Error Response reporting on secondary interface */ + +/* + * PCI 2.2 introduces the concept of ``capability lists.'' Capability lists + * provide a flexible mechanism for a device or bridge to advertise one or + * more standardized capabilities such as the presense of a power management + * interface, etc. The presense of a capability list is indicated by + * PCI_STAT_CAP_LIST being non-zero in the PCI_CFG_STATUS register. If + * PCI_STAT_CAP_LIST is set, then PCI_CFG_CAP_PTR is a ``pointer'' into the + * device-specific portion of the configuration header where the first + * capability block is stored. This ``pointer'' is a single byte which + * contains an offset from the beginning of the configuration header. The + * bottom two bits of the pointer are reserved and should be masked off to + * determine the offset. Each capability block contains a capability ID, a + * ``pointer'' to the next capability (another offset where a zero terminates + * the list) and capability-specific data. Each capability block starts with + * the capability ID and the ``next capability pointer.'' All data following + * this are capability-dependent. + */ +#define PCI_CAP_ID 0x00 /* Capability ID (1B) */ +#define PCI_CAP_PTR 0x01 /* Capability ``pointer'' (1B) */ + +/* PCI Capability IDs */ +#define PCI_CAP_PM 0x01 /* PCI Power Management */ +#define PCI_CAP_AGP 0x02 /* Accelerated Graphics Port */ +#define PCI_CAP_VPD 0x03 /* Vital Product Data (VPD) */ +#define PCI_CAP_SID 0x04 /* Slot Identification */ +#define PCI_CAP_MSI 0x05 /* Message Signaled Intr */ +#define PCI_CAP_HS 0x06 /* CompactPCI Hot Swap */ +#define PCI_CAP_PCIX 0x07 /* PCI-X */ +#define PCI_CAP_ID_HT 0x08 /* HyperTransport */ + + /* PIO interface macros */ #ifndef IOC3_EMULATION @@ -210,10 +262,6 @@ #endif /* !IOC3_EMULATION */ /* effects on reads, merges */ -#ifdef CONFIG_SGI_IP22 -#define BYTECOUNT_W_GIO 0xbf400000 -#endif - /* * Definition of address layouts for PCI Config mechanism #1 * XXX- These largely duplicate PCI_TYPE1 constants at the top @@ -240,4 +288,139 @@ #define PCI_IO_MAP_INCR 0x1000 #endif /* CONFIG_SGI_IP32 */ +/* + * Class codes + */ +#define PCI_CFG_CLASS_PRE20 0x00 +#define PCI_CFG_CLASS_STORAGE 0x01 +#define PCI_CFG_CLASS_NETWORK 0x02 +#define PCI_CFG_CLASS_DISPLAY 0x03 +#define PCI_CFG_CLASS_MMEDIA 0x04 +#define PCI_CFG_CLASS_MEMORY 0x05 +#define PCI_CFG_CLASS_BRIDGE 0x06 +#define PCI_CFG_CLASS_COMM 0x07 +#define PCI_CFG_CLASS_BASE 0x08 +#define PCI_CFG_CLASS_INPUT 0x09 +#define PCI_CFG_CLASS_DOCK 0x0A +#define PCI_CFG_CLASS_PROC 0x0B +#define PCI_CFG_CLASS_SERIALBUS 0x0C +#define PCI_CFG_CLASS_OTHER 0xFF + +/* + * Important Subclasses + */ +#define PCI_CFG_SUBCLASS_BRIDGE_HOST 0x00 +#define PCI_CFG_SUBCLASS_BRIDGE_ISA 0x01 +#define PCI_CFG_SUBCLASS_BRIDGE_EISA 0x02 +#define PCI_CFG_SUBCLASS_BRIDGE_MC 0x03 +#define PCI_CFG_SUBCLASS_BRIDGE_PCI 0x04 +#define PCI_CFG_SUBCLASS_BRIDGE_PCMCIA 0x05 +#define PCI_CFG_SUBCLASS_BRIDGE_NUBUS 0x06 +#define PCI_CFG_SUBCLASS_BRIDGE_CARDBUS 0x07 +#define PCI_CFG_SUBCLASS_BRIDGE_OTHER 0x80 + +#ifndef __ASSEMBLY__ + +/* + * PCI config space definition + */ +typedef volatile struct pci_cfg_s { + uint16_t dev_id; + uint16_t vendor_id; + uint16_t status; + uint16_t cmd; + uchar_t class; + uchar_t sub_class; + uchar_t prog_if; + uchar_t rev; + uchar_t bist; + uchar_t hdr_type; + uchar_t lt; + uchar_t line_size; + uint32_t bar[6]; + uint32_t cardbus; + uint16_t subsys_dev_id; + uint16_t subsys_vendor_id; + uint32_t exp_rom; + uint32_t res[2]; + uchar_t max_lat; + uchar_t min_gnt; + uchar_t int_pin; + uchar_t int_line; +} pci_cfg_t; + +/* + * PCI Type 1 config space definition for PCI to PCI Bridges (PPBs) + */ +typedef volatile struct pci_cfg1_s { + uint16_t dev_id; + uint16_t vendor_id; + uint16_t status; + uint16_t cmd; + uchar_t class; + uchar_t sub_class; + uchar_t prog_if; + uchar_t rev; + uchar_t bist; + uchar_t hdr_type; + uchar_t lt; + uchar_t line_size; + uint32_t bar[2]; + uchar_t slt; + uchar_t sub_bus_num; + uchar_t snd_bus_num; + uchar_t pri_bus_num; + uint16_t snd_status; + uchar_t io_limit; + uchar_t io_base; + uint16_t mem_limit; + uint16_t mem_base; + uint16_t pmem_limit; + uint16_t pmem_base; + uint32_t pmem_limit_upper; + uint32_t pmem_base_upper; + uint16_t io_limit_upper; + uint16_t io_base_upper; + uint32_t res; + uint32_t exp_rom; + uint16_t ppb_control; + uchar_t int_pin; + uchar_t int_line; +} pci_cfg1_t; + +/* + * PCI-X Capability + */ +typedef volatile struct cap_pcix_cmd_reg_s { + uint16_t reserved1: 9, + max_split: 3, + max_mem_read_cnt: 2, + enable_relaxed_order: 1, + data_parity_enable: 1; +} cap_pcix_cmd_reg_t; + +typedef volatile struct cap_pcix_stat_reg_s { + uint32_t reserved1: 2, + split_complt_err: 1, + max_cum_read: 3, + max_out_split: 3, + max_mem_read_cnt: 2, + device_complex: 1, + unexpect_split_complt: 1, + split_complt_discard: 1, + mhz133_capable: 1, + bit64_device: 1, + bus_num: 8, + dev_num: 5, + func_num: 3; +} cap_pcix_stat_reg_t; + +typedef volatile struct cap_pcix_type0_s { + cap_pcix_cmd_reg_t pcix_type0_command; + uchar_t pcix_cap_nxt; + uchar_t pcix_cap_id; + cap_pcix_stat_reg_t pcix_type0_status; +} cap_pcix_type0_t; + +#endif /* __ASSEMBLY__ */ #endif /* _ASM_SN_PCI_PCI_DEFS_H */ diff -Nru a/include/asm-ia64/sn/pci/pciba.h b/include/asm-ia64/sn/pci/pciba.h --- a/include/asm-ia64/sn/pci/pciba.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/pci/pciba.h Wed Jan 15 16:57:28 2003 @@ -91,6 +91,13 @@ #define PCIIOCDMAALLOC _IOWR(0,1,uint64_t) #define PCIIOCDMAFREE _IOW(0,1,uint64_t) +/* pio cache-mode ioctl defines. current only uncached accelerated */ +#define PCIBA_CACHE_MODE_SET 1 +#define PCIBA_CACHE_MODE_CLEAR 2 +#ifdef PIOMAP_UNC_ACC +#define PCIBA_UNCACHED_ACCEL PIOMAP_UNC_ACC +#endif + /* The parameter for PCIIOCDMAALLOC needs to contain * both the size of the request and the flag values * to be used in setting up the DMA. diff -Nru a/include/asm-ia64/sn/pci/pcibr.h b/include/asm-ia64/sn/pci/pcibr.h --- a/include/asm-ia64/sn/pci/pcibr.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/pci/pcibr.h Wed Jan 15 16:57:29 2003 @@ -11,6 +11,7 @@ #if defined(__KERNEL__) +#include #include #include #include @@ -75,6 +76,7 @@ */ extern pciio_provider_t pcibr_provider; +extern pciio_provider_t pci_pic_provider; /* ===================================================================== * secondary entry points: pcibr PCI bus provider @@ -182,7 +184,11 @@ extern void pcibr_intr_free(pcibr_intr_t intr); +#ifdef CONFIG_IA64_SGI_SN1 extern int pcibr_intr_connect(pcibr_intr_t intr); +#else +extern int pcibr_intr_connect(pcibr_intr_t intr, intr_func_t, intr_arg_t); +#endif extern void pcibr_intr_disconnect(pcibr_intr_t intr); @@ -215,9 +221,11 @@ extern int pcibr_error_devenable(devfs_handle_t pconn_vhdl, int error_code); +#ifdef PIC_LATER extern pciio_slot_t pcibr_error_extract(devfs_handle_t pcibr_vhdl, pciio_space_t *spacep, iopaddr_t *addrp); +#endif extern int pcibr_wrb_flush(devfs_handle_t pconn_vhdl); extern int pcibr_rrb_check(devfs_handle_t pconn_vhdl, @@ -226,11 +234,13 @@ int *count_reserved, int *count_pool); +#ifndef CONFIG_IA64_SGI_SN1 extern int pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd, int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2, int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4); +#endif typedef void rrb_alloc_funct_f (devfs_handle_t xconn_vhdl, @@ -340,7 +350,11 @@ extern void pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, ulong); extern void pcibr_hints_handsoff(devfs_handle_t); +#ifdef CONFIG_IA64_SGI_SN1 typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t); +#else +typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t, int); +#endif extern void pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *); extern int pcibr_asic_rev(devfs_handle_t); @@ -414,13 +428,9 @@ char resp_l1_msg[L1_QSIZE + 1]; }; -struct pcibr_slot_info_req_s { - int req_slot; - pcibr_slot_info_resp_t req_respp; - int req_size; -}; - struct pcibr_slot_info_resp_s { + short resp_bs_bridge_type; + short resp_bs_bridge_mode; int resp_has_host; char resp_host_slot; devfs_handle_t resp_slot_conn; @@ -438,17 +448,22 @@ unsigned resp_bss_d64_flags; iopaddr_t resp_bss_d32_base; unsigned resp_bss_d32_flags; - int resp_bss_ext_ates_active; + atomic_t resp_bss_ext_ates_active; volatile unsigned *resp_bss_cmd_pointer; unsigned resp_bss_cmd_shadow; int resp_bs_rrb_valid; - int resp_bs_rrb_valid_v; + int resp_bs_rrb_valid_v1; + int resp_bs_rrb_valid_v2; + int resp_bs_rrb_valid_v3; int resp_bs_rrb_res; bridgereg_t resp_b_resp; bridgereg_t resp_b_int_device; bridgereg_t resp_b_int_enable; bridgereg_t resp_b_int_host; - +#ifndef CONFIG_IA64_SGI_SN1 + picreg_t resp_p_int_enable; + picreg_t resp_p_int_host; +#endif struct pcibr_slot_func_info_resp_s { int resp_f_status; char resp_f_slot_name[MAXDEVNAME]; @@ -507,6 +522,9 @@ #define PCI_SLOT_RRB_ALLOC_ERR 24 /* slot initial rrb alloc error */ #define PCI_SLOT_DRV_ATTACH_ERR 25 /* driver attach error */ #define PCI_SLOT_DRV_DETACH_ERR 26 /* driver detach error */ +/* EFBIG 27 */ +#define PCI_MULTI_FUNC_ERR 28 /* multi-function card error */ +#define PCI_SLOT_RBAR_ALLOC_ERR 29 /* slot PCI-X RBAR alloc error */ /* ERANGE 34 */ /* EUNATCH 42 */ diff -Nru a/include/asm-ia64/sn/pci/pcibr_private.h b/include/asm-ia64/sn/pci/pcibr_private.h --- a/include/asm-ia64/sn/pci/pcibr_private.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/pci/pcibr_private.h Wed Jan 15 16:57:28 2003 @@ -15,6 +15,7 @@ * should ever peek into this file. */ +#include #include #include #include @@ -34,6 +35,68 @@ typedef struct pcibr_intr_wrap_s *pcibr_intr_wrap_t; typedef struct pcibr_intr_cbuf_s *pcibr_intr_cbuf_t; +typedef volatile unsigned *cfg_p; +typedef volatile bridgereg_t *reg_p; + +/* + * extern functions + */ +cfg_p pcibr_slot_config_addr(bridge_t *, pciio_slot_t, int); +cfg_p pcibr_func_config_addr(bridge_t *, pciio_bus_t bus, pciio_slot_t, pciio_function_t, int); +unsigned pcibr_slot_config_get(bridge_t *, pciio_slot_t, int); +unsigned pcibr_func_config_get(bridge_t *, pciio_slot_t, pciio_function_t, int); +void pcibr_debug(uint32_t, devfs_handle_t, char *, ...); +void pcibr_slot_config_set(bridge_t *, pciio_slot_t, int, unsigned); +void pcibr_func_config_set(bridge_t *, pciio_slot_t, pciio_function_t, int, + unsigned); +/* + * PCIBR_DEBUG() macro and debug bitmask defines + */ +/* low freqency debug events (ie. initialization, resource allocation,...) */ +#define PCIBR_DEBUG_INIT 0x00000001 /* bridge init */ +#define PCIBR_DEBUG_HINTS 0x00000002 /* bridge hints */ +#define PCIBR_DEBUG_ATTACH 0x00000004 /* bridge attach */ +#define PCIBR_DEBUG_DETACH 0x00000008 /* bridge detach */ +#define PCIBR_DEBUG_ATE 0x00000010 /* bridge ATE allocation */ +#define PCIBR_DEBUG_RRB 0x00000020 /* bridge RRB allocation */ +#define PCIBR_DEBUG_RBAR 0x00000040 /* bridge RBAR allocation */ +#define PCIBR_DEBUG_PROBE 0x00000080 /* bridge device probing */ +#define PCIBR_DEBUG_INTR_ERROR 0x00000100 /* bridge error interrupt */ +#define PCIBR_DEBUG_ERROR_HDLR 0x00000200 /* bridge error handler */ +#define PCIBR_DEBUG_CONFIG 0x00000400 /* device's config space */ +#define PCIBR_DEBUG_BAR 0x00000800 /* device's BAR allocations */ +#define PCIBR_DEBUG_INTR_ALLOC 0x00001000 /* device's intr allocation */ +#define PCIBR_DEBUG_DEV_ATTACH 0x00002000 /* device's attach */ +#define PCIBR_DEBUG_DEV_DETACH 0x00004000 /* device's detach */ +#define PCIBR_DEBUG_HOTPLUG 0x00008000 + +/* high freqency debug events (ie. map allocation, direct translation,...) */ +#define PCIBR_DEBUG_DEVREG 0x04000000 /* bridges device reg sets */ +#define PCIBR_DEBUG_PIOMAP 0x08000000 /* pcibr_piomap */ +#define PCIBR_DEBUG_PIODIR 0x10000000 /* pcibr_piotrans */ +#define PCIBR_DEBUG_DMAMAP 0x20000000 /* pcibr_dmamap */ +#define PCIBR_DEBUG_DMADIR 0x40000000 /* pcibr_dmatrans */ +#define PCIBR_DEBUG_INTR 0x80000000 /* interrupts */ + +extern char *pcibr_debug_module; +extern int pcibr_debug_widget; +extern int pcibr_debug_slot; +extern uint32_t pcibr_debug_mask; + +/* For low frequency events (ie. initialization, resource allocation,...) */ +#define PCIBR_DEBUG_ALWAYS(args) pcibr_debug args ; + +/* XXX: habeck: maybe make PCIBR_DEBUG() always available? Even in non- + * debug kernels? If tracing isn't enabled (i.e pcibr_debug_mask isn't + * set, then the overhead for this macro is just an extra 'if' check. + */ +/* For high frequency events (ie. map allocation, direct translation,...) */ +#if 1 || DEBUG +#define PCIBR_DEBUG(args) PCIBR_DEBUG_ALWAYS(args) +#else /* DEBUG */ +#define PCIBR_DEBUG(args) +#endif /* DEBUG */ + /* * Bridge sets up PIO using this information. */ @@ -100,6 +163,8 @@ #define bi_flags bi_pi.pi_flags /* PCIBR_INTR flags */ #define bi_dev bi_pi.pi_dev /* associated pci card */ #define bi_lines bi_pi.pi_lines /* which PCI interrupt line(s) */ +#define bi_func bi_pi.pi_func /* handler function (when connected) */ +#define bi_arg bi_pi.pi_arg /* handler parameter (when connected) */ #define bi_mustruncpu bi_pi.pi_mustruncpu /* Where we must run. */ #define bi_irq bi_pi.pi_irq /* IRQ assigned. */ #define bi_cpu bi_pi.pi_cpu /* cpu assigned. */ @@ -108,9 +173,43 @@ struct pcibr_intr_cbuf_s bi_ibuf; /* circular buffer of wrap ptrs */ }; + +/* + * PCIBR_INFO_SLOT_GET_EXT returns the external slot number that the card + * resides in. (i.e the slot number silk screened on the back of the I/O + * brick). PCIBR_INFO_SLOT_GET_INT returns the internal slot (or device) + * number used by the pcibr code to represent that external slot (i.e to + * set bit patterns in BRIDGE/PIC registers to represent the device, or to + * offset into an array, or ...). + * + * In BRIDGE and XBRIDGE the external slot and internal device numbering + * are the same. (0->0, 1->1, 2->2,... 7->7) BUT in the PIC the external + * slot number is always 1 greater than the internal device number (1->0, + * 2->1, 3->2, 4->3). This is due to the fact that the PCI-X spec requires + * that the 'bridge' (i.e PIC) be designated as 'device 0', thus external + * slot numbering can't start at zero. + * + * PCIBR_DEVICE_TO_SLOT converts an internal device number to an external + * slot number. NOTE: PCIIO_SLOT_NONE stays as PCIIO_SLOT_NONE. + * + * PCIBR_SLOT_TO_DEVICE converts an external slot number to an internal + * device number. NOTE: PCIIO_SLOT_NONE stays as PCIIO_SLOT_NONE. + */ +#define PCIBR_INFO_SLOT_GET_EXT(info) (((pcibr_info_t)info)->f_slot) +#define PCIBR_INFO_SLOT_GET_INT(info) (((pcibr_info_t)info)->f_dev) + +#define PCIBR_DEVICE_TO_SLOT(pcibr_soft, dev_num) \ + (((dev_num) != PCIIO_SLOT_NONE) ? \ + (IS_PIC_SOFT((pcibr_soft)) ? ((dev_num) + 1) : (dev_num)) : \ + PCIIO_SLOT_NONE) + +#define PCIBR_SLOT_TO_DEVICE(pcibr_soft, slot) \ + (((slot) != PCIIO_SLOT_NONE) ? \ + (IS_PIC_SOFT((pcibr_soft)) ? ((slot) - 1) : (slot)) : \ + PCIIO_SLOT_NONE) + /* - * per-connect point pcibr data, including - * standard pciio data in-line: + * per-connect point pcibr data, including standard pciio data in-line: */ struct pcibr_info_s { struct pciio_info_s f_c; /* MUST BE FIRST. */ @@ -125,15 +224,18 @@ #define f_pops f_c.c_pops /* cached provider from c_master */ #define f_efunc f_c.c_efunc /* error handling function */ #define f_einfo f_c.c_einfo /* first parameter for efunc */ -#define f_window f_c.c_window /* state of BASE regs */ -#define f_rbase f_c.c_rbase /* expansion rom base */ -#define f_rsize f_c.c_rsize /* expansion rom size */ -#define f_piospace f_c.c_piospace /* additional I/O spaces allocated */ +#define f_window f_c.c_window /* state of BASE regs */ +#define f_rwindow f_c.c_rwindow /* expansion ROM BASE regs */ +#define f_rbase f_c.c_rbase /* expansion ROM base */ +#define f_rsize f_c.c_rsize /* expansion ROM size */ +#define f_piospace f_c.c_piospace /* additional I/O spaces allocated */ /* pcibr-specific connection state */ int f_ibit[4]; /* Bridge bit for each INTx */ pcibr_piomap_t f_piomap; int f_att_det_error; + pciio_slot_t f_dev; /* which device the card represents */ + cap_pcix_type0_t *f_pcix_cap; /* pointer to the pcix capability */ }; /* ===================================================================== @@ -152,15 +254,91 @@ struct pcibr_intr_wrap_s { pcibr_soft_t iw_soft; /* which bridge */ volatile bridgereg_t *iw_stat; /* ptr to b_int_status */ +#ifdef CONFIG_IA64_SGI_SN1 bridgereg_t iw_intr; /* bit in b_int_status */ +#else + bridgereg_t iw_ibit; /* bit in b_int_status */ +#endif pcibr_intr_list_t iw_list; /* ghostbusters! */ int iw_hdlrcnt; /* running handler count */ int iw_shared; /* if Bridge bit is shared */ int iw_connected; /* if already connected */ }; -#define PCIBR_ISR_ERR_START 8 -#define PCIBR_ISR_MAX_ERRS 32 +#define PCIBR_ISR_ERR_START 8 +#define PCIBR_ISR_MAX_ERRS_BRIDGE 32 +#define PCIBR_ISR_MAX_ERRS_PIC 45 +#define PCIBR_ISR_MAX_ERRS PCIBR_ISR_MAX_ERRS_PIC + +/* + * PCI Base Address Register window allocation constants. + * To reduce the size of the internal resource mapping structures, do + * not use the entire PCI bus I/O address space + */ +#define PCIBR_BUS_IO_BASE 0x100000 +#define PCIBR_BUS_IO_MAX 0x0FFFFFFF +#define PCIBR_BUS_IO_PAGE 0x100000 + +#define PCIBR_BUS_SWIN_BASE _PAGESZ +#define PCIBR_BUS_SWIN_MAX 0x000FFFFF +#define PCIBR_BUS_SWIN_PAGE _PAGESZ + +#define PCIBR_BUS_MEM_BASE 0x200000 +#define PCIBR_BUS_MEM_MAX 0x3FFFFFFF +#define PCIBR_BUS_MEM_PAGE 0x100000 + +/* defines for pcibr_soft_s->bs_bridge_type */ +#define PCIBR_BRIDGETYPE_BRIDGE 0 +#define PCIBR_BRIDGETYPE_XBRIDGE 1 +#define PCIBR_BRIDGETYPE_PIC 2 +#define IS_XBRIDGE_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_XBRIDGE) +#define IS_PIC_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_PIC) +#define IS_BRIDGE_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_BRIDGE) +#define IS_XBRIDGE_OR_PIC_SOFT(ps) (IS_XBRIDGE_SOFT(ps) || IS_PIC_SOFT(ps)) + +/* + * Runtime checks for workarounds. + */ +#define PCIBR_WAR_ENABLED(pv, pcibr_soft) \ + ((1 << XWIDGET_PART_REV_NUM_REV(pcibr_soft->bs_rev_num)) & pv) +/* + * Defines for individual WARs. Each is a bitmask of applicable + * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B, etc. + */ +#define PV854697 (~0) /* PIC: write 64bit regs as 64bits. permanent */ +#define PV854827 (~0) /* PIC: fake widget 0xf presence bit. permanent */ +#define PV855271 (~0) /* PIC: use virt chan iff 64-bit device. permanent */ +#define PV855272 (1 << 1) /* PIC: runaway interrupt WAR */ +#define PV856155 (1 << 1) /* PIC: arbitration WAR */ +#define PV856864 (1 << 1) /* PIC: lower timeout to free TNUMs quicker */ +#define PV856866 (1 << 1) /* PIC: avoid rrb's 0/1/8/9. */ +#define PV862253 (1 << 1) /* PIC: don't enable write req RAM parity checking */ +#define PV867308 (3 << 1) /* PIC: make LLP error interrupts FATAL for PIC */ + + +/* defines for pcibr_soft_s->bs_bridge_mode */ +#define PCIBR_BRIDGEMODE_PCI_33 0x0 +#define PCIBR_BRIDGEMODE_PCI_66 0x2 +#define PCIBR_BRIDGEMODE_PCIX_66 0x3 +#define PCIBR_BRIDGEMODE_PCIX_100 0x5 +#define PCIBR_BRIDGEMODE_PCIX_133 0x7 +#define BUSSPEED_MASK 0x6 +#define BUSTYPE_MASK 0x1 + +#define IS_PCI(ps) (!IS_PCIX(ps)) +#define IS_PCIX(ps) ((ps)->bs_bridge_mode & BUSTYPE_MASK) + +#define IS_33MHZ(ps) ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCI_33) +#define IS_66MHZ(ps) (((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCI_66) || \ + ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_66)) +#define IS_100MHZ(ps) ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_100) +#define IS_133MHZ(ps) ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_133) + + +/* Number of PCI slots. NOTE: this works as long as the first slot + * is zero. Otherwise use ((ps->bs_max_slot+1) - ps->bs_min_slot) + */ +#define PCIBR_NUM_SLOTS(ps) (ps->bs_max_slot+1) /* ===================================================================== * Bridge Device State structure @@ -172,7 +350,7 @@ struct pcibr_soft_s { devfs_handle_t bs_conn; /* xtalk connection point */ devfs_handle_t bs_vhdl; /* vertex owned by pcibr */ - int bs_int_enable; /* Mask of enabled intrs */ + uint64_t bs_int_enable; /* Mask of enabled intrs */ bridge_t *bs_base; /* PIO pointer to Bridge chip */ char *bs_name; /* hw graph name */ xwidgetnum_t bs_xid; /* Bridge's xtalk ID number */ @@ -180,7 +358,11 @@ xwidgetnum_t bs_mxid; /* master's xtalk ID number */ pciio_slot_t bs_first_slot; /* first existing slot */ pciio_slot_t bs_last_slot; /* last existing slot */ - + pciio_slot_t bs_last_reset; /* last slot to reset */ + pciio_slot_t bs_min_slot; /* lowest possible slot */ + pciio_slot_t bs_max_slot; /* highest possible slot */ + pcibr_soft_t bs_peers_soft; /* PICs other bus's soft */ + int bs_busnum; /* PIC has two pci busses */ iopaddr_t bs_dir_xbase; /* xtalk address for 32-bit PCI direct map */ xwidgetnum_t bs_dir_xport; /* xtalk port for 32-bit PCI direct map */ @@ -188,14 +370,23 @@ struct map *bs_int_ate_map; /* rmalloc map for internal ATEs */ struct map *bs_ext_ate_map; /* rmalloc map for external ATEs */ short bs_int_ate_size; /* number of internal ates */ - short bs_xbridge; /* if 1 then xbridge */ - + short bs_bridge_type; /* see defines above */ + short bs_bridge_mode; /* see defines above */ +#ifdef CONFIG_IA64_SGI_SN1 +#define bs_xbridge bs_bridge_type +#endif int bs_rev_num; /* revision number of Bridge */ - unsigned bs_dma_flags; /* revision-implied DMA flags */ + /* bs_dma_flags are the forced dma flags used on all DMAs. Used for + * working around ASIC rev issues and protocol specific requirements + */ + unsigned bs_dma_flags; /* forced DMA flags */ +#ifdef CONFIG_IA64_SGI_SN1 l1sc_t *bs_l1sc; /* io brick l1 system cntr */ +#endif moduleid_t bs_moduleid; /* io brick moduleid */ + short bs_bricktype; /* io brick type */ /* * Lock used primarily to get mutual exclusion while managing any @@ -222,7 +413,8 @@ pciio_slot_t host_slot; devfs_handle_t slot_conn; - int slot_status; + /* PCI Hot-Plug status word */ + int slot_status; /* Potentially several connection points * for this slot. bss_ninfo is how many, @@ -299,24 +491,53 @@ pcibr_intr_bits_f *bs_intr_bits; + /* PIC PCI-X Read Buffer Management : + * bs_pcix_num_funcs: the total number of PCI-X functions + * on the bus + * bs_pcix_split_tot: total number of outstanding split + * transactions requested by all functions on the bus + * bs_pcix_rbar_percent_allowed: the percentage of the + * total number of buffers a function requested that are + * available to it, not including the 1 RBAR guaranteed + * to it. + * bs_pcix_rbar_inuse: number of RBARs in use. + * bs_pcix_rbar_avail: number of RBARs available. NOTE: + * this value can go negative if we oversubscribe the + * RBARs. (i.e. We have 16 RBARs but 17 functions). + */ + int bs_pcix_num_funcs; + int bs_pcix_split_tot; + int bs_pcix_rbar_percent_allowed; + + int bs_pcix_rbar_inuse; + int bs_pcix_rbar_avail; + + /* RRB MANAGEMENT * bs_rrb_fixed: bitmap of slots whose RRB * allocations we should not "automatically" change * bs_rrb_avail: number of RRBs that have not * been allocated or reserved for {even,odd} slots - * bs_rrb_res: number of RRBs reserved for the + * bs_rrb_res: number of RRBs currently reserved for the * use of the index slot number - * bs_rrb_valid: number of RRBs marked valid - * for the indexed slot number; indexes 8-15 - * are for the virtual channels for slots 0-7. + * bs_rrb_res_dflt: number of RRBs reserved at boot + * time for the use of the index slot number + * bs_rrb_valid: number of RRBs currently marked valid + * for the indexed slot/vchan number; array[slot][vchan] + * bs_rrb_valid_dflt: number of RRBs marked valid at boot + * time for the indexed slot/vchan number; array[slot][vchan] */ int bs_rrb_fixed; - int bs_rrb_avail[2]; - int bs_rrb_res[8]; + int bs_rrb_avail[2]; + int bs_rrb_res[8]; int bs_rrb_res_dflt[8]; +#ifdef CONFIG_IA64_SGI_SN1 int bs_rrb_valid[16]; int bs_rrb_valid_dflt[16]; - +#else + int bs_rrb_valid[8][4]; + int bs_rrb_valid_dflt[8][4]; +#endif struct { /* Each Bridge interrupt bit has a single XIO * interrupt channel allocated. @@ -347,35 +568,55 @@ * Note that there is no locking while looking at this data structure. * There should not be any race between bus error code and * error interrupt code.. will look into this if needed. + * + * NOTE: The above discussion of error interrupt processing is + * no longer true. Whether it should again be true, is + * being looked into. */ struct br_errintr_info { int bserr_toutcnt; #ifdef LATER toid_t bserr_toutid; /* Timeout started by errintr */ -#endif - iopaddr_t bserr_addr; /* Address where error occurred */ - bridgereg_t bserr_intstat; /* interrupts active at error time */ +#endif /* LATER */ + iopaddr_t bserr_addr; /* Address where error occured */ + uint64_t bserr_intstat; /* interrupts active at error dump */ } bs_errinfo; /* * PCI Bus Space allocation data structure. - * This info is used to satisfy the callers of pcibr_piospace_alloc - * interface. Most of these users need "large" amounts of PIO - * space (typically in Megabytes), and they generally tend to - * take once and never release.. - * For Now use a simple algorithm to manage it. On allocation, - * Update the _base field to reflect next free address. * - * Freeing does nothing.. So, once allocated, it's gone for good. + * The resource mapping functions rmalloc() and rmfree() are used + * to manage the PCI bus I/O, small window, and memory address + * spaces. + * + * This info is used to assign PCI bus space addresses to cards + * via their BARs and to the callers of the pcibr_piospace_alloc() + * interface. + * + * Users of the pcibr_piospace_alloc() interface, such as the VME + * Universe chip, need PCI bus space that is not acquired by BARs. + * Most of these users need "large" amounts of PIO space (typically + * in Megabytes), and they generally tend to take once and never + * release. */ +#ifdef CONFIG_IA64_SGI_SN1 struct br_pcisp_info { - iopaddr_t pci_io_base; - iopaddr_t pci_io_last; - iopaddr_t pci_swin_base; - iopaddr_t pci_swin_last; - iopaddr_t pci_mem_base; - iopaddr_t pci_mem_last; + iopaddr_t pci_io_base; + iopaddr_t pci_io_last; + iopaddr_t pci_swin_base; + iopaddr_t pci_swin_last; + iopaddr_t pci_mem_base; + iopaddr_t pci_mem_last; } bs_spinfo; +#endif /* CONFIG_IA64_SGI_SN1 */ + struct pciio_win_map_s bs_io_win_map; /* I/O addr space */ + struct pciio_win_map_s bs_swin_map; /* Small window addr space */ + struct pciio_win_map_s bs_mem_win_map; /* Memory addr space */ + + int bs_bus_addr_status; /* Bus space status */ + +#define PCIBR_BUS_ADDR_MEM_FREED 1 /* Reserved PROM mem addr freed */ +#define PCIBR_BUS_ADDR_IO_FREED 2 /* Reserved PROM I/O addr freed */ struct bs_errintr_stat_s { uint32_t bs_errcount_total; @@ -437,13 +678,6 @@ #define pcibr_soft_get(v) ((pcibr_soft_t)hwgraph_fastinfo_get((v))) #define pcibr_soft_set(v,i) (hwgraph_fastinfo_set((v), (arbitrary_info_t)(i))) -/* Use io spin locks. This ensures that all the PIO writes from a particular - * CPU to a particular IO device are synched before the start of the next - * set of PIO operations to the same device. - */ -#define pcibr_lock(pcibr_soft) io_splock(&pcibr_soft->bs_lock) -#define pcibr_unlock(pcibr_soft,s) io_spunlock(&pcibr_soft->bs_lock,s) - /* * mem alloc/free macros */ @@ -455,13 +689,37 @@ #define NEW(ptr) NEWA(ptr,1) #define DEL(ptr) DELA(ptr,1) -typedef volatile unsigned *cfg_p; -typedef volatile bridgereg_t *reg_p; +#ifndef CONFIG_IA64_SGI_SN1 +/* + * Additional PIO spaces per slot are + * recorded in this structure. + */ +struct pciio_piospace_s { + pciio_piospace_t next; /* another space for this device */ + char free; /* 1 if free, 0 if in use */ + pciio_space_t space; /* Which space is in use */ + iopaddr_t start; /* Starting address of the PIO space */ + size_t count; /* size of PIO space */ +}; +#endif /* CONFIG_IA64_SGI_SN1 */ -#define PCIBR_RRB_SLOT_VIRTUAL 8 -#define PCIBR_VALID_SLOT(s) (s < 8) +/* Use io spin locks. This ensures that all the PIO writes from a particular + * CPU to a particular IO device are synched before the start of the next + * set of PIO operations to the same device. + */ +#ifdef PCI_LATER +#define pcibr_lock(pcibr_soft) io_splock(pcibr_soft->bs_lock) +#define pcibr_unlock(pcibr_soft, s) io_spunlock(pcibr_soft->bs_lock,s) +#else +#define pcibr_lock(pcibr_soft) 1 +#define pcibr_unlock(pcibr_soft, s) +#endif /* PCI_LATER */ + +#ifndef CONFIG_IA64_SGI_SN1 +#define PCIBR_VALID_SLOT(ps, s) (s < PCIBR_NUM_SLOTS(ps)) #define PCIBR_D64_BASE_UNSET (0xFFFFFFFFFFFFFFFF) #define PCIBR_D32_BASE_UNSET (0xFFFFFFFF) +#endif #define INFO_LBL_PCIBR_ASIC_REV "_pcibr_asic_rev" #define PCIBR_SOFT_LIST 1 diff -Nru a/include/asm-ia64/sn/pci/pciio.h b/include/asm-ia64/sn/pci/pciio.h --- a/include/asm-ia64/sn/pci/pciio.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/pci/pciio.h Wed Jan 15 16:57:28 2003 @@ -13,6 +13,7 @@ * pciio.h -- platform-independent PCI interface */ +#include #include #include #include @@ -207,6 +208,9 @@ typedef struct pciio_intr_s *pciio_intr_t; typedef struct pciio_info_s *pciio_info_t; typedef struct pciio_piospace_s *pciio_piospace_t; +typedef struct pciio_win_info_s *pciio_win_info_t; +typedef struct pciio_win_map_s *pciio_win_map_t; +typedef struct pciio_win_alloc_s *pciio_win_alloc_t; /* PIO MANAGEMENT */ @@ -382,8 +386,13 @@ typedef void pciio_intr_free_f (pciio_intr_t intr_hdl); +#ifdef CONFIG_IA64_SGI_SN1 typedef int pciio_intr_connect_f (pciio_intr_t intr_hdl); /* pciio intr resource handle */ +#else +typedef int +pciio_intr_connect_f (pciio_intr_t intr_hdl, intr_func_t intr_func, intr_arg_t intr_arg); /* pciio intr resource handle */ +#endif typedef void pciio_intr_disconnect_f (pciio_intr_t intr_hdl); @@ -627,6 +636,44 @@ devfs_handle_t pcicard, /* vertex created by pciio_device_register */ int drv_flags); + +/* create and initialize empty window mapping resource */ +extern pciio_win_map_t +pciio_device_win_map_new(pciio_win_map_t win_map, /* preallocated win map structure */ + size_t region_size, /* size of region to be tracked */ + size_t page_size); /* allocation page size */ + +/* destroy window mapping resource freeing up ancillary resources */ +extern void +pciio_device_win_map_free(pciio_win_map_t win_map); /* preallocated win map structure */ + +/* populate window mapping with free range of addresses */ +extern void +pciio_device_win_populate(pciio_win_map_t win_map, /* win map */ + iopaddr_t ioaddr, /* base address of free range */ + size_t size); /* size of free range */ + +/* allocate window from mapping resource */ +#ifdef CONFIG_IA64_SGI_SN1 +extern iopaddr_t +pciio_device_win_alloc(pciio_win_map_t win_map, /* win map */ + pciio_win_alloc_t win_alloc, /* opaque allocation cookie */ + size_t size, /* size of allocation */ + size_t align); /* alignment of allocation */ +#else +extern iopaddr_t +pciio_device_win_alloc(pciio_win_map_t win_map, /* win map */ + pciio_win_alloc_t win_alloc, /* opaque allocation cookie */ + size_t start, /* start unit, or 0 */ + size_t size, /* size of allocation */ + size_t align); /* alignment of allocation */ +#endif + +/* free previously allocated window */ +extern void +pciio_device_win_free(pciio_win_alloc_t win_alloc); /* opaque allocation cookie */ + + /* * Generic PCI interface, for use with all PCI providers * and all PCI devices. @@ -644,52 +691,6 @@ extern ulong pciio_pio_mapsz_get(pciio_piomap_t pciio_piomap); extern caddr_t pciio_pio_kvaddr_get(pciio_piomap_t pciio_piomap); -#ifdef LATER -#ifdef USE_PCI_PIO -extern uint8_t pciio_pio_read8(volatile uint8_t *addr); -extern uint16_t pciio_pio_read16(volatile uint16_t *addr); -extern uint32_t pciio_pio_read32(volatile uint32_t *addr); -extern uint64_t pciio_pio_read64(volatile uint64_t *addr); -extern void pciio_pio_write8(uint8_t val, volatile uint8_t *addr); -extern void pciio_pio_write16(uint16_t val, volatile uint16_t *addr); -extern void pciio_pio_write32(uint32_t val, volatile uint32_t *addr); -extern void pciio_pio_write64(uint64_t val, volatile uint64_t *addr); -#else /* !USE_PCI_PIO */ -__inline uint8_t pciio_pio_read8(volatile uint8_t *addr) -{ - return *addr; -} -__inline uint16_t pciio_pio_read16(volatile uint16_t *addr) -{ - return *addr; -} -__inline uint32_t pciio_pio_read32(volatile uint32_t *addr) -{ - return *addr; -} -__inline uint64_t pciio_pio_read64(volatile uint64_t *addr) -{ - return *addr; -} -__inline void pciio_pio_write8(uint8_t val, volatile uint8_t *addr) -{ - *addr = val; -} -__inline void pciio_pio_write16(uint16_t val, volatile uint16_t *addr) -{ - *addr = val; -} -__inline void pciio_pio_write32(uint32_t val, volatile uint32_t *addr) -{ - *addr = val; -} -__inline void pciio_pio_write64(uint64_t val, volatile uint64_t *addr) -{ - *addr = val; -} -#endif /* USE_PCI_PIO */ -#endif /* LATER */ - /* Generic PCI dma interfaces */ extern devfs_handle_t pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap); @@ -701,8 +702,10 @@ /* Generic pci slot information access interface */ extern pciio_info_t pciio_info_chk(devfs_handle_t vhdl); extern pciio_info_t pciio_info_get(devfs_handle_t vhdl); +extern pciio_info_t pciio_hostinfo_get(devfs_handle_t vhdl); extern void pciio_info_set(devfs_handle_t vhdl, pciio_info_t widget_info); extern devfs_handle_t pciio_info_dev_get(pciio_info_t pciio_info); +extern devfs_handle_t pciio_info_hostdev_get(pciio_info_t pciio_info); extern pciio_bus_t pciio_info_bus_get(pciio_info_t pciio_info); extern pciio_slot_t pciio_info_slot_get(pciio_info_t pciio_info); extern pciio_function_t pciio_info_function_get(pciio_info_t pciio_info); @@ -718,7 +721,7 @@ extern size_t pciio_info_bar_size_get(pciio_info_t, int); extern iopaddr_t pciio_info_rom_base_get(pciio_info_t); extern size_t pciio_info_rom_size_get(pciio_info_t); - +extern int pciio_info_type1_get(pciio_info_t); extern int pciio_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *); extern int pciio_dma_enabled(devfs_handle_t); diff -Nru a/include/asm-ia64/sn/pci/pciio_private.h b/include/asm-ia64/sn/pci/pciio_private.h --- a/include/asm-ia64/sn/pci/pciio_private.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/pci/pciio_private.h Wed Jan 15 16:57:29 2003 @@ -10,6 +10,7 @@ #define _ASM_SN_PCI_PCIIO_PRIVATE_H #include +#include /* * pciio_private.h -- private definitions for pciio @@ -49,6 +50,8 @@ devfs_handle_t pi_dev; /* associated pci card */ device_desc_t pi_dev_desc; /* override device descriptor */ pciio_intr_line_t pi_lines; /* which interrupt line(s) */ + intr_func_t pi_func; /* handler function (when connected) */ + intr_arg_t pi_arg; /* handler parameter (when connected) */ cpuid_t pi_mustruncpu; /* Where we must run. */ int pi_irq; /* IRQ assigned */ int pi_cpu; /* cpu assigned */ @@ -59,6 +62,39 @@ #define PCIIO_INTR_NOTHREAD 2 /* interrupt handler wants to be called at interrupt level */ /* + * Some PCI provider implementations keep track of PCI window Base Address + * Register (BAR) address range assignment via the rmalloc()/rmfree() arena + * management routines. These implementations use the following data + * structure for each allocation address space (e.g. memory, I/O, small + * window, etc.). + * + * The ``page size'' encodes the minimum allocation unit and must be a power + * of 2. The main use of this allocation ``page size'' is to control the + * number of free address ranges that the mapping allocation software will + * need to track. Smaller values will allow more efficient use of the address + * ranges but will result in much larger allocation map structures ... For + * instance, if we want to manage allocations for a 256MB address range, + * choosing a 1MB allocation page size will result in up to 1MB being wasted + * for allocation requests smaller than 1MB. The worst case allocation + * pattern for the allocation software to track would be a pattern of 1MB + * allocated, 1MB free. This results in the need to track up to 128 free + * ranges. + */ +struct pciio_win_map_s { + struct map *wm_map; /* window address map */ + int wm_page_size; /* allocation ``page size'' */ +}; + +/* + * Opaque structure used to keep track of window allocation information. + */ +struct pciio_win_alloc_s { + pciio_win_map_t wa_map; /* window map allocation is from */ + unsigned long wa_base; /* allocation starting page number */ + size_t wa_pages; /* number of pages in allocation */ +}; + +/* * Each PCI Card has one of these. */ @@ -76,17 +112,17 @@ error_handler_f *c_efunc; /* error handling function */ error_handler_arg_t c_einfo; /* first parameter for efunc */ - struct { /* state of BASE regs */ - pciio_space_t w_space; - iopaddr_t w_base; - size_t w_size; - int w_devio_index; /* DevIO[] register used to - access this window */ - } c_window[6]; - - unsigned c_rbase; /* EXPANSION ROM base addr */ - unsigned c_rsize; /* EXPANSION ROM size (bytes) */ - + struct pciio_win_info_s { /* state of BASE regs */ + pciio_space_t w_space; + iopaddr_t w_base; + size_t w_size; + int w_devio_index; /* DevIO[] register used to + access this window */ + struct pciio_win_alloc_s w_win_alloc; /* window allocation cookie */ + } c_window[PCI_CFG_BASE_ADDRS + 1]; +#define c_rwindow c_window[PCI_CFG_BASE_ADDRS] /* EXPANSION ROM window */ +#define c_rbase c_rwindow.w_base /* EXPANSION ROM base addr */ +#define c_rsize c_rwindow.w_size /* EXPANSION ROM size (bytes) */ pciio_piospace_t c_piospace; /* additional I/O spaces allocated */ }; diff -Nru a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h --- a/include/asm-ia64/sn/pda.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/pda.h Wed Jan 15 16:57:29 2003 @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -25,7 +26,14 @@ * all SN per-cpu data structures. */ - +#ifdef BUS_INT_WAR +#define POLL_ENTRIES 50 +typedef struct { + int irq; + int interval; + short tick; +} sn_poll_entry_t; +#endif typedef struct pda_s { @@ -38,11 +46,15 @@ struct subnodepda_s *p_subnodepda; /* Pointer to CPU subnode PDA */ /* - * Support for blinking SN LEDs + * Support for SN LEDs */ - long *led_address; +#ifdef CONFIG_IA64_SGI_SN1 + volatile long *led_address; +#else + volatile short *led_address; +#endif u8 led_state; - char hb_state; /* supports blinking heartbeat leds */ + u8 hb_state; /* supports blinking heartbeat leds */ unsigned int hb_count; unsigned int idle_flag; @@ -52,8 +64,15 @@ #endif volatile unsigned long *bedrock_rev_id; volatile unsigned long *pio_write_status_addr; + volatile unsigned long *pio_shub_war_cam_addr; + volatile unsigned long *mem_write_status_addr; - bteinfo_t *cpubte[BTES_PER_NODE]; + bteinfo_t *cpu_bte_if[BTES_PER_NODE]; /* cpu interface order */ + +#ifdef BUS_INT_WAR + sn_poll_entry_t pda_poll_entries[POLL_ENTRIES]; + int pda_poll_entry_count; +#endif } pda_t; @@ -71,10 +90,11 @@ * size of the cpu_data area dont change cache layout. Should we align to 32, 64, 128 * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later. */ -#define CPU_DATA_END CACHE_ALIGN((long)&(((struct cpuinfo_ia64*)0)->platform_specific)) -#define PDAADDR (PERCPU_ADDR+CPU_DATA_END) +DECLARE_PER_CPU(struct pda_s, pda_percpu); + +#define pda (&__get_cpu_var(pda_percpu)) -#define pda (*((pda_t *) PDAADDR)) +#define pdacpu(cpu) (&per_cpu(pda_percpu, cpu)) #endif /* _ASM_IA64_SN_PDA_H */ diff -Nru a/include/asm-ia64/sn/sgi.h b/include/asm-ia64/sn/sgi.h --- a/include/asm-ia64/sn/sgi.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/sgi.h Wed Jan 15 16:57:28 2003 @@ -18,82 +18,6 @@ #include #include -// This devfs stuff needs a better home ..... - -struct directory_type -{ - struct devfs_entry *first; - struct devfs_entry *last; - unsigned int num_removable; -}; - -struct file_type -{ - unsigned long size; -}; - -struct device_type -{ - unsigned short major; - unsigned short minor; -}; - -struct fcb_type /* File, char, block type */ -{ - uid_t default_uid; - gid_t default_gid; - void *ops; - union - { - struct file_type file; - struct device_type device; - } - u; - unsigned char auto_owner:1; - unsigned char aopen_notify:1; - unsigned char removable:1; /* Belongs in device_type, but save space */ - unsigned char open:1; /* Not entirely correct */ -}; - -struct symlink_type -{ - unsigned int length; /* Not including the NULL-termimator */ - char *linkname; /* This is NULL-terminated */ -}; - -struct fifo_type -{ - uid_t uid; - gid_t gid; -}; - -struct devfs_entry -{ - void *info; - union - { - struct directory_type dir; - struct fcb_type fcb; - struct symlink_type symlink; - struct fifo_type fifo; - } - u; - struct devfs_entry *prev; /* Previous entry in the parent directory */ - struct devfs_entry *next; /* Next entry in the parent directory */ - struct devfs_entry *parent; /* The parent directory */ - struct devfs_entry *slave; /* Another entry to unregister */ - struct devfs_inode *first_inode; - struct devfs_inode *last_inode; - umode_t mode; - unsigned short namelen; /* I think 64k+ filenames are a way off... */ - unsigned char registered:1; - unsigned char show_unreg:1; - unsigned char hide:1; - unsigned char no_persistence /*:1*/; - char name[1]; /* This is just a dummy: the allocated array is - bigger. This is NULL-terminated */ -}; - typedef int64_t __psint_t; /* needed by klgraph.c */ typedef enum { B_FALSE, B_TRUE } boolean_t; @@ -222,6 +146,31 @@ #else #define cpu_enabled(cpu) (1) #endif + +/* print_register() defs */ + +/* + * register values + * map between numeric values and symbolic values + */ +struct reg_values { + unsigned long long rv_value; + char *rv_name; +}; + +/* + * register descriptors are used for formatted prints of register values + * rd_mask and rd_shift must be defined, other entries may be null + */ +struct reg_desc { + unsigned long long rd_mask; /* mask to extract field */ + int rd_shift; /* shift for extracted value, - >>, + << */ + char *rd_name; /* field name */ + char *rd_format; /* format to print field */ + struct reg_values *rd_values; /* symbolic names of values */ +}; + +extern void print_register(unsigned long long, struct reg_desc *); #include /* for now */ diff -Nru a/include/asm-ia64/sn/sn1/addrs.h b/include/asm-ia64/sn/sn1/addrs.h --- a/include/asm-ia64/sn/sn1/addrs.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/sn1/addrs.h Wed Jan 15 16:57:29 2003 @@ -41,7 +41,8 @@ * use some new ANSI preprocessor stuff to paste these on where needed. */ -#define CAC_BASE 0xe000000000000000 +#define CACHEABLE_MEM_SPACE 0xe000000000000000 +#define CAC_BASE CACHEABLE_MEM_SPACE #define HSPEC_BASE 0xc0000b0000000000 #define HSPEC_SWIZ_BASE 0xc000030000000000 #define IO_BASE 0xc0000a0000000000 diff -Nru a/include/asm-ia64/sn/sn1/intr.h b/include/asm-ia64/sn/sn1/intr.h --- a/include/asm-ia64/sn/sn1/intr.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/sn1/intr.h Wed Jan 15 16:57:28 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: intr.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff -Nru a/include/asm-ia64/sn/sn1/intr_public.h b/include/asm-ia64/sn/sn1/intr_public.h --- a/include/asm-ia64/sn/sn1/intr_public.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/sn1/intr_public.h Wed Jan 15 16:57:29 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: intr_public.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff -Nru a/include/asm-ia64/sn/sn1/mmzone_sn1.h b/include/asm-ia64/sn/sn1/mmzone_sn1.h --- a/include/asm-ia64/sn/sn1/mmzone_sn1.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/sn1/mmzone_sn1.h Wed Jan 15 16:57:29 2003 @@ -98,7 +98,7 @@ * absent. Each node consists of a number of possibly discontiguous chunks. */ #define SN1_CHUNKSHIFT 26 /* 64 MB */ -#define SN1_CHUNKSIZE (1UL << SN1_CHUNKSHIFT) +#define PLAT_CHUNKSIZE (1UL << SN1_CHUNKSHIFT) #define PLAT_CHUNKNUM(addr) (((addr) & (PLAT_MAX_PHYS_MEMORY-1)) >> SN1_CHUNKSHIFT) @@ -134,8 +134,8 @@ * This macro takes an address of the end of previous allocation, rounds it to a page boundary & * changes the node number. */ -#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr) SN1_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnodeid]), \ - (SN1_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT) +#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr) __pa(SN1_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnode]), \ + (SN1_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT)) diff -Nru a/include/asm-ia64/sn/sn1/sn_private.h b/include/asm-ia64/sn/sn1/sn_private.h --- a/include/asm-ia64/sn/sn1/sn_private.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/sn1/sn_private.h Wed Jan 15 16:57:28 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: sn_private.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff -Nru a/include/asm-ia64/sn/sn1/synergy.h b/include/asm-ia64/sn/sn1/synergy.h --- a/include/asm-ia64/sn/sn1/synergy.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/sn1/synergy.h Wed Jan 15 16:57:28 2003 @@ -54,9 +54,6 @@ #define WRITE_LOCAL_SYNERGY_REG(addr, value) __synergy_out(addr, value) -#define HUB_L(_a) *(_a) -#define HUB_S(_a, _d) *(_a) = (_d) - #define HSPEC_SYNERGY0_0 0x04000000 /* Synergy0 Registers */ #define HSPEC_SYNERGY1_0 0x05000000 /* Synergy1 Registers */ #define HS_SYNERGY_STRIDE (HSPEC_SYNERGY1_0 - HSPEC_SYNERGY0_0) diff -Nru a/include/asm-ia64/sn/sn2/addrs.h b/include/asm-ia64/sn/sn2/addrs.h --- a/include/asm-ia64/sn/sn2/addrs.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/sn2/addrs.h Wed Jan 15 16:57:28 2003 @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SN2_ADDRS_H @@ -53,19 +53,26 @@ /* Regions determined by AS */ #define LOCAL_MMR_SPACE 0xc000008000000000 /* Local MMR space */ +#define LOCAL_PHYS_MMR_SPACE 0x8000008000000000 /* Local PhysicalMMR space */ #define LOCAL_MEM_SPACE 0xc000010000000000 /* Local Memory space */ #define GLOBAL_MMR_SPACE 0xc000000800000000 /* Global MMR space */ +#define GLOBAL_PHYS_MMR_SPACE 0x0000000800000000 /* Global Physical MMR space */ #define GET_SPACE 0xc000001000000000 /* GET space */ #define AMO_SPACE 0xc000002000000000 /* AMO space */ #define CACHEABLE_MEM_SPACE 0xe000003000000000 /* Cacheable memory space */ #define UNCACHED 0xc000000000000000 /* UnCacheable memory space */ +#define UNCACHED_PHYS 0x8000000000000000 /* UnCacheable physical memory space */ + +#define PHYS_MEM_SPACE 0x0000003000000000 /* physical memory space */ /* SN2 address macros */ #define NID_SHFT 38 #define LOCAL_MMR_ADDR(a) (UNCACHED | LOCAL_MMR_SPACE | (a)) +#define LOCAL_MMR_PHYS_ADDR(a) (UNCACHED_PHYS | LOCAL_PHYS_MMR_SPACE | (a)) #define LOCAL_MEM_ADDR(a) (LOCAL_MEM_SPACE | (a)) #define REMOTE_ADDR(n,a) ((((unsigned long)(n))<> \ NASID_SHFT) & NASID_BITMASK) +#define PHYS_TO_DMA(x) ( ((x & NASID_MASK) >> 2) | \ + (x & (NODE_ADDRSPACE_SIZE - 1)) ) #define CHANGE_NASID(n,x) ({ia64_sn2_pa_t _v; _v.l = (long) (x); _v.f.nasid = n; _v.p;}) + +/* + * Determine if a physical address should be referenced as cached or uncached. + * For now, assume all memory is cached and everything else is noncached. + * (Later, we may need to special case areas of memory to be reference uncached). + */ +#define IS_CACHED_ADDRESS(x) (((x) & PHYS_MEM_SPACE) == PHYS_MEM_SPACE) + #ifndef __ASSEMBLY__ #define NODE_SWIN_BASE(nasid, widget) \ diff -Nru a/include/asm-ia64/sn/sn2/arch.h b/include/asm-ia64/sn/sn2/arch.h --- a/include/asm-ia64/sn/sn2/arch.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/sn2/arch.h Wed Jan 15 16:57:28 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: arch.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -60,7 +60,5 @@ #define LOCALCPU(slice) (((slice) & LOCALCPU_MASK) >> LOCALCPU_SHFT) #define TO_SLICE(subn, local) (((subn) << SUBNODE_SHFT) | \ ((local) << LOCALCPU_SHFT)) - -typedef u64 mmr_t; #endif /* _ASM_IA64_SN_SN2_ARCH_H */ diff -Nru a/include/asm-ia64/sn/sn2/intr.h b/include/asm-ia64/sn/sn2/intr.h --- a/include/asm-ia64/sn/sn2/intr.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/sn2/intr.h Wed Jan 15 16:57:29 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: intr.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -13,13 +13,15 @@ #define SGI_SHUB_ERROR_VECTOR (0xea) // These two IRQ's are used by partitioning. +#define SGI_XPC_ACTIVATE (0x30) #define SGI_XPC_NOTIFY (0xe7) -#define SGI_XPART_ACTIVATE (0x30) #define IA64_SN2_FIRST_DEVICE_VECTOR (0x31) #define IA64_SN2_LAST_DEVICE_VECTOR (0xe6) #define SN2_IRQ_RESERVED (0x1) #define SN2_IRQ_CONNECTED (0x2) + +#define SN2_IRQ_PER_HUB (2048) #endif /* _ASM_IA64_SN_SN2_INTR_H */ diff -Nru a/include/asm-ia64/sn/sn2/mmzone_sn2.h b/include/asm-ia64/sn/sn2/mmzone_sn2.h --- a/include/asm-ia64/sn/sn2/mmzone_sn2.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/sn2/mmzone_sn2.h Wed Jan 15 16:57:29 2003 @@ -103,7 +103,7 @@ * absent. Each node consists of a number of possibly contiguous chunks. */ #define SN2_CHUNKSHIFT 25 /* 32 MB */ -#define SN2_CHUNKSIZE (1UL << SN2_CHUNKSHIFT) +#define PLAT_CHUNKSIZE (1UL << SN2_CHUNKSHIFT) #define PLAT_CHUNKNUM(addr) ({unsigned long _p=(unsigned long)(addr); \ (((_p&SN2_NODE_MASK)>>2) | \ (_p&SN2_NODE_OFFSET_MASK)) >>SN2_CHUNKSHIFT;}) @@ -141,8 +141,8 @@ * This macro takes an address of the end of previous allocation, rounds it to a page boundary & * changes the node number. */ -#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr) SN2_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnodeid]), \ - (SN2_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT) +#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr) __pa(SN2_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnode]), \ + (SN2_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT)) diff -Nru a/include/asm-ia64/sn/sn2/shubio.h b/include/asm-ia64/sn/sn2/shubio.h --- a/include/asm-ia64/sn/sn2/shubio.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/sn2/shubio.h Wed Jan 15 16:57:29 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: shubio.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -493,8 +493,8 @@ shubreg_t i_rsvd_3 : 4; shubreg_t i_enable : 1; shubreg_t i_rsvd_2 : 3; - shubreg_t i_int_sent : 1; - shubreg_t i_rsvd_1 : 3; + shubreg_t i_int_sent : 2; + shubreg_t i_rsvd_1 : 2; shubreg_t i_pi0_forward_int : 1; shubreg_t i_pi1_forward_int : 1; shubreg_t i_rsvd : 30; @@ -3089,11 +3089,11 @@ #define IIO_FIRST_PC_ENTRY 12 */ -#define IIO_ICRB_A(_x) (IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))) -#define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET) -#define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET) -#define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET) -#define IIO_ICRB_E(_x) (IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET) +#define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x)))) +#define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)) +#define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)) +#define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)) +#define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET)) #define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7) @@ -3288,12 +3288,9 @@ #ifndef __ASSEMBLY__ /* - * Easy access macros for CRBs, all 4 registers (A-D) + * Easy access macros for CRBs, all 5 registers (A-E) */ typedef ii_icrb0_a_u_t icrba_t; -#define a_lnetuce ii_icrb0_a_fld_s.ia_ln_uce -#define a_mark ii_icrb0_a_fld_s.ia_mark -#define a_xerr ii_icrb0_a_fld_s.ia_xt_err #define a_sidn ii_icrb0_a_fld_s.ia_sidn #define a_tnum ii_icrb0_a_fld_s.ia_tnum #define a_addr ii_icrb0_a_fld_s.ia_addr @@ -3302,35 +3299,56 @@ #define a_regvalue ii_icrb0_a_regval typedef ii_icrb0_b_u_t icrbb_t; -#define b_error ii_icrb0_b_fld_s.ib_error -#define b_ecode ii_icrb0_b_fld_s.ib_errcode -#define b_cohtrans ii_icrb0_b_fld_s.ib_ct -#define b_xtsize ii_icrb0_b_fld_s.ib_size -#define b_source ii_icrb0_b_fld_s.ib_source +#define b_use_old ii_icrb0_b_fld_s.ib_use_old #define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype #define b_imsg ii_icrb0_b_fld_s.ib_imsg #define b_initiator ii_icrb0_b_fld_s.ib_init +#define b_exc ii_icrb0_b_fld_s.ib_exc +#define b_ackcnt ii_icrb0_b_fld_s.ib_ack_cnt +#define b_resp ii_icrb0_b_fld_s.ib_resp +#define b_ack ii_icrb0_b_fld_s.ib_ack +#define b_hold ii_icrb0_b_fld_s.ib_hold +#define b_wb ii_icrb0_b_fld_s.ib_wb +#define b_intvn ii_icrb0_b_fld_s.ib_intvn +#define b_stall_ib ii_icrb0_b_fld_s.ib_stall_ib +#define b_stall_int ii_icrb0_b_fld_s.ib_stall__intr +#define b_stall_bte_0 ii_icrb0_b_fld_s.ib_stall__bte_0 +#define b_stall_bte_1 ii_icrb0_b_fld_s.ib_stall__bte_1 +#define b_error ii_icrb0_b_fld_s.ib_error +#define b_ecode ii_icrb0_b_fld_s.ib_errcode +#define b_lnetuce ii_icrb0_b_fld_s.ib_ln_uce +#define b_mark ii_icrb0_b_fld_s.ib_mark +#define b_xerr ii_icrb0_b_fld_s.ib_xt_err #define b_regvalue ii_icrb0_b_regval typedef ii_icrb0_c_u_t icrbc_t; -#define c_btenum ii_icrb0_c_fld_s.ic_bte_num -#define c_pricnt ii_icrb0_c_fld_s.ic_pr_cnt -#define c_pripsc ii_icrb0_c_fld_s.ic_pr_psc -#define c_bteaddr ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/ -#define c_benable ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/ #define c_suppl ii_icrb0_c_fld_s.ic_suppl #define c_barrop ii_icrb0_c_fld_s.ic_bo #define c_doresp ii_icrb0_c_fld_s.ic_resprqd #define c_gbr ii_icrb0_c_fld_s.ic_gbr +#define c_btenum ii_icrb0_c_fld_s.ic_bte_num +#define c_cohtrans ii_icrb0_c_fld_s.ic_ct +#define c_xtsize ii_icrb0_c_fld_s.ic_size +#define c_source ii_icrb0_c_fld_s.ic_source #define c_regvalue ii_icrb0_c_regval + typedef ii_icrb0_d_u_t icrbd_t; +#define d_sleep ii_icrb0_d_fld_s.id_sleep +#define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt +#define d_pripsc ii_icrb0_d_fld_s.id_pr_psc #define d_bteop ii_icrb0_d_fld_s.id_bte_op -#define icrbd_ctxtvld ii_icrb0_d_fld_s.id_cvld -#define icrbd_toutvld ii_icrb0_d_fld_s.id_tvld -#define icrbd_context ii_icrb0_d_fld_s.id_context +#define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/ +#define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/ #define d_regvalue ii_icrb0_d_regval +typedef ii_icrb0_e_u_t icrbe_t; +#define icrbe_ctxtvld ii_icrb0_e_fld_s.ie_cvld +#define icrbe_toutvld ii_icrb0_e_fld_s.ie_tvld +#define icrbe_context ii_icrb0_e_fld_s.ie_context +#define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout +#define e_regvalue ii_icrb0_e_regval + #endif /* __ASSEMBLY__ */ /* Number of widgets supported by shub */ @@ -3391,15 +3409,15 @@ /* IO Interrupt Destination Register */ #define IIO_IIDSR_SENT_SHIFT 28 -#define IIO_IIDSR_SENT_MASK 0x10000000 +#define IIO_IIDSR_SENT_MASK 0x30000000 #define IIO_IIDSR_ENB_SHIFT 24 #define IIO_IIDSR_ENB_MASK 0x01000000 -#define IIO_IIDSR_NODE_SHIFT 8 -#define IIO_IIDSR_NODE_MASK 0x0000ff00 +#define IIO_IIDSR_NODE_SHIFT 9 +#define IIO_IIDSR_NODE_MASK 0x000ff700 #define IIO_IIDSR_PI_ID_SHIFT 8 -#define IIO_IIDSR_PI_ID_MASK 0x00000010 +#define IIO_IIDSR_PI_ID_MASK 0x00000100 #define IIO_IIDSR_LVL_SHIFT 0 -#define IIO_IIDSR_LVL_MASK 0x0000007f +#define IIO_IIDSR_LVL_MASK 0x000000ff /* Xtalk timeout threshhold register (IIO_IXTT) */ #define IXTT_RRSP_TO_SHFT 55 /* read response timeout */ @@ -3570,8 +3588,9 @@ extern int hub_intr_connect( hub_intr_t intr_hdl, /* xtalk intr resource hndl */ - xtalk_intr_setfunc_t setfunc, - /* func to set intr hw */ + intr_func_t intr_func, /* xtalk intr handler */ + void *intr_arg, /* arg to intr handler */ + xtalk_intr_setfunc_t setfunc, /* func to set intr hw */ void *setfunc_arg); /* arg to setfunc */ extern void diff -Nru a/include/asm-ia64/sn/sn2/sn_private.h b/include/asm-ia64/sn/sn2/sn_private.h --- a/include/asm-ia64/sn/sn2/sn_private.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/sn2/sn_private.h Wed Jan 15 16:57:28 2003 @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: sn_private.h,v 1.1 2002/02/28 17:31:26 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -27,7 +27,7 @@ extern nasid_t get_console_nasid(void); extern char get_console_pcislot(void); -extern int is_master_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid); +extern int is_master_baseio_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid); /* memsupport.c */ extern void poison_state_alter_range(__psunsigned_t start, int len, int poison); @@ -43,8 +43,10 @@ extern void set_dir_state_UNOWNED(paddr_t); extern int is_POISONED_dir_state(paddr_t); extern int is_UNOWNED_dir_state(paddr_t); +#ifdef LATER extern void get_dir_ent(paddr_t paddr, int *state, uint64_t *vec_ptr, hubreg_t *elo); +#endif /* intr.c */ extern int intr_reserve_level(cpuid_t cpu, int level, int err, devfs_handle_t owner_dev, char *name); diff -Nru a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h --- a/include/asm-ia64/sn/sn_cpuid.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/sn_cpuid.h Wed Jan 15 16:57:28 2003 @@ -121,13 +121,19 @@ #endif /* - * NOTE: id & eid refer to Intels definitions of the LID register - * (id = NASID, eid = slice) + * NOTE: id & eid refer to Intel's definitions of the LID register + * * NOTE: on non-MP systems, only cpuid 0 exists */ -#define id_eid_to_cpu_physical_id(id,eid) (((id)<<8) | (eid)) -#define id_eid_to_cpuid(id,eid) (cpu_logical_id(id_eid_to_cpu_physical_id((id),(eid)))) +#define id_eid_to_cpu_physical_id(id,eid) (((id)<<8) | (eid)) +#define nasid_slice_to_cpuid(nasid,slice) (cpu_logical_id(nasid_slice_to_cpu_physical_id((nasid),(slice)))) + +#ifdef CONFIG_IA64_SGI_SN1 +#define nasid_slice_to_cpu_physical_id(nasid, slice) (((nasid)<<8) | (slice)) +#else +#define nasid_slice_to_cpu_physical_id(nasid, slice) (((slice)<<12) | (nasid)) +#endif /* * The following table/struct is used for managing PTC coherency domains. @@ -190,13 +196,14 @@ /* * nasid_to_cnodeid - convert a NASID to a cnodeid */ -#define nasid_to_cnodeid(nasid) (local_node_data->physical_node_map[nasid]) +#define nasid_to_cnodeid(nasid) (nasid) /* (local_node_data->physical_node_map[nasid]) */ /* * cnode_slice_to_cpuid - convert a codeid & slice to a cpuid */ -#define cnode_slice_to_cpuid(cnodeid,slice) (id_eid_to_cpuid(cnodeid_to_nasid(cnodeid),(slice))) + +#define cnode_slice_to_cpuid(cnodeid,slice) (nasid_slice_to_cpuid(cnodeid_to_nasid(cnodeid),(slice))) /* diff -Nru a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h --- a/include/asm-ia64/sn/sn_sal.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/sn_sal.h Wed Jan 15 16:57:29 2003 @@ -12,20 +12,107 @@ */ +#include #include #include +#include // SGI Specific Calls #define SN_SAL_POD_MODE 0x02000001 #define SN_SAL_SYSTEM_RESET 0x02000002 #define SN_SAL_PROBE 0x02000003 -#define SN_SAL_GET_CONSOLE_NASID 0x02000004 +#define SN_SAL_GET_MASTER_NASID 0x02000004 #define SN_SAL_GET_KLCONFIG_ADDR 0x02000005 #define SN_SAL_LOG_CE 0x02000006 #define SN_SAL_REGISTER_CE 0x02000007 +#define SN_SAL_GET_PARTITION_ADDR 0x02000009 +#define SN_SAL_PRINT_ERROR 0x02000012 +#define SN_SAL_CONSOLE_PUTC 0x02000021 +#define SN_SAL_CONSOLE_GETC 0x02000022 +#define SN_SAL_CONSOLE_PUTS 0x02000023 +#define SN_SAL_CONSOLE_GETS 0x02000024 +#define SN_SAL_CONSOLE_GETS_TIMEOUT 0x02000025 +#define SN_SAL_CONSOLE_POLL 0x02000026 +#define SN_SAL_CONSOLE_INTR 0x02000027 +#define SN_SAL_CONSOLE_PUTB 0x02000028 +#define SN_SAL_SYSCTL_MODID_GET 0x02000031 +#define SN_SAL_SYSCTL_GET 0x02000032 +#define SN_SAL_SYSCTL_IOBRICK_MODULE_GET 0x02000033 +#define SN_SAL_SYSCTL_IO_PORTSPEED_GET 0x02000035 +#define SN_SAL_SYSCTL_SLAB_GET 0x02000036 +#define SN_SAL_BUS_CONFIG 0x02000037 +#define SN_SAL_SYS_SERIAL_GET 0x02000038 +#define SN_SAL_PARTITION_SERIAL_GET 0x02000039 +#define SN_SAL_SYSCTL_PARTITION_GET 0x0200003a +#define SN_SAL_SYSTEM_POWER_DOWN 0x0200003b +#define SN_SAL_GET_MASTER_BASEIO_NASID 0x0200003c +/* + * Service-specific constants + */ +#define SAL_CONSOLE_INTR_IN 0 /* manipulate input interrupts */ +#define SAL_CONSOLE_INTR_OUT 1 /* manipulate output low-water + * interrupts + */ +#define SAL_CONSOLE_INTR_OFF 0 /* turn the interrupt off */ +#define SAL_CONSOLE_INTR_ON 1 /* turn the interrupt on */ + + +/* + * SN_SAL_GET_PARTITION_ADDR return constants + */ +#define SALRET_MORE_PASSES 1 +#define SALRET_OK 0 +#define SALRET_INVALID_ARG -2 +#define SALRET_ERROR -3 + + +/** + * sn_sal_rev_major - get the major SGI SAL revision number + * + * The SGI PROM stores its version in sal_[ab]_rev_(major|minor). + * This routine simply extracts the major value from the + * @ia64_sal_systab structure constructed by ia64_sal_init(). + */ +static inline int +sn_sal_rev_major(void) +{ + struct ia64_sal_systab *systab = efi.sal_systab; + + return (int)systab->sal_b_rev_major; +} + +/** + * sn_sal_rev_minor - get the minor SGI SAL revision number + * + * The SGI PROM stores its version in sal_[ab]_rev_(major|minor). + * This routine simply extracts the minor value from the + * @ia64_sal_systab structure constructed by ia64_sal_init(). + */ +static inline int +sn_sal_rev_minor(void) +{ + struct ia64_sal_systab *systab = efi.sal_systab; + + return (int)systab->sal_b_rev_minor; +} + +/* + * Specify the minimum PROM revsion required for this kernel. + * Note that they're stored in hex format... + */ +#ifdef CONFIG_IA64_SGI_SN1 +#define SN_SAL_MIN_MAJOR 0x0 +#define SN_SAL_MIN_MINOR 0x03 /* SN1 PROMs are stuck at rev 0.03 */ +#elif defined(CONFIG_IA64_SGI_SN2) +#define SN_SAL_MIN_MAJOR 0x0 +#define SN_SAL_MIN_MINOR 0x11 +#else +#error "must specify which PROM revisions this kernel needs" +#endif /* CONFIG_IA64_SGI_SN1 */ + u64 ia64_sn_probe_io_slot(long paddr, long size, void *data_ptr); /* @@ -41,7 +128,7 @@ ret_stuff.v0 = (uint64_t)0; ret_stuff.v1 = (uint64_t)0; ret_stuff.v2 = (uint64_t)0; - SAL_CALL(ret_stuff, SN_SAL_GET_CONSOLE_NASID, 0, 0, 0, 0, 0, 0, 0); + SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_NASID, 0, 0, 0, 0, 0, 0, 0); if (ret_stuff.status < 0) return ret_stuff.status; @@ -50,6 +137,28 @@ return ret_stuff.v0; } +/* + * Returns the master baseio nasid, if the call fails, return an illegal + * value. + */ +static inline u64 +ia64_sn_get_master_baseio_nasid(void) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_BASEIO_NASID, 0, 0, 0, 0, 0, 0, 0); + + if (ret_stuff.status < 0) + return ret_stuff.status; + + /* Master baseio nasid is in 'v0' */ + return ret_stuff.v0; +} + static inline u64 ia64_sn_get_klconfig_addr(nasid_t nasid) { @@ -57,7 +166,7 @@ extern u64 klgraph_addr[]; int cnodeid; - cnodeid = nasid_to_cnodeid(nasid); + cnodeid = 0 /* nasid_to_cnodeid(nasid) */; if (klgraph_addr[cnodeid] == 0) { ret_stuff.status = (uint64_t)0; ret_stuff.v0 = (uint64_t)0; @@ -76,6 +185,245 @@ klgraph_addr[cnodeid] = ret_stuff.v0; } return(klgraph_addr[cnodeid]); +} +/* + * Returns the next console character. + */ +static inline u64 +ia64_sn_console_getc(int *ch) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + __SAL_CALL(ret_stuff, SN_SAL_CONSOLE_GETC, 0, 0, 0, 0, 0, 0, 0); + + /* character is in 'v0' */ + *ch = (int)ret_stuff.v0; + + return ret_stuff.status; } + +/* + * Sends the given character to the console. + */ +static inline u64 +ia64_sn_console_putc(char ch) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + __SAL_CALL(ret_stuff, SN_SAL_CONSOLE_PUTC, (uint64_t)ch, 0, 0, 0, 0, 0, 0); + + return ret_stuff.status; +} + +/* + * Sends the given buffer to the console. + */ +static inline u64 +ia64_sn_console_putb(char *buf, int len) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + __SAL_CALL(ret_stuff, SN_SAL_CONSOLE_PUTB, (uint64_t)buf, (uint64_t)len, 0, 0, 0, 0, 0); + + return ret_stuff.status; +} + +/* + * Print a platform error record + */ +static inline u64 +ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + __SAL_CALL(ret_stuff, SN_SAL_PRINT_ERROR, (uint64_t)hook, (uint64_t)rec, 0, 0, 0, 0, 0); + + return ret_stuff.status; +} + +/* + * Check for Platform errors + */ +static inline u64 +ia64_sn_plat_cpei_handler(void) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + __SAL_CALL(ret_stuff, SN_SAL_LOG_CE, 0, 0, 0, 0, 0, 0, 0); + + return ret_stuff.status; +} + +/* + * Checks for console input. + */ +static inline u64 +ia64_sn_console_check(int *result) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + __SAL_CALL(ret_stuff, SN_SAL_CONSOLE_POLL, 0, 0, 0, 0, 0, 0, 0); + + /* result is in 'v0' */ + *result = (int)ret_stuff.v0; + + return ret_stuff.status; +} + +/* + * Returns the iobrick module Id + */ +static inline u64 +ia64_sn_sysctl_iobrick_module_get(nasid_t nasid, int *result) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + SAL_CALL(ret_stuff, SN_SAL_SYSCTL_IOBRICK_MODULE_GET, nasid, 0, 0, 0, 0, 0, 0); + + /* result is in 'v0' */ + *result = (int)ret_stuff.v0; + + return ret_stuff.status; +} + +/** + * ia64_sn_pod_mode - call the SN_SAL_POD_MODE function + * + * SN_SAL_POD_MODE actually takes an argument, but it's always + * 0 when we call it from the kernel, so we don't have to expose + * it to the caller. + */ +static inline u64 +ia64_sn_pod_mode(void) +{ + struct ia64_sal_retval isrv; + SAL_CALL(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0); + if (isrv.status) + return 0; + return isrv.v0; +} + +/* + * Retrieve the system serial number as an ASCII string. + */ +static inline u64 +ia64_sn_sys_serial_get(char *buf) +{ + struct ia64_sal_retval ret_stuff; + SAL_CALL(ret_stuff, SN_SAL_SYS_SERIAL_GET, buf, 0, 0, 0, 0, 0, 0); + return ret_stuff.status; +} + +extern char sn_system_serial_number_string[]; +extern u64 sn_partition_serial_number; + +static inline char * +sn_system_serial_number(void) { + if (sn_system_serial_number_string[0]) { + return(sn_system_serial_number_string); + } else { + ia64_sn_sys_serial_get(sn_system_serial_number_string); + return(sn_system_serial_number_string); + } +} + + +/* + * Returns a unique id number for this system and partition (suitable for + * use with license managers), based in part on the system serial number. + */ +static inline u64 +ia64_sn_partition_serial_get(void) +{ + struct ia64_sal_retval ret_stuff; + SAL_CALL(ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0, 0, 0, 0, 0, 0, 0); + if (ret_stuff.status != 0) + return 0; + return ret_stuff.v0; +} + +static inline u64 +sn_partition_serial_number_val(void) { + if (sn_partition_serial_number) { + return(sn_partition_serial_number); + } else { + return(sn_partition_serial_number = ia64_sn_partition_serial_get()); + } +} + +/* + * Returns the partition id of the nasid passed in as an argument, + * or INVALID_PARTID if the partition id cannot be retrieved. + */ +static inline partid_t +ia64_sn_sysctl_partition_get(nasid_t nasid) +{ + struct ia64_sal_retval ret_stuff; + SAL_CALL(ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid, + 0, 0, 0, 0, 0, 0); + if (ret_stuff.status != 0) + return INVALID_PARTID; + return ((partid_t)ret_stuff.v0); +} + +#ifdef CONFIG_IA64_SGI_SN2 +/* + * Returns the partition id of the current processor. + */ + +extern partid_t sn_partid; + +static inline partid_t +sn_local_partid(void) { + if (sn_partid < 0) { + return (sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id()))); + } else { + return sn_partid; + } +} + +#endif /* CONFIG_IA64_SGI_SN2 */ + +/* + * Turns off system power. + */ +static inline void +ia64_sn_power_down(void) +{ + struct ia64_sal_retval ret_stuff; + SAL_CALL(ret_stuff, SN_SAL_SYSTEM_POWER_DOWN, 0, 0, 0, 0, 0, 0, 0); + while(1); + /* never returns */ +} + + #endif /* _ASM_IA64_SN_SN_SAL_H */ diff -Nru a/include/asm-ia64/sn/sndrv.h b/include/asm-ia64/sn/sndrv.h --- a/include/asm-ia64/sn/sndrv.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/sndrv.h Wed Jan 15 16:57:29 2003 @@ -27,6 +27,13 @@ #define SNDRV_SYNERGY_ENABLE 34 #define SNDRV_SYNERGY_FREQ 35 +/* see shubstats_ioctl() */ +#define SNDRV_SHUB_INFOSIZE 40 +#define SNDRV_SHUB_CONFIGURE 41 +#define SNDRV_SHUB_RESETSTATS 42 +#define SNDRV_SHUB_GETSTATS 43 +#define SNDRV_SHUB_GETNASID 44 + /* Devices */ #define SNDRV_UKNOWN_DEVICE -1 #define SNDRV_ROUTER_DEVICE 1 diff -Nru a/include/asm-ia64/sn/types.h b/include/asm-ia64/sn/types.h --- a/include/asm-ia64/sn/types.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/types.h Wed Jan 15 16:57:29 2003 @@ -9,14 +9,21 @@ #ifndef _ASM_IA64_SN_TYPES_H #define _ASM_IA64_SN_TYPES_H +#include #include typedef unsigned long cpuid_t; typedef unsigned long cpumask_t; typedef signed short nasid_t; /* node id in numa-as-id space */ typedef signed char partid_t; /* partition ID type */ +#ifdef CONFIG_IA64_SGI_SN2 +typedef unsigned int moduleid_t; /* user-visible module number type */ +typedef unsigned int cmoduleid_t; /* kernel compact module id type */ +#else typedef signed short moduleid_t; /* user-visible module number type */ typedef signed short cmoduleid_t; /* kernel compact module id type */ +#endif +typedef signed char slabid_t; typedef unsigned char clusterid_t; /* Clusterid of the cell */ typedef uint64_t __psunsigned_t; diff -Nru a/include/asm-ia64/sn/vector.h b/include/asm-ia64/sn/vector.h --- a/include/asm-ia64/sn/vector.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/vector.h Wed Jan 15 16:57:28 2003 @@ -10,6 +10,7 @@ #define _ASM_IA64_SN_VECTOR_H #include +#include #define NET_VEC_NULL ((net_vec_t) 0) #define NET_VEC_BAD ((net_vec_t) -1) diff -Nru a/include/asm-ia64/sn/xtalk/xbow.h b/include/asm-ia64/sn/xtalk/xbow.h --- a/include/asm-ia64/sn/xtalk/xbow.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/xtalk/xbow.h Wed Jan 15 16:57:28 2003 @@ -14,6 +14,7 @@ * xbow.h - header file for crossbow chip and xbow section of xbridge */ +#include #include #include #include @@ -42,6 +43,13 @@ #define MAX_PORT_NUM 0x10 /* maximum port number + 1 */ #define XBOW_WIDGET_ID 0 /* xbow is itself widget 0 */ +#define XBOW_HUBLINK_LOW 0xa +#define XBOW_HUBLINK_HIGH 0xb + +#define XBOW_PEER_LINK(link) (link == XBOW_HUBLINK_LOW) ? \ + XBOW_HUBLINK_HIGH : XBOW_HUBLINK_LOW + + #define XBOW_CREDIT 4 #define MAX_XBOW_NAME 16 @@ -384,6 +392,7 @@ #define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */ #define XBOW_WIDGET_MFGR_NUM 0x0 #define XXBOW_WIDGET_MFGR_NUM 0x0 +#define PXBOW_WIDGET_PART_NUM 0xd100 /* PIC */ #define XBOW_REV_1_0 0x1 /* xbow rev 1.0 is "1" */ #define XBOW_REV_1_1 0x2 /* xbow rev 1.1 is "2" */ @@ -398,8 +407,22 @@ #define XBOW_WID_ARB_RELOAD_INT 0x3f /* GBR reload interval */ -#define nasid_has_xbridge(nasid) \ - (XWIDGET_PART_NUM(XWIDGET_ID_READ(nasid, 0)) == XXBOW_WIDGET_PART_NUM) +#ifdef CONFIG_IA64_SGI_SN1 +#define nasid_has_xbridge(nasid) \ + (XWIDGET_PART_NUM(XWIDGET_ID_READ(nasid, 0)) == XXBOW_WIDGET_PART_NUM) +#endif + +#define IS_XBRIDGE_XBOW(wid) \ + (XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \ + XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) + +#define IS_PIC_XBOW(wid) \ + (XWIDGET_PART_NUM(wid) == PXBOW_WIDGET_PART_NUM && \ + XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) + +#define XBOW_WAR_ENABLED(pv, widid) ((1 << XWIDGET_REV_NUM(widid)) & pv) +#define PV854827 (~0) /* PIC: fake widget 0xf presence bit. permanent */ +#define PV863579 (1 << 1) /* PIC: PIO to PIC register */ #ifndef __ASSEMBLY__ diff -Nru a/include/asm-ia64/sn/xtalk/xtalk.h b/include/asm-ia64/sn/xtalk/xtalk.h --- a/include/asm-ia64/sn/xtalk/xtalk.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/xtalk/xtalk.h Wed Jan 15 16:57:29 2003 @@ -8,6 +8,7 @@ */ #ifndef _ASM_SN_XTALK_XTALK_H #define _ASM_SN_XTALK_XTALK_H +#include /* * xtalk.h -- platform-independent crosstalk interface @@ -202,10 +203,19 @@ typedef void xtalk_intr_free_f (xtalk_intr_t intr_hdl); +#ifdef CONFIG_IA64_SGI_SN1 typedef int xtalk_intr_connect_f (xtalk_intr_t intr_hdl, /* xtalk intr resource handle */ xtalk_intr_setfunc_f *setfunc, /* func to set intr hw */ void *setfunc_arg); /* arg to setfunc */ +#else +typedef int +xtalk_intr_connect_f (xtalk_intr_t intr_hdl, /* xtalk intr resource handle */ + intr_func_t intr_func, /* xtalk intr handler */ + void *intr_arg, /* arg to intr handler */ + xtalk_intr_setfunc_f *setfunc, /* func to set intr hw */ + void *setfunc_arg); /* arg to setfunc */ +#endif typedef void xtalk_intr_disconnect_f (xtalk_intr_t intr_hdl); @@ -390,9 +400,6 @@ typedef void xtalk_iter_f(devfs_handle_t vhdl); extern void xtalk_iterate(char *prefix, xtalk_iter_f *func); - -extern int xtalk_device_powerup(devfs_handle_t, xwidgetnum_t); -extern int xtalk_device_shutdown(devfs_handle_t, xwidgetnum_t); #endif /* __KERNEL__ */ #endif /* _ASM_SN_XTALK_XTALK_H */ diff -Nru a/include/asm-ia64/sn/xtalk/xtalk_private.h b/include/asm-ia64/sn/xtalk/xtalk_private.h --- a/include/asm-ia64/sn/xtalk/xtalk_private.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/sn/xtalk/xtalk_private.h Wed Jan 15 16:57:29 2003 @@ -60,12 +60,12 @@ ((_hwid)->mfg_num == XBOW_WIDGET_MFGR_NUM )) #define xwidget_hwid_is_sn1_xswitch(_hwid) \ - (((_hwid)->part_num == XXBOW_WIDGET_PART_NUM ) && \ + (((_hwid)->part_num == XXBOW_WIDGET_PART_NUM || \ + (_hwid)->part_num == PXBOW_WIDGET_PART_NUM) && \ ((_hwid)->mfg_num == XXBOW_WIDGET_MFGR_NUM )) #define xwidget_hwid_is_xswitch(_hwid) \ - (xwidget_hwid_is_sn0_xswitch(_hwid) || \ - xwidget_hwid_is_sn1_xswitch(_hwid)) + xwidget_hwid_is_sn1_xswitch(_hwid) /* common iograph info for all widgets, * stashed in FASTINFO of widget connection points. diff -Nru a/include/asm-ia64/sn/xtalk/xwidget.h b/include/asm-ia64/sn/xtalk/xwidget.h --- a/include/asm-ia64/sn/xtalk/xwidget.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/sn/xtalk/xwidget.h Wed Jan 15 16:57:28 2003 @@ -58,6 +58,7 @@ #define XWIDGET_MFG_NUM(widgetid) (((widgetid) & WIDGET_MFG_NUM) >> WIDGET_MFG_NUM_SHFT) #define XWIDGET_PART_REV_NUM(widgetid) ((XWIDGET_PART_NUM(widgetid) << 4) | \ XWIDGET_REV_NUM(widgetid)) +#define XWIDGET_PART_REV_NUM_REV(partrev) (partrev & 0xf) /* WIDGET_STATUS */ #define WIDGET_LLP_REC_CNT 0xff000000 diff -Nru a/include/asm-ia64/spinlock.h b/include/asm-ia64/spinlock.h --- a/include/asm-ia64/spinlock.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/spinlock.h Wed Jan 15 16:57:28 2003 @@ -74,6 +74,27 @@ #define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } #define spin_lock_init(x) ((x)->lock = 0) +#define DEBUG_SPIN_LOCK 0 + +#if DEBUG_SPIN_LOCK + +#include + +#define _raw_spin_lock(x) \ +do { \ + unsigned long _timeout = 1000000000; \ + volatile unsigned int _old = 0, _new = 1, *_ptr = &((x)->lock); \ + do { \ + if (_timeout-- == 0) { \ + extern void dump_stack (void); \ + printk("kernel DEADLOCK at %s:%d?\n", __FILE__, __LINE__); \ + dump_stack(); \ + } \ + } while (__sync_val_compare_and_swap(_ptr, _old, _new) != _old); \ +} while (0) + +#else + /* * Streamlined test_and_set_bit(0, (x)). We use test-and-test-and-set * rather than a simple xchg to avoid writing the cache-line when @@ -94,6 +115,8 @@ "(p7) br.cond.spnt.few 1b\n" \ ";;\n" \ :: "r"(&(x)->lock) : "ar.ccv", "p7", "r2", "r29", "memory") + +#endif /* !DEBUG_SPIN_LOCK */ #define spin_is_locked(x) ((x)->lock != 0) #define _raw_spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0) diff -Nru a/include/asm-ia64/system.h b/include/asm-ia64/system.h --- a/include/asm-ia64/system.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/system.h Wed Jan 15 16:57:29 2003 @@ -185,169 +185,6 @@ (flags & IA64_PSR_I) == 0; \ }) -/* - * Force an unresolved reference if someone tries to use - * ia64_fetch_and_add() with a bad value. - */ -extern unsigned long __bad_size_for_ia64_fetch_and_add (void); -extern unsigned long __bad_increment_for_ia64_fetch_and_add (void); - -#define IA64_FETCHADD(tmp,v,n,sz) \ -({ \ - switch (sz) { \ - case 4: \ - __asm__ __volatile__ ("fetchadd4.rel %0=[%1],%2" \ - : "=r"(tmp) : "r"(v), "i"(n) : "memory"); \ - break; \ - \ - case 8: \ - __asm__ __volatile__ ("fetchadd8.rel %0=[%1],%2" \ - : "=r"(tmp) : "r"(v), "i"(n) : "memory"); \ - break; \ - \ - default: \ - __bad_size_for_ia64_fetch_and_add(); \ - } \ -}) - -#define ia64_fetch_and_add(i,v) \ -({ \ - __u64 _tmp; \ - volatile __typeof__(*(v)) *_v = (v); \ - switch (i) { \ - case -16: IA64_FETCHADD(_tmp, _v, -16, sizeof(*(v))); break; \ - case -8: IA64_FETCHADD(_tmp, _v, -8, sizeof(*(v))); break; \ - case -4: IA64_FETCHADD(_tmp, _v, -4, sizeof(*(v))); break; \ - case -1: IA64_FETCHADD(_tmp, _v, -1, sizeof(*(v))); break; \ - case 1: IA64_FETCHADD(_tmp, _v, 1, sizeof(*(v))); break; \ - case 4: IA64_FETCHADD(_tmp, _v, 4, sizeof(*(v))); break; \ - case 8: IA64_FETCHADD(_tmp, _v, 8, sizeof(*(v))); break; \ - case 16: IA64_FETCHADD(_tmp, _v, 16, sizeof(*(v))); break; \ - default: \ - _tmp = __bad_increment_for_ia64_fetch_and_add(); \ - break; \ - } \ - (__typeof__(*(v))) (_tmp + (i)); /* return new value */ \ -}) - -/* - * This function doesn't exist, so you'll get a linker error if - * something tries to do an invalid xchg(). - */ -extern void __xchg_called_with_bad_pointer (void); - -static __inline__ unsigned long -__xchg (unsigned long x, volatile void *ptr, int size) -{ - unsigned long result; - - switch (size) { - case 1: - __asm__ __volatile ("xchg1 %0=[%1],%2" : "=r" (result) - : "r" (ptr), "r" (x) : "memory"); - return result; - - case 2: - __asm__ __volatile ("xchg2 %0=[%1],%2" : "=r" (result) - : "r" (ptr), "r" (x) : "memory"); - return result; - - case 4: - __asm__ __volatile ("xchg4 %0=[%1],%2" : "=r" (result) - : "r" (ptr), "r" (x) : "memory"); - return result; - - case 8: - __asm__ __volatile ("xchg8 %0=[%1],%2" : "=r" (result) - : "r" (ptr), "r" (x) : "memory"); - return result; - } - __xchg_called_with_bad_pointer(); - return x; -} - -#define xchg(ptr,x) \ - ((__typeof__(*(ptr))) __xchg ((unsigned long) (x), (ptr), sizeof(*(ptr)))) - -/* - * Atomic compare and exchange. Compare OLD with MEM, if identical, - * store NEW in MEM. Return the initial value in MEM. Success is - * indicated by comparing RETURN with OLD. - */ - -#define __HAVE_ARCH_CMPXCHG 1 - -/* - * This function doesn't exist, so you'll get a linker error - * if something tries to do an invalid cmpxchg(). - */ -extern long __cmpxchg_called_with_bad_pointer(void); - -#define ia64_cmpxchg(sem,ptr,old,new,size) \ -({ \ - __typeof__(ptr) _p_ = (ptr); \ - __typeof__(new) _n_ = (new); \ - __u64 _o_, _r_; \ - \ - switch (size) { \ - case 1: _o_ = (__u8 ) (long) (old); break; \ - case 2: _o_ = (__u16) (long) (old); break; \ - case 4: _o_ = (__u32) (long) (old); break; \ - case 8: _o_ = (__u64) (long) (old); break; \ - default: break; \ - } \ - __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(_o_)); \ - switch (size) { \ - case 1: \ - __asm__ __volatile__ ("cmpxchg1."sem" %0=[%1],%2,ar.ccv" \ - : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ - break; \ - \ - case 2: \ - __asm__ __volatile__ ("cmpxchg2."sem" %0=[%1],%2,ar.ccv" \ - : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ - break; \ - \ - case 4: \ - __asm__ __volatile__ ("cmpxchg4."sem" %0=[%1],%2,ar.ccv" \ - : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ - break; \ - \ - case 8: \ - __asm__ __volatile__ ("cmpxchg8."sem" %0=[%1],%2,ar.ccv" \ - : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ - break; \ - \ - default: \ - _r_ = __cmpxchg_called_with_bad_pointer(); \ - break; \ - } \ - (__typeof__(old)) _r_; \ -}) - -#define cmpxchg_acq(ptr,o,n) ia64_cmpxchg("acq", (ptr), (o), (n), sizeof(*(ptr))) -#define cmpxchg_rel(ptr,o,n) ia64_cmpxchg("rel", (ptr), (o), (n), sizeof(*(ptr))) - -/* for compatibility with other platforms: */ -#define cmpxchg(ptr,o,n) cmpxchg_acq(ptr,o,n) - -#ifdef CONFIG_IA64_DEBUG_CMPXCHG -# define CMPXCHG_BUGCHECK_DECL int _cmpxchg_bugcheck_count = 128; -# define CMPXCHG_BUGCHECK(v) \ - do { \ - if (_cmpxchg_bugcheck_count-- <= 0) { \ - void *ip; \ - extern int printk(const char *fmt, ...); \ - asm ("mov %0=ip" : "=r"(ip)); \ - printk("CMPXCHG_BUGCHECK: stuck at %p on word %p\n", ip, (v)); \ - break; \ - } \ - } while (0) -#else /* !CONFIG_IA64_DEBUG_CMPXCHG */ -# define CMPXCHG_BUGCHECK_DECL -# define CMPXCHG_BUGCHECK(v) -#endif /* !CONFIG_IA64_DEBUG_CMPXCHG */ - #ifdef __KERNEL__ #define prepare_to_switch() do { } while(0) @@ -431,6 +268,38 @@ __switch_to(prev,next,last); \ } while (0) #endif + +/* + * On IA-64, we don't want to hold the runqueue's lock during the low-level context-switch, + * because that could cause a deadlock. Here is an example by Erich Focht: + * + * Example: + * CPU#0: + * schedule() + * -> spin_lock_irq(&rq->lock) + * -> context_switch() + * -> wrap_mmu_context() + * -> read_lock(&tasklist_lock) + * + * CPU#1: + * sys_wait4() or release_task() or forget_original_parent() + * -> write_lock(&tasklist_lock) + * -> do_notify_parent() + * -> wake_up_parent() + * -> try_to_wake_up() + * -> spin_lock_irq(&parent_rq->lock) + * + * If the parent's rq happens to be on CPU#0, we'll wait for the rq->lock + * of that CPU which will not be released, because there we wait for the + * tasklist_lock to become available. + */ +#define prepare_arch_switch(rq, next) \ +do { \ + spin_lock(&(next)->switch_lock); \ + spin_unlock(&(rq)->lock); \ +} while (0) +#define finish_arch_switch(rq, prev) spin_unlock_irq(&(prev)->switch_lock) +#define task_running(rq, p) ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock)) #endif /* __KERNEL__ */ diff -Nru a/include/asm-ia64/thread_info.h b/include/asm-ia64/thread_info.h --- a/include/asm-ia64/thread_info.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/thread_info.h Wed Jan 15 16:57:29 2003 @@ -30,6 +30,7 @@ __u32 cpu; /* current CPU */ mm_segment_t addr_limit; /* user-level address space limit */ __s32 preempt_count; /* 0=premptable, <0=BUG; will also serve as bh-counter */ + struct restart_block restart_block; }; #define INIT_THREAD_SIZE /* tell sched.h not to declare the thread_union */ @@ -42,6 +43,9 @@ .cpu = 0, \ .addr_limit = KERNEL_DS, \ .preempt_count = 0, \ + .restart_block = { \ + .fn = do_no_restart_syscall, \ + }, \ } /* how to get the thread information struct from C */ diff -Nru a/include/asm-ia64/tlbflush.h b/include/asm-ia64/tlbflush.h --- a/include/asm-ia64/tlbflush.h Wed Jan 15 16:57:29 2003 +++ b/include/asm-ia64/tlbflush.h Wed Jan 15 16:57:29 2003 @@ -22,29 +22,47 @@ * Flush everything (kernel mapping may also have changed due to * vmalloc/vfree). */ -extern void __flush_tlb_all (void); +extern void local_flush_tlb_all (void); #ifdef CONFIG_SMP extern void smp_flush_tlb_all (void); + extern void smp_flush_tlb_mm (struct mm_struct *mm); # define flush_tlb_all() smp_flush_tlb_all() #else -# define flush_tlb_all() __flush_tlb_all() +# define flush_tlb_all() local_flush_tlb_all() #endif +static inline void +local_finish_flush_tlb_mm (struct mm_struct *mm) +{ + if (mm == current->active_mm) + activate_context(mm); +} + /* - * Flush a specified user mapping + * Flush a specified user mapping. This is called, e.g., as a result of fork() and + * exit(). fork() ends up here because the copy-on-write mechanism needs to write-protect + * the PTEs of the parent task. */ static inline void flush_tlb_mm (struct mm_struct *mm) { - if (mm) { - mm->context = 0; - if (mm == current->active_mm) { - /* This is called, e.g., as a result of exec(). */ - get_new_mmu_context(mm); - reload_context(mm); - } - } + MMU_TRACE('F', smp_processor_id(), mm, mm->context); + if (!mm) + goto out; + + mm->context = 0; + + if (atomic_read(&mm->mm_users) == 0) + goto out; /* happens as a result of exit_mmap() */ + +#ifdef CONFIG_SMP + smp_flush_tlb_mm(mm); +#else + local_finish_flush_tlb_mm(mm); +#endif + out: + MMU_TRACE('f', smp_processor_id(), mm, mm->context); } extern void flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end); diff -Nru a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h --- a/include/asm-ia64/unistd.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-ia64/unistd.h Wed Jan 15 16:57:28 2003 @@ -114,18 +114,18 @@ /* 1122 was __NR_old_fstat */ #define __NR_vhangup 1123 #define __NR_lchown 1124 -#define __NR_vm86 1125 +#define __NR_remap_file_pages 1125 #define __NR_wait4 1126 #define __NR_sysinfo 1127 #define __NR_clone 1128 #define __NR_setdomainname 1129 #define __NR_uname 1130 #define __NR_adjtimex 1131 -#define __NR_create_module 1132 +/* 1132 was __NR_create_module */ #define __NR_init_module 1133 #define __NR_delete_module 1134 -#define __NR_get_kernel_syms 1135 -#define __NR_query_module 1136 +/* 1135 was __NR_get_kernel_syms */ +/* 1136 was __NR_query_module */ #define __NR_quotactl 1137 #define __NR_bdflush 1138 #define __NR_sysfs 1139 @@ -222,7 +222,7 @@ #define __NR_futex 1230 #define __NR_sched_setaffinity 1231 #define __NR_sched_getaffinity 1232 -/* 1233 currently unused */ +#define __NR_set_tid_address 1233 #define __NR_alloc_hugepages 1234 #define __NR_free_hugepages 1235 #define __NR_exit_group 1236 @@ -235,7 +235,8 @@ #define __NR_epoll_create 1243 #define __NR_epoll_ctl 1244 #define __NR_epoll_wait 1245 -#define __NR_semtimedop 1246 +#define __NR_restart_syscall 1246 +#define __NR_semtimedop 1247 #if !defined(__ASSEMBLY__) && !defined(ASSEMBLER) diff -Nru a/include/asm-sparc64/agp.h b/include/asm-sparc64/agp.h --- a/include/asm-sparc64/agp.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-sparc64/agp.h Wed Jan 15 16:57:28 2003 @@ -8,4 +8,11 @@ #define flush_agp_mappings() #define flush_agp_cache() mb() +/* + * Page-protection value to be used for AGP memory mapped into kernel space. For + * platforms which use coherent AGP DMA, this can be PAGE_KERNEL. For others, it needs to + * be an uncached mapping (such as write-combining). + */ +#define PAGE_AGP PAGE_KERNEL_NOCACHE + #endif diff -Nru a/include/asm-x86_64/agp.h b/include/asm-x86_64/agp.h --- a/include/asm-x86_64/agp.h Wed Jan 15 16:57:28 2003 +++ b/include/asm-x86_64/agp.h Wed Jan 15 16:57:28 2003 @@ -20,4 +20,11 @@ worth it. Would need a page for it. */ #define flush_agp_cache() asm volatile("wbinvd":::"memory") +/* + * Page-protection value to be used for AGP memory mapped into kernel space. For + * platforms which use coherent AGP DMA, this can be PAGE_KERNEL. For others, it needs to + * be an uncached mapping (such as write-combining). + */ +#define PAGE_AGP PAGE_KERNEL_NOCACHE + #endif diff -Nru a/include/linux/acpi_serial.h b/include/linux/acpi_serial.h --- a/include/linux/acpi_serial.h Wed Jan 15 16:57:29 2003 +++ b/include/linux/acpi_serial.h Wed Jan 15 16:57:29 2003 @@ -9,6 +9,8 @@ * */ +#include + extern void setup_serial_acpi(void *); #define ACPI_SIG_LEN 4 diff -Nru a/include/linux/agp_backend.h b/include/linux/agp_backend.h --- a/include/linux/agp_backend.h Wed Jan 15 16:57:29 2003 +++ b/include/linux/agp_backend.h Wed Jan 15 16:57:29 2003 @@ -51,6 +51,7 @@ INTEL_I850, INTEL_I860, INTEL_460GX, + INTEL_I7505, VIA_GENERIC, VIA_VP3, VIA_MVP3, diff -Nru a/include/linux/device-mapper.h b/include/linux/device-mapper.h --- a/include/linux/device-mapper.h Wed Jan 15 16:57:29 2003 +++ b/include/linux/device-mapper.h Wed Jan 15 16:57:29 2003 @@ -7,13 +7,6 @@ #ifndef _LINUX_DEVICE_MAPPER_H #define _LINUX_DEVICE_MAPPER_H -#define DM_DIR "mapper" /* Slashes not supported */ -#define DM_MAX_TYPE_NAME 16 -#define DM_NAME_LEN 128 -#define DM_UUID_LEN 129 - -#ifdef __KERNEL__ - struct dm_target; struct dm_table; struct dm_dev; @@ -100,7 +93,5 @@ int dm_register_target(struct target_type *t); int dm_unregister_target(struct target_type *t); - -#endif /* __KERNEL__ */ #endif /* _LINUX_DEVICE_MAPPER_H */ diff -Nru a/include/linux/dm-ioctl.h b/include/linux/dm-ioctl.h --- a/include/linux/dm-ioctl.h Wed Jan 15 16:57:28 2003 +++ b/include/linux/dm-ioctl.h Wed Jan 15 16:57:28 2003 @@ -7,8 +7,12 @@ #ifndef _LINUX_DM_IOCTL_H #define _LINUX_DM_IOCTL_H -#include #include + +#define DM_DIR "mapper" /* Slashes not supported */ +#define DM_MAX_TYPE_NAME 16 +#define DM_NAME_LEN 128 +#define DM_UUID_LEN 129 /* * Implements a traditional ioctl interface to the device mapper. diff -Nru a/include/linux/fs.h b/include/linux/fs.h --- a/include/linux/fs.h Wed Jan 15 16:57:28 2003 +++ b/include/linux/fs.h Wed Jan 15 16:57:28 2003 @@ -1233,6 +1233,7 @@ extern int sb_min_blocksize(struct super_block *, int); extern int generic_file_mmap(struct file *, struct vm_area_struct *); +extern int generic_file_readonly_mmap(struct file *, struct vm_area_struct *); extern int file_read_actor(read_descriptor_t * desc, struct page *page, unsigned long offset, unsigned long size); extern int file_send_actor(read_descriptor_t * desc, struct page *page, unsigned long offset, unsigned long size); extern ssize_t generic_file_read(struct file *, char *, size_t, loff_t *); diff -Nru a/include/linux/highmem.h b/include/linux/highmem.h --- a/include/linux/highmem.h Wed Jan 15 16:57:29 2003 +++ b/include/linux/highmem.h Wed Jan 15 16:57:29 2003 @@ -3,6 +3,8 @@ #include #include +#include + #include #ifdef CONFIG_HIGHMEM diff -Nru a/include/linux/irq.h b/include/linux/irq.h --- a/include/linux/irq.h Wed Jan 15 16:57:29 2003 +++ b/include/linux/irq.h Wed Jan 15 16:57:29 2003 @@ -56,15 +56,13 @@ * * Pad this out to 32 bytes for cache and indexing reasons. */ -typedef struct { +typedef struct irq_desc { unsigned int status; /* IRQ status */ hw_irq_controller *handler; struct irqaction *action; /* IRQ action list */ unsigned int depth; /* nested irq disables */ spinlock_t lock; } ____cacheline_aligned irq_desc_t; - -extern irq_desc_t irq_desc [NR_IRQS]; #include /* the arch dependent stuff */ diff -Nru a/include/linux/irq_cpustat.h b/include/linux/irq_cpustat.h --- a/include/linux/irq_cpustat.h Wed Jan 15 16:57:29 2003 +++ b/include/linux/irq_cpustat.h Wed Jan 15 16:57:29 2003 @@ -24,7 +24,7 @@ #define __IRQ_STAT(cpu, member) (irq_stat[cpu].member) #else #define __IRQ_STAT(cpu, member) ((void)(cpu), irq_stat[0].member) -#endif +#endif #endif /* arch independent irq_stat fields */ @@ -33,5 +33,10 @@ #define ksoftirqd_task(cpu) __IRQ_STAT((cpu), __ksoftirqd_task) /* arch dependent irq_stat fields */ #define nmi_count(cpu) __IRQ_STAT((cpu), __nmi_count) /* i386, ia64 */ + +#define local_softirq_pending() softirq_pending(smp_processor_id()) +#define local_syscall_count() syscall_count(smp_processor_id()) +#define local_ksoftirqd_task() ksoftirqd_task(smp_processor_id()) +#define local_nmi_count() nmi_count(smp_processor_id()) #endif /* __irq_cpustat_h */ diff -Nru a/include/linux/pci_ids.h b/include/linux/pci_ids.h --- a/include/linux/pci_ids.h Wed Jan 15 16:57:29 2003 +++ b/include/linux/pci_ids.h Wed Jan 15 16:57:29 2003 @@ -1727,6 +1727,9 @@ #define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 #define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222 #define PCI_DEVICE_ID_INTEL_7116 0x1223 +#define PCI_DEVICE_ID_INTEL_7505_0 0x2550 +#define PCI_DEVICE_ID_INTEL_7505_1 0x2552 +#define PCI_DEVICE_ID_INTEL_7205_0 0x255d #define PCI_DEVICE_ID_INTEL_82596 0x1226 #define PCI_DEVICE_ID_INTEL_82865 0x1227 #define PCI_DEVICE_ID_INTEL_82557 0x1229 diff -Nru a/include/linux/percpu.h b/include/linux/percpu.h --- a/include/linux/percpu.h Wed Jan 15 16:57:29 2003 +++ b/include/linux/percpu.h Wed Jan 15 16:57:29 2003 @@ -1,8 +1,7 @@ #ifndef __LINUX_PERCPU_H #define __LINUX_PERCPU_H -#include /* For preempt_disable() */ +#include /* For preempt_disable() */ #include - /* Must be an lvalue. */ #define get_cpu_var(var) (*({ preempt_disable(); &__get_cpu_var(var); })) #define put_cpu_var(var) preempt_enable() diff -Nru a/include/linux/ptrace.h b/include/linux/ptrace.h --- a/include/linux/ptrace.h Wed Jan 15 16:57:28 2003 +++ b/include/linux/ptrace.h Wed Jan 15 16:57:28 2003 @@ -4,6 +4,7 @@ /* structs and defines to help the user use the ptrace system call. */ #include +#include /* has the defines to get at the registers. */ diff -Nru a/include/linux/sched.h b/include/linux/sched.h --- a/include/linux/sched.h Wed Jan 15 16:57:28 2003 +++ b/include/linux/sched.h Wed Jan 15 16:57:28 2003 @@ -145,8 +145,8 @@ extern void init_idle(task_t *idle, int cpu); extern void show_state(void); -extern void show_trace(unsigned long *stack); -extern void show_stack(unsigned long *stack); +extern void show_trace(struct task_struct *); +extern void show_stack(struct task_struct *); extern void show_regs(struct pt_regs *); void io_schedule(void); @@ -461,14 +461,14 @@ #ifndef INIT_THREAD_SIZE # define INIT_THREAD_SIZE 2048*sizeof(long) -#endif - union thread_union { struct thread_info thread_info; unsigned long stack[INIT_THREAD_SIZE/sizeof(long)]; }; extern union thread_union init_thread_union; +#endif + extern struct task_struct init_task; extern struct mm_struct init_mm; diff -Nru a/include/linux/serial.h b/include/linux/serial.h --- a/include/linux/serial.h Wed Jan 15 16:57:28 2003 +++ b/include/linux/serial.h Wed Jan 15 16:57:28 2003 @@ -179,14 +179,9 @@ extern int register_serial(struct serial_struct *req); extern void unregister_serial(int line); -/* Allow complicated architectures to specify rs_table[] at run time */ -extern int early_serial_setup(struct serial_struct *req); - -#ifdef CONFIG_ACPI -/* tty ports reserved for the ACPI serial console port and debug port */ -#define ACPI_SERIAL_CONSOLE_PORT 4 -#define ACPI_SERIAL_DEBUG_PORT 5 -#endif +/* Allow architectures to override entries in serial8250_ports[] at run time: */ +struct uart_port; /* forward declaration */ +extern int early_serial_setup(struct uart_port *port); #endif /* __KERNEL__ */ #endif /* _LINUX_SERIAL_H */ diff -Nru a/include/linux/smp.h b/include/linux/smp.h --- a/include/linux/smp.h Wed Jan 15 16:57:29 2003 +++ b/include/linux/smp.h Wed Jan 15 16:57:29 2003 @@ -57,10 +57,6 @@ */ extern int smp_threads_ready; -extern volatile unsigned long smp_msg_data; -extern volatile int smp_src_cpu; -extern volatile int smp_msg_id; - #define MSG_ALL_BUT_SELF 0x8000 /* Assume <32768 CPU's */ #define MSG_ALL 0x8001 diff -Nru a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h --- a/include/linux/sunrpc/svc.h Wed Jan 15 16:57:29 2003 +++ b/include/linux/sunrpc/svc.h Wed Jan 15 16:57:29 2003 @@ -73,7 +73,7 @@ * This assumes that the non-page part of an rpc reply will fit * in a page - NFSd ensures this. lockd also has no trouble. */ -#define RPCSVC_MAXPAGES ((RPCSVC_MAXPAYLOAD+PAGE_SIZE-1)/PAGE_SIZE + 1) +#define RPCSVC_MAXPAGES ((RPCSVC_MAXPAYLOAD+PAGE_SIZE-1)/PAGE_SIZE + 2) static inline u32 svc_getu32(struct iovec *iov) { diff -Nru a/kernel/exec_domain.c b/kernel/exec_domain.c --- a/kernel/exec_domain.c Wed Jan 15 16:57:29 2003 +++ b/kernel/exec_domain.c Wed Jan 15 16:57:29 2003 @@ -196,8 +196,10 @@ put_exec_domain(oep); +#if 0 printk(KERN_DEBUG "[%s:%d]: set personality to %lx\n", current->comm, current->pid, personality); +#endif return 0; } diff -Nru a/kernel/fork.c b/kernel/fork.c --- a/kernel/fork.c Wed Jan 15 16:57:28 2003 +++ b/kernel/fork.c Wed Jan 15 16:57:28 2003 @@ -50,6 +50,7 @@ rwlock_t tasklist_lock __cacheline_aligned = RW_LOCK_UNLOCKED; /* outer */ +#if 0 /* * A per-CPU task cache - this relies on the fact that * the very last portion of sys_exit() is executed with @@ -74,6 +75,7 @@ put_cpu(); } } +#endif void add_wait_queue(wait_queue_head_t *q, wait_queue_t * wait) { @@ -176,7 +178,11 @@ init_task.rlim[RLIMIT_NPROC].rlim_max = max_threads/2; } -static struct task_struct *dup_task_struct(struct task_struct *orig) +#if 1 +extern struct task_struct *dup_task_struct (struct task_struct *orig); +#else + +struct task_struct *dup_task_struct(struct task_struct *orig) { struct task_struct *tsk; struct thread_info *ti; @@ -206,6 +212,8 @@ return tsk; } +#endif + #ifdef CONFIG_MMU static inline int dup_mmap(struct mm_struct * mm, struct mm_struct * oldmm) { @@ -822,11 +830,15 @@ if (clone_flags & CLONE_CHILD_SETTID) p->set_child_tid = child_tidptr; + else + p->set_child_tid = NULL; /* * Clear TID on mm_release()? */ if (clone_flags & CLONE_CHILD_CLEARTID) p->clear_child_tid = child_tidptr; + else + p->clear_child_tid = NULL; /* * Syscall tracing should be turned off in the child regardless diff -Nru a/kernel/ksyms.c b/kernel/ksyms.c --- a/kernel/ksyms.c Wed Jan 15 16:57:28 2003 +++ b/kernel/ksyms.c Wed Jan 15 16:57:28 2003 @@ -228,6 +228,7 @@ EXPORT_SYMBOL(generic_file_write); EXPORT_SYMBOL(generic_file_write_nolock); EXPORT_SYMBOL(generic_file_mmap); +EXPORT_SYMBOL(generic_file_readonly_mmap); EXPORT_SYMBOL(generic_ro_fops); EXPORT_SYMBOL(file_lock_list); EXPORT_SYMBOL(locks_init_lock); @@ -393,7 +394,9 @@ EXPORT_SYMBOL(del_timer); EXPORT_SYMBOL(request_irq); EXPORT_SYMBOL(free_irq); +#if !defined(CONFIG_IA64) EXPORT_SYMBOL(irq_stat); +#endif /* waitqueue handling */ EXPORT_SYMBOL(add_wait_queue); @@ -581,7 +584,9 @@ /* init task, for moving kthread roots - ought to export a function ?? */ EXPORT_SYMBOL(init_task); +#ifndef CONFIG_IA64 EXPORT_SYMBOL(init_thread_union); +#endif EXPORT_SYMBOL(tasklist_lock); EXPORT_SYMBOL(find_task_by_pid); diff -Nru a/kernel/printk.c b/kernel/printk.c --- a/kernel/printk.c Wed Jan 15 16:57:29 2003 +++ b/kernel/printk.c Wed Jan 15 16:57:29 2003 @@ -327,6 +327,12 @@ __call_console_drivers(start, end); } } +#ifdef CONFIG_IA64_EARLY_PRINTK + if (!console_drivers) { + static void early_printk (const char *str, size_t len); + early_printk(&LOG_BUF(start), end - start); + } +#endif } /* @@ -641,7 +647,11 @@ * release_cosole_sem() will print out the buffered messages for us. */ spin_lock_irqsave(&logbuf_lock, flags); +#ifdef CONFIG_IA64_EARLY_PRINTK + con_start = log_end; +#else con_start = log_start; +#endif spin_unlock_irqrestore(&logbuf_lock, flags); } release_console_sem(); @@ -694,3 +704,110 @@ tty->driver.write(tty, 0, msg, strlen(msg)); return; } + +#ifdef CONFIG_IA64_EARLY_PRINTK + +#include + +# ifdef CONFIG_IA64_EARLY_PRINTK_VGA + + +#define VGABASE ((char *)0xc0000000000b8000) +#define VGALINES 24 +#define VGACOLS 80 + +static int current_ypos = VGALINES, current_xpos = 0; + +static void +early_printk_vga (const char *str, size_t len) +{ + char c; + int i, k, j; + + while (len-- > 0) { + c = *str++; + if (current_ypos >= VGALINES) { + /* scroll 1 line up */ + for (k = 1, j = 0; k < VGALINES; k++, j++) { + for (i = 0; i < VGACOLS; i++) { + writew(readw(VGABASE + 2*(VGACOLS*k + i)), + VGABASE + 2*(VGACOLS*j + i)); + } + } + for (i = 0; i < VGACOLS; i++) { + writew(0x720, VGABASE + 2*(VGACOLS*j + i)); + } + current_ypos = VGALINES-1; + } + if (c == '\n') { + current_xpos = 0; + current_ypos++; + } else if (c != '\r') { + writew(((0x7 << 8) | (unsigned short) c), + VGABASE + 2*(VGACOLS*current_ypos + current_xpos++)); + if (current_xpos >= VGACOLS) { + current_xpos = 0; + current_ypos++; + } + } + } +} + +# endif /* CONFIG_IA64_EARLY_PRINTK_VGA */ + +# ifdef CONFIG_IA64_EARLY_PRINTK_UART + +#include +#include + +static void early_printk_uart(const char *str, size_t len) +{ + static char *uart = NULL; + unsigned long uart_base; + char c; + + if (!uart) { + uart_base = 0; +# ifdef CONFIG_SERIAL_8250_HCDP + { + extern unsigned long hcdp_early_uart(void); + uart_base = hcdp_early_uart(); + } +# endif +# if CONFIG_IA64_EARLY_PRINTK_UART_BASE + if (!uart_base) + uart_base = CONFIG_IA64_EARLY_PRINTK_UART_BASE; +# endif + if (!uart_base) + return; + + uart = ioremap(uart_base, 64); + if (!uart) + return; + } + + while (len-- > 0) { + c = *str++; + while ((readb(uart + UART_LSR) & UART_LSR_TEMT) == 0) + cpu_relax(); /* spin */ + + writeb(c, uart + UART_TX); + + if (c == '\n') + writeb('\r', uart + UART_TX); + } +} + +# endif /* CONFIG_IA64_EARLY_PRINTK_UART */ + +void early_printk(const char *str, size_t len) +{ +#ifdef CONFIG_IA64_EARLY_PRINTK_UART + early_printk_uart(str, len); +#endif +#ifdef CONFIG_IA64_EARLY_PRINTK_VGA + early_printk_vga(str, len); +#endif +} + +#endif /* CONFIG_IA64_EARLY_PRINTK */ diff -Nru a/kernel/softirq.c b/kernel/softirq.c --- a/kernel/softirq.c Wed Jan 15 16:57:28 2003 +++ b/kernel/softirq.c Wed Jan 15 16:57:28 2003 @@ -32,7 +32,10 @@ - Tasklets: serialized wrt itself. */ +/* No separate irq_stat for ia64, it is part of PSA */ +#if !defined(CONFIG_IA64) irq_cpustat_t irq_stat[NR_CPUS] ____cacheline_aligned; +#endif /* CONFIG_IA64 */ static struct softirq_action softirq_vec[32] __cacheline_aligned_in_smp; @@ -63,7 +66,7 @@ local_irq_save(flags); cpu = smp_processor_id(); - pending = softirq_pending(cpu); + pending = local_softirq_pending(); if (pending) { struct softirq_action *h; @@ -72,7 +75,7 @@ local_bh_disable(); restart: /* Reset the pending bitmask before enabling irqs */ - softirq_pending(cpu) = 0; + local_softirq_pending() = 0; local_irq_enable(); @@ -87,7 +90,7 @@ local_irq_disable(); - pending = softirq_pending(cpu); + pending = local_softirq_pending(); if (pending & mask) { mask &= ~pending; goto restart; @@ -95,7 +98,7 @@ __local_bh_enable(); if (pending) - wakeup_softirqd(cpu); + wakeup_softirqd(smp_processor_id()); } local_irq_restore(flags); @@ -315,15 +318,15 @@ __set_current_state(TASK_INTERRUPTIBLE); mb(); - ksoftirqd_task(cpu) = current; + local_ksoftirqd_task() = current; for (;;) { - if (!softirq_pending(cpu)) + if (!local_softirq_pending()) schedule(); __set_current_state(TASK_RUNNING); - while (softirq_pending(cpu)) { + while (local_softirq_pending()) { do_softirq(); cond_resched(); } diff -Nru a/mm/bootmem.c b/mm/bootmem.c --- a/mm/bootmem.c Wed Jan 15 16:57:28 2003 +++ b/mm/bootmem.c Wed Jan 15 16:57:28 2003 @@ -143,6 +143,7 @@ static void * __init __alloc_bootmem_core (bootmem_data_t *bdata, unsigned long size, unsigned long align, unsigned long goal) { + static unsigned long last_success; unsigned long i, start = 0; void *ret; unsigned long offset, remaining_size; @@ -168,6 +169,9 @@ if (goal && (goal >= bdata->node_boot_start) && ((goal >> PAGE_SHIFT) < bdata->node_low_pfn)) { preferred = goal - bdata->node_boot_start; + + if (last_success >= preferred) + preferred = last_success; } else preferred = 0; @@ -179,6 +183,8 @@ restart_scan: for (i = preferred; i < eidx; i += incr) { unsigned long j; + i = find_next_zero_bit((char *)bdata->node_bootmem_map, eidx, i); + i = (i + incr - 1) & -incr; if (test_bit(i, bdata->node_bootmem_map)) continue; for (j = i + 1; j < i + areasize; ++j) { @@ -197,6 +203,7 @@ } return NULL; found: + last_success = start << PAGE_SHIFT; if (start >= eidx) BUG(); @@ -256,21 +263,21 @@ map = bdata->node_bootmem_map; for (i = 0; i < idx; ) { unsigned long v = ~map[i / BITS_PER_LONG]; - if (v) { + if (v) { unsigned long m; - for (m = 1; m && i < idx; m<<=1, page++, i++) { + for (m = 1; m && i < idx; m<<=1, page++, i++) { if (v & m) { - count++; - ClearPageReserved(page); - set_page_count(page, 1); - __free_page(page); - } - } + count++; + ClearPageReserved(page); + set_page_count(page, 1); + __free_page(page); + } + } } else { i+=BITS_PER_LONG; - page+=BITS_PER_LONG; - } - } + page+=BITS_PER_LONG; + } + } total += count; /* diff -Nru a/mm/filemap.c b/mm/filemap.c --- a/mm/filemap.c Wed Jan 15 16:57:28 2003 +++ b/mm/filemap.c Wed Jan 15 16:57:28 2003 @@ -1293,6 +1293,14 @@ vma->vm_ops = &generic_file_vm_ops; return 0; } + +int generic_file_readonly_mmap(struct file *file, struct vm_area_struct *vma) +{ + if ((vma->vm_flags & VM_SHARED) && (vma->vm_flags & VM_WRITE)) + return -EINVAL; + vma->vm_flags &= ~VM_MAYWRITE; + return generic_file_mmap(file, vma); +} #else int generic_file_mmap(struct file * file, struct vm_area_struct * vma) { diff -Nru a/mm/highmem.c b/mm/highmem.c --- a/mm/highmem.c Wed Jan 15 16:57:29 2003 +++ b/mm/highmem.c Wed Jan 15 16:57:29 2003 @@ -452,8 +452,6 @@ mempool_t *pool; int bio_gfp; - BUG_ON((*bio_orig)->bi_idx); - /* * for non-isa bounce case, just check if the bounce pfn is equal * to or bigger than the highest pfn in the system -- in that case, diff -Nru a/mm/memory.c b/mm/memory.c --- a/mm/memory.c Wed Jan 15 16:57:29 2003 +++ b/mm/memory.c Wed Jan 15 16:57:29 2003 @@ -113,7 +113,7 @@ pmd = pmd_offset(dir, 0); pgd_clear(dir); for (j = 0; j < PTRS_PER_PMD ; j++) { - prefetchw(pmd+j+(PREFETCH_STRIDE/16)); + prefetchw(pmd + j + PREFETCH_STRIDE/sizeof(*pmd)); free_one_pmd(tlb, pmd+j); } pmd_free_tlb(tlb, pmd); diff -Nru a/mm/page_alloc.c b/mm/page_alloc.c --- a/mm/page_alloc.c Wed Jan 15 16:57:28 2003 +++ b/mm/page_alloc.c Wed Jan 15 16:57:28 2003 @@ -1049,6 +1049,41 @@ memset(pgdat->valid_addr_bitmap, 0, size); } +static void __init memmap_init(struct page *start, unsigned long size, + int nid, unsigned long zone, unsigned long start_pfn) +{ + struct page *page; + + /* + * Initially all pages are reserved - free ones are freed + * up by free_all_bootmem() once the early boot process is + * done. Non-atomic initialization, single-pass. + */ + + for (page = start; page < (start + size); page++) { + set_page_zone(page, nid * MAX_NR_ZONES + zone); + set_page_count(page, 0); + SetPageReserved(page); + INIT_LIST_HEAD(&page->list); +#ifdef WANT_PAGE_VIRTUAL + if (zone != ZONE_HIGHMEM) + /* + * The shift left won't overflow because the + * ZONE_NORMAL is below 4G. + */ + set_page_address(page, __va(start_pfn << PAGE_SHIFT)); +#endif + start_pfn++; + } +} + +#ifdef HAVE_ARCH_MEMMAP_INIT +#define MEMMAP_INIT(start, size, nid, zone, start_pfn) \ + arch_memmap_init(memmap_init, start, size, nid, zone, start_pfn) +#else +#define MEMMAP_INIT(start, size, nid, zone, start_pfn) \ + memmap_init(start, size, nid, zone, start_pfn) +#endif /* * Set up the zone data structures: * - mark all pages reserved @@ -1160,28 +1195,8 @@ if ((zone_start_pfn) & (zone_required_alignment-1)) printk("BUG: wrong zone alignment, it will crash\n"); - /* - * Initially all pages are reserved - free ones are freed - * up by free_all_bootmem() once the early boot process is - * done. Non-atomic initialization, single-pass. - */ - for (i = 0; i < size; i++) { - struct page *page = lmem_map + local_offset + i; - set_page_zone(page, nid * MAX_NR_ZONES + j); - set_page_count(page, 0); - SetPageReserved(page); - INIT_LIST_HEAD(&page->list); -#ifdef WANT_PAGE_VIRTUAL - if (j != ZONE_HIGHMEM) - /* - * The shift left won't overflow because the - * ZONE_NORMAL is below 4G. - */ - set_page_address(page, - __va(zone_start_pfn << PAGE_SHIFT)); -#endif - zone_start_pfn++; - } + MEMMAP_INIT(lmem_map + local_offset,size,nid,j,zone_start_pfn); + zone_start_pfn += size; local_offset += size; for (i = 0; ; i++) { diff -Nru a/scripts/kallsyms.c b/scripts/kallsyms.c --- a/scripts/kallsyms.c Wed Jan 15 16:57:29 2003 +++ b/scripts/kallsyms.c Wed Jan 15 16:57:29 2003 @@ -12,6 +12,15 @@ #include #include +#include + +#if CONFIG_ALPHA || CONFIG_IA64 || CONFIG_MIPS64 || CONFIG_PPC64 || CONFIG_S390X \ + || CONFIG_SPARC64 || CONFIG_X86_64 +# define ADDR_DIRECTIVE ".quad" +#else +# define ADDR_DIRECTIVE ".long" +#endif + struct sym_entry { unsigned long long addr; char type; @@ -106,7 +115,7 @@ if (table[i].addr == last_addr) continue; - printf("\t.long\t%#llx\n", table[i].addr); + printf("\t"ADDR_DIRECTIVE"\t%#llx\n", table[i].addr); valid++; last_addr = table[i].addr; } @@ -115,7 +124,7 @@ printf(".globl kallsyms_num_syms\n"); printf("\t.align 8\n"); printf("kallsyms_num_syms:\n"); - printf("\t.long\t%d\n", valid); + printf("\t"ADDR_DIRECTIVE"\t%d\n", valid); printf("\n"); printf(".globl kallsyms_names\n"); diff -Nru a/sound/oss/cs4281/cs4281m.c b/sound/oss/cs4281/cs4281m.c --- a/sound/oss/cs4281/cs4281m.c Wed Jan 15 16:57:29 2003 +++ b/sound/oss/cs4281/cs4281m.c Wed Jan 15 16:57:29 2003 @@ -1946,8 +1946,8 @@ len -= x; } CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO - "cs4281: clear_advance(): memset %d at 0x%.8x for %d size \n", - (unsigned)c, (unsigned)((char *) buf) + bptr, len)); + "cs4281: clear_advance(): memset %d at %p for %d size \n", + (unsigned)c, ((char *) buf) + bptr, len)); memset(((char *) buf) + bptr, c, len); } @@ -1982,9 +1982,8 @@ wake_up(&s->dma_adc.wait); } CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO - "cs4281: cs4281_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n", - (unsigned)s, s->dma_adc.hwptr, - s->dma_adc.total_bytes, s->dma_adc.count)); + "cs4281: cs4281_update_ptr(): s=%p hwptr=%d total_bytes=%d count=%d \n", + s, s->dma_adc.hwptr, s->dma_adc.total_bytes, s->dma_adc.count)); } // update DAC pointer // @@ -2016,11 +2015,10 @@ // Continue to play silence until the _release. // CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO - "cs4281: cs4281_update_ptr(): memset %d at 0x%.8x for %d size \n", + "cs4281: cs4281_update_ptr(): memset %d at %p for %d size \n", (unsigned)(s->prop_dac.fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0, - (unsigned)s->dma_dac.rawbuf, - s->dma_dac.dmasize)); + s->dma_dac.rawbuf, s->dma_dac.dmasize)); memset(s->dma_dac.rawbuf, (s->prop_dac. fmt & (AFMT_U8 | AFMT_U16_LE)) ? @@ -2051,9 +2049,8 @@ } } CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO - "cs4281: cs4281_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n", - (unsigned) s, s->dma_dac.hwptr, - s->dma_dac.total_bytes, s->dma_dac.count)); + "cs4281: cs4281_update_ptr(): s=%p hwptr=%d total_bytes=%d count=%d \n", + s, s->dma_dac.hwptr, s->dma_dac.total_bytes, s->dma_dac.count)); } } @@ -2184,8 +2181,7 @@ VALIDATE_STATE(s); CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO - "cs4281: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n", - (unsigned) s, cmd)); + "cs4281: mixer_ioctl(): s=%p cmd=0x%.8x\n", s, cmd)); #if CSDEBUG cs_printioctl(cmd); #endif @@ -2750,9 +2746,8 @@ CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO "cs4281: CopySamples()+ ")); CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO - " dst=0x%x src=0x%x count=%d iChannels=%d fmt=0x%x\n", - (unsigned) dst, (unsigned) src, (unsigned) count, - (unsigned) iChannels, (unsigned) fmt)); + " dst=%p src=%p count=%d iChannels=%d fmt=0x%x\n", + dst, src, (unsigned) count, (unsigned) iChannels, (unsigned) fmt)); // Gershwin does format conversion in hardware so normally // we don't do any host based coversion. The data formatter @@ -2832,9 +2827,9 @@ void *src = hwsrc; //default to the standard destination buffer addr CS_DBGOUT(CS_FUNCTION, 6, printk(KERN_INFO - "cs_copy_to_user()+ fmt=0x%x fmt_o=0x%x cnt=%d dest=0x%.8x\n", + "cs_copy_to_user()+ fmt=0x%x fmt_o=0x%x cnt=%d dest=%p\n", s->prop_adc.fmt, s->prop_adc.fmt_original, - (unsigned) cnt, (unsigned) dest)); + (unsigned) cnt, dest)); if (cnt > s->dma_adc.dmasize) { cnt = s->dma_adc.dmasize; @@ -2879,7 +2874,7 @@ unsigned copied = 0; CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2, - printk(KERN_INFO "cs4281: cs4281_read()+ %d \n", count)); + printk(KERN_INFO "cs4281: cs4281_read()+ %Zu \n", count)); VALIDATE_STATE(s); if (ppos != &file->f_pos) @@ -2902,7 +2897,7 @@ // while (count > 0) { CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO - "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n", + "_read() count>0 count=%Zu .count=%d .swptr=%d .hwptr=%d \n", count, s->dma_adc.count, s->dma_adc.swptr, s->dma_adc.hwptr)); spin_lock_irqsave(&s->lock, flags); @@ -2959,11 +2954,10 @@ // the "cnt" is the number of bytes to read. CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO - "_read() copy_to cnt=%d count=%d ", cnt, count)); + "_read() copy_to cnt=%d count=%Zu ", cnt, count)); CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO - " .dmasize=%d .count=%d buffer=0x%.8x ret=%d\n", - s->dma_adc.dmasize, s->dma_adc.count, - (unsigned) buffer, ret)); + " .dmasize=%d .count=%d buffer=%p ret=%Zd\n", + s->dma_adc.dmasize, s->dma_adc.count, buffer, ret)); if (cs_copy_to_user (s, buffer, s->dma_adc.rawbuf + swptr, cnt, &copied)) @@ -2979,7 +2973,7 @@ start_adc(s); } CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2, - printk(KERN_INFO "cs4281: cs4281_read()- %d\n", ret)); + printk(KERN_INFO "cs4281: cs4281_read()- %Zd\n", ret)); return ret; } @@ -2995,7 +2989,7 @@ int cnt; CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2, - printk(KERN_INFO "cs4281: cs4281_write()+ count=%d\n", + printk(KERN_INFO "cs4281: cs4281_write()+ count=%Zu\n", count)); VALIDATE_STATE(s); @@ -3051,7 +3045,7 @@ start_dac(s); } CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2, - printk(KERN_INFO "cs4281: cs4281_write()- %d\n", ret)); + printk(KERN_INFO "cs4281: cs4281_write()- %Zd\n", ret)); return ret; } @@ -3172,8 +3166,7 @@ int val, mapped, ret; CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO - "cs4281: cs4281_ioctl(): file=0x%.8x cmd=0x%.8x\n", - (unsigned) file, cmd)); + "cs4281: cs4281_ioctl(): file=%p cmd=0x%.8x\n", file, cmd)); #if CSDEBUG cs_printioctl(cmd); #endif @@ -3603,8 +3596,8 @@ (struct cs4281_state *) file->private_data; CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO - "cs4281: cs4281_release(): inode=0x%.8x file=0x%.8x f_mode=%d\n", - (unsigned) inode, (unsigned) file, file->f_mode)); + "cs4281: cs4281_release(): inode=%p file=%p f_mode=%d\n", + inode, file, file->f_mode)); VALIDATE_STATE(s); @@ -3638,8 +3631,8 @@ struct list_head *entry; CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO - "cs4281: cs4281_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n", - (unsigned) inode, (unsigned) file, file->f_mode)); + "cs4281: cs4281_open(): inode=%p file=%p f_mode=0x%x\n", + inode, file, file->f_mode)); list_for_each(entry, &cs4281_devs) { @@ -4348,10 +4341,8 @@ CS_DBGOUT(CS_INIT, 2, printk(KERN_INFO - "cs4281: probe() BA0=0x%.8x BA1=0x%.8x pBA0=0x%.8x pBA1=0x%.8x \n", - (unsigned) temp1, (unsigned) temp2, - (unsigned) s->pBA0, (unsigned) s->pBA1)); - + "cs4281: probe() BA0=0x%.8x BA1=0x%.8x pBA0=%p pBA1=%p \n", + (unsigned) temp1, (unsigned) temp2, s->pBA0, s->pBA1)); CS_DBGOUT(CS_INIT, 2, printk(KERN_INFO "cs4281: probe() pBA0phys=0x%.8x pBA1phys=0x%.8x\n", @@ -4398,15 +4389,13 @@ if (pmdev) { CS_DBGOUT(CS_INIT | CS_PM, 4, printk(KERN_INFO - "cs4281: probe() pm_register() succeeded (0x%x).\n", - (unsigned)pmdev)); + "cs4281: probe() pm_register() succeeded (%p).\n", pmdev)); pmdev->data = s; } else { CS_DBGOUT(CS_INIT | CS_PM | CS_ERROR, 0, printk(KERN_INFO - "cs4281: probe() pm_register() failed (0x%x).\n", - (unsigned)pmdev)); + "cs4281: probe() pm_register() failed (%p).\n", pmdev)); s->pm.flags |= CS4281_PM_NOT_REGISTERED; } #endif diff -Nru a/sound/oss/cs4281/cs4281pm-24.c b/sound/oss/cs4281/cs4281pm-24.c --- a/sound/oss/cs4281/cs4281pm-24.c Wed Jan 15 16:57:29 2003 +++ b/sound/oss/cs4281/cs4281pm-24.c Wed Jan 15 16:57:29 2003 @@ -46,8 +46,8 @@ struct cs4281_state *state; CS_DBGOUT(CS_PM, 2, printk(KERN_INFO - "cs4281: cs4281_pm_callback dev=0x%x rqst=0x%x state=%d\n", - (unsigned)dev,(unsigned)rqst,(unsigned)data)); + "cs4281: cs4281_pm_callback dev=%p rqst=0x%x state=%p\n", + dev,(unsigned)rqst,data)); state = (struct cs4281_state *) dev->data; if (state) { switch(rqst) { diff -Nru a/usr/Makefile b/usr/Makefile --- a/usr/Makefile Wed Jan 15 16:57:29 2003 +++ b/usr/Makefile Wed Jan 15 16:57:29 2003 @@ -5,12 +5,9 @@ clean-files := initramfs_data.cpio.gz -LDFLAGS_initramfs_data.o := $(LDFLAGS_BLOB) -r -T - -$(obj)/initramfs_data.o: $(src)/initramfs_data.scr $(obj)/initramfs_data.cpio.gz FORCE - $(call if_changed,ld) - $(obj)/initramfs_data.cpio.gz: $(obj)/gen_init_cpio ./$< | gzip -9c > $@ - +$(obj)/initramfs_data.S: $(obj)/initramfs_data.cpio.gz + echo '.section ".init.ramfs", "a"' > $@ + od -v -An -t x1 -w8 $^ | cut -c2- | sed -e s"/ /,0x/g" -e s"/^/.byte 0x"/ >> $@