# This is a BitKeeper generated patch for the following project: # Project Name: Linux kernel tree # This patch format is intended for GNU patch command version 2.5 or higher. # This patch includes the following deltas: # ChangeSet 1.1238 -> 1.1244 # arch/i386/kernel/process.c 1.51.1.4 -> 1.56 # include/asm-x86_64/agp.h 1.2 -> 1.4 # arch/ia64/kernel/fsys.S 1.18 -> 1.20 # arch/ppc64/kernel/signal.c 1.28 -> 1.29 # include/asm-ia64/sn/pci/pcibr_private.h 1.8 -> 1.9 # drivers/input/serio/i8042-io.h 1.4.1.1 -> 1.6 # include/asm-parisc/unistd.h 1.8.1.1 -> 1.11 # arch/sparc/kernel/module.c 1.11 -> 1.12 # include/asm-ia64/sn/pci/pciio.h 1.6 -> 1.7 # include/asm-i386/agp.h 1.1.1.1 -> 1.4 # include/asm-ppc64/page.h 1.19 -> 1.21 # include/asm-generic/sections.h 1.2 -> 1.3 # arch/alpha/kernel/module.c 1.5 -> 1.6 # kernel/ksyms.c 1.203.1.15 -> 1.211 # include/asm-ppc64/unistd.h 1.20.1.2 -> 1.26 # arch/ppc64/kernel/entry.S 1.26.1.1 -> 1.29 # include/asm-mips/unistd.h 1.6.1.2 -> 1.10 # include/asm-alpha/agp.h 1.2 -> 1.4 # fs/select.c 1.20 -> 1.21 # arch/ia64/Makefile 1.59 -> 1.60 # arch/ia64/kernel/efi.c 1.22 -> 1.24 # include/linux/timex.h 1.5.1.3 -> 1.11 # include/asm-alpha/hw_irq.h 1.2 -> 1.4 # include/linux/mm.h 1.121.1.8 -> 1.126 # include/linux/init.h 1.26 -> 1.27 # arch/arm/kernel/module.c 1.7 -> 1.8 # drivers/serial/8250.c 1.34 -> 1.35 # arch/ia64/sn/io/sn2/pcibr/pcibr_error.c 1.5 -> 1.6 # include/asm-ia64/io.h 1.13.1.4 -> 1.19 # arch/ppc64/kernel/udbg.c 1.8 -> 1.10 # include/asm-ia64/sn/sn2/shub_mmr_t.h 1.2 -> 1.3 # arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c 1.5 -> 1.6 # include/asm-ppc64/processor.h 1.30.1.1 -> 1.32 # include/asm-i386/ptrace.h 1.5 -> 1.7 # include/asm-ia64/spinlock.h 1.16 -> 1.18 # include/asm-sparc/unistd.h 1.20.1.5 -> 1.25 # arch/ia64/defconfig 1.19.1.1 -> 1.21 # drivers/char/drm/i830_dma.c 1.18.1.1 -> 1.20 # include/linux/sched.h 1.151.1.12 -> 1.161 # kernel/fork.c 1.124.1.14 -> 1.131 # include/asm-ppc64/module.h 1.4 -> 1.6 # kernel/sysctl.c 1.46.1.6 -> 1.51 # kernel/sys.c 1.43.1.12 -> 1.51 # include/asm-ia64/unistd.h 1.35 -> 1.36 # include/asm-ppc64/thread_info.h 1.7.1.1 -> 1.9 # include/asm-ppc64/ucontext.h 1.3 -> 1.5 # include/asm-sparc64/agp.h 1.1 -> 1.3 # arch/ppc64/kernel/chrp_setup.c 1.29.1.1 -> 1.32 # include/asm-ia64/signal.h 1.9 -> 1.10 # include/asm-i386/thread_info.h 1.11.1.2 -> 1.14 # arch/ia64/hp/common/sba_iommu.c 1.29 -> 1.32 # arch/ppc64/kernel/rtas.c 1.11 -> 1.13 # drivers/char/drm/r128_cce.c 1.12.1.2 -> 1.15 # arch/ia64/sn/kernel/irq.c 1.8 -> 1.9 # drivers/char/drm/drm_memory_debug.h 1.1.1.2 -> 1.4 # include/asm-sparc64/unistd.h 1.19.1.5 -> 1.24 # arch/i386/kernel/traps.c 1.52.1.5 -> 1.57 # drivers/char/drm/drm_memory.h 1.8.1.4 -> 1.12 # arch/i386/kernel/Makefile 1.44.1.5 -> 1.49 # include/asm-ppc/unistd.h 1.23.1.3 -> 1.27 # drivers/char/drm/radeon_cp.c 1.20 -> 1.21 # include/asm-ia64/sn/nodepda.h 1.7 -> 1.9 # include/asm-ppc64/sigcontext.h 1.4 -> 1.6 # include/linux/serial.h 1.8.1.1 -> 1.10 # arch/ia64/kernel/time.c 1.31 -> 1.33 # include/asm-ppc/pgtable.h 1.23.1.1 -> 1.25 # include/asm-ppc/thread_info.h 1.7.1.2 -> 1.10 # kernel/time.c 1.11.1.5 -> 1.17 # drivers/char/drm/drm_bufs.h 1.14.1.2 -> 1.17 # arch/ia64/kernel/smpboot.c 1.38 -> 1.39 # kernel/softirq.c 1.39.1.5 -> 1.43 # arch/ppc64/kernel/LparData.c 1.9 -> 1.11 # arch/ia64/kernel/entry.S 1.49 -> 1.51 # drivers/net/tulip/media.c 1.11 -> 1.12 # drivers/acpi/pci_root.c 1.13.1.3 -> 1.17 # arch/ppc/kernel/module.c 1.9 -> 1.10 # include/asm-ppc64/types.h 1.3 -> 1.5 # arch/ia64/sn/io/machvec/pci_dma.c 1.12 -> 1.13 # arch/ppc64/kernel/ras.c 1.5 -> 1.7 # include/asm-ia64/sn/router.h 1.5 -> 1.6 # include/asm-ia64/uaccess.h 1.10 -> 1.11 # include/asm-ia64/sn/ksys/l1.h 1.6 -> 1.7 # include/asm-parisc/thread_info.h 1.2.1.1 -> 1.4 # include/asm-um/thread_info.h 1.3.1.1 -> 1.5 # include/asm-ia64/sn/ioc3.h 1.3 -> (deleted) # drivers/char/drm/i810_dma.c 1.26.1.3 -> 1.30 # include/asm-h8300/thread_info.h 1.1.1.2 -> 1.4 # include/asm-ia64/numa.h 1.5 -> 1.6 # include/linux/nfs_fs.h 1.45.1.2 -> 1.48 # drivers/media/video/Makefile 1.18.1.3 -> 1.22 # include/asm-ia64/sn/hcl.h 1.6 -> 1.7 # include/asm-v850/thread_info.h 1.2.1.1 -> 1.4 # include/asm-ppc64/proc_fs.h 1.2 -> 1.4 # drivers/acpi/tables.c 1.14.1.1 -> 1.16 # mm/swap.c 1.52 -> 1.54 # include/linux/pci_ids.h 1.103.1.20 -> 1.110 # include/linux/irq.h 1.6.1.3 -> 1.12 # include/linux/moduleloader.h 1.6 -> 1.7 # include/asm-alpha/unistd.h 1.18.1.4 -> 1.23 # include/asm-m68knommu/thread_info.h 1.2.1.1 -> 1.4 # arch/ppc64/kernel/irq.c 1.30.1.1 -> 1.32 # drivers/acpi/pci_irq.c 1.16.1.5 -> 1.22 # mm/memory.c 1.123.1.11 -> 1.133 # include/linux/moduleparam.h 1.3 -> 1.4 # include/asm-ia64/sn/klclock.h 1.3 -> (deleted) # arch/ppc64/kernel/rtas-proc.c 1.6 -> 1.8 # include/asm-arm/thread_info.h 1.6.1.2 -> 1.9 # arch/ia64/kernel/mca.c 1.41 -> 1.42 # include/linux/pci.h 1.90.1.17 -> 1.97 # arch/ppc64/kernel/setup.c 1.28.1.2 -> 1.31 # include/asm-ia64/hw_irq.h 1.9 -> 1.10 # arch/ia64/kernel/process.c 1.39.1.6 -> 1.46 # arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c 1.8 -> 1.9 # include/asm-m68k/unistd.h 1.8 -> 1.10 # arch/i386/kernel/module.c 1.11 -> 1.12 # arch/ia64/kernel/acpi.c 1.48 -> 1.50 # drivers/serial/Makefile 1.14.1.5 -> 1.21 # include/asm-ppc64/naca.h 1.6 -> 1.8 # arch/ia64/hp/sim/boot/boot_head.S 1.1 -> 1.2 # include/asm-h8300/unistd.h 1.1.1.1 -> 1.4 # arch/ia64/sn/io/machvec/iomv.c 1.7 -> 1.8 # include/asm-ia64/param.h 1.3 -> 1.4 # arch/ia64/ia32/elfcore32.h 1.2 -> 1.3 # include/linux/acpi_serial.h 1.2.1.1 -> 1.4 # drivers/char/mem.c 1.42.1.1 -> 1.44 # arch/ppc64/kernel/traps.c 1.19.1.1 -> 1.21 # include/asm-m68knommu/unistd.h 1.2 -> 1.4 # kernel/posix-timers.c 1.19.1.1 -> 1.21 # arch/ppc64/kernel/head.S 1.36 -> 1.38 # include/asm-ppc64/xics.h 1.5 -> 1.7 # arch/ia64/sn/io/sn2/shub.c 1.5 -> 1.6 # include/linux/sunrpc/svc.h 1.20.1.5 -> 1.26 # include/linux/sysctl.h 1.47.1.4 -> 1.51 # arch/ppc64/kernel/xics.c 1.25.1.1 -> 1.27 # drivers/net/tg3.c 1.72.1.35 -> 1.78 # include/linux/smp.h 1.22.1.4 -> 1.25 # usr/Makefile 1.6.1.3 -> 1.10 # arch/v850/kernel/module.c 1.5 -> 1.6 # drivers/media/radio/Makefile 1.9 -> 1.10 # arch/ppc64/kernel/htab.c 1.34.1.1 -> 1.36 # arch/ppc64/kernel/open_pic.c 1.15.1.1 -> 1.17 # arch/ppc64/mm/init.c 1.46.1.4 -> 1.52 # drivers/char/agp/i460-agp.c 1.25.1.3 -> 1.30 # arch/ppc64/kernel/process.c 1.35.1.2 -> 1.39 # arch/ppc64/kernel/pci_dma.c 1.16 -> 1.17 # arch/ia64/ia32/sys_ia32.c 1.75 -> 1.76 # arch/ia64/sn/io/sn2/pic.c 1.3 -> 1.4 # mm/mmap.c 1.85.1.5 -> 1.89 # fs/proc/base.c 1.42.1.13 -> 1.50 # include/linux/time.h 1.16.1.5 -> 1.20 # arch/sparc64/kernel/module.c 1.14 -> 1.15 # arch/ppc64/kernel/open_pic_defs.h 1.2 -> 1.4 # arch/ia64/sn/io/drivers/ioconfig_bus.c 1.4 -> 1.5 # include/asm-i386/unistd.h 1.25.1.4 -> 1.30 # include/asm-ia64/ptrace.h 1.15 -> 1.16 # sound/oss/cs4281/cs4281pm-24.c 1.3.1.1 -> 1.5 # arch/ppc64/kernel/asm-offsets.c 1.14 -> 1.16 # include/asm-m68k/thread_info.h 1.4.1.1 -> 1.6 # Makefile 1.410.1.17 -> 1.421 # fs/fcntl.c 1.28.1.1 -> 1.30 # include/asm-s390/thread_info.h 1.4.1.1 -> 1.6 # include/asm-x86_64/unistd.h 1.14.1.3 -> 1.19 # include/asm-ppc64/mmu.h 1.7 -> 1.9 # arch/ppc64/mm/numa.c 1.7.1.1 -> 1.9 # drivers/char/agp/backend.c 1.83.1.3 -> 1.86 # arch/ppc64/kernel/syscalls.c 1.11.1.1 -> 1.14 # include/asm-x86_64/thread_info.h 1.12.1.1 -> 1.14 # include/asm-ppc64/ptrace.h 1.2 -> 1.4 # arch/ppc64/kernel/sys_ppc32.c 1.66 -> 1.67 # include/asm-sparc64/thread_info.h 1.10.1.2 -> 1.13 # arch/ppc64/kernel/prom.c 1.28.1.3 -> 1.33 # kernel/module.c 1.86.1.6 -> 1.92 # include/asm-x86_64/pgtable.h 1.21.1.1 -> 1.23 # arch/ia64/kernel/salinfo.c 1.3 -> 1.4 # arch/ppc64/kernel/iSeries_setup.c 1.15.1.1 -> 1.18 # arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c 1.5 -> 1.6 # drivers/char/drm/drmP.h 1.23.1.4 -> 1.27 # arch/ppc64/kernel/smp.c 1.40.1.1 -> 1.42 # arch/ia64/sn/io/sn2/ml_SN_intr.c 1.3 -> 1.5 # include/asm-i386/pgtable.h 1.35.1.2 -> 1.38 # net/ipv4/tcp_input.c 1.39.1.6 -> 1.43 # arch/ppc64/mm/fault.c 1.10.1.1 -> 1.13 # include/linux/highmem.h 1.25.1.2 -> 1.28 # arch/ppc64/kernel/pacaData.c 1.7.1.1 -> 1.10 # arch/ia64/sn/io/machvec/pci_bus_cvlink.c 1.9 -> 1.10 # mm/slab.c 1.93.1.6 -> 1.99 # include/linux/module.h 1.66.1.2 -> 1.69 # kernel/sched.c 1.193.1.15 -> 1.202 # drivers/char/agp/hp-agp.c 1.24.1.2 -> 1.29 # arch/ia64/sn/io/sn2/pcibr/pcibr_config.c 1.3 -> 1.4 # drivers/acpi/osl.c 1.37.1.5 -> 1.43 # include/linux/jbd.h 1.21.1.17 -> 1.25 # drivers/char/drm/drm_drv.h 1.20.1.4 -> 1.24 # arch/alpha/kernel/traps.c 1.24.1.2 -> 1.27 # kernel/timer.c 1.59.1.8 -> 1.67 # include/asm-ia64/sn/ksys/elsc.h 1.5 -> 1.6 # include/asm-ia64/sn/sn2/intr.h 1.3 -> 1.4 # drivers/scsi/sym53c8xx_2/sym_malloc.c 1.2 -> 1.4 # arch/ppc64/kernel/pci.c 1.33.1.2 -> 1.37 # arch/ppc64/xmon/xmon.c 1.26.1.1 -> 1.29 # include/asm-sh/unistd.h 1.5.1.1 -> 1.8 # include/asm-m68k/pgtable.h 1.8 -> 1.9 # arch/ppc64/kernel/misc.S 1.62 -> 1.63 # drivers/char/drm/mga_dma.c 1.13.1.1 -> 1.15 # include/asm-ia64/acpi.h 1.7 -> 1.10 # arch/s390/kernel/module.c 1.8.1.1 -> 1.10 # drivers/char/drm/mga_drv.h 1.13.1.1 -> 1.15 # arch/x86_64/kernel/module.c 1.9.1.2 -> 1.12 # arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c 1.3 -> 1.4 # include/linux/percpu.h 1.5.1.2 -> 1.7 # arch/arm/kernel/process.c 1.28.1.1 -> 1.30 # include/asm-alpha/thread_info.h 1.5.1.1 -> 1.7 # arch/ppc64/kernel/signal32.c 1.40 -> 1.42 # include/asm-cris/unistd.h 1.10.1.1 -> 1.13 # drivers/serial/Kconfig 1.8.1.7 -> 1.16 # arch/ia64/hp/sim/boot/bootloader.c 1.10 -> 1.11 # drivers/char/drm/gamma_dma.c 1.12.1.3 -> 1.15 # arch/ppc64/kernel/rtas_flash.c 1.5 -> 1.7 # net/sunrpc/svc.c 1.21.1.1 -> 1.23 # include/linux/irq_cpustat.h 1.7.1.3 -> 1.10 # arch/ia64/kernel/perfmon.c 1.56.1.1 -> 1.60 # include/asm-arm/unistd.h 1.16.1.1 -> 1.19 # arch/ia64/Kconfig 1.38.2.2 -> 1.43 # include/asm-ppc64/mmzone.h 1.11.1.1 -> 1.13 # include/asm-ppc64/pgtable.h 1.23 -> 1.24 # include/asm-sparc/thread_info.h 1.4.1.1 -> 1.6 # include/asm-ppc64/io.h 1.8 -> 1.10 # arch/ia64/kernel/traps.c 1.37 -> 1.38 # arch/ia64/scripts/toolchain-flags 1.4 -> 1.5 # drivers/video/radeonfb.c 1.26.1.4 -> 1.29 # include/asm-ia64/sn/sn2/shub.h 1.2 -> 1.3 # include/asm-v850/unistd.h 1.6 -> 1.8 # include/asm-ppc64/topology.h 1.8 -> 1.9 # kernel/kallsyms.c 1.11.1.3 -> 1.15 # arch/ppc64/kernel/Makefile 1.27.1.1 -> 1.30 # arch/ppc64/kernel/module.c 1.6 -> 1.7 # include/asm-ppc64/rtas.h 1.6 -> 1.8 # arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c 1.5 -> 1.6 # arch/ia64/kernel/init_task.c 1.12 -> 1.13 # include/asm-i386/hw_irq.h 1.21.1.3 -> 1.26 # sound/oss/cs4281/cs4281m.c 1.21.1.5 -> 1.25 # arch/ia64/kernel/Makefile 1.25 -> 1.26 # arch/ppc64/kernel/align.c 1.10 -> 1.11 # kernel/printk.c 1.25.1.1 -> 1.29 # drivers/scsi/qla1280.c 1.38.1.9 -> 1.42 # arch/ppc64/kernel/ioctl32.c 1.35.1.2 -> 1.38 # arch/ppc64/kernel/pSeries_lpar.c 1.21 -> 1.23 # drivers/char/drm/drm_vm.h 1.23.1.2 -> 1.26 # arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c 1.12 -> 1.13 # include/asm-s390/unistd.h 1.16 -> 1.18 # arch/ia64/kernel/unwind.c 1.32 -> 1.33 # arch/parisc/kernel/module.c 1.5.1.1 -> 1.7 # drivers/scsi/sym53c8xx_2/sym_glue.c 1.23.1.13 -> 1.28 # (new) -> 1.1 arch/ia64/oprofile/init.c # (new) -> 1.1 arch/ia64/oprofile/Makefile # (new) -> 1.1 drivers/media/video/dummy.c # (new) -> 1.1 arch/ia64/kernel/perfmon_hpsim.h # (new) -> 1.1 arch/ia64/oprofile/Kconfig # (new) -> 1.1 drivers/media/radio/dummy.c # (new) -> 1.1 include/asm-ia64/intel_intrin.h # # The following is the BitKeeper ChangeSet Log # -------------------------------------------- # 03/09/08 jbarnes@sgi.com 1.1153.67.26 # [PATCH] ia64: misc. sn2 updates # # Fix a couple of sn2 files. # -------------------------------------------- # 03/09/08 jbarnes@sgi.com 1.1153.67.27 # [PATCH] ia64: fix current usage in sn2 code # # For some reason, we had a structure field called 'current'. This patch # fixes that. # -------------------------------------------- # 03/09/08 davidm@tiger.hpl.hp.com 1.1153.65.14 # Merge tiger.hpl.hp.com:/data1/bk/lia64/to-linus-2.5 # into tiger.hpl.hp.com:/data1/bk/lia64/linux-ia64-2.5 # -------------------------------------------- # 03/09/08 davidm@tiger.hpl.hp.com 1.1153.65.15 # Mark initcall macros with __attribute_used__ so the definitions do not # get optimized away by the compiler (such as the latest GCC pre-3.4). # -------------------------------------------- # 03/09/08 davidm@tiger.hpl.hp.com 1.1239 # Merge tiger.hpl.hp.com:/data1/bk/vanilla/linux-2.5 # into tiger.hpl.hp.com:/data1/bk/lia64/to-linus-2.5 # -------------------------------------------- # 03/09/08 davidm@tiger.hpl.hp.com 1.1240 # Initial merge with 2.6.0-test5. # -------------------------------------------- # 03/09/08 suresh.b.siddha@intel.com 1.1239.1.1 # [PATCH] ia64: fix typo in spinlock.h # # -------------------------------------------- # 03/09/08 arun.sharma@intel.com 1.1239.1.2 # [PATCH] ia64: MINSIGSTKSZ on ia32 # # MINSIGSTKSZ is defined differently for i386 and ia64. This patch improves # compatibility with apps which use sigaltstack(2) with sizes between # MINSIGSTKSZ_IA32 and MINSIGSTKSZ. # -------------------------------------------- # 03/09/08 peterc@gelato.unsw.edu.au 1.1239.1.3 # [PATCH] ia64: unwind.c fix for spinlock-debug compilation # # If you try to compile 2.6.0-test[45] with spinlock debugging on, then # unwind.c won't compile, because it uses a #define magic that hides # the variable in the spinlock debugging code (also called magic). # -------------------------------------------- # 03/09/08 davidm@tiger.hpl.hp.com 1.1241 # Merge tiger.hpl.hp.com:/data1/bk/lia64/to-linus-2.5 # into tiger.hpl.hp.com:/data1/bk/lia64/linux-ia64-2.5 # -------------------------------------------- # 03/09/08 davidm@tiger.hpl.hp.com 1.1242 # Some more __attribute_used__ fixes. # -------------------------------------------- # 03/09/09 jbarnes@sgi.com 1.1239.1.4 # [PATCH] ia64: cpumask_t fixes # # This patch coverts a few spots to use cpumask_t instead of unsigned # long. # -------------------------------------------- # 03/09/09 jbarnes@sgi.com 1.1239.1.5 # [PATCH] ia64: update Kconfig comment for NR_CPUS # # -------------------------------------------- # 03/09/15 jbarnes@sgi.com 1.1239.1.6 # [PATCH] ia64: turn off SLIT debugging # # This code works pretty well now, so we don't need to dump all this stuff # at boot time (esp. on 128 node systems). # -------------------------------------------- # 03/09/15 jbarnes@sgi.com 1.1239.1.7 # [PATCH] ia64: protect PAL mapping printk with EFI_DEBUG # # Having this print out for every CPU on a large system was a pain, so # protect the printk with EFI_DEBUG. # -------------------------------------------- # 03/09/15 davidm@tiger.hpl.hp.com 1.1239.1.8 # ia64: Re-enable /proc/sal support. Bug reported by Stephane Eranian, patch # by Jesse Barnes. # -------------------------------------------- # 03/09/15 eranian@hpl.hp.co 1.1239.1.9 # [PATCH] ia64: minor perfmon2 patch # # This patch fixes a typo in pfm_write_pmcs() in the test for the default # value. The code was using the lop index instead of the register # index in the PMC_DFL_VAL() macro. This was causing valid values # for some PMCs to be rejected. # -------------------------------------------- # 03/09/17 davidm@tiger.hpl.hp.com 1.1239.1.10 # ia64: In , do not include outside # the #ifdef __KERNEL__ bracket. Doing so pollutes the user- # level namespace. Bug report & proposed fix by GOTO Masanori. # -------------------------------------------- # 03/09/18 davidm@tiger.hpl.hp.com 1.1239.1.11 # ia64: Control /proc/bus/mckinley/zx1 via separate SBA_PROC_FS macro and turn # SBA_PROC_FS off by default (it's too much of a scalability bottleneck). # -------------------------------------------- # 03/09/18 jes@wildopensource.com 1.1239.1.12 # [PATCH] ia64: small sn2 cleanup # # Attached is a small cleanup patch for the sn2 header files which removes # some cases of excessive header file inclusion. # -------------------------------------------- # 03/09/18 eranian@hpl.hp.com 1.1239.1.13 # [PATCH] ia64: pass si_isr for a few more signal sources # # This patch changes the kernel such that si_isr gets setup for hardware # breakpoints, single-step, and taken-branch traps. This is useful, e.g., to # determine what kind of hw breakpoint triggered the signal. # -------------------------------------------- # 03/09/18 jes@wildopensource.com 1.1239.1.14 # [PATCH] ia64: sn2 header file cleanup # # This patch removes a ton of pointless big endian defines for some # registers on SN2 and cleans up the #include hierachy making it include # some really big header files only when they are really needed. # -------------------------------------------- # 03/09/18 jes@wildopensource.com 1.1239.1.15 # [PATCH] ia64: include/asm-ia64/sn/router.h cleanup # # Minor cleanup. # -------------------------------------------- # 03/09/18 jes@wildopensource.com 1.1239.1.16 # [PATCH] ia64: fix for include/asm-ia64/acpi.h # # asm/acpi.h relies on struct pci_vector_struct which is defined in # asm/system.h. # -------------------------------------------- # 03/09/18 jbarnes@sgi.com 1.1243 # [PATCH] ia64: fix early printk for sn2 # # Quick fix for the early printk function name for sn2. Goes along with a # patch I'm about to send to Andrew. # -------------------------------------------- # 03/09/18 bjorn.helgaas@hp.com 1.1239.1.17 # [PATCH] ia64: trivial sba_iommu patch # # I'm aligning the 2.4 and 2.5 versions of arch/ia64/hp/common/sba_iommu.c # and found a couple nits in the 2.5 version. No functional change, just # whitespace, comment, and parameter name changes (and I made # one function static). # -------------------------------------------- # 03/09/18 davidm@tiger.hpl.hp.com 1.1244 # Merge tiger.hpl.hp.com:/data1/bk/lia64/to-linus-2.5 # into tiger.hpl.hp.com:/data1/bk/lia64/linux-ia64-2.5 # -------------------------------------------- # diff -Nru a/arch/ia64/Kconfig b/arch/ia64/Kconfig --- a/arch/ia64/Kconfig Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/Kconfig Fri Sep 19 00:39:54 2003 @@ -267,7 +267,7 @@ unsure, answer Y. config PM - bool + bool "Power Management support" depends on IA64_GENERIC || IA64_DIG || IA64_HP_ZX1 default y ---help--- @@ -413,6 +413,16 @@ To use this option, you have to ensure that the "/proc file system support" (CONFIG_PROC_FS) is enabled, too. +config IA64_SALINFO + tristate "/proc/sal support" + help + The /proc/sal directory exports the SAL (system abstraction layer) + feature bits, like whether the platform is subject to ITC drift. It + is intended to be used by user programs that care about such things. + + To use this option, you have to ensure that the "/proc file system + support" (CONFIG_PROC_FS) is enabled, too. + config EFI_VARS tristate "/proc/efi/vars support" help @@ -424,9 +434,15 @@ support" (CONFIG_PROC_FS) is enabled, too. config NR_CPUS - int "Maximum number of CPUs (2-64)" + int "Maximum number of CPUs" depends on SMP default "64" + help + You should set this to the number of CPUs in your system, but + keep in mind that a kernel compiled for, e.g., 2 CPUs will boot but + only use 2 CPUs on a >2 CPU system. Setting this to a value larger + than 64 will cause the use of a CPU mask array, causing a small + performance hit. source "fs/Kconfig.binfmt" @@ -569,6 +585,7 @@ source "arch/ia64/hp/sim/Kconfig" +source "arch/ia64/oprofile/Kconfig" menu "Kernel hacking" @@ -627,6 +644,33 @@ send a BREAK and then within 5 seconds a command keypress. The keys are documented in . Don't say Y unless you really know what this hack does. + +config IA64_EARLY_PRINTK + bool "Early printk support" + depends on DEBUG_KERNEL && !IA64_GENERIC + help + Selecting this option uses the VGA screen or serial console for + printk() output before the consoles are initialised. It is useful + for debugging problems early in the boot process, but only if you + have a suitable VGA/serial console attached. If you're unsure, + select N. + +config IA64_EARLY_PRINTK_UART + bool "Early printk on MMIO serial port" + depends on IA64_EARLY_PRINTK + +config IA64_EARLY_PRINTK_UART_BASE + hex "UART MMIO base address" + depends on IA64_EARLY_PRINTK_UART + default "ff5e0000" + +config IA64_EARLY_PRINTK_VGA + bool "Early printk on VGA" + depends on IA64_EARLY_PRINTK + +config IA64_EARLY_PRINTK_SGI_SN + bool "Early printk on SGI SN serial console" + depends on IA64_EARLY_PRINTK && (IA64_GENERIC || IA64_SGI_SN2) config DEBUG_SLAB bool "Debug memory allocations" diff -Nru a/arch/ia64/Makefile b/arch/ia64/Makefile --- a/arch/ia64/Makefile Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/Makefile Fri Sep 19 00:39:53 2003 @@ -65,6 +65,7 @@ drivers-$(CONFIG_IA64_HP_SIM) += arch/ia64/hp/sim/ drivers-$(CONFIG_IA64_HP_ZX1) += arch/ia64/hp/common/ arch/ia64/hp/zx1/ drivers-$(CONFIG_IA64_GENERIC) += arch/ia64/hp/common/ arch/ia64/hp/zx1/ arch/ia64/hp/sim/ +drivers-$(CONFIG_OPROFILE) += arch/ia64/oprofile/ boot := arch/ia64/hp/sim/boot diff -Nru a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c --- a/arch/ia64/hp/common/sba_iommu.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/hp/common/sba_iommu.c Fri Sep 19 00:39:53 2003 @@ -54,6 +54,11 @@ */ #define ALLOW_IOV_BYPASS +#ifdef CONFIG_PROC_FS + /* turn it off for now; without per-CPU counters, it's too much of a scalability bottleneck: */ +# define SBA_PROC_FS 0 +#endif + /* ** If a device prefetches beyond the end of a valid pdir entry, it will cause ** a hard failure, ie. MCA. Version 3.0 and later of the zx1 LBA should @@ -193,7 +198,7 @@ } saved[DELAYED_RESOURCE_CNT]; #endif -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS #define SBA_SEARCH_SAMPLE 0x100 unsigned long avg_search[SBA_SEARCH_SAMPLE]; unsigned long avg_idx; /* current index into avg_search */ @@ -227,12 +232,7 @@ static struct ioc *ioc_list; static int reserve_sba_gart = 1; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) #define sba_sg_address(sg) (page_address((sg)->page) + (sg)->offset) -#else -#define sba_sg_address(sg) ((sg)->address ? (sg)->address : \ - page_address((sg)->page) + (sg)->offset) -#endif #ifdef FULL_VALID_PDIR static u64 prefetch_spill_page; @@ -522,7 +522,7 @@ sba_alloc_range(struct ioc *ioc, size_t size) { unsigned int pages_needed = size >> IOVP_SHIFT; -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS unsigned long itc_start = ia64_get_itc(); #endif unsigned long pide; @@ -556,7 +556,7 @@ (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map), ioc->res_bitshift ); -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS { unsigned long itc_end = ia64_get_itc(); unsigned long tmp = itc_end - itc_start; @@ -598,7 +598,7 @@ __FUNCTION__, (uint) iova, size, bits_not_wanted, m, pide, res_ptr, *res_ptr); -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS ioc->used_pages -= bits_not_wanted; #endif @@ -790,7 +790,7 @@ ** Device is bit capable of DMA'ing to the buffer... ** just return the PCI address of ptr */ -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS spin_lock_irqsave(&ioc->res_lock, flags); ioc->msingle_bypass++; spin_unlock_irqrestore(&ioc->res_lock, flags); @@ -816,7 +816,7 @@ panic("Sanity check failed"); #endif -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS ioc->msingle_calls++; ioc->msingle_pages += size >> IOVP_SHIFT; #endif @@ -875,7 +875,7 @@ /* ** Address does not fall w/in IOVA, must be bypassing */ -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS spin_lock_irqsave(&ioc->res_lock, flags); ioc->usingle_bypass++; spin_unlock_irqrestore(&ioc->res_lock, flags); @@ -900,7 +900,7 @@ size = ROUNDUP(size, IOVP_SIZE); spin_lock_irqsave(&ioc->res_lock, flags); -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS ioc->usingle_calls++; ioc->usingle_pages += size >> IOVP_SHIFT; #endif @@ -962,20 +962,20 @@ /** - * sba_alloc_consistent - allocate/map shared mem for DMA - * @hwdev: instance of PCI owned by the driver that's asking. + * sba_alloc_coherent - allocate/map shared mem for DMA + * @dev: instance of PCI owned by the driver that's asking. * @size: number of bytes mapped in driver buffer. * @dma_handle: IOVA of new buffer. * * See Documentation/DMA-mapping.txt */ void * -sba_alloc_coherent (struct device *hwdev, size_t size, dma_addr_t *dma_handle, int flags) +sba_alloc_coherent (struct device *dev, size_t size, dma_addr_t *dma_handle, int flags) { struct ioc *ioc; void *addr; - addr = (void *) __get_free_pages(flags, get_order(size)); + addr = (void *) __get_free_pages(flags, get_order(size)); if (!addr) return NULL; @@ -983,7 +983,7 @@ * REVISIT: if sba_map_single starts needing more than dma_mask from the * device, this needs to be updated. */ - ioc = GET_IOC(hwdev); + ioc = GET_IOC(dev); ASSERT(ioc); *dma_handle = sba_map_single(&ioc->sac_only_dev->dev, addr, size, 0); @@ -993,17 +993,17 @@ /** - * sba_free_consistent - free/unmap shared mem for DMA - * @hwdev: instance of PCI owned by the driver that's asking. + * sba_free_coherent - free/unmap shared mem for DMA + * @dev: instance of PCI owned by the driver that's asking. * @size: number of bytes mapped in driver buffer. * @vaddr: virtual address IOVA of "consistent" buffer. * @dma_handler: IO virtual address of "consistent" buffer. * * See Documentation/DMA-mapping.txt */ -void sba_free_coherent (struct device *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle) +void sba_free_coherent (struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle) { - sba_unmap_single(hwdev, dma_handle, size, 0); + sba_unmap_single(dev, dma_handle, size, 0); free_pages((unsigned long) vaddr, get_order(size)); } @@ -1083,7 +1083,7 @@ cnt += dma_offset; dma_offset=0; /* only want offset on first chunk */ cnt = ROUNDUP(cnt, IOVP_SIZE); -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS ioc->msg_pages += cnt >> IOVP_SHIFT; #endif do { @@ -1273,7 +1273,7 @@ sg->dma_length = sg->length; sg->dma_address = virt_to_phys(sba_sg_address(sg)); } -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS spin_lock_irqsave(&ioc->res_lock, flags); ioc->msg_bypass++; spin_unlock_irqrestore(&ioc->res_lock, flags); @@ -1286,7 +1286,7 @@ sglist->dma_length = sglist->length; sglist->dma_address = sba_map_single(dev, sba_sg_address(sglist), sglist->length, dir); -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS /* ** Should probably do some stats counting, but trying to ** be precise quickly starts wasting CPU time. @@ -1305,7 +1305,7 @@ } #endif -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS ioc->msg_calls++; #endif @@ -1368,7 +1368,7 @@ ioc = GET_IOC(dev); ASSERT(ioc); -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS ioc->usg_calls++; #endif @@ -1381,7 +1381,7 @@ while (nents && sglist->dma_length) { sba_unmap_single(dev, sglist->dma_address, sglist->dma_length, dir); -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS /* ** This leaves inconsistent data in the stats, but we can't ** tell which sg lists were mapped by map_single and which @@ -1709,7 +1709,7 @@ ** **************************************************************************/ -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS static void * ioc_start(struct seq_file *s, loff_t *pos) { @@ -1763,7 +1763,7 @@ if (ioc->avg_search[i] > max) max = ioc->avg_search[i]; if (ioc->avg_search[i] < min) min = ioc->avg_search[i]; } - avg /= SBA_SEARCH_SAMPLE; + avg /= SBA_SEARCH_SAMPLE; seq_printf(s, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", min, avg, max); seq_printf(s, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n", @@ -1864,7 +1864,7 @@ } #endif -void +static void sba_connect_bus(struct pci_bus *bus) { acpi_handle handle, parent; @@ -1872,7 +1872,7 @@ struct ioc *ioc; if (!PCI_CONTROLLER(bus)) - panic(PFX "no sysdata on bus %d!\n",bus->number); + panic(PFX "no sysdata on bus %d!\n", bus->number); if (PCI_CONTROLLER(bus)->iommu) return; @@ -1955,7 +1955,7 @@ } #endif -#ifdef CONFIG_PROC_FS +#if SBA_PROC_FS ioc_proc_init(); #endif return 0; diff -Nru a/arch/ia64/hp/sim/boot/boot_head.S b/arch/ia64/hp/sim/boot/boot_head.S --- a/arch/ia64/hp/sim/boot/boot_head.S Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/hp/sim/boot/boot_head.S Fri Sep 19 00:39:53 2003 @@ -27,6 +27,14 @@ br.call.sptk.many rp=start_bootloader END(_start) +/* + * Set a break point on this function so that symbols are available to set breakpoints in + * the kernel being debugged. + */ +GLOBAL_ENTRY(debug_break) + br.ret.sptk.many b0 +END(debug_break) + GLOBAL_ENTRY(ssc) .regstk 5,0,0,0 mov r15=in4 diff -Nru a/arch/ia64/hp/sim/boot/bootloader.c b/arch/ia64/hp/sim/boot/bootloader.c --- a/arch/ia64/hp/sim/boot/bootloader.c Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/hp/sim/boot/bootloader.c Fri Sep 19 00:39:54 2003 @@ -37,15 +37,7 @@ extern void jmp_to_kernel (unsigned long bp, unsigned long e_entry); extern struct ia64_boot_param *sys_fw_init (const char *args, int arglen); - -/* - * Set a break point on this function so that symbols are available to set breakpoints in - * the kernel being debugged. - */ -static void -debug_break (void) -{ -} +extern void debug_break (void); static void cons_write (const char *buf) diff -Nru a/arch/ia64/ia32/elfcore32.h b/arch/ia64/ia32/elfcore32.h --- a/arch/ia64/ia32/elfcore32.h Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/ia32/elfcore32.h Fri Sep 19 00:39:53 2003 @@ -8,6 +8,8 @@ #ifndef _ELFCORE32_H_ #define _ELFCORE32_H_ +#include + #define USE_ELF_CORE_DUMP 1 /* Override elfcore.h */ @@ -79,8 +81,7 @@ pr_reg[11] = regs->r1; \ pr_reg[12] = regs->cr_iip; \ pr_reg[13] = regs->r17 & 0xffff; \ - asm volatile ("mov %0=ar.eflag ;;" \ - : "=r"(pr_reg[14])); \ + pr_reg[14] = ia64_getreg(_IA64_REG_AR_EFLAG); \ pr_reg[15] = regs->r12; \ pr_reg[16] = (regs->r17 >> 16) & 0xffff; diff -Nru a/arch/ia64/ia32/sys_ia32.c b/arch/ia64/ia32/sys_ia32.c --- a/arch/ia64/ia32/sys_ia32.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/ia32/sys_ia32.c Fri Sep 19 00:39:53 2003 @@ -76,6 +76,7 @@ #define OFFSET4K(a) ((a) & 0xfff) #define PAGE_START(addr) ((addr) & PAGE_MASK) +#define MINSIGSTKSZ_IA32 2048 #define high2lowuid(uid) ((uid) > 65535 ? 65534 : (uid)) #define high2lowgid(gid) ((gid) > 65535 ? 65534 : (gid)) @@ -2262,10 +2263,18 @@ return -EFAULT; uss.ss_sp = (void *) (long) buf32.ss_sp; uss.ss_flags = buf32.ss_flags; - uss.ss_size = buf32.ss_size; + /* MINSIGSTKSZ is different for ia32 vs ia64. We lie here to pass the + check and set it to the user requested value later */ + if (buf32.ss_size < MINSIGSTKSZ_IA32) { + ret = -ENOMEM; + goto out; + } + uss.ss_size = MINSIGSTKSZ; set_fs(KERNEL_DS); ret = do_sigaltstack(uss32 ? &uss : NULL, &uoss, pt->r12); + current->sas_ss_size = buf32.ss_size; set_fs(old_fs); +out: if (ret < 0) return(ret); if (uoss32) { diff -Nru a/arch/ia64/kernel/Makefile b/arch/ia64/kernel/Makefile --- a/arch/ia64/kernel/Makefile Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/kernel/Makefile Fri Sep 19 00:39:54 2003 @@ -14,6 +14,7 @@ obj-$(CONFIG_IA64_HP_ZX1) += acpi-ext.o obj-$(CONFIG_IA64_MCA) += mca.o mca_asm.o obj-$(CONFIG_IA64_PALINFO) += palinfo.o +obj-$(CONFIG_IA64_SALINFO) += salinfo.o obj-$(CONFIG_IOSAPIC) += iosapic.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_SMP) += smp.o smpboot.o diff -Nru a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c --- a/arch/ia64/kernel/acpi.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/kernel/acpi.c Fri Sep 19 00:39:53 2003 @@ -331,7 +331,7 @@ #ifdef CONFIG_ACPI_NUMA -#define SLIT_DEBUG +#undef SLIT_DEBUG #define PXM_FLAG_LEN ((MAX_PXM_DOMAINS + 1)/32) @@ -603,11 +603,13 @@ printk(KERN_ERR PREFIX "Can't find FADT\n"); #ifdef CONFIG_SMP - smp_boot_data.cpu_count = available_cpus; if (available_cpus == 0) { printk(KERN_INFO "ACPI: Found 0 CPUS; assuming 1\n"); + printk(KERN_INFO "CPU 0 (0x%04x)", hard_smp_processor_id()); + smp_boot_data.cpu_phys_id[available_cpus] = hard_smp_processor_id(); available_cpus = 1; /* We've got at least one of these, no? */ } + smp_boot_data.cpu_count = available_cpus; smp_build_cpu_map(); # ifdef CONFIG_NUMA diff -Nru a/arch/ia64/kernel/efi.c b/arch/ia64/kernel/efi.c --- a/arch/ia64/kernel/efi.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/kernel/efi.c Fri Sep 19 00:39:53 2003 @@ -324,7 +324,7 @@ check_md = q; if (check_md->attribute & EFI_MEMORY_WB) - trim_bottom(md, granule_addr); + trim_bottom(check_md, granule_addr); if (check_md->phys_addr < granule_addr) continue; @@ -446,10 +446,12 @@ panic("Woah! PAL code size bigger than a granule!"); mask = ~((1 << IA64_GRANULE_SHIFT) - 1); +#if EFI_DEBUG printk(KERN_INFO "CPU %d: mapping PAL code [0x%lx-0x%lx) into [0x%lx-0x%lx)\n", smp_processor_id(), md->phys_addr, md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT), vaddr & mask, (vaddr & mask) + IA64_GRANULE_SIZE); +#endif /* * Cannot write to CRx with PSR.ic=1 diff -Nru a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S --- a/arch/ia64/kernel/entry.S Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/kernel/entry.S Fri Sep 19 00:39:53 2003 @@ -1448,7 +1448,7 @@ data8 sys_sched_setaffinity data8 sys_sched_getaffinity data8 sys_set_tid_address - data8 sys_fadvise64 + data8 sys_fadvise64_64 data8 sys_tgkill // 1235 data8 sys_exit_group data8 sys_lookup_dcookie @@ -1473,7 +1473,7 @@ data8 sys_clock_nanosleep data8 sys_fstatfs64 data8 sys_statfs64 - data8 sys_fadvise64_64 + data8 ia64_ni_syscall data8 ia64_ni_syscall // 1260 data8 ia64_ni_syscall data8 ia64_ni_syscall diff -Nru a/arch/ia64/kernel/fsys.S b/arch/ia64/kernel/fsys.S --- a/arch/ia64/kernel/fsys.S Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/kernel/fsys.S Fri Sep 19 00:39:53 2003 @@ -655,7 +655,7 @@ data8 0 // sched_setaffinity data8 0 // sched_getaffinity data8 fsys_set_tid_address // set_tid_address - data8 0 // fadvise64 + data8 0 // fadvise64_64 data8 0 // tgkill // 1235 data8 0 // exit_group data8 0 // lookup_dcookie @@ -680,7 +680,7 @@ data8 0 // clock_nanosleep data8 0 // fstatfs64 data8 0 // statfs64 - data8 0 // fadvise64_64 + data8 0 data8 0 // 1260 data8 0 data8 0 diff -Nru a/arch/ia64/kernel/init_task.c b/arch/ia64/kernel/init_task.c --- a/arch/ia64/kernel/init_task.c Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/kernel/init_task.c Fri Sep 19 00:39:54 2003 @@ -28,15 +28,13 @@ */ #define init_thread_info init_task_mem.s.thread_info -static union { +union { struct { struct task_struct task; struct thread_info thread_info; } s; unsigned long stack[KERNEL_STACK_SIZE/sizeof (unsigned long)]; -} init_task_mem asm ("init_task_mem") __attribute__((section(".data.init_task"))) = {{ +} init_task_mem asm ("init_task") __attribute__((section(".data.init_task"))) = {{ .task = INIT_TASK(init_task_mem.s.task), .thread_info = INIT_THREAD_INFO(init_task_mem.s.task) }}; - -extern struct task_struct init_task __attribute__ ((alias("init_task_mem"))); diff -Nru a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c --- a/arch/ia64/kernel/mca.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/kernel/mca.c Fri Sep 19 00:39:53 2003 @@ -1193,7 +1193,7 @@ ia64_mca_cmc_poll (unsigned long dummy) { /* Trigger a CMC interrupt cascade */ - platform_send_ipi(__ffs(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0); + platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0); } /* @@ -1260,7 +1260,7 @@ ia64_mca_cpe_poll (unsigned long dummy) { /* Trigger a CPE interrupt cascade */ - platform_send_ipi(__ffs(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0); + platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0); } /* diff -Nru a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c --- a/arch/ia64/kernel/perfmon.c Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/kernel/perfmon.c Fri Sep 19 00:39:54 2003 @@ -58,23 +58,8 @@ #define PFM_CTX_ZOMBIE 4 /* owner of the context is closing it */ #define PFM_CTX_TERMINATED 5 /* the task the context was loaded onto is gone */ -#define CTX_LOADED(c) (c)->ctx_state = PFM_CTX_LOADED -#define CTX_UNLOADED(c) (c)->ctx_state = PFM_CTX_UNLOADED -#define CTX_ZOMBIE(c) (c)->ctx_state = PFM_CTX_ZOMBIE -#define CTX_DESTROYED(c) (c)->ctx_state = PFM_CTX_DESTROYED -#define CTX_MASKED(c) (c)->ctx_state = PFM_CTX_MASKED -#define CTX_TERMINATED(c) (c)->ctx_state = PFM_CTX_TERMINATED - -#define CTX_IS_UNLOADED(c) ((c)->ctx_state == PFM_CTX_UNLOADED) -#define CTX_IS_LOADED(c) ((c)->ctx_state == PFM_CTX_LOADED) -#define CTX_IS_ZOMBIE(c) ((c)->ctx_state == PFM_CTX_ZOMBIE) -#define CTX_IS_MASKED(c) ((c)->ctx_state == PFM_CTX_MASKED) -#define CTX_IS_TERMINATED(c) ((c)->ctx_state == PFM_CTX_TERMINATED) -#define CTX_IS_DEAD(c) ((c)->ctx_state == PFM_CTX_TERMINATED || (c)->ctx_state == PFM_CTX_ZOMBIE) - #define PFM_INVALID_ACTIVATION (~0UL) - /* * depth of message queue */ @@ -649,6 +634,7 @@ DEFINE_PER_CPU(pfm_context_t *, pmu_ctx); DEFINE_PER_CPU(unsigned long, pmu_activation_number); + /* forward declaration */ static struct file_operations pfm_file_ops; @@ -659,7 +645,13 @@ static void pfm_lazy_save_regs (struct task_struct *ta); #endif -#if defined(CONFIG_ITANIUM) +/* + * the HP simulator must be first because + * CONFIG_IA64_HP_SIM is independent of CONFIG_MCKINLEY or CONFIG_ITANIUM + */ +#if defined(CONFIG_IA64_HP_SIM) +#include "perfmon_hpsim.h" +#elif defined(CONFIG_ITANIUM) #include "perfmon_itanium.h" #elif defined(CONFIG_MCKINLEY) #include "perfmon_mckinley.h" @@ -953,13 +945,15 @@ struct thread_struct *th = &task->thread; unsigned long mask; unsigned long psr, val; - int i; + int i, is_system; + + is_system = ctx->ctx_fl_system; if (task != current) { printk(KERN_ERR "perfmon.%d: invalid task[%d] current[%d]\n", __LINE__, task->pid, current->pid); return; } - if (CTX_IS_MASKED(ctx) == 0) { + if (ctx->ctx_state != PFM_CTX_MASKED) { printk(KERN_ERR "perfmon.%d: task[%d] current[%d] invalid state=%d\n", __LINE__, task->pid, current->pid, ctx->ctx_state); return; @@ -975,7 +969,7 @@ * * system-wide session are pinned and self-monitoring */ - if (ctx->ctx_fl_system && (PFM_CPUINFO_GET() & PFM_CPUINFO_DCR_PP)) { + if (is_system && (PFM_CPUINFO_GET() & PFM_CPUINFO_DCR_PP)) { /* disable dcr pp */ ia64_setreg(_IA64_REG_CR_DCR, ia64_getreg(_IA64_REG_CR_DCR) & ~IA64_DCR_PP); pfm_clear_psr_pp(); @@ -1022,7 +1016,7 @@ /* * now restore PSR */ - if (ctx->ctx_fl_system && (PFM_CPUINFO_GET() & PFM_CPUINFO_DCR_PP)) { + if (is_system && (PFM_CPUINFO_GET() & PFM_CPUINFO_DCR_PP)) { /* enable dcr pp */ ia64_setreg(_IA64_REG_CR_DCR, ia64_getreg(_IA64_REG_CR_DCR) | IA64_DCR_PP); ia64_srlz_i(); @@ -1825,6 +1819,7 @@ void *smpl_buf_vaddr = NULL; void *smpl_buf_addr = NULL; int free_possible = 1; + int state, is_system; { u64 psr = pfm_get_psr(); BUG_ON((psr & IA64_PSR_I) == 0UL); @@ -1850,6 +1845,11 @@ PROTECT_CTX(ctx, flags); + state = ctx->ctx_state; + is_system = ctx->ctx_fl_system; + + task = PFM_CTX_TASK(ctx); + /* * remove our file from the async queue, if we use it */ @@ -1859,11 +1859,10 @@ DPRINT(("[%d] after async_queue=%p\n", current->pid, ctx->ctx_async_queue)); } - task = PFM_CTX_TASK(ctx); - DPRINT(("[%d] ctx_state=%d\n", current->pid, ctx->ctx_state)); + DPRINT(("[%d] ctx_state=%d\n", current->pid, state)); - if (CTX_IS_UNLOADED(ctx) || CTX_IS_TERMINATED(ctx)) { + if (state == PFM_CTX_UNLOADED || state == PFM_CTX_TERMINATED) { goto doit; } @@ -1884,7 +1883,7 @@ * * We need to release the resource on the ORIGINAL cpu. */ - if (ctx->ctx_fl_system && ctx->ctx_cpu != smp_processor_id()) { + if (is_system && ctx->ctx_cpu != smp_processor_id()) { DPRINT(("[%d] should be running on CPU%d\n", current->pid, ctx->ctx_cpu)); @@ -1900,9 +1899,10 @@ task->thread.pfm_context = NULL; ctx->ctx_task = NULL; - CTX_UNLOADED(ctx); + ctx->ctx_state = state = PFM_CTX_UNLOADED; pfm_unreserve_session(ctx, 1 , ctx->ctx_cpu); + } else #endif /* CONFIG_SMP */ { @@ -1914,19 +1914,20 @@ */ pfm_context_unload(ctx, NULL, 0, regs); - CTX_TERMINATED(ctx); + ctx->ctx_state = PFM_CTX_TERMINATED; - DPRINT(("[%d] ctx_state=%d\n", current->pid, ctx->ctx_state)); + DPRINT(("[%d] ctx_state=%d\n", current->pid, state)); } goto doit; } + /* * The task is currently blocked or will block after an overflow. * we must force it to wakeup to get out of the * MASKED state and transition to the unloaded state by itself */ - if (CTX_IS_MASKED(ctx) && CTX_OVFL_NOBLOCK(ctx) == 0) { + if (state == PFM_CTX_MASKED && CTX_OVFL_NOBLOCK(ctx) == 0) { /* * set a "partial" zombie state to be checked @@ -1949,7 +1950,7 @@ */ up(&ctx->ctx_restart_sem); - DPRINT(("waking up ctx_state=%d for [%d]\n", ctx->ctx_state, current->pid)); + DPRINT(("waking up ctx_state=%d for [%d]\n", state, current->pid)); /* * put ourself to sleep waiting for the other @@ -1971,24 +1972,24 @@ */ schedule(); - DPRINT(("woken up ctx_state=%d for [%d]\n", ctx->ctx_state, current->pid)); PROTECT_CTX(ctx, flags); + remove_wait_queue(&ctx->ctx_zombieq, &wait); set_current_state(TASK_RUNNING); /* * context is terminated at this point */ - DPRINT(("after zombie wakeup ctx_state=%d for [%d]\n", ctx->ctx_state, current->pid)); + DPRINT(("after zombie wakeup ctx_state=%d for [%d]\n", state, current->pid)); } else { #ifdef CONFIG_SMP /* * switch context to zombie state */ - CTX_ZOMBIE(ctx); + ctx->ctx_state = PFM_CTX_ZOMBIE; DPRINT(("zombie ctx for [%d]\n", task->pid)); /* @@ -2002,6 +2003,10 @@ } doit: /* cannot assume task is defined from now on */ + + /* reload state, may have changed during opening of critical section */ + state = ctx->ctx_state; + /* * the context is still attached to a task (possibly current) * we cannot destroy it right now @@ -2032,10 +2037,9 @@ ctx->ctx_smpl_hdr = NULL; } - DPRINT(("[%d] ctx_state=%d free_possible=%d vaddr=%p addr=%p size=%lu\n", current->pid, - ctx->ctx_state, + state, free_possible, smpl_buf_vaddr, smpl_buf_addr, @@ -2047,7 +2051,7 @@ * UNLOADED and TERMINATED mean that the session has already been * unreserved. */ - if (CTX_IS_ZOMBIE(ctx)) { + if (state == PFM_CTX_ZOMBIE) { pfm_unreserve_session(ctx, ctx->ctx_fl_system , ctx->ctx_cpu); } @@ -2360,10 +2364,23 @@ static int pfm_bad_permissions(struct task_struct *task) { - /* stolen from bad_signal() */ - return (current->session != task->session) - && (current->euid ^ task->suid) && (current->euid ^ task->uid) - && (current->uid ^ task->suid) && (current->uid ^ task->uid); + /* inspired by ptrace_attach() */ + DPRINT(("[%d] cur: uid=%d gid=%d task: euid=%d suid=%d uid=%d egid=%d sgid=%d\n", + current->pid, + current->uid, + current->gid, + task->euid, + task->suid, + task->uid, + task->egid, + task->sgid)); + + return ((current->uid != task->euid) + || (current->uid != task->suid) + || (current->uid != task->uid) + || (current->gid != task->egid) + || (current->gid != task->sgid) + || (current->gid != task->gid)) && !capable(CAP_SYS_PTRACE); } static int @@ -2655,7 +2672,7 @@ /* * context is unloaded */ - CTX_UNLOADED(ctx); + ctx->ctx_state = PFM_CTX_UNLOADED; /* * initialization of context's flags @@ -2787,7 +2804,7 @@ if (flag == PFM_PMD_NO_RESET) return; - if (CTX_IS_MASKED(ctx)) { + if (ctx->ctx_state == PFM_CTX_MASKED) { pfm_reset_regs_masked(ctx, ovfl_regs, flag); return; } @@ -2836,27 +2853,30 @@ unsigned long value; unsigned long smpl_pmds, reset_pmds; unsigned int cnum, reg_flags, flags; - int i, can_access_pmu = 0, is_loaded; - int is_monitor, is_counting; + int i, can_access_pmu = 0, is_loaded, is_system; + int is_monitor, is_counting, state; int ret = -EINVAL; #define PFM_CHECK_PMC_PM(x, y, z) ((x)->ctx_fl_system ^ PMC_PM(y, z)) - if (CTX_IS_DEAD(ctx)) return -EINVAL; + state = ctx->ctx_state; + is_loaded = state == PFM_CTX_LOADED ? 1 : 0; + is_system = ctx->ctx_fl_system; + + if (state == PFM_CTX_TERMINATED || state == PFM_CTX_ZOMBIE) return -EINVAL; - is_loaded = CTX_IS_LOADED(ctx); if (is_loaded) { thread = &ctx->ctx_task->thread; - can_access_pmu = GET_PMU_OWNER() == ctx->ctx_task ? 1 : 0; /* * In system wide and when the context is loaded, access can only happen * when the caller is running on the CPU being monitored by the session. * It does not have to be the owner (ctx_task) of the context per se. */ - if (ctx->ctx_fl_system && ctx->ctx_cpu != smp_processor_id()) { + if (is_system && ctx->ctx_cpu != smp_processor_id()) { DPRINT(("[%d] should be running on CPU%d\n", current->pid, ctx->ctx_cpu)); return -EBUSY; } + can_access_pmu = GET_PMU_OWNER() == ctx->ctx_task || is_system ? 1 : 0; } for (i = 0; i < count; i++, req++) { @@ -2885,7 +2905,7 @@ * - system-wide session: PMCx.pm=1 (privileged monitor) * - per-task : PMCx.pm=0 (user monitor) */ - if ((is_monitor || is_counting) && value != PMC_DFL_VAL(i) && PFM_CHECK_PMC_PM(ctx, cnum, value)) { + if ((is_monitor || is_counting) && value != PMC_DFL_VAL(cnum) && PFM_CHECK_PMC_PM(ctx, cnum, value)) { DPRINT(("pmc%u pmc_pm=%ld fl_system=%d\n", cnum, PMC_PM(cnum, value), @@ -2893,7 +2913,6 @@ goto error; } - if (is_counting) { pfm_monitor_t *p = (pfm_monitor_t *)&value; /* @@ -2975,7 +2994,7 @@ * make sure we do not try to reset on * restart because we have established new values */ - if (CTX_IS_MASKED(ctx)) ctx->ctx_ovfl_regs[0] &= ~1UL << cnum; + if (state == PFM_CTX_MASKED) ctx->ctx_ovfl_regs[0] &= ~1UL << cnum; } /* * Needed in case the user does not initialize the equivalent @@ -3007,7 +3026,7 @@ /* * write thread state */ - if (ctx->ctx_fl_system == 0) thread->pmcs[cnum] = value; + if (is_system == 0) thread->pmcs[cnum] = value; /* * write hardware register if we can @@ -3067,13 +3086,16 @@ pfarg_reg_t *req = (pfarg_reg_t *)arg; unsigned long value, hw_value; unsigned int cnum; - int i, can_access_pmu = 0; - int is_counting, is_loaded; + int i, can_access_pmu = 0, state; + int is_counting, is_loaded, is_system; int ret = -EINVAL; - if (CTX_IS_DEAD(ctx)) return -EINVAL; - is_loaded = CTX_IS_LOADED(ctx); + state = ctx->ctx_state; + is_loaded = state == PFM_CTX_LOADED ? 1 : 0; + is_system = ctx->ctx_fl_system; + + if (state == PFM_CTX_TERMINATED || state == PFM_CTX_ZOMBIE) return -EINVAL; /* * on both UP and SMP, we can only write to the PMC when the task is @@ -3081,16 +3103,16 @@ */ if (is_loaded) { thread = &ctx->ctx_task->thread; - can_access_pmu = GET_PMU_OWNER() == ctx->ctx_task ? 1 : 0; /* * In system wide and when the context is loaded, access can only happen * when the caller is running on the CPU being monitored by the session. * It does not have to be the owner (ctx_task) of the context per se. */ - if (ctx->ctx_fl_system && ctx->ctx_cpu != smp_processor_id()) { + if (is_system && ctx->ctx_cpu != smp_processor_id()) { DPRINT(("[%d] should be running on CPU%d\n", current->pid, ctx->ctx_cpu)); return -EBUSY; } + can_access_pmu = GET_PMU_OWNER() == ctx->ctx_task || is_system ? 1 : 0; } for (i = 0; i < count; i++, req++) { @@ -3179,7 +3201,7 @@ * make sure we do not try to reset on * restart because we have established new values */ - if (is_counting && CTX_IS_MASKED(ctx)) { + if (is_counting && state == PFM_CTX_MASKED) { ctx->ctx_ovfl_regs[0] &= ~1UL << cnum; } @@ -3187,7 +3209,7 @@ /* * write thread state */ - if (ctx->ctx_fl_system == 0) thread->pmds[cnum] = hw_value; + if (is_system == 0) thread->pmds[cnum] = hw_value; /* * write hardware register if we can @@ -3265,35 +3287,40 @@ unsigned long val = 0UL, lval ; pfarg_reg_t *req = (pfarg_reg_t *)arg; unsigned int cnum, reg_flags = 0; - int i, is_loaded, can_access_pmu = 0; + int i, can_access_pmu = 0, state; + int is_loaded, is_system; int ret = -EINVAL; - if (CTX_IS_ZOMBIE(ctx)) return -EINVAL; - /* * access is possible when loaded only for * self-monitoring tasks or in UP mode */ - is_loaded = CTX_IS_LOADED(ctx); + + state = ctx->ctx_state; + is_loaded = state == PFM_CTX_LOADED ? 1 : 0; + is_system = ctx->ctx_fl_system; + + if (state == PFM_CTX_ZOMBIE) return -EINVAL; if (is_loaded) { thread = &ctx->ctx_task->thread; /* - * this can be true when not self-monitoring only in UP - */ - can_access_pmu = GET_PMU_OWNER() == ctx->ctx_task? 1 : 0; - - if (can_access_pmu) ia64_srlz_d(); - /* * In system wide and when the context is loaded, access can only happen * when the caller is running on the CPU being monitored by the session. * It does not have to be the owner (ctx_task) of the context per se. */ - if (ctx->ctx_fl_system && ctx->ctx_cpu != smp_processor_id()) { + if (is_system && ctx->ctx_cpu != smp_processor_id()) { DPRINT(("[%d] should be running on CPU%d\n", current->pid, ctx->ctx_cpu)); return -EBUSY; } + /* + * this can be true when not self-monitoring only in UP + */ + can_access_pmu = GET_PMU_OWNER() == ctx->ctx_task || is_system ? 1 : 0; + + if (can_access_pmu) ia64_srlz_d(); } + DPRINT(("enter loaded=%d access_pmu=%d ctx_state=%d\n", is_loaded, can_access_pmu, @@ -3334,7 +3361,7 @@ * if context is zombie, then task does not exist anymore. * In this case, we use the full value saved in the context (pfm_flush_regs()). */ - val = CTX_IS_LOADED(ctx) ? thread->pmds[cnum] : 0UL; + val = state == PFM_CTX_LOADED ? thread->pmds[cnum] : 0UL; } if (PMD_IS_COUNTING(cnum)) { @@ -3628,7 +3655,7 @@ if (rst_ctrl.bits.mask_monitoring == 0) { DPRINT(("resuming monitoring for [%d]\n", task->pid)); - if (CTX_IS_MASKED(ctx)) pfm_restore_monitoring(task); + if (state == PFM_CTX_MASKED) pfm_restore_monitoring(task); } else { DPRINT(("keeping monitoring stopped for [%d]\n", task->pid)); @@ -3643,7 +3670,7 @@ /* * back to LOADED state */ - CTX_LOADED(ctx); + ctx->ctx_state = PFM_CTX_LOADED; return 0; } @@ -3706,30 +3733,34 @@ dbreg_t dbreg; unsigned int rnum; int first_time; - int ret = 0; - int i, can_access_pmu = 0, is_loaded; + int ret = 0, state; + int i, can_access_pmu = 0; + int is_system, is_loaded; if (pmu_conf.use_rr_dbregs == 0) return -EINVAL; - if (CTX_IS_DEAD(ctx)) return -EINVAL; + state = ctx->ctx_state; + is_loaded = state == PFM_CTX_LOADED ? 1 : 0; + is_system = ctx->ctx_fl_system; + + if (state == PFM_CTX_TERMINATED || state == PFM_CTX_ZOMBIE) return -EINVAL; - is_loaded = CTX_IS_LOADED(ctx); /* * on both UP and SMP, we can only write to the PMC when the task is * the owner of the local PMU. */ if (is_loaded) { thread = &ctx->ctx_task->thread; - can_access_pmu = GET_PMU_OWNER() == ctx->ctx_task ? 1 : 0; /* * In system wide and when the context is loaded, access can only happen * when the caller is running on the CPU being monitored by the session. * It does not have to be the owner (ctx_task) of the context per se. */ - if (ctx->ctx_fl_system && ctx->ctx_cpu != smp_processor_id()) { + if (is_system && ctx->ctx_cpu != smp_processor_id()) { DPRINT(("[%d] should be running on CPU%d\n", current->pid, ctx->ctx_cpu)); return -EBUSY; } + can_access_pmu = GET_PMU_OWNER() == ctx->ctx_task || is_system ? 1 : 0; } /* @@ -3758,7 +3789,7 @@ */ LOCK_PFS(); - if (first_time && ctx->ctx_fl_system) { + if (first_time && is_system) { if (pfm_sessions.pfs_ptrace_use_dbregs) ret = -EBUSY; else @@ -3906,16 +3937,19 @@ { struct pt_regs *tregs; struct task_struct *task = PFM_CTX_TASK(ctx); + int state, is_system; + state = ctx->ctx_state; + is_system = ctx->ctx_fl_system; - if (CTX_IS_LOADED(ctx) == 0 && CTX_IS_MASKED(ctx) == 0) return -EINVAL; + if (state != PFM_CTX_LOADED && state != PFM_CTX_MASKED) return -EINVAL; /* * In system wide and when the context is loaded, access can only happen * when the caller is running on the CPU being monitored by the session. * It does not have to be the owner (ctx_task) of the context per se. */ - if (ctx->ctx_fl_system && ctx->ctx_cpu != smp_processor_id()) { + if (is_system && ctx->ctx_cpu != smp_processor_id()) { DPRINT(("[%d] should be running on CPU%d\n", current->pid, ctx->ctx_cpu)); return -EBUSY; } @@ -3925,7 +3959,7 @@ * and the user level state of the caller, which may not * necessarily be the creator of the context. */ - if (ctx->ctx_fl_system) { + if (is_system) { /* * Update local PMU first * @@ -3985,15 +4019,19 @@ pfm_start(pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs) { struct pt_regs *tregs; + int state, is_system; + + state = ctx->ctx_state; + is_system = ctx->ctx_fl_system; - if (CTX_IS_LOADED(ctx) == 0) return -EINVAL; + if (state != PFM_CTX_LOADED) return -EINVAL; /* * In system wide and when the context is loaded, access can only happen * when the caller is running on the CPU being monitored by the session. * It does not have to be the owner (ctx_task) of the context per se. */ - if (ctx->ctx_fl_system && ctx->ctx_cpu != smp_processor_id()) { + if (is_system && ctx->ctx_cpu != smp_processor_id()) { DPRINT(("[%d] should be running on CPU%d\n", current->pid, ctx->ctx_cpu)); return -EBUSY; } @@ -4003,7 +4041,7 @@ * and the user level state of the caller, which may not * necessarily be the creator of the context. */ - if (ctx->ctx_fl_system) { + if (is_system) { /* * set user level psr.pp for the caller @@ -4055,7 +4093,6 @@ */ ia64_psr(tregs)->up = 1; } - return 0; } @@ -4121,11 +4158,14 @@ unsigned long *pmcs_source, *pmds_source; int the_cpu; int ret = 0; + int state, is_system; + state = ctx->ctx_state; + is_system = ctx->ctx_fl_system; /* * can only load from unloaded or terminated state */ - if (CTX_IS_UNLOADED(ctx) == 0 && CTX_IS_TERMINATED(ctx) == 0) { + if (state != PFM_CTX_UNLOADED && state != PFM_CTX_TERMINATED) { DPRINT(("[%d] cannot load to [%d], invalid ctx_state=%d\n", current->pid, req->load_pid, @@ -4151,7 +4191,7 @@ /* * system wide is self monitoring only */ - if (ctx->ctx_fl_system && task != current) { + if (is_system && task != current) { DPRINT(("system wide is self monitoring only current=%d load_pid=%d\n", current->pid, req->load_pid)); @@ -4191,7 +4231,7 @@ /* * now reserve the session */ - ret = pfm_reserve_session(current, ctx->ctx_fl_system, the_cpu); + ret = pfm_reserve_session(current, is_system, the_cpu); if (ret) goto error; ret = -EBUSY; @@ -4216,15 +4256,14 @@ pfm_reset_msgq(ctx); - CTX_LOADED(ctx); + ctx->ctx_state = PFM_CTX_LOADED; /* * link context to task */ ctx->ctx_task = task; - if (ctx->ctx_fl_system) { - + if (is_system) { /* * we load as stopped */ @@ -4250,7 +4289,7 @@ */ if (task == current) { - if (ctx->ctx_fl_system == 0) { + if (is_system == 0) { /* allow user level control */ ia64_psr(regs)->sp = 0; @@ -4318,14 +4357,14 @@ /* * release task, there is now a link with the context */ - if (ctx->ctx_fl_system == 0 && task != current) { + if (is_system == 0 && task != current) { pfm_put_task(task); if (ret == 0) { ret = pfm_check_task_exist(ctx); if (ret) { - CTX_UNLOADED(ctx); - ctx->ctx_task = NULL; + ctx->ctx_state = PFM_CTX_UNLOADED; + ctx->ctx_task = NULL; } } } @@ -4347,40 +4386,34 @@ { struct task_struct *task = PFM_CTX_TASK(ctx); struct pt_regs *tregs; + int state, is_system; DPRINT(("ctx_state=%d task [%d]\n", ctx->ctx_state, task ? task->pid : -1)); + state = ctx->ctx_state; + is_system = ctx->ctx_fl_system; + /* * unload only when necessary */ - if (CTX_IS_TERMINATED(ctx) || CTX_IS_UNLOADED(ctx)) { + if (state == PFM_CTX_TERMINATED || state == PFM_CTX_UNLOADED) { DPRINT(("[%d] ctx_state=%d, nothing to do\n", current->pid, ctx->ctx_state)); return 0; } /* - * In system wide and when the context is loaded, access can only happen - * when the caller is running on the CPU being monitored by the session. - * It does not have to be the owner (ctx_task) of the context per se. - */ - if (ctx->ctx_fl_system && ctx->ctx_cpu != smp_processor_id()) { - DPRINT(("[%d] should be running on CPU%d\n", current->pid, ctx->ctx_cpu)); - return -EBUSY; - } - - /* * clear psr and dcr bits */ pfm_stop(ctx, NULL, 0, regs); - CTX_UNLOADED(ctx); + ctx->ctx_state = state = PFM_CTX_UNLOADED; /* * in system mode, we need to update the PMU directly * and the user level state of the caller, which may not * necessarily be the creator of the context. */ - if (ctx->ctx_fl_system) { + if (is_system) { /* * Update cpuinfo @@ -4524,7 +4557,7 @@ if (ret) { printk(KERN_ERR "perfmon: pfm_exit_thread [%d] state=%d unload failed %d\n", task->pid, ctx->ctx_state, ret); } - CTX_TERMINATED(ctx); + ctx->ctx_state = PFM_CTX_TERMINATED; DPRINT(("ctx terminated by [%d]\n", task->pid)); pfm_end_notify_user(ctx); @@ -4606,16 +4639,19 @@ pfm_check_task_state(pfm_context_t *ctx, int cmd, unsigned long flags) { struct task_struct *task; + int state; + + state = ctx->ctx_state; task = PFM_CTX_TASK(ctx); if (task == NULL) { - DPRINT(("context %d no task, state=%d\n", ctx->ctx_fd, ctx->ctx_state)); + DPRINT(("context %d no task, state=%d\n", ctx->ctx_fd, state)); return 0; } DPRINT(("context %d state=%d [%d] task_state=%ld must_stop=%d\n", ctx->ctx_fd, - ctx->ctx_state, + state, task->pid, task->state, PFM_CMD_STOPPED(cmd))); @@ -4631,9 +4667,9 @@ /* * context is UNLOADED, MASKED, TERMINATED we are safe to go */ - if (CTX_IS_LOADED(ctx) == 0) return 0; + if (state != PFM_CTX_LOADED == 0) return 0; - if (CTX_IS_ZOMBIE(ctx)) return -EINVAL; + if (state == PFM_CTX_ZOMBIE) return -EINVAL; /* * context is loaded, we must make sure the task is stopped @@ -4653,6 +4689,7 @@ pfm_wait_task_inactive(task); PROTECT_CTX(ctx, flags); + return 0; } @@ -4830,12 +4867,12 @@ } if (rst_ctrl.bits.mask_monitoring == 0) { DPRINT(("resuming monitoring\n")); - if (CTX_IS_MASKED(ctx)) pfm_restore_monitoring(current); + if (ctx->ctx_state == PFM_CTX_MASKED) pfm_restore_monitoring(current); } else { DPRINT(("stopping monitoring\n")); //pfm_stop_monitoring(current, regs); } - CTX_LOADED(ctx); + ctx->ctx_state = PFM_CTX_LOADED; } } @@ -4869,7 +4906,7 @@ /* * switch to terminated state */ - CTX_TERMINATED(ctx); + ctx->ctx_state = PFM_CTX_TERMINATED; DPRINT(("context <%d> terminated for [%d]\n", ctx->ctx_fd, current->pid)); @@ -4922,7 +4959,7 @@ /* * must be done before we check non-blocking mode */ - if (ctx->ctx_fl_going_zombie || CTX_IS_ZOMBIE(ctx)) goto do_zombie; + if (ctx->ctx_fl_going_zombie || ctx->ctx_state == PFM_CTX_ZOMBIE) goto do_zombie; ovfl_regs = ctx->ctx_ovfl_regs[0]; @@ -4966,7 +5003,7 @@ static int pfm_notify_user(pfm_context_t *ctx, pfm_msg_t *msg) { - if (CTX_IS_ZOMBIE(ctx)) { + if (ctx->ctx_state == PFM_CTX_ZOMBIE) { DPRINT(("ignoring overflow notification, owner is zombie\n")); return 0; } @@ -5049,13 +5086,13 @@ pfm_ovfl_arg_t ovfl_arg; unsigned long mask; unsigned long old_val; - unsigned long ovfl_notify = 0UL, ovfl_pmds = 0UL; + unsigned long ovfl_notify = 0UL, ovfl_pmds = 0UL, smpl_pmds = 0UL; unsigned long tstamp; pfm_ovfl_ctrl_t ovfl_ctrl; unsigned int i, has_smpl; int must_notify = 0; - if (unlikely(CTX_IS_ZOMBIE(ctx))) goto stop_monitoring; + if (unlikely(ctx->ctx_state == PFM_CTX_ZOMBIE)) goto stop_monitoring; /* * sanity test. Should never happen @@ -5106,10 +5143,9 @@ if (PMC_OVFL_NOTIFY(ctx, i)) ovfl_notify |= 1UL << i; } - DPRINT_ovfl(("ctx_pmd[%d].val=0x%lx old_val=0x%lx pmd=0x%lx ovfl_pmds=0x%lx " - "ovfl_notify=0x%lx\n", - i, ctx->ctx_pmds[i].val, old_val, - ia64_get_pmd(i) & pmu_conf.ovfl_val, ovfl_pmds, ovfl_notify)); + DPRINT_ovfl(("ctx_pmd[%d].val=0x%lx old_val=0x%lx pmd=0x%lx ovfl_pmds=0x%lx ovfl_notify=0x%lx smpl_pmds=0x%lx\n", + i, ctx->ctx_pmds[i].val, old_val, + ia64_get_pmd(i) & pmu_conf.ovfl_val, ovfl_pmds, ovfl_notify, smpl_pmds)); } /* @@ -5128,7 +5164,7 @@ */ if (has_smpl) { unsigned long start_cycles, end_cycles; - unsigned long pmd_mask, smpl_pmds; + unsigned long pmd_mask; int j, k, ret = 0; int this_cpu = smp_processor_id(); @@ -5257,7 +5293,7 @@ */ if (ovfl_ctrl.bits.mask_monitoring) { pfm_mask_monitoring(task); - CTX_MASKED(ctx); + ctx->ctx_state = PFM_CTX_MASKED; } /* @@ -5553,19 +5589,18 @@ pfm_set_psr_pp(); ia64_srlz_i(); } - { unsigned long val; - val = ia64_get_pmc(4); - if ((val & (1UL<<23)) == 0UL) printk("perfmon: PMU off: pmc4=0x%lx\n", val); - } } void pfm_syst_wide_update_task(struct task_struct *task, unsigned long info, int is_ctxswin) { unsigned long start, end; + pfm_stats[smp_processor_id()].pfm_sysupdt_count++; start = ia64_get_itc(); + pfm_do_syst_wide_update_task(task, info, is_ctxswin); + end = ia64_get_itc(); pfm_stats[smp_processor_id()].pfm_sysupdt_cycles += end-start; } @@ -5591,7 +5626,7 @@ */ flags = pfm_protect_ctx_ctxsw(ctx); - if (CTX_IS_ZOMBIE(ctx)) { + if (ctx->ctx_state == PFM_CTX_ZOMBIE) { struct pt_regs *regs = ia64_task_regs(task); pfm_clear_psr_up(); @@ -5840,7 +5875,7 @@ BUG_ON(psr & IA64_PSR_I); #endif - if (unlikely(CTX_IS_ZOMBIE(ctx))) { + if (unlikely(ctx->ctx_state == PFM_CTX_ZOMBIE)) { struct pt_regs *regs = ia64_task_regs(task); BUG_ON(ctx->ctx_smpl_hdr); diff -Nru a/arch/ia64/kernel/perfmon_hpsim.h b/arch/ia64/kernel/perfmon_hpsim.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/ia64/kernel/perfmon_hpsim.h Fri Sep 19 00:39:54 2003 @@ -0,0 +1,75 @@ +/* + * This file contains the HP SKI Simulator PMU register description tables + * and pmc checkers used by perfmon.c. + * + * Copyright (C) 2002-2003 Hewlett Packard Co + * Stephane Eranian + * + * File mostly contributed by Ian Wienand + * + * This file is included as a dummy template so the kernel does not + * try to initalize registers the simulator can't handle. + * + * Note the simulator does not (currently) implement these registers, i.e., + * they do not count anything. But you can read/write them. + */ + +#define RDEP(x) (1UL<<(x)) + +#ifndef CONFIG_IA64_HP_SIM +#error "This file should only be included for the HP Simulator" +#endif + +static pfm_reg_desc_t pfm_hpsim_pmc_desc[PMU_MAX_PMCS]={ +/* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL, 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL, 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL, 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL, 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc4 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(4), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc5 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(5), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc6 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(6), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc7 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(7), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc8 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc9 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(9), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc10 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(10), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc11 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(11), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc12 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(12), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc13 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(13), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc14 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(14), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmc15 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(15), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, + { PFM_REG_END , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */ +}; + +static pfm_reg_desc_t pfm_hpsim_pmd_desc[PMU_MAX_PMDS]={ +/* pmd0 */ { PFM_REG_BUFFER, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmd1 */ { PFM_REG_BUFFER, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmd2 */ { PFM_REG_BUFFER, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmd3 */ { PFM_REG_BUFFER, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}}, +/* pmd4 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(4),0UL, 0UL, 0UL}}, +/* pmd5 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(5),0UL, 0UL, 0UL}}, +/* pmd6 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(6),0UL, 0UL, 0UL}}, +/* pmd7 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(7),0UL, 0UL, 0UL}}, +/* pmd8 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(8),0UL, 0UL, 0UL}}, +/* pmd9 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(9),0UL, 0UL, 0UL}}, +/* pmd10 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(10),0UL, 0UL, 0UL}}, +/* pmd11 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}}, +/* pmd12 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}}, +/* pmd13 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(13),0UL, 0UL, 0UL}}, +/* pmd14 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(14),0UL, 0UL, 0UL}}, +/* pmd15 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(15),0UL, 0UL, 0UL}}, + { PFM_REG_END , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */ +}; + +/* + * impl_pmcs, impl_pmds are computed at runtime to minimize errors! + */ +static pmu_config_t pmu_conf={ + .pmu_name = "hpsim", + .pmu_family = 0x7, /* ski emulator reports as Itanium */ + .enabled = 0, + .ovfl_val = (1UL << 32) - 1, + .num_ibrs = 0, /* does not use */ + .num_dbrs = 0, /* does not use */ + .pmd_desc = pfm_hpsim_pmd_desc, + .pmc_desc = pfm_hpsim_pmc_desc +}; diff -Nru a/arch/ia64/kernel/salinfo.c b/arch/ia64/kernel/salinfo.c --- a/arch/ia64/kernel/salinfo.c Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/kernel/salinfo.c Fri Sep 19 00:39:54 2003 @@ -5,6 +5,7 @@ * * Copyright (c) 2001 Silicon Graphics, Inc. All rights reserved. * + * 09/11/2003 jbarnes@sgi.com updated for 2.6 * 10/30/2001 jbarnes@sgi.com copied much of Stephane's palinfo * code to create this file */ @@ -59,7 +60,7 @@ *sdir = create_proc_read_entry (salinfo_entries[i].name, 0, salinfo_dir, salinfo_read, (void *)salinfo_entries[i].feature); if (*sdir) - *sdir->owner = THIS_MODULE; + (*sdir)->owner = THIS_MODULE; sdir++; } *sdir++ = salinfo_dir; diff -Nru a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c --- a/arch/ia64/kernel/smpboot.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/kernel/smpboot.c Fri Sep 19 00:39:53 2003 @@ -534,8 +534,8 @@ printk(KERN_INFO "SMP mode deactivated.\n"); cpus_clear(cpu_online_map); cpus_clear(phys_cpu_present_map); - cpu_set(1, cpu_online_map); - cpu_set(1, phys_cpu_present_map); + cpu_set(0, cpu_online_map); + cpu_set(0, phys_cpu_present_map); return; } } diff -Nru a/arch/ia64/kernel/time.c b/arch/ia64/kernel/time.c --- a/arch/ia64/kernel/time.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/kernel/time.c Fri Sep 19 00:39:53 2003 @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -39,29 +40,6 @@ #endif static void -do_profile (unsigned long ip) -{ - extern cpumask_t prof_cpu_mask; - - if (!prof_buffer) - return; - - if (!cpu_isset(smp_processor_id(), prof_cpu_mask)) - return; - - ip -= (unsigned long) _stext; - ip >>= prof_shift; - /* - * Don't ignore out-of-bounds IP values silently, put them into the last - * histogram slot, so if present, they will show up as a sharp peak. - */ - if (ip > prof_len - 1) - ip = prof_len - 1; - - atomic_inc((atomic_t *) &prof_buffer[ip]); -} - -static void itc_reset (void) { } @@ -199,6 +177,52 @@ tv->tv_usec = usec; } +/* + * The profiling function is SMP safe. (nothing can mess + * around with "current", and the profiling counters are + * updated with atomic operations). This is especially + * useful with a profiling multiplier != 1 + */ +static inline void +ia64_do_profile (struct pt_regs * regs) +{ + unsigned long ip, slot; + extern cpumask_t prof_cpu_mask; + + profile_hook(regs); + + if (user_mode(regs)) + return; + + if (!prof_buffer) + return; + + ip = instruction_pointer(regs); + /* Conserve space in histogram by encoding slot bits in address + * bits 2 and 3 rather than bits 0 and 1. + */ + slot = ip & 3; + ip = (ip & ~3UL) + 4*slot; + + /* + * Only measure the CPUs specified by /proc/irq/prof_cpu_mask. + * (default is all CPUs.) + */ + if (!cpu_isset(smp_processor_id(), prof_cpu_mask)) + return; + + ip -= (unsigned long) &_stext; + ip >>= prof_shift; + /* + * Don't ignore out-of-bounds IP values silently, + * put them into the last histogram slot, so if + * present, they will show up as a sharp peak. + */ + if (ip > prof_len-1) + ip = prof_len-1; + atomic_inc((atomic_t *)&prof_buffer[ip]); +} + static irqreturn_t timer_interrupt (int irq, void *dev_id, struct pt_regs *regs) { @@ -210,14 +234,9 @@ printk(KERN_ERR "Oops: timer tick before it's due (itc=%lx,itm=%lx)\n", ia64_get_itc(), new_itm); + ia64_do_profile(regs); + while (1) { - /* - * Do kernel PC profiling here. We multiply the instruction number by - * four so that we can use a prof_shift of 2 to get instruction-level - * instead of just bundle-level accuracy. - */ - if (!user_mode(regs)) - do_profile(regs->cr_iip + 4*ia64_psr(regs)->ri); #ifdef CONFIG_SMP smp_do_timer(regs); diff -Nru a/arch/ia64/kernel/traps.c b/arch/ia64/kernel/traps.c --- a/arch/ia64/kernel/traps.c Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/kernel/traps.c Fri Sep 19 00:39:54 2003 @@ -568,10 +568,10 @@ } siginfo.si_signo = SIGTRAP; siginfo.si_errno = 0; - siginfo.si_flags = 0; - siginfo.si_isr = 0; - siginfo.si_addr = (void *) ifa; - siginfo.si_imm = 0; + siginfo.si_addr = (void *) ifa; + siginfo.si_imm = 0; + siginfo.si_flags = __ISR_VALID; + siginfo.si_isr = isr; force_sig_info(SIGTRAP, &siginfo, current); return; diff -Nru a/arch/ia64/kernel/unwind.c b/arch/ia64/kernel/unwind.c --- a/arch/ia64/kernel/unwind.c Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/kernel/unwind.c Fri Sep 19 00:39:54 2003 @@ -1171,9 +1171,10 @@ static inline unw_hash_index_t hash (unsigned long ip) { -# define magic 0x9e3779b97f4a7c16 /* based on (sqrt(5)/2-1)*2^64 */ +# define hashmagic 0x9e3779b97f4a7c16 /* based on (sqrt(5)/2-1)*2^64 */ - return (ip >> 4)*magic >> (64 - UNW_LOG_HASH_SIZE); + return (ip >> 4)*hashmagic >> (64 - UNW_LOG_HASH_SIZE); +#undef hashmagic } static inline long diff -Nru a/arch/ia64/oprofile/Kconfig b/arch/ia64/oprofile/Kconfig --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/ia64/oprofile/Kconfig Fri Sep 19 00:39:54 2003 @@ -0,0 +1,22 @@ + +menu "Profiling support" + depends on EXPERIMENTAL + +config PROFILING + bool "Profiling support (EXPERIMENTAL)" + help + Say Y here to enable the extended profiling support mechanisms used + by profilers such as OProfile. + +config OPROFILE + tristate "OProfile system profiling (EXPERIMENTAL)" + depends on PROFILING + help + OProfile is a profiling system capable of profiling the + whole system, include the kernel, kernel modules, libraries, + and applications. + + If unsure, say N. + +endmenu + diff -Nru a/arch/ia64/oprofile/Makefile b/arch/ia64/oprofile/Makefile --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/ia64/oprofile/Makefile Fri Sep 19 00:39:54 2003 @@ -0,0 +1,9 @@ +obj-$(CONFIG_OPROFILE) += oprofile.o + +DRIVER_OBJS := $(addprefix ../../../drivers/oprofile/, \ + oprof.o cpu_buffer.o buffer_sync.o \ + event_buffer.o oprofile_files.o \ + oprofilefs.o oprofile_stats.o \ + timer_int.o ) + +oprofile-y := $(DRIVER_OBJS) init.o diff -Nru a/arch/ia64/oprofile/init.c b/arch/ia64/oprofile/init.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/arch/ia64/oprofile/init.c Fri Sep 19 00:39:54 2003 @@ -0,0 +1,25 @@ +/** + * @file init.c + * + * @remark Copyright 2002 OProfile authors + * @remark Read the file COPYING + * + * @author John Levon + */ + +#include +#include +#include +#include + +extern void timer_init(struct oprofile_operations ** ops); + +int __init oprofile_arch_init(struct oprofile_operations ** ops) +{ + return -ENODEV; +} + + +void oprofile_arch_exit(void) +{ +} diff -Nru a/arch/ia64/scripts/toolchain-flags b/arch/ia64/scripts/toolchain-flags --- a/arch/ia64/scripts/toolchain-flags Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/scripts/toolchain-flags Fri Sep 19 00:39:54 2003 @@ -20,7 +20,7 @@ EOF fi -if ! $CC -c $dir/check-model.c -o $out 2>&1 | grep -q 'attribute directive ignored' +if ! $CC -c $dir/check-model.c -o $out 2>&1 | grep __model__ | grep -q attrib then CPPFLAGS="$CPPFLAGS -DHAVE_MODEL_SMALL_ATTRIBUTE" fi diff -Nru a/arch/ia64/sn/io/drivers/ioconfig_bus.c b/arch/ia64/sn/io/drivers/ioconfig_bus.c --- a/arch/ia64/sn/io/drivers/ioconfig_bus.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/sn/io/drivers/ioconfig_bus.c Fri Sep 19 00:39:53 2003 @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include @@ -157,7 +157,7 @@ char *name; char *temp; char *next; - char *current; + char *curr; char *line; struct ascii_moduleid *moduleid; @@ -166,10 +166,10 @@ name = kmalloc(125, GFP_KERNEL); memset(name, 0, 125); moduleid = table; - current = file_contents; - while (nextline(current, &next, line)){ + curr = file_contents; + while (nextline(curr, &next, line)){ - DBG("current 0x%lx next 0x%lx\n", current, next); + DBG("curr 0x%lx next 0x%lx\n", curr, next); temp = line; /* @@ -182,7 +182,7 @@ break; if (*temp == '\n') { - current = next; + curr = next; memset(line, 0, 256); continue; } @@ -191,7 +191,7 @@ * Skip comment lines */ if (*temp == '#') { - current = next; + curr = next; memset(line, 0, 256); continue; } @@ -204,7 +204,7 @@ DBG("Found %s\n", name); moduleid++; free_entry++; - current = next; + curr = next; memset(line, 0, 256); } diff -Nru a/arch/ia64/sn/io/machvec/iomv.c b/arch/ia64/sn/io/machvec/iomv.c --- a/arch/ia64/sn/io/machvec/iomv.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/sn/io/machvec/iomv.c Fri Sep 19 00:39:53 2003 @@ -6,13 +6,13 @@ * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved. */ -#include #include #include #include #include #include #include +#include /** * sn_io_addr - convert an in/out port to an i/o address diff -Nru a/arch/ia64/sn/io/machvec/pci_bus_cvlink.c b/arch/ia64/sn/io/machvec/pci_bus_cvlink.c --- a/arch/ia64/sn/io/machvec/pci_bus_cvlink.c Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/sn/io/machvec/pci_bus_cvlink.c Fri Sep 19 00:39:54 2003 @@ -544,7 +544,7 @@ pci_read_config_byte(device_dev, PCI_INTERRUPT_PIN, (unsigned char *)&lines); - irqpdaindr->current = device_dev; + irqpdaindr->curr = device_dev; intr_handle = pciio_intr_alloc(device_vertex, NULL, lines, device_vertex); irq = intr_handle->pi_irq; diff -Nru a/arch/ia64/sn/io/machvec/pci_dma.c b/arch/ia64/sn/io/machvec/pci_dma.c --- a/arch/ia64/sn/io/machvec/pci_dma.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/sn/io/machvec/pci_dma.c Fri Sep 19 00:39:53 2003 @@ -597,7 +597,7 @@ if (!sn_dma_supported(dev, dma_mask)) return 0; - dev->dma_mask = dma_mask; + *dev->dma_mask = dma_mask; return 1; } EXPORT_SYMBOL(sn_dma_set_mask); diff -Nru a/arch/ia64/sn/io/sn2/ml_SN_intr.c b/arch/ia64/sn/io/sn2/ml_SN_intr.c --- a/arch/ia64/sn/io/sn2/ml_SN_intr.c Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/sn/io/sn2/ml_SN_intr.c Fri Sep 19 00:39:54 2003 @@ -39,6 +39,7 @@ #include #include #include +#include extern irqpda_t *irqpdaindr; extern cnodeid_t master_node_get(vertex_hdl_t vhdl); @@ -174,8 +175,8 @@ min_shared = 256; for (i=IA64_SN2_FIRST_DEVICE_VECTOR; i < IA64_SN2_LAST_DEVICE_VECTOR; i++) { /* Share with the same device class */ - if (irqpdaindr->current->vendor == irqpdaindr->device_dev[i]->vendor && - irqpdaindr->current->device == irqpdaindr->device_dev[i]->device && + if (irqpdaindr->curr->vendor == irqpdaindr->device_dev[i]->vendor && + irqpdaindr->curr->device == irqpdaindr->device_dev[i]->device && irqpdaindr->share_count[i] < min_shared) { min_shared = irqpdaindr->share_count[i]; bit = i; diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c Fri Sep 19 00:39:53 2003 @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c Fri Sep 19 00:39:54 2003 @@ -27,7 +27,6 @@ #include #include #include -#include #include #include diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c Fri Sep 19 00:39:54 2003 @@ -31,7 +31,6 @@ #include #include #include -#include #include #include diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c Fri Sep 19 00:39:53 2003 @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c Fri Sep 19 00:39:54 2003 @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c Fri Sep 19 00:39:54 2003 @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c Fri Sep 19 00:39:54 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c Fri Sep 19 00:39:54 2003 @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c Fri Sep 19 00:39:53 2003 @@ -27,7 +27,6 @@ #include #include #include -#include #include #include diff -Nru a/arch/ia64/sn/io/sn2/pic.c b/arch/ia64/sn/io/sn2/pic.c --- a/arch/ia64/sn/io/sn2/pic.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/sn/io/sn2/pic.c Fri Sep 19 00:39:53 2003 @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff -Nru a/arch/ia64/sn/io/sn2/shub.c b/arch/ia64/sn/io/sn2/shub.c --- a/arch/ia64/sn/io/sn2/shub.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/sn/io/sn2/shub.c Fri Sep 19 00:39:53 2003 @@ -34,6 +34,8 @@ #include #include #include +#include +#include /* * Shub WAR for Xbridge Little Endian problem: diff -Nru a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c --- a/arch/ia64/sn/kernel/irq.c Fri Sep 19 00:39:53 2003 +++ b/arch/ia64/sn/kernel/irq.c Fri Sep 19 00:39:53 2003 @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include @@ -44,7 +43,6 @@ #include #include #include -#include #include #include #include @@ -62,6 +60,7 @@ #include #include #include +#include int irq_to_bit_pos(int irq); static void force_interrupt(int irq); diff -Nru a/drivers/acpi/tables.c b/drivers/acpi/tables.c --- a/drivers/acpi/tables.c Fri Sep 19 00:39:53 2003 +++ b/drivers/acpi/tables.c Fri Sep 19 00:39:53 2003 @@ -261,10 +261,17 @@ /* Map the DSDT header via the pointer in the FADT */ if (id == ACPI_DSDT) { - struct acpi_table_fadt *fadt = (struct acpi_table_fadt *) *header; + struct fadt_descriptor_rev2 *fadt = (struct fadt_descriptor_rev2 *) *header; + + if (fadt->header.revision == 3 && fadt->Xdsdt) { + *header = (void *) __acpi_map_table(fadt->Xdsdt, + sizeof(struct acpi_table_header)); + } else if (fadt->V1_dsdt) { + *header = (void *) __acpi_map_table(fadt->V1_dsdt, + sizeof(struct acpi_table_header)); + } else + *header = 0; - *header = (void *) __acpi_map_table(fadt->dsdt_addr, - sizeof(struct acpi_table_header)); if (!*header) { printk(KERN_WARNING PREFIX "Unable to map DSDT\n"); return -ENODEV; diff -Nru a/drivers/char/agp/hp-agp.c b/drivers/char/agp/hp-agp.c --- a/drivers/char/agp/hp-agp.c Fri Sep 19 00:39:54 2003 +++ b/drivers/char/agp/hp-agp.c Fri Sep 19 00:39:54 2003 @@ -42,6 +42,8 @@ /* AGP bridge need not be PCI device, but DRM thinks it is. */ static struct pci_dev fake_bridge_dev; +static int hp_zx1_gart_found; + static struct aper_size_info_fixed hp_zx1_sizes[] = { {0, 0, 0}, /* filled in by hp_zx1_fetch_size() */ @@ -386,8 +388,6 @@ struct agp_bridge_data *bridge; int error; - printk(KERN_INFO PFX "Detected HP ZX1 AGP chipset (ioc=%lx, lba=%lx)\n", ioc_hpa, lba_hpa); - error = hp_zx1_ioc_init(ioc_hpa, lba_hpa); if (error) return error; @@ -416,7 +416,7 @@ status = hp_acpi_csr_space(obj, &lba_hpa, &length); if (ACPI_FAILURE(status)) - return 1; + return AE_OK; /* Look for an enclosing IOC scope and find its CSR space */ handle = obj; @@ -436,7 +436,7 @@ else { printk(KERN_ERR PFX "Detected HP ZX1 " "AGP LBA but no IOC.\n"); - return status; + return AE_OK; } } } @@ -446,22 +446,28 @@ } while (ACPI_SUCCESS(status)); if (hp_zx1_setup(sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa)) - return 1; - return 0; + return AE_OK; + + printk(KERN_INFO PFX "Detected HP ZX1 %s AGP chipset (ioc=%lx, lba=%lx)\n", + (char *) context, sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa); + + hp_zx1_gart_found = 1; + return AE_CTRL_TERMINATE; } static int __init agp_hp_init (void) { - acpi_status status; - status = acpi_get_devices("HWP0003", zx1_gart_probe, "HWP0003 AGP LBA", NULL); - if (!(ACPI_SUCCESS(status))) { - agp_bridge->type = NOT_SUPPORTED; - printk(KERN_INFO PFX "Failed to initialize zx1 AGP.\n"); - return -ENODEV; - } - return 0; + acpi_get_devices("HWP0003", zx1_gart_probe, "HWP0003", NULL); + if (hp_zx1_gart_found) + return 0; + + acpi_get_devices("HWP0007", zx1_gart_probe, "HWP0007", NULL); + if (hp_zx1_gart_found) + return 0; + + return -ENODEV; } static void __exit diff -Nru a/drivers/media/radio/Makefile b/drivers/media/radio/Makefile --- a/drivers/media/radio/Makefile Fri Sep 19 00:39:53 2003 +++ b/drivers/media/radio/Makefile Fri Sep 19 00:39:53 2003 @@ -2,6 +2,8 @@ # Makefile for the kernel character device drivers. # +obj-y := dummy.o + miropcm20-objs := miropcm20-rds-core.o miropcm20-radio.o obj-$(CONFIG_RADIO_AZTECH) += radio-aztech.o diff -Nru a/drivers/media/radio/dummy.c b/drivers/media/radio/dummy.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/drivers/media/radio/dummy.c Fri Sep 19 00:39:54 2003 @@ -0,0 +1 @@ +/* just so the linker knows what kind of object files it's deadling with... */ diff -Nru a/drivers/media/video/Makefile b/drivers/media/video/Makefile --- a/drivers/media/video/Makefile Fri Sep 19 00:39:53 2003 +++ b/drivers/media/video/Makefile Fri Sep 19 00:39:53 2003 @@ -7,6 +7,7 @@ zoran-objs := zr36120.o zr36120_i2c.o zr36120_mem.o zr36067-objs := zoran_procfs.o zoran_device.o \ zoran_driver.o zoran_card.o +obj-y := dummy.o obj-$(CONFIG_VIDEO_DEV) += videodev.o v4l2-common.o v4l1-compat.o diff -Nru a/drivers/media/video/dummy.c b/drivers/media/video/dummy.c --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/drivers/media/video/dummy.c Fri Sep 19 00:39:54 2003 @@ -0,0 +1 @@ +/* just so the linker knows what kind of object files it's deadling with... */ diff -Nru a/drivers/net/tulip/media.c b/drivers/net/tulip/media.c --- a/drivers/net/tulip/media.c Fri Sep 19 00:39:53 2003 +++ b/drivers/net/tulip/media.c Fri Sep 19 00:39:53 2003 @@ -278,6 +278,10 @@ for (i = 0; i < init_length; i++) outl(init_sequence[i], ioaddr + CSR12); } + + (void) inl(ioaddr + CSR6); /* flush CSR12 writes */ + udelay(500); /* Give MII time to recover */ + tmp_info = get_u16(&misc_info[1]); if (tmp_info) tp->advertising[phy_num] = tmp_info | 1; diff -Nru a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h --- a/include/asm-ia64/acpi.h Fri Sep 19 00:39:54 2003 +++ b/include/asm-ia64/acpi.h Fri Sep 19 00:39:54 2003 @@ -30,6 +30,8 @@ #ifdef __KERNEL__ +#include + #define COMPILER_DEPENDENT_INT64 long #define COMPILER_DEPENDENT_UINT64 unsigned long @@ -54,47 +56,35 @@ #define ACPI_ENABLE_IRQS() local_irq_enable() #define ACPI_FLUSH_CPU_CACHE() -#define ACPI_ACQUIRE_GLOBAL_LOCK(GLptr, Acq) \ - do { \ - __asm__ volatile ("1: ld4 r29=[%1]\n" \ - ";;\n" \ - "mov ar.ccv=r29\n" \ - "mov r2=r29\n" \ - "shr.u r30=r29,1\n" \ - "and r29=-4,r29\n" \ - ";;\n" \ - "add r29=2,r29\n" \ - "and r30=1,r30\n" \ - ";;\n" \ - "add r29=r29,r30\n" \ - ";;\n" \ - "cmpxchg4.acq r30=[%1],r29,ar.ccv\n" \ - ";;\n" \ - "cmp.eq p6,p7=r2,r30\n" \ - "(p7) br.dpnt.few 1b\n" \ - "cmp.gt p8,p9=3,r29\n" \ - ";;\n" \ - "(p8) mov %0=-1\n" \ - "(p9) mov %0=r0\n" \ - :"=r"(Acq):"r"(GLptr):"r2","r29","r30","memory"); \ - } while (0) - -#define ACPI_RELEASE_GLOBAL_LOCK(GLptr, Acq) \ - do { \ - __asm__ volatile ("1: ld4 r29=[%1]\n" \ - ";;\n" \ - "mov ar.ccv=r29\n" \ - "mov r2=r29\n" \ - "and r29=-4,r29\n" \ - ";;\n" \ - "cmpxchg4.acq r30=[%1],r29,ar.ccv\n" \ - ";;\n" \ - "cmp.eq p6,p7=r2,r30\n" \ - "(p7) br.dpnt.few 1b\n" \ - "and %0=1,r2\n" \ - ";;\n" \ - :"=r"(Acq):"r"(GLptr):"r2","r29","r30","memory"); \ - } while (0) +static inline int +ia64_acpi_acquire_global_lock (unsigned int *lock) +{ + unsigned int old, new, val; + do { + old = *lock; + new = (((old & ~0x3) + 2) + ((old >> 1) & 0x1)); + val = ia64_cmpxchg4_acq(lock, new, old); + } while (unlikely (val != old)); + return (new < 3) ? -1 : 0; +} + +static inline int +ia64_acpi_release_global_lock (unsigned int *lock) +{ + unsigned int old, new, val; + do { + old = *lock; + new = old & ~0x3; + val = ia64_cmpxchg4_acq(lock, new, old); + } while (unlikely (val != old)); + return old & 0x1; +} + +#define ACPI_ACQUIRE_GLOBAL_LOCK(GLptr, Acq) \ + ((Acq) = ia64_acpi_acquire_global_lock((unsigned int *) GLptr)) + +#define ACPI_RELEASE_GLOBAL_LOCK(GLptr, Acq) \ + ((Acq) = ia64_acpi_release_global_lock((unsigned int *) GLptr)) const char *acpi_get_sysname (void); int acpi_request_vector (u32 int_type); diff -Nru a/include/asm-ia64/hw_irq.h b/include/asm-ia64/hw_irq.h --- a/include/asm-ia64/hw_irq.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/hw_irq.h Fri Sep 19 00:39:53 2003 @@ -9,6 +9,7 @@ #include #include #include +#include #include #include diff -Nru a/include/asm-ia64/intel_intrin.h b/include/asm-ia64/intel_intrin.h --- /dev/null Wed Dec 31 16:00:00 1969 +++ b/include/asm-ia64/intel_intrin.h Fri Sep 19 00:39:54 2003 @@ -0,0 +1,254 @@ +#ifndef _ASM_IA64_INTEL_INTRIN_H +#define _ASM_IA64_INTEL_INTRIN_H +/* + * Intel Compiler Intrinsics + * + * Copyright (C) 2002,2003 Jun Nakajima + * Copyright (C) 2002,2003 Suresh Siddha + * + */ +#include + +void __lfetch(int lfhint, void *y); +void __lfetch_excl(int lfhint, void *y); +void __lfetch_fault(int lfhint, void *y); +void __lfetch_fault_excl(int lfhint, void *y); + +/* In the following, whichFloatReg should be an integer from 0-127 */ +void __ldfs(const int whichFloatReg, void *src); +void __ldfd(const int whichFloatReg, void *src); +void __ldfe(const int whichFloatReg, void *src); +void __ldf8(const int whichFloatReg, void *src); +void __ldf_fill(const int whichFloatReg, void *src); +void __stfs(void *dst, const int whichFloatReg); +void __stfd(void *dst, const int whichFloatReg); +void __stfe(void *dst, const int whichFloatReg); +void __stf8(void *dst, const int whichFloatReg); +void __stf_spill(void *dst, const int whichFloatReg); + +void __st1_rel(void *dst, const __s8 value); +void __st2_rel(void *dst, const __s16 value); +void __st4_rel(void *dst, const __s32 value); +void __st8_rel(void *dst, const __s64 value); +__u8 __ld1_acq(void *src); +__u16 __ld2_acq(void *src); +__u32 __ld4_acq(void *src); +__u64 __ld8_acq(void *src); + +__u64 __fetchadd4_acq(__u32 *addend, const int increment); +__u64 __fetchadd4_rel(__u32 *addend, const int increment); +__u64 __fetchadd8_acq(__u64 *addend, const int increment); +__u64 __fetchadd8_rel(__u64 *addend, const int increment); + +__u64 __getf_exp(double d); + +/* OS Related Itanium(R) Intrinsics */ + +/* The names to use for whichReg and whichIndReg below come from + the include file asm/ia64regs.h */ + +__u64 __getIndReg(const int whichIndReg, __s64 index); +__u64 __getReg(const int whichReg); + +void __setIndReg(const int whichIndReg, __s64 index, __u64 value); +void __setReg(const int whichReg, __u64 value); + +void __mf(void); +void __mfa(void); +void __synci(void); +void __itcd(__s64 pa); +void __itci(__s64 pa); +void __itrd(__s64 whichTransReg, __s64 pa); +void __itri(__s64 whichTransReg, __s64 pa); +void __ptce(__s64 va); +void __ptcl(__s64 va, __s64 pagesz); +void __ptcg(__s64 va, __s64 pagesz); +void __ptcga(__s64 va, __s64 pagesz); +void __ptri(__s64 va, __s64 pagesz); +void __ptrd(__s64 va, __s64 pagesz); +void __invala (void); +void __invala_gr(const int whichGeneralReg /* 0-127 */ ); +void __invala_fr(const int whichFloatReg /* 0-127 */ ); +void __nop(const int); +void __fc(__u64 *addr); +void __sum(int mask); +void __rum(int mask); +void __ssm(int mask); +void __rsm(int mask); +__u64 __thash(__s64); +__u64 __ttag(__s64); +__s64 __tpa(__s64); + +/* Intrinsics for implementing get/put_user macros */ +void __st_user(const char *tableName, __u64 addr, char size, char relocType, __u64 val); +void __ld_user(const char *tableName, __u64 addr, char size, char relocType); + +/* This intrinsic does not generate code, it creates a barrier across which + * the compiler will not schedule data access instructions. + */ +void __memory_barrier(void); + +void __isrlz(void); +void __dsrlz(void); + +__u64 _m64_mux1(__u64 a, const int n); +__u64 __thash(__u64); + +/* Lock and Atomic Operation Related Intrinsics */ +__u64 _InterlockedExchange8(volatile __u8 *trgt, __u8 value); +__u64 _InterlockedExchange16(volatile __u16 *trgt, __u16 value); +__s64 _InterlockedExchange(volatile __u32 *trgt, __u32 value); +__s64 _InterlockedExchange64(volatile __u64 *trgt, __u64 value); + +__u64 _InterlockedCompareExchange8_rel(volatile __u8 *dest, __u64 xchg, __u64 comp); +__u64 _InterlockedCompareExchange8_acq(volatile __u8 *dest, __u64 xchg, __u64 comp); +__u64 _InterlockedCompareExchange16_rel(volatile __u16 *dest, __u64 xchg, __u64 comp); +__u64 _InterlockedCompareExchange16_acq(volatile __u16 *dest, __u64 xchg, __u64 comp); +__u64 _InterlockedCompareExchange_rel(volatile __u32 *dest, __u64 xchg, __u64 comp); +__u64 _InterlockedCompareExchange_acq(volatile __u32 *dest, __u64 xchg, __u64 comp); +__u64 _InterlockedCompareExchange64_rel(volatile __u64 *dest, __u64 xchg, __u64 comp); +__u64 _InterlockedCompareExchange64_acq(volatile __u64 *dest, __u64 xchg, __u64 comp); + +__s64 _m64_dep_mi(const int v, __s64 s, const int p, const int len); +__s64 _m64_shrp(__s64 a, __s64 b, const int count); +__s64 _m64_popcnt(__s64 a); + +#define ia64_barrier() __memory_barrier() + +#define ia64_stop() /* Nothing: As of now stop bit is generated for each + * intrinsic + */ + +#define ia64_getreg __getReg +#define ia64_setreg __setReg + +#define ia64_hint(x) + +#define ia64_mux1_brcst 0 +#define ia64_mux1_mix 8 +#define ia64_mux1_shuf 9 +#define ia64_mux1_alt 10 +#define ia64_mux1_rev 11 + +#define ia64_mux1 _m64_mux1 +#define ia64_popcnt _m64_popcnt +#define ia64_getf_exp __getf_exp +#define ia64_shrp _m64_shrp + +#define ia64_tpa __tpa +#define ia64_invala __invala +#define ia64_invala_gr __invala_gr +#define ia64_invala_fr __invala_fr +#define ia64_nop __nop +#define ia64_sum __sum +#define ia64_ssm __ssm +#define ia64_rum __rum +#define ia64_rsm __rsm +#define ia64_fc __fc + +#define ia64_ldfs __ldfs +#define ia64_ldfd __ldfd +#define ia64_ldfe __ldfe +#define ia64_ldf8 __ldf8 +#define ia64_ldf_fill __ldf_fill + +#define ia64_stfs __stfs +#define ia64_stfd __stfd +#define ia64_stfe __stfe +#define ia64_stf8 __stf8 +#define ia64_stf_spill __stf_spill + +#define ia64_mf __mf +#define ia64_mfa __mfa + +#define ia64_fetchadd4_acq __fetchadd4_acq +#define ia64_fetchadd4_rel __fetchadd4_rel +#define ia64_fetchadd8_acq __fetchadd8_acq +#define ia64_fetchadd8_rel __fetchadd8_rel + +#define ia64_xchg1 _InterlockedExchange8 +#define ia64_xchg2 _InterlockedExchange16 +#define ia64_xchg4 _InterlockedExchange +#define ia64_xchg8 _InterlockedExchange64 + +#define ia64_cmpxchg1_rel _InterlockedCompareExchange8_rel +#define ia64_cmpxchg1_acq _InterlockedCompareExchange8_acq +#define ia64_cmpxchg2_rel _InterlockedCompareExchange16_rel +#define ia64_cmpxchg2_acq _InterlockedCompareExchange16_acq +#define ia64_cmpxchg4_rel _InterlockedCompareExchange_rel +#define ia64_cmpxchg4_acq _InterlockedCompareExchange_acq +#define ia64_cmpxchg8_rel _InterlockedCompareExchange64_rel +#define ia64_cmpxchg8_acq _InterlockedCompareExchange64_acq + +#define __ia64_set_dbr(index, val) \ + __setIndReg(_IA64_REG_INDR_DBR, index, val) +#define ia64_set_ibr(index, val) \ + __setIndReg(_IA64_REG_INDR_IBR, index, val) +#define ia64_set_pkr(index, val) \ + __setIndReg(_IA64_REG_INDR_PKR, index, val) +#define ia64_set_pmc(index, val) \ + __setIndReg(_IA64_REG_INDR_PMC, index, val) +#define ia64_set_pmd(index, val) \ + __setIndReg(_IA64_REG_INDR_PMD, index, val) +#define ia64_set_rr(index, val) \ + __setIndReg(_IA64_REG_INDR_RR, index, val) + +#define ia64_get_cpuid(index) __getIndReg(_IA64_REG_INDR_CPUID, index) +#define __ia64_get_dbr(index) __getIndReg(_IA64_REG_INDR_DBR, index) +#define ia64_get_ibr(index) __getIndReg(_IA64_REG_INDR_IBR, index) +#define ia64_get_pkr(index) __getIndReg(_IA64_REG_INDR_PKR, index) +#define ia64_get_pmc(index) __getIndReg(_IA64_REG_INDR_PMC, index) +#define ia64_get_pmd(index) __getIndReg(_IA64_REG_INDR_PMD, index) +#define ia64_get_rr(index) __getIndReg(_IA64_REG_INDR_RR, index) + +#define ia64_srlz_d __dsrlz +#define ia64_srlz_i __isrlz + +#define ia64_st1_rel __st1_rel +#define ia64_st2_rel __st2_rel +#define ia64_st4_rel __st4_rel +#define ia64_st8_rel __st8_rel + +#define ia64_ld1_acq __ld1_acq +#define ia64_ld2_acq __ld2_acq +#define ia64_ld4_acq __ld4_acq +#define ia64_ld8_acq __ld8_acq + +#define ia64_sync_i __synci +#define ia64_thash __thash +#define ia64_ttag __ttag +#define ia64_itcd __itcd +#define ia64_itci __itci +#define ia64_itrd __itrd +#define ia64_itri __itri +#define ia64_ptce __ptce +#define ia64_ptcl __ptcl +#define ia64_ptcg __ptcg +#define ia64_ptcga __ptcga +#define ia64_ptri __ptri +#define ia64_ptrd __ptrd +#define ia64_dep_mi _m64_dep_mi + +/* Values for lfhint in __lfetch and __lfetch_fault */ + +#define ia64_lfhint_none 0 +#define ia64_lfhint_nt1 1 +#define ia64_lfhint_nt2 2 +#define ia64_lfhint_nta 3 + +#define ia64_lfetch __lfetch +#define ia64_lfetch_excl __lfetch_excl +#define ia64_lfetch_fault __lfetch_fault +#define ia64_lfetch_fault_excl __lfetch_fault_excl + +#define ia64_intrin_local_irq_restore(x) \ +do { \ + if ((x) != 0) { \ + ia64_ssm(IA64_PSR_I); \ + ia64_srlz_d(); \ + } else { \ + ia64_rsm(IA64_PSR_I); \ + } \ +} while (0) + +#endif /* _ASM_IA64_INTEL_INTRIN_H */ diff -Nru a/include/asm-ia64/numa.h b/include/asm-ia64/numa.h --- a/include/asm-ia64/numa.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/numa.h Fri Sep 19 00:39:53 2003 @@ -23,7 +23,7 @@ #include extern volatile char cpu_to_node_map[NR_CPUS] __cacheline_aligned; -extern volatile unsigned long node_to_cpu_mask[NR_NODES] __cacheline_aligned; +extern volatile cpumask_t node_to_cpu_mask[NR_NODES] __cacheline_aligned; /* Stuff below this line could be architecture independent */ diff -Nru a/include/asm-ia64/param.h b/include/asm-ia64/param.h --- a/include/asm-ia64/param.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/param.h Fri Sep 19 00:39:53 2003 @@ -4,22 +4,10 @@ /* * Fundamental kernel parameters. * - * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co + * Copyright (C) 1998, 1999, 2002-2003 Hewlett-Packard Co * David Mosberger-Tang */ -#include - -#ifdef CONFIG_IA64_HP_SIM -/* - * Yeah, simulating stuff is slow, so let us catch some breath between - * timer interrupts... - */ -# define HZ 32 -#else -# define HZ 1024 -#endif - #define EXEC_PAGESIZE 65536 #ifndef NGROUPS @@ -33,8 +21,24 @@ #define MAXHOSTNAMELEN 64 /* max length of hostname */ #ifdef __KERNEL__ +# include /* mustn't include outside of #ifdef __KERNEL__ */ +# ifdef CONFIG_IA64_HP_SIM + /* + * Yeah, simulating stuff is slow, so let us catch some breath between + * timer interrupts... + */ +# define HZ 32 +# else +# define HZ 1024 +# endif # define USER_HZ HZ # define CLOCKS_PER_SEC HZ /* frequency at which times() counts */ +#else + /* + * Technically, this is wrong, but some old apps still refer to it. The proper way to + * get the HZ value is via sysconf(_SC_CLK_TCK). + */ +# define HZ 1024 #endif #endif /* _ASM_IA64_PARAM_H */ diff -Nru a/include/asm-ia64/ptrace.h b/include/asm-ia64/ptrace.h --- a/include/asm-ia64/ptrace.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/ptrace.h Fri Sep 19 00:39:53 2003 @@ -223,6 +223,12 @@ }; #ifdef __KERNEL__ +/* + * We use the ia64_psr(regs)->ri to determine which of the three + * instructions in bundle (16 bytes) took the sample. Generate + * the canonical representation by adding to instruction pointer. + */ +# define instruction_pointer(regs) ((regs)->cr_iip + ia64_psr(regs)->ri) /* given a pointer to a task_struct, return the user's pt_regs */ # define ia64_task_regs(t) (((struct pt_regs *) ((char *) (t) + IA64_STK_OFFSET)) - 1) # define ia64_psr(regs) ((struct ia64_psr *) &(regs)->cr_ipsr) diff -Nru a/include/asm-ia64/signal.h b/include/asm-ia64/signal.h --- a/include/asm-ia64/signal.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/signal.h Fri Sep 19 00:39:53 2003 @@ -2,7 +2,7 @@ #define _ASM_IA64_SIGNAL_H /* - * Copyright (C) 1998-2001 Hewlett-Packard Co + * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co * David Mosberger-Tang * * Unfortunately, this file is being included by bits/signal.h in @@ -96,7 +96,16 @@ * ar.rsc.loadrs is 14 bits, we can assume that they'll never take up * more than 16KB of space. */ -#define MINSIGSTKSZ 131027 /* min. stack size for sigaltstack() */ +#if 1 + /* + * This is a stupid typo: the value was _meant_ to be 131072 (0x20000), but I typed it + * in wrong. ;-( To preserve backwards compatibility, we leave the kernel at the + * incorrect value and fix libc only. + */ +# define MINSIGSTKSZ 131027 /* min. stack size for sigaltstack() */ +#else +# define MINSIGSTKSZ 131072 /* min. stack size for sigaltstack() */ +#endif #define SIGSTKSZ 262144 /* default stack size for sigaltstack() */ #ifdef __KERNEL__ diff -Nru a/include/asm-ia64/sn/hcl.h b/include/asm-ia64/sn/hcl.h --- a/include/asm-ia64/sn/hcl.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/sn/hcl.h Fri Sep 19 00:39:53 2003 @@ -10,6 +10,7 @@ #define _ASM_IA64_SN_HCL_H #include +#include extern vertex_hdl_t hwgraph_root; extern vertex_hdl_t linux_busnum; diff -Nru a/include/asm-ia64/sn/ioc3.h b/include/asm-ia64/sn/ioc3.h --- a/include/asm-ia64/sn/ioc3.h Fri Sep 19 00:39:53 2003 +++ /dev/null Wed Dec 31 16:00:00 1969 @@ -1,705 +0,0 @@ -/* - * Copyright (c) 2002-2003 Silicon Graphics, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it would be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * Further, this software is distributed without any warranty that it is - * free of the rightful claim of any third person regarding infringement - * or the like. Any license provided herein, whether implied or - * otherwise, applies only to this software file. Patent licenses, if - * any, provided herein do not apply to combinations of this program with - * other software, or any other product whatsoever. - * - * You should have received a copy of the GNU General Public - * License along with this program; if not, write the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, - * Mountain View, CA 94043, or: - * - * http://www.sgi.com - * - * For further information regarding this notice, see: - * - * http://oss.sgi.com/projects/GenInfo/NoticeExplan - */ - -/* $Id: ioc3.h,v 1.2 2000/11/16 19:49:17 pfg Exp $ - * - * Copyright (C) 1999 Ralf Baechle - * This file is part of the Linux driver for the SGI IOC3. - */ -#ifndef _ASM_IA64_SN_IOC3_H -#define _ASM_IA64_SN_IOC3_H - -#include - -/* SUPERIO uart register map */ -typedef volatile struct ioc3_uartregs { - union { - volatile u8 rbr; /* read only, DLAB == 0 */ - volatile u8 thr; /* write only, DLAB == 0 */ - volatile u8 dll; /* DLAB == 1 */ - } u1; - union { - volatile u8 ier; /* DLAB == 0 */ - volatile u8 dlm; /* DLAB == 1 */ - } u2; - union { - volatile u8 iir; /* read only */ - volatile u8 fcr; /* write only */ - } u3; - volatile u8 iu_lcr; - volatile u8 iu_mcr; - volatile u8 iu_lsr; - volatile u8 iu_msr; - volatile u8 iu_scr; -} ioc3_uregs_t; - -#define iu_rbr u1.rbr -#define iu_thr u1.thr -#define iu_dll u1.dll -#define iu_ier u2.ier -#define iu_dlm u2.dlm -#define iu_iir u3.iir -#define iu_fcr u3.fcr - -struct ioc3_sioregs { - volatile u8 fill[0x141]; /* starts at 0x141 */ - - volatile u8 uartc; - volatile u8 kbdcg; - - volatile u8 fill0[0x150 - 0x142 - 1]; - - volatile u8 pp_data; - volatile u8 pp_dsr; - volatile u8 pp_dcr; - - volatile u8 fill1[0x158 - 0x152 - 1]; - - volatile u8 pp_fifa; - volatile u8 pp_cfgb; - volatile u8 pp_ecr; - - volatile u8 fill2[0x168 - 0x15a - 1]; - - volatile u8 rtcad; - volatile u8 rtcdat; - - volatile u8 fill3[0x170 - 0x169 - 1]; - - struct ioc3_uartregs uartb; /* 0x20170 */ - struct ioc3_uartregs uarta; /* 0x20178 */ -}; - -/* Register layout of IOC3 in configuration space. */ -struct ioc3 { - volatile u32 pad0[7]; /* 0x00000 */ - volatile u32 sio_ir; /* 0x0001c */ - volatile u32 sio_ies; /* 0x00020 */ - volatile u32 sio_iec; /* 0x00024 */ - volatile u32 sio_cr; /* 0x00028 */ - volatile u32 int_out; /* 0x0002c */ - volatile u32 mcr; /* 0x00030 */ - - /* General Purpose I/O registers */ - volatile u32 gpcr_s; /* 0x00034 */ - volatile u32 gpcr_c; /* 0x00038 */ - volatile u32 gpdr; /* 0x0003c */ - volatile u32 gppr_0; /* 0x00040 */ - volatile u32 gppr_1; /* 0x00044 */ - volatile u32 gppr_2; /* 0x00048 */ - volatile u32 gppr_3; /* 0x0004c */ - volatile u32 gppr_4; /* 0x00050 */ - volatile u32 gppr_5; /* 0x00054 */ - volatile u32 gppr_6; /* 0x00058 */ - volatile u32 gppr_7; /* 0x0005c */ - volatile u32 gppr_8; /* 0x00060 */ - volatile u32 gppr_9; /* 0x00064 */ - volatile u32 gppr_10; /* 0x00068 */ - volatile u32 gppr_11; /* 0x0006c */ - volatile u32 gppr_12; /* 0x00070 */ - volatile u32 gppr_13; /* 0x00074 */ - volatile u32 gppr_14; /* 0x00078 */ - volatile u32 gppr_15; /* 0x0007c */ - - /* Parallel Port Registers */ - volatile u32 ppbr_h_a; /* 0x00080 */ - volatile u32 ppbr_l_a; /* 0x00084 */ - volatile u32 ppcr_a; /* 0x00088 */ - volatile u32 ppcr; /* 0x0008c */ - volatile u32 ppbr_h_b; /* 0x00090 */ - volatile u32 ppbr_l_b; /* 0x00094 */ - volatile u32 ppcr_b; /* 0x00098 */ - - /* Keyboard and Mouse Registers */ - volatile u32 km_csr; /* 0x0009c */ - volatile u32 k_rd; /* 0x000a0 */ - volatile u32 m_rd; /* 0x000a4 */ - volatile u32 k_wd; /* 0x000a8 */ - volatile u32 m_wd; /* 0x000ac */ - - /* Serial Port Registers */ - volatile u32 sbbr_h; /* 0x000b0 */ - volatile u32 sbbr_l; /* 0x000b4 */ - volatile u32 sscr_a; /* 0x000b8 */ - volatile u32 stpir_a; /* 0x000bc */ - volatile u32 stcir_a; /* 0x000c0 */ - volatile u32 srpir_a; /* 0x000c4 */ - volatile u32 srcir_a; /* 0x000c8 */ - volatile u32 srtr_a; /* 0x000cc */ - volatile u32 shadow_a; /* 0x000d0 */ - volatile u32 sscr_b; /* 0x000d4 */ - volatile u32 stpir_b; /* 0x000d8 */ - volatile u32 stcir_b; /* 0x000dc */ - volatile u32 srpir_b; /* 0x000e0 */ - volatile u32 srcir_b; /* 0x000e4 */ - volatile u32 srtr_b; /* 0x000e8 */ - volatile u32 shadow_b; /* 0x000ec */ - - /* Ethernet Registers */ - volatile u32 emcr; /* 0x000f0 */ - volatile u32 eisr; /* 0x000f4 */ - volatile u32 eier; /* 0x000f8 */ - volatile u32 ercsr; /* 0x000fc */ - volatile u32 erbr_h; /* 0x00100 */ - volatile u32 erbr_l; /* 0x00104 */ - volatile u32 erbar; /* 0x00108 */ - volatile u32 ercir; /* 0x0010c */ - volatile u32 erpir; /* 0x00110 */ - volatile u32 ertr; /* 0x00114 */ - volatile u32 etcsr; /* 0x00118 */ - volatile u32 ersr; /* 0x0011c */ - volatile u32 etcdc; /* 0x00120 */ - volatile u32 ebir; /* 0x00124 */ - volatile u32 etbr_h; /* 0x00128 */ - volatile u32 etbr_l; /* 0x0012c */ - volatile u32 etcir; /* 0x00130 */ - volatile u32 etpir; /* 0x00134 */ - volatile u32 emar_h; /* 0x00138 */ - volatile u32 emar_l; /* 0x0013c */ - volatile u32 ehar_h; /* 0x00140 */ - volatile u32 ehar_l; /* 0x00144 */ - volatile u32 micr; /* 0x00148 */ - volatile u32 midr_r; /* 0x0014c */ - volatile u32 midr_w; /* 0x00150 */ - volatile u32 pad1[(0x20000 - 0x00154) / 4]; - - /* SuperIO Registers XXX */ - struct ioc3_sioregs sregs; /* 0x20000 */ - volatile u32 pad2[(0x40000 - 0x20180) / 4]; - - /* SSRAM Diagnostic Access */ - volatile u32 ssram[(0x80000 - 0x40000) / 4]; - - /* Bytebus device offsets - 0x80000 - Access to the generic devices selected with DEV0 - 0x9FFFF bytebus DEV_SEL_0 - 0xA0000 - Access to the generic devices selected with DEV1 - 0xBFFFF bytebus DEV_SEL_1 - 0xC0000 - Access to the generic devices selected with DEV2 - 0xDFFFF bytebus DEV_SEL_2 - 0xE0000 - Access to the generic devices selected with DEV3 - 0xFFFFF bytebus DEV_SEL_3 */ -}; - -/* - * Ethernet RX Buffer - */ -struct ioc3_erxbuf { - u32 w0; /* first word (valid,bcnt,cksum) */ - u32 err; /* second word various errors */ - /* next comes n bytes of padding */ - /* then the received ethernet frame itself */ -}; - -#define ERXBUF_IPCKSUM_MASK 0x0000ffff -#define ERXBUF_BYTECNT_MASK 0x07ff0000 -#define ERXBUF_BYTECNT_SHIFT 16 -#define ERXBUF_V 0x80000000 - -#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */ -#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */ -#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */ -#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */ -#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */ -#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */ -#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */ -#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */ -#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */ -#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */ -#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */ -#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */ - -/* - * Ethernet TX Descriptor - */ -#define ETXD_DATALEN 104 -struct ioc3_etxd { - u32 cmd; /* command field */ - u32 bufcnt; /* buffer counts field */ - u64 p1; /* buffer pointer 1 */ - u64 p2; /* buffer pointer 2 */ - u8 data[ETXD_DATALEN]; /* opt. tx data */ -}; - -#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */ -#define ETXD_INTWHENDONE 0x00001000 /* intr when done */ -#define ETXD_D0V 0x00010000 /* data 0 valid */ -#define ETXD_B1V 0x00020000 /* buf 1 valid */ -#define ETXD_B2V 0x00040000 /* buf 2 valid */ -#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */ -#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */ -#define ETXD_CHKOFF_SHIFT 20 - -#define ETXD_D0CNT_MASK 0x0000007f -#define ETXD_B1CNT_MASK 0x0007ff00 -#define ETXD_B1CNT_SHIFT 8 -#define ETXD_B2CNT_MASK 0x7ff00000 -#define ETXD_B2CNT_SHIFT 20 - -/* - * Bytebus device space - */ -#define IOC3_BYTEBUS_DEV0 0x80000L -#define IOC3_BYTEBUS_DEV1 0xa0000L -#define IOC3_BYTEBUS_DEV2 0xc0000L -#define IOC3_BYTEBUS_DEV3 0xe0000L - -/* ------------------------------------------------------------------------- */ - -/* Superio Registers (PIO Access) */ -#define IOC3_SIO_BASE 0x20000 -#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */ -#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */ -#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */ -#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */ -#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */ -#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */ - -/* SSRAM Diagnostic Access */ -#define IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */ -#define IOC3_SSRAM_LEN 0x40000 /* 256kb (address space size, may not be fully populated) */ -#define IOC3_SSRAM_DM 0x0000ffff /* data mask */ -#define IOC3_SSRAM_PM 0x00010000 /* parity mask */ - -/* bitmasks for PCI_SCR */ -#define PCI_SCR_PAR_RESP_EN 0x00000040 /* enb PCI parity checking */ -#define PCI_SCR_SERR_EN 0x00000100 /* enable the SERR# driver */ -#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */ -#define PCI_SCR_RX_SERR (0x1 << 16) -#define PCI_SCR_DROP_MODE (0x1 << 17) -#define PCI_SCR_SIG_PAR_ERR (0x1 << 24) -#define PCI_SCR_SIG_TAR_ABRT (0x1 << 27) -#define PCI_SCR_RX_TAR_ABRT (0x1 << 28) -#define PCI_SCR_SIG_MST_ABRT (0x1 << 29) -#define PCI_SCR_SIG_SERR (0x1 << 30) -#define PCI_SCR_PAR_ERR (0x1 << 31) - -/* bitmasks for IOC3_KM_CSR */ -#define KM_CSR_K_WRT_PEND 0x00000001 /* kbd port xmitting or resetting */ -#define KM_CSR_M_WRT_PEND 0x00000002 /* mouse port xmitting or resetting */ -#define KM_CSR_K_LCB 0x00000004 /* Line Cntrl Bit for last KBD write */ -#define KM_CSR_M_LCB 0x00000008 /* same for mouse */ -#define KM_CSR_K_DATA 0x00000010 /* state of kbd data line */ -#define KM_CSR_K_CLK 0x00000020 /* state of kbd clock line */ -#define KM_CSR_K_PULL_DATA 0x00000040 /* pull kbd data line low */ -#define KM_CSR_K_PULL_CLK 0x00000080 /* pull kbd clock line low */ -#define KM_CSR_M_DATA 0x00000100 /* state of ms data line */ -#define KM_CSR_M_CLK 0x00000200 /* state of ms clock line */ -#define KM_CSR_M_PULL_DATA 0x00000400 /* pull ms data line low */ -#define KM_CSR_M_PULL_CLK 0x00000800 /* pull ms clock line low */ -#define KM_CSR_EMM_MODE 0x00001000 /* emulation mode */ -#define KM_CSR_SIM_MODE 0x00002000 /* clock X8 */ -#define KM_CSR_K_SM_IDLE 0x00004000 /* Keyboard is idle */ -#define KM_CSR_M_SM_IDLE 0x00008000 /* Mouse is idle */ -#define KM_CSR_K_TO 0x00010000 /* Keyboard trying to send/receive */ -#define KM_CSR_M_TO 0x00020000 /* Mouse trying to send/receive */ -#define KM_CSR_K_TO_EN 0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause - SIO_IR to assert */ -#define KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause - SIO_IR to assert */ -#define KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */ -#define KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */ -#define KM_CSR_K_CLAMP_THREE 0x00400000 /* Pull K_CLK low after rec. three chars */ -#define KM_CSR_M_CLAMP_THREE 0x00800000 /* Pull M_CLK low after rec. three char */ - -/* bitmasks for IOC3_K_RD and IOC3_M_RD */ -#define KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */ -#define KM_RD_DATA_2_SHIFT 0 -#define KM_RD_DATA_1 0x0000ff00 /* 2nd char recvd since last read */ -#define KM_RD_DATA_1_SHIFT 8 -#define KM_RD_DATA_0 0x00ff0000 /* 1st char recvd since last read */ -#define KM_RD_DATA_0_SHIFT 16 -#define KM_RD_FRAME_ERR_2 0x01000000 /* framing or parity error in byte 2 */ -#define KM_RD_FRAME_ERR_1 0x02000000 /* same for byte 1 */ -#define KM_RD_FRAME_ERR_0 0x04000000 /* same for byte 0 */ - -#define KM_RD_KBD_MSE 0x08000000 /* 0 if from kbd, 1 if from mouse */ -#define KM_RD_OFLO 0x10000000 /* 4th char recvd before this read */ -#define KM_RD_VALID_2 0x20000000 /* DATA_2 valid */ -#define KM_RD_VALID_1 0x40000000 /* DATA_1 valid */ -#define KM_RD_VALID_0 0x80000000 /* DATA_0 valid */ -#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2) - -/* bitmasks for IOC3_K_WD & IOC3_M_WD */ -#define KM_WD_WRT_DATA 0x000000ff /* write to keyboard/mouse port */ -#define KM_WD_WRT_DATA_SHIFT 0 - -/* bitmasks for serial RX status byte */ -#define RXSB_OVERRUN 0x01 /* char(s) lost */ -#define RXSB_PAR_ERR 0x02 /* parity error */ -#define RXSB_FRAME_ERR 0x04 /* framing error */ -#define RXSB_BREAK 0x08 /* break character */ -#define RXSB_CTS 0x10 /* state of CTS */ -#define RXSB_DCD 0x20 /* state of DCD */ -#define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */ -#define RXSB_DATA_VALID 0x80 /* data byte, FRAME_ERR PAR_ERR & BREAK valid */ - -/* bitmasks for serial TX control byte */ -#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */ -#define TXCB_INVALID 0x00 /* byte is invalid */ -#define TXCB_VALID 0x40 /* byte is valid */ -#define TXCB_MCR 0x80 /* data<7:0> to modem control register */ -#define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */ - -/* bitmasks for IOC3_SBBR_L */ -#define SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */ -#define SBBR_L_BASE 0xfffff000 /* lower serial ring base addr */ - -/* bitmasks for IOC3_SSCR_ */ -#define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */ -#define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */ -#define SSCR_HFC_EN 0x00020000 /* hardware flow control enabled */ -#define SSCR_RX_RING_DCD 0x00040000 /* post RX record on delta-DCD */ -#define SSCR_RX_RING_CTS 0x00080000 /* post RX record on delta-CTS */ -#define SSCR_HIGH_SPD 0x00100000 /* 4X speed */ -#define SSCR_DIAG 0x00200000 /* bypass clock divider for sim */ -#define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */ -#define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */ -#define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */ -#define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */ -#define SSCR_RESET 0x80000000 /* reset DMA channels */ - -/* all producer/comsumer pointers are the same bitfield */ -#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */ -#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */ -#define PROD_CONS_PTR_OFF 3 - -/* bitmasks for IOC3_SRCIR_ */ -#define SRCIR_ARM 0x80000000 /* arm RX timer */ - -/* bitmasks for IOC3_SRPIR_ */ -#define SRPIR_BYTE_CNT 0x07000000 /* bytes in packer */ -#define SRPIR_BYTE_CNT_SHIFT 24 - -/* bitmasks for IOC3_STCIR_ */ -#define STCIR_BYTE_CNT 0x0f000000 /* bytes in unpacker */ -#define STCIR_BYTE_CNT_SHIFT 24 - -/* bitmasks for IOC3_SHADOW_ */ -#define SHADOW_DR 0x00000001 /* data ready */ -#define SHADOW_OE 0x00000002 /* overrun error */ -#define SHADOW_PE 0x00000004 /* parity error */ -#define SHADOW_FE 0x00000008 /* framing error */ -#define SHADOW_BI 0x00000010 /* break interrupt */ -#define SHADOW_THRE 0x00000020 /* transmit holding register empty */ -#define SHADOW_TEMT 0x00000040 /* transmit shift register empty */ -#define SHADOW_RFCE 0x00000080 /* char in RX fifo has an error */ -#define SHADOW_DCTS 0x00010000 /* delta clear to send */ -#define SHADOW_DDCD 0x00080000 /* delta data carrier detect */ -#define SHADOW_CTS 0x00100000 /* clear to send */ -#define SHADOW_DCD 0x00800000 /* data carrier detect */ -#define SHADOW_DTR 0x01000000 /* data terminal ready */ -#define SHADOW_RTS 0x02000000 /* request to send */ -#define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */ -#define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */ -#define SHADOW_LOOP 0x10000000 /* loopback enabled */ - -/* bitmasks for IOC3_SRTR_ */ -#define SRTR_CNT 0x00000fff /* reload value for RX timer */ -#define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */ -#define SRTR_CNT_VAL_SHIFT 16 -#define SRTR_HZ 16000 /* SRTR clock frequency */ - -/* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES */ -#define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */ -#define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */ -#define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */ -#define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */ -#define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */ -#define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */ -#define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */ -#define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */ -#define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */ -#define SIO_IR_SB_TX_MT 0x00000200 /* */ -#define SIO_IR_SB_RX_FULL 0x00000400 /* */ -#define SIO_IR_SB_RX_HIGH 0x00000800 /* */ -#define SIO_IR_SB_RX_TIMER 0x00001000 /* */ -#define SIO_IR_SB_DELTA_DCD 0x00002000 /* */ -#define SIO_IR_SB_DELTA_CTS 0x00004000 /* */ -#define SIO_IR_SB_INT 0x00008000 /* */ -#define SIO_IR_SB_TX_EXPLICIT 0x00010000 /* */ -#define SIO_IR_SB_MEMERR 0x00020000 /* */ -#define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */ -#define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */ -#define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */ -#define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */ -#define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */ -#define SIO_IR_RT_INT 0x08000000 /* RT output pulse */ -#define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */ -#define SIO_IR_GEN_INT_SHIFT 28 - -/* per device interrupt masks */ -#define SIO_IR_SA (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \ - SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \ - SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \ - SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \ - SIO_IR_SA_MEMERR) -#define SIO_IR_SB (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \ - SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \ - SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \ - SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \ - SIO_IR_SB_MEMERR) -#define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \ - SIO_IR_PP_INTB | SIO_IR_PP_MEMERR) -#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1) - -/* macro to load pending interrupts */ -#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \ - PCI_INW(&((mem)->sio_ies_ro))) - -/* bitmasks for SIO_CR */ -#define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */ -#define SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */ -#define SIO_CR_SER_A_BASE_SHIFT 1 -#define SIO_CR_SER_B_BASE 0x00007f00 /* DMA poll addr port B */ -#define SIO_CR_SER_B_BASE_SHIFT 8 -#define SIO_SR_CMD_PULSE 0x00078000 /* byte bus strobe length */ -#define SIO_CR_CMD_PULSE_SHIFT 15 -#define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */ -#define SIO_CR_ARB_DIAG_TXA 0x00000000 -#define SIO_CR_ARB_DIAG_RXA 0x00080000 -#define SIO_CR_ARB_DIAG_TXB 0x00100000 -#define SIO_CR_ARB_DIAG_RXB 0x00180000 -#define SIO_CR_ARB_DIAG_PP 0x00200000 -#define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */ - -/* bitmasks for INT_OUT */ -#define INT_OUT_COUNT 0x0000ffff /* pulse interval timer */ -#define INT_OUT_MODE 0x00070000 /* mode mask */ -#define INT_OUT_MODE_0 0x00000000 /* set output to 0 */ -#define INT_OUT_MODE_1 0x00040000 /* set output to 1 */ -#define INT_OUT_MODE_1PULSE 0x00050000 /* send 1 pulse */ -#define INT_OUT_MODE_PULSES 0x00060000 /* send 1 pulse every interval */ -#define INT_OUT_MODE_SQW 0x00070000 /* toggle output every interval */ -#define INT_OUT_DIAG 0x40000000 /* diag mode */ -#define INT_OUT_INT_OUT 0x80000000 /* current state of INT_OUT */ - -/* time constants for INT_OUT */ -#define INT_OUT_NS_PER_TICK (30 * 260) /* 30 ns PCI clock, divisor=260 */ -#define INT_OUT_TICKS_PER_PULSE 3 /* outgoing pulse lasts 3 ticks */ -#define INT_OUT_US_TO_COUNT(x) /* convert uS to a count value */ \ - (((x) * 10 + INT_OUT_NS_PER_TICK / 200) * \ - 100 / INT_OUT_NS_PER_TICK - 1) -#define INT_OUT_COUNT_TO_US(x) /* convert count value to uS */ \ - (((x) + 1) * INT_OUT_NS_PER_TICK / 1000) -#define INT_OUT_MIN_TICKS 3 /* min period is width of pulse in "ticks" */ -#define INT_OUT_MAX_TICKS INT_OUT_COUNT /* largest possible count */ - -/* bitmasks for GPCR */ -#define GPCR_DIR 0x000000ff /* tristate pin input or output */ -#define GPCR_DIR_PIN(x) (1<<(x)) /* access one of the DIR bits */ -#define GPCR_EDGE 0x000f0000 /* extint edge or level sensitive */ -#define GPCR_EDGE_PIN(x) (1<<((x)+15)) /* access one of the EDGE bits */ - -/* values for GPCR */ -#define GPCR_INT_OUT_EN 0x00100000 /* enable INT_OUT to pin 0 */ -#define GPCR_MLAN_EN 0x00200000 /* enable MCR to pin 8 */ -#define GPCR_DIR_SERA_XCVR 0x00000080 /* Port A Transceiver select enable */ -#define GPCR_DIR_SERB_XCVR 0x00000040 /* Port B Transceiver select enable */ -#define GPCR_DIR_PHY_RST 0x00000020 /* ethernet PHY reset enable */ - -/* defs for some of the generic I/O pins */ -#define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */ -#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */ -#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */ - -#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */ -#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin controlling uart b mode select */ -#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin controlling uart a mode select */ - -#define EMCR_DUPLEX 0x00000001 -#define EMCR_PROMISC 0x00000002 -#define EMCR_PADEN 0x00000004 -#define EMCR_RXOFF_MASK 0x000001f8 -#define EMCR_RXOFF_SHIFT 3 -#define EMCR_RAMPAR 0x00000200 -#define EMCR_BADPAR 0x00000800 -#define EMCR_BUFSIZ 0x00001000 -#define EMCR_TXDMAEN 0x00002000 -#define EMCR_TXEN 0x00004000 -#define EMCR_RXDMAEN 0x00008000 -#define EMCR_RXEN 0x00010000 -#define EMCR_LOOPBACK 0x00020000 -#define EMCR_ARB_DIAG 0x001c0000 -#define EMCR_ARB_DIAG_IDLE 0x00200000 -#define EMCR_RST 0x80000000 - -#define EISR_RXTIMERINT 0x00000001 -#define EISR_RXTHRESHINT 0x00000002 -#define EISR_RXOFLO 0x00000004 -#define EISR_RXBUFOFLO 0x00000008 -#define EISR_RXMEMERR 0x00000010 -#define EISR_RXPARERR 0x00000020 -#define EISR_TXEMPTY 0x00010000 -#define EISR_TXRTRY 0x00020000 -#define EISR_TXEXDEF 0x00040000 -#define EISR_TXLCOL 0x00080000 -#define EISR_TXGIANT 0x00100000 -#define EISR_TXBUFUFLO 0x00200000 -#define EISR_TXEXPLICIT 0x00400000 -#define EISR_TXCOLLWRAP 0x00800000 -#define EISR_TXDEFERWRAP 0x01000000 -#define EISR_TXMEMERR 0x02000000 -#define EISR_TXPARERR 0x04000000 - -#define ERCSR_THRESH_MASK 0x000001ff /* enet RX threshold */ -#define ERCSR_RX_TMR 0x40000000 /* simulation only */ -#define ERCSR_DIAG_OFLO 0x80000000 /* simulation only */ - -#define ERBR_ALIGNMENT 4096 -#define ERBR_L_RXRINGBASE_MASK 0xfffff000 - -#define ERBAR_BARRIER_BIT 0x0100 -#define ERBAR_RXBARR_MASK 0xffff0000 -#define ERBAR_RXBARR_SHIFT 16 - -#define ERCIR_RXCONSUME_MASK 0x00000fff - -#define ERPIR_RXPRODUCE_MASK 0x00000fff -#define ERPIR_ARM 0x80000000 - -#define ERTR_CNT_MASK 0x000007ff - -#define ETCSR_IPGT_MASK 0x0000007f -#define ETCSR_IPGR1_MASK 0x00007f00 -#define ETCSR_IPGR1_SHIFT 8 -#define ETCSR_IPGR2_MASK 0x007f0000 -#define ETCSR_IPGR2_SHIFT 16 -#define ETCSR_NOTXCLK 0x80000000 - -#define ETCDC_COLLCNT_MASK 0x0000ffff -#define ETCDC_DEFERCNT_MASK 0xffff0000 -#define ETCDC_DEFERCNT_SHIFT 16 - -#define ETBR_ALIGNMENT (64*1024) -#define ETBR_L_RINGSZ_MASK 0x00000001 -#define ETBR_L_RINGSZ128 0 -#define ETBR_L_RINGSZ512 1 -#define ETBR_L_TXRINGBASE_MASK 0xffffc000 - -#define ETCIR_TXCONSUME_MASK 0x0000ffff -#define ETCIR_IDLE 0x80000000 - -#define ETPIR_TXPRODUCE_MASK 0x0000ffff - -#define EBIR_TXBUFPROD_MASK 0x0000001f -#define EBIR_TXBUFCONS_MASK 0x00001f00 -#define EBIR_TXBUFCONS_SHIFT 8 -#define EBIR_RXBUFPROD_MASK 0x007fc000 -#define EBIR_RXBUFPROD_SHIFT 14 -#define EBIR_RXBUFCONS_MASK 0xff800000 -#define EBIR_RXBUFCONS_SHIFT 23 - -#define MICR_REGADDR_MASK 0x0000001f -#define MICR_PHYADDR_MASK 0x000003e0 -#define MICR_PHYADDR_SHIFT 5 -#define MICR_READTRIG 0x00000400 -#define MICR_BUSY 0x00000800 - -#define MIDR_DATA_MASK 0x0000ffff - -#define ERXBUF_IPCKSUM_MASK 0x0000ffff -#define ERXBUF_BYTECNT_MASK 0x07ff0000 -#define ERXBUF_BYTECNT_SHIFT 16 -#define ERXBUF_V 0x80000000 - -#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */ -#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */ -#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */ -#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */ -#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */ -#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */ -#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */ -#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */ -#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */ -#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */ -#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */ -#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */ - -#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */ -#define ETXD_INTWHENDONE 0x00001000 /* intr when done */ -#define ETXD_D0V 0x00010000 /* data 0 valid */ -#define ETXD_B1V 0x00020000 /* buf 1 valid */ -#define ETXD_B2V 0x00040000 /* buf 2 valid */ -#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */ -#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */ -#define ETXD_CHKOFF_SHIFT 20 - -#define ETXD_D0CNT_MASK 0x0000007f -#define ETXD_B1CNT_MASK 0x0007ff00 -#define ETXD_B1CNT_SHIFT 8 -#define ETXD_B2CNT_MASK 0x7ff00000 -#define ETXD_B2CNT_SHIFT 20 - -typedef enum ioc3_subdevs_e { - ioc3_subdev_ether, - ioc3_subdev_generic, - ioc3_subdev_nic, - ioc3_subdev_kbms, - ioc3_subdev_ttya, - ioc3_subdev_ttyb, - ioc3_subdev_ecpp, - ioc3_subdev_rt, - ioc3_nsubdevs -} ioc3_subdev_t; - -/* subdevice disable bits, - * from the standard INFO_LBL_SUBDEVS - */ -#define IOC3_SDB_ETHER (1< -#include - -#define RTC_BASE_ADDR (unsigned char *)(nvram_base) - -/* Defines for the SGS-Thomson M48T35 clock */ -#define RTC_SGS_WRITE_ENABLE 0x80 -#define RTC_SGS_READ_PROTECT 0x40 -#define RTC_SGS_YEAR_ADDR (RTC_BASE_ADDR + 0x7fffL) -#define RTC_SGS_MONTH_ADDR (RTC_BASE_ADDR + 0x7ffeL) -#define RTC_SGS_DATE_ADDR (RTC_BASE_ADDR + 0x7ffdL) -#define RTC_SGS_DAY_ADDR (RTC_BASE_ADDR + 0x7ffcL) -#define RTC_SGS_HOUR_ADDR (RTC_BASE_ADDR + 0x7ffbL) -#define RTC_SGS_MIN_ADDR (RTC_BASE_ADDR + 0x7ffaL) -#define RTC_SGS_SEC_ADDR (RTC_BASE_ADDR + 0x7ff9L) -#define RTC_SGS_CONTROL_ADDR (RTC_BASE_ADDR + 0x7ff8L) - -/* Defines for the Dallas DS1386 */ -#define RTC_DAL_UPDATE_ENABLE 0x80 -#define RTC_DAL_UPDATE_DISABLE 0x00 -#define RTC_DAL_YEAR_ADDR (RTC_BASE_ADDR + 0xaL) -#define RTC_DAL_MONTH_ADDR (RTC_BASE_ADDR + 0x9L) -#define RTC_DAL_DATE_ADDR (RTC_BASE_ADDR + 0x8L) -#define RTC_DAL_DAY_ADDR (RTC_BASE_ADDR + 0x6L) -#define RTC_DAL_HOUR_ADDR (RTC_BASE_ADDR + 0x4L) -#define RTC_DAL_MIN_ADDR (RTC_BASE_ADDR + 0x2L) -#define RTC_DAL_SEC_ADDR (RTC_BASE_ADDR + 0x1L) -#define RTC_DAL_CONTROL_ADDR (RTC_BASE_ADDR + 0xbL) -#define RTC_DAL_USER_ADDR (RTC_BASE_ADDR + 0xeL) - -/* Defines for the Dallas DS1742 */ -#define RTC_DS1742_WRITE_ENABLE 0x80 -#define RTC_DS1742_READ_ENABLE 0x40 -#define RTC_DS1742_UPDATE_DISABLE 0x00 -#define RTC_DS1742_YEAR_ADDR (RTC_BASE_ADDR + 0x7ffL) -#define RTC_DS1742_MONTH_ADDR (RTC_BASE_ADDR + 0x7feL) -#define RTC_DS1742_DATE_ADDR (RTC_BASE_ADDR + 0x7fdL) -#define RTC_DS1742_DAY_ADDR (RTC_BASE_ADDR + 0x7fcL) -#define RTC_DS1742_HOUR_ADDR (RTC_BASE_ADDR + 0x7fbL) -#define RTC_DS1742_MIN_ADDR (RTC_BASE_ADDR + 0x7faL) -#define RTC_DS1742_SEC_ADDR (RTC_BASE_ADDR + 0x7f9L) -#define RTC_DS1742_CONTROL_ADDR (RTC_BASE_ADDR + 0x7f8L) -#define RTC_DS1742_USER_ADDR (RTC_BASE_ADDR + 0x0L) - -#define BCD_TO_INT(x) (((x>>4) * 10) + (x & 0xf)) -#define INT_TO_BCD(x) (((x / 10)<<4) + (x % 10)) - -#define YRREF 1970 - -#endif /* _ASM_IA64_SN_KLCLOCK_H */ diff -Nru a/include/asm-ia64/sn/ksys/elsc.h b/include/asm-ia64/sn/ksys/elsc.h --- a/include/asm-ia64/sn/ksys/elsc.h Fri Sep 19 00:39:54 2003 +++ b/include/asm-ia64/sn/ksys/elsc.h Fri Sep 19 00:39:54 2003 @@ -9,9 +9,6 @@ #ifndef _ASM_SN_KSYS_ELSC_H #define _ASM_SN_KSYS_ELSC_H -#include -#include - /* * Error codes * diff -Nru a/include/asm-ia64/sn/ksys/l1.h b/include/asm-ia64/sn/ksys/l1.h --- a/include/asm-ia64/sn/ksys/l1.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/sn/ksys/l1.h Fri Sep 19 00:39:53 2003 @@ -10,10 +10,7 @@ #ifndef _ASM_SN_KSYS_L1_H #define _ASM_SN_KSYS_L1_H -#include -#include -#include -#include +#include /* L1 Target Addresses */ /* @@ -39,18 +36,6 @@ #define L1_ADDR_TASK_BEDROCK 0x05 /* bedrock */ #define L1_ADDR_TASK_GENERAL 0x06 /* general requests */ -#define L1_ADDR_LOCAL \ - (L1_ADDR_TYPE_L1 << L1_ADDR_TYPE_SHFT) | \ - (L1_ADDR_RACK_LOCAL << L1_ADDR_RACK_SHFT) | \ - (L1_ADDR_BAY_LOCAL << L1_ADDR_BAY_SHFT) - -#define L1_ADDR_LOCALIO \ - (L1_ADDR_TYPE_IOBRICK << L1_ADDR_TYPE_SHFT) | \ - (L1_ADDR_RACK_LOCAL << L1_ADDR_RACK_SHFT) | \ - (L1_ADDR_BAY_LOCAL << L1_ADDR_BAY_SHFT) - -#define L1_ADDR_LOCAL_SHFT L1_ADDR_BAY_SHFT - /* response argument types */ #define L1_ARG_INT 0x00 /* 4-byte integer (big-endian) */ #define L1_ARG_ASCII 0x01 /* null-terminated ASCII string */ @@ -133,18 +118,6 @@ #define L1_EEP_IUSE 3 /* internal use area */ #define L1_EEP_SPD 4 /* serial presence detect record */ -typedef uint32_t l1addr_t; - -#define L1_BUILD_ADDR(addr,at,r,s,t) \ - (*(l1addr_t *)(addr) = ((l1addr_t)(at) << L1_ADDR_TYPE_SHFT) | \ - ((l1addr_t)(r) << L1_ADDR_RACK_SHFT) | \ - ((l1addr_t)(s) << L1_ADDR_BAY_SHFT) | \ - ((l1addr_t)(t) << L1_ADDR_TASK_SHFT)) - -#define L1_ADDRESS_TO_TASK(addr,trb,tsk) \ - (*(l1addr_t *)(addr) = (l1addr_t)(trb) | \ - ((l1addr_t)(tsk) << L1_ADDR_TASK_SHFT)) - #define L1_DISPLAY_LINE_LENGTH 12 /* L1 display characters/line */ #ifdef L1_DISP_2LINES @@ -154,11 +127,9 @@ * to system software */ #endif -#define bzero(d, n) memset((d), 0, (n)) - int elsc_display_line(nasid_t nasid, char *line, int lnum); -int iobrick_rack_bay_type_get( nasid_t nasid, uint *rack, - uint *bay, uint *brick_type ); +int iobrick_rack_bay_type_get( nasid_t nasid, unsigned int *rack, + unsigned int *bay, unsigned int *brick_type ); int iobrick_module_get( nasid_t nasid ); diff -Nru a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h --- a/include/asm-ia64/sn/nodepda.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/sn/nodepda.h Fri Sep 19 00:39:53 2003 @@ -87,7 +87,7 @@ char irq_flags[NR_IRQS]; struct pci_dev *device_dev[NR_IRQS]; char share_count[NR_IRQS]; - struct pci_dev *current; + struct pci_dev *curr; }; typedef struct irqpda_s irqpda_t; @@ -128,7 +128,7 @@ * Check if given a compact node id the corresponding node has all the * cpus disabled. */ -#define is_headless_node(cnode) (!node_to_cpumask(cnode)) +#define is_headless_node(cnode) (!any_online_cpu(node_to_cpumask(cnode))) /* * Check if given a node vertex handle the corresponding node has all the diff -Nru a/include/asm-ia64/sn/pci/pcibr_private.h b/include/asm-ia64/sn/pci/pcibr_private.h --- a/include/asm-ia64/sn/pci/pcibr_private.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/sn/pci/pcibr_private.h Fri Sep 19 00:39:53 2003 @@ -15,11 +15,9 @@ * should ever peek into this file. */ -#include #include #include #include -#include /* * convenience typedefs diff -Nru a/include/asm-ia64/sn/pci/pciio.h b/include/asm-ia64/sn/pci/pciio.h --- a/include/asm-ia64/sn/pci/pciio.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/sn/pci/pciio.h Fri Sep 19 00:39:53 2003 @@ -695,5 +695,39 @@ extern int pciio_error_handler(vertex_hdl_t, int, ioerror_mode_t, ioerror_t *); extern int pciio_dma_enabled(vertex_hdl_t); +/** + * sn_pci_set_vchan - Set the requested Virtual Channel bits into the mapped DMA + * address. + * @pci_dev: pci device pointer + * @addr: mapped dma address + * @vchan: Virtual Channel to use 0 or 1. + * + * Set the Virtual Channel bit in the mapped dma address. + */ + +static inline int +sn_pci_set_vchan(struct pci_dev *pci_dev, + dma_addr_t *addr, + int vchan) +{ + if (vchan > 1) { + return -1; + } + + if (!(*addr >> 32)) /* Using a mask here would be cleaner */ + return 0; /* but this generates better code */ + + if (vchan == 1) { + /* Set Bit 57 */ + *addr |= (1UL << 57); + } + else { + /* Clear Bit 57 */ + *addr &= ~(1UL << 57); + } + + return 0; +} + #endif /* C or C++ */ #endif /* _ASM_SN_PCI_PCIIO_H */ diff -Nru a/include/asm-ia64/sn/router.h b/include/asm-ia64/sn/router.h --- a/include/asm-ia64/sn/router.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/sn/router.h Fri Sep 19 00:39:53 2003 @@ -1,5 +1,4 @@ - -/* $Id$ +/* $id$ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -19,7 +18,6 @@ #ifndef __ASSEMBLY__ -#include #include #include #include @@ -31,23 +29,19 @@ #define MAX_ROUTER_PATH 80 #define ROUTER_REG_CAST (volatile router_reg_t *) -#define PS_UINT_CAST (__psunsigned_t) -#define UINT64_CAST (uint64_t) typedef signed char port_no_t; /* Type for router port number */ #else #define ROUTERREG_CAST -#define PS_UINT_CAST -#define UINT64_CAST #endif /* __ASSEMBLY__ */ -#define MAX_ROUTER_PORTS (8) /* Max. number of ports on a router */ +#define MAX_ROUTER_PORTS 8 /* Max. number of ports on a router */ #define ALL_PORTS ((1 << MAX_ROUTER_PORTS) - 1) /* for 0 based references */ -#define PORT_INVALID (-1) /* Invalid port number */ +#define PORT_INVALID -1 /* Invalid port number */ #define IS_META(_rp) ((_rp)->flags & PCFG_ROUTER_META) @@ -126,24 +120,24 @@ */ #define RSRI_INPORT_SHFT 52 -#define RSRI_INPORT_MASK (UINT64_CAST 0xf << 52) +#define RSRI_INPORT_MASK (0xfUL << 52) #define RSRI_LINKWORKING_BIT(_L) (35 + 2 * (_L)) -#define RSRI_LINKWORKING(_L) (UINT64_CAST 1 << (35 + 2 * (_L))) -#define RSRI_LINKRESETFAIL(_L) (UINT64_CAST 1 << (34 + 2 * (_L))) +#define RSRI_LINKWORKING(_L) (1UL << (35 + 2 * (_L))) +#define RSRI_LINKRESETFAIL(_L) (1UL << (34 + 2 * (_L))) #define RSRI_LSTAT_SHFT(_L) (34 + 2 * (_L)) -#define RSRI_LSTAT_MASK(_L) (UINT64_CAST 0x3 << 34 + 2 * (_L)) -#define RSRI_LOCALSBERROR (UINT64_CAST 1 << 35) -#define RSRI_LOCALSTUCK (UINT64_CAST 1 << 34) -#define RSRI_LOCALBADVEC (UINT64_CAST 1 << 33) -#define RSRI_LOCALTAILERR (UINT64_CAST 1 << 32) +#define RSRI_LSTAT_MASK(_L) (0x3UL << 34 + 2 * (_L)) +#define RSRI_LOCALSBERROR (1UL << 35) +#define RSRI_LOCALSTUCK (1UL << 34) +#define RSRI_LOCALBADVEC (1UL << 33) +#define RSRI_LOCALTAILERR (1UL << 32) #define RSRI_LOCAL_SHFT 32 -#define RSRI_LOCAL_MASK (UINT64_CAST 0xf << 32) +#define RSRI_LOCAL_MASK (0xfUL << 32) #define RSRI_CHIPREV_SHFT 28 -#define RSRI_CHIPREV_MASK (UINT64_CAST 0xf << 28) +#define RSRI_CHIPREV_MASK (0xfUL << 28) #define RSRI_CHIPID_SHFT 12 -#define RSRI_CHIPID_MASK (UINT64_CAST 0xffff << 12) +#define RSRI_CHIPID_MASK (0xffffUL << 12) #define RSRI_MFGID_SHFT 1 -#define RSRI_MFGID_MASK (UINT64_CAST 0x7ff << 1) +#define RSRI_MFGID_MASK (0x7ffUL << 1) #define RSRI_LSTAT_WENTDOWN 0 #define RSRI_LSTAT_RESETFAIL 1 @@ -154,38 +148,38 @@ * RR_PORT_RESET mask definitions */ -#define RPRESET_WARM (UINT64_CAST 1 << 9) -#define RPRESET_LINK(_L) (UINT64_CAST 1 << (_L)) -#define RPRESET_LOCAL (UINT64_CAST 1) +#define RPRESET_WARM (1UL << 9) +#define RPRESET_LINK(_L) (1UL << (_L)) +#define RPRESET_LOCAL 1UL /* * RR_PROT_CONF mask and shift definitions */ #define RPCONF_DIRCMPDIS_SHFT 13 -#define RPCONF_DIRCMPDIS_MASK (UINT64_CAST 1 << 13) -#define RPCONF_FORCELOCAL (UINT64_CAST 1 << 12) +#define RPCONF_DIRCMPDIS_MASK (1UL << 13) +#define RPCONF_FORCELOCAL (1UL << 12) #define RPCONF_FLOCAL_SHFT 12 #define RPCONF_METAID_SHFT 8 -#define RPCONF_METAID_MASK (UINT64_CAST 0xf << 8) -#define RPCONF_RESETOK(_L) (UINT64_CAST 1 << ((_L) - 1)) +#define RPCONF_METAID_MASK (0xfUL << 8) +#define RPCONF_RESETOK(_L) (1UL << ((_L) - 1)) /* * RR_GLOBAL_PORT_DEF mask and shift definitions */ #define RGPD_MGLBLNHBR_ID_SHFT 12 /* -global neighbor ID */ -#define RGPD_MGLBLNHBR_ID_MASK (UINT64_CAST 0xf << 12) +#define RGPD_MGLBLNHBR_ID_MASK (0xfUL << 12) #define RGPD_MGLBLNHBR_VLD_SHFT 11 /* -global neighbor Valid */ -#define RGPD_MGLBLNHBR_VLD_MASK (UINT64_CAST 0x1 << 11) +#define RGPD_MGLBLNHBR_VLD_MASK (0x1UL << 11) #define RGPD_MGLBLPORT_SHFT 8 /* -global neighbor Port */ -#define RGPD_MGLBLPORT_MASK (UINT64_CAST 0x7 << 8) +#define RGPD_MGLBLPORT_MASK (0x7UL << 8) #define RGPD_PGLBLNHBR_ID_SHFT 4 /* +global neighbor ID */ -#define RGPD_PGLBLNHBR_ID_MASK (UINT64_CAST 0xf << 4) +#define RGPD_PGLBLNHBR_ID_MASK (0xfUL << 4) #define RGPD_PGLBLNHBR_VLD_SHFT 3 /* +global neighbor Valid */ -#define RGPD_PGLBLNHBR_VLD_MASK (UINT64_CAST 0x1 << 3) +#define RGPD_PGLBLNHBR_VLD_MASK (0x1UL << 3) #define RGPD_PGLBLPORT_SHFT 0 /* +global neighbor Port */ -#define RGPD_PGLBLPORT_MASK (UINT64_CAST 0x7 << 0) +#define RGPD_PGLBLPORT_MASK (0x7UL << 0) #define GLBL_PARMS_REGS 2 /* Two Global Parms registers */ @@ -194,95 +188,95 @@ */ #define RGPARM0_ARB_VALUE_SHFT 54 /* Local Block Arbitration State */ -#define RGPARM0_ARB_VALUE_MASK (UINT64_CAST 0x7 << 54) +#define RGPARM0_ARB_VALUE_MASK (0x7UL << 54) #define RGPARM0_ROTATEARB_SHFT 53 /* Rotate Local Block Arbitration */ -#define RGPARM0_ROTATEARB_MASK (UINT64_CAST 0x1 << 53) +#define RGPARM0_ROTATEARB_MASK (1UL << 53) #define RGPARM0_FAIREN_SHFT 52 /* Fairness logic Enable */ -#define RGPARM0_FAIREN_MASK (UINT64_CAST 0x1 << 52) +#define RGPARM0_FAIREN_MASK (1UL << 52) #define RGPARM0_LOCGNTTO_SHFT 40 /* Local grant timeout */ -#define RGPARM0_LOCGNTTO_MASK (UINT64_CAST 0xfff << 40) +#define RGPARM0_LOCGNTTO_MASK (0xfffUL << 40) #define RGPARM0_DATELINE_SHFT 38 /* Dateline crossing router */ -#define RGPARM0_DATELINE_MASK (UINT64_CAST 0x1 << 38) +#define RGPARM0_DATELINE_MASK (1UL << 38) #define RGPARM0_MAXRETRY_SHFT 28 /* Max retry count */ -#define RGPARM0_MAXRETRY_MASK (UINT64_CAST 0x3ff << 28) +#define RGPARM0_MAXRETRY_MASK (0x3ffUL << 28) #define RGPARM0_URGWRAP_SHFT 20 /* Urgent wrap */ -#define RGPARM0_URGWRAP_MASK (UINT64_CAST 0xff << 20) +#define RGPARM0_URGWRAP_MASK (0xffUL << 20) #define RGPARM0_DEADLKTO_SHFT 16 /* Deadlock timeout */ -#define RGPARM0_DEADLKTO_MASK (UINT64_CAST 0xf << 16) +#define RGPARM0_DEADLKTO_MASK (0xfUL << 16) #define RGPARM0_URGVAL_SHFT 12 /* Urgent value */ -#define RGPARM0_URGVAL_MASK (UINT64_CAST 0xf << 12) +#define RGPARM0_URGVAL_MASK (0xfUL << 12) #define RGPARM0_VCHSELEN_SHFT 11 /* VCH_SEL_EN */ -#define RGPARM0_VCHSELEN_MASK (UINT64_CAST 0x1 << 11) +#define RGPARM0_VCHSELEN_MASK (1UL << 11) #define RGPARM0_LOCURGTO_SHFT 9 /* Local urgent timeout */ -#define RGPARM0_LOCURGTO_MASK (UINT64_CAST 0x3 << 9) +#define RGPARM0_LOCURGTO_MASK (0x3UL << 9) #define RGPARM0_TAILVAL_SHFT 5 /* Tail value */ -#define RGPARM0_TAILVAL_MASK (UINT64_CAST 0xf << 5) +#define RGPARM0_TAILVAL_MASK (0xfUL << 5) #define RGPARM0_CLOCK_SHFT 1 /* Global clock select */ -#define RGPARM0_CLOCK_MASK (UINT64_CAST 0xf << 1) +#define RGPARM0_CLOCK_MASK (0xfUL << 1) #define RGPARM0_BYPEN_SHFT 0 -#define RGPARM0_BYPEN_MASK (UINT64_CAST 1) /* Bypass enable */ +#define RGPARM0_BYPEN_MASK 1UL /* Bypass enable */ /* * RR_GLOBAL_PARMS1 shift and mask definitions */ #define RGPARM1_TTOWRAP_SHFT 12 /* Tail timeout wrap */ -#define RGPARM1_TTOWRAP_MASK (UINT64_CAST 0xfffff << 12) +#define RGPARM1_TTOWRAP_MASK (0xfffffUL << 12) #define RGPARM1_AGERATE_SHFT 8 /* Age rate */ -#define RGPARM1_AGERATE_MASK (UINT64_CAST 0xf << 8) +#define RGPARM1_AGERATE_MASK (0xfUL << 8) #define RGPARM1_JSWSTAT_SHFT 0 /* JTAG Sw Register bits */ -#define RGPARM1_JSWSTAT_MASK (UINT64_CAST 0xff << 0) +#define RGPARM1_JSWSTAT_MASK (0xffUL << 0) /* * RR_DIAG_PARMS mask and shift definitions */ -#define RDPARM_ABSHISTOGRAM (UINT64_CAST 1 << 17) /* Absolute histgrm */ -#define RDPARM_DEADLOCKRESET (UINT64_CAST 1 << 16) /* Reset on deadlck */ -#define RDPARM_DISABLE(_L) (UINT64_CAST 1 << ((_L) + 7)) -#define RDPARM_SENDERROR(_L) (UINT64_CAST 1 << ((_L) - 1)) +#define RDPARM_ABSHISTOGRAM (1UL << 17) /* Absolute histgrm */ +#define RDPARM_DEADLOCKRESET (1UL << 16) /* Reset on deadlck */ +#define RDPARM_DISABLE(_L) (1UL << ((_L) + 7)) +#define RDPARM_SENDERROR(_L) (1UL << ((_L) - 1)) /* * RR_DEBUG_ADDR mask and shift definitions */ #define RDA_DATA_SHFT 10 /* Observed debug data */ -#define RDA_DATA_MASK (UINT64_CAST 0xffff << 10) +#define RDA_DATA_MASK (0xffffUL << 10) #define RDA_ADDR_SHFT 0 /* debug address for data */ -#define RDA_ADDR_MASK (UINT64_CAST 0x3ff << 0) +#define RDA_ADDR_MASK (0x3ffUL << 0) /* * RR_LB_TO_L2 mask and shift definitions */ #define RLBTOL2_DATA_VLD_SHFT 32 /* data is valid for JTAG controller */ -#define RLBTOL2_DATA_VLD_MASK (UINT64_CAST 0x1 << 32) +#define RLBTOL2_DATA_VLD_MASK (1UL << 32) #define RLBTOL2_DATA_SHFT 0 /* data bits for JTAG controller */ -#define RLBTOL2_DATA_MASK (UINT64_CAST 0xffffffff) +#define RLBTOL2_DATA_MASK 0xffffffffUL /* * RR_L2_TO_LB mask and shift definitions */ #define RL2TOLB_DATA_VLD_SHFT 33 /* data is valid from JTAG controller */ -#define RL2TOLB_DATA_VLD_MASK (UINT64_CAST 0x1 << 33) +#define RL2TOLB_DATA_VLD_MASK (1UL << 33) #define RL2TOLB_PARITY_SHFT 32 /* sw implemented parity for data */ -#define RL2TOLB_PARITY_MASK (UINT64_CAST 0x1 << 32) +#define RL2TOLB_PARITY_MASK (1UL << 32) #define RL2TOLB_DATA_SHFT 0 /* data bits from JTAG controller */ -#define RL2TOLB_DATA_MASK (UINT64_CAST 0xffffffff) +#define RL2TOLB_DATA_MASK 0xffffffffUL /* * RR_JBUS_CONTROL mask and shift definitions */ #define RJC_POS_BITS_SHFT 20 /* Router position bits */ -#define RJC_POS_BITS_MASK (UINT64_CAST 0xf << 20) +#define RJC_POS_BITS_MASK (0xfUL << 20) #define RJC_RD_DATA_STROBE_SHFT 16 /* count when read data is strobed in */ -#define RJC_RD_DATA_STROBE_MASK (UINT64_CAST 0xf << 16) +#define RJC_RD_DATA_STROBE_MASK (0xfUL << 16) #define RJC_WE_OE_HOLD_SHFT 8 /* time OE or WE is held */ -#define RJC_WE_OE_HOLD_MASK (UINT64_CAST 0xff << 8) +#define RJC_WE_OE_HOLD_MASK (0xffUL << 8) #define RJC_ADDR_SET_HLD_SHFT 0 /* time address driven around OE/WE */ -#define RJC_ADDR_SET_HLD_MASK (UINT64_CAST 0xff) +#define RJC_ADDR_SET_HLD_MASK 0xffUL /* * RR_SCRATCH_REGx mask and shift definitions @@ -291,58 +285,58 @@ */ #define RSCR0_BOOTED_SHFT 63 -#define RSCR0_BOOTED_MASK (UINT64_CAST 0x1 << RSCR0_BOOTED_SHFT) +#define RSCR0_BOOTED_MASK (0x1UL << RSCR0_BOOTED_SHFT) #define RSCR0_LOCALID_SHFT 56 -#define RSCR0_LOCALID_MASK (UINT64_CAST 0x7f << RSCR0_LOCALID_SHFT) +#define RSCR0_LOCALID_MASK (0x7fUL << RSCR0_LOCALID_SHFT) #define RSCR0_UNUSED_SHFT 48 -#define RSCR0_UNUSED_MASK (UINT64_CAST 0xff << RSCR0_UNUSED_SHFT) +#define RSCR0_UNUSED_MASK (0xffUL << RSCR0_UNUSED_SHFT) #define RSCR0_NIC_SHFT 0 -#define RSCR0_NIC_MASK (UINT64_CAST 0xffffffffffff) +#define RSCR0_NIC_MASK 0xffffffffffffUL #define RSCR1_MODID_SHFT 0 -#define RSCR1_MODID_MASK (UINT64_CAST 0xffff) +#define RSCR1_MODID_MASK 0xffffUL /* * RR_VECTOR_HW_BAR mask and shift definitions */ #define BAR_TX_SHFT 27 /* Barrier in trans(m)it when read */ -#define BAR_TX_MASK (UINT64_CAST 1 << BAR_TX_SHFT) +#define BAR_TX_MASK (1UL << BAR_TX_SHFT) #define BAR_VLD_SHFT 26 /* Valid Configuration */ -#define BAR_VLD_MASK (UINT64_CAST 1 << BAR_VLD_SHFT) +#define BAR_VLD_MASK (1UL << BAR_VLD_SHFT) #define BAR_SEQ_SHFT 24 /* Sequence number */ -#define BAR_SEQ_MASK (UINT64_CAST 3 << BAR_SEQ_SHFT) +#define BAR_SEQ_MASK (3UL << BAR_SEQ_SHFT) #define BAR_LEAFSTATE_SHFT 18 /* Leaf State */ -#define BAR_LEAFSTATE_MASK (UINT64_CAST 0x3f << BAR_LEAFSTATE_SHFT) +#define BAR_LEAFSTATE_MASK (0x3fUL << BAR_LEAFSTATE_SHFT) #define BAR_PARENT_SHFT 14 /* Parent Port */ -#define BAR_PARENT_MASK (UINT64_CAST 0xf << BAR_PARENT_SHFT) +#define BAR_PARENT_MASK (0xfUL << BAR_PARENT_SHFT) #define BAR_CHILDREN_SHFT 6 /* Child Select port bits */ -#define BAR_CHILDREN_MASK (UINT64_CAST 0xff << BAR_CHILDREN_SHFT) +#define BAR_CHILDREN_MASK (0xffUL << BAR_CHILDREN_SHFT) #define BAR_LEAFCOUNT_SHFT 0 /* Leaf Count to trigger parent */ -#define BAR_LEAFCOUNT_MASK (UINT64_CAST 0x3f) +#define BAR_LEAFCOUNT_MASK 0x3fUL /* * RR_PORT_PARMS(_L) mask and shift definitions */ #define RPPARM_MIPRESETEN_SHFT 29 /* Message In Progress reset enable */ -#define RPPARM_MIPRESETEN_MASK (UINT64_CAST 0x1 << 29) +#define RPPARM_MIPRESETEN_MASK (0x1UL << 29) #define RPPARM_UBAREN_SHFT 28 /* Enable user barrier requests */ -#define RPPARM_UBAREN_MASK (UINT64_CAST 0x1 << 28) +#define RPPARM_UBAREN_MASK (0x1UL << 28) #define RPPARM_OUTPDTO_SHFT 24 /* Output Port Deadlock TO value */ -#define RPPARM_OUTPDTO_MASK (UINT64_CAST 0xf << 24) +#define RPPARM_OUTPDTO_MASK (0xfUL << 24) #define RPPARM_PORTMATE_SHFT 21 /* Port Mate for the port */ -#define RPPARM_PORTMATE_MASK (UINT64_CAST 0x7 << 21) +#define RPPARM_PORTMATE_MASK (0x7UL << 21) #define RPPARM_HISTEN_SHFT 20 /* Histogram counter enable */ -#define RPPARM_HISTEN_MASK (UINT64_CAST 0x1 << 20) +#define RPPARM_HISTEN_MASK (0x1UL << 20) #define RPPARM_HISTSEL_SHFT 18 -#define RPPARM_HISTSEL_MASK (UINT64_CAST 0x3 << 18) +#define RPPARM_HISTSEL_MASK (0x3UL << 18) #define RPPARM_DAMQHS_SHFT 16 -#define RPPARM_DAMQHS_MASK (UINT64_CAST 0x3 << 16) +#define RPPARM_DAMQHS_MASK (0x3UL << 16) #define RPPARM_NULLTO_SHFT 10 -#define RPPARM_NULLTO_MASK (UINT64_CAST 0x3f << 10) +#define RPPARM_NULLTO_MASK (0x3fUL << 10) #define RPPARM_MAXBURST_SHFT 0 -#define RPPARM_MAXBURST_MASK (UINT64_CAST 0x3ff) +#define RPPARM_MAXBURST_MASK 0x3ffUL /* * NOTE: Normally the kernel tracks only UTILIZATION statistics. @@ -356,23 +350,23 @@ /* * RR_STATUS_ERROR(_L) and RR_ERROR_CLEAR(_L) mask and shift definitions */ -#define RSERR_POWERNOK (UINT64_CAST 1 << 38) -#define RSERR_PORT_DEADLOCK (UINT64_CAST 1 << 37) -#define RSERR_WARMRESET (UINT64_CAST 1 << 36) -#define RSERR_LINKRESET (UINT64_CAST 1 << 35) -#define RSERR_RETRYTIMEOUT (UINT64_CAST 1 << 34) -#define RSERR_FIFOOVERFLOW (UINT64_CAST 1 << 33) -#define RSERR_ILLEGALPORT (UINT64_CAST 1 << 32) +#define RSERR_POWERNOK (1UL << 38) +#define RSERR_PORT_DEADLOCK (1UL << 37) +#define RSERR_WARMRESET (1UL << 36) +#define RSERR_LINKRESET (1UL << 35) +#define RSERR_RETRYTIMEOUT (1UL << 34) +#define RSERR_FIFOOVERFLOW (1UL << 33) +#define RSERR_ILLEGALPORT (1UL << 32) #define RSERR_DEADLOCKTO_SHFT 28 -#define RSERR_DEADLOCKTO_MASK (UINT64_CAST 0xf << 28) +#define RSERR_DEADLOCKTO_MASK (0xfUL << 28) #define RSERR_RECVTAILTO_SHFT 24 -#define RSERR_RECVTAILTO_MASK (UINT64_CAST 0xf << 24) +#define RSERR_RECVTAILTO_MASK (0xfUL << 24) #define RSERR_RETRYCNT_SHFT 16 -#define RSERR_RETRYCNT_MASK (UINT64_CAST 0xff << 16) +#define RSERR_RETRYCNT_MASK (0xffUL << 16) #define RSERR_CBERRCNT_SHFT 8 -#define RSERR_CBERRCNT_MASK (UINT64_CAST 0xff << 8) +#define RSERR_CBERRCNT_MASK (0xffUL << 8) #define RSERR_SNERRCNT_SHFT 0 -#define RSERR_SNERRCNT_MASK (UINT64_CAST 0xff << 0) +#define RSERR_SNERRCNT_MASK (0xffUL << 0) #define PORT_STATUS_UP (1 << 0) /* Router link up */ @@ -393,10 +387,10 @@ * why the router link * went down */ -#define PROBE_RESULT_BAD (-1) /* Set if any of the router +#define PROBE_RESULT_BAD -1 /* Set if any of the router * links failed after reset */ -#define PROBE_RESULT_GOOD (0) /* Set if all the router links +#define PROBE_RESULT_GOOD 0 /* Set if all the router links * which came out of reset * are up */ @@ -528,23 +522,6 @@ #define RIP_PROMLOG 2 /* Router info in promlog */ #define RIP_CONSOLE 4 /* Router info on console */ -#define ROUTER_INFO_PRINT(_rip,_where) (_rip->ri_print |= _where) - /* Set the field used to check if a - * router info can be printed - */ -#define IS_ROUTER_INFO_PRINTED(_rip,_where) \ - (_rip->ri_print & _where) - /* Was the router info printed to - * the given location (_where) ? - * Mainly used to prevent duplicate - * router error states. - */ -#define ROUTER_INFO_LOCK(_rip,_s) _s = mutex_spinlock(&(_rip->ri_lock)) - /* Take the lock on router info - * to gain exclusive access - */ -#define ROUTER_INFO_UNLOCK(_rip,_s) mutex_spinunlock(&(_rip->ri_lock),_s) - /* Release the lock on router info */ /* * Router info hanging in the nodepda */ @@ -623,7 +600,7 @@ */ #define RHIST_BUCKET_SHFT(_x) (32 * ((_x) & 0x1)) -#define RHIST_BUCKET_MASK(_x) (UINT64_CAST 0xffffffff << RHIST_BUCKET_SHFT((_x) & 0x1)) +#define RHIST_BUCKET_MASK(_x) (0xffffffffUL << RHIST_BUCKET_SHFT((_x) & 0x1)) #define RHIST_GET_BUCKET(_x, _reg) \ ((RHIST_BUCKET_MASK(_x) & ((_reg)[(_x) >> 1])) >> RHIST_BUCKET_SHFT(_x)) @@ -631,7 +608,7 @@ * RR_RESET_MASK(_L) mask and shift definitions */ -#define RRM_RESETOK(_L) (UINT64_CAST 1 << ((_L) - 1)) +#define RRM_RESETOK(_L) (1UL << ((_L) - 1)) #define RRM_RESETOK_ALL ALL_PORTS /* @@ -639,7 +616,7 @@ */ #define RTABLE_SHFT(_L) (4 * ((_L) - 1)) -#define RTABLE_MASK(_L) (UINT64_CAST 0x7 << RTABLE_SHFT(_L)) +#define RTABLE_MASK(_L) (0x7UL << RTABLE_SHFT(_L)) #define ROUTERINFO_STKSZ 4096 diff -Nru a/include/asm-ia64/sn/sn2/intr.h b/include/asm-ia64/sn/sn2/intr.h --- a/include/asm-ia64/sn/sn2/intr.h Fri Sep 19 00:39:54 2003 +++ b/include/asm-ia64/sn/sn2/intr.h Fri Sep 19 00:39:54 2003 @@ -17,10 +17,11 @@ #define SGI_II_ERROR (0x31) #define SGI_XBOW_ERROR (0x32) #define SGI_PCIBR_ERROR (0x33) +#define SGI_ACPI_SCI_INT (0x34) #define SGI_XPC_NOTIFY (0xe7) #define IA64_SN2_FIRST_DEVICE_VECTOR (0x34) -#define IA64_SN2_LAST_DEVICE_VECTOR (0xe6) +#define IA64_SN2_LAST_DEVICE_VECTOR (0xe7) #define SN2_IRQ_RESERVED (0x1) #define SN2_IRQ_CONNECTED (0x2) diff -Nru a/include/asm-ia64/sn/sn2/shub.h b/include/asm-ia64/sn/sn2/shub.h --- a/include/asm-ia64/sn/sn2/shub.h Fri Sep 19 00:39:54 2003 +++ b/include/asm-ia64/sn/sn2/shub.h Fri Sep 19 00:39:54 2003 @@ -11,13 +11,6 @@ #ifndef _ASM_IA64_SN_SN2_SHUB_H #define _ASM_IA64_SN_SN2_SHUB_H -#include /* shub mmr addresses and formats */ -#include -#include -#ifndef __ASSEMBLY__ -#include /* shub mmr struct defines */ -#endif - /* * Junk Bus Address Space * The junk bus is used to access the PROM, LED's, and UART. It's diff -Nru a/include/asm-ia64/sn/sn2/shub_mmr_t.h b/include/asm-ia64/sn/sn2/shub_mmr_t.h --- a/include/asm-ia64/sn/sn2/shub_mmr_t.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/sn/sn2/shub_mmr_t.h Fri Sep 19 00:39:53 2003 @@ -7,8 +7,6 @@ * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. */ - - #ifndef _ASM_IA64_SN_SN2_SHUB_MMR_T_H #define _ASM_IA64_SN_SN2_SHUB_MMR_T_H @@ -19,7 +17,6 @@ /* FSB BINIT# Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_fsb_binit_control_u { mmr_t sh_fsb_binit_control_regval; struct { @@ -27,22 +24,12 @@ mmr_t reserved_0 : 63; } sh_fsb_binit_control_s; } sh_fsb_binit_control_u_t; -#else -typedef union sh_fsb_binit_control_u { - mmr_t sh_fsb_binit_control_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t binit : 1; - } sh_fsb_binit_control_s; -} sh_fsb_binit_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_FSB_RESET_CONTROL" */ /* FSB Reset Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_fsb_reset_control_u { mmr_t sh_fsb_reset_control_regval; struct { @@ -50,22 +37,12 @@ mmr_t reserved_0 : 63; } sh_fsb_reset_control_s; } sh_fsb_reset_control_u_t; -#else -typedef union sh_fsb_reset_control_u { - mmr_t sh_fsb_reset_control_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t reset : 1; - } sh_fsb_reset_control_s; -} sh_fsb_reset_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_FSB_SYSTEM_AGENT_CONFIG" */ /* FSB System Agent Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_fsb_system_agent_config_u { mmr_t sh_fsb_system_agent_config_regval; struct { @@ -88,37 +65,12 @@ mmr_t reserved_3 : 18; } sh_fsb_system_agent_config_s; } sh_fsb_system_agent_config_u_t; -#else -typedef union sh_fsb_system_agent_config_u { - mmr_t sh_fsb_system_agent_config_regval; - struct { - mmr_t reserved_3 : 18; - mmr_t binit_event_enables : 14; - mmr_t reserved_2 : 7; - mmr_t serialize_fsb_en : 1; - mmr_t tdot : 1; - mmr_t reserved_1 : 4; - mmr_t inta_trans_rsp : 1; - mmr_t xtpr_trans_rsp : 1; - mmr_t io_trans_rsp : 1; - mmr_t inta_rsp_data : 8; - mmr_t short_hang_en : 1; - mmr_t bnr_throttling_en : 1; - mmr_t binit_assert_en : 1; - mmr_t berr_sampling_en : 1; - mmr_t berr_assert_en : 1; - mmr_t reserved_0 : 2; - mmr_t rcnt_scnt_en : 1; - } sh_fsb_system_agent_config_s; -} sh_fsb_system_agent_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_FSB_VGA_REMAP" */ /* FSB VGA Address Space Remap */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_fsb_vga_remap_u { mmr_t sh_fsb_vga_remap_regval; struct { @@ -131,27 +83,12 @@ mmr_t reserved_2 : 1; } sh_fsb_vga_remap_s; } sh_fsb_vga_remap_u_t; -#else -typedef union sh_fsb_vga_remap_u { - mmr_t sh_fsb_vga_remap_regval; - struct { - mmr_t reserved_2 : 1; - mmr_t vga_remapping_enabled : 1; - mmr_t reserved_1 : 13; - mmr_t nid : 11; - mmr_t asid : 2; - mmr_t offset : 19; - mmr_t reserved_0 : 17; - } sh_fsb_vga_remap_s; -} sh_fsb_vga_remap_u_t; -#endif /* ==================================================================== */ /* Register "SH_FSB_RESET_STATUS" */ /* FSB Reset Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_fsb_reset_status_u { mmr_t sh_fsb_reset_status_regval; struct { @@ -159,22 +96,12 @@ mmr_t reserved_0 : 63; } sh_fsb_reset_status_s; } sh_fsb_reset_status_u_t; -#else -typedef union sh_fsb_reset_status_u { - mmr_t sh_fsb_reset_status_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t reset_in_progress : 1; - } sh_fsb_reset_status_s; -} sh_fsb_reset_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_FSB_SYMMETRIC_AGENT_STATUS" */ /* FSB Symmetric Agent Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_fsb_symmetric_agent_status_u { mmr_t sh_fsb_symmetric_agent_status_regval; struct { @@ -184,24 +111,12 @@ mmr_t reserved_0 : 61; } sh_fsb_symmetric_agent_status_s; } sh_fsb_symmetric_agent_status_u_t; -#else -typedef union sh_fsb_symmetric_agent_status_u { - mmr_t sh_fsb_symmetric_agent_status_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t cpus_ready : 1; - mmr_t cpu_1_active : 1; - mmr_t cpu_0_active : 1; - } sh_fsb_symmetric_agent_status_s; -} sh_fsb_symmetric_agent_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_CREDIT_COUNT_0" */ /* Graphics-write Credit Count for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_credit_count_0_u { mmr_t sh_gfx_credit_count_0_regval; struct { @@ -210,23 +125,12 @@ mmr_t reset_gfx_state : 1; } sh_gfx_credit_count_0_s; } sh_gfx_credit_count_0_u_t; -#else -typedef union sh_gfx_credit_count_0_u { - mmr_t sh_gfx_credit_count_0_regval; - struct { - mmr_t reset_gfx_state : 1; - mmr_t reserved_0 : 43; - mmr_t count : 20; - } sh_gfx_credit_count_0_s; -} sh_gfx_credit_count_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_CREDIT_COUNT_1" */ /* Graphics-write Credit Count for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_credit_count_1_u { mmr_t sh_gfx_credit_count_1_regval; struct { @@ -235,23 +139,12 @@ mmr_t reset_gfx_state : 1; } sh_gfx_credit_count_1_s; } sh_gfx_credit_count_1_u_t; -#else -typedef union sh_gfx_credit_count_1_u { - mmr_t sh_gfx_credit_count_1_regval; - struct { - mmr_t reset_gfx_state : 1; - mmr_t reserved_0 : 43; - mmr_t count : 20; - } sh_gfx_credit_count_1_s; -} sh_gfx_credit_count_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_MODE_CNTRL_0" */ /* Graphics credit mode amd message ordering for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_mode_cntrl_0_u { mmr_t sh_gfx_mode_cntrl_0_regval; struct { @@ -261,24 +154,12 @@ mmr_t reserved_0 : 61; } sh_gfx_mode_cntrl_0_s; } sh_gfx_mode_cntrl_0_u_t; -#else -typedef union sh_gfx_mode_cntrl_0_u { - mmr_t sh_gfx_mode_cntrl_0_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t relaxed_ordering : 1; - mmr_t mixed_mode_credits : 1; - mmr_t dword_credits : 1; - } sh_gfx_mode_cntrl_0_s; -} sh_gfx_mode_cntrl_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_MODE_CNTRL_1" */ /* Graphics credit mode amd message ordering for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_mode_cntrl_1_u { mmr_t sh_gfx_mode_cntrl_1_regval; struct { @@ -288,24 +169,12 @@ mmr_t reserved_0 : 61; } sh_gfx_mode_cntrl_1_s; } sh_gfx_mode_cntrl_1_u_t; -#else -typedef union sh_gfx_mode_cntrl_1_u { - mmr_t sh_gfx_mode_cntrl_1_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t relaxed_ordering : 1; - mmr_t mixed_mode_credits : 1; - mmr_t dword_credits : 1; - } sh_gfx_mode_cntrl_1_s; -} sh_gfx_mode_cntrl_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_SKID_CREDIT_COUNT_0" */ /* Graphics-write Skid Credit Count for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_skid_credit_count_0_u { mmr_t sh_gfx_skid_credit_count_0_regval; struct { @@ -313,22 +182,12 @@ mmr_t reserved_0 : 44; } sh_gfx_skid_credit_count_0_s; } sh_gfx_skid_credit_count_0_u_t; -#else -typedef union sh_gfx_skid_credit_count_0_u { - mmr_t sh_gfx_skid_credit_count_0_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t skid : 20; - } sh_gfx_skid_credit_count_0_s; -} sh_gfx_skid_credit_count_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_SKID_CREDIT_COUNT_1" */ /* Graphics-write Skid Credit Count for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_skid_credit_count_1_u { mmr_t sh_gfx_skid_credit_count_1_regval; struct { @@ -336,22 +195,12 @@ mmr_t reserved_0 : 44; } sh_gfx_skid_credit_count_1_s; } sh_gfx_skid_credit_count_1_u_t; -#else -typedef union sh_gfx_skid_credit_count_1_u { - mmr_t sh_gfx_skid_credit_count_1_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t skid : 20; - } sh_gfx_skid_credit_count_1_s; -} sh_gfx_skid_credit_count_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_STALL_LIMIT_0" */ /* Graphics-write Stall Limit for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_stall_limit_0_u { mmr_t sh_gfx_stall_limit_0_regval; struct { @@ -359,22 +208,12 @@ mmr_t reserved_0 : 38; } sh_gfx_stall_limit_0_s; } sh_gfx_stall_limit_0_u_t; -#else -typedef union sh_gfx_stall_limit_0_u { - mmr_t sh_gfx_stall_limit_0_regval; - struct { - mmr_t reserved_0 : 38; - mmr_t limit : 26; - } sh_gfx_stall_limit_0_s; -} sh_gfx_stall_limit_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_STALL_LIMIT_1" */ /* Graphics-write Stall Limit for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_stall_limit_1_u { mmr_t sh_gfx_stall_limit_1_regval; struct { @@ -382,22 +221,12 @@ mmr_t reserved_0 : 38; } sh_gfx_stall_limit_1_s; } sh_gfx_stall_limit_1_u_t; -#else -typedef union sh_gfx_stall_limit_1_u { - mmr_t sh_gfx_stall_limit_1_regval; - struct { - mmr_t reserved_0 : 38; - mmr_t limit : 26; - } sh_gfx_stall_limit_1_s; -} sh_gfx_stall_limit_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_STALL_TIMER_0" */ /* Graphics-write Stall Timer for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_stall_timer_0_u { mmr_t sh_gfx_stall_timer_0_regval; struct { @@ -405,22 +234,12 @@ mmr_t reserved_0 : 38; } sh_gfx_stall_timer_0_s; } sh_gfx_stall_timer_0_u_t; -#else -typedef union sh_gfx_stall_timer_0_u { - mmr_t sh_gfx_stall_timer_0_regval; - struct { - mmr_t reserved_0 : 38; - mmr_t timer_value : 26; - } sh_gfx_stall_timer_0_s; -} sh_gfx_stall_timer_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_STALL_TIMER_1" */ /* Graphics-write Stall Timer for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_stall_timer_1_u { mmr_t sh_gfx_stall_timer_1_regval; struct { @@ -428,22 +247,12 @@ mmr_t reserved_0 : 38; } sh_gfx_stall_timer_1_s; } sh_gfx_stall_timer_1_u_t; -#else -typedef union sh_gfx_stall_timer_1_u { - mmr_t sh_gfx_stall_timer_1_regval; - struct { - mmr_t reserved_0 : 38; - mmr_t timer_value : 26; - } sh_gfx_stall_timer_1_s; -} sh_gfx_stall_timer_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_WINDOW_0" */ /* Graphics-write Window for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_window_0_u { mmr_t sh_gfx_window_0_regval; struct { @@ -453,24 +262,12 @@ mmr_t gfx_window_en : 1; } sh_gfx_window_0_s; } sh_gfx_window_0_u_t; -#else -typedef union sh_gfx_window_0_u { - mmr_t sh_gfx_window_0_regval; - struct { - mmr_t gfx_window_en : 1; - mmr_t reserved_1 : 27; - mmr_t base_addr : 12; - mmr_t reserved_0 : 24; - } sh_gfx_window_0_s; -} sh_gfx_window_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_WINDOW_1" */ /* Graphics-write Window for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_window_1_u { mmr_t sh_gfx_window_1_regval; struct { @@ -480,24 +277,12 @@ mmr_t gfx_window_en : 1; } sh_gfx_window_1_s; } sh_gfx_window_1_u_t; -#else -typedef union sh_gfx_window_1_u { - mmr_t sh_gfx_window_1_regval; - struct { - mmr_t gfx_window_en : 1; - mmr_t reserved_1 : 27; - mmr_t base_addr : 12; - mmr_t reserved_0 : 24; - } sh_gfx_window_1_s; -} sh_gfx_window_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0" */ /* Graphics-write Interrupt Limit for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_interrupt_timer_limit_0_u { mmr_t sh_gfx_interrupt_timer_limit_0_regval; struct { @@ -505,22 +290,12 @@ mmr_t reserved_0 : 56; } sh_gfx_interrupt_timer_limit_0_s; } sh_gfx_interrupt_timer_limit_0_u_t; -#else -typedef union sh_gfx_interrupt_timer_limit_0_u { - mmr_t sh_gfx_interrupt_timer_limit_0_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t interrupt_timer_limit : 8; - } sh_gfx_interrupt_timer_limit_0_s; -} sh_gfx_interrupt_timer_limit_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1" */ /* Graphics-write Interrupt Limit for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_interrupt_timer_limit_1_u { mmr_t sh_gfx_interrupt_timer_limit_1_regval; struct { @@ -528,22 +303,12 @@ mmr_t reserved_0 : 56; } sh_gfx_interrupt_timer_limit_1_s; } sh_gfx_interrupt_timer_limit_1_u_t; -#else -typedef union sh_gfx_interrupt_timer_limit_1_u { - mmr_t sh_gfx_interrupt_timer_limit_1_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t interrupt_timer_limit : 8; - } sh_gfx_interrupt_timer_limit_1_s; -} sh_gfx_interrupt_timer_limit_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_WRITE_STATUS_0" */ /* Graphics Write Status for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_write_status_0_u { mmr_t sh_gfx_write_status_0_regval; struct { @@ -552,23 +317,12 @@ mmr_t re_enable_gfx_stall : 1; } sh_gfx_write_status_0_s; } sh_gfx_write_status_0_u_t; -#else -typedef union sh_gfx_write_status_0_u { - mmr_t sh_gfx_write_status_0_regval; - struct { - mmr_t re_enable_gfx_stall : 1; - mmr_t reserved_0 : 62; - mmr_t busy : 1; - } sh_gfx_write_status_0_s; -} sh_gfx_write_status_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_GFX_WRITE_STATUS_1" */ /* Graphics Write Status for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gfx_write_status_1_u { mmr_t sh_gfx_write_status_1_regval; struct { @@ -577,23 +331,12 @@ mmr_t re_enable_gfx_stall : 1; } sh_gfx_write_status_1_s; } sh_gfx_write_status_1_u_t; -#else -typedef union sh_gfx_write_status_1_u { - mmr_t sh_gfx_write_status_1_regval; - struct { - mmr_t re_enable_gfx_stall : 1; - mmr_t reserved_0 : 62; - mmr_t busy : 1; - } sh_gfx_write_status_1_s; -} sh_gfx_write_status_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_INT0" */ /* SHub II Interrupt 0 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_int0_u { mmr_t sh_ii_int0_regval; struct { @@ -602,23 +345,12 @@ mmr_t reserved_0 : 55; } sh_ii_int0_s; } sh_ii_int0_u_t; -#else -typedef union sh_ii_int0_u { - mmr_t sh_ii_int0_regval; - struct { - mmr_t reserved_0 : 55; - mmr_t send : 1; - mmr_t idx : 8; - } sh_ii_int0_s; -} sh_ii_int0_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_INT0_CONFIG" */ /* SHub II Interrupt 0 Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_int0_config_u { mmr_t sh_ii_int0_config_regval; struct { @@ -630,26 +362,12 @@ mmr_t reserved_1 : 14; } sh_ii_int0_config_s; } sh_ii_int0_config_u_t; -#else -typedef union sh_ii_int0_config_u { - mmr_t sh_ii_int0_config_regval; - struct { - mmr_t reserved_1 : 14; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_ii_int0_config_s; -} sh_ii_int0_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_INT0_ENABLE" */ /* SHub II Interrupt 0 Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_int0_enable_u { mmr_t sh_ii_int0_enable_regval; struct { @@ -657,22 +375,12 @@ mmr_t reserved_0 : 63; } sh_ii_int0_enable_s; } sh_ii_int0_enable_u_t; -#else -typedef union sh_ii_int0_enable_u { - mmr_t sh_ii_int0_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t ii_enable : 1; - } sh_ii_int0_enable_s; -} sh_ii_int0_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_INT1" */ /* SHub II Interrupt 1 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_int1_u { mmr_t sh_ii_int1_regval; struct { @@ -681,23 +389,12 @@ mmr_t reserved_0 : 55; } sh_ii_int1_s; } sh_ii_int1_u_t; -#else -typedef union sh_ii_int1_u { - mmr_t sh_ii_int1_regval; - struct { - mmr_t reserved_0 : 55; - mmr_t send : 1; - mmr_t idx : 8; - } sh_ii_int1_s; -} sh_ii_int1_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_INT1_CONFIG" */ /* SHub II Interrupt 1 Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_int1_config_u { mmr_t sh_ii_int1_config_regval; struct { @@ -709,26 +406,12 @@ mmr_t reserved_1 : 14; } sh_ii_int1_config_s; } sh_ii_int1_config_u_t; -#else -typedef union sh_ii_int1_config_u { - mmr_t sh_ii_int1_config_regval; - struct { - mmr_t reserved_1 : 14; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_ii_int1_config_s; -} sh_ii_int1_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_INT1_ENABLE" */ /* SHub II Interrupt 1 Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_int1_enable_u { mmr_t sh_ii_int1_enable_regval; struct { @@ -736,22 +419,12 @@ mmr_t reserved_0 : 63; } sh_ii_int1_enable_s; } sh_ii_int1_enable_u_t; -#else -typedef union sh_ii_int1_enable_u { - mmr_t sh_ii_int1_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t ii_enable : 1; - } sh_ii_int1_enable_s; -} sh_ii_int1_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_INT_NODE_ID_CONFIG" */ /* SHub Interrupt Node ID Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_int_node_id_config_u { mmr_t sh_int_node_id_config_regval; struct { @@ -760,23 +433,12 @@ mmr_t reserved_0 : 52; } sh_int_node_id_config_s; } sh_int_node_id_config_u_t; -#else -typedef union sh_int_node_id_config_u { - mmr_t sh_int_node_id_config_regval; - struct { - mmr_t reserved_0 : 52; - mmr_t id_sel : 1; - mmr_t node_id : 11; - } sh_int_node_id_config_s; -} sh_int_node_id_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_IPI_INT" */ /* SHub Inter-Processor Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ipi_int_u { mmr_t sh_ipi_int_regval; struct { @@ -791,29 +453,12 @@ mmr_t send : 1; } sh_ipi_int_s; } sh_ipi_int_u_t; -#else -typedef union sh_ipi_int_u { - mmr_t sh_ipi_int_regval; - struct { - mmr_t send : 1; - mmr_t reserved_2 : 3; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_ipi_int_s; -} sh_ipi_int_u_t; -#endif /* ==================================================================== */ /* Register "SH_IPI_INT_ENABLE" */ /* SHub Inter-Processor Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ipi_int_enable_u { mmr_t sh_ipi_int_enable_regval; struct { @@ -821,22 +466,12 @@ mmr_t reserved_0 : 63; } sh_ipi_int_enable_s; } sh_ipi_int_enable_u_t; -#else -typedef union sh_ipi_int_enable_u { - mmr_t sh_ipi_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t pio_enable : 1; - } sh_ipi_int_enable_s; -} sh_ipi_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT0_CONFIG" */ /* SHub Local Interrupt 0 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int0_config_u { mmr_t sh_local_int0_config_regval; struct { @@ -850,28 +485,12 @@ mmr_t reserved_2 : 4; } sh_local_int0_config_s; } sh_local_int0_config_u_t; -#else -typedef union sh_local_int0_config_u { - mmr_t sh_local_int0_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_local_int0_config_s; -} sh_local_int0_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT0_ENABLE" */ /* SHub Local Interrupt 0 Enable */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int0_enable_u { mmr_t sh_local_int0_enable_regval; struct { @@ -894,37 +513,12 @@ mmr_t reserved_1 : 48; } sh_local_int0_enable_s; } sh_local_int0_enable_u_t; -#else -typedef union sh_local_int0_enable_u { - mmr_t sh_local_int0_enable_regval; - struct { - mmr_t reserved_1 : 48; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t reserved_0 : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_local_int0_enable_s; -} sh_local_int0_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT1_CONFIG" */ /* SHub Local Interrupt 1 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int1_config_u { mmr_t sh_local_int1_config_regval; struct { @@ -938,28 +532,12 @@ mmr_t reserved_2 : 4; } sh_local_int1_config_s; } sh_local_int1_config_u_t; -#else -typedef union sh_local_int1_config_u { - mmr_t sh_local_int1_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_local_int1_config_s; -} sh_local_int1_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT1_ENABLE" */ /* SHub Local Interrupt 1 Enable */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int1_enable_u { mmr_t sh_local_int1_enable_regval; struct { @@ -982,37 +560,12 @@ mmr_t reserved_1 : 48; } sh_local_int1_enable_s; } sh_local_int1_enable_u_t; -#else -typedef union sh_local_int1_enable_u { - mmr_t sh_local_int1_enable_regval; - struct { - mmr_t reserved_1 : 48; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t reserved_0 : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_local_int1_enable_s; -} sh_local_int1_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT2_CONFIG" */ /* SHub Local Interrupt 2 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int2_config_u { mmr_t sh_local_int2_config_regval; struct { @@ -1026,28 +579,12 @@ mmr_t reserved_2 : 4; } sh_local_int2_config_s; } sh_local_int2_config_u_t; -#else -typedef union sh_local_int2_config_u { - mmr_t sh_local_int2_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_local_int2_config_s; -} sh_local_int2_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT2_ENABLE" */ /* SHub Local Interrupt 2 Enable */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int2_enable_u { mmr_t sh_local_int2_enable_regval; struct { @@ -1070,37 +607,12 @@ mmr_t reserved_1 : 48; } sh_local_int2_enable_s; } sh_local_int2_enable_u_t; -#else -typedef union sh_local_int2_enable_u { - mmr_t sh_local_int2_enable_regval; - struct { - mmr_t reserved_1 : 48; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t reserved_0 : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_local_int2_enable_s; -} sh_local_int2_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT3_CONFIG" */ /* SHub Local Interrupt 3 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int3_config_u { mmr_t sh_local_int3_config_regval; struct { @@ -1114,28 +626,12 @@ mmr_t reserved_2 : 4; } sh_local_int3_config_s; } sh_local_int3_config_u_t; -#else -typedef union sh_local_int3_config_u { - mmr_t sh_local_int3_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_local_int3_config_s; -} sh_local_int3_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT3_ENABLE" */ /* SHub Local Interrupt 3 Enable */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int3_enable_u { mmr_t sh_local_int3_enable_regval; struct { @@ -1158,37 +654,12 @@ mmr_t reserved_1 : 48; } sh_local_int3_enable_s; } sh_local_int3_enable_u_t; -#else -typedef union sh_local_int3_enable_u { - mmr_t sh_local_int3_enable_regval; - struct { - mmr_t reserved_1 : 48; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t reserved_0 : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_local_int3_enable_s; -} sh_local_int3_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT4_CONFIG" */ /* SHub Local Interrupt 4 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int4_config_u { mmr_t sh_local_int4_config_regval; struct { @@ -1202,28 +673,12 @@ mmr_t reserved_2 : 4; } sh_local_int4_config_s; } sh_local_int4_config_u_t; -#else -typedef union sh_local_int4_config_u { - mmr_t sh_local_int4_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_local_int4_config_s; -} sh_local_int4_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT4_ENABLE" */ /* SHub Local Interrupt 4 Enable */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int4_enable_u { mmr_t sh_local_int4_enable_regval; struct { @@ -1246,37 +701,12 @@ mmr_t reserved_1 : 48; } sh_local_int4_enable_s; } sh_local_int4_enable_u_t; -#else -typedef union sh_local_int4_enable_u { - mmr_t sh_local_int4_enable_regval; - struct { - mmr_t reserved_1 : 48; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t reserved_0 : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_local_int4_enable_s; -} sh_local_int4_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT5_CONFIG" */ /* SHub Local Interrupt 5 Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int5_config_u { mmr_t sh_local_int5_config_regval; struct { @@ -1290,28 +720,12 @@ mmr_t reserved_2 : 4; } sh_local_int5_config_s; } sh_local_int5_config_u_t; -#else -typedef union sh_local_int5_config_u { - mmr_t sh_local_int5_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_local_int5_config_s; -} sh_local_int5_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_LOCAL_INT5_ENABLE" */ /* SHub Local Interrupt 5 Enable */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_local_int5_enable_u { mmr_t sh_local_int5_enable_regval; struct { @@ -1334,37 +748,12 @@ mmr_t reserved_1 : 48; } sh_local_int5_enable_s; } sh_local_int5_enable_u_t; -#else -typedef union sh_local_int5_enable_u { - mmr_t sh_local_int5_enable_regval; - struct { - mmr_t reserved_1 : 48; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t reserved_0 : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_local_int5_enable_s; -} sh_local_int5_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC0_ERR_INT_CONFIG" */ /* SHub Processor 0 Error Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc0_err_int_config_u { mmr_t sh_proc0_err_int_config_regval; struct { @@ -1378,28 +767,12 @@ mmr_t reserved_2 : 4; } sh_proc0_err_int_config_s; } sh_proc0_err_int_config_u_t; -#else -typedef union sh_proc0_err_int_config_u { - mmr_t sh_proc0_err_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc0_err_int_config_s; -} sh_proc0_err_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC1_ERR_INT_CONFIG" */ /* SHub Processor 1 Error Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc1_err_int_config_u { mmr_t sh_proc1_err_int_config_regval; struct { @@ -1413,28 +786,12 @@ mmr_t reserved_2 : 4; } sh_proc1_err_int_config_s; } sh_proc1_err_int_config_u_t; -#else -typedef union sh_proc1_err_int_config_u { - mmr_t sh_proc1_err_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc1_err_int_config_s; -} sh_proc1_err_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC2_ERR_INT_CONFIG" */ /* SHub Processor 2 Error Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc2_err_int_config_u { mmr_t sh_proc2_err_int_config_regval; struct { @@ -1448,28 +805,12 @@ mmr_t reserved_2 : 4; } sh_proc2_err_int_config_s; } sh_proc2_err_int_config_u_t; -#else -typedef union sh_proc2_err_int_config_u { - mmr_t sh_proc2_err_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc2_err_int_config_s; -} sh_proc2_err_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC3_ERR_INT_CONFIG" */ /* SHub Processor 3 Error Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc3_err_int_config_u { mmr_t sh_proc3_err_int_config_regval; struct { @@ -1483,28 +824,12 @@ mmr_t reserved_2 : 4; } sh_proc3_err_int_config_s; } sh_proc3_err_int_config_u_t; -#else -typedef union sh_proc3_err_int_config_u { - mmr_t sh_proc3_err_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc3_err_int_config_s; -} sh_proc3_err_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC0_ADV_INT_CONFIG" */ /* SHub Processor 0 Advisory Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc0_adv_int_config_u { mmr_t sh_proc0_adv_int_config_regval; struct { @@ -1518,28 +843,12 @@ mmr_t reserved_2 : 4; } sh_proc0_adv_int_config_s; } sh_proc0_adv_int_config_u_t; -#else -typedef union sh_proc0_adv_int_config_u { - mmr_t sh_proc0_adv_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc0_adv_int_config_s; -} sh_proc0_adv_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC1_ADV_INT_CONFIG" */ /* SHub Processor 1 Advisory Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc1_adv_int_config_u { mmr_t sh_proc1_adv_int_config_regval; struct { @@ -1553,28 +862,12 @@ mmr_t reserved_2 : 4; } sh_proc1_adv_int_config_s; } sh_proc1_adv_int_config_u_t; -#else -typedef union sh_proc1_adv_int_config_u { - mmr_t sh_proc1_adv_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc1_adv_int_config_s; -} sh_proc1_adv_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC2_ADV_INT_CONFIG" */ /* SHub Processor 2 Advisory Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc2_adv_int_config_u { mmr_t sh_proc2_adv_int_config_regval; struct { @@ -1588,28 +881,12 @@ mmr_t reserved_2 : 4; } sh_proc2_adv_int_config_s; } sh_proc2_adv_int_config_u_t; -#else -typedef union sh_proc2_adv_int_config_u { - mmr_t sh_proc2_adv_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc2_adv_int_config_s; -} sh_proc2_adv_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC3_ADV_INT_CONFIG" */ /* SHub Processor 3 Advisory Interrupt Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc3_adv_int_config_u { mmr_t sh_proc3_adv_int_config_regval; struct { @@ -1623,28 +900,12 @@ mmr_t reserved_2 : 4; } sh_proc3_adv_int_config_s; } sh_proc3_adv_int_config_u_t; -#else -typedef union sh_proc3_adv_int_config_u { - mmr_t sh_proc3_adv_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_proc3_adv_int_config_s; -} sh_proc3_adv_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC0_ERR_INT_ENABLE" */ /* SHub Processor 0 Error Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc0_err_int_enable_u { mmr_t sh_proc0_err_int_enable_regval; struct { @@ -1652,22 +913,12 @@ mmr_t reserved_0 : 63; } sh_proc0_err_int_enable_s; } sh_proc0_err_int_enable_u_t; -#else -typedef union sh_proc0_err_int_enable_u { - mmr_t sh_proc0_err_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc0_err_enable : 1; - } sh_proc0_err_int_enable_s; -} sh_proc0_err_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC1_ERR_INT_ENABLE" */ /* SHub Processor 1 Error Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc1_err_int_enable_u { mmr_t sh_proc1_err_int_enable_regval; struct { @@ -1675,22 +926,12 @@ mmr_t reserved_0 : 63; } sh_proc1_err_int_enable_s; } sh_proc1_err_int_enable_u_t; -#else -typedef union sh_proc1_err_int_enable_u { - mmr_t sh_proc1_err_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc1_err_enable : 1; - } sh_proc1_err_int_enable_s; -} sh_proc1_err_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC2_ERR_INT_ENABLE" */ /* SHub Processor 2 Error Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc2_err_int_enable_u { mmr_t sh_proc2_err_int_enable_regval; struct { @@ -1698,22 +939,12 @@ mmr_t reserved_0 : 63; } sh_proc2_err_int_enable_s; } sh_proc2_err_int_enable_u_t; -#else -typedef union sh_proc2_err_int_enable_u { - mmr_t sh_proc2_err_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc2_err_enable : 1; - } sh_proc2_err_int_enable_s; -} sh_proc2_err_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC3_ERR_INT_ENABLE" */ /* SHub Processor 3 Error Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc3_err_int_enable_u { mmr_t sh_proc3_err_int_enable_regval; struct { @@ -1721,22 +952,12 @@ mmr_t reserved_0 : 63; } sh_proc3_err_int_enable_s; } sh_proc3_err_int_enable_u_t; -#else -typedef union sh_proc3_err_int_enable_u { - mmr_t sh_proc3_err_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc3_err_enable : 1; - } sh_proc3_err_int_enable_s; -} sh_proc3_err_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC0_ADV_INT_ENABLE" */ /* SHub Processor 0 Advisory Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc0_adv_int_enable_u { mmr_t sh_proc0_adv_int_enable_regval; struct { @@ -1744,22 +965,12 @@ mmr_t reserved_0 : 63; } sh_proc0_adv_int_enable_s; } sh_proc0_adv_int_enable_u_t; -#else -typedef union sh_proc0_adv_int_enable_u { - mmr_t sh_proc0_adv_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc0_adv_enable : 1; - } sh_proc0_adv_int_enable_s; -} sh_proc0_adv_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC1_ADV_INT_ENABLE" */ /* SHub Processor 1 Advisory Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc1_adv_int_enable_u { mmr_t sh_proc1_adv_int_enable_regval; struct { @@ -1767,22 +978,12 @@ mmr_t reserved_0 : 63; } sh_proc1_adv_int_enable_s; } sh_proc1_adv_int_enable_u_t; -#else -typedef union sh_proc1_adv_int_enable_u { - mmr_t sh_proc1_adv_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc1_adv_enable : 1; - } sh_proc1_adv_int_enable_s; -} sh_proc1_adv_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC2_ADV_INT_ENABLE" */ /* SHub Processor 2 Advisory Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc2_adv_int_enable_u { mmr_t sh_proc2_adv_int_enable_regval; struct { @@ -1790,22 +991,12 @@ mmr_t reserved_0 : 63; } sh_proc2_adv_int_enable_s; } sh_proc2_adv_int_enable_u_t; -#else -typedef union sh_proc2_adv_int_enable_u { - mmr_t sh_proc2_adv_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc2_adv_enable : 1; - } sh_proc2_adv_int_enable_s; -} sh_proc2_adv_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC3_ADV_INT_ENABLE" */ /* SHub Processor 3 Advisory Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc3_adv_int_enable_u { mmr_t sh_proc3_adv_int_enable_regval; struct { @@ -1813,22 +1004,12 @@ mmr_t reserved_0 : 63; } sh_proc3_adv_int_enable_s; } sh_proc3_adv_int_enable_u_t; -#else -typedef union sh_proc3_adv_int_enable_u { - mmr_t sh_proc3_adv_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t proc3_adv_enable : 1; - } sh_proc3_adv_int_enable_s; -} sh_proc3_adv_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_INT_CONFIG" */ /* SHub Profile Interrupt Configuration Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_int_config_u { mmr_t sh_profile_int_config_regval; struct { @@ -1842,28 +1023,12 @@ mmr_t reserved_2 : 4; } sh_profile_int_config_s; } sh_profile_int_config_u_t; -#else -typedef union sh_profile_int_config_u { - mmr_t sh_profile_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_profile_int_config_s; -} sh_profile_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_INT_ENABLE" */ /* SHub Profile Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_int_enable_u { mmr_t sh_profile_int_enable_regval; struct { @@ -1871,22 +1036,12 @@ mmr_t reserved_0 : 63; } sh_profile_int_enable_s; } sh_profile_int_enable_u_t; -#else -typedef union sh_profile_int_enable_u { - mmr_t sh_profile_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t profile_enable : 1; - } sh_profile_int_enable_s; -} sh_profile_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC0_INT_CONFIG" */ /* SHub RTC 0 Interrupt Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc0_int_config_u { mmr_t sh_rtc0_int_config_regval; struct { @@ -1900,28 +1055,12 @@ mmr_t reserved_2 : 4; } sh_rtc0_int_config_s; } sh_rtc0_int_config_u_t; -#else -typedef union sh_rtc0_int_config_u { - mmr_t sh_rtc0_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_rtc0_int_config_s; -} sh_rtc0_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC0_INT_ENABLE" */ /* SHub RTC 0 Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc0_int_enable_u { mmr_t sh_rtc0_int_enable_regval; struct { @@ -1929,22 +1068,12 @@ mmr_t reserved_0 : 63; } sh_rtc0_int_enable_s; } sh_rtc0_int_enable_u_t; -#else -typedef union sh_rtc0_int_enable_u { - mmr_t sh_rtc0_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t rtc0_enable : 1; - } sh_rtc0_int_enable_s; -} sh_rtc0_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC1_INT_CONFIG" */ /* SHub RTC 1 Interrupt Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc1_int_config_u { mmr_t sh_rtc1_int_config_regval; struct { @@ -1958,28 +1087,12 @@ mmr_t reserved_2 : 4; } sh_rtc1_int_config_s; } sh_rtc1_int_config_u_t; -#else -typedef union sh_rtc1_int_config_u { - mmr_t sh_rtc1_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_rtc1_int_config_s; -} sh_rtc1_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC1_INT_ENABLE" */ /* SHub RTC 1 Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc1_int_enable_u { mmr_t sh_rtc1_int_enable_regval; struct { @@ -1987,22 +1100,12 @@ mmr_t reserved_0 : 63; } sh_rtc1_int_enable_s; } sh_rtc1_int_enable_u_t; -#else -typedef union sh_rtc1_int_enable_u { - mmr_t sh_rtc1_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t rtc1_enable : 1; - } sh_rtc1_int_enable_s; -} sh_rtc1_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC2_INT_CONFIG" */ /* SHub RTC 2 Interrupt Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc2_int_config_u { mmr_t sh_rtc2_int_config_regval; struct { @@ -2016,28 +1119,12 @@ mmr_t reserved_2 : 4; } sh_rtc2_int_config_s; } sh_rtc2_int_config_u_t; -#else -typedef union sh_rtc2_int_config_u { - mmr_t sh_rtc2_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_rtc2_int_config_s; -} sh_rtc2_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC2_INT_ENABLE" */ /* SHub RTC 2 Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc2_int_enable_u { mmr_t sh_rtc2_int_enable_regval; struct { @@ -2045,22 +1132,12 @@ mmr_t reserved_0 : 63; } sh_rtc2_int_enable_s; } sh_rtc2_int_enable_u_t; -#else -typedef union sh_rtc2_int_enable_u { - mmr_t sh_rtc2_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t rtc2_enable : 1; - } sh_rtc2_int_enable_s; -} sh_rtc2_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC3_INT_CONFIG" */ /* SHub RTC 3 Interrupt Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc3_int_config_u { mmr_t sh_rtc3_int_config_regval; struct { @@ -2074,28 +1151,12 @@ mmr_t reserved_2 : 4; } sh_rtc3_int_config_s; } sh_rtc3_int_config_u_t; -#else -typedef union sh_rtc3_int_config_u { - mmr_t sh_rtc3_int_config_regval; - struct { - mmr_t reserved_2 : 4; - mmr_t idx : 8; - mmr_t reserved_1 : 2; - mmr_t base : 29; - mmr_t reserved_0 : 1; - mmr_t pid : 16; - mmr_t agt : 1; - mmr_t type : 3; - } sh_rtc3_int_config_s; -} sh_rtc3_int_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC3_INT_ENABLE" */ /* SHub RTC 3 Interrupt Enable Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc3_int_enable_u { mmr_t sh_rtc3_int_enable_regval; struct { @@ -2103,22 +1164,12 @@ mmr_t reserved_0 : 63; } sh_rtc3_int_enable_s; } sh_rtc3_int_enable_u_t; -#else -typedef union sh_rtc3_int_enable_u { - mmr_t sh_rtc3_int_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t rtc3_enable : 1; - } sh_rtc3_int_enable_s; -} sh_rtc3_int_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_EVENT_OCCURRED" */ /* SHub Interrupt Event Occurred */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_event_occurred_u { mmr_t sh_event_occurred_regval; struct { @@ -2156,52 +1207,12 @@ mmr_t reserved_0 : 33; } sh_event_occurred_s; } sh_event_occurred_u_t; -#else -typedef union sh_event_occurred_u { - mmr_t sh_event_occurred_regval; - struct { - mmr_t reserved_0 : 33; - mmr_t ii_int1 : 1; - mmr_t ii_int0 : 1; - mmr_t ipi_int : 1; - mmr_t profile_int : 1; - mmr_t rtc3_int : 1; - mmr_t rtc2_int : 1; - mmr_t rtc1_int : 1; - mmr_t rtc0_int : 1; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t proc3_err_int : 1; - mmr_t proc2_err_int : 1; - mmr_t proc1_err_int : 1; - mmr_t proc0_err_int : 1; - mmr_t proc3_adv_int : 1; - mmr_t proc2_adv_int : 1; - mmr_t proc1_adv_int : 1; - mmr_t proc0_adv_int : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_event_occurred_s; -} sh_event_occurred_u_t; -#endif /* ==================================================================== */ /* Register "SH_EVENT_OVERFLOW" */ /* SHub Interrupt Event Occurred Overflow */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_event_overflow_u { mmr_t sh_event_overflow_regval; struct { @@ -2236,49 +1247,12 @@ mmr_t reserved_0 : 36; } sh_event_overflow_s; } sh_event_overflow_u_t; -#else -typedef union sh_event_overflow_u { - mmr_t sh_event_overflow_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t profile_int : 1; - mmr_t rtc3_int : 1; - mmr_t rtc2_int : 1; - mmr_t rtc1_int : 1; - mmr_t rtc0_int : 1; - mmr_t stop_clock : 1; - mmr_t l1_nmi_int : 1; - mmr_t uart_int : 1; - mmr_t system_shutdown_int : 1; - mmr_t proc3_err_int : 1; - mmr_t proc2_err_int : 1; - mmr_t proc1_err_int : 1; - mmr_t proc0_err_int : 1; - mmr_t proc3_adv_int : 1; - mmr_t proc2_adv_int : 1; - mmr_t proc1_adv_int : 1; - mmr_t proc0_adv_int : 1; - mmr_t xn_uce_int : 1; - mmr_t md_uce_int : 1; - mmr_t pi_uce_int : 1; - mmr_t xn_ce_int : 1; - mmr_t md_ce_int : 1; - mmr_t pi_ce_int : 1; - mmr_t ii_hw_int : 1; - mmr_t lb_hw_int : 1; - mmr_t xn_hw_int : 1; - mmr_t md_hw_int : 1; - mmr_t pi_hw_int : 1; - } sh_event_overflow_s; -} sh_event_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_BUS_TIME" */ /* Junk Bus Timing */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_bus_time_u { mmr_t sh_junk_bus_time_regval; struct { @@ -2289,25 +1263,12 @@ mmr_t reserved_0 : 32; } sh_junk_bus_time_s; } sh_junk_bus_time_u_t; -#else -typedef union sh_junk_bus_time_u { - mmr_t sh_junk_bus_time_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t uart_enable : 8; - mmr_t uart_setup_hold : 8; - mmr_t fprom_enable : 8; - mmr_t fprom_setup_hold : 8; - } sh_junk_bus_time_s; -} sh_junk_bus_time_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_LATCH_TIME" */ /* Junk Bus Latch Timing */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_latch_time_u { mmr_t sh_junk_latch_time_regval; struct { @@ -2315,22 +1276,12 @@ mmr_t reserved_0 : 61; } sh_junk_latch_time_s; } sh_junk_latch_time_u_t; -#else -typedef union sh_junk_latch_time_u { - mmr_t sh_junk_latch_time_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t setup_hold : 3; - } sh_junk_latch_time_s; -} sh_junk_latch_time_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_NACK_RESET" */ /* Junk Bus Nack Counter Reset */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_nack_reset_u { mmr_t sh_junk_nack_reset_regval; struct { @@ -2338,22 +1289,12 @@ mmr_t reserved_0 : 63; } sh_junk_nack_reset_s; } sh_junk_nack_reset_u_t; -#else -typedef union sh_junk_nack_reset_u { - mmr_t sh_junk_nack_reset_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t pulse : 1; - } sh_junk_nack_reset_s; -} sh_junk_nack_reset_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_BUS_LED0" */ /* Junk Bus LED0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_bus_led0_u { mmr_t sh_junk_bus_led0_regval; struct { @@ -2361,22 +1302,12 @@ mmr_t reserved_0 : 56; } sh_junk_bus_led0_s; } sh_junk_bus_led0_u_t; -#else -typedef union sh_junk_bus_led0_u { - mmr_t sh_junk_bus_led0_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t led0_data : 8; - } sh_junk_bus_led0_s; -} sh_junk_bus_led0_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_BUS_LED1" */ /* Junk Bus LED1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_bus_led1_u { mmr_t sh_junk_bus_led1_regval; struct { @@ -2384,22 +1315,12 @@ mmr_t reserved_0 : 56; } sh_junk_bus_led1_s; } sh_junk_bus_led1_u_t; -#else -typedef union sh_junk_bus_led1_u { - mmr_t sh_junk_bus_led1_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t led1_data : 8; - } sh_junk_bus_led1_s; -} sh_junk_bus_led1_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_BUS_LED2" */ /* Junk Bus LED2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_bus_led2_u { mmr_t sh_junk_bus_led2_regval; struct { @@ -2407,22 +1328,12 @@ mmr_t reserved_0 : 56; } sh_junk_bus_led2_s; } sh_junk_bus_led2_u_t; -#else -typedef union sh_junk_bus_led2_u { - mmr_t sh_junk_bus_led2_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t led2_data : 8; - } sh_junk_bus_led2_s; -} sh_junk_bus_led2_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_BUS_LED3" */ /* Junk Bus LED3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_bus_led3_u { mmr_t sh_junk_bus_led3_regval; struct { @@ -2430,22 +1341,12 @@ mmr_t reserved_0 : 56; } sh_junk_bus_led3_s; } sh_junk_bus_led3_u_t; -#else -typedef union sh_junk_bus_led3_u { - mmr_t sh_junk_bus_led3_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t led3_data : 8; - } sh_junk_bus_led3_s; -} sh_junk_bus_led3_u_t; -#endif /* ==================================================================== */ /* Register "SH_JUNK_ERROR_STATUS" */ /* Junk Bus Error Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_junk_error_status_u { mmr_t sh_junk_error_status_regval; struct { @@ -2457,26 +1358,12 @@ mmr_t reserved_1 : 3; } sh_junk_error_status_s; } sh_junk_error_status_u_t; -#else -typedef union sh_junk_error_status_u { - mmr_t sh_junk_error_status_regval; - struct { - mmr_t reserved_1 : 3; - mmr_t status : 4; - mmr_t mode : 1; - mmr_t cmd : 8; - mmr_t reserved_0 : 1; - mmr_t address : 47; - } sh_junk_error_status_s; -} sh_junk_error_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_STAT" */ /* This register describes the LLP status. */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_stat_u { mmr_t sh_ni0_llp_stat_regval; struct { @@ -2484,22 +1371,12 @@ mmr_t reserved_0 : 60; } sh_ni0_llp_stat_s; } sh_ni0_llp_stat_u_t; -#else -typedef union sh_ni0_llp_stat_u { - mmr_t sh_ni0_llp_stat_regval; - struct { - mmr_t reserved_0 : 60; - mmr_t link_reset_state : 4; - } sh_ni0_llp_stat_s; -} sh_ni0_llp_stat_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_RESET" */ /* Writing issues a reset to the network interface */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_reset_u { mmr_t sh_ni0_llp_reset_regval; struct { @@ -2508,23 +1385,12 @@ mmr_t reserved_0 : 62; } sh_ni0_llp_reset_s; } sh_ni0_llp_reset_u_t; -#else -typedef union sh_ni0_llp_reset_u { - mmr_t sh_ni0_llp_reset_regval; - struct { - mmr_t reserved_0 : 62; - mmr_t warm : 1; - mmr_t link : 1; - } sh_ni0_llp_reset_s; -} sh_ni0_llp_reset_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_RESET_EN" */ /* Controls LLP warm reset propagation */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_reset_en_u { mmr_t sh_ni0_llp_reset_en_regval; struct { @@ -2532,22 +1398,12 @@ mmr_t reserved_0 : 63; } sh_ni0_llp_reset_en_s; } sh_ni0_llp_reset_en_u_t; -#else -typedef union sh_ni0_llp_reset_en_u { - mmr_t sh_ni0_llp_reset_en_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t ok : 1; - } sh_ni0_llp_reset_en_s; -} sh_ni0_llp_reset_en_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_CHAN_MODE" */ /* Sets the signaling mode of LLP and channel */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_chan_mode_u { mmr_t sh_ni0_llp_chan_mode_regval; struct { @@ -2559,26 +1415,12 @@ mmr_t reserved_0 : 59; } sh_ni0_llp_chan_mode_s; } sh_ni0_llp_chan_mode_u_t; -#else -typedef union sh_ni0_llp_chan_mode_u { - mmr_t sh_ni0_llp_chan_mode_regval; - struct { - mmr_t reserved_0 : 59; - mmr_t enable_clkquad : 1; - mmr_t enable_rmt_ft_upd : 1; - mmr_t enable_tuning : 1; - mmr_t ac_encode : 1; - mmr_t bitmode32 : 1; - } sh_ni0_llp_chan_mode_s; -} sh_ni0_llp_chan_mode_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_CONFIG" */ /* Sets the configuration of LLP and channel */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_config_u { mmr_t sh_ni0_llp_config_regval; struct { @@ -2589,24 +1431,11 @@ mmr_t reserved_0 : 26; } sh_ni0_llp_config_s; } sh_ni0_llp_config_u_t; -#else -typedef union sh_ni0_llp_config_u { - mmr_t sh_ni0_llp_config_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t ftu_time : 12; - mmr_t nulltimeout : 6; - mmr_t maxretry : 10; - mmr_t maxburst : 10; - } sh_ni0_llp_config_s; -} sh_ni0_llp_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_TEST_CTL" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_test_ctl_u { mmr_t sh_ni0_llp_test_ctl_regval; struct { @@ -2627,77 +1456,36 @@ mmr_t reserved_2 : 1; } sh_ni0_llp_test_ctl_s; } sh_ni0_llp_test_ctl_u_t; -#else -typedef union sh_ni0_llp_test_ctl_u { - mmr_t sh_ni0_llp_test_ctl_regval; - struct { - mmr_t reserved_2 : 1; - mmr_t cberror : 1; - mmr_t captured : 1; - mmr_t fakesnerror : 1; - mmr_t sendsnerror : 1; - mmr_t sendcberror : 1; - mmr_t capturecbonly : 1; - mmr_t armcapture : 1; - mmr_t noise_mode : 2; - mmr_t lfsr_mode : 2; - mmr_t reserved_1 : 2; - mmr_t wire_sel : 6; - mmr_t reserved_0 : 2; - mmr_t send_test_mode : 2; - mmr_t pattern : 40; - } sh_ni0_llp_test_ctl_s; -} sh_ni0_llp_test_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_CAPT_WD1" */ /* low order 64-bit captured word */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni0_llp_capt_wd1_u { - mmr_t sh_ni0_llp_capt_wd1_regval; - struct { - mmr_t data : 64; - } sh_ni0_llp_capt_wd1_s; -} sh_ni0_llp_capt_wd1_u_t; -#else typedef union sh_ni0_llp_capt_wd1_u { mmr_t sh_ni0_llp_capt_wd1_regval; struct { mmr_t data : 64; } sh_ni0_llp_capt_wd1_s; } sh_ni0_llp_capt_wd1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_CAPT_WD2" */ /* high order 64-bit captured word */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_capt_wd2_u { mmr_t sh_ni0_llp_capt_wd2_regval; struct { mmr_t data : 64; } sh_ni0_llp_capt_wd2_s; } sh_ni0_llp_capt_wd2_u_t; -#else -typedef union sh_ni0_llp_capt_wd2_u { - mmr_t sh_ni0_llp_capt_wd2_regval; - struct { - mmr_t data : 64; - } sh_ni0_llp_capt_wd2_s; -} sh_ni0_llp_capt_wd2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_CAPT_SBCB" */ /* captured sideband, sequence, and CRC */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_capt_sbcb_u { mmr_t sh_ni0_llp_capt_sbcb_regval; struct { @@ -2711,27 +1499,11 @@ mmr_t reserved_0 : 27; } sh_ni0_llp_capt_sbcb_s; } sh_ni0_llp_capt_sbcb_u_t; -#else -typedef union sh_ni0_llp_capt_sbcb_u { - mmr_t sh_ni0_llp_capt_sbcb_regval; - struct { - mmr_t reserved_0 : 27; - mmr_t chargeunderflow : 1; - mmr_t chargeoverflow : 1; - mmr_t fakedallsnerrors : 1; - mmr_t sentallsnerrors : 1; - mmr_t sentallcberrors : 1; - mmr_t capturedrcvcrc : 16; - mmr_t capturedrcvsbsn : 16; - } sh_ni0_llp_capt_sbcb_s; -} sh_ni0_llp_capt_sbcb_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LLP_ERR" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_llp_err_u { mmr_t sh_ni0_llp_err_regval; struct { @@ -2747,30 +1519,12 @@ mmr_t reserved_0 : 11; } sh_ni0_llp_err_s; } sh_ni0_llp_err_u_t; -#else -typedef union sh_ni0_llp_err_u { - mmr_t sh_ni0_llp_err_regval; - struct { - mmr_t reserved_0 : 11; - mmr_t wire_overflow : 1; - mmr_t wire_cnt : 24; - mmr_t power_not_ok : 1; - mmr_t squash : 1; - mmr_t rcv_link_reset : 1; - mmr_t retry_timeout : 1; - mmr_t retry_count : 8; - mmr_t rx_cb_err_count : 8; - mmr_t rx_sn_err_count : 8; - } sh_ni0_llp_err_s; -} sh_ni0_llp_err_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_STAT" */ /* This register describes the LLP status. */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_stat_u { mmr_t sh_ni1_llp_stat_regval; struct { @@ -2778,22 +1532,12 @@ mmr_t reserved_0 : 60; } sh_ni1_llp_stat_s; } sh_ni1_llp_stat_u_t; -#else -typedef union sh_ni1_llp_stat_u { - mmr_t sh_ni1_llp_stat_regval; - struct { - mmr_t reserved_0 : 60; - mmr_t link_reset_state : 4; - } sh_ni1_llp_stat_s; -} sh_ni1_llp_stat_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_RESET" */ /* Writing issues a reset to the network interface */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_reset_u { mmr_t sh_ni1_llp_reset_regval; struct { @@ -2802,23 +1546,12 @@ mmr_t reserved_0 : 62; } sh_ni1_llp_reset_s; } sh_ni1_llp_reset_u_t; -#else -typedef union sh_ni1_llp_reset_u { - mmr_t sh_ni1_llp_reset_regval; - struct { - mmr_t reserved_0 : 62; - mmr_t warm : 1; - mmr_t link : 1; - } sh_ni1_llp_reset_s; -} sh_ni1_llp_reset_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_RESET_EN" */ /* Controls LLP warm reset propagation */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_reset_en_u { mmr_t sh_ni1_llp_reset_en_regval; struct { @@ -2826,22 +1559,12 @@ mmr_t reserved_0 : 63; } sh_ni1_llp_reset_en_s; } sh_ni1_llp_reset_en_u_t; -#else -typedef union sh_ni1_llp_reset_en_u { - mmr_t sh_ni1_llp_reset_en_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t ok : 1; - } sh_ni1_llp_reset_en_s; -} sh_ni1_llp_reset_en_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_CHAN_MODE" */ /* Sets the signaling mode of LLP and channel */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_chan_mode_u { mmr_t sh_ni1_llp_chan_mode_regval; struct { @@ -2853,26 +1576,12 @@ mmr_t reserved_0 : 59; } sh_ni1_llp_chan_mode_s; } sh_ni1_llp_chan_mode_u_t; -#else -typedef union sh_ni1_llp_chan_mode_u { - mmr_t sh_ni1_llp_chan_mode_regval; - struct { - mmr_t reserved_0 : 59; - mmr_t enable_clkquad : 1; - mmr_t enable_rmt_ft_upd : 1; - mmr_t enable_tuning : 1; - mmr_t ac_encode : 1; - mmr_t bitmode32 : 1; - } sh_ni1_llp_chan_mode_s; -} sh_ni1_llp_chan_mode_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_CONFIG" */ /* Sets the configuration of LLP and channel */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_config_u { mmr_t sh_ni1_llp_config_regval; struct { @@ -2883,24 +1592,11 @@ mmr_t reserved_0 : 26; } sh_ni1_llp_config_s; } sh_ni1_llp_config_u_t; -#else -typedef union sh_ni1_llp_config_u { - mmr_t sh_ni1_llp_config_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t ftu_time : 12; - mmr_t nulltimeout : 6; - mmr_t maxretry : 10; - mmr_t maxburst : 10; - } sh_ni1_llp_config_s; -} sh_ni1_llp_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_TEST_CTL" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_test_ctl_u { mmr_t sh_ni1_llp_test_ctl_regval; struct { @@ -2921,77 +1617,36 @@ mmr_t reserved_2 : 1; } sh_ni1_llp_test_ctl_s; } sh_ni1_llp_test_ctl_u_t; -#else -typedef union sh_ni1_llp_test_ctl_u { - mmr_t sh_ni1_llp_test_ctl_regval; - struct { - mmr_t reserved_2 : 1; - mmr_t cberror : 1; - mmr_t captured : 1; - mmr_t fakesnerror : 1; - mmr_t sendsnerror : 1; - mmr_t sendcberror : 1; - mmr_t capturecbonly : 1; - mmr_t armcapture : 1; - mmr_t noise_mode : 2; - mmr_t lfsr_mode : 2; - mmr_t reserved_1 : 2; - mmr_t wire_sel : 6; - mmr_t reserved_0 : 2; - mmr_t send_test_mode : 2; - mmr_t pattern : 40; - } sh_ni1_llp_test_ctl_s; -} sh_ni1_llp_test_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_CAPT_WD1" */ /* low order 64-bit captured word */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni1_llp_capt_wd1_u { - mmr_t sh_ni1_llp_capt_wd1_regval; - struct { - mmr_t data : 64; - } sh_ni1_llp_capt_wd1_s; -} sh_ni1_llp_capt_wd1_u_t; -#else typedef union sh_ni1_llp_capt_wd1_u { mmr_t sh_ni1_llp_capt_wd1_regval; struct { mmr_t data : 64; } sh_ni1_llp_capt_wd1_s; } sh_ni1_llp_capt_wd1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_CAPT_WD2" */ /* high order 64-bit captured word */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni1_llp_capt_wd2_u { - mmr_t sh_ni1_llp_capt_wd2_regval; - struct { - mmr_t data : 64; - } sh_ni1_llp_capt_wd2_s; -} sh_ni1_llp_capt_wd2_u_t; -#else typedef union sh_ni1_llp_capt_wd2_u { mmr_t sh_ni1_llp_capt_wd2_regval; struct { mmr_t data : 64; } sh_ni1_llp_capt_wd2_s; } sh_ni1_llp_capt_wd2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_CAPT_SBCB" */ /* captured sideband, sequence, and CRC */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_capt_sbcb_u { mmr_t sh_ni1_llp_capt_sbcb_regval; struct { @@ -3005,27 +1660,11 @@ mmr_t reserved_0 : 27; } sh_ni1_llp_capt_sbcb_s; } sh_ni1_llp_capt_sbcb_u_t; -#else -typedef union sh_ni1_llp_capt_sbcb_u { - mmr_t sh_ni1_llp_capt_sbcb_regval; - struct { - mmr_t reserved_0 : 27; - mmr_t chargeunderflow : 1; - mmr_t chargeoverflow : 1; - mmr_t fakedallsnerrors : 1; - mmr_t sentallsnerrors : 1; - mmr_t sentallcberrors : 1; - mmr_t capturedrcvcrc : 16; - mmr_t capturedrcvsbsn : 16; - } sh_ni1_llp_capt_sbcb_s; -} sh_ni1_llp_capt_sbcb_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LLP_ERR" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_llp_err_u { mmr_t sh_ni1_llp_err_regval; struct { @@ -3041,29 +1680,11 @@ mmr_t reserved_0 : 11; } sh_ni1_llp_err_s; } sh_ni1_llp_err_u_t; -#else -typedef union sh_ni1_llp_err_u { - mmr_t sh_ni1_llp_err_regval; - struct { - mmr_t reserved_0 : 11; - mmr_t wire_overflow : 1; - mmr_t wire_cnt : 24; - mmr_t power_not_ok : 1; - mmr_t squash : 1; - mmr_t rcv_link_reset : 1; - mmr_t retry_timeout : 1; - mmr_t retry_count : 8; - mmr_t rx_cb_err_count : 8; - mmr_t rx_sn_err_count : 8; - } sh_ni1_llp_err_s; -} sh_ni1_llp_err_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_LLP_TO_FIFO02_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_llp_to_fifo02_flow_u { mmr_t sh_xnni0_llp_to_fifo02_flow_regval; struct { @@ -3084,34 +1705,11 @@ mmr_t reserved_6 : 2; } sh_xnni0_llp_to_fifo02_flow_s; } sh_xnni0_llp_to_fifo02_flow_u_t; -#else -typedef union sh_xnni0_llp_to_fifo02_flow_u { - mmr_t sh_xnni0_llp_to_fifo02_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni0_llp_to_fifo02_flow_s; -} sh_xnni0_llp_to_fifo02_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_LLP_TO_FIFO13_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_llp_to_fifo13_flow_u { mmr_t sh_xnni0_llp_to_fifo13_flow_regval; struct { @@ -3132,34 +1730,11 @@ mmr_t reserved_6 : 2; } sh_xnni0_llp_to_fifo13_flow_s; } sh_xnni0_llp_to_fifo13_flow_u_t; -#else -typedef union sh_xnni0_llp_to_fifo13_flow_u { - mmr_t sh_xnni0_llp_to_fifo13_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni0_llp_to_fifo13_flow_s; -} sh_xnni0_llp_to_fifo13_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_LLP_DEBIT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_llp_debit_flow_u { mmr_t sh_xnni0_llp_debit_flow_regval; struct { @@ -3181,35 +1756,11 @@ mmr_t reserved_7 : 3; } sh_xnni0_llp_debit_flow_s; } sh_xnni0_llp_debit_flow_u_t; -#else -typedef union sh_xnni0_llp_debit_flow_u { - mmr_t sh_xnni0_llp_debit_flow_regval; - struct { - mmr_t reserved_7 : 3; - mmr_t debit_vc3_cap : 5; - mmr_t reserved_6 : 3; - mmr_t debit_vc3_dyn : 5; - mmr_t reserved_5 : 3; - mmr_t debit_vc2_cap : 5; - mmr_t reserved_4 : 3; - mmr_t debit_vc2_dyn : 5; - mmr_t reserved_3 : 3; - mmr_t debit_vc1_cap : 5; - mmr_t reserved_2 : 3; - mmr_t debit_vc1_dyn : 5; - mmr_t reserved_1 : 3; - mmr_t debit_vc0_cap : 5; - mmr_t reserved_0 : 3; - mmr_t debit_vc0_dyn : 5; - } sh_xnni0_llp_debit_flow_s; -} sh_xnni0_llp_debit_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_LINK_0_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_link_0_flow_u { mmr_t sh_xnni0_link_0_flow_regval; struct { @@ -3224,28 +1775,11 @@ mmr_t reserved_3 : 33; } sh_xnni0_link_0_flow_s; } sh_xnni0_link_0_flow_u_t; -#else -typedef union sh_xnni0_link_0_flow_u { - mmr_t sh_xnni0_link_0_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc0_test : 7; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni0_link_0_flow_s; -} sh_xnni0_link_0_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_LINK_1_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_link_1_flow_u { mmr_t sh_xnni0_link_1_flow_regval; struct { @@ -3260,28 +1794,11 @@ mmr_t reserved_3 : 33; } sh_xnni0_link_1_flow_s; } sh_xnni0_link_1_flow_u_t; -#else -typedef union sh_xnni0_link_1_flow_u { - mmr_t sh_xnni0_link_1_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc1_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc1_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc1_test : 7; - mmr_t debit_vc1_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc1_withhold : 6; - } sh_xnni0_link_1_flow_s; -} sh_xnni0_link_1_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_LINK_2_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_link_2_flow_u { mmr_t sh_xnni0_link_2_flow_regval; struct { @@ -3296,28 +1813,11 @@ mmr_t reserved_3 : 33; } sh_xnni0_link_2_flow_s; } sh_xnni0_link_2_flow_u_t; -#else -typedef union sh_xnni0_link_2_flow_u { - mmr_t sh_xnni0_link_2_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc2_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc2_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc2_test : 7; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc2_withhold : 6; - } sh_xnni0_link_2_flow_s; -} sh_xnni0_link_2_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_LINK_3_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_link_3_flow_u { mmr_t sh_xnni0_link_3_flow_regval; struct { @@ -3332,28 +1832,11 @@ mmr_t reserved_3 : 33; } sh_xnni0_link_3_flow_s; } sh_xnni0_link_3_flow_u_t; -#else -typedef union sh_xnni0_link_3_flow_u { - mmr_t sh_xnni0_link_3_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc3_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc3_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc3_test : 7; - mmr_t debit_vc3_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc3_withhold : 6; - } sh_xnni0_link_3_flow_s; -} sh_xnni0_link_3_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_LLP_TO_FIFO02_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_llp_to_fifo02_flow_u { mmr_t sh_xnni1_llp_to_fifo02_flow_regval; struct { @@ -3374,34 +1857,11 @@ mmr_t reserved_6 : 2; } sh_xnni1_llp_to_fifo02_flow_s; } sh_xnni1_llp_to_fifo02_flow_u_t; -#else -typedef union sh_xnni1_llp_to_fifo02_flow_u { - mmr_t sh_xnni1_llp_to_fifo02_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni1_llp_to_fifo02_flow_s; -} sh_xnni1_llp_to_fifo02_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_LLP_TO_FIFO13_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_llp_to_fifo13_flow_u { mmr_t sh_xnni1_llp_to_fifo13_flow_regval; struct { @@ -3422,34 +1882,11 @@ mmr_t reserved_6 : 2; } sh_xnni1_llp_to_fifo13_flow_s; } sh_xnni1_llp_to_fifo13_flow_u_t; -#else -typedef union sh_xnni1_llp_to_fifo13_flow_u { - mmr_t sh_xnni1_llp_to_fifo13_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni1_llp_to_fifo13_flow_s; -} sh_xnni1_llp_to_fifo13_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_LLP_DEBIT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_llp_debit_flow_u { mmr_t sh_xnni1_llp_debit_flow_regval; struct { @@ -3471,35 +1908,11 @@ mmr_t reserved_7 : 3; } sh_xnni1_llp_debit_flow_s; } sh_xnni1_llp_debit_flow_u_t; -#else -typedef union sh_xnni1_llp_debit_flow_u { - mmr_t sh_xnni1_llp_debit_flow_regval; - struct { - mmr_t reserved_7 : 3; - mmr_t debit_vc3_cap : 5; - mmr_t reserved_6 : 3; - mmr_t debit_vc3_dyn : 5; - mmr_t reserved_5 : 3; - mmr_t debit_vc2_cap : 5; - mmr_t reserved_4 : 3; - mmr_t debit_vc2_dyn : 5; - mmr_t reserved_3 : 3; - mmr_t debit_vc1_cap : 5; - mmr_t reserved_2 : 3; - mmr_t debit_vc1_dyn : 5; - mmr_t reserved_1 : 3; - mmr_t debit_vc0_cap : 5; - mmr_t reserved_0 : 3; - mmr_t debit_vc0_dyn : 5; - } sh_xnni1_llp_debit_flow_s; -} sh_xnni1_llp_debit_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_LINK_0_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_link_0_flow_u { mmr_t sh_xnni1_link_0_flow_regval; struct { @@ -3514,28 +1927,11 @@ mmr_t reserved_3 : 33; } sh_xnni1_link_0_flow_s; } sh_xnni1_link_0_flow_u_t; -#else -typedef union sh_xnni1_link_0_flow_u { - mmr_t sh_xnni1_link_0_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc0_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc0_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc0_test : 7; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni1_link_0_flow_s; -} sh_xnni1_link_0_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_LINK_1_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_link_1_flow_u { mmr_t sh_xnni1_link_1_flow_regval; struct { @@ -3550,28 +1946,11 @@ mmr_t reserved_3 : 33; } sh_xnni1_link_1_flow_s; } sh_xnni1_link_1_flow_u_t; -#else -typedef union sh_xnni1_link_1_flow_u { - mmr_t sh_xnni1_link_1_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc1_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc1_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc1_test : 7; - mmr_t debit_vc1_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc1_withhold : 6; - } sh_xnni1_link_1_flow_s; -} sh_xnni1_link_1_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_LINK_2_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_link_2_flow_u { mmr_t sh_xnni1_link_2_flow_regval; struct { @@ -3586,28 +1965,11 @@ mmr_t reserved_3 : 33; } sh_xnni1_link_2_flow_s; } sh_xnni1_link_2_flow_u_t; -#else -typedef union sh_xnni1_link_2_flow_u { - mmr_t sh_xnni1_link_2_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc2_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc2_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc2_test : 7; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc2_withhold : 6; - } sh_xnni1_link_2_flow_s; -} sh_xnni1_link_2_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_LINK_3_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_link_3_flow_u { mmr_t sh_xnni1_link_3_flow_regval; struct { @@ -3622,29 +1984,12 @@ mmr_t reserved_3 : 33; } sh_xnni1_link_3_flow_s; } sh_xnni1_link_3_flow_u_t; -#else -typedef union sh_xnni1_link_3_flow_u { - mmr_t sh_xnni1_link_3_flow_regval; - struct { - mmr_t reserved_3 : 33; - mmr_t credit_vc3_cap : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc3_dyn : 7; - mmr_t reserved_1 : 1; - mmr_t credit_vc3_test : 7; - mmr_t debit_vc3_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc3_withhold : 6; - } sh_xnni1_link_3_flow_s; -} sh_xnni1_link_3_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_IILB_LOCAL_TABLE" */ /* local lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_iilb_local_table_u { mmr_t sh_iilb_local_table_regval; struct { @@ -3655,25 +2000,12 @@ mmr_t valid : 1; } sh_iilb_local_table_s; } sh_iilb_local_table_u_t; -#else -typedef union sh_iilb_local_table_u { - mmr_t sh_iilb_local_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_0 : 57; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_iilb_local_table_s; -} sh_iilb_local_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_IILB_GLOBAL_TABLE" */ /* global lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_iilb_global_table_u { mmr_t sh_iilb_global_table_regval; struct { @@ -3684,25 +2016,12 @@ mmr_t valid : 1; } sh_iilb_global_table_s; } sh_iilb_global_table_u_t; -#else -typedef union sh_iilb_global_table_u { - mmr_t sh_iilb_global_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_0 : 57; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_iilb_global_table_s; -} sh_iilb_global_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_IILB_OVER_RIDE_TABLE" */ /* If enabled, bypass the Global/Local tables */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_iilb_over_ride_table_u { mmr_t sh_iilb_over_ride_table_regval; struct { @@ -3713,46 +2032,24 @@ mmr_t enable : 1; } sh_iilb_over_ride_table_s; } sh_iilb_over_ride_table_u_t; -#else -typedef union sh_iilb_over_ride_table_u { - mmr_t sh_iilb_over_ride_table_regval; - struct { - mmr_t enable : 1; - mmr_t reserved_0 : 57; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_iilb_over_ride_table_s; -} sh_iilb_over_ride_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_IILB_RSP_PLANE_HINT" */ /* If enabled, invert incoming response only plane hint bit before lo */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_iilb_rsp_plane_hint_u { - mmr_t sh_iilb_rsp_plane_hint_regval; - struct { - mmr_t reserved_0 : 64; - } sh_iilb_rsp_plane_hint_s; -} sh_iilb_rsp_plane_hint_u_t; -#else typedef union sh_iilb_rsp_plane_hint_u { mmr_t sh_iilb_rsp_plane_hint_regval; struct { mmr_t reserved_0 : 64; } sh_iilb_rsp_plane_hint_s; } sh_iilb_rsp_plane_hint_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_LOCAL_TABLE" */ /* local lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_local_table_u { mmr_t sh_pi_local_table_regval; struct { @@ -3767,29 +2064,12 @@ mmr_t valid : 1; } sh_pi_local_table_s; } sh_pi_local_table_u_t; -#else -typedef union sh_pi_local_table_u { - mmr_t sh_pi_local_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_1 : 49; - mmr_t ni_sel1 : 1; - mmr_t v1 : 1; - mmr_t dir1 : 4; - mmr_t reserved_0 : 2; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_pi_local_table_s; -} sh_pi_local_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_GLOBAL_TABLE" */ /* global lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_global_table_u { mmr_t sh_pi_global_table_regval; struct { @@ -3804,29 +2084,12 @@ mmr_t valid : 1; } sh_pi_global_table_s; } sh_pi_global_table_u_t; -#else -typedef union sh_pi_global_table_u { - mmr_t sh_pi_global_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_1 : 49; - mmr_t ni_sel1 : 1; - mmr_t v1 : 1; - mmr_t dir1 : 4; - mmr_t reserved_0 : 2; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_pi_global_table_s; -} sh_pi_global_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_OVER_RIDE_TABLE" */ /* If enabled, bypass the Global/Local tables */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_over_ride_table_u { mmr_t sh_pi_over_ride_table_regval; struct { @@ -3841,29 +2104,12 @@ mmr_t enable : 1; } sh_pi_over_ride_table_s; } sh_pi_over_ride_table_u_t; -#else -typedef union sh_pi_over_ride_table_u { - mmr_t sh_pi_over_ride_table_regval; - struct { - mmr_t enable : 1; - mmr_t reserved_1 : 49; - mmr_t ni_sel1 : 1; - mmr_t v1 : 1; - mmr_t dir1 : 4; - mmr_t reserved_0 : 2; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_pi_over_ride_table_s; -} sh_pi_over_ride_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_RSP_PLANE_HINT" */ /* If enabled, invert incoming response only plane hint bit before lo */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_rsp_plane_hint_u { mmr_t sh_pi_rsp_plane_hint_regval; struct { @@ -3871,22 +2117,12 @@ mmr_t reserved_0 : 63; } sh_pi_rsp_plane_hint_s; } sh_pi_rsp_plane_hint_u_t; -#else -typedef union sh_pi_rsp_plane_hint_u { - mmr_t sh_pi_rsp_plane_hint_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t invert : 1; - } sh_pi_rsp_plane_hint_s; -} sh_pi_rsp_plane_hint_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_LOCAL_TABLE" */ /* local lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_local_table_u { mmr_t sh_ni0_local_table_regval; struct { @@ -3896,24 +2132,12 @@ mmr_t valid : 1; } sh_ni0_local_table_s; } sh_ni0_local_table_u_t; -#else -typedef union sh_ni0_local_table_u { - mmr_t sh_ni0_local_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_0 : 58; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_ni0_local_table_s; -} sh_ni0_local_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_GLOBAL_TABLE" */ /* global lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_global_table_u { mmr_t sh_ni0_global_table_regval; struct { @@ -3923,24 +2147,12 @@ mmr_t valid : 1; } sh_ni0_global_table_s; } sh_ni0_global_table_u_t; -#else -typedef union sh_ni0_global_table_u { - mmr_t sh_ni0_global_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_0 : 58; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_ni0_global_table_s; -} sh_ni0_global_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_OVER_RIDE_TABLE" */ /* If enabled, bypass the Global/Local tables */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_over_ride_table_u { mmr_t sh_ni0_over_ride_table_regval; struct { @@ -3950,45 +2162,24 @@ mmr_t enable : 1; } sh_ni0_over_ride_table_s; } sh_ni0_over_ride_table_u_t; -#else -typedef union sh_ni0_over_ride_table_u { - mmr_t sh_ni0_over_ride_table_regval; - struct { - mmr_t enable : 1; - mmr_t reserved_0 : 58; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_ni0_over_ride_table_s; -} sh_ni0_over_ride_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_RSP_PLANE_HINT" */ /* If enabled, invert incoming response only plane hint bit before lo */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni0_rsp_plane_hint_u { - mmr_t sh_ni0_rsp_plane_hint_regval; - struct { - mmr_t reserved_0 : 64; - } sh_ni0_rsp_plane_hint_s; -} sh_ni0_rsp_plane_hint_u_t; -#else typedef union sh_ni0_rsp_plane_hint_u { mmr_t sh_ni0_rsp_plane_hint_regval; struct { mmr_t reserved_0 : 64; } sh_ni0_rsp_plane_hint_s; } sh_ni0_rsp_plane_hint_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_LOCAL_TABLE" */ /* local lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_local_table_u { mmr_t sh_ni1_local_table_regval; struct { @@ -3998,24 +2189,12 @@ mmr_t valid : 1; } sh_ni1_local_table_s; } sh_ni1_local_table_u_t; -#else -typedef union sh_ni1_local_table_u { - mmr_t sh_ni1_local_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_0 : 58; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_ni1_local_table_s; -} sh_ni1_local_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_GLOBAL_TABLE" */ /* global lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_global_table_u { mmr_t sh_ni1_global_table_regval; struct { @@ -4025,24 +2204,12 @@ mmr_t valid : 1; } sh_ni1_global_table_s; } sh_ni1_global_table_u_t; -#else -typedef union sh_ni1_global_table_u { - mmr_t sh_ni1_global_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_0 : 58; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_ni1_global_table_s; -} sh_ni1_global_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_OVER_RIDE_TABLE" */ /* If enabled, bypass the Global/Local tables */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_over_ride_table_u { mmr_t sh_ni1_over_ride_table_regval; struct { @@ -4052,45 +2219,24 @@ mmr_t enable : 1; } sh_ni1_over_ride_table_s; } sh_ni1_over_ride_table_u_t; -#else -typedef union sh_ni1_over_ride_table_u { - mmr_t sh_ni1_over_ride_table_regval; - struct { - mmr_t enable : 1; - mmr_t reserved_0 : 58; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_ni1_over_ride_table_s; -} sh_ni1_over_ride_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_RSP_PLANE_HINT" */ /* If enabled, invert incoming response only plane hint bit before lo */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni1_rsp_plane_hint_u { - mmr_t sh_ni1_rsp_plane_hint_regval; - struct { - mmr_t reserved_0 : 64; - } sh_ni1_rsp_plane_hint_s; -} sh_ni1_rsp_plane_hint_u_t; -#else typedef union sh_ni1_rsp_plane_hint_u { mmr_t sh_ni1_rsp_plane_hint_regval; struct { mmr_t reserved_0 : 64; } sh_ni1_rsp_plane_hint_s; } sh_ni1_rsp_plane_hint_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_LOCAL_TABLE" */ /* local lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_local_table_u { mmr_t sh_md_local_table_regval; struct { @@ -4105,29 +2251,12 @@ mmr_t valid : 1; } sh_md_local_table_s; } sh_md_local_table_u_t; -#else -typedef union sh_md_local_table_u { - mmr_t sh_md_local_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_1 : 49; - mmr_t ni_sel1 : 1; - mmr_t v1 : 1; - mmr_t dir1 : 4; - mmr_t reserved_0 : 2; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_md_local_table_s; -} sh_md_local_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_GLOBAL_TABLE" */ /* global lookup table */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_global_table_u { mmr_t sh_md_global_table_regval; struct { @@ -4142,29 +2271,12 @@ mmr_t valid : 1; } sh_md_global_table_s; } sh_md_global_table_u_t; -#else -typedef union sh_md_global_table_u { - mmr_t sh_md_global_table_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_1 : 49; - mmr_t ni_sel1 : 1; - mmr_t v1 : 1; - mmr_t dir1 : 4; - mmr_t reserved_0 : 2; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_md_global_table_s; -} sh_md_global_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_OVER_RIDE_TABLE" */ /* If enabled, bypass the Global/Local tables */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_over_ride_table_u { mmr_t sh_md_over_ride_table_regval; struct { @@ -4179,29 +2291,12 @@ mmr_t enable : 1; } sh_md_over_ride_table_s; } sh_md_over_ride_table_u_t; -#else -typedef union sh_md_over_ride_table_u { - mmr_t sh_md_over_ride_table_regval; - struct { - mmr_t enable : 1; - mmr_t reserved_1 : 49; - mmr_t ni_sel1 : 1; - mmr_t v1 : 1; - mmr_t dir1 : 4; - mmr_t reserved_0 : 2; - mmr_t ni_sel0 : 1; - mmr_t v0 : 1; - mmr_t dir0 : 4; - } sh_md_over_ride_table_s; -} sh_md_over_ride_table_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_RSP_PLANE_HINT" */ /* If enabled, invert incoming response only plane hint bit before lo */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_rsp_plane_hint_u { mmr_t sh_md_rsp_plane_hint_regval; struct { @@ -4209,22 +2304,12 @@ mmr_t reserved_0 : 63; } sh_md_rsp_plane_hint_s; } sh_md_rsp_plane_hint_u_t; -#else -typedef union sh_md_rsp_plane_hint_u { - mmr_t sh_md_rsp_plane_hint_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t invert : 1; - } sh_md_rsp_plane_hint_s; -} sh_md_rsp_plane_hint_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_LIQ_CTL" */ /* Local Block LIQ Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_liq_ctl_u { mmr_t sh_lb_liq_ctl_regval; struct { @@ -4238,28 +2323,12 @@ mmr_t reserved_2 : 45; } sh_lb_liq_ctl_s; } sh_lb_liq_ctl_u_t; -#else -typedef union sh_lb_liq_ctl_u { - mmr_t sh_lb_liq_ctl_regval; - struct { - mmr_t reserved_2 : 45; - mmr_t force_linvv_credit : 1; - mmr_t force_rp_credit : 1; - mmr_t force_rq_credit : 1; - mmr_t reserved_1 : 4; - mmr_t liq_rpl_ctl : 4; - mmr_t reserved_0 : 3; - mmr_t liq_req_ctl : 5; - } sh_lb_liq_ctl_s; -} sh_lb_liq_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_LOQ_CTL" */ /* Local Block LOQ Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_loq_ctl_u { mmr_t sh_lb_loq_ctl_regval; struct { @@ -4268,23 +2337,12 @@ mmr_t reserved_0 : 62; } sh_lb_loq_ctl_s; } sh_lb_loq_ctl_u_t; -#else -typedef union sh_lb_loq_ctl_u { - mmr_t sh_lb_loq_ctl_regval; - struct { - mmr_t reserved_0 : 62; - mmr_t loq_rpl_ctl : 1; - mmr_t loq_req_ctl : 1; - } sh_lb_loq_ctl_s; -} sh_lb_loq_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_MAX_REP_CREDIT_CNT" */ /* Maximum number of reply credits from XN */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_max_rep_credit_cnt_u { mmr_t sh_lb_max_rep_credit_cnt_regval; struct { @@ -4292,22 +2350,12 @@ mmr_t reserved_0 : 59; } sh_lb_max_rep_credit_cnt_s; } sh_lb_max_rep_credit_cnt_u_t; -#else -typedef union sh_lb_max_rep_credit_cnt_u { - mmr_t sh_lb_max_rep_credit_cnt_regval; - struct { - mmr_t reserved_0 : 59; - mmr_t max_cnt : 5; - } sh_lb_max_rep_credit_cnt_s; -} sh_lb_max_rep_credit_cnt_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_MAX_REQ_CREDIT_CNT" */ /* Maximum number of request credits from XN */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_max_req_credit_cnt_u { mmr_t sh_lb_max_req_credit_cnt_regval; struct { @@ -4315,22 +2363,12 @@ mmr_t reserved_0 : 59; } sh_lb_max_req_credit_cnt_s; } sh_lb_max_req_credit_cnt_u_t; -#else -typedef union sh_lb_max_req_credit_cnt_u { - mmr_t sh_lb_max_req_credit_cnt_regval; - struct { - mmr_t reserved_0 : 59; - mmr_t max_cnt : 5; - } sh_lb_max_req_credit_cnt_s; -} sh_lb_max_req_credit_cnt_u_t; -#endif /* ==================================================================== */ /* Register "SH_PIO_TIME_OUT" */ /* Local Block PIO time out value */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pio_time_out_u { mmr_t sh_pio_time_out_regval; struct { @@ -4338,22 +2376,12 @@ mmr_t reserved_0 : 48; } sh_pio_time_out_s; } sh_pio_time_out_u_t; -#else -typedef union sh_pio_time_out_u { - mmr_t sh_pio_time_out_regval; - struct { - mmr_t reserved_0 : 48; - mmr_t value : 16; - } sh_pio_time_out_s; -} sh_pio_time_out_u_t; -#endif /* ==================================================================== */ /* Register "SH_PIO_NACK_RESET" */ /* Local Block PIO Reset for nack counters */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pio_nack_reset_u { mmr_t sh_pio_nack_reset_regval; struct { @@ -4361,22 +2389,12 @@ mmr_t reserved_0 : 63; } sh_pio_nack_reset_s; } sh_pio_nack_reset_u_t; -#else -typedef union sh_pio_nack_reset_u { - mmr_t sh_pio_nack_reset_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t pulse : 1; - } sh_pio_nack_reset_s; -} sh_pio_nack_reset_u_t; -#endif /* ==================================================================== */ /* Register "SH_CONVEYOR_BELT_TIME_OUT" */ /* Local Block conveyor belt time out value */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_conveyor_belt_time_out_u { mmr_t sh_conveyor_belt_time_out_regval; struct { @@ -4384,22 +2402,12 @@ mmr_t reserved_0 : 52; } sh_conveyor_belt_time_out_s; } sh_conveyor_belt_time_out_u_t; -#else -typedef union sh_conveyor_belt_time_out_u { - mmr_t sh_conveyor_belt_time_out_regval; - struct { - mmr_t reserved_0 : 52; - mmr_t value : 12; - } sh_conveyor_belt_time_out_s; -} sh_conveyor_belt_time_out_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_CREDIT_STATUS" */ /* Credit Counter Status Register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_credit_status_u { mmr_t sh_lb_credit_status_regval; struct { @@ -4413,28 +2421,12 @@ mmr_t reserved_2 : 36; } sh_lb_credit_status_s; } sh_lb_credit_status_u_t; -#else -typedef union sh_lb_credit_status_u { - mmr_t sh_lb_credit_status_regval; - struct { - mmr_t reserved_2 : 36; - mmr_t loq_rp_credit : 5; - mmr_t loq_rq_credit : 5; - mmr_t linvv_credit : 6; - mmr_t reserved_1 : 2; - mmr_t liq_rp_credit : 4; - mmr_t reserved_0 : 1; - mmr_t liq_rq_credit : 5; - } sh_lb_credit_status_s; -} sh_lb_credit_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_DEBUG_LOCAL_SEL" */ /* LB Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_debug_local_sel_u { mmr_t sh_lb_debug_local_sel_regval; struct { @@ -4472,52 +2464,12 @@ mmr_t trigger_enable : 1; } sh_lb_debug_local_sel_s; } sh_lb_debug_local_sel_u_t; -#else -typedef union sh_lb_debug_local_sel_u { - mmr_t sh_lb_debug_local_sel_regval; - struct { - mmr_t trigger_enable : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_chiplet_sel : 3; - } sh_lb_debug_local_sel_s; -} sh_lb_debug_local_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_DEBUG_PERF_SEL" */ /* LB Debug Port Performance Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_debug_perf_sel_u { mmr_t sh_lb_debug_perf_sel_regval; struct { @@ -4555,52 +2507,12 @@ mmr_t reserved_15 : 1; } sh_lb_debug_perf_sel_s; } sh_lb_debug_perf_sel_u_t; -#else -typedef union sh_lb_debug_perf_sel_u { - mmr_t sh_lb_debug_perf_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_chiplet_sel : 3; - } sh_lb_debug_perf_sel_s; -} sh_lb_debug_perf_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_DEBUG_TRIG_SEL" */ /* LB Debug Trigger Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_debug_trig_sel_u { mmr_t sh_lb_debug_trig_sel_regval; struct { @@ -4638,52 +2550,12 @@ mmr_t reserved_15 : 1; } sh_lb_debug_trig_sel_s; } sh_lb_debug_trig_sel_u_t; -#else -typedef union sh_lb_debug_trig_sel_u { - mmr_t sh_lb_debug_trig_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_chiplet_sel : 3; - } sh_lb_debug_trig_sel_s; -} sh_lb_debug_trig_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_DETAIL_1" */ /* LB Error capture information: HDR1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_error_detail_1_u { mmr_t sh_lb_error_detail_1_regval; struct { @@ -4700,31 +2572,12 @@ mmr_t valid : 1; } sh_lb_error_detail_1_s; } sh_lb_error_detail_1_u_t; -#else -typedef union sh_lb_error_detail_1_u { - mmr_t sh_lb_error_detail_1_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_3 : 13; - mmr_t data_err : 1; - mmr_t hdr_err : 1; - mmr_t reserved_2 : 5; - mmr_t dest : 3; - mmr_t reserved_1 : 2; - mmr_t source : 14; - mmr_t reserved_0 : 2; - mmr_t suppl : 14; - mmr_t command : 8; - } sh_lb_error_detail_1_s; -} sh_lb_error_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_DETAIL_2" */ /* LB Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_error_detail_2_u { mmr_t sh_lb_error_detail_2_regval; struct { @@ -4732,64 +2585,36 @@ mmr_t reserved_0 : 17; } sh_lb_error_detail_2_s; } sh_lb_error_detail_2_u_t; -#else -typedef union sh_lb_error_detail_2_u { - mmr_t sh_lb_error_detail_2_regval; - struct { - mmr_t reserved_0 : 17; - mmr_t address : 47; - } sh_lb_error_detail_2_s; -} sh_lb_error_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_DETAIL_3" */ /* LB Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_lb_error_detail_3_u { - mmr_t sh_lb_error_detail_3_regval; - struct { - mmr_t data : 64; - } sh_lb_error_detail_3_s; -} sh_lb_error_detail_3_u_t; -#else typedef union sh_lb_error_detail_3_u { mmr_t sh_lb_error_detail_3_regval; struct { mmr_t data : 64; } sh_lb_error_detail_3_s; } sh_lb_error_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_DETAIL_4" */ /* LB Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_lb_error_detail_4_u { - mmr_t sh_lb_error_detail_4_regval; - struct { - mmr_t route : 64; - } sh_lb_error_detail_4_s; -} sh_lb_error_detail_4_u_t; -#else typedef union sh_lb_error_detail_4_u { mmr_t sh_lb_error_detail_4_regval; struct { mmr_t route : 64; } sh_lb_error_detail_4_s; } sh_lb_error_detail_4_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_DETAIL_5" */ /* LB Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_error_detail_5_u { mmr_t sh_lb_error_detail_5_regval; struct { @@ -4803,28 +2628,12 @@ mmr_t reserved_0 : 57; } sh_lb_error_detail_5_s; } sh_lb_error_detail_5_u_t; -#else -typedef union sh_lb_error_detail_5_u { - mmr_t sh_lb_error_detail_5_regval; - struct { - mmr_t reserved_0 : 57; - mmr_t nack_b_timeout : 1; - mmr_t nack_a_timeout : 1; - mmr_t count_b_overflow : 1; - mmr_t count_a_overflow : 1; - mmr_t write_retry : 1; - mmr_t ptc1_write : 1; - mmr_t read_retry : 1; - } sh_lb_error_detail_5_s; -} sh_lb_error_detail_5_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_MASK" */ /* LB Error Mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_error_mask_u { mmr_t sh_lb_error_mask_regval; struct { @@ -4854,44 +2663,12 @@ mmr_t reserved_0 : 41; } sh_lb_error_mask_s; } sh_lb_error_mask_u_t; -#else -typedef union sh_lb_error_mask_u { - mmr_t sh_lb_error_mask_regval; - struct { - mmr_t reserved_0 : 41; - mmr_t rp_credit_overflow : 1; - mmr_t rq_credit_overflow : 1; - mmr_t unexp_valid : 1; - mmr_t rp_fifo_error : 1; - mmr_t rq_fifo_error : 1; - mmr_t gclk_drop : 1; - mmr_t vector_rp_route_error : 1; - mmr_t vector_rq_route_error : 1; - mmr_t pio_cb_err : 1; - mmr_t junk_bus_err : 1; - mmr_t ptc_1_timeout : 1; - mmr_t unexpected_linv : 1; - mmr_t linvv_overflow : 1; - mmr_t rq_time_out : 1; - mmr_t rq_bad_addr : 1; - mmr_t rp_bad_data : 1; - mmr_t rq_bad_data : 1; - mmr_t rp_long : 1; - mmr_t rq_long : 1; - mmr_t rp_short : 1; - mmr_t rq_short : 1; - mmr_t rp_bad_cmd : 1; - mmr_t rq_bad_cmd : 1; - } sh_lb_error_mask_s; -} sh_lb_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_OVERFLOW" */ /* LB Error Overflow */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_error_overflow_u { mmr_t sh_lb_error_overflow_regval; struct { @@ -4921,44 +2698,12 @@ mmr_t reserved_0 : 41; } sh_lb_error_overflow_s; } sh_lb_error_overflow_u_t; -#else -typedef union sh_lb_error_overflow_u { - mmr_t sh_lb_error_overflow_regval; - struct { - mmr_t reserved_0 : 41; - mmr_t rp_credit_overflow_ovrfl : 1; - mmr_t rq_credit_overflow_ovrfl : 1; - mmr_t unexp_valid_ovrfl : 1; - mmr_t rp_fifo_error_ovrfl : 1; - mmr_t rq_fifo_error_ovrfl : 1; - mmr_t gclk_drop_ovrfl : 1; - mmr_t vector_rp_route_error_ovrfl : 1; - mmr_t vector_rq_route_error_ovrfl : 1; - mmr_t pio_cb_err_ovrfl : 1; - mmr_t junk_bus_err_ovrfl : 1; - mmr_t ptc_1_timeout_ovrfl : 1; - mmr_t unexpected_linv_ovrfl : 1; - mmr_t linvv_overflow_ovrfl : 1; - mmr_t rq_time_out_ovrfl : 1; - mmr_t rq_bad_addr_ovrfl : 1; - mmr_t rp_bad_data_ovrfl : 1; - mmr_t rq_bad_data_ovrfl : 1; - mmr_t rp_long_ovrfl : 1; - mmr_t rq_long_ovrfl : 1; - mmr_t rp_short_ovrfl : 1; - mmr_t rq_short_ovrfl : 1; - mmr_t rp_bad_cmd_ovrfl : 1; - mmr_t rq_bad_cmd_ovrfl : 1; - } sh_lb_error_overflow_s; -} sh_lb_error_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_ERROR_SUMMARY" */ /* LB Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_error_summary_u { mmr_t sh_lb_error_summary_regval; struct { @@ -4988,44 +2733,12 @@ mmr_t reserved_0 : 41; } sh_lb_error_summary_s; } sh_lb_error_summary_u_t; -#else -typedef union sh_lb_error_summary_u { - mmr_t sh_lb_error_summary_regval; - struct { - mmr_t reserved_0 : 41; - mmr_t rp_credit_overflow : 1; - mmr_t rq_credit_overflow : 1; - mmr_t unexp_valid : 1; - mmr_t rp_fifo_error : 1; - mmr_t rq_fifo_error : 1; - mmr_t gclk_drop : 1; - mmr_t vector_rp_route_error : 1; - mmr_t vector_rq_route_error : 1; - mmr_t pio_cb_err : 1; - mmr_t junk_bus_err : 1; - mmr_t ptc_1_timeout : 1; - mmr_t unexpected_linv : 1; - mmr_t linvv_overflow : 1; - mmr_t rq_time_out : 1; - mmr_t rq_bad_addr : 1; - mmr_t rp_bad_data : 1; - mmr_t rq_bad_data : 1; - mmr_t rp_long : 1; - mmr_t rq_long : 1; - mmr_t rp_short : 1; - mmr_t rq_short : 1; - mmr_t rp_bad_cmd : 1; - mmr_t rq_bad_cmd : 1; - } sh_lb_error_summary_s; -} sh_lb_error_summary_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_FIRST_ERROR" */ /* LB First Error */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_first_error_u { mmr_t sh_lb_first_error_regval; struct { @@ -5055,44 +2768,12 @@ mmr_t reserved_0 : 41; } sh_lb_first_error_s; } sh_lb_first_error_u_t; -#else -typedef union sh_lb_first_error_u { - mmr_t sh_lb_first_error_regval; - struct { - mmr_t reserved_0 : 41; - mmr_t rp_credit_overflow : 1; - mmr_t rq_credit_overflow : 1; - mmr_t unexp_valid : 1; - mmr_t rp_fifo_error : 1; - mmr_t rq_fifo_error : 1; - mmr_t gclk_drop : 1; - mmr_t vector_rp_route_error : 1; - mmr_t vector_rq_route_error : 1; - mmr_t pio_cb_err : 1; - mmr_t junk_bus_err : 1; - mmr_t ptc_1_timeout : 1; - mmr_t unexpected_linv : 1; - mmr_t linvv_overflow : 1; - mmr_t rq_time_out : 1; - mmr_t rq_bad_addr : 1; - mmr_t rp_bad_data : 1; - mmr_t rq_bad_data : 1; - mmr_t rp_long : 1; - mmr_t rq_long : 1; - mmr_t rp_short : 1; - mmr_t rq_short : 1; - mmr_t rp_bad_cmd : 1; - mmr_t rq_bad_cmd : 1; - } sh_lb_first_error_s; -} sh_lb_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_LAST_CREDIT" */ /* Credit counter status register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_last_credit_u { mmr_t sh_lb_last_credit_regval; struct { @@ -5106,28 +2787,12 @@ mmr_t reserved_2 : 36; } sh_lb_last_credit_s; } sh_lb_last_credit_u_t; -#else -typedef union sh_lb_last_credit_u { - mmr_t sh_lb_last_credit_regval; - struct { - mmr_t reserved_2 : 36; - mmr_t loq_rp_credit : 5; - mmr_t loq_rq_credit : 5; - mmr_t linvv_credit : 6; - mmr_t reserved_1 : 2; - mmr_t liq_rp_credit : 4; - mmr_t reserved_0 : 1; - mmr_t liq_rq_credit : 5; - } sh_lb_last_credit_s; -} sh_lb_last_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_NACK_STATUS" */ /* Nack Counter Status Register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_nack_status_u { mmr_t sh_lb_nack_status_regval; struct { @@ -5141,28 +2806,12 @@ mmr_t reserved_2 : 2; } sh_lb_nack_status_s; } sh_lb_nack_status_u_t; -#else -typedef union sh_lb_nack_status_u { - mmr_t sh_lb_nack_status_regval; - struct { - mmr_t reserved_2 : 2; - mmr_t cb_state : 2; - mmr_t cb_timeout_count : 12; - mmr_t junk_nack : 16; - mmr_t reserved_1 : 4; - mmr_t pio_nack_b : 12; - mmr_t reserved_0 : 4; - mmr_t pio_nack_a : 12; - } sh_lb_nack_status_s; -} sh_lb_nack_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_TRIGGER_COMPARE" */ /* LB Test-point Trigger Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_trigger_compare_u { mmr_t sh_lb_trigger_compare_regval; struct { @@ -5170,22 +2819,12 @@ mmr_t reserved_0 : 32; } sh_lb_trigger_compare_s; } sh_lb_trigger_compare_u_t; -#else -typedef union sh_lb_trigger_compare_u { - mmr_t sh_lb_trigger_compare_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t mask : 32; - } sh_lb_trigger_compare_s; -} sh_lb_trigger_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_TRIGGER_DATA" */ /* LB Test-point Trigger Compare Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_trigger_data_u { mmr_t sh_lb_trigger_data_regval; struct { @@ -5193,22 +2832,12 @@ mmr_t reserved_0 : 32; } sh_lb_trigger_data_s; } sh_lb_trigger_data_u_t; -#else -typedef union sh_lb_trigger_data_u { - mmr_t sh_lb_trigger_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t compare_pattern : 32; - } sh_lb_trigger_data_s; -} sh_lb_trigger_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AEC_CONFIG" */ /* PI Adaptive Error Correction Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_aec_config_u { mmr_t sh_pi_aec_config_regval; struct { @@ -5216,22 +2845,12 @@ mmr_t reserved_0 : 61; } sh_pi_aec_config_s; } sh_pi_aec_config_u_t; -#else -typedef union sh_pi_aec_config_u { - mmr_t sh_pi_aec_config_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t mode : 3; - } sh_pi_aec_config_s; -} sh_pi_aec_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AFI_ERROR_MASK" */ /* PI AFI Error Mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_afi_error_mask_u { mmr_t sh_pi_afi_error_mask_regval; struct { @@ -5253,36 +2872,12 @@ mmr_t reserved_1 : 29; } sh_pi_afi_error_mask_s; } sh_pi_afi_error_mask_u_t; -#else -typedef union sh_pi_afi_error_mask_u { - mmr_t sh_pi_afi_error_mask_regval; - struct { - mmr_t reserved_1 : 29; - mmr_t msg_len : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t bad_snoop : 1; - mmr_t livelock : 1; - mmr_t shub_fsb_ce : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t addr_parity : 1; - mmr_t req_parity : 1; - mmr_t addr_access : 1; - mmr_t req_format : 1; - mmr_t ioq_overrun : 1; - mmr_t rsp_parity : 1; - mmr_t hung_bus : 1; - mmr_t reserved_0 : 21; - } sh_pi_afi_error_mask_s; -} sh_pi_afi_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AFI_TEST_POINT_COMPARE" */ /* PI AFI Test Point Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_afi_test_point_compare_u { mmr_t sh_pi_afi_test_point_compare_regval; struct { @@ -5290,22 +2885,12 @@ mmr_t compare_pattern : 32; } sh_pi_afi_test_point_compare_s; } sh_pi_afi_test_point_compare_u_t; -#else -typedef union sh_pi_afi_test_point_compare_u { - mmr_t sh_pi_afi_test_point_compare_regval; - struct { - mmr_t compare_pattern : 32; - mmr_t compare_mask : 32; - } sh_pi_afi_test_point_compare_s; -} sh_pi_afi_test_point_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AFI_TEST_POINT_SELECT" */ /* PI AFI Test Point Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_afi_test_point_select_u { mmr_t sh_pi_afi_test_point_select_regval; struct { @@ -5335,44 +2920,12 @@ mmr_t trigger_enable : 1; } sh_pi_afi_test_point_select_s; } sh_pi_afi_test_point_select_u_t; -#else -typedef union sh_pi_afi_test_point_select_u { - mmr_t sh_pi_afi_test_point_select_regval; - struct { - mmr_t trigger_enable : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t nibble7_chiplet_sel : 4; - mmr_t reserved_6 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t nibble6_chiplet_sel : 4; - mmr_t reserved_5 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t nibble5_chiplet_sel : 4; - mmr_t reserved_4 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t nibble4_chiplet_sel : 4; - mmr_t reserved_3 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t nibble3_chiplet_sel : 4; - mmr_t reserved_2 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t nibble2_chiplet_sel : 4; - mmr_t reserved_1 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t nibble1_chiplet_sel : 4; - mmr_t reserved_0 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t nibble0_chiplet_sel : 4; - } sh_pi_afi_test_point_select_s; -} sh_pi_afi_test_point_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AFI_TEST_POINT_TRIGGER_SELECT" */ /* PI CRBC Test Point Trigger Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_afi_test_point_trigger_select_u { mmr_t sh_pi_afi_test_point_trigger_select_regval; struct { @@ -5402,44 +2955,12 @@ mmr_t reserved_7 : 1; } sh_pi_afi_test_point_trigger_select_s; } sh_pi_afi_test_point_trigger_select_u_t; -#else -typedef union sh_pi_afi_test_point_trigger_select_u { - mmr_t sh_pi_afi_test_point_trigger_select_regval; - struct { - mmr_t reserved_7 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t trigger7_chiplet_sel : 4; - mmr_t reserved_6 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t trigger6_chiplet_sel : 4; - mmr_t reserved_5 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t trigger5_chiplet_sel : 4; - mmr_t reserved_4 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t trigger4_chiplet_sel : 4; - mmr_t reserved_3 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t trigger3_chiplet_sel : 4; - mmr_t reserved_2 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t trigger2_chiplet_sel : 4; - mmr_t reserved_1 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t trigger1_chiplet_sel : 4; - mmr_t reserved_0 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t trigger0_chiplet_sel : 4; - } sh_pi_afi_test_point_trigger_select_s; -} sh_pi_afi_test_point_trigger_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AUTO_REPLY_ENABLE" */ /* PI Auto Reply Enable */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_auto_reply_enable_u { mmr_t sh_pi_auto_reply_enable_regval; struct { @@ -5447,22 +2968,12 @@ mmr_t reserved_0 : 63; } sh_pi_auto_reply_enable_s; } sh_pi_auto_reply_enable_u_t; -#else -typedef union sh_pi_auto_reply_enable_u { - mmr_t sh_pi_auto_reply_enable_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t auto_reply_enable : 1; - } sh_pi_auto_reply_enable_s; -} sh_pi_auto_reply_enable_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CAM_CONTROL" */ /* CRB CAM MMR Access Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_cam_control_u { mmr_t sh_pi_cam_control_regval; struct { @@ -5474,26 +2985,12 @@ mmr_t start : 1; } sh_pi_cam_control_s; } sh_pi_cam_control_u_t; -#else -typedef union sh_pi_cam_control_u { - mmr_t sh_pi_cam_control_regval; - struct { - mmr_t start : 1; - mmr_t reserved_1 : 53; - mmr_t rrb_rd_xfer_clear : 1; - mmr_t cam_write : 1; - mmr_t reserved_0 : 1; - mmr_t cam_indx : 7; - } sh_pi_cam_control_s; -} sh_pi_cam_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBC_TEST_POINT_COMPARE" */ /* PI CRBC Test Point Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbc_test_point_compare_u { mmr_t sh_pi_crbc_test_point_compare_regval; struct { @@ -5501,22 +2998,12 @@ mmr_t compare_pattern : 32; } sh_pi_crbc_test_point_compare_s; } sh_pi_crbc_test_point_compare_u_t; -#else -typedef union sh_pi_crbc_test_point_compare_u { - mmr_t sh_pi_crbc_test_point_compare_regval; - struct { - mmr_t compare_pattern : 32; - mmr_t compare_mask : 32; - } sh_pi_crbc_test_point_compare_s; -} sh_pi_crbc_test_point_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBC_TEST_POINT_SELECT" */ /* PI CRBC Test Point Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbc_test_point_select_u { mmr_t sh_pi_crbc_test_point_select_regval; struct { @@ -5554,52 +3041,12 @@ mmr_t trigger_enable : 1; } sh_pi_crbc_test_point_select_s; } sh_pi_crbc_test_point_select_u_t; -#else -typedef union sh_pi_crbc_test_point_select_u { - mmr_t sh_pi_crbc_test_point_select_regval; - struct { - mmr_t trigger_enable : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_chiplet_sel : 3; - } sh_pi_crbc_test_point_select_s; -} sh_pi_crbc_test_point_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT" */ /* PI CRBC Test Point Trigger Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbc_test_point_trigger_select_u { mmr_t sh_pi_crbc_test_point_trigger_select_regval; struct { @@ -5637,52 +3084,12 @@ mmr_t reserved_15 : 1; } sh_pi_crbc_test_point_trigger_select_s; } sh_pi_crbc_test_point_trigger_select_u_t; -#else -typedef union sh_pi_crbc_test_point_trigger_select_u { - mmr_t sh_pi_crbc_test_point_trigger_select_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_chiplet_sel : 3; - } sh_pi_crbc_test_point_trigger_select_s; -} sh_pi_crbc_test_point_trigger_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_ERROR_MASK" */ /* PI CRBP Error Mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_error_mask_u { mmr_t sh_pi_crbp_error_mask_regval; struct { @@ -5710,42 +3117,12 @@ mmr_t reserved_0 : 43; } sh_pi_crbp_error_mask_s; } sh_pi_crbp_error_mask_u_t; -#else -typedef union sh_pi_crbp_error_mask_u { - mmr_t sh_pi_crbp_error_mask_regval; - struct { - mmr_t reserved_0 : 43; - mmr_t xn_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t gfx_int_1 : 1; - mmr_t gfx_int_0 : 1; - mmr_t nack_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t msg_color_err : 1; - mmr_t fsb_shub_ce : 1; - mmr_t fsb_shub_uce : 1; - mmr_t pio_to_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t fsb_proto_err : 1; - } sh_pi_crbp_error_mask_s; -} sh_pi_crbp_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_FSB_PIPE_COMPARE" */ /* CRBP FSB Pipe Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_fsb_pipe_compare_u { mmr_t sh_pi_crbp_fsb_pipe_compare_regval; struct { @@ -5754,23 +3131,12 @@ mmr_t reserved_0 : 11; } sh_pi_crbp_fsb_pipe_compare_s; } sh_pi_crbp_fsb_pipe_compare_u_t; -#else -typedef union sh_pi_crbp_fsb_pipe_compare_u { - mmr_t sh_pi_crbp_fsb_pipe_compare_regval; - struct { - mmr_t reserved_0 : 11; - mmr_t compare_req : 6; - mmr_t compare_address : 47; - } sh_pi_crbp_fsb_pipe_compare_s; -} sh_pi_crbp_fsb_pipe_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_FSB_PIPE_MASK" */ /* CRBP Compare Mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_fsb_pipe_mask_u { mmr_t sh_pi_crbp_fsb_pipe_mask_regval; struct { @@ -5779,23 +3145,12 @@ mmr_t reserved_0 : 11; } sh_pi_crbp_fsb_pipe_mask_s; } sh_pi_crbp_fsb_pipe_mask_u_t; -#else -typedef union sh_pi_crbp_fsb_pipe_mask_u { - mmr_t sh_pi_crbp_fsb_pipe_mask_regval; - struct { - mmr_t reserved_0 : 11; - mmr_t compare_req_mask : 6; - mmr_t compare_address_mask : 47; - } sh_pi_crbp_fsb_pipe_mask_s; -} sh_pi_crbp_fsb_pipe_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_TEST_POINT_COMPARE" */ /* PI CRBP Test Point Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_test_point_compare_u { mmr_t sh_pi_crbp_test_point_compare_regval; struct { @@ -5803,22 +3158,12 @@ mmr_t compare_pattern : 32; } sh_pi_crbp_test_point_compare_s; } sh_pi_crbp_test_point_compare_u_t; -#else -typedef union sh_pi_crbp_test_point_compare_u { - mmr_t sh_pi_crbp_test_point_compare_regval; - struct { - mmr_t compare_pattern : 32; - mmr_t compare_mask : 32; - } sh_pi_crbp_test_point_compare_s; -} sh_pi_crbp_test_point_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_TEST_POINT_SELECT" */ /* PI CRBP Test Point Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_test_point_select_u { mmr_t sh_pi_crbp_test_point_select_regval; struct { @@ -5856,52 +3201,12 @@ mmr_t trigger_enable : 1; } sh_pi_crbp_test_point_select_s; } sh_pi_crbp_test_point_select_u_t; -#else -typedef union sh_pi_crbp_test_point_select_u { - mmr_t sh_pi_crbp_test_point_select_regval; - struct { - mmr_t trigger_enable : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_chiplet_sel : 3; - } sh_pi_crbp_test_point_select_s; -} sh_pi_crbp_test_point_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT" */ /* PI CRBP Test Point Trigger Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_test_point_trigger_select_u { mmr_t sh_pi_crbp_test_point_trigger_select_regval; struct { @@ -5939,52 +3244,12 @@ mmr_t reserved_15 : 1; } sh_pi_crbp_test_point_trigger_select_s; } sh_pi_crbp_test_point_trigger_select_u_t; -#else -typedef union sh_pi_crbp_test_point_trigger_select_u { - mmr_t sh_pi_crbp_test_point_trigger_select_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_chiplet_sel : 3; - } sh_pi_crbp_test_point_trigger_select_s; -} sh_pi_crbp_test_point_trigger_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_XB_PIPE_COMPARE_0" */ /* CRBP XB Pipe Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_xb_pipe_compare_0_u { mmr_t sh_pi_crbp_xb_pipe_compare_0_regval; struct { @@ -5993,23 +3258,12 @@ mmr_t reserved_0 : 9; } sh_pi_crbp_xb_pipe_compare_0_s; } sh_pi_crbp_xb_pipe_compare_0_u_t; -#else -typedef union sh_pi_crbp_xb_pipe_compare_0_u { - mmr_t sh_pi_crbp_xb_pipe_compare_0_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t compare_command : 8; - mmr_t compare_address : 47; - } sh_pi_crbp_xb_pipe_compare_0_s; -} sh_pi_crbp_xb_pipe_compare_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_XB_PIPE_COMPARE_1" */ /* CRBP XB Pipe Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_xb_pipe_compare_1_u { mmr_t sh_pi_crbp_xb_pipe_compare_1_regval; struct { @@ -6021,26 +3275,12 @@ mmr_t reserved_2 : 23; } sh_pi_crbp_xb_pipe_compare_1_s; } sh_pi_crbp_xb_pipe_compare_1_u_t; -#else -typedef union sh_pi_crbp_xb_pipe_compare_1_u { - mmr_t sh_pi_crbp_xb_pipe_compare_1_regval; - struct { - mmr_t reserved_2 : 23; - mmr_t compare_echo : 9; - mmr_t reserved_1 : 2; - mmr_t compare_supplemental : 14; - mmr_t reserved_0 : 2; - mmr_t compare_source : 14; - } sh_pi_crbp_xb_pipe_compare_1_s; -} sh_pi_crbp_xb_pipe_compare_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_XB_PIPE_MASK_0" */ /* CRBP Compare Mask Register 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_xb_pipe_mask_0_u { mmr_t sh_pi_crbp_xb_pipe_mask_0_regval; struct { @@ -6049,23 +3289,12 @@ mmr_t reserved_0 : 9; } sh_pi_crbp_xb_pipe_mask_0_s; } sh_pi_crbp_xb_pipe_mask_0_u_t; -#else -typedef union sh_pi_crbp_xb_pipe_mask_0_u { - mmr_t sh_pi_crbp_xb_pipe_mask_0_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t compare_command_mask : 8; - mmr_t compare_address_mask : 47; - } sh_pi_crbp_xb_pipe_mask_0_s; -} sh_pi_crbp_xb_pipe_mask_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_XB_PIPE_MASK_1" */ /* CRBP XB Pipe Compare Mask Register 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_xb_pipe_mask_1_u { mmr_t sh_pi_crbp_xb_pipe_mask_1_regval; struct { @@ -6077,26 +3306,12 @@ mmr_t reserved_2 : 23; } sh_pi_crbp_xb_pipe_mask_1_s; } sh_pi_crbp_xb_pipe_mask_1_u_t; -#else -typedef union sh_pi_crbp_xb_pipe_mask_1_u { - mmr_t sh_pi_crbp_xb_pipe_mask_1_regval; - struct { - mmr_t reserved_2 : 23; - mmr_t compare_echo_mask : 9; - mmr_t reserved_1 : 2; - mmr_t compare_supplemental_mask : 14; - mmr_t reserved_0 : 2; - mmr_t compare_source_mask : 14; - } sh_pi_crbp_xb_pipe_mask_1_s; -} sh_pi_crbp_xb_pipe_mask_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_DPC_QUEUE_CONFIG" */ /* DPC Queue Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_dpc_queue_config_u { mmr_t sh_pi_dpc_queue_config_regval; struct { @@ -6110,28 +3325,12 @@ mmr_t reserved_3 : 35; } sh_pi_dpc_queue_config_s; } sh_pi_dpc_queue_config_u_t; -#else -typedef union sh_pi_dpc_queue_config_u { - mmr_t sh_pi_dpc_queue_config_regval; - struct { - mmr_t reserved_3 : 35; - mmr_t fwcq_af_thresh : 5; - mmr_t reserved_2 : 3; - mmr_t fwcq_ae_level : 5; - mmr_t reserved_1 : 3; - mmr_t dwcq_af_thresh : 5; - mmr_t reserved_0 : 3; - mmr_t dwcq_ae_level : 5; - } sh_pi_dpc_queue_config_s; -} sh_pi_dpc_queue_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_ERROR_MASK" */ /* PI Error Mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_error_mask_u { mmr_t sh_pi_error_mask_regval; struct { @@ -6173,56 +3372,12 @@ mmr_t reserved_0 : 29; } sh_pi_error_mask_s; } sh_pi_error_mask_u_t; -#else -typedef union sh_pi_error_mask_u { - mmr_t sh_pi_error_mask_regval; - struct { - mmr_t reserved_0 : 29; - mmr_t msg_length : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t bad_snoop : 1; - mmr_t livelock : 1; - mmr_t shub_fsb_ce : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t addr_parity : 1; - mmr_t req_parity : 1; - mmr_t addr_access : 1; - mmr_t req_format : 1; - mmr_t ioq_overrun : 1; - mmr_t rsp_parity : 1; - mmr_t hung_bus : 1; - mmr_t xn_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t gfx_int_1 : 1; - mmr_t gfx_int_0 : 1; - mmr_t nack_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t msg_color_err : 1; - mmr_t fsb_shub_ce : 1; - mmr_t fsb_shub_uce : 1; - mmr_t pio_to_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t fsb_proto_err : 1; - } sh_pi_error_mask_s; -} sh_pi_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_EXPRESS_REPLY_CONFIG" */ /* PI Express Reply Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_express_reply_config_u { mmr_t sh_pi_express_reply_config_regval; struct { @@ -6230,64 +3385,36 @@ mmr_t reserved_0 : 61; } sh_pi_express_reply_config_s; } sh_pi_express_reply_config_u_t; -#else -typedef union sh_pi_express_reply_config_u { - mmr_t sh_pi_express_reply_config_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t mode : 3; - } sh_pi_express_reply_config_s; -} sh_pi_express_reply_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_FSB_COMPARE_VALUE" */ /* FSB Compare Value */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_pi_fsb_compare_value_u { - mmr_t sh_pi_fsb_compare_value_regval; - struct { - mmr_t compare_value : 64; - } sh_pi_fsb_compare_value_s; -} sh_pi_fsb_compare_value_u_t; -#else typedef union sh_pi_fsb_compare_value_u { mmr_t sh_pi_fsb_compare_value_regval; struct { mmr_t compare_value : 64; } sh_pi_fsb_compare_value_s; } sh_pi_fsb_compare_value_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_FSB_COMPARE_MASK" */ /* FSB Compare Mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_fsb_compare_mask_u { mmr_t sh_pi_fsb_compare_mask_regval; struct { mmr_t mask_value : 64; } sh_pi_fsb_compare_mask_s; } sh_pi_fsb_compare_mask_u_t; -#else -typedef union sh_pi_fsb_compare_mask_u { - mmr_t sh_pi_fsb_compare_mask_regval; - struct { - mmr_t mask_value : 64; - } sh_pi_fsb_compare_mask_s; -} sh_pi_fsb_compare_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_FSB_ERROR_INJECTION" */ /* Inject an Error onto the FSB */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_fsb_error_injection_u { mmr_t sh_pi_fsb_error_injection_regval; struct { @@ -6321,48 +3448,12 @@ mmr_t reserved_2 : 29; } sh_pi_fsb_error_injection_s; } sh_pi_fsb_error_injection_u_t; -#else -typedef union sh_pi_fsb_error_injection_u { - mmr_t sh_pi_fsb_error_injection_regval; - struct { - mmr_t reserved_2 : 29; - mmr_t bus_hang : 1; - mmr_t livelock : 1; - mmr_t ioq_overrun : 1; - mmr_t reserved_1 : 4; - mmr_t dw3_uce_from_fsb : 1; - mmr_t dw3_ce_from_fsb : 1; - mmr_t dw2_uce_from_fsb : 1; - mmr_t dw2_ce_from_fsb : 1; - mmr_t dw1_uce_from_fsb : 1; - mmr_t dw1_ce_from_fsb : 1; - mmr_t dw0_uce_from_fsb : 1; - mmr_t dw0_ce_from_fsb : 1; - mmr_t rsp_pe_from_fsb : 1; - mmr_t ap1_pe_from_fsb : 1; - mmr_t ap0_pe_from_fsb : 1; - mmr_t rp_pe_from_fsb : 1; - mmr_t reserved_0 : 6; - mmr_t ip1_pe_to_fsb : 1; - mmr_t ip0_pe_to_fsb : 1; - mmr_t dw1_uce_to_fsb : 1; - mmr_t dw1_ce_to_fsb : 1; - mmr_t dw0_uce_to_fsb : 1; - mmr_t dw0_ce_to_fsb : 1; - mmr_t rsp_pe_to_fsb : 1; - mmr_t ap1_pe_to_fsb : 1; - mmr_t ap0_pe_to_fsb : 1; - mmr_t rp_pe_to_fsb : 1; - } sh_pi_fsb_error_injection_s; -} sh_pi_fsb_error_injection_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_MD2PI_REPLY_VC_CONFIG" */ /* MD-to-PI Reply Virtual Channel Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_md2pi_reply_vc_config_u { mmr_t sh_pi_md2pi_reply_vc_config_regval; struct { @@ -6374,26 +3465,12 @@ mmr_t capture_credit_status : 1; } sh_pi_md2pi_reply_vc_config_s; } sh_pi_md2pi_reply_vc_config_u_t; -#else -typedef union sh_pi_md2pi_reply_vc_config_u { - mmr_t sh_pi_md2pi_reply_vc_config_regval; - struct { - mmr_t capture_credit_status : 1; - mmr_t force_credit : 1; - mmr_t reserved_0 : 48; - mmr_t max_credits : 6; - mmr_t data_depth : 4; - mmr_t hdr_depth : 4; - } sh_pi_md2pi_reply_vc_config_s; -} sh_pi_md2pi_reply_vc_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_MD2PI_REQUEST_VC_CONFIG" */ /* MD-to-PI Request Virtual Channel Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_md2pi_request_vc_config_u { mmr_t sh_pi_md2pi_request_vc_config_regval; struct { @@ -6405,26 +3482,12 @@ mmr_t capture_credit_status : 1; } sh_pi_md2pi_request_vc_config_s; } sh_pi_md2pi_request_vc_config_u_t; -#else -typedef union sh_pi_md2pi_request_vc_config_u { - mmr_t sh_pi_md2pi_request_vc_config_regval; - struct { - mmr_t capture_credit_status : 1; - mmr_t force_credit : 1; - mmr_t reserved_0 : 48; - mmr_t max_credits : 6; - mmr_t data_depth : 4; - mmr_t hdr_depth : 4; - } sh_pi_md2pi_request_vc_config_s; -} sh_pi_md2pi_request_vc_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_QUEUE_ERROR_INJECTION" */ /* PI Queue Error Injection */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_queue_error_injection_u { mmr_t sh_pi_queue_error_injection_regval; struct { @@ -6439,29 +3502,12 @@ mmr_t reserved_0 : 56; } sh_pi_queue_error_injection_s; } sh_pi_queue_error_injection_u_t; -#else -typedef union sh_pi_queue_error_injection_u { - mmr_t sh_pi_queue_error_injection_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t xnpi_rpy_bfr : 1; - mmr_t rxl_rdy_q : 1; - mmr_t rxl_kill_q : 1; - mmr_t ptc_intr : 1; - mmr_t mdpi_rpy_bfr : 1; - mmr_t fsb_wtl_cmnd_q : 1; - mmr_t dxb_wtl_cmnd_q : 1; - mmr_t dat_dfr_q : 1; - } sh_pi_queue_error_injection_s; -} sh_pi_queue_error_injection_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_TEST_POINT_COMPARE" */ /* PI Test Point Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_test_point_compare_u { mmr_t sh_pi_test_point_compare_regval; struct { @@ -6469,22 +3515,12 @@ mmr_t compare_pattern : 32; } sh_pi_test_point_compare_s; } sh_pi_test_point_compare_u_t; -#else -typedef union sh_pi_test_point_compare_u { - mmr_t sh_pi_test_point_compare_regval; - struct { - mmr_t compare_pattern : 32; - mmr_t compare_mask : 32; - } sh_pi_test_point_compare_s; -} sh_pi_test_point_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_TEST_POINT_SELECT" */ /* PI Test Point Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_test_point_select_u { mmr_t sh_pi_test_point_select_regval; struct { @@ -6522,52 +3558,12 @@ mmr_t trigger_enable : 1; } sh_pi_test_point_select_s; } sh_pi_test_point_select_u_t; -#else -typedef union sh_pi_test_point_select_u { - mmr_t sh_pi_test_point_select_regval; - struct { - mmr_t trigger_enable : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_chiplet_sel : 3; - } sh_pi_test_point_select_s; -} sh_pi_test_point_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_TEST_POINT_TRIGGER_SELECT" */ /* PI Test Point Trigger Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_test_point_trigger_select_u { mmr_t sh_pi_test_point_trigger_select_regval; struct { @@ -6605,52 +3601,12 @@ mmr_t reserved_15 : 1; } sh_pi_test_point_trigger_select_s; } sh_pi_test_point_trigger_select_u_t; -#else -typedef union sh_pi_test_point_trigger_select_u { - mmr_t sh_pi_test_point_trigger_select_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_chiplet_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_chiplet_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_chiplet_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_chiplet_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_chiplet_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_chiplet_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_chiplet_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_chiplet_sel : 3; - } sh_pi_test_point_trigger_select_s; -} sh_pi_test_point_trigger_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_XN2PI_REPLY_VC_CONFIG" */ /* XN-to-PI Reply Virtual Channel Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_xn2pi_reply_vc_config_u { mmr_t sh_pi_xn2pi_reply_vc_config_regval; struct { @@ -6662,26 +3618,12 @@ mmr_t capture_credit_status : 1; } sh_pi_xn2pi_reply_vc_config_s; } sh_pi_xn2pi_reply_vc_config_u_t; -#else -typedef union sh_pi_xn2pi_reply_vc_config_u { - mmr_t sh_pi_xn2pi_reply_vc_config_regval; - struct { - mmr_t capture_credit_status : 1; - mmr_t force_credit : 1; - mmr_t reserved_0 : 48; - mmr_t max_credits : 6; - mmr_t data_depth : 4; - mmr_t hdr_depth : 4; - } sh_pi_xn2pi_reply_vc_config_s; -} sh_pi_xn2pi_reply_vc_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_XN2PI_REQUEST_VC_CONFIG" */ /* XN-to-PI Request Virtual Channel Configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_xn2pi_request_vc_config_u { mmr_t sh_pi_xn2pi_request_vc_config_regval; struct { @@ -6693,26 +3635,12 @@ mmr_t capture_credit_status : 1; } sh_pi_xn2pi_request_vc_config_s; } sh_pi_xn2pi_request_vc_config_u_t; -#else -typedef union sh_pi_xn2pi_request_vc_config_u { - mmr_t sh_pi_xn2pi_request_vc_config_regval; - struct { - mmr_t capture_credit_status : 1; - mmr_t force_credit : 1; - mmr_t reserved_0 : 48; - mmr_t max_credits : 6; - mmr_t data_depth : 4; - mmr_t hdr_depth : 4; - } sh_pi_xn2pi_request_vc_config_s; -} sh_pi_xn2pi_request_vc_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AEC_STATUS" */ /* PI Adaptive Error Correction Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_aec_status_u { mmr_t sh_pi_aec_status_regval; struct { @@ -6720,22 +3648,12 @@ mmr_t reserved_0 : 61; } sh_pi_aec_status_s; } sh_pi_aec_status_u_t; -#else -typedef union sh_pi_aec_status_u { - mmr_t sh_pi_aec_status_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t state : 3; - } sh_pi_aec_status_s; -} sh_pi_aec_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_AFI_FIRST_ERROR" */ /* PI AFI First Error */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_afi_first_error_u { mmr_t sh_pi_afi_first_error_regval; struct { @@ -6760,39 +3678,12 @@ mmr_t reserved_2 : 29; } sh_pi_afi_first_error_s; } sh_pi_afi_first_error_u_t; -#else -typedef union sh_pi_afi_first_error_u { - mmr_t sh_pi_afi_first_error_regval; - struct { - mmr_t reserved_2 : 29; - mmr_t msg_len : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t bad_snoop : 1; - mmr_t livelock : 1; - mmr_t shub_fsb_ce : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t addr_parity : 1; - mmr_t req_parity : 1; - mmr_t addr_access : 1; - mmr_t req_format : 1; - mmr_t ioq_overrun : 1; - mmr_t rsp_parity : 1; - mmr_t hung_bus : 1; - mmr_t reserved_1 : 12; - mmr_t fsb_shub_ce : 1; - mmr_t fsb_shub_uce : 1; - mmr_t reserved_0 : 7; - } sh_pi_afi_first_error_s; -} sh_pi_afi_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CAM_ADDRESS_READ_DATA" */ /* CRB CAM MMR Address Read Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_cam_address_read_data_u { mmr_t sh_pi_cam_address_read_data_regval; struct { @@ -6801,44 +3692,24 @@ mmr_t cam_addr_val : 1; } sh_pi_cam_address_read_data_s; } sh_pi_cam_address_read_data_u_t; -#else -typedef union sh_pi_cam_address_read_data_u { - mmr_t sh_pi_cam_address_read_data_regval; - struct { - mmr_t cam_addr_val : 1; - mmr_t reserved_0 : 15; - mmr_t cam_addr : 48; - } sh_pi_cam_address_read_data_s; -} sh_pi_cam_address_read_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CAM_LPRA_READ_DATA" */ /* CRB CAM MMR LPRA Read Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_cam_lpra_read_data_u { mmr_t sh_pi_cam_lpra_read_data_regval; struct { mmr_t cam_lpra : 64; } sh_pi_cam_lpra_read_data_s; } sh_pi_cam_lpra_read_data_u_t; -#else -typedef union sh_pi_cam_lpra_read_data_u { - mmr_t sh_pi_cam_lpra_read_data_regval; - struct { - mmr_t cam_lpra : 64; - } sh_pi_cam_lpra_read_data_s; -} sh_pi_cam_lpra_read_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CAM_STATE_READ_DATA" */ /* CRB CAM MMR State Read Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_cam_state_read_data_u { mmr_t sh_pi_cam_state_read_data_regval; struct { @@ -6851,27 +3722,12 @@ mmr_t cam_rd_data_val : 1; } sh_pi_cam_state_read_data_s; } sh_pi_cam_state_read_data_u_t; -#else -typedef union sh_pi_cam_state_read_data_u { - mmr_t sh_pi_cam_state_read_data_regval; - struct { - mmr_t cam_rd_data_val : 1; - mmr_t reserved_1 : 13; - mmr_t cam_lpra : 18; - mmr_t reserved_0 : 26; - mmr_t cam_state_rd_pend : 1; - mmr_t cam_to : 1; - mmr_t cam_state : 4; - } sh_pi_cam_state_read_data_s; -} sh_pi_cam_state_read_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CORRECTED_DETAIL_1" */ /* PI Corrected Error Detail */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_corrected_detail_1_u { mmr_t sh_pi_corrected_detail_1_regval; struct { @@ -6880,44 +3736,24 @@ mmr_t dep : 8; } sh_pi_corrected_detail_1_s; } sh_pi_corrected_detail_1_u_t; -#else -typedef union sh_pi_corrected_detail_1_u { - mmr_t sh_pi_corrected_detail_1_regval; - struct { - mmr_t dep : 8; - mmr_t syndrome : 8; - mmr_t address : 48; - } sh_pi_corrected_detail_1_s; -} sh_pi_corrected_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CORRECTED_DETAIL_2" */ /* PI Corrected Error Detail 2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_pi_corrected_detail_2_u { - mmr_t sh_pi_corrected_detail_2_regval; - struct { - mmr_t data : 64; - } sh_pi_corrected_detail_2_s; -} sh_pi_corrected_detail_2_u_t; -#else typedef union sh_pi_corrected_detail_2_u { mmr_t sh_pi_corrected_detail_2_regval; struct { mmr_t data : 64; } sh_pi_corrected_detail_2_s; } sh_pi_corrected_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CORRECTED_DETAIL_3" */ /* PI Corrected Error Detail 3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_corrected_detail_3_u { mmr_t sh_pi_corrected_detail_3_regval; struct { @@ -6926,44 +3762,24 @@ mmr_t dep : 8; } sh_pi_corrected_detail_3_s; } sh_pi_corrected_detail_3_u_t; -#else -typedef union sh_pi_corrected_detail_3_u { - mmr_t sh_pi_corrected_detail_3_regval; - struct { - mmr_t dep : 8; - mmr_t syndrome : 8; - mmr_t address : 48; - } sh_pi_corrected_detail_3_s; -} sh_pi_corrected_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CORRECTED_DETAIL_4" */ /* PI Corrected Error Detail 4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_pi_corrected_detail_4_u { - mmr_t sh_pi_corrected_detail_4_regval; - struct { - mmr_t data : 64; - } sh_pi_corrected_detail_4_s; -} sh_pi_corrected_detail_4_u_t; -#else typedef union sh_pi_corrected_detail_4_u { mmr_t sh_pi_corrected_detail_4_regval; struct { mmr_t data : 64; } sh_pi_corrected_detail_4_s; } sh_pi_corrected_detail_4_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_CRBP_FIRST_ERROR" */ /* PI CRBP First Error */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_crbp_first_error_u { mmr_t sh_pi_crbp_first_error_regval; struct { @@ -6991,84 +3807,36 @@ mmr_t reserved_0 : 43; } sh_pi_crbp_first_error_s; } sh_pi_crbp_first_error_u_t; -#else -typedef union sh_pi_crbp_first_error_u { - mmr_t sh_pi_crbp_first_error_regval; - struct { - mmr_t reserved_0 : 43; - mmr_t xn_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t gfx_int_1 : 1; - mmr_t gfx_int_0 : 1; - mmr_t nack_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t msg_color_err : 1; - mmr_t fsb_shub_ce : 1; - mmr_t fsb_shub_uce : 1; - mmr_t pio_to_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t fsb_proto_err : 1; - } sh_pi_crbp_first_error_s; -} sh_pi_crbp_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_ERROR_DETAIL_1" */ /* PI Error Detail 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_pi_error_detail_1_u { - mmr_t sh_pi_error_detail_1_regval; - struct { - mmr_t status : 64; - } sh_pi_error_detail_1_s; -} sh_pi_error_detail_1_u_t; -#else typedef union sh_pi_error_detail_1_u { mmr_t sh_pi_error_detail_1_regval; struct { mmr_t status : 64; } sh_pi_error_detail_1_s; } sh_pi_error_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_ERROR_DETAIL_2" */ /* PI Error Detail 2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_pi_error_detail_2_u { - mmr_t sh_pi_error_detail_2_regval; - struct { - mmr_t status : 64; - } sh_pi_error_detail_2_s; -} sh_pi_error_detail_2_u_t; -#else typedef union sh_pi_error_detail_2_u { mmr_t sh_pi_error_detail_2_regval; struct { mmr_t status : 64; } sh_pi_error_detail_2_s; } sh_pi_error_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_ERROR_OVERFLOW" */ /* PI Error Overflow */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_error_overflow_u { mmr_t sh_pi_error_overflow_regval; struct { @@ -7110,56 +3878,12 @@ mmr_t reserved_0 : 29; } sh_pi_error_overflow_s; } sh_pi_error_overflow_u_t; -#else -typedef union sh_pi_error_overflow_u { - mmr_t sh_pi_error_overflow_regval; - struct { - mmr_t reserved_0 : 29; - mmr_t msg_length : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t bad_snoop : 1; - mmr_t livelock : 1; - mmr_t shub_fsb_ce : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t addr_parity : 1; - mmr_t req_parity : 1; - mmr_t addr_access : 1; - mmr_t req_format : 1; - mmr_t ioq_overrun : 1; - mmr_t rsp_parity : 1; - mmr_t hung_bus : 1; - mmr_t xn_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t gfx_int_1 : 1; - mmr_t gfx_int_0 : 1; - mmr_t nack_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t msg_color_err : 1; - mmr_t fsb_shub_ce : 1; - mmr_t fsb_shub_uce : 1; - mmr_t pio_to_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t fsb_proto_err : 1; - } sh_pi_error_overflow_s; -} sh_pi_error_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_ERROR_SUMMARY" */ /* PI Error Summary */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_error_summary_u { mmr_t sh_pi_error_summary_regval; struct { @@ -7201,56 +3925,12 @@ mmr_t reserved_0 : 29; } sh_pi_error_summary_s; } sh_pi_error_summary_u_t; -#else -typedef union sh_pi_error_summary_u { - mmr_t sh_pi_error_summary_regval; - struct { - mmr_t reserved_0 : 29; - mmr_t msg_length : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t bad_snoop : 1; - mmr_t livelock : 1; - mmr_t shub_fsb_ce : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t addr_parity : 1; - mmr_t req_parity : 1; - mmr_t addr_access : 1; - mmr_t req_format : 1; - mmr_t ioq_overrun : 1; - mmr_t rsp_parity : 1; - mmr_t hung_bus : 1; - mmr_t xn_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t gfx_int_1 : 1; - mmr_t gfx_int_0 : 1; - mmr_t nack_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t msg_color_err : 1; - mmr_t fsb_shub_ce : 1; - mmr_t fsb_shub_uce : 1; - mmr_t pio_to_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t fsb_proto_err : 1; - } sh_pi_error_summary_s; -} sh_pi_error_summary_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_EXPRESS_REPLY_STATUS" */ /* PI Express Reply Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_express_reply_status_u { mmr_t sh_pi_express_reply_status_regval; struct { @@ -7258,22 +3938,12 @@ mmr_t reserved_0 : 61; } sh_pi_express_reply_status_s; } sh_pi_express_reply_status_u_t; -#else -typedef union sh_pi_express_reply_status_u { - mmr_t sh_pi_express_reply_status_regval; - struct { - mmr_t reserved_0 : 61; - mmr_t state : 3; - } sh_pi_express_reply_status_s; -} sh_pi_express_reply_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_FIRST_ERROR" */ /* PI First Error */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_first_error_u { mmr_t sh_pi_first_error_regval; struct { @@ -7315,56 +3985,12 @@ mmr_t reserved_0 : 29; } sh_pi_first_error_s; } sh_pi_first_error_u_t; -#else -typedef union sh_pi_first_error_u { - mmr_t sh_pi_first_error_regval; - struct { - mmr_t reserved_0 : 29; - mmr_t msg_length : 1; - mmr_t fsb_tbl_miss : 1; - mmr_t bad_snoop : 1; - mmr_t livelock : 1; - mmr_t shub_fsb_ce : 1; - mmr_t shub_fsb_uce : 1; - mmr_t shub_fsb_dqe : 1; - mmr_t addr_parity : 1; - mmr_t req_parity : 1; - mmr_t addr_access : 1; - mmr_t req_format : 1; - mmr_t ioq_overrun : 1; - mmr_t rsp_parity : 1; - mmr_t hung_bus : 1; - mmr_t xn_rp_crd_oflow : 1; - mmr_t xn_rq_crd_oflow : 1; - mmr_t md_rp_crd_oflow : 1; - mmr_t md_rq_crd_oflow : 1; - mmr_t gfx_int_1 : 1; - mmr_t gfx_int_0 : 1; - mmr_t nack_oflow : 1; - mmr_t xn_rp_q_oflow : 1; - mmr_t xn_rq_q_oflow : 1; - mmr_t md_rp_q_oflow : 1; - mmr_t md_rq_q_oflow : 1; - mmr_t msg_color_err : 1; - mmr_t fsb_shub_ce : 1; - mmr_t fsb_shub_uce : 1; - mmr_t pio_to_err : 1; - mmr_t mem_to_err : 1; - mmr_t pio_rp_err : 1; - mmr_t mem_rp_err : 1; - mmr_t xb_proto_err : 1; - mmr_t gfx_rp_err : 1; - mmr_t fsb_proto_err : 1; - } sh_pi_first_error_s; -} sh_pi_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_PI2MD_REPLY_VC_STATUS" */ /* PI-to-MD Reply Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_pi2md_reply_vc_status_u { mmr_t sh_pi_pi2md_reply_vc_status_regval; struct { @@ -7372,22 +3998,12 @@ mmr_t reserved_0 : 58; } sh_pi_pi2md_reply_vc_status_s; } sh_pi_pi2md_reply_vc_status_u_t; -#else -typedef union sh_pi_pi2md_reply_vc_status_u { - mmr_t sh_pi_pi2md_reply_vc_status_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t output_crd_stat : 6; - } sh_pi_pi2md_reply_vc_status_s; -} sh_pi_pi2md_reply_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_PI2MD_REQUEST_VC_STATUS" */ /* PI-to-MD Request Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_pi2md_request_vc_status_u { mmr_t sh_pi_pi2md_request_vc_status_regval; struct { @@ -7395,22 +4011,12 @@ mmr_t reserved_0 : 58; } sh_pi_pi2md_request_vc_status_s; } sh_pi_pi2md_request_vc_status_u_t; -#else -typedef union sh_pi_pi2md_request_vc_status_u { - mmr_t sh_pi_pi2md_request_vc_status_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t output_crd_stat : 6; - } sh_pi_pi2md_request_vc_status_s; -} sh_pi_pi2md_request_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_PI2XN_REPLY_VC_STATUS" */ /* PI-to-XN Reply Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_pi2xn_reply_vc_status_u { mmr_t sh_pi_pi2xn_reply_vc_status_regval; struct { @@ -7418,22 +4024,12 @@ mmr_t reserved_0 : 58; } sh_pi_pi2xn_reply_vc_status_s; } sh_pi_pi2xn_reply_vc_status_u_t; -#else -typedef union sh_pi_pi2xn_reply_vc_status_u { - mmr_t sh_pi_pi2xn_reply_vc_status_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t output_crd_stat : 6; - } sh_pi_pi2xn_reply_vc_status_s; -} sh_pi_pi2xn_reply_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_PI2XN_REQUEST_VC_STATUS" */ /* PI-to-XN Request Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_pi2xn_request_vc_status_u { mmr_t sh_pi_pi2xn_request_vc_status_regval; struct { @@ -7441,22 +4037,12 @@ mmr_t reserved_0 : 58; } sh_pi_pi2xn_request_vc_status_s; } sh_pi_pi2xn_request_vc_status_u_t; -#else -typedef union sh_pi_pi2xn_request_vc_status_u { - mmr_t sh_pi_pi2xn_request_vc_status_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t output_crd_stat : 6; - } sh_pi_pi2xn_request_vc_status_s; -} sh_pi_pi2xn_request_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_UNCORRECTED_DETAIL_1" */ /* PI Uncorrected Error Detail 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_uncorrected_detail_1_u { mmr_t sh_pi_uncorrected_detail_1_regval; struct { @@ -7465,44 +4051,24 @@ mmr_t dep : 8; } sh_pi_uncorrected_detail_1_s; } sh_pi_uncorrected_detail_1_u_t; -#else -typedef union sh_pi_uncorrected_detail_1_u { - mmr_t sh_pi_uncorrected_detail_1_regval; - struct { - mmr_t dep : 8; - mmr_t syndrome : 8; - mmr_t address : 48; - } sh_pi_uncorrected_detail_1_s; -} sh_pi_uncorrected_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_UNCORRECTED_DETAIL_2" */ /* PI Uncorrected Error Detail 2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_uncorrected_detail_2_u { mmr_t sh_pi_uncorrected_detail_2_regval; struct { mmr_t data : 64; } sh_pi_uncorrected_detail_2_s; } sh_pi_uncorrected_detail_2_u_t; -#else -typedef union sh_pi_uncorrected_detail_2_u { - mmr_t sh_pi_uncorrected_detail_2_regval; - struct { - mmr_t data : 64; - } sh_pi_uncorrected_detail_2_s; -} sh_pi_uncorrected_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_UNCORRECTED_DETAIL_3" */ /* PI Uncorrected Error Detail 3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_uncorrected_detail_3_u { mmr_t sh_pi_uncorrected_detail_3_regval; struct { @@ -7511,44 +4077,24 @@ mmr_t dep : 8; } sh_pi_uncorrected_detail_3_s; } sh_pi_uncorrected_detail_3_u_t; -#else -typedef union sh_pi_uncorrected_detail_3_u { - mmr_t sh_pi_uncorrected_detail_3_regval; - struct { - mmr_t dep : 8; - mmr_t syndrome : 8; - mmr_t address : 48; - } sh_pi_uncorrected_detail_3_s; -} sh_pi_uncorrected_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_UNCORRECTED_DETAIL_4" */ /* PI Uncorrected Error Detail 4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_pi_uncorrected_detail_4_u { - mmr_t sh_pi_uncorrected_detail_4_regval; - struct { - mmr_t data : 64; - } sh_pi_uncorrected_detail_4_s; -} sh_pi_uncorrected_detail_4_u_t; -#else typedef union sh_pi_uncorrected_detail_4_u { mmr_t sh_pi_uncorrected_detail_4_regval; struct { mmr_t data : 64; } sh_pi_uncorrected_detail_4_s; } sh_pi_uncorrected_detail_4_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_MD2PI_REPLY_VC_STATUS" */ /* MD-to-PI Reply Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_md2pi_reply_vc_status_u { mmr_t sh_pi_md2pi_reply_vc_status_regval; struct { @@ -7558,24 +4104,12 @@ mmr_t reserved_0 : 52; } sh_pi_md2pi_reply_vc_status_s; } sh_pi_md2pi_reply_vc_status_u_t; -#else -typedef union sh_pi_md2pi_reply_vc_status_u { - mmr_t sh_pi_md2pi_reply_vc_status_regval; - struct { - mmr_t reserved_0 : 52; - mmr_t input_queue_stat : 4; - mmr_t input_dat_crd_stat : 4; - mmr_t input_hdr_crd_stat : 4; - } sh_pi_md2pi_reply_vc_status_s; -} sh_pi_md2pi_reply_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_MD2PI_REQUEST_VC_STATUS" */ /* MD-to-PI Request Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_md2pi_request_vc_status_u { mmr_t sh_pi_md2pi_request_vc_status_regval; struct { @@ -7585,24 +4119,12 @@ mmr_t reserved_0 : 52; } sh_pi_md2pi_request_vc_status_s; } sh_pi_md2pi_request_vc_status_u_t; -#else -typedef union sh_pi_md2pi_request_vc_status_u { - mmr_t sh_pi_md2pi_request_vc_status_regval; - struct { - mmr_t reserved_0 : 52; - mmr_t input_queue_stat : 4; - mmr_t input_dat_crd_stat : 4; - mmr_t input_hdr_crd_stat : 4; - } sh_pi_md2pi_request_vc_status_s; -} sh_pi_md2pi_request_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_XN2PI_REPLY_VC_STATUS" */ /* XN-to-PI Reply Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_xn2pi_reply_vc_status_u { mmr_t sh_pi_xn2pi_reply_vc_status_regval; struct { @@ -7612,24 +4134,12 @@ mmr_t reserved_0 : 52; } sh_pi_xn2pi_reply_vc_status_s; } sh_pi_xn2pi_reply_vc_status_u_t; -#else -typedef union sh_pi_xn2pi_reply_vc_status_u { - mmr_t sh_pi_xn2pi_reply_vc_status_regval; - struct { - mmr_t reserved_0 : 52; - mmr_t input_queue_stat : 4; - mmr_t input_dat_crd_stat : 4; - mmr_t input_hdr_crd_stat : 4; - } sh_pi_xn2pi_reply_vc_status_s; -} sh_pi_xn2pi_reply_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_XN2PI_REQUEST_VC_STATUS" */ /* XN-to-PI Request Virtual Channel Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_xn2pi_request_vc_status_u { mmr_t sh_pi_xn2pi_request_vc_status_regval; struct { @@ -7639,23 +4149,11 @@ mmr_t reserved_0 : 52; } sh_pi_xn2pi_request_vc_status_s; } sh_pi_xn2pi_request_vc_status_u_t; -#else -typedef union sh_pi_xn2pi_request_vc_status_u { - mmr_t sh_pi_xn2pi_request_vc_status_regval; - struct { - mmr_t reserved_0 : 52; - mmr_t input_queue_stat : 4; - mmr_t input_dat_crd_stat : 4; - mmr_t input_hdr_crd_stat : 4; - } sh_pi_xn2pi_request_vc_status_s; -} sh_pi_xn2pi_request_vc_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_SIC_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_sic_flow_u { mmr_t sh_xnpi_sic_flow_regval; struct { @@ -7680,38 +4178,11 @@ mmr_t disable_bypass_out : 1; } sh_xnpi_sic_flow_s; } sh_xnpi_sic_flow_u_t; -#else -typedef union sh_xnpi_sic_flow_u { - mmr_t sh_xnpi_sic_flow_regval; - struct { - mmr_t disable_bypass_out : 1; - mmr_t reserved_7 : 2; - mmr_t credit_vc2_cap : 5; - mmr_t reserved_6 : 3; - mmr_t credit_vc2_dyn : 5; - mmr_t reserved_5 : 3; - mmr_t credit_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t credit_vc0_cap : 5; - mmr_t reserved_3 : 3; - mmr_t credit_vc0_dyn : 5; - mmr_t reserved_2 : 3; - mmr_t credit_vc0_test : 5; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 2; - mmr_t debit_vc2_withhold : 5; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 2; - mmr_t debit_vc0_withhold : 5; - } sh_xnpi_sic_flow_s; -} sh_xnpi_sic_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_TO_NI0_PORT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_to_ni0_port_flow_u { mmr_t sh_xnpi_to_ni0_port_flow_regval; struct { @@ -7732,34 +4203,11 @@ mmr_t reserved_6 : 2; } sh_xnpi_to_ni0_port_flow_s; } sh_xnpi_to_ni0_port_flow_u_t; -#else -typedef union sh_xnpi_to_ni0_port_flow_u { - mmr_t sh_xnpi_to_ni0_port_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnpi_to_ni0_port_flow_s; -} sh_xnpi_to_ni0_port_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_TO_NI1_PORT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_to_ni1_port_flow_u { mmr_t sh_xnpi_to_ni1_port_flow_regval; struct { @@ -7780,34 +4228,11 @@ mmr_t reserved_6 : 2; } sh_xnpi_to_ni1_port_flow_s; } sh_xnpi_to_ni1_port_flow_u_t; -#else -typedef union sh_xnpi_to_ni1_port_flow_u { - mmr_t sh_xnpi_to_ni1_port_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnpi_to_ni1_port_flow_s; -} sh_xnpi_to_ni1_port_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_TO_IILB_PORT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_to_iilb_port_flow_u { mmr_t sh_xnpi_to_iilb_port_flow_regval; struct { @@ -7828,34 +4253,11 @@ mmr_t reserved_6 : 2; } sh_xnpi_to_iilb_port_flow_s; } sh_xnpi_to_iilb_port_flow_u_t; -#else -typedef union sh_xnpi_to_iilb_port_flow_u { - mmr_t sh_xnpi_to_iilb_port_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnpi_to_iilb_port_flow_s; -} sh_xnpi_to_iilb_port_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_FR_NI0_PORT_FLOW_FIFO" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_fr_ni0_port_flow_fifo_u { mmr_t sh_xnpi_fr_ni0_port_flow_fifo_regval; struct { @@ -7873,31 +4275,11 @@ mmr_t reserved_5 : 19; } sh_xnpi_fr_ni0_port_flow_fifo_s; } sh_xnpi_fr_ni0_port_flow_fifo_u_t; -#else -typedef union sh_xnpi_fr_ni0_port_flow_fifo_u { - mmr_t sh_xnpi_fr_ni0_port_flow_fifo_regval; - struct { - mmr_t reserved_5 : 19; - mmr_t entry_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc0_test : 5; - mmr_t reserved_3 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_dyn : 6; - } sh_xnpi_fr_ni0_port_flow_fifo_s; -} sh_xnpi_fr_ni0_port_flow_fifo_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_FR_NI1_PORT_FLOW_FIFO" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_fr_ni1_port_flow_fifo_u { mmr_t sh_xnpi_fr_ni1_port_flow_fifo_regval; struct { @@ -7915,31 +4297,11 @@ mmr_t reserved_5 : 19; } sh_xnpi_fr_ni1_port_flow_fifo_s; } sh_xnpi_fr_ni1_port_flow_fifo_u_t; -#else -typedef union sh_xnpi_fr_ni1_port_flow_fifo_u { - mmr_t sh_xnpi_fr_ni1_port_flow_fifo_regval; - struct { - mmr_t reserved_5 : 19; - mmr_t entry_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc0_test : 5; - mmr_t reserved_3 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_dyn : 6; - } sh_xnpi_fr_ni1_port_flow_fifo_s; -} sh_xnpi_fr_ni1_port_flow_fifo_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_FR_IILB_PORT_FLOW_FIFO" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_fr_iilb_port_flow_fifo_u { mmr_t sh_xnpi_fr_iilb_port_flow_fifo_regval; struct { @@ -7957,31 +4319,11 @@ mmr_t reserved_5 : 19; } sh_xnpi_fr_iilb_port_flow_fifo_s; } sh_xnpi_fr_iilb_port_flow_fifo_u_t; -#else -typedef union sh_xnpi_fr_iilb_port_flow_fifo_u { - mmr_t sh_xnpi_fr_iilb_port_flow_fifo_regval; - struct { - mmr_t reserved_5 : 19; - mmr_t entry_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc0_test : 5; - mmr_t reserved_3 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_dyn : 6; - } sh_xnpi_fr_iilb_port_flow_fifo_s; -} sh_xnpi_fr_iilb_port_flow_fifo_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_SIC_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_sic_flow_u { mmr_t sh_xnmd_sic_flow_regval; struct { @@ -8006,38 +4348,11 @@ mmr_t disable_bypass_out : 1; } sh_xnmd_sic_flow_s; } sh_xnmd_sic_flow_u_t; -#else -typedef union sh_xnmd_sic_flow_u { - mmr_t sh_xnmd_sic_flow_regval; - struct { - mmr_t disable_bypass_out : 1; - mmr_t reserved_7 : 2; - mmr_t credit_vc2_cap : 5; - mmr_t reserved_6 : 3; - mmr_t credit_vc2_dyn : 5; - mmr_t reserved_5 : 3; - mmr_t credit_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t credit_vc0_cap : 5; - mmr_t reserved_3 : 3; - mmr_t credit_vc0_dyn : 5; - mmr_t reserved_2 : 3; - mmr_t credit_vc0_test : 5; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 2; - mmr_t debit_vc2_withhold : 5; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 2; - mmr_t debit_vc0_withhold : 5; - } sh_xnmd_sic_flow_s; -} sh_xnmd_sic_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_TO_NI0_PORT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_to_ni0_port_flow_u { mmr_t sh_xnmd_to_ni0_port_flow_regval; struct { @@ -8058,34 +4373,11 @@ mmr_t reserved_6 : 2; } sh_xnmd_to_ni0_port_flow_s; } sh_xnmd_to_ni0_port_flow_u_t; -#else -typedef union sh_xnmd_to_ni0_port_flow_u { - mmr_t sh_xnmd_to_ni0_port_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnmd_to_ni0_port_flow_s; -} sh_xnmd_to_ni0_port_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_TO_NI1_PORT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_to_ni1_port_flow_u { mmr_t sh_xnmd_to_ni1_port_flow_regval; struct { @@ -8106,34 +4398,11 @@ mmr_t reserved_6 : 2; } sh_xnmd_to_ni1_port_flow_s; } sh_xnmd_to_ni1_port_flow_u_t; -#else -typedef union sh_xnmd_to_ni1_port_flow_u { - mmr_t sh_xnmd_to_ni1_port_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnmd_to_ni1_port_flow_s; -} sh_xnmd_to_ni1_port_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_TO_IILB_PORT_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_to_iilb_port_flow_u { mmr_t sh_xnmd_to_iilb_port_flow_regval; struct { @@ -8154,34 +4423,11 @@ mmr_t reserved_6 : 2; } sh_xnmd_to_iilb_port_flow_s; } sh_xnmd_to_iilb_port_flow_u_t; -#else -typedef union sh_xnmd_to_iilb_port_flow_u { - mmr_t sh_xnmd_to_iilb_port_flow_regval; - struct { - mmr_t reserved_6 : 2; - mmr_t credit_vc2_cap : 6; - mmr_t reserved_5 : 2; - mmr_t credit_vc2_dyn : 6; - mmr_t reserved_4 : 10; - mmr_t credit_vc0_cap : 6; - mmr_t reserved_3 : 2; - mmr_t credit_vc0_dyn : 6; - mmr_t reserved_2 : 8; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnmd_to_iilb_port_flow_s; -} sh_xnmd_to_iilb_port_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_FR_NI0_PORT_FLOW_FIFO" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_fr_ni0_port_flow_fifo_u { mmr_t sh_xnmd_fr_ni0_port_flow_fifo_regval; struct { @@ -8199,31 +4445,11 @@ mmr_t reserved_5 : 19; } sh_xnmd_fr_ni0_port_flow_fifo_s; } sh_xnmd_fr_ni0_port_flow_fifo_u_t; -#else -typedef union sh_xnmd_fr_ni0_port_flow_fifo_u { - mmr_t sh_xnmd_fr_ni0_port_flow_fifo_regval; - struct { - mmr_t reserved_5 : 19; - mmr_t entry_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc0_test : 5; - mmr_t reserved_3 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_dyn : 6; - } sh_xnmd_fr_ni0_port_flow_fifo_s; -} sh_xnmd_fr_ni0_port_flow_fifo_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_FR_NI1_PORT_FLOW_FIFO" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_fr_ni1_port_flow_fifo_u { mmr_t sh_xnmd_fr_ni1_port_flow_fifo_regval; struct { @@ -8241,31 +4467,11 @@ mmr_t reserved_5 : 19; } sh_xnmd_fr_ni1_port_flow_fifo_s; } sh_xnmd_fr_ni1_port_flow_fifo_u_t; -#else -typedef union sh_xnmd_fr_ni1_port_flow_fifo_u { - mmr_t sh_xnmd_fr_ni1_port_flow_fifo_regval; - struct { - mmr_t reserved_5 : 19; - mmr_t entry_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc0_test : 5; - mmr_t reserved_3 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_dyn : 6; - } sh_xnmd_fr_ni1_port_flow_fifo_s; -} sh_xnmd_fr_ni1_port_flow_fifo_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_FR_IILB_PORT_FLOW_FIFO" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_fr_iilb_port_flow_fifo_u { mmr_t sh_xnmd_fr_iilb_port_flow_fifo_regval; struct { @@ -8283,31 +4489,11 @@ mmr_t reserved_5 : 19; } sh_xnmd_fr_iilb_port_flow_fifo_s; } sh_xnmd_fr_iilb_port_flow_fifo_u_t; -#else -typedef union sh_xnmd_fr_iilb_port_flow_fifo_u { - mmr_t sh_xnmd_fr_iilb_port_flow_fifo_regval; - struct { - mmr_t reserved_5 : 19; - mmr_t entry_vc2_test : 5; - mmr_t reserved_4 : 3; - mmr_t entry_vc0_test : 5; - mmr_t reserved_3 : 2; - mmr_t entry_vc2_cap : 6; - mmr_t reserved_2 : 2; - mmr_t entry_vc2_dyn : 6; - mmr_t reserved_1 : 2; - mmr_t entry_vc0_cap : 6; - mmr_t reserved_0 : 2; - mmr_t entry_vc0_dyn : 6; - } sh_xnmd_fr_iilb_port_flow_fifo_s; -} sh_xnmd_fr_iilb_port_flow_fifo_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNII_INTRA_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnii_intra_flow_u { mmr_t sh_xnii_intra_flow_regval; struct { @@ -8331,37 +4517,11 @@ mmr_t reserved_7 : 1; } sh_xnii_intra_flow_s; } sh_xnii_intra_flow_u_t; -#else -typedef union sh_xnii_intra_flow_u { - mmr_t sh_xnii_intra_flow_regval; - struct { - mmr_t reserved_7 : 1; - mmr_t credit_vc2_cap : 7; - mmr_t reserved_6 : 1; - mmr_t credit_vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t credit_vc2_test : 7; - mmr_t reserved_4 : 1; - mmr_t credit_vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t credit_vc0_dyn : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc0_test : 7; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnii_intra_flow_s; -} sh_xnii_intra_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNLB_INTRA_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnlb_intra_flow_u { mmr_t sh_xnlb_intra_flow_regval; struct { @@ -8385,37 +4545,11 @@ mmr_t disable_bypass_in : 1; } sh_xnlb_intra_flow_s; } sh_xnlb_intra_flow_u_t; -#else -typedef union sh_xnlb_intra_flow_u { - mmr_t sh_xnlb_intra_flow_regval; - struct { - mmr_t disable_bypass_in : 1; - mmr_t credit_vc2_cap : 7; - mmr_t reserved_6 : 1; - mmr_t credit_vc2_dyn : 7; - mmr_t reserved_5 : 1; - mmr_t credit_vc2_test : 7; - mmr_t reserved_4 : 1; - mmr_t credit_vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t credit_vc0_dyn : 7; - mmr_t reserved_2 : 1; - mmr_t credit_vc0_test : 7; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t debit_vc2_withhold : 6; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnlb_intra_flow_s; -} sh_xnlb_intra_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_to_ni0_intra_flow_debit_u { mmr_t sh_xniilb_to_ni0_intra_flow_debit_regval; struct { @@ -8436,34 +4570,11 @@ mmr_t reserved_6 : 1; } sh_xniilb_to_ni0_intra_flow_debit_s; } sh_xniilb_to_ni0_intra_flow_debit_u_t; -#else -typedef union sh_xniilb_to_ni0_intra_flow_debit_u { - mmr_t sh_xniilb_to_ni0_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xniilb_to_ni0_intra_flow_debit_s; -} sh_xniilb_to_ni0_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_to_ni1_intra_flow_debit_u { mmr_t sh_xniilb_to_ni1_intra_flow_debit_regval; struct { @@ -8484,34 +4595,11 @@ mmr_t reserved_6 : 1; } sh_xniilb_to_ni1_intra_flow_debit_s; } sh_xniilb_to_ni1_intra_flow_debit_u_t; -#else -typedef union sh_xniilb_to_ni1_intra_flow_debit_u { - mmr_t sh_xniilb_to_ni1_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xniilb_to_ni1_intra_flow_debit_s; -} sh_xniilb_to_ni1_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_to_md_intra_flow_debit_u { mmr_t sh_xniilb_to_md_intra_flow_debit_regval; struct { @@ -8532,34 +4620,11 @@ mmr_t reserved_6 : 1; } sh_xniilb_to_md_intra_flow_debit_s; } sh_xniilb_to_md_intra_flow_debit_u_t; -#else -typedef union sh_xniilb_to_md_intra_flow_debit_u { - mmr_t sh_xniilb_to_md_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xniilb_to_md_intra_flow_debit_s; -} sh_xniilb_to_md_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_to_iilb_intra_flow_debit_u { mmr_t sh_xniilb_to_iilb_intra_flow_debit_regval; struct { @@ -8580,34 +4645,11 @@ mmr_t reserved_6 : 1; } sh_xniilb_to_iilb_intra_flow_debit_s; } sh_xniilb_to_iilb_intra_flow_debit_u_t; -#else -typedef union sh_xniilb_to_iilb_intra_flow_debit_u { - mmr_t sh_xniilb_to_iilb_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xniilb_to_iilb_intra_flow_debit_s; -} sh_xniilb_to_iilb_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_to_pi_intra_flow_debit_u { mmr_t sh_xniilb_to_pi_intra_flow_debit_regval; struct { @@ -8628,34 +4670,11 @@ mmr_t reserved_6 : 1; } sh_xniilb_to_pi_intra_flow_debit_s; } sh_xniilb_to_pi_intra_flow_debit_u_t; -#else -typedef union sh_xniilb_to_pi_intra_flow_debit_u { - mmr_t sh_xniilb_to_pi_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xniilb_to_pi_intra_flow_debit_s; -} sh_xniilb_to_pi_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_fr_ni0_intra_flow_credit_u { mmr_t sh_xniilb_fr_ni0_intra_flow_credit_regval; struct { @@ -8673,31 +4692,11 @@ mmr_t reserved_5 : 17; } sh_xniilb_fr_ni0_intra_flow_credit_s; } sh_xniilb_fr_ni0_intra_flow_credit_u_t; -#else -typedef union sh_xniilb_fr_ni0_intra_flow_credit_u { - mmr_t sh_xniilb_fr_ni0_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xniilb_fr_ni0_intra_flow_credit_s; -} sh_xniilb_fr_ni0_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_fr_ni1_intra_flow_credit_u { mmr_t sh_xniilb_fr_ni1_intra_flow_credit_regval; struct { @@ -8715,31 +4714,11 @@ mmr_t reserved_5 : 17; } sh_xniilb_fr_ni1_intra_flow_credit_s; } sh_xniilb_fr_ni1_intra_flow_credit_u_t; -#else -typedef union sh_xniilb_fr_ni1_intra_flow_credit_u { - mmr_t sh_xniilb_fr_ni1_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xniilb_fr_ni1_intra_flow_credit_s; -} sh_xniilb_fr_ni1_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_fr_md_intra_flow_credit_u { mmr_t sh_xniilb_fr_md_intra_flow_credit_regval; struct { @@ -8757,31 +4736,11 @@ mmr_t reserved_5 : 17; } sh_xniilb_fr_md_intra_flow_credit_s; } sh_xniilb_fr_md_intra_flow_credit_u_t; -#else -typedef union sh_xniilb_fr_md_intra_flow_credit_u { - mmr_t sh_xniilb_fr_md_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xniilb_fr_md_intra_flow_credit_s; -} sh_xniilb_fr_md_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_fr_iilb_intra_flow_credit_u { mmr_t sh_xniilb_fr_iilb_intra_flow_credit_regval; struct { @@ -8799,31 +4758,11 @@ mmr_t reserved_5 : 17; } sh_xniilb_fr_iilb_intra_flow_credit_s; } sh_xniilb_fr_iilb_intra_flow_credit_u_t; -#else -typedef union sh_xniilb_fr_iilb_intra_flow_credit_u { - mmr_t sh_xniilb_fr_iilb_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xniilb_fr_iilb_intra_flow_credit_s; -} sh_xniilb_fr_iilb_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_fr_pi_intra_flow_credit_u { mmr_t sh_xniilb_fr_pi_intra_flow_credit_regval; struct { @@ -8841,31 +4780,11 @@ mmr_t reserved_5 : 17; } sh_xniilb_fr_pi_intra_flow_credit_s; } sh_xniilb_fr_pi_intra_flow_credit_u_t; -#else -typedef union sh_xniilb_fr_pi_intra_flow_credit_u { - mmr_t sh_xniilb_fr_pi_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xniilb_fr_pi_intra_flow_credit_s; -} sh_xniilb_fr_pi_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_to_pi_intra_flow_debit_u { mmr_t sh_xnni0_to_pi_intra_flow_debit_regval; struct { @@ -8886,34 +4805,11 @@ mmr_t reserved_6 : 1; } sh_xnni0_to_pi_intra_flow_debit_s; } sh_xnni0_to_pi_intra_flow_debit_u_t; -#else -typedef union sh_xnni0_to_pi_intra_flow_debit_u { - mmr_t sh_xnni0_to_pi_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xnni0_to_pi_intra_flow_debit_s; -} sh_xnni0_to_pi_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_to_md_intra_flow_debit_u { mmr_t sh_xnni0_to_md_intra_flow_debit_regval; struct { @@ -8934,34 +4830,11 @@ mmr_t reserved_6 : 1; } sh_xnni0_to_md_intra_flow_debit_s; } sh_xnni0_to_md_intra_flow_debit_u_t; -#else -typedef union sh_xnni0_to_md_intra_flow_debit_u { - mmr_t sh_xnni0_to_md_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xnni0_to_md_intra_flow_debit_s; -} sh_xnni0_to_md_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_to_iilb_intra_flow_debit_u { mmr_t sh_xnni0_to_iilb_intra_flow_debit_regval; struct { @@ -8982,34 +4855,11 @@ mmr_t reserved_6 : 1; } sh_xnni0_to_iilb_intra_flow_debit_s; } sh_xnni0_to_iilb_intra_flow_debit_u_t; -#else -typedef union sh_xnni0_to_iilb_intra_flow_debit_u { - mmr_t sh_xnni0_to_iilb_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xnni0_to_iilb_intra_flow_debit_s; -} sh_xnni0_to_iilb_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_fr_pi_intra_flow_credit_u { mmr_t sh_xnni0_fr_pi_intra_flow_credit_regval; struct { @@ -9027,31 +4877,11 @@ mmr_t reserved_5 : 17; } sh_xnni0_fr_pi_intra_flow_credit_s; } sh_xnni0_fr_pi_intra_flow_credit_u_t; -#else -typedef union sh_xnni0_fr_pi_intra_flow_credit_u { - mmr_t sh_xnni0_fr_pi_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xnni0_fr_pi_intra_flow_credit_s; -} sh_xnni0_fr_pi_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_fr_md_intra_flow_credit_u { mmr_t sh_xnni0_fr_md_intra_flow_credit_regval; struct { @@ -9069,31 +4899,11 @@ mmr_t reserved_5 : 17; } sh_xnni0_fr_md_intra_flow_credit_s; } sh_xnni0_fr_md_intra_flow_credit_u_t; -#else -typedef union sh_xnni0_fr_md_intra_flow_credit_u { - mmr_t sh_xnni0_fr_md_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xnni0_fr_md_intra_flow_credit_s; -} sh_xnni0_fr_md_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_fr_iilb_intra_flow_credit_u { mmr_t sh_xnni0_fr_iilb_intra_flow_credit_regval; struct { @@ -9111,31 +4921,11 @@ mmr_t reserved_5 : 17; } sh_xnni0_fr_iilb_intra_flow_credit_s; } sh_xnni0_fr_iilb_intra_flow_credit_u_t; -#else -typedef union sh_xnni0_fr_iilb_intra_flow_credit_u { - mmr_t sh_xnni0_fr_iilb_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xnni0_fr_iilb_intra_flow_credit_s; -} sh_xnni0_fr_iilb_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_0_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_0_intrani_flow_u { mmr_t sh_xnni0_0_intrani_flow_regval; struct { @@ -9145,23 +4935,11 @@ mmr_t reserved_1 : 56; } sh_xnni0_0_intrani_flow_s; } sh_xnni0_0_intrani_flow_u_t; -#else -typedef union sh_xnni0_0_intrani_flow_u { - mmr_t sh_xnni0_0_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni0_0_intrani_flow_s; -} sh_xnni0_0_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_1_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_1_intrani_flow_u { mmr_t sh_xnni0_1_intrani_flow_regval; struct { @@ -9171,23 +4949,11 @@ mmr_t reserved_1 : 56; } sh_xnni0_1_intrani_flow_s; } sh_xnni0_1_intrani_flow_u_t; -#else -typedef union sh_xnni0_1_intrani_flow_u { - mmr_t sh_xnni0_1_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc1_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc1_withhold : 6; - } sh_xnni0_1_intrani_flow_s; -} sh_xnni0_1_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_2_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_2_intrani_flow_u { mmr_t sh_xnni0_2_intrani_flow_regval; struct { @@ -9197,23 +4963,11 @@ mmr_t reserved_1 : 56; } sh_xnni0_2_intrani_flow_s; } sh_xnni0_2_intrani_flow_u_t; -#else -typedef union sh_xnni0_2_intrani_flow_u { - mmr_t sh_xnni0_2_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc2_withhold : 6; - } sh_xnni0_2_intrani_flow_s; -} sh_xnni0_2_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_3_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_3_intrani_flow_u { mmr_t sh_xnni0_3_intrani_flow_regval; struct { @@ -9223,23 +4977,11 @@ mmr_t reserved_1 : 56; } sh_xnni0_3_intrani_flow_s; } sh_xnni0_3_intrani_flow_u_t; -#else -typedef union sh_xnni0_3_intrani_flow_u { - mmr_t sh_xnni0_3_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc3_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc3_withhold : 6; - } sh_xnni0_3_intrani_flow_s; -} sh_xnni0_3_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_VCSWITCH_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_vcswitch_flow_u { mmr_t sh_xnni0_vcswitch_flow_regval; struct { @@ -9257,31 +4999,11 @@ mmr_t reserved_4 : 29; } sh_xnni0_vcswitch_flow_s; } sh_xnni0_vcswitch_flow_u_t; -#else -typedef union sh_xnni0_vcswitch_flow_u { - mmr_t sh_xnni0_vcswitch_flow_regval; - struct { - mmr_t reserved_4 : 29; - mmr_t async_fifoes : 1; - mmr_t disable_sync_bypass_out : 1; - mmr_t disable_sync_bypass_in : 1; - mmr_t reserved_3 : 7; - mmr_t iilb_vcfifo_switch : 1; - mmr_t reserved_2 : 7; - mmr_t md_vcfifo_switch : 1; - mmr_t reserved_1 : 7; - mmr_t pi_vcfifo_switch : 1; - mmr_t reserved_0 : 7; - mmr_t ni_vcfifo_dateline_switch : 1; - } sh_xnni0_vcswitch_flow_s; -} sh_xnni0_vcswitch_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_TIMER_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_timer_reg_u { mmr_t sh_xnni0_timer_reg_regval; struct { @@ -9291,23 +5013,11 @@ mmr_t reserved_1 : 31; } sh_xnni0_timer_reg_s; } sh_xnni0_timer_reg_u_t; -#else -typedef union sh_xnni0_timer_reg_u { - mmr_t sh_xnni0_timer_reg_regval; - struct { - mmr_t reserved_1 : 31; - mmr_t linkcleanup_reg : 1; - mmr_t reserved_0 : 8; - mmr_t timeout_reg : 24; - } sh_xnni0_timer_reg_s; -} sh_xnni0_timer_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_FIFO02_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_fifo02_flow_u { mmr_t sh_xnni0_fifo02_flow_regval; struct { @@ -9325,31 +5035,11 @@ mmr_t reserved_5 : 20; } sh_xnni0_fifo02_flow_s; } sh_xnni0_fifo02_flow_u_t; -#else -typedef union sh_xnni0_fifo02_flow_u { - mmr_t sh_xnni0_fifo02_flow_regval; - struct { - mmr_t reserved_5 : 20; - mmr_t count_vc2_cap : 4; - mmr_t reserved_4 : 4; - mmr_t count_vc2_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t count_vc2_limit : 4; - mmr_t reserved_2 : 4; - mmr_t count_vc0_cap : 4; - mmr_t reserved_1 : 4; - mmr_t count_vc0_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t count_vc0_limit : 4; - } sh_xnni0_fifo02_flow_s; -} sh_xnni0_fifo02_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_FIFO13_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_fifo13_flow_u { mmr_t sh_xnni0_fifo13_flow_regval; struct { @@ -9367,31 +5057,11 @@ mmr_t reserved_5 : 20; } sh_xnni0_fifo13_flow_s; } sh_xnni0_fifo13_flow_u_t; -#else -typedef union sh_xnni0_fifo13_flow_u { - mmr_t sh_xnni0_fifo13_flow_regval; - struct { - mmr_t reserved_5 : 20; - mmr_t count_vc3_cap : 4; - mmr_t reserved_4 : 4; - mmr_t count_vc3_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t count_vc3_limit : 4; - mmr_t reserved_2 : 4; - mmr_t count_vc1_cap : 4; - mmr_t reserved_1 : 4; - mmr_t count_vc1_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t count_vc1_limit : 4; - } sh_xnni0_fifo13_flow_s; -} sh_xnni0_fifo13_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_NI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_ni_flow_u { mmr_t sh_xnni0_ni_flow_regval; struct { @@ -9413,35 +5083,11 @@ mmr_t vc3_cap : 4; } sh_xnni0_ni_flow_s; } sh_xnni0_ni_flow_u_t; -#else -typedef union sh_xnni0_ni_flow_u { - mmr_t sh_xnni0_ni_flow_regval; - struct { - mmr_t vc3_cap : 4; - mmr_t vc3_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t vc3_limit : 4; - mmr_t vc2_cap : 4; - mmr_t vc2_dyn : 4; - mmr_t reserved_2 : 4; - mmr_t vc2_limit : 4; - mmr_t vc1_cap : 4; - mmr_t vc1_dyn : 4; - mmr_t reserved_1 : 4; - mmr_t vc1_limit : 4; - mmr_t vc0_cap : 4; - mmr_t vc0_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t vc0_limit : 4; - } sh_xnni0_ni_flow_s; -} sh_xnni0_ni_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_DEAD_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_dead_flow_u { mmr_t sh_xnni0_dead_flow_regval; struct { @@ -9463,35 +5109,11 @@ mmr_t vc3_cap : 4; } sh_xnni0_dead_flow_s; } sh_xnni0_dead_flow_u_t; -#else -typedef union sh_xnni0_dead_flow_u { - mmr_t sh_xnni0_dead_flow_regval; - struct { - mmr_t vc3_cap : 4; - mmr_t vc3_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t vc3_limit : 4; - mmr_t vc2_cap : 4; - mmr_t vc2_dyn : 4; - mmr_t reserved_2 : 4; - mmr_t vc2_limit : 4; - mmr_t vc1_cap : 4; - mmr_t vc1_dyn : 4; - mmr_t reserved_1 : 4; - mmr_t vc1_limit : 4; - mmr_t vc0_cap : 4; - mmr_t vc0_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t vc0_limit : 4; - } sh_xnni0_dead_flow_s; -} sh_xnni0_dead_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI0_INJECT_AGE" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni0_inject_age_u { mmr_t sh_xnni0_inject_age_regval; struct { @@ -9500,22 +5122,11 @@ mmr_t reserved_0 : 48; } sh_xnni0_inject_age_s; } sh_xnni0_inject_age_u_t; -#else -typedef union sh_xnni0_inject_age_u { - mmr_t sh_xnni0_inject_age_regval; - struct { - mmr_t reserved_0 : 48; - mmr_t reply_inject : 8; - mmr_t request_inject : 8; - } sh_xnni0_inject_age_s; -} sh_xnni0_inject_age_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_to_pi_intra_flow_debit_u { mmr_t sh_xnni1_to_pi_intra_flow_debit_regval; struct { @@ -9536,34 +5147,11 @@ mmr_t reserved_6 : 1; } sh_xnni1_to_pi_intra_flow_debit_s; } sh_xnni1_to_pi_intra_flow_debit_u_t; -#else -typedef union sh_xnni1_to_pi_intra_flow_debit_u { - mmr_t sh_xnni1_to_pi_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xnni1_to_pi_intra_flow_debit_s; -} sh_xnni1_to_pi_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_to_md_intra_flow_debit_u { mmr_t sh_xnni1_to_md_intra_flow_debit_regval; struct { @@ -9584,34 +5172,11 @@ mmr_t reserved_6 : 1; } sh_xnni1_to_md_intra_flow_debit_s; } sh_xnni1_to_md_intra_flow_debit_u_t; -#else -typedef union sh_xnni1_to_md_intra_flow_debit_u { - mmr_t sh_xnni1_to_md_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xnni1_to_md_intra_flow_debit_s; -} sh_xnni1_to_md_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_to_iilb_intra_flow_debit_u { mmr_t sh_xnni1_to_iilb_intra_flow_debit_regval; struct { @@ -9632,34 +5197,11 @@ mmr_t reserved_6 : 1; } sh_xnni1_to_iilb_intra_flow_debit_s; } sh_xnni1_to_iilb_intra_flow_debit_u_t; -#else -typedef union sh_xnni1_to_iilb_intra_flow_debit_u { - mmr_t sh_xnni1_to_iilb_intra_flow_debit_regval; - struct { - mmr_t reserved_6 : 1; - mmr_t vc2_cap : 7; - mmr_t reserved_5 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_4 : 9; - mmr_t vc0_cap : 7; - mmr_t reserved_3 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_2 : 8; - mmr_t vc2_force_cred : 1; - mmr_t reserved_1 : 1; - mmr_t vc2_withhold : 6; - mmr_t vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t vc0_withhold : 6; - } sh_xnni1_to_iilb_intra_flow_debit_s; -} sh_xnni1_to_iilb_intra_flow_debit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_fr_pi_intra_flow_credit_u { mmr_t sh_xnni1_fr_pi_intra_flow_credit_regval; struct { @@ -9677,31 +5219,11 @@ mmr_t reserved_5 : 17; } sh_xnni1_fr_pi_intra_flow_credit_s; } sh_xnni1_fr_pi_intra_flow_credit_u_t; -#else -typedef union sh_xnni1_fr_pi_intra_flow_credit_u { - mmr_t sh_xnni1_fr_pi_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xnni1_fr_pi_intra_flow_credit_s; -} sh_xnni1_fr_pi_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_fr_md_intra_flow_credit_u { mmr_t sh_xnni1_fr_md_intra_flow_credit_regval; struct { @@ -9719,31 +5241,11 @@ mmr_t reserved_5 : 17; } sh_xnni1_fr_md_intra_flow_credit_s; } sh_xnni1_fr_md_intra_flow_credit_u_t; -#else -typedef union sh_xnni1_fr_md_intra_flow_credit_u { - mmr_t sh_xnni1_fr_md_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xnni1_fr_md_intra_flow_credit_s; -} sh_xnni1_fr_md_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_fr_iilb_intra_flow_credit_u { mmr_t sh_xnni1_fr_iilb_intra_flow_credit_regval; struct { @@ -9761,31 +5263,11 @@ mmr_t reserved_5 : 17; } sh_xnni1_fr_iilb_intra_flow_credit_s; } sh_xnni1_fr_iilb_intra_flow_credit_u_t; -#else -typedef union sh_xnni1_fr_iilb_intra_flow_credit_u { - mmr_t sh_xnni1_fr_iilb_intra_flow_credit_regval; - struct { - mmr_t reserved_5 : 17; - mmr_t vc2_cap : 7; - mmr_t reserved_4 : 1; - mmr_t vc2_dyn : 7; - mmr_t reserved_3 : 1; - mmr_t vc2_test : 7; - mmr_t reserved_2 : 1; - mmr_t vc0_cap : 7; - mmr_t reserved_1 : 1; - mmr_t vc0_dyn : 7; - mmr_t reserved_0 : 1; - mmr_t vc0_test : 7; - } sh_xnni1_fr_iilb_intra_flow_credit_s; -} sh_xnni1_fr_iilb_intra_flow_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_0_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_0_intrani_flow_u { mmr_t sh_xnni1_0_intrani_flow_regval; struct { @@ -9795,23 +5277,11 @@ mmr_t reserved_1 : 56; } sh_xnni1_0_intrani_flow_s; } sh_xnni1_0_intrani_flow_u_t; -#else -typedef union sh_xnni1_0_intrani_flow_u { - mmr_t sh_xnni1_0_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc0_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc0_withhold : 6; - } sh_xnni1_0_intrani_flow_s; -} sh_xnni1_0_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_1_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_1_intrani_flow_u { mmr_t sh_xnni1_1_intrani_flow_regval; struct { @@ -9821,23 +5291,11 @@ mmr_t reserved_1 : 56; } sh_xnni1_1_intrani_flow_s; } sh_xnni1_1_intrani_flow_u_t; -#else -typedef union sh_xnni1_1_intrani_flow_u { - mmr_t sh_xnni1_1_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc1_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc1_withhold : 6; - } sh_xnni1_1_intrani_flow_s; -} sh_xnni1_1_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_2_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_2_intrani_flow_u { mmr_t sh_xnni1_2_intrani_flow_regval; struct { @@ -9847,23 +5305,11 @@ mmr_t reserved_1 : 56; } sh_xnni1_2_intrani_flow_s; } sh_xnni1_2_intrani_flow_u_t; -#else -typedef union sh_xnni1_2_intrani_flow_u { - mmr_t sh_xnni1_2_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc2_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc2_withhold : 6; - } sh_xnni1_2_intrani_flow_s; -} sh_xnni1_2_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_3_INTRANI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_3_intrani_flow_u { mmr_t sh_xnni1_3_intrani_flow_regval; struct { @@ -9873,23 +5319,11 @@ mmr_t reserved_1 : 56; } sh_xnni1_3_intrani_flow_s; } sh_xnni1_3_intrani_flow_u_t; -#else -typedef union sh_xnni1_3_intrani_flow_u { - mmr_t sh_xnni1_3_intrani_flow_regval; - struct { - mmr_t reserved_1 : 56; - mmr_t debit_vc3_force_cred : 1; - mmr_t reserved_0 : 1; - mmr_t debit_vc3_withhold : 6; - } sh_xnni1_3_intrani_flow_s; -} sh_xnni1_3_intrani_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_VCSWITCH_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_vcswitch_flow_u { mmr_t sh_xnni1_vcswitch_flow_regval; struct { @@ -9907,31 +5341,11 @@ mmr_t reserved_4 : 29; } sh_xnni1_vcswitch_flow_s; } sh_xnni1_vcswitch_flow_u_t; -#else -typedef union sh_xnni1_vcswitch_flow_u { - mmr_t sh_xnni1_vcswitch_flow_regval; - struct { - mmr_t reserved_4 : 29; - mmr_t async_fifoes : 1; - mmr_t disable_sync_bypass_out : 1; - mmr_t disable_sync_bypass_in : 1; - mmr_t reserved_3 : 7; - mmr_t iilb_vcfifo_switch : 1; - mmr_t reserved_2 : 7; - mmr_t md_vcfifo_switch : 1; - mmr_t reserved_1 : 7; - mmr_t pi_vcfifo_switch : 1; - mmr_t reserved_0 : 7; - mmr_t ni_vcfifo_dateline_switch : 1; - } sh_xnni1_vcswitch_flow_s; -} sh_xnni1_vcswitch_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_TIMER_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_timer_reg_u { mmr_t sh_xnni1_timer_reg_regval; struct { @@ -9941,23 +5355,11 @@ mmr_t reserved_1 : 31; } sh_xnni1_timer_reg_s; } sh_xnni1_timer_reg_u_t; -#else -typedef union sh_xnni1_timer_reg_u { - mmr_t sh_xnni1_timer_reg_regval; - struct { - mmr_t reserved_1 : 31; - mmr_t linkcleanup_reg : 1; - mmr_t reserved_0 : 8; - mmr_t timeout_reg : 24; - } sh_xnni1_timer_reg_s; -} sh_xnni1_timer_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_FIFO02_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_fifo02_flow_u { mmr_t sh_xnni1_fifo02_flow_regval; struct { @@ -9975,31 +5377,11 @@ mmr_t reserved_5 : 20; } sh_xnni1_fifo02_flow_s; } sh_xnni1_fifo02_flow_u_t; -#else -typedef union sh_xnni1_fifo02_flow_u { - mmr_t sh_xnni1_fifo02_flow_regval; - struct { - mmr_t reserved_5 : 20; - mmr_t count_vc2_cap : 4; - mmr_t reserved_4 : 4; - mmr_t count_vc2_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t count_vc2_limit : 4; - mmr_t reserved_2 : 4; - mmr_t count_vc0_cap : 4; - mmr_t reserved_1 : 4; - mmr_t count_vc0_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t count_vc0_limit : 4; - } sh_xnni1_fifo02_flow_s; -} sh_xnni1_fifo02_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_FIFO13_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_fifo13_flow_u { mmr_t sh_xnni1_fifo13_flow_regval; struct { @@ -10017,31 +5399,11 @@ mmr_t reserved_5 : 20; } sh_xnni1_fifo13_flow_s; } sh_xnni1_fifo13_flow_u_t; -#else -typedef union sh_xnni1_fifo13_flow_u { - mmr_t sh_xnni1_fifo13_flow_regval; - struct { - mmr_t reserved_5 : 20; - mmr_t count_vc3_cap : 4; - mmr_t reserved_4 : 4; - mmr_t count_vc3_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t count_vc3_limit : 4; - mmr_t reserved_2 : 4; - mmr_t count_vc1_cap : 4; - mmr_t reserved_1 : 4; - mmr_t count_vc1_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t count_vc1_limit : 4; - } sh_xnni1_fifo13_flow_s; -} sh_xnni1_fifo13_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_NI_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_ni_flow_u { mmr_t sh_xnni1_ni_flow_regval; struct { @@ -10063,35 +5425,11 @@ mmr_t vc3_cap : 4; } sh_xnni1_ni_flow_s; } sh_xnni1_ni_flow_u_t; -#else -typedef union sh_xnni1_ni_flow_u { - mmr_t sh_xnni1_ni_flow_regval; - struct { - mmr_t vc3_cap : 4; - mmr_t vc3_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t vc3_limit : 4; - mmr_t vc2_cap : 4; - mmr_t vc2_dyn : 4; - mmr_t reserved_2 : 4; - mmr_t vc2_limit : 4; - mmr_t vc1_cap : 4; - mmr_t vc1_dyn : 4; - mmr_t reserved_1 : 4; - mmr_t vc1_limit : 4; - mmr_t vc0_cap : 4; - mmr_t vc0_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t vc0_limit : 4; - } sh_xnni1_ni_flow_s; -} sh_xnni1_ni_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_DEAD_FLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_dead_flow_u { mmr_t sh_xnni1_dead_flow_regval; struct { @@ -10113,35 +5451,11 @@ mmr_t vc3_cap : 4; } sh_xnni1_dead_flow_s; } sh_xnni1_dead_flow_u_t; -#else -typedef union sh_xnni1_dead_flow_u { - mmr_t sh_xnni1_dead_flow_regval; - struct { - mmr_t vc3_cap : 4; - mmr_t vc3_dyn : 4; - mmr_t reserved_3 : 4; - mmr_t vc3_limit : 4; - mmr_t vc2_cap : 4; - mmr_t vc2_dyn : 4; - mmr_t reserved_2 : 4; - mmr_t vc2_limit : 4; - mmr_t vc1_cap : 4; - mmr_t vc1_dyn : 4; - mmr_t reserved_1 : 4; - mmr_t vc1_limit : 4; - mmr_t vc0_cap : 4; - mmr_t vc0_dyn : 4; - mmr_t reserved_0 : 4; - mmr_t vc0_limit : 4; - } sh_xnni1_dead_flow_s; -} sh_xnni1_dead_flow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNNI1_INJECT_AGE" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnni1_inject_age_u { mmr_t sh_xnni1_inject_age_regval; struct { @@ -10150,23 +5464,12 @@ mmr_t reserved_0 : 48; } sh_xnni1_inject_age_s; } sh_xnni1_inject_age_u_t; -#else -typedef union sh_xnni1_inject_age_u { - mmr_t sh_xnni1_inject_age_regval; - struct { - mmr_t reserved_0 : 48; - mmr_t reply_inject : 8; - mmr_t request_inject : 8; - } sh_xnni1_inject_age_s; -} sh_xnni1_inject_age_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_DEBUG_SEL" */ /* XN Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_debug_sel_u { mmr_t sh_xn_debug_sel_regval; struct { @@ -10204,52 +5507,12 @@ mmr_t trigger_enable : 1; } sh_xn_debug_sel_s; } sh_xn_debug_sel_u_t; -#else -typedef union sh_xn_debug_sel_u { - mmr_t sh_xn_debug_sel_regval; - struct { - mmr_t trigger_enable : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_rlm_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_rlm_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_rlm_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_rlm_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_rlm_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_rlm_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_rlm_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_rlm_sel : 3; - } sh_xn_debug_sel_s; -} sh_xn_debug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_DEBUG_TRIG_SEL" */ /* XN Debug trigger Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_debug_trig_sel_u { mmr_t sh_xn_debug_trig_sel_regval; struct { @@ -10287,52 +5550,12 @@ mmr_t reserved_15 : 1; } sh_xn_debug_trig_sel_s; } sh_xn_debug_trig_sel_u_t; -#else -typedef union sh_xn_debug_trig_sel_u { - mmr_t sh_xn_debug_trig_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t trigger7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t trigger7_rlm_sel : 3; - mmr_t reserved_13 : 1; - mmr_t trigger6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t trigger6_rlm_sel : 3; - mmr_t reserved_11 : 1; - mmr_t trigger5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t trigger5_rlm_sel : 3; - mmr_t reserved_9 : 1; - mmr_t trigger4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t trigger4_rlm_sel : 3; - mmr_t reserved_7 : 1; - mmr_t trigger3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t trigger3_rlm_sel : 3; - mmr_t reserved_5 : 1; - mmr_t trigger2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t trigger2_rlm_sel : 3; - mmr_t reserved_3 : 1; - mmr_t trigger1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t trigger1_rlm_sel : 3; - mmr_t reserved_1 : 1; - mmr_t trigger0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t trigger0_rlm_sel : 3; - } sh_xn_debug_trig_sel_s; -} sh_xn_debug_trig_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_TRIGGER_COMPARE" */ /* XN Debug Compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_trigger_compare_u { mmr_t sh_xn_trigger_compare_regval; struct { @@ -10340,22 +5563,12 @@ mmr_t reserved_0 : 32; } sh_xn_trigger_compare_s; } sh_xn_trigger_compare_u_t; -#else -typedef union sh_xn_trigger_compare_u { - mmr_t sh_xn_trigger_compare_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t mask : 32; - } sh_xn_trigger_compare_s; -} sh_xn_trigger_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_TRIGGER_DATA" */ /* XN Debug Compare Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_trigger_data_u { mmr_t sh_xn_trigger_data_regval; struct { @@ -10363,22 +5576,12 @@ mmr_t reserved_0 : 32; } sh_xn_trigger_data_s; } sh_xn_trigger_data_u_t; -#else -typedef union sh_xn_trigger_data_u { - mmr_t sh_xn_trigger_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t compare_pattern : 32; - } sh_xn_trigger_data_s; -} sh_xn_trigger_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_DEBUG_SEL" */ /* XN IILB Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_iilb_debug_sel_u { mmr_t sh_xn_iilb_debug_sel_regval; struct { @@ -10416,52 +5619,12 @@ mmr_t reserved_15 : 1; } sh_xn_iilb_debug_sel_s; } sh_xn_iilb_debug_sel_u_t; -#else -typedef union sh_xn_iilb_debug_sel_u { - mmr_t sh_xn_iilb_debug_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_input_sel : 3; - } sh_xn_iilb_debug_sel_s; -} sh_xn_iilb_debug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_DEBUG_SEL" */ /* XN PI Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_debug_sel_u { mmr_t sh_xn_pi_debug_sel_regval; struct { @@ -10499,52 +5662,12 @@ mmr_t reserved_15 : 1; } sh_xn_pi_debug_sel_s; } sh_xn_pi_debug_sel_u_t; -#else -typedef union sh_xn_pi_debug_sel_u { - mmr_t sh_xn_pi_debug_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_input_sel : 3; - } sh_xn_pi_debug_sel_s; -} sh_xn_pi_debug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_DEBUG_SEL" */ /* XN MD Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_debug_sel_u { mmr_t sh_xn_md_debug_sel_regval; struct { @@ -10582,52 +5705,12 @@ mmr_t reserved_15 : 1; } sh_xn_md_debug_sel_s; } sh_xn_md_debug_sel_u_t; -#else -typedef union sh_xn_md_debug_sel_u { - mmr_t sh_xn_md_debug_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_input_sel : 3; - } sh_xn_md_debug_sel_s; -} sh_xn_md_debug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_DEBUG_SEL" */ /* XN NI0 Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni0_debug_sel_u { mmr_t sh_xn_ni0_debug_sel_regval; struct { @@ -10665,52 +5748,12 @@ mmr_t reserved_15 : 1; } sh_xn_ni0_debug_sel_s; } sh_xn_ni0_debug_sel_u_t; -#else -typedef union sh_xn_ni0_debug_sel_u { - mmr_t sh_xn_ni0_debug_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_input_sel : 3; - } sh_xn_ni0_debug_sel_s; -} sh_xn_ni0_debug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_DEBUG_SEL" */ /* XN NI1 Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_debug_sel_u { mmr_t sh_xn_ni1_debug_sel_regval; struct { @@ -10748,829 +5791,456 @@ mmr_t reserved_15 : 1; } sh_xn_ni1_debug_sel_s; } sh_xn_ni1_debug_sel_u_t; -#else -typedef union sh_xn_ni1_debug_sel_u { - mmr_t sh_xn_ni1_debug_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_input_sel : 3; - } sh_xn_ni1_debug_sel_s; -} sh_xn_ni1_debug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_LB_CMP_EXP_DATA0" */ /* IILB compare LB input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_iilb_lb_cmp_exp_data0_u { mmr_t sh_xn_iilb_lb_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_iilb_lb_cmp_exp_data0_s; } sh_xn_iilb_lb_cmp_exp_data0_u_t; -#else -typedef union sh_xn_iilb_lb_cmp_exp_data0_u { - mmr_t sh_xn_iilb_lb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_lb_cmp_exp_data0_s; -} sh_xn_iilb_lb_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_LB_CMP_EXP_DATA1" */ /* IILB compare LB input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_iilb_lb_cmp_exp_data1_u { mmr_t sh_xn_iilb_lb_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_iilb_lb_cmp_exp_data1_s; } sh_xn_iilb_lb_cmp_exp_data1_u_t; -#else -typedef union sh_xn_iilb_lb_cmp_exp_data1_u { - mmr_t sh_xn_iilb_lb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_lb_cmp_exp_data1_s; -} sh_xn_iilb_lb_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_LB_CMP_ENABLE0" */ /* IILB compare LB input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_lb_cmp_enable0_u { - mmr_t sh_xn_iilb_lb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_lb_cmp_enable0_s; -} sh_xn_iilb_lb_cmp_enable0_u_t; -#else typedef union sh_xn_iilb_lb_cmp_enable0_u { mmr_t sh_xn_iilb_lb_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_iilb_lb_cmp_enable0_s; } sh_xn_iilb_lb_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_LB_CMP_ENABLE1" */ /* IILB compare LB input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_lb_cmp_enable1_u { - mmr_t sh_xn_iilb_lb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_lb_cmp_enable1_s; -} sh_xn_iilb_lb_cmp_enable1_u_t; -#else typedef union sh_xn_iilb_lb_cmp_enable1_u { mmr_t sh_xn_iilb_lb_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_iilb_lb_cmp_enable1_s; } sh_xn_iilb_lb_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_II_CMP_EXP_DATA0" */ /* IILB compare II input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ii_cmp_exp_data0_u { - mmr_t sh_xn_iilb_ii_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ii_cmp_exp_data0_s; -} sh_xn_iilb_ii_cmp_exp_data0_u_t; -#else typedef union sh_xn_iilb_ii_cmp_exp_data0_u { mmr_t sh_xn_iilb_ii_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_iilb_ii_cmp_exp_data0_s; } sh_xn_iilb_ii_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_II_CMP_EXP_DATA1" */ /* IILB compare II input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ii_cmp_exp_data1_u { - mmr_t sh_xn_iilb_ii_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ii_cmp_exp_data1_s; -} sh_xn_iilb_ii_cmp_exp_data1_u_t; -#else typedef union sh_xn_iilb_ii_cmp_exp_data1_u { mmr_t sh_xn_iilb_ii_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_iilb_ii_cmp_exp_data1_s; } sh_xn_iilb_ii_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_II_CMP_ENABLE0" */ /* IILB compare II input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ii_cmp_enable0_u { - mmr_t sh_xn_iilb_ii_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ii_cmp_enable0_s; -} sh_xn_iilb_ii_cmp_enable0_u_t; -#else typedef union sh_xn_iilb_ii_cmp_enable0_u { mmr_t sh_xn_iilb_ii_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_iilb_ii_cmp_enable0_s; } sh_xn_iilb_ii_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_II_CMP_ENABLE1" */ /* IILB compare II input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ii_cmp_enable1_u { - mmr_t sh_xn_iilb_ii_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ii_cmp_enable1_s; -} sh_xn_iilb_ii_cmp_enable1_u_t; -#else typedef union sh_xn_iilb_ii_cmp_enable1_u { mmr_t sh_xn_iilb_ii_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_iilb_ii_cmp_enable1_s; } sh_xn_iilb_ii_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_MD_CMP_EXP_DATA0" */ /* IILB compare MD input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_md_cmp_exp_data0_u { - mmr_t sh_xn_iilb_md_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_md_cmp_exp_data0_s; -} sh_xn_iilb_md_cmp_exp_data0_u_t; -#else typedef union sh_xn_iilb_md_cmp_exp_data0_u { mmr_t sh_xn_iilb_md_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_iilb_md_cmp_exp_data0_s; } sh_xn_iilb_md_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_MD_CMP_EXP_DATA1" */ /* IILB compare MD input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_md_cmp_exp_data1_u { - mmr_t sh_xn_iilb_md_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_md_cmp_exp_data1_s; -} sh_xn_iilb_md_cmp_exp_data1_u_t; -#else typedef union sh_xn_iilb_md_cmp_exp_data1_u { mmr_t sh_xn_iilb_md_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_iilb_md_cmp_exp_data1_s; } sh_xn_iilb_md_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_MD_CMP_ENABLE0" */ /* IILB compare MD input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_md_cmp_enable0_u { - mmr_t sh_xn_iilb_md_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_md_cmp_enable0_s; -} sh_xn_iilb_md_cmp_enable0_u_t; -#else typedef union sh_xn_iilb_md_cmp_enable0_u { mmr_t sh_xn_iilb_md_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_iilb_md_cmp_enable0_s; } sh_xn_iilb_md_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_MD_CMP_ENABLE1" */ /* IILB compare MD input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_md_cmp_enable1_u { - mmr_t sh_xn_iilb_md_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_md_cmp_enable1_s; -} sh_xn_iilb_md_cmp_enable1_u_t; -#else typedef union sh_xn_iilb_md_cmp_enable1_u { mmr_t sh_xn_iilb_md_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_iilb_md_cmp_enable1_s; } sh_xn_iilb_md_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_PI_CMP_EXP_DATA0" */ /* IILB compare PI input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_pi_cmp_exp_data0_u { - mmr_t sh_xn_iilb_pi_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_pi_cmp_exp_data0_s; -} sh_xn_iilb_pi_cmp_exp_data0_u_t; -#else typedef union sh_xn_iilb_pi_cmp_exp_data0_u { mmr_t sh_xn_iilb_pi_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_iilb_pi_cmp_exp_data0_s; } sh_xn_iilb_pi_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_PI_CMP_EXP_DATA1" */ /* IILB compare PI input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_pi_cmp_exp_data1_u { - mmr_t sh_xn_iilb_pi_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_pi_cmp_exp_data1_s; -} sh_xn_iilb_pi_cmp_exp_data1_u_t; -#else typedef union sh_xn_iilb_pi_cmp_exp_data1_u { mmr_t sh_xn_iilb_pi_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_iilb_pi_cmp_exp_data1_s; } sh_xn_iilb_pi_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_PI_CMP_ENABLE0" */ /* IILB compare PI input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_iilb_pi_cmp_enable0_u { mmr_t sh_xn_iilb_pi_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_iilb_pi_cmp_enable0_s; } sh_xn_iilb_pi_cmp_enable0_u_t; -#else -typedef union sh_xn_iilb_pi_cmp_enable0_u { - mmr_t sh_xn_iilb_pi_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_pi_cmp_enable0_s; -} sh_xn_iilb_pi_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_PI_CMP_ENABLE1" */ /* IILB compare PI input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_pi_cmp_enable1_u { - mmr_t sh_xn_iilb_pi_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_pi_cmp_enable1_s; -} sh_xn_iilb_pi_cmp_enable1_u_t; -#else typedef union sh_xn_iilb_pi_cmp_enable1_u { mmr_t sh_xn_iilb_pi_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_iilb_pi_cmp_enable1_s; } sh_xn_iilb_pi_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI0_CMP_EXP_DATA0" */ /* IILB compare NI0 input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ni0_cmp_exp_data0_u { - mmr_t sh_xn_iilb_ni0_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ni0_cmp_exp_data0_s; -} sh_xn_iilb_ni0_cmp_exp_data0_u_t; -#else typedef union sh_xn_iilb_ni0_cmp_exp_data0_u { mmr_t sh_xn_iilb_ni0_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_iilb_ni0_cmp_exp_data0_s; } sh_xn_iilb_ni0_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI0_CMP_EXP_DATA1" */ /* IILB compare NI0 input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ni0_cmp_exp_data1_u { - mmr_t sh_xn_iilb_ni0_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ni0_cmp_exp_data1_s; -} sh_xn_iilb_ni0_cmp_exp_data1_u_t; -#else typedef union sh_xn_iilb_ni0_cmp_exp_data1_u { mmr_t sh_xn_iilb_ni0_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_iilb_ni0_cmp_exp_data1_s; } sh_xn_iilb_ni0_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI0_CMP_ENABLE0" */ /* IILB compare NI0 input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ni0_cmp_enable0_u { - mmr_t sh_xn_iilb_ni0_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ni0_cmp_enable0_s; -} sh_xn_iilb_ni0_cmp_enable0_u_t; -#else typedef union sh_xn_iilb_ni0_cmp_enable0_u { mmr_t sh_xn_iilb_ni0_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_iilb_ni0_cmp_enable0_s; } sh_xn_iilb_ni0_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI0_CMP_ENABLE1" */ /* IILB compare NI0 input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ni0_cmp_enable1_u { - mmr_t sh_xn_iilb_ni0_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ni0_cmp_enable1_s; -} sh_xn_iilb_ni0_cmp_enable1_u_t; -#else typedef union sh_xn_iilb_ni0_cmp_enable1_u { mmr_t sh_xn_iilb_ni0_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_iilb_ni0_cmp_enable1_s; } sh_xn_iilb_ni0_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI1_CMP_EXP_DATA0" */ /* IILB compare NI1 input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ni1_cmp_exp_data0_u { - mmr_t sh_xn_iilb_ni1_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ni1_cmp_exp_data0_s; -} sh_xn_iilb_ni1_cmp_exp_data0_u_t; -#else typedef union sh_xn_iilb_ni1_cmp_exp_data0_u { mmr_t sh_xn_iilb_ni1_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_iilb_ni1_cmp_exp_data0_s; } sh_xn_iilb_ni1_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI1_CMP_EXP_DATA1" */ /* IILB compare NI1 input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_iilb_ni1_cmp_exp_data1_u { mmr_t sh_xn_iilb_ni1_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_iilb_ni1_cmp_exp_data1_s; } sh_xn_iilb_ni1_cmp_exp_data1_u_t; -#else -typedef union sh_xn_iilb_ni1_cmp_exp_data1_u { - mmr_t sh_xn_iilb_ni1_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_iilb_ni1_cmp_exp_data1_s; -} sh_xn_iilb_ni1_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI1_CMP_ENABLE0" */ /* IILB compare NI1 input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ni1_cmp_enable0_u { - mmr_t sh_xn_iilb_ni1_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ni1_cmp_enable0_s; -} sh_xn_iilb_ni1_cmp_enable0_u_t; -#else typedef union sh_xn_iilb_ni1_cmp_enable0_u { mmr_t sh_xn_iilb_ni1_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_iilb_ni1_cmp_enable0_s; } sh_xn_iilb_ni1_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_IILB_NI1_CMP_ENABLE1" */ /* IILB compare NI1 input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_iilb_ni1_cmp_enable1_u { - mmr_t sh_xn_iilb_ni1_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_iilb_ni1_cmp_enable1_s; -} sh_xn_iilb_ni1_cmp_enable1_u_t; -#else typedef union sh_xn_iilb_ni1_cmp_enable1_u { mmr_t sh_xn_iilb_ni1_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_iilb_ni1_cmp_enable1_s; } sh_xn_iilb_ni1_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_IILB_CMP_EXP_DATA0" */ /* MD compare IILB input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_iilb_cmp_exp_data0_u { mmr_t sh_xn_md_iilb_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_md_iilb_cmp_exp_data0_s; } sh_xn_md_iilb_cmp_exp_data0_u_t; -#else -typedef union sh_xn_md_iilb_cmp_exp_data0_u { - mmr_t sh_xn_md_iilb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_md_iilb_cmp_exp_data0_s; -} sh_xn_md_iilb_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_IILB_CMP_EXP_DATA1" */ /* MD compare IILB input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_iilb_cmp_exp_data1_u { - mmr_t sh_xn_md_iilb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_md_iilb_cmp_exp_data1_s; -} sh_xn_md_iilb_cmp_exp_data1_u_t; -#else typedef union sh_xn_md_iilb_cmp_exp_data1_u { mmr_t sh_xn_md_iilb_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_md_iilb_cmp_exp_data1_s; } sh_xn_md_iilb_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_IILB_CMP_ENABLE0" */ /* MD compare IILB input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_iilb_cmp_enable0_u { mmr_t sh_xn_md_iilb_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_md_iilb_cmp_enable0_s; } sh_xn_md_iilb_cmp_enable0_u_t; -#else -typedef union sh_xn_md_iilb_cmp_enable0_u { - mmr_t sh_xn_md_iilb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_iilb_cmp_enable0_s; -} sh_xn_md_iilb_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_IILB_CMP_ENABLE1" */ /* MD compare IILB input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_iilb_cmp_enable1_u { - mmr_t sh_xn_md_iilb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_iilb_cmp_enable1_s; -} sh_xn_md_iilb_cmp_enable1_u_t; -#else typedef union sh_xn_md_iilb_cmp_enable1_u { mmr_t sh_xn_md_iilb_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_md_iilb_cmp_enable1_s; } sh_xn_md_iilb_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI0_CMP_EXP_DATA0" */ /* MD compare NI0 input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_ni0_cmp_exp_data0_u { mmr_t sh_xn_md_ni0_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_md_ni0_cmp_exp_data0_s; } sh_xn_md_ni0_cmp_exp_data0_u_t; -#else -typedef union sh_xn_md_ni0_cmp_exp_data0_u { - mmr_t sh_xn_md_ni0_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_md_ni0_cmp_exp_data0_s; -} sh_xn_md_ni0_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI0_CMP_EXP_DATA1" */ /* MD compare NI0 input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_ni0_cmp_exp_data1_u { - mmr_t sh_xn_md_ni0_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_md_ni0_cmp_exp_data1_s; -} sh_xn_md_ni0_cmp_exp_data1_u_t; -#else typedef union sh_xn_md_ni0_cmp_exp_data1_u { mmr_t sh_xn_md_ni0_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_md_ni0_cmp_exp_data1_s; } sh_xn_md_ni0_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI0_CMP_ENABLE0" */ /* MD compare NI0 input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_ni0_cmp_enable0_u { - mmr_t sh_xn_md_ni0_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_ni0_cmp_enable0_s; -} sh_xn_md_ni0_cmp_enable0_u_t; -#else typedef union sh_xn_md_ni0_cmp_enable0_u { mmr_t sh_xn_md_ni0_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_md_ni0_cmp_enable0_s; } sh_xn_md_ni0_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI0_CMP_ENABLE1" */ /* MD compare NI0 input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_ni0_cmp_enable1_u { - mmr_t sh_xn_md_ni0_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_ni0_cmp_enable1_s; -} sh_xn_md_ni0_cmp_enable1_u_t; -#else typedef union sh_xn_md_ni0_cmp_enable1_u { mmr_t sh_xn_md_ni0_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_md_ni0_cmp_enable1_s; } sh_xn_md_ni0_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI1_CMP_EXP_DATA0" */ /* MD compare NI1 input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_ni1_cmp_exp_data0_u { - mmr_t sh_xn_md_ni1_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_md_ni1_cmp_exp_data0_s; -} sh_xn_md_ni1_cmp_exp_data0_u_t; -#else typedef union sh_xn_md_ni1_cmp_exp_data0_u { mmr_t sh_xn_md_ni1_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_md_ni1_cmp_exp_data0_s; } sh_xn_md_ni1_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI1_CMP_EXP_DATA1" */ /* MD compare NI1 input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_ni1_cmp_exp_data1_u { mmr_t sh_xn_md_ni1_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_md_ni1_cmp_exp_data1_s; } sh_xn_md_ni1_cmp_exp_data1_u_t; -#else -typedef union sh_xn_md_ni1_cmp_exp_data1_u { - mmr_t sh_xn_md_ni1_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_md_ni1_cmp_exp_data1_s; -} sh_xn_md_ni1_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI1_CMP_ENABLE0" */ /* MD compare NI1 input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_ni1_cmp_enable0_u { - mmr_t sh_xn_md_ni1_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_ni1_cmp_enable0_s; -} sh_xn_md_ni1_cmp_enable0_u_t; -#else typedef union sh_xn_md_ni1_cmp_enable0_u { mmr_t sh_xn_md_ni1_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_md_ni1_cmp_enable0_s; } sh_xn_md_ni1_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_NI1_CMP_ENABLE1" */ /* MD compare NI1 input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_ni1_cmp_enable1_u { - mmr_t sh_xn_md_ni1_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_ni1_cmp_enable1_s; -} sh_xn_md_ni1_cmp_enable1_u_t; -#else typedef union sh_xn_md_ni1_cmp_enable1_u { mmr_t sh_xn_md_ni1_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_md_ni1_cmp_enable1_s; } sh_xn_md_ni1_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_EXP_HDR0" */ /* MD compare SIC input expected header0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_sic_cmp_exp_hdr0_u { - mmr_t sh_xn_md_sic_cmp_exp_hdr0_regval; - struct { - mmr_t data : 64; - } sh_xn_md_sic_cmp_exp_hdr0_s; -} sh_xn_md_sic_cmp_exp_hdr0_u_t; -#else typedef union sh_xn_md_sic_cmp_exp_hdr0_u { mmr_t sh_xn_md_sic_cmp_exp_hdr0_regval; struct { mmr_t data : 64; } sh_xn_md_sic_cmp_exp_hdr0_s; } sh_xn_md_sic_cmp_exp_hdr0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_EXP_HDR1" */ /* MD compare SIC input expected header1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_sic_cmp_exp_hdr1_u { mmr_t sh_xn_md_sic_cmp_exp_hdr1_regval; struct { @@ -11578,43 +6248,24 @@ mmr_t reserved_0 : 22; } sh_xn_md_sic_cmp_exp_hdr1_s; } sh_xn_md_sic_cmp_exp_hdr1_u_t; -#else -typedef union sh_xn_md_sic_cmp_exp_hdr1_u { - mmr_t sh_xn_md_sic_cmp_exp_hdr1_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t data : 42; - } sh_xn_md_sic_cmp_exp_hdr1_s; -} sh_xn_md_sic_cmp_exp_hdr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE0" */ /* MD compare SIC header enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_sic_cmp_hdr_enable0_u { - mmr_t sh_xn_md_sic_cmp_hdr_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_md_sic_cmp_hdr_enable0_s; -} sh_xn_md_sic_cmp_hdr_enable0_u_t; -#else typedef union sh_xn_md_sic_cmp_hdr_enable0_u { mmr_t sh_xn_md_sic_cmp_hdr_enable0_regval; struct { mmr_t enable : 64; } sh_xn_md_sic_cmp_hdr_enable0_s; } sh_xn_md_sic_cmp_hdr_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE1" */ /* MD compare SIC header enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_sic_cmp_hdr_enable1_u { mmr_t sh_xn_md_sic_cmp_hdr_enable1_regval; struct { @@ -11622,463 +6273,264 @@ mmr_t reserved_0 : 22; } sh_xn_md_sic_cmp_hdr_enable1_s; } sh_xn_md_sic_cmp_hdr_enable1_u_t; -#else -typedef union sh_xn_md_sic_cmp_hdr_enable1_u { - mmr_t sh_xn_md_sic_cmp_hdr_enable1_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t enable : 42; - } sh_xn_md_sic_cmp_hdr_enable1_s; -} sh_xn_md_sic_cmp_hdr_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA0" */ /* MD compare SIC data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_sic_cmp_data0_u { - mmr_t sh_xn_md_sic_cmp_data0_regval; - struct { - mmr_t data0 : 64; - } sh_xn_md_sic_cmp_data0_s; -} sh_xn_md_sic_cmp_data0_u_t; -#else typedef union sh_xn_md_sic_cmp_data0_u { mmr_t sh_xn_md_sic_cmp_data0_regval; struct { mmr_t data0 : 64; } sh_xn_md_sic_cmp_data0_s; } sh_xn_md_sic_cmp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA1" */ /* MD compare SIC data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_sic_cmp_data1_u { mmr_t sh_xn_md_sic_cmp_data1_regval; struct { mmr_t data1 : 64; } sh_xn_md_sic_cmp_data1_s; } sh_xn_md_sic_cmp_data1_u_t; -#else -typedef union sh_xn_md_sic_cmp_data1_u { - mmr_t sh_xn_md_sic_cmp_data1_regval; - struct { - mmr_t data1 : 64; - } sh_xn_md_sic_cmp_data1_s; -} sh_xn_md_sic_cmp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA2" */ /* MD compare SIC data2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_sic_cmp_data2_u { - mmr_t sh_xn_md_sic_cmp_data2_regval; - struct { - mmr_t data2 : 64; - } sh_xn_md_sic_cmp_data2_s; -} sh_xn_md_sic_cmp_data2_u_t; -#else typedef union sh_xn_md_sic_cmp_data2_u { mmr_t sh_xn_md_sic_cmp_data2_regval; struct { mmr_t data2 : 64; } sh_xn_md_sic_cmp_data2_s; } sh_xn_md_sic_cmp_data2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA3" */ /* MD compare SIC data3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_sic_cmp_data3_u { - mmr_t sh_xn_md_sic_cmp_data3_regval; - struct { - mmr_t data3 : 64; - } sh_xn_md_sic_cmp_data3_s; -} sh_xn_md_sic_cmp_data3_u_t; -#else typedef union sh_xn_md_sic_cmp_data3_u { mmr_t sh_xn_md_sic_cmp_data3_regval; struct { mmr_t data3 : 64; } sh_xn_md_sic_cmp_data3_s; } sh_xn_md_sic_cmp_data3_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE0" */ /* MD enable compare SIC data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_sic_cmp_data_enable0_u { - mmr_t sh_xn_md_sic_cmp_data_enable0_regval; - struct { - mmr_t data_enable0 : 64; - } sh_xn_md_sic_cmp_data_enable0_s; -} sh_xn_md_sic_cmp_data_enable0_u_t; -#else typedef union sh_xn_md_sic_cmp_data_enable0_u { mmr_t sh_xn_md_sic_cmp_data_enable0_regval; struct { mmr_t data_enable0 : 64; } sh_xn_md_sic_cmp_data_enable0_s; } sh_xn_md_sic_cmp_data_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE1" */ /* MD enable compare SIC data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_md_sic_cmp_data_enable1_u { - mmr_t sh_xn_md_sic_cmp_data_enable1_regval; - struct { - mmr_t data_enable1 : 64; - } sh_xn_md_sic_cmp_data_enable1_s; -} sh_xn_md_sic_cmp_data_enable1_u_t; -#else typedef union sh_xn_md_sic_cmp_data_enable1_u { mmr_t sh_xn_md_sic_cmp_data_enable1_regval; struct { mmr_t data_enable1 : 64; } sh_xn_md_sic_cmp_data_enable1_s; } sh_xn_md_sic_cmp_data_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE2" */ /* MD enable compare SIC data2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_sic_cmp_data_enable2_u { mmr_t sh_xn_md_sic_cmp_data_enable2_regval; struct { mmr_t data_enable2 : 64; } sh_xn_md_sic_cmp_data_enable2_s; } sh_xn_md_sic_cmp_data_enable2_u_t; -#else -typedef union sh_xn_md_sic_cmp_data_enable2_u { - mmr_t sh_xn_md_sic_cmp_data_enable2_regval; - struct { - mmr_t data_enable2 : 64; - } sh_xn_md_sic_cmp_data_enable2_s; -} sh_xn_md_sic_cmp_data_enable2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE3" */ /* MD enable compare SIC data3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_sic_cmp_data_enable3_u { mmr_t sh_xn_md_sic_cmp_data_enable3_regval; struct { mmr_t data_enable3 : 64; } sh_xn_md_sic_cmp_data_enable3_s; } sh_xn_md_sic_cmp_data_enable3_u_t; -#else -typedef union sh_xn_md_sic_cmp_data_enable3_u { - mmr_t sh_xn_md_sic_cmp_data_enable3_regval; - struct { - mmr_t data_enable3 : 64; - } sh_xn_md_sic_cmp_data_enable3_s; -} sh_xn_md_sic_cmp_data_enable3_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_IILB_CMP_EXP_DATA0" */ /* PI compare IILB input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_iilb_cmp_exp_data0_u { - mmr_t sh_xn_pi_iilb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_iilb_cmp_exp_data0_s; -} sh_xn_pi_iilb_cmp_exp_data0_u_t; -#else typedef union sh_xn_pi_iilb_cmp_exp_data0_u { mmr_t sh_xn_pi_iilb_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_pi_iilb_cmp_exp_data0_s; } sh_xn_pi_iilb_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_IILB_CMP_EXP_DATA1" */ /* PI compare IILB input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_iilb_cmp_exp_data1_u { - mmr_t sh_xn_pi_iilb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_iilb_cmp_exp_data1_s; -} sh_xn_pi_iilb_cmp_exp_data1_u_t; -#else typedef union sh_xn_pi_iilb_cmp_exp_data1_u { mmr_t sh_xn_pi_iilb_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_pi_iilb_cmp_exp_data1_s; } sh_xn_pi_iilb_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_IILB_CMP_ENABLE0" */ /* PI compare IILB input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_iilb_cmp_enable0_u { - mmr_t sh_xn_pi_iilb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_iilb_cmp_enable0_s; -} sh_xn_pi_iilb_cmp_enable0_u_t; -#else typedef union sh_xn_pi_iilb_cmp_enable0_u { mmr_t sh_xn_pi_iilb_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_pi_iilb_cmp_enable0_s; } sh_xn_pi_iilb_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_IILB_CMP_ENABLE1" */ /* PI compare IILB input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_iilb_cmp_enable1_u { mmr_t sh_xn_pi_iilb_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_pi_iilb_cmp_enable1_s; } sh_xn_pi_iilb_cmp_enable1_u_t; -#else -typedef union sh_xn_pi_iilb_cmp_enable1_u { - mmr_t sh_xn_pi_iilb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_iilb_cmp_enable1_s; -} sh_xn_pi_iilb_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI0_CMP_EXP_DATA0" */ /* PI compare NI0 input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_ni0_cmp_exp_data0_u { mmr_t sh_xn_pi_ni0_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_pi_ni0_cmp_exp_data0_s; } sh_xn_pi_ni0_cmp_exp_data0_u_t; -#else -typedef union sh_xn_pi_ni0_cmp_exp_data0_u { - mmr_t sh_xn_pi_ni0_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_ni0_cmp_exp_data0_s; -} sh_xn_pi_ni0_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI0_CMP_EXP_DATA1" */ /* PI compare NI0 input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_ni0_cmp_exp_data1_u { mmr_t sh_xn_pi_ni0_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_pi_ni0_cmp_exp_data1_s; } sh_xn_pi_ni0_cmp_exp_data1_u_t; -#else -typedef union sh_xn_pi_ni0_cmp_exp_data1_u { - mmr_t sh_xn_pi_ni0_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_ni0_cmp_exp_data1_s; -} sh_xn_pi_ni0_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI0_CMP_ENABLE0" */ /* PI compare NI0 input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_ni0_cmp_enable0_u { mmr_t sh_xn_pi_ni0_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_pi_ni0_cmp_enable0_s; } sh_xn_pi_ni0_cmp_enable0_u_t; -#else -typedef union sh_xn_pi_ni0_cmp_enable0_u { - mmr_t sh_xn_pi_ni0_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_ni0_cmp_enable0_s; -} sh_xn_pi_ni0_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI0_CMP_ENABLE1" */ /* PI compare NI0 input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_ni0_cmp_enable1_u { - mmr_t sh_xn_pi_ni0_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_ni0_cmp_enable1_s; -} sh_xn_pi_ni0_cmp_enable1_u_t; -#else typedef union sh_xn_pi_ni0_cmp_enable1_u { mmr_t sh_xn_pi_ni0_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_pi_ni0_cmp_enable1_s; } sh_xn_pi_ni0_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI1_CMP_EXP_DATA0" */ /* PI compare NI1 input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_ni1_cmp_exp_data0_u { - mmr_t sh_xn_pi_ni1_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_ni1_cmp_exp_data0_s; -} sh_xn_pi_ni1_cmp_exp_data0_u_t; -#else typedef union sh_xn_pi_ni1_cmp_exp_data0_u { mmr_t sh_xn_pi_ni1_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_pi_ni1_cmp_exp_data0_s; } sh_xn_pi_ni1_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI1_CMP_EXP_DATA1" */ /* PI compare NI1 input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_ni1_cmp_exp_data1_u { - mmr_t sh_xn_pi_ni1_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_ni1_cmp_exp_data1_s; -} sh_xn_pi_ni1_cmp_exp_data1_u_t; -#else typedef union sh_xn_pi_ni1_cmp_exp_data1_u { mmr_t sh_xn_pi_ni1_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_pi_ni1_cmp_exp_data1_s; } sh_xn_pi_ni1_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI1_CMP_ENABLE0" */ /* PI compare NI1 input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_ni1_cmp_enable0_u { - mmr_t sh_xn_pi_ni1_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_ni1_cmp_enable0_s; -} sh_xn_pi_ni1_cmp_enable0_u_t; -#else typedef union sh_xn_pi_ni1_cmp_enable0_u { mmr_t sh_xn_pi_ni1_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_pi_ni1_cmp_enable0_s; } sh_xn_pi_ni1_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_NI1_CMP_ENABLE1" */ /* PI compare NI1 input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_ni1_cmp_enable1_u { - mmr_t sh_xn_pi_ni1_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_ni1_cmp_enable1_s; -} sh_xn_pi_ni1_cmp_enable1_u_t; -#else typedef union sh_xn_pi_ni1_cmp_enable1_u { mmr_t sh_xn_pi_ni1_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_pi_ni1_cmp_enable1_s; } sh_xn_pi_ni1_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_EXP_HDR0" */ /* PI compare SIC input expected header0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_exp_hdr0_u { - mmr_t sh_xn_pi_sic_cmp_exp_hdr0_regval; - struct { - mmr_t data : 64; - } sh_xn_pi_sic_cmp_exp_hdr0_s; -} sh_xn_pi_sic_cmp_exp_hdr0_u_t; -#else typedef union sh_xn_pi_sic_cmp_exp_hdr0_u { mmr_t sh_xn_pi_sic_cmp_exp_hdr0_regval; struct { mmr_t data : 64; } sh_xn_pi_sic_cmp_exp_hdr0_s; } sh_xn_pi_sic_cmp_exp_hdr0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_EXP_HDR1" */ /* PI compare SIC input expected header1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_sic_cmp_exp_hdr1_u { mmr_t sh_xn_pi_sic_cmp_exp_hdr1_regval; struct { @@ -12086,43 +6538,24 @@ mmr_t reserved_0 : 22; } sh_xn_pi_sic_cmp_exp_hdr1_s; } sh_xn_pi_sic_cmp_exp_hdr1_u_t; -#else -typedef union sh_xn_pi_sic_cmp_exp_hdr1_u { - mmr_t sh_xn_pi_sic_cmp_exp_hdr1_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t data : 42; - } sh_xn_pi_sic_cmp_exp_hdr1_s; -} sh_xn_pi_sic_cmp_exp_hdr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE0" */ /* PI compare SIC header enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_hdr_enable0_u { - mmr_t sh_xn_pi_sic_cmp_hdr_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_pi_sic_cmp_hdr_enable0_s; -} sh_xn_pi_sic_cmp_hdr_enable0_u_t; -#else typedef union sh_xn_pi_sic_cmp_hdr_enable0_u { mmr_t sh_xn_pi_sic_cmp_hdr_enable0_regval; struct { mmr_t enable : 64; } sh_xn_pi_sic_cmp_hdr_enable0_s; } sh_xn_pi_sic_cmp_hdr_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE1" */ /* PI compare SIC header enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_sic_cmp_hdr_enable1_u { mmr_t sh_xn_pi_sic_cmp_hdr_enable1_regval; struct { @@ -12130,1029 +6563,587 @@ mmr_t reserved_0 : 22; } sh_xn_pi_sic_cmp_hdr_enable1_s; } sh_xn_pi_sic_cmp_hdr_enable1_u_t; -#else -typedef union sh_xn_pi_sic_cmp_hdr_enable1_u { - mmr_t sh_xn_pi_sic_cmp_hdr_enable1_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t enable : 42; - } sh_xn_pi_sic_cmp_hdr_enable1_s; -} sh_xn_pi_sic_cmp_hdr_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA0" */ /* PI compare SIC data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_data0_u { - mmr_t sh_xn_pi_sic_cmp_data0_regval; - struct { - mmr_t data0 : 64; - } sh_xn_pi_sic_cmp_data0_s; -} sh_xn_pi_sic_cmp_data0_u_t; -#else typedef union sh_xn_pi_sic_cmp_data0_u { mmr_t sh_xn_pi_sic_cmp_data0_regval; struct { mmr_t data0 : 64; } sh_xn_pi_sic_cmp_data0_s; } sh_xn_pi_sic_cmp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA1" */ /* PI compare SIC data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_data1_u { - mmr_t sh_xn_pi_sic_cmp_data1_regval; - struct { - mmr_t data1 : 64; - } sh_xn_pi_sic_cmp_data1_s; -} sh_xn_pi_sic_cmp_data1_u_t; -#else typedef union sh_xn_pi_sic_cmp_data1_u { mmr_t sh_xn_pi_sic_cmp_data1_regval; struct { mmr_t data1 : 64; } sh_xn_pi_sic_cmp_data1_s; } sh_xn_pi_sic_cmp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA2" */ /* PI compare SIC data2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_data2_u { - mmr_t sh_xn_pi_sic_cmp_data2_regval; - struct { - mmr_t data2 : 64; - } sh_xn_pi_sic_cmp_data2_s; -} sh_xn_pi_sic_cmp_data2_u_t; -#else typedef union sh_xn_pi_sic_cmp_data2_u { mmr_t sh_xn_pi_sic_cmp_data2_regval; struct { mmr_t data2 : 64; } sh_xn_pi_sic_cmp_data2_s; } sh_xn_pi_sic_cmp_data2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA3" */ /* PI compare SIC data3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_pi_sic_cmp_data3_u { mmr_t sh_xn_pi_sic_cmp_data3_regval; struct { mmr_t data3 : 64; } sh_xn_pi_sic_cmp_data3_s; } sh_xn_pi_sic_cmp_data3_u_t; -#else -typedef union sh_xn_pi_sic_cmp_data3_u { - mmr_t sh_xn_pi_sic_cmp_data3_regval; - struct { - mmr_t data3 : 64; - } sh_xn_pi_sic_cmp_data3_s; -} sh_xn_pi_sic_cmp_data3_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE0" */ /* PI enable compare SIC data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_data_enable0_u { - mmr_t sh_xn_pi_sic_cmp_data_enable0_regval; - struct { - mmr_t data_enable0 : 64; - } sh_xn_pi_sic_cmp_data_enable0_s; -} sh_xn_pi_sic_cmp_data_enable0_u_t; -#else typedef union sh_xn_pi_sic_cmp_data_enable0_u { mmr_t sh_xn_pi_sic_cmp_data_enable0_regval; struct { mmr_t data_enable0 : 64; } sh_xn_pi_sic_cmp_data_enable0_s; } sh_xn_pi_sic_cmp_data_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE1" */ /* PI enable compare SIC data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_data_enable1_u { - mmr_t sh_xn_pi_sic_cmp_data_enable1_regval; - struct { - mmr_t data_enable1 : 64; - } sh_xn_pi_sic_cmp_data_enable1_s; -} sh_xn_pi_sic_cmp_data_enable1_u_t; -#else typedef union sh_xn_pi_sic_cmp_data_enable1_u { mmr_t sh_xn_pi_sic_cmp_data_enable1_regval; struct { mmr_t data_enable1 : 64; } sh_xn_pi_sic_cmp_data_enable1_s; } sh_xn_pi_sic_cmp_data_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE2" */ /* PI enable compare SIC data2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_data_enable2_u { - mmr_t sh_xn_pi_sic_cmp_data_enable2_regval; - struct { - mmr_t data_enable2 : 64; - } sh_xn_pi_sic_cmp_data_enable2_s; -} sh_xn_pi_sic_cmp_data_enable2_u_t; -#else typedef union sh_xn_pi_sic_cmp_data_enable2_u { mmr_t sh_xn_pi_sic_cmp_data_enable2_regval; struct { mmr_t data_enable2 : 64; } sh_xn_pi_sic_cmp_data_enable2_s; } sh_xn_pi_sic_cmp_data_enable2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE3" */ /* PI enable compare SIC data3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_pi_sic_cmp_data_enable3_u { - mmr_t sh_xn_pi_sic_cmp_data_enable3_regval; - struct { - mmr_t data_enable3 : 64; - } sh_xn_pi_sic_cmp_data_enable3_s; -} sh_xn_pi_sic_cmp_data_enable3_u_t; -#else typedef union sh_xn_pi_sic_cmp_data_enable3_u { mmr_t sh_xn_pi_sic_cmp_data_enable3_regval; struct { mmr_t data_enable3 : 64; } sh_xn_pi_sic_cmp_data_enable3_s; } sh_xn_pi_sic_cmp_data_enable3_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_IILB_CMP_EXP_DATA0" */ /* NI0 compare IILB input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_iilb_cmp_exp_data0_u { - mmr_t sh_xn_ni0_iilb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_iilb_cmp_exp_data0_s; -} sh_xn_ni0_iilb_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni0_iilb_cmp_exp_data0_u { mmr_t sh_xn_ni0_iilb_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni0_iilb_cmp_exp_data0_s; } sh_xn_ni0_iilb_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_IILB_CMP_EXP_DATA1" */ /* NI0 compare IILB input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni0_iilb_cmp_exp_data1_u { mmr_t sh_xn_ni0_iilb_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni0_iilb_cmp_exp_data1_s; } sh_xn_ni0_iilb_cmp_exp_data1_u_t; -#else -typedef union sh_xn_ni0_iilb_cmp_exp_data1_u { - mmr_t sh_xn_ni0_iilb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_iilb_cmp_exp_data1_s; -} sh_xn_ni0_iilb_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_IILB_CMP_ENABLE0" */ /* NI0 compare IILB input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_iilb_cmp_enable0_u { - mmr_t sh_xn_ni0_iilb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_iilb_cmp_enable0_s; -} sh_xn_ni0_iilb_cmp_enable0_u_t; -#else typedef union sh_xn_ni0_iilb_cmp_enable0_u { mmr_t sh_xn_ni0_iilb_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni0_iilb_cmp_enable0_s; } sh_xn_ni0_iilb_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_IILB_CMP_ENABLE1" */ /* NI0 compare IILB input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_iilb_cmp_enable1_u { - mmr_t sh_xn_ni0_iilb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_iilb_cmp_enable1_s; -} sh_xn_ni0_iilb_cmp_enable1_u_t; -#else typedef union sh_xn_ni0_iilb_cmp_enable1_u { mmr_t sh_xn_ni0_iilb_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni0_iilb_cmp_enable1_s; } sh_xn_ni0_iilb_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_PI_CMP_EXP_DATA0" */ /* NI0 compare PI input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_pi_cmp_exp_data0_u { - mmr_t sh_xn_ni0_pi_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_pi_cmp_exp_data0_s; -} sh_xn_ni0_pi_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni0_pi_cmp_exp_data0_u { mmr_t sh_xn_ni0_pi_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni0_pi_cmp_exp_data0_s; } sh_xn_ni0_pi_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_PI_CMP_EXP_DATA1" */ /* NI0 compare PI input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni0_pi_cmp_exp_data1_u { mmr_t sh_xn_ni0_pi_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni0_pi_cmp_exp_data1_s; } sh_xn_ni0_pi_cmp_exp_data1_u_t; -#else -typedef union sh_xn_ni0_pi_cmp_exp_data1_u { - mmr_t sh_xn_ni0_pi_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_pi_cmp_exp_data1_s; -} sh_xn_ni0_pi_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_PI_CMP_ENABLE0" */ /* NI0 compare PI input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni0_pi_cmp_enable0_u { mmr_t sh_xn_ni0_pi_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni0_pi_cmp_enable0_s; } sh_xn_ni0_pi_cmp_enable0_u_t; -#else -typedef union sh_xn_ni0_pi_cmp_enable0_u { - mmr_t sh_xn_ni0_pi_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_pi_cmp_enable0_s; -} sh_xn_ni0_pi_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_PI_CMP_ENABLE1" */ /* NI0 compare PI input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni0_pi_cmp_enable1_u { mmr_t sh_xn_ni0_pi_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni0_pi_cmp_enable1_s; } sh_xn_ni0_pi_cmp_enable1_u_t; -#else -typedef union sh_xn_ni0_pi_cmp_enable1_u { - mmr_t sh_xn_ni0_pi_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_pi_cmp_enable1_s; -} sh_xn_ni0_pi_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_MD_CMP_EXP_DATA0" */ /* NI0 compare MD input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_md_cmp_exp_data0_u { - mmr_t sh_xn_ni0_md_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_md_cmp_exp_data0_s; -} sh_xn_ni0_md_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni0_md_cmp_exp_data0_u { mmr_t sh_xn_ni0_md_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni0_md_cmp_exp_data0_s; } sh_xn_ni0_md_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_MD_CMP_EXP_DATA1" */ /* NI0 compare MD input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_md_cmp_exp_data1_u { - mmr_t sh_xn_ni0_md_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_md_cmp_exp_data1_s; -} sh_xn_ni0_md_cmp_exp_data1_u_t; -#else typedef union sh_xn_ni0_md_cmp_exp_data1_u { mmr_t sh_xn_ni0_md_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni0_md_cmp_exp_data1_s; } sh_xn_ni0_md_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_MD_CMP_ENABLE0" */ /* NI0 compare MD input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni0_md_cmp_enable0_u { mmr_t sh_xn_ni0_md_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni0_md_cmp_enable0_s; } sh_xn_ni0_md_cmp_enable0_u_t; -#else -typedef union sh_xn_ni0_md_cmp_enable0_u { - mmr_t sh_xn_ni0_md_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_md_cmp_enable0_s; -} sh_xn_ni0_md_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_MD_CMP_ENABLE1" */ /* NI0 compare MD input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_md_cmp_enable1_u { - mmr_t sh_xn_ni0_md_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_md_cmp_enable1_s; -} sh_xn_ni0_md_cmp_enable1_u_t; -#else typedef union sh_xn_ni0_md_cmp_enable1_u { mmr_t sh_xn_ni0_md_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni0_md_cmp_enable1_s; } sh_xn_ni0_md_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_NI_CMP_EXP_DATA0" */ /* NI0 compare NI input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_ni_cmp_exp_data0_u { - mmr_t sh_xn_ni0_ni_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_ni_cmp_exp_data0_s; -} sh_xn_ni0_ni_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni0_ni_cmp_exp_data0_u { mmr_t sh_xn_ni0_ni_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni0_ni_cmp_exp_data0_s; } sh_xn_ni0_ni_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_NI_CMP_EXP_DATA1" */ /* NI0 compare NI input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_ni_cmp_exp_data1_u { - mmr_t sh_xn_ni0_ni_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_ni_cmp_exp_data1_s; -} sh_xn_ni0_ni_cmp_exp_data1_u_t; -#else typedef union sh_xn_ni0_ni_cmp_exp_data1_u { mmr_t sh_xn_ni0_ni_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni0_ni_cmp_exp_data1_s; } sh_xn_ni0_ni_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_NI_CMP_ENABLE0" */ /* NI0 compare NI input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_ni_cmp_enable0_u { - mmr_t sh_xn_ni0_ni_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_ni_cmp_enable0_s; -} sh_xn_ni0_ni_cmp_enable0_u_t; -#else typedef union sh_xn_ni0_ni_cmp_enable0_u { mmr_t sh_xn_ni0_ni_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni0_ni_cmp_enable0_s; } sh_xn_ni0_ni_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_NI_CMP_ENABLE1" */ /* NI0 compare NI input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni0_ni_cmp_enable1_u { mmr_t sh_xn_ni0_ni_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni0_ni_cmp_enable1_s; } sh_xn_ni0_ni_cmp_enable1_u_t; -#else -typedef union sh_xn_ni0_ni_cmp_enable1_u { - mmr_t sh_xn_ni0_ni_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_ni_cmp_enable1_s; -} sh_xn_ni0_ni_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_LLP_CMP_EXP_DATA0" */ /* NI0 compare LLP input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_llp_cmp_exp_data0_u { - mmr_t sh_xn_ni0_llp_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_llp_cmp_exp_data0_s; -} sh_xn_ni0_llp_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni0_llp_cmp_exp_data0_u { mmr_t sh_xn_ni0_llp_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni0_llp_cmp_exp_data0_s; } sh_xn_ni0_llp_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_LLP_CMP_EXP_DATA1" */ /* NI0 compare LLP input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_llp_cmp_exp_data1_u { - mmr_t sh_xn_ni0_llp_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni0_llp_cmp_exp_data1_s; -} sh_xn_ni0_llp_cmp_exp_data1_u_t; -#else typedef union sh_xn_ni0_llp_cmp_exp_data1_u { mmr_t sh_xn_ni0_llp_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni0_llp_cmp_exp_data1_s; } sh_xn_ni0_llp_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_LLP_CMP_ENABLE0" */ /* NI0 compare LLP input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_llp_cmp_enable0_u { - mmr_t sh_xn_ni0_llp_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_llp_cmp_enable0_s; -} sh_xn_ni0_llp_cmp_enable0_u_t; -#else typedef union sh_xn_ni0_llp_cmp_enable0_u { mmr_t sh_xn_ni0_llp_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni0_llp_cmp_enable0_s; } sh_xn_ni0_llp_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI0_LLP_CMP_ENABLE1" */ /* NI0 compare LLP input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni0_llp_cmp_enable1_u { - mmr_t sh_xn_ni0_llp_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni0_llp_cmp_enable1_s; -} sh_xn_ni0_llp_cmp_enable1_u_t; -#else typedef union sh_xn_ni0_llp_cmp_enable1_u { mmr_t sh_xn_ni0_llp_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni0_llp_cmp_enable1_s; } sh_xn_ni0_llp_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_IILB_CMP_EXP_DATA0" */ /* NI1 compare IILB input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_iilb_cmp_exp_data0_u { mmr_t sh_xn_ni1_iilb_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni1_iilb_cmp_exp_data0_s; } sh_xn_ni1_iilb_cmp_exp_data0_u_t; -#else -typedef union sh_xn_ni1_iilb_cmp_exp_data0_u { - mmr_t sh_xn_ni1_iilb_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_iilb_cmp_exp_data0_s; -} sh_xn_ni1_iilb_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_IILB_CMP_EXP_DATA1" */ /* NI1 compare IILB input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_iilb_cmp_exp_data1_u { mmr_t sh_xn_ni1_iilb_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni1_iilb_cmp_exp_data1_s; } sh_xn_ni1_iilb_cmp_exp_data1_u_t; -#else -typedef union sh_xn_ni1_iilb_cmp_exp_data1_u { - mmr_t sh_xn_ni1_iilb_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_iilb_cmp_exp_data1_s; -} sh_xn_ni1_iilb_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_IILB_CMP_ENABLE0" */ /* NI1 compare IILB input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_iilb_cmp_enable0_u { - mmr_t sh_xn_ni1_iilb_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_iilb_cmp_enable0_s; -} sh_xn_ni1_iilb_cmp_enable0_u_t; -#else typedef union sh_xn_ni1_iilb_cmp_enable0_u { mmr_t sh_xn_ni1_iilb_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni1_iilb_cmp_enable0_s; } sh_xn_ni1_iilb_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_IILB_CMP_ENABLE1" */ /* NI1 compare IILB input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_iilb_cmp_enable1_u { - mmr_t sh_xn_ni1_iilb_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_iilb_cmp_enable1_s; -} sh_xn_ni1_iilb_cmp_enable1_u_t; -#else typedef union sh_xn_ni1_iilb_cmp_enable1_u { mmr_t sh_xn_ni1_iilb_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni1_iilb_cmp_enable1_s; } sh_xn_ni1_iilb_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_PI_CMP_EXP_DATA0" */ /* NI1 compare PI input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_pi_cmp_exp_data0_u { - mmr_t sh_xn_ni1_pi_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_pi_cmp_exp_data0_s; -} sh_xn_ni1_pi_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni1_pi_cmp_exp_data0_u { mmr_t sh_xn_ni1_pi_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni1_pi_cmp_exp_data0_s; } sh_xn_ni1_pi_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_PI_CMP_EXP_DATA1" */ /* NI1 compare PI input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_pi_cmp_exp_data1_u { mmr_t sh_xn_ni1_pi_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni1_pi_cmp_exp_data1_s; } sh_xn_ni1_pi_cmp_exp_data1_u_t; -#else -typedef union sh_xn_ni1_pi_cmp_exp_data1_u { - mmr_t sh_xn_ni1_pi_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_pi_cmp_exp_data1_s; -} sh_xn_ni1_pi_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_PI_CMP_ENABLE0" */ /* NI1 compare PI input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_pi_cmp_enable0_u { - mmr_t sh_xn_ni1_pi_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_pi_cmp_enable0_s; -} sh_xn_ni1_pi_cmp_enable0_u_t; -#else typedef union sh_xn_ni1_pi_cmp_enable0_u { mmr_t sh_xn_ni1_pi_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni1_pi_cmp_enable0_s; } sh_xn_ni1_pi_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_PI_CMP_ENABLE1" */ /* NI1 compare PI input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_pi_cmp_enable1_u { - mmr_t sh_xn_ni1_pi_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_pi_cmp_enable1_s; -} sh_xn_ni1_pi_cmp_enable1_u_t; -#else typedef union sh_xn_ni1_pi_cmp_enable1_u { mmr_t sh_xn_ni1_pi_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni1_pi_cmp_enable1_s; } sh_xn_ni1_pi_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_MD_CMP_EXP_DATA0" */ /* NI1 compare MD input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_md_cmp_exp_data0_u { mmr_t sh_xn_ni1_md_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni1_md_cmp_exp_data0_s; } sh_xn_ni1_md_cmp_exp_data0_u_t; -#else -typedef union sh_xn_ni1_md_cmp_exp_data0_u { - mmr_t sh_xn_ni1_md_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_md_cmp_exp_data0_s; -} sh_xn_ni1_md_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_MD_CMP_EXP_DATA1" */ /* NI1 compare MD input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_md_cmp_exp_data1_u { - mmr_t sh_xn_ni1_md_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_md_cmp_exp_data1_s; -} sh_xn_ni1_md_cmp_exp_data1_u_t; -#else typedef union sh_xn_ni1_md_cmp_exp_data1_u { mmr_t sh_xn_ni1_md_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni1_md_cmp_exp_data1_s; } sh_xn_ni1_md_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_MD_CMP_ENABLE0" */ /* NI1 compare MD input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_md_cmp_enable0_u { mmr_t sh_xn_ni1_md_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni1_md_cmp_enable0_s; } sh_xn_ni1_md_cmp_enable0_u_t; -#else -typedef union sh_xn_ni1_md_cmp_enable0_u { - mmr_t sh_xn_ni1_md_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_md_cmp_enable0_s; -} sh_xn_ni1_md_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_MD_CMP_ENABLE1" */ /* NI1 compare MD input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_md_cmp_enable1_u { mmr_t sh_xn_ni1_md_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni1_md_cmp_enable1_s; } sh_xn_ni1_md_cmp_enable1_u_t; -#else -typedef union sh_xn_ni1_md_cmp_enable1_u { - mmr_t sh_xn_ni1_md_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_md_cmp_enable1_s; -} sh_xn_ni1_md_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_NI_CMP_EXP_DATA0" */ /* NI1 compare NI input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_ni_cmp_exp_data0_u { - mmr_t sh_xn_ni1_ni_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_ni_cmp_exp_data0_s; -} sh_xn_ni1_ni_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni1_ni_cmp_exp_data0_u { mmr_t sh_xn_ni1_ni_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni1_ni_cmp_exp_data0_s; } sh_xn_ni1_ni_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_NI_CMP_EXP_DATA1" */ /* NI1 compare NI input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_ni1_ni_cmp_exp_data1_u { mmr_t sh_xn_ni1_ni_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni1_ni_cmp_exp_data1_s; } sh_xn_ni1_ni_cmp_exp_data1_u_t; -#else -typedef union sh_xn_ni1_ni_cmp_exp_data1_u { - mmr_t sh_xn_ni1_ni_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_ni_cmp_exp_data1_s; -} sh_xn_ni1_ni_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_NI_CMP_ENABLE0" */ /* NI1 compare NI input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_ni_cmp_enable0_u { - mmr_t sh_xn_ni1_ni_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_ni_cmp_enable0_s; -} sh_xn_ni1_ni_cmp_enable0_u_t; -#else typedef union sh_xn_ni1_ni_cmp_enable0_u { mmr_t sh_xn_ni1_ni_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni1_ni_cmp_enable0_s; } sh_xn_ni1_ni_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_NI_CMP_ENABLE1" */ /* NI1 compare NI input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_ni_cmp_enable1_u { - mmr_t sh_xn_ni1_ni_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_ni_cmp_enable1_s; -} sh_xn_ni1_ni_cmp_enable1_u_t; -#else typedef union sh_xn_ni1_ni_cmp_enable1_u { mmr_t sh_xn_ni1_ni_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni1_ni_cmp_enable1_s; } sh_xn_ni1_ni_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_LLP_CMP_EXP_DATA0" */ /* NI1 compare LLP input expected data0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_llp_cmp_exp_data0_u { - mmr_t sh_xn_ni1_llp_cmp_exp_data0_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_llp_cmp_exp_data0_s; -} sh_xn_ni1_llp_cmp_exp_data0_u_t; -#else typedef union sh_xn_ni1_llp_cmp_exp_data0_u { mmr_t sh_xn_ni1_llp_cmp_exp_data0_regval; struct { mmr_t data : 64; } sh_xn_ni1_llp_cmp_exp_data0_s; } sh_xn_ni1_llp_cmp_exp_data0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_LLP_CMP_EXP_DATA1" */ /* NI1 compare LLP input expected data1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_llp_cmp_exp_data1_u { - mmr_t sh_xn_ni1_llp_cmp_exp_data1_regval; - struct { - mmr_t data : 64; - } sh_xn_ni1_llp_cmp_exp_data1_s; -} sh_xn_ni1_llp_cmp_exp_data1_u_t; -#else typedef union sh_xn_ni1_llp_cmp_exp_data1_u { mmr_t sh_xn_ni1_llp_cmp_exp_data1_regval; struct { mmr_t data : 64; } sh_xn_ni1_llp_cmp_exp_data1_s; } sh_xn_ni1_llp_cmp_exp_data1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_LLP_CMP_ENABLE0" */ /* NI1 compare LLP input enable0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_llp_cmp_enable0_u { - mmr_t sh_xn_ni1_llp_cmp_enable0_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_llp_cmp_enable0_s; -} sh_xn_ni1_llp_cmp_enable0_u_t; -#else typedef union sh_xn_ni1_llp_cmp_enable0_u { mmr_t sh_xn_ni1_llp_cmp_enable0_regval; struct { mmr_t enable : 64; } sh_xn_ni1_llp_cmp_enable0_s; } sh_xn_ni1_llp_cmp_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_NI1_LLP_CMP_ENABLE1" */ /* NI1 compare LLP input enable1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_ni1_llp_cmp_enable1_u { - mmr_t sh_xn_ni1_llp_cmp_enable1_regval; - struct { - mmr_t enable : 64; - } sh_xn_ni1_llp_cmp_enable1_s; -} sh_xn_ni1_llp_cmp_enable1_u_t; -#else typedef union sh_xn_ni1_llp_cmp_enable1_u { mmr_t sh_xn_ni1_llp_cmp_enable1_regval; struct { mmr_t enable : 64; } sh_xn_ni1_llp_cmp_enable1_s; } sh_xn_ni1_llp_cmp_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ECC_INJ_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_ecc_inj_reg_u { mmr_t sh_xnpi_ecc_inj_reg_regval; struct { @@ -13182,123 +7173,55 @@ mmr_t data_cb_cont3 : 1; } sh_xnpi_ecc_inj_reg_s; } sh_xnpi_ecc_inj_reg_u_t; -#else -typedef union sh_xnpi_ecc_inj_reg_u { - mmr_t sh_xnpi_ecc_inj_reg_regval; - struct { - mmr_t data_cb_cont3 : 1; - mmr_t data_cb_1shot3 : 1; - mmr_t data_cont3 : 1; - mmr_t data_1shot3 : 1; - mmr_t reserved_3 : 4; - mmr_t byte3 : 8; - mmr_t data_cb_cont2 : 1; - mmr_t data_cb_1shot2 : 1; - mmr_t data_cont2 : 1; - mmr_t data_1shot2 : 1; - mmr_t reserved_2 : 4; - mmr_t byte2 : 8; - mmr_t data_cb_cont1 : 1; - mmr_t data_cb_1shot1 : 1; - mmr_t data_cont1 : 1; - mmr_t data_1shot1 : 1; - mmr_t reserved_1 : 4; - mmr_t byte1 : 8; - mmr_t data_cb_cont0 : 1; - mmr_t data_cb_1shot0 : 1; - mmr_t data_cont0 : 1; - mmr_t data_1shot0 : 1; - mmr_t reserved_0 : 4; - mmr_t byte0 : 8; - } sh_xnpi_ecc_inj_reg_s; -} sh_xnpi_ecc_inj_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ECC0_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_ecc0_inj_mask_reg_u { mmr_t sh_xnpi_ecc0_inj_mask_reg_regval; struct { mmr_t mask_ecc0 : 64; } sh_xnpi_ecc0_inj_mask_reg_s; } sh_xnpi_ecc0_inj_mask_reg_u_t; -#else -typedef union sh_xnpi_ecc0_inj_mask_reg_u { - mmr_t sh_xnpi_ecc0_inj_mask_reg_regval; - struct { - mmr_t mask_ecc0 : 64; - } sh_xnpi_ecc0_inj_mask_reg_s; -} sh_xnpi_ecc0_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ECC1_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xnpi_ecc1_inj_mask_reg_u { - mmr_t sh_xnpi_ecc1_inj_mask_reg_regval; - struct { - mmr_t mask_ecc1 : 64; - } sh_xnpi_ecc1_inj_mask_reg_s; -} sh_xnpi_ecc1_inj_mask_reg_u_t; -#else typedef union sh_xnpi_ecc1_inj_mask_reg_u { mmr_t sh_xnpi_ecc1_inj_mask_reg_regval; struct { mmr_t mask_ecc1 : 64; } sh_xnpi_ecc1_inj_mask_reg_s; } sh_xnpi_ecc1_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ECC2_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xnpi_ecc2_inj_mask_reg_u { - mmr_t sh_xnpi_ecc2_inj_mask_reg_regval; - struct { - mmr_t mask_ecc2 : 64; - } sh_xnpi_ecc2_inj_mask_reg_s; -} sh_xnpi_ecc2_inj_mask_reg_u_t; -#else typedef union sh_xnpi_ecc2_inj_mask_reg_u { mmr_t sh_xnpi_ecc2_inj_mask_reg_regval; struct { mmr_t mask_ecc2 : 64; } sh_xnpi_ecc2_inj_mask_reg_s; } sh_xnpi_ecc2_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ECC3_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_ecc3_inj_mask_reg_u { mmr_t sh_xnpi_ecc3_inj_mask_reg_regval; struct { mmr_t mask_ecc3 : 64; } sh_xnpi_ecc3_inj_mask_reg_s; } sh_xnpi_ecc3_inj_mask_reg_u_t; -#else -typedef union sh_xnpi_ecc3_inj_mask_reg_u { - mmr_t sh_xnpi_ecc3_inj_mask_reg_regval; - struct { - mmr_t mask_ecc3 : 64; - } sh_xnpi_ecc3_inj_mask_reg_s; -} sh_xnpi_ecc3_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ECC_INJ_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_ecc_inj_reg_u { mmr_t sh_xnmd_ecc_inj_reg_regval; struct { @@ -13328,123 +7251,55 @@ mmr_t data_cb_cont3 : 1; } sh_xnmd_ecc_inj_reg_s; } sh_xnmd_ecc_inj_reg_u_t; -#else -typedef union sh_xnmd_ecc_inj_reg_u { - mmr_t sh_xnmd_ecc_inj_reg_regval; - struct { - mmr_t data_cb_cont3 : 1; - mmr_t data_cb_1shot3 : 1; - mmr_t data_cont3 : 1; - mmr_t data_1shot3 : 1; - mmr_t reserved_3 : 4; - mmr_t byte3 : 8; - mmr_t data_cb_cont2 : 1; - mmr_t data_cb_1shot2 : 1; - mmr_t data_cont2 : 1; - mmr_t data_1shot2 : 1; - mmr_t reserved_2 : 4; - mmr_t byte2 : 8; - mmr_t data_cb_cont1 : 1; - mmr_t data_cb_1shot1 : 1; - mmr_t data_cont1 : 1; - mmr_t data_1shot1 : 1; - mmr_t reserved_1 : 4; - mmr_t byte1 : 8; - mmr_t data_cb_cont0 : 1; - mmr_t data_cb_1shot0 : 1; - mmr_t data_cont0 : 1; - mmr_t data_1shot0 : 1; - mmr_t reserved_0 : 4; - mmr_t byte0 : 8; - } sh_xnmd_ecc_inj_reg_s; -} sh_xnmd_ecc_inj_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ECC0_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xnmd_ecc0_inj_mask_reg_u { - mmr_t sh_xnmd_ecc0_inj_mask_reg_regval; - struct { - mmr_t mask_ecc0 : 64; - } sh_xnmd_ecc0_inj_mask_reg_s; -} sh_xnmd_ecc0_inj_mask_reg_u_t; -#else typedef union sh_xnmd_ecc0_inj_mask_reg_u { mmr_t sh_xnmd_ecc0_inj_mask_reg_regval; struct { mmr_t mask_ecc0 : 64; } sh_xnmd_ecc0_inj_mask_reg_s; } sh_xnmd_ecc0_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ECC1_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_ecc1_inj_mask_reg_u { mmr_t sh_xnmd_ecc1_inj_mask_reg_regval; struct { mmr_t mask_ecc1 : 64; } sh_xnmd_ecc1_inj_mask_reg_s; } sh_xnmd_ecc1_inj_mask_reg_u_t; -#else -typedef union sh_xnmd_ecc1_inj_mask_reg_u { - mmr_t sh_xnmd_ecc1_inj_mask_reg_regval; - struct { - mmr_t mask_ecc1 : 64; - } sh_xnmd_ecc1_inj_mask_reg_s; -} sh_xnmd_ecc1_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ECC2_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xnmd_ecc2_inj_mask_reg_u { - mmr_t sh_xnmd_ecc2_inj_mask_reg_regval; - struct { - mmr_t mask_ecc2 : 64; - } sh_xnmd_ecc2_inj_mask_reg_s; -} sh_xnmd_ecc2_inj_mask_reg_u_t; -#else typedef union sh_xnmd_ecc2_inj_mask_reg_u { mmr_t sh_xnmd_ecc2_inj_mask_reg_regval; struct { mmr_t mask_ecc2 : 64; } sh_xnmd_ecc2_inj_mask_reg_s; } sh_xnmd_ecc2_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ECC3_INJ_MASK_REG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xnmd_ecc3_inj_mask_reg_u { - mmr_t sh_xnmd_ecc3_inj_mask_reg_regval; - struct { - mmr_t mask_ecc3 : 64; - } sh_xnmd_ecc3_inj_mask_reg_s; -} sh_xnmd_ecc3_inj_mask_reg_u_t; -#else typedef union sh_xnmd_ecc3_inj_mask_reg_u { mmr_t sh_xnmd_ecc3_inj_mask_reg_regval; struct { mmr_t mask_ecc3 : 64; } sh_xnmd_ecc3_inj_mask_reg_s; } sh_xnmd_ecc3_inj_mask_reg_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ECC_ERR_REPORT" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_ecc_err_report_u { mmr_t sh_xnmd_ecc_err_report_regval; struct { @@ -13458,28 +7313,12 @@ mmr_t reserved_3 : 15; } sh_xnmd_ecc_err_report_s; } sh_xnmd_ecc_err_report_u_t; -#else -typedef union sh_xnmd_ecc_err_report_u { - mmr_t sh_xnmd_ecc_err_report_regval; - struct { - mmr_t reserved_3 : 15; - mmr_t ecc_disable3 : 1; - mmr_t reserved_2 : 15; - mmr_t ecc_disable2 : 1; - mmr_t reserved_1 : 15; - mmr_t ecc_disable1 : 1; - mmr_t reserved_0 : 15; - mmr_t ecc_disable0 : 1; - } sh_xnmd_ecc_err_report_s; -} sh_xnmd_ecc_err_report_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_SUMMARY_1" */ /* ni0 Error Summary Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_error_summary_1_u { mmr_t sh_ni0_error_summary_1_regval; struct { @@ -13549,84 +7388,12 @@ mmr_t tail_timeout_ni_vc3 : 1; } sh_ni0_error_summary_1_s; } sh_ni0_error_summary_1_u_t; -#else -typedef union sh_ni0_error_summary_1_u { - mmr_t sh_ni0_error_summary_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni0_error_summary_1_s; -} sh_ni0_error_summary_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_SUMMARY_2" */ /* ni0 Error Summary Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_error_summary_2_u { mmr_t sh_ni0_error_summary_2_regval; struct { @@ -13687,75 +7454,12 @@ mmr_t reserved_1 : 1; } sh_ni0_error_summary_2_s; } sh_ni0_error_summary_2_u_t; -#else -typedef union sh_ni0_error_summary_2_u { - mmr_t sh_ni0_error_summary_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni0_error_summary_2_s; -} sh_ni0_error_summary_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_OVERFLOW_1" */ /* ni0 Error Overflow Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_error_overflow_1_u { mmr_t sh_ni0_error_overflow_1_regval; struct { @@ -13825,84 +7529,12 @@ mmr_t tail_timeout_ni_vc3 : 1; } sh_ni0_error_overflow_1_s; } sh_ni0_error_overflow_1_u_t; -#else -typedef union sh_ni0_error_overflow_1_u { - mmr_t sh_ni0_error_overflow_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni0_error_overflow_1_s; -} sh_ni0_error_overflow_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_OVERFLOW_2" */ /* ni0 Error Overflow Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_error_overflow_2_u { mmr_t sh_ni0_error_overflow_2_regval; struct { @@ -13963,75 +7595,12 @@ mmr_t reserved_1 : 1; } sh_ni0_error_overflow_2_s; } sh_ni0_error_overflow_2_u_t; -#else -typedef union sh_ni0_error_overflow_2_u { - mmr_t sh_ni0_error_overflow_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni0_error_overflow_2_s; -} sh_ni0_error_overflow_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_MASK_1" */ /* ni0 Error Mask Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_error_mask_1_u { mmr_t sh_ni0_error_mask_1_regval; struct { @@ -14101,84 +7670,12 @@ mmr_t tail_timeout_ni_vc3 : 1; } sh_ni0_error_mask_1_s; } sh_ni0_error_mask_1_u_t; -#else -typedef union sh_ni0_error_mask_1_u { - mmr_t sh_ni0_error_mask_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni0_error_mask_1_s; -} sh_ni0_error_mask_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_MASK_2" */ /* ni0 Error Mask Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_error_mask_2_u { mmr_t sh_ni0_error_mask_2_regval; struct { @@ -14239,75 +7736,12 @@ mmr_t reserved_1 : 1; } sh_ni0_error_mask_2_s; } sh_ni0_error_mask_2_u_t; -#else -typedef union sh_ni0_error_mask_2_u { - mmr_t sh_ni0_error_mask_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni0_error_mask_2_s; -} sh_ni0_error_mask_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_FIRST_ERROR_1" */ /* ni0 First Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_first_error_1_u { mmr_t sh_ni0_first_error_1_regval; struct { @@ -14377,84 +7811,12 @@ mmr_t tail_timeout_ni_vc3 : 1; } sh_ni0_first_error_1_s; } sh_ni0_first_error_1_u_t; -#else -typedef union sh_ni0_first_error_1_u { - mmr_t sh_ni0_first_error_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni0_first_error_1_s; -} sh_ni0_first_error_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_FIRST_ERROR_2" */ /* ni0 First Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_first_error_2_u { mmr_t sh_ni0_first_error_2_regval; struct { @@ -14515,117 +7877,36 @@ mmr_t reserved_1 : 1; } sh_ni0_first_error_2_s; } sh_ni0_first_error_2_u_t; -#else -typedef union sh_ni0_first_error_2_u { - mmr_t sh_ni0_first_error_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni0_first_error_2_s; -} sh_ni0_first_error_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_DETAIL_1" */ /* ni0 Chiplet no match header bits 63:0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni0_error_detail_1_u { - mmr_t sh_ni0_error_detail_1_regval; - struct { - mmr_t header : 64; - } sh_ni0_error_detail_1_s; -} sh_ni0_error_detail_1_u_t; -#else typedef union sh_ni0_error_detail_1_u { mmr_t sh_ni0_error_detail_1_regval; struct { mmr_t header : 64; } sh_ni0_error_detail_1_s; } sh_ni0_error_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_DETAIL_2" */ /* ni0 Chiplet no match header bits 127:64 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni0_error_detail_2_u { - mmr_t sh_ni0_error_detail_2_regval; - struct { - mmr_t header : 64; - } sh_ni0_error_detail_2_s; -} sh_ni0_error_detail_2_u_t; -#else typedef union sh_ni0_error_detail_2_u { mmr_t sh_ni0_error_detail_2_regval; struct { mmr_t header : 64; } sh_ni0_error_detail_2_s; } sh_ni0_error_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_SUMMARY_1" */ /* ni1 Error Summary Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_summary_1_u { mmr_t sh_ni1_error_summary_1_regval; struct { @@ -14695,84 +7976,12 @@ mmr_t tail_timeout_ni_vc3 : 1; } sh_ni1_error_summary_1_s; } sh_ni1_error_summary_1_u_t; -#else -typedef union sh_ni1_error_summary_1_u { - mmr_t sh_ni1_error_summary_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni1_error_summary_1_s; -} sh_ni1_error_summary_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_SUMMARY_2" */ /* ni1 Error Summary Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_summary_2_u { mmr_t sh_ni1_error_summary_2_regval; struct { @@ -14833,75 +8042,12 @@ mmr_t reserved_1 : 1; } sh_ni1_error_summary_2_s; } sh_ni1_error_summary_2_u_t; -#else -typedef union sh_ni1_error_summary_2_u { - mmr_t sh_ni1_error_summary_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni1_error_summary_2_s; -} sh_ni1_error_summary_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_OVERFLOW_1" */ /* ni1 Error Overflow Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_overflow_1_u { mmr_t sh_ni1_error_overflow_1_regval; struct { @@ -14971,84 +8117,12 @@ mmr_t tail_timeout_ni_vc3 : 1; } sh_ni1_error_overflow_1_s; } sh_ni1_error_overflow_1_u_t; -#else -typedef union sh_ni1_error_overflow_1_u { - mmr_t sh_ni1_error_overflow_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni1_error_overflow_1_s; -} sh_ni1_error_overflow_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_OVERFLOW_2" */ /* ni1 Error Overflow Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_overflow_2_u { mmr_t sh_ni1_error_overflow_2_regval; struct { @@ -15109,75 +8183,12 @@ mmr_t reserved_1 : 1; } sh_ni1_error_overflow_2_s; } sh_ni1_error_overflow_2_u_t; -#else -typedef union sh_ni1_error_overflow_2_u { - mmr_t sh_ni1_error_overflow_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni1_error_overflow_2_s; -} sh_ni1_error_overflow_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_MASK_1" */ /* ni1 Error Mask Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_mask_1_u { mmr_t sh_ni1_error_mask_1_regval; struct { @@ -15247,84 +8258,12 @@ mmr_t tail_timeout_ni_vc3 : 1; } sh_ni1_error_mask_1_s; } sh_ni1_error_mask_1_u_t; -#else -typedef union sh_ni1_error_mask_1_u { - mmr_t sh_ni1_error_mask_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni1_error_mask_1_s; -} sh_ni1_error_mask_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_MASK_2" */ /* ni1 Error Mask Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_mask_2_u { mmr_t sh_ni1_error_mask_2_regval; struct { @@ -15385,75 +8324,12 @@ mmr_t reserved_1 : 1; } sh_ni1_error_mask_2_s; } sh_ni1_error_mask_2_u_t; -#else -typedef union sh_ni1_error_mask_2_u { - mmr_t sh_ni1_error_mask_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni1_error_mask_2_s; -} sh_ni1_error_mask_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_FIRST_ERROR_1" */ /* ni1 First Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_first_error_1_u { mmr_t sh_ni1_first_error_1_regval; struct { @@ -15523,84 +8399,12 @@ mmr_t tail_timeout_ni_vc3 : 1; } sh_ni1_first_error_1_s; } sh_ni1_first_error_1_u_t; -#else -typedef union sh_ni1_first_error_1_u { - mmr_t sh_ni1_first_error_1_regval; - struct { - mmr_t tail_timeout_ni_vc3 : 1; - mmr_t tail_timeout_ni_vc2 : 1; - mmr_t tail_timeout_ni_vc1 : 1; - mmr_t tail_timeout_ni_vc0 : 1; - mmr_t tail_timeout_fifo13_vc3 : 1; - mmr_t tail_timeout_fifo13_vc1 : 1; - mmr_t tail_timeout_fifo02_vc2 : 1; - mmr_t tail_timeout_fifo02_vc0 : 1; - mmr_t overflow_ni_fifo_vc3_credit : 1; - mmr_t overflow_ni_fifo_vc2_credit : 1; - mmr_t overflow_ni_fifo_vc1_credit : 1; - mmr_t overflow_ni_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_credit : 1; - mmr_t overflow_md_fifo_vc0_credit : 1; - mmr_t overflow_iilb_fifo_vc2_credit : 1; - mmr_t overflow_iilb_fifo_vc0_credit : 1; - mmr_t overflow_pi_fifo_vc2_credit : 1; - mmr_t overflow_pi_fifo_vc0_credit : 1; - mmr_t overflow_md_fifo_vc2_push : 1; - mmr_t overflow_md_fifo_vc0_push : 1; - mmr_t overflow_iilb_fifo_vc2_push : 1; - mmr_t overflow_iilb_fifo_vc0_push : 1; - mmr_t overflow_pi_fifo_vc2_push : 1; - mmr_t overflow_pi_fifo_vc0_push : 1; - mmr_t overflow_ni_fifo_vc2_pop : 1; - mmr_t overflow_ni_fifo_vc0_pop : 1; - mmr_t overflow_md_fifo_vc2_pop : 1; - mmr_t overflow_md_fifo_vc0_pop : 1; - mmr_t overflow_iilb_fifo_vc2_pop : 1; - mmr_t overflow_iilb_fifo_vc0_pop : 1; - mmr_t overflow_pi_fifo_vc2_pop : 1; - mmr_t overflow_pi_fifo_vc0_pop : 1; - mmr_t overflow_ni_fifo_debit3 : 1; - mmr_t overflow_ni_fifo_debit2 : 1; - mmr_t overflow_ni_fifo_debit1 : 1; - mmr_t overflow_ni_fifo_debit0 : 1; - mmr_t overflow_md_fifo_debit2 : 1; - mmr_t overflow_md_fifo_debit0 : 1; - mmr_t overflow_iilb_fifo_debit2 : 1; - mmr_t overflow_iilb_fifo_debit0 : 1; - mmr_t overflow_pi_fifo_debit2 : 1; - mmr_t overflow_pi_fifo_debit0 : 1; - mmr_t overflow2_vc2_credit : 1; - mmr_t overflow1_vc2_credit : 1; - mmr_t overflow0_vc2_credit : 1; - mmr_t overflow2_vc0_credit : 1; - mmr_t overflow1_vc0_credit : 1; - mmr_t overflow0_vc0_credit : 1; - mmr_t overflow_fifo13_vc2_credit : 1; - mmr_t overflow_fifo13_vc0_credit : 1; - mmr_t overflow_fifo02_vc2_credit : 1; - mmr_t overflow_fifo02_vc0_credit : 1; - mmr_t overflow_fifo13_vc3_push : 1; - mmr_t overflow_fifo13_vc1_push : 1; - mmr_t overflow_fifo02_vc2_push : 1; - mmr_t overflow_fifo02_vc0_push : 1; - mmr_t overflow_fifo13_vc3_pop : 1; - mmr_t overflow_fifo13_vc1_pop : 1; - mmr_t overflow_fifo02_vc2_pop : 1; - mmr_t overflow_fifo02_vc0_pop : 1; - mmr_t overflow_fifo13_debit2 : 1; - mmr_t overflow_fifo13_debit0 : 1; - mmr_t overflow_fifo02_debit2 : 1; - mmr_t overflow_fifo02_debit0 : 1; - } sh_ni1_first_error_1_s; -} sh_ni1_first_error_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_FIRST_ERROR_2" */ /* ni1 First Error Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_first_error_2_u { mmr_t sh_ni1_first_error_2_regval; struct { @@ -15661,117 +8465,36 @@ mmr_t reserved_1 : 1; } sh_ni1_first_error_2_s; } sh_ni1_first_error_2_u_t; -#else -typedef union sh_ni1_first_error_2_u { - mmr_t sh_ni1_first_error_2_regval; - struct { - mmr_t reserved_1 : 1; - mmr_t retry_timeout_error : 1; - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t llp_deadlock_vc3 : 1; - mmr_t llp_deadlock_vc2 : 1; - mmr_t llp_deadlock_vc1 : 1; - mmr_t llp_deadlock_vc0 : 1; - mmr_t underflow_ni_fifo_vc3_credit : 1; - mmr_t underflow_ni_fifo_vc2_credit : 1; - mmr_t underflow_ni_fifo_vc1_credit : 1; - mmr_t underflow_ni_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_credit : 1; - mmr_t underflow_md_fifo_vc0_credit : 1; - mmr_t underflow_iilb_fifo_vc2_credit : 1; - mmr_t underflow_iilb_fifo_vc0_credit : 1; - mmr_t underflow_pi_fifo_vc2_credit : 1; - mmr_t underflow_pi_fifo_vc0_credit : 1; - mmr_t underflow_md_fifo_vc2_push : 1; - mmr_t underflow_md_fifo_vc0_push : 1; - mmr_t underflow_iilb_fifo_vc2_push : 1; - mmr_t underflow_iilb_fifo_vc0_push : 1; - mmr_t underflow_pi_fifo_vc2_push : 1; - mmr_t underflow_pi_fifo_vc0_push : 1; - mmr_t underflow_ni_fifo_vc2_pop : 1; - mmr_t underflow_ni_fifo_vc0_pop : 1; - mmr_t underflow_md_fifo_vc2_pop : 1; - mmr_t underflow_md_fifo_vc0_pop : 1; - mmr_t underflow_iilb_fifo_vc2_pop : 1; - mmr_t underflow_iilb_fifo_vc0_pop : 1; - mmr_t underflow_pi_fifo_vc2_pop : 1; - mmr_t underflow_pi_fifo_vc0_pop : 1; - mmr_t reserved_0 : 10; - mmr_t underflow2_vc2_credit : 1; - mmr_t underflow1_vc2_credit : 1; - mmr_t underflow0_vc2_credit : 1; - mmr_t underflow2_vc0_credit : 1; - mmr_t underflow1_vc0_credit : 1; - mmr_t underflow0_vc0_credit : 1; - mmr_t underflow_fifo13_vc2_credit : 1; - mmr_t underflow_fifo13_vc0_credit : 1; - mmr_t underflow_fifo02_vc2_credit : 1; - mmr_t underflow_fifo02_vc0_credit : 1; - mmr_t underflow_fifo13_vc3_push : 1; - mmr_t underflow_fifo13_vc1_push : 1; - mmr_t underflow_fifo02_vc2_push : 1; - mmr_t underflow_fifo02_vc0_push : 1; - mmr_t underflow_fifo13_vc3_pop : 1; - mmr_t underflow_fifo13_vc1_pop : 1; - mmr_t underflow_fifo02_vc2_pop : 1; - mmr_t underflow_fifo02_vc0_pop : 1; - mmr_t illegal_vciilb : 1; - mmr_t illegal_vcmd : 1; - mmr_t illegal_vcpi : 1; - mmr_t illegal_vcni : 1; - } sh_ni1_first_error_2_s; -} sh_ni1_first_error_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_DETAIL_1" */ /* ni1 Chiplet no match header bits 63:0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_detail_1_u { mmr_t sh_ni1_error_detail_1_regval; struct { mmr_t header : 64; } sh_ni1_error_detail_1_s; } sh_ni1_error_detail_1_u_t; -#else -typedef union sh_ni1_error_detail_1_u { - mmr_t sh_ni1_error_detail_1_regval; - struct { - mmr_t header : 64; - } sh_ni1_error_detail_1_s; -} sh_ni1_error_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_DETAIL_2" */ /* ni1 Chiplet no match header bits 127:64 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ni1_error_detail_2_u { - mmr_t sh_ni1_error_detail_2_regval; - struct { - mmr_t header : 64; - } sh_ni1_error_detail_2_s; -} sh_ni1_error_detail_2_u_t; -#else typedef union sh_ni1_error_detail_2_u { mmr_t sh_ni1_error_detail_2_regval; struct { mmr_t header : 64; } sh_ni1_error_detail_2_s; } sh_ni1_error_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_CORRECTED_DETAIL_1" */ /* Corrected error details */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_corrected_detail_1_u { mmr_t sh_xn_corrected_detail_1_regval; struct { @@ -15793,78 +8516,36 @@ mmr_t reserved_3 : 4; } sh_xn_corrected_detail_1_s; } sh_xn_corrected_detail_1_u_t; -#else -typedef union sh_xn_corrected_detail_1_u { - mmr_t sh_xn_corrected_detail_1_regval; - struct { - mmr_t reserved_3 : 4; - mmr_t ecc3_vc : 2; - mmr_t ecc3_wc : 2; - mmr_t ecc3_syndrome : 8; - mmr_t reserved_2 : 4; - mmr_t ecc2_vc : 2; - mmr_t ecc2_wc : 2; - mmr_t ecc2_syndrome : 8; - mmr_t reserved_1 : 4; - mmr_t ecc1_vc : 2; - mmr_t ecc1_wc : 2; - mmr_t ecc1_syndrome : 8; - mmr_t reserved_0 : 4; - mmr_t ecc0_vc : 2; - mmr_t ecc0_wc : 2; - mmr_t ecc0_syndrome : 8; - } sh_xn_corrected_detail_1_s; -} sh_xn_corrected_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_CORRECTED_DETAIL_2" */ /* Corrected error data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_corrected_detail_2_u { - mmr_t sh_xn_corrected_detail_2_regval; - struct { - mmr_t data : 64; - } sh_xn_corrected_detail_2_s; -} sh_xn_corrected_detail_2_u_t; -#else typedef union sh_xn_corrected_detail_2_u { mmr_t sh_xn_corrected_detail_2_regval; struct { mmr_t data : 64; } sh_xn_corrected_detail_2_s; } sh_xn_corrected_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_CORRECTED_DETAIL_3" */ /* Corrected error header0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_corrected_detail_3_u { mmr_t sh_xn_corrected_detail_3_regval; struct { mmr_t header0 : 64; } sh_xn_corrected_detail_3_s; } sh_xn_corrected_detail_3_u_t; -#else -typedef union sh_xn_corrected_detail_3_u { - mmr_t sh_xn_corrected_detail_3_regval; - struct { - mmr_t header0 : 64; - } sh_xn_corrected_detail_3_s; -} sh_xn_corrected_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_CORRECTED_DETAIL_4" */ /* Corrected error header1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_corrected_detail_4_u { mmr_t sh_xn_corrected_detail_4_regval; struct { @@ -15873,23 +8554,12 @@ mmr_t err_group : 2; } sh_xn_corrected_detail_4_s; } sh_xn_corrected_detail_4_u_t; -#else -typedef union sh_xn_corrected_detail_4_u { - mmr_t sh_xn_corrected_detail_4_regval; - struct { - mmr_t err_group : 2; - mmr_t reserved_0 : 20; - mmr_t header1 : 42; - } sh_xn_corrected_detail_4_s; -} sh_xn_corrected_detail_4_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_UNCORRECTED_DETAIL_1" */ /* Uncorrected error details */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_uncorrected_detail_1_u { mmr_t sh_xn_uncorrected_detail_1_regval; struct { @@ -15911,78 +8581,36 @@ mmr_t reserved_3 : 4; } sh_xn_uncorrected_detail_1_s; } sh_xn_uncorrected_detail_1_u_t; -#else -typedef union sh_xn_uncorrected_detail_1_u { - mmr_t sh_xn_uncorrected_detail_1_regval; - struct { - mmr_t reserved_3 : 4; - mmr_t ecc3_vc : 2; - mmr_t ecc3_wc : 2; - mmr_t ecc3_syndrome : 8; - mmr_t reserved_2 : 4; - mmr_t ecc2_vc : 2; - mmr_t ecc2_wc : 2; - mmr_t ecc2_syndrome : 8; - mmr_t reserved_1 : 4; - mmr_t ecc1_vc : 2; - mmr_t ecc1_wc : 2; - mmr_t ecc1_syndrome : 8; - mmr_t reserved_0 : 4; - mmr_t ecc0_vc : 2; - mmr_t ecc0_wc : 2; - mmr_t ecc0_syndrome : 8; - } sh_xn_uncorrected_detail_1_s; -} sh_xn_uncorrected_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_UNCORRECTED_DETAIL_2" */ /* Uncorrected error data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xn_uncorrected_detail_2_u { - mmr_t sh_xn_uncorrected_detail_2_regval; - struct { - mmr_t data : 64; - } sh_xn_uncorrected_detail_2_s; -} sh_xn_uncorrected_detail_2_u_t; -#else typedef union sh_xn_uncorrected_detail_2_u { mmr_t sh_xn_uncorrected_detail_2_regval; struct { mmr_t data : 64; } sh_xn_uncorrected_detail_2_s; } sh_xn_uncorrected_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_UNCORRECTED_DETAIL_3" */ /* Uncorrected error header0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_uncorrected_detail_3_u { mmr_t sh_xn_uncorrected_detail_3_regval; struct { mmr_t header0 : 64; } sh_xn_uncorrected_detail_3_s; } sh_xn_uncorrected_detail_3_u_t; -#else -typedef union sh_xn_uncorrected_detail_3_u { - mmr_t sh_xn_uncorrected_detail_3_regval; - struct { - mmr_t header0 : 64; - } sh_xn_uncorrected_detail_3_s; -} sh_xn_uncorrected_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_UNCORRECTED_DETAIL_4" */ /* Uncorrected error header1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_uncorrected_detail_4_u { mmr_t sh_xn_uncorrected_detail_4_regval; struct { @@ -15991,23 +8619,12 @@ mmr_t err_group : 2; } sh_xn_uncorrected_detail_4_s; } sh_xn_uncorrected_detail_4_u_t; -#else -typedef union sh_xn_uncorrected_detail_4_u { - mmr_t sh_xn_uncorrected_detail_4_regval; - struct { - mmr_t err_group : 2; - mmr_t reserved_0 : 20; - mmr_t header1 : 42; - } sh_xn_uncorrected_detail_4_s; -} sh_xn_uncorrected_detail_4_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ERROR_DETAIL_1" */ /* Look Up Table Address (md) */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_error_detail_1_u { mmr_t sh_xnmd_error_detail_1_regval; struct { @@ -16015,22 +8632,12 @@ mmr_t reserved_0 : 53; } sh_xnmd_error_detail_1_s; } sh_xnmd_error_detail_1_u_t; -#else -typedef union sh_xnmd_error_detail_1_u { - mmr_t sh_xnmd_error_detail_1_regval; - struct { - mmr_t reserved_0 : 53; - mmr_t lut_addr : 11; - } sh_xnmd_error_detail_1_s; -} sh_xnmd_error_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ERROR_DETAIL_1" */ /* Look Up Table Address (pi) */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_error_detail_1_u { mmr_t sh_xnpi_error_detail_1_regval; struct { @@ -16038,64 +8645,36 @@ mmr_t reserved_0 : 53; } sh_xnpi_error_detail_1_s; } sh_xnpi_error_detail_1_u_t; -#else -typedef union sh_xnpi_error_detail_1_u { - mmr_t sh_xnpi_error_detail_1_regval; - struct { - mmr_t reserved_0 : 53; - mmr_t lut_addr : 11; - } sh_xnpi_error_detail_1_s; -} sh_xnpi_error_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_ERROR_DETAIL_1" */ /* Chiplet NoMatch header [63:0] */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xniilb_error_detail_1_u { - mmr_t sh_xniilb_error_detail_1_regval; - struct { - mmr_t header : 64; - } sh_xniilb_error_detail_1_s; -} sh_xniilb_error_detail_1_u_t; -#else typedef union sh_xniilb_error_detail_1_u { mmr_t sh_xniilb_error_detail_1_regval; struct { mmr_t header : 64; } sh_xniilb_error_detail_1_s; } sh_xniilb_error_detail_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_ERROR_DETAIL_2" */ /* Chiplet NoMatch header [127:64] */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_xniilb_error_detail_2_u { - mmr_t sh_xniilb_error_detail_2_regval; - struct { - mmr_t header : 64; - } sh_xniilb_error_detail_2_s; -} sh_xniilb_error_detail_2_u_t; -#else typedef union sh_xniilb_error_detail_2_u { mmr_t sh_xniilb_error_detail_2_regval; struct { mmr_t header : 64; } sh_xniilb_error_detail_2_s; } sh_xniilb_error_detail_2_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_ERROR_DETAIL_3" */ /* Look Up Table Address (iilb) */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_error_detail_3_u { mmr_t sh_xniilb_error_detail_3_regval; struct { @@ -16103,22 +8682,12 @@ mmr_t reserved_0 : 53; } sh_xniilb_error_detail_3_s; } sh_xniilb_error_detail_3_u_t; -#else -typedef union sh_xniilb_error_detail_3_u { - mmr_t sh_xniilb_error_detail_3_regval; - struct { - mmr_t reserved_0 : 53; - mmr_t lut_addr : 11; - } sh_xniilb_error_detail_3_s; -} sh_xniilb_error_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI0_ERROR_DETAIL_3" */ /* Look Up Table Address (ni0) */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni0_error_detail_3_u { mmr_t sh_ni0_error_detail_3_regval; struct { @@ -16126,22 +8695,12 @@ mmr_t reserved_0 : 53; } sh_ni0_error_detail_3_s; } sh_ni0_error_detail_3_u_t; -#else -typedef union sh_ni0_error_detail_3_u { - mmr_t sh_ni0_error_detail_3_regval; - struct { - mmr_t reserved_0 : 53; - mmr_t lut_addr : 11; - } sh_ni0_error_detail_3_s; -} sh_ni0_error_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_NI1_ERROR_DETAIL_3" */ /* Look Up Table Address (ni1) */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ni1_error_detail_3_u { mmr_t sh_ni1_error_detail_3_regval; struct { @@ -16149,21 +8708,11 @@ mmr_t reserved_0 : 53; } sh_ni1_error_detail_3_s; } sh_ni1_error_detail_3_u_t; -#else -typedef union sh_ni1_error_detail_3_u { - mmr_t sh_ni1_error_detail_3_regval; - struct { - mmr_t reserved_0 : 53; - mmr_t lut_addr : 11; - } sh_ni1_error_detail_3_s; -} sh_ni1_error_detail_3_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_ERROR_SUMMARY" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_error_summary_u { mmr_t sh_xn_error_summary_regval; struct { @@ -16208,58 +8757,11 @@ mmr_t reserved_0 : 26; } sh_xn_error_summary_s; } sh_xn_error_summary_u_t; -#else -typedef union sh_xn_error_summary_u { - mmr_t sh_xn_error_summary_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t iilb_chiplet_or_lut : 1; - mmr_t iilb_fifo_underflow : 1; - mmr_t iilb_credit_underflow : 1; - mmr_t iilb_fifo_overflow : 1; - mmr_t iilb_credit_overflow : 1; - mmr_t iilb_debit_overflow : 1; - mmr_t xnpi_lut_error : 1; - mmr_t xnpi_uce_error : 1; - mmr_t xnpi_sbe_error : 1; - mmr_t xnpi_credit_underflow : 1; - mmr_t xnpi_data_buff_overflow : 1; - mmr_t xnpi_debit_overflow : 1; - mmr_t xnpi_credit_overflow : 1; - mmr_t xnmd_lut_error : 1; - mmr_t xnmd_uce_error : 1; - mmr_t xnmd_sbe_error : 1; - mmr_t xnmd_credit_underflow : 1; - mmr_t xnmd_data_buff_overflow : 1; - mmr_t xnmd_debit_overflow : 1; - mmr_t xnmd_credit_overflow : 1; - mmr_t ni1_pipe_error : 1; - mmr_t ni1_llp_error : 1; - mmr_t ni1_credit_underflow : 1; - mmr_t ni1_push_underflow : 1; - mmr_t ni1_pop_underflow : 1; - mmr_t ni1_debit_overflow : 1; - mmr_t ni1_credit_overflow : 1; - mmr_t ni1_push_overflow : 1; - mmr_t ni1_pop_overflow : 1; - mmr_t ni0_pipe_error : 1; - mmr_t ni0_llp_error : 1; - mmr_t ni0_credit_underflow : 1; - mmr_t ni0_push_underflow : 1; - mmr_t ni0_pop_underflow : 1; - mmr_t ni0_debit_overflow : 1; - mmr_t ni0_credit_overflow : 1; - mmr_t ni0_push_overflow : 1; - mmr_t ni0_pop_overflow : 1; - } sh_xn_error_summary_s; -} sh_xn_error_summary_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_ERROR_OVERFLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_error_overflow_u { mmr_t sh_xn_error_overflow_regval; struct { @@ -16304,58 +8806,11 @@ mmr_t reserved_0 : 26; } sh_xn_error_overflow_s; } sh_xn_error_overflow_u_t; -#else -typedef union sh_xn_error_overflow_u { - mmr_t sh_xn_error_overflow_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t iilb_chiplet_or_lut : 1; - mmr_t iilb_fifo_underflow : 1; - mmr_t iilb_credit_underflow : 1; - mmr_t iilb_fifo_overflow : 1; - mmr_t iilb_credit_overflow : 1; - mmr_t iilb_debit_overflow : 1; - mmr_t xnpi_lut_error : 1; - mmr_t xnpi_uce_error : 1; - mmr_t xnpi_sbe_error : 1; - mmr_t xnpi_credit_underflow : 1; - mmr_t xnpi_data_buff_overflow : 1; - mmr_t xnpi_debit_overflow : 1; - mmr_t xnpi_credit_overflow : 1; - mmr_t xnmd_lut_error : 1; - mmr_t xnmd_uce_error : 1; - mmr_t xnmd_sbe_error : 1; - mmr_t xnmd_credit_underflow : 1; - mmr_t xnmd_data_buff_overflow : 1; - mmr_t xnmd_debit_overflow : 1; - mmr_t xnmd_credit_overflow : 1; - mmr_t ni1_pipe_error : 1; - mmr_t ni1_llp_error : 1; - mmr_t ni1_credit_underflow : 1; - mmr_t ni1_push_underflow : 1; - mmr_t ni1_pop_underflow : 1; - mmr_t ni1_debit_overflow : 1; - mmr_t ni1_credit_overflow : 1; - mmr_t ni1_push_overflow : 1; - mmr_t ni1_pop_overflow : 1; - mmr_t ni0_pipe_error : 1; - mmr_t ni0_llp_error : 1; - mmr_t ni0_credit_underflow : 1; - mmr_t ni0_push_underflow : 1; - mmr_t ni0_pop_underflow : 1; - mmr_t ni0_debit_overflow : 1; - mmr_t ni0_credit_overflow : 1; - mmr_t ni0_push_overflow : 1; - mmr_t ni0_pop_overflow : 1; - } sh_xn_error_overflow_s; -} sh_xn_error_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_ERROR_MASK" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_error_mask_u { mmr_t sh_xn_error_mask_regval; struct { @@ -16400,58 +8855,11 @@ mmr_t reserved_0 : 26; } sh_xn_error_mask_s; } sh_xn_error_mask_u_t; -#else -typedef union sh_xn_error_mask_u { - mmr_t sh_xn_error_mask_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t iilb_chiplet_or_lut : 1; - mmr_t iilb_fifo_underflow : 1; - mmr_t iilb_credit_underflow : 1; - mmr_t iilb_fifo_overflow : 1; - mmr_t iilb_credit_overflow : 1; - mmr_t iilb_debit_overflow : 1; - mmr_t xnpi_lut_error : 1; - mmr_t xnpi_uce_error : 1; - mmr_t xnpi_sbe_error : 1; - mmr_t xnpi_credit_underflow : 1; - mmr_t xnpi_data_buff_overflow : 1; - mmr_t xnpi_debit_overflow : 1; - mmr_t xnpi_credit_overflow : 1; - mmr_t xnmd_lut_error : 1; - mmr_t xnmd_uce_error : 1; - mmr_t xnmd_sbe_error : 1; - mmr_t xnmd_credit_underflow : 1; - mmr_t xnmd_data_buff_overflow : 1; - mmr_t xnmd_debit_overflow : 1; - mmr_t xnmd_credit_overflow : 1; - mmr_t ni1_pipe_error : 1; - mmr_t ni1_llp_error : 1; - mmr_t ni1_credit_underflow : 1; - mmr_t ni1_push_underflow : 1; - mmr_t ni1_pop_underflow : 1; - mmr_t ni1_debit_overflow : 1; - mmr_t ni1_credit_overflow : 1; - mmr_t ni1_push_overflow : 1; - mmr_t ni1_pop_overflow : 1; - mmr_t ni0_pipe_error : 1; - mmr_t ni0_llp_error : 1; - mmr_t ni0_credit_underflow : 1; - mmr_t ni0_push_underflow : 1; - mmr_t ni0_pop_underflow : 1; - mmr_t ni0_debit_overflow : 1; - mmr_t ni0_credit_overflow : 1; - mmr_t ni0_push_overflow : 1; - mmr_t ni0_pop_overflow : 1; - } sh_xn_error_mask_s; -} sh_xn_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_FIRST_ERROR" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_first_error_u { mmr_t sh_xn_first_error_regval; struct { @@ -16496,58 +8904,11 @@ mmr_t reserved_0 : 26; } sh_xn_first_error_s; } sh_xn_first_error_u_t; -#else -typedef union sh_xn_first_error_u { - mmr_t sh_xn_first_error_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t iilb_chiplet_or_lut : 1; - mmr_t iilb_fifo_underflow : 1; - mmr_t iilb_credit_underflow : 1; - mmr_t iilb_fifo_overflow : 1; - mmr_t iilb_credit_overflow : 1; - mmr_t iilb_debit_overflow : 1; - mmr_t xnpi_lut_error : 1; - mmr_t xnpi_uce_error : 1; - mmr_t xnpi_sbe_error : 1; - mmr_t xnpi_credit_underflow : 1; - mmr_t xnpi_data_buff_overflow : 1; - mmr_t xnpi_debit_overflow : 1; - mmr_t xnpi_credit_overflow : 1; - mmr_t xnmd_lut_error : 1; - mmr_t xnmd_uce_error : 1; - mmr_t xnmd_sbe_error : 1; - mmr_t xnmd_credit_underflow : 1; - mmr_t xnmd_data_buff_overflow : 1; - mmr_t xnmd_debit_overflow : 1; - mmr_t xnmd_credit_overflow : 1; - mmr_t ni1_pipe_error : 1; - mmr_t ni1_llp_error : 1; - mmr_t ni1_credit_underflow : 1; - mmr_t ni1_push_underflow : 1; - mmr_t ni1_pop_underflow : 1; - mmr_t ni1_debit_overflow : 1; - mmr_t ni1_credit_overflow : 1; - mmr_t ni1_push_overflow : 1; - mmr_t ni1_pop_overflow : 1; - mmr_t ni0_pipe_error : 1; - mmr_t ni0_llp_error : 1; - mmr_t ni0_credit_underflow : 1; - mmr_t ni0_push_underflow : 1; - mmr_t ni0_pop_underflow : 1; - mmr_t ni0_debit_overflow : 1; - mmr_t ni0_credit_overflow : 1; - mmr_t ni0_push_overflow : 1; - mmr_t ni0_pop_overflow : 1; - } sh_xn_first_error_s; -} sh_xn_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_ERROR_SUMMARY" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_error_summary_u { mmr_t sh_xniilb_error_summary_regval; struct { @@ -16617,83 +8978,11 @@ mmr_t lut_read_error : 1; } sh_xniilb_error_summary_s; } sh_xniilb_error_summary_u_t; -#else -typedef union sh_xniilb_error_summary_u { - mmr_t sh_xniilb_error_summary_regval; - struct { - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t underflow_ni1_vc2_credit_out : 1; - mmr_t underflow_ni1_vc0_credit_out : 1; - mmr_t underflow_ni0_vc2_credit_out : 1; - mmr_t underflow_ni0_vc0_credit_out : 1; - mmr_t underflow_iilb_vc2_credit_out : 1; - mmr_t underflow_iilb_vc0_credit_out : 1; - mmr_t underflow_md_vc2_credit_out : 1; - mmr_t underflow_md_vc0_credit_out : 1; - mmr_t underflow_pi_vc2_credit_out : 1; - mmr_t underflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_vc2_credit_out : 1; - mmr_t overflow_ni1_vc0_credit_out : 1; - mmr_t overflow_ni0_vc2_credit_out : 1; - mmr_t overflow_ni0_vc0_credit_out : 1; - mmr_t overflow_iilb_vc2_credit_out : 1; - mmr_t overflow_iilb_vc0_credit_out : 1; - mmr_t overflow_md_vc2_credit_out : 1; - mmr_t overflow_md_vc0_credit_out : 1; - mmr_t overflow_pi_vc2_credit_out : 1; - mmr_t overflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_md_debit2 : 1; - mmr_t overflow_md_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_pi_debit2 : 1; - mmr_t overflow_pi_debit0 : 1; - mmr_t underflow_ni1_vc2_credit_in : 1; - mmr_t underflow_ni0_vc2_credit_in : 1; - mmr_t underflow_md_vc2_credit_in : 1; - mmr_t underflow_iilb_vc2_credit_in : 1; - mmr_t underflow_pi_vc2_credit_in : 1; - mmr_t underflow_ni1_vc0_credit_in : 1; - mmr_t underflow_ni0_vc0_credit_in : 1; - mmr_t underflow_md_vc0_credit_in : 1; - mmr_t underflow_iilb_vc0_credit_in : 1; - mmr_t underflow_pi_vc0_credit_in : 1; - mmr_t overflow_ni1_vc2_credit_in : 1; - mmr_t overflow_ni0_vc2_credit_in : 1; - mmr_t overflow_md_vc2_credit_in : 1; - mmr_t overflow_iilb_vc2_credit_in : 1; - mmr_t overflow_pi_vc2_credit_in : 1; - mmr_t overflow_ni1_vc0_credit_in : 1; - mmr_t overflow_ni0_vc0_credit_in : 1; - mmr_t overflow_md_vc0_credit_in : 1; - mmr_t overflow_iilb_vc0_credit_in : 1; - mmr_t overflow_pi_vc0_credit_in : 1; - mmr_t underflow_lb_vc2 : 1; - mmr_t underflow_lb_vc0 : 1; - mmr_t overflow_lb_vc2 : 1; - mmr_t overflow_lb_vc0 : 1; - mmr_t underflow_ii_vc2 : 1; - mmr_t underflow_ii_vc0 : 1; - mmr_t overflow_ii_vc2 : 1; - mmr_t overflow_ii_vc0 : 1; - mmr_t overflow_lb_debit2 : 1; - mmr_t overflow_lb_debit0 : 1; - mmr_t overflow_ii_debit2 : 1; - mmr_t overflow_ii_debit0 : 1; - } sh_xniilb_error_summary_s; -} sh_xniilb_error_summary_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_ERROR_OVERFLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_error_overflow_u { mmr_t sh_xniilb_error_overflow_regval; struct { @@ -16763,83 +9052,11 @@ mmr_t lut_read_error : 1; } sh_xniilb_error_overflow_s; } sh_xniilb_error_overflow_u_t; -#else -typedef union sh_xniilb_error_overflow_u { - mmr_t sh_xniilb_error_overflow_regval; - struct { - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t underflow_ni1_vc2_credit_out : 1; - mmr_t underflow_ni1_vc0_credit_out : 1; - mmr_t underflow_ni0_vc2_credit_out : 1; - mmr_t underflow_ni0_vc0_credit_out : 1; - mmr_t underflow_iilb_vc2_credit_out : 1; - mmr_t underflow_iilb_vc0_credit_out : 1; - mmr_t underflow_md_vc2_credit_out : 1; - mmr_t underflow_md_vc0_credit_out : 1; - mmr_t underflow_pi_vc2_credit_out : 1; - mmr_t underflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_vc2_credit_out : 1; - mmr_t overflow_ni1_vc0_credit_out : 1; - mmr_t overflow_ni0_vc2_credit_out : 1; - mmr_t overflow_ni0_vc0_credit_out : 1; - mmr_t overflow_iilb_vc2_credit_out : 1; - mmr_t overflow_iilb_vc0_credit_out : 1; - mmr_t overflow_md_vc2_credit_out : 1; - mmr_t overflow_md_vc0_credit_out : 1; - mmr_t overflow_pi_vc2_credit_out : 1; - mmr_t overflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_md_debit2 : 1; - mmr_t overflow_md_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_pi_debit2 : 1; - mmr_t overflow_pi_debit0 : 1; - mmr_t underflow_ni1_vc2_credit_in : 1; - mmr_t underflow_ni0_vc2_credit_in : 1; - mmr_t underflow_md_vc2_credit_in : 1; - mmr_t underflow_iilb_vc2_credit_in : 1; - mmr_t underflow_pi_vc2_credit_in : 1; - mmr_t underflow_ni1_vc0_credit_in : 1; - mmr_t underflow_ni0_vc0_credit_in : 1; - mmr_t underflow_md_vc0_credit_in : 1; - mmr_t underflow_iilb_vc0_credit_in : 1; - mmr_t underflow_pi_vc0_credit_in : 1; - mmr_t overflow_ni1_vc2_credit_in : 1; - mmr_t overflow_ni0_vc2_credit_in : 1; - mmr_t overflow_md_vc2_credit_in : 1; - mmr_t overflow_iilb_vc2_credit_in : 1; - mmr_t overflow_pi_vc2_credit_in : 1; - mmr_t overflow_ni1_vc0_credit_in : 1; - mmr_t overflow_ni0_vc0_credit_in : 1; - mmr_t overflow_md_vc0_credit_in : 1; - mmr_t overflow_iilb_vc0_credit_in : 1; - mmr_t overflow_pi_vc0_credit_in : 1; - mmr_t underflow_lb_vc2 : 1; - mmr_t underflow_lb_vc0 : 1; - mmr_t overflow_lb_vc2 : 1; - mmr_t overflow_lb_vc0 : 1; - mmr_t underflow_ii_vc2 : 1; - mmr_t underflow_ii_vc0 : 1; - mmr_t overflow_ii_vc2 : 1; - mmr_t overflow_ii_vc0 : 1; - mmr_t overflow_lb_debit2 : 1; - mmr_t overflow_lb_debit0 : 1; - mmr_t overflow_ii_debit2 : 1; - mmr_t overflow_ii_debit0 : 1; - } sh_xniilb_error_overflow_s; -} sh_xniilb_error_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_ERROR_MASK" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_error_mask_u { mmr_t sh_xniilb_error_mask_regval; struct { @@ -16909,83 +9126,11 @@ mmr_t lut_read_error : 1; } sh_xniilb_error_mask_s; } sh_xniilb_error_mask_u_t; -#else -typedef union sh_xniilb_error_mask_u { - mmr_t sh_xniilb_error_mask_regval; - struct { - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t underflow_ni1_vc2_credit_out : 1; - mmr_t underflow_ni1_vc0_credit_out : 1; - mmr_t underflow_ni0_vc2_credit_out : 1; - mmr_t underflow_ni0_vc0_credit_out : 1; - mmr_t underflow_iilb_vc2_credit_out : 1; - mmr_t underflow_iilb_vc0_credit_out : 1; - mmr_t underflow_md_vc2_credit_out : 1; - mmr_t underflow_md_vc0_credit_out : 1; - mmr_t underflow_pi_vc2_credit_out : 1; - mmr_t underflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_vc2_credit_out : 1; - mmr_t overflow_ni1_vc0_credit_out : 1; - mmr_t overflow_ni0_vc2_credit_out : 1; - mmr_t overflow_ni0_vc0_credit_out : 1; - mmr_t overflow_iilb_vc2_credit_out : 1; - mmr_t overflow_iilb_vc0_credit_out : 1; - mmr_t overflow_md_vc2_credit_out : 1; - mmr_t overflow_md_vc0_credit_out : 1; - mmr_t overflow_pi_vc2_credit_out : 1; - mmr_t overflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_md_debit2 : 1; - mmr_t overflow_md_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_pi_debit2 : 1; - mmr_t overflow_pi_debit0 : 1; - mmr_t underflow_ni1_vc2_credit_in : 1; - mmr_t underflow_ni0_vc2_credit_in : 1; - mmr_t underflow_md_vc2_credit_in : 1; - mmr_t underflow_iilb_vc2_credit_in : 1; - mmr_t underflow_pi_vc2_credit_in : 1; - mmr_t underflow_ni1_vc0_credit_in : 1; - mmr_t underflow_ni0_vc0_credit_in : 1; - mmr_t underflow_md_vc0_credit_in : 1; - mmr_t underflow_iilb_vc0_credit_in : 1; - mmr_t underflow_pi_vc0_credit_in : 1; - mmr_t overflow_ni1_vc2_credit_in : 1; - mmr_t overflow_ni0_vc2_credit_in : 1; - mmr_t overflow_md_vc2_credit_in : 1; - mmr_t overflow_iilb_vc2_credit_in : 1; - mmr_t overflow_pi_vc2_credit_in : 1; - mmr_t overflow_ni1_vc0_credit_in : 1; - mmr_t overflow_ni0_vc0_credit_in : 1; - mmr_t overflow_md_vc0_credit_in : 1; - mmr_t overflow_iilb_vc0_credit_in : 1; - mmr_t overflow_pi_vc0_credit_in : 1; - mmr_t underflow_lb_vc2 : 1; - mmr_t underflow_lb_vc0 : 1; - mmr_t overflow_lb_vc2 : 1; - mmr_t overflow_lb_vc0 : 1; - mmr_t underflow_ii_vc2 : 1; - mmr_t underflow_ii_vc0 : 1; - mmr_t overflow_ii_vc2 : 1; - mmr_t overflow_ii_vc0 : 1; - mmr_t overflow_lb_debit2 : 1; - mmr_t overflow_lb_debit0 : 1; - mmr_t overflow_ii_debit2 : 1; - mmr_t overflow_ii_debit0 : 1; - } sh_xniilb_error_mask_s; -} sh_xniilb_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNIILB_FIRST_ERROR" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xniilb_first_error_u { mmr_t sh_xniilb_first_error_regval; struct { @@ -17055,83 +9200,11 @@ mmr_t lut_read_error : 1; } sh_xniilb_first_error_s; } sh_xniilb_first_error_u_t; -#else -typedef union sh_xniilb_first_error_u { - mmr_t sh_xniilb_first_error_regval; - struct { - mmr_t lut_read_error : 1; - mmr_t chiplet_nomatch : 1; - mmr_t underflow_ni1_vc2_credit_out : 1; - mmr_t underflow_ni1_vc0_credit_out : 1; - mmr_t underflow_ni0_vc2_credit_out : 1; - mmr_t underflow_ni0_vc0_credit_out : 1; - mmr_t underflow_iilb_vc2_credit_out : 1; - mmr_t underflow_iilb_vc0_credit_out : 1; - mmr_t underflow_md_vc2_credit_out : 1; - mmr_t underflow_md_vc0_credit_out : 1; - mmr_t underflow_pi_vc2_credit_out : 1; - mmr_t underflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_vc2_credit_out : 1; - mmr_t overflow_ni1_vc0_credit_out : 1; - mmr_t overflow_ni0_vc2_credit_out : 1; - mmr_t overflow_ni0_vc0_credit_out : 1; - mmr_t overflow_iilb_vc2_credit_out : 1; - mmr_t overflow_iilb_vc0_credit_out : 1; - mmr_t overflow_md_vc2_credit_out : 1; - mmr_t overflow_md_vc0_credit_out : 1; - mmr_t overflow_pi_vc2_credit_out : 1; - mmr_t overflow_pi_vc0_credit_out : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_md_debit2 : 1; - mmr_t overflow_md_debit0 : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_pi_debit2 : 1; - mmr_t overflow_pi_debit0 : 1; - mmr_t underflow_ni1_vc2_credit_in : 1; - mmr_t underflow_ni0_vc2_credit_in : 1; - mmr_t underflow_md_vc2_credit_in : 1; - mmr_t underflow_iilb_vc2_credit_in : 1; - mmr_t underflow_pi_vc2_credit_in : 1; - mmr_t underflow_ni1_vc0_credit_in : 1; - mmr_t underflow_ni0_vc0_credit_in : 1; - mmr_t underflow_md_vc0_credit_in : 1; - mmr_t underflow_iilb_vc0_credit_in : 1; - mmr_t underflow_pi_vc0_credit_in : 1; - mmr_t overflow_ni1_vc2_credit_in : 1; - mmr_t overflow_ni0_vc2_credit_in : 1; - mmr_t overflow_md_vc2_credit_in : 1; - mmr_t overflow_iilb_vc2_credit_in : 1; - mmr_t overflow_pi_vc2_credit_in : 1; - mmr_t overflow_ni1_vc0_credit_in : 1; - mmr_t overflow_ni0_vc0_credit_in : 1; - mmr_t overflow_md_vc0_credit_in : 1; - mmr_t overflow_iilb_vc0_credit_in : 1; - mmr_t overflow_pi_vc0_credit_in : 1; - mmr_t underflow_lb_vc2 : 1; - mmr_t underflow_lb_vc0 : 1; - mmr_t overflow_lb_vc2 : 1; - mmr_t overflow_lb_vc0 : 1; - mmr_t underflow_ii_vc2 : 1; - mmr_t underflow_ii_vc0 : 1; - mmr_t overflow_ii_vc2 : 1; - mmr_t overflow_ii_vc0 : 1; - mmr_t overflow_lb_debit2 : 1; - mmr_t overflow_lb_debit0 : 1; - mmr_t overflow_ii_debit2 : 1; - mmr_t overflow_ii_debit0 : 1; - } sh_xniilb_first_error_s; -} sh_xniilb_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ERROR_SUMMARY" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_error_summary_u { mmr_t sh_xnpi_error_summary_regval; struct { @@ -17188,70 +9261,11 @@ mmr_t reserved_0 : 14; } sh_xnpi_error_summary_s; } sh_xnpi_error_summary_u_t; -#else -typedef union sh_xnpi_error_summary_u { - mmr_t sh_xnpi_error_summary_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnpi_error_summary_s; -} sh_xnpi_error_summary_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ERROR_OVERFLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_error_overflow_u { mmr_t sh_xnpi_error_overflow_regval; struct { @@ -17308,70 +9322,11 @@ mmr_t reserved_0 : 14; } sh_xnpi_error_overflow_s; } sh_xnpi_error_overflow_u_t; -#else -typedef union sh_xnpi_error_overflow_u { - mmr_t sh_xnpi_error_overflow_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnpi_error_overflow_s; -} sh_xnpi_error_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_ERROR_MASK" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_error_mask_u { mmr_t sh_xnpi_error_mask_regval; struct { @@ -17428,70 +9383,11 @@ mmr_t reserved_0 : 14; } sh_xnpi_error_mask_s; } sh_xnpi_error_mask_u_t; -#else -typedef union sh_xnpi_error_mask_u { - mmr_t sh_xnpi_error_mask_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnpi_error_mask_s; -} sh_xnpi_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNPI_FIRST_ERROR" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnpi_first_error_u { mmr_t sh_xnpi_first_error_regval; struct { @@ -17548,70 +9444,11 @@ mmr_t reserved_0 : 14; } sh_xnpi_first_error_s; } sh_xnpi_first_error_u_t; -#else -typedef union sh_xnpi_first_error_u { - mmr_t sh_xnpi_first_error_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnpi_first_error_s; -} sh_xnpi_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ERROR_SUMMARY" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_error_summary_u { mmr_t sh_xnmd_error_summary_regval; struct { @@ -17668,70 +9505,11 @@ mmr_t reserved_0 : 14; } sh_xnmd_error_summary_s; } sh_xnmd_error_summary_u_t; -#else -typedef union sh_xnmd_error_summary_u { - mmr_t sh_xnmd_error_summary_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnmd_error_summary_s; -} sh_xnmd_error_summary_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ERROR_OVERFLOW" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_error_overflow_u { mmr_t sh_xnmd_error_overflow_regval; struct { @@ -17788,70 +9566,11 @@ mmr_t reserved_0 : 14; } sh_xnmd_error_overflow_s; } sh_xnmd_error_overflow_u_t; -#else -typedef union sh_xnmd_error_overflow_u { - mmr_t sh_xnmd_error_overflow_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnmd_error_overflow_s; -} sh_xnmd_error_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_ERROR_MASK" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_error_mask_u { mmr_t sh_xnmd_error_mask_regval; struct { @@ -17908,70 +9627,11 @@ mmr_t reserved_0 : 14; } sh_xnmd_error_mask_s; } sh_xnmd_error_mask_u_t; -#else -typedef union sh_xnmd_error_mask_u { - mmr_t sh_xnmd_error_mask_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnmd_error_mask_s; -} sh_xnmd_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_XNMD_FIRST_ERROR" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xnmd_first_error_u { mmr_t sh_xnmd_first_error_regval; struct { @@ -18028,155 +9688,60 @@ mmr_t reserved_0 : 14; } sh_xnmd_first_error_s; } sh_xnmd_first_error_u_t; -#else -typedef union sh_xnmd_first_error_u { - mmr_t sh_xnmd_first_error_regval; - struct { - mmr_t reserved_0 : 14; - mmr_t overflow_header_cancel_fifo : 1; - mmr_t overflow_iilb_vc2_credit : 1; - mmr_t underflow_iilb_vc2_credit : 1; - mmr_t overflow_iilb_vc0_credit : 1; - mmr_t underflow_iilb_vc0_credit : 1; - mmr_t overflow_ni1_vc2_credit : 1; - mmr_t underflow_ni1_vc2_credit : 1; - mmr_t overflow_ni1_vc0_credit : 1; - mmr_t underflow_ni1_vc0_credit : 1; - mmr_t overflow_ni0_vc2_credit : 1; - mmr_t underflow_ni0_vc2_credit : 1; - mmr_t overflow_ni0_vc0_credit : 1; - mmr_t underflow_ni0_vc0_credit : 1; - mmr_t overflow_iilb_debit2 : 1; - mmr_t overflow_iilb_debit0 : 1; - mmr_t overflow_ni1_debit2 : 1; - mmr_t overflow_ni1_debit0 : 1; - mmr_t overflow_ni0_debit2 : 1; - mmr_t overflow_ni0_debit0 : 1; - mmr_t overflow_sic_cntr2 : 1; - mmr_t underflow_sic_cntr2 : 1; - mmr_t overflow_sic_cntr0 : 1; - mmr_t underflow_sic_cntr0 : 1; - mmr_t uncor_error3 : 1; - mmr_t uncor_error2 : 1; - mmr_t uncor_error1 : 1; - mmr_t uncor_error0 : 1; - mmr_t single_bit_error3 : 1; - mmr_t single_bit_error2 : 1; - mmr_t single_bit_error1 : 1; - mmr_t single_bit_error0 : 1; - mmr_t lut_read_error : 1; - mmr_t overflow_databuff_vc2 : 1; - mmr_t overflow_databuff_vc0 : 1; - mmr_t overflow_vc2_credit : 1; - mmr_t underflow_vc2_credit : 1; - mmr_t overflow_vc0_credit : 1; - mmr_t underflow_vc0_credit : 1; - mmr_t overflow_iilb_vc2 : 1; - mmr_t underflow_iilb_vc2 : 1; - mmr_t overflow_iilb_vc0 : 1; - mmr_t underflow_iilb_vc0 : 1; - mmr_t overflow_ni1_vc2 : 1; - mmr_t underflow_ni1_vc2 : 1; - mmr_t overflow_ni1_vc0 : 1; - mmr_t underflow_ni1_vc0 : 1; - mmr_t overflow_ni0_vc2 : 1; - mmr_t underflow_ni0_vc2 : 1; - mmr_t overflow_ni0_vc0 : 1; - mmr_t underflow_ni0_vc0 : 1; - } sh_xnmd_first_error_s; -} sh_xnmd_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_AUTO_REPLY_ENABLE0" */ /* Automatic Maintenance Reply Enable 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_auto_reply_enable0_u { - mmr_t sh_auto_reply_enable0_regval; - struct { - mmr_t enable0 : 64; - } sh_auto_reply_enable0_s; -} sh_auto_reply_enable0_u_t; -#else typedef union sh_auto_reply_enable0_u { mmr_t sh_auto_reply_enable0_regval; struct { mmr_t enable0 : 64; } sh_auto_reply_enable0_s; } sh_auto_reply_enable0_u_t; -#endif /* ==================================================================== */ /* Register "SH_AUTO_REPLY_ENABLE1" */ /* Automatic Maintenance Reply Enable 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_auto_reply_enable1_u { - mmr_t sh_auto_reply_enable1_regval; - struct { - mmr_t enable1 : 64; - } sh_auto_reply_enable1_s; -} sh_auto_reply_enable1_u_t; -#else typedef union sh_auto_reply_enable1_u { mmr_t sh_auto_reply_enable1_regval; struct { mmr_t enable1 : 64; } sh_auto_reply_enable1_s; } sh_auto_reply_enable1_u_t; -#endif /* ==================================================================== */ /* Register "SH_AUTO_REPLY_HEADER0" */ /* Automatic Maintenance Reply Header 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_auto_reply_header0_u { - mmr_t sh_auto_reply_header0_regval; - struct { - mmr_t header0 : 64; - } sh_auto_reply_header0_s; -} sh_auto_reply_header0_u_t; -#else typedef union sh_auto_reply_header0_u { mmr_t sh_auto_reply_header0_regval; struct { mmr_t header0 : 64; } sh_auto_reply_header0_s; } sh_auto_reply_header0_u_t; -#endif /* ==================================================================== */ /* Register "SH_AUTO_REPLY_HEADER1" */ /* Automatic Maintenance Reply Header 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_auto_reply_header1_u { - mmr_t sh_auto_reply_header1_regval; - struct { - mmr_t header1 : 64; - } sh_auto_reply_header1_s; -} sh_auto_reply_header1_u_t; -#else typedef union sh_auto_reply_header1_u { mmr_t sh_auto_reply_header1_regval; struct { mmr_t header1 : 64; } sh_auto_reply_header1_s; } sh_auto_reply_header1_u_t; -#endif /* ==================================================================== */ /* Register "SH_ENABLE_RP_AUTO_REPLY" */ /* Enable Automatic Maintenance Reply From Reply Queue */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_enable_rp_auto_reply_u { mmr_t sh_enable_rp_auto_reply_regval; struct { @@ -18184,22 +9749,12 @@ mmr_t reserved_0 : 63; } sh_enable_rp_auto_reply_s; } sh_enable_rp_auto_reply_u_t; -#else -typedef union sh_enable_rp_auto_reply_u { - mmr_t sh_enable_rp_auto_reply_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t enable : 1; - } sh_enable_rp_auto_reply_s; -} sh_enable_rp_auto_reply_u_t; -#endif /* ==================================================================== */ /* Register "SH_ENABLE_RQ_AUTO_REPLY" */ /* Enable Automatic Maintenance Reply From Request Queue */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_enable_rq_auto_reply_u { mmr_t sh_enable_rq_auto_reply_regval; struct { @@ -18207,22 +9762,12 @@ mmr_t reserved_0 : 63; } sh_enable_rq_auto_reply_s; } sh_enable_rq_auto_reply_u_t; -#else -typedef union sh_enable_rq_auto_reply_u { - mmr_t sh_enable_rq_auto_reply_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t enable : 1; - } sh_enable_rq_auto_reply_s; -} sh_enable_rq_auto_reply_u_t; -#endif /* ==================================================================== */ /* Register "SH_REDIRECT_INVAL" */ /* Redirect invalidate to LB instead of PI */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_redirect_inval_u { mmr_t sh_redirect_inval_regval; struct { @@ -18230,22 +9775,12 @@ mmr_t reserved_0 : 63; } sh_redirect_inval_s; } sh_redirect_inval_u_t; -#else -typedef union sh_redirect_inval_u { - mmr_t sh_redirect_inval_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t redirect : 1; - } sh_redirect_inval_s; -} sh_redirect_inval_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_CNTRL" */ /* Diagnostic Message Control Register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_diag_msg_cntrl_u { mmr_t sh_diag_msg_cntrl_regval; struct { @@ -18258,447 +9793,252 @@ mmr_t busy : 1; } sh_diag_msg_cntrl_s; } sh_diag_msg_cntrl_u_t; -#else -typedef union sh_diag_msg_cntrl_u { - mmr_t sh_diag_msg_cntrl_regval; - struct { - mmr_t busy : 1; - mmr_t start : 1; - mmr_t reserved_0 : 48; - mmr_t port : 1; - mmr_t error_inject_enable : 1; - mmr_t error_inject_point : 6; - mmr_t msg_length : 6; - } sh_diag_msg_cntrl_s; -} sh_diag_msg_cntrl_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA0L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data0l_u { - mmr_t sh_diag_msg_data0l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data0l_s; -} sh_diag_msg_data0l_u_t; -#else typedef union sh_diag_msg_data0l_u { mmr_t sh_diag_msg_data0l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data0l_s; } sh_diag_msg_data0l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA0U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data0u_u { - mmr_t sh_diag_msg_data0u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data0u_s; -} sh_diag_msg_data0u_u_t; -#else typedef union sh_diag_msg_data0u_u { mmr_t sh_diag_msg_data0u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data0u_s; } sh_diag_msg_data0u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA1L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_diag_msg_data1l_u { mmr_t sh_diag_msg_data1l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data1l_s; } sh_diag_msg_data1l_u_t; -#else -typedef union sh_diag_msg_data1l_u { - mmr_t sh_diag_msg_data1l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data1l_s; -} sh_diag_msg_data1l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA1U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data1u_u { - mmr_t sh_diag_msg_data1u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data1u_s; -} sh_diag_msg_data1u_u_t; -#else typedef union sh_diag_msg_data1u_u { mmr_t sh_diag_msg_data1u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data1u_s; } sh_diag_msg_data1u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA2L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data2l_u { - mmr_t sh_diag_msg_data2l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data2l_s; -} sh_diag_msg_data2l_u_t; -#else typedef union sh_diag_msg_data2l_u { mmr_t sh_diag_msg_data2l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data2l_s; } sh_diag_msg_data2l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA2U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data2u_u { - mmr_t sh_diag_msg_data2u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data2u_s; -} sh_diag_msg_data2u_u_t; -#else typedef union sh_diag_msg_data2u_u { mmr_t sh_diag_msg_data2u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data2u_s; } sh_diag_msg_data2u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA3L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data3l_u { - mmr_t sh_diag_msg_data3l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data3l_s; -} sh_diag_msg_data3l_u_t; -#else typedef union sh_diag_msg_data3l_u { mmr_t sh_diag_msg_data3l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data3l_s; } sh_diag_msg_data3l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA3U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data3u_u { - mmr_t sh_diag_msg_data3u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data3u_s; -} sh_diag_msg_data3u_u_t; -#else typedef union sh_diag_msg_data3u_u { mmr_t sh_diag_msg_data3u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data3u_s; } sh_diag_msg_data3u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA4L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data4l_u { - mmr_t sh_diag_msg_data4l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data4l_s; -} sh_diag_msg_data4l_u_t; -#else typedef union sh_diag_msg_data4l_u { mmr_t sh_diag_msg_data4l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data4l_s; } sh_diag_msg_data4l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA4U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_diag_msg_data4u_u { mmr_t sh_diag_msg_data4u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data4u_s; } sh_diag_msg_data4u_u_t; -#else -typedef union sh_diag_msg_data4u_u { - mmr_t sh_diag_msg_data4u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data4u_s; -} sh_diag_msg_data4u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA5L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data5l_u { - mmr_t sh_diag_msg_data5l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data5l_s; -} sh_diag_msg_data5l_u_t; -#else typedef union sh_diag_msg_data5l_u { mmr_t sh_diag_msg_data5l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data5l_s; } sh_diag_msg_data5l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA5U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data5u_u { - mmr_t sh_diag_msg_data5u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data5u_s; -} sh_diag_msg_data5u_u_t; -#else typedef union sh_diag_msg_data5u_u { mmr_t sh_diag_msg_data5u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data5u_s; } sh_diag_msg_data5u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA6L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_diag_msg_data6l_u { mmr_t sh_diag_msg_data6l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data6l_s; } sh_diag_msg_data6l_u_t; -#else -typedef union sh_diag_msg_data6l_u { - mmr_t sh_diag_msg_data6l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data6l_s; -} sh_diag_msg_data6l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA6U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data6u_u { - mmr_t sh_diag_msg_data6u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data6u_s; -} sh_diag_msg_data6u_u_t; -#else typedef union sh_diag_msg_data6u_u { mmr_t sh_diag_msg_data6u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data6u_s; } sh_diag_msg_data6u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA7L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_diag_msg_data7l_u { mmr_t sh_diag_msg_data7l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data7l_s; } sh_diag_msg_data7l_u_t; -#else -typedef union sh_diag_msg_data7l_u { - mmr_t sh_diag_msg_data7l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data7l_s; -} sh_diag_msg_data7l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA7U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data7u_u { - mmr_t sh_diag_msg_data7u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data7u_s; -} sh_diag_msg_data7u_u_t; -#else typedef union sh_diag_msg_data7u_u { mmr_t sh_diag_msg_data7u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data7u_s; } sh_diag_msg_data7u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA8L" */ /* Diagnostic Data, lower 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_diag_msg_data8l_u { mmr_t sh_diag_msg_data8l_regval; struct { mmr_t data_lower : 64; } sh_diag_msg_data8l_s; } sh_diag_msg_data8l_u_t; -#else -typedef union sh_diag_msg_data8l_u { - mmr_t sh_diag_msg_data8l_regval; - struct { - mmr_t data_lower : 64; - } sh_diag_msg_data8l_s; -} sh_diag_msg_data8l_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_DATA8U" */ /* Diagnostice Data, upper 64 bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_data8u_u { - mmr_t sh_diag_msg_data8u_regval; - struct { - mmr_t data_upper : 64; - } sh_diag_msg_data8u_s; -} sh_diag_msg_data8u_u_t; -#else typedef union sh_diag_msg_data8u_u { mmr_t sh_diag_msg_data8u_regval; struct { mmr_t data_upper : 64; } sh_diag_msg_data8u_s; } sh_diag_msg_data8u_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_HDR0" */ /* Diagnostice Data, lower 64 bits of header */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_hdr0_u { - mmr_t sh_diag_msg_hdr0_regval; - struct { - mmr_t header0 : 64; - } sh_diag_msg_hdr0_s; -} sh_diag_msg_hdr0_u_t; -#else typedef union sh_diag_msg_hdr0_u { mmr_t sh_diag_msg_hdr0_regval; struct { mmr_t header0 : 64; } sh_diag_msg_hdr0_s; } sh_diag_msg_hdr0_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIAG_MSG_HDR1" */ /* Diagnostice Data, upper 64 bits of header */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_diag_msg_hdr1_u { - mmr_t sh_diag_msg_hdr1_regval; - struct { - mmr_t header1 : 64; - } sh_diag_msg_hdr1_s; -} sh_diag_msg_hdr1_u_t; -#else typedef union sh_diag_msg_hdr1_u { mmr_t sh_diag_msg_hdr1_regval; struct { mmr_t header1 : 64; } sh_diag_msg_hdr1_s; } sh_diag_msg_hdr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_DEBUG_SELECT" */ /* SHub Debug Port Select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_debug_select_u { mmr_t sh_debug_select_regval; struct { @@ -18724,40 +10064,12 @@ mmr_t trigger_enable : 1; } sh_debug_select_s; } sh_debug_select_u_t; -#else -typedef union sh_debug_select_u { - mmr_t sh_debug_select_regval; - struct { - mmr_t trigger_enable : 1; - mmr_t reserved_0 : 3; - mmr_t sel_ii : 9; - mmr_t debug_ii_sel : 3; - mmr_t nibble7_chiplet_sel : 3; - mmr_t nibble7_nibble_sel : 3; - mmr_t nibble6_chiplet_sel : 3; - mmr_t nibble6_nibble_sel : 3; - mmr_t nibble5_chiplet_sel : 3; - mmr_t nibble5_nibble_sel : 3; - mmr_t nibble4_chiplet_sel : 3; - mmr_t nibble4_nibble_sel : 3; - mmr_t nibble3_chiplet_sel : 3; - mmr_t nibble3_nibble_sel : 3; - mmr_t nibble2_chiplet_sel : 3; - mmr_t nibble2_nibble_sel : 3; - mmr_t nibble1_chiplet_sel : 3; - mmr_t nibble1_nibble_sel : 3; - mmr_t nibble0_chiplet_sel : 3; - mmr_t nibble0_nibble_sel : 3; - } sh_debug_select_s; -} sh_debug_select_u_t; -#endif /* ==================================================================== */ /* Register "SH_TRIGGER_COMPARE_MASK" */ /* SHub Trigger Compare Mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_trigger_compare_mask_u { mmr_t sh_trigger_compare_mask_regval; struct { @@ -18765,22 +10077,12 @@ mmr_t reserved_0 : 32; } sh_trigger_compare_mask_s; } sh_trigger_compare_mask_u_t; -#else -typedef union sh_trigger_compare_mask_u { - mmr_t sh_trigger_compare_mask_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t mask : 32; - } sh_trigger_compare_mask_s; -} sh_trigger_compare_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_TRIGGER_COMPARE_PATTERN" */ /* SHub Trigger Compare Pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_trigger_compare_pattern_u { mmr_t sh_trigger_compare_pattern_regval; struct { @@ -18788,22 +10090,12 @@ mmr_t reserved_0 : 32; } sh_trigger_compare_pattern_s; } sh_trigger_compare_pattern_u_t; -#else -typedef union sh_trigger_compare_pattern_u { - mmr_t sh_trigger_compare_pattern_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t data : 32; - } sh_trigger_compare_pattern_s; -} sh_trigger_compare_pattern_u_t; -#endif /* ==================================================================== */ /* Register "SH_TRIGGER_SEL" */ /* Trigger select for SHUB debug port */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_trigger_sel_u { mmr_t sh_trigger_sel_regval; struct { @@ -18841,52 +10133,12 @@ mmr_t reserved_15 : 1; } sh_trigger_sel_s; } sh_trigger_sel_u_t; -#else -typedef union sh_trigger_sel_u { - mmr_t sh_trigger_sel_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble_sel : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_input_sel : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble_sel : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_input_sel : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble_sel : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_input_sel : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble_sel : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_input_sel : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_input_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_input_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_input_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_input_sel : 3; - } sh_trigger_sel_s; -} sh_trigger_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_STOP_CLK_CONTROL" */ /* Stop Clock Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_stop_clk_control_u { mmr_t sh_stop_clk_control_regval; struct { @@ -18897,25 +10149,12 @@ mmr_t reserved_0 : 56; } sh_stop_clk_control_s; } sh_stop_clk_control_u_t; -#else -typedef union sh_stop_clk_control_u { - mmr_t sh_stop_clk_control_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t mode : 1; - mmr_t polarity : 1; - mmr_t event : 1; - mmr_t stimulus : 5; - } sh_stop_clk_control_s; -} sh_stop_clk_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_STOP_CLK_DELAY_PHASE" */ /* Stop Clock Delay Phase */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_stop_clk_delay_phase_u { mmr_t sh_stop_clk_delay_phase_regval; struct { @@ -18923,43 +10162,24 @@ mmr_t reserved_0 : 56; } sh_stop_clk_delay_phase_s; } sh_stop_clk_delay_phase_u_t; -#else -typedef union sh_stop_clk_delay_phase_u { - mmr_t sh_stop_clk_delay_phase_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t delay : 8; - } sh_stop_clk_delay_phase_s; -} sh_stop_clk_delay_phase_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_ARM_MASK" */ /* Trigger sequencing facility arm mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_arm_mask_u { mmr_t sh_tsf_arm_mask_regval; struct { mmr_t mask : 64; } sh_tsf_arm_mask_s; } sh_tsf_arm_mask_u_t; -#else -typedef union sh_tsf_arm_mask_u { - mmr_t sh_tsf_arm_mask_regval; - struct { - mmr_t mask : 64; - } sh_tsf_arm_mask_s; -} sh_tsf_arm_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_COUNTER_PRESETS" */ /* Trigger sequencing facility counter presets */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_counter_presets_u { mmr_t sh_tsf_counter_presets_regval; struct { @@ -18969,24 +10189,12 @@ mmr_t count_8a : 8; } sh_tsf_counter_presets_s; } sh_tsf_counter_presets_u_t; -#else -typedef union sh_tsf_counter_presets_u { - mmr_t sh_tsf_counter_presets_regval; - struct { - mmr_t count_8a : 8; - mmr_t count_8b : 8; - mmr_t count_16 : 16; - mmr_t count_32 : 32; - } sh_tsf_counter_presets_s; -} sh_tsf_counter_presets_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_DECREMENT_CTL" */ /* Trigger sequencing facility counter decrement control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_decrement_ctl_u { mmr_t sh_tsf_decrement_ctl_regval; struct { @@ -18994,22 +10202,12 @@ mmr_t reserved_0 : 48; } sh_tsf_decrement_ctl_s; } sh_tsf_decrement_ctl_u_t; -#else -typedef union sh_tsf_decrement_ctl_u { - mmr_t sh_tsf_decrement_ctl_regval; - struct { - mmr_t reserved_0 : 48; - mmr_t ctl : 16; - } sh_tsf_decrement_ctl_s; -} sh_tsf_decrement_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_DIAG_MSG_CTL" */ /* Trigger sequencing facility diagnostic message control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_diag_msg_ctl_u { mmr_t sh_tsf_diag_msg_ctl_regval; struct { @@ -19017,43 +10215,24 @@ mmr_t reserved_0 : 56; } sh_tsf_diag_msg_ctl_s; } sh_tsf_diag_msg_ctl_u_t; -#else -typedef union sh_tsf_diag_msg_ctl_u { - mmr_t sh_tsf_diag_msg_ctl_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t enable : 8; - } sh_tsf_diag_msg_ctl_s; -} sh_tsf_diag_msg_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_DISARM_MASK" */ /* Trigger sequencing facility disarm mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_disarm_mask_u { mmr_t sh_tsf_disarm_mask_regval; struct { mmr_t mask : 64; } sh_tsf_disarm_mask_s; } sh_tsf_disarm_mask_u_t; -#else -typedef union sh_tsf_disarm_mask_u { - mmr_t sh_tsf_disarm_mask_regval; - struct { - mmr_t mask : 64; - } sh_tsf_disarm_mask_s; -} sh_tsf_disarm_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_ENABLE_CTL" */ /* Trigger sequencing facility counter enable control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_enable_ctl_u { mmr_t sh_tsf_enable_ctl_regval; struct { @@ -19061,22 +10240,12 @@ mmr_t reserved_0 : 48; } sh_tsf_enable_ctl_s; } sh_tsf_enable_ctl_u_t; -#else -typedef union sh_tsf_enable_ctl_u { - mmr_t sh_tsf_enable_ctl_regval; - struct { - mmr_t reserved_0 : 48; - mmr_t ctl : 16; - } sh_tsf_enable_ctl_s; -} sh_tsf_enable_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_SOFTWARE_ARM" */ /* Trigger sequencing facility software arm */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_software_arm_u { mmr_t sh_tsf_software_arm_regval; struct { @@ -19091,29 +10260,12 @@ mmr_t reserved_0 : 56; } sh_tsf_software_arm_s; } sh_tsf_software_arm_u_t; -#else -typedef union sh_tsf_software_arm_u { - mmr_t sh_tsf_software_arm_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t bit7 : 1; - mmr_t bit6 : 1; - mmr_t bit5 : 1; - mmr_t bit4 : 1; - mmr_t bit3 : 1; - mmr_t bit2 : 1; - mmr_t bit1 : 1; - mmr_t bit0 : 1; - } sh_tsf_software_arm_s; -} sh_tsf_software_arm_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_SOFTWARE_DISARM" */ /* Trigger sequencing facility software disarm */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_software_disarm_u { mmr_t sh_tsf_software_disarm_regval; struct { @@ -19128,29 +10280,12 @@ mmr_t reserved_0 : 56; } sh_tsf_software_disarm_s; } sh_tsf_software_disarm_u_t; -#else -typedef union sh_tsf_software_disarm_u { - mmr_t sh_tsf_software_disarm_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t bit7 : 1; - mmr_t bit6 : 1; - mmr_t bit5 : 1; - mmr_t bit4 : 1; - mmr_t bit3 : 1; - mmr_t bit2 : 1; - mmr_t bit1 : 1; - mmr_t bit0 : 1; - } sh_tsf_software_disarm_s; -} sh_tsf_software_disarm_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_SOFTWARE_TRIGGERED" */ /* Trigger sequencing facility software triggered */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_software_triggered_u { mmr_t sh_tsf_software_triggered_regval; struct { @@ -19165,71 +10300,36 @@ mmr_t reserved_0 : 56; } sh_tsf_software_triggered_s; } sh_tsf_software_triggered_u_t; -#else -typedef union sh_tsf_software_triggered_u { - mmr_t sh_tsf_software_triggered_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t bit7 : 1; - mmr_t bit6 : 1; - mmr_t bit5 : 1; - mmr_t bit4 : 1; - mmr_t bit3 : 1; - mmr_t bit2 : 1; - mmr_t bit1 : 1; - mmr_t bit0 : 1; - } sh_tsf_software_triggered_s; -} sh_tsf_software_triggered_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_TRIGGER_MASK" */ /* Trigger sequencing facility trigger mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_tsf_trigger_mask_u { - mmr_t sh_tsf_trigger_mask_regval; - struct { - mmr_t mask : 64; - } sh_tsf_trigger_mask_s; -} sh_tsf_trigger_mask_u_t; -#else typedef union sh_tsf_trigger_mask_u { mmr_t sh_tsf_trigger_mask_regval; struct { mmr_t mask : 64; } sh_tsf_trigger_mask_s; } sh_tsf_trigger_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_VEC_DATA" */ /* Vector Write Request Message Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_vec_data_u { - mmr_t sh_vec_data_regval; - struct { - mmr_t data : 64; - } sh_vec_data_s; -} sh_vec_data_u_t; -#else typedef union sh_vec_data_u { mmr_t sh_vec_data_regval; struct { mmr_t data : 64; } sh_vec_data_s; } sh_vec_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_VEC_PARMS" */ /* Vector Message Parameters Register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_vec_parms_u { mmr_t sh_vec_parms_regval; struct { @@ -19243,133 +10343,72 @@ mmr_t busy : 1; } sh_vec_parms_s; } sh_vec_parms_u_t; -#else -typedef union sh_vec_parms_u { - mmr_t sh_vec_parms_regval; - struct { - mmr_t busy : 1; - mmr_t start : 1; - mmr_t reserved_1 : 16; - mmr_t pio_id : 11; - mmr_t address : 32; - mmr_t reserved_0 : 1; - mmr_t ni_port : 1; - mmr_t type : 1; - } sh_vec_parms_s; -} sh_vec_parms_u_t; -#endif /* ==================================================================== */ /* Register "SH_VEC_ROUTE" */ /* Vector Request Message Route */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_vec_route_u { - mmr_t sh_vec_route_regval; - struct { - mmr_t route : 64; - } sh_vec_route_s; -} sh_vec_route_u_t; -#else typedef union sh_vec_route_u { mmr_t sh_vec_route_regval; struct { mmr_t route : 64; } sh_vec_route_s; } sh_vec_route_u_t; -#endif /* ==================================================================== */ /* Register "SH_CPU_PERM" */ /* CPU MMR Access Permission Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_cpu_perm_u { - mmr_t sh_cpu_perm_regval; - struct { - mmr_t access_bits : 64; - } sh_cpu_perm_s; -} sh_cpu_perm_u_t; -#else typedef union sh_cpu_perm_u { mmr_t sh_cpu_perm_regval; struct { mmr_t access_bits : 64; } sh_cpu_perm_s; } sh_cpu_perm_u_t; -#endif /* ==================================================================== */ /* Register "SH_CPU_PERM_OVR" */ /* CPU MMR Access Permission Override */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_cpu_perm_ovr_u { mmr_t sh_cpu_perm_ovr_regval; struct { mmr_t override : 64; } sh_cpu_perm_ovr_s; } sh_cpu_perm_ovr_u_t; -#else -typedef union sh_cpu_perm_ovr_u { - mmr_t sh_cpu_perm_ovr_regval; - struct { - mmr_t override : 64; - } sh_cpu_perm_ovr_s; -} sh_cpu_perm_ovr_u_t; -#endif /* ==================================================================== */ /* Register "SH_EXT_IO_PERM" */ /* External IO MMR Access Permission Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ext_io_perm_u { - mmr_t sh_ext_io_perm_regval; - struct { - mmr_t access_bits : 64; - } sh_ext_io_perm_s; -} sh_ext_io_perm_u_t; -#else typedef union sh_ext_io_perm_u { mmr_t sh_ext_io_perm_regval; struct { mmr_t access_bits : 64; } sh_ext_io_perm_s; } sh_ext_io_perm_u_t; -#endif /* ==================================================================== */ /* Register "SH_EXT_IOI_ACCESS" */ /* External IO Interrupt Access Permission Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ext_ioi_access_u { - mmr_t sh_ext_ioi_access_regval; - struct { - mmr_t access_bits : 64; - } sh_ext_ioi_access_s; -} sh_ext_ioi_access_u_t; -#else typedef union sh_ext_ioi_access_u { mmr_t sh_ext_ioi_access_regval; struct { mmr_t access_bits : 64; } sh_ext_ioi_access_s; } sh_ext_ioi_access_u_t; -#endif /* ==================================================================== */ /* Register "SH_GC_FIL_CTRL" */ /* SHub Global Clock Filter Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gc_fil_ctrl_u { mmr_t sh_gc_fil_ctrl_regval; struct { @@ -19386,31 +10425,12 @@ mmr_t reserved_4 : 6; } sh_gc_fil_ctrl_s; } sh_gc_fil_ctrl_u_t; -#else -typedef union sh_gc_fil_ctrl_u { - mmr_t sh_gc_fil_ctrl_regval; - struct { - mmr_t reserved_4 : 6; - mmr_t error_counter : 10; - mmr_t reserved_3 : 2; - mmr_t dropout_thresh : 10; - mmr_t reserved_2 : 2; - mmr_t dropout_counter : 10; - mmr_t reserved_1 : 3; - mmr_t mask_enable : 1; - mmr_t mask_counter : 12; - mmr_t reserved_0 : 3; - mmr_t offset : 5; - } sh_gc_fil_ctrl_s; -} sh_gc_fil_ctrl_u_t; -#endif /* ==================================================================== */ /* Register "SH_GC_SRC_CTRL" */ /* SHub Global Clock Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_gc_src_ctrl_u { mmr_t sh_gc_src_ctrl_regval; struct { @@ -19426,30 +10446,12 @@ mmr_t reserved_4 : 30; } sh_gc_src_ctrl_s; } sh_gc_src_ctrl_u_t; -#else -typedef union sh_gc_src_ctrl_u { - mmr_t sh_gc_src_ctrl_regval; - struct { - mmr_t reserved_4 : 30; - mmr_t source_sel : 2; - mmr_t reserved_3 : 3; - mmr_t toggle_bit : 1; - mmr_t reserved_2 : 2; - mmr_t counter : 10; - mmr_t reserved_1 : 2; - mmr_t max_count : 10; - mmr_t reserved_0 : 3; - mmr_t enable_counter : 1; - } sh_gc_src_ctrl_s; -} sh_gc_src_ctrl_u_t; -#endif /* ==================================================================== */ /* Register "SH_HARD_RESET" */ /* SHub Hard Reset */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_hard_reset_u { mmr_t sh_hard_reset_regval; struct { @@ -19457,85 +10459,48 @@ mmr_t reserved_0 : 63; } sh_hard_reset_s; } sh_hard_reset_u_t; -#else -typedef union sh_hard_reset_u { - mmr_t sh_hard_reset_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t hard_reset : 1; - } sh_hard_reset_s; -} sh_hard_reset_u_t; -#endif /* ==================================================================== */ /* Register "SH_IO_PERM" */ /* II MMR Access Permission Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_io_perm_u { mmr_t sh_io_perm_regval; struct { mmr_t access_bits : 64; } sh_io_perm_s; } sh_io_perm_u_t; -#else -typedef union sh_io_perm_u { - mmr_t sh_io_perm_regval; - struct { - mmr_t access_bits : 64; - } sh_io_perm_s; -} sh_io_perm_u_t; -#endif /* ==================================================================== */ /* Register "SH_IOI_ACCESS" */ /* II Interrupt Access Permission Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_ioi_access_u { - mmr_t sh_ioi_access_regval; - struct { - mmr_t access_bits : 64; - } sh_ioi_access_s; -} sh_ioi_access_u_t; -#else typedef union sh_ioi_access_u { mmr_t sh_ioi_access_regval; struct { mmr_t access_bits : 64; } sh_ioi_access_s; } sh_ioi_access_u_t; -#endif /* ==================================================================== */ /* Register "SH_IPI_ACCESS" */ /* CPU interrupt Access Permission Bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ipi_access_u { mmr_t sh_ipi_access_regval; struct { mmr_t access_bits : 64; } sh_ipi_access_s; } sh_ipi_access_u_t; -#else -typedef union sh_ipi_access_u { - mmr_t sh_ipi_access_regval; - struct { - mmr_t access_bits : 64; - } sh_ipi_access_s; -} sh_ipi_access_u_t; -#endif /* ==================================================================== */ /* Register "SH_JTAG_CONFIG" */ /* SHub JTAG configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_jtag_config_u { mmr_t sh_jtag_config_regval; struct { @@ -19559,38 +10524,12 @@ mmr_t reserved_0 : 8; } sh_jtag_config_s; } sh_jtag_config_u_t; -#else -typedef union sh_jtag_config_u { - mmr_t sh_jtag_config_regval; - struct { - mmr_t reserved_0 : 8; - mmr_t gtl_config_re : 1; - mmr_t fsb_config_aux : 2; - mmr_t fsb_config_enable_bist : 1; - mmr_t fsb_config_output_tristate : 4; - mmr_t fsb_config_clock_ratio : 5; - mmr_t fsb_config_enable_bus_parking : 1; - mmr_t fsb_config_sample_binit : 1; - mmr_t fsb_config_ioq_depth : 1; - mmr_t jtag_mci_override : 1; - mmr_t jtag_mci_target : 14; - mmr_t jtag_mci_reset_delay : 4; - mmr_t wrt90_override : 1; - mmr_t wrt90_overrider : 1; - mmr_t wrt90_target : 14; - mmr_t ii_clk_sel : 2; - mmr_t ni_clk_sel : 1; - mmr_t md_clk_sel : 2; - } sh_jtag_config_s; -} sh_jtag_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_SHUB_ID" */ /* SHub ID Number */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_shub_id_u { mmr_t sh_shub_id_regval; struct { @@ -19608,116 +10547,60 @@ mmr_t reserved_3 : 7; } sh_shub_id_s; } sh_shub_id_u_t; -#else -typedef union sh_shub_id_u { - mmr_t sh_shub_id_regval; - struct { - mmr_t reserved_3 : 7; - mmr_t ni_port : 1; - mmr_t reserved_2 : 3; - mmr_t nodes_per_bit : 5; - mmr_t reserved_1 : 2; - mmr_t sharing_mode : 2; - mmr_t reserved_0 : 1; - mmr_t node_id : 11; - mmr_t revision : 4; - mmr_t part_number : 16; - mmr_t manufacturer : 11; - mmr_t force1 : 1; - } sh_shub_id_s; -} sh_shub_id_u_t; -#endif /* ==================================================================== */ /* Register "SH_SHUBS_PRESENT0" */ /* Shubs 0 - 63 Present. Used for invalidate generation */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_shubs_present0_u { - mmr_t sh_shubs_present0_regval; - struct { - mmr_t shubs_present0 : 64; - } sh_shubs_present0_s; -} sh_shubs_present0_u_t; -#else typedef union sh_shubs_present0_u { mmr_t sh_shubs_present0_regval; struct { mmr_t shubs_present0 : 64; } sh_shubs_present0_s; } sh_shubs_present0_u_t; -#endif /* ==================================================================== */ /* Register "SH_SHUBS_PRESENT1" */ /* Shubs 64 - 127 Present. Used for invalidate generation */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_shubs_present1_u { mmr_t sh_shubs_present1_regval; struct { mmr_t shubs_present1 : 64; } sh_shubs_present1_s; } sh_shubs_present1_u_t; -#else -typedef union sh_shubs_present1_u { - mmr_t sh_shubs_present1_regval; - struct { - mmr_t shubs_present1 : 64; - } sh_shubs_present1_s; -} sh_shubs_present1_u_t; -#endif /* ==================================================================== */ /* Register "SH_SHUBS_PRESENT2" */ /* Shubs 128 - 191 Present. Used for invalidate generation */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_shubs_present2_u { - mmr_t sh_shubs_present2_regval; - struct { - mmr_t shubs_present2 : 64; - } sh_shubs_present2_s; -} sh_shubs_present2_u_t; -#else typedef union sh_shubs_present2_u { mmr_t sh_shubs_present2_regval; struct { mmr_t shubs_present2 : 64; } sh_shubs_present2_s; } sh_shubs_present2_u_t; -#endif /* ==================================================================== */ /* Register "SH_SHUBS_PRESENT3" */ /* Shubs 192 - 255 Present. Used for invalidate generation */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_shubs_present3_u { - mmr_t sh_shubs_present3_regval; - struct { - mmr_t shubs_present3 : 64; - } sh_shubs_present3_s; -} sh_shubs_present3_u_t; -#else typedef union sh_shubs_present3_u { mmr_t sh_shubs_present3_regval; struct { mmr_t shubs_present3 : 64; } sh_shubs_present3_s; } sh_shubs_present3_u_t; -#endif /* ==================================================================== */ /* Register "SH_SOFT_RESET" */ /* SHub Soft Reset */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_soft_reset_u { mmr_t sh_soft_reset_regval; struct { @@ -19725,22 +10608,12 @@ mmr_t reserved_0 : 63; } sh_soft_reset_s; } sh_soft_reset_u_t; -#else -typedef union sh_soft_reset_u { - mmr_t sh_soft_reset_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t soft_reset : 1; - } sh_soft_reset_s; -} sh_soft_reset_u_t; -#endif /* ==================================================================== */ /* Register "SH_FIRST_ERROR" */ /* Shub Global First Error Flags */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_first_error_u { mmr_t sh_first_error_regval; struct { @@ -19748,22 +10621,12 @@ mmr_t reserved_0 : 45; } sh_first_error_s; } sh_first_error_u_t; -#else -typedef union sh_first_error_u { - mmr_t sh_first_error_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t first_error : 19; - } sh_first_error_s; -} sh_first_error_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_HW_TIME_STAMP" */ /* II hardware error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_hw_time_stamp_u { mmr_t sh_ii_hw_time_stamp_regval; struct { @@ -19771,22 +10634,12 @@ mmr_t valid : 1; } sh_ii_hw_time_stamp_s; } sh_ii_hw_time_stamp_u_t; -#else -typedef union sh_ii_hw_time_stamp_u { - mmr_t sh_ii_hw_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_ii_hw_time_stamp_s; -} sh_ii_hw_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_HW_TIME_STAMP" */ /* LB hardware error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_hw_time_stamp_u { mmr_t sh_lb_hw_time_stamp_regval; struct { @@ -19794,22 +10647,12 @@ mmr_t valid : 1; } sh_lb_hw_time_stamp_s; } sh_lb_hw_time_stamp_u_t; -#else -typedef union sh_lb_hw_time_stamp_u { - mmr_t sh_lb_hw_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_lb_hw_time_stamp_s; -} sh_lb_hw_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_COR_TIME_STAMP" */ /* MD correctable error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_cor_time_stamp_u { mmr_t sh_md_cor_time_stamp_regval; struct { @@ -19817,22 +10660,12 @@ mmr_t valid : 1; } sh_md_cor_time_stamp_s; } sh_md_cor_time_stamp_u_t; -#else -typedef union sh_md_cor_time_stamp_u { - mmr_t sh_md_cor_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_md_cor_time_stamp_s; -} sh_md_cor_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_HW_TIME_STAMP" */ /* MD hardware error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_hw_time_stamp_u { mmr_t sh_md_hw_time_stamp_regval; struct { @@ -19840,22 +10673,12 @@ mmr_t valid : 1; } sh_md_hw_time_stamp_s; } sh_md_hw_time_stamp_u_t; -#else -typedef union sh_md_hw_time_stamp_u { - mmr_t sh_md_hw_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_md_hw_time_stamp_s; -} sh_md_hw_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_UNCOR_TIME_STAMP" */ /* MD uncorrectable error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_uncor_time_stamp_u { mmr_t sh_md_uncor_time_stamp_regval; struct { @@ -19863,22 +10686,12 @@ mmr_t valid : 1; } sh_md_uncor_time_stamp_s; } sh_md_uncor_time_stamp_u_t; -#else -typedef union sh_md_uncor_time_stamp_u { - mmr_t sh_md_uncor_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_md_uncor_time_stamp_s; -} sh_md_uncor_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_COR_TIME_STAMP" */ /* PI correctable error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_cor_time_stamp_u { mmr_t sh_pi_cor_time_stamp_regval; struct { @@ -19886,22 +10699,12 @@ mmr_t valid : 1; } sh_pi_cor_time_stamp_s; } sh_pi_cor_time_stamp_u_t; -#else -typedef union sh_pi_cor_time_stamp_u { - mmr_t sh_pi_cor_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_pi_cor_time_stamp_s; -} sh_pi_cor_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_HW_TIME_STAMP" */ /* PI hardware error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_hw_time_stamp_u { mmr_t sh_pi_hw_time_stamp_regval; struct { @@ -19909,22 +10712,12 @@ mmr_t valid : 1; } sh_pi_hw_time_stamp_s; } sh_pi_hw_time_stamp_u_t; -#else -typedef union sh_pi_hw_time_stamp_u { - mmr_t sh_pi_hw_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_pi_hw_time_stamp_s; -} sh_pi_hw_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_UNCOR_TIME_STAMP" */ /* PI uncorrectable error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_uncor_time_stamp_u { mmr_t sh_pi_uncor_time_stamp_regval; struct { @@ -19932,22 +10725,12 @@ mmr_t valid : 1; } sh_pi_uncor_time_stamp_s; } sh_pi_uncor_time_stamp_u_t; -#else -typedef union sh_pi_uncor_time_stamp_u { - mmr_t sh_pi_uncor_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_pi_uncor_time_stamp_s; -} sh_pi_uncor_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC0_ADV_TIME_STAMP" */ /* Proc 0 advisory time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc0_adv_time_stamp_u { mmr_t sh_proc0_adv_time_stamp_regval; struct { @@ -19955,22 +10738,12 @@ mmr_t valid : 1; } sh_proc0_adv_time_stamp_s; } sh_proc0_adv_time_stamp_u_t; -#else -typedef union sh_proc0_adv_time_stamp_u { - mmr_t sh_proc0_adv_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc0_adv_time_stamp_s; -} sh_proc0_adv_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC0_ERR_TIME_STAMP" */ /* Proc 0 error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc0_err_time_stamp_u { mmr_t sh_proc0_err_time_stamp_regval; struct { @@ -19978,22 +10751,12 @@ mmr_t valid : 1; } sh_proc0_err_time_stamp_s; } sh_proc0_err_time_stamp_u_t; -#else -typedef union sh_proc0_err_time_stamp_u { - mmr_t sh_proc0_err_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc0_err_time_stamp_s; -} sh_proc0_err_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC1_ADV_TIME_STAMP" */ /* Proc 1 advisory time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc1_adv_time_stamp_u { mmr_t sh_proc1_adv_time_stamp_regval; struct { @@ -20001,22 +10764,12 @@ mmr_t valid : 1; } sh_proc1_adv_time_stamp_s; } sh_proc1_adv_time_stamp_u_t; -#else -typedef union sh_proc1_adv_time_stamp_u { - mmr_t sh_proc1_adv_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc1_adv_time_stamp_s; -} sh_proc1_adv_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC1_ERR_TIME_STAMP" */ /* Proc 1 error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc1_err_time_stamp_u { mmr_t sh_proc1_err_time_stamp_regval; struct { @@ -20024,22 +10777,12 @@ mmr_t valid : 1; } sh_proc1_err_time_stamp_s; } sh_proc1_err_time_stamp_u_t; -#else -typedef union sh_proc1_err_time_stamp_u { - mmr_t sh_proc1_err_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc1_err_time_stamp_s; -} sh_proc1_err_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC2_ADV_TIME_STAMP" */ /* Proc 2 advisory time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc2_adv_time_stamp_u { mmr_t sh_proc2_adv_time_stamp_regval; struct { @@ -20047,22 +10790,12 @@ mmr_t valid : 1; } sh_proc2_adv_time_stamp_s; } sh_proc2_adv_time_stamp_u_t; -#else -typedef union sh_proc2_adv_time_stamp_u { - mmr_t sh_proc2_adv_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc2_adv_time_stamp_s; -} sh_proc2_adv_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC2_ERR_TIME_STAMP" */ /* Proc 2 error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc2_err_time_stamp_u { mmr_t sh_proc2_err_time_stamp_regval; struct { @@ -20070,22 +10803,12 @@ mmr_t valid : 1; } sh_proc2_err_time_stamp_s; } sh_proc2_err_time_stamp_u_t; -#else -typedef union sh_proc2_err_time_stamp_u { - mmr_t sh_proc2_err_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc2_err_time_stamp_s; -} sh_proc2_err_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC3_ADV_TIME_STAMP" */ /* Proc 3 advisory time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc3_adv_time_stamp_u { mmr_t sh_proc3_adv_time_stamp_regval; struct { @@ -20093,22 +10816,12 @@ mmr_t valid : 1; } sh_proc3_adv_time_stamp_s; } sh_proc3_adv_time_stamp_u_t; -#else -typedef union sh_proc3_adv_time_stamp_u { - mmr_t sh_proc3_adv_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc3_adv_time_stamp_s; -} sh_proc3_adv_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROC3_ERR_TIME_STAMP" */ /* Proc 3 error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_proc3_err_time_stamp_u { mmr_t sh_proc3_err_time_stamp_regval; struct { @@ -20116,22 +10829,12 @@ mmr_t valid : 1; } sh_proc3_err_time_stamp_s; } sh_proc3_err_time_stamp_u_t; -#else -typedef union sh_proc3_err_time_stamp_u { - mmr_t sh_proc3_err_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_proc3_err_time_stamp_s; -} sh_proc3_err_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_COR_TIME_STAMP" */ /* XN correctable error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_cor_time_stamp_u { mmr_t sh_xn_cor_time_stamp_regval; struct { @@ -20139,22 +10842,12 @@ mmr_t valid : 1; } sh_xn_cor_time_stamp_s; } sh_xn_cor_time_stamp_u_t; -#else -typedef union sh_xn_cor_time_stamp_u { - mmr_t sh_xn_cor_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_xn_cor_time_stamp_s; -} sh_xn_cor_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_HW_TIME_STAMP" */ /* XN hardware error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_hw_time_stamp_u { mmr_t sh_xn_hw_time_stamp_regval; struct { @@ -20162,22 +10855,12 @@ mmr_t valid : 1; } sh_xn_hw_time_stamp_s; } sh_xn_hw_time_stamp_u_t; -#else -typedef union sh_xn_hw_time_stamp_u { - mmr_t sh_xn_hw_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_xn_hw_time_stamp_s; -} sh_xn_hw_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_UNCOR_TIME_STAMP" */ /* XN uncorrectable error time stamp */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_uncor_time_stamp_u { mmr_t sh_xn_uncor_time_stamp_regval; struct { @@ -20185,22 +10868,12 @@ mmr_t valid : 1; } sh_xn_uncor_time_stamp_s; } sh_xn_uncor_time_stamp_u_t; -#else -typedef union sh_xn_uncor_time_stamp_u { - mmr_t sh_xn_uncor_time_stamp_regval; - struct { - mmr_t valid : 1; - mmr_t time : 63; - } sh_xn_uncor_time_stamp_s; -} sh_xn_uncor_time_stamp_u_t; -#endif /* ==================================================================== */ /* Register "SH_DEBUG_PORT" */ /* SHub Debug Port */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_debug_port_u { mmr_t sh_debug_port_regval; struct { @@ -20215,29 +10888,12 @@ mmr_t reserved_0 : 32; } sh_debug_port_s; } sh_debug_port_u_t; -#else -typedef union sh_debug_port_u { - mmr_t sh_debug_port_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t debug_nibble7 : 4; - mmr_t debug_nibble6 : 4; - mmr_t debug_nibble5 : 4; - mmr_t debug_nibble4 : 4; - mmr_t debug_nibble3 : 4; - mmr_t debug_nibble2 : 4; - mmr_t debug_nibble1 : 4; - mmr_t debug_nibble0 : 4; - } sh_debug_port_s; -} sh_debug_port_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_DEBUG_DATA" */ /* II Debug Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_debug_data_u { mmr_t sh_ii_debug_data_regval; struct { @@ -20245,22 +10901,12 @@ mmr_t reserved_0 : 32; } sh_ii_debug_data_s; } sh_ii_debug_data_u_t; -#else -typedef union sh_ii_debug_data_u { - mmr_t sh_ii_debug_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t ii_data : 32; - } sh_ii_debug_data_s; -} sh_ii_debug_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_II_WRAP_DEBUG_DATA" */ /* SHub II Wrapper Debug Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ii_wrap_debug_data_u { mmr_t sh_ii_wrap_debug_data_regval; struct { @@ -20268,22 +10914,12 @@ mmr_t reserved_0 : 32; } sh_ii_wrap_debug_data_s; } sh_ii_wrap_debug_data_u_t; -#else -typedef union sh_ii_wrap_debug_data_u { - mmr_t sh_ii_wrap_debug_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t ii_wrap_data : 32; - } sh_ii_wrap_debug_data_s; -} sh_ii_wrap_debug_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_LB_DEBUG_DATA" */ /* SHub LB Debug Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_lb_debug_data_u { mmr_t sh_lb_debug_data_regval; struct { @@ -20291,22 +10927,12 @@ mmr_t reserved_0 : 32; } sh_lb_debug_data_s; } sh_lb_debug_data_u_t; -#else -typedef union sh_lb_debug_data_u { - mmr_t sh_lb_debug_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t lb_data : 32; - } sh_lb_debug_data_s; -} sh_lb_debug_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DEBUG_DATA" */ /* SHub MD Debug Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_debug_data_u { mmr_t sh_md_debug_data_regval; struct { @@ -20314,22 +10940,12 @@ mmr_t reserved_0 : 32; } sh_md_debug_data_s; } sh_md_debug_data_u_t; -#else -typedef union sh_md_debug_data_u { - mmr_t sh_md_debug_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t md_data : 32; - } sh_md_debug_data_s; -} sh_md_debug_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_DEBUG_DATA" */ /* SHub PI Debug Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_debug_data_u { mmr_t sh_pi_debug_data_regval; struct { @@ -20337,22 +10953,12 @@ mmr_t reserved_0 : 32; } sh_pi_debug_data_s; } sh_pi_debug_data_u_t; -#else -typedef union sh_pi_debug_data_u { - mmr_t sh_pi_debug_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t pi_data : 32; - } sh_pi_debug_data_s; -} sh_pi_debug_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_DEBUG_DATA" */ /* SHub XN Debug Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_debug_data_u { mmr_t sh_xn_debug_data_regval; struct { @@ -20360,22 +10966,12 @@ mmr_t reserved_0 : 32; } sh_xn_debug_data_s; } sh_xn_debug_data_u_t; -#else -typedef union sh_xn_debug_data_u { - mmr_t sh_xn_debug_data_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t xn_data : 32; - } sh_xn_debug_data_s; -} sh_xn_debug_data_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_ARMED_STATE" */ /* Trigger sequencing facility arm state */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_armed_state_u { mmr_t sh_tsf_armed_state_regval; struct { @@ -20383,22 +10979,12 @@ mmr_t reserved_0 : 56; } sh_tsf_armed_state_s; } sh_tsf_armed_state_u_t; -#else -typedef union sh_tsf_armed_state_u { - mmr_t sh_tsf_armed_state_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t state : 8; - } sh_tsf_armed_state_s; -} sh_tsf_armed_state_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_COUNTER_VALUE" */ /* Trigger sequencing facility counter value */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_counter_value_u { mmr_t sh_tsf_counter_value_regval; struct { @@ -20408,24 +10994,12 @@ mmr_t count_8a : 8; } sh_tsf_counter_value_s; } sh_tsf_counter_value_u_t; -#else -typedef union sh_tsf_counter_value_u { - mmr_t sh_tsf_counter_value_regval; - struct { - mmr_t count_8a : 8; - mmr_t count_8b : 8; - mmr_t count_16 : 16; - mmr_t count_32 : 32; - } sh_tsf_counter_value_s; -} sh_tsf_counter_value_u_t; -#endif /* ==================================================================== */ /* Register "SH_TSF_TRIGGERED_STATE" */ /* Trigger sequencing facility triggered state */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_tsf_triggered_state_u { mmr_t sh_tsf_triggered_state_regval; struct { @@ -20433,64 +11007,36 @@ mmr_t reserved_0 : 56; } sh_tsf_triggered_state_s; } sh_tsf_triggered_state_u_t; -#else -typedef union sh_tsf_triggered_state_u { - mmr_t sh_tsf_triggered_state_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t state : 8; - } sh_tsf_triggered_state_s; -} sh_tsf_triggered_state_u_t; -#endif /* ==================================================================== */ /* Register "SH_VEC_RDDATA" */ /* Vector Reply Message Data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_vec_rddata_u { - mmr_t sh_vec_rddata_regval; - struct { - mmr_t data : 64; - } sh_vec_rddata_s; -} sh_vec_rddata_u_t; -#else typedef union sh_vec_rddata_u { mmr_t sh_vec_rddata_regval; struct { mmr_t data : 64; } sh_vec_rddata_s; } sh_vec_rddata_u_t; -#endif /* ==================================================================== */ /* Register "SH_VEC_RETURN" */ /* Vector Reply Message Return Route */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_vec_return_u { - mmr_t sh_vec_return_regval; - struct { - mmr_t route : 64; - } sh_vec_return_s; -} sh_vec_return_u_t; -#else typedef union sh_vec_return_u { mmr_t sh_vec_return_regval; struct { mmr_t route : 64; } sh_vec_return_s; } sh_vec_return_u_t; -#endif /* ==================================================================== */ /* Register "SH_VEC_STATUS" */ /* Vector Reply Message Status */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_vec_status_u { mmr_t sh_vec_status_regval; struct { @@ -20503,27 +11049,12 @@ mmr_t status_valid : 1; } sh_vec_status_s; } sh_vec_status_u_t; -#else -typedef union sh_vec_status_u { - mmr_t sh_vec_status_regval; - struct { - mmr_t status_valid : 1; - mmr_t overrun : 1; - mmr_t reserved_0 : 2; - mmr_t source : 14; - mmr_t pio_id : 11; - mmr_t address : 32; - mmr_t type : 3; - } sh_vec_status_s; -} sh_vec_status_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT0_CONTROL" */ /* Performance Counter 0 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count0_control_u { mmr_t sh_performance_count0_control_regval; struct { @@ -20541,32 +11072,12 @@ mmr_t reserved_0 : 45; } sh_performance_count0_control_s; } sh_performance_count0_control_u_t; -#else -typedef union sh_performance_count0_control_u { - mmr_t sh_performance_count0_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count0_control_s; -} sh_performance_count0_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT1_CONTROL" */ /* Performance Counter 1 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count1_control_u { mmr_t sh_performance_count1_control_regval; struct { @@ -20584,32 +11095,12 @@ mmr_t reserved_0 : 45; } sh_performance_count1_control_s; } sh_performance_count1_control_u_t; -#else -typedef union sh_performance_count1_control_u { - mmr_t sh_performance_count1_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count1_control_s; -} sh_performance_count1_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT2_CONTROL" */ /* Performance Counter 2 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count2_control_u { mmr_t sh_performance_count2_control_regval; struct { @@ -20627,32 +11118,12 @@ mmr_t reserved_0 : 45; } sh_performance_count2_control_s; } sh_performance_count2_control_u_t; -#else -typedef union sh_performance_count2_control_u { - mmr_t sh_performance_count2_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count2_control_s; -} sh_performance_count2_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT3_CONTROL" */ /* Performance Counter 3 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count3_control_u { mmr_t sh_performance_count3_control_regval; struct { @@ -20670,32 +11141,12 @@ mmr_t reserved_0 : 45; } sh_performance_count3_control_s; } sh_performance_count3_control_u_t; -#else -typedef union sh_performance_count3_control_u { - mmr_t sh_performance_count3_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count3_control_s; -} sh_performance_count3_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT4_CONTROL" */ /* Performance Counter 4 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count4_control_u { mmr_t sh_performance_count4_control_regval; struct { @@ -20713,32 +11164,12 @@ mmr_t reserved_0 : 45; } sh_performance_count4_control_s; } sh_performance_count4_control_u_t; -#else -typedef union sh_performance_count4_control_u { - mmr_t sh_performance_count4_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count4_control_s; -} sh_performance_count4_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT5_CONTROL" */ /* Performance Counter 5 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count5_control_u { mmr_t sh_performance_count5_control_regval; struct { @@ -20756,32 +11187,12 @@ mmr_t reserved_0 : 45; } sh_performance_count5_control_s; } sh_performance_count5_control_u_t; -#else -typedef union sh_performance_count5_control_u { - mmr_t sh_performance_count5_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count5_control_s; -} sh_performance_count5_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT6_CONTROL" */ /* Performance Counter 6 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count6_control_u { mmr_t sh_performance_count6_control_regval; struct { @@ -20799,32 +11210,12 @@ mmr_t reserved_0 : 45; } sh_performance_count6_control_s; } sh_performance_count6_control_u_t; -#else -typedef union sh_performance_count6_control_u { - mmr_t sh_performance_count6_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count6_control_s; -} sh_performance_count6_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNT7_CONTROL" */ /* Performance Counter 7 Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_count7_control_u { mmr_t sh_performance_count7_control_regval; struct { @@ -20842,32 +11233,12 @@ mmr_t reserved_0 : 45; } sh_performance_count7_control_s; } sh_performance_count7_control_u_t; -#else -typedef union sh_performance_count7_control_u { - mmr_t sh_performance_count7_control_regval; - struct { - mmr_t reserved_0 : 45; - mmr_t peak_det_enable : 1; - mmr_t dec_enable : 1; - mmr_t inc_enable : 1; - mmr_t dn_mode : 1; - mmr_t dn_polarity : 1; - mmr_t dn_event : 1; - mmr_t dn_stimulus : 5; - mmr_t up_mode : 1; - mmr_t up_polarity : 1; - mmr_t up_event : 1; - mmr_t up_stimulus : 5; - } sh_performance_count7_control_s; -} sh_performance_count7_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_DN_CONTROL" */ /* Profile Counter Down Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_dn_control_u { mmr_t sh_profile_dn_control_regval; struct { @@ -20878,25 +11249,12 @@ mmr_t reserved_0 : 56; } sh_profile_dn_control_s; } sh_profile_dn_control_u_t; -#else -typedef union sh_profile_dn_control_u { - mmr_t sh_profile_dn_control_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t mode : 1; - mmr_t polarity : 1; - mmr_t event : 1; - mmr_t stimulus : 5; - } sh_profile_dn_control_s; -} sh_profile_dn_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_PEAK_CONTROL" */ /* Profile Counter Peak Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_peak_control_u { mmr_t sh_profile_peak_control_regval; struct { @@ -20908,26 +11266,12 @@ mmr_t reserved_2 : 57; } sh_profile_peak_control_s; } sh_profile_peak_control_u_t; -#else -typedef union sh_profile_peak_control_u { - mmr_t sh_profile_peak_control_regval; - struct { - mmr_t reserved_2 : 57; - mmr_t polarity : 1; - mmr_t event : 1; - mmr_t reserved_1 : 1; - mmr_t stimulus : 1; - mmr_t reserved_0 : 3; - } sh_profile_peak_control_s; -} sh_profile_peak_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_RANGE" */ /* Profile Counter Range */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_range_u { mmr_t sh_profile_range_regval; struct { @@ -20941,28 +11285,12 @@ mmr_t range7 : 8; } sh_profile_range_s; } sh_profile_range_u_t; -#else -typedef union sh_profile_range_u { - mmr_t sh_profile_range_regval; - struct { - mmr_t range7 : 8; - mmr_t range6 : 8; - mmr_t range5 : 8; - mmr_t range4 : 8; - mmr_t range3 : 8; - mmr_t range2 : 8; - mmr_t range1 : 8; - mmr_t range0 : 8; - } sh_profile_range_s; -} sh_profile_range_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_UP_CONTROL" */ /* Profile Counter Up Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_up_control_u { mmr_t sh_profile_up_control_regval; struct { @@ -20973,25 +11301,12 @@ mmr_t reserved_0 : 56; } sh_profile_up_control_s; } sh_profile_up_control_u_t; -#else -typedef union sh_profile_up_control_u { - mmr_t sh_profile_up_control_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t mode : 1; - mmr_t polarity : 1; - mmr_t event : 1; - mmr_t stimulus : 5; - } sh_profile_up_control_s; -} sh_profile_up_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER0" */ /* Performance Counter 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter0_u { mmr_t sh_performance_counter0_regval; struct { @@ -20999,22 +11314,12 @@ mmr_t reserved_0 : 32; } sh_performance_counter0_s; } sh_performance_counter0_u_t; -#else -typedef union sh_performance_counter0_u { - mmr_t sh_performance_counter0_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter0_s; -} sh_performance_counter0_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER1" */ /* Performance Counter 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter1_u { mmr_t sh_performance_counter1_regval; struct { @@ -21022,22 +11327,12 @@ mmr_t reserved_0 : 32; } sh_performance_counter1_s; } sh_performance_counter1_u_t; -#else -typedef union sh_performance_counter1_u { - mmr_t sh_performance_counter1_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter1_s; -} sh_performance_counter1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER2" */ /* Performance Counter 2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter2_u { mmr_t sh_performance_counter2_regval; struct { @@ -21045,22 +11340,12 @@ mmr_t reserved_0 : 32; } sh_performance_counter2_s; } sh_performance_counter2_u_t; -#else -typedef union sh_performance_counter2_u { - mmr_t sh_performance_counter2_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter2_s; -} sh_performance_counter2_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER3" */ /* Performance Counter 3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter3_u { mmr_t sh_performance_counter3_regval; struct { @@ -21068,22 +11353,12 @@ mmr_t reserved_0 : 32; } sh_performance_counter3_s; } sh_performance_counter3_u_t; -#else -typedef union sh_performance_counter3_u { - mmr_t sh_performance_counter3_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter3_s; -} sh_performance_counter3_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER4" */ /* Performance Counter 4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter4_u { mmr_t sh_performance_counter4_regval; struct { @@ -21091,22 +11366,12 @@ mmr_t reserved_0 : 32; } sh_performance_counter4_s; } sh_performance_counter4_u_t; -#else -typedef union sh_performance_counter4_u { - mmr_t sh_performance_counter4_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter4_s; -} sh_performance_counter4_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER5" */ /* Performance Counter 5 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter5_u { mmr_t sh_performance_counter5_regval; struct { @@ -21114,22 +11379,12 @@ mmr_t reserved_0 : 32; } sh_performance_counter5_s; } sh_performance_counter5_u_t; -#else -typedef union sh_performance_counter5_u { - mmr_t sh_performance_counter5_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter5_s; -} sh_performance_counter5_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER6" */ /* Performance Counter 6 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter6_u { mmr_t sh_performance_counter6_regval; struct { @@ -21137,22 +11392,12 @@ mmr_t reserved_0 : 32; } sh_performance_counter6_s; } sh_performance_counter6_u_t; -#else -typedef union sh_performance_counter6_u { - mmr_t sh_performance_counter6_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter6_s; -} sh_performance_counter6_u_t; -#endif /* ==================================================================== */ /* Register "SH_PERFORMANCE_COUNTER7" */ /* Performance Counter 7 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_performance_counter7_u { mmr_t sh_performance_counter7_regval; struct { @@ -21160,22 +11405,12 @@ mmr_t reserved_0 : 32; } sh_performance_counter7_s; } sh_performance_counter7_u_t; -#else -typedef union sh_performance_counter7_u { - mmr_t sh_performance_counter7_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t count : 32; - } sh_performance_counter7_s; -} sh_performance_counter7_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_COUNTER" */ /* Profile Counter */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_counter_u { mmr_t sh_profile_counter_regval; struct { @@ -21183,22 +11418,12 @@ mmr_t reserved_0 : 56; } sh_profile_counter_s; } sh_profile_counter_u_t; -#else -typedef union sh_profile_counter_u { - mmr_t sh_profile_counter_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t counter : 8; - } sh_profile_counter_s; -} sh_profile_counter_u_t; -#endif /* ==================================================================== */ /* Register "SH_PROFILE_PEAK" */ /* Profile Peak Counter */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_profile_peak_u { mmr_t sh_profile_peak_regval; struct { @@ -21206,22 +11431,12 @@ mmr_t reserved_0 : 56; } sh_profile_peak_s; } sh_profile_peak_u_t; -#else -typedef union sh_profile_peak_u { - mmr_t sh_profile_peak_regval; - struct { - mmr_t reserved_0 : 56; - mmr_t counter : 8; - } sh_profile_peak_s; -} sh_profile_peak_u_t; -#endif /* ==================================================================== */ /* Register "SH_PTC_0" */ /* Puge Translation Cache Message Configuration Information */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ptc_0_u { mmr_t sh_ptc_0_regval; struct { @@ -21233,26 +11448,12 @@ mmr_t start : 1; } sh_ptc_0_s; } sh_ptc_0_u_t; -#else -typedef union sh_ptc_0_u { - mmr_t sh_ptc_0_regval; - struct { - mmr_t start : 1; - mmr_t reserved_1 : 31; - mmr_t rid : 24; - mmr_t ps : 6; - mmr_t reserved_0 : 1; - mmr_t a : 1; - } sh_ptc_0_s; -} sh_ptc_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_PTC_1" */ /* Puge Translation Cache Message Configuration Information */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ptc_1_u { mmr_t sh_ptc_1_regval; struct { @@ -21262,24 +11463,12 @@ mmr_t start : 1; } sh_ptc_1_s; } sh_ptc_1_u_t; -#else -typedef union sh_ptc_1_u { - mmr_t sh_ptc_1_regval; - struct { - mmr_t start : 1; - mmr_t reserved_1 : 2; - mmr_t vpn : 49; - mmr_t reserved_0 : 12; - } sh_ptc_1_s; -} sh_ptc_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PTC_PARMS" */ /* PTC Time-out parmaeters */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_ptc_parms_u { mmr_t sh_ptc_parms_regval; struct { @@ -21288,23 +11477,12 @@ mmr_t reserved_0 : 28; } sh_ptc_parms_s; } sh_ptc_parms_u_t; -#else -typedef union sh_ptc_parms_u { - mmr_t sh_ptc_parms_regval; - struct { - mmr_t reserved_0 : 28; - mmr_t ptc_to_val : 12; - mmr_t ptc_to_wrap : 24; - } sh_ptc_parms_s; -} sh_ptc_parms_u_t; -#endif /* ==================================================================== */ /* Register "SH_INT_CMPA" */ /* RTC Compare Value for Processor A */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_int_cmpa_u { mmr_t sh_int_cmpa_regval; struct { @@ -21312,22 +11490,12 @@ mmr_t reserved_0 : 9; } sh_int_cmpa_s; } sh_int_cmpa_u_t; -#else -typedef union sh_int_cmpa_u { - mmr_t sh_int_cmpa_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t real_time_cmpa : 55; - } sh_int_cmpa_s; -} sh_int_cmpa_u_t; -#endif /* ==================================================================== */ /* Register "SH_INT_CMPB" */ /* RTC Compare Value for Processor B */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_int_cmpb_u { mmr_t sh_int_cmpb_regval; struct { @@ -21335,22 +11503,12 @@ mmr_t reserved_0 : 9; } sh_int_cmpb_s; } sh_int_cmpb_u_t; -#else -typedef union sh_int_cmpb_u { - mmr_t sh_int_cmpb_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t real_time_cmpb : 55; - } sh_int_cmpb_s; -} sh_int_cmpb_u_t; -#endif /* ==================================================================== */ /* Register "SH_INT_CMPC" */ /* RTC Compare Value for Processor C */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_int_cmpc_u { mmr_t sh_int_cmpc_regval; struct { @@ -21358,22 +11516,12 @@ mmr_t reserved_0 : 9; } sh_int_cmpc_s; } sh_int_cmpc_u_t; -#else -typedef union sh_int_cmpc_u { - mmr_t sh_int_cmpc_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t real_time_cmpc : 55; - } sh_int_cmpc_s; -} sh_int_cmpc_u_t; -#endif /* ==================================================================== */ /* Register "SH_INT_CMPD" */ /* RTC Compare Value for Processor D */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_int_cmpd_u { mmr_t sh_int_cmpd_regval; struct { @@ -21381,22 +11529,12 @@ mmr_t reserved_0 : 9; } sh_int_cmpd_s; } sh_int_cmpd_u_t; -#else -typedef union sh_int_cmpd_u { - mmr_t sh_int_cmpd_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t real_time_cmpd : 55; - } sh_int_cmpd_s; -} sh_int_cmpd_u_t; -#endif /* ==================================================================== */ /* Register "SH_INT_PROF" */ /* Profile Compare Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_int_prof_u { mmr_t sh_int_prof_regval; struct { @@ -21404,22 +11542,12 @@ mmr_t reserved_0 : 32; } sh_int_prof_s; } sh_int_prof_u_t; -#else -typedef union sh_int_prof_u { - mmr_t sh_int_prof_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t profile_compare : 32; - } sh_int_prof_s; -} sh_int_prof_u_t; -#endif /* ==================================================================== */ /* Register "SH_RTC" */ /* Real-time Clock */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_rtc_u { mmr_t sh_rtc_regval; struct { @@ -21427,85 +11555,48 @@ mmr_t reserved_0 : 9; } sh_rtc_s; } sh_rtc_u_t; -#else -typedef union sh_rtc_u { - mmr_t sh_rtc_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t real_time_clock : 55; - } sh_rtc_s; -} sh_rtc_u_t; -#endif /* ==================================================================== */ /* Register "SH_SCRATCH0" */ /* Scratch Register 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_scratch0_u { mmr_t sh_scratch0_regval; struct { mmr_t scratch0 : 64; } sh_scratch0_s; } sh_scratch0_u_t; -#else -typedef union sh_scratch0_u { - mmr_t sh_scratch0_regval; - struct { - mmr_t scratch0 : 64; - } sh_scratch0_s; -} sh_scratch0_u_t; -#endif /* ==================================================================== */ /* Register "SH_SCRATCH1" */ /* Scratch Register 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_scratch1_u { - mmr_t sh_scratch1_regval; - struct { - mmr_t scratch1 : 64; - } sh_scratch1_s; -} sh_scratch1_u_t; -#else typedef union sh_scratch1_u { mmr_t sh_scratch1_regval; struct { mmr_t scratch1 : 64; } sh_scratch1_s; } sh_scratch1_u_t; -#endif /* ==================================================================== */ /* Register "SH_SCRATCH2" */ /* Scratch Register 2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_scratch2_u { - mmr_t sh_scratch2_regval; - struct { - mmr_t scratch2 : 64; - } sh_scratch2_s; -} sh_scratch2_u_t; -#else typedef union sh_scratch2_u { mmr_t sh_scratch2_regval; struct { mmr_t scratch2 : 64; } sh_scratch2_s; } sh_scratch2_u_t; -#endif /* ==================================================================== */ /* Register "SH_SCRATCH3" */ /* Scratch Register 3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_scratch3_u { mmr_t sh_scratch3_regval; struct { @@ -21513,22 +11604,12 @@ mmr_t reserved_0 : 63; } sh_scratch3_s; } sh_scratch3_u_t; -#else -typedef union sh_scratch3_u { - mmr_t sh_scratch3_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t scratch3 : 1; - } sh_scratch3_s; -} sh_scratch3_u_t; -#endif /* ==================================================================== */ /* Register "SH_SCRATCH4" */ /* Scratch Register 4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_scratch4_u { mmr_t sh_scratch4_regval; struct { @@ -21536,22 +11617,12 @@ mmr_t reserved_0 : 63; } sh_scratch4_s; } sh_scratch4_u_t; -#else -typedef union sh_scratch4_u { - mmr_t sh_scratch4_regval; - struct { - mmr_t reserved_0 : 63; - mmr_t scratch4 : 1; - } sh_scratch4_s; -} sh_scratch4_u_t; -#endif /* ==================================================================== */ /* Register "SH_CRB_MESSAGE_CONTROL" */ /* Coherent Request Buffer Message Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_crb_message_control_u { mmr_t sh_crb_message_control_regval; struct { @@ -21572,35 +11643,12 @@ mmr_t ivack_throttle_control : 16; } sh_crb_message_control_s; } sh_crb_message_control_u_t; -#else -typedef union sh_crb_message_control_u { - mmr_t sh_crb_message_control_regval; - struct { - mmr_t ivack_throttle_control : 16; - mmr_t ivack_stall_count : 16; - mmr_t reserved_0 : 20; - mmr_t enable_ivack_consolidation : 1; - mmr_t suppress_bogus_writes : 1; - mmr_t wrb_attribute_mismatch_xb_enable : 1; - mmr_t rrb_attribute_mismatch_xb_enable : 1; - mmr_t irb_attribute_mismatch_fsb_enable : 1; - mmr_t wrb_attribute_mismatch_fsb_enable : 1; - mmr_t rrb_attribute_mismatch_fsb_enable : 1; - mmr_t message_color_enable : 1; - mmr_t message_color : 1; - mmr_t remote_speculative_message_enable : 1; - mmr_t local_speculative_message_enable : 1; - mmr_t system_coherence_enable : 1; - } sh_crb_message_control_s; -} sh_crb_message_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_CRB_NACK_LIMIT" */ /* CRB Nack Limit */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_crb_nack_limit_u { mmr_t sh_crb_nack_limit_regval; struct { @@ -21610,24 +11658,12 @@ mmr_t enable : 1; } sh_crb_nack_limit_s; } sh_crb_nack_limit_u_t; -#else -typedef union sh_crb_nack_limit_u { - mmr_t sh_crb_nack_limit_regval; - struct { - mmr_t enable : 1; - mmr_t reserved_0 : 47; - mmr_t pri_freq : 4; - mmr_t limit : 12; - } sh_crb_nack_limit_s; -} sh_crb_nack_limit_u_t; -#endif /* ==================================================================== */ /* Register "SH_CRB_TIMEOUT_PRESCALE" */ /* Coherent Request Buffer Timeout Prescale */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_crb_timeout_prescale_u { mmr_t sh_crb_timeout_prescale_regval; struct { @@ -21635,22 +11671,12 @@ mmr_t reserved_0 : 32; } sh_crb_timeout_prescale_s; } sh_crb_timeout_prescale_u_t; -#else -typedef union sh_crb_timeout_prescale_u { - mmr_t sh_crb_timeout_prescale_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t scaling_factor : 32; - } sh_crb_timeout_prescale_s; -} sh_crb_timeout_prescale_u_t; -#endif /* ==================================================================== */ /* Register "SH_CRB_TIMEOUT_SKID" */ /* Coherent Request Buffer Timeout Skid Limit */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_crb_timeout_skid_u { mmr_t sh_crb_timeout_skid_regval; struct { @@ -21659,23 +11685,12 @@ mmr_t reset_skid_count : 1; } sh_crb_timeout_skid_s; } sh_crb_timeout_skid_u_t; -#else -typedef union sh_crb_timeout_skid_u { - mmr_t sh_crb_timeout_skid_regval; - struct { - mmr_t reset_skid_count : 1; - mmr_t reserved_0 : 57; - mmr_t skid : 6; - } sh_crb_timeout_skid_s; -} sh_crb_timeout_skid_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEMORY_WRITE_STATUS_0" */ /* Memory Write Status for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_memory_write_status_0_u { mmr_t sh_memory_write_status_0_regval; struct { @@ -21683,22 +11698,12 @@ mmr_t reserved_0 : 58; } sh_memory_write_status_0_s; } sh_memory_write_status_0_u_t; -#else -typedef union sh_memory_write_status_0_u { - mmr_t sh_memory_write_status_0_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t pending_write_count : 6; - } sh_memory_write_status_0_s; -} sh_memory_write_status_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEMORY_WRITE_STATUS_1" */ /* Memory Write Status for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_memory_write_status_1_u { mmr_t sh_memory_write_status_1_regval; struct { @@ -21706,22 +11711,12 @@ mmr_t reserved_0 : 58; } sh_memory_write_status_1_s; } sh_memory_write_status_1_u_t; -#else -typedef union sh_memory_write_status_1_u { - mmr_t sh_memory_write_status_1_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t pending_write_count : 6; - } sh_memory_write_status_1_s; -} sh_memory_write_status_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_PIO_WRITE_STATUS_0" */ /* PIO Write Status for CPU 0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pio_write_status_0_u { mmr_t sh_pio_write_status_0_regval; struct { @@ -21735,28 +11730,12 @@ mmr_t writes_ok : 1; } sh_pio_write_status_0_s; } sh_pio_write_status_0_u_t; -#else -typedef union sh_pio_write_status_0_u { - mmr_t sh_pio_write_status_0_regval; - struct { - mmr_t writes_ok : 1; - mmr_t reserved_1 : 1; - mmr_t pending_write_count : 6; - mmr_t reserved_0 : 6; - mmr_t write_error_address : 47; - mmr_t write_error : 1; - mmr_t write_deadlock : 1; - mmr_t multi_write_error : 1; - } sh_pio_write_status_0_s; -} sh_pio_write_status_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_PIO_WRITE_STATUS_1" */ /* PIO Write Status for CPU 1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pio_write_status_1_u { mmr_t sh_pio_write_status_1_regval; struct { @@ -21770,28 +11749,12 @@ mmr_t writes_ok : 1; } sh_pio_write_status_1_s; } sh_pio_write_status_1_u_t; -#else -typedef union sh_pio_write_status_1_u { - mmr_t sh_pio_write_status_1_regval; - struct { - mmr_t writes_ok : 1; - mmr_t reserved_1 : 1; - mmr_t pending_write_count : 6; - mmr_t reserved_0 : 6; - mmr_t write_error_address : 47; - mmr_t write_error : 1; - mmr_t write_deadlock : 1; - mmr_t multi_write_error : 1; - } sh_pio_write_status_1_s; -} sh_pio_write_status_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEMORY_WRITE_STATUS_NON_USER_0" */ /* Memory Write Status for CPU 0. OS access only */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_memory_write_status_non_user_0_u { mmr_t sh_memory_write_status_non_user_0_regval; struct { @@ -21800,23 +11763,12 @@ mmr_t clear : 1; } sh_memory_write_status_non_user_0_s; } sh_memory_write_status_non_user_0_u_t; -#else -typedef union sh_memory_write_status_non_user_0_u { - mmr_t sh_memory_write_status_non_user_0_regval; - struct { - mmr_t clear : 1; - mmr_t reserved_0 : 57; - mmr_t pending_write_count : 6; - } sh_memory_write_status_non_user_0_s; -} sh_memory_write_status_non_user_0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEMORY_WRITE_STATUS_NON_USER_1" */ /* Memory Write Status for CPU 1. OS access only */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_memory_write_status_non_user_1_u { mmr_t sh_memory_write_status_non_user_1_regval; struct { @@ -21825,23 +11777,12 @@ mmr_t clear : 1; } sh_memory_write_status_non_user_1_s; } sh_memory_write_status_non_user_1_u_t; -#else -typedef union sh_memory_write_status_non_user_1_u { - mmr_t sh_memory_write_status_non_user_1_regval; - struct { - mmr_t clear : 1; - mmr_t reserved_0 : 57; - mmr_t pending_write_count : 6; - } sh_memory_write_status_non_user_1_s; -} sh_memory_write_status_non_user_1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MMRBIST_ERR" */ /* Error capture for bist read errors */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mmrbist_err_u { mmr_t sh_mmrbist_err_regval; struct { @@ -21853,26 +11794,12 @@ mmr_t reserved_1 : 25; } sh_mmrbist_err_s; } sh_mmrbist_err_u_t; -#else -typedef union sh_mmrbist_err_u { - mmr_t sh_mmrbist_err_regval; - struct { - mmr_t reserved_1 : 25; - mmr_t cancelled : 1; - mmr_t multiple_detected : 1; - mmr_t detected : 1; - mmr_t reserved_0 : 3; - mmr_t addr : 33; - } sh_mmrbist_err_s; -} sh_mmrbist_err_u_t; -#endif /* ==================================================================== */ /* Register "SH_MISC_ERR_HDR_LOWER" */ /* Header capture register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_misc_err_hdr_lower_u { mmr_t sh_misc_err_hdr_lower_regval; struct { @@ -21886,28 +11813,12 @@ mmr_t valid : 1; } sh_misc_err_hdr_lower_s; } sh_misc_err_hdr_lower_u_t; -#else -typedef union sh_misc_err_hdr_lower_u { - mmr_t sh_misc_err_hdr_lower_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_2 : 2; - mmr_t write : 1; - mmr_t reserved_1 : 2; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t reserved_0 : 3; - } sh_misc_err_hdr_lower_s; -} sh_misc_err_hdr_lower_u_t; -#endif /* ==================================================================== */ /* Register "SH_MISC_ERR_HDR_UPPER" */ /* Error header capture packet and protocol errors */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_misc_err_hdr_upper_u { mmr_t sh_misc_err_hdr_upper_regval; struct { @@ -21924,31 +11835,12 @@ mmr_t reserved_1 : 35; } sh_misc_err_hdr_upper_s; } sh_misc_err_hdr_upper_u_t; -#else -typedef union sh_misc_err_hdr_upper_u { - mmr_t sh_misc_err_hdr_upper_regval; - struct { - mmr_t reserved_1 : 35; - mmr_t echo : 9; - mmr_t reserved_0 : 12; - mmr_t xn_pkt_size : 1; - mmr_t pi_pkt_size : 1; - mmr_t dir_acc : 1; - mmr_t rmw_cor : 1; - mmr_t rmw_uc : 1; - mmr_t nonexist_addr : 1; - mmr_t illegal_cmd : 1; - mmr_t dir_protocol : 1; - } sh_misc_err_hdr_upper_s; -} sh_misc_err_hdr_upper_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIR_UC_ERR_HDR_LOWER" */ /* Header capture register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_dir_uc_err_hdr_lower_u { mmr_t sh_dir_uc_err_hdr_lower_regval; struct { @@ -21962,28 +11854,12 @@ mmr_t valid : 1; } sh_dir_uc_err_hdr_lower_s; } sh_dir_uc_err_hdr_lower_u_t; -#else -typedef union sh_dir_uc_err_hdr_lower_u { - mmr_t sh_dir_uc_err_hdr_lower_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_2 : 2; - mmr_t write : 1; - mmr_t reserved_1 : 2; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t reserved_0 : 3; - } sh_dir_uc_err_hdr_lower_s; -} sh_dir_uc_err_hdr_lower_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIR_UC_ERR_HDR_UPPER" */ /* Error header capture packet and protocol errors */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_dir_uc_err_hdr_upper_u { mmr_t sh_dir_uc_err_hdr_upper_regval; struct { @@ -21994,25 +11870,12 @@ mmr_t reserved_2 : 35; } sh_dir_uc_err_hdr_upper_s; } sh_dir_uc_err_hdr_upper_u_t; -#else -typedef union sh_dir_uc_err_hdr_upper_u { - mmr_t sh_dir_uc_err_hdr_upper_regval; - struct { - mmr_t reserved_2 : 35; - mmr_t echo : 9; - mmr_t reserved_1 : 16; - mmr_t dir_uc : 1; - mmr_t reserved_0 : 3; - } sh_dir_uc_err_hdr_upper_s; -} sh_dir_uc_err_hdr_upper_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIR_COR_ERR_HDR_LOWER" */ /* Header capture register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_dir_cor_err_hdr_lower_u { mmr_t sh_dir_cor_err_hdr_lower_regval; struct { @@ -22026,28 +11889,12 @@ mmr_t valid : 1; } sh_dir_cor_err_hdr_lower_s; } sh_dir_cor_err_hdr_lower_u_t; -#else -typedef union sh_dir_cor_err_hdr_lower_u { - mmr_t sh_dir_cor_err_hdr_lower_regval; - struct { - mmr_t valid : 1; - mmr_t reserved_2 : 2; - mmr_t write : 1; - mmr_t reserved_1 : 2; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t reserved_0 : 3; - } sh_dir_cor_err_hdr_lower_s; -} sh_dir_cor_err_hdr_lower_u_t; -#endif /* ==================================================================== */ /* Register "SH_DIR_COR_ERR_HDR_UPPER" */ /* Error header capture packet and protocol errors */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_dir_cor_err_hdr_upper_u { mmr_t sh_dir_cor_err_hdr_upper_regval; struct { @@ -22058,25 +11905,12 @@ mmr_t reserved_2 : 35; } sh_dir_cor_err_hdr_upper_s; } sh_dir_cor_err_hdr_upper_u_t; -#else -typedef union sh_dir_cor_err_hdr_upper_u { - mmr_t sh_dir_cor_err_hdr_upper_regval; - struct { - mmr_t reserved_2 : 35; - mmr_t echo : 9; - mmr_t reserved_1 : 11; - mmr_t dir_cor : 1; - mmr_t reserved_0 : 8; - } sh_dir_cor_err_hdr_upper_s; -} sh_dir_cor_err_hdr_upper_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEM_ERROR_SUMMARY" */ /* Memory error flags */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mem_error_summary_u { mmr_t sh_mem_error_summary_regval; struct { @@ -22118,56 +11952,12 @@ mmr_t reserved_5 : 29; } sh_mem_error_summary_s; } sh_mem_error_summary_u_t; -#else -typedef union sh_mem_error_summary_u { - mmr_t sh_mem_error_summary_regval; - struct { - mmr_t reserved_5 : 29; - mmr_t xn_pkt_size : 1; - mmr_t pi_pkt_size : 1; - mmr_t red_black_err_timeout : 1; - mmr_t xn_request_overflow : 1; - mmr_t pi_request_overflow : 1; - mmr_t xn_reply_overflow : 1; - mmr_t pi_reply_overflow : 1; - mmr_t reserved_4 : 1; - mmr_t dqrs_int_hw : 1; - mmr_t dqrs_int_cor : 1; - mmr_t dqrs_int_uc : 1; - mmr_t reserved_3 : 1; - mmr_t dqrp_int_hw : 1; - mmr_t dqrp_int_cor : 1; - mmr_t dqrp_int_uc : 1; - mmr_t reserved_2 : 1; - mmr_t dqls_int_hw : 1; - mmr_t dqls_int_cor : 1; - mmr_t dqls_int_uc : 1; - mmr_t reserved_1 : 1; - mmr_t dqlp_int_hw : 1; - mmr_t dqlp_int_cor : 1; - mmr_t dqlp_int_uc : 1; - mmr_t reserved_0 : 1; - mmr_t dir_acc : 1; - mmr_t acy_int_hw : 1; - mmr_t acx_int_hw : 1; - mmr_t dqrp_dir_cor : 1; - mmr_t dqrp_dir_uc : 1; - mmr_t dqlp_dir_cor : 1; - mmr_t dqlp_dir_uc : 1; - mmr_t dqrp_dir_perr : 1; - mmr_t dqlp_dir_perr : 1; - mmr_t nonexist_addr : 1; - mmr_t illegal_cmd : 1; - } sh_mem_error_summary_s; -} sh_mem_error_summary_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEM_ERROR_OVERFLOW" */ /* Memory error flags */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mem_error_overflow_u { mmr_t sh_mem_error_overflow_regval; struct { @@ -22209,56 +11999,12 @@ mmr_t reserved_5 : 29; } sh_mem_error_overflow_s; } sh_mem_error_overflow_u_t; -#else -typedef union sh_mem_error_overflow_u { - mmr_t sh_mem_error_overflow_regval; - struct { - mmr_t reserved_5 : 29; - mmr_t xn_pkt_size : 1; - mmr_t pi_pkt_size : 1; - mmr_t red_black_err_timeout : 1; - mmr_t xn_request_overflow : 1; - mmr_t pi_request_overflow : 1; - mmr_t xn_reply_overflow : 1; - mmr_t pi_reply_overflow : 1; - mmr_t reserved_4 : 1; - mmr_t dqrs_int_hw : 1; - mmr_t dqrs_int_cor : 1; - mmr_t dqrs_int_uc : 1; - mmr_t reserved_3 : 1; - mmr_t dqrp_int_hw : 1; - mmr_t dqrp_int_cor : 1; - mmr_t dqrp_int_uc : 1; - mmr_t reserved_2 : 1; - mmr_t dqls_int_hw : 1; - mmr_t dqls_int_cor : 1; - mmr_t dqls_int_uc : 1; - mmr_t reserved_1 : 1; - mmr_t dqlp_int_hw : 1; - mmr_t dqlp_int_cor : 1; - mmr_t dqlp_int_uc : 1; - mmr_t reserved_0 : 1; - mmr_t dir_acc : 1; - mmr_t acy_int_hw : 1; - mmr_t acx_int_hw : 1; - mmr_t dqrp_dir_cor : 1; - mmr_t dqrp_dir_uc : 1; - mmr_t dqlp_dir_cor : 1; - mmr_t dqlp_dir_uc : 1; - mmr_t dqrp_dir_perr : 1; - mmr_t dqlp_dir_perr : 1; - mmr_t nonexist_addr : 1; - mmr_t illegal_cmd : 1; - } sh_mem_error_overflow_s; -} sh_mem_error_overflow_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEM_ERROR_MASK" */ /* Memory error flags */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mem_error_mask_u { mmr_t sh_mem_error_mask_regval; struct { @@ -22300,56 +12046,12 @@ mmr_t reserved_5 : 29; } sh_mem_error_mask_s; } sh_mem_error_mask_u_t; -#else -typedef union sh_mem_error_mask_u { - mmr_t sh_mem_error_mask_regval; - struct { - mmr_t reserved_5 : 29; - mmr_t xn_pkt_size : 1; - mmr_t pi_pkt_size : 1; - mmr_t red_black_err_timeout : 1; - mmr_t xn_request_overflow : 1; - mmr_t pi_request_overflow : 1; - mmr_t xn_reply_overflow : 1; - mmr_t pi_reply_overflow : 1; - mmr_t reserved_4 : 1; - mmr_t dqrs_int_hw : 1; - mmr_t dqrs_int_cor : 1; - mmr_t dqrs_int_uc : 1; - mmr_t reserved_3 : 1; - mmr_t dqrp_int_hw : 1; - mmr_t dqrp_int_cor : 1; - mmr_t dqrp_int_uc : 1; - mmr_t reserved_2 : 1; - mmr_t dqls_int_hw : 1; - mmr_t dqls_int_cor : 1; - mmr_t dqls_int_uc : 1; - mmr_t reserved_1 : 1; - mmr_t dqlp_int_hw : 1; - mmr_t dqlp_int_cor : 1; - mmr_t dqlp_int_uc : 1; - mmr_t reserved_0 : 1; - mmr_t dir_acc : 1; - mmr_t acy_int_hw : 1; - mmr_t acx_int_hw : 1; - mmr_t dqrp_dir_cor : 1; - mmr_t dqrp_dir_uc : 1; - mmr_t dqlp_dir_cor : 1; - mmr_t dqlp_dir_uc : 1; - mmr_t dqrp_dir_perr : 1; - mmr_t dqlp_dir_perr : 1; - mmr_t nonexist_addr : 1; - mmr_t illegal_cmd : 1; - } sh_mem_error_mask_s; -} sh_mem_error_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_DIMM_CFG" */ /* AC Mem Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_dimm_cfg_u { mmr_t sh_x_dimm_cfg_regval; struct { @@ -22377,42 +12079,12 @@ mmr_t reserved_4 : 28; } sh_x_dimm_cfg_s; } sh_x_dimm_cfg_u_t; -#else -typedef union sh_x_dimm_cfg_u { - mmr_t sh_x_dimm_cfg_regval; - struct { - mmr_t reserved_4 : 28; - mmr_t freq : 4; - mmr_t reserved_3 : 1; - mmr_t dimm3_cs : 2; - mmr_t dimm3_rev : 1; - mmr_t dimm3_2bk : 1; - mmr_t dimm3_size : 3; - mmr_t reserved_2 : 1; - mmr_t dimm2_cs : 2; - mmr_t dimm2_rev : 1; - mmr_t dimm2_2bk : 1; - mmr_t dimm2_size : 3; - mmr_t reserved_1 : 1; - mmr_t dimm1_cs : 2; - mmr_t dimm1_rev : 1; - mmr_t dimm1_2bk : 1; - mmr_t dimm1_size : 3; - mmr_t reserved_0 : 1; - mmr_t dimm0_cs : 2; - mmr_t dimm0_rev : 1; - mmr_t dimm0_2bk : 1; - mmr_t dimm0_size : 3; - } sh_x_dimm_cfg_s; -} sh_x_dimm_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_DIMM_CFG" */ /* AC Mem Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_dimm_cfg_u { mmr_t sh_y_dimm_cfg_regval; struct { @@ -22440,42 +12112,12 @@ mmr_t reserved_4 : 28; } sh_y_dimm_cfg_s; } sh_y_dimm_cfg_u_t; -#else -typedef union sh_y_dimm_cfg_u { - mmr_t sh_y_dimm_cfg_regval; - struct { - mmr_t reserved_4 : 28; - mmr_t freq : 4; - mmr_t reserved_3 : 1; - mmr_t dimm3_cs : 2; - mmr_t dimm3_rev : 1; - mmr_t dimm3_2bk : 1; - mmr_t dimm3_size : 3; - mmr_t reserved_2 : 1; - mmr_t dimm2_cs : 2; - mmr_t dimm2_rev : 1; - mmr_t dimm2_2bk : 1; - mmr_t dimm2_size : 3; - mmr_t reserved_1 : 1; - mmr_t dimm1_cs : 2; - mmr_t dimm1_rev : 1; - mmr_t dimm1_2bk : 1; - mmr_t dimm1_size : 3; - mmr_t reserved_0 : 1; - mmr_t dimm0_cs : 2; - mmr_t dimm0_rev : 1; - mmr_t dimm0_2bk : 1; - mmr_t dimm0_size : 3; - } sh_y_dimm_cfg_s; -} sh_y_dimm_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_JNR_DIMM_CFG" */ /* AC Mem Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_jnr_dimm_cfg_u { mmr_t sh_jnr_dimm_cfg_regval; struct { @@ -22503,42 +12145,12 @@ mmr_t reserved_4 : 28; } sh_jnr_dimm_cfg_s; } sh_jnr_dimm_cfg_u_t; -#else -typedef union sh_jnr_dimm_cfg_u { - mmr_t sh_jnr_dimm_cfg_regval; - struct { - mmr_t reserved_4 : 28; - mmr_t freq : 4; - mmr_t reserved_3 : 1; - mmr_t dimm3_cs : 2; - mmr_t dimm3_rev : 1; - mmr_t dimm3_2bk : 1; - mmr_t dimm3_size : 3; - mmr_t reserved_2 : 1; - mmr_t dimm2_cs : 2; - mmr_t dimm2_rev : 1; - mmr_t dimm2_2bk : 1; - mmr_t dimm2_size : 3; - mmr_t reserved_1 : 1; - mmr_t dimm1_cs : 2; - mmr_t dimm1_rev : 1; - mmr_t dimm1_2bk : 1; - mmr_t dimm1_size : 3; - mmr_t reserved_0 : 1; - mmr_t dimm0_cs : 2; - mmr_t dimm0_rev : 1; - mmr_t dimm0_2bk : 1; - mmr_t dimm0_size : 3; - } sh_jnr_dimm_cfg_s; -} sh_jnr_dimm_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_PHASE_CFG" */ /* AC Phase Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_phase_cfg_u { mmr_t sh_x_phase_cfg_regval; struct { @@ -22560,36 +12172,12 @@ mmr_t reserved_0 : 1; } sh_x_phase_cfg_s; } sh_x_phase_cfg_u_t; -#else -typedef union sh_x_phase_cfg_u { - mmr_t sh_x_phase_cfg_regval; - struct { - mmr_t reserved_0 : 1; - mmr_t dq_sel_a : 4; - mmr_t sel_a : 4; - mmr_t phe_bubble : 3; - mmr_t phd_bubble : 3; - mmr_t phc_bubble : 3; - mmr_t phb_bubble : 3; - mmr_t pha_bubble : 3; - mmr_t bubble_en : 5; - mmr_t add_cp : 5; - mmr_t hold_req : 5; - mmr_t hold : 5; - mmr_t dq_ld_b : 5; - mmr_t dq_ld_a : 5; - mmr_t ld_b : 5; - mmr_t ld_a : 5; - } sh_x_phase_cfg_s; -} sh_x_phase_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_CFG" */ /* AC Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_cfg_u { mmr_t sh_x_cfg_regval; struct { @@ -22609,34 +12197,12 @@ mmr_t clr_dir_cache : 1; } sh_x_cfg_s; } sh_x_cfg_u_t; -#else -typedef union sh_x_cfg_u { - mmr_t sh_x_cfg_regval; - struct { - mmr_t clr_dir_cache : 1; - mmr_t inv_cas_addr : 1; - mmr_t req_cntr_val : 6; - mmr_t req_cntr_dis : 1; - mmr_t trcd4_en : 1; - mmr_t trcd2_en : 1; - mmr_t sso_wt_en : 1; - mmr_t wt_bb_clr : 4; - mmr_t dc_bb_clr : 4; - mmr_t da_bb_clr : 4; - mmr_t ta_dlys : 32; - mmr_t dir_counter_init : 6; - mmr_t dirc_random_replacement : 1; - mmr_t mode_serial : 1; - } sh_x_cfg_s; -} sh_x_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_DQCT_CFG" */ /* AC Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_dqct_cfg_u { mmr_t sh_x_dqct_cfg_regval; struct { @@ -22649,27 +12215,12 @@ mmr_t reserved_0 : 40; } sh_x_dqct_cfg_s; } sh_x_dqct_cfg_u_t; -#else -typedef union sh_x_dqct_cfg_u { - mmr_t sh_x_dqct_cfg_regval; - struct { - mmr_t reserved_0 : 40; - mmr_t mdir_rd_sel : 4; - mmr_t dir_rd_sel : 4; - mmr_t dta_wt_sel : 4; - mmr_t dta_rd_sel : 4; - mmr_t wt_sel : 4; - mmr_t rd_sel : 4; - } sh_x_dqct_cfg_s; -} sh_x_dqct_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_REFRESH_CONTROL" */ /* Refresh Control Register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_refresh_control_u { mmr_t sh_x_refresh_control_regval; struct { @@ -22681,26 +12232,12 @@ mmr_t reserved_0 : 36; } sh_x_refresh_control_s; } sh_x_refresh_control_u_t; -#else -typedef union sh_x_refresh_control_u { - mmr_t sh_x_refresh_control_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t half_rate : 4; - mmr_t interleave : 1; - mmr_t hold : 6; - mmr_t interval : 9; - mmr_t enable : 8; - } sh_x_refresh_control_s; -} sh_x_refresh_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_PHASE_CFG" */ /* AC Phase Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_phase_cfg_u { mmr_t sh_y_phase_cfg_regval; struct { @@ -22722,36 +12259,12 @@ mmr_t reserved_0 : 1; } sh_y_phase_cfg_s; } sh_y_phase_cfg_u_t; -#else -typedef union sh_y_phase_cfg_u { - mmr_t sh_y_phase_cfg_regval; - struct { - mmr_t reserved_0 : 1; - mmr_t dq_sel_a : 4; - mmr_t sel_a : 4; - mmr_t phe_bubble : 3; - mmr_t phd_bubble : 3; - mmr_t phc_bubble : 3; - mmr_t phb_bubble : 3; - mmr_t pha_bubble : 3; - mmr_t bubble_en : 5; - mmr_t add_cp : 5; - mmr_t hold_req : 5; - mmr_t hold : 5; - mmr_t dq_ld_b : 5; - mmr_t dq_ld_a : 5; - mmr_t ld_b : 5; - mmr_t ld_a : 5; - } sh_y_phase_cfg_s; -} sh_y_phase_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_CFG" */ /* AC Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_cfg_u { mmr_t sh_y_cfg_regval; struct { @@ -22771,34 +12284,12 @@ mmr_t clr_dir_cache : 1; } sh_y_cfg_s; } sh_y_cfg_u_t; -#else -typedef union sh_y_cfg_u { - mmr_t sh_y_cfg_regval; - struct { - mmr_t clr_dir_cache : 1; - mmr_t inv_cas_addr : 1; - mmr_t req_cntr_val : 6; - mmr_t req_cntr_dis : 1; - mmr_t trcd4_en : 1; - mmr_t trcd2_en : 1; - mmr_t sso_wt_en : 1; - mmr_t wt_bb_clr : 4; - mmr_t dc_bb_clr : 4; - mmr_t da_bb_clr : 4; - mmr_t ta_dlys : 32; - mmr_t dir_counter_init : 6; - mmr_t dirc_random_replacement : 1; - mmr_t mode_serial : 1; - } sh_y_cfg_s; -} sh_y_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_DQCT_CFG" */ /* AC Config Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_dqct_cfg_u { mmr_t sh_y_dqct_cfg_regval; struct { @@ -22811,27 +12302,12 @@ mmr_t reserved_0 : 40; } sh_y_dqct_cfg_s; } sh_y_dqct_cfg_u_t; -#else -typedef union sh_y_dqct_cfg_u { - mmr_t sh_y_dqct_cfg_regval; - struct { - mmr_t reserved_0 : 40; - mmr_t mdir_rd_sel : 4; - mmr_t dir_rd_sel : 4; - mmr_t dta_wt_sel : 4; - mmr_t dta_rd_sel : 4; - mmr_t wt_sel : 4; - mmr_t rd_sel : 4; - } sh_y_dqct_cfg_s; -} sh_y_dqct_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_REFRESH_CONTROL" */ /* Refresh Control Register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_refresh_control_u { mmr_t sh_y_refresh_control_regval; struct { @@ -22843,26 +12319,12 @@ mmr_t reserved_0 : 36; } sh_y_refresh_control_s; } sh_y_refresh_control_u_t; -#else -typedef union sh_y_refresh_control_u { - mmr_t sh_y_refresh_control_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t half_rate : 4; - mmr_t interleave : 1; - mmr_t hold : 6; - mmr_t interval : 9; - mmr_t enable : 8; - } sh_y_refresh_control_s; -} sh_y_refresh_control_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEM_RED_BLACK" */ /* MD fairness watchdog timers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mem_red_black_u { mmr_t sh_mem_red_black_regval; struct { @@ -22871,22 +12333,11 @@ mmr_t reserved_0 : 12; } sh_mem_red_black_s; } sh_mem_red_black_u_t; -#else -typedef union sh_mem_red_black_u { - mmr_t sh_mem_red_black_regval; - struct { - mmr_t reserved_0 : 12; - mmr_t err_time : 36; - mmr_t time : 16; - } sh_mem_red_black_s; -} sh_mem_red_black_u_t; -#endif /* ==================================================================== */ /* Register "SH_MISC_MEM_CFG" */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_misc_mem_cfg_u { mmr_t sh_misc_mem_cfg_regval; struct { @@ -22909,37 +12360,12 @@ mmr_t reserved_5 : 11; } sh_misc_mem_cfg_s; } sh_misc_mem_cfg_u_t; -#else -typedef union sh_misc_mem_cfg_u { - mmr_t sh_misc_mem_cfg_regval; - struct { - mmr_t reserved_5 : 11; - mmr_t alternate_xn_rp_plane : 1; - mmr_t reserved_4 : 2; - mmr_t disabled_victims : 6; - mmr_t reserved_3 : 3; - mmr_t disabled_write_tnums : 5; - mmr_t reserved_2 : 3; - mmr_t disabled_read_tnums : 5; - mmr_t throttle_cnt : 8; - mmr_t reserved_1 : 2; - mmr_t low_victim_buffer_threshold : 6; - mmr_t reserved_0 : 2; - mmr_t low_write_buffer_threshold : 6; - mmr_t xn_rd_same_as_pi : 1; - mmr_t jnr_bypass_enable : 1; - mmr_t spec_header_enable : 1; - mmr_t express_header_enable : 1; - } sh_misc_mem_cfg_s; -} sh_misc_mem_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_PIO_RQ_CRD_CTL" */ /* pio_rq Credit Circulation Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pio_rq_crd_ctl_u { mmr_t sh_pio_rq_crd_ctl_regval; struct { @@ -22947,22 +12373,12 @@ mmr_t reserved_0 : 58; } sh_pio_rq_crd_ctl_s; } sh_pio_rq_crd_ctl_u_t; -#else -typedef union sh_pio_rq_crd_ctl_u { - mmr_t sh_pio_rq_crd_ctl_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t depth : 6; - } sh_pio_rq_crd_ctl_s; -} sh_pio_rq_crd_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_MD_RQ_CRD_CTL" */ /* pi_md_rq Credit Circulation Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_md_rq_crd_ctl_u { mmr_t sh_pi_md_rq_crd_ctl_regval; struct { @@ -22970,22 +12386,12 @@ mmr_t reserved_0 : 58; } sh_pi_md_rq_crd_ctl_s; } sh_pi_md_rq_crd_ctl_u_t; -#else -typedef union sh_pi_md_rq_crd_ctl_u { - mmr_t sh_pi_md_rq_crd_ctl_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t depth : 6; - } sh_pi_md_rq_crd_ctl_s; -} sh_pi_md_rq_crd_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_PI_MD_RP_CRD_CTL" */ /* pi_md_rp Credit Circulation Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_pi_md_rp_crd_ctl_u { mmr_t sh_pi_md_rp_crd_ctl_regval; struct { @@ -22993,22 +12399,12 @@ mmr_t reserved_0 : 58; } sh_pi_md_rp_crd_ctl_s; } sh_pi_md_rp_crd_ctl_u_t; -#else -typedef union sh_pi_md_rp_crd_ctl_u { - mmr_t sh_pi_md_rp_crd_ctl_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t depth : 6; - } sh_pi_md_rp_crd_ctl_s; -} sh_pi_md_rp_crd_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_RQ_CRD_CTL" */ /* xn_md_rq Credit Circulation Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_rq_crd_ctl_u { mmr_t sh_xn_md_rq_crd_ctl_regval; struct { @@ -23016,22 +12412,12 @@ mmr_t reserved_0 : 58; } sh_xn_md_rq_crd_ctl_s; } sh_xn_md_rq_crd_ctl_u_t; -#else -typedef union sh_xn_md_rq_crd_ctl_u { - mmr_t sh_xn_md_rq_crd_ctl_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t depth : 6; - } sh_xn_md_rq_crd_ctl_s; -} sh_xn_md_rq_crd_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_XN_MD_RP_CRD_CTL" */ /* xn_md_rp Credit Circulation Control */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_xn_md_rp_crd_ctl_u { mmr_t sh_xn_md_rp_crd_ctl_regval; struct { @@ -23039,22 +12425,12 @@ mmr_t reserved_0 : 58; } sh_xn_md_rp_crd_ctl_s; } sh_xn_md_rp_crd_ctl_u_t; -#else -typedef union sh_xn_md_rp_crd_ctl_u { - mmr_t sh_xn_md_rp_crd_ctl_regval; - struct { - mmr_t reserved_0 : 58; - mmr_t depth : 6; - } sh_xn_md_rp_crd_ctl_s; -} sh_xn_md_rp_crd_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG0" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag0_u { mmr_t sh_x_tag0_regval; struct { @@ -23062,22 +12438,12 @@ mmr_t reserved_0 : 44; } sh_x_tag0_s; } sh_x_tag0_u_t; -#else -typedef union sh_x_tag0_u { - mmr_t sh_x_tag0_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag0_s; -} sh_x_tag0_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG1" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag1_u { mmr_t sh_x_tag1_regval; struct { @@ -23085,22 +12451,12 @@ mmr_t reserved_0 : 44; } sh_x_tag1_s; } sh_x_tag1_u_t; -#else -typedef union sh_x_tag1_u { - mmr_t sh_x_tag1_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag1_s; -} sh_x_tag1_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG2" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag2_u { mmr_t sh_x_tag2_regval; struct { @@ -23108,22 +12464,12 @@ mmr_t reserved_0 : 44; } sh_x_tag2_s; } sh_x_tag2_u_t; -#else -typedef union sh_x_tag2_u { - mmr_t sh_x_tag2_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag2_s; -} sh_x_tag2_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG3" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag3_u { mmr_t sh_x_tag3_regval; struct { @@ -23131,22 +12477,12 @@ mmr_t reserved_0 : 44; } sh_x_tag3_s; } sh_x_tag3_u_t; -#else -typedef union sh_x_tag3_u { - mmr_t sh_x_tag3_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag3_s; -} sh_x_tag3_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG4" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag4_u { mmr_t sh_x_tag4_regval; struct { @@ -23154,22 +12490,12 @@ mmr_t reserved_0 : 44; } sh_x_tag4_s; } sh_x_tag4_u_t; -#else -typedef union sh_x_tag4_u { - mmr_t sh_x_tag4_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag4_s; -} sh_x_tag4_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG5" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag5_u { mmr_t sh_x_tag5_regval; struct { @@ -23177,22 +12503,12 @@ mmr_t reserved_0 : 44; } sh_x_tag5_s; } sh_x_tag5_u_t; -#else -typedef union sh_x_tag5_u { - mmr_t sh_x_tag5_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag5_s; -} sh_x_tag5_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG6" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag6_u { mmr_t sh_x_tag6_regval; struct { @@ -23200,22 +12516,12 @@ mmr_t reserved_0 : 44; } sh_x_tag6_s; } sh_x_tag6_u_t; -#else -typedef union sh_x_tag6_u { - mmr_t sh_x_tag6_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag6_s; -} sh_x_tag6_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG7" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag7_u { mmr_t sh_x_tag7_regval; struct { @@ -23223,22 +12529,12 @@ mmr_t reserved_0 : 44; } sh_x_tag7_s; } sh_x_tag7_u_t; -#else -typedef union sh_x_tag7_u { - mmr_t sh_x_tag7_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_x_tag7_s; -} sh_x_tag7_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG0" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag0_u { mmr_t sh_y_tag0_regval; struct { @@ -23246,22 +12542,12 @@ mmr_t reserved_0 : 44; } sh_y_tag0_s; } sh_y_tag0_u_t; -#else -typedef union sh_y_tag0_u { - mmr_t sh_y_tag0_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag0_s; -} sh_y_tag0_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG1" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag1_u { mmr_t sh_y_tag1_regval; struct { @@ -23269,22 +12555,12 @@ mmr_t reserved_0 : 44; } sh_y_tag1_s; } sh_y_tag1_u_t; -#else -typedef union sh_y_tag1_u { - mmr_t sh_y_tag1_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag1_s; -} sh_y_tag1_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG2" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag2_u { mmr_t sh_y_tag2_regval; struct { @@ -23292,22 +12568,12 @@ mmr_t reserved_0 : 44; } sh_y_tag2_s; } sh_y_tag2_u_t; -#else -typedef union sh_y_tag2_u { - mmr_t sh_y_tag2_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag2_s; -} sh_y_tag2_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG3" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag3_u { mmr_t sh_y_tag3_regval; struct { @@ -23315,22 +12581,12 @@ mmr_t reserved_0 : 44; } sh_y_tag3_s; } sh_y_tag3_u_t; -#else -typedef union sh_y_tag3_u { - mmr_t sh_y_tag3_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag3_s; -} sh_y_tag3_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG4" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag4_u { mmr_t sh_y_tag4_regval; struct { @@ -23338,22 +12594,12 @@ mmr_t reserved_0 : 44; } sh_y_tag4_s; } sh_y_tag4_u_t; -#else -typedef union sh_y_tag4_u { - mmr_t sh_y_tag4_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag4_s; -} sh_y_tag4_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG5" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag5_u { mmr_t sh_y_tag5_regval; struct { @@ -23361,22 +12607,12 @@ mmr_t reserved_0 : 44; } sh_y_tag5_s; } sh_y_tag5_u_t; -#else -typedef union sh_y_tag5_u { - mmr_t sh_y_tag5_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag5_s; -} sh_y_tag5_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG6" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag6_u { mmr_t sh_y_tag6_regval; struct { @@ -23384,22 +12620,12 @@ mmr_t reserved_0 : 44; } sh_y_tag6_s; } sh_y_tag6_u_t; -#else -typedef union sh_y_tag6_u { - mmr_t sh_y_tag6_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag6_s; -} sh_y_tag6_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG7" */ /* AC tag Registers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag7_u { mmr_t sh_y_tag7_regval; struct { @@ -23407,22 +12633,12 @@ mmr_t reserved_0 : 44; } sh_y_tag7_s; } sh_y_tag7_u_t; -#else -typedef union sh_y_tag7_u { - mmr_t sh_y_tag7_regval; - struct { - mmr_t reserved_0 : 44; - mmr_t tag : 20; - } sh_y_tag7_s; -} sh_y_tag7_u_t; -#endif /* ==================================================================== */ /* Register "SH_MMRBIST_BASE" */ /* mmr/bist base address */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mmrbist_base_u { mmr_t sh_mmrbist_base_regval; struct { @@ -23431,23 +12647,12 @@ mmr_t reserved_1 : 14; } sh_mmrbist_base_s; } sh_mmrbist_base_u_t; -#else -typedef union sh_mmrbist_base_u { - mmr_t sh_mmrbist_base_regval; - struct { - mmr_t reserved_1 : 14; - mmr_t dword_addr : 47; - mmr_t reserved_0 : 3; - } sh_mmrbist_base_s; -} sh_mmrbist_base_u_t; -#endif /* ==================================================================== */ /* Register "SH_MMRBIST_CTL" */ /* Bist base address */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mmrbist_ctl_u { mmr_t sh_mmrbist_ctl_regval; struct { @@ -23463,30 +12668,12 @@ mmr_t reserved_3 : 19; } sh_mmrbist_ctl_s; } sh_mmrbist_ctl_u_t; -#else -typedef union sh_mmrbist_ctl_u { - mmr_t sh_mmrbist_ctl_regval; - struct { - mmr_t reserved_3 : 19; - mmr_t reset_state : 1; - mmr_t reserved_2 : 1; - mmr_t mem_idle : 1; - mmr_t fail : 1; - mmr_t in_progress : 1; - mmr_t reserved_1 : 1; - mmr_t cmd : 7; - mmr_t reserved_0 : 1; - mmr_t block_length : 31; - } sh_mmrbist_ctl_s; -} sh_mmrbist_ctl_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DBUG_DATA_CFG" */ /* configuration for md debug data muxes */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dbug_data_cfg_u { mmr_t sh_md_dbug_data_cfg_regval; struct { @@ -23524,52 +12711,12 @@ mmr_t reserved_15 : 1; } sh_md_dbug_data_cfg_s; } sh_md_dbug_data_cfg_u_t; -#else -typedef union sh_md_dbug_data_cfg_u { - mmr_t sh_md_dbug_data_cfg_regval; - struct { - mmr_t reserved_15 : 1; - mmr_t nibble7_nibble : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_chiplet : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_chiplet : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_chiplet : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_chiplet : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_chiplet : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_chiplet : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_chiplet : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_chiplet : 3; - } sh_md_dbug_data_cfg_s; -} sh_md_dbug_data_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DBUG_TRIGGER_CFG" */ /* configuration for md debug triggers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dbug_trigger_cfg_u { mmr_t sh_md_dbug_trigger_cfg_regval; struct { @@ -23607,52 +12754,12 @@ mmr_t enable : 1; } sh_md_dbug_trigger_cfg_s; } sh_md_dbug_trigger_cfg_u_t; -#else -typedef union sh_md_dbug_trigger_cfg_u { - mmr_t sh_md_dbug_trigger_cfg_regval; - struct { - mmr_t enable : 1; - mmr_t nibble7_nibble : 3; - mmr_t reserved_14 : 1; - mmr_t nibble7_chiplet : 3; - mmr_t reserved_13 : 1; - mmr_t nibble6_nibble : 3; - mmr_t reserved_12 : 1; - mmr_t nibble6_chiplet : 3; - mmr_t reserved_11 : 1; - mmr_t nibble5_nibble : 3; - mmr_t reserved_10 : 1; - mmr_t nibble5_chiplet : 3; - mmr_t reserved_9 : 1; - mmr_t nibble4_nibble : 3; - mmr_t reserved_8 : 1; - mmr_t nibble4_chiplet : 3; - mmr_t reserved_7 : 1; - mmr_t nibble3_nibble : 3; - mmr_t reserved_6 : 1; - mmr_t nibble3_chiplet : 3; - mmr_t reserved_5 : 1; - mmr_t nibble2_nibble : 3; - mmr_t reserved_4 : 1; - mmr_t nibble2_chiplet : 3; - mmr_t reserved_3 : 1; - mmr_t nibble1_nibble : 3; - mmr_t reserved_2 : 1; - mmr_t nibble1_chiplet : 3; - mmr_t reserved_1 : 1; - mmr_t nibble0_nibble : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_chiplet : 3; - } sh_md_dbug_trigger_cfg_s; -} sh_md_dbug_trigger_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DBUG_COMPARE" */ /* md debug compare pattern and mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dbug_compare_u { mmr_t sh_md_dbug_compare_regval; struct { @@ -23660,22 +12767,12 @@ mmr_t mask : 32; } sh_md_dbug_compare_s; } sh_md_dbug_compare_u_t; -#else -typedef union sh_md_dbug_compare_u { - mmr_t sh_md_dbug_compare_regval; - struct { - mmr_t mask : 32; - mmr_t pattern : 32; - } sh_md_dbug_compare_s; -} sh_md_dbug_compare_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_MOD_DBUG_SEL" */ /* MD acx debug select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_mod_dbug_sel_u { mmr_t sh_x_mod_dbug_sel_regval; struct { @@ -23689,28 +12786,12 @@ mmr_t reserved_0 : 6; } sh_x_mod_dbug_sel_s; } sh_x_mod_dbug_sel_u_t; -#else -typedef union sh_x_mod_dbug_sel_u { - mmr_t sh_x_mod_dbug_sel_regval; - struct { - mmr_t reserved_0 : 6; - mmr_t dqr_sel : 6; - mmr_t dql_sel : 6; - mmr_t atr_sel : 11; - mmr_t atl_sel : 11; - mmr_t arb_sel : 8; - mmr_t wbq_sel : 8; - mmr_t tag_sel : 8; - } sh_x_mod_dbug_sel_s; -} sh_x_mod_dbug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_DBUG_SEL" */ /* MD acx debug select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_dbug_sel_u { mmr_t sh_x_dbug_sel_regval; struct { @@ -23718,22 +12799,12 @@ mmr_t reserved_0 : 40; } sh_x_dbug_sel_s; } sh_x_dbug_sel_u_t; -#else -typedef union sh_x_dbug_sel_u { - mmr_t sh_x_dbug_sel_regval; - struct { - mmr_t reserved_0 : 40; - mmr_t dbg_sel : 24; - } sh_x_dbug_sel_s; -} sh_x_dbug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_LADDR_CMP" */ /* MD acx address compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_laddr_cmp_u { mmr_t sh_x_laddr_cmp_regval; struct { @@ -23743,24 +12814,12 @@ mmr_t reserved_1 : 4; } sh_x_laddr_cmp_s; } sh_x_laddr_cmp_u_t; -#else -typedef union sh_x_laddr_cmp_u { - mmr_t sh_x_laddr_cmp_regval; - struct { - mmr_t reserved_1 : 4; - mmr_t mask_val : 28; - mmr_t reserved_0 : 4; - mmr_t cmp_val : 28; - } sh_x_laddr_cmp_s; -} sh_x_laddr_cmp_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_RADDR_CMP" */ /* MD acx address compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_raddr_cmp_u { mmr_t sh_x_raddr_cmp_regval; struct { @@ -23770,24 +12829,12 @@ mmr_t reserved_1 : 4; } sh_x_raddr_cmp_s; } sh_x_raddr_cmp_u_t; -#else -typedef union sh_x_raddr_cmp_u { - mmr_t sh_x_raddr_cmp_regval; - struct { - mmr_t reserved_1 : 4; - mmr_t mask_val : 28; - mmr_t reserved_0 : 4; - mmr_t cmp_val : 28; - } sh_x_raddr_cmp_s; -} sh_x_raddr_cmp_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG_CMP" */ /* MD acx tagmgr compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag_cmp_u { mmr_t sh_x_tag_cmp_regval; struct { @@ -23797,24 +12844,12 @@ mmr_t reserved_0 : 9; } sh_x_tag_cmp_s; } sh_x_tag_cmp_u_t; -#else -typedef union sh_x_tag_cmp_u { - mmr_t sh_x_tag_cmp_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t src : 14; - mmr_t addr : 33; - mmr_t cmd : 8; - } sh_x_tag_cmp_s; -} sh_x_tag_cmp_u_t; -#endif /* ==================================================================== */ /* Register "SH_X_TAG_MASK" */ /* MD acx tagmgr mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_x_tag_mask_u { mmr_t sh_x_tag_mask_regval; struct { @@ -23824,24 +12859,12 @@ mmr_t reserved_0 : 9; } sh_x_tag_mask_s; } sh_x_tag_mask_u_t; -#else -typedef union sh_x_tag_mask_u { - mmr_t sh_x_tag_mask_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t src : 14; - mmr_t addr : 33; - mmr_t cmd : 8; - } sh_x_tag_mask_s; -} sh_x_tag_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_MOD_DBUG_SEL" */ /* MD acy debug select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_mod_dbug_sel_u { mmr_t sh_y_mod_dbug_sel_regval; struct { @@ -23855,28 +12878,12 @@ mmr_t reserved_0 : 6; } sh_y_mod_dbug_sel_s; } sh_y_mod_dbug_sel_u_t; -#else -typedef union sh_y_mod_dbug_sel_u { - mmr_t sh_y_mod_dbug_sel_regval; - struct { - mmr_t reserved_0 : 6; - mmr_t dqr_sel : 6; - mmr_t dql_sel : 6; - mmr_t atr_sel : 11; - mmr_t atl_sel : 11; - mmr_t arb_sel : 8; - mmr_t wbq_sel : 8; - mmr_t tag_sel : 8; - } sh_y_mod_dbug_sel_s; -} sh_y_mod_dbug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_DBUG_SEL" */ /* MD acy debug select */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_dbug_sel_u { mmr_t sh_y_dbug_sel_regval; struct { @@ -23884,22 +12891,12 @@ mmr_t reserved_0 : 40; } sh_y_dbug_sel_s; } sh_y_dbug_sel_u_t; -#else -typedef union sh_y_dbug_sel_u { - mmr_t sh_y_dbug_sel_regval; - struct { - mmr_t reserved_0 : 40; - mmr_t dbg_sel : 24; - } sh_y_dbug_sel_s; -} sh_y_dbug_sel_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_LADDR_CMP" */ /* MD acy address compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_laddr_cmp_u { mmr_t sh_y_laddr_cmp_regval; struct { @@ -23909,24 +12906,12 @@ mmr_t reserved_1 : 4; } sh_y_laddr_cmp_s; } sh_y_laddr_cmp_u_t; -#else -typedef union sh_y_laddr_cmp_u { - mmr_t sh_y_laddr_cmp_regval; - struct { - mmr_t reserved_1 : 4; - mmr_t mask_val : 28; - mmr_t reserved_0 : 4; - mmr_t cmp_val : 28; - } sh_y_laddr_cmp_s; -} sh_y_laddr_cmp_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_RADDR_CMP" */ /* MD acy address compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_raddr_cmp_u { mmr_t sh_y_raddr_cmp_regval; struct { @@ -23936,24 +12921,12 @@ mmr_t reserved_1 : 4; } sh_y_raddr_cmp_s; } sh_y_raddr_cmp_u_t; -#else -typedef union sh_y_raddr_cmp_u { - mmr_t sh_y_raddr_cmp_regval; - struct { - mmr_t reserved_1 : 4; - mmr_t mask_val : 28; - mmr_t reserved_0 : 4; - mmr_t cmp_val : 28; - } sh_y_raddr_cmp_s; -} sh_y_raddr_cmp_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG_CMP" */ /* MD acy tagmgr compare */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag_cmp_u { mmr_t sh_y_tag_cmp_regval; struct { @@ -23963,24 +12936,12 @@ mmr_t reserved_0 : 9; } sh_y_tag_cmp_s; } sh_y_tag_cmp_u_t; -#else -typedef union sh_y_tag_cmp_u { - mmr_t sh_y_tag_cmp_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t src : 14; - mmr_t addr : 33; - mmr_t cmd : 8; - } sh_y_tag_cmp_s; -} sh_y_tag_cmp_u_t; -#endif /* ==================================================================== */ /* Register "SH_Y_TAG_MASK" */ /* MD acy tagmgr mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_y_tag_mask_u { mmr_t sh_y_tag_mask_regval; struct { @@ -23990,24 +12951,12 @@ mmr_t reserved_0 : 9; } sh_y_tag_mask_s; } sh_y_tag_mask_u_t; -#else -typedef union sh_y_tag_mask_u { - mmr_t sh_y_tag_mask_regval; - struct { - mmr_t reserved_0 : 9; - mmr_t src : 14; - mmr_t addr : 33; - mmr_t cmd : 8; - } sh_y_tag_mask_s; -} sh_y_tag_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_JNR_DBUG_DATA_CFG" */ /* configuration for md jnr debug data muxes */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_jnr_dbug_data_cfg_u { mmr_t sh_md_jnr_dbug_data_cfg_regval; struct { @@ -24029,36 +12978,12 @@ mmr_t reserved_7 : 33; } sh_md_jnr_dbug_data_cfg_s; } sh_md_jnr_dbug_data_cfg_u_t; -#else -typedef union sh_md_jnr_dbug_data_cfg_u { - mmr_t sh_md_jnr_dbug_data_cfg_regval; - struct { - mmr_t reserved_7 : 33; - mmr_t nibble7_sel : 3; - mmr_t reserved_6 : 1; - mmr_t nibble6_sel : 3; - mmr_t reserved_5 : 1; - mmr_t nibble5_sel : 3; - mmr_t reserved_4 : 1; - mmr_t nibble4_sel : 3; - mmr_t reserved_3 : 1; - mmr_t nibble3_sel : 3; - mmr_t reserved_2 : 1; - mmr_t nibble2_sel : 3; - mmr_t reserved_1 : 1; - mmr_t nibble1_sel : 3; - mmr_t reserved_0 : 1; - mmr_t nibble0_sel : 3; - } sh_md_jnr_dbug_data_cfg_s; -} sh_md_jnr_dbug_data_cfg_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_LAST_CREDIT" */ /* captures last credit values on reset */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_last_credit_u { mmr_t sh_md_last_credit_regval; struct { @@ -24074,30 +12999,12 @@ mmr_t reserved_4 : 26; } sh_md_last_credit_s; } sh_md_last_credit_u_t; -#else -typedef union sh_md_last_credit_u { - mmr_t sh_md_last_credit_regval; - struct { - mmr_t reserved_4 : 26; - mmr_t to_lb : 6; - mmr_t reserved_3 : 2; - mmr_t rp_to_xn : 6; - mmr_t reserved_2 : 2; - mmr_t rq_to_xn : 6; - mmr_t reserved_1 : 2; - mmr_t rp_to_pi : 6; - mmr_t reserved_0 : 2; - mmr_t rq_to_pi : 6; - } sh_md_last_credit_s; -} sh_md_last_credit_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEM_CAPTURE_ADDR" */ /* Address capture address register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mem_capture_addr_u { mmr_t sh_mem_capture_addr_regval; struct { @@ -24107,24 +13014,12 @@ mmr_t reserved_1 : 20; } sh_mem_capture_addr_s; } sh_mem_capture_addr_u_t; -#else -typedef union sh_mem_capture_addr_u { - mmr_t sh_mem_capture_addr_regval; - struct { - mmr_t reserved_1 : 20; - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t reserved_0 : 3; - } sh_mem_capture_addr_s; -} sh_mem_capture_addr_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEM_CAPTURE_MASK" */ /* Address capture mask register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mem_capture_mask_u { mmr_t sh_mem_capture_mask_regval; struct { @@ -24136,26 +13031,12 @@ mmr_t reserved_1 : 18; } sh_mem_capture_mask_s; } sh_mem_capture_mask_u_t; -#else -typedef union sh_mem_capture_mask_u { - mmr_t sh_mem_capture_mask_regval; - struct { - mmr_t reserved_1 : 18; - mmr_t enable_remote : 1; - mmr_t enable_local : 1; - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t reserved_0 : 3; - } sh_mem_capture_mask_s; -} sh_mem_capture_mask_u_t; -#endif /* ==================================================================== */ /* Register "SH_MEM_CAPTURE_HDR" */ /* Address capture header register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_mem_capture_hdr_u { mmr_t sh_mem_capture_hdr_regval; struct { @@ -24166,25 +13047,12 @@ mmr_t cntr : 6; } sh_mem_capture_hdr_s; } sh_mem_capture_hdr_u_t; -#else -typedef union sh_mem_capture_hdr_u { - mmr_t sh_mem_capture_hdr_regval; - struct { - mmr_t cntr : 6; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t addr : 33; - mmr_t reserved_0 : 3; - } sh_mem_capture_hdr_s; -} sh_mem_capture_hdr_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_CONFIG" */ /* DQ directory config register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_config_u { mmr_t sh_md_dqlp_mmr_dir_config_regval; struct { @@ -24194,276 +13062,156 @@ mmr_t reserved_0 : 59; } sh_md_dqlp_mmr_dir_config_s; } sh_md_dqlp_mmr_dir_config_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_config_u { - mmr_t sh_md_dqlp_mmr_dir_config_regval; - struct { - mmr_t reserved_0 : 59; - mmr_t en_dirpois : 1; - mmr_t en_direcc : 1; - mmr_t sys_size : 3; - } sh_md_dqlp_mmr_dir_config_s; -} sh_md_dqlp_mmr_dir_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC0" */ /* node [63:0] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_presvec0_u { - mmr_t sh_md_dqlp_mmr_dir_presvec0_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_presvec0_s; -} sh_md_dqlp_mmr_dir_presvec0_u_t; -#else typedef union sh_md_dqlp_mmr_dir_presvec0_u { mmr_t sh_md_dqlp_mmr_dir_presvec0_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_presvec0_s; } sh_md_dqlp_mmr_dir_presvec0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC1" */ /* node [127:64] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_presvec1_u { - mmr_t sh_md_dqlp_mmr_dir_presvec1_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_presvec1_s; -} sh_md_dqlp_mmr_dir_presvec1_u_t; -#else typedef union sh_md_dqlp_mmr_dir_presvec1_u { mmr_t sh_md_dqlp_mmr_dir_presvec1_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_presvec1_s; } sh_md_dqlp_mmr_dir_presvec1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC2" */ /* node [191:128] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_presvec2_u { - mmr_t sh_md_dqlp_mmr_dir_presvec2_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_presvec2_s; -} sh_md_dqlp_mmr_dir_presvec2_u_t; -#else typedef union sh_md_dqlp_mmr_dir_presvec2_u { mmr_t sh_md_dqlp_mmr_dir_presvec2_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_presvec2_s; } sh_md_dqlp_mmr_dir_presvec2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRESVEC3" */ /* node [255:192] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_presvec3_u { - mmr_t sh_md_dqlp_mmr_dir_presvec3_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_presvec3_s; -} sh_md_dqlp_mmr_dir_presvec3_u_t; -#else typedef union sh_md_dqlp_mmr_dir_presvec3_u { mmr_t sh_md_dqlp_mmr_dir_presvec3_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_presvec3_s; } sh_md_dqlp_mmr_dir_presvec3_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC0" */ /* local vector for acc=0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_locvec0_u { mmr_t sh_md_dqlp_mmr_dir_locvec0_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec0_s; } sh_md_dqlp_mmr_dir_locvec0_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_locvec0_u { - mmr_t sh_md_dqlp_mmr_dir_locvec0_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec0_s; -} sh_md_dqlp_mmr_dir_locvec0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC1" */ /* local vector for acc=1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_locvec1_u { - mmr_t sh_md_dqlp_mmr_dir_locvec1_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec1_s; -} sh_md_dqlp_mmr_dir_locvec1_u_t; -#else typedef union sh_md_dqlp_mmr_dir_locvec1_u { mmr_t sh_md_dqlp_mmr_dir_locvec1_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec1_s; } sh_md_dqlp_mmr_dir_locvec1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC2" */ /* local vector for acc=2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_locvec2_u { - mmr_t sh_md_dqlp_mmr_dir_locvec2_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec2_s; -} sh_md_dqlp_mmr_dir_locvec2_u_t; -#else typedef union sh_md_dqlp_mmr_dir_locvec2_u { mmr_t sh_md_dqlp_mmr_dir_locvec2_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec2_s; } sh_md_dqlp_mmr_dir_locvec2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC3" */ /* local vector for acc=3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_locvec3_u { - mmr_t sh_md_dqlp_mmr_dir_locvec3_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec3_s; -} sh_md_dqlp_mmr_dir_locvec3_u_t; -#else typedef union sh_md_dqlp_mmr_dir_locvec3_u { mmr_t sh_md_dqlp_mmr_dir_locvec3_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec3_s; } sh_md_dqlp_mmr_dir_locvec3_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC4" */ /* local vector for acc=4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_locvec4_u { - mmr_t sh_md_dqlp_mmr_dir_locvec4_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec4_s; -} sh_md_dqlp_mmr_dir_locvec4_u_t; -#else typedef union sh_md_dqlp_mmr_dir_locvec4_u { mmr_t sh_md_dqlp_mmr_dir_locvec4_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec4_s; } sh_md_dqlp_mmr_dir_locvec4_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC5" */ /* local vector for acc=5 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_locvec5_u { - mmr_t sh_md_dqlp_mmr_dir_locvec5_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec5_s; -} sh_md_dqlp_mmr_dir_locvec5_u_t; -#else typedef union sh_md_dqlp_mmr_dir_locvec5_u { mmr_t sh_md_dqlp_mmr_dir_locvec5_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec5_s; } sh_md_dqlp_mmr_dir_locvec5_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC6" */ /* local vector for acc=6 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqlp_mmr_dir_locvec6_u { - mmr_t sh_md_dqlp_mmr_dir_locvec6_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec6_s; -} sh_md_dqlp_mmr_dir_locvec6_u_t; -#else typedef union sh_md_dqlp_mmr_dir_locvec6_u { mmr_t sh_md_dqlp_mmr_dir_locvec6_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec6_s; } sh_md_dqlp_mmr_dir_locvec6_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_LOCVEC7" */ /* local vector for acc=7 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_locvec7_u { mmr_t sh_md_dqlp_mmr_dir_locvec7_regval; struct { mmr_t vec : 64; } sh_md_dqlp_mmr_dir_locvec7_s; } sh_md_dqlp_mmr_dir_locvec7_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_locvec7_u { - mmr_t sh_md_dqlp_mmr_dir_locvec7_regval; - struct { - mmr_t vec : 64; - } sh_md_dqlp_mmr_dir_locvec7_s; -} sh_md_dqlp_mmr_dir_locvec7_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ /* privilege vector for acc=0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec0_u { mmr_t sh_md_dqlp_mmr_dir_privec0_regval; struct { @@ -24472,23 +13220,12 @@ mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec0_s; } sh_md_dqlp_mmr_dir_privec0_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec0_u { - mmr_t sh_md_dqlp_mmr_dir_privec0_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec0_s; -} sh_md_dqlp_mmr_dir_privec0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC1" */ /* privilege vector for acc=1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec1_u { mmr_t sh_md_dqlp_mmr_dir_privec1_regval; struct { @@ -24497,23 +13234,12 @@ mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec1_s; } sh_md_dqlp_mmr_dir_privec1_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec1_u { - mmr_t sh_md_dqlp_mmr_dir_privec1_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec1_s; -} sh_md_dqlp_mmr_dir_privec1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC2" */ /* privilege vector for acc=2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec2_u { mmr_t sh_md_dqlp_mmr_dir_privec2_regval; struct { @@ -24522,23 +13248,12 @@ mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec2_s; } sh_md_dqlp_mmr_dir_privec2_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec2_u { - mmr_t sh_md_dqlp_mmr_dir_privec2_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec2_s; -} sh_md_dqlp_mmr_dir_privec2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC3" */ /* privilege vector for acc=3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec3_u { mmr_t sh_md_dqlp_mmr_dir_privec3_regval; struct { @@ -24547,23 +13262,12 @@ mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec3_s; } sh_md_dqlp_mmr_dir_privec3_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec3_u { - mmr_t sh_md_dqlp_mmr_dir_privec3_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec3_s; -} sh_md_dqlp_mmr_dir_privec3_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC4" */ /* privilege vector for acc=4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec4_u { mmr_t sh_md_dqlp_mmr_dir_privec4_regval; struct { @@ -24572,23 +13276,12 @@ mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec4_s; } sh_md_dqlp_mmr_dir_privec4_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec4_u { - mmr_t sh_md_dqlp_mmr_dir_privec4_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec4_s; -} sh_md_dqlp_mmr_dir_privec4_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC5" */ /* privilege vector for acc=5 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec5_u { mmr_t sh_md_dqlp_mmr_dir_privec5_regval; struct { @@ -24597,23 +13290,12 @@ mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec5_s; } sh_md_dqlp_mmr_dir_privec5_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec5_u { - mmr_t sh_md_dqlp_mmr_dir_privec5_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec5_s; -} sh_md_dqlp_mmr_dir_privec5_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC6" */ /* privilege vector for acc=6 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec6_u { mmr_t sh_md_dqlp_mmr_dir_privec6_regval; struct { @@ -24622,23 +13304,12 @@ mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec6_s; } sh_md_dqlp_mmr_dir_privec6_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec6_u { - mmr_t sh_md_dqlp_mmr_dir_privec6_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec6_s; -} sh_md_dqlp_mmr_dir_privec6_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC7" */ /* privilege vector for acc=7 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_privec7_u { mmr_t sh_md_dqlp_mmr_dir_privec7_regval; struct { @@ -24647,23 +13318,12 @@ mmr_t reserved_0 : 36; } sh_md_dqlp_mmr_dir_privec7_s; } sh_md_dqlp_mmr_dir_privec7_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_privec7_u { - mmr_t sh_md_dqlp_mmr_dir_privec7_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqlp_mmr_dir_privec7_s; -} sh_md_dqlp_mmr_dir_privec7_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_TIMER" */ /* MD SXRO timer */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_timer_u { mmr_t sh_md_dqlp_mmr_dir_timer_regval; struct { @@ -24673,24 +13333,12 @@ mmr_t reserved_0 : 42; } sh_md_dqlp_mmr_dir_timer_s; } sh_md_dqlp_mmr_dir_timer_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_timer_u { - mmr_t sh_md_dqlp_mmr_dir_timer_regval; - struct { - mmr_t reserved_0 : 42; - mmr_t timer_cur : 9; - mmr_t timer_en : 1; - mmr_t timer_div : 12; - } sh_md_dqlp_mmr_dir_timer_s; -} sh_md_dqlp_mmr_dir_timer_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY" */ /* directory pio write data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_piowd_dir_entry_u { mmr_t sh_md_dqlp_mmr_piowd_dir_entry_regval; struct { @@ -24701,25 +13349,12 @@ mmr_t reserved_0 : 6; } sh_md_dqlp_mmr_piowd_dir_entry_s; } sh_md_dqlp_mmr_piowd_dir_entry_u_t; -#else -typedef union sh_md_dqlp_mmr_piowd_dir_entry_u { - mmr_t sh_md_dqlp_mmr_piowd_dir_entry_regval; - struct { - mmr_t reserved_0 : 6; - mmr_t acc : 3; - mmr_t pri : 3; - mmr_t dirb : 26; - mmr_t dira : 26; - } sh_md_dqlp_mmr_piowd_dir_entry_s; -} sh_md_dqlp_mmr_piowd_dir_entry_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ECC" */ /* directory ecc register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_piowd_dir_ecc_u { mmr_t sh_md_dqlp_mmr_piowd_dir_ecc_regval; struct { @@ -24728,23 +13363,12 @@ mmr_t reserved_0 : 50; } sh_md_dqlp_mmr_piowd_dir_ecc_s; } sh_md_dqlp_mmr_piowd_dir_ecc_u_t; -#else -typedef union sh_md_dqlp_mmr_piowd_dir_ecc_u { - mmr_t sh_md_dqlp_mmr_piowd_dir_ecc_regval; - struct { - mmr_t reserved_0 : 50; - mmr_t eccb : 7; - mmr_t ecca : 7; - } sh_md_dqlp_mmr_piowd_dir_ecc_s; -} sh_md_dqlp_mmr_piowd_dir_ecc_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY" */ /* x directory pio read data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xpiord_xdir_entry_u { mmr_t sh_md_dqlp_mmr_xpiord_xdir_entry_regval; struct { @@ -24757,27 +13381,12 @@ mmr_t reserved_0 : 4; } sh_md_dqlp_mmr_xpiord_xdir_entry_s; } sh_md_dqlp_mmr_xpiord_xdir_entry_u_t; -#else -typedef union sh_md_dqlp_mmr_xpiord_xdir_entry_u { - mmr_t sh_md_dqlp_mmr_xpiord_xdir_entry_regval; - struct { - mmr_t reserved_0 : 4; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t acc : 3; - mmr_t pri : 3; - mmr_t dirb : 26; - mmr_t dira : 26; - } sh_md_dqlp_mmr_xpiord_xdir_entry_s; -} sh_md_dqlp_mmr_xpiord_xdir_entry_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ECC" */ /* x directory ecc */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xpiord_xdir_ecc_u { mmr_t sh_md_dqlp_mmr_xpiord_xdir_ecc_regval; struct { @@ -24786,23 +13395,12 @@ mmr_t reserved_0 : 50; } sh_md_dqlp_mmr_xpiord_xdir_ecc_s; } sh_md_dqlp_mmr_xpiord_xdir_ecc_u_t; -#else -typedef union sh_md_dqlp_mmr_xpiord_xdir_ecc_u { - mmr_t sh_md_dqlp_mmr_xpiord_xdir_ecc_regval; - struct { - mmr_t reserved_0 : 50; - mmr_t eccb : 7; - mmr_t ecca : 7; - } sh_md_dqlp_mmr_xpiord_xdir_ecc_s; -} sh_md_dqlp_mmr_xpiord_xdir_ecc_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY" */ /* y directory pio read data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ypiord_ydir_entry_u { mmr_t sh_md_dqlp_mmr_ypiord_ydir_entry_regval; struct { @@ -24815,27 +13413,12 @@ mmr_t reserved_0 : 4; } sh_md_dqlp_mmr_ypiord_ydir_entry_s; } sh_md_dqlp_mmr_ypiord_ydir_entry_u_t; -#else -typedef union sh_md_dqlp_mmr_ypiord_ydir_entry_u { - mmr_t sh_md_dqlp_mmr_ypiord_ydir_entry_regval; - struct { - mmr_t reserved_0 : 4; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t acc : 3; - mmr_t pri : 3; - mmr_t dirb : 26; - mmr_t dira : 26; - } sh_md_dqlp_mmr_ypiord_ydir_entry_s; -} sh_md_dqlp_mmr_ypiord_ydir_entry_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ECC" */ /* y directory ecc */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ypiord_ydir_ecc_u { mmr_t sh_md_dqlp_mmr_ypiord_ydir_ecc_regval; struct { @@ -24844,23 +13427,12 @@ mmr_t reserved_0 : 50; } sh_md_dqlp_mmr_ypiord_ydir_ecc_s; } sh_md_dqlp_mmr_ypiord_ydir_ecc_u_t; -#else -typedef union sh_md_dqlp_mmr_ypiord_ydir_ecc_u { - mmr_t sh_md_dqlp_mmr_ypiord_ydir_ecc_regval; - struct { - mmr_t reserved_0 : 50; - mmr_t eccb : 7; - mmr_t ecca : 7; - } sh_md_dqlp_mmr_ypiord_ydir_ecc_s; -} sh_md_dqlp_mmr_ypiord_ydir_ecc_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XCERR1" */ /* correctable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xcerr1_u { mmr_t sh_md_dqlp_mmr_xcerr1_regval; struct { @@ -24871,25 +13443,12 @@ mmr_t reserved_0 : 25; } sh_md_dqlp_mmr_xcerr1_s; } sh_md_dqlp_mmr_xcerr1_u_t; -#else -typedef union sh_md_dqlp_mmr_xcerr1_u { - mmr_t sh_md_dqlp_mmr_xcerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqlp_mmr_xcerr1_s; -} sh_md_dqlp_mmr_xcerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XCERR2" */ /* correctable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xcerr2_u { mmr_t sh_md_dqlp_mmr_xcerr2_regval; struct { @@ -24899,24 +13458,12 @@ mmr_t reserved_0 : 26; } sh_md_dqlp_mmr_xcerr2_s; } sh_md_dqlp_mmr_xcerr2_u_t; -#else -typedef union sh_md_dqlp_mmr_xcerr2_u { - mmr_t sh_md_dqlp_mmr_xcerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqlp_mmr_xcerr2_s; -} sh_md_dqlp_mmr_xcerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XUERR1" */ /* uncorrectable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xuerr1_u { mmr_t sh_md_dqlp_mmr_xuerr1_regval; struct { @@ -24927,25 +13474,12 @@ mmr_t reserved_0 : 25; } sh_md_dqlp_mmr_xuerr1_s; } sh_md_dqlp_mmr_xuerr1_u_t; -#else -typedef union sh_md_dqlp_mmr_xuerr1_u { - mmr_t sh_md_dqlp_mmr_xuerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqlp_mmr_xuerr1_s; -} sh_md_dqlp_mmr_xuerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XUERR2" */ /* uncorrectable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xuerr2_u { mmr_t sh_md_dqlp_mmr_xuerr2_regval; struct { @@ -24955,24 +13489,12 @@ mmr_t reserved_0 : 26; } sh_md_dqlp_mmr_xuerr2_s; } sh_md_dqlp_mmr_xuerr2_u_t; -#else -typedef union sh_md_dqlp_mmr_xuerr2_u { - mmr_t sh_md_dqlp_mmr_xuerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqlp_mmr_xuerr2_s; -} sh_md_dqlp_mmr_xuerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XPERR" */ /* protocol error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xperr_u { mmr_t sh_md_dqlp_mmr_xperr_regval; struct { @@ -24990,32 +13512,12 @@ mmr_t reserved_0 : 1; } sh_md_dqlp_mmr_xperr_s; } sh_md_dqlp_mmr_xperr_u_t; -#else -typedef union sh_md_dqlp_mmr_xperr_u { - mmr_t sh_md_dqlp_mmr_xperr_regval; - struct { - mmr_t reserved_0 : 1; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t mybit : 8; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t priv : 1; - mmr_t prige : 1; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t dir : 26; - } sh_md_dqlp_mmr_xperr_s; -} sh_md_dqlp_mmr_xperr_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YCERR1" */ /* correctable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ycerr1_u { mmr_t sh_md_dqlp_mmr_ycerr1_regval; struct { @@ -25026,25 +13528,12 @@ mmr_t reserved_0 : 25; } sh_md_dqlp_mmr_ycerr1_s; } sh_md_dqlp_mmr_ycerr1_u_t; -#else -typedef union sh_md_dqlp_mmr_ycerr1_u { - mmr_t sh_md_dqlp_mmr_ycerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqlp_mmr_ycerr1_s; -} sh_md_dqlp_mmr_ycerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YCERR2" */ /* correctable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ycerr2_u { mmr_t sh_md_dqlp_mmr_ycerr2_regval; struct { @@ -25054,24 +13543,12 @@ mmr_t reserved_0 : 26; } sh_md_dqlp_mmr_ycerr2_s; } sh_md_dqlp_mmr_ycerr2_u_t; -#else -typedef union sh_md_dqlp_mmr_ycerr2_u { - mmr_t sh_md_dqlp_mmr_ycerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqlp_mmr_ycerr2_s; -} sh_md_dqlp_mmr_ycerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YUERR1" */ /* uncorrectable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_yuerr1_u { mmr_t sh_md_dqlp_mmr_yuerr1_regval; struct { @@ -25082,25 +13559,12 @@ mmr_t reserved_0 : 25; } sh_md_dqlp_mmr_yuerr1_s; } sh_md_dqlp_mmr_yuerr1_u_t; -#else -typedef union sh_md_dqlp_mmr_yuerr1_u { - mmr_t sh_md_dqlp_mmr_yuerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqlp_mmr_yuerr1_s; -} sh_md_dqlp_mmr_yuerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YUERR2" */ /* uncorrectable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_yuerr2_u { mmr_t sh_md_dqlp_mmr_yuerr2_regval; struct { @@ -25110,24 +13574,12 @@ mmr_t reserved_0 : 26; } sh_md_dqlp_mmr_yuerr2_s; } sh_md_dqlp_mmr_yuerr2_u_t; -#else -typedef union sh_md_dqlp_mmr_yuerr2_u { - mmr_t sh_md_dqlp_mmr_yuerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqlp_mmr_yuerr2_s; -} sh_md_dqlp_mmr_yuerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YPERR" */ /* protocol error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_yperr_u { mmr_t sh_md_dqlp_mmr_yperr_regval; struct { @@ -25145,32 +13597,12 @@ mmr_t reserved_0 : 1; } sh_md_dqlp_mmr_yperr_s; } sh_md_dqlp_mmr_yperr_u_t; -#else -typedef union sh_md_dqlp_mmr_yperr_u { - mmr_t sh_md_dqlp_mmr_yperr_regval; - struct { - mmr_t reserved_0 : 1; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t mybit : 8; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t priv : 1; - mmr_t prige : 1; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t dir : 26; - } sh_md_dqlp_mmr_yperr_s; -} sh_md_dqlp_mmr_yperr_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_CMDTRIG" */ /* cmd triggers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_cmdtrig_u { mmr_t sh_md_dqlp_mmr_dir_cmdtrig_regval; struct { @@ -25181,25 +13613,12 @@ mmr_t reserved_0 : 32; } sh_md_dqlp_mmr_dir_cmdtrig_s; } sh_md_dqlp_mmr_dir_cmdtrig_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_cmdtrig_u { - mmr_t sh_md_dqlp_mmr_dir_cmdtrig_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t cmd3 : 8; - mmr_t cmd2 : 8; - mmr_t cmd1 : 8; - mmr_t cmd0 : 8; - } sh_md_dqlp_mmr_dir_cmdtrig_s; -} sh_md_dqlp_mmr_dir_cmdtrig_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_TBLTRIG" */ /* dir table trigger */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_tbltrig_u { mmr_t sh_md_dqlp_mmr_dir_tbltrig_regval; struct { @@ -25212,27 +13631,12 @@ mmr_t reserved_0 : 22; } sh_md_dqlp_mmr_dir_tbltrig_s; } sh_md_dqlp_mmr_dir_tbltrig_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_tbltrig_u { - mmr_t sh_md_dqlp_mmr_dir_tbltrig_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t mybit : 8; - mmr_t dirst : 9; - mmr_t prige : 1; - mmr_t acc : 2; - mmr_t cmd : 8; - mmr_t src : 14; - } sh_md_dqlp_mmr_dir_tbltrig_s; -} sh_md_dqlp_mmr_dir_tbltrig_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_DIR_TBLMASK" */ /* dir table trigger mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_dir_tblmask_u { mmr_t sh_md_dqlp_mmr_dir_tblmask_regval; struct { @@ -25245,27 +13649,12 @@ mmr_t reserved_0 : 22; } sh_md_dqlp_mmr_dir_tblmask_s; } sh_md_dqlp_mmr_dir_tblmask_u_t; -#else -typedef union sh_md_dqlp_mmr_dir_tblmask_u { - mmr_t sh_md_dqlp_mmr_dir_tblmask_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t mybit : 8; - mmr_t dirst : 9; - mmr_t prige : 1; - mmr_t acc : 2; - mmr_t cmd : 8; - mmr_t src : 14; - } sh_md_dqlp_mmr_dir_tblmask_s; -} sh_md_dqlp_mmr_dir_tblmask_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xbist_h_u { mmr_t sh_md_dqlp_mmr_xbist_h_regval; struct { @@ -25277,26 +13666,12 @@ mmr_t reserved_1 : 21; } sh_md_dqlp_mmr_xbist_h_s; } sh_md_dqlp_mmr_xbist_h_u_t; -#else -typedef union sh_md_dqlp_mmr_xbist_h_u { - mmr_t sh_md_dqlp_mmr_xbist_h_regval; - struct { - mmr_t reserved_1 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_xbist_h_s; -} sh_md_dqlp_mmr_xbist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xbist_l_u { mmr_t sh_md_dqlp_mmr_xbist_l_regval; struct { @@ -25307,25 +13682,12 @@ mmr_t reserved_1 : 22; } sh_md_dqlp_mmr_xbist_l_s; } sh_md_dqlp_mmr_xbist_l_u_t; -#else -typedef union sh_md_dqlp_mmr_xbist_l_u { - mmr_t sh_md_dqlp_mmr_xbist_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_xbist_l_s; -} sh_md_dqlp_mmr_xbist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xbist_err_h_u { mmr_t sh_md_dqlp_mmr_xbist_err_h_regval; struct { @@ -25336,25 +13698,12 @@ mmr_t reserved_1 : 22; } sh_md_dqlp_mmr_xbist_err_h_s; } sh_md_dqlp_mmr_xbist_err_h_u_t; -#else -typedef union sh_md_dqlp_mmr_xbist_err_h_u { - mmr_t sh_md_dqlp_mmr_xbist_err_h_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_xbist_err_h_s; -} sh_md_dqlp_mmr_xbist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_XBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_xbist_err_l_u { mmr_t sh_md_dqlp_mmr_xbist_err_l_regval; struct { @@ -25365,25 +13714,12 @@ mmr_t reserved_1 : 22; } sh_md_dqlp_mmr_xbist_err_l_s; } sh_md_dqlp_mmr_xbist_err_l_u_t; -#else -typedef union sh_md_dqlp_mmr_xbist_err_l_u { - mmr_t sh_md_dqlp_mmr_xbist_err_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_xbist_err_l_s; -} sh_md_dqlp_mmr_xbist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ybist_h_u { mmr_t sh_md_dqlp_mmr_ybist_h_regval; struct { @@ -25395,26 +13731,12 @@ mmr_t reserved_1 : 21; } sh_md_dqlp_mmr_ybist_h_s; } sh_md_dqlp_mmr_ybist_h_u_t; -#else -typedef union sh_md_dqlp_mmr_ybist_h_u { - mmr_t sh_md_dqlp_mmr_ybist_h_regval; - struct { - mmr_t reserved_1 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_ybist_h_s; -} sh_md_dqlp_mmr_ybist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ybist_l_u { mmr_t sh_md_dqlp_mmr_ybist_l_regval; struct { @@ -25425,25 +13747,12 @@ mmr_t reserved_1 : 22; } sh_md_dqlp_mmr_ybist_l_s; } sh_md_dqlp_mmr_ybist_l_u_t; -#else -typedef union sh_md_dqlp_mmr_ybist_l_u { - mmr_t sh_md_dqlp_mmr_ybist_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_ybist_l_s; -} sh_md_dqlp_mmr_ybist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ybist_err_h_u { mmr_t sh_md_dqlp_mmr_ybist_err_h_regval; struct { @@ -25454,25 +13763,12 @@ mmr_t reserved_1 : 22; } sh_md_dqlp_mmr_ybist_err_h_s; } sh_md_dqlp_mmr_ybist_err_h_u_t; -#else -typedef union sh_md_dqlp_mmr_ybist_err_h_u { - mmr_t sh_md_dqlp_mmr_ybist_err_h_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_ybist_err_h_s; -} sh_md_dqlp_mmr_ybist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLP_MMR_YBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqlp_mmr_ybist_err_l_u { mmr_t sh_md_dqlp_mmr_ybist_err_l_regval; struct { @@ -25483,25 +13779,12 @@ mmr_t reserved_1 : 22; } sh_md_dqlp_mmr_ybist_err_l_s; } sh_md_dqlp_mmr_ybist_err_l_u_t; -#else -typedef union sh_md_dqlp_mmr_ybist_err_l_u { - mmr_t sh_md_dqlp_mmr_ybist_err_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqlp_mmr_ybist_err_l_s; -} sh_md_dqlp_mmr_ybist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_XBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_xbist_h_u { mmr_t sh_md_dqls_mmr_xbist_h_regval; struct { @@ -25512,25 +13795,12 @@ mmr_t reserved_0 : 21; } sh_md_dqls_mmr_xbist_h_s; } sh_md_dqls_mmr_xbist_h_u_t; -#else -typedef union sh_md_dqls_mmr_xbist_h_u { - mmr_t sh_md_dqls_mmr_xbist_h_regval; - struct { - mmr_t reserved_0 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_xbist_h_s; -} sh_md_dqls_mmr_xbist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_XBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_xbist_l_u { mmr_t sh_md_dqls_mmr_xbist_l_regval; struct { @@ -25540,24 +13810,12 @@ mmr_t reserved_0 : 22; } sh_md_dqls_mmr_xbist_l_s; } sh_md_dqls_mmr_xbist_l_u_t; -#else -typedef union sh_md_dqls_mmr_xbist_l_u { - mmr_t sh_md_dqls_mmr_xbist_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_xbist_l_s; -} sh_md_dqls_mmr_xbist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_XBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_xbist_err_h_u { mmr_t sh_md_dqls_mmr_xbist_err_h_regval; struct { @@ -25567,24 +13825,12 @@ mmr_t reserved_0 : 22; } sh_md_dqls_mmr_xbist_err_h_s; } sh_md_dqls_mmr_xbist_err_h_u_t; -#else -typedef union sh_md_dqls_mmr_xbist_err_h_u { - mmr_t sh_md_dqls_mmr_xbist_err_h_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_xbist_err_h_s; -} sh_md_dqls_mmr_xbist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_XBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_xbist_err_l_u { mmr_t sh_md_dqls_mmr_xbist_err_l_regval; struct { @@ -25594,24 +13840,12 @@ mmr_t reserved_0 : 22; } sh_md_dqls_mmr_xbist_err_l_s; } sh_md_dqls_mmr_xbist_err_l_u_t; -#else -typedef union sh_md_dqls_mmr_xbist_err_l_u { - mmr_t sh_md_dqls_mmr_xbist_err_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_xbist_err_l_s; -} sh_md_dqls_mmr_xbist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_YBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_ybist_h_u { mmr_t sh_md_dqls_mmr_ybist_h_regval; struct { @@ -25622,25 +13856,12 @@ mmr_t reserved_0 : 21; } sh_md_dqls_mmr_ybist_h_s; } sh_md_dqls_mmr_ybist_h_u_t; -#else -typedef union sh_md_dqls_mmr_ybist_h_u { - mmr_t sh_md_dqls_mmr_ybist_h_regval; - struct { - mmr_t reserved_0 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_ybist_h_s; -} sh_md_dqls_mmr_ybist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_YBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_ybist_l_u { mmr_t sh_md_dqls_mmr_ybist_l_regval; struct { @@ -25650,24 +13871,12 @@ mmr_t reserved_0 : 22; } sh_md_dqls_mmr_ybist_l_s; } sh_md_dqls_mmr_ybist_l_u_t; -#else -typedef union sh_md_dqls_mmr_ybist_l_u { - mmr_t sh_md_dqls_mmr_ybist_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_ybist_l_s; -} sh_md_dqls_mmr_ybist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_YBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_ybist_err_h_u { mmr_t sh_md_dqls_mmr_ybist_err_h_regval; struct { @@ -25677,24 +13886,12 @@ mmr_t reserved_0 : 22; } sh_md_dqls_mmr_ybist_err_h_s; } sh_md_dqls_mmr_ybist_err_h_u_t; -#else -typedef union sh_md_dqls_mmr_ybist_err_h_u { - mmr_t sh_md_dqls_mmr_ybist_err_h_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_ybist_err_h_s; -} sh_md_dqls_mmr_ybist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_YBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_ybist_err_l_u { mmr_t sh_md_dqls_mmr_ybist_err_l_regval; struct { @@ -25704,24 +13901,12 @@ mmr_t reserved_0 : 22; } sh_md_dqls_mmr_ybist_err_l_s; } sh_md_dqls_mmr_ybist_err_l_u_t; -#else -typedef union sh_md_dqls_mmr_ybist_err_l_u { - mmr_t sh_md_dqls_mmr_ybist_err_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqls_mmr_ybist_err_l_s; -} sh_md_dqls_mmr_ybist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_JNR_DEBUG" */ /* joiner/fct debug configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_jnr_debug_u { mmr_t sh_md_dqls_mmr_jnr_debug_regval; struct { @@ -25730,23 +13915,12 @@ mmr_t reserved_0 : 62; } sh_md_dqls_mmr_jnr_debug_s; } sh_md_dqls_mmr_jnr_debug_u_t; -#else -typedef union sh_md_dqls_mmr_jnr_debug_u { - mmr_t sh_md_dqls_mmr_jnr_debug_regval; - struct { - mmr_t reserved_0 : 62; - mmr_t rw : 1; - mmr_t px : 1; - } sh_md_dqls_mmr_jnr_debug_s; -} sh_md_dqls_mmr_jnr_debug_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQLS_MMR_XAMOPW_ERR" */ /* amo/partial rmw ecc error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqls_mmr_xamopw_err_u { mmr_t sh_md_dqls_mmr_xamopw_err_regval; struct { @@ -25762,30 +13936,12 @@ mmr_t reserved_2 : 31; } sh_md_dqls_mmr_xamopw_err_s; } sh_md_dqls_mmr_xamopw_err_u_t; -#else -typedef union sh_md_dqls_mmr_xamopw_err_u { - mmr_t sh_md_dqls_mmr_xamopw_err_regval; - struct { - mmr_t reserved_2 : 31; - mmr_t arm : 1; - mmr_t reserved_1 : 6; - mmr_t runc : 1; - mmr_t rcor : 1; - mmr_t rsyn : 8; - mmr_t reserved_0 : 6; - mmr_t sunc : 1; - mmr_t scor : 1; - mmr_t ssyn : 8; - } sh_md_dqls_mmr_xamopw_err_s; -} sh_md_dqls_mmr_xamopw_err_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_CONFIG" */ /* DQ directory config register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_config_u { mmr_t sh_md_dqrp_mmr_dir_config_regval; struct { @@ -25795,276 +13951,156 @@ mmr_t reserved_0 : 59; } sh_md_dqrp_mmr_dir_config_s; } sh_md_dqrp_mmr_dir_config_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_config_u { - mmr_t sh_md_dqrp_mmr_dir_config_regval; - struct { - mmr_t reserved_0 : 59; - mmr_t en_dirpois : 1; - mmr_t en_direcc : 1; - mmr_t sys_size : 3; - } sh_md_dqrp_mmr_dir_config_s; -} sh_md_dqrp_mmr_dir_config_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC0" */ /* node [63:0] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqrp_mmr_dir_presvec0_u { - mmr_t sh_md_dqrp_mmr_dir_presvec0_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_presvec0_s; -} sh_md_dqrp_mmr_dir_presvec0_u_t; -#else typedef union sh_md_dqrp_mmr_dir_presvec0_u { mmr_t sh_md_dqrp_mmr_dir_presvec0_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_presvec0_s; } sh_md_dqrp_mmr_dir_presvec0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC1" */ /* node [127:64] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_presvec1_u { mmr_t sh_md_dqrp_mmr_dir_presvec1_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_presvec1_s; } sh_md_dqrp_mmr_dir_presvec1_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_presvec1_u { - mmr_t sh_md_dqrp_mmr_dir_presvec1_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_presvec1_s; -} sh_md_dqrp_mmr_dir_presvec1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC2" */ /* node [191:128] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqrp_mmr_dir_presvec2_u { - mmr_t sh_md_dqrp_mmr_dir_presvec2_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_presvec2_s; -} sh_md_dqrp_mmr_dir_presvec2_u_t; -#else typedef union sh_md_dqrp_mmr_dir_presvec2_u { mmr_t sh_md_dqrp_mmr_dir_presvec2_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_presvec2_s; } sh_md_dqrp_mmr_dir_presvec2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRESVEC3" */ /* node [255:192] presence bits */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqrp_mmr_dir_presvec3_u { - mmr_t sh_md_dqrp_mmr_dir_presvec3_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_presvec3_s; -} sh_md_dqrp_mmr_dir_presvec3_u_t; -#else typedef union sh_md_dqrp_mmr_dir_presvec3_u { mmr_t sh_md_dqrp_mmr_dir_presvec3_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_presvec3_s; } sh_md_dqrp_mmr_dir_presvec3_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC0" */ /* local vector for acc=0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqrp_mmr_dir_locvec0_u { - mmr_t sh_md_dqrp_mmr_dir_locvec0_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec0_s; -} sh_md_dqrp_mmr_dir_locvec0_u_t; -#else typedef union sh_md_dqrp_mmr_dir_locvec0_u { mmr_t sh_md_dqrp_mmr_dir_locvec0_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec0_s; } sh_md_dqrp_mmr_dir_locvec0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC1" */ /* local vector for acc=1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_locvec1_u { mmr_t sh_md_dqrp_mmr_dir_locvec1_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec1_s; } sh_md_dqrp_mmr_dir_locvec1_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_locvec1_u { - mmr_t sh_md_dqrp_mmr_dir_locvec1_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec1_s; -} sh_md_dqrp_mmr_dir_locvec1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC2" */ /* local vector for acc=2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_locvec2_u { mmr_t sh_md_dqrp_mmr_dir_locvec2_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec2_s; } sh_md_dqrp_mmr_dir_locvec2_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_locvec2_u { - mmr_t sh_md_dqrp_mmr_dir_locvec2_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec2_s; -} sh_md_dqrp_mmr_dir_locvec2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC3" */ /* local vector for acc=3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_locvec3_u { mmr_t sh_md_dqrp_mmr_dir_locvec3_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec3_s; } sh_md_dqrp_mmr_dir_locvec3_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_locvec3_u { - mmr_t sh_md_dqrp_mmr_dir_locvec3_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec3_s; -} sh_md_dqrp_mmr_dir_locvec3_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC4" */ /* local vector for acc=4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqrp_mmr_dir_locvec4_u { - mmr_t sh_md_dqrp_mmr_dir_locvec4_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec4_s; -} sh_md_dqrp_mmr_dir_locvec4_u_t; -#else typedef union sh_md_dqrp_mmr_dir_locvec4_u { mmr_t sh_md_dqrp_mmr_dir_locvec4_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec4_s; } sh_md_dqrp_mmr_dir_locvec4_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC5" */ /* local vector for acc=5 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqrp_mmr_dir_locvec5_u { - mmr_t sh_md_dqrp_mmr_dir_locvec5_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec5_s; -} sh_md_dqrp_mmr_dir_locvec5_u_t; -#else typedef union sh_md_dqrp_mmr_dir_locvec5_u { mmr_t sh_md_dqrp_mmr_dir_locvec5_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec5_s; } sh_md_dqrp_mmr_dir_locvec5_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC6" */ /* local vector for acc=6 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_locvec6_u { mmr_t sh_md_dqrp_mmr_dir_locvec6_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec6_s; } sh_md_dqrp_mmr_dir_locvec6_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_locvec6_u { - mmr_t sh_md_dqrp_mmr_dir_locvec6_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec6_s; -} sh_md_dqrp_mmr_dir_locvec6_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_LOCVEC7" */ /* local vector for acc=7 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN -typedef union sh_md_dqrp_mmr_dir_locvec7_u { - mmr_t sh_md_dqrp_mmr_dir_locvec7_regval; - struct { - mmr_t vec : 64; - } sh_md_dqrp_mmr_dir_locvec7_s; -} sh_md_dqrp_mmr_dir_locvec7_u_t; -#else typedef union sh_md_dqrp_mmr_dir_locvec7_u { mmr_t sh_md_dqrp_mmr_dir_locvec7_regval; struct { mmr_t vec : 64; } sh_md_dqrp_mmr_dir_locvec7_s; } sh_md_dqrp_mmr_dir_locvec7_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ /* privilege vector for acc=0 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec0_u { mmr_t sh_md_dqrp_mmr_dir_privec0_regval; struct { @@ -26073,23 +14109,12 @@ mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec0_s; } sh_md_dqrp_mmr_dir_privec0_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec0_u { - mmr_t sh_md_dqrp_mmr_dir_privec0_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec0_s; -} sh_md_dqrp_mmr_dir_privec0_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC1" */ /* privilege vector for acc=1 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec1_u { mmr_t sh_md_dqrp_mmr_dir_privec1_regval; struct { @@ -26098,23 +14123,12 @@ mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec1_s; } sh_md_dqrp_mmr_dir_privec1_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec1_u { - mmr_t sh_md_dqrp_mmr_dir_privec1_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec1_s; -} sh_md_dqrp_mmr_dir_privec1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC2" */ /* privilege vector for acc=2 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec2_u { mmr_t sh_md_dqrp_mmr_dir_privec2_regval; struct { @@ -26123,23 +14137,12 @@ mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec2_s; } sh_md_dqrp_mmr_dir_privec2_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec2_u { - mmr_t sh_md_dqrp_mmr_dir_privec2_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec2_s; -} sh_md_dqrp_mmr_dir_privec2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC3" */ /* privilege vector for acc=3 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec3_u { mmr_t sh_md_dqrp_mmr_dir_privec3_regval; struct { @@ -26148,23 +14151,12 @@ mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec3_s; } sh_md_dqrp_mmr_dir_privec3_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec3_u { - mmr_t sh_md_dqrp_mmr_dir_privec3_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec3_s; -} sh_md_dqrp_mmr_dir_privec3_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC4" */ /* privilege vector for acc=4 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec4_u { mmr_t sh_md_dqrp_mmr_dir_privec4_regval; struct { @@ -26173,23 +14165,12 @@ mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec4_s; } sh_md_dqrp_mmr_dir_privec4_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec4_u { - mmr_t sh_md_dqrp_mmr_dir_privec4_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec4_s; -} sh_md_dqrp_mmr_dir_privec4_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC5" */ /* privilege vector for acc=5 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec5_u { mmr_t sh_md_dqrp_mmr_dir_privec5_regval; struct { @@ -26198,23 +14179,12 @@ mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec5_s; } sh_md_dqrp_mmr_dir_privec5_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec5_u { - mmr_t sh_md_dqrp_mmr_dir_privec5_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec5_s; -} sh_md_dqrp_mmr_dir_privec5_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC6" */ /* privilege vector for acc=6 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec6_u { mmr_t sh_md_dqrp_mmr_dir_privec6_regval; struct { @@ -26223,23 +14193,12 @@ mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec6_s; } sh_md_dqrp_mmr_dir_privec6_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec6_u { - mmr_t sh_md_dqrp_mmr_dir_privec6_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec6_s; -} sh_md_dqrp_mmr_dir_privec6_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC7" */ /* privilege vector for acc=7 */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_privec7_u { mmr_t sh_md_dqrp_mmr_dir_privec7_regval; struct { @@ -26248,23 +14207,12 @@ mmr_t reserved_0 : 36; } sh_md_dqrp_mmr_dir_privec7_s; } sh_md_dqrp_mmr_dir_privec7_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_privec7_u { - mmr_t sh_md_dqrp_mmr_dir_privec7_regval; - struct { - mmr_t reserved_0 : 36; - mmr_t out : 14; - mmr_t in : 14; - } sh_md_dqrp_mmr_dir_privec7_s; -} sh_md_dqrp_mmr_dir_privec7_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_TIMER" */ /* MD SXRO timer */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_timer_u { mmr_t sh_md_dqrp_mmr_dir_timer_regval; struct { @@ -26274,24 +14222,12 @@ mmr_t reserved_0 : 42; } sh_md_dqrp_mmr_dir_timer_s; } sh_md_dqrp_mmr_dir_timer_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_timer_u { - mmr_t sh_md_dqrp_mmr_dir_timer_regval; - struct { - mmr_t reserved_0 : 42; - mmr_t timer_cur : 9; - mmr_t timer_en : 1; - mmr_t timer_div : 12; - } sh_md_dqrp_mmr_dir_timer_s; -} sh_md_dqrp_mmr_dir_timer_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY" */ /* directory pio write data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_piowd_dir_entry_u { mmr_t sh_md_dqrp_mmr_piowd_dir_entry_regval; struct { @@ -26302,25 +14238,12 @@ mmr_t reserved_0 : 6; } sh_md_dqrp_mmr_piowd_dir_entry_s; } sh_md_dqrp_mmr_piowd_dir_entry_u_t; -#else -typedef union sh_md_dqrp_mmr_piowd_dir_entry_u { - mmr_t sh_md_dqrp_mmr_piowd_dir_entry_regval; - struct { - mmr_t reserved_0 : 6; - mmr_t acc : 3; - mmr_t pri : 3; - mmr_t dirb : 26; - mmr_t dira : 26; - } sh_md_dqrp_mmr_piowd_dir_entry_s; -} sh_md_dqrp_mmr_piowd_dir_entry_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ECC" */ /* directory ecc register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_piowd_dir_ecc_u { mmr_t sh_md_dqrp_mmr_piowd_dir_ecc_regval; struct { @@ -26329,23 +14252,12 @@ mmr_t reserved_0 : 50; } sh_md_dqrp_mmr_piowd_dir_ecc_s; } sh_md_dqrp_mmr_piowd_dir_ecc_u_t; -#else -typedef union sh_md_dqrp_mmr_piowd_dir_ecc_u { - mmr_t sh_md_dqrp_mmr_piowd_dir_ecc_regval; - struct { - mmr_t reserved_0 : 50; - mmr_t eccb : 7; - mmr_t ecca : 7; - } sh_md_dqrp_mmr_piowd_dir_ecc_s; -} sh_md_dqrp_mmr_piowd_dir_ecc_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY" */ /* x directory pio read data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xpiord_xdir_entry_u { mmr_t sh_md_dqrp_mmr_xpiord_xdir_entry_regval; struct { @@ -26358,27 +14270,12 @@ mmr_t reserved_0 : 4; } sh_md_dqrp_mmr_xpiord_xdir_entry_s; } sh_md_dqrp_mmr_xpiord_xdir_entry_u_t; -#else -typedef union sh_md_dqrp_mmr_xpiord_xdir_entry_u { - mmr_t sh_md_dqrp_mmr_xpiord_xdir_entry_regval; - struct { - mmr_t reserved_0 : 4; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t acc : 3; - mmr_t pri : 3; - mmr_t dirb : 26; - mmr_t dira : 26; - } sh_md_dqrp_mmr_xpiord_xdir_entry_s; -} sh_md_dqrp_mmr_xpiord_xdir_entry_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ECC" */ /* x directory ecc */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xpiord_xdir_ecc_u { mmr_t sh_md_dqrp_mmr_xpiord_xdir_ecc_regval; struct { @@ -26387,23 +14284,12 @@ mmr_t reserved_0 : 50; } sh_md_dqrp_mmr_xpiord_xdir_ecc_s; } sh_md_dqrp_mmr_xpiord_xdir_ecc_u_t; -#else -typedef union sh_md_dqrp_mmr_xpiord_xdir_ecc_u { - mmr_t sh_md_dqrp_mmr_xpiord_xdir_ecc_regval; - struct { - mmr_t reserved_0 : 50; - mmr_t eccb : 7; - mmr_t ecca : 7; - } sh_md_dqrp_mmr_xpiord_xdir_ecc_s; -} sh_md_dqrp_mmr_xpiord_xdir_ecc_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY" */ /* y directory pio read data */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ypiord_ydir_entry_u { mmr_t sh_md_dqrp_mmr_ypiord_ydir_entry_regval; struct { @@ -26416,27 +14302,12 @@ mmr_t reserved_0 : 4; } sh_md_dqrp_mmr_ypiord_ydir_entry_s; } sh_md_dqrp_mmr_ypiord_ydir_entry_u_t; -#else -typedef union sh_md_dqrp_mmr_ypiord_ydir_entry_u { - mmr_t sh_md_dqrp_mmr_ypiord_ydir_entry_regval; - struct { - mmr_t reserved_0 : 4; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t acc : 3; - mmr_t pri : 3; - mmr_t dirb : 26; - mmr_t dira : 26; - } sh_md_dqrp_mmr_ypiord_ydir_entry_s; -} sh_md_dqrp_mmr_ypiord_ydir_entry_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ECC" */ /* y directory ecc */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ypiord_ydir_ecc_u { mmr_t sh_md_dqrp_mmr_ypiord_ydir_ecc_regval; struct { @@ -26445,23 +14316,12 @@ mmr_t reserved_0 : 50; } sh_md_dqrp_mmr_ypiord_ydir_ecc_s; } sh_md_dqrp_mmr_ypiord_ydir_ecc_u_t; -#else -typedef union sh_md_dqrp_mmr_ypiord_ydir_ecc_u { - mmr_t sh_md_dqrp_mmr_ypiord_ydir_ecc_regval; - struct { - mmr_t reserved_0 : 50; - mmr_t eccb : 7; - mmr_t ecca : 7; - } sh_md_dqrp_mmr_ypiord_ydir_ecc_s; -} sh_md_dqrp_mmr_ypiord_ydir_ecc_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XCERR1" */ /* correctable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xcerr1_u { mmr_t sh_md_dqrp_mmr_xcerr1_regval; struct { @@ -26472,25 +14332,12 @@ mmr_t reserved_0 : 25; } sh_md_dqrp_mmr_xcerr1_s; } sh_md_dqrp_mmr_xcerr1_u_t; -#else -typedef union sh_md_dqrp_mmr_xcerr1_u { - mmr_t sh_md_dqrp_mmr_xcerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqrp_mmr_xcerr1_s; -} sh_md_dqrp_mmr_xcerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XCERR2" */ /* correctable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xcerr2_u { mmr_t sh_md_dqrp_mmr_xcerr2_regval; struct { @@ -26500,24 +14347,12 @@ mmr_t reserved_0 : 26; } sh_md_dqrp_mmr_xcerr2_s; } sh_md_dqrp_mmr_xcerr2_u_t; -#else -typedef union sh_md_dqrp_mmr_xcerr2_u { - mmr_t sh_md_dqrp_mmr_xcerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqrp_mmr_xcerr2_s; -} sh_md_dqrp_mmr_xcerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XUERR1" */ /* uncorrectable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xuerr1_u { mmr_t sh_md_dqrp_mmr_xuerr1_regval; struct { @@ -26528,25 +14363,12 @@ mmr_t reserved_0 : 25; } sh_md_dqrp_mmr_xuerr1_s; } sh_md_dqrp_mmr_xuerr1_u_t; -#else -typedef union sh_md_dqrp_mmr_xuerr1_u { - mmr_t sh_md_dqrp_mmr_xuerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqrp_mmr_xuerr1_s; -} sh_md_dqrp_mmr_xuerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XUERR2" */ /* uncorrectable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xuerr2_u { mmr_t sh_md_dqrp_mmr_xuerr2_regval; struct { @@ -26556,24 +14378,12 @@ mmr_t reserved_0 : 26; } sh_md_dqrp_mmr_xuerr2_s; } sh_md_dqrp_mmr_xuerr2_u_t; -#else -typedef union sh_md_dqrp_mmr_xuerr2_u { - mmr_t sh_md_dqrp_mmr_xuerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqrp_mmr_xuerr2_s; -} sh_md_dqrp_mmr_xuerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XPERR" */ /* protocol error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xperr_u { mmr_t sh_md_dqrp_mmr_xperr_regval; struct { @@ -26591,32 +14401,12 @@ mmr_t reserved_0 : 1; } sh_md_dqrp_mmr_xperr_s; } sh_md_dqrp_mmr_xperr_u_t; -#else -typedef union sh_md_dqrp_mmr_xperr_u { - mmr_t sh_md_dqrp_mmr_xperr_regval; - struct { - mmr_t reserved_0 : 1; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t mybit : 8; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t priv : 1; - mmr_t prige : 1; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t dir : 26; - } sh_md_dqrp_mmr_xperr_s; -} sh_md_dqrp_mmr_xperr_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YCERR1" */ /* correctable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ycerr1_u { mmr_t sh_md_dqrp_mmr_ycerr1_regval; struct { @@ -26627,25 +14417,12 @@ mmr_t reserved_0 : 25; } sh_md_dqrp_mmr_ycerr1_s; } sh_md_dqrp_mmr_ycerr1_u_t; -#else -typedef union sh_md_dqrp_mmr_ycerr1_u { - mmr_t sh_md_dqrp_mmr_ycerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqrp_mmr_ycerr1_s; -} sh_md_dqrp_mmr_ycerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YCERR2" */ /* correctable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ycerr2_u { mmr_t sh_md_dqrp_mmr_ycerr2_regval; struct { @@ -26655,24 +14432,12 @@ mmr_t reserved_0 : 26; } sh_md_dqrp_mmr_ycerr2_s; } sh_md_dqrp_mmr_ycerr2_u_t; -#else -typedef union sh_md_dqrp_mmr_ycerr2_u { - mmr_t sh_md_dqrp_mmr_ycerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqrp_mmr_ycerr2_s; -} sh_md_dqrp_mmr_ycerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YUERR1" */ /* uncorrectable dir ecc group 1 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_yuerr1_u { mmr_t sh_md_dqrp_mmr_yuerr1_regval; struct { @@ -26683,25 +14448,12 @@ mmr_t reserved_0 : 25; } sh_md_dqrp_mmr_yuerr1_s; } sh_md_dqrp_mmr_yuerr1_u_t; -#else -typedef union sh_md_dqrp_mmr_yuerr1_u { - mmr_t sh_md_dqrp_mmr_yuerr1_regval; - struct { - mmr_t reserved_0 : 25; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp1 : 36; - } sh_md_dqrp_mmr_yuerr1_s; -} sh_md_dqrp_mmr_yuerr1_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YUERR2" */ /* uncorrectable dir ecc group 2 error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_yuerr2_u { mmr_t sh_md_dqrp_mmr_yuerr2_regval; struct { @@ -26711,24 +14463,12 @@ mmr_t reserved_0 : 26; } sh_md_dqrp_mmr_yuerr2_s; } sh_md_dqrp_mmr_yuerr2_u_t; -#else -typedef union sh_md_dqrp_mmr_yuerr2_u { - mmr_t sh_md_dqrp_mmr_yuerr2_regval; - struct { - mmr_t reserved_0 : 26; - mmr_t more : 1; - mmr_t val : 1; - mmr_t grp2 : 36; - } sh_md_dqrp_mmr_yuerr2_s; -} sh_md_dqrp_mmr_yuerr2_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YPERR" */ /* protocol error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_yperr_u { mmr_t sh_md_dqrp_mmr_yperr_regval; struct { @@ -26746,32 +14486,12 @@ mmr_t reserved_0 : 1; } sh_md_dqrp_mmr_yperr_s; } sh_md_dqrp_mmr_yperr_u_t; -#else -typedef union sh_md_dqrp_mmr_yperr_u { - mmr_t sh_md_dqrp_mmr_yperr_regval; - struct { - mmr_t reserved_0 : 1; - mmr_t arm : 1; - mmr_t more : 1; - mmr_t val : 1; - mmr_t mybit : 8; - mmr_t unc : 1; - mmr_t cor : 1; - mmr_t priv : 1; - mmr_t prige : 1; - mmr_t src : 14; - mmr_t cmd : 8; - mmr_t dir : 26; - } sh_md_dqrp_mmr_yperr_s; -} sh_md_dqrp_mmr_yperr_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_CMDTRIG" */ /* cmd triggers */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_cmdtrig_u { mmr_t sh_md_dqrp_mmr_dir_cmdtrig_regval; struct { @@ -26782,25 +14502,12 @@ mmr_t reserved_0 : 32; } sh_md_dqrp_mmr_dir_cmdtrig_s; } sh_md_dqrp_mmr_dir_cmdtrig_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_cmdtrig_u { - mmr_t sh_md_dqrp_mmr_dir_cmdtrig_regval; - struct { - mmr_t reserved_0 : 32; - mmr_t cmd3 : 8; - mmr_t cmd2 : 8; - mmr_t cmd1 : 8; - mmr_t cmd0 : 8; - } sh_md_dqrp_mmr_dir_cmdtrig_s; -} sh_md_dqrp_mmr_dir_cmdtrig_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_TBLTRIG" */ /* dir table trigger */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_tbltrig_u { mmr_t sh_md_dqrp_mmr_dir_tbltrig_regval; struct { @@ -26813,27 +14520,12 @@ mmr_t reserved_0 : 22; } sh_md_dqrp_mmr_dir_tbltrig_s; } sh_md_dqrp_mmr_dir_tbltrig_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_tbltrig_u { - mmr_t sh_md_dqrp_mmr_dir_tbltrig_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t mybit : 8; - mmr_t dirst : 9; - mmr_t prige : 1; - mmr_t acc : 2; - mmr_t cmd : 8; - mmr_t src : 14; - } sh_md_dqrp_mmr_dir_tbltrig_s; -} sh_md_dqrp_mmr_dir_tbltrig_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_DIR_TBLMASK" */ /* dir table trigger mask */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_dir_tblmask_u { mmr_t sh_md_dqrp_mmr_dir_tblmask_regval; struct { @@ -26846,27 +14538,12 @@ mmr_t reserved_0 : 22; } sh_md_dqrp_mmr_dir_tblmask_s; } sh_md_dqrp_mmr_dir_tblmask_u_t; -#else -typedef union sh_md_dqrp_mmr_dir_tblmask_u { - mmr_t sh_md_dqrp_mmr_dir_tblmask_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t mybit : 8; - mmr_t dirst : 9; - mmr_t prige : 1; - mmr_t acc : 2; - mmr_t cmd : 8; - mmr_t src : 14; - } sh_md_dqrp_mmr_dir_tblmask_s; -} sh_md_dqrp_mmr_dir_tblmask_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xbist_h_u { mmr_t sh_md_dqrp_mmr_xbist_h_regval; struct { @@ -26878,26 +14555,12 @@ mmr_t reserved_1 : 21; } sh_md_dqrp_mmr_xbist_h_s; } sh_md_dqrp_mmr_xbist_h_u_t; -#else -typedef union sh_md_dqrp_mmr_xbist_h_u { - mmr_t sh_md_dqrp_mmr_xbist_h_regval; - struct { - mmr_t reserved_1 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_xbist_h_s; -} sh_md_dqrp_mmr_xbist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xbist_l_u { mmr_t sh_md_dqrp_mmr_xbist_l_regval; struct { @@ -26908,25 +14571,12 @@ mmr_t reserved_1 : 22; } sh_md_dqrp_mmr_xbist_l_s; } sh_md_dqrp_mmr_xbist_l_u_t; -#else -typedef union sh_md_dqrp_mmr_xbist_l_u { - mmr_t sh_md_dqrp_mmr_xbist_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_xbist_l_s; -} sh_md_dqrp_mmr_xbist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xbist_err_h_u { mmr_t sh_md_dqrp_mmr_xbist_err_h_regval; struct { @@ -26937,25 +14587,12 @@ mmr_t reserved_1 : 22; } sh_md_dqrp_mmr_xbist_err_h_s; } sh_md_dqrp_mmr_xbist_err_h_u_t; -#else -typedef union sh_md_dqrp_mmr_xbist_err_h_u { - mmr_t sh_md_dqrp_mmr_xbist_err_h_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_xbist_err_h_s; -} sh_md_dqrp_mmr_xbist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_XBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_xbist_err_l_u { mmr_t sh_md_dqrp_mmr_xbist_err_l_regval; struct { @@ -26966,25 +14603,12 @@ mmr_t reserved_1 : 22; } sh_md_dqrp_mmr_xbist_err_l_s; } sh_md_dqrp_mmr_xbist_err_l_u_t; -#else -typedef union sh_md_dqrp_mmr_xbist_err_l_u { - mmr_t sh_md_dqrp_mmr_xbist_err_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_xbist_err_l_s; -} sh_md_dqrp_mmr_xbist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ybist_h_u { mmr_t sh_md_dqrp_mmr_ybist_h_regval; struct { @@ -26996,26 +14620,12 @@ mmr_t reserved_1 : 21; } sh_md_dqrp_mmr_ybist_h_s; } sh_md_dqrp_mmr_ybist_h_u_t; -#else -typedef union sh_md_dqrp_mmr_ybist_h_u { - mmr_t sh_md_dqrp_mmr_ybist_h_regval; - struct { - mmr_t reserved_1 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_ybist_h_s; -} sh_md_dqrp_mmr_ybist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ybist_l_u { mmr_t sh_md_dqrp_mmr_ybist_l_regval; struct { @@ -27026,25 +14636,12 @@ mmr_t reserved_1 : 22; } sh_md_dqrp_mmr_ybist_l_s; } sh_md_dqrp_mmr_ybist_l_u_t; -#else -typedef union sh_md_dqrp_mmr_ybist_l_u { - mmr_t sh_md_dqrp_mmr_ybist_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_ybist_l_s; -} sh_md_dqrp_mmr_ybist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ybist_err_h_u { mmr_t sh_md_dqrp_mmr_ybist_err_h_regval; struct { @@ -27055,25 +14652,12 @@ mmr_t reserved_1 : 22; } sh_md_dqrp_mmr_ybist_err_h_s; } sh_md_dqrp_mmr_ybist_err_h_u_t; -#else -typedef union sh_md_dqrp_mmr_ybist_err_h_u { - mmr_t sh_md_dqrp_mmr_ybist_err_h_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_ybist_err_h_s; -} sh_md_dqrp_mmr_ybist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRP_MMR_YBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrp_mmr_ybist_err_l_u { mmr_t sh_md_dqrp_mmr_ybist_err_l_regval; struct { @@ -27084,25 +14668,12 @@ mmr_t reserved_1 : 22; } sh_md_dqrp_mmr_ybist_err_l_s; } sh_md_dqrp_mmr_ybist_err_l_u_t; -#else -typedef union sh_md_dqrp_mmr_ybist_err_l_u { - mmr_t sh_md_dqrp_mmr_ybist_err_l_regval; - struct { - mmr_t reserved_1 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t reserved_0 : 8; - mmr_t pat : 32; - } sh_md_dqrp_mmr_ybist_err_l_s; -} sh_md_dqrp_mmr_ybist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_XBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_xbist_h_u { mmr_t sh_md_dqrs_mmr_xbist_h_regval; struct { @@ -27113,25 +14684,12 @@ mmr_t reserved_0 : 21; } sh_md_dqrs_mmr_xbist_h_s; } sh_md_dqrs_mmr_xbist_h_u_t; -#else -typedef union sh_md_dqrs_mmr_xbist_h_u { - mmr_t sh_md_dqrs_mmr_xbist_h_regval; - struct { - mmr_t reserved_0 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_xbist_h_s; -} sh_md_dqrs_mmr_xbist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_XBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_xbist_l_u { mmr_t sh_md_dqrs_mmr_xbist_l_regval; struct { @@ -27141,24 +14699,12 @@ mmr_t reserved_0 : 22; } sh_md_dqrs_mmr_xbist_l_s; } sh_md_dqrs_mmr_xbist_l_u_t; -#else -typedef union sh_md_dqrs_mmr_xbist_l_u { - mmr_t sh_md_dqrs_mmr_xbist_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_xbist_l_s; -} sh_md_dqrs_mmr_xbist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_XBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_xbist_err_h_u { mmr_t sh_md_dqrs_mmr_xbist_err_h_regval; struct { @@ -27168,24 +14714,12 @@ mmr_t reserved_0 : 22; } sh_md_dqrs_mmr_xbist_err_h_s; } sh_md_dqrs_mmr_xbist_err_h_u_t; -#else -typedef union sh_md_dqrs_mmr_xbist_err_h_u { - mmr_t sh_md_dqrs_mmr_xbist_err_h_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_xbist_err_h_s; -} sh_md_dqrs_mmr_xbist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_XBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_xbist_err_l_u { mmr_t sh_md_dqrs_mmr_xbist_err_l_regval; struct { @@ -27195,24 +14729,12 @@ mmr_t reserved_0 : 22; } sh_md_dqrs_mmr_xbist_err_l_s; } sh_md_dqrs_mmr_xbist_err_l_u_t; -#else -typedef union sh_md_dqrs_mmr_xbist_err_l_u { - mmr_t sh_md_dqrs_mmr_xbist_err_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_xbist_err_l_s; -} sh_md_dqrs_mmr_xbist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_YBIST_H" */ /* rising edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_ybist_h_u { mmr_t sh_md_dqrs_mmr_ybist_h_regval; struct { @@ -27223,25 +14745,12 @@ mmr_t reserved_0 : 21; } sh_md_dqrs_mmr_ybist_h_s; } sh_md_dqrs_mmr_ybist_h_u_t; -#else -typedef union sh_md_dqrs_mmr_ybist_h_u { - mmr_t sh_md_dqrs_mmr_ybist_h_regval; - struct { - mmr_t reserved_0 : 21; - mmr_t arm : 1; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_ybist_h_s; -} sh_md_dqrs_mmr_ybist_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_YBIST_L" */ /* falling edge bist/fill pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_ybist_l_u { mmr_t sh_md_dqrs_mmr_ybist_l_regval; struct { @@ -27251,24 +14760,12 @@ mmr_t reserved_0 : 22; } sh_md_dqrs_mmr_ybist_l_s; } sh_md_dqrs_mmr_ybist_l_u_t; -#else -typedef union sh_md_dqrs_mmr_ybist_l_u { - mmr_t sh_md_dqrs_mmr_ybist_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t rot : 1; - mmr_t inv : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_ybist_l_s; -} sh_md_dqrs_mmr_ybist_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_YBIST_ERR_H" */ /* rising edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_ybist_err_h_u { mmr_t sh_md_dqrs_mmr_ybist_err_h_regval; struct { @@ -27278,24 +14775,12 @@ mmr_t reserved_0 : 22; } sh_md_dqrs_mmr_ybist_err_h_s; } sh_md_dqrs_mmr_ybist_err_h_u_t; -#else -typedef union sh_md_dqrs_mmr_ybist_err_h_u { - mmr_t sh_md_dqrs_mmr_ybist_err_h_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_ybist_err_h_s; -} sh_md_dqrs_mmr_ybist_err_h_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_YBIST_ERR_L" */ /* falling edge bist error pattern */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_ybist_err_l_u { mmr_t sh_md_dqrs_mmr_ybist_err_l_regval; struct { @@ -27305,24 +14790,12 @@ mmr_t reserved_0 : 22; } sh_md_dqrs_mmr_ybist_err_l_s; } sh_md_dqrs_mmr_ybist_err_l_u_t; -#else -typedef union sh_md_dqrs_mmr_ybist_err_l_u { - mmr_t sh_md_dqrs_mmr_ybist_err_l_regval; - struct { - mmr_t reserved_0 : 22; - mmr_t more : 1; - mmr_t val : 1; - mmr_t pat : 40; - } sh_md_dqrs_mmr_ybist_err_l_s; -} sh_md_dqrs_mmr_ybist_err_l_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_JNR_DEBUG" */ /* joiner/fct debug configuration */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_jnr_debug_u { mmr_t sh_md_dqrs_mmr_jnr_debug_regval; struct { @@ -27331,23 +14804,12 @@ mmr_t reserved_0 : 62; } sh_md_dqrs_mmr_jnr_debug_s; } sh_md_dqrs_mmr_jnr_debug_u_t; -#else -typedef union sh_md_dqrs_mmr_jnr_debug_u { - mmr_t sh_md_dqrs_mmr_jnr_debug_regval; - struct { - mmr_t reserved_0 : 62; - mmr_t rw : 1; - mmr_t px : 1; - } sh_md_dqrs_mmr_jnr_debug_s; -} sh_md_dqrs_mmr_jnr_debug_u_t; -#endif /* ==================================================================== */ /* Register "SH_MD_DQRS_MMR_YAMOPW_ERR" */ /* amo/partial rmw ecc error register */ /* ==================================================================== */ -#ifdef LITTLE_ENDIAN typedef union sh_md_dqrs_mmr_yamopw_err_u { mmr_t sh_md_dqrs_mmr_yamopw_err_regval; struct { @@ -27363,23 +14825,5 @@ mmr_t reserved_2 : 31; } sh_md_dqrs_mmr_yamopw_err_s; } sh_md_dqrs_mmr_yamopw_err_u_t; -#else -typedef union sh_md_dqrs_mmr_yamopw_err_u { - mmr_t sh_md_dqrs_mmr_yamopw_err_regval; - struct { - mmr_t reserved_2 : 31; - mmr_t arm : 1; - mmr_t reserved_1 : 6; - mmr_t runc : 1; - mmr_t rcor : 1; - mmr_t rsyn : 8; - mmr_t reserved_0 : 6; - mmr_t sunc : 1; - mmr_t scor : 1; - mmr_t ssyn : 8; - } sh_md_dqrs_mmr_yamopw_err_s; -} sh_md_dqrs_mmr_yamopw_err_u_t; -#endif - #endif /* _ASM_IA64_SN_SN2_SHUB_MMR_T_H */ diff -Nru a/include/asm-ia64/spinlock.h b/include/asm-ia64/spinlock.h --- a/include/asm-ia64/spinlock.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/spinlock.h Fri Sep 19 00:39:53 2003 @@ -24,6 +24,7 @@ #define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } #define spin_lock_init(x) ((x)->lock = 0) +#ifdef ASM_SUPPORTED /* * Try to get the lock. If we fail to get the lock, make a non-standard call to * ia64_spinlock_contention(). We do not use a normal call because that would force all @@ -85,6 +86,21 @@ # endif /* CONFIG_MCKINLEY */ #endif } +#else /* !ASM_SUPPORTED */ +# define _raw_spin_lock(x) \ +do { \ + __u32 *ia64_spinlock_ptr = (__u32 *) (x); \ + __u64 ia64_spinlock_val; \ + ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \ + if (unlikely(ia64_spinlock_val)) { \ + do { \ + while (*ia64_spinlock_ptr) \ + ia64_barrier(); \ + ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \ + } while (ia64_spinlock_val); \ + } \ +} while (0) +#endif /* !ASM_SUPPORTED */ #define spin_is_locked(x) ((x)->lock != 0) #define _raw_spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0) @@ -117,22 +133,19 @@ ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \ } while (0) +#ifdef ASM_SUPPORTED #define _raw_write_lock(rw) \ do { \ __asm__ __volatile__ ( \ "mov ar.ccv = r0\n" \ - "dep r29 = -1, r0, 31, 1\n" \ - ";;\n" \ + "dep r29 = -1, r0, 31, 1;;\n" \ "1:\n" \ - "ld4 r2 = [%0]\n" \ - ";;\n" \ + "ld4 r2 = [%0];;\n" \ "cmp4.eq p0,p7 = r0,r2\n" \ "(p7) br.cond.spnt.few 1b \n" \ - "cmpxchg4.acq r2 = [%0], r29, ar.ccv\n" \ - ";;\n" \ + "cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n" \ "cmp4.eq p0,p7 = r0, r2\n" \ - "(p7) br.cond.spnt.few 1b\n" \ - ";;\n" \ + "(p7) br.cond.spnt.few 1b;;\n" \ :: "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory"); \ } while(0) @@ -142,12 +155,34 @@ \ __asm__ __volatile__ ( \ "mov ar.ccv = r0\n" \ - "dep r29 = -1, r0, 31, 1\n" \ - ";;\n" \ + "dep r29 = -1, r0, 31, 1;;\n" \ "cmpxchg4.acq %0 = [%1], r29, ar.ccv\n" \ : "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory"); \ (result == 0); \ }) + +#else /* !ASM_SUPPORTED */ + +#define _raw_write_lock(l) \ +({ \ + __u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1); \ + __u32 *ia64_write_lock_ptr = (__u32 *) (l); \ + do { \ + while (*ia64_write_lock_ptr) \ + ia64_barrier(); \ + ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0); \ + } while (ia64_val); \ +}) + +#define _raw_write_trylock(rw) \ +({ \ + __u64 ia64_val; \ + __u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1); \ + ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0); \ + (ia64_val == 0); \ +}) + +#endif /* !ASM_SUPPORTED */ #define _raw_write_unlock(x) \ ({ \ diff -Nru a/include/asm-ia64/uaccess.h b/include/asm-ia64/uaccess.h --- a/include/asm-ia64/uaccess.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/uaccess.h Fri Sep 19 00:39:53 2003 @@ -33,6 +33,7 @@ #include #include +#include #include /* @@ -86,6 +87,8 @@ #define __put_user(x,ptr) __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) #define __get_user(x,ptr) __get_user_nocheck((x),(ptr),sizeof(*(ptr))) +#ifdef ASM_SUPPORTED + extern void __get_user_unknown (void); #define __get_user_nocheck(x,ptr,size) \ @@ -216,6 +219,90 @@ "\t.xdata4 \"__ex_table\", 1b-., 1f-.\n" \ "[1:]" \ : "=r"(__pu_err) : "m"(__m(addr)), "rO"(x), "0"(__pu_err)) + +#else /* !ASM_SUPPORTED */ + +#define RELOC_TYPE 2 /* ip-rel */ + +#define __put_user_xx(val, addr, size, err) \ + __st_user("__ex_table", (unsigned long) addr, size, RELOC_TYPE, (unsigned long) (val)); \ + (err) = ia64_getreg(_IA64_REG_R8); + +#define __get_user_xx(val, addr, size, err) \ + __ld_user("__ex_table", (unsigned long) addr, size, RELOC_TYPE); \ + (err) = ia64_getreg(_IA64_REG_R8); \ + (val) = ia64_getreg(_IA64_REG_R9); + +extern void __get_user_unknown (void); + +#define __get_user_nocheck(x, ptr, size) \ +({ \ + register long __gu_err = 0; \ + register long __gu_val = 0; \ + const __typeof__(*(ptr)) *__gu_addr = (ptr); \ + switch (size) { \ + case 1: case 2: case 4: case 8: \ + __get_user_xx(__gu_val, __gu_addr, size, __gu_err); \ + break; \ + default: \ + __get_user_unknown(); \ + break; \ + } \ + (x) = (__typeof__(*(ptr))) __gu_val; \ + __gu_err; \ +}) + +#define __get_user_check(x,ptr,size,segment) \ +({ \ + register long __gu_err = -EFAULT; \ + register long __gu_val = 0; \ + const __typeof__(*(ptr)) *__gu_addr = (ptr); \ + if (__access_ok((long) __gu_addr, size, segment)) { \ + switch (size) { \ + case 1: case 2: case 4: case 8: \ + __get_user_xx(__gu_val, __gu_addr, size, __gu_err); \ + break; \ + default: \ + __get_user_unknown(); break; \ + } \ + } \ + (x) = (__typeof__(*(ptr))) __gu_val; \ + __gu_err; \ +}) + +extern void __put_user_unknown (void); + +#define __put_user_nocheck(x, ptr, size) \ +({ \ + int __pu_err = 0; \ + __typeof__(*(ptr)) *__pu_addr = (ptr); \ + switch (size) { \ + case 1: case 2: case 4: case 8: \ + __put_user_xx(x, __pu_addr, size, __pu_err); \ + break; \ + default: \ + __put_user_unknown(); break; \ + } \ + __pu_err; \ +}) + +#define __put_user_check(x,ptr,size,segment) \ +({ \ + register long __pu_err = -EFAULT; \ + __typeof__(*(ptr)) *__pu_addr = (ptr); \ + if (__access_ok((long)__pu_addr,size,segment)) { \ + switch (size) { \ + case 1: case 2: case 4: case 8: \ + __put_user_xx(x,__pu_addr, size, __pu_err); \ + break; \ + default: \ + __put_user_unknown(); break; \ + } \ + } \ + __pu_err; \ +}) + +#endif /* !ASM_SUPPORTED */ /* * Complex access routines diff -Nru a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h --- a/include/asm-ia64/unistd.h Fri Sep 19 00:39:53 2003 +++ b/include/asm-ia64/unistd.h Fri Sep 19 00:39:53 2003 @@ -248,7 +248,6 @@ #define __NR_sys_clock_nanosleep 1256 #define __NR_sys_fstatfs64 1257 #define __NR_sys_statfs64 1258 -#define __NR_fadvises64_64 1259 #ifdef __KERNEL__ diff -Nru a/include/linux/init.h b/include/linux/init.h --- a/include/linux/init.h Fri Sep 19 00:39:53 2003 +++ b/include/linux/init.h Fri Sep 19 00:39:53 2003 @@ -2,6 +2,7 @@ #define _LINUX_INIT_H #include +#include /* These macros are used to mark some functions or * initialized data (doesn't apply to uninitialized data) @@ -71,15 +72,16 @@ #ifndef __ASSEMBLY__ -/* initcalls are now grouped by functionality into separate +/* initcalls are now grouped by functionality into separate * subsections. Ordering inside the subsections is determined - * by link order. - * For backwards compatibility, initcall() puts the call in + * by link order. + * For backwards compatibility, initcall() puts the call in * the device init subsection. */ -#define __define_initcall(level,fn) \ - static initcall_t __initcall_##fn __attribute__ ((unused,__section__ (".initcall" level ".init"))) = fn +#define __define_initcall(level,fn) \ + static initcall_t __initcall_##fn \ + __attribute_used__ __attribute__ ((__section__ (".initcall" level ".init"))) = fn #define core_initcall(fn) __define_initcall("1",fn) #define postcore_initcall(fn) __define_initcall("2",fn) @@ -95,10 +97,12 @@ static exitcall_t __exitcall_##fn __exit_call = fn #define console_initcall(fn) \ - static initcall_t __initcall_##fn __attribute__ ((unused,__section__ (".con_initcall.init")))=fn + static initcall_t __initcall_##fn \ + __attribute_used__ __attribute__ ((__section__ (".con_initcall.init"))) = fn #define security_initcall(fn) \ - static initcall_t __initcall_##fn __attribute__ ((unused,__section__ (".security_initcall.init"))) = fn + static initcall_t __initcall_##fn \ + __attribute_used__ __attribute__ ((__section__ (".security_initcall.init"))) = fn struct obs_kernel_param { const char *str; @@ -106,10 +110,10 @@ }; /* OBSOLETE: see moduleparam.h for the right way. */ -#define __setup(str, fn) \ - static char __setup_str_##fn[] __initdata = str; \ - static struct obs_kernel_param __setup_##fn \ - __attribute__((unused,__section__ (".init.setup"))) \ +#define __setup(str, fn) \ + static char __setup_str_##fn[] __initdata = str; \ + static struct obs_kernel_param __setup_##fn \ + __attribute_used__ __attribute__((__section__ (".init.setup"))) \ = { __setup_str_##fn, fn } #endif /* __ASSEMBLY__ */ diff -Nru a/include/linux/module.h b/include/linux/module.h --- a/include/linux/module.h Fri Sep 19 00:39:54 2003 +++ b/include/linux/module.h Fri Sep 19 00:39:54 2003 @@ -60,10 +60,12 @@ #define __module_cat(a,b) ___module_cat(a,b) #define __MODULE_INFO(tag, name, info) \ static const char __module_cat(name,__LINE__)[] \ + __attribute_used__ \ __attribute__((section(".modinfo"),unused)) = __stringify(tag) "=" info -#define MODULE_GENERIC_TABLE(gtype,name) \ -extern const struct gtype##_id __mod_##gtype##_table \ +#define MODULE_GENERIC_TABLE(gtype,name) \ +extern const struct gtype##_id __mod_##gtype##_table \ + __attribute_used__ \ __attribute__ ((unused, alias(__stringify(name)))) #define THIS_MODULE (&__this_module) @@ -142,6 +144,7 @@ #define __CRC_SYMBOL(sym, sec) \ extern void *__crc_##sym __attribute__((weak)); \ static const unsigned long __kcrctab_##sym \ + __attribute_used__ \ __attribute__((section("__kcrctab" sec), unused)) \ = (unsigned long) &__crc_##sym; #else @@ -155,6 +158,7 @@ __attribute__((section("__ksymtab_strings"))) \ = MODULE_SYMBOL_PREFIX #sym; \ static const struct kernel_symbol __ksymtab_##sym \ + __attribute_used__ \ __attribute__((section("__ksymtab" sec), unused)) \ = { (unsigned long)&sym, __kstrtab_##sym } diff -Nru a/include/linux/moduleparam.h b/include/linux/moduleparam.h --- a/include/linux/moduleparam.h Fri Sep 19 00:39:53 2003 +++ b/include/linux/moduleparam.h Fri Sep 19 00:39:53 2003 @@ -40,6 +40,7 @@ #define __module_param_call(prefix, name, set, get, arg, perm) \ static char __param_str_##name[] __initdata = prefix #name; \ static struct kernel_param const __param_##name \ + __attribute_used__ \ __attribute__ ((unused,__section__ ("__param"),aligned(sizeof(void *)))) \ = { __param_str_##name, perm, set, get, arg } diff -Nru a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h --- a/include/linux/nfs_fs.h Fri Sep 19 00:39:53 2003 +++ b/include/linux/nfs_fs.h Fri Sep 19 00:39:53 2003 @@ -410,7 +410,7 @@ nfs_size_to_loff_t(__u64 size) { loff_t maxsz = (((loff_t) ULONG_MAX) << PAGE_CACHE_SHIFT) + PAGE_CACHE_SIZE - 1; - if (size > maxsz) + if (size > (__u64) maxsz) return maxsz; return (loff_t) size; } diff -Nru a/include/linux/sysctl.h b/include/linux/sysctl.h --- a/include/linux/sysctl.h Fri Sep 19 00:39:53 2003 +++ b/include/linux/sysctl.h Fri Sep 19 00:39:53 2003 @@ -127,6 +127,7 @@ KERN_PANIC_ON_OOPS=57, /* int: whether we will panic on an oops */ KERN_HPPA_PWRSW=58, /* int: hppa soft-power enable */ KERN_HPPA_UNALIGNED=59, /* int: hppa unaligned-trap enable */ + KERN_CACHEDECAYTICKS=60,/* ulong: value for cache_decay_ticks (EXPERIMENTAL!) */ }; diff -Nru a/kernel/printk.c b/kernel/printk.c --- a/kernel/printk.c Fri Sep 19 00:39:54 2003 +++ b/kernel/printk.c Fri Sep 19 00:39:54 2003 @@ -313,6 +313,12 @@ __call_console_drivers(start, end); } } +#ifdef CONFIG_IA64_EARLY_PRINTK + if (!console_drivers) { + void early_printk (const char *str, size_t len); + early_printk(&LOG_BUF(start), end - start); + } +#endif } /* @@ -630,7 +636,11 @@ * for us. */ spin_lock_irqsave(&logbuf_lock, flags); +#ifdef CONFIG_IA64_EARLY_PRINTK + con_start = log_end; +#else con_start = log_start; +#endif spin_unlock_irqrestore(&logbuf_lock, flags); } release_console_sem(); @@ -683,3 +693,117 @@ tty->driver->write(tty, 0, msg, strlen(msg)); return; } + +#ifdef CONFIG_IA64_EARLY_PRINTK + +#include + +# ifdef CONFIG_IA64_EARLY_PRINTK_VGA + + +#define VGABASE ((char *)0xc0000000000b8000) +#define VGALINES 24 +#define VGACOLS 80 + +static int current_ypos = VGALINES, current_xpos = 0; + +static void +early_printk_vga (const char *str, size_t len) +{ + char c; + int i, k, j; + + while (len-- > 0) { + c = *str++; + if (current_ypos >= VGALINES) { + /* scroll 1 line up */ + for (k = 1, j = 0; k < VGALINES; k++, j++) { + for (i = 0; i < VGACOLS; i++) { + writew(readw(VGABASE + 2*(VGACOLS*k + i)), + VGABASE + 2*(VGACOLS*j + i)); + } + } + for (i = 0; i < VGACOLS; i++) { + writew(0x720, VGABASE + 2*(VGACOLS*j + i)); + } + current_ypos = VGALINES-1; + } + if (c == '\n') { + current_xpos = 0; + current_ypos++; + } else if (c != '\r') { + writew(((0x7 << 8) | (unsigned short) c), + VGABASE + 2*(VGACOLS*current_ypos + current_xpos++)); + if (current_xpos >= VGACOLS) { + current_xpos = 0; + current_ypos++; + } + } + } +} + +# endif /* CONFIG_IA64_EARLY_PRINTK_VGA */ + +# ifdef CONFIG_IA64_EARLY_PRINTK_UART + +#include +#include + +static void early_printk_uart(const char *str, size_t len) +{ + static char *uart = NULL; + unsigned long uart_base; + char c; + + if (!uart) { + uart_base = 0; +# ifdef CONFIG_SERIAL_8250_HCDP + { + extern unsigned long hcdp_early_uart(void); + uart_base = hcdp_early_uart(); + } +# endif +# if CONFIG_IA64_EARLY_PRINTK_UART_BASE + if (!uart_base) + uart_base = CONFIG_IA64_EARLY_PRINTK_UART_BASE; +# endif + if (!uart_base) + return; + + uart = ioremap(uart_base, 64); + if (!uart) + return; + } + + while (len-- > 0) { + c = *str++; + while ((readb(uart + UART_LSR) & UART_LSR_TEMT) == 0) + cpu_relax(); /* spin */ + + writeb(c, uart + UART_TX); + + if (c == '\n') + writeb('\r', uart + UART_TX); + } +} + +# endif /* CONFIG_IA64_EARLY_PRINTK_UART */ + +#ifdef CONFIG_IA64_EARLY_PRINTK_SGI_SN +extern int early_printk_sn_sal(const char *str, int len); +#endif + +void early_printk(const char *str, size_t len) +{ +#ifdef CONFIG_IA64_EARLY_PRINTK_UART + early_printk_uart(str, len); +#endif +#ifdef CONFIG_IA64_EARLY_PRINTK_VGA + early_printk_vga(str, len); +#endif +#ifdef CONFIG_IA64_EARLY_PRINTK_SGI_SN + early_printk_sn_sal(str, len); +#endif +} + +#endif /* CONFIG_IA64_EARLY_PRINTK */ diff -Nru a/kernel/sysctl.c b/kernel/sysctl.c --- a/kernel/sysctl.c Fri Sep 19 00:39:53 2003 +++ b/kernel/sysctl.c Fri Sep 19 00:39:53 2003 @@ -581,6 +581,16 @@ .mode = 0644, .proc_handler = &proc_dointvec, }, +#ifdef CONFIG_SMP + { + .ctl_name = KERN_CACHEDECAYTICKS, + .procname = "cache_decay_ticks", + .data = &cache_decay_ticks, + .maxlen = sizeof(cache_decay_ticks), + .mode = 0644, + .proc_handler = &proc_doulongvec_minmax, + }, +#endif { .ctl_name = 0 } }; diff -Nru a/mm/memory.c b/mm/memory.c --- a/mm/memory.c Fri Sep 19 00:39:53 2003 +++ b/mm/memory.c Fri Sep 19 00:39:53 2003 @@ -114,8 +114,10 @@ } pmd = pmd_offset(dir, 0); pgd_clear(dir); - for (j = 0; j < PTRS_PER_PMD ; j++) + for (j = 0; j < PTRS_PER_PMD ; j++) { + prefetchw(pmd + j + PREFETCH_STRIDE/sizeof(*pmd)); free_one_pmd(tlb, pmd+j); + } pmd_free_tlb(tlb, pmd); }