## Automatically generated incremental diff ## From: linux-2.4.22-bk20 ## To: linux-2.4.22-bk21 ## Robot: $Id: make-incremental-diff,v 1.11 2002/02/20 02:59:33 hpa Exp $ diff -urN linux-2.4.22-bk20/Documentation/Configure.help linux-2.4.22-bk21/Documentation/Configure.help --- linux-2.4.22-bk20/Documentation/Configure.help 2003-09-18 03:05:42.000000000 -0700 +++ linux-2.4.22-bk21/Documentation/Configure.help 2003-09-18 03:06:08.000000000 -0700 @@ -27012,11 +27012,13 @@ # Choice: ia64type Itanium CONFIG_ITANIUM - Select your IA64 processor type. The default is Intel Itanium. + Select your IA-64 processor type. The default is Intel Itanium. + This choice is safe for all IA-64 systems, but may not perform + optimally on systems with, say, Itanium 2 or newer processors. -McKinley +Itanium 2 CONFIG_MCKINLEY - Select this to configure for a McKinley processor. + Select this to configure for an Itanium 2 (McKinley) processor. # Choice: ia64system IA-64 system type @@ -27073,6 +27075,14 @@ Say Y here to enable machine check support for IA-64. If you're unsure, answer Y. +Use PAL_HALT_LIGHT in idle loop +CONFIG_IA64_PAL_IDLE + Say Y here to enable use of PAL_HALT_LIGHT in the cpu_idle loop. + This allows the CPU to enter a low power state when idle. You + can enable CONFIG_IA64_PALINFO and check /proc/pal/cpu0/power_info + to see the power consumption and latency for this state. If you're + unsure your firmware supports it, answer N. + Disable IA-64 Virtual Hash Page Table CONFIG_DISABLE_VHPT The Virtual Hash Page Table (VHPT) enhances virtual address diff -urN linux-2.4.22-bk20/Makefile linux-2.4.22-bk21/Makefile --- linux-2.4.22-bk20/Makefile 2003-09-18 03:05:43.000000000 -0700 +++ linux-2.4.22-bk21/Makefile 2003-09-18 03:06:08.000000000 -0700 @@ -1,7 +1,7 @@ VERSION = 2 PATCHLEVEL = 4 SUBLEVEL = 22 -EXTRAVERSION = -bk20 +EXTRAVERSION = -bk21 KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) diff -urN linux-2.4.22-bk20/arch/i386/kernel/acpi.c linux-2.4.22-bk21/arch/i386/kernel/acpi.c --- linux-2.4.22-bk20/arch/i386/kernel/acpi.c 2003-08-25 04:44:39.000000000 -0700 +++ linux-2.4.22-bk21/arch/i386/kernel/acpi.c 2003-09-18 03:06:09.000000000 -0700 @@ -355,7 +355,6 @@ result = acpi_table_parse(ACPI_APIC, acpi_parse_madt); if (!result) { - printk(KERN_WARNING PREFIX "MADT not present\n"); return 0; } else if (result < 0) { diff -urN linux-2.4.22-bk20/arch/i386/kernel/dmi_scan.c linux-2.4.22-bk21/arch/i386/kernel/dmi_scan.c --- linux-2.4.22-bk20/arch/i386/kernel/dmi_scan.c 2003-09-18 03:05:44.000000000 -0700 +++ linux-2.4.22-bk21/arch/i386/kernel/dmi_scan.c 2003-09-18 03:06:09.000000000 -0700 @@ -895,11 +895,6 @@ MATCH(DMI_BOARD_NAME, "CUR-DLS"), NO_MATCH, NO_MATCH }}, - { force_acpi_ht, "ASUS A7V", { - MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC"), - MATCH(DMI_BOARD_NAME, ""), - MATCH(DMI_BIOS_VERSION, "ASUS A7V ACPI BIOS Revision 1011"), NO_MATCH }}, - { force_acpi_ht, "ABIT i440BX-W83977", { MATCH(DMI_BOARD_VENDOR, "ABIT "), MATCH(DMI_BOARD_NAME, "i440BX-W83977 (BP6)"), @@ -932,7 +927,9 @@ { disable_acpi_pci, "ASUS A7V", { MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC"), MATCH(DMI_BOARD_NAME, ""), - MATCH(DMI_BIOS_VERSION, "ASUS A7V ACPI BIOS Revision 1007"), NO_MATCH }}, + /* newer BIOS, Revision 1011, does work */ + MATCH(DMI_BIOS_VERSION, "ASUS A7V ACPI BIOS Revision 1007"), + NO_MATCH }}, #endif // CONFIG_ACPI_BOOT { NULL, } diff -urN linux-2.4.22-bk20/arch/i386/kernel/mpparse.c linux-2.4.22-bk21/arch/i386/kernel/mpparse.c --- linux-2.4.22-bk20/arch/i386/kernel/mpparse.c 2003-09-18 03:05:44.000000000 -0700 +++ linux-2.4.22-bk21/arch/i386/kernel/mpparse.c 2003-09-18 03:06:09.000000000 -0700 @@ -1224,8 +1224,6 @@ } } -/* Ensure the ACPI SCI interrupt level is active low, edge-triggered */ - extern FADT_DESCRIPTOR acpi_fadt; void __init mp_config_ioapic_for_sci(int irq) @@ -1234,6 +1232,7 @@ int ioapic_pin; struct acpi_table_madt* madt; struct acpi_table_int_src_ovr *entry = NULL; + acpi_interrupt_flags flags; void *madt_end; acpi_status status; @@ -1257,25 +1256,28 @@ * See the note at the end of ACPI 2.0b section * 5.2.10.8 for what this is about. */ - if (entry->bus_irq != entry->global_irq) { - acpi_fadt.sci_int = entry->global_irq; - irq = entry->global_irq; - break; - } - else - return; + flags = entry->flags; + acpi_fadt.sci_int = entry->global_irq; + irq = entry->global_irq; + break; } - + entry = (struct acpi_table_int_src_ovr *) ((unsigned long) entry + entry->header.length); } } - + ioapic = mp_find_ioapic(irq); ioapic_pin = irq - mp_ioapic_routing[ioapic].irq_start; - io_apic_set_pci_routing(ioapic, ioapic_pin, irq, 1, 1); // Active low, level triggered + if (flags.polarity == 0) + flags.polarity = 0x3; /* Active low */ + if (flags.trigger == 0) + flags.trigger = 0x3; /* Level-triggered */ + + io_apic_set_pci_routing(ioapic, ioapic_pin, irq, + (flags.trigger >> 1) , (flags.polarity >> 1)); } diff -urN linux-2.4.22-bk20/arch/i386/mm/ioremap.c linux-2.4.22-bk21/arch/i386/mm/ioremap.c --- linux-2.4.22-bk20/arch/i386/mm/ioremap.c 2002-08-02 17:39:42.000000000 -0700 +++ linux-2.4.22-bk21/arch/i386/mm/ioremap.c 2003-09-18 03:06:09.000000000 -0700 @@ -140,7 +140,7 @@ */ offset = phys_addr & ~PAGE_MASK; phys_addr &= PAGE_MASK; - size = PAGE_ALIGN(last_addr) - phys_addr; + size = PAGE_ALIGN(last_addr+1) - phys_addr; /* * Ok, go for it.. diff -urN linux-2.4.22-bk20/drivers/acpi/ec.c linux-2.4.22-bk21/drivers/acpi/ec.c --- linux-2.4.22-bk20/drivers/acpi/ec.c 2003-08-25 04:44:41.000000000 -0700 +++ linux-2.4.22-bk21/drivers/acpi/ec.c 2003-09-18 03:06:15.000000000 -0700 @@ -33,7 +33,7 @@ #include #include #include - +#include #define _COMPONENT ACPI_EC_COMPONENT ACPI_MODULE_NAME ("acpi_ec") @@ -408,7 +408,10 @@ * The EC object is in the handler context and is needed * when calling the acpi_ec_space_handler. */ - *return_context = handler_context; + if(function == ACPI_REGION_DEACTIVATE) + *return_context = NULL; + else + *return_context = handler_context; return AE_OK; } diff -urN linux-2.4.22-bk20/drivers/acpi/events/evregion.c linux-2.4.22-bk21/drivers/acpi/events/evregion.c --- linux-2.4.22-bk20/drivers/acpi/events/evregion.c 2003-08-25 04:44:41.000000000 -0700 +++ linux-2.4.22-bk21/drivers/acpi/events/evregion.c 2003-09-18 03:06:15.000000000 -0700 @@ -382,7 +382,7 @@ union acpi_operand_object *obj_desc; union acpi_operand_object **last_obj_ptr; acpi_adr_space_setup region_setup; - void *region_context; + void **region_context; union acpi_operand_object *region_obj2; acpi_status status; @@ -394,7 +394,7 @@ if (!region_obj2) { return_VOID; } - region_context = region_obj2->extra.region_context; + region_context = ®ion_obj2->extra.region_context; /* Get the address handler from the region object */ @@ -450,7 +450,7 @@ region_setup = handler_obj->address_space.setup; status = region_setup (region_obj, ACPI_REGION_DEACTIVATE, - handler_obj->address_space.context, ®ion_context); + handler_obj->address_space.context, region_context); /* Init routine may fail, Just ignore errors */ diff -urN linux-2.4.22-bk20/drivers/acpi/pci_link.c linux-2.4.22-bk21/drivers/acpi/pci_link.c --- linux-2.4.22-bk20/drivers/acpi/pci_link.c 2003-08-25 04:44:41.000000000 -0700 +++ linux-2.4.22-bk21/drivers/acpi/pci_link.c 2003-09-18 03:06:15.000000000 -0700 @@ -216,7 +216,6 @@ return AE_CTRL_TERMINATE; } - static int acpi_pci_link_get_current ( struct acpi_pci_link *link) @@ -275,6 +274,28 @@ return_VALUE(result); } +static int +acpi_pci_link_try_get_current ( + struct acpi_pci_link *link, + int irq) +{ + int result; + + ACPI_FUNCTION_TRACE("acpi_pci_link_try_get_current"); + + result = acpi_pci_link_get_current(link); + if (result && link->irq.active) { + return_VALUE(result); + } + + if (!link->irq.active) { + ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "No active IRQ resource found\n")); + printk(KERN_WARNING "_CRS returns NULL! Using IRQ %d for device (%s [%s]).\n", irq, acpi_device_name(link->device), acpi_device_bid(link->device)); + link->irq.active = irq; + } + + return 0; +} static int acpi_pci_link_set ( @@ -290,7 +311,8 @@ struct acpi_buffer buffer = {sizeof(resource)+1, &resource}; int i = 0; int valid = 0; - + int resource_type = 0; + ACPI_FUNCTION_TRACE("acpi_pci_link_set"); if (!link || !irq) @@ -313,12 +335,23 @@ } } + /* If IRQ<=15, first try with a "normal" IRQ descriptor. If that fails, try with + * an extended one */ + if (irq <= 15) { + resource_type = ACPI_RSTYPE_IRQ; + } else { + resource_type = ACPI_RSTYPE_EXT_IRQ; + } + +retry_programming: + memset(&resource, 0, sizeof(resource)); /* NOTE: PCI interrupts are always level / active_low / shared. But not all interrupts > 15 are PCI interrupts. Rely on the ACPI IRQ definition for parameters */ - if (irq <= 15) { + switch(resource_type) { + case ACPI_RSTYPE_IRQ: resource.res.id = ACPI_RSTYPE_IRQ; resource.res.length = sizeof(struct acpi_resource); resource.res.data.irq.edge_level = link->irq.edge_level; @@ -326,8 +359,9 @@ resource.res.data.irq.shared_exclusive = ACPI_SHARED; resource.res.data.irq.number_of_interrupts = 1; resource.res.data.irq.interrupts[0] = irq; - } - else { + break; + + case ACPI_RSTYPE_EXT_IRQ: resource.res.id = ACPI_RSTYPE_EXT_IRQ; resource.res.length = sizeof(struct acpi_resource); resource.res.data.extended_irq.producer_consumer = ACPI_CONSUMER; @@ -337,11 +371,22 @@ resource.res.data.extended_irq.number_of_interrupts = 1; resource.res.data.extended_irq.interrupts[0] = irq; /* ignore resource_source, it's optional */ + break; } resource.end.id = ACPI_RSTYPE_END_TAG; /* Attempt to set the resource */ status = acpi_set_current_resources(link->handle, &buffer); + + + /* if we failed and IRQ <= 15, try again with an extended descriptor */ + if (ACPI_FAILURE(status) && (resource_type == ACPI_RSTYPE_IRQ)) { + resource_type = ACPI_RSTYPE_EXT_IRQ; + printk(PREFIX "Retrying with extended IRQ descriptor\n"); + goto retry_programming; + } + + /* check for total failure */ if (ACPI_FAILURE(status)) { ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Error evaluating _SRS\n")); return_VALUE(-ENODEV); @@ -359,7 +404,7 @@ } /* Make sure the active IRQ is the one we requested. */ - result = acpi_pci_link_get_current(link); + result = acpi_pci_link_try_get_current(link, irq); if (result) { return_VALUE(result); } @@ -573,10 +618,6 @@ else printk(" %d", link->irq.possible[i]); } - if (!link->irq.active) - printk(", disabled"); - else if (!found) - printk(", enabled at IRQ %d", link->irq.active); printk(")\n"); /* TBD: Acquire/release lock */ diff -urN linux-2.4.22-bk20/drivers/char/Config.in linux-2.4.22-bk21/drivers/char/Config.in --- linux-2.4.22-bk20/drivers/char/Config.in 2003-09-18 03:06:00.000000000 -0700 +++ linux-2.4.22-bk21/drivers/char/Config.in 2003-09-18 03:06:22.000000000 -0700 @@ -327,6 +327,7 @@ bool ' NVIDIA chipset support' CONFIG_AGP_NVIDIA fi if [ "$CONFIG_IA64" = "y" ]; then + bool ' Intel 460GX support' CONFIG_AGP_I460 bool ' HP ZX1 AGP support' CONFIG_AGP_HP_ZX1 fi bool ' ATI IGP chipset support' CONFIG_AGP_ATI diff -urN linux-2.4.22-bk20/drivers/char/agp/agp.h linux-2.4.22-bk21/drivers/char/agp/agp.h --- linux-2.4.22-bk20/drivers/char/agp/agp.h 2003-09-18 03:06:00.000000000 -0700 +++ linux-2.4.22-bk21/drivers/char/agp/agp.h 2003-09-18 03:06:22.000000000 -0700 @@ -256,6 +256,9 @@ #ifndef PCI_DEVICE_ID_INTEL_82443GX_1 #define PCI_DEVICE_ID_INTEL_82443GX_1 0x71a1 #endif +#ifndef PCI_DEVICE_ID_INTEL_460GX +#define PCI_DEVICE_ID_INTEL_460GX 0x84ea +#endif #ifndef PCI_DEVICE_ID_AMD_IRONGATE_0 #define PCI_DEVICE_ID_AMD_IRONGATE_0 0x7006 #endif @@ -331,6 +334,14 @@ #define INTEL_NBXCFG 0x50 #define INTEL_ERRSTS 0x91 +/* Intel 460GX Registers */ +#define INTEL_I460_APBASE 0x10 +#define INTEL_I460_BAPBASE 0x98 +#define INTEL_I460_GXBCTL 0xa0 +#define INTEL_I460_AGPSIZ 0xa2 +#define INTEL_I460_ATTBASE 0xfe200000 +#define INTEL_I460_GATT_VALID (1UL << 24) +#define INTEL_I460_GATT_COHERENT (1UL << 25) /* Intel 855GM/852GM registers */ #define I855_GMCH_CTRL 0x52 #define I855_GMCH_ENABLED 0x4 @@ -500,14 +511,16 @@ #define NVIDIA_3_APBASE 0x50 #define NVIDIA_3_APLIMIT 0x54 -/* HP ZX1 SBA registers */ -#define HP_ZX1_CTRL 0x200 +/* HP ZX1 IOC registers */ #define HP_ZX1_IBASE 0x300 #define HP_ZX1_IMASK 0x308 #define HP_ZX1_PCOM 0x310 #define HP_ZX1_TCNFG 0x318 #define HP_ZX1_PDIR_BASE 0x320 -#define HP_ZX1_CACHE_FLUSH 0x428 + +/* HP ZX1 LBA registers */ +#define HP_ZX1_AGP_STATUS 0x64 +#define HP_ZX1_AGP_COMMAND 0x68 /* ATI register */ #define ATI_APBASE 0x10 diff -urN linux-2.4.22-bk20/drivers/char/agp/agpgart_be.c linux-2.4.22-bk21/drivers/char/agp/agpgart_be.c --- linux-2.4.22-bk20/drivers/char/agp/agpgart_be.c 2003-09-18 03:06:00.000000000 -0700 +++ linux-2.4.22-bk21/drivers/char/agp/agpgart_be.c 2003-09-18 03:06:22.000000000 -0700 @@ -1427,9 +1427,605 @@ #endif /* CONFIG_AGP_I810 */ - #ifdef CONFIG_AGP_INTEL +#ifdef CONFIG_AGP_I460 -#endif /* CONFIG_AGP_I810 */ +/* BIOS configures the chipset so that one of two apbase registers are used */ +static u8 intel_i460_dynamic_apbase = 0x10; + +/* 460 supports multiple GART page sizes, so GART pageshift is dynamic */ +static u8 intel_i460_pageshift = 12; +static u32 intel_i460_pagesize; + +/* Keep track of which is larger, chipset or kernel page size. */ +static u32 intel_i460_cpk = 1; + +/* Structure for tracking partial use of 4MB GART pages */ +static u32 **i460_pg_detail = NULL; +static u32 *i460_pg_count = NULL; + +#define I460_CPAGES_PER_KPAGE (PAGE_SIZE >> intel_i460_pageshift) +#define I460_KPAGES_PER_CPAGE ((1 << intel_i460_pageshift) >> PAGE_SHIFT) + +#define I460_SRAM_IO_DISABLE (1 << 4) +#define I460_BAPBASE_ENABLE (1 << 3) +#define I460_AGPSIZ_MASK 0x7 +#define I460_4M_PS (1 << 1) + +#define log2(x) ffz(~(x)) + +static gatt_mask intel_i460_masks[] = +{ + { INTEL_I460_GATT_VALID | INTEL_I460_GATT_COHERENT, 0 } +}; + +static unsigned long intel_i460_mask_memory(unsigned long addr, int type) +{ + /* Make sure the returned address is a valid GATT entry */ + return (agp_bridge.masks[0].mask | (((addr & + ~((1 << intel_i460_pageshift) - 1)) & 0xffffff000) >> 12)); +} + +static unsigned long intel_i460_unmask_memory(unsigned long addr) +{ + /* Turn a GATT entry into a physical address */ + return ((addr & 0xffffff) << 12); +} + +static int intel_i460_fetch_size(void) +{ + int i; + u8 temp; + aper_size_info_8 *values; + + /* Determine the GART page size */ + pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &temp); + intel_i460_pageshift = (temp & I460_4M_PS) ? 22 : 12; + intel_i460_pagesize = 1UL << intel_i460_pageshift; + + values = A_SIZE_8(agp_bridge.aperture_sizes); + + pci_read_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, &temp); + + /* Exit now if the IO drivers for the GART SRAMS are turned off */ + if (temp & I460_SRAM_IO_DISABLE) { + printk(KERN_WARNING PFX "GART SRAMS disabled on 460GX chipset\n"); + printk(KERN_WARNING PFX "AGPGART operation not possible\n"); + return 0; + } + + /* Make sure we don't try to create an 2 ^ 23 entry GATT */ + if ((intel_i460_pageshift == 0) && ((temp & I460_AGPSIZ_MASK) == 4)) { + printk(KERN_WARNING PFX "We can't have a 32GB aperture with 4KB" + " GART pages\n"); + return 0; + } + + /* Determine the proper APBASE register */ + if (temp & I460_BAPBASE_ENABLE) + intel_i460_dynamic_apbase = INTEL_I460_BAPBASE; + else + intel_i460_dynamic_apbase = INTEL_I460_APBASE; + + for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { + + /* + * Dynamically calculate the proper num_entries and page_order + * values for the define aperture sizes. Take care not to + * shift off the end of values[i].size. + */ + values[i].num_entries = (values[i].size << 8) >> + (intel_i460_pageshift - 12); + values[i].page_order = log2((sizeof(u32)*values[i].num_entries) + >> PAGE_SHIFT); + } + + for (i = 0; i < agp_bridge.num_aperture_sizes; i++) { + /* Neglect control bits when matching up size_value */ + if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) { + agp_bridge.previous_size = + agp_bridge.current_size = (void *) (values + i); + agp_bridge.aperture_size_idx = i; + return values[i].size; + } + } + + return 0; +} + +/* There isn't anything to do here since 460 has no GART TLB. */ +static void intel_i460_tlb_flush(agp_memory * mem) +{ + return; +} + +/* + * This utility function is needed to prevent corruption of the control bits + * which are stored along with the aperture size in 460's AGPSIZ register + */ +static void intel_i460_write_agpsiz(u8 size_value) +{ + u8 temp; + + pci_read_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, &temp); + pci_write_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, + ((temp & ~I460_AGPSIZ_MASK) | size_value)); +} + +static void intel_i460_cleanup(void) +{ + aper_size_info_8 *previous_size; + + previous_size = A_SIZE_8(agp_bridge.previous_size); + intel_i460_write_agpsiz(previous_size->size_value); + + if (intel_i460_cpk == 0) { + vfree(i460_pg_detail); + vfree(i460_pg_count); + } +} + + +/* Control bits for Out-Of-GART coherency and Burst Write Combining */ +#define I460_GXBCTL_OOG (1UL << 0) +#define I460_GXBCTL_BWC (1UL << 2) + +static int intel_i460_configure(void) +{ + union { + u32 small[2]; + u64 large; + } temp; + u8 scratch; + int i; + + aper_size_info_8 *current_size; + + temp.large = 0; + + current_size = A_SIZE_8(agp_bridge.current_size); + intel_i460_write_agpsiz(current_size->size_value); + + /* + * Do the necessary rigmarole to read all eight bytes of APBASE. + * This has to be done since the AGP aperture can be above 4GB on + * 460 based systems. + */ + pci_read_config_dword(agp_bridge.dev, intel_i460_dynamic_apbase, + &(temp.small[0])); + pci_read_config_dword(agp_bridge.dev, intel_i460_dynamic_apbase + 4, + &(temp.small[1])); + + /* Clear BAR control bits */ + agp_bridge.gart_bus_addr = temp.large & ~((1UL << 3) - 1); + + pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &scratch); + pci_write_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, + (scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC); + + /* + * Initialize partial allocation trackers if a GART page is bigger than + * a kernel page. + */ + if (I460_CPAGES_PER_KPAGE >= 1) { + intel_i460_cpk = 1; + } else { + intel_i460_cpk = 0; + + i460_pg_detail = (void *) vmalloc(sizeof(*i460_pg_detail) * + current_size->num_entries); + i460_pg_count = (void *) vmalloc(sizeof(*i460_pg_count) * + current_size->num_entries); + + for (i = 0; i < current_size->num_entries; i++) { + i460_pg_count[i] = 0; + i460_pg_detail[i] = NULL; + } + } + + return 0; +} + +static int intel_i460_create_gatt_table(void) { + + char *table; + int i; + int page_order; + int num_entries; + void *temp; + unsigned int read_back; + + /* + * Load up the fixed address of the GART SRAMS which hold our + * GATT table. + */ + table = (char *) __va(INTEL_I460_ATTBASE); + + temp = agp_bridge.current_size; + page_order = A_SIZE_8(temp)->page_order; + num_entries = A_SIZE_8(temp)->num_entries; + + agp_bridge.gatt_table_real = (u32 *) table; + agp_bridge.gatt_table = ioremap_nocache(virt_to_phys(table), + (PAGE_SIZE * (1 << page_order))); + agp_bridge.gatt_bus_addr = virt_to_phys(agp_bridge.gatt_table_real); + + for (i = 0; i < num_entries; i++) { + agp_bridge.gatt_table[i] = 0; + } + + /* + * The 460 spec says we have to read the last location written to + * make sure that all writes have taken effect + */ + read_back = agp_bridge.gatt_table[i - 1]; + + return 0; +} + +static int intel_i460_free_gatt_table(void) +{ + int num_entries; + int i; + void *temp; + unsigned int read_back; + + temp = agp_bridge.current_size; + + num_entries = A_SIZE_8(temp)->num_entries; + + for (i = 0; i < num_entries; i++) { + agp_bridge.gatt_table[i] = 0; + } + + /* + * The 460 spec says we have to read the last location written to + * make sure that all writes have taken effect + */ + read_back = agp_bridge.gatt_table[i - 1]; + + iounmap(agp_bridge.gatt_table); + + return 0; +} + +/* These functions are called when PAGE_SIZE exceeds the GART page size */ + +static int intel_i460_insert_memory_cpk(agp_memory * mem, + off_t pg_start, int type) +{ + int i, j, k, num_entries; + void *temp; + unsigned long paddr; + unsigned int read_back; + + /* + * The rest of the kernel will compute page offsets in terms of + * PAGE_SIZE. + */ + pg_start = I460_CPAGES_PER_KPAGE * pg_start; + + temp = agp_bridge.current_size; + num_entries = A_SIZE_8(temp)->num_entries; + + if ((pg_start + I460_CPAGES_PER_KPAGE * mem->page_count) > num_entries) { + printk(KERN_WARNING PFX "Looks like we're out of AGP memory\n"); + return -EINVAL; + } + + j = pg_start; + while (j < (pg_start + I460_CPAGES_PER_KPAGE * mem->page_count)) { + if (!PGE_EMPTY(agp_bridge.gatt_table[j])) { + return -EBUSY; + } + j++; + } + + for (i = 0, j = pg_start; i < mem->page_count; i++) { + + paddr = mem->memory[i]; + + for (k = 0; k < I460_CPAGES_PER_KPAGE; k++, j++, paddr += intel_i460_pagesize) + agp_bridge.gatt_table[j] = (unsigned int) + agp_bridge.mask_memory(paddr, mem->type); + } + + /* + * The 460 spec says we have to read the last location written to + * make sure that all writes have taken effect + */ + read_back = agp_bridge.gatt_table[j - 1]; + + return 0; +} + +static int intel_i460_remove_memory_cpk(agp_memory * mem, off_t pg_start, + int type) +{ + int i; + unsigned int read_back; + + pg_start = I460_CPAGES_PER_KPAGE * pg_start; + + for (i = pg_start; i < (pg_start + I460_CPAGES_PER_KPAGE * + mem->page_count); i++) + agp_bridge.gatt_table[i] = 0; + + /* + * The 460 spec says we have to read the last location written to + * make sure that all writes have taken effect + */ + read_back = agp_bridge.gatt_table[i - 1]; + + return 0; +} + +/* + * These functions are called when the GART page size exceeds PAGE_SIZE. + * + * This situation is interesting since AGP memory allocations that are + * smaller than a single GART page are possible. The structures i460_pg_count + * and i460_pg_detail track partial allocation of the large GART pages to + * work around this issue. + * + * i460_pg_count[pg_num] tracks the number of kernel pages in use within + * GART page pg_num. i460_pg_detail[pg_num] is an array containing a + * psuedo-GART entry for each of the aforementioned kernel pages. The whole + * of i460_pg_detail is equivalent to a giant GATT with page size equal to + * that of the kernel. + */ + +static void *intel_i460_alloc_large_page(int pg_num) +{ + int i; + void *bp, *bp_end; + struct page *page; + + i460_pg_detail[pg_num] = (void *) vmalloc(sizeof(u32) * + I460_KPAGES_PER_CPAGE); + if (i460_pg_detail[pg_num] == NULL) { + printk(KERN_WARNING PFX "Out of memory, we're in trouble...\n"); + return NULL; + } + + for (i = 0; i < I460_KPAGES_PER_CPAGE; i++) + i460_pg_detail[pg_num][i] = 0; + + bp = (void *) __get_free_pages(GFP_KERNEL, + intel_i460_pageshift - PAGE_SHIFT); + if (bp == NULL) { + printk(KERN_WARNING PFX "Couldn't alloc 4M GART page...\n"); + return NULL; + } + + bp_end = bp + ((PAGE_SIZE * + (1 << (intel_i460_pageshift - PAGE_SHIFT))) - 1); + + for (page = virt_to_page(bp); page <= virt_to_page(bp_end); page++) { + atomic_inc(&page->count); + set_bit(PG_locked, &page->flags); + atomic_inc(&agp_bridge.current_memory_agp); + } + + return bp; +} + +static void intel_i460_free_large_page(int pg_num, unsigned long addr) +{ + struct page *page; + void *bp, *bp_end; + + bp = (void *) __va(addr); + bp_end = bp + (PAGE_SIZE * + (1 << (intel_i460_pageshift - PAGE_SHIFT))); + + vfree(i460_pg_detail[pg_num]); + i460_pg_detail[pg_num] = NULL; + + for (page = virt_to_page(bp); page < virt_to_page(bp_end); page++) { + put_page(page); + UnlockPage(page); + atomic_dec(&agp_bridge.current_memory_agp); + } + + free_pages((unsigned long) bp, intel_i460_pageshift - PAGE_SHIFT); +} + +static int intel_i460_insert_memory_kpc(agp_memory * mem, + off_t pg_start, int type) +{ + int i, pg, start_pg, end_pg, start_offset, end_offset, idx; + int num_entries; + void *temp; + unsigned int read_back; + unsigned long paddr; + + temp = agp_bridge.current_size; + num_entries = A_SIZE_8(temp)->num_entries; + + /* Figure out what pg_start means in terms of our large GART pages */ + start_pg = pg_start / I460_KPAGES_PER_CPAGE; + start_offset = pg_start % I460_KPAGES_PER_CPAGE; + end_pg = (pg_start + mem->page_count - 1) / + I460_KPAGES_PER_CPAGE; + end_offset = (pg_start + mem->page_count - 1) % + I460_KPAGES_PER_CPAGE; + + if (end_pg > num_entries) { + printk(KERN_WARNING PFX "Looks like we're out of AGP memory\n"); + return -EINVAL; + } + + /* Check if the requested region of the aperture is free */ + for (pg = start_pg; pg <= end_pg; pg++) { + /* Allocate new GART pages if necessary */ + if (i460_pg_detail[pg] == NULL) { + temp = intel_i460_alloc_large_page(pg); + if (temp == NULL) + return -ENOMEM; + agp_bridge.gatt_table[pg] = agp_bridge.mask_memory( + (unsigned long) temp, 0); + read_back = agp_bridge.gatt_table[pg]; + } + + for (idx = ((pg == start_pg) ? start_offset : 0); + idx < ((pg == end_pg) ? (end_offset + 1) + : I460_KPAGES_PER_CPAGE); + idx++) { + if(i460_pg_detail[pg][idx] != 0) + return -EBUSY; + } + } + + for (pg = start_pg, i = 0; pg <= end_pg; pg++) { + paddr = intel_i460_unmask_memory(agp_bridge.gatt_table[pg]); + for (idx = ((pg == start_pg) ? start_offset : 0); + idx < ((pg == end_pg) ? (end_offset + 1) + : I460_KPAGES_PER_CPAGE); + idx++, i++) { + mem->memory[i] = paddr + (idx * PAGE_SIZE); + i460_pg_detail[pg][idx] = + agp_bridge.mask_memory(mem->memory[i], mem->type); + + i460_pg_count[pg]++; + } + } + + return 0; +} + +static int intel_i460_remove_memory_kpc(agp_memory * mem, + off_t pg_start, int type) +{ + int i, pg, start_pg, end_pg, start_offset, end_offset, idx; + int num_entries; + void *temp; + unsigned int read_back; + unsigned long paddr; + + temp = agp_bridge.current_size; + num_entries = A_SIZE_8(temp)->num_entries; + + /* Figure out what pg_start means in terms of our large GART pages */ + start_pg = pg_start / I460_KPAGES_PER_CPAGE; + start_offset = pg_start % I460_KPAGES_PER_CPAGE; + end_pg = (pg_start + mem->page_count - 1) / + I460_KPAGES_PER_CPAGE; + end_offset = (pg_start + mem->page_count - 1) % + I460_KPAGES_PER_CPAGE; + + for (i = 0, pg = start_pg; pg <= end_pg; pg++) { + for (idx = ((pg == start_pg) ? start_offset : 0); + idx < ((pg == end_pg) ? (end_offset + 1) + : I460_KPAGES_PER_CPAGE); + idx++, i++) { + mem->memory[i] = 0; + i460_pg_detail[pg][idx] = 0; + i460_pg_count[pg]--; + } + + /* Free GART pages if they are unused */ + if (i460_pg_count[pg] == 0) { + paddr = intel_i460_unmask_memory(agp_bridge.gatt_table[pg]); + agp_bridge.gatt_table[pg] = agp_bridge.scratch_page; + read_back = agp_bridge.gatt_table[pg]; + + intel_i460_free_large_page(pg, paddr); + } + } + + return 0; +} + +/* Dummy routines to call the approriate {cpk,kpc} function */ + +static int intel_i460_insert_memory(agp_memory * mem, + off_t pg_start, int type) +{ + if (intel_i460_cpk) + return intel_i460_insert_memory_cpk(mem, pg_start, type); + else + return intel_i460_insert_memory_kpc(mem, pg_start, type); +} + +static int intel_i460_remove_memory(agp_memory * mem, + off_t pg_start, int type) +{ + if (intel_i460_cpk) + return intel_i460_remove_memory_cpk(mem, pg_start, type); + else + return intel_i460_remove_memory_kpc(mem, pg_start, type); +} + +/* + * If the kernel page size is smaller that the chipset page size, we don't + * want to allocate memory until we know where it is to be bound in the + * aperture (a multi-kernel-page alloc might fit inside of an already + * allocated GART page). Consequently, don't allocate or free anything + * if i460_cpk (meaning chipset pages per kernel page) isn't set. + * + * Let's just hope nobody counts on the allocated AGP memory being there + * before bind time (I don't think current drivers do)... + */ +static unsigned long intel_i460_alloc_page(void) +{ + if (intel_i460_cpk) + return agp_generic_alloc_page(); + + /* Returning NULL would cause problems */ + return ((unsigned long) ~0UL); +} + +static void intel_i460_destroy_page(unsigned long page) +{ + if (intel_i460_cpk) + agp_generic_destroy_page(page); +} + +static aper_size_info_8 intel_i460_sizes[3] = +{ + /* + * The 32GB aperture is only available with a 4M GART page size. + * Due to the dynamic GART page size, we can't figure out page_order + * or num_entries until runtime. + */ + {32768, 0, 0, 4}, + {1024, 0, 0, 2}, + {256, 0, 0, 1} +}; + +static int __init intel_i460_setup(struct pci_dev *pdev) +{ + agp_bridge.masks = intel_i460_masks; + agp_bridge.aperture_sizes = (void *) intel_i460_sizes; + agp_bridge.size_type = U8_APER_SIZE; + agp_bridge.num_aperture_sizes = 3; + agp_bridge.dev_private_data = NULL; + agp_bridge.needs_scratch_page = FALSE; + agp_bridge.configure = intel_i460_configure; + agp_bridge.fetch_size = intel_i460_fetch_size; + agp_bridge.cleanup = intel_i460_cleanup; + agp_bridge.tlb_flush = intel_i460_tlb_flush; + agp_bridge.mask_memory = intel_i460_mask_memory; + agp_bridge.agp_enable = agp_generic_agp_enable; + agp_bridge.cache_flush = global_cache_flush; + agp_bridge.create_gatt_table = intel_i460_create_gatt_table; + agp_bridge.free_gatt_table = intel_i460_free_gatt_table; + agp_bridge.insert_memory = intel_i460_insert_memory; + agp_bridge.remove_memory = intel_i460_remove_memory; + agp_bridge.alloc_by_type = agp_generic_alloc_by_type; + agp_bridge.free_by_type = agp_generic_free_by_type; + agp_bridge.agp_alloc_page = intel_i460_alloc_page; + agp_bridge.agp_destroy_page = intel_i460_destroy_page; + agp_bridge.suspend = agp_generic_suspend; + agp_bridge.resume = agp_generic_resume; + agp_bridge.cant_use_aperture = 1; + + return 0; + + (void) pdev; /* unused */ +} + +#endif /* CONFIG_AGP_I460 */ #ifdef CONFIG_AGP_INTEL @@ -4442,6 +5038,8 @@ #define log2(x) ffz(~(x)) #endif +#define HP_ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */ + #define HP_ZX1_IOVA_BASE GB(1UL) #define HP_ZX1_IOVA_SIZE GB(1UL) #define HP_ZX1_GART_SIZE (HP_ZX1_IOVA_SIZE / 2) @@ -4451,19 +5049,16 @@ #define HP_ZX1_IOVA_TO_PDIR(va) ((va - hp_private.iova_base) >> \ hp_private.io_tlb_shift) +static int hp_zx1_gart_found; + static aper_size_info_fixed hp_zx1_sizes[] = { {0, 0, 0}, /* filled in by hp_zx1_fetch_size() */ }; -static gatt_mask hp_zx1_masks[] = -{ - {HP_ZX1_PDIR_VALID_BIT, 0} -}; - static struct _hp_private { - struct pci_dev *ioc; - volatile u8 *registers; + volatile u8 *ioc_regs; + volatile u8 *lba_regs; u64 *io_pdir; // PDIR for entire IOVA u64 *gatt; // PDIR just for GART (subset of above) u64 gatt_entries; @@ -4490,7 +5085,7 @@ * - IOVA space is 1Gb in size * - first 512Mb is IOMMU, second 512Mb is GART */ - hp->io_tlb_ps = INREG64(hp->registers, HP_ZX1_TCNFG); + hp->io_tlb_ps = INREG64(hp->ioc_regs, HP_ZX1_TCNFG); switch (hp->io_tlb_ps) { case 0: hp->io_tlb_shift = 12; break; case 1: hp->io_tlb_shift = 13; break; @@ -4506,13 +5101,13 @@ hp->io_page_size = 1 << hp->io_tlb_shift; hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size; - hp->iova_base = INREG64(hp->registers, HP_ZX1_IBASE) & ~0x1; + hp->iova_base = INREG64(hp->ioc_regs, HP_ZX1_IBASE) & ~0x1; hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - HP_ZX1_GART_SIZE; hp->gart_size = HP_ZX1_GART_SIZE; hp->gatt_entries = hp->gart_size / hp->io_page_size; - hp->io_pdir = phys_to_virt(INREG64(hp->registers, HP_ZX1_PDIR_BASE)); + hp->io_pdir = phys_to_virt(INREG64(hp->ioc_regs, HP_ZX1_PDIR_BASE)); hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)]; if (hp->gatt[0] != HP_ZX1_SBA_IOMMU_COOKIE) { @@ -4526,7 +5121,7 @@ return 0; } -static int __init hp_zx1_ioc_owner(u8 ioc_rev) +static int __init hp_zx1_ioc_owner(void) { struct _hp_private *hp = &hp_private; @@ -4561,44 +5156,21 @@ return 0; } -static int __init hp_zx1_ioc_init(void) +static int __init hp_zx1_ioc_init(u64 ioc_hpa, u64 lba_hpa) { struct _hp_private *hp = &hp_private; - struct pci_dev *ioc; - int i; - u8 ioc_rev; - ioc = pci_find_device(PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_ZX1_IOC, NULL); - if (!ioc) { - printk(KERN_ERR PFX "Detected HP ZX1 AGP bridge but no IOC\n"); - return -ENODEV; - } - hp->ioc = ioc; - - pci_read_config_byte(ioc, PCI_REVISION_ID, &ioc_rev); - - for (i = 0; i < PCI_NUM_RESOURCES; i++) { - if (pci_resource_flags(ioc, i) == IORESOURCE_MEM) { - hp->registers = (u8 *) ioremap(pci_resource_start(ioc, - i), - pci_resource_len(ioc, i)); - break; - } - } - if (!hp->registers) { - printk(KERN_ERR PFX "Detected HP ZX1 AGP bridge but no CSRs\n"); - - return -ENODEV; - } + hp->ioc_regs = ioremap(ioc_hpa, 1024); + hp->lba_regs = ioremap(lba_hpa, 256); /* * If the IOTLB is currently disabled, we can take it over. * Otherwise, we have to share with sba_iommu. */ - hp->io_pdir_owner = (INREG64(hp->registers, HP_ZX1_IBASE) & 0x1) == 0; + hp->io_pdir_owner = (INREG64(hp->ioc_regs, HP_ZX1_IBASE) & 0x1) == 0; if (hp->io_pdir_owner) - return hp_zx1_ioc_owner(ioc_rev); + return hp_zx1_ioc_owner(); return hp_zx1_ioc_shared(); } @@ -4618,19 +5190,17 @@ struct _hp_private *hp = &hp_private; agp_bridge.gart_bus_addr = hp->gart_base; - agp_bridge.capndx = pci_find_capability(agp_bridge.dev, PCI_CAP_ID_AGP); - pci_read_config_dword(agp_bridge.dev, - agp_bridge.capndx + PCI_AGP_STATUS, &agp_bridge.mode); + agp_bridge.mode = INREG32(hp->lba_regs, HP_ZX1_AGP_STATUS); if (hp->io_pdir_owner) { - OUTREG64(hp->registers, HP_ZX1_PDIR_BASE, + OUTREG64(hp->ioc_regs, HP_ZX1_PDIR_BASE, virt_to_phys(hp->io_pdir)); - OUTREG64(hp->registers, HP_ZX1_TCNFG, hp->io_tlb_ps); - OUTREG64(hp->registers, HP_ZX1_IMASK, ~(HP_ZX1_IOVA_SIZE - 1)); - OUTREG64(hp->registers, HP_ZX1_IBASE, hp->iova_base | 0x1); - OUTREG64(hp->registers, HP_ZX1_PCOM, + OUTREG64(hp->ioc_regs, HP_ZX1_TCNFG, hp->io_tlb_ps); + OUTREG64(hp->ioc_regs, HP_ZX1_IMASK, ~(HP_ZX1_IOVA_SIZE - 1)); + OUTREG64(hp->ioc_regs, HP_ZX1_IBASE, hp->iova_base | 0x1); + OUTREG64(hp->ioc_regs, HP_ZX1_PCOM, hp->iova_base | log2(HP_ZX1_IOVA_SIZE)); - INREG64(hp->registers, HP_ZX1_PCOM); + INREG64(hp->ioc_regs, HP_ZX1_PCOM); } return 0; @@ -4641,17 +5211,18 @@ struct _hp_private *hp = &hp_private; if (hp->io_pdir_owner) - OUTREG64(hp->registers, HP_ZX1_IBASE, 0); - iounmap((void *) hp->registers); + OUTREG64(hp->ioc_regs, HP_ZX1_IBASE, 0); + iounmap((void *) hp->ioc_regs); + iounmap((void *) hp->lba_regs); } static void hp_zx1_tlbflush(agp_memory * mem) { struct _hp_private *hp = &hp_private; - OUTREG64(hp->registers, HP_ZX1_PCOM, + OUTREG64(hp->ioc_regs, HP_ZX1_PCOM, hp->gart_base | log2(hp->gart_size)); - INREG64(hp->registers, HP_ZX1_PCOM); + INREG64(hp->ioc_regs, HP_ZX1_PCOM); } static int hp_zx1_create_gatt_table(void) @@ -4718,11 +5289,6 @@ j++; } - if (mem->is_flushed == FALSE) { - CACHE_FLUSH(); - mem->is_flushed = TRUE; - } - for (i = 0, j = io_pg_start; i < mem->page_count; i++) { unsigned long paddr; @@ -4762,14 +5328,23 @@ return HP_ZX1_PDIR_VALID_BIT | addr; } -static unsigned long hp_zx1_unmask_memory(unsigned long addr) +static void hp_zx1_agp_enable(u32 mode) { - return addr & ~(HP_ZX1_PDIR_VALID_BIT); + struct _hp_private *hp = &hp_private; + u32 command; + + command = INREG32(hp->lba_regs, HP_ZX1_AGP_STATUS); + + command = agp_collect_device_status(mode, command); + command |= 0x00000100; + + OUTREG32(hp->lba_regs, HP_ZX1_AGP_COMMAND, command); + + agp_device_command(command, 0); } -static int __init hp_zx1_setup (struct pci_dev *pdev) +static int __init hp_zx1_setup(u64 ioc_hpa, u64 lba_hpa) { - agp_bridge.masks = hp_zx1_masks; agp_bridge.dev_private_data = NULL; agp_bridge.size_type = FIXED_APER_SIZE; agp_bridge.needs_scratch_page = FALSE; @@ -4778,8 +5353,7 @@ agp_bridge.cleanup = hp_zx1_cleanup; agp_bridge.tlb_flush = hp_zx1_tlbflush; agp_bridge.mask_memory = hp_zx1_mask_memory; - agp_bridge.unmask_memory = hp_zx1_unmask_memory; - agp_bridge.agp_enable = agp_generic_agp_enable; + agp_bridge.agp_enable = hp_zx1_agp_enable; agp_bridge.cache_flush = global_cache_flush; agp_bridge.create_gatt_table = hp_zx1_create_gatt_table; agp_bridge.free_gatt_table = hp_zx1_free_gatt_table; @@ -4790,10 +5364,76 @@ agp_bridge.agp_alloc_page = agp_generic_alloc_page; agp_bridge.agp_destroy_page = agp_generic_destroy_page; agp_bridge.cant_use_aperture = 1; + agp_bridge.type = HP_ZX1; - return hp_zx1_ioc_init(); + fake_bridge_dev.vendor = PCI_VENDOR_ID_HP; + fake_bridge_dev.device = PCI_DEVICE_ID_HP_PCIX_LBA; - (void) pdev; /* unused */ + return hp_zx1_ioc_init(ioc_hpa, lba_hpa); +} + +static acpi_status __init hp_zx1_gart_probe(acpi_handle obj, u32 depth, void *context, void **ret) +{ + acpi_handle handle, parent; + acpi_status status; + struct acpi_buffer buffer; + struct acpi_device_info *info; + u64 lba_hpa, sba_hpa, length; + int match; + + status = acpi_hp_csr_space(obj, &lba_hpa, &length); + if (ACPI_FAILURE(status)) + return AE_OK; + + /* Look for an enclosing IOC scope and find its CSR space */ + handle = obj; + do { + buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER; + status = acpi_get_object_info(handle, &buffer); + if (ACPI_SUCCESS(status)) { + /* TBD check _CID also */ + info = buffer.pointer; + info->hardware_id.value[sizeof(info->hardware_id)-1] = '\0'; + match = (strcmp(info->hardware_id.value, "HWP0001") == 0); + ACPI_MEM_FREE(info); + if (match) { + status = acpi_hp_csr_space(handle, &sba_hpa, &length); + if (ACPI_SUCCESS(status)) + break; + else { + printk(KERN_ERR PFX "Detected HP ZX1 " + "AGP LBA but no IOC.\n"); + return AE_OK; + } + } + } + + status = acpi_get_parent(handle, &parent); + handle = parent; + } while (ACPI_SUCCESS(status)); + + if (hp_zx1_setup(sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa)) + return AE_OK; + + printk(KERN_INFO PFX "Detected HP ZX1 %s AGP chipset (ioc=%lx, lba=%lx)\n", + (char *) context, sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa); + + hp_zx1_gart_found = 1; + return AE_CTRL_TERMINATE; +} + +static int __init +hp_zx1_gart_init(void) +{ + acpi_get_devices("HWP0003", hp_zx1_gart_probe, "HWP0003", NULL); + if (hp_zx1_gart_found) + return 0; + + acpi_get_devices("HWP0007", hp_zx1_gart_probe, "HWP0007", NULL); + if (hp_zx1_gart_found) + return 0; + + return -ENODEV; } #endif /* CONFIG_AGP_HP_ZX1 */ @@ -5432,6 +6072,15 @@ #endif /* CONFIG_AGP_INTEL */ +#ifdef CONFIG_AGP_I460 + { PCI_DEVICE_ID_INTEL_460GX, + PCI_VENDOR_ID_INTEL, + INTEL_460GX, + "Intel", + "460GX", + intel_i460_setup }, +#endif + #ifdef CONFIG_AGP_SIS { PCI_DEVICE_ID_SI_740, PCI_VENDOR_ID_SI, @@ -5645,15 +6294,6 @@ nvidia_generic_setup }, #endif /* CONFIG_AGP_NVIDIA */ -#ifdef CONFIG_AGP_HP_ZX1 - { PCI_DEVICE_ID_HP_ZX1_LBA, - PCI_VENDOR_ID_HP, - HP_ZX1, - "HP", - "ZX1", - hp_zx1_setup }, -#endif - #ifdef CONFIG_AGP_ATI { PCI_DEVICE_ID_ATI_RS100, PCI_VENDOR_ID_ATI, @@ -5785,6 +6425,11 @@ struct pci_dev *dev = NULL; u8 cap_ptr = 0x00; +#ifdef CONFIG_AGP_HP_ZX1 + if (hp_zx1_gart_init() == 0) + return 0; +#endif + if ((dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) == NULL) return -ENODEV; @@ -6058,23 +6703,6 @@ #endif /* CONFIG_AGP_SWORKS */ -#ifdef CONFIG_AGP_HP_ZX1 - if (dev->vendor == PCI_VENDOR_ID_HP) { - do { - /* ZX1 LBAs can be either PCI or AGP bridges */ - if (pci_find_capability(dev, PCI_CAP_ID_AGP)) { - printk(KERN_INFO PFX "Detected HP ZX1 AGP " - "chipset at %s\n", dev->slot_name); - agp_bridge.type = HP_ZX1; - agp_bridge.dev = dev; - return hp_zx1_setup(dev); - } - dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, dev); - } while (dev); - return -ENODEV; - } -#endif /* CONFIG_AGP_HP_ZX1 */ - /* find capndx */ cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP); if (cap_ptr == 0x00) diff -urN linux-2.4.22-bk20/drivers/char/drm-4.0/agpsupport.c linux-2.4.22-bk21/drivers/char/drm-4.0/agpsupport.c --- linux-2.4.22-bk20/drivers/char/drm-4.0/agpsupport.c 2003-09-18 03:06:00.000000000 -0700 +++ linux-2.4.22-bk21/drivers/char/drm-4.0/agpsupport.c 2003-09-18 03:06:22.000000000 -0700 @@ -264,6 +264,7 @@ #if LINUX_VERSION_CODE >= 0x020400 case INTEL_I840: head->chipset = "Intel i840"; break; #endif + case INTEL_460GX: head->chipset = "Intel 460GX"; break; case VIA_GENERIC: head->chipset = "VIA"; break; case VIA_VP3: head->chipset = "VIA VP3"; break; @@ -300,6 +301,7 @@ break; case SVWRKS_HE: head->chipset = "Serverworks HE"; break; case SVWRKS_LE: head->chipset = "Serverworks LE"; break; + case HP_ZX1: head->chipset = "HP ZX1"; break; default: head->chipset = "Unknown"; break; } diff -urN linux-2.4.22-bk20/drivers/ide/ide-tape.c linux-2.4.22-bk21/drivers/ide/ide-tape.c --- linux-2.4.22-bk20/drivers/ide/ide-tape.c 2003-06-13 07:51:33.000000000 -0700 +++ linux-2.4.22-bk21/drivers/ide/ide-tape.c 2003-09-18 03:06:22.000000000 -0700 @@ -1,5 +1,5 @@ /* - * linux/drivers/ide/ide-tape.c Version 1.17b Dec, 2002 + * linux/drivers/ide/ide-tape.c Version 1.17c Sep, 2003 * * Copyright (C) 1995 - 1999 Gadi Oxman * @@ -313,6 +313,9 @@ * Cosmetic fixes to miscellaneous debugging output messages. * Set the minimum /proc/ide/hd?/settings values for "pipeline", * "pipeline_min", and "pipeline_max" to 1. + * Ver 1.17c Sep 2003 Stuart Hayes + * Initialized "feature" in idetape_issue_packet_command + * (this was causing lockups on certain systems) * * Here are some words from the first releases of hd.c, which are quoted * in ide.c and apply here as well: @@ -422,7 +425,7 @@ * sharing a (fast) ATA-2 disk with any (slow) new ATAPI device. */ -#define IDETAPE_VERSION "1.17b-ac1" +#define IDETAPE_VERSION "1.17c" #include #include @@ -2367,6 +2370,8 @@ atapi_feature_t feature; atapi_bcount_t bcount; + feature.all = 0; + #if IDETAPE_DEBUG_BUGS if (tape->pc->c[0] == IDETAPE_REQUEST_SENSE_CMD && pc->c[0] == IDETAPE_REQUEST_SENSE_CMD) { diff -urN linux-2.4.22-bk20/drivers/scsi/ide-scsi.c linux-2.4.22-bk21/drivers/scsi/ide-scsi.c --- linux-2.4.22-bk20/drivers/scsi/ide-scsi.c 2003-08-25 04:44:42.000000000 -0700 +++ linux-2.4.22-bk21/drivers/scsi/ide-scsi.c 2003-09-18 03:06:23.000000000 -0700 @@ -531,6 +531,8 @@ atapi_bcount_t bcount; struct request *rq = pc->rq; + feature.all = 0; + /* Set the current packet command */ scsi->pc = pc; /* We haven't transferred any data yet */ @@ -539,6 +541,7 @@ /* Request to transfer the entire buffer at once */ bcount.all = IDE_MIN(pc->request_transfer, 63 * 1024); + if (drive->using_dma && rq->bh) { if (test_bit(PC_WRITING, &pc->flags)) feature.b.dma = !HWIF(drive)->ide_dma_write(drive); diff -urN linux-2.4.22-bk20/include/acpi/acconfig.h linux-2.4.22-bk21/include/acpi/acconfig.h --- linux-2.4.22-bk20/include/acpi/acconfig.h 2003-08-25 04:44:43.000000000 -0700 +++ linux-2.4.22-bk21/include/acpi/acconfig.h 2003-09-18 03:06:23.000000000 -0700 @@ -64,7 +64,7 @@ /* Version string */ -#define ACPI_CA_VERSION 0x20030813 +#define ACPI_CA_VERSION 0x20030916 /* Maximum objects in the various object caches */ diff -urN linux-2.4.22-bk20/include/linux/agp_backend.h linux-2.4.22-bk21/include/linux/agp_backend.h --- linux-2.4.22-bk20/include/linux/agp_backend.h 2003-09-18 03:06:04.000000000 -0700 +++ linux-2.4.22-bk21/include/linux/agp_backend.h 2003-09-18 03:06:23.000000000 -0700 @@ -57,6 +57,7 @@ INTEL_I865_G, INTEL_I7205, INTEL_I7505, + INTEL_460GX, VIA_GENERIC, VIA_VP3, VIA_MVP3,