## Automatically generated incremental diff
## From:   linux-2.4.22-bk24
## To:     linux-2.4.22-bk25
## Robot:  $Id: make-incremental-diff,v 1.11 2002/02/20 02:59:33 hpa Exp $

diff -urN linux-2.4.22-bk24/Documentation/networking/atm.txt linux-2.4.22-bk25/Documentation/networking/atm.txt
--- linux-2.4.22-bk24/Documentation/networking/atm.txt	2000-02-08 18:23:13.000000000 -0800
+++ linux-2.4.22-bk25/Documentation/networking/atm.txt	2003-09-26 02:49:43.000000000 -0700
@@ -1,8 +1,8 @@
 In order to use anything but the most primitive functions of ATM,
 several user-mode programs are required to assist the kernel. These
 programs and related material can be found via the ATM on Linux Web
-page at http://icawww1.epfl.ch/linux-atm/
+page at http://linux-atm.sourceforge.net/
 
 If you encounter problems with ATM, please report them on the ATM
 on Linux mailing list. Subscription information, archives, etc.,
-can be found on http://icawww1.epfl.ch/linux-atm/
+can be found on http://linux-atm.sourceforge.net/
diff -urN linux-2.4.22-bk24/Makefile linux-2.4.22-bk25/Makefile
--- linux-2.4.22-bk24/Makefile	2003-09-26 02:49:35.000000000 -0700
+++ linux-2.4.22-bk25/Makefile	2003-09-26 02:49:43.000000000 -0700
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 4
 SUBLEVEL = 22
-EXTRAVERSION = -bk24
+EXTRAVERSION = -bk25
 
 KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 
diff -urN linux-2.4.22-bk24/arch/alpha/Makefile linux-2.4.22-bk25/arch/alpha/Makefile
--- linux-2.4.22-bk24/arch/alpha/Makefile	2002-08-02 17:39:42.000000000 -0700
+++ linux-2.4.22-bk25/arch/alpha/Makefile	2003-09-26 02:49:43.000000000 -0700
@@ -131,3 +131,6 @@
 
 bootpfile:
 	@$(MAKEBOOT) bootpfile
+
+bootpzfile:
+	@$(MAKEBOOT) bootpzfile
diff -urN linux-2.4.22-bk24/arch/alpha/boot/Makefile linux-2.4.22-bk25/arch/alpha/boot/Makefile
--- linux-2.4.22-bk24/arch/alpha/boot/Makefile	2001-10-04 18:47:08.000000000 -0700
+++ linux-2.4.22-bk25/arch/alpha/boot/Makefile	2003-09-26 02:49:43.000000000 -0700
@@ -7,6 +7,21 @@
 #
 # Copyright (C) 1994 by Linus Torvalds
 #
+# Creating a compressed kernel image (arch/alpha/boot/vmlinux.gz)
+# is done via:
+#
+#	make boot
+#
+# Creating a BOOTP image (arch/alpha/boot/bootpfile or bootpzfile)
+# is done via:
+#
+#	make bootpfile		# using an uncompressed kernel
+#	make bootpzfile		# using a compressed kernel
+#
+# Adding an INITRD image to a BOOTP file (arch/alpha/boot/bootpzfile)
+# can be done, e.g, via:
+#
+# INITRD=`pwd`/initrd.img make bootpzfile
 
 LINKFLAGS = -static -T bootloader.lds #-N -relax
 
@@ -17,6 +32,7 @@
 
 OBJECTS = head.o main.o
 BPOBJECTS = head.o bootp.o
+BPZOBJECTS = head.o bootpz.o misc.o
 TARGETS = vmlinux.gz tools/objstrip # also needed by aboot & milo
 VMLINUX = $(TOPDIR)/vmlinux
 OBJSTRIP = tools/objstrip
@@ -41,6 +57,12 @@
 	cat $(INITRD) >> bootpfile
 endif
 
+bootpzfile:	tools/bootpzh vmlinux.nh.gz
+	cat tools/bootpzh vmlinux.nh.gz > bootpzfile
+ifdef INITRD
+	cat $(INITRD) >> bootpzfile
+endif
+
 srmboot:	bootdevice bootimage
 	dd if=bootimage of=$(BOOTDEV) bs=512 seek=1 skip=1
 	tools/mkbb $(BOOTDEV) tools/lxboot
@@ -48,16 +70,31 @@
 bootdevice:
 	@test "$(BOOTDEV)" != ""  || (echo You must specify BOOTDEV ; exit -1)
 
-vmlinux.gz: vmlinux
-	gzip -fv9 vmlinux
+vmlinux.gz: $(TOPDIR)/vmlinux
+	gzip -fv9c $(TOPDIR)/vmlinux > vmlinux.gz
+
+vmlinux.nh.gz: vmlinux.nh
+	gzip -fv9c vmlinux.nh > vmlinux.nh.gz
 
 main.o: ksize.h
 
 bootp.o: ksize.h
 
+bootpz.o: kzsize.h
+
 ksize.h: vmlinux.nh dummy
 	echo "#define KERNEL_SIZE `ls -l vmlinux.nh | awk '{print $$5}'`" > $@T
 ifdef INITRD
+	[ ! \( -f $(INITRD) \) ] || exit 1
+	echo "#define INITRD_IMAGE_SIZE `ls -l $(INITRD) | awk '{print $$5}'`" >> $@T
+endif
+	cmp -s $@T $@ || mv -f $@T $@
+	rm -f $@T
+
+kzsize.h: vmlinux.nh.gz dummy
+	echo "#define KERNEL_SIZE `ls -l vmlinux.nh | awk '{print $$5}'`" > $@T
+	echo "#define KERNEL_Z_SIZE `ls -l vmlinux.nh.gz | awk '{print $$5}'`" >> $@T
+ifdef INITRD
 	[ -f $(INITRD) ] || exit 1
 	echo "#define INITRD_IMAGE_SIZE `ls -l $(INITRD) | awk '{print $$5}'`" >> $@T
 endif
@@ -67,7 +104,7 @@
 vmlinux.nh: $(VMLINUX) $(OBJSTRIP)
 	$(OBJSTRIP) -v $(VMLINUX) vmlinux.nh
 
-vmlinux: $(TOPDIR)/vmlinux
+vmlinux: $(VMLINUX)
 	$(STRIP) -o vmlinux $(VMLINUX)
 
 tools/lxboot: $(OBJSTRIP) bootloader
@@ -79,6 +116,9 @@
 tools/bootph: bootpheader $(OBJSTRIP)
 	$(OBJSTRIP) -vb bootpheader tools/bootph
 
+tools/bootpzh: bootpzheader $(OBJSTRIP)
+	$(OBJSTRIP) -vb bootpzheader tools/bootpzh
+
 $(OBJSTRIP): $(OBJSTRIP).c
 	$(HOSTCC) $(HOSTCFLAGS) -I$(HPATH) $(OBJSTRIP).c -o $(OBJSTRIP)
 
@@ -91,6 +131,11 @@
 bootpheader: $(BPOBJECTS)
 	$(LD) $(LINKFLAGS) $(BPOBJECTS) $(LIBS) -o bootpheader
 
+bootpzheader: $(BPZOBJECTS)
+	$(LD) $(LINKFLAGS) $(BPZOBJECTS) $(LIBS) -o bootpzheader
+
+misc.o: misc.c $(TOPDIR)/lib/inflate.c
+
 clean:
 	rm -f $(TARGETS) bootloader bootimage bootpfile bootpheader
 	rm -f tools/mkbb tools/bootlx tools/lxboot tools/bootph
diff -urN linux-2.4.22-bk24/arch/alpha/boot/bootpz.c linux-2.4.22-bk25/arch/alpha/boot/bootpz.c
--- linux-2.4.22-bk24/arch/alpha/boot/bootpz.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-2.4.22-bk25/arch/alpha/boot/bootpz.c	2003-09-26 02:49:43.000000000 -0700
@@ -0,0 +1,447 @@
+/*
+ * arch/alpha/boot/bootpz.c
+ *
+ * Copyright (C) 1997 Jay Estabrook
+ *
+ * This file is used for creating a compressed BOOTP file for the
+ * Linux/AXP kernel
+ *
+ * based significantly on the arch/alpha/boot/main.c of Linus Torvalds
+ * and the decompression code from MILO.
+ */
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/version.h>
+#include <linux/mm.h>
+
+#include <asm/system.h>
+#include <asm/console.h>
+#include <asm/hwrpb.h>
+#include <asm/pgtable.h>
+#include <asm/io.h>
+
+#include <stdarg.h>
+
+#include "kzsize.h"
+
+/* FIXME FIXME FIXME */
+#define MALLOC_AREA_SIZE 0x200000 /* 2MB for now */
+/* FIXME FIXME FIXME */
+
+
+#undef DEBUG_CHECK_RANGE
+#define DEBUG_ADDRESSES
+
+#define DEBUG_SP(x) \
+    {register long sp asm("30"); srm_printk("%s (sp=%lx)\n", x, sp);}
+
+extern unsigned long switch_to_osf_pal(unsigned long nr,
+	struct pcb_struct * pcb_va, struct pcb_struct * pcb_pa,
+	unsigned long *vptb);
+
+extern int decompress_kernel(void* destination, void *source,
+			     size_t ksize, size_t kzsize);
+
+struct hwrpb_struct *hwrpb = INIT_HWRPB;
+static struct pcb_struct pcb_va[1];
+
+/*
+ * Find a physical address of a virtual object..
+ *
+ * This is easy using the virtual page table address.
+ */
+#define VPTB	((unsigned long *) 0x200000000)
+
+static inline unsigned long
+find_pa(unsigned long address)
+{
+	unsigned long result;
+
+	result = VPTB[address >> 13];
+	result >>= 32;
+	result <<= 13;
+	result |= address & 0x1fff;
+	return result;
+}	
+
+int
+check_range(unsigned long vstart, unsigned long vend,
+	    unsigned long kstart, unsigned long kend)
+{
+	unsigned long vaddr, kaddr;
+
+#ifdef DEBUG_CHECK_RANGE
+	srm_printk("check_range: V[0x%lx:0x%lx] K[0x%lx:0x%lx]\n",
+		   vstart, vend, kstart, kend);
+#endif
+	/* do some range checking for detecting an overlap... */
+	for (vaddr = vstart; vaddr <= vend; vaddr += PAGE_SIZE)
+	{
+		kaddr = (find_pa(vaddr) | PAGE_OFFSET);
+		if (kaddr >= kstart && kaddr <= kend)
+		{
+#ifdef DEBUG_CHECK_RANGE
+			srm_printk("OVERLAP: vaddr 0x%lx kaddr 0x%lx"
+				   " [0x%lx:0x%lx]\n",
+				   vaddr, kaddr, kstart, kend);
+#endif
+			return 1;
+		}
+	}
+	return 0;
+}
+
+/*
+ * This function moves into OSF/1 pal-code, and has a temporary
+ * PCB for that. The kernel proper should replace this PCB with
+ * the real one as soon as possible.
+ *
+ * The page table muckery in here depends on the fact that the boot
+ * code has the L1 page table identity-map itself in the second PTE
+ * in the L1 page table. Thus the L1-page is virtually addressable
+ * itself (through three levels) at virtual address 0x200802000.
+ */
+
+#define L1	((unsigned long *) 0x200802000)
+
+void
+pal_init(void)
+{
+	unsigned long i, rev;
+	struct percpu_struct * percpu;
+	struct pcb_struct * pcb_pa;
+
+	/* Create the dummy PCB.  */
+	pcb_va->ksp = 0;
+	pcb_va->usp = 0;
+	pcb_va->ptbr = L1[1] >> 32;
+	pcb_va->asn = 0;
+	pcb_va->pcc = 0;
+	pcb_va->unique = 0;
+	pcb_va->flags = 1;
+	pcb_va->res1 = 0;
+	pcb_va->res2 = 0;
+	pcb_pa = (struct pcb_struct *)find_pa((unsigned long)pcb_va);
+
+	/*
+	 * a0 = 2 (OSF)
+	 * a1 = return address, but we give the asm the vaddr of the PCB
+	 * a2 = physical addr of PCB
+	 * a3 = new virtual page table pointer
+	 * a4 = KSP (but the asm sets it)
+	 */
+	srm_printk("Switching to OSF PAL-code... ");
+
+	i = switch_to_osf_pal(2, pcb_va, pcb_pa, VPTB);
+	if (i) {
+		srm_printk("failed, code %ld\n", i);
+		__halt();
+	}
+
+	percpu = (struct percpu_struct *)
+		(INIT_HWRPB->processor_offset + (unsigned long) INIT_HWRPB);
+	rev = percpu->pal_revision = percpu->palcode_avail[2];
+
+	srm_printk("OK (rev %lx)\n", rev);
+
+	tbia(); /* do it directly in case we are SMP */
+}
+
+/*
+ * Start the kernel.
+ */
+static inline void
+runkernel(void)
+{
+	__asm__ __volatile__(
+		"bis %1,%1,$30\n\t"
+		"bis %0,%0,$27\n\t"
+		"jmp ($27)"
+		: /* no outputs: it doesn't even return */
+		: "r" (START_ADDR),
+		  "r" (PAGE_SIZE + INIT_STACK));
+}
+
+/* Must record the SP (it is virtual) on entry, so we can make sure
+   not to overwrite it during movement or decompression. */
+unsigned long SP_on_entry;
+
+/* Calculate the kernel image address based on the end of the BOOTP
+   bootstrapper (ie this program).
+*/
+extern char _end;
+#define KERNEL_ORIGIN \
+	((((unsigned long)&_end) + 511) & ~511)
+
+/* Round address to next higher page boundary. */
+#define NEXT_PAGE(a)	(((a) | (PAGE_SIZE - 1)) + 1)
+
+#ifdef INITRD_IMAGE_SIZE
+# define REAL_INITRD_SIZE INITRD_IMAGE_SIZE
+#else
+# define REAL_INITRD_SIZE 0
+#endif
+
+/* Defines from include/asm-alpha/system.h
+
+	BOOT_ADDR	Virtual address at which the consoles loads
+			the BOOTP image.
+
+	KERNEL_START    KSEG address at which the kernel is built to run,
+			which includes some initial data pages before the
+			code.
+
+	START_ADDR	KSEG address of the entry point of kernel code.
+
+	ZERO_PGE	KSEG address of page full of zeroes, but 
+			upon entry to kerne cvan be expected
+			to hold the parameter list and possible
+			INTRD information.
+
+   These are used in the local defines below.
+*/
+  
+
+/* Virtual addresses for the BOOTP image. Note that this includes the
+   bootstrapper code as well as the compressed kernel image, and
+   possibly the INITRD image.
+
+   Oh, and do NOT forget the STACK, which appears to be placed virtually
+   beyond the end of the loaded image.
+*/
+#define V_BOOT_IMAGE_START	BOOT_ADDR
+#define V_BOOT_IMAGE_END	SP_on_entry
+
+/* Virtual addresses for just the bootstrapper part of the BOOTP image. */
+#define V_BOOTSTRAPPER_START	BOOT_ADDR
+#define V_BOOTSTRAPPER_END	KERNEL_ORIGIN
+
+/* Virtual addresses for just the data part of the BOOTP
+   image. This may also include the INITRD image, but always
+   includes the STACK.
+*/
+#define V_DATA_START		KERNEL_ORIGIN
+#define V_INITRD_START		(KERNEL_ORIGIN + KERNEL_Z_SIZE)
+#define V_INTRD_END		(V_INITRD_START + REAL_INITRD_SIZE)
+#define V_DATA_END	 	V_BOOT_IMAGE_END
+
+/* KSEG addresses for the uncompressed kernel.
+
+   Note that the end address includes workspace for the decompression.
+   Note also that the DATA_START address is ZERO_PGE, to which we write
+   just before jumping to the kernel image at START_ADDR.
+ */
+#define K_KERNEL_DATA_START	ZERO_PGE
+#define K_KERNEL_IMAGE_START	START_ADDR
+#define K_KERNEL_IMAGE_END	(START_ADDR + KERNEL_SIZE)
+
+/* Define to where we may have to decompress the kernel image, before
+   we move it to the final position, in case of overlap. This will be
+   above the final position of the kernel.
+
+   Regardless of overlap, we move the INITRD image to the end of this
+   copy area, because there needs to be a buffer area after the kernel
+   for "bootmem" anyway.
+*/
+#define K_COPY_IMAGE_START	NEXT_PAGE(K_KERNEL_IMAGE_END)
+#define K_INITRD_START		NEXT_PAGE(K_COPY_IMAGE_START + KERNEL_SIZE)
+#define K_COPY_IMAGE_END \
+    (K_INITRD_START + REAL_INITRD_SIZE + MALLOC_AREA_SIZE)
+#define K_COPY_IMAGE_SIZE \
+    NEXT_PAGE(K_COPY_IMAGE_END - K_COPY_IMAGE_START)
+
+void
+start_kernel(void)
+{
+	int must_move = 0;
+
+	/* Initialize these for the decompression-in-place situation,
+	   which is the smallest amount of work and most likely to
+	   occur when using the normal START_ADDR of the kernel
+	   (currently set to 16MB, to clear all console code.
+	*/
+	unsigned long uncompressed_image_start = K_KERNEL_IMAGE_START;
+	unsigned long uncompressed_image_end = K_KERNEL_IMAGE_END;
+
+	unsigned long initrd_image_start = K_INITRD_START;
+
+	/*
+	 * Note that this crufty stuff with static and envval
+	 * and envbuf is because:
+	 *
+	 * 1. Frequently, the stack is short, and we don't want to overrun;
+	 * 2. Frequently the stack is where we are going to copy the kernel to;
+	 * 3. A certain SRM console required the GET_ENV output to stack.
+	 *    ??? A comment in the aboot sources indicates that the GET_ENV
+	 *    destination must be quadword aligned.  Might this explain the
+	 *    behaviour, rather than requiring output to the stack, which
+	 *    seems rather far-fetched.
+	 */
+	static long nbytes;
+	static char envval[256] __attribute__((aligned(8)));
+	register unsigned long asm_sp asm("30");
+
+	SP_on_entry = asm_sp;
+
+	srm_printk("Linux/Alpha BOOTPZ Loader for Linux " UTS_RELEASE "\n");
+
+	/* Validity check the HWRPB. */
+	if (INIT_HWRPB->pagesize != 8192) {
+		srm_printk("Expected 8kB pages, got %ldkB\n",
+		           INIT_HWRPB->pagesize >> 10);
+		return;
+	}
+	if (INIT_HWRPB->vptb != (unsigned long) VPTB) {
+		srm_printk("Expected vptb at %p, got %p\n",
+			   VPTB, (void *)INIT_HWRPB->vptb);
+		return;
+	}
+
+	/* PALcode (re)initialization. */
+	pal_init();
+
+	/* Get the parameter list from the console environment variable. */
+	nbytes = callback_getenv(ENV_BOOTED_OSFLAGS, envval, sizeof(envval));
+	if (nbytes < 0 || nbytes >= sizeof(envval)) {
+		nbytes = 0;
+	}
+	envval[nbytes] = '\0';
+
+#ifdef DEBUG_ADDRESSES
+	srm_printk("START_ADDR 0x%lx\n", START_ADDR);
+	srm_printk("KERNEL_ORIGIN 0x%lx\n", KERNEL_ORIGIN);
+	srm_printk("KERNEL_SIZE 0x%x\n", KERNEL_SIZE);
+	srm_printk("KERNEL_Z_SIZE 0x%x\n", KERNEL_Z_SIZE);
+#endif
+
+	/* Since all the SRM consoles load the BOOTP image at virtual
+	 * 0x20000000, we have to ensure that the physical memory
+	 * pages occupied by that image do NOT overlap the physical
+	 * address range where the kernel wants to be run.  This
+	 * causes real problems when attempting to cdecompress the
+	 * former into the latter... :-(
+	 *
+	 * So, we may have to decompress/move the kernel/INITRD image
+	 * virtual-to-physical someplace else first before moving
+	 * kernel /INITRD to their final resting places... ;-}
+	 *
+	 * Sigh...
+	 */
+
+	/* First, check to see if the range of addresses occupied by
+	   the bootstrapper part of the BOOTP image include any of the
+	   physical pages into which the kernel will be placed for
+	   execution.
+
+	   We only need check on the final kernel image range, since we
+	   will put the INITRD someplace that we can be sure is not
+	   in conflict.
+	 */
+	if (check_range(V_BOOTSTRAPPER_START, V_BOOTSTRAPPER_END,
+			K_KERNEL_DATA_START, K_KERNEL_IMAGE_END))
+	{
+		srm_printk("FATAL ERROR: overlap of bootstrapper code\n");
+		__halt();
+	}
+
+	/* Next, check to see if the range of addresses occupied by
+	   the compressed kernel/INITRD/stack portion of the BOOTP
+	   image include any of the physical pages into which the
+	   decompressed kernel or the INITRD will be placed for
+	   execution.
+	 */
+	if (check_range(V_DATA_START, V_DATA_END,
+			K_KERNEL_IMAGE_START, K_COPY_IMAGE_END))
+	{
+#ifdef DEBUG_ADDRESSES
+		srm_printk("OVERLAP: cannot decompress in place\n");
+#endif
+		uncompressed_image_start = K_COPY_IMAGE_START;
+		uncompressed_image_end = K_COPY_IMAGE_END;
+		must_move = 1;
+
+		/* Finally, check to see if the range of addresses
+		   occupied by the compressed kernel/INITRD part of
+		   the BOOTP image include any of the physical pages
+		   into which that part is to be copied for
+		   decompression.
+		*/
+		while (check_range(V_DATA_START, V_DATA_END,
+				   uncompressed_image_start,
+				   uncompressed_image_end))
+		{
+#if 0
+			uncompressed_image_start += K_COPY_IMAGE_SIZE;
+			uncompressed_image_end += K_COPY_IMAGE_SIZE;
+			initrd_image_start += K_COPY_IMAGE_SIZE;
+#else
+			/* Keep as close as possible to end of BOOTP image. */
+			uncompressed_image_start += PAGE_SIZE;
+			uncompressed_image_end += PAGE_SIZE;
+			initrd_image_start += PAGE_SIZE;
+#endif
+		}
+	}
+
+	srm_printk("Starting to load the kernel with args '%s'\n", envval);
+
+#ifdef DEBUG_ADDRESSES
+	srm_printk("Decompressing the kernel...\n"
+		   "...from 0x%lx to 0x%lx size 0x%x\n",
+		   V_DATA_START,
+		   uncompressed_image_start,
+		   KERNEL_SIZE);
+#endif
+        decompress_kernel((void *)uncompressed_image_start,
+			  (void *)V_DATA_START,
+			  KERNEL_SIZE, KERNEL_Z_SIZE);
+
+	/*
+	 * Now, move things to their final positions, if/as required.
+	 */
+
+#ifdef INITRD_IMAGE_SIZE
+
+	/* First, we always move the INITRD image, if present. */
+#ifdef DEBUG_ADDRESSES
+	srm_printk("Moving the INITRD image...\n"
+		   " from 0x%lx to 0x%lx size 0x%x\n",
+		   V_INITRD_START,
+		   initrd_image_start,
+		   INITRD_IMAGE_SIZE);
+#endif
+	memcpy((void *)initrd_image_start,
+	       (void *)V_INITRD_START,
+	       INITRD_IMAGE_SIZE);
+
+#endif /* INITRD_IMAGE_SIZE */
+
+	/* Next, we may have to move the uncompressed kernel to the
+	   final destination.
+	 */
+	if (must_move) {
+#ifdef DEBUG_ADDRESSES
+		srm_printk("Moving the uncompressed kernel...\n"
+			   "...from 0x%lx to 0x%lx size 0x%x\n",
+			   uncompressed_image_start,
+			   K_KERNEL_IMAGE_START,
+			   (unsigned)KERNEL_SIZE);
+#endif
+		memcpy((void *)K_KERNEL_IMAGE_START,
+		       (void *)uncompressed_image_start,
+		       KERNEL_SIZE);
+	}
+	
+	/* Clear the zero page, then move the argument list in. */
+	memset((char*)ZERO_PGE, 0, PAGE_SIZE);
+	strcpy((char*)ZERO_PGE, envval);
+
+#ifdef INITRD_IMAGE_SIZE
+	/* Finally, set the INITRD paramenters for the kernel. */
+	((long *)(ZERO_PGE+256))[0] = initrd_image_start;
+	((long *)(ZERO_PGE+256))[1] = INITRD_IMAGE_SIZE;
+
+#endif /* INITRD_IMAGE_SIZE */
+
+	runkernel();
+}
diff -urN linux-2.4.22-bk24/arch/alpha/boot/misc.c linux-2.4.22-bk25/arch/alpha/boot/misc.c
--- linux-2.4.22-bk24/arch/alpha/boot/misc.c	1969-12-31 16:00:00.000000000 -0800
+++ linux-2.4.22-bk25/arch/alpha/boot/misc.c	2003-09-26 02:49:43.000000000 -0700
@@ -0,0 +1,207 @@
+/*
+ * misc.c
+ * 
+ * This is a collection of several routines from gzip-1.0.3 
+ * adapted for Linux.
+ *
+ * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
+ *
+ * Modified for ARM Linux by Russell King
+ *
+ * Nicolas Pitre <nico@visuaide.com>  1999/04/14 :
+ *  For this code to run directly from Flash, all constant variables must
+ *  be marked with 'const' and all other variables initialized at run-time 
+ *  only.  This way all non constant variables will end up in the bss segment,
+ *  which should point to addresses in RAM and cleared to 0 on start.
+ *  This allows for a much quicker boot time.
+ *
+ * Modified for Alpha, from the ARM version, by Jay Estabrook 2003.
+ */
+
+#include <linux/kernel.h>
+
+#include <asm/uaccess.h>
+
+#define memzero(s,n)	memset ((s),0,(n))
+#define puts		srm_printk
+extern long srm_printk(const char *, ...)
+     __attribute__ ((format (printf, 1, 2)));;
+
+/*
+ * gzip delarations
+ */
+#define OF(args)  args
+#define STATIC static
+
+typedef unsigned char  uch;
+typedef unsigned short ush;
+typedef unsigned long  ulg;
+
+#define WSIZE 0x8000		/* Window size must be at least 32k, */
+				/* and a power of two */
+
+static uch *inbuf;		/* input buffer */
+static uch *window;		/* Sliding window buffer */
+
+static unsigned insize;		/* valid bytes in inbuf */
+static unsigned inptr;		/* index of next byte to be processed in inbuf */
+static unsigned outcnt;		/* bytes in output buffer */
+
+/* gzip flag byte */
+#define ASCII_FLAG   0x01 /* bit 0 set: file probably ascii text */
+#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
+#define EXTRA_FIELD  0x04 /* bit 2 set: extra field present */
+#define ORIG_NAME    0x08 /* bit 3 set: original file name present */
+#define COMMENT      0x10 /* bit 4 set: file comment present */
+#define ENCRYPTED    0x20 /* bit 5 set: file is encrypted */
+#define RESERVED     0xC0 /* bit 6,7:   reserved */
+
+#define get_byte()  (inptr < insize ? inbuf[inptr++] : fill_inbuf())
+
+/* Diagnostic functions */
+#ifdef DEBUG
+#  define Assert(cond,msg) {if(!(cond)) error(msg);}
+#  define Trace(x) fprintf x
+#  define Tracev(x) {if (verbose) fprintf x ;}
+#  define Tracevv(x) {if (verbose>1) fprintf x ;}
+#  define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
+#  define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
+#else
+#  define Assert(cond,msg)
+#  define Trace(x)
+#  define Tracev(x)
+#  define Tracevv(x)
+#  define Tracec(c,x)
+#  define Tracecv(c,x)
+#endif
+
+static int  fill_inbuf(void);
+static void flush_window(void);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+static char *input_data;
+static int  input_data_size;
+
+static uch *output_data;
+static ulg output_ptr;
+static ulg bytes_out;
+
+static void *malloc(int size);
+static void free(void *where);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+extern int end;
+static ulg free_mem_ptr;
+static ulg free_mem_ptr_end;
+
+#define HEAP_SIZE 0x2000
+
+#include "../../../lib/inflate.c"
+
+static void *malloc(int size)
+{
+	void *p;
+
+	if (size <0) error("Malloc error\n");
+	if (free_mem_ptr <= 0) error("Memory error\n");
+
+	free_mem_ptr = (free_mem_ptr + 3) & ~3;	/* Align */
+
+	p = (void *)free_mem_ptr;
+	free_mem_ptr += size;
+
+	if (free_mem_ptr >= free_mem_ptr_end)
+		error("Out of memory");
+	return p;
+}
+
+static void free(void *where)
+{ /* gzip_mark & gzip_release do the free */
+}
+
+static void gzip_mark(void **ptr)
+{
+	*ptr = (void *) free_mem_ptr;
+}
+
+static void gzip_release(void **ptr)
+{
+	free_mem_ptr = (long) *ptr;
+}
+
+/* ===========================================================================
+ * Fill the input buffer. This is called only when the buffer is empty
+ * and at least one byte is really needed.
+ */
+int fill_inbuf(void)
+{
+	if (insize != 0)
+		error("ran out of input data\n");
+
+	inbuf = input_data;
+	insize = input_data_size;
+
+	inptr = 1;
+	return inbuf[0];
+}
+
+/* ===========================================================================
+ * Write the output window window[0..outcnt-1] and update crc and bytes_out.
+ * (Used for the decompressed data only.)
+ */
+void flush_window(void)
+{
+	ulg c = crc;
+	unsigned n;
+	uch *in, *out, ch;
+
+	in = window;
+	out = &output_data[output_ptr];
+	for (n = 0; n < outcnt; n++) {
+		ch = *out++ = *in++;
+		c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
+	}
+	crc = c;
+	bytes_out += (ulg)outcnt;
+	output_ptr += (ulg)outcnt;
+	outcnt = 0;
+/*	puts("."); */
+}
+
+static void error(char *x)
+{
+	puts("\n\n");
+	puts(x);
+	puts("\n\n -- System halted");
+
+	while(1);	/* Halt */
+}
+
+unsigned int
+decompress_kernel(void *output_start,
+		  void *input_start,
+		  size_t ksize,
+		  size_t kzsize)
+{
+	output_data		= (uch *)output_start;
+	input_data		= (uch *)input_start;
+	input_data_size		= kzsize; /* use compressed size */
+
+	/* FIXME FIXME FIXME */
+	free_mem_ptr		= (ulg)output_start + ksize;
+	free_mem_ptr_end	= (ulg)output_start + ksize + 0x200000;
+	/* FIXME FIXME FIXME */
+
+	/* put in temp area to reduce initial footprint */
+	window = malloc(WSIZE);
+
+	makecrc();
+/*	puts("Uncompressing Linux..."); */
+	gunzip();
+/*	puts(" done, booting the kernel.\n"); */
+	return output_ptr;
+}
diff -urN linux-2.4.22-bk24/arch/alpha/boot/tools/objstrip.c linux-2.4.22-bk25/arch/alpha/boot/tools/objstrip.c
--- linux-2.4.22-bk24/arch/alpha/boot/tools/objstrip.c	2001-05-21 13:41:40.000000000 -0700
+++ linux-2.4.22-bk25/arch/alpha/boot/tools/objstrip.c	2003-09-26 02:49:43.000000000 -0700
@@ -27,7 +27,6 @@
 #include <linux/param.h>
 #include <linux/string.h>
 #ifdef __ELF__
-# include <asm/elf.h>
 # include <linux/elf.h>
 #endif
 
diff -urN linux-2.4.22-bk24/arch/alpha/config.in linux-2.4.22-bk25/arch/alpha/config.in
--- linux-2.4.22-bk24/arch/alpha/config.in	2003-09-26 02:49:35.000000000 -0700
+++ linux-2.4.22-bk25/arch/alpha/config.in	2003-09-26 02:49:43.000000000 -0700
@@ -440,7 +440,16 @@
 mainmenu_option next_comment
 comment 'Kernel hacking'
 
-bool 'Legacy kernel start address' CONFIG_ALPHA_LEGACY_START_ADDRESS
+if [ "$CONFIG_ALPHA_TITAN" = "y" -o "$CONFIG_ALPHA_WILDFIRE" = "y" -o \
+     "$CONFIG_ALPHA_MARVEL" = "y" ]; then
+   define_bool CONFIG_ALPHA_LEGACY_START_ADDRESS n
+else
+   if [ "$CONFIG_ALPHA_GENERIC" = "y" ]; then
+      bool 'Legacy kernel start address' CONFIG_ALPHA_LEGACY_START_ADDRESS
+   else
+      define_bool CONFIG_ALPHA_LEGACY_START_ADDRESS y
+   fi
+fi
 
 bool 'Kernel debugging' CONFIG_DEBUG_KERNEL
 if [ "$CONFIG_DEBUG_KERNEL" != "n" ]; then
diff -urN linux-2.4.22-bk24/arch/alpha/kernel/Makefile linux-2.4.22-bk25/arch/alpha/kernel/Makefile
--- linux-2.4.22-bk24/arch/alpha/kernel/Makefile	2003-08-25 04:44:39.000000000 -0700
+++ linux-2.4.22-bk25/arch/alpha/kernel/Makefile	2003-09-26 02:49:43.000000000 -0700
@@ -37,17 +37,21 @@
 ifdef CONFIG_ALPHA_GENERIC
 
 obj-y 	 += core_apecs.o core_cia.o core_irongate.o core_lca.o core_mcpcia.o \
-	    core_polaris.o core_t2.o core_tsunami.o core_titan.o \
-	    core_wildfire.o core_marvel.o \
+	    core_polaris.o core_t2.o core_tsunami.o \
 	    sys_alcor.o sys_cabriolet.o sys_dp264.o sys_eb64p.o sys_eiger.o \
-	    sys_jensen.o sys_miata.o sys_mikasa.o sys_nautilus.o sys_titan.o \
+	    sys_jensen.o sys_miata.o sys_mikasa.o sys_nautilus.o \
 	    sys_noritake.o sys_rawhide.o sys_ruffian.o sys_rx164.o \
 	    sys_sable.o sys_sio.o sys_sx164.o sys_takara.o sys_rx164.o \
-	    sys_wildfire.o sys_marvel.o \
-	    err_titan.o err_marvel.o \
 	    irq_pyxis.o srmcons.o gct.o \
 	    es1888.o smc37c669.o smc37c93x.o ns87312.o
 
+ifndef CONFIG_ALPHA_LEGACY_START_ADDRESS
+obj-y 	 += core_titan.o core_wildfire.o core_marvel.o \
+	    sys_titan.o sys_wildfire.o sys_marvel.o \
+	    err_titan.o err_marvel.o
+
+endif
+
 else
 
 # Misc support
diff -urN linux-2.4.22-bk24/arch/alpha/kernel/setup.c linux-2.4.22-bk25/arch/alpha/kernel/setup.c
--- linux-2.4.22-bk24/arch/alpha/kernel/setup.c	2003-08-25 04:44:39.000000000 -0700
+++ linux-2.4.22-bk25/arch/alpha/kernel/setup.c	2003-09-26 02:49:43.000000000 -0700
@@ -583,6 +583,35 @@
 	       var_name, alpha_mv.vector_name,
 	       (alpha_using_srm ? "SRM" : "MILO"));
 
+	printk("Major Options: "
+#ifdef CONFIG_SMP
+	       "SMP "
+#endif
+#ifdef CONFIG_ALPHA_EV56
+	       "EV56 "
+#endif
+#ifdef CONFIG_ALPHA_EV67
+	       "EV67 "
+#endif
+#ifdef CONFIG_ALPHA_LEGACY_START_ADDRESS
+	       "LEGACY_START "
+#endif
+
+#ifdef CONFIG_DISCONTIGMEM
+	       "DISCONTIGMEM "
+#ifdef CONFIG_NUMA
+	       "NUMA "
+#endif
+#endif
+
+#ifdef CONFIG_DEBUG_SPINLOCK
+	       "DEBUG_SPINLOCK "
+#endif
+#ifdef CONFIG_MAGIC_SYSRQ
+	       "MAGIC_SYSRQ "
+#endif
+	       "\n");
+
 	printk("Command line: %s\n", command_line);
 
 	/* 
diff -urN linux-2.4.22-bk24/arch/alpha/kernel/sys_nautilus.c linux-2.4.22-bk25/arch/alpha/kernel/sys_nautilus.c
--- linux-2.4.22-bk24/arch/alpha/kernel/sys_nautilus.c	2003-08-25 04:44:39.000000000 -0700
+++ linux-2.4.22-bk25/arch/alpha/kernel/sys_nautilus.c	2003-09-26 02:49:43.000000000 -0700
@@ -226,11 +226,13 @@
 	if (request_resource(&iomem_resource, bus->resource[1]) < 0)
 		printk(KERN_ERR "Failed to request MEM on hose 0\n");
 
-	if (pci_mem < memtop && pci_mem > alpha_mv.min_mem_address) {
+	if (pci_mem < memtop)
+		memtop = pci_mem;
+	if (memtop > alpha_mv.min_mem_address) {
 		free_reserved_mem(__va(alpha_mv.min_mem_address),
-				  __va(pci_mem));
+				  __va(memtop));
 		printk("nautilus_init_pci: %ldk freed\n",
-			(pci_mem - alpha_mv.min_mem_address) >> 10);
+			(memtop - alpha_mv.min_mem_address) >> 10);
 	}
 
 	if ((IRONGATE0->dev_vendor >> 16) > 0x7006)	/* Albacore? */
diff -urN linux-2.4.22-bk24/arch/alpha/mm/init.c linux-2.4.22-bk25/arch/alpha/mm/init.c
--- linux-2.4.22-bk24/arch/alpha/mm/init.c	2003-06-13 07:51:29.000000000 -0700
+++ linux-2.4.22-bk25/arch/alpha/mm/init.c	2003-09-26 02:49:43.000000000 -0700
@@ -234,7 +234,8 @@
 	/* Allocate one PGD and one PMD.  In the case of SRM, we'll need
 	   these to actually remap the console.  There is an assumption
 	   here that only one of each is needed, and this allows for 8MB.
-	   Currently (late 1999), big consoles are still under 4MB.
+	   On systems with larger consoles, additional pages will be
+	   allocated as needed during the mapping process.
 
 	   In the case of not SRM, but not CONFIG_ALPHA_LARGE_VMALLOC,
 	   we need to allocate the PGD we use for vmalloc before we start
@@ -261,6 +262,15 @@
 			unsigned long paddr = crb->map[i].pa;
 			crb->map[i].va = vaddr;
 			for (j = 0; j < crb->map[i].count; ++j) {
+				/* Newer console's (especially on larger
+				   systems) may require more pages of
+				   PTEs. Grab additional pages as needed. */
+				if (pmd != pmd_offset(pgd, vaddr)) {
+					memset(kernel_end, 0, PAGE_SIZE);
+					pmd = pmd_offset(pgd, vaddr);
+					pmd_set(pmd, (pte_t *)kernel_end);
+					kernel_end += PAGE_SIZE;
+				}
 				set_pte(pte_offset(pmd, vaddr),
 					mk_pte_phys(paddr, PAGE_KERNEL));
 				paddr += PAGE_SIZE;
diff -urN linux-2.4.22-bk24/arch/i386/kernel/mpparse.c linux-2.4.22-bk25/arch/i386/kernel/mpparse.c
--- linux-2.4.22-bk24/arch/i386/kernel/mpparse.c	2003-09-26 02:49:37.000000000 -0700
+++ linux-2.4.22-bk25/arch/i386/kernel/mpparse.c	2003-09-26 02:49:43.000000000 -0700
@@ -229,6 +229,11 @@
 		boot_cpu_logical_apicid = logical_apicid;
 	}
 
+	if (num_processors >= NR_CPUS){
+		printk(KERN_WARNING "NR_CPUS limit of %i reached. Cannot "
+			"boot CPU(apicid 0x%x).\n", NR_CPUS, m->mpc_apicid);
+		return;
+	}
 	num_processors++;
 
 	if (m->mpc_apicid > MAX_APICS) {
diff -urN linux-2.4.22-bk24/drivers/atm/he.c linux-2.4.22-bk25/drivers/atm/he.c
--- linux-2.4.22-bk24/drivers/atm/he.c	2003-09-26 02:49:37.000000000 -0700
+++ linux-2.4.22-bk25/drivers/atm/he.c	2003-09-26 02:49:43.000000000 -0700
@@ -2866,8 +2866,10 @@
 			if (!capable(CAP_NET_ADMIN))
 				return -EPERM;
 
-			copy_from_user(&reg, (struct he_ioctl_reg *) arg,
-						sizeof(struct he_ioctl_reg));
+			if (copy_from_user(&reg, (struct he_ioctl_reg *) arg,
+						sizeof(struct he_ioctl_reg)))
+				return -EFAULT;
+			
 			spin_lock_irqsave(&he_dev->global_lock, flags);
 			switch (reg.type) {
 				case HE_REGTYPE_PCI:
@@ -2891,8 +2893,9 @@
 			}
 			spin_unlock_irqrestore(&he_dev->global_lock, flags);
 			if (err == 0)
-				copy_to_user((struct he_ioctl_reg *) arg, &reg,
-							sizeof(struct he_ioctl_reg));
+				if (copy_to_user((struct he_ioctl_reg *) arg, &reg,
+							sizeof(struct he_ioctl_reg)))
+					return -EFAULT;
 			break;
 		default:
 #ifdef CONFIG_ATM_HE_USE_SUNI
diff -urN linux-2.4.22-bk24/drivers/cdrom/cdrom.c linux-2.4.22-bk25/drivers/cdrom/cdrom.c
--- linux-2.4.22-bk24/drivers/cdrom/cdrom.c	2002-11-28 15:53:12.000000000 -0800
+++ linux-2.4.22-bk25/drivers/cdrom/cdrom.c	2003-09-26 02:49:44.000000000 -0700
@@ -1882,20 +1882,26 @@
 	if (cgc->buflen < 0 || cgc->buflen >= 131072)
 		return -EINVAL;
 
-	if ((ubuf = cgc->buffer)) {
+	usense = cgc->sense;
+	cgc->sense = &sense;
+	if (usense && !access_ok(VERIFY_WRITE, usense, sizeof(*usense))) {
+		return -EFAULT;
+	}
+
+	ubuf = cgc->buffer;
+	if (cgc->data_direction == CGC_DATA_READ ||
+	    cgc->data_direction == CGC_DATA_WRITE) {
 		cgc->buffer = kmalloc(cgc->buflen, GFP_KERNEL);
 		if (cgc->buffer == NULL)
 			return -ENOMEM;
 	}
 
-	usense = cgc->sense;
-	cgc->sense = &sense;
-	if (usense && !access_ok(VERIFY_WRITE, usense, sizeof(*usense)))
-		return -EFAULT;
 
 	if (cgc->data_direction == CGC_DATA_READ) {
-		if (!access_ok(VERIFY_READ, ubuf, cgc->buflen))
+		if (!access_ok(VERIFY_READ, ubuf, cgc->buflen)) {
+			kfree(cgc->buffer);
 			return -EFAULT;
+		}
 	} else if (cgc->data_direction == CGC_DATA_WRITE) {
 		if (copy_from_user(cgc->buffer, ubuf, cgc->buflen)) {
 			kfree(cgc->buffer);
@@ -1907,7 +1913,10 @@
 	__copy_to_user(usense, cgc->sense, sizeof(*usense));
 	if (!ret && cgc->data_direction == CGC_DATA_READ)
 		__copy_to_user(ubuf, cgc->buffer, cgc->buflen);
-	kfree(cgc->buffer);
+	if (cgc->data_direction == CGC_DATA_READ ||
+	    cgc->data_direction == CGC_DATA_WRITE) {
+		kfree(cgc->buffer);
+	}
 	return ret;
 }
 
diff -urN linux-2.4.22-bk24/include/asm-alpha/irq.h linux-2.4.22-bk25/include/asm-alpha/irq.h
--- linux-2.4.22-bk24/include/asm-alpha/irq.h	2003-08-25 04:44:43.000000000 -0700
+++ linux-2.4.22-bk25/include/asm-alpha/irq.h	2003-09-26 02:49:45.000000000 -0700
@@ -16,7 +16,17 @@
    many places throughout the kernel to size static arrays.  That's ok,
    we'll use alpha_mv.nr_irqs when we want the real thing.  */
 
-# define NR_IRQS	(32768 + 16)	/* marvel - 32 pids */
+/* When LEGACY_START_ADDRESS is selected, we leave out:
+     TITAN
+     WILDFIRE
+     MARVEL
+*/
+
+# if defined(CONFIG_ALPHA_LEGACY_START_ADDRESS)
+#  define NR_IRQS	(128)		/* max is RAWHIDE/TAKARA */
+# else
+#  define NR_IRQS	(32768 + 16)	/* marvel - 32 pids */
+# endif
 
 #elif defined(CONFIG_ALPHA_CABRIOLET) || \
       defined(CONFIG_ALPHA_EB66P)     || \
diff -urN linux-2.4.22-bk24/include/asm-alpha/processor.h linux-2.4.22-bk25/include/asm-alpha/processor.h
--- linux-2.4.22-bk24/include/asm-alpha/processor.h	2003-06-13 07:51:38.000000000 -0700
+++ linux-2.4.22-bk25/include/asm-alpha/processor.h	2003-09-26 02:49:45.000000000 -0700
@@ -56,8 +56,8 @@
 	/*
 	 * The fields below are Linux-specific:
 	 *
-	 * bit 1..5: IEEE_TRAP_ENABLE bits (see fpu.h)
-	 * bit 6..8: UAC bits (see sysinfo.h)
+	 * bit 1..6: IEEE_TRAP_ENABLE bits (see fpu.h)
+	 * bit 7..9: UAC bits (see sysinfo.h)
 	 * bit 17..21: IEEE_STATUS_MASK bits (see fpu.h)
 	 * bit 63: die_if_kernel recursion lock
 	 */
diff -urN linux-2.4.22-bk24/include/asm-alpha/sysinfo.h linux-2.4.22-bk25/include/asm-alpha/sysinfo.h
--- linux-2.4.22-bk24/include/asm-alpha/sysinfo.h	1999-03-21 20:53:46.000000000 -0800
+++ linux-2.4.22-bk25/include/asm-alpha/sysinfo.h	2003-09-26 02:49:45.000000000 -0700
@@ -31,7 +31,7 @@
 
 /* This is the shift that is applied to the UAC bits as stored in the 
    per-thread flags.  */
-#define UAC_SHIFT			6
+#define UAC_SHIFT			7
 
 #endif
 
diff -urN linux-2.4.22-bk24/include/asm-alpha/xor.h linux-2.4.22-bk25/include/asm-alpha/xor.h
--- linux-2.4.22-bk24/include/asm-alpha/xor.h	2000-11-12 19:39:51.000000000 -0800
+++ linux-2.4.22-bk25/include/asm-alpha/xor.h	2003-09-26 02:49:45.000000000 -0700
@@ -32,809 +32,809 @@
 				 unsigned long *, unsigned long *,
 				 unsigned long *, unsigned long *);
 
-asm("
-	.text
-	.align 3
-	.ent xor_alpha_2
-xor_alpha_2:
-	.prologue 0
-	srl $16, 6, $16
-	.align 4
-2:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,8($17)
-	ldq $3,8($18)
-
-	ldq $4,16($17)
-	ldq $5,16($18)
-	ldq $6,24($17)
-	ldq $7,24($18)
-
-	ldq $19,32($17)
-	ldq $20,32($18)
-	ldq $21,40($17)
-	ldq $22,40($18)
-
-	ldq $23,48($17)
-	ldq $24,48($18)
-	ldq $25,56($17)
-	xor $0,$1,$0		# 7 cycles from $1 load
-
-	ldq $27,56($18)
-	xor $2,$3,$2
-	stq $0,0($17)
-	xor $4,$5,$4
-
-	stq $2,8($17)
-	xor $6,$7,$6
-	stq $4,16($17)
-	xor $19,$20,$19
-
-	stq $6,24($17)
-	xor $21,$22,$21
-	stq $19,32($17)
-	xor $23,$24,$23
-
-	stq $21,40($17)
-	xor $25,$27,$25
-	stq $23,48($17)
-	subq $16,1,$16
-
-	stq $25,56($17)
-	addq $17,64,$17
-	addq $18,64,$18
-	bgt $16,2b
-
-	ret
-	.end xor_alpha_2
-
-	.align 3
-	.ent xor_alpha_3
-xor_alpha_3:
-	.prologue 0
-	srl $16, 6, $16
-	.align 4
-3:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,8($17)
-
-	ldq $4,8($18)
-	ldq $6,16($17)
-	ldq $7,16($18)
-	ldq $21,24($17)
-
-	ldq $22,24($18)
-	ldq $24,32($17)
-	ldq $25,32($18)
-	ldq $5,8($19)
-
-	ldq $20,16($19)
-	ldq $23,24($19)
-	ldq $27,32($19)
-	nop
-
-	xor $0,$1,$1		# 8 cycles from $0 load
-	xor $3,$4,$4		# 6 cycles from $4 load
-	xor $6,$7,$7		# 6 cycles from $7 load
-	xor $21,$22,$22		# 5 cycles from $22 load
-
-	xor $1,$2,$2		# 9 cycles from $2 load
-	xor $24,$25,$25		# 5 cycles from $25 load
-	stq $2,0($17)
-	xor $4,$5,$5		# 6 cycles from $5 load
-
-	stq $5,8($17)
-	xor $7,$20,$20		# 7 cycles from $20 load
-	stq $20,16($17)
-	xor $22,$23,$23		# 7 cycles from $23 load
-
-	stq $23,24($17)
-	xor $25,$27,$27		# 7 cycles from $27 load
-	stq $27,32($17)
-	nop
-
-	ldq $0,40($17)
-	ldq $1,40($18)
-	ldq $3,48($17)
-	ldq $4,48($18)
-
-	ldq $6,56($17)
-	ldq $7,56($18)
-	ldq $2,40($19)
-	ldq $5,48($19)
-
-	ldq $20,56($19)
-	xor $0,$1,$1		# 4 cycles from $1 load
-	xor $3,$4,$4		# 5 cycles from $4 load
-	xor $6,$7,$7		# 5 cycles from $7 load
-
-	xor $1,$2,$2		# 4 cycles from $2 load
-	xor $4,$5,$5		# 5 cycles from $5 load
-	stq $2,40($17)
-	xor $7,$20,$20		# 4 cycles from $20 load
-
-	stq $5,48($17)
-	subq $16,1,$16
-	stq $20,56($17)
-	addq $19,64,$19
-
-	addq $18,64,$18
-	addq $17,64,$17
-	bgt $16,3b
-	ret
-	.end xor_alpha_3
-
-	.align 3
-	.ent xor_alpha_4
-xor_alpha_4:
-	.prologue 0
-	srl $16, 6, $16
-	.align 4
-4:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,0($20)
-
-	ldq $4,8($17)
-	ldq $5,8($18)
-	ldq $6,8($19)
-	ldq $7,8($20)
-
-	ldq $21,16($17)
-	ldq $22,16($18)
-	ldq $23,16($19)
-	ldq $24,16($20)
-
-	ldq $25,24($17)
-	xor $0,$1,$1		# 6 cycles from $1 load
-	ldq $27,24($18)
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	ldq $0,24($19)
-	xor $1,$3,$3
-	ldq $1,24($20)
-	xor $4,$5,$5		# 7 cycles from $5 load
-
-	stq $3,0($17)
-	xor $6,$7,$7
-	xor $21,$22,$22		# 7 cycles from $22 load
-	xor $5,$7,$7
-
-	stq $7,8($17)
-	xor $23,$24,$24		# 7 cycles from $24 load
-	ldq $2,32($17)
-	xor $22,$24,$24
-
-	ldq $3,32($18)
-	ldq $4,32($19)
-	ldq $5,32($20)
-	xor $25,$27,$27		# 8 cycles from $27 load
-
-	ldq $6,40($17)
-	ldq $7,40($18)
-	ldq $21,40($19)
-	ldq $22,40($20)
-
-	stq $24,16($17)
-	xor $0,$1,$1		# 9 cycles from $1 load
-	xor $2,$3,$3		# 5 cycles from $3 load
-	xor $27,$1,$1
-
-	stq $1,24($17)
-	xor $4,$5,$5		# 5 cycles from $5 load
-	ldq $23,48($17)
-	ldq $24,48($18)
-
-	ldq $25,48($19)
-	xor $3,$5,$5
-	ldq $27,48($20)
-	ldq $0,56($17)
-
-	ldq $1,56($18)
-	ldq $2,56($19)
-	xor $6,$7,$7		# 8 cycles from $6 load
-	ldq $3,56($20)
-
-	stq $5,32($17)
-	xor $21,$22,$22		# 8 cycles from $22 load
-	xor $7,$22,$22
-	xor $23,$24,$24		# 5 cycles from $24 load
-
-	stq $22,40($17)
-	xor $25,$27,$27		# 5 cycles from $27 load
-	xor $24,$27,$27
-	xor $0,$1,$1		# 5 cycles from $1 load
-
-	stq $27,48($17)
-	xor $2,$3,$3		# 4 cycles from $3 load
-	xor $1,$3,$3
-	subq $16,1,$16
-
-	stq $3,56($17)
-	addq $20,64,$20
-	addq $19,64,$19
-	addq $18,64,$18
-
-	addq $17,64,$17
-	bgt $16,4b
-	ret
-	.end xor_alpha_4
-
-	.align 3
-	.ent xor_alpha_5
-xor_alpha_5:
-	.prologue 0
-	srl $16, 6, $16
-	.align 4
-5:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,0($20)
-
-	ldq $4,0($21)
-	ldq $5,8($17)
-	ldq $6,8($18)
-	ldq $7,8($19)
-
-	ldq $22,8($20)
-	ldq $23,8($21)
-	ldq $24,16($17)
-	ldq $25,16($18)
-
-	ldq $27,16($19)
-	xor $0,$1,$1		# 6 cycles from $1 load
-	ldq $28,16($20)
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	ldq $0,16($21)
-	xor $1,$3,$3
-	ldq $1,24($17)
-	xor $3,$4,$4		# 7 cycles from $4 load
-
-	stq $4,0($17)
-	xor $5,$6,$6		# 7 cycles from $6 load
-	xor $7,$22,$22		# 7 cycles from $22 load
-	xor $6,$23,$23		# 7 cycles from $23 load
-
-	ldq $2,24($18)
-	xor $22,$23,$23
-	ldq $3,24($19)
-	xor $24,$25,$25		# 8 cycles from $25 load
-
-	stq $23,8($17)
-	xor $25,$27,$27		# 8 cycles from $27 load
-	ldq $4,24($20)
-	xor $28,$0,$0		# 7 cycles from $0 load
-
-	ldq $5,24($21)
-	xor $27,$0,$0
-	ldq $6,32($17)
-	ldq $7,32($18)
-
-	stq $0,16($17)
-	xor $1,$2,$2		# 6 cycles from $2 load
-	ldq $22,32($19)
-	xor $3,$4,$4		# 4 cycles from $4 load
-	
-	ldq $23,32($20)
-	xor $2,$4,$4
-	ldq $24,32($21)
-	ldq $25,40($17)
-
-	ldq $27,40($18)
-	ldq $28,40($19)
-	ldq $0,40($20)
-	xor $4,$5,$5		# 7 cycles from $5 load
-
-	stq $5,24($17)
-	xor $6,$7,$7		# 7 cycles from $7 load
-	ldq $1,40($21)
-	ldq $2,48($17)
-
-	ldq $3,48($18)
-	xor $7,$22,$22		# 7 cycles from $22 load
-	ldq $4,48($19)
-	xor $23,$24,$24		# 6 cycles from $24 load
-
-	ldq $5,48($20)
-	xor $22,$24,$24
-	ldq $6,48($21)
-	xor $25,$27,$27		# 7 cycles from $27 load
-
-	stq $24,32($17)
-	xor $27,$28,$28		# 8 cycles from $28 load
-	ldq $7,56($17)
-	xor $0,$1,$1		# 6 cycles from $1 load
-
-	ldq $22,56($18)
-	ldq $23,56($19)
-	ldq $24,56($20)
-	ldq $25,56($21)
-
-	xor $28,$1,$1
-	xor $2,$3,$3		# 9 cycles from $3 load
-	xor $3,$4,$4		# 9 cycles from $4 load
-	xor $5,$6,$6		# 8 cycles from $6 load
-
-	stq $1,40($17)
-	xor $4,$6,$6
-	xor $7,$22,$22		# 7 cycles from $22 load
-	xor $23,$24,$24		# 6 cycles from $24 load
-
-	stq $6,48($17)
-	xor $22,$24,$24
-	subq $16,1,$16
-	xor $24,$25,$25		# 8 cycles from $25 load
-
-	stq $25,56($17)
-	addq $21,64,$21
-	addq $20,64,$20
-	addq $19,64,$19
-
-	addq $18,64,$18
-	addq $17,64,$17
-	bgt $16,5b
-	ret
-	.end xor_alpha_5
-
-	.align 3
-	.ent xor_alpha_prefetch_2
-xor_alpha_prefetch_2:
-	.prologue 0
-	srl $16, 6, $16
-
-	ldq $31, 0($17)
-	ldq $31, 0($18)
-
-	ldq $31, 64($17)
-	ldq $31, 64($18)
-
-	ldq $31, 128($17)
-	ldq $31, 128($18)
-
-	ldq $31, 192($17)
-	ldq $31, 192($18)
-	.align 4
-2:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,8($17)
-	ldq $3,8($18)
-
-	ldq $4,16($17)
-	ldq $5,16($18)
-	ldq $6,24($17)
-	ldq $7,24($18)
-
-	ldq $19,32($17)
-	ldq $20,32($18)
-	ldq $21,40($17)
-	ldq $22,40($18)
-
-	ldq $23,48($17)
-	ldq $24,48($18)
-	ldq $25,56($17)
-	ldq $27,56($18)
-
-	ldq $31,256($17)
-	xor $0,$1,$0		# 8 cycles from $1 load
-	ldq $31,256($18)
-	xor $2,$3,$2
-
-	stq $0,0($17)
-	xor $4,$5,$4
-	stq $2,8($17)
-	xor $6,$7,$6
-
-	stq $4,16($17)
-	xor $19,$20,$19
-	stq $6,24($17)
-	xor $21,$22,$21
-
-	stq $19,32($17)
-	xor $23,$24,$23
-	stq $21,40($17)
-	xor $25,$27,$25
-
-	stq $23,48($17)
-	subq $16,1,$16
-	stq $25,56($17)
-	addq $17,64,$17
-
-	addq $18,64,$18
-	bgt $16,2b
-	ret
-	.end xor_alpha_prefetch_2
-
-	.align 3
-	.ent xor_alpha_prefetch_3
-xor_alpha_prefetch_3:
-	.prologue 0
-	srl $16, 6, $16
-
-	ldq $31, 0($17)
-	ldq $31, 0($18)
-	ldq $31, 0($19)
-
-	ldq $31, 64($17)
-	ldq $31, 64($18)
-	ldq $31, 64($19)
-
-	ldq $31, 128($17)
-	ldq $31, 128($18)
-	ldq $31, 128($19)
-
-	ldq $31, 192($17)
-	ldq $31, 192($18)
-	ldq $31, 192($19)
-	.align 4
-3:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,8($17)
-
-	ldq $4,8($18)
-	ldq $6,16($17)
-	ldq $7,16($18)
-	ldq $21,24($17)
-
-	ldq $22,24($18)
-	ldq $24,32($17)
-	ldq $25,32($18)
-	ldq $5,8($19)
-
-	ldq $20,16($19)
-	ldq $23,24($19)
-	ldq $27,32($19)
-	nop
-
-	xor $0,$1,$1		# 8 cycles from $0 load
-	xor $3,$4,$4		# 7 cycles from $4 load
-	xor $6,$7,$7		# 6 cycles from $7 load
-	xor $21,$22,$22		# 5 cycles from $22 load
-
-	xor $1,$2,$2		# 9 cycles from $2 load
-	xor $24,$25,$25		# 5 cycles from $25 load
-	stq $2,0($17)
-	xor $4,$5,$5		# 6 cycles from $5 load
-
-	stq $5,8($17)
-	xor $7,$20,$20		# 7 cycles from $20 load
-	stq $20,16($17)
-	xor $22,$23,$23		# 7 cycles from $23 load
-
-	stq $23,24($17)
-	xor $25,$27,$27		# 7 cycles from $27 load
-	stq $27,32($17)
-	nop
-
-	ldq $0,40($17)
-	ldq $1,40($18)
-	ldq $3,48($17)
-	ldq $4,48($18)
-
-	ldq $6,56($17)
-	ldq $7,56($18)
-	ldq $2,40($19)
-	ldq $5,48($19)
-
-	ldq $20,56($19)
-	ldq $31,256($17)
-	ldq $31,256($18)
-	ldq $31,256($19)
-
-	xor $0,$1,$1		# 6 cycles from $1 load
-	xor $3,$4,$4		# 5 cycles from $4 load
-	xor $6,$7,$7		# 5 cycles from $7 load
-	xor $1,$2,$2		# 4 cycles from $2 load
-	
-	xor $4,$5,$5		# 5 cycles from $5 load
-	xor $7,$20,$20		# 4 cycles from $20 load
-	stq $2,40($17)
-	subq $16,1,$16
-
-	stq $5,48($17)
-	addq $19,64,$19
-	stq $20,56($17)
-	addq $18,64,$18
-
-	addq $17,64,$17
-	bgt $16,3b
-	ret
-	.end xor_alpha_prefetch_3
-
-	.align 3
-	.ent xor_alpha_prefetch_4
-xor_alpha_prefetch_4:
-	.prologue 0
-	srl $16, 6, $16
-
-	ldq $31, 0($17)
-	ldq $31, 0($18)
-	ldq $31, 0($19)
-	ldq $31, 0($20)
-
-	ldq $31, 64($17)
-	ldq $31, 64($18)
-	ldq $31, 64($19)
-	ldq $31, 64($20)
-
-	ldq $31, 128($17)
-	ldq $31, 128($18)
-	ldq $31, 128($19)
-	ldq $31, 128($20)
-
-	ldq $31, 192($17)
-	ldq $31, 192($18)
-	ldq $31, 192($19)
-	ldq $31, 192($20)
-	.align 4
-4:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,0($20)
-
-	ldq $4,8($17)
-	ldq $5,8($18)
-	ldq $6,8($19)
-	ldq $7,8($20)
-
-	ldq $21,16($17)
-	ldq $22,16($18)
-	ldq $23,16($19)
-	ldq $24,16($20)
-
-	ldq $25,24($17)
-	xor $0,$1,$1		# 6 cycles from $1 load
-	ldq $27,24($18)
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	ldq $0,24($19)
-	xor $1,$3,$3
-	ldq $1,24($20)
-	xor $4,$5,$5		# 7 cycles from $5 load
-
-	stq $3,0($17)
-	xor $6,$7,$7
-	xor $21,$22,$22		# 7 cycles from $22 load
-	xor $5,$7,$7
-
-	stq $7,8($17)
-	xor $23,$24,$24		# 7 cycles from $24 load
-	ldq $2,32($17)
-	xor $22,$24,$24
-
-	ldq $3,32($18)
-	ldq $4,32($19)
-	ldq $5,32($20)
-	xor $25,$27,$27		# 8 cycles from $27 load
-
-	ldq $6,40($17)
-	ldq $7,40($18)
-	ldq $21,40($19)
-	ldq $22,40($20)
-
-	stq $24,16($17)
-	xor $0,$1,$1		# 9 cycles from $1 load
-	xor $2,$3,$3		# 5 cycles from $3 load
-	xor $27,$1,$1
-
-	stq $1,24($17)
-	xor $4,$5,$5		# 5 cycles from $5 load
-	ldq $23,48($17)
-	xor $3,$5,$5
-
-	ldq $24,48($18)
-	ldq $25,48($19)
-	ldq $27,48($20)
-	ldq $0,56($17)
-
-	ldq $1,56($18)
-	ldq $2,56($19)
-	ldq $3,56($20)
-	xor $6,$7,$7		# 8 cycles from $6 load
-
-	ldq $31,256($17)
-	xor $21,$22,$22		# 8 cycles from $22 load
-	ldq $31,256($18)
-	xor $7,$22,$22
-
-	ldq $31,256($19)
-	xor $23,$24,$24		# 6 cycles from $24 load
-	ldq $31,256($20)
-	xor $25,$27,$27		# 6 cycles from $27 load
-
-	stq $5,32($17)
-	xor $24,$27,$27
-	xor $0,$1,$1		# 7 cycles from $1 load
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	stq $22,40($17)
-	xor $1,$3,$3
-	stq $27,48($17)
-	subq $16,1,$16
-
-	stq $3,56($17)
-	addq $20,64,$20
-	addq $19,64,$19
-	addq $18,64,$18
-
-	addq $17,64,$17
-	bgt $16,4b
-	ret
-	.end xor_alpha_prefetch_4
-
-	.align 3
-	.ent xor_alpha_prefetch_5
-xor_alpha_prefetch_5:
-	.prologue 0
-	srl $16, 6, $16
-
-	ldq $31, 0($17)
-	ldq $31, 0($18)
-	ldq $31, 0($19)
-	ldq $31, 0($20)
-	ldq $31, 0($21)
-
-	ldq $31, 64($17)
-	ldq $31, 64($18)
-	ldq $31, 64($19)
-	ldq $31, 64($20)
-	ldq $31, 64($21)
-
-	ldq $31, 128($17)
-	ldq $31, 128($18)
-	ldq $31, 128($19)
-	ldq $31, 128($20)
-	ldq $31, 128($21)
-
-	ldq $31, 192($17)
-	ldq $31, 192($18)
-	ldq $31, 192($19)
-	ldq $31, 192($20)
-	ldq $31, 192($21)
-	.align 4
-5:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,0($20)
-
-	ldq $4,0($21)
-	ldq $5,8($17)
-	ldq $6,8($18)
-	ldq $7,8($19)
-
-	ldq $22,8($20)
-	ldq $23,8($21)
-	ldq $24,16($17)
-	ldq $25,16($18)
-
-	ldq $27,16($19)
-	xor $0,$1,$1		# 6 cycles from $1 load
-	ldq $28,16($20)
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	ldq $0,16($21)
-	xor $1,$3,$3
-	ldq $1,24($17)
-	xor $3,$4,$4		# 7 cycles from $4 load
-
-	stq $4,0($17)
-	xor $5,$6,$6		# 7 cycles from $6 load
-	xor $7,$22,$22		# 7 cycles from $22 load
-	xor $6,$23,$23		# 7 cycles from $23 load
-
-	ldq $2,24($18)
-	xor $22,$23,$23
-	ldq $3,24($19)
-	xor $24,$25,$25		# 8 cycles from $25 load
-
-	stq $23,8($17)
-	xor $25,$27,$27		# 8 cycles from $27 load
-	ldq $4,24($20)
-	xor $28,$0,$0		# 7 cycles from $0 load
-
-	ldq $5,24($21)
-	xor $27,$0,$0
-	ldq $6,32($17)
-	ldq $7,32($18)
-
-	stq $0,16($17)
-	xor $1,$2,$2		# 6 cycles from $2 load
-	ldq $22,32($19)
-	xor $3,$4,$4		# 4 cycles from $4 load
-	
-	ldq $23,32($20)
-	xor $2,$4,$4
-	ldq $24,32($21)
-	ldq $25,40($17)
-
-	ldq $27,40($18)
-	ldq $28,40($19)
-	ldq $0,40($20)
-	xor $4,$5,$5		# 7 cycles from $5 load
-
-	stq $5,24($17)
-	xor $6,$7,$7		# 7 cycles from $7 load
-	ldq $1,40($21)
-	ldq $2,48($17)
-
-	ldq $3,48($18)
-	xor $7,$22,$22		# 7 cycles from $22 load
-	ldq $4,48($19)
-	xor $23,$24,$24		# 6 cycles from $24 load
-
-	ldq $5,48($20)
-	xor $22,$24,$24
-	ldq $6,48($21)
-	xor $25,$27,$27		# 7 cycles from $27 load
-
-	stq $24,32($17)
-	xor $27,$28,$28		# 8 cycles from $28 load
-	ldq $7,56($17)
-	xor $0,$1,$1		# 6 cycles from $1 load
-
-	ldq $22,56($18)
-	ldq $23,56($19)
-	ldq $24,56($20)
-	ldq $25,56($21)
-
-	ldq $31,256($17)
-	xor $28,$1,$1
-	ldq $31,256($18)
-	xor $2,$3,$3		# 9 cycles from $3 load
-
-	ldq $31,256($19)
-	xor $3,$4,$4		# 9 cycles from $4 load
-	ldq $31,256($20)
-	xor $5,$6,$6		# 8 cycles from $6 load
-
-	stq $1,40($17)
-	xor $4,$6,$6
-	xor $7,$22,$22		# 7 cycles from $22 load
-	xor $23,$24,$24		# 6 cycles from $24 load
-
-	stq $6,48($17)
-	xor $22,$24,$24
-	ldq $31,256($21)
-	xor $24,$25,$25		# 8 cycles from $25 load
-
-	stq $25,56($17)
-	subq $16,1,$16
-	addq $21,64,$21
-	addq $20,64,$20
-
-	addq $19,64,$19
-	addq $18,64,$18
-	addq $17,64,$17
-	bgt $16,5b
-
-	ret
-	.end xor_alpha_prefetch_5
+asm("								\n\
+	.text							\n\
+	.align 3						\n\
+	.ent xor_alpha_2					\n\
+xor_alpha_2:							\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+	.align 4						\n\
+2:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,8($17)						\n\
+	ldq $3,8($18)						\n\
+								\n\
+	ldq $4,16($17)						\n\
+	ldq $5,16($18)						\n\
+	ldq $6,24($17)						\n\
+	ldq $7,24($18)						\n\
+								\n\
+	ldq $19,32($17)						\n\
+	ldq $20,32($18)						\n\
+	ldq $21,40($17)						\n\
+	ldq $22,40($18)						\n\
+								\n\
+	ldq $23,48($17)						\n\
+	ldq $24,48($18)						\n\
+	ldq $25,56($17)						\n\
+	xor $0,$1,$0		# 7 cycles from $1 load		\n\
+								\n\
+	ldq $27,56($18)						\n\
+	xor $2,$3,$2						\n\
+	stq $0,0($17)						\n\
+	xor $4,$5,$4						\n\
+								\n\
+	stq $2,8($17)						\n\
+	xor $6,$7,$6						\n\
+	stq $4,16($17)						\n\
+	xor $19,$20,$19						\n\
+								\n\
+	stq $6,24($17)						\n\
+	xor $21,$22,$21						\n\
+	stq $19,32($17)						\n\
+	xor $23,$24,$23						\n\
+								\n\
+	stq $21,40($17)						\n\
+	xor $25,$27,$25						\n\
+	stq $23,48($17)						\n\
+	subq $16,1,$16						\n\
+								\n\
+	stq $25,56($17)						\n\
+	addq $17,64,$17						\n\
+	addq $18,64,$18						\n\
+	bgt $16,2b						\n\
+								\n\
+	ret							\n\
+	.end xor_alpha_2					\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_3					\n\
+xor_alpha_3:							\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+	.align 4						\n\
+3:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,8($17)						\n\
+								\n\
+	ldq $4,8($18)						\n\
+	ldq $6,16($17)						\n\
+	ldq $7,16($18)						\n\
+	ldq $21,24($17)						\n\
+								\n\
+	ldq $22,24($18)						\n\
+	ldq $24,32($17)						\n\
+	ldq $25,32($18)						\n\
+	ldq $5,8($19)						\n\
+								\n\
+	ldq $20,16($19)						\n\
+	ldq $23,24($19)						\n\
+	ldq $27,32($19)						\n\
+	nop							\n\
+								\n\
+	xor $0,$1,$1		# 8 cycles from $0 load		\n\
+	xor $3,$4,$4		# 6 cycles from $4 load		\n\
+	xor $6,$7,$7		# 6 cycles from $7 load		\n\
+	xor $21,$22,$22		# 5 cycles from $22 load	\n\
+								\n\
+	xor $1,$2,$2		# 9 cycles from $2 load		\n\
+	xor $24,$25,$25		# 5 cycles from $25 load	\n\
+	stq $2,0($17)						\n\
+	xor $4,$5,$5		# 6 cycles from $5 load		\n\
+								\n\
+	stq $5,8($17)						\n\
+	xor $7,$20,$20		# 7 cycles from $20 load	\n\
+	stq $20,16($17)						\n\
+	xor $22,$23,$23		# 7 cycles from $23 load	\n\
+								\n\
+	stq $23,24($17)						\n\
+	xor $25,$27,$27		# 7 cycles from $27 load	\n\
+	stq $27,32($17)						\n\
+	nop							\n\
+								\n\
+	ldq $0,40($17)						\n\
+	ldq $1,40($18)						\n\
+	ldq $3,48($17)						\n\
+	ldq $4,48($18)						\n\
+								\n\
+	ldq $6,56($17)						\n\
+	ldq $7,56($18)						\n\
+	ldq $2,40($19)						\n\
+	ldq $5,48($19)						\n\
+								\n\
+	ldq $20,56($19)						\n\
+	xor $0,$1,$1		# 4 cycles from $1 load		\n\
+	xor $3,$4,$4		# 5 cycles from $4 load		\n\
+	xor $6,$7,$7		# 5 cycles from $7 load		\n\
+								\n\
+	xor $1,$2,$2		# 4 cycles from $2 load		\n\
+	xor $4,$5,$5		# 5 cycles from $5 load		\n\
+	stq $2,40($17)						\n\
+	xor $7,$20,$20		# 4 cycles from $20 load	\n\
+								\n\
+	stq $5,48($17)						\n\
+	subq $16,1,$16						\n\
+	stq $20,56($17)						\n\
+	addq $19,64,$19						\n\
+								\n\
+	addq $18,64,$18						\n\
+	addq $17,64,$17						\n\
+	bgt $16,3b						\n\
+	ret							\n\
+	.end xor_alpha_3					\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_4					\n\
+xor_alpha_4:							\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+	.align 4						\n\
+4:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,0($20)						\n\
+								\n\
+	ldq $4,8($17)						\n\
+	ldq $5,8($18)						\n\
+	ldq $6,8($19)						\n\
+	ldq $7,8($20)						\n\
+								\n\
+	ldq $21,16($17)						\n\
+	ldq $22,16($18)						\n\
+	ldq $23,16($19)						\n\
+	ldq $24,16($20)						\n\
+								\n\
+	ldq $25,24($17)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	ldq $27,24($18)						\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	ldq $0,24($19)						\n\
+	xor $1,$3,$3						\n\
+	ldq $1,24($20)						\n\
+	xor $4,$5,$5		# 7 cycles from $5 load		\n\
+								\n\
+	stq $3,0($17)						\n\
+	xor $6,$7,$7						\n\
+	xor $21,$22,$22		# 7 cycles from $22 load	\n\
+	xor $5,$7,$7						\n\
+								\n\
+	stq $7,8($17)						\n\
+	xor $23,$24,$24		# 7 cycles from $24 load	\n\
+	ldq $2,32($17)						\n\
+	xor $22,$24,$24						\n\
+								\n\
+	ldq $3,32($18)						\n\
+	ldq $4,32($19)						\n\
+	ldq $5,32($20)						\n\
+	xor $25,$27,$27		# 8 cycles from $27 load	\n\
+								\n\
+	ldq $6,40($17)						\n\
+	ldq $7,40($18)						\n\
+	ldq $21,40($19)						\n\
+	ldq $22,40($20)						\n\
+								\n\
+	stq $24,16($17)						\n\
+	xor $0,$1,$1		# 9 cycles from $1 load		\n\
+	xor $2,$3,$3		# 5 cycles from $3 load		\n\
+	xor $27,$1,$1						\n\
+								\n\
+	stq $1,24($17)						\n\
+	xor $4,$5,$5		# 5 cycles from $5 load		\n\
+	ldq $23,48($17)						\n\
+	ldq $24,48($18)						\n\
+								\n\
+	ldq $25,48($19)						\n\
+	xor $3,$5,$5						\n\
+	ldq $27,48($20)						\n\
+	ldq $0,56($17)						\n\
+								\n\
+	ldq $1,56($18)						\n\
+	ldq $2,56($19)						\n\
+	xor $6,$7,$7		# 8 cycles from $6 load		\n\
+	ldq $3,56($20)						\n\
+								\n\
+	stq $5,32($17)						\n\
+	xor $21,$22,$22		# 8 cycles from $22 load	\n\
+	xor $7,$22,$22						\n\
+	xor $23,$24,$24		# 5 cycles from $24 load	\n\
+								\n\
+	stq $22,40($17)						\n\
+	xor $25,$27,$27		# 5 cycles from $27 load	\n\
+	xor $24,$27,$27						\n\
+	xor $0,$1,$1		# 5 cycles from $1 load		\n\
+								\n\
+	stq $27,48($17)						\n\
+	xor $2,$3,$3		# 4 cycles from $3 load		\n\
+	xor $1,$3,$3						\n\
+	subq $16,1,$16						\n\
+								\n\
+	stq $3,56($17)						\n\
+	addq $20,64,$20						\n\
+	addq $19,64,$19						\n\
+	addq $18,64,$18						\n\
+								\n\
+	addq $17,64,$17						\n\
+	bgt $16,4b						\n\
+	ret							\n\
+	.end xor_alpha_4					\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_5					\n\
+xor_alpha_5:							\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+	.align 4						\n\
+5:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,0($20)						\n\
+								\n\
+	ldq $4,0($21)						\n\
+	ldq $5,8($17)						\n\
+	ldq $6,8($18)						\n\
+	ldq $7,8($19)						\n\
+								\n\
+	ldq $22,8($20)						\n\
+	ldq $23,8($21)						\n\
+	ldq $24,16($17)						\n\
+	ldq $25,16($18)						\n\
+								\n\
+	ldq $27,16($19)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	ldq $28,16($20)						\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	ldq $0,16($21)						\n\
+	xor $1,$3,$3						\n\
+	ldq $1,24($17)						\n\
+	xor $3,$4,$4		# 7 cycles from $4 load		\n\
+								\n\
+	stq $4,0($17)						\n\
+	xor $5,$6,$6		# 7 cycles from $6 load		\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	xor $6,$23,$23		# 7 cycles from $23 load	\n\
+								\n\
+	ldq $2,24($18)						\n\
+	xor $22,$23,$23						\n\
+	ldq $3,24($19)						\n\
+	xor $24,$25,$25		# 8 cycles from $25 load	\n\
+								\n\
+	stq $23,8($17)						\n\
+	xor $25,$27,$27		# 8 cycles from $27 load	\n\
+	ldq $4,24($20)						\n\
+	xor $28,$0,$0		# 7 cycles from $0 load		\n\
+								\n\
+	ldq $5,24($21)						\n\
+	xor $27,$0,$0						\n\
+	ldq $6,32($17)						\n\
+	ldq $7,32($18)						\n\
+								\n\
+	stq $0,16($17)						\n\
+	xor $1,$2,$2		# 6 cycles from $2 load		\n\
+	ldq $22,32($19)						\n\
+	xor $3,$4,$4		# 4 cycles from $4 load		\n\
+								\n\
+	ldq $23,32($20)						\n\
+	xor $2,$4,$4						\n\
+	ldq $24,32($21)						\n\
+	ldq $25,40($17)						\n\
+								\n\
+	ldq $27,40($18)						\n\
+	ldq $28,40($19)						\n\
+	ldq $0,40($20)						\n\
+	xor $4,$5,$5		# 7 cycles from $5 load		\n\
+								\n\
+	stq $5,24($17)						\n\
+	xor $6,$7,$7		# 7 cycles from $7 load		\n\
+	ldq $1,40($21)						\n\
+	ldq $2,48($17)						\n\
+								\n\
+	ldq $3,48($18)						\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	ldq $4,48($19)						\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+								\n\
+	ldq $5,48($20)						\n\
+	xor $22,$24,$24						\n\
+	ldq $6,48($21)						\n\
+	xor $25,$27,$27		# 7 cycles from $27 load	\n\
+								\n\
+	stq $24,32($17)						\n\
+	xor $27,$28,$28		# 8 cycles from $28 load	\n\
+	ldq $7,56($17)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+								\n\
+	ldq $22,56($18)						\n\
+	ldq $23,56($19)						\n\
+	ldq $24,56($20)						\n\
+	ldq $25,56($21)						\n\
+								\n\
+	xor $28,$1,$1						\n\
+	xor $2,$3,$3		# 9 cycles from $3 load		\n\
+	xor $3,$4,$4		# 9 cycles from $4 load		\n\
+	xor $5,$6,$6		# 8 cycles from $6 load		\n\
+								\n\
+	stq $1,40($17)						\n\
+	xor $4,$6,$6						\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+								\n\
+	stq $6,48($17)						\n\
+	xor $22,$24,$24						\n\
+	subq $16,1,$16						\n\
+	xor $24,$25,$25		# 8 cycles from $25 load	\n\
+								\n\
+	stq $25,56($17)						\n\
+	addq $21,64,$21						\n\
+	addq $20,64,$20						\n\
+	addq $19,64,$19						\n\
+								\n\
+	addq $18,64,$18						\n\
+	addq $17,64,$17						\n\
+	bgt $16,5b						\n\
+	ret							\n\
+	.end xor_alpha_5					\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_prefetch_2				\n\
+xor_alpha_prefetch_2:						\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+								\n\
+	ldq $31, 0($17)						\n\
+	ldq $31, 0($18)						\n\
+								\n\
+	ldq $31, 64($17)					\n\
+	ldq $31, 64($18)					\n\
+								\n\
+	ldq $31, 128($17)					\n\
+	ldq $31, 128($18)					\n\
+								\n\
+	ldq $31, 192($17)					\n\
+	ldq $31, 192($18)					\n\
+	.align 4						\n\
+2:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,8($17)						\n\
+	ldq $3,8($18)						\n\
+								\n\
+	ldq $4,16($17)						\n\
+	ldq $5,16($18)						\n\
+	ldq $6,24($17)						\n\
+	ldq $7,24($18)						\n\
+								\n\
+	ldq $19,32($17)						\n\
+	ldq $20,32($18)						\n\
+	ldq $21,40($17)						\n\
+	ldq $22,40($18)						\n\
+								\n\
+	ldq $23,48($17)						\n\
+	ldq $24,48($18)						\n\
+	ldq $25,56($17)						\n\
+	ldq $27,56($18)						\n\
+								\n\
+	ldq $31,256($17)					\n\
+	xor $0,$1,$0		# 8 cycles from $1 load		\n\
+	ldq $31,256($18)					\n\
+	xor $2,$3,$2						\n\
+								\n\
+	stq $0,0($17)						\n\
+	xor $4,$5,$4						\n\
+	stq $2,8($17)						\n\
+	xor $6,$7,$6						\n\
+								\n\
+	stq $4,16($17)						\n\
+	xor $19,$20,$19						\n\
+	stq $6,24($17)						\n\
+	xor $21,$22,$21						\n\
+								\n\
+	stq $19,32($17)						\n\
+	xor $23,$24,$23						\n\
+	stq $21,40($17)						\n\
+	xor $25,$27,$25						\n\
+								\n\
+	stq $23,48($17)						\n\
+	subq $16,1,$16						\n\
+	stq $25,56($17)						\n\
+	addq $17,64,$17						\n\
+								\n\
+	addq $18,64,$18						\n\
+	bgt $16,2b						\n\
+	ret							\n\
+	.end xor_alpha_prefetch_2				\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_prefetch_3				\n\
+xor_alpha_prefetch_3:						\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+								\n\
+	ldq $31, 0($17)						\n\
+	ldq $31, 0($18)						\n\
+	ldq $31, 0($19)						\n\
+								\n\
+	ldq $31, 64($17)					\n\
+	ldq $31, 64($18)					\n\
+	ldq $31, 64($19)					\n\
+								\n\
+	ldq $31, 128($17)					\n\
+	ldq $31, 128($18)					\n\
+	ldq $31, 128($19)					\n\
+								\n\
+	ldq $31, 192($17)					\n\
+	ldq $31, 192($18)					\n\
+	ldq $31, 192($19)					\n\
+	.align 4						\n\
+3:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,8($17)						\n\
+								\n\
+	ldq $4,8($18)						\n\
+	ldq $6,16($17)						\n\
+	ldq $7,16($18)						\n\
+	ldq $21,24($17)						\n\
+								\n\
+	ldq $22,24($18)						\n\
+	ldq $24,32($17)						\n\
+	ldq $25,32($18)						\n\
+	ldq $5,8($19)						\n\
+								\n\
+	ldq $20,16($19)						\n\
+	ldq $23,24($19)						\n\
+	ldq $27,32($19)						\n\
+	nop							\n\
+								\n\
+	xor $0,$1,$1		# 8 cycles from $0 load		\n\
+	xor $3,$4,$4		# 7 cycles from $4 load		\n\
+	xor $6,$7,$7		# 6 cycles from $7 load		\n\
+	xor $21,$22,$22		# 5 cycles from $22 load	\n\
+								\n\
+	xor $1,$2,$2		# 9 cycles from $2 load		\n\
+	xor $24,$25,$25		# 5 cycles from $25 load	\n\
+	stq $2,0($17)						\n\
+	xor $4,$5,$5		# 6 cycles from $5 load		\n\
+								\n\
+	stq $5,8($17)						\n\
+	xor $7,$20,$20		# 7 cycles from $20 load	\n\
+	stq $20,16($17)						\n\
+	xor $22,$23,$23		# 7 cycles from $23 load	\n\
+								\n\
+	stq $23,24($17)						\n\
+	xor $25,$27,$27		# 7 cycles from $27 load	\n\
+	stq $27,32($17)						\n\
+	nop							\n\
+								\n\
+	ldq $0,40($17)						\n\
+	ldq $1,40($18)						\n\
+	ldq $3,48($17)						\n\
+	ldq $4,48($18)						\n\
+								\n\
+	ldq $6,56($17)						\n\
+	ldq $7,56($18)						\n\
+	ldq $2,40($19)						\n\
+	ldq $5,48($19)						\n\
+								\n\
+	ldq $20,56($19)						\n\
+	ldq $31,256($17)					\n\
+	ldq $31,256($18)					\n\
+	ldq $31,256($19)					\n\
+								\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	xor $3,$4,$4		# 5 cycles from $4 load		\n\
+	xor $6,$7,$7		# 5 cycles from $7 load		\n\
+	xor $1,$2,$2		# 4 cycles from $2 load		\n\
+								\n\
+	xor $4,$5,$5		# 5 cycles from $5 load		\n\
+	xor $7,$20,$20		# 4 cycles from $20 load	\n\
+	stq $2,40($17)						\n\
+	subq $16,1,$16						\n\
+								\n\
+	stq $5,48($17)						\n\
+	addq $19,64,$19						\n\
+	stq $20,56($17)						\n\
+	addq $18,64,$18						\n\
+								\n\
+	addq $17,64,$17						\n\
+	bgt $16,3b						\n\
+	ret							\n\
+	.end xor_alpha_prefetch_3				\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_prefetch_4				\n\
+xor_alpha_prefetch_4:						\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+								\n\
+	ldq $31, 0($17)						\n\
+	ldq $31, 0($18)						\n\
+	ldq $31, 0($19)						\n\
+	ldq $31, 0($20)						\n\
+								\n\
+	ldq $31, 64($17)					\n\
+	ldq $31, 64($18)					\n\
+	ldq $31, 64($19)					\n\
+	ldq $31, 64($20)					\n\
+								\n\
+	ldq $31, 128($17)					\n\
+	ldq $31, 128($18)					\n\
+	ldq $31, 128($19)					\n\
+	ldq $31, 128($20)					\n\
+								\n\
+	ldq $31, 192($17)					\n\
+	ldq $31, 192($18)					\n\
+	ldq $31, 192($19)					\n\
+	ldq $31, 192($20)					\n\
+	.align 4						\n\
+4:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,0($20)						\n\
+								\n\
+	ldq $4,8($17)						\n\
+	ldq $5,8($18)						\n\
+	ldq $6,8($19)						\n\
+	ldq $7,8($20)						\n\
+								\n\
+	ldq $21,16($17)						\n\
+	ldq $22,16($18)						\n\
+	ldq $23,16($19)						\n\
+	ldq $24,16($20)						\n\
+								\n\
+	ldq $25,24($17)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	ldq $27,24($18)						\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	ldq $0,24($19)						\n\
+	xor $1,$3,$3						\n\
+	ldq $1,24($20)						\n\
+	xor $4,$5,$5		# 7 cycles from $5 load		\n\
+								\n\
+	stq $3,0($17)						\n\
+	xor $6,$7,$7						\n\
+	xor $21,$22,$22		# 7 cycles from $22 load	\n\
+	xor $5,$7,$7						\n\
+								\n\
+	stq $7,8($17)						\n\
+	xor $23,$24,$24		# 7 cycles from $24 load	\n\
+	ldq $2,32($17)						\n\
+	xor $22,$24,$24						\n\
+								\n\
+	ldq $3,32($18)						\n\
+	ldq $4,32($19)						\n\
+	ldq $5,32($20)						\n\
+	xor $25,$27,$27		# 8 cycles from $27 load	\n\
+								\n\
+	ldq $6,40($17)						\n\
+	ldq $7,40($18)						\n\
+	ldq $21,40($19)						\n\
+	ldq $22,40($20)						\n\
+								\n\
+	stq $24,16($17)						\n\
+	xor $0,$1,$1		# 9 cycles from $1 load		\n\
+	xor $2,$3,$3		# 5 cycles from $3 load		\n\
+	xor $27,$1,$1						\n\
+								\n\
+	stq $1,24($17)						\n\
+	xor $4,$5,$5		# 5 cycles from $5 load		\n\
+	ldq $23,48($17)						\n\
+	xor $3,$5,$5						\n\
+								\n\
+	ldq $24,48($18)						\n\
+	ldq $25,48($19)						\n\
+	ldq $27,48($20)						\n\
+	ldq $0,56($17)						\n\
+								\n\
+	ldq $1,56($18)						\n\
+	ldq $2,56($19)						\n\
+	ldq $3,56($20)						\n\
+	xor $6,$7,$7		# 8 cycles from $6 load		\n\
+								\n\
+	ldq $31,256($17)					\n\
+	xor $21,$22,$22		# 8 cycles from $22 load	\n\
+	ldq $31,256($18)					\n\
+	xor $7,$22,$22						\n\
+								\n\
+	ldq $31,256($19)					\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+	ldq $31,256($20)					\n\
+	xor $25,$27,$27		# 6 cycles from $27 load	\n\
+								\n\
+	stq $5,32($17)						\n\
+	xor $24,$27,$27						\n\
+	xor $0,$1,$1		# 7 cycles from $1 load		\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	stq $22,40($17)						\n\
+	xor $1,$3,$3						\n\
+	stq $27,48($17)						\n\
+	subq $16,1,$16						\n\
+								\n\
+	stq $3,56($17)						\n\
+	addq $20,64,$20						\n\
+	addq $19,64,$19						\n\
+	addq $18,64,$18						\n\
+								\n\
+	addq $17,64,$17						\n\
+	bgt $16,4b						\n\
+	ret							\n\
+	.end xor_alpha_prefetch_4				\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_prefetch_5				\n\
+xor_alpha_prefetch_5:						\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+								\n\
+	ldq $31, 0($17)						\n\
+	ldq $31, 0($18)						\n\
+	ldq $31, 0($19)						\n\
+	ldq $31, 0($20)						\n\
+	ldq $31, 0($21)						\n\
+								\n\
+	ldq $31, 64($17)					\n\
+	ldq $31, 64($18)					\n\
+	ldq $31, 64($19)					\n\
+	ldq $31, 64($20)					\n\
+	ldq $31, 64($21)					\n\
+								\n\
+	ldq $31, 128($17)					\n\
+	ldq $31, 128($18)					\n\
+	ldq $31, 128($19)					\n\
+	ldq $31, 128($20)					\n\
+	ldq $31, 128($21)					\n\
+								\n\
+	ldq $31, 192($17)					\n\
+	ldq $31, 192($18)					\n\
+	ldq $31, 192($19)					\n\
+	ldq $31, 192($20)					\n\
+	ldq $31, 192($21)					\n\
+	.align 4						\n\
+5:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,0($20)						\n\
+								\n\
+	ldq $4,0($21)						\n\
+	ldq $5,8($17)						\n\
+	ldq $6,8($18)						\n\
+	ldq $7,8($19)						\n\
+								\n\
+	ldq $22,8($20)						\n\
+	ldq $23,8($21)						\n\
+	ldq $24,16($17)						\n\
+	ldq $25,16($18)						\n\
+								\n\
+	ldq $27,16($19)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	ldq $28,16($20)						\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	ldq $0,16($21)						\n\
+	xor $1,$3,$3						\n\
+	ldq $1,24($17)						\n\
+	xor $3,$4,$4		# 7 cycles from $4 load		\n\
+								\n\
+	stq $4,0($17)						\n\
+	xor $5,$6,$6		# 7 cycles from $6 load		\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	xor $6,$23,$23		# 7 cycles from $23 load	\n\
+								\n\
+	ldq $2,24($18)						\n\
+	xor $22,$23,$23						\n\
+	ldq $3,24($19)						\n\
+	xor $24,$25,$25		# 8 cycles from $25 load	\n\
+								\n\
+	stq $23,8($17)						\n\
+	xor $25,$27,$27		# 8 cycles from $27 load	\n\
+	ldq $4,24($20)						\n\
+	xor $28,$0,$0		# 7 cycles from $0 load		\n\
+								\n\
+	ldq $5,24($21)						\n\
+	xor $27,$0,$0						\n\
+	ldq $6,32($17)						\n\
+	ldq $7,32($18)						\n\
+								\n\
+	stq $0,16($17)						\n\
+	xor $1,$2,$2		# 6 cycles from $2 load		\n\
+	ldq $22,32($19)						\n\
+	xor $3,$4,$4		# 4 cycles from $4 load		\n\
+								\n\
+	ldq $23,32($20)						\n\
+	xor $2,$4,$4						\n\
+	ldq $24,32($21)						\n\
+	ldq $25,40($17)						\n\
+								\n\
+	ldq $27,40($18)						\n\
+	ldq $28,40($19)						\n\
+	ldq $0,40($20)						\n\
+	xor $4,$5,$5		# 7 cycles from $5 load		\n\
+								\n\
+	stq $5,24($17)						\n\
+	xor $6,$7,$7		# 7 cycles from $7 load		\n\
+	ldq $1,40($21)						\n\
+	ldq $2,48($17)						\n\
+								\n\
+	ldq $3,48($18)						\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	ldq $4,48($19)						\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+								\n\
+	ldq $5,48($20)						\n\
+	xor $22,$24,$24						\n\
+	ldq $6,48($21)						\n\
+	xor $25,$27,$27		# 7 cycles from $27 load	\n\
+								\n\
+	stq $24,32($17)						\n\
+	xor $27,$28,$28		# 8 cycles from $28 load	\n\
+	ldq $7,56($17)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+								\n\
+	ldq $22,56($18)						\n\
+	ldq $23,56($19)						\n\
+	ldq $24,56($20)						\n\
+	ldq $25,56($21)						\n\
+								\n\
+	ldq $31,256($17)					\n\
+	xor $28,$1,$1						\n\
+	ldq $31,256($18)					\n\
+	xor $2,$3,$3		# 9 cycles from $3 load		\n\
+								\n\
+	ldq $31,256($19)					\n\
+	xor $3,$4,$4		# 9 cycles from $4 load		\n\
+	ldq $31,256($20)					\n\
+	xor $5,$6,$6		# 8 cycles from $6 load		\n\
+								\n\
+	stq $1,40($17)						\n\
+	xor $4,$6,$6						\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+								\n\
+	stq $6,48($17)						\n\
+	xor $22,$24,$24						\n\
+	ldq $31,256($21)					\n\
+	xor $24,$25,$25		# 8 cycles from $25 load	\n\
+								\n\
+	stq $25,56($17)						\n\
+	subq $16,1,$16						\n\
+	addq $21,64,$21						\n\
+	addq $20,64,$20						\n\
+								\n\
+	addq $19,64,$19						\n\
+	addq $18,64,$18						\n\
+	addq $17,64,$17						\n\
+	bgt $16,5b						\n\
+								\n\
+	ret							\n\
+	.end xor_alpha_prefetch_5				\n\
 ");
 
 static struct xor_block_template xor_block_alpha = {
-	name: "alpha",
-	do_2: xor_alpha_2,
-	do_3: xor_alpha_3,
-	do_4: xor_alpha_4,
-	do_5: xor_alpha_5,
+	.name	= "alpha",
+	.do_2	= xor_alpha_2,
+	.do_3	= xor_alpha_3,
+	.do_4	= xor_alpha_4,
+	.do_5	= xor_alpha_5,
 };
 
 static struct xor_block_template xor_block_alpha_prefetch = {
-	name: "alpha prefetch",
-	do_2: xor_alpha_prefetch_2,
-	do_3: xor_alpha_prefetch_3,
-	do_4: xor_alpha_prefetch_4,
-	do_5: xor_alpha_prefetch_5,
+	.name	= "alpha prefetch",
+	.do_2	= xor_alpha_prefetch_2,
+	.do_3	= xor_alpha_prefetch_3,
+	.do_4	= xor_alpha_prefetch_4,
+	.do_5	= xor_alpha_prefetch_5,
 };
 
 /* For grins, also test the generic routines.  */
diff -urN linux-2.4.22-bk24/net/ipv4/netfilter/ipt_REJECT.c linux-2.4.22-bk25/net/ipv4/netfilter/ipt_REJECT.c
--- linux-2.4.22-bk24/net/ipv4/netfilter/ipt_REJECT.c	2003-09-26 02:49:41.000000000 -0700
+++ linux-2.4.22-bk25/net/ipv4/netfilter/ipt_REJECT.c	2003-09-26 02:49:45.000000000 -0700
@@ -34,16 +34,17 @@
 		attach(new_skb, nfct);
 }
 
-static inline struct rtable *route_reverse(struct sk_buff *skb, int local)
+static inline struct rtable *route_reverse(struct sk_buff *skb, int hook)
 {
 	struct iphdr *iph = skb->nh.iph;
 	struct dst_entry *odst;
 	struct rt_key key = {};
 	struct rtable *rt;
 
-	if (local) {
+	if (hook != NF_IP_FORWARD) {
 		key.dst = iph->saddr;
-		key.src = iph->daddr;
+		if (hook == NF_IP_LOCAL_IN)
+			key.src = iph->daddr;
 		key.tos = RT_TOS(iph->tos);
 
 		if (ip_route_output_key(&rt, &key) != 0)
@@ -75,7 +76,7 @@
 }
 
 /* Send RST reply */
-static void send_reset(struct sk_buff *oldskb, int local)
+static void send_reset(struct sk_buff *oldskb, int hook)
 {
 	struct sk_buff *nskb;
 	struct tcphdr *otcph, *tcph;
@@ -104,7 +105,7 @@
 			 csum_partial((char *)otcph, otcplen, 0)) != 0)
 		return;
 
-	if ((rt = route_reverse(oldskb, local)) == NULL)
+	if ((rt = route_reverse(oldskb, hook)) == NULL)
 		return;
 
 	hh_len = (rt->u.dst.dev->hard_header_len + 15)&~15;
@@ -186,8 +187,8 @@
 	nskb->nh.iph->check = ip_fast_csum((unsigned char *)nskb->nh.iph, 
 					   nskb->nh.iph->ihl);
 
-	/* dst->pmtu can be zero because it is not set for local dst's */
-	if (nskb->dst->pmtu && nskb->len > nskb->dst->pmtu)
+	/* "Never happens" */
+	if (nskb->len > nskb->dst->pmtu)
 		goto free_nskb;
 
 	connection_attach(nskb, oldskb->nfct);
@@ -372,7 +373,7 @@
 		send_unreach(*pskb, ICMP_PKT_FILTERED);
 		break;
 	case IPT_TCP_RESET:
-		send_reset(*pskb, hooknum == NF_IP_LOCAL_IN);
+		send_reset(*pskb, hooknum);
 	case IPT_ICMP_ECHOREPLY:
 		/* Doesn't happen. */
 		break;