## Automatically generated incremental diff
## From:   linux-2.4.29-bk10
## To:     linux-2.4.29-bk11
## Robot:  $Id: make-incremental-diff,v 1.12 2004/01/06 07:19:36 hpa Exp $

diff -urN linux-2.4.29-bk10/Makefile linux-2.4.29-bk11/Makefile
--- linux-2.4.29-bk10/Makefile	2005-02-10 02:50:23.818306673 -0800
+++ linux-2.4.29-bk11/Makefile	2005-02-10 02:50:27.286457251 -0800
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 4
 SUBLEVEL = 29
-EXTRAVERSION = -bk10
+EXTRAVERSION = -bk11
 
 KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 
diff -urN linux-2.4.29-bk10/arch/i386/kernel/pci-irq.c linux-2.4.29-bk11/arch/i386/kernel/pci-irq.c
--- linux-2.4.29-bk10/arch/i386/kernel/pci-irq.c	2005-02-10 02:50:23.819306716 -0800
+++ linux-2.4.29-bk11/arch/i386/kernel/pci-irq.c	2005-02-10 02:50:27.287457294 -0800
@@ -1127,6 +1127,8 @@
 	if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
 		char *msg;
 
+		pin--;		/* interrupt pins are numbered starting from 1 */
+
 		/* With IDE legacy devices the IRQ lookup failure is not a problem.. */
 		if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
 			return;
@@ -1134,7 +1136,6 @@
 		if (io_apic_assign_pci_irqs) {
 			int irq;
 
-			pin--;		/* interrupt pins are numbered starting from 1 */
 			irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
 			/*
 			 * Busses behind bridges are typically not listed in the MP-table.
@@ -1167,7 +1168,7 @@
 		else
 			msg = " Please try using pci=biosirq.";
 		printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
-		       'A' + pin - 1, dev->slot_name, msg);
+		       'A' + pin, dev->slot_name, msg);
 	}
 	/* VIA bridges use interrupt line for apic/pci steering across
 	   the V-Link */
diff -urN linux-2.4.29-bk10/arch/sparc64/kernel/ioctl32.c linux-2.4.29-bk11/arch/sparc64/kernel/ioctl32.c
--- linux-2.4.29-bk10/arch/sparc64/kernel/ioctl32.c	2005-01-19 06:09:39.000000000 -0800
+++ linux-2.4.29-bk11/arch/sparc64/kernel/ioctl32.c	2005-02-10 02:50:27.508466890 -0800
@@ -562,6 +562,8 @@
 
 	if (!(current->thread.flags & SPARC_FLAG_32BIT))
 		usp += STACK_BIAS;
+	else
+		usp &= 0xffffffffUL;
 
 	return (void *) (usp - len);
 }
diff -urN linux-2.4.29-bk10/arch/sparc64/kernel/smp.c linux-2.4.29-bk11/arch/sparc64/kernel/smp.c
--- linux-2.4.29-bk10/arch/sparc64/kernel/smp.c	2005-01-19 06:09:39.000000000 -0800
+++ linux-2.4.29-bk11/arch/sparc64/kernel/smp.c	2005-02-10 02:50:27.509466933 -0800
@@ -1034,7 +1034,7 @@
 void smp_capture(void)
 {
 	if (smp_processors_ready) {
-		int result = __atomic_add(1, &smp_capture_depth);
+		int result = atomic_add_ret(1, &smp_capture_depth);
 
 		membar("#StoreStore | #LoadStore");
 		if (result == 1) {
diff -urN linux-2.4.29-bk10/arch/sparc64/kernel/sparc64_ksyms.c linux-2.4.29-bk11/arch/sparc64/kernel/sparc64_ksyms.c
--- linux-2.4.29-bk10/arch/sparc64/kernel/sparc64_ksyms.c	2004-11-17 03:54:21.000000000 -0800
+++ linux-2.4.29-bk11/arch/sparc64/kernel/sparc64_ksyms.c	2005-02-10 02:50:27.510466977 -0800
@@ -173,18 +173,21 @@
 EXPORT_SYMBOL(__up);
 
 /* Atomic counter implementation. */
-EXPORT_SYMBOL(__atomic_add);
-EXPORT_SYMBOL(__atomic_sub);
+EXPORT_SYMBOL(atomic_add);
+EXPORT_SYMBOL(atomic_add_ret);
+EXPORT_SYMBOL(atomic_sub);
+EXPORT_SYMBOL(atomic_sub_ret);
 #ifdef CONFIG_SMP
 EXPORT_SYMBOL(atomic_dec_and_lock);
 #endif
 
 /* Atomic bit operations. */
-EXPORT_SYMBOL(___test_and_set_bit);
-EXPORT_SYMBOL(___test_and_clear_bit);
-EXPORT_SYMBOL(___test_and_change_bit);
-EXPORT_SYMBOL(___test_and_set_le_bit);
-EXPORT_SYMBOL(___test_and_clear_le_bit);
+EXPORT_SYMBOL(test_and_set_bit);
+EXPORT_SYMBOL(test_and_clear_bit);
+EXPORT_SYMBOL(test_and_change_bit);
+EXPORT_SYMBOL(set_bit);
+EXPORT_SYMBOL(clear_bit);
+EXPORT_SYMBOL(change_bit);
 
 EXPORT_SYMBOL(ivector_table);
 EXPORT_SYMBOL(enable_irq);
diff -urN linux-2.4.29-bk10/arch/sparc64/kernel/sys_sparc32.c linux-2.4.29-bk11/arch/sparc64/kernel/sys_sparc32.c
--- linux-2.4.29-bk10/arch/sparc64/kernel/sys_sparc32.c	2005-02-10 02:50:24.115319568 -0800
+++ linux-2.4.29-bk11/arch/sparc64/kernel/sys_sparc32.c	2005-02-10 02:50:27.513467107 -0800
@@ -770,6 +770,8 @@
 
 	if (!(current->thread.flags & SPARC_FLAG_32BIT))
 		usp += STACK_BIAS;
+	else
+		usp &= 0xffffffffUL;
 
 	return (void *) (usp - len);
 }
diff -urN linux-2.4.29-bk10/arch/sparc64/lib/atomic.S linux-2.4.29-bk11/arch/sparc64/lib/atomic.S
--- linux-2.4.29-bk10/arch/sparc64/lib/atomic.S	2005-02-10 02:50:24.116319612 -0800
+++ linux-2.4.29-bk11/arch/sparc64/lib/atomic.S	2005-02-10 02:50:27.513467107 -0800
@@ -4,46 +4,83 @@
  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
  */
 
+#include <linux/config.h>
 #include <asm/asi.h>
 
+	/* On SMP we need to use memory barriers to ensure
+	 * correct memory operation ordering, nop these out
+	 * for uniprocessor.
+	 */
+#ifdef CONFIG_SMP
+#define ATOMIC_PRE_BARRIER	membar #StoreLoad | #LoadLoad
+#define ATOMIC_POST_BARRIER	membar #StoreLoad | #StoreStore
+#else
+#define ATOMIC_PRE_BARRIER	nop
+#define ATOMIC_POST_BARRIER	nop
+#endif
+
 	.text
 
 	.globl	atomic_impl_begin, atomic_impl_end
 atomic_impl_begin:
-	/* We use these stubs for the uncommon case
-	 * of contention on the atomic value.  This is
-	 * so that we can keep the main fast path 8
-	 * instructions long and thus fit into a single
-	 * L2 cache line.
+	/* Two versions of the atomic routines, one that
+	 * does not return a value and does not perform
+	 * memory barriers, and a second which returns
+	 * a value and does the barriers.
 	 */
-__atomic_add_membar:
-	ba,pt	%xcc, __atomic_add
-	 membar	#StoreLoad | #StoreStore
-
-__atomic_sub_membar:
-	ba,pt	%xcc, __atomic_sub
-	 membar	#StoreLoad | #StoreStore
-
-	.align	64
-	.globl	__atomic_add
-__atomic_add: /* %o0 = increment, %o1 = atomic_ptr */
-	lduw	[%o1], %g5
+	.globl	atomic_add
+	.type	atomic_add,#function
+atomic_add: /* %o0 = increment, %o1 = atomic_ptr */
+1:	lduw	[%o1], %g5
+	add	%g5, %o0, %g7
+	cas	[%o1], %g5, %g7
+	cmp	%g5, %g7
+	bne,pn	%icc, 1b
+	 nop
+	retl
+	 nop
+	.size	atomic_add, .-atomic_add
+
+	.globl	atomic_sub
+	.type	atomic_sub,#function
+atomic_sub: /* %o0 = decrement, %o1 = atomic_ptr */
+1:	lduw	[%o1], %g5
+	sub	%g5, %o0, %g7
+	cas	[%o1], %g5, %g7
+	cmp	%g5, %g7
+	bne,pn	%icc, 1b
+	 nop
+	retl
+	 nop
+	.size	atomic_sub, .-atomic_sub
+
+	.globl	atomic_add_ret
+	.type	atomic_add_ret,#function
+atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
+	ATOMIC_PRE_BARRIER
+1:	lduw	[%o1], %g5
 	add	%g5, %o0, %g7
 	cas	[%o1], %g5, %g7
 	cmp	%g5, %g7
-	bne,pn	%icc, __atomic_add_membar
+	bne,pn	%icc, 1b
 	 add	%g7, %o0, %g7
+	ATOMIC_POST_BARRIER
 	retl
 	 sra	%g7, 0, %o0
+	.size	atomic_add_ret, .-atomic_add_ret
 
-	.globl	__atomic_sub
-__atomic_sub: /* %o0 = increment, %o1 = atomic_ptr */
-	lduw	[%o1], %g5
+	.globl	atomic_sub_ret
+	.type	atomic_sub_ret,#function
+atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
+	ATOMIC_PRE_BARRIER
+1:	lduw	[%o1], %g5
 	sub	%g5, %o0, %g7
 	cas	[%o1], %g5, %g7
 	cmp	%g5, %g7
-	bne,pn	%icc, __atomic_sub_membar
+	bne,pn	%icc, 1b
 	 sub	%g7, %o0, %g7
+	ATOMIC_POST_BARRIER
 	retl
 	 sra	%g7, 0, %o0
+	.size	atomic_sub_ret, .-atomic_sub_ret
 atomic_impl_end:
diff -urN linux-2.4.29-bk10/arch/sparc64/lib/bitops.S linux-2.4.29-bk11/arch/sparc64/lib/bitops.S
--- linux-2.4.29-bk10/arch/sparc64/lib/bitops.S	2001-12-21 09:41:53.000000000 -0800
+++ linux-2.4.29-bk11/arch/sparc64/lib/bitops.S	2005-02-10 02:50:27.514467150 -0800
@@ -4,107 +4,149 @@
  * Copyright (C) 2000 David S. Miller (davem@redhat.com)
  */
 
+#include <linux/config.h>
 #include <asm/asi.h>
 
+	/* On SMP we need to use memory barriers to ensure
+	 * correct memory operation ordering, nop these out
+	 * for uniprocessor.
+	 */
+#ifdef CONFIG_SMP
+#define BITOP_PRE_BARRIER	membar #StoreLoad | #LoadLoad
+#define BITOP_POST_BARRIER	membar #StoreLoad | #StoreStore
+#else
+#define BITOP_PRE_BARRIER	nop
+#define BITOP_POST_BARRIER	nop
+#endif
+
 	.text
-	.align	64
+
 	.globl	__bitops_begin
 __bitops_begin:
 
-	.globl	___test_and_set_bit
-___test_and_set_bit:	/* %o0=nr, %o1=addr */
+
+	.globl	test_and_set_bit
+	.type	test_and_set_bit,#function
+test_and_set_bit:	/* %o0=nr, %o1=addr */
+	BITOP_PRE_BARRIER
 	srlx	%o0, 6, %g1
 	mov	1, %g5
 	sllx	%g1, 3, %g3
 	and	%o0, 63, %g2
 	sllx	%g5, %g2, %g5
 	add	%o1, %g3, %o1
-	ldx	[%o1], %g7
-1:	andcc	%g7, %g5, %o0
-	bne,pn	%xcc, 2f
-	 xor	%g7, %g5, %g1
+1:	ldx	[%o1], %g7
+	or	%g7, %g5, %g1
 	casx	[%o1], %g7, %g1
 	cmp	%g7, %g1
-	bne,a,pn %xcc, 1b
-	 ldx	[%o1], %g7
-2:	retl
-	 membar	#StoreLoad | #StoreStore
-
-	.globl	___test_and_clear_bit
-___test_and_clear_bit:	/* %o0=nr, %o1=addr */
+	bne,pn	%xcc, 1b
+	 and	%g7, %g5, %g2
+	BITOP_POST_BARRIER
+	clr	%o0
+	retl
+	 movrne	%g2, 1, %o0
+	.size	test_and_set_bit, .-test_and_set_bit
+
+	.globl	test_and_clear_bit
+	.type	test_and_clear_bit,#function
+test_and_clear_bit:	/* %o0=nr, %o1=addr */
+	BITOP_PRE_BARRIER
 	srlx	%o0, 6, %g1
 	mov	1, %g5
 	sllx	%g1, 3, %g3
 	and	%o0, 63, %g2
 	sllx	%g5, %g2, %g5
 	add	%o1, %g3, %o1
-	ldx	[%o1], %g7
-1:	andcc	%g7, %g5, %o0
-	be,pn	%xcc, 2f
-	 xor	%g7, %g5, %g1
+1:	ldx	[%o1], %g7
+	andn	%g7, %g5, %g1
 	casx	[%o1], %g7, %g1
 	cmp	%g7, %g1
-	bne,a,pn %xcc, 1b
-	 ldx	[%o1], %g7
-2:	retl
-	 membar	#StoreLoad | #StoreStore
-
-	.globl	___test_and_change_bit
-___test_and_change_bit:	/* %o0=nr, %o1=addr */
+	bne,pn	%xcc, 1b
+	 and	%g7, %g5, %g2
+	BITOP_POST_BARRIER
+	clr	%o0
+	retl
+	 movrne	%g2, 1, %o0
+	.size	test_and_clear_bit, .-test_and_clear_bit
+
+	.globl	test_and_change_bit
+	.type	test_and_change_bit,#function
+test_and_change_bit:	/* %o0=nr, %o1=addr */
+	BITOP_PRE_BARRIER
+	srlx	%o0, 6, %g1
+	mov	1, %g5
+	sllx	%g1, 3, %g3
+	and	%o0, 63, %g2
+	sllx	%g5, %g2, %g5
+	add	%o1, %g3, %o1
+1:	ldx	[%o1], %g7
+	xor	%g7, %g5, %g1
+	casx	[%o1], %g7, %g1
+	cmp	%g7, %g1
+	bne,pn	%xcc, 1b
+	 and	%g7, %g5, %g2
+	BITOP_POST_BARRIER
+	clr	%o0
+	retl
+	 movrne	%g2, 1, %o0
+	.size	test_and_change_bit, .-test_and_change_bit
+
+	.globl	set_bit
+	.type	set_bit,#function
+set_bit:		/* %o0=nr, %o1=addr */
+	srlx	%o0, 6, %g1
+	mov	1, %g5
+	sllx	%g1, 3, %g3
+	and	%o0, 63, %g2
+	sllx	%g5, %g2, %g5
+	add	%o1, %g3, %o1
+1:	ldx	[%o1], %g7
+	or	%g7, %g5, %g1
+	casx	[%o1], %g7, %g1
+	cmp	%g7, %g1
+	bne,pn	%xcc, 1b
+	 nop
+	retl
+	 nop
+	.size	set_bit, .-set_bit
+
+	.globl	clear_bit
+	.type	clear_bit,#function
+clear_bit:		/* %o0=nr, %o1=addr */
+	srlx	%o0, 6, %g1
+	mov	1, %g5
+	sllx	%g1, 3, %g3
+	and	%o0, 63, %g2
+	sllx	%g5, %g2, %g5
+	add	%o1, %g3, %o1
+1:	ldx	[%o1], %g7
+	andn	%g7, %g5, %g1
+	casx	[%o1], %g7, %g1
+	cmp	%g7, %g1
+	bne,pn	%xcc, 1b
+	 nop
+	retl
+	 nop
+	.size	clear_bit, .-clear_bit
+
+	.globl	change_bit
+	.type	change_bit,#function
+change_bit:		/* %o0=nr, %o1=addr */
 	srlx	%o0, 6, %g1
 	mov	1, %g5
 	sllx	%g1, 3, %g3
 	and	%o0, 63, %g2
 	sllx	%g5, %g2, %g5
 	add	%o1, %g3, %o1
-	ldx	[%o1], %g7
-1:	and	%g7, %g5, %o0
+1:	ldx	[%o1], %g7
 	xor	%g7, %g5, %g1
 	casx	[%o1], %g7, %g1
 	cmp	%g7, %g1
-	bne,a,pn %xcc, 1b
-	 ldx	[%o1], %g7
-2:	retl
-	 membar	#StoreLoad | #StoreStore
-	nop
-
-	.globl	___test_and_set_le_bit
-___test_and_set_le_bit:	/* %o0=nr, %o1=addr */
-	srlx	%o0, 5, %g1
-	mov	1, %g5
-	sllx	%g1, 2, %g3
-	and	%o0, 31, %g2
-	sllx	%g5, %g2, %g5
-	add	%o1, %g3, %o1
-	lduwa	[%o1] ASI_PL, %g7
-1:	andcc	%g7, %g5, %o0
-	bne,pn	%icc, 2f
-	 xor	%g7, %g5, %g1
-	casa	[%o1] ASI_PL, %g7, %g1
-	cmp	%g7, %g1
-	bne,a,pn %icc, 1b
-	 lduwa	[%o1] ASI_PL, %g7
-2:	retl
-	 membar	#StoreLoad | #StoreStore
-
-	.globl	___test_and_clear_le_bit
-___test_and_clear_le_bit:	/* %o0=nr, %o1=addr */
-	srlx	%o0, 5, %g1
-	mov	1, %g5
-	sllx	%g1, 2, %g3
-	and	%o0, 31, %g2
-	sllx	%g5, %g2, %g5
-	add	%o1, %g3, %o1
-	lduwa	[%o1] ASI_PL, %g7
-1:	andcc	%g7, %g5, %o0
-	be,pn	%icc, 2f
-	 xor	%g7, %g5, %g1
-	casa	[%o1] ASI_PL, %g7, %g1
-	cmp	%g7, %g1
-	bne,a,pn %icc, 1b
-	 lduwa	[%o1] ASI_PL, %g7
-2:	retl
-	 membar	#StoreLoad | #StoreStore
+	bne,pn	%xcc, 1b
+	 nop
+	retl
+	 nop
+	.size	change_bit, .-change_bit
 
 	.globl	__bitops_end
 __bitops_end:
diff -urN linux-2.4.29-bk10/arch/sparc64/lib/debuglocks.c linux-2.4.29-bk11/arch/sparc64/lib/debuglocks.c
--- linux-2.4.29-bk10/arch/sparc64/lib/debuglocks.c	2001-12-21 09:41:53.000000000 -0800
+++ linux-2.4.29-bk11/arch/sparc64/lib/debuglocks.c	2005-02-10 02:50:27.515467194 -0800
@@ -162,6 +162,7 @@
 runlock_again:
 	/* Spin trying to decrement the counter using casx.  */
 	__asm__ __volatile__(
+"	membar	#StoreLoad | #LoadLoad\n"
 "	ldx	[%0], %%g5\n"
 "	sub	%%g5, 1, %%g7\n"
 "	casx	[%0], %%g5, %%g7\n"
@@ -276,6 +277,7 @@
 	current->thread.smp_lock_count--;
 wlock_again:
 	__asm__ __volatile__(
+"	membar	#StoreLoad | #LoadLoad\n"
 "	mov	1, %%g3\n"
 "	sllx	%%g3, 63, %%g3\n"
 "	ldx	[%0], %%g5\n"
diff -urN linux-2.4.29-bk10/arch/sparc64/lib/rwlock.S linux-2.4.29-bk11/arch/sparc64/lib/rwlock.S
--- linux-2.4.29-bk10/arch/sparc64/lib/rwlock.S	2000-09-08 17:55:17.000000000 -0700
+++ linux-2.4.29-bk11/arch/sparc64/lib/rwlock.S	2005-02-10 02:50:27.515467194 -0800
@@ -24,12 +24,13 @@
 99:	retl
 	 nop
 __read_unlock: /* %o0 = lock_ptr */
+	membar		#StoreLoad | #LoadLoad
 	lduw		[%o0], %g5
 	sub		%g5, 1, %g7
 	cas		[%o0], %g5, %g7
 	cmp		%g5, %g7
 	be,pt		%xcc, 99b
-	 membar		#StoreLoad | #StoreStore
+	 nop
 	ba,a,pt		%xcc, __read_unlock
 
 __read_wait_for_writer:
diff -urN linux-2.4.29-bk10/drivers/char/agp/agp.h linux-2.4.29-bk11/drivers/char/agp/agp.h
--- linux-2.4.29-bk10/drivers/char/agp/agp.h	2004-11-17 03:54:21.000000000 -0800
+++ linux-2.4.29-bk11/drivers/char/agp/agp.h	2005-02-10 02:50:27.518467324 -0800
@@ -217,6 +217,12 @@
 #ifndef PCI_DEVICE_ID_INTEL_915_G_1
 #define PCI_DEVICE_ID_INTEL_915_G_1	0x2582
 #endif
+#ifndef PCI_DEVICE_ID_INTEL_915_GM_0
+#define PCI_DEVICE_ID_INTEL_915_GM_0	0x2590
+#endif
+#ifndef PCI_DEVICE_ID_INTEL_915_GM_1
+#define PCI_DEVICE_ID_INTEL_915_GM_1	0x2592
+#endif
 #ifndef PCI_DEVICE_ID_INTEL_820_0
 #define PCI_DEVICE_ID_INTEL_820_0       0x2500
 #endif
diff -urN linux-2.4.29-bk10/drivers/char/agp/agpgart_be.c linux-2.4.29-bk11/drivers/char/agp/agpgart_be.c
--- linux-2.4.29-bk10/drivers/char/agp/agpgart_be.c	2004-11-17 03:54:21.000000000 -0800
+++ linux-2.4.29-bk11/drivers/char/agp/agpgart_be.c	2005-02-10 02:50:27.535468062 -0800
@@ -1170,14 +1170,14 @@
 	{128, 32768, 5},
 	/* The 64M mode still requires a 128k gatt */
 	{64, 16384, 5},
-	/* For I915G */
+	/* For I915G/I915GM */
 	{256, 65536, 6}
 };
 
 static struct _intel_i830_private {
 	struct pci_dev *i830_dev;   /* device one */
 	volatile u8 *registers;
-	volatile u32 *gtt;	/* I915G */
+	volatile u32 *gtt;	/* I915G/I915GM */
 	int gtt_entries;
 } intel_i830_private;
 
@@ -1220,14 +1220,16 @@
 			break;
 		case I915_GMCH_GMS_STOLEN_48M:
 			/* Check it's really I915 */
-			if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0)
+			if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0 ||
+			    agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_GM_0)
 				gtt_entries = MB(48) - KB(size);
 			else
 				gtt_entries = 0;
 			break;
 		case I915_GMCH_GMS_STOLEN_64M:
 			/* Check it's really I915 */
-			if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0)
+			if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0 ||
+			    agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_GM_0)
 				gtt_entries = MB(64) - KB(size);
 			else
 				gtt_entries = 0;
@@ -1287,7 +1289,8 @@
 	num_entries = size->num_entries;
 	agp_bridge.gatt_table_real = 0;
 
-	if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0) {
+	if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0 ||
+	    agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_GM_0) {
 		pci_read_config_dword(intel_i830_private.i830_dev,
 							I915_MMADDR,&temp);
 		pci_read_config_dword(intel_i830_private.i830_dev,
@@ -1331,7 +1334,8 @@
 
 	values = A_SIZE_FIX(agp_bridge.aperture_sizes);
 
-	if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0) {
+	if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0 ||
+	    agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_GM_0) {
 		u32 temp, offset = 0;
 		pci_read_config_dword(intel_i830_private.i830_dev,
 							I915_GMADDR,&temp);
@@ -1375,7 +1379,8 @@
 
 	current_size = A_SIZE_FIX(agp_bridge.current_size);
 
-	if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0)
+	if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0 ||
+	    agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_GM_0)
 		pci_read_config_dword(intel_i830_private.i830_dev,
 							I915_GMADDR,&temp);
 	else
@@ -1392,7 +1397,8 @@
 	CACHE_FLUSH();
 
 	if (agp_bridge.needs_scratch_page == TRUE) {
-		if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0) {
+		if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0 ||
+		    agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_GM_0) {
 			for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++)
 				OUTREG32(intel_i830_private.gtt, i, agp_bridge.scratch_page);
 		} else {
@@ -1406,7 +1412,8 @@
 
 static void intel_i830_cleanup(void)
 {
-	if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0)
+	if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0 ||
+	    agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_GM_0)
 		iounmap((void *)intel_i830_private.gtt);
 
 	iounmap((void *) intel_i830_private.registers);
@@ -1441,7 +1448,8 @@
 
 	CACHE_FLUSH();
 
-	if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0) {
+	if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0 ||
+	    agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_GM_0) {
 		for (i = 0, j = pg_start; i < mem->page_count; i++, j++)
 			OUTREG32(intel_i830_private.gtt, j, agp_bridge.mask_memory(mem->memory[i], mem->type));
 	} else {
@@ -1467,7 +1475,8 @@
 		return (-EINVAL);
 	}
 
-	if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0) {
+	if (agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_G_0 ||
+	    agp_bridge.dev->device == PCI_DEVICE_ID_INTEL_915_GM_0) {
 		for (i = pg_start; i < (mem->page_count + pg_start); i++)
 			OUTREG32(intel_i830_private.gtt, i, agp_bridge.scratch_page);
 	} else {
@@ -6270,6 +6279,13 @@
 		"915G",
 		 intel_845_setup },
 
+	{ PCI_DEVICE_ID_INTEL_915_GM_0,
+		PCI_VENDOR_ID_INTEL,
+		INTEL_I915_GM,
+		"Intel(R)",
+		"915GM",
+		 intel_845_setup },
+
 	{ PCI_DEVICE_ID_INTEL_840_0,
 		PCI_VENDOR_ID_INTEL,
 		INTEL_I840,
@@ -7021,6 +7037,33 @@
 			agp_bridge.type = INTEL_I810;
 			return intel_i830_setup(i810_dev);
 
+		case PCI_DEVICE_ID_INTEL_915_GM_0:
+			i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
+					PCI_DEVICE_ID_INTEL_915_GM_1, NULL);
+			if(i810_dev && PCI_FUNC(i810_dev->devfn) != 0) {
+				i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
+					PCI_DEVICE_ID_INTEL_915_GM_1, i810_dev);
+			}
+
+			if (i810_dev == NULL) {
+                                /* 
+                                 * We probably have a 915GM chipset
+                                 * with an external graphics
+                                 * card. It will be initialized later 
+                                 */
+				printk(KERN_ERR PFX "Detected an "
+				       "Intel(R) 915GM, but could not"
+				       " find the"
+				       " secondary device. Assuming a "
+				       "non-integrated video card.\n");
+				agp_bridge.type = INTEL_I915_GM;
+				break;
+			}
+			printk(KERN_INFO PFX "Detected an Intel(R) "
+				   "915GM Chipset.\n");
+			agp_bridge.type = INTEL_I810;
+			return intel_i830_setup(i810_dev);
+
 		default:
 			break;
 		}
diff -urN linux-2.4.29-bk10/drivers/net/tg3.c linux-2.4.29-bk11/drivers/net/tg3.c
--- linux-2.4.29-bk10/drivers/net/tg3.c	2005-02-10 02:50:24.181322434 -0800
+++ linux-2.4.29-bk11/drivers/net/tg3.c	2005-02-10 02:50:27.551468757 -0800
@@ -59,8 +59,8 @@
 
 #define DRV_MODULE_NAME		"tg3"
 #define PFX DRV_MODULE_NAME	": "
-#define DRV_MODULE_VERSION	"3.19"
-#define DRV_MODULE_RELDATE	"January 26, 2005"
+#define DRV_MODULE_VERSION	"3.21"
+#define DRV_MODULE_RELDATE	"February 8, 2005"
 
 #define TG3_DEF_MAC_MODE	0
 #define TG3_DEF_RX_MODE		0
@@ -877,7 +877,7 @@
 			      GRC_LCLCTRL_GPIO_OUTPUT1));
 			udelay(100);
 		} else {
-			int no_gpio2;
+			u32 no_gpio2;
 			u32 grc_local_ctrl;
 
 			if (tp_peer != tp &&
@@ -885,8 +885,8 @@
 				return;
 
 			/* On 5753 and variants, GPIO2 cannot be used. */
-			no_gpio2 = (tp->nic_sram_data_cfg &
-				    NIC_SRAM_DATA_CFG_NO_GPIO2) != 0;
+			no_gpio2 = tp->nic_sram_data_cfg &
+				    NIC_SRAM_DATA_CFG_NO_GPIO2;
 
 			grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
 					 GRC_LCLCTRL_GPIO_OE1 |
@@ -898,29 +898,17 @@
 						    GRC_LCLCTRL_GPIO_OUTPUT2);
 			}
 			tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
-			       grc_local_ctrl);
+						grc_local_ctrl);
 			udelay(100);
 
-			grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
-					 GRC_LCLCTRL_GPIO_OE1 |
-					 GRC_LCLCTRL_GPIO_OE2 |
-					 GRC_LCLCTRL_GPIO_OUTPUT0 |
-					 GRC_LCLCTRL_GPIO_OUTPUT1 |
-					 GRC_LCLCTRL_GPIO_OUTPUT2;
-			if (no_gpio2) {
-				grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
-						    GRC_LCLCTRL_GPIO_OUTPUT2);
-			}
+			grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
+
 			tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
-			       grc_local_ctrl);
+						grc_local_ctrl);
 			udelay(100);
 
-			grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
-					 GRC_LCLCTRL_GPIO_OE1 |
-					 GRC_LCLCTRL_GPIO_OE2 |
-					 GRC_LCLCTRL_GPIO_OUTPUT0 |
-					 GRC_LCLCTRL_GPIO_OUTPUT1;
 			if (!no_gpio2) {
+				grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
 				tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
 				       grc_local_ctrl);
 				udelay(100);
@@ -2130,8 +2118,9 @@
 		if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
 			port_a = 0;
 
-		serdes_cfg = tr32(MAC_SERDES_CFG) &
-			((1 << 23) | (1 << 22) | (1 << 21) | (1 << 20));
+		/* preserve bits 0-11,13,14 for signal pre-emphasis */
+		/* preserve bits 20-23 for voltage regulator */
+		serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
 	}
 
 	sg_dig_ctrl = tr32(SG_DIG_CTRL);
@@ -2142,9 +2131,9 @@
 				u32 val = serdes_cfg;
 
 				if (port_a)
-					val |= 0xc010880;
+					val |= 0xc010000;
 				else
-					val |= 0x4010880;
+					val |= 0x4010000;
 				tw32_f(MAC_SERDES_CFG, val);
 			}
 			tw32_f(SG_DIG_CTRL, 0x01388400);
@@ -2167,7 +2156,7 @@
 
 	if (sg_dig_ctrl != expected_sg_dig_ctrl) {
 		if (workaround)
-			tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011880);
+			tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
 		tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
 		udelay(5);
 		tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
@@ -2208,9 +2197,9 @@
 					u32 val = serdes_cfg;
 
 					if (port_a)
-						val |= 0xc010880;
+						val |= 0xc010000;
 					else
-						val |= 0x4010880;
+						val |= 0x4010000;
 
 					tw32_f(MAC_SERDES_CFG, val);
 				}
@@ -2218,8 +2207,12 @@
 				tw32_f(SG_DIG_CTRL, 0x01388400);
 				udelay(40);
 
+				/* Link parallel detection - link is up */
+				/* only if we have PCS_SYNC and not */
+				/* receiving config code words */
 				mac_status = tr32(MAC_STATUS);
-				if (mac_status & MAC_STATUS_PCS_SYNCED) {
+				if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
+				    !(mac_status & MAC_STATUS_RCVD_CFG)) {
 					tg3_setup_flow_control(tp, 0, 0);
 					current_link_up = 1;
 				}
@@ -5393,8 +5386,10 @@
 	udelay(10);
 
 	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
+		if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
+			!(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
 			/* Set drive transmission level to 1.2V  */
+			/* only if the signal pre-emphasis bit is not set  */
 			val = tr32(MAC_SERDES_CFG);
 			val &= 0xfffff000;
 			val |= 0x880;
@@ -7488,6 +7483,8 @@
 		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
 		tp->nic_sram_data_cfg = nic_cfg;
 
+		tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
+
 		eeprom_signature_found = 1;
 
 		if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
@@ -7506,8 +7503,7 @@
 			eeprom_phy_id = 0;
 
 		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
-			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &led_cfg);
-			led_cfg &= (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
+			led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
 				    SHASTA_EXT_LED_MODE_MASK);
 		} else
 			led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
@@ -7565,9 +7561,13 @@
 		if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
 			tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
 
-		tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &cfg2);
 		if (cfg2 & (1 << 17))
 			tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
+
+		/* serdes signal pre-emphasis in register 0x590 set by */
+		/* bootcode if bit 18 is set */
+		if (cfg2 & (1 << 18))
+			tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
 	}
 
 	/* Reading the PHY ID register can conflict with ASF
diff -urN linux-2.4.29-bk10/drivers/net/tg3.h linux-2.4.29-bk11/drivers/net/tg3.h
--- linux-2.4.29-bk10/drivers/net/tg3.h	2005-02-10 02:50:24.183322521 -0800
+++ linux-2.4.29-bk11/drivers/net/tg3.h	2005-02-10 02:50:27.553468844 -0800
@@ -2106,6 +2106,7 @@
 #define TG3_FLG2_CAPACITIVE_COUPLING	0x00004000
 #define TG3_FLG2_FLASH			0x00008000
 #define TG3_FLG2_HW_TSO			0x00010000
+#define TG3_FLG2_SERDES_PREEMPHASIS	0x00020000
 
 	u32				split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ		3
diff -urN linux-2.4.29-bk10/drivers/scsi/sym53c8xx.c linux-2.4.29-bk11/drivers/scsi/sym53c8xx.c
--- linux-2.4.29-bk10/drivers/scsi/sym53c8xx.c	2004-04-14 06:05:32.000000000 -0700
+++ linux-2.4.29-bk11/drivers/scsi/sym53c8xx.c	2005-02-10 02:50:27.571469625 -0800
@@ -13182,7 +13182,7 @@
 	** descriptors.
 	*/
 	if (chip && (chip->features & FE_DAC)) {
-		if (pci_set_dma_mask(pdev, (u64) 0xffffffffff))
+		if (pci_set_dma_mask(pdev, (u64) 0xffffffffffULL))
 			chip->features &= ~FE_DAC_IN_USE;
 		else
 			chip->features |= FE_DAC_IN_USE;
diff -urN linux-2.4.29-bk10/include/asm-sparc64/atomic.h linux-2.4.29-bk11/include/asm-sparc64/atomic.h
--- linux-2.4.29-bk10/include/asm-sparc64/atomic.h	2001-07-19 18:11:13.000000000 -0700
+++ linux-2.4.29-bk11/include/asm-sparc64/atomic.h	2005-02-10 02:50:27.579469973 -0800
@@ -8,31 +8,59 @@
 #ifndef __ARCH_SPARC64_ATOMIC__
 #define __ARCH_SPARC64_ATOMIC__
 
+#include <linux/config.h>
+
 typedef struct { volatile int counter; } atomic_t;
 #define ATOMIC_INIT(i)	{ (i) }
 
 #define atomic_read(v)		((v)->counter)
 #define atomic_set(v, i)	(((v)->counter) = i)
 
-extern int __atomic_add(int, atomic_t *);
-extern int __atomic_sub(int, atomic_t *);
+extern void atomic_add(int, atomic_t *);
+extern void atomic_sub(int, atomic_t *);
+
+extern int atomic_add_ret(int, atomic_t *);
+extern int atomic_sub_ret(int, atomic_t *);
+
+#define atomic_dec_return(v) atomic_sub_ret(1, v)
+
+#define atomic_inc_return(v) atomic_add_ret(1, v)
+
+#define atomic_sub_return(i, v) atomic_sub_ret(i, v)
+
+#define atomic_add_return(i, v) atomic_add_ret(i, v)
+
+/*
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+
+#define atomic_sub_and_test(i, v) (atomic_sub_ret(i, v) == 0)
 
-#define atomic_add(i, v) ((void)__atomic_add(i, v))
-#define atomic_sub(i, v) ((void)__atomic_sub(i, v))
+#define atomic_dec_and_test(v) (atomic_sub_ret(1, v) == 0)
 
-#define atomic_dec_return(v) __atomic_sub(1, v)
-#define atomic_inc_return(v) __atomic_add(1, v)
+#define atomic_inc(v) atomic_add(1, v)
 
-#define atomic_sub_and_test(i, v) (__atomic_sub(i, v) == 0)
-#define atomic_dec_and_test(v) (__atomic_sub(1, v) == 0)
+#define atomic_dec(v) atomic_sub(1, v)
 
-#define atomic_inc(v) ((void)__atomic_add(1, v))
-#define atomic_dec(v) ((void)__atomic_sub(1, v))
+#define atomic_add_negative(i, v) (atomic_add_ret(i, v) < 0)
 
 /* Atomic operations are already serializing */
+#ifdef CONFIG_SMP
+#define smp_mb__before_atomic_dec()	membar("#StoreLoad | #LoadLoad")
+#define smp_mb__after_atomic_dec()	membar("#StoreLoad | #StoreStore")
+#define smp_mb__before_atomic_inc()	membar("#StoreLoad | #LoadLoad")
+#define smp_mb__after_atomic_inc()	membar("#StoreLoad | #StoreStore")
+#else
 #define smp_mb__before_atomic_dec()	barrier()
 #define smp_mb__after_atomic_dec()	barrier()
 #define smp_mb__before_atomic_inc()	barrier()
 #define smp_mb__after_atomic_inc()	barrier()
+#endif
 
 #endif /* !(__ARCH_SPARC64_ATOMIC__) */
diff -urN linux-2.4.29-bk10/include/asm-sparc64/bitops.h linux-2.4.29-bk11/include/asm-sparc64/bitops.h
--- linux-2.4.29-bk10/include/asm-sparc64/bitops.h	2001-12-21 09:42:03.000000000 -0800
+++ linux-2.4.29-bk11/include/asm-sparc64/bitops.h	2005-02-10 02:50:27.580470016 -0800
@@ -1,4 +1,4 @@
-/* $Id: bitops.h,v 1.38 2001/11/19 18:36:34 davem Exp $
+/* $Id: bitops.h,v 1.39 2002/01/30 01:40:00 davem Exp $
  * bitops.h: Bit string operations on the V9.
  *
  * Copyright 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
@@ -7,114 +7,126 @@
 #ifndef _SPARC64_BITOPS_H
 #define _SPARC64_BITOPS_H
 
+#include <linux/config.h>
+#include <linux/compiler.h>
 #include <asm/byteorder.h>
 
-extern long ___test_and_set_bit(unsigned long nr, volatile void *addr);
-extern long ___test_and_clear_bit(unsigned long nr, volatile void *addr);
-extern long ___test_and_change_bit(unsigned long nr, volatile void *addr);
-
-#define test_and_set_bit(nr,addr)	({___test_and_set_bit(nr,addr)!=0;})
-#define test_and_clear_bit(nr,addr)	({___test_and_clear_bit(nr,addr)!=0;})
-#define test_and_change_bit(nr,addr)	({___test_and_change_bit(nr,addr)!=0;})
-#define set_bit(nr,addr)		((void)___test_and_set_bit(nr,addr))
-#define clear_bit(nr,addr)		((void)___test_and_clear_bit(nr,addr))
-#define change_bit(nr,addr)		((void)___test_and_change_bit(nr,addr))
+extern int test_and_set_bit(unsigned long nr, volatile void *addr);
+extern int test_and_clear_bit(unsigned long nr, volatile void *addr);
+extern int test_and_change_bit(unsigned long nr, volatile void *addr);
+extern void set_bit(unsigned long nr, volatile void *addr);
+extern void clear_bit(unsigned long nr, volatile void *addr);
+extern void change_bit(unsigned long nr, volatile void *addr);
 
 /* "non-atomic" versions... */
-#define __set_bit(X,Y)					\
-do {	unsigned long __nr = (X);			\
-	long *__m = ((long *) (Y)) + (__nr >> 6);	\
-	*__m |= (1UL << (__nr & 63));			\
-} while (0)
-#define __clear_bit(X,Y)				\
-do {	unsigned long __nr = (X);			\
-	long *__m = ((long *) (Y)) + (__nr >> 6);	\
-	*__m &= ~(1UL << (__nr & 63));			\
-} while (0)
-#define __change_bit(X,Y)				\
-do {	unsigned long __nr = (X);			\
-	long *__m = ((long *) (Y)) + (__nr >> 6);	\
-	*__m ^= (1UL << (__nr & 63));			\
-} while (0)
-#define __test_and_set_bit(X,Y)				\
-({	unsigned long __nr = (X);			\
-	long *__m = ((long *) (Y)) + (__nr >> 6);	\
-	long __old = *__m;				\
-	long __mask = (1UL << (__nr & 63));		\
-	*__m = (__old | __mask);			\
-	((__old & __mask) != 0);			\
-})
-#define __test_and_clear_bit(X,Y)			\
-({	unsigned long __nr = (X);			\
-	long *__m = ((long *) (Y)) + (__nr >> 6);	\
-	long __old = *__m;				\
-	long __mask = (1UL << (__nr & 63));		\
-	*__m = (__old & ~__mask);			\
-	((__old & __mask) != 0);			\
-})
-#define __test_and_change_bit(X,Y)			\
-({	unsigned long __nr = (X);			\
-	long *__m = ((long *) (Y)) + (__nr >> 6);	\
-	long __old = *__m;				\
-	long __mask = (1UL << (__nr & 63));		\
-	*__m = (__old ^ __mask);			\
-	((__old & __mask) != 0);			\
-})
 
-#define smp_mb__before_clear_bit()	do { } while(0)
-#define smp_mb__after_clear_bit()	do { } while(0)
+static __inline__ void __set_bit(int nr, volatile void *addr)
+{
+	unsigned long *m;
+
+	m = ((unsigned long *)addr) + (nr >> 6);
+	*m |= (1UL << (nr & 63));
+}
+
+static __inline__ void __clear_bit(int nr, volatile void *addr)
+{
+	unsigned long *m;
+
+	m = ((unsigned long *)addr) + (nr >> 6);
+	*m &= ~(1UL << (nr & 63));
+}
 
-extern __inline__ int test_bit(int nr, __const__ void *addr)
+static __inline__ void __change_bit(int nr, volatile void *addr)
 {
-	return (1UL & (((__const__ long *) addr)[nr >> 6] >> (nr & 63))) != 0UL;
+	unsigned long *m;
+
+	m = ((unsigned long *)addr) + (nr >> 6);
+	*m ^= (1UL << (nr & 63));
+}
+
+static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
+	unsigned long old = *m;
+	unsigned long mask = (1UL << (nr & 63));
+
+	*m = (old | mask);
+	return ((old & mask) != 0);
+}
+
+static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
+	unsigned long old = *m;
+	unsigned long mask = (1UL << (nr & 63));
+
+	*m = (old & ~mask);
+	return ((old & mask) != 0);
+}
+
+static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
+	unsigned long old = *m;
+	unsigned long mask = (1UL << (nr & 63));
+
+	*m = (old ^ mask);
+	return ((old & mask) != 0);
+}
+
+#ifdef CONFIG_SMP
+#define smp_mb__before_clear_bit()	membar("#StoreLoad | #LoadLoad")
+#define smp_mb__after_clear_bit()	membar("#StoreLoad | #StoreStore")
+#else
+#define smp_mb__before_clear_bit()	barrier()
+#define smp_mb__after_clear_bit()	barrier()
+#endif
+
+static __inline__ int test_bit(int nr, __const__ volatile void *_addr)
+{
+	__const__ unsigned long *addr;
+
+	addr = (__const__ unsigned long *) _addr;
+
+	return (1UL & ((addr)[nr >> 6] >> (nr & 63))) != 0UL;
 }
 
 /* The easy/cheese version for now. */
-extern __inline__ unsigned long ffz(unsigned long word)
+static __inline__ unsigned long ffz(unsigned long word)
 {
 	unsigned long result;
 
-#ifdef ULTRA_HAS_POPULATION_COUNT	/* Thanks for nothing Sun... */
-	__asm__ __volatile__(
-"	brz,pn	%0, 1f\n"
-"	 neg	%0, %%g1\n"
-"	xnor	%0, %%g1, %%g2\n"
-"	popc	%%g2, %0\n"
-"1:	" : "=&r" (result)
-	  : "0" (word)
-	  : "g1", "g2");
-#else
-#if 1 /* def EASY_CHEESE_VERSION */
 	result = 0;
 	while(word & 1) {
 		result++;
 		word >>= 1;
 	}
-#else
-	unsigned long tmp;
+	return result;
+}
 
-	result = 0;	
-	tmp = ~word & -~word;
-	if (!(unsigned)tmp) {
-		tmp >>= 32;
-		result = 32;
-	}
-	if (!(unsigned short)tmp) {
-		tmp >>= 16;
-		result += 16;
-	}
-	if (!(unsigned char)tmp) {
-		tmp >>= 8;
-		result += 8;
+/**
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static __inline__ unsigned long __ffs(unsigned long word)
+{
+	unsigned long result = 0;
+
+	while (!(word & 1UL)) {
+		result++;
+		word >>= 1;
 	}
-	if (tmp & 0xf0) result += 4;
-	if (tmp & 0xcc) result += 2;
-	if (tmp & 0xaa) result ++;
-#endif
-#endif
 	return result;
 }
 
+/*
+ * fls: find last bit set.
+ */
+
+#define fls(x) generic_fls(x)
+
 #ifdef __KERNEL__
 
 /*
@@ -122,8 +134,12 @@
  * the libc and compiler builtin ffs routines, therefore
  * differs in spirit from the above ffz (man ffs).
  */
-
-#define ffs(x) generic_ffs(x)
+static __inline__ int ffs(int x)
+{
+	if (!x)
+		return 0;
+	return __ffs((unsigned long)x) + 1;
+}
 
 /*
  * hweightN: returns the hamming weight (i.e. the number
@@ -132,7 +148,15 @@
 
 #ifdef ULTRA_HAS_POPULATION_COUNT
 
-extern __inline__ unsigned int hweight32(unsigned int w)
+static __inline__ unsigned int hweight64(unsigned long w)
+{
+	unsigned int res;
+
+	__asm__ ("popc %1,%0" : "=r" (res) : "r" (w));
+	return res;
+}
+
+static __inline__ unsigned int hweight32(unsigned int w)
 {
 	unsigned int res;
 
@@ -140,7 +164,7 @@
 	return res;
 }
 
-extern __inline__ unsigned int hweight16(unsigned int w)
+static __inline__ unsigned int hweight16(unsigned int w)
 {
 	unsigned int res;
 
@@ -148,7 +172,7 @@
 	return res;
 }
 
-extern __inline__ unsigned int hweight8(unsigned int w)
+static __inline__ unsigned int hweight8(unsigned int w)
 {
 	unsigned int res;
 
@@ -158,6 +182,7 @@
 
 #else
 
+#define hweight64(x) generic_hweight64(x)
 #define hweight32(x) generic_hweight32(x)
 #define hweight16(x) generic_hweight16(x)
 #define hweight8(x) generic_hweight8(x)
@@ -170,7 +195,7 @@
  * on Linus's ALPHA routines, which are pretty portable BTW.
  */
 
-extern __inline__ unsigned long find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
+static __inline__ unsigned long find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
 {
 	unsigned long *p = ((unsigned long *) addr) + (offset >> 6);
 	unsigned long result = offset & ~63UL;
@@ -211,15 +236,12 @@
 #define find_first_zero_bit(addr, size) \
         find_next_zero_bit((addr), (size), 0)
 
-extern long ___test_and_set_le_bit(int nr, volatile void *addr);
-extern long ___test_and_clear_le_bit(int nr, volatile void *addr);
-
-#define test_and_set_le_bit(nr,addr)	({___test_and_set_le_bit(nr,addr)!=0;})
-#define test_and_clear_le_bit(nr,addr)	({___test_and_clear_le_bit(nr,addr)!=0;})
-#define set_le_bit(nr,addr)		((void)___test_and_set_le_bit(nr,addr))
-#define clear_le_bit(nr,addr)		((void)___test_and_clear_le_bit(nr,addr))
+#define test_and_set_le_bit(nr,addr)	\
+	test_and_set_bit((nr) ^ 0x38, (addr))
+#define test_and_clear_le_bit(nr,addr)	\
+	test_and_clear_bit((nr) ^ 0x38, (addr))
 
-extern __inline__ int test_le_bit(int nr, __const__ void * addr)
+static __inline__ int test_le_bit(int nr, __const__ void *addr)
 {
 	int			mask;
 	__const__ unsigned char	*ADDR = (__const__ unsigned char *) addr;
@@ -232,7 +254,7 @@
 #define find_first_zero_le_bit(addr, size) \
         find_next_zero_le_bit((addr), (size), 0)
 
-extern __inline__ unsigned long find_next_zero_le_bit(void *addr, unsigned long size, unsigned long offset)
+static __inline__ unsigned long find_next_zero_le_bit(void *addr, unsigned long size, unsigned long offset)
 {
 	unsigned long *p = ((unsigned long *) addr) + (offset >> 6);
 	unsigned long result = offset & ~63UL;
@@ -271,18 +293,41 @@
 
 #ifdef __KERNEL__
 
-#define ext2_set_bit			test_and_set_le_bit
-#define ext2_clear_bit			test_and_clear_le_bit
-#define ext2_test_bit  			test_le_bit
-#define ext2_find_first_zero_bit	find_first_zero_le_bit
-#define ext2_find_next_zero_bit		find_next_zero_le_bit
+#define __set_le_bit(nr, addr) \
+	__set_bit((nr) ^ 0x38, (addr))
+#define __clear_le_bit(nr, addr) \
+	__clear_bit((nr) ^ 0x38, (addr))
+#define __test_and_clear_le_bit(nr, addr) \
+	__test_and_clear_bit((nr) ^ 0x38, (addr))
+#define __test_and_set_le_bit(nr, addr) \
+	__test_and_set_bit((nr) ^ 0x38, (addr))
+
+#define ext2_set_bit(nr,addr)	\
+	__test_and_set_le_bit((nr),(unsigned long *)(addr))
+#define ext2_set_bit_atomic(lock,nr,addr) \
+	test_and_set_le_bit((nr),(unsigned long *)(addr))
+#define ext2_clear_bit(nr,addr)	\
+	__test_and_clear_le_bit((nr),(unsigned long *)(addr))
+#define ext2_clear_bit_atomic(lock,nr,addr) \
+	test_and_clear_le_bit((nr),(unsigned long *)(addr))
+#define ext2_test_bit(nr,addr)	\
+	test_le_bit((nr),(unsigned long *)(addr))
+#define ext2_find_first_zero_bit(addr, size) \
+	find_first_zero_le_bit((unsigned long *)(addr), (size))
+#define ext2_find_next_zero_bit(addr, size, off) \
+	find_next_zero_le_bit((unsigned long *)(addr), (size), (off))
 
 /* Bitmap functions for the minix filesystem.  */
-#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
-#define minix_set_bit(nr,addr) set_bit(nr,addr)
-#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
-#define minix_test_bit(nr,addr) test_bit(nr,addr)
-#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
+#define minix_test_and_set_bit(nr,addr)	\
+	test_and_set_bit((nr),(unsigned long *)(addr))
+#define minix_set_bit(nr,addr)	\
+	set_bit((nr),(unsigned long *)(addr))
+#define minix_test_and_clear_bit(nr,addr) \
+	test_and_clear_bit((nr),(unsigned long *)(addr))
+#define minix_test_bit(nr,addr)	\
+	test_bit((nr),(unsigned long *)(addr))
+#define minix_find_first_zero_bit(addr,size) \
+	find_first_zero_bit((unsigned long *)(addr),(size))
 
 #endif /* __KERNEL__ */
 
diff -urN linux-2.4.29-bk10/include/asm-sparc64/system.h linux-2.4.29-bk11/include/asm-sparc64/system.h
--- linux-2.4.29-bk10/include/asm-sparc64/system.h	2003-06-13 07:51:38.000000000 -0700
+++ linux-2.4.29-bk11/include/asm-sparc64/system.h	2005-02-10 02:50:27.581470059 -0800
@@ -246,6 +246,7 @@
 extern __inline__ unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
 {
 	__asm__ __volatile__(
+"	membar		#StoreLoad | #LoadLoad\n"
 "	mov		%0, %%g5\n"
 "1:	lduw		[%2], %%g7\n"
 "	cas		[%2], %%g7, %0\n"
@@ -262,6 +263,7 @@
 extern __inline__ unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
 {
 	__asm__ __volatile__(
+"	membar		#StoreLoad | #LoadLoad\n"
 "	mov		%0, %%g5\n"
 "1:	ldx		[%2], %%g7\n"
 "	casx		[%2], %%g7, %0\n"
@@ -306,7 +308,8 @@
 extern __inline__ unsigned long
 __cmpxchg_u32(volatile int *m, int old, int new)
 {
-	__asm__ __volatile__("cas [%2], %3, %0\n\t"
+	__asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
+			     "cas [%2], %3, %0\n\t"
 			     "membar #StoreLoad | #StoreStore"
 			     : "=&r" (new)
 			     : "0" (new), "r" (m), "r" (old)
@@ -318,7 +321,8 @@
 extern __inline__ unsigned long
 __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
 {
-	__asm__ __volatile__("casx [%2], %3, %0\n\t"
+	__asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
+			     "casx [%2], %3, %0\n\t"
 			     "membar #StoreLoad | #StoreStore"
 			     : "=&r" (new)
 			     : "0" (new), "r" (m), "r" (old)
diff -urN linux-2.4.29-bk10/include/linux/netlink.h linux-2.4.29-bk11/include/linux/netlink.h
--- linux-2.4.29-bk10/include/linux/netlink.h	2005-01-19 06:10:12.000000000 -0800
+++ linux-2.4.29-bk11/include/linux/netlink.h	2005-02-10 02:50:27.585470233 -0800
@@ -117,10 +117,9 @@
 
 /*
  *	skb should fit one page. This choice is good for headerless malloc.
- *
- *      FIXME: What is the best size for SLAB???? --ANK
  */
-#define NLMSG_GOODSIZE (PAGE_SIZE - ((sizeof(struct sk_buff)+0xF)&~0xF))
+#define NLMSG_GOODORDER 0
+#define NLMSG_GOODSIZE (SKB_MAX_ORDER(0, NLMSG_GOODORDER))
 
 
 struct netlink_callback
diff -urN linux-2.4.29-bk10/include/linux/skbuff.h linux-2.4.29-bk11/include/linux/skbuff.h
--- linux-2.4.29-bk10/include/linux/skbuff.h	2004-08-07 16:26:06.000000000 -0700
+++ linux-2.4.29-bk11/include/linux/skbuff.h	2005-02-10 02:50:27.587470320 -0800
@@ -290,15 +290,11 @@
  
 static inline void kfree_skb(struct sk_buff *skb)
 {
-	if (atomic_read(&skb->users) == 1 || atomic_dec_and_test(&skb->users))
-		__kfree_skb(skb);
-}
-
-/* Use this if you didn't touch the skb state [for fast switching] */
-static inline void kfree_skb_fast(struct sk_buff *skb)
-{
-	if (atomic_read(&skb->users) == 1 || atomic_dec_and_test(&skb->users))
-		kfree_skbmem(skb);	
+	if (likely(atomic_read(&skb->users) == 1))
+		smp_rmb();
+	else if (likely(!atomic_dec_and_test(&skb->users)))
+		return;
+	__kfree_skb(skb);
 }
 
 /**
diff -urN linux-2.4.29-bk10/include/net/dst.h linux-2.4.29-bk11/include/net/dst.h
--- linux-2.4.29-bk10/include/net/dst.h	2003-08-25 04:44:44.000000000 -0700
+++ linux-2.4.29-bk11/include/net/dst.h	2005-02-10 02:50:27.588470363 -0800
@@ -104,8 +104,10 @@
 static inline
 void dst_release(struct dst_entry * dst)
 {
-	if (dst)
+	if (dst) {
+		smp_mb__before_atomic_dec();
 		atomic_dec(&dst->__refcnt);
+	}
 }
 
 extern void * dst_alloc(struct dst_ops * ops);
diff -urN linux-2.4.29-bk10/net/core/dst.c linux-2.4.29-bk11/net/core/dst.c
--- linux-2.4.29-bk10/net/core/dst.c	2003-08-25 04:44:44.000000000 -0700
+++ linux-2.4.29-bk11/net/core/dst.c	2005-02-10 02:50:27.591470494 -0800
@@ -142,8 +142,13 @@
 
 void dst_destroy(struct dst_entry * dst)
 {
-	struct neighbour *neigh = dst->neighbour;
-	struct hh_cache *hh = dst->hh;
+	struct neighbour *neigh;
+	struct hh_cache *hh;
+
+	smp_rmb();
+
+	neigh = dst->neighbour;
+	hh = dst->hh;
 
 	dst->hh = NULL;
 	if (hh && atomic_dec_and_test(&hh->hh_refcnt))
diff -urN linux-2.4.29-bk10/net/core/wireless.c linux-2.4.29-bk11/net/core/wireless.c
--- linux-2.4.29-bk10/net/core/wireless.c	2003-11-28 10:26:21.000000000 -0800
+++ linux-2.4.29-bk11/net/core/wireless.c	2005-02-10 02:50:27.594470624 -0800
@@ -310,7 +310,7 @@
 
 /* ---------------------------------------------------------------- */
 /*
- * Number of private arguments
+ * Calculate size of private arguments
  */
 static inline int get_priv_size(__u16	args)
 {
@@ -320,6 +320,24 @@
 	return num * priv_type_size[type];
 }
 
+/* ---------------------------------------------------------------- */
+/*
+ * Re-calculate the size of private arguments
+ */
+static inline int adjust_priv_size(__u16		args,
+				   union iwreq_data *	wrqu)
+{
+	int	num = wrqu->data.length;
+	int	max = args & IW_PRIV_SIZE_MASK;
+	int	type = (args & IW_PRIV_TYPE_MASK) >> 12;
+
+	/* Make sure the driver doesn't goof up */
+	if (max < num)
+		num = max;
+
+	return num * priv_type_size[type];
+}
+
 
 /******************** /proc/net/wireless SUPPORT ********************/
 /*
@@ -701,7 +719,7 @@
 			   ((extra_size + offset) <= IFNAMSIZ))
 				extra_size = 0;
 		} else {
-			/* Size of set arguments */
+			/* Size of get arguments */
 			extra_size = get_priv_size(descr->get_args);
 
 			/* Does it fits in iwr ? */
@@ -771,6 +789,14 @@
 
 		/* If we have something to return to the user */
 		if (!ret && IW_IS_GET(cmd)) {
+
+			/* Adjust for the actual length if it's variable,
+			 * avoid leaking kernel bits outside. */
+			if (!(descr->get_args & IW_PRIV_SIZE_FIXED)) {
+				extra_size = adjust_priv_size(descr->get_args,
+							      &(iwr->u));
+			}
+
 			err = copy_to_user(iwr->u.data.pointer, extra,
 					   extra_size);
 			if (err)
diff -urN linux-2.4.29-bk10/net/ipv4/ipconfig.c linux-2.4.29-bk11/net/ipv4/ipconfig.c
--- linux-2.4.29-bk10/net/ipv4/ipconfig.c	2004-11-17 03:54:22.000000000 -0800
+++ linux-2.4.29-bk11/net/ipv4/ipconfig.c	2005-02-10 02:50:27.596470711 -0800
@@ -1162,7 +1162,7 @@
 		if (*cp == ':')
 			*cp++ = '\0';
 		addr = in_aton(name);
-		strcpy(name, cp);
+		memmove(name, cp, strlen(cp) + 1);
 	} else
 		addr = INADDR_NONE;
 
diff -urN linux-2.4.29-bk10/net/sched/sch_ingress.c linux-2.4.29-bk11/net/sched/sch_ingress.c
--- linux-2.4.29-bk10/net/sched/sch_ingress.c	2004-11-17 03:54:22.000000000 -0800
+++ linux-2.4.29-bk11/net/sched/sch_ingress.c	2005-02-10 02:50:27.602470971 -0800
@@ -14,6 +14,7 @@
 #include <linux/netdevice.h>
 #include <linux/rtnetlink.h>
 #include <linux/netfilter_ipv4.h>
+#include <linux/netfilter_ipv6.h>
 #include <linux/netfilter.h>
 #include <linux/smp.h>
 #include <net/pkt_sched.h>
@@ -241,6 +242,15 @@
 	NF_IP_PRI_FILTER + 1
 };
 
+static struct nf_hook_ops ing6_ops =
+{
+	{ NULL, NULL},
+	ing_hook,
+	PF_INET6,
+	NF_IP6_PRE_ROUTING,
+	NF_IP6_PRI_FILTER + 1
+};
+
 int ingress_init(struct Qdisc *sch,struct rtattr *opt)
 {
 	struct ingress_qdisc_data *p = PRIV(sch);
@@ -249,8 +259,13 @@
 		if (nf_register_hook(&ing_ops) < 0) {
 			printk("ingress qdisc registration error \n");
 			goto error;
-			}
+		}
 		nf_registered++;
+		if (nf_register_hook(&ing6_ops) < 0) {
+			printk("IPv6 ingress qdisc registration error, " \
+			    "disabling IPv6 support.\n");
+		} else
+			nf_registered++;
 	}
 
 	DPRINTK("ingress_init(sch %p,[qdisc %p],opt %p)\n",sch,p,opt);
@@ -374,8 +389,11 @@
 void cleanup_module(void) 
 {
 	unregister_qdisc(&ingress_qdisc_ops);
-	if (nf_registered)
+	if (nf_registered) {
 		nf_unregister_hook(&ing_ops);
+		if (nf_registered > 1)
+			nf_unregister_hook(&ing6_ops);
+	}
 }
 #endif
 MODULE_LICENSE("GPL");
diff -urN linux-2.4.29-bk10/net/sched/sch_netem.c linux-2.4.29-bk11/net/sched/sch_netem.c
--- linux-2.4.29-bk10/net/sched/sch_netem.c	2005-01-19 06:10:14.000000000 -0800
+++ linux-2.4.29-bk11/net/sched/sch_netem.c	2005-02-10 02:50:27.602470971 -0800
@@ -180,6 +180,7 @@
 	if (q->loss && q->loss >= get_crandom(&q->loss_cor)) {
 		pr_debug("netem_enqueue: random loss\n");
 		sch->stats.drops++;
+		kfree_skb(skb);
 		return 0;	/* lie about loss so TCP doesn't know */
 	}