## Automatically generated incremental diff ## From: linux-2.5.2-pre8 ## To: linux-2.5.2-pre9 ## Robot: $Id: make-incremental-diff,v 1.9 2001/12/10 00:06:56 hpa Exp $ diff -urN linux-2.5.2-pre8/Makefile linux/Makefile --- linux-2.5.2-pre8/Makefile Sat Jan 5 14:43:12 2002 +++ linux/Makefile Sat Jan 5 14:43:15 2002 @@ -1,7 +1,7 @@ VERSION = 2 PATCHLEVEL = 5 SUBLEVEL = 2 -EXTRAVERSION =-pre8 +EXTRAVERSION =-pre9 KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) diff -urN linux-2.5.2-pre8/arch/arm/Makefile linux/arch/arm/Makefile --- linux-2.5.2-pre8/arch/arm/Makefile Fri Nov 9 13:58:02 2001 +++ linux/arch/arm/Makefile Sat Jan 5 14:43:15 2002 @@ -9,7 +9,7 @@ LINKFLAGS :=-p -X -T arch/arm/vmlinux.lds GZFLAGS :=-9 -CFLAGS +=-fno-common -pipe +CFLAGS +=-pipe ifneq ($(CONFIG_NO_FRAME_POINTER),y) CFLAGS :=$(CFLAGS:-fomit-frame-pointer=) @@ -22,9 +22,7 @@ # Select CPU dependent flags. Note that order of declaration is important; # the options further down the list override previous items. # -# Note! For APCS-26 YOU MUST HAVE AN APCS-26 LIBGCC.A -# -apcs-y :=-mapcs-32 +apcs-$(CONFIG_CPU_32) :=-mapcs-32 apcs-$(CONFIG_CPU_26) :=-mapcs-26 -mcpu=arm3 -Os # This selects which instruction set is used. @@ -32,6 +30,7 @@ arch-$(CONFIG_CPU_32v3) :=-march=armv3 arch-$(CONFIG_CPU_32v4) :=-march=armv4 arch-$(CONFIG_CPU_32v5) :=-march=armv5 +arch-$(CONFIG_CPU_XSCALE) :=-march=armv4 -Wa,-mxscale #-march=armv5te # This selects how we optimise for the processor. tune-y := @@ -39,15 +38,19 @@ tune-$(CONFIG_CPU_ARM710) :=-mtune=arm710 tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi +tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110 tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100 +tune-$(CONFIG_CPU_XSCALE) :=-mtune=strongarm #-mtune=xscale +CFLAGS_BOOT :=$(apcs-y) $(arch-y) $(tune-y) -mshort-load-bytes -msoft-float CFLAGS +=$(apcs-y) $(arch-y) $(tune-y) -mshort-load-bytes -msoft-float AFLAGS +=$(apcs-y) $(arch-y) -mno-fpu -msoft-float ifeq ($(CONFIG_CPU_26),y) -PROCESSOR = armo +PROCESSOR := armo +HEAD := arch/arm/mach-arc/head.o arch/arm/kernel/init_task.o ifeq ($(CONFIG_ROM_KERNEL),y) DATAADDR = 0x02080000 TEXTADDR = 0x03800000 @@ -60,6 +63,7 @@ ifeq ($(CONFIG_CPU_32),y) PROCESSOR = armv +HEAD := arch/arm/kernel/head.o arch/arm/kernel/init_task.o TEXTADDR = 0xC0008000 LDSCRIPT = arch/arm/vmlinux-armv.lds.in endif @@ -134,51 +138,55 @@ MACHINE = anakin endif -export MACHINE PROCESSOR TEXTADDR GZFLAGS +ifeq ($(CONFIG_ARCH_IOP310),y) +MACHINE = iop310 +endif + +ifeq ($(CONFIG_ARCH_ADIFCC),y) +MACHINE = adifcc +endif + +export MACHINE PROCESSOR TEXTADDR GZFLAGS CFLAGS_BOOT # Only set INCDIR if its not already defined above # Grr, ?= doesn't work as all the other assignment operators do. Make bug? ifeq ($(origin INCDIR), undefined) -INCDIR := $(MACHINE) +INCDIR :=$(MACHINE) endif ifeq ($(origin DATAADDR), undefined) DATAADDR := . endif -# If we have a machine-specific directory, then include it in the build. -MACHDIR := arch/arm/mach-$(MACHINE) -ifeq ($(MACHDIR),$(wildcard $(MACHDIR))) -SUBDIRS += $(MACHDIR) -CORE_FILES := $(MACHDIR)/$(MACHINE).o $(CORE_FILES) +# Do we have FASTFPE? +FASTFPE :=arch/arm/fastfpe +ifeq ($(FASTFPE),$(wildcard $(FASTFPE))) +SUBDIRS +=$(FASTFPE) +FASTFPE_OBJ :=$(FASTFPE)/fast-math-emu.o endif -HEAD := arch/arm/kernel/head-$(PROCESSOR).o \ - arch/arm/kernel/init_task.o -SUBDIRS += arch/arm/kernel arch/arm/mm arch/arm/lib arch/arm/nwfpe -CORE_FILES := arch/arm/kernel/kernel.o arch/arm/mm/mm.o $(CORE_FILES) -LIBS := arch/arm/lib/lib.a $(LIBS) +# If we have a machine-specific directory, then include it in the build. +SUBDIRS +=arch/arm/mach-$(MACHINE) \ + arch/arm/kernel arch/arm/mm arch/arm/lib arch/arm/nwfpe +CORE_FILES :=arch/arm/mach-$(MACHINE)/$(MACHINE).o \ + arch/arm/kernel/kernel.o arch/arm/mm/mm.o $(CORE_FILES) +LIBS :=arch/arm/lib/lib.a $(LIBS) ifeq ($(CONFIG_FPE_NWFPE),y) -LIBS := arch/arm/nwfpe/math-emu.o $(LIBS) +LIBS :=arch/arm/nwfpe/math-emu.o $(LIBS) endif -# Only include fastfpe if it is part of the kernel tree. -FASTFPE := arch/arm/fastfpe -ifeq ($(FASTFPE),$(wildcard $(FASTFPE))) -SUBDIRS += $(FASTFPE) ifeq ($(CONFIG_FPE_FASTFPE),y) -LIBS := arch/arm/fastfpe/fast-math-emu.o $(LIBS) -endif +LIBS :=$(FASTFPE_OBJ) $(LIBS) endif ifeq ($(findstring y,$(CONFIG_ARCH_CLPS7500) $(CONFIG_ARCH_L7200)),y) -SUBDIRS += drivers/acorn/char -DRIVERS += drivers/acorn/char/acorn-char.o +SUBDIRS +=drivers/acorn/char +DRIVERS +=drivers/acorn/char/acorn-char.o endif -MAKEBOOT = $(MAKE) -C arch/$(ARCH)/boot -MAKETOOLS = $(MAKE) -C arch/$(ARCH)/tools +MAKEBOOT =$(MAKE) -C arch/$(ARCH)/boot +MAKETOOLS =$(MAKE) -C arch/$(ARCH)/tools # The following is a hack to get 'constants.h' up # to date before starting compilation @@ -254,7 +262,7 @@ @( \ CFG=$(@:_config=); \ if [ -f arch/arm/def-configs/$$CFG ]; then \ - [ -f .config ] && $(MV) .config .config.old; \ + [ -f .config ] && mv -f .config .config.old; \ cp arch/arm/def-configs/$$CFG .config; \ echo "*** Default configuration for $$CFG installed"; \ echo "*** Next, you may run 'make oldconfig'"; \ diff -urN linux-2.5.2-pre8/arch/arm/boot/Makefile linux/arch/arm/boot/Makefile --- linux-2.5.2-pre8/arch/arm/boot/Makefile Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/boot/Makefile Sat Jan 5 14:43:15 2002 @@ -118,6 +118,22 @@ ZTEXTADDR = 0x20008000 endif +ifeq ($(CONFIG_ARCH_IQ80310),y) +ZRELADDR = 0xa0008000 + +# for serial upload +ZTEXTADDR = 0xa1008000 + +# for direct flash execution +# ZTEXTADDR = 0x00060000 +# ZBSSADDR = 0xa1008000 +endif + +ifeq ($(CONFIG_ARCH_ADIFCC),y) +ZRELADDR = 0xc0008000 +ZTEXTADDR = 0xc1000000 +endif + # # If you don't define ZRELADDR above, # then it defaults to ZTEXTADDR diff -urN linux-2.5.2-pre8/arch/arm/boot/compressed/Makefile linux/arch/arm/boot/compressed/Makefile --- linux-2.5.2-pre8/arch/arm/boot/compressed/Makefile Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/boot/compressed/Makefile Sat Jan 5 14:43:15 2002 @@ -9,7 +9,7 @@ HEAD = head.o OBJS = misc.o -CFLAGS = $(CPPFLAGS) -O2 -DSTDC_HEADERS $(CFLAGS_PROC) -msoft-float +CFLAGS = $(CPPFLAGS) -O2 -DSTDC_HEADERS $(CFLAGS_BOOT) FONTC = $(TOPDIR)/drivers/video/font_acorn_8x8.c ZLDFLAGS = -p -X -T vmlinux.lds @@ -57,6 +57,10 @@ endif endif +ifeq ($(CONFIG_CPU_XSCALE),y) +OBJS += head-xscale.o +endif + SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/LOAD_ADDR/$(ZRELADDR)/; ifneq ($(ZBSSADDR),) @@ -84,12 +88,12 @@ font.o: $(FONTC) $(CC) $(CFLAGS) -Dstatic= -c -o $@ $(FONTC) -vmlinux.lds: vmlinux.lds.in +vmlinux.lds: vmlinux.lds.in Makefile $(TOPDIR)/arch/$(ARCH)/boot/Makefile $(TOPDIR)/.config @sed "$(SEDFLAGS)" < vmlinux.lds.in > $@ clean:; rm -f vmlinux core piggy* vmlinux.lds -.PHONY: vmlinux.lds clean +.PHONY: clean misc.o: misc.c $(TOPDIR)/include/asm/arch/uncompress.h $(TOPDIR)/lib/inflate.c diff -urN linux-2.5.2-pre8/arch/arm/boot/compressed/head-shark.S linux/arch/arm/boot/compressed/head-shark.S --- linux-2.5.2-pre8/arch/arm/boot/compressed/head-shark.S Thu Apr 12 12:03:50 2001 +++ linux/arch/arm/boot/compressed/head-shark.S Sat Jan 5 14:43:15 2002 @@ -1,5 +1,5 @@ /* The head-file for the Shark - * by Alexander Schulz + * by Alexander Schulz * * Does the following: * - get the memory layout from firmware. This can only be done as long as the mmu diff -urN linux-2.5.2-pre8/arch/arm/boot/compressed/head-xscale.S linux/arch/arm/boot/compressed/head-xscale.S --- linux-2.5.2-pre8/arch/arm/boot/compressed/head-xscale.S Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/boot/compressed/head-xscale.S Sat Jan 5 14:43:15 2002 @@ -0,0 +1,66 @@ +/* + * linux/arch/arm/boot/compressed/head-xscale.S + * + * XScale specific tweaks. This is merged into head.S by the linker. + * + */ + +#include +#include +#include + + .section ".start", #alloc, #execinstr + +__XScale_start: + + @ Preserve r8/r7 i.e. kernel entry values + + @ Data cache might be active. + @ Be sure to flush kernel binary out of the cache, + @ whatever state it is, before it is turned off. + @ This is done by fetching through currently executed + @ memory to be sure we hit the same cache. + bic r2, pc, #0x1f + add r3, r2, #0x10000 @ 64 kb is quite enough... +1: ldr r0, [r2], #32 + teq r2, r3 + bne 1b + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches + + @ disabling MMU and caches + mrc p15, 0, r0, c1, c0, 0 @ read control reg + bic r0, r0, #0x05 @ clear DC, MMU + bic r0, r0, #0x1000 @ clear Icache + mcr p15, 0, r0, c1, c0, 0 + +#ifdef CONFIG_ARCH_LUBBOCK + mov r7, #MACH_TYPE_LUBBOCK +#endif + +#ifdef CONFIG_ARCH_COTULLA_IDP + mov r7, #MACH_TYPE_COTULLA_IDP +#endif + +#ifdef CONFIG_ARCH_IQ80310 + /* + * Crank the CPU up to 733MHz + */ + mov r1, #9 + mcr p14, 0, r1, c6, c0, 0 + + /* + * Disable ECC error notification + * At some point, we should add an ECC handler to Linux + */ + mov r1, #0x1500 + mov r0, #0x4 + str r0, [r1, #0x34] + + mov r7, #MACH_TYPE_IQ80310 +#endif + +#ifdef CONFIG_ARCH_ADI_EVB + mov r7, #MACH_TYPE_ADI_EVB +#endif + diff -urN linux-2.5.2-pre8/arch/arm/boot/compressed/head.S linux/arch/arm/boot/compressed/head.S --- linux-2.5.2-pre8/arch/arm/boot/compressed/head.S Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/boot/compressed/head.S Sat Jan 5 14:43:15 2002 @@ -64,7 +64,7 @@ kphex r7, 8 /* architecture id */ kputc #':' mrc p15, 0, r0, c1, c0 - kphex r0, 8 /* control reg + kphex r0, 8 /* control reg */ kputc #'\n' kphex r5, 8 /* decompressed kernel start */ kputc #'-' @@ -218,7 +218,12 @@ ldr r1, proc_sa1110_type eor r1, r1, r6 movs r1, r1, lsr #4 - movne pc, lr + beq 1f + ldr r1, proc_xscale_type + eor r1, r1, r6 + movs r1, r1, lsr #16 +@ movne pc, lr + bne cache_off 1: sub r3, r4, #16384 @ Page directory size bic r3, r3, #0xff @ Align the pointer @@ -379,10 +384,14 @@ ldr r1, proc_sa1110_type eor r1, r1, r6 movs r1, r1, lsr #4 + beq 1f + ldr r1, proc_xscale_type + eor r1, r1, r6 + movs r1, r1, lsr #16 movne pc, lr 1: bic r1, pc, #31 - add r2, r1, #32768 + add r2, r1, #65536 @ 2x the largest dcache size 1: ldr r12, [r1], #32 @ s/w flush D cache teq r1, r2 bne 1b @@ -390,6 +399,12 @@ mcr p15, 0, r1, c7, c7, 0 @ flush I cache mcr p15, 0, r1, c7, c10, 4 @ drain WB mov pc, lr + + .type proc_xscale_type,#object +proc_xscale_type: + .word 0x69050000 + .size proc_xscale_type, . - proc_xscale_type + /* * Various debugging routines for printing hex characters and diff -urN linux-2.5.2-pre8/arch/arm/boot/compressed/ofw-shark.c linux/arch/arm/boot/compressed/ofw-shark.c --- linux-2.5.2-pre8/arch/arm/boot/compressed/ofw-shark.c Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/boot/compressed/ofw-shark.c Sat Jan 5 14:43:15 2002 @@ -1,7 +1,7 @@ /* * linux/arch/arm/boot/compressed/ofw-shark.c * - * by Alexander Schulz + * by Alexander Schulz * * This file is used to get some basic information * about the memory layout of the shark we are running diff -urN linux-2.5.2-pre8/arch/arm/config.in linux/arch/arm/config.in --- linux-2.5.2-pre8/arch/arm/config.in Fri Nov 9 13:58:02 2001 +++ linux/arch/arm/config.in Sat Jan 5 14:43:15 2002 @@ -33,7 +33,8 @@ comment 'System Type' choice 'ARM system type' \ - "Anakin CONFIG_ARCH_ANAKIN \ + "ADIFCC-based CONFIG_ARCH_ADIFCC \ + Anakin CONFIG_ARCH_ANAKIN \ Archimedes/A5000 CONFIG_ARCH_ARCA5K \ Cirrus-CL-PS7500FE CONFIG_ARCH_CLPS7500 \ CLPS711x/EP721x-based CONFIG_ARCH_CLPS711X \ @@ -42,6 +43,7 @@ Epxa10db CONFIG_ARCH_CAMELOT \ FootBridge CONFIG_ARCH_FOOTBRIDGE \ Integrator CONFIG_ARCH_INTEGRATOR \ + IOP310-based CONFIG_ARCH_IOP310 \ LinkUp-L7200 CONFIG_ARCH_L7200 \ RiscPC CONFIG_ARCH_RPC \ SA1100-based CONFIG_ARCH_SA1100 \ @@ -85,7 +87,14 @@ 32MB CONFIG_SA1100_CERF_FLASH_32MB" CerfFlash bool 'Cerf w/CPLD support (CerfPDA)' CONFIG_SA1100_CERF_CPLD fi -dep_bool ' Compaq iPAQ H3600' CONFIG_SA1100_H3600 $CONFIG_ARCH_SA1100 +dep_bool ' Compaq iPAQ H3100' CONFIG_SA1100_H3100 $CONFIG_ARCH_SA1100 +dep_bool ' Compaq iPAQ H3600/H3700' CONFIG_SA1100_H3600 $CONFIG_ARCH_SA1100 +dep_bool ' Compaq iPAQ H3800' CONFIG_SA1100_H3800 $CONFIG_ARCH_SA1100 +if [ "$CONFIG_SA1100_H3100" = "y" -o "$CONFIG_SA1100_H3600" = "y" -o "$CONFIG_SA1100_H3800" = "y" ]; then + define_bool CONFIG_SA1100_H3XXX y +else + define_bool CONFIG_SA1100_H3XXX n +fi #dep_bool ' Empeg' CONFIG_SA1100_EMPEG $CONFIG_ARCH_SA1100 dep_bool ' Extenex HandHeld Theater (Squashtail)' CONFIG_SA1100_EXTENEX1 $CONFIG_ARCH_SA1100 if [ "$CONFIG_SA1100_EXTENEX1" = "y" ]; then @@ -103,6 +112,8 @@ dep_bool ' OmniMeter' CONFIG_SA1100_OMNIMETER $CONFIG_ARCH_SA1100 dep_bool ' Pangolin' CONFIG_SA1100_PANGOLIN $CONFIG_ARCH_SA1100 dep_bool ' PLEB' CONFIG_SA1100_PLEB $CONFIG_ARCH_SA1100 +dep_bool ' PT System 3' CONFIG_SA1100_PT_SYSTEM3 $CONFIG_ARCH_SA1100 +dep_bool ' Shannon' CONFIG_SA1100_SHANNON $CONFIG_ARCH_SA1100 dep_bool ' Sherman' CONFIG_SA1100_SHERMAN $CONFIG_ARCH_SA1100 dep_bool ' Simpad' CONFIG_SA1100_SIMPAD $CONFIG_ARCH_SA1100 dep_bool ' Tulsa' CONFIG_SA1100_PFS168 $CONFIG_ARCH_SA1100 @@ -116,14 +127,22 @@ "$CONFIG_SA1100_PFS168" = "y" -o \ "$CONFIG_SA1100_XP860" = "y" -o \ "$CONFIG_SA1100_GRAPHICSMASTER" = "y" -o \ + "$CONFIG_SA1100_PT_SYSTEM3" = "y" -o \ "$CONFIG_SA1100_ADSBITSY" = "y" ]; then define_bool CONFIG_SA1111 y define_int CONFIG_FORCE_MAX_ZONEORDER 9 fi + +dep_tristate 'SA1100 USB function support' CONFIG_SA1100_USB $CONFIG_ARCH_SA1100 +dep_tristate ' Support for SA11x0 USB network link function' CONFIG_SA1100_USB_NETLINK $CONFIG_SA1100_USB +dep_tristate ' Support for SA11x0 USB character device emulation' CONFIG_SA1100_USB_CHAR $CONFIG_SA1100_USB + +dep_tristate 'Compaq iPAQ Handheld sleeve support' CONFIG_H3600_SLEEVE $CONFIG_SA1100_H3600 endmenu mainmenu_option next_comment comment 'CLPS711X/EP721X Implementations' +dep_bool ' AUTCPU12' CONFIG_ARCH_AUTCPU12 $CONFIG_ARCH_CLPS711X dep_bool ' CDB89712' CONFIG_ARCH_CDB89712 $CONFIG_ARCH_CLPS711X dep_bool ' CLEP7312' CONFIG_ARCH_CLEP7312 $CONFIG_ARCH_CLPS711X dep_bool ' EDB7211' CONFIG_ARCH_EDB7211 $CONFIG_ARCH_CLPS711X @@ -148,6 +167,19 @@ fi endmenu +if [ "$CONFIG_ARCH_IOP310" = "y" ]; then + mainmenu_option next_comment + comment 'IOP310 Implementation Options' + choice 'IOP310 System Type' \ + "IQ80310 CONFIG_ARCH_IQ80310" IQ80310 + comment 'IOP310 Chipset Features' + bool 'Support Intel 80312 Application Accelerator Unit (EXPERIMENTAL)' CONFIG_IOP310_AAU + bool 'Support Intel 80312 DMA (EXPERIMENTAL)' CONFIG_IOP310_DMA + bool 'Support Intel 80312 Messaging Unit (EXPERIMENTAL)' CONFIG_IOP310_MU + bool 'Support Intel 80312 Performance Monitor (EXPERIMENTAL)' CONFIG_IOP310_PMON + endmenu +fi + # Definitions to make life easier if [ "$CONFIG_ARCH_ARCA5K" = "y" -o \ "$CONFIG_ARCH_RPC" = "y" ]; then @@ -195,6 +227,8 @@ comment 'Processor Type' # Firstly, figure out what processor architecture version we should be using. +# This depends more on the machine type than anything else. + if [ "$CONFIG_ARCH_RPC" = "y" -o "$CONFIG_ARCH_CLPS7500" = "y" ]; then define_bool CONFIG_CPU_32v3 y else @@ -261,6 +295,21 @@ fi fi +# ARM922T +if [ "$CONFIG_ARCH_CAMELOT" = "y" ]; then + define_bool CONFIG_CPU_ARM922T y +else + define_bool CONFIG_CPU_ARM922T n +fi +if [ "$CONFIG_CPU_ARM922T" = "y" ]; then + bool ' ARM922T CPU idle' CONFIG_CPU_ARM922_CPU_IDLE + bool ' ARM922T I-Cache on' CONFIG_CPU_ARM922_I_CACHE_ON + bool ' ARM922T D-Cache on' CONFIG_CPU_ARM922_D_CACHE_ON + if [ "$CONFIG_CPU_ARM922_D_CACHE_ON" = "y" ] ; then + bool ' Force write through caches on ARM922T' CONFIG_CPU_ARM922_WRITETHROUGH + fi +fi + # ARM926T if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then bool 'Support ARM926T processor' CONFIG_CPU_ARM926T @@ -318,6 +367,22 @@ define_bool CONFIG_CPU_SA1100 n fi +# XScale +if [ "$CONFIG_ARCH_IOP310" = "y" -o "$CONFIG_ARCH_ADIFCC" = "y" ]; then + define_bool CONFIG_CPU_32v5 y + define_bool CONFIG_CPU_XSCALE y +fi + +#if [ "$CONFIG_CPU_XSCALE" = "y" ]; then +# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER +#fi + +if [ "$CONFIG_CPU_XSCALE" = "y" -a "$CONFIG_XSCALE_PMU_TIMER" != "y" ]; then + define_bool CONFIG_XSCALE_PMU y +else + define_bool CONFIG_XSCALE_PMU n +fi + if [ "$CONFIG_CPU_32" = "y" ]; then dep_bool 'Support Thumb instructions (experimental)' CONFIG_ARM_THUMB $CONFIG_EXPERIMENTAL fi @@ -338,7 +403,8 @@ # Now handle the bus types if [ "$CONFIG_ARCH_FTVPCI" = "y" -o \ "$CONFIG_ARCH_SHARK" = "y" -o \ - "$CONFIG_FOOTBRIDGE_HOST" = "y" ]; then + "$CONFIG_FOOTBRIDGE_HOST" = "y" -o \ + "$CONFIG_ARCH_IOP310" = "y" ]; then define_bool CONFIG_PCI y else if [ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then @@ -349,6 +415,20 @@ fi fi +# Select the host bridge type +if [ "$CONFIG_PCI" = "y" ]; then + if [ "$CONFIG_ARCH_FTVPCI" = "y" ]; then + define_bool CONFIG_PCI_HOST_PLX90X0 y + else + define_bool CONFIG_PCI_HOST_PLX90X0 n + fi + if [ "$CONFIG_ARCH_SHARK" = "y" ]; then + define_bool CONFIG_PCI_HOST_VIA82C505 y + else + define_bool CONFIG_PCI_HOST_VIA82C505 n + fi +fi + if [ "$CONFIG_FOOTBRIDGE_HOST" = "y" -o \ "$CONFIG_ARCH_SHARK" = "y" -o \ "$CONFIG_ARCH_CLPS7500" = "y" -o \ @@ -368,6 +448,13 @@ define_bool CONFIG_ISA_DMA n fi +if [ "$CONFIG_ARCH_ACORN" = "y" -o \ + "$CONFIG_ARCH_L7200" = "y" ]; then + define_bool CONFIG_FIQ y +else + define_bool CONFIG_FIQ n +fi + if [ "$CONFIG_ARCH_SA1100" = "y" -o \ "$CONFIG_ARCH_INTEGRATOR" = "y" ]; then dep_bool 'Support CPU clock change (EXPERIMENTAL)' CONFIG_CPU_FREQ $CONFIG_EXPERIMENTAL @@ -393,7 +480,8 @@ tristate 'Kernel support for a.out binaries' CONFIG_BINFMT_AOUT tristate 'Kernel support for ELF binaries' CONFIG_BINFMT_ELF tristate 'Kernel support for MISC binaries' CONFIG_BINFMT_MISC -dep_bool 'Power Management support (experimental)' CONFIG_PM $CONFIG_EXPERIMENTAL +bool 'Power Management support' CONFIG_PM +dep_tristate 'Advanced Power Management Emulation' CONFIG_APM $CONFIG_PM dep_tristate 'RISC OS personality' CONFIG_ARTHUR $CONFIG_CPU_32 if [ "$CONFIG_ARCH_EBSA110" = "y" -o \ @@ -404,7 +492,9 @@ "$CONFIG_ARCH_P720T" = "y" -o \ "$CONFIG_ARCH_CDB89712" = "y" -o \ "$CONFIG_ARCH_CAMELOT" = "y" -o \ - "$CONFIG_ARCH_ANAKIN" = "y" ]; then + "$CONFIG_ARCH_ANAKIN" = "y" -o \ + "$CONFIG_ARCH_IOP310" = "y" -o \ + "$CONFIG_ARCH_ADIFCC" = "y" ]; then string 'Default kernel command string' CONFIG_CMDLINE "" fi if [ "$CONFIG_ARCH_NETWINDER" = "y" -o \ @@ -434,8 +524,16 @@ define_bool CONFIG_LEDS_TIMER y fi fi -if [ "$CONFIG_CPU_32" = "y" -a "$CONFIG_ARCH_EBSA110" != "y" ]; then - bool 'Kernel-mode alignment trap handler' CONFIG_ALIGNMENT_TRAP + +if [ "$CONFIG_ARCH_SA1100" = "y" ]; then + define_bool CONFIG_ALIGNMENT_TRAP y +else + if [ "$CONFIG_CPU_32" = "y" -a \ + "$CONFIG_ARCH_EBSA110" != "y" ]; then + bool 'Mis-alignment trap handler' CONFIG_ALIGNMENT_TRAP + else + define_bool CONFIG_ALIGNMENT_TRAP n + fi fi endmenu @@ -594,15 +692,20 @@ # Always compile kernel with framepointer (until 2.4 real comes out) # Bug reports aren't much use without this. bool 'Compile kernel without frame pointer' CONFIG_NO_FRAME_POINTER -bool 'Verbose kernel error messages' CONFIG_DEBUG_ERRORS bool 'Verbose user fault messages' CONFIG_DEBUG_USER bool 'Include debugging information in kernel binary' CONFIG_DEBUG_INFO -bool 'Debug memory allocations' CONFIG_DEBUG_SLAB -bool 'Magic SysRq key' CONFIG_MAGIC_SYSRQ -bool 'Spinlock debugging' CONFIG_DEBUG_SPINLOCK dep_bool 'Disable pgtable cache' CONFIG_NO_PGT_CACHE $CONFIG_CPU_26 + +bool 'Kernel debugging' CONFIG_DEBUG_KERNEL +dep_bool ' Debug memory allocations' CONFIG_DEBUG_SLAB $CONFIG_DEBUG_KERNEL +dep_bool ' Magic SysRq key' CONFIG_MAGIC_SYSRQ $CONFIG_DEBUG_KERNEL +dep_bool ' Spinlock debugging' CONFIG_DEBUG_SPINLOCK $CONFIG_DEBUG_KERNEL +dep_bool ' Wait queue debugging' CONFIG_DEBUG_WAITQ $CONFIG_DEBUG_KERNEL +dep_bool ' Verbose BUG() reporting (adds 70K)' CONFIG_DEBUG_BUGVERBOSE $CONFIG_DEBUG_KERNEL +dep_bool ' Verbose kernel error messages' CONFIG_DEBUG_ERRORS $CONFIG_DEBUG_KERNEL # These options are only for real kernel hackers who want to get their hands dirty. -dep_bool 'Kernel low-level debugging functions' CONFIG_DEBUG_LL $CONFIG_EXPERIMENTAL -dep_bool ' Kernel low-level debugging messages via footbridge serial port' CONFIG_DEBUG_DC21285_PORT $CONFIG_DEBUG_LL $CONFIG_FOOTBRIDGE -dep_bool ' kernel low-level debugging messages via UART2' CONFIG_DEBUG_CLPS711X_UART2 $CONFIG_DEBUG_LL $CONFIG_ARCH_CLPS711X +dep_bool ' Kernel low-level debugging functions' CONFIG_DEBUG_LL $CONFIG_DEBUG_KERNEL +dep_bool ' Kernel low-level debugging messages via footbridge serial port' CONFIG_DEBUG_DC21285_PORT $CONFIG_DEBUG_LL $CONFIG_FOOTBRIDGE +dep_bool ' Kernel low-level debugging messages via UART2' CONFIG_DEBUG_CLPS711X_UART2 $CONFIG_DEBUG_LL $CONFIG_ARCH_CLPS711X +dep_bool ' Kernel low-level debugging messages via SA1100 Ser3 (otherwise Ser1)' CONFIG_DEBUG_LL_SER3 $CONFIG_DEBUG_LL $CONFIG_ARCH_SA1100 endmenu diff -urN linux-2.5.2-pre8/arch/arm/def-configs/adi_evb linux/arch/arm/def-configs/adi_evb --- linux-2.5.2-pre8/arch/arm/def-configs/adi_evb Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/def-configs/adi_evb Sat Jan 5 14:43:15 2002 @@ -0,0 +1,681 @@ +# +# Automatically generated by make menuconfig: don't edit +# +CONFIG_ARM=y +# CONFIG_EISA is not set +# CONFIG_SBUS is not set +# CONFIG_MCA is not set +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_GENERIC_BUST_SPINLOCK is not set +# CONFIG_GENERIC_ISA_DMA is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +# CONFIG_OBSOLETE is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODVERSIONS is not set +# CONFIG_KMOD is not set + +# +# System Type +# +CONFIG_ARCH_ADIFCC=y +# CONFIG_ARCH_ANAKIN is not set +# CONFIG_ARCH_ARCA5K is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_CAMELOT is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_IOP310 is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_SHARK is not set + +# +# Archimedes/A5000 Implementations +# +# CONFIG_ARCH_ARC is not set +# CONFIG_ARCH_A5K is not set + +# +# Footbridge Implementations +# +# CONFIG_ARCH_CATS is not set +# CONFIG_ARCH_PERSONAL_SERVER is not set +# CONFIG_ARCH_EBSA285_ADDIN is not set +# CONFIG_ARCH_EBSA285_HOST is not set +# CONFIG_ARCH_NETWINDER is not set + +# +# SA11x0 Implementations +# +# CONFIG_SA1100_ASSABET is not set +# CONFIG_ASSABET_NEPONSET is not set +# CONFIG_SA1100_ADSBITSY is not set +# CONFIG_SA1100_BRUTUS is not set +# CONFIG_SA1100_CERF is not set +# CONFIG_SA1100_H3600 is not set +# CONFIG_SA1100_EXTENEX1 is not set +# CONFIG_SA1100_FLEXANET is not set +# CONFIG_SA1100_FREEBIRD is not set +# CONFIG_SA1100_GRAPHICSCLIENT is not set +# CONFIG_SA1100_GRAPHICSMASTER is not set +# CONFIG_SA1100_JORNADA720 is not set +# CONFIG_SA1100_HUW_WEBPANEL is not set +# CONFIG_SA1100_ITSY is not set +# CONFIG_SA1100_LART is not set +# CONFIG_SA1100_NANOENGINE is not set +# CONFIG_SA1100_OMNIMETER is not set +# CONFIG_SA1100_PANGOLIN is not set +# CONFIG_SA1100_PLEB is not set +# CONFIG_SA1100_SHERMAN is not set +# CONFIG_SA1100_SIMPAD is not set +# CONFIG_SA1100_PFS168 is not set +# CONFIG_SA1100_VICTOR is not set +# CONFIG_SA1100_XP860 is not set +# CONFIG_SA1100_YOPY is not set +# CONFIG_SA1100_USB is not set +# CONFIG_SA1100_USB_NETLINK is not set +# CONFIG_SA1100_USB_CHAR is not set + +# +# CLPS711X/EP721X Implementations +# +# CONFIG_ARCH_CDB89712 is not set +# CONFIG_ARCH_CLEP7312 is not set +# CONFIG_ARCH_EDB7211 is not set +# CONFIG_ARCH_P720T is not set +# CONFIG_ARCH_EP7211 is not set +# CONFIG_ARCH_EP7212 is not set +CONFIG_ARCH_ADI_EVB=y +CONFIG_XSCALE_PMU_TIMER=y +# CONFIG_ARCH_ACORN is not set +# CONFIG_FOOTBRIDGE is not set +# CONFIG_FOOTBRIDGE_HOST is not set +# CONFIG_FOOTBRIDGE_ADDIN is not set +CONFIG_CPU_32=y +# CONFIG_CPU_26 is not set +# CONFIG_CPU_32v3 is not set +# CONFIG_CPU_32v4 is not set +# CONFIG_CPU_ARM610 is not set +# CONFIG_CPU_ARM710 is not set +# CONFIG_CPU_ARM720T is not set +# CONFIG_CPU_ARM920T is not set +# CONFIG_CPU_ARM926T is not set +# CONFIG_CPU_ARM1020 is not set +# CONFIG_CPU_SA110 is not set +# CONFIG_CPU_SA1100 is not set +CONFIG_CPU_32v4=y +CONFIG_CPU_XSCALE=y +CONFIG_ARM_THUMB=y +# CONFIG_XSCALE_TOOLS is not set +CONFIG_XSCALE_WRITE_ALLOC=y +CONFIG_XSCALE_PMU=y +CONFIG_ARM_THUMB=y +# CONFIG_DISCONTIGMEM is not set + +# +# General setup +# +# CONFIG_PCI is not set +# CONFIG_ISA is not set +# CONFIG_ISA_DMA is not set +# CONFIG_HOTPLUG is not set +# CONFIG_PCMCIA is not set +CONFIG_NET=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_FASTFPE is not set +CONFIG_KCORE_ELF=y +# CONFIG_KCORE_AOUT is not set +CONFIG_BINFMT_AOUT=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_PM is not set +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/mtdblock1" +CONFIG_ALIGNMENT_TRAP=y + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_BOOTLDR_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set +# CONFIG_MTD_AMDSTD is not set +# CONFIG_MTD_SHARP is not set +# CONFIG_MTD_JEDEC is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_NORA is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_CDB89712 is not set +# CONFIG_MTD_SA1100 is not set +# CONFIG_MTD_DC21285 is not set +# CONFIG_MTD_IQ80310 is not set +CONFIG_MTD_ADI_EVB=y +# CONFIG_MTD_PCI is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_DOC1000 is not set +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOCPROBE is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Plug and Play configuration +# +# CONFIG_PNP is not set +# CONFIG_ISAPNP is not set +# CONFIG_PNPBIOS is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_CISS_SCSI_TAPE is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4192 +CONFIG_BLK_DEV_INITRD=y + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set +# CONFIG_BLK_DEV_MD is not set +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID5 is not set +# CONFIG_MD_MULTIPATH is not set +# CONFIG_BLK_DEV_LVM is not set + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_NETLINK=y +CONFIG_RTNETLINK=y +# CONFIG_NETLINK_DEV is not set +# CONFIG_NETFILTER is not set +# CONFIG_FILTER is not set +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_IPV6 is not set +# CONFIG_KHTTPD is not set +# CONFIG_ATM is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_LLC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_ARM_AM79C961A is not set +# CONFIG_SUNLANCE is not set +# CONFIG_SUNBMAC is not set +# CONFIG_SUNQE is not set +# CONFIG_SUNLANCE is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_LANCE is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_NET_ISA is not set +# CONFIG_NET_PCI is not set +# CONFIG_NET_POCKET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_MYRI_SBUS is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_SK98LIN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PLIP is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set +# CONFIG_NET_FC is not set +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ATA/IDE/MFM/RLL support +# +# CONFIG_IDE is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# I2O device support +# +# CONFIG_I2O is not set +# CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_LAN is not set +# CONFIG_I2O_SCSI is not set +# CONFIG_I2O_PROC is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input core support +# +# CONFIG_INPUT is not set +# CONFIG_INPUT_KEYBDEV is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_SERIAL=y +CONFIG_SERIAL_CONSOLE=y +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_ANAKIN is not set +# CONFIG_SERIAL_ANAKIN_CONSOLE is not set +# CONFIG_SERIAL_AMBA is not set +# CONFIG_SERIAL_AMBA_CONSOLE is not set +# CONFIG_SERIAL_CLPS711X is not set +# CONFIG_SERIAL_CLPS711X_CONSOLE is not set +# CONFIG_SERIAL_21285 is not set +# CONFIG_SERIAL_21285_OLD is not set +# CONFIG_SERIAL_21285_CONSOLE is not set +# CONFIG_SERIAL_UART00 is not set +# CONFIG_SERIAL_UART00_CONSOLE is not set +# CONFIG_SERIAL_SA1100 is not set +# CONFIG_SERIAL_SA1100_CONSOLE is not set +# CONFIG_SERIAL_8250 is not set +# CONFIG_SERIAL_8250_CONSOLE is not set +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_MANY_PORTS is not set +# CONFIG_SERIAL_8250_SHARE_IRQ is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_MULTIPORT is not set +# CONFIG_SERIAL_8250_HUB6 is not set +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# L3 serial bus support +# +# CONFIG_L3 is not set +# CONFIG_L3_ALGOBIT is not set +# CONFIG_L3_BIT_SA1100_GPIO is not set +# CONFIG_L3_SA1111 is not set +# CONFIG_BIT_SA1100_GPIO is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +CONFIG_MOUSE=y +CONFIG_PSMOUSE=y +# CONFIG_82C710_MOUSE is not set +# CONFIG_PC110_PAD is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_QIC02_TAPE is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_INTEL_RNG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_CMS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_JBD_DEBUG is not set +# CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_CRAMFS is not set +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_FREEVXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +CONFIG_DEVPTS_FS=y +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +# CONFIG_ROMFS_FS is not set +CONFIG_EXT2_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_NFS_FS is not set +# CONFIG_NFS_V3 is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +# CONFIG_NFSD_V3 is not set +# CONFIG_SUNRPC is not set +# CONFIG_LOCKD is not set +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_ZISOFS_FS is not set +# CONFIG_ZLIB_FS_INFLATE is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +# CONFIG_MSDOS_PARTITION is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_SMB_NLS is not set +# CONFIG_NLS is not set + +# +# Multimedia Capabilities Port drivers +# +# CONFIG_MCP is not set +# CONFIG_MCP_SA1100 is not set +# CONFIG_MCP_UCB1200 is not set +# CONFIG_MCP_UCB1200_AUDIO is not set +# CONFIG_MCP_UCB1200_TS is not set + +# +# USB support +# +# CONFIG_USB is not set +# CONFIG_USB_UHCI is not set +# CONFIG_USB_UHCI_ALT is not set +# CONFIG_USB_OHCI is not set +# CONFIG_USB_OHCI_SA1111 is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_BLUETOOTH is not set +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_HP8200e is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_DC2XX is not set +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_SCANNER is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_HPUSBSCSI is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_CATC is not set +# CONFIG_USB_CDCETHER is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_USS720 is not set + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_ID75 is not set + +# +# Bluetooth support +# +# CONFIG_BLUEZ is not set + +# +# Kernel hacking +# +# CONFIG_NO_FRAME_POINTER is not set +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_USER=y +# CONFIG_DEBUG_INFO is not set +CONFIG_DEBUG_SLAB=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_NO_PGT_CACHE is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_DC21285_PORT is not set +# CONFIG_DEBUG_CLPS711X_UART2 is not set diff -urN linux-2.5.2-pre8/arch/arm/def-configs/flexanet linux/arch/arm/def-configs/flexanet --- linux-2.5.2-pre8/arch/arm/def-configs/flexanet Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/def-configs/flexanet Sat Jan 5 14:43:15 2002 @@ -8,6 +8,8 @@ CONFIG_UID16=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_GENERIC_BUST_SPINLOCK is not set +# CONFIG_GENERIC_ISA_DMA is not set # # Code maturity level options @@ -25,17 +27,19 @@ # # System Type # +# CONFIG_ARCH_ANAKIN is not set # CONFIG_ARCH_ARCA5K is not set # CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_CAMELOT is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_L7200 is not set # CONFIG_ARCH_RPC is not set CONFIG_ARCH_SA1100=y -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_ANAKIN is not set +# CONFIG_ARCH_SHARK is not set # # Archimedes/A5000 Implementations @@ -44,22 +48,32 @@ # # Archimedes/A5000 Implementations (select only ONE) # +# CONFIG_ARCH_ARC is not set +# CONFIG_ARCH_A5K is not set # # Footbridge Implementations # +# CONFIG_ARCH_CATS is not set +# CONFIG_ARCH_PERSONAL_SERVER is not set +# CONFIG_ARCH_EBSA285_ADDIN is not set +# CONFIG_ARCH_EBSA285_HOST is not set +# CONFIG_ARCH_NETWINDER is not set # # SA11x0 Implementations # # CONFIG_SA1100_ASSABET is not set +# CONFIG_ASSABET_NEPONSET is not set +# CONFIG_SA1100_ADSBITSY is not set # CONFIG_SA1100_BRUTUS is not set # CONFIG_SA1100_CERF is not set -# CONFIG_SA1100_BITSY is not set +# CONFIG_SA1100_H3600 is not set # CONFIG_SA1100_EXTENEX1 is not set CONFIG_SA1100_FLEXANET=y # CONFIG_SA1100_FREEBIRD is not set # CONFIG_SA1100_GRAPHICSCLIENT is not set +# CONFIG_SA1100_GRAPHICSMASTER is not set # CONFIG_SA1100_JORNADA720 is not set # CONFIG_SA1100_HUW_WEBPANEL is not set # CONFIG_SA1100_ITSY is not set @@ -68,7 +82,9 @@ # CONFIG_SA1100_OMNIMETER is not set # CONFIG_SA1100_PANGOLIN is not set # CONFIG_SA1100_PLEB is not set +# CONFIG_SA1100_SHANNON is not set # CONFIG_SA1100_SHERMAN is not set +# CONFIG_SA1100_SIMPAD is not set # CONFIG_SA1100_PFS168 is not set # CONFIG_SA1100_VICTOR is not set # CONFIG_SA1100_XP860 is not set @@ -76,11 +92,17 @@ CONFIG_SA1100_USB=y CONFIG_SA1100_USB_NETLINK=y # CONFIG_SA1100_USB_CHAR is not set -# CONFIG_SA1100_FREQUENCY_SCALE is not set # # CLPS711X/EP721X Implementations # +# CONFIG_ARCH_AUTCPU12 is not set +# CONFIG_ARCH_CDB89712 is not set +# CONFIG_ARCH_CLEP7312 is not set +# CONFIG_ARCH_EDB7211 is not set +# CONFIG_ARCH_P720T is not set +# CONFIG_ARCH_EP7211 is not set +# CONFIG_ARCH_EP7212 is not set # CONFIG_ARCH_ACORN is not set # CONFIG_FOOTBRIDGE is not set # CONFIG_FOOTBRIDGE_HOST is not set @@ -97,32 +119,40 @@ # CONFIG_CPU_ARM710 is not set # CONFIG_CPU_ARM720T is not set # CONFIG_CPU_ARM920T is not set +# CONFIG_CPU_ARM922T is not set +# CONFIG_CPU_ARM926T is not set # CONFIG_CPU_ARM1020 is not set # CONFIG_CPU_SA110 is not set CONFIG_CPU_SA1100=y +# CONFIG_ARM_THUMB is not set CONFIG_DISCONTIGMEM=y -# CONFIG_CPU_BIG_ENDIAN is not set # # General setup # # CONFIG_PCI is not set -# CONFIG_ISA is not set +CONFIG_ISA=y # CONFIG_ISA_DMA is not set -# CONFIG_CPU_CLOCK is not set +CONFIG_CPU_FREQ=y CONFIG_HOTPLUG=y # # PCMCIA/CardBus support # CONFIG_PCMCIA=y +# CONFIG_I82092 is not set # CONFIG_I82365 is not set # CONFIG_TCIC is not set +# CONFIG_PCMCIA_CLPS6700 is not set CONFIG_PCMCIA_SA1100=y CONFIG_NET=y CONFIG_SYSVIPC=y # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y + +# +# At least one math emulation must be selected +# CONFIG_FPE_NWFPE=y CONFIG_FPE_FASTFPE=y CONFIG_KCORE_ELF=y @@ -130,7 +160,7 @@ # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set -# CONFIG_PM is not set +CONFIG_PM=y # CONFIG_ARTHUR is not set CONFIG_CMDLINE="" CONFIG_LEDS=y @@ -149,7 +179,7 @@ CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_REDBOOT_PARTS=y # CONFIG_MTD_BOOTLDR_PARTS is not set # CONFIG_MTD_AFS_PARTS is not set @@ -165,43 +195,42 @@ # RAM/ROM/Flash chip drivers # CONFIG_MTD_CFI=y -# CONFIG_MTD_CFI_VIRTUAL_ER is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y CONFIG_MTD_CFI_ADV_OPTIONS=y CONFIG_MTD_CFI_NOSWAP=y # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_LART_BIT_SWAP is not set # CONFIG_MTD_CFI_GEOMETRY is not set CONFIG_MTD_CFI_INTELEXT=y # CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_AMDSTD is not set -# CONFIG_MTD_SHARP is not set # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set +# CONFIG_MTD_AMDSTD is not set +# CONFIG_MTD_SHARP is not set # CONFIG_MTD_JEDEC is not set # # Mapping drivers for chip access # # CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_SUN_UFLASH is not set # CONFIG_MTD_NORA is not set -# CONFIG_MTD_PNC2000 is not set -# CONFIG_MTD_RPXLITE is not set -# CONFIG_MTD_SC520CDP is not set -# CONFIG_MTD_NETSC520 is not set -# CONFIG_MTD_SBC_GXX is not set -# CONFIG_MTD_ELAN_104NC is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_CDB89712 is not set CONFIG_MTD_SA1100=y +# CONFIG_MTD_DC21285 is not set # CONFIG_MTD_IQ80310 is not set -# CONFIG_MTD_CFI_FLAGADM is not set -# CONFIG_MTD_ARMFLASH is not set +# CONFIG_MTD_PCI is not set # # Self-contained MTD device drivers # +# CONFIG_MTD_PMC551 is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set # # Disk-On-Chip Device Drivers @@ -220,11 +249,17 @@ # Plug and Play configuration # # CONFIG_PNP is not set +# CONFIG_ISAPNP is not set # # Block devices # # CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y @@ -235,6 +270,13 @@ # Multi-device support (RAID and LVM) # # CONFIG_MD is not set +# CONFIG_BLK_DEV_MD is not set +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID5 is not set +# CONFIG_MD_MULTIPATH is not set +# CONFIG_BLK_DEV_LVM is not set # # Networking options @@ -258,6 +300,7 @@ # CONFIG_IPV6 is not set # CONFIG_KHTTPD is not set # CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set # # @@ -293,42 +336,75 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_NET_SB1000 is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y +# CONFIG_ARM_AM79C961A is not set +# CONFIG_SUNLANCE is not set +# CONFIG_SUNBMAC is not set +# CONFIG_SUNQE is not set +# CONFIG_SUNLANCE is not set +# CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set +# CONFIG_LANCE is not set CONFIG_NET_VENDOR_SMC=y # CONFIG_WD80x3 is not set +# CONFIG_ULTRAMCA is not set # CONFIG_ULTRA is not set +# CONFIG_ULTRA32 is not set CONFIG_SMC9194=y # CONFIG_NET_VENDOR_RACAL is not set # CONFIG_AT1700 is not set # CONFIG_DEPCA is not set +# CONFIG_HP100 is not set +# CONFIG_NET_ISA is not set # CONFIG_NET_PCI is not set # CONFIG_NET_POCKET is not set # # Ethernet (1000 Mbit) # -# CONFIG_ACENIC_OMIT_TIGON_I is not set +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_MYRI_SBUS is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_SK98LIN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set +# CONFIG_PLIP is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # # Wireless LAN (non-hamradio) # -# CONFIG_NET_RADIO is not set +CONFIG_NET_RADIO=y +# CONFIG_STRIP is not set +# CONFIG_WAVELAN is not set +# CONFIG_ARLAN is not set +# CONFIG_AIRONET4500 is not set +# CONFIG_AIRONET4500_NONCS is not set +# CONFIG_AIRONET4500_PROC is not set +# CONFIG_AIRO is not set +CONFIG_HERMES=m + +# +# Wireless Pcmcia cards support +# +CONFIG_PCMCIA_HERMES=m +# CONFIG_AIRO_CS is not set +CONFIG_NET_WIRELESS=y # # Token Ring devices # # CONFIG_TR is not set # CONFIG_NET_FC is not set +# CONFIG_RCPCI is not set # CONFIG_SHAPER is not set # @@ -347,8 +423,10 @@ # CONFIG_PCMCIA_NMCLAN is not set # CONFIG_PCMCIA_SMC91C92 is not set # CONFIG_PCMCIA_XIRC2PS is not set +# CONFIG_PCMCIA_AXNET is not set +# CONFIG_ARCNET_COM20020_CS is not set +# CONFIG_PCMCIA_IBMTR is not set # CONFIG_NET_PCMCIA_RADIO is not set -CONFIG_PCMCIA_NETCARD=y # # Amateur Radio support @@ -378,20 +456,33 @@ CONFIG_BLK_DEV_IDEDISK=y # CONFIG_IDEDISK_MULTI_MODE is not set # CONFIG_BLK_DEV_IDEDISK_VENDOR is not set +# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set +# CONFIG_BLK_DEV_IDEDISK_IBM is not set +# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set +# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set +# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set +# CONFIG_BLK_DEV_IDEDISK_WD is not set # CONFIG_BLK_DEV_COMMERIAL is not set +# CONFIG_BLK_DEV_TIVO is not set CONFIG_BLK_DEV_IDECS=y # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set # CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set # # IDE chipset support/bugfixes # # CONFIG_BLK_DEV_CMD640 is not set +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set +# CONFIG_BLK_DEV_ISAPNP is not set # CONFIG_IDE_CHIPSETS is not set # CONFIG_IDEDMA_AUTO is not set # CONFIG_DMA_NONPCI is not set # CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_ATARAID is not set +# CONFIG_BLK_DEV_ATARAID_PDC is not set +# CONFIG_BLK_DEV_ATARAID_HPT is not set # # SCSI support @@ -402,6 +493,10 @@ # I2O device support # # CONFIG_I2O is not set +# CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_LAN is not set +# CONFIG_I2O_SCSI is not set +# CONFIG_I2O_PROC is not set # # ISDN subsystem @@ -412,6 +507,10 @@ # Input core support # # CONFIG_INPUT is not set +# CONFIG_INPUT_KEYBDEV is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set # # Character devices @@ -419,21 +518,38 @@ CONFIG_VT=y # CONFIG_VT_CONSOLE is not set # CONFIG_SERIAL is not set +# CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_ANAKIN is not set +# CONFIG_SERIAL_ANAKIN_CONSOLE is not set +# CONFIG_SERIAL_AMBA is not set +# CONFIG_SERIAL_AMBA_CONSOLE is not set +# CONFIG_SERIAL_CLPS711X is not set +# CONFIG_SERIAL_CLPS711X_CONSOLE is not set +# CONFIG_SERIAL_21285 is not set +# CONFIG_SERIAL_21285_OLD is not set +# CONFIG_SERIAL_21285_CONSOLE is not set +# CONFIG_SERIAL_UART00 is not set +# CONFIG_SERIAL_UART00_CONSOLE is not set CONFIG_SERIAL_SA1100=y -# CONFIG_SERIAL_SA1100_OLD is not set CONFIG_SERIAL_SA1100_CONSOLE=y CONFIG_SA1100_DEFAULT_BAUDRATE=57600 +# CONFIG_SERIAL_8250 is not set +# CONFIG_SERIAL_8250_CONSOLE is not set +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_MANY_PORTS is not set +# CONFIG_SERIAL_8250_SHARE_IRQ is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_MULTIPORT is not set +# CONFIG_SERIAL_8250_HUB6 is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=32 -CONFIG_UCB1200=y -CONFIG_TOUCHSCREEN_UCB1200=y -CONFIG_AUDIO_UCB1200=y -CONFIG_ADC_UCB1200=y -# CONFIG_TOUCHSCREEN_BITSY is not set -# CONFIG_PROFILER is not set # # I2C support @@ -441,37 +557,35 @@ # CONFIG_I2C is not set # -# Mice +# L3 serial bus support # -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set +# CONFIG_L3 is not set +# CONFIG_L3_ALGOBIT is not set +# CONFIG_L3_BIT_SA1100_GPIO is not set # -# Joysticks +# Other L3 adapters # +# CONFIG_L3_SA1111 is not set +# CONFIG_BIT_SA1100_GPIO is not set # -# Game port support -# - -# -# Gameport joysticks -# - -# -# Serial port support +# Mice # +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set # -# Serial port joysticks +# Joysticks # +# CONFIG_INPUT_GAMEPORT is not set # -# Parallel port joysticks +# Input core support is needed for gameports # # -# Parport support is needed for parallel port joysticks +# Input core support is needed for joysticks # # CONFIG_QIC02_TAPE is not set @@ -479,6 +593,7 @@ # Watchdog Cards # # CONFIG_WATCHDOG is not set +# CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set CONFIG_SA1100_RTC=y @@ -509,44 +624,74 @@ # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set # CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_BFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_JBD_DEBUG is not set # CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -CONFIG_CRAMFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_CRAMFS is not set # CONFIG_TMPFS is not set CONFIG_RAMFS=y # CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set # CONFIG_MINIX_FS is not set # CONFIG_VXFS_FS is not set # CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set # CONFIG_HPFS_FS is not set CONFIG_PROC_FS=y # CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set -CONFIG_ROMFS_FS=y +# CONFIG_QNX4FS_RW is not set +# CONFIG_ROMFS_FS is not set CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set # CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set # # Network File Systems # # CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set CONFIG_ROOT_NFS=y # CONFIG_NFSD is not set +# CONFIG_NFSD_V3 is not set CONFIG_SUNRPC=y CONFIG_LOCKD=y # CONFIG_SMB_FS is not set # CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_ZISOFS_FS is not set +# CONFIG_ZLIB_FS_INFLATE is not set # # Partition Types @@ -562,6 +707,7 @@ # CONFIG_MINIX_SUBPARTITION is not set # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set # CONFIG_SGI_PARTITION is not set # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set @@ -573,15 +719,17 @@ # CONFIG_PC_KEYMAP=y # CONFIG_VGA_CONSOLE is not set -CONFIG_FB=y # # Frame-buffer support # CONFIG_FB=y CONFIG_DUMMY_CONSOLE=y +# CONFIG_FB_ACORN is not set +# CONFIG_FB_ANAKIN is not set +# CONFIG_FB_CLPS711X is not set CONFIG_FB_SA1100=y -# CONFIG_FB_E1355 is not set +# CONFIG_FB_CYBER2000 is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FBCON_ADVANCED is not set CONFIG_FBCON_CFB2=y @@ -597,28 +745,49 @@ # Sound # CONFIG_SOUND=y -# CONFIG_SOUND_SA1100_SSP is not set +# CONFIG_SOUND_BT878 is not set +# CONFIG_SOUND_CMPCI is not set +# CONFIG_SOUND_EMU10K1 is not set +# CONFIG_MIDI_EMU10K1 is not set # CONFIG_SOUND_FUSION is not set # CONFIG_SOUND_CS4281 is not set +# CONFIG_SOUND_ES1370 is not set +# CONFIG_SOUND_ES1371 is not set # CONFIG_SOUND_ESSSOLO1 is not set # CONFIG_SOUND_MAESTRO is not set +# CONFIG_SOUND_MAESTRO3 is not set +# CONFIG_SOUND_ICH is not set +# CONFIG_SOUND_RME96XX is not set # CONFIG_SOUND_SONICVIBES is not set # CONFIG_SOUND_TRIDENT is not set # CONFIG_SOUND_MSNDCLAS is not set # CONFIG_SOUND_MSNDPIN is not set +# CONFIG_SOUND_VIA82CXXX is not set +# CONFIG_MIDI_VIA82CXXX is not set +# CONFIG_SOUND_SA1100 is not set +# CONFIG_SOUND_UDA1341 is not set +# CONFIG_SOUND_ASSABET_UDA1341 is not set +# CONFIG_SOUND_H3600_UDA1341 is not set +# CONFIG_SOUND_PANGOLIN_UDA1341 is not set +# CONFIG_SOUND_SA1111_UDA1341 is not set +# CONFIG_SOUND_SA1100SSP is not set # CONFIG_SOUND_OSS is not set +# CONFIG_SOUND_WAVEARTIST is not set +# CONFIG_SOUND_TVMIXER is not set # -# USB support +# Multimedia Capabilities Port drivers # -CONFIG_USB=y -CONFIG_USB_DEBUG=y +# CONFIG_MCP is not set +# CONFIG_MCP_SA1100 is not set +# CONFIG_MCP_UCB1200 is not set +# CONFIG_MCP_UCB1200_AUDIO is not set +# CONFIG_MCP_UCB1200_TS is not set # -# Miscellaneous USB options +# USB support # -# CONFIG_USB_DEVICEFS is not set -# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB is not set # # USB Controllers @@ -626,15 +795,22 @@ # CONFIG_USB_UHCI is not set # CONFIG_USB_UHCI_ALT is not set # CONFIG_USB_OHCI is not set +# CONFIG_USB_OHCI_SA1111 is not set # # USB Device Class drivers # # CONFIG_USB_AUDIO is not set # CONFIG_USB_BLUETOOTH is not set +# CONFIG_USB_STORAGE is not set # CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set # CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_HP8200e is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set @@ -652,40 +828,83 @@ # CONFIG_USB_DC2XX is not set # CONFIG_USB_MDC800 is not set # CONFIG_USB_SCANNER is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_HPUSBSCSI is not set # # USB Multimedia devices # -# CONFIG_USB_DABUSB is not set + +# +# Video4Linux support is needed for USB Multimedia device support +# # # USB Network adaptors # -# CONFIG_USB_PLUSB is not set # CONFIG_USB_PEGASUS is not set -# CONFIG_USB_NET1080 is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_CATC is not set +# CONFIG_USB_CDCETHER is not set # CONFIG_USB_USBNET is not set # # USB port drivers # +# CONFIG_USB_USS720 is not set # # USB Serial Converter support # # CONFIG_USB_SERIAL is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OMNINET is not set # -# USB misc drivers +# USB Miscellaneous drivers # # CONFIG_USB_RIO500 is not set # +# Bluetooth support +# +# CONFIG_BLUEZ is not set + +# # Kernel hacking # # CONFIG_NO_FRAME_POINTER is not set -CONFIG_DEBUG_ERRORS=y CONFIG_DEBUG_USER=y # CONFIG_DEBUG_INFO is not set -CONFIG_MAGIC_SYSRQ=y +# CONFIG_NO_PGT_CACHE is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_ERRORS is not set # CONFIG_DEBUG_LL is not set +# CONFIG_DEBUG_DC21285_PORT is not set +# CONFIG_DEBUG_CLPS711X_UART2 is not set diff -urN linux-2.5.2-pre8/arch/arm/def-configs/iq80310 linux/arch/arm/def-configs/iq80310 --- linux-2.5.2-pre8/arch/arm/def-configs/iq80310 Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/def-configs/iq80310 Sat Jan 5 14:43:15 2002 @@ -0,0 +1,812 @@ +# +# Automatically generated by make menuconfig: don't edit +# +CONFIG_ARM=y +# CONFIG_EISA is not set +# CONFIG_SBUS is not set +# CONFIG_MCA is not set +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_GENERIC_BUST_SPINLOCK is not set +# CONFIG_GENERIC_ISA_DMA is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +# CONFIG_OBSOLETE is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODVERSIONS is not set +CONFIG_KMOD=y + +# +# System Type +# +# CONFIG_ARCH_ADIFCC is not set +# CONFIG_ARCH_ANAKIN is not set +# CONFIG_ARCH_ARCA5K is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_CAMELOT is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_INTEGRATOR is not set +CONFIG_ARCH_IOP310=y +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_SHARK is not set + +# +# Archimedes/A5000 Implementations +# +# CONFIG_ARCH_ARC is not set +# CONFIG_ARCH_A5K is not set + +# +# Footbridge Implementations +# +# CONFIG_ARCH_CATS is not set +# CONFIG_ARCH_PERSONAL_SERVER is not set +# CONFIG_ARCH_EBSA285_ADDIN is not set +# CONFIG_ARCH_EBSA285_HOST is not set +# CONFIG_ARCH_NETWINDER is not set + +# +# SA11x0 Implementations +# +# CONFIG_SA1100_ASSABET is not set +# CONFIG_ASSABET_NEPONSET is not set +# CONFIG_SA1100_ADSBITSY is not set +# CONFIG_SA1100_BRUTUS is not set +# CONFIG_SA1100_CERF is not set +# CONFIG_SA1100_H3600 is not set +# CONFIG_SA1100_EXTENEX1 is not set +# CONFIG_SA1100_FLEXANET is not set +# CONFIG_SA1100_FREEBIRD is not set +# CONFIG_SA1100_GRAPHICSCLIENT is not set +# CONFIG_SA1100_GRAPHICSMASTER is not set +# CONFIG_SA1100_JORNADA720 is not set +# CONFIG_SA1100_HUW_WEBPANEL is not set +# CONFIG_SA1100_ITSY is not set +# CONFIG_SA1100_LART is not set +# CONFIG_SA1100_NANOENGINE is not set +# CONFIG_SA1100_OMNIMETER is not set +# CONFIG_SA1100_PANGOLIN is not set +# CONFIG_SA1100_PLEB is not set +# CONFIG_SA1100_SHANNON is not set +# CONFIG_SA1100_SHERMAN is not set +# CONFIG_SA1100_SIMPAD is not set +# CONFIG_SA1100_PFS168 is not set +# CONFIG_SA1100_VICTOR is not set +# CONFIG_SA1100_XP860 is not set +# CONFIG_SA1100_YOPY is not set +# CONFIG_SA1100_USB is not set +# CONFIG_SA1100_USB_NETLINK is not set +# CONFIG_SA1100_USB_CHAR is not set + +# +# CLPS711X/EP721X Implementations +# +# CONFIG_ARCH_AUTCPU12 is not set +# CONFIG_ARCH_CDB89712 is not set +# CONFIG_ARCH_CLEP7312 is not set +# CONFIG_ARCH_EDB7211 is not set +# CONFIG_ARCH_P720T is not set +# CONFIG_ARCH_EP7211 is not set +# CONFIG_ARCH_EP7212 is not set + +# +# IOP310 Implementation Options +# +CONFIG_ARCH_IQ80310=y +# CONFIG_IOP310_AAU is not set +# CONFIG_IOP310_DMA is not set +# CONFIG_IOP310_MU is not set +# CONFIG_IOP310_PMON is not set +# CONFIG_ARCH_ACORN is not set +# CONFIG_FOOTBRIDGE is not set +# CONFIG_FOOTBRIDGE_HOST is not set +# CONFIG_FOOTBRIDGE_ADDIN is not set +CONFIG_CPU_32=y +# CONFIG_CPU_26 is not set +# CONFIG_CPU_32v3 is not set +# CONFIG_CPU_32v4 is not set +# CONFIG_CPU_ARM610 is not set +# CONFIG_CPU_ARM710 is not set +# CONFIG_CPU_ARM720T is not set +# CONFIG_CPU_ARM920T is not set +# CONFIG_CPU_ARM922T is not set +# CONFIG_CPU_ARM926T is not set +# CONFIG_CPU_ARM1020 is not set +# CONFIG_CPU_SA110 is not set +# CONFIG_CPU_SA1100 is not set +CONFIG_CPU_32v4=y +CONFIG_CPU_XSCALE=y +CONFIG_ARM_THUMB=y +# CONFIG_XSCALE_TOOLS is not set +# CONFIG_XSCALE_CACHE_WRITE_ALLOC is not set +CONFIG_XSCALE_PMU=y +CONFIG_ARM_THUMB=y +# CONFIG_DISCONTIGMEM is not set + +# +# General setup +# +CONFIG_PCI=y +# CONFIG_ISA is not set +# CONFIG_ISA_DMA is not set +CONFIG_PCI_NAMES=y +# CONFIG_HOTPLUG is not set +# CONFIG_PCMCIA is not set +CONFIG_NET=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_FASTFPE is not set +CONFIG_KCORE_ELF=y +# CONFIG_KCORE_AOUT is not set +CONFIG_BINFMT_AOUT=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_PM is not set +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE="console=ttyS0,115200 ip=bootp" +CONFIG_ALIGNMENT_TRAP=y + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_REDBOOT_PARTS=y +# CONFIG_MTD_BOOTLDR_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set +# CONFIG_MTD_AMDSTD is not set +# CONFIG_MTD_SHARP is not set +# CONFIG_MTD_JEDEC is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_NORA is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_CDB89712 is not set +# CONFIG_MTD_SA1100 is not set +# CONFIG_MTD_DC21285 is not set +CONFIG_MTD_IQ80310=y +# CONFIG_MTD_EPXA10DB is not set +# CONFIG_MTD_PCI is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_DOC1000 is not set +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOCPROBE is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Plug and Play configuration +# +# CONFIG_PNP is not set +# CONFIG_ISAPNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_INITRD=y + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set +# CONFIG_BLK_DEV_MD is not set +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID5 is not set +# CONFIG_MD_MULTIPATH is not set +# CONFIG_BLK_DEV_LVM is not set + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_NETLINK=y +CONFIG_RTNETLINK=y +# CONFIG_NETLINK_DEV is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_FILTER is not set +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_COMPAT_IPCHAINS is not set +# CONFIG_IP_NF_COMPAT_IPFWADM is not set +# CONFIG_IPV6 is not set +# CONFIG_KHTTPD is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_LLC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_ARM_AM79C961A is not set +# CONFIG_SUNLANCE is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNBMAC is not set +# CONFIG_SUNQE is not set +# CONFIG_SUNLANCE is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_LANCE is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_HP100 is not set +# CONFIG_NET_ISA is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_APRICOT is not set +# CONFIG_CS89x0 is not set +# CONFIG_TULIP is not set +# CONFIG_DE4X5 is not set +# CONFIG_DGRS is not set +# CONFIG_DM9102 is not set +CONFIG_EEPRO100=y +# CONFIG_LNE390 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_NE3210 is not set +# CONFIG_ES3210 is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139TOO_8129 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_RHINE_MMIO is not set +# CONFIG_WINBOND_840 is not set +# CONFIG_NET_POCKET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_MYRI_SBUS is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_SK98LIN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PLIP is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set +# CONFIG_NET_FC is not set +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ATA/IDE/MFM/RLL support +# +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y +# CONFIG_BLK_DEV_HD_IDE is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set +# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set +# CONFIG_BLK_DEV_IDEDISK_IBM is not set +# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set +# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set +# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set +# CONFIG_BLK_DEV_IDEDISK_WD is not set +# CONFIG_BLK_DEV_COMMERIAL is not set +# CONFIG_BLK_DEV_TIVO is not set +# CONFIG_BLK_DEV_IDECS is not set +CONFIG_BLK_DEV_IDECD=y +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set +# CONFIG_BLK_DEV_CMD640 is not set +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set +# CONFIG_BLK_DEV_ISAPNP is not set +# CONFIG_BLK_DEV_RZ1000 is not set +CONFIG_BLK_DEV_IDEPCI=y +# CONFIG_IDEPCI_SHARE_IRQ is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +CONFIG_BLK_DEV_ADMA=y +# CONFIG_BLK_DEV_OFFBOARD is not set +CONFIG_IDEDMA_PCI_AUTO=y +CONFIG_BLK_DEV_IDEDMA=y +# CONFIG_IDEDMA_PCI_WIP is not set +# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_AEC62XX_TUNING is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_WDC_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_AMD74XX_OVERRIDE is not set +CONFIG_BLK_DEV_CMD64X=y +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT34X is not set +# CONFIG_HPT34X_AUTODMA is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_OPTI621 is not set +# CONFIG_BLK_DEV_PDC202XX is not set +# CONFIG_PDC202XX_BURST is not set +# CONFIG_PDC202XX_FORCE is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIS5513 is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_SL82C105 is not set +# CONFIG_IDE_CHIPSETS is not set +CONFIG_IDEDMA_AUTO=y +# CONFIG_IDEDMA_IVB is not set +# CONFIG_DMA_NONPCI is not set +CONFIG_BLK_DEV_IDE_MODES=y +# CONFIG_BLK_DEV_ATARAID is not set +# CONFIG_BLK_DEV_ATARAID_PDC is not set +# CONFIG_BLK_DEV_ATARAID_HPT is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set +# CONFIG_I2O_PCI is not set +# CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_LAN is not set +# CONFIG_I2O_SCSI is not set +# CONFIG_I2O_PROC is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input core support +# +# CONFIG_INPUT is not set +# CONFIG_INPUT_KEYBDEV is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_SERIAL=y +CONFIG_SERIAL_CONSOLE=y +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_ANAKIN is not set +# CONFIG_SERIAL_ANAKIN_CONSOLE is not set +# CONFIG_SERIAL_AMBA is not set +# CONFIG_SERIAL_AMBA_CONSOLE is not set +# CONFIG_SERIAL_CLPS711X is not set +# CONFIG_SERIAL_CLPS711X_CONSOLE is not set +# CONFIG_SERIAL_21285 is not set +# CONFIG_SERIAL_21285_OLD is not set +# CONFIG_SERIAL_21285_CONSOLE is not set +# CONFIG_SERIAL_UART00 is not set +# CONFIG_SERIAL_UART00_CONSOLE is not set +# CONFIG_SERIAL_SA1100 is not set +# CONFIG_SERIAL_SA1100_CONSOLE is not set +# CONFIG_SERIAL_8250 is not set +# CONFIG_SERIAL_8250_CONSOLE is not set +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_MANY_PORTS is not set +# CONFIG_SERIAL_8250_SHARE_IRQ is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_MULTIPORT is not set +# CONFIG_SERIAL_8250_HUB6 is not set +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# L3 serial bus support +# +# CONFIG_L3 is not set +# CONFIG_L3_ALGOBIT is not set +# CONFIG_L3_BIT_SA1100_GPIO is not set +# CONFIG_L3_SA1111 is not set +# CONFIG_BIT_SA1100_GPIO is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +CONFIG_MOUSE=y +CONFIG_PSMOUSE=y +# CONFIG_82C710_MOUSE is not set +# CONFIG_PC110_PAD is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_QIC02_TAPE is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_INTEL_RNG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_JBD_DEBUG is not set +# CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_CRAMFS is not set +CONFIG_TMPFS=y +# CONFIG_RAMFS is not set +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +CONFIG_DEVPTS_FS=y +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +# CONFIG_ROMFS_FS is not set +CONFIG_EXT2_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +# CONFIG_NFSD_V3 is not set +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_ZISOFS_FS is not set +# CONFIG_ZLIB_FS_INFLATE is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_SMB_NLS is not set +# CONFIG_NLS is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# Multimedia Capabilities Port drivers +# +# CONFIG_MCP is not set +# CONFIG_MCP_SA1100 is not set +# CONFIG_MCP_UCB1200 is not set +# CONFIG_MCP_UCB1200_AUDIO is not set +# CONFIG_MCP_UCB1200_TS is not set + +# +# USB support +# +# CONFIG_USB is not set +# CONFIG_USB_UHCI is not set +# CONFIG_USB_UHCI_ALT is not set +# CONFIG_USB_OHCI is not set +# CONFIG_USB_OHCI_SA1111 is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_BLUETOOTH is not set +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_HP8200e is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_DC2XX is not set +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_SCANNER is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_HPUSBSCSI is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_CATC is not set +# CONFIG_USB_CDCETHER is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_USS720 is not set + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_RIO500 is not set + +# +# Bluetooth support +# +# CONFIG_BLUEZ is not set + +# +# Kernel hacking +# +# CONFIG_NO_FRAME_POINTER is not set +CONFIG_DEBUG_USER=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_NO_PGT_CACHE is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SLAB is not set +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_WAITQ is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_DC21285_PORT is not set +# CONFIG_DEBUG_CLPS711X_UART2 is not set diff -urN linux-2.5.2-pre8/arch/arm/def-configs/shannon linux/arch/arm/def-configs/shannon --- linux-2.5.2-pre8/arch/arm/def-configs/shannon Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/def-configs/shannon Sat Jan 5 14:43:15 2002 @@ -0,0 +1,737 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_ARM=y +# CONFIG_EISA is not set +# CONFIG_SBUS is not set +# CONFIG_MCA is not set +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_GENERIC_BUST_SPINLOCK is not set +# CONFIG_GENERIC_ISA_DMA is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_OBSOLETE=y + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODVERSIONS is not set +# CONFIG_KMOD is not set + +# +# System Type +# +# CONFIG_ARCH_ANAKIN is not set +# CONFIG_ARCH_ARCA5K is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_CAMELOT is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_RPC is not set +CONFIG_ARCH_SA1100=y +# CONFIG_ARCH_SHARK is not set + +# +# Archimedes/A5000 Implementations +# + +# +# Archimedes/A5000 Implementations (select only ONE) +# + +# +# Footbridge Implementations +# + +# +# SA11x0 Implementations +# +# CONFIG_SA1100_ASSABET is not set +# CONFIG_SA1100_ADSBITSY is not set +# CONFIG_SA1100_BRUTUS is not set +# CONFIG_SA1100_CERF is not set +# CONFIG_SA1100_H3600 is not set +# CONFIG_SA1100_EXTENEX1 is not set +# CONFIG_SA1100_FLEXANET is not set +# CONFIG_SA1100_FREEBIRD is not set +# CONFIG_SA1100_GRAPHICSCLIENT is not set +# CONFIG_SA1100_GRAPHICSMASTER is not set +# CONFIG_SA1100_JORNADA720 is not set +# CONFIG_SA1100_HUW_WEBPANEL is not set +# CONFIG_SA1100_ITSY is not set +# CONFIG_SA1100_LART is not set +# CONFIG_SA1100_NANOENGINE is not set +# CONFIG_SA1100_OMNIMETER is not set +# CONFIG_SA1100_PANGOLIN is not set +# CONFIG_SA1100_PLEB is not set +CONFIG_SA1100_SHANNON=y +# CONFIG_SA1100_SHERMAN is not set +# CONFIG_SA1100_SIMPAD is not set +# CONFIG_SA1100_PFS168 is not set +# CONFIG_SA1100_VICTOR is not set +# CONFIG_SA1100_XP860 is not set +# CONFIG_SA1100_YOPY is not set +# CONFIG_SA1100_USB is not set + +# +# CLPS711X/EP721X Implementations +# +# CONFIG_ARCH_EP7211 is not set +# CONFIG_ARCH_EP7212 is not set +# CONFIG_ARCH_ACORN is not set +# CONFIG_FOOTBRIDGE is not set +# CONFIG_FOOTBRIDGE_HOST is not set +# CONFIG_FOOTBRIDGE_ADDIN is not set +CONFIG_CPU_32=y +# CONFIG_CPU_26 is not set + +# +# Processor Type +# +# CONFIG_CPU_32v3 is not set +CONFIG_CPU_32v4=y +# CONFIG_CPU_ARM610 is not set +# CONFIG_CPU_ARM710 is not set +# CONFIG_CPU_ARM720T is not set +# CONFIG_CPU_ARM920T is not set +# CONFIG_CPU_ARM922T is not set +# CONFIG_CPU_ARM926T is not set +# CONFIG_CPU_ARM1020 is not set +# CONFIG_CPU_SA110 is not set +CONFIG_CPU_SA1100=y +# CONFIG_ARM_THUMB is not set +CONFIG_DISCONTIGMEM=y + +# +# General setup +# +# CONFIG_PCI is not set +CONFIG_ISA=y +# CONFIG_ISA_DMA is not set +# CONFIG_CPU_FREQ is not set +CONFIG_HOTPLUG=y + +# +# PCMCIA/CardBus support +# +CONFIG_PCMCIA=y +# CONFIG_I82092 is not set +# CONFIG_I82365 is not set +# CONFIG_TCIC is not set +CONFIG_PCMCIA_SA1100=y +CONFIG_NET=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y + +# +# At least one math emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_FASTFPE is not set +CONFIG_KCORE_ELF=y +# CONFIG_KCORE_AOUT is not set +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_PM is not set +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE="console=ttySA0,9600 console=tty1 root=/dev/mtdblock2 init=/linuxrc" +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_BOOTLDR_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_NORA is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +CONFIG_MTD_SA1100=y +# CONFIG_MTD_IQ80310 is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC1000 is not set +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOCPROBE is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Plug and Play configuration +# +# CONFIG_PNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_INITRD=y + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +# CONFIG_NETLINK is not set +# CONFIG_NETFILTER is not set +# CONFIG_FILTER is not set +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_IPV6 is not set +# CONFIG_KHTTPD is not set +# CONFIG_ATM is not set + +# +# +# +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_LLC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_LANCE is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_AT1700 is not set +# CONFIG_DEPCA is not set +# CONFIG_HP100 is not set +# CONFIG_NET_ISA is not set +# CONFIG_NET_PCI is not set +# CONFIG_NET_POCKET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC_OMIT_TIGON_I is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# PCMCIA network device support +# +CONFIG_NET_PCMCIA=y +# CONFIG_PCMCIA_3C589 is not set +# CONFIG_PCMCIA_3C574 is not set +# CONFIG_PCMCIA_FMVJ18X is not set +CONFIG_PCMCIA_PCNET=y +# CONFIG_PCMCIA_NMCLAN is not set +CONFIG_PCMCIA_SMC91C92=y +# CONFIG_PCMCIA_XIRC2PS is not set +# CONFIG_NET_PCMCIA_RADIO is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ATA/IDE/MFM/RLL support +# +CONFIG_IDE=m + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=m + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD_IDE is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_IDEDISK is not set +# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set +# CONFIG_BLK_DEV_IDECS is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set + +# +# IDE chipset support/bugfixes +# +# CONFIG_BLK_DEV_CMD640 is not set +# CONFIG_IDE_CHIPSETS is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_DMA_NONPCI is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_ATARAID is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input core support +# +CONFIG_INPUT=y +CONFIG_INPUT_KEYBDEV=y +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +# CONFIG_SERIAL is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_SA1100=y +CONFIG_SERIAL_SA1100_CONSOLE=y +CONFIG_SA1100_DEFAULT_BAUDRATE=9600 +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# L3 serial bus support +# +# CONFIG_L3 is not set + +# +# Other L3 adapters +# +# CONFIG_BIT_SA1100_GPIO is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_INPUT_SERIO is not set + +# +# Joysticks +# +# CONFIG_QIC02_TAPE is not set + +# +# Watchdog Cards +# +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_WDT is not set +# CONFIG_WDTPCI is not set +# CONFIG_PCWATCHDOG is not set +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_ADVANTECH_WDT is not set +CONFIG_SA1100_WATCHDOG=y +# CONFIG_EUROTECH_WDT is not set +# CONFIG_IB700_WDT is not set +# CONFIG_I810_TCO is not set +# CONFIG_MIXCOMWD is not set +# CONFIG_60XX_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_MACHZ_WDT is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +CONFIG_SA1100_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# PCMCIA character devices +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_CMS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +# CONFIG_UMSDOS_FS is not set +CONFIG_VFAT_FS=y +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_CRAMFS is not set +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +CONFIG_MINIX_FS=y +# CONFIG_FREEVXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_EXT2_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFSD is not set +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_ZISOFS_FS is not set +# CONFIG_ZLIB_FS_INFLATE is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_SMB_NLS is not set +CONFIG_NLS=y + +# +# Native Language Support +# +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Console drivers +# +CONFIG_PC_KEYMAP=y +# CONFIG_VGA_CONSOLE is not set + +# +# Frame-buffer support +# +CONFIG_FB=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_FB_SA1100=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FBCON_ADVANCED is not set +CONFIG_FBCON_CFB2=y +CONFIG_FBCON_CFB4=y +CONFIG_FBCON_CFB8=y +CONFIG_FBCON_CFB16=y +# CONFIG_FBCON_FONTWIDTH8_ONLY is not set +# CONFIG_FBCON_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y + +# +# Sound +# +CONFIG_SOUND=y +# CONFIG_SOUND_BT878 is not set +# CONFIG_SOUND_FUSION is not set +# CONFIG_SOUND_CS4281 is not set +# CONFIG_SOUND_ESSSOLO1 is not set +# CONFIG_SOUND_MAESTRO is not set +# CONFIG_SOUND_SONICVIBES is not set +# CONFIG_SOUND_TRIDENT is not set +# CONFIG_SOUND_MSNDCLAS is not set +# CONFIG_SOUND_MSNDPIN is not set +CONFIG_SOUND_SA1100=y +# CONFIG_SOUND_SA1100SSP is not set +# CONFIG_SOUND_OSS is not set + +# +# Multimedia Capabilities Port drivers +# +CONFIG_MCP=y +CONFIG_MCP_SA1100=y +CONFIG_MCP_UCB1200=y +CONFIG_MCP_UCB1200_AUDIO=y +CONFIG_MCP_UCB1200_TS=y + +# +# USB support +# +# CONFIG_USB is not set + +# +# USB Controllers +# + +# +# USB Device Class drivers +# + +# +# USB Human Interface Devices (HID) +# + +# +# USB Imaging devices +# + +# +# USB Multimedia devices +# + +# +# Video4Linux support is needed for USB Multimedia device support +# + +# +# USB Network adaptors +# + +# +# USB port drivers +# + +# +# USB Serial Converter support +# + +# +# USB Miscellaneous drivers +# + +# +# Bluetooth support +# +# CONFIG_BLUEZ is not set + +# +# Kernel hacking +# +# CONFIG_NO_FRAME_POINTER is not set +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_USER=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_SLAB is not set +CONFIG_MAGIC_SYSRQ=y +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_LL=y diff -urN linux-2.5.2-pre8/arch/arm/def-configs/system3 linux/arch/arm/def-configs/system3 --- linux-2.5.2-pre8/arch/arm/def-configs/system3 Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/def-configs/system3 Sat Jan 5 14:43:15 2002 @@ -0,0 +1,977 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_ARM=y +# CONFIG_EISA is not set +# CONFIG_SBUS is not set +# CONFIG_MCA is not set +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_GENERIC_BUST_SPINLOCK is not set +# CONFIG_GENERIC_ISA_DMA is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +# CONFIG_OBSOLETE is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODVERSIONS is not set +# CONFIG_KMOD is not set + +# +# System Type +# +# CONFIG_ARCH_ANAKIN is not set +# CONFIG_ARCH_ARCA5K is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_CAMELOT is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_RPC is not set +CONFIG_ARCH_SA1100=y +# CONFIG_ARCH_SHARK is not set + +# +# Archimedes/A5000 Implementations +# + +# +# Archimedes/A5000 Implementations (select only ONE) +# +# CONFIG_ARCH_ARC is not set +# CONFIG_ARCH_A5K is not set + +# +# Footbridge Implementations +# +# CONFIG_ARCH_CATS is not set +# CONFIG_ARCH_PERSONAL_SERVER is not set +# CONFIG_ARCH_EBSA285_ADDIN is not set +# CONFIG_ARCH_EBSA285_HOST is not set +# CONFIG_ARCH_NETWINDER is not set + +# +# SA11x0 Implementations +# +# CONFIG_SA1100_ASSABET is not set +# CONFIG_ASSABET_NEPONSET is not set +# CONFIG_SA1100_ADSBITSY is not set +# CONFIG_SA1100_BRUTUS is not set +# CONFIG_SA1100_CERF is not set +# CONFIG_SA1100_H3600 is not set +# CONFIG_SA1100_EXTENEX1 is not set +# CONFIG_SA1100_FLEXANET is not set +# CONFIG_SA1100_FREEBIRD is not set +# CONFIG_SA1100_GRAPHICSCLIENT is not set +# CONFIG_SA1100_GRAPHICSMASTER is not set +# CONFIG_SA1100_JORNADA720 is not set +# CONFIG_SA1100_HUW_WEBPANEL is not set +# CONFIG_SA1100_ITSY is not set +# CONFIG_SA1100_LART is not set +# CONFIG_SA1100_NANOENGINE is not set +# CONFIG_SA1100_OMNIMETER is not set +# CONFIG_SA1100_PANGOLIN is not set +# CONFIG_SA1100_PLEB is not set +# CONFIG_SA1100_SHANNON is not set +# CONFIG_SA1100_SHERMAN is not set +# CONFIG_SA1100_SIMPAD is not set +# CONFIG_SA1100_PFS168 is not set +# CONFIG_SA1100_VICTOR is not set +# CONFIG_SA1100_XP860 is not set +# CONFIG_SA1100_YOPY is not set +CONFIG_SA1100_PT_SYSTEM3=y +CONFIG_SA1111=y +CONFIG_FORCE_MAX_ZONEORDER=9 +CONFIG_SA1100_USB=m +CONFIG_SA1100_USB_NETLINK=m +CONFIG_SA1100_USB_CHAR=m + +# +# CLPS711X/EP721X Implementations +# +# CONFIG_ARCH_AUTCPU12 is not set +# CONFIG_ARCH_CDB89712 is not set +# CONFIG_ARCH_CLEP7312 is not set +# CONFIG_ARCH_EDB7211 is not set +# CONFIG_ARCH_P720T is not set +# CONFIG_ARCH_EP7211 is not set +# CONFIG_ARCH_EP7212 is not set +# CONFIG_ARCH_ACORN is not set +# CONFIG_FOOTBRIDGE is not set +# CONFIG_FOOTBRIDGE_HOST is not set +# CONFIG_FOOTBRIDGE_ADDIN is not set +CONFIG_CPU_32=y +# CONFIG_CPU_26 is not set + +# +# Processor Type +# +# CONFIG_CPU_32v3 is not set +CONFIG_CPU_32v4=y +# CONFIG_CPU_ARM610 is not set +# CONFIG_CPU_ARM710 is not set +# CONFIG_CPU_ARM720T is not set +# CONFIG_CPU_ARM920T is not set +# CONFIG_CPU_ARM922T is not set +# CONFIG_CPU_ARM926T is not set +# CONFIG_CPU_ARM1020 is not set +# CONFIG_CPU_SA110 is not set +CONFIG_CPU_SA1100=y +# CONFIG_ARM_THUMB is not set +CONFIG_DISCONTIGMEM=y + +# +# General setup +# +# CONFIG_PCI is not set +CONFIG_ISA=y +# CONFIG_ISA_DMA is not set +CONFIG_CPU_FREQ=y +CONFIG_HOTPLUG=y + +# +# PCMCIA/CardBus support +# +CONFIG_PCMCIA=m +# CONFIG_I82092 is not set +# CONFIG_I82365 is not set +# CONFIG_TCIC is not set +# CONFIG_PCMCIA_CLPS6700 is not set +CONFIG_PCMCIA_SA1100=m +CONFIG_NET=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y + +# +# At least one math emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_FASTFPE is not set +CONFIG_KCORE_ELF=y +# CONFIG_KCORE_AOUT is not set +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_PM=y +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE="noinitrd root=/dev/mtdblock3" +CONFIG_LEDS=y +CONFIG_LEDS_TIMER=y +CONFIG_LEDS_CPU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_REDBOOT_PARTS=m +CONFIG_MTD_BOOTLDR_PARTS=m +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set +# CONFIG_MTD_AMDSTD is not set +# CONFIG_MTD_SHARP is not set +# CONFIG_MTD_JEDEC is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_NORA is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_CDB89712 is not set +CONFIG_MTD_SA1100=y +# CONFIG_MTD_DC21285 is not set +# CONFIG_MTD_IQ80310 is not set +# CONFIG_MTD_PCI is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC1000 is not set +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOCPROBE is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Plug and Play configuration +# +# CONFIG_PNP is not set +# CONFIG_ISAPNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_INITRD=y + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set +# CONFIG_BLK_DEV_MD is not set +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID5 is not set +# CONFIG_MD_MULTIPATH is not set +# CONFIG_BLK_DEV_LVM is not set + +# +# Networking options +# +# CONFIG_PACKET is not set +# CONFIG_NETLINK is not set +# CONFIG_NETFILTER is not set +# CONFIG_FILTER is not set +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_IPV6 is not set +# CONFIG_KHTTPD is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set + +# +# +# +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_LLC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +CONFIG_DUMMY=m +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_ARM_AM79C961A is not set +# CONFIG_SUNLANCE is not set +# CONFIG_SUNBMAC is not set +# CONFIG_SUNQE is not set +# CONFIG_SUNLANCE is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_LANCE is not set +CONFIG_NET_VENDOR_SMC=y +# CONFIG_WD80x3 is not set +# CONFIG_ULTRAMCA is not set +# CONFIG_ULTRA is not set +# CONFIG_ULTRA32 is not set +CONFIG_SMC9194=m +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_AT1700 is not set +# CONFIG_DEPCA is not set +# CONFIG_HP100 is not set +# CONFIG_NET_ISA is not set +# CONFIG_NET_PCI is not set +# CONFIG_NET_POCKET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_MYRI_SBUS is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_SK98LIN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PLIP is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set +# CONFIG_NET_FC is not set +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# PCMCIA network device support +# +CONFIG_NET_PCMCIA=y +# CONFIG_PCMCIA_3C589 is not set +# CONFIG_PCMCIA_3C574 is not set +# CONFIG_PCMCIA_FMVJ18X is not set +CONFIG_PCMCIA_PCNET=m +# CONFIG_PCMCIA_NMCLAN is not set +CONFIG_PCMCIA_SMC91C92=m +# CONFIG_PCMCIA_XIRC2PS is not set +# CONFIG_PCMCIA_AXNET is not set +# CONFIG_ARCNET_COM20020_CS is not set +# CONFIG_PCMCIA_IBMTR is not set +# CONFIG_NET_PCMCIA_RADIO is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +CONFIG_IRDA=m + +# +# IrDA protocols +# +CONFIG_IRLAN=m +# CONFIG_IRNET is not set +CONFIG_IRCOMM=m +# CONFIG_IRDA_ULTRA is not set +# CONFIG_IRDA_OPTIONS is not set + +# +# Infrared-port device drivers +# + +# +# SIR device drivers +# +CONFIG_IRTTY_SIR=m +CONFIG_IRPORT_SIR=m + +# +# Dongle support +# +# CONFIG_DONGLE is not set + +# +# FIR device drivers +# +# CONFIG_USB_IRDA is not set +# CONFIG_NSC_FIR is not set +# CONFIG_WINBOND_FIR is not set +# CONFIG_TOSHIBA_FIR is not set +# CONFIG_SMC_IRCC_FIR is not set +# CONFIG_ALI_FIR is not set +# CONFIG_VLSI_FIR is not set +CONFIG_SA1100_FIR=m + +# +# ATA/IDE/MFM/RLL support +# +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD_IDE is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set +# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set +# CONFIG_BLK_DEV_IDEDISK_IBM is not set +# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set +# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set +# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set +# CONFIG_BLK_DEV_IDEDISK_WD is not set +# CONFIG_BLK_DEV_COMMERIAL is not set +# CONFIG_BLK_DEV_TIVO is not set +CONFIG_BLK_DEV_IDECS=m +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set + +# +# IDE chipset support/bugfixes +# +# CONFIG_BLK_DEV_CMD640 is not set +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set +# CONFIG_BLK_DEV_ISAPNP is not set +# CONFIG_IDE_CHIPSETS is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_DMA_NONPCI is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_ATARAID is not set +# CONFIG_BLK_DEV_ATARAID_PDC is not set +# CONFIG_BLK_DEV_ATARAID_HPT is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# I2O device support +# +# CONFIG_I2O is not set +# CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_LAN is not set +# CONFIG_I2O_SCSI is not set +# CONFIG_I2O_PROC is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input core support +# +CONFIG_INPUT=y +CONFIG_INPUT_KEYBDEV=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_VT_CONSOLE is not set +# CONFIG_SERIAL is not set +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_ANAKIN is not set +# CONFIG_SERIAL_ANAKIN_CONSOLE is not set +# CONFIG_SERIAL_AMBA is not set +# CONFIG_SERIAL_AMBA_CONSOLE is not set +# CONFIG_SERIAL_CLPS711X is not set +# CONFIG_SERIAL_CLPS711X_CONSOLE is not set +# CONFIG_SERIAL_21285 is not set +# CONFIG_SERIAL_21285_OLD is not set +# CONFIG_SERIAL_21285_CONSOLE is not set +# CONFIG_SERIAL_UART00 is not set +# CONFIG_SERIAL_UART00_CONSOLE is not set +CONFIG_SERIAL_SA1100=y +CONFIG_SERIAL_SA1100_CONSOLE=y +CONFIG_SA1100_DEFAULT_BAUDRATE=38400 +CONFIG_SERIAL_8250=m +# CONFIG_SERIAL_8250_CONSOLE is not set +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_MANY_PORTS is not set +# CONFIG_SERIAL_8250_SHARE_IRQ is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_MULTIPORT is not set +# CONFIG_SERIAL_8250_HUB6 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=32 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# L3 serial bus support +# +# CONFIG_L3 is not set +# CONFIG_L3_ALGOBIT is not set +# CONFIG_L3_BIT_SA1100_GPIO is not set + +# +# Other L3 adapters +# +# CONFIG_L3_SA1111 is not set +# CONFIG_BIT_SA1100_GPIO is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_INPUT_NS558 is not set +# CONFIG_INPUT_LIGHTNING is not set +# CONFIG_INPUT_PCIGAME is not set +# CONFIG_INPUT_CS461X is not set +# CONFIG_INPUT_EMU10K1 is not set +# CONFIG_INPUT_SERIO is not set +# CONFIG_INPUT_SERPORT is not set + +# +# Joysticks +# +# CONFIG_INPUT_ANALOG is not set +# CONFIG_INPUT_A3D is not set +# CONFIG_INPUT_ADI is not set +# CONFIG_INPUT_COBRA is not set +# CONFIG_INPUT_GF2K is not set +# CONFIG_INPUT_GRIP is not set +# CONFIG_INPUT_INTERACT is not set +# CONFIG_INPUT_TMDC is not set +# CONFIG_INPUT_SIDEWINDER is not set +# CONFIG_INPUT_IFORCE_USB is not set +# CONFIG_INPUT_IFORCE_232 is not set +# CONFIG_INPUT_WARRIOR is not set +# CONFIG_INPUT_MAGELLAN is not set +# CONFIG_INPUT_SPACEORB is not set +# CONFIG_INPUT_SPACEBALL is not set +# CONFIG_INPUT_STINGER is not set +# CONFIG_INPUT_DB9 is not set +# CONFIG_INPUT_GAMECON is not set +# CONFIG_INPUT_TURBOGRAFX is not set +# CONFIG_QIC02_TAPE is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_INTEL_RNG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_SA1100_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# PCMCIA character devices +# +CONFIG_PCMCIA_SERIAL_CS=m + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_JBD_DEBUG is not set +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_CRAMFS is not set +CONFIG_TMPFS=y +# CONFIG_RAMFS is not set +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +CONFIG_DEVPTS_FS=y +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +# CONFIG_ROMFS_FS is not set +CONFIG_EXT2_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +# CONFIG_NFSD_V3 is not set +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_ZISOFS_FS is not set +# CONFIG_ZLIB_FS_INFLATE is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_SMB_NLS is not set +CONFIG_NLS=y + +# +# Native Language Support +# +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Console drivers +# +CONFIG_PC_KEYMAP=y +# CONFIG_VGA_CONSOLE is not set + +# +# Frame-buffer support +# +CONFIG_FB=y +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FB_ACORN is not set +# CONFIG_FB_ANAKIN is not set +# CONFIG_FB_CLPS711X is not set +CONFIG_FB_SA1100=y +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FBCON_ADVANCED is not set +CONFIG_FBCON_CFB2=y +CONFIG_FBCON_CFB4=y +CONFIG_FBCON_CFB8=y +CONFIG_FBCON_CFB16=y +CONFIG_FBCON_FONTWIDTH8_ONLY=y +CONFIG_FBCON_FONTS=y +CONFIG_FONT_8x8=y +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# Multimedia Capabilities Port drivers +# +# CONFIG_MCP is not set +# CONFIG_MCP_SA1100 is not set +# CONFIG_MCP_UCB1200 is not set +# CONFIG_MCP_UCB1200_AUDIO is not set +# CONFIG_MCP_UCB1200_TS is not set + +# +# USB support +# +CONFIG_USB=m +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB_LONG_TIMEOUT is not set + +# +# USB Controllers +# +# CONFIG_USB_UHCI is not set +# CONFIG_USB_UHCI_ALT is not set +# CONFIG_USB_OHCI is not set +CONFIG_USB_OHCI_SA1111=m + +# +# USB Device Class drivers +# +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_BLUETOOTH is not set +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_HP8200e is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=m + +# +# USB Human Interface Devices (HID) +# +CONFIG_USB_HID=m +CONFIG_USB_HIDDEV=y +CONFIG_USB_KBD=m +CONFIG_USB_MOUSE=m +# CONFIG_USB_WACOM is not set + +# +# USB Imaging devices +# +# CONFIG_USB_DC2XX is not set +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_SCANNER is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_HPUSBSCSI is not set + +# +# USB Multimedia devices +# + +# +# Video4Linux support is needed for USB Multimedia device support +# + +# +# USB Network adaptors +# +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_CATC is not set +# CONFIG_USB_CDCETHER is not set +CONFIG_USB_USBNET=m + +# +# USB port drivers +# +# CONFIG_USB_USS720 is not set + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OMNINET is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_RIO500 is not set + +# +# Bluetooth support +# +# CONFIG_BLUEZ is not set + +# +# Kernel hacking +# +# CONFIG_NO_FRAME_POINTER is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_INFO=y +# CONFIG_NO_PGT_CACHE is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_SLAB=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_WAITQ=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_DC21285_PORT is not set +# CONFIG_DEBUG_CLPS711X_UART2 is not set diff -urN linux-2.5.2-pre8/arch/arm/kernel/Makefile linux/arch/arm/kernel/Makefile --- linux-2.5.2-pre8/arch/arm/kernel/Makefile Thu Oct 25 13:53:45 2001 +++ linux/arch/arm/kernel/Makefile Sat Jan 5 14:43:15 2002 @@ -7,60 +7,45 @@ USE_STANDARD_AS_RULE := true -HEAD_OBJ = head-$(PROCESSOR).o ENTRY_OBJ = entry-$(PROCESSOR).o -AFLAGS_head-armv.o := -DTEXTADDR=$(TEXTADDR) -AFLAGS_head-armo.o := -DTEXTADDR=$(TEXTADDR) +AFLAGS_head.o := -DTEXTADDR=$(TEXTADDR) -# This is depreciated. -O_OBJS_arc = dma-arc.o oldlatches.o -O_OBJS_rpc = dma-rpc.o -O_OBJS_footbridge = dma-footbridge.o isa.o -O_OBJS_l7200 = fiq.o - -pci-ftvpci = plx90x0.o -pci-footbridge = dec21285.o -pci-shark = via82c505.o - -# this is here to allow us to eventually move it out to mach-ftvpci -pci-$(CONFIG_ARCH_FTVPCI) += ftv-pci.o - - -O_TARGET := kernel.o +O_TARGET := kernel.o # Object file lists. obj-y := arch.o compat.o dma.o $(ENTRY_OBJ) entry-common.o irq.o \ process.o ptrace.o semaphore.o setup.o signal.o sys_arm.o \ - time.o traps.o $(O_OBJS_$(MACHINE)) + time.o traps.o obj-m := obj-n := obj- := -export-objs := armksyms.o dma.o ecard.o fiq.o io.o oldlatches.o time.o +export-objs := armksyms.o apm.o dma.o ecard.o fiq.o io.o time.o -no-irq-arch := $(CONFIG_ARCH_INTEGRATOR) $(CONFIG_ARCH_CLPS711X) \ - $(CONFIG_FOOTBRIDGE) $(CONFIG_ARCH_EBSA110) \ - $(CONFIG_ARCH_SA1100) $(CONFIG_ARCH_CAMELOT) - -ifneq ($(findstring y,$(no-irq-arch)),y) - obj-y += irq-arch.o -endif - -obj-$(CONFIG_ARCH_ACORN) += ecard.o fiq.o time-acorn.o -obj-$(CONFIG_ARCH_CLPS7500) += time-acorn.o -obj-$(CONFIG_DEBUG_LL) += debug-$(PROCESSOR).o -obj-$(CONFIG_MODULES) += armksyms.o -obj-$(CONFIG_ARTHUR) += arthur.o -obj-$(CONFIG_ISA_DMA) += dma-isa.o -obj-$(CONFIG_PCI) += bios32.o $(pci-$(MACHINE)) $(pci-y) +obj-$(CONFIG_APM) += apm.o +obj-$(CONFIG_ARCH_ACORN) += ecard.o time-acorn.o +obj-$(CONFIG_ARCH_CLPS7500) += time-acorn.o +obj-$(CONFIG_FOOTBRIDGE) += isa.o +obj-$(CONFIG_FIQ) += fiq.o +obj-$(CONFIG_MODULES) += armksyms.o +obj-$(CONFIG_ARTHUR) += arthur.o +obj-$(CONFIG_ISA_DMA) += dma-isa.o +obj-$(CONFIG_PCI) += bios32.o +obj-$(CONFIG_PCI_HOST_PLX90X0) += plx90x0.o +obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o ifneq ($(MACHINE),ebsa110) obj-y += io.o endif -all: kernel.o $(HEAD_OBJ) init_task.o +ifeq ($(CONFIG_CPU_32),y) +head-y := head.o +obj-$(CONFIG_DEBUG_LL) += debug.o +endif + +all: kernel.o $(head-y) init_task.o include $(TOPDIR)/Rules.make diff -urN linux-2.5.2-pre8/arch/arm/kernel/arch.c linux/arch/arm/kernel/arch.c --- linux-2.5.2-pre8/arch/arm/kernel/arch.c Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/kernel/arch.c Sat Jan 5 14:43:15 2002 @@ -4,19 +4,13 @@ * Architecture specific fixups. */ #include -#include -#include -#include #include +#include #include #include #include - #include -#include - -extern void genarch_init_irq(void); unsigned int vram_size; @@ -49,129 +43,4 @@ __tagtable(ATAG_ACORN, parse_tag_acorn); -#ifdef CONFIG_ARCH_RPC -static void __init -fixup_riscpc(struct machine_desc *desc, struct param_struct *unusd, - char **cmdline, struct meminfo *mi) -{ - /* - * RiscPC can't handle half-word loads and stores - */ - elf_hwcap &= ~HWCAP_HALF; -} - -extern void __init rpc_map_io(void); - -MACHINE_START(RISCPC, "Acorn-RiscPC") - MAINTAINER("Russell King") - BOOT_MEM(0x10000000, 0x03000000, 0xe0000000) - BOOT_PARAMS(0x10000100) - DISABLE_PARPORT(0) - DISABLE_PARPORT(1) - FIXUP(fixup_riscpc) - MAPIO(rpc_map_io) - INITIRQ(genarch_init_irq) -MACHINE_END -#endif -#ifdef CONFIG_ARCH_ARC -MACHINE_START(ARCHIMEDES, "Acorn-Archimedes") - MAINTAINER("Dave Gilbert") - BOOT_PARAMS(0x0207c000) - INITIRQ(genarch_init_irq) -MACHINE_END -#endif -#ifdef CONFIG_ARCH_A5K -MACHINE_START(A5K, "Acorn-A5000") - MAINTAINER("Russell King") - BOOT_PARAMS(0x0207c000) - INITIRQ(genarch_init_irq) -MACHINE_END -#endif -#endif - -#ifdef CONFIG_ARCH_L7200 -extern void __init l7200_map_io(void); - -static void __init -fixup_l7200(struct machine_desc *desc, struct param_struct *unused, - char **cmdline, struct meminfo *mi) -{ - mi->nr_banks = 1; - mi->bank[0].start = PHYS_OFFSET; - mi->bank[0].size = (32*1024*1024); - mi->bank[0].node = 0; - - ROOT_DEV = MKDEV(RAMDISK_MAJOR,0); - setup_ramdisk( 1, 0, 0, CONFIG_BLK_DEV_RAM_SIZE); - setup_initrd( __phys_to_virt(0xf1000000), 0x005dac7b); - - /* Serial Console COM2 and LCD */ - strcpy( *cmdline, "console=tty0 console=ttyLU1,115200"); - - /* Serial Console COM1 and LCD */ - //strcpy( *cmdline, "console=tty0 console=ttyLU0,115200"); - - /* Console on LCD */ - //strcpy( *cmdline, "console=tty0"); -} - -MACHINE_START(L7200, "LinkUp Systems L7200") - MAINTAINER("Steve Hill / Scott McConnell") - BOOT_MEM(0xf0000000, 0x80040000, 0xd0000000) - FIXUP(fixup_l7200) - MAPIO(l7200_map_io) - INITIRQ(genarch_init_irq) -MACHINE_END -#endif - -#ifdef CONFIG_ARCH_NEXUSPCI - -extern void __init nexuspci_map_io(void); - -MACHINE_START(NEXUSPCI, "FTV/PCI") - MAINTAINER("Philip Blundell") - BOOT_MEM(0x40000000, 0x10000000, 0xe0000000) - MAPIO(nexuspci_map_io) - INITIRQ(genarch_init_irq) -MACHINE_END -#endif -#ifdef CONFIG_ARCH_TBOX - -extern void __init tbox_map_io(void); - -MACHINE_START(TBOX, "unknown-TBOX") - MAINTAINER("Philip Blundell") - BOOT_MEM(0x80000000, 0x00400000, 0xe0000000) - MAPIO(tbox_map_io) - INITIRQ(genarch_init_irq) -MACHINE_END -#endif -#ifdef CONFIG_ARCH_CLPS7110 -MACHINE_START(CLPS7110, "CL-PS7110") - MAINTAINER("Werner Almesberger") - INITIRQ(genarch_init_irq) -MACHINE_END -#endif -#ifdef CONFIG_ARCH_ETOILE -MACHINE_START(ETOILE, "Etoile") - MAINTAINER("Alex de Vries") - INITIRQ(genarch_init_irq) -MACHINE_END -#endif -#ifdef CONFIG_ARCH_LACIE_NAS -MACHINE_START(LACIE_NAS, "LaCie_NAS") - MAINTAINER("Benjamin Herrenschmidt") - INITIRQ(genarch_init_irq) -MACHINE_END -#endif -#ifdef CONFIG_ARCH_CLPS7500 - -extern void __init clps7500_map_io(void); - -MACHINE_START(CLPS7500, "CL-PS7500") - MAINTAINER("Philip Blundell") - BOOT_MEM(0x10000000, 0x03000000, 0xe0000000) - MAPIO(clps7500_map_io) - INITIRQ(genarch_init_irq) -MACHINE_END #endif diff -urN linux-2.5.2-pre8/arch/arm/kernel/armksyms.c linux/arch/arm/kernel/armksyms.c --- linux-2.5.2-pre8/arch/arm/kernel/armksyms.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/kernel/armksyms.c Sat Jan 5 14:43:15 2002 @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -77,7 +78,7 @@ extern void __do_softirq(void); #define EXPORT_SYMBOL_ALIAS(sym,orig) \ - const char __kstrtab_##sym##[] \ + const char __kstrtab_##sym[] \ __attribute__((section(".kstrtab"))) = \ __MODULE_STRING(sym); \ const struct module_symbol __ksymtab_##sym \ @@ -115,7 +116,9 @@ EXPORT_SYMBOL(system_rev); EXPORT_SYMBOL(system_serial_low); EXPORT_SYMBOL(system_serial_high); +#ifdef CONFIG_DEBUG_BUGVERBOSE EXPORT_SYMBOL(__bug); +#endif EXPORT_SYMBOL(__bad_xchg); EXPORT_SYMBOL(__readwrite_bug); EXPORT_SYMBOL(enable_irq); @@ -231,14 +234,25 @@ EXPORT_SYMBOL_NOVERS(__umodsi3); /* bitops */ -EXPORT_SYMBOL(set_bit); -EXPORT_SYMBOL(test_and_set_bit); -EXPORT_SYMBOL(clear_bit); -EXPORT_SYMBOL(test_and_clear_bit); -EXPORT_SYMBOL(change_bit); -EXPORT_SYMBOL(test_and_change_bit); -EXPORT_SYMBOL(find_first_zero_bit); -EXPORT_SYMBOL(find_next_zero_bit); +EXPORT_SYMBOL(_set_bit_le); +EXPORT_SYMBOL(_test_and_set_bit_le); +EXPORT_SYMBOL(_clear_bit_le); +EXPORT_SYMBOL(_test_and_clear_bit_le); +EXPORT_SYMBOL(_change_bit_le); +EXPORT_SYMBOL(_test_and_change_bit_le); +EXPORT_SYMBOL(_find_first_zero_bit_le); +EXPORT_SYMBOL(_find_next_zero_bit_le); + +#ifdef __ARMEB__ +EXPORT_SYMBOL(_set_bit_be); +EXPORT_SYMBOL(_test_and_set_bit_be); +EXPORT_SYMBOL(_clear_bit_be); +EXPORT_SYMBOL(_test_and_clear_bit_be); +EXPORT_SYMBOL(_change_bit_be); +EXPORT_SYMBOL(_test_and_change_bit_be); +EXPORT_SYMBOL(_find_first_zero_bit_be); +EXPORT_SYMBOL(_find_next_zero_bit_be); +#endif /* elf */ EXPORT_SYMBOL(elf_platform); diff -urN linux-2.5.2-pre8/arch/arm/kernel/bios32.c linux/arch/arm/kernel/bios32.c --- linux-2.5.2-pre8/arch/arm/kernel/bios32.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/kernel/bios32.c Sat Jan 5 14:43:15 2002 @@ -19,20 +19,6 @@ static int debug_pci; int have_isa_bridge; -struct pci_sys_data { - /* - * The hardware we are attached to - */ - struct hw_pci *hw; - - unsigned long mem_offset; - - /* - * These are the resources for the root bus. - */ - struct resource *resource[3]; -}; - void pcibios_report_status(u_int status_mask, int warn) { struct pci_dev *dev; @@ -153,8 +139,7 @@ } /* - * PCI IDE controllers use non-standard I/O port - * decoding, respect it. + * PCI IDE controllers use non-standard I/O port decoding, respect it. */ static void __init pci_fixup_ide_bases(struct pci_dev *dev) { @@ -181,9 +166,82 @@ pci_write_config_dword(dev, 0x40, 0x80000000); } +/* + * The CY82C693 needs some rather major fixups to ensure that it does + * the right thing. Idea from the Alpha people, with a few additions. + * + * We ensure that the IDE base registers are set to 1f0/3f4 for the + * primary bus, and 170/374 for the secondary bus. Also, hide them + * from the PCI subsystem view as well so we won't try to perform + * our own auto-configuration on them. + * + * In addition, we ensure that the PCI IDE interrupts are routed to + * IRQ 14 and IRQ 15 respectively. + * + * The above gets us to a point where the IDE on this device is + * functional. However, The CY82C693U _does not work_ in bus + * master mode without locking the PCI bus solid. + */ +static void __init pci_fixup_cy82c693(struct pci_dev *dev) +{ + if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) { + u32 base0, base1; + + if (dev->class & 0x80) { /* primary */ + base0 = 0x1f0; + base1 = 0x3f4; + } else { /* secondary */ + base0 = 0x170; + base1 = 0x374; + } + + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, + base0 | PCI_BASE_ADDRESS_SPACE_IO); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, + base1 | PCI_BASE_ADDRESS_SPACE_IO); + + dev->resource[0].start = 0; + dev->resource[0].end = 0; + dev->resource[0].flags = 0; + + dev->resource[1].start = 0; + dev->resource[1].end = 0; + dev->resource[1].flags = 0; + } else if (PCI_FUNC(dev->devfn) == 0) { + /* + * Setup IDE IRQ routing. + */ + pci_write_config_byte(dev, 0x4b, 14); + pci_write_config_byte(dev, 0x4c, 15); + + /* + * Disable FREQACK handshake, enable USB. + */ + pci_write_config_byte(dev, 0x4d, 0x41); + + /* + * Enable PCI retry, and PCI post-write buffer. + */ + pci_write_config_byte(dev, 0x44, 0x17); + + /* + * Enable ISA master and DMA post write buffering. + */ + pci_write_config_byte(dev, 0x45, 0x03); + } +} + struct pci_fixup pcibios_fixups[] = { { PCI_FIXUP_HEADER, + PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, + pci_fixup_cy82c693 + }, { + PCI_FIXUP_HEADER, + PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, + pci_fixup_dec21142 + }, { + PCI_FIXUP_HEADER, PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285 }, { @@ -198,10 +256,6 @@ PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases - }, { - PCI_FIXUP_HEADER, - PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, - pci_fixup_dec21142 }, { 0 } }; @@ -232,6 +286,8 @@ val = res->start; if (res->flags & IORESOURCE_MEM) val -= sys->mem_offset; + else + val -= sys->io_offset; val |= res->flags & PCI_REGION_FLAG_MASK; pci_write_config_dword(dev, reg, val); @@ -268,15 +324,19 @@ static void __init pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev) { + unsigned long offset; int i; for (i = 0; i < PCI_NUM_RESOURCES; i++) { if (dev->resource[i].start == 0) continue; - if (dev->resource[i].flags & IORESOURCE_MEM) { - dev->resource[i].start += root->mem_offset; - dev->resource[i].end += root->mem_offset; - } + if (dev->resource[i].flags & IORESOURCE_MEM) + offset = root->mem_offset; + else + offset = root->io_offset; + + dev->resource[i].start += offset; + dev->resource[i].end += offset; } } @@ -388,15 +448,116 @@ { struct pci_sys_data *root = bus->sysdata; + ranges->io_start -= root->io_offset; + ranges->io_end -= root->io_offset; ranges->mem_start -= root->mem_offset; ranges->mem_end -= root->mem_offset; ranges->prefetch_start -= root->mem_offset; ranges->prefetch_end -= root->mem_offset; } -u8 __init no_swizzle(struct pci_dev *dev, u8 *pin) +/* + * This is the standard PCI-PCI bridge swizzling algorithm: + * + * Dev: 0 1 2 3 + * A A B C D + * B B C D A + * C C D A B + * D D A B C + * ^^^^^^^^^^ irq pin on bridge + */ +u8 __devinit pci_std_swizzle(struct pci_dev *dev, u8 *pinp) +{ + int pin = *pinp; + + if (pin != 0) { + pin -= 1; + while (dev->bus->self) { + pin = (pin + PCI_SLOT(dev->devfn)) & 3; + /* + * move up the chain of bridges, + * swizzling as we go. + */ + dev = dev->bus->self; + } + *pinp = pin + 1; + } + + return PCI_SLOT(dev->devfn); +} + +/* + * Swizzle the device pin each time we cross a bridge. + * This might update pin and returns the slot number. + */ +static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin) +{ + struct pci_sys_data *sys = dev->sysdata; + int slot = 0, oldpin = *pin; + + if (sys->swizzle) + slot = sys->swizzle(dev, pin); + + if (debug_pci) + printk("PCI: %s swizzling pin %d => pin %d slot %d\n", + dev->slot_name, oldpin, *pin, slot); + + return slot; +} + +/* + * Map a slot/pin to an IRQ. + */ +static int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - return 0; + struct pci_sys_data *sys = dev->sysdata; + int irq = -1; + + if (sys->map_irq) + irq = sys->map_irq(dev, slot, pin); + + if (debug_pci) + printk("PCI: %s mapping slot %d pin %d => irq %d\n", + dev->slot_name, slot, pin, irq); + + return irq; +} + +static void __init pcibios_init_hw(struct hw_pci *hw) +{ + struct pci_sys_data *sys = NULL; + int ret; + int nr, busnr; + + for (nr = busnr = 0; nr < hw->nr_controllers; nr++) { + sys = kmalloc(sizeof(struct pci_sys_data), GFP_KERNEL); + if (!sys) + panic("PCI: unable to allocate sys data!"); + + memset(sys, 0, sizeof(struct pci_sys_data)); + + sys->hw = hw; + sys->busnr = busnr; + sys->swizzle = hw->swizzle; + sys->map_irq = hw->map_irq; + sys->resource[0] = &ioport_resource; + sys->resource[1] = &iomem_resource; + + ret = hw->setup(nr, sys); + + if (ret > 0) { + sys->bus = hw->scan(nr, sys); + + if (!sys->bus) + panic("PCI: unable to scan bus!"); + + busnr = sys->bus->subordinate + 1; + } else if (ret < 0) + break; + } + + kfree(sys); + } extern struct hw_pci ebsa285_pci; @@ -406,10 +567,10 @@ extern struct hw_pci ftv_pci; extern struct hw_pci shark_pci; extern struct hw_pci integrator_pci; +extern struct hw_pci iq80310_pci; void __init pcibios_init(void) { - struct pci_sys_data *root; struct hw_pci *hw = NULL; do { @@ -455,44 +616,28 @@ break; } #endif +#ifdef CONFIG_ARCH_IQ80310 + if (machine_is_iq80310()) { + hw = &iq80310_pci; + break; + } +#endif } while (0); if (hw == NULL) return; - root = kmalloc(sizeof(*root), GFP_KERNEL); - if (!root) - panic("PCI: unable to allocate root data!"); - - root->hw = hw; - root->mem_offset = hw->mem_offset; - - memset(root->resource, 0, sizeof(root->resource)); - - /* - * Setup the resources for this bus. - * resource[0] - IO ports - * resource[1] - non-prefetchable memory - * resource[2] - prefetchable memory - */ - if (root->hw->setup_resources) - root->hw->setup_resources(root->resource); - else { - root->resource[0] = &ioport_resource; - root->resource[1] = &iomem_resource; - root->resource[2] = NULL; - } - - /* - * Set up the host bridge, and scan the bus. - */ - root->hw->init(root); + if (hw->preinit) + hw->preinit(); + pcibios_init_hw(hw); + if (hw->postinit) + hw->postinit(); /* * Assign any unassigned resources. */ pci_assign_unassigned_resources(); - pci_fixup_irqs(root->hw->swizzle, root->hw->map_irq); + pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq); } char * __init pcibios_setup(char *str) diff -urN linux-2.5.2-pre8/arch/arm/kernel/compat.c linux/arch/arm/kernel/compat.c --- linux-2.5.2-pre8/arch/arm/kernel/compat.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/kernel/compat.c Sat Jan 5 14:43:15 2002 @@ -89,10 +89,12 @@ } #ifdef CONFIG_FOOTBRIDGE - tag = tag_next(tag); - tag->hdr.tag = ATAG_MEMCLK; - tag->hdr.size = tag_size(tag_memclk); - tag->u.memclk.fmemclk = params->u1.s.mem_fclk_21285; + if (params->u1.s.mem_fclk_21285) { + tag = tag_next(tag); + tag->hdr.tag = ATAG_MEMCLK; + tag->hdr.size = tag_size(tag_memclk); + tag->u.memclk.fmemclk = params->u1.s.mem_fclk_21285; + } #endif #ifdef CONFIG_ARCH_ACORN diff -urN linux-2.5.2-pre8/arch/arm/kernel/debug-armo.S linux/arch/arm/kernel/debug-armo.S --- linux-2.5.2-pre8/arch/arm/kernel/debug-armo.S Mon Sep 18 15:15:24 2000 +++ linux/arch/arm/kernel/debug-armo.S Wed Dec 31 16:00:00 1969 @@ -1,90 +0,0 @@ -/* - * linux/arch/arm/kernel/debug-armo.S - * - * Copyright (C) 1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * 26-bit debugging code - */ -#include - - .macro addruart,rx - mov \rx, #0x03000000 - orr \rx, \rx, #0x00010000 - orr \rx, \rx, #0x00000fe0 - .endm - - .macro senduart,rd,rx - strb \rd, [\rx] - .endm - - .macro busyuart,rd,rx -1002: ldrb \rd, [\rx, #0x14] - and \rd, \rd, #0x60 - teq \rd, #0x60 - bne 1002b - .endm - - .macro waituart,rd,rx -1001: ldrb \rd, [\rx, #0x18] - tst \rd, #0x10 - beq 1001b - .endm - - .text -/* - * Useful debugging routines - */ -ENTRY(printhex8) - mov r1, #8 - b printhex - -ENTRY(printhex4) - mov r1, #4 - b printhex - -ENTRY(printhex2) - mov r1, #2 -printhex: ldr r2, =hexbuf - add r3, r2, r1 - mov r1, #0 - strb r1, [r3] -1: and r1, r0, #15 - mov r0, r0, lsr #4 - cmp r1, #10 - addlt r1, r1, #'0' - addge r1, r1, #'a' - 10 - strb r1, [r3, #-1]! - teq r3, r2 - bne 1b - mov r0, r2 - b printascii - - .ltorg - -ENTRY(printascii) - addruart r3 - b 2f -1: waituart r2, r3 - senduart r1, r3 - busyuart r2, r3 - teq r1, #'\n' - moveq r1, #'\r' - beq 1b -2: teq r0, #0 - ldrneb r1, [r0], #1 - teqne r1, #0 - bne 1b - mov pc, lr - -ENTRY(printch) - addruart r3 - mov r1, r0 - mov r0, #0 - b 1b - - .bss -hexbuf: .space 16 diff -urN linux-2.5.2-pre8/arch/arm/kernel/dma-arc.c linux/arch/arm/kernel/dma-arc.c --- linux-2.5.2-pre8/arch/arm/kernel/dma-arc.c Wed Jul 4 14:56:44 2001 +++ linux/arch/arm/kernel/dma-arc.c Wed Dec 31 16:00:00 1969 @@ -1,208 +0,0 @@ -/* - * linux/arch/arm/kernel/dma-arc.c - * - * Copyright (C) 1998-1999 Dave Gilbert / Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * DMA functions specific to Archimedes and A5000 architecture - */ -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#define DPRINTK(x...) printk(KERN_DEBUG x) - -#if defined(CONFIG_BLK_DEV_FD1772) || defined(CONFIG_BLK_DEV_FD1772_MODULE) -static void arc_floppy_data_enable_dma(dmach_t channel, dma_t *dma) -{ - DPRINTK("arc_floppy_data_enable_dma\n"); - switch (dma->dma_mode) { - case DMA_MODE_READ: { /* read */ - extern unsigned char fdc1772_dma_read, fdc1772_dma_read_end; - extern void fdc1772_setupdma(unsigned int count,unsigned int addr); - unsigned long flags; - DPRINTK("enable_dma fdc1772 data read\n"); - save_flags(flags); - clf(); - - memcpy ((void *)0x1c, (void *)&fdc1772_dma_read, - &fdc1772_dma_read_end - &fdc1772_dma_read); - fdc1772_setupdma(dma->buf.length, dma->buf.address); /* Sets data pointer up */ - enable_fiq(FIQ_FLOPPYDATA); - restore_flags(flags); - } - break; - - case DMA_MODE_WRITE: { /* write */ - extern unsigned char fdc1772_dma_write, fdc1772_dma_write_end; - extern void fdc1772_setupdma(unsigned int count,unsigned int addr); - unsigned long flags; - DPRINTK("enable_dma fdc1772 data write\n"); - save_flags(flags); - clf(); - memcpy ((void *)0x1c, (void *)&fdc1772_dma_write, - &fdc1772_dma_write_end - &fdc1772_dma_write); - fdc1772_setupdma(dma->buf.length, dma->buf.address); /* Sets data pointer up */ - enable_fiq(FIQ_FLOPPYDATA; - - restore_flags(flags); - } - break; - default: - printk ("enable_dma: dma%d not initialised\n", channel); - } -} - -static int arc_floppy_data_get_dma_residue(dmach_t channel, dma_t *dma) -{ - extern unsigned int fdc1772_bytestogo; - - /* 10/1/1999 DAG - I presume its the number of bytes left? */ - return fdc1772_bytestogo; -} - -static void arc_floppy_cmdend_enable_dma(dmach_t channel, dma_t *dma) -{ - /* Need to build a branch at the FIQ address */ - extern void fdc1772_comendhandler(void); - unsigned long flags; - - DPRINTK("arc_floppy_cmdend_enable_dma\n"); - /*printk("enable_dma fdc1772 command end FIQ\n");*/ - save_flags(flags); - clf(); - - /* B fdc1772_comendhandler */ - *((unsigned int *)0x1c)=0xea000000 | - (((unsigned int)fdc1772_comendhandler-(0x1c+8))/4); - - restore_flags(flags); -} - -static int arc_floppy_cmdend_get_dma_residue(dmach_t channel, dma_t *dma) -{ - /* 10/1/1999 DAG - Presume whether there is an outstanding command? */ - extern unsigned int fdc1772_fdc_int_done; - - * Explicit! If the int done is 0 then 1 int to go */ - return (fdc1772_fdc_int_done==0)?1:0; -} - -static void arc_disable_dma(dmach_t channel, dma_t *dma) -{ - disable_fiq(dma->dma_irq); -} - -static struct dma_ops arc_floppy_data_dma_ops = { - type: "FIQDMA", - enable: arc_floppy_data_enable_dma, - disable: arc_disable_dma, - residue: arc_floppy_data_get_dma_residue, -}; - -static struct dma_ops arc_floppy_cmdend_dma_ops = { - type: "FIQCMD", - enable: arc_floppy_cmdend_enable_dma, - disable: arc_disable_dma, - residue: arc_floppy_cmdend_get_dma_residue, -}; -#endif - -#ifdef CONFIG_ARCH_A5K -static struct fiq_handler fh = { - name: "floppydata" -}; - -static int a5k_floppy_get_dma_residue(dmach_t channel, dma_t *dma) -{ - struct pt_regs regs; - get_fiq_regs(®s); - return regs.ARM_r9; -} - -static void a5k_floppy_enable_dma(dmach_t channel, dma_t *dma) -{ - struct pt_regs regs; - void *fiqhandler_start; - unsigned int fiqhandler_length; - extern void floppy_fiqsetup(unsigned long len, unsigned long addr, - unsigned long port); - - if (dma->dma_mode == DMA_MODE_READ) { - extern unsigned char floppy_fiqin_start, floppy_fiqin_end; - fiqhandler_start = &floppy_fiqin_start; - fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start; - } else { - extern unsigned char floppy_fiqout_start, floppy_fiqout_end; - fiqhandler_start = &floppy_fiqout_start; - fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start; - } - if (claim_fiq(&fh)) { - printk("floppydma: couldn't claim FIQ.\n"); - return; - } - memcpy((void *)0x1c, fiqhandler_start, fiqhandler_length); - regs.ARM_r9 = dma->buf.length; - regs.ARM_r10 = (unsigned long)dma->buf.address; - regs.ARM_fp = FLOPPYDMA_BASE; - set_fiq_regs(®s); - enable_fiq(dma->dma_irq); -} - -static void a5k_floppy_disable_dma(dmach_t channel, dma_t *dma) -{ - disable_fiq(dma->dma_irq); - release_fiq(&fh); -} - -static struct dma_ops a5k_floppy_dma_ops = { - type: "FIQDMA", - enable: a5k_floppy_enable_dma, - disable: a5k_floppy_disable_dma, - residue: a5k_floppy_get_dma_residue, -}; -#endif - -/* - * This is virtual DMA - we don't need anything here - */ -static void sound_enable_disable_dma(dmach_t channel, dma_t *dma) -{ -} - -static struct dma_ops sound_dma_ops = { - type: "VIRTUAL", - enable: sound_enable_disable_dma, - disable: sound_enable_disable_dma, -}; - -void __init arch_dma_init(dma_t *dma) -{ -#if defined(CONFIG_BLK_DEV_FD1772) || defined(CONFIG_BLK_DEV_FD1772_MODULE) - if (machine_is_archimedes()) { - dma[DMA_VIRTUAL_FLOPPY0].dma_irq = FIQ_FLOPPYDATA; - dma[DMA_VIRTUAL_FLOPPY0].d_ops = &arc_floppy_data_dma_ops; - dma[DMA_VIRTUAL_FLOPPY1].dma_irq = 1; - dma[DMA_VIRTUAL_FLOPPY1].d_ops = &arc_floppy_cmdend_dma_ops; - } -#endif -#ifdef CONFIG_ARCH_A5K - if (machine_is_a5k()) { - dma[DMA_VIRTUAL_FLOPPY0].dma_irq = FIQ_FLOPPYDATA; - dma[DMA_VIRTUAL_FLOPPY0].d_ops = &a5k_floppy_dma_ops; - } -#endif - dma[DMA_VIRTUAL_SOUND].d_ops = &sound_dma_ops; -} diff -urN linux-2.5.2-pre8/arch/arm/kernel/dma-isa.c linux/arch/arm/kernel/dma-isa.c --- linux-2.5.2-pre8/arch/arm/kernel/dma-isa.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/kernel/dma-isa.c Sat Jan 5 14:43:15 2002 @@ -95,7 +95,7 @@ * coherence. */ dma->buf.dma_address = pci_map_single(NULL, - dma->buf.address, dma->buf.length, + dma->buf.__address, dma->buf.length, direction); } diff -urN linux-2.5.2-pre8/arch/arm/kernel/dma.c linux/arch/arm/kernel/dma.c --- linux-2.5.2-pre8/arch/arm/kernel/dma.c Fri Feb 9 11:29:44 2001 +++ linux/arch/arm/kernel/dma.c Sat Jan 5 14:43:15 2002 @@ -139,7 +139,7 @@ dma->sg = &dma->buf; dma->sgcount = 1; - dma->buf.address = bus_to_virt(physaddr); + dma->buf.__address = bus_to_virt(physaddr); dma->using_sg = 0; dma->invalid = 1; } @@ -275,6 +275,8 @@ #endif +EXPORT_SYMBOL(request_dma); +EXPORT_SYMBOL(free_dma); EXPORT_SYMBOL(enable_dma); EXPORT_SYMBOL(disable_dma); EXPORT_SYMBOL(set_dma_addr); diff -urN linux-2.5.2-pre8/arch/arm/kernel/entry-armo.S linux/arch/arm/kernel/entry-armo.S --- linux-2.5.2-pre8/arch/arm/kernel/entry-armo.S Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/kernel/entry-armo.S Sat Jan 5 14:43:15 2002 @@ -169,7 +169,7 @@ bne __und_svc save_user_regs zero_fp - teqp pc, #I_BIT | MODE_SVC + teqp pc, #PSR_I_BIT | MODE_SVC .Lbug_undef: ldr r4, .LC2 ldr pc, [r4] @ Call FP module USR entry point diff -urN linux-2.5.2-pre8/arch/arm/kernel/entry-armv.S linux/arch/arm/kernel/entry-armv.S --- linux-2.5.2-pre8/arch/arm/kernel/entry-armv.S Thu Oct 25 13:53:45 2001 +++ linux/arch/arm/kernel/entry-armv.S Sat Jan 5 14:43:15 2002 @@ -548,6 +548,39 @@ .text .endm +#elif defined(CONFIG_ARCH_IOP310) || defined(CONFIG_ARCH_ADIFCC) + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mrc p13, 0, \irqstat, c4, c0, 0 @ get INTSRC + mrc p13, 0, \base, c0, c0, 0 @ get INTCTL + + tst \irqstat, #(1<<29) @ if INTSRC_BI + tstne \base, #(1<<3) @ and INTCTL_BM + movne \irqnr, #IRQ_XS80200_BCU + bne 1001f + + tst \irqstat, #(1<<28) @ if INTSRC_PI + tstne \base, #(1<<2) @ and INTCTL_PM + movne \irqnr, #IRQ_XS80200_PMU + bne 1001f + + tst \irqstat, #(1<<31) @ if INTSRC_FI + tstne \base, #(1<<0) @ and INTCTL_FM + movne \irqnr, #IRQ_XS80200_EXTFIQ + bne 1001f + + tst \irqstat, #(1<<30) @ if INTSRC_II + tstne \base, #(1<<1) @ and INTCTL_IM + movne \irqnr, #IRQ_XS80200_EXTIRQ + +1001: + .endm + + .macro irq_prio_table + .endm #else #error Unknown architecture #endif @@ -641,23 +674,23 @@ mov r1, lr stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_ro mrs r9, cpsr @ Enable interrupts if they were - tst r3, #I_BIT - biceq r9, r9, #I_BIT @ previously - mov r0, r2 + tst r3, #PSR_I_BIT + biceq r9, r9, #PSR_I_BIT @ previously + mov r0, r2 @ *** remove once everyones in sync /* * This routine must not corrupt r9 */ #ifdef MULTI_CPU - ldr r2, .LCprocfns @ pass r0, r3 to + ldr r4, .LCprocfns @ pass r0, r3 to mov lr, pc @ processor code - ldr pc, [r2] @ call processor specific code + ldr pc, [r4] @ call processor specific code #else bl cpu_data_abort #endif msr cpsr_c, r9 mov r2, sp bl SYMBOL_NAME(do_DataAbort) - mov r0, #I_BIT | MODE_SVC + mov r0, #PSR_I_BIT | MODE_SVC msr cpsr_c, r0 ldr r0, [sp, #S_PSR] msr spsr, r0 @@ -700,7 +733,7 @@ mov r1, sp @ struct pt_regs *regs bl SYMBOL_NAME(do_undefinstr) -1: mov r0, #I_BIT | MODE_SVC +1: mov r0, #PSR_I_BIT | MODE_SVC msr cpsr_c, r0 ldr lr, [sp, #S_PSR] @ Get SVC cpsr msr spsr, lr @@ -716,13 +749,13 @@ mov r1, lr stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_ro mrs r9, cpsr @ Enable interrupts if they were - tst r3, #I_BIT - biceq r9, r9, #I_BIT @ previously + tst r3, #PSR_I_BIT + biceq r9, r9, #PSR_I_BIT @ previously msr cpsr_c, r9 mov r0, r2 @ address (pc) mov r1, sp @ regs bl SYMBOL_NAME(do_PrefetchAbort) @ call abort handler - mov r0, #I_BIT | MODE_SVC + mov r0, #PSR_I_BIT | MODE_SVC msr cpsr_c, r0 ldr r0, [sp, #S_PSR] msr spsr, r0 @@ -747,15 +780,16 @@ stmia sp, {r0 - r12} @ save r0 - r12 ldr r7, .LCabt add r5, sp, #S_PC - ldmia r7, {r0, r3, r4} @ Get USR pc, cpsr - stmia r5, {r0, r3, r4} @ Save USR pc, cpsr, old_r0 + ldmia r7, {r2 - r4} @ Get USR pc, cpsr + stmia r5, {r2 - r4} @ Save USR pc, cpsr, old_r0 stmdb r5, {sp, lr}^ alignment_trap r7, r7, __temp_abt zero_fp + mov r0, r2 @ remove once everyones in sync #ifdef MULTI_CPU - ldr r2, .LCprocfns @ pass r0, r3 to + ldr r4, .LCprocfns @ pass r0, r3 to mov lr, pc @ processor code - ldr pc, [r2] @ call processor specific code + ldr pc, [r4] @ call processor specific code #else bl cpu_data_abort #endif @@ -883,7 +917,7 @@ @ @ now branch to the relevent MODE handling routine @ - mov r13, #I_BIT | MODE_SVC + mov r13, #PSR_I_BIT | MODE_SVC msr spsr_c, r13 @ switch to SVC_32 mode and lr, lr, #15 @@ -924,7 +958,7 @@ @ @ now branch to the relevent MODE handling routine @ - mov r13, #I_BIT | MODE_SVC + mov r13, #PSR_I_BIT | MODE_SVC msr spsr_c, r13 @ switch to SVC_32 mode and lr, lr, #15 @@ -966,7 +1000,7 @@ @ @ now branch to the relevent MODE handling routine @ - mov r13, #I_BIT | MODE_SVC + mov r13, #PSR_I_BIT | MODE_SVC msr spsr_c, r13 @ switch to SVC_32 mode ands lr, lr, #15 @@ -1007,7 +1041,7 @@ @ @ now branch to the relevent MODE handling routine @ - mov r13, #I_BIT | MODE_SVC + mov r13, #PSR_I_BIT | MODE_SVC msr spsr_c, r13 @ switch to SVC_32 mode and lr, lr, #15 diff -urN linux-2.5.2-pre8/arch/arm/kernel/entry-common.S linux/arch/arm/kernel/entry-common.S --- linux-2.5.2-pre8/arch/arm/kernel/entry-common.S Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/kernel/entry-common.S Sat Jan 5 14:43:15 2002 @@ -22,12 +22,10 @@ * Our do_softirq out of line code. See include/asm-arm/softirq.h for * the calling assembly. */ - .section ".text.lock","ax" ENTRY(__do_softirq) stmfd sp!, {r0 - r3, ip, lr} bl do_softirq ldmfd sp!, {r0 - r3, ip, pc} - .previous .align 5 /* diff -urN linux-2.5.2-pre8/arch/arm/kernel/entry-header.S linux/arch/arm/kernel/entry-header.S --- linux-2.5.2-pre8/arch/arm/kernel/entry-header.S Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/kernel/entry-header.S Sat Jan 5 14:43:15 2002 @@ -83,7 +83,7 @@ .macro restore_user_regs ldr r0, [sp, #S_PSR] @ Get calling cpsr - mov ip, #I_BIT | MODE_SVC + mov ip, #PSR_I_BIT | MODE_SVC msr cpsr_c, ip @ disable IRQs msr spsr, r0 @ save in spsr_svc ldr lr, [sp, #S_PC] @ Get PC @@ -94,7 +94,7 @@ .endm .macro fast_restore_user_regs - mov ip, #I_BIT | MODE_SVC + mov ip, #PSR_I_BIT | MODE_SVC msr cpsr_c, ip @ disable IRQs ldr r1, [sp, #S_OFF + S_PSR] @ get calling cpsr ldr lr, [sp, #S_OFF + S_PC]! @ get pc @@ -207,7 +207,7 @@ */ .macro get_scno #ifdef CONFIG_ARM_THUMB - tst r8, #T_BIT @ this is SPSR from save_user_regs + tst r8, #PSR_T_BIT @ this is SPSR from save_user_regs addne scno, r7, #OS_NUMBER << 20 @ put OS number in ldreq scno, [lr, #-4] diff -urN linux-2.5.2-pre8/arch/arm/kernel/fiq.c linux/arch/arm/kernel/fiq.c --- linux-2.5.2-pre8/arch/arm/kernel/fiq.c Wed Nov 28 13:22:25 2001 +++ linux/arch/arm/kernel/fiq.c Sat Jan 5 14:43:15 2002 @@ -139,7 +139,7 @@ mov r0, r0" #endif : "=&r" (tmp), "=&r" (tmp2) - : "r" (®s->ARM_r8), "I" (I_BIT | F_BIT | FIQ_MODE) + : "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE) /* These registers aren't modified by the above code in a way visible to the compiler, but we mark them as clobbers anyway so that GCC won't put any of the input or output operands in @@ -171,7 +171,7 @@ mov r0, r0" #endif : "=&r" (tmp), "=&r" (tmp2) - : "r" (®s->ARM_r8), "I" (I_BIT | F_BIT | FIQ_MODE) + : "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE) /* These registers aren't modified by the above code in a way visible to the compiler, but we mark them as clobbers anyway so that GCC won't put any of the input or output operands in diff -urN linux-2.5.2-pre8/arch/arm/kernel/head-armo.S linux/arch/arm/kernel/head-armo.S --- linux-2.5.2-pre8/arch/arm/kernel/head-armo.S Thu Apr 12 12:20:31 2001 +++ linux/arch/arm/kernel/head-armo.S Wed Dec 31 16:00:00 1969 @@ -1,92 +0,0 @@ -/* - * linux/arch/arm/kernel/head-armo.S - * - * Copyright (C) 1994-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * 26-bit kernel startup code - */ -#include -#include -#include - - .globl SYMBOL_NAME(swapper_pg_dir) - .equ SYMBOL_NAME(swapper_pg_dir), 0x0207d000 - -/* - * Entry point. - */ - .section ".text.init",#alloc,#execinstr -ENTRY(stext) -__entry: cmp pc, #0x02000000 - ldrlt pc, LC0 @ if 0x01800000, call at 0x02080000 - teq r0, #0 @ Check for old calling method - blne oldparams @ Move page if old - adr r0, LC0 - ldmib r0, {r2-r5, sp} @ Setup stack - mov r0, #0 -1: cmp r2, r3 @ Clear BSS - strcc r0, [r2], #4 - bcc 1b - - bl detect_proc_type - str r0, [r4] - bl detect_arch_type - str r0, [r5] - - mov fp, #0 - b SYMBOL_NAME(start_kernel) - -LC0: .word SYMBOL_NAME(_stext) - .word SYMBOL_NAME(__bss_start) @ r2 - .word SYMBOL_NAME(_end) @ r3 - .word SYMBOL_NAME(processor_id) @ r4 - .word SYMBOL_NAME(__machine_arch_type) @ r5 - .word SYMBOL_NAME(init_task_union)+8192 @ sp -arm2_id: .long 0x41560200 -arm250_id: .long 0x41560250 - .align - -oldparams: mov r4, #0x02000000 - add r3, r4, #0x00080000 - add r4, r4, #0x0007c000 -1: ldmia r0!, {r5 - r12} - stmia r4!, {r5 - r12} - cmp r4, r3 - blt 1b - mov pc, lr - -/* - * We need some way to automatically detect the difference between - * these two machines. Unfortunately, it is not possible to detect - * the presence of the SuperIO chip, because that will hang the old - * Archimedes machines solid. - */ -/* DAG: Outdated, these have been combined !!!!!!! */ -detect_arch_type: -#if defined(CONFIG_ARCH_ARC) - mov r0, #MACH_TYPE_ARCHIMEDES -#elif defined(CONFIG_ARCH_A5K) - mov r0, #MACH_TYPE_A5K -#endif - mov pc, lr - -detect_proc_type: - mov ip, lr - mov r2, #0xea000000 @ Point undef instr to continuation - adr r0, continue - 12 - orr r0, r2, r0, lsr #2 - mov r1, #0 - str r0, [r1, #4] - ldr r0, arm2_id - swp r2, r2, [r1] @ check for swp (ARM2 cant) - ldr r0, arm250_id - mrc 15, 0, r3, c0, c0 @ check for CP#15 (ARM250 cant) - mov r0, r3 -continue: mov r2, #0xeb000000 @ Make undef vector loop - sub r2, r2, #2 - str r2, [r1, #4] - mov pc, ip diff -urN linux-2.5.2-pre8/arch/arm/kernel/init_task.c linux/arch/arm/kernel/init_task.c --- linux-2.5.2-pre8/arch/arm/kernel/init_task.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/kernel/init_task.c Sat Jan 5 14:43:15 2002 @@ -9,7 +9,6 @@ #include #include -static struct vm_area_struct init_mmap = INIT_MMAP; static struct fs_struct init_fs = INIT_FS; static struct files_struct init_files = INIT_FILES; static struct signal_struct init_signals = INIT_SIGNALS; diff -urN linux-2.5.2-pre8/arch/arm/kernel/irq.c linux/arch/arm/kernel/irq.c --- linux-2.5.2-pre8/arch/arm/kernel/irq.c Wed Nov 28 13:22:25 2001 +++ linux/arch/arm/kernel/irq.c Sat Jan 5 14:43:15 2002 @@ -114,7 +114,7 @@ } #ifdef CONFIG_ARCH_ACORN - show_fiq_list(p); + show_fiq_list(p, v); #endif seq_printf(p, "Err: %10lu\n", irq_err_count); return 0; diff -urN linux-2.5.2-pre8/arch/arm/kernel/oldlatches.c linux/arch/arm/kernel/oldlatches.c --- linux-2.5.2-pre8/arch/arm/kernel/oldlatches.c Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/kernel/oldlatches.c Wed Dec 31 16:00:00 1969 @@ -1,72 +0,0 @@ -/* - * linux/arch/arm/kernel/oldlatches.c - * - * Copyright (C) David Alan Gilbert 1995/1996,2000 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Support for the latches on the old Archimedes which control the floppy, - * hard disc and printer - */ -#include -#include -#include -#include - -#include -#include -#include -#include - -static unsigned char latch_a_copy; -static unsigned char latch_b_copy; - -/* newval=(oldval & ~mask)|newdata */ -void oldlatch_aupdate(unsigned char mask,unsigned char newdata) -{ - if (machine_is_archimedes()) { - unsigned long flags; - - local_save_flags(flags); - latch_a_copy = (latch_a_copy & ~mask) | newdata; - __raw_writeb(latch_a_copy, LATCHA_BASE); - local_restore_flags(flags); - - printk("Latch: A = 0x%02x\n", latch_a_copy); - } else - BUG(); -} - - -/* newval=(oldval & ~mask)|newdata */ -void oldlatch_bupdate(unsigned char mask,unsigned char newdata) -{ - if (machine_is_archimedes()) { - unsigned long flags; - - local_save_flags(flags); - latch_b_copy = (latch_b_copy & ~mask) | newdata; - __raw_writeb(latch_b_copy, LATCHB_BASE); - local_restore_flags(flags); - - printk("Latch: B = 0x%02x\n", latch_b_copy); - } else - BUG(); -} - -static int __init oldlatch_init(void) -{ - if (machine_is_archimedes()) { - oldlatch_aupdate(0xff, 0xff); - /* Thats no FDC reset...*/ - oldlatch_bupdate(0xff, LATCHB_FDCRESET); - } - return 0; -} - -__initcall(oldlatch_init); - -EXPORT_SYMBOL(oldlatch_aupdate); -EXPORT_SYMBOL(oldlatch_bupdate); diff -urN linux-2.5.2-pre8/arch/arm/kernel/process.c linux/arch/arm/kernel/process.c --- linux-2.5.2-pre8/arch/arm/kernel/process.c Sat Jan 5 14:43:12 2002 +++ linux/arch/arm/kernel/process.c Sat Jan 5 14:43:15 2002 @@ -172,10 +172,10 @@ regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); printk("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', - flags & CC_V_BIT ? 'V' : 'v'); + flags & PSR_N_BIT ? 'N' : 'n', + flags & PSR_Z_BIT ? 'Z' : 'z', + flags & PSR_C_BIT ? 'C' : 'c', + flags & PSR_V_BIT ? 'V' : 'v'); printk(" IRQs %s FIQs %s Mode %s%s Segment %s\n", interrupts_enabled(regs) ? "on" : "off", fast_interrupts_enabled(regs) ? "on" : "off", diff -urN linux-2.5.2-pre8/arch/arm/kernel/semaphore.c linux/arch/arm/kernel/semaphore.c --- linux-2.5.2-pre8/arch/arm/kernel/semaphore.c Fri Apr 27 14:11:59 2001 +++ linux/arch/arm/kernel/semaphore.c Sat Jan 5 14:43:15 2002 @@ -177,8 +177,7 @@ * value in some cases.. */ #ifdef CONFIG_CPU_26 -asm(" .section .text.lock, \"ax\" - .align 5 +asm(" .align 5 .globl __down_failed __down_failed: stmfd sp!, {r0 - r3, lr} @@ -211,14 +210,11 @@ mov r0, ip bl __up ldmfd sp!, {r0 - r3, pc}^ - - .previous "); #else /* 32 bit version */ -asm(" .section .text.lock, \"ax\" - .align 5 +asm(" .align 5 .globl __down_failed __down_failed: stmfd sp!, {r0 - r3, lr} @@ -251,8 +247,6 @@ mov r0, ip bl __up ldmfd sp!, {r0 - r3, pc} - - .previous "); #endif diff -urN linux-2.5.2-pre8/arch/arm/kernel/setup.c linux/arch/arm/kernel/setup.c --- linux-2.5.2-pre8/arch/arm/kernel/setup.c Fri Nov 16 10:07:47 2001 +++ linux/arch/arm/kernel/setup.c Sat Jan 5 14:43:15 2002 @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -105,6 +106,109 @@ #define lp1 io_res[1] #define lp2 io_res[2] +#ifdef CONFIG_CPU_32 +static const char *cache_types[16] = { + "write-through", + "write-back", + "write-back", + "undefined 3", + "undefined 4", + "undefined 5", + "write-back", + "write-back", + "undefined 8", + "undefined 9", + "undefined 10", + "undefined 11", + "undefined 12", + "undefined 13", + "undefined 14", + "undefined 15", +}; + +static const char *cache_clean[16] = { + "not required", + "read-block", + "cp15 c7 ops", + "undefined 3", + "undefined 4", + "undefined 5", + "cp15 c7 ops", + "cp15 c7 ops", + "undefined 8", + "undefined 9", + "undefined 10", + "undefined 11", + "undefined 12", + "undefined 13", + "undefined 14", + "undefined 15", +}; + +static const char *cache_lockdown[16] = { + "not supported", + "not supported", + "not supported", + "undefined 3", + "undefined 4", + "undefined 5", + "format A", + "format B", + "undefined 8", + "undefined 9", + "undefined 10", + "undefined 11", + "undefined 12", + "undefined 13", + "undefined 14", + "undefined 15", +}; + +#define CACHE_TYPE(x) (((x) >> 25) & 15) +#define CACHE_S(x) ((x) & (1 << 24)) +#define CACHE_DSIZE(x) (((x) >> 12) & 4095) /* only if S=1 */ +#define CACHE_ISIZE(x) ((x) & 4095) + +#define CACHE_SIZE(y) (((y) >> 6) & 7) +#define CACHE_ASSOC(y) (((y) >> 3) & 7) +#define CACHE_M(y) ((y) & (1 << 2)) +#define CACHE_LINE(y) ((y) & 3) + +static inline void dump_cache(const char *prefix, unsigned int cache) +{ + unsigned int mult = 2 + CACHE_M(cache) ? 1 : 0; + + printk("%s size %dK associativity %d line length %d sets %d\n", + prefix, + mult << (8 + CACHE_SIZE(cache)), + (mult << CACHE_ASSOC(cache)) >> 1, + 8 << CACHE_LINE(cache), + 1 << (6 + CACHE_SIZE(cache) - CACHE_ASSOC(cache) - + CACHE_LINE(cache))); +} + +static inline void dump_cpu_cache_id(void) +{ + unsigned int cache_info; + + asm("mrc p15, 0, %0, c0, c0, 1" : "=r" (cache_info)); + + if (cache_info == processor_id) + return; + + printk("CPU: D %s cache\n", cache_types[CACHE_TYPE(cache_info)]); + if (CACHE_S(cache_info)) { + dump_cache("CPU: I cache", CACHE_ISIZE(cache_info)); + dump_cache("CPU: D cache", CACHE_DSIZE(cache_info)); + } else { + dump_cache("CPU: cache", CACHE_ISIZE(cache_info)); + } +} + +#else +#define dump_cpu_cache_id() do { } while (0) +#endif + static void __init setup_processor(void) { extern struct proc_info_list __proc_info_begin, __proc_info_end; @@ -139,6 +243,8 @@ proc_info.manufacturer, proc_info.cpu_name, (int)processor_id & 15); + dump_cpu_cache_id(); + sprintf(system_utsname.machine, "%s%c", list->arch_name, ENDIANNESS); sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS); elf_hwcap = list->elf_hwcap; @@ -146,7 +252,7 @@ cpu_proc_init(); } -static struct machine_desc * __init setup_architecture(unsigned int nr) +static struct machine_desc * __init setup_machine(unsigned int nr) { extern struct machine_desc __arch_info_begin, __arch_info_end; struct machine_desc *list; @@ -168,7 +274,7 @@ while (1); } - printk("Architecture: %s\n", list->name); + printk("Machine: %s\n", list->name); if (compat) printk(KERN_WARNING "Using compatibility code " "scheduled for removal in v%d.%d.%d\n", @@ -231,7 +337,7 @@ setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz) { #ifdef CONFIG_BLK_DEV_RAM - extern int rd_size; + extern int rd_size, rd_image_start, rd_prompt, rd_doload; rd_image_start = image_start; rd_prompt = prompt; @@ -458,10 +564,10 @@ struct machine_desc *mdesc; char *from = default_command_line; - ROOT_DEV = MKDEV(0, 255); + ROOT_DEV = mk_kdev(0, 255); setup_processor(); - mdesc = setup_architecture(machine_arch_type); + mdesc = setup_machine(machine_arch_type); machine_name = mdesc->name; if (mdesc->soft_reboot) @@ -533,6 +639,41 @@ NULL }; +static const char *proc_arch[16] = { + "undefined 0", + "4", + "4T", + "5", + "5T", + "5TE", + "undefined 6", + "undefined 7", + "undefined 8", + "undefined 9", + "undefined 10", + "undefined 11", + "undefined 12", + "undefined 13", + "undefined 14", + "undefined 15" +}; + +static void +c_show_cache(struct seq_file *m, const char *type, unsigned int cache) +{ + unsigned int mult = 2 + CACHE_M(cache) ? 1 : 0; + + seq_printf(m, "%s size\t\t: %d\n" + "%s assoc\t\t: %d\n" + "%s line length\t: %d\n" + "%s sets\t\t: %d\n", + type, mult << (8 + CACHE_SIZE(cache)), + type, (mult << CACHE_ASSOC(cache)) >> 1, + type, 8 << CACHE_LINE(cache), + type, 1 << (6 + CACHE_SIZE(cache) - CACHE_ASSOC(cache) - + CACHE_LINE(cache))); +} + static int c_show(struct seq_file *m, void *v) { int i; @@ -552,7 +693,60 @@ if (elf_hwcap & (1 << i)) seq_printf(m, "%s ", hwcap_str[i]); - seq_puts(m, "\n\n"); + seq_puts(m, "\n"); + + if ((processor_id & 0x0000f000) == 0x00000000) { + /* pre-ARM7 */ + seq_printf(m, "CPU part\t\t: %07x\n", processor_id >> 4); + } else if ((processor_id & 0x0000f000) == 0x00007000) { + /* ARM7 */ + seq_printf(m, "CPU implementor\t: 0x%02x\n" + "CPU architecture: %s\n" + "CPU variant\t: 0x%02x\n" + "CPU part\t: 0x%03x\n", + processor_id >> 24, + processor_id & (1 << 23) ? "4T" : "3", + (processor_id >> 16) & 127, + (processor_id >> 4) & 0xfff); + } else { + /* post-ARM7 */ + seq_printf(m, "CPU implementor\t: 0x%02x\n" + "CPU architecture: %s\n" + "CPU variant\t: 0x%x\n" + "CPU part\t: 0x%03x\n", + processor_id >> 24, + proc_arch[(processor_id >> 16) & 15], + (processor_id >> 20) & 15, + (processor_id >> 4) & 0xfff); + } + seq_printf(m, "CPU revision\t: %d\n", processor_id & 15); + +#ifdef CONFIG_CPU_32 + { + unsigned int cache_info; + + asm("mrc p15, 0, %0, c0, c0, 1" : "=r" (cache_info)); + if (cache_info != processor_id) { + seq_printf(m, "Cache type\t: %s\n" + "Cache clean\t: %s\n" + "Cache lockdown\t: %s\n" + "Cache unified\t: %s\n", + cache_types[CACHE_TYPE(cache_info)], + cache_clean[CACHE_TYPE(cache_info)], + cache_lockdown[CACHE_TYPE(cache_info)], + CACHE_S(cache_info) ? "separate I,D" : "unified"); + + if (CACHE_S(cache_info)) { + c_show_cache(m, "I", CACHE_ISIZE(cache_info)); + c_show_cache(m, "D", CACHE_DSIZE(cache_info)); + } else { + c_show_cache(m, "Cache", CACHE_ISIZE(cache_info)); + } + } + } +#endif + + seq_puts(m, "\n"); seq_printf(m, "Hardware\t: %s\n", machine_name); seq_printf(m, "Revision\t: %04x\n", system_rev); diff -urN linux-2.5.2-pre8/arch/arm/kernel/signal.c linux/arch/arm/kernel/signal.c --- linux-2.5.2-pre8/arch/arm/kernel/signal.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/kernel/signal.c Sat Jan 5 14:43:15 2002 @@ -344,7 +344,7 @@ /* * This is the X/Open sanctioned signal stack switching. */ - if ((ka->sa.sa_flags & SA_ONSTACK) && sas_ss_flags(sp)) + if ((ka->sa.sa_flags & SA_ONSTACK) && !sas_ss_flags(sp)) sp = current->sas_ss_sp + current->sas_ss_size; /* @@ -378,9 +378,9 @@ thumb = handler & 1; if (thumb) - cpsr |= T_BIT; + cpsr |= PSR_T_BIT; else - cpsr &= ~T_BIT; + cpsr &= ~PSR_T_BIT; } #endif #endif diff -urN linux-2.5.2-pre8/arch/arm/kernel/time.c linux/arch/arm/kernel/time.c --- linux-2.5.2-pre8/arch/arm/kernel/time.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/kernel/time.c Sat Jan 5 14:43:15 2002 @@ -2,7 +2,7 @@ * linux/arch/arm/kernel/time.c * * Copyright (C) 1991, 1992, 1995 Linus Torvalds - * Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King + * Modifications for ARM (C) 1994-2001 Russell King * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -24,13 +24,12 @@ #include #include #include +#include -#include +#include #include #include - -#include -#include +#include extern int setup_arm_irq(int, struct irqaction *); extern rwlock_t xtime_lock; @@ -122,18 +121,14 @@ #ifdef CONFIG_LEDS -#include - static void dummy_leds_event(led_event_t evt) { } void (*leds_event)(led_event_t) = dummy_leds_event; -#ifdef CONFIG_MODULES EXPORT_SYMBOL(leds_event); #endif -#endif #ifdef CONFIG_LEDS_TIMER static void do_leds(void) @@ -152,16 +147,15 @@ void do_gettimeofday(struct timeval *tv) { unsigned long flags; - unsigned long usec, sec; + unsigned long usec, sec, lost; read_lock_irqsave(&xtime_lock, flags); usec = gettimeoffset(); - { - unsigned long lost = jiffies - wall_jiffies; - if (lost) - usec += lost * USECS_PER_JIFFY; - } + lost = jiffies - wall_jiffies; + if (lost) + usec += lost * USECS_PER_JIFFY; + sec = xtime.tv_sec; usec += xtime.tv_usec; read_unlock_irqrestore(&xtime_lock, flags); @@ -179,11 +173,11 @@ void do_settimeofday(struct timeval *tv) { write_lock_irq(&xtime_lock); - /* This is revolting. We need to set the xtime.tv_usec - * correctly. However, the value in this location is - * is value at the last tick. - * Discover what correction gettimeofday - * would have done, and then undo it! + /* + * This is revolting. We need to set "xtime" correctly. However, the + * value in this location is the value at the most recent update of + * wall time. Discover what correction gettimeofday() would have + * done, and then undo it! */ tv->tv_usec -= gettimeoffset(); tv->tv_usec -= (jiffies - wall_jiffies) * USECS_PER_JIFFY; @@ -209,17 +203,3 @@ * Include architecture specific code */ #include - -/* - * This must cause the timer to start ticking. - * It doesn't have to set the current time though - * from an RTC - it can be done later once we have - * some buses initialised. - */ -void __init time_init(void) -{ - xtime.tv_usec = 0; - xtime.tv_sec = 0; - - setup_timer(); -} diff -urN linux-2.5.2-pre8/arch/arm/kernel/traps.c linux/arch/arm/kernel/traps.c --- linux-2.5.2-pre8/arch/arm/kernel/traps.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/kernel/traps.c Sat Jan 5 14:43:15 2002 @@ -53,7 +53,7 @@ */ static int verify_stack(unsigned long sp) { - if (sp < PAGE_OFFSET || sp > (unsigned long)high_memory) + if (sp < PAGE_OFFSET || (sp > (unsigned long)high_memory && high_memory != 0)) return -EFAULT; return 0; @@ -62,13 +62,16 @@ /* * Dump out the contents of some memory nicely... */ -void dump_mem(unsigned long bottom, unsigned long top) +static void dump_mem(const char *str, unsigned long bottom, unsigned long top) { unsigned long p = bottom & ~31; int i; + printk("%s", str); + printk("(0x%08lx to 0x%08lx)\n", bottom, top); + for (p = bottom & ~31; p < top;) { - printk("%08lx: ", p); + printk("%04lx: ", p & 0xffff); for (i = 0; i < 8; i++, p += 4) { unsigned int val; @@ -79,21 +82,11 @@ __get_user(val, (unsigned long *)p); printk("%08x ", val); } - if (i == 3) - printk(" "); } printk ("\n"); } } -/* - * These constants are for searching for possible module text - * segments. VMALLOC_OFFSET comes from mm/vmalloc.c; MODULE_RANGE is - * a guess of how much space is likely to be vmalloced. - */ -#define VMALLOC_OFFSET (8*1024*1024) -#define MODULE_RANGE (8*1024*1024) - static void dump_instr(struct pt_regs *regs) { unsigned long addr = instruction_pointer(regs); @@ -122,8 +115,7 @@ static void dump_stack(struct task_struct *tsk, unsigned long sp) { - printk("Stack:\n"); - dump_mem(sp - 16, 8192+(unsigned long)tsk); + dump_mem("Stack: ", sp - 16, 8192+(unsigned long)tsk); } static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) @@ -289,10 +281,9 @@ handler[reason], processor_modes[proc_mode]); /* - * We need to switch to kernel mode so that we can - * use __get_user to safely read from kernel space. - * Note that we now dump the code first, just in case - * the backtrace kills us. + * We need to switch to kernel mode so that we can use __get_user + * to safely read from kernel space. Note that we now dump the + * code first, just in case the backtrace kills us. */ fs = get_fs(); set_fs(KERNEL_DS); @@ -301,10 +292,8 @@ * Dump out the vectors and stub routines. Maybe a better solution * would be to dump them out only if we detect that they are corrupted. */ - printk(KERN_CRIT "Vectors:\n"); - dump_mem(vectors, 0x40); - printk(KERN_CRIT "Stubs:\n"); - dump_mem(vectors + 0x200, 0x4b8); + dump_mem(KERN_CRIT "Vectors: ", vectors, vectors + 0x40); + dump_mem(KERN_CRIT "Stubs: ", vectors + 0x200, vectors + 0x4b8); set_fs(fs); @@ -528,11 +517,6 @@ void abort(void) { - void *lr = __builtin_return_address(0); - - printk(KERN_CRIT "abort() called from %p! (Please " - "report to rmk@arm.linux.org.uk)\n", lr); - BUG(); /* if that doesn't kill us, halt */ diff -urN linux-2.5.2-pre8/arch/arm/lib/Makefile linux/arch/arm/lib/Makefile --- linux-2.5.2-pre8/arch/arm/lib/Makefile Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/lib/Makefile Sat Jan 5 14:43:15 2002 @@ -43,9 +43,9 @@ obj-$(v4) += io-readsw-armv4.o io-writesw-armv4.o io-readsl-armv4.o obj-y += io-writesl.o -ifeq ($(PROCESSOR),armo) - obj-y += uaccess-armo.o -endif +obj-$(CONFIG_CPU_26) += uaccess-armo.o +obj-$(CONFIG_CPU_32) += copy_page-armv3.o copy_page-armv4.o copy_page-armv4mc.o +obj-$(CONFIG_CPU_32v5) += copy_page-armv5te.o include $(TOPDIR)/Rules.make diff -urN linux-2.5.2-pre8/arch/arm/lib/copy_page-armv3.S linux/arch/arm/lib/copy_page-armv3.S --- linux-2.5.2-pre8/arch/arm/lib/copy_page-armv3.S Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/lib/copy_page-armv3.S Sat Jan 5 14:43:15 2002 @@ -0,0 +1,59 @@ +/* + * linux/arch/arm/lib/copypage.S + * + * Copyright (C) 1995-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASM optimised string functions + */ +#include +#include +#include + + .text + .align 5 +/* + * ARMv3 optimised copy_user_page + * + * FIXME: do we need to handle cache stuff... + */ +ENTRY(armv3_copy_user_page) + stmfd sp!, {r4, lr} @ 2 + mov r2, #PAGE_SZ/64 @ 1 + ldmia r1!, {r3, r4, ip, lr} @ 4+1 +1: stmia r0!, {r3, r4, ip, lr} @ 4 + ldmia r1!, {r3, r4, ip, lr} @ 4+1 + stmia r0!, {r3, r4, ip, lr} @ 4 + ldmia r1!, {r3, r4, ip, lr} @ 4+1 + stmia r0!, {r3, r4, ip, lr} @ 4 + ldmia r1!, {r3, r4, ip, lr} @ 4 + subs r2, r2, #1 @ 1 + stmia r0!, {r3, r4, ip, lr} @ 4 + ldmneia r1!, {r3, r4, ip, lr} @ 4 + bne 1b @ 1 + LOADREGS(fd, sp!, {r4, pc}) @ 3 + + .align 5 +/* + * ARMv3 optimised clear_user_page + * + * FIXME: do we need to handle cache stuff... + */ +ENTRY(armv3_clear_user_page) + str lr, [sp, #-4]! + mov r1, #PAGE_SZ/64 @ 1 + mov r2, #0 @ 1 + mov r3, #0 @ 1 + mov ip, #0 @ 1 + mov lr, #0 @ 1 +1: stmia r0!, {r2, r3, ip, lr} @ 4 + stmia r0!, {r2, r3, ip, lr} @ 4 + stmia r0!, {r2, r3, ip, lr} @ 4 + stmia r0!, {r2, r3, ip, lr} @ 4 + subs r1, r1, #1 @ 1 + bne 1b @ 1 + ldr pc, [sp], #4 + diff -urN linux-2.5.2-pre8/arch/arm/lib/copy_page-armv4.S linux/arch/arm/lib/copy_page-armv4.S --- linux-2.5.2-pre8/arch/arm/lib/copy_page-armv4.S Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/lib/copy_page-armv4.S Sat Jan 5 14:43:15 2002 @@ -0,0 +1,70 @@ +/* + * linux/arch/arm/lib/copypage.S + * + * Copyright (C) 1995-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASM optimised string functions + */ +#include +#include + + .text + .align 5 +/* + * ARMv4 optimised copy_user_page + * + * We flush the destination cache lines just before we write the data into the + * corresponding address. Since the Dcache is read-allocate, this removes the + * Dcache aliasing issue. The writes will be forwarded to the write buffer, + * and merged as appropriate. + * + * Note: We rely on all ARMv4 processors implementing the "invalidate D line" + * instruction. If your processor does not supply this, you have to write your + * own copy_user_page that does the right thing. + */ +ENTRY(armv4_copy_user_page) + stmfd sp!, {r4, lr} @ 2 + mov r2, #PAGE_SZ/64 @ 1 + ldmia r1!, {r3, r4, ip, lr} @ 4 +1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line + stmia r0!, {r3, r4, ip, lr} @ 4 + ldmia r1!, {r3, r4, ip, lr} @ 4+1 + stmia r0!, {r3, r4, ip, lr} @ 4 + ldmia r1!, {r3, r4, ip, lr} @ 4 + mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line + stmia r0!, {r3, r4, ip, lr} @ 4 + ldmia r1!, {r3, r4, ip, lr} @ 4 + subs r2, r2, #1 @ 1 + stmia r0!, {r3, r4, ip, lr} @ 4 + ldmneia r1!, {r3, r4, ip, lr} @ 4 + bne 1b @ 1 + mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB + ldmfd sp!, {r4, pc} @ 3 + + .align 5 +/* + * ARMv4 optimised clear_user_page + * + * Same story as above. + */ +ENTRY(armv4_clear_user_page) + str lr, [sp, #-4]! + mov r1, #PAGE_SZ/64 @ 1 + mov r2, #0 @ 1 + mov r3, #0 @ 1 + mov ip, #0 @ 1 + mov lr, #0 @ 1 +1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line + stmia r0!, {r2, r3, ip, lr} @ 4 + stmia r0!, {r2, r3, ip, lr} @ 4 + mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line + stmia r0!, {r2, r3, ip, lr} @ 4 + stmia r0!, {r2, r3, ip, lr} @ 4 + subs r1, r1, #1 @ 1 + bne 1b @ 1 + mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB + ldr pc, [sp], #4 diff -urN linux-2.5.2-pre8/arch/arm/lib/copy_page-armv4mc.S linux/arch/arm/lib/copy_page-armv4mc.S --- linux-2.5.2-pre8/arch/arm/lib/copy_page-armv4mc.S Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/lib/copy_page-armv4mc.S Sat Jan 5 14:43:15 2002 @@ -0,0 +1,71 @@ +/* + * linux/arch/arm/lib/copy_page-armv4mc.S + * + * Copyright (C) 1995-2001 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASM optimised string functions + */ +#include +#include + + .text + .align 5 +/* + * ARMv4 mini-dcache optimised copy_user_page + * + * We flush the destination cache lines just before we write the data into the + * corresponding address. Since the Dcache is read-allocate, this removes the + * Dcache aliasing issue. The writes will be forwarded to the write buffer, + * and merged as appropriate. + * + * Note: We rely on all ARMv4 processors implementing the "invalidate D line" + * instruction. If your processor does not supply this, you have to write your + * own copy_user_page that does the right thing. + */ +ENTRY(armv4_mc_copy_user_page) + stmfd sp!, {r4, lr} @ 2 + mov r4, r0 + mov r0, r1 + bl map_page_minicache + mov r1, #PAGE_SZ/64 @ 1 + ldmia r0!, {r2, r3, ip, lr} @ 4 +1: mcr p15, 0, r4, c7, c6, 1 @ 1 invalidate D line + stmia r4!, {r2, r3, ip, lr} @ 4 + ldmia r0!, {r2, r3, ip, lr} @ 4+1 + stmia r4!, {r2, r3, ip, lr} @ 4 + ldmia r0!, {r2, r3, ip, lr} @ 4 + mcr p15, 0, r4, c7, c6, 1 @ 1 invalidate D line + stmia r4!, {r2, r3, ip, lr} @ 4 + ldmia r0!, {r2, r3, ip, lr} @ 4 + subs r1, r1, #1 @ 1 + stmia r4!, {r2, r3, ip, lr} @ 4 + ldmneia r0!, {r2, r3, ip, lr} @ 4 + bne 1b @ 1 + ldmfd sp!, {r4, pc} @ 3 + + .align 5 +/* + * ARMv4 optimised clear_user_page + * + * Same story as above. + */ +ENTRY(armv4_mc_clear_user_page) + str lr, [sp, #-4]! + mov r1, #PAGE_SZ/64 @ 1 + mov r2, #0 @ 1 + mov r3, #0 @ 1 + mov ip, #0 @ 1 + mov lr, #0 @ 1 +1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line + stmia r0!, {r2, r3, ip, lr} @ 4 + stmia r0!, {r2, r3, ip, lr} @ 4 + mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line + stmia r0!, {r2, r3, ip, lr} @ 4 + stmia r0!, {r2, r3, ip, lr} @ 4 + subs r1, r1, #1 @ 1 + bne 1b @ 1 + ldr pc, [sp], #4 diff -urN linux-2.5.2-pre8/arch/arm/lib/copy_page-armv5te.S linux/arch/arm/lib/copy_page-armv5te.S --- linux-2.5.2-pre8/arch/arm/lib/copy_page-armv5te.S Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/lib/copy_page-armv5te.S Sat Jan 5 14:43:15 2002 @@ -0,0 +1,79 @@ +/* + * linux/arch/arm/lib/copypage-armv5te.S + * + * Copyright (C) 2001 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include + +/* + * General note: + * We don't really want write-allocate cache behaviour for these functions + * since that will just eat through 8K of the cache. + */ + + .text + .align 5 +/* + * ARMv5TE optimised copy_user_page + * r0 = destination + * r1 = source + * r2 = virtual user address of ultimate destination page + * + * The source page may have some clean entries in the cache already, but we + * can safely ignore them - break_cow() will flush them out of the cache + * if we eventually end up using our copied page. + * + * What we could do is use the mini-cache to buffer reads from the source + * page. We rely on the mini-cache being smaller than one page, so we'll + * cycle through the complete cache anyway. + */ +ENTRY(armv5te_copy_user_page) + stmfd sp!, {r4, r5, lr} + mov r5, r0 + mov r0, r1 + bl map_page_minicache + mov r1, r5 + mov lr, #PAGE_SZ/32 + +1: mov ip, r1 + ldrd r2, [r0], #8 + ldrd r4, [r0], #8 + strd r2, [r1], #8 + ldrd r2, [r0], #8 + strd r4, [r1], #8 + ldrd r4, [r0], #8 + strd r2, [r1], #8 + strd r4, [r1], #8 + mcr p15, 0, ip, c7, c10, 1 @ clean D line + mcr p15, 0, ip, c7, c6, 1 @ invalidate D line + subs lr, lr, #1 + bne 1b + + ldmfd sp!, {r4, r5, pc} + + .align 5 +/* + * ARMv5TE optimised clear_user_page + * r0 = destination + * r1 = virtual user address of ultimate destination page + */ +ENTRY(armv5te_clear_user_page) + str lr, [sp, #-4]! + mov r1, #PAGE_SZ/32 + mov r2, #0 + mov r3, #0 +1: mov ip, r0 + strd r2, [r0], #8 + strd r2, [r0], #8 + strd r2, [r0], #8 + strd r2, [r0], #8 + mcr p15, 0, ip, c7, c10, 1 @ clean D line + mcr p15, 0, ip, c7, c6, 1 @ invalidate D line + subs r1, r1, #1 + bne 1b + ldr pc, [sp], #4 diff -urN linux-2.5.2-pre8/arch/arm/lib/delay.S linux/arch/arm/lib/delay.S --- linux-2.5.2-pre8/arch/arm/lib/delay.S Thu Apr 12 12:20:31 2001 +++ linux/arch/arm/lib/delay.S Sat Jan 5 14:43:15 2002 @@ -29,25 +29,29 @@ RETINSTR(moveq,pc,lr) /* - * loops = (r0 * 0x10c6 * 100 * loops_per_jiffie) / 2^32 + * loops = (r0 * 0x10c6 * 100 * loops_per_jiffy) / 2^32 + * + * Oh, if only we had a cycle counter... */ @ Delay routine ENTRY(__delay) subs r0, r0, #1 - RETINSTR(movcc,pc,lr) +#if 0 + RETINSTR(movls,pc,lr) subs r0, r0, #1 - RETINSTR(movcc,pc,lr) + RETINSTR(movls,pc,lr) subs r0, r0, #1 - RETINSTR(movcc,pc,lr) + RETINSTR(movls,pc,lr) subs r0, r0, #1 - RETINSTR(movcc,pc,lr) + RETINSTR(movls,pc,lr) subs r0, r0, #1 - RETINSTR(movcc,pc,lr) + RETINSTR(movls,pc,lr) subs r0, r0, #1 - RETINSTR(movcc,pc,lr) + RETINSTR(movls,pc,lr) subs r0, r0, #1 - RETINSTR(movcc,pc,lr) + RETINSTR(movls,pc,lr) subs r0, r0, #1 - bcs SYMBOL_NAME(__delay) +#endif + bhi SYMBOL_NAME(__delay) RETINSTR(mov,pc,lr) diff -urN linux-2.5.2-pre8/arch/arm/lib/getuser.S linux/arch/arm/lib/getuser.S --- linux-2.5.2-pre8/arch/arm/lib/getuser.S Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/lib/getuser.S Sat Jan 5 14:43:15 2002 @@ -49,7 +49,11 @@ cmp r0, r2 2: ldrlsbt r1, [r0], #1 3: ldrlsbt r2, [r0] +#ifndef __ARMEB__ orrls r1, r1, r2, lsl #8 +#else + orrls r1, r2, r1, lsl #8 +#endif movls r0, #0 movls pc, lr b __get_user_bad @@ -80,8 +84,9 @@ /* fall through */ -__get_user_bad: +__get_user_bad_8: mov r2, #0 +__get_user_bad: mov r1, #0 mov r0, #-14 mov pc, lr @@ -91,6 +96,6 @@ .long 2b, __get_user_bad .long 3b, __get_user_bad .long 4b, __get_user_bad - .long 5b, __get_user_bad - .long 6b, __get_user_bad + .long 5b, __get_user_bad_8 + .long 6b, __get_user_bad_8 .previous diff -urN linux-2.5.2-pre8/arch/arm/lib/io-shark.c linux/arch/arm/lib/io-shark.c --- linux-2.5.2-pre8/arch/arm/lib/io-shark.c Thu Apr 12 12:20:31 2001 +++ linux/arch/arm/lib/io-shark.c Sat Jan 5 14:43:15 2002 @@ -1,7 +1,7 @@ /* * linux/arch/arm/lib/io-shark.c * - * by Alexander Schulz + * by Alexander Schulz * * derived from: * linux/arch/arm/lib/io-ebsa.S diff -urN linux-2.5.2-pre8/arch/arm/lib/memcpy.S linux/arch/arm/lib/memcpy.S --- linux-2.5.2-pre8/arch/arm/lib/memcpy.S Tue Mar 6 19:44:35 2001 +++ linux/arch/arm/lib/memcpy.S Sat Jan 5 14:43:15 2002 @@ -99,24 +99,24 @@ cmp r2, #12 blt 10f sub r2, r2, #12 -9: mov r3, r7, lsr #8 +9: mov r3, r7, pull #8 ldmia r1!, {r4 - r7} - orr r3, r3, r4, lsl #24 - mov r4, r4, lsr #8 - orr r4, r4, r5, lsl #24 - mov r5, r5, lsr #8 - orr r5, r5, r6, lsl #24 - mov r6, r6, lsr #8 - orr r6, r6, r7, lsl #24 + orr r3, r3, r4, push #24 + mov r4, r4, pull #8 + orr r4, r4, r5, push #24 + mov r5, r5, pull #8 + orr r5, r5, r6, push #24 + mov r6, r6, pull #8 + orr r6, r6, r7, push #24 stmia r0!, {r3 - r6} subs r2, r2, #16 bge 9b adds r2, r2, #12 blt 100f -10: mov r3, r7, lsr #8 +10: mov r3, r7, pull #8 ldr r7, [r1], #4 subs r2, r2, #4 - orr r3, r3, r7, lsl #24 + orr r3, r3, r7, push #24 str r3, [r0], #4 bge 10b 100: sub r1, r1, #3 @@ -125,24 +125,24 @@ 11: cmp r2, #12 blt 13f /* */ sub r2, r2, #12 -12: mov r3, r7, lsr #16 +12: mov r3, r7, pull #16 ldmia r1!, {r4 - r7} - orr r3, r3, r4, lsl #16 - mov r4, r4, lsr #16 - orr r4, r4, r5, lsl #16 - mov r5, r5, lsr #16 - orr r5, r5, r6, lsl #16 - mov r6, r6, lsr #16 - orr r6, r6, r7,LSL#16 + orr r3, r3, r4, push #16 + mov r4, r4, pull #16 + orr r4, r4, r5, push #16 + mov r5, r5, pull #16 + orr r5, r5, r6, push #16 + mov r6, r6, pull #16 + orr r6, r6, r7, push #16 stmia r0!, {r3 - r6} subs r2, r2, #16 bge 12b adds r2, r2, #12 blt 14f -13: mov r3, r7, lsr #16 +13: mov r3, r7, pull #16 ldr r7, [r1], #4 subs r2, r2, #4 - orr r3, r3, r7, lsl #16 + orr r3, r3, r7, push #16 str r3, [r0], #4 bge 13b 14: sub r1, r1, #2 @@ -151,24 +151,24 @@ 15: cmp r2, #12 blt 17f sub r2, r2, #12 -16: mov r3, r7, lsr #24 - ldmia r1!,{r4 - r7} - orr r3, r3, r4, lsl #8 - mov r4, r4, lsr #24 - orr r4, r4, r5, lsl #8 - mov r5, r5, lsr #24 - orr r5, r5, r6, lsl #8 - mov r6, r6, lsr #24 - orr r6, r6, r7, lsl #8 +16: mov r3, r7, pull #24 + ldmia r1!, {r4 - r7} + orr r3, r3, r4, push #8 + mov r4, r4, pull #24 + orr r4, r4, r5, push #8 + mov r5, r5, pull #24 + orr r5, r5, r6, push #8 + mov r6, r6, pull #24 + orr r6, r6, r7, push #8 stmia r0!, {r3 - r6} subs r2, r2, #16 bge 16b adds r2, r2, #12 blt 18f -17: mov r3, r7, lsr #24 +17: mov r3, r7, pull #24 ldr r7, [r1], #4 subs r2, r2, #4 - orr r3, r3, r7, lsl#8 + orr r3, r3, r7, push #8 str r3, [r0], #4 bge 17b 18: sub r1, r1, #1 @@ -240,24 +240,24 @@ cmp r2, #12 blt 28f sub r2, r2, #12 -27: mov r7, r3, lsl #8 +27: mov r7, r3, push #8 ldmdb r1!, {r3, r4, r5, r6} - orr r7, r7, r6, lsr #24 - mov r6, r6, lsl #8 - orr r6, r6, r5, lsr #24 - mov r5, r5, lsl #8 - orr r5, r5, r4, lsr #24 - mov r4, r4, lsl #8 - orr r4, r4, r3, lsr #24 + orr r7, r7, r6, pull #24 + mov r6, r6, push #8 + orr r6, r6, r5, pull #24 + mov r5, r5, push #8 + orr r5, r5, r4, pull #24 + mov r4, r4, push #8 + orr r4, r4, r3, pull #24 stmdb r0!, {r4, r5, r6, r7} subs r2, r2, #16 bge 27b adds r2, r2, #12 blt 29f -28: mov ip, r3, lsl #8 +28: mov ip, r3, push #8 ldr r3, [r1, #-4]! subs r2, r2, #4 - orr ip, ip, r3, lsr #24 + orr ip, ip, r3, pull #24 str ip, [r0, #-4]! bge 28b 29: add r1, r1, #3 @@ -266,24 +266,24 @@ 30: cmp r2, #12 blt 32f sub r2, r2, #12 -31: mov r7, r3, lsl #16 +31: mov r7, r3, push #16 ldmdb r1!, {r3, r4, r5, r6} - orr r7, r7, r6, lsr #16 - mov r6, r6, lsl #16 - orr r6, r6, r5, lsr #16 - mov r5, r5, lsl #16 - orr r5, r5, r4, lsr #16 - mov r4, r4, lsl #16 - orr r4, r4, r3, lsr #16 + orr r7, r7, r6, pull #16 + mov r6, r6, push #16 + orr r6, r6, r5, pull #16 + mov r5, r5, push #16 + orr r5, r5, r4, pull #16 + mov r4, r4, push #16 + orr r4, r4, r3, pull #16 stmdb r0!, {r4, r5, r6, r7} subs r2, r2, #16 bge 31b adds r2, r2, #12 blt 33f -32: mov ip, r3, lsl #16 +32: mov ip, r3, push #16 ldr r3, [r1, #-4]! subs r2, r2, #4 - orr ip, ip, r3, lsr #16 + orr ip, ip, r3, pull #16 str ip, [r0, #-4]! bge 32b 33: add r1, r1, #2 @@ -292,24 +292,24 @@ 34: cmp r2, #12 blt 36f sub r2, r2, #12 -35: mov r7, r3, lsl #24 +35: mov r7, r3, push #24 ldmdb r1!, {r3, r4, r5, r6} - orr r7, r7, r6, lsr #8 - mov r6, r6, lsl #24 - orr r6, r6, r5, lsr #8 - mov r5, r5, lsl #24 - orr r5, r5, r4, lsr #8 - mov r4, r4, lsl #24 - orr r4, r4, r3, lsr #8 + orr r7, r7, r6, pull #8 + mov r6, r6, push #24 + orr r6, r6, r5, pull #8 + mov r5, r5, push #24 + orr r5, r5, r4, pull #8 + mov r4, r4, push #24 + orr r4, r4, r3, pull #8 stmdb r0!, {r4, r5, r6, r7} subs r2, r2, #16 bge 35b adds r2, r2, #12 blt 37f -36: mov ip, r3, lsl #24 +36: mov ip, r3, push #24 ldr r3, [r1, #-4]! subs r2, r2, #4 - orr ip, ip, r3, lsr #8 + orr ip, ip, r3, pull #8 str ip, [r0, #-4]! bge 36b 37: add r1, r1, #1 diff -urN linux-2.5.2-pre8/arch/arm/lib/putuser.S linux/arch/arm/lib/putuser.S --- linux-2.5.2-pre8/arch/arm/lib/putuser.S Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/lib/putuser.S Sat Jan 5 14:43:15 2002 @@ -47,9 +47,14 @@ ldr r2, [r2, #TSK_ADDR_LIMIT] sub r2, r2, #2 cmp r0, r2 + movls r2, r1, lsr #8 +#ifndef __ARMEB__ 2: strlsbt r1, [r0], #1 - movls r1, r1, lsr #8 +3: strlsbt r2, [r0] +#else +2: strlsbt r2, [r0], #1 3: strlsbt r1, [r0] +#endif movls r0, #0 movls pc, lr b __put_user_bad diff -urN linux-2.5.2-pre8/arch/arm/lib/uaccess.S linux/arch/arm/lib/uaccess.S --- linux-2.5.2-pre8/arch/arm/lib/uaccess.S Mon Sep 18 15:15:25 2000 +++ linux/arch/arm/lib/uaccess.S Sat Jan 5 14:43:15 2002 @@ -115,9 +115,9 @@ .c2u_1fupi: subs r2, r2, #4 addmi ip, r2, #4 bmi .c2u_1nowords - mov r3, r7, lsr #8 + mov r3, r7, pull #8 ldr r7, [r1], #4 - orr r3, r3, r7, lsl #24 + orr r3, r3, r7, push #24 USER( strt r3, [r0], #4) @ May fault mov ip, r0, lsl #32 - PAGE_SHIFT rsb ip, ip, #0 @@ -129,49 +129,49 @@ subs ip, ip, #16 blt .c2u_1rem8lp -.c2u_1cpy8lp: mov r3, r7, lsr #8 +.c2u_1cpy8lp: mov r3, r7, pull #8 ldmia r1!, {r4 - r7} - orr r3, r3, r4, lsl #24 - mov r4, r4, lsr #8 - orr r4, r4, r5, lsl #24 - mov r5, r5, lsr #8 - orr r5, r5, r6, lsl #24 - mov r6, r6, lsr #8 - orr r6, r6, r7, lsl #24 + orr r3, r3, r4, push #24 + mov r4, r4, pull #8 + orr r4, r4, r5, push #24 + mov r5, r5, pull #8 + orr r5, r5, r6, push #24 + mov r6, r6, pull #8 + orr r6, r6, r7, push #24 stmia r0!, {r3 - r6} @ Shouldnt fault subs ip, ip, #16 bpl .c2u_1cpy8lp .c2u_1rem8lp: tst ip, #8 - movne r3, r7, lsr #8 + movne r3, r7, pull #8 ldmneia r1!, {r4, r7} - orrne r3, r3, r4, lsl #24 - movne r4, r4, lsr #8 - orrne r4, r4, r7, lsl #24 + orrne r3, r3, r4, push #24 + movne r4, r4, pull #8 + orrne r4, r4, r7, push #24 stmneia r0!, {r3 - r4} @ Shouldnt fault tst ip, #4 - movne r3, r7, lsr #8 + movne r3, r7, pull #8 ldrne r7, [r1], #4 - orrne r3, r3, r7, lsl #24 + orrne r3, r3, r7, push #24 strnet r3, [r0], #4 @ Shouldnt fault ands ip, ip, #3 beq .c2u_1fupi -.c2u_1nowords: mov r3, r7, lsr #8 +.c2u_1nowords: mov r3, r7, lsr #byte(1) teq ip, #0 beq .c2u_finished cmp ip, #2 USER( strbt r3, [r0], #1) @ May fault - movge r3, r3, lsr #8 + movge r3, r7, lsr #byte(2) USER( strgebt r3, [r0], #1) @ May fault - movgt r3, r3, lsr #8 + movgt r3, r7, lsr #byte(3) USER( strgtbt r3, [r0], #1) @ May fault b .c2u_finished .c2u_2fupi: subs r2, r2, #4 addmi ip, r2, #4 bmi .c2u_2nowords - mov r3, r7, lsr #16 + mov r3, r7, pull #16 ldr r7, [r1], #4 - orr r3, r3, r7, lsl #16 + orr r3, r3, r7, push #16 USER( strt r3, [r0], #4) @ May fault mov ip, r0, lsl #32 - PAGE_SHIFT rsb ip, ip, #0 @@ -183,38 +183,38 @@ subs ip, ip, #16 blt .c2u_2rem8lp -.c2u_2cpy8lp: mov r3, r7, lsr #16 +.c2u_2cpy8lp: mov r3, r7, pull #16 ldmia r1!, {r4 - r7} - orr r3, r3, r4, lsl #16 - mov r4, r4, lsr #16 - orr r4, r4, r5, lsl #16 - mov r5, r5, lsr #16 - orr r5, r5, r6, lsl #16 - mov r6, r6, lsr #16 - orr r6, r6, r7, lsl #16 + orr r3, r3, r4, push #16 + mov r4, r4, pull #16 + orr r4, r4, r5, push #16 + mov r5, r5, pull #16 + orr r5, r5, r6, push #16 + mov r6, r6, pull #16 + orr r6, r6, r7, push #16 stmia r0!, {r3 - r6} @ Shouldnt fault subs ip, ip, #16 bpl .c2u_2cpy8lp .c2u_2rem8lp: tst ip, #8 - movne r3, r7, lsr #16 + movne r3, r7, pull #16 ldmneia r1!, {r4, r7} - orrne r3, r3, r4, lsl #16 - movne r4, r4, lsr #16 - orrne r4, r4, r7, lsl #16 + orrne r3, r3, r4, push #16 + movne r4, r4, pull #16 + orrne r4, r4, r7, push #16 stmneia r0!, {r3 - r4} @ Shouldnt fault tst ip, #4 - movne r3, r7, lsr #16 + movne r3, r7, pull #16 ldrne r7, [r1], #4 - orrne r3, r3, r7, lsl #16 + orrne r3, r3, r7, push #16 strnet r3, [r0], #4 @ Shouldnt fault ands ip, ip, #3 beq .c2u_2fupi -.c2u_2nowords: mov r3, r7, lsr #16 +.c2u_2nowords: mov r3, r7, lsr #byte(2) teq ip, #0 beq .c2u_finished cmp ip, #2 USER( strbt r3, [r0], #1) @ May fault - movge r3, r3, lsr #8 + movge r3, r7, lsr #byte(3) USER( strgebt r3, [r0], #1) @ May fault ldrgtb r3, [r1], #0 USER( strgtbt r3, [r0], #1) @ May fault @@ -223,9 +223,9 @@ .c2u_3fupi: subs r2, r2, #4 addmi ip, r2, #4 bmi .c2u_3nowords - mov r3, r7, lsr #24 + mov r3, r7, pull #24 ldr r7, [r1], #4 - orr r3, r3, r7, lsl #8 + orr r3, r3, r7, push #8 USER( strt r3, [r0], #4) @ May fault mov ip, r0, lsl #32 - PAGE_SHIFT rsb ip, ip, #0 @@ -237,40 +237,40 @@ subs ip, ip, #16 blt .c2u_3rem8lp -.c2u_3cpy8lp: mov r3, r7, lsr #24 +.c2u_3cpy8lp: mov r3, r7, pull #24 ldmia r1!, {r4 - r7} - orr r3, r3, r4, lsl #8 - mov r4, r4, lsr #24 - orr r4, r4, r5, lsl #8 - mov r5, r5, lsr #24 - orr r5, r5, r6, lsl #8 - mov r6, r6, lsr #24 - orr r6, r6, r7, lsl #8 + orr r3, r3, r4, push #8 + mov r4, r4, pull #24 + orr r4, r4, r5, push #8 + mov r5, r5, pull #24 + orr r5, r5, r6, push #8 + mov r6, r6, pull #24 + orr r6, r6, r7, push #8 stmia r0!, {r3 - r6} @ Shouldnt fault subs ip, ip, #16 bpl .c2u_3cpy8lp .c2u_3rem8lp: tst ip, #8 - movne r3, r7, lsr #24 + movne r3, r7, pull #24 ldmneia r1!, {r4, r7} - orrne r3, r3, r4, lsl #8 - movne r4, r4, lsr #24 - orrne r4, r4, r7, lsl #8 + orrne r3, r3, r4, push #8 + movne r4, r4, pull #24 + orrne r4, r4, r7, push #8 stmneia r0!, {r3 - r4} @ Shouldnt fault tst ip, #4 - movne r3, r7, lsr #24 + movne r3, r7, pull #24 ldrne r7, [r1], #4 - orrne r3, r3, r7, lsl #8 + orrne r3, r3, r7, push #8 strnet r3, [r0], #4 @ Shouldnt fault ands ip, ip, #3 beq .c2u_3fupi -.c2u_3nowords: mov r3, r7, lsr #24 +.c2u_3nowords: mov r3, r7, lsr #byte(3) teq ip, #0 beq .c2u_finished cmp ip, #2 USER( strbt r3, [r0], #1) @ May fault - ldrge r3, [r1], #0 + ldrgeb r3, [r1], #1 USER( strgebt r3, [r0], #1) @ May fault - movgt r3, r3, lsr #8 + ldrgtb r3, [r1], #0 USER( strgtbt r3, [r0], #1) @ May fault b .c2u_finished @@ -374,9 +374,9 @@ .cfu_1fupi: subs r2, r2, #4 addmi ip, r2, #4 bmi .cfu_1nowords - mov r3, r7, lsr #8 + mov r3, r7, pull #8 USER( ldrt r7, [r1], #4) @ May fault - orr r3, r3, r7, lsl #24 + orr r3, r3, r7, push #24 str r3, [r0], #4 mov ip, r1, lsl #32 - PAGE_SHIFT rsb ip, ip, #0 @@ -388,49 +388,49 @@ subs ip, ip, #16 blt .cfu_1rem8lp -.cfu_1cpy8lp: mov r3, r7, lsr #8 +.cfu_1cpy8lp: mov r3, r7, pull #8 ldmia r1!, {r4 - r7} @ Shouldnt fault - orr r3, r3, r4, lsl #24 - mov r4, r4, lsr #8 - orr r4, r4, r5, lsl #24 - mov r5, r5, lsr #8 - orr r5, r5, r6, lsl #24 - mov r6, r6, lsr #8 - orr r6, r6, r7, lsl #24 + orr r3, r3, r4, push #24 + mov r4, r4, pull #8 + orr r4, r4, r5, push #24 + mov r5, r5, pull #8 + orr r5, r5, r6, push #24 + mov r6, r6, pull #8 + orr r6, r6, r7, push #24 stmia r0!, {r3 - r6} subs ip, ip, #16 bpl .cfu_1cpy8lp .cfu_1rem8lp: tst ip, #8 - movne r3, r7, lsr #8 + movne r3, r7, pull #8 ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, lsl #24 - movne r4, r4, lsr #8 - orrne r4, r4, r7, lsl #24 + orrne r3, r3, r4, push #24 + movne r4, r4, pull #8 + orrne r4, r4, r7, push #24 stmneia r0!, {r3 - r4} tst ip, #4 - movne r3, r7, lsr #8 + movne r3, r7, pull #8 USER( ldrnet r7, [r1], #4) @ May fault - orrne r3, r3, r7, lsl #24 + orrne r3, r3, r7, push #24 strne r3, [r0], #4 ands ip, ip, #3 beq .cfu_1fupi -.cfu_1nowords: mov r3, r7, lsr #8 +.cfu_1nowords: mov r3, r7, lsr #byte(1) teq ip, #0 beq .cfu_finished cmp ip, #2 strb r3, [r0], #1 - movge r3, r3, lsr #8 + movge r3, r7, lsr #byte(2) strgeb r3, [r0], #1 - movgt r3, r3, lsr #8 + movgt r3, r7, lsr #byte(3) strgtb r3, [r0], #1 b .cfu_finished .cfu_2fupi: subs r2, r2, #4 addmi ip, r2, #4 bmi .cfu_2nowords - mov r3, r7, lsr #16 + mov r3, r7, pull #16 USER( ldrt r7, [r1], #4) @ May fault - orr r3, r3, r7, lsl #16 + orr r3, r3, r7, push #16 str r3, [r0], #4 mov ip, r1, lsl #32 - PAGE_SHIFT rsb ip, ip, #0 @@ -442,38 +442,38 @@ subs ip, ip, #16 blt .cfu_2rem8lp -.cfu_2cpy8lp: mov r3, r7, lsr #16 +.cfu_2cpy8lp: mov r3, r7, pull #16 ldmia r1!, {r4 - r7} @ Shouldnt fault - orr r3, r3, r4, lsl #16 - mov r4, r4, lsr #16 - orr r4, r4, r5, lsl #16 - mov r5, r5, lsr #16 - orr r5, r5, r6, lsl #16 - mov r6, r6, lsr #16 - orr r6, r6, r7, lsl #16 + orr r3, r3, r4, push #16 + mov r4, r4, pull #16 + orr r4, r4, r5, push #16 + mov r5, r5, pull #16 + orr r5, r5, r6, push #16 + mov r6, r6, pull #16 + orr r6, r6, r7, push #16 stmia r0!, {r3 - r6} subs ip, ip, #16 bpl .cfu_2cpy8lp .cfu_2rem8lp: tst ip, #8 - movne r3, r7, lsr #16 + movne r3, r7, pull #16 ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, lsl #16 - movne r4, r4, lsr #16 - orrne r4, r4, r7, lsl #16 + orrne r3, r3, r4, push #16 + movne r4, r4, pull #16 + orrne r4, r4, r7, push #16 stmneia r0!, {r3 - r4} tst ip, #4 - movne r3, r7, lsr #16 + movne r3, r7, pull #16 USER( ldrnet r7, [r1], #4) @ May fault - orrne r3, r3, r7, lsl #16 + orrne r3, r3, r7, push #16 strne r3, [r0], #4 ands ip, ip, #3 beq .cfu_2fupi -.cfu_2nowords: mov r3, r7, lsr #16 +.cfu_2nowords: mov r3, r7, lsr #byte(2) teq ip, #0 beq .cfu_finished cmp ip, #2 strb r3, [r0], #1 - movge r3, r3, lsr #8 + movge r3, r7, lsr #byte(3) strgeb r3, [r0], #1 USER( ldrgtbt r3, [r1], #0) @ May fault strgtb r3, [r0], #1 @@ -482,9 +482,9 @@ .cfu_3fupi: subs r2, r2, #4 addmi ip, r2, #4 bmi .cfu_3nowords - mov r3, r7, lsr #24 + mov r3, r7, pull #24 USER( ldrt r7, [r1], #4) @ May fault - orr r3, r3, r7, lsl #8 + orr r3, r3, r7, push #8 str r3, [r0], #4 mov ip, r1, lsl #32 - PAGE_SHIFT rsb ip, ip, #0 @@ -496,40 +496,40 @@ subs ip, ip, #16 blt .cfu_3rem8lp -.cfu_3cpy8lp: mov r3, r7, lsr #24 +.cfu_3cpy8lp: mov r3, r7, pull #24 ldmia r1!, {r4 - r7} @ Shouldnt fault - orr r3, r3, r4, lsl #8 - mov r4, r4, lsr #24 - orr r4, r4, r5, lsl #8 - mov r5, r5, lsr #24 - orr r5, r5, r6, lsl #8 - mov r6, r6, lsr #24 - orr r6, r6, r7, lsl #8 + orr r3, r3, r4, push #8 + mov r4, r4, pull #24 + orr r4, r4, r5, push #8 + mov r5, r5, pull #24 + orr r5, r5, r6, push #8 + mov r6, r6, pull #24 + orr r6, r6, r7, push #8 stmia r0!, {r3 - r6} subs ip, ip, #16 bpl .cfu_3cpy8lp .cfu_3rem8lp: tst ip, #8 - movne r3, r7, lsr #24 + movne r3, r7, pull #24 ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, lsl #8 - movne r4, r4, lsr #24 - orrne r4, r4, r7, lsl #8 + orrne r3, r3, r4, push #8 + movne r4, r4, pull #24 + orrne r4, r4, r7, push #8 stmneia r0!, {r3 - r4} tst ip, #4 - movne r3, r7, lsr #24 + movne r3, r7, pull #24 USER( ldrnet r7, [r1], #4) @ May fault - orrne r3, r3, r7, lsl #8 + orrne r3, r3, r7, push #8 strne r3, [r0], #4 ands ip, ip, #3 beq .cfu_3fupi -.cfu_3nowords: mov r3, r7, lsr #24 +.cfu_3nowords: mov r3, r7, lsr #byte(3) teq ip, #0 beq .cfu_finished cmp ip, #2 strb r3, [r0], #1 -USER( ldrget r3, [r1], #0) @ May fault +USER( ldrgebt r3, [r1], #1) @ May fault strgeb r3, [r0], #1 - movgt r3, r3, lsr #8 +USER( ldrgtbt r3, [r1], #1) @ May fault strgtb r3, [r0], #1 b .cfu_finished diff -urN linux-2.5.2-pre8/arch/arm/mach-adifcc/Makefile linux/arch/arm/mach-adifcc/Makefile --- linux-2.5.2-pre8/arch/arm/mach-adifcc/Makefile Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-adifcc/Makefile Sat Jan 5 14:43:15 2002 @@ -0,0 +1,21 @@ +# +# Makefile for the linux kernel. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). + +USE_STANDARD_AS_RULE := true + +O_TARGET := adifcc.o + +# Object file lists. + +obj-y := arch.o irq.o mm.o +obj-m := +obj-n := +obj- := + +export-objs := + +include $(TOPDIR)/Rules.make diff -urN linux-2.5.2-pre8/arch/arm/mach-adifcc/arch.c linux/arch/arm/mach-adifcc/arch.c --- linux-2.5.2-pre8/arch/arm/mach-adifcc/arch.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-adifcc/arch.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,49 @@ +/* + * linux/arch/arm/mach-adifcc/arch.c + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void adifcc_map_io(void); +extern void adifcc_init_irq(void); + +static void __init +fixup_adifcc(struct machine_desc *desc, struct param_struct *params, + char **cmdline, struct meminfo *mi) +{ +#ifdef CONFIG_ARCH_ADI_EVB + mi->bank[0].start = PHYS_OFFSET; + mi->bank[0].size = (32*1024*1024); + mi->bank[0].node = 0; + mi->nr_banks = 1; + + setup_ramdisk( 1, 0, 0, 8192 ); + setup_initrd( 0xc0800000, 3*1024*1024 ); + ROOT_DEV = MKDEV(RAMDISK_MAJOR,0); +#endif +} + +#ifdef CONFIG_ARCH_ADI_EVB +MACHINE_START(ADI_EVB, "ADI 80200FCC Evaluation Board") + MAINTAINER("MontaVista Software Inc.") + BOOT_MEM(0xc0000000, 0x00400000, 0xff400000) + FIXUP(fixup_adifcc) + MAPIO(adifcc_map_io) + INITIRQ(adifcc_init_irq) +MACHINE_END +#endif + diff -urN linux-2.5.2-pre8/arch/arm/mach-adifcc/irq.c linux/arch/arm/mach-adifcc/irq.c --- linux-2.5.2-pre8/arch/arm/mach-adifcc/irq.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-adifcc/irq.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,66 @@ +/* + * linux/arch/arm/mach-xscale/irq.c + * + * Author: Deepak Saxena + * Copyright: (C) 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Based on IOP80310 code. Currently there's nothing more than the + * 80200 on chip interrupts. That'll change once the hardware adds + * support for PCI though. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +static void xs80200_irq_mask (unsigned int irq) +{ + long INTCTL; + asm ("mrc p13, 0, %0, c0, c0, 0" : "=r" (INTCTL)); + switch (irq) { + case IRQ_XS80200_BCU: INTCTL &= ~(1<<3); break; + case IRQ_XS80200_PMU: INTCTL &= ~(1<<2); break; + case IRQ_XS80200_EXTIRQ: INTCTL &= ~(1<<1); break; + case IRQ_XS80200_EXTFIQ: INTCTL &= ~(1<<0); break; + } + asm ("mcr p13, 0, %0, c0, c0, 0" : : "r" (INTCTL)); +} + +static void xs80200_irq_unmask (unsigned int irq) +{ + long INTCTL; + asm ("mrc p13, 0, %0, c0, c0, 0" : "=r" (INTCTL)); + switch (irq) { + case IRQ_XS80200_BCU: INTCTL |= (1<<3); break; + case IRQ_XS80200_PMU: INTCTL |= (1<<2); break; + case IRQ_XS80200_EXTIRQ: INTCTL |= (1<<1); break; + case IRQ_XS80200_EXTFIQ: INTCTL |= (1<<0); break; + } + asm ("mcr p13, 0, %0, c0, c0, 0" : : "r" (INTCTL)); +} + +void __init adifcc_init_irq(void) +{ + int i; + + for (i = 0; i < NR_XS80200_IRQS; i++) { + irq_desc[i].valid = 1; + irq_desc[i].probe_ok = 0; + irq_desc[i].mask_ack = xs80200_irq_mask; + irq_desc[i].mask = xs80200_irq_mask; + irq_desc[i].unmask = xs80200_irq_unmask; + } +} + + diff -urN linux-2.5.2-pre8/arch/arm/mach-adifcc/mm.c linux/arch/arm/mach-adifcc/mm.c --- linux-2.5.2-pre8/arch/arm/mach-adifcc/mm.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-adifcc/mm.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,24 @@ +/* + * linux/arch/arm/mach-xscale/mm.c + */ + +#include +#include + +#include +#include +#include + +#include + + +static struct map_desc adifcc_io_desc[] __initdata = { + /* on-board devices */ + { 0xff400000, 0x00400000, 0x00300000, DOMAIN_IO, 1, 1, 0, 0}, + LAST_DESC +}; + +void __init adifcc_map_io(void) +{ + iotable_init(adifcc_io_desc); +} diff -urN linux-2.5.2-pre8/arch/arm/mach-arc/Makefile linux/arch/arm/mach-arc/Makefile --- linux-2.5.2-pre8/arch/arm/mach-arc/Makefile Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-arc/Makefile Sat Jan 5 14:43:15 2002 @@ -0,0 +1,28 @@ +# +# Makefile for the linux kernel. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). + +USE_STANDARD_AS_RULE := true + +O_TARGET := arc.o + +# Object file lists. + +obj-y := arch.o dma.o fault.o irq.o mm.o oldlatches.o \ + small_page.o +obj-m := +obj-n := +obj- := + +export-objs := oldlatches.o + +obj-$(CONFIG_DEBUG_LL) += debug.o + +all: arc.o head.o + +include $(TOPDIR)/Rules.make + +AFLAGS_head.o := -DTEXTADDR=$(TEXTADDR) diff -urN linux-2.5.2-pre8/arch/arm/mach-arc/arch.c linux/arch/arm/mach-arc/arch.c --- linux-2.5.2-pre8/arch/arm/mach-arc/arch.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-arc/arch.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,39 @@ +/* + * linux/arch/arm/mach-arc/arch.c + * + * Copyright (C) 1998-2001 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Architecture specific fixups. + */ +#include +#include + +#include +#include +#include +#include + +#include +#include + +extern void arc_init_irq(void); + +#ifdef CONFIG_ARCH_ARC +MACHINE_START(ARCHIMEDES, "Acorn-Archimedes") + MAINTAINER("Dave Gilbert") + BOOT_PARAMS(0x0207c000) + INITIRQ(arc_init_irq) +MACHINE_END +#endif +#ifdef CONFIG_ARCH_A5K +MACHINE_START(A5K, "Acorn-A5000") + MAINTAINER("Russell King") + BOOT_PARAMS(0x0207c000) + INITIRQ(arc_init_irq) +MACHINE_END +#endif + diff -urN linux-2.5.2-pre8/arch/arm/mach-arc/debug.S linux/arch/arm/mach-arc/debug.S --- linux-2.5.2-pre8/arch/arm/mach-arc/debug.S Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-arc/debug.S Sat Jan 5 14:43:15 2002 @@ -0,0 +1,90 @@ +/* + * linux/arch/arm/kernel/debug-armo.S + * + * Copyright (C) 1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * 26-bit debugging code + */ +#include + + .macro addruart,rx + mov \rx, #0x03000000 + orr \rx, \rx, #0x00010000 + orr \rx, \rx, #0x00000fe0 + .endm + + .macro senduart,rd,rx + strb \rd, [\rx] + .endm + + .macro busyuart,rd,rx +1002: ldrb \rd, [\rx, #0x14] + and \rd, \rd, #0x60 + teq \rd, #0x60 + bne 1002b + .endm + + .macro waituart,rd,rx +1001: ldrb \rd, [\rx, #0x18] + tst \rd, #0x10 + beq 1001b + .endm + + .text +/* + * Useful debugging routines + */ +ENTRY(printhex8) + mov r1, #8 + b printhex + +ENTRY(printhex4) + mov r1, #4 + b printhex + +ENTRY(printhex2) + mov r1, #2 +printhex: ldr r2, =hexbuf + add r3, r2, r1 + mov r1, #0 + strb r1, [r3] +1: and r1, r0, #15 + mov r0, r0, lsr #4 + cmp r1, #10 + addlt r1, r1, #'0' + addge r1, r1, #'a' - 10 + strb r1, [r3, #-1]! + teq r3, r2 + bne 1b + mov r0, r2 + b printascii + + .ltorg + +ENTRY(printascii) + addruart r3 + b 2f +1: waituart r2, r3 + senduart r1, r3 + busyuart r2, r3 + teq r1, #'\n' + moveq r1, #'\r' + beq 1b +2: teq r0, #0 + ldrneb r1, [r0], #1 + teqne r1, #0 + bne 1b + mov pc, lr + +ENTRY(printch) + addruart r3 + mov r1, r0 + mov r0, #0 + b 1b + + .bss +hexbuf: .space 16 diff -urN linux-2.5.2-pre8/arch/arm/mach-arc/dma.c linux/arch/arm/mach-arc/dma.c --- linux-2.5.2-pre8/arch/arm/mach-arc/dma.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-arc/dma.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,208 @@ +/* + * linux/arch/arm/kernel/dma-arc.c + * + * Copyright (C) 1998-1999 Dave Gilbert / Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * DMA functions specific to Archimedes and A5000 architecture + */ +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#define DPRINTK(x...) printk(KERN_DEBUG x) + +#if defined(CONFIG_BLK_DEV_FD1772) || defined(CONFIG_BLK_DEV_FD1772_MODULE) +static void arc_floppy_data_enable_dma(dmach_t channel, dma_t *dma) +{ + DPRINTK("arc_floppy_data_enable_dma\n"); + switch (dma->dma_mode) { + case DMA_MODE_READ: { /* read */ + extern unsigned char fdc1772_dma_read, fdc1772_dma_read_end; + extern void fdc1772_setupdma(unsigned int count,unsigned int addr); + unsigned long flags; + DPRINTK("enable_dma fdc1772 data read\n"); + save_flags(flags); + clf(); + + memcpy ((void *)0x1c, (void *)&fdc1772_dma_read, + &fdc1772_dma_read_end - &fdc1772_dma_read); + fdc1772_setupdma(dma->buf.length, dma->buf.address); /* Sets data pointer up */ + enable_fiq(FIQ_FLOPPYDATA); + restore_flags(flags); + } + break; + + case DMA_MODE_WRITE: { /* write */ + extern unsigned char fdc1772_dma_write, fdc1772_dma_write_end; + extern void fdc1772_setupdma(unsigned int count,unsigned int addr); + unsigned long flags; + DPRINTK("enable_dma fdc1772 data write\n"); + save_flags(flags); + clf(); + memcpy ((void *)0x1c, (void *)&fdc1772_dma_write, + &fdc1772_dma_write_end - &fdc1772_dma_write); + fdc1772_setupdma(dma->buf.length, dma->buf.address); /* Sets data pointer up */ + enable_fiq(FIQ_FLOPPYDATA; + + restore_flags(flags); + } + break; + default: + printk ("enable_dma: dma%d not initialised\n", channel); + } +} + +static int arc_floppy_data_get_dma_residue(dmach_t channel, dma_t *dma) +{ + extern unsigned int fdc1772_bytestogo; + + /* 10/1/1999 DAG - I presume its the number of bytes left? */ + return fdc1772_bytestogo; +} + +static void arc_floppy_cmdend_enable_dma(dmach_t channel, dma_t *dma) +{ + /* Need to build a branch at the FIQ address */ + extern void fdc1772_comendhandler(void); + unsigned long flags; + + DPRINTK("arc_floppy_cmdend_enable_dma\n"); + /*printk("enable_dma fdc1772 command end FIQ\n");*/ + save_flags(flags); + clf(); + + /* B fdc1772_comendhandler */ + *((unsigned int *)0x1c)=0xea000000 | + (((unsigned int)fdc1772_comendhandler-(0x1c+8))/4); + + restore_flags(flags); +} + +static int arc_floppy_cmdend_get_dma_residue(dmach_t channel, dma_t *dma) +{ + /* 10/1/1999 DAG - Presume whether there is an outstanding command? */ + extern unsigned int fdc1772_fdc_int_done; + + * Explicit! If the int done is 0 then 1 int to go */ + return (fdc1772_fdc_int_done==0)?1:0; +} + +static void arc_disable_dma(dmach_t channel, dma_t *dma) +{ + disable_fiq(dma->dma_irq); +} + +static struct dma_ops arc_floppy_data_dma_ops = { + type: "FIQDMA", + enable: arc_floppy_data_enable_dma, + disable: arc_disable_dma, + residue: arc_floppy_data_get_dma_residue, +}; + +static struct dma_ops arc_floppy_cmdend_dma_ops = { + type: "FIQCMD", + enable: arc_floppy_cmdend_enable_dma, + disable: arc_disable_dma, + residue: arc_floppy_cmdend_get_dma_residue, +}; +#endif + +#ifdef CONFIG_ARCH_A5K +static struct fiq_handler fh = { + name: "floppydata" +}; + +static int a5k_floppy_get_dma_residue(dmach_t channel, dma_t *dma) +{ + struct pt_regs regs; + get_fiq_regs(®s); + return regs.ARM_r9; +} + +static void a5k_floppy_enable_dma(dmach_t channel, dma_t *dma) +{ + struct pt_regs regs; + void *fiqhandler_start; + unsigned int fiqhandler_length; + extern void floppy_fiqsetup(unsigned long len, unsigned long addr, + unsigned long port); + + if (dma->dma_mode == DMA_MODE_READ) { + extern unsigned char floppy_fiqin_start, floppy_fiqin_end; + fiqhandler_start = &floppy_fiqin_start; + fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start; + } else { + extern unsigned char floppy_fiqout_start, floppy_fiqout_end; + fiqhandler_start = &floppy_fiqout_start; + fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start; + } + if (claim_fiq(&fh)) { + printk("floppydma: couldn't claim FIQ.\n"); + return; + } + memcpy((void *)0x1c, fiqhandler_start, fiqhandler_length); + regs.ARM_r9 = dma->buf.length; + regs.ARM_r10 = (unsigned long)dma->buf.address; + regs.ARM_fp = FLOPPYDMA_BASE; + set_fiq_regs(®s); + enable_fiq(dma->dma_irq); +} + +static void a5k_floppy_disable_dma(dmach_t channel, dma_t *dma) +{ + disable_fiq(dma->dma_irq); + release_fiq(&fh); +} + +static struct dma_ops a5k_floppy_dma_ops = { + type: "FIQDMA", + enable: a5k_floppy_enable_dma, + disable: a5k_floppy_disable_dma, + residue: a5k_floppy_get_dma_residue, +}; +#endif + +/* + * This is virtual DMA - we don't need anything here + */ +static void sound_enable_disable_dma(dmach_t channel, dma_t *dma) +{ +} + +static struct dma_ops sound_dma_ops = { + type: "VIRTUAL", + enable: sound_enable_disable_dma, + disable: sound_enable_disable_dma, +}; + +void __init arch_dma_init(dma_t *dma) +{ +#if defined(CONFIG_BLK_DEV_FD1772) || defined(CONFIG_BLK_DEV_FD1772_MODULE) + if (machine_is_archimedes()) { + dma[DMA_VIRTUAL_FLOPPY0].dma_irq = FIQ_FLOPPYDATA; + dma[DMA_VIRTUAL_FLOPPY0].d_ops = &arc_floppy_data_dma_ops; + dma[DMA_VIRTUAL_FLOPPY1].dma_irq = 1; + dma[DMA_VIRTUAL_FLOPPY1].d_ops = &arc_floppy_cmdend_dma_ops; + } +#endif +#ifdef CONFIG_ARCH_A5K + if (machine_is_a5k()) { + dma[DMA_VIRTUAL_FLOPPY0].dma_irq = FIQ_FLOPPYDATA; + dma[DMA_VIRTUAL_FLOPPY0].d_ops = &a5k_floppy_dma_ops; + } +#endif + dma[DMA_VIRTUAL_SOUND].d_ops = &sound_dma_ops; +} diff -urN linux-2.5.2-pre8/arch/arm/mach-arc/fault.c linux/arch/arm/mach-arc/fault.c --- linux-2.5.2-pre8/arch/arm/mach-arc/fault.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-arc/fault.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,66 @@ +/* + * linux/arch/arm/mm/fault-armo.c + * + * Copyright (C) 1995 Linus Torvalds + * Modifications for ARM processor (c) 1995-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define FAULT_CODE_LDRSTRPOST 0x80 +#define FAULT_CODE_LDRSTRPRE 0x40 +#define FAULT_CODE_LDRSTRREG 0x20 +#define FAULT_CODE_LDMSTM 0x10 +#define FAULT_CODE_LDCSTC 0x08 +#define FAULT_CODE_PREFETCH 0x04 +#define FAULT_CODE_WRITE 0x02 +#define FAULT_CODE_FORCECOW 0x01 + +#define DO_COW(m) ((m) & (FAULT_CODE_WRITE|FAULT_CODE_FORCECOW)) +#define READ_FAULT(m) (!((m) & FAULT_CODE_WRITE)) + +extern int do_page_fault(unsigned long addr, int mode, struct pt_regs *regs); +extern void show_pte(struct mm_struct *mm, unsigned long addr); + +/* + * Handle a data abort. Note that we have to handle a range of addresses + * on ARM2/3 for ldm. If both pages are zero-mapped, then we have to force + * a copy-on-write. However, on the second page, we always force COW. + */ +asmlinkage void +do_DataAbort(unsigned long min_addr, unsigned long max_addr, int mode, struct pt_regs *regs) +{ + do_page_fault(min_addr, mode, regs); + + if ((min_addr ^ max_addr) >> PAGE_SHIFT) + do_page_fault(max_addr, mode | FAULT_CODE_FORCECOW, regs); +} + +asmlinkage int +do_PrefetchAbort(unsigned long addr, struct pt_regs *regs) +{ +#if 0 + if (the memc mapping for this page exists) { + printk ("Page in, but got abort (undefined instruction?)\n"); + return 0; + } +#endif + do_page_fault(addr, FAULT_CODE_PREFETCH, regs); + return 1; +} diff -urN linux-2.5.2-pre8/arch/arm/mach-arc/head.S linux/arch/arm/mach-arc/head.S --- linux-2.5.2-pre8/arch/arm/mach-arc/head.S Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-arc/head.S Sat Jan 5 14:43:15 2002 @@ -0,0 +1,92 @@ +/* + * linux/arch/arm/kernel/head-armo.S + * + * Copyright (C) 1994-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * 26-bit kernel startup code + */ +#include +#include +#include + + .globl SYMBOL_NAME(swapper_pg_dir) + .equ SYMBOL_NAME(swapper_pg_dir), 0x0207d000 + +/* + * Entry point. + */ + .section ".text.init",#alloc,#execinstr +ENTRY(stext) +__entry: cmp pc, #0x02000000 + ldrlt pc, LC0 @ if 0x01800000, call at 0x02080000 + teq r0, #0 @ Check for old calling method + blne oldparams @ Move page if old + adr r0, LC0 + ldmib r0, {r2-r5, sp} @ Setup stack + mov r0, #0 +1: cmp r2, r3 @ Clear BSS + strcc r0, [r2], #4 + bcc 1b + + bl detect_proc_type + str r0, [r4] + bl detect_arch_type + str r0, [r5] + + mov fp, #0 + b SYMBOL_NAME(start_kernel) + +LC0: .word SYMBOL_NAME(_stext) + .word SYMBOL_NAME(__bss_start) @ r2 + .word SYMBOL_NAME(_end) @ r3 + .word SYMBOL_NAME(processor_id) @ r4 + .word SYMBOL_NAME(__machine_arch_type) @ r5 + .word SYMBOL_NAME(init_task_union)+8192 @ sp +arm2_id: .long 0x41560200 +arm250_id: .long 0x41560250 + .align + +oldparams: mov r4, #0x02000000 + add r3, r4, #0x00080000 + add r4, r4, #0x0007c000 +1: ldmia r0!, {r5 - r12} + stmia r4!, {r5 - r12} + cmp r4, r3 + blt 1b + mov pc, lr + +/* + * We need some way to automatically detect the difference between + * these two machines. Unfortunately, it is not possible to detect + * the presence of the SuperIO chip, because that will hang the old + * Archimedes machines solid. + */ +/* DAG: Outdated, these have been combined !!!!!!! */ +detect_arch_type: +#if defined(CONFIG_ARCH_ARC) + mov r0, #MACH_TYPE_ARCHIMEDES +#elif defined(CONFIG_ARCH_A5K) + mov r0, #MACH_TYPE_A5K +#endif + mov pc, lr + +detect_proc_type: + mov ip, lr + mov r2, #0xea000000 @ Point undef instr to continuation + adr r0, continue - 12 + orr r0, r2, r0, lsr #2 + mov r1, #0 + str r0, [r1, #4] + ldr r0, arm2_id + swp r2, r2, [r1] @ check for swp (ARM2 cant) + ldr r0, arm250_id + mrc 15, 0, r3, c0, c0 @ check for CP#15 (ARM250 cant) + mov r0, r3 +continue: mov r2, #0xeb000000 @ Make undef vector loop + sub r2, r2, #2 + str r2, [r1, #4] + mov pc, ip diff -urN linux-2.5.2-pre8/arch/arm/mach-arc/irq.c linux/arch/arm/mach-arc/irq.c --- linux-2.5.2-pre8/arch/arm/mach-arc/irq.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-arc/irq.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,153 @@ +/* + * linux/arch/arm/mach-arc/irq.c + * + * Copyright (C) 1996 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 24-09-1996 RMK Created + * 10-10-1996 RMK Brought up to date with arch-sa110eval + * 22-10-1996 RMK Changed interrupt numbers & uses new inb/outb macros + * 11-01-1998 RMK Added mask_and_ack_irq + * 22-08-1998 RMK Restructured IRQ routines + */ +#include +#include + +#include +#include +#include +#include + +extern void init_FIQ(void); + +#ifdef CONFIG_ARCH_ARC +#define a_clf() clf() +#define a_stf() stf() +#else +#define a_clf() do { } while (0) +#define a_stf() do { } while (0) +#endif + +static void arc_mask_irq_ack_a(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << irq; + a_clf(); + val = ioc_readb(IOC_IRQMASKA); + ioc_writeb(val & ~mask, IOC_IRQMASKA); + ioc_writeb(mask, IOC_IRQCLRA); + a_stf(); +} + +static void arc_mask_irq_a(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << irq; + a_clf(); + val = ioc_readb(IOC_IRQMASKA); + ioc_writeb(val & ~mask, IOC_IRQMASKA); + a_stf(); +} + +static void arc_unmask_irq_a(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << irq; + a_clf(); + val = ioc_readb(IOC_IRQMASKA); + ioc_writeb(val | mask, IOC_IRQMASKA); + a_stf(); +} + +static void arc_mask_irq_b(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = ioc_readb(IOC_IRQMASKB); + ioc_writeb(val & ~mask, IOC_IRQMASKB); +} + +static void arc_unmask_irq_b(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = ioc_readb(IOC_IRQMASKB); + ioc_writeb(val | mask, IOC_IRQMASKB); +} + +static void arc_mask_irq_fiq(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = ioc_readb(IOC_FIQMASK); + ioc_writeb(val & ~mask, IOC_FIQMASK); +} + +static void arc_unmask_irq_fiq(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = ioc_readb(IOC_FIQMASK); + ioc_writeb(val | mask, IOC_FIQMASK); +} + +void __init arc_init_irq(void) +{ + int irq; + + ioc_writeb(0, IOC_IRQMASKA); + ioc_writeb(0, IOC_IRQMASKB); + ioc_writeb(0, IOC_FIQMASK); + + for (irq = 0; irq < NR_IRQS; irq++) { + switch (irq) { + case 0 ... 6: + irq_desc[irq].probe_ok = 1; + irq_desc[irq].valid = 1; + irq_desc[irq].mask_ack = arc_mask_irq_ack_a; + irq_desc[irq].mask = arc_mask_irq_a; + irq_desc[irq].unmask = arc_unmask_irq_a; + break; + + case 7: + irq_desc[irq].noautoenable = 1; + irq_desc[irq].valid = 1; + irq_desc[irq].mask_ack = arc_mask_irq_ack_a; + irq_desc[irq].mask = arc_mask_irq_a; + irq_desc[irq].unmask = arc_unmask_irq_a; + break; + + case 9 ... 15: + irq_desc[irq].probe_ok = 1; + case 8: + irq_desc[irq].valid = 1; + irq_desc[irq].mask_ack = arc_mask_irq_b; + irq_desc[irq].mask = arc_mask_irq_b; + irq_desc[irq].unmask = arc_unmask_irq_b; + break; + + case 64 ... 72: + irq_desc[irq].valid = 1; + irq_desc[irq].mask_ack = arc_mask_irq_fiq; + irq_desc[irq].mask = arc_mask_irq_fiq; + irq_desc[irq].unmask = arc_unmask_irq_fiq; + break; + } + } + + irq_desc[IRQ_KEYBOARDTX].noautoenable = 1; + + init_FIQ(); +} + diff -urN linux-2.5.2-pre8/arch/arm/mach-arc/mm.c linux/arch/arm/mach-arc/mm.c --- linux-2.5.2-pre8/arch/arm/mach-arc/mm.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-arc/mm.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,184 @@ +/* + * linux/arch/arm/mm/mm-armo.c + * + * Copyright (C) 1998-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Page table sludge for older ARM processor architectures. + */ +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#define MEMC_TABLE_SIZE (256*sizeof(unsigned long)) + +kmem_cache_t *pte_cache, *pgd_cache; +int page_nr; + +/* + * Allocate a page table. Note that we place the MEMC + * table before the page directory. This means we can + * easily get to both tightly-associated data structures + * with a single pointer. + */ +static inline pgd_t *alloc_pgd_table(int priority) +{ + void *pg2k = kmem_cache_alloc(pgd_cache, GFP_KERNEL); + + if (pg2k) + pg2k += MEMC_TABLE_SIZE; + + return (pgd_t *)pg2k; +} + +void free_pgd_slow(pgd_t *pgd) +{ + unsigned long tbl = (unsigned long)pgd; + + /* + * CHECKME: are we leaking pte tables here??? + */ + + tbl -= MEMC_TABLE_SIZE; + + kmem_cache_free(pgd_cache, (void *)tbl); +} + +pgd_t *get_pgd_slow(struct mm_struct *mm) +{ + pgd_t *new_pgd, *init_pgd; + pmd_t *new_pmd, *init_pmd; + pte_t *new_pte, *init_pte; + + new_pgd = alloc_pgd_table(GFP_KERNEL); + if (!new_pgd) + goto no_pgd; + + /* + * This lock is here just to satisfy pmd_alloc and pte_lock + */ + spin_lock(&mm->page_table_lock); + + /* + * On ARM, first page must always be allocated since it contains + * the machine vectors. + */ + new_pmd = pmd_alloc(mm, new_pgd, 0); + if (!new_pmd) + goto no_pmd; + + new_pte = pte_alloc(mm, new_pmd, 0); + if (!new_pte) + goto no_pte; + + init_pgd = pgd_offset_k(0); + init_pmd = pmd_offset(init_pgd, 0); + init_pte = pte_offset(init_pmd, 0); + + set_pte(new_pte, *init_pte); + + /* + * most of the page table entries are zeroed + * wne the table is created. + */ + memcpy(new_pgd + USER_PTRS_PER_PGD, init_pgd + USER_PTRS_PER_PGD, + (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); + + spin_unlock(&mm->page_table_lock); + + /* update MEMC tables */ + cpu_memc_update_all(new_pgd); + return new_pgd; + +no_pte: + spin_unlock(&mm->page_table_lock); + pmd_free(new_pmd); + free_pgd_slow(new_pgd); + return NULL; + +no_pmd: + spin_unlock(&mm->page_table_lock); + free_pgd_slow(new_pgd); + return NULL; + +no_pgd: + return NULL; +} + +/* + * No special code is required here. + */ +void setup_mm_for_reboot(char mode) +{ +} + +/* + * This contains the code to setup the memory map on an ARM2/ARM250/ARM3 + * machine. This is both processor & architecture specific, and requires + * some more work to get it to fit into our separate processor and + * architecture structure. + */ +void __init memtable_init(struct meminfo *mi) +{ + pte_t *pte; + int i; + + page_nr = max_low_pfn; + + pte = alloc_bootmem_low_pages(PTRS_PER_PTE * sizeof(pte_t)); + pte[0] = mk_pte_phys(PAGE_OFFSET + 491520, PAGE_READONLY); + pmd_populate(&init_mm, pmd_offset(swapper_pg_dir, 0), pte); + + for (i = 1; i < PTRS_PER_PGD; i++) + pgd_val(swapper_pg_dir[i]) = 0; +} + +void __init iotable_init(struct map_desc *io_desc) +{ + /* nothing to do */ +} + +/* + * We never have holes in the memmap + */ +void __init create_memmap_holes(struct meminfo *mi) +{ +} + +static void pte_cache_ctor(void *pte, kmem_cache_t *cache, unsigned long flags) +{ + memzero(pte, sizeof(pte_t) * PTRS_PER_PTE); +} + +static void pgd_cache_ctor(void *pte, kmem_cache_t *cache, unsigned long flags) +{ + pgd_t *pgd = (pte + MEMC_TABLE_SIZE); + + memzero(pgd, USER_PTRS_PER_PGD * sizeof(pgd_t)); +} + +void __init pgtable_cache_init(void) +{ + pte_cache = kmem_cache_create("pte-cache", + sizeof(pte_t) * PTRS_PER_PTE, + 0, 0, pte_cache_ctor, NULL); + if (!pte_cache) + BUG(); + + pgd_cache = kmem_cache_create("pgd-cache", MEMC_TABLE_SIZE + + sizeof(pgd_t) * PTRS_PER_PGD, + 0, 0, pgd_cache_ctor, NULL); + if (!pgd_cache) + BUG(); +} diff -urN linux-2.5.2-pre8/arch/arm/mach-arc/oldlatches.c linux/arch/arm/mach-arc/oldlatches.c --- linux-2.5.2-pre8/arch/arm/mach-arc/oldlatches.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-arc/oldlatches.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,72 @@ +/* + * linux/arch/arm/kernel/oldlatches.c + * + * Copyright (C) David Alan Gilbert 1995/1996,2000 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Support for the latches on the old Archimedes which control the floppy, + * hard disc and printer + */ +#include +#include +#include +#include + +#include +#include +#include +#include + +static unsigned char latch_a_copy; +static unsigned char latch_b_copy; + +/* newval=(oldval & ~mask)|newdata */ +void oldlatch_aupdate(unsigned char mask,unsigned char newdata) +{ + if (machine_is_archimedes()) { + unsigned long flags; + + local_save_flags(flags); + latch_a_copy = (latch_a_copy & ~mask) | newdata; + __raw_writeb(latch_a_copy, LATCHA_BASE); + local_restore_flags(flags); + + printk("Latch: A = 0x%02x\n", latch_a_copy); + } else + BUG(); +} + + +/* newval=(oldval & ~mask)|newdata */ +void oldlatch_bupdate(unsigned char mask,unsigned char newdata) +{ + if (machine_is_archimedes()) { + unsigned long flags; + + local_save_flags(flags); + latch_b_copy = (latch_b_copy & ~mask) | newdata; + __raw_writeb(latch_b_copy, LATCHB_BASE); + local_restore_flags(flags); + + printk("Latch: B = 0x%02x\n", latch_b_copy); + } else + BUG(); +} + +static int __init oldlatch_init(void) +{ + if (machine_is_archimedes()) { + oldlatch_aupdate(0xff, 0xff); + /* Thats no FDC reset...*/ + oldlatch_bupdate(0xff, LATCHB_FDCRESET); + } + return 0; +} + +__initcall(oldlatch_init); + +EXPORT_SYMBOL(oldlatch_aupdate); +EXPORT_SYMBOL(oldlatch_bupdate); diff -urN linux-2.5.2-pre8/arch/arm/mach-clps711x/Makefile linux/arch/arm/mach-clps711x/Makefile --- linux-2.5.2-pre8/arch/arm/mach-clps711x/Makefile Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-clps711x/Makefile Sat Jan 5 14:43:15 2002 @@ -0,0 +1,29 @@ +# +# Makefile for the linux kernel. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). + +USE_STANDARD_AS_RULE := true + +O_TARGET := clps711x.o + +# Object file lists. + +obj-y := irq.o mm.o time.o +obj-m := +obj-n := +obj- := + +export-objs := leds-p720t.o + +obj-$(CONFIG_ARCH_AUTCPU12) += autcpu12.o +obj-$(CONFIG_ARCH_CDB89712) += cdb89712.o +obj-$(CONFIG_ARCH_CLEP7312) += clep7312.o +obj-$(CONFIG_ARCH_EDB7211) += edb7211-arch.o edb7211-mm.o +obj-$(CONFIG_ARCH_P720T) += p720t.o +leds-$(CONFIG_ARCH_P720T) += p720t-leds.o +obj-$(CONFIG_LEDS) += $(leds-y) + +include $(TOPDIR)/Rules.make diff -urN linux-2.5.2-pre8/arch/arm/mach-clps711x/autcpu12.c linux/arch/arm/mach-clps711x/autcpu12.c --- linux-2.5.2-pre8/arch/arm/mach-clps711x/autcpu12.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-clps711x/autcpu12.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,72 @@ +/* + * linux/arch/arm/mach-clps711x/autcpu12.c + * + * (c) 2001 Thomas Gleixner, autronix automation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +extern void clps711x_map_io(void); +extern void clps711x_init_irq(void); + +/* + * The on-chip registers are given a size of 1MB so that a section can + * be used to map them; this saves a page table. This is the place to + * add mappings for ROM, expansion memory, PCMCIA, etc. (if static + * mappings are chosen for those areas). + * +*/ + +static struct map_desc autcpu12_io_desc[] __initdata = { + /* virtual, physical, length, domain, r, w, c, b */ + /* memory-mapped extra io and CS8900A Ethernet chip */ + /* ethernet chip */ + { AUTCPU12_VIRT_CS8900A, AUTCPU12_PHYS_CS8900A, SZ_1M, DOMAIN_IO, 1, 1, 0, 0 }, + + LAST_DESC +}; + +void __init autcpu12_map_io(void) +{ + clps711x_map_io(); + iotable_init(autcpu12_io_desc); +} + +MACHINE_START(AUTCPU12, "autronix autcpu12") + MAINTAINER("Thomas Gleixner") + BOOT_MEM(0xc0000000, 0x80000000, 0xff000000) + BOOT_PARAMS(0xc0020000) + MAPIO(autcpu12_map_io) + INITIRQ(clps711x_init_irq) +MACHINE_END + diff -urN linux-2.5.2-pre8/arch/arm/mach-clps711x/cdb89712.c linux/arch/arm/mach-clps711x/cdb89712.c --- linux-2.5.2-pre8/arch/arm/mach-clps711x/cdb89712.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-clps711x/cdb89712.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,75 @@ +/* + * linux/arch/arm/mach-clps711x/cdb89712.c + * + * Copyright (C) 2000-2001 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +extern void clps711x_init_irq(void); +extern void clps711x_map_io(void); + +/* + * Map the CS89712 Ethernet port. That should be moved to the + * ethernet driver, perhaps. + */ +static struct map_desc cdb89712_io_desc[] __initdata = { + { ETHER_BASE, ETHER_START, ETHER_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, + LAST_DESC +}; + +static void __init +fixup_cdb89712(struct machine_desc *desc, struct param_struct *params, + char **cmdline, struct meminfo *mi) +{ +} + +static void __init cdb89712_map_io(void) +{ + clps711x_map_io(); + iotable_init(cdb89712_io_desc); +} + +MACHINE_START(CDB89712, "Cirrus-CDB89712") + MAINTAINER("Ray Lehtiniemi") + BOOT_MEM(0xc0000000, 0x80000000, 0xff000000) + BOOT_PARAMS(0xc0000100) + FIXUP(fixup_cdb89712) + MAPIO(cdb89712_map_io) + INITIRQ(clps711x_init_irq) +MACHINE_END + +static int cdb89712_hw_init(void) +{ + return 0; +} + +__initcall(cdb89712_hw_init); + diff -urN linux-2.5.2-pre8/arch/arm/mach-clps711x/clep7312.c linux/arch/arm/mach-clps711x/clep7312.c --- linux-2.5.2-pre8/arch/arm/mach-clps711x/clep7312.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-clps711x/clep7312.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,49 @@ +/* + * linux/arch/arm/mach-clps711x/clep7312.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include + +#include +#include +#include + +extern void clps711x_init_irq(void); +extern void clps711x_map_io(void); + +static void __init +fixup_clep7312(struct machine_desc *desc, struct param_struct *params, + char **cmdline, struct meminfo *mi) +{ + mi->nr_banks=1; + mi->end = 0xc0FFFFFF; + mi->bank[0].start = 0xc0000000; + mi->bank[0].size = 0x01000000; + mi->bank[0].node = 0; +} + + +MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312") + MAINTAINER("Nobody") + BOOT_MEM(0xc0000000, 0x80000000, 0xff000000) + BOOT_PARAMS(0xc0000100) + FIXUP(fixup_clep7312) + MAPIO(clps711x_map_io) + INITIRQ(clps711x_init_irq) +MACHINE_END + diff -urN linux-2.5.2-pre8/arch/arm/mach-clps711x/dma.c linux/arch/arm/mach-clps711x/dma.c --- linux-2.5.2-pre8/arch/arm/mach-clps711x/dma.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-clps711x/dma.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,35 @@ +/* + * linux/arch/arm/mach-clps711x/dma.c + * + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +void __init arch_dma_init(dma_t *dma) +{ +} diff -urN linux-2.5.2-pre8/arch/arm/mach-clps711x/edb7211-arch.c linux/arch/arm/mach-clps711x/edb7211-arch.c --- linux-2.5.2-pre8/arch/arm/mach-clps711x/edb7211-arch.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-clps711x/edb7211-arch.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,59 @@ +/* + * linux/arch/arm/mach-clps711x/arch-edb7211.c + * + * Copyright (C) 2000, 2001 Blue Mug, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include + +#include +#include +#include + +extern void clps711x_init_irq(void); +extern void edb7211_map_io(void); + +static void __init +fixup_edb7211(struct machine_desc *desc, struct param_struct *params, + char **cmdline, struct meminfo *mi) +{ + /* + * Bank start addresses are not present in the information + * passed in from the boot loader. We could potentially + * detect them, but instead we hard-code them. + * + * Banks sizes _are_ present in the param block, but we're + * not using that information yet. + */ + mi->bank[0].start = 0xc0000000; + mi->bank[0].size = 8*1024*1024; + mi->bank[0].node = 0; + mi->bank[1].start = 0xc1000000; + mi->bank[1].size = 8*1024*1024; + mi->bank[1].node = 1; + mi->nr_banks = 2; +} + +MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") + MAINTAINER("Jon McClintock") + BOOT_MEM(0xc0000000, 0x80000000, 0xff000000) + BOOT_PARAMS(0xc0020100) /* 0xc0000000 - 0xc001ffff can be video RAM */ + FIXUP(fixup_edb7211) + MAPIO(edb7211_map_io) + INITIRQ(clps711x_init_irq) +MACHINE_END diff -urN linux-2.5.2-pre8/arch/arm/mach-clps711x/edb7211-mm.c linux/arch/arm/mach-clps711x/edb7211-mm.c --- linux-2.5.2-pre8/arch/arm/mach-clps711x/edb7211-mm.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-clps711x/edb7211-mm.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,74 @@ +/* + * linux/arch/arm/mach-clps711x/mm.c + * + * Extra MM routines for the EDB7211 board + * + * Copyright (C) 2000, 2001 Blue Mug, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include + +#include +#include +#include + +#include + +#define MB1 1048576 /* one megabyte == size of an MMU section */ + +extern void clps711x_map_io(void); + +/* + * The on-chip registers are given a size of 1MB so that a section can + * be used to map them; this saves a page table. This is the place to + * add mappings for ROM, expansion memory, PCMCIA, etc. (if static + * mappings are chosen for those areas). + * + * Here is a physical memory map (to be fleshed out later): + * + * Physical Address Size Description + * ----------------- ----- --------------------------------- + * c0000000-c001ffff 128KB reserved for video RAM [1] + * c0020000-c0023fff 16KB parameters (see Documentation/arm/Setup) + * c0024000-c0027fff 16KB swapper_pg_dir (task 0 page directory) + * c0028000-... kernel image (TEXTADDR) + * + * [1] Unused pages should be given back to the VM; they are not yet. + * The parameter block should also be released (not sure if this + * happens). + */ +static struct map_desc edb7211_io_desc[] __initdata = { + /* virtual, physical, length, domain, r, w, c, b */ + + /* memory-mapped extra keyboard row and CS8900A Ethernet chip */ + { EP7211_VIRT_EXTKBD, EP7211_PHYS_EXTKBD, MB1, DOMAIN_IO, 1, 1, 0, 0 }, + { EP7211_VIRT_CS8900A, EP7211_PHYS_CS8900A, MB1, DOMAIN_IO, 1, 1, 0, 0 }, + + /* flash banks */ + { EP7211_VIRT_FLASH1, EP7211_PHYS_FLASH1, MB1 * 8, DOMAIN_KERNEL, 1, 1, 0, 0 }, + { EP7211_VIRT_FLASH2, EP7211_PHYS_FLASH2, MB1 * 8, DOMAIN_KERNEL, 1, 1, 0, 0 }, + + LAST_DESC +}; + +void __init edb7211_map_io(void) +{ + clps711x_map_io(); + iotable_init(edb7211_io_desc); +} + diff -urN linux-2.5.2-pre8/arch/arm/mach-clps711x/irq.c linux/arch/arm/mach-clps711x/irq.c --- linux-2.5.2-pre8/arch/arm/mach-clps711x/irq.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-clps711x/irq.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,138 @@ +/* + * linux/arch/arm/mach-clps711x/irq.c + * + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include + +#include +#include +#include +#include + +#include + +static void mask_irq_int1(unsigned int irq) +{ + u32 intmr1; + + intmr1 = clps_readl(INTMR1); + intmr1 &= ~(1 << irq); + clps_writel(intmr1, INTMR1); +} + +static void mask_ack_irq_int1(unsigned int irq) +{ + u32 intmr1; + + intmr1 = clps_readl(INTMR1); + intmr1 &= ~(1 << irq); + clps_writel(intmr1, INTMR1); + + switch (irq) { + case IRQ_CSINT: clps_writel(0, COEOI); break; + case IRQ_TC1OI: clps_writel(0, TC1EOI); break; + case IRQ_TC2OI: clps_writel(0, TC2EOI); break; + case IRQ_RTCMI: clps_writel(0, RTCEOI); break; + case IRQ_TINT: clps_writel(0, TEOI); break; + case IRQ_UMSINT: clps_writel(0, UMSEOI); break; + } +} + +static void unmask_irq_int1(unsigned int irq) +{ + u32 intmr1; + + intmr1 = clps_readl(INTMR1); + intmr1 |= 1 << irq; + clps_writel(intmr1, INTMR1); +} + +static void mask_irq_int2(unsigned int irq) +{ + u32 intmr2; + + intmr2 = clps_readl(INTMR2); + intmr2 &= ~(1 << (irq - 16)); + clps_writel(intmr2, INTMR2); +} + +static void mask_ack_irq_int2(unsigned int irq) +{ + u32 intmr2; + + intmr2 = clps_readl(INTMR2); + intmr2 &= ~(1 << (irq - 16)); + clps_writel(intmr2, INTMR2); + + switch (irq) { + case IRQ_KBDINT: clps_writel(0, KBDEOI); break; + } +} + +static void unmask_irq_int2(unsigned int irq) +{ + u32 intmr2; + + intmr2 = clps_readl(INTMR2); + intmr2 |= 1 << (irq - 16); + clps_writel(intmr2, INTMR2); +} + +void __init clps711x_init_irq(void) +{ + unsigned int i; + + for (i = 0; i < NR_IRQS; i++) { + if (INT1_IRQS & (1 << i)) { + irq_desc[i].valid = 1; + irq_desc[i].probe_ok = 1; + irq_desc[i].mask_ack = (INT1_ACK_IRQS & (1 << i)) ? + mask_ack_irq_int1 : + mask_irq_int1; + irq_desc[i].mask = mask_irq_int1; + irq_desc[i].unmask = unmask_irq_int1; + } + if (INT2_IRQS & (1 << i)) { + irq_desc[i].valid = 1; + irq_desc[i].probe_ok = 1; + irq_desc[i].mask_ack = (INT2_ACK_IRQS & (1 << i)) ? + mask_ack_irq_int2 : + mask_irq_int2; + irq_desc[i].mask = mask_irq_int2; + irq_desc[i].unmask = unmask_irq_int2; + } + } + + /* + * Disable interrupts + */ + clps_writel(0, INTMR1); + clps_writel(0, INTMR2); + + /* + * Clear down any pending interrupts + */ + clps_writel(0, COEOI); + clps_writel(0, TC1EOI); + clps_writel(0, TC2EOI); + clps_writel(0, RTCEOI); + clps_writel(0, TEOI); + clps_writel(0, UMSEOI); + clps_writel(0, SYNCIO); + clps_writel(0, KBDEOI); +} diff -urN linux-2.5.2-pre8/arch/arm/mach-clps711x/mm.c linux/arch/arm/mach-clps711x/mm.c --- linux-2.5.2-pre8/arch/arm/mach-clps711x/mm.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-clps711x/mm.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,70 @@ +/* + * linux/arch/arm/mach-clps711x/mm.c + * + * Generic MM setup for the CLPS711x-based machines. + * + * Copyright (C) 2001 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#if 0 //def CONFIG_DISCONTIGMEM + +/* + * The assumption of maximum 4 discontiguous memory banks is present + * in several places in the ARM kernel, including the parameter block + * (this affects boot loaders, too). Banks do not necessarily + * correspond 1:1 with NUMA nodes, although they usually will, + * especially if they are widely discontiguous. + * + * - note that the parameter block is depreciated for new implementations + * - also note that discontig_node_data is actually used + * -- rmk + */ + +static bootmem_data_t node_bootmem_data[4]; + +pg_data_t clps711x_node_data[4] = { + { bdata: &node_bootmem_data[0] }, + { bdata: &node_bootmem_data[1] }, + { bdata: &node_bootmem_data[2] }, + { bdata: &node_bootmem_data[3] }, +}; + +#endif + +/* + * This maps the generic CLPS711x registers + */ +static struct map_desc clps711x_io_desc[] __initdata = { + { CLPS7111_VIRT_BASE, CLPS7111_PHYS_BASE, 1048576, DOMAIN_IO, 0, 1 }, + LAST_DESC +}; + +void __init clps711x_map_io(void) +{ + iotable_init(clps711x_io_desc); +} diff -urN linux-2.5.2-pre8/arch/arm/mach-clps711x/p720t-leds.c linux/arch/arm/mach-clps711x/p720t-leds.c --- linux-2.5.2-pre8/arch/arm/mach-clps711x/p720t-leds.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-clps711x/p720t-leds.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,67 @@ +/* + * linux/arch/arm/mach-clps711x/leds.c + * + * Integrator LED control routines + * + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +static void p720t_leds_event(led_event_t ledevt) +{ + unsigned long flags; + u32 pddr; + + local_irq_save(flags); + switch(ledevt) { + case led_idle_start: + break; + + case led_idle_end: + break; + + case led_timer: + pddr = clps_readb(PDDR); + clps_writeb(pddr ^ 1, PDDR); + break; + + default: + break; + } + + local_irq_restore(flags); +} + +static int __init leds_init(void) +{ + if (machine_is_p720t()) + leds_event = p720t_leds_event; + + return 0; +} + +__initcall(leds_init); diff -urN linux-2.5.2-pre8/arch/arm/mach-clps711x/p720t.c linux/arch/arm/mach-clps711x/p720t.c --- linux-2.5.2-pre8/arch/arm/mach-clps711x/p720t.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-clps711x/p720t.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,118 @@ +/* + * linux/arch/arm/mach-clps711x/p720t.c + * + * Copyright (C) 2000-2001 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void clps711x_init_irq(void); +extern void clps711x_map_io(void); + +/* + * Map the P720T system PLD. It occupies two address spaces: + * SYSPLD_PHYS_BASE and SYSPLD_PHYS_BASE + 0x00400000 + * We map both here. + */ +static struct map_desc p720t_io_desc[] __initdata = { + { SYSPLD_VIRT_BASE, SYSPLD_PHYS_BASE, 1048576, DOMAIN_IO, 0, 1 }, + { 0xfe400000, 0x10400000, 1048576, DOMAIN_IO, 0, 1 }, + LAST_DESC +}; + +static void __init +fixup_p720t(struct machine_desc *desc, struct param_struct *params, + char **cmdline, struct meminfo *mi) +{ + struct tag *tag = (struct tag *)params; + + /* + * Our bootloader doesn't setup any tags (yet). + */ + if (tag->hdr.tag != ATAG_CORE) { + tag->hdr.tag = ATAG_CORE; + tag->hdr.size = tag_size(tag_core); + tag->u.core.flags = 0; + tag->u.core.pagesize = PAGE_SIZE; + tag->u.core.rootdev = 0x0100; + + tag = tag_next(tag); + tag->hdr.tag = ATAG_MEM; + tag->hdr.size = tag_size(tag_mem32); + tag->u.mem.size = 4096; + tag->u.mem.start = PHYS_OFFSET; + + tag = tag_next(tag); + tag->hdr.tag = ATAG_NONE; + tag->hdr.size = 0; + } +} + +static void __init p720t_map_io(void) +{ + clps711x_map_io(); + iotable_init(p720t_io_desc); +} + +MACHINE_START(P720T, "ARM-Prospector720T") + MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd") + BOOT_MEM(0xc0000000, 0x80000000, 0xff000000) + BOOT_PARAMS(0xc0000100) + FIXUP(fixup_p720t) + MAPIO(p720t_map_io) + INITIRQ(clps711x_init_irq) +MACHINE_END + +static int p720t_hw_init(void) +{ + /* + * Power down as much as possible in case we don't + * have the drivers loaded. + */ + PLD_LCDEN = 0; + PLD_PWR &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON); + + PLD_KBD = 0; + PLD_IO = 0; + PLD_IRDA = 0; + PLD_CODEC = 0; + PLD_TCH = 0; + PLD_SPI = 0; +#ifndef CONFIG_DEBUG_LL + PLD_COM2 = 0; + PLD_COM1 = 0; +#endif + + return 0; +} + +__initcall(p720t_hw_init); + diff -urN linux-2.5.2-pre8/arch/arm/mach-clps711x/time.c linux/arch/arm/mach-clps711x/time.c --- linux-2.5.2-pre8/arch/arm/mach-clps711x/time.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-clps711x/time.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,54 @@ +/* + * linux/arch/arm/mach-clps711x/time.c + * + * Copyright (C) 2001 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include + +#include +#include +#include + +extern unsigned long (*gettimeoffset)(void); + +/* + * gettimeoffset() returns time since last timer tick, in usecs. + * + * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy. + * 'tick' is usecs per jiffy. + */ +static unsigned long clps711x_gettimeoffset(void) +{ + unsigned long hwticks; + hwticks = LATCH - (clps_readl(TC2D) & 0xffff); /* since last underflow */ + return (hwticks * tick) / LATCH; +} + +void __init clps711x_setup_timer(void) +{ + unsigned int syscon; + + gettimeoffset = clps711x_gettimeoffset; + + syscon = clps_readl(SYSCON1); + syscon |= SYSCON1_TC2S | SYSCON1_TC2M; + clps_writel(syscon, SYSCON1); + + clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */ + + xtime.tv_sec = clps_readl(RTCDR); +} diff -urN linux-2.5.2-pre8/arch/arm/mach-clps7500/Makefile linux/arch/arm/mach-clps7500/Makefile --- linux-2.5.2-pre8/arch/arm/mach-clps7500/Makefile Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-clps7500/Makefile Sat Jan 5 14:43:15 2002 @@ -0,0 +1,21 @@ +# +# Makefile for the linux kernel. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). + +USE_STANDARD_AS_RULE := true + +O_TARGET := clps7500.o + +# Object file lists. + +obj-y := core.o +obj-m := +obj-n := +obj- := + +export-objs := + +include $(TOPDIR)/Rules.make diff -urN linux-2.5.2-pre8/arch/arm/mach-clps7500/core.c linux/arch/arm/mach-clps7500/core.c --- linux-2.5.2-pre8/arch/arm/mach-clps7500/core.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-clps7500/core.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,236 @@ +/* + * linux/arch/arm/mm/mm-cl7500.c + * + * Copyright (C) 1998 Russell King + * Copyright (C) 1999 Nexus Electronics Ltd + * + * Extra MM routines for CL7500 architecture + */ +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +static void cl7500_mask_irq_ack_a(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << irq; + val = iomd_readb(IOMD_IRQMASKA); + iomd_writeb(val & ~mask, IOMD_IRQMASKA); + iomd_writeb(mask, IOMD_IRQCLRA); +} + +static void cl7500_mask_irq_a(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << irq; + val = iomd_readb(IOMD_IRQMASKA); + iomd_writeb(val & ~mask, IOMD_IRQMASKA); +} + +static void cl7500_unmask_irq_a(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << irq; + val = iomd_readb(IOMD_IRQMASKA); + iomd_writeb(val | mask, IOMD_IRQMASKA); +} + +static void cl7500_mask_irq_b(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_IRQMASKB); + iomd_writeb(val & ~mask, IOMD_IRQMASKB); +} + +static void cl7500_unmask_irq_b(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_IRQMASKB); + iomd_writeb(val | mask, IOMD_IRQMASKB); +} + +static void cl7500_mask_irq_c(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_IRQMASKC); + iomd_writeb(val & ~mask, IOMD_IRQMASKC); +} + +static void cl7500_unmask_irq_c(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_IRQMASKC); + iomd_writeb(val | mask, IOMD_IRQMASKC); +} + + +static void cl7500_mask_irq_d(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_IRQMASKD); + iomd_writeb(val & ~mask, IOMD_IRQMASKD); +} + +static void cl7500_unmask_irq_d(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_IRQMASKD); + iomd_writeb(val | mask, IOMD_IRQMASKD); +} + +static void cl7500_mask_irq_dma(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_DMAMASK); + iomd_writeb(val & ~mask, IOMD_DMAMASK); +} + +static void cl7500_unmask_irq_dma(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_DMAMASK); + iomd_writeb(val | mask, IOMD_DMAMASK); +} + +static void cl7500_mask_irq_fiq(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_FIQMASK); + iomd_writeb(val & ~mask, IOMD_FIQMASK); +} + +static void cl7500_unmask_irq_fiq(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_FIQMASK); + iomd_writeb(val | mask, IOMD_FIQMASK); +} + +static void no_action(int cpl, void *dev_id, struct pt_regs *regs) +{ +} + +static struct irqaction irq_isa = { no_action, 0, 0, "isa", NULL, NULL }; + +static void __init clps7500_init_irq(void) +{ + int irq; + + iomd_writeb(0, IOMD_IRQMASKA); + iomd_writeb(0, IOMD_IRQMASKB); + iomd_writeb(0, IOMD_FIQMASK); + iomd_writeb(0, IOMD_DMAMASK); + + for (irq = 0; irq < NR_IRQS; irq++) { + switch (irq) { + case 0 ... 6: + irq_desc[irq].probe_ok = 1; + case 7: + irq_desc[irq].valid = 1; + irq_desc[irq].mask_ack = cl7500_mask_irq_ack_a; + irq_desc[irq].mask = cl7500_mask_irq_a; + irq_desc[irq].unmask = cl7500_unmask_irq_a; + break; + + case 9 ... 15: + irq_desc[irq].probe_ok = 1; + case 8: + irq_desc[irq].valid = 1; + irq_desc[irq].mask_ack = cl7500_mask_irq_b; + irq_desc[irq].mask = cl7500_mask_irq_b; + irq_desc[irq].unmask = cl7500_unmask_irq_b; + break; + + case 16 ... 22: + irq_desc[irq].valid = 1; + irq_desc[irq].mask_ack = cl7500_mask_irq_dma; + irq_desc[irq].mask = cl7500_mask_irq_dma; + irq_desc[irq].unmask = cl7500_unmask_irq_dma; + break; + + case 24 ... 31: + irq_desc[irq].valid = 1; + irq_desc[irq].mask_ack = cl7500_mask_irq_c; + irq_desc[irq].mask = cl7500_mask_irq_c; + irq_desc[irq].unmask = cl7500_unmask_irq_c; + break; + + case 40 ... 47: + irq_desc[irq].valid = 1; + irq_desc[irq].mask_ack = cl7500_mask_irq_d; + irq_desc[irq].mask = cl7500_mask_irq_d; + irq_desc[irq].unmask = cl7500_unmask_irq_d; + break; + + case 48 ... 55: + irq_desc[irq].valid = 1; + irq_desc[irq].probe_ok = 1; + irq_desc[irq].mask_ack = no_action; + irq_desc[irq].mask = no_action; + irq_desc[irq].unmask = no_action; + break; + + case 64 ... 72: + irq_desc[irq].valid = 1; + irq_desc[irq].mask_ack = cl7500_mask_irq_fiq; + irq_desc[irq].mask = cl7500_mask_irq_fiq; + irq_desc[irq].unmask = cl7500_unmask_irq_fiq; + break; + } + } + + setup_arm_irq(IRQ_ISA, &irq_isa); +} + +static struct map_desc cl7500_io_desc[] __initdata = { + { IO_BASE, IO_START, IO_SIZE , DOMAIN_IO, 0, 1 }, /* IO space */ + { ISA_BASE, ISA_START, ISA_SIZE , DOMAIN_IO, 0, 1 }, /* ISA space */ + { FLASH_BASE, FLASH_START, FLASH_SIZE, DOMAIN_IO, 0, 1 }, /* Flash */ + { LED_BASE, LED_START, LED_SIZE , DOMAIN_IO, 0, 1 }, /* LED */ + LAST_DESC +}; + +static void __init clps7500_map_io(void) +{ + iotable_init(cl7500_io_desc); +} + +MACHINE_START(CLPS7500, "CL-PS7500") + MAINTAINER("Philip Blundell") + BOOT_MEM(0x10000000, 0x03000000, 0xe0000000) + MAPIO(clps7500_map_io) + INITIRQ(clps7500_init_irq) +MACHINE_END + diff -urN linux-2.5.2-pre8/arch/arm/mach-ebsa110/Makefile linux/arch/arm/mach-ebsa110/Makefile --- linux-2.5.2-pre8/arch/arm/mach-ebsa110/Makefile Thu Apr 12 12:20:31 2001 +++ linux/arch/arm/mach-ebsa110/Makefile Sat Jan 5 14:43:15 2002 @@ -11,7 +11,7 @@ # Object file lists. -obj-y := arch.o io.o irq.o mm.o time.o +obj-y := core.o io.o time.o obj-m := obj-n := obj- := diff -urN linux-2.5.2-pre8/arch/arm/mach-ebsa110/arch.c linux/arch/arm/mach-ebsa110/arch.c --- linux-2.5.2-pre8/arch/arm/mach-ebsa110/arch.c Wed Jun 27 14:12:04 2001 +++ linux/arch/arm/mach-ebsa110/arch.c Wed Dec 31 16:00:00 1969 @@ -1,30 +0,0 @@ -/* - * linux/arch/arm/mach-ebsa110/arch.c - * - * Architecture specific fixups. - */ -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -extern void ebsa110_map_io(void); -extern void ebsa110_init_irq(void); - -MACHINE_START(EBSA110, "EBSA110") - MAINTAINER("Russell King") - BOOT_MEM(0x00000000, 0xe0000000, 0xe0000000) - BOOT_PARAMS(0x00000400) - DISABLE_PARPORT(0) - DISABLE_PARPORT(2) - SOFT_REBOOT - MAPIO(ebsa110_map_io) - INITIRQ(ebsa110_init_irq) -MACHINE_END diff -urN linux-2.5.2-pre8/arch/arm/mach-ebsa110/core.c linux/arch/arm/mach-ebsa110/core.c --- linux-2.5.2-pre8/arch/arm/mach-ebsa110/core.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-ebsa110/core.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,97 @@ +/* + * linux/arch/arm/mach-ebsa110/core.c + * + * Copyright (C) 1998-2001 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Extra MM routines for the EBSA-110 architecture + */ +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define IRQ_MASK 0xfe000000 /* read */ +#define IRQ_MSET 0xfe000000 /* write */ +#define IRQ_STAT 0xff000000 /* read */ +#define IRQ_MCLR 0xff000000 /* write */ + +static void ebsa110_mask_irq(unsigned int irq) +{ + __raw_writeb(1 << irq, IRQ_MCLR); +} + +static void ebsa110_unmask_irq(unsigned int irq) +{ + __raw_writeb(1 << irq, IRQ_MSET); +} + +static void __init ebsa110_init_irq(void) +{ + unsigned long flags; + int irq; + + save_flags_cli (flags); + __raw_writeb(0xff, IRQ_MCLR); + __raw_writeb(0x55, IRQ_MSET); + __raw_writeb(0x00, IRQ_MSET); + if (__raw_readb(IRQ_MASK) != 0x55) + while (1); + __raw_writeb(0xff, IRQ_MCLR); /* clear all interrupt enables */ + restore_flags (flags); + + for (irq = 0; irq < NR_IRQS; irq++) { + irq_desc[irq].valid = 1; + irq_desc[irq].probe_ok = 1; + irq_desc[irq].mask_ack = ebsa110_mask_irq; + irq_desc[irq].mask = ebsa110_mask_irq; + irq_desc[irq].unmask = ebsa110_unmask_irq; + } +} + +static struct map_desc ebsa110_io_desc[] __initdata = { + /* + * sparse external-decode ISAIO space + */ + { IRQ_STAT, TRICK4_PHYS, PGDIR_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* IRQ_STAT/IRQ_MCLR */ + { IRQ_MASK, TRICK3_PHYS, PGDIR_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* IRQ_MASK/IRQ_MSET */ + { SOFT_BASE, TRICK1_PHYS, PGDIR_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* SOFT_BASE */ + { PIT_BASE, TRICK0_PHYS, PGDIR_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* PIT_BASE */ + + /* + * self-decode ISAIO space + */ + { ISAIO_BASE, ISAIO_PHYS, ISAIO_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, + { ISAMEM_BASE, ISAMEM_PHYS, ISAMEM_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, + LAST_DESC +}; + +static void __init ebsa110_map_io(void) +{ + iotable_init(ebsa110_io_desc); +} + +MACHINE_START(EBSA110, "EBSA110") + MAINTAINER("Russell King") + BOOT_MEM(0x00000000, 0xe0000000, 0xe0000000) + BOOT_PARAMS(0x00000400) + DISABLE_PARPORT(0) + DISABLE_PARPORT(2) + SOFT_REBOOT + MAPIO(ebsa110_map_io) + INITIRQ(ebsa110_init_irq) +MACHINE_END diff -urN linux-2.5.2-pre8/arch/arm/mach-ebsa110/hardware.h linux/arch/arm/mach-ebsa110/hardware.h --- linux-2.5.2-pre8/arch/arm/mach-ebsa110/hardware.h Wed Jun 27 14:12:04 2001 +++ linux/arch/arm/mach-ebsa110/hardware.h Wed Dec 31 16:00:00 1969 @@ -1,16 +0,0 @@ -/* - * linux/arch/arm/mach-ebsa110/hardware.h - * - * Copyright (C) 2001 Russell King - * - * Local hardware definitions. - */ -#ifndef HARDWARE_H -#define HARDWARE_H - -#define IRQ_MASK 0xfe000000 /* read */ -#define IRQ_MSET 0xfe000000 /* write */ -#define IRQ_STAT 0xff000000 /* read */ -#define IRQ_MCLR 0xff000000 /* write */ - -#endif diff -urN linux-2.5.2-pre8/arch/arm/mach-ebsa110/io.c linux/arch/arm/mach-ebsa110/io.c --- linux-2.5.2-pre8/arch/arm/mach-ebsa110/io.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/mach-ebsa110/io.c Sat Jan 5 14:43:15 2002 @@ -67,9 +67,9 @@ u32 ret, a = __isamem_convert_addr(addr); if ((int)addr & 1) - ret = __arch_getl(a); + ret = __raw_getl(a); else - ret = __arch_getb(a); + ret = __raw_getb(a); return ret; } @@ -80,7 +80,7 @@ if ((int)addr & 1) BUG(); - return __arch_getw(a); + return __raw_getw(a); } u32 __readl(void *addr) @@ -90,8 +90,8 @@ if ((int)addr & 3) BUG(); - ret = __arch_getw(a); - ret |= __arch_getw(a + 4) << 16; + ret = __raw_getw(a); + ret |= __raw_getw(a + 4) << 16; return ret; } @@ -104,9 +104,9 @@ u32 a = __isamem_convert_addr(addr); if ((int)addr & 1) - __arch_putl(val, a); + __raw_putl(val, a); else - __arch_putb(val, a); + __raw_putb(val, a); } void __writew(u16 val, void *addr) @@ -116,7 +116,7 @@ if ((int)addr & 1) BUG(); - __arch_putw(val, a); + __raw_putw(val, a); } void __writel(u32 val, void *addr) @@ -126,8 +126,8 @@ if ((int)addr & 3) BUG(); - __arch_putw(val, a); - __arch_putw(val >> 16, a + 4); + __raw_putw(val, a); + __raw_putw(val >> 16, a + 4); } EXPORT_SYMBOL(__writeb); @@ -147,7 +147,7 @@ * The SuperIO registers use sane addressing techniques... */ if (SUPERIO_PORT(port)) - ret = __arch_getb(ISAIO_BASE + (port << 2)); + ret = __raw_getb(ISAIO_BASE + (port << 2)); else { u32 a = ISAIO_BASE + ((port & ~1) << 1); @@ -155,9 +155,9 @@ * Shame nothing else does */ if (port & 1) - ret = __arch_getl(a); + ret = __raw_getl(a); else - ret = __arch_getb(a); + ret = __raw_getb(a); } return ret; } @@ -170,7 +170,7 @@ * The SuperIO registers use sane addressing techniques... */ if (SUPERIO_PORT(port)) - ret = __arch_getw(ISAIO_BASE + (port << 2)); + ret = __raw_getw(ISAIO_BASE + (port << 2)); else { u32 a = ISAIO_BASE + ((port & ~1) << 1); @@ -180,7 +180,7 @@ if (port & 1) BUG(); - ret = __arch_getw(a); + ret = __raw_getw(a); } return ret; } @@ -201,7 +201,7 @@ * The SuperIO registers use sane addressing techniques... */ if (SUPERIO_PORT(port)) - __arch_putb(val, ISAIO_BASE + (port << 2)); + __raw_putb(val, ISAIO_BASE + (port << 2)); else { u32 a = ISAIO_BASE + ((port & ~1) << 1); @@ -209,9 +209,9 @@ * Shame nothing else does */ if (port & 1) - __arch_putl(val, a); + __raw_putl(val, a); else - __arch_putb(val, a); + __raw_putb(val, a); } } @@ -230,7 +230,7 @@ BUG(); } - __arch_putw(val, ISAIO_BASE + off); + __raw_putw(val, ISAIO_BASE + off); } void __outl(u32 val, int port) diff -urN linux-2.5.2-pre8/arch/arm/mach-ebsa110/irq.c linux/arch/arm/mach-ebsa110/irq.c --- linux-2.5.2-pre8/arch/arm/mach-ebsa110/irq.c Thu Apr 12 12:20:31 2001 +++ linux/arch/arm/mach-ebsa110/irq.c Wed Dec 31 16:00:00 1969 @@ -1,55 +0,0 @@ -/* - * linux/arch/arm/mach-ebsa110/irq.c - * - * Copyright (C) 1996-1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 22-08-1998 RMK Restructured IRQ routines - */ -#include - -#include -#include -#include -#include -#include - -#include "hardware.h" - -static void ebsa110_mask_irq(unsigned int irq) -{ - __raw_writeb(1 << irq, IRQ_MCLR); -} - -static void ebsa110_unmask_irq(unsigned int irq) -{ - __raw_writeb(1 << irq, IRQ_MSET); -} - -void __init ebsa110_init_irq(void) -{ - unsigned long flags; - int irq; - - save_flags_cli (flags); - __raw_writeb(0xff, IRQ_MCLR); - __raw_writeb(0x55, IRQ_MSET); - __raw_writeb(0x00, IRQ_MSET); - if (__raw_readb(IRQ_MASK) != 0x55) - while (1); - __raw_writeb(0xff, IRQ_MCLR); /* clear all interrupt enables */ - restore_flags (flags); - - for (irq = 0; irq < NR_IRQS; irq++) { - irq_desc[irq].valid = 1; - irq_desc[irq].probe_ok = 1; - irq_desc[irq].mask_ack = ebsa110_mask_irq; - irq_desc[irq].mask = ebsa110_mask_irq; - irq_desc[irq].unmask = ebsa110_unmask_irq; - } -} - diff -urN linux-2.5.2-pre8/arch/arm/mach-ebsa110/mm.c linux/arch/arm/mach-ebsa110/mm.c --- linux-2.5.2-pre8/arch/arm/mach-ebsa110/mm.c Thu Apr 12 12:20:31 2001 +++ linux/arch/arm/mach-ebsa110/mm.c Wed Dec 31 16:00:00 1969 @@ -1,43 +0,0 @@ -/* - * linux/arch/arm/mach-ebsa110/mm.c - * - * Copyright (C) 1998-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Extra MM routines for the EBSA-110 architecture - */ -#include -#include - -#include -#include -#include - -#include - -#include "hardware.h" - -static struct map_desc ebsa110_io_desc[] __initdata = { - /* - * sparse external-decode ISAIO space - */ - { IRQ_STAT, TRICK4_PHYS, PGDIR_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* IRQ_STAT/IRQ_MCLR */ - { IRQ_MASK, TRICK3_PHYS, PGDIR_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* IRQ_MASK/IRQ_MSET */ - { SOFT_BASE, TRICK1_PHYS, PGDIR_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* SOFT_BASE */ - { PIT_BASE, TRICK0_PHYS, PGDIR_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* PIT_BASE */ - - /* - * self-decode ISAIO space - */ - { ISAIO_BASE, ISAIO_PHYS, ISAIO_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, - { ISAMEM_BASE, ISAMEM_PHYS, ISAMEM_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, - LAST_DESC -}; - -void __init ebsa110_map_io(void) -{ - iotable_init(ebsa110_io_desc); -} diff -urN linux-2.5.2-pre8/arch/arm/mach-epxa10db/mm.c linux/arch/arm/mach-epxa10db/mm.c --- linux-2.5.2-pre8/arch/arm/mach-epxa10db/mm.c Thu Oct 25 13:53:45 2001 +++ linux/arch/arm/mach-epxa10db/mm.c Sat Jan 5 14:43:15 2002 @@ -27,6 +27,7 @@ #include #include #include +#include #include diff -urN linux-2.5.2-pre8/arch/arm/mach-footbridge/Makefile linux/arch/arm/mach-footbridge/Makefile --- linux-2.5.2-pre8/arch/arm/mach-footbridge/Makefile Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/mach-footbridge/Makefile Sat Jan 5 14:43:15 2002 @@ -11,7 +11,7 @@ # Object file lists. -obj-y := arch.o irq.o mm.o #dma.o +obj-y := arch.o dc21285.o dma.o irq.o mm.o obj-m := obj-n := obj- := diff -urN linux-2.5.2-pre8/arch/arm/mach-footbridge/cats-pci.c linux/arch/arm/mach-footbridge/cats-pci.c --- linux-2.5.2-pre8/arch/arm/mach-footbridge/cats-pci.c Wed Jul 4 15:43:05 2001 +++ linux/arch/arm/mach-footbridge/cats-pci.c Sat Jan 5 14:43:15 2002 @@ -11,7 +11,6 @@ #include #include -#include /* cats host-specific stuff */ static int irqmap_cats[] __initdata = { IRQ_PCI, IRQ_IN0, IRQ_IN1, IRQ_IN3 }; @@ -31,10 +30,16 @@ return -1; } +/* + * why not the standard PCI swizzle? does this prevent 4-port tulip + * cards being used (ie, pci-pci bridge based cards)? + */ struct hw_pci cats_pci __initdata = { - setup_resources: dc21285_setup_resources, - init: dc21285_init, - mem_offset: DC21285_PCI_MEM, - swizzle: no_swizzle, + swizzle: NULL, map_irq: cats_map_irq, + nr_controllers: 1, + setup: dc21285_setup, + scan: dc21285_scan_bus, + preinit: dc21285_preinit, + postinit: dc21285_postinit, }; diff -urN linux-2.5.2-pre8/arch/arm/mach-footbridge/ebsa285-pci.c linux/arch/arm/mach-footbridge/ebsa285-pci.c --- linux-2.5.2-pre8/arch/arm/mach-footbridge/ebsa285-pci.c Wed Jul 4 15:43:05 2001 +++ linux/arch/arm/mach-footbridge/ebsa285-pci.c Sat Jan 5 14:43:15 2002 @@ -11,15 +11,9 @@ #include #include -#include static int irqmap_ebsa285[] __initdata = { IRQ_IN3, IRQ_IN1, IRQ_IN0, IRQ_PCI }; -static u8 __init ebsa285_swizzle(struct pci_dev *dev, u8 *pin) -{ - return PCI_SLOT(dev->devfn); -} - static int __init ebsa285_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { if (dev->vendor == PCI_VENDOR_ID_CONTAQ && @@ -34,9 +28,11 @@ } struct hw_pci ebsa285_pci __initdata = { - setup_resources: dc21285_setup_resources, - init: dc21285_init, - mem_offset: DC21285_PCI_MEM, - swizzle: ebsa285_swizzle, + swizzle: pci_std_swizzle, map_irq: ebsa285_map_irq, + nr_controllers: 1, + setup: dc21285_setup, + scan: dc21285_scan_bus, + preinit: dc21285_preinit, + postinit: dc21285_postinit, }; diff -urN linux-2.5.2-pre8/arch/arm/mach-footbridge/netwinder-pci.c linux/arch/arm/mach-footbridge/netwinder-pci.c --- linux-2.5.2-pre8/arch/arm/mach-footbridge/netwinder-pci.c Wed Jul 4 15:43:05 2001 +++ linux/arch/arm/mach-footbridge/netwinder-pci.c Sat Jan 5 14:43:15 2002 @@ -11,47 +11,42 @@ #include #include -#include -/* netwinder host-specific stuff */ +/* + * We now use the slot ID instead of the device identifiers to select + * which interrupt is routed where. + */ static int __init netwinder_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { -#define DEV(v,d) ((v)<<16|(d)) - switch (DEV(dev->vendor, dev->device)) { - case DEV(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142): - case DEV(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C885): - case DEV(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_YELLOWFIN): - return IRQ_NETWINDER_ETHER100; + switch (slot) { + case 0: /* host bridge */ + return 0; - case DEV(PCI_VENDOR_ID_WINBOND2, 0x5a5a): - return IRQ_NETWINDER_ETHER10; + case 9: /* CyberPro */ + return IRQ_NETWINDER_VGA; - case DEV(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553): - return 0; + case 10: /* DC21143 */ + return IRQ_NETWINDER_ETHER100; - case DEV(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105): + case 12: /* Winbond 553 */ return IRQ_ISA_HARDDISK1; - case DEV(PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2000): - case DEV(PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2010): - case DEV(PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_5000): - return IRQ_NETWINDER_VGA; - - case DEV(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285): - return 0; + case 13: /* Winbond 89C940F */ + return IRQ_NETWINDER_ETHER10; default: - printk(KERN_ERR "PCI: %02X:%02X [%04X:%04X] unknown device\n", - dev->bus->number, dev->devfn, - dev->vendor, dev->device); + printk(KERN_ERR "PCI: unknown device in slot %s: %s\n", + dev->slot_name, dev->name); return 0; } } struct hw_pci netwinder_pci __initdata = { - setup_resources: dc21285_setup_resources, - init: dc21285_init, - mem_offset: DC21285_PCI_MEM, - swizzle: no_swizzle, + swizzle: pci_std_swizzle, map_irq: netwinder_map_irq, + nr_controllers: 1, + setup: dc21285_setup, + scan: dc21285_scan_bus, + preinit: dc21285_preinit, + postinit: dc21285_postinit, }; diff -urN linux-2.5.2-pre8/arch/arm/mach-footbridge/personal-pci.c linux/arch/arm/mach-footbridge/personal-pci.c --- linux-2.5.2-pre8/arch/arm/mach-footbridge/personal-pci.c Wed Jul 4 15:43:05 2001 +++ linux/arch/arm/mach-footbridge/personal-pci.c Sat Jan 5 14:43:15 2002 @@ -11,7 +11,6 @@ #include #include -#include static int irqmap_personal_server[] __initdata = { IRQ_IN0, IRQ_IN1, IRQ_IN2, IRQ_IN3, 0, 0, 0, @@ -38,9 +37,10 @@ } struct hw_pci personal_server_pci __initdata = { - setup_resources: dc21285_setup_resources, - init: dc21285_init, - mem_offset: DC21285_PCI_MEM, - swizzle: no_swizzle, map_irq: personal_server_map_irq, + nr_controllers: 1, + setup: dc21285_setup, + scan: dc21285_scan_bus, + preinit: dc21285_preinit, + postinit: dc21285_postinit, }; diff -urN linux-2.5.2-pre8/arch/arm/mach-ftvpci/Makefile linux/arch/arm/mach-ftvpci/Makefile --- linux-2.5.2-pre8/arch/arm/mach-ftvpci/Makefile Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-ftvpci/Makefile Sat Jan 5 14:43:15 2002 @@ -0,0 +1,24 @@ +# +# Makefile for the linux kernel. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). + +USE_STANDARD_AS_RULE := true + +O_TARGET := ftvpci.o + +# Object file lists. + +obj-y := core.o +obj-m := +obj-n := +obj- := + +export-objs := + +obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_LEDS) += leds.o + +include $(TOPDIR)/Rules.make diff -urN linux-2.5.2-pre8/arch/arm/mach-ftvpci/core.c linux/arch/arm/mach-ftvpci/core.c --- linux-2.5.2-pre8/arch/arm/mach-ftvpci/core.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-ftvpci/core.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,98 @@ +/* + * linux/arch/arm/mach-ftvpci/core.c + * + * Architecture specific fixups. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +extern unsigned long soft_irq_mask; + +static const unsigned char irq_cmd[] = +{ + INTCONT_IRQ_DUART, + INTCONT_IRQ_PLX, + INTCONT_IRQ_D, + INTCONT_IRQ_C, + INTCONT_IRQ_B, + INTCONT_IRQ_A, + INTCONT_IRQ_SYSERR +}; + +static void ftvpci_mask_irq(unsigned int irq) +{ + __raw_writel(irq_cmd[irq], INTCONT_BASE); + soft_irq_mask &= ~(1<= FIRST_IRQ && i <= LAST_IRQ) { + irq_desc[i].valid = 1; + irq_desc[i].probe_ok = 1; + irq_desc[i].mask_ack = ftvpci_mask_irq; + irq_desc[i].mask = ftvpci_mask_irq; + irq_desc[i].unmask = ftvpci_unmask_irq; + ftvpci_mask_irq(i); + } else { + irq_desc[i].valid = 0; + irq_desc[i].probe_ok = 0; + } + } +} + +static struct map_desc ftvpci_io_desc[] __initdata = { + { INTCONT_BASE, INTCONT_START, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, + { PLX_BASE, PLX_START, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, + { PCIO_BASE, PLX_IO_START, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, + { DUART_BASE, DUART_START, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, + { STATUS_BASE, STATUS_START, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, + LAST_DESC +}; + +static void __init ftvpci_map_io(void) +{ + iotable_init(ftvpci_io_desc); +} + +MACHINE_START(NEXUSPCI, "FTV/PCI") + MAINTAINER("Philip Blundell") + BOOT_MEM(0x40000000, 0x10000000, 0xe0000000) + MAPIO(ftvpci_map_io) + INITIRQ(ftvpci_init_irq) +MACHINE_END diff -urN linux-2.5.2-pre8/arch/arm/mach-integrator/pci.c linux/arch/arm/mach-integrator/pci.c --- linux-2.5.2-pre8/arch/arm/mach-integrator/pci.c Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/mach-integrator/pci.c Sat Jan 5 14:43:15 2002 @@ -114,9 +114,11 @@ extern void pci_v3_init(void *); struct hw_pci integrator_pci __initdata = { - setup_resources: pci_v3_setup_resources, - init: pci_v3_init, mem_offset: 0x40000000, swizzle: integrator_swizzle, map_irq: integrator_map_irq, + setup: pci_v3_setup, + scan: pci_v3_scan_bus, + preinit: pci_v3_preinit, + postinit: pci_v3_postinit, }; diff -urN linux-2.5.2-pre8/arch/arm/mach-integrator/pci_v3.c linux/arch/arm/mach-integrator/pci_v3.c --- linux-2.5.2-pre8/arch/arm/mach-integrator/pci_v3.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/mach-integrator/pci_v3.c Sat Jan 5 14:43:15 2002 @@ -37,6 +37,8 @@ #include +int setup_arm_irq(int irq, struct irqaction * new); + /* * The V3 PCI interface chip in Integrator provides several windows from * local bus memory into the PCI memory areas. Unfortunately, there @@ -411,7 +413,7 @@ flags: IORESOURCE_MEM | IORESOURCE_PREFETCH, }; -void __init pci_v3_setup_resources(struct resource **resource) +static void __init pci_v3_setup_resources(struct resource **resource) { if (request_resource(&iomem_resource, &non_mem)) printk("PCI: unable to allocate non-prefetchable memory region\n"); @@ -433,18 +435,21 @@ * means I can't get additional information on the reason for the pm2fb * problems. I suppose I'll just have to mind-meld with the machine. ;) */ -#define SC_PCI (IO_ADDRESS(INTEGRATOR_SC_PCIENABLE)) -#define SC_LBFADDR (IO_ADDRESS(INTEGRATOR_SC_BASE+0x20)) -#define SC_LBFCODE (IO_ADDRESS(INTEGRATOR_SC_BASE+0x24)) +#define SC_PCI (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_PCIENABLE_OFFSET) +#define SC_LBFADDR (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x20) +#define SC_LBFCODE (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x24) static int v3_fault(unsigned long addr, struct pt_regs *regs) { unsigned long pc = instruction_pointer(regs); unsigned long instr = *(unsigned long *)pc; +// char buf[128]; - printk("V3 fault: address=0x%08lx, pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n", - addr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255, - v3_readb(V3_LB_ISTAT)); +// sprintf(buf, "V3 fault: address=0x%08lx, pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n", +// addr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255, +// v3_readb(V3_LB_ISTAT)); +// printk("%s", buf); +// printascii(buf); v3_writeb(V3_LB_ISTAT, 0); __raw_writel(3, SC_PCI); @@ -467,11 +472,20 @@ return 0; } + if ((instr & 0x0e100090) == 0x00100090) { + int reg = (instr >> 12) & 15; + + regs->uregs[reg] = -1; + regs->ARM_pc += 4; + return 0; + } + return 1; } static void v3_irq(int irq, void *devid, struct pt_regs *regs) { +#ifdef CONFIG_DEBUG_LL unsigned long pc = instruction_pointer(regs); unsigned long instr = *(unsigned long *)pc; char buf[128]; @@ -480,10 +494,13 @@ pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255, v3_readb(V3_LB_ISTAT)); printascii(buf); +#endif + v3_writew(V3_PCI_STAT, 0xf000); v3_writeb(V3_LB_ISTAT, 0); __raw_writel(3, SC_PCI); +#ifdef CONFIG_DEBUG_LL /* * If the instruction being executed was a read, * make it look like it read all-ones. @@ -493,12 +510,14 @@ sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]); printascii(buf); } +#endif } static struct irqaction v3_int = { name: "V3", handler: v3_irq, }; + static struct irqaction v3_int2 = { name: "V3TM", handler: v3_irq, @@ -506,14 +525,26 @@ extern int (*external_fault)(unsigned long addr, struct pt_regs *regs); +int pci_v3_setup(int nr, struct pci_sys_data *sys) +{ + if (nr) + pci_v3_setup_resources(sys->resource); + return nr ? 0 : 1; +} + +struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *sys) +{ + return pci_scan_bus(sys->busnr, &pci_v3_ops, sys); +} + /* * V3_LB_BASE? - local bus address * V3_LB_MAP? - pci bus address */ -void __init pci_v3_init(void *sysdata) +void __init pci_v3_preinit(void) { - unsigned int pci_cmd; unsigned long flags; + unsigned int temp; /* * Hook in our fault handler for PCI errors @@ -523,6 +554,12 @@ spin_lock_irqsave(&v3_lock, flags); /* + * Unlock V3 registers, but only if they were previously locked. + */ + if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK) + v3_writew(V3_SYSTEM, 0xa05f); + + /* * Setup window 0 - PCI non-prefetchable memory * Local: 0x40000000 Bus: 0x00000000 Size: 256MB */ @@ -548,27 +585,56 @@ V3_LB_BASE_ENABLE); v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0)); + /* + * Disable PCI to host IO cycles + */ + temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN; + temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS; + v3_writew(V3_PCI_CFG, temp); + + printk("FIFO_CFG: %04x FIFO_PRIO: %04x\n", + v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY)); + + /* + * Set the V3 FIFO such that writes have higher priority than + * reads, and local bus write causes local bus read fifo flush. + * Same for PCI. + */ + v3_writew(V3_FIFO_PRIORITY, 0x0a0a); + + /* + * Re-lock the system register. + */ + temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK; + v3_writew(V3_SYSTEM, temp); + + /* + * Clear any error conditions, and enable write errors. + */ + v3_writeb(V3_LB_ISTAT, 0); + v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10)); + v3_writeb(V3_LB_IMASK, 0x28); + __raw_writel(3, SC_PCI); + + /* + * Grab the PCI error interrupt. + */ + setup_arm_irq(IRQ_V3INT, &v3_int); + spin_unlock_irqrestore(&v3_lock, flags); +} - pci_scan_bus(0, &pci_v3_ops, sysdata); +void __init pci_v3_postinit(void) +{ + unsigned int pci_cmd; pci_cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; v3_writew(V3_PCI_CMD, pci_cmd); - /* - * Clear any error conditions. - */ - __raw_writel(3, SC_PCI); - v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10)); - v3_writeb(V3_LB_ISTAT, 0); + v3_writeb(V3_LB_ISTAT, ~0x40); v3_writeb(V3_LB_IMASK, 0x68); - printk("LB_CFG: %04x LB_ISTAT: %02x LB_IMASK: %02x\n", - v3_readw(V3_LB_CFG), - v3_readb(V3_LB_ISTAT), - v3_readb(V3_LB_IMASK)); - setup_arm_irq(IRQ_V3INT, &v3_int); // setup_arm_irq(IRQ_LBUSTIMEOUT, &v3_int2); } diff -urN linux-2.5.2-pre8/arch/arm/mach-iop310/Makefile linux/arch/arm/mach-iop310/Makefile --- linux-2.5.2-pre8/arch/arm/mach-iop310/Makefile Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-iop310/Makefile Sat Jan 5 14:43:15 2002 @@ -0,0 +1,33 @@ +# +# Makefile for the linux kernel. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). + +USE_STANDARD_AS_RULE := true + +O_TARGET := iop310.o + +# Object file lists. + +obj-y := arch.o mm.o xs80200-irq.o iop310-irq.o \ + iop310-pci.o +obj-m := +obj-n := +obj- := + +export-objs := + +obj-$(CONFIG_ARCH_IQ80310) += iq80310-pci.o iq80310-irq.o + +ifneq ($(CONFIG_XSCALE_PMU_TIMER),y) +obj-y += iq80310-time.o +endif + +obj-$(CONFIG_IOP310_AAU) += aau.o +obj-$(CONFIG_IOP310_DMA) += dma.o +obj-$(CONFIG_IOP310_MU) += message.o +obj-$(CONFIG_IOP310_PMON) += pmon.o + +include $(TOPDIR)/Rules.make diff -urN linux-2.5.2-pre8/arch/arm/mach-iop310/arch.c linux/arch/arm/mach-iop310/arch.c --- linux-2.5.2-pre8/arch/arm/mach-iop310/arch.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-iop310/arch.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,61 @@ +/* + * linux/arch/arm/mach-iop310/arch.c + * + * Author: Nicolas Pitre + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_ARCH_IQ80310 +extern void iq80310_map_io(void); +extern void iq80310_init_irq(void); + +static void __init +fixup_iq80310(struct machine_desc *desc, struct param_struct *params, + char **cmdline, struct meminfo *mi) +{ + system_rev = (*(volatile unsigned int*)0xfe830000) & 0x0f; + + if(system_rev) + system_rev = 0xF; + + mi->bank[0].start = PHYS_OFFSET; + mi->bank[0].size = (32*1024*1024); + mi->bank[0].node = 0; + mi->nr_banks = 1; + +#ifdef CONFIG_ROOT_NFS + ROOT_DEV = to_kdev_t(0x00FF); /* /dev/nfs pseudo device */ +#elif defined(CONFIG_BLK_DEV_INITRD) + setup_ramdisk( 1, 0, 0, CONFIG_BLK_DEV_RAM_SIZE ); + setup_initrd( 0xc0800000, 4*1024*1024 ); + ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); /* /dev/ram */ +#endif +} + +MACHINE_START(IQ80310, "Cyclone IQ80310") + MAINTAINER("MontaVista Software Inc.") + BOOT_MEM(0xa0000000, 0xfe000000, 0xfe000000) + FIXUP(fixup_iq80310) + MAPIO(iq80310_map_io) + INITIRQ(iq80310_init_irq) +MACHINE_END + +#else +#error No machine descriptor defined for this IOP310 implementation +#endif diff -urN linux-2.5.2-pre8/arch/arm/mach-iop310/iop310-irq.c linux/arch/arm/mach-iop310/iop310-irq.c --- linux-2.5.2-pre8/arch/arm/mach-iop310/iop310-irq.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-iop310/iop310-irq.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,109 @@ +/* + * linux/arch/arm/mach-iop310/iop310-irq.c + * + * Generic IOP310 IRQ handling functionality + * + * Author: Nicolas Pitre + * Copyright: (C) 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Added IOP310 chipset and IQ80310 board demuxing, masking code. - DS + * + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +extern void xs80200_irq_mask(unsigned int); +extern void xs80200_irq_unmask(unsigned int); +extern void xs80200_init_irq(void); + +extern void do_IRQ(int, struct pt_regs *); + +u32 iop310_mask = 0; + +static void +iop310_irq_mask (unsigned int irq) +{ + iop310_mask |= (1 << (irq - IOP310_IRQ_OFS)); + + /* + * No mask bits on the 80312, so we have to + * mask everything from the outside! + */ + xs80200_irq_mask(IRQ_XS80200_EXTIRQ); +} + +static void +iop310_irq_unmask (unsigned int irq) +{ + iop310_mask &= ~(1 << (irq - IOP310_IRQ_OFS)); + + /* + * Check if all 80312 sources are unmasked now + */ + if(!iop310_mask) + { + xs80200_irq_unmask(IRQ_XS80200_EXTIRQ); + + } +} + +void iop310_irq_demux(int irq, void *dev_id, + struct pt_regs *regs) +{ + u32 fiq1isr = *((volatile u32*)IOP310_FIQ1ISR); + u32 fiq2isr = *((volatile u32*)IOP310_FIQ2ISR); + unsigned int irqno = 0; + + if(fiq1isr) + { + if(fiq1isr & 0x1) + irqno = IRQ_IOP310_DMA0; + if(fiq1isr & 0x2) + irqno = IRQ_IOP310_DMA1; + if(fiq1isr & 0x4) + irqno = IRQ_IOP310_DMA2; + if(fiq1isr & 0x10) + irqno = IRQ_IOP310_PMON; + if(fiq1isr & 0x20) + irqno = IRQ_IOP310_AAU; + } + else + { + if(fiq2isr & 0x2) + irqno = IRQ_IOP310_I2C; + if(fiq2isr & 0x4) + irqno = IRQ_IOP310_MU; + } + + do_IRQ(irqno, regs); +} + +void __init iop310_init_irq(void) +{ + int i; + + for(i = IOP310_IRQ_OFS; i < NR_IOP310_IRQS; i++) + { + irq_desc[i].valid = 1; + irq_desc[i].probe_ok = 1; + irq_desc[i].mask_ack = iop310_irq_mask; + irq_desc[i].mask = iop310_irq_mask; + irq_desc[i].unmask = iop310_irq_unmask; + } + + xs80200_init_irq(); +} + diff -urN linux-2.5.2-pre8/arch/arm/mach-iop310/iop310-pci.c linux/arch/arm/mach-iop310/iop310-pci.c --- linux-2.5.2-pre8/arch/arm/mach-iop310/iop310-pci.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-iop310/iop310-pci.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,500 @@ +/* + * arch/arm/mach-iop310/iop310-pci.c + * + * PCI support for the Intel IOP310 chipset + * + * Matt Porter + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +/* + * *** Special note - why the IOP310 should NOT be used *** + * + * The PCI ATU is a brain dead implementation, only allowing 32-bit + * accesses to PCI configuration space. This is especially brain + * dead for writes to this space. A simple for-instance: + * + * You want to modify the command register *without* corrupting the + * status register. + * + * To perform this, you need to read *32* bits of data from offset 4, + * mask off the low 16, replace them with the new data, and write *32* + * bits back. + * + * Writing the status register at offset 6 with status bits set *clears* + * the status. + * + * Hello? Could we have a *SANE* implementation of a PCI ATU some day + * *PLEASE*? + */ +#undef DEBUG +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +extern int (*external_fault)(unsigned long, struct pt_regs *); + +static u32 iop310_cfg_address(struct pci_dev *dev, int where) +{ + struct pci_sys_data *sys = dev->sysdata; + u32 addr; + + where &= ~3; + + if (sys->busnr == dev->bus->number) + addr = 1 << (PCI_SLOT(dev->devfn) + 16); + else + addr = dev->bus->number << 16 | + PCI_SLOT(dev->devfn) << 11 | 1; + + addr |= PCI_FUNC(dev->devfn) << 8 | where; + + return addr; +} + +/* + * Primary PCI interface support. + */ +static int iop310_pri_pci_status(void) +{ + unsigned int status; + int ret = 0; + + status = *IOP310_PATUSR; + if (status & 0xf900) { + *IOP310_PATUSR = status & 0xf900; + ret = 1; + } + status = *IOP310_PATUISR; + if (status & 0x0000018f) { + *IOP310_PATUISR = status & 0x0000018f; + ret = 1; + } + status = *IOP310_PSR; + if (status & 0xf900) { + *IOP310_PSR = status & 0xf900; + ret = 1; + } + status = *IOP310_PBISR; + if (status & 0x003f) { + *IOP310_PBISR = status & 0x003f; + ret = 1; + } + return ret; +} + +static int +iop310_pri_rd_cfg_byte(struct pci_dev *dev, int where, u8 *p) +{ + int ret; + u8 val; + + *IOP310_POCCAR = iop310_cfg_address(dev, where); + + val = (*IOP310_POCCDR) >> ((where & 3) * 8); + __asm__ __volatile__("nop; nop; nop; nop"); + + ret = iop310_pri_pci_status(); + if (ret) + val = 0xff; + + *p = val; + + return PCIBIOS_SUCCESSFUL; +} + +static int +iop310_pri_rd_cfg_word(struct pci_dev *dev, int where, u16 *p) +{ + int ret; + u16 val; + + *IOP310_POCCAR = iop310_cfg_address(dev, where); + + val = (*IOP310_POCCDR) >> ((where & 2) * 8); + __asm__ __volatile__("nop; nop; nop; nop"); + + ret = iop310_pri_pci_status(); + if (ret) + val = 0xffff; + + *p = val; + + return PCIBIOS_SUCCESSFUL; +} + +static int +iop310_pri_rd_cfg_dword(struct pci_dev *dev, int where, u32 *p) +{ + int ret; + u32 val; + + *IOP310_POCCAR = iop310_cfg_address(dev, where); + + val = *IOP310_POCCDR; + __asm__ __volatile__("nop; nop; nop; nop"); + + ret = iop310_pri_pci_status(); + if (ret) + val = 0xffffffff; + + *p = val; + + return PCIBIOS_SUCCESSFUL; +} + +static int +iop310_pri_wr_cfg_byte(struct pci_dev *dev, int where, u8 v) +{ + int ret; + u32 val; + + *IOP310_POCCAR = iop310_cfg_address(dev, where); + + val = *IOP310_POCCDR; + __asm__ __volatile__("nop; nop; nop; nop"); + + ret = iop310_pri_pci_status(); + if (ret == 0) { + where = (where & 3) * 8; + val &= ~(0xff << where); + val |= v << where; + *IOP310_POCCDR = val; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int +iop310_pri_wr_cfg_word(struct pci_dev *dev, int where, u16 v) +{ + int ret; + u32 val; + + *IOP310_POCCAR = iop310_cfg_address(dev, where); + + val = *IOP310_POCCDR; + __asm__ __volatile__("nop; nop; nop; nop"); + + ret = iop310_pri_pci_status(); + if (ret == 0) { + where = (where & 2) * 8; + val &= ~(0xffff << where); + val |= v << where; + *IOP310_POCCDR = val; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int +iop310_pri_wr_cfg_dword(struct pci_dev *dev, int where, u32 v) +{ + *IOP310_POCCAR = iop310_cfg_address(dev, where); + *IOP310_POCCDR = v; + __asm__ __volatile__("nop; nop; nop; nop"); + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops iop310_primary_ops = { + iop310_pri_rd_cfg_byte, + iop310_pri_rd_cfg_word, + iop310_pri_rd_cfg_dword, + iop310_pri_wr_cfg_byte, + iop310_pri_wr_cfg_word, + iop310_pri_wr_cfg_dword, +}; + +/* + * Secondary PCI interface support. + */ +static int iop310_sec_pci_status(void) +{ + unsigned int usr, uisr; + int ret = 0; + + usr = *IOP310_SATUSR; + uisr = *IOP310_SATUISR; + if (usr & 0xf900) { + *IOP310_SATUSR = usr & 0xf900; + ret = 1; + } + if (uisr & 0x0000069f) { + *IOP310_SATUISR = uisr & 0x0000069f; + ret = 1; + } +//if (ret) printk("ERROR (%08lx %08lx)", usr, uisr); + return ret; +} + +static int +iop310_sec_rd_cfg_byte(struct pci_dev *dev, int where, u8 *p) +{ + int ret; + u8 val; +//printk("rdb: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where); + *IOP310_SOCCAR = iop310_cfg_address(dev, where); + + val = (*IOP310_SOCCDR) >> ((where & 3) * 8); + __asm__ __volatile__("nop; nop; nop; nop"); +//printk(">= %08lx ", val); + ret = iop310_sec_pci_status(); + if (ret) + val = 0xff; +//printk("\n"); + *p = val; + + return PCIBIOS_SUCCESSFUL; +} + +static int +iop310_sec_rd_cfg_word(struct pci_dev *dev, int where, u16 *p) +{ + int ret; + u16 val; +//printk("rdw: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where); + *IOP310_SOCCAR = iop310_cfg_address(dev, where); + + val = (*IOP310_SOCCDR) >> ((where & 3) * 8); + __asm__ __volatile__("nop; nop; nop; nop"); +//printk(">= %08lx ", val); + ret = iop310_sec_pci_status(); + if (ret) + val = 0xffff; +//printk("\n"); + *p = val; + + return PCIBIOS_SUCCESSFUL; +} + +static int +iop310_sec_rd_cfg_dword(struct pci_dev *dev, int where, u32 *p) +{ + int ret; + u32 val; +//printk("rdl: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where); + *IOP310_SOCCAR = iop310_cfg_address(dev, where); + + val = *IOP310_SOCCDR; + __asm__ __volatile__("nop; nop; nop; nop"); +//printk(">= %08lx ", val); + ret = iop310_sec_pci_status(); + if (ret) + val = 0xffffffff; +//printk("\n"); + *p = val; + + return PCIBIOS_SUCCESSFUL; +} + +static int +iop310_sec_wr_cfg_byte(struct pci_dev *dev, int where, u8 v) +{ + int ret; + u32 val; +//printk("wrb: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where); + *IOP310_SOCCAR = iop310_cfg_address(dev, where); + + val = *IOP310_SOCCDR; + __asm__ __volatile__("nop; nop; nop; nop"); +//printk("<= %08lx", v); + ret = iop310_sec_pci_status(); + if (ret == 0) { + where = (where & 3) * 8; + val &= ~(0xff << where); + val |= v << where; + *IOP310_SOCCDR = val; + } +//printk("\n"); + return PCIBIOS_SUCCESSFUL; +} + +static int +iop310_sec_wr_cfg_word(struct pci_dev *dev, int where, u16 v) +{ + int ret; + u32 val; +//printk("wrw: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where); + *IOP310_SOCCAR = iop310_cfg_address(dev, where); + + val = *IOP310_SOCCDR; + __asm__ __volatile__("nop; nop; nop; nop"); +//printk("<= %08lx", v); + ret = iop310_sec_pci_status(); + if (ret == 0) { + where = (where & 2) * 8; + val &= ~(0xffff << where); + val |= v << where; + *IOP310_SOCCDR = val; + } +//printk("\n"); + return PCIBIOS_SUCCESSFUL; +} + +static int +iop310_sec_wr_cfg_dword(struct pci_dev *dev, int where, u32 v) +{ +//printk("wrl: %d:%02x.%x %02x ", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where); + *IOP310_SOCCAR = iop310_cfg_address(dev, where); + *IOP310_SOCCDR = v; + __asm__ __volatile__("nop; nop; nop; nop"); +//printk("<= %08lx\n", v); + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops iop310_secondary_ops = { + iop310_sec_rd_cfg_byte, + iop310_sec_rd_cfg_word, + iop310_sec_rd_cfg_dword, + iop310_sec_wr_cfg_byte, + iop310_sec_wr_cfg_word, + iop310_sec_wr_cfg_dword, +}; + +/* + * When a PCI device does not exist during config cycles, the 80200 gets a + * bus error instead of returning 0xffffffff. This handler simply returns. + */ +int iop310_pci_abort_handler(unsigned long addr, struct pt_regs *regs) +{ +// printk("PCI abort: address = %08x PC = %08x LR = %08lx\n", +// addr, regs->ARM_pc, regs->ARM_lr); + return 0; +} + +/* + * Scan an IOP310 PCI bus. sys->bus defines which bus we scan. + */ +struct pci_bus *iop310_scan_bus(int nr, struct pci_sys_data *sys) +{ + struct pci_ops *ops; + + if (nr) + ops = &iop310_secondary_ops; + else + ops = &iop310_primary_ops; + + return pci_scan_bus(sys->busnr, ops, sys); +} + +/* + * Setup the system data for controller 'nr'. Return 0 if none found, + * 1 if found, or negative error. + * + * We can alter: + * io_offset - offset between IO resources and PCI bus BARs + * mem_offset - offset between mem resources and PCI bus BARs + * resource[0] - parent IO resource + * resource[1] - parent non-prefetchable memory resource + * resource[2] - parent prefetchable memory resource + * swizzle - bridge swizzling function + * map_irq - irq mapping function + * + * Note that 'io_offset' and 'mem_offset' are left as zero since + * the IOP310 doesn't attempt to perform any address translation + * on accesses from the host to the bus. + */ +int iop310_setup(int nr, struct pci_sys_data *sys) +{ + struct resource *res; + + if (nr >= 2) + return 0; + + res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("PCI: unable to alloc resources"); + + switch (nr) { + case 0: + res[0].start = IOP310_PCIPRI_LOWER_IO + 0x6e000000; + res[0].end = IOP310_PCIPRI_LOWER_IO + 0x6e00ffff; + res[0].name = "PCI IO Primary"; + + res[1].start = IOP310_PCIPRI_LOWER_MEM; + res[1].end = IOP310_PCIPRI_LOWER_MEM + IOP310_PCI_WINDOW_SIZE; + res[1].name = "PCI Memory Primary"; + break; + + case 1: + res[0].start = IOP310_PCISEC_LOWER_IO + 0x6e000000; + res[0].end = IOP310_PCISEC_LOWER_IO + 0x6e00ffff; + res[0].name = "PCI IO Primary"; + + res[1].start = IOP310_PCISEC_LOWER_MEM; + res[1].end = IOP310_PCISEC_LOWER_MEM + IOP310_PCI_WINDOW_SIZE; + res[1].name = "PCI Memory Primary"; + break; + } + + request_resource(&ioport_resource, &res[0]); + request_resource(&iomem_resource, &res[1]); + + sys->resource[0] = &res[0]; + sys->resource[1] = &res[1]; + sys->resource[2] = NULL; + sys->io_offset = 0x6e000000; + + return 1; +} + +void iop310_init(void) +{ + DBG("PCI: Intel 80312 PCI-to-PCI init code.\n"); + DBG(" ATU secondary: IOP310_SOMWVR=0x%04x, IOP310_SOIOWVR=0x%04x\n", + *IOP310_SOMWVR, + *IOP310_SOIOWVR); + DBG(" ATU secondary: IOP310_ATUCR=0x%08x\n", *IOP310_ATUCR); + DBG(" ATU secondary: IOP310_SIABAR=0x%08x IOP310_SIALR=0x%08x IOP310_SIATVR=%08x\n", *IOP310_SIABAR, *IOP310_SIALR, *IOP310_SIATVR); + + DBG(" ATU primary: IOP310_POMWVR=0x%04x, IOP310_POIOWVR=0x%04x\n", + *IOP310_POMWVR, + *IOP310_POIOWVR); + DBG(" ATU secondary: IOP310_PIABAR=0x%08x IOP310_PIALR=0x%08x IOP310_PIATVR=%08x\n", *IOP310_PIABAR, *IOP310_PIALR, *IOP310_PIATVR); + + DBG(" P2P: IOP310_PCR=0x%04x IOP310_BCR=0x%04x IOP310_EBCR=0x%04x\n", *IOP310_PCR, *IOP310_BCR, *IOP310_EBCR); + + /* + * Windows have to be carefully opened via a nice set of calls + * here or just some direct register fiddling in the board + * specific init when we want transactions to occur between the + * two PCI hoses. + * + * To do this, we will have manage RETRY assertion between the + * firmware and the kernel. This will ensure that the host + * system's enumeration code is held off until we have tweaked + * the interrupt routing and public/private IDSELs. + * + * For now we will simply default to disabling the integrated type + * 81 P2P bridge. + */ + *IOP310_PCR &= 0xfff8; + + external_fault = iop310_pci_abort_handler; + +} + diff -urN linux-2.5.2-pre8/arch/arm/mach-iop310/iq80310-irq.c linux/arch/arm/mach-iop310/iq80310-irq.c --- linux-2.5.2-pre8/arch/arm/mach-iop310/iq80310-irq.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-iop310/iq80310-irq.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,172 @@ +/* + * linux/arch/arm/mach-iop310/iq80310-irq.c + * + * IRQ hadling/demuxing for IQ80310 board + * + * Author: Nicolas Pitre + * Copyright: (C) 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * 2.4.7-rmk1-iop310.1 + * Moved demux from asm to C - DS + * Fixes for various revision boards - DS + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +extern void xs80200_irq_mask(unsigned int); +extern void xs80200_irq_unmask(unsigned int); +extern void xs80200_init_irq(void); + +extern void do_IRQ(int, struct pt_regs *); + +extern u32 iop310_mask; + +extern void iop310_irq_demux(int, void *, struct pt_regs *); + +extern int iop310_init_irq(void); + +static void +iq80310_irq_mask (unsigned int irq) +{ + volatile char *mask = (volatile char *)IQ80310_INT_MASK; + *mask |= (1 << (irq - IQ80310_IRQ_OFS)); + + /* + * There's no mask for PCI INT A-C, so we just mask out all + * external interrupts on the CPU. + * + * We set a bit of the iop310 mask so that the iop310_irq_mask + * function does not unmask EXTINT + */ + if (irq > IRQ_IQ80310_INTD) + { + xs80200_irq_mask(IRQ_XS80200_EXTIRQ); + iop310_mask |= (0x80000000 >> (irq - IRQ_IQ80310_INTD)); + } +} + +static void +iq80310_irq_unmask (unsigned int irq) +{ + volatile char *mask = (volatile char *)IQ80310_INT_MASK; + *mask &= ~(1 << (irq - IQ80310_IRQ_OFS)); + + /* + * See comment above + */ + if (irq > IRQ_IQ80310_INTD) + { + xs80200_irq_unmask(IRQ_XS80200_EXTIRQ); + iop310_mask &= ~((0x80000000 >> (irq - IRQ_IQ80310_INTD))); + } +} + +static void iq80310_cpld_irq_demux(int irq, void *dev_id, + struct pt_regs *regs) +{ + u8 irq_stat = *((volatile u8*)IQ80310_INT_STAT); + u8 irq_mask = *((volatile u8*)IQ80310_INT_MASK); + unsigned int irqno = 0xffffffff; + + // Needed? If IRQ is masked, it shouldn't get through... + irq_stat &= ~irq_mask; + + + if(irq_stat & 0x01) + irqno = IRQ_IQ80310_TIMER; + else if(irq_stat & 0x02) + irqno = IRQ_IQ80310_I82559; + else if(irq_stat & 0x04) + irqno = IRQ_IQ80310_UART1; + else if(irq_stat & 0x08) + irqno = IRQ_IQ80310_UART2; + else if(irq_stat & 0x10) + irqno = IRQ_IQ80310_INTD; + else if(system_rev) + { + irq_stat = *((volatile u8*)IQ80310_PCI_INT_STAT) & 0xf; + + if(irq_stat & 0x1) + irqno = IRQ_IQ80310_INTA; + else if(irq_stat & 0x2) + irqno = IRQ_IQ80310_INTB; + else if(irq_stat & 0x4) + irqno = IRQ_IQ80310_INTC; + } + else /* Running on a REV D.1 or older, assume PCI INTA */ + irqno = IRQ_IQ80310_INTA; + + /* + * If we didn't read a CPLD interrupt, we assume it's from + * a device on the chipset itself. + */ + if(irqno == 0xffffffff) + { + iop310_irq_demux(irq, dev_id, regs); + return; + } + + /* + * If on a REV D.1 or lower board, we just assumed INTA since + * PCI is not routed, and it may actually be an on-chip interrupt. + * + * Note that we're giving on-chip interrupts slightly higher + * priority than PCI by handling them first. + */ + if(irqno == IRQ_IQ80310_INTA && !system_rev) + iop310_irq_demux(irq, dev_id, regs); + + do_IRQ(irqno, regs); +} + + +static struct irqaction iq80310_cpld_irq = { + name: "CPLD_IRQ", + handler: iq80310_cpld_irq_demux, + flags: SA_INTERRUPT +}; + +extern int setup_arm_irq(int, struct irqaction *); + +void __init iq80310_init_irq(void) +{ + volatile char *mask = (volatile char *)IQ80310_INT_MASK; + unsigned int i; + + iop310_init_irq(); + + /* + * Setup PIRSR to route PCI interrupts into xs80200 + */ + *IOP310_PIRSR = 0xff; + + for (i = IQ80310_IRQ_OFS; i < NR_IRQS; i++) { + irq_desc[i].valid = 1; + irq_desc[i].probe_ok = 1; + irq_desc[i].mask_ack = iq80310_irq_mask; + irq_desc[i].mask = iq80310_irq_mask; + irq_desc[i].unmask = iq80310_irq_unmask; + } + + *mask = 0xff; /* mask all sources */ + setup_arm_irq(IRQ_XS80200_EXTIRQ, &iq80310_cpld_irq); + + /* enable only external IRQ in the INTCTL for now */ + asm ("mcr p13, 0, %0, c0, c0, 0" : : "r" (1<<1)); +} diff -urN linux-2.5.2-pre8/arch/arm/mach-iop310/iq80310-pci.c linux/arch/arm/mach-iop310/iq80310-pci.c --- linux-2.5.2-pre8/arch/arm/mach-iop310/iq80310-pci.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-iop310/iq80310-pci.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,149 @@ +/* + * arch/arm/mach-iop310/iq80310-pci.c + * + * PCI support for the Intel IQ80310 reference board + * + * Matt Porter + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include + +#include +#include +#include + +/* + * The following macro is used to lookup irqs in a standard table + * format for those systems that do not already have PCI + * interrupts properly routed. We assume 1 <= pin <= 4 + */ +#define PCI_IRQ_TABLE_LOOKUP(minid,maxid) \ +({ int _ctl_ = -1; \ + if (idsel >= minid && idsel <= maxid && pin >= 1 && pin <= 4) \ + _ctl_ = pci_irq_table[idsel - minid][pin-1]; \ + _ctl_; }) + +#define INTA IRQ_IQ80310_INTA +#define INTB IRQ_IQ80310_INTB +#define INTC IRQ_IQ80310_INTC +#define INTD IRQ_IQ80310_INTD + +#define INTE IRQ_IQ80310_I82559 + +typedef u8 irq_table[4]; + +/* + * IRQ tables for primary bus. + * + * On a Rev D.1 and older board, INT A-C are not routed, so we + * just fake it as INTA and than we take care of handling it + * correctly in the IRQ demux routine. + */ +static irq_table pci_pri_d_irq_table[] = { +/* Pin: A B C D */ + { INTA, INTD, INTA, INTA }, /* PCI Slot J3 */ + { INTD, INTA, INTA, INTA }, /* PCI Slot J4 */ +}; + +static irq_table pci_pri_f_irq_table[] = { +/* Pin: A B C D */ + { INTC, INTD, INTA, INTB }, /* PCI Slot J3 */ + { INTD, INTA, INTB, INTC }, /* PCI Slot J4 */ +}; + +static int __init +iq80310_pri_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) +{ + irq_table *pci_irq_table; + + if (!system_rev) { + pci_irq_table = pci_pri_d_irq_table; + } else { + pci_irq_table = pci_pri_f_irq_table; + } + + return PCI_IRQ_TABLE_LOOKUP(2, 3); +} + +/* + * IRQ tables for secondary bus. + * + * On a Rev D.1 and older board, INT A-C are not routed, so we + * just fake it as INTA and than we take care of handling it + * correctly in the IRQ demux routine. + */ +static irq_table pci_sec_d_irq_table[] = { +/* Pin: A B C D */ + { INTA, INTA, INTA, INTD }, /* PCI Slot J1 */ + { INTA, INTA, INTD, INTA }, /* PCI Slot J5 */ + { INTE, INTE, INTE, INTE }, /* P2P Bridge */ +}; + +static irq_table pci_sec_f_irq_table[] = { +/* Pin: A B C D */ + { INTA, INTB, INTC, INTD }, /* PCI Slot J1 */ + { INTB, INTC, INTD, INTA }, /* PCI Slot J5 */ + { INTE, INTE, INTE, INTE }, /* P2P Bridge */ +}; + +static int __init +iq80310_sec_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) +{ + irq_table *pci_irq_table; + + if (!system_rev) { + pci_irq_table = pci_sec_d_irq_table; + } else { + pci_irq_table = pci_sec_f_irq_table; + } + + return PCI_IRQ_TABLE_LOOKUP(0, 2); +} + +static int iq80310_pri_host; + +static int iq80310_setup(int nr, struct pci_sys_data *sys) +{ + switch (nr) { + case 0: + if (!iq80310_pri_host) + return 0; + + sys->map_irq = iq80310_pri_map_irq; + break; + + case 1: + sys->map_irq = iq80310_sec_map_irq; + break; + + default: + return 0; + } + + return iop310_setup(nr, sys); +} + +static void iq80310_preinit(void) +{ + iq80310_pri_host = *(volatile u32 *)IQ80310_BACKPLANE & 1; + + printk(KERN_INFO "PCI: IQ80310 is a%s\n", + iq80310_pri_host ? " system controller" : "n agent"); + + iop310_init(); +} + +struct hw_pci iq80310_pci __initdata = { + swizzle: pci_std_swizzle, + nr_controllers: 2, + setup: iq80310_setup, + scan: iop310_scan_bus, + preinit: iq80310_preinit, +}; diff -urN linux-2.5.2-pre8/arch/arm/mach-iop310/iq80310-time.c linux/arch/arm/mach-iop310/iq80310-time.c --- linux-2.5.2-pre8/arch/arm/mach-iop310/iq80310-time.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-iop310/iq80310-time.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,125 @@ +/* + * linux/arch/arm/mach-iop310/time-iq80310.c + * + * Timer functions for IQ80310 onboard timer + * + * Author: Nicolas Pitre + * Copyright: (C) 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include + +static void iq80310_write_timer (u_long val) +{ + volatile u_char *la0 = (volatile u_char *)IQ80310_TIMER_LA0; + volatile u_char *la1 = (volatile u_char *)IQ80310_TIMER_LA1; + volatile u_char *la2 = (volatile u_char *)IQ80310_TIMER_LA2; + + *la0 = val; + *la1 = val >> 8; + *la2 = (val >> 16) & 0x3f; +} + +static u_long iq80310_read_timer (void) +{ + volatile u_char *la0 = (volatile u_char *)IQ80310_TIMER_LA0; + volatile u_char *la1 = (volatile u_char *)IQ80310_TIMER_LA1; + volatile u_char *la2 = (volatile u_char *)IQ80310_TIMER_LA2; + volatile u_char *la3 = (volatile u_char *)IQ80310_TIMER_LA3; + u_long b0, b1, b2, b3, val; + + b0 = *la0; b1 = *la1; b2 = *la2; b3 = *la3; + b0 = (((b0 & 0x20) >> 1) | (b0 & 0x1f)); + b1 = (((b1 & 0x20) >> 1) | (b1 & 0x1f)); + b2 = (((b2 & 0x20) >> 1) | (b2 & 0x1f)); + b3 = (b3 & 0x0f); + val = ((b0 << 0) | (b1 << 6) | (b2 << 12) | (b3 << 18)); + return val; +} + +/* IRQs are disabled before entering here from do_gettimeofday() */ +static unsigned long iq80310_gettimeoffset (void) +{ + unsigned long elapsed, usec; + + /* We need elapsed timer ticks since last interrupt */ + elapsed = iq80310_read_timer(); + + /* Now convert them to usec */ + usec = (unsigned long)(elapsed*tick)/LATCH; + + return usec; +} + + +static void iq80310_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + volatile u_char *timer_en = (volatile u_char *)IQ80310_TIMER_EN; + + /* clear timer interrupt */ + *timer_en &= ~2; + *timer_en |= 2; + + /* + * AHEM..HACK + * + * Since the timer interrupt is cascaded through the CPLD and + * the 80312 and the demux code calls do_IRQ, the irq count is + * going to be atleast 2 when we get here and this will cause the + * kernel to increment the system tick counter even if we're + * idle. This causes it to look like there's always 100% system + * time, which is not the case. To get around it, we just decrement + * the IRQ count before calling do_timer. We increment it again + * b/c otherwise it will go negative and than bad things happen. + * + * -DS + */ + irq_exit(smp_processor_id(), irq); + do_timer(regs); + irq_enter(smp_processor_id(), irq); +} + +extern unsigned long (*gettimeoffset)(void); + +static struct irqaction timer_irq = { + name: "timer", + handler: iq80310_timer_interrupt, +}; + + +extern int setup_arm_irq(int, struct irqaction*); + +void __init time_init(void) +{ + volatile u_char *timer_en = (volatile u_char *)IQ80310_TIMER_EN; + + gettimeoffset = iq80310_gettimeoffset; + setup_arm_irq(IRQ_IQ80310_TIMER, &timer_irq); + *timer_en = 0; + iq80310_write_timer(LATCH); + *timer_en |= 2; + *timer_en |= 1; +} + diff -urN linux-2.5.2-pre8/arch/arm/mach-iop310/mm.c linux/arch/arm/mach-iop310/mm.c --- linux-2.5.2-pre8/arch/arm/mach-iop310/mm.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-iop310/mm.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,71 @@ +/* + * linux/arch/arm/mach-iop310/mm.c + * + * Low level memory intialization for IOP310 based systems + * + * Author: Nicolas Pitre + * + * Copyright 2000-2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include + +#include +#include +#include + +#include +#include + +#ifdef CONFIG_IOP310_MU +#include "message.h" +#endif + +/* + * Standard IO mapping for all IOP310 based systems + */ +static struct map_desc iop80310_std_desc[] __initdata = { + /* virtual physical length domain r w c b */ + // IOP310 Memory Mapped Registers + { 0xe8001000, 0x00001000, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, + // PCI I/O Space + { 0xfe000000, 0x90000000, 0x00020000, DOMAIN_IO, 0, 1, 0, 0 }, + LAST_DESC +}; + +void __init iop310_map_io(void) +{ + iotable_init(iop80310_std_desc); +} + +/* + * IQ80310 specific IO mappings + */ +#ifdef CONFIG_ARCH_IQ80310 +static struct map_desc iq80310_io_desc[] __initdata = { + /* virtual physical length domain r w c b */ + // IQ80310 On-Board Devices + { 0xfe800000, 0xfe800000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, + LAST_DESC +}; + +void __init iq80310_map_io(void) +{ +#ifdef CONFIG_IOP310_MU + /* acquiring 1MB of memory aligned on 1MB boundary for MU */ + mu_mem = __alloc_bootmem(0x100000, 0x100000, 0); +#endif + + iop310_map_io(); + + iotable_init(iq80310_io_desc); +} +#endif // CONFIG_ARCH_IQ80310 + diff -urN linux-2.5.2-pre8/arch/arm/mach-iop310/xs80200-irq.c linux/arch/arm/mach-iop310/xs80200-irq.c --- linux-2.5.2-pre8/arch/arm/mach-iop310/xs80200-irq.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-iop310/xs80200-irq.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,66 @@ +/* + * linux/arch/arm/mach-iop310/xs80200-irq.c + * + * Generic IRQ handling for the XS80200 XScale core. + * + * Author: Nicolas Pitre + * Copyright: (C) 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +void +xs80200_irq_mask (unsigned int irq) +{ + long INTCTL; + asm ("mrc p13, 0, %0, c0, c0, 0" : "=r" (INTCTL)); + switch (irq) { + case IRQ_XS80200_BCU: INTCTL &= ~(1<<3); break; + case IRQ_XS80200_PMU: INTCTL &= ~(1<<2); break; + case IRQ_XS80200_EXTIRQ: INTCTL &= ~(1<<1); break; + case IRQ_XS80200_EXTFIQ: INTCTL &= ~(1<<0); break; + } + asm ("mcr p13, 0, %0, c0, c0, 0" : : "r" (INTCTL)); +} + +void +xs80200_irq_unmask (unsigned int irq) +{ + long INTCTL; + asm ("mrc p13, 0, %0, c0, c0, 0" : "=r" (INTCTL)); + switch (irq) { + case IRQ_XS80200_BCU: INTCTL |= (1<<3); break; + case IRQ_XS80200_PMU: INTCTL |= (1<<2); break; + case IRQ_XS80200_EXTIRQ: INTCTL |= (1<<1); break; + case IRQ_XS80200_EXTFIQ: INTCTL |= (1<<0); break; + } + asm ("mcr p13, 0, %0, c0, c0, 0" : : "r" (INTCTL)); +} + +void __init xs80200_init_irq(void) +{ + int i; + + for (i = 0; i < NR_XS80200_IRQS; i++) { + irq_desc[i].valid = 1; + irq_desc[i].probe_ok = 0; + irq_desc[i].mask_ack = xs80200_irq_mask; + irq_desc[i].mask = xs80200_irq_mask; + irq_desc[i].unmask = xs80200_irq_unmask; + } +} + + diff -urN linux-2.5.2-pre8/arch/arm/mach-l7200/Makefile linux/arch/arm/mach-l7200/Makefile --- linux-2.5.2-pre8/arch/arm/mach-l7200/Makefile Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-l7200/Makefile Sat Jan 5 14:43:15 2002 @@ -0,0 +1,21 @@ +# +# Makefile for the linux kernel. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). + +USE_STANDARD_AS_RULE := true + +O_TARGET := l7200.o + +# Object file lists. + +obj-y := core.o +obj-m := +obj-n := +obj- := + +export-objs := + +include $(TOPDIR)/Rules.make diff -urN linux-2.5.2-pre8/arch/arm/mach-l7200/core.c linux/arch/arm/mach-l7200/core.c --- linux-2.5.2-pre8/arch/arm/mach-l7200/core.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-l7200/core.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,114 @@ +/* + * linux/arch/arm/mm/mm-lusl7200.c + * + * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) + * + * Extra MM routines for L7200 architecture + */ +#include + +#include +#include +#include + +#include +#include + +/* + * IRQ base register + */ +#define IRQ_BASE (IO_BASE_2 + 0x1000) + +/* + * Normal IRQ registers + */ +#define IRQ_STATUS (*(volatile unsigned long *) (IRQ_BASE + 0x000)) +#define IRQ_RAWSTATUS (*(volatile unsigned long *) (IRQ_BASE + 0x004)) +#define IRQ_ENABLE (*(volatile unsigned long *) (IRQ_BASE + 0x008)) +#define IRQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x00c)) +#define IRQ_SOFT (*(volatile unsigned long *) (IRQ_BASE + 0x010)) +#define IRQ_SOURCESEL (*(volatile unsigned long *) (IRQ_BASE + 0x018)) + +/* + * Fast IRQ registers + */ +#define FIQ_STATUS (*(volatile unsigned long *) (IRQ_BASE + 0x100)) +#define FIQ_RAWSTATUS (*(volatile unsigned long *) (IRQ_BASE + 0x104)) +#define FIQ_ENABLE (*(volatile unsigned long *) (IRQ_BASE + 0x108)) +#define FIQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x10c)) +#define FIQ_SOFT (*(volatile unsigned long *) (IRQ_BASE + 0x110)) +#define FIQ_SOURCESEL (*(volatile unsigned long *) (IRQ_BASE + 0x118)) + +static void l7200_mask_irq(unsigned int irq) +{ + IRQ_ENABLECLEAR = 1 << irq; +} + +static void l7200_unmask_irq(unsigned int irq) +{ + IRQ_ENABLE = 1 << irq; +} + +static void __init l7200_init_irq(void) +{ + int irq; + + IRQ_ENABLECLEAR = 0xffffffff; /* clear all interrupt enables */ + FIQ_ENABLECLEAR = 0xffffffff; /* clear all fast interrupt enables */ + + for (irq = 0; irq < NR_IRQS; irq++) { + irq_desc[irq].valid = 1; + irq_desc[irq].probe_ok = 1; + irq_desc[irq].mask_ack = l7200_mask_irq; + irq_desc[irq].mask = l7200_mask_irq; + irq_desc[irq].unmask = l7200_unmask_irq; + } + + init_FIQ(); +} + +static struct map_desc l7200_io_desc[] __initdata = { + { IO_BASE, IO_START, IO_SIZE, DOMAIN_IO, 0, 1 ,0 ,0}, + { IO_BASE_2, IO_START_2, IO_SIZE_2, DOMAIN_IO, 0, 1 ,0 ,0}, + { AUX_BASE, AUX_START, AUX_SIZE, DOMAIN_IO, 0, 1 ,0 ,0}, + { FLASH1_BASE, FLASH1_START, FLASH1_SIZE, DOMAIN_IO, 0, 1 ,0 ,0}, + { FLASH2_BASE, FLASH2_START, FLASH2_SIZE, DOMAIN_IO, 0, 1 ,0 ,0}, + LAST_DESC +}; + +static void __init l7200_map_io(void) +{ + iotable_init(l7200_io_desc); +} + +static void __init +fixup_l7200(struct machine_desc *desc, struct param_struct *unused, + char **cmdline, struct meminfo *mi) +{ + mi->nr_banks = 1; + mi->bank[0].start = PHYS_OFFSET; + mi->bank[0].size = (32*1024*1024); + mi->bank[0].node = 0; + + ROOT_DEV = MKDEV(RAMDISK_MAJOR,0); + setup_ramdisk( 1, 0, 0, CONFIG_BLK_DEV_RAM_SIZE); + setup_initrd( __phys_to_virt(0xf1000000), 0x005dac7b); + + /* Serial Console COM2 and LCD */ + strcpy( *cmdline, "console=tty0 console=ttyLU1,115200"); + + /* Serial Console COM1 and LCD */ + //strcpy( *cmdline, "console=tty0 console=ttyLU0,115200"); + + /* Console on LCD */ + //strcpy( *cmdline, "console=tty0"); +} + +MACHINE_START(L7200, "LinkUp Systems L7200") + MAINTAINER("Steve Hill / Scott McConnell") + BOOT_MEM(0xf0000000, 0x80040000, 0xd0000000) + FIXUP(fixup_l7200) + MAPIO(l7200_map_io) + INITIRQ(l7200_init_irq) +MACHINE_END + diff -urN linux-2.5.2-pre8/arch/arm/mach-rpc/Makefile linux/arch/arm/mach-rpc/Makefile --- linux-2.5.2-pre8/arch/arm/mach-rpc/Makefile Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-rpc/Makefile Sat Jan 5 14:43:15 2002 @@ -0,0 +1,22 @@ +# +# Makefile for the linux kernel. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). + +USE_STANDARD_AS_RULE := true + +O_TARGET := rpc.o + +# Object file lists. + +obj-y := dma.o irq.o riscpc.o +obj-m := +obj-n := +obj- := + +export-objs := + + +include $(TOPDIR)/Rules.make diff -urN linux-2.5.2-pre8/arch/arm/mach-rpc/irq.c linux/arch/arm/mach-rpc/irq.c --- linux-2.5.2-pre8/arch/arm/mach-rpc/irq.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-rpc/irq.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,142 @@ +#include + +#include +#include +#include +#include + +static void rpc_mask_irq_ack_a(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << irq; + val = iomd_readb(IOMD_IRQMASKA); + iomd_writeb(val & ~mask, IOMD_IRQMASKA); + iomd_writeb(mask, IOMD_IRQCLRA); +} + +static void rpc_mask_irq_a(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << irq; + val = iomd_readb(IOMD_IRQMASKA); + iomd_writeb(val & ~mask, IOMD_IRQMASKA); +} + +static void rpc_unmask_irq_a(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << irq; + val = iomd_readb(IOMD_IRQMASKA); + iomd_writeb(val | mask, IOMD_IRQMASKA); +} + +static void rpc_mask_irq_b(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_IRQMASKB); + iomd_writeb(val & ~mask, IOMD_IRQMASKB); +} + +static void rpc_unmask_irq_b(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_IRQMASKB); + iomd_writeb(val | mask, IOMD_IRQMASKB); +} + +static void rpc_mask_irq_dma(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_DMAMASK); + iomd_writeb(val & ~mask, IOMD_DMAMASK); +} + +static void rpc_unmask_irq_dma(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_DMAMASK); + iomd_writeb(val | mask, IOMD_DMAMASK); +} + +static void rpc_mask_irq_fiq(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_FIQMASK); + iomd_writeb(val & ~mask, IOMD_FIQMASK); +} + +static void rpc_unmask_irq_fiq(unsigned int irq) +{ + unsigned int val, mask; + + mask = 1 << (irq & 7); + val = iomd_readb(IOMD_FIQMASK); + iomd_writeb(val | mask, IOMD_FIQMASK); +} + +void __init rpc_init_irq(void) +{ + int irq; + + iomd_writeb(0, IOMD_IRQMASKA); + iomd_writeb(0, IOMD_IRQMASKB); + iomd_writeb(0, IOMD_FIQMASK); + iomd_writeb(0, IOMD_DMAMASK); + + for (irq = 0; irq < NR_IRQS; irq++) { + switch (irq) { + case 0 ... 6: + irq_desc[irq].probe_ok = 1; + case 7: + irq_desc[irq].valid = 1; + irq_desc[irq].mask_ack = rpc_mask_irq_ack_a; + irq_desc[irq].mask = rpc_mask_irq_a; + irq_desc[irq].unmask = rpc_unmask_irq_a; + break; + + case 9 ... 15: + irq_desc[irq].probe_ok = 1; + case 8: + irq_desc[irq].valid = 1; + irq_desc[irq].mask_ack = rpc_mask_irq_b; + irq_desc[irq].mask = rpc_mask_irq_b; + irq_desc[irq].unmask = rpc_unmask_irq_b; + break; + + case 16 ... 19: + case 21: + irq_desc[irq].noautoenable = 1; + case 20: + irq_desc[irq].valid = 1; + irq_desc[irq].mask_ack = rpc_mask_irq_dma; + irq_desc[irq].mask = rpc_mask_irq_dma; + irq_desc[irq].unmask = rpc_unmask_irq_dma; + break; + + case 64 ... 71: + irq_desc[irq].valid = 1; + irq_desc[irq].mask_ack = rpc_mask_irq_fiq; + irq_desc[irq].mask = rpc_mask_irq_fiq; + irq_desc[irq].unmask = rpc_unmask_irq_fiq; + break; + } + } + + irq_desc[IRQ_KEYBOARDTX].noautoenable = 1; + + init_FIQ(); +} + diff -urN linux-2.5.2-pre8/arch/arm/mach-rpc/riscpc.c linux/arch/arm/mach-rpc/riscpc.c --- linux-2.5.2-pre8/arch/arm/mach-rpc/riscpc.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-rpc/riscpc.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,94 @@ +/* + * linux/arch/arm/mach-rpc/riscpc.c + * + * Copyright (C) 1998-2001 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Architecture specific fixups. + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +extern void rpc_init_irq(void); + +extern unsigned int vram_size; + +#if 0 + +unsigned int memc_ctrl_reg; +unsigned int number_mfm_drives; + +static int __init parse_tag_acorn(const struct tag *tag) +{ + memc_ctrl_reg = tag->u.acorn.memc_control_reg; + number_mfm_drives = tag->u.acorn.adfsdrives; + + switch (tag->u.acorn.vram_pages) { + case 512: + vram_size += PAGE_SIZE * 256; + case 256: + vram_size += PAGE_SIZE * 256; + default: + break; + } +#if 0 + if (vram_size) { + desc->video_start = 0x02000000; + desc->video_end = 0x02000000 + vram_size; + } +#endif + return 0; +} + +__tagtable(ATAG_ACORN, parse_tag_acorn); + +#endif + +static void __init +fixup_riscpc(struct machine_desc *desc, struct param_struct *unusd, + char **cmdline, struct meminfo *mi) +{ + /* + * RiscPC can't handle half-word loads and stores + */ + elf_hwcap &= ~HWCAP_HALF; +} + +static struct map_desc rpc_io_desc[] __initdata = { + { SCREEN_BASE, SCREEN_START, 2*1048576, DOMAIN_IO, 0, 1, 0, 0 }, /* VRAM */ + { IO_BASE, IO_START, IO_SIZE , DOMAIN_IO, 0, 1, 0, 0 }, /* IO space */ + { EASI_BASE, EASI_START, EASI_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* EASI space */ + LAST_DESC +}; + +void __init rpc_map_io(void) +{ + iotable_init(rpc_io_desc); +} + +MACHINE_START(RISCPC, "Acorn-RiscPC") + MAINTAINER("Russell King") + BOOT_MEM(0x10000000, 0x03000000, 0xe0000000) + BOOT_PARAMS(0x10000100) + DISABLE_PARPORT(0) + DISABLE_PARPORT(1) + FIXUP(fixup_riscpc) + MAPIO(rpc_map_io) + INITIRQ(rpc_init_irq) +MACHINE_END diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/Makefile linux/arch/arm/mach-sa1100/Makefile --- linux-2.5.2-pre8/arch/arm/mach-sa1100/Makefile Thu Oct 25 13:53:45 2001 +++ linux/arch/arm/mach-sa1100/Makefile Sat Jan 5 14:43:15 2002 @@ -9,20 +9,15 @@ O_TARGET := sa1100.o -obj-y := +# Common support (must be linked before board specific support) +obj-y := generic.o irq.o dma.o obj-m := obj-n := obj- := -export-objs := assabet.o dma-sa1100.o dma-sa1111.o freebird.o generic.o \ - h3600.o huw_webpanel.o irq.o pcipool.o sa1111-pcibuf.o \ - yopy.o - -# These aren't present yet, and prevents a plain -ac kernel building. -# hwtimer.o usb_ctl.o usb_recv.o usb_send.o - -# Common support (must be linked before board specific support) -obj-y += generic.o irq.o dma-sa1100.o +export-objs := assabet.o dma.o flexanet.o freebird.o generic.o h3600.o \ + huw_webpanel.o irq.o pcipool.o sa1111.o sa1111-pcibuf.o \ + yopy.o usb_ctl.o usb_recv.o usb_send.o # This needs to be cleaned up. We probably need to have SA1100 # and SA1110 config symbols. @@ -31,11 +26,12 @@ ifeq ($(CONFIG_CPU_FREQ),y) obj-$(CONFIG_SA1100_ASSABET) += cpu-sa1110.o obj-$(CONFIG_SA1100_CERF) += cpu-sa1110.o +obj-$(CONFIG_SA1100_PT_SYSTEM3) += cpu-sa1110.o obj-$(CONFIG_SA1100_LART) += cpu-sa1100.o endif # Next, the SA1111 stuff. -obj-$(CONFIG_SA1111) += sa1111.o dma-sa1111.o +obj-$(CONFIG_SA1111) += sa1111.o obj-$(CONFIG_USB_OHCI_SA1111) += sa1111-pcibuf.o pcipool.o # Specific board support @@ -59,7 +55,9 @@ obj-$(CONFIG_SA1100_PANGOLIN) += pangolin.o obj-$(CONFIG_SA1100_PFS168) += pfs168.o obj-$(CONFIG_SA1100_PLEB) += pleb.o +obj-$(CONFIG_SA1100_SHANNON) += shannon.o obj-$(CONFIG_SA1100_SHERMAN) += sherman.o +obj-$(CONFIG_SA1100_PT_SYSTEM3) += system3.o obj-$(CONFIG_SA1100_SIMPAD) += simpad.o obj-$(CONFIG_SA1100_VICTOR) += victor.o obj-$(CONFIG_SA1100_XP860) += xp860.o @@ -77,9 +75,21 @@ leds-$(CONFIG_SA1100_LART) += leds-lart.o leds-$(CONFIG_SA1100_PFS168) += leds-pfs168.o leds-$(CONFIG_SA1100_SIMPAD) += leds-simpad.o +leds-$(CONFIG_SA1100_PT_SYSTEM3) += leds-system3.o obj-$(CONFIG_LEDS) += $(leds-y) +# SA1110 USB client support +list-multi += sa1100usb_core.o +sa1100usb_core-objs := usb_ctl.o usb_ep0.o usb_recv.o usb_send.o +obj-$(CONFIG_SA1100_USB) += sa1100usb_core.o +obj-$(CONFIG_SA1100_USB_NETLINK) += usb-eth.o +obj-$(CONFIG_SA1100_USB_CHAR) += usb-char.o + # Miscelaneous functions obj-$(CONFIG_PM) += pm.o sleep.o include $(TOPDIR)/Rules.make + +sa1100usb_core.o: $(sa1100usb_core-objs) + $(LD) -r -o $@ $(sa1100usb_core-objs) + diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/adsbitsy.c linux/arch/arm/mach-sa1100/adsbitsy.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/adsbitsy.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/mach-sa1100/adsbitsy.c Sat Jan 5 14:43:15 2002 @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -53,7 +54,7 @@ /* * Probe for SA1111. */ - ret = sa1111_probe(); + ret = sa1111_probe(0x18000000); if (ret < 0) return ret; @@ -94,7 +95,7 @@ sa1110_mb_enable(); set_GPIO_IRQ_edge(GPIO_GPIO0, GPIO_RISING_EDGE); - sa1111_init_irq(SA1100_GPIO_TO_IRQ(0)); + sa1111_init_irq(IRQ_GPIO0); return 0; } @@ -126,7 +127,6 @@ static struct map_desc adsbitsy_io_desc[] __initdata = { /* virtual physical length domain r w c b */ - { 0xe8000000, 0x08000000, 0x01000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 1 */ { 0xf4000000, 0x18000000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* SA1111 */ LAST_DESC }; @@ -135,24 +135,15 @@ { if (port->mapbase == _Ser1UTCR0) { Ser1SDCR0 |= SDCR0_UART; - // Set RTS Output and High (should be done in the set_mctrl fn) - GPDR |= GPIO_GPIO15; - GPCR |= GPIO_GPIO15; - // Set CTS Input - GPDR &= ~GPIO_GPIO14; +#error Fixme // Set RTS High (should be done in the set_mctrl fn) + GPCR = GPIO_GPIO15; } else if (port->mapbase == _Ser2UTCR0) { Ser2UTCR4 = Ser2HSCR0 = 0; - // Set RTS Output and High (should be done in the set_mctrl fn) - GPDR |= GPIO_GPIO17; - GPCR |= GPIO_GPIO17; - // Set CTS Input - GPDR &= ~GPIO_GPIO16; +#error Fixme // Set RTS High (should be done in the set_mctrl fn) + GPCR = GPIO_GPIO17; } else if (port->mapbase == _Ser2UTCR0) { - // Set RTS Output and High (should be done in the set_mctrl fn) - GPDR |= GPIO_GPIO19; - GPCR |= GPIO_GPIO19; - // Set CTS Input - GPDR &= ~GPIO_GPIO18; +#error Fixme // Set RTS High (should be done in the set_mctrl fn) + GPCR = GPIO_GPIO19; } return 0; } @@ -166,10 +157,12 @@ sa1100_map_io(); iotable_init(adsbitsy_io_desc); - sa1110_register_uart_fns(&adsbitsy_port_fns); + sa1100_register_uart_fns(&adsbitsy_port_fns); sa1100_register_uart(0, 3); sa1100_register_uart(1, 1); sa1100_register_uart(2, 2); + GPDR |= GPIO_GPIO15 | GPIO_GPIO17 | GPIO_GPIO19; + GPDR &= ~(GPIO_GPIO14 | GPIO_GPIO16 | GPIO_GPIO18); } MACHINE_START(ADSBITSY, "ADS Bitsy") diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/assabet.c linux/arch/arm/mach-sa1100/assabet.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/assabet.c Thu Oct 25 13:53:45 2001 +++ linux/arch/arm/mach-sa1100/assabet.c Sat Jan 5 14:43:15 2002 @@ -31,16 +31,70 @@ #include "generic.h" +#define ASSABET_BCR_DB1110 \ + (ASSABET_BCR_SPK_OFF | ASSABET_BCR_QMUTE | \ + ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \ + ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \ + ASSABET_BCR_IRDA_MD0) + +#define ASSABET_BCR_DB1111 \ + (ASSABET_BCR_SPK_OFF | ASSABET_BCR_QMUTE | \ + ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \ + ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \ + ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \ + ASSABET_BCR_IRDA_MD0 | ASSABET_BCR_CF_RST) -unsigned long BCR_value = ASSABET_BCR_DB1110; unsigned long SCR_value = ASSABET_SCR_INIT; -EXPORT_SYMBOL(BCR_value); EXPORT_SYMBOL(SCR_value); +static unsigned long BCR_value = ASSABET_BCR_DB1110; + +void ASSABET_BCR_frob(unsigned int mask, unsigned int val) +{ + unsigned long flags; + + local_irq_save(flags); + BCR_value = (BCR_value & ~mask) | val; + ASSABET_BCR = BCR_value; + local_irq_restore(flags); +} + +EXPORT_SYMBOL(ASSABET_BCR_frob); + +static void assabet_backlight_power(int on) +{ +#ifndef ASSABET_PAL_VIDEO + if (on) + ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON); + else +#endif + ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON); +} + +static void assabet_lcd_power(int on) +{ +#ifndef ASSABET_PAL_VIDEO + if (on) + ASSABET_BCR_set(ASSABET_BCR_LCD_ON); + else +#endif + ASSABET_BCR_clear(ASSABET_BCR_LCD_ON); +} static int __init assabet_init(void) { - if (machine_is_assabet() && machine_has_neponset()) { + if (!machine_is_assabet()) + return -EINVAL; + + /* + * Set the IRQ edges + */ + set_GPIO_IRQ_edge(GPIO_GPIO23, GPIO_RISING_EDGE); /* UCB1300 */ + + sa1100fb_lcd_power = assabet_lcd_power; + sa1100fb_backlight_power = assabet_backlight_power; + + if (machine_has_neponset()) { /* * Angel sets this, but other bootloaders may not. * @@ -55,6 +109,7 @@ "hasn't been configured in the kernel\n" ); #endif } + return 0; } @@ -87,18 +142,18 @@ * repeat it here because the kernel may not be loaded as a zImage, and * also because it's a hassle to communicate the SCR value to the kernel * from the decompressor. + * + * Note that IRQs are guaranteed to be disabled. */ static void __init get_assabet_scr(void) { - unsigned long flags, scr, i; + unsigned long scr, i; - local_irq_save(flags); GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */ GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */ GPDR &= ~(0x3fc); /* Configure GPIO 9:2 as inputs */ for(i = 100; i--; scr = GPLR); /* Read GPIO 9:2 */ GPDR |= 0x3fc; /* restore correct pin direction */ - local_irq_restore(flags); scr &= 0x3fc; /* save as system configuration byte. */ SCR_value = scr; } @@ -174,7 +229,6 @@ static struct map_desc assabet_io_desc[] __initdata = { /* virtual physical length domain r w c b */ - { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */ { 0xf1000000, 0x12000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* Board Control Register */ { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* MQ200 */ /* f3000000 - neponset system registers */ @@ -186,19 +240,18 @@ { if (port->mapbase == _Ser1UTCR0) { if (state) - ASSABET_BCR_clear(ASSABET_BCR_RS232EN); + ASSABET_BCR_clear(ASSABET_BCR_RS232EN | + ASSABET_BCR_COM_RTS | + ASSABET_BCR_COM_DTR); else - ASSABET_BCR_set(ASSABET_BCR_RS232EN); + ASSABET_BCR_set(ASSABET_BCR_RS232EN | + ASSABET_BCR_COM_RTS | + ASSABET_BCR_COM_DTR); } } /* - * Note! this can be called from IRQ context. - * FIXME: You _need_ to handle ASSABET_BCR carefully, which doesn't - * happen at the moment. Suggest putting interrupt save/restore - * in ASSABET_BCR_set/clear. - * - * NB: Assabet uses COM_RTS and COM_DTR for both UART1 (com port) + * Assabet uses COM_RTS and COM_DTR for both UART1 (com port) * and UART3 (radio module). We only handle them for UART1 here. */ static void assabet_set_mctrl(struct uart_port *port, u_int mctrl) @@ -207,21 +260,21 @@ u_int set = 0, clear = 0; if (mctrl & TIOCM_RTS) - set |= ASSABET_BCR_COM_RTS; - else clear |= ASSABET_BCR_COM_RTS; + else + set |= ASSABET_BCR_COM_RTS; if (mctrl & TIOCM_DTR) - set |= ASSABET_BCR_COM_DTR; - else clear |= ASSABET_BCR_COM_DTR; + else + set |= ASSABET_BCR_COM_DTR; ASSABET_BCR_clear(clear); ASSABET_BCR_set(set); } } -static int assabet_get_mctrl(struct uart_port *port) +static u_int assabet_get_mctrl(struct uart_port *port) { u_int ret = 0; u_int bsr = ASSABET_BSR; @@ -312,11 +365,7 @@ PWER = PWER_GPIO0; PGSR = 0; PCFR = 0; - - /* - * Clear all possible wakeup reasons. - */ - RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR; + PSDR = 0; } diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/cerf.c linux/arch/arm/mach-sa1100/cerf.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/cerf.c Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-sa1100/cerf.c Sat Jan 5 14:43:15 2002 @@ -16,20 +16,22 @@ #include "generic.h" -static void __init cerf_init_irq (void) +static void __init cerf_init_irq(void) { - sa1100_init_irq(); + sa1100_init_irq(); - /* Need to register these as rising edge interrupts - * For standard 16550 serial driver support - * Basically - I copied it from pfs168.c :) - */ + /* Need to register these as rising edge interrupts + * For standard 16550 serial driver support + * Basically - I copied it from pfs168.c :) + */ #ifdef CONFIG_SA1100_CERF_CPLD - set_GPIO_IRQ_edge(GPIO_GPIO(3), GPIO_RISING_EDGE); /* PDA Full serial port */ - set_GPIO_IRQ_edge(GPIO_GPIO(2), GPIO_RISING_EDGE); /* PDA Bluetooth */ - GPDR &= ~(GPIO_GPIO(3)); /* Set the direction of serial port GPIO pin to in */ - GPDR &= ~(GPIO_GPIO(2)); /* Set the direction of bluetooth GPIO pin to in */ + /* PDA Full serial port */ + set_GPIO_IRQ_edge(GPIO_GPIO3, GPIO_RISING_EDGE); + /* PDA Bluetooth */ + set_GPIO_IRQ_edge(GPIO_GPIO2, GPIO_RISING_EDGE); #endif /* CONFIG_SA1100_CERF_CPLD */ + + set_GPIO_IRQ_edge(GPIO_UCB1200_IRQ, GPIO_RISING_EDGE); } static void __init @@ -37,22 +39,20 @@ char **cmdline, struct meminfo *mi) { #if defined(CONFIG_SA1100_CERF_64MB) - // 64MB RAM - SET_BANK( 0, 0xc0000000, 64*1024*1024 ); - mi->nr_banks = 1; -#elif defined(CONFIG_SA1100_CERF_32MB) // 32MB RAM + SET_BANK( 0, 0xc0000000, 64*1024*1024 ); + mi->nr_banks = 1; +#elif defined(CONFIG_SA1100_CERF_32MB) SET_BANK( 0, 0xc0000000, 32*1024*1024 ); mi->nr_banks = 1; -#elif defined(CONFIG_SA1100_CERF_16MB) // 16Meg Ram. +#elif defined(CONFIG_SA1100_CERF_16MB) SET_BANK( 0, 0xc0000000, 8*1024*1024 ); SET_BANK( 1, 0xc8000000, 8*1024*1024 ); mi->nr_banks = 2; #elif defined(CONFIG_SA1100_CERF_8MB) - // 8Meg Ram. - SET_BANK( 0, 0xc0000000, 8*1024*1024 ); - mi->nr_banks = 1; + SET_BANK( 0, 0xc0000000, 8*1024*1024 ); + mi->nr_banks = 1; #else - #error "Undefined memory size for Cerfboard." +#error "Undefined memory size for Cerfboard." #endif // ROOT_DEV = MKDEV(RAMDISK_MAJOR,0); @@ -62,8 +62,7 @@ } static struct map_desc cerf_io_desc[] __initdata = { - /* virtual physical length domain r w c b */ - { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */ + /* virtual physical length domain r w c b */ { 0xf0000000, 0x08000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* Crystal Ethernet Chip */ #ifdef CONFIG_SA1100_CERF_CPLD { 0xf1000000, 0x40000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* CPLD Chip */ @@ -78,12 +77,18 @@ sa1100_map_io(); iotable_init(cerf_io_desc); - sa1100_register_uart(0, 3); + sa1100_register_uart(0, 3); #ifdef CONFIG_SA1100_CERF_IRDA_ENABLED sa1100_register_uart(1, 1); #else sa1100_register_uart(1, 2); sa1100_register_uart(2, 1); +#endif + + /* set some GPDR bits here while it's safe */ + GPDR |= GPIO_CF_RESET; +#ifdef CONFIG_SA1100_CERF_CPLD + GPDR |= GPIO_PWR_SHUTDOWN; #endif } diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/cpu-sa1100.c linux/arch/arm/mach-sa1100/cpu-sa1100.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/cpu-sa1100.c Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/mach-sa1100/cpu-sa1100.c Sat Jan 5 14:43:15 2002 @@ -90,7 +90,8 @@ #include - +extern unsigned int sa11x0_freq_to_ppcr(unsigned int khz); +extern unsigned int sa11x0_validatespeed(unsigned int khz); typedef struct { @@ -219,14 +220,22 @@ }; - +static void sa1100_setspeed(unsigned int khz) +{ + PPCR = sa11x0_freq_to_ppcr(khz); +} static int __init sa1100_dram_init(void) { - return cpufreq_register_notifier(&sa1100_dram_block); -} + int ret = -ENODEV; + if ((processor_id & CPU_SA1100_MASK) == CPU_SA1100_ID) { + ret = cpufreq_register_notifier(&sa1100_dram_block); + cpufreq_setfunctions(sa11x0_validatespeed, sa1100_setspeed); + } + return ret; +} __initcall(sa1100_dram_init); diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/cpu-sa1110.c linux/arch/arm/mach-sa1100/cpu-sa1110.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/cpu-sa1110.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/mach-sa1100/cpu-sa1110.c Sat Jan 5 14:43:15 2002 @@ -3,7 +3,7 @@ * * Copyright (C) 2001 Russell King * - * $Id: cpu-sa1110.c,v 1.5 2001/09/10 13:25:58 rmk Exp $ + * $Id: cpu-sa1110.c,v 1.6 2001/10/22 11:53:47 rmk Exp $ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -29,14 +29,8 @@ #undef DEBUG -extern u_int processor_id; - -#define CPU_REVISION (processor_id & 15) -#define CPU_SA1110_A0 (0) -#define CPU_SA1110_B0 (4) -#define CPU_SA1110_B1 (5) -#define CPU_SA1110_B2 (6) -#define CPU_SA1110_B4 (8) +extern unsigned int sa11x0_freq_to_ppcr(unsigned int khz); +extern unsigned int sa11x0_validatespeed(unsigned int khz); struct sdram_params { u_char rows; /* bits */ @@ -48,6 +42,12 @@ u_short refresh; /* refresh time for array (us) */ }; +struct sdram_info { + u_int mdcnfg; + u_int mdrefr; + u_int mdcas[3]; +}; + static struct sdram_params tc59sm716_cl2_params __initdata = { rows: 12, tck: 10, @@ -68,6 +68,16 @@ cas_latency: 3, }; +static struct sdram_params samsung_k4s641632d_tc75 __initdata = { + rows: 14, + tck: 9, + trcd: 27, + trp: 20, + twr: 9, + refresh: 64000, + cas_latency: 3, +}; + static struct sdram_params sdram_params; /* @@ -95,10 +105,11 @@ mdcas[1] = mdcas[2] = 0x55555555 << (shift & 1); } -static void sdram_update_timing(u_int cpu_khz, struct sdram_params *sdram) +static void +sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz, + struct sdram_params *sdram) { - u_int mdcnfg, mdrefr, mdcas[3], mem_khz, sd_khz, trp, twr; - unsigned long flags; + u_int mem_khz, sd_khz, trp, twr; mem_khz = cpu_khz / 2; sd_khz = mem_khz; @@ -114,7 +125,7 @@ (CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000)) sd_khz /= 2; - mdcnfg = MDCNFG & 0x007f007f; + sd->mdcnfg = MDCNFG & 0x007f007f; twr = ns_to_cycles(sdram->twr, mem_khz); @@ -123,53 +134,26 @@ if (trp < 1) trp = 1; - mdcnfg |= trp << 8; - mdcnfg |= trp << 24; - mdcnfg |= sdram->cas_latency << 12; - mdcnfg |= sdram->cas_latency << 28; - mdcnfg |= twr << 14; - mdcnfg |= twr << 30; + sd->mdcnfg |= trp << 8; + sd->mdcnfg |= trp << 24; + sd->mdcnfg |= sdram->cas_latency << 12; + sd->mdcnfg |= sdram->cas_latency << 28; + sd->mdcnfg |= twr << 14; + sd->mdcnfg |= twr << 30; - mdrefr = MDREFR & 0xffbffff0; - mdrefr |= 7; + sd->mdrefr = MDREFR & 0xffbffff0; + sd->mdrefr |= 7; if (sd_khz != mem_khz) - mdrefr |= MDREFR_K1DB2; + sd->mdrefr |= MDREFR_K1DB2; /* initial number of '1's in MDCAS + 1 */ - set_mdcas(mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz)); + set_mdcas(sd->mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz)); #ifdef DEBUG - mdelay(250); printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n", - mdcnfg, mdrefr, mdcas[0], mdcas[1], mdcas[2]); + sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], sd->mdcas[2]); #endif - - /* - * Reprogram the DRAM timings with interrupts disabled, and - * ensure that we are doing this within a complete cache line. - * This means that we won't access SDRAM for the duration of - * the programming. - */ - local_irq_save(flags); - asm("mcr p15, 0, %0, c10, c4" : : "r" (0)); - udelay(10); - __asm__(" - b 1f - .align 5 -1: str %3, [%1, #28] @ MDREFR - str %4, [%1, #4] @ MDCAS0 - str %5, [%1, #8] @ MDCAS1 - str %6, [%1, #12] @ MDCAS2 - str %2, [%1, #0] @ MDCNFG - ldr %0, [%1, #0] - nop - nop" - : "=&r" (mdcnfg) - : "r" (io_p2v(_MDCNFG)), - "0" (mdcnfg), "r" (mdrefr), - "r" (mdcas[0]), "r" (mdcas[1]), "r" (mdcas[2])); - local_irq_restore(flags); } /* @@ -203,65 +187,93 @@ sdram_set_refresh(dri); } -static int -sdram_notifier(struct notifier_block *nb, unsigned long val, void *data) +/* + * Ok, set the CPU frequency. Since we've done the validation + * above, we can match for an exact frequency. If we don't find + * an exact match, we will to set the lowest frequency to be safe. + */ +static void sa1110_setspeed(unsigned int khz) { - struct cpufreq_info *ci = data; struct sdram_params *sdram = &sdram_params; + struct sdram_info sd; + unsigned long flags; + unsigned int ppcr, unused; - /* were we initialised? */ - if (sdram->cas_latency == 0) { - struct cpufreq_minmax *m = data; - m->min_freq = m->max_freq = m->cur_freq; - return 0; - } + ppcr = sa11x0_freq_to_ppcr(khz); + sdram_calculate_timing(&sd, khz, sdram); - switch (val) { - case CPUFREQ_MINMAX: - /* - * until we work out why the assabet - * crashes below 147.5MHz... - */ - cpufreq_updateminmax(data, 147500, -1); - break; - - case CPUFREQ_PRECHANGE: - /* - * The clock could be going away for some time. - * Set the SDRAMs to refresh rapidly (every 64 - * memory clock cycles). To get through the - * whole array, we need to wait 262144 mclk cycles. - * We wait 20ms to be safe. - */ - sdram_set_refresh(2); - set_current_state(TASK_UNINTERRUPTIBLE); - schedule_timeout(20 * HZ / 1000); - - if (ci->old_freq < ci->new_freq) - sdram_update_timing(ci->new_freq, sdram); - break; - - case CPUFREQ_POSTCHANGE: - if (ci->old_freq > ci->new_freq) - sdram_update_timing(ci->new_freq, sdram); - sdram_update_refresh(ci->new_freq, sdram); - break; +#if 0 + /* + * These values are wrong according to the SA1110 documentation + * and errata, but they seem to work. Need to get a storage + * scope on to the SDRAM signals to work out why. + */ + if (khz < 147500) { + sd.mdrefr |= MDREFR_K1DB2; + sd.mdcas[0] = 0xaaaaaa7f; + } else { + sd.mdrefr &= ~MDREFR_K1DB2; + sd.mdcas[0] = 0xaaaaaa9f; } - return 0; -} + sd.mdcas[1] = 0xaaaaaaaa; + sd.mdcas[2] = 0xaaaaaaaa; +#endif + /* + * The clock could be going away for some time. Set the SDRAMs + * to refresh rapidly (every 64 memory clock cycles). To get + * through the whole array, we need to wait 262144 mclk cycles. + * We wait 20ms to be safe. + */ + sdram_set_refresh(2); + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(20 * HZ / 1000); -static struct notifier_block sa1110_clkchg_block = { - notifier_call: sdram_notifier, -}; + /* + * Reprogram the DRAM timings with interrupts disabled, and + * ensure that we are doing this within a complete cache line. + * This means that we won't access SDRAM for the duration of + * the programming. + */ + local_irq_save(flags); + asm("mcr p15, 0, %0, c10, c4" : : "r" (0)); + udelay(10); + __asm__ __volatile__(" + b 2f + .align 5 +1: str %3, [%1, #0] @ MDCNFG + str %4, [%1, #28] @ MDREFR + str %5, [%1, #4] @ MDCAS0 + str %6, [%1, #8] @ MDCAS1 + str %7, [%1, #12] @ MDCAS2 + str %8, [%2, #0] @ PPCR + ldr %0, [%1, #0] + b 3f +2: b 1b +3: nop + nop" + : "=&r" (unused) + : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg), + "r" (sd.mdrefr), "r" (sd.mdcas[0]), + "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr)); + local_irq_restore(flags); -static int __init sa1110_sdram_init(void) + /* + * Now, return the SDRAM refresh back to normal. + */ + sdram_update_refresh(khz, sdram); +} + +static int __init sa1110_clk_init(void) { struct sdram_params *sdram = NULL; - unsigned int cur_freq = cpufreq_get(smp_processor_id()); if (machine_is_assabet()) sdram = &tc59sm716_cl3_params; + if (machine_is_pt_system3()) + sdram = &samsung_k4s641632d_tc75; + + if (sdram) { printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d" " twr: %d refresh: %d cas_latency: %d\n", @@ -270,11 +282,11 @@ memcpy(&sdram_params, sdram, sizeof(sdram_params)); - sdram_update_timing(cur_freq, &sdram_params); - sdram_update_refresh(cur_freq, &sdram_params); + sa1110_setspeed(cpufreq_get(0)); + cpufreq_setfunctions(sa11x0_validatespeed, sa1110_setspeed); } - return cpufreq_register_notifier(&sa1110_clkchg_block); + return 0; } -__initcall(sa1110_sdram_init); +__initcall(sa1110_clk_init); diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/dma-sa1100.c linux/arch/arm/mach-sa1100/dma-sa1100.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/dma-sa1100.c Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-sa1100/dma-sa1100.c Wed Dec 31 16:00:00 1969 @@ -1,620 +0,0 @@ -/* - * arch/arm/kernel/dma-sa1100.c - * - * Support functions for the SA11x0 internal DMA channels. - * (see also Documentation/arm/SA1100/DMA) - * - * Copyright (C) 2000 Nicolas Pitre - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - - -#undef DEBUG -#ifdef DEBUG -#define DPRINTK( s, arg... ) printk( "dma<%s>: " s, dma->device_id , ##arg ) -#else -#define DPRINTK( x... ) -#endif - - -/* - * DMA control register structure - */ -typedef struct { - volatile u_long DDAR; - volatile u_long SetDCSR; - volatile u_long ClrDCSR; - volatile u_long RdDCSR; - volatile dma_addr_t DBSA; - volatile u_long DBTA; - volatile dma_addr_t DBSB; - volatile u_long DBTB; -} dma_regs_t; - -#include "dma.h" - -sa1100_dma_t dma_chan[MAX_SA1100_DMA_CHANNELS]; - -/* - * Maximum physical DMA buffer size - */ -#define MAX_DMA_SIZE 0x1fff -#define MAX_DMA_ORDER 12 - - -/* - * DMA processing... - */ - -static inline int start_sa1100_dma(sa1100_dma_t * dma, dma_addr_t dma_ptr, int size) -{ - dma_regs_t *regs = dma->regs; - int status; - - status = regs->RdDCSR; - - /* If both DMA buffers are started, there's nothing else we can do. */ - if ((status & (DCSR_STRTA | DCSR_STRTB)) == (DCSR_STRTA | DCSR_STRTB)) { - DPRINTK("start: st %#x busy\n", status); - return -EBUSY; - } - - if (((status & DCSR_BIU) && (status & DCSR_STRTB)) || - (!(status & DCSR_BIU) && !(status & DCSR_STRTA))) { - if (status & DCSR_DONEA) { - /* give a chance for the interrupt to be processed */ - goto irq_pending; - } - regs->DBSA = dma_ptr; - regs->DBTA = size; - regs->SetDCSR = DCSR_STRTA | DCSR_IE | DCSR_RUN; - DPRINTK("start a=%#x s=%d on A\n", dma_ptr, size); - } else { - if (status & DCSR_DONEB) { - /* give a chance for the interrupt to be processed */ - goto irq_pending; - } - regs->DBSB = dma_ptr; - regs->DBTB = size; - regs->SetDCSR = DCSR_STRTB | DCSR_IE | DCSR_RUN; - DPRINTK("start a=%#x s=%d on B\n", dma_ptr, size); - } - - return 0; - -irq_pending: - return -EAGAIN; -} - - -static int start_dma(sa1100_dma_t *dma, dma_addr_t dma_ptr, int size) -{ - if (channel_is_sa1111_sac(dma - dma_chan)) - return start_sa1111_sac_dma(dma, dma_ptr, size); - return start_sa1100_dma(dma, dma_ptr, size); -} - - -/* This must be called with IRQ disabled */ -static void process_dma(sa1100_dma_t * dma) -{ - dma_buf_t *buf; - int chunksize; - - for (;;) { - buf = dma->tail; - - if (!buf || dma->stopped) { - /* no more data available */ - DPRINTK("process: no more buf (dma %s)\n", - dma->curr ? "active" : "inactive"); - /* - * Some devices may require DMA still sending data - * at any time for clock reference, etc. - * Note: if there is still a data buffer being - * processed then the ref count is negative. This - * allows for the DMA termination to be accounted in - * the proper order. - */ - if (dma->spin_size && dma->spin_ref >= 0) { - chunksize = dma->spin_size; - if (chunksize > MAX_DMA_SIZE) - chunksize = (1 << MAX_DMA_ORDER); - while (start_dma(dma, dma->spin_addr, chunksize) == 0) - dma->spin_ref++; - if (dma->curr != NULL) - dma->spin_ref = -dma->spin_ref; - } - break; - } - - /* - * Let's try to start DMA on the current buffer. - * If DMA is busy then we break here. - */ - chunksize = buf->size; - if (chunksize > MAX_DMA_SIZE) - chunksize = (1 << MAX_DMA_ORDER); - DPRINTK("process: b=%#x s=%d\n", (int) buf->id, buf->size); - if (start_dma(dma, buf->dma_ptr, chunksize) != 0) - break; - if (!dma->curr) - dma->curr = buf; - buf->ref++; - buf->dma_ptr += chunksize; - buf->size -= chunksize; - if (buf->size == 0) { - /* current buffer is done: move tail to the next one */ - dma->tail = buf->next; - DPRINTK("process: next b=%#x\n", (int) dma->tail); - } - } -} - - -/* This must be called with IRQ disabled */ -void sa1100_dma_done (sa1100_dma_t *dma) -{ - dma_buf_t *buf = dma->curr; - - if (dma->spin_ref > 0) { - dma->spin_ref--; - } else if (buf) { - buf->ref--; - if (buf->ref == 0 && buf->size == 0) { - /* - * Current buffer is done. - * Move current reference to the next one and send - * the processed buffer to the callback function, - * then discard it. - */ - DPRINTK("IRQ: buf done\n"); - dma->curr = buf->next; - if (dma->curr == NULL) - dma->spin_ref = -dma->spin_ref; - if (dma->head == buf) - dma->head = NULL; - if (dma->callback) { - int size = buf->dma_ptr - buf->dma_start; - dma->callback(buf->id, size); - } - kfree(buf); - } - } - - process_dma(dma); -} - - -static void dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs) -{ - sa1100_dma_t *dma = (sa1100_dma_t *) dev_id; - int status = dma->regs->RdDCSR; - - DPRINTK("IRQ: b=%#x st=%#x\n", (int) dma->curr->id, status); - - if (status & (DCSR_ERROR)) { - printk(KERN_ERR "DMA on \"%s\" caused an error\n", dma->device_id); - dma->regs->ClrDCSR = DCSR_ERROR; - } - - dma->regs->ClrDCSR = status & (DCSR_DONEA | DCSR_DONEB); - if (status & DCSR_DONEA) - sa1100_dma_done (dma); - if (status & DCSR_DONEB) - sa1100_dma_done (dma); -} - - -/* - * DMA interface functions - */ - -static spinlock_t dma_list_lock; - -int sa1100_request_dma (dmach_t * channel, const char *device_id, - dma_device_t device) -{ - sa1100_dma_t *dma = NULL; - dma_regs_t *regs; - int i, err; - - *channel = -1; /* to be sure we catch the freeing of a misregistered channel */ - - err = 0; - spin_lock(&dma_list_lock); - for (i = 0; i < SA1100_DMA_CHANNELS; i++) { - if (dma_chan[i].in_use) { - if (dma_chan[i].device == device) { - err = -EBUSY; - break; - } - } else if (!dma) { - dma = &dma_chan[i]; - } - } - if (!err) { - if (dma) - dma->in_use = 1; - else - err = -ENOSR; - } - spin_unlock(&dma_list_lock); - if (err) - return err; - - err = request_irq(dma->irq, dma_irq_handler, SA_INTERRUPT, - device_id, (void *) dma); - if (err) { - printk(KERN_ERR - "%s: unable to request IRQ %d for DMA channel\n", - device_id, dma->irq); - return err; - } - - *channel = dma - dma_chan; - dma->device_id = device_id; - dma->device = device; - dma->callback = NULL; - dma->spin_size = 0; - - regs = dma->regs; - regs->ClrDCSR = - (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB | - DCSR_IE | DCSR_ERROR | DCSR_RUN); - regs->DDAR = device; - DPRINTK("requested\n"); - return 0; -} - - -int sa1100_dma_set_callback(dmach_t channel, dma_callback_t cb) -{ - sa1100_dma_t *dma = &dma_chan[channel]; - - if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use) - return -EINVAL; - - dma->callback = cb; - DPRINTK("cb = %p\n", cb); - return 0; -} - - -int sa1100_dma_set_spin(dmach_t channel, dma_addr_t addr, int size) -{ - sa1100_dma_t *dma = &dma_chan[channel]; - int flags; - - if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use) - return -EINVAL; - - DPRINTK("set spin %d at %#x\n", size, addr); - local_irq_save(flags); - dma->spin_addr = addr; - dma->spin_size = size; - if (size) - process_dma(dma); - local_irq_restore(flags); - return 0; -} - - -int sa1100_dma_queue_buffer(dmach_t channel, void *buf_id, - dma_addr_t data, int size) -{ - sa1100_dma_t *dma; - dma_buf_t *buf; - int flags; - - dma = &dma_chan[channel]; - if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use) - return -EINVAL; - - buf = kmalloc(sizeof(*buf), GFP_ATOMIC); - if (!buf) - return -ENOMEM; - - buf->next = NULL; - buf->ref = 0; - buf->dma_ptr = buf->dma_start = data; - buf->size = size; - buf->id = buf_id; - DPRINTK("queueing b=%#x a=%#x s=%d\n", (int) buf_id, data, size); - - local_irq_save(flags); - if (dma->head) - dma->head->next = buf; - dma->head = buf; - if (!dma->tail) - dma->tail = buf; - process_dma(dma); - local_irq_restore(flags); - - return 0; -} - - -int sa1100_dma_get_current(dmach_t channel, void **buf_id, dma_addr_t *addr) -{ - sa1100_dma_t *dma = &dma_chan[channel]; - dma_regs_t *regs; - int flags, ret; - - if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use) - return -EINVAL; - - if (channel_is_sa1111_sac(channel)) - return sa1111_dma_get_current(channel, buf_id, addr); - - regs = dma->regs; - local_irq_save(flags); - if (dma->curr && dma->spin_ref <= 0) { - dma_buf_t *buf = dma->curr; - int status, using_bufa; - - status = regs->RdDCSR; - /* - * If we got here, that's because there is, or recently was, a - * buffer being processed. We must determine whether buffer - * A or B is active. Two possibilities: either we are - * in the middle of a buffer, or the DMA controller just - * switched to the next toggle but the interrupt hasn't been - * serviced yet. The former case is straight forward. In - * the later case, we'll do like if DMA is just at the end - * of the previous toggle since all registers haven't been - * reset yet. This goes around the edge case and since we're - * always a little behind anyways it shouldn't make a big - * difference. If DMA has been stopped prior calling this - * then the position is always exact. - */ - using_bufa = ((!(status & DCSR_BIU) && (status & DCSR_STRTA)) || - ( (status & DCSR_BIU) && !(status & DCSR_STRTB))); - if (buf_id) - *buf_id = buf->id; - *addr = (using_bufa) ? regs->DBSA : regs->DBSB; - /* - * Clamp funky pointers sometimes returned by the hardware - * on completed DMA transfers - */ - if (*addr < buf->dma_start || - *addr > buf->dma_ptr) - *addr = buf->dma_ptr; - DPRINTK("curr_pos: b=%#x a=%#x\n", (int)dma->curr->id, *addr); - ret = 0; - } else if (dma->tail && dma->stopped) { - dma_buf_t *buf = dma->tail; - if (buf_id) - *buf_id = buf->id; - *addr = buf->dma_ptr; - ret = 0; - } else { - if (buf_id) - *buf_id = NULL; - *addr = 0; - ret = -ENXIO; - } - local_irq_restore(flags); - return ret; -} - - -int sa1100_dma_stop(dmach_t channel) -{ - sa1100_dma_t *dma = &dma_chan[channel]; - int flags; - - if (channel_is_sa1111_sac(channel)) - return sa1111_dma_stop(channel); - - if (dma->stopped) - return 0; - local_irq_save(flags); - dma->stopped = 1; - /* - * Stop DMA and tweak state variables so everything could restart - * from there when resume/wakeup occurs. - */ - dma->regs->ClrDCSR = DCSR_RUN | DCSR_IE; - if (dma->curr) { - dma_buf_t *buf = dma->curr; - if (dma->spin_ref <= 0) { - dma_addr_t curpos; - sa1100_dma_get_current(channel, NULL, &curpos); - buf->size += buf->dma_ptr - curpos; - buf->dma_ptr = curpos; - } - buf->ref = 0; - dma->tail = buf; - dma->curr = NULL; - } - dma->spin_ref = 0; - dma->regs->ClrDCSR = DCSR_STRTA|DCSR_STRTB|DCSR_DONEA|DCSR_DONEB; - process_dma(dma); - local_irq_restore(flags); - return 0; -} - - -int sa1100_dma_resume(dmach_t channel) -{ - sa1100_dma_t *dma = &dma_chan[channel]; - - if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use) - return -EINVAL; - - if (channel_is_sa1111_sac(channel)) - return sa1111_dma_resume(channel); - - if (dma->stopped) { - int flags; - save_flags_cli(flags); - dma->stopped = 0; - dma->spin_ref = 0; - process_dma(dma); - restore_flags(flags); - } - return 0; -} - - -int sa1100_dma_flush_all(dmach_t channel) -{ - sa1100_dma_t *dma = &dma_chan[channel]; - dma_buf_t *buf, *next_buf; - int flags; - - if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use) - return -EINVAL; - - local_irq_save(flags); - if (channel_is_sa1111_sac(channel)) - sa1111_reset_sac_dma(channel); - else - dma->regs->ClrDCSR = DCSR_STRTA|DCSR_STRTB|DCSR_DONEA|DCSR_DONEB|DCSR_RUN|DCSR_IE; - buf = dma->curr; - if (!buf) - buf = dma->tail; - dma->head = dma->tail = dma->curr = NULL; - dma->stopped = 0; - dma->spin_ref = 0; - process_dma(dma); - local_irq_restore(flags); - while (buf) { - next_buf = buf->next; - kfree(buf); - buf = next_buf; - } - DPRINTK("flushed\n"); - return 0; -} - - -void sa1100_free_dma(dmach_t channel) -{ - sa1100_dma_t *dma; - - if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS) - return; - - dma = &dma_chan[channel]; - if (!dma->in_use) { - printk(KERN_ERR "Trying to free free DMA%d\n", channel); - return; - } - - sa1100_dma_set_spin(channel, 0, 0); - sa1100_dma_flush_all(channel); - - if (channel_is_sa1111_sac(channel)) { - sa1111_cleanup_sac_dma(channel); - } else { - free_irq(IRQ_DMA0 + channel, (void *) dma); - } - dma->in_use = 0; - - DPRINTK("freed\n"); -} - - -EXPORT_SYMBOL(sa1100_request_dma); -EXPORT_SYMBOL(sa1100_dma_set_callback); -EXPORT_SYMBOL(sa1100_dma_set_spin); -EXPORT_SYMBOL(sa1100_dma_queue_buffer); -EXPORT_SYMBOL(sa1100_dma_get_current); -EXPORT_SYMBOL(sa1100_dma_stop); -EXPORT_SYMBOL(sa1100_dma_resume); -EXPORT_SYMBOL(sa1100_dma_flush_all); -EXPORT_SYMBOL(sa1100_free_dma); - - -#ifdef CONFIG_PM -/* Drivers should call this from their PM callback function */ - -int sa1100_dma_sleep(dmach_t channel) -{ - sa1100_dma_t *dma = &dma_chan[channel]; - int orig_state; - - if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use) - return -EINVAL; - - if (channel_is_sa1111_sac(channel)) { - /* We'll cheat a little until someone actually - * write the real thing. - */ - sa1111_reset_sac_dma(channel); - return 0; - } - - orig_state = dma->stopped; - sa1100_dma_stop(channel); - dma->regs->ClrDCSR = DCSR_RUN | DCSR_IE | DCSR_STRTA | DCSR_STRTB; - dma->stopped = orig_state; - dma->spin_ref = 0; - return 0; -} - -int sa1100_dma_wakeup(dmach_t channel) -{ - sa1100_dma_t *dma = &dma_chan[channel]; - dma_regs_t *regs; - int flags; - - if ((unsigned)channel >= MAX_SA1100_DMA_CHANNELS || !dma->in_use) - return -EINVAL; - - if (channel_is_sa1111_sac(channel)) { - /* We'll cheat a little until someone actually - * write the real thing. - */ - return 0; - } - - regs = dma->regs; - regs->ClrDCSR = - (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB | - DCSR_IE | DCSR_ERROR | DCSR_RUN); - regs->DDAR = dma->device; - local_irq_save(flags); - process_dma(dma); - local_irq_restore(flags); - return 0; -} - -EXPORT_SYMBOL(sa1100_dma_sleep); -EXPORT_SYMBOL(sa1100_dma_wakeup); - -#endif - - -static int __init sa1100_init_dma(void) -{ - int channel; - for (channel = 0; channel < SA1100_DMA_CHANNELS; channel++) { - dma_chan[channel].regs = - (dma_regs_t *) &DDAR(channel); - dma_chan[channel].irq = IRQ_DMA0 + channel; - } - return 0; -} - -__initcall(sa1100_init_dma); diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/dma-sa1111.c linux/arch/arm/mach-sa1100/dma-sa1111.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/dma-sa1111.c Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-sa1100/dma-sa1111.c Wed Dec 31 16:00:00 1969 @@ -1,363 +0,0 @@ -/* - * linux/arch/arm/mach-sa1100/dma-sa1111.c - * - * Copyright (C) 2000 John Dorsey - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * 4 September 2000 - created. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -// #define DEBUG -#ifdef DEBUG -#define DPRINTK( s, arg... ) printk( "dma<%s>: " s, dma->device_id , ##arg ) -#else -#define DPRINTK( x... ) -#endif - - -/* - * Control register structure for the SA1111 SAC DMA - */ - -typedef struct { - volatile u_long SAD_CS; - volatile dma_addr_t SAD_SA; - volatile u_long SAD_CA; - volatile dma_addr_t SAD_SB; - volatile u_long SAD_CB; -} dma_regs_t; - -#include "dma.h" - - -void sa1111_reset_sac_dma(dmach_t channel) -{ - sa1100_dma_t *dma = &dma_chan[channel]; - dma->regs->SAD_CS = 0; - mdelay(1); - dma->dma_a = dma->dma_b = 0; -} - - -int start_sa1111_sac_dma(sa1100_dma_t *dma, dma_addr_t dma_ptr, size_t size) -{ - dma_regs_t *sac_regs = dma->regs; - - DPRINTK(" SAC DMA %cCS %02x at %08x (%d)\n", - (sac_regs==&SADTCS)?'T':'R', sac_regs->SAD_CS, dma_ptr, size); - - /* The minimum transfer length requirement has not yet been - * verified: - */ - if( size < SA1111_SAC_DMA_MIN_XFER ) - printk(KERN_WARNING "Warning: SAC xfers below %u bytes may be buggy!" - " (%u bytes)\n", SA1111_SAC_DMA_MIN_XFER, size); - - if( dma->dma_a && dma->dma_b ){ - DPRINTK(" neither engine available! (A %d, B %d)\n", - dma->dma_a, dma->dma_b); - return -1; - } - - if( sa1111_check_dma_bug(dma_ptr) ) - printk(KERN_WARNING "Warning: DMA address %08x is buggy!\n", - dma_ptr); - - if( (dma->last_dma || dma->dma_b) && dma->dma_a == 0 ){ - if( sac_regs->SAD_CS & SAD_CS_DBDB ){ - DPRINTK(" awaiting \"done B\" interrupt, not starting\n"); - return -1; - } - sac_regs->SAD_SA = SA1111_DMA_ADDR((u_int)dma_ptr); - sac_regs->SAD_CA = size; - sac_regs->SAD_CS = SAD_CS_DSTA | SAD_CS_DEN; - ++dma->dma_a; - DPRINTK(" with A [%02lx %08lx %04lx]\n", sac_regs->SAD_CS, - sac_regs->SAD_SA, sac_regs->SAD_CA); - } else { - if( sac_regs->SAD_CS & SAD_CS_DBDA ){ - DPRINTK(" awaiting \"done A\" interrupt, not starting\n"); - return -1; - } - sac_regs->SAD_SB = SA1111_DMA_ADDR((u_int)dma_ptr); - sac_regs->SAD_CB = size; - sac_regs->SAD_CS = SAD_CS_DSTB | SAD_CS_DEN; - ++dma->dma_b; - DPRINTK(" with B [%02lx %08lx %04lx]\n", sac_regs->SAD_CS, - sac_regs->SAD_SB, sac_regs->SAD_CB); - } - - /* Additional delay to avoid DMA engine lockup during record: */ - if( sac_regs == (dma_regs_t*)&SADRCS ) - mdelay(1); /* NP : wouuuh! ugly... */ - - return 0; -} - - -static void sa1111_sac_dma_irq(int irq, void *dev_id, struct pt_regs *regs) -{ - sa1100_dma_t *dma = (sa1100_dma_t *) dev_id; - - DPRINTK("irq %d, last DMA serviced was %c, CS %02x\n", irq, - dma->last_dma?'B':'A', dma->regs->SAD_CS); - - /* Occasionally, one of the DMA engines (A or B) will - * lock up. We try to deal with this by quietly kicking - * the control register for the afflicted transfer - * direction. - * - * Note for the debugging-inclined: we currently aren't - * properly flushing the DMA engines during channel - * shutdown. A slight hiccup at the beginning of playback - * after a channel has been stopped can be heard as - * evidence of this. Programmatically, this shows up - * as either a locked engine, or a spurious interrupt. -jd - */ - - if(irq==AUDXMTDMADONEA || irq==AUDRCVDMADONEA){ - - if(dma->last_dma == 0){ - DPRINTK("DMA B has locked up!\n"); - dma->regs->SAD_CS = 0; - mdelay(1); - dma->dma_a = dma->dma_b = 0; - } else { - if(dma->dma_a == 0) - DPRINTK("spurious SAC IRQ %d\n", irq); - else { - --dma->dma_a; - - /* Servicing the SAC DMA engines too quickly - * after they issue a DONE interrupt causes - * them to lock up. - */ - if(irq==AUDRCVDMADONEA || irq==AUDRCVDMADONEB) - mdelay(1); - } - } - - dma->regs->SAD_CS = SAD_CS_DBDA | SAD_CS_DEN; /* w1c */ - dma->last_dma = 0; - - } else { - - if(dma->last_dma == 1){ - DPRINTK("DMA A has locked up!\n"); - dma->regs->SAD_CS = 0; - mdelay(1); - dma->dma_a = dma->dma_b = 0; - } else { - if(dma->dma_b == 0) - DPRINTK("spurious SAC IRQ %d\n", irq); - else { - --dma->dma_b; - - /* See lock-up note above. */ - if(irq==AUDRCVDMADONEA || irq==AUDRCVDMADONEB) - mdelay(1); - } - } - - dma->regs->SAD_CS = SAD_CS_DBDB | SAD_CS_DEN; /* w1c */ - dma->last_dma = 1; - - } - - /* NP: maybe this shouldn't be called in all cases? */ - sa1100_dma_done (dma); -} - - -int sa1111_sac_request_dma(dmach_t *channel, const char *device_id, - unsigned int direction) -{ - sa1100_dma_t *dma = NULL; - int ch, irq, err; - - *channel = -1; /* to be sure we catch the freeing of a misregistered channel */ - - ch = SA1111_SAC_DMA_BASE + direction; - - if (!channel_is_sa1111_sac(ch)) { - printk(KERN_ERR "%s: invalid SA-1111 SAC DMA channel (%d)\n", - device_id, ch); - return -1; - } - - dma = &dma_chan[ch]; - - if (xchg(&dma->in_use, 1) == 1) { - printk(KERN_ERR "%s: SA-1111 SAC DMA channel %d in use\n", - device_id, ch); - return -EBUSY; - } - - irq = AUDXMTDMADONEA + direction; - err = request_irq(irq, sa1111_sac_dma_irq, SA_INTERRUPT, - device_id, (void *) dma); - if (err) { - printk(KERN_ERR - "%s: unable to request IRQ %d for DMA channel %d (A)\n", - device_id, irq, ch); - dma->in_use = 0; - return err; - } - - irq = AUDXMTDMADONEB + direction; - err = request_irq(irq, sa1111_sac_dma_irq, SA_INTERRUPT, - device_id, (void *) dma); - if (err) { - printk(KERN_ERR - "%s: unable to request IRQ %d for DMA channel %d (B)\n", - device_id, irq, ch); - dma->in_use = 0; - return err; - } - - *channel = ch; - dma->device_id = device_id; - dma->callback = NULL; - dma->spin_size = 0; - - return 0; -} - - -/* FIXME: need to complete the three following functions */ - -int sa1111_dma_get_current(dmach_t channel, void **buf_id, dma_addr_t *addr) -{ - sa1100_dma_t *dma = &dma_chan[channel]; - int flags, ret; - - local_irq_save(flags); - if (dma->curr && dma->spin_ref <= 0) { - dma_buf_t *buf = dma->curr; - if (buf_id) - *buf_id = buf->id; - /* not fully accurate but still... */ - *addr = buf->dma_ptr; - ret = 0; - } else { - if (buf_id) - *buf_id = NULL; - *addr = 0; - ret = -ENXIO; - } - local_irq_restore(flags); - return ret; -} - -int sa1111_dma_stop(dmach_t channel) -{ - return 0; -} - -int sa1111_dma_resume(dmach_t channel) -{ - return 0; -} - - -void sa1111_cleanup_sac_dma(dmach_t channel) -{ - sa1100_dma_t *dma = &dma_chan[channel]; - free_irq(AUDXMTDMADONEA + (channel - SA1111_SAC_DMA_BASE), (void*) dma); - free_irq(AUDXMTDMADONEB + (channel - SA1111_SAC_DMA_BASE), (void*) dma); -} - - -/* According to the "Intel StrongARM SA-1111 Microprocessor Companion - * Chip Specification Update" (June 2000), erratum #7, there is a - * significant bug in Serial Audio Controller DMA. If the SAC is - * accessing a region of memory above 1MB relative to the bank base, - * it is important that address bit 10 _NOT_ be asserted. Depending - * on the configuration of the RAM, bit 10 may correspond to one - * of several different (processor-relative) address bits. - * - * This routine only identifies whether or not a given DMA address - * is susceptible to the bug. - */ -int sa1111_check_dma_bug(dma_addr_t addr){ - unsigned int physaddr=SA1111_DMA_ADDR((unsigned int)addr); - - /* Section 4.6 of the "Intel StrongARM SA-1111 Development Module - * User's Guide" mentions that jumpers R51 and R52 control the - * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or - * SDRAM bank 1 on Neponset). The default configuration selects - * Assabet, so any address in bank 1 is necessarily invalid. - */ - if((machine_is_assabet() || machine_is_pfs168()) && addr >= 0xc8000000) - return -1; - - /* The bug only applies to buffers located more than one megabyte - * above the start of the target bank: - */ - if(physaddr<(1<<20)) - return 0; - - switch(FExtr(SBI_SMCR, SMCR_DRAC)){ - case 01: /* 10 row + bank address bits, A<20> must not be set */ - if(physaddr & (1<<20)) - return -1; - break; - case 02: /* 11 row + bank address bits, A<23> must not be set */ - if(physaddr & (1<<23)) - return -1; - break; - case 03: /* 12 row + bank address bits, A<24> must not be set */ - if(physaddr & (1<<24)) - return -1; - break; - case 04: /* 13 row + bank address bits, A<25> must not be set */ - if(physaddr & (1<<25)) - return -1; - break; - case 05: /* 14 row + bank address bits, A<20> must not be set */ - if(physaddr & (1<<20)) - return -1; - break; - case 06: /* 15 row + bank address bits, A<20> must not be set */ - if(physaddr & (1<<20)) - return -1; - break; - default: - printk(KERN_ERR "%s(): invalid SMCR DRAC value 0%lo\n", - __FUNCTION__, FExtr(SBI_SMCR, SMCR_DRAC)); - return -1; - } - - return 0; -} - - -EXPORT_SYMBOL(sa1111_sac_request_dma); -EXPORT_SYMBOL(sa1111_check_dma_bug); - - -static int __init sa1111_init_sac_dma(void) -{ - int channel = SA1111_SAC_DMA_BASE; - dma_chan[channel++].regs = (dma_regs_t *) &SADTCS; - dma_chan[channel++].regs = (dma_regs_t *) &SADRCS; - return 0; -} - -__initcall(sa1111_init_sac_dma); diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/dma.c linux/arch/arm/mach-sa1100/dma.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/dma.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-sa1100/dma.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,343 @@ +/* + * arch/arm/kernel/dma-sa1100.c + * + * Support functions for the SA11x0 internal DMA channels. + * + * Copyright (C) 2000, 2001 by Nicolas Pitre + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + + +#undef DEBUG +#ifdef DEBUG +#define DPRINTK( s, arg... ) printk( "dma<%p>: " s, regs , ##arg ) +#else +#define DPRINTK( x... ) +#endif + + +typedef struct { + const char *device_id; /* device name */ + u_long device; /* this channel device, 0 if unused*/ + dma_callback_t callback; /* to call when DMA completes */ + void *data; /* ... with private data ptr */ +} sa1100_dma_t; + +static sa1100_dma_t dma_chan[SA1100_DMA_CHANNELS]; + +static spinlock_t dma_list_lock; + + +static void dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs) +{ + dma_regs_t *dma_regs = dev_id; + sa1100_dma_t *dma = dma_chan + (((u_int)dma_regs >> 5) & 7); + int status = dma_regs->RdDCSR; + + if (status & (DCSR_ERROR)) { + printk(KERN_CRIT "DMA on \"%s\" caused an error\n", dma->device_id); + dma_regs->ClrDCSR = DCSR_ERROR; + } + + dma_regs->ClrDCSR = status & (DCSR_DONEA | DCSR_DONEB); + if (dma->callback) { + if (status & DCSR_DONEA) + dma->callback(dma->data); + if (status & DCSR_DONEB) + dma->callback(dma->data); + } +} + + +/** + * sa1100_request_dma - allocate one of the SA11x0's DMA chanels + * @device: The SA11x0 peripheral targeted by this request + * @device_id: An ascii name for the claiming device + * @callback: Function to be called when the DMA completes + * @data: A cookie passed back to the callback function + * @dma_regs: Pointer to the location of the allocated channel's identifier + * + * This function will search for a free DMA channel and returns the + * address of the hardware registers for that channel as the channel + * identifier. This identifier is written to the location pointed by + * @dma_regs. The list of possible values for @device are listed into + * linux/include/asm-arm/arch-sa1100/dma.h as a dma_device_t enum. + * + * Note that reading from a port and writing to the same port are + * actually considered as two different streams requiring separate + * DMA registrations. + * + * The @callback function is called from interrupt context when one + * of the two possible DMA buffers in flight has terminated. That + * function has to be small and efficient while posponing more complex + * processing to a lower priority execution context. + * + * If no channels are available, or if the desired @device is already in + * use by another DMA channel, then an error code is returned. This + * function must be called before any other DMA calls. + **/ + +int sa1100_request_dma (dma_device_t device, const char *device_id, + dma_callback_t callback, void *data, + dma_regs_t **dma_regs) +{ + sa1100_dma_t *dma = NULL; + dma_regs_t *regs; + int i, err; + + *dma_regs = NULL; + + err = 0; + spin_lock(&dma_list_lock); + for (i = 0; i < SA1100_DMA_CHANNELS; i++) { + if (dma_chan[i].device == device) { + err = -EBUSY; + break; + } else if (!dma_chan[i].device && !dma) { + dma = &dma_chan[i]; + } + } + if (!err) { + if (dma) + dma->device = device; + else + err = -ENOSR; + } + spin_unlock(&dma_list_lock); + if (err) + return err; + + i = dma - dma_chan; + regs = (dma_regs_t *)&DDAR(i); + err = request_irq(IRQ_DMA0 + i, dma_irq_handler, SA_INTERRUPT, + device_id, regs); + if (err) { + printk(KERN_ERR __FUNCTION__ + "unable to request IRQ %d for %s\n", + IRQ_DMA0 + i, device_id); + dma->device = 0; + return err; + } + + *dma_regs = regs; + dma->device_id = device_id; + dma->callback = callback; + dma->data = data; + + regs->ClrDCSR = + (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB | + DCSR_IE | DCSR_ERROR | DCSR_RUN); + regs->DDAR = device; + + return 0; +} + + +/** + * sa1100_free_dma - free a SA11x0 DMA channel + * @regs: identifier for the channel to free + * + * This clears all activities on a given DMA channel and releases it + * for future requests. The @regs identifier is provided by a + * successful call to sa1100_request_dma(). + **/ + +void sa1100_free_dma(dma_regs_t *regs) +{ + int i; + + for (i = 0; i < SA1100_DMA_CHANNELS; i++) + if (regs == (dma_regs_t *)&DDAR(i)) + break; + if (i >= SA1100_DMA_CHANNELS) { + printk(KERN_ERR __FUNCTION__ ": bad DMA identifier\n"); + return; + } + + if (!dma_chan[i].device) { + printk(KERN_ERR __FUNCTION__ "Trying to free free DMA\n"); + return; + } + + regs->ClrDCSR = + (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB | + DCSR_IE | DCSR_ERROR | DCSR_RUN); + free_irq(IRQ_DMA0 + i, regs); + dma_chan[i].device = 0; +} + + +/** + * sa1100_start_dma - submit a data buffer for DMA + * @regs: identifier for the channel to use + * @dma_ptr: buffer physical (or bus) start address + * @size: buffer size + * + * This function hands the given data buffer to the hardware for DMA + * access. If another buffer is already in flight then this buffer + * will be queued so the DMA engine will switch to it automatically + * when the previous one is done. The DMA engine is actually toggling + * between two buffers so at most 2 successful calls can be made before + * one of them terminates and the callback function is called. + * + * The @regs identifier is provided by a successful call to + * sa1100_request_dma(). + * + * The @size must not be larger than %MAX_DMA_SIZE. If a given buffer + * is larger than that then it's the caller's responsibility to split + * it into smaller chunks and submit them separately. If this is the + * case then a @size of %CUT_DMA_SIZE is recommended to avoid ending + * up with too small chunks. The callback function can be used to chain + * submissions of buffer chunks. + * + * Error return values: + * %-EOVERFLOW: Given buffer size is too big. + * %-EBUSY: Both DMA buffers are already in use. + * %-EAGAIN: Both buffers were busy but one of them just completed + * but the interrupt handler has to execute first. + * + * This function returs 0 on success. + **/ + +int sa1100_start_dma(dma_regs_t *regs, dma_addr_t dma_ptr, u_int size) +{ + long flags; + u_long status; + int ret; + + if (size > MAX_DMA_SIZE) + return -EOVERFLOW; + + local_irq_save(flags); + status = regs->RdDCSR; + + /* If both DMA buffers are started, there's nothing else we can do. */ + if ((status & (DCSR_STRTA | DCSR_STRTB)) == (DCSR_STRTA | DCSR_STRTB)) { + DPRINTK("start: st %#x busy\n", status); + ret = -EBUSY; + goto out; + } + + if (((status & DCSR_BIU) && (status & DCSR_STRTB)) || + (!(status & DCSR_BIU) && !(status & DCSR_STRTA))) { + if (status & DCSR_DONEA) { + /* give a chance for the interrupt to be processed */ + ret = -EAGAIN; + goto out; + } + regs->DBSA = dma_ptr; + regs->DBTA = size; + regs->SetDCSR = DCSR_STRTA | DCSR_IE | DCSR_RUN; + DPRINTK("start a=%#x s=%d on A\n", dma_ptr, size); + } else { + if (status & DCSR_DONEB) { + /* give a chance for the interrupt to be processed */ + ret = -EAGAIN; + goto out; + } + regs->DBSB = dma_ptr; + regs->DBTB = size; + regs->SetDCSR = DCSR_STRTB | DCSR_IE | DCSR_RUN; + DPRINTK("start a=%#x s=%d on B\n", dma_ptr, size); + } + ret = 0; + +out: + local_irq_restore(flags); + return ret; +} + + +/** + * sa1100_get_dma_pos - return current DMA position + * @regs: identifier for the channel to use + * + * This function returns the current physical (or bus) address for the + * given DMA channel. If the channel is running i.e. not in a stopped + * state then the caller must disable interrupts prior calling this + * function and process the returned value before re-enabling them to + * prevent races with the completion interrupt handler and the callback + * function. The validation of the returned value is the caller's + * responsibility as well -- the hardware seems to return out of range + * values when the DMA engine completes a buffer. + * + * The @regs identifier is provided by a successful call to + * sa1100_request_dma(). + **/ + +dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs) +{ + int status; + + /* + * We must determine whether buffer A or B is active. + * Two possibilities: either we are in the middle of + * a buffer, or the DMA controller just switched to the + * next toggle but the interrupt hasn't been serviced yet. + * The former case is straight forward. In the later case, + * we'll do like if DMA is just at the end of the previous + * toggle since all registers haven't been reset yet. + * This goes around the edge case and since we're always + * a little behind anyways it shouldn't make a big difference. + * If DMA has been stopped prior calling this then the + * position is exact. + */ + status = regs->RdDCSR; + if ((!(status & DCSR_BIU) && (status & DCSR_STRTA)) || + ( (status & DCSR_BIU) && !(status & DCSR_STRTB))) + return regs->DBSA; + else + return regs->DBSB; +} + + +/** + * sa1100_reset_dma - reset a DMA channel + * @regs: identifier for the channel to use + * + * This function resets and reconfigure the given DMA channel. This is + * particularly useful after a sleep/wakeup event. + * + * The @regs identifier is provided by a successful call to + * sa1100_request_dma(). + **/ + +void sa1100_reset_dma(dma_regs_t *regs) +{ + int i; + + for (i = 0; i < SA1100_DMA_CHANNELS; i++) + if (regs == (dma_regs_t *)&DDAR(i)) + break; + if (i >= SA1100_DMA_CHANNELS) { + printk(KERN_ERR __FUNCTION__ ": bad DMA identifier\n"); + return; + } + + regs->ClrDCSR = + (DCSR_DONEA | DCSR_DONEB | DCSR_STRTA | DCSR_STRTB | + DCSR_IE | DCSR_ERROR | DCSR_RUN); + regs->DDAR = dma_chan[i].device; +} + + +EXPORT_SYMBOL(sa1100_request_dma); +EXPORT_SYMBOL(sa1100_free_dma); +EXPORT_SYMBOL(sa1100_start_dma); +EXPORT_SYMBOL(sa1100_get_dma_pos); +EXPORT_SYMBOL(sa1100_reset_dma); + diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/dma.h linux/arch/arm/mach-sa1100/dma.h --- linux-2.5.2-pre8/arch/arm/mach-sa1100/dma.h Sun Aug 12 17:36:24 2001 +++ linux/arch/arm/mach-sa1100/dma.h Wed Dec 31 16:00:00 1969 @@ -1,69 +0,0 @@ -/* - * Definitions shared between dma-sa1100.c and dma-sa1111.c - * (C) 2000 Nicolas Pitre - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include - -/* - * DMA buffer structure - */ - -typedef struct dma_buf_s { - int size; /* buffer size */ - dma_addr_t dma_start; /* starting DMA address */ - dma_addr_t dma_ptr; /* next DMA pointer to use */ - int ref; /* number of DMA references */ - void *id; /* to identify buffer from outside */ - struct dma_buf_s *next; /* next buffer to process */ -} dma_buf_t; - - -/* - * DMA channel structure. - */ - -typedef struct { - unsigned int in_use; /* Device is allocated */ - const char *device_id; /* Device name */ - dma_device_t device; /* ... to which this channel is attached */ - dma_buf_t *head; /* where to insert buffers */ - dma_buf_t *tail; /* where to remove buffers */ - dma_buf_t *curr; /* buffer currently DMA'ed */ - int stopped; /* 1 if DMA is stalled */ - dma_regs_t *regs; /* points to appropriate DMA registers */ - int irq; /* IRQ used by the channel */ - dma_callback_t callback; /* ... to call when buffers are done */ - int spin_size; /* > 0 when DMA should spin when no more buffer */ - dma_addr_t spin_addr; /* DMA address to spin onto */ - int spin_ref; /* number of spinning references */ -#ifdef CONFIG_SA1111 - int dma_a, dma_b, last_dma; /* SA-1111 specific */ -#endif -} sa1100_dma_t; - -extern sa1100_dma_t dma_chan[MAX_SA1100_DMA_CHANNELS]; - - -int start_sa1111_sac_dma(sa1100_dma_t *dma, dma_addr_t dma_ptr, size_t size); -int sa1111_dma_get_current(dmach_t channel, void **buf_id, dma_addr_t *addr); -int sa1111_dma_stop(dmach_t channel); -int sa1111_dma_resume(dmach_t channel); -void sa1111_reset_sac_dma(dmach_t channel); -void sa1111_cleanup_sac_dma(dmach_t channel); - -void sa1100_dma_done (sa1100_dma_t *dma); - - -#ifdef CONFIG_SA1111 -#define channel_is_sa1111_sac(ch) \ - ((ch) >= SA1111_SAC_DMA_BASE && \ - (ch) < SA1111_SAC_DMA_BASE + SA1111_SAC_DMA_CHANNELS) -#else -#define channel_is_sa1111_sac(ch) (0) -#endif - diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/flexanet.c linux/arch/arm/mach-sa1100/flexanet.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/flexanet.c Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/mach-sa1100/flexanet.c Sat Jan 5 14:43:15 2002 @@ -27,22 +27,142 @@ #include #include #include +#include #include "generic.h" -unsigned long BCR_value = BCR_POWERUP; -unsigned long flexanet_GUI_type = 0x0000000F; +unsigned long flexanet_BCR = FHH_BCR_POWERUP; -EXPORT_SYMBOL(BCR_value); -EXPORT_SYMBOL(flexanet_GUI_type); +EXPORT_SYMBOL(flexanet_BCR); + +/* physical addresses */ +#define _RCNR 0x90010004 +#define _GPLR 0x90040000 +#define _Ser4SSCR0 0x80070060 + +/* + * Get the modem-control register of the UARTs + * + */ +static int flexanet_get_mctrl(struct uart_port *port) +{ + int stat = 0; + unsigned long bsr; + + /* only DSR and CTS are implemented in UART1 & 3 */ + if (port->membase == (void *)&Ser1UTCR0) + { + bsr = FHH_BSR; + + if ((bsr & FHH_BSR_DSR1) != 0) + stat |= TIOCM_DSR; + if ((bsr & FHH_BSR_CTS1) != 0) + stat |= TIOCM_CTS; + } + else if (port->membase == (void *)&Ser3UTCR0) + { + bsr = FHH_BSR; + + if ((bsr & FHH_BSR_DSR3) != 0) + stat |= TIOCM_DSR; + if ((bsr & FHH_BSR_CTS3) != 0) + stat |= TIOCM_CTS; + } + + return stat; +} + +/* + * Set the modem-control register of the UARTs + * + */ +static void flexanet_set_mctrl(struct uart_port *port, u_int mctrl) +{ + unsigned long flags; + + /* only the RTS signal is implemented in UART1 & 3 */ + if (port->membase == (void *)&Ser1UTCR0) + { + local_irq_save(flags); + + if (mctrl & TIOCM_RTS) + flexanet_BCR |= FHH_BCR_RTS1; + else + flexanet_BCR &= ~FHH_BCR_RTS1; + + FHH_BCR = flexanet_BCR; + local_irq_restore(flags); + } + else if (port->membase == (void *)&Ser3UTCR0) + { + local_irq_save(flags); + + if (mctrl & TIOCM_RTS) + flexanet_BCR |= FHH_BCR_RTS3; + else + flexanet_BCR &= ~FHH_BCR_RTS3; + + FHH_BCR = flexanet_BCR; + local_irq_restore(flags); + } +} + +/* + * machine-specific serial port functions + * + * get_mctrl : set state of modem control lines + * set_mctrl : set the modem control lines + * enable_ms : enable modem-status interrupts + * pm : power-management. Turn device on/off. + * + */ +static struct sa1100_port_fns flexanet_port_fns __initdata = +{ + set_mctrl : flexanet_set_mctrl, + get_mctrl : flexanet_get_mctrl, + enable_ms : NULL, + pm : NULL, +}; + + +/* + * Initialization and serial port mapping + * + */ + +static int flexanet_serial_init(void) +{ + /* register low-level functions */ + sa1100_register_uart_fns(&flexanet_port_fns); + + /* UART port number mapping */ + sa1100_register_uart(0, 1); /* RS232 */ + sa1100_register_uart(1, 3); /* Radio */ + + /* Select UART function in Serial port 1 */ + Ser1SDCR0 |= SDCR0_UART; + + return 0; +} + + +static int __init flexanet_init(void) +{ + return 0; +} + +__initcall(flexanet_init); -static unsigned long probe_gui_board (void); static void __init fixup_flexanet(struct machine_desc *desc, struct param_struct *params, char **cmdline, struct meminfo *mi) { + int status; + unsigned long now; + + /* fixed RAM size, by now (64MB) */ SET_BANK( 0, 0xc0000000, 64*1024*1024 ); mi->nr_banks = 1; @@ -56,8 +176,10 @@ static struct map_desc flexanet_io_desc[] __initdata = { /* virtual physical length domain r w c b */ - { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */ { 0xf0000000, 0x10000000, 0x00001000, DOMAIN_IO, 1, 1, 0, 0 }, /* Board Control Register */ + { 0xf1000000, 0x18000000, 0x01000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Ethernet controller */ + { 0xD0000000, 0x40000000, 0x01000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Instrument boards */ + { 0xD8000000, 0x48000000, 0x01000000, DOMAIN_IO, 1, 1, 0, 0 }, /* External peripherals */ LAST_DESC }; @@ -65,9 +187,27 @@ { sa1100_map_io(); iotable_init(flexanet_io_desc); + flexanet_serial_init(); - sa1100_register_uart(0, 1); - Ser1SDCR0 |= SDCR0_UART; + /* wakeup source is GPIO-0 only */ + PWER = PWER_GPIO0; + + /* GPIOs set to zero during sleep */ + PGSR = 0; + + /* + * stop the 3.68 MHz oscillator and float control busses + * during sleep, since peripherals are powered off. + */ + PCFR = PCFR_OPDE | PCFR_FP | PCFR_FS; + + /* deassert the GUI reset */ + FLEXANET_BCR_set(FHH_BCR_GUI_NRST); + + /* + * Set IRQ edges + */ + set_GPIO_IRQ_edge(GPIO_GUI_IRQ, GPIO_RISING_EDGE); } @@ -78,3 +218,4 @@ MAPIO(flexanet_map_io) INITIRQ(sa1100_init_irq) MACHINE_END + diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/freebird.c linux/arch/arm/mach-sa1100/freebird.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/freebird.c Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-sa1100/freebird.c Sat Jan 5 14:43:15 2002 @@ -21,6 +21,35 @@ unsigned long BCR_value = BCR_DB1110; EXPORT_SYMBOL(BCR_value); +static void freebird_backlight_power(int on) +{ +#error FIXME + if (on) { + BCR_set(BCR_FREEBIRD_LCD_PWR | BCR_FREEBIRD_LCD_DISP); + /* Turn on backlight, Chester */ + BCR_set(BCR_FREEBIRD_LCD_BACKLIGHT); + } else { + BCR_clear(BCR_FREEBIRD_LCD_PWR | BCR_FREEBIRD_LCD_DISP + /* | BCR_FREEBIRD_LCD_BACKLIGHT */); + } +} + +static void freebird_lcd_power(int on) +{ +} + +static int __init freebird_init(void) +{ + if (machine_is_freebird()) { + sa1100fb_backlight_power = freebird_backlight_power; + sa1100fb_lcd_power = freebird_lcd_power; + + set_GPIO_IRQ_edge(GPIO_FREEBIRD_UCB1300, GPIO_RISING_EDGE); + } + return 0; +} + +__initcall(freebird_init); static void __init fixup_freebird(struct machine_desc *desc, struct param_struct *params, @@ -37,7 +66,6 @@ static struct map_desc freebird_io_desc[] __initdata = { /* virtual physical length domain r w c b */ - { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */ { 0xf0000000, 0x12000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* Board Control Register */ { 0xf2000000, 0x19000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0}, LAST_DESC diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/generic.c linux/arch/arm/mach-sa1100/generic.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/generic.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/mach-sa1100/generic.c Sat Jan 5 14:43:15 2002 @@ -53,23 +53,8 @@ 2802 /* 280.2 MHz */ }; -/* - * Return the current CPU clock frequency in units of 100kHz - */ -unsigned short get_cclk_frequency(void) -{ - return cclk_frequency_100khz[PPCR & 0xf]; -} - -EXPORT_SYMBOL(get_cclk_frequency); - #ifdef CONFIG_CPU_FREQ - -/* - * Validate the speed in khz. If we can't generate the precise - * frequency requested, round it down (to be on the safe side). - */ -unsigned int sa1100_validatespeed(unsigned int khz) +unsigned int sa11x0_freq_to_ppcr(unsigned int khz) { int i; @@ -79,35 +64,34 @@ if (cclk_frequency_100khz[i] <= khz) break; - return cclk_frequency_100khz[i] * 100; + return i; } /* - * Ok, set the CPU frequency. Since we've done the validation - * above, we can match for an exact frequency. If we don't find - * an exact match, we will to set the lowest frequency to be safe. + * Validate the speed in khz. If we can't generate the precise + * frequency requested, round it down (to be on the safe side). */ -void sa1100_setspeed(unsigned int khz) +unsigned int sa11x0_validatespeed(unsigned int khz) { - int i; - - khz /= 100; - - for (i = NR_FREQS - 1; i > 0; i--) - if (cclk_frequency_100khz[i] == khz) - break; -//printk("setting ppcr to %d\n", i); - PPCR = i; + return cclk_frequency_100khz[sa11x0_freq_to_ppcr(khz)] * 100; } -static int __init sa1100_init_clock(void) +static int __init sa11x0_init_clock(void) { - cpufreq_init(get_cclk_frequency() * 100); - cpufreq_setfunctions(sa1100_validatespeed, sa1100_setspeed); + cpufreq_init(cclk_frequency_100khz[PPCR & 0xf] * 100); return 0; } -__initcall(sa1100_init_clock); +__initcall(sa11x0_init_clock); +#else +/* + * We still need to provide this so building without cpufreq works. + */ +unsigned int cpufreq_get(int cpu) +{ + return cclk_frequency_100khz[PPCR & 0xf] * 100; +} +EXPORT_SYMBOL(cpufreq_get); #endif /* @@ -130,13 +114,19 @@ PMCR = PMCR_SF; } -static int __init sa1100_set_poweroff(void) +static int __init sa1100_init(void) { pm_power_off = sa1100_power_off; return 0; } -__initcall(sa1100_set_poweroff); +__initcall(sa1100_init); + +void (*sa1100fb_backlight_power)(int on); +void (*sa1100fb_lcd_power)(int on); + +EXPORT_SYMBOL(sa1100fb_backlight_power); +EXPORT_SYMBOL(sa1100fb_lcd_power); /* @@ -149,7 +139,9 @@ * 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.) * 0xf4000000-0xf4ffffff: SA-1111 * 0xf5000000-0xf5ffffff: reserved (used by cache flushing area) - * 0xf6000000-0xffffffff: reserved (internal SA1100 IO defined above) + * 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above) + * 0xffff0000-0xffff0fff: SA1100 exception vectors + * 0xffff2000-0xffff2fff: Minicache copy_user_page area * * Below 0xe8000000 is reserved for vm allocation. * @@ -159,8 +151,6 @@ static struct map_desc standard_io_desc[] __initdata = { /* virtual physical length domain r w c b */ - { 0xf6000000, 0x20000000, 0x01000000, DOMAIN_IO, 1, 1, 0, 0 }, /* PCMCIA0 IO */ - { 0xf7000000, 0x30000000, 0x01000000, DOMAIN_IO, 1, 1, 0, 0 }, /* PCMCIA1 IO */ { 0xf8000000, 0x80000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* PCM */ { 0xfa000000, 0x90000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SCM */ { 0xfc000000, 0xa0000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* MER */ diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/generic.h linux/arch/arm/mach-sa1100/generic.h --- linux-2.5.2-pre8/arch/arm/mach-sa1100/generic.h Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/mach-sa1100/generic.h Sat Jan 5 14:43:15 2002 @@ -12,3 +12,6 @@ mi->bank[__nr].size = (__size), \ mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27) +extern void (*sa1100fb_backlight_power)(int on); +extern void (*sa1100fb_lcd_power)(int on); + diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/graphicsclient.c linux/arch/arm/mach-sa1100/graphicsclient.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/graphicsclient.c Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-sa1100/graphicsclient.c Sat Jan 5 14:43:15 2002 @@ -113,7 +113,6 @@ irq_desc[irq].mask = ADS_mask_irq1; irq_desc[irq].unmask = ADS_unmask_irq1; } - GPDR &= ~GPIO_GPIO0; set_GPIO_IRQ_edge(GPIO_GPIO0, GPIO_FALLING_EDGE); setup_arm_irq( IRQ_GPIO0, &ADS_ext_irq ); } @@ -138,7 +137,6 @@ static struct map_desc graphicsclient_io_desc[] __initdata = { /* virtual physical length domain r w c b */ - { 0xe8000000, 0x08000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 1 */ { 0xf0000000, 0x10000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* CPLD */ { 0xf1000000, 0x18000000, 0x00400000, DOMAIN_IO, 0, 1, 0, 0 }, /* CAN */ LAST_DESC @@ -193,12 +191,8 @@ if (port->mapbase == _Ser1UTCR0) { Ser1SDCR0 |= SDCR0_UART; /* Set RTS Output */ - GPDR |= GPIO_GC_UART0_RTS; GPSR = GPIO_GC_UART0_RTS; - /* Set CTS Input */ - GPDR &= ~GPIO_GC_UART0_CTS; - gc_uart_ctrl_data[0].cts_prev_state = 0; gc_uart_ctrl_data[0].info = info; gc_uart_ctrl_data[0].port = port; @@ -210,12 +204,8 @@ } else if (port->mapbase == _Ser2UTCR0) { Ser2UTCR4 = Ser2HSCR0 = 0; /* Set RTS Output */ - GPDR |= GPIO_GC_UART1_RTS; GPSR = GPIO_GC_UART1_RTS; - /* Set CTS Input */ - GPDR &= ~GPIO_GC_UART1_RTS; - gc_uart_ctrl_data[1].cts_prev_state = 0; gc_uart_ctrl_data[1].info = info; gc_uart_ctrl_data[1].port = port; @@ -226,12 +216,8 @@ &gc_uart_ctrl_data[1]); } else if (port->mapbase == _Ser3UTCR0) { /* Set RTS Output */ - GPDR |= GPIO_GC_UART2_RTS; GPSR = GPIO_GC_UART2_RTS; - /* Set CTS Input */ - GPDR &= ~GPIO_GC_UART2_RTS; - gc_uart_ctrl_data[2].cts_prev_state = 0; gc_uart_ctrl_data[2].info = info; gc_uart_ctrl_data[2].port = port; @@ -258,9 +244,9 @@ return 0; } -static int graphicsclient_get_mctrl(struct uart_port *port) +static u_int graphicsclient_get_mctrl(struct uart_port *port) { - int result = TIOCM_CD | TIOCM_DSR; + u_int result = TIOCM_CD | TIOCM_DSR; if (port->mapbase == _Ser1UTCR0) { if (!(GPLR & GPIO_GC_UART0_CTS)) @@ -326,6 +312,8 @@ sa1100_register_uart(0, 3); sa1100_register_uart(1, 1); sa1100_register_uart(2, 2); + GPDR |= GPIO_GC_UART0_RTS | GPIO_GC_UART1_RTS | GPIO_GC_UART2_RTS; + GPDR &= ~(GPIO_GC_UART0_CTS | GPIO_GC_UART1_RTS | GPIO_GC_UART2_RTS); } MACHINE_START(GRAPHICSCLIENT, "ADS GraphicsClient") diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/graphicsmaster.c linux/arch/arm/mach-sa1100/graphicsmaster.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/graphicsmaster.c Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-sa1100/graphicsmaster.c Sat Jan 5 14:43:15 2002 @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -43,7 +44,7 @@ /* * Probe for SA1111. */ - ret = sa1111_probe(); + ret = sa1111_probe(0x18000000); if (ret < 0) return ret; @@ -174,7 +175,6 @@ irq_desc[irq].mask = ADS_mask_irq1; irq_desc[irq].unmask = ADS_unmask_irq1; } - GPDR &= ~GPIO_GPIO0; set_GPIO_IRQ_edge(GPIO_GPIO0, GPIO_FALLING_EDGE); setup_arm_irq( IRQ_GPIO0, &ADS_ext_irq ); } @@ -200,7 +200,6 @@ static struct map_desc graphicsmaster_io_desc[] __initdata = { /* virtual physical length domain r w c b */ - { 0xe8000000, 0x08000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 1 */ { 0xf0000000, 0x10000000, 0x00400000, DOMAIN_IO, 1, 1, 0, 0 }, /* CPLD */ { 0xf1000000, 0x40000000, 0x00400000, DOMAIN_IO, 1, 1, 0, 0 }, /* CAN */ { 0xf4000000, 0x18000000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* SA-1111 */ @@ -215,31 +214,22 @@ Ser1SDCR0 |= SDCR0_UART; /* Set RTS Output */ GPSR = GPIO_GPIO15; - GPDR |= GPIO_GPIO15; - /* Set CTS Input */ - GPDR &= ~GPIO_GPIO14; } else if (port->mapbase == _Ser2UTCR0) { Ser2UTCR4 = Ser2HSCR0 = 0; /* Set RTS Output */ GPSR = GPIO_GPIO17; - GPDR |= GPIO_GPIO17; - /* Set CTS Input */ - GPDR &= ~GPIO_GPIO16; } else if (port->mapbase == _Ser3UTCR0) { /* Set RTS Output */ GPSR = GPIO_GPIO19; - GPDR |= GPIO_GPIO19; - /* Set CTS Input */ - GPDR &= ~GPIO_GPIO18; } return ret; } -static int graphicsmaster_get_mctrl(struct uart_port *port) +static u_int graphicsmaster_get_mctrl(struct uart_port *port) { - int result = TIOCM_CD | TIOCM_DSR; + u_int result = TIOCM_CD | TIOCM_DSR; if (port->mapbase == _Ser1UTCR0) { if (!(GPLR & GPIO_GPIO14)) @@ -304,6 +294,10 @@ sa1100_register_uart(0, 3); sa1100_register_uart(1, 1); sa1100_register_uart(2, 2); + + /* set GPDR now */ + GPDR |= GPIO_GPIO15 | GPIO_GPIO17 | GPIO_GPIO19; + GPDR &= ~(GPIO_GPIO14 | GPIO_GPIO16 | GPIO_GPIO18); } MACHINE_START(GRAPHICSMASTER, "ADS GraphicsMaster") diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/h3600.c linux/arch/arm/mach-sa1100/h3600.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/h3600.c Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-sa1100/h3600.c Sat Jan 5 14:43:15 2002 @@ -1,5 +1,23 @@ /* - * linux/arch/arm/mach-sa1100/h3600.c + * Hardware definitions for Compaq iPAQ H3xxx Handheld Computers + * + * Copyright 2000,1 Compaq Computer Corporation. + * + * Use consistent with the GNU GPL is permitted, + * provided that this copyright notice is + * preserved in its entirety in all copies and derived works. + * + * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, + * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS + * FITNESS FOR ANY PARTICULAR PURPOSE. + * + * Author: Jamey Hicks. + * + * History: + * + * 2001-10-?? Andrew Christian Added support for iPAQ H3800 + * and abstracted EGPIO interface. + * */ #include @@ -17,84 +35,345 @@ #include #include #include +#include #include "generic.h" - /* - * Bitsy has extended, write-only memory-mapped GPIO's + * H3600 has extended, write-only memory-mapped GPIO's + * H3100 has 1/2 extended, write-only GPIO and 1/2 on + * regular GPIO lines. + * H3800 has memory-mapped GPIO through ASIC1 & 2 */ -static int h3600_egpio = EGPIO_H3600_RS232_ON; +#define H3600_EGPIO (*(volatile unsigned int *)H3600_EGPIO_VIRT) + +static unsigned int h3600_egpio; + +/************************* H3100 *************************/ + +#define H3100_DIRECT_EGPIO (GPIO_H3100_BT_ON \ + | GPIO_H3100_GPIO3 \ + | GPIO_H3100_QMUTE \ + | GPIO_H3100_LCD_3V_ON \ + | GPIO_H3100_AUD_ON \ + | GPIO_H3100_AUD_PWR_ON \ + | GPIO_H3100_IR_ON \ + | GPIO_H3100_IR_FSEL) -void init_h3600_egpio(void) +void h3100_init_egpio( void ) { -#ifdef CONFIG_IPAQ_H3100 - int h3100_controls = (GPIO_H3100_BT_ON - | GPIO_H3100_QMUTE - | GPIO_H3100_LCD_3V_ON - | GPIO_H3100_AUD_ON - | GPIO_H3100_AUD_PWR_ON - | GPIO_H3100_IR_ON - | GPIO_H3100_IR_FSEL); - GPDR |= h3100_controls; - GPCR = h3100_controls; - GAFR = GPIO_SSP_CLK; -#endif -} - -void clr_h3600_egpio(unsigned long x) -{ -#ifdef CONFIG_IPAQ_H3100 - unsigned long gpcr = 0; - if (x&EGPIO_H3600_QMUTE) - gpcr |= GPIO_H3100_QMUTE; - if (x&EGPIO_H3600_LCD_ON) - gpcr |= GPIO_H3100_LCD_3V_ON; - if (x&EGPIO_H3600_AUD_AMP_ON) - gpcr |= GPIO_H3100_AUD_ON; - if (x&EGPIO_H3600_AUD_PWR_ON) - gpcr |= GPIO_H3100_AUD_PWR_ON; - if (x&EGPIO_H3600_IR_ON) - gpcr |= GPIO_H3100_IR_ON; - if (x&EGPIO_H3600_IR_FSEL) - gpcr |= GPIO_H3100_IR_FSEL; - GPCR = gpcr; -#endif - h3600_egpio &= ~x; + GPDR |= H3100_DIRECT_EGPIO; + GPCR = H3100_DIRECT_EGPIO; /* Initially all off */ + + /* Older bootldrs put GPIO2-9 in alternate mode on the + assumption that they are used for video */ + GAFR &= ~H3100_DIRECT_EGPIO; + + h3600_egpio = EGPIO_H3600_RS232_ON; H3600_EGPIO = h3600_egpio; } -void set_h3600_egpio(unsigned long x) +void h3100_control_egpio( enum ipaq_egpio_type x, int setp ) { -#ifdef CONFIG_IPAQ_H3100 - unsigned long gpsr = 0; - if (x&EGPIO_H3600_QMUTE) - gpsr |= GPIO_H3100_QMUTE; - if (x&EGPIO_H3600_LCD_ON) - gpsr |= GPIO_H3100_LCD_3V_ON; - if (x&EGPIO_H3600_AUD_AMP_ON) - gpsr |= GPIO_H3100_AUD_ON; - if (x&EGPIO_H3600_AUD_PWR_ON) - gpsr |= GPIO_H3100_AUD_PWR_ON; - if (x&EGPIO_H3600_IR_ON) - gpsr |= GPIO_H3100_IR_ON; - if (x&EGPIO_H3600_IR_FSEL) - gpsr |= GPIO_H3100_IR_FSEL; - GPSR = gpsr; -#endif - h3600_egpio |= x; + unsigned int egpio = 0; + long gpio = 0; + unsigned long flags; + + switch (x) { + case IPAQ_EGPIO_LCD_ON: + egpio |= EGPIO_H3600_LCD_ON; + gpio |= GPIO_H3100_LCD_3V_ON; + break; + case IPAQ_EGPIO_CODEC_NRESET: + egpio |= EGPIO_H3600_CODEC_NRESET; + break; + case IPAQ_EGPIO_AUDIO_ON: + gpio |= GPIO_H3100_AUD_PWR_ON + | GPIO_H3100_AUD_ON; + break; + case IPAQ_EGPIO_QMUTE: + gpio |= GPIO_H3100_QMUTE; + break; + case IPAQ_EGPIO_OPT_NVRAM_ON: + egpio |= EGPIO_H3600_OPT_NVRAM_ON; + break; + case IPAQ_EGPIO_OPT_ON: + egpio |= EGPIO_H3600_OPT_ON; + break; + case IPAQ_EGPIO_CARD_RESET: + egpio |= EGPIO_H3600_CARD_RESET; + break; + case IPAQ_EGPIO_OPT_RESET: + egpio |= EGPIO_H3600_OPT_RESET; + break; + case IPAQ_EGPIO_IR_ON: + gpio |= GPIO_H3100_IR_ON; + break; + case IPAQ_EGPIO_IR_FSEL: + gpio |= GPIO_H3100_IR_FSEL; + break; + case IPAQ_EGPIO_RS232_ON: + egpio |= EGPIO_H3600_RS232_ON; + break; + case IPAQ_EGPIO_VPP_ON: + egpio |= EGPIO_H3600_VPP_ON; + break; + } + + local_irq_save(flags); + if ( setp ) { + h3600_egpio |= egpio; + GPSR = gpio; + } else { + h3600_egpio &= ~egpio; + GPCR = gpio; + } H3600_EGPIO = h3600_egpio; + local_irq_restore(flags); + + /* + if ( x != IPAQ_EGPIO_VPP_ON ) { + printk(__FUNCTION__ " : type=%d (%s) gpio=0x%x (0x%x) egpio=0x%x (0x%x) setp=%d\n", + x, egpio_names[x], GPLR, gpio, h3600_egpio, egpio, setp ); + } + */ +} + +unsigned long h3100_read_egpio( void ) +{ + return h3600_egpio; } -EXPORT_SYMBOL(clr_h3600_egpio); -EXPORT_SYMBOL(set_h3600_egpio); +static struct ipaq_model_ops h3100_model_ops __initdata = { + model : IPAQ_H3100, + generic_name : "3100", + initialize : h3100_init_egpio, + control : h3100_control_egpio, + read : h3100_read_egpio +}; + + +/************************* H3600 *************************/ + +void h3600_init_egpio( void ) +{ + h3600_egpio = EGPIO_H3600_RS232_ON; + H3600_EGPIO = h3600_egpio; +} + +void h3600_control_egpio( enum ipaq_egpio_type x, int setp ) +{ + unsigned int egpio = 0; + unsigned long flags; + + switch (x) { + case IPAQ_EGPIO_LCD_ON: + egpio |= EGPIO_H3600_LCD_ON | + EGPIO_H3600_LCD_PCI | + EGPIO_H3600_LCD_5V_ON | + EGPIO_H3600_LVDD_ON; + break; + case IPAQ_EGPIO_CODEC_NRESET: + egpio |= EGPIO_H3600_CODEC_NRESET; + break; + case IPAQ_EGPIO_AUDIO_ON: + egpio |= EGPIO_H3600_AUD_AMP_ON | + EGPIO_H3600_AUD_PWR_ON; + break; + case IPAQ_EGPIO_QMUTE: + egpio |= EGPIO_H3600_QMUTE; + break; + case IPAQ_EGPIO_OPT_NVRAM_ON: + egpio |= EGPIO_H3600_OPT_NVRAM_ON; + break; + case IPAQ_EGPIO_OPT_ON: + egpio |= EGPIO_H3600_OPT_ON; + break; + case IPAQ_EGPIO_CARD_RESET: + egpio |= EGPIO_H3600_CARD_RESET; + break; + case IPAQ_EGPIO_OPT_RESET: + egpio |= EGPIO_H3600_OPT_RESET; + break; + case IPAQ_EGPIO_IR_ON: + egpio |= EGPIO_H3600_IR_ON; + break; + case IPAQ_EGPIO_IR_FSEL: + egpio |= EGPIO_H3600_IR_FSEL; + break; + case IPAQ_EGPIO_RS232_ON: + egpio |= EGPIO_H3600_RS232_ON; + break; + case IPAQ_EGPIO_VPP_ON: + egpio |= EGPIO_H3600_VPP_ON; + break; + } + + local_irq_save(flags); + if ( setp ) + h3600_egpio |= egpio; + else + h3600_egpio &= ~egpio; + H3600_EGPIO = h3600_egpio; + local_irq_restore(flags); +} + +unsigned long h3600_read_egpio( void ) +{ + return h3600_egpio; +} + +static struct ipaq_model_ops h3600_model_ops __initdata = { + model : IPAQ_H3600, + generic_name : "3600", + initialize : h3600_init_egpio, + control : h3600_control_egpio, + read : h3600_read_egpio +}; + +/************************* H3800 *************************/ + +#define ASIC1_OUTPUTS 0x7fff /* First 15 bits are used */ +static unsigned int h3800_asic1_gpio; +static unsigned int h3800_asic2_gpio; + +void h3800_init_egpio(void) +{ + /* Set up ASIC #1 */ + H3800_ASIC1_GPIO_Direction = ASIC1_OUTPUTS; /* All outputs */ + H3800_ASIC1_GPIO_Mask = ASIC1_OUTPUTS; /* No interrupts */ + H3800_ASIC1_GPIO_SleepMask = ASIC1_OUTPUTS; + H3800_ASIC1_GPIO_SleepDir = ASIC1_OUTPUTS; + H3800_ASIC1_GPIO_SleepOut = GPIO_H3800_ASIC1_EAR_ON_N; + H3800_ASIC1_GPIO_BattFaultDir = ASIC1_OUTPUTS; + H3800_ASIC1_GPIO_BattFaultOut = GPIO_H3800_ASIC1_EAR_ON_N; + + h3800_asic1_gpio = GPIO_H3800_ASIC1_IR_ON_N /* TODO: Check IR level */ + | GPIO_H3800_ASIC1_RS232_ON + | GPIO_H3800_ASIC1_EAR_ON_N; + + H3800_ASIC1_GPIO_Out = h3800_asic1_gpio; + + /* Set up ASIC #2 */ + H3800_ASIC2_GPIO_Direction = GPIO_H3800_ASIC2_PEN_IRQ + | GPIO_H3800_ASIC2_SD_DETECT + | GPIO_H3800_ASIC2_EAR_IN_N + | GPIO_H3800_ASIC2_USB_DETECT_N + | GPIO_H3800_ASIC2_SD_CON_SLT; + + h3800_asic2_gpio = GPIO_H3800_ASIC2_IN_Y1_N | GPIO_H3800_ASIC2_IN_X1_N; + H3800_ASIC2_GPIO_Data = h3800_asic2_gpio; + H3800_ASIC2_GPIO_BattFaultOut = h3800_asic2_gpio; + + /* TODO : Set sleep states & battery fault states */ + + /* Clear VPP Enable */ + H3800_ASIC1_FlashWP_VPP_ON = 0; +} + +void h3800_control_egpio( enum ipaq_egpio_type x, int setp ) +{ + unsigned int set_asic1_egpio = 0; + unsigned int clear_asic1_egpio = 0; + unsigned long flags; + + switch (x) { + case IPAQ_EGPIO_LCD_ON: + set_asic1_egpio |= GPIO_H3800_ASIC1_LCD_5V_ON + | GPIO_H3800_ASIC1_LCD_ON + | GPIO_H3800_ASIC1_LCD_PCI + | GPIO_H3800_ASIC1_VGH_ON + | GPIO_H3800_ASIC1_VGL_ON; + break; + case IPAQ_EGPIO_CODEC_NRESET: + break; + case IPAQ_EGPIO_AUDIO_ON: + break; + case IPAQ_EGPIO_QMUTE: + break; + case IPAQ_EGPIO_OPT_NVRAM_ON: + break; + case IPAQ_EGPIO_OPT_ON: + break; + case IPAQ_EGPIO_CARD_RESET: + break; + case IPAQ_EGPIO_OPT_RESET: + break; + case IPAQ_EGPIO_IR_ON: + clear_asic1_egpio |= GPIO_H3800_ASIC1_IR_ON_N; /* TODO : This is backwards? */ + break; + case IPAQ_EGPIO_IR_FSEL: + break; + case IPAQ_EGPIO_RS232_ON: + set_asic1_egpio |= GPIO_H3800_ASIC1_RS232_ON; + break; + case IPAQ_EGPIO_VPP_ON: + H3800_ASIC1_FlashWP_VPP_ON = setp; + break; + } + + local_irq_save(flags); + if ( setp ) { + h3800_asic1_gpio |= set_asic1_egpio; + h3800_asic1_gpio &= ~clear_asic1_egpio; + } + else { + h3800_asic1_gpio &= ~set_asic1_egpio; + h3800_asic1_gpio |= clear_asic1_egpio; + } + H3800_ASIC1_GPIO_Out = h3800_asic1_gpio; + local_irq_restore(flags); +} + +unsigned long h3800_read_egpio( void ) +{ + return h3800_asic1_gpio | (h3800_asic2_gpio << 16); +} + +static struct ipaq_model_ops h3800_model_ops __initdata = { + model : IPAQ_H3800, + generic_name : "3800", + initialize : h3800_init_egpio, + control : h3800_control_egpio, + read : h3800_read_egpio +}; + + +static void h3600_lcd_power(int on) +{ + if (on) + set_h3600_egpio(IPAQ_EGPIO_LCD_ON); + else + clr_h3600_egpio(IPAQ_EGPIO_LCD_ON); +} + + +struct ipaq_model_ops ipaq_model_ops; +EXPORT_SYMBOL(ipaq_model_ops); + +static int __init h3600_init_model_ops(void) +{ + if (machine_is_h3xxx()) { + sa1100fb_lcd_power = h3600_lcd_power; + + if (machine_is_h3100()) { + ipaq_model_ops = h3100_model_ops; + } else if (machine_is_h3600()) { + ipaq_model_ops = h3600_model_ops; + } else if (machine_is_h3800()) { + ipaq_model_ops = h3800_model_ops; + } + init_h3600_egpio(); + } + return 0; +} + +__initcall(h3600_init_model_ops); /* - * Low-level UART features. - * - * Note that RTS, CTS and DCD are all active low. + * low-level UART features */ static void h3600_uart_set_mctrl(struct uart_port *port, u_int mctrl) @@ -107,9 +386,9 @@ } } -static int h3600_uart_get_mctrl(struct uart_port *port) +static u_int h3600_uart_get_mctrl(struct uart_port *port) { - int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; + u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; if (port->mapbase == _Ser3UTCR0) { int gplr = GPLR; @@ -126,33 +405,47 @@ { struct uart_info *info = dev_id; /* Note: should only call this if something has changed */ + spin_lock_irq(&info->lock); uart_handle_dcd_change(info, !(GPLR & GPIO_H3600_COM_DCD)); + spin_unlock_irq(&info->lock); } static void h3600_cts_intr(int irq, void *dev_id, struct pt_regs *regs) { struct uart_info *info = dev_id; /* Note: should only call this if something has changed */ + spin_lock_irq(&info->lock); uart_handle_cts_change(info, !(GPLR & GPIO_H3600_COM_CTS)); + spin_unlock_irq(&info->lock); } static void h3600_uart_pm(struct uart_port *port, u_int state, u_int oldstate) { if (port->mapbase == _Ser2UTCR0) { - if (state == 0) { - set_h3600_egpio(EGPIO_H3600_IR_ON); - } else { - clr_h3600_egpio(EGPIO_H3600_IR_ON); - } + assign_h3600_egpio( IPAQ_EGPIO_IR_ON, !state ); } else if (port->mapbase == _Ser3UTCR0) { - if (state == 0) { - set_h3600_egpio(EGPIO_H3600_RS232_ON); - } else { - clr_h3600_egpio(EGPIO_H3600_RS232_ON); - } + assign_h3600_egpio( IPAQ_EGPIO_RS232_ON, !state ); } } +/* + * Enable/Disable wake up events for this serial port. + * Obviously, we only support this on the normal COM port. + */ +static int h3600_uart_set_wake(struct uart_port *port, u_int enable) +{ + int err = -EINVAL; + + if (port->mapbase == _Ser3UTCR0) { + if (enable) + PWER |= PWER_GPIO23 | PWER_GPIO25 ; /* DCD and CTS */ + else + PWER &= ~(PWER_GPIO23 | PWER_GPIO25); /* DCD and CTS */ + err = 0; + } + return err; +} + static int h3600_uart_open(struct uart_port *port, struct uart_info *info) { int ret = 0; @@ -163,8 +456,6 @@ Ser2HSSR0 = HSSR0_EIF | HSSR0_TUR | HSSR0_RAB | HSSR0_FRE; } else if (port->mapbase == _Ser3UTCR0) { - GPDR &= ~(GPIO_H3600_COM_DCD|GPIO_H3600_COM_CTS); - GPDR |= GPIO_H3600_COM_RTS; set_GPIO_IRQ_edge(GPIO_H3600_COM_DCD|GPIO_H3600_COM_CTS, GPIO_BOTH_EDGES); @@ -193,16 +484,16 @@ set_mctrl: h3600_uart_set_mctrl, get_mctrl: h3600_uart_get_mctrl, pm: h3600_uart_pm, + set_wake: h3600_uart_set_wake, open: h3600_uart_open, close: h3600_uart_close, }; static struct map_desc h3600_io_desc[] __initdata = { - /* virtual physical length domain r w c b */ - { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */ - { 0xf0000000, 0x49000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* EGPIO 0 */ - { 0xf1000000, 0x10000000, 0x02800000, DOMAIN_IO, 1, 1, 0, 0 }, /* static memory bank 2 */ - { 0xf3800000, 0x40000000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* static memory bank 4 */ + /* virtual physical length domain r w c b */ + { H3600_EGPIO_VIRT, 0x49000000, 0x01000000, DOMAIN_IO, 1, 1, 0, 0 }, /* EGPIO 0 CS#5 */ + { H3600_BANK_2_VIRT, 0x10000000, 0x02800000, DOMAIN_IO, 1, 1, 0, 0 }, /* static memory bank 2 CS#2 */ + { H3600_BANK_4_VIRT, 0x40000000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* static memory bank 4 CS#4 */ LAST_DESC }; @@ -214,13 +505,19 @@ sa1100_register_uart_fns(&h3600_port_fns); sa1100_register_uart(0, 3); sa1100_register_uart(1, 1); /* isn't this one driven elsewhere? */ - init_h3600_egpio(); /* - * Default GPIO settings. + * Default GPIO settings. Should be set by machine */ GPCR = 0x0fffffff; - GPDR = 0x0401f3fc; +// GPDR = 0x0401f3fc; + GPDR = GPIO_H3600_COM_RTS | GPIO_H3600_L3_CLOCK | + GPIO_H3600_L3_MODE | GPIO_H3600_L3_DATA | + GPIO_H3600_CLK_SET1 | GPIO_H3600_CLK_SET0 | + GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 | + GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; + + init_h3600_egpio(); /* * Ensure those pins are outputs and driving low. @@ -230,11 +527,24 @@ /* Configure suspend conditions */ PGSR = 0; - PWER = 0x1 | (1 << 31); - PCFR = PCFR_OPDE | PCFR_FP | PCFR_FS; -} - -MACHINE_START(H3600, "Compaq iPAQ") + PWER = PWER_GPIO0 | PWER_RTC; + PCFR = PCFR_OPDE; + PSDR = 0; +} + +MACHINE_START(H3600, "Compaq iPAQ H3600") + BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000) + BOOT_PARAMS(0xc0000100) + MAPIO(h3600_map_io) + INITIRQ(sa1100_init_irq) +MACHINE_END +MACHINE_START(H3100, "Compaq iPAQ H3100") + BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000) + BOOT_PARAMS(0xc0000100) + MAPIO(h3600_map_io) + INITIRQ(sa1100_init_irq) +MACHINE_END +MACHINE_START(H3800, "Compaq iPAQ H3800") BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000) BOOT_PARAMS(0xc0000100) MAPIO(h3600_map_io) diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/huw_webpanel.c linux/arch/arm/mach-sa1100/huw_webpanel.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/huw_webpanel.c Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/mach-sa1100/huw_webpanel.c Sat Jan 5 14:43:15 2002 @@ -22,11 +22,35 @@ unsigned long BCR_value; EXPORT_SYMBOL(BCR_value); +static void huw_lcd_power(int on) +{ + if (on) + BCR_clear(BCR_TFT_NPWR); + else + BCR_set(BCR_TFT_NPWR); +} + +static void huw_backlight_power(int on) +{ +#error FIXME + if (on) { + BCR_set(BCR_CCFL_POW | BCR_PWM_BACKLIGHT); + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_task(200 * HZ / 1000); + BCR_set(BCR_TFT_ENA); + } +} -static void __init init_huw_cs3(void) +static int __init init_huw_cs3(void) { // here we can place some initcode // BCR_value = 0x1045bf70; //*((volatile unsigned long*)0xf1fffff0); + if (machine_is_huw_webpanel()) { + sa1100fb_lcd_power = huw_lcd_power; + sa1100fb_backlight_power = huw_backlight_power; + } + + return 0; } __initcall(init_huw_cs3); @@ -55,7 +79,6 @@ **/ static struct map_desc huw_webpanel_io_desc[] __initdata = { /* virtual physical length domain r w c b */ - { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0, neccessary for mtd */ { 0xf0000000, 0xc1fb8000, 0x00048000, DOMAIN_IO, 1, 1, 0, 0 }, /* Parameter */ { 0xf1000000, 0x18000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Paules CS3, write only */ LAST_DESC diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/irq.c linux/arch/arm/mach-sa1100/irq.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/irq.c Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/mach-sa1100/irq.c Sat Jan 5 14:43:15 2002 @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -37,6 +38,9 @@ void set_GPIO_IRQ_edge( int gpio_mask, int edge ) { + int flags; + + local_irq_save(flags); if (edge & GPIO_FALLING_EDGE) GPIO_IRQ_falling_edge |= gpio_mask; else @@ -45,6 +49,9 @@ GPIO_IRQ_rising_edge |= gpio_mask; else GPIO_IRQ_rising_edge &= ~gpio_mask; + GPDR &= ~gpio_mask; + GAFR &= ~gpio_mask; + restore_flags(flags); } EXPORT_SYMBOL(set_GPIO_IRQ_edge); @@ -121,7 +128,7 @@ for (i = 11; i <= 27; ++i) { if (irq & (1< #include #include +#include #include #include @@ -37,20 +38,17 @@ SKCR = JORSKCR_INIT; /* Turn on the PLL, enable Ready and enable nOE assertion from DC */ mdelay(100); - SKCR = JORSKCR_RCLK; /* turn on the RCLOCK */ - SMCR = 0x35; /* initialize the SMC (debug SA-1111 reset */ - PCCR = 0; /* initialize the S2MC (debug SA-1111 reset) */ + SBI_SKCR = JORSKCR_RCLK;/* turn on the RCLOCK */ + SBI_SMCR = 0x35; /* initialize the SMC (debug SA-1111 reset */ + PCCR = 0; /* initialize the S2MC (debug SA-1111 reset) */ /* LDD4 is speaker, LDD3 is microphone */ PPSR &= ~(PPC_LDD3 | PPC_LDD4); PPDR |= PPC_LDD3 | PPC_LDD4; /* initialize extra IRQs */ - set_GPIO_IRQ_edge(GPIO_GPIO(1), GPIO_RISING_EDGE); - sa1111_init_irq(SA1100_GPIO_TO_IRQ(1)); /* chained on GPIO 1 */ - - sa1100_register_uart(0, 3); - sa1100_register_uart(1, 1); + set_GPIO_IRQ_edge(GPIO_GPIO1, GPIO_RISING_EDGE); + sa1111_init_irq(IRQ_GPIO1)); /* chained on GPIO 1 */ return 0; } @@ -68,7 +66,6 @@ static struct map_desc jornada720_io_desc[] __initdata = { /* virtual physical length domain r w c b */ - { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */ { 0xf0000000, 0x48000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* Epson registers */ { 0xf1000000, 0x48200000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* Epson frame buffer */ { 0xf4000000, 0x40000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* SA-1111 */ @@ -79,6 +76,9 @@ { sa1100_map_io(); iotable_init(jornada720_io_desc); + + sa1100_register_uart(0, 3); + sa1100_register_uart(1, 1); } MACHINE_START(JORNADA720, "HP Jornada 720") diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/lart.c linux/arch/arm/mach-sa1100/lart.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/lart.c Sun Aug 12 17:36:24 2001 +++ linux/arch/arm/mach-sa1100/lart.c Sat Jan 5 14:43:15 2002 @@ -31,6 +31,7 @@ sa1100_register_uart(0, 3); sa1100_register_uart(1, 1); sa1100_register_uart(2, 2); + GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD); GPDR |= GPIO_UART_TXD; GPDR &= ~GPIO_UART_RXD; diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/leds-assabet.c linux/arch/arm/mach-sa1100/leds-assabet.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/leds-assabet.c Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-sa1100/leds-assabet.c Sat Jan 5 14:43:15 2002 @@ -42,6 +42,8 @@ case led_stop: led_state &= ~LED_STATE_ENABLED; + hw_led_state = ASSABET_BCR_LED_RED | ASSABET_BCR_LED_GREEN; + ASSABET_BCR_frob(ASSABET_BCR_LED_MASK, hw_led_state); break; case led_claim: @@ -107,8 +109,7 @@ } if (led_state & LED_STATE_ENABLED) - ASSABET_BCR = BCR_value = (BCR_value & ~ASSABET_BCR_LED_MASK) | - hw_led_state; + ASSABET_BCR_frob(ASSABET_BCR_LED_MASK, hw_led_state); local_irq_restore(flags); } diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/leds-flexanet.c linux/arch/arm/mach-sa1100/leds-flexanet.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/leds-flexanet.c Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/mach-sa1100/leds-flexanet.c Sat Jan 5 14:43:15 2002 @@ -35,7 +35,7 @@ switch (evt) { case led_start: /* start using LEDs and enable its hardware */ - hw_led_bcr = BCR_LED_GREEN; + hw_led_bcr = FHH_BCR_LED_GREEN; hw_led_gpio = GPIO_LED_RED; led_state = LED_STATE_ENABLED; break; @@ -71,13 +71,13 @@ case led_idle_start: /* turn off CPU load LED */ if (!(led_state & LED_STATE_CLAIMED)) - hw_led_bcr &= ~BCR_LED_GREEN; + hw_led_bcr &= ~FHH_BCR_LED_GREEN; break; case led_idle_end: /* turn on CPU load LED */ if (!(led_state & LED_STATE_CLAIMED)) - hw_led_bcr |= BCR_LED_GREEN; + hw_led_bcr |= FHH_BCR_LED_GREEN; break; #endif @@ -88,12 +88,12 @@ /* direct LED access (must be previously claimed) */ case led_green_on: if (led_state & LED_STATE_CLAIMED) - hw_led_bcr |= BCR_LED_GREEN; + hw_led_bcr |= FHH_BCR_LED_GREEN; break; case led_green_off: if (led_state & LED_STATE_CLAIMED) - hw_led_bcr &= ~BCR_LED_GREEN; + hw_led_bcr &= ~FHH_BCR_LED_GREEN; break; case led_amber_on: @@ -119,7 +119,7 @@ if (led_state & LED_STATE_ENABLED) { /* update LEDs */ - BCR = BCR_value = (BCR_value & ~BCR_LED_GREEN) | hw_led_bcr; + FHH_BCR = flexanet_BCR = (flexanet_BCR & ~FHH_BCR_LED_GREEN) | hw_led_bcr; GPSR = hw_led_gpio; GPCR = hw_led_gpio ^ GPIO_LED_RED; } diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/leds-system3.c linux/arch/arm/mach-sa1100/leds-system3.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/leds-system3.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-sa1100/leds-system3.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,49 @@ +/* + * linux/arch/arm/mach-sa1100/leds-system3.c + * + * Copyright (C) 2001 Stefan Eletzhofer + * + * Original (leds-footbridge.c) by Russell King + * + * $Id: leds-system3.c,v 1.1.6.1 2001/12/04 15:19:26 seletz Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * $Log: leds-system3.c,v $ + * Revision 1.1.6.1 2001/12/04 15:19:26 seletz + * - merged from linux_2_4_13_ac5_rmk2 + * + * Revision 1.1.4.2 2001/11/19 17:58:53 seletz + * - cleanup + * + * Revision 1.1.4.1 2001/11/16 13:49:54 seletz + * - dummy LED support for PT Digital Board + * + * Revision 1.1.2.1 2001/10/15 16:03:39 seletz + * - dummy function + * + * + */ +#include +#include + +#include +#include +#include + +#include "leds.h" + + +#define LED_STATE_ENABLED 1 +#define LED_STATE_CLAIMED 2 + +static unsigned int led_state; +static unsigned int hw_led_state; + +void system3_leds_event(led_event_t evt) +{ + + /* TODO: support LEDs */ +} diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/leds.c linux/arch/arm/mach-sa1100/leds.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/leds.c Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-sa1100/leds.c Sat Jan 5 14:43:15 2002 @@ -34,6 +34,8 @@ leds_event = graphicsmaster_leds_event; if (machine_is_adsbitsy()) leds_event = adsbitsy_leds_event; + if (machine_is_pt_system3()) + leds_event = system3_leds_event; leds_event(led_start); return 0; diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/leds.h linux/arch/arm/mach-sa1100/leds.h --- linux-2.5.2-pre8/arch/arm/mach-sa1100/leds.h Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-sa1100/leds.h Sat Jan 5 14:43:15 2002 @@ -7,3 +7,4 @@ extern void pfs168_leds_event(led_event_t evt); extern void graphicsmaster_leds_event(led_event_t evt); extern void adsbitsy_leds_event(led_event_t evt); +extern void system3_leds_event(led_event_t evt); diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/neponset.c linux/arch/arm/mach-sa1100/neponset.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/neponset.c Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-sa1100/neponset.c Sat Jan 5 14:43:15 2002 @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include @@ -16,6 +18,7 @@ #include #include #include +#include #include "sa1111.h" @@ -40,10 +43,10 @@ if (!irr) break; if( irr & IRR_ETHERNET ) - do_IRQ(NEPONSET_ETHERNET_IRQ, regs); + do_IRQ(IRQ_NEPONSET_SMC9196, regs); if( irr & IRR_USAR ) - do_IRQ(NEPONSET_USAR_IRQ, regs); + do_IRQ(IRQ_NEPONSET_USAR, regs); if( irr & IRR_SA1111 ) sa1111_IRQ_demux(irq, dev_id, regs); @@ -58,19 +61,16 @@ static void __init neponset_init_irq(void) { - int irq; - sa1111_init_irq(-1); /* SA1111 IRQ not routed to a GPIO */ /* setup extra Neponset IRQs */ - irq = NEPONSET_ETHERNET_IRQ; - irq_desc[irq].valid = 1; - irq_desc[irq].probe_ok = 1; - irq = NEPONSET_USAR_IRQ; - irq_desc[irq].valid = 1; - irq_desc[irq].probe_ok = 1; - set_GPIO_IRQ_edge(ASSABET_GPIO_NEP_IRQ, GPIO_RISING_EDGE); - setup_arm_irq(ASSABET_IRQ_GPIO_NEP_IRQ, &neponset_irq); + irq_desc[IRQ_NEPONSET_SMC9196].valid = 1; + irq_desc[IRQ_NEPONSET_SMC9196].probe_ok = 1; + irq_desc[IRQ_NEPONSET_USAR].valid = 1; + irq_desc[IRQ_NEPONSET_USAR].probe_ok = 1; + + set_GPIO_IRQ_edge(GPIO_GPIO25, GPIO_RISING_EDGE); + setup_arm_irq(IRQ_GPIO25, &neponset_irq); } static int __init neponset_init(void) @@ -102,6 +102,11 @@ } /* + * Disable GPIO 0/1 drivers so the buttons work on the module. + */ + NCR_0 |= NCR_GP01_OFF; + + /* * Neponset has SA1111 connected to CS4. We know that after * reset the chip will be configured for variable latency IO. */ @@ -110,7 +115,7 @@ /* * Probe for a SA1111. */ - ret = sa1111_probe(); + ret = sa1111_probe(0x40000000); if (ret < 0) return ret; @@ -184,7 +189,7 @@ MDM_CTL_0 = mdm_ctl0; } -static int neponset_get_mctrl(struct uart_port *port) +static u_int neponset_get_mctrl(struct uart_port *port) { u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; u_int mdm_ctl1 = MDM_CTL_1; diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/omnimeter.c linux/arch/arm/mach-sa1100/omnimeter.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/omnimeter.c Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/mach-sa1100/omnimeter.c Sat Jan 5 14:43:15 2002 @@ -15,6 +15,30 @@ #include "generic.h" +static void omnimeter_backlight_power(int on) +{ + if (on) + LEDBacklightOn(); + else + LEDBacklightOff(); +} + +static void omnimeter_lcd_power(int on) +{ + if (on) + LCDPowerOn(); +} + +static int __init omnimeter_init(void) +{ + if (machine_is_omnimeter()) { + sa1100fb_backlight_power = omnimeter_backlight_power; + sa1100fb_lcd_power = omnimeter_lcd_power; + } + return 0; +} + +__initcall(omnimeter_init); static void __init fixup_omnimeter(struct machine_desc *desc, struct param_struct *params, diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/pangolin.c linux/arch/arm/mach-sa1100/pangolin.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/pangolin.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/mach-sa1100/pangolin.c Sat Jan 5 14:43:15 2002 @@ -30,7 +30,6 @@ static struct map_desc pangolin_io_desc[] __initdata = { /* virtual physical length domain r w c b */ - { 0xe8000000, 0x00000000, 0x04000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */ { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* MQ200 */ LAST_DESC }; @@ -43,6 +42,12 @@ sa1100_register_uart(0, 1); sa1100_register_uart(1, 3); Ser1SDCR0 |= SDCR0_UART; + + /* set some GPDR bits while it's safe */ + GPDR |= GPIO_PCMCIA_RESET; +#ifndef CONFIG_SA1100_PANGOLIN_PCMCIA_IDE + GPDR |= GPIO_PCMCIA_BUS_ON; +#endif } MACHINE_START(PANGOLIN, "Dialogue-Pangolin") diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/pfs168.c linux/arch/arm/mach-sa1100/pfs168.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/pfs168.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/mach-sa1100/pfs168.c Sat Jan 5 14:43:15 2002 @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -34,7 +35,7 @@ /* * Probe for SA1111. */ - ret = sa1111_probe(); + ret = sa1111_probe(0x40000000); if (ret < 0) return ret; @@ -65,8 +66,7 @@ */ sa1110_mb_enable(); - set_GPIO_IRQ_edge(GPIO_GPIO(25), GPIO_RISING_EDGE); - sa1111_init_irq(SA1100_GPIO_TO_IRQ(25)); /* SA1111 IRQ on GPIO 25 */ + sa1111_init_irq(IRQ_GPIO25); /* SA1111 IRQ on GPIO 25 */ return 0; } @@ -84,6 +84,8 @@ */ set_GPIO_IRQ_edge(GPIO_GPIO(19), GPIO_RISING_EDGE); set_GPIO_IRQ_edge(GPIO_GPIO(20), GPIO_RISING_EDGE); + set_GPIO_IRQ_edge(GPIO_GPIO(25), GPIO_RISING_EDGE); + set_GPIO_IRQ_edge(GPIO_UCB1300_IRQ, GPIO_RISING_EDGE); } diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/pm.c linux/arch/arm/mach-sa1100/pm.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/pm.c Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-sa1100/pm.c Sat Jan 5 14:43:15 2002 @@ -19,30 +19,27 @@ * Cleaned up, pushed platform dependent stuff * in the platform specific files. */ - -/* - * Debug macros - */ -#define DEBUG 1 -#ifdef DEBUG -# define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args) -#else -# define DPRINTK(fmt, args...) -#endif - - +#include #include #include #include +#include +#include #include -#include +#include #include #include #include +#include #include "sleep.h" +/* + * Debug macros + */ +#undef DEBUG + extern void sa1100_cpu_suspend(void); extern void sa1100_cpu_resume(void); @@ -57,19 +54,16 @@ int retval; /* set up pointer to sleep parameters */ - sleep_save = kmalloc (SLEEP_SAVE_SIZE*sizeof(long), GFP_ATOMIC); + sleep_save = kmalloc(SLEEP_SAVE_SIZE*sizeof(long), GFP_ATOMIC); if (!sleep_save) return -ENOMEM; - sleep_save_p = virt_to_phys(sleep_save); - retval = pm_send_all(PM_SUSPEND, (void *)2); - if (retval) { - kfree(sleep_save); - return retval; - } + sleep_save_p = virt_to_phys(sleep_save); cli(); + leds_event(led_stop); + /* preserve current time */ RCNR = xtime.tv_sec; @@ -112,7 +106,9 @@ /* ensure not to come back here if it wasn't intended */ PSPR = 0; - DPRINTK("*** made it back from resume\n"); +#ifdef DEBUG + printk("*** made it back from resume\n"); +#endif /* restore registers */ RESTORE(GPDR); @@ -146,21 +142,61 @@ /* restore current time */ xtime.tv_sec = RCNR; + leds_event(led_start); + sti(); kfree (sleep_save); - retval = pm_send_all(PM_RESUME, (void *)0); - if (retval) - return retval; + /* + * Restore the CPU frequency settings. + */ +#ifdef CONFIG_CPU_FREQ + cpufreq_restore(); +#endif return 0; } +#ifdef CONFIG_SYSCTL +/* + * ARGH! ACPI people defined CTL_ACPI in linux/acpi.h rather than + * linux/sysctl.h. + * + * This means our interface here won't survive long - it needs a new + * interface. Quick hack to get this working - use sysctl id 9999. + */ +#warning ACPI broke the kernel, this interface needs to be fixed up. +#define CTL_ACPI 9999 +#define ACPI_S1_SLP_TYP 19 + +/* + * Send us to sleep. We must not be called from IRQ context. + */ +static int sysctl_pm_do_suspend(void) +{ + int retval; + + if (in_interrupt()) { + printk(KERN_CRIT "pm_do_suspend() called from IRQ\n"); + return -EINVAL; + } + + retval = pm_send_all(PM_SUSPEND, (void *)3); + + if (retval == 0) { + retval = __pm_do_suspend(); + + pm_send_all(PM_RESUME, (void *)0); + } + + return retval; +} + static struct ctl_table pm_table[] = { - {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, (proc_handler *)&pm_do_suspend}, + {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, (proc_handler *)&sysctl_pm_do_suspend}, {0} }; @@ -181,3 +217,4 @@ __initcall(pm_init); +#endif diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/sa1111.c linux/arch/arm/mach-sa1100/sa1111.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/sa1111.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/mach-sa1100/sa1111.c Sat Jan 5 14:43:15 2002 @@ -9,12 +9,12 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * This file contains all generic SA1111 support, except for DMA which is - * provided separately in dma-sa1111.c. + * This file contains all generic SA1111 support. * * All initialization functions provided here are intended to be called * from machine specific code with proper arguments when required. */ +#include #include #include #include @@ -22,57 +22,80 @@ #include #include #include +#include #include #include #include #include +#include + #include "sa1111.h" +struct resource sa1111_resource = { + name: "SA1111", +}; + +EXPORT_SYMBOL(sa1111_resource); + /* - * SA1111 Interrupt support + * SA1111 interrupt support */ - -void sa1111_IRQ_demux( int irq, void *dev_id, struct pt_regs *regs ) +void sa1111_IRQ_demux(int irq, void *dev_id, struct pt_regs *regs) { - int i; unsigned long stat0, stat1; - for(;;) { - stat0 = INTSTATCLR0, stat1 = INTSTATCLR1; - if( !stat0 && !stat1 ) break; - if( stat0 ) - for( i = 0; i < 32; i++ ) - if( stat0 & (1<>= 1) + if (stat0 & 1) + do_IRQ(i, regs); + + for (i = IRQ_SA1111_START + 32; stat1; i++, stat1 >>= 1) + if (stat1 & 1) + do_IRQ(i, regs); } } -static struct irqaction sa1111_irq = { - name: "SA1111", - handler: sa1111_IRQ_demux, - flags: SA_INTERRUPT -}; +#define SA1111_IRQMASK_LO(x) (1 << (x - IRQ_SA1111_START)) +#define SA1111_IRQMASK_HI(x) (1 << (x - IRQ_SA1111_START - 32)) +/* + * A note about masking IRQs: + * + * The GPIO IRQ edge detection only functions while the IRQ itself is + * enabled; edges are not detected while the IRQ is disabled. + * + * This is especially important for the PCMCIA signals, where we must + * pick up every transition. We therefore do not disable the IRQs + * while processing them. + * + * However, since we are changed to a GPIO on the host processor, + * all SA1111 IRQs will be disabled while we're processing any SA1111 + * IRQ. + * + * Note also that changing INTPOL while an IRQ is enabled will itself + * trigger an IRQ. + */ static void sa1111_mask_and_ack_lowirq(unsigned int irq) { - unsigned int mask = 1 << (irq - SA1111_IRQ(0)); + unsigned int mask = SA1111_IRQMASK_LO(irq); - // broken hardware: interrupt events are lost if they occur - // while the interrupts are disabled. //INTEN0 &= ~mask; INTSTATCLR0 = mask; } static void sa1111_mask_and_ack_highirq(unsigned int irq) { - unsigned int mask = 1 << (irq - SA1111_IRQ(32)); + unsigned int mask = SA1111_IRQMASK_HI(irq); //INTEN1 &= ~mask; INTSTATCLR1 = mask; @@ -80,27 +103,29 @@ static void sa1111_mask_lowirq(unsigned int irq) { - //INTEN0 &= ~(1 << (irq - SA1111_IRQ(0))); + INTEN0 &= ~SA1111_IRQMASK_LO(irq); } static void sa1111_mask_highirq(unsigned int irq) { - //INTEN1 &= ~(1 << (irq - SA1111_IRQ(32))); + INTEN1 &= ~SA1111_IRQMASK_HI(irq); } static void sa1111_unmask_lowirq(unsigned int irq) { - INTEN0 |= 1 << (irq - SA1111_IRQ(0)); + INTEN0 |= SA1111_IRQMASK_LO(irq); } static void sa1111_unmask_highirq(unsigned int irq) { - INTEN1 |= 1 << ((irq - SA1111_IRQ(32))); + INTEN1 |= SA1111_IRQMASK_HI(irq); } void __init sa1111_init_irq(int irq_nr) { - int irq; + int irq, ret; + + request_mem_region(_INTTEST0, 512, "irqs"); /* disable all IRQs */ INTEN0 = 0; @@ -111,21 +136,21 @@ * specifies that S0ReadyInt and S1ReadyInt should be '1'. */ INTPOL0 = 0; - INTPOL1 = 1 << (S0_READY_NINT - SA1111_IRQ(32)) | - 1 << (S1_READY_NINT - SA1111_IRQ(32)); + INTPOL1 = SA1111_IRQMASK_HI(S0_READY_NINT) | + SA1111_IRQMASK_HI(S1_READY_NINT); /* clear all IRQs */ INTSTATCLR0 = -1; INTSTATCLR1 = -1; - for (irq = SA1111_IRQ(0); irq <= SA1111_IRQ(26); irq++) { + for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 0; irq_desc[irq].mask_ack = sa1111_mask_and_ack_lowirq; irq_desc[irq].mask = sa1111_mask_lowirq; irq_desc[irq].unmask = sa1111_unmask_lowirq; } - for (irq = SA1111_IRQ(32); irq <= SA1111_IRQ(54); irq++) { + for (irq = AUDXMTDMADONEA; irq <= S1_BVD1_STSCHG; irq++) { irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 0; irq_desc[irq].mask_ack = sa1111_mask_and_ack_highirq; @@ -134,28 +159,60 @@ } /* Register SA1111 interrupt */ - if (irq_nr >= 0) - setup_arm_irq(irq_nr, &sa1111_irq); + if (irq_nr < 0) + return; + + ret = request_irq(irq_nr, sa1111_IRQ_demux, SA_INTERRUPT, + "SA1111", NULL); + if (ret < 0) + printk(KERN_ERR "SA1111: unable to claim IRQ%d: %d\n", + irq_nr, ret); } -/* - * Probe for a SA1111 chip. +/** + * sa1111_probe - probe for a single SA1111 chip. + * @phys_addr: physical address of device. + * + * Probe for a SA1111 chip. This must be called + * before any other SA1111-specific code. + * + * Returns: + * %-ENODEV device not found. + * %-EBUSY physical address already marked in-use. + * %0 successful. */ - -int __init sa1111_probe(void) +int __init sa1111_probe(unsigned long phys_addr) { - unsigned long id = SBI_SKID; + unsigned long id; int ret = -ENODEV; - if ((id & SKID_ID_MASK) == SKID_SA1111_ID) { - printk(KERN_INFO "SA-1111 Microprocessor Companion Chip: " - "silicon revision %lx, metal revision %lx\n", - (id & SKID_SIREV_MASK)>>4, (id & SKID_MTREV_MASK)); - ret = 0; - } else { + sa1111_resource.start = phys_addr; + sa1111_resource.end = phys_addr + 0x2000; + + if (request_resource(&iomem_resource, &sa1111_resource)) { + ret = -EBUSY; + goto out; + } + + /* + * Probe for the chip. Only touch the SBI registers. + */ + id = SBI_SKID; + if ((id & SKID_ID_MASK) != SKID_SA1111_ID) { printk(KERN_DEBUG "SA-1111 not detected: ID = %08lx\n", id); + ret = -ENODEV; + goto release; } + printk(KERN_INFO "SA-1111 Microprocessor Companion Chip: " + "silicon revision %lx, metal revision %lx\n", + (id & SKID_SIREV_MASK)>>4, (id & SKID_MTREV_MASK)); + + return 0; + + release: + release_resource(&sa1111_resource); + out: return ret; } @@ -175,6 +232,10 @@ */ void sa1111_wake(void) { + unsigned long flags; + + local_irq_save(flags); + /* * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: * (SA-1110 Developer's Manual, section 9.1.2.1) @@ -210,6 +271,8 @@ * Ensure all clocks are initially off. */ SKPCR = 0; + + local_irq_restore(flags); } void sa1111_doze(void) @@ -242,12 +305,17 @@ */ void __init sa1110_mb_disable(void) { + unsigned long flags; + + local_irq_save(flags); + PGSR &= ~GPIO_MBGNT; GPCR = GPIO_MBGNT; GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ); + local_irq_restore(flags); } /* @@ -256,10 +324,85 @@ */ void __init sa1110_mb_enable(void) { + unsigned long flags; + + local_irq_save(flags); + PGSR &= ~GPIO_MBGNT; GPCR = GPIO_MBGNT; GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; GAFR |= (GPIO_MBGNT | GPIO_MBREQ); TUCR |= TUCR_MR; + + local_irq_restore(flags); +} + +EXPORT_SYMBOL(sa1111_wake); +EXPORT_SYMBOL(sa1111_doze); + +/* According to the "Intel StrongARM SA-1111 Microprocessor Companion + * Chip Specification Update" (June 2000), erratum #7, there is a + * significant bug in Serial Audio Controller DMA. If the SAC is + * accessing a region of memory above 1MB relative to the bank base, + * it is important that address bit 10 _NOT_ be asserted. Depending + * on the configuration of the RAM, bit 10 may correspond to one + * of several different (processor-relative) address bits. + * + * This routine only identifies whether or not a given DMA address + * is susceptible to the bug. + */ +int sa1111_check_dma_bug(dma_addr_t addr) +{ + unsigned int physaddr=SA1111_DMA_ADDR((unsigned int)addr); + + /* Section 4.6 of the "Intel StrongARM SA-1111 Development Module + * User's Guide" mentions that jumpers R51 and R52 control the + * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or + * SDRAM bank 1 on Neponset). The default configuration selects + * Assabet, so any address in bank 1 is necessarily invalid. + */ + if ((machine_is_assabet() || machine_is_pfs168()) && addr >= 0xc8000000) + return -1; + + /* The bug only applies to buffers located more than one megabyte + * above the start of the target bank: + */ + if (physaddr<(1<<20)) + return 0; + + switch (FExtr(SBI_SMCR, SMCR_DRAC)) { + case 01: /* 10 row + bank address bits, A<20> must not be set */ + if (physaddr & (1<<20)) + return -1; + break; + case 02: /* 11 row + bank address bits, A<23> must not be set */ + if (physaddr & (1<<23)) + return -1; + break; + case 03: /* 12 row + bank address bits, A<24> must not be set */ + if (physaddr & (1<<24)) + return -1; + break; + case 04: /* 13 row + bank address bits, A<25> must not be set */ + if (physaddr & (1<<25)) + return -1; + break; + case 05: /* 14 row + bank address bits, A<20> must not be set */ + if (physaddr & (1<<20)) + return -1; + break; + case 06: /* 15 row + bank address bits, A<20> must not be set */ + if (physaddr & (1<<20)) + return -1; + break; + default: + printk(KERN_ERR "%s(): invalid SMCR DRAC value 0%lo\n", + __FUNCTION__, FExtr(SBI_SMCR, SMCR_DRAC)); + return -1; + } + + return 0; } + +EXPORT_SYMBOL(sa1111_check_dma_bug); diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/sa1111.h linux/arch/arm/mach-sa1100/sa1111.h --- linux-2.5.2-pre8/arch/arm/mach-sa1100/sa1111.h Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/mach-sa1100/sa1111.h Sat Jan 5 14:43:15 2002 @@ -11,7 +11,7 @@ /* * Probe for a SA1111 chip. */ -extern int sa1111_probe(void); +extern int sa1111_probe(unsigned long phys); /* * Wake up a SA1111 chip. @@ -30,5 +30,5 @@ extern void sa1111_init_irq(int irq_nr); -extern void sa1111_IRQ_demux( int irq, void *dev_id, struct pt_regs *regs ); +extern void sa1111_IRQ_demux(int irq, void *dev_id, struct pt_regs *regs); diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/shannon.c linux/arch/arm/mach-sa1100/shannon.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/shannon.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-sa1100/shannon.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,40 @@ +/* + * linux/arch/arm/mach-sa1100/shannon.c + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "generic.h" + + +static void __init shannon_map_io(void) +{ + sa1100_map_io(); + + sa1100_register_uart(0, 3); + sa1100_register_uart(1, 1); + Ser1SDCR0 |= SDCR0_SUS; + GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD); + GPDR |= GPIO_UART_TXD; + GPDR &= ~GPIO_UART_RXD; + PPAR |= PPAR_UPR; + + set_GPIO_IRQ_edge(SHANNON_GPIO_IRQ_CODEC); +} + +MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)") + BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000) + BOOT_PARAMS(0xc0000100) + MAPIO(shannon_map_io) + INITIRQ(sa1100_init_irq) +MACHINE_END diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/sherman.c linux/arch/arm/mach-sa1100/sherman.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/sherman.c Sun Aug 12 17:36:24 2001 +++ linux/arch/arm/mach-sa1100/sherman.c Sat Jan 5 14:43:15 2002 @@ -29,16 +29,9 @@ // setup_initrd( 0xc0400000, 8*1024*1024 ); } -static struct map_desc sherman_io_desc[] __initdata = { - /* virtual physical length domain r w c b */ - { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash*/ - LAST_DESC -}; - static void __init sherman_map_io(void) { sa1100_map_io(); - iotable_init(sherman_io_desc); sa1100_register_uart(0, 3); sa1100_register_uart(1, 1); diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/simpad.c linux/arch/arm/mach-sa1100/simpad.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/simpad.c Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-sa1100/simpad.c Sat Jan 5 14:43:15 2002 @@ -23,18 +23,6 @@ long cs3_shadow; -static int __init simpad_init(void) -{ - PSPR = 0xc0008000; - GPDR &= ~GPIO_GPIO0; - cs3_shadow = (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON | - ENABLE_5V | RESET_SIMCARD); - *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow; - return 0; -} - -__initcall(simpad_init); - long get_cs3_shadow() { return cs3_shadow; @@ -70,7 +58,6 @@ static struct map_desc simpad_io_desc[] __initdata = { /* virtual physical length domain r w c b */ - { 0xe8000000, 0x00000000, 0x02000000, DOMAIN_IO, 1, 1, 0, 0 }, { 0xf2800000, 0x4b800000, 0x00800000, DOMAIN_IO, 1, 1, 0, 0 }, /* MQ200 */ { 0xf1000000, 0x18000000, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* Paules CS3, write only */ LAST_DESC @@ -96,11 +83,17 @@ sa1100_map_io(); iotable_init(simpad_io_desc); -#ifndef CONFIG_SERIAL_SA1100_OLD + PSPR = 0xc0008000; + GPDR &= ~GPIO_GPIO0; + cs3_shadow = (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON | + ENABLE_5V | RESET_SIMCARD); + *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow; + //It is only possible to register 3 UART in serial_sa1100.c sa1100_register_uart(0, 3); sa1100_register_uart(1, 1); -#endif + + set_GPIO_IRQ_edge(GPIO_UCB1300_IRQ); } #ifdef CONFIG_PROC_FS diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/sleep.S linux/arch/arm/mach-sa1100/sleep.S --- linux-2.5.2-pre8/arch/arm/mach-sa1100/sleep.S Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-sa1100/sleep.S Sat Jan 5 14:43:15 2002 @@ -176,7 +176,7 @@ ENTRY(sa1100_cpu_resume) @ set SVC, irqs off - mov r0, #I_BIT | MODE_SVC + mov r0, #PSR_F_BIT | PSR_I_BIT | MODE_SVC msr cpsr_c, r0 @ load physical address of sleep_save diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/system3.c linux/arch/arm/mach-sa1100/system3.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/system3.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-sa1100/system3.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,479 @@ +/* + * linux/arch/arm/mach-sa1100/system3.c + * + * Copyright (C) 2001 Stefan Eletzhofer + * + * $Id: system3.c,v 1.1.6.1 2001/12/04 17:28:06 seletz Exp $ + * + * This file contains all PT Sytsem 3 tweaks. Based on original work from + * Nicolas Pitre's assabet fixes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * $Log: system3.c,v $ + * Revision 1.1.6.1 2001/12/04 17:28:06 seletz + * - merged from previous branch + * + * Revision 1.1.4.3 2001/12/04 15:16:31 seletz + * - merged from linux_2_4_13_ac5_rmk2 + * + * Revision 1.1.4.2 2001/11/19 17:18:57 seletz + * - more code cleanups + * + * Revision 1.1.4.1 2001/11/16 13:52:05 seletz + * - PT Digital Board Support Code + * + * Revision 1.1.2.2 2001/11/05 16:46:18 seletz + * - cleanups + * + * Revision 1.1.2.1 2001/10/15 16:00:43 seletz + * - first revision working with new board + * + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include + +#include "generic.h" +#include "sa1111.h" + +#define DEBUG 1 + +#ifdef DEBUG +# define DPRINTK( x, args... ) printk( "%s: line %d: "x, __FUNCTION__, __LINE__, ## args ); +#else +# define DPRINTK( x, args... ) /* nix */ +#endif + +/********************************************************************** + * prototypes + */ + +/* init funcs */ +static void __init fixup_system3(struct machine_desc *desc, + struct param_struct *params, char **cmdline, struct meminfo *mi); +static void __init get_system3_scr(void); +static int __init system3_init(void); +static void __init system3_init_irq(void); +static void __init system3_map_io(void); + +static void system3_IRQ_demux( int irq, void *dev_id, struct pt_regs *regs ); +static int system3_get_mctrl(struct uart_port *port); +static void system3_set_mctrl(struct uart_port *port, u_int mctrl); +static void system3_uart_pm(struct uart_port *port, u_int state, u_int oldstate); +static int sdram_notifier(struct notifier_block *nb, unsigned long event, void *data); + +static int system3_lcd_power(int on); +static int system3_backlight_power(int on); + +extern void convert_to_tag_list(struct param_struct *params, int mem_init); + + +/********************************************************************** + * global data + */ + +/********************************************************************** + * static data + */ + +static struct map_desc system3_io_desc[] __initdata = { + /* virtual physical length domain r w c b */ + { 0xe8000000, 0x00000000, 0x01000000, DOMAIN_IO, 1, 1, 0, 0 }, /* Flash bank 0 */ + { 0xf3000000, 0x10000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* System Registers */ + { 0xf4000000, 0x40000000, 0x00100000, DOMAIN_IO, 1, 1, 0, 0 }, /* SA-1111 */ + LAST_DESC +}; + +static struct sa1100_port_fns system3_port_fns __initdata = { + set_mctrl: system3_set_mctrl, + get_mctrl: system3_get_mctrl, + pm: system3_uart_pm, +}; + +static struct irqaction system3_irq = { + name: "PT Digital Board SA1111 IRQ", + handler: system3_IRQ_demux, + flags: SA_INTERRUPT +}; + +static struct notifier_block system3_clkchg_block = { + notifier_call: sdram_notifier, +}; + +/********************************************************************** + * Static functions + */ + +static void __init system3_map_io(void) +{ + DPRINTK( "%s\n", "START" ); + sa1100_map_io(); + iotable_init(system3_io_desc); + + sa1100_register_uart_fns(&system3_port_fns); + sa1100_register_uart(0, 1); /* com port */ + sa1100_register_uart(1, 2); + sa1100_register_uart(2, 3); /* radio module */ + + Ser1SDCR0 |= SDCR0_SUS; +} + + +/********************************************************************* + * Install IRQ handler + */ +static void system3_IRQ_demux( int irq, void *dev_id, struct pt_regs *regs ) +{ + u_char irr; + + for(;;){ + //irr = PTCPLD_REG_IRQSR & (PT_IRQ_LAN | PT_IRQ_USAR | PT_IRQ_SA1111); + irr = PT_IRQSR & (PT_IRQ_LAN | PT_IRQ_SA1111); + + irr ^= (PT_IRQ_LAN); + if (!irr) break; + + if( irr & PT_IRQ_LAN ) + do_IRQ(IRQ_SYSTEM3_SMC9196, regs); + +#if 0 + /* Highspeed Serial Bus not yet used */ + if( irr & PT_IRQ_USAR ) + do_IRQ(PT_USAR_IRQ, regs); +#endif + + if( irr & PT_IRQ_SA1111 ) + sa1111_IRQ_demux(irq, dev_id, regs); + } +} + + +static void __init system3_init_irq(void) +{ + int irq; + + DPRINTK( "%s\n", "START" ); + + /* SA1111 IRQ not routed to a GPIO. */ + sa1111_init_irq(-1); + + /* setup extra IRQs */ + irq = IRQ_SYSTEM3_SMC9196; + irq_desc[irq].valid = 1; + irq_desc[irq].probe_ok = 1; + +#if 0 + /* Highspeed Serial Bus not yet used */ + irq = PT_USAR_IRQ; + irq_desc[irq].valid = 1; + irq_desc[irq].probe_ok = 1; +#endif + + /* IRQ by CPLD */ + set_GPIO_IRQ_edge( GPIO_GPIO(25), GPIO_RISING_EDGE ); + setup_arm_irq( IRQ_GPIO25, &system3_irq ); +} + +/********************************************************************** + * On system 3 limit cpu frequency to 206 Mhz + */ +static int sdram_notifier(struct notifier_block *nb, unsigned long event, + void *data) +{ + switch (event) { + case CPUFREQ_MINMAX: + cpufreq_updateminmax(data, 147500, 206000); + break; + + } + return 0; +} + +/** + * fixup_system3 - fixup function for system 3 board + * @desc: machine description + * @param: kernel params + * @cmdline: kernel cmdline + * @mi: memory info struct + * + */ +static void __init fixup_system3(struct machine_desc *desc, + struct param_struct *params, char **cmdline, struct meminfo *mi) +{ + DPRINTK( "%s\n", "START" ); + + ROOT_DEV = MKDEV(RAMDISK_MAJOR,0); + setup_ramdisk( 1, 0, 0, 8192 ); + setup_initrd( 0xc0800000, 8*1024*1024 ); +} + + +/** + * system3_uart_pm - powermgmt callback function for system 3 UART + * @port: uart port structure + * @state: pm state + * @oldstate: old pm state + * + */ +static void system3_uart_pm(struct uart_port *port, u_int state, u_int oldstate) +{ + /* TODO: switch on/off uart in powersave mode */ +} + +/* + * Note! this can be called from IRQ context. + * FIXME: Handle PT Digital Board CTRL regs irq-safe. + * + * NB: system3 uses COM_RTS and COM_DTR for both UART1 (com port) + * and UART3 (radio module). We only handle them for UART1 here. + */ +static void system3_set_mctrl(struct uart_port *port, u_int mctrl) +{ + if (port->mapbase == _Ser1UTCR0) { + u_int set = 0, clear = 0; + + if (mctrl & TIOCM_RTS) + set |= PT_CTRL2_RS1_RTS; + else + clear |= PT_CTRL2_RS1_RTS; + + if (mctrl & TIOCM_DTR) + set |= PT_CTRL2_RS1_DTR; + else + clear |= PT_CTRL2_RS1_DTR; + + PTCTRL2_clear(clear); + PTCTRL2_set(set); + } +} + +static int system3_get_mctrl(struct uart_port *port) +{ + u_int ret = 0; + u_int irqsr = PT_IRQSR; + + /* need 2 reads to read current value */ + irqsr = PT_IRQSR; + + /* TODO: check IRQ source register for modem/com + status lines and set them correctly. */ + + ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; + + return ret; +} + +/** + * system3_lcd_backlight_on - switch system 3 lcd backlight on + * + */ +int system3_lcd_backlight_on( void ) +{ + PTCTRL0_set( PT_CTRL0_LCD_BL ); + return 0; +} + +/** + * system3_lcd_backlight_off - switch system 3 lcd backlight off + * + */ +static void system3_lcd_backlight_off(void) +{ + PTCTRL0_clear( PT_CTRL0_LCD_BL ); +} + +/** + * system3_lcd_on - switch system 3 lcd on + * + */ +static void system3_lcd_on(void) +{ + DPRINTK( "%s\n", "START" ); + PTCTRL0_set( PT_CTRL0_LCD_EN ); + + /* brightness / contrast */ + SKPCR |= SKPCR_PWMCLKEN; + PB_DDR = 0xFFFFFFFF; + SKPEN0 = 1; + SKPEN1 = 1; +} + +/** + * system3_lcd_off - switch system 3 lcd off + * + */ +static void system3_lcd_off(void) +{ + DPRINTK( "%s\n", "START" ); + PTCTRL0_clear( PT_CTRL0_LCD_EN ); + SKPEN0 = 0; + SKPEN1 = 0; + SKPCR &= ~SKPCR_PWMCLKEN; +} + +/** + * system3_lcd_contrast - set system 3 contrast + * @value: the new contrast + * + */ +static void system3_lcd_contrast(unsigned char value) +{ + DPRINTK( "value=0x%02x\n", value ); + SYS3LCDCONTR = value; +} + +/** + * system3_lcd_brightness - set system 3 brightness + * @value: the new brightness + * + */ +static void system3_lcd_brightness(unsigned char value) +{ + DPRINTK( "value=0x%02x\n", value ); + SYS3LCDBRIGHT = value; +} + +static void system3_lcd_power(int on) +{ +#error why is backlight stuff here??? + if (on) { + system3_lcd_on(); + system3_lcd_backlight_on(); + system3_lcd_contrast(0x95); + system3_lcd_brightness(240); + } else { + system3_lcd_off(); + } +} + +static void system3_backlight_power(int on) +{ + if (on) { + system3_lcd_backlight_on(); + system3_lcd_contrast(0x95); + system3_lcd_brightness(240); + } else { + system3_lcd_backlight_off(); + } +} + +static int __init system3_init(void) +{ + int ret = 0; + DPRINTK( "%s\n", "START" ); + + if ( !machine_is_pt_system3() ) { + ret = -EINVAL; + goto DONE; + } + + sa1100fb_lcd_power = system3_lcd_power; + sa1100fb_backlight_power = system3_backlight_power; + + /* init control register */ + PT_CTRL0 = PT_CTRL0_INIT; + PT_CTRL1 = 0x02; + PT_CTRL2 = 0x00; + DPRINTK( "CTRL[0]=0x%02x\n", PT_CTRL0 ); + DPRINTK( "CTRL[1]=0x%02x\n", PT_CTRL1 ); + DPRINTK( "CTRL[2]=0x%02x\n", PT_CTRL2 ); + + /* + * Ensure that the memory bus request/grant signals are setup, + * and the grant is held in its inactive state. + */ + sa1110_mb_disable(); + + /* + * Probe for a SA1111. + */ + ret = sa1111_probe(0x40000000); + if (ret < 0) { + printk( KERN_WARNING"PT Digital Board: no SA1111 found!\n" ); + goto DONE; + } + + /* + * We found it. Wake the chip up. + */ + sa1111_wake(); + + /* + * The SDRAM configuration of the SA1110 and the SA1111 must + * match. This is very important to ensure that SA1111 accesses + * don't corrupt the SDRAM. Note that this ungates the SA1111's + * MBGNT signal, so we must have called sa1110_mb_disable() + * beforehand. + */ + sa1111_configure_smc(1, + FExtr(MDCNFG, MDCNFG_SA1110_DRAC0), + FExtr(MDCNFG, MDCNFG_SA1110_TDL0)); + + /* + * We only need to turn on DCLK whenever we want to use the + * DMA. It can otherwise be held firmly in the off position. + */ + SKPCR |= SKPCR_DCLKEN; + + /* + * Enable the SA1110 memory bus request and grant signals. + */ + sa1110_mb_enable(); + + system3_init_irq(); + +#if defined( CONFIG_CPU_FREQ ) + ret = cpufreq_register_notifier(&system3_clkchg_block); + if ( ret != 0 ) { + printk( KERN_WARNING"PT Digital Board: could not register clock scale callback\n" ); + goto DONE; + } +#endif + + ret = 0; +DONE: + DPRINTK( "ret=%d\n", ret ); + return ret; +} + +/********************************************************************** + * Exported Functions + */ + +/********************************************************************** + * kernel magic macros + */ +__initcall(system3_init); + +MACHINE_START(PT_SYSTEM3, "PT System 3") + BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000) + BOOT_PARAMS(0xc0000100) + FIXUP(fixup_system3) + MAPIO(system3_map_io) + INITIRQ(sa1100_init_irq) +MACHINE_END diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/xp860.c linux/arch/arm/mach-sa1100/xp860.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/xp860.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/mach-sa1100/xp860.c Sat Jan 5 14:43:15 2002 @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -21,6 +22,7 @@ static void xp860_power_off(void) { + cli(); GPDR |= GPIO_GPIO20; GPSR = GPIO_GPIO20; mdelay(1000); @@ -40,7 +42,7 @@ /* * Probe for SA1111. */ - ret = sa1111_probe(); + ret = sa1111_probe(0x40000000); if (ret < 0) return ret; diff -urN linux-2.5.2-pre8/arch/arm/mach-sa1100/yopy.c linux/arch/arm/mach-sa1100/yopy.c --- linux-2.5.2-pre8/arch/arm/mach-sa1100/yopy.c Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/mach-sa1100/yopy.c Sat Jan 5 14:43:15 2002 @@ -52,14 +52,16 @@ static int __init yopy_hw_init(void) { - YOPY_EGPIO = yopy_egpio; + if (machine_is_yopy()) { + YOPY_EGPIO = yopy_egpio; - /* Enable Output */ - PPDR |= PPC_L_BIAS; - PSDR &= ~PPC_L_BIAS; - PPSR |= PPC_L_BIAS; + /* Enable Output */ + PPDR |= PPC_L_BIAS; + PSDR &= ~PPC_L_BIAS; + PPSR |= PPC_L_BIAS; - YOPY_EGPIO = yopy_egpio; + YOPY_EGPIO = yopy_egpio; + } return 0; } @@ -82,6 +84,8 @@ iotable_init(yopy_io_desc); sa1100_register_uart(0, 3); + + set_GPIO_IRQ_edge(GPIO_UCB1200_IRQ, GPIO_RISING_EDGE); } diff -urN linux-2.5.2-pre8/arch/arm/mach-shark/Makefile linux/arch/arm/mach-shark/Makefile --- linux-2.5.2-pre8/arch/arm/mach-shark/Makefile Thu Apr 12 12:20:31 2001 +++ linux/arch/arm/mach-shark/Makefile Sat Jan 5 14:43:15 2002 @@ -11,7 +11,7 @@ # Object file lists. -obj-y := arch.o dma.o mm.o pci.o +obj-y := core.o dma.o irq.o pci.o obj-m := obj-n := obj- := diff -urN linux-2.5.2-pre8/arch/arm/mach-shark/arch.c linux/arch/arm/mach-shark/arch.c --- linux-2.5.2-pre8/arch/arm/mach-shark/arch.c Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/mach-shark/arch.c Wed Dec 31 16:00:00 1969 @@ -1,27 +0,0 @@ -/* - * linux/arch/arm/mach-shark/arch.c - * - * Architecture specific stuff. - */ -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -extern void shark_map_io(void); -extern void genarch_init_irq(void); - -MACHINE_START(SHARK, "Shark") - MAINTAINER("Alexander Schulz") - BOOT_MEM(0x08000000, 0x40000000, 0xe0000000) - BOOT_PARAMS(0x08003000) - MAPIO(shark_map_io) - INITIRQ(genarch_init_irq) -MACHINE_END diff -urN linux-2.5.2-pre8/arch/arm/mach-shark/core.c linux/arch/arm/mach-shark/core.c --- linux-2.5.2-pre8/arch/arm/mach-shark/core.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-shark/core.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,41 @@ +/* + * linux/arch/arm/mach-shark/arch.c + * + * Architecture specific stuff. + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +extern void shark_init_irq(void); + +static struct map_desc shark_io_desc[] __initdata = { + { IO_BASE , IO_START , IO_SIZE , DOMAIN_IO, 0, 1, 0, 0 }, + LAST_DESC +}; + +static void __init shark_map_io(void) +{ + iotable_init(shark_io_desc); +} + +MACHINE_START(SHARK, "Shark") + MAINTAINER("Alexander Schulz") + BOOT_MEM(0x08000000, 0x40000000, 0xe0000000) + BOOT_PARAMS(0x08003000) + MAPIO(shark_map_io) + INITIRQ(shark_init_irq) +MACHINE_END diff -urN linux-2.5.2-pre8/arch/arm/mach-shark/irq.c linux/arch/arm/mach-shark/irq.c --- linux-2.5.2-pre8/arch/arm/mach-shark/irq.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-shark/irq.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,124 @@ +/* + * linux/arch/arm/mach-shark/irq.c + * + * by Alexander Schulz + * + * derived from linux/arch/ppc/kernel/i8259.c and: + * include/asm-arm/arch-ebsa110/irq.h + * Copyright (C) 1996-1998 Russell King + */ +#include +#include +#include + +/* + * 8259A PIC functions to handle ISA devices: + */ + +/* + * This contains the irq mask for both 8259A irq controllers, + * Let through the cascade-interrupt no. 2 (ff-(1<<2)==fb) + */ +static unsigned char cached_irq_mask[2] = { 0xfb, 0xff }; + +/* + * These have to be protected by the irq controller spinlock + * before being called. + */ +static void shark_disable_8259A_irq(unsigned int irq) +{ + unsigned int mask; + if (irq<8) { + mask = 1 << irq; + cached_irq_mask[0] |= mask; + } else { + mask = 1 << (irq-8); + cached_irq_mask[1] |= mask; + } + outb(cached_irq_mask[1],0xA1); + outb(cached_irq_mask[0],0x21); +} + +static void shark_enable_8259A_irq(unsigned int irq) +{ + unsigned int mask; + if (irq<8) { + mask = ~(1 << irq); + cached_irq_mask[0] &= mask; + } else { + mask = ~(1 << (irq-8)); + cached_irq_mask[1] &= mask; + } + outb(cached_irq_mask[1],0xA1); + outb(cached_irq_mask[0],0x21); +} + +/* + * Careful! The 8259A is a fragile beast, it pretty + * much _has_ to be done exactly like this (mask it + * first, _then_ send the EOI, and the order of EOI + * to the two 8259s is important! + */ +static void shark_mask_and_ack_8259A_irq(unsigned int irq) +{ + if (irq & 8) { + cached_irq_mask[1] |= 1 << (irq-8); + inb(0xA1); /* DUMMY */ + outb(cached_irq_mask[1],0xA1); + } else { + cached_irq_mask[0] |= 1 << irq; + outb(cached_irq_mask[0],0x21); + } +} + +static void bogus_int(int irq, void *dev_id, struct pt_regs *regs) +{ + printk("Got interrupt %i!\n",irq); +} + +static struct irqaction cascade; + +void __init shark_init_irq(void) +{ + int irq; + + for (irq = 0; irq < NR_IRQS; irq++) { + irq_desc[irq].valid = 1; + irq_desc[irq].probe_ok = 1; + irq_desc[irq].mask_ack = shark_mask_and_ack_8259A_irq; + irq_desc[irq].mask = shark_disable_8259A_irq; + irq_desc[irq].unmask = shark_enable_8259A_irq; + } + + /* The PICs are initialized to level triggered and auto eoi! + * If they are set to edge triggered they lose some IRQs, + * if they are set to manual eoi they get locked up after + * a short time + */ + + /* init master interrupt controller */ + outb(0x19, 0x20); /* Start init sequence, level triggered */ + outb(0x00, 0x21); /* Vector base */ + outb(0x04, 0x21); /* Cascade (slave) on IRQ2 */ + outb(0x03, 0x21); /* Select 8086 mode , auto eoi*/ + outb(0x0A, 0x20); + /* init slave interrupt controller */ + outb(0x19, 0xA0); /* Start init sequence, level triggered */ + outb(0x08, 0xA1); /* Vector base */ + outb(0x02, 0xA1); /* Cascade (slave) on IRQ2 */ + outb(0x03, 0xA1); /* Select 8086 mode, auto eoi */ + outb(0x0A, 0xA0); + outb(cached_irq_mask[1],0xA1); + outb(cached_irq_mask[0],0x21); + //request_region(0x20,0x2,"pic1"); + //request_region(0xA0,0x2,"pic2"); + + cascade.handler = bogus_int; + cascade.flags = 0; + cascade.mask = 0; + cascade.name = "cascade"; + cascade.next = NULL; + cascade.dev_id = NULL; + setup_arm_irq(2,&cascade); +} + diff -urN linux-2.5.2-pre8/arch/arm/mach-shark/mm.c linux/arch/arm/mach-shark/mm.c --- linux-2.5.2-pre8/arch/arm/mach-shark/mm.c Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mach-shark/mm.c Wed Dec 31 16:00:00 1969 @@ -1,28 +0,0 @@ -/* - * linux/arch/arm/mach-shark/mm.c - * - * by Alexander Schulz - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include - -#include -#include -#include - -#include - -static struct map_desc shark_io_desc[] __initdata = { - { IO_BASE , IO_START , IO_SIZE , DOMAIN_IO, 0, 1, 0, 0 }, - LAST_DESC -}; - -void __init shark_map_io(void) -{ - iotable_init(shark_io_desc); -} diff -urN linux-2.5.2-pre8/arch/arm/mach-tbox/Makefile linux/arch/arm/mach-tbox/Makefile --- linux-2.5.2-pre8/arch/arm/mach-tbox/Makefile Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-tbox/Makefile Sat Jan 5 14:43:15 2002 @@ -0,0 +1,21 @@ +# +# Makefile for the linux kernel. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). + +USE_STANDARD_AS_RULE := true + +O_TARGET := tbox.o + +# Object file lists. + +obj-y := core.o +obj-m := +obj-n := +obj- := + +export-objs := + +include $(TOPDIR)/Rules.make diff -urN linux-2.5.2-pre8/arch/arm/mach-tbox/core.c linux/arch/arm/mach-tbox/core.c --- linux-2.5.2-pre8/arch/arm/mach-tbox/core.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mach-tbox/core.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,75 @@ +/* + * linux/arch/arm/mm/mm-tbox.c + * + * Copyright (C) 1998, 1999, 2000 Phil Blundell + * Copyright (C) 1998-1999 Russell King + * + * Extra MM routines for the Tbox architecture + */ +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +extern unsigned long soft_irq_mask; + +static void tbox_mask_irq(unsigned int irq) +{ + __raw_writel(0, INTCONT + (irq << 2)); + soft_irq_mask &= ~(1<= 12 && i <= 13)) { + irq_desc[i].valid = 1; + irq_desc[i].probe_ok = 0; + irq_desc[i].mask_ack = tbox_mask_irq; + irq_desc[i].mask = tbox_mask_irq; + irq_desc[i].unmask = tbox_unmask_irq; + tbox_mask_irq(i); + } else { + irq_desc[i].valid = 0; + irq_desc[i].probe_ok = 0; + } + } +} + +static struct map_desc tbox_io_desc[] __initdata = { + /* See hardware.h for details */ + { IO_BASE, IO_START, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, + LAST_DESC +}; + +static void __init tbox_map_io(void) +{ + iotable_init(tbox_io_desc); +} + +MACHINE_START(TBOX, "unknown-TBOX") + MAINTAINER("Philip Blundell") + BOOT_MEM(0x80000000, 0x00400000, 0xe0000000) + MAPIO(tbox_map_io) + INITIRQ(tbox_init_irq) +MACHINE_END + diff -urN linux-2.5.2-pre8/arch/arm/mm/Makefile linux/arch/arm/mm/Makefile --- linux-2.5.2-pre8/arch/arm/mm/Makefile Fri Nov 9 13:58:02 2001 +++ linux/arch/arm/mm/Makefile Sat Jan 5 14:43:15 2002 @@ -13,38 +13,32 @@ # Object file lists. -obj-y := init.o +obj-y := init.o extable.o fault-common.o obj-m := obj-n := obj- := export-objs := proc-syms.o discontig.o -cpu32-y := consistent.o fault-armv.o ioremap.o mm-armv.o -cpu32-$(CONFIG_MODULES) += proc-syms.o - -obj-y += extable.o fault-common.o -obj-$(CONFIG_CPU_26) += fault-armo.o mm-armo.o small_page.o -obj-$(CONFIG_CPU_32) += $(cpu32-y) +ifeq ($(CONFIG_CPU_32),y) +obj-y += consistent.o fault-armv.o ioremap.o mm-armv.o +obj-$(CONFIG_MODULES) += proc-syms.o +endif +obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o obj-$(CONFIG_DISCONTIGMEM) += discontig.o # Select the processor-specific files p-$(CONFIG_CPU_26) += proc-arm2,3.o p-$(CONFIG_CPU_ARM610) += proc-arm6,7.o p-$(CONFIG_CPU_ARM710) += proc-arm6,7.o -p-$(CONFIG_CPU_ARM720T) += proc-arm720.o -p-$(CONFIG_CPU_ARM920T) += proc-arm920.o -p-$(CONFIG_CPU_ARM926T) += proc-arm926.o -p-$(CONFIG_CPU_ARM1020) += proc-arm1020.o -p-$(CONFIG_CPU_SA110) += proc-sa110.o -p-$(CONFIG_CPU_SA1100) += proc-sa110.o - -# Integrator follows "new style" -# Soon, others will do too, and we can get rid of this -MMMACH := mm-$(MACHINE).c -ifeq ($(MMMACH),$(wildcard $(MMMACH))) -obj-$(CONFIG_CPU_32) += $(MMMACH:.c=.o) -endif +p-$(CONFIG_CPU_ARM720T) += proc-arm720.o armv4t-late-abort.o +p-$(CONFIG_CPU_ARM920T) += proc-arm920.o armv4t-early-abort.o +p-$(CONFIG_CPU_ARM922T) += proc-arm922.o armv4t-early-abort.o +p-$(CONFIG_CPU_ARM926T) += proc-arm926.o armv5ej-early-abort.o +p-$(CONFIG_CPU_ARM1020) += proc-arm1020.o armv4t-early-abort.o +p-$(CONFIG_CPU_SA110) += proc-sa110.o armv4-early-abort.o +p-$(CONFIG_CPU_SA1100) += proc-sa110.o armv4-early-abort.o minicache.o +p-$(CONFIG_CPU_XSCALE) += proc-xscale.o armv4t-early-abort.o minicache.o obj-y += $(sort $(p-y)) diff -urN linux-2.5.2-pre8/arch/arm/mm/alignment.c linux/arch/arm/mm/alignment.c --- linux-2.5.2-pre8/arch/arm/mm/alignment.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mm/alignment.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,578 @@ +/* + * linux/arch/arm/mm/alignment.c + * + * Copyright (C) 1995 Linus Torvalds + * Modifications for ARM processor (c) 1995-2001 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* + * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998 + * /proc/sys/debug/alignment, modified and integrated into + * Linux 2.1 by Russell King + * + * Speed optimisations and better fault handling by Russell King. + * + * *** NOTE *** + * This code is not portable to processors with late data abort handling. + */ +#define CODING_BITS(i) (i & 0x0e000000) + +#define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */ +#define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */ +#define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */ +#define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */ +#define LDST_L_BIT(i) (i & (1 << 20)) /* Load */ + +#define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0) + +#define LDSTH_I_BIT(i) (i & (1 << 22)) /* half-word immed */ +#define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */ + +#define RN_BITS(i) ((i >> 16) & 15) /* Rn */ +#define RD_BITS(i) ((i >> 12) & 15) /* Rd */ +#define RM_BITS(i) (i & 15) /* Rm */ + +#define REGMASK_BITS(i) (i & 0xffff) +#define OFFSET_BITS(i) (i & 0x0fff) + +#define IS_SHIFT(i) (i & 0x0ff0) +#define SHIFT_BITS(i) ((i >> 7) & 0x1f) +#define SHIFT_TYPE(i) (i & 0x60) +#define SHIFT_LSL 0x00 +#define SHIFT_LSR 0x20 +#define SHIFT_ASR 0x40 +#define SHIFT_RORRRX 0x60 + +static unsigned long ai_user; +static unsigned long ai_sys; +static unsigned long ai_skipped; +static unsigned long ai_half; +static unsigned long ai_word; +static unsigned long ai_multi; +static int ai_usermode; + +#ifdef CONFIG_PROC_FS +static const char *usermode_action[] = { + "ignored", + "warn", + "fixup", + "fixup+warn", + "signal", + "signal+warn" +}; + +static int +proc_alignment_read(char *page, char **start, off_t off, int count, int *eof, + void *data) +{ + char *p = page; + int len; + + p += sprintf(p, "User:\t\t%lu\n", ai_user); + p += sprintf(p, "System:\t\t%lu\n", ai_sys); + p += sprintf(p, "Skipped:\t%lu\n", ai_skipped); + p += sprintf(p, "Half:\t\t%lu\n", ai_half); + p += sprintf(p, "Word:\t\t%lu\n", ai_word); + p += sprintf(p, "Multi:\t\t%lu\n", ai_multi); + p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode, + usermode_action[ai_usermode]); + + len = (p - page) - off; + if (len < 0) + len = 0; + + *eof = (len <= count) ? 1 : 0; + *start = page + off; + + return len; +} + +static int proc_alignment_write(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + int mode; + + if (count > 0) { + if (get_user(mode, buffer)) + return -EFAULT; + if (mode >= '0' && mode <= '5') + ai_usermode = mode - '0'; + } + return count; +} + +/* + * This needs to be done after sysctl_init, otherwise sys/ will be + * overwritten. Actually, this shouldn't be in sys/ at all since + * it isn't a sysctl, and it doesn't contain sysctl information. + * We now locate it in /proc/cpu/alignment instead. + */ +static int __init alignment_init(void) +{ + struct proc_dir_entry *res; + + res = proc_mkdir("cpu", NULL); + if (!res) + return -ENOMEM; + + res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, res); + if (!res) + return -ENOMEM; + + res->read_proc = proc_alignment_read; + res->write_proc = proc_alignment_write; + + return 0; +} + +__initcall(alignment_init); +#endif /* CONFIG_PROC_FS */ + +union offset_union { + unsigned long un; + signed long sn; +}; + +#define TYPE_ERROR 0 +#define TYPE_FAULT 1 +#define TYPE_LDST 2 +#define TYPE_DONE 3 + +#define get8_unaligned_check(val,addr,err) \ + __asm__( \ + "1: ldrb %1, [%2], #1\n" \ + "2:\n" \ + " .section .fixup,\"ax\"\n" \ + " .align 2\n" \ + "3: mov %0, #1\n" \ + " b 2b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .align 3\n" \ + " .long 1b, 3b\n" \ + " .previous\n" \ + : "=r" (err), "=&r" (val), "=r" (addr) \ + : "0" (err), "2" (addr)) + +#define get8t_unaligned_check(val,addr,err) \ + __asm__( \ + "1: ldrbt %1, [%2], #1\n" \ + "2:\n" \ + " .section .fixup,\"ax\"\n" \ + " .align 2\n" \ + "3: mov %0, #1\n" \ + " b 2b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .align 3\n" \ + " .long 1b, 3b\n" \ + " .previous\n" \ + : "=r" (err), "=&r" (val), "=r" (addr) \ + : "0" (err), "2" (addr)) + +#define get16_unaligned_check(val,addr) \ + do { \ + unsigned int err = 0, v, a = addr; \ + get8_unaligned_check(val,a,err); \ + get8_unaligned_check(v,a,err); \ + val |= v << 8; \ + if (err) \ + goto fault; \ + } while (0) + +#define put16_unaligned_check(val,addr) \ + do { \ + unsigned int err = 0, v = val, a = addr; \ + __asm__( \ + "1: strb %1, [%2], #1\n" \ + " mov %1, %1, lsr #8\n" \ + "2: strb %1, [%2]\n" \ + "3:\n" \ + " .section .fixup,\"ax\"\n" \ + " .align 2\n" \ + "4: mov %0, #1\n" \ + " b 3b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .align 3\n" \ + " .long 1b, 4b\n" \ + " .long 2b, 4b\n" \ + " .previous\n" \ + : "=r" (err), "=&r" (v), "=&r" (a) \ + : "0" (err), "1" (v), "2" (a)); \ + if (err) \ + goto fault; \ + } while (0) + +#define __put32_unaligned_check(ins,val,addr) \ + do { \ + unsigned int err = 0, v = val, a = addr; \ + __asm__( \ + "1: "ins" %1, [%2], #1\n" \ + " mov %1, %1, lsr #8\n" \ + "2: "ins" %1, [%2], #1\n" \ + " mov %1, %1, lsr #8\n" \ + "3: "ins" %1, [%2], #1\n" \ + " mov %1, %1, lsr #8\n" \ + "4: "ins" %1, [%2]\n" \ + "5:\n" \ + " .section .fixup,\"ax\"\n" \ + " .align 2\n" \ + "6: mov %0, #1\n" \ + " b 5b\n" \ + " .previous\n" \ + " .section __ex_table,\"a\"\n" \ + " .align 3\n" \ + " .long 1b, 6b\n" \ + " .long 2b, 6b\n" \ + " .long 3b, 6b\n" \ + " .long 4b, 6b\n" \ + " .previous\n" \ + : "=r" (err), "=&r" (v), "=&r" (a) \ + : "0" (err), "1" (v), "2" (a)); \ + if (err) \ + goto fault; \ + } while (0) + +#define get32_unaligned_check(val,addr) \ + do { \ + unsigned int err = 0, v, a = addr; \ + get8_unaligned_check(val,a,err); \ + get8_unaligned_check(v,a,err); \ + val |= v << 8; \ + get8_unaligned_check(v,a,err); \ + val |= v << 16; \ + get8_unaligned_check(v,a,err); \ + val |= v << 24; \ + if (err) \ + goto fault; \ + } while (0) + +#define put32_unaligned_check(val,addr) \ + __put32_unaligned_check("strb", val, addr) + +#define get32t_unaligned_check(val,addr) \ + do { \ + unsigned int err = 0, v, a = addr; \ + get8t_unaligned_check(val,a,err); \ + get8t_unaligned_check(v,a,err); \ + val |= v << 8; \ + get8t_unaligned_check(v,a,err); \ + val |= v << 16; \ + get8t_unaligned_check(v,a,err); \ + val |= v << 24; \ + if (err) \ + goto fault; \ + } while (0) + +#define put32t_unaligned_check(val,addr) \ + __put32_unaligned_check("strbt", val, addr) + +static void +do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset) +{ + if (!LDST_U_BIT(instr)) + offset.un = -offset.un; + + if (!LDST_P_BIT(instr)) + addr += offset.un; + + if (!LDST_P_BIT(instr) || LDST_W_BIT(instr)) + regs->uregs[RN_BITS(instr)] = addr; +} + +static int +do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs) +{ + unsigned int rd = RD_BITS(instr); + + if ((instr & 0x01f00ff0) == 0x01000090) + goto swp; + + if ((instr & 0x90) != 0x90 || (instr & 0x60) == 0) + goto bad; + + ai_half += 1; + + if (LDST_L_BIT(instr)) { + unsigned long val; + get16_unaligned_check(val, addr); + + /* signed half-word? */ + if (instr & 0x40) + val = (signed long)((signed short) val); + + regs->uregs[rd] = val; + } else + put16_unaligned_check(regs->uregs[rd], addr); + + return TYPE_LDST; + +swp: + printk(KERN_ERR "Alignment trap: not handling swp instruction\n"); +bad: + return TYPE_ERROR; + +fault: + return TYPE_FAULT; +} + +static int +do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs) +{ + unsigned int rd = RD_BITS(instr); + + ai_word += 1; + + if (!LDST_P_BIT(instr) && LDST_W_BIT(instr)) + goto trans; + + if (LDST_L_BIT(instr)) + get32_unaligned_check(regs->uregs[rd], addr); + else + put32_unaligned_check(regs->uregs[rd], addr); + return TYPE_LDST; + +trans: + if (LDST_L_BIT(instr)) + get32t_unaligned_check(regs->uregs[rd], addr); + else + put32t_unaligned_check(regs->uregs[rd], addr); + return TYPE_LDST; + +fault: + return TYPE_FAULT; +} + +/* + * LDM/STM alignment handler. + * + * There are 4 variants of this instruction: + * + * B = rn pointer before instruction, A = rn pointer after instruction + * ------ increasing address -----> + * | | r0 | r1 | ... | rx | | + * PU = 01 B A + * PU = 11 B A + * PU = 00 A B + * PU = 10 A B + */ +static int +do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs) +{ + unsigned int rd, rn, correction, nr_regs, regbits; + unsigned long eaddr, newaddr; + + if (LDM_S_BIT(instr)) + goto bad; + + correction = 4; /* processor implementation defined */ + regs->ARM_pc += correction; + + ai_multi += 1; + + /* count the number of registers in the mask to be transferred */ + nr_regs = hweight16(REGMASK_BITS(instr)) * 4; + + rn = RN_BITS(instr); + newaddr = eaddr = regs->uregs[rn]; + + if (!LDST_U_BIT(instr)) + nr_regs = -nr_regs; + newaddr += nr_regs; + if (!LDST_U_BIT(instr)) + eaddr = newaddr; + + if (LDST_P_EQ_U(instr)) /* U = P */ + eaddr += 4; + + /* + * For alignment faults on the ARM922T the MMU makes + * the FSR (and hence addr) equal to the updated base address + * of the multiple access rather than the restored value. + * Switch this messsage off if we've got a ARM922, otherwise + * [ls]dm alignment faults are noisy! + */ +#if !(defined CONFIG_CPU_ARM922T) + /* + * This is a "hint" - we already have eaddr worked out by the + * processor for us. + */ + if (addr != eaddr) { + printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, " + "addr = %08lx, eaddr = %08lx\n", + instruction_pointer(regs), instr, addr, eaddr); + show_regs(regs); + } +#endif + + for (regbits = REGMASK_BITS(instr), rd = 0; regbits; regbits >>= 1, rd += 1) + if (regbits & 1) { + if (LDST_L_BIT(instr)) + get32_unaligned_check(regs->uregs[rd], eaddr); + else + put32_unaligned_check(regs->uregs[rd], eaddr); + eaddr += 4; + } + + if (LDST_W_BIT(instr)) + regs->uregs[rn] = newaddr; + if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15))) + regs->ARM_pc -= correction; + return TYPE_DONE; + +fault: + regs->ARM_pc -= correction; + return TYPE_FAULT; + +bad: + printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n"); + return TYPE_ERROR; +} + +int do_alignment(unsigned long addr, int error_code, struct pt_regs *regs) +{ + union offset_union offset; + unsigned long instr, instrptr; + int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs); + unsigned int type; + + instrptr = instruction_pointer(regs); + instr = *(unsigned long *)instrptr; + + if (user_mode(regs)) + goto user; + + ai_sys += 1; + + fixup: + + regs->ARM_pc += 4; + + switch (CODING_BITS(instr)) { + case 0x00000000: /* ldrh or strh */ + if (LDSTH_I_BIT(instr)) + offset.un = (instr & 0xf00) >> 4 | (instr & 15); + else + offset.un = regs->uregs[RM_BITS(instr)]; + handler = do_alignment_ldrhstrh; + break; + + case 0x04000000: /* ldr or str immediate */ + offset.un = OFFSET_BITS(instr); + handler = do_alignment_ldrstr; + break; + + case 0x06000000: /* ldr or str register */ + offset.un = regs->uregs[RM_BITS(instr)]; + + if (IS_SHIFT(instr)) { + unsigned int shiftval = SHIFT_BITS(instr); + + switch(SHIFT_TYPE(instr)) { + case SHIFT_LSL: + offset.un <<= shiftval; + break; + + case SHIFT_LSR: + offset.un >>= shiftval; + break; + + case SHIFT_ASR: + offset.sn >>= shiftval; + break; + + case SHIFT_RORRRX: + if (shiftval == 0) { + offset.un >>= 1; + if (regs->ARM_cpsr & PSR_C_BIT) + offset.un |= 1 << 31; + } else + offset.un = offset.un >> shiftval | + offset.un << (32 - shiftval); + break; + } + } + handler = do_alignment_ldrstr; + break; + + case 0x08000000: /* ldm or stm */ + handler = do_alignment_ldmstm; + break; + + default: + goto bad; + } + + type = handler(addr, instr, regs); + + if (type == TYPE_ERROR || type == TYPE_FAULT) + goto bad_or_fault; + + if (type == TYPE_LDST) + do_alignment_finish_ldst(addr, instr, regs, offset); + + return 0; + +bad_or_fault: + if (type == TYPE_ERROR) + goto bad; + regs->ARM_pc -= 4; + /* + * We got a fault - fix it up, or die. + */ + do_bad_area(current, current->mm, addr, error_code, regs); + return 0; + +bad: + /* + * Oops, we didn't handle the instruction. + */ + printk(KERN_ERR "Alignment trap: not handling instruction " + "%08lx at [<%08lx>]\n", instr, instrptr); + ai_skipped += 1; + return 1; + + user: + ai_user += 1; + + if (ai_usermode & 1) + printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%08lx " + "Address=0x%08lx Code 0x%02x\n", current->comm, + current->pid, instrptr, instr, addr, error_code); + + if (ai_usermode & 2) + goto fixup; + + if (ai_usermode & 4) + force_sig(SIGBUS, current); + else + set_cr(cr_no_alignment); + + return 0; +} diff -urN linux-2.5.2-pre8/arch/arm/mm/armv4-early-abort.S linux/arch/arm/mm/armv4-early-abort.S --- linux-2.5.2-pre8/arch/arm/mm/armv4-early-abort.S Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mm/armv4-early-abort.S Sat Jan 5 14:43:15 2002 @@ -0,0 +1,29 @@ +#include +#include +/* + * Function: armv4_early_abort + * + * Params : r2 = address of aborted instruction + * : r3 = saved SPSR + * + * Returns : r0 = address of abort + * : r1 = FSR, bit 8 = write + * : r2-r8 = corrupted + * : r9 = preserved + * : sp = pointer to registers + * + * Purpose : obtain information about current aborted instruction. + * Note: we read user space. This means we might cause a data + * abort here if the I-TLB and D-TLB aren't seeing the same + * picture. Unfortunately, this does happen. We live with it. + */ + .align 5 +ENTRY(armv4_early_abort) + mrc p15, 0, r1, c5, c0, 0 @ get FSR + mrc p15, 0, r0, c6, c0, 0 @ get FAR + ldr r3, [r2] @ read aborted ARM instruction + tst r3, #1 << 20 @ L = 1 -> write? + orreq r1, r1, #1 << 8 @ yes. + mov pc, lr + + diff -urN linux-2.5.2-pre8/arch/arm/mm/armv4t-early-abort.S linux/arch/arm/mm/armv4t-early-abort.S --- linux-2.5.2-pre8/arch/arm/mm/armv4t-early-abort.S Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mm/armv4t-early-abort.S Sat Jan 5 14:43:15 2002 @@ -0,0 +1,31 @@ +#include +#include +/* + * Function: armv4t_early_abort + * + * Params : r2 = address of aborted instruction + * : r3 = saved SPSR + * + * Returns : r0 = address of abort + * : r1 = FSR, bit 8 = write + * : r2-r8 = corrupted + * : r9 = preserved + * : sp = pointer to registers + * + * Purpose : obtain information about current aborted instruction. + * Note: we read user space. This means we might cause a data + * abort here if the I-TLB and D-TLB aren't seeing the same + * picture. Unfortunately, this does happen. We live with it. + */ + .align 5 +ENTRY(armv4t_early_abort) + mrc p15, 0, r1, c5, c0, 0 @ get FSR + mrc p15, 0, r0, c6, c0, 0 @ get FAR + tst r3, #PSR_T_BIT + ldrneh r3, [r2] @ read aborted thumb instruction + ldreq r3, [r2] @ read aborted ARM instruction + bic r1, r1, #1 << 8 + movne r3, r3, lsl #(21 - 12) @ move thumb bit 11 to ARM bit 20 + tst r3, #1 << 20 @ check write + orreq r1, r1, #1 << 8 + mov pc, lr diff -urN linux-2.5.2-pre8/arch/arm/mm/armv4t-late-abort.S linux/arch/arm/mm/armv4t-late-abort.S --- linux-2.5.2-pre8/arch/arm/mm/armv4t-late-abort.S Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mm/armv4t-late-abort.S Sat Jan 5 14:43:15 2002 @@ -0,0 +1,224 @@ +#include +#include +/* + * Function: armv4t_late_abort + * + * Params : r2 = address of aborted instruction + * : r3 = saved SPSR + * + * Returns : r0 = address of abort + * : r1 = FSR, bit 8 = writing + * : r2-r8 = corrupted + * : r9 = preserved + * : sp = pointer to registers + * + * Purpose : obtain information about current aborted instruction. + * Note: we read user space. This means we might cause a data + * abort here if the I-TLB and D-TLB aren't seeing the same + * picture. Unfortunately, this does happen. We live with it. + */ +ENTRY(armv4t_late_abort) + tst r3, #PSR_T_BIT @ check for thumb mode + mrc p15, 0, r1, c5, c0, 0 @ get FSR + mrc p15, 0, r0, c6, c0, 0 @ get FAR + ldreq r8, [r2] @ read arm instruction + bne .data_thumb_abort + tst r8, #1 << 20 @ L = 1 -> write? + orreq r1, r1, #1 << 8 @ yes. + and r7, r8, #15 << 24 + add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine + nop + +/* 0 */ b .data_arm_lateldrhpost @ ldrh rd, [rn], #m/rm +/* 1 */ b .data_arm_lateldrhpre @ ldrh rd, [rn, #m/rm] +/* 2 */ b .data_unknown +/* 3 */ b .data_unknown +/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m +/* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m] +/* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm +/* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm] +/* 8 */ b .data_arm_ldmstm @ ldm*a rn, +/* 9 */ b .data_arm_ldmstm @ ldm*b rn, +/* a */ b .data_unknown +/* b */ b .data_unknown +/* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m +/* d */ mov pc, lr @ ldc rd, [rn, #m] +/* e */ b .data_unknown +/* f */ +.data_unknown: @ Part of jumptable + mov r0, r2 + mov r1, r8 + mov r2, sp + bl baddataabort + b ret_from_exception + +.data_arm_ldmstm: + tst r8, #1 << 21 @ check writeback bit + moveq pc, lr @ no writeback -> no fixup + mov r7, #0x11 + orr r7, r7, #0x1100 + and r6, r8, r7 + and r2, r8, r7, lsl #1 + add r6, r6, r2, lsr #1 + and r2, r8, r7, lsl #2 + add r6, r6, r2, lsr #2 + and r2, r8, r7, lsl #3 + add r6, r6, r2, lsr #3 + add r6, r6, r6, lsr #8 + add r6, r6, r6, lsr #4 + and r6, r6, #15 @ r7 = no. of registers to transfer. + and r5, r8, #15 << 16 @ Extract 'n' form instruction + ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' + tst r8, #1 << 23 @ Check U bit + subne r7, r7, r6, lsl #2 @ Undo increment + addeq r7, r7, r6, lsl #2 @ Undo decrement + str r7, [sp, r5, lsr #14] @ Put register 'Rn' + mov pc, lr + +.data_arm_lateldrhpre: + tst r8, #1 << 21 @ Check writeback bit + moveq pc, lr @ No writeback -> no fixup +.data_arm_lateldrhpost: + and r5, r8, #0x00f @ get Rm / low nibble of immediate value + tst r8, #1 << 22 @ if (immediate offset) + andne r6, r8, #0xf00 @ { immediate high nibble + orrne r6, r5, r6, lsr #4 @ combine nibbles } else + ldreq r6, [sp, r5, lsl #2] @ { load Rm value } +.data_arm_apply_r6_and_rn: + and r5, r8, #15 << 16 @ Extract 'n' from instruction + ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' + tst r8, #1 << 23 @ Check U bit + subne r7, r7, r6 @ Undo incrmenet + addeq r7, r7, r6 @ Undo decrement + str r7, [sp, r5, lsr #14] @ Put register 'Rn' + mov pc, lr + +.data_arm_lateldrpreconst: + tst r8, #1 << 21 @ check writeback bit + moveq pc, lr @ no writeback -> no fixup +.data_arm_lateldrpostconst: + movs r2, r8, lsl #20 @ Get offset + moveq pc, lr @ zero -> no fixup + and r5, r8, #15 << 16 @ Extract 'n' from instruction + ldr r7, [sp, r5, lsr #14] @ Get register 'Rn' + tst r8, #1 << 23 @ Check U bit + subne r7, r7, r2, lsr #20 @ Undo increment + addeq r7, r7, r2, lsr #20 @ Undo decrement + str r7, [sp, r5, lsr #14] @ Put register 'Rn' + mov pc, lr + +.data_arm_lateldrprereg: + tst r8, #1 << 21 @ check writeback bit + moveq pc, lr @ no writeback -> no fixup +.data_arm_lateldrpostreg: + and r7, r8, #15 @ Extract 'm' from instruction + ldr r6, [sp, r7, lsl #2] @ Get register 'Rm' + mov r5, r8, lsr #7 @ get shift count + ands r5, r5, #31 + and r7, r8, #0x70 @ get shift type + orreq r7, r7, #8 @ shift count = 0 + add pc, pc, r7 + nop + + mov r6, r6, lsl r5 @ 0: LSL #!0 + b .data_arm_apply_r6_and_rn + b .data_arm_apply_r6_and_rn @ 1: LSL #0 + nop + b .data_unknown @ 2: MUL? + nop + b .data_unknown @ 3: MUL? + nop + mov r6, r6, lsr r5 @ 4: LSR #!0 + b .data_arm_apply_r6_and_rn + mov r6, r6, lsr #32 @ 5: LSR #32 + b .data_arm_apply_r6_and_rn + b .data_unknown @ 6: MUL? + nop + b .data_unknown @ 7: MUL? + nop + mov r6, r6, asr r5 @ 8: ASR #!0 + b .data_arm_apply_r6_and_rn + mov r6, r6, asr #32 @ 9: ASR #32 + b .data_arm_apply_r6_and_rn + b .data_unknown @ A: MUL? + nop + b .data_unknown @ B: MUL? + nop + mov r6, r6, ror r5 @ C: ROR #!0 + b .data_arm_apply_r6_and_rn + mov r6, r6, rrx @ D: RRX + b .data_arm_apply_r6_and_rn + b .data_unknown @ E: MUL? + nop + b .data_unknown @ F: MUL? + +.data_thumb_abort: + ldrh r8, [r2] @ read instruction + tst r8, #1 << 11 @ L = 1 -> write? + orreq r1, r1, #1 << 8 @ yes + and r7, r8, #15 << 12 + add pc, pc, r7, lsr #10 @ lookup in table + nop + +/* 0 */ b .data_unknown +/* 1 */ b .data_unknown +/* 2 */ b .data_unknown +/* 3 */ b .data_unknown +/* 4 */ b .data_unknown +/* 5 */ b .data_thumb_reg +/* 6 */ mov pc, lr +/* 7 */ mov pc, lr +/* 8 */ mov pc, lr +/* 9 */ mov pc, lr +/* A */ b .data_unknown +/* B */ b .data_thumb_pushpop +/* C */ b .data_thumb_ldmstm +/* D */ b .data_unknown +/* E */ b .data_unknown +/* F */ b .data_unknown + +.data_thumb_reg: + tst r8, #1 << 9 + moveq pc, lr + tst r8, #1 << 10 @ If 'S' (signed) bit is set + movne r1, #0 @ it must be a load instr + mov pc, lr + +.data_thumb_pushpop: + tst r8, #1 << 10 + beq .data_unknown + mov r7, #0x11 + and r6, r8, r7 + and r2, r8, r7, lsl #1 + add r6, r6, r2, lsr #1 + and r2, r8, r7, lsl #2 + add r6, r6, r2, lsr #2 + and r2, r8, r7, lsl #3 + add r6, r6, r2, lsr #3 + add r6, r6, r6, lsr #4 + and r2, r8, #0x0100 @ catch 'R' bit for push/pop + add r6, r6, r2, lsr #8 + and r6, r6, #15 @ number of regs to transfer + ldr r7, [sp, #13 << 2] + tst r8, #1 << 11 + addne r7, r7, r6, lsl #2 @ increment SP if PUSH + subeq r7, r7, r6, lsr #2 @ decrement SP if POP + str r7, [sp, #13 << 2] + mov pc, lr + +.data_thumb_ldmstm: + mov r7, #0x11 + and r6, r8, r7 + and r2, r8, r7, lsl #1 + add r6, r6, r2, lsr #1 + and r2, r8, r7, lsl #2 + add r6, r6, r2, lsr #2 + and r2, r8, r7, lsl #3 + add r6, r6, r2, lsr #3 + add r6, r6, r6, lsr #4 + and r6, r6, #15 @ number of regs to transfer + and r5, r8, #7 << 8 + ldr r7, [sp, r5, lsr #6] + sub r7, r7, r6, lsr #2 @ always decrement + str r7, [sp, r5, lsr #6] + mov pc, lr diff -urN linux-2.5.2-pre8/arch/arm/mm/armv5ej-early-abort.S linux/arch/arm/mm/armv5ej-early-abort.S --- linux-2.5.2-pre8/arch/arm/mm/armv5ej-early-abort.S Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mm/armv5ej-early-abort.S Sat Jan 5 14:43:15 2002 @@ -0,0 +1,35 @@ +#include +#include +/* + * Function: armv5ej_early_abort + * + * Params : r2 = address of aborted instruction + * : r3 = saved SPSR + * + * Returns : r0 = address of abort + * : r1 = FSR, bit 8 = write + * : r2-r8 = corrupted + * : r9 = preserved + * : sp = pointer to registers + * + * Purpose : obtain information about current aborted instruction. + * Note: we read user space. This means we might cause a data + * abort here if the I-TLB and D-TLB aren't seeing the same + * picture. Unfortunately, this does happen. We live with it. + */ + .align 5 +ENTRY(armv5ej_early_abort) + mrc p15, 0, r1, c5, c0, 0 @ get FSR + mrc p15, 0, r0, c6, c0, 0 @ get FAR + tst r3, #PSR_J_BIT + orrne r1, r1, #1 << 8 @ always assume write + bne 1f + tst r3, #PSR_T_BIT + ldrneh r3, [r2] @ read aborted thumb instruction + ldreq r3, [r2] @ read aborted ARM instruction + movne r3, r3, lsl #(21 - 12) @ move thumb bit 11 to ARM bit 20 + tst r2, #1 << 20 @ L = 1 -> write + orreq r1, r1, #1 << 8 @ yes. +1: mov pc, lr + + diff -urN linux-2.5.2-pre8/arch/arm/mm/fault-armo.c linux/arch/arm/mm/fault-armo.c --- linux-2.5.2-pre8/arch/arm/mm/fault-armo.c Thu Feb 8 16:32:44 2001 +++ linux/arch/arm/mm/fault-armo.c Wed Dec 31 16:00:00 1969 @@ -1,66 +0,0 @@ -/* - * linux/arch/arm/mm/fault-armo.c - * - * Copyright (C) 1995 Linus Torvalds - * Modifications for ARM processor (c) 1995-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#define FAULT_CODE_LDRSTRPOST 0x80 -#define FAULT_CODE_LDRSTRPRE 0x40 -#define FAULT_CODE_LDRSTRREG 0x20 -#define FAULT_CODE_LDMSTM 0x10 -#define FAULT_CODE_LDCSTC 0x08 -#define FAULT_CODE_PREFETCH 0x04 -#define FAULT_CODE_WRITE 0x02 -#define FAULT_CODE_FORCECOW 0x01 - -#define DO_COW(m) ((m) & (FAULT_CODE_WRITE|FAULT_CODE_FORCECOW)) -#define READ_FAULT(m) (!((m) & FAULT_CODE_WRITE)) - -extern int do_page_fault(unsigned long addr, int mode, struct pt_regs *regs); -extern void show_pte(struct mm_struct *mm, unsigned long addr); - -/* - * Handle a data abort. Note that we have to handle a range of addresses - * on ARM2/3 for ldm. If both pages are zero-mapped, then we have to force - * a copy-on-write. However, on the second page, we always force COW. - */ -asmlinkage void -do_DataAbort(unsigned long min_addr, unsigned long max_addr, int mode, struct pt_regs *regs) -{ - do_page_fault(min_addr, mode, regs); - - if ((min_addr ^ max_addr) >> PAGE_SHIFT) - do_page_fault(max_addr, mode | FAULT_CODE_FORCECOW, regs); -} - -asmlinkage int -do_PrefetchAbort(unsigned long addr, struct pt_regs *regs) -{ -#if 0 - if (the memc mapping for this page exists) { - printk ("Page in, but got abort (undefined instruction?)\n"); - return 0; - } -#endif - do_page_fault(addr, FAULT_CODE_PREFETCH, regs); - return 1; -} diff -urN linux-2.5.2-pre8/arch/arm/mm/fault-armv.c linux/arch/arm/mm/fault-armv.c --- linux-2.5.2-pre8/arch/arm/mm/fault-armv.c Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mm/fault-armv.c Sat Jan 5 14:43:15 2002 @@ -9,6 +9,7 @@ * published by the Free Software Foundation. */ #include +#include #include #include #include @@ -27,7 +28,6 @@ #include #include #include -#include extern void die_if_kernel(const char *str, struct pt_regs *regs, int err); extern void show_pte(struct mm_struct *mm, unsigned long addr); @@ -40,499 +40,15 @@ struct pt_regs *regs); #ifdef CONFIG_ALIGNMENT_TRAP -/* - * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998 - * /proc/sys/debug/alignment, modified and integrated into - * Linux 2.1 by Russell King - * - * Speed optimisations and better fault handling by Russell King. - * - * *** NOTE *** - * This code is not portable to processors with late data abort handling. - */ -#define CODING_BITS(i) (i & 0x0e000000) - -#define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */ -#define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */ -#define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */ -#define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */ -#define LDST_L_BIT(i) (i & (1 << 20)) /* Load */ - -#define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0) - -#define LDSTH_I_BIT(i) (i & (1 << 22)) /* half-word immed */ -#define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */ - -#define RN_BITS(i) ((i >> 16) & 15) /* Rn */ -#define RD_BITS(i) ((i >> 12) & 15) /* Rd */ -#define RM_BITS(i) (i & 15) /* Rm */ - -#define REGMASK_BITS(i) (i & 0xffff) -#define OFFSET_BITS(i) (i & 0x0fff) - -#define IS_SHIFT(i) (i & 0x0ff0) -#define SHIFT_BITS(i) ((i >> 7) & 0x1f) -#define SHIFT_TYPE(i) (i & 0x60) -#define SHIFT_LSL 0x00 -#define SHIFT_LSR 0x20 -#define SHIFT_ASR 0x40 -#define SHIFT_RORRRX 0x60 - -static unsigned long ai_user; -static unsigned long ai_sys; -static unsigned long ai_skipped; -static unsigned long ai_half; -static unsigned long ai_word; -static unsigned long ai_multi; - -#ifdef CONFIG_SYSCTL -static int proc_alignment_read(char *page, char **start, off_t off, - int count, int *eof, void *data) -{ - char *p = page; - int len; - - p += sprintf(p, "User:\t\t%li\n", ai_user); - p += sprintf(p, "System:\t\t%li\n", ai_sys); - p += sprintf(p, "Skipped:\t%li\n", ai_skipped); - p += sprintf(p, "Half:\t\t%li\n", ai_half); - p += sprintf(p, "Word:\t\t%li\n", ai_word); - p += sprintf(p, "Multi:\t\t%li\n", ai_multi); - - len = (p - page) - off; - if (len < 0) - len = 0; - - *eof = (len <= count) ? 1 : 0; - *start = page + off; - - return len; -} - -/* - * This needs to be done after sysctl_init, otherwise sys/ - * will be overwritten. - */ -static int __init alignment_init(void) -{ - create_proc_read_entry("sys/debug/alignment", 0, NULL, - proc_alignment_read, NULL); - return 0; -} - -__initcall(alignment_init); -#endif /* CONFIG_SYSCTL */ - -union offset_union { - unsigned long un; - signed long sn; -}; - -#define TYPE_ERROR 0 -#define TYPE_FAULT 1 -#define TYPE_LDST 2 -#define TYPE_DONE 3 - -#define get8_unaligned_check(val,addr,err) \ - __asm__( \ - "1: ldrb %1, [%2], #1\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - " .align 2\n" \ - "3: mov %0, #1\n" \ - " b 2b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 3b\n" \ - " .previous\n" \ - : "=r" (err), "=&r" (val), "=r" (addr) \ - : "0" (err), "2" (addr)) - -#define get8t_unaligned_check(val,addr,err) \ - __asm__( \ - "1: ldrbt %1, [%2], #1\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - " .align 2\n" \ - "3: mov %0, #1\n" \ - " b 2b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 3b\n" \ - " .previous\n" \ - : "=r" (err), "=&r" (val), "=r" (addr) \ - : "0" (err), "2" (addr)) - -#define get16_unaligned_check(val,addr) \ - do { \ - unsigned int err = 0, v, a = addr; \ - get8_unaligned_check(val,a,err); \ - get8_unaligned_check(v,a,err); \ - val |= v << 8; \ - if (err) \ - goto fault; \ - } while (0) - -#define put16_unaligned_check(val,addr) \ - do { \ - unsigned int err = 0, v = val, a = addr; \ - __asm__( \ - "1: strb %1, [%2], #1\n" \ - " mov %1, %1, lsr #8\n" \ - "2: strb %1, [%2]\n" \ - "3:\n" \ - " .section .fixup,\"ax\"\n" \ - " .align 2\n" \ - "4: mov %0, #1\n" \ - " b 3b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 4b\n" \ - " .long 2b, 4b\n" \ - " .previous\n" \ - : "=r" (err), "=&r" (v), "=&r" (a) \ - : "0" (err), "1" (v), "2" (a)); \ - if (err) \ - goto fault; \ - } while (0) - -#define __put32_unaligned_check(ins,val,addr) \ - do { \ - unsigned int err = 0, v = val, a = addr; \ - __asm__( \ - "1: "ins" %1, [%2], #1\n" \ - " mov %1, %1, lsr #8\n" \ - "2: "ins" %1, [%2], #1\n" \ - " mov %1, %1, lsr #8\n" \ - "3: "ins" %1, [%2], #1\n" \ - " mov %1, %1, lsr #8\n" \ - "4: "ins" %1, [%2]\n" \ - "5:\n" \ - " .section .fixup,\"ax\"\n" \ - " .align 2\n" \ - "6: mov %0, #1\n" \ - " b 5b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 6b\n" \ - " .long 2b, 6b\n" \ - " .long 3b, 6b\n" \ - " .long 4b, 6b\n" \ - " .previous\n" \ - : "=r" (err), "=&r" (v), "=&r" (a) \ - : "0" (err), "1" (v), "2" (a)); \ - if (err) \ - goto fault; \ - } while (0) - -#define get32_unaligned_check(val,addr) \ - do { \ - unsigned int err = 0, v, a = addr; \ - get8_unaligned_check(val,a,err); \ - get8_unaligned_check(v,a,err); \ - val |= v << 8; \ - get8_unaligned_check(v,a,err); \ - val |= v << 16; \ - get8_unaligned_check(v,a,err); \ - val |= v << 24; \ - if (err) \ - goto fault; \ - } while (0) - -#define put32_unaligned_check(val,addr) \ - __put32_unaligned_check("strb", val, addr) - -#define get32t_unaligned_check(val,addr) \ - do { \ - unsigned int err = 0, v, a = addr; \ - get8t_unaligned_check(val,a,err); \ - get8t_unaligned_check(v,a,err); \ - val |= v << 8; \ - get8t_unaligned_check(v,a,err); \ - val |= v << 16; \ - get8t_unaligned_check(v,a,err); \ - val |= v << 24; \ - if (err) \ - goto fault; \ - } while (0) - -#define put32t_unaligned_check(val,addr) \ - __put32_unaligned_check("strbt", val, addr) - -static void -do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset) -{ - if (!LDST_U_BIT(instr)) - offset.un = -offset.un; - - if (!LDST_P_BIT(instr)) - addr += offset.un; - - if (!LDST_P_BIT(instr) || LDST_W_BIT(instr)) - regs->uregs[RN_BITS(instr)] = addr; -} - -static int -do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs) -{ - unsigned int rd = RD_BITS(instr); - - if ((instr & 0x01f00ff0) == 0x01000090) - goto swp; - - if ((instr & 0x90) != 0x90 || (instr & 0x60) == 0) - goto bad; - - ai_half += 1; - - if (LDST_L_BIT(instr)) { - unsigned long val; - get16_unaligned_check(val, addr); - - /* signed half-word? */ - if (instr & 0x40) - val = (signed long)((signed short) val); - - regs->uregs[rd] = val; - } else - put16_unaligned_check(regs->uregs[rd], addr); - - return TYPE_LDST; - -swp: - printk(KERN_ERR "Alignment trap: not handling swp instruction\n"); -bad: - return TYPE_ERROR; - -fault: - return TYPE_FAULT; -} - -static int -do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs) -{ - unsigned int rd = RD_BITS(instr); - - ai_word += 1; - - if (!LDST_P_BIT(instr) && LDST_W_BIT(instr)) - goto trans; - - if (LDST_L_BIT(instr)) - get32_unaligned_check(regs->uregs[rd], addr); - else - put32_unaligned_check(regs->uregs[rd], addr); - return TYPE_LDST; - -trans: - if (LDST_L_BIT(instr)) - get32t_unaligned_check(regs->uregs[rd], addr); - else - put32t_unaligned_check(regs->uregs[rd], addr); - return TYPE_LDST; - -fault: - return TYPE_FAULT; -} - -/* - * LDM/STM alignment handler. - * - * There are 4 variants of this instruction: - * - * B = rn pointer before instruction, A = rn pointer after instruction - * ------ increasing address -----> - * | | r0 | r1 | ... | rx | | - * PU = 01 B A - * PU = 11 B A - * PU = 00 A B - * PU = 10 A B - */ -static int -do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs) -{ - unsigned int rd, rn, correction, nr_regs, regbits; - unsigned long eaddr, newaddr; - - if (LDM_S_BIT(instr)) - goto bad; - - correction = 4; /* processor implementation defined */ - regs->ARM_pc += correction; - - ai_multi += 1; - - /* count the number of registers in the mask to be transferred */ - nr_regs = hweight16(REGMASK_BITS(instr)) * 4; - - rn = RN_BITS(instr); - newaddr = eaddr = regs->uregs[rn]; - - if (!LDST_U_BIT(instr)) - nr_regs = -nr_regs; - newaddr += nr_regs; - if (!LDST_U_BIT(instr)) - eaddr = newaddr; - - if (LDST_P_EQ_U(instr)) /* U = P */ - eaddr += 4; - - /* - * This is a "hint" - we already have eaddr worked out by the - * processor for us. - */ - if (addr != eaddr) { - printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, " - "addr = %08lx, eaddr = %08lx\n", - instruction_pointer(regs), instr, addr, eaddr); - show_regs(regs); - } - - for (regbits = REGMASK_BITS(instr), rd = 0; regbits; regbits >>= 1, rd += 1) - if (regbits & 1) { - if (LDST_L_BIT(instr)) - get32_unaligned_check(regs->uregs[rd], eaddr); - else - put32_unaligned_check(regs->uregs[rd], eaddr); - eaddr += 4; - } - - if (LDST_W_BIT(instr)) - regs->uregs[rn] = newaddr; - if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15))) - regs->ARM_pc -= correction; - return TYPE_DONE; - -fault: - regs->ARM_pc -= correction; - return TYPE_FAULT; - -bad: - printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n"); - return TYPE_ERROR; -} - -static int -do_alignment(unsigned long addr, int error_code, struct pt_regs *regs) -{ - union offset_union offset; - unsigned long instr, instrptr; - int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs); - unsigned int type; - - if (user_mode(regs)) - goto user; - - ai_sys += 1; - - instrptr = instruction_pointer(regs); - instr = *(unsigned long *)instrptr; - - regs->ARM_pc += 4; - - switch (CODING_BITS(instr)) { - case 0x00000000: /* ldrh or strh */ - if (LDSTH_I_BIT(instr)) - offset.un = (instr & 0xf00) >> 4 | (instr & 15); - else - offset.un = regs->uregs[RM_BITS(instr)]; - handler = do_alignment_ldrhstrh; - break; - - case 0x04000000: /* ldr or str immediate */ - offset.un = OFFSET_BITS(instr); - handler = do_alignment_ldrstr; - break; - - case 0x06000000: /* ldr or str register */ - offset.un = regs->uregs[RM_BITS(instr)]; - - if (IS_SHIFT(instr)) { - unsigned int shiftval = SHIFT_BITS(instr); - - switch(SHIFT_TYPE(instr)) { - case SHIFT_LSL: - offset.un <<= shiftval; - break; - - case SHIFT_LSR: - offset.un >>= shiftval; - break; - - case SHIFT_ASR: - offset.sn >>= shiftval; - break; - - case SHIFT_RORRRX: - if (shiftval == 0) { - offset.un >>= 1; - if (regs->ARM_cpsr & CC_C_BIT) - offset.un |= 1 << 31; - } else - offset.un = offset.un >> shiftval | - offset.un << (32 - shiftval); - break; - } - } - handler = do_alignment_ldrstr; - break; - - case 0x08000000: /* ldm or stm */ - handler = do_alignment_ldmstm; - break; - - default: - goto bad; - } - - type = handler(addr, instr, regs); - - if (type == TYPE_ERROR || type == TYPE_FAULT) - goto bad_or_fault; - - if (type == TYPE_LDST) - do_alignment_finish_ldst(addr, instr, regs, offset); - - return 0; - -bad_or_fault: - if (type == TYPE_ERROR) - goto bad; - regs->ARM_pc -= 4; - /* - * We got a fault - fix it up, or die. - */ - do_bad_area(current, current->mm, addr, error_code, regs); - return 0; - -bad: - /* - * Oops, we didn't handle the instruction. - */ - printk(KERN_ERR "Alignment trap: not handling instruction " - "%08lx at [<%08lx>]\n", instr, instrptr); - ai_skipped += 1; - return 1; - -user: - set_cr(cr_no_alignment); - ai_user += 1; - return 0; -} - +extern int do_alignment(unsigned long addr, int error_code, struct pt_regs *regs); #else - -#define do_alignment NULL - +#define do_alignment do_bad #endif + /* - * Some section permission faults need to be handled gracefully, for - * instance, when they happen due to a __{get,put}_user during an oops). + * Some section permission faults need to be handled gracefully. + * They can happen due to a __{get,put}_user during an oops. */ static int do_sect_fault(unsigned long addr, int error_code, struct pt_regs *regs) @@ -557,73 +73,54 @@ return 1; } +/* + * This abort handler always returns "fault". + */ +static int +do_bad(unsigned long addr, int error_code, struct pt_regs *regs) +{ + return 1; +} + static const struct fsr_info { int (*fn)(unsigned long addr, int error_code, struct pt_regs *regs); int sig; - char *name; + const char *name; } fsr_info[] = { - { NULL, SIGSEGV, "vector exception" }, + { do_bad, SIGSEGV, "vector exception" }, { do_alignment, SIGILL, "alignment exception" }, - { NULL, SIGKILL, "terminal exception" }, + { do_bad, SIGKILL, "terminal exception" }, { do_alignment, SIGILL, "alignment exception" }, { do_external_fault, SIGBUS, "external abort on linefetch" }, { do_translation_fault, SIGSEGV, "section translation fault" }, { do_external_fault, SIGBUS, "external abort on linefetch" }, { do_page_fault, SIGSEGV, "page translation fault" }, { do_external_fault, SIGBUS, "external abort on non-linefetch" }, - { NULL, SIGSEGV, "section domain fault" }, + { do_bad, SIGSEGV, "section domain fault" }, { do_external_fault, SIGBUS, "external abort on non-linefetch" }, - { NULL, SIGSEGV, "page domain fault" }, - { NULL, SIGBUS, "external abort on translation" }, + { do_bad, SIGSEGV, "page domain fault" }, + { do_bad, SIGBUS, "external abort on translation" }, { do_sect_fault, SIGSEGV, "section permission fault" }, - { NULL, SIGBUS, "external abort on translation" }, + { do_bad, SIGBUS, "external abort on translation" }, { do_page_fault, SIGSEGV, "page permission fault" } }; /* - * Currently dropped down to debug level + * Dispatch a data abort to the relevant handler. */ asmlinkage void -do_DataAbort(unsigned long addr, int error_code, struct pt_regs *regs, int fsr) +do_DataAbort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { const struct fsr_info *inf = fsr_info + (fsr & 15); -#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100) || defined(CONFIG_DEBUG_ERRORS) - if (addr == regs->ARM_pc) - goto sa1_weirdness; -#endif - - if (!inf->fn) - goto bad; - - if (!inf->fn(addr, error_code, regs)) + if (!inf->fn(addr, fsr, regs)) return; -bad: + printk(KERN_ALERT "Unhandled fault: %s (%X) at 0x%08lx\n", inf->name, fsr, addr); - show_pte(current->mm, addr); force_sig(inf->sig, current); + show_pte(current->mm, addr); die_if_kernel("Oops", regs, 0); - return; - -#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100) || defined(CONFIG_DEBUG_ERRORS) -sa1_weirdness: - if (user_mode(regs)) { - static int first = 1; - if (first) { - printk(KERN_DEBUG "Fixing up bad data abort at %08lx\n", addr); -#ifdef CONFIG_DEBUG_ERRORS - show_pte(current->mm, addr); -#endif - } - first = 0; - return; - } - - if (!inf->fn || inf->fn(addr, error_code, regs)) - goto bad; - return; -#endif } asmlinkage void @@ -727,7 +224,7 @@ * Note that we intentionally don't mask out the VMA * that we are fixing up. */ - if (mpnt->vm_mm != mm && mpnt != vma) + if (mpnt->vm_mm != mm || mpnt == vma) continue; /* diff -urN linux-2.5.2-pre8/arch/arm/mm/fault-common.c linux/arch/arm/mm/fault-common.c --- linux-2.5.2-pre8/arch/arm/mm/fault-common.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/mm/fault-common.c Sat Jan 5 14:43:15 2002 @@ -39,8 +39,8 @@ * of the 26-bit machines, and also means that we avoid the horrible * gcc code for "int val = !other_val;". */ -#define DO_COW(m) (m) -#define READ_FAULT(m) (!(m)) +#define DO_COW(code) ((code) & (1 << 8)) +#define READ_FAULT(code) (!DO_COW(code)) #endif NORET_TYPE void die(const char *msg, struct pt_regs *regs, int err) ATTRIB_NORET; diff -urN linux-2.5.2-pre8/arch/arm/mm/minicache.c linux/arch/arm/mm/minicache.c --- linux-2.5.2-pre8/arch/arm/mm/minicache.c Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mm/minicache.c Sat Jan 5 14:43:15 2002 @@ -0,0 +1,63 @@ +/* + * linux/arch/arm/mm/minicache.c + * + * Copyright (C) 2001 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This handles the mini data cache, as found on SA11x0 and XScale + * processors. When we copy a user page page, we map it in such a way + * that accesses to this page will not touch the main data cache, but + * will be cached in the mini data cache. This prevents us thrashing + * the main data cache on page faults. + */ +#include +#include +#include +#include + +#define minicache_address (0xffff2000) +#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \ + L_PTE_CACHEABLE) + +static pte_t *minicache_pte; + +/* + * Note that this is intended to be called only from the copy_user_page + * asm code; anything else will require special locking to prevent the + * mini-cache space being re-used. (Note: probably preempt unsafe). + * + * We rely on the fact that the minicache is 2K, and we'll be pushing + * 4K of data through it, so we don't actually have to specifically + * flush the minicache when we change the mapping. + * + * Note also: assert(PAGE_OFFSET <= virt < high_memory). + * Unsafe: preempt, kmap. + */ +unsigned long map_page_minicache(unsigned long virt) +{ + set_pte(minicache_pte, mk_pte_phys(__pa(virt), minicache_pgprot)); + cpu_tlb_invalidate_page(minicache_address, 0); + + return minicache_address; +} + +static int __init minicache_init(void) +{ + pgd_t *pgd; + pmd_t *pmd; + + pgd = pgd_offset_k(minicache_address); + pmd = pmd_alloc(&init_mm, pgd, minicache_address); + if (!pmd) + BUG(); + minicache_pte = pte_alloc(&init_mm, pmd, minicache_address); + if (!minicache_pte) + BUG(); + + return 0; +} + +__initcall(minicache_init); diff -urN linux-2.5.2-pre8/arch/arm/mm/mm-armo.c linux/arch/arm/mm/mm-armo.c --- linux-2.5.2-pre8/arch/arm/mm/mm-armo.c Thu Apr 12 12:20:31 2001 +++ linux/arch/arm/mm/mm-armo.c Wed Dec 31 16:00:00 1969 @@ -1,184 +0,0 @@ -/* - * linux/arch/arm/mm/mm-armo.c - * - * Copyright (C) 1998-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Page table sludge for older ARM processor architectures. - */ -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#define MEMC_TABLE_SIZE (256*sizeof(unsigned long)) - -kmem_cache_t *pte_cache, *pgd_cache; -int page_nr; - -/* - * Allocate a page table. Note that we place the MEMC - * table before the page directory. This means we can - * easily get to both tightly-associated data structures - * with a single pointer. - */ -static inline pgd_t *alloc_pgd_table(int priority) -{ - void *pg2k = kmem_cache_alloc(pgd_cache, GFP_KERNEL); - - if (pg2k) - pg2k += MEMC_TABLE_SIZE; - - return (pgd_t *)pg2k; -} - -void free_pgd_slow(pgd_t *pgd) -{ - unsigned long tbl = (unsigned long)pgd; - - /* - * CHECKME: are we leaking pte tables here??? - */ - - tbl -= MEMC_TABLE_SIZE; - - kmem_cache_free(pgd_cache, (void *)tbl); -} - -pgd_t *get_pgd_slow(struct mm_struct *mm) -{ - pgd_t *new_pgd, *init_pgd; - pmd_t *new_pmd, *init_pmd; - pte_t *new_pte, *init_pte; - - new_pgd = alloc_pgd_table(GFP_KERNEL); - if (!new_pgd) - goto no_pgd; - - /* - * This lock is here just to satisfy pmd_alloc and pte_lock - */ - spin_lock(&mm->page_table_lock); - - /* - * On ARM, first page must always be allocated since it contains - * the machine vectors. - */ - new_pmd = pmd_alloc(mm, new_pgd, 0); - if (!new_pmd) - goto no_pmd; - - new_pte = pte_alloc(mm, new_pmd, 0); - if (!new_pte) - goto no_pte; - - init_pgd = pgd_offset_k(0); - init_pmd = pmd_offset(init_pgd, 0); - init_pte = pte_offset(init_pmd, 0); - - set_pte(new_pte, *init_pte); - - /* - * most of the page table entries are zeroed - * wne the table is created. - */ - memcpy(new_pgd + USER_PTRS_PER_PGD, init_pgd + USER_PTRS_PER_PGD, - (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); - - spin_unlock(&mm->page_table_lock); - - /* update MEMC tables */ - cpu_memc_update_all(new_pgd); - return new_pgd; - -no_pte: - spin_unlock(&mm->page_table_lock); - pmd_free(new_pmd); - free_pgd_slow(new_pgd); - return NULL; - -no_pmd: - spin_unlock(&mm->page_table_lock); - free_pgd_slow(new_pgd); - return NULL; - -no_pgd: - return NULL; -} - -/* - * No special code is required here. - */ -void setup_mm_for_reboot(char mode) -{ -} - -/* - * This contains the code to setup the memory map on an ARM2/ARM250/ARM3 - * machine. This is both processor & architecture specific, and requires - * some more work to get it to fit into our separate processor and - * architecture structure. - */ -void __init memtable_init(struct meminfo *mi) -{ - pte_t *pte; - int i; - - page_nr = max_low_pfn; - - pte = alloc_bootmem_low_pages(PTRS_PER_PTE * sizeof(pte_t)); - pte[0] = mk_pte_phys(PAGE_OFFSET + 491520, PAGE_READONLY); - pmd_populate(&init_mm, pmd_offset(swapper_pg_dir, 0), pte); - - for (i = 1; i < PTRS_PER_PGD; i++) - pgd_val(swapper_pg_dir[i]) = 0; -} - -void __init iotable_init(struct map_desc *io_desc) -{ - /* nothing to do */ -} - -/* - * We never have holes in the memmap - */ -void __init create_memmap_holes(struct meminfo *mi) -{ -} - -static void pte_cache_ctor(void *pte, kmem_cache_t *cache, unsigned long flags) -{ - memzero(pte, sizeof(pte_t) * PTRS_PER_PTE); -} - -static void pgd_cache_ctor(void *pte, kmem_cache_t *cache, unsigned long flags) -{ - pgd_t *pgd = (pte + MEMC_TABLE_SIZE); - - memzero(pgd, USER_PTRS_PER_PGD * sizeof(pgd_t)); -} - -void __init pgtable_cache_init(void) -{ - pte_cache = kmem_cache_create("pte-cache", - sizeof(pte_t) * PTRS_PER_PTE, - 0, 0, pte_cache_ctor, NULL); - if (!pte_cache) - BUG(); - - pgd_cache = kmem_cache_create("pgd-cache", MEMC_TABLE_SIZE + - sizeof(pgd_t) * PTRS_PER_PGD, - 0, 0, pgd_cache_ctor, NULL); - if (!pgd_cache) - BUG(); -} diff -urN linux-2.5.2-pre8/arch/arm/mm/mm-armv.c linux/arch/arm/mm/mm-armv.c --- linux-2.5.2-pre8/arch/arm/mm/mm-armv.c Wed Jun 27 14:12:04 2001 +++ linux/arch/arm/mm/mm-armv.c Sat Jan 5 14:43:15 2002 @@ -30,8 +30,8 @@ */ static int __init nocache_setup(char *__unused) { - cr_alignment &= ~4; - cr_no_alignment &= ~4; + cr_alignment &= ~CR1_C; + cr_no_alignment &= ~CR1_C; flush_cache_all(); set_cr(cr_alignment); return 1; @@ -39,8 +39,8 @@ static int __init nowrite_setup(char *__unused) { - cr_alignment &= ~(8|4); - cr_no_alignment &= ~(8|4); + cr_alignment &= ~(CR1_W|CR1_C); + cr_no_alignment &= ~(CR1_W|CR1_C); flush_cache_all(); set_cr(cr_alignment); return 1; @@ -48,8 +48,8 @@ static int __init noalign_setup(char *__unused) { - cr_alignment &= ~2; - cr_no_alignment &= ~2; + cr_alignment &= ~CR1_A; + cr_no_alignment &= ~CR1_A; set_cr(cr_alignment); return 1; } diff -urN linux-2.5.2-pre8/arch/arm/mm/mm-clps7500.c linux/arch/arm/mm/mm-clps7500.c --- linux-2.5.2-pre8/arch/arm/mm/mm-clps7500.c Thu Apr 12 12:20:31 2001 +++ linux/arch/arm/mm/mm-clps7500.c Wed Dec 31 16:00:00 1969 @@ -1,30 +0,0 @@ -/* - * linux/arch/arm/mm/mm-cl7500.c - * - * Copyright (C) 1998 Russell King - * Copyright (C) 1999 Nexus Electronics Ltd - * - * Extra MM routines for CL7500 architecture - */ -#include -#include - -#include -#include -#include -#include - -#include - -static struct map_desc cl7500_io_desc[] __initdata = { - { IO_BASE, IO_START, IO_SIZE , DOMAIN_IO, 0, 1 }, /* IO space */ - { ISA_BASE, ISA_START, ISA_SIZE , DOMAIN_IO, 0, 1 }, /* ISA space */ - { FLASH_BASE, FLASH_START, FLASH_SIZE, DOMAIN_IO, 0, 1 }, /* Flash */ - { LED_BASE, LED_START, LED_SIZE , DOMAIN_IO, 0, 1 }, /* LED */ - LAST_DESC -}; - -void __init clps7500_map_io(void) -{ - iotable_init(cl7500_io_desc); -} diff -urN linux-2.5.2-pre8/arch/arm/mm/mm-ftvpci.c linux/arch/arm/mm/mm-ftvpci.c --- linux-2.5.2-pre8/arch/arm/mm/mm-ftvpci.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/mm/mm-ftvpci.c Wed Dec 31 16:00:00 1969 @@ -1,32 +0,0 @@ -/* - * linux/arch/arm/mm/mm-nexuspci.c - * from linux/arch/arm/mm/mm-ebsa110.c - * - * Copyright (C) 1998-1999 Phil Blundell - * Copyright (C) 1998-1999 Russell King - * - * Extra MM routines for the FTV/PCI architecture - */ -#include -#include -#include - -#include -#include -#include - -#include - -static struct map_desc nexuspci_io_desc[] __initdata = { - { INTCONT_BASE, INTCONT_START, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, - { PLX_BASE, PLX_START, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, - { PCIO_BASE, PLX_IO_START, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, - { DUART_BASE, DUART_START, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, - { STATUS_BASE, STATUS_START, 0x00001000, DOMAIN_IO, 0, 1, 0, 0 }, - LAST_DESC -}; - -void __init nexuspci_map_io(void) -{ - iotable_init(nexuspci_io_desc); -} diff -urN linux-2.5.2-pre8/arch/arm/mm/mm-l7200.c linux/arch/arm/mm/mm-l7200.c --- linux-2.5.2-pre8/arch/arm/mm/mm-l7200.c Wed Jun 27 14:12:04 2001 +++ linux/arch/arm/mm/mm-l7200.c Wed Dec 31 16:00:00 1969 @@ -1,28 +0,0 @@ -/* - * linux/arch/arm/mm/mm-lusl7200.c - * - * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) - * - * Extra MM routines for L7200 architecture - */ -#include - -#include -#include -#include - -#include - -static struct map_desc l7200_io_desc[] __initdata = { - { IO_BASE, IO_START, IO_SIZE, DOMAIN_IO, 0, 1 ,0 ,0}, - { IO_BASE_2, IO_START_2, IO_SIZE_2, DOMAIN_IO, 0, 1 ,0 ,0}, - { AUX_BASE, AUX_START, AUX_SIZE, DOMAIN_IO, 0, 1 ,0 ,0}, - { FLASH1_BASE, FLASH1_START, FLASH1_SIZE, DOMAIN_IO, 0, 1 ,0 ,0}, - { FLASH2_BASE, FLASH2_START, FLASH2_SIZE, DOMAIN_IO, 0, 1 ,0 ,0}, - LAST_DESC -}; - -void __init l7200_map_io(void) -{ - iotable_init(l7200_io_desc); -} diff -urN linux-2.5.2-pre8/arch/arm/mm/mm-rpc.c linux/arch/arm/mm/mm-rpc.c --- linux-2.5.2-pre8/arch/arm/mm/mm-rpc.c Tue Mar 6 19:44:35 2001 +++ linux/arch/arm/mm/mm-rpc.c Wed Dec 31 16:00:00 1969 @@ -1,32 +0,0 @@ -/* - * linux/arch/arm/mm/mm-rpc.c - * - * Copyright (C) 1998-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Extra MM routines for RiscPC architecture - */ -#include -#include - -#include -#include -#include -#include - -#include - -static struct map_desc rpc_io_desc[] __initdata = { - { SCREEN_BASE, SCREEN_START, 2*1048576, DOMAIN_IO, 0, 1, 0, 0 }, /* VRAM */ - { IO_BASE, IO_START, IO_SIZE , DOMAIN_IO, 0, 1, 0, 0 }, /* IO space */ - { EASI_BASE, EASI_START, EASI_SIZE, DOMAIN_IO, 0, 1, 0, 0 }, /* EASI space */ - LAST_DESC -}; - -void __init rpc_map_io(void) -{ - iotable_init(rpc_io_desc); -} diff -urN linux-2.5.2-pre8/arch/arm/mm/mm-tbox.c linux/arch/arm/mm/mm-tbox.c --- linux-2.5.2-pre8/arch/arm/mm/mm-tbox.c Mon Sep 18 15:15:25 2000 +++ linux/arch/arm/mm/mm-tbox.c Wed Dec 31 16:00:00 1969 @@ -1,28 +0,0 @@ -/* - * linux/arch/arm/mm/mm-tbox.c - * - * Copyright (C) 1998, 1999, 2000 Phil Blundell - * Copyright (C) 1998-1999 Russell King - * - * Extra MM routines for the Tbox architecture - */ -#include -#include -#include - -#include -#include -#include - -#include - -static struct map_desc tbox_io_desc[] __initdata = { - /* See hardware.h for details */ - { IO_BASE, IO_START, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, - LAST_DESC -}; - -void __init tbox_map_io(void) -{ - iotable_init(tbox_io_desc); -} diff -urN linux-2.5.2-pre8/arch/arm/mm/proc-arm1020.S linux/arch/arm/mm/proc-arm1020.S --- linux-2.5.2-pre8/arch/arm/mm/proc-arm1020.S Fri Nov 9 13:58:02 2001 +++ linux/arch/arm/mm/proc-arm1020.S Sat Jan 5 14:43:15 2002 @@ -51,35 +51,12 @@ #define PAGESIZE 4096 .text - -/* - * cpu_arm1020_data_abort() - * - * obtain information about current aborted instruction - * - * r0 = address of aborted instruction - * - * Returns: - * r0 = address of abort - * r1 != 0 if writing - * r3 = FSR - */ - .align 5 -ENTRY(cpu_arm1020_data_abort) - ldr r1, [r0] @ read aborted instruction - mrc p15, 0, r0, c6, c0, 0 @ get FAR - tst r1, r1, lsr #21 @ C = bit 20 - mrc p15, 0, r3, c5, c0, 0 @ get FSR - sbc r1, r1, r1 @ r1 = C - 1 - and r3, r3, #255 - mov pc, lr - /* * cpu_arm1020_check_bugs() */ ENTRY(cpu_arm1020_check_bugs) mrs ip, cpsr - bic ip, ip, #F_BIT + bic ip, ip, #PSR_F_BIT msr cpsr, ip mov pc, lr @@ -94,7 +71,7 @@ */ ENTRY(cpu_arm1020_proc_fin) stmfd sp!, {lr} - mov ip, #F_BIT | I_BIT | SVC_MODE + mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE msr cpsr_c, ip bl cpu_arm1020_cache_clean_invalidate_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register @@ -696,7 +673,7 @@ */ .type arm1020_processor_functions, #object arm1020_processor_functions: - .word cpu_arm1020_data_abort + .word armv4t_early_abort .word cpu_arm1020_check_bugs .word cpu_arm1020_proc_init .word cpu_arm1020_proc_fin @@ -727,6 +704,11 @@ .word cpu_arm1020_set_pgd .word cpu_arm1020_set_pmd .word cpu_arm1020_set_pte + + /* misc */ + .word armv4_clear_user_page + .word armv4_copy_user_page + .size arm1020_processor_functions, . - arm1020_processor_functions .type cpu_arm1020_info, #object diff -urN linux-2.5.2-pre8/arch/arm/mm/proc-arm2,3.S linux/arch/arm/mm/proc-arm2,3.S --- linux-2.5.2-pre8/arch/arm/mm/proc-arm2,3.S Tue Mar 6 19:44:35 2001 +++ linux/arch/arm/mm/proc-arm2,3.S Sat Jan 5 14:43:15 2002 @@ -234,7 +234,7 @@ */ _arm3_proc_fin: mov r0, #2 mcr p15, 0, r0, c2, c0 -_arm2_proc_fin: orrs pc, lr, #I_BIT|F_BIT +_arm2_proc_fin: orrs pc, lr, #PSR_I_BIT|PSR_F_BIT /* * Function: *_xchg_1 (int new, volatile void *ptr) @@ -244,7 +244,7 @@ * Returns : Original byte data at 'ptr' */ _arm2_xchg_1: mov r2, pc - orr r2, r2, #I_BIT + orr r2, r2, #PSR_I_BIT teqp r2, #0 ldrb r2, [r1] strb r0, [r1] @@ -262,7 +262,7 @@ * Returns : Original word data at 'ptr' */ _arm2_xchg_4: mov r2, pc - orr r2, r2, #I_BIT + orr r2, r2, #PSR_I_BIT teqp r2, #0 ldr r2, [r1] str r0, [r1] diff -urN linux-2.5.2-pre8/arch/arm/mm/proc-arm6,7.S linux/arch/arm/mm/proc-arm6,7.S --- linux-2.5.2-pre8/arch/arm/mm/proc-arm6,7.S Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/mm/proc-arm6,7.S Sat Jan 5 14:43:15 2002 @@ -240,7 +240,7 @@ ENTRY(cpu_arm6_check_bugs) ENTRY(cpu_arm7_check_bugs) mrs ip, cpsr - bic ip, ip, #F_BIT + bic ip, ip, #PSR_F_BIT msr cpsr, ip mov pc, lr @@ -250,7 +250,7 @@ ENTRY(cpu_arm6_proc_fin) ENTRY(cpu_arm7_proc_fin) - mov r0, #F_BIT | I_BIT | SVC_MODE + mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE msr cpsr_c, r0 mov r0, #0x31 @ ....S..DP...M mcr p15, 0, r0, c1, c0, 0 @ disable caches @@ -418,6 +418,11 @@ .word cpu_arm6_set_pgd .word cpu_arm6_set_pmd .word cpu_arm6_set_pte + + /* other */ + .word armv3_clear_user_page + .word armv3_copy_user_page + .size arm6_processor_functions, . - arm6_processor_functions /* @@ -457,6 +462,11 @@ .word cpu_arm7_set_pgd .word cpu_arm7_set_pmd .word cpu_arm7_set_pte + + /* other */ + .word armv3_clear_user_page + .word armv3_copy_user_page + .size arm7_processor_functions, . - arm7_processor_functions .type cpu_arm6_info, #object diff -urN linux-2.5.2-pre8/arch/arm/mm/proc-arm720.S linux/arch/arm/mm/proc-arm720.S --- linux-2.5.2-pre8/arch/arm/mm/proc-arm720.S Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/mm/proc-arm720.S Sat Jan 5 14:43:15 2002 @@ -105,231 +105,6 @@ mov pc, lr /* - * Function: arm720_data_abort () - * - * Params : r0 = address of aborted instruction - * : r3 = saved SPSR - * - * Purpose : obtain information about current aborted instruction - * - * Returns : r0 = address of abort - * : r1 != 0 if writing - * : r3 = FSR - * : sp = pointer to registers - */ - -Ldata_ldmstm: tst r4, #1 << 21 @ check writeback bit - beq Ldata_simple - mov r7, #0x11 - orr r7, r7, r7, lsl #8 - and r0, r4, r7 - and r2, r4, r7, lsl #1 - add r0, r0, r2, lsr #1 - and r2, r4, r7, lsl #2 - add r0, r0, r2, lsr #2 - and r2, r4, r7, lsl #3 - add r0, r0, r2, lsr #3 - add r0, r0, r0, lsr #8 - add r0, r0, r0, lsr #4 - and r7, r0, #15 @ r7 = no. of registers to transfer. - and r5, r4, #15 << 16 @ Get Rn - ldr r0, [sp, r5, lsr #14] @ Get register - tst r4, #1 << 23 @ U bit - subne r7, r0, r7, lsl #2 - addeq r7, r0, r7, lsl #2 @ Do correction (signed) -Ldata_saver7: str r7, [sp, r5, lsr #14] @ Put register -Ldata_simple: mrc p15, 0, r0, c6, c0, 0 @ get FAR - mrc p15, 0, r3, c5, c0, 0 @ get FSR - and r3, r3, #255 - mov pc, lr - -ENTRY(cpu_arm720_data_abort) - tst r3, #T_BIT - bne .data_thumb_abort - ldr r4, [r0] @ read instruction causing problem - tst r4, r4, lsr #21 @ C = bit 20 - sbc r1, r1, r1 @ r1 = C - 1 - and r2, r4, #15 << 24 - add pc, pc, r2, lsr #22 @ Now branch to the relevent processing routine - movs pc, lr - - b Ldata_lateldrhpost @ ldrh rd, [rn], #m/rm - b Ldata_lateldrhpre @ ldrh rd, [rn, #m/rm] - b Ldata_unknown - b Ldata_unknown - b Ldata_lateldrpostconst @ ldr rd, [rn], #m - b Ldata_lateldrpreconst @ ldr rd, [rn, #m] - b Ldata_lateldrpostreg @ ldr rd, [rn], rm - b Ldata_lateldrprereg @ ldr rd, [rn, rm] - b Ldata_ldmstm @ ldm*a rn, - b Ldata_ldmstm @ ldm*b rn, - b Ldata_unknown - b Ldata_unknown - b Ldata_simple @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m - b Ldata_simple @ ldc rd, [rn, #m] - b Ldata_unknown - -Ldata_unknown: @ Part of jumptable - mov r0, r2 - mov r1, r4 - mov r2, sp - bl baddataabort - b ret_from_exception - -Ldata_lateldrhpre: - tst r4, #1 << 21 @ check writeback bit - beq Ldata_simple -Ldata_lateldrhpost: - and r5, r4, #0x00f @ get Rm / low nibble of immediate value - tst r4, #1 << 22 @ if (immediate offset) - andne r2, r4, #0xf00 @ { immediate high nibble - orrne r2, r5, r2, lsr #4 @ combine nibbles } else - ldreq r2, [sp, r5, lsl #2] @ { load Rm value } - and r5, r4, #15 << 16 @ get Rn - ldr r0, [sp, r5, lsr #14] @ load Rn value - tst r4, #1 << 23 @ U bit - subne r7, r0, r2 - addeq r7, r0, r2 - b Ldata_saver7 - -Ldata_lateldrpreconst: - tst r4, #1 << 21 @ check writeback bit - beq Ldata_simple -Ldata_lateldrpostconst: - movs r2, r4, lsl #20 @ Get offset - beq Ldata_simple - and r5, r4, #15 << 16 @ Get Rn - ldr r0, [sp, r5, lsr #14] - tst r4, #1 << 23 @ U bit - subne r7, r0, r2, lsr #20 - addeq r7, r0, r2, lsr #20 - b Ldata_saver7 - -Ldata_lateldrprereg: - tst r4, #1 << 21 @ check writeback bit - beq Ldata_simple -Ldata_lateldrpostreg: - and r5, r4, #15 - ldr r2, [sp, r5, lsl #2] @ Get Rm - mov r3, r4, lsr #7 - ands r3, r3, #31 - and r6, r4, #0x70 - orreq r6, r6, #8 - add pc, pc, r6 - mov r0, r0 - - mov r2, r2, lsl r3 @ 0: LSL #!0 - b 1f - b 1f @ 1: LSL #0 - mov r0, r0 - b 1f @ 2: MUL? - mov r0, r0 - b 1f @ 3: MUL? - mov r0, r0 - mov r2, r2, lsr r3 @ 4: LSR #!0 - b 1f - mov r2, r2, lsr #32 @ 5: LSR #32 - b 1f - b 1f @ 6: MUL? - mov r0, r0 - b 1f @ 7: MUL? - mov r0, r0 - mov r2, r2, asr r3 @ 8: ASR #!0 - b 1f - mov r2, r2, asr #32 @ 9: ASR #32 - b 1f - b 1f @ A: MUL? - mov r0, r0 - b 1f @ B: MUL? - mov r0, r0 - mov r2, r2, ror r3 @ C: ROR #!0 - b 1f - mov r2, r2, rrx @ D: RRX - b 1f - mov r0, r0 @ E: MUL? - mov r0, r0 - mov r0, r0 @ F: MUL? - - -1: and r5, r4, #15 << 16 @ Get Rn - ldr r0, [sp, r5, lsr #14] - tst r4, #1 << 23 @ U bit - subne r7, r0, r2 - addeq r7, r0, r2 - b Ldata_saver7 - -.data_thumb_abort: - ldrh r4, [r0] @ read instruction - tst r4, r4, lsr #12 @ C = bit 11 - sbc r1, r1, r1 @ r1 = C - 1 - and r2, r4, #15 << 12 - add pc, pc, r2, lsr #10 @ lookup in table - nop - -/* 0 */ b Ldata_unknown -/* 1 */ b Ldata_unknown -/* 2 */ b Ldata_unknown -/* 3 */ b Ldata_unknown -/* 4 */ b Ldata_unknown -/* 5 */ b .data_thumb_reg -/* 6 */ b Ldata_simple -/* 7 */ b Ldata_simple -/* 8 */ b Ldata_simple -/* 9 */ b Ldata_simple -/* A */ b Ldata_unknown -/* B */ b .data_thumb_pushpop -/* C */ b .data_thumb_ldmstm -/* D */ b Ldata_unknown -/* E */ b Ldata_unknown -/* F */ b Ldata_unknown - -.data_thumb_reg: - tst r4, #1 << 9 - beq Ldata_simple - tst r4, #1 << 10 @ If 'S' (signed) bit is set - movne r1, #0 @ it must be a load instr - b Ldata_simple - -.data_thumb_pushpop: - tst r4, #1 << 10 - beq Ldata_unknown - mov r7, #0x11 - and r0, r4, r7 - and r2, r4, r7, lsl #1 - add r0, r0, r2, lsr #1 - and r2, r4, r7, lsl #2 - add r0, r0, r2, lsr #2 - and r2, r4, r7, lsl #3 - add r0, r0, r2, lsr #3 - add r0, r0, r0, lsr #4 - and r2, r4, #0x0100 @ catch 'R' bit for push/pop - add r0, r0, r2, lsr #8 - and r0, r0, #15 @ number of regs to transfer - ldr r7, [sp, #13 << 2] - tst r4, #1 << 11 - addne r7, r7, r0, lsl #2 @ increment SP if PUSH - subeq r7, r7, r0, lsr #2 @ decrement SP if POP - str r7, [sp, #13 << 2] - b Ldata_simple - -.data_thumb_ldmstm: - mov r7, #0x11 - and r0, r4, r7 - and r2, r4, r7, lsl #1 - add r0, r0, r2, lsr #1 - and r2, r4, r7, lsl #2 - add r0, r0, r2, lsr #2 - and r2, r4, r7, lsl #3 - add r0, r0, r2, lsr #3 - add r0, r0, r0, lsr #4 - and r0, r0, #15 @ number of regs to transfer - and r5, r4, #7 << 8 - ldr r7, [sp, r5, lsr #6] - sub r7, r7, r0, lsr #2 @ always decrement - str r7, [sp, r5, lsr #6] - b Ldata_simple - -/* * Function: arm720_check_bugs (void) * : arm720_proc_init (void) * : arm720_proc_fin (void) @@ -338,7 +113,7 @@ */ ENTRY(cpu_arm720_check_bugs) mrs ip, cpsr - bic ip, ip, #F_BIT + bic ip, ip, #PSR_F_BIT msr cpsr, ip mov pc, lr @@ -347,7 +122,7 @@ ENTRY(cpu_arm720_proc_fin) stmfd sp!, {lr} - mov ip, #F_BIT | I_BIT | SVC_MODE + mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE msr cpsr_c, ip mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x1000 @ ...i............ @@ -462,7 +237,7 @@ */ .type arm720_processor_functions, #object ENTRY(arm720_processor_functions) - .word cpu_arm720_data_abort + .word armv4t_late_abort .word cpu_arm720_check_bugs .word cpu_arm720_proc_init .word cpu_arm720_proc_fin @@ -493,6 +268,11 @@ .word cpu_arm720_set_pgd .word cpu_arm720_set_pmd .word cpu_arm720_set_pte + + /* misc */ + .word armv4_clear_user_page + .word armv4_copy_user_page + .size arm720_processor_functions, . - arm720_processor_functions .type cpu_arm720_info, #object diff -urN linux-2.5.2-pre8/arch/arm/mm/proc-arm920.S linux/arch/arm/mm/proc-arm920.S --- linux-2.5.2-pre8/arch/arm/mm/proc-arm920.S Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mm/proc-arm920.S Sat Jan 5 14:43:15 2002 @@ -51,35 +51,12 @@ #define PAGESIZE 4096 .text - -/* - * cpu_arm920_data_abort() - * - * obtain information about current aborted instruction - * - * r0 = address of aborted instruction - * - * Returns: - * r0 = address of abort - * r1 != 0 if writing - * r3 = FSR - */ - .align 5 -ENTRY(cpu_arm920_data_abort) - ldr r1, [r0] @ read aborted instruction - mrc p15, 0, r0, c6, c0, 0 @ get FAR - tst r1, r1, lsr #21 @ C = bit 20 - mrc p15, 0, r3, c5, c0, 0 @ get FSR - sbc r1, r1, r1 @ r1 = C - 1 - and r3, r3, #255 - mov pc, lr - /* * cpu_arm920_check_bugs() */ ENTRY(cpu_arm920_check_bugs) mrs ip, cpsr - bic ip, ip, #F_BIT + bic ip, ip, #PSR_F_BIT msr cpsr, ip mov pc, lr @@ -94,7 +71,7 @@ */ ENTRY(cpu_arm920_proc_fin) stmfd sp!, {lr} - mov ip, #F_BIT | I_BIT | SVC_MODE + mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE msr cpsr_c, ip bl cpu_arm920_cache_clean_invalidate_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register @@ -590,7 +567,7 @@ */ .type arm920_processor_functions, #object arm920_processor_functions: - .word cpu_arm920_data_abort + .word armv4t_early_abort .word cpu_arm920_check_bugs .word cpu_arm920_proc_init .word cpu_arm920_proc_fin @@ -621,6 +598,11 @@ .word cpu_arm920_set_pgd .word cpu_arm920_set_pmd .word cpu_arm920_set_pte + + /* misc */ + .word armv4_clear_user_page + .word armv4_copy_user_page + .size arm920_processor_functions, . - arm920_processor_functions .type cpu_arm920_info, #object diff -urN linux-2.5.2-pre8/arch/arm/mm/proc-arm922.S linux/arch/arm/mm/proc-arm922.S --- linux-2.5.2-pre8/arch/arm/mm/proc-arm922.S Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mm/proc-arm922.S Sat Jan 5 14:43:15 2002 @@ -0,0 +1,639 @@ +/* + * linux/arch/arm/mm/arm922.S: MMU functions for ARM922 + * + * Copyright (C) 1999,2000 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * These are the low level assembler for performing cache and TLB + * functions on the arm922. + */ +#include +#include +#include +#include +#include +#include + +/* + * This is the maximum size of an area which will be invalidated + * using the single invalidate entry instructions. Anything larger + * than this, and we go for the whole cache. + * + * This value should be chosen such that we choose the cheapest + * alternative. + */ +#define MAX_AREA_SIZE 8192 + +/* + * the cache line size of the I and D cache + */ +#define DCACHELINESIZE 32 +#define ICACHELINESIZE 32 + +/* + * and the page size + */ +#define PAGESIZE 4096 + + .text +/* + * cpu_arm922_check_bugs() + */ +ENTRY(cpu_arm922_check_bugs) + mrs ip, cpsr + bic ip, ip, #PSR_F_BIT + msr cpsr, ip + mov pc, lr + +/* + * cpu_arm922_proc_init() + */ +ENTRY(cpu_arm922_proc_init) + mov pc, lr + +/* + * cpu_arm922_proc_fin() + */ +ENTRY(cpu_arm922_proc_fin) + stmfd sp!, {lr} + mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE + msr cpsr_c, ip + bl cpu_arm922_cache_clean_invalidate_all + mrc p15, 0, r0, c1, c0, 0 @ ctrl register + bic r0, r0, #0x1000 @ ...i............ + bic r0, r0, #0x000e @ ............wca. + mcr p15, 0, r0, c1, c0, 0 @ disable caches + ldmfd sp!, {pc} + +/* + * cpu_arm922_reset(loc) + * + * Perform a soft reset of the system. Put the CPU into the + * same state as it would be if it had been reset, and branch + * to what would be the reset vector. + * + * loc: location to jump to for soft reset + */ + .align 5 +ENTRY(cpu_arm922_reset) + mov ip, #0 + mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches + mcr p15, 0, ip, c7, c10, 4 @ drain WB + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs + mrc p15, 0, ip, c1, c0, 0 @ ctrl register + bic ip, ip, #0x000f @ ............wcam + bic ip, ip, #0x1100 @ ...i...s........ + mcr p15, 0, ip, c1, c0, 0 @ ctrl register + mov pc, r0 + +/* + * cpu_arm922_do_idle() + */ + .align 5 +ENTRY(cpu_arm922_do_idle) +#if defined(CONFIG_CPU_ARM922_CPU_IDLE) + mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt +#endif + mov pc, lr + +/* ================================= CACHE ================================ */ + + +/* + * cpu_arm922_cache_clean_invalidate_all() + * + * clean and invalidate all cache lines + * + * Note: + * 1. we should preserve r0 at all times + */ + .align 5 +ENTRY(cpu_arm922_cache_clean_invalidate_all) + mov r2, #1 +cpu_arm922_cache_clean_invalidate_all_r2: + mov ip, #0 +#ifdef CONFIG_CPU_ARM922_WRITETHROUGH + mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache +#else +/* + * 'Clean & Invalidate whole DCache' + * Re-written to use Index Ops. + * Uses registers r1, r3 and ip + */ + mov r1, #3 << 5 @ 4 segments +1: orr r3, r1, #63 << 26 @ 64 entries +2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index + subs r3, r3, #1 << 26 + bcs 2b @ entries 63 to 0 + subs r1, r1, #1 << 5 + bcs 1b @ segments 7 to 0 +#endif + teq r2, #0 + mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache + mcr p15, 0, ip, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * cpu_arm922_cache_clean_invalidate_range(start, end, flags) + * + * clean and invalidate all cache lines associated with this area of memory + * + * start: Area start address + * end: Area end address + * flags: nonzero for I cache as well + */ + .align 5 +ENTRY(cpu_arm922_cache_clean_invalidate_range) + bic r0, r0, #DCACHELINESIZE - 1 @ && added by PGM + bic r1, r1, #DCACHELINESIZE - 1 @ && added by DHM + sub r3, r1, r0 + cmp r3, #MAX_AREA_SIZE + bgt cpu_arm922_cache_clean_invalidate_all_r2 +1: teq r2, #0 +#ifdef CONFIG_CPU_ARM922_WRITETHROUGH + mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry + mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #DCACHELINESIZE + mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry + mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #DCACHELINESIZE +#else + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry + mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #DCACHELINESIZE + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry + mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry + add r0, r0, #DCACHELINESIZE +#endif + cmp r0, r1 + blt 1b + + mcr p15, 0, r1, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * cpu_arm922_flush_ram_page(page) + * + * clean and invalidate all cache lines associated with this area of memory + * + * page: page to clean and invalidate + */ + .align 5 +ENTRY(cpu_arm922_flush_ram_page) + mov r1, #PAGESIZE +#ifdef CONFIG_CPU_ARM922_WRITETHROUGH +1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry + add r0, r0, #DCACHELINESIZE + mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry + add r0, r0, #DCACHELINESIZE +#else +1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry + add r0, r0, #DCACHELINESIZE + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry + add r0, r0, #DCACHELINESIZE +#endif + subs r1, r1, #2 * DCACHELINESIZE + bne 1b + mcr p15, 0, r1, c7, c10, 4 @ drain WB + mov pc, lr + +/* ================================ D-CACHE =============================== */ + +/* + * cpu_arm922_dcache_invalidate_range(start, end) + * + * throw away all D-cached data in specified region without an obligation + * to write them back. Note however that we must clean the D-cached entries + * around the boundaries if the start and/or end address are not cache + * aligned. + * + * start: virtual start address + * end: virtual end address + */ + .align 5 +ENTRY(cpu_arm922_dcache_invalidate_range) +#ifndef CONFIG_CPU_ARM922_WRITETHROUGH + tst r0, #DCACHELINESIZE - 1 + mcrne p15, 0, r0, c7, c10, 1 @ clean D entry + tst r1, #DCACHELINESIZE - 1 + mcrne p15, 0, r1, c7, c10, 1 @ clean D entry +#endif @ clean D entry + bic r0, r0, #DCACHELINESIZE - 1 + bic r1, r1, #DCACHELINESIZE - 1 +1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry + add r0, r0, #DCACHELINESIZE + cmp r0, r1 + blt 1b + mov pc, lr + +/* + * cpu_arm922_dcache_clean_range(start, end) + * + * For the specified virtual address range, ensure that all caches contain + * clean data, such that peripheral accesses to the physical RAM fetch + * correct data. + * + * start: virtual start address + * end: virtual end address + */ + .align 5 +ENTRY(cpu_arm922_dcache_clean_range) +#ifndef CONFIG_CPU_ARM922_WRITETHROUGH + bic r0, r0, #DCACHELINESIZE - 1 + sub r1, r1, r0 + cmp r1, #MAX_AREA_SIZE + mov r2, #0 + bgt cpu_arm922_cache_clean_invalidate_all_r2 + + bic r1, r1, #DCACHELINESIZE -1 + add r1, r1, #DCACHELINESIZE + +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, #DCACHELINESIZE + subs r1, r1, #DCACHELINESIZE + bpl 1b +#endif + mcr p15, 0, r2, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * cpu_arm922_dcache_clean_page(page) + * + * Cleans a single page of dcache so that if we have any future aliased + * mappings, they will be consistent at the time that they are created. + * + * page: virtual address of page to clean from dcache + * + * Note: + * 1. we don't need to flush the write buffer in this case. + * 2. we don't invalidate the entries since when we write the page + * out to disk, the entries may get reloaded into the cache. + */ + .align 5 +ENTRY(cpu_arm922_dcache_clean_page) +#ifndef CONFIG_CPU_ARM922_WRITETHROUGH + mov r1, #PAGESIZE +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, #DCACHELINESIZE + mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, #DCACHELINESIZE + subs r1, r1, #2 * DCACHELINESIZE + bne 1b +#endif + mov pc, lr + +/* + * cpu_arm922_dcache_clean_entry(addr) + * + * Clean the specified entry of any caches such that the MMU + * translation fetches will obtain correct data. + * + * addr: cache-unaligned virtual address + */ + .align 5 +ENTRY(cpu_arm922_dcache_clean_entry) +#ifndef CONFIG_CPU_ARM922_WRITETHROUGH + mcr p15, 0, r0, c7, c10, 1 @ clean D entry +#endif + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + +/* ================================ I-CACHE =============================== */ + +/* + * cpu_arm922_icache_invalidate_range(start, end) + * + * invalidate a range of virtual addresses from the Icache + * + * This is a little misleading, it is not intended to clean out + * the i-cache but to make sure that any data written to the + * range is made consistant. This means that when we execute code + * in that region, everything works as we expect. + * + * This generally means writing back data in the Dcache and + * write buffer and flushing the Icache over that region + * + * start: virtual start address + * end: virtual end address + * + * NOTE: ICACHELINESIZE == DCACHELINESIZE (so we don't need to + * loop twice, once for i-cache, once for d-cache) + */ + .align 5 +ENTRY(cpu_arm922_icache_invalidate_range) + bic r0, r0, #ICACHELINESIZE - 1 @ Safety check + sub r1, r1, r0 + cmp r1, #MAX_AREA_SIZE + bgt cpu_arm922_cache_clean_invalidate_all_r2 + + bic r1, r1, #ICACHELINESIZE - 1 + add r1, r1, #ICACHELINESIZE + +1: mcr p15, 0, r0, c7, c5, 1 @ Clean I entry + mcr p15, 0, r0, c7, c10, 1 @ Clean D entry + add r0, r0, #ICACHELINESIZE + subs r1, r1, #ICACHELINESIZE + bne 1b + + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + +ENTRY(cpu_arm922_icache_invalidate_page) + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mov pc, lr + +/* ================================== TLB ================================= */ + +/* + * cpu_arm922_tlb_invalidate_all() + * + * Invalidate all TLB entries + */ + .align 5 +ENTRY(cpu_arm922_tlb_invalidate_all) + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mcr p15, 0, r0, c8, c7, 0 @ invalidate I & D TLBs + mov pc, lr + +/* + * cpu_arm922_tlb_invalidate_range(start, end) + * + * invalidate TLB entries covering the specified range + * + * start: range start address + * end: range end address + */ + .align 5 +ENTRY(cpu_arm922_tlb_invalidate_range) + mov r3, #0 + mcr p15, 0, r3, c7, c10, 4 @ drain WB + + mov r3, #PAGESIZE + sub r3, r3, #1 + bic r0, r0, r3 + bic r1, r1, r3 + +1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry + mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry + add r0, r0, #PAGESIZE + cmp r0, r1 + blt 1b + mov pc, lr + +/* + * cpu_arm922_tlb_invalidate_page(page, flags) + * + * invalidate the TLB entries for the specified page. + * + * page: page to invalidate + * flags: non-zero if we include the I TLB + */ + .align 5 +ENTRY(cpu_arm922_tlb_invalidate_page) + mov r3, #0 + mcr p15, 0, r3, c7, c10, 4 @ drain WB + teq r1, #0 + mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry + mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry + mov pc, lr + +/* =============================== PageTable ============================== */ + +/* + * cpu_arm922_set_pgd(pgd) + * + * Set the translation base pointer to be as described by pgd. + * + * pgd: new page tables + */ + .align 5 +ENTRY(cpu_arm922_set_pgd) + mov ip, #0 +#ifdef CONFIG_CPU_ARM922_WRITETHROUGH + /* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */ + mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache +#else +@ && 'Clean & Invalidate whole DCache' +@ && Re-written to use Index Ops. +@ && Uses registers r1, r3 and ip + + mov r1, #3 << 5 @ 4 segments +1: orr r3, r1, #63 << 26 @ 64 entries +2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index + subs r3, r3, #1 << 26 + bcs 2b @ entries 63 to 0 + subs r1, r1, #1 << 5 + bcs 1b @ segments 7 to 0 +#endif + mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache + mcr p15, 0, ip, c7, c10, 4 @ drain WB + mcr p15, 0, r0, c2, c0, 0 @ load page table pointer + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs + mov pc, lr + +/* + * cpu_arm922_set_pmd(pmdp, pmd) + * + * Set a level 1 translation table entry, and clean it out of + * any caches such that the MMUs can load it correctly. + * + * pmdp: pointer to PMD entry + * pmd: PMD value to store + */ + .align 5 +ENTRY(cpu_arm922_set_pmd) +#ifdef CONFIG_CPU_ARM922_WRITETHROUGH + eor r2, r1, #0x0a @ C & Section + tst r2, #0x0b + biceq r1, r1, #4 @ clear bufferable bit +#endif + str r1, [r0] + mcr p15, 0, r0, c7, c10, 1 @ clean D entry + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + +/* + * cpu_arm922_set_pte(ptep, pte) + * + * Set a PTE and flush it out + */ + .align 5 +ENTRY(cpu_arm922_set_pte) + str r1, [r0], #-1024 @ linux version + + eor r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY + + bic r2, r1, #0xff0 + bic r2, r2, #3 + orr r2, r2, #HPTE_TYPE_SMALL + + tst r1, #LPTE_USER | LPTE_EXEC @ User or Exec? + orrne r2, r2, #HPTE_AP_READ + + tst r1, #LPTE_WRITE | LPTE_DIRTY @ Write and Dirty? + orreq r2, r2, #HPTE_AP_WRITE + + tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young? + movne r2, #0 + +#ifdef CONFIG_CPU_ARM922_WRITETHROUGH + eor r3, r2, #0x0a @ C & small page? + tst r3, #0x0b + biceq r2, r2, #4 +#endif + str r2, [r0] @ hardware version + mov r0, r0 + mcr p15, 0, r0, c7, c10, 1 @ clean D entry + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + + +cpu_manu_name: + .asciz "ARM/ALTERA" +ENTRY(cpu_arm922_name) + .ascii "Arm922T" +#if defined(CONFIG_CPU_ARM922_CPU_IDLE) + .ascii "s" +#endif +#if defined(CONFIG_CPU_ARM922_I_CACHE_ON) + .ascii "i" +#endif +#if defined(CONFIG_CPU_ARM922_D_CACHE_ON) + .ascii "d" +#if defined(CONFIG_CPU_ARM922_WRITETHROUGH) + .ascii "(wt)" +#else + .ascii "(wb)" +#endif +#endif + .ascii "\0" + .align + + .section ".text.init", #alloc, #execinstr + +__arm922_setup: + mov r0, #0 + mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 + mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 + mcr p15, 0, r4, c2, c0 @ load page table pointer + mov r0, #0x1f @ Domains 0, 1 = client + mcr p15, 0, r0, c3, c0 @ load domain access register + mrc p15, 0, r0, c1, c0 @ get control register v4 +/* + * Clear out 'unwanted' bits (then put them in if we need them) + */ + @ VI ZFRS BLDP WCAM + bic r0, r0, #0x0e00 + bic r0, r0, #0x0002 + bic r0, r0, #0x000c + bic r0, r0, #0x1000 @ ...0 000. .... 000. +/* + * Turn on what we want + */ + orr r0, r0, #0x0031 + orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1 + +#ifdef CONFIG_CPU_ARM922_D_CACHE_ON + orr r0, r0, #0x0004 @ .... .... .... .1.. +#endif +#ifdef CONFIG_CPU_ARM922_I_CACHE_ON + orr r0, r0, #0x1000 @ ...1 .... .... .... +#endif + mov pc, lr + + .text + +/* + * Purpose : Function pointers used to access above functions - all calls + * come through these + */ + .type arm922_processor_functions, #object +arm922_processor_functions: + .word armv4t_early_abort + .word cpu_arm922_check_bugs + .word cpu_arm922_proc_init + .word cpu_arm922_proc_fin + .word cpu_arm922_reset + .word cpu_arm922_do_idle + + /* cache */ + .word cpu_arm922_cache_clean_invalidate_all + .word cpu_arm922_cache_clean_invalidate_range + .word cpu_arm922_flush_ram_page + + /* dcache */ + .word cpu_arm922_dcache_invalidate_range + .word cpu_arm922_dcache_clean_range + .word cpu_arm922_dcache_clean_page + .word cpu_arm922_dcache_clean_entry + + /* icache */ + .word cpu_arm922_icache_invalidate_range + .word cpu_arm922_icache_invalidate_page + + /* tlb */ + .word cpu_arm922_tlb_invalidate_all + .word cpu_arm922_tlb_invalidate_range + .word cpu_arm922_tlb_invalidate_page + + /* pgtable */ + .word cpu_arm922_set_pgd + .word cpu_arm922_set_pmd + .word cpu_arm922_set_pte + + /* misc */ + .word armv4_clear_user_page + .word armv4_copy_user_page + + .size arm922_processor_functions, . - arm922_processor_functions + + .type cpu_arm922_info, #object +cpu_arm922_info: + .long cpu_manu_name + .long cpu_arm922_name + .size cpu_arm922_info, . - cpu_arm922_info + + .type cpu_arch_name, #object +cpu_arch_name: + .asciz "armv4" + .size cpu_arch_name, . - cpu_arch_name + + .type cpu_elf_name, #object +cpu_elf_name: + .asciz "v4" + .size cpu_elf_name, . - cpu_elf_name + .align + + .section ".proc.info", #alloc, #execinstr + + .type __arm922_proc_info,#object +__arm922_proc_info: + .long 0x41009220 + .long 0xff00fff0 + .long 0x00000c1e @ mmuflags + b __arm922_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT + .long cpu_arm922_info + .long arm922_processor_functions + .size __arm922_proc_info, . - __arm922_proc_info diff -urN linux-2.5.2-pre8/arch/arm/mm/proc-arm926.S linux/arch/arm/mm/proc-arm926.S --- linux-2.5.2-pre8/arch/arm/mm/proc-arm926.S Fri Nov 9 13:58:02 2001 +++ linux/arch/arm/mm/proc-arm926.S Sat Jan 5 14:43:15 2002 @@ -56,35 +56,39 @@ * cpu_arm926_data_abort() * * obtain information about current aborted instruction + * Note: we read user space. This means we might cause a data + * abort here if the I-TLB and D-TLB aren't seeing the same + * picture. Unfortunately, this does happen. We live with it. * * Inputs: - * r0 = address of abort - * r1 = cpsr of abort + * r2 = address of abort + * r3 = cpsr of abort * * Returns: * r0 = address of abort * r1 != 0 if writing * r3 = FSR + * r4 = corrupted */ .align 5 ENTRY(cpu_arm926_data_abort) + mrc p15, 0, r0, c6, c0, 0 @ get FAR + mrc p15, 0, r4, c5, c0, 0 @ get FSR + tst r1, #1<<24 @ Check for Jbit (NE -> found) movne r1, #-1 @ Mark as writing bne 2f - tst r1, #1<<5 @ Check for Thumb-bit (NE -> found) - ldrneh r1, [r0] @ Read aborted Thumb instruction + tst r3, #1<<5 @ Check for Thumb-bit (NE -> found) + ldrneh r1, [r2] @ Read aborted Thumb instruction tstne r1, r1, lsr #12 @ C = bit 11 - ldreq r1, [r0] @ Read aborted ARM instruction + ldreq r1, [r2] @ Read aborted ARM instruction tsteq r1, r1, lsr #21 @ C = bit 20 sbc r1, r1, r1 @ r1 = C - 1 2: - mrc p15, 0, r3, c5, c0, 0 @ get FSR - and r3, r3, #255 - mrc p15, 0, r0, c6, c0, 0 @ get FAR - + and r3, r4, #255 mov pc, lr /* @@ -92,7 +96,7 @@ */ ENTRY(cpu_arm926_check_bugs) mrs ip, cpsr - bic ip, ip, #F_BIT + bic ip, ip, #PSR_F_BIT msr cpsr, ip mov pc, lr @@ -107,7 +111,7 @@ */ ENTRY(cpu_arm926_proc_fin) stmfd sp!, {lr} - mov ip, #F_BIT | I_BIT | SVC_MODE + mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE msr cpsr_c, ip bl cpu_arm926_cache_clean_invalidate_all mrc p15, 0, r0, c1, c0, 0 @ ctrl register @@ -601,7 +605,7 @@ */ .type arm926_processor_functions, #object arm926_processor_functions: - .word cpu_arm926_data_abort + .word armv5ej_early_abort .word cpu_arm926_check_bugs .word cpu_arm926_proc_init .word cpu_arm926_proc_fin @@ -632,6 +636,11 @@ .word cpu_arm926_set_pgd .word cpu_arm926_set_pmd .word cpu_arm926_set_pte + + /* misc */ + .word armv4_clear_user_page + .word armv4_copy_user_page + .size arm926_processor_functions, . - arm926_processor_functions .type cpu_arm926_info, #object diff -urN linux-2.5.2-pre8/arch/arm/mm/proc-sa110.S linux/arch/arm/mm/proc-sa110.S --- linux-2.5.2-pre8/arch/arm/mm/proc-sa110.S Thu Oct 25 13:53:46 2001 +++ linux/arch/arm/mm/proc-sa110.S Sat Jan 5 14:43:15 2002 @@ -22,6 +22,7 @@ #include #include #include +#include /* This is the maximum size of an area which will be flushed. If the area * is larger than this, then we flush the whole cache @@ -41,6 +42,10 @@ #define FLUSH_OFFSET 32768 .macro flush_110_dcache rd, ra, re + ldr \rd, =flush_base + ldr \ra, [\rd] + eor \ra, \ra, #FLUSH_OFFSET + str \ra, [\rd] add \re, \ra, #16384 @ only necessary for 16k 1001: ldr \rd, [\ra], #DCACHELINESIZE teq \re, \ra @@ -48,6 +53,10 @@ .endm .macro flush_1100_dcache rd, ra, re + ldr \rd, =flush_base + ldr \ra, [\rd] + eor \ra, \ra, #FLUSH_OFFSET + str \ra, [\rd] add \re, \ra, #8192 @ only necessary for 8k 1001: ldr \rd, [\ra], #DCACHELINESIZE teq \re, \ra @@ -62,40 +71,16 @@ .endm .data -Lclean_switch: .long 0 +flush_base: .long FLUSH_BASE .text - -/* - * cpu_sa110_data_abort() - * - * obtain information about current aborted instruction - * - * r0 = address of aborted instruction - * - * Returns: - * r0 = address of abort - * r1 != 0 if writing - * r3 = FSR - */ - .align 5 -ENTRY(cpu_sa110_data_abort) -ENTRY(cpu_sa1100_data_abort) - ldr r1, [r0] @ read aborted instruction - mrc p15, 0, r0, c6, c0, 0 @ get FAR - tst r1, r1, lsr #21 @ C = bit 20 - mrc p15, 0, r3, c5, c0, 0 @ get FSR - sbc r1, r1, r1 @ r1 = C - 1 - and r3, r3, #255 - mov pc, lr - /* * cpu_sa110_check_bugs() */ ENTRY(cpu_sa110_check_bugs) ENTRY(cpu_sa1100_check_bugs) mrs ip, cpsr - bic ip, ip, #F_BIT + bic ip, ip, #PSR_F_BIT msr cpsr, ip mov pc, lr @@ -113,7 +98,7 @@ */ ENTRY(cpu_sa110_proc_fin) stmfd sp!, {lr} - mov ip, #F_BIT | I_BIT | SVC_MODE + mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE msr cpsr_c, ip bl cpu_sa110_cache_clean_invalidate_all @ clean caches 1: mov r0, #0 @@ -126,7 +111,7 @@ ENTRY(cpu_sa1100_proc_fin) stmfd sp!, {lr} - mov ip, #F_BIT | I_BIT | SVC_MODE + mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE msr cpsr_c, ip bl cpu_sa1100_cache_clean_invalidate_all @ clean caches b 1b @@ -224,13 +209,6 @@ ENTRY(cpu_sa110_cache_clean_invalidate_all) mov r2, #1 cpu_sa110_cache_clean_invalidate_all_r2: - ldr r3, =Lclean_switch - ldr ip, =FLUSH_BASE - ldr r1, [r3] - ands r1, r1, #1 - eor r1, r1, #1 - str r1, [r3] - addne ip, ip, #FLUSH_OFFSET flush_110_dcache r3, ip, r1 mov ip, #0 teq r2, #0 @@ -242,13 +220,6 @@ ENTRY(cpu_sa1100_cache_clean_invalidate_all) mov r2, #1 cpu_sa1100_cache_clean_invalidate_all_r2: - ldr r3, =Lclean_switch - ldr ip, =FLUSH_BASE - ldr r1, [r3] - ands r1, r1, #1 - eor r1, r1, #1 - str r1, [r3] - addne ip, ip, #FLUSH_OFFSET flush_1100_dcache r3, ip, r1 mov ip, #0 teq r2, #0 @@ -501,13 +472,6 @@ */ .align 5 ENTRY(cpu_sa110_set_pgd) - ldr r3, =Lclean_switch - ldr ip, =FLUSH_BASE - ldr r2, [r3] - ands r2, r2, #1 - eor r2, r2, #1 - str r2, [r3] - addne ip, ip, #FLUSH_OFFSET flush_110_dcache r3, ip, r1 mov r1, #0 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache @@ -525,13 +489,6 @@ */ .align 5 ENTRY(cpu_sa1100_set_pgd) - ldr r3, =Lclean_switch - ldr ip, =FLUSH_BASE - ldr r2, [r3] - ands r2, r2, #1 - eor r2, r2, #1 - str r2, [r3] - addne ip, ip, #FLUSH_OFFSET flush_1100_dcache r3, ip, r1 mov ip, #0 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache @@ -568,19 +525,19 @@ ENTRY(cpu_sa1100_set_pte) str r1, [r0], #-1024 @ linux version - eor r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY + eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY bic r2, r1, #0xff0 bic r2, r2, #3 - orr r2, r2, #HPTE_TYPE_SMALL + orr r2, r2, #PTE_TYPE_SMALL - tst r1, #LPTE_USER | LPTE_EXEC @ User or Exec? - orrne r2, r2, #HPTE_AP_READ + tst r1, #L_PTE_USER | L_PTE_EXEC @ User or Exec? + orrne r2, r2, #PTE_SMALL_AP_URO_SRW - tst r1, #LPTE_WRITE | LPTE_DIRTY @ Write and Dirty? - orreq r2, r2, #HPTE_AP_WRITE + tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? + orreq r2, r2, #PTE_SMALL_AP_UNO_SRW - tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young? + tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? movne r2, #0 str r2, [r0] @ hardware version @@ -636,7 +593,7 @@ .type sa110_processor_functions, #object ENTRY(sa110_processor_functions) - .word cpu_sa110_data_abort + .word armv4_early_abort .word cpu_sa110_check_bugs .word cpu_sa110_proc_init .word cpu_sa110_proc_fin @@ -667,6 +624,11 @@ .word cpu_sa110_set_pgd .word cpu_sa110_set_pmd .word cpu_sa110_set_pte + + /* misc */ + .word armv4_clear_user_page + .word armv4_copy_user_page + .size sa110_processor_functions, . - sa110_processor_functions .type cpu_sa110_info, #object @@ -681,7 +643,7 @@ */ .type sa1100_processor_functions, #object ENTRY(sa1100_processor_functions) - .word cpu_sa1100_data_abort + .word armv4_early_abort .word cpu_sa1100_check_bugs .word cpu_sa1100_proc_init .word cpu_sa1100_proc_fin @@ -712,6 +674,11 @@ .word cpu_sa1100_set_pgd .word cpu_sa1100_set_pmd .word cpu_sa1100_set_pte + + /* misc */ + .word armv4_clear_user_page + .word armv4_copy_user_page + .size sa1100_processor_functions, . - sa1100_processor_functions cpu_sa1100_info: diff -urN linux-2.5.2-pre8/arch/arm/mm/proc-xscale.S linux/arch/arm/mm/proc-xscale.S --- linux-2.5.2-pre8/arch/arm/mm/proc-xscale.S Wed Dec 31 16:00:00 1969 +++ linux/arch/arm/mm/proc-xscale.S Sat Jan 5 14:43:15 2002 @@ -0,0 +1,812 @@ +/* + * linux/arch/arm/mm/proc-xscale.S + * + * Author: Nicolas Pitre + * Created: November 2000 + * Copyright: (C) 2000, 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * MMU functions for the Intel XScale CPUs + * + * 2001 Aug 21: + * some contributions by Brett Gaines + * Copyright 2001 by Intel Corp. + * + * 2001 Sep 08: + * Completely revisited, many important fixes + * Nicolas Pitre + */ + +#include +#include +#include +#include +#include +#include + +/* + * This is the maximum size of an area which will be flushed. If the area + * is larger than this, then we flush the whole cache + */ +#define MAX_AREA_SIZE 32768 + +/* + * the cache line size of the I and D cache + */ +#define CACHELINESIZE 32 + +/* + * the size of the data cache + */ +#define CACHESIZE 32768 + +/* + * and the page size + */ +#define PAGESIZE 4096 + +/* + * Virtual address used to allocate the cache when flushed + * + * This must be an address range which is _never_ used. It should + * apparently have a mapping in the corresponding page table for + * compatibility with future CPUs that _could_ require it. For instance we + * don't care. + * + * This must be aligned on a 2*CACHESIZE boundary. The code selects one of + * the 2 areas in alternance each time the clean_d_cache macro is used. + * Without this the XScale core exhibits cache eviction problems and no one + * knows why. + * + * Reminder: the vector table is located at 0xffff0000-0xffff0fff. + */ +#define CLEAN_ADDR 0xfffe0000 + +/* + * This macro is used to wait for a CP15 write and is needed + * when we have to ensure that the last operation to the co-pro + * was completed before continuing with operation. + */ + .macro cpwait, rd + mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 + mov \rd, \rd @ wait for completion + sub pc, pc, #4 @ flush instruction pipeline + .endm + + .macro cpwait_ret, lr, rd + mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 + sub pc, \lr, \rd, LSR #32 @ wait for completion and + @ flush instruction pipeline + .endm + +/* + * This macro cleans the entire dcache using line allocate. + * The main loop has been unrolled to reduce loop overhead. + * rd and rs are two scratch registers. + */ + .macro clean_d_cache, rd, rs + ldr \rs, =clean_addr + ldr \rd, [\rs] + eor \rd, \rd, #CACHESIZE + str \rd, [\rs] + add \rs, \rd, #CACHESIZE +1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line + add \rd, \rd, #CACHELINESIZE + mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line + add \rd, \rd, #CACHELINESIZE + mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line + add \rd, \rd, #CACHELINESIZE + mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line + add \rd, \rd, #CACHELINESIZE + teq \rd, \rs + bne 1b + .endm + + .data +clean_addr: .word CLEAN_ADDR + + .text + +/* + * cpu_xscale_check_bugs() + */ +ENTRY(cpu_xscale_check_bugs) + mrs ip, cpsr + bic ip, ip, #PSR_F_BIT + msr cpsr, ip + mov pc, lr + +/* + * cpu_xscale_proc_init() + * + * Nothing too exciting at the moment + */ +ENTRY(cpu_xscale_proc_init) + mov pc, lr + +/* + * cpu_xscale_proc_fin() + */ +ENTRY(cpu_xscale_proc_fin) + str lr, [sp, #-4]! + mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE + msr cpsr_c, r0 + mrc p15, 0, r0, c1, c0, 0 @ ctrl register + bic r0, r0, #0x1800 @ ...IZ........... + bic r0, r0, #0x0006 @ .............CA. + mcr p15, 0, r0, c1, c0, 0 @ disable caches + bl cpu_xscale_cache_clean_invalidate_all @ clean caches + ldr pc, [sp], #4 + +/* + * cpu_xscale_reset(loc) + * + * Perform a soft reset of the system. Put the CPU into the + * same state as it would be if it had been reset, and branch + * to what would be the reset vector. + * + * loc: location to jump to for soft reset + */ + .align 5 +ENTRY(cpu_xscale_reset) + mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE + msr cpsr_c, r1 @ reset CPSR + mrc p15, 0, r1, c1, c0, 0 @ ctrl register + bic r1, r1, #0x0086 @ ........B....CA. + bic r1, r1, #0x1900 @ ...IZ..S........ + mcr p15, 0, r1, c1, c0, 0 @ ctrl register + mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB + bic r1, r1, #0x0001 @ ...............M + mcr p15, 0, r1, c1, c0, 0 @ ctrl register + @ CAUTION: MMU turned off from this point. We count on the pipeline + @ already containing those two last instructions to survive. + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs + mov pc, r0 + +/* + * cpu_xscale_do_idle(type) + * + * Cause the processor to idle + * + * type: + * 0 = slow idle + * 1 = fast idle + * 2 = switch to slow processor clock + * 3 = switch to fast processor clock + * + * For now we do nothing but go to idle mode for every case + * + * XScale supports clock switching, but using idle mode support + * allows external hardware to react to system state changes. + */ + .align 5 + +ENTRY(cpu_xscale_do_idle) + mov r0, #1 + mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE + mov pc, lr + +/* ================================= CACHE ================================ */ + +/* + * cpu_xscale_cache_clean_invalidate_all (void) + * + * clean and invalidate all cache lines + * + * Note: + * 1. We should preserve r0 at all times. + * 2. Even if this function implies cache "invalidation" by its name, + * we don't need to actually use explicit invalidation operations + * since the goal is to discard all valid references from the cache + * and the cleaning of it already has that effect. + * 3. Because of 2 above and the fact that kernel space memory is always + * coherent across task switches there is no need to worry about + * inconsistencies due to interrupts, ence no irq disabling. + */ + .align 5 +ENTRY(cpu_xscale_cache_clean_invalidate_all) + mov r2, #1 +cpu_xscale_cache_clean_invalidate_all_r2: + clean_d_cache r0, r1 + teq r2, #0 + mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mov pc, lr + +/* + * cpu_xscale_cache_clean_invalidate_range(start, end, flags) + * + * clean and invalidate all cache lines associated with this area of memory + * + * start: Area start address + * end: Area end address + * flags: nonzero for I cache as well + */ + .align 5 +ENTRY(cpu_xscale_cache_clean_invalidate_range) + bic r0, r0, #CACHELINESIZE - 1 @ round down to cache line + sub r3, r1, r0 + cmp r3, #MAX_AREA_SIZE + bhi cpu_xscale_cache_clean_invalidate_all_r2 +1: mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line + mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line + add r0, r0, #CACHELINESIZE + cmp r0, r1 + blo 1b + teq r2, #0 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + moveq pc, lr + sub r0, r0, r3 +1: mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache line + add r0, r0, #CACHELINESIZE + cmp r0, r1 + blo 1b + mcr p15, 0, ip, c7, c5, 6 @ Invalidate BTB + mov pc, lr + +/* + * cpu_xscale_flush_ram_page(page) + * + * clean all cache lines associated with this memory page + * + * page: page to clean + */ + .align 5 +ENTRY(cpu_xscale_flush_ram_page) + mov r1, #PAGESIZE +1: mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line + add r0, r0, #CACHELINESIZE + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line + add r0, r0, #CACHELINESIZE + subs r1, r1, #2 * CACHELINESIZE + bne 1b + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mov pc, lr + +/* ================================ D-CACHE =============================== */ + +/* + * cpu_xscale_dcache_invalidate_range(start, end) + * + * throw away all D-cached data in specified region without an obligation + * to write them back. Note however that on XScale we must clean all + * entries also due to hardware errata (80200 A0 & A1 only). + * + * start: virtual start address + * end: virtual end address + */ + .align 5 +ENTRY(cpu_xscale_dcache_invalidate_range) + mrc p15, 0, r2, c0, c0, 0 @ Read part no. + eor r2, r2, #0x69000000 + eor r2, r2, #0x00052000 @ 80200 XX part no. + bics r2, r2, #0x1 @ Clear LSB in revision field + moveq r2, #0 + beq cpu_xscale_cache_clean_invalidate_range @ An 80200 A0 or A1 + + tst r0, #CACHELINESIZE - 1 + mcrne p15, 0, r0, c7, c10, 1 @ Clean D cache line + tst r1, #CACHELINESIZE - 1 + mcrne p15, 0, r1, c7, c10, 1 @ Clean D cache line + bic r0, r0, #CACHELINESIZE - 1 @ round down to cache line +1: mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line + add r0, r0, #CACHELINESIZE + cmp r0, r1 + blo 1b + mov pc, lr + +/* + * cpu_xscale_dcache_clean_range(start, end) + * + * For the specified virtual address range, ensure that all caches contain + * clean data, such that peripheral accesses to the physical RAM fetch + * correct data. + * + * start: virtual start address + * end: virtual end address + */ + .align 5 +ENTRY(cpu_xscale_dcache_clean_range) + bic r0, r0, #CACHELINESIZE - 1 + sub r2, r1, r0 + cmp r2, #MAX_AREA_SIZE + movhi r2, #0 + bhi cpu_xscale_cache_clean_invalidate_all_r2 + +1: mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line + add r0, r0, #CACHELINESIZE + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line + add r0, r0, #CACHELINESIZE + cmp r0, r1 + blo 1b + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mov pc, lr + +/* + * cpu_xscale_clean_dcache_page(page) + * + * Cleans a single page of dcache so that if we have any future aliased + * mappings, they will be consistent at the time that they are created. + * + * Note: + * 1. we don't need to flush the write buffer in this case. [really? -Nico] + * 2. we don't invalidate the entries since when we write the page + * out to disk, the entries may get reloaded into the cache. + */ + .align 5 +ENTRY(cpu_xscale_dcache_clean_page) + mov r1, #PAGESIZE +1: mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line + add r0, r0, #CACHELINESIZE + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line + add r0, r0, #CACHELINESIZE + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line + add r0, r0, #CACHELINESIZE + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line + add r0, r0, #CACHELINESIZE + subs r1, r1, #4 * CACHELINESIZE + bne 1b + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mov pc, lr + +/* + * cpu_xscale_dcache_clean_entry(addr) + * + * Clean the specified entry of any caches such that the MMU + * translation fetches will obtain correct data. + * + * addr: cache-unaligned virtual address + */ + .align 5 +ENTRY(cpu_xscale_dcache_clean_entry) + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mov pc, lr + +/* ================================ I-CACHE =============================== */ + +/* + * cpu_xscale_icache_invalidate_range(start, end) + * + * invalidate a range of virtual addresses from the Icache + * + * start: virtual start address + * end: virtual end address + * + * Note: This is vaguely defined as supposed to bring the dcache and the + * icache in sync by the way this function is used. + */ + .align 5 +ENTRY(cpu_xscale_icache_invalidate_range) + bic r0, r0, #CACHELINESIZE - 1 +1: mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line + mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache line + add r0, r0, #CACHELINESIZE + cmp r0, r1 + blo 1b + mcr p15, 0, ip, c7, c5, 6 @ Invalidate BTB + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mov pc, lr + +/* + * cpu_xscale_icache_invalidate_page(page) + * + * invalidate all Icache lines associated with this area of memory + * + * page: page to invalidate + */ + .align 5 +ENTRY(cpu_xscale_icache_invalidate_page) + mov r1, #PAGESIZE +1: mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache line + add r0, r0, #CACHELINESIZE + mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache line + add r0, r0, #CACHELINESIZE + mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache line + add r0, r0, #CACHELINESIZE + mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache line + add r0, r0, #CACHELINESIZE + subs r1, r1, #4 * CACHELINESIZE + bne 1b + mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB + mov pc, lr + +/* ================================ CACHE LOCKING============================ + * + * The XScale MicroArchitecture implements support for locking entries into + * the data and instruction cache. The following functions implement the core + * low level instructions needed to accomplish the locking. The developer's + * manual states that the code that performs the locking must be in non-cached + * memory. To accomplish this, the code in xscale-cache-lock.c copies the + * following functions from the cache into a non-cached memory region that + * is allocated through consistent_alloc(). + * + */ + .align 5 +/* + * xscale_icache_lock + * + * r0: starting address to lock + * r1: end address to lock + */ +ENTRY(xscale_icache_lock) + +iLockLoop: + bic r0, r0, #CACHELINESIZE - 1 + mcr p15, 0, r0, c9, c1, 0 @ lock into cache + cmp r0, r1 @ are we done? + add r0, r0, #CACHELINESIZE @ advance to next cache line + bls iLockLoop + mov pc, lr + +/* + * xscale_icache_unlock + */ +ENTRY(xscale_icache_unlock) + mcr p15, 0, r0, c9, c1, 1 @ Unlock icache + mov pc, lr + +/* + * xscale_dcache_lock + * + * r0: starting address to lock + * r1: end address to lock + */ +ENTRY(xscale_dcache_lock) + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mov r2, #1 + mcr p15, 0, r2, c9, c2, 0 @ Put dcache in lock mode + cpwait ip @ Wait for completion + + mrs r2, cpsr + orr r3, r2, #PSR_F_BIT | PSR_I_BIT +dLockLoop: + msr cpsr_c, r3 + mcr p15, 0, r0, c7, c10, 1 @ Write back line if it is dirty + mcr p15, 0, r0, c7, c6, 1 @ Flush/invalidate line + msr cpsr_c, r2 + ldr ip, [r0], #CACHELINESIZE @ Preload 32 bytes into cache from + @ location [r0]. Post-increment + @ r3 to next cache line + cmp r0, r1 @ Are we done? + bls dLockLoop + + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mov r2, #0 + mcr p15, 0, r2, c9, c2, 0 @ Get out of lock mode + cpwait_ret lr, ip + +/* + * xscale_dcache_unlock + */ +ENTRY(xscale_dcache_unlock) + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mcr p15, 0, ip, c9, c2, 1 @ Unlock cache + mov pc, lr + +/* + * Needed to determine the length of the code that needs to be copied. + */ + .align 5 +ENTRY(xscale_cache_dummy) + mov pc, lr + +/* ================================== TLB ================================= */ + +/* + * cpu_xscale_tlb_invalidate_all() + * + * Invalidate all TLB entries + */ + .align 5 +ENTRY(cpu_xscale_tlb_invalidate_all) + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs + cpwait_ret lr, ip + +/* + * cpu_xscale_tlb_invalidate_range(start, end) + * + * invalidate TLB entries covering the specified range + * + * start: range start address + * end: range end address + */ + .align 5 +ENTRY(cpu_xscale_tlb_invalidate_range) + bic r0, r0, #(PAGESIZE - 1) & 0x00ff + bic r0, r0, #(PAGESIZE - 1) & 0xff00 + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer +1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry + mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry + add r0, r0, #PAGESIZE + cmp r0, r1 + blo 1b + cpwait_ret lr, ip + +/* + * cpu_xscale_tlb_invalidate_page(page, flags) + * + * invalidate the TLB entries for the specified page. + * + * page: page to invalidate + * flags: non-zero if we include the I TLB + */ + .align 5 +ENTRY(cpu_xscale_tlb_invalidate_page) + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + teq r1, #0 + mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry + mcrne p15, 0, r3, c8, c5, 1 @ invalidate I TLB entry + cpwait_ret lr, ip + +/* ================================ TLB LOCKING============================== + * + * The XScale MicroArchitecture implements support for locking entries into + * the Instruction and Data TLBs. The following functions provide the + * low level support for supporting these under Linux. xscale-lock.c + * implements some higher level management code. Most of the following + * is taken straight out of the Developer's Manual. + */ + +/* + * Lock I-TLB entry + * + * r0: Virtual address to translate and lock + */ + .align 5 +ENTRY(xscale_itlb_lock) + mrs r2, cpsr + orr r3, r2, #PSR_F_BIT | PSR_I_BIT + msr cpsr_c, r3 @ Disable interrupts + mcr p15, 0, r0, c8, c5, 1 @ Invalidate I-TLB entry + mcr p15, 0, r0, c10, c4, 0 @ Translate and lock + msr cpsr_c, r2 @ Restore interrupts + cpwait_ret lr, ip + +/* + * Lock D-TLB entry + * + * r0: Virtual address to translate and lock + */ + .align 5 +ENTRY(xscale_dtlb_lock) + mrs r2, cpsr + orr r3, r2, #PSR_F_BIT | PSR_I_BIT + msr cpsr_c, r3 @ Disable interrupts + mcr p15, 0, r0, c8, c6, 1 @ Invalidate D-TLB entry + mcr p15, 0, r0, c10, c8, 0 @ Translate and lock + msr cpsr_c, r2 @ Restore interrupts + cpwait_ret lr, ip + +/* + * Unlock all I-TLB entries + */ + .align 5 +ENTRY(xscale_itlb_unlock) + mcr p15, 0, ip, c10, c4, 1 @ Unlock I-TLB + mcr p15, 0, ip, c8, c5, 0 @ Invalidate I-TLB + cpwait_ret lr, ip + +/* + * Unlock all D-TLB entries + */ +ENTRY(xscale_dtlb_unlock) + mcr p15, 0, ip, c10, c8, 1 @ Unlock D-TBL + mcr p15, 0, ip, c8, c6, 0 @ Invalidate D-TLB + cpwait_ret lr, ip + +/* =============================== PageTable ============================== */ + +#define PMD_CACHE_WRITE_ALLOCATE 0 +#define PTE_CACHE_WRITE_ALLOCATE 0 + +/* + * cpu_xscale_set_pgd(pgd) + * + * Set the translation base pointer to be as described by pgd. + * + * pgd: new page tables + */ + .align 5 +ENTRY(cpu_xscale_set_pgd) + clean_d_cache r1, r2 + mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mcr p15, 0, r0, c2, c0, 0 @ load page table pointer + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs + cpwait_ret lr, ip + +/* + * cpu_xscale_set_pmd(pmdp, pmd) + * + * Set a level 1 translation table entry, and clean it out of + * any caches such that the MMUs can load it correctly. + * + * pmdp: pointer to PMD entry + * pmd: PMD value to store + */ + .align 5 +ENTRY(cpu_xscale_set_pmd) +#if PMD_CACHE_WRITE_ALLOCATE + and r2, r1, #PMD_TYPE_MASK|PMD_SECT_CACHEABLE|PMD_SECT_BUFFERABLE + cmp r2, #PMD_TYPE_SECT|PMD_SECT_CACHEABLE|PMD_SECT_BUFFERABLE + orreq r1, r1, #PMD_SECT_TEX(1) +#endif + str r1, [r0] + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mov pc, lr + +/* + * cpu_xscale_set_pte(ptep, pte) + * + * Set a PTE and flush it out + */ + .align 5 +ENTRY(cpu_xscale_set_pte) + str r1, [r0], #-1024 @ linux version + + bic r2, r1, #0xff0 + orr r2, r2, #PTE_TYPE_EXT @ extended page + + eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY + + tst r1, #L_PTE_USER | L_PTE_EXEC @ User or Exec? + orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w + + tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? + orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w + @ combined with user -> user r/w + +#if PTE_CACHE_WRITE_ALLOCATE + tst r1, #L_PTE_CACHEABLE @ cacheable? + orrne r2, r2, #PTE_EXT_TEX(1) +#else + eor r1, r1, #L_PTE_CACHEABLE + tst r1, #L_PTE_CACHEABLE | L_PTE_BUFFERABLE @ C = 1 B = 0? + orreq r2, r2, #PTE_EXT_TEX(1) @ yes -> set X (minicache) +#endif + + tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? + movne r2, #0 @ no -> fault + + str r2, [r0] @ hardware version + mov r0, r0 + mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mov pc, lr + + + .ltorg + +cpu_manu_name: + .asciz "Intel" + +cpu_80200_name: + .asciz "XScale-80200" + +cpu_cotulla_name: + .asciz "XScale-Cotulla" + + .align + + .section ".text.init", #alloc, #execinstr + +__xscale_setup: + mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE + msr cpsr_c, r0 + mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB + mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer + mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs + mcr p15, 0, r4, c2, c0, 0 @ load page table pointer + mov r0, #0x1f @ Domains 0, 1 = client + mcr p15, 0, r0, c3, c0, 0 @ load domain access register + mrc p15, 0, r0, c1, c0, 0 @ get control register + bic r0, r0, #0x0200 @ .... ..R. .... .... + bic r0, r0, #0x0082 @ .... .... B... ..A. + orr r0, r0, #0x0005 @ .... .... .... .C.M + orr r0, r0, #0x3900 @ ..VI Z..S .... .... + mov pc, lr + + .text + +/* + * Purpose : Function pointers used to access above functions - all calls + * come through these + */ + + .type xscale_processor_functions, #object +ENTRY(xscale_processor_functions) + .word armv4t_early_abort + .word cpu_xscale_check_bugs + .word cpu_xscale_proc_init + .word cpu_xscale_proc_fin + .word cpu_xscale_reset + .word cpu_xscale_do_idle + + /* cache */ + .word cpu_xscale_cache_clean_invalidate_all + .word cpu_xscale_cache_clean_invalidate_range + .word cpu_xscale_flush_ram_page + + /* dcache */ + .word cpu_xscale_dcache_invalidate_range + .word cpu_xscale_dcache_clean_range + .word cpu_xscale_dcache_clean_page + .word cpu_xscale_dcache_clean_entry + + /* icache */ + .word cpu_xscale_icache_invalidate_range + .word cpu_xscale_icache_invalidate_page + + /* tlb */ + .word cpu_xscale_tlb_invalidate_all + .word cpu_xscale_tlb_invalidate_range + .word cpu_xscale_tlb_invalidate_page + + /* pgtable */ + .word cpu_xscale_set_pgd + .word cpu_xscale_set_pmd + .word cpu_xscale_set_pte + + /* misc */ + .word armv5te_clear_user_page + .word armv5te_copy_user_page + + .size xscale_processor_functions, . - xscale_processor_functions + + .type cpu_80200_info, #object +cpu_80200_info: + .long cpu_manu_name + .long cpu_80200_name + .size cpu_80200_info, . - cpu_80200_info + + .type cpu_cotulla_info, #object +cpu_cotulla_info: + .long cpu_manu_name + .long cpu_cotulla_name + .size cpu_cotulla_info, . - cpu_cotulla_info + + .type cpu_arch_name, #object +cpu_arch_name: + .asciz "armv5" + .size cpu_arch_name, . - cpu_arch_name + + .type cpu_elf_name, #object +cpu_elf_name: + .asciz "v5" + .size cpu_elf_name, . - cpu_elf_name + .align + + .section ".proc.info", #alloc, #execinstr + + .type __80200_proc_info,#object +__80200_proc_info: + .long 0x69052000 + .long 0xfffffff0 + .long 0x00000c0e + b __xscale_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP + .long cpu_80200_info + .long xscale_processor_functions + .size __80200_proc_info, . - __80200_proc_info + + .type __cotulla_proc_info,#object +__cotulla_proc_info: + .long 0x69052100 + .long 0xfffffff0 + .long 0x00000c0e + b __xscale_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP + .long cpu_cotulla_info + .long xscale_processor_functions + .size __cotulla_proc_info, . - __cotulla_proc_info + diff -urN linux-2.5.2-pre8/arch/arm/nwfpe/entry26.S linux/arch/arm/nwfpe/entry26.S --- linux-2.5.2-pre8/arch/arm/nwfpe/entry26.S Wed Apr 11 19:02:27 2001 +++ linux/arch/arm/nwfpe/entry26.S Sat Jan 5 14:43:15 2002 @@ -26,7 +26,7 @@ It is called from the kernel with code similar to this: mov fp, #0 - teqp pc, #I_BIT | MODE_SVC + teqp pc, #PSR_I_BIT | MODE_SVC ldr r4, .LC2 ldr pc, [r4] @ Call FP module USR entry point diff -urN linux-2.5.2-pre8/arch/arm/nwfpe/fpa11.c linux/arch/arm/nwfpe/fpa11.c --- linux-2.5.2-pre8/arch/arm/nwfpe/fpa11.c Sat Jan 5 14:43:12 2002 +++ linux/arch/arm/nwfpe/fpa11.c Sat Jan 5 14:43:15 2002 @@ -139,7 +139,6 @@ { unsigned int nRc = 1, code; unsigned long flags; - FPA11 *fpa11; save_flags(flags); sti(); diff -urN linux-2.5.2-pre8/arch/arm/tools/Makefile linux/arch/arm/tools/Makefile --- linux-2.5.2-pre8/arch/arm/tools/Makefile Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/tools/Makefile Sat Jan 5 14:43:15 2002 @@ -15,13 +15,17 @@ # what we want. We do this in several stages so make picks up on # any errors that occur along the way. -$(TOPDIR)/include/asm-arm/constants.h: constants-hdr getconstants.c - $(CC) $(CFLAGS) -S -o - getconstants.c > $@.tmp.1 +constants.h: constants-hdr getconstants.c + $(CC) $(CFLAGS) -S -o $@.tmp.1 getconstants.c sed 's/^\(#define .* \)[#$$]\(.*\)/\1\2/;/^#define/!d' $@.tmp.1 > $@.tmp.2 - cat constants-hdr $@.tmp.2 > $@.tmp - cmp $@.tmp $@ >/dev/null 2>&1 || mv $@.tmp $@ + cat constants-hdr $@.tmp.2 > $@ $(RM) $@.tmp* +# Only update include/asm-arm/constants.h when it has actually changed. + +$(TOPDIR)/include/asm-arm/constants.h: constants.h + cmp constants.h $@ >/dev/null 2>&1 || cp -p constants.h $@ + # Build our dependencies, and then generate the constants and # mach-types header files. If we do it now, mkdep will pick # the dependencies up later on when it runs through the other @@ -29,7 +33,7 @@ dep: $(TOPDIR)/scripts/mkdep $(CFLAGS) $(EXTRA_CFLAGS) -- getconstants.c |\ - sed s,getconstants.o,$(TOPDIR)/include/asm-arm/constants.h, > .depend + sed s,getconstants.o,constants.h, > .depend $(MAKE) all .PHONY: all dep diff -urN linux-2.5.2-pre8/arch/arm/tools/getconstants.c linux/arch/arm/tools/getconstants.c --- linux-2.5.2-pre8/arch/arm/tools/getconstants.c Thu Oct 11 09:04:57 2001 +++ linux/arch/arm/tools/getconstants.c Sat Jan 5 14:43:15 2002 @@ -18,10 +18,17 @@ * Make sure that the compiler and target are compatible. */ #if defined(__APCS_32__) && defined(CONFIG_CPU_26) -#error Your compiler targets APCS-32 but this kernel requires APCS-26 +#error Sorry, your compiler targets APCS-32 but this kernel requires APCS-26 #endif #if defined(__APCS_26__) && defined(CONFIG_CPU_32) -#error Your compiler targets APCS-26 but this kernel requires APCS-32 +#error Sorry, your compiler targets APCS-26 but this kernel requires APCS-32 +#endif +#if __GNUC__ < 2 || (__GNUC__ == 2 && __GNUC_MINOR__ < 95) +#error Sorry, your compiler is known to miscompile kernels. Only use gcc 2.95.3 and later. +#endif +#if __GNUC__ == 2 && __GNUC_MINOR__ == 95 +/* shame we can't detect the .1 or .2 releases */ +#warning GCC 2.95.2 and earlier miscompiles kernels. #endif #define OFF_TSK(n) (unsigned long)&(((struct task_struct *)0)->n) diff -urN linux-2.5.2-pre8/arch/arm/tools/mach-types linux/arch/arm/tools/mach-types --- linux-2.5.2-pre8/arch/arm/tools/mach-types Fri Nov 9 13:58:02 2001 +++ linux/arch/arm/tools/mach-types Sat Jan 5 14:43:15 2002 @@ -6,7 +6,7 @@ # To add an entry into this database, please see Documentation/arm/README, # or contact rmk@arm.linux.org.uk # -# Last update: Fri Oct 26 17:37:13 2001 +# Last update: Fri Jan 4 10:27:21 2002 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -137,3 +137,28 @@ elroy SA1100_ELROY ELROY 126 gms720 ARCH_GMS720 GMS720 127 s24x ARCH_S24X S24X 128 +jtel_clep7312 ARCH_JTEL_CLEP7312 JTEL_CLEP7312 129 +cx821xx ARCH_CX821XX CX821XX 130 +edb7312 ARCH_EDB7312 EDB7312 131 +bsa1110 SA1100_BSA1110 BSA1110 132 +powerpin ARCH_POWERPIN POWERPIN 133 +openarm ARCH_OPENARM OPENARM 134 +whitechapel SA1100_WHITECHAPEL WHITECHAPEL 135 +h3100 SA1100_H3100 H3100 136 +h3800 SA1100_H3800 H3800 137 +blue_v1 ARCH_BLUE_V1 BLUE_V1 138 +xscale_cerf ARCH_XSCALE_CERF XSCALE_CERF 139 +arm7tevb ARCH_ARM7TEVB ARM7TEVB 140 +d7400 ARCH_D7400 D7400 141 +piranha ARCH_PIRANHA PIRANHA 142 +sbcamelot SA1100_SBCAMELOT SBCAMELOT 143 +kings SA1100_KINGS KINGS 144 +smdk2400 ARCH_SMDK2400 SMDK2400 145 +collie ARCH_COLLIE COLLIE 146 +idr ARCH_IDR IDR 147 +badge4 SA1100_BADGE4 BADGE4 148 +webnet ARCH_WEBNET WEBNET 149 +d7300 SA1100_D7300 D7300 150 +cep SA1100_CEP CEP 151 +fortunet ARCH_FORTUNET FORTUNET 152 +vc547x ARCH_VC547X VC547X 153 diff -urN linux-2.5.2-pre8/arch/arm/vmlinux-armo.lds.in linux/arch/arm/vmlinux-armo.lds.in --- linux-2.5.2-pre8/arch/arm/vmlinux-armo.lds.in Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/vmlinux-armo.lds.in Sat Jan 5 14:43:15 2002 @@ -48,7 +48,6 @@ *(.text) *(.fixup) *(.gnu.warning) - *(.text.lock) /* out-of-line lock text */ *(.rodata) *(.rodata.*) *(.glue_7) diff -urN linux-2.5.2-pre8/arch/arm/vmlinux-armv.lds.in linux/arch/arm/vmlinux-armv.lds.in --- linux-2.5.2-pre8/arch/arm/vmlinux-armv.lds.in Sun Aug 12 11:13:59 2001 +++ linux/arch/arm/vmlinux-armv.lds.in Sat Jan 5 14:43:15 2002 @@ -43,7 +43,6 @@ *(.text) *(.fixup) *(.gnu.warning) - *(.text.lock) /* out-of-line lock text */ *(.rodata) *(.rodata.*) *(.glue_7) diff -urN linux-2.5.2-pre8/drivers/cdrom/sbpcd.c linux/drivers/cdrom/sbpcd.c --- linux-2.5.2-pre8/drivers/cdrom/sbpcd.c Sat Dec 8 20:02:47 2001 +++ linux/drivers/cdrom/sbpcd.c Sat Jan 5 14:43:15 2002 @@ -2057,7 +2057,7 @@ static int sbpcd_select_speed(struct cdrom_device_info *cdi, int speed) { - int i = MINOR(cdi->dev); + int i = minor(cdi->dev); if (i != d) switch_drive(i); @@ -2095,7 +2095,7 @@ static int sbpcd_reset(struct cdrom_device_info *cdi) { - int i = MINOR(cdi->dev); + int i = minor(cdi->dev); if (i != d) switch_drive(i); @@ -2376,7 +2376,7 @@ { int i; int retval=0; - i = MINOR(cdi->dev); + i = minor(cdi->dev); switch_drive(i); /* DUH! --AJK */ if(D_S[d].CD_changed != 0xFF) { @@ -4061,13 +4061,13 @@ msg(DBG_000,"Drive Status: busy =%d.\n", st_busy); #if 0 - if (!(D_S[MINOR(cdi->dev)].status_bits & p_door_closed)) return CDS_TRAY_OPEN; - if (D_S[MINOR(cdi->dev)].status_bits & p_disk_ok) return CDS_DISC_OK; - if (D_S[MINOR(cdi->dev)].status_bits & p_disk_in) return CDS_DRIVE_NOT_READY; + if (!(D_S[minor(cdi->dev)].status_bits & p_door_closed)) return CDS_TRAY_OPEN; + if (D_S[minor(cdi->dev)].status_bits & p_disk_ok) return CDS_DISC_OK; + if (D_S[minor(cdi->dev)].status_bits & p_disk_in) return CDS_DRIVE_NOT_READY; return CDS_NO_DISC; #else - if (D_S[MINOR(cdi->dev)].status_bits & p_spinning) return CDS_DISC_OK; + if (D_S[minor(cdi->dev)].status_bits & p_spinning) return CDS_DISC_OK; /* return CDS_TRAY_OPEN; */ return CDS_NO_DISC; @@ -4203,8 +4203,8 @@ static int sbpcd_get_last_session(struct cdrom_device_info *cdi, struct cdrom_multisession *ms_infp) { ms_infp->addr_format = CDROM_LBA; - ms_infp->addr.lba = D_S[MINOR(cdi->dev)].lba_multi; - if (D_S[MINOR(cdi->dev)].f_multisession) + ms_infp->addr.lba = D_S[minor(cdi->dev)].lba_multi; + if (D_S[minor(cdi->dev)].f_multisession) ms_infp->xa_flag=1; /* valid redirection address */ else ms_infp->xa_flag=0; /* invalid redirection address */ @@ -4223,8 +4223,8 @@ int i; msg(DBG_IO2,"ioctl(%d, 0x%08lX, 0x%08lX)\n", - MINOR(cdi->dev), cmd, arg); - i=MINOR(cdi->dev); + minor(cdi->dev), cmd, arg); + i=minor(cdi->dev); if ((i<0) || (i>=NR_SBPCD) || (D_S[i].drv_id==-1)) { msg(DBG_INF, "ioctl: bad device: %04X\n", cdi->dev); @@ -4533,9 +4533,9 @@ case BLKRASET: if(!capable(CAP_SYS_ADMIN)) RETURN_UP(-EACCES); - if(!(cdi->dev)) RETURN_UP(-EINVAL); + if(kdev_none(cdi->dev)) RETURN_UP(-EINVAL); if(arg > 0xff) RETURN_UP(-EINVAL); - read_ahead[MAJOR(cdi->dev)] = arg; + read_ahead[major(cdi->dev)] = arg; RETURN_UP(0); default: msg(DBG_IOC,"ioctl: unknown function request %04X\n", cmd); @@ -4549,8 +4549,8 @@ int i, st, j; msg(DBG_IO2,"ioctl(%d, 0x%08lX, 0x%08p)\n", - MINOR(cdi->dev), cmd, arg); - i=MINOR(cdi->dev); + minor(cdi->dev), cmd, arg); + i=minor(cdi->dev); if ((i<0) || (i>=NR_SBPCD) || (D_S[i].drv_id==-1)) { msg(DBG_INF, "ioctl: bad device: %04X\n", cdi->dev); @@ -4930,7 +4930,7 @@ sbpcd_end_request(req, 0); if (req -> sector == -1) sbpcd_end_request(req, 0); - spin_unlock_irq(&q->queue_lock); + spin_unlock_irq(q->queue_lock); down(&ioctl_read_sem); if (req->cmd != READ) @@ -4938,7 +4938,7 @@ msg(DBG_INF, "bad cmd %d\n", req->cmd); goto err_done; } - i = MINOR(req->rq_dev); + i = minor(req->rq_dev); if ( (i<0) || (i>=NR_SBPCD) || (D_S[i].drv_id==-1)) { msg(DBG_INF, "do_request: bad device: %s\n", @@ -4970,7 +4970,7 @@ xnr, req, req->sector, req->nr_sectors, jiffies); #endif up(&ioctl_read_sem); - spin_lock_irq(&q->queue_lock); + spin_lock_irq(q->queue_lock); sbpcd_end_request(req, 1); goto request_loop; } @@ -5011,7 +5011,7 @@ xnr, req, req->sector, req->nr_sectors, jiffies); #endif up(&ioctl_read_sem); - spin_lock_irq(&q->queue_lock); + spin_lock_irq(q->queue_lock); sbpcd_end_request(req, 1); goto request_loop; } @@ -5027,7 +5027,7 @@ #endif up(&ioctl_read_sem); sbp_sleep(0); /* wait a bit, try again */ - spin_lock_irq(&q->queue_lock); + spin_lock_irq(q->queue_lock); sbpcd_end_request(req, 0); goto request_loop; } @@ -5435,7 +5435,7 @@ { int i; - i = MINOR(cdi->dev); + i = minor(cdi->dev); down(&ioctl_read_sem); switch_drive(i); @@ -5474,7 +5474,7 @@ { int i; - i = MINOR(cdi->dev); + i = minor(cdi->dev); if ((i<0) || (i>=NR_SBPCD) || (D_S[i].drv_id==-1)) { msg(DBG_INF, "release: bad device: %04X\n", cdi->dev); @@ -6003,8 +6003,8 @@ { int i; - msg(DBG_CHK,"media_check (%d) called\n", MINOR(full_dev)); - i=MINOR(full_dev); + i=minor(full_dev); + msg(DBG_CHK,"media_check (%d) called\n", i); if (D_S[i].CD_changed==0xFF) { diff -urN linux-2.5.2-pre8/drivers/cdrom/sjcd.c linux/drivers/cdrom/sjcd.c --- linux-2.5.2-pre8/drivers/cdrom/sjcd.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/cdrom/sjcd.c Sat Jan 5 14:43:15 2002 @@ -105,6 +105,7 @@ static volatile unsigned char sjcd_completion_error = 0; static unsigned short sjcd_command_is_in_progress = 0; static unsigned short sjcd_error_reported = 0; +static spinlock_t sjcd_lock = SPIN_LOCK_UNLOCKED; static int sjcd_open_count; @@ -458,7 +459,7 @@ #if 0 printk("SJCD: sjcd_disk_change( 0x%x )\n", full_dev); #endif - if (MINOR(full_dev) > 0) { + if (minor(full_dev) > 0) { printk("SJCD: request error: invalid device minor.\n"); return 0; } @@ -1074,7 +1075,7 @@ */ #define CURRENT_IS_VALID \ - ( !QUEUE_EMPTY && MAJOR( CURRENT->rq_dev ) == MAJOR_NR && \ + ( !QUEUE_EMPTY && major( CURRENT->rq_dev ) == MAJOR_NR && \ CURRENT->cmd == READ && CURRENT->sector != -1 ) static void sjcd_transfer(void) @@ -1497,12 +1498,6 @@ #endif sjcd_transfer_is_active = 1; while (CURRENT_IS_VALID) { - /* - * Who of us are paranoiac? - */ - if (CURRENT->bh && !buffer_locked(CURRENT->bh)) - panic(DEVICE_NAME ": block not locked"); - sjcd_transfer(); if (CURRENT->nr_sectors == 0) end_request(1); @@ -1699,9 +1694,9 @@ return (-EIO); } - blk_init_queue(BLK_DEFAULT_QUEUE(MAJOR_NR), DEVICE_REQUEST); + blk_init_queue(BLK_DEFAULT_QUEUE(MAJOR_NR), DEVICE_REQUEST,&sjcd_lock); read_ahead[MAJOR_NR] = 4; - register_disk(NULL, MKDEV(MAJOR_NR, 0), 1, &sjcd_fops, 0); + register_disk(NULL, mk_kdev(MAJOR_NR, 0), 1, &sjcd_fops, 0); if (check_region(sjcd_base, 4)) { printk diff -urN linux-2.5.2-pre8/drivers/cdrom/sonycd535.c linux/drivers/cdrom/sonycd535.c --- linux-2.5.2-pre8/drivers/cdrom/sonycd535.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/cdrom/sonycd535.c Sat Jan 5 14:43:15 2002 @@ -281,7 +281,7 @@ { int retval; - if (MINOR(full_dev) != 0) { + if (minor(full_dev) != 0) { printk(CDU535_MESSAGE_NAME " request error: invalid device.\n"); return 0; } @@ -810,7 +810,7 @@ return; } INIT_REQUEST; - dev = MINOR(CURRENT->rq_dev); + dev = minor(CURRENT->rq_dev); block = CURRENT->sector; nsect = CURRENT->nr_sectors; if (dev != 0) { @@ -1089,7 +1089,7 @@ if (!inode) { return -EINVAL; } - dev = MINOR(inode->i_rdev) >> 6; + dev = minor(inode->i_rdev) >> 6; if (dev != 0) { return -EINVAL; } @@ -1644,7 +1644,7 @@ return -EIO; } request_region(sony535_cd_base_io, 4, CDU535_HANDLE); - register_disk(NULL, MKDEV(MAJOR_NR,0), 1, &cdu_fops, 0); + register_disk(NULL, mk_kdev(MAJOR_NR,0), 1, &cdu_fops, 0); return 0; } diff -urN linux-2.5.2-pre8/drivers/char/amiserial.c linux/drivers/char/amiserial.c --- linux-2.5.2-pre8/drivers/char/amiserial.c Sun Sep 16 21:22:56 2001 +++ linux/drivers/char/amiserial.c Sat Jan 5 14:43:15 2002 @@ -1904,7 +1904,7 @@ unsigned long page; MOD_INC_USE_COUNT; - line = MINOR(tty->device) - tty->driver.minor_start; + line = minor(tty->device) - tty->driver.minor_start; if ((line < 0) || (line >= NR_PORTS)) { MOD_DEC_USE_COUNT; return -ENODEV; @@ -2328,7 +2328,7 @@ static kdev_t serial_console_device(struct console *c) { - return MKDEV(TTY_MAJOR, 64); + return mk_kdev(TTY_MAJOR, 64); } static struct console sercons = { diff -urN linux-2.5.2-pre8/drivers/char/cyclades.c linux/drivers/char/cyclades.c --- linux-2.5.2-pre8/drivers/char/cyclades.c Fri Sep 14 14:04:07 2001 +++ linux/drivers/char/cyclades.c Sat Jan 5 14:43:15 2002 @@ -2591,7 +2591,7 @@ unsigned long page; MOD_INC_USE_COUNT; - line = MINOR(tty->device) - tty->driver.minor_start; + line = minor(tty->device) - tty->driver.minor_start; if ((line < 0) || (NR_PORTS <= line)){ MOD_DEC_USE_COUNT; return -ENODEV; diff -urN linux-2.5.2-pre8/drivers/char/dsp56k.c linux/drivers/char/dsp56k.c --- linux-2.5.2-pre8/drivers/char/dsp56k.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/dsp56k.c Sat Jan 5 14:43:15 2002 @@ -207,7 +207,7 @@ loff_t *ppos) { struct inode *inode = file->f_dentry->d_inode; - int dev = MINOR(inode->i_rdev) & 0x0f; + int dev = minor(inode->i_rdev) & 0x0f; switch(dev) { @@ -270,7 +270,7 @@ loff_t *ppos) { struct inode *inode = file->f_dentry->d_inode; - int dev = MINOR(inode->i_rdev) & 0x0f; + int dev = minor(inode->i_rdev) & 0x0f; switch(dev) { @@ -331,7 +331,7 @@ static int dsp56k_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) { - int dev = MINOR(inode->i_rdev) & 0x0f; + int dev = minor(inode->i_rdev) & 0x0f; switch(dev) { @@ -424,7 +424,7 @@ #if 0 static unsigned int dsp56k_poll(struct file *file, poll_table *wait) { - int dev = MINOR(file->f_dentry->d_inode->i_rdev) & 0x0f; + int dev = minor(file->f_dentry->d_inode->i_rdev) & 0x0f; switch(dev) { @@ -441,7 +441,7 @@ static int dsp56k_open(struct inode *inode, struct file *file) { - int dev = MINOR(inode->i_rdev) & 0x0f; + int dev = minor(inode->i_rdev) & 0x0f; switch(dev) { @@ -472,7 +472,7 @@ static int dsp56k_release(struct inode *inode, struct file *file) { - int dev = MINOR(inode->i_rdev) & 0x0f; + int dev = minor(inode->i_rdev) & 0x0f; switch(dev) { diff -urN linux-2.5.2-pre8/drivers/char/dtlk.c linux/drivers/char/dtlk.c --- linux-2.5.2-pre8/drivers/char/dtlk.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/dtlk.c Sat Jan 5 14:43:15 2002 @@ -125,7 +125,7 @@ static ssize_t dtlk_read(struct file *file, char *buf, size_t count, loff_t * ppos) { - unsigned int minor = MINOR(file->f_dentry->d_inode->i_rdev); + unsigned int minor = minor(file->f_dentry->d_inode->i_rdev); char ch; int i = 0, retries; @@ -185,7 +185,7 @@ if (ppos != &file->f_pos) return -ESPIPE; - if (MINOR(file->f_dentry->d_inode->i_rdev) != DTLK_MINOR) + if (minor(file->f_dentry->d_inode->i_rdev) != DTLK_MINOR) return -EINVAL; while (1) { @@ -304,7 +304,7 @@ { TRACE_TEXT("(dtlk_open"); - switch (MINOR(inode->i_rdev)) { + switch (minor(inode->i_rdev)) { case DTLK_MINOR: if (dtlk_busy) return -EBUSY; @@ -319,7 +319,7 @@ { TRACE_TEXT("(dtlk_release"); - switch (MINOR(inode->i_rdev)) { + switch (minor(inode->i_rdev)) { case DTLK_MINOR: break; diff -urN linux-2.5.2-pre8/drivers/char/dz.c linux/drivers/char/dz.c --- linux-2.5.2-pre8/drivers/char/dz.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/dz.c Sat Jan 5 14:43:15 2002 @@ -1273,7 +1273,7 @@ struct dz_serial *info; int retval, line; - line = MINOR(tty->device) - tty->driver.minor_start; + line = minor(tty->device) - tty->driver.minor_start; /* * The dz lines for the mouse/keyboard must be opened using their @@ -1508,7 +1508,7 @@ static kdev_t dz_console_device(struct console *c) { - return MKDEV(TTY_MAJOR, 64 + c->index); + return mk_kdev(TTY_MAJOR, 64 + c->index); } static int __init dz_console_setup(struct console *co, char *options) diff -urN linux-2.5.2-pre8/drivers/char/epca.c linux/drivers/char/epca.c --- linux-2.5.2-pre8/drivers/char/epca.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/epca.c Sat Jan 5 14:43:15 2002 @@ -1384,7 +1384,7 @@ return (0) ; } - line = MINOR(tty->device) - tty->driver.minor_start; + line = minor(tty->device) - tty->driver.minor_start; if (line < 0 || line >= nbdevs) { printk(KERN_ERR " - pc_open : line out of range in pc_open\n"); @@ -2895,7 +2895,7 @@ if (bc->orun) { bc->orun = 0; - printk(KERN_WARNING "overrun! DigiBoard device minor = %d\n",MINOR(tty->device)); + printk(KERN_WARNING "overrun! DigiBoard device minor = %d\n",minor(tty->device)); } rxwinon(ch); diff -urN linux-2.5.2-pre8/drivers/char/esp.c linux/drivers/char/esp.c --- linux-2.5.2-pre8/drivers/char/esp.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/esp.c Sat Jan 5 14:43:15 2002 @@ -2354,7 +2354,7 @@ struct esp_struct *info; int retval, line; - line = MINOR(tty->device) - tty->driver.minor_start; + line = minor(tty->device) - tty->driver.minor_start; if ((line < 0) || (line >= NR_PORTS)) return -ENODEV; diff -urN linux-2.5.2-pre8/drivers/char/ftape/zftape/zftape-init.c linux/drivers/char/ftape/zftape/zftape-init.c --- linux-2.5.2-pre8/drivers/char/ftape/zftape/zftape-init.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/ftape/zftape/zftape-init.c Sat Jan 5 14:43:15 2002 @@ -112,11 +112,11 @@ int result; TRACE_FUN(ft_t_flow); - TRACE(ft_t_flow, "called for minor %d", MINOR(ino->i_rdev)); + TRACE(ft_t_flow, "called for minor %d", minor(ino->i_rdev)); if ( test_and_set_bit(0,&busy_flag) ) { TRACE_ABORT(-EBUSY, ft_t_warn, "failed: already busy"); } - if ((MINOR(ino->i_rdev) & ~(ZFT_MINOR_OP_MASK | FTAPE_NO_REWIND)) + if ((minor(ino->i_rdev) & ~(ZFT_MINOR_OP_MASK | FTAPE_NO_REWIND)) > FTAPE_SEL_D) { clear_bit(0,&busy_flag); @@ -124,7 +124,7 @@ } orig_sigmask = current->blocked; sigfillset(¤t->blocked); - result = _zft_open(MINOR(ino->i_rdev), filep->f_flags & O_ACCMODE); + result = _zft_open(minor(ino->i_rdev), filep->f_flags & O_ACCMODE); if (result < 0) { current->blocked = orig_sigmask; /* restore mask */ clear_bit(0,&busy_flag); @@ -146,7 +146,7 @@ int result; TRACE_FUN(ft_t_flow); - if ( !test_bit(0,&busy_flag) || MINOR(ino->i_rdev) != zft_unit) { + if ( !test_bit(0,&busy_flag) || minor(ino->i_rdev) != zft_unit) { TRACE(ft_t_err, "failed: not busy or wrong unit"); TRACE_EXIT 0; } @@ -169,7 +169,7 @@ sigset_t old_sigmask; TRACE_FUN(ft_t_flow); - if ( !test_bit(0,&busy_flag) || MINOR(ino->i_rdev) != zft_unit || ft_failure) { + if ( !test_bit(0,&busy_flag) || minor(ino->i_rdev) != zft_unit || ft_failure) { TRACE_ABORT(-EIO, ft_t_err, "failed: not busy, failure or wrong unit"); } @@ -190,7 +190,7 @@ TRACE_FUN(ft_t_flow); if ( !test_bit(0,&busy_flag) || - MINOR(filep->f_dentry->d_inode->i_rdev) != zft_unit || + minor(filep->f_dentry->d_inode->i_rdev) != zft_unit || ft_failure) { TRACE_ABORT(-EIO, ft_t_err, @@ -219,7 +219,7 @@ TRACE_FUN(ft_t_flow); TRACE(ft_t_data_flow, "called with count: %ld", (unsigned long)req_len); - if (!test_bit(0,&busy_flag) || MINOR(ino->i_rdev) != zft_unit || ft_failure) { + if (!test_bit(0,&busy_flag) || minor(ino->i_rdev) != zft_unit || ft_failure) { TRACE_ABORT(-EIO, ft_t_err, "failed: not busy, failure or wrong unit"); } @@ -242,7 +242,7 @@ TRACE_FUN(ft_t_flow); TRACE(ft_t_flow, "called with count: %ld", (unsigned long)req_len); - if (!test_bit(0,&busy_flag) || MINOR(ino->i_rdev) != zft_unit || ft_failure) { + if (!test_bit(0,&busy_flag) || minor(ino->i_rdev) != zft_unit || ft_failure) { TRACE_ABORT(-EIO, ft_t_err, "failed: not busy, failure or wrong unit"); } diff -urN linux-2.5.2-pre8/drivers/char/ip2main.c linux/drivers/char/ip2main.c --- linux-2.5.2-pre8/drivers/char/ip2main.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/ip2main.c Sat Jan 5 14:43:15 2002 @@ -1589,9 +1589,9 @@ wait_queue_t wait; int rc = 0; int do_clocal = 0; - i2ChanStrPtr pCh = DevTable[MINOR(tty->device)]; + i2ChanStrPtr pCh = DevTable[minor(tty->device)]; - ip2trace (MINOR(tty->device), ITRC_OPEN, ITRC_ENTER, 0 ); + ip2trace (minor(tty->device), ITRC_OPEN, ITRC_ENTER, 0 ); if ( pCh == NULL ) { return -ENODEV; @@ -1604,7 +1604,7 @@ #ifdef IP2DEBUG_OPEN printk(KERN_DEBUG \ "IP2:open(tty=%p,pFile=%p):dev=%x,maj=%d,min=%d,ch=%d,idx=%d\n", - tty, pFile, tty->device, MAJOR(tty->device), MINOR(tty->device), + tty, pFile, tty->device, major(tty->device), minor(tty->device), pCh->infl.hd.i2sChannel, pCh->port_index); open_sanity_check ( pCh, pCh->pMyBord ); #endif @@ -1796,7 +1796,7 @@ ip2trace (CHANN, ITRC_CLOSE, ITRC_ENTER, 0 ); #ifdef IP2DEBUG_OPEN - printk(KERN_DEBUG "IP2:close ttyF%02X:\n",MINOR(tty->device)); + printk(KERN_DEBUG "IP2:close ttyF%02X:\n",minor(tty->device)); #endif if ( tty_hung_up_p ( pFile ) ) { @@ -2205,7 +2205,7 @@ static void ip2_start ( PTTY tty ) { - i2ChanStrPtr pCh = DevTable[MINOR(tty->device)]; + i2ChanStrPtr pCh = DevTable[minor(tty->device)]; i2QueueCommands(PTYPE_BYPASS, pCh, 0, 1, CMD_RESUME); i2QueueCommands(PTYPE_BYPASS, pCh, 100, 1, CMD_UNSUSPEND); @@ -2218,7 +2218,7 @@ static void ip2_stop ( PTTY tty ) { - i2ChanStrPtr pCh = DevTable[MINOR(tty->device)]; + i2ChanStrPtr pCh = DevTable[minor(tty->device)]; i2QueueCommands(PTYPE_BYPASS, pCh, 100, 1, CMD_SUSPEND); #ifdef IP2DEBUG_WRITE @@ -2246,7 +2246,7 @@ ip2_ioctl ( PTTY tty, struct file *pFile, UINT cmd, ULONG arg ) { wait_queue_t wait; - i2ChanStrPtr pCh = DevTable[MINOR(tty->device)]; + i2ChanStrPtr pCh = DevTable[minor(tty->device)]; struct async_icount cprev, cnow; /* kernel counter temps */ struct serial_icounter_struct *p_cuser; /* user space */ int rc = 0; @@ -3010,12 +3010,12 @@ #if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,0) int ip2_ipl_read(struct inode *pInode, char *pData, size_t count, loff_t *off ) - unsigned int minor = MINOR( pInode->i_rdev ); + unsigned int minor = minor( pInode->i_rdev ); #else ssize_t ip2_ipl_read(struct file *pFile, char *pData, size_t count, loff_t *off ) { - unsigned int minor = MINOR( pFile->f_dentry->d_inode->i_rdev ); + unsigned int minor = minor( pFile->f_dentry->d_inode->i_rdev ); #endif int rc = 0; @@ -3146,7 +3146,7 @@ static int ip2_ipl_ioctl ( struct inode *pInode, struct file *pFile, UINT cmd, ULONG arg ) { - unsigned int iplminor = MINOR(pInode->i_rdev); + unsigned int iplminor = minor(pInode->i_rdev); int rc = 0; ULONG *pIndex = (ULONG*)arg; i2eBordStrPtr pB = i2BoardPtrTable[iplminor / 4]; @@ -3281,7 +3281,7 @@ static int ip2_ipl_open( struct inode *pInode, struct file *pFile ) { - unsigned int iplminor = MINOR(pInode->i_rdev); + unsigned int iplminor = minor(pInode->i_rdev); i2eBordStrPtr pB; i2ChanStrPtr pCh; diff -urN linux-2.5.2-pre8/drivers/char/isicom.c linux/drivers/char/isicom.c --- linux-2.5.2-pre8/drivers/char/isicom.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/isicom.c Sat Jan 5 14:43:15 2002 @@ -1021,7 +1021,7 @@ #ifdef ISICOM_DEBUG printk(KERN_DEBUG "ISICOM: open start!!!.\n"); #endif - line = MINOR(tty->device) - tty->driver.minor_start; + line = minor(tty->device) - tty->driver.minor_start; #ifdef ISICOM_DEBUG printk(KERN_DEBUG "line = %d.\n", line); diff -urN linux-2.5.2-pre8/drivers/char/istallion.c linux/drivers/char/istallion.c --- linux-2.5.2-pre8/drivers/char/istallion.c Thu Oct 25 13:53:47 2001 +++ linux/drivers/char/istallion.c Sat Jan 5 14:43:15 2002 @@ -1034,7 +1034,7 @@ (int) filp, tty->device); #endif - minordev = MINOR(tty->device); + minordev = minor(tty->device); brdnr = MINOR2BRD(minordev); if (brdnr >= stli_nrbrds) return(-ENODEV); @@ -4859,7 +4859,7 @@ (int) fp, (int) buf, count, (int) offp); #endif - brdnr = MINOR(fp->f_dentry->d_inode->i_rdev); + brdnr = minor(fp->f_dentry->d_inode->i_rdev); if (brdnr >= stli_nrbrds) return(-ENODEV); brdp = stli_brds[brdnr]; @@ -4910,7 +4910,7 @@ (int) fp, (int) buf, count, (int) offp); #endif - brdnr = MINOR(fp->f_dentry->d_inode->i_rdev); + brdnr = minor(fp->f_dentry->d_inode->i_rdev); if (brdnr >= stli_nrbrds) return(-ENODEV); brdp = stli_brds[brdnr]; @@ -5247,7 +5247,7 @@ * Now handle the board specific ioctls. These all depend on the * minor number of the device they were called from. */ - brdnr = MINOR(ip->i_rdev); + brdnr = minor(ip->i_rdev); if (brdnr >= STL_MAXBRDS) return(-ENODEV); brdp = stli_brds[brdnr]; diff -urN linux-2.5.2-pre8/drivers/char/ite_gpio.c linux/drivers/char/ite_gpio.c --- linux-2.5.2-pre8/drivers/char/ite_gpio.c Sun Sep 9 10:43:02 2001 +++ linux/drivers/char/ite_gpio.c Sat Jan 5 14:43:15 2002 @@ -238,7 +238,7 @@ static int ite_gpio_open(struct inode *inode, struct file *file) { - unsigned int minor = MINOR(inode->i_rdev); + unsigned int minor = minor(inode->i_rdev); if (minor != GPIO_MINOR) return -ENODEV; diff -urN linux-2.5.2-pre8/drivers/char/lp.c linux/drivers/char/lp.c --- linux-2.5.2-pre8/drivers/char/lp.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/lp.c Sat Jan 5 14:43:15 2002 @@ -683,7 +683,7 @@ static kdev_t lp_console_device (struct console *c) { - return MKDEV(LP_MAJOR, CONSOLE_LP); + return mk_kdev(LP_MAJOR, CONSOLE_LP); } static struct console lpcons = { diff -urN linux-2.5.2-pre8/drivers/char/moxa.c linux/drivers/char/moxa.c --- linux-2.5.2-pre8/drivers/char/moxa.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/moxa.c Sat Jan 5 14:43:15 2002 @@ -189,7 +189,7 @@ #define WAKEUP_CHARS 256 -#define PORTNO(x) (MINOR((x)->device) - (x)->driver.minor_start) +#define PORTNO(x) (minor((x)->device) - (x)->driver.minor_start) static int verbose = 0; static int ttymajor = MOXAMAJOR; @@ -648,7 +648,7 @@ } if (--ch->count < 0) { printk("moxa_close: bad serial port count, minor=%d\n", - MINOR(tty->device)); + minor(tty->device)); ch->count = 0; } if (ch->count) { diff -urN linux-2.5.2-pre8/drivers/char/mxser.c linux/drivers/char/mxser.c --- linux-2.5.2-pre8/drivers/char/mxser.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/mxser.c Sat Jan 5 14:43:15 2002 @@ -91,7 +91,7 @@ #define UART_MCR_AFE 0x20 #define UART_LSR_SPECIAL 0x1E -#define PORTNO(x) (MINOR((x)->device) - (x)->driver.minor_start) +#define PORTNO(x) (minor((x)->device) - (x)->driver.minor_start) #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) diff -urN linux-2.5.2-pre8/drivers/char/n_hdlc.c linux/drivers/char/n_hdlc.c --- linux-2.5.2-pre8/drivers/char/n_hdlc.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/n_hdlc.c Sat Jan 5 14:43:15 2002 @@ -327,7 +327,7 @@ if (debuglevel >= DEBUG_LEVEL_INFO) printk("%s(%d)n_hdlc_tty_open() called (major=%u,minor=%u)\n", __FILE__,__LINE__, - MAJOR(tty->device), MINOR(tty->device)); + major(tty->device), minor(tty->device)); /* There should not be an existing table for this slot. */ if (n_hdlc) { diff -urN linux-2.5.2-pre8/drivers/char/pcxx.c linux/drivers/char/pcxx.c --- linux-2.5.2-pre8/drivers/char/pcxx.c Thu Sep 13 15:21:32 2001 +++ linux/drivers/char/pcxx.c Sat Jan 5 14:43:15 2002 @@ -406,7 +406,7 @@ int boardnum; int retval; - line = MINOR(tty->device) - tty->driver.minor_start; + line = minor(tty->device) - tty->driver.minor_start; if(line < 0 || line >= nbdevs) { printk("line out of range in pcxe_open\n"); @@ -2080,7 +2080,7 @@ if(bc->orun) { bc->orun = 0; - printk("overrun! DigiBoard device minor=%d\n",MINOR(tty->device)); + printk("overrun! DigiBoard device minor=%d\n",minor(tty->device)); } rxwinon(ch); diff -urN linux-2.5.2-pre8/drivers/char/rio/linux_compat.h linux/drivers/char/rio/linux_compat.h --- linux-2.5.2-pre8/drivers/char/rio/linux_compat.h Wed Jul 4 14:41:33 2001 +++ linux/drivers/char/rio/linux_compat.h Sat Jan 5 14:43:15 2002 @@ -60,9 +60,6 @@ #define getpid() (current->pid) -#define major(dev) MAJOR(dev) -#define minor(dev) MINOR(dev) - #define QSIZE SERIAL_XMIT_SIZE #define pseterr(errno) return (- errno) diff -urN linux-2.5.2-pre8/drivers/char/rio/rio.h linux/drivers/char/rio/rio.h --- linux-2.5.2-pre8/drivers/char/rio/rio.h Wed Aug 15 01:22:15 2001 +++ linux/drivers/char/rio/rio.h Sat Jan 5 14:43:15 2002 @@ -205,10 +205,10 @@ #define RIO_MODEMOFFSET 0x200 /* doesn't mean anything */ #define RIO_MODEM_MASK 0x1FF #define RIO_MODEM_BIT 0x200 -#define RIO_UNMODEM(DEV) (minor(DEV) & RIO_MODEM_MASK) -#define RIO_ISMODEM(DEV) (minor(DEV) & RIO_MODEM_BIT) -#define RIO_PORT(DEV,FIRST_MAJ) ( (major(DEV) - FIRST_MAJ) * PORTS_PER_HOST) \ - + minor(DEV) +#define RIO_UNMODEM(DEV) (MINOR(DEV) & RIO_MODEM_MASK) +#define RIO_ISMODEM(DEV) (MINOR(DEV) & RIO_MODEM_BIT) +#define RIO_PORT(DEV,FIRST_MAJ) ( (MAJOR(DEV) - FIRST_MAJ) * PORTS_PER_HOST) \ + + MINOR(DEV) #define splrio spltty diff -urN linux-2.5.2-pre8/drivers/char/rio/rio_linux.c linux/drivers/char/rio/rio_linux.c --- linux-2.5.2-pre8/drivers/char/rio/rio_linux.c Thu Oct 25 13:53:47 2001 +++ linux/drivers/char/rio/rio_linux.c Sat Jan 5 14:43:15 2002 @@ -375,16 +375,16 @@ int rio_minor (kdev_t device) { - return MINOR (device) + - 256 * ((MAJOR (device) == RIO_NORMAL_MAJOR1) || - (MAJOR (device) == RIO_CALLOUT_MAJOR1)); + return minor (device) + + 256 * ((major (device) == RIO_NORMAL_MAJOR1) || + (major (device) == RIO_CALLOUT_MAJOR1)); } int rio_ismodem (kdev_t device) { - return (MAJOR (device) == RIO_NORMAL_MAJOR0) || - (MAJOR (device) == RIO_NORMAL_MAJOR1); + return (major (device) == RIO_NORMAL_MAJOR0) || + (major (device) == RIO_NORMAL_MAJOR1); } @@ -424,7 +424,7 @@ tty = ((struct Port *)ptr)->gs.tty; - modem = (MAJOR(tty->device) == RIO_NORMAL_MAJOR0) || (MAJOR(tty->device) == RIO_NORMAL_MAJOR1); + modem = (major(tty->device) == RIO_NORMAL_MAJOR0) || (major(tty->device) == RIO_NORMAL_MAJOR1); rv = RIOParam( (struct Port *) ptr, CONFIG, modem, 1); diff -urN linux-2.5.2-pre8/drivers/char/rio/rio_linux.h linux/drivers/char/rio/rio_linux.h --- linux-2.5.2-pre8/drivers/char/rio/rio_linux.h Wed Jul 4 14:41:33 2001 +++ linux/drivers/char/rio/rio_linux.h Sat Jan 5 14:43:15 2002 @@ -178,10 +178,9 @@ #ifdef DEBUG #define rio_dprintk(f, str...) do { if (rio_debug & f) printk (str);} while (0) -#define func_enter() rio_dprintk (RIO_DEBUG_FLOW, "rio: enter " __FUNCTION__ "\n") -#define func_exit() rio_dprintk (RIO_DEBUG_FLOW, "rio: exit " __FUNCTION__ "\n") -#define func_enter2() rio_dprintk (RIO_DEBUG_FLOW, "rio: enter " __FUNCTION__ \ - "(port %d)\n", port->line) +#define func_enter() rio_dprintk (RIO_DEBUG_FLOW, "rio: enter %s\n", __FUNCTION__) +#define func_exit() rio_dprintk (RIO_DEBUG_FLOW, "rio: exit %s\n", __FUNCTION__) +#define func_enter2() rio_dprintk (RIO_DEBUG_FLOW, "rio: enter %s (port %d)\n",__FUNCTION__, port->line) #else #define rio_dprintk(f, str...) /* nothing */ #define func_enter() diff -urN linux-2.5.2-pre8/drivers/char/rio/rioctrl.c linux/drivers/char/rio/rioctrl.c --- linux-2.5.2-pre8/drivers/char/rio/rioctrl.c Fri Apr 13 20:26:07 2001 +++ linux/drivers/char/rio/rioctrl.c Sat Jan 5 14:43:15 2002 @@ -1737,15 +1737,15 @@ switch ( (uint)arg & RIO_DEV_MASK ) { case RIO_DEV_DIRECT: - arg = (caddr_t)drv_makedev(major(dev), port); + arg = (caddr_t)drv_makedev(MAJOR(dev), port); rio_dprintk (RIO_DEBUG_CTRL, "Makedev direct 0x%x is 0x%x\n",port, (int)arg); return (int)arg; case RIO_DEV_MODEM: - arg = (caddr_t)drv_makedev(major(dev), (port|RIO_MODEM_BIT) ); + arg = (caddr_t)drv_makedev(MAJOR(dev), (port|RIO_MODEM_BIT) ); rio_dprintk (RIO_DEBUG_CTRL, "Makedev modem 0x%x is 0x%x\n",port, (int)arg); return (int)arg; case RIO_DEV_XPRINT: - arg = (caddr_t)drv_makedev(major(dev), port); + arg = (caddr_t)drv_makedev(MAJOR(dev), port); rio_dprintk (RIO_DEBUG_CTRL, "Makedev printer 0x%x is 0x%x\n",port, (int)arg); return (int)arg; } diff -urN linux-2.5.2-pre8/drivers/char/riscom8.c linux/drivers/char/riscom8.c --- linux-2.5.2-pre8/drivers/char/riscom8.c Thu Sep 13 15:21:32 2001 +++ linux/drivers/char/riscom8.c Sat Jan 5 14:43:15 2002 @@ -1089,12 +1089,12 @@ struct riscom_board * bp; unsigned long flags; - board = RC_BOARD(MINOR(tty->device)); + board = RC_BOARD(minor(tty->device)); if (board > RC_NBOARD || !(rc_board[board].flags & RC_BOARD_PRESENT)) return -ENODEV; bp = &rc_board[board]; - port = rc_port + board * RC_NPORT + RC_PORT(MINOR(tty->device)); + port = rc_port + board * RC_NPORT + RC_PORT(minor(tty->device)); if (rc_paranoia_check(port, tty->device, "rc_open")) return -ENODEV; diff -urN linux-2.5.2-pre8/drivers/char/sbc60xxwdt.c linux/drivers/char/sbc60xxwdt.c --- linux-2.5.2-pre8/drivers/char/sbc60xxwdt.c Fri Nov 30 08:26:04 2001 +++ linux/drivers/char/sbc60xxwdt.c Sat Jan 5 14:43:15 2002 @@ -196,7 +196,7 @@ static int fop_open(struct inode * inode, struct file * file) { - switch(MINOR(inode->i_rdev)) + switch(minor(inode->i_rdev)) { case WATCHDOG_MINOR: /* Just in case we're already talking to someone... */ @@ -214,7 +214,7 @@ static int fop_close(struct inode * inode, struct file * file) { - if(MINOR(inode->i_rdev) == WATCHDOG_MINOR) + if(minor(inode->i_rdev) == WATCHDOG_MINOR) { if(wdt_expect_close) wdt_turnoff(); diff -urN linux-2.5.2-pre8/drivers/char/ser_a2232.c linux/drivers/char/ser_a2232.c --- linux-2.5.2-pre8/drivers/char/ser_a2232.c Thu Sep 13 15:21:32 2001 +++ linux/drivers/char/ser_a2232.c Sat Jan 5 14:43:15 2002 @@ -460,7 +460,7 @@ int retval; struct a2232_port *port; - line = MINOR(tty->device); + line = minor(tty->device); port = &a2232_ports[line]; tty->driver_data = port; diff -urN linux-2.5.2-pre8/drivers/char/serial167.c linux/drivers/char/serial167.c --- linux-2.5.2-pre8/drivers/char/serial167.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/serial167.c Sat Jan 5 14:43:15 2002 @@ -248,18 +248,18 @@ "Warning: cyclades_port out of range for (%d, %d) in %s\n"; if (!info) { - printk(badinfo, MAJOR(device), MINOR(device), routine); + printk(badinfo, major(device), minor(device), routine); return 1; } if( (long)info < (long)(&cy_port[0]) || (long)(&cy_port[NR_PORTS]) < (long)info ){ - printk(badrange, MAJOR(device), MINOR(device), routine); + printk(badrange, major(device), minor(device), routine); return 1; } if (info->magic != CYCLADES_MAGIC) { - printk(badmagic, MAJOR(device), MINOR(device), routine); + printk(badmagic, major(device), minor(device), routine); return 1; } #endif @@ -2132,7 +2132,7 @@ int retval, line; /* CP('O'); */ - line = MINOR(tty->device) - tty->driver.minor_start; + line = minor(tty->device) - tty->driver.minor_start; if ((line < 0) || (NR_PORTS <= line)){ return -ENODEV; } @@ -2807,7 +2807,7 @@ static kdev_t serial167_console_device(struct console *c) { - return MKDEV(TTY_MAJOR, 64 + c->index); + return mk_kdev(TTY_MAJOR, 64 + c->index); } diff -urN linux-2.5.2-pre8/drivers/char/serial_21285.c linux/drivers/char/serial_21285.c --- linux-2.5.2-pre8/drivers/char/serial_21285.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/serial_21285.c Sat Jan 5 14:43:15 2002 @@ -264,7 +264,7 @@ int line; MOD_INC_USE_COUNT; - line = MINOR(tty->device) - tty->driver.minor_start; + line = minor(tty->device) - tty->driver.minor_start; if (line) { MOD_DEC_USE_COUNT; return -ENODEV; @@ -391,7 +391,7 @@ static kdev_t rs285_console_device(struct console *c) { - return MKDEV(SERIAL_21285_MAJOR, SERIAL_21285_MINOR); + return mk_kdev(SERIAL_21285_MAJOR, SERIAL_21285_MINOR); } static int __init rs285_console_setup(struct console *co, char *options) diff -urN linux-2.5.2-pre8/drivers/char/serial_amba.c linux/drivers/char/serial_amba.c --- linux-2.5.2-pre8/drivers/char/serial_amba.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/serial_amba.c Sat Jan 5 14:43:15 2002 @@ -953,7 +953,7 @@ #if DEBUG printk("ambauart_flush_buffer(%d) called\n", - MINOR(tty->device) - tty->driver.minor_start); + minor(tty->device) - tty->driver.minor_start); #endif save_flags(flags); cli(); info->xmit.head = info->xmit.tail = 0; @@ -1515,7 +1515,7 @@ expire = jiffies + timeout; #if DEBUG printk("ambauart_wait_until_sent(%d), jiff=%lu, expire=%lu...\n", - MINOR(tty->device) - tty->driver.minor_start, jiffies, + minor(tty->device) - tty->driver.minor_start, jiffies, expire); #endif while (UART_GET_FR(info->port) & AMBA_UARTFR_BUSY) { @@ -1690,7 +1690,7 @@ static int ambauart_open(struct tty_struct *tty, struct file *filp) { struct amba_info *info; - int retval, line = MINOR(tty->device) - tty->driver.minor_start; + int retval, line = minor(tty->device) - tty->driver.minor_start; #if DEBUG printk("ambauart_open(%d) called\n", line); @@ -1923,7 +1923,7 @@ static kdev_t ambauart_console_device(struct console *c) { - return MKDEV(SERIAL_AMBA_MAJOR, SERIAL_AMBA_MINOR + c->index); + return mk_kdev(SERIAL_AMBA_MAJOR, SERIAL_AMBA_MINOR + c->index); } static int __init ambauart_console_setup(struct console *co, char *options) diff -urN linux-2.5.2-pre8/drivers/char/serial_tx3912.c linux/drivers/char/serial_tx3912.c --- linux-2.5.2-pre8/drivers/char/serial_tx3912.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/serial_tx3912.c Sat Jan 5 14:43:15 2002 @@ -548,7 +548,7 @@ return -EIO; } - line = MINOR(tty->device) - tty->driver.minor_start; + line = minor(tty->device) - tty->driver.minor_start; rs_dprintk (TX3912_UART_DEBUG_OPEN, "%d: opening line %d. tty=%p ctty=%p)\n", (int) current->pid, line, tty, current->tty); @@ -1007,7 +1007,7 @@ static kdev_t serial_console_device(struct console *c) { - return MKDEV(TTY_MAJOR, 64 + c->index); + return mk_kdev(TTY_MAJOR, 64 + c->index); } static __init int serial_console_setup(struct console *co, char *options) diff -urN linux-2.5.2-pre8/drivers/char/sh-sci.c linux/drivers/char/sh-sci.c --- linux-2.5.2-pre8/drivers/char/sh-sci.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/sh-sci.c Sat Jan 5 14:43:15 2002 @@ -813,7 +813,7 @@ struct sci_port *port; int retval, line; - line = MINOR(tty->device) - SCI_MINOR_START; + line = minor(tty->device) - SCI_MINOR_START; if ((line < 0) || (line >= SCI_NPORTS)) return -ENODEV; @@ -1183,7 +1183,7 @@ static kdev_t serial_console_device(struct console *c) { - return MKDEV(SCI_MAJOR, SCI_MINOR_START + c->index); + return mk_kdev(SCI_MAJOR, SCI_MINOR_START + c->index); } /* diff -urN linux-2.5.2-pre8/drivers/char/shwdt.c linux/drivers/char/shwdt.c --- linux-2.5.2-pre8/drivers/char/shwdt.c Tue Dec 11 10:10:18 2001 +++ linux/drivers/char/shwdt.c Sat Jan 5 14:43:15 2002 @@ -131,7 +131,7 @@ */ static int sh_wdt_open(struct inode *inode, struct file *file) { - switch (MINOR(inode->i_rdev)) { + switch (minor(inode->i_rdev)) { case WATCHDOG_MINOR: if (sh_is_open) { return -EBUSY; @@ -160,7 +160,7 @@ { lock_kernel(); - if (MINOR(inode->i_rdev) == WATCHDOG_MINOR) { + if (minor(inode->i_rdev) == WATCHDOG_MINOR) { #ifndef CONFIG_WATCHDOG_NOWAYOUT sh_wdt_stop(); #endif diff -urN linux-2.5.2-pre8/drivers/char/specialix.c linux/drivers/char/specialix.c --- linux-2.5.2-pre8/drivers/char/specialix.c Fri Nov 9 14:01:21 2001 +++ linux/drivers/char/specialix.c Sat Jan 5 14:43:15 2002 @@ -1455,17 +1455,17 @@ struct specialix_board * bp; unsigned long flags; - board = SX_BOARD(MINOR(tty->device)); + board = SX_BOARD(minor(tty->device)); if (board > SX_NBOARD || !(sx_board[board].flags & SX_BOARD_PRESENT)) return -ENODEV; bp = &sx_board[board]; - port = sx_port + board * SX_NPORT + SX_PORT(MINOR(tty->device)); + port = sx_port + board * SX_NPORT + SX_PORT(minor(tty->device)); #ifdef DEBUG_SPECIALIX printk (KERN_DEBUG "Board = %d, bp = %p, port = %p, portno = %d.\n", - board, bp, port, SX_PORT(MINOR(tty->device))); + board, bp, port, SX_PORT(minor(tty->device))); #endif if (sx_paranoia_check(port, tty->device, "sx_open")) diff -urN linux-2.5.2-pre8/drivers/char/stallion.c linux/drivers/char/stallion.c --- linux-2.5.2-pre8/drivers/char/stallion.c Fri Sep 21 10:55:23 2001 +++ linux/drivers/char/stallion.c Sat Jan 5 14:43:15 2002 @@ -1018,7 +1018,7 @@ (int) filp, tty->device); #endif - minordev = MINOR(tty->device); + minordev = minor(tty->device); brdnr = MINOR2BRD(minordev); if (brdnr >= stl_nrbrds) return(-ENODEV); @@ -3133,7 +3133,7 @@ (int) fp, cmd, (int) arg); #endif - brdnr = MINOR(ip->i_rdev); + brdnr = minor(ip->i_rdev); if (brdnr >= STL_MAXBRDS) return(-ENODEV); rc = 0; diff -urN linux-2.5.2-pre8/drivers/char/sx.c linux/drivers/char/sx.c --- linux-2.5.2-pre8/drivers/char/sx.c Fri Nov 9 14:01:21 2001 +++ linux/drivers/char/sx.c Sat Jan 5 14:43:15 2002 @@ -1420,7 +1420,7 @@ return -EIO; } - line = MINOR(tty->device); + line = minor(tty->device); sx_dprintk (SX_DEBUG_OPEN, "%d: opening line %d. tty=%p ctty=%p, np=%d)\n", current->pid, line, tty, current->tty, sx_nports); diff -urN linux-2.5.2-pre8/drivers/char/synclink.c linux/drivers/char/synclink.c --- linux-2.5.2-pre8/drivers/char/synclink.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/synclink.c Sat Jan 5 14:43:15 2002 @@ -3600,7 +3600,7 @@ unsigned long flags; /* verify range of specified line number */ - line = MINOR(tty->device) - tty->driver.minor_start; + line = minor(tty->device) - tty->driver.minor_start; if ((line < 0) || (line >= mgsl_device_count)) { printk("%s(%d):mgsl_open with illegal line #%d.\n", __FILE__,__LINE__,line); diff -urN linux-2.5.2-pre8/drivers/char/tpqic02.c linux/drivers/char/tpqic02.c --- linux-2.5.2-pre8/drivers/char/tpqic02.c Fri Nov 30 08:26:04 2001 +++ linux/drivers/char/tpqic02.c Sat Jan 5 14:43:15 2002 @@ -1830,7 +1830,7 @@ /* can't print a ``long long'' (for filp->f_pos), so chop it */ printk(TPQIC02_NAME ": request READ, minor=%x, buf=%p, count=%lx" - ", pos=%lx, flags=%x\n", MINOR(dev), buf, + ", pos=%lx, flags=%x\n", minor(dev), buf, (long) count, (unsigned long) filp->f_pos, flags); if (count % TAPE_BLKSIZE) { /* Only allow mod 512 bytes at a time. */ @@ -2027,7 +2027,7 @@ /* can't print a ``long long'' (for filp->f_pos), so chop it */ printk(TPQIC02_NAME ": request WRITE, minor=%x, buf=%p" ", count=%lx, pos=%lx, flags=%x\n", - MINOR(dev), buf, + minor(dev), buf, (long) count, (unsigned long) filp->f_pos, flags); } @@ -2203,7 +2203,7 @@ kdevname(dev), flags); } - if (MINOR(dev) == 255) { /* special case for resetting */ + if (minor(dev) == 255) { /* special case for resetting */ if (capable(CAP_SYS_ADMIN)) { return (tape_reset(1) == TE_OK) ? -EAGAIN : -ENXIO; } else { @@ -2383,7 +2383,7 @@ } if (s != 0) { status_dead = YES; /* force reset */ - current_tape_dev = 0; /* earlier 0xff80 */ + current_tape_dev = NODEV;/* earlier 0xff80 */ return -EIO; } @@ -2522,7 +2522,7 @@ unsigned int iocmd, unsigned long ioarg) { int error; - int dev_maj = MAJOR(inode->i_rdev); + int dev_maj = major(inode->i_rdev); int c; struct mtop operation; unsigned char blk_addr[6]; @@ -2828,7 +2828,7 @@ return -ENODEV; } - current_tape_dev = MKDEV(QIC02_TAPE_MAJOR, 0); + current_tape_dev = mk_kdev(QIC02_TAPE_MAJOR, 0); #ifndef CONFIG_QIC02_DYNCONF printk(TPQIC02_NAME ": IRQ %d, DMA %d, IO 0x%x, IFC %s, %s, %s\n", diff -urN linux-2.5.2-pre8/drivers/char/vme_scc.c linux/drivers/char/vme_scc.c --- linux-2.5.2-pre8/drivers/char/vme_scc.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/char/vme_scc.c Sat Jan 5 14:43:15 2002 @@ -833,7 +833,7 @@ static int scc_open (struct tty_struct * tty, struct file * filp) { - int line = MINOR(tty->device) - SCC_MINOR_BASE; + int line = minor(tty->device) - SCC_MINOR_BASE; int retval; struct scc_port *port = &scc_ports[line]; int i, channel = port->channel; @@ -1067,7 +1067,7 @@ static kdev_t scc_console_device(struct console *c) { - return MKDEV(TTY_MAJOR, SCC_MINOR_BASE + c->index); + return mk_kdev(TTY_MAJOR, SCC_MINOR_BASE + c->index); } diff -urN linux-2.5.2-pre8/drivers/char/w83877f_wdt.c linux/drivers/char/w83877f_wdt.c --- linux-2.5.2-pre8/drivers/char/w83877f_wdt.c Fri Nov 30 08:26:04 2001 +++ linux/drivers/char/w83877f_wdt.c Sat Jan 5 14:43:15 2002 @@ -196,7 +196,7 @@ static int fop_open(struct inode * inode, struct file * file) { - switch(MINOR(inode->i_rdev)) + switch(minor(inode->i_rdev)) { case WATCHDOG_MINOR: /* Just in case we're already talking to someone... */ @@ -214,7 +214,7 @@ static int fop_close(struct inode * inode, struct file * file) { - if(MINOR(inode->i_rdev) == WATCHDOG_MINOR) + if(minor(inode->i_rdev) == WATCHDOG_MINOR) { if(wdt_expect_close) wdt_turnoff(); diff -urN linux-2.5.2-pre8/drivers/isdn/sc/command.c linux/drivers/isdn/sc/command.c --- linux-2.5.2-pre8/drivers/isdn/sc/command.c Sun Sep 30 12:26:06 2001 +++ linux/drivers/isdn/sc/command.c Sat Jan 5 14:43:16 2002 @@ -95,7 +95,7 @@ if(adapter[i]->driverId == driver) return i; } - return -NODEV; + return -ENODEV; } /* diff -urN linux-2.5.2-pre8/drivers/md/lvm-fs.c linux/drivers/md/lvm-fs.c --- linux-2.5.2-pre8/drivers/md/lvm-fs.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/md/lvm-fs.c Sat Jan 5 14:43:16 2002 @@ -172,9 +172,9 @@ struct proc_dir_entry *pde; const char *name = _basename(lv->lv_name); - lv_devfs_handle[MINOR(lv->lv_dev)] = devfs_register( + lv_devfs_handle[minor(lv->lv_dev)] = devfs_register( vg_devfs_handle[vg_ptr->vg_number], name, - DEVFS_FL_DEFAULT, LVM_BLK_MAJOR, MINOR(lv->lv_dev), + DEVFS_FL_DEFAULT, LVM_BLK_MAJOR, minor(lv->lv_dev), S_IFBLK | S_IRUSR | S_IWUSR | S_IRGRP, &lvm_blk_dops, NULL); @@ -183,12 +183,12 @@ pde->read_proc = _proc_read_lv; pde->data = lv; } - return lv_devfs_handle[MINOR(lv->lv_dev)]; + return lv_devfs_handle[minor(lv->lv_dev)]; } void lvm_fs_remove_lv(vg_t *vg_ptr, lv_t *lv) { - devfs_unregister(lv_devfs_handle[MINOR(lv->lv_dev)]); - lv_devfs_handle[MINOR(lv->lv_dev)] = NULL; + devfs_unregister(lv_devfs_handle[minor(lv->lv_dev)]); + lv_devfs_handle[minor(lv->lv_dev)] = NULL; if(vg_ptr->lv_subdir_pde) { const char *name = _basename(lv->lv_name); @@ -283,7 +283,7 @@ lv->lv_stripesize); } sz += sprintf(page + sz, "device: %02u:%02u\n", - MAJOR(lv->lv_dev), MINOR(lv->lv_dev)); + major(lv->lv_dev), minor(lv->lv_dev)); return sz; } @@ -304,7 +304,7 @@ sz += sprintf(page + sz, "PE total: %u\n", pv->pe_total); sz += sprintf(page + sz, "PE allocated: %u\n", pv->pe_allocated); sz += sprintf(page + sz, "device: %02u:%02u\n", - MAJOR(pv->pv_dev), MINOR(pv->pv_dev)); + major(pv->pv_dev), minor(pv->pv_dev)); _show_uuid(pv->pv_uuid, uuid, uuid + sizeof(uuid)); sz += sprintf(page + sz, "uuid: %s\n", uuid); diff -urN linux-2.5.2-pre8/drivers/md/lvm-snap.c linux/drivers/md/lvm-snap.c --- linux-2.5.2-pre8/drivers/md/lvm-snap.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/md/lvm-snap.c Sat Jan 5 14:43:16 2002 @@ -68,7 +68,7 @@ if(vg->pv[p] == NULL) continue; - if(vg->pv[p]->pv_dev == rdev) + if(kdev_same(vg->pv[p]->pv_dev, rdev)) break; } @@ -77,7 +77,7 @@ /* bad news, the snapshot COW table is probably corrupt */ printk(KERN_ERR "%s -- _pv_get_number failed for rdev = %u\n", - lvm_name, rdev); + lvm_name, kdev_t_to_nr(rdev)); return -1; } @@ -105,7 +105,7 @@ exception = list_entry(next, lv_block_exception_t, hash); if (exception->rsector_org == org_start && - exception->rdev_org == org_dev) + kdev_same(exception->rdev_org, org_dev)) { if (i) { @@ -169,8 +169,10 @@ /* wipe the snapshot since it's inconsistent now */ _disable_snapshot(vg, lv_snap); - for (i = last_dev = 0; i < lv_snap->lv_remap_ptr; i++) { - if ( lv_snap->lv_block_exception[i].rdev_new != last_dev) { + last_dev = NODEV; + for (i = 0; i < lv_snap->lv_remap_ptr; i++) { + if ( !kdev_same(lv_snap->lv_block_exception[i].rdev_new, + last_dev)) { last_dev = lv_snap->lv_block_exception[i].rdev_new; invalidate_buffers(last_dev); } @@ -213,7 +215,7 @@ struct buffer_head * bh; int sectors_per_block, i, blksize, minor; - minor = MINOR(dev); + minor = minor(dev); blksize = lvm_blocksizes[minor]; sectors_per_block = blksize >> 9; nr /= sectors_per_block; @@ -299,7 +301,8 @@ vg_t *vg, lv_t* lv_snap) { const char * reason; - unsigned long org_start, snap_start, snap_phys_dev, virt_start, pe_off; + kdev_t snap_phys_dev; + unsigned long org_start, snap_start, virt_start, pe_off; int idx = lv_snap->lv_remap_ptr, chunk_size = lv_snap->lv_chunk_size; struct kiobuf * iobuf; int blksize_snap, blksize_org, min_blksize, max_blksize; diff -urN linux-2.5.2-pre8/drivers/md/lvm.c linux/drivers/md/lvm.c --- linux-2.5.2-pre8/drivers/md/lvm.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/md/lvm.c Sat Jan 5 14:43:16 2002 @@ -480,8 +480,8 @@ lvm_lock = lvm_snapshot_lock = SPIN_LOCK_UNLOCKED; pe_lock_req.lock = UNLOCK_PE; - pe_lock_req.data.lv_dev = 0; - pe_lock_req.data.pv_dev = 0; + pe_lock_req.data.lv_dev = NODEV; + pe_lock_req.data.pv_dev = NODEV; pe_lock_req.data.pv_offset = 0; /* Initialize VG pointers */ @@ -512,7 +512,7 @@ */ static int lvm_chr_open(struct inode *inode, struct file *file) { - unsigned int minor = MINOR(inode->i_rdev); + unsigned int minor = minor(inode->i_rdev); P_DEV("chr_open MINOR: %d VG#: %d mode: %s%s lock: %d\n", minor, VG_CHR(minor), MODE_TO_STR(file->f_mode), lock); @@ -546,7 +546,7 @@ static int lvm_chr_ioctl(struct inode *inode, struct file *file, uint command, ulong a) { - int minor = MINOR(inode->i_rdev); + int minor = minor(inode->i_rdev); uint extendable, l, v; void *arg = (void *) a; lv_t lv; @@ -752,7 +752,7 @@ static int lvm_chr_close(struct inode *inode, struct file *file) { P_DEV("chr_close MINOR: %d VG#: %d\n", - MINOR(inode->i_rdev), VG_CHR(MINOR(inode->i_rdev))); + minor(inode->i_rdev), VG_CHR(minor(inode->i_rdev))); #ifdef LVM_TOTAL_RESET if (lvm_reset_spindown > 0) { @@ -792,7 +792,7 @@ */ static int lvm_blk_open(struct inode *inode, struct file *file) { - int minor = MINOR(inode->i_rdev); + int minor = minor(inode->i_rdev); lv_t *lv_ptr; vg_t *vg_ptr = vg[VG_BLK(minor)]; @@ -845,7 +845,7 @@ static int lvm_blk_ioctl(struct inode *inode, struct file *file, uint command, ulong a) { - int minor = MINOR(inode->i_rdev); + int minor = minor(inode->i_rdev); vg_t *vg_ptr = vg[VG_BLK(minor)]; lv_t *lv_ptr = vg_ptr->lv[LV_BLK(minor)]; void *arg = (void *) a; @@ -985,7 +985,7 @@ */ static int lvm_blk_close(struct inode *inode, struct file *file) { - int minor = MINOR(inode->i_rdev); + int minor = minor(inode->i_rdev); vg_t *vg_ptr = vg[VG_BLK(minor)]; lv_t *lv_ptr = vg_ptr->lv[LV_BLK(minor)]; @@ -1097,7 +1097,7 @@ */ static inline int _should_defer(kdev_t pv, ulong sector, uint32_t pe_size) { return ((pe_lock_req.lock == LOCK_PE) && - (pv == pe_lock_req.data.pv_dev) && + kdev_same(pv, pe_lock_req.data.pv_dev) && (sector >= pe_lock_req.data.pv_offset) && (sector < (pe_lock_req.data.pv_offset + pe_size))); } @@ -1122,7 +1122,7 @@ static int lvm_map(struct bio *bi) { - int minor = MINOR(bi->bi_dev); + int minor = minor(bi->bi_dev); ulong index; ulong pe_start; ulong size = bio_sectors(bi); @@ -1339,7 +1339,8 @@ case LOCK_PE: for (p = 0; p < vg_ptr->pv_max; p++) { if (vg_ptr->pv[p] != NULL && - new_lock.data.pv_dev == vg_ptr->pv[p]->pv_dev) + kdev_same(new_lock.data.pv_dev, + vg_ptr->pv[p]->pv_dev)) break; } if (p == vg_ptr->pv_max) return -ENXIO; @@ -1373,8 +1374,8 @@ case UNLOCK_PE: down_write(&_pe_lock); pe_lock_req.lock = UNLOCK_PE; - pe_lock_req.data.lv_dev = 0; - pe_lock_req.data.pv_dev = 0; + pe_lock_req.data.lv_dev = NODEV; + pe_lock_req.data.pv_dev = NODEV; pe_lock_req.data.pv_offset = 0; bh = _dequeue_io(); up_write(&_pe_lock); @@ -1409,8 +1410,8 @@ strcmp(lv_ptr->lv_name, le_remap_req.lv_name) == 0) { for (le = 0; le < lv_ptr->lv_allocated_le; le++) { - if (lv_ptr->lv_current_pe[le].dev == - le_remap_req.old_dev && + if (kdev_same(lv_ptr->lv_current_pe[le].dev, + le_remap_req.old_dev) && lv_ptr->lv_current_pe[le].pe == le_remap_req.old_pe) { lv_ptr->lv_current_pe[le].dev = @@ -1928,8 +1929,8 @@ for (le = 0; le < lv_ptr->lv_allocated_le; le++) { vg_ptr->pe_allocated++; for (p = 0; p < vg_ptr->pv_cur; p++) { - if (vg_ptr->pv[p]->pv_dev == - lv_ptr->lv_current_pe[le].dev) + if (kdev_same(vg_ptr->pv[p]->pv_dev, + lv_ptr->lv_current_pe[le].dev)) vg_ptr->pv[p]->pe_allocated++; } } @@ -2029,11 +2030,11 @@ } /* if ( vg[VG_CHR(minor)]->lv[l]->lv_access & LV_SNAPSHOT) */ lv_ptr = vg_ptr->lv[l]; - lvm_gendisk.part[MINOR(lv_ptr->lv_dev)].start_sect = 0; - lvm_gendisk.part[MINOR(lv_ptr->lv_dev)].nr_sects = lv_ptr->lv_size; - lvm_size[MINOR(lv_ptr->lv_dev)] = lv_ptr->lv_size >> 1; - vg_lv_map[MINOR(lv_ptr->lv_dev)].vg_number = vg_ptr->vg_number; - vg_lv_map[MINOR(lv_ptr->lv_dev)].lv_number = lv_ptr->lv_number; + lvm_gendisk.part[minor(lv_ptr->lv_dev)].start_sect = 0; + lvm_gendisk.part[minor(lv_ptr->lv_dev)].nr_sects = lv_ptr->lv_size; + lvm_size[minor(lv_ptr->lv_dev)] = lv_ptr->lv_size >> 1; + vg_lv_map[minor(lv_ptr->lv_dev)].vg_number = vg_ptr->vg_number; + vg_lv_map[minor(lv_ptr->lv_dev)].lv_number = lv_ptr->lv_number; LVM_CORRECT_READ_AHEAD(lv_ptr->lv_read_ahead); vg_ptr->lv_cur++; lv_ptr->lv_status = lv_status_save; @@ -2081,7 +2082,7 @@ lv_ptr->vg = vg_ptr; - lvm_gendisk.part[MINOR(lv_ptr->lv_dev)].de = + lvm_gendisk.part[minor(lv_ptr->lv_dev)].de = lvm_fs_create_lv(vg_ptr, lv_ptr); return 0; @@ -2161,14 +2162,14 @@ invalidate_buffers(lv_ptr->lv_dev); /* reset generic hd */ - lvm_gendisk.part[MINOR(lv_ptr->lv_dev)].start_sect = -1; - lvm_gendisk.part[MINOR(lv_ptr->lv_dev)].nr_sects = 0; - lvm_gendisk.part[MINOR(lv_ptr->lv_dev)].de = 0; - lvm_size[MINOR(lv_ptr->lv_dev)] = 0; + lvm_gendisk.part[minor(lv_ptr->lv_dev)].start_sect = -1; + lvm_gendisk.part[minor(lv_ptr->lv_dev)].nr_sects = 0; + lvm_gendisk.part[minor(lv_ptr->lv_dev)].de = 0; + lvm_size[minor(lv_ptr->lv_dev)] = 0; /* reset VG/LV mapping */ - vg_lv_map[MINOR(lv_ptr->lv_dev)].vg_number = ABS_MAX_VG; - vg_lv_map[MINOR(lv_ptr->lv_dev)].lv_number = -1; + vg_lv_map[minor(lv_ptr->lv_dev)].vg_number = ABS_MAX_VG; + vg_lv_map[minor(lv_ptr->lv_dev)].lv_number = -1; /* correct the PE count in PVs if this is not a snapshot logical volume */ @@ -2179,8 +2180,8 @@ for (le = 0; le < lv_ptr->lv_allocated_le; le++) { vg_ptr->pe_allocated--; for (p = 0; p < vg_ptr->pv_cur; p++) { - if (vg_ptr->pv[p]->pv_dev == - lv_ptr->lv_current_pe[le].dev) + if (kdev_same(vg_ptr->pv[p]->pv_dev, + lv_ptr->lv_current_pe[le].dev)) vg_ptr->pv[p]->pe_allocated--; } } @@ -2257,8 +2258,8 @@ for (l = 0; l < old_lv->lv_allocated_le; l++) { vg_ptr->pe_allocated--; for (p = 0; p < vg_ptr->pv_cur; p++) { - if (vg_ptr->pv[p]->pv_dev == - old_lv->lv_current_pe[l].dev) { + if (kdev_same(vg_ptr->pv[p]->pv_dev, + old_lv->lv_current_pe[l].dev)) { vg_ptr->pv[p]->pe_allocated--; break; } @@ -2269,8 +2270,8 @@ for (l = 0; l < new_lv->lv_allocated_le; l++) { vg_ptr->pe_allocated++; for (p = 0; p < vg_ptr->pv_cur; p++) { - if (vg_ptr->pv[p]->pv_dev == - new_lv->lv_current_pe[l].dev) { + if (kdev_same(vg_ptr->pv[p]->pv_dev, + new_lv->lv_current_pe[l].dev)) { vg_ptr->pv[p]->pe_allocated++; break; } @@ -2378,9 +2379,9 @@ old_lv->lv_allocated_le = new_lv->lv_allocated_le; old_lv->lv_current_le = new_lv->lv_current_le; old_lv->lv_current_pe = new_lv->lv_current_pe; - lvm_gendisk.part[MINOR(old_lv->lv_dev)].nr_sects = + lvm_gendisk.part[minor(old_lv->lv_dev)].nr_sects = old_lv->lv_size; - lvm_size[MINOR(old_lv->lv_dev)] = old_lv->lv_size >> 1; + lvm_size[minor(old_lv->lv_dev)] = old_lv->lv_size >> 1; if (old_lv->lv_access & LV_SNAPSHOT_ORG) { lv_t *snap; @@ -2393,9 +2394,9 @@ snap->lv_current_le = old_lv->lv_current_le; snap->lv_size = old_lv->lv_size; - lvm_gendisk.part[MINOR(snap->lv_dev)].nr_sects + lvm_gendisk.part[minor(snap->lv_dev)].nr_sects = old_lv->lv_size; - lvm_size[MINOR(snap->lv_dev)] = + lvm_size[minor(snap->lv_dev)] = old_lv->lv_size >> 1; __update_hardsectsize(snap); up_write(&snap->lv_lock); @@ -2523,7 +2524,9 @@ for ( l = 0; l < vg_ptr->lv_max; l++) { if ( vg_ptr->lv[l] == NULL) continue; - if ( vg_ptr->lv[l]->lv_dev == lv_status_bydev_req.dev) break; + if ( kdev_same(vg_ptr->lv[l]->lv_dev, + to_kdev_t(lv_status_bydev_req.dev))) + break; } if ( l == vg_ptr->lv_max) return -ENXIO; @@ -2564,7 +2567,7 @@ for (l = 0; l < vg_ptr->lv_max; l++) { if ( (lv_ptr = vg_ptr->lv[l]) == NULL) continue; - if (lv_ptr->lv_dev == lv->lv_dev) + if (kdev_same(lv_ptr->lv_dev, lv->lv_dev)) { lvm_fs_remove_lv(vg_ptr, lv_ptr); strncpy(lv_ptr->lv_name, diff -urN linux-2.5.2-pre8/drivers/md/md.c linux/drivers/md/md.c --- linux-2.5.2-pre8/drivers/md/md.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/md/md.c Sat Jan 5 14:43:16 2002 @@ -30,6 +30,7 @@ #include #include +#include #include #include #include @@ -139,9 +140,9 @@ void add_mddev_mapping(mddev_t * mddev, kdev_t dev, void *data) { - unsigned int minor = MINOR(dev); + unsigned int minor = minor(dev); - if (MAJOR(dev) != MD_MAJOR) { + if (major(dev) != MD_MAJOR) { MD_BUG(); return; } @@ -155,9 +156,9 @@ void del_mddev_mapping(mddev_t * mddev, kdev_t dev) { - unsigned int minor = MINOR(dev); + unsigned int minor = minor(dev); - if (MAJOR(dev) != MD_MAJOR) { + if (major(dev) != MD_MAJOR) { MD_BUG(); return; } @@ -185,7 +186,7 @@ { mddev_t *mddev; - if (MAJOR(dev) != MD_MAJOR) { + if (major(dev) != MD_MAJOR) { MD_BUG(); return 0; } @@ -195,7 +196,7 @@ memset(mddev, 0, sizeof(*mddev)); - mddev->__minor = MINOR(dev); + mddev->__minor = minor(dev); init_MUTEX(&mddev->reconfig_sem); init_MUTEX(&mddev->recovery_sem); init_MUTEX(&mddev->resync_sem); @@ -234,7 +235,7 @@ mdk_rdev_t *rdev; ITERATE_RDEV(mddev,rdev,tmp) { - if (rdev->dev == dev) + if (kdev_same(rdev->dev, dev)) return rdev; } return NULL; @@ -251,7 +252,7 @@ while (tmp != &device_names) { dname = list_entry(tmp, dev_name_t, list); - if (dname->dev == dev) + if (kdev_same(dname->dev, dev)) return dname->name; tmp = tmp->next; } @@ -266,7 +267,7 @@ hd = get_gendisk (dev); dname->name = NULL; if (hd) - dname->name = disk_name (hd, MINOR(dev), dname->namebuf); + dname->name = disk_name (hd, minor(dev), dname->namebuf); if (!dname->name) { sprintf (dname->namebuf, "[dev %s]", kdevname(dev)); dname->name = dname->namebuf; @@ -284,8 +285,8 @@ { unsigned int size = 0; - if (blk_size[MAJOR(dev)]) - size = blk_size[MAJOR(dev)][MINOR(dev)]; + if (blk_size[major(dev)]) + size = blk_size[major(dev)][minor(dev)]; if (persistent) size = MD_NEW_SIZE_BLOCKS(size); return size; @@ -559,10 +560,10 @@ struct gendisk *hd = get_gendisk(dev); if (!hd) - return 0; + return NODEV; mask = ~((1 << hd->minor_shift) - 1); - return MKDEV(MAJOR(dev), MINOR(dev) & mask); + return mk_kdev(major(dev), minor(dev) & mask); } static mdk_rdev_t * match_dev_unit(mddev_t *mddev, kdev_t dev) @@ -571,7 +572,7 @@ mdk_rdev_t *rdev; ITERATE_RDEV(mddev,rdev,tmp) - if (dev_unit(rdev->dev) == dev_unit(dev)) + if (kdev_same(dev_unit(rdev->dev), dev_unit(dev))) return rdev; return NULL; @@ -678,7 +679,7 @@ #ifndef MODULE md_autodetect_dev(rdev->dev); #endif - rdev->dev = 0; + rdev->dev = NODEV; rdev->faulty = 0; kfree(rdev); } @@ -731,7 +732,7 @@ while (atomic_read(&mddev->recovery_sem.count) != 1) schedule(); - del_mddev_mapping(mddev, MKDEV(MD_MAJOR, mdidx(mddev))); + del_mddev_mapping(mddev, mk_kdev(MD_MAJOR, mdidx(mddev))); list_del(&mddev->all_mddevs); INIT_LIST_HEAD(&mddev->all_mddevs); kfree(mddev); @@ -746,7 +747,7 @@ static void print_desc(mdp_disk_t *desc) { printk(" DISK\n", desc->number, - partition_name(MKDEV(desc->major,desc->minor)), + partition_name(mk_kdev(desc->major,desc->minor)), desc->major,desc->minor,desc->raid_disk,desc->state); } @@ -880,7 +881,7 @@ tmp = all_raid_disks.next; while (tmp != &all_raid_disks) { rdev = list_entry(tmp, mdk_rdev_t, all); - if (rdev->dev == dev) + if (kdev_same(rdev->dev, dev)) return rdev; tmp = tmp->next; } @@ -965,12 +966,12 @@ desc = mddev->sb->disks + i; #if 0 if (disk_faulty(desc)) { - if (MKDEV(desc->major,desc->minor) == rdev->dev) + if (mk_kdev(desc->major,desc->minor) == rdev->dev) ok = 1; continue; } #endif - if (MKDEV(desc->major,desc->minor) == rdev->dev) { + if (kdev_same(mk_kdev(desc->major,desc->minor), rdev->dev)) { rdev->sb->this_disk = *desc; rdev->desc_nr = desc->number; ok = 1; @@ -1105,8 +1106,8 @@ rdev->faulty = 0; size = 0; - if (blk_size[MAJOR(newdev)]) - size = blk_size[MAJOR(newdev)][MINOR(newdev)]; + if (blk_size[major(newdev)]) + size = blk_size[major(newdev)][minor(newdev)]; if (!size) { printk(KERN_WARNING "md: %s has zero size, marking faulty!\n", partition_name(newdev)); @@ -1127,11 +1128,11 @@ } if (rdev->sb->level != -4) { - rdev->old_dev = MKDEV(rdev->sb->this_disk.major, + rdev->old_dev = mk_kdev(rdev->sb->this_disk.major, rdev->sb->this_disk.minor); rdev->desc_nr = rdev->sb->this_disk.number; } else { - rdev->old_dev = MKDEV(0, 0); + rdev->old_dev = NODEV; rdev->desc_nr = -1; } } @@ -1297,7 +1298,7 @@ ev2 = md_event(sb); ev3 = ev2; --ev3; - if ((rdev->dev != rdev->old_dev) && + if (!kdev_same(rdev->dev, rdev->old_dev) && ((ev1 == ev2) || (ev1 == ev3))) { mdp_disk_t *desc; @@ -1308,15 +1309,15 @@ goto abort; } desc = &sb->disks[rdev->desc_nr]; - if (rdev->old_dev != MKDEV(desc->major, desc->minor)) { + if (!kdev_same( rdev->old_dev, mk_kdev(desc->major, desc->minor))) { MD_BUG(); goto abort; } - desc->major = MAJOR(rdev->dev); - desc->minor = MINOR(rdev->dev); + desc->major = major(rdev->dev); + desc->minor = minor(rdev->dev); desc = &rdev->sb->this_disk; - desc->major = MAJOR(rdev->dev); - desc->minor = MINOR(rdev->dev); + desc->major = major(rdev->dev); + desc->minor = minor(rdev->dev); } } @@ -1334,7 +1335,7 @@ kdev_t dev; desc = sb->disks + i; - dev = MKDEV(desc->major, desc->minor); + dev = mk_kdev(desc->major, desc->minor); /* * We kick faulty devices/descriptors immediately. @@ -1356,7 +1357,7 @@ break; } if (!found) { - if (dev == MKDEV(0,0)) + if (kdev_none(dev)) continue; printk(KERN_WARNING "md%d: removing former faulty %s!\n", mdidx(mddev), partition_name(dev)); @@ -1374,7 +1375,7 @@ remove_descriptor(desc, sb); } - if (dev == MKDEV(0,0)) + if (kdev_none(dev)) continue; /* * Is this device present in the rdev ring? @@ -1387,8 +1388,9 @@ * we cannot check rdev->number. * We can check the device though. */ - if ((sb->level == -4) && (rdev->dev == - MKDEV(desc->major,desc->minor))) { + if ((sb->level == -4) && + kdev_same(rdev->dev, + mk_kdev(desc->major,desc->minor))) { found = 1; break; } @@ -1415,9 +1417,9 @@ kdev_t dev; desc = sb->disks + i; - dev = MKDEV(desc->major, desc->minor); + dev = mk_kdev(desc->major, desc->minor); - if (dev == MKDEV(0,0)) + if (kdev_none(dev)) continue; if (disk_faulty(desc)) { @@ -1481,8 +1483,8 @@ * is the device unique? */ ITERATE_RDEV(mddev,rdev2,tmp2) { - if ((rdev2 != rdev) && - (rdev2->dev == rdev->dev)) { + if (rdev2 != rdev && + kdev_same(rdev2->dev, rdev->dev)) { MD_BUG(); goto abort; } @@ -1732,7 +1734,7 @@ * twice as large as sectors. */ md_hd_struct[mdidx(mddev)].start_sect = 0; - register_disk(&md_gendisk, MKDEV(MAJOR_NR,mdidx(mddev)), + register_disk(&md_gendisk, mk_kdev(MAJOR_NR,mdidx(mddev)), 1, &md_fops, md_size[mdidx(mddev)]<<1); read_ahead[MD_MAJOR] = 1024; @@ -1952,7 +1954,7 @@ * mostly sane superblocks. It's time to allocate the * mddev. */ - md_kdev = MKDEV(MD_MAJOR, rdev0->sb->md_minor); + md_kdev = mk_kdev(MD_MAJOR, rdev0->sb->md_minor); mddev = kdev_to_mddev(md_kdev); if (mddev) { printk(KERN_WARNING "md: md%d already running, cannot run %s\n", @@ -1966,7 +1968,7 @@ printk(KERN_ERR "md: cannot allocate memory for md drive.\n"); break; } - if (md_kdev == countdev) + if (kdev_same(md_kdev, countdev)) atomic_inc(&mddev->active); printk(KERN_INFO "md: created md%d\n", mdidx(mddev)); ITERATE_RDEV_GENERIC(candidates,pending,rdev,tmp) { @@ -2049,11 +2051,11 @@ kdev_t dev; desc = sb->disks + i; - dev = MKDEV(desc->major, desc->minor); + dev = mk_kdev(desc->major, desc->minor); - if (dev == MKDEV(0,0)) + if (kdev_none(dev)) continue; - if (dev == startdev) + if (kdev_same(dev, startdev)) continue; if (md_import_device(dev, 1)) { printk(KERN_WARNING "md: could not import %s, trying to run array nevertheless.\n", @@ -2178,7 +2180,7 @@ mdk_rdev_t *rdev; unsigned int nr; kdev_t dev; - dev = MKDEV(info->major,info->minor); + dev = mk_kdev(info->major,info->minor); if (find_rdev_all(dev)) { printk(KERN_WARNING "md: device %s already used in a RAID array!\n", @@ -2450,8 +2452,8 @@ } disk->raid_disk = disk->number; - disk->major = MAJOR(dev); - disk->minor = MINOR(dev); + disk->major = major(dev); + disk->minor = minor(dev); if (mddev->pers->diskop(mddev, &disk, DISKOP_HOT_ADD_DISK)) { MD_BUG(); @@ -2577,7 +2579,7 @@ return -EACCES; dev = inode->i_rdev; - minor = MINOR(dev); + minor = minor(dev); if (minor >= MAX_MD_DEVS) { MD_BUG(); return -EINVAL; @@ -2693,10 +2695,10 @@ /* * possibly make it lock the array ... */ - err = autostart_array((kdev_t)arg, dev); + err = autostart_array(val_to_kdev(arg), dev); if (err) { printk(KERN_WARNING "md: autostart %s failed!\n", - partition_name((kdev_t)arg)); + partition_name(val_to_kdev(arg))); goto abort; } goto done; @@ -2801,14 +2803,14 @@ goto done_unlock; } case HOT_GENERATE_ERROR: - err = hot_generate_error(mddev, (kdev_t)arg); + err = hot_generate_error(mddev, val_to_kdev(arg)); goto done_unlock; case HOT_REMOVE_DISK: - err = hot_remove_disk(mddev, (kdev_t)arg); + err = hot_remove_disk(mddev, val_to_kdev(arg)); goto done_unlock; case HOT_ADD_DISK: - err = hot_add_disk(mddev, (kdev_t)arg); + err = hot_add_disk(mddev, val_to_kdev(arg)); goto done_unlock; case SET_DISK_INFO: @@ -2828,7 +2830,7 @@ goto done_unlock; case SET_DISK_FAULTY: - err = set_disk_faulty(mddev, (kdev_t)arg); + err = set_disk_faulty(mddev, val_to_kdev(arg)); goto done_unlock; case RUN_ARRAY: @@ -3046,7 +3048,7 @@ mdk_rdev_t * rrdev; dprintk("md_error dev:(%d:%d), rdev:(%d:%d), (caller: %p,%p,%p,%p).\n", - MAJOR(dev),MINOR(dev),MAJOR(rdev),MINOR(rdev), + major(dev),minor(dev),major(rdev),minor(rdev), __builtin_return_address(0),__builtin_return_address(1), __builtin_return_address(2),__builtin_return_address(3)); @@ -3290,7 +3292,7 @@ static unsigned int sync_io[DK_MAX_MAJOR][DK_MAX_DISK]; void md_sync_acct(kdev_t dev, unsigned long nr_sectors) { - unsigned int major = MAJOR(dev); + unsigned int major = major(dev); unsigned int index; index = disk_index(dev); @@ -3309,7 +3311,7 @@ idle = 1; ITERATE_RDEV(mddev,rdev,tmp) { - int major = MAJOR(rdev->dev); + int major = major(rdev->dev); int idx = disk_index(rdev->dev); if ((idx >= DK_MAX_DISK) || (major >= DK_MAX_MAJOR)) @@ -3533,7 +3535,7 @@ if (!spare) continue; printk(KERN_INFO "md%d: resyncing spare disk %s to replace failed disk\n", - mdidx(mddev), partition_name(MKDEV(spare->major,spare->minor))); + mdidx(mddev), partition_name(mk_kdev(spare->major,spare->minor))); if (!mddev->pers->diskop) continue; if (mddev->pers->diskop(mddev, &spare, DISKOP_SPARE_WRITE)) @@ -3543,7 +3545,7 @@ err = md_do_sync(mddev, spare); if (err == -EIO) { printk(KERN_INFO "md%d: spare disk %s failed, skipping to next spare.\n", - mdidx(mddev), partition_name(MKDEV(spare->major,spare->minor))); + mdidx(mddev), partition_name(mk_kdev(spare->major,spare->minor))); if (!disk_faulty(spare)) { mddev->pers->diskop(mddev,&spare,DISKOP_SPARE_INACTIVE); mark_disk_faulty(spare); @@ -3868,7 +3870,7 @@ if (handle != 0) { unsigned major, minor; devfs_get_maj_min(handle, &major, &minor); - dev = MKDEV(major, minor); + dev = mk_kdev(major, minor); } if (!dev) { printk(KERN_WARNING "md: Unknown device name: %s\n", devname); @@ -3893,7 +3895,7 @@ } printk(KERN_INFO "md: Loading md%d: %s\n", minor, md_setup_args.device_names[minor]); - mddev = alloc_mddev(MKDEV(MD_MAJOR,minor)); + mddev = alloc_mddev(mk_kdev(MD_MAJOR,minor)); if (!mddev) { printk(KERN_ERR "md: kmalloc failed - cannot start array %d\n", minor); continue; @@ -3920,8 +3922,8 @@ dinfo.number = i; dinfo.raid_disk = i; dinfo.state = (1<sb->nr_disks++; mddev->sb->raid_disks++; mddev->sb->active_disks++; @@ -3931,8 +3933,8 @@ } else { /* persistent */ for (i = 0; (dev = devices[i]); i++) { - dinfo.major = MAJOR(dev); - dinfo.minor = MINOR(dev); + dinfo.major = major(dev); + dinfo.minor = minor(dev); add_new_disk (mddev, &dinfo); } } diff -urN linux-2.5.2-pre8/drivers/md/multipath.c linux/drivers/md/multipath.c --- linux-2.5.2-pre8/drivers/md/multipath.c Mon Nov 12 09:51:56 2001 +++ linux/drivers/md/multipath.c Sat Jan 5 14:43:16 2002 @@ -21,6 +21,7 @@ #include #include +#include #include #include @@ -353,7 +354,7 @@ * which has just failed. */ for (i = 0; i < disks; i++) { - if (multipaths[i].dev==dev && !multipaths[i].operational) + if (kdev_same(multipaths[i].dev, dev) && !multipaths[i].operational) return 0; } printk (LAST_DISK); @@ -362,7 +363,7 @@ * Mark disk as unusable */ for (i = 0; i < disks; i++) { - if (multipaths[i].dev==dev && multipaths[i].operational) { + if (kdev_same(multipaths[i].dev,dev) && multipaths[i].operational) { mark_disk_bad(mddev, i); break; } @@ -605,7 +606,7 @@ *d = failed_desc; - if (sdisk->dev == MKDEV(0,0)) + if (kdev_none(sdisk->dev)) sdisk->used_slot = 0; /* * this really activates the spare. @@ -630,7 +631,7 @@ err = 1; goto abort; } - rdisk->dev = MKDEV(0,0); + rdisk->dev = NODEV; rdisk->used_slot = 0; conf->nr_disks--; break; @@ -647,7 +648,7 @@ adisk->number = added_desc->number; adisk->raid_disk = added_desc->raid_disk; - adisk->dev = MKDEV(added_desc->major,added_desc->minor); + adisk->dev = mk_kdev(added_desc->major,added_desc->minor); adisk->operational = 0; adisk->spare = 1; @@ -710,7 +711,7 @@ dev = bh->b_dev; multipath_map (mddev, &bh->b_dev); - if (bh->b_dev == dev) { + if (kdev_same(bh->b_dev, dev)) { printk (IO_ERROR, partition_name(bh->b_dev), bh->b_blocknr); multipath_end_bh_io(mp_bh, 0); } else { diff -urN linux-2.5.2-pre8/drivers/md/raid1.c linux/drivers/md/raid1.c --- linux-2.5.2-pre8/drivers/md/raid1.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/md/raid1.c Sat Jan 5 14:43:16 2002 @@ -611,7 +611,7 @@ * else mark the drive as failed */ for (i = 0; i < disks; i++) - if (mirrors[i].dev == dev && mirrors[i].operational) + if (kdev_same(mirrors[i].dev, dev) && mirrors[i].operational) break; if (i == disks) return 0; @@ -853,7 +853,7 @@ *d = failed_desc; - if (sdisk->dev == MKDEV(0,0)) + if (kdev_none(sdisk->dev)) sdisk->used_slot = 0; /* * this really activates the spare. @@ -879,7 +879,7 @@ err = 1; goto abort; } - rdisk->dev = MKDEV(0,0); + rdisk->dev = NODEV; rdisk->used_slot = 0; conf->nr_disks--; break; @@ -896,7 +896,7 @@ adisk->number = added_desc->number; adisk->raid_disk = added_desc->raid_disk; - adisk->dev = MKDEV(added_desc->major, added_desc->minor); + adisk->dev = mk_kdev(added_desc->major, added_desc->minor); adisk->operational = 0; adisk->write_only = 0; @@ -1098,7 +1098,7 @@ case READA: dev = bio->bi_dev; map(mddev, &bio->bi_dev); - if (bio->bi_dev == dev) { + if (kdev_same(bio->bi_dev, dev)) { printk(IO_ERROR, partition_name(bio->bi_dev), r1_bio->sector); raid_end_bio_io(r1_bio, 0, 0); break; @@ -1428,7 +1428,7 @@ disk->number = descriptor->number; disk->raid_disk = disk_idx; - disk->dev = MKDEV(0,0); + disk->dev = NODEV; disk->operational = 0; disk->write_only = 0; diff -urN linux-2.5.2-pre8/drivers/md/raid5.c linux/drivers/md/raid5.c --- linux-2.5.2-pre8/drivers/md/raid5.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/md/raid5.c Sat Jan 5 14:43:16 2002 @@ -487,7 +487,7 @@ PRINTK("raid5_error called\n"); for (i = 0, disk = conf->disks; i < conf->raid_disks; i++, disk++) { - if (disk->dev == dev) { + if (kdev_same(disk->dev, dev)) { if (disk->operational) { disk->operational = 0; mark_disk_faulty(sb->disks+disk->number); @@ -513,7 +513,7 @@ */ if (conf->spare) { disk = conf->spare; - if (disk->dev == dev) { + if (kdev_same(disk->dev, dev)) { printk (KERN_ALERT "raid5: Disk failure on spare %s\n", partition_name (dev)); @@ -1460,7 +1460,7 @@ disk->number = desc->number; disk->raid_disk = raid_disk; - disk->dev = MKDEV(0,0); + disk->dev = NODEV; disk->operational = 0; disk->write_only = 0; @@ -1919,7 +1919,7 @@ *d = failed_desc; - if (sdisk->dev == MKDEV(0,0)) + if (kdev_none(sdisk->dev)) sdisk->used_slot = 0; /* @@ -1947,7 +1947,7 @@ err = 1; goto abort; } - rdisk->dev = MKDEV(0,0); + rdisk->dev = NODEV; rdisk->used_slot = 0; break; @@ -1964,7 +1964,7 @@ adisk->number = added_desc->number; adisk->raid_disk = added_desc->raid_disk; - adisk->dev = MKDEV(added_desc->major,added_desc->minor); + adisk->dev = mk_kdev(added_desc->major,added_desc->minor); adisk->operational = 0; adisk->write_only = 0; diff -urN linux-2.5.2-pre8/drivers/md/xor.c linux/drivers/md/xor.c --- linux-2.5.2-pre8/drivers/md/xor.c Sun Sep 30 12:26:06 2001 +++ linux/drivers/md/xor.c Sat Jan 5 14:43:16 2002 @@ -19,6 +19,7 @@ #define BH_TRACE 0 #include #include +#include #include #include diff -urN linux-2.5.2-pre8/drivers/media/video/tvmixer.c linux/drivers/media/video/tvmixer.c --- linux-2.5.2-pre8/drivers/media/video/tvmixer.c Wed Oct 17 14:19:20 2001 +++ linux/drivers/media/video/tvmixer.c Sat Jan 5 14:43:16 2002 @@ -177,7 +177,7 @@ static int tvmixer_open(struct inode *inode, struct file *file) { - int i, minor = MINOR(inode->i_rdev); + int i, minor = minor(inode->i_rdev); struct TVMIXER *mix = NULL; struct i2c_client *client = NULL; diff -urN linux-2.5.2-pre8/drivers/scsi/pci2000.c linux/drivers/scsi/pci2000.c --- linux-2.5.2-pre8/drivers/scsi/pci2000.c Sat Jan 5 14:43:13 2002 +++ linux/drivers/scsi/pci2000.c Sat Jan 5 14:43:16 2002 @@ -389,7 +389,7 @@ OpDone (SCpnt, DID_OK << 16); irq_return: - spin_unlock_irqrestore(&shost->host_flag, flags); + spin_unlock_irqrestore(&shost->host_lock, flags); out:; } /**************************************************************** diff -urN linux-2.5.2-pre8/fs/ext3/super.c linux/fs/ext3/super.c --- linux-2.5.2-pre8/fs/ext3/super.c Sat Jan 5 14:43:13 2002 +++ linux/fs/ext3/super.c Sat Jan 5 14:43:17 2002 @@ -56,10 +56,10 @@ static void make_rdonly(kdev_t dev, int *no_write) { - if (dev) { + if (kdev_val(dev)) { printk(KERN_WARNING "Turning device %s read-only\n", bdevname(dev)); - *no_write = 0xdead0000 + dev; + *no_write = 0xdead0000 + kdev_val(dev); } } diff -urN linux-2.5.2-pre8/fs/sysv/ChangeLog linux/fs/sysv/ChangeLog --- linux-2.5.2-pre8/fs/sysv/ChangeLog Sat Jan 5 14:43:14 2002 +++ linux/fs/sysv/ChangeLog Sat Jan 5 14:43:18 2002 @@ -1,3 +1,41 @@ +Fri Jan 4 2001 Alexander Viro + + * ialloc.c (sysv_free_inode): Use sb->s_id instead of bdevname(). + * inode.c (sysv_read_inode): Likewise. + (sysv_update_inode): Likewise. + (sysv_sync_inode): Likewise. + * super.c (detect_sysv): Likewise. + (complete_read_super): Likewise. + (sysv_read_super): Likewise. + (v7_read_super): Likewise. + +Sun Dec 30 2001 Manfred Spraul + + * dir.c (dir_commit_chunk): Do not set dir->i_version. + (sysv_readdir): Likewise. + +Thu Dec 27 2001 Alexander Viro + + * itree.c (get_block): Use map_bh() to fill out bh_result. + +Tue Dec 25 2001 Alexander Viro + + * super.c (sysv_read_super): Use sb_set_blocksize() to set blocksize. + (v7_read_super): Likewise. + +Tue Nov 27 2001 Alexander Viro + + * itree.c (get_block): Change type for iblock argument to sector_t. + * super.c (sysv_read_super): Set s_blocksize early. + (v7_read_super): Likewise. + * balloc.c (sysv_new_block): Use sb_bread(). instead of bread(). + (sysv_count_free_blocks): Likewise. + * ialloc.c (sysv_raw_inode): Likewise. + * itree.c (get_branch): Likewise. + (free_branches): Likewise. + * super.c (sysv_read_super): Likewise. + (v7_read_super): Likewise. + Sat Dec 15 2001 Christoph Hellwig * inode.c (sysv_read_inode): Mark inode as bad in case of failure. diff -urN linux-2.5.2-pre8/include/asm-arm/arch-adifcc/adi_evb.h linux/include/asm-arm/arch-adifcc/adi_evb.h --- linux-2.5.2-pre8/include/asm-arm/arch-adifcc/adi_evb.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-adifcc/adi_evb.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,19 @@ +/* + * linux/include/asm/arch-80200fcc/adi_evb.h + * + * ADI 80200FCC evaluation board definitions + * + * Author: Deepak Saxena + * + * Copyright (C) 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#define ADI_EVB__RAMBASE 0xa0000000 +#define ADI_EVB__UART 0x00400000 /* UART */ +#define ADI_EVB_7SEG_1 0x00500000 /* 7-Segment */ + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-adifcc/dma.h linux/include/asm-arm/arch-adifcc/dma.h --- linux-2.5.2-pre8/include/asm-arm/arch-adifcc/dma.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-adifcc/dma.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,18 @@ +/* + * linux/include/asm-arm/arch-80200fcc/dma.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff + +/* No DMA */ +#define MAX_DMA_CHANNELS 0 + +#endif /* _ASM_ARCH_DMA_H */ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-adifcc/hardware.h linux/include/asm-arm/arch-adifcc/hardware.h --- linux-2.5.2-pre8/include/asm-arm/arch-adifcc/hardware.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-adifcc/hardware.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,27 @@ +/* + * linux/include/asm-arm/arch-adifcc/hardware.h + * + * Hardware definitions for ADI based systems + * + * Author: Deepak Saxena + * + * Copyright (C) 2000-2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include + +#define PCIO_BASE 0 + +#if defined(CONFIG_ARCH_ADI_EVB) +#include "adi_evb.h" +#endif + +#endif /* _ASM_ARCH_HARDWARE_H */ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-adifcc/io.h linux/include/asm-arm/arch-adifcc/io.h --- linux-2.5.2-pre8/include/asm-arm/arch-adifcc/io.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-adifcc/io.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,22 @@ +/* + * linux/include/asm-arm/arch-adifcc/io.h + * + * Author: Deepak Saxena + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) (PCIO_BASE + (a)) +#define __mem_pci(a) ((unsigned long)(a)) +#define __mem_isa(a) ((unsigned long)(a)) + +#endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-adifcc/irq.h linux/include/asm-arm/arch-adifcc/irq.h --- linux-2.5.2-pre8/include/asm-arm/arch-adifcc/irq.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-adifcc/irq.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,13 @@ +/* + * linux/include/asm-arm/arch-adifcc/irq.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define fixup_irq(irq) (irq) + + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-adifcc/irqs.h linux/include/asm-arm/arch-adifcc/irqs.h --- linux-2.5.2-pre8/include/asm-arm/arch-adifcc/irqs.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-adifcc/irqs.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,28 @@ +/* + * linux/include/asm-arm/arch-80200fcc/irqs.h + * + * Author: Deepak Saxena + * Copyright: (C) 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define IRQ_XS80200_BCU 0 /* Bus Control Unit */ +#define IRQ_XS80200_PMU 1 /* Performance Monitoring Unit */ +#define IRQ_XS80200_EXTIRQ 2 /* external IRQ signal */ +#define IRQ_XS80200_EXTFIQ 3 /* external IRQ signal */ + +#define NR_XS80200_IRQS 4 +#define NR_IRQS NR_XS80200_IRQS + +#define IRQ_XSCALE_PMU IRQ_XS80200_PMU + +#ifdef CONFIG_XSCALE_ADI_EVB + +/* Interrupts available on the ADI Eval Board */ + +#endif + + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-adifcc/memory.h linux/include/asm-arm/arch-adifcc/memory.h --- linux-2.5.2-pre8/include/asm-arm/arch-adifcc/memory.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-adifcc/memory.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,57 @@ +/* + * linux/include/asm-arm/arch-adifcc/memory.h + * + * Copyright (c) 2001 MontaVista Software, Inc. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + + +/* + * Task size: 3GB + */ +#define TASK_SIZE (0xc0000000UL) +#define TASK_SIZE_26 (0x04000000UL) + +/* + * This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) + +/* + * Page offset: 3GB + */ +#define PAGE_OFFSET (0xc0000000UL) + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET (0xC0000000UL) + +/* + * physical vs virtual ram conversion + */ +#define __virt_to_phys__is_a_macro +#define __phys_to_virt__is_a_macro +#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) +#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + * + * These are dummies for now. + */ +#define __virt_to_bus__is_a_macro +#define __bus_to_virt__is_a_macro +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#define PHYS_TO_NID(x) 0 + +#endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-adifcc/param.h linux/include/asm-arm/arch-adifcc/param.h --- linux-2.5.2-pre8/include/asm-arm/arch-adifcc/param.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-adifcc/param.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,3 @@ +/* + * linux/include/asm-arm/arch-adifcc/param.h + */ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-adifcc/serial.h linux/include/asm-arm/arch-adifcc/serial.h --- linux-2.5.2-pre8/include/asm-arm/arch-adifcc/serial.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-adifcc/serial.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,36 @@ +/* + * include/asm-arm/arch-adifcc/serial.h + * + * Author: Deepak Saxena + * + * Copyright (c) 2001 MontaVista Software, Inc. + */ + + +/* + * This assumes you have a 1.8432 MHz clock for your UART. + * + * It'd be nice if someone built a serial card with a 24.576 MHz + * clock, since the 16550A is capable of handling a top speed of 1.5 + * megabits/second; but this requires the faster clock. + */ +#define BASE_BAUD ( 1852000 / 16 ) + +/* Standard COM flags */ +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) + +#ifdef CONFIG_ARCH_ADI_EVB + +#define RS_TABLE_SIZE 1 + +/* + * One serial port, int goes to FIQ, so we run in polled mode + */ +#define STD_SERIAL_PORT_DEFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0xff400000, 0, STD_COM_FLAGS } /* ttyS0 */ + +#define EXTRA_SERIAL_PORT_DEFNS + +#endif + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-adifcc/system.h linux/include/asm-arm/arch-adifcc/system.h --- linux-2.5.2-pre8/include/asm-arm/arch-adifcc/system.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-adifcc/system.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,29 @@ +/* + * linux/include/asm-arm/arch-adifcc/system.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +static inline void arch_idle(void) +{ +#if 0 + if (!hlt_counter) + cpu_do_idle(0); +#endif +} + + +static inline void arch_reset(char mode) +{ + if ( 1 && mode == 's') { + /* Jump into ROM at address 0 */ + cpu_reset(0); + } else { + /* Use on-chip reset capability */ + } +} + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-adifcc/time.h linux/include/asm-arm/arch-adifcc/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-adifcc/time.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-adifcc/time.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,9 @@ +/* + * linux/include/asm-arm/arch-adifcc/time.h + * + */ + +/* + * No on board timer, implemenation @ arch/arm/kernel/xscale-time.c + */ + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-adifcc/timex.h linux/include/asm-arm/arch-adifcc/timex.h --- linux-2.5.2-pre8/include/asm-arm/arch-adifcc/timex.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-adifcc/timex.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,10 @@ +/* + * linux/include/asm-arm/arch-adifcc/timex.h + * + * XScale architecture timex specifications + */ + +/* This is for a timer based on the XS80200's PMU counter */ + +#define CLOCK_TICK_RATE 600000000 /* Underlying HZ */ + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-adifcc/uncompress.h linux/include/asm-arm/arch-adifcc/uncompress.h --- linux-2.5.2-pre8/include/asm-arm/arch-adifcc/uncompress.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-adifcc/uncompress.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,35 @@ +/* + * linux/include/asm-arm/arch-adifcc/uncompress.h + * + * Author: Deepak Saxena + * + * Copyright (c) 2001 MontaVista Software, Inc. + * + */ + +#define UART_BASE ((volatile unsigned char *)0x00400000) + +static __inline__ void putc(char c) +{ + while ((UART_BASE[5] & 0x60) != 0x60); + UART_BASE[0] = c; +} + +/* + * This does not append a newline + */ +static void puts(const char *s) +{ + while (*s) { + putc(*s); + if (*s == '\n') + putc('\r'); + s++; + } +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff -urN linux-2.5.2-pre8/include/asm-arm/arch-adifcc/vmalloc.h linux/include/asm-arm/arch-adifcc/vmalloc.h --- linux-2.5.2-pre8/include/asm-arm/arch-adifcc/vmalloc.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-adifcc/vmalloc.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,16 @@ +/* + * linux/include/asm-arm/arch-adifcc/vmalloc.h + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) +#define VMALLOC_END (0xe8000000) diff -urN linux-2.5.2-pre8/include/asm-arm/arch-anakin/io.h linux/include/asm-arm/arch-anakin/io.h --- linux-2.5.2-pre8/include/asm-arm/arch-anakin/io.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-anakin/io.h Sat Jan 5 14:43:18 2002 @@ -17,12 +17,7 @@ #define IO_SPACE_LIMIT 0xffffffff -#define __io(a) a -#define __arch_getw(a) (*(volatile unsigned short *) (a)) -#define __arch_putw(b, a) (*(volatile unsigned short *) (a) = (b)) - -#define iomem_valid_addr(i, s) 1 -#define iomem_to_phys(i) i +#define __io(a) (a) /* * We don't support ins[lb]/outs[lb]. Make them fault. diff -urN linux-2.5.2-pre8/include/asm-arm/arch-anakin/time.h linux/include/asm-arm/arch-anakin/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-anakin/time.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-anakin/time.h Sat Jan 5 14:43:18 2002 @@ -20,8 +20,7 @@ do_timer(regs); } -static inline void -setup_timer(void) +void __init time_init(void) { timer_irq.handler = anakin_timer_interrupt; timer_irq.flags = SA_INTERRUPT; diff -urN linux-2.5.2-pre8/include/asm-arm/arch-arc/io.h linux/include/asm-arm/arch-arc/io.h --- linux-2.5.2-pre8/include/asm-arm/arch-arc/io.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-arc/io.h Sat Jan 5 14:43:18 2002 @@ -249,4 +249,10 @@ /* the following macro is depreciated */ #define ioaddr(port) __ioaddr((port)) +/* + * No ioremap support here. + */ +#define __arch_ioremap(c,s,f) ((void *)(c)) +#define __arch_iounmap(c) do { } while (0) + #endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-arc/irq.h linux/include/asm-arm/arch-arc/irq.h --- linux-2.5.2-pre8/include/asm-arm/arch-arc/irq.h Thu Apr 12 12:20:31 2001 +++ linux/include/asm-arm/arch-arc/irq.h Sat Jan 5 14:43:18 2002 @@ -6,143 +6,5 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * - * Changelog: - * 24-09-1996 RMK Created - * 10-10-1996 RMK Brought up to date with arch-sa110eval - * 22-10-1996 RMK Changed interrupt numbers & uses new inb/outb macros - * 11-01-1998 RMK Added mask_and_ack_irq - * 22-08-1998 RMK Restructured IRQ routines */ -#include -#include -#include - -#ifdef CONFIG_ARCH_ARC -#define a_clf() clf() -#define a_stf() stf() -#else -#define a_clf() do { } while (0) -#define a_stf() do { } while (0) -#endif - #define fixup_irq(x) (x) - -static void arc_mask_irq_ack_a(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << irq; - a_clf(); - val = ioc_readb(IOC_IRQMASKA); - ioc_writeb(val & ~mask, IOC_IRQMASKA); - ioc_writeb(mask, IOC_IRQCLRA); - a_stf(); -} - -static void arc_mask_irq_a(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << irq; - a_clf(); - val = ioc_readb(IOC_IRQMASKA); - ioc_writeb(val & ~mask, IOC_IRQMASKA); - a_stf(); -} - -static void arc_unmask_irq_a(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << irq; - a_clf(); - val = ioc_readb(IOC_IRQMASKA); - ioc_writeb(val | mask, IOC_IRQMASKA); - a_stf(); -} - -static void arc_mask_irq_b(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = ioc_readb(IOC_IRQMASKB); - ioc_writeb(val & ~mask, IOC_IRQMASKB); -} - -static void arc_unmask_irq_b(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = ioc_readb(IOC_IRQMASKB); - ioc_writeb(val | mask, IOC_IRQMASKB); -} - -static void arc_mask_irq_fiq(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = ioc_readb(IOC_FIQMASK); - ioc_writeb(val & ~mask, IOC_FIQMASK); -} - -static void arc_unmask_irq_fiq(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = ioc_readb(IOC_FIQMASK); - ioc_writeb(val | mask, IOC_FIQMASK); -} - -static __inline__ void irq_init_irq(void) -{ - int irq; - - ioc_writeb(0, IOC_IRQMASKA); - ioc_writeb(0, IOC_IRQMASKB); - ioc_writeb(0, IOC_FIQMASK); - - for (irq = 0; irq < NR_IRQS; irq++) { - switch (irq) { - case 0 ... 6: - irq_desc[irq].probe_ok = 1; - irq_desc[irq].valid = 1; - irq_desc[irq].mask_ack = arc_mask_irq_ack_a; - irq_desc[irq].mask = arc_mask_irq_a; - irq_desc[irq].unmask = arc_unmask_irq_a; - break; - - case 7: - irq_desc[irq].noautoenable = 1; - irq_desc[irq].valid = 1; - irq_desc[irq].mask_ack = arc_mask_irq_ack_a; - irq_desc[irq].mask = arc_mask_irq_a; - irq_desc[irq].unmask = arc_unmask_irq_a; - break; - - case 9 ... 15: - irq_desc[irq].probe_ok = 1; - case 8: - irq_desc[irq].valid = 1; - irq_desc[irq].mask_ack = arc_mask_irq_b; - irq_desc[irq].mask = arc_mask_irq_b; - irq_desc[irq].unmask = arc_unmask_irq_b; - break; - - case 64 ... 72: - irq_desc[irq].valid = 1; - irq_desc[irq].mask_ack = arc_mask_irq_fiq; - irq_desc[irq].mask = arc_mask_irq_fiq; - irq_desc[irq].unmask = arc_unmask_irq_fiq; - break; - } - } - - irq_desc[IRQ_KEYBOARDTX].noautoenable = 1; - - init_FIQ(); -} diff -urN linux-2.5.2-pre8/include/asm-arm/arch-arc/time.h linux/include/asm-arm/arch-arc/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-arc/time.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-arc/time.h Sat Jan 5 14:43:18 2002 @@ -24,7 +24,7 @@ /* * Set up timer interrupt. */ -static inline void setup_timer(void) +void __init time_init(void) { ioctime_init(); diff -urN linux-2.5.2-pre8/include/asm-arm/arch-cl7500/irq.h linux/include/asm-arm/arch-cl7500/irq.h --- linux-2.5.2-pre8/include/asm-arm/arch-cl7500/irq.h Thu Apr 12 12:20:31 2001 +++ linux/include/asm-arm/arch-cl7500/irq.h Sat Jan 5 14:43:18 2002 @@ -30,198 +30,3 @@ return irq; } - -static void cl7500_mask_irq_ack_a(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << irq; - val = iomd_readb(IOMD_IRQMASKA); - iomd_writeb(val & ~mask, IOMD_IRQMASKA); - iomd_writeb(mask, IOMD_IRQCLRA); -} - -static void cl7500_mask_irq_a(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << irq; - val = iomd_readb(IOMD_IRQMASKA); - iomd_writeb(val & ~mask, IOMD_IRQMASKA); -} - -static void cl7500_unmask_irq_a(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << irq; - val = iomd_readb(IOMD_IRQMASKA); - iomd_writeb(val | mask, IOMD_IRQMASKA); -} - -static void cl7500_mask_irq_b(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_IRQMASKB); - iomd_writeb(val & ~mask, IOMD_IRQMASKB); -} - -static void cl7500_unmask_irq_b(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_IRQMASKB); - iomd_writeb(val | mask, IOMD_IRQMASKB); -} - -static void cl7500_mask_irq_c(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_IRQMASKC); - iomd_writeb(val & ~mask, IOMD_IRQMASKC); -} - -static void cl7500_unmask_irq_c(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_IRQMASKC); - iomd_writeb(val | mask, IOMD_IRQMASKC); -} - - -static void cl7500_mask_irq_d(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_IRQMASKD); - iomd_writeb(val & ~mask, IOMD_IRQMASKD); -} - -static void cl7500_unmask_irq_d(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_IRQMASKD); - iomd_writeb(val | mask, IOMD_IRQMASKD); -} - -static void cl7500_mask_irq_dma(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_DMAMASK); - iomd_writeb(val & ~mask, IOMD_DMAMASK); -} - -static void cl7500_unmask_irq_dma(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_DMAMASK); - iomd_writeb(val | mask, IOMD_DMAMASK); -} - -static void cl7500_mask_irq_fiq(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_FIQMASK); - iomd_writeb(val & ~mask, IOMD_FIQMASK); -} - -static void cl7500_unmask_irq_fiq(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_FIQMASK); - iomd_writeb(val | mask, IOMD_FIQMASK); -} - -static void no_action(int cpl, void *dev_id, struct pt_regs *regs) -{ -} - -static struct irqaction irq_isa = { no_action, 0, 0, "isa", NULL, NULL }; - -static __inline__ void irq_init_irq(void) -{ - int irq; - - iomd_writeb(0, IOMD_IRQMASKA); - iomd_writeb(0, IOMD_IRQMASKB); - iomd_writeb(0, IOMD_FIQMASK); - iomd_writeb(0, IOMD_DMAMASK); - - for (irq = 0; irq < NR_IRQS; irq++) { - switch (irq) { - case 0 ... 6: - irq_desc[irq].probe_ok = 1; - case 7: - irq_desc[irq].valid = 1; - irq_desc[irq].mask_ack = cl7500_mask_irq_ack_a; - irq_desc[irq].mask = cl7500_mask_irq_a; - irq_desc[irq].unmask = cl7500_unmask_irq_a; - break; - - case 9 ... 15: - irq_desc[irq].probe_ok = 1; - case 8: - irq_desc[irq].valid = 1; - irq_desc[irq].mask_ack = cl7500_mask_irq_b; - irq_desc[irq].mask = cl7500_mask_irq_b; - irq_desc[irq].unmask = cl7500_unmask_irq_b; - break; - - case 16 ... 22: - irq_desc[irq].valid = 1; - irq_desc[irq].mask_ack = cl7500_mask_irq_dma; - irq_desc[irq].mask = cl7500_mask_irq_dma; - irq_desc[irq].unmask = cl7500_unmask_irq_dma; - break; - - case 24 ... 31: - irq_desc[irq].valid = 1; - irq_desc[irq].mask_ack = cl7500_mask_irq_c; - irq_desc[irq].mask = cl7500_mask_irq_c; - irq_desc[irq].unmask = cl7500_unmask_irq_c; - break; - - case 40 ... 47: - irq_desc[irq].valid = 1; - irq_desc[irq].mask_ack = cl7500_mask_irq_d; - irq_desc[irq].mask = cl7500_mask_irq_d; - irq_desc[irq].unmask = cl7500_unmask_irq_d; - break; - - case 48 ... 55: - irq_desc[irq].valid = 1; - irq_desc[irq].probe_ok = 1; - irq_desc[irq].mask_ack = no_action; - irq_desc[irq].mask = no_action; - irq_desc[irq].unmask = no_action; - break; - - case 64 ... 72: - irq_desc[irq].valid = 1; - irq_desc[irq].mask_ack = cl7500_mask_irq_fiq; - irq_desc[irq].mask = cl7500_mask_irq_fiq; - irq_desc[irq].unmask = cl7500_unmask_irq_fiq; - break; - } - } - - setup_arm_irq(IRQ_ISA, &irq_isa); -} diff -urN linux-2.5.2-pre8/include/asm-arm/arch-cl7500/keyboard.h linux/include/asm-arm/arch-cl7500/keyboard.h --- linux-2.5.2-pre8/include/asm-arm/arch-cl7500/keyboard.h Thu Oct 25 13:53:53 2001 +++ linux/include/asm-arm/arch-cl7500/keyboard.h Sat Jan 5 14:43:18 2002 @@ -6,6 +6,7 @@ * * Copyright (C) 1998-2001 Russell King */ +#include #define NR_SCANCODES 128 extern int ps2kbd_init_hw(void); diff -urN linux-2.5.2-pre8/include/asm-arm/arch-cl7500/time.h linux/include/asm-arm/arch-cl7500/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-cl7500/time.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-cl7500/time.h Sat Jan 5 14:43:18 2002 @@ -9,6 +9,8 @@ * 04-Dec-1997 RMK Updated for new arch/arm/time.c */ +extern void ioctime_init(void); + static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { do_timer(regs); @@ -29,9 +31,8 @@ /* * Set up timer interrupt. */ -static inline void setup_timer(void) +void __init time_init(void) { - extern void ioctime_init(void); ioctime_init(); timer_irq.handler = timer_interrupt; diff -urN linux-2.5.2-pre8/include/asm-arm/arch-clps711x/autcpu12.h linux/include/asm-arm/arch-clps711x/autcpu12.h --- linux-2.5.2-pre8/include/asm-arm/arch-clps711x/autcpu12.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-clps711x/autcpu12.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,78 @@ +/* + * AUTCPU12 specific defines + * + * (c) 2001 Thomas Gleixner, autronix automation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_AUTCPU12_H +#define __ASM_ARCH_AUTCPU12_H + +/* + * The CS8900A ethernet chip has its I/O registers wired to chip select 2 + * (nCS2). This is the mapping for it. + */ +#define AUTCPU12_PHYS_CS8900A CS2_PHYS_BASE /* physical */ +#define AUTCPU12_VIRT_CS8900A (0xfe000000) /* virtual */ + +/* + * The flash bank is wired to chip select 0 + */ +#define AUTCPU12_PHYS_FLASH CS0_PHYS_BASE /* physical */ + +/* offset for device specific information structure */ +#define AUTCPU12_LCDINFO_OFFS (0x00010000) +/* +* Videomemory is the internal SRAM (CS 6) +*/ +#define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE +#define AUTCPU12_VIRT_VIDEO (0xfd000000) + +/* +* All special IO's are tied to CS1 +*/ +#define AUTCPU12_PHYS_CHAR_LCD CS1_PHYS_BASE +0x00000000 /* physical */ + +#define AUTCPU12_PHYS_NVRAM CS1_PHYS_BASE +0x02000000 /* physical */ + +#define AUTCPU12_PHYS_CSAUX1 CS1_PHYS_BASE +0x04000000 /* physical */ + +#define AUTCPU12_PHYS_SMC CS1_PHYS_BASE +0x06000000 /* physical */ + +#define AUTCPU12_PHYS_CAN CS1_PHYS_BASE +0x08000000 /* physical */ + +#define AUTCPU12_PHYS_TOUCH CS1_PHYS_BASE +0x0A000000 /* physical */ + +#define AUTCPU12_PHYS_IO CS1_PHYS_BASE +0x0C000000 /* physical */ + +#define AUTCPU12_PHYS_LPT CS1_PHYS_BASE +0x0E000000 /* physical */ + +/* +* defines for smartmedia card access +*/ +#define AUTCPU12_SMC_RDY (1<<2) +#define AUTCPU12_SMC_ALE (1<<3) +#define AUTCPU12_SMC_CLE (1<<4) +#define AUTCPU12_SMC_PORT_OFFSET PBDR +#define AUTCPU12_SMC_SELECT_OFFSET 0x10 +/* +* defines for lcd contrast +*/ +#define AUTCPU12_DPOT_PORT_OFFSET PEDR +#define AUTCPU12_DPOT_CS (1<<0) +#define AUTCPU12_DPOT_CLK (1<<1) +#define AUTCPU12_DPOT_UD (1<<2) + +#endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-clps711x/dma.h linux/include/asm-arm/arch-clps711x/dma.h --- linux-2.5.2-pre8/include/asm-arm/arch-clps711x/dma.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-clps711x/dma.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,28 @@ +/* + * linux/include/asm-arm/arch-clps711x/dma.h + * + * Copyright (C) 1997,1998 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff + +#define MAX_DMA_CHANNELS 0 + +#endif /* _ASM_ARCH_DMA_H */ + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-clps711x/hardware.h linux/include/asm-arm/arch-clps711x/hardware.h --- linux-2.5.2-pre8/include/asm-arm/arch-clps711x/hardware.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-clps711x/hardware.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,179 @@ +/* + * linux/include/asm-arm/arch-clps711x/hardware.h + * + * This file contains the hardware definitions of the Prospector P720T. + * + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include + +#define CLPS7111_VIRT_BASE 0xff000000 +#define CLPS7111_BASE CLPS7111_VIRT_BASE + +/* + * The physical addresses that the external chip select signals map to is + * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212 + * processors. CONFIG_EP72XX_BOOT_ROM is only available if these + * processors are in use. + */ +#ifndef CONFIG_EP72XX_ROM_BOOT +#define CS0_PHYS_BASE (0x00000000) +#define CS1_PHYS_BASE (0x10000000) +#define CS2_PHYS_BASE (0x20000000) +#define CS3_PHYS_BASE (0x30000000) +#define CS4_PHYS_BASE (0x40000000) +#define CS5_PHYS_BASE (0x50000000) +#define CS6_PHYS_BASE (0x60000000) +#define CS7_PHYS_BASE (0x70000000) +#else +#define CS0_PHYS_BASE (0x70000000) +#define CS1_PHYS_BASE (0x60000000) +#define CS2_PHYS_BASE (0x50000000) +#define CS3_PHYS_BASE (0x40000000) +#define CS4_PHYS_BASE (0x30000000) +#define CS5_PHYS_BASE (0x20000000) +#define CS6_PHYS_BASE (0x10000000) +#define CS7_PHYS_BASE (0x00000000) +#endif + +#if defined (CONFIG_ARCH_EP7211) + +#define EP7211_VIRT_BASE CLPS7111_VIRT_BASE +#define EP7211_BASE CLPS7111_VIRT_BASE +#include + +#elif defined (CONFIG_ARCH_EP7212) + +#define EP7212_VIRT_BASE CLPS7111_VIRT_BASE +#define EP7212_BASE CLPS7111_VIRT_BASE +#include + + +#endif + +#define SYSPLD_VIRT_BASE 0xfe000000 +#define SYSPLD_BASE SYSPLD_VIRT_BASE + +#ifndef __ASSEMBLER__ + +#define PCIO_BASE IO_BASE + +#endif + + +#if defined (CONFIG_ARCH_AUTCPU12) + +#define CS89712_VIRT_BASE CLPS7111_VIRT_BASE +#define CS89712_BASE CLPS7111_VIRT_BASE + +#include +#include +#include + +#endif + + +#if defined (CONFIG_ARCH_CDB89712) + +#include +#include +#include + +/* dynamic ioremap() areas */ +#define FLASH_START 0x00000000 +#define FLASH_SIZE 0x800000 +#define FLASH_WIDTH 4 + +#define SRAM_START 0x60000000 +#define SRAM_SIZE 0xc000 +#define SRAM_WIDTH 4 + +#define BOOTROM_START 0x70000000 +#define BOOTROM_SIZE 0x80 +#define BOOTROM_WIDTH 4 + + +/* static cdb89712_map_io() areas */ +#define REGISTER_START 0x80000000 +#define REGISTER_SIZE 0x4000 +#define REGISTER_BASE 0xff000000 + +#define ETHER_START 0x20000000 +#define ETHER_SIZE 0x1000 +#define ETHER_BASE 0xfe000000 + +#endif + + +#if defined (CONFIG_ARCH_EDB7211) + +/* + * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3) + * and repeat across it. This is the mapping for it. + * + * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This + * was cause for much consternation and headscratching. This should probably + * be made a compile/run time kernel option. + */ +#define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */ + +#define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */ + + +/* + * The CS8900A ethernet chip has its I/O registers wired to chip select 2 + * (nCS2). This is the mapping for it. + * + * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This + * was cause for much consternation and headscratching. This should probably + * be made a compile/run time kernel option. + */ +#define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */ + +#define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */ + + +/* + * The two flash banks are wired to chip selects 0 and 1. This is the mapping + * for them. + * + * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running + * in jumpered boot mode. + */ +#define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */ +#define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */ + +#define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */ +#define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */ + +#endif /* CONFIG_ARCH_EDB7211 */ + + +/* + * Relevant bits in port D, which controls power to the various parts of + * the LCD on the EDB7211. + */ +#define EDB_PD1_LCD_DC_DC_EN (1<<1) +#define EDB_PD2_LCDEN (1<<2) +#define EDB_PD3_LCDBL (1<<3) + + +#endif + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-clps711x/io.h linux/include/asm-arm/arch-clps711x/io.h --- linux-2.5.2-pre8/include/asm-arm/arch-clps711x/io.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-clps711x/io.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,37 @@ +/* + * linux/include/asm-arm/arch-clps711x/io.h + * + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) ((a)) +#define __mem_pci(a) ((unsigned long)(a)) +#define __mem_isa(a) ((unsigned long)(a)) + +/* + * We don't support ins[lb]/outs[lb]. Make them fault. + */ +#define __raw_readsb(p,d,l) do { *(int *)0 = 0; } while (0) +#define __raw_readsl(p,d,l) do { *(int *)0 = 0; } while (0) +#define __raw_writesb(p,d,l) do { *(int *)0 = 0; } while (0) +#define __raw_writesl(p,d,l) do { *(int *)0 = 0; } while (0) + +#endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-clps711x/irq.h linux/include/asm-arm/arch-clps711x/irq.h --- linux-2.5.2-pre8/include/asm-arm/arch-clps711x/irq.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-clps711x/irq.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,20 @@ +/* + * linux/include/asm-arm/arch-clps711x/irq.h + * + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define fixup_irq(i) (i) diff -urN linux-2.5.2-pre8/include/asm-arm/arch-clps711x/irqs.h linux/include/asm-arm/arch-clps711x/irqs.h --- linux-2.5.2-pre8/include/asm-arm/arch-clps711x/irqs.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-clps711x/irqs.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,53 @@ +/* + * linux/include/asm-arm/arch-clps711x/irqs.h + * + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * Interrupts from INTSR1 + */ +#define IRQ_CSINT 4 +#define IRQ_EINT1 5 +#define IRQ_EINT2 6 +#define IRQ_EINT3 7 +#define IRQ_TC1OI 8 +#define IRQ_TC2OI 9 +#define IRQ_RTCMI 10 +#define IRQ_TINT 11 +#define IRQ_UTXINT1 12 +#define IRQ_URXINT1 13 +#define IRQ_UMSINT 14 +#define IRQ_SSEOTI 15 + +#define INT1_IRQS (0x0000fff0) +#define INT1_ACK_IRQS (0x00004f10) + +/* + * Interrupts from INTSR2 + */ +#define IRQ_KBDINT (16+0) /* bit 0 */ +#define IRQ_SS2RX (16+1) /* bit 1 */ +#define IRQ_SS2TX (16+2) /* bit 2 */ +#define IRQ_UTXINT2 (16+12) /* bit 12 */ +#define IRQ_URXINT2 (16+13) /* bit 13 */ + +#define INT2_IRQS (0x30070000) +#define INT2_ACK_IRQS (0x00010000) + +#define NR_IRQS 30 + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-clps711x/keyboard.h linux/include/asm-arm/arch-clps711x/keyboard.h --- linux-2.5.2-pre8/include/asm-arm/arch-clps711x/keyboard.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-clps711x/keyboard.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,26 @@ +/* + * linux/include/asm-arm/arch-clps711x/keyboard.h + * + * Copyright (C) 1998-2001 Russell King + */ +#include + +#define NR_SCANCODES 128 + +#define kbd_disable_irq() do { } while (0) +#define kbd_enable_irq() do { } while (0) + +/* + * EDB7211 keyboard driver + */ +extern void edb7211_kbd_init_hw(void); +extern void clps711x_kbd_init_hw(void); + +static inline void kbd_init_hw(void) +{ + if (machine_is_edb7211()) + edb7211_kbd_init_hw(); + + if (machine_is_autcpu12()) + clps711x_kbd_init_hw(); +} diff -urN linux-2.5.2-pre8/include/asm-arm/arch-clps711x/memory.h linux/include/asm-arm/arch-clps711x/memory.h --- linux-2.5.2-pre8/include/asm-arm/arch-clps711x/memory.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-clps711x/memory.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,204 @@ +/* + * linux/include/asm-arm/arch-clps711x/mmu.h + * + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_MMU_H +#define __ASM_ARCH_MMU_H + +/* + * Task size: 3GB + */ +#define TASK_SIZE (0xc0000000UL) +#define TASK_SIZE_26 (0x04000000UL) + +/* + * This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) + +/* + * Page offset: 3GB + */ +#define PAGE_OFFSET (0xc0000000UL) +#define PHYS_OFFSET (0xc0000000UL) + +/* + * On integrator, the dram is contiguous + */ +#define __virt_to_phys__is_a_macro +#define __virt_to_phys(vpage) ((vpage) - PAGE_OFFSET + PHYS_OFFSET) +#define __phys_to_virt__is_a_macro +#define __phys_to_virt(ppage) ((ppage) + PAGE_OFFSET - PHYS_OFFSET) + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ + +#if defined(CONFIG_ARCH_CDB89712) + +#define __virt_to_bus__is_a_macro +#define __virt_to_bus(x) (x) +#define __bus_to_virt__is_a_macro +#define __bus_to_virt(x) (x) + +#elif defined (CONFIG_ARCH_AUTCPU12) + +#define __virt_to_bus__is_a_macro +#define __virt_to_bus(x) (x) +#define __bus_to_virt__is_a_macro +#define __bus_to_virt(x) (x) + +#else + +#define __virt_to_bus__is_a_macro +#define __virt_to_bus(x) ((x) - PAGE_OFFSET) +#define __bus_to_virt__is_a_macro +#define __bus_to_virt(x) ((x) + PAGE_OFFSET) + +#endif + + +/* + * Like the SA1100, the EDB7211 has a large gap between physical RAM + * banks. In 2.2, the Psion (CL-PS7110) port added custom support for + * discontiguous physical memory. In 2.4, we can use the standard + * Linux NUMA support. + * + * This is not necessary for EP7211 implementations with only one used + * memory bank. For those systems, simply undefine CONFIG_DISCONTIGMEM. + */ + +#ifdef CONFIG_ARCH_EDB7211 + +#ifdef CONFIG_DISCONTIGMEM +/* + * Because of the wide memory address space between physical RAM banks on the + * SA1100, it's much more convenient to use Linux's NUMA support to implement + * our memory map representation. Assuming all memory nodes have equal access + * characteristics, we then have generic discontigous memory support. + * + * Of course, all this isn't mandatory for SA1100 implementations with only + * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. + * + * The nodes are matched with the physical memory bank addresses which are + * incidentally the same as virtual addresses. + * + * node 0: 0xc0000000 - 0xc7ffffff + * node 1: 0xc8000000 - 0xcfffffff + * node 2: 0xd0000000 - 0xd7ffffff + * node 3: 0xd8000000 - 0xdfffffff + */ + +#define NR_NODES 4 + +/* + * Given a kernel address, find the home node of the underlying memory. + */ +#define KVADDR_TO_NID(addr) \ + (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT) + +/* + * Given a physical address, convert it to a node id. + */ +#define PHYS_TO_NID(addr) KVADDR_TO_NID(__phys_to_virt(addr)) + +/* + * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory + * and returns the mem_map of that node. + */ +#define ADDR_TO_MAPBASE(kaddr) \ + NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr))) + +/* + * Given a kaddr, LOCAL_MAR_NR finds the owning node of the memory + * and returns the index corresponding to the appropriate page in the + * node's mem_map. + */ +#define LOCAL_MAP_NR(kaddr) \ + (((unsigned long)(kaddr)-LOCAL_BASE_ADDR((kaddr))) >> PAGE_SHIFT) + +/* + * Given a kaddr, virt_to_page returns a pointer to the corresponding + * mem_map entry. + */ +#define virt_to_page(kaddr) \ + (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) + +/* + * VALID_PAGE returns a non-zero value if given page pointer is valid. + * This assumes all node's mem_maps are stored within the node they refer to. + */ +#define VALID_PAGE(page) \ +({ unsigned int node = KVADDR_TO_NID(page); \ + ( (node < NR_NODES) && \ + ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size) ); \ +}) + +/* + * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211 + * uses only one of the two banks (bank #1). However, even within + * bank #1, memory is discontiguous. + * + * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between + * them, so we use 24 for the node max shift to get 16MB node sizes. + */ +#define NODE_MAX_MEM_SHIFT 24 +#define NODE_MAX_MEM_SIZE (1< + +#define SYSPLD_REG(type,off) (*(volatile type *)(SYSPLD_BASE + off)) +#else +#define SYSPLD_REG(type,off) (off) +#endif + +#define PLD_INT SYSPLD_REG(u32, 0x000000) +#define PLD_INT_PENIRQ (1 << 5) +#define PLD_INT_UCB_IRQ (1 << 1) +#define PLD_INT_KBD_ATN (1 << 0) /* EINT1 */ + +#define PLD_PWR SYSPLD_REG(u32, 0x000004) +#define PLD_PWR_EXT (1 << 5) +#define PLD_PWR_MODE (1 << 4) /* 1 = PWM, 0 = PFM */ +#define PLD_S4_ON (1 << 3) /* LCD bias voltage enable */ +#define PLD_S3_ON (1 << 2) /* LCD backlight enable */ +#define PLD_S2_ON (1 << 1) /* LCD 3V3 supply enable */ +#define PLD_S1_ON (1 << 0) /* LCD 3V supply enable */ + +#define PLD_KBD SYSPLD_REG(u32, 0x000008) +#define PLD_KBD_WAKE (1 << 1) +#define PLD_KBD_EN (1 << 0) + +#define PLD_SPI SYSPLD_REG(u32, 0x00000c) +#define PLD_SPI_EN (1 << 0) + +#define PLD_IO SYSPLD_REG(u32, 0x000010) +#define PLD_IO_BOOTSEL (1 << 6) /* boot sel switch */ +#define PLD_IO_USER (1 << 5) /* user defined switch */ +#define PLD_IO_LED3 (1 << 4) +#define PLD_IO_LED2 (1 << 3) +#define PLD_IO_LED1 (1 << 2) +#define PLD_IO_LED0 (1 << 1) +#define PLD_IO_LEDEN (1 << 0) + +#define PLD_IRDA SYSPLD_REG(u32, 0x000014) +#define PLD_IRDA_EN (1 << 0) + +#define PLD_COM2 SYSPLD_REG(u32, 0x000018) +#define PLD_COM2_EN (1 << 0) + +#define PLD_COM1 SYSPLD_REG(u32, 0x00001c) +#define PLD_COM1_EN (1 << 0) + +#define PLD_AUD SYSPLD_REG(u32, 0x000020) +#define PLD_AUD_DIV1 (1 << 6) +#define PLD_AUD_DIV0 (1 << 5) +#define PLD_AUD_CLK_SEL1 (1 << 4) +#define PLD_AUD_CLK_SEL0 (1 << 3) +#define PLD_AUD_MIC_PWR (1 << 2) +#define PLD_AUD_MIC_GAIN (1 << 1) +#define PLD_AUD_CODEC_EN (1 << 0) + +#define PLD_CF SYSPLD_REG(u32, 0x000024) +#define PLD_CF2_SLEEP (1 << 5) +#define PLD_CF1_SLEEP (1 << 4) +#define PLD_CF2_nPDREQ (1 << 3) +#define PLD_CF1_nPDREQ (1 << 2) +#define PLD_CF2_nIRQ (1 << 1) +#define PLD_CF1_nIRQ (1 << 0) + +#define PLD_SDC SYSPLD_REG(u32, 0x000028) +#define PLD_SDC_INT_EN (1 << 2) +#define PLD_SDC_WP (1 << 1) +#define PLD_SDC_CD (1 << 0) + +#define PLD_FPGA SYSPLD_REG(u32, 0x00002c) + +#define PLD_CODEC SYSPLD_REG(u32, 0x400000) +#define PLD_CODEC_IRQ3 (1 << 4) +#define PLD_CODEC_IRQ2 (1 << 3) +#define PLD_CODEC_IRQ1 (1 << 2) +#define PLD_CODEC_EN (1 << 0) + +#define PLD_BRITE SYSPLD_REG(u32, 0x400004) +#define PLD_BRITE_UP (1 << 1) +#define PLD_BRITE_DN (1 << 0) + +#define PLD_LCDEN SYSPLD_REG(u32, 0x400008) +#define PLD_LCDEN_EN (1 << 0) + +#define PLD_ID SYSPLD_REG(u32, 0x40000c) + +#define PLD_TCH SYSPLD_REG(u32, 0x400010) +#define PLD_TCH_PENIRQ (1 << 1) +#define PLD_TCH_EN (1 << 0) + +#define PLD_GPIO SYSPLD_REG(u32, 0x400014) +#define PLD_GPIO2 (1 << 2) +#define PLD_GPIO1 (1 << 1) +#define PLD_GPIO0 (1 << 0) + +#endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-clps711x/system.h linux/include/asm-arm/arch-clps711x/system.h --- linux-2.5.2-pre8/include/asm-arm/arch-clps711x/system.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-clps711x/system.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,38 @@ +/* + * linux/include/asm-arm/arch-clps711x/system.h + * + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include + +static void arch_idle(void) +{ + clps_writel(1, HALT); + __asm__ __volatile__( + "mov r0, r0 + mov r0, r0"); +} + +static inline void arch_reset(char mode) +{ + cpu_reset(0); +} + +#endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-clps711x/time.h linux/include/asm-arm/arch-clps711x/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-clps711x/time.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-clps711x/time.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,43 @@ +/* + * linux/include/asm-arm/arch-clps711x/time.h + * + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include + +extern void clps711x_setup_timer(void); + +/* + * IRQ handler for the timer + */ +static void p720t_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + do_leds(); + do_timer(regs); + do_profile(regs); +} + +/* + * Set up timer interrupt, and return the current time in seconds. + */ +void __init time_init(void) +{ + clps711x_setup_timer(); + timer_irq.handler = p720t_timer_interrupt; + setup_arm_irq(IRQ_TC2OI, &timer_irq); +} diff -urN linux-2.5.2-pre8/include/asm-arm/arch-clps711x/timex.h linux/include/asm-arm/arch-clps711x/timex.h --- linux-2.5.2-pre8/include/asm-arm/arch-clps711x/timex.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-clps711x/timex.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,23 @@ +/* + * linux/include/asm-arm/arch-clps711x/timex.h + * + * Prospector 720T architecture timex specifications + * + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define CLOCK_TICK_RATE 512000 diff -urN linux-2.5.2-pre8/include/asm-arm/arch-clps711x/uncompress.h linux/include/asm-arm/arch-clps711x/uncompress.h --- linux-2.5.2-pre8/include/asm-arm/arch-clps711x/uncompress.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-clps711x/uncompress.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,67 @@ +/* + * linux/include/asm-arm/arch-clps711x/uncompress.h + * + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include + +#undef CLPS7111_BASE +#define CLPS7111_BASE CLPS7111_PHYS_BASE + +#define barrier() __asm__ __volatile__("": : :"memory") +#define __raw_readl(p) (*(unsigned long *)(p)) +#define __raw_writel(v,p) (*(unsigned long *)(p) = (v)) + +#ifdef CONFIG_DEBUG_CLPS711X_UART2 +#define SYSFLGx SYSFLG2 +#define UARTDRx UARTDR2 +#else +#define SYSFLGx SYSFLG1 +#define UARTDRx UARTDR1 +#endif + +/* + * This does not append a newline + */ +static void puts(const char *s) +{ + char c; + + while ((c = *s++) != '\0') { + while (clps_readl(SYSFLGx) & SYSFLG_UTXFF) + barrier(); + clps_writel(c, UARTDRx); + + if (c == '\n') { + while (clps_readl(SYSFLGx) & SYSFLG_UTXFF) + barrier(); + clps_writel('\r', UARTDRx); + } + } + while (clps_readl(SYSFLGx) & SYSFLG_UBUSY) + barrier(); +} + +/* + * nothing to do + */ +#define arch_decomp_setup() + +#define arch_decomp_wdog() diff -urN linux-2.5.2-pre8/include/asm-arm/arch-clps711x/vmalloc.h linux/include/asm-arm/arch-clps711x/vmalloc.h --- linux-2.5.2-pre8/include/asm-arm/arch-clps711x/vmalloc.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-clps711x/vmalloc.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,32 @@ +/* + * linux/include/asm-arm/arch-clps711x/vmalloc.h + * + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff -urN linux-2.5.2-pre8/include/asm-arm/arch-ebsa110/io.h linux/include/asm-arm/arch-ebsa110/io.h --- linux-2.5.2-pre8/include/asm-arm/arch-ebsa110/io.h Thu Apr 12 12:20:31 2001 +++ linux/include/asm-arm/arch-ebsa110/io.h Sat Jan 5 14:43:18 2002 @@ -15,12 +15,6 @@ #define IO_SPACE_LIMIT 0xffff -/* - * Generic virtual read/write - */ -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) - u8 __inb(int port); u16 __inw(int port); u32 __inl(int port); @@ -53,7 +47,7 @@ #define writew(v,b) __writew(v,b) #define writel(v,b) __writel(v,b) -#define __arch_ioremap(off,sz,c) ((void *)(off)) -#define __arch_iounmap(virt) do { } while (0) +#define __arch_ioremap(cookie,sz,c) ((void *)(cookie)) +#define __arch_iounmap(cookie) do { } while (0) #endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-ebsa110/time.h linux/include/asm-arm/arch-ebsa110/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-ebsa110/time.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-ebsa110/time.h Sat Jan 5 14:43:18 2002 @@ -33,7 +33,7 @@ /* * Set up timer interrupt. */ -static inline void setup_timer(void) +void __init time_init(void) { ebsa110_setup_timer(); diff -urN linux-2.5.2-pre8/include/asm-arm/arch-ebsa110/vmalloc.h linux/include/asm-arm/arch-ebsa110/vmalloc.h --- linux-2.5.2-pre8/include/asm-arm/arch-ebsa110/vmalloc.h Mon Sep 18 15:15:23 2000 +++ linux/include/asm-arm/arch-ebsa110/vmalloc.h Sat Jan 5 14:43:18 2002 @@ -19,4 +19,4 @@ #define VMALLOC_OFFSET (8*1024*1024) #define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_VMADDR(x) ((unsigned long)(x)) -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) +#define VMALLOC_END (PAGE_OFFSET + 0x1f000000) diff -urN linux-2.5.2-pre8/include/asm-arm/arch-ebsa285/io.h linux/include/asm-arm/arch-ebsa285/io.h --- linux-2.5.2-pre8/include/asm-arm/arch-ebsa285/io.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-ebsa285/io.h Sat Jan 5 14:43:18 2002 @@ -42,13 +42,4 @@ #define __mem_isa(a) ___mem_isa((unsigned long)(a)) #endif -/* - * Generic virtual read/write - */ -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) - -#define iomem_valid_addr(iomem,sz) (1) -#define iomem_to_phys(iomem) (iomem) - #endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-ebsa285/time.h linux/include/asm-arm/arch-ebsa285/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-ebsa285/time.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-ebsa285/time.h Sat Jan 5 14:43:18 2002 @@ -199,7 +199,7 @@ /* * Set up timer interrupt. */ -static inline void setup_timer(void) +void __init time_init(void) { int irq; diff -urN linux-2.5.2-pre8/include/asm-arm/arch-ebsa285/vmalloc.h linux/include/asm-arm/arch-ebsa285/vmalloc.h --- linux-2.5.2-pre8/include/asm-arm/arch-ebsa285/vmalloc.h Mon Sep 18 15:15:23 2000 +++ linux/include/asm-arm/arch-ebsa285/vmalloc.h Sat Jan 5 14:43:18 2002 @@ -6,6 +6,8 @@ * published by the Free Software Foundation. */ +#include + /* * Just any arbitrary offset to the start of the vmalloc VM area: the * current 8MB value just means that there will be a 8MB "hole" after the @@ -17,4 +19,9 @@ #define VMALLOC_OFFSET (8*1024*1024) #define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_VMADDR(x) ((unsigned long)(x)) + +#ifdef CONFIG_ARCH_FOOTBRIDGE +#define VMALLOC_END (PAGE_OFFSET + 0x30000000) +#else #define VMALLOC_END (PAGE_OFFSET + 0x20000000) +#endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-epxa10db/ether00.h linux/include/asm-arm/arch-epxa10db/ether00.h --- linux-2.5.2-pre8/include/asm-arm/arch-epxa10db/ether00.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-epxa10db/ether00.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,482 @@ +#ifndef __ETHER00_H +#define __ETHER00_H + + + +/* + * Register definitions for the Ethernet MAC + */ + +/* + * Copyright (c) Altera Corporation 2000. + * All rights reserved. + */ + +/* +* Structures for the DMA controller +*/ +typedef struct fda_desc + { + struct fda_desc * FDNext; + long FDSystem; + long FDStat; + short FDLength; + short FDCtl; + }FDA_DESC; + +typedef struct buf_desc + { + char * BuffData; + short BuffLength; + char BDStat; + char BDCtl; + }BUF_DESC; + +/* +* Control masks for the DMA controller +*/ +#define FDCTL_BDCOUNT_MSK (0x1F) +#define FDCTL_BDCOUNT_OFST (0) +#define FDCTL_FRMOPT_MSK (0x7C00) +#define FDCTL_FRMOPT_OFST (10) +#define FDCTL_COWNSFD_MSK (0x8000) +#define FDCTL_COWNSFD_OFST (15) + +#define BDCTL_RXBDSEQN_MSK (0x7F) +#define BDCTL_RXBDSEQN_OFST (0) +#define BDCTL_COWNSBD_MSK (0x80) +#define BDCTL_COWNSBD_OFST (7) + +#define FDNEXT_EOL_MSK (0x1) +#define FDNEXT_EOL_OFST (0) +#define FDNEXT_EOL_POINTER_MSK (0xFFFFFFF0) +#define FDNEXT_EOL_POINTER_OFST (4) + +#define ETHER_ARC_SIZE (21) + +/* +* Regsiter definitions and masks +*/ +#define ETHER_DMA_CTL(base) (ETHER00_TYPE (base + 0x100)) +#define ETHER_DMA_CTL_DMBURST_OFST (2) +#define ETHER_DMA_CTL_DMBURST_MSK (0x1FC) +#define ETHER_DMA_CTL_POWRMGMNT_OFST (11) +#define ETHER_DMA_CTL_POWRMGMNT_MSK (0x1000) +#define ETHER_DMA_CTL_TXBIGE_OFST (14) +#define ETHER_DMA_CTL_TXBIGE_MSK (0x4000) +#define ETHER_DMA_CTL_RXBIGE_OFST (15) +#define ETHER_DMA_CTL_RXBIGE_MSK (0x8000) +#define ETHER_DMA_CTL_TXWAKEUP_OFST (16) +#define ETHER_DMA_CTL_TXWAKEUP_MSK (0x10000) +#define ETHER_DMA_CTL_SWINTREQ_OFST (17) +#define ETHER_DMA_CTL_SWINTREQ_MSK (0x20000) +#define ETHER_DMA_CTL_INTMASK_OFST (18) +#define ETHER_DMA_CTL_INTMASK_MSK (0x40000) +#define ETHER_DMA_CTL_M66ENSTAT_OFST (19) +#define ETHER_DMA_CTL_M66ENSTAT_MSK (0x80000) +#define ETHER_DMA_CTL_RMTXINIT_OFST (20) +#define ETHER_DMA_CTL_RMTXINIT_MSK (0x100000) +#define ETHER_DMA_CTL_RMRXINIT_OFST (21) +#define ETHER_DMA_CTL_RMRXINIT_MSK (0x200000) +#define ETHER_DMA_CTL_RXALIGN_OFST (22) +#define ETHER_DMA_CTL_RXALIGN_MSK (0xC00000) +#define ETHER_DMA_CTL_RMSWRQ_OFST (24) +#define ETHER_DMA_CTL_RMSWRQ_MSK (0x1000000) +#define ETHER_DMA_CTL_RMEMBANK_OFST (25) +#define ETHER_DMA_CTL_RMEMBANK_MSK (0x2000000) + +#define ETHER_TXFRMPTR(base) (ETHER00_TYPE (base + 0x104)) + +#define ETHER_TXTHRSH(base) (ETHER00_TYPE (base + 0x308)) + +#define ETHER_TXPOLLCTR(base) (ETHER00_TYPE (base + 0x30c)) + +#define ETHER_BLFRMPTR(base) (ETHER00_TYPE (base + 0x110)) +#define ETHER_BLFFRMPTR_EOL_OFST (0) +#define ETHER_BLFFRMPTR_EOL_MSK (0x1) +#define ETHER_BLFFRMPTR_ADDRESS_OFST (4) +#define ETHER_BLFFRMPTR_ADDRESS_MSK (0xFFFFFFF0) + +#define ETHER_RXFRAGSIZE(base) (ETHER00_TYPE (base + 0x114)) +#define ETHER_RXFRAGSIZE_MINFRAG_OFST (2) +#define ETHER_RXFRAGSIZE_MINFRAG_MSK (0xFFC) +#define ETHER_RXFRAGSIZE_ENPACK_OFST (15) +#define ETHER_RXFRAGSIZE_ENPACK_MSK (0x8000) + +#define ETHER_INT_EN(base) (ETHER00_TYPE (base + 0x118)) +#define ETHER_INT_EN_FDAEXEN_OFST (0) +#define ETHER_INT_EN_FDAEXEN_MSK (0x1) +#define ETHER_INT_EN_BLEXEN_OFST (1) +#define ETHER_INT_EN_BLEXN_MSK (0x2) +#define ETHER_INT_EN_STARGABTEN_OFST (2) +#define ETHER_INT_EN_STARGABTEN_MSK (0x4) +#define ETHER_INT_EN_RTARGABTEN_OFST (3) +#define ETHER_INT_EN_RTARGABTEN_MSK (0x8) +#define ETHER_INT_EN_RMASABTEN_OFST (4) +#define ETHER_INT_EN_RMASABTEN_MSK (0x10) +#define ETHER_INT_EN_SSYSERREN_OFST (5) +#define ETHER_INT_EN_SSYSERREN_MSK (0x20) +#define ETHER_INT_EN_DPARERREN_OFST (6) +#define ETHER_INT_EN_DPARERREN_MSK (0x40) +#define ETHER_INT_EN_EARNOTEN_OFST (7) +#define ETHER_INT_EN_EARNOTEN_MSK (0x80) +#define ETHER_INT_EN_DPARDEN_OFST (8) +#define ETHER_INT_EN_DPARDEN_MSK (0x100) +#define ETHER_INT_EN_DMPARERREN_OFST (9) +#define ETHER_INT_EN_DMPARERREN_MSK (0x200) +#define ETHER_INT_EN_TXCTLCMPEN_OFST (10) +#define ETHER_INT_EN_TXCTLCMPEN_MSK (0x400) +#define ETHER_INT_EN_NRABTEN_OFST (11) +#define ETHER_INT_EN_NRABTEN_MSK (0x800) + +#define ETHER_FDA_BAS(base) (ETHER00_TYPE (base + 0x11C)) +#define ETHER_FDA_BAS_ADDRESS_OFST (4) +#define ETHER_FDA_BAS_ADDRESS_MSK (0xFFFFFFF0) + +#define ETHER_FDA_LIM(base) (ETHER00_TYPE (base + 0x120)) +#define ETHER_FDA_LIM_COUNT_OFST (4) +#define ETHER_FDA_LIM_COUNT_MSK (0xFFF0) + +#define ETHER_INT_SRC(base) (ETHER00_TYPE (base + 0x124)) +#define ETHER_INT_SRC_INTMACTX_OFST (0) +#define ETHER_INT_SRC_INTMACTX_MSK (0x1) +#define ETHER_INT_SRC_INTMACRX_OFST (1) +#define ETHER_INT_SRC_INTMACRX_MSK (0x2) +#define ETHER_INT_SRC_INTSBUS_OFST (2) +#define ETHER_INT_SRC_INTSBUS_MSK (0x4) +#define ETHER_INT_SRC_INTFDAEX_OFST (3) +#define ETHER_INT_SRC_INTFDAEX_MSK (0x8) +#define ETHER_INT_SRC_INTBLEX_OFST (4) +#define ETHER_INT_SRC_INTBLEX_MSK (0x10) +#define ETHER_INT_SRC_SWINT_OFST (5) +#define ETHER_INT_SRC_SWINT_MSK (0x20) +#define ETHER_INT_SRC_INTEARNOT_OFST (6) +#define ETHER_INT_SRC_INTEARNOT_MSK (0x40) +#define ETHER_INT_SRC_DMPARERR_OFST (7) +#define ETHER_INT_SRC_DMPARERR_MSK (0x80) +#define ETHER_INT_SRC_INTEXBD_OFST (8) +#define ETHER_INT_SRC_INTEXBD_MSK (0x100) +#define ETHER_INT_SRC_INTTXCTLCMP_OFST (9) +#define ETHER_INT_SRC_INTTXCTLCMP_MSK (0x200) +#define ETHER_INT_SRC_INTNRABT_OFST (10) +#define ETHER_INT_SRC_INTNRABT_MSK (0x400) +#define ETHER_INT_SRC_FDAEX_OFST (11) +#define ETHER_INT_SRC_FDAEX_MSK (0x800) +#define ETHER_INT_SRC_BLEX_OFST (12) +#define ETHER_INT_SRC_BLEX_MSK (0x1000) +#define ETHER_INT_SRC_DMPARERRSTAT_OFST (13) +#define ETHER_INT_SRC_DMPARERRSTAT_MSK (0x2000) +#define ETHER_INT_SRC_NRABT_OFST (14) +#define ETHER_INT_SRC_NRABT_MSK (0x4000) +#define ETHER_INT_SRC_INTLINK_OFST (15) +#define ETHER_INT_SRC_INTLINK_MSK (0x8000) +#define ETHER_INT_SRC_INTEXDEFER_OFST (16) +#define ETHER_INT_SRC_INTEXDEFER_MSK (0x10000) +#define ETHER_INT_SRC_INTRMON_OFST (17) +#define ETHER_INT_SRC_INTRMON_MSK (0x20000) +#define ETHER_INT_SRC_IRQ_MSK (0x83FF) + +#define ETHER_PAUSECNT(base) (ETHER00_TYPE (base + 0x40)) +#define ETHER_PAUSECNT_COUNT_OFST (0) +#define ETHER_PAUSECNT_COUNT_MSK (0xFFFF) + +#define ETHER_REMPAUCNT(base) (ETHER00_TYPE (base + 0x44)) +#define ETHER_REMPAUCNT_COUNT_OFST (0) +#define ETHER_REMPAUCNT_COUNT_MSK (0xFFFF) + +#define ETHER_TXCONFRMSTAT(base) (ETHER00_TYPE (base + 0x348)) +#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_OFST (0) +#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_MSK (0x3FFFFF) + +#define ETHER_MAC_CTL(base) (ETHER00_TYPE (base + 0)) +#define ETHER_MAC_CTL_HALTREQ_OFST (0) +#define ETHER_MAC_CTL_HALTREQ_MSK (0x1) +#define ETHER_MAC_CTL_HALTIMM_OFST (1) +#define ETHER_MAC_CTL_HALTIMM_MSK (0x2) +#define ETHER_MAC_CTL_RESET_OFST (2) +#define ETHER_MAC_CTL_RESET_MSK (0x4) +#define ETHER_MAC_CTL_FULLDUP_OFST (3) +#define ETHER_MAC_CTL_FULLDUP_MSK (0x8) +#define ETHER_MAC_CTL_MACLOOP_OFST (4) +#define ETHER_MAC_CTL_MACLOOP_MSK (0x10) +#define ETHER_MAC_CTL_CONN_OFST (5) +#define ETHER_MAC_CTL_CONN_MSK (0x60) +#define ETHER_MAC_CTL_LOOP10_OFST (7) +#define ETHER_MAC_CTL_LOOP10_MSK (0x80) +#define ETHER_MAC_CTL_LNKCHG_OFST (8) +#define ETHER_MAC_CTL_LNKCHG_MSK (0x100) +#define ETHER_MAC_CTL_MISSROLL_OFST (10) +#define ETHER_MAC_CTL_MISSROLL_MSK (0x400) +#define ETHER_MAC_CTL_ENMISSROLL_OFST (13) +#define ETHER_MAC_CTL_ENMISSROLL_MSK (0x2000) +#define ETHER_MAC_CTL_LINK10_OFST (15) +#define ETHER_MAC_CTL_LINK10_MSK (0x8000) + +#define ETHER_ARC_CTL(base) (ETHER00_TYPE (base + 0x4)) +#define ETHER_ARC_CTL_STATIONACC_OFST (0) +#define ETHER_ARC_CTL_STATIONACC_MSK (0x1) +#define ETHER_ARC_CTL_GROUPACC_OFST (1) +#define ETHER_ARC_CTL_GROUPACC_MSK (0x2) +#define ETHER_ARC_CTL_BROADACC_OFST (2) +#define ETHER_ARC_CTL_BROADACC_MSK (0x4) +#define ETHER_ARC_CTL_NEGARC_OFST (3) +#define ETHER_ARC_CTL_NEGARC_MSK (0x8) +#define ETHER_ARC_CTL_COMPEN_OFST (4) +#define ETHER_ARC_CTL_COMPEN_MSK (0x10) + +#define ETHER_TX_CTL(base) (ETHER00_TYPE (base + 0x8)) +#define ETHER_TX_CTL_TXEN_OFST (0) +#define ETHER_TX_CTL_TXEN_MSK (0x1) +#define ETHER_TX_CTL_TXHALT_OFST (1) +#define ETHER_TX_CTL_TXHALT_MSK (0x2) +#define ETHER_TX_CTL_NOPAD_OFST (2) +#define ETHER_TX_CTL_NOPAD_MSK (0x4) +#define ETHER_TX_CTL_NOCRC_OFST (3) +#define ETHER_TX_CTL_NOCRC_MSK (0x8) +#define ETHER_TX_CTL_FBACK_OFST (4) +#define ETHER_TX_CTL_FBACK_MSK (0x10) +#define ETHER_TX_CTL_NOEXDEF_OFST (5) +#define ETHER_TX_CTL_NOEXDEF_MSK (0x20) +#define ETHER_TX_CTL_SDPAUSE_OFST (6) +#define ETHER_TX_CTL_SDPAUSE_MSK (0x40) +#define ETHER_TX_CTL_MII10_OFST (7) +#define ETHER_TX_CTL_MII10_MSK (0x80) +#define ETHER_TX_CTL_ENUNDER_OFST (8) +#define ETHER_TX_CTL_ENUNDER_MSK (0x100) +#define ETHER_TX_CTL_ENEXDEFER_OFST (9) +#define ETHER_TX_CTL_ENEXDEFER_MSK (0x200) +#define ETHER_TX_CTL_ENLCARR_OFST (10) +#define ETHER_TX_CTL_ENLCARR_MSK (0x400) +#define ETHER_TX_CTL_ENEXCOLL_OFST (11) +#define ETHER_TX_CTL_ENEXCOLL_MSK (0x800) +#define ETHER_TX_CTL_ENLATECOLL_OFST (12) +#define ETHER_TX_CTL_ENLATECOLL_MSK (0x1000) +#define ETHER_TX_CTL_ENTXPAR_OFST (13) +#define ETHER_TX_CTL_ENTXPAR_MSK (0x2000) +#define ETHER_TX_CTL_ENCOMP_OFST (14) +#define ETHER_TX_CTL_ENCOMP_MSK (0x4000) + +#define ETHER_TX_STAT(base) (ETHER00_TYPE (base + 0xc)) +#define ETHER_TX_STAT_TXCOLL_OFST (0) +#define ETHER_TX_STAT_TXCOLL_MSK (0xF) +#define ETHER_TX_STAT_EXCOLL_OFST (4) +#define ETHER_TX_STAT_EXCOLL_MSK (0x10) +#define ETHER_TX_STAT_TXDEFER_OFST (5) +#define ETHER_TX_STAT_TXDEFER_MSK (0x20) +#define ETHER_TX_STAT_PAUSED_OFST (6) +#define ETHER_TX_STAT_PAUSED_MSK (0x40) +#define ETHER_TX_STAT_INTTX_OFST (7) +#define ETHER_TX_STAT_INTTX_MSK (0x80) +#define ETHER_TX_STAT_UNDER_OFST (8) +#define ETHER_TX_STAT_UNDER_MSK (0x100) +#define ETHER_TX_STAT_EXDEFER_OFST (9) +#define ETHER_TX_STAT_EXDEFER_MSK (0x200) +#define ETHER_TX_STAT_LCARR_OFST (10) +#define ETHER_TX_STAT_LCARR_MSK (0x400) +#define ETHER_TX_STAT_TX10STAT_OFST (11) +#define ETHER_TX_STAT_TX10STAT_MSK (0x800) +#define ETHER_TX_STAT_LATECOLL_OFST (12) +#define ETHER_TX_STAT_LATECOLL_MSK (0x1000) +#define ETHER_TX_STAT_TXPAR_OFST (13) +#define ETHER_TX_STAT_TXPAR_MSK (0x2000) +#define ETHER_TX_STAT_COMP_OFST (14) +#define ETHER_TX_STAT_COMP_MSK (0x4000) +#define ETHER_TX_STAT_TXHALTED_OFST (15) +#define ETHER_TX_STAT_TXHALTED_MSK (0x8000) +#define ETHER_TX_STAT_SQERR_OFST (16) +#define ETHER_TX_STAT_SQERR_MSK (0x10000) +#define ETHER_TX_STAT_TXMCAST_OFST (17) +#define ETHER_TX_STAT_TXMCAST_MSK (0x20000) +#define ETHER_TX_STAT_TXBCAST_OFST (18) +#define ETHER_TX_STAT_TXBCAST_MSK (0x40000) +#define ETHER_TX_STAT_VLAN_OFST (19) +#define ETHER_TX_STAT_VLAN_MSK (0x80000) +#define ETHER_TX_STAT_MACC_OFST (20) +#define ETHER_TX_STAT_MACC_MSK (0x100000) +#define ETHER_TX_STAT_TXPAUSE_OFST (21) +#define ETHER_TX_STAT_TXPAUSE_MSK (0x200000) + +#define ETHER_RX_CTL(base) (ETHER00_TYPE (base + 0x10)) +#define ETHER_RX_CTL_RXEN_OFST (0) +#define ETHER_RX_CTL_RXEN_MSK (0x1) +#define ETHER_RX_CTL_RXHALT_OFST (1) +#define ETHER_RX_CTL_RXHALT_MSK (0x2) +#define ETHER_RX_CTL_LONGEN_OFST (2) +#define ETHER_RX_CTL_LONGEN_MSK (0x4) +#define ETHER_RX_CTL_SHORTEN_OFST (3) +#define ETHER_RX_CTL_SHORTEN_MSK (0x8) +#define ETHER_RX_CTL_STRIPCRC_OFST (4) +#define ETHER_RX_CTL_STRIPCRC_MSK (0x10) +#define ETHER_RX_CTL_PASSCTL_OFST (5) +#define ETHER_RX_CTL_PASSCTL_MSK (0x20) +#define ETHER_RX_CTL_IGNORECRC_OFST (6) +#define ETHER_RX_CTL_IGNORECRC_MSK (0x40) +#define ETHER_RX_CTL_ENALIGN_OFST (8) +#define ETHER_RX_CTL_ENALIGN_MSK (0x100) +#define ETHER_RX_CTL_ENCRCERR_OFST (9) +#define ETHER_RX_CTL_ENCRCERR_MSK (0x200) +#define ETHER_RX_CTL_ENOVER_OFST (10) +#define ETHER_RX_CTL_ENOVER_MSK (0x400) +#define ETHER_RX_CTL_ENLONGERR_OFST (11) +#define ETHER_RX_CTL_ENLONGERR_MSK (0x800) +#define ETHER_RX_CTL_ENRXPAR_OFST (13) +#define ETHER_RX_CTL_ENRXPAR_MSK (0x2000) +#define ETHER_RX_CTL_ENGOOD_OFST (14) +#define ETHER_RX_CTL_ENGOOD_MSK (0x4000) + +#define ETHER_RX_STAT(base) (ETHER00_TYPE (base + 0x14)) +#define ETHER_RX_STAT_LENERR_OFST (4) +#define ETHER_RX_STAT_LENERR_MSK (0x10) +#define ETHER_RX_STAT_CTLRECD_OFST (5) +#define ETHER_RX_STAT_CTLRECD_MSK (0x20) +#define ETHER_RX_STAT_INTRX_OFST (6) +#define ETHER_RX_STAT_INTRX_MSK (0x40) +#define ETHER_RX_STAT_RX10STAT_OFST (7) +#define ETHER_RX_STAT_RX10STAT_MSK (0x80) +#define ETHER_RX_STAT_ALIGNERR_OFST (8) +#define ETHER_RX_STAT_ALIGNERR_MSK (0x100) +#define ETHER_RX_STAT_CRCERR_OFST (9) +#define ETHER_RX_STAT_CRCERR_MSK (0x200) +#define ETHER_RX_STAT_OVERFLOW_OFST (10) +#define ETHER_RX_STAT_OVERFLOW_MSK (0x400) +#define ETHER_RX_STAT_LONGERR_OFST (11) +#define ETHER_RX_STAT_LONGERR_MSK (0x800) +#define ETHER_RX_STAT_RXPAR_OFST (13) +#define ETHER_RX_STAT_RXPAR_MSK (0x2000) +#define ETHER_RX_STAT_GOOD_OFST (14) +#define ETHER_RX_STAT_GOOD_MSK (0x4000) +#define ETHER_RX_STAT_RXHALTED_OFST (15) +#define ETHER_RX_STAT_RXHALTED_MSK (0x8000) +#define ETHER_RX_STAT_RXMCAST_OFST (17) +#define ETHER_RX_STAT_RXMCAST_MSK (0x10000) +#define ETHER_RX_STAT_RXBCAST_OFST (18) +#define ETHER_RX_STAT_RXBCAST_MSK (0x20000) +#define ETHER_RX_STAT_RXVLAN_OFST (19) +#define ETHER_RX_STAT_RXVLAN_MSK (0x40000) +#define ETHER_RX_STAT_RXPAUSE_OFST (20) +#define ETHER_RX_STAT_RXPAUSE_MSK (0x80000) +#define ETHER_RX_STAT_ARCSTATUS_OFST (21) +#define ETHER_RX_STAT_ARCSTATUS_MSK (0xF00000) +#define ETHER_RX_STAT_ARCENT_OFST (25) +#define ETHER_RX_STAT_ARCENT_MSK (0x1F000000) + +#define ETHER_MD_DATA(base) (ETHER00_TYPE (base + 0x18)) + +#define ETHER_MD_CA(base) (ETHER00_TYPE (base + 0x1c)) +#define ETHER_MD_CA_ADDR_OFST (0) +#define ETHER_MD_CA_ADDR_MSK (0x1F) +#define ETHER_MD_CA_PHY_OFST (5) +#define ETHER_MD_CA_PHY_MSK (0x3E0) +#define ETHER_MD_CA_WR_OFST (10) +#define ETHER_MD_CA_WR_MSK (0x400) +#define ETHER_MD_CA_BUSY_OFST (11) +#define ETHER_MD_CA_BUSY_MSK (0x800) +#define ETHER_MD_CA_PRESUPP_OFST (12) +#define ETHER_MD_CA_PRESUPP_MSK (0x1000) + +#define ETHER_ARC_ADR(base) (ETHER00_TYPE (base + 0x160)) +#define ETHER_ARC_ADR_ARC_LOC_OFST (2) +#define ETHER_ARC_ADR_ARC_LOC_MSK (0xFFC) + +#define ETHER_ARC_DATA(base) (ETHER00_TYPE (base + 0x364)) + +#define ETHER_ARC_ENA(base) (ETHER00_TYPE (base + 0x28)) +#define ETHER_ARC_ENA_MSK (0x1FFFFF) + +#define ETHER_PROM_CTL(base) (ETHER00_TYPE (base + 0x2c)) +#define ETHER_PROM_CTL_PROM_ADDR_OFST (0) +#define ETHER_PROM_CTL_PROM_ADDR_MSK (0x3F) +#define ETHER_PROM_CTL_OPCODE_OFST (13) +#define ETHER_PROM_CTL_OPCODE_MSK (0x6000) +#define ETHER_PROM_CTL_OPCODE_READ_MSK (0x4000) +#define ETHER_PROM_CTL_OPCODE_WRITE_MSK (0x2000) +#define ETHER_PROM_CTL_OPCODE_ERASE_MSK (0x6000) +#define ETHER_PROM_CTL_ENABLE_MSK (0x0030) +#define ETHER_PROM_CTL_DISABLE_MSK (0x0000) +#define ETHER_PROM_CTL_BUSY_OFST (15) +#define ETHER_PROM_CTL_BUSY_MSK (0x8000) + +#define ETHER_PROM_DATA(base) (ETHER00_TYPE (base + 0x30)) + +#define ETHER_MISS_CNT(base) (ETHER00_TYPE (base + 0x3c)) +#define ETHER_MISS_CNT_COUNT_OFST (0) +#define ETHER_MISS_CNT_COUNT_MSK (0xFFFF) + +#define ETHER_CNTDATA(base) (ETHER00_TYPE (base + 0x80)) + +#define ETHER_CNTACC(base) (ETHER00_TYPE (base + 0x84)) +#define ETHER_CNTACC_ADDR_OFST (0) +#define ETHER_CNTACC_ADDR_MSK (0xFF) +#define ETHER_CNTACC_WRRDN_OFST (8) +#define ETHER_CNTACC_WRRDN_MSK (0x100) +#define ETHER_CNTACC_CLEAR_OFST (9) +#define ETHER_CNTACC_CLEAR_MSK (0x200) + +#define ETHER_TXRMINTEN(base) (ETHER00_TYPE (base + 0x88)) +#define ETHER_TXRMINTEN_MSK (0x3FFFFFFF) + +#define ETHER_RXRMINTEN(base) (ETHER00_TYPE (base + 0x8C)) +#define ETHER_RXRMINTEN_MSK (0xFFFFFF) + +/* +* RMON Registers +*/ +#define RMON_COLLISION0 0x0 +#define RMON_COLLISION1 0x1 +#define RMON_COLLISION2 0x2 +#define RMON_COLLISION3 0x3 +#define RMON_COLLISION4 0x4 +#define RMON_COLLISION5 0x5 +#define RMON_COLLISION6 0x6 +#define RMON_COLLISION7 0x7 +#define RMON_COLLISION8 0x8 +#define RMON_COLLISION9 0x9 +#define RMON_COLLISION10 0xa +#define RMON_COLLISION11 0xb +#define RMON_COLLISION12 0xc +#define RMON_COLLISION13 0xd +#define RMON_COLLISION14 0xe +#define RMON_COLLISION15 0xf +#define RMON_COLLISION16 0x10 +#define RMON_FRAMES_WITH_DEFERRED_XMISSIONS 0x11 +#define RMON_LATE_COLLISIONS 0x12 +#define RMON_FRAMES_LOST_DUE_TO_MAC_XMIT 0x13 +#define RMON_CARRIER_SENSE_ERRORS 0x14 +#define RMON_FRAMES_WITH_EXCESSIVE_DEFERAL 0x15 +#define RMON_UNICAST_FRAMES_TRANSMITTED_OK 0x16 +#define RMON_MULTICAST_FRAMES_XMITTED_OK 0x17 +#define RMON_BROADCAST_FRAMES_XMITTED_OK 0x18 +#define RMON_SQE_TEST_ERRORS 0x19 +#define RMON_PAUSE_MACCTRL_FRAMES_XMITTED 0x1A +#define RMON_MACCTRL_FRAMES_XMITTED 0x1B +#define RMON_VLAN_FRAMES_XMITTED 0x1C +#define RMON_OCTETS_XMITTED_OK 0x1D +#define RMON_OCTETS_XMITTED_OK_HI 0x1E + +#define RMON_RX_PACKET_SIZES0 0x40 +#define RMON_RX_PACKET_SIZES1 0x41 +#define RMON_RX_PACKET_SIZES2 0x42 +#define RMON_RX_PACKET_SIZES3 0x43 +#define RMON_RX_PACKET_SIZES4 0x44 +#define RMON_RX_PACKET_SIZES5 0x45 +#define RMON_RX_PACKET_SIZES6 0x46 +#define RMON_RX_PACKET_SIZES7 0x47 +#define RMON_FRAME_CHECK_SEQUENCE_ERRORS 0x48 +#define RMON_ALIGNMENT_ERRORS 0x49 +#define RMON_FRAGMENTS 0x4A +#define RMON_JABBERS 0x4B +#define RMON_FRAMES_LOST_TO_INTMACRCVERR 0x4C +#define RMON_UNICAST_FRAMES_RCVD_OK 0x4D +#define RMON_MULTICAST_FRAMES_RCVD_OK 0x4E +#define RMON_BROADCAST_FRAMES_RCVD_OK 0x4F +#define RMON_IN_RANGE_LENGTH_ERRORS 0x50 +#define RMON_OUT_OF_RANGE_LENGTH_ERRORS 0x51 +#define RMON_VLAN_FRAMES_RCVD 0x52 +#define RMON_PAUSE_MAC_CTRL_FRAMES_RCVD 0x53 +#define RMON_MAC_CTRL_FRAMES_RCVD 0x54 +#define RMON_OCTETS_RCVD_OK 0x55 +#define RMON_OCTETS_RCVD_OK_HI 0x56 +#define RMON_OCTETS_RCVD_OTHER 0x57 +#define RMON_OCTETS_RCVD_OTHER_HI 0x58 + +#endif /* __ETHER00_H */ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-epxa10db/io.h linux/include/asm-arm/arch-epxa10db/io.h --- linux-2.5.2-pre8/include/asm-arm/arch-epxa10db/io.h Thu Oct 25 13:53:53 2001 +++ linux/include/asm-arm/arch-epxa10db/io.h Sat Jan 5 14:43:18 2002 @@ -26,8 +26,6 @@ /* * Generic virtual read/write */ -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) /*#define outsw __arch_writesw #define outsl __arch_writesl #define outsb __arch_writesb @@ -36,20 +34,6 @@ #define insl __arch_readsl*/ #define __io(a) (a) -#if 0 -#define __mem_pci(a) ((unsigned long)(a)) -#define __mem_isa(a) (PCI_MEMORY_VADDR + (unsigned long)(a)) -/* - * Validate the pci memory address for ioremap. - */ -#define iomem_valid_addr(iomem,size) \ - ((iomem) > 0 && (iomem) + (size) <= 0x20000000) - -/* - * Convert PCI memory space to a CPU physical address - */ -#define iomem_to_phys(iomem) ((iomem) + PHYS_PCI_MEM_BASE) - -#endif +#define __mem_pci(a) (a) #endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-epxa10db/tdkphy.h linux/include/asm-arm/arch-epxa10db/tdkphy.h --- linux-2.5.2-pre8/include/asm-arm/arch-epxa10db/tdkphy.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-epxa10db/tdkphy.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,209 @@ +/* + * linux/drivers/tdkphy.h + * + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __TDKPHY_H +#define __TDKPHY_H + +/* + * Register definitions for the TDK 78Q2120 PHY + * which is on the Camelot board + */ + +/* + * Copyright (c) Altera Corporation 2000. + * All rights reserved. + */ +#define PHY_CONTROL (0) +#define PHY_CONTROL_COLT_MSK (0x80) +#define PHY_CONTROL_COLT_OFST (7) +#define PHY_CONTROL_DUPLEX_MSK (0x100) +#define PHY_CONTROL_DUPLEX_OFST (8) +#define PHY_CONTROL_RANEG_MSK (0x200) +#define PHY_CONTROL_RANEG_OFST (9) +#define PHY_CONTROL_ISO_MSK (0x400) +#define PHY_CONTROL_ISO_OFST (10) +#define PHY_CONTROL_PWRDN_MSK (0x800) +#define PHY_CONTROL_PWRDN_OFST (11) +#define PHY_CONTROL_ANEGEN_MSK (0x1000) +#define PHY_CONTROL_ANEGEN_OFST (12) +#define PHY_CONTROL_SPEEDSL_MSK (0x2000) +#define PHY_CONTROL_SPEEDSL_OFST (13) +#define PHY_CONTROL_LOOPBK_MSK (0x4000) +#define PHY_CONTROL_LOOPBK_OFST (14) +#define PHY_CONTROL_RESET_MSK (0x8000) +#define PHY_CONTROL_RESET_OFST (15) + +#define PHY_STATUS (1) +#define PHY_STATUS_ETXD_MSK (0x1) +#define PHY_STATUS_EXTD_OFST (0) +#define PHY_STATUS_JAB_MSK (0x2) +#define PHY_STATUS_JAB_OFST (1) +#define PHY_STATUS_LINK_MSK (0x4) +#define PHY_STATUS_LINK_OFST (2) +#define PHY_STATUS_ANEGA_MSK (0x8) +#define PHY_STATUS_ANEGA_OFST (3) +#define PHY_STATUS_RFAULT_MSK (0x10) +#define PHY_STATUS_RFAULT_OFST (4) +#define PHY_STATUS_ANEGC_MSK (0x20) +#define PHY_STATUS_ANEGC_OFST (5) +#define PHY_STATUS_10T_H_MSK (0x800) +#define PHY_STATUS_10T_H_OFST (11) +#define PHY_STATUS_10T_F_MSK (0x1000) +#define PHY_STATUS_10T_F_OFST (12) +#define PHY_STATUS_100_X_H_MSK (0x2000) +#define PHY_STATUS_100_X_H_OFST (13) +#define PHY_STATUS_100_X_F_MSK (0x4000) +#define PHY_STATUS_100_X_F_OFST (14) +#define PHY_STATUS_100T4_MSK (0x8000) +#define PHY_STATUS_100T4_OFST (15) + +#define PHY_ID1 (2) +#define PHY_ID1_OUI_MSK (0xFFFF) +#define PHY_ID1_OUI_OFST (0) + +#define PHY_ID2 (3) +#define PHY_ID2_RN_MSK (0xF) +#define PHY_ID2_RN_OFST (0) +#define PHY_ID2_MN_MSK (0x3F0) +#define PHY_ID2_MN_OFST (4) +#define PHY_ID2_OUI_MSK (0xFC00) +#define PHY_ID2_OUI_OFST (10) + +#define PHY_AUTO_NEG_ADVERTISEMENT (4) +#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_MSK (0x1F) +#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_OFST (0) +#define PHY_AUTO_NEG_ADVERTISEMENT_A0_MSK (0x20) +#define PHY_AUTO_NEG_ADVERTISEMENT_A0_OFST (5) +#define PHY_AUTO_NEG_ADVERTISEMENT_A1_MSK (0x40) +#define PHY_AUTO_NEG_ADVERTISEMENT_A1_OFST (6) +#define PHY_AUTO_NEG_ADVERTISEMENT_A2_MSK (0x80) +#define PHY_AUTO_NEG_ADVERTISEMENT_A2_OFST (7) +#define PHY_AUTO_NEG_ADVERTISEMENT_A3_MSK (0x100) +#define PHY_AUTO_NEG_ADVERTISEMENT_A3_OFST (8) +#define PHY_AUTO_NEG_ADVERTISEMENT_A4_MSK (0x200) +#define PHY_AUTO_NEG_ADVERTISEMENT_A4_OFST (9) +#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_MSK (0x1FE0) +#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_OFST (5) +#define PHY_AUTO_NEG_ADVERTISEMENT_RF_MSK (0x2000) +#define PHY_AUTO_NEG_ADVERTISEMENT_RF_OFST (13) +#define PHY_AUTO_NEG_ADVERTISEMENT_RSVD_MSK (0x4000) +#define PHY_AUTO_NEG_ADVERTISEMENT_RVSD_OFST (14) +#define PHY_AUTO_NEG_ADVERTISEMENT_NP_MSK (0x8000) +#define PHY_AUTO_NEG_ADVERTISEMENT_NP_OFST (15) + +#define PHY_AUTO_NEG_LINK_PARTNER (5) +#define PHY_AUTO_NEG_LINK_PARTNER_S4_MSK (0x1F) +#define PHY_AUTO_NEG_LINK_PARTNER_S4_OFST (0) +#define PHY_AUTO_NEG_LINK_PARTNER_A7_MSK (0x1FE0) +#define PHY_AUTO_NEG_LINK_PARTNER_A7_OFST (5) +#define PHY_AUTO_NEG_LINK_PARTNER_RF_MSK (0x2000) +#define PHY_AUTO_NEG_LINK_PARTNER_RF_OFST (13) +#define PHY_AUTO_NEG_LINK_PARTNER_ACK_MSK (0x4000) +#define PHY_AUTO_NEG_LINK_PARTNER_ACK_OFST (14) +#define PHY_AUTO_NEG_LINK_PARTNER_NP_MSK (0x8000) +#define PHY_AUTO_NEG_LINK_PARTNER_NP_OFST (15) + +#define PHY_AUTO_NEG_EXPANSION (6) +#define PHY_AUTO_NEG_EXPANSION_LPANEGA_MSK (0x1) +#define PHY_AUTO_NEG_EXPANSION_LPANEGA_OFST (0) +#define PHY_AUTO_NEG_EXPANSION_PRX_MSK (0x2) +#define PHY_AUTO_NEG_EXPANSION_PRX_OFST (1) +#define PHY_AUTO_NEG_EXPANSION_NPA_MSK (0x4) +#define PHY_AUTO_NEG_EXPANSION_NPA_OFST (2) +#define PHY_AUTO_NEG_EXPANSION_LPNPA_MSK (0x8) +#define PHY_AUTO_NEG_EXPANSION_LPNPA_OFST (3) +#define PHY_AUTO_NEG_EXPANSION_PDF_MSK (0x10) +#define PHY_AUTO_NEG_EXPANSION_PDF_OFST (4) + +#define PHY_VENDOR_SPECIFIC (16) +#define PHY_VENDOR_SPECIFIC_RXCC_MSK (0x1) +#define PHY_VENDOR_SPECIFIC_RXCC_OFST (0) +#define PHY_VENDOR_SPECIFIC_PCSBP_MSK (0x2) +#define PHY_VENDOR_SPECIFIC_PCSBP_OFST (1) +#define PHY_VENDOR_SPECIFIC_RVSPOL_MSK (0x10) +#define PHY_VENDOR_SPECIFIC_RVSPOL_OFST (4) +#define PHY_VENDOR_SPECIFIC_APOL_MSK (0x20) +#define PHY_VENDOR_SPECIFIC_APOL_OFST (5) +#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_MSK (0x40) +#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_OFST (6) +#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_MSK (0x80) +#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_OFST (7) +#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_MSK (0x100) +#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_OFST (8) +#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_MSK (0x200) +#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_OFST (9) +#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_MSK (0x400) +#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_OFST (10) +#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_MSK (0x800) +#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_OFST (11) +#define PHY_VENDOR_SPECIFIC_TXHIM_MSK (0x1000) +#define PHY_VENDOR_SPECIFIC_TXHIM_OFST (12) +#define PHY_VENDOR_SPECIFIC_INT_LEVEL_MSK (0x4000) +#define PHY_VENDOR_SPECIFIC_INT_LEVEL_OFST (14) +#define PHY_VENDOR_SPECIFIC_RPTR_MSK (0x8000) +#define PHY_VENDOR_SPECIFIC_RPTR_OFST (15) + +#define PHY_IRQ_CONTROL (17) +#define PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK (0x1) +#define PHY_IRQ_CONTROL_ANEG_COMP_INT_OFST (0) +#define PHY_IRQ_CONTROL_RFAULT_INT_MSK (0x2) +#define PHY_IRQ_CONTROL_RFAULT_INT_OFST (1) +#define PHY_IRQ_CONTROL_LS_CHG_INT_MSK (0x4) +#define PHY_IRQ_CONTROL_LS_CHG_INT_OFST (2) +#define PHY_IRQ_CONTROL_LP_ACK_INT_MSK (0x8) +#define PHY_IRQ_CONTROL_LP_ACK_INT_OFST (3) +#define PHY_IRQ_CONTROL_PDF_INT_MSK (0x10) +#define PHY_IRQ_CONTROL_PDF_INT_OFST (4) +#define PHY_IRQ_CONTROL_PRX_INT_MSK (0x20) +#define PHY_IRQ_CONTROL_PRX_INT_OFST (5) +#define PHY_IRQ_CONTROL_RXER_INT_MSK (0x40) +#define PHY_IRQ_CONTROL_RXER_INT_OFST (6) +#define PHY_IRQ_CONTROL_JABBER_INT_MSK (0x80) +#define PHY_IRQ_CONTROL_JABBER_INT_OFST (7) +#define PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK (0x100) +#define PHY_IRQ_CONTROL_ANEG_COMP_IE_OFST (8) +#define PHY_IRQ_CONTROL_RFAULT_IE_MSK (0x200) +#define PHY_IRQ_CONTROL_RFAULT_IE_OFST (9) +#define PHY_IRQ_CONTROL_LS_CHG_IE_MSK (0x400) +#define PHY_IRQ_CONTROL_LS_CHG_IE_OFST (10) +#define PHY_IRQ_CONTROL_LP_ACK_IE_MSK (0x800) +#define PHY_IRQ_CONTROL_LP_ACK_IE_OFST (11) +#define PHY_IRQ_CONTROL_PDF_IE_MSK (0x1000) +#define PHY_IRQ_CONTROL_PDF_IE_OFST (12) +#define PHY_IRQ_CONTROL_PRX_IE_MSK (0x2000) +#define PHY_IRQ_CONTROL_PRX_IE_OFST (13) +#define PHY_IRQ_CONTROL_RXER_IE_MSK (0x4000) +#define PHY_IRQ_CONTROL_RXER_IE_OFST (14) +#define PHY_IRQ_CONTROL_JABBER_IE_MSK (0x8000) +#define PHY_IRQ_CONTROL_JABBER_IE_OFST (15) + +#define PHY_DIAGNOSTIC (18) +#define PHY_DIAGNOSTIC_RX_LOCK_MSK (0x100) +#define PHY_DIAGNOSTIC_RX_LOCK_OFST (8) +#define PHY_DIAGNOSTIC_RX_PASS_MSK (0x200) +#define PHY_DIAGNOSTIC_RX_PASS_OFST (9) +#define PHY_DIAGNOSTIC_RATE_MSK (0x400) +#define PHY_DIAGNOSTIC_RATE_OFST (10) +#define PHY_DIAGNOSTIC_DPLX_MSK (0x800) +#define PHY_DIAGNOSTIC_DPLX_OFST (11) +#define PHY_DIAGNOSTIC_ANEGF_MSK (0x1000) +#define PHY_DIAGNOSTIC_ANEGF_OFST (12) + +#endif /* __TDKPHY_H */ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-epxa10db/time.h linux/include/asm-arm/arch-epxa10db/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-epxa10db/time.h Thu Oct 25 13:53:53 2001 +++ linux/include/asm-arm/arch-epxa10db/time.h Sat Jan 5 14:43:18 2002 @@ -42,20 +42,17 @@ /* * Set up timer interrupt, and return the current time in seconds. */ -extern __inline__ void setup_timer(void) +void __init time_init(void) { - - timer_irq.handler = excalibur_timer_interrupt; - /* * Make irqs happen for the system timer */ setup_arm_irq(IRQ_TIMER0, &timer_irq); /* Start the timer */ - *TIMER0_LIMIT(IO_ADDRESS(EXC_TIMER00_BASE))=(unsigned int)(EXC_AHB2_CLK_FREQUENCY/50); + *TIMER0_LIMIT(IO_ADDRESS(EXC_TIMER00_BASE))=(unsigned int)(EXC_AHB2_CLK_FREQUENCY/200); *TIMER0_PRESCALE(IO_ADDRESS(EXC_TIMER00_BASE))=1; *TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))=TIMER0_CR_IE_MSK | TIMER0_CR_S_MSK; } diff -urN linux-2.5.2-pre8/include/asm-arm/arch-integrator/io.h linux/include/asm-arm/arch-integrator/io.h --- linux-2.5.2-pre8/include/asm-arm/arch-integrator/io.h Wed Jul 4 20:11:17 2001 +++ linux/include/asm-arm/arch-integrator/io.h Sat Jan 5 14:43:18 2002 @@ -26,20 +26,4 @@ #define __mem_pci(a) ((unsigned long)(a)) #define __mem_isa(a) (PCI_MEMORY_VADDR + (unsigned long)(a)) -/* - * Generic virtual read/write - */ -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) - -/* - * Validate the pci memory address for ioremap. - */ -#define iomem_valid_addr(iomem,size) (1) - -/* - * Convert PCI memory space to a CPU physical address - */ -#define iomem_to_phys(iomem) (iomem) - #endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-integrator/time.h linux/include/asm-arm/arch-integrator/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-integrator/time.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-integrator/time.h Sat Jan 5 14:43:18 2002 @@ -113,7 +113,7 @@ /* * Set up timer interrupt, and return the current time in seconds. */ -static inline void setup_timer(void) +void __init time_init(void) { volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE; volatile TimerStruct_t *timer1 = (volatile TimerStruct_t *)TIMER1_VA_BASE; diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/dma.h linux/include/asm-arm/arch-iop310/dma.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/dma.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/dma.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,109 @@ +/* + * linux/include/asm-arm/arch-iop80310/dma.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _IOP310_DMA_H_ +#define _IOP310_DMA_H_ + +/* 2 DMA on primary PCI and 1 on secondary for 80310 */ +#define MAX_IOP310_DMA_CHANNEL 3 +#define MAX_DMA_DESC 64 /*128 */ + +/* + * Make the generic DMA bits go away since we don't use it + */ +#define MAX_DMA_CHANNELS 0 + +#define MAX_DMA_ADDRESS 0xffffffff + +#define IOP310_DMA_P0 0 +#define IOP310_DMA_P1 1 +#define IOP310_DMA_S0 2 + +#define DMA_MOD_READ 0x0001 +#define DMA_MOD_WRITE 0x0002 +#define DMA_MOD_CACHED 0x0004 +#define DMA_MOD_NONCACHED 0x0008 + + +#define DMA_DESC_DONE 0x0010 +#define DMA_INCOMPLETE 0x0020 +#define DMA_HOLD 0x0040 +#define DMA_END_CHAIN 0x0080 +#define DMA_COMPLETE 0x0100 +#define DMA_NOTIFY 0x0200 +#define DMA_NEW_HEAD 0x0400 + +#define DMA_USER_MASK (DMA_NOTIFY | DMA_INCOMPLETE | \ + DMA_HOLD | DMA_COMPLETE) + +#define DMA_DCR_DAC 0x00000020 /* Dual Addr Cycle Enab */ +#define DMA_DCR_IE 0x00000010 /* Interrupt Enable */ +#define DMA_DCR_PCI_IOR 0x00000002 /* I/O Read */ +#define DMA_DCR_PCI_IOW 0x00000003 /* I/O Write */ +#define DMA_DCR_PCI_MR 0x00000006 /* Memory Read */ +#define DMA_DCR_PCI_MW 0x00000007 /* Memory Write */ +#define DMA_DCR_PCI_CR 0x0000000A /* Configuration Read */ +#define DMA_DCR_PCI_CW 0x0000000B /* Configuration Write */ +#define DMA_DCR_PCI_MRM 0x0000000C /* Memory Read Multiple */ +#define DMA_DCR_PCI_MRL 0x0000000E /* Memory Read Line */ +#define DMA_DCR_PCI_MWI 0x0000000F /* Mem Write and Inval */ + +#define DMA_USER_CMD_IE 0x00000001 /* user request int */ +#define DMA_USER_END_CHAIN 0x00000002 /* end of sgl chain flag */ + +/* ATU defines */ +#define IOP310_ATUCR_PRIM_OUT_ENAB /* Configuration */ 0x00000002 +#define IOP310_ATUCR_DIR_ADDR_ENAB /* Configuration */ 0x00000080 + + +typedef void (*dma_callback_t) (void *buf_context); +/* + * DMA Descriptor + */ +typedef struct _dma_desc +{ + u32 NDAR; /* next descriptor adress */ + u32 PDAR; /* PCI address */ + u32 PUADR; /* upper PCI address */ + u32 LADR; /* local address */ + u32 BC; /* byte count */ + u32 DC; /* descriptor control */ +} dma_desc_t; + +typedef struct _dma_sgl +{ + dma_desc_t dma_desc; /* DMA descriptor pointer */ + u32 status; /* descriptor status */ + void *data; /* local virt */ + struct _dma_sgl *next; /* next descriptor */ +} dma_sgl_t; + +/* dma sgl head */ +typedef struct _dma_head +{ + u32 total; /* total elements in SGL */ + u32 status; /* status of sgl */ + u32 mode; /* read or write mode */ + dma_sgl_t *list; /* pointer to list */ + dma_callback_t callback; /* callback function */ +} dma_head_t; + +/* function prototypes */ +int dma_request(dmach_t, const char *); +int dma_queue_buffer(dmach_t, dma_head_t *); +int dma_suspend(dmach_t); +int dma_resume(dmach_t); +int dma_flush_all(dmach_t); +void dma_free(dmach_t); +void dma_set_irq_threshold(dmach_t, int); +dma_sgl_t *dma_get_buffer(dmach_t, int); +void dma_return_buffer(dmach_t, dma_sgl_t *); + +#endif /* _ASM_ARCH_DMA_H */ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/hardware.h linux/include/asm-arm/arch-iop310/hardware.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/hardware.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/hardware.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,38 @@ +/* + * linux/include/asm-arm/arch-iop80310/hardware.h + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include + +/* + * Note about PCI IO space mappings + * + * To make IO space accesses efficient, we store virtual addresses in + * the IO resources. + * + * The PCI IO space is located at virtual 0xfe000000 from physical + * 0x90000000. The PCI BARs must be programmed with physical addresses, + * but when we read them, we convert them to virtual addresses. See + * arch/arm/mach-iop310/iop310-pci.c + */ + +#define pcibios_assign_all_busses() 1 + +/* + * these are the values for the secondary PCI bus on the 80312 chip. I will + * have to do some fixup in the bus/dev fixup code + */ +#define PCIBIOS_MIN_IO 0 +#define PCIBIOS_MIN_MEM 0x88000000 + +// Generic chipset bits +#include "iop310.h" + +// Board specific +#if defined(CONFIG_ARCH_IQ80310) +#include "iq80310.h" +#endif + +#endif /* _ASM_ARCH_HARDWARE_H */ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/ide.h linux/include/asm-arm/arch-iop310/ide.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/ide.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/ide.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,51 @@ +/* + * include/asm-arm/arch-iop310/ide.h + * + * Generic IDE functions for IOP310 systems + * + * Author: Deepak Saxena + * + * Copyright 2001 MontaVista Software Inc. + * + * 09/26/2001 - Sharon Baartmans + * Fixed so it actually works. + */ + +#ifndef _ASM_ARCH_IDE_H_ +#define _ASM_ARCH_IDE_H_ + +/* + * Set up a hw structure for a specified data port, control port and IRQ. + * This should follow whatever the default interface uses. + */ +static __inline__ void +ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int *irq) +{ + ide_ioreg_t reg; + int i; + int regincr = 1; + + memset(hw, 0, sizeof(*hw)); + + reg = (ide_ioreg_t)data_port; + + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { + hw->io_ports[i] = reg; + reg += regincr; + } + + hw->io_ports[IDE_CONTROL_OFFSET] = (ide_ioreg_t) ctrl_port; + + if (irq) *irq = 0; +} + +/* + * This registers the standard ports for this architecture with the IDE + * driver. + */ +static __inline__ void ide_init_default_hwifs(void) +{ + /* There are no standard ports */ +} + +#endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/io.h linux/include/asm-arm/arch-iop310/io.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/io.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/io.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,20 @@ +/* + * linux/include/asm-arm/arch-iop310/io.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(p) ((p)) +#define __mem_pci(a) ((unsigned long)(a)) +#define __mem_isa(a) ((unsigned long)(a)) + +#endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/iop310.h linux/include/asm-arm/arch-iop310/iop310.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/iop310.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/iop310.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,247 @@ +/* + * linux/include/asm/arch-iop310/iop310.h + * + * Intel IOP310 Compainion Chip definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _IOP310_HW_H_ +#define _IOP310_HW_H_ + +/* + * IOP310 I/O and Mem space regions for PCI autoconfiguration + */ +#define IOP310_PCISEC_LOWER_IO 0x90010000 +#define IOP310_PCISEC_UPPER_IO 0x9001ffff +#define IOP310_PCISEC_LOWER_MEM 0x88000000 +#define IOP310_PCISEC_UPPER_MEM 0x8bffffff + +#define IOP310_PCIPRI_LOWER_IO 0x90000000 +#define IOP310_PCIPRI_UPPER_IO 0x9000ffff +#define IOP310_PCIPRI_LOWER_MEM 0x80000000 +#define IOP310_PCIPRI_UPPER_MEM 0x83ffffff + +#define IOP310_PCI_WINDOW_SIZE 64 * 0x100000 + +/* + * IOP310 chipset registers + */ +#define IOP310_VIRT_MEM_BASE 0xe8001000 /* chip virtual mem address*/ +#define IOP310_PHY_MEM_BASE 0x00001000 /* chip physical memory address */ +#define IOP310_REG_ADDR(reg) (IOP310_VIRT_MEM_BASE | IOP310_PHY_MEM_BASE | (reg)) + +/* PCI-to-PCI Bridge Unit 0x00001000 through 0x000010FF */ +#define IOP310_VIDR (volatile u16 *)IOP310_REG_ADDR(0x00001000) +#define IOP310_DIDR (volatile u16 *)IOP310_REG_ADDR(0x00001002) +#define IOP310_PCR (volatile u16 *)IOP310_REG_ADDR(0x00001004) +#define IOP310_PSR (volatile u16 *)IOP310_REG_ADDR(0x00001006) +#define IOP310_RIDR (volatile u8 *)IOP310_REG_ADDR(0x00001008) +#define IOP310_CCR (volatile u32 *)IOP310_REG_ADDR(0x00001009) +#define IOP310_CLSR (volatile u8 *)IOP310_REG_ADDR(0x0000100C) +#define IOP310_PLTR (volatile u8 *)IOP310_REG_ADDR(0x0000100D) +#define IOP310_HTR (volatile u8 *)IOP310_REG_ADDR(0x0000100E) +/* Reserved 0x0000100F through 0x00001017 */ +#define IOP310_PBNR (volatile u8 *)IOP310_REG_ADDR(0x00001018) +#define IOP310_SBNR (volatile u8 *)IOP310_REG_ADDR(0x00001019) +#define IOP310_SUBBNR (volatile u8 *)IOP310_REG_ADDR(0x0000101A) +#define IOP310_SLTR (volatile u8 *)IOP310_REG_ADDR(0x0000101B) +#define IOP310_IOBR (volatile u8 *)IOP310_REG_ADDR(0x0000101C) +#define IOP310_IOLR (volatile u8 *)IOP310_REG_ADDR(0x0000101D) +#define IOP310_SSR (volatile u16 *)IOP310_REG_ADDR(0x0000101E) +#define IOP310_MBR (volatile u16 *)IOP310_REG_ADDR(0x00001020) +#define IOP310_MLR (volatile u16 *)IOP310_REG_ADDR(0x00001022) +#define IOP310_PMBR (volatile u16 *)IOP310_REG_ADDR(0x00001024) +#define IOP310_PMLR (volatile u16 *)IOP310_REG_ADDR(0x00001026) +/* Reserved 0x00001028 through 0x00001033 */ +#define IOP310_CAPR (volatile u8 *)IOP310_REG_ADDR(0x00001034) +/* Reserved 0x00001035 through 0x0000103D */ +#define IOP310_BCR (volatile u16 *)IOP310_REG_ADDR(0x0000103E) +#define IOP310_EBCR (volatile u16 *)IOP310_REG_ADDR(0x00001040) +#define IOP310_SISR (volatile u16 *)IOP310_REG_ADDR(0x00001042) +#define IOP310_PBISR (volatile u32 *)IOP310_REG_ADDR(0x00001044) +#define IOP310_SBISR (volatile u32 *)IOP310_REG_ADDR(0x00001048) +#define IOP310_SACR (volatile u32 *)IOP310_REG_ADDR(0x0000104C) +#define IOP310_PIRSR (volatile u32 *)IOP310_REG_ADDR(0x00001050) +#define IOP310_SIOBR (volatile u8 *)IOP310_REG_ADDR(0x00001054) +#define IOP310_SIOLR (volatile u8 *)IOP310_REG_ADDR(0x00001055) +#define IOP310_SCDR (volatile u8 *)IOP310_REG_ADDR(0x00001056) + +#define IOP310_SMBR (volatile u16 *)IOP310_REG_ADDR(0x00001058) +#define IOP310_SMLR (volatile u16 *)IOP310_REG_ADDR(0x0000105A) +#define IOP310_SDER (volatile u16 *)IOP310_REG_ADDR(0x0000105C) +#define IOP310_QCR (volatile u16 *)IOP310_REG_ADDR(0x0000105E) +#define IOP310_CAPID (volatile u8 *)IOP310_REG_ADDR(0x00001068) +#define IOP310_NIPTR (volatile u8 *)IOP310_REG_ADDR(0x00001069) +#define IOP310_PMCR (volatile u16 *)IOP310_REG_ADDR(0x0000106A) +#define IOP310_PMCSR (volatile u16 *)IOP310_REG_ADDR(0x0000106C) +#define IOP310_PMCSRBSE (volatile u8 *)IOP310_REG_ADDR(0x0000106E) +/* Reserved 0x00001064 through 0x000010FFH */ + +/* Performance monitoring unit 0x00001100 through 0x000011FF*/ +#define IOP310_PMONGTMR (volatile u32 *)IOP310_REG_ADDR(0x00001100) +#define IOP310_PMONESR (volatile u32 *)IOP310_REG_ADDR(0x00001104) +#define IOP310_PMONEMISR (volatile u32 *)IOP310_REG_ADDR(0x00001108) +#define IOP310_PMONGTSR (volatile u32 *)IOP310_REG_ADDR(0x00001110) +#define IOP310_PMONPECR1 (volatile u32 *)IOP310_REG_ADDR(0x00001114) +#define IOP310_PMONPECR2 (volatile u32 *)IOP310_REG_ADDR(0x00001118) +#define IOP310_PMONPECR3 (volatile u32 *)IOP310_REG_ADDR(0x0000111C) +#define IOP310_PMONPECR4 (volatile u32 *)IOP310_REG_ADDR(0x00001120) +#define IOP310_PMONPECR5 (volatile u32 *)IOP310_REG_ADDR(0x00001124) +#define IOP310_PMONPECR6 (volatile u32 *)IOP310_REG_ADDR(0x00001128) +#define IOP310_PMONPECR7 (volatile u32 *)IOP310_REG_ADDR(0x0000112C) +#define IOP310_PMONPECR8 (volatile u32 *)IOP310_REG_ADDR(0x00001130) +#define IOP310_PMONPECR9 (volatile u32 *)IOP310_REG_ADDR(0x00001134) +#define IOP310_PMONPECR10 (volatile u32 *)IOP310_REG_ADDR(0x00001138) +#define IOP310_PMONPECR11 (volatile u32 *)IOP310_REG_ADDR(0x0000113C) +#define IOP310_PMONPECR12 (volatile u32 *)IOP310_REG_ADDR(0x00001140) +#define IOP310_PMONPECR13 (volatile u32 *)IOP310_REG_ADDR(0x00001144) +#define IOP310_PMONPECR14 (volatile u32 *)IOP310_REG_ADDR(0x00001148) + +/* Address Translation Unit 0x00001200 through 0x000012FF */ +#define IOP310_ATUVID (volatile u16 *)IOP310_REG_ADDR(0x00001200) +#define IOP310_ATUDID (volatile u16 *)IOP310_REG_ADDR(0x00001202) +#define IOP310_PATUCMD (volatile u16 *)IOP310_REG_ADDR(0x00001204) +#define IOP310_PATUSR (volatile u16 *)IOP310_REG_ADDR(0x00001206) +#define IOP310_ATURID (volatile u8 *)IOP310_REG_ADDR(0x00001208) +#define IOP310_ATUCCR (volatile u32 *)IOP310_REG_ADDR(0x00001209) +#define IOP310_ATUCLSR (volatile u8 *)IOP310_REG_ADDR(0x0000120C) +#define IOP310_ATULT (volatile u8 *)IOP310_REG_ADDR(0x0000120D) +#define IOP310_ATUHTR (volatile u8 *)IOP310_REG_ADDR(0x0000120E) + +#define IOP310_PIABAR (volatile u32 *)IOP310_REG_ADDR(0x00001210) +/* Reserved 0x00001214 through 0x0000122B */ +#define IOP310_ASVIR (volatile u16 *)IOP310_REG_ADDR(0x0000122C) +#define IOP310_ASIR (volatile u16 *)IOP310_REG_ADDR(0x0000122E) +#define IOP310_ERBAR (volatile u32 *)IOP310_REG_ADDR(0x00001230) +#define IOP310_ATUCAPPTR (volatile u8 *)IOP310_REG_ADDR(0x00001234) +/* Reserved 0x00001235 through 0x0000123B */ +#define IOP310_ATUILR (volatile u8 *)IOP310_REG_ADDR(0x0000123C) +#define IOP310_ATUIPR (volatile u8 *)IOP310_REG_ADDR(0x0000123D) +#define IOP310_ATUMGNT (volatile u8 *)IOP310_REG_ADDR(0x0000123E) +#define IOP310_ATUMLAT (volatile u8 *)IOP310_REG_ADDR(0x0000123F) +#define IOP310_PIALR (volatile u32 *)IOP310_REG_ADDR(0x00001240) +#define IOP310_PIATVR (volatile u32 *)IOP310_REG_ADDR(0x00001244) +#define IOP310_SIABAR (volatile u32 *)IOP310_REG_ADDR(0x00001248) +#define IOP310_SIALR (volatile u32 *)IOP310_REG_ADDR(0x0000124C) +#define IOP310_SIATVR (volatile u32 *)IOP310_REG_ADDR(0x00001250) +#define IOP310_POMWVR (volatile u32 *)IOP310_REG_ADDR(0x00001254) +/* Reserved 0x00001258 through 0x0000125B */ +#define IOP310_POIOWVR (volatile u32 *)IOP310_REG_ADDR(0x0000125C) +#define IOP310_PODWVR (volatile u32 *)IOP310_REG_ADDR(0x00001260) +#define IOP310_POUDR (volatile u32 *)IOP310_REG_ADDR(0x00001264) +#define IOP310_SOMWVR (volatile u32 *)IOP310_REG_ADDR(0x00001268) +#define IOP310_SOIOWVR (volatile u32 *)IOP310_REG_ADDR(0x0000126C) +/* Reserved 0x00001270 through 0x00001273*/ +#define IOP310_ERLR (volatile u32 *)IOP310_REG_ADDR(0x00001274) +#define IOP310_ERTVR (volatile u32 *)IOP310_REG_ADDR(0x00001278) +/* Reserved 0x00001279 through 0x0000127C*/ +#define IOP310_ATUCAPID (volatile u8 *)IOP310_REG_ADDR(0x00001280) +#define IOP310_ATUNIPTR (volatile u8 *)IOP310_REG_ADDR(0x00001281) +#define IOP310_APMCR (volatile u16 *)IOP310_REG_ADDR(0x00001282) +#define IOP310_APMCSR (volatile u16 *)IOP310_REG_ADDR(0x00001284) +/* Reserved 0x00001286 through 0x00001287 */ +#define IOP310_ATUCR (volatile u32 *)IOP310_REG_ADDR(0x00001288) +/* Reserved 0x00001289 through 0x0000128C*/ +#define IOP310_PATUISR (volatile u32 *)IOP310_REG_ADDR(0x00001290) +#define IOP310_SATUISR (volatile u32 *)IOP310_REG_ADDR(0x00001294) +#define IOP310_SATUCMD (volatile u16 *)IOP310_REG_ADDR(0x00001298) +#define IOP310_SATUSR (volatile u16 *)IOP310_REG_ADDR(0x0000129A) +#define IOP310_SODWVR (volatile u32 *)IOP310_REG_ADDR(0x0000129C) +#define IOP310_SOUDR (volatile u32 *)IOP310_REG_ADDR(0x000012A0) +#define IOP310_POCCAR (volatile u32 *)IOP310_REG_ADDR(0x000012A4) +#define IOP310_SOCCAR (volatile u32 *)IOP310_REG_ADDR(0x000012A8) +#define IOP310_POCCDR (volatile u32 *)IOP310_REG_ADDR(0x000012AC) +#define IOP310_SOCCDR (volatile u32 *)IOP310_REG_ADDR(0x000012B0) +#define IOP310_PAQCR (volatile u32 *)IOP310_REG_ADDR(0x000012B4) +#define IOP310_SAQCR (volatile u32 *)IOP310_REG_ADDR(0x000012B8) +#define IOP310_PATUIMR (volatile u32 *)IOP310_REG_ADDR(0x000012BC) +#define IOP310_SATUIMR (volatile u32 *)IOP310_REG_ADDR(0x000012C0) +/* Reserved 0x000012C4 through 0x000012FF */ +/* Messaging Unit 0x00001300 through 0x000013FF */ +#define IOP310_MUIMR0 (volatile u32 *)IOP310_REG_ADDR(0x00001310) +#define IOP310_MUIMR1 (volatile u32 *)IOP310_REG_ADDR(0x00001314) +#define IOP310_MUOMR0 (volatile u32 *)IOP310_REG_ADDR(0x00001318) +#define IOP310_MUOMR1 (volatile u32 *)IOP310_REG_ADDR(0x0000131C) +#define IOP310_MUIDR (volatile u32 *)IOP310_REG_ADDR(0x00001320) +#define IOP310_MUIISR (volatile u32 *)IOP310_REG_ADDR(0x00001324) +#define IOP310_MUIIMR (volatile u32 *)IOP310_REG_ADDR(0x00001328) +#define IOP310_MUODR (volatile u32 *)IOP310_REG_ADDR(0x0000132C) +#define IOP310_MUOISR (volatile u32 *)IOP310_REG_ADDR(0x00001330) +#define IOP310_MUOIMR (volatile u32 *)IOP310_REG_ADDR(0x00001334) +#define IOP310_MUMUCR (volatile u32 *)IOP310_REG_ADDR(0x00001350) +#define IOP310_MUQBAR (volatile u32 *)IOP310_REG_ADDR(0x00001354) +#define IOP310_MUIFHPR (volatile u32 *)IOP310_REG_ADDR(0x00001360) +#define IOP310_MUIFTPR (volatile u32 *)IOP310_REG_ADDR(0x00001364) +#define IOP310_MUIPHPR (volatile u32 *)IOP310_REG_ADDR(0x00001368) +#define IOP310_MUIPTPR (volatile u32 *)IOP310_REG_ADDR(0x0000136C) +#define IOP310_MUOFHPR (volatile u32 *)IOP310_REG_ADDR(0x00001370) +#define IOP310_MUOFTPR (volatile u32 *)IOP310_REG_ADDR(0x00001374) +#define IOP310_MUOPHPR (volatile u32 *)IOP310_REG_ADDR(0x00001378) +#define IOP310_MUOPTPR (volatile u32 *)IOP310_REG_ADDR(0x0000137C) +#define IOP310_MUIAR (volatile u32 *)IOP310_REG_ADDR(0x00001380) +/* DMA Controller 0x00001400 through 0x000014FF */ +#define IOP310_DMA0CCR (volatile u32 *)IOP310_REG_ADDR(0x00001400) +#define IOP310_DMA0CSR (volatile u32 *)IOP310_REG_ADDR(0x00001404) +/* Reserved 0x001408 through 0x00140B */ +#define IOP310_DMA0DAR (volatile u32 *)IOP310_REG_ADDR(0x0000140C) +#define IOP310_DMA0NDAR (volatile u32 *)IOP310_REG_ADDR(0x00001410) +#define IOP310_DMA0PADR (volatile u32 *)IOP310_REG_ADDR(0x00001414) +#define IOP310_DMA0PUADR (volatile u32 *)IOP310_REG_ADDR(0x00001418) +#define IOP310_DMA0LADR (volatile u32 *)IOP310_REG_ADDR(0x0000141C) +#define IOP310_DMA0BCR (volatile u32 *)IOP310_REG_ADDR(0x00001420) +#define IOP310_DMA0DCR (volatile u32 *)IOP310_REG_ADDR(0x00001424) +/* Reserved 0x00001428 through 0x0000143F */ +#define IOP310_DMA1CCR (volatile u32 *)IOP310_REG_ADDR(0x00001440) +#define IOP310_DMA1CSR (volatile u32 *)IOP310_REG_ADDR(0x00001444) +/* Reserved 0x00001448 through 0x0000144B */ +#define IOP310_DMA1DAR (volatile u32 *)IOP310_REG_ADDR(0x0000144C) +#define IOP310_DMA1NDAR (volatile u32 *)IOP310_REG_ADDR(0x00001450) +#define IOP310_DMA1PADR (volatile u32 *)IOP310_REG_ADDR(0x00001454) +#define IOP310_DMA1PUADR (volatile u32 *)IOP310_REG_ADDR(0x00001458) +#define IOP310_DMA1LADR (volatile u32 *)IOP310_REG_ADDR(0x0000145C) +#define IOP310_DMA1BCR (volatile u32 *)IOP310_REG_ADDR(0x00001460) +#define IOP310_DMA1DCR (volatile u32 *)IOP310_REG_ADDR(0x00001464) +/* Reserved 0x00001468 through 0x0000147F */ +#define IOP310_DMA2CCR (volatile u32 *)IOP310_REG_ADDR(0x00001480) +#define IOP310_DMA2CSR (volatile u32 *)IOP310_REG_ADDR(0x00001484) +/* Reserved 0x00001488 through 0x0000148B */ +#define IOP310_DMA2DAR (volatile u32 *)IOP310_REG_ADDR(0x0000148C) +#define IOP310_DMA2NDAR (volatile u32 *)IOP310_REG_ADDR(0x00001490) +#define IOP310_DMA2PADR (volatile u32 *)IOP310_REG_ADDR(0x00001494) +#define IOP310_DMA2PUADR (volatile u32 *)IOP310_REG_ADDR(0x00001498) +#define IOP310_DMA2LADR (volatile u32 *)IOP310_REG_ADDR(0x0000149C) +#define IOP310_DMA2BCR (volatile u32 *)IOP310_REG_ADDR(0x000014A0) +#define IOP310_DMA2DCR (volatile u32 *)IOP310_REG_ADDR(0x000014A4) + +/* Memory controller 0x00001500 through 0x0015FF */ + +/* core interface unit 0x00001640 - 0x0000167F */ +#define IOP310_CIUISR (volatile u32 *)IOP310_REG_ADDR(0x00001644) + +/* PCI and Peripheral Interrupt Controller 0x00001700 - 0x0000171B */ +#define IOP310_IRQISR (volatile u32 *)IOP310_REG_ADDR(0x00001700) +#define IOP310_FIQ2ISR (volatile u32 *)IOP310_REG_ADDR(0x00001704) +#define IOP310_FIQ1ISR (volatile u32 *)IOP310_REG_ADDR(0x00001708) +#define IOP310_PDIDR (volatile u32 *)IOP310_REG_ADDR(0x00001710) + +/* AAU registers. DJ 0x00001800 - 0x00001838 */ +#define IOP310_AAUACR (volatile u32 *)IOP310_REG_ADDR(0x00001800) +#define IOP310_AAUASR (volatile u32 *)IOP310_REG_ADDR(0x00001804) +#define IOP310_AAUADAR (volatile u32 *)IOP310_REG_ADDR(0x00001808) +#define IOP310_AAUANDAR (volatile u32 *)IOP310_REG_ADDR(0x0000180C) +#define IOP310_AAUSAR1 (volatile u32 *)IOP310_REG_ADDR(0x00001810) +#define IOP310_AAUSAR2 (volatile u32 *)IOP310_REG_ADDR(0x00001814) +#define IOP310_AAUSAR3 (volatile u32 *)IOP310_REG_ADDR(0x00001818) +#define IOP310_AAUSAR4 (volatile u32 *)IOP310_REG_ADDR(0x0000181C) +#define IOP310_AAUDAR (volatile u32 *)IOP310_REG_ADDR(0x00001820) +#define IOP310_AAUABCR (volatile u32 *)IOP310_REG_ADDR(0x00001824) +#define IOP310_AAUADCR (volatile u32 *)IOP310_REG_ADDR(0x00001828) +#define IOP310_AAUSAR5 (volatile u32 *)IOP310_REG_ADDR(0x0000182C) +#define IOP310_AAUSAR6 (volatile u32 *)IOP310_REG_ADDR(0x00001830) +#define IOP310_AAUSAR7 (volatile u32 *)IOP310_REG_ADDR(0x00001834) +#define IOP310_AAUSAR8 (volatile u32 *)IOP310_REG_ADDR(0x00001838) + +#endif // _IOP310_HW_H_ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/iq80310.h linux/include/asm-arm/arch-iop310/iq80310.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/iq80310.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/iq80310.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,30 @@ +/* + * linux/include/asm/arch-iop80310/iq80310.h + * + * Intel IQ-80310 evaluation board registers + */ + +#ifndef _IQ80310_H_ +#define _IQ80310_H_ + +#define IQ80310_RAMBASE 0xa0000000 +#define IQ80310_UART1 0xfe800000 /* UART #1 */ +#define IQ80310_UART2 0xfe810000 /* UART #2 */ +#define IQ80310_INT_STAT 0xfe820000 /* Interrupt (XINT3#) Status */ +#define IQ80310_BOARD_REV 0xfe830000 /* Board revision register */ +#define IQ80310_CPLD_REV 0xfe840000 /* CPLD revision register */ +#define IQ80310_7SEG_1 0xfe840000 /* 7-Segment MSB */ +#define IQ80310_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ +#define IQ80310_PCI_INT_STAT 0xfe850000 /* PCI Interrupt Status */ +#define IQ80310_INT_MASK 0xfe860000 /* Interrupt (XINT3#) Mask */ +#define IQ80310_BACKPLANE 0xfe870000 /* Backplane Detect */ +#define IQ80310_TIMER_LA0 0xfe880000 /* Timer LA0 */ +#define IQ80310_TIMER_LA1 0xfe890000 /* Timer LA1 */ +#define IQ80310_TIMER_LA2 0xfe8a0000 /* Timer LA2 */ +#define IQ80310_TIMER_LA3 0xfe8b0000 /* Timer LA3 */ +#define IQ80310_TIMER_EN 0xfe8c0000 /* Timer Enable */ +#define IQ80310_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ +#define IQ80310_JTAG 0xfe8e0000 /* JTAG Port Access */ +#define IQ80310_BATT_STAT 0xfe8f0000 /* Battery Status */ + +#endif // _IQ80310_H_ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/irq.h linux/include/asm-arm/arch-iop310/irq.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/irq.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/irq.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,13 @@ +/* + * linux/include/asm-arm/arch-iop80310/irq.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define fixup_irq(irq) (irq) + + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/irqs.h linux/include/asm-arm/arch-iop310/irqs.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/irqs.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/irqs.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,80 @@ +/* + * linux/include/asm-arm/arch-iop310/irqs.h + * + * Author: Nicolas Pitre + * Copyright: (C) 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * 06/13/01: Added 80310 on-chip interrupt sources + * + */ + + +/* + * XS80200 specific IRQs + */ +#define IRQ_XS80200_BCU 0 /* Bus Control Unit */ +#define IRQ_XS80200_PMU 1 /* Performance Monitoring Unit */ +#define IRQ_XS80200_EXTIRQ 2 /* external IRQ signal */ +#define IRQ_XS80200_EXTFIQ 3 /* external IRQ signal */ + +#define NR_XS80200_IRQS 4 + +#define XSCALE_PMU_IRQ IRQ_XS80200_PMU + +/* + * IOP80310 chipset interrupts + */ +#define IOP310_IRQ_OFS NR_XS80200_IRQS +#define IOP310_IRQ(x) (IOP310_IRQ_OFS + (x)) + +/* + * On FIQ1ISR register + */ +#define IRQ_IOP310_DMA0 IOP310_IRQ(0) /* DMA Channel 0 */ +#define IRQ_IOP310_DMA1 IOP310_IRQ(1) /* DMA Channel 1 */ +#define IRQ_IOP310_DMA2 IOP310_IRQ(2) /* DMA Channel 2 */ +#define IRQ_IOP310_PMON IOP310_IRQ(3) /* Bus performance Unit */ +#define IRQ_IOP310_AAU IOP310_IRQ(4) /* Application Accelator Unit */ + +/* + * On FIQ2ISR register + */ +#define IRQ_IOP310_I2C IOP310_IRQ(5) /* I2C unit */ +#define IRQ_IOP310_MU IOP310_IRQ(6) /* messaging unit */ + +#define NR_IOP310_IRQS (IOP310_IRQ(6) + 1) + +#define NR_IRQS NR_IOP310_IRQS + + +/* + * Interrupts available on the Cyclone IQ80310 board + */ +#ifdef CONFIG_ARCH_IQ80310 + +#define IQ80310_IRQ_OFS NR_IOP310_IRQS +#define IQ80310_IRQ(y) ((IQ80310_IRQ_OFS) + (y)) + +#define IRQ_IQ80310_TIMER IQ80310_IRQ(0) /* Timer Interrupt */ +#define IRQ_IQ80310_I82559 IQ80310_IRQ(1) /* I82559 Ethernet Interrupt */ +#define IRQ_IQ80310_UART1 IQ80310_IRQ(2) /* UART1 Interrupt */ +#define IRQ_IQ80310_UART2 IQ80310_IRQ(3) /* UART2 Interrupt */ +#define IRQ_IQ80310_INTD IQ80310_IRQ(4) /* PCI INTD */ + + +/* + * ONLY AVAILABLE ON REV F OR NEWER BOARDS! + */ +#define IRQ_IQ80310_INTA IQ80310_IRQ(5) /* PCI INTA */ +#define IRQ_IQ80310_INTB IQ80310_IRQ(6) /* PCI INTB */ +#define IRQ_IQ80310_INTC IQ80310_IRQ(7) /* PCI INTC */ + +#undef NR_IRQS +#define NR_IRQS (IQ80310_IRQ(7) + 1) + +#endif // CONFIG_ARCH_IQ80310 + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/memory.h linux/include/asm-arm/arch-iop310/memory.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/memory.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/memory.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,58 @@ +/* + * linux/include/asm-arm/arch-iop80310/memory.h + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + + +/* + * Task size: 3GB + */ +#define TASK_SIZE (0xc0000000UL) +#define TASK_SIZE_26 (0x04000000UL) + +/* + * This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) + +/* + * Page offset: 3GB + */ +#define PAGE_OFFSET (0xc0000000UL) + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET (0xa0000000UL) + +/* + * physical vs virtual ram conversion + */ +#define __virt_to_phys__is_a_macro +#define __phys_to_virt__is_a_macro +#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) +#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ +#define __virt_to_bus__is_a_macro +#define __bus_to_virt__is_a_macro +#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP310_SIATVR)) | ((*IOP310_SIABAR) & 0xfffffff0)) +#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP310_SIALR)) | ( *IOP310_SIATVR))) + +#define PHYS_TO_NID(x) 0 + +/* boot mem allocate global pointer for MU circular queues QBAR */ +#ifdef CONFIG_IOP310_MU +extern void *mu_mem; +#endif + +#endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/param.h linux/include/asm-arm/arch-iop310/param.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/param.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/param.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,3 @@ +/* + * linux/include/asm-arm/arch-iop80310/param.h + */ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/pmon.h linux/include/asm-arm/arch-iop310/pmon.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/pmon.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/pmon.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,50 @@ +/* + * Definitions for XScale 80312 PMON + * (C) 2001 Intel Corporation + * Author: Chen Chen(chen.chen@intel.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _IOP310_PMON_H_ +#define _IOP310_PMON_H_ + +/* + * Different modes for Event Select Register for intel 80312 + */ + +#define IOP310_PMON_MODE0 0x00000000 +#define IOP310_PMON_MODE1 0x00000001 +#define IOP310_PMON_MODE2 0x00000002 +#define IOP310_PMON_MODE3 0x00000003 +#define IOP310_PMON_MODE4 0x00000004 +#define IOP310_PMON_MODE5 0x00000005 +#define IOP310_PMON_MODE6 0x00000006 +#define IOP310_PMON_MODE7 0x00000007 + +typedef struct _iop310_pmon_result +{ + u32 timestamp; /* Global Time Stamp Register */ + u32 timestamp_overflow; /* Time Stamp overflow count */ + u32 event_count[14]; /* Programmable Event Counter + Registers 1-14 */ + u32 event_overflow[14]; /* Overflow counter for PECR1-14 */ +} iop310_pmon_res_t; + +/* function prototypes */ + +/* Claim IQ80312 PMON for usage */ +int iop310_pmon_claim(void); + +/* Start IQ80312 PMON */ +int iop310_pmon_start(int, int); + +/* Stop Performance Monitor Unit */ +int iop310_pmon_stop(iop310_pmon_res_t *); + +/* Release IQ80312 PMON */ +int iop310_pmon_release(int); + +#endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/serial.h linux/include/asm-arm/arch-iop310/serial.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/serial.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/serial.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,34 @@ +/* + * include/asm-arm/arch-iop310/serial.h + */ + + +/* + * This assumes you have a 1.8432 MHz clock for your UART. + * + * It'd be nice if someone built a serial card with a 24.576 MHz + * clock, since the 16550A is capable of handling a top speed of 1.5 + * megabits/second; but this requires the faster clock. + */ +#define BASE_BAUD ( 1843200 / 16 ) + +/* Standard COM flags */ +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) + +#ifdef CONFIG_ARCH_IQ80310 + +#define IRQ_UART1 IRQ_IQ80310_UART1 +#define IRQ_UART2 IRQ_IQ80310_UART2 + +#define RS_TABLE_SIZE 2 + +#define STD_SERIAL_PORT_DEFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0xfe810000, IRQ_UART2, STD_COM_FLAGS }, /* ttyS0 */ \ + { 0, BASE_BAUD, 0xfe800000, IRQ_UART1, STD_COM_FLAGS } /* ttyS1 */ + +#endif // CONFIG_ARCH_IQ80310 + + +#define EXTRA_SERIAL_PORT_DEFNS + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/system.h linux/include/asm-arm/arch-iop310/system.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/system.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/system.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,30 @@ +/* + * linux/include/asm-arm/arch-iop80310/system.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +static inline void arch_idle(void) +{ + if (!hlt_counter) + { + cpu_do_idle(0); + } +} + + +static inline void arch_reset(char mode) +{ + if ( 1 && mode == 's') { + /* Jump into ROM at address 0 */ + cpu_reset(0); + } else { + /* No on-chip reset capability */ + cpu_reset(0); + } +} + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/time.h linux/include/asm-arm/arch-iop310/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/time.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/time.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,12 @@ +/* + * linux/include/asm-arm/arch-iop80310/time.h + * + * Author: Nicolas Pitre + * Copyright: (C) 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/timex.h linux/include/asm-arm/arch-iop310/timex.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/timex.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/timex.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,23 @@ +/* + * linux/include/asm-arm/arch-iop80310/timex.h + * + * IOP310 architecture timex specifications + */ + + + +#ifdef CONFIG_ARCH_IQ80310 + +#ifndef CONFIG_XSCALE_PMU_TIMER +/* This is for the on-board timer */ +#define CLOCK_TICK_RATE 33000000 /* Underlying HZ */ +#else +/* This is for the underlying xs80200 PMU clock. We run the core @ 733MHz */ +#define CLOCK_TICK_RATE 733000000 +#endif + +#else + +#error "No IOP310 timex information for this architecture" + +#endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/uncompress.h linux/include/asm-arm/arch-iop310/uncompress.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/uncompress.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/uncompress.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,33 @@ +/* + * linux/include/asm-arm/arch-iop80310/uncompress.h + */ + +#ifdef CONFIG_ARCH_IQ80310 +#define UART1_BASE ((volatile unsigned char *)0xfe800000) +#define UART2_BASE ((volatile unsigned char *)0xfe810000) +#endif + +static __inline__ void putc(char c) +{ + while ((UART2_BASE[5] & 0x60) != 0x60); + UART2_BASE[0] = c; +} + +/* + * This does not append a newline + */ +static void puts(const char *s) +{ + while (*s) { + putc(*s); + if (*s == '\n') + putc('\r'); + s++; + } +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff -urN linux-2.5.2-pre8/include/asm-arm/arch-iop310/vmalloc.h linux/include/asm-arm/arch-iop310/vmalloc.h --- linux-2.5.2-pre8/include/asm-arm/arch-iop310/vmalloc.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-iop310/vmalloc.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,16 @@ +/* + * linux/include/asm-arm/arch-iop310/vmalloc.h + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) +#define VMALLOC_END (0xe8000000) diff -urN linux-2.5.2-pre8/include/asm-arm/arch-l7200/io.h linux/include/asm-arm/arch-l7200/io.h --- linux-2.5.2-pre8/include/asm-arm/arch-l7200/io.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-l7200/io.h Sat Jan 5 14:43:18 2002 @@ -73,6 +73,4 @@ #define outw(v,p) outw_t(v,p) #define outl(v,p) outl_t(v,p) -#define __arch_ioremap __ioremap - #endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-l7200/irq.h linux/include/asm-arm/arch-l7200/irq.h --- linux-2.5.2-pre8/include/asm-arm/arch-l7200/irq.h Thu Apr 12 12:20:31 2001 +++ linux/include/asm-arm/arch-l7200/irq.h Sat Jan 5 14:43:18 2002 @@ -9,60 +9,4 @@ * 04-15-2000 RS Made dependent on hardware.h * 05-05-2000 SJH Complete rewrite */ - -#include - -/* - * IRQ base register - */ -#define IRQ_BASE (IO_BASE_2 + 0x1000) - -/* - * Normal IRQ registers - */ -#define IRQ_STATUS (*(volatile unsigned long *) (IRQ_BASE + 0x000)) -#define IRQ_RAWSTATUS (*(volatile unsigned long *) (IRQ_BASE + 0x004)) -#define IRQ_ENABLE (*(volatile unsigned long *) (IRQ_BASE + 0x008)) -#define IRQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x00c)) -#define IRQ_SOFT (*(volatile unsigned long *) (IRQ_BASE + 0x010)) -#define IRQ_SOURCESEL (*(volatile unsigned long *) (IRQ_BASE + 0x018)) - -/* - * Fast IRQ registers - */ -#define FIQ_STATUS (*(volatile unsigned long *) (IRQ_BASE + 0x100)) -#define FIQ_RAWSTATUS (*(volatile unsigned long *) (IRQ_BASE + 0x104)) -#define FIQ_ENABLE (*(volatile unsigned long *) (IRQ_BASE + 0x108)) -#define FIQ_ENABLECLEAR (*(volatile unsigned long *) (IRQ_BASE + 0x10c)) -#define FIQ_SOFT (*(volatile unsigned long *) (IRQ_BASE + 0x110)) -#define FIQ_SOURCESEL (*(volatile unsigned long *) (IRQ_BASE + 0x118)) - #define fixup_irq(x) (x) - -static void l7200_mask_irq(unsigned int irq) -{ - IRQ_ENABLECLEAR = 1 << irq; -} - -static void l7200_unmask_irq(unsigned int irq) -{ - IRQ_ENABLE = 1 << irq; -} - -static __inline__ void irq_init_irq(void) -{ - int irq; - - IRQ_ENABLECLEAR = 0xffffffff; /* clear all interrupt enables */ - FIQ_ENABLECLEAR = 0xffffffff; /* clear all fast interrupt enables */ - - for (irq = 0; irq < NR_IRQS; irq++) { - irq_desc[irq].valid = 1; - irq_desc[irq].probe_ok = 1; - irq_desc[irq].mask_ack = l7200_mask_irq; - irq_desc[irq].mask = l7200_mask_irq; - irq_desc[irq].unmask = l7200_unmask_irq; - } - - init_FIQ(); -} diff -urN linux-2.5.2-pre8/include/asm-arm/arch-l7200/keyboard.h linux/include/asm-arm/arch-l7200/keyboard.h --- linux-2.5.2-pre8/include/asm-arm/arch-l7200/keyboard.h Wed May 16 15:25:16 2001 +++ linux/include/asm-arm/arch-l7200/keyboard.h Sat Jan 5 14:43:18 2002 @@ -17,6 +17,8 @@ #include +#error This needs fixing --rmk + /* * Layout of L7200 keyboard registers */ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-l7200/time.h linux/include/asm-arm/arch-l7200/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-l7200/time.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-l7200/time.h Sat Jan 5 14:43:18 2002 @@ -52,7 +52,7 @@ /* * Set up RTC timer interrupt, and return the current time in seconds. */ -static inline void setup_timer(void) +void __init time_init(void) { RTC_RTCC = 0; /* Clear interrupt */ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-nexuspci/io.h linux/include/asm-arm/arch-nexuspci/io.h --- linux-2.5.2-pre8/include/asm-arm/arch-nexuspci/io.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-nexuspci/io.h Sat Jan 5 14:43:18 2002 @@ -37,12 +37,6 @@ #endif /* - * Generic virtual read/write - */ -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) - -/* * ioremap support - validate a PCI memory address, * and convert a PCI memory address to a physical * address for the page tables. @@ -50,5 +44,16 @@ #define iomem_valid_addr(iomem,sz) \ ((iomem) < 0x80000000 && (iomem) + (sz) <= 0x80000000) #define iomem_to_phys(iomem) ((iomem) + PLX_MEM_START) + +#define __arch_ioremap(off,sz,nocache) \ + ({ \ + unsigned long _off = (off), _size = (sz); \ + void *_ret = (void *)0; \ + if (iomem_valid_addr(_off, _size)) \ + _ret = __ioremap(iomem_to_phys(_off),_size,0); \ + _ret; \ + }) + +#define __arch_iounmap __iounmap #endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-nexuspci/irq.h linux/include/asm-arm/arch-nexuspci/irq.h --- linux-2.5.2-pre8/include/asm-arm/arch-nexuspci/irq.h Mon Sep 18 15:15:23 2000 +++ linux/include/asm-arm/arch-nexuspci/irq.h Sat Jan 5 14:43:18 2002 @@ -10,60 +10,5 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ - -#include - #define fixup_irq(x) (x) -extern unsigned long soft_irq_mask; - -static const unsigned char irq_cmd[] = -{ - INTCONT_IRQ_DUART, - INTCONT_IRQ_PLX, - INTCONT_IRQ_D, - INTCONT_IRQ_C, - INTCONT_IRQ_B, - INTCONT_IRQ_A, - INTCONT_IRQ_SYSERR -}; - -static void ftvpci_mask_irq(unsigned int irq) -{ - __raw_writel(irq_cmd[irq], INTCONT_BASE); - soft_irq_mask &= ~(1<= FIRST_IRQ && i <= LAST_IRQ) { - irq_desc[i].valid = 1; - irq_desc[i].probe_ok = 1; - irq_desc[i].mask_ack = ftvpci_mask_irq; - irq_desc[i].mask = ftvpci_mask_irq; - irq_desc[i].unmask = ftvpci_unmask_irq; - ftvpci_mask_irq(i); - } else { - irq_desc[i].valid = 0; - irq_desc[i].probe_ok = 0; - } - } -} diff -urN linux-2.5.2-pre8/include/asm-arm/arch-nexuspci/time.h linux/include/asm-arm/arch-nexuspci/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-nexuspci/time.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-nexuspci/time.h Sat Jan 5 14:43:18 2002 @@ -43,7 +43,7 @@ do_timer(regs); } -static inline void setup_timer(void) +void __init time_init(void) { int tick = 3686400 / 16 / 2 / 100; diff -urN linux-2.5.2-pre8/include/asm-arm/arch-rpc/io.h linux/include/asm-arm/arch-rpc/io.h --- linux-2.5.2-pre8/include/asm-arm/arch-rpc/io.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-rpc/io.h Sat Jan 5 14:43:18 2002 @@ -241,4 +241,10 @@ /* the following macro is depreciated */ #define ioaddr(port) __ioaddr((port)) +#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) +#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) + +#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l) +#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l) + #endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-rpc/irq.h linux/include/asm-arm/arch-rpc/irq.h --- linux-2.5.2-pre8/include/asm-arm/arch-rpc/irq.h Thu Apr 12 12:20:31 2001 +++ linux/include/asm-arm/arch-rpc/irq.h Sat Jan 5 14:43:18 2002 @@ -11,142 +11,4 @@ * 10-10-1996 RMK Brought up to date with arch-sa110eval * 22-08-1998 RMK Restructured IRQ routines */ -#include -#include - #define fixup_irq(x) (x) - -static void rpc_mask_irq_ack_a(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << irq; - val = iomd_readb(IOMD_IRQMASKA); - iomd_writeb(val & ~mask, IOMD_IRQMASKA); - iomd_writeb(mask, IOMD_IRQCLRA); -} - -static void rpc_mask_irq_a(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << irq; - val = iomd_readb(IOMD_IRQMASKA); - iomd_writeb(val & ~mask, IOMD_IRQMASKA); -} - -static void rpc_unmask_irq_a(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << irq; - val = iomd_readb(IOMD_IRQMASKA); - iomd_writeb(val | mask, IOMD_IRQMASKA); -} - -static void rpc_mask_irq_b(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_IRQMASKB); - iomd_writeb(val & ~mask, IOMD_IRQMASKB); -} - -static void rpc_unmask_irq_b(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_IRQMASKB); - iomd_writeb(val | mask, IOMD_IRQMASKB); -} - -static void rpc_mask_irq_dma(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_DMAMASK); - iomd_writeb(val & ~mask, IOMD_DMAMASK); -} - -static void rpc_unmask_irq_dma(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_DMAMASK); - iomd_writeb(val | mask, IOMD_DMAMASK); -} - -static void rpc_mask_irq_fiq(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_FIQMASK); - iomd_writeb(val & ~mask, IOMD_FIQMASK); -} - -static void rpc_unmask_irq_fiq(unsigned int irq) -{ - unsigned int val, mask; - - mask = 1 << (irq & 7); - val = iomd_readb(IOMD_FIQMASK); - iomd_writeb(val | mask, IOMD_FIQMASK); -} - -static __inline__ void irq_init_irq(void) -{ - int irq; - - iomd_writeb(0, IOMD_IRQMASKA); - iomd_writeb(0, IOMD_IRQMASKB); - iomd_writeb(0, IOMD_FIQMASK); - iomd_writeb(0, IOMD_DMAMASK); - - for (irq = 0; irq < NR_IRQS; irq++) { - switch (irq) { - case 0 ... 6: - irq_desc[irq].probe_ok = 1; - case 7: - irq_desc[irq].valid = 1; - irq_desc[irq].mask_ack = rpc_mask_irq_ack_a; - irq_desc[irq].mask = rpc_mask_irq_a; - irq_desc[irq].unmask = rpc_unmask_irq_a; - break; - - case 9 ... 15: - irq_desc[irq].probe_ok = 1; - case 8: - irq_desc[irq].valid = 1; - irq_desc[irq].mask_ack = rpc_mask_irq_b; - irq_desc[irq].mask = rpc_mask_irq_b; - irq_desc[irq].unmask = rpc_unmask_irq_b; - break; - - case 16 ... 19: - case 21: - irq_desc[irq].noautoenable = 1; - case 20: - irq_desc[irq].valid = 1; - irq_desc[irq].mask_ack = rpc_mask_irq_dma; - irq_desc[irq].mask = rpc_mask_irq_dma; - irq_desc[irq].unmask = rpc_unmask_irq_dma; - break; - - case 64 ... 71: - irq_desc[irq].valid = 1; - irq_desc[irq].mask_ack = rpc_mask_irq_fiq; - irq_desc[irq].mask = rpc_mask_irq_fiq; - irq_desc[irq].unmask = rpc_unmask_irq_fiq; - break; - } - } - - irq_desc[IRQ_KEYBOARDTX].noautoenable = 1; - - init_FIQ(); -} diff -urN linux-2.5.2-pre8/include/asm-arm/arch-rpc/time.h linux/include/asm-arm/arch-rpc/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-rpc/time.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-rpc/time.h Sat Jan 5 14:43:18 2002 @@ -24,7 +24,7 @@ /* * Set up timer interrupt. */ -static inline void setup_timer(void) +void __init time_init(void) { ioctime_init(); diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/SA-1111.h linux/include/asm-arm/arch-sa1100/SA-1111.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/SA-1111.h Thu Oct 25 13:53:54 2001 +++ linux/include/asm-arm/arch-sa1100/SA-1111.h Sat Jan 5 14:43:18 2002 @@ -1,647 +1,5 @@ /* - * linux/include/asm/arch/SA-1111.h - * - * Copyright (C) 2000 John G Dorsey - * - * This file contains definitions for the SA-1111 Companion Chip. - * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.) - * + * Moved to new location */ - -#ifndef _ASM_ARCH_SA1111 -#define _ASM_ARCH_SA1111 - -#include - -/* - * Macro that calculates real address for registers in the SA-1111 - */ - -#define _SA1111( x ) ((x) + SA1111_BASE) - -/* - * 26 bits of the SA-1110 address bus are available to the SA-1111. - * Use these when feeding target addresses to the DMA engines. - */ - -#define SA1111_ADDR_WIDTH (26) -#define SA1111_ADDR_MASK ((1< +#include diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/assabet.h linux/include/asm-arm/arch-sa1100/assabet.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/assabet.h Thu Oct 25 13:53:54 2001 +++ linux/include/asm-arm/arch-sa1100/assabet.h Sat Jan 5 14:43:18 2002 @@ -29,19 +29,6 @@ #define ASSABET_BCR_BASE 0xf1000000 #define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE)) -#define ASSABET_BCR_DB1110 \ - (ASSABET_BCR_SPK_OFF | ASSABET_BCR_QMUTE | \ - ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \ - ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \ - ASSABET_BCR_IRDA_MD0) - -#define ASSABET_BCR_DB1111 \ - (ASSABET_BCR_SPK_OFF | ASSABET_BCR_QMUTE | \ - ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \ - ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \ - ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \ - ASSABET_BCR_IRDA_MD0 | ASSABET_BCR_CF_RST) - #define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */ #define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */ #define ASSABET_BCR_GFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */ @@ -69,9 +56,15 @@ #define ASSABET_BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */ extern unsigned long SCR_value; -extern unsigned long BCR_value; -#define ASSABET_BCR_set(x) ASSABET_BCR = (BCR_value |= (x)) -#define ASSABET_BCR_clear(x) ASSABET_BCR = (BCR_value &= ~(x)) + +#ifdef CONFIG_SA1100_ASSABET +extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set); +#else +#define ASSABET_BCR_frob(x) do { } while (0) +#endif + +#define ASSABET_BCR_set(x) ASSABET_BCR_frob((x), (x)) +#define ASSABET_BCR_clear(x) ASSABET_BCR_frob((x), 0) #define ASSABET_BSR_BASE 0xf1000000 #define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE)) @@ -88,37 +81,25 @@ /* GPIOs for which the generic definition doesn't say much */ #define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */ -#define ASSABET_GPIO_L3_I2C_SDA GPIO_GPIO (15) /* L3 and SMB control ports */ #define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */ -#define ASSABET_GPIO_L3_MODE GPIO_GPIO (17) /* L3 mode signal with LED */ -#define ASSABET_GPIO_L3_I2C_SCL GPIO_GPIO (18) /* L3 and I2C control ports */ #define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */ #define ASSABET_GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */ #define ASSABET_GPIO_CF_CD GPIO_GPIO (22) /* CF CD */ -#define ASSABET_GPIO_UCB1300_IRQ GPIO_GPIO (23) /* UCB GPIO and touchscreen */ #define ASSABET_GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */ #define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */ #define ASSABET_GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */ -#define ASSABET_GPIO_NEP_IRQ GPIO_GPIO (25) /* Neponset IRQ */ #define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */ #define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */ #define ASSABET_IRQ_GPIO_CF_IRQ IRQ_GPIO21 #define ASSABET_IRQ_GPIO_CF_CD IRQ_GPIO22 -#define ASSABET_IRQ_GPIO_UCB1300_IRQ IRQ_GPIO23 #define ASSABET_IRQ_GPIO_CF_BVD2 IRQ_GPIO24 #define ASSABET_IRQ_GPIO_CF_BVD1 IRQ_GPIO25 -#define ASSABET_IRQ_GPIO_NEP_IRQ IRQ_GPIO25 /* * Neponset definitions: */ - -#define SA1111_BASE (0x40000000) - -#define NEPONSET_ETHERNET_IRQ MISC_IRQ0 -#define NEPONSET_USAR_IRQ MISC_IRQ1 #define NEPONSET_CPLD_BASE (0x10000000) #define Nep_p2v( x ) ((x) - NEPONSET_CPLD_BASE + 0xf3000000) diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/dma.h linux/include/asm-arm/arch-sa1100/dma.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/dma.h Thu Oct 11 09:04:57 2001 +++ linux/include/asm-arm/arch-sa1100/dma.h Sat Jan 5 14:43:18 2002 @@ -28,34 +28,16 @@ */ #define MAX_DMA_CHANNELS 0 - /* * The SA1100 has six internal DMA channels. */ -#define SA1100_DMA_CHANNELS 6 - - -/* - * The SA-1111 SAC has two DMA channels. - */ -#define SA1111_SAC_DMA_CHANNELS 2 -#define SA1111_SAC_XMT_CHANNEL 0 -#define SA1111_SAC_RCV_CHANNEL 1 - +#define SA1100_DMA_CHANNELS 6 /* - * The SA-1111 SAC channels will reside in the same index space as - * the built-in SA-1100 channels, and will take on the next available - * identifiers after the 1100. + * Maximum physical DMA buffer size */ -#define SA1111_SAC_DMA_BASE SA1100_DMA_CHANNELS - -#ifdef CONFIG_SA1111 -# define MAX_SA1100_DMA_CHANNELS (SA1100_DMA_CHANNELS + SA1111_SAC_DMA_CHANNELS) -#else -# define MAX_SA1100_DMA_CHANNELS SA1100_DMA_CHANNELS -#endif - +#define MAX_DMA_SIZE 0x1fff +#define CUT_DMA_SIZE 0x1000 /* * All possible SA1100 devices a DMA channel can be attached to. @@ -81,29 +63,72 @@ DMA_Ser4SSPRd = DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ } dma_device_t; +typedef struct { + volatile u_long DDAR; + volatile u_long SetDCSR; + volatile u_long ClrDCSR; + volatile u_long RdDCSR; + volatile dma_addr_t DBSA; + volatile u_long DBTA; + volatile dma_addr_t DBSB; + volatile u_long DBTB; +} dma_regs_t; + +typedef void (*dma_callback_t)(void *data); + +/* + * DMA function prototypes + */ -typedef void (*dma_callback_t)( void *buf_id, int size ); +extern int sa1100_request_dma( dma_device_t device, const char *device_id, + dma_callback_t callback, void *data, + dma_regs_t **regs ); +extern void sa1100_free_dma( dma_regs_t *regs ); +extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size ); +extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs); +extern void sa1100_reset_dma(dma_regs_t *regs); + +/** + * sa1100_stop_dma - stop DMA in progress + * @regs: identifier for the channel to use + * + * This stops DMA without clearing buffer pointers. Unlike + * sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma() + * or sa1100_get_dma_pos(). + * + * The @regs identifier is provided by a successful call to + * sa1100_request_dma(). + **/ + +#define sa1100_stop_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN) + +/** + * sa1100_resume_dma - resume DMA on a stopped channel + * @regs: identifier for the channel to use + * + * This resumes DMA on a channel previously stopped with + * sa1100_stop_dma(). + * + * The @regs identifier is provided by a successful call to + * sa1100_request_dma(). + **/ + +#define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN) + +/** + * sa1100_clear_dma - clear DMA pointers + * @regs: identifier for the channel to use + * + * This clear any DMA state so the DMA engine is ready to restart + * with new buffers through sa1100_start_dma(). Any buffers in flight + * are discarded. + * + * The @regs identifier is provided by a successful call to + * sa1100_request_dma(). + **/ +#define sa1100_clear_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB) -/* SA1100 DMA API */ -extern int sa1100_request_dma( dmach_t *channel, const char *device_id, - dma_device_t device ); -extern int sa1100_dma_set_callback( dmach_t channel, dma_callback_t cb ); -extern int sa1100_dma_set_spin( dmach_t channel, dma_addr_t addr, int size ); -extern int sa1100_dma_queue_buffer( dmach_t channel, void *buf_id, - dma_addr_t data, int size ); -extern int sa1100_dma_get_current( dmach_t channel, void **buf_id, dma_addr_t *addr ); -extern int sa1100_dma_stop( dmach_t channel ); -extern int sa1100_dma_resume( dmach_t channel ); -extern int sa1100_dma_flush_all( dmach_t channel ); -extern void sa1100_free_dma( dmach_t channel ); -extern int sa1100_dma_sleep( dmach_t channel ); -extern int sa1100_dma_wakeup( dmach_t channel ); - -/* Sa1111 DMA interface (all but registration uses the above) */ -extern int sa1111_sac_request_dma( dmach_t *channel, const char *device_id, - unsigned int direction ); -extern int sa1111_check_dma_bug( dma_addr_t addr ); #ifdef CONFIG_SA1111 static inline void diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/flexanet.h linux/include/asm-arm/arch-sa1100/flexanet.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/flexanet.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-sa1100/flexanet.h Sat Jan 5 14:43:18 2002 @@ -1,5 +1,5 @@ /* - * linux/include/asm-arm/arch-sa1100/flexanet.h + * include/asm-arm/arch-sa1100/flexanet.h * * Created 2001/05/04 by Jordi Colomer * @@ -11,39 +11,79 @@ #error "include instead" #endif - /* Board Control Register (virtual address) */ -#define BCR_PHYS 0x10000000 -#define BCR_VIRT 0xf0000000 -#define BCR (*(volatile unsigned int *)(BCR_VIRT)) +#define FHH_BCR_PHYS 0x10000000 +#define FHH_BCR_VIRT 0xf0000000 +#define FHH_BCR (*(volatile unsigned int *)(FHH_BCR_VIRT)) /* Power-up value */ -#define BCR_POWERUP 0x00000000 +#define FHH_BCR_POWERUP 0x00000000 /* Mandatory bits */ -#define BCR_LED_GREEN (1<<0) /* General-purpose green LED (1 = on) */ -#define BCR_GUI_NRST (1<<4) /* GUI board reset (0 = reset) */ - -/* Board Status Register (virtual address) */ -#define BSR_BASE BCR_BASE -#define BSR (*(volatile unsigned int *)(BSR_BASE)) - +#define FHH_BCR_LED_GREEN (1<<0) /* General-purpose green LED (1 = on) */ +#define FHH_BCR_SPARE_1 (1<<1) /* Not defined */ +#define FHH_BCR_CF1_RST (1<<2) /* Compact Flash Slot #1 Reset (1 = reset) */ +#define FHH_BCR_CF2_RST (1<<3) /* Compact Flash Slot #2 Reset (1 = reset) */ +#define FHH_BCR_GUI_NRST (1<<4) /* GUI board reset (0 = reset) */ +#define FHH_BCR_RTS1 (1<<5) /* RS232 RTS for UART-1 */ +#define FHH_BCR_RTS3 (1<<6) /* RS232 RTS for UART-3 */ +#define FHH_BCR_XCDBG0 (1<<7) /* Not defined. Wired to XPLA3 for debug */ + +/* BCR extension, only required by L3-bus in some audio codecs */ +#define FHH_BCR_L3MOD (1<<8) /* L3-bus MODE signal */ +#define FHH_BCR_L3DAT (1<<9) /* L3-bus DATA signal */ +#define FHH_BCR_L3CLK (1<<10) /* L3-bus CLK signal */ +#define FHH_BCR_SPARE_11 (1<<11) /* Not defined */ +#define FHH_BCR_SPARE_12 (1<<12) /* Not defined */ +#define FHH_BCR_SPARE_13 (1<<13) /* Not defined */ +#define FHH_BCR_SPARE_14 (1<<14) /* Not defined */ +#define FHH_BCR_SPARE_15 (1<<15) /* Not defined */ + + /* Board Status Register (virtual address) */ +#define FHH_BSR_BASE FHH_BCR_VIRT +#define FHH_BSR (*(volatile unsigned int *)(FHH_BSR_BASE)) + +#define FHH_BSR_CTS1 (1<<0) /* RS232 CTS for UART-1 */ +#define FHH_BSR_CTS3 (1<<1) /* RS232 CTS for UART-3 */ +#define FHH_BSR_DSR1 (1<<2) /* RS232 DSR for UART-1 */ +#define FHH_BSR_DSR3 (1<<3) /* RS232 DSR for UART-3 */ +#define FHH_BSR_ID0 (1<<4) /* Board identification */ +#define FHH_BSR_ID1 (1<<5) +#define FHH_BSR_CFG0 (1<<6) /* Board configuration options */ +#define FHH_BSR_CFG1 (1<<7) #ifndef __ASSEMBLY__ -extern unsigned long BCR_value; /* Image of the BCR */ -#define BCR_set( x ) BCR = (BCR_value |= (x)) -#define BCR_clear( x ) BCR = (BCR_value &= ~(x)) +extern unsigned long flexanet_BCR; /* Image of the BCR */ +#define FLEXANET_BCR_set( x ) FHH_BCR = (flexanet_BCR |= (x)) +#define FLEXANET_BCR_clear( x ) FHH_BCR = (flexanet_BCR &= ~(x)) #endif - /* GPIOs for which the generic definition doesn't say much */ -#define GPIO_GUI_IRQ GPIO_GPIO (23) /* IRQ from GUI board (i.e., UCB1300) */ -#define GPIO_ETH_IRQ GPIO_GPIO (24) /* IRQ from Ethernet controller */ -#define GPIO_LED_RED GPIO_GPIO (26) /* General-purpose red LED */ +#define GPIO_CF1_NCD GPIO_GPIO (14) /* Card Detect from CF slot #1 */ +#define GPIO_CF2_NCD GPIO_GPIO (15) /* Card Detect from CF slot #2 */ +#define GPIO_CF1_IRQ GPIO_GPIO (16) /* IRQ from CF slot #1 */ +#define GPIO_CF2_IRQ GPIO_GPIO (17) /* IRQ from CF slot #2 */ +#define GPIO_APP_IRQ GPIO_GPIO (18) /* Extra IRQ from application bus */ +#define GPIO_RADIO_REF GPIO_GPIO (20) /* Ref. clock for UART3 (Radio) */ +#define GPIO_CF1_BVD1 GPIO_GPIO (21) /* BVD1 from CF slot #1 */ +#define GPIO_CF2_BVD1 GPIO_GPIO (22) /* BVD1 from CF slot #2 */ +#define GPIO_GUI_IRQ GPIO_GPIO (23) /* IRQ from GUI board (i.e., UCB1300) */ +#define GPIO_ETH_IRQ GPIO_GPIO (24) /* IRQ from Ethernet controller */ +#define GPIO_INTIP_IRQ GPIO_GPIO (25) /* Measurement IRQ (INTIP) */ +#define GPIO_LED_RED GPIO_GPIO (26) /* General-purpose red LED */ /* IRQ sources from GPIOs */ -#define IRQ_GPIO_GUI IRQ_GPIO23 -#define IRQ_GPIO_ETH IRQ_GPIO24 +#define IRQ_GPIO_CF1_CD IRQ_GPIO14 +#define IRQ_GPIO_CF2_CD IRQ_GPIO15 +#define IRQ_GPIO_CF1_IRQ IRQ_GPIO16 +#define IRQ_GPIO_CF2_IRQ IRQ_GPIO17 +#define IRQ_GPIO_APP IRQ_GPIO18 +#define IRQ_GPIO_CF1_BVD1 IRQ_GPIO21 +#define IRQ_GPIO_CF2_BVD1 IRQ_GPIO22 +#define IRQ_GPIO_GUI IRQ_GPIO23 +#define IRQ_GPIO_ETH IRQ_GPIO24 +#define IRQ_GPIO_INTIP IRQ_GPIO25 + /* On-Board Ethernet */ #define _FHH_ETH_IOBASE 0x18000000 /* I/O base (physical addr) */ @@ -57,15 +97,4 @@ #define FHH_ETH_IOBASE FHH_ETH_p2v(_FHH_ETH_IOBASE) /* Virtual base addr */ #define FHH_ETH_MMBASE FHH_ETH_p2v(_FHH_ETH_MMBASE) - -/* Types of GUI */ -#ifndef __ASSEMBLY__ -extern unsigned long GUI_type; -#endif - -#define FHH_GUI_ERROR 0xFFFFFFFF -#define FHH_GUI_NONE 0x0000000F -#define FHH_GUI_TYPE_0 0 -#define FHH_GUI_TYPE_1 1 -#define FHH_GUI_TYPE_2 2 diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/graphicsmaster.h linux/include/asm-arm/arch-sa1100/graphicsmaster.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/graphicsmaster.h Thu Oct 11 09:04:57 2001 +++ linux/include/asm-arm/arch-sa1100/graphicsmaster.h Sat Jan 5 14:43:18 2002 @@ -62,5 +62,3 @@ #endif #define SA1111_BASE (0x18000000) - -#include "SA-1111.h" diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/h3600.h linux/include/asm-arm/arch-sa1100/h3600.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/h3600.h Thu Oct 11 09:04:57 2001 +++ linux/include/asm-arm/arch-sa1100/h3600.h Sat Jan 5 14:43:18 2002 @@ -1,81 +1,138 @@ /* -* -* Definitions for H3600 Handheld Computer -* -* Copyright 2000 Compaq Computer Corporation. -* -* Use consistent with the GNU GPL is permitted, -* provided that this copyright notice is -* preserved in its entirety in all copies and derived works. -* -* COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, -* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS -* FITNESS FOR ANY PARTICULAR PURPOSE. -* -* Author: Jamey Hicks. -* -*/ + * + * Definitions for H3600 Handheld Computer + * + * Copyright 2000 Compaq Computer Corporation. + * + * Use consistent with the GNU GPL is permitted, + * provided that this copyright notice is + * preserved in its entirety in all copies and derived works. + * + * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, + * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS + * FITNESS FOR ANY PARTICULAR PURPOSE. + * + * Author: Jamey Hicks. + * + * History: + * + * 2001-10-?? Andrew Christian Added support for iPAQ H3800 + * + */ #ifndef _INCLUDE_H3600_H_ #define _INCLUDE_H3600_H_ -#define GPIO_H3600_NPOWER_BUTTON GPIO_GPIO (0) -#define GPIO_H3600_ACTION_BUTTON GPIO_GPIO (18) +/* generalized support for H3xxx series Compaq Pocket PC's */ +#define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800()) + +/* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */ +#define H3600_EGPIO_VIRT 0xf0000000 +#define H3600_BANK_2_VIRT 0xf1000000 +#define H3600_BANK_4_VIRT 0xf3800000 + +/* + Machine-independent GPIO definitions + --- these are common across all current iPAQ platforms +*/ + +#define GPIO_H3600_NPOWER_BUTTON GPIO_GPIO (0) /* Also known as the "off button" */ +#define GPIO_H3600_MICROCONTROLLER GPIO_GPIO (1) /* From ASIC2 on H3800 */ -#define GPIO_H3600_PCMCIA_CD0 GPIO_GPIO (17) #define GPIO_H3600_PCMCIA_CD1 GPIO_GPIO (10) -#define GPIO_H3600_PCMCIA_IRQ0 GPIO_GPIO (21) #define GPIO_H3600_PCMCIA_IRQ1 GPIO_GPIO (11) -/* audio sample rate clock generator */ -#define GPIO_H3600_CLK_SET0 GPIO_GPIO (12) -#define GPIO_H3600_CLK_SET1 GPIO_GPIO (13) - /* UDA1341 L3 Interface */ #define GPIO_H3600_L3_DATA GPIO_GPIO (14) -#define GPIO_H3600_L3_CLOCK GPIO_GPIO (16) #define GPIO_H3600_L3_MODE GPIO_GPIO (15) +#define GPIO_H3600_L3_CLOCK GPIO_GPIO (16) -#define GPIO_H3600_OPT_LOCK GPIO_GPIO (22) -#define GPIO_H3600_OPT_IRQ GPIO_GPIO (24) -#define GPIO_H3600_OPT_DET GPIO_GPIO (27) +#define GPIO_H3600_PCMCIA_CD0 GPIO_GPIO (17) +#define GPIO_H3600_SYS_CLK GPIO_GPIO (19) +#define GPIO_H3600_PCMCIA_IRQ0 GPIO_GPIO (21) #define GPIO_H3600_COM_DCD GPIO_GPIO (23) +#define GPIO_H3600_OPT_IRQ GPIO_GPIO (24) #define GPIO_H3600_COM_CTS GPIO_GPIO (25) #define GPIO_H3600_COM_RTS GPIO_GPIO (26) #define IRQ_GPIO_H3600_NPOWER_BUTTON IRQ_GPIO0 -#define IRQ_GPIO_H3600_ACTION_BUTTON IRQ_GPIO18 -#define IRQ_GPIO_H3600_PCMCIA_CD0 IRQ_GPIO17 +#define IRQ_GPIO_H3600_MICROCONTROLLER IRQ_GPIO1 #define IRQ_GPIO_H3600_PCMCIA_CD1 IRQ_GPIO10 -#define IRQ_GPIO_H3600_PCMCIA_IRQ0 IRQ_GPIO21 #define IRQ_GPIO_H3600_PCMCIA_IRQ1 IRQ_GPIO11 -#define IRQ_GPIO_H3600_OPT_IRQ IRQ_GPIO24 -#define IRQ_GPIO_H3600_OPT_DET IRQ_GPIO27 +#define IRQ_GPIO_H3600_PCMCIA_CD0 IRQ_GPIO17 +#define IRQ_GPIO_H3600_PCMCIA_IRQ0 IRQ_GPIO21 #define IRQ_GPIO_H3600_COM_DCD IRQ_GPIO23 +#define IRQ_GPIO_H3600_OPT_IRQ IRQ_GPIO24 #define IRQ_GPIO_H3600_COM_CTS IRQ_GPIO25 -#define EGPIO_H3600_VPP_ON (1 << 0) -#define EGPIO_H3600_CARD_RESET (1 << 1) /* reset the attached pcmcia/compactflash card. active high. */ -#define EGPIO_H3600_OPT_RESET (1 << 2) /* reset the attached option pack. active high. */ -#define EGPIO_H3600_CODEC_NRESET (1 << 3) /* reset the onboard UDA1341. active low. */ -#define EGPIO_H3600_OPT_NVRAM_ON (1 << 4) /* apply power to optionpack nvram, active high. */ -#define EGPIO_H3600_OPT_ON (1 << 5) /* full power to option pack. active high. */ -#define EGPIO_H3600_LCD_ON (1 << 6) /* enable 3.3V to LCD. active high. */ -#define EGPIO_H3600_RS232_ON (1 << 7) /* UART3 transceiver force on. Active high. */ -#define EGPIO_H3600_LCD_PCI (1 << 8) /* LCD control IC enable. active high. */ -#define EGPIO_H3600_IR_ON (1 << 9) /* apply power to IR module. active high. */ -#define EGPIO_H3600_AUD_AMP_ON (1 << 10) /* apply power to audio power amp. active high. */ -#define EGPIO_H3600_AUD_PWR_ON (1 << 11) /* apply poewr to reset of audio circuit. active high. */ -#define EGPIO_H3600_QMUTE (1 << 12) /* mute control for onboard UDA1341. active high. */ -#define EGPIO_H3600_IR_FSEL (1 << 13) /* IR speed select: 1->fast, 0->slow */ -#define EGPIO_H3600_LCD_5V_ON (1 << 14) /* enable 5V to LCD. active high. */ -#define EGPIO_H3600_LVDD_ON (1 << 15) /* enable 9V and -6.5V to LCD. */ #ifndef __ASSEMBLY__ -#define H3600_EGPIO (*(volatile int *)0xf0000000) -extern void clr_h3600_egpio(unsigned long x); -extern void set_h3600_egpio(unsigned long x); -#endif +enum ipaq_model { + IPAQ_H3100, + IPAQ_H3600, + IPAQ_H3800 +}; + +enum ipaq_egpio_type { + IPAQ_EGPIO_LCD_ON, /* Power to the LCD panel */ + IPAQ_EGPIO_CODEC_NRESET, /* Clear to reset the audio codec (remember to return high) */ + IPAQ_EGPIO_AUDIO_ON, /* Audio power */ + IPAQ_EGPIO_QMUTE, /* Audio muting */ + IPAQ_EGPIO_OPT_NVRAM_ON, /* Non-volatile RAM on extension sleeves (SPI interface) */ + IPAQ_EGPIO_OPT_ON, /* Power to extension sleeves */ + IPAQ_EGPIO_CARD_RESET, /* Reset PCMCIA cards on extension sleeve (???) */ + IPAQ_EGPIO_OPT_RESET, /* Reset option pack (???) */ + IPAQ_EGPIO_IR_ON, /* IR sensor/emitter power */ + IPAQ_EGPIO_IR_FSEL, /* IR speed selection 1->fast, 0->slow */ + IPAQ_EGPIO_RS232_ON, /* Maxim RS232 chip power */ + IPAQ_EGPIO_VPP_ON, /* Turn on power to flash programming */ +}; + +struct ipaq_model_ops { + enum ipaq_model model; + const char *generic_name; + void (*initialize)(void); + void (*control)(enum ipaq_egpio_type, int); + unsigned long (*read)(void); +}; + +extern struct ipaq_model_ops ipaq_model_ops; + +static __inline__ enum ipaq_model h3600_model( void ) { + return ipaq_model_ops.model; +} + +static __inline__ const char * h3600_generic_name( void ) { + return ipaq_model_ops.generic_name; +} + +static __inline__ void init_h3600_egpio( void ) { + if (ipaq_model_ops.initialize) + ipaq_model_ops.initialize(); +} + +static __inline__ void assign_h3600_egpio( enum ipaq_egpio_type x, int level ) { + if (ipaq_model_ops.control) + ipaq_model_ops.control(x,level); +} + +static __inline__ void clr_h3600_egpio( enum ipaq_egpio_type x ) { + if (ipaq_model_ops.control) + ipaq_model_ops.control(x,0); +} + +static __inline__ void set_h3600_egpio( enum ipaq_egpio_type x ) { + if (ipaq_model_ops.control) + ipaq_model_ops.control(x,1); +} + +static __inline__ unsigned long read_h3600_egpio( void ) { + if (ipaq_model_ops.read) + return ipaq_model_ops.read(); + return 0; +} + +#endif /* ASSEMBLY */ -#endif +#endif /* _INCLUDE_H3600_H_ */ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/h3600_gpio.h linux/include/asm-arm/arch-sa1100/h3600_gpio.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/h3600_gpio.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-sa1100/h3600_gpio.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,540 @@ +/* + * + * Definitions for H3600 Handheld Computer + * + * Copyright 2000 Compaq Computer Corporation. + * + * Use consistent with the GNU GPL is permitted, + * provided that this copyright notice is + * preserved in its entirety in all copies and derived works. + * + * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, + * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS + * FITNESS FOR ANY PARTICULAR PURPOSE. + * + * Author: Jamey Hicks. + * + * History: + * + * 2001-10-?? Andrew Christian Added support for iPAQ H3800 + * + */ + +#ifndef _INCLUDE_H3600_GPIO_H_ +#define _INCLUDE_H3600_GPIO_H_ + +/* + * GPIO lines that are common across ALL iPAQ models are in "h3600.h" + * This file contains machine-specific definitions + */ + +#define GPIO_H3600_SUSPEND GPIO_GPIO (0) +/* GPIO[2:9] used by LCD on H3600/3800, used as GPIO on H3100 */ +#define GPIO_H3100_BT_ON GPIO_GPIO (2) +#define GPIO_H3100_GPIO3 GPIO_GPIO (3) +#define GPIO_H3100_QMUTE GPIO_GPIO (4) +#define GPIO_H3100_LCD_3V_ON GPIO_GPIO (5) +#define GPIO_H3100_AUD_ON GPIO_GPIO (6) +#define GPIO_H3100_AUD_PWR_ON GPIO_GPIO (7) +#define GPIO_H3100_IR_ON GPIO_GPIO (8) +#define GPIO_H3100_IR_FSEL GPIO_GPIO (9) + +/* for H3600, audio sample rate clock generator */ +#define GPIO_H3600_CLK_SET0 GPIO_GPIO (12) +#define GPIO_H3600_CLK_SET1 GPIO_GPIO (13) + +#define GPIO_H3600_ACTION_BUTTON GPIO_GPIO (18) +#define GPIO_H3600_SOFT_RESET GPIO_GPIO (20) /* Also known as BATT_FAULT */ +#define GPIO_H3600_OPT_LOCK GPIO_GPIO (22) +#define GPIO_H3600_OPT_DET GPIO_GPIO (27) + +/* H3800 specific pins */ +#define GPIO_H3800_AC_IN GPIO_GPIO (12) +#define GPIO_H3800_COM_DSR GPIO_GPIO (13) +#define GPIO_H3800_MMC_INT GPIO_GPIO (18) +#define GPIO_H3800_NOPT_IND GPIO_GPIO (20) /* Almost exactly the same as GPIO_H3600_OPT_DET */ +#define GPIO_H3800_OPT_BAT_FAULT GPIO_GPIO (22) +#define GPIO_H3800_CLK_OUT GPIO_GPIO (27) + +/****************************************************/ + +#define IRQ_GPIO_H3600_ACTION_BUTTON IRQ_GPIO18 +#define IRQ_GPIO_H3600_OPT_DET IRQ_GPIO27 + +#define IRQ_GPIO_H3800_MMC_INT IRQ_GPIO18 +#define IRQ_GPIO_H3800_NOPT_IND IRQ_GPIO20 /* almost same as OPT_DET */ + +/* H3100 / 3600 EGPIO pins */ +#define EGPIO_H3600_VPP_ON (1 << 0) +#define EGPIO_H3600_CARD_RESET (1 << 1) /* reset the attached pcmcia/compactflash card. active high. */ +#define EGPIO_H3600_OPT_RESET (1 << 2) /* reset the attached option pack. active high. */ +#define EGPIO_H3600_CODEC_NRESET (1 << 3) /* reset the onboard UDA1341. active low. */ +#define EGPIO_H3600_OPT_NVRAM_ON (1 << 4) /* apply power to optionpack nvram, active high. */ +#define EGPIO_H3600_OPT_ON (1 << 5) /* full power to option pack. active high. */ +#define EGPIO_H3600_LCD_ON (1 << 6) /* enable 3.3V to LCD. active high. */ +#define EGPIO_H3600_RS232_ON (1 << 7) /* UART3 transceiver force on. Active high. */ + +/* H3600 only EGPIO pins */ +#define EGPIO_H3600_LCD_PCI (1 << 8) /* LCD control IC enable. active high. */ +#define EGPIO_H3600_IR_ON (1 << 9) /* apply power to IR module. active high. */ +#define EGPIO_H3600_AUD_AMP_ON (1 << 10) /* apply power to audio power amp. active high. */ +#define EGPIO_H3600_AUD_PWR_ON (1 << 11) /* apply power to reset of audio circuit. active high. */ +#define EGPIO_H3600_QMUTE (1 << 12) /* mute control for onboard UDA1341. active high. */ +#define EGPIO_H3600_IR_FSEL (1 << 13) /* IR speed select: 1->fast, 0->slow */ +#define EGPIO_H3600_LCD_5V_ON (1 << 14) /* enable 5V to LCD. active high. */ +#define EGPIO_H3600_LVDD_ON (1 << 15) /* enable 9V and -6.5V to LCD. */ + +/********************* H3800, ASIC #2 ********************/ + +#define _H3800_ASIC2_Base (H3600_EGPIO_VIRT) +#define H3800_ASIC2_OFFSET(s,x,y) \ + (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _Base + _H3800_ASIC2_ ## x ## _ ## y))) +#define H3800_ASIC2_NOFFSET(s,x,n,y) \ + (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _ ## n ## _Base + _H3800_ASIC2_ ## x ## _ ## y))) + +#define _H3800_ASIC2_GPIO_Base 0x0000 +#define _H3800_ASIC2_GPIO_Direction 0x0000 /* R/W, 16 bits 1:input, 0:output */ +#define _H3800_ASIC2_GPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */ +#define _H3800_ASIC2_GPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */ +#define _H3800_ASIC2_GPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */ +#define _H3800_ASIC2_GPIO_InterruptClear 0x0010 /* W, 12 bits */ +#define _H3800_ASIC2_GPIO_InterruptFlag 0x0010 /* R, 12 bits - reads int status */ +#define _H3800_ASIC2_GPIO_Data 0x0014 /* R/W, 16 bits */ +#define _H3800_ASIC2_GPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */ +#define _H3800_ASIC2_GPIO_InterruptEnable 0x001c /* R/W, 12 bits 1:enable interrupt */ +#define _H3800_ASIC2_GPIO_Alternate 0x003c /* R/W, 12+1 bits - set alternate functions */ + +#define H3800_ASIC2_GPIO_Direction H3800_ASIC2_OFFSET( u16, GPIO, Direction ) +#define H3800_ASIC2_GPIO_InterruptType H3800_ASIC2_OFFSET( u16, GPIO, InterruptType ) +#define H3800_ASIC2_GPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType ) +#define H3800_ASIC2_GPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType ) +#define H3800_ASIC2_GPIO_InterruptClear H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear ) +#define H3800_ASIC2_GPIO_InterruptFlag H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag ) +#define H3800_ASIC2_GPIO_Data H3800_ASIC2_OFFSET( u16, GPIO, Data ) +#define H3800_ASIC2_GPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut ) +#define H3800_ASIC2_GPIO_InterruptEnable H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable ) +#define H3800_ASIC2_GPIO_Alternate H3800_ASIC2_OFFSET( u16, GPIO, Alternate ) + +#define GPIO_H3800_ASIC2_IN_Y1_N (1 << 0) /* Output: Touchscreen Y1 */ +#define GPIO_H3800_ASIC2_IN_X0 (1 << 1) /* Output: Touchscreen X0 */ +#define GPIO_H3800_ASIC2_IN_Y0 (1 << 2) /* Output: Touchscreen Y0 */ +#define GPIO_H3800_ASIC2_IN_X1_N (1 << 3) /* Output: Touchscreen X1 */ +#define GPIO_H3800_ASIC2_BT_RST (1 << 4) /* Output: Bluetooth reset */ +#define GPIO_H3800_ASIC2_PEN_IRQ (1 << 5) /* Input : Pen down */ +#define GPIO_H3800_ASIC2_SD_DETECT (1 << 6) /* Input : SD detect */ +#define GPIO_H3800_ASIC2_EAR_IN_N (1 << 7) /* Input : Audio jack plug inserted */ +#define GPIO_H3800_ASIC2_OPT_PCM_RESET (1 << 8) /* Output: */ +#define GPIO_H3800_ASIC2_OPT_RESET (1 << 9) /* Output: */ +#define GPIO_H3800_ASIC2_USB_DETECT_N (1 << 10) /* Input : */ +#define GPIO_H3800_ASIC2_SD_CON_SLT (1 << 11) /* Input : */ + +#define _H3800_ASIC2_KPIO_Base 0x0200 +#define _H3800_ASIC2_KPIO_Direction 0x0000 /* R/W, 12 bits 1:input, 0:output */ +#define _H3800_ASIC2_KPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */ +#define _H3800_ASIC2_KPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */ +#define _H3800_ASIC2_KPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */ +#define _H3800_ASIC2_KPIO_InterruptClear 0x0010 /* W, 20 bits - 8 special */ +#define _H3800_ASIC2_KPIO_InterruptFlag 0x0010 /* R, 20 bits - 8 special - reads int status */ +#define _H3800_ASIC2_KPIO_Data 0x0014 /* R/W, 16 bits */ +#define _H3800_ASIC2_KPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */ +#define _H3800_ASIC2_KPIO_InterruptEnable 0x001c /* R/W, 20 bits - 8 special */ +#define _H3800_ASIC2_KPIO_Alternate 0x003c /* R/W, 6 bits */ + +#define H3800_ASIC2_KPIO_Direction H3800_ASIC2_OFFSET( u16, KPIO, Direction ) +#define H3800_ASIC2_KPIO_InterruptType H3800_ASIC2_OFFSET( u16, KPIO, InterruptType ) +#define H3800_ASIC2_KPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, KPIO, InterruptEdgeType ) +#define H3800_ASIC2_KPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, KPIO, InterruptLevelType ) +#define H3800_ASIC2_KPIO_InterruptClear H3800_ASIC2_OFFSET( u32, KPIO, InterruptClear ) +#define H3800_ASIC2_KPIO_InterruptFlag H3800_ASIC2_OFFSET( u32, KPIO, InterruptFlag ) +#define H3800_ASIC2_KPIO_Data H3800_ASIC2_OFFSET( u16, KPIO, Data ) +#define H3800_ASIC2_KPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, KPIO, BattFaultOut ) +#define H3800_ASIC2_KPIO_InterruptEnable H3800_ASIC2_OFFSET( u32, KPIO, InterruptEnable ) +#define H3800_ASIC2_KPIO_Alternate H3800_ASIC2_OFFSET( u16, KPIO, Alternate ) + +#define H3800_ASIC2_KPIO_SPI_INT ( 1 << 16 ) +#define H3800_ASIC2_KPIO_OWM_INT ( 1 << 17 ) +#define H3800_ASIC2_KPIO_ADC_INT ( 1 << 18 ) +#define H3800_ASIC2_KPIO_UART_0_INT ( 1 << 19 ) +#define H3800_ASIC2_KPIO_UART_1_INT ( 1 << 20 ) +#define H3800_ASIC2_KPIO_TIMER_0_INT ( 1 << 21 ) +#define H3800_ASIC2_KPIO_TIMER_1_INT ( 1 << 22 ) +#define H3800_ASIC2_KPIO_TIMER_2_INT ( 1 << 23 ) + +#define KPIO_H3800_ASIC2_RECORD_BTN_N (1 << 0) /* Record button */ +#define KPIO_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Keypad */ +#define KPIO_H3800_ASIC2_KEY_5W2_N (1 << 2) /* */ +#define KPIO_H3800_ASIC2_KEY_5W3_N (1 << 3) /* */ +#define KPIO_H3800_ASIC2_KEY_5W4_N (1 << 4) /* */ +#define KPIO_H3800_ASIC2_KEY_5W5_N (1 << 5) /* */ +#define KPIO_H3800_ASIC2_KEY_LEFT_N (1 << 6) /* */ +#define KPIO_H3800_ASIC2_KEY_RIGHT_N (1 << 7) /* */ +#define KPIO_H3800_ASIC2_KEY_AP1_N (1 << 8) /* Old "Calendar" */ +#define KPIO_H3800_ASIC2_KEY_AP2_N (1 << 9) /* Old "Schedule" */ +#define KPIO_H3800_ASIC2_KEY_AP3_N (1 << 10) /* Old "Q" */ +#define KPIO_H3800_ASIC2_KEY_AP4_N (1 << 11) /* Old "Undo" */ + +/* Alternate KPIO functions (set by default) */ +#define KPIO_ALT_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Action key */ +#define KPIO_ALT_H3800_ASIC2_KEY_5W2_N (1 << 2) /* J1 of keypad input */ +#define KPIO_ALT_H3800_ASIC2_KEY_5W3_N (1 << 3) /* J2 of keypad input */ +#define KPIO_ALT_H3800_ASIC2_KEY_5W4_N (1 << 4) /* J3 of keypad input */ +#define KPIO_ALT_H3800_ASIC2_KEY_5W5_N (1 << 5) /* J4 of keypad input */ + +#define _H3800_ASIC2_SPI_Base 0x0400 +#define _H3800_ASIC2_SPI_Control 0x0000 /* R/W 8 bits */ +#define _H3800_ASIC2_SPI_Data 0x0004 /* R/W 8 bits */ +#define _H3800_ASIC2_SPI_ChipSelectDisabled 0x0008 /* W 8 bits */ + +#define H3800_ASIC2_SPI_Control H3800_ASIC2_OFFSET( u8, SPI, Control ) +#define H3800_ASIC2_SPI_Data H3800_ASIC2_OFFSET( u8, SPI, Data ) +#define H3800_ASIC2_SPI_ChipSelectDisabled H3800_ASIC2_OFFSET( u8, SPI, ChipSelectDisabled ) + +#define _H3800_ASIC2_PWM_0_Base 0x0600 +#define _H3800_ASIC2_PWM_1_Base 0x0700 +#define _H3800_ASIC2_PWM_TimeBase 0x0000 /* R/W 6 bits */ +#define _H3800_ASIC2_PWM_PeriodTime 0x0004 /* R/W 12 bits */ +#define _H3800_ASIC2_PWM_DutyTime 0x0008 /* R/W 12 bits */ + +#define H3800_ASIC2_PWM_0_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 0, TimeBase ) +#define H3800_ASIC2_PWM_0_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 0, PeriodTime ) +#define H3800_ASIC2_PWM_0_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 0, DutyTime ) + +#define H3800_ASIC2_PWM_1_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 1, TimeBase ) +#define H3800_ASIC2_PWM_1_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 1, PeriodTime ) +#define H3800_ASIC2_PWM_1_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 1, DutyTime ) + +#define H3800_ASIC2_PWM_TIMEBASE_MASK 0xf /* Low 4 bits sets time base, max = 8 */ +#define H3800_ASIC2_PWM_TIMEBASE_ENABLE ( 1 << 4 ) /* Enable clock */ +#define H3800_ASIC2_PWM_TIMEBASE_CLEAR ( 1 << 5 ) /* Clear the PWM */ + +#define _H3800_ASIC2_LED_0_Base 0x0800 +#define _H3800_ASIC2_LED_1_Base 0x0880 +#define _H3800_ASIC2_LED_2_Base 0x0900 +#define _H3800_ASIC2_LED_TimeBase 0x0000 /* R/W 7 bits */ +#define _H3800_ASIC2_LED_PeriodTime 0x0004 /* R/W 12 bits */ +#define _H3800_ASIC2_LED_DutyTime 0x0008 /* R/W 12 bits */ +#define _H3800_ASIC2_LED_AutoStopCount 0x000c /* R/W 16 bits */ + +#define H3800_ASIC2_LED_0_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 0, TimeBase ) +#define H3800_ASIC2_LED_0_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 0, PeriodTime ) +#define H3800_ASIC2_LED_0_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 0, DutyTime ) +#define H3800_ASIC2_LED_0_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 0, AutoStopClock ) + +#define H3800_ASIC2_LED_1_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 1, TimeBase ) +#define H3800_ASIC2_LED_1_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 1, PeriodTime ) +#define H3800_ASIC2_LED_1_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 1, DutyTime ) +#define H3800_ASIC2_LED_1_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 1, AutoStopClock ) + +#define H3800_ASIC2_LED_2_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 2, TimeBase ) +#define H3800_ASIC2_LED_2_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 2, PeriodTime ) +#define H3800_ASIC2_LED_2_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 2, DutyTime ) +#define H3800_ASIC2_LED_2_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 2, AutoStopClock ) + +#define H3800_ASIC2_LED_TIMEBASE_MASK 0x0f /* Low 4 bits sets time base, max = 13 */ +#define H3800_ASIC2_LED_TIMEBASE_BLINK ( 1 << 4 ) /* Enable blinking */ +#define H3800_ASIC2_LED_TIMEBASE_AUTOSTOP ( 1 << 5 ) +#define H3800_ASIC2_LED_TIMEBASE_ALWAYS ( 1 << 6 ) /* Enable blink always */ + +#define _H3800_ASIC2_UART_0_Base 0x0A00 +#define _H3800_ASIC2_UART_1_Base 0x0C00 +#define _H3800_ASIC2_UART_Receive 0x0000 /* R 8 bits */ +#define _H3800_ASIC2_UART_Transmit 0x0000 /* W 8 bits */ +#define _H3800_ASIC2_UART_IntEnable 0x0004 /* R/W 8 bits */ +#define _H3800_ASIC2_UART_IntVerify 0x0008 /* R/W 8 bits */ +#define _H3800_ASIC2_UART_FIFOControl 0x000c /* R/W 8 bits */ +#define _H3800_ASIC2_UART_LineControl 0x0010 /* R/W 8 bits */ +#define _H3800_ASIC2_UART_ModemStatus 0x0014 /* R/W 8 bits */ +#define _H3800_ASIC2_UART_LineStatus 0x0018 /* R/W 8 bits */ +#define _H3800_ASIC2_UART_ScratchPad 0x001c /* R/W 8 bits */ +#define _H3800_ASIC2_UART_DivisorLatchL 0x0020 /* R/W 8 bits */ +#define _H3800_ASIC2_UART_DivisorLatchH 0x0024 /* R/W 8 bits */ + +#define H3800_ASIC2_UART_0_Receive H3800_ASIC2_NOFFSET( u8, UART, 0, Receive ) +#define H3800_ASIC2_UART_0_Transmit H3800_ASIC2_NOFFSET( u8, UART, 0, Transmit ) +#define H3800_ASIC2_UART_0_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 0, IntEnable ) +#define H3800_ASIC2_UART_0_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 0, IntVerify ) +#define H3800_ASIC2_UART_0_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 0, FIFOControl ) +#define H3800_ASIC2_UART_0_LineControl H3800_ASIC2_NOFFSET( u8, UART, 0, LineControl ) +#define H3800_ASIC2_UART_0_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 0, ModemStatus ) +#define H3800_ASIC2_UART_0_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 0, LineStatus ) +#define H3800_ASIC2_UART_0_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 0, ScratchPad ) +#define H3800_ASIC2_UART_0_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchL ) +#define H3800_ASIC2_UART_0_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchH ) + +#define H3800_ASIC2_UART_1_Receive H3800_ASIC2_NOFFSET( u8, UART, 1, Receive ) +#define H3800_ASIC2_UART_1_Transmit H3800_ASIC2_NOFFSET( u8, UART, 1, Transmit ) +#define H3800_ASIC2_UART_1_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 1, IntEnable ) +#define H3800_ASIC2_UART_1_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 1, IntVerify ) +#define H3800_ASIC2_UART_1_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 1, FIFOControl ) +#define H3800_ASIC2_UART_1_LineControl H3800_ASIC2_NOFFSET( u8, UART, 1, LineControl ) +#define H3800_ASIC2_UART_1_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 1, ModemStatus ) +#define H3800_ASIC2_UART_1_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 1, LineStatus ) +#define H3800_ASIC2_UART_1_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 1, ScratchPad ) +#define H3800_ASIC2_UART_1_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchL ) +#define H3800_ASIC2_UART_1_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchH ) + +#define _H3800_ASIC2_TIMER_Base 0x0E00 +#define _H3800_ASIC2_TIMER_Command 0x0000 /* R/W 8 bits */ + +#define H3800_ASIC2_TIMER_Command H3800_ASIC2_OFFSET( u8, Timer, Command ) + +#define H3800_ASIC2_TIMER_GAT_0 ( 1 << 0 ) /* Gate enable, counter 0 */ +#define H3800_ASIC2_TIMER_GAT_1 ( 1 << 1 ) /* Gate enable, counter 1 */ +#define H3800_ASIC2_TIMER_GAT_2 ( 1 << 2 ) /* Gate enable, counter 2 */ +#define H3800_ASIC2_TIMER_CLK_0 ( 1 << 3 ) /* Clock enable, counter 0 */ +#define H3800_ASIC2_TIMER_CLK_1 ( 1 << 4 ) /* Clock enable, counter 1 */ +#define H3800_ASIC2_TIMER_CLK_2 ( 1 << 5 ) /* Clock enable, counter 2 */ +#define H3800_ASIC2_TIMER_MODE_0 ( 1 << 6 ) /* Mode 0 enable, counter 0 */ +#define H3800_ASIC2_TIMER_MODE_1 ( 1 << 7 ) /* Mode 0 enable, counter 1 */ + +#define _H3800_ASIC2_CLOCK_Base 0x1000 +#define _H3800_ASIC2_CLOCK_Enable 0x0000 /* R/W 18 bits */ + +#define H3800_ASIC2_CLOCK_Enable H3800_ASIC2_OFFSET( u32, CLOCK, Enable ) + +#define H3800_ASIC2_CLOCK_AUDIO_1 0x0001 /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */ +#define H3800_ASIC2_CLOCK_AUDIO_2 0x0002 /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */ +#define H3800_ASIC2_CLOCK_AUDIO_3 0x0004 /* Enable 5.6 MHz clock for 11 kHZ sample rate */ +#define H3800_ASIC2_CLOCK_AUDIO_4 0x0008 /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */ +#define H3800_ASIC2_CLOCK_ADC ( 1 << 4 ) /* 1.024 MHz clock to ADC */ +#define H3800_ASIC2_CLOCK_SPI ( 1 << 5 ) /* 4.096 MHz clock to SPI */ +#define H3800_ASIC2_CLOCK_OWM ( 1 << 6 ) /* 4.096 MHz clock to OWM */ +#define H3800_ASIC2_CLOCK_PWM ( 1 << 7 ) /* 2.048 MHz clock to PWM */ +#define H3800_ASIC2_CLOCK_UART_1 ( 1 << 8 ) /* 24.576 MHz clock to UART1 (turn off bit 16) */ +#define H3800_ASIC2_CLOCK_UART_0 ( 1 << 9 ) /* 24.576 MHz clock to UART0 (turn off bit 17) */ +#define H3800_ASIC2_CLOCK_SD_1 ( 1 << 10 ) /* 16.934 MHz to SD */ +#define H3800_ASIC2_CLOCK_SD_2 ( 2 << 10 ) /* 24.576 MHz to SD */ +#define H3800_ASIC2_CLOCK_SD_3 ( 3 << 10 ) /* 33.869 MHz to SD */ +#define H3800_ASIC2_CLOCK_SD_4 ( 4 << 10 ) /* 49.152 MHz to SD */ +#define H3800_ASIC2_CLOCK_EX0 ( 1 << 13 ) /* Enable 32.768 kHz crystal */ +#define H3800_ASIC2_CLOCK_EX1 ( 1 << 14 ) /* Enable 24.576 MHz crystal */ +#define H3800_ASIC2_CLOCK_EX2 ( 1 << 15 ) /* Enable 33.869 MHz crystal */ +#define H3800_ASIC2_CLOCK_SLOW_UART_1 ( 1 << 16 ) /* Enable 3.686 MHz to UART1 (turn off bit 8) */ +#define H3800_ASIC2_CLOCK_SLOW_UART_0 ( 1 << 17 ) /* Enable 3.686 MHz to UART0 (turn off bit 9) */ + +#define _H3800_ASIC2_ADC_Base 0x1200 +#define _H3800_ASIC2_ADC_Multiplexer 0x0000 /* R/W 4 bits - low 3 bits set channel */ +#define _H3800_ASIC2_ADC_ControlStatus 0x0004 /* R/W 8 bits */ +#define _H3800_ASIC2_ADC_Data 0x0008 /* R 10 bits */ + +#define H3800_ASIC2_ADC_Multiplexer H3800_ASIC2_OFFSET( u8, ADC, Multiplexer ) +#define H3800_ASIC2_ADC_ControlStatus H3800_ASIC2_OFFSET( u8, ADC, ControlStatus ) +#define H3800_ASIC2_ADC_Data H3800_ASIC2_OFFSET( u16, ADC, Data ) + +#define H3600_ASIC2_ADC_MUX_CHANNEL_MASK 0x07 /* Low 3 bits sets channel. max = 4 */ +#define H3600_ASIC2_ADC_MUX_CLKEN ( 1 << 3 ) /* Enable clock */ + +#define H3600_ASIC2_ADC_CSR_ADPS_MASK 0x0f /* Low 4 bits sets prescale, max = 8 */ +#define H3600_ASIC2_ADC_CSR_FREE_RUN ( 1 << 4 ) +#define H3600_ASIC2_ADC_CSR_INT_ENABLE ( 1 << 5 ) +#define H3600_ASIC2_ADC_CSR_START ( 1 << 6 ) /* Set to start conversion. Goes to 0 when done */ +#define H3600_ASIC2_ADC_CSR_ENABLE ( 1 << 7 ) /* 1:power up ADC, 0:power down */ + + +#define _H3800_ASIC2_INTR_Base 0x1600 +#define _H3800_ASIC2_INTR_MaskAndFlag 0x0000 /* R/(W) 8bits */ +#define _H3800_ASIC2_INTR_ClockPrescale 0x0004 /* R/(W) 5bits */ +#define _H3800_ASIC2_INTR_TimerSet 0x0008 /* R/(W) 8bits */ + +#define H3800_ASIC2_INTR_MaskAndFlag H3800_ASIC2_OFFSET( u8, INTR, MaskAndFlag ) +#define H3800_ASIC2_INTR_ClockPrescale H3800_ASIC2_OFFSET( u8, INTR, ClockPrescale ) +#define H3800_ASIC2_INTR_TimerSet H3800_ASIC2_OFFSET( u8, INTR, TimerSet ) + +#define H3800_ASIC2_INTR_GLOBAL_MASK ( 1 << 0 ) /* Global interrupt mask */ +#define H3800_ASIC2_INTR_POWER_ON_RESET ( 1 << 1 ) /* 01: Power on reset (bits 1 & 2 ) */ +#define H3800_ASIC2_INTR_EXTERNAL_RESET ( 2 << 1 ) /* 10: External reset (bits 1 & 2 ) */ +#define H3800_ASIC2_INTR_MASK_UART_0 ( 1 << 4 ) +#define H3800_ASIC2_INTR_MASK_UART_1 ( 1 << 5 ) +#define H3800_ASIC2_INTR_MASK_TIMER ( 1 << 6 ) +#define H3800_ASIC2_INTR_MASK_OWM ( 1 << 7 ) + +#define H3800_ASIC2_INTR_CLOCK_PRESCALE 0x0f /* 4 bits, max 14 */ +#define H3800_ASIC2_INTR_SET ( 1 << 4 ) /* Time base enable */ + + +#define _H3800_ASIC2_OWM_Base 0x1800 +#define _H3800_ASIC2_OWM_Command 0x0000 /* R/W 4 bits command register */ +#define _H3800_ASIC2_OWM_Data 0x0004 /* R/W 8 bits, transmit / receive buffer */ +#define _H3800_ASIC2_OWM_Interrupt 0x0008 /* R/W Command register */ +#define _H3800_ASIC2_OWM_InterruptEnable 0x000c /* R/W Command register */ +#define _H3800_ASIC2_OWM_ClockDivisor 0x0010 /* R/W 5 bits of divisor and pre-scale */ + +#define H3800_ASIC2_OWM_Command H3800_ASIC2_OFFSET( u8, OWM, Command ) +#define H3800_ASIC2_OWM_Data H3800_ASIC2_OFFSET( u8, OWM, Data ) +#define H3800_ASIC2_OWM_Interrupt H3800_ASIC2_OFFSET( u8, OWM, Interrupt ) +#define H3800_ASIC2_OWM_InterruptEnable H3800_ASIC2_OFFSET( u8, OWM, InterruptEnable ) +#define H3800_ASIC2_OWM_ClockDivisor H3800_ASIC2_OFFSET( u8, OWM, ClockDivisor ) + +#define H3800_ASIC2_OWM_CMD_ONE_WIRE_RESET ( 1 << 0 ) /* Set to force reset on 1-wire bus */ +#define H3800_ASIC2_OWM_CMD_SRA ( 1 << 1 ) /* Set to switch to Search ROM accelerator mode */ +#define H3800_ASIC2_OWM_CMD_DQ_OUTPUT ( 1 << 2 ) /* Write only - forces bus low */ +#define H3800_ASIC2_OWM_CMD_DQ_INPUT ( 1 << 3 ) /* Read only - reflects state of bus */ + +#define H3800_ASIC2_OWM_INT_PD ( 1 << 0 ) /* Presence detect */ +#define H3800_ASIC2_OWM_INT_PDR ( 1 << 1 ) /* Presence detect result */ +#define H3800_ASIC2_OWM_INT_TBE ( 1 << 2 ) /* Transmit buffer empty */ +#define H3800_ASIC2_OWM_INT_TEMT ( 1 << 3 ) /* Transmit shift register empty */ +#define H3800_ASIC2_OWM_INT_RBF ( 1 << 4 ) /* Receive buffer full */ + +#define H3800_ASIC2_OWM_INTEN_EPD ( 1 << 0 ) /* Enable receive buffer full interrupt */ +#define H3800_ASIC2_OWM_INTEN_IAS ( 1 << 1 ) /* Enable transmit shift register empty interrupt */ +#define H3800_ASIC2_OWM_INTEN_ETBE ( 1 << 2 ) /* Enable transmit buffer empty interrupt */ +#define H3800_ASIC2_OWM_INTEN_ETMT ( 1 << 3 ) /* INTR active state */ +#define H3800_ASIC2_OWM_INTEN_ERBF ( 1 << 4 ) /* Enable presence detect interrupt */ + +#define _H3800_ASIC2_FlashCtl_Base 0x1A00 + +/****************************************************/ +/* H3800, ASIC #1 + * This ASIC is accesed through ASIC #2, and + * mapped into the 1c00 - 1f00 region + */ + +#define H3800_ASIC1_OFFSET(s,x,y) \ + (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y << 1)))) + +#define _H3800_ASIC1_MMC_Base 0x1c00 + +#define _H3800_ASIC1_MMC_StartStopClock 0x00 /* R/W 8bit */ +#define _H3800_ASIC1_MMC_Status 0x02 /* R See below, default 0x0040 */ +#define _H3800_ASIC1_MMC_ClockRate 0x04 /* R/W 8bit, low 3 bits are clock divisor */ +#define _H3800_ASIC1_MMC_SPIRegister 0x08 /* R/W 8bit, see below */ +#define _H3800_ASIC1_MMC_CmdDataCont 0x0a /* R/W 8bit, write to start MMC adapter */ +#define _H3800_ASIC1_MMC_ResponseTimeout 0x0c /* R/W 8bit, clocks before response timeout */ +#define _H3800_ASIC1_MMC_ReadTimeout 0x0e /* R/W 16bit, clocks before received data timeout */ +#define _H3800_ASIC1_MMC_BlockLength 0x10 /* R/W 10bit */ +#define _H3800_ASIC1_MMC_NumOfBlocks 0x12 /* R/W 16bit, in block mode, number of blocks */ +#define _H3800_ASIC1_MMC_InterruptMask 0x1a /* R/W 8bit */ +#define _H3800_ASIC1_MMC_CommandNumber 0x1c /* R/W 6 bits */ +#define _H3800_ASIC1_MMC_ArgumentH 0x1e /* R/W 16 bits */ +#define _H3800_ASIC1_MMC_ArgumentL 0x20 /* R/W 16 bits */ +#define _H3800_ASIC1_MMC_ResFifo 0x22 /* R 8 x 16 bits - contains response FIFO */ +#define _H3800_ASIC1_MMC_BufferPartFull 0x28 /* R/W 8 bits */ + +#define H3800_ASIC1_MMC_StartStopClock H3800_ASIC1_OFFSET( u8, MMC, StartStopClock ) +#define H3800_ASIC1_MMC_Status H3800_ASIC1_OFFSET( u16, MMC, Status ) +#define H3800_ASIC1_MMC_ClockRate H3800_ASIC1_OFFSET( u8, MMC, ClockRate ) +#define H3800_ASIC1_MMC_SPIRegister H3800_ASIC1_OFFSET( u8, MMC, SPIRegister ) +#define H3800_ASIC1_MMC_CmdDataCont H3800_ASIC1_OFFSET( u8, MMC, CmdDataCont ) +#define H3800_ASIC1_MMC_ResponseTimeout H3800_ASIC1_OFFSET( u8, MMC, ResponseTimeout ) +#define H3800_ASIC1_MMC_ReadTimeout H3800_ASIC1_OFFSET( u16, MMC, ReadTimeout ) +#define H3800_ASIC1_MMC_BlockLength H3800_ASIC1_OFFSET( u16, MMC, BlockLength ) +#define H3800_ASIC1_MMC_NumOfBlocks H3800_ASIC1_OFFSET( u16, MMC, NumOfBlocks ) +#define H3800_ASIC1_MMC_InterruptMask H3800_ASIC1_OFFSET( u8, MMC, InterruptMask ) +#define H3800_ASIC1_MMC_CommandNumber H3800_ASIC1_OFFSET( u8, MMC, CommandNumber ) +#define H3800_ASIC1_MMC_ArgumentH H3800_ASIC1_OFFSET( u16, MMC, ArgumentH ) +#define H3800_ASIC1_MMC_ArgumentL H3800_ASIC1_OFFSET( u16, MMC, ArgumentL ) +#define H3800_ASIC1_MMC_ResFifo H3800_ASIC1_OFFSET( u16, MMC, ResFifo ) +#define H3800_ASIC1_MMC_BufferPartFull H3800_ASIC1_OFFSET( u8, MMC, BufferPartFull ) + +#define H3800_ASIC1_MMC_STOP_CLOCK (1 << 0) /* Write to "StartStopClock" register */ +#define H3800_ASIC1_MMC_START_CLOCK (1 << 1) + +#define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT (1 << 0) +#define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT (1 << 1) +#define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR (1 << 2) +#define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR (1 << 3) +#define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR (1 << 4) /* SPI data token error received */ +#define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR (1 << 5) +#define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY (1 << 6) +#define H3800_ASIC1_MMC_STATUS_FIFO_FULL (1 << 7) +#define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE (1 << 8) /* MultiMediaCard clock stopped */ +#define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE (1 << 11) /* Write operation, indicates transfer finished */ +#define H3800_ASIC1_MMC_STATUS_END_PROGRAM (1 << 12) /* End write and read operations */ +#define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE (1 << 13) /* End command response */ + +#define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE (1 << 0) /* Enables SPI mode */ +#define H3800_ASIC1_MMC_SPI_REG_CRC_ON (1 << 1) /* 1:turn on CRC */ +#define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE (1 << 2) /* 1:turn on SPI CS */ +#define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK 0x38 /* Bits 3,4,5 are the SPI CS relative address */ + +#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE 0x00 +#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1 0x01 +#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2 0x02 +#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3 0x03 +#define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE (1 << 2) /* This command contains a data transfer */ +#define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE (1 << 3) /* This data transfer is a write */ +#define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE (1 << 4) /* This data transfer is in stream mode */ +#define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT (1 << 5) /* Busy signal expected after current cmd */ +#define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE (1 << 6) /* Enables the 80 bits for initializing card */ + +#define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE (1 << 0) +#define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE (1 << 1) +#define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE (1 << 2) +#define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY (1 << 3) + +#define H3800_ASIC1_MMC_BUFFER_PART_FULL (1 << 0) + +/********* GPIO **********/ + +#define _H3800_ASIC1_GPIO_Base 0x1e00 + +#define _H3800_ASIC1_GPIO_Mask 0x30 /* R/W 0:don't mask, 1:mask interrupt */ +#define _H3800_ASIC1_GPIO_Direction 0x32 /* R/W 0:input, 1:output */ +#define _H3800_ASIC1_GPIO_Out 0x34 /* R/W 0:output low, 1:output high */ +#define _H3800_ASIC1_GPIO_TriggerType 0x36 /* R/W 0:level, 1:edge */ +#define _H3800_ASIC1_GPIO_EdgeTrigger 0x38 /* R/W 0:falling, 1:rising */ +#define _H3800_ASIC1_GPIO_LevelTrigger 0x3A /* R/W 0:low, 1:high level detect */ +#define _H3800_ASIC1_GPIO_LevelStatus 0x3C /* R/W 0:none, 1:detect */ +#define _H3800_ASIC1_GPIO_EdgeStatus 0x3E /* R/W 0:none, 1:detect */ +#define _H3800_ASIC1_GPIO_State 0x40 /* R See masks below (default 0) */ +#define _H3800_ASIC1_GPIO_Reset 0x42 /* R/W See masks below (default 0x04) */ +#define _H3800_ASIC1_GPIO_SleepMask 0x44 /* R/W 0:don't mask, 1:mask trigger in sleep mode */ +#define _H3800_ASIC1_GPIO_SleepDir 0x46 /* R/W direction 0:input, 1:ouput in sleep mode */ +#define _H3800_ASIC1_GPIO_SleepOut 0x48 /* R/W level 0:low, 1:high in sleep mode */ +#define _H3800_ASIC1_GPIO_Status 0x4A /* R Pin status */ +#define _H3800_ASIC1_GPIO_BattFaultDir 0x4C /* R/W direction 0:input, 1:output in batt_fault */ +#define _H3800_ASIC1_GPIO_BattFaultOut 0x4E /* R/W level 0:low, 1:high in batt_fault */ + +#define H3800_ASIC1_GPIO_Mask H3800_ASIC1_OFFSET( u16, GPIO, Mask ) +#define H3800_ASIC1_GPIO_Direction H3800_ASIC1_OFFSET( u16, GPIO, Direction ) +#define H3800_ASIC1_GPIO_Out H3800_ASIC1_OFFSET( u16, GPIO, Out ) +#define H3800_ASIC1_GPIO_TriggerType H3800_ASIC1_OFFSET( u16, GPIO, TriggerType ) +#define H3800_ASIC1_GPIO_EdgeTrigger H3800_ASIC1_OFFSET( u16, GPIO, EdgeTrigger ) +#define H3800_ASIC1_GPIO_LevelTrigger H3800_ASIC1_OFFSET( u16, GPIO, LevelTrigger ) +#define H3800_ASIC1_GPIO_LevelStatus H3800_ASIC1_OFFSET( u16, GPIO, LevelStatus ) +#define H3800_ASIC1_GPIO_EdgeStatus H3800_ASIC1_OFFSET( u16, GPIO, EdgeStatus ) +#define H3800_ASIC1_GPIO_State H3800_ASIC1_OFFSET( u8, GPIO, State ) +#define H3800_ASIC1_GPIO_Reset H3800_ASIC1_OFFSET( u8, GPIO, Reset ) +#define H3800_ASIC1_GPIO_SleepMask H3800_ASIC1_OFFSET( u16, GPIO, SleepMask ) +#define H3800_ASIC1_GPIO_SleepDir H3800_ASIC1_OFFSET( u16, GPIO, SleepDir ) +#define H3800_ASIC1_GPIO_SleepOut H3800_ASIC1_OFFSET( u16, GPIO, SleepOut ) +#define H3800_ASIC1_GPIO_Status H3800_ASIC1_OFFSET( u16, GPIO, Status ) +#define H3800_ASIC1_GPIO_BattFaultDir H3800_ASIC1_OFFSET( u16, GPIO, BattFaultDir ) +#define H3800_ASIC1_GPIO_BattFaultOut H3800_ASIC1_OFFSET( u16, GPIO, BattFaultOut ) + +#define H3800_ASIC1_GPIO_STATE_MASK (1 << 0) +#define H3800_ASIC1_GPIO_STATE_DIRECTION (1 << 1) +#define H3800_ASIC1_GPIO_STATE_OUT (1 << 2) +#define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE (1 << 3) +#define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER (1 << 4) +#define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER (1 << 5) + +#define H3800_ASIC1_GPIO_RESET_SOFTWARE (1 << 0) +#define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP (1 << 1) +#define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON (1 << 2) + +/* These are all outputs */ +#define GPIO_H3800_ASIC1_IR_ON_N (1 << 0) /* Apply power to the IR Module */ +#define GPIO_H3800_ASIC1_SD_PWR_ON (1 << 1) /* Secure Digital power on */ +#define GPIO_H3800_ASIC1_RS232_ON (1 << 2) /* Turn on power to the RS232 chip ? */ +#define GPIO_H3800_ASIC1_PULSE_GEN (1 << 3) /* Goes to speaker / earphone */ +#define GPIO_H3800_ASIC1_CH_TIMER (1 << 4) /* */ +#define GPIO_H3800_ASIC1_LCD_5V_ON (1 << 5) /* Enables LCD_5V */ +#define GPIO_H3800_ASIC1_LCD_ON (1 << 6) /* Enables LCD_3V */ +#define GPIO_H3800_ASIC1_LCD_PCI (1 << 7) /* Connects to PDWN on LCD controller */ +#define GPIO_H3800_ASIC1_VGH_ON (1 << 8) /* Drives VGH on the LCD (+9??) */ +#define GPIO_H3800_ASIC1_VGL_ON (1 << 9) /* Drivers VGL on the LCD (-6??) */ +#define GPIO_H3800_ASIC1_FL_PWR_ON (1 << 10) /* Frontlight power on */ +#define GPIO_H3800_ASIC1_BT_PWR_ON (1 << 11) /* Bluetooth power on */ +#define GPIO_H3800_ASIC1_SPK_ON (1 << 12) /* */ +#define GPIO_H3800_ASIC1_EAR_ON_N (1 << 13) /* */ +#define GPIO_H3800_ASIC1_AUD_PWR_ON (1 << 14) /* */ + +/* Write enable for the flash */ + +#define _H3800_ASIC1_FlashWP_Base 0x1F00 +#define _H3800_ASIC1_FlashWP_VPP_ON 0x00 /* R 1: write, 0: protect */ +#define H3800_ASIC1_FlashWP_VPP_ON H3800_ASIC1_OFFSET( u8, FlashWP, VPP_ON ) + +#endif /* _INCLUDE_H3600_GPIO_H_ */ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/hardware.h linux/include/asm-arm/arch-sa1100/hardware.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/hardware.h Fri Nov 9 14:11:15 2001 +++ linux/include/asm-arm/arch-sa1100/hardware.h Sat Jan 5 14:43:18 2002 @@ -60,6 +60,7 @@ ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))< #if 0 # define __REG(x) (*((volatile u32 *)io_p2v(x))) @@ -93,17 +94,12 @@ * This must be called *before* the corresponding IRQ is registered. * Use this instead of directly setting GRER/GFER. */ +#define GPIO_NO_EDGES 0 #define GPIO_FALLING_EDGE 1 #define GPIO_RISING_EDGE 2 #define GPIO_BOTH_EDGES 3 #ifndef __ASSEMBLY__ extern void set_GPIO_IRQ_edge( int gpio_mask, int edge_mask ); - -/* - * Return the current CPU clock frequency in units of 100kHz - */ -extern unsigned short get_cclk_frequency(void); - #endif @@ -145,9 +141,7 @@ #include "empeg.h" #endif -#ifdef CONFIG_SA1100_H3600 #include "h3600.h" -#endif #ifdef CONFIG_SA1100_ITSY #include "itsy.h" @@ -185,6 +179,8 @@ #include "adsbitsy.h" #endif +#include "system3.h" + #ifdef CONFIG_SA1101 /* @@ -209,21 +205,6 @@ #if defined(CONFIG_SA1100_FLEXANET) #include "flexanet.h" -#endif - -#ifdef CONFIG_SA1111 - -/* - * The SA1111 is always located at virtual 0xf4000000. - */ - -#define SA1111_VBASE 0xf4000000 - -#define SA1111_p2v( x ) ((x) - SA1111_BASE + SA1111_VBASE) -#define SA1111_v2p( x ) ((x) - SA1111_VBASE + SA1111_BASE) - -#include "SA-1111.h" - #endif #endif /* _ASM_ARCH_HARDWARE_H */ diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/io.h linux/include/asm-arm/arch-sa1100/io.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/io.h Thu Feb 8 16:32:44 2001 +++ linux/include/asm-arm/arch-sa1100/io.h Sat Jan 5 14:43:18 2002 @@ -20,13 +20,4 @@ #define __mem_pci(a) ((unsigned long)(a)) #define __mem_isa(a) ((unsigned long)(a)) -/* - * Generic virtual read/write - */ -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) - -#define iomem_valid_addr(iomem,sz) (1) -#define iomem_to_phys(iomem) (iomem) - #endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/irqs.h linux/include/asm-arm/arch-sa1100/irqs.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/irqs.h Thu Oct 11 09:04:57 2001 +++ linux/include/asm-arm/arch-sa1100/irqs.h Sat Jan 5 14:43:18 2002 @@ -4,154 +4,150 @@ * Copyright (C) 1996 Russell King * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus). * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation) + * + * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs. */ - #include -#define SA1100_IRQ(x) (0 + (x)) - -#define IRQ_GPIO0 SA1100_IRQ(0) -#define IRQ_GPIO1 SA1100_IRQ(1) -#define IRQ_GPIO2 SA1100_IRQ(2) -#define IRQ_GPIO3 SA1100_IRQ(3) -#define IRQ_GPIO4 SA1100_IRQ(4) -#define IRQ_GPIO5 SA1100_IRQ(5) -#define IRQ_GPIO6 SA1100_IRQ(6) -#define IRQ_GPIO7 SA1100_IRQ(7) -#define IRQ_GPIO8 SA1100_IRQ(8) -#define IRQ_GPIO9 SA1100_IRQ(9) -#define IRQ_GPIO10 SA1100_IRQ(10) -#define IRQ_GPIO11_27 SA1100_IRQ(11) -#define IRQ_LCD SA1100_IRQ(12) /* LCD controller */ -#define IRQ_Ser0UDC SA1100_IRQ(13) /* Ser. port 0 UDC */ -#define IRQ_Ser1SDLC SA1100_IRQ(14) /* Ser. port 1 SDLC */ -#define IRQ_Ser1UART SA1100_IRQ(15) /* Ser. port 1 UART */ -#define IRQ_Ser2ICP SA1100_IRQ(16) /* Ser. port 2 ICP */ -#define IRQ_Ser3UART SA1100_IRQ(17) /* Ser. port 3 UART */ -#define IRQ_Ser4MCP SA1100_IRQ(18) /* Ser. port 4 MCP */ -#define IRQ_Ser4SSP SA1100_IRQ(19) /* Ser. port 4 SSP */ -#define IRQ_DMA0 SA1100_IRQ(20) /* DMA controller channel 0 */ -#define IRQ_DMA1 SA1100_IRQ(21) /* DMA controller channel 1 */ -#define IRQ_DMA2 SA1100_IRQ(22) /* DMA controller channel 2 */ -#define IRQ_DMA3 SA1100_IRQ(23) /* DMA controller channel 3 */ -#define IRQ_DMA4 SA1100_IRQ(24) /* DMA controller channel 4 */ -#define IRQ_DMA5 SA1100_IRQ(25) /* DMA controller channel 5 */ -#define IRQ_OST0 SA1100_IRQ(26) /* OS Timer match 0 */ -#define IRQ_OST1 SA1100_IRQ(27) /* OS Timer match 1 */ -#define IRQ_OST2 SA1100_IRQ(28) /* OS Timer match 2 */ -#define IRQ_OST3 SA1100_IRQ(29) /* OS Timer match 3 */ -#define IRQ_RTC1Hz SA1100_IRQ(30) /* RTC 1 Hz clock */ -#define IRQ_RTCAlrm SA1100_IRQ(31) /* RTC Alarm */ - -#define IRQ_GPIO_11_27(x) (32 + (x) - 11) - -#define IRQ_GPIO11 IRQ_GPIO_11_27(11) -#define IRQ_GPIO12 IRQ_GPIO_11_27(12) -#define IRQ_GPIO13 IRQ_GPIO_11_27(13) -#define IRQ_GPIO14 IRQ_GPIO_11_27(14) -#define IRQ_GPIO15 IRQ_GPIO_11_27(15) -#define IRQ_GPIO16 IRQ_GPIO_11_27(16) -#define IRQ_GPIO17 IRQ_GPIO_11_27(17) -#define IRQ_GPIO18 IRQ_GPIO_11_27(18) -#define IRQ_GPIO19 IRQ_GPIO_11_27(19) -#define IRQ_GPIO20 IRQ_GPIO_11_27(20) -#define IRQ_GPIO21 IRQ_GPIO_11_27(21) -#define IRQ_GPIO22 IRQ_GPIO_11_27(22) -#define IRQ_GPIO23 IRQ_GPIO_11_27(23) -#define IRQ_GPIO24 IRQ_GPIO_11_27(24) -#define IRQ_GPIO25 IRQ_GPIO_11_27(25) -#define IRQ_GPIO26 IRQ_GPIO_11_27(26) -#define IRQ_GPIO27 IRQ_GPIO_11_27(27) - -#define SA1100_GPIO_TO_IRQ(i) (((i) < 11) ? SA1100_IRQ(i) : IRQ_GPIO_11_27(i)) - -/* To get the GPIO number from an IRQ number */ -#define GPIO_11_27_IRQ(i) (11 + (i) - 32) -#define SA1100_IRQ_TO_GPIO(i) (((i) < 11) ? (i) : GPIO_11_27_IRQ(i)) - -#define NR_IRQS (IRQ_GPIO27 + 1) - - -#if defined(CONFIG_SA1100_GRAPHICSCLIENT) || defined(CONFIG_SA1100_GRAPHICSMASTER) -#define ADS_EXT_IRQ(x) (IRQ_GPIO27 + 1 + (x)) -#undef NR_IRQS -#define NR_IRQS (ADS_EXT_IRQ(15) + 1) -#endif +#define IRQ_GPIO0 0 +#define IRQ_GPIO1 1 +#define IRQ_GPIO2 2 +#define IRQ_GPIO3 3 +#define IRQ_GPIO4 4 +#define IRQ_GPIO5 5 +#define IRQ_GPIO6 6 +#define IRQ_GPIO7 7 +#define IRQ_GPIO8 8 +#define IRQ_GPIO9 9 +#define IRQ_GPIO10 10 +#define IRQ_GPIO11_27 11 +#define IRQ_LCD 12 /* LCD controller */ +#define IRQ_Ser0UDC 13 /* Ser. port 0 UDC */ +#define IRQ_Ser1SDLC 14 /* Ser. port 1 SDLC */ +#define IRQ_Ser1UART 15 /* Ser. port 1 UART */ +#define IRQ_Ser2ICP 16 /* Ser. port 2 ICP */ +#define IRQ_Ser3UART 17 /* Ser. port 3 UART */ +#define IRQ_Ser4MCP 18 /* Ser. port 4 MCP */ +#define IRQ_Ser4SSP 19 /* Ser. port 4 SSP */ +#define IRQ_DMA0 20 /* DMA controller channel 0 */ +#define IRQ_DMA1 21 /* DMA controller channel 1 */ +#define IRQ_DMA2 22 /* DMA controller channel 2 */ +#define IRQ_DMA3 23 /* DMA controller channel 3 */ +#define IRQ_DMA4 24 /* DMA controller channel 4 */ +#define IRQ_DMA5 25 /* DMA controller channel 5 */ +#define IRQ_OST0 26 /* OS Timer match 0 */ +#define IRQ_OST1 27 /* OS Timer match 1 */ +#define IRQ_OST2 28 /* OS Timer match 2 */ +#define IRQ_OST3 29 /* OS Timer match 3 */ +#define IRQ_RTC1Hz 30 /* RTC 1 Hz clock */ +#define IRQ_RTCAlrm 31 /* RTC Alarm */ + +#define IRQ_GPIO11 32 +#define IRQ_GPIO12 33 +#define IRQ_GPIO13 34 +#define IRQ_GPIO14 35 +#define IRQ_GPIO15 36 +#define IRQ_GPIO16 37 +#define IRQ_GPIO17 38 +#define IRQ_GPIO18 39 +#define IRQ_GPIO19 40 +#define IRQ_GPIO20 41 +#define IRQ_GPIO21 42 +#define IRQ_GPIO22 43 +#define IRQ_GPIO23 44 +#define IRQ_GPIO24 45 +#define IRQ_GPIO25 46 +#define IRQ_GPIO26 47 +#define IRQ_GPIO27 48 +/* + * To get the GPIO number from an IRQ number + */ +#define GPIO_11_27_IRQ(i) ((i) - 21) -#if defined(CONFIG_SA1111) +/* + * The next 16 interrupts are for board specific purposes. Since + * the kernel can only run on one machine at a time, we can re-use + * these. If you need more, increase IRQ_BOARD_END, but keep it + * within sensible limits. IRQs 49 to 64 are available. + */ +#define IRQ_BOARD_START 49 +#define IRQ_BOARD_END 65 -#if defined(CONFIG_SA1100_GRAPHICSMASTER) -#define SA1111_IRQ(x) (ADS_EXT_IRQ(15) + 1 + 1 + (x)) +#define IRQ_SA1111_START (IRQ_BOARD_END) +#define IRQ_GPAIN0 (IRQ_BOARD_END + 0) +#define IRQ_GPAIN1 (IRQ_BOARD_END + 1) +#define IRQ_GPAIN2 (IRQ_BOARD_END + 2) +#define IRQ_GPAIN3 (IRQ_BOARD_END + 3) +#define IRQ_GPBIN0 (IRQ_BOARD_END + 4) +#define IRQ_GPBIN1 (IRQ_BOARD_END + 5) +#define IRQ_GPBIN2 (IRQ_BOARD_END + 6) +#define IRQ_GPBIN3 (IRQ_BOARD_END + 7) +#define IRQ_GPBIN4 (IRQ_BOARD_END + 8) +#define IRQ_GPBIN5 (IRQ_BOARD_END + 9) +#define IRQ_GPCIN0 (IRQ_BOARD_END + 10) +#define IRQ_GPCIN1 (IRQ_BOARD_END + 11) +#define IRQ_GPCIN2 (IRQ_BOARD_END + 12) +#define IRQ_GPCIN3 (IRQ_BOARD_END + 13) +#define IRQ_GPCIN4 (IRQ_BOARD_END + 14) +#define IRQ_GPCIN5 (IRQ_BOARD_END + 15) +#define IRQ_GPCIN6 (IRQ_BOARD_END + 16) +#define IRQ_GPCIN7 (IRQ_BOARD_END + 17) +#define IRQ_MSTXINT (IRQ_BOARD_END + 18) +#define IRQ_MSRXINT (IRQ_BOARD_END + 19) +#define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20) +#define IRQ_TPTXINT (IRQ_BOARD_END + 21) +#define IRQ_TPRXINT (IRQ_BOARD_END + 22) +#define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23) +#define SSPXMTINT (IRQ_BOARD_END + 24) +#define SSPRCVINT (IRQ_BOARD_END + 25) +#define SSPROR (IRQ_BOARD_END + 26) +#define AUDXMTDMADONEA (IRQ_BOARD_END + 32) +#define AUDRCVDMADONEA (IRQ_BOARD_END + 33) +#define AUDXMTDMADONEB (IRQ_BOARD_END + 34) +#define AUDRCVDMADONEB (IRQ_BOARD_END + 35) +#define AUDTFSR (IRQ_BOARD_END + 36) +#define AUDRFSR (IRQ_BOARD_END + 37) +#define AUDTUR (IRQ_BOARD_END + 38) +#define AUDROR (IRQ_BOARD_END + 39) +#define AUDDTS (IRQ_BOARD_END + 40) +#define AUDRDD (IRQ_BOARD_END + 41) +#define AUDSTO (IRQ_BOARD_END + 42) +#define USBPWR (IRQ_BOARD_END + 43) +#define NIRQHCIM (IRQ_BOARD_END + 44) +#define IRQHCIBUFFACC (IRQ_BOARD_END + 45) +#define IRQHCIRMTWKP (IRQ_BOARD_END + 46) +#define NHCIMFCIR (IRQ_BOARD_END + 47) +#define USB_PORT_RESUME (IRQ_BOARD_END + 48) +#define S0_READY_NINT (IRQ_BOARD_END + 49) +#define S1_READY_NINT (IRQ_BOARD_END + 50) +#define S0_CD_VALID (IRQ_BOARD_END + 51) +#define S1_CD_VALID (IRQ_BOARD_END + 52) +#define S0_BVD1_STSCHG (IRQ_BOARD_END + 53) +#define S1_BVD1_STSCHG (IRQ_BOARD_END + 54) + +/* + * Figure out the MAX IRQ number. + * + * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1. + * If graphicsclient or graphicsmaster, we don't have a SA1111. + * Otherwise, we have the standard IRQs only. + */ +#ifdef CONFIG_SA1111 +#define NR_IRQS (S1_BVD1_STSCHG + 1) +#elif defined(CONFIG_SA1100_GRAPHICSCLIENT) || \ + defined(CONFIG_SA1100_GRAPHICSMASTER) +#define NR_IRQS (IRQ_BOARD_END) #else -#define SA1111_IRQ(x) (IRQ_GPIO27 + 1 + (x)) +#define NR_IRQS (IRQ_BOARD_START) #endif -#define GPAIN0 SA1111_IRQ(0) -#define GPAIN1 SA1111_IRQ(1) -#define GPAIN2 SA1111_IRQ(2) -#define GPAIN3 SA1111_IRQ(3) -#define GPBIN0 SA1111_IRQ(4) -#define GPBIN1 SA1111_IRQ(5) -#define GPBIN2 SA1111_IRQ(6) -#define GPBIN3 SA1111_IRQ(7) -#define GPBIN4 SA1111_IRQ(8) -#define GPBIN5 SA1111_IRQ(9) -#define GPCIN0 SA1111_IRQ(10) -#define GPCIN1 SA1111_IRQ(11) -#define GPCIN2 SA1111_IRQ(12) -#define GPCIN3 SA1111_IRQ(13) -#define GPCIN4 SA1111_IRQ(14) -#define GPCIN5 SA1111_IRQ(15) -#define GPCIN6 SA1111_IRQ(16) -#define GPCIN7 SA1111_IRQ(17) -#define MSTXINT SA1111_IRQ(18) -#define MSRXINT SA1111_IRQ(19) -#define MSSTOPERRINT SA1111_IRQ(20) -#define TPTXINT SA1111_IRQ(21) -#define TPRXINT SA1111_IRQ(22) -#define TPSTOPERRINT SA1111_IRQ(23) -#define SSPXMTINT SA1111_IRQ(24) -#define SSPRCVINT SA1111_IRQ(25) -#define SSPROR SA1111_IRQ(26) -#define AUDXMTDMADONEA SA1111_IRQ(32) -#define AUDRCVDMADONEA SA1111_IRQ(33) -#define AUDXMTDMADONEB SA1111_IRQ(34) -#define AUDRCVDMADONEB SA1111_IRQ(35) -#define AUDTFSR SA1111_IRQ(36) -#define AUDRFSR SA1111_IRQ(37) -#define AUDTUR SA1111_IRQ(38) -#define AUDROR SA1111_IRQ(39) -#define AUDDTS SA1111_IRQ(40) -#define AUDRDD SA1111_IRQ(41) -#define AUDSTO SA1111_IRQ(42) -#define USBPWR SA1111_IRQ(43) -#define NIRQHCIM SA1111_IRQ(44) -#define IRQHCIBUFFACC SA1111_IRQ(45) -#define IRQHCIRMTWKP SA1111_IRQ(46) -#define NHCIMFCIR SA1111_IRQ(47) -#define USB_PORT_RESUME SA1111_IRQ(48) -#define S0_READY_NINT SA1111_IRQ(49) -#define S1_READY_NINT SA1111_IRQ(50) -#define S0_CD_VALID SA1111_IRQ(51) -#define S1_CD_VALID SA1111_IRQ(52) -#define S0_BVD1_STSCHG SA1111_IRQ(53) -#define S1_BVD1_STSCHG SA1111_IRQ(54) - -#define SA1111_IRQ_MAX SA1111_IRQ(54) - -#undef NR_IRQS -#define NR_IRQS (SA1111_IRQ_MAX + 1) - - -#ifdef CONFIG_ASSABET_NEPONSET - -#define MISC_IRQ0 SA1111_IRQ(55) -#define MISC_IRQ1 SA1111_IRQ(56) - -#undef NR_IRQS -#define NR_IRQS (SA1111_IRQ_MAX + 3) - -#endif /* CONFIG_ASSABET_NEPONSET */ +/* + * Board specific IRQs. Define them here. + * Do not surround them with ifdefs. + */ +#define IRQ_NEPONSET_SMC9196 (IRQ_BOARD_START + 0) +#define IRQ_NEPONSET_USAR (IRQ_BOARD_START + 1) -#endif /* CONFIG_SA1111 */ +/* PT Digital Board Interrupts (CONFIG_SA1100_PT_SYSTEM3) */ +#define IRQ_SYSTEM3_SMC9196 (IRQ_BOARD_START + 0) diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/keyboard.h linux/include/asm-arm/arch-sa1100/keyboard.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/keyboard.h Thu Oct 25 13:53:54 2001 +++ linux/include/asm-arm/arch-sa1100/keyboard.h Sat Jan 5 14:43:18 2002 @@ -13,7 +13,7 @@ #define kbd_disable_irq() do { } while(0); #define kbd_enable_irq() do { } while(0); -extern void sa1111_kbd_init_hw(void); +extern int sa1111_kbd_init_hw(void); extern void gc_kbd_init_hw(void); extern void smartio_kbd_init_hw(void); extern void cerf_kbd_init_hw(void); @@ -30,6 +30,11 @@ #ifdef CONFIG_SA1100_CERF_CPLD if (machine_is_cerf()) cerf_kbd_init_hw(); +#endif +#ifdef CONFIG_SA1100_PT_SYSTEM3 + /* TODO: add system 3 board specific functions here */ + if (machine_is_pt_system3()) + sa1111_kbd_init_hw(); #endif } diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/pcmcia.h linux/include/asm-arm/arch-sa1100/pcmcia.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/pcmcia.h Thu Apr 12 12:20:31 2001 +++ linux/include/asm-arm/arch-sa1100/pcmcia.h Wed Dec 31 16:00:00 1969 @@ -1,70 +0,0 @@ -/* - * linux/include/asm/arch/pcmcia.h - * - * Copyright (C) 2000 John G Dorsey - * - * This file contains definitions for the low-level SA-1100 kernel PCMCIA - * interface. Please see linux/Documentation/arm/SA1100/PCMCIA for details. - */ - -#ifndef _ASM_ARCH_PCMCIA -#define _ASM_ARCH_PCMCIA - - -/* Ideally, we'd support up to MAX_SOCK sockets, but the SA-1100 only - * has support for two. This shows up in lots of hardwired ways, such - * as the fact that MECR only has enough bits to configure two sockets. - * Since it's so entrenched in the hardware, limiting the software - * in this way doesn't seem too terrible. - */ -#define SA1100_PCMCIA_MAX_SOCK (2) - - -#ifndef __ASSEMBLY__ - -struct pcmcia_init { - void (*handler)(int irq, void *dev, struct pt_regs *regs); -}; - -struct pcmcia_state { - unsigned detect: 1, - ready: 1, - bvd1: 1, - bvd2: 1, - wrprot: 1, - vs_3v: 1, - vs_Xv: 1; -}; - -struct pcmcia_state_array { - unsigned int size; - struct pcmcia_state *state; -}; - -struct pcmcia_configure { - unsigned sock: 8, - vcc: 8, - vpp: 8, - output: 1, - speaker: 1, - reset: 1; -}; - -struct pcmcia_irq_info { - unsigned int sock; - unsigned int irq; -}; - -struct pcmcia_low_level { - int (*init)(struct pcmcia_init *); - int (*shutdown)(void); - int (*socket_state)(struct pcmcia_state_array *); - int (*get_irq_info)(struct pcmcia_irq_info *); - int (*configure_socket)(const struct pcmcia_configure *); -}; - -extern struct pcmcia_low_level *pcmcia_low_level; - -#endif /* __ASSEMBLY__ */ - -#endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/shannon.h linux/include/asm-arm/arch-sa1100/shannon.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/shannon.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-sa1100/shannon.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,43 @@ +#ifndef _INCLUDE_SHANNON_H +#define _INCLUDE_SHANNON_H + +/* taken from comp.os.inferno Tue, 12 Sep 2000 09:21:50 GMT, + * written by */ + +#define SHANNON_GPIO_SPI_FLASH GPIO_GPIO (0) /* Output - Driven low, enables SPI to flash */ +#define SHANNON_GPIO_SPI_DSP GPIO_GPIO (1) /* Output - Driven low, enables SPI to DSP */ +/* lcd lower = GPIO 2-9 */ +#define SHANNON_GPIO_SPI_OUTPUT GPIO_GPIO (10) /* Output - SPI output to DSP */ +#define SHANNON_GPIO_SPI_INPUT GPIO_GPIO (11) /* Input - SPI input from DSP */ +#define SHANNON_GPIO_SPI_CLOCK GPIO_GPIO (12) /* Output - Clock for SPI */ +#define SHANNON_GPIO_SPI_FRAME GPIO_GPIO (13) /* Output - Frame marker - not used */ +#define SHANNON_GPIO_SPI_RTS GPIO_GPIO (14) /* Input - SPI Ready to Send */ +#define SHANNON_IRQ_GPIO_SPI_RTS IRQ_GPIO14 +#define SHANNON_GPIO_SPI_CTS GPIO_GPIO (15) /* Output - SPI Clear to Send */ +#define SHANNON_GPIO_IRQ_CODEC GPIO_GPIO (16) /* in, irq from ucb1200 */ +#define SHANNON_IRQ_GPIO_IRQ_CODEC IRQ_GPIO16 +#define SHANNON_GPIO_DSP_RESET GPIO_GPIO (17) /* Output - Drive low to reset the DSP */ +#define SHANNON_GPIO_CODEC_RESET GPIO_GPIO (18) /* Output - Drive low to reset the UCB1x00 */ +#define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */ +#define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */ +#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ +#define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */ +/* XXX GPIO 23 unaccounted for */ +#define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */ +#define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24 +#define SHANNON_GPIO_EJECT_1 GPIO_GPIO (25) /* in */ +#define SHANNON_IRQ_GPIO_EJECT_1 IRQ_GPIO25 +#define SHANNON_GPIO_RDY_0 GPIO_GPIO (26) /* in */ +#define SHANNON_IRQ_GPIO_RDY_0 IRQ_GPIO26 +#define SHANNON_GPIO_RDY_1 GPIO_GPIO (27) /* in */ +#define SHANNON_IRQ_GPIO_RDY_1 IRQ_GPIO27 + +/* MCP UCB codec GPIO pins... */ + +#define SHANNON_UCB_GPIO_BACKLIGHT 9 +#define SHANNON_UCB_GPIO_BRIGHT_MASK 7 +#define SHANNON_UCB_GPIO_BRIGHT 6 +#define SHANNON_UCB_GPIO_CONTRAST_MASK 0x3f +#define SHANNON_UCB_GPIO_CONTRAST 0 + +#endif diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/system3.h linux/include/asm-arm/arch-sa1100/system3.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/system3.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/arch-sa1100/system3.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,113 @@ +/* + * linux/include/asm-arm/arch-sa1100/system3.h + * + * Copyright (C) 2001 Stefan Eletzhofer + * + * $Id: system3.h,v 1.2.4.2 2001/12/04 14:58:50 seletz Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * $Log: system3.h,v $ + * Revision 1.2.4.2 2001/12/04 14:58:50 seletz + * - removed neponset hack + * - removed irq definitions (now in irqs.h) + * + * Revision 1.2.4.1 2001/12/04 12:51:18 seletz + * - re-added from linux_2_4_8_ac12_rmk1_np1_pt1 + * + * Revision 1.2.2.2 2001/11/16 13:58:43 seletz + * - simplified cpld register access + * + * Revision 1.2.2.1 2001/10/15 16:17:20 seletz + * - first revision + * + * + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#error "include instead" +#endif + +/* System 3 LCD */ +#define SYS3LCD SKPEN0 +#define SYS3LCDBACKL SKPEN1 +#define SYS3LCDBRIGHT SKPWM0 +#define SYS3LCDCONTR SKPWM1 + +#define PT_CPLD_BASE (0x10000000) +#define PT_SMC_BASE (0x18000000) +#define PT_SA1111_BASE (0x40000000) + +#define SA1111_BASE PT_SA1111_BASE + +#define Ptcpld_p2v( x ) ((x) - PT_CPLD_BASE + 0xf3000000) +#define Ptcpld_v2p( x ) ((x) - 0xf3000000 + PT_CPLD_BASE) + +#define _PT_SYSID ( PT_CPLD_BASE + 0x00 ) +#define _PT_IRQSR ( PT_CPLD_BASE + 0x24 ) +#define _PT_CTRL0 ( PT_CPLD_BASE + 0x90 ) +#define _PT_CTRL1 ( PT_CPLD_BASE + 0xA0 ) +#define _PT_CTRL2 ( PT_CPLD_BASE + 0xB0 ) + +#define PT_SYSID (*((volatile u_char *)Ptcpld_p2v( _PT_SYSID ))) +#define PT_IRQSR (*((volatile u_char *)Ptcpld_p2v( _PT_IRQSR ))) +#define PT_CTRL0 (*((volatile u_char *)Ptcpld_p2v( _PT_CTRL0 ))) +#define PT_CTRL1 (*((volatile u_char *)Ptcpld_p2v( _PT_CTRL1 ))) +#define PT_CTRL2 (*((volatile u_char *)Ptcpld_p2v( _PT_CTRL2 ))) + +#define PTCTRL0_set( x ) PT_CTRL0 |= (x) +#define PTCTRL1_set( x ) PT_CTRL1 |= (x) +#define PTCTRL2_set( x ) PT_CTRL2 |= (x) +#define PTCTRL0_clear( x ) PT_CTRL0 &= ~(x) +#define PTCTRL1_clear( x ) PT_CTRL1 &= ~(x) +#define PTCTRL2_clear( x ) PT_CTRL2 &= ~(x) + +/* System ID register */ + +/* IRQ Source Register */ +#define PT_IRQ_LAN ( 1<<0 ) +#define PT_IRQ_X ( 1<<1 ) +#define PT_IRQ_SA1111 ( 1<<2 ) +#define PT_IRQ_RS1 ( 1<<3 ) +#define PT_IRQ_RS1_RING ( 1<<4 ) +#define PT_IRQ_RS1_DCD ( 1<<5 ) +#define PT_IRQ_RS1_DSR ( 1<<6 ) +#define PT_IRQ_RS2 ( 1<<7 ) + +/* FIXME */ +#define PT_IRQ_USAR ( 1<<1 ) + +/* CTRL 0 */ +#define PT_CTRL0_USBSLAVE ( 1<<0 ) +#define PT_CTRL0_USBHOST ( 1<<1 ) +#define PT_CTRL0_LCD_BL ( 1<<2 ) +#define PT_CTRL0_LAN_EN ( 1<<3 ) /* active low */ +#define PT_CTRL0_IRDA_M(x) ( (((u_char)x)&0x03)<<4 ) +#define PT_CTRL0_IRDA_M0 ( 1<<4 ) +#define PT_CTRL0_IRDA_M1 ( 1<<5 ) +#define PT_CTRL0_IRDA_FSEL ( 1<<6 ) +#define PT_CTRL0_LCD_EN ( 1<<7 ) + +#define PT_CTRL0_INIT ( PT_CTRL0_USBSLAVE | PT_CTRL0_USBHOST | \ + PT_CTRL0_LCD_BL | PT_CTRL0_LAN_EN | PT_CTRL0_LCD_EN ) + +/* CTRL 1 */ +#define PT_CTRL1_RS3_MUX(x) ( (((u_char)x)&0x03)<<0 ) +#define PT_CTRL1_RS3_MUX0 ( 1<<0 ) +#define PT_CTRL1_RS3_MUX1 ( 1<<1 ) +#define PT_CTRL1_RS3_RST ( 1<<2 ) +#define PT_CTRL1_RS3_RS485_TERM ( 1<<4 ) +#define PT_CTRL1_X ( 1<<4 ) +#define PT_CTRL1_PCMCIA_A0VPP ( 1<<6 ) +#define PT_CTRL1_PCMCIA_A1VPP ( 1<<7 ) + +#define PT_RS3_MUX_ALIRS ( 0 ) +#define PT_RS3_MUX_IDATA ( 1 ) +#define PT_RS3_MUX_RADIO ( 2 ) +#define PT_RS3_MUX_RS485 ( 3 ) + +/* CTRL 2 */ +#define PT_CTRL2_RS1_RTS ( 1<<0 ) +#define PT_CTRL2_RS1_DTR ( 1<<1 ) diff -urN linux-2.5.2-pre8/include/asm-arm/arch-sa1100/time.h linux/include/asm-arm/arch-sa1100/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-sa1100/time.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-sa1100/time.h Sat Jan 5 14:43:18 2002 @@ -10,7 +10,7 @@ */ -#define RTC_DEF_DIVIDER 32768 - 1 +#define RTC_DEF_DIVIDER (32768 - 1) #define RTC_DEF_TRIM 0 static unsigned long __init sa1100_get_rtc_time(void) @@ -63,29 +63,34 @@ return usec; } +/* + * We will be entered with IRQs enabled. + * + * Loop until we get ahead of the free running timer. + * This ensures an exact clock tick count and time acuracy. + * IRQs are disabled inside the loop to ensure coherence between + * lost_ticks (updated in do_timer()) and the match reg value, so we + * can use do_gettimeofday() from interrupt handlers. + */ static void sa1100_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { - long flags; - int next_match; + unsigned int next_match; + unsigned long flags; - /* Loop until we get ahead of the free running timer. - * This ensures an exact clock tick count and time acuracy. - * IRQs are disabled inside the loop to ensure coherence between - * lost_ticks (updated in do_timer()) and the match reg value, so we - * can use do_gettimeofday() from interrupt handlers. - */ do { do_leds(); - do_set_rtc(); - save_flags_cli( flags ); + local_irq_save(flags); do_timer(regs); OSSR = OSSR_M0; /* Clear match on timer 0 */ next_match = (OSMR0 += LATCH); - restore_flags( flags ); - } while( (signed long)(next_match - OSCR) <= 0 ); + local_irq_restore(flags); + do_set_rtc(); + } while ((signed long)(next_match - OSCR) <= 0); + + do_profile(regs); } -static inline void setup_timer (void) +void __init time_init(void) { gettimeoffset = sa1100_gettimeoffset; set_rtc = sa1100_set_rtc; diff -urN linux-2.5.2-pre8/include/asm-arm/arch-shark/io.h linux/include/asm-arm/arch-shark/io.h --- linux-2.5.2-pre8/include/asm-arm/arch-shark/io.h Thu Oct 25 13:53:55 2001 +++ linux/include/asm-arm/arch-shark/io.h Sat Jan 5 14:43:18 2002 @@ -11,9 +11,6 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#define iomem_valid_addr(off,sz) (1) -#define iomem_to_phys(off) (off) - #define IO_SPACE_LIMIT 0xffffffff /* @@ -181,9 +178,6 @@ #define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) #define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) #define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) - -#define __arch_getw(addr) (*(volatile unsigned short *)(addr)) -#define __arch_putw(b,addr) (*(volatile unsigned short *)(addr) = (b)) /* * Translated address IO functions diff -urN linux-2.5.2-pre8/include/asm-arm/arch-shark/irq.h linux/include/asm-arm/arch-shark/irq.h --- linux-2.5.2-pre8/include/asm-arm/arch-shark/irq.h Thu Oct 25 13:53:55 2001 +++ linux/include/asm-arm/arch-shark/irq.h Sat Jan 5 14:43:18 2002 @@ -7,118 +7,4 @@ * include/asm-arm/arch-ebsa110/irq.h * Copyright (C) 1996-1998 Russell King */ - -#include #define fixup_irq(x) (x) - -/* - * 8259A PIC functions to handle ISA devices: - */ - -/* - * This contains the irq mask for both 8259A irq controllers, - * Let through the cascade-interrupt no. 2 (ff-(1<<2)==fb) - */ -static unsigned char cached_irq_mask[2] = { 0xfb, 0xff }; - -/* - * These have to be protected by the irq controller spinlock - * before being called. - */ -static void shark_disable_8259A_irq(unsigned int irq) -{ - unsigned int mask; - if (irq<8) { - mask = 1 << irq; - cached_irq_mask[0] |= mask; - } else { - mask = 1 << (irq-8); - cached_irq_mask[1] |= mask; - } - outb(cached_irq_mask[1],0xA1); - outb(cached_irq_mask[0],0x21); -} - -static void shark_enable_8259A_irq(unsigned int irq) -{ - unsigned int mask; - if (irq<8) { - mask = ~(1 << irq); - cached_irq_mask[0] &= mask; - } else { - mask = ~(1 << (irq-8)); - cached_irq_mask[1] &= mask; - } - outb(cached_irq_mask[1],0xA1); - outb(cached_irq_mask[0],0x21); -} - -/* - * Careful! The 8259A is a fragile beast, it pretty - * much _has_ to be done exactly like this (mask it - * first, _then_ send the EOI, and the order of EOI - * to the two 8259s is important! - */ -static void shark_mask_and_ack_8259A_irq(unsigned int irq) -{ - if (irq & 8) { - cached_irq_mask[1] |= 1 << (irq-8); - inb(0xA1); /* DUMMY */ - outb(cached_irq_mask[1],0xA1); - } else { - cached_irq_mask[0] |= 1 << irq; - outb(cached_irq_mask[0],0x21); - } -} - -static void bogus_int(int irq, void *dev_id, struct pt_regs *regs) -{ - printk("Got interrupt %i!\n",irq); -} - -static struct irqaction cascade; - -static __inline__ void irq_init_irq(void) -{ - int irq; - - for (irq = 0; irq < NR_IRQS; irq++) { - irq_desc[irq].valid = 1; - irq_desc[irq].probe_ok = 1; - irq_desc[irq].mask_ack = shark_mask_and_ack_8259A_irq; - irq_desc[irq].mask = shark_disable_8259A_irq; - irq_desc[irq].unmask = shark_enable_8259A_irq; - } - - /* The PICs are initialized to level triggered and auto eoi! - * If they are set to edge triggered they lose some IRQs, - * if they are set to manual eoi they get locked up after - * a short time - */ - - /* init master interrupt controller */ - outb(0x19, 0x20); /* Start init sequence, level triggered */ - outb(0x00, 0x21); /* Vector base */ - outb(0x04, 0x21); /* Cascade (slave) on IRQ2 */ - outb(0x03, 0x21); /* Select 8086 mode , auto eoi*/ - outb(0x0A, 0x20); - /* init slave interrupt controller */ - outb(0x19, 0xA0); /* Start init sequence, level triggered */ - outb(0x08, 0xA1); /* Vector base */ - outb(0x02, 0xA1); /* Cascade (slave) on IRQ2 */ - outb(0x03, 0xA1); /* Select 8086 mode, auto eoi */ - outb(0x0A, 0xA0); - outb(cached_irq_mask[1],0xA1); - outb(cached_irq_mask[0],0x21); - //request_region(0x20,0x2,"pic1"); - //request_region(0xA0,0x2,"pic2"); - - cascade.handler = bogus_int; - cascade.flags = 0; - cascade.mask = 0; - cascade.name = "cascade"; - cascade.next = NULL; - cascade.dev_id = NULL; - setup_arm_irq(2,&cascade); - -} diff -urN linux-2.5.2-pre8/include/asm-arm/arch-shark/time.h linux/include/asm-arm/arch-shark/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-shark/time.h Thu Oct 25 13:53:55 2001 +++ linux/include/asm-arm/arch-shark/time.h Sat Jan 5 14:43:18 2002 @@ -46,7 +46,7 @@ /* * Set up timer interrupt, and return the current time in seconds. */ -static inline void setup_timer(void) +void __init time_init(void) { struct rtc_time r_time; unsigned long flags; diff -urN linux-2.5.2-pre8/include/asm-arm/arch-tbox/irq.h linux/include/asm-arm/arch-tbox/irq.h --- linux-2.5.2-pre8/include/asm-arm/arch-tbox/irq.h Mon Sep 18 15:15:23 2000 +++ linux/include/asm-arm/arch-tbox/irq.h Sat Jan 5 14:43:18 2002 @@ -10,41 +10,4 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ - -#include - #define fixup_irq(x) (x) - -extern unsigned long soft_irq_mask; - -static void tbox_mask_irq(unsigned int irq) -{ - __raw_writel(0, INTCONT + (irq << 2)); - soft_irq_mask &= ~(1<= 12 && i <= 13)) { - irq_desc[i].valid = 1; - irq_desc[i].probe_ok = 0; - irq_desc[i].mask_ack = tbox_mask_irq; - irq_desc[i].mask = tbox_mask_irq; - irq_desc[i].unmask = tbox_unmask_irq; - tbox_mask_irq(i); - } else { - irq_desc[i].valid = 0; - irq_desc[i].probe_ok = 0; - } - } -} diff -urN linux-2.5.2-pre8/include/asm-arm/arch-tbox/time.h linux/include/asm-arm/arch-tbox/time.h --- linux-2.5.2-pre8/include/asm-arm/arch-tbox/time.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/arch-tbox/time.h Sat Jan 5 14:43:18 2002 @@ -29,15 +29,8 @@ do_timer(regs); } -static inline void setup_timer (void) +void __init time_init(void) { - /* - * Default the date to 1 Jan 1970 0:0:0 - * You will have to run a time daemon to set the - * clock correctly at bootup - */ - xtime.tv_sec = mktime(1970, 1, 1, 0, 0, 0); - timer_irq.handler = timer_interrupt; setup_arm_irq(IRQ_TIMER, &timer_irq); } diff -urN linux-2.5.2-pre8/include/asm-arm/arch-tbox/vmalloc.h linux/include/asm-arm/arch-tbox/vmalloc.h --- linux-2.5.2-pre8/include/asm-arm/arch-tbox/vmalloc.h Mon Sep 18 15:15:23 2000 +++ linux/include/asm-arm/arch-tbox/vmalloc.h Sat Jan 5 14:43:18 2002 @@ -1,5 +1,5 @@ /* - * linux/include/asm-arm/arch-rpc/vmalloc.h + * linux/include/asm-arm/arch-tbox/vmalloc.h */ /* diff -urN linux-2.5.2-pre8/include/asm-arm/assembler.h linux/include/asm-arm/assembler.h --- linux-2.5.2-pre8/include/asm-arm/assembler.h Sun Aug 13 09:54:15 2000 +++ linux/include/asm-arm/assembler.h Sat Jan 5 14:43:18 2002 @@ -13,3 +13,16 @@ #include #include + +/* + * Endian independent macros for shifting bytes within registers. + */ +#ifndef __ARMEB__ +#define pull lsr +#define push lsl +#define byte(x) (x*8) +#else +#define pull lsl +#define push lsr +#define byte(x) ((3-x)*8) +#endif diff -urN linux-2.5.2-pre8/include/asm-arm/bitops.h linux/include/asm-arm/bitops.h --- linux-2.5.2-pre8/include/asm-arm/bitops.h Sat Jan 5 14:43:14 2002 +++ linux/include/asm-arm/bitops.h Sat Jan 5 14:43:18 2002 @@ -258,7 +258,7 @@ #else /* - * These are the little endian, atomic definitions. + * These are the big endian, atomic definitions. */ #define set_bit(nr,p) ATOMIC_BITOP_BE(set_bit,nr,p) #define clear_bit(nr,p) ATOMIC_BITOP_BE(clear_bit,nr,p) @@ -271,7 +271,7 @@ #define find_next_zero_bit(p,sz,off) _find_next_zero_bit_be(p,sz,off) /* - * These are the little endian, non-atomic definitions. + * These are the big endian, non-atomic definitions. */ #define __set_bit(nr,p) NONATOMIC_BITOP_BE(set_bit,nr,p) #define __clear_bit(nr,p) NONATOMIC_BITOP_BE(clear_bit,nr,p) diff -urN linux-2.5.2-pre8/include/asm-arm/checksum.h linux/include/asm-arm/checksum.h --- linux-2.5.2-pre8/include/asm-arm/checksum.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/checksum.h Sat Jan 5 14:43:18 2002 @@ -55,25 +55,24 @@ unsigned int sum, tmp1; __asm__ __volatile__( - "ldr %0, [%1], #4 @ ip_fast_csum - ldr %3, [%1], #4 - sub %2, %2, #5 - adds %0, %0, %3 - ldr %3, [%1], #4 - adcs %0, %0, %3 - ldr %3, [%1], #4 - adcs %0, %0, %3 -1: ldr %3, [%1], #4 - adcs %0, %0, %3 - tst %2, #15 - subne %2, %2, #1 - bne 1b - adc %0, %0, #0 - adds %0, %0, %0, lsl #16 - addcs %0, %0, #0x10000 - mvn %0, %0 - mov %0, %0, lsr #16 - " + "ldr %0, [%1], #4 @ ip_fast_csum \n\ + ldr %3, [%1], #4 \n\ + sub %2, %2, #5 \n\ + adds %0, %0, %3 \n\ + ldr %3, [%1], #4 \n\ + adcs %0, %0, %3 \n\ + ldr %3, [%1], #4 \n\ +1: adcs %0, %0, %3 \n\ + ldr %3, [%1], #4 \n\ + tst %2, #15 @ do this carefully \n\ + subne %2, %2, #1 @ without destroying \n\ + bne 1b @ the carry flag \n\ + adcs %0, %0, %3 \n\ + adc %0, %0, #0 \n\ + adds %0, %0, %0, lsl #16 \n\ + addcs %0, %0, #0x10000 \n\ + mvn %0, %0 \n\ + mov %0, %0, lsr #16" : "=r" (sum), "=r" (iph), "=r" (ihl), "=r" (tmp1) : "1" (iph), "2" (ihl) : "cc"); @@ -87,7 +86,7 @@ csum_fold(unsigned int sum) { __asm__( - "adds %0, %1, %1, lsl #16 @ csum_fold + "adds %0, %1, %1, lsl #16 @ csum_fold \n\ addcs %0, %0, #0x10000" : "=r" (sum) : "r" (sum) @@ -100,10 +99,10 @@ unsigned int proto, unsigned int sum) { __asm__( - "adds %0, %1, %2 @ csum_tcpudp_nofold - adcs %0, %0, %3 - adcs %0, %0, %4 - adcs %0, %0, %5 + "adds %0, %1, %2 @ csum_tcpudp_nofold \n\ + adcs %0, %0, %3 \n\ + adcs %0, %0, %4 \n\ + adcs %0, %0, %5 \n\ adc %0, %0, #0" : "=&r"(sum) : "r" (sum), "r" (daddr), "r" (saddr), "r" (ntohs(len) << 16), "Ir" (proto << 8) @@ -119,13 +118,13 @@ unsigned int proto, unsigned int sum) { __asm__( - "adds %0, %1, %2 @ csum_tcpudp_magic - adcs %0, %0, %3 - adcs %0, %0, %4 - adcs %0, %0, %5 - adc %0, %0, #0 - adds %0, %0, %0, lsl #16 - addcs %0, %0, #0x10000 + "adds %0, %1, %2 @ csum_tcpudp_magic \n\ + adcs %0, %0, %3 \n\ + adcs %0, %0, %4 \n\ + adcs %0, %0, %5 \n\ + adc %0, %0, #0 \n\ + adds %0, %0, %0, lsl #16 \n\ + addcs %0, %0, #0x10000 \n\ mvn %0, %0" : "=&r"(sum) : "r" (sum), "r" (daddr), "r" (saddr), "r" (ntohs(len)), "Ir" (proto << 8) diff -urN linux-2.5.2-pre8/include/asm-arm/cpu-multi32.h linux/include/asm-arm/cpu-multi32.h --- linux-2.5.2-pre8/include/asm-arm/cpu-multi32.h Thu Oct 11 09:04:57 2001 +++ linux/include/asm-arm/cpu-multi32.h Sat Jan 5 14:43:18 2002 @@ -122,6 +122,11 @@ */ void (*set_pte)(pte_t *ptep, pte_t pte); } pgtable; + + struct { /* other */ + void (*clear_user_page)(void *page, unsigned long u_addr); + void (*copy_user_page)(void *to, void *from, unsigned long u_addr); + } misc; } processor; extern const struct processor arm6_processor_functions; @@ -154,6 +159,9 @@ #define cpu_set_pgd(pgd) processor.pgtable.set_pgd(pgd) #define cpu_set_pmd(pmdp, pmd) processor.pgtable.set_pmd(pmdp, pmd) #define cpu_set_pte(ptep, pte) processor.pgtable.set_pte(ptep, pte) + +#define cpu_copy_user_page(to,from,uaddr) processor.misc.copy_user_page(to,from,uaddr) +#define cpu_clear_user_page(page,uaddr) processor.misc.clear_user_page(page,uaddr) #define cpu_switch_mm(pgd,tsk) cpu_set_pgd(__virt_to_phys((unsigned long)(pgd))) diff -urN linux-2.5.2-pre8/include/asm-arm/cpu-single.h linux/include/asm-arm/cpu-single.h --- linux-2.5.2-pre8/include/asm-arm/cpu-single.h Thu Oct 11 09:04:57 2001 +++ linux/include/asm-arm/cpu-single.h Sat Jan 5 14:43:18 2002 @@ -11,43 +11,40 @@ * Single CPU */ #ifdef __STDC__ -#define __cpu_fn(name,x) cpu_##name##x +#define __catify_fn(name,x) name##x #else -#define __cpu_fn(name,x) cpu_/**/name/**/x +#define __catify_fn(name,x) name/**/x #endif -#define cpu_fn(name,x) __cpu_fn(name,x) +#define __cpu_fn(name,x) __catify_fn(name,x) /* * If we are supporting multiple CPUs, then we must use a table of * function pointers for this lot. Otherwise, we can optimise the * table away. */ -#define cpu_data_abort cpu_fn(CPU_NAME,_data_abort) -#define cpu_check_bugs cpu_fn(CPU_NAME,_check_bugs) -#define cpu_proc_init cpu_fn(CPU_NAME,_proc_init) -#define cpu_proc_fin cpu_fn(CPU_NAME,_proc_fin) -#define cpu_reset cpu_fn(CPU_NAME,_reset) -#define cpu_do_idle cpu_fn(CPU_NAME,_do_idle) - -#define cpu_cache_clean_invalidate_all cpu_fn(CPU_NAME,_cache_clean_invalidate_all) -#define cpu_cache_clean_invalidate_range cpu_fn(CPU_NAME,_cache_clean_invalidate_range) -#define cpu_flush_ram_page cpu_fn(CPU_NAME,_flush_ram_page) - -#define cpu_dcache_invalidate_range cpu_fn(CPU_NAME,_dcache_invalidate_range) -#define cpu_dcache_clean_range cpu_fn(CPU_NAME,_dcache_clean_range) -#define cpu_dcache_clean_page cpu_fn(CPU_NAME,_dcache_clean_page) -#define cpu_dcache_clean_entry cpu_fn(CPU_NAME,_dcache_clean_entry) - -#define cpu_icache_invalidate_range cpu_fn(CPU_NAME,_icache_invalidate_range) -#define cpu_icache_invalidate_page cpu_fn(CPU_NAME,_icache_invalidate_page) - -#define cpu_tlb_invalidate_all cpu_fn(CPU_NAME,_tlb_invalidate_all) -#define cpu_tlb_invalidate_range cpu_fn(CPU_NAME,_tlb_invalidate_range) -#define cpu_tlb_invalidate_page cpu_fn(CPU_NAME,_tlb_invalidate_page) - -#define cpu_set_pgd cpu_fn(CPU_NAME,_set_pgd) -#define cpu_set_pmd cpu_fn(CPU_NAME,_set_pmd) -#define cpu_set_pte cpu_fn(CPU_NAME,_set_pte) +#define cpu_data_abort __cpu_fn(CPU_ABRT,_abort) +#define cpu_check_bugs __cpu_fn(CPU_NAME,_check_bugs) +#define cpu_proc_init __cpu_fn(CPU_NAME,_proc_init) +#define cpu_proc_fin __cpu_fn(CPU_NAME,_proc_fin) +#define cpu_reset __cpu_fn(CPU_NAME,_reset) +#define cpu_do_idle __cpu_fn(CPU_NAME,_do_idle) +#define cpu_cache_clean_invalidate_all __cpu_fn(CPU_NAME,_cache_clean_invalidate_all) +#define cpu_cache_clean_invalidate_range __cpu_fn(CPU_NAME,_cache_clean_invalidate_range) +#define cpu_flush_ram_page __cpu_fn(CPU_NAME,_flush_ram_page) +#define cpu_dcache_invalidate_range __cpu_fn(CPU_NAME,_dcache_invalidate_range) +#define cpu_dcache_clean_range __cpu_fn(CPU_NAME,_dcache_clean_range) +#define cpu_dcache_clean_page __cpu_fn(CPU_NAME,_dcache_clean_page) +#define cpu_dcache_clean_entry __cpu_fn(CPU_NAME,_dcache_clean_entry) +#define cpu_icache_invalidate_range __cpu_fn(CPU_NAME,_icache_invalidate_range) +#define cpu_icache_invalidate_page __cpu_fn(CPU_NAME,_icache_invalidate_page) +#define cpu_tlb_invalidate_all __cpu_fn(CPU_NAME,_tlb_invalidate_all) +#define cpu_tlb_invalidate_range __cpu_fn(CPU_NAME,_tlb_invalidate_range) +#define cpu_tlb_invalidate_page __cpu_fn(CPU_NAME,_tlb_invalidate_page) +#define cpu_set_pgd __cpu_fn(CPU_NAME,_set_pgd) +#define cpu_set_pmd __cpu_fn(CPU_NAME,_set_pmd) +#define cpu_set_pte __cpu_fn(CPU_NAME,_set_pte) +#define cpu_copy_user_page __cpu_fn(MMU_ARCH,_copy_user_page) +#define cpu_clear_user_page __cpu_fn(MMU_ARCH,_clear_user_page) #ifndef __ASSEMBLY__ @@ -83,6 +80,10 @@ extern void cpu_set_pgd(unsigned long pgd_phys); extern void cpu_set_pmd(pmd_t *pmdp, pmd_t pmd); extern void cpu_set_pte(pte_t *ptep, pte_t pte); + +extern void cpu_copy_user_page(void *to, void *from, unsigned long u_addr); +extern void cpu_clear_user_page(void *page, unsigned long u_addr); + extern volatile void cpu_reset(unsigned long addr); #define cpu_switch_mm(pgd,tsk) cpu_set_pgd(__virt_to_phys((unsigned long)(pgd))) diff -urN linux-2.5.2-pre8/include/asm-arm/hardware/clps7111.h linux/include/asm-arm/hardware/clps7111.h --- linux-2.5.2-pre8/include/asm-arm/hardware/clps7111.h Thu Apr 12 12:20:31 2001 +++ linux/include/asm-arm/hardware/clps7111.h Sat Jan 5 14:43:18 2002 @@ -27,8 +27,10 @@ #ifndef __ASSEMBLY__ #define clps_readb(off) __raw_readb(CLPS7111_BASE + (off)) +#define clps_readw(off) __raw_readw(CLPS7111_BASE + (off)) #define clps_readl(off) __raw_readl(CLPS7111_BASE + (off)) #define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off)) +#define clps_writew(val,off) __raw_writew(val, CLPS7111_BASE + (off)) #define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off)) #endif @@ -48,6 +50,7 @@ #define INTSR1 (0x0240) #define INTMR1 (0x0280) #define LCDCON (0x02c0) +#define TC1D (0x0300) #define TC2D (0x0340) #define RTCDR (0x0380) #define RTCMR (0x03c0) diff -urN linux-2.5.2-pre8/include/asm-arm/hardware/cs89712.h linux/include/asm-arm/hardware/cs89712.h --- linux-2.5.2-pre8/include/asm-arm/hardware/cs89712.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/hardware/cs89712.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,49 @@ +/* + * linux/include/asm-arm/hardware/cs89712.h + * + * This file contains the hardware definitions of the CS89712 + * additional internal registers. + * + * Copyright (C) 2001 Thomas Gleixner autronix automation + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_HARDWARE_CS89712_H +#define __ASM_HARDWARE_CS89712_H + +/* +* CS89712 additional registers +*/ + +#define PCDR 0x0002 /* Port C Data register ---------------------------- */ +#define PCDDR 0x0042 /* Port C Data Direction register ------------------ */ +#define SDCONF 0x2300 /* SDRAM Configuration register ---------------------*/ +#define SDRFPR 0x2340 /* SDRAM Refresh period register --------------------*/ + +#define SDCONF_ACTIVE (1 << 10) +#define SDCONF_CLKCTL (1 << 9) +#define SDCONF_WIDTH_4 (0 << 7) +#define SDCONF_WIDTH_8 (1 << 7) +#define SDCONF_WIDTH_16 (2 << 7) +#define SDCONF_WIDTH_32 (3 << 7) +#define SDCONF_SIZE_16 (0 << 5) +#define SDCONF_SIZE_64 (1 << 5) +#define SDCONF_SIZE_128 (2 << 5) +#define SDCONF_SIZE_256 (3 << 5) +#define SDCONF_CASLAT_2 (2) +#define SDCONF_CASLAT_3 (3) + +#endif /* __ASM_HARDWARE_CS89712_H */ diff -urN linux-2.5.2-pre8/include/asm-arm/hardware/ep7212.h linux/include/asm-arm/hardware/ep7212.h --- linux-2.5.2-pre8/include/asm-arm/hardware/ep7212.h Thu Oct 25 13:53:55 2001 +++ linux/include/asm-arm/hardware/ep7212.h Sat Jan 5 14:43:18 2002 @@ -23,8 +23,6 @@ #ifndef __ASM_HARDWARE_EP7212_H #define __ASM_HARDWARE_EP7212_H -#include - /* * define EP7212_BASE to be the base address of the region * you want to access. @@ -49,10 +47,6 @@ #define INTSR3 0x2240 #define INTMR3 0x2280 #define LEDFLSH 0x22c0 -#if defined (CONFIG_ARCH_CDB89712) -#define SDCONF 0x2300 -#define SDRFPR 0x2340 -#endif #define DAIR_DAIEN (1 << 16) #define DAIR_ECS (1 << 17) @@ -85,20 +79,5 @@ #define SYSCON3_ADCCKNSEN (1 << 4) #define SYSCON3_FASTWAKE (1 << 8) #define SYSCON3_DAIEN (1 << 9) - -#if defined (CONFIG_ARCH_CDB89712) -#define SDCONF_ACTIVE (1 << 10) -#define SDCONF_CLKCTL (1 << 9) -#define SDCONF_WIDTH_4 (0 << 7) -#define SDCONF_WIDTH_8 (1 << 7) -#define SDCONF_WIDTH_16 (2 << 7) -#define SDCONF_WIDTH_32 (3 << 7) -#define SDCONF_SIZE_16 (0 << 5) -#define SDCONF_SIZE_64 (1 << 5) -#define SDCONF_SIZE_128 (2 << 5) -#define SDCONF_SIZE_256 (3 << 5) -#define SDCONF_CASLAT_2 (2) -#define SDCONF_CASLAT_3 (3) -#endif #endif /* __ASM_HARDWARE_EP7212_H */ diff -urN linux-2.5.2-pre8/include/asm-arm/hardware/ioc.h linux/include/asm-arm/hardware/ioc.h --- linux-2.5.2-pre8/include/asm-arm/hardware/ioc.h Thu Apr 12 12:20:31 2001 +++ linux/include/asm-arm/hardware/ioc.h Sat Jan 5 14:43:18 2002 @@ -19,8 +19,8 @@ * We use __raw_base variants here so that we give the compiler the * chance to keep IOC_BASE in a register. */ -#define ioc_readb(off) __raw_base_readb(IOC_BASE, (off)) -#define ioc_writeb(val,off) __raw_base_writeb(val, IOC_BASE, (off)) +#define ioc_readb(off) __raw_readb(IOC_BASE + (off)) +#define ioc_writeb(val,off) __raw_writeb(val, IOC_BASE + (off)) #endif diff -urN linux-2.5.2-pre8/include/asm-arm/hardware/iomd.h linux/include/asm-arm/hardware/iomd.h --- linux-2.5.2-pre8/include/asm-arm/hardware/iomd.h Thu Apr 12 12:20:31 2001 +++ linux/include/asm-arm/hardware/iomd.h Sat Jan 5 14:43:18 2002 @@ -21,10 +21,10 @@ * We use __raw_base variants here so that we give the compiler the * chance to keep IOC_BASE in a register. */ -#define iomd_readb(off) __raw_base_readb(IOMD_BASE, (off)) -#define iomd_readl(off) __raw_base_readl(IOMD_BASE, (off)) -#define iomd_writeb(val,off) __raw_base_writeb(val, IOMD_BASE, (off)) -#define iomd_writel(val,off) __raw_base_writel(val, IOMD_BASE, (off)) +#define iomd_readb(off) __raw_readb(IOMD_BASE + (off)) +#define iomd_readl(off) __raw_readl(IOMD_BASE + (off)) +#define iomd_writeb(val,off) __raw_writeb(val, IOMD_BASE + (off)) +#define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off)) #endif diff -urN linux-2.5.2-pre8/include/asm-arm/hardware/linkup-l1110.h linux/include/asm-arm/hardware/linkup-l1110.h --- linux-2.5.2-pre8/include/asm-arm/hardware/linkup-l1110.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/hardware/linkup-l1110.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,48 @@ +/* +* +* Definitions for H3600 Handheld Computer +* +* Copyright 2001 Compaq Computer Corporation. +* +* Use consistent with the GNU GPL is permitted, +* provided that this copyright notice is +* preserved in its entirety in all copies and derived works. +* +* COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, +* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS +* FITNESS FOR ANY PARTICULAR PURPOSE. +* +* Author: Jamey Hicks. +* +*/ + +/* LinkUp Systems PCCard/CompactFlash Interface for SA-1100 */ + +/* PC Card Status Register */ +#define LINKUP_PRS_S1 (1 << 0) /* voltage control bits S1-S4 */ +#define LINKUP_PRS_S2 (1 << 1) +#define LINKUP_PRS_S3 (1 << 2) +#define LINKUP_PRS_S4 (1 << 3) +#define LINKUP_PRS_BVD1 (1 << 4) +#define LINKUP_PRS_BVD2 (1 << 5) +#define LINKUP_PRS_VS1 (1 << 6) +#define LINKUP_PRS_VS2 (1 << 7) +#define LINKUP_PRS_RDY (1 << 8) +#define LINKUP_PRS_CD1 (1 << 9) +#define LINKUP_PRS_CD2 (1 << 10) + +/* PC Card Command Register */ +#define LINKUP_PRC_S1 (1 << 0) +#define LINKUP_PRC_S2 (1 << 1) +#define LINKUP_PRC_S3 (1 << 2) +#define LINKUP_PRC_S4 (1 << 3) +#define LINKUP_PRC_RESET (1 << 4) +#define LINKUP_PRC_APOE (1 << 5) /* Auto Power Off Enable: clears S1-S4 when either nCD goes high */ +#define LINKUP_PRC_CFE (1 << 6) /* CompactFlash mode Enable: addresses A[10:0] only, A[25:11] high */ +#define LINKUP_PRC_SOE (1 << 7) /* signal output driver enable */ +#define LINKUP_PRC_SSP (1 << 8) /* sock select polarity: 0 for socket 0, 1 for socket 1 */ +#define LINKUP_PRC_MBZ (1 << 15) /* must be zero */ + +struct linkup_l1110 { + volatile short prc; +}; diff -urN linux-2.5.2-pre8/include/asm-arm/hardware/sa1111.h linux/include/asm-arm/hardware/sa1111.h --- linux-2.5.2-pre8/include/asm-arm/hardware/sa1111.h Wed Dec 31 16:00:00 1969 +++ linux/include/asm-arm/hardware/sa1111.h Sat Jan 5 14:43:18 2002 @@ -0,0 +1,678 @@ +/* + * linux/include/asm-arm/hardware/SA-1111.h + * + * Copyright (C) 2000 John G Dorsey + * + * This file contains definitions for the SA-1111 Companion Chip. + * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.) + * + * Macro that calculates real address for registers in the SA-1111 + */ + +#ifndef _ASM_ARCH_SA1111 +#define _ASM_ARCH_SA1111 + +#include + +/* + * The SA1111 is always located at virtual 0xf4000000, and is always + * "native" endian. + */ + +#define SA1111_VBASE 0xf4000000 + +/* Don't use these! */ +#define SA1111_p2v( x ) ((x) - SA1111_BASE + SA1111_VBASE) +#define SA1111_v2p( x ) ((x) - SA1111_VBASE + SA1111_BASE) + +#ifndef __ASSEMBLY__ + +extern struct resource sa1111_resource; +#define _SA1111(x) ((x) + sa1111_resource.start) +#endif + +/* + * 26 bits of the SA-1110 address bus are available to the SA-1111. + * Use these when feeding target addresses to the DMA engines. + */ + +#define SA1111_ADDR_WIDTH (26) +#define SA1111_ADDR_MASK ((1< +#include #include #include /* - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. + * Generic IO read/write. These perform native-endian accesses. Note + * that some architectures will want to re-define __raw_{read,write}w. */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - extern void __raw_writesb(unsigned int addr, void *data, int bytelen); extern void __raw_writesw(unsigned int addr, void *data, int wordlen); extern void __raw_writesl(unsigned int addr, void *data, int longlen); @@ -45,116 +39,85 @@ extern void __raw_readsw(unsigned int addr, void *data, int wordlen); extern void __raw_readsl(unsigned int addr, void *data, int longlen); -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -/* - * The compiler seems to be incapable of optimising constants - * properly. Spell it out to the compiler in some cases. - * These are only valid for small values of "off" (< 1<<12) - */ -#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) -#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) -#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) - -#define __raw_base_readb(base,off) __arch_base_getb(base,off) -#define __raw_base_readw(base,off) __arch_base_getw(base,off) -#define __raw_base_readl(base,off) __arch_base_getl(base,off) +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + +/* + * Bad read/write accesses... + */ +extern void __readwrite_bug(const char *fn); /* * Now, pick up the machine-defined IO definitions */ #include +#ifdef __io_pci +#warning machine class uses buggy __io_pci +#endif +#if defined(__arch_putb) || defined(__arch_putw) || defined(__arch_putl) || \ + defined(__arch_getb) || defined(__arch_getw) || defined(__arch_getl) +#warning machine class uses old __arch_putw or __arch_getw +#endif + /* - * IO definitions. We define {out,in,outs,ins}[bwl] if __io is defined - * by the machine. Otherwise, these definitions are left for the machine - * specific header files to pick up. + * IO port access primitives + * ------------------------- + * + * The ARM doesn't have special IO access instructions; all IO is memory + * mapped. Note that these are defined to perform little endian accesses + * only. Their primary purpose is to access PCI and ISA peripherals. + * + * Note that for a big endian machine, this implies that the following + * big endian mode connectivity is in place, as described by numerious + * ARM documents: + * + * PCI: D0-D7 D8-D15 D16-D23 D24-D31 + * ARM: D24-D31 D16-D23 D8-D15 D0-D7 + * + * The machine specific io.h include defines __io to translate an "IO" + * address to a memory address. * * Note that we prevent GCC re-ordering or caching values in expressions * by introducing sequence points into the in*() definitions. Note that * __raw_* do not guarantee this behaviour. */ #ifdef __io -#define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(v,__io(p)) -#define outl(v,p) __raw_writel(v,__io(p)) - -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = __raw_readw(__io(p)); __v; }) -#define inl(p) ({ unsigned int __v = __raw_readl(__io(p)); __v; }) - -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) -#define outsl(p,d,l) __raw_writesl(__io(p),d,l) - -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -#define insl(p,d,l) __raw_readsl(__io(p),d,l) +#define outb(v,p) __raw_writeb(v,__io(p)) +#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) +#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) + +#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) +#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) +#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) + +#define outsb(p,d,l) __raw_writesb(__io(p),d,l) +#define outsw(p,d,l) __raw_writesw(__io(p),d,l) +#define outsl(p,d,l) __raw_writesl(__io(p),d,l) + +#define insb(p,d,l) __raw_readsb(__io(p),d,l) +#define insw(p,d,l) __raw_readsw(__io(p),d,l) +#define insl(p,d,l) __raw_readsl(__io(p),d,l) #endif -#define outb_p(val,port) outb((val),(port)) -#define outw_p(val,port) outw((val),(port)) -#define outl_p(val,port) outl((val),(port)) -#define inb_p(port) inb((port)) -#define inw_p(port) inw((port)) -#define inl_p(port) inl((port)) - -#define outsb_p(port,from,len) outsb(port,from,len) -#define outsw_p(port,from,len) outsw(port,from,len) -#define outsl_p(port,from,len) outsl(port,from,len) -#define insb_p(port,to,len) insb(port,to,len) -#define insw_p(port,to,len) insw(port,to,len) -#define insl_p(port,to,len) insl(port,to,len) - -/* - * ioremap and friends. - * - * ioremap takes a PCI memory address, as specified in - * linux/Documentation/IO-mapping.txt. If you want a - * physical address, use __ioremap instead. - */ -extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); -extern void __iounmap(void *addr); - -/* - * Generic ioremap support. - * - * Define: - * iomem_valid_addr(off,size) - * iomem_to_phys(off) - */ -#ifdef iomem_valid_addr -#define __arch_ioremap(off,sz,nocache) \ - ({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off),_size,0); \ - _ret; \ - }) - -#define __arch_iounmap __iounmap -#endif - -#define ioremap(off,sz) __arch_ioremap((off),(sz),0) -#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) -#define iounmap(_addr) __arch_iounmap(_addr) - -/* - * DMA-consistent mapping functions. These allocate/free a region of - * uncached, unwrite-buffered mapped memory space for use with DMA - * devices. This is the "generic" version. The PCI specific version - * is in pci.h - */ -extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); -extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); -extern void consistent_sync(void *vaddr, size_t size, int rw); +#define outb_p(val,port) outb((val),(port)) +#define outw_p(val,port) outw((val),(port)) +#define outl_p(val,port) outl((val),(port)) +#define inb_p(port) inb((port)) +#define inw_p(port) inw((port)) +#define inl_p(port) inl((port)) + +#define outsb_p(port,from,len) outsb(port,from,len) +#define outsw_p(port,from,len) outsw(port,from,len) +#define outsl_p(port,from,len) outsl(port,from,len) +#define insb_p(port,to,len) insb(port,to,len) +#define insw_p(port,to,len) insw(port,to,len) +#define insl_p(port,to,len) insl(port,to,len) /* * String version of IO memory access ops: @@ -163,29 +126,31 @@ extern void _memcpy_toio(unsigned long, const void *, size_t); extern void _memset_io(unsigned long, int, size_t); -extern void __readwrite_bug(const char *fn); - /* - * If this architecture has PCI memory IO, then define the read/write - * macros. These should only be used with the cookie passed from - * ioremap. + * Memory access primitives + * ------------------------ + * + * These perform PCI memory accesses via an ioremap region. They don't + * take an address as such, but a cookie. + * + * Again, this are defined to perform little endian accesses. See the + * IO port primitives for more information. */ #ifdef __mem_pci +#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) +#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) +#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) + +#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) +#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) +#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) + +#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) +#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) +#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) -#define readb(addr) ({ unsigned int __v = __raw_readb(__mem_pci(addr)); __v; }) -#define readw(addr) ({ unsigned int __v = __raw_readw(__mem_pci(addr)); __v; }) -#define readl(addr) ({ unsigned int __v = __raw_readl(__mem_pci(addr)); __v; }) - -#define writeb(val,addr) __raw_writeb(val,__mem_pci(addr)) -#define writew(val,addr) __raw_writew(val,__mem_pci(addr)) -#define writel(val,addr) __raw_writel(val,__mem_pci(addr)) - -#define memset_io(a,b,c) _memset_io(__mem_pci(a),(b),(c)) -#define memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_pci(b),(c)) -#define memcpy_toio(a,b,c) _memcpy_toio(__mem_pci(a),(b),(c)) - -#define eth_io_copy_and_sum(a,b,c,d) \ - eth_copy_and_sum((a),__mem_pci(b),(c),(d)) +#define eth_io_copy_and_sum(s,c,l,b) \ + eth_copy_and_sum((s),__mem_pci(c),(l),(b)) static inline int check_signature(unsigned long io_addr, const unsigned char *signature, @@ -206,28 +171,20 @@ #elif !defined(readb) -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") +#define readb(c) (__readwrite_bug("readb"),0) +#define readw(c) (__readwrite_bug("readw"),0) +#define readl(c) (__readwrite_bug("readl"),0) +#define writeb(v,c) __readwrite_bug("writeb") +#define writew(v,c) __readwrite_bug("writew") +#define writel(v,c) __readwrite_bug("writel") -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") +#define eth_io_copy_and_sum(s,c,l,b) __readwrite_bug("eth_io_copy_and_sum") #define check_signature(io,sig,len) (0) #endif /* __mem_pci */ /* - * remap a physical address `phys' of size `size' with page protection `prot' - * into virtual address `from' - */ -#define io_remap_page_range(from,phys,size,prot) \ - remap_page_range(from,phys,size,prot) - - -/* * If this architecture has ISA IO, then define the isa_read/isa_write * macros. */ @@ -281,5 +238,51 @@ #define isa_check_signature(io,sig,len) (0) #endif /* __mem_isa */ + +/* + * ioremap and friends. + * + * ioremap takes a PCI memory address, as specified in + * linux/Documentation/IO-mapping.txt. + */ +extern void * __ioremap(unsigned long, size_t, unsigned long, unsigned long); +extern void __iounmap(void *addr); + +#ifndef __arch_ioremap +#define ioremap(cookie,size) __ioremap(cookie,size,0,1) +#define ioremap_nocache(cookie,size) __ioremap(cookie,size,0,1) +#define iounmap(cookie) __iounmap(cookie) +#else +#define ioremap(cookie,size) __arch_ioremap((cookie),(size),0,1) +#define ioremap_nocache(cookie,size) __arch_ioremap((cookie),(size),0,1) +#define iounmap(cookie) __arch_iounmap(cookie) +#endif + +/* + * DMA-consistent mapping functions. These allocate/free a region of + * uncached, unwrite-buffered mapped memory space for use with DMA + * devices. This is the "generic" version. The PCI specific version + * is in pci.h + */ +extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); +extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); +extern void consistent_sync(void *vaddr, size_t size, int rw); + +/* + * FIXME: I'm sure these will need to be changed for DISCONTIG + */ +/* + * Change "struct page" to physical address. + */ +#define page_to_phys(page) (PHYS_OFFSET + ((page - mem_map) << PAGE_SHIFT)) +#define page_to_bus(page) (PHYS_OFFSET + ((page - mem_map) << PAGE_SHIFT)) + +/* + * can the hardware map this into one segment or not, given no other + * constraints. + */ +#define BIOVEC_MERGEABLE(vec1, vec2) \ + ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2))) + #endif /* __KERNEL__ */ #endif /* __ASM_ARM_IO_H */ diff -urN linux-2.5.2-pre8/include/asm-arm/mach/pci.h linux/include/asm-arm/mach/pci.h --- linux-2.5.2-pre8/include/asm-arm/mach/pci.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/mach/pci.h Sat Jan 5 14:43:18 2002 @@ -7,7 +7,12 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ + +struct pci_sys_data; +struct pci_bus; + struct hw_pci { + /* START OF OLD STUFF */ /* Initialise the hardware */ void (*init)(void *); @@ -25,10 +30,55 @@ /* IRQ mapping */ int (*map_irq)(struct pci_dev *dev, u8 slot, u8 pin); + + /* END OF OLD STUFF */ + + /* NEW STUFF */ + int nr_controllers; + int (*setup)(int nr, struct pci_sys_data *); + struct pci_bus *(*scan)(int nr, struct pci_sys_data *); + void (*preinit)(void); + void (*postinit)(void); +}; + +/* + * Per-controller structure + */ +struct pci_sys_data { + int busnr; /* primary bus number */ + unsigned long mem_offset; /* bus->cpu memory mapping offset */ + unsigned long io_offset; /* bus->cpu IO mapping offset */ + struct pci_bus *bus; /* PCI bus */ + struct resource *resource[3]; /* Primary PCI bus resources */ + /* Bridge swizzling */ + u8 (*swizzle)(struct pci_dev *, u8 *); + /* IRQ mapping */ + int (*map_irq)(struct pci_dev *, u8, u8); + struct hw_pci *hw; }; -extern u8 no_swizzle(struct pci_dev *dev, u8 *pin); -extern void __init dc21285_setup_resources(struct resource **resource); -extern void __init dc21285_init(void *sysdata); +/* + * This is the standard PCI-PCI bridge swizzling algorithm. + */ +u8 pci_std_swizzle(struct pci_dev *dev, u8 *pinp); + +/* + * PCI controllers + */ +extern int iop310_setup(int nr, struct pci_sys_data *); +extern struct pci_bus *iop310_scan_bus(int nr, struct pci_sys_data *); + +extern int dc21285_setup(int nr, struct pci_sys_data *); +extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *); +extern void dc21285_preinit(void); +extern void dc21285_postinit(void); + +extern int via82c505_setup(int nr, struct pci_sys_data *); +extern struct pci_bus *via82c505_scan_bus(int nr, struct pci_sys_data *); extern void __init via82c505_init(void *sysdata); + +extern int pci_v3_setup(int nr, struct pci_sys_data *); +extern struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *); +extern void pci_v3_preinit(void); +extern void pci_v3_postinit(void); diff -urN linux-2.5.2-pre8/include/asm-arm/mach/serial_sa1100.h linux/include/asm-arm/mach/serial_sa1100.h --- linux-2.5.2-pre8/include/asm-arm/mach/serial_sa1100.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/mach/serial_sa1100.h Sat Jan 5 14:43:18 2002 @@ -18,9 +18,10 @@ */ struct sa1100_port_fns { void (*set_mctrl)(struct uart_port *, u_int); - int (*get_mctrl)(struct uart_port *); + u_int (*get_mctrl)(struct uart_port *); void (*enable_ms)(struct uart_port *); void (*pm)(struct uart_port *, u_int, u_int); + int (*set_wake)(struct uart_port *, u_int); int (*open)(struct uart_port *, struct uart_info *); void (*close)(struct uart_port *, struct uart_info *); }; diff -urN linux-2.5.2-pre8/include/asm-arm/page.h linux/include/asm-arm/page.h --- linux-2.5.2-pre8/include/asm-arm/page.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/page.h Sat Jan 5 14:43:18 2002 @@ -3,8 +3,8 @@ #include -#define PAGE_SIZE (1UL << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) +#define PAGE_SIZE (1UL << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) #ifdef __KERNEL__ #ifndef __ASSEMBLY__ @@ -14,8 +14,8 @@ #define clear_page(page) memzero((void *)(page), PAGE_SIZE) extern void copy_page(void *to, void *from); -#define clear_user_page(page, vaddr) clear_page(page) -#define copy_user_page(to, from, vaddr) copy_page(to, from) +#define clear_user_page(page, vaddr) cpu_clear_user_page(page,vaddr) +#define copy_user_page(to, from, vaddr) cpu_copy_user_page(to,from,vaddr) #ifdef STRICT_MM_TYPECHECKS /* @@ -63,10 +63,20 @@ #ifndef __ASSEMBLY__ +#ifdef CONFIG_DEBUG_BUGVERBOSE extern void __bug(const char *file, int line, void *data); +/* give file/line information */ #define BUG() __bug(__FILE__, __LINE__, NULL) #define PAGE_BUG(page) __bug(__FILE__, __LINE__, page) + +#else + +/* these just cause an oops */ +#define BUG() (*(int *)0 = 0) +#define PAGE_BUG(page) (*(int *)0 = 0) + +#endif /* Pure 2^n version of get_order */ static inline int get_order(unsigned long size) diff -urN linux-2.5.2-pre8/include/asm-arm/pci.h linux/include/asm-arm/pci.h --- linux-2.5.2-pre8/include/asm-arm/pci.h Fri Nov 9 14:11:15 2001 +++ linux/include/asm-arm/pci.h Sat Jan 5 14:43:18 2002 @@ -3,7 +3,14 @@ #ifdef __KERNEL__ +#include /* bah! */ + #include +#include +#include +#include + +struct pci_dev; static inline void pcibios_set_master(struct pci_dev *dev) { @@ -15,10 +22,11 @@ /* We don't do dynamic PCI IRQ allocation */ } -#include -#include - -struct pci_dev; +/* The PCI address space does equal the physical memory + * address space. The networking and block device layers use + * this boolean for bounce buffer decisions. + */ +#define PCI_DMA_BUS_IS_PHYS (0) /* Allocate and map kernel buffer using consistent mode DMA for a device. * hwdev should be valid struct pci_dev pointer for PCI devices, @@ -108,8 +116,20 @@ int i; for (i = 0; i < nents; i++, sg++) { - consistent_sync(sg->address, sg->length, direction); - sg->dma_address = virt_to_bus(sg->address); + char *virt; + if (sg->address && sg->page) + BUG(); + else if (!sg->address && !sg->page) + BUG(); + + if (sg->address) { + sg->dma_address = virt_to_bus(sg->address); + virt = sg->address; + } else { + sg->dma_address = page_to_bus(sg->page) + sg->offset; + virt = page_address(sg->page) + sg->offset; + } + consistent_sync(virt, sg->length, direction); } return nents; @@ -151,8 +171,15 @@ { int i; - for (i = 0; i < nelems; i++, sg++) - consistent_sync(sg->address, sg->length, direction); + for (i = 0; i < nelems; i++, sg++) { + char *virt; + + if (sg->address) + virt = sg->address; + else + virt = page_address(sg->page) + sg->offset; + consistent_sync(virt, sg->length, direction); + } } /* Return whether the given PCI device DMA address mask can diff -urN linux-2.5.2-pre8/include/asm-arm/pgtable.h linux/include/asm-arm/pgtable.h --- linux-2.5.2-pre8/include/asm-arm/pgtable.h Thu Oct 11 09:04:57 2001 +++ linux/include/asm-arm/pgtable.h Sat Jan 5 14:43:18 2002 @@ -12,6 +12,7 @@ #include #include +#include #include /* @@ -176,6 +177,13 @@ #include extern void pgtable_cache_init(void); + +/* + * remap a physical address `phys' of size `size' with page protection `prot' + * into virtual address `from' + */ +#define io_remap_page_range(from,phys,size,prot) \ + remap_page_range(from,phys,size,prot) #endif /* !__ASSEMBLY__ */ diff -urN linux-2.5.2-pre8/include/asm-arm/proc-armo/ptrace.h linux/include/asm-arm/proc-armo/ptrace.h --- linux-2.5.2-pre8/include/asm-arm/proc-armo/ptrace.h Thu Apr 12 12:20:31 2001 +++ linux/include/asm-arm/proc-armo/ptrace.h Sat Jan 5 14:43:18 2002 @@ -10,21 +10,21 @@ #ifndef __ASM_PROC_PTRACE_H #define __ASM_PROC_PTRACE_H -#define USR26_MODE 0x00 -#define FIQ26_MODE 0x01 -#define IRQ26_MODE 0x02 -#define SVC26_MODE 0x03 +#define USR26_MODE 0x00000000 +#define FIQ26_MODE 0x00000001 +#define IRQ26_MODE 0x00000002 +#define SVC26_MODE 0x00000003 #define USR_MODE USR26_MODE #define FIQ_MODE FIQ26_MODE #define IRQ_MODE IRQ26_MODE #define SVC_MODE SVC26_MODE -#define MODE_MASK 0x03 -#define F_BIT (1 << 26) -#define I_BIT (1 << 27) -#define CC_V_BIT (1 << 28) -#define CC_C_BIT (1 << 29) -#define CC_Z_BIT (1 << 30) -#define CC_N_BIT (1 << 31) +#define MODE_MASK 0x00000003 +#define PSR_F_BIT 0x04000000 +#define PSR_I_BIT 0x08000000 +#define PSR_V_BIT 0x10000000 +#define PSR_C_BIT 0x20000000 +#define PSR_Z_BIT 0x40000000 +#define PSR_N_BIT 0x80000000 #define PCMASK 0xfc000003 #ifndef __ASSEMBLY__ @@ -65,13 +65,13 @@ #define thumb_mode(regs) (0) #define interrupts_enabled(regs) \ - (!((regs)->ARM_pc & I_BIT)) + (!((regs)->ARM_pc & PSR_I_BIT)) #define fast_interrupts_enabled(regs) \ - (!((regs)->ARM_pc & F_BIT)) + (!((regs)->ARM_pc & PSR_F_BIT)) #define condition_codes(regs) \ - ((regs)->ARM_pc & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT)) + ((regs)->ARM_pc & (PSR_V_BIT|PSR_C_BIT|PSR_Z_BIT|PSR_N_BIT)) /* Are the current registers suitable for user mode? * (used to maintain security in signal handlers) @@ -79,13 +79,13 @@ static inline int valid_user_regs(struct pt_regs *regs) { if (user_mode(regs) && - (regs->ARM_pc & (F_BIT | I_BIT)) == 0) + (regs->ARM_pc & (PSR_F_BIT | PSR_I_BIT)) == 0) return 1; /* * force it to be something sensible */ - regs->ARM_pc &= ~(MODE_MASK | F_BIT | I_BIT); + regs->ARM_pc &= ~(MODE_MASK | PSR_F_BIT | PSR_I_BIT); return 0; } diff -urN linux-2.5.2-pre8/include/asm-arm/proc-armv/assembler.h linux/include/asm-arm/proc-armv/assembler.h --- linux-2.5.2-pre8/include/asm-arm/proc-armv/assembler.h Mon Sep 18 15:15:24 2000 +++ linux/include/asm-arm/proc-armv/assembler.h Sat Jan 5 14:43:18 2002 @@ -40,7 +40,7 @@ */ .macro save_and_disable_irqs, oldcpsr, temp mrs \oldcpsr, cpsr - mov \temp, #I_BIT | MODE_SVC + mov \temp, #PSR_I_BIT | MODE_SVC msr cpsr_c, \temp .endm diff -urN linux-2.5.2-pre8/include/asm-arm/proc-armv/cache.h linux/include/asm-arm/proc-armv/cache.h --- linux-2.5.2-pre8/include/asm-arm/proc-armv/cache.h Thu Oct 25 13:53:55 2001 +++ linux/include/asm-arm/proc-armv/cache.h Sat Jan 5 14:43:18 2002 @@ -44,13 +44,13 @@ #define flush_cache_range(_mm,_start,_end) \ do { \ - if ((_mm) == current->mm) \ + if ((_mm) == current->active_mm) \ cpu_cache_clean_invalidate_range((_start), (_end), 1); \ } while (0) #define flush_cache_page(_vma,_vmaddr) \ do { \ - if ((_vma)->vm_mm == current->mm) { \ + if ((_vma)->vm_mm == current->active_mm) { \ cpu_cache_clean_invalidate_range((_vmaddr), \ (_vmaddr) + PAGE_SIZE, \ ((_vma)->vm_flags & VM_EXEC)); \ @@ -62,36 +62,68 @@ * in the cache for this page. This does not invalidate either I or D caches. * * Called from: - * 1. mm/filemap.c:filemap_nopage - * 2. mm/filemap.c:filemap_nopage - * [via do_no_page - ok] - * - * 3. mm/memory.c:break_cow - * [copy_cow_page doesn't do anything to the cache; insufficient cache - * handling. Need to add flush_dcache_page() here] - * - * 4. mm/memory.c:do_swap_page - * [read_swap_cache_async doesn't do anything to the cache: insufficient - * cache handling. Need to add flush_dcache_page() here] - * - * 5. mm/memory.c:do_anonymous_page - * [zero page, never written by kernel - ok] - * - * 6. mm/memory.c:do_no_page - * [we will be calling update_mmu_cache, which will catch on PG_dcache_dirty] - * - * 7. mm/shmem.c:shmem_nopage - * 8. mm/shmem.c:shmem_nopage - * [via do_no_page - ok] - * - * 9. fs/exec.c:put_dirty_page - * [we call flush_dcache_page prior to this, which will flush out the - * kernel virtual addresses from the dcache - ok] + * 1. fs/exec.c:put_dirty_page - ok + * - page came from alloc_page(), so page->mapping = NULL. + * - flush_dcache_page called immediately prior. + * + * 2. kernel/ptrace.c:access_one_page - flush_icache_page + * - flush_cache_page takes care of the user space side of the mapping. + * - page is either a page cache page (with page->mapping set, and + * hence page->mapping->i_mmap{,shared} also set) or an anonymous + * page. I think this is ok. + * + * 3. kernel/ptrace.c:access_one_page - bad + * - flush_cache_page takes care of the user space side of the mapping. + * - no apparant cache protection, reading the kernel virtual alias + * + * 4. mm/filemap.c:filemap_no_page - ok + * - add_to_page_cache_* clears PG_arch_1. + * - page->mapping != NULL. + * - i_mmap or i_mmap_shared will be non-null if mmap'd + * - called from (8). + * + * 5. mm/memory.c:break_cow,do_wp_page - {copy,clear}_user_page + * - need to ensure that copy_cow_page has pushed all data from the dcache + * to the page. + * - calls + * - clear_user_highpage -> clear_user_page + * - copy_user_highpage -> copy_user_page + * + * 6. mm/memory.c:do_swap_page - flush_icache_page + * - flush_icache_page called afterwards - if flush_icache_page does the + * same as flush_dcache_page, update_mmu_cache will do the work for us. + * - update_mmu_cache called. + * + * 7. mm/memory.c:do_anonymous_page - {copy,clear}_user_page + * - calls clear_user_highpage. See (5) + * + * 8. mm/memory.c:do_no_page - flush_icache_page + * - flush_icache_page called afterwards - if flush_icache_page does the + * same as flush_dcache_page, update_mmu_cache will do the work for us. + * - update_mmu_cache called. + * - When we place a user mapping, we will call update_mmu_cache, + * which will catch PG_arch_1 set. + * + * 9. mm/shmem.c:shmem_no_page - ok + * - shmem_get_page clears PG_arch_1, as does add_to_page_cache (duplicate) + * - page->mapping != NULL. + * - i_mmap or i_mmap_shared will be non-null if mmap'd + * - called from (8). + * + * 10. mm/swapfile.c:try_to_unuse - bad + * - this looks really dodgy - we're putting pages from the swap cache + * straight into processes, and the only cache handling appears to + * be flush_page_to_ram. */ +#define flush_page_to_ram_ok +#ifdef flush_page_to_ram_ok +#define flush_page_to_ram(page) do { } while (0) +#else static __inline__ void flush_page_to_ram(struct page *page) { cpu_flush_ram_page(page_address(page)); } +#endif /* * D cache only @@ -101,6 +133,8 @@ #define clean_dcache_range(_s,_e) cpu_dcache_clean_range((_s),(_e)) #define flush_dcache_range(_s,_e) cpu_cache_clean_invalidate_range((_s),(_e),0) +#define mapping_mapped(map) ((map)->i_mmap || (map)->i_mmap_shared) + /* * flush_dcache_page is used when the kernel has written to the page * cache page at virtual address page->virtual. @@ -116,8 +150,7 @@ */ static inline void flush_dcache_page(struct page *page) { - if (page->mapping && !(page->mapping->i_mmap) && - !(page->mapping->i_mmap_shared)) + if (page->mapping && !mapping_mapped(page->mapping)) set_bit(PG_dcache_dirty, &page->flags); else { unsigned long virt = (unsigned long)page_address(page); @@ -125,6 +158,30 @@ } } +/* + * flush_icache_page makes the kernel page address consistent with the + * user space mappings. The functionality is the same as flush_dcache_page, + * except we can do an optimisation and only clean the caches here if + * vma->vm_mm == current->active_mm. + * + * This function is misnamed IMHO. There are three places where it + * is called, each of which is preceded immediately by a call to + * flush_page_to_ram: + */ +#ifdef flush_page_to_ram_ok +static inline void flush_icache_page(struct vm_area_struct *vma, struct page *page) +{ + if (page->mapping && !mapping_mapped(page->mapping)) + set_bit(PG_dcache_dirty, &page->flags); + else if (vma->vm_mm == current->active_mm) { + unsigned long virt = (unsigned long)page_address(page); + cpu_cache_clean_invalidate_range(virt, virt + PAGE_SIZE, 0); + } +} +#else +#define flush_icache_page(vma,pg) do { } while (0) +#endif + #define clean_dcache_entry(_s) cpu_dcache_clean_entry((unsigned long)(_s)) /* @@ -141,32 +198,6 @@ do { \ cpu_icache_invalidate_range((_s), (_e)); \ } while (0) - -/* - * This function is misnamed IMHO. There are three places where it - * is called, each of which is preceded immediately by a call to - * flush_page_to_ram: - * - * 1. kernel/ptrace.c:access_one_page - * called after we have written to the kernel view of a user page. - * The user page has been expundged from the cache by flush_cache_page. - * [we don't need to do anything here if we add a call to - * flush_dcache_page] - * - * 2. mm/memory.c:do_swap_page - * called after we have (possibly) written to the kernel view of a - * user page, which has previously been removed (ie, has been through - * the swap cache). - * [if the flush_page_to_ram() conditions are satisfied, then ok] - * - * 3. mm/memory.c:do_no_page - * [if the flush_page_to_ram() conditions are satisfied, then ok] - * - * Invalidating the icache at the kernels virtual page isn't really - * going to do us much good, since we wouldn't have executed any - * instructions there. - */ -#define flush_icache_page(vma,pg) do { } while (0) /* * Old ARM MEMC stuff. This supports the reversed mapping handling that diff -urN linux-2.5.2-pre8/include/asm-arm/proc-armv/pgalloc.h linux/include/asm-arm/proc-armv/pgalloc.h --- linux-2.5.2-pre8/include/asm-arm/proc-armv/pgalloc.h Thu Apr 12 12:20:31 2001 +++ linux/include/asm-arm/proc-armv/pgalloc.h Sat Jan 5 14:43:18 2002 @@ -46,13 +46,12 @@ * If 'mm' is the init tasks mm, then we are doing a vmalloc, and we * need to set stuff up correctly for it. */ -#define pmd_populate(mm,pmdp,pte) \ - do { \ - unsigned long __prot; \ - if (mm == &init_mm) \ - __prot = _PAGE_KERNEL_TABLE; \ - else \ - __prot = _PAGE_USER_TABLE; \ - set_pmd(pmdp, __mk_pmd(pte, __prot)); \ +#define pmd_populate(mm,pmdp,pte) \ + do { \ + unsigned long __prot; \ + if (mm == &init_mm) \ + __prot = _PAGE_KERNEL_TABLE; \ + else \ + __prot = _PAGE_USER_TABLE; \ + set_pmd(pmdp, __mk_pmd(pte, __prot)); \ } while (0) - diff -urN linux-2.5.2-pre8/include/asm-arm/proc-armv/pgtable.h linux/include/asm-arm/proc-armv/pgtable.h --- linux-2.5.2-pre8/include/asm-arm/proc-armv/pgtable.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/proc-armv/pgtable.h Sat Jan 5 14:43:18 2002 @@ -15,9 +15,6 @@ #ifndef __ASM_PROC_PGTABLE_H #define __ASM_PROC_PGTABLE_H -#include -#include - /* * entries per page directory level: they are two-level, so * we don't really have any PMD directory. @@ -26,27 +23,91 @@ #define PTRS_PER_PMD 1 #define PTRS_PER_PGD 4096 -/**************** -* PMD functions * -****************/ - -/* PMD types (actually level 1 descriptor) */ -#define PMD_TYPE_MASK 0x0003 -#define PMD_TYPE_FAULT 0x0000 -#define PMD_TYPE_TABLE 0x0001 -#define PMD_TYPE_SECT 0x0002 -#define PMD_UPDATABLE 0x0010 -#define PMD_SECT_CACHEABLE 0x0008 -#define PMD_SECT_BUFFERABLE 0x0004 -#define PMD_SECT_AP_WRITE 0x0400 -#define PMD_SECT_AP_READ 0x0800 +/* + * Hardware page table definitions. + * + * + Level 1 descriptor (PMD) + * - common + */ +#define PMD_TYPE_MASK (3 << 0) +#define PMD_TYPE_FAULT (0 << 0) +#define PMD_TYPE_TABLE (1 << 0) +#define PMD_TYPE_SECT (2 << 0) +#define PMD_UPDATABLE (1 << 4) #define PMD_DOMAIN(x) ((x) << 5) +#define PMD_PROTECTION (1 << 9) /* v5 */ +/* + * - section + */ +#define PMD_SECT_BUFFERABLE (1 << 2) +#define PMD_SECT_CACHEABLE (1 << 3) +#define PMD_SECT_AP_WRITE (1 << 10) +#define PMD_SECT_AP_READ (1 << 11) +#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */ +/* + * - coarse table (not used) + */ + +/* + * + Level 2 descriptor (PTE) + * - common + */ +#define PTE_TYPE_MASK (3 << 0) +#define PTE_TYPE_FAULT (0 << 0) +#define PTE_TYPE_LARGE (1 << 0) +#define PTE_TYPE_SMALL (2 << 0) +#define PTE_TYPE_EXT (3 << 0) /* v5 */ +#define PTE_BUFFERABLE (1 << 2) +#define PTE_CACHEABLE (1 << 3) + +/* + * - extended small page/tiny page + */ +#define PTE_EXT_AP_UNO_SRO (0 << 4) +#define PTE_EXT_AP_UNO_SRW (1 << 4) +#define PTE_EXT_AP_URO_SRW (2 << 4) +#define PTE_EXT_AP_URW_SRW (3 << 4) +#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ + +/* + * - small page + */ +#define PTE_SMALL_AP_UNO_SRO (0x00 << 4) +#define PTE_SMALL_AP_UNO_SRW (0x55 << 4) +#define PTE_SMALL_AP_URO_SRW (0xaa << 4) +#define PTE_SMALL_AP_URW_SRW (0xff << 4) +#define PTE_AP_READ PTE_SMALL_AP_URO_SRW +#define PTE_AP_WRITE PTE_SMALL_AP_UNO_SRW + +/* + * "Linux" PTE definitions. + * + * We keep two sets of PTEs - the hardware and the linux version. + * This allows greater flexibility in the way we map the Linux bits + * onto the hardware tables, and allows us to have YOUNG and DIRTY + * bits. + * + * The PTE table pointer refers to the hardware entries; the "Linux" + * entries are stored 1024 bytes below. + */ +#define L_PTE_PRESENT (1 << 0) +#define L_PTE_YOUNG (1 << 1) +#define L_PTE_BUFFERABLE (1 << 2) /* matches PTE */ +#define L_PTE_CACHEABLE (1 << 3) /* matches PTE */ +#define L_PTE_USER (1 << 4) +#define L_PTE_WRITE (1 << 5) +#define L_PTE_EXEC (1 << 6) +#define L_PTE_DIRTY (1 << 7) + +#ifndef __ASSEMBLY__ + +#include #define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_DOMAIN(DOMAIN_USER)) #define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_DOMAIN(DOMAIN_KERNEL)) #define pmd_bad(pmd) (pmd_val(pmd) & 2) -#define set_pmd(pmdp,pmd) cpu_set_pmd(pmdp,pmd) +#define set_pmd(pmdp,pmd) cpu_set_pmd(pmdp, pmd) static inline pmd_t __mk_pmd(pte_t *ptep, unsigned long prot) { @@ -75,49 +136,8 @@ return __phys_to_virt(ptr); } -/**************** -* PTE functions * -****************/ - -/* PTE types (actually level 2 descriptor) */ -#define PTE_TYPE_MASK 0x0003 -#define PTE_TYPE_FAULT 0x0000 -#define PTE_TYPE_LARGE 0x0001 -#define PTE_TYPE_SMALL 0x0002 -#define PTE_AP_READ 0x0aa0 -#define PTE_AP_WRITE 0x0550 -#define PTE_CACHEABLE 0x0008 -#define PTE_BUFFERABLE 0x0004 - #define set_pte(ptep, pte) cpu_set_pte(ptep,pte) -/* We now keep two sets of ptes - the physical and the linux version. - * This gives us many advantages, and allows us greater flexibility. - * - * The Linux pte's contain: - * bit meaning - * 0 page present - * 1 young - * 2 bufferable - matches physical pte - * 3 cacheable - matches physical pte - * 4 user - * 5 write - * 6 execute - * 7 dirty - * 8-11 unused - * 12-31 virtual page address - * - * These are stored at the pte pointer; the physical PTE is at -1024bytes - */ -#define L_PTE_PRESENT (1 << 0) -#define L_PTE_YOUNG (1 << 1) -#define L_PTE_BUFFERABLE (1 << 2) -#define L_PTE_CACHEABLE (1 << 3) -#define L_PTE_USER (1 << 4) -#define L_PTE_WRITE (1 << 5) -#define L_PTE_EXEC (1 << 6) -#define L_PTE_DIRTY (1 << 7) - /* * The following macros handle the cache and bufferable bits... */ @@ -162,5 +182,7 @@ * Mark the prot value as uncacheable and unbufferable. */ #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) & ~(L_PTE_CACHEABLE | L_PTE_BUFFERABLE)) + +#endif /* __ASSEMBLY__ */ #endif /* __ASM_PROC_PGTABLE_H */ diff -urN linux-2.5.2-pre8/include/asm-arm/proc-armv/ptrace.h linux/include/asm-arm/proc-armv/ptrace.h --- linux-2.5.2-pre8/include/asm-arm/proc-armv/ptrace.h Mon Nov 27 17:07:59 2000 +++ linux/include/asm-arm/proc-armv/ptrace.h Sat Jan 5 14:43:18 2002 @@ -12,27 +12,51 @@ #include -#define USR26_MODE 0x00 -#define FIQ26_MODE 0x01 -#define IRQ26_MODE 0x02 -#define SVC26_MODE 0x03 -#define USR_MODE 0x10 -#define FIQ_MODE 0x11 -#define IRQ_MODE 0x12 -#define SVC_MODE 0x13 -#define ABT_MODE 0x17 -#define UND_MODE 0x1b -#define SYSTEM_MODE 0x1f -#define MODE_MASK 0x1f -#define T_BIT 0x20 -#define F_BIT 0x40 -#define I_BIT 0x80 -#define CC_V_BIT (1 << 28) -#define CC_C_BIT (1 << 29) -#define CC_Z_BIT (1 << 30) -#define CC_N_BIT (1 << 31) +/* + * PSR bits + */ +#define USR26_MODE 0x00000000 +#define FIQ26_MODE 0x00000001 +#define IRQ26_MODE 0x00000002 +#define SVC26_MODE 0x00000003 +#define USR_MODE 0x00000010 +#define FIQ_MODE 0x00000011 +#define IRQ_MODE 0x00000012 +#define SVC_MODE 0x00000013 +#define ABT_MODE 0x00000017 +#define UND_MODE 0x0000001b +#define SYSTEM_MODE 0x0000001f +#define MODE32_BIT 0x00000010 +#define MODE_MASK 0x0000001f +#define PSR_T_BIT 0x00000020 +#define PSR_F_BIT 0x00000040 +#define PSR_I_BIT 0x00000080 +#define PSR_J_BIT 0x01000000 +#define PSR_V_BIT 0x10000000 +#define PSR_C_BIT 0x20000000 +#define PSR_Z_BIT 0x40000000 +#define PSR_N_BIT 0x80000000 #define PCMASK 0 +/* + * CR1 bits + */ +#define CR1_M 0x00000001 /* MMU */ +#define CR1_A 0x00000002 /* Alignment fault */ +#define CR1_C 0x00000004 /* Dcache */ +#define CR1_W 0x00000008 /* Write buffer */ +#define CR1_P 0x00000010 /* Prog32 */ +#define CR1_D 0x00000020 /* Data32 */ +#define CR1_L 0x00000040 /* Late abort */ +#define CR1_B 0x00000080 /* Big endian */ +#define CR1_S 0x00000100 /* System protection */ +#define CR1_R 0x00000200 /* ROM protection */ +#define CR1_F 0x00000400 +#define CR1_Z 0x00000800 /* BTB enable */ +#define CR1_I 0x00001000 /* Icache */ +#define CR1_V 0x00002000 /* Vector relocation */ +#define CR1_RR 0x00004000 /* Round Robin */ + #ifndef __ASSEMBLY__ /* this struct defines the way the registers are stored on the @@ -68,7 +92,7 @@ #ifdef CONFIG_ARM_THUMB #define thumb_mode(regs) \ - (((regs)->ARM_cpsr & T_BIT)) + (((regs)->ARM_cpsr & PSR_T_BIT)) #else #define thumb_mode(regs) (0) #endif @@ -77,27 +101,27 @@ ((regs)->ARM_cpsr & MODE_MASK) #define interrupts_enabled(regs) \ - (!((regs)->ARM_cpsr & I_BIT)) + (!((regs)->ARM_cpsr & PSR_I_BIT)) #define fast_interrupts_enabled(regs) \ - (!((regs)->ARM_cpsr & F_BIT)) + (!((regs)->ARM_cpsr & PSR_F_BIT)) #define condition_codes(regs) \ - ((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT)) + ((regs)->ARM_cpsr & (PSR_V_BIT|PSR_C_BIT|PSR_Z_BIT|PSR_N_BIT)) /* Are the current registers suitable for user mode? * (used to maintain security in signal handlers) */ static inline int valid_user_regs(struct pt_regs *regs) { - if ((regs->ARM_cpsr & 0xf) == 0 && - (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0) + if (user_mode(regs) && + (regs->ARM_cpsr & (PSR_F_BIT|PSR_I_BIT)) == 0) return 1; /* * Force CPSR to something logical... */ - regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10); + regs->ARM_cpsr &= (PSR_V_BIT|PSR_C_BIT|PSR_Z_BIT|PSR_N_BIT|MODE32_BIT); return 0; } diff -urN linux-2.5.2-pre8/include/asm-arm/proc-armv/uaccess.h linux/include/asm-arm/proc-armv/uaccess.h --- linux-2.5.2-pre8/include/asm-arm/proc-armv/uaccess.h Thu Oct 25 13:53:55 2001 +++ linux/include/asm-arm/proc-armv/uaccess.h Sat Jan 5 14:43:18 2002 @@ -54,6 +54,7 @@ : "=r" (err) \ : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err)) +#ifndef __ARMEB__ #define __put_user_asm_half(x,addr,err) \ ({ \ unsigned long __temp = (unsigned long)(x); \ @@ -61,6 +62,15 @@ __put_user_asm_byte(__temp, __ptr, err); \ __put_user_asm_byte(__temp >> 8, __ptr + 1, err); \ }) +#else +#define __put_user_asm_half(x,addr,err) \ +({ \ + unsigned long __temp = (unsigned long)(x); \ + unsigned long __ptr = (unsigned long)(addr); \ + __put_user_asm_byte(__temp >> 8, __ptr, err); \ + __put_user_asm_byte(__temp, __ptr + 1, err); \ +}) +#endif #define __put_user_asm_word(x,addr,err) \ __asm__ __volatile__( \ @@ -95,6 +105,7 @@ : "=r" (err), "=&r" (x) \ : "r" (addr), "i" (-EFAULT), "0" (err)) +#ifndef __ARMEB__ #define __get_user_asm_half(x,addr,err) \ ({ \ unsigned long __b1, __b2, __ptr = (unsigned long)addr; \ @@ -102,7 +113,15 @@ __get_user_asm_byte(__b2, __ptr + 1, err); \ (x) = __b1 | (__b2 << 8); \ }) - +#else +#define __get_user_asm_half(x,addr,err) \ +({ \ + unsigned long __b1, __b2; \ + __get_user_asm_byte(__b1, addr, err); \ + __get_user_asm_byte(__b2, (int)(addr) + 1, err); \ + (x) = (__b1 << 8) | __b2; \ +}) +#endif #define __get_user_asm_word(x,addr,err) \ __asm__ __volatile__( \ diff -urN linux-2.5.2-pre8/include/asm-arm/proc-fns.h linux/include/asm-arm/proc-fns.h --- linux-2.5.2-pre8/include/asm-arm/proc-fns.h Fri Nov 9 14:11:15 2001 +++ linux/include/asm-arm/proc-fns.h Sat Jan 5 14:43:18 2002 @@ -26,6 +26,12 @@ # define MULTI_CPU #endif +/* + * CPU_NAME - the prefix for CPU related functions + * CPU_ABRT - the prefix for the CPU abort decoding function + * MMU_ARCH - the prefix for copy_user_page/clear_user_page + */ + #ifdef CONFIG_CPU_32 # define CPU_INCLUDE_NAME "asm/cpu-multi32.h" # ifdef CONFIG_CPU_ARM610 @@ -33,7 +39,9 @@ # undef MULTI_CPU # define MULTI_CPU # else -# define CPU_NAME arm6 +# define CPU_NAME cpu_arm6 +# define CPU_ABRT cpu_arm6 +# define MMU_ARCH armv3 # endif # endif # ifdef CONFIG_CPU_ARM710 @@ -41,7 +49,9 @@ # undef MULTI_CPU # define MULTI_CPU # else -# define CPU_NAME arm7 +# define CPU_NAME cpu_arm7 +# define CPU_ABRT cpu_arm7 +# define MMU_ARCH armv3 # endif # endif # ifdef CONFIG_CPU_ARM720T @@ -49,7 +59,9 @@ # undef MULTI_CPU # define MULTI_CPU # else -# define CPU_NAME arm720 +# define CPU_NAME cpu_arm720 +# define CPU_ABRT armv4t_late +# define MMU_ARCH armv4 # endif # endif # ifdef CONFIG_CPU_ARM920T @@ -57,7 +69,19 @@ # undef MULTI_CPU # define MULTI_CPU # else -# define CPU_NAME arm920 +# define CPU_NAME cpu_arm920 +# define CPU_ABRT armv4t_early +# define MMU_ARCH armv4 +# endif +# endif +# ifdef CONFIG_CPU_ARM922T +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm922 +# define CPU_ABRT armv4t_early +# define MMU_ARCH armv4 # endif # endif # ifdef CONFIG_CPU_ARM926T @@ -65,7 +89,9 @@ # undef MULTI_CPU # define MULTI_CPU # else -# define CPU_NAME arm926 +# define CPU_NAME cpu_arm926 +# define CPU_ABRT armv5ej_early +# define MMU_ARCH armv4 # endif # endif # ifdef CONFIG_CPU_SA110 @@ -73,7 +99,9 @@ # undef MULTI_CPU # define MULTI_CPU # else -# define CPU_NAME sa110 +# define CPU_NAME cpu_sa110 +# define CPU_ABRT armv4_early +# define MMU_ARCH armv4 # endif # endif # ifdef CONFIG_CPU_SA1100 @@ -81,7 +109,29 @@ # undef MULTI_CPU # define MULTI_CPU # else -# define CPU_NAME sa1100 +# define CPU_NAME cpu_sa1100 +# define CPU_ABRT armv4_early +# define MMU_ARCH armv4_mc +# endif +# endif +# ifdef CONFIG_CPU_ARM1020 +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_arm1020 +# define CPU_ABRT armv4t_early +# define MMU_ARCH armv4 +# endif +# endif +# ifdef CONFIG_CPU_XSCALE +# ifdef CPU_NAME +# undef MULTI_CPU +# define MULTI_CPU +# else +# define CPU_NAME cpu_xscale +# define CPU_ABRT armv4t_early +# define MMU_ARCH armv5te # endif # endif #endif diff -urN linux-2.5.2-pre8/include/asm-arm/processor.h linux/include/asm-arm/processor.h --- linux-2.5.2-pre8/include/asm-arm/processor.h Thu Oct 11 09:04:57 2001 +++ linux/include/asm-arm/processor.h Sat Jan 5 14:43:18 2002 @@ -68,13 +68,6 @@ EXTRA_THREAD_STRUCT }; -#define INIT_MMAP { \ - vm_mm: &init_mm, \ - vm_page_prot: PAGE_SHARED, \ - vm_flags: VM_READ | VM_WRITE | VM_EXEC, \ - vm_avl_height: 1, \ -} - #define INIT_THREAD { \ refcount: ATOMIC_INIT(1), \ EXTRA_THREAD_STRUCT_INIT \ diff -urN linux-2.5.2-pre8/include/asm-arm/scatterlist.h linux/include/asm-arm/scatterlist.h --- linux-2.5.2-pre8/include/asm-arm/scatterlist.h Fri Oct 12 15:35:54 2001 +++ linux/include/asm-arm/scatterlist.h Sat Jan 5 14:43:18 2002 @@ -5,8 +5,11 @@ struct scatterlist { char *address; /* virtual address */ + struct page *page; /* Location for highmem page, if any */ + unsigned int offset; /* for highmem, page offset */ dma_addr_t dma_address; /* dma address */ unsigned int length; /* length */ + char *__address; /* for set_dma_addr */ }; /* diff -urN linux-2.5.2-pre8/include/asm-arm/types.h linux/include/asm-arm/types.h --- linux-2.5.2-pre8/include/asm-arm/types.h Sun Feb 6 17:45:26 2000 +++ linux/include/asm-arm/types.h Sat Jan 5 14:43:18 2002 @@ -44,6 +44,7 @@ /* Dma addresses are 32-bits wide. */ typedef u32 dma_addr_t; +typedef u32 dma64_addr_t; #endif /* __KERNEL__ */ diff -urN linux-2.5.2-pre8/include/asm-arm/unaligned.h linux/include/asm-arm/unaligned.h --- linux-2.5.2-pre8/include/asm-arm/unaligned.h Sun Aug 13 09:54:15 2000 +++ linux/include/asm-arm/unaligned.h Sat Jan 5 14:43:18 2002 @@ -39,24 +39,30 @@ * out of long long >> 32, or the low word from long long << 32 */ -#define __get_unaligned_2(__p) \ +#define __get_unaligned_2_le(__p) \ (__p[0] | __p[1] << 8) -#define __get_unaligned_4(__p) \ +#define __get_unaligned_2_be(__p) \ + (__p[0] << 8 | __p[1]) + +#define __get_unaligned_4_le(__p) \ (__p[0] | __p[1] << 8 | __p[2] << 16 | __p[3] << 24) -#define get_unaligned(ptr) \ +#define __get_unaligned_4_be(__p) \ + (__p[0] << 24 | __p[1] << 16 | __p[2] << 8 | __p[3]) + +#define __get_unaligned_le(ptr) \ ({ \ __typeof__(*(ptr)) __v; \ __u8 *__p = (__u8 *)(ptr); \ switch (sizeof(*(ptr))) { \ case 1: __v = *(ptr); break; \ - case 2: __v = __get_unaligned_2(__p); break; \ - case 4: __v = __get_unaligned_4(__p); break; \ + case 2: __v = __get_unaligned_2_le(__p); break; \ + case 4: __v = __get_unaligned_4_le(__p); break; \ case 8: { \ unsigned int __v1, __v2; \ - __v2 = __get_unaligned_4((__p+4)); \ - __v1 = __get_unaligned_4(__p); \ + __v2 = __get_unaligned_4_le((__p+4)); \ + __v1 = __get_unaligned_4_le(__p); \ __v = ((unsigned long long)__v2 << 32 | __v1); \ } \ break; \ @@ -65,44 +71,105 @@ __v; \ }) +#define __get_unaligned_be(ptr) \ + ({ \ + __typeof__(*(ptr)) __v; \ + __u8 *__p = (__u8 *)(ptr); \ + switch (sizeof(*(ptr))) { \ + case 1: __v = *(ptr); break; \ + case 2: __v = __get_unaligned_2_be(__p); break; \ + case 4: __v = __get_unaligned_4_be(__p); break; \ + case 8: { \ + unsigned int __v1, __v2; \ + __v2 = __get_unaligned_4_be(__p); \ + __v1 = __get_unaligned_4_be((__p+4)); \ + __v = ((unsigned long long)__v2 << 32 | __v1); \ + } \ + break; \ + default: __v = __bug_unaligned_x(__p); break; \ + } \ + __v; \ + }) -static inline void __put_unaligned_2(__u32 __v, register __u8 *__p) + +static inline void __put_unaligned_2_le(__u32 __v, register __u8 *__p) { *__p++ = __v; *__p++ = __v >> 8; } -static inline void __put_unaligned_4(__u32 __v, register __u8 *__p) +static inline void __put_unaligned_2_be(__u32 __v, register __u8 *__p) +{ + *__p++ = __v >> 8; + *__p++ = __v; +} + +static inline void __put_unaligned_4_le(__u32 __v, register __u8 *__p) +{ + __put_unaligned_2_le(__v >> 16, __p + 2); + __put_unaligned_2_le(__v, __p); +} + +static inline void __put_unaligned_4_be(__u32 __v, register __u8 *__p) { - __put_unaligned_2(__v >> 16, __p + 2); - __put_unaligned_2(__v, __p); + __put_unaligned_2_be(__v >> 16, __p); + __put_unaligned_2_be(__v, __p + 2); } -static inline void __put_unaligned_8(const unsigned long long __v, register __u8 *__p) +static inline void __put_unaligned_8_le(const unsigned long long __v, register __u8 *__p) { /* * tradeoff: 8 bytes of stack for all unaligned puts (2 * instructions), or an extra register in the long long * case - go for the extra register. */ - __put_unaligned_4(__v >> 32, __p+4); - __put_unaligned_4(__v, __p); + __put_unaligned_4_le(__v >> 32, __p+4); + __put_unaligned_4_le(__v, __p); +} + +static inline void __put_unaligned_8_be(const unsigned long long __v, register __u8 *__p) +{ + /* + * tradeoff: 8 bytes of stack for all unaligned puts (2 + * instructions), or an extra register in the long long + * case - go for the extra register. + */ + __put_unaligned_4_be(__v >> 32, __p); + __put_unaligned_4_be(__v, __p+4); } /* * Try to store an unaligned value as efficiently as possible. */ -#define put_unaligned(val,ptr) \ +#define __put_unaligned_le(val,ptr) \ + ({ \ + switch (sizeof(*(ptr))) { \ + case 1: \ + *(ptr) = (val); \ + break; \ + case 2: __put_unaligned_2_le((val),(__u8 *)(ptr)); \ + break; \ + case 4: __put_unaligned_4_le((val),(__u8 *)(ptr)); \ + break; \ + case 8: __put_unaligned_8_le((val),(__u8 *)(ptr)); \ + break; \ + default: __bug_unaligned_x(ptr); \ + break; \ + } \ + (void) 0; \ + }) + +#define put_unaligned_be(val,ptr) \ ({ \ switch (sizeof(*(ptr))) { \ case 1: \ *(ptr) = (val); \ break; \ - case 2: __put_unaligned_2((val),(__u8 *)(ptr)); \ + case 2: __put_unaligned_2_be((val),(__u8 *)(ptr)); \ break; \ - case 4: __put_unaligned_4((val),(__u8 *)(ptr)); \ + case 4: __put_unaligned_4_be((val),(__u8 *)(ptr)); \ break; \ - case 8: __put_unaligned_8((val),(__u8 *)(ptr)); \ + case 8: __put_unaligned_8_be((val),(__u8 *)(ptr)); \ break; \ default: __bug_unaligned_x(ptr); \ break; \ @@ -110,5 +177,15 @@ (void) 0; \ }) +/* + * Select endianness + */ +#ifndef __ARMEB__ +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#else +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#endif #endif diff -urN linux-2.5.2-pre8/include/asm-arm/unistd.h linux/include/asm-arm/unistd.h --- linux-2.5.2-pre8/include/asm-arm/unistd.h Sun Aug 12 11:14:00 2001 +++ linux/include/asm-arm/unistd.h Sat Jan 5 14:43:18 2002 @@ -240,6 +240,10 @@ #define __NR_mincore (__NR_SYSCALL_BASE+219) #define __NR_madvise (__NR_SYSCALL_BASE+220) #define __NR_fcntl64 (__NR_SYSCALL_BASE+221) + /* 222 for tux */ +#define __NR_security (__NR_SYSCALL_BASE+223) +#define __NR_gettid (__NR_SYSCALL_BASE+224) +#define __NR_readahead (__NR_SYSCALL_BASE+225) /* * The following SWIs are ARM private. @@ -356,6 +360,9 @@ } #ifdef __KERNEL_SYSCALLS__ + +struct rusage; +asmlinkage long sys_wait4(pid_t pid,unsigned int * stat_addr, int options, struct rusage * ru); static inline long idle(void) { diff -urN linux-2.5.2-pre8/include/asm-arm/vt.h linux/include/asm-arm/vt.h --- linux-2.5.2-pre8/include/asm-arm/vt.h Tue Jan 20 16:39:43 1998 +++ linux/include/asm-arm/vt.h Wed Dec 31 16:00:00 1969 @@ -1,8 +0,0 @@ -#ifndef _ASMARM_VT_H -#define _ASMARM_VT_H - -#define VT_GETSCRINFO 0x56FD /* get screen info */ -#define VT_GETPALETTE 0x56FE /* get palette */ -#define VT_SETPALETTE 0x56FF /* set palette */ - -#endif /* _ASMARM_VT_H */ diff -urN linux-2.5.2-pre8/include/linux/tpqic02.h linux/include/linux/tpqic02.h --- linux-2.5.2-pre8/include/linux/tpqic02.h Sun Dec 16 15:44:43 2001 +++ linux/include/linux/tpqic02.h Sat Jan 5 14:43:18 2002 @@ -587,10 +587,10 @@ * |___________________ Reserved for diagnostics during debugging. */ -#define TP_REWCLOSE(d) ((MINOR(d)&0x01) == 1) /* rewind bit */ +#define TP_REWCLOSE(d) ((minor(d)&0x01) == 1) /* rewind bit */ /* rewind is only done if data has been transferred */ -#define TP_DENS(dev) ((MINOR(dev) >> 1) & 0x07) /* tape density */ -#define TP_UNIT(dev) ((MINOR(dev) >> 4) & 0x07) /* unit number */ +#define TP_DENS(dev) ((minor(dev) >> 1) & 0x07) /* tape density */ +#define TP_UNIT(dev) ((minor(dev) >> 4) & 0x07) /* unit number */ /* print excessive diagnostics */ #define TP_DIAGS(dev) (QIC02_TAPE_DEBUG & TPQD_DIAGS)