--- linux-2.5.73/arch/alpha/Kconfig 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/alpha/Kconfig 2003-06-27 15:56:22.000000000 -0700 @@ -665,33 +665,8 @@ source "drivers/md/Kconfig" source "drivers/ide/Kconfig" - -menu "SCSI support" - -config SCSI - tristate "SCSI support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - source "drivers/scsi/Kconfig" -endmenu - if PCI source "drivers/message/fusion/Kconfig" endif @@ -704,42 +679,8 @@ source "net/ax25/Kconfig" source "drivers/isdn/Kconfig" - -menu "Old CD-ROM drivers (not SCSI, not IDE)" - -config CD_NO_IDESCSI - bool "Support non-SCSI/IDE/ATAPI CDROM drives" - ---help--- - If you have a CD-ROM drive that is neither SCSI nor IDE/ATAPI, say Y - here, otherwise N. Read the CD-ROM-HOWTO, available from - . - - Note that the answer to this question doesn't directly affect the - kernel: saying N will just cause the configurator to skip all - the questions about these CD-ROM drives. If you are unsure what you - have, say Y and find out whether you have one of the following - drives. - - For each of these drivers, a file Documentation/cdrom/{driver_name} - exists. Especially in cases where you do not know exactly which kind - of drive you have you should read there. Most of these drivers use a - file drivers/cdrom/{driver_name}.h where you can define your - interface parameters and switch some internal goodies. - - All these CD-ROM drivers are also usable as a module ( = code which - can be inserted in and removed from the running kernel whenever you - want). If you want to compile them as module, say M instead of Y and - read . - - If you want to use any of these CD-ROM drivers, you also have to - answer Y or M to "ISO 9660 CD-ROM file system support" below (this - answer will get "defaulted" for you if you enable any of the Linux - CD-ROM drivers). - source "drivers/cdrom/Kconfig" -endmenu - source "drivers/input/Kconfig" source "drivers/char/Kconfig" --- linux-2.5.73/arch/arm26/Kconfig 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/arm26/Kconfig 2003-06-27 15:56:22.000000000 -0700 @@ -364,32 +364,8 @@ source "drivers/ide/Kconfig" endmenu -menu "SCSI support" - -config SCSI - tristate "SCSI support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - source "drivers/scsi/Kconfig" -endmenu - source "drivers/isdn/Kconfig" # --- linux-2.5.73/arch/arm/Kconfig 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/arm/Kconfig 2003-06-27 15:56:22.000000000 -0700 @@ -898,33 +898,8 @@ source "net/ax25/Kconfig" source "drivers/ide/Kconfig" - -menu "SCSI support" - -config SCSI - tristate "SCSI support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - source "drivers/scsi/Kconfig" -endmenu - source "drivers/ieee1394/Kconfig" source "drivers/message/i2o/Kconfig" --- linux-2.5.73/arch/cris/Kconfig 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/cris/Kconfig 2003-06-27 15:56:22.000000000 -0700 @@ -533,33 +533,8 @@ source "drivers/md/Kconfig" source "drivers/ide/Kconfig" - -menu "SCSI support" - -config SCSI - tristate "SCSI support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - source "drivers/scsi/Kconfig" -endmenu - source "drivers/ieee1394/Kconfig" source "drivers/message/i2o/Kconfig" @@ -574,42 +549,8 @@ source "drivers/isdn/Kconfig" source "drivers/telephony/Kconfig" - -menu "Old CD-ROM drivers (not SCSI, not IDE)" - -config CD_NO_IDESCSI - bool "Support non-SCSI/IDE/ATAPI CDROM drives" - ---help--- - If you have a CD-ROM drive that is neither SCSI nor IDE/ATAPI, say Y - here, otherwise N. Read the CD-ROM-HOWTO, available from - . - - Note that the answer to this question doesn't directly affect the - kernel: saying N will just cause the configurator to skip all - the questions about these CD-ROM drives. If you are unsure what you - have, say Y and find out whether you have one of the following - drives. - - For each of these drivers, a file Documentation/cdrom/{driver_name} - exists. Especially in cases where you do not know exactly which kind - of drive you have you should read there. Most of these drivers use a - file drivers/cdrom/{driver_name}.h where you can define your - interface parameters and switch some internal goodies. - - All these CD-ROM drivers are also usable as a module ( = code which - can be inserted in and removed from the running kernel whenever you - want). If you want to compile them as module, say M instead of Y and - read . - - If you want to use any of these CD-ROM drivers, you also have to - answer Y or M to "ISO 9660 CD-ROM file system support" below (this - answer will get "defaulted" for you if you enable any of the Linux - CD-ROM drivers). - source "drivers/cdrom/Kconfig" -endmenu - # # input before char - char/joystick depends on it. As does USB. # --- linux-2.5.73/arch/i386/Kconfig 2003-06-26 22:07:22.000000000 -0700 +++ 25/arch/i386/Kconfig 2003-06-27 15:56:51.000000000 -0700 @@ -680,6 +680,48 @@ config HIGHMEM64G endchoice +choice + help + On i386, a process can only virtually address 4GB of memory. This + lets you select how much of that virtual space you would like to + devoted to userspace, and how much to the kernel. + + Some userspace programs would like to address as much as possible and + have few demands of the kernel other than it get out of the way. These + users may opt to use the 3.5GB option to give their userspace program + as much room as possible. Due to alignment issues imposed by PAE, + the "3.5GB" option is unavailable if "64GB" high memory support is + enabled. + + Other users (especially those who use PAE) may be running out of + ZONE_NORMAL memory. Those users may benefit from increasing the + kernel's virtual address space size by taking it away from userspace, + which may not need all of its space. An indicator that this is + happening is when /proc/Meminfo's "LowFree:" is a small percentage of + "LowTotal:" while "HighFree:" is very large. + + If unsure, say "3GB" + prompt "User address space size" + default 1GB + +config 025GB + bool "3.75 GB" + depends on !HIGHMEM64G + +config 05GB + bool "3.5 GB" + depends on !HIGHMEM64G + +config 1GB + bool "3 GB" + +config 2GB + bool "2 GB" + +config 3GB + bool "1 GB" +endchoice + config HIGHMEM bool depends on HIGHMEM64G || HIGHMEM4G @@ -1206,70 +1248,10 @@ source "drivers/block/Kconfig" source "drivers/ide/Kconfig" - -menu "SCSI device support" - -config SCSI - tristate "SCSI device support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - source "drivers/scsi/Kconfig" -endmenu - - -menu "Old CD-ROM drivers (not SCSI, not IDE)" - depends on ISA - -config CD_NO_IDESCSI - bool "Support non-SCSI/IDE/ATAPI CDROM drives" - ---help--- - If you have a CD-ROM drive that is neither SCSI nor IDE/ATAPI, say Y - here, otherwise N. Read the CD-ROM-HOWTO, available from - . - - Note that the answer to this question doesn't directly affect the - kernel: saying N will just cause the configurator to skip all - the questions about these CD-ROM drives. If you are unsure what you - have, say Y and find out whether you have one of the following - drives. - - For each of these drivers, a file Documentation/cdrom/{driver_name} - exists. Especially in cases where you do not know exactly which kind - of drive you have you should read there. Most of these drivers use a - file drivers/cdrom/{driver_name}.h where you can define your - interface parameters and switch some internal goodies. - - All these CD-ROM drivers are also usable as a module ( = code which - can be inserted in and removed from the running kernel whenever you - want). If you want to compile them as module, say M instead of Y and - read . - - If you want to use any of these CD-ROM drivers, you also have to - answer Y or M to "ISO 9660 CD-ROM file system support" below (this - answer will get "defaulted" for you if you enable any of the Linux - CD-ROM drivers). - source "drivers/cdrom/Kconfig" -endmenu - source "drivers/md/Kconfig" source "drivers/message/fusion/Kconfig" @@ -1399,6 +1381,23 @@ config DEBUG_SPINLOCK best used in conjunction with the NMI watchdog so that spinlock deadlocks are also debuggable. +config SPINLINE + bool "Spinlock inlining" + depends on DEBUG_KERNEL + help + This will change spinlocks from out of line to inline, making them + account cost to the callers in readprofile, rather than the lock + itself (as ".text.lock.filename"). This can be helpful for finding + the callers of locks. + +config DEBUG_PAGEALLOC + bool "Page alloc debugging" + depends on DEBUG_KERNEL + help + Unmap pages from the kernel linear mapping after free_pages(). + This results in a large slowdown, but helps to find certain types + of memory corruptions. + config DEBUG_HIGHMEM bool "Highmem debugging" depends on DEBUG_KERNEL && HIGHMEM @@ -1413,20 +1412,207 @@ config KALLSYMS symbolic stack backtraces. This increases the size of the kernel somewhat, as all symbols have to be loaded into the kernel image. +config LOCKMETER + bool "Kernel lock metering" + depends on SMP && !PREEMPT + help + Say Y to enable kernel lock metering, which adds overhead to SMP locks, + but allows you to see various statistics using the lockstat command. + config DEBUG_SPINLOCK_SLEEP bool "Sleep-inside-spinlock checking" help If you say Y here, various routines which may sleep will become very noisy if they are called with a spinlock held. +config KGDB + bool "Include kgdb kernel debugger" + depends on DEBUG_KERNEL + help + If you say Y here, the system will be compiled with the debug + option (-g) and a debugging stub will be included in the + kernel. This stub communicates with gdb on another (host) + computer via a serial port. The host computer should have + access to the kernel binary file (vmlinux) and a serial port + that is connected to the target machine. Gdb can be made to + configure the serial port or you can use stty and setserial to + do this. See the 'target' command in gdb. This option also + configures in the ability to request a breakpoint early in the + boot process. To request the breakpoint just include 'kgdb' + as a boot option when booting the target machine. The system + will then break as soon as it looks at the boot options. This + option also installs a breakpoint in panic and sends any + kernel faults to the debugger. For more information see the + Documentation/i386/kgdb.txt file. + +choice + depends on KGDB + prompt "Debug serial port BAUD" + default KGDB_115200BAUD + help + Gdb and the kernel stub need to agree on the baud rate to be + used. Some systems (x86 family at this writing) allow this to + be configured. + +config KGDB_9600BAUD + bool "9600" + +config KGDB_19200BAUD + bool "19200" + +config KGDB_38400BAUD + bool "38400" + +config KGDB_57600BAUD + bool "57600" + +config KGDB_115200BAUD + bool "115200" +endchoice + +config KGDB_PORT + hex "hex I/O port address of the debug serial port" + depends on KGDB + default 3f8 + help + Some systems (x86 family at this writing) allow the port + address to be configured. The number entered is assumed to be + hex, don't put 0x in front of it. The standard address are: + COM1 3f8 , irq 4 and COM2 2f8 irq 3. Setserial /dev/ttySx + will tell you what you have. It is good to test the serial + connection with a live system before trying to debug. + +config KGDB_IRQ + int "IRQ of the debug serial port" + depends on KGDB + default 4 + help + This is the irq for the debug port. If everything is working + correctly and the kernel has interrupts on a control C to the + port should cause a break into the kernel debug stub. + +config DEBUG_INFO + bool + default y + +config KGDB_MORE + bool "Add any additional compile options" + depends on KGDB + default n + help + Saying yes here turns on the ability to enter additional + compile options. + + +config KGDB_OPTIONS + depends on KGDB_MORE + string "Additional compile arguments" + default "-O1" + help + This option allows you enter additional compile options for + the whole kernel compile. Each platform will have a default + that seems right for it. For example on PPC "-ggdb -O1", and + for i386 "-O1". Note that by configuring KGDB "-g" is already + turned on. In addition, on i386 platforms + "-fomit-frame-pointer" is deleted from the standard compile + options. + +config NO_KGDB_CPUS + int "Number of CPUs" + depends on KGDB && SMP + default NR_CPUS + help + + This option sets the number of cpus for kgdb ONLY. It is used + to prune some internal structures so they look "nice" when + displayed with gdb. This is to overcome possibly larger + numbers that may have been entered above. Enter the real + number to get nice clean kgdb_info displays. + +config KGDB_TS + bool "Enable kgdb time stamp macros?" + depends on KGDB + default n + help + Kgdb event macros allow you to instrument your code with calls + to the kgdb event recording function. The event log may be + examined with gdb at a break point. Turning on this + capability also allows you to choose how many events to + keep. Kgdb always keeps the lastest events. + +choice + depends on KGDB_TS + prompt "Max number of time stamps to save?" + default KGDB_TS_128 + +config KGDB_TS_64 + bool "64" + +config KGDB_TS_128 + bool "128" + +config KGDB_TS_256 + bool "256" + +config KGDB_TS_512 + bool "512" + +config KGDB_TS_1024 + bool "1024" + +endchoice + +config STACK_OVERFLOW_TEST + bool "Turn on kernel stack overflow testing?" + depends on KGDB + default n + help + This option enables code in the front line interrupt handlers + to check for kernel stack overflow on interrupts and system + calls. This is part of the kgdb code on x86 systems. + +config KGDB_CONSOLE + bool "Enable serial console thru kgdb port" + depends on KGDB + default n + help + This option enables the command line "console=kgdb" option. + When the system is booted with this option in the command line + all kernel printk output is sent to gdb (as well as to other + consoles). For this to work gdb must be connected. For this + reason, this command line option will generate a breakpoint if + gdb has not yet connected. After the gdb continue command is + given all pent up console output will be printed by gdb on the + host machine. Neither this option, nor KGDB require the + serial driver to be configured. + +config KGDB_SYSRQ + bool "Turn on SysRq 'G' command to do a break?" + depends on KGDB + default y + help + This option includes an option in the SysRq code that allows + you to enter SysRq G which generates a breakpoint to the KGDB + stub. This will work if the keyboard is alive and can + interrupt the system. Because of constraints on when the + serial port interrupt can be enabled, this code may allow you + to interrupt the system before the serial port control C is + available. Just say yes here. + config FRAME_POINTER bool "Compile the kernel with frame pointers" + default KGDB help If you say Y here the resulting kernel image will be slightly larger and slower, but it will give very useful debugging information. If you don't debug the kernel, you can say N, but we may not be able to solve problems without frame pointers. +config MAGIC_SYSRQ + bool + depends on KGDB_SYSRQ + default y + config X86_EXTRA_IRQS bool depends on X86_LOCAL_APIC || X86_VOYAGER @@ -1442,6 +1628,13 @@ config X86_MPPARSE depends on X86_LOCAL_APIC && !X86_VISWS default y +config SLEEPOMETER + bool "sleep instrumentation" if !PREEMPT + default n + help + Creates /proc/sleepo, and puts things in there which identify + where the kernel is blocking and for how long. + endmenu source "security/Kconfig" --- linux-2.5.73/arch/i386/kernel/apic.c 2003-06-26 22:07:22.000000000 -0700 +++ 25/arch/i386/kernel/apic.c 2003-06-27 15:56:22.000000000 -0700 @@ -616,7 +616,7 @@ static int __init detect_init_APIC (void goto no_apic; case X86_VENDOR_INTEL: if (boot_cpu_data.x86 == 6 || - (boot_cpu_data.x86 == 15 && cpu_has_apic) || + boot_cpu_data.x86 == 15 || (boot_cpu_data.x86 == 5 && cpu_has_apic)) break; goto no_apic; --- linux-2.5.73/arch/i386/kernel/cpu/common.c 2003-06-26 22:07:22.000000000 -0700 +++ 25/arch/i386/kernel/cpu/common.c 2003-06-27 15:56:34.000000000 -0700 @@ -430,6 +430,14 @@ void __init early_cpu_init(void) rise_init_cpu(); nexgen_init_cpu(); umc_init_cpu(); + +#ifdef CONFIG_DEBUG_PAGEALLOC + /* pse is not compatible with on-the-fly unmapping, + * disable it even if the cpus claim to support it. + */ + clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability); + disable_pse = 1; +#endif } /* * cpu_init() initializes state that is per-CPU. Some data is already --- linux-2.5.73/arch/i386/kernel/cpu/cpufreq/Kconfig 2003-06-14 12:18:00.000000000 -0700 +++ 25/arch/i386/kernel/cpu/cpufreq/Kconfig 2003-06-27 15:56:22.000000000 -0700 @@ -123,6 +123,11 @@ config X86_SPEEDSTEP_CENTRINO If in doubt, say N. +config X86_SPEEDSTEP_LIB + tristate + depends on X86_SPEEDSTEP_ICH + default X86_SPEEDSTEP_ICH + config X86_P4_CLOCKMOD tristate "Intel Pentium 4 clock modulation" depends on CPU_FREQ_TABLE --- linux-2.5.73/arch/i386/kernel/cpu/cpufreq/Makefile 2003-06-14 12:18:08.000000000 -0700 +++ 25/arch/i386/kernel/cpu/cpufreq/Makefile 2003-06-27 15:56:22.000000000 -0700 @@ -8,6 +8,7 @@ obj-$(CONFIG_X86_GX_SUSPMOD) += gx-su obj-$(CONFIG_X86_ACPI_CPUFREQ) += acpi.o obj-$(CONFIG_X86_SPEEDSTEP_ICH) += speedstep-ich.o obj-$(CONFIG_X86_SPEEDSTEP_CENTRINO) += speedstep-centrino.o +obj-$(CONFIG_X86_SPEEDSTEP_LIB) += speedstep-lib.o ifdef CONFIG_X86_ACPI_CPUFREQ ifdef CONFIG_ACPI_DEBUG --- linux-2.5.73/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c 2003-06-14 12:18:07.000000000 -0700 +++ 25/arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c 2003-06-27 15:56:22.000000000 -0700 @@ -29,7 +29,7 @@ #define PFX "speedstep-centrino: " #define MAINTAINER "Jeremy Fitzhardinge " -#define CENTRINO_DEBUG +/*#define CENTRINO_DEBUG*/ #ifdef CENTRINO_DEBUG #define dprintk(msg...) printk(msg) --- linux-2.5.73/arch/i386/kernel/cpu/cpufreq/speedstep-ich.c 2003-06-14 12:17:55.000000000 -0700 +++ 25/arch/i386/kernel/cpu/cpufreq/speedstep-ich.c 2003-06-27 15:56:22.000000000 -0700 @@ -1,6 +1,4 @@ /* - * $Id: speedstep.c,v 1.70 2003/02/22 10:23:46 db Exp $ - * * (C) 2001 Dave Jones, Arjan van de ven. * (C) 2002 - 2003 Dominik Brodowski * @@ -27,46 +25,32 @@ #include #include -#include +#include "speedstep-lib.h" + /* speedstep_chipset: * It is necessary to know which chipset is used. As accesses to * this device occur at various places in this module, we need a * static struct pci_dev * pointing to that device. */ -static unsigned int speedstep_chipset; -static struct pci_dev *speedstep_chipset_dev; +static struct pci_dev *speedstep_chipset_dev; -#define SPEEDSTEP_CHIPSET_ICH2M 0x00000002 -#define SPEEDSTEP_CHIPSET_ICH3M 0x00000003 -#define SPEEDSTEP_CHIPSET_ICH4M 0x00000004 /* speedstep_processor */ -static unsigned int speedstep_processor = 0; -static int speedstep_coppermine = 0; - -#define SPEEDSTEP_PROCESSOR_PIII_C 0x00000001 /* Coppermine core */ -#define SPEEDSTEP_PROCESSOR_PIII_T 0x00000002 /* Tualatin core */ -#define SPEEDSTEP_PROCESSOR_P4M 0x00000003 /* P4-M with 100 MHz FSB */ +static unsigned int speedstep_processor = 0; -/* speedstep_[low,high]_freq +/* * There are only two frequency states for each processor. Values * are in kHz for the time being. */ -#define SPEEDSTEP_HIGH 0x00000000 -#define SPEEDSTEP_LOW 0x00000001 - static struct cpufreq_frequency_table speedstep_freqs[] = { {SPEEDSTEP_HIGH, 0}, {SPEEDSTEP_LOW, 0}, {0, CPUFREQ_TABLE_END}, }; -#define speedstep_low_freq speedstep_freqs[SPEEDSTEP_LOW].frequency -#define speedstep_high_freq speedstep_freqs[SPEEDSTEP_HIGH].frequency - /* DEBUG * Define it if you want verbose debug output, e.g. for bug reporting @@ -80,149 +64,82 @@ static struct cpufreq_frequency_table sp #endif - -/********************************************************************* - * LOW LEVEL CHIPSET INTERFACE * - *********************************************************************/ - -/** - * speedstep_get_state - read the current SpeedStep state - * @state: Speedstep state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH) - * - * Tries to read the SpeedStep state. Returns -EIO when there has been - * trouble to read the status or write to the control register, -EINVAL - * on an unsupported chipset, and zero on success. - */ -static int speedstep_get_state (unsigned int *state) -{ - unsigned long flags; - u32 pmbase; - u8 value; - - if (!speedstep_chipset_dev || !state) - return -EINVAL; - - switch (speedstep_chipset) { - case SPEEDSTEP_CHIPSET_ICH2M: - case SPEEDSTEP_CHIPSET_ICH3M: - case SPEEDSTEP_CHIPSET_ICH4M: - /* get PMBASE */ - pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase); - if (!(pmbase & 0x01)) - return -EIO; - - pmbase &= 0xFFFFFFFE; - if (!pmbase) - return -EIO; - - /* read state */ - local_irq_save(flags); - value = inb(pmbase + 0x50); - local_irq_restore(flags); - - dprintk(KERN_DEBUG "cpufreq: read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value); - - *state = value & 0x01; - return 0; - - } - - printk (KERN_ERR "cpufreq: setting CPU frequency on this chipset unsupported.\n"); - return -EINVAL; -} - - /** * speedstep_set_state - set the SpeedStep state * @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH) * * Tries to change the SpeedStep state. */ -static void speedstep_set_state (unsigned int state, int notify) +static void speedstep_set_state (unsigned int state, unsigned int notify) { - u32 pmbase; - u8 pm2_blk; - u8 value; - unsigned long flags; - unsigned int oldstate; - struct cpufreq_freqs freqs; + u32 pmbase; + u8 pm2_blk; + u8 value; + unsigned long flags; + struct cpufreq_freqs freqs; if (!speedstep_chipset_dev || (state > 0x1)) return; - if (speedstep_get_state(&oldstate)) - return; - - if (oldstate == state) - return; - - freqs.old = (oldstate == SPEEDSTEP_HIGH) ? speedstep_high_freq : speedstep_low_freq; - freqs.new = (state == SPEEDSTEP_HIGH) ? speedstep_high_freq : speedstep_low_freq; + freqs.old = speedstep_get_processor_frequency(speedstep_processor); + freqs.new = speedstep_freqs[SPEEDSTEP_LOW].frequency; freqs.cpu = 0; /* speedstep.c is UP only driver */ if (notify) cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); - switch (speedstep_chipset) { - case SPEEDSTEP_CHIPSET_ICH2M: - case SPEEDSTEP_CHIPSET_ICH3M: - case SPEEDSTEP_CHIPSET_ICH4M: - /* get PMBASE */ - pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase); - if (!(pmbase & 0x01)) - { - printk(KERN_ERR "cpufreq: could not find speedstep register\n"); - return; - } + /* get PMBASE */ + pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase); + if (!(pmbase & 0x01)) + { + printk(KERN_ERR "cpufreq: could not find speedstep register\n"); + return; + } - pmbase &= 0xFFFFFFFE; - if (!pmbase) { - printk(KERN_ERR "cpufreq: could not find speedstep register\n"); - return; - } + pmbase &= 0xFFFFFFFE; + if (!pmbase) { + printk(KERN_ERR "cpufreq: could not find speedstep register\n"); + return; + } - /* Disable IRQs */ - local_irq_save(flags); + /* Disable IRQs */ + local_irq_save(flags); - /* read state */ - value = inb(pmbase + 0x50); + /* read state */ + value = inb(pmbase + 0x50); - dprintk(KERN_DEBUG "cpufreq: read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value); + dprintk(KERN_DEBUG "cpufreq: read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value); - /* write new state */ - value &= 0xFE; - value |= state; + /* write new state */ + value &= 0xFE; + value |= state; - dprintk(KERN_DEBUG "cpufreq: writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase); + dprintk(KERN_DEBUG "cpufreq: writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase); - /* Disable bus master arbitration */ - pm2_blk = inb(pmbase + 0x20); - pm2_blk |= 0x01; - outb(pm2_blk, (pmbase + 0x20)); + /* Disable bus master arbitration */ + pm2_blk = inb(pmbase + 0x20); + pm2_blk |= 0x01; + outb(pm2_blk, (pmbase + 0x20)); - /* Actual transition */ - outb(value, (pmbase + 0x50)); + /* Actual transition */ + outb(value, (pmbase + 0x50)); - /* Restore bus master arbitration */ - pm2_blk &= 0xfe; - outb(pm2_blk, (pmbase + 0x20)); + /* Restore bus master arbitration */ + pm2_blk &= 0xfe; + outb(pm2_blk, (pmbase + 0x20)); - /* check if transition was successful */ - value = inb(pmbase + 0x50); + /* check if transition was successful */ + value = inb(pmbase + 0x50); - /* Enable IRQs */ - local_irq_restore(flags); + /* Enable IRQs */ + local_irq_restore(flags); - dprintk(KERN_DEBUG "cpufreq: read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value); + dprintk(KERN_DEBUG "cpufreq: read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value); - if (state == (value & 0x1)) { - dprintk (KERN_INFO "cpufreq: change to %u MHz succeeded\n", (freqs.new / 1000)); - } else { - printk (KERN_ERR "cpufreq: change failed - I/O error\n"); - } - break; - default: - printk (KERN_ERR "cpufreq: setting CPU frequency on this chipset unsupported.\n"); + if (state == (value & 0x1)) { + dprintk (KERN_INFO "cpufreq: change to %u MHz succeeded\n", (freqs.new / 1000)); + } else { + printk (KERN_ERR "cpufreq: change failed - I/O error\n"); } if (notify) @@ -240,31 +157,21 @@ static void speedstep_set_state (unsigne */ static int speedstep_activate (void) { + u16 value = 0; + if (!speedstep_chipset_dev) return -EINVAL; - switch (speedstep_chipset) { - case SPEEDSTEP_CHIPSET_ICH2M: - case SPEEDSTEP_CHIPSET_ICH3M: - case SPEEDSTEP_CHIPSET_ICH4M: - { - u16 value = 0; - - pci_read_config_word(speedstep_chipset_dev, - 0x00A0, &value); - if (!(value & 0x08)) { - value |= 0x08; - dprintk(KERN_DEBUG "cpufreq: activating SpeedStep (TM) registers\n"); - pci_write_config_word(speedstep_chipset_dev, - 0x00A0, value); - } - - return 0; - } + pci_read_config_word(speedstep_chipset_dev, + 0x00A0, &value); + if (!(value & 0x08)) { + value |= 0x08; + dprintk(KERN_DEBUG "cpufreq: activating SpeedStep (TM) registers\n"); + pci_write_config_word(speedstep_chipset_dev, + 0x00A0, value); } - - printk (KERN_ERR "cpufreq: SpeedStep (TM) on this chipset unsupported.\n"); - return -EINVAL; + + return 0; } @@ -284,7 +191,7 @@ static unsigned int speedstep_detect_chi PCI_ANY_ID, NULL); if (speedstep_chipset_dev) - return SPEEDSTEP_CHIPSET_ICH4M; + return 4; /* 4-M */ speedstep_chipset_dev = pci_find_subsys(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, @@ -292,7 +199,7 @@ static unsigned int speedstep_detect_chi PCI_ANY_ID, NULL); if (speedstep_chipset_dev) - return SPEEDSTEP_CHIPSET_ICH3M; + return 3; /* 3-M */ speedstep_chipset_dev = pci_find_subsys(PCI_VENDOR_ID_INTEL, @@ -305,7 +212,7 @@ static unsigned int speedstep_detect_chi * 8100 which use a pretty old revision of the 82815 * host brige. Abort on these systems. */ - static struct pci_dev *hostbridge; + static struct pci_dev *hostbridge; u8 rev = 0; hostbridge = pci_find_subsys(PCI_VENDOR_ID_INTEL, @@ -315,7 +222,7 @@ static unsigned int speedstep_detect_chi NULL); if (!hostbridge) - return SPEEDSTEP_CHIPSET_ICH2M; + return 2; /* 2-M */ pci_read_config_byte(hostbridge, PCI_REVISION_ID, &rev); if (rev < 5) { @@ -324,266 +231,9 @@ static unsigned int speedstep_detect_chi return 0; } - return SPEEDSTEP_CHIPSET_ICH2M; - } - - return 0; -} - - - -/********************************************************************* - * LOW LEVEL PROCESSOR INTERFACE * - *********************************************************************/ - - -/** - * pentium3_get_frequency - get the core frequencies for PIIIs - * - * Returns the core frequency of a Pentium III processor (in kHz) - */ -static unsigned int pentium3_get_frequency (void) -{ - /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */ - struct { - unsigned int ratio; /* Frequency Multiplier (x10) */ - u8 bitmap; /* power on configuration bits - [27, 25:22] (in MSR 0x2a) */ - } msr_decode_mult [] = { - { 30, 0x01 }, - { 35, 0x05 }, - { 40, 0x02 }, - { 45, 0x06 }, - { 50, 0x00 }, - { 55, 0x04 }, - { 60, 0x0b }, - { 65, 0x0f }, - { 70, 0x09 }, - { 75, 0x0d }, - { 80, 0x0a }, - { 85, 0x26 }, - { 90, 0x20 }, - { 100, 0x2b }, - { 0, 0xff } /* error or unknown value */ - }; - /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */ - struct { - unsigned int value; /* Front Side Bus speed in MHz */ - u8 bitmap; /* power on configuration bits [18: 19] - (in MSR 0x2a) */ - } msr_decode_fsb [] = { - { 66, 0x0 }, - { 100, 0x2 }, - { 133, 0x1 }, - { 0, 0xff} - }; - u32 msr_lo, msr_tmp; - int i = 0, j = 0; - struct cpuinfo_x86 *c = cpu_data; - - /* read MSR 0x2a - we only need the low 32 bits */ - rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); - dprintk(KERN_DEBUG "cpufreq: P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); - msr_tmp = msr_lo; - - /* decode the FSB */ - msr_tmp &= 0x00c0000; - msr_tmp >>= 18; - while (msr_tmp != msr_decode_fsb[i].bitmap) { - if (msr_decode_fsb[i].bitmap == 0xff) - return -EINVAL; - i++; - } - - /* decode the multiplier */ - if ((c->x86_model == 0x08) && (c->x86_mask == 0x01)) - /* different on early Coppermine PIII */ - msr_lo &= 0x03c00000; - else - msr_lo &= 0x0bc00000; - msr_lo >>= 22; - while (msr_lo != msr_decode_mult[j].bitmap) { - if (msr_decode_mult[j].bitmap == 0xff) - return -EINVAL; - j++; - } - - return (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100); -} - - -/** - * pentium4_get_frequency - get the core frequency for P4-Ms - * - * Should return the core frequency (in kHz) for P4-Ms. - */ -static unsigned int pentium4_get_frequency(void) -{ - u32 msr_lo, msr_hi; - - rdmsr(0x2c, msr_lo, msr_hi); - - dprintk(KERN_DEBUG "cpufreq: P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi); - - /* First 12 bits seem to change a lot (0x511, 0x410 and 0x30f seen - * yet). Next 12 bits always seem to be 0x300. If this is not true - * on this CPU, complain. Last 8 bits are frequency (in 100MHz). - */ - if (msr_hi || ((msr_lo & 0x00FFF000) != 0x300000)) { - printk(KERN_DEBUG "cpufreq: P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi); - printk(KERN_INFO "cpufreq: problem in initialization. Please contact Dominik Brodowski\n"); - printk(KERN_INFO "cpufreq: and attach this dmesg. Thanks in advance\n"); - return 0; - } - - msr_lo >>= 24; - return (msr_lo * 100000); -} - - -/** - * speedstep_detect_processor - detect Intel SpeedStep-capable processors. - * - * Returns the SPEEDSTEP_PROCESSOR_-number for the detected processor, - * or zero on failure. - */ -static unsigned int speedstep_detect_processor (void) -{ - struct cpuinfo_x86 *c = cpu_data; - u32 ebx; - - if ((c->x86_vendor != X86_VENDOR_INTEL) || - ((c->x86 != 6) && (c->x86 != 0xF))) - return 0; - - if (c->x86 == 0xF) { - /* Intel Pentium 4 Mobile P4-M */ - if (c->x86_model != 2) - return 0; - - if ((c->x86_mask != 4) && (c->x86_mask != 7)) - return 0; - - ebx = cpuid_ebx(0x00000001); - ebx &= 0x000000FF; - if ((ebx != 0x0e) && (ebx != 0x0f)) - return 0; - - return SPEEDSTEP_PROCESSOR_P4M; - } - - switch (c->x86_model) { - case 0x0B: /* Intel PIII [Tualatin] */ - /* cpuid_ebx(1) is 0x04 for desktop PIII, - 0x06 for mobile PIII-M */ - ebx = cpuid_ebx(0x00000001); - - ebx &= 0x000000FF; - if (ebx != 0x06) - return 0; - - /* So far all PIII-M processors support SpeedStep. See - * Intel's 24540633.pdf of August 2002 - */ - - return SPEEDSTEP_PROCESSOR_PIII_T; - - case 0x08: /* Intel PIII [Coppermine] */ - { - u32 msr_lo, msr_hi; - - /* all mobile PIII Coppermines have FSB 100 MHz - * ==> sort out a few desktop PIIIs. */ - rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi); - dprintk(KERN_DEBUG "cpufreq: Coppermine: MSR_IA32_EBL_Cr_POWERON is 0x%x, 0x%x\n", msr_lo, msr_hi); - msr_lo &= 0x00c0000; - if (msr_lo != 0x0080000) - return 0; - - if (speedstep_coppermine) - return SPEEDSTEP_PROCESSOR_PIII_C; - - /* - * If the processor is a mobile version, - * platform ID has bit 50 set - * it has SpeedStep technology if either - * bit 56 or 57 is set - */ - rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi); - dprintk(KERN_DEBUG "cpufreq: Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", msr_lo, msr_hi); - if ((msr_hi & (1<<18)) && (msr_hi & (3<<24))) - return SPEEDSTEP_PROCESSOR_PIII_C; - - printk(KERN_INFO "cpufreq: in case this is a SpeedStep-capable Intel Pentium III Coppermine\n"); - printk(KERN_INFO "cpufreq: processor, please pass the boot option or module parameter\n"); - printk(KERN_INFO "cpufreq: `speedstep_coppermine=1` to the kernel. Thanks!\n"); - return 0; - } - - default: - return 0; - } -} - - - -/********************************************************************* - * HIGH LEVEL FUNCTIONS * - *********************************************************************/ - -/** - * speedstep_detect_speeds - detects low and high CPU frequencies. - * - * Detects the low and high CPU frequencies in kHz. Returns 0 on - * success or -EINVAL / -EIO on problems. - */ -static int speedstep_detect_speeds (void) -{ - unsigned long flags; - unsigned int state; - int i, result; - - /* Disable irqs for entire detection process */ - local_irq_save(flags); - - for (i=0; i<2; i++) { - /* read the current state */ - result = speedstep_get_state(&state); - if (result) { - local_irq_restore(flags); - return result; - } - - /* save the correct value, and switch to other */ - if (state == SPEEDSTEP_LOW) { - switch (speedstep_processor) { - case SPEEDSTEP_PROCESSOR_PIII_C: - case SPEEDSTEP_PROCESSOR_PIII_T: - speedstep_low_freq = pentium3_get_frequency(); - break; - case SPEEDSTEP_PROCESSOR_P4M: - speedstep_low_freq = pentium4_get_frequency(); - } - speedstep_set_state(SPEEDSTEP_HIGH, 0); - } else { - switch (speedstep_processor) { - case SPEEDSTEP_PROCESSOR_PIII_C: - case SPEEDSTEP_PROCESSOR_PIII_T: - speedstep_high_freq = pentium3_get_frequency(); - break; - case SPEEDSTEP_PROCESSOR_P4M: - speedstep_high_freq = pentium4_get_frequency(); - } - speedstep_set_state(SPEEDSTEP_LOW, 0); - } + return 2; /* 2-M */ } - local_irq_restore(flags); - - if (!speedstep_low_freq || !speedstep_high_freq || - (speedstep_low_freq == speedstep_high_freq)) - return -EIO; - return 0; } @@ -598,7 +248,7 @@ static int speedstep_target (struct cpuf unsigned int target_freq, unsigned int relation) { - unsigned int newstate = 0; + unsigned int newstate = 0; if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0], target_freq, relation, &newstate)) return -EINVAL; @@ -632,22 +282,24 @@ static int speedstep_cpu_init(struct cpu return -ENODEV; /* detect low and high frequency */ - result = speedstep_detect_speeds(); + result = speedstep_get_freqs(speedstep_processor, + &speedstep_freqs[SPEEDSTEP_LOW].frequency, + &speedstep_freqs[SPEEDSTEP_HIGH].frequency, + &speedstep_set_state); if (result) return result; /* get current speed setting */ - result = speedstep_get_state(&speed); - if (result) - return result; + speed = speedstep_get_processor_frequency(speedstep_processor); + if (!speed) + return -EIO; - speed = (speed == SPEEDSTEP_LOW) ? speedstep_low_freq : speedstep_high_freq; dprintk(KERN_INFO "cpufreq: currently at %s speed setting - %i MHz\n", (speed == speedstep_low_freq) ? "low" : "high", (speed / 1000)); /* cpuinfo and default policy values */ - policy->policy = (speed == speedstep_low_freq) ? + policy->policy = (speed == speedstep_freqs[SPEEDSTEP_LOW].frequency) ? CPUFREQ_POLICY_POWERSAVE : CPUFREQ_POLICY_PERFORMANCE; policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; policy->cur = speed; @@ -656,26 +308,6 @@ static int speedstep_cpu_init(struct cpu } -#ifndef MODULE -/** - * speedstep_setup speedstep command line parameter parsing - * - * speedstep command line parameter. Use: - * speedstep_coppermine=1 - * if the CPU in your notebook is a SpeedStep-capable Intel - * Pentium III Coppermine. These processors cannot be detected - * automatically, as Intel continues to consider the detection - * algorithm as proprietary material. - */ -static int __init speedstep_setup(char *str) -{ - speedstep_coppermine = simple_strtoul(str, &str, 0); - return 1; -} -__setup("speedstep_coppermine=", speedstep_setup); -#endif - - static struct cpufreq_driver speedstep_driver = { .name = "speedstep", .verify = speedstep_verify, @@ -694,20 +326,17 @@ static struct cpufreq_driver speedstep_d */ static int __init speedstep_init(void) { - /* detect chipset */ - speedstep_chipset = speedstep_detect_chipset(); + /* detect processor */ + speedstep_processor = speedstep_detect_processor(); + if (!speedstep_processor) + return -ENODEV; /* detect chipset */ - if (speedstep_chipset) - speedstep_processor = speedstep_detect_processor(); - - if ((!speedstep_chipset) || (!speedstep_processor)) { - printk(KERN_INFO "cpufreq: Intel(R) SpeedStep(TM) for this %s not (yet) available.\n", speedstep_chipset ? "processor" : "chipset"); + if (!speedstep_detect_chipset()) { + printk(KERN_INFO "cpufreq: Intel(R) SpeedStep(TM) for this chipset not (yet) available.\n"); return -ENODEV; } - dprintk(KERN_INFO "cpufreq: Intel(R) SpeedStep(TM) support $Revision: 1.70 $\n"); - /* activate speedstep support */ if (speedstep_activate()) return -EINVAL; @@ -727,10 +356,8 @@ static void __exit speedstep_exit(void) } -MODULE_PARM (speedstep_coppermine, "i"); - MODULE_AUTHOR ("Dave Jones , Dominik Brodowski "); -MODULE_DESCRIPTION ("Speedstep driver for Intel mobile processors."); +MODULE_DESCRIPTION ("Speedstep driver for Intel mobile processors on chipsets with ICH-M southbridges."); MODULE_LICENSE ("GPL"); module_init(speedstep_init); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c 2003-06-27 15:56:22.000000000 -0700 @@ -0,0 +1,275 @@ +/* + * (C) 2002 - 2003 Dominik Brodowski + * + * Licensed under the terms of the GNU GPL License version 2. + * + * Library for common functions for Intel SpeedStep v.1 and v.2 support + * + * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous* + */ + +#include +#include +#include +#include +#include +#include + +#include +#include "speedstep-lib.h" + + +/* DEBUG + * Define it if you want verbose debug output, e.g. for bug reporting + */ +//#define SPEEDSTEP_DEBUG + +#ifdef SPEEDSTEP_DEBUG +#define dprintk(msg...) printk(msg) +#else +#define dprintk(msg...) do { } while(0) +#endif + +/********************************************************************* + * GET PROCESSOR CORE SPEED IN KHZ * + *********************************************************************/ + +static unsigned int pentium3_get_frequency (unsigned int processor) +{ + /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */ + struct { + unsigned int ratio; /* Frequency Multiplier (x10) */ + u8 bitmap; /* power on configuration bits + [27, 25:22] (in MSR 0x2a) */ + } msr_decode_mult [] = { + { 30, 0x01 }, + { 35, 0x05 }, + { 40, 0x02 }, + { 45, 0x06 }, + { 50, 0x00 }, + { 55, 0x04 }, + { 60, 0x0b }, + { 65, 0x0f }, + { 70, 0x09 }, + { 75, 0x0d }, + { 80, 0x0a }, + { 85, 0x26 }, + { 90, 0x20 }, + { 100, 0x2b }, + { 0, 0xff } /* error or unknown value */ + }; + + /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */ + struct { + unsigned int value; /* Front Side Bus speed in MHz */ + u8 bitmap; /* power on configuration bits [18: 19] + (in MSR 0x2a) */ + } msr_decode_fsb [] = { + { 66, 0x0 }, + { 100, 0x2 }, + { 133, 0x1 }, + { 0, 0xff} + }; + + u32 msr_lo, msr_tmp; + int i = 0, j = 0; + + /* read MSR 0x2a - we only need the low 32 bits */ + rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); + dprintk(KERN_DEBUG "speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); + msr_tmp = msr_lo; + + /* decode the FSB */ + msr_tmp &= 0x00c0000; + msr_tmp >>= 18; + while (msr_tmp != msr_decode_fsb[i].bitmap) { + if (msr_decode_fsb[i].bitmap == 0xff) + return 0; + i++; + } + + /* decode the multiplier */ + if (processor == SPEEDSTEP_PROCESSOR_PIII_C_EARLY) + msr_lo &= 0x03c00000; + else + msr_lo &= 0x0bc00000; + msr_lo >>= 22; + while (msr_lo != msr_decode_mult[j].bitmap) { + if (msr_decode_mult[j].bitmap == 0xff) + return 0; + j++; + } + + return (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100); +} + + +static unsigned int pentium4_get_frequency(void) +{ + u32 msr_lo, msr_hi; + + rdmsr(0x2c, msr_lo, msr_hi); + + dprintk(KERN_DEBUG "speedstep-lib: P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi); + + msr_lo >>= 24; + return (msr_lo * 100000); +} + + +unsigned int speedstep_get_processor_frequency(unsigned int processor) +{ + switch (processor) { + case SPEEDSTEP_PROCESSOR_P4M: + return pentium4_get_frequency(); + case SPEEDSTEP_PROCESSOR_PIII_T: + case SPEEDSTEP_PROCESSOR_PIII_C: + case SPEEDSTEP_PROCESSOR_PIII_C_EARLY: + return pentium3_get_frequency(processor); + default: + return 0; + }; + return 0; +} +EXPORT_SYMBOL_GPL(speedstep_get_processor_frequency); + + +/********************************************************************* + * DETECT SPEEDSTEP-CAPABLE PROCESSOR * + *********************************************************************/ + +unsigned int speedstep_detect_processor (void) +{ + struct cpuinfo_x86 *c = cpu_data; + u32 ebx, msr_lo, msr_hi; + + if ((c->x86_vendor != X86_VENDOR_INTEL) || + ((c->x86 != 6) && (c->x86 != 0xF))) + return 0; + + if (c->x86 == 0xF) { + /* Intel Mobile Pentium 4-M + * or Intel Mobile Pentium 4 with 533 MHz FSB */ + if (c->x86_model != 2) + return 0; + + if ((c->x86_mask != 4) && /* B-stepping [M-P4-M] */ + (c->x86_mask != 7) && /* C-stepping [M-P4-M] */ + (c->x86_mask != 9)) /* D-stepping [M-P4-M or M-P4/533] */ + return 0; + + ebx = cpuid_ebx(0x00000001); + ebx &= 0x000000FF; + if ((ebx != 0x0e) && (ebx != 0x0f)) + return 0; + + return SPEEDSTEP_PROCESSOR_P4M; + } + + switch (c->x86_model) { + case 0x0B: /* Intel PIII [Tualatin] */ + /* cpuid_ebx(1) is 0x04 for desktop PIII, + 0x06 for mobile PIII-M */ + ebx = cpuid_ebx(0x00000001); + + ebx &= 0x000000FF; + if (ebx != 0x06) + return 0; + + /* So far all PIII-M processors support SpeedStep. See + * Intel's 24540640.pdf of June 2003 + */ + + return SPEEDSTEP_PROCESSOR_PIII_T; + + case 0x08: /* Intel PIII [Coppermine] */ + + /* all mobile PIII Coppermines have FSB 100 MHz + * ==> sort out a few desktop PIIIs. */ + rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi); + dprintk(KERN_DEBUG "cpufreq: Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", msr_lo, msr_hi); + msr_lo &= 0x00c0000; + if (msr_lo != 0x0080000) + return 0; + + /* + * If the processor is a mobile version, + * platform ID has bit 50 set + * it has SpeedStep technology if either + * bit 56 or 57 is set + */ + rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi); + dprintk(KERN_DEBUG "cpufreq: Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", msr_lo, msr_hi); + if ((msr_hi & (1<<18)) && (msr_hi & (3<<24))) { + if (c->x86_mask == 0x01) + return SPEEDSTEP_PROCESSOR_PIII_C_EARLY; + else + return SPEEDSTEP_PROCESSOR_PIII_C; + } + + default: + return 0; + } +} +EXPORT_SYMBOL_GPL(speedstep_detect_processor); + + +/********************************************************************* + * DETECT SPEEDSTEP SPEEDS * + *********************************************************************/ + +unsigned int speedstep_get_freqs(unsigned int processor, + unsigned int *low_speed, + unsigned int *high_speed, + void (*set_state) (unsigned int state, + unsigned int notify) + ) +{ + unsigned int prev_speed; + unsigned int ret = 0; + unsigned long flags; + + if ((!processor) || (!low_speed) || (!high_speed) || (!set_state)) + return EINVAL; + + /* get current speed */ + prev_speed = speedstep_get_processor_frequency(processor); + if (!prev_speed) + return EIO; + + local_irq_save(flags); + + /* switch to low state */ + set_state(SPEEDSTEP_LOW, 0); + *low_speed = speedstep_get_processor_frequency(processor); + if (!*low_speed) { + ret = EIO; + goto out; + } + + /* switch to high state */ + set_state(SPEEDSTEP_HIGH, 0); + *high_speed = speedstep_get_processor_frequency(processor); + if (!*high_speed) { + ret = EIO; + goto out; + } + + if (*low_speed == *high_speed) { + ret = ENODEV; + goto out; + } + + /* switch to previous state, if necessary */ + if (*high_speed != prev_speed) + set_state(SPEEDSTEP_LOW, 0); + + out: + local_irq_restore(flags); + return (ret); +} +EXPORT_SYMBOL_GPL(speedstep_get_freqs); + +MODULE_AUTHOR ("Dominik Brodowski "); +MODULE_DESCRIPTION ("Library for Intel SpeedStep 1 or 2 cpufreq drivers."); +MODULE_LICENSE ("GPL"); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/i386/kernel/cpu/cpufreq/speedstep-lib.h 2003-06-27 15:56:22.000000000 -0700 @@ -0,0 +1,41 @@ +/* + * (C) 2002 - 2003 Dominik Brodowski + * + * Licensed under the terms of the GNU GPL License version 2. + * + * Library for common functions for Intel SpeedStep v.1 and v.2 support + * + * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous* + */ + + + +/* processors */ + +#define SPEEDSTEP_PROCESSOR_PIII_C_EARLY 0x00000001 /* Coppermine core */ +#define SPEEDSTEP_PROCESSOR_PIII_C 0x00000002 /* Coppermine core */ +#define SPEEDSTEP_PROCESSOR_PIII_T 0x00000003 /* Tualatin core */ +#define SPEEDSTEP_PROCESSOR_P4M 0x00000004 /* P4-M with 100 MHz FSB */ + +/* speedstep states -- only two of them */ + +#define SPEEDSTEP_HIGH 0x00000000 +#define SPEEDSTEP_LOW 0x00000001 + + +/* detect a speedstep-capable processor */ +extern unsigned int speedstep_detect_processor (void); + +/* detect the current speed (in khz) of the processor */ +extern unsigned int speedstep_get_processor_frequency(unsigned int processor); + + +/* detect the low and high speeds of the processor. The callback + * set_state"'s first argument is either SPEEDSTEP_HIGH or + * SPEEDSTEP_LOW; the second argument is zero so that no + * cpufreq_notify_transition calls are initiated. + */ +extern unsigned int speedstep_get_freqs(unsigned int processor, + unsigned int *low_speed, + unsigned int *high_speed, + void (*set_state) (unsigned int state, unsigned int notify)); --- linux-2.5.73/arch/i386/kernel/cpu/mtrr/main.c 2003-06-26 22:07:22.000000000 -0700 +++ 25/arch/i386/kernel/cpu/mtrr/main.c 2003-06-27 15:56:35.000000000 -0700 @@ -701,5 +701,5 @@ char *mtrr_strings[MTRR_NUM_TYPES] = "write-back", /* 6 */ }; -subsys_initcall(mtrr_init); +core_initcall(mtrr_init); --- linux-2.5.73/arch/i386/kernel/doublefault.c 2003-06-26 22:07:22.000000000 -0700 +++ 25/arch/i386/kernel/doublefault.c 2003-06-27 15:56:32.000000000 -0700 @@ -12,7 +12,7 @@ static unsigned long doublefault_stack[DOUBLEFAULT_STACKSIZE]; #define STACK_START (unsigned long)(doublefault_stack+DOUBLEFAULT_STACKSIZE) -#define ptr_ok(x) ((x) > 0xc0000000 && (x) < 0xc1000000) +#define ptr_ok(x) ((x) >= PAGE_OFFSET && (x) < (PAGE_OFFSET + 0x01000000)) static void doublefault_fn(void) { --- linux-2.5.73/arch/i386/kernel/entry.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/kernel/entry.S 2003-06-27 15:56:51.000000000 -0700 @@ -48,6 +48,18 @@ #include #include #include "irq_vectors.h" + /* We do not recover from a stack overflow, but at least + * we know it happened and should be able to track it down. + */ +#ifdef CONFIG_STACK_OVERFLOW_TEST +#define STACK_OVERFLOW_TEST \ + testl $7680,%esp; \ + jnz 10f; \ + call stack_overflow; \ +10: +#else +#define STACK_OVERFLOW_TEST +#endif EBX = 0x00 ECX = 0x04 @@ -98,7 +110,8 @@ TSS_ESP0_OFFSET = (4 - 0x200) pushl %ebx; \ movl $(__USER_DS), %edx; \ movl %edx, %ds; \ - movl %edx, %es; + movl %edx, %es; \ + STACK_OVERFLOW_TEST #define RESTORE_INT_REGS \ popl %ebx; \ @@ -224,7 +237,11 @@ need_resched: jz restore_all movl $PREEMPT_ACTIVE,TI_PRE_COUNT(%ebp) sti +#ifdef CONFIG_SLEEPOMETER + call sleepo_schedule +#else call schedule +#endif movl $0,TI_PRE_COUNT(%ebp) cli jmp need_resched @@ -298,6 +315,19 @@ syscall_exit: testw $_TIF_ALLWORK_MASK, %cx # current->work jne syscall_exit_work restore_all: +#ifdef CONFIG_TRAP_BAD_SYSCALL_EXITS + movl EFLAGS(%esp), %eax # mix EFLAGS and CS + movb CS(%esp), %al + testl $(VM_MASK | 3), %eax + jz resume_kernelX # returning to kernel or vm86-space + + cmpl $0,TI_PRE_COUNT(%ebx) # non-zero preempt_count ? + jz resume_kernelX + + int $3 + +resume_kernelX: +#endif RESTORE_ALL # perform work that needs to be done immediately before resumption @@ -306,7 +336,11 @@ work_pending: testb $_TIF_NEED_RESCHED, %cl jz work_notifysig work_resched: +#ifdef CONFIG_SLEEPOMETER + call sleepo_schedule +#else call schedule +#endif cli # make sure we don't miss an interrupt # setting need_resched or sigpending # between sampling and the iret @@ -876,5 +910,6 @@ ENTRY(sys_call_table) .long sys_clock_nanosleep .long sys_statfs64 .long sys_fstatfs64 - + .long sys_mknod64 /* 270 */ + nr_syscalls=(.-sys_call_table)/4 --- linux-2.5.73/arch/i386/kernel/i386_ksyms.c 2003-06-14 12:18:51.000000000 -0700 +++ 25/arch/i386/kernel/i386_ksyms.c 2003-06-27 15:56:22.000000000 -0700 @@ -159,6 +159,7 @@ EXPORT_SYMBOL(smp_call_function); /* TLB flushing */ EXPORT_SYMBOL(flush_tlb_page); +EXPORT_SYMBOL_GPL(flush_tlb_all); #endif #ifdef CONFIG_X86_IO_APIC --- linux-2.5.73/arch/i386/kernel/io_apic.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/kernel/io_apic.c 2003-06-27 15:56:58.000000000 -0700 @@ -35,6 +35,7 @@ #include #include #include +#include #include @@ -1272,9 +1273,10 @@ static inline void UNEXPECTED_IO_APIC(vo void __init print_IO_APIC(void) { int apic, i; - struct IO_APIC_reg_00 reg_00; - struct IO_APIC_reg_01 reg_01; - struct IO_APIC_reg_02 reg_02; + union IO_APIC_reg_00 reg_00; + union IO_APIC_reg_01 reg_01; + union IO_APIC_reg_02 reg_02; + union IO_APIC_reg_03 reg_03; unsigned long flags; printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); @@ -1291,51 +1293,70 @@ void __init print_IO_APIC(void) for (apic = 0; apic < nr_ioapics; apic++) { spin_lock_irqsave(&ioapic_lock, flags); - *(int *)®_00 = io_apic_read(apic, 0); - *(int *)®_01 = io_apic_read(apic, 1); - if (reg_01.version >= 0x10) - *(int *)®_02 = io_apic_read(apic, 2); + reg_00.raw = io_apic_read(apic, 0); + reg_01.raw = io_apic_read(apic, 1); + if (reg_01.bits.version >= 0x10) + reg_02.raw = io_apic_read(apic, 2); + if (reg_01.bits.version >= 0x20) + reg_03.raw = io_apic_read(apic, 3); spin_unlock_irqrestore(&ioapic_lock, flags); - printk("\n"); printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); - printk(KERN_DEBUG ".... register #00: %08X\n", *(int *)®_00); - printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.ID); - printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.delivery_type); - printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.LTS); - if (reg_00.ID >= APIC_BROADCAST_ID) + printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); + printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); + printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); + printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); + if (reg_00.bits.ID >= APIC_BROADCAST_ID) UNEXPECTED_IO_APIC(); - if (reg_00.__reserved_1 || reg_00.__reserved_2) + if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2) UNEXPECTED_IO_APIC(); - printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); - printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.entries); - if ( (reg_01.entries != 0x0f) && /* older (Neptune) boards */ - (reg_01.entries != 0x17) && /* typical ISA+PCI boards */ - (reg_01.entries != 0x1b) && /* Compaq Proliant boards */ - (reg_01.entries != 0x1f) && /* dual Xeon boards */ - (reg_01.entries != 0x22) && /* bigger Xeon boards */ - (reg_01.entries != 0x2E) && - (reg_01.entries != 0x3F) + printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw); + printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); + if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */ + (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */ + (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */ + (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */ + (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */ + (reg_01.bits.entries != 0x2E) && + (reg_01.bits.entries != 0x3F) ) UNEXPECTED_IO_APIC(); - printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.PRQ); - printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.version); - if ( (reg_01.version != 0x01) && /* 82489DX IO-APICs */ - (reg_01.version != 0x10) && /* oldest IO-APICs */ - (reg_01.version != 0x11) && /* Pentium/Pro IO-APICs */ - (reg_01.version != 0x13) && /* Xeon IO-APICs */ - (reg_01.version != 0x20) /* Intel P64H (82806 AA) */ + printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); + printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); + if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */ + (reg_01.bits.version != 0x10) && /* oldest IO-APICs */ + (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */ + (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */ + (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */ ) UNEXPECTED_IO_APIC(); - if (reg_01.__reserved_1 || reg_01.__reserved_2) + if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2) UNEXPECTED_IO_APIC(); - if (reg_01.version >= 0x10) { - printk(KERN_DEBUG ".... register #02: %08X\n", *(int *)®_02); - printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.arbitration); - if (reg_02.__reserved_1 || reg_02.__reserved_2) + /* + * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, + * but the value of reg_02 is read as the previous read register + * value, so ignore it if reg_02 == reg_01. + */ + if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { + printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); + printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); + if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2) + UNEXPECTED_IO_APIC(); + } + + /* + * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 + * or reg_03, but the value of reg_0[23] is read as the previous read + * register value, so ignore it if reg_03 == reg_0[12]. + */ + if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && + reg_03.raw != reg_01.raw) { + printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); + printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); + if (reg_03.bits.__reserved_1) UNEXPECTED_IO_APIC(); } @@ -1344,7 +1365,7 @@ void __init print_IO_APIC(void) printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" " Stat Dest Deli Vect: \n"); - for (i = 0; i <= reg_01.entries; i++) { + for (i = 0; i <= reg_01.bits.entries; i++) { struct IO_APIC_route_entry entry; spin_lock_irqsave(&ioapic_lock, flags); @@ -1525,7 +1546,7 @@ void /*__init*/ print_PIC(void) static void __init enable_IO_APIC(void) { - struct IO_APIC_reg_01 reg_01; + union IO_APIC_reg_01 reg_01; int i; unsigned long flags; @@ -1542,9 +1563,9 @@ static void __init enable_IO_APIC(void) */ for (i = 0; i < nr_ioapics; i++) { spin_lock_irqsave(&ioapic_lock, flags); - *(int *)®_01 = io_apic_read(i, 1); + reg_01.raw = io_apic_read(i, 1); spin_unlock_irqrestore(&ioapic_lock, flags); - nr_ioapic_registers[i] = reg_01.entries+1; + nr_ioapic_registers[i] = reg_01.bits.entries+1; } /* @@ -1576,7 +1597,7 @@ void disable_IO_APIC(void) #ifndef CONFIG_X86_NUMAQ static void __init setup_ioapic_ids_from_mpc(void) { - struct IO_APIC_reg_00 reg_00; + union IO_APIC_reg_00 reg_00; unsigned long phys_id_present_map; int apic; int i; @@ -1596,7 +1617,7 @@ static void __init setup_ioapic_ids_from /* Read the register 0 value */ spin_lock_irqsave(&ioapic_lock, flags); - *(int *)®_00 = io_apic_read(apic, 0); + reg_00.raw = io_apic_read(apic, 0); spin_unlock_irqrestore(&ioapic_lock, flags); old_id = mp_ioapics[apic].mpc_apicid; @@ -1605,8 +1626,8 @@ static void __init setup_ioapic_ids_from printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", apic, mp_ioapics[apic].mpc_apicid); printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", - reg_00.ID); - mp_ioapics[apic].mpc_apicid = reg_00.ID; + reg_00.bits.ID); + mp_ioapics[apic].mpc_apicid = reg_00.bits.ID; } /* @@ -1650,18 +1671,18 @@ static void __init setup_ioapic_ids_from printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...", mp_ioapics[apic].mpc_apicid); - reg_00.ID = mp_ioapics[apic].mpc_apicid; + reg_00.bits.ID = mp_ioapics[apic].mpc_apicid; spin_lock_irqsave(&ioapic_lock, flags); - io_apic_write(apic, 0, *(int *)®_00); + io_apic_write(apic, 0, reg_00.raw); spin_unlock_irqrestore(&ioapic_lock, flags); /* * Sanity check */ spin_lock_irqsave(&ioapic_lock, flags); - *(int *)®_00 = io_apic_read(apic, 0); + reg_00.raw = io_apic_read(apic, 0); spin_unlock_irqrestore(&ioapic_lock, flags); - if (reg_00.ID != mp_ioapics[apic].mpc_apicid) + if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) panic("could not set ID!\n"); else printk(" ok.\n"); @@ -2032,7 +2053,6 @@ static inline void unlock_ExtINT_logic(v */ static inline void check_timer(void) { - extern int timer_ack; int pin1, pin2; int vector; @@ -2199,7 +2219,7 @@ late_initcall(io_apic_bug_finalize); int __init io_apic_get_unique_id (int ioapic, int apic_id) { - struct IO_APIC_reg_00 reg_00; + union IO_APIC_reg_00 reg_00; static unsigned long apic_id_map = 0; unsigned long flags; int i = 0; @@ -2217,13 +2237,13 @@ int __init io_apic_get_unique_id (int io apic_id_map = phys_cpu_present_map; spin_lock_irqsave(&ioapic_lock, flags); - *(int *)®_00 = io_apic_read(ioapic, 0); + reg_00.raw = io_apic_read(ioapic, 0); spin_unlock_irqrestore(&ioapic_lock, flags); if (apic_id >= IO_APIC_MAX_ID) { printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " - "%d\n", ioapic, apic_id, reg_00.ID); - apic_id = reg_00.ID; + "%d\n", ioapic, apic_id, reg_00.bits.ID); + apic_id = reg_00.bits.ID; } /* @@ -2248,16 +2268,16 @@ int __init io_apic_get_unique_id (int io apic_id_map |= apicid_to_cpu_present(apic_id); - if (reg_00.ID != apic_id) { - reg_00.ID = apic_id; + if (reg_00.bits.ID != apic_id) { + reg_00.bits.ID = apic_id; spin_lock_irqsave(&ioapic_lock, flags); - io_apic_write(ioapic, 0, *(int *)®_00); - *(int *)®_00 = io_apic_read(ioapic, 0); + io_apic_write(ioapic, 0, reg_00.raw); + reg_00.raw = io_apic_read(ioapic, 0); spin_unlock_irqrestore(&ioapic_lock, flags); /* Sanity check */ - if (reg_00.ID != apic_id) + if (reg_00.bits.ID != apic_id) panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic); } @@ -2269,27 +2289,27 @@ int __init io_apic_get_unique_id (int io int __init io_apic_get_version (int ioapic) { - struct IO_APIC_reg_01 reg_01; + union IO_APIC_reg_01 reg_01; unsigned long flags; spin_lock_irqsave(&ioapic_lock, flags); - *(int *)®_01 = io_apic_read(ioapic, 1); + reg_01.raw = io_apic_read(ioapic, 1); spin_unlock_irqrestore(&ioapic_lock, flags); - return reg_01.version; + return reg_01.bits.version; } int __init io_apic_get_redir_entries (int ioapic) { - struct IO_APIC_reg_01 reg_01; + union IO_APIC_reg_01 reg_01; unsigned long flags; spin_lock_irqsave(&ioapic_lock, flags); - *(int *)®_01 = io_apic_read(ioapic, 1); + reg_01.raw = io_apic_read(ioapic, 1); spin_unlock_irqrestore(&ioapic_lock, flags); - return reg_01.entries; + return reg_01.bits.entries; } --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/i386/kernel/kgdb_stub.c 2003-06-27 15:56:26.000000000 -0700 @@ -0,0 +1,2214 @@ +/* + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2, or (at your option) any + * later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + */ + +/* + * Copyright (c) 2000 VERITAS Software Corporation. + * + */ +/**************************************************************************** + * Header: remcom.c,v 1.34 91/03/09 12:29:49 glenne Exp $ + * + * Module name: remcom.c $ + * Revision: 1.34 $ + * Date: 91/03/09 12:29:49 $ + * Contributor: Lake Stevens Instrument Division$ + * + * Description: low level support for gdb debugger. $ + * + * Considerations: only works on target hardware $ + * + * Written by: Glenn Engel $ + * Updated by: David Grothe + * ModuleState: Experimental $ + * + * NOTES: See Below $ + * + * Modified for 386 by Jim Kingdon, Cygnus Support. + * Compatibility with 2.1.xx kernel by David Grothe + * + * Changes to allow auto initilization. All that is needed is that it + * be linked with the kernel and a break point (int 3) be executed. + * The header file defines BREAKPOINT to allow one to do + * this. It should also be possible, once the interrupt system is up, to + * call putDebugChar("+"). Once this is done, the remote debugger should + * get our attention by sending a ^C in a packet. George Anzinger + * + * Integrated into 2.2.5 kernel by Tigran Aivazian + * Added thread support, support for multiple processors, + * support for ia-32(x86) hardware debugging. + * Amit S. Kale ( akale@veritas.com ) + * + * + * To enable debugger support, two things need to happen. One, a + * call to set_debug_traps() is necessary in order to allow any breakpoints + * or error conditions to be properly intercepted and reported to gdb. + * Two, a breakpoint needs to be generated to begin communication. This + * is most easily accomplished by a call to breakpoint(). Breakpoint() + * simulates a breakpoint by executing an int 3. + * + ************* + * + * The following gdb commands are supported: + * + * command function Return value + * + * g return the value of the CPU registers hex data or ENN + * G set the value of the CPU registers OK or ENN + * + * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN + * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN + * + * c Resume at current address SNN ( signal NN) + * cAA..AA Continue at address AA..AA SNN + * + * s Step one instruction SNN + * sAA..AA Step one instruction from AA..AA SNN + * + * k kill + * + * ? What was the last sigval ? SNN (signal NN) + * + * All commands and responses are sent with a packet which includes a + * checksum. A packet consists of + * + * $#. + * + * where + * :: + * :: < two hex digits computed as modulo 256 sum of > + * + * When a packet is received, it is first acknowledged with either '+' or '-'. + * '+' indicates a successful transfer. '-' indicates a failed transfer. + * + * Example: + * + * Host: Reply: + * $m0,10#2a +$00010203040506070809101112131415#42 + * + ****************************************************************************/ +#define KGDB_VERSION "<20030530.0126.22>" +#include +#include +#include /* for strcpy */ +#include +#include +#include +#include +#include /* for linux pt_regs struct */ +#include +#include +#include +#include +#include +#include + +/************************************************************************ + * + * external low-level support routines + */ +typedef void (*Function) (void); /* pointer to a function */ + +/* Thread reference */ +typedef unsigned char threadref[8]; + +extern void putDebugChar(int); /* write a single character */ +extern int getDebugChar(void); /* read and return a single char */ + +/************************************************************************/ +/* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/ +/* at least NUMREGBYTES*2 are needed for register packets */ +/* Longer buffer is needed to list all threads */ +#define BUFMAX 1024 + +char *kgdb_version = KGDB_VERSION; + +/* debug > 0 prints ill-formed commands in valid packets & checksum errors */ +int debug_regs = 0; /* set to non-zero to print registers */ + +/* filled in by an external module */ +char *gdb_module_offsets; + +static const char hexchars[] = "0123456789abcdef"; + +/* Number of bytes of registers. */ +#define NUMREGBYTES 64 +/* + * Note that this register image is in a different order than + * the register image that Linux produces at interrupt time. + * + * Linux's register image is defined by struct pt_regs in ptrace.h. + * Just why GDB uses a different order is a historical mystery. + */ +enum regnames { _EAX, /* 0 */ + _ECX, /* 1 */ + _EDX, /* 2 */ + _EBX, /* 3 */ + _ESP, /* 4 */ + _EBP, /* 5 */ + _ESI, /* 6 */ + _EDI, /* 7 */ + _PC /* 8 also known as eip */ , + _PS /* 9 also known as eflags */ , + _CS, /* 10 */ + _SS, /* 11 */ + _DS, /* 12 */ + _ES, /* 13 */ + _FS, /* 14 */ + _GS /* 15 */ +}; + +/*************************** ASSEMBLY CODE MACROS *************************/ +/* + * Put the error code here just in case the user cares. + * Likewise, the vector number here (since GDB only gets the signal + * number through the usual means, and that's not very specific). + * The called_from is the return address so he can tell how we entered kgdb. + * This will allow him to seperate out the various possible entries. + */ +#define REMOTE_DEBUG 0 /* set != to turn on printing (also available in info) */ + +#define PID_MAX PID_MAX_DEFAULT + +#ifdef CONFIG_SMP +void smp_send_nmi_allbutself(void); +#define IF_SMP(x) x +#undef MAX_NO_CPUS +#ifndef CONFIG_NO_KGDB_CPUS +#define CONFIG_NO_KGDB_CPUS 2 +#endif +#if CONFIG_NO_KGDB_CPUS > NR_CPUS +#define MAX_NO_CPUS NR_CPUS +#else +#define MAX_NO_CPUS CONFIG_NO_KGDB_CPUS +#endif +#define hold_init hold_on_sstep: 1, +#define MAX_CPU_MASK (unsigned long)((1LL << MAX_NO_CPUS) - 1LL) +#define NUM_CPUS num_online_cpus() +extern volatile unsigned long cpu_callout_map; +#else +#define IF_SMP(x) +#define hold_init +#undef MAX_NO_CPUS +#define MAX_NO_CPUS 1 +#define NUM_CPUS 1 +#endif +#define NOCPU (struct task_struct *)0xbad1fbad +/* *INDENT-OFF* */ +struct kgdb_info { + int used_malloc; + void *called_from; + long long entry_tsc; + int errcode; + int vector; + int print_debug_info; +#ifdef CONFIG_SMP + int hold_on_sstep; + struct { + volatile struct task_struct *task; + int pid; + int hold; + struct pt_regs *regs; + } cpus_waiting[MAX_NO_CPUS]; +#endif +} kgdb_info = {hold_init print_debug_info:REMOTE_DEBUG, vector:-1}; + +/* *INDENT-ON* */ + +#define used_m kgdb_info.used_malloc +/* + * This is little area we set aside to contain the stack we + * need to build to allow gdb to call functions. We use one + * per cpu to avoid locking issues. We will do all this work + * with interrupts off so that should take care of the protection + * issues. + */ +#define LOOKASIDE_SIZE 200 /* should be more than enough */ +#define MALLOC_MAX 200 /* Max malloc size */ +struct { + unsigned int esp; + int array[LOOKASIDE_SIZE]; +} fn_call_lookaside[MAX_NO_CPUS]; + +static int trap_cpu; +static unsigned int OLD_esp; + +#define END_OF_LOOKASIDE &fn_call_lookaside[trap_cpu].array[LOOKASIDE_SIZE] +#define IF_BIT 0x200 +#define TF_BIT 0x100 + +#define MALLOC_ROUND 8-1 + +static char malloc_array[MALLOC_MAX]; +IF_SMP(static void to_gdb(const char *mess)); +void * +malloc(int size) +{ + + if (size <= (MALLOC_MAX - used_m)) { + int old_used = used_m; + used_m += ((size + MALLOC_ROUND) & (~MALLOC_ROUND)); + return &malloc_array[old_used]; + } else { + return NULL; + } +} + +/* + * Gdb calls functions by pushing agruments, including a return address + * on the stack and the adjusting EIP to point to the function. The + * whole assumption in GDB is that we are on a different stack than the + * one the "user" i.e. code that hit the break point, is on. This, of + * course is not true in the kernel. Thus various dodges are needed to + * do the call without directly messing with EIP (which we can not change + * as it is just a location and not a register. To adjust it would then + * require that we move every thing below EIP up or down as needed. This + * will not work as we may well have stack relative pointer on the stack + * (such as the pointer to regs, for example). + + * So here is what we do: + * We detect gdb attempting to store into the stack area and instead, store + * into the fn_call_lookaside.array at the same relative location as if it + * were the area ESP pointed at. We also trap ESP modifications + * and uses these to adjust fn_call_lookaside.esp. On entry + * fn_call_lookaside.esp will be set to point at the last entry in + * fn_call_lookaside.array. This allows us to check if it has changed, and + * if so, on exit, we add the registers we will use to do the move and a + * trap/ interrupt return exit sequence. We then adjust the eflags in the + * regs array (remember we now have a copy in the fn_call_lookaside.array) to + * kill the interrupt bit, AND we change EIP to point at our set up stub. + * As part of the register set up we preset the registers to point at the + * begining and end of the fn_call_lookaside.array, so all the stub needs to + * do is move words from the array to the stack until ESP= the desired value + * then do the rti. This will then transfer to the desired function with + * all the correct registers. Nifty huh? + */ +extern asmlinkage void fn_call_stub(void); +extern asmlinkage void fn_rtn_stub(void); +/* *INDENT-OFF* */ +__asm__("fn_rtn_stub:\n\t" + "movl %eax,%esp\n\t" + "fn_call_stub:\n\t" + "1:\n\t" + "addl $-4,%ebx\n\t" + "movl (%ebx), %eax\n\t" + "pushl %eax\n\t" + "cmpl %esp,%ecx\n\t" + "jne 1b\n\t" + "popl %eax\n\t" + "popl %ebx\n\t" + "popl %ecx\n\t" + "iret \n\t"); +/* *INDENT-ON* */ +#define gdb_i386vector kgdb_info.vector +#define gdb_i386errcode kgdb_info.errcode +#define waiting_cpus kgdb_info.cpus_waiting +#define remote_debug kgdb_info.print_debug_info +#define hold_cpu(cpu) kgdb_info.cpus_waiting[cpu].hold +/* gdb locks */ + +#ifdef CONFIG_SMP +static int in_kgdb_called; +static spinlock_t waitlocks[MAX_NO_CPUS] = + {[0 ... MAX_NO_CPUS - 1] = SPIN_LOCK_UNLOCKED }; +/* + * The following array has the thread pointer of each of the "other" + * cpus. We make it global so it can be seen by gdb. + */ +volatile int in_kgdb_entry_log[MAX_NO_CPUS]; +volatile struct pt_regs *in_kgdb_here_log[MAX_NO_CPUS]; +/* +static spinlock_t continuelocks[MAX_NO_CPUS]; +*/ +spinlock_t kgdb_spinlock = SPIN_LOCK_UNLOCKED; +/* waiters on our spinlock plus us */ +static atomic_t spinlock_waiters = ATOMIC_INIT(1); +static int spinlock_count = 0; +static int spinlock_cpu = 0; +/* + * Note we use nested spin locks to account for the case where a break + * point is encountered when calling a function by user direction from + * kgdb. Also there is the memory exception recursion to account for. + * Well, yes, but this lets other cpus thru too. Lets add a + * cpu id to the lock. + */ +#define KGDB_SPIN_LOCK(x) if( spinlock_count == 0 || \ + spinlock_cpu != smp_processor_id()){\ + atomic_inc(&spinlock_waiters); \ + while (! spin_trylock(x)) {\ + in_kgdb(®s);\ + }\ + atomic_dec(&spinlock_waiters); \ + spinlock_count = 1; \ + spinlock_cpu = smp_processor_id(); \ + }else{ \ + spinlock_count++; \ + } +#define KGDB_SPIN_UNLOCK(x) if( --spinlock_count == 0) spin_unlock(x) +extern volatile unsigned long cpu_callout_map; +#else +unsigned kgdb_spinlock = 0; +#define KGDB_SPIN_LOCK(x) --*x +#define KGDB_SPIN_UNLOCK(x) ++*x +#endif + +int +hex(char ch) +{ + if ((ch >= 'a') && (ch <= 'f')) + return (ch - 'a' + 10); + if ((ch >= '0') && (ch <= '9')) + return (ch - '0'); + if ((ch >= 'A') && (ch <= 'F')) + return (ch - 'A' + 10); + return (-1); +} + +/* scan for the sequence $# */ +void +getpacket(char *buffer) +{ + unsigned char checksum; + unsigned char xmitcsum; + int i; + int count; + char ch; + + do { + /* wait around for the start character, ignore all other characters */ + while ((ch = (getDebugChar() & 0x7f)) != '$') ; + checksum = 0; + xmitcsum = -1; + + count = 0; + + /* now, read until a # or end of buffer is found */ + while (count < BUFMAX) { + ch = getDebugChar() & 0x7f; + if (ch == '#') + break; + checksum = checksum + ch; + buffer[count] = ch; + count = count + 1; + } + buffer[count] = 0; + + if (ch == '#') { + xmitcsum = hex(getDebugChar() & 0x7f) << 4; + xmitcsum += hex(getDebugChar() & 0x7f); + if ((remote_debug) && (checksum != xmitcsum)) { + printk + ("bad checksum. My count = 0x%x, sent=0x%x. buf=%s\n", + checksum, xmitcsum, buffer); + } + + if (checksum != xmitcsum) + putDebugChar('-'); /* failed checksum */ + else { + putDebugChar('+'); /* successful transfer */ + /* if a sequence char is present, reply the sequence ID */ + if (buffer[2] == ':') { + putDebugChar(buffer[0]); + putDebugChar(buffer[1]); + /* remove sequence chars from buffer */ + count = strlen(buffer); + for (i = 3; i <= count; i++) + buffer[i - 3] = buffer[i]; + } + } + } + } while (checksum != xmitcsum); + + if (remote_debug) + printk("R:%s\n", buffer); +} + +/* send the packet in buffer. */ + +void +putpacket(char *buffer) +{ + unsigned char checksum; + int count; + char ch; + + /* $#. */ + do { + if (remote_debug) + printk("T:%s\n", buffer); + putDebugChar('$'); + checksum = 0; + count = 0; + + while ((ch = buffer[count])) { + putDebugChar(ch); + checksum += ch; + count += 1; + } + + putDebugChar('#'); + putDebugChar(hexchars[checksum >> 4]); + putDebugChar(hexchars[checksum % 16]); + + } while ((getDebugChar() & 0x7f) != '+'); + +} + +static char remcomInBuffer[BUFMAX]; +static char remcomOutBuffer[BUFMAX]; +static short error; + +void +debug_error(char *format, char *parm) +{ + if (remote_debug) + printk(format, parm); +} + +static void +print_regs(struct pt_regs *regs) +{ + printk("EAX=%08lx ", regs->eax); + printk("EBX=%08lx ", regs->ebx); + printk("ECX=%08lx ", regs->ecx); + printk("EDX=%08lx ", regs->edx); + printk("\n"); + printk("ESI=%08lx ", regs->esi); + printk("EDI=%08lx ", regs->edi); + printk("EBP=%08lx ", regs->ebp); + printk("ESP=%08lx ", (long) ®s->esp); + printk("\n"); + printk(" DS=%08x ", regs->xds); + printk(" ES=%08x ", regs->xes); + printk(" SS=%08x ", __KERNEL_DS); + printk(" FL=%08lx ", regs->eflags); + printk("\n"); + printk(" CS=%08x ", regs->xcs); + printk(" IP=%08lx ", regs->eip); +#if 0 + printk(" FS=%08x ", regs->fs); + printk(" GS=%08x ", regs->gs); +#endif + printk("\n"); + +} /* print_regs */ + +#define NEW_esp fn_call_lookaside[trap_cpu].esp + +static void +regs_to_gdb_regs(int *gdb_regs, struct pt_regs *regs) +{ + gdb_regs[_EAX] = regs->eax; + gdb_regs[_EBX] = regs->ebx; + gdb_regs[_ECX] = regs->ecx; + gdb_regs[_EDX] = regs->edx; + gdb_regs[_ESI] = regs->esi; + gdb_regs[_EDI] = regs->edi; + gdb_regs[_EBP] = regs->ebp; + gdb_regs[_DS] = regs->xds; + gdb_regs[_ES] = regs->xes; + gdb_regs[_PS] = regs->eflags; + gdb_regs[_CS] = regs->xcs; + gdb_regs[_PC] = regs->eip; + /* Note, as we are a debugging the kernel, we will always + * trap in kernel code, this means no priviledge change, + * and so the pt_regs structure is not completely valid. In a non + * privilege change trap, only EFLAGS, CS and EIP are put on the stack, + * SS and ESP are not stacked, this means that the last 2 elements of + * pt_regs is not valid (they would normally refer to the user stack) + * also, using regs+1 is no good because you end up will a value that is + * 2 longs (8) too high. This used to cause stepping over functions + * to fail, so my fix is to use the address of regs->esp, which + * should point at the end of the stack frame. Note I have ignored + * completely exceptions that cause an error code to be stacked, such + * as double fault. Stuart Hughes, Zentropix. + * original code: gdb_regs[_ESP] = (int) (regs + 1) ; + + * this is now done on entry and moved to OLD_esp (as well as NEW_esp). + */ + gdb_regs[_ESP] = NEW_esp; + gdb_regs[_SS] = __KERNEL_DS; + gdb_regs[_FS] = 0xFFFF; + gdb_regs[_GS] = 0xFFFF; +} /* regs_to_gdb_regs */ + +static void +gdb_regs_to_regs(int *gdb_regs, struct pt_regs *regs) +{ + regs->eax = gdb_regs[_EAX]; + regs->ebx = gdb_regs[_EBX]; + regs->ecx = gdb_regs[_ECX]; + regs->edx = gdb_regs[_EDX]; + regs->esi = gdb_regs[_ESI]; + regs->edi = gdb_regs[_EDI]; + regs->ebp = gdb_regs[_EBP]; + regs->xds = gdb_regs[_DS]; + regs->xes = gdb_regs[_ES]; + regs->eflags = gdb_regs[_PS]; + regs->xcs = gdb_regs[_CS]; + regs->eip = gdb_regs[_PC]; + NEW_esp = gdb_regs[_ESP]; /* keep the value */ +#if 0 /* can't change these */ + regs->esp = gdb_regs[_ESP]; + regs->xss = gdb_regs[_SS]; + regs->fs = gdb_regs[_FS]; + regs->gs = gdb_regs[_GS]; +#endif + +} /* gdb_regs_to_regs */ +extern void scheduling_functions_start_here(void); +extern void scheduling_functions_end_here(void); +#define first_sched ((unsigned long) scheduling_functions_start_here) +#define last_sched ((unsigned long) scheduling_functions_end_here) + +int thread_list = 0; + +void +get_gdb_regs(struct task_struct *p, struct pt_regs *regs, int *gdb_regs) +{ + unsigned long stack_page; + int count = 0; + IF_SMP(int i); + if (!p || p == current) { + regs_to_gdb_regs(gdb_regs, regs); + return; + } +#ifdef CONFIG_SMP + for (i = 0; i < MAX_NO_CPUS; i++) { + if (p == kgdb_info.cpus_waiting[i].task) { + regs_to_gdb_regs(gdb_regs, + kgdb_info.cpus_waiting[i].regs); + gdb_regs[_ESP] = + (int) &kgdb_info.cpus_waiting[i].regs->esp; + + return; + } + } +#endif + memset(gdb_regs, 0, NUMREGBYTES); + gdb_regs[_ESP] = p->thread.esp; + gdb_regs[_PC] = p->thread.eip; + gdb_regs[_EBP] = *(int *) gdb_regs[_ESP]; + gdb_regs[_EDI] = *(int *) (gdb_regs[_ESP] + 4); + gdb_regs[_ESI] = *(int *) (gdb_regs[_ESP] + 8); + +/* + * This code is to give a more informative notion of where a process + * is waiting. It is used only when the user asks for a thread info + * list. If he then switches to the thread, s/he will find the task + * is in schedule, but a back trace should show the same info we come + * up with. This code was shamelessly purloined from process.c. It was + * then enhanced to provide more registers than simply the program + * counter. + */ + + if (!thread_list) { + return; + } + + if (p->state == TASK_RUNNING) + return; + stack_page = (unsigned long) p->thread_info; + if (gdb_regs[_ESP] < stack_page || gdb_regs[_ESP] > 8188 + stack_page) + return; + /* include/asm-i386/system.h:switch_to() pushes ebp last. */ + do { + if (gdb_regs[_EBP] < stack_page || + gdb_regs[_EBP] > 8184 + stack_page) + return; + gdb_regs[_PC] = *(unsigned long *) (gdb_regs[_EBP] + 4); + gdb_regs[_ESP] = gdb_regs[_EBP] + 8; + gdb_regs[_EBP] = *(unsigned long *) gdb_regs[_EBP]; + if (gdb_regs[_PC] < first_sched || gdb_regs[_PC] >= last_sched) + return; + } while (count++ < 16); + return; +} + +/* Indicate to caller of mem2hex or hex2mem that there has been an + error. */ +static volatile int mem_err = 0; +static volatile int mem_err_expected = 0; +static volatile int mem_err_cnt = 0; +static int garbage_loc = -1; + +int +get_char(char *addr) +{ + return *addr; +} + +void +set_char(char *addr, int val, int may_fault) +{ + /* + * This code traps references to the area mapped to the kernel + * stack as given by the regs and, instead, stores to the + * fn_call_lookaside[cpu].array + */ + if (may_fault && + (unsigned int) addr < OLD_esp && + ((unsigned int) addr > (OLD_esp - (unsigned int) LOOKASIDE_SIZE))) { + addr = (char *) END_OF_LOOKASIDE - ((char *) OLD_esp - addr); + } + *addr = val; +} + +/* convert the memory pointed to by mem into hex, placing result in buf */ +/* return a pointer to the last char put in buf (null) */ +/* If MAY_FAULT is non-zero, then we should set mem_err in response to + a fault; if zero treat a fault like any other fault in the stub. */ +char * +mem2hex(char *mem, char *buf, int count, int may_fault) +{ + int i; + unsigned char ch; + + if (may_fault) { + mem_err_expected = 1; + mem_err = 0; + } + for (i = 0; i < count; i++) { + /* printk("%lx = ", mem) ; */ + + ch = get_char(mem++); + + /* printk("%02x\n", ch & 0xFF) ; */ + if (may_fault && mem_err) { + if (remote_debug) + printk("Mem fault fetching from addr %lx\n", + (long) (mem - 1)); + *buf = 0; /* truncate buffer */ + return (buf); + } + *buf++ = hexchars[ch >> 4]; + *buf++ = hexchars[ch % 16]; + } + *buf = 0; + if (may_fault) + mem_err_expected = 0; + return (buf); +} + +/* convert the hex array pointed to by buf into binary to be placed in mem */ +/* return a pointer to the character AFTER the last byte written */ +/* NOTE: We use the may fault flag to also indicate if the write is to + * the registers (0) or "other" memory (!=0) + */ +char * +hex2mem(char *buf, char *mem, int count, int may_fault) +{ + int i; + unsigned char ch; + + if (may_fault) { + mem_err_expected = 1; + mem_err = 0; + } + for (i = 0; i < count; i++) { + ch = hex(*buf++) << 4; + ch = ch + hex(*buf++); + set_char(mem++, ch, may_fault); + + if (may_fault && mem_err) { + if (remote_debug) + printk("Mem fault storing to addr %lx\n", + (long) (mem - 1)); + return (mem); + } + } + if (may_fault) + mem_err_expected = 0; + return (mem); +} + +/**********************************************/ +/* WHILE WE FIND NICE HEX CHARS, BUILD AN INT */ +/* RETURN NUMBER OF CHARS PROCESSED */ +/**********************************************/ +int +hexToInt(char **ptr, int *intValue) +{ + int numChars = 0; + int hexValue; + + *intValue = 0; + + while (**ptr) { + hexValue = hex(**ptr); + if (hexValue >= 0) { + *intValue = (*intValue << 4) | hexValue; + numChars++; + } else + break; + + (*ptr)++; + } + + return (numChars); +} + +#define stubhex(h) hex(h) + +static int +stub_unpack_int(char *buff, int fieldlength) +{ + int nibble; + int retval = 0; + + while (fieldlength) { + nibble = stubhex(*buff++); + retval |= nibble; + fieldlength--; + if (fieldlength) + retval = retval << 4; + } + return retval; +} + +static char * +pack_hex_byte(char *pkt, int byte) +{ + *pkt++ = hexchars[(byte >> 4) & 0xf]; + *pkt++ = hexchars[(byte & 0xf)]; + return pkt; +} + +#define BUF_THREAD_ID_SIZE 16 + +static char * +pack_threadid(char *pkt, threadref * id) +{ + char *limit; + unsigned char *altid; + + altid = (unsigned char *) id; + limit = pkt + BUF_THREAD_ID_SIZE; + while (pkt < limit) + pkt = pack_hex_byte(pkt, *altid++); + return pkt; +} + +static char * +unpack_byte(char *buf, int *value) +{ + *value = stub_unpack_int(buf, 2); + return buf + 2; +} + +static char * +unpack_threadid(char *inbuf, threadref * id) +{ + char *altref; + char *limit = inbuf + BUF_THREAD_ID_SIZE; + int x, y; + + altref = (char *) id; + + while (inbuf < limit) { + x = stubhex(*inbuf++); + y = stubhex(*inbuf++); + *altref++ = (x << 4) | y; + } + return inbuf; +} + +void +int_to_threadref(threadref * id, int value) +{ + unsigned char *scan; + + scan = (unsigned char *) id; + { + int i = 4; + while (i--) + *scan++ = 0; + } + *scan++ = (value >> 24) & 0xff; + *scan++ = (value >> 16) & 0xff; + *scan++ = (value >> 8) & 0xff; + *scan++ = (value & 0xff); +} + +static int +threadref_to_int(threadref * ref) +{ + int i, value = 0; + unsigned char *scan; + + scan = (char *) ref; + scan += 4; + i = 4; + while (i-- > 0) + value = (value << 8) | ((*scan++) & 0xff); + return value; +} + +#if 1 /* this is a hold over from 2.4 where O(1) was "sometimes" */ +extern struct task_struct *kgdb_get_idle(int cpu); +#define idle_task(cpu) kgdb_get_idle(cpu) +#else +#define idle_task(cpu) init_tasks[cpu] +#endif + +struct task_struct * +getthread(int pid) +{ + struct task_struct *thread; + if (pid >= PID_MAX && pid <= (PID_MAX + MAX_NO_CPUS)) { + + return idle_task(pid - PID_MAX); + } else { + /* + * find_task_by_pid is relatively safe all the time + * Other pid functions require lock downs which imply + * that we may be interrupting them (as we get here + * in the middle of most any lock down) + */ + thread = find_task_by_pid(pid); + if (thread) { + return thread; + } + } + return NULL; +} +/* *INDENT-OFF* */ +struct hw_breakpoint { + unsigned enabled; + unsigned type; + unsigned len; + unsigned addr; +} breakinfo[4] = { {enabled:0}, + {enabled:0}, + {enabled:0}, + {enabled:0}}; +/* *INDENT-ON* */ +unsigned hw_breakpoint_status; +void +correct_hw_break(void) +{ + int breakno; + int correctit; + int breakbit; + unsigned dr7; + + asm volatile ("movl %%db7, %0\n":"=r" (dr7) + :); + /* *INDENT-OFF* */ + do { + unsigned addr0, addr1, addr2, addr3; + asm volatile ("movl %%db0, %0\n" + "movl %%db1, %1\n" + "movl %%db2, %2\n" + "movl %%db3, %3\n" + :"=r" (addr0), "=r"(addr1), + "=r"(addr2), "=r"(addr3) + :); + } while (0); + /* *INDENT-ON* */ + correctit = 0; + for (breakno = 0; breakno < 3; breakno++) { + breakbit = 2 << (breakno << 1); + if (!(dr7 & breakbit) && breakinfo[breakno].enabled) { + correctit = 1; + dr7 |= breakbit; + dr7 &= ~(0xf0000 << (breakno << 2)); + dr7 |= (((breakinfo[breakno].len << 2) | + breakinfo[breakno].type) << 16) << + (breakno << 2); + switch (breakno) { + case 0: + asm volatile ("movl %0, %%dr0\n"::"r" + (breakinfo[breakno].addr)); + break; + + case 1: + asm volatile ("movl %0, %%dr1\n"::"r" + (breakinfo[breakno].addr)); + break; + + case 2: + asm volatile ("movl %0, %%dr2\n"::"r" + (breakinfo[breakno].addr)); + break; + + case 3: + asm volatile ("movl %0, %%dr3\n"::"r" + (breakinfo[breakno].addr)); + break; + } + } else if ((dr7 & breakbit) && !breakinfo[breakno].enabled) { + correctit = 1; + dr7 &= ~breakbit; + dr7 &= ~(0xf0000 << (breakno << 2)); + } + } + if (correctit) { + asm volatile ("movl %0, %%db7\n"::"r" (dr7)); + } +} + +int +remove_hw_break(unsigned breakno) +{ + if (!breakinfo[breakno].enabled) { + return -1; + } + breakinfo[breakno].enabled = 0; + return 0; +} + +int +set_hw_break(unsigned breakno, unsigned type, unsigned len, unsigned addr) +{ + if (breakinfo[breakno].enabled) { + return -1; + } + breakinfo[breakno].enabled = 1; + breakinfo[breakno].type = type; + breakinfo[breakno].len = len; + breakinfo[breakno].addr = addr; + return 0; +} + +#ifdef CONFIG_SMP +static int in_kgdb_console = 0; + +int +in_kgdb(struct pt_regs *regs) +{ + unsigned flags; + int cpu = smp_processor_id(); + in_kgdb_called = 1; + if (!spin_is_locked(&kgdb_spinlock)) { + if (in_kgdb_here_log[cpu] || /* we are holding this cpu */ + in_kgdb_console) { /* or we are doing slow i/o */ + return 1; + } + return 0; + } + + /* As I see it the only reason not to let all cpus spin on + * the same spin_lock is to allow selected ones to proceed. + * This would be a good thing, so we leave it this way. + * Maybe someday.... Done ! + + * in_kgdb() is called from an NMI so we don't pretend + * to have any resources, like printk() for example. + */ + + kgdb_local_irq_save(flags); /* only local here, to avoid hanging */ + /* + * log arival of this cpu + * The NMI keeps on ticking. Protect against recurring more + * than once, and ignor the cpu that has the kgdb lock + */ + in_kgdb_entry_log[cpu]++; + in_kgdb_here_log[cpu] = regs; + if (cpu == spinlock_cpu || waiting_cpus[cpu].task) { + goto exit_in_kgdb; + } + /* + * For protection of the initilization of the spin locks by kgdb + * it locks the kgdb spinlock before it gets the wait locks set + * up. We wait here for the wait lock to be taken. If the + * kgdb lock goes away first?? Well, it could be a slow exit + * sequence where the wait lock is removed prior to the kgdb lock + * so if kgdb gets unlocked, we just exit. + */ + while (spin_is_locked(&kgdb_spinlock) && + !spin_is_locked(waitlocks + cpu)) ; + if (!spin_is_locked(&kgdb_spinlock)) { + goto exit_in_kgdb; + } + waiting_cpus[cpu].task = current; + waiting_cpus[cpu].pid = (current->pid) ? : (PID_MAX + cpu); + waiting_cpus[cpu].regs = regs; + + spin_unlock_wait(waitlocks + cpu); + /* + * log departure of this cpu + */ + waiting_cpus[cpu].task = 0; + waiting_cpus[cpu].pid = 0; + waiting_cpus[cpu].regs = 0; + correct_hw_break(); + exit_in_kgdb: + in_kgdb_here_log[cpu] = 0; + kgdb_local_irq_restore(flags); + return 1; + /* + spin_unlock(continuelocks + smp_processor_id()); + */ +} + +void +smp__in_kgdb(struct pt_regs regs) +{ + ack_APIC_irq(); + in_kgdb(®s); +} +#else +int +in_kgdb(struct pt_regs *regs) +{ + return (kgdb_spinlock); +} +#endif + +void +printexceptioninfo(int exceptionNo, int errorcode, char *buffer) +{ + unsigned dr6; + int i; + switch (exceptionNo) { + case 1: /* debug exception */ + break; + case 3: /* breakpoint */ + sprintf(buffer, "Software breakpoint"); + return; + default: + sprintf(buffer, "Details not available"); + return; + } + asm volatile ("movl %%db6, %0\n":"=r" (dr6) + :); + if (dr6 & 0x4000) { + sprintf(buffer, "Single step"); + return; + } + for (i = 0; i < 4; ++i) { + if (dr6 & (1 << i)) { + sprintf(buffer, "Hardware breakpoint %d", i); + return; + } + } + sprintf(buffer, "Unknown trap"); + return; +} + +/* + * This function does all command procesing for interfacing to gdb. + * + * NOTE: The INT nn instruction leaves the state of the interrupt + * enable flag UNCHANGED. That means that when this routine + * is entered via a breakpoint (INT 3) instruction from code + * that has interrupts enabled, then interrupts will STILL BE + * enabled when this routine is entered. The first thing that + * we do here is disable interrupts so as to prevent recursive + * entries and bothersome serial interrupts while we are + * trying to run the serial port in polled mode. + * + * For kernel version 2.1.xx the kgdb_cli() actually gets a spin lock so + * it is always necessary to do a restore_flags before returning + * so as to let go of that lock. + */ +int +kgdb_handle_exception(int exceptionVector, + int signo, int err_code, struct pt_regs *linux_regs) +{ + struct task_struct *usethread = NULL; + struct task_struct *thread_list_start = 0, *thread = NULL; + int addr, length; + int breakno, breaktype; + char *ptr; + int newPC; + threadref thref; + int threadid; + int thread_min = PID_MAX + MAX_NO_CPUS; + int maxthreads; + int nothreads; + unsigned long flags; + int gdb_regs[NUMREGBYTES / 4]; + int dr6; + IF_SMP(int entry_state = 0); /* 0, ok, 1, no nmi, 2 sync failed */ +#define NO_NMI 1 +#define NO_SYNC 2 +#define regs (*linux_regs) +#define NUMREGS NUMREGBYTES/4 + /* + * If the entry is not from the kernel then return to the Linux + * trap handler and let it process the interrupt normally. + */ + if ((linux_regs->eflags & VM_MASK) || (3 & linux_regs->xcs)) { + printk("ignoring non-kernel exception\n"); + print_regs(®s); + return (0); + } + + kgdb_local_irq_save(flags); + + /* Get kgdb spinlock */ + + KGDB_SPIN_LOCK(&kgdb_spinlock); + rdtscll(kgdb_info.entry_tsc); + /* + * We depend on this spinlock and the NMI watch dog to control the + * other cpus. They will arrive at "in_kgdb()" as a result of the + * NMI and will wait there for the following spin locks to be + * released. + */ +#ifdef CONFIG_SMP + + if (cpu_callout_map & ~MAX_CPU_MASK) { + printk("kgdb : too many cpus, possibly not mapped" + " in contiguous space, change MAX_NO_CPUS" + " in kgdb_stub and make new kernel.\n" + " cpu_callout_map is %lx\n", cpu_callout_map); + goto exit_just_unlock; + } + + if (spinlock_count == 1) { + int time, end_time, dum; + int i; + int cpu_logged_in[MAX_NO_CPUS] = {[0 ... MAX_NO_CPUS - 1] = (0) + }; + if (remote_debug) { + printk("kgdb : cpu %d entry, syncing others\n", + smp_processor_id()); + } + for (i = 0; i < MAX_NO_CPUS; i++) { + /* + * Use trylock as we may already hold the lock if + * we are holding the cpu. Net result is all + * locked. + */ + spin_trylock(&waitlocks[i]); + } + for (i = 0; i < MAX_NO_CPUS; i++) + cpu_logged_in[i] = 0; + /* + * Wait for their arrival. We know the watch dog is active if + * in_kgdb() has ever been called, as it is always called on a + * watchdog tick. + */ + rdtsc(dum, time); + end_time = time + 2; /* Note: we use the High order bits! */ + i = 1; + if (num_online_cpus() > 1) { + int me_in_kgdb = in_kgdb_entry_log[smp_processor_id()]; + smp_send_nmi_allbutself(); + while (i < num_online_cpus() && time != end_time) { + int j; + for (j = 0; j < MAX_NO_CPUS; j++) { + if (waiting_cpus[j].task && + !cpu_logged_in[j]) { + i++; + cpu_logged_in[j] = 1; + if (remote_debug) { + printk + ("kgdb : cpu %d arrived at kgdb\n", + j); + } + break; + } else if (!waiting_cpus[j].task && + !cpu_online(j)) { + waiting_cpus[j].task = NOCPU; + cpu_logged_in[j] = 1; + waiting_cpus[j].hold = 1; + break; + } + if (!waiting_cpus[j].task && + in_kgdb_here_log[j]) { + + int wait = 100000; + while (wait--) ; + if (!waiting_cpus[j].task && + in_kgdb_here_log[j]) { + printk + ("kgdb : cpu %d stall" + " in in_kgdb\n", + j); + i++; + cpu_logged_in[j] = 1; + waiting_cpus[j].task = + (struct task_struct + *) 1; + } + } + } + + if (in_kgdb_entry_log[smp_processor_id()] > + (me_in_kgdb + 10)) { + break; + } + + rdtsc(dum, time); + } + if (i < num_online_cpus()) { + printk + ("kgdb : time out, proceeding without sync\n"); +#if 0 + printk("kgdb : Waiting_cpus: 0 = %d, 1 = %d\n", + waiting_cpus[0].task != 0, + waiting_cpus[1].task != 0); + printk("kgdb : Cpu_logged in: 0 = %d, 1 = %d\n", + cpu_logged_in[0], cpu_logged_in[1]); + printk + ("kgdb : in_kgdb_here_log in: 0 = %d, 1 = %d\n", + in_kgdb_here_log[0] != 0, + in_kgdb_here_log[1] != 0); +#endif + entry_state = NO_SYNC; + } else { +#if 0 + int ent = + in_kgdb_entry_log[smp_processor_id()] - + me_in_kgdb; + printk("kgdb : sync after %d entries\n", ent); +#endif + } + } else { + if (remote_debug) { + printk + ("kgdb : %d cpus, but watchdog not active\n" + "proceeding without locking down other cpus\n", + num_online_cpus()); + entry_state = NO_NMI; + } + } + } +#endif + + if (remote_debug) { + unsigned long *lp = (unsigned long *) &linux_regs; + + printk("handle_exception(exceptionVector=%d, " + "signo=%d, err_code=%d, linux_regs=%p)\n", + exceptionVector, signo, err_code, linux_regs); + if (debug_regs) { + print_regs(®s); + printk("Stk: %8lx %8lx %8lx %8lx" + " %8lx %8lx %8lx %8lx\n", + lp[0], lp[1], lp[2], lp[3], + lp[4], lp[5], lp[6], lp[7]); + printk(" %8lx %8lx %8lx %8lx" + " %8lx %8lx %8lx %8lx\n", + lp[8], lp[9], lp[10], lp[11], + lp[12], lp[13], lp[14], lp[15]); + printk(" %8lx %8lx %8lx %8lx " + "%8lx %8lx %8lx %8lx\n", + lp[16], lp[17], lp[18], lp[19], + lp[20], lp[21], lp[22], lp[23]); + printk(" %8lx %8lx %8lx %8lx " + "%8lx %8lx %8lx %8lx\n", + lp[24], lp[25], lp[26], lp[27], + lp[28], lp[29], lp[30], lp[31]); + } + } + + /* Disable hardware debugging while we are in kgdb */ + /* Get the debug register status register */ +/* *INDENT-OFF* */ + __asm__("movl %0,%%db7" + : /* no output */ + :"r"(0)); + + asm volatile ("movl %%db6, %0\n" + :"=r" (hw_breakpoint_status) + :); + +/* *INDENT-ON* */ + switch (exceptionVector) { + case 0: /* divide error */ + case 1: /* debug exception */ + case 2: /* NMI */ + case 3: /* breakpoint */ + case 4: /* overflow */ + case 5: /* bounds check */ + case 6: /* invalid opcode */ + case 7: /* device not available */ + case 8: /* double fault (errcode) */ + case 10: /* invalid TSS (errcode) */ + case 12: /* stack fault (errcode) */ + case 16: /* floating point error */ + case 17: /* alignment check (errcode) */ + default: /* any undocumented */ + break; + case 11: /* segment not present (errcode) */ + case 13: /* general protection (errcode) */ + case 14: /* page fault (special errcode) */ + case 19: /* cache flush denied */ + if (mem_err_expected) { + /* + * This fault occured because of the + * get_char or set_char routines. These + * two routines use either eax of edx to + * indirectly reference the location in + * memory that they are working with. + * For a page fault, when we return the + * instruction will be retried, so we + * have to make sure that these + * registers point to valid memory. + */ + mem_err = 1; /* set mem error flag */ + mem_err_expected = 0; + mem_err_cnt++; /* helps in debugging */ + /* make valid address */ + regs.eax = (long) &garbage_loc; + /* make valid address */ + regs.edx = (long) &garbage_loc; + if (remote_debug) + printk("Return after memory error: " + "mem_err_cnt=%d\n", mem_err_cnt); + if (debug_regs) + print_regs(®s); + goto exit_kgdb; + } + break; + } + if (remote_debug) + printk("kgdb : entered kgdb on cpu %d\n", smp_processor_id()); + + gdb_i386vector = exceptionVector; + gdb_i386errcode = err_code; + kgdb_info.called_from = __builtin_return_address(0); +#ifdef CONFIG_SMP + /* + * OK, we can now communicate, lets tell gdb about the sync. + * but only if we had a problem. + */ + switch (entry_state) { + case NO_NMI: + to_gdb("NMI not active, other cpus not stopped\n"); + break; + case NO_SYNC: + to_gdb("Some cpus not stopped, see 'kgdb_info' for details\n"); + default:; + } + +#endif +/* + * Set up the gdb function call area. + */ + trap_cpu = smp_processor_id(); + OLD_esp = NEW_esp = (int) (&linux_regs->esp); + + IF_SMP(once_again:) + /* reply to host that an exception has occurred */ + remcomOutBuffer[0] = 'S'; + remcomOutBuffer[1] = hexchars[signo >> 4]; + remcomOutBuffer[2] = hexchars[signo % 16]; + remcomOutBuffer[3] = 0; + + putpacket(remcomOutBuffer); + + while (1 == 1) { + error = 0; + remcomOutBuffer[0] = 0; + getpacket(remcomInBuffer); + switch (remcomInBuffer[0]) { + case '?': + remcomOutBuffer[0] = 'S'; + remcomOutBuffer[1] = hexchars[signo >> 4]; + remcomOutBuffer[2] = hexchars[signo % 16]; + remcomOutBuffer[3] = 0; + break; + case 'd': + remote_debug = !(remote_debug); /* toggle debug flag */ + printk("Remote debug %s\n", + remote_debug ? "on" : "off"); + break; + case 'g': /* return the value of the CPU registers */ + get_gdb_regs(usethread, ®s, gdb_regs); + mem2hex((char *) gdb_regs, + remcomOutBuffer, NUMREGBYTES, 0); + break; + case 'G': /* set the value of the CPU registers - return OK */ + hex2mem(&remcomInBuffer[1], + (char *) gdb_regs, NUMREGBYTES, 0); + if (!usethread || usethread == current) { + gdb_regs_to_regs(gdb_regs, ®s); + strcpy(remcomOutBuffer, "OK"); + } else { + strcpy(remcomOutBuffer, "E00"); + } + break; + + case 'P':{ /* set the value of a single CPU register - + return OK */ + /* + * For some reason, gdb wants to talk about psudo + * registers (greater than 15). These may have + * meaning for ptrace, but for us it is safe to + * ignor them. We do this by dumping them into + * _GS which we also ignor, but do have memory for. + */ + int regno; + + ptr = &remcomInBuffer[1]; + regs_to_gdb_regs(gdb_regs, ®s); + if ((!usethread || usethread == current) && + hexToInt(&ptr, ®no) && + *ptr++ == '=' && (regno >= 0)) { + regno = + (regno >= NUMREGS ? _GS : regno); + hex2mem(ptr, (char *) &gdb_regs[regno], + 4, 0); + gdb_regs_to_regs(gdb_regs, ®s); + strcpy(remcomOutBuffer, "OK"); + break; + } + strcpy(remcomOutBuffer, "E01"); + break; + } + + /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */ + case 'm': + /* TRY TO READ %x,%x. IF SUCCEED, SET PTR = 0 */ + ptr = &remcomInBuffer[1]; + if (hexToInt(&ptr, &addr) && + (*(ptr++) == ',') && (hexToInt(&ptr, &length))) { + ptr = 0; + /* + * hex doubles the byte count + */ + if (length > (BUFMAX / 2)) + length = BUFMAX / 2; + mem2hex((char *) addr, + remcomOutBuffer, length, 1); + if (mem_err) { + strcpy(remcomOutBuffer, "E03"); + debug_error("memory fault\n", NULL); + } + } + + if (ptr) { + strcpy(remcomOutBuffer, "E01"); + debug_error + ("malformed read memory command: %s\n", + remcomInBuffer); + } + break; + + /* MAA..AA,LLLL: + Write LLLL bytes at address AA.AA return OK */ + case 'M': + /* TRY TO READ '%x,%x:'. IF SUCCEED, SET PTR = 0 */ + ptr = &remcomInBuffer[1]; + if (hexToInt(&ptr, &addr) && + (*(ptr++) == ',') && + (hexToInt(&ptr, &length)) && (*(ptr++) == ':')) { + hex2mem(ptr, (char *) addr, length, 1); + + if (mem_err) { + strcpy(remcomOutBuffer, "E03"); + debug_error("memory fault\n", NULL); + } else { + strcpy(remcomOutBuffer, "OK"); + } + + ptr = 0; + } + if (ptr) { + strcpy(remcomOutBuffer, "E02"); + debug_error + ("malformed write memory command: %s\n", + remcomInBuffer); + } + break; + + /* cAA..AA Continue at address AA..AA(optional) */ + /* sAA..AA Step one instruction from AA..AA(optional) */ + /* D detach, reply OK and then continue */ + case 'c': + case 's': + case 'D': + + /* try to read optional parameter, + pc unchanged if no parm */ + ptr = &remcomInBuffer[1]; + if (hexToInt(&ptr, &addr)) { + if (remote_debug) + printk("Changing EIP to 0x%x\n", addr); + + regs.eip = addr; + } + + newPC = regs.eip; + + /* clear the trace bit */ + regs.eflags &= 0xfffffeff; + + /* set the trace bit if we're stepping */ + if (remcomInBuffer[0] == 's') + regs.eflags |= 0x100; + + /* detach is a friendly version of continue. Note that + debugging is still enabled (e.g hit control C) + until the process that issued an ioctl TIOCGDB + terminates + */ + if (remcomInBuffer[0] == 'D') { + strcpy(remcomOutBuffer, "OK"); + putpacket(remcomOutBuffer); + } + + if (remote_debug) { + printk("Resuming execution\n"); + print_regs(®s); + } + asm volatile ("movl %%db6, %0\n":"=r" (dr6) + :); + if (!(dr6 & 0x4000)) { + for (breakno = 0; breakno < 4; ++breakno) { + if (dr6 & (1 << breakno) && + (breakinfo[breakno].type == 0)) { + /* Set restore flag */ + regs.eflags |= 0x10000; + break; + } + } + } + correct_hw_break(); + asm volatile ("movl %0, %%db6\n"::"r" (0)); + goto exit_kgdb; + + /* kill the program */ + case 'k': /* do nothing */ + break; + + /* query */ + case 'q': + switch (remcomInBuffer[1]) { + case 'L': + /* List threads */ + thread_list = 2; + thread_list_start = (usethread ? : current); + unpack_byte(remcomInBuffer + 3, &maxthreads); + unpack_threadid(remcomInBuffer + 5, &thref); + do { + int buf_thread_limit = + (BUFMAX - 22) / BUF_THREAD_ID_SIZE; + if (maxthreads > buf_thread_limit) { + maxthreads = buf_thread_limit; + } + } while (0); + remcomOutBuffer[0] = 'q'; + remcomOutBuffer[1] = 'M'; + remcomOutBuffer[4] = '0'; + pack_threadid(remcomOutBuffer + 5, &thref); + + threadid = threadref_to_int(&thref); + for (nothreads = 0; + nothreads < maxthreads && + threadid < PID_MAX + MAX_NO_CPUS; + threadid++) { + thread = getthread(threadid); + if (thread) { + int_to_threadref(&thref, + threadid); + pack_threadid(remcomOutBuffer + + 21 + + nothreads * 16, + &thref); + nothreads++; + if (thread_min > threadid) + thread_min = threadid; + } + } + + if (threadid == PID_MAX + MAX_NO_CPUS) { + remcomOutBuffer[4] = '1'; + } + pack_hex_byte(remcomOutBuffer + 2, nothreads); + remcomOutBuffer[21 + nothreads * 16] = '\0'; + break; + + case 'C': + /* Current thread id */ + remcomOutBuffer[0] = 'Q'; + remcomOutBuffer[1] = 'C'; + threadid = current->pid; + if (!threadid) { + /* + * idle thread + */ + for (threadid = PID_MAX; + threadid < PID_MAX + MAX_NO_CPUS; + threadid++) { + if (current == + idle_task(threadid - + PID_MAX)) + break; + } + } + int_to_threadref(&thref, threadid); + pack_threadid(remcomOutBuffer + 2, &thref); + remcomOutBuffer[18] = '\0'; + break; + + case 'E': + /* Print exception info */ + printexceptioninfo(exceptionVector, + err_code, remcomOutBuffer); + break; + } + break; + + /* task related */ + case 'H': + switch (remcomInBuffer[1]) { + case 'g': + ptr = &remcomInBuffer[2]; + hexToInt(&ptr, &threadid); + thread = getthread(threadid); + if (!thread) { + remcomOutBuffer[0] = 'E'; + remcomOutBuffer[1] = '\0'; + break; + } + /* + * Just in case I forget what this is all about, + * the "thread info" command to gdb causes it + * to ask for a thread list. It then switches + * to each thread and asks for the registers. + * For this (and only this) usage, we want to + * fudge the registers of tasks not on the run + * list (i.e. waiting) to show the routine that + * called schedule. Also, gdb, is a minimalist + * in that if the current thread is the last + * it will not re-read the info when done. + * This means that in this case we must show + * the real registers. So here is how we do it: + * Each entry we keep track of the min + * thread in the list (the last that gdb will) + * get info for. We also keep track of the + * starting thread. + * "thread_list" is cleared when switching back + * to the min thread if it is was current, or + * if it was not current, thread_list is set + * to 1. When the switch to current comes, + * if thread_list is 1, clear it, else do + * nothing. + */ + usethread = thread; + if ((thread_list == 1) && + (thread == thread_list_start)) { + thread_list = 0; + } + if (thread_list && (threadid == thread_min)) { + if (thread == thread_list_start) { + thread_list = 0; + } else { + thread_list = 1; + } + } + /* follow through */ + case 'c': + remcomOutBuffer[0] = 'O'; + remcomOutBuffer[1] = 'K'; + remcomOutBuffer[2] = '\0'; + break; + } + break; + + /* Query thread status */ + case 'T': + ptr = &remcomInBuffer[1]; + hexToInt(&ptr, &threadid); + thread = getthread(threadid); + if (thread) { + remcomOutBuffer[0] = 'O'; + remcomOutBuffer[1] = 'K'; + remcomOutBuffer[2] = '\0'; + if (thread_min > threadid) + thread_min = threadid; + } else { + remcomOutBuffer[0] = 'E'; + remcomOutBuffer[1] = '\0'; + } + break; + + case 'Y': + ptr = &remcomInBuffer[1]; + hexToInt(&ptr, &breakno); + ptr++; + hexToInt(&ptr, &breaktype); + ptr++; + hexToInt(&ptr, &length); + ptr++; + hexToInt(&ptr, &addr); + if (set_hw_break(breakno & 0x3, + breaktype & 0x3, + length & 0x3, addr) == 0) { + strcpy(remcomOutBuffer, "OK"); + } else { + strcpy(remcomOutBuffer, "ERROR"); + } + break; + + /* Remove hardware breakpoint */ + case 'y': + ptr = &remcomInBuffer[1]; + hexToInt(&ptr, &breakno); + if (remove_hw_break(breakno & 0x3) == 0) { + strcpy(remcomOutBuffer, "OK"); + } else { + strcpy(remcomOutBuffer, "ERROR"); + } + break; + + case 'r': /* reboot */ + strcpy(remcomOutBuffer, "OK"); + putpacket(remcomOutBuffer); + /*to_gdb("Rebooting\n"); */ + /* triplefault no return from here */ + { + static long no_idt[2]; + __asm__ __volatile__("lidt %0"::"m"(no_idt)); + BREAKPOINT; + } + + } /* switch */ + + /* reply to the request */ + putpacket(remcomOutBuffer); + } /* while(1==1) */ + /* + * reached by goto only. + */ + exit_kgdb: + /* + * Here is where we set up to trap a gdb function call. NEW_esp + * will be changed if we are trying to do this. We handle both + * adding and subtracting, thus allowing gdb to put grung on + * the stack which it removes later. + */ + if (NEW_esp != OLD_esp) { + int *ptr = END_OF_LOOKASIDE; + if (NEW_esp < OLD_esp) + ptr -= (OLD_esp - NEW_esp) / sizeof (int); + *--ptr = linux_regs->eflags; + *--ptr = linux_regs->xcs; + *--ptr = linux_regs->eip; + *--ptr = linux_regs->ecx; + *--ptr = linux_regs->ebx; + *--ptr = linux_regs->eax; + linux_regs->ecx = NEW_esp - (sizeof (int) * 6); + linux_regs->ebx = (unsigned int) END_OF_LOOKASIDE; + if (NEW_esp < OLD_esp) { + linux_regs->eip = (unsigned int) fn_call_stub; + } else { + linux_regs->eip = (unsigned int) fn_rtn_stub; + linux_regs->eax = NEW_esp; + } + linux_regs->eflags &= ~(IF_BIT | TF_BIT); + } +#ifdef CONFIG_SMP + /* + * Release gdb wait locks + * Sanity check time. Must have at least one cpu to run. Also single + * step must not be done if the current cpu is on hold. + */ + if (spinlock_count == 1) { + int ss_hold = (regs.eflags & 0x100) && kgdb_info.hold_on_sstep; + int cpu_avail = 0; + int i; + + for (i = 0; i < MAX_NO_CPUS; i++) { + if (!cpu_online(i)) + break; + if (!hold_cpu(i)) { + cpu_avail = 1; + } + } + /* + * Early in the bring up there will be NO cpus on line... + */ + if (!cpu_avail && cpu_online_map) { + to_gdb("No cpus unblocked, see 'kgdb_info.hold_cpu'\n"); + goto once_again; + } + if (hold_cpu(smp_processor_id()) && (regs.eflags & 0x100)) { + to_gdb + ("Current cpu must be unblocked to single step\n"); + goto once_again; + } + if (!(ss_hold)) { + int i; + for (i = 0; i < MAX_NO_CPUS; i++) { + if (!hold_cpu(i)) { + spin_unlock(&waitlocks[i]); + } + } + } else { + spin_unlock(&waitlocks[smp_processor_id()]); + } + /* Release kgdb spinlock */ + KGDB_SPIN_UNLOCK(&kgdb_spinlock); + /* + * If this cpu is on hold, this is where we + * do it. Note, the NMI will pull us out of here, + * but will return as the above lock is not held. + * We will stay here till another cpu releases the lock for us. + */ + spin_unlock_wait(waitlocks + smp_processor_id()); + kgdb_local_irq_restore(flags); + return (0); + } + exit_just_unlock: +#endif + /* Release kgdb spinlock */ + KGDB_SPIN_UNLOCK(&kgdb_spinlock); + kgdb_local_irq_restore(flags); + return (0); +} + +/* this function is used to set up exception handlers for tracing and + * breakpoints. + * This function is not needed as the above line does all that is needed. + * We leave it for backward compatitability... + */ +void +set_debug_traps(void) +{ + /* + * linux_debug_hook is defined in traps.c. We store a pointer + * to our own exception handler into it. + + * But really folks, every hear of labeled common, an old Fortran + * concept. Lots of folks can reference it and it is define if + * anyone does. Only one can initialize it at link time. We do + * this with the hook. See the statement above. No need for any + * executable code and it is ready as soon as the kernel is + * loaded. Very desirable in kernel debugging. + + linux_debug_hook = handle_exception ; + */ + + /* In case GDB is started before us, ack any packets (presumably + "$?#xx") sitting there. + putDebugChar ('+'); + + initialized = 1; + */ +} + +/* This function will generate a breakpoint exception. It is used at the + beginning of a program to sync up with a debugger and can be used + otherwise as a quick means to stop program execution and "break" into + the debugger. */ +/* But really, just use the BREAKPOINT macro. We will handle the int stuff + */ + +#ifdef later +/* + * possibly we should not go thru the traps.c code at all? Someday. + */ +void +do_kgdb_int3(struct pt_regs *regs, long error_code) +{ + kgdb_handle_exception(3, 5, error_code, regs); + return; +} +#endif +#undef regs +#ifdef CONFIG_TRAP_BAD_SYSCALL_EXITS +asmlinkage void +bad_sys_call_exit(int stuff) +{ + struct pt_regs *regs = (struct pt_regs *) &stuff; + printk("Sys call %d return with %x preempt_count\n", + (int) regs->orig_eax, preempt_count()); +} +#endif +#ifdef CONFIG_STACK_OVERFLOW_TEST +#include +asmlinkage void +stack_overflow(void) +{ +#ifdef BREAKPOINT + BREAKPOINT; +#else + printk("Kernel stack overflow, looping forever\n"); +#endif + while (1) { + } +} +#endif + +#if defined(CONFIG_SMP) || defined(CONFIG_KGDB_CONSOLE) +char gdbconbuf[BUFMAX]; + +static void +kgdb_gdb_message(const char *s, unsigned count) +{ + int i; + int wcount; + char *bufptr; + /* + * This takes care of NMI while spining out chars to gdb + */ + IF_SMP(in_kgdb_console = 1); + gdbconbuf[0] = 'O'; + bufptr = gdbconbuf + 1; + while (count > 0) { + if ((count << 1) > (BUFMAX - 2)) { + wcount = (BUFMAX - 2) >> 1; + } else { + wcount = count; + } + count -= wcount; + for (i = 0; i < wcount; i++) { + bufptr = pack_hex_byte(bufptr, s[i]); + } + *bufptr = '\0'; + s += wcount; + + putpacket(gdbconbuf); + + } + IF_SMP(in_kgdb_console = 0); +} +#endif +#ifdef CONFIG_SMP +static void +to_gdb(const char *s) +{ + int count = 0; + while (s[count] && (count++ < BUFMAX)) ; + kgdb_gdb_message(s, count); +} +#endif +#ifdef CONFIG_KGDB_CONSOLE +#include +#include +#include +#include +#include + +void +kgdb_console_write(struct console *co, const char *s, unsigned count) +{ + + if (gdb_i386vector == -1) { + /* + * We have not yet talked to gdb. What to do... + * lets break, on continue we can do the write. + * But first tell him whats up. Uh, well no can do, + * as this IS the console. Oh well... + * We do need to wait or the messages will be lost. + * Other option would be to tell the above code to + * ignore this breakpoint and do an auto return, + * but that might confuse gdb. Also this happens + * early enough in boot up that we don't have the traps + * set up yet, so... + */ + breakpoint(); + } + kgdb_gdb_message(s, count); +} + +/* + * ------------------------------------------------------------ + * Serial KGDB driver + * ------------------------------------------------------------ + */ + +static struct console kgdbcons = { + name:"kgdb", + write:kgdb_console_write, +#ifdef CONFIG_KGDB_USER_CONSOLE + device:kgdb_console_device, +#endif + flags:CON_PRINTBUFFER | CON_ENABLED, + index:-1, +}; + +/* + * The trick here is that this file gets linked before printk.o + * That means we get to peer at the console info in the command + * line before it does. If we are up, we register, otherwise, + * do nothing. By returning 0, we allow printk to look also. + */ +static int kgdb_console_enabled; + +int __init +kgdb_console_init(char *str) +{ + if ((strncmp(str, "kgdb", 4) == 0) || (strncmp(str, "gdb", 3) == 0)) { + register_console(&kgdbcons); + kgdb_console_enabled = 1; + } + return 0; /* let others look at the string */ +} + +__setup("console=", kgdb_console_init); + +#ifdef CONFIG_KGDB_USER_CONSOLE +static kdev_t kgdb_console_device(struct console *c); +/* This stuff sort of works, but it knocks out telnet devices + * we are leaving it here in case we (or you) find time to figure it out + * better.. + */ + +/* + * We need a real char device as well for when the console is opened for user + * space activities. + */ + +static int +kgdb_consdev_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static ssize_t +kgdb_consdev_write(struct file *file, const char *buf, + size_t count, loff_t * ppos) +{ + int size, ret = 0; + static char kbuf[128]; + static DECLARE_MUTEX(sem); + + /* We are not reentrant... */ + if (down_interruptible(&sem)) + return -ERESTARTSYS; + + while (count > 0) { + /* need to copy the data from user space */ + size = count; + if (size > sizeof (kbuf)) + size = sizeof (kbuf); + if (copy_from_user(kbuf, buf, size)) { + ret = -EFAULT; + break;; + } + kgdb_console_write(&kgdbcons, kbuf, size); + count -= size; + ret += size; + buf += size; + } + + up(&sem); + + return ret; +} + +struct file_operations kgdb_consdev_fops = { + open:kgdb_consdev_open, + write:kgdb_consdev_write +}; +static kdev_t +kgdb_console_device(struct console *c) +{ + return MKDEV(TTYAUX_MAJOR, 1); +} + +/* + * This routine gets called from the serial stub in the i386/lib + * This is so it is done late in bring up (just before the console open). + */ +void +kgdb_console_finit(void) +{ + if (kgdb_console_enabled) { + char *cptr = cdevname(MKDEV(TTYAUX_MAJOR, 1)); + char *cp = cptr; + while (*cptr && *cptr != '(') + cptr++; + *cptr = 0; + unregister_chrdev(TTYAUX_MAJOR, cp); + register_chrdev(TTYAUX_MAJOR, "kgdb", &kgdb_consdev_fops); + } +} +#endif +#endif +#ifdef CONFIG_KGDB_TS +#include /* time stamp code */ +#include /* in_interrupt */ +#ifdef CONFIG_KGDB_TS_64 +#define DATA_POINTS 64 +#endif +#ifdef CONFIG_KGDB_TS_128 +#define DATA_POINTS 128 +#endif +#ifdef CONFIG_KGDB_TS_256 +#define DATA_POINTS 256 +#endif +#ifdef CONFIG_KGDB_TS_512 +#define DATA_POINTS 512 +#endif +#ifdef CONFIG_KGDB_TS_1024 +#define DATA_POINTS 1024 +#endif +#ifndef DATA_POINTS +#define DATA_POINTS 128 /* must be a power of two */ +#endif +#define INDEX_MASK (DATA_POINTS - 1) +#if (INDEX_MASK & DATA_POINTS) +#error "CONFIG_KGDB_TS_COUNT must be a power of 2" +#endif +struct kgdb_and_then_struct { +#ifdef CONFIG_SMP + int on_cpu; +#endif + struct task_struct *task; + long long at_time; + int from_ln; + char *in_src; + void *from; + int *with_shpf; + int data0; + int data1; +}; +struct kgdb_and_then_struct2 { +#ifdef CONFIG_SMP + int on_cpu; +#endif + struct task_struct *task; + long long at_time; + int from_ln; + char *in_src; + void *from; + int *with_shpf; + struct task_struct *t1; + struct task_struct *t2; +}; +struct kgdb_and_then_struct kgdb_data[DATA_POINTS]; + +struct kgdb_and_then_struct *kgdb_and_then = &kgdb_data[0]; +int kgdb_and_then_count; + +void +kgdb_tstamp(int line, char *source, int data0, int data1) +{ + static spinlock_t ts_spin = SPIN_LOCK_UNLOCKED; + int flags; + kgdb_local_irq_save(flags); + spin_lock(&ts_spin); + rdtscll(kgdb_and_then->at_time); +#ifdef CONFIG_SMP + kgdb_and_then->on_cpu = smp_processor_id(); +#endif + kgdb_and_then->task = current; + kgdb_and_then->from_ln = line; + kgdb_and_then->in_src = source; + kgdb_and_then->from = __builtin_return_address(0); + kgdb_and_then->with_shpf = (int *) (((flags & IF_BIT) >> 9) | + (preempt_count() << 8)); + kgdb_and_then->data0 = data0; + kgdb_and_then->data1 = data1; + kgdb_and_then = &kgdb_data[++kgdb_and_then_count & INDEX_MASK]; + spin_unlock(&ts_spin); + kgdb_local_irq_restore(flags); +#ifdef CONFIG_PREEMPT + +#endif + return; +} +#endif +typedef int gdb_debug_hook(int exceptionVector, + int signo, int err_code, struct pt_regs *linux_regs); +gdb_debug_hook *linux_debug_hook = &kgdb_handle_exception; /* histerical reasons... */ --- linux-2.5.73/arch/i386/kernel/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/kernel/Makefile 2003-06-27 15:56:26.000000000 -0700 @@ -14,6 +14,7 @@ obj-y += timers/ obj-$(CONFIG_ACPI) += acpi/ obj-$(CONFIG_X86_BIOS_REBOOT) += reboot.o obj-$(CONFIG_MCA) += mca.o +obj-$(CONFIG_KGDB) += kgdb_stub.o obj-$(CONFIG_X86_MSR) += msr.o obj-$(CONFIG_X86_CPUID) += cpuid.o obj-$(CONFIG_MICROCODE) += microcode.o @@ -47,7 +48,7 @@ quiet_cmd_syscall = SYSCALL $@ cmd_syscall = $(CC) -nostdlib $(SYSCFLAGS_$(@F)) \ -Wl,-T,$(filter-out FORCE,$^) -o $@ -vsyscall-flags = -shared -s -Wl,-soname=linux-vsyscall.so.1 +vsyscall-flags = -shared -s -Wl,-soname=linux-gate.so.1 SYSCFLAGS_vsyscall-sysenter.so = $(vsyscall-flags) SYSCFLAGS_vsyscall-int80.so = $(vsyscall-flags) --- linux-2.5.73/arch/i386/kernel/nmi.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/kernel/nmi.c 2003-06-27 15:56:26.000000000 -0700 @@ -31,7 +31,17 @@ #include #include +#ifdef CONFIG_KGDB +#include +#ifdef CONFIG_SMP +unsigned int nmi_watchdog = NMI_IO_APIC; +#else +unsigned int nmi_watchdog = NMI_LOCAL_APIC; +#endif +#else unsigned int nmi_watchdog = NMI_NONE; +#endif + static unsigned int nmi_hz = HZ; unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */ extern void show_registers(struct pt_regs *regs); @@ -398,6 +408,9 @@ void touch_nmi_watchdog (void) for (i = 0; i < NR_CPUS; i++) alert_counter[i] = 0; } +#ifdef CONFIG_KGDB +int tune_watchdog = 5*HZ; +#endif void nmi_watchdog_tick (struct pt_regs * regs) { @@ -411,12 +424,24 @@ void nmi_watchdog_tick (struct pt_regs * sum = irq_stat[cpu].apic_timer_irqs; +#ifdef CONFIG_KGDB + if (! in_kgdb(regs) && last_irq_sums[cpu] == sum ) { + +#else if (last_irq_sums[cpu] == sum) { +#endif /* * Ayiee, looks like this CPU is stuck ... * wait a few IRQs (5 seconds) before doing the oops ... */ alert_counter[cpu]++; +#ifdef CONFIG_KGDB + if (alert_counter[cpu] == tune_watchdog) { + kgdb_handle_exception(2, SIGPWR, 0, regs); + last_irq_sums[cpu] = sum; + alert_counter[cpu] = 0; + } +#endif if (alert_counter[cpu] == 5*nmi_hz) { spin_lock(&nmi_print_lock); /* --- linux-2.5.73/arch/i386/kernel/setup.c 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/i386/kernel/setup.c 2003-06-27 16:30:31.000000000 -0700 @@ -61,10 +61,10 @@ struct cpuinfo_x86 boot_cpu_data = { 0, unsigned long mmu_cr4_features; EXPORT_SYMBOL_GPL(mmu_cr4_features); -#ifdef CONFIG_ACPI_HT_ONLY -int acpi_disabled = 1; -#else +#ifdef CONFIG_ACPI int acpi_disabled = 0; +#else +int acpi_disabled = 1; #endif EXPORT_SYMBOL(acpi_disabled); @@ -519,10 +519,6 @@ static void __init parse_cmdline_early ( if (c == ' ' && !memcmp(from, "acpi=off", 8)) acpi_disabled = 1; - /* "acpismp=force" turns on ACPI again */ - else if (!memcmp(from, "acpismp=force", 14)) - acpi_disabled = 0; - /* * highmem=size forces highmem to be exactly 'size' bytes. * This works even on boxes that have no highmem otherwise. @@ -977,13 +973,16 @@ void __init setup_arch(char **cmdline_p) generic_apic_probe(*cmdline_p); #endif -#ifdef CONFIG_ACPI_BOOT +#if defined(CONFIG_ACPI_BOOT) || defined(CONFIG_ACPI_HT_ONLY) /* * Parse the ACPI tables for possible boot-time SMP configuration. */ if (!acpi_disabled) acpi_boot_init(); #endif +#ifdef CONFIG_ACPI_HT_ONLY + acpi_disabled = 1; +#endif #ifdef CONFIG_X86_LOCAL_APIC if (smp_found_config) get_smp_config(); --- linux-2.5.73/arch/i386/kernel/smpboot.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/kernel/smpboot.c 2003-06-27 15:56:52.000000000 -0700 @@ -82,6 +82,10 @@ extern unsigned char trampoline_data []; extern unsigned char trampoline_end []; static unsigned char *trampoline_base; +/* used to selectively not boot certain CPUs with apicids */ +extern int skip_apic_ids[NR_CPUS]; + + /* * Currently trivial. Write the real->protected mode * bootstrap into the page concerned. The caller @@ -934,6 +938,16 @@ void *xquad_portio; int cpu_sibling_map[NR_CPUS] __cacheline_aligned; +static int skip_this_apicid(int apicid) +{ + int i; + + for (i = 1; i < (skip_apic_ids[0] + 1); i++) + if (apicid == skip_apic_ids[i]) + return 1; + return 0; +} + static void __init smp_boot_cpus(unsigned int max_cpus) { int apicid, cpu, bit, kicked; @@ -1032,6 +1046,8 @@ static void __init smp_boot_cpus(unsigne continue; if (max_cpus <= cpucount+1) continue; + if (skip_this_apicid(apicid)) + continue; if (do_boot_cpu(apicid)) printk("CPU #%d not responding - cannot use it.\n", --- linux-2.5.73/arch/i386/kernel/smp.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/kernel/smp.c 2003-06-27 15:56:26.000000000 -0700 @@ -459,7 +459,17 @@ void smp_send_reschedule(int cpu) { send_IPI_mask(1 << cpu, RESCHEDULE_VECTOR); } - +#ifdef CONFIG_KGDB +/* + * By using the NMI code instead of a vector we just sneak thru the + * word generator coming out with just what we want. AND it does + * not matter if clustered_apic_mode is set or not. + */ +void smp_send_nmi_allbutself(void) +{ + send_IPI_allbutself(APIC_DM_NMI); +} +#endif /* * Structure and data for smp_call_function(). This is designed to minimise * static memory requirements. It also looks cleaner. --- linux-2.5.73/arch/i386/kernel/time.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/kernel/time.c 2003-06-27 15:56:58.000000000 -0700 @@ -80,8 +80,7 @@ spinlock_t rtc_lock = SPIN_LOCK_UNLOCKED spinlock_t i8253_lock = SPIN_LOCK_UNLOCKED; EXPORT_SYMBOL(i8253_lock); -extern struct timer_opts timer_none; -struct timer_opts* timer = &timer_none; +struct timer_opts *cur_timer = &timer_none; /* * This version of gettimeofday has microsecond resolution @@ -93,14 +92,14 @@ void do_gettimeofday(struct timeval *tv) unsigned long usec, sec; do { + unsigned long lost; + seq = read_seqbegin(&xtime_lock); - usec = timer->get_offset(); - { - unsigned long lost = jiffies - wall_jiffies; - if (lost) - usec += lost * (1000000 / HZ); - } + usec = cur_timer->get_offset(); + lost = jiffies - wall_jiffies; + if (lost) + usec += lost * (1000000 / HZ); sec = xtime.tv_sec; usec += (xtime.tv_nsec / 1000); } while (read_seqretry(&xtime_lock, seq)); @@ -126,7 +125,7 @@ int do_settimeofday(struct timespec *tv) * wall time. Discover what correction gettimeofday() would have * made, and then undo it! */ - tv->tv_nsec -= timer->get_offset() * NSEC_PER_USEC; + tv->tv_nsec -= cur_timer->get_offset() * NSEC_PER_USEC; tv->tv_nsec -= (jiffies - wall_jiffies) * TICK_NSEC; while (tv->tv_nsec < 0) { @@ -180,7 +179,7 @@ int timer_ack; */ unsigned long long monotonic_clock(void) { - return timer->monotonic_clock(); + return cur_timer->monotonic_clock(); } EXPORT_SYMBOL(monotonic_clock); @@ -189,7 +188,8 @@ EXPORT_SYMBOL(monotonic_clock); * timer_interrupt() needs to keep up the real-time clock, * as well as call the "do_timer()" routine every clocktick */ -static inline void do_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +static inline void do_timer_interrupt(int irq, void *dev_id, + struct pt_regs *regs) { #ifdef CONFIG_X86_IO_APIC if (timer_ack) { @@ -259,7 +259,7 @@ irqreturn_t timer_interrupt(int irq, voi */ write_seqlock(&xtime_lock); - timer->mark_offset(); + cur_timer->mark_offset(); do_timer_interrupt(irq, NULL, regs); @@ -301,16 +301,13 @@ static int time_init_device(void) device_initcall(time_init_device); - void __init time_init(void) { - xtime.tv_sec = get_cmos_time(); wall_to_monotonic.tv_sec = -xtime.tv_sec; xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ); wall_to_monotonic.tv_nsec = -xtime.tv_nsec; - - timer = select_timer(); + cur_timer = select_timer(); time_init_hook(); } --- linux-2.5.73/arch/i386/kernel/timers/timer.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/kernel/timers/timer.c 2003-06-27 15:56:58.000000000 -0700 @@ -3,12 +3,6 @@ #include #include -/* list of externed timers */ -extern struct timer_opts timer_pit; -extern struct timer_opts timer_tsc; -#ifdef CONFIG_X86_CYCLONE_TIMER -extern struct timer_opts timer_cyclone; -#endif /* list of timers, ordered by preference, NULL terminated */ static struct timer_opts* timers[] = { #ifdef CONFIG_X86_CYCLONE_TIMER @@ -29,6 +23,16 @@ static int __init clock_setup(char* str) } __setup("clock=", clock_setup); + +/* + * The chosen timesource has been found to be bad. Fall back to a known good + * timesource (the PIT) + */ +void clock_fallback(void) +{ + cur_timer = &timer_pit; +} + /* iterates through the list of timers, returning the first * one that initializes successfully. */ --- linux-2.5.73/arch/i386/kernel/timers/timer_tsc.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/kernel/timers/timer_tsc.c 2003-06-27 15:56:58.000000000 -0700 @@ -124,6 +124,7 @@ static void mark_offset_tsc(void) int countmp; static int count1 = 0; unsigned long long this_offset, last_offset; + static int lost_count = 0; write_lock(&monotonic_lock); last_offset = ((unsigned long long)last_tsc_high<<32)|last_tsc_low; @@ -178,9 +179,20 @@ static void mark_offset_tsc(void) delta += delay_at_last_interrupt; lost = delta/(1000000/HZ); delay = delta%(1000000/HZ); - if (lost >= 2) + if (lost >= 2) { jiffies += lost-1; + /* sanity check to ensure we're not always loosing ticks */ + if (lost_count++ > 100) { + printk(KERN_WARNING "Loosing too many ticks!\n"); + printk(KERN_WARNING "TSC cannot be used as a " + "timesource. (Are you using SpeedStep?)\n"); + printk(KERN_WARNING "Falling back to a sane " + "timesource.\n"); + clock_fallback(); + } + } else + lost_count = 0; /* update the monotonic base value */ this_offset = ((unsigned long long)last_tsc_high<<32)|last_tsc_low; monotonic_base += cycles_2_ns(this_offset - last_offset); --- linux-2.5.73/arch/i386/kernel/traps.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/kernel/traps.c 2003-06-27 15:56:44.000000000 -0700 @@ -90,6 +90,42 @@ asmlinkage void alignment_check(void); asmlinkage void spurious_interrupt_bug(void); asmlinkage void machine_check(void); +#ifdef CONFIG_KGDB +extern void sysenter_entry(void); +#include +#include +extern void int3(void); +extern void debug(void); +void set_intr_gate(unsigned int n, void *addr); +static void set_intr_usr_gate(unsigned int n, void *addr); +/* + * Should be able to call this breakpoint() very early in + * bring up. Just hard code the call where needed. + * The breakpoint() code is here because set_?_gate() functions + * are local (static) to trap.c. They need be done only once, + * but it does not hurt to do them over. + */ +void breakpoint(void) +{ + set_intr_usr_gate(3,&int3); /* disable ints on trap */ + set_intr_gate(1,&debug); + set_intr_gate(14,&page_fault); + + BREAKPOINT; +} +#define CHK_REMOTE_DEBUG(trapnr,signr,error_code,regs,after) \ + { \ + if (!user_mode(regs) ) \ + { \ + kgdb_handle_exception(trapnr, signr, error_code, regs); \ + after; \ + } else if ((trapnr == 3) && (regs->eflags &0x200)) local_irq_enable(); \ + } +#else +#define CHK_REMOTE_DEBUG(trapnr,signr,error_code,regs,after) +#endif + + static int kstack_depth_to_print = 24; void show_trace(struct task_struct *task, unsigned long * stack) @@ -123,19 +159,20 @@ void show_trace_task(struct task_struct show_trace(tsk, (unsigned long *)esp); } -void show_stack(struct task_struct *task, unsigned long * esp) +void show_stack(struct task_struct *task, unsigned long *esp) { unsigned long *stack; int i; - // debugging aid: "show_stack(NULL);" prints the - // back trace for this cpu. - - if(esp==NULL) - esp=(unsigned long*)&esp; + if (esp == NULL) { + if (task) + esp = (unsigned long*)task->thread.esp; + else + esp = (unsigned long *)&esp; + } stack = esp; - for(i=0; i < kstack_depth_to_print; i++) { + for(i = 0; i < kstack_depth_to_print; i++) { if (((long) stack & (THREAD_SIZE-1)) == 0) break; if (i && ((i % 8) == 0)) @@ -171,8 +208,9 @@ void show_registers(struct pt_regs *regs ss = regs->xss & 0xffff; } print_modules(); - printk("CPU: %d\nEIP: %04x:[<%08lx>] %s\nEFLAGS: %08lx\n", - smp_processor_id(), 0xffff & regs->xcs, regs->eip, print_tainted(), regs->eflags); + printk("CPU: %d\nEIP: %04x:[<%08lx>] %s VLI\nEFLAGS: %08lx\n", + smp_processor_id(), 0xffff & regs->xcs, + regs->eip, print_tainted(), regs->eflags); print_symbol("EIP is at %s\n", regs->eip); printk("eax: %08lx ebx: %08lx ecx: %08lx edx: %08lx\n", @@ -188,23 +226,25 @@ void show_registers(struct pt_regs *regs * time of the fault.. */ if (in_kernel) { + u8 *eip; printk("\nStack: "); show_stack(NULL, (unsigned long*)esp); printk("Code: "); - if(regs->eip < PAGE_OFFSET) - goto bad; - for(i=0;i<20;i++) - { + eip = (u8 *)regs->eip - 43; + for (i = 0; i < 64; i++, eip++) { unsigned char c; - if(__get_user(c, &((unsigned char*)regs->eip)[i])) { -bad: + + if (eip < (u8 *)PAGE_OFFSET || __get_user(c, eip)) { printk(" Bad EIP value."); break; } - printk("%02x ", c); + if (eip == (u8 *)regs->eip) + printk("<%02x> ", c); + else + printk("%02x ", c); } } printk("\n"); @@ -251,12 +291,36 @@ spinlock_t die_lock = SPIN_LOCK_UNLOCKED void die(const char * str, struct pt_regs * regs, long err) { static int die_counter; + int nl = 0; console_verbose(); spin_lock_irq(&die_lock); bust_spinlocks(1); handle_BUG(regs); printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter); +#ifdef CONFIG_PREEMPT + printk("PREEMPT "); + nl = 1; +#endif +#ifdef CONFIG_SMP + printk("SMP "); + nl = 1; +#endif +#ifdef CONFIG_DEBUG_PAGEALLOC + printk("DEBUG_PAGEALLOC"); + nl = 1; +#endif + if (nl) + printk("\n"); +#ifdef CONFIG_KGDB + /* This is about the only place we want to go to kgdb even if in + * user mode. But we must go in via a trap so within kgdb we will + * always be in kernel mode. + */ + if (user_mode(regs)) + BREAKPOINT; +#endif + CHK_REMOTE_DEBUG(0,SIGTRAP,err,regs,) show_registers(regs); bust_spinlocks(0); spin_unlock_irq(&die_lock); @@ -326,6 +390,7 @@ static inline void do_trap(int trapnr, i #define DO_ERROR(trapnr, signr, str, name) \ asmlinkage void do_##name(struct pt_regs * regs, long error_code) \ { \ + CHK_REMOTE_DEBUG(trapnr,signr,error_code,regs,)\ do_trap(trapnr, signr, str, 0, regs, error_code, NULL); \ } @@ -343,7 +408,9 @@ asmlinkage void do_##name(struct pt_regs #define DO_VM86_ERROR(trapnr, signr, str, name) \ asmlinkage void do_##name(struct pt_regs * regs, long error_code) \ { \ + CHK_REMOTE_DEBUG(trapnr, signr, error_code,regs, return)\ do_trap(trapnr, signr, str, 1, regs, error_code, NULL); \ + return; \ } #define DO_VM86_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr) \ @@ -386,8 +453,10 @@ gp_in_vm86: return; gp_in_kernel: - if (!fixup_exception(regs)) + if (!fixup_exception(regs)){ + CHK_REMOTE_DEBUG(13,SIGSEGV,error_code,regs,) die("general protection fault", regs, error_code); + } } static void mem_parity_error(unsigned char reason, struct pt_regs * regs) @@ -549,8 +618,18 @@ asmlinkage void do_debug(struct pt_regs * allowing programs to debug themselves without the ptrace() * interface. */ - if ((regs->xcs & 3) == 0) +#ifdef CONFIG_KGDB + /* + * I think this is the only "real" case of a TF in the kernel + * that really belongs to user space. Others are + * "Ours all ours!" + */ + if (((regs->xcs & 3) == 0) && ((void *)regs->eip == sysenter_entry)) + goto clear_TF_reenable; +#else + if ((regs->xcs & 3) == 0) goto clear_TF_reenable; +#endif if ((tsk->ptrace & (PT_DTRACE|PT_PTRACED)) == PT_DTRACE) goto clear_TF; } @@ -562,6 +641,17 @@ asmlinkage void do_debug(struct pt_regs info.si_errno = 0; info.si_code = TRAP_BRKPT; +#ifdef CONFIG_KGDB + /* + * If this is a kernel mode trap, we need to reset db7 to allow us + * to continue sanely ALSO skip the signal delivery + */ + if ((regs->xcs & 3) == 0) + goto clear_dr7; + + /* if not kernel, allow ints but only if they were on */ + if ( regs->eflags & 0x200) local_irq_enable(); +#endif /* If this is a kernel mode trap, save the user PC on entry to * the kernel, that's what the debugger can make sense of. */ @@ -576,6 +666,7 @@ clear_dr7: __asm__("movl %0,%%db7" : /* no output */ : "r" (0)); + CHK_REMOTE_DEBUG(1,SIGTRAP,error_code,regs,) return; debug_vm86: @@ -822,6 +913,12 @@ static void __init set_call_gate(void *a { _set_gate(a,12,3,addr,__KERNEL_CS); } +#ifdef CONFIG_KGDB +void set_intr_usr_gate(unsigned int n, void *addr) +{ + _set_gate(idt_table+n,14,3,addr,__KERNEL_CS); +} +#endif static void __init set_task_gate(unsigned int n, unsigned int gdt_entry) { @@ -848,7 +945,11 @@ void __init trap_init(void) set_trap_gate(0,÷_error); set_intr_gate(1,&debug); set_intr_gate(2,&nmi); +#ifndef CONFIG_KGDB set_system_gate(3,&int3); /* int3-5 can be called from all */ +#else + set_intr_usr_gate(3,&int3); /* int3-5 can be called from all */ +#endif set_system_gate(4,&overflow); set_system_gate(5,&bounds); set_trap_gate(6,&invalid_op); --- linux-2.5.73/arch/i386/lib/dec_and_lock.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/lib/dec_and_lock.c 2003-06-27 15:56:46.000000000 -0700 @@ -10,6 +10,7 @@ #include #include +#ifndef ATOMIC_DEC_AND_LOCK int atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock) { int counter; @@ -38,3 +39,5 @@ slow_path: spin_unlock(lock); return 0; } +#endif + --- linux-2.5.73/arch/i386/lib/delay.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/lib/delay.c 2003-06-27 15:56:58.000000000 -0700 @@ -25,7 +25,7 @@ extern struct timer_opts* timer; void __delay(unsigned long loops) { - timer->delay(loops); + cur_timer->delay(loops); } inline void __const_udelay(unsigned long xloops) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/i386/lib/kgdb_serial.c 2003-06-27 15:56:26.000000000 -0700 @@ -0,0 +1,485 @@ +/* + * Serial interface GDB stub + * + * Written (hacked together) by David Grothe (dave@gcom.com) + * Modified to allow invokation early in boot see also + * kgdb.h for instructions by George Anzinger(george@mvista.com) + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_KGDB_USER_CONSOLE +extern void kgdb_console_finit(void); +#endif +#define PRNT_off +#define TEST_EXISTANCE +#ifdef PRNT +#define dbprintk(s) printk s +#else +#define dbprintk(s) +#endif +#define TEST_INTERRUPT_off +#ifdef TEST_INTERRUPT +#define intprintk(s) printk s +#else +#define intprintk(s) +#endif + +#define IRQ_T(info) ((info->flags & ASYNC_SHARE_IRQ) ? SA_SHIRQ : SA_INTERRUPT) + +#define GDB_BUF_SIZE 512 /* power of 2, please */ + +static char gdb_buf[GDB_BUF_SIZE]; +static int gdb_buf_in_inx; +static atomic_t gdb_buf_in_cnt; +static int gdb_buf_out_inx; + +struct async_struct *gdb_async_info; +static int gdb_async_irq; + +#define outb_px(a,b) outb_p(b,a) + +static void program_uart(struct async_struct *info); +static void write_char(struct async_struct *info, int chr); +/* + * Get a byte from the hardware data buffer and return it + */ +static int +read_data_bfr(struct async_struct *info) +{ + char it = inb_p(info->port + UART_LSR); + + if (it & UART_LSR_DR) + return (inb_p(info->port + UART_RX)); + /* + * If we have a framing error assume somebody messed with + * our uart. Reprogram it and send '-' both ways... + */ + if (it & 0xc) { + program_uart(info); + write_char(info, '-'); + return ('-'); + } + return (-1); + +} /* read_data_bfr */ + +/* + * Get a char if available, return -1 if nothing available. + * Empty the receive buffer first, then look at the interface hardware. + + * Locking here is a bit of a problem. We MUST not lock out communication + * if we are trying to talk to gdb about a kgdb entry. ON the other hand + * we can loose chars in the console pass thru if we don't lock. It is also + * possible that we could hold the lock or be waiting for it when kgdb + * NEEDS to talk. Since kgdb locks down the world, it does not need locks. + * We do, of course have possible issues with interrupting a uart operation, + * but we will just depend on the uart status to help keep that straight. + + */ +static spinlock_t uart_interrupt_lock = SPIN_LOCK_UNLOCKED; +#ifdef CONFIG_SMP +extern spinlock_t kgdb_spinlock; +#endif + +static int +read_char(struct async_struct *info) +{ + int chr; + unsigned long flags; + local_irq_save(flags); +#ifdef CONFIG_SMP + if (!spin_is_locked(&kgdb_spinlock)) { + spin_lock(&uart_interrupt_lock); + } +#endif + if (atomic_read(&gdb_buf_in_cnt) != 0) { /* intr routine has q'd chars */ + chr = gdb_buf[gdb_buf_out_inx++]; + gdb_buf_out_inx &= (GDB_BUF_SIZE - 1); + atomic_dec(&gdb_buf_in_cnt); + } else { + chr = read_data_bfr(info); + } +#ifdef CONFIG_SMP + if (!spin_is_locked(&kgdb_spinlock)) { + spin_unlock(&uart_interrupt_lock); + } +#endif + local_irq_restore(flags); + return (chr); +} + +/* + * Wait until the interface can accept a char, then write it. + */ +static void +write_char(struct async_struct *info, int chr) +{ + while (!(inb_p(info->port + UART_LSR) & UART_LSR_THRE)) ; + + outb_p(chr, info->port + UART_TX); + +} /* write_char */ + +/* + * Mostly we don't need a spinlock, but since the console goes + * thru here with interrutps on, well, we need to catch those + * chars. + */ +/* + * This is the receiver interrupt routine for the GDB stub. + * It will receive a limited number of characters of input + * from the gdb host machine and save them up in a buffer. + * + * When the gdb stub routine getDebugChar() is called it + * draws characters out of the buffer until it is empty and + * then reads directly from the serial port. + * + * We do not attempt to write chars from the interrupt routine + * since the stubs do all of that via putDebugChar() which + * writes one byte after waiting for the interface to become + * ready. + * + * The debug stubs like to run with interrupts disabled since, + * after all, they run as a consequence of a breakpoint in + * the kernel. + * + * Perhaps someone who knows more about the tty driver than I + * care to learn can make this work for any low level serial + * driver. + */ +static irqreturn_t +gdb_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + struct async_struct *info; + unsigned long flags; + + info = gdb_async_info; + if (!info || !info->tty || irq != gdb_async_irq) + return IRQ_NONE; + + local_irq_save(flags); + spin_lock(&uart_interrupt_lock); + do { + int chr = read_data_bfr(info); + intprintk(("Debug char on int: %x hex\n", chr)); + if (chr < 0) + continue; + + if (chr == 3) { /* Ctrl-C means remote interrupt */ + BREAKPOINT; + continue; + } + + if (atomic_read(&gdb_buf_in_cnt) >= GDB_BUF_SIZE) { + /* buffer overflow tosses early char */ + read_char(info); + } + gdb_buf[gdb_buf_in_inx++] = chr; + gdb_buf_in_inx &= (GDB_BUF_SIZE - 1); + } while (inb_p(info->port + UART_IIR) & UART_IIR_RDI); + spin_unlock(&uart_interrupt_lock); + local_irq_restore(flags); + return IRQ_HANDLED; +} /* gdb_interrupt */ + +/* + * Just a NULL routine for testing. + */ +void +gdb_null(void) +{ +} /* gdb_null */ + +/* These structure are filled in with values defined in asm/kgdb_local.h + */ +static struct serial_state state = SB_STATE; +static struct async_struct local_info = SB_INFO; +static int ok_to_enable_ints = 0; +static void kgdb_enable_ints_now(void); + +extern char *kgdb_version; +/* + * Hook an IRQ for KGDB. + * + * This routine is called from putDebugChar, below. + */ +static int ints_disabled = 1; +int +gdb_hook_interrupt(struct async_struct *info, int verb) +{ + struct serial_state *state = info->state; + unsigned long flags; + int port; +#ifdef TEST_EXISTANCE + int scratch, scratch2; +#endif + + /* The above fails if memory managment is not set up yet. + * Rather than fail the set up, just keep track of the fact + * and pick up the interrupt thing later. + */ + gdb_async_info = info; + port = gdb_async_info->port; + gdb_async_irq = state->irq; + if (verb) { + printk("kgdb %s : port =%x, IRQ=%d, divisor =%d\n", + kgdb_version, + port, + gdb_async_irq, gdb_async_info->state->custom_divisor); + } + local_irq_save(flags); +#ifdef TEST_EXISTANCE + /* Existance test */ + /* Should not need all this, but just in case.... */ + + scratch = inb_p(port + UART_IER); + outb_px(port + UART_IER, 0); + outb_px(0xff, 0x080); + scratch2 = inb_p(port + UART_IER); + outb_px(port + UART_IER, scratch); + if (scratch2) { + printk + ("gdb_hook_interrupt: Could not clear IER, not a UART!\n"); + local_irq_restore(flags); + return 1; /* We failed; there's nothing here */ + } + scratch2 = inb_p(port + UART_LCR); + outb_px(port + UART_LCR, 0xBF); /* set up for StarTech test */ + outb_px(port + UART_EFR, 0); /* EFR is the same as FCR */ + outb_px(port + UART_LCR, 0); + outb_px(port + UART_FCR, UART_FCR_ENABLE_FIFO); + scratch = inb_p(port + UART_IIR) >> 6; + if (scratch == 1) { + printk("gdb_hook_interrupt: Undefined UART type!" + " Not a UART! \n"); + local_irq_restore(flags); + return 1; + } else { + dbprintk(("gdb_hook_interrupt: UART type " + "is %d where 0=16450, 2=16550 3=16550A\n", scratch)); + } + scratch = inb_p(port + UART_MCR); + outb_px(port + UART_MCR, UART_MCR_LOOP | scratch); + outb_px(port + UART_MCR, UART_MCR_LOOP | 0x0A); + scratch2 = inb_p(port + UART_MSR) & 0xF0; + outb_px(port + UART_MCR, scratch); + if (scratch2 != 0x90) { + printk("gdb_hook_interrupt: " + "Loop back test failed! Not a UART!\n"); + local_irq_restore(flags); + return scratch2 + 1000; /* force 0 to fail */ + } +#endif /* test existance */ + program_uart(info); + local_irq_restore(flags); + + return (0); + +} /* gdb_hook_interrupt */ + +static void +program_uart(struct async_struct *info) +{ + int port = info->port; + + (void) inb_p(port + UART_RX); + outb_px(port + UART_IER, 0); + + (void) inb_p(port + UART_RX); /* serial driver comments say */ + (void) inb_p(port + UART_IIR); /* this clears the interrupt regs */ + (void) inb_p(port + UART_MSR); + outb_px(port + UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB); + outb_px(port + UART_DLL, info->state->custom_divisor & 0xff); /* LS */ + outb_px(port + UART_DLM, info->state->custom_divisor >> 8); /* MS */ + outb_px(port + UART_MCR, info->MCR); + + outb_px(port + UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1 | UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); /* set fcr */ + outb_px(port + UART_LCR, UART_LCR_WLEN8); /* reset DLAB */ + outb_px(port + UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1); /* set fcr */ + if (!ints_disabled) { + intprintk(("KGDB: Sending %d to port %x offset %d\n", + gdb_async_info->IER, + (int) gdb_async_info->port, UART_IER)); + outb_px(gdb_async_info->port + UART_IER, gdb_async_info->IER); + } + return; +} + +/* + * getDebugChar + * + * This is a GDB stub routine. It waits for a character from the + * serial interface and then returns it. If there is no serial + * interface connection then it returns a bogus value which will + * almost certainly cause the system to hang. In the + */ +int kgdb_in_isr = 0; +int kgdb_in_lsr = 0; +extern spinlock_t kgdb_spinlock; + +/* Caller takes needed protections */ + +int +getDebugChar(void) +{ + volatile int chr, dum, time, end_time; + + dbprintk(("getDebugChar(port %x): ", gdb_async_info->port)); + + if (gdb_async_info == NULL) { + gdb_hook_interrupt(&local_info, 0); + } + /* + * This trick says if we wait a very long time and get + * no char, return the -1 and let the upper level deal + * with it. + */ + rdtsc(dum, time); + end_time = time + 2; + while (((chr = read_char(gdb_async_info)) == -1) && + (end_time - time) > 0) { + rdtsc(dum, time); + }; + /* + * This covers our butts if some other code messes with + * our uart, hay, it happens :o) + */ + if (chr == -1) + program_uart(gdb_async_info); + + dbprintk(("%c\n", chr > ' ' && chr < 0x7F ? chr : ' ')); + return (chr); + +} /* getDebugChar */ + +static int count = 3; +static spinlock_t one_at_atime = SPIN_LOCK_UNLOCKED; + +static int __init +kgdb_enable_ints(void) +{ + if (gdb_async_info == NULL) { + gdb_hook_interrupt(&local_info, 1); + } + ok_to_enable_ints = 1; + kgdb_enable_ints_now(); +#ifdef CONFIG_KGDB_USER_CONSOLE + kgdb_console_finit(); +#endif + return 0; +} + +#ifdef CONFIG_SERIAL_8250 +void shutdown_for_kgdb(struct async_struct *gdb_async_info); +#endif + +#ifdef CONFIG_DISCONTIGMEM +static inline int kgdb_mem_init_done(void) +{ + return highmem_start_page != NULL; +} +#else +static inline int kgdb_mem_init_done(void) +{ + return max_mapnr != 0; +} +#endif + +static void +kgdb_enable_ints_now(void) +{ + if (!spin_trylock(&one_at_atime)) + return; + if (!ints_disabled) + goto exit; + if (kgdb_mem_init_done() && + ints_disabled) { /* don't try till mem init */ +#ifdef CONFIG_SERIAL_8250 + /* + * The ifdef here allows the system to be configured + * without the serial driver. + * Don't make it a module, however, it will steal the port + */ + shutdown_for_kgdb(gdb_async_info); +#endif + ints_disabled = request_irq(gdb_async_info->state->irq, + gdb_interrupt, + IRQ_T(gdb_async_info), + "KGDB-stub", NULL); + intprintk(("KGDB: request_irq returned %d\n", ints_disabled)); + } + if (!ints_disabled) { + intprintk(("KGDB: Sending %d to port %x offset %d\n", + gdb_async_info->IER, + (int) gdb_async_info->port, UART_IER)); + outb_px(gdb_async_info->port + UART_IER, gdb_async_info->IER); + } + exit: + spin_unlock(&one_at_atime); +} + +/* + * putDebugChar + * + * This is a GDB stub routine. It waits until the interface is ready + * to transmit a char and then sends it. If there is no serial + * interface connection then it simply returns to its caller, having + * pretended to send the char. Caller takes needed protections. + */ +void +putDebugChar(int chr) +{ + dbprintk(("putDebugChar(port %x): chr=%02x '%c', ints_on=%d\n", + gdb_async_info->port, + chr, + chr > ' ' && chr < 0x7F ? chr : ' ', ints_disabled ? 0 : 1)); + + if (gdb_async_info == NULL) { + gdb_hook_interrupt(&local_info, 0); + } + + write_char(gdb_async_info, chr); /* this routine will wait */ + count = (chr == '#') ? 0 : count + 1; + if ((count == 2)) { /* try to enable after */ + if (ints_disabled & ok_to_enable_ints) + kgdb_enable_ints_now(); /* try to enable after */ + + /* We do this a lot because, well we really want to get these + * interrupts. The serial driver will clear these bits when it + * initializes the chip. Every thing else it does is ok, + * but this. + */ + if (!ints_disabled) { + outb_px(gdb_async_info->port + UART_IER, + gdb_async_info->IER); + } + } + +} /* putDebugChar */ + +module_init(kgdb_enable_ints); --- linux-2.5.73/arch/i386/lib/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/lib/Makefile 2003-06-27 15:56:26.000000000 -0700 @@ -9,4 +9,5 @@ lib-y = checksum.o delay.o \ lib-$(CONFIG_X86_USE_3DNOW) += mmx.o lib-$(CONFIG_HAVE_DEC_LOCK) += dec_and_lock.o +lib-$(CONFIG_KGDB) += kgdb_serial.o lib-$(CONFIG_DEBUG_IOVIRT) += iodebug.o --- linux-2.5.73/arch/i386/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/Makefile 2003-06-27 15:56:32.000000000 -0700 @@ -85,6 +85,9 @@ mcore-$(CONFIG_X86_ES7000) := mach-es700 # default subarch .h files mflags-y += -Iinclude/asm-i386/mach-default +mflags-$(CONFIG_KGDB) += -ggdb +mflags-$(CONFIG_KGDB_MORE) += $(shell echo $(CONFIG_KGDB_OPTIONS) | sed -e 's/"//g') + head-y := arch/i386/kernel/head.o arch/i386/kernel/init_task.o libs-y += arch/i386/lib/ @@ -98,6 +101,7 @@ drivers-$(CONFIG_OPROFILE) += arch/i386 CFLAGS += $(mflags-y) AFLAGS += $(mflags-y) +AFLAGS_vmlinux.lds.o += -imacros $(TOPDIR)/include/asm-i386/page.h boot := arch/i386/boot --- linux-2.5.73/arch/i386/mm/fault.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/mm/fault.c 2003-06-27 15:56:26.000000000 -0700 @@ -236,6 +236,12 @@ no_context: * Oops. The kernel tried to access some bad page. We'll have to * terminate things with extreme prejudice. */ +#ifdef CONFIG_KGDB + if (!user_mode(regs)){ + kgdb_handle_exception(14,SIGBUS, error_code, regs); + return; + } +#endif bust_spinlocks(1); --- linux-2.5.73/arch/i386/mm/init.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/mm/init.c 2003-06-27 15:56:35.000000000 -0700 @@ -512,20 +512,30 @@ void __init mem_init(void) #endif } -#ifdef CONFIG_X86_PAE -struct kmem_cache_s *pae_pgd_cachep; +kmem_cache_t *pgd_cache; +kmem_cache_t *pmd_cache; void __init pgtable_cache_init(void) { - /* - * PAE pgds must be 16-byte aligned: - */ - pae_pgd_cachep = kmem_cache_create("pae_pgd", 32, 0, - SLAB_HWCACHE_ALIGN | SLAB_MUST_HWCACHE_ALIGN, NULL, NULL); - if (!pae_pgd_cachep) - panic("init_pae(): Cannot alloc pae_pgd SLAB cache"); + if (PTRS_PER_PMD > 1) { + pmd_cache = kmem_cache_create("pmd", + PTRS_PER_PMD*sizeof(pmd_t), + 0, + SLAB_HWCACHE_ALIGN | SLAB_MUST_HWCACHE_ALIGN, + pmd_ctor, + NULL); + if (!pmd_cache) + panic("pgtable_cache_init(): cannot create pmd cache"); + } + pgd_cache = kmem_cache_create("pgd", + PTRS_PER_PGD*sizeof(pgd_t), + 0, + SLAB_HWCACHE_ALIGN | SLAB_MUST_HWCACHE_ALIGN, + pgd_ctor, + PTRS_PER_PMD == 1 ? pgd_dtor : NULL); + if (!pgd_cache) + panic("pgtable_cache_init(): Cannot create pgd cache"); } -#endif /* * This function cannot be __init, since exceptions don't work in that --- linux-2.5.73/arch/i386/mm/pageattr.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/mm/pageattr.c 2003-06-27 15:56:35.000000000 -0700 @@ -13,6 +13,10 @@ #include #include +static spinlock_t cpa_lock = SPIN_LOCK_UNLOCKED; +static struct list_head df_list = LIST_HEAD_INIT(df_list); + + static inline pte_t *lookup_address(unsigned long address) { pgd_t *pgd = pgd_offset_k(address); @@ -31,10 +35,15 @@ static struct page *split_large_page(uns { int i; unsigned long addr; - struct page *base = alloc_pages(GFP_KERNEL, 0); + struct page *base; pte_t *pbase; + + spin_unlock_irq(&cpa_lock); + base = alloc_pages(GFP_KERNEL, 0); + spin_lock_irq(&cpa_lock); if (!base) return NULL; + address = __pa(address); addr = address & LARGE_PAGE_MASK; pbase = (pte_t *)page_address(base); @@ -58,19 +67,22 @@ static void flush_kernel_map(void *dummy static void set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) { + struct page *page; + unsigned long flags; + set_pte_atomic(kpte, pte); /* change init_mm */ -#ifndef CONFIG_X86_PAE - { - struct list_head *l; - spin_lock(&mmlist_lock); - list_for_each(l, &init_mm.mmlist) { - struct mm_struct *mm = list_entry(l, struct mm_struct, mmlist); - pmd_t *pmd = pmd_offset(pgd_offset(mm, address), address); - set_pte_atomic((pte_t *)pmd, pte); - } - spin_unlock(&mmlist_lock); + if (PTRS_PER_PMD > 1) + return; + + spin_lock_irqsave(&pgd_lock, flags); + list_for_each_entry(page, &pgd_list, lru) { + pgd_t *pgd; + pmd_t *pmd; + pgd = (pgd_t *)page_address(page) + pgd_index(address); + pmd = pmd_offset(pgd, address); + set_pte_atomic((pte_t *)pmd, pte); } -#endif + spin_unlock_irqrestore(&pgd_lock, flags); } /* @@ -87,7 +99,7 @@ static inline void revert_page(struct pa } static int -__change_page_attr(struct page *page, pgprot_t prot, struct page **oldpage) +__change_page_attr(struct page *page, pgprot_t prot) { pte_t *kpte; unsigned long address; @@ -123,7 +135,7 @@ __change_page_attr(struct page *page, pg } if (cpu_has_pse && (atomic_read(&kpte_page->count) == 1)) { - *oldpage = kpte_page; + list_add(&kpte_page->list, &df_list); revert_page(kpte_page, address); } return 0; @@ -134,12 +146,6 @@ static inline void flush_map(void) on_each_cpu(flush_kernel_map, NULL, 1, 1); } -struct deferred_page { - struct deferred_page *next; - struct page *fpage; -}; -static struct deferred_page *df_list; /* protected by init_mm.mmap_sem */ - /* * Change the page attributes of an page in the linear mapping. * @@ -156,47 +162,52 @@ static struct deferred_page *df_list; /* int change_page_attr(struct page *page, int numpages, pgprot_t prot) { int err = 0; - struct page *fpage; int i; + unsigned long flags; - down_write(&init_mm.mmap_sem); + spin_lock_irqsave(&cpa_lock, flags); for (i = 0; i < numpages; i++, page++) { - fpage = NULL; - err = __change_page_attr(page, prot, &fpage); + err = __change_page_attr(page, prot); if (err) break; - if (fpage) { - struct deferred_page *df; - df = kmalloc(sizeof(struct deferred_page), GFP_KERNEL); - if (!df) { - flush_map(); - __free_page(fpage); - } else { - df->next = df_list; - df->fpage = fpage; - df_list = df; - } - } } - up_write(&init_mm.mmap_sem); + spin_unlock_irqrestore(&cpa_lock, flags); return err; } void global_flush_tlb(void) { - struct deferred_page *df, *next_df; + LIST_HEAD(l); + struct list_head* n; + + BUG_ON(irqs_disabled()); - down_read(&init_mm.mmap_sem); - df = xchg(&df_list, NULL); - up_read(&init_mm.mmap_sem); + spin_lock_irq(&cpa_lock); + list_splice_init(&df_list, &l); + spin_unlock_irq(&cpa_lock); flush_map(); - for (; df; df = next_df) { - next_df = df->next; - if (df->fpage) - __free_page(df->fpage); - kfree(df); - } + n = l.next; + while (n != &l) { + struct page *pg = list_entry(n, struct page, list); + n = n->next; + __free_page(pg); + } } +#ifdef CONFIG_DEBUG_PAGEALLOC +void kernel_map_pages(struct page *page, int numpages, int enable) +{ + /* the return value is ignored - the calls cannot fail, + * large pages are disabled at boot time. + */ + change_page_attr(page, numpages, enable ? PAGE_KERNEL : __pgprot(0)); + /* we should perform an IPI and flush all tlbs, + * but that can deadlock->flush only current cpu. + */ + __flush_tlb_all(); +} +EXPORT_SYMBOL(kernel_map_pages); +#endif + EXPORT_SYMBOL(change_page_attr); EXPORT_SYMBOL(global_flush_tlb); --- linux-2.5.73/arch/i386/mm/pgtable.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/mm/pgtable.c 2003-06-27 15:56:59.000000000 -0700 @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -34,7 +35,7 @@ void show_mem(void) show_free_areas(); printk("Free swap: %6dkB\n",nr_swap_pages<<(PAGE_SHIFT-10)); for_each_pgdat(pgdat) { - for (i = 0; i < pgdat->node_size; ++i) { + for (i = 0; i < pgdat->node_spanned_size; ++i) { page = pgdat->node_mem_map + i; total++; if (PageHighMem(page)) @@ -151,61 +152,88 @@ struct page *pte_alloc_one(struct mm_str return pte; } -#ifdef CONFIG_X86_PAE +void pmd_ctor(void *pmd, kmem_cache_t *cache, unsigned long flags) +{ + memset(pmd, 0, PTRS_PER_PMD*sizeof(pmd_t)); +} -pgd_t *pgd_alloc(struct mm_struct *mm) +/* + * List of all pgd's needed for non-PAE so it can invalidate entries + * in both cached and uncached pgd's; not needed for PAE since the + * kernel pmd is shared. If PAE were not to share the pmd a similar + * tactic would be needed. This is essentially codepath-based locking + * against pageattr.c; it is the unique case in which a valid change + * of kernel pagetables can't be lazily synchronized by vmalloc faults. + * vmalloc faults work because attached pagetables are never freed. + * If the locking proves to be non-performant, a ticketing scheme with + * checks at dup_mmap(), exec(), and other mmlist addition points + * could be used. The locking scheme was chosen on the basis of + * manfred's recommendations and having no core impact whatsoever. + * -- wli + */ +spinlock_t pgd_lock = SPIN_LOCK_UNLOCKED; +LIST_HEAD(pgd_list); + +void pgd_ctor(void *pgd, kmem_cache_t *cache, unsigned long unused) { - int i; - pgd_t *pgd = kmem_cache_alloc(pae_pgd_cachep, GFP_KERNEL); + unsigned long flags; - if (pgd) { - for (i = 0; i < USER_PTRS_PER_PGD; i++) { - unsigned long pmd = __get_free_page(GFP_KERNEL); - if (!pmd) - goto out_oom; - clear_page(pmd); - set_pgd(pgd + i, __pgd(1 + __pa(pmd))); - } - memcpy(pgd + USER_PTRS_PER_PGD, + if (PTRS_PER_PMD == 1) + spin_lock_irqsave(&pgd_lock, flags); + + memcpy((pgd_t *)pgd + USER_PTRS_PER_PGD, swapper_pg_dir + USER_PTRS_PER_PGD, (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); - } - return pgd; -out_oom: - for (i--; i >= 0; i--) - free_page((unsigned long)__va(pgd_val(pgd[i])-1)); - kmem_cache_free(pae_pgd_cachep, pgd); - return NULL; + + if (PTRS_PER_PMD > 1) + return; + + list_add(&virt_to_page(pgd)->lru, &pgd_list); + spin_unlock_irqrestore(&pgd_lock, flags); + memset(pgd, 0, USER_PTRS_PER_PGD*sizeof(pgd_t)); } -void pgd_free(pgd_t *pgd) +/* never called when PTRS_PER_PMD > 1 */ +void pgd_dtor(void *pgd, kmem_cache_t *cache, unsigned long unused) { - int i; + unsigned long flags; /* can be called from interrupt context */ - for (i = 0; i < USER_PTRS_PER_PGD; i++) - free_page((unsigned long)__va(pgd_val(pgd[i])-1)); - kmem_cache_free(pae_pgd_cachep, pgd); + spin_lock_irqsave(&pgd_lock, flags); + list_del(&virt_to_page(pgd)->lru); + spin_unlock_irqrestore(&pgd_lock, flags); } -#else - pgd_t *pgd_alloc(struct mm_struct *mm) { - pgd_t *pgd = (pgd_t *)__get_free_page(GFP_KERNEL); + int i; + pgd_t *pgd = kmem_cache_alloc(pgd_cache, GFP_KERNEL); - if (pgd) { - memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t)); - memcpy(pgd + USER_PTRS_PER_PGD, - swapper_pg_dir + USER_PTRS_PER_PGD, - (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); + if (PTRS_PER_PMD == 1 || !pgd) + return pgd; + + for (i = 0; i < USER_PTRS_PER_PGD; ++i) { + pmd_t *pmd = kmem_cache_alloc(pmd_cache, GFP_KERNEL); + if (!pmd) + goto out_oom; + set_pgd(&pgd[i], __pgd(1 + __pa((u64)((u32)pmd)))); } return pgd; + +out_oom: + for (i--; i >= 0; i--) + kmem_cache_free(pmd_cache, (void *)__va(pgd_val(pgd[i])-1)); + kmem_cache_free(pgd_cache, pgd); + return NULL; } void pgd_free(pgd_t *pgd) { - free_page((unsigned long)pgd); -} - -#endif /* CONFIG_X86_PAE */ + int i; + /* in the PAE case user pgd entries are overwritten before usage */ + if (PTRS_PER_PMD > 1) + for (i = 0; i < USER_PTRS_PER_PGD; ++i) + kmem_cache_free(pmd_cache, (void *)__va(pgd_val(pgd[i])-1)); + /* in the non-PAE case, clear_page_tables() clears user pgd entries */ + kmem_cache_free(pgd_cache, pgd); +} --- linux-2.5.73/arch/i386/pci/acpi.c 2003-06-14 12:18:24.000000000 -0700 +++ 25/arch/i386/pci/acpi.c 2003-06-27 15:56:22.000000000 -0700 @@ -3,6 +3,16 @@ #include #include "pci.h" +struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_device *device, int domain, int busnum) +{ + if (domain != 0) { + printk(KERN_WARNING "PCI: Multiple domains not supported\n"); + return NULL; + } + + return pcibios_scan_root(busnum); +} + static int __init pci_acpi_init(void) { if (pcibios_scanned) --- linux-2.5.73/arch/i386/pci/common.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/pci/common.c 2003-06-27 15:56:22.000000000 -0700 @@ -27,14 +27,12 @@ struct pci_raw_ops *raw_pci_ops; static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) { - return raw_pci_ops->read(0, bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where, size, value); + return raw_pci_ops->read(0, bus->number, devfn, where, size, value); } static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) { - return raw_pci_ops->write(0, bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where, size, value); + return raw_pci_ops->write(0, bus->number, devfn, where, size, value); } struct pci_ops pci_root_ops = { --- linux-2.5.73/arch/i386/pci/direct.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/pci/direct.c 2003-06-27 15:56:22.000000000 -0700 @@ -10,19 +10,19 @@ * Functions for accessing PCI configuration space with type 1 accesses */ -#define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \ - (0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3)) +#define PCI_CONF1_ADDRESS(bus, devfn, reg) \ + (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3)) -static int pci_conf1_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) +static int pci_conf1_read (int seg, int bus, int devfn, int reg, int len, u32 *value) { unsigned long flags; - if (!value || (bus > 255) || (dev > 31) || (fn > 7) || (reg > 255)) + if (!value || (bus > 255) || (devfn > 255) || (reg > 255)) return -EINVAL; spin_lock_irqsave(&pci_config_lock, flags); - outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8); + outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); switch (len) { case 1: @@ -41,16 +41,16 @@ static int pci_conf1_read (int seg, int return 0; } -static int pci_conf1_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) +static int pci_conf1_write (int seg, int bus, int devfn, int reg, int len, u32 value) { unsigned long flags; - if ((bus > 255) || (dev > 31) || (fn > 7) || (reg > 255)) + if ((bus > 255) || (devfn > 255) || (reg > 255)) return -EINVAL; spin_lock_irqsave(&pci_config_lock, flags); - outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8); + outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); switch (len) { case 1: @@ -83,13 +83,17 @@ struct pci_raw_ops pci_direct_conf1 = { #define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg) -static int pci_conf2_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) +static int pci_conf2_read(int seg, int bus, int devfn, int reg, int len, u32 *value) { unsigned long flags; + int dev, fn; - if (!value || (bus > 255) || (dev > 31) || (fn > 7) || (reg > 255)) + if (!value || (bus > 255) || (devfn > 255) || (reg > 255)) return -EINVAL; + dev = PCI_SLOT(devfn); + fn = PCI_FUNC(devfn); + if (dev & 0x10) return PCIBIOS_DEVICE_NOT_FOUND; @@ -110,20 +114,24 @@ static int pci_conf2_read (int seg, int break; } - outb (0, 0xCF8); + outb(0, 0xCF8); spin_unlock_irqrestore(&pci_config_lock, flags); return 0; } -static int pci_conf2_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) +static int pci_conf2_write (int seg, int bus, int devfn, int reg, int len, u32 value) { unsigned long flags; + int dev, fn; - if ((bus > 255) || (dev > 31) || (fn > 7) || (reg > 255)) + if ((bus > 255) || (devfn > 255) || (reg > 255)) return -EINVAL; + dev = PCI_SLOT(devfn); + fn = PCI_FUNC(devfn); + if (dev & 0x10) return PCIBIOS_DEVICE_NOT_FOUND; @@ -134,17 +142,17 @@ static int pci_conf2_write (int seg, int switch (len) { case 1: - outb ((u8)value, PCI_CONF2_ADDRESS(dev, reg)); + outb((u8)value, PCI_CONF2_ADDRESS(dev, reg)); break; case 2: - outw ((u16)value, PCI_CONF2_ADDRESS(dev, reg)); + outw((u16)value, PCI_CONF2_ADDRESS(dev, reg)); break; case 4: - outl ((u32)value, PCI_CONF2_ADDRESS(dev, reg)); + outl((u32)value, PCI_CONF2_ADDRESS(dev, reg)); break; } - outb (0, 0xCF8); + outb(0, 0xCF8); spin_unlock_irqrestore(&pci_config_lock, flags); @@ -178,14 +186,12 @@ static int __devinit pci_sanity_check(st return 1; for (devfn = 0; devfn < 0x100; devfn++) { - if (o->read(0, 0, PCI_SLOT(devfn), PCI_FUNC(devfn), - PCI_CLASS_DEVICE, 2, &x)) + if (o->read(0, 0, devfn, PCI_CLASS_DEVICE, 2, &x)) continue; if (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA) return 1; - if (o->read(0, 0, PCI_SLOT(devfn), PCI_FUNC(devfn), - PCI_VENDOR_ID, 2, &x)) + if (o->read(0, 0, devfn, PCI_VENDOR_ID, 2, &x)) continue; if (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ) return 1; @@ -195,54 +201,84 @@ static int __devinit pci_sanity_check(st return 0; } -static int __init pci_direct_init(void) +static int __init pci_check_type1(void) { + unsigned long flags; unsigned int tmp; + int works = 0; + + local_irq_save(flags); + + outb(0x01, 0xCFB); + tmp = inl(0xCF8); + outl(0x80000000, 0xCF8); + if (inl(0xCF8) == 0x80000000 && pci_sanity_check(&pci_direct_conf1)) { + works = 1; + } + outl(tmp, 0xCF8); + local_irq_restore(flags); + + return works; +} + +static int __init pci_check_type2(void) +{ unsigned long flags; + int works = 0; local_irq_save(flags); - /* - * Check if configuration type 1 works. - */ - if (pci_probe & PCI_PROBE_CONF1) { - outb (0x01, 0xCFB); - tmp = inl (0xCF8); - outl (0x80000000, 0xCF8); - if (inl (0xCF8) == 0x80000000 && - pci_sanity_check(&pci_direct_conf1)) { - outl (tmp, 0xCF8); - local_irq_restore(flags); - printk(KERN_INFO "PCI: Using configuration type 1\n"); - if (!request_region(0xCF8, 8, "PCI conf1")) - raw_pci_ops = NULL; - else - raw_pci_ops = &pci_direct_conf1; - return 0; - } - outl (tmp, 0xCF8); - } - - /* - * Check if configuration type 2 works. - */ - if (pci_probe & PCI_PROBE_CONF2) { - outb (0x00, 0xCFB); - outb (0x00, 0xCF8); - outb (0x00, 0xCFA); - if (inb (0xCF8) == 0x00 && inb (0xCFA) == 0x00 && - pci_sanity_check(&pci_direct_conf2)) { - local_irq_restore(flags); - printk(KERN_INFO "PCI: Using configuration type 2\n"); - if (!request_region(0xCF8, 4, "PCI conf2")) - raw_pci_ops = NULL; - else - raw_pci_ops = &pci_direct_conf2; - return 0; - } + outb(0x00, 0xCFB); + outb(0x00, 0xCF8); + outb(0x00, 0xCFA); + if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 && + pci_sanity_check(&pci_direct_conf2)) { + works = 1; } local_irq_restore(flags); + + return works; +} + +static int __init pci_direct_init(void) +{ + struct resource *region, *region2; + + if ((pci_probe & PCI_PROBE_CONF1) == 0) + goto type2; + region = request_region(0xCF8, 8, "PCI conf1"); + if (!region) + goto type2; + + if (pci_check_type1()) { + printk(KERN_INFO "PCI: Using configuration type 1\n"); + raw_pci_ops = &pci_direct_conf1; + return 0; + } + release_resource(region); + + type2: + if ((!pci_probe & PCI_PROBE_CONF2) == 0) + goto out; + region = request_region(0xCF8, 4, "PCI conf2"); + if (!region) + goto out; + region2 = request_region(0xC000, 0x1000, "PCI conf2"); + if (!region2) + goto fail2; + + if (pci_check_type2()) { + printk(KERN_INFO "PCI: Using configuration type 2\n"); + raw_pci_ops = &pci_direct_conf2; + return 0; + } + + release_resource(region2); + fail2: + release_resource(region); + + out: return 0; } --- linux-2.5.73/arch/i386/pci/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/pci/Makefile 2003-06-27 15:56:22.000000000 -0700 @@ -1,27 +1,13 @@ -obj-y := i386.o +obj-y := i386.o obj-$(CONFIG_PCI_BIOS) += pcbios.o obj-$(CONFIG_PCI_DIRECT) += direct.o -obj-$(CONFIG_X86_VISWS) += visws.o +pci-y := fixup.o +pci-$(CONFIG_ACPI_PCI) += acpi.o +pci-y += legacy.o irq.o -ifdef CONFIG_X86_NUMAQ -obj-y += numa.o -else -obj-y += fixup.o +pci-$(CONFIG_X86_VISWS) := visws.o fixup.o +pci-$(CONFIG_X86_NUMAQ) := numa.o irq.o -ifdef CONFIG_ACPI_PCI -obj-y += acpi.o -endif - -ifndef CONFIG_X86_VISWS -obj-y += legacy.o -endif - -endif # CONFIG_X86_NUMAQ - -ifndef CONFIG_X86_VISWS -obj-y += irq.o -endif - -obj-y += common.o +obj-y += $(pci-y) common.o --- linux-2.5.73/arch/i386/pci/numa.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/pci/numa.c 2003-06-27 15:56:22.000000000 -0700 @@ -10,19 +10,19 @@ #define BUS2LOCAL(global) (mp_bus_id_to_local[global]) #define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local]) -#define PCI_CONF1_MQ_ADDRESS(bus, dev, fn, reg) \ - (0x80000000 | (BUS2LOCAL(bus) << 16) | (dev << 11) | (fn << 8) | (reg & ~3)) +#define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \ + (0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3)) -static int pci_conf1_mq_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) +static int pci_conf1_mq_read (int seg, int bus, int devfn, int reg, int len, u32 *value) { unsigned long flags; - if (!value || (bus > MAX_MP_BUSSES) || (dev > 31) || (fn > 7) || (reg > 255)) + if (!value || (bus > MAX_MP_BUSSES) || (devfn > 255) || (reg > 255)) return -EINVAL; spin_lock_irqsave(&pci_config_lock, flags); - outl_quad(PCI_CONF1_MQ_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus)); + outl_quad(PCI_CONF1_MQ_ADDRESS(bus, devfn, reg), 0xCF8, BUS2QUAD(bus)); switch (len) { case 1: @@ -41,16 +41,16 @@ static int pci_conf1_mq_read (int seg, i return 0; } -static int pci_conf1_mq_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) +static int pci_conf1_mq_write (int seg, int bus, int devfn, int reg, int len, u32 value) { unsigned long flags; - if ((bus > MAX_MP_BUSSES) || (dev > 31) || (fn > 7) || (reg > 255)) + if ((bus > MAX_MP_BUSSES) || (devfn > 255) || (reg > 255)) return -EINVAL; spin_lock_irqsave(&pci_config_lock, flags); - outl_quad(PCI_CONF1_MQ_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus)); + outl_quad(PCI_CONF1_MQ_ADDRESS(bus, devfn, reg), 0xCF8, BUS2QUAD(bus)); switch (len) { case 1: --- linux-2.5.73/arch/i386/pci/pcbios.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/pci/pcbios.c 2003-06-27 15:56:22.000000000 -0700 @@ -172,13 +172,13 @@ static int __devinit pci_bios_find_devic return (int) (ret & 0xff00) >> 8; } -static int pci_bios_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) +static int pci_bios_read (int seg, int bus, int devfn, int reg, int len, u32 *value) { unsigned long result = 0; unsigned long flags; - unsigned long bx = ((bus << 8) | (dev << 3) | fn); + unsigned long bx = (bus << 8) | devfn; - if (!value || (bus > 255) || (dev > 31) || (fn > 7) || (reg > 255)) + if (!value || (bus > 255) || (devfn > 255) || (reg > 255)) return -EINVAL; spin_lock_irqsave(&pci_config_lock, flags); @@ -227,13 +227,13 @@ static int pci_bios_read (int seg, int b return (int)((result & 0xff00) >> 8); } -static int pci_bios_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) +static int pci_bios_write (int seg, int bus, int devfn, int reg, int len, u32 value) { unsigned long result = 0; unsigned long flags; - unsigned long bx = ((bus << 8) | (dev << 3) | fn); + unsigned long bx = (bus << 8) | devfn; - if ((bus > 255) || (dev > 31) || (fn > 7) || (reg > 255)) + if ((bus > 255) || (devfn > 255) || (reg > 255)) return -EINVAL; spin_lock_irqsave(&pci_config_lock, flags); --- linux-2.5.73/arch/i386/vmlinux.lds.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/i386/vmlinux.lds.S 2003-06-27 15:56:32.000000000 -0700 @@ -10,7 +10,7 @@ ENTRY(startup_32) jiffies = jiffies_64; SECTIONS { - . = 0xC0000000 + 0x100000; + . = __PAGE_OFFSET + 0x100000; /* read-only */ _text = .; /* Text and read-only data */ .text : { --- linux-2.5.73/arch/ia64/defconfig 2003-06-14 12:17:57.000000000 -0700 +++ 25/arch/ia64/defconfig 2003-06-27 15:56:22.000000000 -0700 @@ -10,30 +10,38 @@ CONFIG_EXPERIMENTAL=y # # General setup # -CONFIG_NET=y +CONFIG_SWAP=y CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_BSD_PROCESS_ACCT=y CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y # # Loadable module support # CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_OBSOLETE_MODPARM=y CONFIG_MODVERSIONS=y -# CONFIG_KMOD is not set +CONFIG_KMOD=y # # Processor type and features # CONFIG_IA64=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_ITANIUM=y -# CONFIG_MCKINLEY is not set +CONFIG_MMU=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_TIME_INTERPOLATION=y +# CONFIG_ITANIUM is not set +CONFIG_MCKINLEY=y # CONFIG_IA64_GENERIC is not set -CONFIG_IA64_DIG=y +# CONFIG_IA64_DIG is not set # CONFIG_IA64_HP_SIM is not set -# CONFIG_IA64_HP_ZX1 is not set -# CONFIG_IA64_SGI_SN1 is not set +CONFIG_IA64_HP_ZX1=y # CONFIG_IA64_SGI_SN2 is not set # CONFIG_IA64_PAGE_SIZE_4KB is not set # CONFIG_IA64_PAGE_SIZE_8KB is not set @@ -43,41 +51,64 @@ CONFIG_ACPI=y CONFIG_ACPI_EFI=y CONFIG_ACPI_INTERPRETER=y CONFIG_ACPI_KERNEL_CONFIG=y -CONFIG_IA64_BRL_EMU=y -# CONFIG_ITANIUM_BSTEP_SPECIFIC is not set -CONFIG_IA64_L1_CACHE_SHIFT=6 +CONFIG_IA64_L1_CACHE_SHIFT=7 +# CONFIG_MCKINLEY_ASTEP_SPECIFIC is not set # CONFIG_NUMA is not set +CONFIG_VIRTUAL_MEM_MAP=y CONFIG_IA64_MCA=y CONFIG_PM=y CONFIG_IOSAPIC=y CONFIG_KCORE_ELF=y CONFIG_FORCE_MAX_ZONEORDER=18 -# CONFIG_HUGETLB_PAGE is not set +CONFIG_HUGETLB_PAGE=y +# CONFIG_HUGETLB_PAGE_SIZE_4GB is not set +# CONFIG_HUGETLB_PAGE_SIZE_1GB is not set +# CONFIG_HUGETLB_PAGE_SIZE_256MB is not set +CONFIG_HUGETLB_PAGE_SIZE_64MB=y +# CONFIG_HUGETLB_PAGE_SIZE_16MB is not set +# CONFIG_HUGETLB_PAGE_SIZE_4MB is not set +# CONFIG_HUGETLB_PAGE_SIZE_1MB is not set +# CONFIG_HUGETLB_PAGE_SIZE_256KB is not set +CONFIG_IA64_PAL_IDLE=y CONFIG_SMP=y +# CONFIG_PREEMPT is not set CONFIG_IA32_SUPPORT=y +CONFIG_COMPAT=y CONFIG_PERFMON=y CONFIG_IA64_PALINFO=y CONFIG_EFI_VARS=y CONFIG_NR_CPUS=16 CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set +CONFIG_BINFMT_MISC=y # # ACPI Support # CONFIG_ACPI_BOOT=y CONFIG_ACPI_BUTTON=y -CONFIG_ACPI_FAN=m -CONFIG_ACPI_PROCESSOR=m -CONFIG_ACPI_THERMAL=m +CONFIG_ACPI_FAN=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_THERMAL=y # CONFIG_ACPI_DEBUG is not set CONFIG_ACPI_BUS=y CONFIG_ACPI_POWER=y CONFIG_ACPI_PCI=y CONFIG_ACPI_SYSTEM=y CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LEGACY_PROC=y CONFIG_PCI_NAMES=y -# CONFIG_HOTPLUG is not set +CONFIG_HOTPLUG=y + +# +# PCI Hotplug Support +# +# CONFIG_HOTPLUG_PCI is not set + +# +# PCMCIA/CardBus support +# +# CONFIG_PCMCIA is not set # # Parallel port support @@ -85,12 +116,17 @@ CONFIG_PCI_NAMES=y # CONFIG_PARPORT is not set # +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# # Memory Technology Devices (MTD) # # CONFIG_MTD is not set # -# Plug and Play configuration +# Plug and Play support # # CONFIG_PNP is not set @@ -104,7 +140,9 @@ CONFIG_PCI_NAMES=y # CONFIG_BLK_DEV_UMEM is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_INITRD=y # # IEEE 1394 (FireWire) support (EXPERIMENTAL) @@ -124,64 +162,11 @@ CONFIG_BLK_DEV_LOOP=y # # Fusion MPT device support # -# CONFIG_FUSION is not set - -# -# ATA/ATAPI/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -CONFIG_IDEDISK_MULTI_MODE=y -# CONFIG_IDEDISK_STROKE is not set -CONFIG_BLK_DEV_IDECD=y -CONFIG_BLK_DEV_IDEFLOPPY=y -CONFIG_BLK_DEV_IDESCSI=y -# CONFIG_IDE_TASK_IOCTL is not set - -# -# IDE chipset support/bugfixes -# -CONFIG_BLK_DEV_IDEPCI=y -# CONFIG_BLK_DEV_GENERIC is not set -CONFIG_IDEPCI_SHARE_IRQ=y -CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_IDE_TCQ is not set -# CONFIG_BLK_DEV_OFFBOARD is not set -# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -# CONFIG_IDEDMA_PCI_AUTO is not set -CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_PCI_WIP is not set -CONFIG_BLK_DEV_ADMA=y -# CONFIG_BLK_DEV_AEC62XX is not set -# CONFIG_BLK_DEV_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set -# CONFIG_BLK_DEV_CMD64X is not set -# CONFIG_BLK_DEV_CY82C693 is not set -# CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_NFORCE is not set -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_OPTI621 is not set -# CONFIG_BLK_DEV_PDC202XX_OLD is not set -# CONFIG_BLK_DEV_PDC202XX_NEW is not set -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SIIMAGE is not set -# CONFIG_BLK_DEV_SLC90E66 is not set -# CONFIG_BLK_DEV_TRM290 is not set -# CONFIG_BLK_DEV_VIA82CXXX is not set -# CONFIG_IDEDMA_IVB is not set +CONFIG_FUSION=y +CONFIG_FUSION_BOOT=y +CONFIG_FUSION_MAX_SGE=40 +# CONFIG_FUSION_ISENSE is not set +# CONFIG_FUSION_CTL is not set # # SCSI support @@ -192,16 +177,17 @@ CONFIG_SCSI=y # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set +CONFIG_CHR_DEV_ST=y +CONFIG_CHR_DEV_OSST=y +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=y # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs # -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_REPORT_LUNS is not set +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_REPORT_LUNS=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y @@ -212,57 +198,76 @@ CONFIG_SCSI_LOGGING=y # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set +CONFIG_SCSI_AIC7XXX_OLD=y +# CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set +CONFIG_SCSI_MEGARAID=y # CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_CPQFCTS is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set # CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_NCR53C8XX is not set -# CONFIG_SCSI_SYM53C8XX is not set +CONFIG_SCSI_SYM53C8XX_2=y +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set # CONFIG_SCSI_PCI2000 is not set # CONFIG_SCSI_PCI2220I is not set # CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set CONFIG_SCSI_QLOGIC_1280=y +# CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_U14_34F is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # +# Networking support +# +CONFIG_NET=y + +# # Networking options # CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y +# CONFIG_PACKET_MMAP is not set # CONFIG_NETLINK_DEV is not set -# CONFIG_NETFILTER is not set -CONFIG_FILTER=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set CONFIG_UNIX=y +# CONFIG_NET_KEY is not set CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set +CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set # CONFIG_IP_PNP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set # CONFIG_ARPD is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +CONFIG_IP_NF_ARPTABLES=y +# CONFIG_IP_NF_ARPFILTER is not set +# CONFIG_IP_NF_COMPAT_IPCHAINS is not set +# CONFIG_IP_NF_COMPAT_IPFWADM is not set # CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set # # SCTP Configuration (EXPERIMENTAL) @@ -288,8 +293,9 @@ CONFIG_IPV6_SCTP__=y # CONFIG_NET_SCHED is not set # -# Network device support +# Network testing # +# CONFIG_NET_PKTGEN is not set CONFIG_NETDEVICES=y # @@ -297,7 +303,7 @@ CONFIG_NETDEVICES=y # # CONFIG_ARCNET is not set CONFIG_DUMMY=y -# CONFIG_BONDING is not set +CONFIG_BONDING=y # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # CONFIG_ETHERTAP is not set @@ -306,11 +312,10 @@ CONFIG_DUMMY=y # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y +CONFIG_MII=y # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set # # Tulip family network device support @@ -319,9 +324,12 @@ CONFIG_NET_ETHERNET=y # CONFIG_HP100 is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set # CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set # CONFIG_DGRS is not set CONFIG_EEPRO100=y +# CONFIG_EEPRO100_PIO is not set # CONFIG_E100 is not set # CONFIG_FEALNX is not set # CONFIG_NATSEMI is not set @@ -333,19 +341,25 @@ CONFIG_EEPRO100=y # CONFIG_SUNDANCE is not set # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set -# CONFIG_NET_POCKET is not set # # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set # CONFIG_DL2K is not set -# CONFIG_E1000 is not set +CONFIG_E1000=y +# CONFIG_E1000_NAPI is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set # CONFIG_SK98LIN is not set -# CONFIG_TIGON3 is not set +CONFIG_TIGON3=m + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PPP is not set @@ -357,9 +371,8 @@ CONFIG_EEPRO100=y # CONFIG_NET_RADIO is not set # -# Token Ring devices +# Token Ring devices (depends on LLC=y) # -# CONFIG_TR is not set # CONFIG_NET_FC is not set # CONFIG_RCPCI is not set # CONFIG_SHAPER is not set @@ -393,10 +406,10 @@ CONFIG_INPUT=y # Userland interfaces # CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_JOYDEV=y # CONFIG_INPUT_TSDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set @@ -407,26 +420,19 @@ CONFIG_INPUT_EVDEV=y # CONFIG_GAMEPORT is not set CONFIG_SOUND_GAMEPORT=y CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set # CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set # # Input Device Drivers # -CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_NEWTON is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -# CONFIG_MOUSE_SERIAL is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TOUCHSCREEN is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_PCSPKR is not set -# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_MISC is not set # # Character devices @@ -441,12 +447,9 @@ CONFIG_HW_CONSOLE=y # CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EXTENDED=y -# CONFIG_SERIAL_8250_MANY_PORTS is not set -CONFIG_SERIAL_8250_SHARE_IRQ=y -# CONFIG_SERIAL_8250_DETECT_IRQ is not set -# CONFIG_SERIAL_8250_MULTIPORT is not set -# CONFIG_SERIAL_8250_RSA is not set +CONFIG_SERIAL_8250_ACPI=y +CONFIG_SERIAL_8250_HCDP=y +# CONFIG_SERIAL_8250_EXTENDED is not set # # Non-8250 serial port support @@ -459,14 +462,16 @@ CONFIG_UNIX98_PTY_COUNT=256 # # I2C support # -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -# CONFIG_I2C_ELV is not set -# CONFIG_I2C_VELLEMAN is not set -# CONFIG_SCx200_ACB is not set -# CONFIG_I2C_ALGOPCF is not set -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_PROC=y +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set # # Mice @@ -475,12 +480,16 @@ CONFIG_I2C_PROC=y # CONFIG_QIC02_TAPE is not set # +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# # Watchdog Cards # # CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set +# CONFIG_HW_RANDOM is not set # CONFIG_NVRAM is not set -# CONFIG_RTC is not set # CONFIG_GEN_RTC is not set CONFIG_EFI_RTC=y # CONFIG_DTLK is not set @@ -491,25 +500,17 @@ CONFIG_EFI_RTC=y # Ftape, the floppy tape device driver # # CONFIG_FTAPE is not set -CONFIG_AGP=y -CONFIG_AGP_INTEL=y -CONFIG_AGP_I810=y -CONFIG_AGP_VIA=y -CONFIG_AGP_AMD=y -CONFIG_AGP_SIS=y -CONFIG_AGP_ALI=y -CONFIG_AGP_SWORKS=y -# CONFIG_AGP_AMD_8151 is not set -CONFIG_AGP_I460=y -CONFIG_AGP_HP_ZX1=y +CONFIG_AGP=m +CONFIG_AGP_I460=m +CONFIG_AGP_HP_ZX1=m CONFIG_DRM=y -CONFIG_DRM_TDFX=y -CONFIG_DRM_R128=y -CONFIG_DRM_RADEON=y -CONFIG_DRM_I810=y -CONFIG_DRM_I830=y -CONFIG_DRM_MGA=y +# CONFIG_DRM_TDFX is not set +# CONFIG_DRM_GAMMA is not set +# CONFIG_DRM_R128 is not set +CONFIG_DRM_RADEON=m +# CONFIG_DRM_MGA is not set # CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set # # Multimedia devices @@ -517,51 +518,79 @@ CONFIG_DRM_MGA=y # CONFIG_VIDEO_DEV is not set # +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# # File systems # +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set CONFIG_AUTOFS_FS=y # CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +# CONFIG_DEVPTS_FS_XATTR is not set +CONFIG_TMPFS=y +CONFIG_HUGETLBFS=y +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set -CONFIG_EXT3_FS=y -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y # CONFIG_EFS_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_TMPFS is not set -CONFIG_RAMFS=y -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_ZISOFS is not set -# CONFIG_JFS_FS is not set -# CONFIG_MINIX_FS is not set # CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set # CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_XFS_FS is not set # # Network File Systems # -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y CONFIG_NFS_V3=y CONFIG_NFS_V4=y @@ -569,13 +598,16 @@ CONFIG_NFSD=y CONFIG_NFSD_V3=y # CONFIG_NFSD_V4 is not set # CONFIG_NFSD_TCP is not set -CONFIG_SUNRPC=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=y -# CONFIG_CIFS is not set +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y # CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set # CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set # CONFIG_AFS_FS is not set # @@ -593,6 +625,7 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_LDM_PARTITION is not set +# CONFIG_NEC98_PARTITION is not set # CONFIG_SGI_PARTITION is not set # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set @@ -603,53 +636,84 @@ CONFIG_NLS=y # Native Language Support # CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +CONFIG_NLS_CODEPAGE_874=y +CONFIG_NLS_ISO8859_8=y # CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_3=y +CONFIG_NLS_ISO8859_4=y +CONFIG_NLS_ISO8859_5=y +CONFIG_NLS_ISO8859_6=y +CONFIG_NLS_ISO8859_7=y +CONFIG_NLS_ISO8859_9=y +CONFIG_NLS_ISO8859_13=y +CONFIG_NLS_ISO8859_14=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_KOI8_R=y +CONFIG_NLS_KOI8_U=y +CONFIG_NLS_UTF8=y + +# +# Graphics support +# +CONFIG_FB=y +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_IMSTT is not set +CONFIG_FB_RIVA=m +# CONFIG_FB_MATROX is not set +CONFIG_FB_RADEON=y +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_VIRTUAL is not set # -# Console drivers +# Console display driver support # CONFIG_VGA_CONSOLE=y +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_PCI_CONSOLE=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y # -# Frame-buffer support -# -# CONFIG_FB is not set +# Logo configuration +# +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y # # Sound @@ -659,31 +723,62 @@ CONFIG_SOUND=y # # Advanced Linux Sound Architecture # -# CONFIG_SND is not set +CONFIG_SND=m +CONFIG_SND_SEQUENCER=m +# CONFIG_SND_SEQ_DUMMY is not set +# CONFIG_SND_OSSEMUL is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_YMFPCI is not set +# CONFIG_SND_ALS4000 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_MAESTRO3 is not set +CONFIG_SND_FM801=m +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VX222 is not set + +# +# ALSA USB devices +# +# CONFIG_SND_USB_AUDIO is not set # # Open Sound System # -CONFIG_SOUND_PRIME=y -# CONFIG_SOUND_BT878 is not set -# CONFIG_SOUND_CMPCI is not set -# CONFIG_SOUND_EMU10K1 is not set -# CONFIG_SOUND_FUSION is not set -CONFIG_SOUND_CS4281=y -# CONFIG_SOUND_ES1370 is not set -# CONFIG_SOUND_ES1371 is not set -# CONFIG_SOUND_ESSSOLO1 is not set -# CONFIG_SOUND_MAESTRO is not set -# CONFIG_SOUND_MAESTRO3 is not set -# CONFIG_SOUND_ICH is not set -# CONFIG_SOUND_RME96XX is not set -# CONFIG_SOUND_SONICVIBES is not set -# CONFIG_SOUND_TRIDENT is not set -# CONFIG_SOUND_MSNDCLAS is not set -# CONFIG_SOUND_MSNDPIN is not set -# CONFIG_SOUND_VIA82CXXX is not set -# CONFIG_SOUND_OSS is not set -# CONFIG_SOUND_TVMIXER is not set +# CONFIG_SOUND_PRIME is not set # # USB support @@ -694,17 +789,16 @@ CONFIG_USB=y # # Miscellaneous USB options # -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_LONG_TIMEOUT is not set -# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_BANDWIDTH=y # CONFIG_USB_DYNAMIC_MINORS is not set # # USB Host Controller Drivers # -# CONFIG_USB_EHCI_HCD is not set -# CONFIG_USB_OHCI_HCD is not set -CONFIG_USB_UHCI_HCD_ALT=y +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_UHCI_HCD=m # # USB Device Class drivers @@ -725,6 +819,7 @@ CONFIG_USB_HIDINPUT=y CONFIG_USB_HIDDEV=y # CONFIG_USB_AIPTEK is not set # CONFIG_USB_WACOM is not set +# CONFIG_USB_KBTAB is not set # CONFIG_USB_POWERMATE is not set # CONFIG_USB_XPAD is not set @@ -748,8 +843,8 @@ CONFIG_USB_HIDDEV=y # # USB Network adaptors # +# CONFIG_USB_AX8817X is not set # CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set @@ -772,17 +867,17 @@ CONFIG_USB_HIDDEV=y # CONFIG_USB_RIO500 is not set # CONFIG_USB_BRLVGER is not set # CONFIG_USB_LCD is not set -# CONFIG_USB_TEST is not set +# CONFIG_USB_GADGET is not set # -# Library routines +# Bluetooth support # -# CONFIG_CRC32 is not set +# CONFIG_BT is not set # -# Bluetooth support +# Library routines # -# CONFIG_BT is not set +CONFIG_CRC32=y # # Kernel hacking @@ -794,18 +889,17 @@ CONFIG_KALLSYMS=y CONFIG_IA64_PRINT_HAZARDS=y # CONFIG_DISABLE_VHPT is not set CONFIG_MAGIC_SYSRQ=y -CONFIG_IA64_EARLY_PRINTK=y -# CONFIG_IA64_EARLY_PRINTK_UART is not set -CONFIG_IA64_EARLY_PRINTK_VGA=y +# CONFIG_IA64_EARLY_PRINTK is not set # CONFIG_DEBUG_SLAB is not set # CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_IA64_DEBUG_CMPXCHG is not set # CONFIG_IA64_DEBUG_IRQ is not set # # Security options # -CONFIG_SECURITY_CAPABILITIES=y +# CONFIG_SECURITY is not set # # Cryptographic options --- linux-2.5.73/arch/ia64/Kconfig 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/Kconfig 2003-06-27 15:56:22.000000000 -0700 @@ -544,6 +544,8 @@ source "drivers/pnp/Kconfig" source "drivers/block/Kconfig" +source "drivers/ide/Kconfig" + source "drivers/ieee1394/Kconfig" source "drivers/message/i2o/Kconfig" @@ -555,32 +557,8 @@ source "drivers/message/fusion/Kconfig" endif -menu "SCSI support" - -config SCSI - tristate "SCSI support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - source "drivers/scsi/Kconfig" -endmenu - source "net/Kconfig" @@ -590,42 +568,8 @@ source "net/ax25/Kconfig" source "drivers/isdn/Kconfig" - -menu "CD-ROM drivers (not for SCSI or IDE/ATAPI drives)" - -config CD_NO_IDESCSI - bool "Support non-SCSI/IDE/ATAPI CDROM drives" - ---help--- - If you have a CD-ROM drive that is neither SCSI nor IDE/ATAPI, say Y - here, otherwise N. Read the CD-ROM-HOWTO, available from - . - - Note that the answer to this question doesn't directly affect the - kernel: saying N will just cause the configurator to skip all - the questions about these CD-ROM drives. If you are unsure what you - have, say Y and find out whether you have one of the following - drives. - - For each of these drivers, a file Documentation/cdrom/{driver_name} - exists. Especially in cases where you do not know exactly which kind - of drive you have you should read there. Most of these drivers use a - file drivers/cdrom/{driver_name}.h where you can define your - interface parameters and switch some internal goodies. - - All these CD-ROM drivers are also usable as a module ( = code which - can be inserted in and removed from the running kernel whenever you - want). If you want to compile them as module, say M instead of Y and - read . - - If you want to use any of these CD-ROM drivers, you also have to - answer Y or M to "ISO 9660 CD-ROM file system support" below (this - answer will get "defaulted" for you if you enable any of the Linux - CD-ROM drivers). - source "drivers/cdrom/Kconfig" -endmenu - # # input before char - char/joystick depends on it. As does USB. # @@ -787,6 +731,10 @@ config IA64_EARLY_PRINTK_VGA bool "Early printk on VGA" depends on IA64_EARLY_PRINTK +config IA64_EARLY_PRINTK_SGI_SN + bool "Early printk on SGI SN serial console" + depends on IA64_EARLY_PRINTK && (IA64_GENERIC || IA64_SGI_SN2) + config DEBUG_SLAB bool "Debug memory allocations" depends on DEBUG_KERNEL --- linux-2.5.73/arch/ia64/kernel/acpi.c 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/kernel/acpi.c 2003-06-27 15:56:22.000000000 -0700 @@ -575,59 +575,6 @@ acpi_find_rsdp (void) } -#ifdef CONFIG_SERIAL_8250_ACPI - -#include - -static int __init -acpi_parse_spcr (unsigned long phys_addr, unsigned long size) -{ - acpi_ser_t *spcr; - unsigned int gsi; - - if (!phys_addr || !size) - return -EINVAL; - - if (!iosapic_register_intr) - return -ENODEV; - - /* - * ACPI is able to describe serial ports that live at non-standard - * memory addresses and use non-standard interrupts, either via - * direct SAPIC mappings or via PCI interrupts. We handle interrupt - * routing for SAPIC-based (non-PCI) devices here. Interrupt routing - * for PCI devices will be handled when processing the PCI Interrupt - * Routing Table (PRT). - */ - - spcr = (acpi_ser_t *) __va(phys_addr); - - setup_serial_acpi(spcr); - - if (spcr->length < sizeof(acpi_ser_t)) - /* Table not long enough for full info, thus no interrupt */ - return -ENODEV; - - if ((spcr->base_addr.space_id != ACPI_SERIAL_PCICONF_SPACE) && - (spcr->int_type == ACPI_SERIAL_INT_SAPIC)) - { - int vector; - - /* We have a UART in memory space with an SAPIC interrupt */ - - gsi = ( (spcr->global_int[3] << 24) | - (spcr->global_int[2] << 16) | - (spcr->global_int[1] << 8) | - (spcr->global_int[0]) ); - - vector = iosapic_register_intr(gsi, IOSAPIC_POL_HIGH, IOSAPIC_EDGE); - } - return 0; -} - -#endif /* CONFIG_SERIAL_8250_ACPI */ - - int __init acpi_boot_init (void) { @@ -682,16 +629,6 @@ acpi_boot_init (void) if (acpi_table_parse(ACPI_FADT, acpi_parse_fadt) < 1) printk(KERN_ERR PREFIX "Can't find FADT\n"); -#ifdef CONFIG_SERIAL_8250_ACPI - /* - * TBD: Need phased approach to table parsing (only do those absolutely - * required during boot-up). Recommend expanding concept of fix- - * feature devices (LDM) to include table-based devices such as - * serial ports, EC, SMBus, etc. - */ - acpi_table_parse(ACPI_SPCR, acpi_parse_spcr); -#endif - #ifdef CONFIG_SMP smp_boot_data.cpu_count = available_cpus; if (available_cpus == 0) { --- linux-2.5.73/arch/ia64/kernel/efi.c 2003-06-14 12:17:56.000000000 -0700 +++ 25/arch/ia64/kernel/efi.c 2003-06-27 15:56:22.000000000 -0700 @@ -46,7 +46,7 @@ static efi_runtime_services_t *runtime; * prior to creating their own entries under /proc/efi. */ #ifdef CONFIG_PROC_FS -struct proc_dir_entry *efi_dir = NULL; +struct proc_dir_entry *efi_dir; #endif static unsigned long mem_limit = ~0UL; --- linux-2.5.73/arch/ia64/kernel/efivars.c 2003-06-14 12:18:09.000000000 -0700 +++ 25/arch/ia64/kernel/efivars.c 2003-06-27 15:56:22.000000000 -0700 @@ -119,7 +119,7 @@ typedef struct _efivar_entry_t { */ static spinlock_t efivars_lock = SPIN_LOCK_UNLOCKED; static LIST_HEAD(efivar_list); -static struct proc_dir_entry *efi_vars_dir = NULL; +static struct proc_dir_entry *efi_vars_dir; #define efivar_entry(n) list_entry(n, efivar_entry_t, list) --- linux-2.5.73/arch/ia64/kernel/gate.S 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/kernel/gate.S 2003-06-27 15:56:22.000000000 -0700 @@ -199,7 +199,7 @@ GLOBAL_ENTRY(__kernel_sigtramp) cmp.ne p8,p0=r15,r0 // do we need to switch the rbs? mov.m r9=ar.bsp // fetch ar.bsp .spillsp.p p8, ar.rnat, RNAT_OFF+SIGCONTEXT_OFF -(p8) br.cond.spnt setup_rbs // yup -> (clobbers r14, r15, and r16) +(p8) br.cond.spnt setup_rbs // yup -> (clobbers p8, r14-r16, and r18-r20) back_from_setup_rbs: alloc r8=ar.pfs,0,0,3,0 ld8 out0=[base0],16 // load arg0 (signum) @@ -268,26 +268,30 @@ back_from_restore_rbs: setup_rbs: mov ar.rsc=0 // put RSE into enforced lazy mode ;; - .save ar.rnat, r16 - mov r16=ar.rnat // save RNaT before switching backing store area + .save ar.rnat, r19 + mov r19=ar.rnat // save RNaT before switching backing store area adds r14=(RNAT_OFF+SIGCONTEXT_OFF),sp + mov r18=ar.bspstore mov ar.bspstore=r15 // switch over to new register backing store area ;; + .spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF - st8 [r14]=r16 // save sc_ar_rnat + st8 [r14]=r19 // save sc_ar_rnat .body - adds r14=(LOADRS_OFF+SIGCONTEXT_OFF),sp - mov.m r16=ar.bsp // sc_loadrs <- (new bsp - new bspstore) << 16 + adds r14=(LOADRS_OFF+SIGCONTEXT_OFF),sp ;; invala sub r15=r16,r15 + extr.u r20=r18,3,6 ;; + mov ar.rsc=0xf // set RSE into eager mode, pl 3 + cmp.eq p8,p0=63,r20 shl r15=r15,16 ;; st8 [r14]=r15 // save sc_loadrs - mov ar.rsc=0xf // set RSE into eager mode, pl 3 +(p8) st8 [r18]=r19 // if bspstore points at RNaT slot, store RNaT there now .restore sp // pop .prologue br.cond.sptk back_from_setup_rbs --- linux-2.5.73/arch/ia64/kernel/head.S 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/kernel/head.S 2003-06-27 15:56:22.000000000 -0700 @@ -144,13 +144,13 @@ start_ap: movl r3=task_for_booting_cpu ;; ld8 r3=[r3] - movl r2=init_thread_union + movl r2=init_task ;; cmp.eq isBP,isAP=r3,r0 ;; (isAP) mov r2=r3 #else - movl r2=init_thread_union + movl r2=init_task cmp.eq isBP,isAP=r0,r0 #endif ;; --- linux-2.5.73/arch/ia64/kernel/init_task.c 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/kernel/init_task.c 2003-06-27 15:56:22.000000000 -0700 @@ -26,17 +26,17 @@ struct mm_struct init_mm = INIT_MM(init_ * We need to make sure that this is properly aligned due to the way process stacks are * handled. This is done by having a special ".data.init_task" section... */ -#define init_thread_info init_thread_union.s.thread_info +#define init_thread_info init_task_mem.s.thread_info -union init_thread { +static union { struct { struct task_struct task; struct thread_info thread_info; } s; unsigned long stack[KERNEL_STACK_SIZE/sizeof (unsigned long)]; -} init_thread_union __attribute__((section(".data.init_task"))) = {{ - .task = INIT_TASK(init_thread_union.s.task), - .thread_info = INIT_THREAD_INFO(init_thread_union.s.task) +} init_task_mem __attribute__((section(".data.init_task"))) = {{ + .task = INIT_TASK(init_task_mem.s.task), + .thread_info = INIT_THREAD_INFO(init_task_mem.s.task) }}; -asm (".global init_task; init_task = init_thread_union"); +asm (".global init_task; init_task = init_task_mem"); --- linux-2.5.73/arch/ia64/kernel/iosapic.c 2003-06-14 12:18:09.000000000 -0700 +++ 25/arch/ia64/kernel/iosapic.c 2003-06-27 15:56:22.000000000 -0700 @@ -382,7 +382,7 @@ iosapic_startup_edge_irq (unsigned int i static void iosapic_ack_edge_irq (unsigned int irq) { - irq_desc_t *idesc = irq_desc(irq); + irq_desc_t *idesc = irq_descp(irq); /* * Once we have recorded IRQ_PENDING already, we can mask the * interrupt for real. This prevents IRQ storms from unhandled @@ -478,7 +478,7 @@ register_intr (unsigned int gsi, int vec else irq_type = &irq_type_iosapic_level; - idesc = irq_desc(vector); + idesc = irq_descp(vector); if (idesc->handler != irq_type) { if (idesc->handler != &no_irq_type) printk(KERN_WARNING "%s: changing vector %d from %s to %s\n", @@ -724,7 +724,7 @@ iosapic_parse_prt (void) * If vector was previously initialized to a different * handler, re-initialize. */ - idesc = irq_desc(vector); + idesc = irq_descp(vector); if (idesc->handler != irq_type) register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, IOSAPIC_POL_LOW, IOSAPIC_LEVEL); --- linux-2.5.73/arch/ia64/kernel/irq.c 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/kernel/irq.c 2003-06-27 15:56:22.000000000 -0700 @@ -74,7 +74,7 @@ irq_desc_t _irq_desc[NR_IRQS] __cachelin }; #ifdef CONFIG_IA64_GENERIC -struct irq_desc * __ia64_irq_desc (unsigned int irq) +irq_desc_t * __ia64_irq_desc (unsigned int irq) { return _irq_desc + irq; } @@ -171,7 +171,7 @@ int show_interrupts(struct seq_file *p, seq_putc(p, '\n'); for (i = 0 ; i < NR_IRQS ; i++) { - idesc = irq_desc(i); + idesc = irq_descp(i); spin_lock_irqsave(&idesc->lock, flags); action = idesc->action; if (!action) @@ -218,7 +218,7 @@ skip: #ifdef CONFIG_SMP inline void synchronize_irq(unsigned int irq) { - while (irq_desc(irq)->status & IRQ_INPROGRESS) + while (irq_descp(irq)->status & IRQ_INPROGRESS) cpu_relax(); } #endif @@ -352,7 +352,7 @@ static void note_interrupt(int irq, irq_ inline void disable_irq_nosync(unsigned int irq) { - irq_desc_t *desc = irq_desc(irq); + irq_desc_t *desc = irq_descp(irq); unsigned long flags; spin_lock_irqsave(&desc->lock, flags); @@ -395,7 +395,7 @@ void disable_irq(unsigned int irq) void enable_irq(unsigned int irq) { - irq_desc_t *desc = irq_desc(irq); + irq_desc_t *desc = irq_descp(irq); unsigned long flags; spin_lock_irqsave(&desc->lock, flags); @@ -437,7 +437,7 @@ unsigned int do_IRQ(unsigned long irq, s * 0 return value means that this irq is already being * handled by some other CPU. (or is disabled) */ - irq_desc_t *desc = irq_desc(irq); + irq_desc_t *desc = irq_descp(irq); struct irqaction * action; irqreturn_t action_ret; unsigned int status; @@ -620,7 +620,7 @@ void free_irq(unsigned int irq, void *de if (irq >= NR_IRQS) return; - desc = irq_desc(irq); + desc = irq_descp(irq); spin_lock_irqsave(&desc->lock,flags); p = &desc->action; for (;;) { @@ -682,7 +682,7 @@ unsigned long probe_irq_on(void) * flush such a longstanding irq before considering it as spurious. */ for (i = NR_IRQS-1; i > 0; i--) { - desc = irq_desc(i); + desc = irq_descp(i); spin_lock_irq(&desc->lock); if (!desc->action) @@ -700,7 +700,7 @@ unsigned long probe_irq_on(void) * happened in the previous stage, it may have masked itself) */ for (i = NR_IRQS-1; i > 0; i--) { - desc = irq_desc(i); + desc = irq_descp(i); spin_lock_irq(&desc->lock); if (!desc->action) { @@ -722,7 +722,7 @@ unsigned long probe_irq_on(void) */ val = 0; for (i = 0; i < NR_IRQS; i++) { - irq_desc_t *desc = irq_desc(i); + irq_desc_t *desc = irq_descp(i); unsigned int status; spin_lock_irq(&desc->lock); @@ -762,7 +762,7 @@ unsigned int probe_irq_mask(unsigned lon mask = 0; for (i = 0; i < 16; i++) { - irq_desc_t *desc = irq_desc(i); + irq_desc_t *desc = irq_descp(i); unsigned int status; spin_lock_irq(&desc->lock); @@ -807,7 +807,7 @@ int probe_irq_off(unsigned long val) nr_irqs = 0; irq_found = 0; for (i = 0; i < NR_IRQS; i++) { - irq_desc_t *desc = irq_desc(i); + irq_desc_t *desc = irq_descp(i); unsigned int status; spin_lock_irq(&desc->lock); @@ -836,7 +836,7 @@ int setup_irq(unsigned int irq, struct i int shared = 0; unsigned long flags; struct irqaction *old, **p; - irq_desc_t *desc = irq_desc(irq); + irq_desc_t *desc = irq_descp(irq); if (desc->handler == &no_irq_type) return -ENOSYS; @@ -963,15 +963,16 @@ static int irq_affinity_read_proc (char } static int irq_affinity_write_proc (struct file *file, const char *buffer, - unsigned long count, void *data) + unsigned long count, void *data) { unsigned int irq = (unsigned long) data; int full_count = count, err; unsigned long new_value; const char *buf = buffer; + irq_desc_t *desc = irq_descp(irq); int redir; - if (!irq_desc(irq)->handler->set_affinity) + if (!desc->handler->set_affinity) return -EIO; if (buf[0] == 'r' || buf[0] == 'R') { @@ -993,8 +994,7 @@ static int irq_affinity_write_proc (stru if (!(new_value & cpu_online_map)) return -EINVAL; - irq_desc(irq)->handler->set_affinity(irq | (redir? IA64_IRQ_REDIRECTED : 0), new_value); - + desc->handler->set_affinity(irq | (redir? IA64_IRQ_REDIRECTED : 0), new_value); return full_count; } @@ -1030,7 +1030,7 @@ static void register_irq_proc (unsigned { char name [MAX_NAMELEN]; - if (!root_irq_dir || (irq_desc(irq)->handler == &no_irq_type) || irq_dir[irq]) + if (!root_irq_dir || (irq_descp(irq)->handler == &no_irq_type) || irq_dir[irq]) return; memset(name, 0, MAX_NAMELEN); @@ -1083,7 +1083,7 @@ void init_irq_proc (void) * Create entries for all existing IRQs. */ for (i = 0; i < NR_IRQS; i++) { - if (irq_desc(i)->handler == &no_irq_type) + if (irq_descp(i)->handler == &no_irq_type) continue; register_irq_proc(i); } --- linux-2.5.73/arch/ia64/kernel/irq_ia64.c 2003-06-14 12:18:07.000000000 -0700 +++ 25/arch/ia64/kernel/irq_ia64.c 2003-06-27 15:56:22.000000000 -0700 @@ -162,7 +162,7 @@ register_percpu_irq (ia64_vector vec, st for (irq = 0; irq < NR_IRQS; ++irq) if (irq_to_vector(irq) == vec) { - desc = irq_desc(irq); + desc = irq_descp(irq); desc->status |= IRQ_PER_CPU; desc->handler = &irq_type_ia64_lsapic; if (action) --- linux-2.5.73/arch/ia64/kernel/mca.c 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/kernel/mca.c 2003-06-27 15:56:22.000000000 -0700 @@ -734,7 +734,7 @@ ia64_mca_init(void) if (cpev >= 0) { for (irq = 0; irq < NR_IRQS; ++irq) if (irq_to_vector(irq) == cpev) { - desc = irq_desc(irq); + desc = irq_descp(irq); desc->status |= IRQ_PER_CPU; desc->handler = &irq_type_iosapic_level; setup_irq(irq, &mca_cpe_irqaction); --- linux-2.5.73/arch/ia64/kernel/perfmon.c 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/kernel/perfmon.c 2003-06-27 15:56:22.000000000 -0700 @@ -115,6 +115,8 @@ #define PMD_IS_COUNTING(i) ((pmu_conf.pmd_desc[i].type & PFM_REG_COUNTING) == PFM_REG_COUNTING) #define PMC_IS_COUNTING(i) ((pmu_conf.pmc_desc[i].type & PFM_REG_COUNTING) == PFM_REG_COUNTING) #define PMC_IS_MONITOR(i) ((pmu_conf.pmc_desc[i].type & PFM_REG_MONITOR) == PFM_REG_MONITOR) +#define PMC_IS_CONTROL(i) ((pmu_conf.pmc_desc[i].type & PFM_REG_CONTROL) == PFM_REG_CONTROL) + #define PMC_DFL_VAL(i) pmu_conf.pmc_desc[i].default_value #define PMC_RSVD_MASK(i) pmu_conf.pmc_desc[i].reserved_mask #define PMD_PMD_DEP(i) pmu_conf.pmd_desc[i].dep_pmd[0] @@ -232,6 +234,8 @@ */ #define PMC0_HAS_OVFL(cmp0) (cmp0 & ~0x1UL) +#define PFMFS_MAGIC 0xa0b4d889 + /* * debugging */ @@ -328,7 +332,7 @@ typedef struct pfm_context { pfm_counter_t ctx_pmds[IA64_NUM_PMD_REGS]; /* software state for PMDS */ - u64 ctx_saved_psr; /* copy of psr used for ctxsw */ + u64 ctx_saved_psr_up; /* only contains psr.up value */ unsigned long ctx_last_activation; /* context last activation number for last_cpu */ unsigned int ctx_last_cpu; /* CPU id of current or last CPU used (SMP only) */ @@ -560,100 +564,6 @@ static struct vm_operations_struct pfm_v close: pfm_vm_close }; -/* - * Linux 2.5 vs. 2.4 helper macros and definitions - * - * if not at least 2.5.69, then assume 2.4.x. - */ -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69) - -#define PFM_COMPILED_FOR_2_4 1 - -#include - -#define pfm_get_cpu_var(v) local_cpu_data->v -#define pfm_get_cpu_data(a,b) cpu_data((b))->a -typedef void pfm_irq_handler_t; -#define PFM_IRQ_HANDLER_RET(v) - -#define DEFINE_PER_CPU(a,b) - -static inline int -pfm_wait_task_inactive(struct task_struct *task) -{ -#ifdef CONFIG_SMP - /* Make sure the child gets off its CPU.. */ - for (;;) { - task_lock(task); - if (!task_has_cpu(task)) break; - task_unlock(task); - do { - if (task->state != TASK_STOPPED) - return -ESRCH; - barrier(); - cpu_relax(); - } while (task_has_cpu(task)); - } - task_unlock(task); -#endif - return 0; -} - -static inline void -pfm_put_task(struct task_struct *task) -{ - if (task != current) free_task_struct(task); -} - -static inline void -pfm_set_task_notify(struct task_struct *task) -{ -} - -static inline void -pfm_clear_task_notify(void) -{ -} - -static inline void -pfm_reserve_page(unsigned long a) -{ - unsigned long page; - - page = ia64_tpa(a); - mem_map_reserve(virt_to_page(__va(page))); -} - -static inline void -pfm_unreserve_page(unsigned long a) -{ - unsigned long page; - - page = ia64_tpa(a); - mem_map_unreserve(virt_to_page(__va(page))); -} - -static inline int -pfm_remap_page_range(struct vm_area_struct *vma, unsigned long from, unsigned long phys_addr, unsigned long size, pgprot_t prot) -{ - return remap_page_range(from, phys_addr, size, prot); -} - -static inline unsigned long -pfm_protect_ctx_ctxsw(pfm_context_t *x) -{ - unsigned long f; - spin_lock(&(x)->ctx_lock); - return f; -} - -static inline unsigned long -pfm_unprotect_ctx_ctxsw(pfm_context_t *x, unsigned long f) -{ - spin_unlock(&(x)->ctx_lock); -} - -#else /* 2.5.69 or higher */ #define pfm_wait_task_inactive(t) wait_task_inactive(t) #define pfm_get_cpu_var(v) __get_cpu_var(v) @@ -705,7 +615,7 @@ pfm_remap_page_range(struct vm_area_stru static inline unsigned long pfm_protect_ctx_ctxsw(pfm_context_t *x) { - spin_lock_irq(&(x)->ctx_lock); + spin_lock(&(x)->ctx_lock); return 0UL; } @@ -715,7 +625,30 @@ pfm_unprotect_ctx_ctxsw(pfm_context_t *x spin_unlock(&(x)->ctx_lock); } -#endif /* 2.5 vs. 2.4 */ +static inline unsigned int +pfm_do_munmap(struct mm_struct *mm, unsigned long addr, size_t len, int acct) +{ + return do_munmap(mm, addr, len); +} + +static inline unsigned long +pfm_get_unmapped_area(struct file *file, unsigned long addr, unsigned long len, unsigned long pgoff, unsigned long flags, unsigned long exec) +{ + return get_unmapped_area(file, addr, len, pgoff, flags); +} + + +static struct super_block * +pfmfs_get_sb(struct file_system_type *fs_type, int flags, const char *dev_name, void *data) +{ + return get_sb_pseudo(fs_type, "pfm:", NULL, PFMFS_MAGIC); +} + +static struct file_system_type pfm_fs_type = { + .name = "pfmfs", + .get_sb = pfmfs_get_sb, + .kill_sb = kill_anon_super, +}; DEFINE_PER_CPU(unsigned long, pfm_syst_info); DEFINE_PER_CPU(struct task_struct *, pmu_owner); @@ -758,13 +691,13 @@ pfm_set_psr_pp(void) static inline void pfm_clear_psr_up(void) { - __asm__ __volatile__ ("rum psr.up;; srlz.i;;"::: "memory"); + __asm__ __volatile__ ("rsm psr.up;; srlz.i;;"::: "memory"); } static inline void pfm_set_psr_up(void) { - __asm__ __volatile__ ("sum psr.up;; srlz.i;;"::: "memory"); + __asm__ __volatile__ ("ssm psr.up;; srlz.i;;"::: "memory"); } static inline unsigned long @@ -1502,7 +1435,7 @@ pfm_remove_smpl_mapping(struct task_stru DPRINT(("down_write done smpl_vaddr=%p size=%lu\n", vaddr, size)); - r = do_munmap(task->mm, (unsigned long)vaddr, size); + r = pfm_do_munmap(task->mm, (unsigned long)vaddr, size, 0); up_write(&task->mm->mmap_sem); if (r !=0) { @@ -1569,68 +1502,6 @@ pfm_exit_smpl_buffer(pfm_buffer_fmt_t *f * d_name - pfm: will go nicely and kill the special-casing in procfs. */ static struct vfsmount *pfmfs_mnt; -#define PFMFS_MAGIC 0xa0b4d889 - -#ifdef PFM_COMPILED_FOR_2_4 - -static int -pfmfs_statfs(struct super_block *sb, struct statfs *buf) -{ - buf->f_type = PFMFS_MAGIC; - buf->f_bsize = 1024; - buf->f_namelen = 255; - return 0; -} - -static struct super_operations pfmfs_ops = { - statfs: pfmfs_statfs, -}; - -static struct super_block * -pfmfs_read_super(struct super_block *sb, void *data, int silent) -{ - struct inode *root = new_inode(sb); - if (!root) - return NULL; - root->i_mode = S_IFDIR | S_IRUSR | S_IWUSR; - root->i_uid = root->i_gid = 0; - root->i_atime = root->i_mtime = root->i_ctime = CURRENT_TIME; - sb->s_blocksize = 1024; - sb->s_blocksize_bits = 10; - sb->s_magic = PFMFS_MAGIC; - sb->s_op = &pfmfs_ops; - sb->s_root = d_alloc(NULL, &(const struct qstr) { "pfm:", 4, 0 }); - if (!sb->s_root) { - iput(root); - return NULL; - } - sb->s_root->d_sb = sb; - sb->s_root->d_parent = sb->s_root; - d_instantiate(sb->s_root, root); - return sb; -} - -//static DECLARE_FSTYPE(pfm_fs_type, "pfmfs", pfmfs_read_super, FS_NOMOUNT); -static struct file_system_type pfm_fs_type = { - name: "pfmfs", - read_super: pfmfs_read_super, - fs_flags: FS_NOMOUNT, -}; - -#else /* ! COMPILED_FOR_2_4 */ - -static struct super_block * -pfmfs_get_sb(struct file_system_type *fs_type, int flags, char *dev_name, void *data) -{ - return get_sb_pseudo(fs_type, "pfm:", NULL, PFMFS_MAGIC); -} - -static struct file_system_type pfm_fs_type = { - .name = "pfmfs", - .get_sb = pfmfs_get_sb, - .kill_sb = kill_anon_super, -}; -#endif /* COMPILED_FOR_2_4 */ static int __init init_pfm_fs(void) @@ -2453,7 +2324,7 @@ pfm_smpl_buffer_alloc(struct task_struct down_write(&task->mm->mmap_sem); /* find some free area in address space, must have mmap sem held */ - vma->vm_start = get_unmapped_area(NULL, 0, size, 0, MAP_PRIVATE|MAP_ANONYMOUS); + vma->vm_start = pfm_get_unmapped_area(NULL, 0, size, 0, MAP_PRIVATE|MAP_ANONYMOUS, 0); if (vma->vm_start == 0UL) { DPRINT(("Cannot find unmapped area for size %ld\n", size)); up_write(&task->mm->mmap_sem); @@ -3020,7 +2891,7 @@ pfm_write_pmcs(pfm_context_t *ctx, void * as attempts to modify PMC[0-3] which are used * as status registers by the PMU */ - if (!PMC_IS_IMPL(cnum) || cnum < 4) { + if (PMC_IS_IMPL(cnum) == 0 || PMC_IS_CONTROL(cnum)) { DPRINT(("pmc%u is unimplemented or invalid\n", cnum)); goto error; } @@ -4124,7 +3995,7 @@ pfm_stop(pfm_context_t *ctx, void *arg, /* * monitoring disabled in kernel at next reschedule */ - ctx->ctx_saved_psr &= ~IA64_PSR_UP; + ctx->ctx_saved_psr_up = 0; printk("pfm_stop: current [%d] task=[%d]\n", current->pid, ctx->ctx_task->pid); } return 0; @@ -4198,7 +4069,7 @@ pfm_start(pfm_context_t *ctx, void *arg, * start monitoring at the kernel level the next * time the task is scheduled */ - ctx->ctx_saved_psr |= IA64_PSR_UP; + ctx->ctx_saved_psr_up = IA64_PSR_UP; /* * activate monitoring at user level @@ -4429,7 +4300,7 @@ pfm_context_load(pfm_context_t *ctx, voi SET_LAST_CPU(ctx, -1); /* initial saved psr (stopped) */ - ctx->ctx_saved_psr = pfm_get_psr() & ~(IA64_PSR_PP|IA64_PSR_UP); + ctx->ctx_saved_psr_up = 0UL; ia64_psr(regs)->up = ia64_psr(regs)->pp = 0; if (ctx->ctx_fl_unsecure) { @@ -5640,6 +5511,7 @@ pfm_save_regs(struct task_struct *task) unsigned long flags; u64 psr; + ctx = PFM_GET_CTX(task); if (ctx == NULL) goto save_error; t = &task->thread; @@ -5672,9 +5544,9 @@ pfm_save_regs(struct task_struct *task) * sanity check */ if (ctx->ctx_last_activation != GET_ACTIVATION()) { - DPRINT(("ctx_activation=%lu activation=%lu state=%d: no save\n", + printk("ctx_activation=%lu activation=%lu state=%d: no save\n", ctx->ctx_last_activation, - GET_ACTIVATION(), ctx->ctx_state)); + GET_ACTIVATION(), ctx->ctx_state); pfm_unprotect_ctx_ctxsw(ctx, flags); @@ -5684,8 +5556,11 @@ pfm_save_regs(struct task_struct *task) /* * save current PSR: needed because we modify it */ + ia64_srlz_d(); psr = pfm_get_psr(); + BUG_ON(psr & (IA64_PSR_I)); + /* * stop monitoring: * This is the last instruction which may generate an overflow @@ -5696,9 +5571,13 @@ pfm_save_regs(struct task_struct *task) pfm_clear_psr_up(); /* - * keep a copy of the saved psr (for reload) + * keep a copy of psr.up (for reload) */ - ctx->ctx_saved_psr = psr; + ctx->ctx_saved_psr_up = psr & IA64_PSR_UP; + + { u64 foo = pfm_get_psr(); + BUG_ON(foo & ((IA64_PSR_UP|IA64_PSR_PP))); + } /* * release ownership of this PMU. @@ -5772,18 +5651,16 @@ pfm_save_regs(struct task_struct *task) pfm_clear_psr_up(); /* - * keep a copy of the saved psr (for reload) + * keep a copy of psr.up (for reload) */ - ctx->ctx_saved_psr = psr; + ctx->ctx_saved_psr_up = psr & IA64_PSR_UP; - psr = pfm_get_psr(); - if (psr & IA64_PSR_UP) { - printk(KERN_ERR " perfmon: pfm_save_regs: psr.up set current [%d] owner [%d] psr=0x%lx\n", current->pid, GET_PMU_OWNER()->pid, psr); - } - if (psr & IA64_PSR_I) { - printk(KERN_ERR " perfmon: pfm_save_regs: psr.i set current [%d] owner [%d] psr=0x%lx\n", current->pid, GET_PMU_OWNER()->pid, psr); +#if 1 + { u64 foo = pfm_get_psr(); + BUG_ON(foo & (IA64_PSR_I)); + BUG_ON(foo & ((IA64_PSR_UP|IA64_PSR_PP))); } - +#endif return; save_error: printk(KERN_ERR "perfmon: pfm_save_regs CPU%d [%d] NULL context PM_VALID=%ld\n", @@ -5797,13 +5674,10 @@ pfm_lazy_save_regs (struct task_struct * pfm_context_t *ctx; struct thread_struct *t; unsigned long flags; - unsigned long psr; #if 1 - psr = pfm_get_psr(); - if (psr & IA64_PSR_UP) { - printk(KERN_ERR " perfmon: pfm_lazy_save_regs: psr.up set current [%d] owner [%d] psr=0x%lx\n", current->pid, task->pid, psr); - pfm_clear_psr_up(); + { u64 foo = pfm_get_psr(); + BUG_ON(foo & IA64_PSR_UP); } #endif @@ -5864,10 +5738,9 @@ pfm_load_regs (struct task_struct *task) { pfm_context_t *ctx; struct thread_struct *t; - struct task_struct *owner; unsigned long pmc_mask = 0UL, pmd_mask = 0UL; unsigned long flags; - u64 psr; + u64 psr, psr_up; ctx = PFM_GET_CTX(task); if (unlikely(ctx == NULL)) { @@ -5875,22 +5748,21 @@ pfm_load_regs (struct task_struct *task) return; } - owner = GET_PMU_OWNER(); + BUG_ON(GET_PMU_OWNER()); + t = &task->thread; + psr = pfm_get_psr(); #if 1 - psr = pfm_get_psr(); - BUG_ON(psr & IA64_PSR_UP); - psr = pfm_get_psr(); + BUG_ON(psr & (IA64_PSR_UP|IA64_PSR_PP)); BUG_ON(psr & IA64_PSR_I); #endif - /* * possible on unload */ if (unlikely((t->flags & IA64_THREAD_PM_VALID) == 0)) { - DPRINT(("[%d] PM_VALID=0, nothing to do\n", task->pid)); + printk("[%d] PM_VALID=0, nothing to do\n", task->pid); return; } @@ -5923,19 +5795,15 @@ pfm_load_regs (struct task_struct *task) /* * we restore ALL the debug registers to avoid picking up * stale state. - * - * This must be done even when the task is still the owner - * as the registers may have been modified via ptrace() - * (not perfmon) by the previous task. */ if (ctx->ctx_fl_using_dbreg) { pfm_restore_ibrs(ctx->ctx_ibrs, pmu_conf.num_ibrs); pfm_restore_dbrs(ctx->ctx_dbrs, pmu_conf.num_dbrs); } /* - * retrieve saved psr + * retrieve saved psr.up */ - psr = ctx->ctx_saved_psr; + psr_up = ctx->ctx_saved_psr_up; /* * if we were the last user of the PMU on that CPU, @@ -5968,8 +5836,8 @@ pfm_load_regs (struct task_struct *task) */ pmc_mask = ctx->ctx_all_pmcs[0]; - DPRINT(("full reload for [%d] owner=%d activation=%lu last_activation=%lu last_cpu=%d pmd_mask=0x%lx pmc_mask=0x%lx\n", - task->pid, owner ? owner->pid : -1, + DPRINT(("full reload for [%d] activation=%lu last_activation=%lu last_cpu=%d pmd_mask=0x%lx pmc_mask=0x%lx\n", + task->pid, GET_ACTIVATION(), ctx->ctx_last_activation, GET_LAST_CPU(ctx), pmd_mask, pmc_mask)); @@ -6026,9 +5894,9 @@ pfm_load_regs (struct task_struct *task) SET_PMU_OWNER(task, ctx); /* - * restore the psr we changed + * restore the psr.up bit */ - pfm_set_psr_l(psr); + if (likely(psr_up)) pfm_set_psr_up(); /* * allow concurrent access to context @@ -6047,21 +5915,16 @@ pfm_load_regs (struct task_struct *task) pfm_context_t *ctx; struct task_struct *owner; unsigned long pmd_mask, pmc_mask; - u64 psr; + u64 psr, psr_up; - owner = GET_PMU_OWNER(); - ctx = PFM_GET_CTX(task); - t = &task->thread; + owner = GET_PMU_OWNER(); + ctx = PFM_GET_CTX(task); + t = &task->thread; + psr = pfm_get_psr(); #if 1 - psr = pfm_get_psr(); - if (psr & IA64_PSR_UP) { - printk(KERN_ERR " perfmon: pfm_load_regs: psr.up set current [%d] owner [%d] psr=0x%lx\n", current->pid, owner->pid, psr); - } - psr = pfm_get_psr(); - if (psr & IA64_PSR_I) { - printk(KERN_ERR " perfmon: pfm_load_regs: psr.i set current [%d] owner [%d] psr=0x%lx\n", current->pid, owner->pid, psr); - } + BUG_ON(psr & (IA64_PSR_UP|IA64_PSR_PP)); + BUG_ON(psr & IA64_PSR_I); #endif /* @@ -6078,9 +5941,9 @@ pfm_load_regs (struct task_struct *task) } /* - * retrieved save psr + * retrieved saved psr.up */ - psr = ctx->ctx_saved_psr; + psr_up = ctx->ctx_saved_psr_up; /* * short path, our state is still there, just @@ -6091,7 +5954,7 @@ pfm_load_regs (struct task_struct *task) * concurrency even without interrupt masking. */ if (likely(owner == task)) { - pfm_set_psr_l(psr); + if (likely(psr_up)) pfm_set_psr_up(); return; } @@ -6163,8 +6026,7 @@ pfm_load_regs (struct task_struct *task) * restore the psr. This is the point at which * new overflow interrupts can be generated again. */ - pfm_set_psr_l(psr); - + if (likely(psr_up)) pfm_set_psr_up(); } #endif /* CONFIG_SMP */ @@ -6469,13 +6331,13 @@ dump_pmu_state(void) printk("pmd[%d]=0x%lx tpmd=0x%lx\n", i, ia64_get_pmd(i), t->pmds[i]); } if (ctx) { - printk("ctx_state=%d vaddr=%p addr=%p fd=%d ctx_task=[%d] saved_psr=0x%lx\n", + printk("ctx_state=%d vaddr=%p addr=%p fd=%d ctx_task=[%d] saved_psr_up=0x%lx\n", ctx->ctx_state, ctx->ctx_smpl_vaddr, ctx->ctx_smpl_hdr, ctx->ctx_msgq_head, ctx->ctx_msgq_tail, - ctx->ctx_saved_psr); + ctx->ctx_saved_psr_up); } } --- linux-2.5.73/arch/ia64/kernel/smpboot.c 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/kernel/smpboot.c 2003-06-27 15:56:22.000000000 -0700 @@ -452,7 +452,7 @@ smp_build_cpu_map (void) sapicid = smp_boot_data.cpu_phys_id[i]; if (sapicid == boot_cpu_id) continue; - phys_cpu_present_map |= (1 << cpu); + phys_cpu_present_map |= (1UL << cpu); ia64_cpu_to_sapicid[cpu] = sapicid; cpu++; } --- linux-2.5.73/arch/ia64/lib/Makefile 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/lib/Makefile 2003-06-27 15:56:22.000000000 -0700 @@ -12,12 +12,7 @@ lib-y := __divsi3.o __udivsi3.o __modsi3 lib-$(CONFIG_ITANIUM) += copy_page.o copy_user.o memcpy.o lib-$(CONFIG_MCKINLEY) += copy_page_mck.o memcpy_mck.o lib-$(CONFIG_PERFMON) += carta_random.o - -ifeq ($(CONFIG_MD_RAID5),m) - lib-y += xor.o -else - lib-$(CONFIG_MD_RAID5) += xor.o -endif +lib-$(CONFIG_MD_RAID5) += xor.o IGNORE_FLAGS_OBJS = __divsi3.o __udivsi3.o __modsi3.o __umodsi3.o \ __divdi3.o __udivdi3.o __moddi3.o __umoddi3.o --- linux-2.5.73/arch/ia64/Makefile 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/Makefile 2003-06-27 15:56:22.000000000 -0700 @@ -27,7 +27,7 @@ GCC_MINOR_VERSION=$(shell $(CC) -v 2>&1 GAS_STATUS=$(shell arch/ia64/scripts/check-gas $(CC) $(OBJDUMP)) -arch-cppflags := $(shell arch/ia64/scripts/toolchain-flags $(CC) $(LD) $(OBJDUMP)) +arch-cppflags := $(shell arch/ia64/scripts/toolchain-flags $(CC) $(OBJDUMP)) cflags-y += $(arch-cppflags) AFLAGS += $(arch-cppflags) @@ -66,7 +66,8 @@ core-$(CONFIG_IA64_SGI_SN2) += arch/ia64 drivers-$(CONFIG_PCI) += arch/ia64/pci/ drivers-$(CONFIG_IA64_HP_SIM) += arch/ia64/hp/sim/ drivers-$(CONFIG_IA64_HP_ZX1) += arch/ia64/hp/common/ arch/ia64/hp/zx1/ -drivers-$(CONFIG_IA64_GENERIC) += arch/ia64/hp/common/ arch/ia64/hp/zx1/ arch/ia64/hp/sim/ +drivers-$(CONFIG_IA64_GENERIC) += arch/ia64/hp/common/ arch/ia64/hp/zx1/ arch/ia64/hp/sim/ \ + arch/ia64/sn/ boot := arch/ia64/boot --- linux-2.5.73/arch/ia64/pci/pci.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/ia64/pci/pci.c 2003-06-27 15:56:22.000000000 -0700 @@ -53,21 +53,21 @@ struct pci_fixup pcibios_fixups[1]; * synchronization mechanism here. */ -#define PCI_SAL_ADDRESS(seg, bus, dev, fn, reg) \ +#define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \ ((u64)(seg << 24) | (u64)(bus << 16) | \ - (u64)(dev << 11) | (u64)(fn << 8) | (u64)(reg)) + (u64)(devfn << 8) | (u64)(reg)) static int -pci_sal_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) +pci_sal_read (int seg, int bus, int devfn, int reg, int len, u32 *value) { int result = 0; u64 data = 0; - if (!value || (seg > 255) || (bus > 255) || (dev > 31) || (fn > 7) || (reg > 255)) + if (!value || (seg > 255) || (bus > 255) || (devfn > 255) || (reg > 255)) return -EINVAL; - result = ia64_sal_pci_config_read(PCI_SAL_ADDRESS(seg, bus, dev, fn, reg), len, &data); + result = ia64_sal_pci_config_read(PCI_SAL_ADDRESS(seg, bus, devfn, reg), len, &data); *value = (u32) data; @@ -75,12 +75,12 @@ pci_sal_read (int seg, int bus, int dev, } static int -pci_sal_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) +pci_sal_write (int seg, int bus, int devfn, int reg, int len, u32 value) { - if ((seg > 255) || (bus > 255) || (dev > 31) || (fn > 7) || (reg > 255)) + if ((seg > 255) || (bus > 255) || (devfn > 255) || (reg > 255)) return -EINVAL; - return ia64_sal_pci_config_write(PCI_SAL_ADDRESS(seg, bus, dev, fn, reg), len, value); + return ia64_sal_pci_config_write(PCI_SAL_ADDRESS(seg, bus, devfn, reg), len, value); } struct pci_raw_ops pci_sal_ops = { @@ -95,14 +95,14 @@ static int pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) { return raw_pci_ops->read(pci_domain_nr(bus), bus->number, - PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, value); + devfn, where, size, value); } static int pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) { return raw_pci_ops->write(pci_domain_nr(bus), bus->number, - PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, value); + devfn, where, size, value); } static struct pci_ops pci_root_ops = { @@ -284,21 +284,21 @@ add_window (struct acpi_resource *res, v } struct pci_bus * -pcibios_scan_root (void *handle, int seg, int bus) +pci_acpi_scan_root (struct acpi_device *device, int domain, int bus) { struct pci_root_info info; struct pci_controller *controller; unsigned int windows = 0; char *name; - printk("PCI: Probing PCI hardware on bus (%02x:%02x)\n", seg, bus); - controller = alloc_pci_controller(seg); + printk("PCI: Probing PCI hardware on bus (%04x:%02x)\n", domain, bus); + controller = alloc_pci_controller(domain); if (!controller) goto out1; - controller->acpi_handle = handle; + controller->acpi_handle = device->handle; - acpi_walk_resources(handle, METHOD_NAME__CRS, count_window, &windows); + acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, &windows); controller->window = kmalloc(sizeof(*controller->window) * windows, GFP_KERNEL); if (!controller->window) goto out2; @@ -307,10 +307,10 @@ pcibios_scan_root (void *handle, int seg if (!name) goto out3; - sprintf(name, "PCI Bus %02x:%02x", seg, bus); + sprintf(name, "PCI Bus %04x:%02x", domain, bus); info.controller = controller; info.name = name; - acpi_walk_resources(handle, METHOD_NAME__CRS, add_window, &info); + acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window, &info); return scan_root_bus(bus, &pci_root_ops, controller); @@ -364,8 +364,6 @@ pcibios_fixup_bus (struct pci_bus *b) return; } -#warning pcibios_update_resource() is now a generic implementation - please check - void __devinit pcibios_update_irq (struct pci_dev *dev, int irq) { --- linux-2.5.73/arch/ia64/scripts/toolchain-flags 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/scripts/toolchain-flags 2003-06-27 15:56:22.000000000 -0700 @@ -3,15 +3,13 @@ # Check whether linker can handle cross-segment @segrel(): # CC=$1 -LD=$2 -OBJDUMP=$3 +OBJDUMP=$2 dir=$(dirname $0) tmp=${TMPDIR:-/tmp} out=$tmp/out$$ -$CC -c $dir/check-segrel.S -o $out.o -$LD -static -T$dir/check-segrel.lds $out.o -o $out +$CC -nostdlib -static -Wl,-T$dir/check-segrel.lds $dir/check-segrel.S -o $out res=$($OBJDUMP --full --section .rodata $out | fgrep 000 | cut -f3 -d' ') -rm -f $out $out.o +rm -f $out if [ $res != 00000a00 ]; then echo " -DHAVE_BUGGY_SEGREL" cat >&2 < -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SGI_IFCONFIG_NET "SGI-PERSISTENT NETWORK DEVICE NAME DRIVER" -#define SGI_IFCONFIG_NET_VERSION "1.0" - -/* - * Some Global definitions. - */ -static devfs_handle_t ifconfig_net_handle; -static unsigned long ifconfig_net_debug; - -/* - * ifconfig_net_open - Opens the special device node "/devhw/.ifconfig_net". - */ -static int ifconfig_net_open(struct inode * inode, struct file * filp) -{ - if (ifconfig_net_debug) { - printk("ifconfig_net_open called.\n"); - } - - return(0); - -} - -/* - * ifconfig_net_close - Closes the special device node "/devhw/.ifconfig_net". - */ -static int ifconfig_net_close(struct inode * inode, struct file * filp) -{ - - if (ifconfig_net_debug) { - printk("ifconfig_net_close called.\n"); - } - - return(0); -} - -/* - * assign_ifname - Assign the next available interface name from the persistent list. - */ -void -assign_ifname(struct net_device *dev, - struct ifname_num *ifname_num) - -{ - - /* - * Handle eth devices. - */ - if ( (memcmp(dev->name, "eth", 3) == 0) ) { - if (ifname_num->next_eth != -1) { - /* - * Assign it the next available eth interface number. - */ - memset(dev->name, 0, strlen(dev->name)); - sprintf(dev->name, "eth%d", (int)ifname_num->next_eth); - ifname_num->next_eth++; - } - - return; - } - - /* - * Handle fddi devices. - */ - if ( (memcmp(dev->name, "fddi", 4) == 0) ) { - if (ifname_num->next_fddi != -1) { - /* - * Assign it the next available fddi interface number. - */ - memset(dev->name, 0, strlen(dev->name)); - sprintf(dev->name, "fddi%d", (int)ifname_num->next_fddi); - ifname_num->next_fddi++; - } - - return; - } - - /* - * Handle hip devices. - */ - if ( (memcmp(dev->name, "hip", 3) == 0) ) { - if (ifname_num->next_hip != -1) { - /* - * Assign it the next available hip interface number. - */ - memset(dev->name, 0, strlen(dev->name)); - sprintf(dev->name, "hip%d", (int)ifname_num->next_hip); - ifname_num->next_hip++; - } - - return; - } - - /* - * Handle tr devices. - */ - if ( (memcmp(dev->name, "tr", 2) == 0) ) { - if (ifname_num->next_tr != -1) { - /* - * Assign it the next available tr interface number. - */ - memset(dev->name, 0, strlen(dev->name)); - sprintf(dev->name, "tr%d", (int)ifname_num->next_tr); - ifname_num->next_tr++; - } - - return; - } - - /* - * Handle fc devices. - */ - if ( (memcmp(dev->name, "fc", 2) == 0) ) { - if (ifname_num->next_fc != -1) { - /* - * Assign it the next available fc interface number. - */ - memset(dev->name, 0, strlen(dev->name)); - sprintf(dev->name, "fc%d", (int)ifname_num->next_fc); - ifname_num->next_fc++; - } - - return; - } -} - -/* - * find_persistent_ifname: Returns the entry that was seen in previous boot. - */ -struct ifname_MAC * -find_persistent_ifname(struct net_device *dev, - struct ifname_MAC *ifname_MAC) - -{ - - while (ifname_MAC->addr_len) { - if (memcmp(dev->dev_addr, ifname_MAC->dev_addr, dev->addr_len) == 0) - return(ifname_MAC); - - ifname_MAC++; - } - - return(NULL); -} - -/* - * ifconfig_net_ioctl: ifconfig_net driver ioctl interface. - */ -static int ifconfig_net_ioctl(struct inode * inode, struct file * file, - unsigned int cmd, unsigned long arg) -{ - - extern struct net_device *__dev_get_by_name(const char *); -#ifdef CONFIG_NET - struct net_device *dev; - struct ifname_MAC *found; - char temp[64]; -#endif - struct ifname_MAC *ifname_MAC; - struct ifname_MAC *new_devices, *temp_new_devices; - struct ifname_num *ifname_num; - unsigned long size; - - - if (ifconfig_net_debug) { - printk("HCL: hcl_ioctl called.\n"); - } - - /* - * Read in the header and see how big of a buffer we really need to - * allocate. - */ - ifname_num = (struct ifname_num *) kmalloc(sizeof(struct ifname_num), - GFP_KERNEL); - copy_from_user( ifname_num, (char *) arg, sizeof(struct ifname_num)); - size = ifname_num->size; - kfree(ifname_num); - ifname_num = (struct ifname_num *) kmalloc(size, GFP_KERNEL); - ifname_MAC = (struct ifname_MAC *) ((char *)ifname_num + (sizeof(struct ifname_num)) ); - - copy_from_user( ifname_num, (char *) arg, size); - new_devices = kmalloc(size - sizeof(struct ifname_num), GFP_KERNEL); - temp_new_devices = new_devices; - - memset(new_devices, 0, size - sizeof(struct ifname_num)); - -#ifdef CONFIG_NET - /* - * Go through the net device entries and make them persistent! - */ - for (dev = dev_base; dev != NULL; dev = dev->next) { - /* - * Skip NULL entries or "lo" - */ - if ( (dev->addr_len == 0) || ( !strncmp(dev->name, "lo", strlen(dev->name))) ){ - continue; - } - - /* - * See if we have a persistent interface name for this device. - */ - found = NULL; - found = find_persistent_ifname(dev, ifname_MAC); - if (found) { - strcpy(dev->name, found->name); - } else { - /* Never seen this before .. */ - assign_ifname(dev, ifname_num); - - /* - * Save the information for the next boot. - */ - sprintf(temp,"%s %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name, - dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], - dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); - strcpy(temp_new_devices->name, dev->name); - temp_new_devices->addr_len = dev->addr_len; - memcpy(temp_new_devices->dev_addr, dev->dev_addr, dev->addr_len); - temp_new_devices++; - } - - } -#endif - - /* - * Copy back to the User Buffer area any new devices encountered. - */ - copy_to_user((char *)arg + (sizeof(struct ifname_num)), new_devices, - size - sizeof(struct ifname_num)); - - return(0); - -} - -struct file_operations ifconfig_net_fops = { - ioctl:ifconfig_net_ioctl, /* ioctl */ - open:ifconfig_net_open, /* open */ - release:ifconfig_net_close /* release */ -}; - - -/* - * init_ifconfig_net() - Boot time initialization. Ensure that it is called - * after devfs has been initialized. - * - */ -#ifdef MODULE -int init_module (void) -#else -int __init init_ifconfig_net(void) -#endif -{ - ifconfig_net_handle = NULL; - ifconfig_net_handle = hwgraph_register(hwgraph_root, ".ifconfig_net", - 0, 0, - 0, 0, - S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0, - &ifconfig_net_fops, NULL); - - if (ifconfig_net_handle == NULL) { - panic("Unable to create SGI PERSISTENT NETWORK DEVICE Name Driver.\n"); - } - - return(0); - -} --- linux-2.5.73/arch/ia64/sn/io/drivers/Makefile 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/sn/io/drivers/Makefile 2003-06-27 15:56:22.000000000 -0700 @@ -9,4 +9,4 @@ EXTRA_CFLAGS := -DLITTLE_ENDIAN -obj-y += ioconfig_bus.o ifconfig_net.o +obj-y += ioconfig_bus.o --- linux-2.5.73/arch/ia64/sn/io/hwgfs/hcl.c 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/sn/io/hwgfs/hcl.c 2003-06-27 15:56:22.000000000 -0700 @@ -113,22 +113,10 @@ static int hcl_ioctl(struct inode * inod } struct file_operations hcl_fops = { - (struct module *)0, - NULL, /* lseek - default */ - NULL, /* read - general block-dev read */ - NULL, /* write - general block-dev write */ - NULL, /* readdir - bad */ - NULL, /* poll */ - hcl_ioctl, /* ioctl */ - NULL, /* mmap */ - hcl_open, /* open */ - NULL, /* flush */ - hcl_close, /* release */ - NULL, /* fsync */ - NULL, /* fasync */ - NULL, /* lock */ - NULL, /* readv */ - NULL, /* writev */ + .owner = (struct module *)0, + .ioctl = hcl_ioctl, + .open = hcl_open, + .release = hcl_close, }; @@ -140,7 +128,6 @@ int __init init_hcl(void) { extern void string_table_init(struct string_table *); extern struct string_table label_string_table; - extern int init_ifconfig_net(void); extern int init_ioconfig_bus(void); extern int init_hwgfs_fs(void); int rv = 0; @@ -195,7 +182,6 @@ int __init init_hcl(void) * Initialize the ifconfgi_net driver that does network devices * Persistent Naming. */ - init_ifconfig_net(); init_ioconfig_bus(); return(0); @@ -258,6 +244,7 @@ hwgraph_fastinfo_get(vertex_hdl_t de) if (!de) { printk(KERN_WARNING "HCL: hwgraph_fastinfo_get handle given is NULL.\n"); + dump_stack(); return(-1); } @@ -568,7 +555,7 @@ hwgraph_edge_add(vertex_hdl_t from, vert * In this case the vertex was previous created with a REAL pathname. */ rv = hwgfs_mk_symlink (from, (const char *)name, - DEVFS_FL_DEFAULT, link, + 0, link, &handle, NULL); kfree(path); kfree(link); --- linux-2.5.73/arch/ia64/sn/io/machvec/pci.c 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/sn/io/machvec/pci.c 2003-06-27 15:56:22.000000000 -0700 @@ -49,6 +49,8 @@ int sn_read_config(struct pci_bus *bus, vertex_hdl_t device_vertex; device_vertex = devfn_to_vertex(bus->number, devfn); + if (!device_vertex) + return PCIBIOS_DEVICE_NOT_FOUND; res = pciio_config_get(device_vertex, (unsigned) where, size); *val = (unsigned int) res; return PCIBIOS_SUCCESSFUL; @@ -59,6 +61,8 @@ int sn_write_config(struct pci_bus *bus, vertex_hdl_t device_vertex; device_vertex = devfn_to_vertex(bus->number, devfn); + if (!device_vertex) + return PCIBIOS_DEVICE_NOT_FOUND; pciio_config_set( device_vertex, (unsigned)where, size, (uint64_t) val); return PCIBIOS_SUCCESSFUL; } --- linux-2.5.73/arch/ia64/sn/io/machvec/pci_dma.c 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/sn/io/machvec/pci_dma.c 2003-06-27 15:56:22.000000000 -0700 @@ -280,7 +280,7 @@ sn_pci_map_sg(struct pci_dev *hwdev, str */ for (i = 0; i < nents; i++, sg++) { phys_addr = __pa(sg->dma_address ? sg->dma_address : - page_address(sg->page) + sg->offset); + (unsigned long)page_address(sg->page) + sg->offset); /* * Handle the most common case: 64 bit cards. This @@ -578,7 +578,7 @@ sn_dma_supported(struct device *dev, u64 { BUG_ON(dev->bus != &pci_bus_type); - return pci_dma_supported(to_pci_dev(dev), mask); + return sn_pci_dma_supported(to_pci_dev(dev), mask); } EXPORT_SYMBOL(sn_dma_supported); @@ -587,7 +587,11 @@ sn_dma_set_mask(struct device *dev, u64 { BUG_ON(dev->bus != &pci_bus_type); - return pci_set_dma_mask(to_pci_dev(dev), dma_mask); + if (!sn_dma_supported(dev, dma_mask)) + return 0; + + dev->dma_mask = dma_mask; + return 1; } EXPORT_SYMBOL(sn_dma_set_mask); @@ -597,7 +601,7 @@ sn_dma_alloc_coherent(struct device *dev { BUG_ON(dev->bus != &pci_bus_type); - return pci_alloc_consistent(to_pci_dev(dev), size, dma_handle); + return sn_pci_alloc_consistent(to_pci_dev(dev), size, dma_handle); } EXPORT_SYMBOL(sn_dma_alloc_coherent); @@ -607,7 +611,7 @@ sn_dma_free_coherent(struct device *dev, { BUG_ON(dev->bus != &pci_bus_type); - pci_free_consistent(to_pci_dev(dev), size, cpu_addr, dma_handle); + sn_pci_free_consistent(to_pci_dev(dev), size, cpu_addr, dma_handle); } EXPORT_SYMBOL(sn_dma_free_coherent); @@ -617,7 +621,7 @@ sn_dma_map_single(struct device *dev, vo { BUG_ON(dev->bus != &pci_bus_type); - return pci_map_single(to_pci_dev(dev), cpu_addr, size, (int)direction); + return sn_pci_map_single(to_pci_dev(dev), cpu_addr, size, (int)direction); } EXPORT_SYMBOL(sn_dma_map_single); @@ -627,7 +631,7 @@ sn_dma_unmap_single(struct device *dev, { BUG_ON(dev->bus != &pci_bus_type); - pci_unmap_single(to_pci_dev(dev), dma_addr, size, (int)direction); + sn_pci_unmap_single(to_pci_dev(dev), dma_addr, size, (int)direction); } EXPORT_SYMBOL(sn_dma_unmap_single); @@ -658,7 +662,7 @@ sn_dma_map_sg(struct device *dev, struct { BUG_ON(dev->bus != &pci_bus_type); - return pci_map_sg(to_pci_dev(dev), sg, nents, (int)direction); + return sn_pci_map_sg(to_pci_dev(dev), sg, nents, (int)direction); } EXPORT_SYMBOL(sn_dma_map_sg); @@ -668,7 +672,7 @@ sn_dma_unmap_sg(struct device *dev, stru { BUG_ON(dev->bus != &pci_bus_type); - pci_unmap_sg(to_pci_dev(dev), sg, nhwentries, (int)direction); + sn_pci_unmap_sg(to_pci_dev(dev), sg, nhwentries, (int)direction); } EXPORT_SYMBOL(sn_dma_unmap_sg); @@ -678,7 +682,7 @@ sn_dma_sync_single(struct device *dev, d { BUG_ON(dev->bus != &pci_bus_type); - pci_dma_sync_single(to_pci_dev(dev), dma_handle, size, (int)direction); + sn_pci_dma_sync_single(to_pci_dev(dev), dma_handle, size, (int)direction); } EXPORT_SYMBOL(sn_dma_sync_single); @@ -688,7 +692,7 @@ sn_dma_sync_sg(struct device *dev, struc { BUG_ON(dev->bus != &pci_bus_type); - pci_dma_sync_sg(to_pci_dev(dev), sg, nelems, (int)direction); + sn_pci_dma_sync_sg(to_pci_dev(dev), sg, nelems, (int)direction); } EXPORT_SYMBOL(sn_dma_sync_sg); --- linux-2.5.73/arch/ia64/sn/kernel/idle.c 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/sn/kernel/idle.c 2003-06-27 15:56:22.000000000 -0700 @@ -12,7 +12,7 @@ void snidle(int state) { if (state) { - if (pda.idle_flag == 0) { + if (pda->idle_flag == 0) { /* * Turn the activity LED off. */ @@ -24,13 +24,13 @@ void snidle(int state) { SIMULATOR_SLEEP(); #endif - pda.idle_flag = 1; + pda->idle_flag = 1; } else { /* * Turn the activity LED on. */ set_led_bits(LED_CPU_ACTIVITY, LED_CPU_ACTIVITY); - pda.idle_flag = 0; + pda->idle_flag = 0; } } --- linux-2.5.73/arch/ia64/sn/kernel/machvec.c 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/sn/kernel/machvec.c 2003-06-27 15:56:22.000000000 -0700 @@ -31,4 +31,5 @@ */ #define MACHVEC_PLATFORM_NAME sn2 +#define MACHVEC_PLATFORM_HEADER #include --- linux-2.5.73/arch/ia64/sn/kernel/Makefile 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/sn/kernel/Makefile 2003-06-27 15:56:22.000000000 -0700 @@ -9,7 +9,8 @@ EXTRA_CFLAGS := -DLITTLE_ENDIAN -obj-y := probe.o setup.o sv.o bte.o irq.o mca.o sn2/ +obj-y := probe.o setup.o sv.o bte.o irq.o mca.o \ + idle.o sn2/ obj-$(CONFIG_IA64_GENERIC) += machvec.o obj-$(CONFIG_MODULES) += sn_ksyms.o --- linux-2.5.73/arch/ia64/sn/kernel/setup.c 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/ia64/sn/kernel/setup.c 2003-06-27 15:56:22.000000000 -0700 @@ -75,11 +75,13 @@ DEFINE_PER_CPU(struct pda_s, pda_percpu) #define pxm_to_nasid(pxm) ((pxm)<<1) +#define MAX_PHYS_MEMORY (1UL << 49) /* 1 TB */ + extern void bte_init_node (nodepda_t *, cnodeid_t); extern void bte_init_cpu (void); -extern void sn_timer_init (void); +extern void sn_timer_init(void); extern void (*ia64_mark_idle)(int); -void snidle(int); +extern void snidle(int); unsigned long sn_rtc_cycles_per_second; @@ -296,21 +298,20 @@ sn_setup(char **cmdline_p) */ sn_check_for_wars(); + ia64_mark_idle = &snidle; + /* * For the bootcpu, we do this here. All other cpus will make the * call as part of cpu_init in slave cpu initialization. */ sn_cpu_init(); - #ifdef CONFIG_SMP init_smp_config(); #endif screen_info = sn_screen_info; sn_timer_init(); - - ia64_mark_idle = &snidle; } /** @@ -438,19 +439,3 @@ sn_cpu_init(void) bte_init_cpu(); } - -void snidle(int idleness) -{ - if (!idleness) { - if (pda->idle_flag == 0) { - set_led_bits(0, LED_CPU_ACTIVITY); - } - - pda->idle_flag = 1; - } - else { - set_led_bits(LED_CPU_ACTIVITY, LED_CPU_ACTIVITY); - - pda->idle_flag = 0; - } -} --- linux-2.5.73/arch/m68k/Kconfig 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/m68k/Kconfig 2003-06-27 15:56:22.000000000 -0700 @@ -585,33 +585,8 @@ source "drivers/input/Kconfig" source "drivers/ide/Kconfig" - -menu "SCSI device support" - -config SCSI - tristate "SCSI device support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - source "drivers/scsi/Kconfig" -endmenu - source "net/Kconfig" --- linux-2.5.73/arch/m68knommu/Kconfig 2003-06-22 12:04:43.000000000 -0700 +++ 25/arch/m68knommu/Kconfig 2003-06-27 15:56:22.000000000 -0700 @@ -499,6 +499,7 @@ config KCORE_AOUT default y config KCORE_ELF + bool default y source "fs/Kconfig.binfmt" @@ -527,60 +528,10 @@ source "drivers/block/Kconfig" source "drivers/ide/Kconfig" - -menu "SCSI device support" - -config SCSI - tristate "SCSI device support" - help - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - source "drivers/scsi/Kconfig" -endmenu - - -menu "Old CD-ROM drivers (not SCSI, not IDE)" - depends on ISA - -config CD_NO_IDESCSI - bool "Support non-SCSI/IDE/ATAPI CDROM drives" - ---help--- - If you have a CD-ROM drive that is neither SCSI nor IDE/ATAPI, say Y - here, otherwise N. Read the CD-ROM-HOWTO, available from - . - - Note that the answer to this question doesn't directly affect the - kernel: saying N will just cause the configurator to skip all - the questions about these CD-ROM drives. If you are unsure what you - have, say Y and find out whether you have one of the following - drives. - - For each of these drivers, a file Documentation/cdrom/{driver_name} - exists. Especially in cases where you do not know exactly which kind - of drive you have you should read there. Most of these drivers use a - file drivers/cdrom/{driver_name}.h where you can define your - interface parameters and switch some internal goodies. - - All these CD-ROM drivers are also usable as a module ( = code which - can be inserted in and removed from the running kernel whenever you - want). If you want to compile them as module, say M instead of Y and - read . - - If you want to use any of these CD-ROM drivers, you also have to - answer Y or M to "ISO 9660 CD-ROM file system support" below (this - answer will get "defaulted" for you if you enable any of the Linux - CD-ROM drivers). - source "drivers/cdrom/Kconfig" -endmenu - - source "drivers/md/Kconfig" source "drivers/message/fusion/Kconfig" --- linux-2.5.73/arch/m68knommu/kernel/time.c 2003-06-14 12:18:24.000000000 -0700 +++ 25/arch/m68knommu/kernel/time.c 2003-06-27 15:56:22.000000000 -0700 @@ -162,28 +162,33 @@ void do_gettimeofday(struct timeval *tv) tv->tv_usec = usec; } -void do_settimeofday(struct timeval *tv) +int do_settimeofday(struct timespec *tv) { + if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC) + return -EINVAL; + write_seqlock_irq(&xtime_lock); - /* This is revolting. We need to set the xtime.tv_usec + /* + * This is revolting. We need to set the xtime.tv_usec * correctly. However, the value in this location is * is value at the last tick. * Discover what correction gettimeofday * would have done, and then undo it! */ if (mach_gettimeoffset) - tv->tv_usec -= mach_gettimeoffset(); + tv->tv_nsec -= (mach_gettimeoffset() * 1000); - while (tv->tv_usec < 0) { - tv->tv_usec += 1000000; + while (tv->tv_nsec < 0) { + tv->tv_nsec += NSEC_PER_SEC; tv->tv_sec--; } xtime.tv_sec = tv->tv_sec; - xtime.tv_nsec = (tv->tv_usec * 1000); + xtime.tv_nsec = tv->tv_nsec; time_adjust = 0; /* stop active adjtime() */ time_status |= STA_UNSYNC; time_maxerror = NTP_PHASE_LIMIT; time_esterror = NTP_PHASE_LIMIT; write_sequnlock_irq(&xtime_lock); + return 0; } --- linux-2.5.73/arch/m68knommu/kernel/traps.c 2003-06-14 12:18:08.000000000 -0700 +++ 25/arch/m68knommu/kernel/traps.c 2003-06-27 15:56:22.000000000 -0700 @@ -82,7 +82,7 @@ void die_if_kernel(char *str, struct pt_ printk("Process %s (pid: %d, stackpage=%08lx)\n", current->comm, current->pid, PAGE_SIZE+(unsigned long)current); - show_stack((unsigned long *)fp); + show_stack(NULL, (unsigned long *)fp); do_exit(SIGSEGV); } @@ -106,7 +106,7 @@ asmlinkage void buserr_c(struct frame *f int kstack_depth_to_print = 48; -void show_stack(unsigned long *esp) +void show_stack(struct task_struct *task, unsigned long *esp) { unsigned long *stack, *endstack, addr; extern char _start, _etext; --- linux-2.5.73/arch/m68knommu/platform/5206e/MOTOROLA/crt0_ram.S 2003-06-14 12:18:04.000000000 -0700 +++ 25/arch/m68knommu/platform/5206e/MOTOROLA/crt0_ram.S 2003-06-27 15:56:22.000000000 -0700 @@ -96,6 +96,7 @@ _start: movec %d0, %CACR /* Enable cache */ +#ifdef CONFIG_ROMFS_FS /* * Move ROM filesystem above bss :-) */ @@ -117,6 +118,12 @@ _copy_romfs: cmp.l %a0, %a2 /* Check if at end */ bne _copy_romfs +#else /* CONFIG_ROMFS_FS */ + lea.l _ebss, %a1 + move.l %a1, _ramstart +#endif /* CONFIG_ROMFS_FS */ + + /* * Zero out the bss region. */ --- linux-2.5.73/arch/m68knommu/platform/5272/NETtel/crt0_ram.S 2003-06-14 12:18:30.000000000 -0700 +++ 25/arch/m68knommu/platform/5272/NETtel/crt0_ram.S 2003-06-27 15:56:22.000000000 -0700 @@ -116,6 +116,8 @@ _start: movec %d0, %CACR /* Enable cache */ nop + +#ifdef CONFIG_ROMFS_FS #ifdef CONFIG_ROMFS_FROM_ROM /* * check for an in RAM romfs @@ -160,6 +162,12 @@ _copy_romfs: done_romfs: #endif +#else /* CONFIG_ROMFS_FS */ + lea.l _ebss, %a1 + move.l %a1, _ramstart +#endif /* CONFIG_ROMFS_FS */ + + /* * Zero out the bss region. */ --- linux-2.5.73/arch/mips64/arc/arc_con.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,78 +0,0 @@ -/* - * Wrap-around code for a console using the - * ARC io-routines. - * - * Copyright (c) 1998 Harald Koerfgen - * Copyright (c) 2001 Ralf Baechle - */ -#include -#include -#include -#include -#include -#include - -#include - -extern void prom_printf (char *, ...); - -void prom_putchar(char c) -{ - ULONG cnt; - CHAR it = c; - - ArcWrite(1, &it, 1, &cnt); -} - -static void prom_console_write(struct console *co, const char *s, - unsigned count) -{ - unsigned i; - - /* - * Now, do each character - */ - for (i = 0; i < count; i++) { - if (*s == 10) - prom_printf("%c", 13); - prom_printf("%c", *s++); - } -} - -static int prom_console_wait_key(struct console *co) -{ - return 0; -} - -static int __init prom_console_setup(struct console *co, char *options) -{ - return 0; -} - -static kdev_t prom_console_device(struct console *c) -{ - return MKDEV(TTY_MAJOR, 64 + c->index); -} - -static struct console arc_cons = { - "ttyS", - prom_console_write, - NULL, - prom_console_device, - prom_console_wait_key, - NULL, - prom_console_setup, - CON_PRINTBUFFER, - -1, - 0, - NULL -}; - -/* - * Register console. - */ - -void __init arc_console_init(void) -{ - register_console(&arc_cons); -} --- linux-2.5.73/arch/mips64/arc/cmdline.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,111 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * cmdline.c: Kernel command line creation using ARCS argc/argv. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include -#include - -#include -#include - -/* #define DEBUG_CMDLINE */ - -char arcs_cmdline[CL_SIZE]; - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - -static char *ignored[] = { - "ConsoleIn=", - "ConsoleOut=", - "SystemPartition=", - "OSLoader=", - "OSLoadPartition=", - "OSLoadFilename=", - "OSLoadOptions=" -}; -#define NENTS(foo) ((sizeof((foo)) / (sizeof((foo[0]))))) - -static char *used_arc[][2] = { - { "OSLoadPartition=", "root=" }, - { "OSLoadOptions=", "" } -}; - -static char * __init move_firmware_args(char* cp) -{ - char *s; - int actr, i; - - actr = 1; /* Always ignore argv[0] */ - - while (actr < prom_argc) { - for(i = 0; i < NENTS(used_arc); i++) { - int len = strlen(used_arc[i][0]); - - if (!strncmp(prom_argv(actr), used_arc[i][0], len)) { - /* Ok, we want it. First append the replacement... */ - strcat(cp, used_arc[i][1]); - cp += strlen(used_arc[i][1]); - /* ... and now the argument */ - s = strstr(prom_argv(actr), "="); - if (s) { - s++; - strcpy(cp, s); - cp += strlen(s); - } - *cp++ = ' '; - break; - } - } - actr++; - } - - return cp; -} - - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr, i; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - /* - * Move ARC variables to the beginning to make sure they can be - * overridden by later arguments. - */ - cp = move_firmware_args(cp); - - while (actr < prom_argc) { - for (i = 0; i < NENTS(ignored); i++) { - int len = strlen(ignored[i]); - - if (!strncmp(prom_argv(actr), ignored[i], len)) - goto pic_cont; - } - /* Ok, we want it. */ - strcpy(cp, prom_argv(actr)); - cp += strlen(prom_argv(actr)); - *cp++ = ' '; - - pic_cont: - actr++; - } - if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ - --cp; - *cp = '\0'; - -#ifdef DEBUG_CMDLINE - prom_printf("prom_init_cmdline: %s\n", &(arcs_cmdline[0])); -#endif -} --- linux-2.5.73/arch/mips64/arc/console.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,33 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996 David S. Miller (dm@sgi.com) - */ -#include -#include -#include - -static char ppbuf[1024]; - -void prom_printf(char *fmt, ...) -{ - va_list args; - char ch, *bptr; - int i; - - va_start(args, fmt); - i = vsprintf(ppbuf, fmt, args); - - bptr = ppbuf; - - while((ch = *(bptr++)) != 0) { - if(ch == '\n') - prom_putchar('\r'); - - prom_putchar(ch); - } - va_end(args); - return; -} --- linux-2.5.73/arch/mips64/arc/env.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,27 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * env.c: ARCS environment variable routines. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include -#include - -#include -#include - -PCHAR __init -ArcGetEnvironmentVariable(CHAR *name) -{ - return (CHAR *) ARC_CALL1(get_evar, name); -} - -LONG __init -ArcSetEnvironmentVariable(PCHAR name, PCHAR value) -{ - return ARC_CALL2(set_evar, name, value); -} --- linux-2.5.73/arch/mips64/arc/file.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,75 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * ARC firmware interface. - * - * Copyright (C) 1994, 1995, 1996, 1999 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#include - -#include -#include - -LONG __init -ArcGetDirectoryEntry(ULONG FileID, struct linux_vdirent *Buffer, - ULONG N, ULONG *Count) -{ - return ARC_CALL4(get_vdirent, FileID, Buffer, N, Count); -} - -LONG __init -ArcOpen(CHAR *Path, enum linux_omode OpenMode, ULONG *FileID) -{ - return ARC_CALL3(open, Path, OpenMode, FileID); -} - -LONG __init -ArcClose(ULONG FileID) -{ - return ARC_CALL1(close, FileID); -} - -LONG __init -ArcRead(ULONG FileID, VOID *Buffer, ULONG N, ULONG *Count) -{ - return ARC_CALL4(read, FileID, Buffer, N, Count); -} - -LONG __init -ArcGetReadStatus(ULONG FileID) -{ - return ARC_CALL1(get_rstatus, FileID); -} - -LONG __init -ArcWrite(ULONG FileID, PVOID Buffer, ULONG N, PULONG Count) -{ - return ARC_CALL4(write, FileID, Buffer, N, Count); -} - -LONG __init -ArcSeek(ULONG FileID, struct linux_bigint *Position, enum linux_seekmode SeekMode) -{ - return ARC_CALL3(seek, FileID, Position, SeekMode); -} - -LONG __init -ArcMount(char *name, enum linux_mountops op) -{ - return ARC_CALL2(mount, name, op); -} - -LONG __init -ArcGetFileInformation(ULONG FileID, struct linux_finfo *Information) -{ - return ARC_CALL2(get_finfo, FileID, Information); -} - -LONG __init ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags, - ULONG AttributeMask) -{ - return ARC_CALL3(set_finfo, FileID, AttributeFlags, AttributeMask); -} --- linux-2.5.73/arch/mips64/arc/identify.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,79 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * identify.c: identify machine by looking up system identifier - * - * Copyright (C) 1998 Thomas Bogendoerfer - * - * This code is based on arch/mips/sgi/kernel/system.c, which is - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include -#include -#include -#include - -#include -#include - -struct smatch { - char *name; - int group; - int type; - int flags; -}; - -static struct smatch mach_table[] = { - { "SGI-IP22", MACH_GROUP_SGI, MACH_SGI_INDY, PROM_FLAG_ARCS }, - { "SGI-IP27", MACH_GROUP_SGI, MACH_SGI_IP27, PROM_FLAG_ARCS }, - { "Microsoft-Jazz", MACH_GROUP_JAZZ, MACH_MIPS_MAGNUM_4000, 0 }, - { "PICA-61", MACH_GROUP_JAZZ, MACH_ACER_PICA_61, 0 }, - { "RM200PCI", MACH_GROUP_SNI_RM, MACH_SNI_RM200_PCI, 0 } -}; - -int prom_flags; - -static struct smatch * __init -string_to_mach(const char *s) -{ - int i; - - for (i = 0; i < (sizeof (mach_table) / sizeof (mach_table[0])); i++) { - if(!strcmp(s, mach_table[i].name)) - return &mach_table[i]; - } - panic("\nYeee, could not determine architecture type <%s>", s); - - return NULL; -} - -void __init -prom_identify_arch(void) -{ - pcomponent *p; - struct smatch *mach; - const char *iname; - - /* The root component tells us what machine architecture we - have here. */ - p = ArcGetChild(PROM_NULL_COMPONENT); - if (p == NULL) { -#ifdef CONFIG_SGI_IP27 - /* IP27 PROM bisbehaves, seems to not implement ARC - GetChild(). So we just assume it's an IP27. */ - iname = "SGI-IP27"; -#endif - } else - iname = (char *) (long) p->iname; - - printk("ARCH: %s\n", iname); - mach = string_to_mach(iname); - - mips_machgroup = mach->group; - mips_machtype = mach->type; - prom_flags = mach->flags; -} --- linux-2.5.73/arch/mips64/arc/init.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,60 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * PROM library initialisation code. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include - -#include - -#undef DEBUG_PROM_INIT - -/* Master romvec interface. */ -struct linux_romvec *romvec; -PSYSTEM_PARAMETER_BLOCK sgi_pblock; -int prom_argc; -LONG *_prom_argv, *_prom_envp; -unsigned short prom_vers, prom_rev; - -extern void prom_testtree(void); - -int __init -prom_init(int argc, char **argv, char **envp) -{ - PSYSTEM_PARAMETER_BLOCK pb; - - romvec = ROMVECTOR; - pb = sgi_pblock = PROMBLOCK; - prom_argc = argc; - _prom_argv = (LONG *) argv; - _prom_envp = (LONG *) envp; - - if(pb->magic != 0x53435241) { - prom_printf("Aieee, bad prom vector magic %08lx\n", pb->magic); - while(1) - ; - } - - prom_init_cmdline(); - - prom_vers = pb->ver; - prom_rev = pb->rev; - prom_identify_arch(); - printk("PROMLIB: ARC firmware Version %d Revision %d\n", - prom_vers, prom_rev); - prom_meminit(); - -#ifdef DEBUG_PROM_INIT - { - prom_printf("Press a key to reboot\n"); - (void) prom_getchar(); - ArcEnterInteractiveMode(); - } -#endif - return 0; -} --- linux-2.5.73/arch/mips64/arc/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,9 +0,0 @@ -# -# Makefile for the ARC prom monitor library routines under Linux. -# - -lib-y := console.o init.o identify.o tree.o env.o cmdline.o misc.o time.o \ - file.o - -lib-$(CONFIG_ARC_MEMORY) += memory.o -lib-$(CONFIG_ARC_CONSOLE) += arc_con.o --- linux-2.5.73/arch/mips64/arc/memory.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,163 +0,0 @@ -/* - * memory.c: PROM library functions for acquiring/using memory descriptors - * given to us from the ARCS firmware. - * - * Copyright (C) 1996 by David S. Miller - * Copyright (C) 1999, 2000, 2001 by Ralf Baechle - * Copyright (C) 1999, 2000 by Silicon Graphics, Inc. - * - * PROM library functions for acquiring/using memory descriptors given to us - * from the ARCS firmware. This is only used when CONFIG_ARC_MEMORY is set - * because on some machines like SGI IP27 the ARC memory configuration data - * completly bogus and alternate easier to use mechanisms are available. - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#undef DEBUG - -struct linux_mdesc * __init -ArcGetMemoryDescriptor(struct linux_mdesc *Current) -{ - return (struct linux_mdesc *) ARC_CALL1(get_mdesc, Current); -} - -#ifdef DEBUG /* convenient for debugging */ -static char *arcs_mtypes[8] = { - "Exception Block", - "ARCS Romvec Page", - "Free/Contig RAM", - "Generic Free RAM", - "Bad Memory", - "Standalone Program Pages", - "ARCS Temp Storage Area", - "ARCS Permanent Storage Area" -}; - -static char *arc_mtypes[8] = { - "Exception Block", - "SystemParameterBlock", - "FreeMemory", - "Bad Memory", - "LoadedProgram", - "FirmwareTemporary", - "FirmwarePermanent", - "FreeContiguous" -}; -#define mtypes(a) (prom_flags & PROM_FLAG_ARCS) ? arcs_mtypes[a.arcs] \ - : arc_mtypes[a.arc] -#endif - -static inline int memtype_classify_arcs (union linux_memtypes type) -{ - switch (type.arcs) { - case arcs_fcontig: - case arcs_free: - return BOOT_MEM_RAM; - case arcs_atmp: - return BOOT_MEM_ROM_DATA; - case arcs_eblock: - case arcs_rvpage: - case arcs_bmem: - case arcs_prog: - case arcs_aperm: - return BOOT_MEM_RESERVED; - default: - BUG(); - } - while(1); /* Nuke warning. */ -} - -static inline int memtype_classify_arc (union linux_memtypes type) -{ - switch (type.arc) { - case arc_free: - case arc_fcontig: - return BOOT_MEM_RAM; - case arc_atmp: - return BOOT_MEM_ROM_DATA; - case arc_eblock: - case arc_rvpage: - case arc_bmem: - case arc_prog: - case arc_aperm: - return BOOT_MEM_RESERVED; - default: - BUG(); - } - while(1); /* Nuke warning. */ -} - -static int __init prom_memtype_classify (union linux_memtypes type) -{ - if (prom_flags & PROM_FLAG_ARCS) /* SGI is ``different'' ... */ - return memtype_classify_arcs(type); - - return memtype_classify_arc(type); -} - -void __init prom_meminit(void) -{ - struct linux_mdesc *p; - -#ifdef DEBUG - int i = 0; - - prom_printf("ARCS MEMORY DESCRIPTOR dump:\n"); - i=0; - prom_printf ("i=%d\n", i); - p = ArcGetMemoryDescriptor(PROM_NULL_MDESC); - prom_printf ("i=%d\n", i); - while(p) { - prom_printf("[%d,%p]: base<%08lx> pages<%08lx> type<%s>\n", - i, p, p->base, p->pages, mtypes(p->type)); - p = ArcGetMemoryDescriptor(p); - i++; - } -#endif - - p = PROM_NULL_MDESC; - while ((p = ArcGetMemoryDescriptor(p))) { - unsigned long base, size; - long type; - - base = p->base << PAGE_SHIFT; - size = p->pages << PAGE_SHIFT; - type = prom_memtype_classify(p->type); - - add_memory_region(base, size, type); - } -} - -void __init prom_free_prom_memory (void) -{ - unsigned long freed = 0; - unsigned long addr; - int i; - - for (i = 0; i < boot_mem_map.nr_map; i++) { - if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) - continue; - - addr = boot_mem_map.map[i].addr; - while (addr < boot_mem_map.map[i].addr - + boot_mem_map.map[i].size) { - ClearPageReserved(virt_to_page(__va(addr))); - set_page_count(virt_to_page(__va(addr)), 1); - free_page((unsigned long)__va(addr)); - addr += PAGE_SIZE; - freed += PAGE_SIZE; - } - } - printk(KERN_INFO "Freeing prom memory: %ldkb freed\n", freed >> 10); -} --- linux-2.5.73/arch/mips64/arc/misc.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,104 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Miscellaneous ARCS PROM routines. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#include -#include -#include - -#include - -#include -#include -#include -#include - -extern unsigned long mips_cputype; -extern void *sgiwd93_host; -extern void reset_wd33c93(void *instance); - -VOID -ArcHalt(VOID) -{ - bc_disable(); - cli(); -#ifdef CONFIG_SCSI_SGIWD93 - reset_wd33c93(sgiwd93_host); -#endif - ARC_CALL0(halt); -never: goto never; -} - -VOID -ArcPowerDown(VOID) -{ - bc_disable(); - cli(); -#ifdef CONFIG_SCSI_SGIWD93 - reset_wd33c93(sgiwd93_host); -#endif - ARC_CALL0(pdown); -never: goto never; -} - -/* XXX is this a soft reset basically? XXX */ -VOID -ArcRestart(VOID) -{ - bc_disable(); - cli(); -#ifdef CONFIG_SCSI_SGIWD93 - reset_wd33c93(sgiwd93_host); -#endif - ARC_CALL0(restart); -never: goto never; -} - -VOID -ArcReboot(VOID) -{ - bc_disable(); - cli(); -#ifdef CONFIG_SCSI_SGIWD93 - reset_wd33c93(sgiwd93_host); -#endif - ARC_CALL0(reboot); -never: goto never; -} - -VOID -ArcEnterInteractiveMode(VOID) -{ - bc_disable(); - cli(); -#ifdef CONFIG_SCSI_SGIWD93 - reset_wd33c93(sgiwd93_host); -#endif - ARC_CALL0(imode); -never: goto never; -} - -LONG -ArcSaveConfiguration(VOID) -{ - return ARC_CALL0(cfg_save); -} - -struct linux_sysid * -ArcGetSystemId(VOID) -{ - return (struct linux_sysid *) ARC_CALL0(get_sysid); -} - -VOID __init -ArcFlushAllCaches(VOID) -{ - ARC_CALL0(cache_flush); -} --- linux-2.5.73/arch/mips64/arc/salone.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,27 +0,0 @@ -/* - * Routines to load into memory and execute stand-along program images using - * ARCS PROM firmware. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include - -LONG __init -ArcLoad(CHAR *Path, ULONG TopAddr, ULONG *ExecAddr, ULONG *LowAddr) -{ - return ARC_CALL4(load, Path, TopAddr, ExecAddr, LowAddr); -} - -LONG __init -ArcInvoke(ULONG ExecAddr, ULONG StackAddr, ULONG Argc, CHAR *Argv[], - CHAR *Envp[]) -{ - return ARC_CALL5(invoke, ExecAddr, StackAddr, Argc, Argv, Envp); -} - -LONG __init -ArcExecute(CHAR *Path, LONG Argc, CHAR *Argv[], CHAR *Envp[]) -{ - return ARC_CALL4(exec, Path, Argc, Argv, Envp); -} --- linux-2.5.73/arch/mips64/arc/time.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Extracting time information from ARCS prom. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include - -#include -#include - -struct linux_tinfo * __init -ArcGetTime(VOID) -{ - return (struct linux_tinfo *) ARC_CALL0(get_tinfo); -} - -ULONG __init -ArcGetRelativeTime(VOID) -{ - return ARC_CALL0(get_rtime); -} --- linux-2.5.73/arch/mips64/arc/tree.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,127 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * PROM component device tree code. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#include -#include -#include - -#undef DEBUG_PROM_TREE - -pcomponent * __init -ArcGetPeer(pcomponent *Current) -{ - if (Current == PROM_NULL_COMPONENT) - return PROM_NULL_COMPONENT; - - return (pcomponent *) ARC_CALL1(next_component, Current); -} - -pcomponent * __init -ArcGetChild(pcomponent *Current) -{ - return (pcomponent *) ARC_CALL1(child_component, Current); -} - -pcomponent * __init -ArcGetParent(pcomponent *Current) -{ - if (Current == PROM_NULL_COMPONENT) - return PROM_NULL_COMPONENT; - - return (pcomponent *) ARC_CALL1(parent_component, Current); -} - -LONG __init -ArcGetConfigurationData(VOID *Buffer, pcomponent *Current) -{ - return ARC_CALL2(component_data, Buffer, Current); -} - -pcomponent * __init -ArcAddChild(pcomponent *Current, pcomponent *Template, VOID *ConfigurationData) -{ - return (pcomponent *) - ARC_CALL3(child_add, Current, Template, ConfigurationData); -} - -LONG __init -ArcDeleteComponent(pcomponent *ComponentToDelete) -{ - return ARC_CALL1(comp_del, ComponentToDelete); -} - -pcomponent * __init -ArcGetComponent(CHAR *Path) -{ - return (pcomponent *)ARC_CALL1(component_by_path, Path); -} - -#ifdef DEBUG_PROM_TREE - -static char *classes[] = { - "system", "processor", "cache", "adapter", "controller", "peripheral", - "memory" -}; - -static char *types[] = { - "arc", "cpu", "fpu", "picache", "pdcache", "sicache", "sdcache", - "sccache", "memdev", "eisa adapter", "tc adapter", "scsi adapter", - "dti adapter", "multi-func adapter", "disk controller", - "tp controller", "cdrom controller", "worm controller", - "serial controller", "net controller", "display controller", - "parallel controller", "pointer controller", "keyboard controller", - "audio controller", "misc controller", "disk peripheral", - "floppy peripheral", "tp peripheral", "modem peripheral", - "monitor peripheral", "printer peripheral", "pointer peripheral", - "keyboard peripheral", "terminal peripheral", "line peripheral", - "net peripheral", "misc peripheral", "anonymous" -}; - -static char *iflags[] = { - "bogus", "read only", "removable", "console in", "console out", - "input", "output" -}; - -static void __init -dump_component(pcomponent *p) -{ - prom_printf("[%p]:class<%s>type<%s>flags<%s>ver<%d>rev<%d>", - p, classes[p->class], types[p->type], - iflags[p->iflags], p->vers, p->rev); - prom_printf("key<%08lx>\n\tamask<%08lx>cdsize<%d>ilen<%d>iname<%s>\n", - p->key, p->amask, (int)p->cdsize, (int)p->ilen, p->iname); -} - -static void __init -traverse(pcomponent *p, int op) -{ - dump_component(p); - if(ArcGetChild(p)) - traverse(ArcGetChild(p), 1); - if(ArcGetPeer(p) && op) - traverse(ArcGetPeer(p), 1); -} - -void __init -prom_testtree(void) -{ - pcomponent *p; - - p = ArcGetChild(PROM_NULL_COMPONENT); - dump_component(p); - p = ArcGetChild(p); - while(p) { - dump_component(p); - p = ArcGetPeer(p); - } -} - -#endif /* DEBUG_PROM_TREE */ --- linux-2.5.73/arch/mips64/boot/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/boot/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -15,16 +15,30 @@ else E2EFLAGS = endif +# +# Drop some uninteresting sections in the kernel. +# This is only relevant for ELF kernels but doesn't hurt a.out +# +drop-sections = .reginfo .mdebug .comment .note +strip-flags = $(addprefix --remove-section=,$(drop-sections)) + all: vmlinux.ecoff addinitrd +vmlinux.rm200: vmlinux + $(OBJCOPY) \ + --change-addresses=0xfffffffc \ + -O elf32-littlemips \ + $(strip-flags) \ + $< $@ + vmlinux.ecoff: elf2ecoff $(TOPDIR)/vmlinux ./elf2ecoff $(TOPDIR)/vmlinux vmlinux.ecoff $(E2EFLAGS) -elf2ecoff: elf2ecoff.c - $(HOSTCC) -o $@ $^ +elf2ecoff: $(TOPDIR)/arch/mips/boot/elf2ecoff.c + $(HOSTCC) -I$(TOPDIR)/arch/mips/boot -I- -o $@ $^ -addinitrd: addinitrd.c - $(HOSTCC) -o $@ $^ +addinitrd: $(TOPDIR)/arch/mips/boot/addinitrd.c + $(HOSTCC) -I$(TOPDIR)/arch/mips/boot -I- -o $@ $^ clean: rm -f vmlinux.ecoff --- linux-2.5.73/arch/mips64/defconfig 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/defconfig 2003-06-27 15:56:23.000000000 -0700 @@ -1,71 +1,133 @@ # # Automatically generated make config: don't edit # +CONFIG_MIPS=y +# CONFIG_MIPS32 is not set +CONFIG_MIPS64=y # # Code maturity level options # -# CONFIG_EXPERIMENTAL is not set +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=15 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set # # Machine selection # +# CONFIG_ACER_PICA_61 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set CONFIG_SGI_IP27=y # CONFIG_SGI_SN0_N_MODE is not set -CONFIG_DISCONTIGMEM=y -CONFIG_NUMA=y +# CONFIG_DISCONTIGMEM is not set +# CONFIG_NUMA is not set # CONFIG_MAPPED_KERNEL is not set # CONFIG_REPLICATE_KTEXT is not set # CONFIG_REPLICATE_EXHANDLERS is not set -CONFIG_SMP=y +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_BOOT_ELF64=y +CONFIG_ARC=y +CONFIG_GENERIC_ISA_DMA=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_L1_CACHE_SHIFT=7 +# CONFIG_FB is not set CONFIG_ARC64=y -CONFIG_COHERENT_IO=y -CONFIG_MAPPED_PCI_IO=y -CONFIG_PCI=y +CONFIG_BOOT_ELF64=y CONFIG_QL_ISP_A64=y -CONFIG_L1_CACHE_SHIFT=7 -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_NR_CPUS=64 # # CPU selection # +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set CONFIG_CPU_R10000=y +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_MIPS_INSANE_LARGE is not set # -# General setup +# Bus options (PCI, PCMCIA, EISA, ISA, TC) # -# CONFIG_MIPS_INSANE_LARGE is not set -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_NET=y +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y CONFIG_PCI_NAMES=y +CONFIG_MMU=y # CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_BINFMT_ELF=y -CONFIG_MIPS32_COMPAT=y -CONFIG_BINFMT_ELF32=y -# CONFIG_BINFMT_MISC is not set # -# Loadable module support +# Executable file formats # -# CONFIG_MODULES is not set -CONFIG_PCI_NAMES=y +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_MIPS32_O32=y +# CONFIG_MIPS32_N32 is not set +CONFIG_BINFMT_ELF32=y # # Memory Technology Devices (MTD) @@ -78,83 +140,35 @@ CONFIG_PCI_NAMES=y # CONFIG_PARPORT is not set # +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_NETLINK=y -CONFIG_RTNETLINK=y -CONFIG_NETLINK_DEV=y -# CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_INET_ECN is not set -# CONFIG_SYN_COOKIES is not set - -# -# -# -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set -# CONFIG_PHONE_IXJ is not set -# CONFIG_PHONE_IXJ_PCMCIA is not set - -# -# ATA/IDE/MFM/RLL support +# ATA/ATAPI/MFM/RLL support # # CONFIG_IDE is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_HD is not set # -# SCSI support +# SCSI device support # CONFIG_SCSI=y @@ -162,7 +176,6 @@ CONFIG_SCSI=y # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 CONFIG_CHR_DEV_ST=y # CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set @@ -171,8 +184,8 @@ CONFIG_CHR_DEV_ST=y # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs # -# CONFIG_SCSI_DEBUG_QUEUES is not set # CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_REPORT_LUNS is not set CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y @@ -180,52 +193,116 @@ CONFIG_SCSI_LOGGING=y # SCSI low-level drivers # # CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set # CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set +# CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set # CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set # CONFIG_SCSI_MEGARAID is not set # CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_CPQFCTS is not set # CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set # CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set # CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR_D700 is not set -# CONFIG_SCSI_NCR53C7xx is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_NCR53C8XX is not set # CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set # CONFIG_SCSI_PCI2000 is not set # CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -CONFIG_SCSI_QLOGIC_ISP=y +# CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set +# CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set # -# Network device support +# IEEE 1394 (FireWire) support (EXPERIMENTAL) # +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set CONFIG_NETDEVICES=y # @@ -236,39 +313,44 @@ CONFIG_NETDEVICES=y # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set CONFIG_SGI_IOC3_ETH=y -# CONFIG_SUNLANCE is not set # CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set # CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set # # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set # CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set +# CONFIG_E1000 is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set # CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set # CONFIG_FDDI is not set -# CONFIG_PLIP is not set +# CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -278,10 +360,11 @@ CONFIG_SGI_IOC3_ETH=y # CONFIG_NET_RADIO is not set # -# Token Ring devices +# Token Ring devices (depends on LLC=y) # -# CONFIG_TR is not set # CONFIG_NET_FC is not set +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set # # Wan interfaces @@ -301,21 +384,69 @@ CONFIG_SGI_IOC3_ETH=y # # ISDN subsystem # -# CONFIG_ISDN is not set +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set # -# Old CD-ROM drivers (not SCSI, not IDE) +# Input Device Drivers # -# CONFIG_CD_NO_IDESCSI is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Character devices # # CONFIG_VT is not set -CONFIG_SERIAL=y -CONFIG_SERIAL_CONSOLE=y -# CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_CONSOLE is not set +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_MULTIPORT is not set +# CONFIG_SERIAL_8250_RSA is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 @@ -325,32 +456,33 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_I2C is not set # -# Mice +# I2C Hardware Sensors Mainboard support # -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set # -# Joysticks +# I2C Hardware Sensors Chip support # -# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_I2C_SENSOR is not set # -# Input core support is needed for gameports +# Mice # +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set # -# Input core support is needed for joysticks +# IPMI # -# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +CONFIG_SGI_IP27_RTC=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set @@ -361,6 +493,8 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set # # Multimedia devices @@ -368,79 +502,92 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_VIDEO_DEV is not set # +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# # File systems # +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_JBD=y +CONFIG_JBD_DEBUG=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set CONFIG_AUTOFS_FS=y # CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set -# CONFIG_CMS_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_JBD_DEBUG is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_TMPFS is not set -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_FREEVXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set +# CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set # # Network File Systems # -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y +# CONFIG_NFS_V4 is not set # CONFIG_NFSD is not set -# CONFIG_NFSD_V3 is not set -CONFIG_SUNRPC=y +CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set # CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set # CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types @@ -457,12 +604,15 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_LDM_PARTITION is not set +# CONFIG_NEC98_PARTITION is not set CONFIG_SGI_PARTITION=y # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set -CONFIG_KCORE_ELF=y +# CONFIG_EFI_PARTITION is not set + +# +# Graphics support +# # # Sound @@ -473,113 +623,30 @@ CONFIG_KCORE_ELF=y # USB support # # CONFIG_USB is not set +# CONFIG_USB_GADGET is not set # -# USB Controllers +# Bluetooth support # -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set +# CONFIG_BT is not set # -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# -# CONFIG_USB_DABUSB is not set - -# -# USB Network adaptors -# -# CONFIG_USB_PLUSB is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support +# Kernel hacking # -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_OMNINET is not set +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set # -# Miscellaneous USB drivers +# Security options # -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_ID75 is not set +# CONFIG_SECURITY is not set # -# Input core support +# Cryptographic options # -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set +# CONFIG_CRYPTO is not set # -# Kernel hacking +# Library routines # -CONFIG_CROSSCOMPILE=y -# CONFIG_REMOTE_DEBUG is not set -# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_CRC32 is not set --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/defconfig-atlas 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,547 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +# CONFIG_MIPS32 is not set +CONFIG_MIPS64=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +CONFIG_MIPS_ATLAS=y +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_NONCOHERENT_IO=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_MIPS_BOARDS_GEN=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_L1_CACHE_SHIFT=5 +# CONFIG_FB is not set + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +CONFIG_CPU_R5000=y +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_PCI is not set +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_MIPS32_O32=y +# CONFIG_MIPS32_N32 is not set +CONFIG_BINFMT_ELF32=y + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_REPORT_LUNS is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI low-level drivers +# +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_EATA_PIO is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +CONFIG_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +CONFIG_EFS_FS=y +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/defconfig-decstation 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,573 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +# CONFIG_MIPS32 is not set +CONFIG_MIPS64=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +CONFIG_DECSTATION=y +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_BOOT_ELF32=y +CONFIG_L1_CACHE_SHIFT=4 +# CONFIG_FB is not set + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +CONFIG_CPU_R4X00=y +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_TC=y +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_MIPS32_O32=y +# CONFIG_MIPS32_N32 is not set +CONFIG_BINFMT_ELF32=y + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_REPORT_LUNS is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI low-level drivers +# +CONFIG_SCSI_DECNCR=y +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_EATA_PIO is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +# CONFIG_NETLINK_DEV is not set +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +CONFIG_DECLANCE=y + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_CT82C710 is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_COMPUTONE is not set +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_DIGIEPCA is not set +# CONFIG_DIGI is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_SYNCLINK is not set +# CONFIG_SYNCLINKMP is not set +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_SX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_DZ=y +CONFIG_SERIAL_DZ_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_EXPORTFS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_OSF_PARTITION=y +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_NEC98_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +CONFIG_ULTRIX_PARTITION=y +# CONFIG_SUN_PARTITION is not set +# CONFIG_EFI_PARTITION is not set + +# +# Graphics support +# + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set --- linux-2.5.73/arch/mips64/defconfig-ip22 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/defconfig-ip22 2003-06-27 15:56:23.000000000 -0700 @@ -1,6 +1,9 @@ # # Automatically generated make config: don't edit # +CONFIG_MIPS=y +# CONFIG_MIPS32 is not set +CONFIG_MIPS64=y # # Code maturity level options @@ -8,57 +11,122 @@ CONFIG_EXPERIMENTAL=y # +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# # Machine selection # +# CONFIG_ACER_PICA_61 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set CONFIG_SGI_IP22=y # CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +CONFIG_ARC=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_NONCOHERENT_IO=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_IRQ_CPU=y +CONFIG_SWAP_IO_SPACE=y CONFIG_BOOT_ELF32=y +CONFIG_L1_CACHE_SHIFT=5 CONFIG_ARC32=y +# CONFIG_FB is not set +CONFIG_ARC_CONSOLE=y +CONFIG_ARC_PROMLIB=y CONFIG_BOARD_SCACHE=y -CONFIG_ARC_MEMORY=y -CONFIG_SGI=y -CONFIG_L1_CACHE_SHIFT=5 -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_PCI is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set # # CPU selection # +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set CONFIG_CPU_R5000=y +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set # -# General setup +# Bus options (PCI, PCMCIA, EISA, ISA, TC) # -# CONFIG_CPU_LITTLE_ENDIAN is not set -# CONFIG_MIPS_FPU_EMULATOR is not set -CONFIG_NET=y +# CONFIG_ISA is not set +CONFIG_MMU=y # CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_ARC_CONSOLE is not set -CONFIG_BINFMT_ELF=y -CONFIG_MIPS32_COMPAT=y -CONFIG_BINFMT_ELF32=y -# CONFIG_BINFMT_MISC is not set # -# Loadable module support +# Executable file formats # -CONFIG_MODULES=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_MIPS32_O32=y +CONFIG_MIPS32_N32=y +CONFIG_BINFMT_ELF32=y # # Memory Technology Devices (MTD) @@ -71,41 +139,90 @@ CONFIG_KMOD=y # CONFIG_PARPORT is not set # +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=y +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +# CONFIG_CHR_DEV_SG is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_REPORT_LUNS is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI low-level drivers +# +CONFIG_SGIWD93_SCSI=y +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_EATA_PIO is not set +# CONFIG_SCSI_DEBUG is not set + +# # Multi-device support (RAID and LVM) # # CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_BLK_DEV_LVM is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y # # Networking options # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK=y -CONFIG_RTNETLINK=y CONFIG_NETLINK_DEV=y # CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set CONFIG_UNIX=y +CONFIG_NET_KEY=y CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set @@ -119,20 +236,24 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_ARPD is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set # CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set +# CONFIG_XFRM_USER is not set # -# +# SCTP Configuration (EXPERIMENTAL) # -# CONFIG_IPX is not set -# CONFIG_ATALK is not set +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set # CONFIG_DECNET is not set # CONFIG_BRIDGE is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_LLC is not set # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set @@ -145,94 +266,10 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_NET_SCHED is not set # -# Telephony Support -# -# CONFIG_PHONE is not set -# CONFIG_PHONE_IXJ is not set -# CONFIG_PHONE_IXJ_PCMCIA is not set - -# -# ATA/IDE/MFM/RLL support -# -# CONFIG_IDE is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -CONFIG_CHR_DEV_ST=y -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set -CONFIG_SR_EXTRA_DEVS=2 -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -CONFIG_SGIWD93_SCSI=y -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR_D700 is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Network device support +# Network testing # +# CONFIG_NET_PKTGEN is not set CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set @@ -243,33 +280,16 @@ CONFIG_NETDEVICES=y # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -# CONFIG_SUNLANCE is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set +# CONFIG_MII is not set CONFIG_SGISEEQ=y # # Ethernet (1000 Mbit) # -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set + +# +# Ethernet (10000 Mbit) +# # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -279,11 +299,8 @@ CONFIG_SGISEEQ=y # CONFIG_NET_RADIO is not set # -# Token Ring devices +# Token Ring devices (depends on LLC=y) # -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set # CONFIG_SHAPER is not set # @@ -304,21 +321,69 @@ CONFIG_SGISEEQ=y # # ISDN subsystem # -# CONFIG_ISDN is not set +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set # -# Old CD-ROM drivers (not SCSI, not IDE) +# Input I/O drivers # -# CONFIG_CD_NO_IDESCSI is not set +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Character devices # CONFIG_VT=y CONFIG_VT_CONSOLE=y -# CONFIG_SERIAL is not set -# CONFIG_SERIAL_EXTENDED is not set +CONFIG_HW_CONSOLE=y # CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_IP22_ZILOG=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 @@ -328,36 +393,58 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_I2C is not set # -# Mice +# I2C Hardware Sensors Mainboard support # -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set # -# Joysticks +# I2C Hardware Sensors Chip support # -# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_I2C_SENSOR is not set # -# Input core support is needed for gameports +# Mice # +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set # -# Input core support is needed for joysticks +# IPMI # -# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set # # Watchdog Cards # -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_WDT is not set +# CONFIG_WDTPCI is not set +# CONFIG_PCWATCHDOG is not set +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_ADVANTECH_WDT is not set +# CONFIG_EUROTECH_WDT is not set +# CONFIG_IB700_WDT is not set +# CONFIG_I810_TCO is not set +# CONFIG_MIXCOMWD is not set +# CONFIG_SCx200_WDT is not set +# CONFIG_60XX_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_MACHZ_WDT is not set +CONFIG_INDYDOG=y +# CONFIG_SC520_WDT is not set +# CONFIG_AMD7XX_TCO is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_SC1200_WDT is not set +# CONFIG_WAFER_WDT is not set +# CONFIG_CPU5_WDT is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +CONFIG_SGI_DS1286=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_SONYPI is not set # # Ftape, the floppy tape device driver @@ -365,6 +452,8 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set # # Multimedia devices @@ -372,78 +461,92 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_VIDEO_DEV is not set # +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# # File systems # +# CONFIG_EXT2_FS is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set -# CONFIG_CMS_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_JBD_DEBUG is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_TMPFS is not set -# CONFIG_RAMFS is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_FREEVXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set +# CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set # # Network File Systems # -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set -CONFIG_ROOT_NFS=y +# CONFIG_NFS_V4 is not set CONFIG_NFSD=y # CONFIG_NFSD_V3 is not set -CONFIG_SUNRPC=y +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y CONFIG_LOCKD=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set # CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set # CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types @@ -460,150 +563,82 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_LDM_PARTITION is not set +# CONFIG_NEC98_PARTITION is not set CONFIG_SGI_PARTITION=y # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set +# CONFIG_EFI_PARTITION is not set # -# Console drivers +# Graphics support # # -# Frame-buffer support +# Console display driver support # -# CONFIG_FB is not set +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set CONFIG_SGI_NEWPORT_CONSOLE=y +CONFIG_DUMMY_CONSOLE=y CONFIG_FONT_8x16=y -CONFIG_KCORE_ELF=y # -# Sound +# Logo configuration # -# CONFIG_SOUND is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_LOGO_SGI_CLUT224=y # -# SGI devices +# Sound # -CONFIG_SGI_SERIAL=y -# CONFIG_SERIAL_CONSOLE is not set -CONFIG_SGI_DS1286=y -# CONFIG_SGI_NEWPORT_GFX is not set +# CONFIG_SOUND is not set # # USB support # -# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set # -# USB Controllers +# Bluetooth support # -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set +# CONFIG_BT is not set # -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# -# CONFIG_USB_DABUSB is not set - -# -# USB Network adaptors -# -# CONFIG_USB_PLUSB is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support +# Kernel hacking # -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_OMNINET is not set +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set # -# Miscellaneous USB drivers +# Security options # -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_ID75 is not set +# CONFIG_SECURITY is not set # -# Input core support +# Cryptographic options # -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_TEST is not set # -# Kernel hacking +# Library routines # -CONFIG_CROSSCOMPILE=y -# CONFIG_MIPS_FPE_MODULE is not set -# CONFIG_REMOTE_DEBUG is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_MIPS_UNCACHED is not set +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y --- linux-2.5.73/arch/mips64/defconfig-ip27 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/defconfig-ip27 2003-06-27 15:56:23.000000000 -0700 @@ -1,70 +1,133 @@ # # Automatically generated make config: don't edit # +CONFIG_MIPS=y +# CONFIG_MIPS32 is not set +CONFIG_MIPS64=y # # Code maturity level options # -# CONFIG_EXPERIMENTAL is not set +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=15 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set # # Machine selection # +# CONFIG_ACER_PICA_61 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set CONFIG_SGI_IP27=y # CONFIG_SGI_SN0_N_MODE is not set -CONFIG_DISCONTIGMEM=y -CONFIG_NUMA=y +# CONFIG_DISCONTIGMEM is not set +# CONFIG_NUMA is not set # CONFIG_MAPPED_KERNEL is not set # CONFIG_REPLICATE_KTEXT is not set # CONFIG_REPLICATE_EXHANDLERS is not set -CONFIG_SMP=y +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_BOOT_ELF64=y +CONFIG_ARC=y +CONFIG_GENERIC_ISA_DMA=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_L1_CACHE_SHIFT=7 +# CONFIG_FB is not set CONFIG_ARC64=y -CONFIG_COHERENT_IO=y -CONFIG_MAPPED_PCI_IO=y -CONFIG_PCI=y +CONFIG_BOOT_ELF64=y CONFIG_QL_ISP_A64=y -CONFIG_L1_CACHE_SHIFT=7 -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set # # CPU selection # +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set CONFIG_CPU_R10000=y +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_SMP=y +CONFIG_NR_CPUS=4 +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_MIPS_INSANE_LARGE is not set # -# General setup +# Bus options (PCI, PCMCIA, EISA, ISA, TC) # -# CONFIG_MIPS_INSANE_LARGE is not set -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_NET=y +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y CONFIG_PCI_NAMES=y +CONFIG_MMU=y # CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_BINFMT_ELF=y -CONFIG_MIPS32_COMPAT=y -CONFIG_BINFMT_ELF32=y -# CONFIG_BINFMT_MISC is not set # -# Loadable module support +# Executable file formats # -# CONFIG_MODULES is not set -CONFIG_PCI_NAMES=y +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_MIPS32_O32=y +# CONFIG_MIPS32_N32 is not set +CONFIG_BINFMT_ELF32=y # # Memory Technology Devices (MTD) @@ -77,83 +140,35 @@ CONFIG_PCI_NAMES=y # CONFIG_PARPORT is not set # +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_NETLINK=y -CONFIG_RTNETLINK=y -CONFIG_NETLINK_DEV=y -# CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_INET_ECN is not set -# CONFIG_SYN_COOKIES is not set - -# -# -# -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set -# CONFIG_PHONE_IXJ is not set -# CONFIG_PHONE_IXJ_PCMCIA is not set - -# -# ATA/IDE/MFM/RLL support +# ATA/ATAPI/MFM/RLL support # # CONFIG_IDE is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_HD is not set # -# SCSI support +# SCSI device support # CONFIG_SCSI=y @@ -161,7 +176,6 @@ CONFIG_SCSI=y # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 CONFIG_CHR_DEV_ST=y # CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set @@ -170,8 +184,8 @@ CONFIG_CHR_DEV_ST=y # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs # -# CONFIG_SCSI_DEBUG_QUEUES is not set # CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_REPORT_LUNS is not set CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y @@ -179,52 +193,116 @@ CONFIG_SCSI_LOGGING=y # SCSI low-level drivers # # CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set # CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set +# CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set # CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set # CONFIG_SCSI_MEGARAID is not set # CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_CPQFCTS is not set # CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set # CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set # CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR_D700 is not set -# CONFIG_SCSI_NCR53C7xx is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_NCR53C8XX is not set # CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set # CONFIG_SCSI_PCI2000 is not set # CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -CONFIG_SCSI_QLOGIC_ISP=y +# CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set +# CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set # -# Network device support +# IEEE 1394 (FireWire) support (EXPERIMENTAL) # +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set CONFIG_NETDEVICES=y # @@ -235,39 +313,44 @@ CONFIG_NETDEVICES=y # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set CONFIG_SGI_IOC3_ETH=y -# CONFIG_SUNLANCE is not set # CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set # CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set # # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set # CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set +# CONFIG_E1000 is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set # CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set # CONFIG_FDDI is not set -# CONFIG_PLIP is not set +# CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -277,10 +360,11 @@ CONFIG_SGI_IOC3_ETH=y # CONFIG_NET_RADIO is not set # -# Token Ring devices +# Token Ring devices (depends on LLC=y) # -# CONFIG_TR is not set # CONFIG_NET_FC is not set +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set # # Wan interfaces @@ -300,21 +384,69 @@ CONFIG_SGI_IOC3_ETH=y # # ISDN subsystem # -# CONFIG_ISDN is not set +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set # -# Old CD-ROM drivers (not SCSI, not IDE) +# Input Device Drivers # -# CONFIG_CD_NO_IDESCSI is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Character devices # # CONFIG_VT is not set -CONFIG_SERIAL=y -CONFIG_SERIAL_CONSOLE=y -# CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_CONSOLE is not set +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_MULTIPORT is not set +# CONFIG_SERIAL_8250_RSA is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 @@ -324,32 +456,33 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_I2C is not set # -# Mice +# I2C Hardware Sensors Mainboard support # -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set # -# Joysticks +# I2C Hardware Sensors Chip support # -# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_I2C_SENSOR is not set # -# Input core support is needed for gameports +# Mice # +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set # -# Input core support is needed for joysticks +# IPMI # -# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +CONFIG_SGI_IP27_RTC=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set @@ -360,6 +493,8 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set # # Multimedia devices @@ -367,79 +502,92 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_VIDEO_DEV is not set # +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# # File systems # +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_JBD=y +CONFIG_JBD_DEBUG=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set CONFIG_AUTOFS_FS=y # CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set -# CONFIG_CMS_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_JBD_DEBUG is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_TMPFS is not set -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_FREEVXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set +# CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set # # Network File Systems # -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y +# CONFIG_NFS_V4 is not set # CONFIG_NFSD is not set -# CONFIG_NFSD_V3 is not set -CONFIG_SUNRPC=y +CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set # CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set # CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types @@ -456,12 +604,15 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_LDM_PARTITION is not set +# CONFIG_NEC98_PARTITION is not set CONFIG_SGI_PARTITION=y # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set -CONFIG_KCORE_ELF=y +# CONFIG_EFI_PARTITION is not set + +# +# Graphics support +# # # Sound @@ -472,113 +623,30 @@ CONFIG_KCORE_ELF=y # USB support # # CONFIG_USB is not set +# CONFIG_USB_GADGET is not set # -# USB Controllers +# Bluetooth support # -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set +# CONFIG_BT is not set # -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# -# CONFIG_USB_DABUSB is not set - -# -# USB Network adaptors -# -# CONFIG_USB_PLUSB is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support +# Kernel hacking # -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_OMNINET is not set +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set # -# Miscellaneous USB drivers +# Security options # -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_ID75 is not set +# CONFIG_SECURITY is not set # -# Input core support +# Cryptographic options # -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set +# CONFIG_CRYPTO is not set # -# Kernel hacking +# Library routines # -CONFIG_CROSSCOMPILE=y -# CONFIG_REMOTE_DEBUG is not set -# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_CRC32 is not set --- linux-2.5.73/arch/mips64/defconfig-ip32 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/defconfig-ip32 2003-06-27 15:56:23.000000000 -0700 @@ -1,6 +1,9 @@ # # Automatically generated make config: don't edit # +CONFIG_MIPS=y +# CONFIG_MIPS32 is not set +CONFIG_MIPS64=y # # Code maturity level options @@ -8,57 +11,118 @@ CONFIG_EXPERIMENTAL=y # +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# # Machine selection # +# CONFIG_ACER_PICA_61 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set CONFIG_SGI_IP32=y +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +CONFIG_ARC=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_NONCOHERENT_IO=y +# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_BOOT_ELF32=y +CONFIG_L1_CACHE_SHIFT=5 CONFIG_ARC32=y -CONFIG_PC_KEYB=y -CONFIG_PCI=y +# CONFIG_FB is not set CONFIG_ARC_MEMORY=y -CONFIG_L1_CACHE_SHIFT=5 -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set +CONFIG_ARC_PROMLIB=y +CONFIG_BOARD_SCACHE=y # # CPU selection # +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set CONFIG_CPU_R5000=y +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_R5000_CPU_SCACHE=y +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set # -# General setup +# Bus options (PCI, PCMCIA, EISA, ISA, TC) # -# CONFIG_CPU_LITTLE_ENDIAN is not set -# CONFIG_MIPS_FPU_EMULATOR is not set -CONFIG_NET=y +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y CONFIG_PCI_NAMES=y +CONFIG_MMU=y # CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_SYSCTL=y -# CONFIG_PROM_CONSOLE is not set -CONFIG_BINFMT_ELF=y -CONFIG_MIPS32_COMPAT=y -CONFIG_BINFMT_ELF32=y -CONFIG_BINFMT_MISC=y # -# Loadable module support +# Executable file formats # -# CONFIG_MODULES is not set -CONFIG_PCI_NAMES=y +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +CONFIG_BINFMT_MISC=y +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_MIPS32_O32=y +# CONFIG_MIPS32_N32 is not set +CONFIG_BINFMT_ELF32=y # # Memory Technology Devices (MTD) @@ -71,90 +135,35 @@ CONFIG_PCI_NAMES=y # CONFIG_PARPORT is not set # +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -# CONFIG_NETLINK is not set -# CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_INET_ECN is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set - -# -# -# -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_LLC is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_FASTROUTE is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set -# CONFIG_PHONE_IXJ is not set - -# -# ATA/IDE/MFM/RLL support +# ATA/ATAPI/MFM/RLL support # # CONFIG_IDE is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_HD is not set # -# SCSI support +# SCSI device support # CONFIG_SCSI=y @@ -162,19 +171,17 @@ CONFIG_SCSI=y # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 CONFIG_CHR_DEV_ST=y CONFIG_CHR_DEV_OSST=y CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_SR_EXTRA_DEVS=2 CONFIG_CHR_DEV_SG=y # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs # -CONFIG_SCSI_DEBUG_QUEUES=y CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_REPORT_LUNS is not set CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y @@ -182,63 +189,122 @@ CONFIG_SCSI_LOGGING=y # SCSI low-level drivers # # CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set # CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set +# CONFIG_SCSI_AACRAID is not set CONFIG_SCSI_AIC7XXX=y CONFIG_AIC7XXX_CMDS_PER_DEVICE=8 CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +# CONFIG_AIC7XXX_PROBE_EISA_VL is not set # CONFIG_AIC7XXX_BUILD_FIRMWARE is not set +CONFIG_AIC7XXX_DEBUG_ENABLE=y +CONFIG_AIC7XXX_DEBUG_MASK=0 +CONFIG_AIC7XXX_REG_PRETTY_PRINT=y +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set # CONFIG_SCSI_MEGARAID is not set # CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_CPQFCTS is not set # CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set # CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set # CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR53C7xx is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_NCR53C8XX is not set # CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set # CONFIG_SCSI_PCI2000 is not set # CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set # CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set +# CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set +# CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# # I2O device support # # CONFIG_I2O is not set -# CONFIG_I2O_PCI is not set -# CONFIG_I2O_BLOCK is not set -# CONFIG_I2O_LAN is not set -# CONFIG_I2O_SCSI is not set -# CONFIG_I2O_PROC is not set # -# Network device support +# Networking support # +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set CONFIG_NETDEVICES=y # @@ -249,58 +315,42 @@ CONFIG_NETDEVICES=y # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_NET_SB1000 is not set +# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +CONFIG_SGI_O2MACE_ETH=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_AT1700 is not set -# CONFIG_DEPCA is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_APRICOT is not set -# CONFIG_CS89x0 is not set -CONFIG_TULIP=y -# CONFIG_DE4X5 is not set -# CONFIG_DGRS is not set -# CONFIG_DM9102 is not set -CONFIG_EEPRO100=y -# CONFIG_EEPRO100_PM is not set -# CONFIG_LNE390 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_NE3210 is not set -# CONFIG_ES3210 is not set -# CONFIG_8139TOO is not set -# CONFIG_8139TOO_PIO is not set -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139TOO_8129 is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_LAN_SAA9730 is not set -# CONFIG_NET_POCKET is not set +# CONFIG_NET_PCI is not set # # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set # CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PPP is not set @@ -312,9 +362,8 @@ CONFIG_EEPRO100=y # CONFIG_NET_RADIO is not set # -# Token Ring devices +# Token Ring devices (depends on LLC=y) # -# CONFIG_TR is not set # CONFIG_NET_FC is not set # CONFIG_RCPCI is not set # CONFIG_SHAPER is not set @@ -337,21 +386,65 @@ CONFIG_EEPRO100=y # # ISDN subsystem # -# CONFIG_ISDN is not set +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set # -# Old CD-ROM drivers (not SCSI, not IDE) +# Input device support # -# CONFIG_CD_NO_IDESCSI is not set +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Character devices # # CONFIG_VT is not set -CONFIG_SERIAL=y -CONFIG_SERIAL_CONSOLE=y -# CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 @@ -361,31 +454,32 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_I2C is not set # -# Mice +# I2C Hardware Sensors Mainboard support # -# CONFIG_BUSMOUSE is not set -CONFIG_MOUSE=y -CONFIG_PSMOUSE=y -# CONFIG_82C710_MOUSE is not set -# CONFIG_PC110_PAD is not set # -# Joysticks +# I2C Hardware Sensors Chip support # -# CONFIG_JOYSTICK is not set +# CONFIG_I2C_SENSOR is not set # -# Input core support is needed for joysticks +# Mice # +# CONFIG_BUSMOUSE is not set # CONFIG_QIC02_TAPE is not set # +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# # Watchdog Cards # # CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set @@ -396,6 +490,8 @@ CONFIG_PSMOUSE=y # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set # # Multimedia devices @@ -403,73 +499,84 @@ CONFIG_PSMOUSE=y # CONFIG_VIDEO_DEV is not set # +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# # File systems # +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +CONFIG_TMPFS=y +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set # CONFIG_CRAMFS is not set -CONFIG_TMPFS=y -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set # CONFIG_VXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set # CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set -# CONFIG_SYSV_FS_WRITE is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set # # Network File Systems # -# CONFIG_CODA_FS is not set CONFIG_NFS_FS=y CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y +# CONFIG_NFS_V4 is not set # CONFIG_NFSD is not set -# CONFIG_NFSD_V3 is not set -CONFIG_SUNRPC=y +CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set # CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set # CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types @@ -481,12 +588,16 @@ CONFIG_PARTITION_ADVANCED=y # CONFIG_ATARI_PARTITION is not set # CONFIG_MAC_PARTITION is not set # CONFIG_MSDOS_PARTITION is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_NEC98_PARTITION is not set CONFIG_SGI_PARTITION=y # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set -CONFIG_KCORE_ELF=y +# CONFIG_EFI_PARTITION is not set + +# +# Graphics support +# # # Sound @@ -497,16 +608,30 @@ CONFIG_KCORE_ELF=y # USB support # # CONFIG_USB is not set +# CONFIG_USB_GADGET is not set # -# Input core support +# Bluetooth support # -# CONFIG_INPUT is not set +# CONFIG_BT is not set # # Kernel hacking # CONFIG_CROSSCOMPILE=y -# CONFIG_REMOTE_DEBUG is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_MIPS_UNCACHED=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/defconfig-malta 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,558 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +# CONFIG_MIPS32 is not set +CONFIG_MIPS64=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +CONFIG_MIPS_MALTA=y +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_I8259=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_MIPS_BOARDS_GEN=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_L1_CACHE_SHIFT=5 +# CONFIG_FB is not set +CONFIG_HAVE_STD_PC_SERIAL_PORT=y + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +CONFIG_CPU_R4X00=y +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_PCI is not set +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_MIPS32_O32=y +# CONFIG_MIPS32_N32 is not set +CONFIG_BINFMT_ELF32=y + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +CONFIG_BLK_DEV_FD=y +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_REPORT_LUNS is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI low-level drivers +# +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_EATA_PIO is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +CONFIG_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +CONFIG_EFS_FS=y +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V4 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/defconfig-sb1250-swarm 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,611 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +# CONFIG_MIPS32 is not set +CONFIG_MIPS64=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=15 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +CONFIG_SIBYTE_SB1xxx_SOC=y +CONFIG_SIBYTE_SB1250=y +# CONFIG_SIMULATION is not set +CONFIG_SIBYTE_CFE=y +# CONFIG_SIBYTE_CFE_CONSOLE is not set +# CONFIG_SIBYTE_BUS_WATCHER is not set +# CONFIG_SIBYTE_SB1250_PROF is not set +# CONFIG_SIBYTE_TBPROF is not set +CONFIG_SIBYTE_SWARM=y +CONFIG_SIBYTE_BOARD=y +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_DUMMY_KEYB=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +# CONFIG_FB is not set + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +CONFIG_CPU_SB1=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_VTAG_ICACHE=y +CONFIG_CPU_SB1_PASS_1=y +# CONFIG_CPU_SB1_PASS_2 is not set +# CONFIG_CPU_SB1_PASS_2_2 is not set +CONFIG_SB1_PASS_1_WORKAROUNDS=y +CONFIG_SB1_CACHE_ERROR=y +CONFIG_SB1_CERR_IGNORE_RECOVERABLE=y +# CONFIG_SB1_CERR_SPIN is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_NAMES=y +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_MIPS32_O32=y +# CONFIG_MIPS32_N32 is not set +CONFIG_BINFMT_ELF32=y + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=9220 +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +CONFIG_NET_SB1250_MAC=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_COMPUTONE is not set +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_DIGIEPCA is not set +# CONFIG_DIGI is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_ISI is not set +# CONFIG_SYNCLINK is not set +# CONFIG_SYNCLINKMP is not set +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_SX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set +CONFIG_SIBYTE_SB1250_DUART=y +CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y +CONFIG_SERIAL_CONSOLE=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_TEST is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/defconfig-sead 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,391 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +# CONFIG_MIPS32 is not set +CONFIG_MIPS64=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +CONFIG_MIPS_SEAD=y +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_MIPS_BOARDS_GEN=y +CONFIG_L1_CACHE_SHIFT=5 +# CONFIG_FB is not set + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +CONFIG_CPU_R4X00=y +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_MIPS32_O32=y +# CONFIG_MIPS32_N32 is not set +CONFIG_BINFMT_ELF32=y + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=18432 +CONFIG_BLK_DEV_INITRD=y + +# +# MIPS initrd options +# +# CONFIG_EMBEDDED_RAMDISK is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# I2O device support +# + +# +# Networking support +# +# CONFIG_NET is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# ISDN subsystem +# + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB_GADGET is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set --- linux-2.5.73/arch/mips64/Kconfig 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/Kconfig 2003-06-27 15:56:23.000000000 -0700 @@ -2,586 +2,16 @@ # For a description of the syntax of this configuration file, # see Documentation/kbuild/kconfig-language.txt. # - -mainmenu "Linux Kernel Configuration" - -config MIPS64 - bool - default y - -config MMU - bool - default y - -source "init/Kconfig" - - -menu "Machine selection" - -choice - prompt "Machine type" - default SGI_IP27 - -config SGI_IP22 - bool "SGI-IP22,Indy/Indigo2" - help - This are the SGI Indy, Challenge S and Indigo2, as well as certain - OEM variants like the Tandem CMN B006S. To compile a Linux kernel - that runs on these, say Y here. - -config SGI_IP27 - bool "SGI-IP27,Origin200/2000" - help - This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics - workstations. To compile a Linux kernel that runs on these, say Y - here. - -endchoice - -config SGI_SN0_N_MODE - bool "IP27 N-Mode" - depends on SGI_IP27 - help - The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be - configured in either N-Modes which allows for more nodes or M-Mode - which allows for more memory. Your system is most probably - running in M-Mode, so you should say N here. - -config DISCONTIGMEM - bool "Discontiguous Memory Support" - depends on SGI_IP27 - help - Say Y to upport efficient handling of discontiguous physical memory, - for architectures which are either NUMA (Non-Uniform Memory Access) - or have huge holes in the physical address space for other reasons. - See for more. - -config NUMA - bool "NUMA Support" - depends on SGI_IP27 - help - Say Y to compile the kernel to support NUMA (Non-Uniform Memory - Access). This option is for configuring high-end multiprocessor - server machines. If in doubt, say N. - -config MAPPED_KERNEL - bool "Mapped kernel support" - depends on SGI_IP27 - help - Change the way a Linux kernel is loaded unto memory on a MIPS64 - machine. This is required in order to support text replication and - NUMA. If you need to undersatand it, read the source code. - -config REPLICATE_KTEXT - bool "Kernel text replication support" - depends on SGI_IP27 - help - Say Y here to enable replicating the kernel text across multiple - nodes in a NUMA cluster. This trades memory for speed. - -config REPLICATE_EXHANDLERS - bool "Exception handler replication support" - depends on SGI_IP27 - help - Say Y here to enable replicating the kernel exception handlers - across multiple nodes in a NUMA cluster. This trades memory for - speed. - -config SMP - bool "Multi-Processing support" - depends on SGI_IP27 - ---help--- - This enables support for systems with more than one CPU. If you have - a system with only one CPU, like most personal computers, say N. If - you have a system with more than one CPU, say Y. - - If you say N here, the kernel will run on single and multiprocessor - machines, but will use only one CPU of a multiprocessor machine. If - you say Y here, the kernel will run on many, but not all, - singleprocessor machines. On a singleprocessor machine, the kernel - will run faster if you say N here. - - Note that if you say Y here and choose architecture "586" or - "Pentium" under "Processor family", the kernel will not work on 486 - architectures. Similarly, multiprocessor kernels for the "PPro" - architecture may not work on all Pentium based boards. - - People using multiprocessor machines who say Y here should also say - Y to "Enhanced Real Time Clock Support", below. The "Advanced Power - Management" code will be disabled if you say Y here. - - See also the , - , , - and the SMP-HOWTO available at - . - - If you don't know what to do here, say N. - -#bool ' IP27 XXL' CONFIG_SGI_SN0_XXL -endmenu - -# -# Select some configuration options automatically based on user selections -# -config RWSEM_GENERIC_SPINLOCK - bool - default y - -config RWSEM_XCHGADD_ALGORITHM - bool - -config GENERIC_ISA_DMA - bool - default y - -config PCI - bool - depends on SGI_IP27 - default y - help - Find out whether you have a PCI motherboard. PCI is the name of a - bus system, i.e. the way the CPU talks to the other stuff inside - your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or - VESA. If you have PCI, say Y, otherwise N. - - The PCI-HOWTO, available from - , contains valuable - information about which PCI hardware does work under Linux and which - doesn't. - -config ISA - bool - help - Find out whether you have ISA slots on your motherboard. ISA is the - name of a bus system, i.e. the way the CPU talks to the other stuff - inside your box. Other bus systems are PCI, EISA, MicroChannel - (MCA) or VESA. ISA is an older system, now being displaced by PCI; - newer boards don't support it. If you have ISA, say Y, otherwise N. - -config EISA - bool - depends on ISA - default y - ---help--- - The Extended Industry Standard Architecture (EISA) bus was - developed as an open alternative to the IBM MicroChannel bus. - - The EISA bus provided some of the features of the IBM MicroChannel - bus while maintaining backward compatibility with cards made for - the older ISA bus. The EISA bus saw limited use between 1988 and - 1995 when it was made obsolete by the PCI bus. - - Say Y here if you are building a kernel for an EISA-based machine. - - Otherwise, say N. - -config BOOT_ELF32 - bool - depends on SGI_IP22 - default y - -config ARC32 - bool - depends on SGI_IP22 - default y - -config BOARD_SCACHE - bool - depends on SGI_IP22 - default y - -config ARC_MEMORY - bool - depends on SGI_IP22 - default y - -config SGI - bool - depends on SGI_IP22 - default y - -config L1_CACHE_SHIFT - int - default "7" if SGI_IP27 - default "5" if SGI_IP22 - -config BOOT_ELF64 - bool - depends on SGI_IP27 - default y - -config ARC64 - bool - depends on SGI_IP27 - default y - -config COHERENT_IO - bool - depends on SGI_IP27 - default y - -config MAPPED_PCI_IO - bool - depends on SGI_IP27 - default y - -config QL_ISP_A64 - bool - depends on SGI_IP27 - default y - -config MCA - bool - help - MicroChannel Architecture is found in some IBM PS/2 machines and - laptops. It is a bus system similar to PCI or ISA. See - (and especially the web page given - there) before attempting to build an MCA bus kernel. - -config SBUS - bool - - -menu "CPU selection" - -choice - prompt "CPU type" - default CPU_R4X00 - -config CPU_R4300 - bool "R4300" - help - MIPS Technologies R4300-series processors. - -config CPU_R4X00 - bool "R4x00" - help - MIPS Technologies R4000-series processors other than 4300, including - the 4640, 4650, and 4700. - -config CPU_R5000 - bool "R5000" - help - MIPS Technologies R5000-series processors other than the Nevada. - -config CPU_NEVADA - bool "R52x0" - help - MIPS Technologies R52x0-series ("Nevada") processors. - -config CPU_R8000 - bool "R8000" - help - MIPS Technologies R8000-series processors. - -config CPU_R10000 - bool "R10000" - help - MIPS Technologies R10000-series processors. - -endchoice - -endmenu - - -menu "General setup" - -config MIPS_INSANE_LARGE - bool "Support for large 64-bit configurations" - depends on CPU_R10000 - help - MIPS R10000 does support a 44 bit / 16TB address space as opposed to - previous 64-bit processors which only supported 40 bit / 1TB. If you - need processes of more than 1TB virtual address space, say Y here. - This will result in additional memory usage, so it is not - recommended for normal users. - -config CPU_LITTLE_ENDIAN - bool "Generate little endian code" - help - Some MIPS machines can be configured for either little or big endian - byte order. These modes require different kernels. Say Y if your - machine is little endian, N if it's a big endian machine. - -config MIPS_FPU_EMULATOR - bool "Kernel floating-point emulation" - depends on EXPERIMENTAL - help - This option enables the MIPS software floatingpoint support. Due to - the way floating point works you should always enable this option - unless you exactly know what you're doing. - -config HOTPLUG - bool "Support for hot-pluggable devices" - ---help--- - Say Y here if you want to plug devices into your computer while - the system is running, and be able to use them quickly. In many - cases, the devices can likewise be unplugged at any time too. - - One well known example of this is PCMCIA- or PC-cards, credit-card - size devices such as network cards, modems or hard drives which are - plugged into slots found on all modern laptop computers. Another - example, used on modern desktops as well as laptops, is USB. - - Enable HOTPLUG and KMOD, and build a modular kernel. Get agent - software (at ) and install it. - Then your kernel will automatically call out to a user mode "policy - agent" (/sbin/hotplug) to load modules and set up software needed - to use devices as you hotplug them. - -source "drivers/pcmcia/Kconfig" - -config ARC_CONSOLE - bool "ARC console support" - depends on ARC32 - -source "fs/Kconfig.binfmt" - -config MIPS32_COMPAT - bool "Kernel support for Linux/MIPS 32-bit binary compatibility" - help - Select this option if you want Linux/MIPS 32-bit binary - compatibility. Since all software available for Linux/MIPS is - currently 32-bit you should say Y here. - -config COMPAT +config MIPS bool - depends on MIPS32_COMPAT default y -config BINFMT_ELF32 +config MIPS32 bool - depends on BINFMT_ELF && MIPS32_COMPAT - default y - help - This allows you to run 32-bit Linux/ELF binaries on your Ultra. - Everybody wants this; say Y. - -endmenu - -source "drivers/pci/Kconfig" - -source "drivers/base/Kconfig" - -source "drivers/mtd/Kconfig" - -source "drivers/parport/Kconfig" - -source "drivers/block/Kconfig" - -source "drivers/md/Kconfig" - -source "drivers/ide/Kconfig" - - -menu "SCSI support" - -config SCSI - tristate "SCSI support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - -source "drivers/scsi/Kconfig" - -endmenu - -#source drivers/message/i2o/Config.in -source "net/Kconfig" - -source "net/ax25/Kconfig" - -source "net/irda/Kconfig" + default n -source "drivers/isdn/Kconfig" - -source "drivers/telephony/Kconfig" - - -menu "Old CD-ROM drivers (not SCSI, not IDE)" - -config CD_NO_IDESCSI - bool "Support non-SCSI/IDE/ATAPI CDROM drives" - ---help--- - If you have a CD-ROM drive that is neither SCSI nor IDE/ATAPI, say Y - here, otherwise N. Read the CD-ROM-HOWTO, available from - . - - Note that the answer to this question doesn't directly affect the - kernel: saying N will just cause the configurator to skip all - the questions about these CD-ROM drives. If you are unsure what you - have, say Y and find out whether you have one of the following - drives. - - For each of these drivers, a file Documentation/cdrom/{driver_name} - exists. Especially in cases where you do not know exactly which kind - of drive you have you should read there. Most of these drivers use a - file drivers/cdrom/{driver_name}.h where you can define your - interface parameters and switch some internal goodies. - - All these CD-ROM drivers are also usable as a module ( = code which - can be inserted in and removed from the running kernel whenever you - want). If you want to compile them as module, say M instead of Y and - read . - - If you want to use any of these CD-ROM drivers, you also have to - answer Y or M to "ISO 9660 CD-ROM file system support" below (this - answer will get "defaulted" for you if you enable any of the Linux - CD-ROM drivers). - -source "drivers/cdrom/Kconfig" - -endmenu - -source "drivers/input/Kconfig" - -source "drivers/char/Kconfig" - -#source drivers/misc/Config.in -source "drivers/media/Kconfig" - -source "fs/Kconfig" - -source "drivers/video/Kconfig" - -config KCORE_ELF +config MIPS64 bool - depends on PROC_FS default y - ---help--- - If you enabled support for /proc file system then the file - /proc/kcore will contain the kernel core image. This can be used - in gdb: - - $ cd /usr/src/linux ; gdb vmlinux /proc/kcore - - You have two choices here: ELF and A.OUT. Selecting ELF will make - /proc/kcore appear in ELF core format as defined by the Executable - and Linking Format specification. Selecting A.OUT will choose the - old "a.out" format which may be necessary for some old versions - of binutils or on some architectures. - - This is especially useful if you have compiled the kernel with the - "-g" option to preserve debugging information. It is mainly used - for examining kernel data structures on the live kernel so if you - don't understand what this means or are not a kernel hacker, just - leave it at its default value ELF. - - -menu "Sound" - -config SOUND - tristate "Sound card support" - ---help--- - If you have a sound card in your computer, i.e. if it can say more - than an occasional beep, say Y. Be sure to have all the information - about your sound card and its configuration down (I/O port, - interrupt and DMA channel), because you will be asked for it. - - You want to read the Sound-HOWTO, available from - . General information about - the modular sound system is contained in the files - . The file - contains some slightly - outdated but still useful information as well. - - If you have a PnP sound card and you want to configure it at boot - time using the ISA PnP tools (read - ), then you need to - compile the sound card support as a module ( = code which can be - inserted in and removed from the running kernel whenever you want) - and load that module after the PnP configuration is finished. To do - this, say M here and read as well - as ; the module will be - called soundcore. - - I'm told that even without a sound card, you can make your computer - say more than an occasional beep, by programming the PC speaker. - Kernel patches and supporting utilities to do that are in the pcsp - package, available at . - -source "sound/Kconfig" - -endmenu - -source "drivers/sgi/Kconfig" - -source "drivers/usb/Kconfig" - - -menu "Kernel hacking" - -#bool 'Debug kmalloc/kfree' CONFIG_DEBUG_MALLOC -config CROSSCOMPILE - bool "Are you using a crosscompiler" - help - Say Y here if you are compiling the kernel on a different - architecture than the one it is intended to run on. - -config MIPS_FPE_MODULE - bool "Build fp exception handler module" - depends on MODULES - help - Build the floating point exception handler module. This option is - only useful for people working on the floating point exception - handler. If you don't, say N. - -config REMOTE_DEBUG - bool "Remote GDB kernel debugging" - help - If you say Y here, it will be possible to remotely debug the MIPS - kernel using gdb. This enlarges your kernel image disk size by - several megabytes and requires a machine with more than 16 MB, - better 32 MB RAM to avoid excessive linking time. This is only - useful for kernel hackers. If unsure, say N. - -config MAGIC_SYSRQ - bool "Magic SysRq key" - help - If you say Y here, you will have some control over the system even - if the system crashes for example during kernel debugging (e.g., you - will be able to flush the buffer cache to disk, reboot the system - immediately or dump some status information). This is accomplished - by pressing various keys while holding SysRq (Alt+PrintScreen). It - also works on a serial console (on PC hardware at least), if you - send a BREAK and then within 5 seconds a command keypress. The - keys are documented in . Don't say Y - unless you really know what this hack does. - -config MIPS_UNCACHED - bool "Run uncached" - depends on !SMP - help - If you say Y here there kernel will disable all CPU caches. This will - reduce the system's performance dramatically but can help finding - otherwise hard to track bugs. It can also useful if you're doing - hardware debugging with a logic analyzer and need to see all traffic - on the bus. - -config NR_CPUS - int "Maximum number of CPUs (2-64)" - depends on SMP - default "64" - -endmenu - -source "security/Kconfig" - -source "crypto/Kconfig" - -source "lib/Kconfig" +source "arch/mips/Kconfig-shared" --- linux-2.5.73/arch/mips64/kernel/binfmt_elf32.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,99 +0,0 @@ -/* - * Support for 32-bit Linux/MIPS ELF binaries. - * - * Copyright (C) 1999, 2001 Ralf Baechle - * Copyright (C) 1999, 2001 Silicon Graphics, Inc. - * - * Heavily inspired by the 32-bit Sparc compat code which is - * Copyright (C) 1995, 1996, 1997, 1998 David S. Miller (davem@redhat.com) - * Copyright (C) 1995, 1996, 1997, 1998 Jakub Jelinek (jj@ultra.linux.cz) - */ - -#define ELF_ARCH EM_MIPS -#define ELF_CLASS ELFCLASS32 -#ifdef __MIPSEB__ -#define ELF_DATA ELFDATA2MSB; -#else /* __MIPSEL__ */ -#define ELF_DATA ELFDATA2LSB; -#endif - -/* ELF register definitions */ -#define ELF_NGREG 45 -#define ELF_NFPREG 33 - -typedef unsigned int elf_greg_t; -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -typedef double elf_fpreg_t; -typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; - -#define elf_check_arch(x) \ - ((x)->e_machine == EM_MIPS) - -#define TASK32_SIZE 0x80000000UL -#undef ELF_ET_DYN_BASE -#define ELF_ET_DYN_BASE (TASK32_SIZE / 3 * 2) - -#include -#include -#include -#include - -struct timeval32 -{ - unsigned int tv_sec, tv_usec; -}; - -#define elf_prstatus elf_prstatus32 -struct elf_prstatus32 -{ - struct elf_siginfo pr_info; /* Info associated with signal */ - short pr_cursig; /* Current signal */ - unsigned int pr_sigpend; /* Set of pending signals */ - unsigned int pr_sighold; /* Set of held signals */ - pid_t pr_pid; - pid_t pr_ppid; - pid_t pr_pgrp; - pid_t pr_sid; - struct timeval32 pr_utime; /* User time */ - struct timeval32 pr_stime; /* System time */ - struct timeval32 pr_cutime; /* Cumulative user time */ - struct timeval32 pr_cstime; /* Cumulative system time */ - elf_gregset_t pr_reg; /* GP registers */ - int pr_fpvalid; /* True if math co-processor being used. */ -}; - -#define elf_prpsinfo elf_prpsinfo32 -struct elf_prpsinfo32 -{ - char pr_state; /* numeric process state */ - char pr_sname; /* char for pr_state */ - char pr_zomb; /* zombie */ - char pr_nice; /* nice val */ - unsigned int pr_flag; /* flags */ - u16 pr_uid; - u16 pr_gid; - pid_t pr_pid, pr_ppid, pr_pgrp, pr_sid; - /* Lots missing */ - char pr_fname[16]; /* filename of executable */ - char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */ -}; - -#define elf_addr_t u32 -#define init_elf_binfmt init_elf32_binfmt -#undef CONFIG_BINFMT_ELF -#ifdef CONFIG_BINFMT_ELF32 -#define CONFIG_BINFMT_ELF CONFIG_BINFMT_ELF32 -#endif -#undef CONFIG_BINFMT_ELF_MODULE -#ifdef CONFIG_BINFMT_ELF32_MODULE -#define CONFIG_BINFMT_ELF_MODULE CONFIG_BINFMT_ELF32_MODULE -#endif - -MODULE_DESCRIPTION("Binary format loader for compatibility with 32bit Linux/MIPS binaries"); -MODULE_AUTHOR("Ralf Baechle (ralf@oss.sgi.com)"); - -#undef MODULE_DESCRIPTION -#undef MODULE_AUTHOR - -#include "../../../fs/binfmt_elf.c" --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/kernel/binfmt_elfn32.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,115 @@ +/* + * Support for n32 Linux/MIPS ELF binaries. + * + * Copyright (C) 1999, 2001 Ralf Baechle + * Copyright (C) 1999, 2001 Silicon Graphics, Inc. + * + * Heavily inspired by the 32-bit Sparc compat code which is + * Copyright (C) 1995, 1996, 1997, 1998 David S. Miller (davem@redhat.com) + * Copyright (C) 1995, 1996, 1997, 1998 Jakub Jelinek (jj@ultra.linux.cz) + */ + +#define ELF_ARCH EM_MIPS +#define ELF_CLASS ELFCLASS32 +#ifdef __MIPSEB__ +#define ELF_DATA ELFDATA2MSB; +#else /* __MIPSEL__ */ +#define ELF_DATA ELFDATA2LSB; +#endif + +/* ELF register definitions */ +#define ELF_NGREG 45 +#define ELF_NFPREG 33 + +typedef unsigned long elf_greg_t; +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +typedef double elf_fpreg_t; +typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(hdr) \ +({ \ + int __res = 1; \ + struct elfhdr *__h = (hdr); \ + \ + if (__h->e_machine != EM_MIPS) \ + __res = 0; \ + if (__h->e_ident[EI_CLASS] != ELFCLASS32) \ + __res = 0; \ + if (((__h->e_flags & EF_MIPS_ABI2) == 0) || \ + ((__h->e_flags & EF_MIPS_ABI) != 0)) \ + __res = 0; \ + \ + __res; \ +}) + +#define TASK32_SIZE 0x7fff8000UL +#undef ELF_ET_DYN_BASE +#define ELF_ET_DYN_BASE (TASK32_SIZE / 3 * 2) + +#include +#include +#include +#include +#include + +#define elf_prstatus elf_prstatus32 +struct elf_prstatus32 +{ + struct elf_siginfo pr_info; /* Info associated with signal */ + short pr_cursig; /* Current signal */ + unsigned int pr_sigpend; /* Set of pending signals */ + unsigned int pr_sighold; /* Set of held signals */ + pid_t pr_pid; + pid_t pr_ppid; + pid_t pr_pgrp; + pid_t pr_sid; + struct compat_timeval pr_utime; /* User time */ + struct compat_timeval pr_stime; /* System time */ + struct compat_timeval pr_cutime;/* Cumulative user time */ + struct compat_timeval pr_cstime;/* Cumulative system time */ + elf_gregset_t pr_reg; /* GP registers */ + int pr_fpvalid; /* True if math co-processor being used. */ +}; + +#define elf_prpsinfo elf_prpsinfo32 +struct elf_prpsinfo32 +{ + char pr_state; /* numeric process state */ + char pr_sname; /* char for pr_state */ + char pr_zomb; /* zombie */ + char pr_nice; /* nice val */ + unsigned int pr_flag; /* flags */ + __kernel_uid_t pr_uid; + __kernel_gid_t pr_gid; + pid_t pr_pid, pr_ppid, pr_pgrp, pr_sid; + /* Lots missing */ + char pr_fname[16]; /* filename of executable */ + char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */ +}; + +#define elf_addr_t u32 +#define elf_caddr_t u32 +#define init_elf_binfmt init_elfn32_binfmt + +#define ELF_CORE_EFLAGS EF_MIPS_ABI2 + +#undef CONFIG_BINFMT_ELF +#ifdef CONFIG_BINFMT_ELF32 +#define CONFIG_BINFMT_ELF CONFIG_BINFMT_ELF32 +#endif +#undef CONFIG_BINFMT_ELF_MODULE +#ifdef CONFIG_BINFMT_ELF32_MODULE +#define CONFIG_BINFMT_ELF_MODULE CONFIG_BINFMT_ELF32_MODULE +#endif + +MODULE_DESCRIPTION("Binary format loader for compatibility with n32 Linux/MIPS binaries"); +MODULE_AUTHOR("Ralf Baechle (ralf@linux-mips.org)"); + +#undef MODULE_DESCRIPTION +#undef MODULE_AUTHOR + +#include "../../../fs/binfmt_elf.c" --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/kernel/binfmt_elfo32.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,136 @@ +/* + * Support for o32 Linux/MIPS ELF binaries. + * + * Copyright (C) 1999, 2001 Ralf Baechle + * Copyright (C) 1999, 2001 Silicon Graphics, Inc. + * + * Heavily inspired by the 32-bit Sparc compat code which is + * Copyright (C) 1995, 1996, 1997, 1998 David S. Miller (davem@redhat.com) + * Copyright (C) 1995, 1996, 1997, 1998 Jakub Jelinek (jj@ultra.linux.cz) + */ + +#define ELF_ARCH EM_MIPS +#define ELF_CLASS ELFCLASS32 +#ifdef __MIPSEB__ +#define ELF_DATA ELFDATA2MSB; +#else /* __MIPSEL__ */ +#define ELF_DATA ELFDATA2LSB; +#endif + +/* ELF register definitions */ +#define ELF_NGREG 45 +#define ELF_NFPREG 33 + +typedef unsigned int elf_greg_t; +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +typedef double elf_fpreg_t; +typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(hdr) \ +({ \ + int __res = 1; \ + struct elfhdr *__h = (hdr); \ + \ + if (__h->e_machine != EM_MIPS) \ + __res = 0; \ + if (__h->e_ident[EI_CLASS] != ELFCLASS32) \ + __res = 0; \ + if ((__h->e_flags & EF_MIPS_ABI2) != 0) \ + __res = 0; \ + if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ + ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ + __res = 0; \ + \ + __res; \ +}) + +#define TASK32_SIZE 0x7fff8000UL +#undef ELF_ET_DYN_BASE +#define ELF_ET_DYN_BASE (TASK32_SIZE / 3 * 2) + +#include +#include +#include +#include +#include + +#define elf_prstatus elf_prstatus32 +struct elf_prstatus32 +{ + struct elf_siginfo pr_info; /* Info associated with signal */ + short pr_cursig; /* Current signal */ + unsigned int pr_sigpend; /* Set of pending signals */ + unsigned int pr_sighold; /* Set of held signals */ + pid_t pr_pid; + pid_t pr_ppid; + pid_t pr_pgrp; + pid_t pr_sid; + struct compat_timeval pr_utime; /* User time */ + struct compat_timeval pr_stime; /* System time */ + struct compat_timeval pr_cutime;/* Cumulative user time */ + struct compat_timeval pr_cstime;/* Cumulative system time */ + elf_gregset_t pr_reg; /* GP registers */ + int pr_fpvalid; /* True if math co-processor being used. */ +}; + +#define elf_prpsinfo elf_prpsinfo32 +struct elf_prpsinfo32 +{ + char pr_state; /* numeric process state */ + char pr_sname; /* char for pr_state */ + char pr_zomb; /* zombie */ + char pr_nice; /* nice val */ + unsigned int pr_flag; /* flags */ + __kernel_uid_t pr_uid; + __kernel_gid_t pr_gid; + pid_t pr_pid, pr_ppid, pr_pgrp, pr_sid; + /* Lots missing */ + char pr_fname[16]; /* filename of executable */ + char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */ +}; + +#define elf_addr_t u32 +#define elf_caddr_t u32 +#define init_elf_binfmt init_elf32_binfmt + + +#undef ELF_CORE_COPY_REGS +#define ELF_CORE_COPY_REGS(_dest,_regs) elf32_core_copy_regs(_dest,_regs); + +void elf32_core_copy_regs(elf_gregset_t _dest, struct pt_regs *_regs) +{ + int i; + + memset(_dest, 0, sizeof(elf_gregset_t)); + + /* XXXKW the 6 is from EF_REG0 in gdb/gdb/mips-linux-tdep.c, include/asm-mips/reg.h */ + for (i=6; i<38; i++) + _dest[i] = (elf_greg_t) _regs->regs[i-6]; + _dest[i++] = (elf_greg_t) _regs->lo; + _dest[i++] = (elf_greg_t) _regs->hi; + _dest[i++] = (elf_greg_t) _regs->cp0_epc; + _dest[i++] = (elf_greg_t) _regs->cp0_badvaddr; + _dest[i++] = (elf_greg_t) _regs->cp0_status; + _dest[i++] = (elf_greg_t) _regs->cp0_cause; +} + +#undef CONFIG_BINFMT_ELF +#ifdef CONFIG_BINFMT_ELF32 +#define CONFIG_BINFMT_ELF CONFIG_BINFMT_ELF32 +#endif +#undef CONFIG_BINFMT_ELF_MODULE +#ifdef CONFIG_BINFMT_ELF32_MODULE +#define CONFIG_BINFMT_ELF_MODULE CONFIG_BINFMT_ELF32_MODULE +#endif + +MODULE_DESCRIPTION("Binary format loader for compatibility with o32 Linux/MIPS binaries"); +MODULE_AUTHOR("Ralf Baechle (ralf@linux-mips.org)"); + +#undef MODULE_DESCRIPTION +#undef MODULE_AUTHOR + +#include "../../../fs/binfmt_elf.c" --- linux-2.5.73/arch/mips64/kernel/branch.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/branch.c 2003-06-27 15:56:23.000000000 -0700 @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -163,7 +164,10 @@ int __compute_return_epc(struct pt_regs * And now the FPA/cp1 branch instructions. */ case cop1_op: - asm ("cfc1\t%0,$31":"=r" (fcr31)); + if (!cpu_has_fpu) + fcr31 = current->thread.fpu.soft.sr; + else + asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); bit = (insn.i_format.rt >> 2); bit += (bit != 0); bit += 23; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/kernel/cpu-probe.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,746 @@ +/* + * arch/mips64/kernel/cpu-probe.c + * + * Processor capabilities determination functions. + * + * Copyright (C) xxxx the Anonymous + * Copyright (C) 2003 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* + * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, + * the implementation of the "wait" feature differs between CPU families. This + * points to the function that implements CPU specific wait. + * The wait instruction stops the pipeline and reduces the power consumption of + * the CPU very much. + */ +void (*cpu_wait)(void) = NULL; + +static void r3081_wait(void) +{ + unsigned long cfg = read_c0_conf(); + write_c0_conf(cfg | R30XX_CONF_HALT); +} + +static void r39xx_wait(void) +{ + unsigned long cfg = read_c0_conf(); + write_c0_conf(cfg | TX39_CONF_HALT); +} + +static void r4k_wait(void) +{ + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void au1k_wait(void) +{ +#ifdef CONFIG_PM + /* using the wait instruction makes CP0 counter unusable */ + __asm__(".set\tmips3\n\t" + "wait\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + ".set\tmips0"); +#else + __asm__("nop\n\t" + "nop"); +#endif +} + +static inline void check_wait(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + + printk("Checking for 'wait' instruction... "); + switch (c->cputype) { + case CPU_R3081: + case CPU_R3081E: + cpu_wait = r3081_wait; + printk(" available.\n"); + break; + case CPU_TX3927: + cpu_wait = r39xx_wait; + printk(" available.\n"); + break; + case CPU_R4200: +/* case CPU_R4300: */ + case CPU_R4600: + case CPU_R4640: + case CPU_R4650: + case CPU_R4700: + case CPU_R5000: + case CPU_NEVADA: + case CPU_RM7000: + case CPU_TX49XX: + case CPU_4KC: + case CPU_4KEC: + case CPU_4KSC: + case CPU_5KC: +/* case CPU_20KC:*/ + cpu_wait = r4k_wait; + printk(" available.\n"); + break; + case CPU_AU1000: + case CPU_AU1100: + case CPU_AU1500: + cpu_wait = au1k_wait; + printk(" available.\n"); + break; + default: + printk(" unavailable.\n"); + break; + } +} + +static inline void check_mult_sh(void) +{ + unsigned long flags; + int m1, m2; + long p, s, v; + + printk("Checking for the multiply/shift bug... "); + + local_irq_save(flags); + /* + * The following code leads to a wrong result of dsll32 when + * executed on R4000 rev. 2.2 or 3.0. + * + * See "MIPS R4000PC/SC Errata, Processor Revision 2.2 and + * 3.0" by MIPS Technologies, Inc., errata #16 and #28 for + * details. I got no permission to duplicate them here, + * sigh... --macro + */ + asm volatile( + ".set push\n\t" + ".set noat\n\t" + ".set noreorder\n\t" + ".set nomacro\n\t" + "mult %1, %2\n\t" + "dsll32 %0, %3, %4\n\t" + "mflo $0\n\t" + ".set pop" + : "=r" (v) + : "r" (5), "r" (8), "r" (5), "I" (0) + : "hi", "lo", "accum"); + local_irq_restore(flags); + + if (v == 5L << 32) { + printk("no.\n"); + return; + } + + printk("yes, workaround... "); + local_irq_save(flags); + /* + * We want the multiply and the shift to be isolated from the + * rest of the code to disable gcc optimizations. Hence the + * asm statements that execute nothing, but make gcc not know + * what the values of m1, m2 and s are and what v and p are + * used for. + * + * We have to use single integers for m1 and m2 and a double + * one for p to be sure the mulsidi3 gcc's RTL multiplication + * instruction has the workaround applied. Older versions of + * gcc have correct mulsi3, but other multiplication variants + * lack the workaround. + */ + asm volatile( + "" + : "=r" (m1), "=r" (m2), "=r" (s) + : "0" (5), "1" (8), "2" (5)); + p = m1 * m2; + v = s << 32; + asm volatile( + "" + : "=r" (v) + : "0" (v), "r" (p)); + local_irq_restore(flags); + + if (v == 5L << 32) { + printk("yes.\n"); + return; + } + + printk("no.\n"); + panic("Reliable operation impossible!\n" +#ifndef CONFIG_CPU_R4000 + "Configure for R4000 to enable the workaround." +#else + "Please report to ." +#endif + ); +} + +static volatile int daddi_ov __initdata = 0; + +asmlinkage void __init do_daddi_ov(struct pt_regs *regs) +{ + daddi_ov = 1; + regs->cp0_epc += 4; +} + +static inline void check_daddi(void) +{ + extern asmlinkage void handle_daddi_ov(void); + unsigned long flags; + void *handler; + long v; + + printk("Checking for the daddi bug... "); + + local_irq_save(flags); + handler = set_except_vector(12, handle_daddi_ov); + /* + * The following code fails to trigger an overflow exception + * when executed on R4000 rev. 2.2 or 3.0. + * + * See "MIPS R4000PC/SC Errata, Processor Revision 2.2 and + * 3.0" by MIPS Technologies, Inc., erratum #23 for details. + * I got no permission to duplicate it here, sigh... --macro + */ + asm volatile( + ".set push\n\t" + ".set noat\n\t" + ".set noreorder\n\t" + ".set nomacro\n\t" +#ifdef HAVE_AS_SET_DADDI + ".set daddi\n\t" +#endif + "daddi %0, %1, %2\n\t" + ".set pop" + : "=r" (v) + : "r" (0x7fffffffffffedcd), "I" (0x1234)); + set_except_vector(12, handler); + local_irq_restore(flags); + + if (daddi_ov) { + printk("no.\n"); + return; + } + + printk("yes, workaround... "); + + local_irq_save(flags); + handler = set_except_vector(12, handle_daddi_ov); + asm volatile( + "daddi %0, %1, %2" + : "=r" (v) + : "r" (0x7fffffffffffedcd), "I" (0x1234)); + set_except_vector(12, handler); + local_irq_restore(flags); + + if (daddi_ov) { + printk("yes.\n"); + return; + } + + printk("no.\n"); + panic("Reliable operation impossible!\n" +#if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400) + "Configure for R4000 or R4400 to enable the workaround." +#else + "Please report to ." +#endif + ); +} + +static inline void check_daddiu(void) +{ + long v, w; + + printk("Checking for the daddiu bug... "); + + /* + * The following code leads to a wrong result of daddiu when + * executed on R4400 rev. 1.0. + * + * See "MIPS R4400PC/SC Errata, Processor Revision 1.0" by + * MIPS Technologies, Inc., erratum #7 for details. + * + * According to "MIPS R4000PC/SC Errata, Processor Revision + * 2.2 and 3.0" by MIPS Technologies, Inc., erratum #41 this + * problem affects R4000 rev. 2.2 and 3.0, too. Testing + * failed to trigger it so far. + * + * I got no permission to duplicate the errata here, sigh... + * --macro + */ + asm volatile( + ".set push\n\t" + ".set noat\n\t" + ".set noreorder\n\t" + ".set nomacro\n\t" +#ifdef HAVE_AS_SET_DADDI + ".set daddi\n\t" +#endif + "daddiu %0, %2, %3\n\t" + "addiu %1, $0, %3\n\t" + "daddu %1, %2\n\t" + ".set pop" + : "=&r" (v), "=&r" (w) + : "r" (0x7fffffffffffedcd), "I" (0x1234)); + + if (v == w) { + printk("no.\n"); + return; + } + + printk("yes, workaround... "); + + asm volatile( + "daddiu %0, %2, %3\n\t" + "addiu %1, $0, %3\n\t" + "daddu %1, %2" + : "=&r" (v), "=&r" (w) + : "r" (0x7fffffffffffedcd), "I" (0x1234)); + + if (v == w) { + printk("yes.\n"); + return; + } + + printk("no.\n"); + panic("Reliable operation impossible!\n" +#if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400) + "Configure for R4000 or R4400 to enable the workaround." +#else + "Please report to ." +#endif + ); +} + +void __init check_bugs(void) +{ + check_wait(); + check_mult_sh(); + check_daddi(); + check_daddiu(); +} + +/* + * Probe whether cpu has config register by trying to play with + * alternate cache bit and see whether it matters. + * It's used by cpu_probe to distinguish between R3000A and R3081. + */ +static inline int cpu_has_confreg(void) +{ +#ifdef CONFIG_CPU_R3000 + extern unsigned long r3k_cache_size(unsigned long); + unsigned long size1, size2; + unsigned long cfg = read_c0_conf(); + + size1 = r3k_cache_size(ST0_ISC); + write_c0_conf(cfg ^ R30XX_CONF_AC); + size2 = r3k_cache_size(ST0_ISC); + write_c0_conf(cfg); + return size1 != size2; +#else + return 0; +#endif +} + +/* + * Get the FPU Implementation/Revision. + */ +static inline unsigned long cpu_get_fpu_id(void) +{ + unsigned long tmp, fpu_id; + + tmp = read_c0_status(); + __enable_fpu(); + fpu_id = read_32bit_cp1_register(CP1_REVISION); + write_c0_status(tmp); + return fpu_id; +} + +/* + * Check the CPU has an FPU the official way. + */ +static inline int __cpu_has_fpu(void) +{ + return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); +} + +#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \ + | MIPS_CPU_COUNTER | MIPS_CPU_CACHE_CDEX) + +__init void cpu_probe(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned long config0 = read_c0_config(); + unsigned long config1; + + c->processor_id = PRID_IMP_UNKNOWN; + c->fpu_id = FPIR_IMP_NONE; + c->cputype = CPU_UNKNOWN; + + if (config0 & (1 << 31)) { + /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */ + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | + MIPS_CPU_LLSC; + config1 = read_c0_config1(); + if (config1 & (1 << 3)) + c->options |= MIPS_CPU_WATCH; + if (config1 & (1 << 2)) + c->options |= MIPS_CPU_MIPS16; + if (config1 & (1 << 1)) + c->options |= MIPS_CPU_EJTAG; + if (config1 & 1) { + c->options |= MIPS_CPU_FPU; + c->options |= MIPS_CPU_32FPR; + } + c->scache.flags = MIPS_CACHE_NOT_PRESENT; + + c->tlbsize = ((config1 >> 25) & 0x3f) + 1; + } + + c->processor_id = read_c0_prid(); + switch (c->processor_id & 0xff0000) { + case PRID_COMP_LEGACY: + switch (c->processor_id & 0xff00) { + case PRID_IMP_R2000: + c->cputype = CPU_R2000; + c->isa_level = MIPS_CPU_ISA_I; + c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX | + MIPS_CPU_LLSC; + if (__cpu_has_fpu()) + c->options |= MIPS_CPU_FPU; + c->tlbsize = 64; + break; + case PRID_IMP_R3000: + if ((c->processor_id & 0xff) == PRID_REV_R3000A) + if (cpu_has_confreg()) + c->cputype = CPU_R3081E; + else + c->cputype = CPU_R3000A; + else + c->cputype = CPU_R3000; + c->isa_level = MIPS_CPU_ISA_I; + c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX | + MIPS_CPU_LLSC; + if (__cpu_has_fpu()) + c->options |= MIPS_CPU_FPU; + c->tlbsize = 64; + break; + case PRID_IMP_R4000: + if ((c->processor_id & 0xff) >= PRID_REV_R4400) + c->cputype = CPU_R4400SC; + else + c->cputype = CPU_R4000SC; + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_WATCH | MIPS_CPU_VCE | + MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + case PRID_IMP_VR41XX: + switch (c->processor_id & 0xf0) { +#ifndef CONFIG_VR4181 + case PRID_REV_VR4111: + c->cputype = CPU_VR4111; + break; +#else + case PRID_REV_VR4181: + c->cputype = CPU_VR4181; + break; +#endif + case PRID_REV_VR4121: + c->cputype = CPU_VR4121; + break; + case PRID_REV_VR4122: + if ((c->processor_id & 0xf) < 0x3) + c->cputype = CPU_VR4122; + else + c->cputype = CPU_VR4181A; + break; + case PRID_REV_VR4131: + c->cputype = CPU_VR4131; + break; + default: + printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); + c->cputype = CPU_VR41XX; + break; + } + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS; + c->tlbsize = 32; + break; + case PRID_IMP_R4300: + c->cputype = CPU_R4300; + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; + c->tlbsize = 32; + break; + case PRID_IMP_R4600: + c->cputype = CPU_R4600; + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + #if 0 + case PRID_IMP_R4650: + /* + * This processor doesn't have an MMU, so it's not + * "real easy" to run Linux on it. It is left purely + * for documentation. Commented out because it shares + * it's c0_prid id number with the TX3900. + */ + c->cputype = CPU_R4650; + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + #endif + case PRID_IMP_TX39: + c->isa_level = MIPS_CPU_ISA_I; + c->options = MIPS_CPU_TLB; + + if ((c->processor_id & 0xf0) == + (PRID_REV_TX3927 & 0xf0)) { + c->cputype = CPU_TX3927; + c->tlbsize = 64; + } else { + switch (c->processor_id & 0xff) { + case PRID_REV_TX3912: + c->cputype = CPU_TX3912; + c->tlbsize = 32; + break; + case PRID_REV_TX3922: + c->cputype = CPU_TX3922; + c->tlbsize = 64; + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } + } + break; + case PRID_IMP_R4700: + c->cputype = CPU_R4700; + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + case PRID_IMP_TX49: + c->cputype = CPU_TX49XX; + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + case PRID_IMP_R5000: + c->cputype = CPU_R5000; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + case PRID_IMP_R5432: + c->cputype = CPU_R5432; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_WATCH | MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + case PRID_IMP_R5500: + c->cputype = CPU_R5500; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_WATCH | MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + case PRID_IMP_NEVADA: + c->cputype = CPU_NEVADA; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_DIVEC | MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + case PRID_IMP_R6000: + c->cputype = CPU_R6000; + c->isa_level = MIPS_CPU_ISA_II; + c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | + MIPS_CPU_LLSC; + c->tlbsize = 32; + break; + case PRID_IMP_R6000A: + c->cputype = CPU_R6000A; + c->isa_level = MIPS_CPU_ISA_II; + c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | + MIPS_CPU_LLSC; + c->tlbsize = 32; + break; + case PRID_IMP_RM7000: + c->cputype = CPU_RM7000; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; + /* + * Undocumented RM7000: Bit 29 in the info register of + * the RM7000 v2.0 indicates if the TLB has 48 or 64 + * entries. + * + * 29 1 => 64 entry JTLB + * 0 => 48 entry JTLB + */ + c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; + break; + case PRID_IMP_R8000: + c->cputype = CPU_R8000; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; + c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ + break; + case PRID_IMP_R10000: + c->cputype = CPU_R10000; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_COUNTER | MIPS_CPU_WATCH | + MIPS_CPU_LLSC; + c->tlbsize = 64; + break; + case PRID_IMP_R12000: + c->cputype = CPU_R12000; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_COUNTER | MIPS_CPU_WATCH | + MIPS_CPU_LLSC; + c->tlbsize = 64; + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } + break; + case PRID_COMP_MIPS: + switch (c->processor_id & 0xff00) { + case PRID_IMP_4KC: + c->cputype = CPU_4KC; + c->isa_level = MIPS_CPU_ISA_M32; + break; + case PRID_IMP_4KEC: + c->cputype = CPU_4KEC; + c->isa_level = MIPS_CPU_ISA_M32; + break; + case PRID_IMP_4KSC: + c->cputype = CPU_4KSC; + c->isa_level = MIPS_CPU_ISA_M32; + break; + case PRID_IMP_5KC: + c->cputype = CPU_5KC; + c->isa_level = MIPS_CPU_ISA_M64; + break; + case PRID_IMP_20KC: + c->cputype = CPU_20KC; + c->isa_level = MIPS_CPU_ISA_M64; + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } + break; + case PRID_COMP_ALCHEMY: + switch (c->processor_id & 0xff00) { + case PRID_IMP_AU1_REV1: + case PRID_IMP_AU1_REV2: + switch ((c->processor_id >> 24) & 0xff) { + case 0: + c->cputype = CPU_AU1000; + break; + case 1: + c->cputype = CPU_AU1500; + break; + case 2: + c->cputype = CPU_AU1100; + break; + default: + panic("Unknown Au Core!"); + break; + } + c->isa_level = MIPS_CPU_ISA_M32; + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } + break; + case PRID_COMP_SIBYTE: + switch (c->processor_id & 0xff00) { + case PRID_IMP_SB1: + c->cputype = CPU_SB1; + c->isa_level = MIPS_CPU_ISA_M64; + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | + MIPS_CPU_MCHECK | MIPS_CPU_EJTAG | + MIPS_CPU_WATCH | MIPS_CPU_LLSC; +#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS + /* FPU in pass1 is known to have issues. */ + c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; +#endif + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } + break; + + case PRID_COMP_SANDCRAFT: + switch (c->processor_id & 0xff00) { + case PRID_IMP_SR71000: + c->cputype = CPU_SR71000; + c->isa_level = MIPS_CPU_ISA_M64; + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + MIPS_CPU_4KTLB | MIPS_CPU_FPU | + MIPS_CPU_COUNTER | MIPS_CPU_MCHECK; + c->scache.ways = 8; + c->tlbsize = 64; + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } + break; + default: + c->cputype = CPU_UNKNOWN; + c->tlbsize = ((config1 >> 25) & 0x3f) + 1; + } + if (c->options & MIPS_CPU_FPU) + c->fpu_id = cpu_get_fpu_id(); +} + +__init void cpu_report(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + + printk("CPU revision is: %08x\n", c->processor_id); + if (c->options & MIPS_CPU_FPU) + printk("FPU revision is: %08x\n", c->fpu_id); +} --- linux-2.5.73/arch/mips64/kernel/entry.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/entry.S 2003-06-27 15:56:23.000000000 -0700 @@ -9,67 +9,88 @@ * Copyright (C) 1999, 2000 Silicon Graphics * Copyright (C) 2001 MIPS Technologies, Inc. */ -#include - #include #include #include #include - -/* This duplicates the definition from */ -#error #define PT_TRACESYS 0x00000002 /* tracing system calls */ +#include #define KU_USER 0x10 .text - .align 4 -FEXPORT(ret_from_fork) - move a0, v0 # prev - jal schedule_tail -#error lw t0, TASK_PTRACE($28) # syscall tracing enabled? -#error andi t0, PT_TRACESYS - bnez t0, tracesys_exit - j ret_from_sys_call - -tracesys_exit: - jal syscall_trace - b ret_from_sys_call - -EXPORT(ret_from_irq) -EXPORT(ret_from_exception) - lw t0, PT_STATUS(sp) # returning to kernel mode? + .align 5 +FEXPORT(ret_from_irq) +FEXPORT(ret_from_exception) + ld t0, PT_STATUS(sp) # returning to kernel mode? andi t0, t0, KU_USER - bnez t0, ret_from_sys_call + beqz t0, restore_all + +FEXPORT(resume_userspace) + mfc0 t0, CP0_STATUS # make sure need_resched and + ori t0, t0, 1 # signals dont change between + xori t0, t0, 1 # sampling and return + SSNOP; SSNOP; SSNOP + + LONG_L a2, TI_FLAGS($28) + andi a2, _TIF_WORK_MASK # current->work (ignoring + # syscall_trace + bnez a2, work_pending j restore_all -reschedule: jal schedule +FEXPORT(ret_from_fork) + jal schedule_tail -FEXPORT(ret_from_sys_call) - mfc0 t0, CP0_STATUS # need_resched and signals atomic test - ori t0, t0, 1 - xori t0, t0, 1 +FEXPORT(syscall_exit) + mfc0 t0, CP0_STATUS # make sure need_resched and + ori t0, t0, 1 # signals dont change between + xori t0, t0, 1 # sampling and return mtc0 t0, CP0_STATUS + SSNOP; SSNOP; SSNOP -#error ld v0, TASK_NEED_RESCHED($28) -#error lw v1, TASK_SIGPENDING($28) - bnez v0, reschedule - bnez v1, signal_return + LONG_L a2, TI_FLAGS($28) # current->work + bnez a2, syscall_exit_work -restore_all: .set noat +restore_all: + .set noat RESTORE_ALL eret .set at -signal_return: .type signal_return, @function +work_pending: + bltz a2, work_notifysig # current->work.need_resched + # test high 8 bits +work_resched: + jal schedule + + mfc0 t0, CP0_STATUS # make sure need_resched and + ori t0, t0, 1 # signals dont change between + xori t0, t0, 1 # sampling and return + mtc0 t0, CP0_STATUS + SSNOP; SSNOP; SSNOP + + LONG_L a2, TI_FLAGS($28) # This also converts into + # a union of four chars + andi a2, _TIF_WORK_MASK # is there any work to be done + # other than syscall tracing? + beqz a2, restore_all + andi t0, a2, _TIF_NEED_RESCHED + bnez t0, work_notifysig + +work_notifysig: # deal with pending signals and + # notify-resume requests + move a0, sp + li a1, 0 + jal do_notify_resume # a2 already loaded + j restore_all - mfc0 t0, CP0_STATUS +FEXPORT(syscall_exit_work) + LONG_L t0, TI_FLAGS($28) # current->work.syscall_trace + bgez t0, work_pending + mfc0 t0, CP0_STATUS # sti ori t0, t0, 1 mtc0 t0, CP0_STATUS - - move a0, zero - move a1, sp - jal do_signal - b restore_all + jal do_syscall_trace + b resume_userspace /* * Common spurious interrupt handler. @@ -81,9 +102,10 @@ LEAF(spurious_interrupt) * Someone tried to fool us by sending an interrupt but we * couldn't find a cause for it. */ - lui t1,%hi(spurious_count) - lw t0,%lo(spurious_count)(t1) - addiu t0,1 - sw t0,%lo(spurious_count)(t1) + lui t1, %hi(irq_err_count) +1: ll t0, %lo(irq_err_count)(t1) + addiu t0, 1 + sc t0, %lo(irq_err_count)(t1) + beqz t0, 1b j ret_from_irq END(spurious_interrupt) --- linux-2.5.73/arch/mips64/kernel/head.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/head.S 2003-06-27 15:56:23.000000000 -0700 @@ -10,7 +10,6 @@ * Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999 Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. */ -#define __ASSEMBLY__ #include #include #include @@ -27,7 +26,7 @@ #if defined(CONFIG_ARC64) || defined(CONFIG_MAPPED_KERNEL) /* We get launched at a XKPHYS address but the kernel is linked to run at a KSEG0 address, so jump there. */ - la t0, \@f + PTR_LA t0, \@f jr t0 \@: #endif @@ -35,13 +34,13 @@ #ifdef CONFIG_SGI_IP27 /* - * outputs the local nasid into t1. + * outputs the local nasid into res. IP27 stuff. */ - .macro GET_NASID_ASM - dli t1, LOCAL_HUB_ADDR(NI_STATUS_REV_ID) - ld t1, (t1) - and t1, NSRI_NODEID_MASK - dsrl t1, NSRI_NODEID_SHFT + .macro GET_NASID_ASM res + dli \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID) + ld \res, (\res) + and \res, NSRI_NODEID_MASK + dsrl \res, NSRI_NODEID_SHFT .endm #endif /* CONFIG_SGI_IP27 */ @@ -97,7 +96,7 @@ NESTED(kernel_entry, 16, sp) # kernel xori sp, 0xf #ifdef CONFIG_SGI_IP27 - GET_NASID_ASM + GET_NASID_ASM t1 move t2, t1 # text and data are here MAPPED_KERNEL_SETUP_TLB #endif /* IP27 */ @@ -106,39 +105,39 @@ NESTED(kernel_entry, 16, sp) # kernel CLI # disable interrupts - mfc0 t0, CP0_STATUS + PTR_LA $28, init_thread_union # init current pointer + daddiu sp, $28, KERNEL_STACK_SIZE-32 + set_saved_sp sp, t0, t1 + /* - * On IP27, I am seeing the TS bit set when the - * kernel is loaded. Maybe because the kernel is - * in ckseg0 and not xkphys? Clear it anyway ... + * The firmware/bootloader passes argc/argp/envp + * to us as arguments. But clear bss first because + * the romvec and other important info is stored there + * by prom_init(). */ - li t1, ~(ST0_TS|ST0_CU1|ST0_CU2|ST0_CU3) - and t0, t1 - or t0, (ST0_CU0|ST0_KX|ST0_SX|ST0_FR) # Bogosity: cu0 indicates kernel - mtc0 t0, CP0_STATUS # thread in copy_thread. - - la $28, init_task_union # init current pointer - daddiu t0, $28, KERNEL_STACK_SIZE-32 - sd t0, kernelsp - dsubu sp, t0, 4*SZREG # init stack pointer - move t0, $28 -#ifdef CONFIG_SMP - mtc0 t0, CP0_WATCHLO - dsrl32 t0, t0, 0 - mtc0 t0, CP0_WATCHHI -#endif - /* Note that all firmware passed argument registers still - have their values. */ - jal prom_init # initialize firmware + PTR_LA t0, __bss_start + sd zero, (t0) + PTR_LA t1, __bss_stop - 8 +1: + daddiu t0, 8 + sd zero, (t0) + bne t0, t1, 1b + + dsubu sp, 4*SZREG # init stack pointer - jal start_kernel -1: b 1b # just in case ... + j init_arch END(kernel_entry) +#ifdef CONFIG_SMP +/* + * SMP slave cpus entry point. Board specific code for bootstrap calls this + * function after setting up the stack and gp registers. + */ +NESTED(smp_bootstrap, 16, sp) #ifdef CONFIG_SGI_IP27 -NESTED(bootstrap, 16, sp) - GET_NASID_ASM - li t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + KLDIR_OFF_POINTER + K0BASE + GET_NASID_ASM t1 + li t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \ + KLDIR_OFF_POINTER + K0BASE dsll t1, NASID_SHFT or t0, t0, t1 ld t0, 0(t0) # t0 points to kern_vars struct @@ -146,19 +145,27 @@ NESTED(bootstrap, 16, sp) lh t2, KV_RW_NASID_OFFSET(t0) MAPPED_KERNEL_SETUP_TLB ARC64_TWIDDLE_PC - CLI - mfc0 t0, CP0_STATUS - li t1, ~(ST0_CU1|ST0_CU2|ST0_CU3) - and t0, t1 - or t0, (ST0_CU0|ST0_KX|ST0_SX|ST0_FR) # Bogosity: cu0 indicates kernel - mtc0 t0, CP0_STATUS # thread in copy_thread. - jal cboot - END(bootstrap) #endif /* CONFIG_SGI_IP27 */ + CLI + + /* + * For the moment set ST0_KU so the CPU will not spit fire when + * executing 64-bit instructions. The full initialization of the + * CPU's status register is done later in per_cpu_trap_init(). + */ + mfc0 t0, CP0_STATUS + or t0, ST0_KX + mtc0 t0, CP0_STATUS + + jal start_secondary + + END(smp_bootstrap) +#endif /* CONFIG_SMP */ + __FINIT - .comm kernelsp, 8, 8 # current stackpointer + declare_saved_sp #undef PAGE_SIZE #define PAGE_SIZE 0x1000 @@ -171,12 +178,12 @@ NESTED(bootstrap, 16, sp) .endm .data - .align 12 + .align PAGE_SHIFT page swapper_pg_dir, 1 page invalid_pte_table, 0 page invalid_pmd_table, 1 - page kptbl, KPTBL_PAGE_ORDER + page kptbl, _PGD_ORDER .globl ekptbl page kpmdtbl, 0 ekptbl: --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/kernel/i8259.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,336 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Code to handle x86 style IRQs plus some generic interrupt stuff. + * + * Copyright (C) 1992 Linus Torvalds + * Copyright (C) 1994 - 2000 Ralf Baechle + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +void enable_8259A_irq(unsigned int irq); +void disable_8259A_irq(unsigned int irq); + +/* + * This is the 'legacy' 8259A Programmable Interrupt Controller, + * present in the majority of PC/AT boxes. + * plus some generic x86 specific things if generic specifics makes + * any sense at all. + * this file should become arch/i386/kernel/irq.c when the old irq.c + * moves to arch independent land + */ + +static spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED; + +static void end_8259A_irq (unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) && + irq_desc[irq].action) + enable_8259A_irq(irq); +} + +#define shutdown_8259A_irq disable_8259A_irq + +void mask_and_ack_8259A(unsigned int); + +static unsigned int startup_8259A_irq(unsigned int irq) +{ + enable_8259A_irq(irq); + + return 0; /* never anything pending */ +} + +static struct hw_interrupt_type i8259A_irq_type = { + "XT-PIC", + startup_8259A_irq, + shutdown_8259A_irq, + enable_8259A_irq, + disable_8259A_irq, + mask_and_ack_8259A, + end_8259A_irq, + NULL +}; + +/* + * 8259A PIC functions to handle ISA devices: + */ + +/* + * This contains the irq mask for both 8259A irq controllers, + */ +static unsigned int cached_irq_mask = 0xffff; + +#define cached_21 (cached_irq_mask) +#define cached_A1 (cached_irq_mask >> 8) + +void disable_8259A_irq(unsigned int irq) +{ + unsigned int mask = 1 << irq; + unsigned long flags; + + spin_lock_irqsave(&i8259A_lock, flags); + cached_irq_mask |= mask; + if (irq & 8) + outb(cached_A1,0xA1); + else + outb(cached_21,0x21); + spin_unlock_irqrestore(&i8259A_lock, flags); +} + +void enable_8259A_irq(unsigned int irq) +{ + unsigned int mask = ~(1 << irq); + unsigned long flags; + + spin_lock_irqsave(&i8259A_lock, flags); + cached_irq_mask &= mask; + if (irq & 8) + outb(cached_A1,0xA1); + else + outb(cached_21,0x21); + spin_unlock_irqrestore(&i8259A_lock, flags); +} + +int i8259A_irq_pending(unsigned int irq) +{ + unsigned int mask = 1 << irq; + unsigned long flags; + int ret; + + spin_lock_irqsave(&i8259A_lock, flags); + if (irq < 8) + ret = inb(0x20) & mask; + else + ret = inb(0xA0) & (mask >> 8); + spin_unlock_irqrestore(&i8259A_lock, flags); + + return ret; +} + +void make_8259A_irq(unsigned int irq) +{ + disable_irq_nosync(irq); + irq_desc[irq].handler = &i8259A_irq_type; + enable_irq(irq); +} + +/* + * This function assumes to be called rarely. Switching between + * 8259A registers is slow. + * This has to be protected by the irq controller spinlock + * before being called. + */ +static inline int i8259A_irq_real(unsigned int irq) +{ + int value; + int irqmask = 1 << irq; + + if (irq < 8) { + outb(0x0B,0x20); /* ISR register */ + value = inb(0x20) & irqmask; + outb(0x0A,0x20); /* back to the IRR register */ + return value; + } + outb(0x0B,0xA0); /* ISR register */ + value = inb(0xA0) & (irqmask >> 8); + outb(0x0A,0xA0); /* back to the IRR register */ + return value; +} + +/* + * Careful! The 8259A is a fragile beast, it pretty + * much _has_ to be done exactly like this (mask it + * first, _then_ send the EOI, and the order of EOI + * to the two 8259s is important! + */ +void mask_and_ack_8259A(unsigned int irq) +{ + unsigned int irqmask = 1 << irq; + unsigned long flags; + + spin_lock_irqsave(&i8259A_lock, flags); + /* + * Lightweight spurious IRQ detection. We do not want to overdo + * spurious IRQ handling - it's usually a sign of hardware problems, so + * we only do the checks we can do without slowing down good hardware + * nnecesserily. + * + * Note that IRQ7 and IRQ15 (the two spurious IRQs usually resulting + * rom the 8259A-1|2 PICs) occur even if the IRQ is masked in the 8259A. + * Thus we can check spurious 8259A IRQs without doing the quite slow + * i8259A_irq_real() call for every IRQ. This does not cover 100% of + * spurious interrupts, but should be enough to warn the user that + * there is something bad going on ... + */ + if (cached_irq_mask & irqmask) + goto spurious_8259A_irq; + cached_irq_mask |= irqmask; + +handle_real_irq: + if (irq & 8) { + inb(0xA1); /* DUMMY - (do we need this?) */ + outb(cached_A1,0xA1); + outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */ + outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */ + } else { + inb(0x21); /* DUMMY - (do we need this?) */ + outb(cached_21,0x21); + outb(0x60+irq,0x20); /* 'Specific EOI' to master */ + } + spin_unlock_irqrestore(&i8259A_lock, flags); + return; + +spurious_8259A_irq: + /* + * this is the slow path - should happen rarely. + */ + if (i8259A_irq_real(irq)) + /* + * oops, the IRQ _is_ in service according to the + * 8259A - not spurious, go handle it. + */ + goto handle_real_irq; + + { + static int spurious_irq_mask = 0; + /* + * At this point we can be sure the IRQ is spurious, + * lets ACK and report it. [once per IRQ] + */ + if (!(spurious_irq_mask & irqmask)) { + printk("spurious 8259A interrupt: IRQ%d.\n", irq); + spurious_irq_mask |= irqmask; + } + atomic_inc(&irq_err_count); + /* + * Theoretically we do not have to handle this IRQ, + * but in Linux this does not cause problems and is + * simpler for us. + */ + goto handle_real_irq; + } +} + +static int i8259A_resume(struct sys_device *dev) +{ + init_8259A(0); + return 0; +} + +static struct sysdev_class i8259_sysdev_class = { + set_kset_name("i8259"), + .resume = i8259A_resume, +}; + +static struct sys_device device_i8259A = { + .id = 0, + .cls = &i8259_sysdev_class, +}; + +static int __init i8259A_init_sysfs(void) +{ + int error = sysdev_class_register(&i8259_sysdev_class); + if (!error) + error = sys_device_register(&device_i8259A); + return error; +} + +device_initcall(i8259A_init_sysfs); + +void __init init_8259A(int auto_eoi) +{ + unsigned long flags; + + spin_lock_irqsave(&i8259A_lock, flags); + + outb(0xff, 0x21); /* mask all of 8259A-1 */ + outb(0xff, 0xA1); /* mask all of 8259A-2 */ + + /* + * outb_p - this has to work on a wide range of PC hardware. + */ + outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */ + outb_p(0x00, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x00-0x07 */ + outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */ + if (auto_eoi) + outb_p(0x03, 0x21); /* master does Auto EOI */ + else + outb_p(0x01, 0x21); /* master expects normal EOI */ + + outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */ + outb_p(0x08, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x08-0x0f */ + outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */ + outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode + is to be investigated) */ + + if (auto_eoi) + /* + * in AEOI mode we just have to mask the interrupt + * when acking. + */ + i8259A_irq_type.ack = disable_8259A_irq; + else + i8259A_irq_type.ack = mask_and_ack_8259A; + + udelay(100); /* wait for 8259A to initialize */ + + outb(cached_21, 0x21); /* restore master IRQ mask */ + outb(cached_A1, 0xA1); /* restore slave IRQ mask */ + + spin_unlock_irqrestore(&i8259A_lock, flags); +} + +asmlinkage void i8259_do_irq(int irq, struct pt_regs regs) +{ + panic("i8259_do_irq: I want to be implemented"); +} + +/* + * IRQ2 is cascade interrupt to second interrupt controller + */ +static struct irqaction irq2 = { + no_action, 0, 0, "cascade", NULL, NULL +}; + +static struct resource pic1_io_resource = { + "pic1", 0x20, 0x3f, IORESOURCE_BUSY +}; + +static struct resource pic2_io_resource = { + "pic2", 0xa0, 0xbf, IORESOURCE_BUSY +}; + +/* + * On systems with i8259-style interrupt controllers we assume for + * driver compatibility reasons interrupts 0 - 15 to be the i8295 + * interrupts even if the hardware uses a different interrupt numbering. + */ +void __init init_i8259_irqs (void) +{ + int i; + + request_resource(&ioport_resource, &pic1_io_resource); + request_resource(&ioport_resource, &pic2_io_resource); + + init_8259A(0); + + for (i = 0; i < 16; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &i8259A_irq_type; + } + + setup_irq(2, &irq2); +} --- linux-2.5.73/arch/mips64/kernel/init_task.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/init_task.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,17 +1,19 @@ #include #include #include +#include #include #include static struct fs_struct init_fs = INIT_FS; static struct files_struct init_files = INIT_FILES; -static struct signal_struct init_signals = INIT_SIGNALS; +static struct signal_struct init_signals = INIT_SIGNALS(init_signals); +static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); struct mm_struct init_mm = INIT_MM(init_mm); /* - * Initial task structure. + * Initial thread structure. * * We need to make sure that this is 8192-byte aligned due to the * way process stacks are handled. This is done by making sure @@ -20,6 +22,13 @@ struct mm_struct init_mm = INIT_MM(init_ * * The things we do for performance.. */ -union task_union init_task_union +union thread_union init_thread_union __attribute__((__section__(".data.init_task"))) = - { INIT_TASK(init_task_union.task) }; + { INIT_THREAD_INFO(init_task) }; + +/* + * Initial task structure. + * + * All other task structs will be allocated on slabs in fork.c + */ +struct task_struct init_task = INIT_TASK(init_task); --- linux-2.5.73/arch/mips64/kernel/ioctl32.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/ioctl32.c 2003-06-27 15:56:23.000000000 -0700 @@ -4,33 +4,95 @@ * Copyright (C) 2000 Silicon Graphics, Inc. * Written by Ulf Carlsson (ulfc@engr.sgi.com) * Copyright (C) 2000 Ralf Baechle + * Copyright (C) 2002 Maciej W. Rozycki * * Mostly stolen from the sparc64 ioctl32 implementation. */ #include #include #include +#include #include -#include #include +#include #include #include +#include +#include +#include +#include #include +#include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include #include +#include +#include #include +#include +#include +#include #include #include +#include #include #include #include -#include -#include -#include +#include +#include #include -#include -#include + +#include +#undef __KERNEL__ /* This file was born to be ugly ... */ +#include +#define __KERNEL__ +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SIBYTE_TBPROF +#include +#endif long sys_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg); @@ -39,7 +101,7 @@ static int w_long(unsigned int fd, unsig mm_segment_t old_fs = get_fs(); int err; unsigned long val; - + set_fs (KERNEL_DS); err = sys_ioctl(fd, cmd, (unsigned long)&val); set_fs (old_fs); @@ -66,6 +128,166 @@ static int rw_long(unsigned int fd, unsi #define A(__x) ((unsigned long)(__x)) + +#ifdef CONFIG_FB + +struct fb_fix_screeninfo32 { + char id[16]; /* identification string eg "TT Builtin" */ + __u32 smem_start; /* Start of frame buffer mem */ + /* (physical address) */ + __u32 smem_len; /* Length of frame buffer mem */ + __u32 type; /* see FB_TYPE_* */ + __u32 type_aux; /* Interleave for interleaved Planes */ + __u32 visual; /* see FB_VISUAL_* */ + __u16 xpanstep; /* zero if no hardware panning */ + __u16 ypanstep; /* zero if no hardware panning */ + __u16 ywrapstep; /* zero if no hardware ywrap */ + __u32 line_length; /* length of a line in bytes */ + __u32 mmio_start; /* Start of Memory Mapped I/O */ + /* (physical address) */ + __u32 mmio_len; /* Length of Memory Mapped I/O */ + __u32 accel; /* Type of acceleration available */ + __u16 reserved[3]; /* Reserved for future compatibility */ +}; + +static int do_fbioget_fscreeninfo_ioctl(unsigned int fd, unsigned int cmd, + unsigned long arg) +{ + mm_segment_t old_fs = get_fs(); + struct fb_fix_screeninfo fix; + struct fb_fix_screeninfo32 *fix32 = (struct fb_fix_screeninfo32 *)arg; + int err; + + set_fs(KERNEL_DS); + err = sys_ioctl(fd, cmd, (unsigned long)&fix); + set_fs(old_fs); + + if (err == 0) { + err = __copy_to_user((char *)fix32->id, (char *)fix.id, + sizeof(fix.id)); + err |= __put_user((__u32)(unsigned long)fix.smem_start, + &fix32->smem_start); + err |= __put_user(fix.smem_len, &fix32->smem_len); + err |= __put_user(fix.type, &fix32->type); + err |= __put_user(fix.type_aux, &fix32->type_aux); + err |= __put_user(fix.visual, &fix32->visual); + err |= __put_user(fix.xpanstep, &fix32->xpanstep); + err |= __put_user(fix.ypanstep, &fix32->ypanstep); + err |= __put_user(fix.ywrapstep, &fix32->ywrapstep); + err |= __put_user(fix.line_length, &fix32->line_length); + err |= __put_user((__u32)(unsigned long)fix.mmio_start, + &fix32->mmio_start); + err |= __put_user(fix.mmio_len, &fix32->mmio_len); + err |= __put_user(fix.accel, &fix32->accel); + err |= __copy_to_user((char *)fix32->reserved, + (char *)fix.reserved, + sizeof(fix.reserved)); + if (err) + err = -EFAULT; + } + + return err; +} + +struct fb_cmap32 { + __u32 start; /* First entry */ + __u32 len; /* Number of entries */ + __u32 red; /* Red values */ + __u32 green; + __u32 blue; + __u32 transp; /* transparency, can be NULL */ +}; + +static int do_fbiocmap_ioctl(unsigned int fd, unsigned int cmd, + unsigned long arg) +{ + mm_segment_t old_fs = get_fs(); + u32 red = 0, green = 0, blue = 0, transp = 0; + struct fb_cmap cmap; + struct fb_cmap32 *cmap32 = (struct fb_cmap32 *)arg; + int err; + + memset(&cmap, 0, sizeof(cmap)); + + err = __get_user(cmap.start, &cmap32->start); + err |= __get_user(cmap.len, &cmap32->len); + err |= __get_user(red, &cmap32->red); + err |= __get_user(green, &cmap32->green); + err |= __get_user(blue, &cmap32->blue); + err |= __get_user(transp, &cmap32->transp); + if (err) + return -EFAULT; + + err = -ENOMEM; + cmap.red = kmalloc(cmap.len * sizeof(__u16), GFP_KERNEL); + if (!cmap.red) + goto out; + cmap.green = kmalloc(cmap.len * sizeof(__u16), GFP_KERNEL); + if (!cmap.green) + goto out; + cmap.blue = kmalloc(cmap.len * sizeof(__u16), GFP_KERNEL); + if (!cmap.blue) + goto out; + if (transp) { + cmap.transp = kmalloc(cmap.len * sizeof(__u16), GFP_KERNEL); + if (!cmap.transp) + goto out; + } + + if (cmd == FBIOPUTCMAP) { + err = __copy_from_user(cmap.red, (char *)A(red), + cmap.len * sizeof(__u16)); + err |= __copy_from_user(cmap.green, (char *)A(green), + cmap.len * sizeof(__u16)); + err |= __copy_from_user(cmap.blue, (char *)A(blue), + cmap.len * sizeof(__u16)); + if (cmap.transp) + err |= __copy_from_user(cmap.transp, (char *)A(transp), + cmap.len * sizeof(__u16)); + if (err) { + err = -EFAULT; + goto out; + } + } + + set_fs(KERNEL_DS); + err = sys_ioctl(fd, cmd, (unsigned long)&cmap); + set_fs(old_fs); + if (err) + goto out; + + if (cmd == FBIOGETCMAP) { + err = __copy_to_user((char *)A(red), cmap.red, + cmap.len * sizeof(__u16)); + err |= __copy_to_user((char *)A(green), cmap.blue, + cmap.len * sizeof(__u16)); + err |= __copy_to_user((char *)A(blue), cmap.blue, + cmap.len * sizeof(__u16)); + if (cmap.transp) + err |= __copy_to_user((char *)A(transp), cmap.transp, + cmap.len * sizeof(__u16)); + if (err) { + err = -EFAULT; + goto out; + } + } + +out: + if (cmap.red) + kfree(cmap.red); + if (cmap.green) + kfree(cmap.green); + if (cmap.blue) + kfree(cmap.blue); + if (cmap.transp) + kfree(cmap.transp); + + return err; +} + +#endif /* CONFIG_FB */ + + static int do_siocgstamp(unsigned int fd, unsigned int cmd, unsigned long arg) { struct compat_timeval *up = (struct compat_timeval *)arg; @@ -190,7 +412,7 @@ static inline int dev_ifconf(unsigned in old_fs = get_fs(); set_fs (KERNEL_DS); - err = sys_ioctl (fd, SIOCGIFCONF, (unsigned long)&ifc); + err = sys_ioctl (fd, SIOCGIFCONF, (unsigned long)&ifc); set_fs (old_fs); if (err) goto out; @@ -217,28 +439,52 @@ out: return err; } -static inline int dev_ifsioc(unsigned int fd, unsigned int cmd, - unsigned long arg) +int siocdevprivate_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg) +{ + struct ifreq *u_ifreq64; + struct ifreq32 *u_ifreq32 = (struct ifreq32 *) arg; + char tmp_buf[IFNAMSIZ]; + void *data64; + u32 data32; + + if (copy_from_user(&tmp_buf[0], &(u_ifreq32->ifr_ifrn.ifrn_name[0]), + IFNAMSIZ)) + return -EFAULT; + if (__get_user(data32, &u_ifreq32->ifr_ifru.ifru_data)) + return -EFAULT; + data64 = (void *) A(data32); + + u_ifreq64 = compat_alloc_user_space(sizeof(*u_ifreq64)); + + /* Don't check these user accesses, just let that get trapped + * in the ioctl handler instead. + */ + copy_to_user(&u_ifreq64->ifr_ifrn.ifrn_name[0], &tmp_buf[0], IFNAMSIZ); + __put_user(data64, &u_ifreq64->ifr_ifru.ifru_data); + + return sys_ioctl(fd, cmd, (unsigned long) u_ifreq64); +} + +static int dev_ifsioc(unsigned int fd, unsigned int cmd, unsigned long arg) { - struct ifreq32 *uifr = (struct ifreq32 *)arg; struct ifreq ifr; mm_segment_t old_fs; int err; switch (cmd) { case SIOCSIFMAP: - err = copy_from_user(&ifr, uifr, sizeof(ifr.ifr_name)); - err |= __get_user(ifr.ifr_map.mem_start, &(uifr->ifr_ifru.ifru_map.mem_start)); - err |= __get_user(ifr.ifr_map.mem_end, &(uifr->ifr_ifru.ifru_map.mem_end)); - err |= __get_user(ifr.ifr_map.base_addr, &(uifr->ifr_ifru.ifru_map.base_addr)); - err |= __get_user(ifr.ifr_map.irq, &(uifr->ifr_ifru.ifru_map.irq)); - err |= __get_user(ifr.ifr_map.dma, &(uifr->ifr_ifru.ifru_map.dma)); - err |= __get_user(ifr.ifr_map.port, &(uifr->ifr_ifru.ifru_map.port)); + err = copy_from_user(&ifr, (struct ifreq32 *)arg, sizeof(ifr.ifr_name)); + err |= __get_user(ifr.ifr_map.mem_start, &(((struct ifreq32 *)arg)->ifr_ifru.ifru_map.mem_start)); + err |= __get_user(ifr.ifr_map.mem_end, &(((struct ifreq32 *)arg)->ifr_ifru.ifru_map.mem_end)); + err |= __get_user(ifr.ifr_map.base_addr, &(((struct ifreq32 *)arg)->ifr_ifru.ifru_map.base_addr)); + err |= __get_user(ifr.ifr_map.irq, &(((struct ifreq32 *)arg)->ifr_ifru.ifru_map.irq)); + err |= __get_user(ifr.ifr_map.dma, &(((struct ifreq32 *)arg)->ifr_ifru.ifru_map.dma)); + err |= __get_user(ifr.ifr_map.port, &(((struct ifreq32 *)arg)->ifr_ifru.ifru_map.port)); if (err) return -EFAULT; break; default: - if (copy_from_user(&ifr, uifr, sizeof(struct ifreq32))) + if (copy_from_user(&ifr, (struct ifreq32 *)arg, sizeof(struct ifreq32))) return -EFAULT; break; } @@ -259,17 +505,17 @@ static inline int dev_ifsioc(unsigned in case SIOCGIFDSTADDR: case SIOCGIFNETMASK: case SIOCGIFTXQLEN: - if (copy_to_user(uifr, &ifr, sizeof(struct ifreq32))) + if (copy_to_user((struct ifreq32 *)arg, &ifr, sizeof(struct ifreq32))) return -EFAULT; break; case SIOCGIFMAP: - err = copy_to_user(uifr, &ifr, sizeof(ifr.ifr_name)); - err |= __put_user(ifr.ifr_map.mem_start, &(uifr->ifr_ifru.ifru_map.mem_start)); - err |= __put_user(ifr.ifr_map.mem_end, &(uifr->ifr_ifru.ifru_map.mem_end)); - err |= __put_user(ifr.ifr_map.base_addr, &(uifr->ifr_ifru.ifru_map.base_addr)); - err |= __put_user(ifr.ifr_map.irq, &(uifr->ifr_ifru.ifru_map.irq)); - err |= __put_user(ifr.ifr_map.dma, &(uifr->ifr_ifru.ifru_map.dma)); - err |= __put_user(ifr.ifr_map.port, &(uifr->ifr_ifru.ifru_map.port)); + err = copy_to_user((struct ifreq32 *)arg, &ifr, sizeof(ifr.ifr_name)); + err |= __put_user(ifr.ifr_map.mem_start, &(((struct ifreq32 *)arg)->ifr_ifru.ifru_map.mem_start)); + err |= __put_user(ifr.ifr_map.mem_end, &(((struct ifreq32 *)arg)->ifr_ifru.ifru_map.mem_end)); + err |= __put_user(ifr.ifr_map.base_addr, &(((struct ifreq32 *)arg)->ifr_ifru.ifru_map.base_addr)); + err |= __put_user(ifr.ifr_map.irq, &(((struct ifreq32 *)arg)->ifr_ifru.ifru_map.irq)); + err |= __put_user(ifr.ifr_map.dma, &(((struct ifreq32 *)arg)->ifr_ifru.ifru_map.dma)); + err |= __put_user(ifr.ifr_map.port, &(((struct ifreq32 *)arg)->ifr_ifru.ifru_map.port)); if (err) err = -EFAULT; break; @@ -306,7 +552,7 @@ static inline int routing_ioctl(unsigned u32 rtdev; int ret; mm_segment_t old_fs = get_fs(); - + ret = copy_from_user (&r.rt_dst, &(ur->rt_dst), 3 * sizeof(struct sockaddr)); ret |= __get_user (r.rt_flags, &(ur->rt_flags)); ret |= __get_user (r.rt_metric, &(ur->rt_metric)); @@ -404,7 +650,7 @@ static int blkpg_ioctl_trans(unsigned in struct blkpg_partition p; int err; mm_segment_t old_fs = get_fs(); - + err = get_user(a.op, &arg->op); err |= __get_user(a.flags, &arg->flags); err |= __get_user(a.datalen, &arg->datalen); @@ -423,7 +669,7 @@ static int blkpg_ioctl_trans(unsigned in set_fs (old_fs); default: return -EINVAL; - } + } return err; } @@ -557,235 +803,356 @@ static int ioc_settimeout(unsigned int f return rw_long(fd, AUTOFS_IOC_SETTIMEOUT, arg); } -struct ioctl32_handler { - unsigned int cmd; - int (*function)(unsigned int, unsigned int, unsigned long); -}; - -struct ioctl32_list { - struct ioctl32_handler handler; - struct ioctl32_list *next; -}; - -#define IOCTL32_DEFAULT(cmd) { { cmd, (void *) sys_ioctl }, 0 } -#define IOCTL32_HANDLER(cmd, handler) { { cmd, (void *) handler }, 0 } - -static struct ioctl32_list ioctl32_handler_table[] = { - IOCTL32_DEFAULT(TCGETA), - IOCTL32_DEFAULT(TCSETA), - IOCTL32_DEFAULT(TCSETAW), - IOCTL32_DEFAULT(TCSETAF), - IOCTL32_DEFAULT(TCSBRK), - IOCTL32_DEFAULT(TCXONC), - IOCTL32_DEFAULT(TCFLSH), - IOCTL32_DEFAULT(TCGETS), - IOCTL32_DEFAULT(TCSETS), - IOCTL32_DEFAULT(TCSETSW), - IOCTL32_DEFAULT(TCSETSF), - IOCTL32_DEFAULT(TIOCLINUX), - - IOCTL32_DEFAULT(TIOCGETD), - IOCTL32_DEFAULT(TIOCSETD), - IOCTL32_DEFAULT(TIOCEXCL), - IOCTL32_DEFAULT(TIOCNXCL), - IOCTL32_DEFAULT(TIOCCONS), - IOCTL32_DEFAULT(TIOCGSOFTCAR), - IOCTL32_DEFAULT(TIOCSSOFTCAR), - IOCTL32_DEFAULT(TIOCSWINSZ), - IOCTL32_DEFAULT(TIOCGWINSZ), - IOCTL32_DEFAULT(TIOCMGET), - IOCTL32_DEFAULT(TIOCMBIC), - IOCTL32_DEFAULT(TIOCMBIS), - IOCTL32_DEFAULT(TIOCMSET), - IOCTL32_DEFAULT(TIOCPKT), - IOCTL32_DEFAULT(TIOCNOTTY), - IOCTL32_DEFAULT(TIOCSTI), - IOCTL32_DEFAULT(TIOCOUTQ), - IOCTL32_DEFAULT(TIOCSPGRP), - IOCTL32_DEFAULT(TIOCGPGRP), - IOCTL32_DEFAULT(TIOCSCTTY), - IOCTL32_DEFAULT(TIOCGPTN), - IOCTL32_DEFAULT(TIOCSPTLCK), - IOCTL32_DEFAULT(TIOCGSERIAL), - IOCTL32_DEFAULT(TIOCSSERIAL), - IOCTL32_DEFAULT(TIOCSERGETLSR), - - IOCTL32_DEFAULT(FIOCLEX), - IOCTL32_DEFAULT(FIONCLEX), - IOCTL32_DEFAULT(FIOASYNC), - IOCTL32_DEFAULT(FIONBIO), - IOCTL32_DEFAULT(FIONREAD), - - IOCTL32_DEFAULT(PIO_FONT), - IOCTL32_DEFAULT(GIO_FONT), - IOCTL32_DEFAULT(KDSIGACCEPT), - IOCTL32_DEFAULT(KDGETKEYCODE), - IOCTL32_DEFAULT(KDSETKEYCODE), - IOCTL32_DEFAULT(KIOCSOUND), - IOCTL32_DEFAULT(KDMKTONE), - IOCTL32_DEFAULT(KDGKBTYPE), - IOCTL32_DEFAULT(KDSETMODE), - IOCTL32_DEFAULT(KDGETMODE), - IOCTL32_DEFAULT(KDSKBMODE), - IOCTL32_DEFAULT(KDGKBMODE), - IOCTL32_DEFAULT(KDSKBMETA), - IOCTL32_DEFAULT(KDGKBMETA), - IOCTL32_DEFAULT(KDGKBENT), - IOCTL32_DEFAULT(KDSKBENT), - IOCTL32_DEFAULT(KDGKBSENT), - IOCTL32_DEFAULT(KDSKBSENT), - IOCTL32_DEFAULT(KDGKBDIACR), - IOCTL32_DEFAULT(KDSKBDIACR), - IOCTL32_DEFAULT(KDGKBLED), - IOCTL32_DEFAULT(KDSKBLED), - IOCTL32_DEFAULT(KDGETLED), - IOCTL32_DEFAULT(KDSETLED), - IOCTL32_DEFAULT(GIO_SCRNMAP), - IOCTL32_DEFAULT(PIO_SCRNMAP), - IOCTL32_DEFAULT(GIO_UNISCRNMAP), - IOCTL32_DEFAULT(PIO_UNISCRNMAP), - IOCTL32_DEFAULT(PIO_FONTRESET), - IOCTL32_DEFAULT(PIO_UNIMAPCLR), - - IOCTL32_DEFAULT(VT_SETMODE), - IOCTL32_DEFAULT(VT_GETMODE), - IOCTL32_DEFAULT(VT_GETSTATE), - IOCTL32_DEFAULT(VT_OPENQRY), - IOCTL32_DEFAULT(VT_ACTIVATE), - IOCTL32_DEFAULT(VT_WAITACTIVE), - IOCTL32_DEFAULT(VT_RELDISP), - IOCTL32_DEFAULT(VT_DISALLOCATE), - IOCTL32_DEFAULT(VT_RESIZE), - IOCTL32_DEFAULT(VT_RESIZEX), - IOCTL32_DEFAULT(VT_LOCKSWITCH), - IOCTL32_DEFAULT(VT_UNLOCKSWITCH), +typedef int (* ioctl32_handler_t)(unsigned int, unsigned int, unsigned long, struct file *); + +#define COMPATIBLE_IOCTL(cmd) HANDLE_IOCTL((cmd),sys_ioctl) +#define HANDLE_IOCTL(cmd,handler) { (cmd), (ioctl32_handler_t)(handler), NULL }, +#define IOCTL_TABLE_START \ + struct ioctl_trans ioctl_start[] = { +#define IOCTL_TABLE_END \ + }; struct ioctl_trans ioctl_end[0]; + + +IOCTL_TABLE_START +#include +COMPATIBLE_IOCTL(TCGETA) +COMPATIBLE_IOCTL(TCSETA) +COMPATIBLE_IOCTL(TCSETAW) +COMPATIBLE_IOCTL(TCSETAF) +COMPATIBLE_IOCTL(TCSBRK) +COMPATIBLE_IOCTL(TCXONC) +COMPATIBLE_IOCTL(TCFLSH) +COMPATIBLE_IOCTL(TCGETS) +COMPATIBLE_IOCTL(TCSETS) +COMPATIBLE_IOCTL(TCSETSW) +COMPATIBLE_IOCTL(TCSETSF) +COMPATIBLE_IOCTL(TIOCLINUX) + +COMPATIBLE_IOCTL(TIOCGETD) +COMPATIBLE_IOCTL(TIOCSETD) +COMPATIBLE_IOCTL(TIOCEXCL) +COMPATIBLE_IOCTL(TIOCNXCL) +COMPATIBLE_IOCTL(TIOCCONS) +COMPATIBLE_IOCTL(TIOCGSOFTCAR) +COMPATIBLE_IOCTL(TIOCSSOFTCAR) +COMPATIBLE_IOCTL(TIOCSWINSZ) +COMPATIBLE_IOCTL(TIOCGWINSZ) +COMPATIBLE_IOCTL(TIOCMGET) +COMPATIBLE_IOCTL(TIOCMBIC) +COMPATIBLE_IOCTL(TIOCMBIS) +COMPATIBLE_IOCTL(TIOCMSET) +COMPATIBLE_IOCTL(TIOCPKT) +COMPATIBLE_IOCTL(TIOCNOTTY) +COMPATIBLE_IOCTL(TIOCSTI) +COMPATIBLE_IOCTL(TIOCOUTQ) +COMPATIBLE_IOCTL(TIOCSPGRP) +COMPATIBLE_IOCTL(TIOCGPGRP) +COMPATIBLE_IOCTL(TIOCSCTTY) +COMPATIBLE_IOCTL(TIOCGPTN) +COMPATIBLE_IOCTL(TIOCSPTLCK) +COMPATIBLE_IOCTL(TIOCGSERIAL) +COMPATIBLE_IOCTL(TIOCSSERIAL) +COMPATIBLE_IOCTL(TIOCSERGETLSR) + +COMPATIBLE_IOCTL(FIOCLEX) +COMPATIBLE_IOCTL(FIONCLEX) +COMPATIBLE_IOCTL(FIOASYNC) +COMPATIBLE_IOCTL(FIONBIO) +COMPATIBLE_IOCTL(FIONREAD) + +#ifdef CONFIG_FB +/* Big F */ +COMPATIBLE_IOCTL(FBIOGET_VSCREENINFO) +COMPATIBLE_IOCTL(FBIOPUT_VSCREENINFO) +HANDLE_IOCTL(FBIOGET_FSCREENINFO, do_fbioget_fscreeninfo_ioctl) +HANDLE_IOCTL(FBIOGETCMAP, do_fbiocmap_ioctl) +HANDLE_IOCTL(FBIOPUTCMAP, do_fbiocmap_ioctl) +COMPATIBLE_IOCTL(FBIOPAN_DISPLAY) +#endif /* CONFIG_FB */ + +/* Big K */ +COMPATIBLE_IOCTL(PIO_FONT) +COMPATIBLE_IOCTL(GIO_FONT) +COMPATIBLE_IOCTL(KDSIGACCEPT) +COMPATIBLE_IOCTL(KDGETKEYCODE) +COMPATIBLE_IOCTL(KDSETKEYCODE) +COMPATIBLE_IOCTL(KIOCSOUND) +COMPATIBLE_IOCTL(KDMKTONE) +COMPATIBLE_IOCTL(KDGKBTYPE) +COMPATIBLE_IOCTL(KDSETMODE) +COMPATIBLE_IOCTL(KDGETMODE) +COMPATIBLE_IOCTL(KDSKBMODE) +COMPATIBLE_IOCTL(KDGKBMODE) +COMPATIBLE_IOCTL(KDSKBMETA) +COMPATIBLE_IOCTL(KDGKBMETA) +COMPATIBLE_IOCTL(KDGKBENT) +COMPATIBLE_IOCTL(KDSKBENT) +COMPATIBLE_IOCTL(KDGKBSENT) +COMPATIBLE_IOCTL(KDSKBSENT) +COMPATIBLE_IOCTL(KDGKBDIACR) +COMPATIBLE_IOCTL(KDSKBDIACR) +COMPATIBLE_IOCTL(KDKBDREP) +COMPATIBLE_IOCTL(KDGKBLED) +COMPATIBLE_IOCTL(KDSKBLED) +COMPATIBLE_IOCTL(KDGETLED) +COMPATIBLE_IOCTL(KDSETLED) +COMPATIBLE_IOCTL(GIO_SCRNMAP) +COMPATIBLE_IOCTL(PIO_SCRNMAP) +COMPATIBLE_IOCTL(GIO_UNISCRNMAP) +COMPATIBLE_IOCTL(PIO_UNISCRNMAP) +COMPATIBLE_IOCTL(PIO_FONTRESET) +COMPATIBLE_IOCTL(PIO_UNIMAPCLR) + +/* Big S */ +COMPATIBLE_IOCTL(SCSI_IOCTL_GET_IDLUN) +COMPATIBLE_IOCTL(SCSI_IOCTL_DOORLOCK) +COMPATIBLE_IOCTL(SCSI_IOCTL_DOORUNLOCK) +COMPATIBLE_IOCTL(SCSI_IOCTL_TEST_UNIT_READY) +COMPATIBLE_IOCTL(SCSI_IOCTL_TAGGED_ENABLE) +COMPATIBLE_IOCTL(SCSI_IOCTL_TAGGED_DISABLE) +COMPATIBLE_IOCTL(SCSI_IOCTL_GET_BUS_NUMBER) +COMPATIBLE_IOCTL(SCSI_IOCTL_SEND_COMMAND) + +/* Big V */ +COMPATIBLE_IOCTL(VT_SETMODE) +COMPATIBLE_IOCTL(VT_GETMODE) +COMPATIBLE_IOCTL(VT_GETSTATE) +COMPATIBLE_IOCTL(VT_OPENQRY) +COMPATIBLE_IOCTL(VT_ACTIVATE) +COMPATIBLE_IOCTL(VT_WAITACTIVE) +COMPATIBLE_IOCTL(VT_RELDISP) +COMPATIBLE_IOCTL(VT_DISALLOCATE) +COMPATIBLE_IOCTL(VT_RESIZE) +COMPATIBLE_IOCTL(VT_RESIZEX) +COMPATIBLE_IOCTL(VT_LOCKSWITCH) +COMPATIBLE_IOCTL(VT_UNLOCKSWITCH) #ifdef CONFIG_NET - /* Socket level stuff */ - IOCTL32_DEFAULT(FIOSETOWN), - IOCTL32_DEFAULT(SIOCSPGRP), - IOCTL32_DEFAULT(FIOGETOWN), - IOCTL32_DEFAULT(SIOCGPGRP), - IOCTL32_DEFAULT(SIOCATMARK), - IOCTL32_DEFAULT(SIOCSIFLINK), - IOCTL32_DEFAULT(SIOCSIFENCAP), - IOCTL32_DEFAULT(SIOCGIFENCAP), - IOCTL32_DEFAULT(SIOCSIFBR), - IOCTL32_DEFAULT(SIOCGIFBR), - IOCTL32_DEFAULT(SIOCSARP), - IOCTL32_DEFAULT(SIOCGARP), - IOCTL32_DEFAULT(SIOCDARP), - IOCTL32_DEFAULT(SIOCSRARP), - IOCTL32_DEFAULT(SIOCGRARP), - IOCTL32_DEFAULT(SIOCDRARP), - IOCTL32_DEFAULT(SIOCADDDLCI), - IOCTL32_DEFAULT(SIOCDELDLCI), - - IOCTL32_HANDLER(SIOCGIFNAME, dev_ifname32), - IOCTL32_HANDLER(SIOCGIFCONF, dev_ifconf), - IOCTL32_HANDLER(SIOCGIFFLAGS, dev_ifsioc), - IOCTL32_HANDLER(SIOCSIFFLAGS, dev_ifsioc), - IOCTL32_HANDLER(SIOCGIFMETRIC, dev_ifsioc), - IOCTL32_HANDLER(SIOCSIFMETRIC, dev_ifsioc), - IOCTL32_HANDLER(SIOCGIFMTU, dev_ifsioc), - IOCTL32_HANDLER(SIOCSIFMTU, dev_ifsioc), - IOCTL32_HANDLER(SIOCGIFMEM, dev_ifsioc), - IOCTL32_HANDLER(SIOCSIFMEM, dev_ifsioc), - IOCTL32_HANDLER(SIOCGIFHWADDR, dev_ifsioc), - IOCTL32_HANDLER(SIOCSIFHWADDR, dev_ifsioc), - IOCTL32_HANDLER(SIOCADDMULTI, dev_ifsioc), - IOCTL32_HANDLER(SIOCDELMULTI, dev_ifsioc), - IOCTL32_HANDLER(SIOCGIFINDEX, dev_ifsioc), - IOCTL32_HANDLER(SIOCGIFMAP, dev_ifsioc), - IOCTL32_HANDLER(SIOCSIFMAP, dev_ifsioc), - IOCTL32_HANDLER(SIOCGIFADDR, dev_ifsioc), - IOCTL32_HANDLER(SIOCSIFADDR, dev_ifsioc), - IOCTL32_HANDLER(SIOCGIFBRDADDR, dev_ifsioc), - IOCTL32_HANDLER(SIOCSIFBRDADDR, dev_ifsioc), - IOCTL32_HANDLER(SIOCGIFDSTADDR, dev_ifsioc), - IOCTL32_HANDLER(SIOCSIFDSTADDR, dev_ifsioc), - IOCTL32_HANDLER(SIOCGIFNETMASK, dev_ifsioc), - IOCTL32_HANDLER(SIOCSIFNETMASK, dev_ifsioc), - IOCTL32_HANDLER(SIOCSIFPFLAGS, dev_ifsioc), - IOCTL32_HANDLER(SIOCGIFPFLAGS, dev_ifsioc), - IOCTL32_HANDLER(SIOCGIFTXQLEN, dev_ifsioc), - IOCTL32_HANDLER(SIOCSIFTXQLEN, dev_ifsioc), - IOCTL32_HANDLER(SIOCADDRT, routing_ioctl), - IOCTL32_HANDLER(SIOCDELRT, routing_ioctl), - /* - * Note SIOCRTMSG is no longer, so this is safe and * the user would - * have seen just an -EINVAL anyways. - */ - IOCTL32_HANDLER(SIOCRTMSG, ret_einval), - IOCTL32_HANDLER(SIOCGSTAMP, do_siocgstamp), +/* Socket level stuff */ +COMPATIBLE_IOCTL(FIOSETOWN) +COMPATIBLE_IOCTL(SIOCSPGRP) +COMPATIBLE_IOCTL(FIOGETOWN) +COMPATIBLE_IOCTL(SIOCGPGRP) +COMPATIBLE_IOCTL(SIOCATMARK) +COMPATIBLE_IOCTL(SIOCSIFLINK) +COMPATIBLE_IOCTL(SIOCSIFENCAP) +COMPATIBLE_IOCTL(SIOCGIFENCAP) +COMPATIBLE_IOCTL(SIOCSIFBR) +COMPATIBLE_IOCTL(SIOCGIFBR) +COMPATIBLE_IOCTL(SIOCSARP) +COMPATIBLE_IOCTL(SIOCGARP) +COMPATIBLE_IOCTL(SIOCDARP) +COMPATIBLE_IOCTL(SIOCSRARP) +COMPATIBLE_IOCTL(SIOCGRARP) +COMPATIBLE_IOCTL(SIOCDRARP) +COMPATIBLE_IOCTL(SIOCADDDLCI) +COMPATIBLE_IOCTL(SIOCDELDLCI) +/* SG stuff */ +COMPATIBLE_IOCTL(SG_SET_TIMEOUT) +COMPATIBLE_IOCTL(SG_GET_TIMEOUT) +COMPATIBLE_IOCTL(SG_EMULATED_HOST) +COMPATIBLE_IOCTL(SG_SET_TRANSFORM) +COMPATIBLE_IOCTL(SG_GET_TRANSFORM) +COMPATIBLE_IOCTL(SG_SET_RESERVED_SIZE) +COMPATIBLE_IOCTL(SG_GET_RESERVED_SIZE) +COMPATIBLE_IOCTL(SG_GET_SCSI_ID) +COMPATIBLE_IOCTL(SG_SET_FORCE_LOW_DMA) +COMPATIBLE_IOCTL(SG_GET_LOW_DMA) +COMPATIBLE_IOCTL(SG_SET_FORCE_PACK_ID) +COMPATIBLE_IOCTL(SG_GET_PACK_ID) +COMPATIBLE_IOCTL(SG_GET_NUM_WAITING) +COMPATIBLE_IOCTL(SG_SET_DEBUG) +COMPATIBLE_IOCTL(SG_GET_SG_TABLESIZE) +COMPATIBLE_IOCTL(SG_GET_COMMAND_Q) +COMPATIBLE_IOCTL(SG_SET_COMMAND_Q) +COMPATIBLE_IOCTL(SG_GET_VERSION_NUM) +COMPATIBLE_IOCTL(SG_NEXT_CMD_LEN) +COMPATIBLE_IOCTL(SG_SCSI_RESET) +COMPATIBLE_IOCTL(SG_IO) +COMPATIBLE_IOCTL(SG_GET_REQUEST_TABLE) +COMPATIBLE_IOCTL(SG_SET_KEEP_ORPHAN) +COMPATIBLE_IOCTL(SG_GET_KEEP_ORPHAN) +/* PPP stuff */ +COMPATIBLE_IOCTL(PPPIOCGFLAGS) +COMPATIBLE_IOCTL(PPPIOCSFLAGS) +COMPATIBLE_IOCTL(PPPIOCGASYNCMAP) +COMPATIBLE_IOCTL(PPPIOCSASYNCMAP) +COMPATIBLE_IOCTL(PPPIOCGUNIT) +COMPATIBLE_IOCTL(PPPIOCGRASYNCMAP) +COMPATIBLE_IOCTL(PPPIOCSRASYNCMAP) +COMPATIBLE_IOCTL(PPPIOCGMRU) +COMPATIBLE_IOCTL(PPPIOCSMRU) +COMPATIBLE_IOCTL(PPPIOCSMAXCID) +COMPATIBLE_IOCTL(PPPIOCGXASYNCMAP) +COMPATIBLE_IOCTL(PPPIOCSXASYNCMAP) +COMPATIBLE_IOCTL(PPPIOCXFERUNIT) +COMPATIBLE_IOCTL(PPPIOCGNPMODE) +COMPATIBLE_IOCTL(PPPIOCSNPMODE) +COMPATIBLE_IOCTL(PPPIOCGDEBUG) +COMPATIBLE_IOCTL(PPPIOCSDEBUG) +COMPATIBLE_IOCTL(PPPIOCNEWUNIT) +COMPATIBLE_IOCTL(PPPIOCATTACH) +COMPATIBLE_IOCTL(PPPIOCGCHAN) +/* PPPOX */ +COMPATIBLE_IOCTL(PPPOEIOCSFWD) +COMPATIBLE_IOCTL(PPPOEIOCDFWD) +/* CDROM stuff */ +COMPATIBLE_IOCTL(CDROMPAUSE) +COMPATIBLE_IOCTL(CDROMRESUME) +COMPATIBLE_IOCTL(CDROMPLAYMSF) +COMPATIBLE_IOCTL(CDROMPLAYTRKIND) +COMPATIBLE_IOCTL(CDROMREADTOCHDR) +COMPATIBLE_IOCTL(CDROMREADTOCENTRY) +COMPATIBLE_IOCTL(CDROMSTOP) +COMPATIBLE_IOCTL(CDROMSTART) +COMPATIBLE_IOCTL(CDROMEJECT) +COMPATIBLE_IOCTL(CDROMVOLCTRL) +COMPATIBLE_IOCTL(CDROMSUBCHNL) +COMPATIBLE_IOCTL(CDROMEJECT_SW) +COMPATIBLE_IOCTL(CDROMMULTISESSION) +COMPATIBLE_IOCTL(CDROM_GET_MCN) +COMPATIBLE_IOCTL(CDROMRESET) +COMPATIBLE_IOCTL(CDROMVOLREAD) +COMPATIBLE_IOCTL(CDROMSEEK) +COMPATIBLE_IOCTL(CDROMPLAYBLK) +COMPATIBLE_IOCTL(CDROMCLOSETRAY) +COMPATIBLE_IOCTL(CDROM_SET_OPTIONS) +COMPATIBLE_IOCTL(CDROM_CLEAR_OPTIONS) +COMPATIBLE_IOCTL(CDROM_SELECT_SPEED) +COMPATIBLE_IOCTL(CDROM_SELECT_DISC) +COMPATIBLE_IOCTL(CDROM_MEDIA_CHANGED) +COMPATIBLE_IOCTL(CDROM_DRIVE_STATUS) +COMPATIBLE_IOCTL(CDROM_DISC_STATUS) +COMPATIBLE_IOCTL(CDROM_CHANGER_NSLOTS) +COMPATIBLE_IOCTL(CDROM_LOCKDOOR) +COMPATIBLE_IOCTL(CDROM_DEBUG) +COMPATIBLE_IOCTL(CDROM_GET_CAPABILITY) +/* DVD ioctls */ +COMPATIBLE_IOCTL(DVD_READ_STRUCT) +COMPATIBLE_IOCTL(DVD_WRITE_STRUCT) +COMPATIBLE_IOCTL(DVD_AUTH) +/* Big L */ +COMPATIBLE_IOCTL(LOOP_SET_FD) +COMPATIBLE_IOCTL(LOOP_CLR_FD) + +/* And these ioctls need translation */ +HANDLE_IOCTL(SIOCGIFNAME, dev_ifname32) +HANDLE_IOCTL(SIOCGIFCONF, dev_ifconf) +HANDLE_IOCTL(SIOCGIFFLAGS, dev_ifsioc) +HANDLE_IOCTL(SIOCSIFFLAGS, dev_ifsioc) +HANDLE_IOCTL(SIOCGIFMETRIC, dev_ifsioc) +HANDLE_IOCTL(SIOCSIFMETRIC, dev_ifsioc) +HANDLE_IOCTL(SIOCGIFMTU, dev_ifsioc) +HANDLE_IOCTL(SIOCSIFMTU, dev_ifsioc) +HANDLE_IOCTL(SIOCGIFMEM, dev_ifsioc) +HANDLE_IOCTL(SIOCSIFMEM, dev_ifsioc) +HANDLE_IOCTL(SIOCGIFHWADDR, dev_ifsioc) +HANDLE_IOCTL(SIOCSIFHWADDR, dev_ifsioc) +HANDLE_IOCTL(SIOCADDMULTI, dev_ifsioc) +HANDLE_IOCTL(SIOCDELMULTI, dev_ifsioc) +HANDLE_IOCTL(SIOCGIFINDEX, dev_ifsioc) +HANDLE_IOCTL(SIOCGIFMAP, dev_ifsioc) +HANDLE_IOCTL(SIOCSIFMAP, dev_ifsioc) +HANDLE_IOCTL(SIOCGIFADDR, dev_ifsioc) +HANDLE_IOCTL(SIOCSIFADDR, dev_ifsioc) +HANDLE_IOCTL(SIOCGIFBRDADDR, dev_ifsioc) +HANDLE_IOCTL(SIOCSIFBRDADDR, dev_ifsioc) +HANDLE_IOCTL(SIOCGIFDSTADDR, dev_ifsioc) +HANDLE_IOCTL(SIOCSIFDSTADDR, dev_ifsioc) +HANDLE_IOCTL(SIOCGIFNETMASK, dev_ifsioc) +HANDLE_IOCTL(SIOCSIFNETMASK, dev_ifsioc) +HANDLE_IOCTL(SIOCSIFPFLAGS, dev_ifsioc) +HANDLE_IOCTL(SIOCGIFPFLAGS, dev_ifsioc) +HANDLE_IOCTL(SIOCGPPPSTATS, dev_ifsioc) +HANDLE_IOCTL(SIOCGPPPCSTATS, dev_ifsioc) +HANDLE_IOCTL(SIOCGPPPVER, dev_ifsioc) +HANDLE_IOCTL(SIOCGIFTXQLEN, dev_ifsioc) +HANDLE_IOCTL(SIOCSIFTXQLEN, dev_ifsioc) +HANDLE_IOCTL(SIOCADDRT, routing_ioctl) +HANDLE_IOCTL(SIOCDELRT, routing_ioctl) +/* + * Note SIOCRTMSG is no longer, so this is safe and * the user would + * have seen just an -EINVAL anyways. + */ +HANDLE_IOCTL(SIOCRTMSG, ret_einval) +HANDLE_IOCTL(SIOCGSTAMP, do_siocgstamp) #endif /* CONFIG_NET */ - IOCTL32_HANDLER(EXT2_IOC32_GETFLAGS, do_ext2_ioctl), - IOCTL32_HANDLER(EXT2_IOC32_SETFLAGS, do_ext2_ioctl), - IOCTL32_HANDLER(EXT2_IOC32_GETVERSION, do_ext2_ioctl), - IOCTL32_HANDLER(EXT2_IOC32_SETVERSION, do_ext2_ioctl), - - IOCTL32_HANDLER(HDIO_GETGEO, hdio_getgeo), /* hdreg.h ioctls */ - IOCTL32_HANDLER(HDIO_GET_UNMASKINTR, hdio_ioctl_trans), - IOCTL32_HANDLER(HDIO_GET_MULTCOUNT, hdio_ioctl_trans), - IOCTL32_HANDLER(HDIO_GET_KEEPSETTINGS, hdio_ioctl_trans), - IOCTL32_HANDLER(HDIO_GET_32BIT, hdio_ioctl_trans), - IOCTL32_HANDLER(HDIO_GET_NOWERR, hdio_ioctl_trans), - IOCTL32_HANDLER(HDIO_GET_DMA, hdio_ioctl_trans), - IOCTL32_HANDLER(HDIO_GET_NICE, hdio_ioctl_trans), - IOCTL32_DEFAULT(HDIO_GET_IDENTITY), - IOCTL32_DEFAULT(HDIO_DRIVE_CMD), - IOCTL32_DEFAULT(HDIO_SET_MULTCOUNT), - IOCTL32_DEFAULT(HDIO_SET_UNMASKINTR), - IOCTL32_DEFAULT(HDIO_SET_KEEPSETTINGS), - IOCTL32_DEFAULT(HDIO_SET_32BIT), - IOCTL32_DEFAULT(HDIO_SET_NOWERR), - IOCTL32_DEFAULT(HDIO_SET_DMA), - IOCTL32_DEFAULT(HDIO_SET_PIO_MODE), - IOCTL32_DEFAULT(HDIO_SET_NICE), - - IOCTL32_DEFAULT(BLKROSET), /* fs.h ioctls */ - IOCTL32_DEFAULT(BLKROGET), - IOCTL32_DEFAULT(BLKRRPART), - IOCTL32_HANDLER(BLKGETSIZE, w_long), - - IOCTL32_DEFAULT(BLKFLSBUF), - IOCTL32_DEFAULT(BLKSECTSET), - IOCTL32_HANDLER(BLKSECTGET, w_long), - IOCTL32_DEFAULT(BLKSSZGET), - IOCTL32_HANDLER(BLKPG, blkpg_ioctl_trans), - IOCTL32_DEFAULT(BLKBSZGET), - IOCTL32_DEFAULT(BLKBSZSET), +HANDLE_IOCTL(EXT2_IOC32_GETFLAGS, do_ext2_ioctl) +HANDLE_IOCTL(EXT2_IOC32_SETFLAGS, do_ext2_ioctl) +HANDLE_IOCTL(EXT2_IOC32_GETVERSION, do_ext2_ioctl) +HANDLE_IOCTL(EXT2_IOC32_SETVERSION, do_ext2_ioctl) + +HANDLE_IOCTL(HDIO_GETGEO, hdio_getgeo) /* hdreg.h ioctls */ +HANDLE_IOCTL(HDIO_GET_UNMASKINTR, hdio_ioctl_trans) +HANDLE_IOCTL(HDIO_GET_MULTCOUNT, hdio_ioctl_trans) +// HDIO_OBSOLETE_IDENTITY +//HANDLE_IOCTL(HDIO_GET_KEEPSETTINGS, hdio_ioctl_trans) +HANDLE_IOCTL(HDIO_GET_32BIT, hdio_ioctl_trans) +HANDLE_IOCTL(HDIO_GET_NOWERR, hdio_ioctl_trans) +HANDLE_IOCTL(HDIO_GET_DMA, hdio_ioctl_trans) +HANDLE_IOCTL(HDIO_GET_NICE, hdio_ioctl_trans) +COMPATIBLE_IOCTL(HDIO_GET_IDENTITY) +// HDIO_TRISTATE_HWIF /* not implemented */ +// HDIO_DRIVE_TASK /* To do, need specs */ +COMPATIBLE_IOCTL(HDIO_DRIVE_CMD) +COMPATIBLE_IOCTL(HDIO_SET_MULTCOUNT) +COMPATIBLE_IOCTL(HDIO_SET_UNMASKINTR) +//COMPATIBLE_IOCTL(HDIO_SET_KEEPSETTINGS) +COMPATIBLE_IOCTL(HDIO_SET_32BIT) +COMPATIBLE_IOCTL(HDIO_SET_NOWERR) +COMPATIBLE_IOCTL(HDIO_SET_DMA) +COMPATIBLE_IOCTL(HDIO_SET_PIO_MODE) +COMPATIBLE_IOCTL(HDIO_SET_NICE) + +COMPATIBLE_IOCTL(BLKROSET) /* fs.h ioctls */ +COMPATIBLE_IOCTL(BLKROGET) +COMPATIBLE_IOCTL(BLKRRPART) +HANDLE_IOCTL(BLKGETSIZE, w_long) + +COMPATIBLE_IOCTL(BLKFLSBUF) +COMPATIBLE_IOCTL(BLKSECTSET) +HANDLE_IOCTL(BLKSECTGET, w_long) +COMPATIBLE_IOCTL(BLKSSZGET) +HANDLE_IOCTL(BLKPG, blkpg_ioctl_trans) +COMPATIBLE_IOCTL(BLKBSZGET) +COMPATIBLE_IOCTL(BLKBSZSET) #ifdef CONFIG_MD - /* status */ - IOCTL32_DEFAULT(RAID_VERSION), - IOCTL32_DEFAULT(GET_ARRAY_INFO), - IOCTL32_DEFAULT(GET_DISK_INFO), - IOCTL32_DEFAULT(PRINT_RAID_DEBUG), - IOCTL32_DEFAULT(RAID_AUTORUN), - - /* configuration */ - IOCTL32_DEFAULT(CLEAR_ARRAY), - IOCTL32_DEFAULT(ADD_NEW_DISK), - IOCTL32_DEFAULT(HOT_REMOVE_DISK), - IOCTL32_DEFAULT(SET_ARRAY_INFO), - IOCTL32_DEFAULT(SET_DISK_INFO), - IOCTL32_DEFAULT(WRITE_RAID_INFO), - IOCTL32_DEFAULT(UNPROTECT_ARRAY), - IOCTL32_DEFAULT(PROTECT_ARRAY), - IOCTL32_DEFAULT(HOT_ADD_DISK), - IOCTL32_DEFAULT(SET_DISK_FAULTY), - - /* usage */ - IOCTL32_DEFAULT(RUN_ARRAY), - IOCTL32_DEFAULT(START_ARRAY), - IOCTL32_DEFAULT(STOP_ARRAY), - IOCTL32_DEFAULT(STOP_ARRAY_RO), - IOCTL32_DEFAULT(RESTART_ARRAY_RW), +/* status */ +COMPATIBLE_IOCTL(RAID_VERSION) +COMPATIBLE_IOCTL(GET_ARRAY_INFO) +COMPATIBLE_IOCTL(GET_DISK_INFO) +COMPATIBLE_IOCTL(PRINT_RAID_DEBUG) +COMPATIBLE_IOCTL(RAID_AUTORUN) + +/* configuration */ +COMPATIBLE_IOCTL(CLEAR_ARRAY) +COMPATIBLE_IOCTL(ADD_NEW_DISK) +COMPATIBLE_IOCTL(HOT_REMOVE_DISK) +COMPATIBLE_IOCTL(SET_ARRAY_INFO) +COMPATIBLE_IOCTL(SET_DISK_INFO) +COMPATIBLE_IOCTL(WRITE_RAID_INFO) +COMPATIBLE_IOCTL(UNPROTECT_ARRAY) +COMPATIBLE_IOCTL(PROTECT_ARRAY) +COMPATIBLE_IOCTL(HOT_ADD_DISK) +COMPATIBLE_IOCTL(SET_DISK_FAULTY) + +/* usage */ +COMPATIBLE_IOCTL(RUN_ARRAY) +COMPATIBLE_IOCTL(START_ARRAY) +COMPATIBLE_IOCTL(STOP_ARRAY) +COMPATIBLE_IOCTL(STOP_ARRAY_RO) +COMPATIBLE_IOCTL(RESTART_ARRAY_RW) #endif /* CONFIG_MD */ +#ifdef CONFIG_SIBYTE_TBPROF +COMPATIBLE_IOCTL(SBPROF_ZBSTART), +COMPATIBLE_IOCTL(SBPROF_ZBSTOP), +COMPATIBLE_IOCTL(SBPROF_ZBWAITFULL), +#endif /* CONFIG_SIBYTE_TBPROF */ + #if defined(CONFIG_BLK_DEV_DM) || defined(CONFIG_BLK_DEV_DM_MODULE) IOCTL32_DEFAULT(DM_VERSION), IOCTL32_DEFAULT(DM_REMOVE_ALL), @@ -800,25 +1167,44 @@ static struct ioctl32_list ioctl32_handl IOCTL32_DEFAULT(DM_TARGET_WAIT), #endif /* CONFIG_BLK_DEV_DM */ - IOCTL32_DEFAULT(MTIOCTOP), /* mtio.h ioctls */ - IOCTL32_HANDLER(MTIOCGET32, mt_ioctl_trans), - IOCTL32_HANDLER(MTIOCPOS32, mt_ioctl_trans), - IOCTL32_HANDLER(MTIOCGETCONFIG32, mt_ioctl_trans), - IOCTL32_HANDLER(MTIOCSETCONFIG32, mt_ioctl_trans), - // MTIOCRDFTSEG - // MTIOCWRFTSEG - // MTIOCVOLINFO - // MTIOCGETSIZE - // MTIOCFTFORMAT - // MTIOCFTCMD - - IOCTL32_DEFAULT(AUTOFS_IOC_READY), /* auto_fs.h ioctls */ - IOCTL32_DEFAULT(AUTOFS_IOC_FAIL), - IOCTL32_DEFAULT(AUTOFS_IOC_CATATONIC), - IOCTL32_DEFAULT(AUTOFS_IOC_PROTOVER), - IOCTL32_HANDLER(AUTOFS_IOC_SETTIMEOUT32, ioc_settimeout), - IOCTL32_DEFAULT(AUTOFS_IOC_EXPIRE) -}; +COMPATIBLE_IOCTL(MTIOCTOP) /* mtio.h ioctls */ +HANDLE_IOCTL(MTIOCGET32, mt_ioctl_trans) +HANDLE_IOCTL(MTIOCPOS32, mt_ioctl_trans) +HANDLE_IOCTL(MTIOCGETCONFIG32, mt_ioctl_trans) +HANDLE_IOCTL(MTIOCSETCONFIG32, mt_ioctl_trans) +// MTIOCRDFTSEG +// MTIOCWRFTSEG +// MTIOCVOLINFO +// MTIOCGETSIZE +// MTIOCFTFORMAT +// MTIOCFTCMD + +COMPATIBLE_IOCTL(AUTOFS_IOC_READY) /* auto_fs.h ioctls */ +COMPATIBLE_IOCTL(AUTOFS_IOC_FAIL) +COMPATIBLE_IOCTL(AUTOFS_IOC_CATATONIC) +COMPATIBLE_IOCTL(AUTOFS_IOC_PROTOVER) +HANDLE_IOCTL(AUTOFS_IOC_SETTIMEOUT32, ioc_settimeout) +COMPATIBLE_IOCTL(AUTOFS_IOC_EXPIRE) +COMPATIBLE_IOCTL(AUTOFS_IOC_EXPIRE_MULTI) + +/* Little p (/dev/rtc, /dev/envctrl, etc.) */ +COMPATIBLE_IOCTL(_IOR('p', 20, int[7])) /* RTCGET */ +COMPATIBLE_IOCTL(_IOW('p', 21, int[7])) /* RTCSET */ +COMPATIBLE_IOCTL(RTC_AIE_ON) +COMPATIBLE_IOCTL(RTC_AIE_OFF) +COMPATIBLE_IOCTL(RTC_UIE_ON) +COMPATIBLE_IOCTL(RTC_UIE_OFF) +COMPATIBLE_IOCTL(RTC_PIE_ON) +COMPATIBLE_IOCTL(RTC_PIE_OFF) +COMPATIBLE_IOCTL(RTC_WIE_ON) +COMPATIBLE_IOCTL(RTC_WIE_OFF) +COMPATIBLE_IOCTL(RTC_ALM_SET) +COMPATIBLE_IOCTL(RTC_ALM_READ) +COMPATIBLE_IOCTL(RTC_RD_TIME) +COMPATIBLE_IOCTL(RTC_SET_TIME) +COMPATIBLE_IOCTL(RTC_WKALM_SET) +COMPATIBLE_IOCTL(RTC_WKALM_RD) +IOCTL_TABLE_END -#define NR_IOCTL32_HANDLERS (sizeof(ioctl32_handler_table) / \ - sizeof(ioctl32_handler_table[0])) +#define NR_IOCTL_TRANS (sizeof(ioctl_translations) / \ + sizeof(ioctl_translations[0])) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/kernel/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,984 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Code to handle x86 style IRQs plus some generic interrupt stuff. + * + * Copyright (C) 1992 Linus Torvalds + * Copyright (C) 1994 - 2000 Ralf Baechle + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* + * Controller mappings for all interrupt sources: + */ +irq_desc_t irq_desc[NR_IRQS] __cacheline_aligned = { + [0 ... NR_IRQS-1] = { + .handler = &no_irq_type, + .lock = SPIN_LOCK_UNLOCKED + } +}; + +static void register_irq_proc (unsigned int irq); + +/* + * Special irq handlers. + */ + +irqreturn_t no_action(int cpl, void *dev_id, struct pt_regs *regs) +{ return IRQ_NONE; } + +/* + * Generic no controller code + */ + +static void enable_none(unsigned int irq) { } +static unsigned int startup_none(unsigned int irq) { return 0; } +static void disable_none(unsigned int irq) { } +static void ack_none(unsigned int irq) +{ + /* + * 'what should we do if we get a hw irq event on an illegal vector'. + * each architecture has to answer this themselves, it doesn't deserve + * a generic callback i think. + */ + printk("unexpected interrupt %d\n", irq); +} + +/* startup is the same as "enable", shutdown is same as "disable" */ +#define shutdown_none disable_none +#define end_none enable_none + +struct hw_interrupt_type no_irq_type = { + "none", + startup_none, + shutdown_none, + enable_none, + disable_none, + ack_none, + end_none +}; + +atomic_t irq_err_count; + +/* + * Generic, controller-independent functions: + */ + +int show_interrupts(struct seq_file *p, void *v) +{ + int i, j; + struct irqaction * action; + unsigned long flags; + + seq_printf(p, " "); + for (j=0; jtypename); + seq_printf(p, " %s", action->name); + + for (action=action->next; action; action = action->next) + seq_printf(p, ", %s", action->name); + + seq_putc(p, '\n'); +skip: + spin_unlock_irqrestore(&irq_desc[i].lock, flags); + } + seq_putc(p, '\n'); + seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); + + return 0; +} + +#ifdef CONFIG_SMP +inline void synchronize_irq(unsigned int irq) +{ + while (irq_desc[irq].status & IRQ_INPROGRESS) + cpu_relax(); +} +#endif + +/* + * This should really return information about whether + * we should do bottom half handling etc. Right now we + * end up _always_ checking the bottom half, which is a + * waste of time and is not what some drivers would + * prefer. + */ +int handle_IRQ_event(unsigned int irq, struct pt_regs * regs, struct irqaction * action) +{ + int status = 1; /* Force the "do bottom halves" bit */ + int retval = 0; + + if (!(action->flags & SA_INTERRUPT)) + local_irq_enable(); + + do { + status |= action->flags; + retval |= action->handler(irq, action->dev_id, regs); + action = action->next; + } while (action); + if (status & SA_SAMPLE_RANDOM) + add_interrupt_randomness(irq); + local_irq_disable(); + + return retval; +} + +static void __report_bad_irq(int irq, irq_desc_t *desc, irqreturn_t action_ret) +{ + struct irqaction *action; + + if (action_ret != IRQ_HANDLED && action_ret != IRQ_NONE) { + printk(KERN_ERR "irq event %d: bogus return value %x\n", + irq, action_ret); + } else { + printk(KERN_ERR "irq %d: nobody cared!\n", irq); + } + dump_stack(); + printk(KERN_ERR "handlers:\n"); + action = desc->action; + do { + printk(KERN_ERR "[<%p>]", action->handler); + print_symbol(" (%s)", + (unsigned long)action->handler); + printk("\n"); + action = action->next; + } while (action); +} + +static void report_bad_irq(int irq, irq_desc_t *desc, irqreturn_t action_ret) +{ + static int count = 100; + + if (count) { + count--; + __report_bad_irq(irq, desc, action_ret); + } +} + +static int noirqdebug; + +static int __init noirqdebug_setup(char *str) +{ + noirqdebug = 1; + printk("IRQ lockup detection disabled\n"); + return 1; +} + +__setup("noirqdebug", noirqdebug_setup); + +/* + * If 99,900 of the previous 100,000 interrupts have not been handled then + * assume that the IRQ is stuck in some manner. Drop a diagnostic and try to + * turn the IRQ off. + * + * (The other 100-of-100,000 interrupts may have been a correctly-functioning + * device sharing an IRQ with the failing one) + * + * Called under desc->lock + */ +static void note_interrupt(int irq, irq_desc_t *desc, irqreturn_t action_ret) +{ + if (action_ret != IRQ_HANDLED) { + desc->irqs_unhandled++; + if (action_ret != IRQ_NONE) + report_bad_irq(irq, desc, action_ret); + } + + desc->irq_count++; + if (desc->irq_count < 100000) + return; + + desc->irq_count = 0; + if (desc->irqs_unhandled > 99900) { + /* + * The interrupt is stuck + */ + __report_bad_irq(irq, desc, action_ret); + /* + * Now kill the IRQ + */ + printk(KERN_EMERG "Disabling IRQ #%d\n", irq); + desc->status |= IRQ_DISABLED; + desc->handler->disable(irq); + } + desc->irqs_unhandled = 0; +} + +/* + * Generic enable/disable code: this just calls + * down into the PIC-specific version for the actual + * hardware disable after having gotten the irq + * controller lock. + */ + +/** + * disable_irq_nosync - disable an irq without waiting + * @irq: Interrupt to disable + * + * Disable the selected interrupt line. Disables of an interrupt + * stack. Unlike disable_irq(), this function does not ensure existing + * instances of the IRQ handler have completed before returning. + * + * This function may be called from IRQ context. + */ + +void inline disable_irq_nosync(unsigned int irq) +{ + irq_desc_t *desc = irq_desc + irq; + unsigned long flags; + + spin_lock_irqsave(&desc->lock, flags); + if (!desc->depth++) { + desc->status |= IRQ_DISABLED; + desc->handler->disable(irq); + } + spin_unlock_irqrestore(&desc->lock, flags); +} + +/** + * disable_irq - disable an irq and wait for completion + * @irq: Interrupt to disable + * + * Disable the selected interrupt line. Disables of an interrupt + * stack. That is for two disables you need two enables. This + * function waits for any pending IRQ handlers for this interrupt + * to complete before returning. If you use this function while + * holding a resource the IRQ handler may need you will deadlock. + * + * This function may be called - with care - from IRQ context. + */ + +void disable_irq(unsigned int irq) +{ + disable_irq_nosync(irq); + synchronize_irq(irq); +} + +/** + * enable_irq - enable interrupt handling on an irq + * @irq: Interrupt to enable + * + * Re-enables the processing of interrupts on this IRQ line + * providing no disable_irq calls are now in effect. + * + * This function may be called from IRQ context. + */ + +void enable_irq(unsigned int irq) +{ + irq_desc_t *desc = irq_desc + irq; + unsigned long flags; + + spin_lock_irqsave(&desc->lock, flags); + switch (desc->depth) { + case 1: { + unsigned int status = desc->status & ~IRQ_DISABLED; + desc->status = status; + if ((status & (IRQ_PENDING | IRQ_REPLAY)) == IRQ_PENDING) { + desc->status = status | IRQ_REPLAY; + hw_resend_irq(desc->handler,irq); + } + desc->handler->enable(irq); + /* fall-through */ + } + default: + desc->depth--; + break; + case 0: + printk("enable_irq(%u) unbalanced from %p\n", irq, + __builtin_return_address(0)); + } + spin_unlock_irqrestore(&desc->lock, flags); +} + +/* + * do_IRQ handles all normal device IRQ's (the special + * SMP cross-CPU interrupts have their own specific + * handlers). + */ +asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs) +{ + /* + * We ack quickly, we don't want the irq controller + * thinking we're snobs just because some other CPU has + * disabled global interrupts (we have already done the + * INT_ACK cycles, it's too late to try to pretend to the + * controller that we aren't taking the interrupt). + * + * 0 return value means that this irq is already being + * handled by some other CPU. (or is disabled) + */ + int cpu = smp_processor_id(); + irq_desc_t *desc = irq_desc + irq; + struct irqaction * action; + unsigned int status; + + irq_enter(); + kstat_cpu(cpu).irqs[irq]++; + spin_lock(&desc->lock); + desc->handler->ack(irq); + /* + REPLAY is when Linux resends an IRQ that was dropped earlier + WAITING is used by probe to mark irqs that are being tested + */ + status = desc->status & ~(IRQ_REPLAY | IRQ_WAITING); + status |= IRQ_PENDING; /* we _want_ to handle it */ + + /* + * If the IRQ is disabled for whatever reason, we cannot + * use the action we have. + */ + action = NULL; + if (likely(!(status & (IRQ_DISABLED | IRQ_INPROGRESS)))) { + action = desc->action; + status &= ~IRQ_PENDING; /* we commit to handling */ + status |= IRQ_INPROGRESS; /* we are handling it */ + } + desc->status = status; + + /* + * If there is no IRQ handler or it was disabled, exit early. + Since we set PENDING, if another processor is handling + a different instance of this same irq, the other processor + will take care of it. + */ + if (unlikely(!action)) + goto out; + + /* + * Edge triggered interrupts need to remember + * pending events. + * This applies to any hw interrupts that allow a second + * instance of the same irq to arrive while we are in do_IRQ + * or in the handler. But the code here only handles the _second_ + * instance of the irq, not the third or fourth. So it is mostly + * useful for irq hardware that does not mask cleanly in an + * SMP environment. + */ + for (;;) { + irqreturn_t action_ret; + + spin_unlock(&desc->lock); + action_ret = handle_IRQ_event(irq, ®s, action); + spin_lock(&desc->lock); + if (!noirqdebug) + note_interrupt(irq, desc, action_ret); + if (likely(!(desc->status & IRQ_PENDING))) + break; + desc->status &= ~IRQ_PENDING; + } + desc->status &= ~IRQ_INPROGRESS; + +out: + /* + * The ->end() handler has to deal with interrupts which got + * disabled while the handler was running. + */ + desc->handler->end(irq); + spin_unlock(&desc->lock); + + irq_exit(); + + return 1; +} + +/** + * request_irq - allocate an interrupt line + * @irq: Interrupt line to allocate + * @handler: Function to be called when the IRQ occurs + * @irqflags: Interrupt type flags + * @devname: An ascii name for the claiming device + * @dev_id: A cookie passed back to the handler function + * + * This call allocates interrupt resources and enables the + * interrupt line and IRQ handling. From the point this + * call is made your handler function may be invoked. Since + * your handler function must clear any interrupt the board + * raises, you must take care both to initialise your hardware + * and to set up the interrupt handler in the right order. + * + * Dev_id must be globally unique. Normally the address of the + * device data structure is used as the cookie. Since the handler + * receives this value it makes sense to use it. + * + * If your interrupt is shared you must pass a non NULL dev_id + * as this is required when freeing the interrupt. + * + * Flags: + * + * SA_SHIRQ Interrupt is shared + * + * SA_INTERRUPT Disable local interrupts while processing + * + * SA_SAMPLE_RANDOM The interrupt can be used for entropy + * + */ + +int request_irq(unsigned int irq, + irqreturn_t (*handler)(int, void *, struct pt_regs *), + unsigned long irqflags, + const char * devname, + void *dev_id) +{ + int retval; + struct irqaction * action; + +#if 1 + /* + * Sanity-check: shared interrupts should REALLY pass in + * a real dev-ID, otherwise we'll have trouble later trying + * to figure out which interrupt is which (messes up the + * interrupt freeing logic etc). + */ + if (irqflags & SA_SHIRQ) { + if (!dev_id) + printk("Bad boy: %s (at 0x%x) called us without a dev_id!\n", devname, (&irq)[-1]); + } +#endif + + if (irq >= NR_IRQS) + return -EINVAL; + if (!handler) + return -EINVAL; + + action = (struct irqaction *) + kmalloc(sizeof(struct irqaction), GFP_ATOMIC); + if (!action) + return -ENOMEM; + + action->handler = handler; + action->flags = irqflags; + action->mask = 0; + action->name = devname; + action->next = NULL; + action->dev_id = dev_id; + + retval = setup_irq(irq, action); + if (retval) + kfree(action); + return retval; +} + +/** + * free_irq - free an interrupt + * @irq: Interrupt line to free + * @dev_id: Device identity to free + * + * Remove an interrupt handler. The handler is removed and if the + * interrupt line is no longer in use by any driver it is disabled. + * On a shared IRQ the caller must ensure the interrupt is disabled + * on the card it drives before calling this function. The function + * does not return until any executing interrupts for this IRQ + * have completed. + * + * This function must not be called from interrupt context. + */ + +void free_irq(unsigned int irq, void *dev_id) +{ + irq_desc_t *desc; + struct irqaction **p; + unsigned long flags; + + if (irq >= NR_IRQS) + return; + + desc = irq_desc + irq; + spin_lock_irqsave(&desc->lock,flags); + p = &desc->action; + for (;;) { + struct irqaction * action = *p; + if (action) { + struct irqaction **pp = p; + p = &action->next; + if (action->dev_id != dev_id) + continue; + + /* Found it - now remove it from the list of entries */ + *pp = action->next; + if (!desc->action) { + desc->status |= IRQ_DISABLED; + desc->handler->shutdown(irq); + } + spin_unlock_irqrestore(&desc->lock,flags); + + /* Wait to make sure it's not being used on another CPU */ + synchronize_irq(irq); + kfree(action); + return; + } + printk("Trying to free free IRQ%d\n",irq); + spin_unlock_irqrestore(&desc->lock,flags); + return; + } +} + +/* + * IRQ autodetection code.. + * + * This depends on the fact that any interrupt that + * comes in on to an unassigned handler will get stuck + * with "IRQ_WAITING" cleared and the interrupt + * disabled. + */ + +static DECLARE_MUTEX(probe_sem); + +/** + * probe_irq_on - begin an interrupt autodetect + * + * Commence probing for an interrupt. The interrupts are scanned + * and a mask of potential interrupt lines is returned. + * + */ + +unsigned long probe_irq_on(void) +{ + unsigned int i; + irq_desc_t *desc; + unsigned long val; + unsigned long delay; + + down(&probe_sem); + /* + * something may have generated an irq long ago and we want to + * flush such a longstanding irq before considering it as spurious. + */ + for (i = NR_IRQS-1; i > 0; i--) { + desc = irq_desc + i; + + spin_lock_irq(&desc->lock); + if (!irq_desc[i].action) + irq_desc[i].handler->startup(i); + spin_unlock_irq(&desc->lock); + } + + /* Wait for longstanding interrupts to trigger. */ + for (delay = jiffies + HZ/50; time_after(delay, jiffies); ) + /* about 20ms delay */ barrier(); + + /* + * enable any unassigned irqs + * (we must startup again here because if a longstanding irq + * happened in the previous stage, it may have masked itself) + */ + for (i = NR_IRQS-1; i > 0; i--) { + desc = irq_desc + i; + + spin_lock_irq(&desc->lock); + if (!desc->action) { + desc->status |= IRQ_AUTODETECT | IRQ_WAITING; + if (desc->handler->startup(i)) + desc->status |= IRQ_PENDING; + } + spin_unlock_irq(&desc->lock); + } + + /* + * Wait for spurious interrupts to trigger + */ + for (delay = jiffies + HZ/10; time_after(delay, jiffies); ) + /* about 100ms delay */ barrier(); + + /* + * Now filter out any obviously spurious interrupts + */ + val = 0; + for (i = 0; i < NR_IRQS; i++) { + irq_desc_t *desc = irq_desc + i; + unsigned int status; + + spin_lock_irq(&desc->lock); + status = desc->status; + + if (status & IRQ_AUTODETECT) { + /* It triggered already - consider it spurious. */ + if (!(status & IRQ_WAITING)) { + desc->status = status & ~IRQ_AUTODETECT; + desc->handler->shutdown(i); + } else + if (i < 32) + val |= 1 << i; + } + spin_unlock_irq(&desc->lock); + } + + return val; +} + +/* + * Return a mask of triggered interrupts (this + * can handle only legacy ISA interrupts). + */ + +/** + * probe_irq_mask - scan a bitmap of interrupt lines + * @val: mask of interrupts to consider + * + * Scan the ISA bus interrupt lines and return a bitmap of + * active interrupts. The interrupt probe logic state is then + * returned to its previous value. + * + * Note: we need to scan all the irq's even though we will + * only return ISA irq numbers - just so that we reset them + * all to a known state. + */ +unsigned int probe_irq_mask(unsigned long val) +{ + int i; + unsigned int mask; + + mask = 0; + for (i = 0; i < NR_IRQS; i++) { + irq_desc_t *desc = irq_desc + i; + unsigned int status; + + spin_lock_irq(&desc->lock); + status = desc->status; + + if (status & IRQ_AUTODETECT) { + if (i < 16 && !(status & IRQ_WAITING)) + mask |= 1 << i; + + desc->status = status & ~IRQ_AUTODETECT; + desc->handler->shutdown(i); + } + spin_unlock_irq(&desc->lock); + } + up(&probe_sem); + + return mask & val; +} + +/* + * Return the one interrupt that triggered (this can + * handle any interrupt source). + */ + +/** + * probe_irq_off - end an interrupt autodetect + * @val: mask of potential interrupts (unused) + * + * Scans the unused interrupt lines and returns the line which + * appears to have triggered the interrupt. If no interrupt was + * found then zero is returned. If more than one interrupt is + * found then minus the first candidate is returned to indicate + * their is doubt. + * + * The interrupt probe logic state is returned to its previous + * value. + * + * BUGS: When used in a module (which arguably shouldnt happen) + * nothing prevents two IRQ probe callers from overlapping. The + * results of this are non-optimal. + */ + +int probe_irq_off(unsigned long val) +{ + int i, irq_found, nr_irqs; + + nr_irqs = 0; + irq_found = 0; + for (i = 0; i < NR_IRQS; i++) { + irq_desc_t *desc = irq_desc + i; + unsigned int status; + + spin_lock_irq(&desc->lock); + status = desc->status; + + if (status & IRQ_AUTODETECT) { + if (!(status & IRQ_WAITING)) { + if (!nr_irqs) + irq_found = i; + nr_irqs++; + } + desc->status = status & ~IRQ_AUTODETECT; + desc->handler->shutdown(i); + } + spin_unlock_irq(&desc->lock); + } + up(&probe_sem); + + if (nr_irqs > 1) + irq_found = -irq_found; + return irq_found; +} + +/* this was setup_x86_irq but it seems pretty generic */ +int setup_irq(unsigned int irq, struct irqaction * new) +{ + int shared = 0; + unsigned long flags; + struct irqaction *old, **p; + irq_desc_t *desc = irq_desc + irq; + + /* + * Some drivers like serial.c use request_irq() heavily, + * so we have to be careful not to interfere with a + * running system. + */ + if (new->flags & SA_SAMPLE_RANDOM) { + /* + * This function might sleep, we want to call it first, + * outside of the atomic block. + * Yes, this might clear the entropy pool if the wrong + * driver is attempted to be loaded, without actually + * installing a new handler, but is this really a problem, + * only the sysadmin is able to do this. + */ + rand_initialize_irq(irq); + } + + /* + * The following block of code has to be executed atomically + */ + spin_lock_irqsave(&desc->lock,flags); + p = &desc->action; + if ((old = *p) != NULL) { + /* Can't share interrupts unless both agree to */ + if (!(old->flags & new->flags & SA_SHIRQ)) { + spin_unlock_irqrestore(&desc->lock,flags); + return -EBUSY; + } + + /* add new interrupt at end of irq queue */ + do { + p = &old->next; + old = *p; + } while (old); + shared = 1; + } + + *p = new; + + if (!shared) { + desc->depth = 0; + desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS); + desc->handler->startup(irq); + } + spin_unlock_irqrestore(&desc->lock,flags); + + register_irq_proc(irq); + return 0; +} + +void __init init_generic_irq(void) +{ + int i; + + for (i = 0; i < NR_IRQS; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].handler = &no_irq_type; + } +} + +EXPORT_SYMBOL(disable_irq_nosync); +EXPORT_SYMBOL(disable_irq); +EXPORT_SYMBOL(enable_irq); +EXPORT_SYMBOL(probe_irq_mask); + +static struct proc_dir_entry * root_irq_dir; +static struct proc_dir_entry * irq_dir [NR_IRQS]; + +#define HEX_DIGITS 8 + +static unsigned int parse_hex_value (const char *buffer, + unsigned long count, unsigned long *ret) +{ + unsigned char hexnum [HEX_DIGITS]; + unsigned long value; + int i; + + if (!count) + return -EINVAL; + if (count > HEX_DIGITS) + count = HEX_DIGITS; + if (copy_from_user(hexnum, buffer, count)) + return -EFAULT; + + /* + * Parse the first 8 characters as a hex string, any non-hex char + * is end-of-string. '00e1', 'e1', '00E1', 'E1' are all the same. + */ + value = 0; + + for (i = 0; i < count; i++) { + unsigned int c = hexnum[i]; + + switch (c) { + case '0' ... '9': c -= '0'; break; + case 'a' ... 'f': c -= 'a'-10; break; + case 'A' ... 'F': c -= 'A'-10; break; + default: + goto out; + } + value = (value << 4) | c; + } +out: + *ret = value; + return 0; +} + +#ifdef CONFIG_SMP + +static struct proc_dir_entry * smp_affinity_entry [NR_IRQS]; + +static unsigned long irq_affinity [NR_IRQS] = { [0 ... NR_IRQS-1] = ~0UL }; +static int irq_affinity_read_proc (char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + if (count < HEX_DIGITS+1) + return -EINVAL; + return sprintf (page, "%08lx\n", irq_affinity[(long)data]); +} + +static int irq_affinity_write_proc (struct file *file, const char *buffer, + unsigned long count, void *data) +{ + int irq = (long) data, full_count = count, err; + unsigned long new_value; + + if (!irq_desc[irq].handler->set_affinity) + return -EIO; + + err = parse_hex_value(buffer, count, &new_value); + + /* + * Do not allow disabling IRQs completely - it's a too easy + * way to make the system unusable accidentally :-) At least + * one online CPU still has to be targeted. + */ + if (!(new_value & cpu_online_map)) + return -EINVAL; + + irq_affinity[irq] = new_value; + irq_desc[irq].handler->set_affinity(irq, new_value); + + return full_count; +} + +#endif + +static int prof_cpu_mask_read_proc (char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + unsigned long *mask = (unsigned long *) data; + if (count < HEX_DIGITS+1) + return -EINVAL; + return sprintf (page, "%08lx\n", *mask); +} + +static int prof_cpu_mask_write_proc (struct file *file, const char *buffer, + unsigned long count, void *data) +{ + unsigned long *mask = (unsigned long *) data, full_count = count, err; + unsigned long new_value; + + err = parse_hex_value(buffer, count, &new_value); + if (err) + return err; + + *mask = new_value; + return full_count; +} + +#define MAX_NAMELEN 10 + +static void register_irq_proc (unsigned int irq) +{ + char name [MAX_NAMELEN]; + + if (!root_irq_dir || (irq_desc[irq].handler == &no_irq_type) || + irq_dir[irq]) + return; + + memset(name, 0, MAX_NAMELEN); + sprintf(name, "%d", irq); + + /* create /proc/irq/1234 */ + irq_dir[irq] = proc_mkdir(name, root_irq_dir); + +#ifdef CONFIG_SMP + { + struct proc_dir_entry *entry; + + /* create /proc/irq/1234/smp_affinity */ + entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]); + + if (entry) { + entry->nlink = 1; + entry->data = (void *)(long)irq; + entry->read_proc = irq_affinity_read_proc; + entry->write_proc = irq_affinity_write_proc; + } + + smp_affinity_entry[irq] = entry; + } +#endif +} + +unsigned long prof_cpu_mask = -1; + +void init_irq_proc (void) +{ + struct proc_dir_entry *entry; + int i; + + /* create /proc/irq */ + root_irq_dir = proc_mkdir("irq", 0); + + /* create /proc/irq/prof_cpu_mask */ + entry = create_proc_entry("prof_cpu_mask", 0600, root_irq_dir); + + if (!entry) + return; + + entry->nlink = 1; + entry->data = (void *)&prof_cpu_mask; + entry->read_proc = prof_cpu_mask_read_proc; + entry->write_proc = prof_cpu_mask_write_proc; + + /* + * Create entries for all existing IRQs. + */ + for (i = 0; i < NR_IRQS; i++) + register_irq_proc(i); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/kernel/irq_cpu.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,116 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * Copyright (C) 2001 Ralf Baechle + * + * This file define the irq handler for MIPS CPU interrupts. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/* + * Almost all MIPS CPUs define 8 interrupt sources. They are typically + * level triggered (i.e., cannot be cleared from CPU; must be cleared from + * device). The first two are software interrupts which we don't really + * use or support. The last one is usually cpu timer interrupt if a counter + * register is present. + * + * Don't even think about using this on SMP. You have been warned. + * + * This file exports one global function: + * mips_cpu_irq_init(u32 irq_base); + */ +#include +#include +#include + +#include +#include + +static int mips_cpu_irq_base; + +static inline void unmask_mips_irq(unsigned int irq) +{ + clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); + set_c0_status(0x100 << (irq - mips_cpu_irq_base)); +} + +static inline void mask_mips_irq(unsigned int irq) +{ + clear_c0_status(0x100 << (irq - mips_cpu_irq_base)); +} + +static inline void mips_cpu_irq_enable(unsigned int irq) +{ + unsigned long flags; + + local_irq_save(flags); + unmask_mips_irq(irq); + local_irq_restore(flags); +} + +static void mips_cpu_irq_disable(unsigned int irq) +{ + unsigned long flags; + + local_irq_save(flags); + mask_mips_irq(irq); + local_irq_restore(flags); +} + +static unsigned int mips_cpu_irq_startup(unsigned int irq) +{ + mips_cpu_irq_enable(irq); + + return 0; +} + +#define mips_cpu_irq_shutdown mips_cpu_irq_disable + +/* + * While we ack the interrupt interrupts are disabled and thus we don't need + * to deal with concurrency issues. Same for mips_cpu_irq_end. + */ +static void mips_cpu_irq_ack(unsigned int irq) +{ + /* Only necessary for soft interrupts */ + clear_c0_cause(1 << (irq - mips_cpu_irq_base + 8)); + + mask_mips_irq(irq); +} + +static void mips_cpu_irq_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + unmask_mips_irq(irq); +} + +static hw_irq_controller mips_cpu_irq_controller = { + "CPU_irq", + mips_cpu_irq_startup, + mips_cpu_irq_shutdown, + mips_cpu_irq_enable, + mips_cpu_irq_disable, + mips_cpu_irq_ack, + mips_cpu_irq_end, + NULL /* no affinity stuff for UP */ +}; + + +void mips_cpu_irq_init(u32 irq_base) +{ + u32 i; + + for (i = irq_base; i < irq_base + 8; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].handler = &mips_cpu_irq_controller; + } + + mips_cpu_irq_base = irq_base; +} --- linux-2.5.73/arch/mips64/kernel/linux32.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/linux32.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,10 +1,11 @@ -/* +/* * Conversion between 32-bit and 64-bit native system calls. * * Copyright (C) 2000 Silicon Graphics, Inc. * Written by Ulf Carlsson (ulfc@engr.sgi.com) * sys32_execve from ia64/ia32 code, Feb 2000, Kanoj Sarcar (kanoj@sgi.com) */ +#include #include #include #include @@ -14,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -21,29 +23,52 @@ #include #include #include +#include #include +#include #include #include #include #include +#include +#include +#include #include #include + #include +#include +#include #include +#include #include -#include - +/* Use this to get at 32-bit user passed pointers. */ +/* A() macro should be used for places where you e.g. + have some internal variable u32 and just want to get + rid of a compiler warning. AA() has to be used in + places where you want to convert a function argument + to 32bit pointer or when you e.g. access pt_regs + structure and want to consider 32bit registers only. + */ #define A(__x) ((unsigned long)(__x)) +#define AA(__x) ((unsigned long)((int)__x)) + +#ifdef __MIPSEB__ +#define merge_64(r1,r2) ((((r1) & 0xffffffffUL) << 32) + ((r2) & 0xffffffffUL)) +#endif +#ifdef __MIPSEL__ +#define merge_64(r1,r2) ((((r2) & 0xffffffffUL) << 32) + ((r1) & 0xffffffffUL)) +#endif /* * Revalidate the inode. This is required for proper NFS attribute caching. */ -static int cp_new_stat32(struct kstat *stat, struct stat32 *statbuf) +int cp_compat_stat(struct kstat *stat, struct compat_stat *statbuf) { - struct stat32 tmp; + struct compat_stat tmp; memset(&tmp, 0, sizeof(tmp)); tmp.st_dev = stat->dev; @@ -54,48 +79,45 @@ static int cp_new_stat32(struct kstat *s SET_STAT_GID(tmp, stat->gid); tmp.st_rdev = stat->rdev; tmp.st_size = stat->size; - tmp.st_atime = stat->atime; - tmp.st_mtime = stat->mtime; - tmp.st_ctime = stat->ctime; + tmp.st_atime = stat->atime.tv_sec; + tmp.st_mtime = stat->mtime.tv_sec; + tmp.st_ctime = stat->ctime.tv_sec; +#ifdef STAT_HAVE_NSEC + tmp.st_atime_nsec = stat->atime.tv_nsec; + tmp.st_mtime_nsec = stat->mtime.tv_nsec; + tmp.st_ctime_nsec = stat->ctime.tv_nsec; +#endif tmp.st_blocks = stat->blocks; tmp.st_blksize = stat->blksize; return copy_to_user(statbuf,&tmp,sizeof(tmp)) ? -EFAULT : 0; } -asmlinkage int sys32_newstat(char * filename, struct stat32 *statbuf) -{ - struct kstat stat; - int error = vfs_stat(filename, &stat); - - if (!error) - error = cp_new_stat32(&stat, statbuf); - - return error; -} - -asmlinkage int sys32_newlstat(char * filename, struct stat32 *statbuf) -{ - struct kstat stat; - int error = vfs_lstat(filename, &stat); - - if (!error) - error = cp_new_stat32(&stat, statbuf); - - return error; -} - -asmlinkage long sys32_newfstat(unsigned int fd, struct stat32 * statbuf) -{ - struct kstat stat; - int error = vfs_fstat(fd, &stat); +asmlinkage unsigned long +sys32_mmap2(unsigned long addr, size_t len, unsigned long prot, + unsigned long flags, unsigned long fd, unsigned long pgoff) +{ + struct file * file = NULL; + unsigned long error; + + error = -EINVAL; + if (!(flags & MAP_ANONYMOUS)) { + error = -EBADF; + file = fget(fd); + if (!file) + goto out; + } + flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE); - if (!error) - error = cp_new_stat32(&stat, statbuf); + down_write(¤t->mm->mmap_sem); + error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff); + up_write(¤t->mm->mmap_sem); + if (file) + fput(file); +out: return error; } -asmlinkage int sys_mmap2(void) {return 0;} asmlinkage long sys_truncate(const char * path, unsigned long length); @@ -117,7 +139,6 @@ asmlinkage int sys_ftruncate64(unsigned return sys_ftruncate(fd, ((long) high << 32) | low); } -#if 0 /* * count32() counts the number of arguments/envelopes */ @@ -127,15 +148,15 @@ static int count32(u32 * argv, int max) if (argv != NULL) { for (;;) { - u32 p; - /* egcs is stupid */ - if (!access_ok(VERIFY_READ, argv, sizeof (u32))) - return -EFAULT; - __get_user(p,argv); + u32 p; int error; + + error = get_user(p,argv); + if (error) + return error; if (!p) break; argv++; - if(++i > max) + if (++i > max) return -E2BIG; } } @@ -148,7 +169,7 @@ static int count32(u32 * argv, int max) * memory to free pages in kernel mem. These are in a format ready * to be put directly into the top of new user memory. */ -int copy_strings32(int argc, u32 * argv, struct linux_binprm *bprm) +int copy_strings32(int argc, u32 * argv, struct linux_binprm *bprm) { while (argc-- > 0) { u32 str; @@ -156,13 +177,13 @@ int copy_strings32(int argc, u32 * argv, unsigned long pos; if (get_user(str, argv+argc) || !str || - !(len = strnlen_user((char *)A(str), bprm->p))) + !(len = strnlen_user((char *)A(str), bprm->p))) return -EFAULT; - if (bprm->p < len) - return -E2BIG; + if (bprm->p < len) + return -E2BIG; bprm->p -= len; - /* XXX: add architecture specific overflow check here. */ + /* XXX: add architecture specific overflow check here. */ pos = bprm->p; while (len > 0) { @@ -199,7 +220,7 @@ int copy_strings32(int argc, u32 * argv, kunmap(page); if (err) - return -EFAULT; + return -EFAULT; pos += bytes_to_copy; str += bytes_to_copy; @@ -209,73 +230,95 @@ int copy_strings32(int argc, u32 * argv, return 0; } - /* - * sys_execve32() executes a new program. + * sys32_execve() executes a new program. */ -int do_execve32(char * filename, u32 * argv, u32 * envp, struct pt_regs * regs) +static inline int +do_execve32(char * filename, u32 * argv, u32 * envp, struct pt_regs * regs) { struct linux_binprm bprm; - struct dentry * dentry; + struct file * file; int retval; int i; - bprm.p = PAGE_SIZE*MAX_ARG_PAGES-sizeof(void *); - memset(bprm.page, 0, MAX_ARG_PAGES*sizeof(bprm.page[0])); + file = open_exec(filename); - dentry = open_namei(filename, 0, 0); - retval = PTR_ERR(dentry); - if (IS_ERR(dentry)) + retval = PTR_ERR(file); + if (IS_ERR(file)) return retval; - bprm.dentry = dentry; + bprm.p = PAGE_SIZE*MAX_ARG_PAGES-sizeof(void *); + memset(bprm.page, 0, MAX_ARG_PAGES * sizeof(bprm.page[0])); + + bprm.file = file; bprm.filename = filename; bprm.sh_bang = 0; bprm.loader = 0; bprm.exec = 0; - if ((bprm.argc = count32(argv, bprm.p / sizeof(u32))) < 0) { - dput(dentry); - return bprm.argc; - } + bprm.security = NULL; + bprm.mm = mm_alloc(); + retval = -ENOMEM; + if (!bprm.mm) + goto out_file; + + retval = init_new_context(current, bprm.mm); + if (retval < 0) + goto out_mm; + + bprm.argc = count32(argv, bprm.p / sizeof(u32)); + if ((retval = bprm.argc) < 0) + goto out_mm; + + bprm.envc = count32(envp, bprm.p / sizeof(u32)); + if ((retval = bprm.envc) < 0) + goto out_mm; - if ((bprm.envc = count32(envp, bprm.p / sizeof(u32))) < 0) { - dput(dentry); - return bprm.envc; - } + if ((retval = security_bprm_alloc(&bprm))) + goto out; retval = prepare_binprm(&bprm); - if (retval < 0) - goto out; - + if (retval < 0) + goto out; + retval = copy_strings_kernel(1, &bprm.filename, &bprm); - if (retval < 0) - goto out; + if (retval < 0) + goto out; bprm.exec = bprm.p; retval = copy_strings32(bprm.envc, envp, &bprm); - if (retval < 0) - goto out; + if (retval < 0) + goto out; retval = copy_strings32(bprm.argc, argv, &bprm); - if (retval < 0) - goto out; + if (retval < 0) + goto out; - retval = search_binary_handler(&bprm,regs); - if (retval >= 0) + retval = search_binary_handler(&bprm, regs); + if (retval >= 0) { /* execve success */ + security_bprm_free(&bprm); return retval; + } out: /* Something went wrong, return the inode and free the argument pages*/ - if (bprm.dentry) - dput(bprm.dentry); - - /* Assumes that free_page() can take a NULL argument. */ - /* I hope this is ok for all architectures */ - for (i = 0 ; i < MAX_ARG_PAGES ; i++) - if (bprm.page[i]) - __free_page(bprm.page[i]); - + for (i = 0 ; i < MAX_ARG_PAGES ; i++) { + struct page * page = bprm.page[i]; + if (page) + __free_page(page); + } + + if (bprm.security) + security_bprm_free(&bprm); + +out_mm: + mmdrop(bprm.mm); + +out_file: + if (bprm.file) { + allow_write_access(bprm.file); + fput(bprm.file); + } return retval; } @@ -299,84 +342,6 @@ asmlinkage int sys32_execve(abi64_no_reg out: return error; } -#else -static int -nargs(unsigned int arg, char **ap) -{ - char *ptr; - int n, ret; - - n = 0; - do { - /* egcs is stupid */ - if (!access_ok(VERIFY_READ, arg, sizeof (unsigned int))) - return -EFAULT; - if (IS_ERR(ret = __get_user((long)ptr,(int *)A(arg)))) - return ret; - if (ap) /* no access_ok needed, we allocated */ - if (IS_ERR(ret = __put_user(ptr, ap++))) - return ret; - arg += sizeof(unsigned int); - n++; - } while (ptr); - return(n - 1); -} - -asmlinkage int -sys32_execve(abi64_no_regargs, struct pt_regs regs) -{ - extern asmlinkage int sys_execve(abi64_no_regargs, struct pt_regs regs); - extern asmlinkage long sys_munmap(unsigned long addr, size_t len); - unsigned int argv = (unsigned int)regs.regs[5]; - unsigned int envp = (unsigned int)regs.regs[6]; - char **av, **ae; - int na, ne, r, len; - char * filename; - - na = nargs(argv, NULL); - if (IS_ERR(na)) - return(na); - ne = nargs(envp, NULL); - if (IS_ERR(ne)) - return(ne); - len = (na + ne + 2) * sizeof(*av); - /* - * kmalloc won't work because the `sys_exec' code will attempt - * to do a `get_user' on the arg list and `get_user' will fail - * on a kernel address (simplifies `get_user'). Instead we - * do an mmap to get a user address. Note that since a successful - * `execve' frees all current memory we only have to do an - * `munmap' if the `execve' failes. - */ - down_write(¤t->mm->mmap_sem); - av = (char **) do_mmap_pgoff(0, 0, len, PROT_READ | PROT_WRITE, - MAP_PRIVATE | MAP_ANONYMOUS, 0); - up_write(¤t->mm->mmap_sem); - - if (IS_ERR(av)) - return (long) av; - ae = av + na + 1; - if (IS_ERR(r = __put_user(0, (av + na)))) - goto out; - if (IS_ERR(r = __put_user(0, (ae + ne)))) - goto out; - if (IS_ERR(r = nargs(argv, av))) - goto out; - if (IS_ERR(r = nargs(envp, ae))) - goto out; - filename = getname((char *) (long)regs.regs[4]); - r = PTR_ERR(filename); - if (IS_ERR(filename)) - goto out; - - r = do_execve(filename, av, ae, ®s); - putname(filename); - if (IS_ERR(r)) -out: - sys_munmap((unsigned long)av, len); - return(r); -} -#endif struct dirent32 { unsigned int d_ino; @@ -446,8 +411,8 @@ struct rusage32 { int ru_nswap; int ru_inblock; int ru_oublock; - int ru_msgsnd; - int ru_msgrcv; + int ru_msgsnd; + int ru_msgrcv; int ru_nsignals; int ru_nvcsw; int ru_nivcsw; @@ -457,8 +422,11 @@ static int put_rusage (struct rusage32 *ru, struct rusage *r) { int err; - - err = put_user (r->ru_utime.tv_sec, &ru->ru_utime.tv_sec); + + if (verify_area(VERIFY_WRITE, ru, sizeof *ru)) + return -EFAULT; + + err = __put_user (r->ru_utime.tv_sec, &ru->ru_utime.tv_sec); err |= __put_user (r->ru_utime.tv_usec, &ru->ru_utime.tv_usec); err |= __put_user (r->ru_stime.tv_sec, &ru->ru_stime.tv_sec); err |= __put_user (r->ru_stime.tv_usec, &ru->ru_stime.tv_usec); @@ -476,6 +444,7 @@ put_rusage (struct rusage32 *ru, struct err |= __put_user (r->ru_nsignals, &ru->ru_nsignals); err |= __put_user (r->ru_nvcsw, &ru->ru_nvcsw); err |= __put_user (r->ru_nivcsw, &ru->ru_nivcsw); + return err; } @@ -490,8 +459,8 @@ sys32_wait4(__kernel_pid_t32 pid, unsign int ret; unsigned int status; mm_segment_t old_fs = get_fs(); - - set_fs(KERNEL_DS); + + set_fs(KERNEL_DS); ret = sys_wait4(pid, stat_addr ? &status : NULL, options, &r); set_fs(old_fs); if (put_rusage (ru, &r)) return -EFAULT; @@ -507,139 +476,90 @@ sys32_waitpid(__kernel_pid_t32 pid, unsi return sys32_wait4(pid, stat_addr, options, NULL); } -#define RLIM_INFINITY32 0x7fffffff -#define RESOURCE32(x) ((x > RLIM_INFINITY32) ? RLIM_INFINITY32 : x) - -struct rlimit32 { - int rlim_cur; - int rlim_max; +struct sysinfo32 { + s32 uptime; + u32 loads[3]; + u32 totalram; + u32 freeram; + u32 sharedram; + u32 bufferram; + u32 totalswap; + u32 freeswap; + u16 procs; + u32 totalhigh; + u32 freehigh; + u32 mem_unit; + char _f[8]; }; -extern asmlinkage int sys_old_getrlimit(unsigned int resource, struct rlimit *rlim); +extern asmlinkage int sys_sysinfo(struct sysinfo *info); -asmlinkage int -sys32_getrlimit(unsigned int resource, struct rlimit32 *rlim) +asmlinkage int sys32_sysinfo(struct sysinfo32 *info) { - struct rlimit r; - int ret; + struct sysinfo s; + int ret, err; mm_segment_t old_fs = get_fs (); set_fs (KERNEL_DS); - ret = sys_old_getrlimit(resource, &r); + ret = sys_sysinfo(&s); set_fs (old_fs); - if (!ret) { - ret = put_user (RESOURCE32(r.rlim_cur), &rlim->rlim_cur); - ret |= __put_user (RESOURCE32(r.rlim_max), &rlim->rlim_max); - } - return ret; -} - -extern asmlinkage int sys_setrlimit(unsigned int resource, struct rlimit *rlim); - -asmlinkage int -sys32_setrlimit(unsigned int resource, struct rlimit32 *rlim) -{ - struct rlimit r; - int ret; - mm_segment_t old_fs = get_fs (); - - if (resource >= RLIM_NLIMITS) return -EINVAL; - if (get_user (r.rlim_cur, &rlim->rlim_cur) || - __get_user (r.rlim_max, &rlim->rlim_max)) + err = put_user (s.uptime, &info->uptime); + err |= __put_user (s.loads[0], &info->loads[0]); + err |= __put_user (s.loads[1], &info->loads[1]); + err |= __put_user (s.loads[2], &info->loads[2]); + err |= __put_user (s.totalram, &info->totalram); + err |= __put_user (s.freeram, &info->freeram); + err |= __put_user (s.sharedram, &info->sharedram); + err |= __put_user (s.bufferram, &info->bufferram); + err |= __put_user (s.totalswap, &info->totalswap); + err |= __put_user (s.freeswap, &info->freeswap); + err |= __put_user (s.procs, &info->procs); + err |= __put_user (s.totalhigh, &info->totalhigh); + err |= __put_user (s.freehigh, &info->freehigh); + err |= __put_user (s.mem_unit, &info->mem_unit); + if (err) return -EFAULT; - if (r.rlim_cur == RLIM_INFINITY32) - r.rlim_cur = RLIM_INFINITY; - if (r.rlim_max == RLIM_INFINITY32) - r.rlim_max = RLIM_INFINITY; - set_fs (KERNEL_DS); - ret = sys_setrlimit(resource, &r); - set_fs (old_fs); return ret; } -struct statfs32 { - int f_type; - int f_bsize; - int f_frsize; - int f_blocks; - int f_bfree; - int f_files; - int f_ffree; - int f_bavail; - __kernel_fsid_t32 f_fsid; - int f_namelen; - int f_spare[6]; +#define RLIM_INFINITY32 0x7fffffff +#define RESOURCE32(x) ((x > RLIM_INFINITY32) ? RLIM_INFINITY32 : x) + +struct rlimit32 { + int rlim_cur; + int rlim_max; }; -static inline int -put_statfs (struct statfs32 *ubuf, struct statfs *kbuf) +#ifdef __MIPSEB__ +asmlinkage long sys32_truncate64(const char * path, unsigned long __dummy, + int length_hi, int length_lo) +#endif +#ifdef __MIPSEL__ +asmlinkage long sys32_truncate64(const char * path, unsigned long __dummy, + int length_lo, int length_hi) +#endif { - int err; - - err = put_user (kbuf->f_type, &ubuf->f_type); - err |= __put_user (kbuf->f_bsize, &ubuf->f_bsize); - err |= __put_user (kbuf->f_blocks, &ubuf->f_blocks); - err |= __put_user (kbuf->f_bfree, &ubuf->f_bfree); - err |= __put_user (kbuf->f_bavail, &ubuf->f_bavail); - err |= __put_user (kbuf->f_files, &ubuf->f_files); - err |= __put_user (kbuf->f_ffree, &ubuf->f_ffree); - err |= __put_user (kbuf->f_namelen, &ubuf->f_namelen); - err |= __put_user (kbuf->f_fsid.val[0], &ubuf->f_fsid.val[0]); - err |= __put_user (kbuf->f_fsid.val[1], &ubuf->f_fsid.val[1]); - return err; -} + loff_t length; -extern asmlinkage int sys_statfs(const char * path, struct statfs * buf); + length = ((unsigned long) length_hi << 32) | (unsigned int) length_lo; -asmlinkage int -sys32_statfs(const char * path, struct statfs32 *buf) -{ - int ret; - struct statfs s; - mm_segment_t old_fs = get_fs(); - - set_fs (KERNEL_DS); - ret = sys_statfs((const char *)path, &s); - set_fs (old_fs); - if (put_statfs(buf, &s)) - return -EFAULT; - return ret; + return sys_truncate(path, length); } -extern asmlinkage int sys_fstatfs(unsigned int fd, struct statfs * buf); - -asmlinkage int -sys32_fstatfs(unsigned int fd, struct statfs32 *buf) +#ifdef __MIPSEB__ +asmlinkage long sys32_ftruncate64(unsigned int fd, unsigned long __dummy, + int length_hi, int length_lo) +#endif +#ifdef __MIPSEL__ +asmlinkage long sys32_ftruncate64(unsigned int fd, unsigned long __dummy, + int length_lo, int length_hi) +#endif { - int ret; - struct statfs s; - mm_segment_t old_fs = get_fs(); - - set_fs (KERNEL_DS); - ret = sys_fstatfs(fd, &s); - set_fs (old_fs); - if (put_statfs(buf, &s)) - return -EFAULT; - return ret; -} - -extern asmlinkage int -sys_getrusage(int who, struct rusage *ru); + loff_t length; -asmlinkage int -sys32_getrusage(int who, struct rusage32 *ru) -{ - struct rusage r; - int ret; - mm_segment_t old_fs = get_fs(); - - set_fs (KERNEL_DS); - ret = sys_getrusage(who, &r); - set_fs (old_fs); - if (put_rusage (ru, &r)) - return -EFAULT; + length = ((unsigned long) length_hi << 32) | (unsigned int) length_lo; - return ret; + return sys_ftruncate(fd, length); } static inline long @@ -658,31 +578,7 @@ put_tv32(struct compat_timeval *o, struc __put_user(i->tv_usec, &o->tv_usec))); } -asmlinkage unsigned long -sys32_alarm(unsigned int seconds) -{ - struct itimerval it_new, it_old; - unsigned int oldalarm; - - it_new.it_interval.tv_sec = it_new.it_interval.tv_usec = 0; - it_new.it_value.tv_sec = seconds; - it_new.it_value.tv_usec = 0; - do_setitimer(ITIMER_REAL, &it_new, &it_old); - oldalarm = it_old.it_value.tv_sec; - /* ehhh.. We can't return 0 if we have an alarm pending.. */ - /* And we'd better return too much than too little anyway */ - if (it_old.it_value.tv_usec) - oldalarm++; - - return oldalarm; -} - -/* Translations due to time_t size differences. Which affects all - sorts of things, like timeval and itimerval. */ - - extern struct timezone sys_tz; -extern int do_sys_settimeofday(struct timeval *tv, struct timezone *tz); asmlinkage int sys32_gettimeofday(struct compat_timeval *tv, struct timezone *tz) @@ -700,14 +596,28 @@ sys32_gettimeofday(struct compat_timeval return 0; } +static inline long get_ts32(struct timespec *o, struct compat_timeval *i) +{ + long usec; + + if (!access_ok(VERIFY_READ, i, sizeof(*i))) + return -EFAULT; + if (__get_user(o->tv_sec, &i->tv_sec)) + return -EFAULT; + if (__get_user(usec, &i->tv_usec)) + return -EFAULT; + o->tv_nsec = usec * 1000; + return 0; +} + asmlinkage int sys32_settimeofday(struct compat_timeval *tv, struct timezone *tz) { - struct timeval ktv; + struct timespec kts; struct timezone ktz; if (tv) { - if (get_tv32(&ktv, tv)) + if (get_ts32(&kts, tv)) return -EFAULT; } if (tz) { @@ -715,16 +625,16 @@ sys32_settimeofday(struct compat_timeval return -EFAULT; } - return do_sys_settimeofday(tv ? &ktv : NULL, tz ? &ktz : NULL); + return do_sys_settimeofday(tv ? &kts : NULL, tz ? &ktz : NULL); } extern asmlinkage long sys_llseek(unsigned int fd, unsigned long offset_high, unsigned long offset_low, loff_t * result, unsigned int origin); -extern asmlinkage int sys32_llseek(unsigned int fd, unsigned int offset_high, - unsigned int offset_low, loff_t * result, - unsigned int origin) +asmlinkage int sys32_llseek(unsigned int fd, unsigned int offset_high, + unsigned int offset_low, loff_t * result, + unsigned int origin) { return sys_llseek(fd, offset_high, offset_low, result, origin); } @@ -805,7 +715,7 @@ do_readv_writev32(int type, struct file /* VERIFY_WRITE actually means a read, as we write to user space */ fn = file->f_op->read; if (type == VERIFY_READ) - fn = (IO_fn_t) file->f_op->write; + fn = (IO_fn_t) file->f_op->write; ivp = iov; while (count > 0) { void * base; @@ -876,11 +786,12 @@ bad_file: non-seekable files. */ asmlinkage ssize_t sys32_pread(unsigned int fd, char * buf, - size_t count, u32 unused, loff_t pos) + size_t count, u32 unused, u64 a4, u64 a5) { ssize_t ret; struct file * file; ssize_t (*read)(struct file *, char *, size_t, loff_t *); + loff_t pos; ret = -EBADF; file = fget(fd); @@ -888,6 +799,7 @@ asmlinkage ssize_t sys32_pread(unsigned goto bad_file; if (!(file->f_mode & FMODE_READ)) goto out; + pos = merge_64(a4, a5); ret = locks_verify_area(FLOCK_VERIFY_READ, file->f_dentry->d_inode, file, pos, count); if (ret) @@ -907,11 +819,12 @@ bad_file: } asmlinkage ssize_t sys32_pwrite(unsigned int fd, const char * buf, - size_t count, u32 unused, loff_t pos) + size_t count, u32 unused, u64 a4, u64 a5) { ssize_t ret; struct file * file; ssize_t (*write)(struct file *, const char *, size_t, loff_t *); + loff_t pos; ret = -EBADF; file = fget(fd); @@ -919,6 +832,7 @@ asmlinkage ssize_t sys32_pwrite(unsigned goto bad_file; if (!(file->f_mode & FMODE_WRITE)) goto out; + pos = merge_64(a4, a5); ret = locks_verify_area(FLOCK_VERIFY_WRITE, file->f_dentry->d_inode, file, pos, count); if (ret) @@ -945,7 +859,6 @@ bad_file: static inline int get_fd_set32(unsigned long n, unsigned long *fdset, u32 *ufdset) { -#ifdef __MIPSEB__ if (ufdset) { unsigned long odd; @@ -972,9 +885,6 @@ get_fd_set32(unsigned long n, unsigned l memset(fdset, 0, ((n + 1) & ~1)*sizeof(u32)); } return 0; -#else - <> -#endif } static inline void @@ -1047,7 +957,7 @@ asmlinkage int sys32_select(int n, u32 * /* * We need 6 bitmaps (in/out/ex for both incoming and outgoing), * since we used fdset we need to allocate memory in units of - * long-words. + * long-words. */ ret = -ENOMEM; size = FDS_BYTES(n); @@ -1105,15 +1015,15 @@ out_nofds: extern asmlinkage int sys_sched_rr_get_interval(pid_t pid, - struct timespec *interval); + struct timespec *interval); -asmlinkage int -sys32_sched_rr_get_interval(__kernel_pid_t32 pid, struct compat_timespec *interval) +asmlinkage int sys32_sched_rr_get_interval(__kernel_pid_t32 pid, + struct compat_timespec *interval) { struct timespec t; int ret; mm_segment_t old_fs = get_fs (); - + set_fs (KERNEL_DS); ret = sys_sched_rr_get_interval(pid, &t); set_fs (old_fs); @@ -1123,113 +1033,6 @@ sys32_sched_rr_get_interval(__kernel_pid return ret; } - -struct tms32 { - int tms_utime; - int tms_stime; - int tms_cutime; - int tms_cstime; -}; - -extern asmlinkage long sys_times(struct tms * tbuf); -asmlinkage long sys32_times(struct tms32 *tbuf) -{ - struct tms t; - long ret; - mm_segment_t old_fs = get_fs(); - int err; - - set_fs(KERNEL_DS); - ret = sys_times(tbuf ? &t : NULL); - set_fs(old_fs); - if (tbuf) { - err = put_user (t.tms_utime, &tbuf->tms_utime); - err |= __put_user (t.tms_stime, &tbuf->tms_stime); - err |= __put_user (t.tms_cutime, &tbuf->tms_cutime); - err |= __put_user (t.tms_cstime, &tbuf->tms_cstime); - if (err) - ret = -EFAULT; - } - return ret; -} - -struct flock32 { - short l_type; - short l_whence; - __kernel_off_t32 l_start; - __kernel_off_t32 l_len; - __kernel_pid_t32 l_pid; - short __unused; -}; - -static inline int get_flock(struct flock *kfl, struct flock32 *ufl) -{ - int err; - - err = get_user(kfl->l_type, &ufl->l_type); - err |= __get_user(kfl->l_whence, &ufl->l_whence); - err |= __get_user(kfl->l_start, &ufl->l_start); - err |= __get_user(kfl->l_len, &ufl->l_len); - err |= __get_user(kfl->l_pid, &ufl->l_pid); - return err; -} - -static inline int put_flock(struct flock *kfl, struct flock32 *ufl) -{ - int err; - - err = __put_user(kfl->l_type, &ufl->l_type); - err |= __put_user(kfl->l_whence, &ufl->l_whence); - err |= __put_user(kfl->l_start, &ufl->l_start); - err |= __put_user(kfl->l_len, &ufl->l_len); - err |= __put_user(kfl->l_pid, &ufl->l_pid); - return err; -} - -extern asmlinkage long -sys_fcntl(unsigned int fd, unsigned int cmd, unsigned long arg); - -asmlinkage long -sys32_fcntl(unsigned int fd, unsigned int cmd, unsigned long arg) -{ - switch (cmd) { - case F_GETLK: - case F_SETLK: - case F_SETLKW: - { - struct flock f; - mm_segment_t old_fs; - long ret; - - if (get_flock(&f, (struct flock32 *)arg)) - return -EFAULT; - old_fs = get_fs(); set_fs (KERNEL_DS); - ret = sys_fcntl(fd, cmd, (unsigned long)&f); - set_fs (old_fs); - if (put_flock(&f, (struct flock32 *)arg)) - return -EFAULT; - return ret; - } - default: - return sys_fcntl(fd, cmd, (unsigned long)arg); - } -} - -asmlinkage long -sys32_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg) -{ - switch (cmd) { - case F_GETLK64: - return sys_fcntl(fd, F_GETLK, arg); - case F_SETLK64: - return sys_fcntl(fd, F_SETLK, arg); - case F_SETLKW64: - return sys_fcntl(fd, F_SETLKW, arg); - } - - return sys32_fcntl(fd, cmd, arg); -} - struct msgbuf32 { s32 mtype; char mtext[1]; }; struct ipc_perm32 @@ -1243,6 +1046,19 @@ struct ipc_perm32 unsigned short seq; }; +struct ipc64_perm32 { + key_t key; + __kernel_uid_t32 uid; + __kernel_gid_t32 gid; + __kernel_uid_t32 cuid; + __kernel_gid_t32 cgid; + __kernel_mode_t32 mode; + unsigned short seq; + unsigned short __pad1; + unsigned int __unused1; + unsigned int __unused2; +}; + struct semid_ds32 { struct ipc_perm32 sem_perm; /* permissions .. see ipc.h */ compat_time_t sem_otime; /* last semop time */ @@ -1254,6 +1070,15 @@ struct semid_ds32 { unsigned short sem_nsems; /* no. of semaphores in array */ }; +struct semid64_ds32 { + struct ipc64_perm32 sem_perm; + compat_time_t sem_otime; + compat_time_t sem_ctime; + unsigned int sem_nsems; + unsigned int __unused1; + unsigned int __unused2; +}; + struct msqid_ds32 { struct ipc_perm32 msg_perm; @@ -1265,24 +1090,57 @@ struct msqid_ds32 u32 wwait; u32 rwait; unsigned short msg_cbytes; - unsigned short msg_qnum; + unsigned short msg_qnum; unsigned short msg_qbytes; __kernel_ipc_pid_t32 msg_lspid; __kernel_ipc_pid_t32 msg_lrpid; }; +struct msqid64_ds32 { + struct ipc64_perm32 msg_perm; + compat_time_t msg_stime; + unsigned int __unused1; + compat_time_t msg_rtime; + unsigned int __unused2; + compat_time_t msg_ctime; + unsigned int __unused3; + unsigned int msg_cbytes; + unsigned int msg_qnum; + unsigned int msg_qbytes; + __kernel_pid_t32 msg_lspid; + __kernel_pid_t32 msg_lrpid; + unsigned int __unused4; + unsigned int __unused5; +}; + struct shmid_ds32 { struct ipc_perm32 shm_perm; int shm_segsz; - compat_time_t shm_atime; - compat_time_t shm_dtime; - compat_time_t shm_ctime; - __kernel_ipc_pid_t32 shm_cpid; - __kernel_ipc_pid_t32 shm_lpid; + compat_time_t shm_atime; + compat_time_t shm_dtime; + compat_time_t shm_ctime; + __kernel_ipc_pid_t32 shm_cpid; + __kernel_ipc_pid_t32 shm_lpid; unsigned short shm_nattch; }; -#define IPCOP_MASK(__x) (1UL << (__x)) +struct shmid64_ds32 { + struct ipc64_perm32 shm_perm; + compat_size_t shm_segsz; + compat_time_t shm_atime; + compat_time_t shm_dtime; + compat_time_t shm_ctime; + __kernel_pid_t32 shm_cpid; + __kernel_pid_t32 shm_lpid; + unsigned int shm_nattch; + unsigned int __unused1; + unsigned int __unused2; +}; + +struct ipc_kludge32 { + u32 msgp; + s32 msgtyp; +}; static int do_sys32_semctl(int first, int second, int third, void *uptr) @@ -1291,7 +1149,6 @@ do_sys32_semctl(int first, int second, i u32 pad; int err, err2; struct semid64_ds s; - struct semid_ds32 *usp; mm_segment_t old_fs; if (!uptr) @@ -1304,7 +1161,6 @@ do_sys32_semctl(int first, int second, i else fourth.__pad = (void *)A(pad); switch (third & ~IPC_64) { - case IPC_INFO: case IPC_RMID: case IPC_SET: @@ -1321,29 +1177,54 @@ do_sys32_semctl(int first, int second, i case IPC_STAT: case SEM_STAT: - usp = (struct semid_ds32 *)A(pad); fourth.__pad = &s; old_fs = get_fs (); set_fs (KERNEL_DS); err = sys_semctl (first, second, third, fourth); set_fs (old_fs); - err2 = put_user(s.sem_perm.key, &usp->sem_perm.key); - err2 |= __put_user(s.sem_perm.uid, &usp->sem_perm.uid); - err2 |= __put_user(s.sem_perm.gid, &usp->sem_perm.gid); - err2 |= __put_user(s.sem_perm.cuid, - &usp->sem_perm.cuid); - err2 |= __put_user (s.sem_perm.cgid, - &usp->sem_perm.cgid); - err2 |= __put_user (s.sem_perm.mode, - &usp->sem_perm.mode); - err2 |= __put_user (s.sem_perm.seq, &usp->sem_perm.seq); - err2 |= __put_user (s.sem_otime, &usp->sem_otime); - err2 |= __put_user (s.sem_ctime, &usp->sem_ctime); - err2 |= __put_user (s.sem_nsems, &usp->sem_nsems); + + if (third & IPC_64) { + struct semid64_ds32 *usp64 = (struct semid64_ds32 *) A(pad); + + if (!access_ok(VERIFY_WRITE, usp64, sizeof(*usp64))) { + err = -EFAULT; + break; + } + err2 = __put_user(s.sem_perm.key, &usp64->sem_perm.key); + err2 |= __put_user(s.sem_perm.uid, &usp64->sem_perm.uid); + err2 |= __put_user(s.sem_perm.gid, &usp64->sem_perm.gid); + err2 |= __put_user(s.sem_perm.cuid, &usp64->sem_perm.cuid); + err2 |= __put_user(s.sem_perm.cgid, &usp64->sem_perm.cgid); + err2 |= __put_user(s.sem_perm.mode, &usp64->sem_perm.mode); + err2 |= __put_user(s.sem_perm.seq, &usp64->sem_perm.seq); + err2 |= __put_user(s.sem_otime, &usp64->sem_otime); + err2 |= __put_user(s.sem_ctime, &usp64->sem_ctime); + err2 |= __put_user(s.sem_nsems, &usp64->sem_nsems); + } else { + struct semid_ds32 *usp32 = (struct semid_ds32 *) A(pad); + + if (!access_ok(VERIFY_WRITE, usp32, sizeof(*usp32))) { + err = -EFAULT; + break; + } + err2 = __put_user(s.sem_perm.key, &usp32->sem_perm.key); + err2 |= __put_user(s.sem_perm.uid, &usp32->sem_perm.uid); + err2 |= __put_user(s.sem_perm.gid, &usp32->sem_perm.gid); + err2 |= __put_user(s.sem_perm.cuid, &usp32->sem_perm.cuid); + err2 |= __put_user(s.sem_perm.cgid, &usp32->sem_perm.cgid); + err2 |= __put_user(s.sem_perm.mode, &usp32->sem_perm.mode); + err2 |= __put_user(s.sem_perm.seq, &usp32->sem_perm.seq); + err2 |= __put_user(s.sem_otime, &usp32->sem_otime); + err2 |= __put_user(s.sem_ctime, &usp32->sem_ctime); + err2 |= __put_user(s.sem_nsems, &usp32->sem_nsems); + } if (err2) err = -EFAULT; break; + default: + err = - EINVAL; + break; } return err; @@ -1352,15 +1233,20 @@ do_sys32_semctl(int first, int second, i static int do_sys32_msgsnd (int first, int second, int third, void *uptr) { - struct msgbuf *p = kmalloc (second + sizeof (struct msgbuf) - + 4, GFP_USER); struct msgbuf32 *up = (struct msgbuf32 *)uptr; + struct msgbuf *p; mm_segment_t old_fs; int err; + if (second < 0) + return -EINVAL; + p = kmalloc (second + sizeof (struct msgbuf) + + 4, GFP_USER); if (!p) return -ENOMEM; err = get_user (p->mtype, &up->mtype); + if (err) + goto out; err |= __copy_from_user (p->mtext, &up->mtext, second); if (err) goto out; @@ -1370,6 +1256,7 @@ do_sys32_msgsnd (int first, int second, set_fs (old_fs); out: kfree (p); + return err; } @@ -1383,18 +1270,21 @@ do_sys32_msgrcv (int first, int second, int err; if (!version) { - struct ipc_kludge *uipck = (struct ipc_kludge *)uptr; - struct ipc_kludge ipck; + struct ipc_kludge32 *uipck = (struct ipc_kludge32 *)uptr; + struct ipc_kludge32 ipck; err = -EINVAL; if (!uptr) goto out; err = -EFAULT; - if (copy_from_user (&ipck, uipck, sizeof (struct ipc_kludge))) + if (copy_from_user (&ipck, uipck, sizeof (struct ipc_kludge32))) goto out; - uptr = (void *)A(ipck.msgp); + uptr = (void *)AA(ipck.msgp); msgtyp = ipck.msgtyp; } + + if (second < 0) + return -EINVAL; err = -ENOMEM; p = kmalloc (second + sizeof (struct msgbuf) + 4, GFP_USER); if (!p) @@ -1419,13 +1309,12 @@ static int do_sys32_msgctl (int first, int second, void *uptr) { int err = -EINVAL, err2; - struct msqid_ds m; - struct msqid64_ds m64; - struct msqid_ds32 *up = (struct msqid_ds32 *)uptr; + struct msqid64_ds m; + struct msqid_ds32 *up32 = (struct msqid_ds32 *)uptr; + struct msqid64_ds32 *up64 = (struct msqid64_ds32 *)uptr; mm_segment_t old_fs; - switch (second) { - + switch (second & ~IPC_64) { case IPC_INFO: case IPC_RMID: case MSG_INFO: @@ -1433,15 +1322,30 @@ do_sys32_msgctl (int first, int second, break; case IPC_SET: - err = get_user (m.msg_perm.uid, &up->msg_perm.uid); - err |= __get_user (m.msg_perm.gid, &up->msg_perm.gid); - err |= __get_user (m.msg_perm.mode, &up->msg_perm.mode); - err |= __get_user (m.msg_qbytes, &up->msg_qbytes); + if (second & IPC_64) { + if (!access_ok(VERIFY_READ, up64, sizeof(*up64))) { + err = -EFAULT; + break; + } + err = __get_user(m.msg_perm.uid, &up64->msg_perm.uid); + err |= __get_user(m.msg_perm.gid, &up64->msg_perm.gid); + err |= __get_user(m.msg_perm.mode, &up64->msg_perm.mode); + err |= __get_user(m.msg_qbytes, &up64->msg_qbytes); + } else { + if (!access_ok(VERIFY_READ, up32, sizeof(*up32))) { + err = -EFAULT; + break; + } + err = __get_user(m.msg_perm.uid, &up32->msg_perm.uid); + err |= __get_user(m.msg_perm.gid, &up32->msg_perm.gid); + err |= __get_user(m.msg_perm.mode, &up32->msg_perm.mode); + err |= __get_user(m.msg_qbytes, &up32->msg_qbytes); + } if (err) break; old_fs = get_fs (); set_fs (KERNEL_DS); - err = sys_msgctl (first, second, &m); + err = sys_msgctl (first, second, (struct msqid_ds *)&m); set_fs (old_fs); break; @@ -1449,27 +1353,54 @@ do_sys32_msgctl (int first, int second, case MSG_STAT: old_fs = get_fs (); set_fs (KERNEL_DS); - err = sys_msgctl (first, second, (void *) &m64); + err = sys_msgctl (first, second, (struct msqid_ds *)&m); set_fs (old_fs); - err2 = put_user (m64.msg_perm.key, &up->msg_perm.key); - err2 |= __put_user(m64.msg_perm.uid, &up->msg_perm.uid); - err2 |= __put_user(m64.msg_perm.gid, &up->msg_perm.gid); - err2 |= __put_user(m64.msg_perm.cuid, &up->msg_perm.cuid); - err2 |= __put_user(m64.msg_perm.cgid, &up->msg_perm.cgid); - err2 |= __put_user(m64.msg_perm.mode, &up->msg_perm.mode); - err2 |= __put_user(m64.msg_perm.seq, &up->msg_perm.seq); - err2 |= __put_user(m64.msg_stime, &up->msg_stime); - err2 |= __put_user(m64.msg_rtime, &up->msg_rtime); - err2 |= __put_user(m64.msg_ctime, &up->msg_ctime); - err2 |= __put_user(m64.msg_cbytes, &up->msg_cbytes); - err2 |= __put_user(m64.msg_qnum, &up->msg_qnum); - err2 |= __put_user(m64.msg_qbytes, &up->msg_qbytes); - err2 |= __put_user(m64.msg_lspid, &up->msg_lspid); - err2 |= __put_user(m64.msg_lrpid, &up->msg_lrpid); - if (err2) - err = -EFAULT; + if (second & IPC_64) { + if (!access_ok(VERIFY_WRITE, up64, sizeof(*up64))) { + err = -EFAULT; + break; + } + err2 = __put_user(m.msg_perm.key, &up64->msg_perm.key); + err2 |= __put_user(m.msg_perm.uid, &up64->msg_perm.uid); + err2 |= __put_user(m.msg_perm.gid, &up64->msg_perm.gid); + err2 |= __put_user(m.msg_perm.cuid, &up64->msg_perm.cuid); + err2 |= __put_user(m.msg_perm.cgid, &up64->msg_perm.cgid); + err2 |= __put_user(m.msg_perm.mode, &up64->msg_perm.mode); + err2 |= __put_user(m.msg_perm.seq, &up64->msg_perm.seq); + err2 |= __put_user(m.msg_stime, &up64->msg_stime); + err2 |= __put_user(m.msg_rtime, &up64->msg_rtime); + err2 |= __put_user(m.msg_ctime, &up64->msg_ctime); + err2 |= __put_user(m.msg_cbytes, &up64->msg_cbytes); + err2 |= __put_user(m.msg_qnum, &up64->msg_qnum); + err2 |= __put_user(m.msg_qbytes, &up64->msg_qbytes); + err2 |= __put_user(m.msg_lspid, &up64->msg_lspid); + err2 |= __put_user(m.msg_lrpid, &up64->msg_lrpid); + if (err2) + err = -EFAULT; + } else { + if (!access_ok(VERIFY_WRITE, up32, sizeof(*up32))) { + err = -EFAULT; + break; + } + err2 = __put_user(m.msg_perm.key, &up32->msg_perm.key); + err2 |= __put_user(m.msg_perm.uid, &up32->msg_perm.uid); + err2 |= __put_user(m.msg_perm.gid, &up32->msg_perm.gid); + err2 |= __put_user(m.msg_perm.cuid, &up32->msg_perm.cuid); + err2 |= __put_user(m.msg_perm.cgid, &up32->msg_perm.cgid); + err2 |= __put_user(m.msg_perm.mode, &up32->msg_perm.mode); + err2 |= __put_user(m.msg_perm.seq, &up32->msg_perm.seq); + err2 |= __put_user(m.msg_stime, &up32->msg_stime); + err2 |= __put_user(m.msg_rtime, &up32->msg_rtime); + err2 |= __put_user(m.msg_ctime, &up32->msg_ctime); + err2 |= __put_user(m.msg_cbytes, &up32->msg_cbytes); + err2 |= __put_user(m.msg_qnum, &up32->msg_qnum); + err2 |= __put_user(m.msg_qbytes, &up32->msg_qbytes); + err2 |= __put_user(m.msg_lspid, &up32->msg_lspid); + err2 |= __put_user(m.msg_lrpid, &up32->msg_lrpid); + if (err2) + err = -EFAULT; + } break; - } return err; @@ -1499,7 +1430,8 @@ do_sys32_shmctl (int first, int second, int err = -EFAULT, err2; struct shmid_ds s; struct shmid64_ds s64; - struct shmid_ds32 *up = (struct shmid_ds32 *)uptr; + struct shmid_ds32 *up32 = (struct shmid_ds32 *)uptr; + struct shmid64_ds32 *up64 = (struct shmid64_ds32 *)uptr; mm_segment_t old_fs; struct shm_info32 { int used_ids; @@ -1508,18 +1440,24 @@ do_sys32_shmctl (int first, int second, } *uip = (struct shm_info32 *)uptr; struct shm_info si; - switch (second) { - + switch (second & ~IPC_64) { case IPC_INFO: + second = IPC_INFO; /* So that we don't have to translate it */ case IPC_RMID: case SHM_LOCK: case SHM_UNLOCK: err = sys_shmctl (first, second, (struct shmid_ds *)uptr); break; case IPC_SET: - err = get_user (s.shm_perm.uid, &up->shm_perm.uid); - err |= __get_user (s.shm_perm.gid, &up->shm_perm.gid); - err |= __get_user (s.shm_perm.mode, &up->shm_perm.mode); + if (second & IPC_64) { + err = get_user(s.shm_perm.uid, &up64->shm_perm.uid); + err |= get_user(s.shm_perm.gid, &up64->shm_perm.gid); + err |= get_user(s.shm_perm.mode, &up64->shm_perm.mode); + } else { + err = get_user(s.shm_perm.uid, &up32->shm_perm.uid); + err |= get_user(s.shm_perm.gid, &up32->shm_perm.gid); + err |= get_user(s.shm_perm.mode, &up32->shm_perm.mode); + } if (err) break; old_fs = get_fs (); @@ -1536,23 +1474,45 @@ do_sys32_shmctl (int first, int second, set_fs (old_fs); if (err < 0) break; - err2 = put_user (s64.shm_perm.key, &up->shm_perm.key); - err2 |= __put_user (s64.shm_perm.uid, &up->shm_perm.uid); - err2 |= __put_user (s64.shm_perm.gid, &up->shm_perm.gid); - err2 |= __put_user (s64.shm_perm.cuid, - &up->shm_perm.cuid); - err2 |= __put_user (s64.shm_perm.cgid, - &up->shm_perm.cgid); - err2 |= __put_user (s64.shm_perm.mode, - &up->shm_perm.mode); - err2 |= __put_user (s64.shm_perm.seq, &up->shm_perm.seq); - err2 |= __put_user (s64.shm_atime, &up->shm_atime); - err2 |= __put_user (s64.shm_dtime, &up->shm_dtime); - err2 |= __put_user (s64.shm_ctime, &up->shm_ctime); - err2 |= __put_user (s64.shm_segsz, &up->shm_segsz); - err2 |= __put_user (s64.shm_nattch, &up->shm_nattch); - err2 |= __put_user (s64.shm_cpid, &up->shm_cpid); - err2 |= __put_user (s64.shm_lpid, &up->shm_lpid); + if (second & IPC_64) { + if (!access_ok(VERIFY_WRITE, up64, sizeof(*up64))) { + err = -EFAULT; + break; + } + err2 = __put_user(s64.shm_perm.key, &up64->shm_perm.key); + err2 |= __put_user(s64.shm_perm.uid, &up64->shm_perm.uid); + err2 |= __put_user(s64.shm_perm.gid, &up64->shm_perm.gid); + err2 |= __put_user(s64.shm_perm.cuid, &up64->shm_perm.cuid); + err2 |= __put_user(s64.shm_perm.cgid, &up64->shm_perm.cgid); + err2 |= __put_user(s64.shm_perm.mode, &up64->shm_perm.mode); + err2 |= __put_user(s64.shm_perm.seq, &up64->shm_perm.seq); + err2 |= __put_user(s64.shm_atime, &up64->shm_atime); + err2 |= __put_user(s64.shm_dtime, &up64->shm_dtime); + err2 |= __put_user(s64.shm_ctime, &up64->shm_ctime); + err2 |= __put_user(s64.shm_segsz, &up64->shm_segsz); + err2 |= __put_user(s64.shm_nattch, &up64->shm_nattch); + err2 |= __put_user(s64.shm_cpid, &up64->shm_cpid); + err2 |= __put_user(s64.shm_lpid, &up64->shm_lpid); + } else { + if (!access_ok(VERIFY_WRITE, up32, sizeof(*up32))) { + err = -EFAULT; + break; + } + err2 = __put_user(s64.shm_perm.key, &up32->shm_perm.key); + err2 |= __put_user(s64.shm_perm.uid, &up32->shm_perm.uid); + err2 |= __put_user(s64.shm_perm.gid, &up32->shm_perm.gid); + err2 |= __put_user(s64.shm_perm.cuid, &up32->shm_perm.cuid); + err2 |= __put_user(s64.shm_perm.cgid, &up32->shm_perm.cgid); + err2 |= __put_user(s64.shm_perm.mode, &up32->shm_perm.mode); + err2 |= __put_user(s64.shm_perm.seq, &up32->shm_perm.seq); + err2 |= __put_user(s64.shm_atime, &up32->shm_atime); + err2 |= __put_user(s64.shm_dtime, &up32->shm_dtime); + err2 |= __put_user(s64.shm_ctime, &up32->shm_ctime); + err2 |= __put_user(s64.shm_segsz, &up32->shm_segsz); + err2 |= __put_user(s64.shm_nattch, &up32->shm_nattch); + err2 |= __put_user(s64.shm_cpid, &up32->shm_cpid); + err2 |= __put_user(s64.shm_lpid, &up32->shm_lpid); + } if (err2) err = -EFAULT; break; @@ -1576,7 +1536,11 @@ do_sys32_shmctl (int first, int second, err = -EFAULT; break; + default: + err = -ENOSYS; + break; } + return err; } @@ -1592,7 +1556,7 @@ sys32_ipc (u32 call, int first, int seco case SEMOP: /* struct sembuf is the same on 32 and 64bit :)) */ - err = sys_semop (first, (struct sembuf *)A(ptr), + err = sys_semop (first, (struct sembuf *)AA(ptr), second); break; case SEMGET: @@ -1600,36 +1564,36 @@ sys32_ipc (u32 call, int first, int seco break; case SEMCTL: err = do_sys32_semctl (first, second, third, - (void *)A(ptr)); + (void *)AA(ptr)); break; case MSGSND: err = do_sys32_msgsnd (first, second, third, - (void *)A(ptr)); + (void *)AA(ptr)); break; case MSGRCV: err = do_sys32_msgrcv (first, second, fifth, third, - version, (void *)A(ptr)); + version, (void *)AA(ptr)); break; case MSGGET: err = sys_msgget ((key_t) first, second); break; case MSGCTL: - err = do_sys32_msgctl (first, second, (void *)A(ptr)); + err = do_sys32_msgctl (first, second, (void *)AA(ptr)); break; case SHMAT: err = do_sys32_shmat (first, second, third, - version, (void *)A(ptr)); + version, (void *)AA(ptr)); break; - case SHMDT: + case SHMDT: err = sys_shmdt ((char *)A(ptr)); break; case SHMGET: err = sys_shmget (first, second, third); break; case SHMCTL: - err = do_sys32_shmctl (first, second, (void *)A(ptr)); + err = do_sys32_shmctl (first, second, (void *)AA(ptr)); break; default: err = -EINVAL; @@ -1650,81 +1614,103 @@ struct sysctl_args32 unsigned int __unused[4]; }; -asmlinkage long sys32_sysctl(struct sysctl_args32 *uargs32) -{ - struct __sysctl_args kargs; - struct sysctl_args32 kargs32; - mm_segment_t old_fs; - int name[CTL_MAXNAME]; - size_t oldlen[1]; - int err, ret; - - ret = -EFAULT; - - memset(&kargs, 0, sizeof (kargs)); - - err = get_user(kargs32.name, &uargs32->name); - err |= __get_user(kargs32.nlen, &uargs32->nlen); - err |= __get_user(kargs32.oldval, &uargs32->oldval); - err |= __get_user(kargs32.oldlenp, &uargs32->oldlenp); - err |= __get_user(kargs32.newval, &uargs32->newval); - err |= __get_user(kargs32.newlen, &uargs32->newlen); - if (err) - goto out; +#ifdef CONFIG_SYSCTL - if (kargs32.nlen == 0 || kargs32.nlen >= CTL_MAXNAME) { - ret = -ENOTDIR; - goto out; - } +asmlinkage long sys32_sysctl(struct sysctl_args32 *args) +{ + struct sysctl_args32 tmp; + int error; + size_t oldlen, *oldlenp = NULL; + unsigned long addr = (((long)&args->__unused[0]) + 7) & ~7; - kargs.name = name; - kargs.nlen = kargs32.nlen; - if (copy_from_user(kargs.name, (int *)A(kargs32.name), - kargs32.nlen * sizeof(name) / sizeof(name[0]))) - goto out; + if (copy_from_user(&tmp, args, sizeof(tmp))) + return -EFAULT; - if (kargs32.oldval) { - if (!kargs32.oldlenp || get_user(oldlen[0], - (int *)A(kargs32.oldlenp))) + if (tmp.oldval && tmp.oldlenp) { + /* Duh, this is ugly and might not work if sysctl_args + is in read-only memory, but do_sysctl does indirectly + a lot of uaccess in both directions and we'd have to + basically copy the whole sysctl.c here, and + glibc's __sysctl uses rw memory for the structure + anyway. */ + if (get_user(oldlen, (u32 *)A(tmp.oldlenp)) || + put_user(oldlen, (size_t *)addr)) return -EFAULT; - kargs.oldlenp = oldlen; - kargs.oldval = kmalloc(oldlen[0], GFP_KERNEL); - if (!kargs.oldval) { - ret = -ENOMEM; - goto out; - } + oldlenp = (size_t *)addr; } - if (kargs32.newval && kargs32.newlen) { - kargs.newval = kmalloc(kargs32.newlen, GFP_KERNEL); - if (!kargs.newval) { - ret = -ENOMEM; - goto out; + lock_kernel(); + error = do_sysctl((int *)A(tmp.name), tmp.nlen, (void *)A(tmp.oldval), + oldlenp, (void *)A(tmp.newval), tmp.newlen); + unlock_kernel(); + if (oldlenp) { + if (!error) { + if (get_user(oldlen, (size_t *)addr) || + put_user(oldlen, (u32 *)A(tmp.oldlenp))) + error = -EFAULT; } - if (copy_from_user(kargs.newval, (int *)A(kargs32.newval), - kargs32.newlen)) - goto out; + copy_to_user(args->__unused, tmp.__unused, sizeof(tmp.__unused)); } + return error; +} - old_fs = get_fs(); set_fs (KERNEL_DS); - ret = sys_sysctl(&kargs); - set_fs (old_fs); +#else /* CONFIG_SYSCTL */ - if (ret) - goto out; +asmlinkage long sys32_sysctl(struct sysctl_args32 *args) +{ + return -ENOSYS; +} + +#endif /* CONFIG_SYSCTL */ + +extern asmlinkage int sys_sched_setaffinity(pid_t pid, unsigned int len, + unsigned long *user_mask_ptr); - if (kargs.oldval) { - if (put_user(oldlen[0], (int *)A(kargs32.oldlenp)) || - copy_to_user((int *)A(kargs32.oldval), kargs.oldval, - oldlen[0])) +asmlinkage int sys32_sched_setaffinity(__kernel_pid_t32 pid, unsigned int len, + u32 *user_mask_ptr) +{ + unsigned long kernel_mask; + mm_segment_t old_fs; + int ret; + + if (get_user(kernel_mask, user_mask_ptr)) + return -EFAULT; + + old_fs = get_fs(); + set_fs(KERNEL_DS); + ret = sys_sched_setaffinity(pid, + /* XXX Nice api... */ + sizeof(kernel_mask), + &kernel_mask); + set_fs(old_fs); + + return ret; +} + +extern asmlinkage int sys_sched_getaffinity(pid_t pid, unsigned int len, + unsigned long *user_mask_ptr); + +asmlinkage int sys32_sched_getaffinity(__kernel_pid_t32 pid, unsigned int len, + u32 *user_mask_ptr) +{ + unsigned long kernel_mask; + mm_segment_t old_fs; + int ret; + + old_fs = get_fs(); + set_fs(KERNEL_DS); + ret = sys_sched_getaffinity(pid, + /* XXX Nice api... */ + sizeof(kernel_mask), + &kernel_mask); + set_fs(old_fs); + + if (ret == 0) { + if (put_user(kernel_mask, user_mask_ptr)) ret = -EFAULT; } -out: - if (kargs.oldval) - kfree(kargs.oldval); - if (kargs.newval) - kfree(kargs.newval); - return ret; + + return ret; } asmlinkage long sys32_newuname(struct new_utsname * name) @@ -1780,7 +1766,7 @@ asmlinkage int sys32_adjtimex(struct tim memset(&txc, 0, sizeof(struct timex)); - if(get_user(txc.modes, &utp->modes) || + if (get_user(txc.modes, &utp->modes) || __get_user(txc.offset, &utp->offset) || __get_user(txc.freq, &utp->freq) || __get_user(txc.maxerror, &utp->maxerror) || @@ -1804,7 +1790,7 @@ asmlinkage int sys32_adjtimex(struct tim ret = do_adjtimex(&txc); - if(put_user(txc.modes, &utp->modes) || + if (put_user(txc.modes, &utp->modes) || __put_user(txc.offset, &utp->offset) || __put_user(txc.freq, &utp->freq) || __put_user(txc.maxerror, &utp->maxerror) || @@ -1829,3 +1815,31 @@ asmlinkage int sys32_adjtimex(struct tim return ret; } +extern asmlinkage ssize_t sys_sendfile(int out_fd, int in_fd, off_t *offset, size_t count); + +asmlinkage int sys32_sendfile(int out_fd, int in_fd, __kernel_off_t32 *offset, s32 count) +{ + mm_segment_t old_fs = get_fs(); + int ret; + off_t of; + + if (offset && get_user(of, offset)) + return -EFAULT; + + set_fs(KERNEL_DS); + ret = sys_sendfile(out_fd, in_fd, offset ? &of : NULL, count); + set_fs(old_fs); + + if (offset && put_user(of, offset)) + return -EFAULT; + + return ret; +} + +asmlinkage ssize_t sys_readahead(int fd, loff_t offset, size_t count); + +asmlinkage ssize_t sys32_readahead(int fd, u32 pad0, u64 a2, u64 a3, + size_t count) +{ + return sys_readahead(fd, merge_64(a2, a3), count); +} --- linux-2.5.73/arch/mips64/kernel/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -2,18 +2,29 @@ # Makefile for the Linux/MIPS kernel. # -extra-y := head.o init_task.o +extra-y := head.o init_task.o -obj-y := branch.o entry.o proc.o process.o ptrace.o r4k_cache.o r4k_fpu.o \ - r4k_genex.o r4k_switch.o r4k_tlb.o r4k_tlb_debug.o r4k_tlb_glue.o \ - scall_64.o semaphore.o setup.o signal.o softfp.o syscall.o \ - traps.o unaligned.o +obj-y := branch.o cpu-probe.o entry.o irq.o proc.o process.o \ + ptrace.o r4k_cache.o r4k_fpu.o r4k_genex.o r4k_switch.o \ + reset.o scall_64.o semaphore.o setup.o signal.o syscall.o \ + time.o traps.o unaligned.o + +obj-$(CONFIG_I8259) += i8259.o +obj-$(CONFIG_IRQ_CPU) += irq_cpu.o obj-$(CONFIG_MODULES) += mips64_ksyms.o -obj-$(CONFIG_MIPS32_COMPAT) += linux32.o scall_o32.o signal32.o ioctl32.o -obj-$(CONFIG_BINFMT_ELF32) += binfmt_elf32.o +obj-$(CONFIG_MIPS32_COMPAT) += linux32.o signal32.o ioctl32.o +obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall_n32.o +obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall_o32.o obj-$(CONFIG_SMP) += smp.o -AFLAGS_r4k_genex.o := -P -AFLAGS_r4k_tlb_glue.o := -P +ifndef CONFIG_MAPPED_PCI_IO +obj-y += pci-dma.o +endif + +obj-$(CONFIG_MODULES) += module.o + +CFLAGS_cpu-probe.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) +AFLAGS_r4k_genex.o = -P + EXTRA_AFLAGS := $(CFLAGS) --- linux-2.5.73/arch/mips64/kernel/mips64_ksyms.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/mips64_ksyms.c 2003-06-27 15:56:23.000000000 -0700 @@ -13,9 +13,9 @@ #include #include #include -#include #include #include +#include #include #include @@ -38,7 +38,10 @@ extern long __strnlen_user_nocheck_asm(c extern long __strnlen_user_asm(const char *s); EXPORT_SYMBOL(mips_machtype); + +#ifdef CONFIG_EISA EXPORT_SYMBOL(EISA_bus); +#endif /* * String functions @@ -53,12 +56,9 @@ EXPORT_SYMBOL_NOVERS(strlen); EXPORT_SYMBOL_NOVERS(strncat); EXPORT_SYMBOL_NOVERS(strnlen); EXPORT_SYMBOL_NOVERS(strrchr); -EXPORT_SYMBOL_NOVERS(strsep); EXPORT_SYMBOL_NOVERS(strpbrk); EXPORT_SYMBOL(_clear_page); -EXPORT_SYMBOL(enable_irq); -EXPORT_SYMBOL(disable_irq); EXPORT_SYMBOL(kernel_thread); /* @@ -74,43 +74,16 @@ EXPORT_SYMBOL_NOVERS(__strnlen_user_noch EXPORT_SYMBOL_NOVERS(__strnlen_user_asm); -/* - * Functions to control caches. - */ -EXPORT_SYMBOL(_flush_page_to_ram); -EXPORT_SYMBOL(_flush_cache_l1); -#ifndef CONFIG_COHERENT_IO -EXPORT_SYMBOL(_dma_cache_wback_inv); -EXPORT_SYMBOL(_dma_cache_inv); -#endif - EXPORT_SYMBOL(invalid_pte_table); /* - * Base address of ports for Intel style I/O. - */ -#if defined (CONFIG_PCI) || defined (CONFIG_ISA) -EXPORT_SYMBOL(mips_io_port_base); -#endif - -/* * Kernel hacking ... */ #include #include -int register_fpe(void (*handler)(struct pt_regs *regs, unsigned int fcr31)); -int unregister_fpe(void (*handler)(struct pt_regs *regs, unsigned int fcr31)); - -#ifdef CONFIG_MIPS_FPE_MODULE -EXPORT_SYMBOL(__compute_return_epc); -EXPORT_SYMBOL(register_fpe); -EXPORT_SYMBOL(unregister_fpe); -#endif - #ifdef CONFIG_VT EXPORT_SYMBOL(screen_info); #endif EXPORT_SYMBOL(get_wchan); -EXPORT_SYMBOL(_flush_tlb_page); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/kernel/module.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,349 @@ +/* Kernel module help for MIPS. + Copyright (C) 2001 Rusty Russell. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ +#include +#include +#include +#include +#include +#include +#include + +struct mips_hi16 { + struct mips_hi16 *next; + Elf32_Addr *addr; + Elf32_Addr value; +}; + +static struct mips_hi16 *mips_hi16_list; + +#if 0 +#define DEBUGP printk +#else +#define DEBUGP(fmt , ...) +#endif + +static struct vm_struct * modvmlist = NULL; + +void module_unmap(void * addr) +{ + struct vm_struct **p, *tmp; + int i; + + if (!addr) + return; + if ((PAGE_SIZE-1) & (unsigned long) addr) { + printk("Trying to unmap module with bad address (%p)\n", addr); + return; + } + + for (p = &modvmlist ; (tmp = *p) ; p = &tmp->next) { + if (tmp->addr == addr) { + *p = tmp->next; + goto found; + } + } + printk("Trying to unmap nonexistent module vm area (%p)\n", addr); + return; + +found: + unmap_vm_area(tmp); + + for (i = 0; i < tmp->nr_pages; i++) { + if (unlikely(!tmp->pages[i])) + BUG(); + __free_page(tmp->pages[i]); + } + + kfree(tmp->pages); + kfree(tmp); +} + +#define MODULES_LEN (512*1024*1024) /* Random silly large number */ +#define MODULES_END (512*1024*1024) /* Random silly large number */ +#define MODULES_VADDR (512*1024*1024) /* Random silly large number */ + +void *module_map(unsigned long size) +{ + struct vm_struct **p, *tmp, *area; + struct page **pages; + void * addr; + unsigned int nr_pages, array_size, i; + + size = PAGE_ALIGN(size); + if (!size || size > MODULES_LEN) + return NULL; + + addr = (void *) MODULES_VADDR; + for (p = &modvmlist; (tmp = *p) ; p = &tmp->next) { + if (size + (unsigned long) addr < (unsigned long) tmp->addr) + break; + addr = (void *) (tmp->size + (unsigned long) tmp->addr); + } + if ((unsigned long) addr + size >= MODULES_END) + return NULL; + + area = (struct vm_struct *) kmalloc(sizeof(*area), GFP_KERNEL); + if (!area) + return NULL; + area->size = size + PAGE_SIZE; + area->addr = addr; + area->next = *p; + area->pages = NULL; + area->nr_pages = 0; + area->phys_addr = 0; + *p = area; + + nr_pages = size >> PAGE_SHIFT; + array_size = (nr_pages * sizeof(struct page *)); + + area->nr_pages = nr_pages; + area->pages = pages = kmalloc(array_size, GFP_KERNEL); + if (!area->pages) + goto fail; + + memset(area->pages, 0, array_size); + + for (i = 0; i < area->nr_pages; i++) { + area->pages[i] = alloc_page(GFP_KERNEL); + if (unlikely(!area->pages[i])) + goto fail; + } + + if (map_vm_area(area, PAGE_KERNEL, &pages)) { + unmap_vm_area(area); + goto fail; + } + + return area->addr; + +fail: + if (area->pages) { + for (i = 0; i < area->nr_pages; i++) { + if (area->pages[i]) + __free_page(area->pages[i]); + } + kfree(area->pages); + } + kfree(area); + + return NULL; +} + +void *module_alloc(unsigned long size) +{ + if (size == 0) + return NULL; + return vmalloc(size); +} + + +/* Free memory returned from module_alloc */ +void module_free(struct module *mod, void *module_region) +{ + vfree(module_region); + /* FIXME: If module_region == mod->init_region, trim exception + table entries. */ +} + +/* We don't need anything special. */ +long module_core_size(const Elf32_Ehdr *hdr, + const Elf32_Shdr *sechdrs, + const char *secstrings, + struct module *module) +{ + return module->core_size; +} + +long module_init_size(const Elf32_Ehdr *hdr, + const Elf32_Shdr *sechdrs, + const char *secstrings, + struct module *module) +{ + return module->init_size; +} + +int module_frob_arch_sections(Elf_Ehdr *hdr, + Elf_Shdr *sechdrs, + char *secstrings, + struct module *mod) +{ + return 0; +} + +int apply_relocate(Elf32_Shdr *sechdrs, + const char *strtab, + unsigned int symindex, + unsigned int relsec, + struct module *me) +{ + unsigned int i; + Elf32_Rel *rel = (void *)sechdrs[relsec].sh_offset; + Elf32_Sym *sym; + uint32_t *location; + Elf32_Addr v; + + DEBUGP("Applying relocate section %u to %u\n", relsec, + sechdrs[relsec].sh_info); + for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { + /* This is where to make the change */ + location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_offset + + rel[i].r_offset; + /* This is the symbol it is referring to */ + sym = (Elf32_Sym *)sechdrs[symindex].sh_offset + + ELF32_R_SYM(rel[i].r_info); + if (!sym->st_value) { + printk(KERN_WARNING "%s: Unknown symbol %s\n", + me->name, strtab + sym->st_name); + return -ENOENT; + } + + v = sym->st_value; + + switch (ELF32_R_TYPE(rel[i].r_info)) { + case R_MIPS_NONE: + break; + + case R_MIPS_32: + *location += v; + break; + + case R_MIPS_26: + if (v % 4) + printk(KERN_ERR + "module %s: dangerous relocation\n", + me->name); + return -ENOEXEC; + if ((v & 0xf0000000) != + (((unsigned long)location + 4) & 0xf0000000)) + printk(KERN_ERR + "module %s: relocation overflow\n", + me->name); + return -ENOEXEC; + *location = (*location & ~0x03ffffff) | + ((*location + (v >> 2)) & 0x03ffffff); + break; + + case R_MIPS_HI16: { + struct mips_hi16 *n; + + /* + * We cannot relocate this one now because we don't + * know the value of the carry we need to add. Save + * the information, and let LO16 do the actual + * relocation. + */ + n = (struct mips_hi16 *) kmalloc(sizeof *n, GFP_KERNEL); + n->addr = location; + n->value = v; + n->next = mips_hi16_list; + mips_hi16_list = n; + break; + } + + case R_MIPS_LO16: { + unsigned long insnlo = *location; + Elf32_Addr val, vallo; + + /* Sign extend the addend we extract from the lo insn. */ + vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; + + if (mips_hi16_list != NULL) { + struct mips_hi16 *l; + + l = mips_hi16_list; + while (l != NULL) { + struct mips_hi16 *next; + unsigned long insn; + + /* + * The value for the HI16 had best be + * the same. + */ + printk(KERN_ERR "module %s: dangerous " + "relocation\n", me->name); + return -ENOEXEC; + + /* + * Do the HI16 relocation. Note that + * we actually don't need to know + * anything about the LO16 itself, + * except where to find the low 16 bits + * of the addend needed by the LO16. + */ + insn = *l->addr; + val = ((insn & 0xffff) << 16) + vallo; + val += v; + + /* + * Account for the sign extension that + * will happen in the low bits. + */ + val = ((val >> 16) + ((val & 0x8000) != + 0)) & 0xffff; + + insn = (insn & ~0xffff) | val; + *l->addr = insn; + + next = l->next; + kfree(l); + l = next; + } + + mips_hi16_list = NULL; + } + + /* + * Ok, we're done with the HI16 relocs. Now deal with + * the LO16. + */ + val = v + vallo; + insnlo = (insnlo & ~0xffff) | (val & 0xffff); + *location = insnlo; + break; + } + + default: + printk(KERN_ERR "module %s: Unknown relocation: %u\n", + me->name, ELF32_R_TYPE(rel[i].r_info)); + return -ENOEXEC; + } + } + return 0; +} + +int apply_relocate_add(Elf32_Shdr *sechdrs, + const char *strtab, + unsigned int symindex, + unsigned int relsec, + struct module *me) +{ + printk(KERN_ERR "module %s: ADD RELOCATION unsupported\n", + me->name); + return -ENOEXEC; +} + +int module_finalize(const Elf_Ehdr *hdr, + const Elf_Shdr *sechdrs, + struct module *me) +{ + return 0; +} + +void module_arch_cleanup(struct module *mod) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/kernel/offset.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,207 @@ +/* + * offset.c: Calculate pt_regs and task_struct offsets. + * + * Copyright (C) 1996 David S. Miller + * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * + * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. + */ +#include +#include +#include +#include + +#include +#include + +#define text(t) __asm__("\n@@@" t) +#define _offset(type, member) (&(((type *)NULL)->member)) + +#define offset(string, ptr, member) \ + __asm__("\n@@@" string "%0" : : "i" (_offset(ptr, member))) +#define constant(string, member) \ + __asm__("\n@@@" string "%x0" : : "i" (member)) +#define size(string, size) \ + __asm__("\n@@@" string "%0" : : "i" (sizeof(size))) +#define linefeed text("") + +void output_ptreg_defines(void) +{ + text("/* MIPS pt_regs offsets. */"); + offset("#define PT_R0 ", struct pt_regs, regs[0]); + offset("#define PT_R1 ", struct pt_regs, regs[1]); + offset("#define PT_R2 ", struct pt_regs, regs[2]); + offset("#define PT_R3 ", struct pt_regs, regs[3]); + offset("#define PT_R4 ", struct pt_regs, regs[4]); + offset("#define PT_R5 ", struct pt_regs, regs[5]); + offset("#define PT_R6 ", struct pt_regs, regs[6]); + offset("#define PT_R7 ", struct pt_regs, regs[7]); + offset("#define PT_R8 ", struct pt_regs, regs[8]); + offset("#define PT_R9 ", struct pt_regs, regs[9]); + offset("#define PT_R10 ", struct pt_regs, regs[10]); + offset("#define PT_R11 ", struct pt_regs, regs[11]); + offset("#define PT_R12 ", struct pt_regs, regs[12]); + offset("#define PT_R13 ", struct pt_regs, regs[13]); + offset("#define PT_R14 ", struct pt_regs, regs[14]); + offset("#define PT_R15 ", struct pt_regs, regs[15]); + offset("#define PT_R16 ", struct pt_regs, regs[16]); + offset("#define PT_R17 ", struct pt_regs, regs[17]); + offset("#define PT_R18 ", struct pt_regs, regs[18]); + offset("#define PT_R19 ", struct pt_regs, regs[19]); + offset("#define PT_R20 ", struct pt_regs, regs[20]); + offset("#define PT_R21 ", struct pt_regs, regs[21]); + offset("#define PT_R22 ", struct pt_regs, regs[22]); + offset("#define PT_R23 ", struct pt_regs, regs[23]); + offset("#define PT_R24 ", struct pt_regs, regs[24]); + offset("#define PT_R25 ", struct pt_regs, regs[25]); + offset("#define PT_R26 ", struct pt_regs, regs[26]); + offset("#define PT_R27 ", struct pt_regs, regs[27]); + offset("#define PT_R28 ", struct pt_regs, regs[28]); + offset("#define PT_R29 ", struct pt_regs, regs[29]); + offset("#define PT_R30 ", struct pt_regs, regs[30]); + offset("#define PT_R31 ", struct pt_regs, regs[31]); + offset("#define PT_LO ", struct pt_regs, lo); + offset("#define PT_HI ", struct pt_regs, hi); + offset("#define PT_EPC ", struct pt_regs, cp0_epc); + offset("#define PT_BVADDR ", struct pt_regs, cp0_badvaddr); + offset("#define PT_STATUS ", struct pt_regs, cp0_status); + offset("#define PT_CAUSE ", struct pt_regs, cp0_cause); + size("#define PT_SIZE ", struct pt_regs); + linefeed; +} + +void output_task_defines(void) +{ + text("/* MIPS task_struct offsets. */"); + offset("#define TASK_STATE ", struct task_struct, state); + offset("#define TASK_THREAD_INFO ", struct task_struct, thread_info); + offset("#define TASK_FLAGS ", struct task_struct, flags); + offset("#define TASK_MM ", struct task_struct, mm); + offset("#define TASK_PID ", struct task_struct, pid); + size( "#define TASK_STRUCT_SIZE ", struct task_struct); + linefeed; +} + +void output_thread_info_defines(void) +{ + text("/* MIPS thread_info offsets. */"); + offset("#define TI_TASK ", struct thread_info, task); + offset("#define TI_EXEC_DOMAIN ", struct thread_info, exec_domain); + offset("#define TI_FLAGS ", struct thread_info, flags); + offset("#define TI_CPU ", struct thread_info, cpu); + offset("#define TI_PRE_COUNT ", struct thread_info, preempt_count); + offset("#define TI_ADDR_LIMIT ", struct thread_info, addr_limit); + offset("#define TI_RESTART_BLOCK ", struct thread_info, restart_block); + linefeed; +} + +void output_thread_defines(void) +{ + text("/* MIPS specific thread_struct offsets. */"); + offset("#define THREAD_REG16 ", struct task_struct, thread.reg16); + offset("#define THREAD_REG17 ", struct task_struct, thread.reg17); + offset("#define THREAD_REG18 ", struct task_struct, thread.reg18); + offset("#define THREAD_REG19 ", struct task_struct, thread.reg19); + offset("#define THREAD_REG20 ", struct task_struct, thread.reg20); + offset("#define THREAD_REG21 ", struct task_struct, thread.reg21); + offset("#define THREAD_REG22 ", struct task_struct, thread.reg22); + offset("#define THREAD_REG23 ", struct task_struct, thread.reg23); + offset("#define THREAD_REG29 ", struct task_struct, thread.reg29); + offset("#define THREAD_REG30 ", struct task_struct, thread.reg30); + offset("#define THREAD_REG31 ", struct task_struct, thread.reg31); + offset("#define THREAD_STATUS ", struct task_struct, \ + thread.cp0_status); + offset("#define THREAD_FPU ", struct task_struct, thread.fpu); + offset("#define THREAD_BVADDR ", struct task_struct, \ + thread.cp0_badvaddr); + offset("#define THREAD_BUADDR ", struct task_struct, \ + thread.cp0_baduaddr); + offset("#define THREAD_ECODE ", struct task_struct, \ + thread.error_code); + offset("#define THREAD_TRAPNO ", struct task_struct, thread.trap_no); + offset("#define THREAD_MFLAGS ", struct task_struct, thread.mflags); + offset("#define THREAD_TRAMP ", struct task_struct, \ + thread.irix_trampoline); + offset("#define THREAD_OLDCTX ", struct task_struct, \ + thread.irix_oldctx); + linefeed; +} + +void output_mm_defines(void) +{ + text("/* Linux mm_struct offsets. */"); + offset("#define MM_USERS ", struct mm_struct, mm_users); + offset("#define MM_PGD ", struct mm_struct, pgd); + offset("#define MM_CONTEXT ", struct mm_struct, context); + linefeed; + constant("#define _PAGE_SIZE ", PAGE_SIZE); + constant("#define _PGD_ORDER ", PGD_ORDER); + constant("#define _PGDIR_SHIFT ", PGDIR_SHIFT); + linefeed; +} + +void output_sc_defines(void) +{ + text("/* Linux sigcontext offsets. */"); + offset("#define SC_REGS ", struct sigcontext, sc_regs); + offset("#define SC_FPREGS ", struct sigcontext, sc_fpregs); + offset("#define SC_MDHI ", struct sigcontext, sc_mdhi); + offset("#define SC_MDLO ", struct sigcontext, sc_mdlo); + offset("#define SC_PC ", struct sigcontext, sc_pc); + offset("#define SC_STATUS ", struct sigcontext, sc_status); + offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr); + offset("#define SC_FPC_EIR ", struct sigcontext, sc_fpc_eir); + offset("#define SC_CAUSE ", struct sigcontext, sc_cause); + offset("#define SC_BADVADDR ", struct sigcontext, sc_badvaddr); + linefeed; +} + +void output_signal_defined(void) +{ + text("/* Linux signal numbers. */"); + constant("#define _SIGHUP ", SIGHUP); + constant("#define _SIGINT ", SIGINT); + constant("#define _SIGQUIT ", SIGQUIT); + constant("#define _SIGILL ", SIGILL); + constant("#define _SIGTRAP ", SIGTRAP); + constant("#define _SIGIOT ", SIGIOT); + constant("#define _SIGABRT ", SIGABRT); + constant("#define _SIGEMT ", SIGEMT); + constant("#define _SIGFPE ", SIGFPE); + constant("#define _SIGKILL ", SIGKILL); + constant("#define _SIGBUS ", SIGBUS); + constant("#define _SIGSEGV ", SIGSEGV); + constant("#define _SIGSYS ", SIGSYS); + constant("#define _SIGPIPE ", SIGPIPE); + constant("#define _SIGALRM ", SIGALRM); + constant("#define _SIGTERM ", SIGTERM); + constant("#define _SIGUSR1 ", SIGUSR1); + constant("#define _SIGUSR2 ", SIGUSR2); + constant("#define _SIGCHLD ", SIGCHLD); + constant("#define _SIGPWR ", SIGPWR); + constant("#define _SIGWINCH ", SIGWINCH); + constant("#define _SIGURG ", SIGURG); + constant("#define _SIGIO ", SIGIO); + constant("#define _SIGSTOP ", SIGSTOP); + constant("#define _SIGTSTP ", SIGTSTP); + constant("#define _SIGCONT ", SIGCONT); + constant("#define _SIGTTIN ", SIGTTIN); + constant("#define _SIGTTOU ", SIGTTOU); + constant("#define _SIGVTALRM ", SIGVTALRM); + constant("#define _SIGPROF ", SIGPROF); + constant("#define _SIGXCPU ", SIGXCPU); + constant("#define _SIGXFSZ ", SIGXFSZ); + linefeed; +} + +void output_irq_cpustat_t_defines(void) +{ + text("/* Linux irq_cpustat_t offsets. */"); + offset("#define IC_SOFTIRQ_PENDING ", irq_cpustat_t, __softirq_pending); + offset("#define IC_SYSCALL_COUNT ", irq_cpustat_t, __syscall_count); + offset("#define IC_KSOFTIRQD_TASK ", irq_cpustat_t, __ksoftirqd_task); + size("#define IC_IRQ_CPUSTAT_T ", irq_cpustat_t); + linefeed; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/kernel/pci-dma.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,62 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Ani Joshi + * Copyright (C) 2000, 2001 Ralf Baechle + * swiped from i386, and cloned for MIPS by Geert, polished by Ralf. + */ +#include +#include +#include +#include +#include +#include + +#include + +#ifndef UNCAC_BASE /* Hack ... */ +#define UNCAC_BASE 0x9000000000000000UL +#endif + +void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, + dma_addr_t * dma_handle) +{ + void *ret; + int gfp = GFP_ATOMIC; + struct pci_bus *bus = NULL; + +#ifdef CONFIG_ISA + if (hwdev == NULL || hwdev->dma_mask != 0xffffffff) + gfp |= GFP_DMA; +#endif + ret = (void *) __get_free_pages(gfp, get_order(size)); + + if (ret != NULL) { + memset(ret, 0, size); + if (hwdev) + bus = hwdev->bus; + *dma_handle = bus_to_baddr(bus, __pa(ret)); +#ifdef CONFIG_NONCOHERENT_IO + dma_cache_wback_inv((unsigned long) ret, size); + ret = UNCAC_ADDR(ret); +#endif + } + + return ret; +} + +void pci_free_consistent(struct pci_dev *hwdev, size_t size, + void *vaddr, dma_addr_t dma_handle) +{ + unsigned long addr = (unsigned long) vaddr; + +#ifdef CONFIG_NONCOHERENT_IO + addr = CAC_ADDR(addr); +#endif + free_pages(addr, get_order(size)); +} + +EXPORT_SYMBOL(pci_alloc_consistent); +EXPORT_SYMBOL(pci_free_consistent); --- linux-2.5.73/arch/mips64/kernel/proc.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/proc.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,76 +1,143 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * linux/arch/mips/kernel/proc.c * - * Copyright (C) 1995, 1996, 1999, 2001 Ralf Baechle - * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 1995, 1996, 2001 Ralf Baechle + * Copyright (C) 2001 MIPS Technologies, Inc. */ +#include #include #include #include -#include +#include #include +#include #include #include #include -extern unsigned long unaligned_instructions; unsigned int vced_count, vcei_count; -/* - * BUFFER is PAGE_SIZE bytes long. - * - * Currently /proc/cpuinfo is being abused to print data about the - * number of date/instruction cacheflushes. - */ -int get_cpuinfo(char *buffer) +static const char *cpu_name[] = { + [CPU_UNKNOWN] "unknown", + [CPU_R2000] "R2000", + [CPU_R3000] "R3000", + [CPU_R3000A] "R3000A", + [CPU_R3041] "R3041", + [CPU_R3051] "R3051", + [CPU_R3052] "R3052", + [CPU_R3081] "R3081", + [CPU_R3081E] "R3081E", + [CPU_R4000PC] "R4000PC", + [CPU_R4000SC] "R4000SC", + [CPU_R4000MC] "R4000MC", + [CPU_R4200] "R4200", + [CPU_R4400PC] "R4400PC", + [CPU_R4400SC] "R4400SC", + [CPU_R4400MC] "R4400MC", + [CPU_R4600] "R4600", + [CPU_R6000] "R6000", + [CPU_R6000A] "R6000A", + [CPU_R8000] "R8000", + [CPU_R10000] "R10000", + [CPU_R4300] "R4300", + [CPU_R4650] "R4650", + [CPU_R4700] "R4700", + [CPU_R5000] "R5000", + [CPU_R5000A] "R5000A", + [CPU_R4640] "R4640", + [CPU_NEVADA] "Nevada", + [CPU_RM7000] "RM7000", + [CPU_R5432] "R5432", + [CPU_4KC] "MIPS 4Kc", + [CPU_5KC] "MIPS 5Kc", + [CPU_R4310] "R4310", + [CPU_SB1] "SiByte SB1", + [CPU_TX3912] "TX3912", + [CPU_TX3922] "TX3922", + [CPU_TX3927] "TX3927", + [CPU_AU1000] "Au1000", + [CPU_AU1500] "Au1500", + [CPU_4KEC] "MIPS 4KEc", + [CPU_4KSC] "MIPS 4KSc", + [CPU_VR41XX] "NEC Vr41xx", + [CPU_R5500] "R5500", + [CPU_TX49XX] "TX49xx", + [CPU_20KC] "MIPS 20Kc", + [CPU_VR4111] "NEC VR4111", + [CPU_VR4121] "NEC VR4121", + [CPU_VR4122] "NEC VR4122", + [CPU_VR4131] "NEC VR4131", + [CPU_VR4181] "NEC VR4181", + [CPU_VR4181A] "NEC VR4181A", + [CPU_SR71000] "Sandcraft SR71000" +}; + + +static int show_cpuinfo(struct seq_file *m, void *v) { + unsigned int version = current_cpu_data.processor_id; + unsigned int fp_vers = current_cpu_data.fpu_id; + unsigned long n = (unsigned long) v - 1; char fmt [64]; - size_t len; - len = sprintf(buffer, "cpu\t\t\t: MIPS\n"); -#if 0 - len += sprintf(buffer + len, "cpu model\t\t: %s V%d.%d\n", - cpu_name[mips_cputype <= CPU_LAST ? - mips_cputype : - CPU_UNKNOWN], - (version >> 4) & 0x0f, - version & 0x0f); - len += sprintf(buffer + len, "system type\t\t: %s %s\n", - mach_group_names[mips_machgroup], - mach_group_to_name[mips_machgroup][mips_machtype]); -#endif - len += sprintf(buffer + len, "BogoMIPS\t\t: %lu.%02lu\n", - (loops_per_jiffy + 2500) / (500000/HZ), - ((loops_per_jiffy + 2500) / (5000/HZ)) % 100); - len += sprintf(buffer + len, "Number of cpus\t\t: %d\n", smp_num_cpus); -#if defined (__MIPSEB__) - len += sprintf(buffer + len, "byteorder\t\t: big endian\n"); +#ifdef CONFIG_SMP + if (!CPUMASK_TSTB(cpu_online_map, n)) + return 0; #endif -#if defined (__MIPSEL__) - len += sprintf(buffer + len, "byteorder\t\t: little endian\n"); -#endif - len += sprintf(buffer + len, "unaligned accesses\t: %lu\n", - unaligned_instructions); - len += sprintf(buffer + len, "wait instruction\t: %s\n", - wait_available ? "yes" : "no"); - len += sprintf(buffer + len, "microsecond timers\t: %s\n", - cyclecounter_available ? "yes" : "no"); - len += sprintf(buffer + len, "extra interrupt vector\t: %s\n", - dedicated_iv_available ? "yes" : "no"); - len += sprintf(buffer + len, "hardware watchpoint\t: %s\n", - watch_available ? "yes" : "no"); + + /* + * For the first processor also print the system type + */ + if (n == 0) + seq_printf(m, "system type\t\t: %s\n", get_system_type()); + + seq_printf(m, "processor\t\t: %ld\n", n); + sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", + cpu_has_fpu ? " FPU V%d.%d" : ""); + seq_printf(m, fmt, cpu_name[current_cpu_data.cputype <= CPU_LAST ? + current_cpu_data.cputype : CPU_UNKNOWN], + (version >> 4) & 0x0f, version & 0x0f, + (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); + seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n", + loops_per_jiffy / (500000/HZ), + (loops_per_jiffy / (5000/HZ)) % 100); + seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); + seq_printf(m, "microsecond timers\t: %s\n", + cpu_has_counter ? "yes" : "no"); + seq_printf(m, "tlb_entries\t\t: %d\n", current_cpu_data.tlbsize); + seq_printf(m, "extra interrupt vector\t: %s\n", + cpu_has_divec ? "yes" : "no"); + seq_printf(m, "hardware watchpoint\t: %s\n", + cpu_has_watch ? "yes" : "no"); sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", - vce_available ? "%d" : "not available"); - len += sprintf(buffer + len, fmt, 'D', vced_count); - len += sprintf(buffer + len, fmt, 'I', vcei_count); + cpu_has_vce ? "%d" : "not available"); + seq_printf(m, fmt, 'D', vced_count); + seq_printf(m, fmt, 'I', vcei_count); - return len; + return 0; } -void init_irq_proc(void) +static void *c_start(struct seq_file *m, loff_t *pos) { - /* Nothing, for now. */ + unsigned long i = *pos; + + return i < NR_CPUS ? (void *) (i + 1) : NULL; +} + +static void *c_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return c_start(m, pos); } + +static void c_stop(struct seq_file *m, void *v) +{ +} + +struct seq_operations cpuinfo_op = { + .start = c_start, + .next = c_next, + .stop = c_stop, + .show = show_cpuinfo, +}; --- linux-2.5.73/arch/mips64/kernel/process.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/process.c 2003-06-27 15:56:23.000000000 -0700 @@ -15,9 +15,12 @@ #include #include #include +#include #include #include #include +#include +#include #include #include @@ -28,78 +31,88 @@ #include #include #include +#include +#include +#include -asmlinkage int cpu_idle(void) +/* + * We use this if we don't have any better idle routine.. + * (This to kill: kernel/platform.c. + */ +void default_idle (void) +{ +} + +/* + * The idle thread. There's no useful work to be done, so just try to conserve + * power and have a low exit latency (ie sit in a loop waiting for somebody to + * say that they'd like to reschedule) + */ +ATTRIB_NORET void cpu_idle(void) { /* endless idle loop with no priority at all */ - init_idle(); - current->nice = 20; while (1) { while (!need_resched()) - if (wait_available) - __asm__("wait"); + if (cpu_wait) + (*cpu_wait)(); schedule(); - check_pgt_cache(); } } -struct task_struct *last_task_used_math = NULL; - asmlinkage void ret_from_fork(void); +void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) +{ + unsigned long status; + + /* New thread loses kernel privileges. */ + status = regs->cp0_status & ~(ST0_CU0|ST0_FR|ST0_KSU); + status |= KSU_USER; + status |= (current->thread.mflags & MF_32BIT_REGS) ? 0 : ST0_FR; + regs->cp0_status = status; + current->used_math = 0; + loose_fpu(); + regs->cp0_epc = pc; + regs->regs[29] = sp; + current_thread_info()->addr_limit = USER_DS; +} + void exit_thread(void) { - /* Forget lazy fpu state */ - if (IS_FPU_OWNER()) { - set_cp0_status(ST0_CU1, ST0_CU1); - __asm__ __volatile__("cfc1\t$0,$31"); - CLEAR_FPU_OWNER(); - } } void flush_thread(void) { - /* Forget lazy fpu state */ - if (IS_FPU_OWNER()) { - set_cp0_status(ST0_CU1, ST0_CU1); - __asm__ __volatile__("cfc1\t$0,$31"); - CLEAR_FPU_OWNER(); - } } int copy_thread(int nr, unsigned long clone_flags, unsigned long usp, - unsigned long unused, - struct task_struct * p, struct pt_regs * regs) + unsigned long unused, struct task_struct *p, + struct pt_regs *regs) { - struct pt_regs * childregs; + struct thread_info *ti = p->thread_info; + struct pt_regs *childregs; long childksp; - childksp = (unsigned long)p + KERNEL_STACK_SIZE - 32; + childksp = (unsigned long)ti + KERNEL_STACK_SIZE - 32; - if (IS_FPU_OWNER()) { + if (is_fpu_owner()) { save_fp(p); } + /* set up new TSS. */ childregs = (struct pt_regs *) childksp - 1; *childregs = *regs; childregs->regs[7] = 0; /* Clear error flag */ - if (current->personality == PER_LINUX) { - childregs->regs[2] = 0; /* Child gets zero as return value */ - regs->regs[2] = p->pid; - } else { - /* Under IRIX things are a little different. */ - childregs->regs[2] = 0; - childregs->regs[3] = 1; - regs->regs[2] = p->pid; - regs->regs[3] = 0; - } + childregs->regs[2] = 0; /* Child gets zero as return value */ + regs->regs[2] = p->pid; + if (childregs->cp0_status & ST0_CU0) { - childregs->regs[28] = (unsigned long) p; + childregs->regs[28] = (unsigned long) ti; childregs->regs[29] = childksp; - p->thread.current_ds = KERNEL_DS; + ti->addr_limit = KERNEL_DS; } else { childregs->regs[29] = usp; - p->thread.current_ds = USER_DS; + ti->addr_limit = USER_DS; } p->thread.reg29 = (unsigned long) childregs; p->thread.reg31 = (unsigned long) ret_from_fork; @@ -108,9 +121,9 @@ int copy_thread(int nr, unsigned long cl * New tasks lose permission to use the fpu. This accelerates context * switching for most programs since they don't use the fpu. */ - p->thread.cp0_status = read_32bit_cp0_register(CP0_STATUS) & - ~(ST0_CU3|ST0_CU2|ST0_CU1|ST0_KSU); - childregs->cp0_status &= ~(ST0_CU3|ST0_CU2|ST0_CU1); + p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1|ST0_KSU); + childregs->cp0_status &= ~(ST0_CU2|ST0_CU1); + p->set_child_tid = p->clear_child_tid = NULL; return 0; } @@ -118,32 +131,8 @@ int copy_thread(int nr, unsigned long cl /* Fill in the fpu structure for a core dump.. */ int dump_fpu(struct pt_regs *regs, elf_fpregset_t *r) { - /* We actually store the FPU info in the task->thread - * area. - */ - if(regs->cp0_status & ST0_CU1) { - memcpy(r, ¤t->thread.fpu, sizeof(current->thread.fpu)); - return 1; - } - return 0; /* Task didn't use the fpu at all. */ -} - -/* Fill in the user structure for a core dump.. */ -void dump_thread(struct pt_regs *regs, struct user *dump) -{ - dump->magic = CMAGIC; - dump->start_code = current->mm->start_code; - dump->start_data = current->mm->start_data; - dump->start_stack = regs->regs[29] & ~(PAGE_SIZE - 1); - dump->u_tsize = (current->mm->end_code - dump->start_code) - >> PAGE_SHIFT; - dump->u_dsize = (current->mm->brk + (PAGE_SIZE - 1) - dump->start_data) - >> PAGE_SHIFT; - dump->u_ssize = (current->mm->start_stack - dump->start_stack + - PAGE_SIZE - 1) >> PAGE_SHIFT; - memcpy(&dump->regs[0], regs, sizeof(struct pt_regs)); - memcpy(&dump->regs[EF_SIZE/4], ¤t->thread.fpu, - sizeof(current->thread.fpu)); + memcpy(r, ¤t->thread.fpu, sizeof(current->thread.fpu)); + return 1; } /* @@ -154,29 +143,106 @@ int kernel_thread(int (*fn)(void *), voi int retval; __asm__ __volatile__( - "move\t$6, $sp\n\t" - "move\t$4, %5\n\t" - "li\t$2, %1\n\t" - "syscall\n\t" - "beq\t$6, $sp, 1f\n\t" - "move\t$4, %3\n\t" - "jalr\t%4\n\t" - "move\t$4, $2\n\t" - "li\t$2, %2\n\t" - "syscall\n" - "1:\tmove\t%0, $2" - :"=r" (retval) - :"i" (__NR_clone), "i" (__NR_exit), "r" (arg), "r" (fn), - "r" (flags | CLONE_VM | CLONE_UNTRACED) - - /* The called subroutine might have destroyed any of the - * at, result, argument or temporary registers ... */ - :"$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", - "$9","$10","$11","$12","$13","$14","$15","$24","$25"); + " move $6, $sp \n" + " move $4, %5 \n" + " li $2, %1 \n" + " syscall \n" + " beq $6, $sp, 1f \n" + " move $4, %3 \n" + " jalr %4 \n" + " move $4, $2 \n" + " li $2, %2 \n" + " syscall \n" + "1: move %0, $2" + : "=r" (retval) + : "i" (__NR_clone), "i" (__NR_exit), "r" (arg), "r" (fn), + "r" (flags | CLONE_VM | CLONE_UNTRACED) + /* + * The called subroutine might have destroyed any of the + * at, result, argument or temporary registers ... + */ + : "$2", "$3", "$4", "$5", "$6", "$7", "$8", + "$9","$10","$11","$12","$13","$14","$15","$24","$25","$31"); return retval; } +struct mips_frame_info { + int frame_offset; + int pc_offset; +}; +static struct mips_frame_info schedule_frame; +static struct mips_frame_info schedule_timeout_frame; +static struct mips_frame_info sleep_on_frame; +static struct mips_frame_info sleep_on_timeout_frame; +static struct mips_frame_info wait_for_completion_frame; +static int mips_frame_info_initialized; +static int __init get_frame_info(struct mips_frame_info *info, void *func) +{ + int i; + union mips_instruction *ip = (union mips_instruction *)func; + info->pc_offset = -1; + info->frame_offset = -1; + for (i = 0; i < 128; i++, ip++) { + /* if jal, jalr, jr, stop. */ + if (ip->j_format.opcode == jal_op || + (ip->r_format.opcode == spec_op && + (ip->r_format.func == jalr_op || + ip->r_format.func == jr_op))) + break; + if (ip->i_format.opcode == sd_op && + ip->i_format.rs == 29) { + /* sd $ra, offset($sp) */ + if (ip->i_format.rt == 31) { + if (info->pc_offset != -1) + break; + info->pc_offset = + ip->i_format.simmediate / sizeof(long); + } + /* sd $s8, offset($sp) */ + if (ip->i_format.rt == 30) { + if (info->frame_offset != -1) + break; + info->frame_offset = + ip->i_format.simmediate / sizeof(long); + } + } + } + if (info->pc_offset == -1 || info->frame_offset == -1) { + printk("Can't analyze prologue code at %p\n", func); + info->pc_offset = -1; + info->frame_offset = -1; + return -1; + } + + return 0; +} +void __init frame_info_init(void) +{ + mips_frame_info_initialized = + !get_frame_info(&schedule_frame, schedule) && + !get_frame_info(&schedule_timeout_frame, schedule_timeout) && + !get_frame_info(&sleep_on_frame, sleep_on) && + !get_frame_info(&sleep_on_timeout_frame, sleep_on_timeout) && + !get_frame_info(&wait_for_completion_frame, wait_for_completion); +} + +/* + * Return saved PC of a blocked thread. + */ +unsigned long thread_saved_pc(struct thread_struct *t) +{ + extern void ret_from_fork(void); + + /* New born processes are a special case */ + if (t->reg31 == (unsigned long) ret_from_fork) + return t->reg31; + + if (schedule_frame.pc_offset < 0) + return 0; + return ((unsigned long *)t->reg29)[schedule_frame.pc_offset]; +} + /* * These bracket the sleeping functions.. */ @@ -193,6 +259,8 @@ unsigned long get_wchan(struct task_stru if (!p || p == current || p->state == TASK_RUNNING) return 0; + if (!mips_frame_info_initialized) + return 0; pc = thread_saved_pc(&p->thread); if (pc < first_sched || pc >= last_sched) goto out; @@ -205,30 +273,33 @@ unsigned long get_wchan(struct task_stru goto schedule_timeout_caller; if (pc >= (unsigned long)interruptible_sleep_on) goto schedule_caller; + if (pc >= (unsigned long)wait_for_completion) + goto schedule_caller; goto schedule_timeout_caller; schedule_caller: - frame = ((unsigned long *)p->thread.reg30)[10]; - pc = ((unsigned long *)frame)[7]; + frame = ((unsigned long *)p->thread.reg30)[schedule_frame.frame_offset]; + if (pc >= (unsigned long) sleep_on) + pc = ((unsigned long *)frame)[sleep_on_frame.pc_offset]; + else + pc = ((unsigned long *)frame)[wait_for_completion_frame.pc_offset]; goto out; schedule_timeout_caller: /* Must be schedule_timeout ... */ - pc = ((unsigned long *)p->thread.reg30)[11]; - frame = ((unsigned long *)p->thread.reg30)[10]; + frame = ((unsigned long *)p->thread.reg30)[schedule_frame.frame_offset]; /* The schedule_timeout frame ... */ - pc = ((unsigned long *)frame)[9]; - frame = ((unsigned long *)frame)[8]; + pc = ((unsigned long *)frame)[schedule_timeout_frame.pc_offset]; if (pc >= first_sched && pc < last_sched) { - /* schedule_timeout called by interruptible_sleep_on_timeout */ - pc = ((unsigned long *)frame)[7]; - frame = ((unsigned long *)frame)[6]; + /* schedule_timeout called by [interruptible_]sleep_on_timeout */ + frame = ((unsigned long *)frame)[schedule_timeout_frame.frame_offset]; + pc = ((unsigned long *)frame)[sleep_on_timeout_frame.pc_offset]; } out: - if (current->thread.mflags & MF_32BIT) /* Kludge for 32-bit ps */ + if (current->thread.mflags & MF_32BIT_REGS) /* Kludge for 32-bit ps */ pc &= 0xffffffff; return pc; --- linux-2.5.73/arch/mips64/kernel/ptrace.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/ptrace.c 2003-06-27 15:56:23.000000000 -0700 @@ -21,12 +21,16 @@ #include #include #include +#include +#include +#include #include #include #include #include #include +#include /* * Called by kernel/ptrace.c when detaching.. @@ -53,6 +57,8 @@ asmlinkage int sys32_ptrace(int request, /* are we already being traced? */ if (current->ptrace & PT_PTRACED) goto out; + if ((ret = security_ptrace(current->parent, current))) + goto out; /* set the ptrace bit in the process flags. */ current->ptrace |= PT_PTRACED; ret = 0; @@ -75,18 +81,14 @@ asmlinkage int sys32_ptrace(int request, ret = ptrace_attach(child); goto out_tsk; } - ret = -ESRCH; - if (!(child->ptrace & PT_PTRACED)) - goto out_tsk; - if (child->state != TASK_STOPPED) { - if (request != PTRACE_KILL) - goto out_tsk; - } - if (child->p_pptr != current) + + ret = ptrace_check_attach(child, request == PTRACE_KILL); + if (ret < 0) goto out_tsk; + switch (request) { /* when I and D space are separate, these will need to be fixed. */ - case PTRACE_PEEKTEXT: /* read word at location addr. */ + case PTRACE_PEEKTEXT: /* read word at location addr. */ case PTRACE_PEEKDATA: { unsigned int tmp; int copied; @@ -104,7 +106,7 @@ asmlinkage int sys32_ptrace(int request, struct pt_regs *regs; unsigned int tmp; - regs = (struct pt_regs *) ((unsigned long) child + + regs = (struct pt_regs *) ((unsigned long) child->thread_info + KERNEL_STACK_SIZE - 32 - sizeof(struct pt_regs)); ret = 0; @@ -114,28 +116,19 @@ asmlinkage int sys32_ptrace(int request, break; case FPR_BASE ... FPR_BASE + 31: if (child->used_math) { - unsigned long *fregs = - (void *) child->thread.fpu.hard.fp_regs; - -#ifndef CONFIG_SMP - if (last_task_used_math == child) { - set_cp0_status(ST0_CU1, ST0_CU1); - save_fp(child); - set_cp0_status(ST0_CU1, 0); - last_task_used_math = NULL; - } -#endif + unsigned long long *fregs; + fregs = (unsigned long long *)get_fpu_regs(child); /* * The odd registers are actually the high * order bits of the values stored in the even - * registers. + * registers - unless we're using r2k_switch.S. */ if (addr & 1) tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32); else tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff); } else { - tmp = -EIO; + tmp = -1; /* FP not yet used */ } break; case PC: @@ -154,14 +147,17 @@ asmlinkage int sys32_ptrace(int request, tmp = regs->lo; break; case FPC_CSR: - tmp = child->thread.fpu.hard.control; + if (cpu_has_fpu) + tmp = child->thread.fpu.hard.control; + else + tmp = child->thread.fpu.soft.sr; break; case FPC_EIR: { /* implementation / version register */ unsigned int flags; - local_save_flags(flags); - set_cp0_status(ST0_CU1, ST0_CU1); + flags = read_c0_status(); + __enable_fpu(); __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); - local_irq_restore(flags); + write_c0_status(flags); break; } default: @@ -184,7 +180,7 @@ asmlinkage int sys32_ptrace(int request, case PTRACE_POKEUSR: { struct pt_regs *regs; ret = 0; - regs = (struct pt_regs *) ((unsigned long) child + + regs = (struct pt_regs *) ((unsigned long) child->thread_info + KERNEL_STACK_SIZE - 32 - sizeof(struct pt_regs)); switch (addr) { @@ -192,19 +188,9 @@ asmlinkage int sys32_ptrace(int request, regs->regs[addr] = data; break; case FPR_BASE ... FPR_BASE + 31: { - unsigned long *fregs = - (void *) child->thread.fpu.hard.fp_regs; - if (child->used_math) { -#ifndef CONFIG_SMP - if (last_task_used_math == child) { - set_cp0_status(ST0_CU1, ST0_CU1); - save_fp(child); - set_cp0_status(ST0_CU1, 0); - last_task_used_math = NULL; - regs->cp0_status &= ~ST0_CU1; - } -#endif - } else { + unsigned long long *fregs; + fregs = (unsigned long long *)get_fpu_regs(child); + if (!child->used_math) { /* FP not yet used */ memset(&child->thread.fpu.hard, ~0, sizeof(child->thread.fpu.hard)); @@ -217,10 +203,12 @@ asmlinkage int sys32_ptrace(int request, */ if (addr & 1) { fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff; - fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long) data) << 32; + fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32; } else { fregs[addr - FPR_BASE] &= ~0xffffffffLL; - fregs[addr - FPR_BASE] |= data; + /* Must cast, lest sign extension fill upper + bits! */ + fregs[addr - FPR_BASE] |= (unsigned int)data; } break; } @@ -234,24 +222,29 @@ asmlinkage int sys32_ptrace(int request, regs->lo = data; break; case FPC_CSR: - child->thread.fpu.hard.control = data; + if (cpu_has_fpu) + child->thread.fpu.hard.control = data; + else + child->thread.fpu.soft.sr = data; break; default: /* The rest are not allowed. */ ret = -EIO; break; } - goto out; + break; } case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ case PTRACE_CONT: { /* restart after signal. */ ret = -EIO; if ((unsigned int) data > _NSIG) break; - if (request == PTRACE_SYSCALL) - child->ptrace |= PT_TRACESYS; - else - child->ptrace &= ~PT_TRACESYS; + if (request == PTRACE_SYSCALL) { + set_tsk_thread_flag(child, TIF_SYSCALL_TRACE); + } + else { + clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE); + } child->exit_code = data; wake_up_process(child); ret = 0; @@ -259,8 +252,8 @@ asmlinkage int sys32_ptrace(int request, } /* - * make the child exit. Best I can do is send it a sigkill. - * perhaps it should be put in the status that it wants to + * make the child exit. Best I can do is send it a sigkill. + * perhaps it should be put in the status that it wants to * exit. */ case PTRACE_KILL: { @@ -281,7 +274,7 @@ asmlinkage int sys32_ptrace(int request, } out_tsk: - free_task_struct(child); + put_task_struct(child); out: unlock_kernel(); return ret; @@ -303,6 +296,8 @@ asmlinkage int sys_ptrace(long request, /* are we already being traced? */ if (current->ptrace & PT_PTRACED) goto out; + if ((ret = security_ptrace(current->parent, current))) + goto out; /* set the ptrace bit in the process flags. */ current->ptrace |= PT_PTRACED; ret = 0; @@ -319,25 +314,20 @@ asmlinkage int sys_ptrace(long request, ret = -EPERM; if (pid == 1) /* you may not mess with init */ - goto out; + goto out_tsk; if (request == PTRACE_ATTACH) { ret = ptrace_attach(child); goto out_tsk; } - ret = -ESRCH; - if (!(child->ptrace & PT_PTRACED)) - goto out_tsk; - if (child->state != TASK_STOPPED) { - if (request != PTRACE_KILL) - goto out_tsk; - } - if (child->p_pptr != current) + + ret = ptrace_check_attach(child, request == PTRACE_KILL); + if (ret < 0) goto out_tsk; switch (request) { /* when I and D space are separate, these will need to be fixed. */ - case PTRACE_PEEKTEXT: /* read word at location addr. */ + case PTRACE_PEEKTEXT: /* read word at location addr. */ case PTRACE_PEEKDATA: { unsigned long tmp; int copied; @@ -355,7 +345,7 @@ asmlinkage int sys_ptrace(long request, struct pt_regs *regs; unsigned long tmp; - regs = (struct pt_regs *) ((unsigned long) child + + regs = (struct pt_regs *) ((unsigned long) child->thread_info + KERNEL_STACK_SIZE - 32 - sizeof(struct pt_regs)); ret = 0; @@ -365,26 +355,8 @@ asmlinkage int sys_ptrace(long request, break; case FPR_BASE ... FPR_BASE + 31: if (child->used_math) { - unsigned long long *fregs - = (unsigned long long *) - &child->thread.fpu.hard.fp_regs[0]; -#ifndef CONFIG_SMP - if (last_task_used_math == child) { - set_cp0_status(ST0_CU1, ST0_CU1); - save_fp(child); - set_cp0_status(ST0_CU1, 0); - last_task_used_math = NULL; - } -#endif - /* - * The odd registers are actually the high - * order bits of the values stored in the even - * registers. - */ - if (addr & 1) - tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32); - else - tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff); + unsigned long *fregs = get_fpu_regs(child); + tmp = fregs[addr - FPR_BASE]; } else { tmp = -EIO; } @@ -405,14 +377,17 @@ asmlinkage int sys_ptrace(long request, tmp = regs->lo; break; case FPC_CSR: - tmp = child->thread.fpu.hard.control; + if (cpu_has_fpu) + tmp = child->thread.fpu.hard.control; + else + tmp = child->thread.fpu.soft.sr; break; case FPC_EIR: { /* implementation / version register */ unsigned int flags; - local_save_flags(flags); - set_cp0_status(ST0_CU1, ST0_CU1); + flags = read_c0_status(); + __enable_fpu(); __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); - local_irq_restore(flags); + write_c0_status(flags); break; } default: @@ -435,7 +410,7 @@ asmlinkage int sys_ptrace(long request, case PTRACE_POKEUSR: { struct pt_regs *regs; ret = 0; - regs = (struct pt_regs *) ((unsigned long) child + + regs = (struct pt_regs *) ((unsigned long) child->thread_info + KERNEL_STACK_SIZE - 32 - sizeof(struct pt_regs)); switch (addr) { @@ -443,36 +418,14 @@ asmlinkage int sys_ptrace(long request, regs->regs[addr] = data; break; case FPR_BASE ... FPR_BASE + 31: { - unsigned long *fregs = - (void *) child->thread.fpu.hard.fp_regs; - if (child->used_math) { -#ifndef CONFIG_SMP - if (last_task_used_math == child) { - set_cp0_status(ST0_CU1, ST0_CU1); - save_fp(child); - set_cp0_status(ST0_CU1, 0); - last_task_used_math = NULL; - regs->cp0_status &= ~ST0_CU1; - } -#endif - } else { + unsigned long *fregs = get_fpu_regs(child); + if (!child->used_math) { /* FP not yet used */ memset(&child->thread.fpu.hard, ~0, sizeof(child->thread.fpu.hard)); child->thread.fpu.hard.control = 0; } - /* - * The odd registers are actually the high order bits - * of the values stored in the even registers - unless - * we're using r2k_switch.S. - */ - if (addr & 1) { - fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff; - fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long) data) << 32; - } else { - fregs[addr - FPR_BASE] &= ~0xffffffffLL; - fregs[addr - FPR_BASE] |= data; - } + fregs[addr - FPR_BASE] = data; break; } case PC: @@ -485,24 +438,29 @@ asmlinkage int sys_ptrace(long request, regs->lo = data; break; case FPC_CSR: - child->thread.fpu.hard.control = data; + if (cpu_has_fpu) + child->thread.fpu.hard.control = data; + else + child->thread.fpu.soft.sr = data; break; default: /* The rest are not allowed. */ ret = -EIO; break; } - goto out; + break; } case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ case PTRACE_CONT: { /* restart after signal. */ ret = -EIO; if ((unsigned long) data > _NSIG) break; - if (request == PTRACE_SYSCALL) - child->ptrace |= PT_TRACESYS; - else - child->ptrace &= ~PT_TRACESYS; + if (request == PTRACE_SYSCALL) { + set_tsk_thread_flag(child, TIF_SYSCALL_TRACE); + } + else { + clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE); + } child->exit_code = data; wake_up_process(child); ret = 0; @@ -510,8 +468,8 @@ asmlinkage int sys_ptrace(long request, } /* - * make the child exit. Best I can do is send it a sigkill. - * perhaps it should be put in the status that it wants to + * make the child exit. Best I can do is send it a sigkill. + * perhaps it should be put in the status that it wants to * exit. */ case PTRACE_KILL: { @@ -532,25 +490,47 @@ asmlinkage int sys_ptrace(long request, } out_tsk: - free_task_struct(child); + put_task_struct(child); out: unlock_kernel(); return ret; } -asmlinkage void syscall_trace(void) +struct task_work_bf { +#ifdef __MIPSEB__ + signed need_resched :8; + unsigned syscall_trace; /* count of syscall interceptors */ + unsigned sigpending; + unsigned notify_resume; /* request for notification on + userspace execution resumption */ +#endif +#ifdef __MIPSEL__ + unsigned notify_resume : 8; /* request for notification on + userspace execution + resumption */ + unsigned sigpending : 8; + unsigned syscall_trace : 8; /* count of syscall + interceptors */ + signed need_resched : 8; +#endif +}; + +asmlinkage void do_syscall_trace(void) { - if ((current->ptrace & (PT_PTRACED|PT_TRACESYS)) - != (PT_PTRACED|PT_TRACESYS)) + if (!test_thread_flag(TIF_SYSCALL_TRACE)) + return; + if (!(current->ptrace & PT_PTRACED)) return; /* The 0x80 provides a way for the tracing parent to distinguish between a syscall stop and SIGTRAP delivery */ current->exit_code = SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ? 0x80 : 0); + preempt_disable(); current->state = TASK_STOPPED; notify_parent(current, SIGCHLD); schedule(); + preempt_enable(); /* * this isn't the same as continuing with a signal, but it will do * for normal use. strace only continues with a signal if the --- linux-2.5.73/arch/mips64/kernel/r4k_fpu.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/r4k_fpu.S 2003-06-27 15:56:23.000000000 -0700 @@ -31,7 +31,7 @@ .set noreorder /* Save floating point context */ -LEAF(save_fp_context) +LEAF(_save_fp_context) mfc0 t1, CP0_STATUS sll t2, t1,5 @@ -79,7 +79,7 @@ LEAF(save_fp_context) jr ra li v0, 0 # success - END(save_fp_context) + END(_save_fp_context) /* * Restore FPU state: @@ -90,7 +90,7 @@ LEAF(save_fp_context) * frame on the current content of c0_status, not on the content of the * stack frame which might have been changed by the user. */ -LEAF(restore_fp_context) +LEAF(_restore_fp_context) mfc0 t1, CP0_STATUS sll t0, t1,5 bgez t0, 1f @@ -139,7 +139,7 @@ LEAF(restore_fp_context) ctc1 t0, fcr31 jr ra li v0, 0 # success - END(restore_fp_context) + END(_restore_fp_context) .type fault@function .ent fault --- linux-2.5.73/arch/mips64/kernel/r4k_genex.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/r4k_genex.S 2003-06-27 15:56:23.000000000 -0700 @@ -5,116 +5,61 @@ * * Copyright (C) 1994 - 1999 by Ralf Baechle * Copyright (C) 1999 Silicon Graphics + * Copyright (C) 2002 Maciej W. Rozycki * * Low level exception handling */ -#define __ASSEMBLY__ #include #include #include #include #include #include -#include - - .macro __build_clear_none - .endm - - .macro __build_clear_sti - STI - .endm - - .macro __build_clear_cli - CLI - .endm - - .macro __build_clear_fpe - cfc1 a1, fcr31 - li a2, ~(0x3f << 13) - and a2, a1 - ctc1 a2, fcr31 - STI - .endm - - .macro __build_clear_ade - dmfc0 t0, CP0_BADVADDR - sd t0, PT_BVADDR(sp) - KMODE - .endm - - .macro __BUILD_silent exception - .endm - - /* Gas tries to parse the PRINT argument as a string containing - string escapes and emits bogus warnings if it believes to - recognize an unknown escape code. So make the arguments - start with an n and gas will believe \n is ok ... */ - .macro __BUILD_verbose nexception - ld a1, PT_EPC(sp) - PRINT("Got \nexception at %016lx\012") - .endm - - .macro __BUILD_count exception - .set reorder - ld t0,exception_count_\exception - daddiu t0, 1 - sd t0,exception_count_\exception - .set noreorder - .comm exception_count\exception, 8, 8 - .endm - - .macro BUILD_HANDLER exception handler clear verbose - .align 5 - NESTED(handle_\exception, PT_SIZE, sp) - .set noat - SAVE_ALL -#if DEBUG_MIPS64 -jal dodebug2 -ld $4, PT_R4(sp) -ld $5, PT_R5(sp) -ld $6, PT_R6(sp) -ld $7, PT_R7(sp) -ld $2, PT_R2(sp) -#endif - __BUILD_clear_\clear - .set at - __BUILD_\verbose \exception - move a0, sp - jal do_\handler - j ret_from_sys_call - nop - END(handle_\exception) - .endm +#include +#include BUILD_HANDLER adel ade ade silent /* #4 */ BUILD_HANDLER ades ade ade silent /* #5 */ - BUILD_HANDLER ibe ibe cli silent /* #6 */ - BUILD_HANDLER dbe dbe cli silent /* #7 */ + BUILD_HANDLER ibe be cli silent /* #6 */ + BUILD_HANDLER dbe be cli silent /* #7 */ BUILD_HANDLER bp bp sti silent /* #9 */ BUILD_HANDLER ri ri sti silent /* #10 */ BUILD_HANDLER cpu cpu sti silent /* #11 */ BUILD_HANDLER ov ov sti silent /* #12 */ BUILD_HANDLER tr tr sti silent /* #13 */ BUILD_HANDLER fpe fpe fpe silent /* #15 */ + BUILD_HANDLER mdmx mdmx sti silent /* #22 */ BUILD_HANDLER watch watch sti verbose /* #23 */ + BUILD_HANDLER mcheck mcheck cli verbose /* #24 */ BUILD_HANDLER reserved reserved sti verbose /* others */ + __INIT +/* A temporary overflow handler used by check_daddi(). */ + + BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */ + + /* General exception handler for CPUs with virtual coherency exception. * - * Be careful when changing this, it has to be at most 128 bytes to fit - * into space reserved for the exception handler. + * Be careful when changing this, it has to be at most 256 (as a special + * exception) bytes to fit into space reserved for the exception handler. */ - NESTED(except_vec3_r4000, 0, sp) + .set push .set noat +NESTED(except_vec3_r4000, 0, sp) mfc0 k1, CP0_CAUSE - andi k1, k1, 0x7c li k0, 31<<2 + andi k1, k1, 0x7c + .set push + .set noreorder + .set nomacro beq k1, k0, handle_vced li k0, 14<<2 beq k1, k0, handle_vcei dsll k1, k1, 1 + .set pop ld k0, exception_handlers(k1) jr k0 @@ -125,51 +70,110 @@ ld $2, PT_R2(sp) * store will be re-executed. */ handle_vced: - mfc0 k0, CP0_BADVADDR + dmfc0 k0, CP0_BADVADDR li k1, -4 # Is this ... and k0, k1 # ... really needed? mtc0 zero, CP0_TAGLO cache Index_Store_Tag_D,(k0) cache Hit_Writeback_Inv_SD,(k0) - lui k0, %hi(vced_count) - lw k1, %lo(vced_count)(k0) + dla k0, vced_count + lw k1, (k0) addiu k1, 1 - sw k1, %lo(vced_count)(k0) + sw k1, (k0) eret handle_vcei: - mfc0 k0, CP0_BADVADDR + dmfc0 k0, CP0_BADVADDR cache Hit_Writeback_Inv_SD,(k0) # also cleans pi - lui k0, %hi(vcei_count) - lw k1, %lo(vcei_count)(k0) + dla k0, vcei_count + lw k1, (k0) addiu k1, 1 - sw k1, %lo(vcei_count)(k0) + sw k1, (k0) eret +END(except_vec3_r4000) + .set pop - END(except_vec3_r4000) - .set at - /* General exception vector for all other CPUs. */ - NESTED(except_vec3_generic, 0, sp) +/* General exception vector for all other CPUs. + * + * Be careful when changing this, it has to be at most 128 bytes + * to fit into space reserved for the exception handler. + */ + .set push .set noat +NESTED(except_vec3_generic, 0, sp) +#if R5432_CP0_INTERRUPT_WAR + mfc0 k0, CP0_INDEX +#endif mfc0 k1, CP0_CAUSE andi k1, k1, 0x7c dsll k1, k1, 1 ld k0, exception_handlers(k1) jr k0 - nop - END(except_vec3_generic) - .set at +END(except_vec3_generic) + .set pop + /* - * Special interrupt vector for embedded MIPS. This is a dedicated interrupt - * vector which reduces interrupt processing overhead. The jump instruction - * will be inserted here at initialization time. This handler may only be 8 - * bytes in size! + * Special interrupt vector for MIPS64 ISA & embedded MIPS processors. + * This is a dedicated interrupt exception vector which reduces the + * interrupt processing overhead. The jump instruction will be replaced + * at the initialization time. + * + * Be careful when changing this, it has to be at most 128 bytes + * to fit into space reserved for the exception handler. */ NESTED(except_vec4, 0, sp) 1: j 1b /* Dummy, will be replaced */ +END(except_vec4) + + /* + * EJTAG debug exception handler. + * The EJTAG debug exception entry point is 0xbfc00480, which + * normally is in the boot PROM, so the boot PROM must do a + * unconditional jump to this vector. + */ +NESTED(except_vec_ejtag_debug, 0, sp) + j ejtag_debug_handler nop - END(except_vec4) + END(except_vec_ejtag_debug) __FINIT + + /* + * EJTAG debug exception handler. + */ + NESTED(ejtag_debug_handler, PT_SIZE, sp) + .set noat + .set noreorder + mtc0 k0, CP0_DESAVE + mfc0 k0, CP0_DEBUG + + sll k0, k0, 30 # Check for SDBBP. + bgez k0, ejtag_return + + la k0, ejtag_debug_buffer + sw k1, 0(k0) + SAVE_ALL + jal ejtag_exception_handler + move a0, sp + RESTORE_ALL + la k0, ejtag_debug_buffer + lw k1, 0(k0) + +ejtag_return: + mfc0 k0, CP0_DESAVE + .set mips32 + deret + .set mips0 + nop + .set at + END(ejtag_debug_handler) + + /* + * This buffer is reserved for the use of the EJTAG debug + * handler. + */ + .data + EXPORT(ejtag_debug_buffer) + .fill 8 --- linux-2.5.73/arch/mips64/kernel/r4k_switch.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/r4k_switch.S 2003-06-27 15:56:23.000000000 -0700 @@ -8,11 +8,8 @@ * Copyright (C) 1994, 1995, 1996, by Andreas Busse * Copyright (C) 1999 Silicon Graphics, Inc. */ -#include #include -#include #include -#include #include #include #include @@ -21,15 +18,32 @@ #include #include #include +#include #include .set mips3 +/* + * Offset to the current process status flags, the first 32 bytes of the + * stack are not used. + */ +#define ST_OFF (KERNEL_STACK_SIZE - 32 - PT_SIZE + PT_STATUS) + +/* + * FPU context is saved iff the process has used it's FPU in the current + * time slice as indicated by TIF_USEDFPU. In any case, the CU1 bit for user + * space STATUS register should be 0, so that a process *always* starts its + * userland with FPU disabled after each context switch. + * + * FPU will be enabled as soon as the process accesses FPU again, through + * do_cpu() trap. + */ + /* - * task_struct *resume(task_struct *prev, task_struct *next) + * task_struct *resume(task_struct *prev, task_struct *next, + * struct thread_info *next_ti)) */ - .set noreorder .align 5 LEAF(resume) mfc0 t1, CP0_STATUS @@ -38,86 +52,85 @@ sd ra, THREAD_REG31(a0) /* + * check if we need to save FPU registers + */ + ld t3, TASK_THREAD_INFO(a0) + ld t0, TI_FLAGS(t3) + li t1, TIF_USEDFPU + and t2, t0, t1 + beqz t2, 1f + nor t1, zero, t1 + + and t0, t0, t1 + sd t0, TI_FLAGS(t3) + + /* + * clear saved user stack CU1 bit + */ + ld t0, ST_OFF(t3) + li t1, ~ST0_CU1 + and t0, t0, t1 + sd t0, ST_OFF(t3) + + + sll t2, t0, 5 + bgez t2, 2f + sdc1 $f0, (THREAD_FPU + 0x00)(a0) + fpu_save_16odd a0 +2: + fpu_save_16even a0 t1 # clobbers t1 +1: + + /* * The order of restoring the registers takes care of the race * updating $28, $29 and kernelsp without disabling ints. */ - move $28, a1 - cpu_restore_nonscratch $28 -#ifndef CONFIG_SMP - daddiu t0, $28, KERNEL_STACK_SIZE-32 - sd t0, kernelsp -#else - mtc0 a1, CP0_WATCHLO - dsrl32 a1, a1, 0 - mtc0 a1, CP0_WATCHHI -#endif + move $28, a2 + cpu_restore_nonscratch a1 + + daddiu t1, $28, KERNEL_STACK_SIZE-32 + set_saved_sp t1, t0, t2 + mfc0 t1, CP0_STATUS /* Do we really need this? */ li a3, 0xff00 and t1, a3 - ld a2, THREAD_STATUS($28) + ld a2, THREAD_STATUS(a1) nor a3, $0, a3 and a2, a3 or a2, t1 mtc0 a2, CP0_STATUS + move v0, a0 jr ra - move v0, a0 END(resume) /* - * Do lazy fpu context switch. Saves FPU context to the process in a0 - * and loads the new context of the current process. + * Save a thread's fp context. */ - -#define ST_OFF (KERNEL_STACK_SIZE - 32 - PT_SIZE + PT_STATUS) - -LEAF(lazy_fpu_switch) - mfc0 t0, CP0_STATUS # enable cp1 - li t3, 0x20000000 - or t0, t3 - mtc0 t0, CP0_STATUS - - beqz a0, 2f # Save floating point state - nor t3, zero, t3 - - ld t1, ST_OFF(a0) # last thread loses fpu - and t1, t3 - sd t1, ST_OFF(a0) - sll t2, t1, 5 - bgez t2, 1f - sdc1 $f0, (THREAD_FPU + 0x00)(a0) +LEAF(_save_fp) + mfc0 t0, CP0_STATUS + sll t1, t0, 5 + bgez t1, 1f # 16 register mode? fpu_save_16odd a0 1: fpu_save_16even a0 t1 # clobbers t1 -2: - - beqz a1, 3f - - sll t0, t0, 5 # load new fp state - bgez t0, 1f - ldc1 $f0, (THREAD_FPU + 0x00)($28) - fpu_restore_16odd $28 -1: - .set reorder - fpu_restore_16even $28, t0 # clobbers t0 -3: + sdc1 $f0, (THREAD_FPU + 0x00)(a0) jr ra - END(lazy_fpu_switch) + END(_save_fp) /* - * Save a thread's fp context. + * Restore a thread's fp context. */ - .set noreorder -LEAF(save_fp) +LEAF(_restore_fp) mfc0 t0, CP0_STATUS sll t1, t0, 5 bgez t1, 1f # 16 register mode? - nop - fpu_save_16odd a0 -1: - fpu_save_16even a0 t1 # clobbers t1 + + fpu_restore_16odd a0 +1: fpu_restore_16even a0, t0 # clobbers t0 + ldc1 $f0, (THREAD_FPU + 0x00)(a0) + jr ra - sdc1 $f0, (THREAD_FPU + 0x00)(a0) - END(save_fp) + END(_restore_fp) /* * Load the FPU with signalling NANS. This bit pattern we're using has @@ -129,18 +142,19 @@ LEAF(save_fp) #define FPU_DEFAULT 0x00000000 -LEAF(init_fpu) +LEAF(_init_fpu) mfc0 t0, CP0_STATUS - li t1, 0x20000000 + li t1, ST0_CU1 or t0, t1 mtc0 t0, CP0_STATUS + FPU_ENABLE_HAZARD sll t0, t0, 5 li t1, FPU_DEFAULT ctc1 t1, fcr31 + li t0, -1 # SNaN bgez t0, 1f # 16 / 32 register mode? - li t0, -1 dmtc1 t0, $f1 dmtc1 t0, $f3 @@ -174,6 +188,6 @@ LEAF(init_fpu) dmtc1 t0, $f24 dmtc1 t0, $f26 dmtc1 t0, $f28 + dmtc1 t0, $f30 jr ra - dmtc1 t0, $f30 - END(init_fpu) + END(_init_fpu) --- linux-2.5.73/arch/mips64/kernel/r4k_tlb_debug.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,71 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - * - * TLB debugging routines. These perform horribly slow but can easily be - * modified for debugging purposes. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write, - unsigned long address); - -asmlinkage void tlb_refill_debug(struct pt_regs regs) -{ - show_regs(®s); - panic(__FUNCTION__ " called. This Does Not Happen (TM)."); -} - -asmlinkage void xtlb_refill_debug(struct pt_regs *regs) -{ - unsigned long addr; - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - addr = regs->cp0_badvaddr & ~((PAGE_SIZE << 1) - 1); - pgd = pgd_offset(current->active_mm, addr); - pmd = pmd_offset(pgd, addr); - pte = pte_offset(pmd, addr); - - set_entrylo0(pte_val(pte[0]) >> 6); - set_entrylo1(pte_val(pte[1]) >> 6); - __asm__ __volatile__("nop;nop;nop"); - - tlb_write_random(); -} - -asmlinkage void xtlb_mod_debug(struct pt_regs *regs) -{ - unsigned long addr; - - addr = regs->cp0_badvaddr; - do_page_fault(regs, 1, addr); -} - -asmlinkage void xtlb_tlbl_debug(struct pt_regs *regs) -{ - unsigned long addr; - - addr = regs->cp0_badvaddr; - do_page_fault(regs, 0, addr); -} - -asmlinkage void xtlb_tlbs_debug(struct pt_regs *regs) -{ - unsigned long addr; - - addr = regs->cp0_badvaddr; - do_page_fault(regs, 1, addr); -} --- linux-2.5.73/arch/mips64/kernel/r4k_tlb_glue.S 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,46 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#define __ASSEMBLY__ -#include -#include -#include -#include - - .macro __BUILD_cli - CLI - .endm - - .macro __BUILD_sti - STI - .endm - - .macro tlb_handler name interruptible writebit - NESTED(__\name, PT_SIZE, sp) - SAVE_ALL -#if DEBUG_MIPS64 -jal dodebug2 -ld $4, PT_R4(sp) -ld $5, PT_R5(sp) -ld $6, PT_R6(sp) -ld $7, PT_R7(sp) -ld $2, PT_R2(sp) -#endif - dmfc0 a2, CP0_BADVADDR - __BUILD_\interruptible - li a1, \writebit - sd a2, PT_BVADDR(sp) - move a0, sp - jal do_page_fault - j ret_from_sys_call - END(__\name) - .endm - - tlb_handler xtlb_mod sti 1 - tlb_handler xtlb_tlbl sti 0 - tlb_handler xtlb_tlbs sti 1 --- linux-2.5.73/arch/mips64/kernel/r4k_tlb.S 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,126 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Silicon Graphics, Inc. - * Written by Ulf Carlsson (ulfc@engr.sgi.com) - */ -#include -#include -#include -#include -#include -#include -#include - - .data - .comm pgd_current, NR_CPUS * 8, 8 - - /* - * After this macro runs we have a pointer to the pte of the address - * that caused the fault in in PTR. - */ - - .macro LOAD_PTE2, ptr, tmp -#ifdef CONFIG_SMP - dmfc0 \tmp, CP0_CONTEXT - dla \ptr, pgd_current - dsrl \tmp, 23 - daddu \ptr, \tmp -#else - dla \ptr, pgd_current -#endif - dmfc0 \tmp, CP0_BADVADDR - ld \ptr, (\ptr) - bltz \tmp, kaddr - dsrl \tmp, (PGDIR_SHIFT-3) # get pgd offset in bytes - andi \tmp, ((PTRS_PER_PGD - 1)<<3) - daddu \ptr, \tmp # add in pgd offset - dmfc0 \tmp, CP0_BADVADDR - ld \ptr, (\ptr) # get pmd pointer - dsrl \tmp, (PMD_SHIFT-3) # get pmd offset in bytes - andi \tmp, ((PTRS_PER_PMD - 1)<<3) - daddu \ptr, \tmp # add in pmd offset - dmfc0 \tmp, CP0_XCONTEXT - ld \ptr, (\ptr) # get pte pointer - andi \tmp, 0xff0 # get pte offset - daddu \ptr, \tmp - .endm - - /* - * This places the even/odd pte pair in the page table at the pte - * entry pointed to by PTE into ENTRYLO0 and ENTRYLO1. - */ - .macro PTE_RELOAD, pte0, pte1 - dsrl \pte0, 6 # convert to entrylo0 - dmtc0 \pte0, CP0_ENTRYLO0 # load it - dsrl \pte1, 6 # convert to entrylo1 - dmtc0 \pte1, CP0_ENTRYLO1 # load it - .endm - - .text - .set noreorder - .set mips3 - - .align 5 -FEXPORT(except_vec0) - .set noat -1: b 1b - nop - - /* TLB refill handler for the R10000. - * Attention: We may only use 32 instructions. - */ - - .align 5 -FEXPORT(except_vec1_r10k) - .set noat - LOAD_PTE2 k1 k0 - ld k0, 0(k1) # get even pte - ld k1, 8(k1) # get odd pte - PTE_RELOAD k0 k1 - nop - tlbwr - eret -kaddr: - dla k0, handle_vmalloc_address # MAPPED kernel needs this - jr k0 - nop - - .align 5 -FEXPORT(handle_vmalloc_address) - .set noat - /* - * First, determine that the address is in/above vmalloc range. - */ - dmfc0 k0, CP0_BADVADDR - dli k1, VMALLOC_START - - /* - * Now find offset into kptbl. - */ - dsubu k0, k0, k1 - dla k1, kptbl - dsrl k0, (PAGE_SHIFT+1) # get vpn2 - dsll k0, 4 # byte offset of pte - daddu k1, k1, k0 - - /* - * Determine that fault address is within vmalloc range. - */ - dla k0, ekptbl - sltu k0, k1, k0 - beqz k0, not_vmalloc - - /* - * Load cp0 registers. - */ - ld k0, 0(k1) # get even pte - ld k1, 8(k1) # get odd pte - -not_vmalloc: - PTE_RELOAD k0 k1 - nop - tlbwr - eret --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/kernel/reset.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,36 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2001 by Ralf Baechle + * Copyright (C) 2001 MIPS Technologies, Inc. + */ +#include +#include +#include +#include + +/* + * Urgs ... Too many MIPS machines to handle this in a generic way. + * So handle all using function pointers to machine specific + * functions. + */ +void (*_machine_restart)(char *command); +void (*_machine_halt)(void); +void (*_machine_power_off)(void); + +void machine_restart(char *command) +{ + _machine_restart(command); +} + +void machine_halt(void) +{ + _machine_halt(); +} + +void machine_power_off(void) +{ + _machine_power_off(); +} --- linux-2.5.73/arch/mips64/kernel/scall_64.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/scall_64.S 2003-06-27 15:56:23.000000000 -0700 @@ -3,106 +3,125 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01 by Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02 by Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 2001 MIPS Technologies, Inc. */ #include #include #include -#include #include #include #include +#include #include +#include -/* This duplicates the definition from */ -#define PT_TRACESYS 0x00000002 /* tracing system calls */ - -/* This duplicates the definition from */ -#define SIGILL 4 /* Illegal instruction (ANSI). */ - -#ifndef CONFIG_MIPS32_COMPAT +#ifndef CONFIG_BINFMT_ELF32 +/* Neither O32 nor N32, so define handle_sys here */ #define handle_sys64 handle_sys #endif .align 5 NESTED(handle_sys64, PT_SIZE, sp) -/* When 32-bit compatibility is configured scall_o32.S already did this. */ -#ifndef CONFIG_MIPS32_COMPAT - .set noat - SAVE_SOME - STI - .set at +#if !defined(CONFIG_MIPS32_O32) && !defined(CONFIG_MIPS32_N32) + /* + * When 32-bit compatibility is configured scall_o32.S + * already did this. + */ + .set noat + SAVE_SOME + STI + .set at #endif - ld t1, PT_EPC(sp) # skip syscall on return - - subu t0, v0, __NR_Linux # check syscall number - sltiu t0, t0, __NR_Linux_syscalls + 1 - daddiu t1, 4 # skip to next instruction - beqz t0, illegal_syscall - sd t1, PT_EPC(sp) - - dsll t0, v0, 3 # offset into table - ld t2, (sys_call_table - (__NR_Linux * 8))(t0) # syscall routine + ld t1, PT_EPC(sp) # skip syscall on return - sd a3, PT_R26(sp) # save a3 for syscall restarting - - ld t0, TASK_PTRACE($28) # syscall tracing enabled? - andi t0, PT_TRACESYS - bnez t0, trace_a_syscall - - jalr t2 # Do The Real Thing (TM) - - li t0, -EMAXERRNO - 1 # error? - sltu t0, t0, v0 - sd t0, PT_R7(sp) # set error flag - beqz t0, 1f - - negu v0 # error - sd v0, PT_R0(sp) # set flag for syscall restarting -1: sd v0, PT_R2(sp) # result - -ret_from_sys_call: - mfc0 t0, CP0_STATUS - xori t0, t0, 1 - ori t0, t0, 1 - mtc0 t0, CP0_STATUS - -#error ld t2, TASK_NEED_RESCHED($28) - bnez t2, reschedule -#error lw v0, TASK_SIGPENDING($28) - bnez v0, signal_return - -restore_all: - RESTORE_SOME - RESTORE_SP - eret - -/* Put this behind restore_all for the sake of the branch prediction. */ -signal_return: - .type signal_return, @function - - mfc0 t0, CP0_STATUS - ori t0, t0, 1 - mtc0 t0, CP0_STATUS - - move a0, zero - move a1, sp - jal do_signal - b restore_all - -reschedule: - SAVE_STATIC - jal schedule - b ret_from_sys_call + subu t0, v0, __NR_Linux # check syscall number + sltiu t0, t0, __NR_Linux_syscalls + 1 + daddiu t1, 4 # skip to next instruction + beqz t0, illegal_syscall + sd t1, PT_EPC(sp) + + dsll t0, v0, 3 # offset into table + ld t2, (sys_call_table - (__NR_Linux * 8))(t0) + # syscall routine + + sd a3, PT_R26(sp) # save a3 for syscall restarting + + LONG_L t0, TI_FLAGS($28) + bltz t0, syscall_trace_entry # syscall tracing enabled? + + jalr t2 # Do The Real Thing (TM) + + li t0, -EMAXERRNO - 1 # error? + sltu t0, t0, v0 + sd t0, PT_R7(sp) # set error flag + beqz t0, 1f + + negu v0 # error + sd v0, PT_R0(sp) # set flag for syscall + # restarting +1: sd v0, PT_R2(sp) # result + +syscall_exit: + mfc0 t0, CP0_STATUS # make sure need_resched and + ori t0, t0, 1 # signals dont change between + xori t0, t0, 1 # sampling and return + mtc0 t0, CP0_STATUS + SSNOP; SSNOP; SSNOP + + LONG_L a2, TI_FLAGS($28) # current->work + bnez a2, syscall_exit_work + +FEXPORT(restore_all) + RESTORE_SOME + RESTORE_SP + eret + +EXPORT(work_pending) + andi t0, a2, _TIF_NEED_RESCHED + bltz t0, work_notifysig +work_resched: + jal schedule + + mfc0 t0, CP0_STATUS # make sure need_resched and + ori t0, t0, 1 # signals dont change between + xori t0, t0, 1 # sampling and return + mtc0 t0, CP0_STATUS + SSNOP; SSNOP; SSNOP + + LONG_L a2, TI_FLAGS($28) + andi a2, _TIF_WORK_MASK # is there any work to be done + # other than syscall tracing + beqz a2, restore_all + andi t0, a2, _TIF_NEED_RESCHED + bnez t0, work_resched + +work_notifysig: # deal with pending signals and + # notify-resume requests + SAVE_STATIC + move a0, sp + li a1, 0 + jal do_notify_resume # a2 already loaded + RESTORE_STATIC + j restore_all + +syscall_exit_work: + LONG_L t0, TI_FLAGS($28) # current->work.syscall_trace + bgez t0, work_pending + + mfc0 t0, CP0_STATUS # sti + ori t0, t0, 1 + mtc0 t0, CP0_STATUS + jal do_syscall_trace + j resume_userspace /* ------------------------------------------------------------------------ */ -trace_a_syscall: +syscall_trace_entry: SAVE_STATIC sd t2,PT_R1(sp) - jal syscall_trace + jal do_syscall_trace ld t2,PT_R1(sp) ld a0, PT_R4(sp) # Restore argument registers @@ -120,8 +139,7 @@ trace_a_syscall: sd v0, PT_R0(sp) # set flag for syscall restarting 1: sd v0, PT_R2(sp) # result - jal syscall_trace - j ret_from_sys_call + j syscall_exit illegal_syscall: /* This also isn't a 64-bit syscall, throw an error. */ @@ -129,223 +147,224 @@ illegal_syscall: sd v0, PT_R2(sp) li t0, 1 # set error flag sd t0, PT_R7(sp) - j ret_from_sys_call + j syscall_exit END(handle_sys64) + .align 3 sys_call_table: - PTR sys_syscall /* 5000 */ - PTR sys_exit - PTR sys_fork - PTR sys_read + PTR sys_read /* 5000 */ PTR sys_write - PTR sys_open /* 5005 */ + PTR sys_open PTR sys_close - PTR sys_waitpid - PTR sys_creat - PTR sys_link - PTR sys_unlink /* 5010 */ - PTR sys_execve - PTR sys_chdir - PTR sys_time - PTR sys_mknod - PTR sys_chmod /* 5015 */ - PTR sys_lchown - PTR sys_ni_syscall - PTR sys_stat + PTR sys_newstat + PTR sys_newfstat /* 5005 */ + PTR sys_newlstat + PTR sys_poll PTR sys_lseek - PTR sys_getpid /* 5020 */ - PTR sys_mount - PTR sys_oldumount - PTR sys_setuid - PTR sys_getuid - PTR sys_stime /* 5025 */ - PTR sys_ni_syscall /* ptrace */ - PTR sys_alarm - PTR sys_fstat + PTR sys_mmap + PTR sys_mprotect /* 5010 */ + PTR sys_munmap + PTR sys_brk + PTR sys_rt_sigaction + PTR sys_rt_sigprocmask + PTR sys_ioctl /* 5015 */ + PTR sys_pread64 + PTR sys_pwrite64 + PTR sys_readv + PTR sys_writev + PTR sys_access /* 5020 */ + PTR sys_pipe + PTR sys_select + PTR sys_sched_yield + PTR sys_mremap + PTR sys_msync /* 5025 */ + PTR sys_mincore + PTR sys_madvise + PTR sys_shmget + PTR sys_shmat + PTR sys_shmctl /* 5030 */ + PTR sys_dup + PTR sys_dup2 PTR sys_pause - PTR sys_utime /* 5030 */ - PTR sys_ni_syscall - PTR sys_ni_syscall - PTR sys_access - PTR sys_nice - PTR sys_ni_syscall /* 5035 */ - PTR sys_sync - PTR sys_kill - PTR sys_rename + PTR sys_nanosleep + PTR sys_getitimer /* 5035 */ + PTR sys_setitimer + PTR sys_alarm + PTR sys_getpid + PTR sys_sendfile + PTR sys_socket /* 5040 */ + PTR sys_connect + PTR sys_accept + PTR sys_sendto + PTR sys_recvfrom + PTR sys_sendmsg /* 5045 */ + PTR sys_recvmsg + PTR sys_shutdown + PTR sys_bind + PTR sys_listen + PTR sys_getsockname /* 5050 */ + PTR sys_getpeername + PTR sys_socketpair + PTR sys_setsockopt + PTR sys_getsockopt + PTR sys_clone /* 5055 */ + PTR sys_fork + PTR sys_execve + PTR sys_exit + PTR sys_wait4 + PTR sys_kill /* 5060 */ + PTR sys_newuname + PTR sys_semget + PTR sys_semop + PTR sys_semctl + PTR sys_shmdt /* 5065 */ + PTR sys_msgget + PTR sys_msgsnd + PTR sys_msgrcv + PTR sys_msgctl + PTR sys_fcntl /* 5070 */ + PTR sys_flock + PTR sys_fsync + PTR sys_fdatasync + PTR sys_truncate + PTR sys_ftruncate /* 5075 */ + PTR sys_getdents + PTR sys_getcwd + PTR sys_chdir + PTR sys_fchdir + PTR sys_rename /* 5080 */ PTR sys_mkdir - PTR sys_rmdir /* 5040 */ - PTR sys_dup - PTR sys_pipe + PTR sys_rmdir + PTR sys_creat + PTR sys_link + PTR sys_unlink /* 5085 */ + PTR sys_symlink + PTR sys_readlink + PTR sys_chmod + PTR sys_fchmod + PTR sys_chown /* 5090 */ + PTR sys_fchown + PTR sys_lchown + PTR sys_umask + PTR sys_gettimeofday + PTR sys_getrlimit /* 5095 */ + PTR sys_getrusage + PTR sys_sysinfo PTR sys_times - PTR sys_ni_syscall - PTR sys_brk /* 5045 */ - PTR sys_setgid + PTR sys_ptrace + PTR sys_getuid /* 5100 */ + PTR sys_syslog PTR sys_getgid - PTR sys_ni_syscall /* was signal 2 */ - PTR sys_geteuid - PTR sys_getegid /* 5050 */ - PTR sys_acct - PTR sys_umount - PTR sys_ni_syscall - PTR sys_ioctl - PTR sys_fcntl /* 5055 */ - PTR sys_ni_syscall + PTR sys_setuid + PTR sys_setgid + PTR sys_geteuid /* 5105 */ + PTR sys_getegid PTR sys_setpgid - PTR sys_ni_syscall - PTR sys_ni_syscall - PTR sys_umask /* 5060 */ - PTR sys_chroot - PTR sys_ustat - PTR sys_dup2 PTR sys_getppid - PTR sys_getpgrp /* 5065 */ - PTR sys_setsid - PTR sys_sigaction - PTR sys_sgetmask - PTR sys_ssetmask - PTR sys_setreuid /* 5070 */ + PTR sys_getpgrp + PTR sys_setsid /* 5110 */ + PTR sys_setreuid PTR sys_setregid - PTR sys_sigsuspend - PTR sys_sigpending - PTR sys_sethostname - PTR sys_setrlimit /* 5075 */ - PTR sys_getrlimit - PTR sys_getrusage - PTR sys_gettimeofday - PTR sys_settimeofday - PTR sys_getgroups /* 5080 */ + PTR sys_getgroups PTR sys_setgroups - PTR sys_ni_syscall /* old_select */ - PTR sys_symlink - PTR sys_lstat - PTR sys_readlink /* 5085 */ - PTR sys_uselib - PTR sys_swapon - PTR sys_reboot - PTR sys_ni_syscall /* old_readdir */ - PTR sys_mmap /* 5090 */ - PTR sys_munmap - PTR sys_truncate - PTR sys_ftruncate - PTR sys_fchmod - PTR sys_fchown /* 5095 */ - PTR sys_getpriority - PTR sys_setpriority - PTR sys_ni_syscall - PTR sys_statfs - PTR sys_fstatfs /* 5100 */ - PTR sys_ni_syscall /* sys_ioperm */ - PTR sys_socketcall - PTR sys_syslog - PTR sys_setitimer - PTR sys_getitimer /* 5105 */ - PTR sys_newstat - PTR sys_newlstat - PTR sys_newfstat - PTR sys_ni_syscall - PTR sys_ni_syscall /* sys_ioperm *//* 5110 */ - PTR sys_vhangup - PTR sys_ni_syscall /* was sys_idle */ - PTR sys_ni_syscall /* sys_vm86 */ - PTR sys_wait4 - PTR sys_swapoff /* 5115 */ - PTR sys_sysinfo - PTR sys_ipc - PTR sys_fsync - PTR sys_sigreturn - PTR sys_clone /* 5120 */ - PTR sys_setdomainname - PTR sys_newuname - PTR sys_ni_syscall /* sys_modify_ldt */ - PTR sys_adjtimex - PTR sys_mprotect /* 5125 */ - PTR sys_sigprocmask - PTR sys_create_module - PTR sys_init_module - PTR sys_delete_module - PTR sys_get_kernel_syms /* 5130 */ - PTR sys_quotactl + PTR sys_setresuid /* 5115 */ + PTR sys_getresuid + PTR sys_setresgid + PTR sys_getresgid PTR sys_getpgid - PTR sys_fchdir - PTR sys_bdflush - PTR sys_sysfs /* 5135 */ - PTR sys_personality - PTR sys_ni_syscall /* for afs_syscall */ - PTR sys_setfsuid + PTR sys_setfsuid /* 5120 */ PTR sys_setfsgid - PTR sys_llseek /* 5140 */ - PTR sys_getdents - PTR sys_select - PTR sys_flock - PTR sys_msync - PTR sys_readv /* 5145 */ - PTR sys_writev - PTR sys_cacheflush - PTR sys_cachectl - PTR sys_sysmips - PTR sys_ni_syscall /* 5150 */ PTR sys_getsid - PTR sys_fdatasync - PTR sys_sysctl - PTR sys_mlock - PTR sys_munlock /* 5155 */ - PTR sys_mlockall - PTR sys_munlockall + PTR sys_capget + PTR sys_capset + PTR sys_rt_sigpending /* 5125 */ + PTR sys_rt_sigtimedwait + PTR sys_rt_sigqueueinfo + PTR sys_rt_sigsuspend + PTR sys_sigaltstack + PTR sys_utime /* 5130 */ + PTR sys_mknod + PTR sys_personality + PTR sys_ustat + PTR sys_statfs + PTR sys_fstatfs /* 5135 */ + PTR sys_sysfs + PTR sys_getpriority + PTR sys_setpriority PTR sys_sched_setparam - PTR sys_sched_getparam - PTR sys_sched_setscheduler /* 5160 */ + PTR sys_sched_getparam /* 5140 */ + PTR sys_sched_setscheduler PTR sys_sched_getscheduler - PTR sys_sched_yield PTR sys_sched_get_priority_max PTR sys_sched_get_priority_min - PTR sys_sched_rr_get_interval /* 5165 */ - PTR sys_nanosleep - PTR sys_mremap - PTR sys_accept - PTR sys_bind - PTR sys_connect /* 5170 */ - PTR sys_getpeername - PTR sys_getsockname - PTR sys_getsockopt - PTR sys_listen - PTR sys_recv /* 5175 */ - PTR sys_recvfrom - PTR sys_recvmsg - PTR sys_send - PTR sys_sendmsg - PTR sys_sendto /* 5180 */ - PTR sys_setsockopt - PTR sys_shutdown - PTR sys_socket - PTR sys_socketpair - PTR sys_setresuid /* 5185 */ - PTR sys_getresuid - PTR sys_query_module - PTR sys_poll - PTR sys_nfsservctl - PTR sys_setresgid /* 5190 */ - PTR sys_getresgid + PTR sys_sched_rr_get_interval /* 5145 */ + PTR sys_mlock + PTR sys_munlock + PTR sys_mlockall + PTR sys_munlockall + PTR sys_vhangup /* 5150 */ + PTR sys_pivot_root + PTR sys_sysctl PTR sys_prctl - PTR sys_rt_sigreturn - PTR sys_rt_sigaction - PTR sys_rt_sigprocmask /* 5195 */ - PTR sys_rt_sigpending - PTR sys_rt_sigtimedwait - PTR sys_rt_sigqueueinfo - PTR sys_rt_sigsuspend - PTR sys_pread64 /* 5200 */ - PTR sys_pwrite64 - PTR sys_chown - PTR sys_getcwd - PTR sys_capget - PTR sys_capset /* 5205 */ - PTR sys_sigaltstack - PTR sys_sendfile - PTR sys_ni_syscall - PTR sys_ni_syscall - PTR sys_pivot_root /* 5210 */ - PTR sys_mincore - PTR sys_madvise - PTR sys_getdents64 + PTR sys_adjtimex + PTR sys_setrlimit /* 5155 */ + PTR sys_chroot + PTR sys_sync + PTR sys_acct + PTR sys_settimeofday + PTR sys_mount /* 5160 */ + PTR sys_umount + PTR sys_swapon + PTR sys_swapoff + PTR sys_reboot + PTR sys_sethostname /* 5165 */ + PTR sys_setdomainname + PTR sys_ni_syscall /* was create_module */ + PTR sys_init_module + PTR sys_delete_module + PTR sys_ni_syscall /* 5170, was get_kernel_syms */ + PTR sys_ni_syscall /* was query_module */ + PTR sys_quotactl + PTR sys_nfsservctl + PTR sys_ni_syscall /* res. for getpmsg */ + PTR sys_ni_syscall /* 5175 for putpmsg */ + PTR sys_ni_syscall /* res. for afs_syscall */ + PTR sys_ni_syscall /* res. for security */ PTR sys_gettid + PTR sys_readahead + PTR sys_setxattr /* 5180 */ + PTR sys_lsetxattr + PTR sys_fsetxattr + PTR sys_getxattr + PTR sys_lgetxattr + PTR sys_fgetxattr /* 5185 */ + PTR sys_listxattr + PTR sys_llistxattr + PTR sys_flistxattr + PTR sys_removexattr + PTR sys_lremovexattr /* 5190 */ + PTR sys_fremovexattr PTR sys_tkill + PTR sys_time + PTR sys_futex + PTR sys_sched_setaffinity /* 5195 */ + PTR sys_sched_getaffinity + PTR sys_cacheflush + PTR sys_cachectl + PTR sys_sysmips + PTR sys_io_setup /* 5200 */ + PTR sys_io_destroy + PTR sys_io_getevents + PTR sys_io_submit + PTR sys_io_cancel + PTR sys_exit_group /* 5205 */ + PTR sys_lookup_dcookie + PTR sys_epoll_create + PTR sys_epoll_ctl + PTR sys_epoll_wait + PTR sys_remap_file_pages /* 5210 */ + PTR sys_rt_sigreturn + PTR sys_set_tid_address + PTR sys_restart_syscall + PTR sys_semtimedop + PTR sys_fadvise64 /* 5215 */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/kernel/scall_n32.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,334 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01 by Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2001 MIPS Technologies, Inc. + */ +#include +#include +#include +#include +#include +#include +#include + +/* This duplicates the definition from */ +#define PT_TRACESYS 0x00000002 /* tracing system calls */ + +/* This duplicates the definition from */ +#define SIGILL 4 /* Illegal instruction (ANSI). */ + +#ifndef CONFIG_MIPS32_O32 +/* No O32, so define handle_sys here */ +#define handle_sysn32 handle_sys +#endif + + .align 5 +NESTED(handle_sysn32, PT_SIZE, sp) +#ifndef CONFIG_MIPS32_O32 + .set noat + SAVE_SOME + STI + .set at +#endif + ld t1, PT_EPC(sp) # skip syscall on return + + subu t0, v0, __NR_N32_Linux # check syscall number + sltiu t0, t0, __NR_N32_Linux_syscalls + 1 + daddiu t1, 4 # skip to next instruction + beqz t0, not_n32_scall + sd t1, PT_EPC(sp) + + dsll t0, v0, 3 # offset into table + ld t2, (sysn32_call_table - (__NR_N32_Linux * 8))(t0) + + sd a3, PT_R26(sp) # save a3 for syscall restarting + + LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? + bltz t0, n32_syscall_trace_entry + + jalr t2 # Do The Real Thing (TM) + + li t0, -EMAXERRNO - 1 # error? + sltu t0, t0, v0 + sd t0, PT_R7(sp) # set error flag + beqz t0, 1f + + negu v0 # error + sd v0, PT_R0(sp) # set flag for syscall restarting +1: sd v0, PT_R2(sp) # result + +FEXPORT(n32_syscall_exit) + mfc0 t0, CP0_STATUS # make sure need_resched and + xori t0, t0, 1 # signals dont change between + ori t0, t0, 1 # sampling and return + mtc0 t0, CP0_STATUS + SSNOP; SSNOP; SSNOP + + LONG_L a2, TI_FLAGS($28) # current->work + bnez a2, n32_syscall_exit_work + +restore_all: + RESTORE_SOME + RESTORE_SP + eret + +n32_syscall_exit_work: + SAVE_STATIC + j syscall_exit_work + +/* ------------------------------------------------------------------------ */ + +n32_syscall_trace_entry: + SAVE_STATIC + sd t2,PT_R1(sp) + jal do_syscall_trace + ld t2,PT_R1(sp) + + ld a0, PT_R4(sp) # Restore argument registers + ld a1, PT_R5(sp) + ld a2, PT_R6(sp) + ld a3, PT_R7(sp) + jalr t2 + + li t0, -EMAXERRNO - 1 # error? + sltu t0, t0, v0 + sd t0, PT_R7(sp) # set error flag + beqz t0, 1f + + negu v0 # error + sd v0, PT_R0(sp) # set flag for syscall restarting +1: sd v0, PT_R2(sp) # result + + j n32_syscall_exit + +not_n32_scall: + /* This is not an n32 compatibility syscall, pass it on to + the n64 syscall handlers. */ + j handle_sys64 + + END(handle_sysn32) + +EXPORT(sysn32_call_table) + PTR sys_read /* 6000 */ + PTR sys_write + PTR sys_open + PTR sys_close + PTR sys_newstat + PTR sys_newfstat /* 6005 */ + PTR sys_newlstat + PTR sys_poll + PTR sys_lseek + PTR sys_mmap + PTR sys_mprotect /* 6010 */ + PTR sys_munmap + PTR sys_brk + PTR sys32_rt_sigaction + PTR sys32_rt_sigprocmask + PTR compat_sys_ioctl /* 6015 */ + PTR sys_pread64 + PTR sys_pwrite64 + PTR sys32_readv + PTR sys32_writev + PTR sys_access /* 6020 */ + PTR sys_pipe + PTR sys32_select + PTR sys_sched_yield + PTR sys_mremap + PTR sys_msync /* 6025 */ + PTR sys_mincore + PTR sys_madvise + PTR sys_shmget + PTR sys_shmat + PTR sys_shmctl /* 6030 */ + PTR sys_dup + PTR sys_dup2 + PTR sys_pause + PTR compat_sys_nanosleep + PTR compat_sys_getitimer /* 6035 */ + PTR compat_sys_setitimer + PTR sys_alarm + PTR sys_getpid + PTR sys32_sendfile + PTR sys_socket /* 6040 */ + PTR sys_connect + PTR sys_accept + PTR sys_sendto + PTR sys_recvfrom + PTR compat_sys_sendmsg /* 6045 */ + PTR compat_sys_recvmsg + PTR sys_shutdown + PTR sys_bind + PTR sys_listen + PTR sys_getsockname /* 6050 */ + PTR sys_getpeername + PTR sys_socketpair + PTR compat_sys_setsockopt + PTR sys_getsockopt + PTR sys_clone /* 6055 */ + PTR sys_fork + PTR sys32_execve + PTR sys_exit + PTR sys32_wait4 + PTR sys_kill /* 6060 */ + PTR sys32_newuname + PTR sys_semget + PTR sys_semop + PTR sys_semctl + PTR sys_shmdt /* 6065 */ + PTR sys_msgget + PTR sys_msgsnd + PTR sys_msgrcv + PTR sys_msgctl + PTR compat_sys_fcntl /* 6070 */ + PTR sys_flock + PTR sys_fsync + PTR sys_fdatasync + PTR sys_truncate + PTR sys_ftruncate /* 6075 */ + PTR sys32_getdents + PTR sys_getcwd + PTR sys_chdir + PTR sys_fchdir + PTR sys_rename /* 6080 */ + PTR sys_mkdir + PTR sys_rmdir + PTR sys_creat + PTR sys_link + PTR sys_unlink /* 6085 */ + PTR sys_symlink + PTR sys_readlink + PTR sys_chmod + PTR sys_fchmod + PTR sys_chown /* 6090 */ + PTR sys_fchown + PTR sys_lchown + PTR sys_umask + PTR sys32_gettimeofday + PTR compat_sys_getrlimit /* 6095 */ + PTR compat_sys_getrusage + PTR sys32_sysinfo + PTR compat_sys_times + PTR sys_ptrace + PTR sys_getuid /* 6100 */ + PTR sys_syslog + PTR sys_getgid + PTR sys_setuid + PTR sys_setgid + PTR sys_geteuid /* 6105 */ + PTR sys_getegid + PTR sys_setpgid + PTR sys_getppid + PTR sys_getpgrp + PTR sys_setsid /* 6110 */ + PTR sys_setreuid + PTR sys_setregid + PTR sys_getgroups + PTR sys_setgroups + PTR sys_setresuid /* 6115 */ + PTR sys_getresuid + PTR sys_setresgid + PTR sys_getresgid + PTR sys_getpgid + PTR sys_setfsuid /* 6120 */ + PTR sys_setfsgid + PTR sys_getsid + PTR sys_capget + PTR sys_capset + PTR sys32_rt_sigpending /* 6125 */ + PTR sys32_rt_sigtimedwait + PTR sys32_rt_sigqueueinfo + PTR sys32_rt_sigsuspend + PTR sys32_sigaltstack + PTR compat_sys_utime /* 6130 */ + PTR sys_mknod + PTR sys32_personality + PTR sys_ustat + PTR compat_sys_statfs + PTR compat_sys_fstatfs /* 6135 */ + PTR sys_sysfs + PTR sys_getpriority + PTR sys_setpriority + PTR sys_sched_setparam + PTR sys_sched_getparam /* 6140 */ + PTR sys_sched_setscheduler + PTR sys_sched_getscheduler + PTR sys_sched_get_priority_max + PTR sys_sched_get_priority_min + PTR sys32_sched_rr_get_interval /* 6145 */ + PTR sys_mlock + PTR sys_munlock + PTR sys_mlockall + PTR sys_munlockall + PTR sys_vhangup /* 6150 */ + PTR sys_pivot_root + PTR sys32_sysctl + PTR sys_prctl + PTR sys32_adjtimex + PTR compat_sys_setrlimit /* 6155 */ + PTR sys_chroot + PTR sys_sync + PTR sys_acct + PTR sys32_settimeofday + PTR sys_mount /* 6160 */ + PTR sys_umount + PTR sys_swapon + PTR sys_swapoff + PTR sys_reboot + PTR sys_sethostname /* 6165 */ + PTR sys_setdomainname + PTR sys_ni_syscall /* was create_module */ + PTR sys_init_module + PTR sys_delete_module + PTR sys_ni_syscall /* 6170, was get_kernel_syms */ + PTR sys_ni_syscall /* was query_module */ + PTR sys_quotactl + PTR sys_nfsservctl + PTR sys_ni_syscall /* res. for getpmsg */ + PTR sys_ni_syscall /* 6175 for putpmsg */ + PTR sys_ni_syscall /* res. for afs_syscall */ + PTR sys_ni_syscall /* res. for security */ + PTR sys_gettid + PTR sys32_readahead + PTR sys_setxattr /* 6180 */ + PTR sys_lsetxattr + PTR sys_fsetxattr + PTR sys_getxattr + PTR sys_lgetxattr + PTR sys_fgetxattr /* 6185 */ + PTR sys_listxattr + PTR sys_llistxattr + PTR sys_flistxattr + PTR sys_removexattr + PTR sys_lremovexattr /* 6190 */ + PTR sys_fremovexattr + PTR sys_tkill + PTR sys_time + PTR compat_sys_futex + PTR sys32_sched_setaffinity /* 6195 */ + PTR sys32_sched_getaffinity + PTR sys_cacheflush + PTR sys_cachectl + PTR sys_sysmips + PTR sys_io_setup /* 6200 */ + PTR sys_io_destroy + PTR sys_io_getevents + PTR sys_io_submit + PTR sys_io_cancel + PTR sys_exit_group /* 6205 */ + PTR sys_lookup_dcookie + PTR sys_epoll_create + PTR sys_epoll_ctl + PTR sys_epoll_wait + PTR sys_remap_file_pages /* 6210 */ + PTR sys_ni_syscall + PTR sys_fcntl + PTR sys_set_tid_address + PTR sys_restart_syscall + PTR sys_semtimedop /* 6215 */ + PTR sys_fadvise64 + PTR sys_statfs64 + PTR sys_fstatfs64 --- linux-2.5.73/arch/mips64/kernel/scall_o32.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/scall_o32.S 2003-06-27 15:56:23.000000000 -0700 @@ -14,22 +14,12 @@ */ #include #include -#include #include #include #include #include #include -/* This duplicates the definition from */ -#error #define PT_TRACESYS 0x00000002 /* tracing system calls */ - -/* This duplicates the definition from */ -#define SIGILL 4 /* Illegal instruction (ANSI). */ - -/* Highest syscall used of any syscall flavour */ -#define MAX_SYSCALL_NO __NR_Linux32 + __NR_Linux32_syscalls - .align 5 NESTED(handle_sys, PT_SIZE, sp) .set noat @@ -38,24 +28,35 @@ NESTED(handle_sys, PT_SIZE, sp) .set at ld t1, PT_EPC(sp) # skip syscall on return - subu t0, v0, __NR_Linux32 # check syscall number - sltiu t0, t0, __NR_Linux32_syscalls + 1 + subu t0, v0, __NR_O32_Linux # check syscall number + sltiu t0, t0, __NR_O32_Linux_syscalls + 1 daddiu t1, 4 # skip to next instruction beqz t0, not_o32_scall sd t1, PT_EPC(sp) +#if 0 + SAVE_ALL + move a1, v0 + PRINT("Scall %ld\n") + RESTORE_ALL +#endif + + sll a0, a0, 0 + sll a1, a1, 0 + sll a2, a2, 0 + sll a3, a3, 0 /* XXX Put both in one cacheline, should save a bit. */ dsll t0, v0, 3 # offset into table - ld t2, (sys_call_table - (__NR_Linux32 * 8))(t0) # syscall routine - lbu t3, (sys_narg_table - __NR_Linux32)(v0) # number of arguments + ld t2, (sys_call_table - (__NR_O32_Linux * 8))(t0) + lbu t3, (sys_narg_table - __NR_O32_Linux)(v0) subu t0, t3, 5 # 5 or more arguments? sd a3, PT_R26(sp) # save a3 for syscall restarting bgez t0, stackargs stack_done: -#error ld t0, TASK_PTRACE($28) # syscall tracing enabled? -#error andi t0, PT_TRACESYS + LONG_L t0, TI_FLAGS($28) + # syscall tracing enabled? bnez t0, trace_a_syscall jalr t2 # Do The Real Thing (TM) @@ -69,35 +70,23 @@ stack_done: sd v0, PT_R0(sp) # flag for syscall restarting 1: sd v0, PT_R2(sp) # result -FEXPORT(o32_ret_from_sys_call) - mfc0 t0, CP0_STATUS # need_resched and signals atomic test - ori t0, t0, 1 - xori t0, t0, 1 +FEXPORT(o32_syscall_exit) + mfc0 t0, CP0_STATUS # make need_resched and + ori t0, t0, 1 # signals dont change between + xori t0, t0, 1 # sampling and return mtc0 t0, CP0_STATUS + SSNOP; SSNOP; SSNOP -#error ld t2, TASK_NEED_RESCHED($28) - bnez t2, o32_reschedule -#error lw v0, TASK_SIGPENDING($28) - bnez v0, signal_return + LONG_L a2, TI_FLAGS($28) + bnez a2, o32_syscall_exit_work restore_all: RESTORE_SOME RESTORE_SP - .set mips3 eret - .set mips0 - -signal_return: mfc0 t0, CP0_STATUS # need_resched and signals atomic test - ori t0, t0, 1 - mtc0 t0, CP0_STATUS - move a0, zero - move a1, sp - SAVE_STATIC -#error jal do_signal -o32_reschedule: +o32_syscall_exit_work: SAVE_STATIC - jal schedule - b o32_ret_from_sys_call + j syscall_exit_work /* ------------------------------------------------------------------------ */ @@ -109,7 +98,7 @@ trace_a_syscall: sd a7, PT_R11(sp) sd t2,PT_R1(sp) - jal syscall_trace + jal do_syscall_trace ld t2,PT_R1(sp) ld a0, PT_R4(sp) # Restore argument registers @@ -130,8 +119,7 @@ trace_a_syscall: sd v0, PT_R0(sp) # set flag for syscall restarting 1: sd v0, PT_R2(sp) # result -#error jal syscall_trace - j o32_ret_from_sys_call + j syscall_exit /* ------------------------------------------------------------------------ */ @@ -150,16 +138,20 @@ stackargs: bltz t0, bad_stack # -> sp is bad ld t0, PT_R29(sp) # get old user stack pointer - la t1, 3f # copy 1 to 2 arguments + PTR_LA t1, 3f # copy 1 to 2 arguments sll t3, t3, 2 subu t1, t3 jr t1 /* Ok, copy the args from the luser stack to the kernel stack */ + .set push + .set noreorder + .set nomacro 1: lw a5, 20(t0) # argument #6 from usp 2: lw a4, 16(t0) # argument #5 from usp +3: .set pop -3: j stack_done # go back + j stack_done # go back .section __ex_table,"a" PTR 1b, bad_stack @@ -170,70 +162,148 @@ stackargs: * The stackpointer for a call with more than 4 arguments is bad. */ bad_stack: - negu v0 # error - sd v0, PT_R0(sp) - sd v0, PT_R2(sp) - li t0, 1 # set error flag - sd t0, PT_R7(sp) - j ret_from_sys_call + negu v0 # error + sd v0, PT_R0(sp) + sd v0, PT_R2(sp) + li t0, 1 # set error flag + sd t0, PT_R7(sp) + j o32_syscall_exit not_o32_scall: - /* This is not an 32-bit compatibility syscall, pass it on to - the 64-bit syscall handlers. */ - j handle_sys64 + /* + * This is not an o32 compatibility syscall, pass it on + * to the 64-bit syscall handlers. + */ +#ifdef CONFIG_MIPS32_N32 + j handle_sysn32 +#else + j handle_sys64 +#endif illegal_syscall: - /* This also isn't a 64-bit syscall, throw an error. */ - li v0, ENOSYS # error - sd v0, PT_R2(sp) - li t0, 1 # set error flag - sd t0, PT_R7(sp) - j ret_from_sys_call - END(handle_sys) - - LEAF(mips_atomic_set) - ld v1, THREAD_CURDS($28) - daddiu a0, a1, 4 - or a0, a0, a1 - li v0, -EFAULT - and a0, a0, v1 - bltz a0, 9f - - /* Ok, this is the ll/sc case. World is sane :-) */ -1: ll v0, (a1) - move a0, a2 -2: sc a0, (a1) - beqz a0, 1b + /* This also isn't a 64-bit syscall, throw an error. */ + li v0, ENOSYS # error + sd v0, PT_R2(sp) + li t0, 1 # set error flag + sd t0, PT_R7(sp) + j o32_syscall_exit + END(handle_sys) + +LEAF(mips_atomic_set) + andi v0, a1, 3 # must be word aligned + bnez v0, bad_alignment + + ld v1, TI_ADDR_LIMIT($28) # in legal address range? + daddiu a0, a1, 4 + or a0, a0, a1 + and a0, a0, v1 + bnez a0, bad_address + + /* Ok, this is the ll/sc case. World is sane :-) */ +1: ll v0, (a1) + move a0, a2 +2: sc a0, (a1) + beqz a0, 1b + + .section __ex_table,"a" + PTR 1b, bad_stack + PTR 2b, bad_stack + .previous + +1: sd v0, PT_R2(sp) # result + + /* Success, so skip usual error handling garbage. */ + LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? + bltz t0, 1f + b o32_syscall_exit + +1: SAVE_STATIC + jal do_syscall_trace + li a3, 0 # success + j syscall_exit + +bad_address: + li v0, -EFAULT + jr ra + +bad_alignment: + li v0, -EINVAL + jr ra + END(mips_atomic_set) + +LEAF(sys32_sysmips) + beq a0, MIPS_ATOMIC_SET, mips_atomic_set + j sys_sysmips + END(sys32_sysmips) + +LEAF(sys32_syscall) + ld t0, PT_R29(sp) # user sp + + sltu v0, a0, __NR_O32_Linux + __NR_O32_Linux_syscalls + 1 + beqz v0, enosys + + dsll v0, a0, 3 + dla v1, sys32_syscall + ld t2, (sys_call_table - (__NR_O32_Linux * 8))(v0) + lbu t3, (sys_narg_table - __NR_O32_Linux)(a0) + + li v0, -EINVAL + beq t2, v1, out # do not recurse + + beqz t2, enosys # null function pointer? + + andi v0, t0, 0x3 # unaligned stack pointer? + bnez v0, sigsegv + + daddiu v0, t0, 16 # v0 = usp + 16 + daddu t1, v0, 12 # 3 32-bit arguments + ld v1, TI_ADDR_LIMIT($28) + or v0, v0, t1 + and v1, v1, v0 + bnez v1, efault + + move a0, a1 # shift argument registers + move a1, a2 + move a2, a3 + +1: lw a3, 16(t0) +2: lw t3, 20(t0) +3: lw t1, 24(t0) .section __ex_table,"a" - PTR 1b, bad_stack - PTR 2b, bad_stack + PTR 1b, efault + PTR 2b, efault + PTR 3b, efault .previous -1: sd v0, PT_R2(sp) # result + sw t3, 16(sp) # put into new stackframe + sw t1, 20(sp) + + bnez t1, 1f # zero arguments? + daddu a0, sp, 32 # then pass sp in a0 +1: + + sw t3, 16(sp) + sw v1, 20(sp) + jr t2 + /* Unreached */ + +enosys: li v0, -ENOSYS + b out + +sigsegv: + li a0, _SIGSEGV + move a1, $28 + jal force_sig + /* Fall through */ - /* Success, so skip usual error handling garbage. */ -#error ld t0, TASK_PTRACE($28) # syscall tracing enabled? -#error andi t0, PT_TRACESYS - bnez t0, 1f - b o32_ret_from_sys_call - -1: SAVE_STATIC -#error jal syscall_trace - li a3, 0 # success - j ret_from_sys_call - -9: li v0, -EFAULT - jr ra - END(mips_atomic_set) - - LEAF(sys_sysmips) - beq a0, MIPS_ATOMIC_SET, mips_atomic_set - j _sys_sysmips - END(sys_sysmips) +efault: li v0, -EFAULT + +out: jr ra + END(sys32_syscall) .macro syscalltable - sys sys_syscall 0 /* 4000 */ + sys sys32_syscall 0 /* 4000 */ sys sys_exit 1 sys sys_fork 0 sys sys_read 3 @@ -251,7 +321,7 @@ illegal_syscall: sys sys_chmod 2 /* 4015 */ sys sys_lchown 3 sys sys_ni_syscall 0 - sys sys_stat 2 + sys sys_ni_syscall 0 /* was sys_stat */ sys sys_lseek 3 sys sys_getpid 0 /* 4020 */ sys sys_mount 5 @@ -260,8 +330,8 @@ illegal_syscall: sys sys_getuid 0 sys sys_stime 1 /* 4025 */ sys sys32_ptrace 4 - sys sys32_alarm 1 - sys sys_fstat 2 + sys sys_alarm 1 + sys sys_ni_syscall 0 /* was sys_fstat */ sys sys_pause 0 sys compat_sys_utime 2 /* 4030 */ sys sys_ni_syscall 0 @@ -276,7 +346,7 @@ illegal_syscall: sys sys_rmdir 1 /* 4040 */ sys sys_dup 1 sys sys_pipe 0 - sys sys32_times 1 + sys compat_sys_times 1 sys sys_ni_syscall 0 sys sys_brk 1 /* 4045 */ sys sys_setgid 1 @@ -288,7 +358,7 @@ illegal_syscall: sys sys_umount 2 sys sys_ni_syscall 0 sys compat_sys_ioctl 3 - sys sys32_fcntl 3 /* 4055 */ + sys compat_sys_fcntl 3 /* 4055 */ sys sys_ni_syscall 2 sys sys_setpgid 2 sys sys_ni_syscall, 0 @@ -306,18 +376,18 @@ illegal_syscall: sys sys_setreuid 2 /* 4070 */ sys sys_setregid 2 sys sys32_sigsuspend 0 - sys sys32_sigpending 1 + sys compat_sys_sigpending 1 sys sys_sethostname 2 - sys sys32_setrlimit 2 /* 4075 */ - sys sys32_getrlimit 2 - sys sys32_getrusage 2 + sys compat_sys_setrlimit 2 /* 4075 */ + sys compat_sys_getrlimit 2 + sys compat_sys_getrusage 2 sys sys32_gettimeofday 2 sys sys32_settimeofday 2 sys sys_getgroups 2 /* 4080 */ sys sys_setgroups 2 - sys sys_ni_syscall 0 /* old_select */ + sys sys_ni_syscall 0 /* old_select */ sys sys_symlink 2 - sys sys_lstat 2 + sys sys_ni_syscall 0 /* was sys_lstat */ sys sys_readlink 3 /* 4085 */ sys sys_uselib 1 sys sys_swapon 2 @@ -332,24 +402,24 @@ illegal_syscall: sys sys_getpriority 2 sys sys_setpriority 3 sys sys_ni_syscall 0 - sys sys32_statfs 2 - sys sys32_fstatfs 2 /* 4100 */ - sys sys_ni_syscall 0 /* sys_ioperm */ - sys sys_socketcall 2 - sys sys_syslog 3 + sys compat_sys_statfs 2 + sys compat_sys_fstatfs 2 /* 4100 */ + sys sys_ni_syscall 0 /* sys_ioperm */ + sys sys_socketcall 2 + sys sys_syslog 3 sys compat_sys_setitimer 3 - sys compat_sys_getitimer 2 /* 4105 */ - sys sys32_newstat 2 - sys sys32_newlstat 2 - sys sys32_newfstat 2 - sys sys_ni_syscall 0 /* was sys_uname */ - sys sys_ni_syscall 0 /* sys_ioperm *//* 4110 */ - sys sys_vhangup 0 - sys sys_ni_syscall 0 /* was sys_idle */ - sys sys_ni_syscall 0 /* sys_vm86 */ - sys sys32_wait4 4 - sys sys_swapoff 1 /* 4115 */ - sys sys_sysinfo 1 + sys compat_sys_getitimer 2 /* 4105 */ + sys compat_sys_newstat 2 + sys compat_sys_newlstat 2 + sys compat_sys_newfstat 2 + sys sys_ni_syscall 0 /* was sys_uname */ + sys sys_ni_syscall 0 /* sys_ioperm *//* 4110 */ + sys sys_vhangup 0 + sys sys_ni_syscall 0 /* was sys_idle */ + sys sys_ni_syscall 0 /* sys_vm86 */ + sys sys32_wait4 4 + sys sys_swapoff 1 /* 4115 */ + sys sys32_sysinfo 1 sys sys32_ipc 6 sys sys_fsync 1 sys sys32_sigreturn 0 @@ -359,11 +429,11 @@ illegal_syscall: sys sys_ni_syscall 0 /* sys_modify_ldt */ sys sys32_adjtimex 1 sys sys_mprotect 3 /* 4125 */ - sys sys32_sigprocmask 3 - sys sys_create_module 2 + sys compat_sys_sigprocmask 3 + sys sys_ni_syscall 0 /* was creat_module */ sys sys_init_module 5 sys sys_delete_module 1 - sys sys_get_kernel_syms 1 /* 4130 */ + sys sys_ni_syscall 0 /* 4130, get_kernel_syms */ sys sys_quotactl 0 sys sys_getpgid 1 sys sys_fchdir 1 @@ -378,11 +448,11 @@ illegal_syscall: sys sys32_select 5 sys sys_flock 2 sys sys_msync 3 - sys compat_sys_readv 3 /* 4145 */ - sys compat_sys_writev 3 + sys sys32_readv 3 /* 4145 */ + sys sys32_writev 3 sys sys_cacheflush 3 sys sys_cachectl 3 - sys sys_sysmips 4 + sys sys32_sysmips 4 sys sys_ni_syscall 0 /* 4150 */ sys sys_getsid 1 sys sys_fdatasync 0 @@ -420,7 +490,7 @@ illegal_syscall: sys sys_socketpair 4 sys sys_setresuid 3 /* 4185 */ sys sys_getresuid 3 - sys sys_query_module 5 + sys sys_ni_syscall 0 /* was query_module */ sys sys_poll 3 sys sys_nfsservctl 3 sys sys_setresgid 3 /* 4190 */ @@ -440,12 +510,12 @@ illegal_syscall: sys sys_capget 2 sys sys_capset 2 /* 4205 */ sys sys32_sigaltstack 0 - sys sys_sendfile 3 + sys sys32_sendfile 4 sys sys_ni_syscall 0 sys sys_ni_syscall 0 - sys sys_mmap2 6 /* 4210 */ - sys sys_truncate64 2 - sys sys_ftruncate64 2 + sys sys32_mmap2 6 /* 4210 */ + sys sys32_truncate64 4 + sys sys32_ftruncate64 4 sys sys_newstat 2 sys sys_newlstat 2 sys sys_newfstat 2 /* 4215 */ @@ -453,15 +523,50 @@ illegal_syscall: sys sys_mincore 3 sys sys_madvise 3 sys sys_getdents64 3 - sys sys32_fcntl64 3 /* 4220 */ - sys sys32_gettid 0 - sys sys32_tkill 2 + sys compat_sys_fcntl64 3 /* 4220 */ + sys sys_ni_syscall 0 + sys sys_gettid 0 + sys sys32_readahead 5 + sys sys_setxattr 5 + sys sys_lsetxattr 5 /* 4225 */ + sys sys_fsetxattr 5 + sys sys_getxattr 4 + sys sys_lgetxattr 4 + sys sys_fgetxattr 4 + sys sys_listxattr 3 /* 4230 */ + sys sys_llistxattr 3 + sys sys_flistxattr 3 + sys sys_removexattr 2 + sys sys_lremovexattr 2 + sys sys_fremovexattr 2 /* 4235 */ + sys sys_tkill 2 + sys sys_sendfile64 5 + sys compat_sys_futex 5 + sys sys32_sched_setaffinity 3 + sys sys32_sched_getaffinity 3 /* 4240 */ + sys sys_io_setup 2 + sys sys_io_destroy 1 + sys sys_io_getevents 5 + sys sys_io_submit 3 + sys sys_io_cancel 3 /* 4245 */ + sys sys_exit_group 1 + sys sys_lookup_dcookie 3 + sys sys_epoll_create 1 + sys sys_epoll_ctl 4 + sys sys_epoll_wait 3 /* 4250 */ + sys sys_remap_file_pages 5 + sys sys_set_tid_address 1 + sys sys_restart_syscall 0 + sys sys_fadvise64 6 + sys sys_statfs64 3 /* 4255 */ + sys sys_fstatfs64 2 .endm .macro sys function, nargs PTR \function .endm + .align 3 sys_call_table: syscalltable --- linux-2.5.73/arch/mips64/kernel/setup.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -4,16 +4,20 @@ * for more details. * * Copyright (C) 1995 Linus Torvalds - * Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999 Ralf Baechle + * Copyright (C) 1995 Waldorf Electronics + * Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 Ralf Baechle * Copyright (C) 1996 Stoned Elipot * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2002 Maciej W. Rozycki */ #include #include #include +#include #include #include #include +#include #include #include #include @@ -23,42 +27,35 @@ #include #include #include +#include #ifdef CONFIG_BLK_DEV_RAM #include #endif +#include +#include +#include -#include +#include #include -#include #include +#include #include #include +#include #include -#ifndef CONFIG_SMP -struct cpuinfo_mips cpu_data[1]; -#endif +struct cpuinfo_mips cpu_data[NR_CPUS]; #ifdef CONFIG_VT struct screen_info screen_info; #endif /* - * Not all of the MIPS CPUs have the "wait" instruction available. This - * is set to true if it is available. The wait instruction stops the - * pipeline and reduces the power consumption of the CPU very much. - */ -char wait_available; - -/* - * Do we have a cyclecounter available? - */ -char cyclecounter_available; - -/* * Set if box has EISA slots. */ +#ifdef CONFIG_EISA int EISA_bus = 0; +#endif #ifdef CONFIG_BLK_DEV_FD extern struct fd_ops no_fd_ops; @@ -70,6 +67,8 @@ extern struct ide_ops no_ide_ops; struct ide_ops *ide_ops; #endif +extern void * __rd_start, * __rd_end; + extern struct rtc_ops no_rtc_ops; struct rtc_ops *rtc_ops; @@ -81,7 +80,6 @@ struct kbd_ops *kbd_ops; * * These are initialized so they are in the .data section */ -unsigned long mips_cputype = CPU_UNKNOWN; unsigned long mips_machtype = MACH_UNKNOWN; unsigned long mips_machgroup = MACH_GROUP_UNKNOWN; @@ -89,70 +87,396 @@ struct boot_mem_map boot_mem_map; unsigned char aux_device_present; -extern void load_mmu(void); - static char command_line[CL_SIZE] = { 0, }; char saved_command_line[CL_SIZE]; extern char arcs_cmdline[CL_SIZE]; -extern void ip22_setup(void); -extern void ip27_setup(void); +/* + * mips_io_port_base is the begin of the address space to which x86 style + * I/O ports are mapped. + */ +const unsigned long mips_io_port_base = -1; +EXPORT_SYMBOL(mips_io_port_base); + +/* + * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped + * for the processor. + */ +unsigned long isa_slot_offset; +EXPORT_SYMBOL(isa_slot_offset); + +extern void SetUpBootInfo(void); +extern void load_mmu(void); +extern ATTRIB_NORET asmlinkage void start_kernel(void); +extern void prom_init(int, char **, char **, int *); + +static struct resource code_resource = { "Kernel code" }; +static struct resource data_resource = { "Kernel data" }; -static inline void cpu_probe(void) +asmlinkage void __init init_arch(int argc, char **argv, char **envp, + int *prom_vec) { - unsigned int prid = read_32bit_cp0_register(CP0_PRID); + /* Determine which MIPS variant we are running on. */ + cpu_probe(); - switch(prid & 0xff00) { - case PRID_IMP_R4000: - if((prid & 0xff) == PRID_REV_R4400) - mips_cputype = CPU_R4400SC; - else - mips_cputype = CPU_R4000SC; - break; - case PRID_IMP_R4600: - mips_cputype = CPU_R4600; - break; - case PRID_IMP_R4700: - mips_cputype = CPU_R4700; - break; - case PRID_IMP_R5000: - mips_cputype = CPU_R5000; - break; - case PRID_IMP_NEVADA: - mips_cputype = CPU_NEVADA; - break; - case PRID_IMP_R8000: - mips_cputype = CPU_R8000; - break; - case PRID_IMP_R10000: - case PRID_IMP_R12000: - mips_cputype = CPU_R10000; - break; - default: - mips_cputype = CPU_UNKNOWN; + prom_init(argc, argv, envp, prom_vec); + + cpu_report(); + + /* + * Determine the mmu/cache attached to this machine, then flush the + * tlb and caches. On the r4xx0 variants this also sets CP0_WIRED to + * zero. + */ + load_mmu(); + + /* + * On IP27, I am seeing the TS bit set when the kernel is loaded. + * Maybe because the kernel is in ckseg0 and not xkphys? Clear it + * anyway ... + */ + clear_c0_status(ST0_BEV|ST0_TS|ST0_CU1|ST0_CU2|ST0_CU3); + set_c0_status(ST0_CU0|ST0_KX|ST0_SX|ST0_FR); + + start_kernel(); +} + +void __init add_memory_region(phys_t start, phys_t size, + long type) +{ + int x = boot_mem_map.nr_map; + + if (x == BOOT_MEM_MAP_MAX) { + printk("Ooops! Too many entries in the memory map!\n"); + return; } + + boot_mem_map.map[x].addr = start; + boot_mem_map.map[x].size = size; + boot_mem_map.map[x].type = type; + boot_mem_map.nr_map++; } -void __init setup_arch(char **cmdline_p) +static void __init print_memory_map(void) { - cpu_probe(); - load_mmu(); + int i; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + printk(" memory: %016Lx @ %016Lx ", + (unsigned long long) boot_mem_map.map[i].size, + (unsigned long long) boot_mem_map.map[i].addr); + switch (boot_mem_map.map[i].type) { + case BOOT_MEM_RAM: + printk("(usable)\n"); + break; + case BOOT_MEM_ROM_DATA: + printk("(ROM data)\n"); + break; + case BOOT_MEM_RESERVED: + printk("(reserved)\n"); + break; + default: + printk("type %lu\n", boot_mem_map.map[i].type); + break; + } + } +} + +static inline void parse_cmdline_early(void) +{ + char c = ' ', *to = command_line, *from = saved_command_line; + unsigned long start_at, mem_size; + int len = 0; + int usermem = 0; + + printk("Determined physical RAM map:\n"); + print_memory_map(); + + for (;;) { + /* + * "mem=XXX[kKmM]" defines a memory region from + * 0 to , overriding the determined size. + * "mem=XXX[KkmM]@YYY[KkmM]" defines a memory region from + * to +, overriding the determined size. + */ + if (c == ' ' && !memcmp(from, "mem=", 4)) { + if (to != command_line) + to--; + /* + * If a user specifies memory size, we + * blow away any automatically generated + * size. + */ + if (usermem == 0) { + boot_mem_map.nr_map = 0; + usermem = 1; + } + mem_size = memparse(from + 4, &from); + if (*from == '@') + start_at = memparse(from + 1, &from); + else + start_at = 0; + add_memory_region(start_at, mem_size, BOOT_MEM_RAM); + } + c = *(from++); + if (!c) + break; + if (CL_SIZE <= ++len) + break; + *(to++) = c; + } + *to = '\0'; + if (usermem) { + printk("User-defined physical RAM map:\n"); + print_memory_map(); + } +} + + +#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT) +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT) +#define PFN_PHYS(x) ((x) << PAGE_SHIFT) + +static inline void bootmem_init(void) +{ +#ifdef CONFIG_BLK_DEV_INITRD + unsigned long tmp; + unsigned long *initrd_header; +#endif + unsigned long bootmap_size; + unsigned long start_pfn, max_pfn; + int i; + +#ifdef CONFIG_BLK_DEV_INITRD + tmp = (((unsigned long)&_end + PAGE_SIZE-1) & PAGE_MASK) - 8; + if (tmp < (unsigned long)&_end) + tmp += PAGE_SIZE; + initrd_header = (unsigned long *)tmp; + if (initrd_header[0] == 0x494E5244) { + initrd_start = (unsigned long)&initrd_header[2]; + initrd_end = initrd_start + initrd_header[1]; + } + start_pfn = PFN_UP(CPHYSADDR((&_end)+(initrd_end - initrd_start) + PAGE_SIZE)); +#else + /* + * Partially used pages are not usable - thus + * we are rounding upwards. + */ + start_pfn = PFN_UP(CPHYSADDR(&_end)); +#endif /* CONFIG_BLK_DEV_INITRD */ + +#ifndef CONFIG_SGI_IP27 + /* Find the highest page frame number we have available. */ + max_pfn = 0; + for (i = 0; i < boot_mem_map.nr_map; i++) { + unsigned long start, end; + + if (boot_mem_map.map[i].type != BOOT_MEM_RAM) + continue; + + start = PFN_UP(boot_mem_map.map[i].addr); + end = PFN_DOWN(boot_mem_map.map[i].addr + + boot_mem_map.map[i].size); + + if (start >= end) + continue; + if (end > max_pfn) + max_pfn = end; + } + + /* Initialize the boot-time allocator. */ + bootmap_size = init_bootmem(start_pfn, max_pfn); + + /* + * Register fully available low RAM pages with the bootmem allocator. + */ + for (i = 0; i < boot_mem_map.nr_map; i++) { + unsigned long curr_pfn, last_pfn, size; + + /* + * Reserve usable memory. + */ + if (boot_mem_map.map[i].type != BOOT_MEM_RAM) + continue; + + /* + * We are rounding up the start address of usable memory: + */ + curr_pfn = PFN_UP(boot_mem_map.map[i].addr); + if (curr_pfn >= max_pfn) + continue; + if (curr_pfn < start_pfn) + curr_pfn = start_pfn; + + /* + * ... and at the end of the usable range downwards: + */ + last_pfn = PFN_DOWN(boot_mem_map.map[i].addr + + boot_mem_map.map[i].size); + + if (last_pfn > max_pfn) + last_pfn = max_pfn; + + /* + * ... finally, did all the rounding and playing + * around just make the area go away? + */ + if (last_pfn <= curr_pfn) + continue; + + size = last_pfn - curr_pfn; + free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size)); + } + + /* Reserve the bootmap memory. */ + reserve_bootmem(PFN_PHYS(start_pfn), bootmap_size); +#endif + +#ifdef CONFIG_BLK_DEV_INITRD + /* Board specific code should have set up initrd_start and initrd_end */ + ROOT_DEV = Root_RAM0; + if (&__rd_start != &__rd_end) { + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; + } + initrd_below_start_ok = 1; + if (initrd_start) { + unsigned long initrd_size = ((unsigned char *)initrd_end) - ((unsigned char *)initrd_start); + printk("Initial ramdisk at: 0x%p (%lu bytes)\n", + (void *)initrd_start, + initrd_size); +/* FIXME: is this right? */ +#ifndef CONFIG_SGI_IP27 + if (CPHYSADDR(initrd_end) > PFN_PHYS(max_pfn)) { + printk("initrd extends beyond end of memory " + "(0x%p > 0x%p)\ndisabling initrd\n", + (void *)CPHYSADDR(initrd_end), + (void *)PFN_PHYS(max_pfn)); + initrd_start = 0; + } +#endif /* !CONFIG_SGI_IP27 */ + } +#endif +} + +static inline void resource_init(void) +{ + int i; + + code_resource.start = virt_to_bus(&_text); + code_resource.end = virt_to_bus(&_etext) - 1; + data_resource.start = virt_to_bus(&_etext); + data_resource.end = virt_to_bus(&_edata) - 1; + + /* + * Request address space for all standard RAM. + */ + for (i = 0; i < boot_mem_map.nr_map; i++) { + struct resource *res; + + res = alloc_bootmem(sizeof(struct resource)); + switch (boot_mem_map.map[i].type) { + case BOOT_MEM_RAM: + case BOOT_MEM_ROM_DATA: + res->name = "System RAM"; + break; + case BOOT_MEM_RESERVED: + default: + res->name = "reserved"; + } + + res->start = boot_mem_map.map[i].addr; + res->end = boot_mem_map.map[i].addr + + boot_mem_map.map[i].size - 1; + + res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; + request_resource(&iomem_resource, res); + + /* + * We don't know which RAM region contains kernel data, + * so we try it repeatedly and let the resource manager + * test it. + */ + request_resource(res, &code_resource); + request_resource(res, &data_resource); + } +} + +#undef PFN_UP +#undef PFN_DOWN +#undef PFN_PHYS + + +void __init setup_arch(char **cmdline_p) +{ + extern void decstation_setup(void); + extern void ip22_setup(void); + extern void ip27_setup(void); + extern void ip32_setup(void); + extern void swarm_setup(void); + extern void malta_setup(void); + extern void momenco_ocelot_setup(void); + extern void momenco_ocelot_g_setup(void); + extern void momenco_ocelot_c_setup(void); + extern void swarm_setup(void); + void frame_info_init(void); + + frame_info_init(); +#ifdef CONFIG_DECSTATION + decstation_setup(); +#endif #ifdef CONFIG_SGI_IP22 ip22_setup(); #endif #ifdef CONFIG_SGI_IP27 ip27_setup(); #endif - -#ifdef CONFIG_ARC_MEMORY - bootmem_init (); +#ifdef CONFIG_SGI_IP32 + ip32_setup(); +#endif +#ifdef CONFIG_SIBYTE_BOARD + swarm_setup(); +#endif +#ifdef CONFIG_MIPS_MALTA + malta_setup(); +#endif +#ifdef CONFIG_MOMENCO_OCELOT + case MACH_GROUP_MOMENCO: + momenco_ocelot_setup(); + break; +#endif +#ifdef CONFIG_MOMENCO_OCELOT_G + case MACH_GROUP_MOMENCO: + momenco_ocelot_g_setup(); + break; #endif +#ifdef CONFIG_MOMENCO_OCELOT_C + case MACH_GROUP_MOMENCO: + momenco_ocelot_c_setup(); + break; +#endif + strlcpy(command_line, arcs_cmdline, sizeof(command_line)); strlcpy(saved_command_line, command_line, sizeof(saved_command_line)); *cmdline_p = command_line; + parse_cmdline_early(); + + bootmem_init(); + paging_init(); + + resource_init(); } + +int __init fpu_disable(char *s) +{ + cpu_data[0].options &= ~MIPS_CPU_FPU; + + return 1; +} + +__setup("nofpu", fpu_disable); --- linux-2.5.73/arch/mips64/kernel/signal32.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/signal32.c 2003-06-27 15:56:23.000000000 -0700 @@ -26,25 +26,20 @@ #include #include #include +#include #define DEBUG_SIG 0 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) extern asmlinkage int do_signal32(sigset_t *oldset, struct pt_regs *regs); -extern asmlinkage int save_fp_context(struct sigcontext *sc); -extern asmlinkage int restore_fp_context(struct sigcontext *sc); -extern asmlinkage void syscall_trace(void); +extern asmlinkage void do_syscall_trace(void); /* 32-bit compatibility types */ -#define _NSIG32_BPW 32 -#define _NSIG32_WORDS (_NSIG / _NSIG32_BPW) - -typedef struct { - unsigned int sig[_NSIG32_WORDS]; -} sigset32_t; +#define _NSIG_BPW32 32 +#define _NSIG_WORDS32 (_NSIG / _NSIG_BPW32) typedef unsigned int __sighandler32_t; typedef void (*vfptr_t)(void); @@ -52,9 +47,7 @@ typedef void (*vfptr_t)(void); struct sigaction32 { unsigned int sa_flags; __sighandler32_t sa_handler; - sigset32_t sa_mask; - unsigned int sa_restorer; - int sa_resv[1]; /* reserved */ + compat_sigset_t sa_mask; }; /* IRIX compatible stack_t */ @@ -64,41 +57,10 @@ typedef struct sigaltstack32 { int ss_flags; } stack32_t; - -static inline int store_fp_context(struct sigcontext *sc) -{ - unsigned int fcr0; - int err = 0; - - err |= __copy_to_user(&sc->sc_fpregs[0], - ¤t->thread.fpu.hard.fp_regs[0], NUM_FPU_REGS * - sizeof(unsigned long)); - err |= __copy_to_user(&sc->sc_fpc_csr, ¤t->thread.fpu.hard.control, - sizeof(unsigned int)); - __asm__ __volatile__("cfc1 %0, $0\n\t" : "=r" (fcr0)); - err |= __copy_to_user(&sc->sc_fpc_eir, &fcr0, sizeof(unsigned int)); - - return err; -} - -static inline int refill_fp_context(struct sigcontext *sc) -{ - int err = 0; - - if (verify_area(VERIFY_READ, sc, sizeof(*sc))) - return -EFAULT; - err |= __copy_from_user(¤t->thread.fpu.hard.fp_regs[0], - &sc->sc_fpregs[0], NUM_FPU_REGS * sizeof(unsigned long)); - err |= __copy_from_user(¤t->thread.fpu.hard.control, &sc->sc_fpc_csr, - sizeof(unsigned int)); - return err; -} - extern void __put_sigset_unknown_nsig(void); extern void __get_sigset_unknown_nsig(void); -static inline int -put_sigset(const sigset_t *kbuf, sigset32_t *ubuf) +static inline int put_sigset(const sigset_t *kbuf, compat_sigset_t *ubuf) { int err = 0; @@ -119,8 +81,7 @@ put_sigset(const sigset_t *kbuf, sigset3 return err; } -static inline int -get_sigset(sigset_t *kbuf, const sigset32_t *ubuf) +static inline int get_sigset(sigset_t *kbuf, const compat_sigset_t *ubuf) { int err = 0; unsigned long sig[4]; @@ -147,23 +108,22 @@ get_sigset(sigset_t *kbuf, const sigset3 /* * Atomically swap in the new signal mask, and wait for a signal. */ -asmlinkage inline int -sys32_sigsuspend(abi64_no_regargs, struct pt_regs regs) +asmlinkage inline int sys32_sigsuspend(abi64_no_regargs, struct pt_regs regs) { - sigset32_t *uset; + compat_sigset_t *uset; sigset_t newset, saveset; save_static(®s); - uset = (sigset32_t *) regs.regs[4]; + uset = (compat_sigset_t *) regs.regs[4]; if (get_sigset(&newset, uset)) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); + spin_lock_irq(¤t->sighand->siglock); saveset = current->blocked; current->blocked = newset; recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); + spin_unlock_irq(¤t->sighand->siglock); regs.regs[2] = EINTR; regs.regs[7] = 1; @@ -175,29 +135,28 @@ sys32_sigsuspend(abi64_no_regargs, struc } } -asmlinkage int -sys32_rt_sigsuspend(abi64_no_regargs, struct pt_regs regs) +asmlinkage int sys32_rt_sigsuspend(abi64_no_regargs, struct pt_regs regs) { - sigset32_t *uset; + compat_sigset_t *uset; sigset_t newset, saveset; size_t sigsetsize; save_static(®s); /* XXX Don't preclude handling different sized sigset_t's. */ sigsetsize = regs.regs[5]; - if (sigsetsize != sizeof(sigset32_t)) + if (sigsetsize != sizeof(compat_sigset_t)) return -EINVAL; - uset = (sigset32_t *) regs.regs[4]; + uset = (compat_sigset_t *) regs.regs[4]; if (get_sigset(&newset, uset)) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); + spin_lock_irq(¤t->sighand->siglock); saveset = current->blocked; current->blocked = newset; recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); + spin_unlock_irq(¤t->sighand->siglock); regs.regs[2] = EINTR; regs.regs[7] = 1; @@ -225,8 +184,6 @@ asmlinkage int sys32_sigaction(int sig, &act->sa_handler); err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags); err |= __get_user(mask, &act->sa_mask.sig[0]); - err |= __get_user((u32)(u64)new_ka.sa.sa_restorer, - &act->sa_restorer); if (err) return -EFAULT; @@ -245,8 +202,6 @@ asmlinkage int sys32_sigaction(int sig, err |= __put_user(0, &oact->sa_mask.sig[1]); err |= __put_user(0, &oact->sa_mask.sig[2]); err |= __put_user(0, &oact->sa_mask.sig[3]); - err |= __put_user((u32)(u64)old_ka.sa.sa_restorer, - &oact->sa_restorer); if (err) return -EFAULT; } @@ -254,8 +209,7 @@ asmlinkage int sys32_sigaction(int sig, return ret; } -asmlinkage int -sys32_sigaltstack(abi64_no_regargs, struct pt_regs regs) +asmlinkage int sys32_sigaltstack(abi64_no_regargs, struct pt_regs regs) { const stack32_t *uss = (const stack32_t *) regs.regs[4]; stack32_t *uoss = (stack32_t *) regs.regs[5]; @@ -293,10 +247,9 @@ sys32_sigaltstack(abi64_no_regargs, stru return ret; } -static asmlinkage int -restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) +static asmlinkage int restore_sigcontext(struct pt_regs *regs, + struct sigcontext *sc) { - int owned_fp; int err = 0; err |= __get_user(regs->cp0_epc, &sc->sc_pc); @@ -319,14 +272,15 @@ restore_sigcontext(struct pt_regs *regs, restore_gp_reg(31); #undef restore_gp_reg - err |= __get_user(owned_fp, &sc->sc_ownedfp); - if (owned_fp) { - if (IS_FPU_OWNER()) { - CLEAR_FPU_OWNER(); - regs->cp0_status &= ~ST0_CU1; - } - current->used_math = 1; - err |= refill_fp_context(sc); + err |= __get_user(current->used_math, &sc->sc_used_math); + + if (current->used_math) { + /* restore fpu context if we have used it before */ + own_fpu(); + err |= restore_fp_context(sc); + } else { + /* signal handler may have used FPU. Give it up. */ + loose_fpu(); } return err; @@ -339,15 +293,56 @@ struct sigframe { sigset_t sf_mask; }; -struct rt_sigframe { +struct rt_sigframe32 { u32 rs_ass[4]; /* argument save space for o32 */ u32 rs_code[2]; /* signal trampoline */ - struct siginfo rs_info; + struct siginfo32 rs_info; struct ucontext rs_uc; }; -asmlinkage void -sys32_sigreturn(abi64_no_regargs, struct pt_regs regs) +static int copy_siginfo_to_user32(siginfo_t32 *to, siginfo_t *from) +{ + int err; + + if (!access_ok (VERIFY_WRITE, to, sizeof(siginfo_t32))) + return -EFAULT; + + /* If you change siginfo_t structure, please be sure + this code is fixed accordingly. + It should never copy any pad contained in the structure + to avoid security leaks, but must copy the generic + 3 ints plus the relevant union member. + This routine must convert siginfo from 64bit to 32bit as well + at the same time. */ + err = __put_user(from->si_signo, &to->si_signo); + err |= __put_user(from->si_errno, &to->si_errno); + err |= __put_user((short)from->si_code, &to->si_code); + if (from->si_code < 0) + err |= __copy_to_user(&to->_sifields._pad, &from->_sifields._pad, SI_PAD_SIZE); + else { + switch (from->si_code >> 16) { + case __SI_CHLD >> 16: + err |= __put_user(from->si_utime, &to->si_utime); + err |= __put_user(from->si_stime, &to->si_stime); + err |= __put_user(from->si_status, &to->si_status); + default: + err |= __put_user(from->si_pid, &to->si_pid); + err |= __put_user(from->si_uid, &to->si_uid); + break; + case __SI_FAULT >> 16: + err |= __put_user((long)from->si_addr, &to->si_addr); + break; + case __SI_POLL >> 16: + err |= __put_user(from->si_band, &to->si_band); + err |= __put_user(from->si_fd, &to->si_fd); + break; + /* case __SI_RT: This is not generated by the kernel as of now. */ + } + } + return err; +} + +asmlinkage void sys32_sigreturn(abi64_no_regargs, struct pt_regs regs) { struct sigframe *frame; sigset_t blocked; @@ -359,10 +354,10 @@ sys32_sigreturn(abi64_no_regargs, struct goto badframe; sigdelsetmask(&blocked, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); + spin_lock_irq(¤t->sighand->siglock); current->blocked = blocked; recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); + spin_unlock_irq(¤t->sighand->siglock); if (restore_sigcontext(®s, &frame->sf_sc)) goto badframe; @@ -370,11 +365,11 @@ sys32_sigreturn(abi64_no_regargs, struct /* * Don't let your children do this ... */ - if (current->ptrace & PT_TRACESYS) - syscall_trace(); + if (current_thread_info()->flags & TIF_SYSCALL_TRACE) + do_syscall_trace(); __asm__ __volatile__( "move\t$29, %0\n\t" - "j\tret_from_sys_call" + "j\tsyscall_exit" :/* no outputs */ :"r" (®s)); /* Unreached */ @@ -383,24 +378,23 @@ badframe: force_sig(SIGSEGV, current); } -asmlinkage void -sys32_rt_sigreturn(abi64_no_regargs, struct pt_regs regs) +asmlinkage void sys32_rt_sigreturn(abi64_no_regargs, struct pt_regs regs) { - struct rt_sigframe *frame; + struct rt_sigframe32 *frame; sigset_t set; stack_t st; - frame = (struct rt_sigframe *) regs.regs[29]; + frame = (struct rt_sigframe32 *) regs.regs[29]; if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) goto badframe; if (__copy_from_user(&set, &frame->rs_uc.uc_sigmask, sizeof(set))) goto badframe; sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); + spin_lock_irq(¤t->sighand->siglock); current->blocked = set; recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); + spin_unlock_irq(¤t->sighand->siglock); if (restore_sigcontext(®s, &frame->rs_uc.uc_mcontext)) goto badframe; @@ -416,7 +410,7 @@ sys32_rt_sigreturn(abi64_no_regargs, str */ __asm__ __volatile__( "move\t$29, %0\n\t" - "j\tret_from_sys_call" + "j\tsyscall_exit" :/* no outputs */ :"r" (®s)); /* Unreached */ @@ -425,12 +419,13 @@ badframe: force_sig(SIGSEGV, current); } -static inline int -setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc) +static inline int setup_sigcontext(struct pt_regs *regs, + struct sigcontext *sc) { int err = 0; err |= __put_user(regs->cp0_epc, &sc->sc_pc); + err |= __put_user(regs->cp0_status, &sc->sc_status); #define save_gp_reg(i) { \ err |= __put_user(regs->regs[i], &sc->sc_regs[i]); \ @@ -451,34 +446,43 @@ setup_sigcontext(struct pt_regs *regs, s err |= __put_user(regs->cp0_cause, &sc->sc_cause); err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr); - if (current->used_math) { /* fp is active. */ - if (IS_FPU_OWNER()) { - lazy_fpu_switch(current, 0); - CLEAR_FPU_OWNER(); - regs->cp0_status &= ~ST0_CU1; - } - err |= __put_user(1, &sc->sc_ownedfp); - err |= store_fp_context(sc); - current->used_math = 0; - } else { - err |= __put_user(0, &sc->sc_ownedfp); + err |= __put_user(current->used_math, &sc->sc_used_math); + + if (!current->used_math) + goto out; + + /* + * Save FPU state to signal context. Signal handler will "inherit" + * current FPU state. + */ + if (!is_fpu_owner()) { + own_fpu(); + restore_fp(current); } - err |= __put_user(regs->cp0_status, &sc->sc_status); + err |= save_fp_context(sc); +out: return err; } /* * Determine which stack to use.. */ -static inline void * -get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) +static inline void *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, + size_t frame_size) { unsigned long sp; /* Default to using normal stack */ sp = regs->regs[29]; + /* + * FPU emulator may have it's own trampoline active just + * above the user stack, 16-bytes before the next lowest + * 16 byte boundary. Try to avoid trashing it. + */ + sp -= 32; + /* This is the X/Open sanctioned signal stack switching. */ if ((ka->sa.sa_flags & SA_ONSTACK) && ! on_sig_stack(sp)) sp = current->sas_ss_sp + current->sas_ss_size; @@ -486,9 +490,8 @@ get_sigframe(struct k_sigaction *ka, str return (void *)((sp - frame_size) & ALMASK); } -static void inline -setup_frame(struct k_sigaction * ka, struct pt_regs *regs, - int signr, sigset_t *set) +static inline void setup_frame(struct k_sigaction * ka, struct pt_regs *regs, + int signr, sigset_t *set) { struct sigframe *frame; int err = 0; @@ -497,23 +500,15 @@ setup_frame(struct k_sigaction * ka, str if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - /* Set up to return from userspace. If provided, use a stub already - in userspace. */ - if (ka->sa.sa_flags & SA_RESTORER) - regs->regs[31] = (unsigned long) ka->sa.sa_restorer; - else { - /* - * Set up the return code ... - * - * li v0, __NR_Linux32_sigreturn - * syscall - */ - err |= __put_user(0x24020000 + __NR_Linux32_sigreturn, - frame->sf_code + 0); - err |= __put_user(0x0000000c , - frame->sf_code + 1); - flush_cache_sigtramp((unsigned long) frame->sf_code); - } + /* + * Set up the return code ... + * + * li v0, __NR_O32_sigreturn + * syscall + */ + err |= __put_user(0x24020000 + __NR_O32_sigreturn, frame->sf_code + 0); + err |= __put_user(0x0000000c , frame->sf_code + 1); + flush_cache_sigtramp((unsigned long) frame->sf_code); err |= setup_sigcontext(regs, &frame->sf_sc); err |= __copy_to_user(&frame->sf_mask, set, sizeof(*set)); @@ -538,8 +533,9 @@ setup_frame(struct k_sigaction * ka, str regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler; #if DEBUG_SIG - printk("SIG deliver (%s:%d): sp=0x%p pc=0x%p ra=0x%p\n", - current->comm, current->pid, frame, regs->cp0_epc, frame->code); + printk("SIG deliver (%s:%d): sp=0x%p pc=0x%lx ra=0x%p\n", + current->comm, current->pid, + frame, regs->cp0_epc, frame->sf_code); #endif return; @@ -549,11 +545,11 @@ give_sigsegv: force_sig(SIGSEGV, current); } -static void inline -setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, - int signr, sigset_t *set, siginfo_t *info) +static inline void setup_rt_frame(struct k_sigaction * ka, + struct pt_regs *regs, int signr, + sigset_t *set, siginfo_t *info) { - struct rt_sigframe *frame; + struct rt_sigframe32 *frame; int err = 0; frame = get_sigframe(ka, regs, sizeof(*frame)); @@ -562,24 +558,18 @@ setup_rt_frame(struct k_sigaction * ka, /* Set up to return from userspace. If provided, use a stub already in userspace. */ - if (ka->sa.sa_flags & SA_RESTORER) - regs->regs[31] = (unsigned long) ka->sa.sa_restorer; - else { - /* - * Set up the return code ... - * - * li v0, __NR_Linux32_rt_sigreturn - * syscall - */ - err |= __put_user(0x24020000 + __NR_Linux32_rt_sigreturn, - frame->rs_code + 0); - err |= __put_user(0x0000000c , - frame->rs_code + 1); - flush_cache_sigtramp((unsigned long) frame->rs_code); - } + /* + * Set up the return code ... + * + * li v0, __NR_O32_rt_sigreturn + * syscall + */ + err |= __put_user(0x24020000 + __NR_O32_rt_sigreturn, frame->rs_code + 0); + err |= __put_user(0x0000000c , frame->rs_code + 1); + flush_cache_sigtramp((unsigned long) frame->rs_code); - /* Create siginfo. */ - err |= __copy_to_user(&frame->rs_info, info, sizeof(*info)); + /* Convert (siginfo_t -> siginfo_t32) and copy to user. */ + err |= copy_siginfo_to_user32(&frame->rs_info, info); /* Create the ucontext. */ err |= __put_user(0, &frame->rs_uc.uc_flags); @@ -604,7 +594,7 @@ setup_rt_frame(struct k_sigaction * ka, * a2 = pointer to ucontext * * $25 and c0_epc point to the signal handler, $29 points to - * the struct rt_sigframe. + * the struct rt_sigframe32. */ regs->regs[ 4] = signr; regs->regs[ 5] = (unsigned long) &frame->rs_info; @@ -614,8 +604,9 @@ setup_rt_frame(struct k_sigaction * ka, regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler; #if DEBUG_SIG - printk("SIG deliver (%s:%d): sp=0x%p pc=0x%p ra=0x%p\n", - current->comm, current->pid, frame, regs->cp0_epc, frame->code); + printk("SIG deliver (%s:%d): sp=0x%p pc=0x%lx ra=0x%p\n", + current->comm, current->pid, + frame, regs->cp0_epc, frame->rs_code); #endif return; @@ -625,32 +616,12 @@ give_sigsegv: force_sig(SIGSEGV, current); } -static inline void -handle_signal(unsigned long sig siginfo_t *info, sigset_t *oldset, - struct pt_regs * regs) +static inline void handle_signal(unsigned long sig, siginfo_t *info, + sigset_t *oldset, struct pt_regs * regs) { - struct k_sigaction *ka = ¤t->sig->action[sig-1]; + struct k_sigaction *ka = ¤t->sighand->action[sig-1]; - if (ka->sa.sa_flags & SA_SIGINFO) - setup_rt_frame(ka, regs, sig, oldset, info); - else - setup_frame(ka, regs, sig, oldset); - - if (ka->sa.sa_flags & SA_ONESHOT) - ka->sa.sa_handler = SIG_DFL; - if (!(ka->sa.sa_flags & SA_NODEFER)) { - spin_lock_irq(¤t->sigmask_lock); - sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); - sigaddset(¤t->blocked,sig); - recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); - } -} - -static inline void -syscall_restart(struct pt_regs *regs, struct k_sigaction *ka) -{ - switch(regs->regs[0]) { + switch (regs->regs[0]) { case ERESTARTNOHAND: regs->regs[2] = EINTR; break; @@ -666,6 +637,21 @@ syscall_restart(struct pt_regs *regs, st } regs->regs[0] = 0; /* Don't deal with this again. */ + + if (ka->sa.sa_flags & SA_SIGINFO) + setup_rt_frame(ka, regs, sig, oldset, info); + else + setup_frame(ka, regs, sig, oldset); + + if (ka->sa.sa_flags & SA_ONESHOT) + ka->sa.sa_handler = SIG_DFL; + if (!(ka->sa.sa_flags & SA_NODEFER)) { + spin_lock_irq(¤t->sighand->siglock); + sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); + sigaddset(¤t->blocked,sig); + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + } } asmlinkage int do_signal32(sigset_t *oldset, struct pt_regs *regs) @@ -678,9 +664,6 @@ asmlinkage int do_signal32(sigset_t *old signr = get_signal_to_deliver(&info, regs, NULL); if (signr > 0) { - if (regs->regs[0]) - syscall_restart(regs, ka); - /* Whee! Actually deliver the signal. */ handle_signal(signr, &info, oldset, regs); return 1; } @@ -701,44 +684,6 @@ asmlinkage int do_signal32(sigset_t *old return 0; } -extern asmlinkage int sys_sigprocmask(int how, old_sigset_t *set, - old_sigset_t *oset); - -asmlinkage int sys32_sigprocmask(int how, old_sigset_t32 *set, - old_sigset_t32 *oset) -{ - old_sigset_t s; - int ret; - mm_segment_t old_fs = get_fs(); - - if (set && get_user (s, set)) - return -EFAULT; - set_fs (KERNEL_DS); - ret = sys_sigprocmask(how, set ? &s : NULL, oset ? &s : NULL); - set_fs (old_fs); - if (!ret && oset && put_user (s, oset)) - return -EFAULT; - return ret; -} - -asmlinkage long sys_sigpending(old_sigset_t *set); - -asmlinkage int sys32_sigpending(old_sigset_t32 *set) -{ - old_sigset_t pending; - int ret; - mm_segment_t old_fs = get_fs(); - - set_fs (KERNEL_DS); - ret = sys_sigpending(&pending); - set_fs (old_fs); - - if (put_user(pending, set)) - return -EFAULT; - - return ret; -} - asmlinkage int sys32_rt_sigaction(int sig, const struct sigaction32 *act, struct sigaction32 *oact, unsigned int sigsetsize) @@ -758,8 +703,6 @@ asmlinkage int sys32_rt_sigaction(int si err |= __get_user((u32)(u64)new_sa.sa.sa_handler, &act->sa_handler); err |= __get_user(new_sa.sa.sa_flags, &act->sa_flags); - err |= __get_user((u32)(u64)new_sa.sa.sa_restorer, - &act->sa_restorer); err |= get_sigset(&new_sa.sa.sa_mask, &act->sa_mask); if (err) return -EFAULT; @@ -776,8 +719,6 @@ asmlinkage int sys32_rt_sigaction(int si err |= __put_user((u32)(u64)old_sa.sa.sa_handler, &oact->sa_handler); err |= __put_user(old_sa.sa.sa_flags, &oact->sa_flags); - err |= __put_user((u32)(u64)old_sa.sa.sa_restorer, - &oact->sa_restorer); err |= put_sigset(&old_sa.sa.sa_mask, &oact->sa_mask); if (err) return -EFAULT; @@ -789,8 +730,8 @@ out: asmlinkage long sys_rt_sigprocmask(int how, sigset_t *set, sigset_t *oset, size_t sigsetsize); -asmlinkage int sys32_rt_sigprocmask(int how, sigset32_t *set, sigset32_t *oset, - unsigned int sigsetsize) +asmlinkage int sys32_rt_sigprocmask(int how, compat_sigset_t *set, + compat_sigset_t *oset, unsigned int sigsetsize) { sigset_t old_set, new_set; int ret; @@ -798,7 +739,7 @@ asmlinkage int sys32_rt_sigprocmask(int if (set && get_sigset(&new_set, set)) return -EFAULT; - + set_fs (KERNEL_DS); ret = sys_rt_sigprocmask(how, set ? &new_set : NULL, oset ? &old_set : NULL, sigsetsize); @@ -812,7 +753,8 @@ asmlinkage int sys32_rt_sigprocmask(int asmlinkage long sys_rt_sigpending(sigset_t *set, size_t sigsetsize); -asmlinkage int sys32_rt_sigpending(sigset32_t *uset, unsigned int sigsetsize) +asmlinkage int sys32_rt_sigpending(compat_sigset_t *uset, + unsigned int sigsetsize) { int ret; sigset_t set; @@ -828,5 +770,110 @@ asmlinkage int sys32_rt_sigpending(sigse return ret; } -asmlinkage void sys32_rt_sigtimedwait(void) { panic(__FUNCTION__ " called."); } -asmlinkage void sys32_rt_sigqueueinfo(void) { panic(__FUNCTION__ " called."); } +asmlinkage int sys32_rt_sigtimedwait(compat_sigset_t *uthese, + siginfo_t32 *uinfo, struct compat_timespec *uts, + compat_time_t sigsetsize) +{ + int ret, sig; + sigset_t these; + compat_sigset_t these32; + struct timespec ts; + siginfo_t info; + long timeout = 0; + + /* + * As the result of a brainfarting competition a few years ago the + * size of sigset_t for the 32-bit kernel was choosen to be 128 bits + * but nothing so far is actually using that many, 64 are enough. So + * for now we just drop the high bits. + */ + if (copy_from_user (&these32, uthese, sizeof(compat_old_sigset_t))) + return -EFAULT; + + switch (_NSIG_WORDS) { +#ifdef __MIPSEB__ + case 4: these.sig[3] = these32.sig[6] | (((long)these32.sig[7]) << 32); + case 3: these.sig[2] = these32.sig[4] | (((long)these32.sig[5]) << 32); + case 2: these.sig[1] = these32.sig[2] | (((long)these32.sig[3]) << 32); + case 1: these.sig[0] = these32.sig[0] | (((long)these32.sig[1]) << 32); +#endif +#ifdef __MIPSEL__ + case 4: these.sig[3] = these32.sig[7] | (((long)these32.sig[6]) << 32); + case 3: these.sig[2] = these32.sig[5] | (((long)these32.sig[4]) << 32); + case 2: these.sig[1] = these32.sig[3] | (((long)these32.sig[2]) << 32); + case 1: these.sig[0] = these32.sig[1] | (((long)these32.sig[0]) << 32); +#endif + } + + /* + * Invert the set of allowed signals to get those we + * want to block. + */ + sigdelsetmask(&these, sigmask(SIGKILL)|sigmask(SIGSTOP)); + signotset(&these); + + if (uts) { + if (get_user (ts.tv_sec, &uts->tv_sec) || + get_user (ts.tv_nsec, &uts->tv_nsec)) + return -EINVAL; + if (ts.tv_nsec >= 1000000000L || ts.tv_nsec < 0 + || ts.tv_sec < 0) + return -EINVAL; + } + + spin_lock_irq(¤t->sighand->siglock); + sig = dequeue_signal(current, &these, &info); + if (!sig) { + /* None ready -- temporarily unblock those we're interested + in so that we'll be awakened when they arrive. */ + sigset_t oldblocked = current->blocked; + sigandsets(¤t->blocked, ¤t->blocked, &these); + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + + timeout = MAX_SCHEDULE_TIMEOUT; + if (uts) + timeout = (timespec_to_jiffies(&ts) + + (ts.tv_sec || ts.tv_nsec)); + + current->state = TASK_INTERRUPTIBLE; + timeout = schedule_timeout(timeout); + + spin_lock_irq(¤t->sighand->siglock); + sig = dequeue_signal(current, &these, &info); + current->blocked = oldblocked; + recalc_sigpending(); + } + spin_unlock_irq(¤t->sighand->siglock); + + if (sig) { + ret = sig; + if (uinfo) { + if (copy_siginfo_to_user32(uinfo, &info)) + ret = -EFAULT; + } + } else { + ret = -EAGAIN; + if (timeout) + ret = -EINTR; + } + + return ret; +} + +extern asmlinkage int sys_rt_sigqueueinfo(int pid, int sig, siginfo_t *uinfo); + +asmlinkage int sys32_rt_sigqueueinfo(int pid, int sig, siginfo_t32 *uinfo) +{ + siginfo_t info; + int ret; + mm_segment_t old_fs = get_fs(); + + if (copy_from_user (&info, uinfo, 3*sizeof(int)) || + copy_from_user (info._sifields._pad, uinfo->_sifields._pad, SI_PAD_SIZE)) + return -EFAULT; + set_fs (KERNEL_DS); + ret = sys_rt_sigqueueinfo(pid, sig, &info); + set_fs (old_fs); + return ret; +} --- linux-2.5.73/arch/mips64/kernel/signal.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/signal.c 2003-06-27 15:56:23.000000000 -0700 @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -21,118 +22,25 @@ #include #include -#include +#include #include #include #include #include +#include #define DEBUG_SIG 0 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) extern asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs); -extern asmlinkage int save_fp_context(struct sigcontext *sc); -extern asmlinkage int restore_fp_context(struct sigcontext *sc); -extern asmlinkage void syscall_trace(void); - -int copy_siginfo_to_user(siginfo_t *to, siginfo_t *from) -{ - if (!access_ok (VERIFY_WRITE, to, sizeof(siginfo_t))) - return -EFAULT; - if (from->si_code < 0) - return __copy_to_user(to, from, sizeof(siginfo_t)); - else { - int err; - - /* If you change siginfo_t structure, please be sure - this code is fixed accordingly. - It should never copy any pad contained in the structure - to avoid security leaks, but must copy the generic - 3 ints plus the relevant union member. */ - err = __put_user(from->si_signo, &to->si_signo); - err |= __put_user(from->si_errno, &to->si_errno); - err |= __put_user((short)from->si_code, &to->si_code); - switch (from->si_code >> 16) { - case __SI_FAULT >> 16: - err |= __put_user((long)from->si_addr, &to->si_addr); - break; - case __SI_CHLD >> 16: - err |= __put_user(from->si_utime, &to->si_utime); - err |= __put_user(from->si_stime, &to->si_stime); - err |= __put_user(from->si_status, &to->si_status); - default: - err |= __put_user(from->si_pid, &to->si_pid); - err |= __put_user(from->si_uid, &to->si_uid); - break; - /* case __SI_RT: This is not generated by the kernel as of now. */ - } - return err; - } -} - -static inline int store_fp_context(struct sigcontext *sc) -{ - unsigned int fcr0; - int err = 0; - - err |= __copy_to_user(&sc->sc_fpregs[0], - ¤t->thread.fpu.hard.fp_regs[0], NUM_FPU_REGS * - sizeof(unsigned long)); - err |= __copy_to_user(&sc->sc_fpc_csr, ¤t->thread.fpu.hard.control, - sizeof(unsigned int)); - __asm__ __volatile__("cfc1 %0, $0\n\t" : "=r" (fcr0)); - err |= __copy_to_user(&sc->sc_fpc_eir, &fcr0, sizeof(unsigned int)); - - return err; -} - -static inline int refill_fp_context(struct sigcontext *sc) -{ - int err = 0; - - if (verify_area(VERIFY_READ, sc, sizeof(*sc))) - return -EFAULT; - err |= __copy_from_user(¤t->thread.fpu.hard.fp_regs[0], - &sc->sc_fpregs[0], NUM_FPU_REGS * sizeof(unsigned long)); - err |= __copy_from_user(¤t->thread.fpu.hard.control, &sc->sc_fpc_csr, - sizeof(unsigned int)); - return err; -} +extern asmlinkage void do_syscall_trace(void); /* * Atomically swap in the new signal mask, and wait for a signal. */ -asmlinkage inline int -sys_sigsuspend(abi64_no_regargs, struct pt_regs regs) -{ - sigset_t *uset, saveset, newset; - - save_static(®s); - uset = (sigset_t *) regs.regs[4]; - if (copy_from_user(&newset, uset, sizeof(sigset_t))) - return -EFAULT; - sigdelsetmask(&newset, ~_BLOCKABLE); - - spin_lock_irq(¤t->sigmask_lock); - saveset = current->blocked; - current->blocked = newset; - recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); - - regs.regs[2] = EINTR; - regs.regs[7] = 1; - while (1) { - current->state = TASK_INTERRUPTIBLE; - schedule(); - if (do_signal(&saveset, ®s)) - return -EINTR; - } -} - -asmlinkage int -sys_rt_sigsuspend(abi64_no_regargs, struct pt_regs regs) +asmlinkage int sys_rt_sigsuspend(abi64_no_regargs, struct pt_regs regs) { sigset_t *unewset, saveset, newset; size_t sigsetsize; @@ -149,11 +57,11 @@ sys_rt_sigsuspend(abi64_no_regargs, stru return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); + spin_lock_irq(¤t->sighand->siglock); saveset = current->blocked; current->blocked = newset; recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); + spin_unlock_irq(¤t->sighand->siglock); regs.regs[2] = EINTR; regs.regs[7] = 1; @@ -165,47 +73,7 @@ sys_rt_sigsuspend(abi64_no_regargs, stru } } -asmlinkage int -sys_sigaction(int sig, const struct sigaction *act, struct sigaction *oact) -{ - struct k_sigaction new_ka, old_ka; - int ret; - int err = 0; - - if (act) { - old_sigset_t mask; - - if (!access_ok(VERIFY_READ, act, sizeof(*act))) - return -EFAULT; - err |= __get_user(new_ka.sa.sa_handler, &act->sa_handler); - err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags); - err |= __get_user(mask, &act->sa_mask.sig[0]); - err |= __get_user(new_ka.sa.sa_restorer, &act->sa_restorer); - if (err) - return -EFAULT; - - siginitset(&new_ka.sa.sa_mask, mask); - } - - ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); - - if (!ret && oact) { - if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact))) - return -EFAULT; - err |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags); - err |= __put_user(old_ka.sa.sa_handler, &oact->sa_handler); - err |= __put_user(old_ka.sa.sa_mask.sig[0], oact->sa_mask.sig); - err |= __put_user(0, &oact->sa_mask.sig[1]); - err |= __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer); - if (err) - return -EFAULT; - } - - return ret; -} - -asmlinkage int -sys_sigaltstack(abi64_no_regargs, struct pt_regs regs) +asmlinkage int sys_sigaltstack(abi64_no_regargs, struct pt_regs regs) { const stack_t *uss = (const stack_t *) regs.regs[4]; stack_t *uoss = (stack_t *) regs.regs[5]; @@ -214,10 +82,8 @@ sys_sigaltstack(abi64_no_regargs, struct return do_sigaltstack(uss, uoss, usp); } -asmlinkage int -restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) +asmlinkage int restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) { - int owned_fp; int err = 0; err |= __get_user(regs->cp0_epc, &sc->sc_pc); @@ -240,26 +106,20 @@ restore_sigcontext(struct pt_regs *regs, restore_gp_reg(31); #undef restore_gp_reg - err |= __get_user(owned_fp, &sc->sc_ownedfp); - if (owned_fp) { - if (IS_FPU_OWNER()) { - CLEAR_FPU_OWNER(); - regs->cp0_status &= ~ST0_CU1; - } - current->used_math = 1; - err |= refill_fp_context(sc); + err |= __get_user(current->used_math, &sc->sc_used_math); + + if (current->used_math) { + /* restore fpu context if we have used it before */ + own_fpu(); + err |= restore_fp_context(sc); + } else { + /* signal handler may have used FPU. Give it up. */ + loose_fpu(); } return err; } -struct sigframe { - u32 sf_ass[4]; /* argument save space for o32 */ - u32 sf_code[2]; /* signal trampoline */ - struct sigcontext sf_sc; - sigset_t sf_mask; -}; - struct rt_sigframe { u32 rs_ass[4]; /* argument save space for o32 */ u32 rs_code[2]; /* signal trampoline */ @@ -267,42 +127,6 @@ struct rt_sigframe { struct ucontext rs_uc; }; -asmlinkage void sys_sigreturn(abi64_no_regargs, struct pt_regs regs) -{ - struct sigframe *frame; - sigset_t blocked; - - frame = (struct sigframe *) regs.regs[29]; - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__copy_from_user(&blocked, &frame->sf_mask, sizeof(blocked))) - goto badframe; - - sigdelsetmask(&blocked, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); - current->blocked = blocked; - recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); - - if (restore_sigcontext(®s, &frame->sf_sc)) - goto badframe; - - /* - * Don't let your children do this ... - */ - if (current->ptrace & PT_TRACESYS) - syscall_trace(); - __asm__ __volatile__( - "move\t$29, %0\n\t" - "j\tret_from_sys_call" - :/* no outputs */ - :"r" (®s)); - /* Unreached */ - -badframe: - force_sig(SIGSEGV, current); -} - asmlinkage void sys_rt_sigreturn(abi64_no_regargs, struct pt_regs regs) { struct rt_sigframe *frame; @@ -316,10 +140,10 @@ asmlinkage void sys_rt_sigreturn(abi64_n goto badframe; sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); + spin_lock_irq(¤t->sighand->siglock); current->blocked = set; recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); + spin_unlock_irq(¤t->sighand->siglock); if (restore_sigcontext(®s, &frame->rs_uc.uc_mcontext)) goto badframe; @@ -335,7 +159,7 @@ asmlinkage void sys_rt_sigreturn(abi64_n */ __asm__ __volatile__( "move\t$29, %0\n\t" - "j\tret_from_sys_call" + "j\tsyscall_exit" :/* no outputs */ :"r" (®s)); /* Unreached */ @@ -344,12 +168,12 @@ badframe: force_sig(SIGSEGV, current); } -static inline int setup_sigcontext(struct pt_regs *regs, - struct sigcontext *sc) +static inline int setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc) { int err = 0; err |= __put_user(regs->cp0_epc, &sc->sc_pc); + err |= __put_user(regs->cp0_status, &sc->sc_status); #define save_gp_reg(i) do { \ err |= __put_user(regs->regs[i], &sc->sc_regs[i]); \ @@ -370,20 +194,22 @@ static inline int setup_sigcontext(struc err |= __put_user(regs->cp0_cause, &sc->sc_cause); err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr); - if (current->used_math) { /* fp is active. */ - if (IS_FPU_OWNER()) { - lazy_fpu_switch(current, 0); - CLEAR_FPU_OWNER(); - regs->cp0_status &= ~ST0_CU1; - } - err |= __put_user(1, &sc->sc_ownedfp); - err |= store_fp_context(sc); - current->used_math = 0; - } else { - err |= __put_user(0, &sc->sc_ownedfp); + err |= __put_user(current->used_math, &sc->sc_used_math); + + if (!current->used_math) + goto out; + + /* + * Save FPU state to signal context. Signal handler will "inherit" + * current FPU state. + */ + if (!is_fpu_owner()) { + own_fpu(); + restore_fp(current); } - err |= __put_user(regs->cp0_status, &sc->sc_status); + err |= save_fp_context(sc); +out: return err; } @@ -391,13 +217,20 @@ static inline int setup_sigcontext(struc * Determine which stack to use.. */ static inline void *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, - size_t frame_size) + size_t frame_size) { unsigned long sp; /* Default to using normal stack */ sp = regs->regs[29]; + /* + * FPU emulator may have it's own trampoline active just + * above the user stack, 16-bytes before the next lowest + * 16 byte boundary. Try to avoid trashing it. + */ + sp -= 32; + /* This is the X/Open sanctioned signal stack switching. */ if ((ka->sa.sa_flags & SA_ONSTACK) && ! on_sig_stack(sp)) sp = current->sas_ss_sp + current->sas_ss_size; @@ -405,96 +238,25 @@ static inline void *get_sigframe(struct return (void *)((sp - frame_size) & ALMASK); } -static void inline setup_frame(struct k_sigaction * ka, struct pt_regs *regs, - int signr, sigset_t *set) +static void inline setup_rt_frame(struct k_sigaction * ka, + struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info) { - struct sigframe *frame; + struct rt_sigframe *frame; int err = 0; frame = get_sigframe(ka, regs, sizeof(*frame)); if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - /* Set up to return from userspace. If provided, use a stub already - in userspace. */ - if (ka->sa.sa_flags & SA_RESTORER) - regs->regs[31] = (unsigned long) ka->sa.sa_restorer; - else { - /* - * Set up the return code ... - * - * li v0, __NR_sigreturn - * syscall - */ - err |= __put_user(0x24020000 + __NR_sigreturn, - frame->sf_code + 0); - err |= __put_user(0x0000000c , - frame->sf_code + 1); - flush_cache_sigtramp((unsigned long) frame->sf_code); - } - - err |= setup_sigcontext(regs, &frame->sf_sc); - err |= __copy_to_user(&frame->sf_mask, set, sizeof(*set)); - if (err) - goto give_sigsegv; - /* - * Arguments to signal handler: - * - * a0 = signal number - * a1 = 0 (should be cause) - * a2 = pointer to struct sigcontext + * Set up the return code ... * - * $25 and c0_epc point to the signal handler, $29 points to the - * struct sigframe. + * li v0, __NR_rt_sigreturn + * syscall */ - regs->regs[ 4] = signr; - regs->regs[ 5] = 0; - regs->regs[ 6] = (unsigned long) &frame->sf_sc; - regs->regs[29] = (unsigned long) frame; - regs->regs[31] = (unsigned long) frame->sf_code; - regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler; - -#if DEBUG_SIG - printk("SIG deliver (%s:%d): sp=0x%p pc=0x%p ra=0x%p\n", - current->comm, current->pid, frame, regs->cp0_epc, frame->code); -#endif - return; - -give_sigsegv: - if (signr == SIGSEGV) - ka->sa.sa_handler = SIG_DFL; - force_sig(SIGSEGV, current); -} - -static void inline setup_rt_frame(struct k_sigaction * ka, - struct pt_regs *regs, int signr, - sigset_t *set, siginfo_t *info) -{ - struct rt_sigframe *frame; - int err = 0; - - frame = get_sigframe(ka, regs, sizeof(*frame)); - if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) - goto give_sigsegv; - - /* Set up to return from userspace. If provided, use a stub already - in userspace. */ - if (ka->sa.sa_flags & SA_RESTORER) - regs->regs[31] = (unsigned long) ka->sa.sa_restorer; - else { - /* - * Set up the return code ... - * - * li v0, __NR_rt_sigreturn - * syscall - */ - err |= __put_user(0x24020000 + __NR_rt_sigreturn, - frame->rs_code + 0); - err |= __put_user(0x0000000c , - frame->rs_code + 1); - flush_cache_sigtramp((unsigned long) frame->rs_code); - } + err |= __put_user(0x24020000 + __NR_rt_sigreturn, frame->rs_code + 0); + err |= __put_user(0x0000000c , frame->rs_code + 1); + flush_cache_sigtramp((unsigned long) frame->rs_code); /* Create siginfo. */ err |= copy_siginfo_to_user(&frame->rs_info, info); @@ -532,8 +294,9 @@ static void inline setup_rt_frame(struct regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler; #if DEBUG_SIG - printk("SIG deliver (%s:%d): sp=0x%p pc=0x%p ra=0x%p\n", - current->comm, current->pid, frame, regs->cp0_epc, frame->code); + printk("SIG deliver (%s:%d): sp=0x%p pc=0x%lx ra=0x%p\n", + current->comm, current->pid, + frame, regs->cp0_epc, regs->regs[31]); #endif return; @@ -544,29 +307,10 @@ give_sigsegv: } static inline void handle_signal(unsigned long sig, siginfo_t *info, - sigset_t *oldset, struct pt_regs *regs) + sigset_t *oldset, struct pt_regs *regs) { - struct k_sigaction *ka = ¤t->sig->action[sig-1]; - - if (ka->sa.sa_flags & SA_SIGINFO) - setup_rt_frame(ka, regs, sig, oldset, info); - else - setup_frame(ka, regs, sig, oldset); - - if (ka->sa.sa_flags & SA_ONESHOT) - ka->sa.sa_handler = SIG_DFL; - if (!(ka->sa.sa_flags & SA_NODEFER)) { - spin_lock_irq(¤t->sigmask_lock); - sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); - sigaddset(¤t->blocked,sig); - recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); - } -} + struct k_sigaction *ka = ¤t->sighand->action[sig-1]; -static inline void syscall_restart(struct pt_regs *regs, - struct k_sigaction *ka) -{ switch(regs->regs[0]) { case ERESTARTNOHAND: regs->regs[2] = EINTR; @@ -583,10 +327,23 @@ static inline void syscall_restart(struc } regs->regs[0] = 0; /* Don't deal with this again. */ + + setup_rt_frame(ka, regs, sig, oldset, info); + + if (ka->sa.sa_flags & SA_ONESHOT) + ka->sa.sa_handler = SIG_DFL; + if (!(ka->sa.sa_flags & SA_NODEFER)) { + spin_lock_irq(¤t->sighand->siglock); + sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); + sigaddset(¤t->blocked,sig); + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + } } -extern int do_irix_signal(sigset_t *oldset, struct pt_regs *regs); + extern int do_signal32(sigset_t *oldset, struct pt_regs *regs); +extern int do_irix_signal(sigset_t *oldset, struct pt_regs *regs); asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs) { @@ -594,7 +351,7 @@ asmlinkage int do_signal(sigset_t *oldse int signr; #ifdef CONFIG_BINFMT_ELF32 - if (current->thread.mflags & MF_32BIT) { + if (current->thread.mflags & MF_32BIT_REGS) { return do_signal32(oldset, regs); } #endif @@ -604,9 +361,6 @@ asmlinkage int do_signal(sigset_t *oldse signr = get_signal_to_deliver(&info, regs, NULL); if (signr > 0) { - if (regs->regs[0]) - syscall_restart(regs, ka); - /* Whee! Actually deliver the signal. */ handle_signal(signr, &info, oldset, regs); return 1; } @@ -626,3 +380,29 @@ asmlinkage int do_signal(sigset_t *oldse } return 0; } + + +/* + * notification of userspace execution resumption + * - triggered by current->work.notify_resume + */ +asmlinkage void do_notify_resume(struct pt_regs *regs, sigset_t *oldset, + __u32 thread_info_flags) +{ + /* deal with pending signal delivery */ + if (thread_info_flags & _TIF_SIGPENDING) { +#ifdef CONFIG_BINFMT_ELF32 + if (likely((current->thread.mflags & MF_32BIT_REGS))) { + do_signal32(oldset, regs); + return; + } +#endif +#ifdef CONFIG_BINFMT_IRIX + if (unlikely(current->personality != PER_LINUX)) { + do_irix_signal(oldset, regs); + return; + } +#endif + do_signal(oldset, regs); + } +} --- linux-2.5.73/arch/mips64/kernel/smp.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/smp.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,100 +1,156 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2000, 2001 Kanoj Sarcar + * Copyright (C) 2000, 2001 Ralf Baechle + * Copyright (C) 2000, 2001 Silicon Graphics, Inc. + * Copyright (C) 2000, 2001 Broadcom Corporation + */ #include +#include +#include #include +#include #include #include +#include #include #include #include -#include -#include #include +#include #include #include #include #include -#include +#include -#ifdef CONFIG_SGI_IP27 +int smp_threads_ready; /* Not used */ -#include -#include -#include -#include -#include +// static atomic_t cpus_booted = ATOMIC_INIT(0); +atomic_t cpus_booted = ATOMIC_INIT(0); -#define DORESCHED 0xab -#define DOCALL 0xbc +cpumask_t phys_cpu_present_map; /* Bitmask of physically CPUs */ +cpumask_t cpu_online_map; /* Bitmask of currently online CPUs */ +int __cpu_number_map[NR_CPUS]; +int __cpu_logical_map[NR_CPUS]; -static void sendintr(int destid, unsigned char status) -{ - int irq; +/* These are defined by the board-specific code. */ -#if (CPUS_PER_NODE == 2) - switch (status) { - case DORESCHED: irq = CPU_RESCHED_A_IRQ; break; - case DOCALL: irq = CPU_CALL_A_IRQ; break; - default: panic("sendintr"); - } - irq += cputoslice(destid); +/* + * Cause the function described by call_data to be executed on the passed + * cpu. When the function has finished, increment the finished field of + * call_data. + */ +void core_send_ipi(int cpu, unsigned int action); - /* - * Convert the compact hub number to the NASID to get the correct - * part of the address space. Then set the interrupt bit associated - * with the CPU we want to send the interrupt to. - */ - REMOTE_HUB_SEND_INTR(COMPACT_TO_NASID_NODEID(cputocnode(destid)), - FAST_IRQ_TO_LEVEL(irq)); -#else - << Bomb! Must redefine this for more than 2 CPUS. >> -#endif -} +/* + * Clear all undefined state in the cpu, set up sp and gp to the passed + * values, and kick the cpu into smp_bootstrap(); + */ +void prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp); -#endif /* CONFIG_SGI_IP27 */ +/* + * After we've done initial boot, this function is called to allow the + * board code to clean up state, if needed + */ +void prom_init_secondary(void); + +void prom_smp_finish(void); -/* The 'big kernel lock' */ -int smp_threads_ready; /* Not used */ -atomic_t smp_commenced = ATOMIC_INIT(0); -struct cpuinfo_mips cpu_data[NR_CPUS]; -int smp_num_cpus = 1; /* Number that came online. */ -int __cpu_number_map[NR_CPUS]; -int __cpu_logical_map[NR_CPUS]; cycles_t cacheflush_time; +unsigned long cache_decay_ticks; -static void smp_tune_scheduling (void) +void smp_tune_scheduling (void) { -} + struct cache_desc *cd = ¤t_cpu_data.scache; + unsigned long cachesize; /* kB */ + unsigned long bandwidth = 350; /* MB/s */ + unsigned long cpu_khz; -void __init smp_boot_cpus(void) -{ - extern void allowboot(void); + /* + * Crude estimate until we actually meassure ... + */ + cpu_khz = loops_per_jiffy * 2 * HZ / 1000; - init_new_context(current, &init_mm); - current->processor = 0; - init_idle(); - smp_tune_scheduling(); - allowboot(); -} + /* + * Rough estimation for SMP scheduling, this is the number of + * cycles it takes for a fully memory-limited process to flush + * the SMP-local cache. + * + * (For a P5 this pretty much means we will choose another idle + * CPU almost always at wakeup time (this is due to the small + * L1 cache), on PIIs it's around 50-100 usecs, depending on + * the cache size) + */ + if (!cpu_khz) { + /* + * This basically disables processor-affinity scheduling on SMP + * without a cycle counter. Currently all SMP capable MIPS + * processors have a cycle counter. + */ + cacheflush_time = 0; + return; + } -void __init smp_commence(void) -{ - wmb(); - atomic_set(&smp_commenced,1); + cachesize = cd->linesz * cd->sets * cd->ways; + cacheflush_time = (cpu_khz>>10) * (cachesize<<10) / bandwidth; + cache_decay_ticks = (long)cacheflush_time/cpu_khz * HZ / 1000; + + printk("per-CPU timeslice cutoff: %ld.%02ld usecs.\n", + (long)cacheflush_time/(cpu_khz/1000), + ((long)cacheflush_time*100/(cpu_khz/1000)) % 100); + printk("task migration cache decay timeout: %ld msecs.\n", + (cache_decay_ticks + 1) * 1000 / HZ); +} + +void __init smp_callin(void) +{ +#if 0 + calibrate_delay(); + smp_store_cpu_info(cpuid); +#endif } -static void stop_this_cpu(void *dummy) +#ifndef CONFIG_SGI_IP27 +/* + * Hook for doing final board-specific setup after the generic smp setup + * is done + */ +asmlinkage void start_secondary(void) { + unsigned int cpu = smp_processor_id(); + + cpu_probe(); + prom_init_secondary(); + per_cpu_trap_init(); + /* - * Remove this CPU + * XXX parity protection should be folded in here when it's converted + * to an option instead of something based on .cputype */ - for (;;); -} - -void smp_send_stop(void) -{ - smp_call_function(stop_this_cpu, NULL, 1, 0); - smp_num_cpus = 1; + pgd_current[cpu] = init_mm.pgd; + cpu_data[cpu].udelay_val = loops_per_jiffy; + prom_smp_finish(); + printk("Slave cpu booted successfully\n"); + CPUMASK_SETB(cpu_online_map, cpu); + atomic_inc(&cpus_booted); + cpu_idle(); } +#endif /* CONFIG_SGI_IP27 */ /* * this function sends a 'reschedule' IPI to another CPU. @@ -103,14 +159,12 @@ void smp_send_stop(void) */ void smp_send_reschedule(int cpu) { - sendintr(cpu, DORESCHED); + core_send_ipi(cpu, SMP_RESCHEDULE_YOURSELF); } -/* Not really SMP stuff ... */ -int setup_profiling_timer(unsigned int multiplier) -{ - return 0; -} +static spinlock_t call_lock = SPIN_LOCK_UNLOCKED; + +struct call_data_struct *call_data; /* * Run a function on all other CPUs. @@ -122,23 +176,18 @@ int setup_profiling_timer(unsigned int m * * Does not return until remote CPUs are nearly ready to execute * or are or have executed. + * + * You must not call this function with disabled interrupts or from a + * hardware interrupt handler or from a bottom half handler. */ -static volatile struct call_data_struct { - void (*func) (void *info); - void *info; - atomic_t started; - atomic_t finished; - int wait; -} *call_data; - -int smp_call_function (void (*func) (void *info), void *info, int retry, +int smp_call_function (void (*func) (void *info), void *info, int retry, int wait) { struct call_data_struct data; - int i, cpus = smp_num_cpus-1; - static spinlock_t lock = SPIN_LOCK_UNLOCKED; + int i, cpus = num_online_cpus() - 1; + int cpu = smp_processor_id(); - if (cpus == 0) + if (!cpus) return 0; data.func = func; @@ -148,12 +197,13 @@ int smp_call_function (void (*func) (voi if (wait) atomic_set(&data.finished, 0); - spin_lock_bh(&lock); + spin_lock(&call_lock); call_data = &data; + /* Send a message to all other CPUs and wait for them to respond */ - for (i = 0; i < smp_num_cpus; i++) - if (smp_processor_id() != i) - sendintr(i, DOCALL); + for (i = 0; i < NR_CPUS; i++) + if (cpu_online(cpu) && cpu != smp_processor_id()) + core_send_ipi(i, SMP_CALL_FUNCTION); /* Wait for response */ /* FIXME: lock-up detection, backtrace on lock-up */ @@ -163,34 +213,62 @@ int smp_call_function (void (*func) (voi if (wait) while (atomic_read(&data.finished) != cpus) barrier(); - spin_unlock_bh(&lock); + spin_unlock(&call_lock); + return 0; } -extern void smp_call_function_interrupt(int irq, void *d, struct pt_regs *r) +void smp_call_function_interrupt(void) { void (*func) (void *info) = call_data->func; void *info = call_data->info; int wait = call_data->wait; + irq_enter(); /* * Notify initiating CPU that I've grabbed the data and am * about to execute the function. */ + mb(); atomic_inc(&call_data->started); /* * At this point the info structure may be out of scope unless wait==1. */ + irq_enter(); (*func)(info); - if (wait) + irq_exit(); + + if (wait) { + mb(); atomic_inc(&call_data->finished); + } +} + +static void stop_this_cpu(void *dummy) +{ + /* + * Remove this CPU: + */ + clear_bit(smp_processor_id(), &cpu_online_map); + local_irq_enable(); /* May need to service _machine_restart IPI */ + for (;;); /* Wait if available. */ +} + +void smp_send_stop(void) +{ + smp_call_function(stop_this_cpu, NULL, 1, 0); +} + +/* Not really SMP stuff ... */ +int setup_profiling_timer(unsigned int multiplier) +{ + return 0; } - static void flush_tlb_all_ipi(void *info) { - _flush_tlb_all(); + local_flush_tlb_all(); } void flush_tlb_all(void) @@ -200,15 +278,15 @@ void flush_tlb_all(void) static void flush_tlb_mm_ipi(void *mm) { - _flush_tlb_mm((struct mm_struct *)mm); + local_flush_tlb_mm((struct mm_struct *)mm); } /* - * The following tlb flush calls are invoked when old translations are + * The following tlb flush calls are invoked when old translations are * being torn down, or pte attributes are changing. For single threaded * address spaces, a new context is obtained on the current cpu, and tlb * context on other cpus are invalidated to force a new context allocation - * at switch_mm time, should the mm ever be used on other cpus. For + * at switch_mm time, should the mm ever be used on other cpus. For * multithreaded address spaces, intercpu interrupts have to be sent. * Another case where intercpu interrupts are required is when the target * mm might be active on another cpu (eg debuggers doing the flushes on @@ -224,17 +302,16 @@ void flush_tlb_mm(struct mm_struct *mm) smp_call_function(flush_tlb_mm_ipi, (void *)mm, 1, 1); } else { int i; - for (i = 0; i < smp_num_cpus; i++) + for (i = 0; i < num_online_cpus(); i++) if (smp_processor_id() != i) - CPU_CONTEXT(i, mm) = 0; + cpu_context(i, mm) = 0; } - _flush_tlb_mm(mm); + local_flush_tlb_mm(mm); preempt_enable(); } struct flush_tlb_data { - struct mm_struct *mm; struct vm_area_struct *vma; unsigned long addr1; unsigned long addr2; @@ -244,13 +321,14 @@ static void flush_tlb_range_ipi(void *in { struct flush_tlb_data *fd = (struct flush_tlb_data *)info; - _flush_tlb_range(fd->vma, fd->addr1, fd->addr2); + local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); } void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - preempt_disable(); + struct mm_struct *mm = vma->vm_mm; + preempt_disable(); if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { struct flush_tlb_data fd; @@ -260,26 +338,41 @@ void flush_tlb_range(struct vm_area_stru smp_call_function(flush_tlb_range_ipi, (void *)&fd, 1, 1); } else { int i; - for (i = 0; i < smp_num_cpus; i++) + for (i = 0; i < num_online_cpus(); i++) if (smp_processor_id() != i) - CPU_CONTEXT(i, mm) = 0; + cpu_context(i, mm) = 0; } - _flush_tlb_range(mm, start, end); - + local_flush_tlb_range(vma, start, end); preempt_enable(); } +static void flush_tlb_kernel_range_ipi(void *info) +{ + struct flush_tlb_data *fd = (struct flush_tlb_data *)info; + + local_flush_tlb_kernel_range(fd->addr1, fd->addr2); +} + +void flush_tlb_kernel_range(unsigned long start, unsigned long end) +{ + struct flush_tlb_data fd; + + fd.addr1 = start; + fd.addr2 = end; + smp_call_function(flush_tlb_kernel_range_ipi, (void *)&fd, 1, 1); + local_flush_tlb_kernel_range(start, end); +} + static void flush_tlb_page_ipi(void *info) { struct flush_tlb_data *fd = (struct flush_tlb_data *)info; - _flush_tlb_page(fd->vma, fd->addr1); + local_flush_tlb_page(fd->vma, fd->addr1); } void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) { preempt_disable(); - if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { struct flush_tlb_data fd; @@ -288,12 +381,28 @@ void flush_tlb_page(struct vm_area_struc smp_call_function(flush_tlb_page_ipi, (void *)&fd, 1, 1); } else { int i; - for (i = 0; i < smp_num_cpus; i++) + for (i = 0; i < num_online_cpus(); i++) if (smp_processor_id() != i) - CPU_CONTEXT(i, vma->vm_mm) = 0; + cpu_context(i, vma->vm_mm) = 0; } - _flush_tlb_page(vma, page); - + local_flush_tlb_page(vma, page); preempt_enable(); } +static void flush_tlb_one_ipi(void *info) +{ + unsigned long vaddr = (unsigned long) info; + + local_flush_tlb_one(vaddr); +} + +void flush_tlb_one(unsigned long vaddr) +{ + smp_call_function(flush_tlb_one_ipi, (void *) vaddr, 1, 1); + local_flush_tlb_one(vaddr); +} + +EXPORT_SYMBOL(flush_tlb_page); +EXPORT_SYMBOL(flush_tlb_one); +EXPORT_SYMBOL(cpu_data); +EXPORT_SYMBOL(synchronize_irq); --- linux-2.5.73/arch/mips64/kernel/softfp.S 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,666 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 1999, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 by Silicon Graphics, Inc. - * - * For now it's just a crude hack good enough to run certain fp programs like - * Mozilla. - * XXX: Handle MIPS II/III/IV/V enhancements, exceptions, ... - */ -#include -#include - -#ifndef __KERNEL__ -#define printk printf -#endif - -#define LOCK_KERNEL -#define UNLOCK_KERNEL - -/* - * This duplicates definitions from . - */ -#define KERN_EMERG "<0>" /* system is unusable */ -#define KERN_ALERT "<1>" /* action must be taken immediately */ -#define KERN_CRIT "<2>" /* critical conditions */ -#define KERN_ERR "<3>" /* error conditions */ -#define KERN_WARNING "<4>" /* warning conditions */ -#define KERN_NOTICE "<5>" /* normal but significant condition */ -#define KERN_INFO "<6>" /* informational */ -#define KERN_DEBUG "<7>" /* debug-level messages */ - -/* - * This duplicates definitions from - */ -#define SIGILL 4 /* Illegal instruction (ANSI). */ - -/* - * Definitions about the instruction format - */ -#define fd_shift 6 -#define fr_shift 21 -#define fs_shift 11 -#define ft_shift 16 - -/* - * NaNs as use by the MIPS architecture - */ -#define S_QNaN 0x7fbfffff -#define D_QNaN 0x7ff7ffffffffffff -#define W_QNaN 0x7fffffff -#define L_QNaN 0x7fffffffffffffff - -/* - * Checking for NaNs - */ -#define S_is_QNaN(reg,res) \ - sll res, reg, S_F_size - S_F_bits -#define D_is_QNaN(reg1,reg2,res) \ - sll res, reg1, (D_F_size - 32) - (D_F_bits - 32); \ - or res, reg2 - -/* - * Checking for Denorms - */ -#define S_is_Denorm(reg,res) \ - li res, 1 << (S_F_bits - 1); \ - and reg, res - -/* - * Some constants that define the properties of single precission numbers. - */ -#define S_M_prec 24 -#define S_E_max 127 -#define S_E_min -126 -#define S_E_bias 127 -#define S_E_bits 8 -#define S_F_bits 23 -#define S_F_size 32 - -/* Set temp0, if exponent of reg is S_E_max + 1. */ -#define S_is_E_max(reg,temp0,temp1) \ - li temp0, (S_E_max + 1 + S_E_bias) << S_F_bits; \ - and temp1, temp0, reg; \ - seq temp0, temp1 /* temp0 != 0 if NaN */ - -/* Clear temp0, if exponent of reg is S_E_min - 1. */ -#define S_is_E_min(reg,temp0) \ - li temp0, (S_E_min - 1 + S_E_bias) << S_F_bits; \ - and temp0, reg /* temp0 == 0 if denorm or zero */ - -/* Set temp0 if reg is a NaN assuming S_is_E_max is true */ -#define S_get_F(reg,temp0) \ - li temp0, (1 << S_F_bits) - 1; \ - and temp0, reg /* temp0 != 0 if NaN */ - -/* Set res if fraction of reg is != 0. */ -#define S_is_Inf(reg,res) \ - li res, (1 << S_F_bits) - 1; \ - and res, reg /* temp0 == 0 if Inf */ - - -/* - * Some constants that define the properties of double precission numbers. - */ -#define D_M_prec 53 -#define D_E_max 1023 -#define D_E_min -1022 -#define D_E_bias 1023 -#define D_E_bits 8 -#define D_F_bits 52 -#define D_F_size 64 - -/* Set temp0, if exponent of reg1/reg2 is D_E_max. */ -#define D_is_E_max(reg1,reg2,temp0,temp1) \ - li temp0, (D_E_max + 1 + D_E_bias) << (D_F_bits - 32); \ - and temp1, temp0, reg1; \ - seq temp0, temp1 /* temp0 != 0 if NaN */ - -/* Clear temp0, if exponent of reg is D_E_min. */ -#define D_is_E_min(reg1,reg2,res) \ - li res, (D_E_min + 1 + D_E_bias) << (D_F_bits - 32); \ - and res, reg1 /* temp0 == 0 if NaN or zero */ - -/* Set res if reg is a NaN assuming S_is_E_max is true */ -#define D_get_F(reg1,reg2,res) \ - li res, (1 << (D_F_bits - 32)) - 1; \ - and res, reg1 /* temp0 != 0 if NaN */ - -/* Set temp0 if reg1/reg2 is a NaN */ -#define D_is_NAN(reg1,reg2,temp0,temp1) \ - li temp0, (1 << (D_F_bits - 32) - 1; \ - and temp0, reg1; \ - or temp0, reg2; \ - sne temp0, zero, temp0 /* temp0 != 0 if NaN */ - -/* Set res if fraction of reg1/reg2 is != 0. */ -#define D_is_Inf(reg1,reg2,res) \ - li res, (1 << (D_F_bits - 32)) - 1; \ - and res, reg1; \ - or res, reg2 /* temp0 == 0 if Inf */ - -/* Complain about yet unhandled instruction. */ -#define BITCH(insn) \ -insn: LOCK_KERNEL; \ - la a1, 8f; \ - TEXT(#insn); \ - la a0, nosim; \ - jal printk; \ - UNLOCK_KERNEL; \ - j done - - .data -nosim: .asciz KERN_DEBUG "Don't know how to simulate %s instruction\n" - .previous - -/* - * When we come here, we've saved some of the integer registers and - * reenabled interrupts. - */ -LEAF(simfp) - .set noreorder - .cpload $25 - .set reorder - - dsubu sp, 16 - .cprestore 20 - sd ra, 0(sp) - - /* For now we assume that we get the opcode to simulate passed in as - an argument. */ - move ta0, a0 - - /* - * First table lookup using insn[5:0] - */ - la ta1, lowtab - andi ta2, ta0, 0x3f - sll ta2, ta2, 3 - daddu ta1, ta2 - ld ta1, (ta1) - jr ta1 - END(simfp) - -/* - * We only decode the lower 3 of the 5 bit in the fmt field. That way we - * can keep the jump table significantly shorter. - */ -#define FMT_switch(insn,opc,temp0,temp1) \ -insn: srl temp0, opc, 18; \ - andi temp0, 0x1c; \ - la temp1, insn##.tab; \ - daddu temp0, temp1; \ - ld temp0, (temp0); \ - jr temp0; \ - \ - .data; \ -insn##.tab: \ - .dword insn##.s, insn##.d, unimp, unimp; \ - .dword insn##.w, insn##.l, unimp, unimp; \ - .previous - - BITCH(add) - BITCH(sub) - BITCH(mul) - BITCH(div) - BITCH(sqrt) - BITCH(abs) - BITCH(mov) - BITCH(neg) - BITCH(round.l) - BITCH(trunc.l) - BITCH(ceil.l) - BITCH(floor.l) - BITCH(round.w) - BITCH(trunc.w) - BITCH(ceil.w) - BITCH(floor.w) - BITCH(cvt.s) - BITCH(cvt.d) - -/* ------------------------------------------------------------------------ */ - -FMT_switch(cvt.w,ta0,ta1,ta2) - -/* Convert a single fp to a fixed point integer. */ -cvt.w.s: - srl ta1, ta0, fs_shift # Get source register - andi ta1, 31 - jal s_get_fpreg - - S_is_E_max(ta1,ta2,ta3) - beqz ta2, 3f - /* Might be a NaN or Inf. */ - S_get_F(ta1,ta2) - beqz ta2, 2f - - /* It's a NaN. IEEE says undefined. */ - /* Is it a QNaN? Then the result is a QNaN as well. */ - S_is_QNaN(ta1,ta2) - bltz ta2, 1f - - /* XXX Ok, it's a SNaN. Signal invalid exception, if enabled. - For now we don't signal and supply a QNaN for result. */ - -1: li ta2, W_QNaN - srl ta1, ta0, fd_shift # Put result register - andi ta1, 31 - jal s_put_fpreg - j done -2: - - S_is_Inf(ta1,ta2) - bnez ta2, 2f - - /* It's +/- Inf. Set register to +/- max. integer. */ - /* XXX Send invalid operation exception instead, if enabled. */ - srl ta1, ta1, 31 # Extract sign bit - li ta2, 0x7fffffff - addu ta2, ta1 - - srl ta1, ta0, fd_shift # Put result register - andi ta1, 31 - jal s_put_fpreg - j done -2: -3: - - /* But then it might be a denorm or zero? */ - S_is_E_min(ta1,ta2) - bnez ta2, 2f - - /* Ok, it's a denorm or zero. */ - S_get_F(ta1,ta2) - beqz ta2, 1f - - /* It's a denorm. */ - /* XXX Should be signaling inexact exception, if enabled. */ - /* Fall through. */ -1: - /* Yes, it is a denorm or zero. Supply a zero as result. */ - move ta2, zero - srl ta1, ta0, fd_shift # Put result register - andi ta1, 31 - jal s_put_fpreg - j done -2: - - /* XXX Ok, it's a normal number. We don't handle that case yet. - If we have fp hardware this case is unreached. Add this for - full fp simulation. */ - - /* Done, return. */ - ld ra, 0(sp) - daddu sp, 16 - jr ra - -/* Convert a double fp to a fixed point integer. */ -cvt.w.d: - srl ta1, ta0, fs_shift # Get source register - andi ta1, 31 - jal d_get_fpreg - - D_is_E_max(ta1,ta2,ta3,t0) - beqz ta3, 3f - - /* Might be a NaN or Inf. */ - D_get_F(ta1,ta2,ta3) - or ta3, ta2 - beqz ta3, 2f - - /* It's a NaN. IEEE says undefined. */ - /* Is it a QNaN? Then the result is a QNaN as well. */ - D_is_QNaN(ta1,ta2,ta3) - bltz ta3, 1f - - /* XXX Ok, it's a SNaN. Signal invalid exception, if enabled. - For now we don't signal and supply a QNaN for result. */ - -1: li ta2, W_QNaN - srl ta1, ta0, fd_shift # Put result register - andi ta1, 31 - jal s_put_fpreg - j done -2: - - D_is_Inf(ta1,ta2,ta3) - bnez ta3, 2f - - /* It's +/- Inf. Set register to +/- max. integer. */ - /* XXX Send invalid operation exception instead, if enabled. */ - srl ta1, ta1, 31 # Extract sign bit - li ta2, 0x7fffffff - addu ta2, ta1 - - srl ta1, ta0, fd_shift # Put result register - andi ta1, 31 - jal s_put_fpreg - j done -2: -3: - - /* But then it might be a denorm or zero? */ - D_is_E_min(ta1,ta2,ta3) - bnez ta3, 2f - - /* Ok, it's a denorm or zero. */ - D_get_F(ta1,ta2,ta3) - or ta3, ta2 - beqz ta3, 1f - - /* It's a denorm. */ - /* XXX Should be signaling inexact exception, if enabled. */ - /* Fall through. */ -1: - /* Yes, it is a denorm or zero. Supply a zero as result. */ - move ta2, zero - srl ta1, ta0, fd_shift # Put result register - andi ta1, 31 - jal s_put_fpreg - j done -2: - - /* XXX Ok, it's a normal number. We don't handle that case yet. - If we have fp hardware this case is only reached if the value - of the source register exceeds the range which is representable - in a single precission register. For now we kludge by returning - +/- maxint and don't signal overflow. */ - - srl ta1, ta1, 31 # Extract sign bit - li ta2, 0x7fffffff - addu ta2, ta1 - - srl ta1, ta0, fd_shift # Put result register - andi ta1, 31 - jal s_put_fpreg - - /* Done, return. */ - ld ra, 0(sp) - daddu sp, 16 - jr ra - -cvt.w.w = unimp # undefined result -cvt.w.l = unimp # undefined result - -/* MIPS III extension, no need to handle for 32bit OS. */ -cvt.l = unimp - -/* ------------------------------------------------------------------------ */ - - BITCH(c.f) - BITCH(c.un) - BITCH(c.eq) - BITCH(c.ueq) - BITCH(c.olt) - BITCH(c.ult) - BITCH(c.ole) - BITCH(c.ule) - BITCH(c.sf) - BITCH(c.ngle) - BITCH(c.seq) - BITCH(c.ngl) - BITCH(c.lt) - BITCH(c.nge) - BITCH(c.le) - BITCH(c.ngt) - -/* Get the single precission register which's number is in ta1. */ -s_get_fpreg: - .set noat - sll ta1, 3 - la AT, 1f - daddu AT, ta1 - jr AT - .set at - -1: mfc1 ta1, $0 - jr ra - mfc1 ta1, $1 - jr ra - mfc1 ta1, $2 - jr ra - mfc1 ta1, $3 - jr ra - mfc1 ta1, $4 - jr ra - mfc1 ta1, $5 - jr ra - mfc1 ta1, $6 - jr ra - mfc1 ta1, $7 - jr ra - mfc1 ta1, $8 - jr ra - mfc1 ta1, $9 - jr ra - mfc1 ta1, $10 - jr ra - mfc1 ta1, $11 - jr ra - mfc1 ta1, $12 - jr ra - mfc1 ta1, $13 - jr ra - mfc1 ta1, $14 - jr ra - mfc1 ta1, $15 - jr ra - mfc1 ta1, $16 - jr ra - mfc1 ta1, $17 - jr ra - mfc1 ta1, $18 - jr ra - mfc1 ta1, $19 - jr ra - mfc1 ta1, $20 - jr ra - mfc1 ta1, $21 - jr ra - mfc1 ta1, $22 - jr ra - mfc1 ta1, $23 - jr ra - mfc1 ta1, $24 - jr ra - mfc1 ta1, $25 - jr ra - mfc1 ta1, $26 - jr ra - mfc1 ta1, $27 - jr ra - mfc1 ta1, $28 - jr ra - mfc1 ta1, $29 - jr ra - mfc1 ta1, $30 - jr ra - mfc1 ta1, $31 - jr ra - -/* - * Put the value in ta2 into the single precission register which's number - * is in ta1. - */ -s_put_fpreg: - .set noat - sll ta1, 3 - la AT, 1f - daddu AT, ta1 - jr AT - .set at - -1: mtc1 ta2, $0 - jr ra - mtc1 ta2, $1 - jr ra - mtc1 ta2, $2 - jr ra - mtc1 ta2, $3 - jr ra - mtc1 ta2, $4 - jr ra - mtc1 ta2, $5 - jr ra - mtc1 ta2, $6 - jr ra - mtc1 ta2, $7 - jr ra - mtc1 ta2, $8 - jr ra - mtc1 ta2, $9 - jr ra - mtc1 ta2, $10 - jr ra - mtc1 ta2, $11 - jr ra - mtc1 ta2, $12 - jr ra - mtc1 ta2, $13 - jr ra - mtc1 ta2, $14 - jr ra - mtc1 ta2, $15 - jr ra - mtc1 ta2, $16 - jr ra - mtc1 ta2, $17 - jr ra - mtc1 ta2, $18 - jr ra - mtc1 ta2, $19 - jr ra - mtc1 ta2, $20 - jr ra - mtc1 ta2, $21 - jr ra - mtc1 ta2, $22 - jr ra - mtc1 ta2, $23 - jr ra - mtc1 ta2, $24 - jr ra - mtc1 ta2, $25 - jr ra - mtc1 ta2, $26 - jr ra - mtc1 ta2, $27 - jr ra - mtc1 ta2, $28 - jr ra - mtc1 ta2, $29 - jr ra - mtc1 ta2, $30 - jr ra - mtc1 ta2, $31 - jr ra - -/* Get the double precission register which's number is in ta1 into ta1/ta2. */ -d_get_fpreg: - .set noat - sll AT, ta1, 1 - sll ta1, 2 - daddu ta1, AT - la AT, 1f - daddu AT, ta1 - jr AT - .set at - -1: mfc1 ta1, $0 - mfc1 ta2, $1 - jr ra - mfc1 ta1, $2 - mfc1 ta2, $3 - jr ra - mfc1 ta1, $4 - mfc1 ta2, $5 - jr ra - mfc1 ta1, $6 - mfc1 ta2, $7 - jr ra - mfc1 ta1, $8 - mfc1 ta2, $9 - jr ra - mfc1 ta1, $10 - mfc1 ta2, $11 - jr ra - mfc1 ta1, $12 - mfc1 ta2, $13 - jr ra - mfc1 ta1, $14 - mfc1 ta2, $15 - jr ra - mfc1 ta1, $16 - mfc1 ta2, $17 - jr ra - mfc1 ta1, $18 - mfc1 ta2, $19 - jr ra - mfc1 ta1, $20 - mfc1 ta2, $21 - jr ra - mfc1 ta1, $22 - mfc1 ta2, $23 - jr ra - mfc1 ta1, $24 - mfc1 ta2, $25 - jr ra - mfc1 ta1, $26 - mfc1 ta2, $27 - jr ra - mfc1 ta1, $28 - mfc1 ta2, $29 - jr ra - mfc1 ta1, $30 - mfc1 ta2, $31 - jr ra - -/* - * Send an invalid operation exception. - */ -invalid: - ld ra, 0(sp) - daddu sp, 16 - jr ra - -/* - * Done, just skip over the current instruction - */ -done: - ld ra, 0(sp) - daddu sp, 16 - jr ra - -unimp: - /* We've run into an yet unknown instruction. This happens either - on new, yet unsupported CPU types or when the faulting instruction - is being executed for cache but has been overwritten in memory. */ - LOCK_KERNEL - move a1, ta0 - PRINT(KERN_DEBUG "FP support: unknown fp op %08lx, ") - PRINT("please mail to ralf@gnu.org.\n") - UNLOCK_KERNEL - - li a0, SIGILL # Die, sucker ... - move a1, $28 - jal force_sig - - ld ra, 0(sp) - daddu sp, 16 - jr ra - -/* - * Jump table for the lowest 6 bits of a cp1 instruction. - */ - .data -lowtab: .dword add, sub, mul, div, sqrt, abs, mov, neg - .dword round.l,trunc.l,ceil.l,floor.l,round.w,trunc.w,ceil.w,floor.w - .dword unimp, unimp, unimp, unimp, unimp, unimp, unimp, unimp - .dword unimp, unimp, unimp, unimp, unimp, unimp, unimp, unimp - .dword cvt.s, cvt.d, unimp, unimp, cvt.w, cvt.l, unimp, unimp - .dword unimp, unimp, unimp, unimp, unimp, unimp, unimp, unimp - .dword c.f, c.un, c.eq, c.ueq, c.olt, c.ult, c.ole, c.ule - .dword c.sf, c.ngle,c.seq, c.ngl, c.lt, c.nge, c.le, c.ngt --- linux-2.5.73/arch/mips64/kernel/syscall.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/syscall.c 2003-06-27 15:56:23.000000000 -0700 @@ -32,8 +32,6 @@ #include #include -u64 jiffies_64; - extern asmlinkage void syscall_trace(void); asmlinkage int sys_pipe(abi64_no_regargs, struct pt_regs regs) @@ -52,12 +50,71 @@ out: return res; } +unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */ + +#define COLOUR_ALIGN(addr,pgoff) \ + ((((addr) + shm_align_mask) & ~shm_align_mask) + \ + (((pgoff) << PAGE_SHIFT) & shm_align_mask)) + +unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, + unsigned long len, unsigned long pgoff, unsigned long flags) +{ + struct vm_area_struct * vmm; + int do_color_align; + + if (flags & MAP_FIXED) { + /* + * We do not accept a shared mapping if it would violate + * cache aliasing constraints. + */ + if ((flags & MAP_SHARED) && (addr & shm_align_mask)) + return -EINVAL; + return addr; + } + + if (len > TASK_SIZE) + return -ENOMEM; + do_color_align = 0; + if (filp || (flags & MAP_SHARED)) + do_color_align = 1; + if (addr) { + if (do_color_align) + addr = COLOUR_ALIGN(addr, pgoff); + else + addr = PAGE_ALIGN(addr); + vmm = find_vma(current->mm, addr); + if (TASK_SIZE - len >= addr && + (!vmm || addr + len <= vmm->vm_start)) + return addr; + } + addr = TASK_UNMAPPED_BASE; + if (do_color_align) + addr = COLOUR_ALIGN(addr, pgoff); + else + addr = PAGE_ALIGN(addr); + + for (vmm = find_vma(current->mm, addr); ; vmm = vmm->vm_next) { + /* At this point: (!vmm || addr < vmm->vm_end). */ + if (TASK_SIZE - len < addr) + return -ENOMEM; + if (!vmm || addr + len <= vmm->vm_start) + return addr; + addr = vmm->vm_end; + if (do_color_align) + addr = COLOUR_ALIGN(addr, pgoff); + } +} + asmlinkage unsigned long sys_mmap(unsigned long addr, size_t len, unsigned long prot, unsigned long flags, unsigned long fd, off_t offset) { struct file * file = NULL; - unsigned long error = -EFAULT; + unsigned long error; + + error = -EINVAL; + if (offset & ~PAGE_MASK) + goto out; if (!(flags & MAP_ANONYMOUS)) { error = -EBADF; @@ -72,33 +129,32 @@ sys_mmap(unsigned long addr, size_t len, up_write(¤t->mm->mmap_sem); if (file) fput(file); -out: +out: return error; } asmlinkage int sys_fork(abi64_no_regargs, struct pt_regs regs) { - struct task_struct *p; - save_static(®s); - p = do_fork(SIGCHLD, regs.regs[29], ®s, 0); - return IS_ERR(p) ? PTR_ERR(p) : p->pid; + return do_fork(SIGCHLD, regs.regs[29], ®s, 0, NULL, NULL); } asmlinkage int sys_clone(abi64_no_regargs, struct pt_regs regs) { unsigned long clone_flags; unsigned long newsp; - struct task_struct *p; + int *parent_tidptr, *child_tidptr; save_static(®s); clone_flags = regs.regs[4]; newsp = regs.regs[5]; if (!newsp) newsp = regs.regs[29]; - p = do_fork(clone_flags & ~CLONE_IDLETASK, newsp, ®s, 0); - return IS_ERR(p) ? PTR_ERR(p) : p->pid; + parent_tidptr = (int *) regs.regs[6]; + child_tidptr = (int *) regs.regs[7]; + return do_fork(clone_flags & ~CLONE_IDLETASK, newsp, ®s, 0, + parent_tidptr, child_tidptr); } /* @@ -131,12 +187,10 @@ asmlinkage int sys_syscall(abi64_no_rega return -ENOSYS; } -asmlinkage int -_sys_sysmips(int cmd, long arg1, int arg2, int arg3) +asmlinkage int sys_sysmips(int cmd, long arg1, int arg2, int arg3) { - int *p; + int tmp, len; char *name; - int tmp, len, errno; switch(cmd) { case SETNAME: { @@ -150,11 +204,12 @@ _sys_sysmips(int cmd, long arg1, int arg len = strncpy_from_user(nodename, name, __NEW_UTS_LEN); if (len < 0) return -EFAULT; - nodename[__NEW_UTS_LEN] = '\0'; down_write(&uts_sem); + strncpy(system_utsname.nodename, nodename, len); + nodename[__NEW_UTS_LEN] = '\0'; strlcpy(system_utsname.nodename, nodename, - sizeof(system_utsname.nodename)); + sizeof(system_utsname.nodename)); up_write(&uts_sem); return 0; } @@ -169,7 +224,7 @@ _sys_sysmips(int cmd, long arg1, int arg return 0; case FLUSH_CACHE: - _flush_cache_l2(); + __flush_cache_all(); return 0; case MIPS_RDNVRAM: @@ -207,7 +262,7 @@ asmlinkage int sys_ipc (uint call, int f } case MSGSND: - return sys_msgsnd (first, (struct msgbuf *) ptr, + return sys_msgsnd (first, (struct msgbuf *) ptr, second, third); case MSGRCV: switch (version) { @@ -215,9 +270,9 @@ asmlinkage int sys_ipc (uint call, int f struct ipc_kludge tmp; if (!ptr) return -EINVAL; - + if (copy_from_user(&tmp, - (struct ipc_kludge *) ptr, + (struct ipc_kludge *) ptr, sizeof (tmp))) return -EFAULT; return sys_msgrcv (first, tmp.msgp, second, @@ -247,7 +302,7 @@ asmlinkage int sys_ipc (uint call, int f return -EINVAL; return sys_shmat (first, (char *) ptr, second, (ulong *) third); } - case SHMDT: + case SHMDT: return sys_shmdt ((char *)ptr); case SHMGET: return sys_shmget (first, second, third); @@ -255,15 +310,14 @@ asmlinkage int sys_ipc (uint call, int f return sys_shmctl (first, second, (struct shmid_ds *) ptr); default: - return -EINVAL; + return -ENOSYS; } } /* * No implemented yet ... */ -asmlinkage int -sys_cachectl(char *addr, int nbytes, int op) +asmlinkage int sys_cachectl(char *addr, int nbytes, int op) { return -ENOSYS; } --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/kernel/time.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,602 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * Common time service routines for MIPS machines. See + * Documents/mips/README.txt. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* This is for machines which generate the exact clock. */ +#define USECS_PER_JIFFY (1000000/HZ) +#define USECS_PER_JIFFY_FRAC ((u32)((1000000ULL << 32) / HZ)) + +#define TICK_SIZE (tick_nsec / 1000) + +u64 jiffies_64; + +/* + * forward reference + */ +extern volatile unsigned long wall_jiffies; + +spinlock_t rtc_lock = SPIN_LOCK_UNLOCKED; + +/* + * whether we emulate local_timer_interrupts for SMP machines. + */ +int emulate_local_timer_interrupt; + +/* + * By default we provide the null RTC ops + */ +static unsigned long null_rtc_get_time(void) +{ + return mktime(2000, 1, 1, 0, 0, 0); +} + +static int null_rtc_set_time(unsigned long sec) +{ + return 0; +} + +unsigned long (*rtc_get_time)(void) = null_rtc_get_time; +int (*rtc_set_time)(unsigned long) = null_rtc_set_time; + + +/* + * This version of gettimeofday has microsecond resolution and better than + * microsecond precision on fast machines with cycle counter. + */ +void do_gettimeofday(struct timeval *tv) +{ + unsigned long seq; + unsigned long usec, sec; + + do { + seq = read_seqbegin(&xtime_lock); + usec = do_gettimeoffset(); + { + unsigned long lost = jiffies - wall_jiffies; + if (lost) + usec += lost * (1000000 / HZ); + } + sec = xtime.tv_sec; + usec += (xtime.tv_nsec / 1000); + } while (read_seqretry(&xtime_lock, seq)); + + while (usec >= 1000000) { + usec -= 1000000; + sec++; + } + + tv->tv_sec = sec; + tv->tv_usec = usec; +} + +int do_settimeofday(struct timespec *tv) +{ + if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC) + return -EINVAL; + + write_seqlock_irq(&xtime_lock); + /* + * This is revolting. We need to set "xtime" correctly. However, the + * value in this location is the value at the most recent update of + * wall time. Discover what correction gettimeofday() would have + * made, and then undo it! + */ + tv->tv_nsec -= do_gettimeoffset() * NSEC_PER_USEC; + tv->tv_nsec -= (jiffies - wall_jiffies) * TICK_NSEC; + + while (tv->tv_nsec < 0) { + tv->tv_nsec += NSEC_PER_SEC; + tv->tv_sec--; + } + + xtime.tv_sec = tv->tv_sec; + xtime.tv_nsec = tv->tv_nsec; + time_adjust = 0; /* stop active adjtime() */ + time_status |= STA_UNSYNC; + time_maxerror = NTP_PHASE_LIMIT; + time_esterror = NTP_PHASE_LIMIT; + write_sequnlock_irq(&xtime_lock); + + return 0; +} + + +/* + * Gettimeoffset routines. These routines returns the time duration + * since last timer interrupt in usecs. + * + * If the exact CPU counter frequency is known, use fixed_rate_gettimeoffset. + * Otherwise use calibrate_gettimeoffset() + * + * If the CPU does not have counter register all, you can either supply + * your own gettimeoffset() routine, or use null_gettimeoffset() routines, + * which gives the same resolution as HZ. + */ + + +/* This is for machines which generate the exact clock. */ +#define USECS_PER_JIFFY (1000000/HZ) + +/* usecs per counter cycle, shifted to left by 32 bits */ +static unsigned int sll32_usecs_per_cycle=0; + +/* how many counter cycles in a jiffy */ +static unsigned long cycles_per_jiffy=0; + +/* Cycle counter value at the previous timer interrupt.. */ +static unsigned int timerhi, timerlo; + +/* expirelo is the count value for next CPU timer interrupt */ +static unsigned int expirelo; + +/* last time when xtime and rtc are sync'ed up */ +static long last_rtc_update; + +/* the function pointer to one of the gettimeoffset funcs*/ +unsigned long (*do_gettimeoffset)(void) = null_gettimeoffset; + +unsigned long null_gettimeoffset(void) +{ + return 0; +} + +unsigned long fixed_rate_gettimeoffset(void) +{ + u32 count; + unsigned long res; + + /* Get last timer tick in absolute kernel time */ + count = read_c0_count(); + + /* .. relative to previous jiffy (32 bits is enough) */ + count -= timerlo; + + __asm__("multu\t%1,%2\n\t" + "mfhi\t%0" + :"=r" (res) + :"r" (count), + "r" (sll32_usecs_per_cycle)); + + /* + * Due to possible jiffies inconsistencies, we need to check + * the result so that we'll get a timer that is monotonic. + */ + if (res >= USECS_PER_JIFFY) + res = USECS_PER_JIFFY-1; + + return res; +} + +/* + * Cached "1/(clocks per usec)*2^32" value. + * It has to be recalculated once each jiffy. + */ +static unsigned long cached_quotient; + +/* Last jiffy when calibrate_divXX_gettimeoffset() was called. */ +static unsigned long last_jiffies = 0; + + +/* + * This is copied from dec/time.c:do_ioasic_gettimeoffset() by Mercij. + */ +unsigned long calibrate_div32_gettimeoffset(void) +{ + u32 count; + unsigned long res, tmp; + unsigned long quotient; + + tmp = jiffies; + + quotient = cached_quotient; + + if (last_jiffies != tmp) { + last_jiffies = tmp; + if (last_jiffies != 0) { + unsigned long r0; + do_div64_32(r0, timerhi, timerlo, tmp); + do_div64_32(quotient, USECS_PER_JIFFY, + USECS_PER_JIFFY_FRAC, r0); + cached_quotient = quotient; + } + } + + /* Get last timer tick in absolute kernel time */ + count = read_c0_count(); + + /* .. relative to previous jiffy (32 bits is enough) */ + count -= timerlo; + + __asm__("multu %2,%3" + : "=l" (tmp), "=h" (res) + : "r" (count), "r" (quotient)); + + /* + * Due to possible jiffies inconsistencies, we need to check + * the result so that we'll get a timer that is monotonic. + */ + if (res >= USECS_PER_JIFFY) + res = USECS_PER_JIFFY - 1; + + return res; +} + +unsigned long calibrate_div64_gettimeoffset(void) +{ + u32 count; + unsigned long res, tmp; + unsigned long quotient; + + tmp = jiffies; + + quotient = cached_quotient; + + if (tmp && last_jiffies != tmp) { + last_jiffies = tmp; + __asm__(".set\tnoreorder\n\t" + ".set\tnoat\n\t" + ".set\tmips3\n\t" + "lwu\t%0,%2\n\t" + "dsll32\t$1,%1,0\n\t" + "or\t$1,$1,%0\n\t" + "ddivu\t$0,$1,%3\n\t" + "mflo\t$1\n\t" + "dsll32\t%0,%4,0\n\t" + "nop\n\t" + "ddivu\t$0,%0,$1\n\t" + "mflo\t%0\n\t" + ".set\tmips0\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=&r" (quotient) + :"r" (timerhi), + "m" (timerlo), + "r" (tmp), + "r" (USECS_PER_JIFFY)); + cached_quotient = quotient; + } + + /* Get last timer tick in absolute kernel time */ + count = read_c0_count(); + + /* .. relative to previous jiffy (32 bits is enough) */ + count -= timerlo; + + __asm__("multu\t%1,%2\n\t" + "mfhi\t%0" + :"=r" (res) + :"r" (count), + "r" (quotient)); + + /* + * Due to possible jiffies inconsistencies, we need to check + * the result so that we'll get a timer that is monotonic. + */ + if (res >= USECS_PER_JIFFY) + res = USECS_PER_JIFFY-1; + + return res; +} + + +/* + * local_timer_interrupt() does profiling and process accounting + * on a per-CPU basis. + * + * In UP mode, it is invoked from the (global) timer_interrupt. + * + * In SMP mode, it might invoked by per-CPU timer interrupt, or + * a broadcasted inter-processor interrupt which itself is triggered + * by the global timer interrupt. + */ +void local_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + if (!user_mode(regs)) { + if (prof_buffer && current->pid) { + extern int _stext; + unsigned long pc = regs->cp0_epc; + + pc -= (unsigned long) &_stext; + pc >>= prof_shift; + /* + * Dont ignore out-of-bounds pc values silently, + * put them into the last histogram slot, so if + * present, they will show up as a sharp peak. + */ + if (pc > prof_len-1) + pc = prof_len-1; + atomic_inc((atomic_t *)&prof_buffer[pc]); + } + } + +#ifdef CONFIG_SMP + /* in UP mode, update_process_times() is invoked by do_timer() */ + update_process_times(user_mode(regs)); +#endif +} + +/* + * high-level timer interrupt service routines. This function + * is set as irqaction->handler and is invoked through do_IRQ. + */ +irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + if (cpu_has_counter) { + unsigned int count; + + /* ack timer interrupt, and try to set next interrupt */ + expirelo += cycles_per_jiffy; + write_c0_compare(expirelo); + count = read_c0_count(); + + /* check to see if we have missed any timer interrupts */ + if ((count - expirelo) < 0x7fffffff) { + /* missed_timer_count ++; */ + expirelo = count + cycles_per_jiffy; + write_c0_compare(expirelo); + } + + /* Update timerhi/timerlo for intra-jiffy calibration. */ + timerhi += count < timerlo; /* Wrap around */ + timerlo = count; + } + + /* + * call the generic timer interrupt handling + */ + do_timer(regs); + + /* + * If we have an externally synchronized Linux clock, then update + * CMOS clock accordingly every ~11 minutes. rtc_set_time() has to be + * called as close as possible to 500 ms before the new second starts. + */ + write_seqlock(&xtime_lock); + if ((time_status & STA_UNSYNC) == 0 && + xtime.tv_sec > last_rtc_update + 660 && + (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && + (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { + if (rtc_set_time(xtime.tv_sec) == 0) { + last_rtc_update = xtime.tv_sec; + } else { + last_rtc_update = xtime.tv_sec - 600; + /* do it again in 60 s */ + } + } + write_sequnlock(&xtime_lock); + + /* + * If jiffies has overflowed in this timer_interrupt we must + * update the timer[hi]/[lo] to make fast gettimeoffset funcs + * quotient calc still valid. -arca + */ + if (!jiffies) { + timerhi = timerlo = 0; + } + +#if !defined(CONFIG_SMP) + /* + * In UP mode, we call local_timer_interrupt() to do profiling + * and process accouting. + * + * In SMP mode, local_timer_interrupt() is invoked by appropriate + * low-level local timer interrupt handler. + */ + local_timer_interrupt(0, NULL, regs); + +#else /* CONFIG_SMP */ + + if (emulate_local_timer_interrupt) { + /* + * this is the place where we send out inter-process + * interrupts and let each CPU do its own profiling + * and process accouting. + * + * Obviously we need to call local_timer_interrupt() for + * the current CPU too. + */ + panic("Not implemented yet!!!"); + } +#endif /* CONFIG_SMP */ + + return IRQ_HANDLED; +} + +asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs) +{ + int cpu = smp_processor_id(); + + irq_enter(); + kstat_cpu(cpu).irqs[irq]++; + + /* we keep interrupt disabled all the time */ + timer_interrupt(irq, NULL, regs); + + irq_exit(); + + if (softirq_pending(cpu)) + do_softirq(); +} + +asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs) +{ + int cpu = smp_processor_id(); + + irq_enter(); + kstat_cpu(cpu).irqs[irq]++; + + /* we keep interrupt disabled all the time */ + local_timer_interrupt(irq, NULL, regs); + + irq_exit(); + + if (softirq_pending(cpu)) + do_softirq(); +} + +/* + * time_init() - it does the following things. + * + * 1) board_time_init() - + * a) (optional) set up RTC routines, + * b) (optional) calibrate and set the mips_counter_frequency + * (only needed if you intended to use fixed_rate_gettimeoffset + * or use cpu counter as timer interrupt source) + * 2) setup xtime based on rtc_get_time(). + * 3) choose a appropriate gettimeoffset routine. + * 4) calculate a couple of cached variables for later usage + * 5) board_timer_setup() - + * a) (optional) over-write any choices made above by time_init(). + * b) machine specific code should setup the timer irqaction. + * c) enable the timer interrupt + */ + +void (*board_time_init)(void) = NULL; +void (*board_timer_setup)(struct irqaction *irq) = NULL; + +unsigned int mips_counter_frequency = 0; + +static struct irqaction timer_irqaction = { + timer_interrupt, + SA_INTERRUPT, + 0, + "timer", + NULL, + NULL +}; + +void __init time_init(void) +{ + if (board_time_init) + board_time_init(); + + xtime.tv_sec = rtc_get_time(); + xtime.tv_nsec = 0; + + /* choose appropriate gettimeoffset routine */ + if (!cpu_has_counter) { + /* no cpu counter - sorry */ + do_gettimeoffset = null_gettimeoffset; + } else if (mips_counter_frequency != 0) { + /* we have cpu counter and know counter frequency! */ + do_gettimeoffset = fixed_rate_gettimeoffset; + } else if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32) || + (current_cpu_data.isa_level == MIPS_CPU_ISA_I) || + (current_cpu_data.isa_level == MIPS_CPU_ISA_II) ) { + /* we need to calibrate the counter but we don't have + * 64-bit division. */ + do_gettimeoffset = calibrate_div32_gettimeoffset; + } else { + /* we need to calibrate the counter but we *do* have + * 64-bit division. */ + do_gettimeoffset = calibrate_div64_gettimeoffset; + } + + /* caclulate cache parameters */ + if (mips_counter_frequency) { + cycles_per_jiffy = mips_counter_frequency / HZ; + + /* sll32_usecs_per_cycle = 10^6 * 2^32 / mips_counter_freq */ + /* any better way to do this? */ + sll32_usecs_per_cycle = mips_counter_frequency / 100000; + sll32_usecs_per_cycle = 0xffffffff / sll32_usecs_per_cycle; + sll32_usecs_per_cycle *= 10; + + /* + * For those using cpu counter as timer, this sets up the + * first interrupt + */ + write_c0_compare(cycles_per_jiffy); + write_c0_count(0); + expirelo = cycles_per_jiffy; + } + + /* + * Call board specific timer interrupt setup. + * + * this pointer must be setup in machine setup routine. + * + * Even if the machine choose to use low-level timer interrupt, + * it still needs to setup the timer_irqaction. + * In that case, it might be better to set timer_irqaction.handler + * to be NULL function so that we are sure the high-level code + * is not invoked accidentally. + */ + board_timer_setup(&timer_irqaction); +} + +#define FEBRUARY 2 +#define STARTOFTIME 1970 +#define SECDAY 86400L +#define SECYR (SECDAY * 365) +#define leapyear(year) ((year) % 4 == 0) +#define days_in_year(a) (leapyear(a) ? 366 : 365) +#define days_in_month(a) (month_days[(a) - 1]) + +static int month_days[12] = { + 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 +}; + +void to_tm(unsigned long tim, struct rtc_time * tm) +{ + long hms, day, gday; + int i; + + gday = day = tim / SECDAY; + hms = tim % SECDAY; + + /* Hours, minutes, seconds are easy */ + tm->tm_hour = hms / 3600; + tm->tm_min = (hms % 3600) / 60; + tm->tm_sec = (hms % 3600) % 60; + + /* Number of years in days */ + for (i = STARTOFTIME; day >= days_in_year(i); i++) + day -= days_in_year(i); + tm->tm_year = i; + + /* Number of months in days left */ + if (leapyear(tm->tm_year)) + days_in_month(FEBRUARY) = 29; + for (i = 1; day >= days_in_month(i); i++) + day -= days_in_month(i); + days_in_month(FEBRUARY) = 28; + tm->tm_mon = i-1; /* tm_mon starts from 0 to 11 */ + + /* Days are what is left over (+1) from all that. */ + tm->tm_mday = day + 1; + + /* + * Determine the day of week + */ + tm->tm_wday = (gday + 4) % 7; /* 1970/1/1 was Thursday */ +} + +EXPORT_SYMBOL(rtc_lock); --- linux-2.5.73/arch/mips64/kernel/traps.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/traps.c 2003-06-27 15:56:23.000000000 -0700 @@ -3,29 +3,39 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994 - 1999 by Ralf Baechle + * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle * Copyright (C) 1995, 1996 Paul M. Antoine * Copyright (C) 1998 Ulf Carlsson * Copyright (C) 1999 Silicon Graphics, Inc. + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000, 01 MIPS Technologies, Inc. + * Copyright (C) 2002, 2003 Maciej W. Rozycki */ #include #include #include +#include #include #include #include #include +#include +#include #include -#include +#include +#include +#include #include -#include -#include #include -#include +#include #include +#include +#include #include #include +#include +#include extern asmlinkage void __xtlb_mod(void); extern asmlinkage void __xtlb_tlbl(void); @@ -41,15 +51,16 @@ extern asmlinkage void handle_cpu(void); extern asmlinkage void handle_ov(void); extern asmlinkage void handle_tr(void); extern asmlinkage void handle_fpe(void); +extern asmlinkage void handle_mdmx(void); extern asmlinkage void handle_watch(void); +extern asmlinkage void handle_mcheck(void); extern asmlinkage void handle_reserved(void); -static char *cpu_names[] = CPU_NAMES; +extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, + struct mips_fpu_soft_struct *ctx); -char watch_available = 0; -char dedicated_iv_available = 0; -char vce_available = 0; -char mips4_available = 0; +void (*board_be_init)(void); +int (*board_be_handler)(struct pt_regs *regs, int is_fixup); /* * These constant is for searching for possible module text segments. @@ -61,84 +72,70 @@ char mips4_available = 0; * This routine abuses get_user()/put_user() to reference pointers * with at least a bit of error checking ... */ -void show_stack(unsigned long *sp) +void show_stack(struct task_struct *task, unsigned long *sp) { + const int field = 2 * sizeof(unsigned long); + long stackdata; int i; - unsigned long *stack; - - stack = sp; - i = 0; - printk("Stack:"); - while ((unsigned long) stack & (PAGE_SIZE - 1)) { - unsigned long stackdata; + sp = sp ? sp : (unsigned long *) &sp; - if (__get_user(stackdata, stack++)) { - printk(" (Bad stack address)"); + printk("Stack: "); + i = 1; + while ((unsigned long) sp & (PAGE_SIZE - 1)) { + if (i && ((i % (64 / sizeof(unsigned long))) == 0)) + printk("\n "); + if (i > 40) { + printk(" ..."); break; } - printk(" %016lx", stackdata); - - if (++i > 40) { - printk(" ..."); + if (__get_user(stackdata, sp++)) { + printk(" (Bad stack address)"); break; } - if (i % 4 == 0) - printk("\n "); + printk(" %0*lx", field, stackdata); + i++; } + printk("\n"); } -void show_trace(unsigned long *sp) +void show_trace(struct task_struct *task, unsigned long *stack) { - int i; - unsigned long *stack; - unsigned long kernel_start, kernel_end; - unsigned long module_start, module_end; - extern char _stext, _etext; - - stack = sp; - i = 0; - - kernel_start = (unsigned long) &_stext; - kernel_end = (unsigned long) &_etext; - module_start = VMALLOC_START; - module_end = module_start + MODULE_RANGE; - - printk("\nCall Trace:"); + const int field = 2 * sizeof(unsigned long); + unsigned long addr; - while ((unsigned long) stack & (PAGE_SIZE -1)) { - unsigned long addr; + if (!stack) + stack = (unsigned long*)&stack; - if (__get_user(addr, stack++)) { - printk(" (Bad stack address)\n"); - break; + printk("Call Trace:"); +#ifdef CONFIG_KALLSYMS + printk("\n"); +#endif + while (((long) stack & (THREAD_SIZE-1)) != 0) { + addr = *stack++; + if (kernel_text_address(addr)) { + printk(" [<%0*lx>] ", field, addr); + print_symbol("%s\n", addr); } + } + printk("\n"); +} - /* - * If the address is either in the text segment of the - * kernel, or in the region which contains vmalloc'ed - * memory, it *may* be the address of a calling - * routine; if so, print it so that someone tracing - * down the cause of the crash will be able to figure - * out the call path that was taken. - */ +void show_trace_task(struct task_struct *tsk) +{ + show_trace(tsk, (long *)tsk->thread.reg29); +} - if ((addr >= kernel_start && addr < kernel_end) || - (addr >= module_start && addr < module_end)) { +/* + * The architecture-independent dump_stack generator + */ +void dump_stack(void) +{ + unsigned long stack; - /* Since our kernel is still at KSEG0, - * truncate the address so that ksymoops - * understands it. - */ - printk(" [<%08x>]", (unsigned int) addr); - if (++i > 40) { - printk(" ..."); - break; - } - } - } + show_trace(current, &stack); } void show_code(unsigned int *pc) @@ -153,120 +150,369 @@ void show_code(unsigned int *pc) printk(" (Bad address in epc)\n"); break; } - printk("%c%08x%c",(i?' ':'<'),insn,(i?' ':'>')); + printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); + } +} + +void show_regs(struct pt_regs *regs) +{ + const int field = 2 * sizeof(unsigned long); + int i; + + printk("Cpu %d\n", smp_processor_id()); + + /* + * Saved main processor registers + */ + for (i = 0; i < 32; i++) { + if ((i % 4) == 0) + printk("$%2d :", i); + if (i == 0) + printk(" %0*lx", field, 0UL); + else if (i == 26 || i == 27) + printk(" %*s", field, ""); + else + printk(" %0*lx", field, regs->regs[i]); + + i++; + if ((i % 4) == 0) + printk("\n"); } + + printk("Hi : %0*lx\n", field, regs->hi); + printk("Lo : %0*lx\n", field, regs->lo); + + /* + * Saved cp0 registers + */ + printk("epc : %0*lx %s\n", field, regs->cp0_epc, print_tainted()); + printk("Status: %0*lx\n", field, regs->cp0_status); + printk("Cause : %0*lx\n", field, regs->cp0_cause); + + if (regs->cp0_status & ST0_KX) + printk("KX "); + if (regs->cp0_status & ST0_SX) + printk("SX "); + if (regs->cp0_status & ST0_UX) + printk("UX "); + switch (regs->cp0_status & ST0_KSU) { + case KSU_USER: + printk("USER "); + break; + case KSU_SUPERVISOR: + printk("SUPERVISOR "); + break; + case KSU_KERNEL: + printk("KERNEL "); + break; + default: + printk("BAD_MODE "); + break; + } + if (regs->cp0_status & ST0_ERL) + printk("ERL "); + if (regs->cp0_status & ST0_EXL) + printk("EXL "); + if (regs->cp0_status & ST0_IE) + printk("IE "); } -spinlock_t die_lock; +void show_registers(struct pt_regs *regs) +{ + const int field = 2 * sizeof(unsigned long); -void die(const char * str, struct pt_regs * regs, unsigned long err) + show_regs(regs); + printk("Process %s (pid: %d, stackpage=%0*lx)\n", + current->comm, current->pid, field, (unsigned long) current); + show_stack(current, (long *) regs->regs[29]); + show_trace(current, (long *) regs->regs[29]); + show_code((unsigned int *) regs->cp0_epc); + printk("\n"); +} + +static spinlock_t die_lock = SPIN_LOCK_UNLOCKED; + +void __die(const char * str, struct pt_regs * regs, const char * file, + const char * func, unsigned long line) { static int die_counter; - if (user_mode(regs)) /* Just return if in user mode. */ - return; console_verbose(); spin_lock_irq(&die_lock); - printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter); - show_regs(regs); - printk("Process %s (pid: %d, stackpage=%08lx)\n", - current->comm, current->pid, (unsigned long) current); - show_stack((unsigned long *) regs->regs[29]); - show_trace((unsigned long *) regs->regs[29]); - show_code((unsigned int *) regs->cp0_epc); - printk("\n"); + printk("%s", str); + if (file && func) + printk(" in %s:%s, line %ld", file, func, line); + printk("[#%d]:\n", ++die_counter); + show_registers(regs); spin_unlock_irq(&die_lock); do_exit(SIGSEGV); } -void die_if_kernel(const char * str, struct pt_regs * regs, unsigned long err) +void __die_if_kernel(const char * str, struct pt_regs * regs, + const char * file, const char * func, unsigned long line) { if (!user_mode(regs)) - die(str, regs, err); + __die(str, regs, file, func, line); +} + +extern const struct exception_table_entry __start___dbe_table[]; +extern const struct exception_table_entry __stop___dbe_table[]; + +void __declare_dbe_table(void) +{ + __asm__ __volatile__( + ".section\t__dbe_table,\"a\"\n\t" + ".previous" + ); } -void do_ov(struct pt_regs *regs) +asmlinkage void do_be(struct pt_regs *regs) { - if (compute_return_epc(regs)) + const int field = 2 * sizeof(unsigned long); + const struct exception_table_entry *fixup = NULL; + int data = regs->cp0_cause & 4; + int action = MIPS_BE_FATAL; + + /* XXX For now. Fixme, this searches the wrong table ... */ + if (data && !user_mode(regs)) + fixup = search_exception_tables(regs->cp0_epc); + + if (fixup) + action = MIPS_BE_FIXUP; + + if (board_be_handler) + action = board_be_handler(regs, fixup != 0); + + switch (action) { + case MIPS_BE_DISCARD: return; - force_sig(SIGFPE, current); + case MIPS_BE_FIXUP: + if (fixup) { + regs->cp0_epc = fixup->nextinsn; + return; + } + break; + default: + break; + } + + /* + * Assume it would be too dangerous to continue ... + */ + printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", + data ? "Data" : "Instruction", + field, regs->cp0_epc, field, regs->regs[31]); + die_if_kernel("Oops", regs); + force_sig(SIGBUS, current); } -#ifdef CONFIG_MIPS_FPE_MODULE -static void (*fpe_handler)(struct pt_regs *regs, unsigned int fcr31); +static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode) +{ + unsigned int *epc; + + epc = (unsigned int *) regs->cp0_epc + + ((regs->cp0_cause & CAUSEF_BD) != 0); + if (!get_user(*opcode, epc)) + return 0; + + force_sig(SIGSEGV, current); + return 1; +} + +/* + * ll/sc emulation + */ + +#define OPCODE 0xfc000000 +#define BASE 0x03e00000 +#define RT 0x001f0000 +#define OFFSET 0x0000ffff +#define LL 0xc0000000 +#define SC 0xe0000000 /* - * Register_fpe/unregister_fpe are for debugging purposes only. To make - * this hack work a bit better there is no error checking. + * The ll_bit is cleared by r*_switch.S */ -int register_fpe(void (*handler)(struct pt_regs *regs, unsigned int fcr31)) + +unsigned long ll_bit; + +static struct task_struct *ll_task = NULL; + +static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) { - fpe_handler = handler; - return 0; + unsigned long value, *vaddr; + long offset; + int signal = 0; + + /* + * analyse the ll instruction that just caused a ri exception + * and put the referenced address to addr. + */ + + /* sign extend offset */ + offset = opcode & OFFSET; + offset <<= 16; + offset >>= 16; + + vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset); + + if ((unsigned long)vaddr & 3) { + signal = SIGBUS; + goto sig; + } + if (get_user(value, vaddr)) { + signal = SIGSEGV; + goto sig; + } + + if (ll_task == NULL || ll_task == current) { + ll_bit = 1; + } else { + ll_bit = 0; + } + ll_task = current; + + regs->regs[(opcode & RT) >> 16] = value; + + compute_return_epc(regs); + return; + +sig: + force_sig(signal, current); } -int unregister_fpe(void (*handler)(struct pt_regs *regs, unsigned int fcr31)) +static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) { - fpe_handler = NULL; - return 0; + unsigned long *vaddr, reg; + long offset; + int signal = 0; + + /* + * analyse the sc instruction that just caused a ri exception + * and put the referenced address to addr. + */ + + /* sign extend offset */ + offset = opcode & OFFSET; + offset <<= 16; + offset >>= 16; + + vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset); + reg = (opcode & RT) >> 16; + + if ((unsigned long)vaddr & 3) { + signal = SIGBUS; + goto sig; + } + if (ll_bit == 0 || ll_task != current) { + regs->regs[reg] = 0; + compute_return_epc(regs); + return; + } + + if (put_user(regs->regs[reg], vaddr)) { + signal = SIGSEGV; + goto sig; + } + + regs->regs[reg] = 1; + + compute_return_epc(regs); + return; + +sig: + force_sig(signal, current); } -#endif /* - * XXX Delayed fp exceptions when doing a lazy ctx switch XXX + * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both + * opcodes are supposed to result in coprocessor unusable exceptions if + * executed on ll/sc-less processors. That's the theory. In practice a + * few processors such as NEC's VR4100 throw reserved instruction exceptions + * instead, so we're doing the emulation thing in both exception handlers. */ -void do_fpe(struct pt_regs *regs, unsigned long fcr31) +static inline int simulate_llsc(struct pt_regs *regs) { - unsigned long pc; - unsigned int insn; - extern void simfp(unsigned int); - -#ifdef CONFIG_MIPS_FPE_MODULE - if (fpe_handler != NULL) { - fpe_handler(regs, fcr31); - return; - } -#endif - if (fcr31 & 0x20000) { - /* Retry instruction with flush to zero ... */ - if (!(fcr31 & (1<<24))) { - printk("Setting flush to zero for %s.\n", - current->comm); - fcr31 &= ~0x20000; - fcr31 |= (1<<24); - __asm__ __volatile__( - "ctc1\t%0,$31" - : /* No outputs */ - : "r" (fcr31)); - return; - } - pc = regs->cp0_epc + ((regs->cp0_cause & CAUSEF_BD) ? 4 : 0); - if (get_user(insn, (unsigned int *)pc)) { - /* XXX Can this happen? */ - force_sig(SIGSEGV, current); - } + unsigned int opcode; - printk(KERN_DEBUG "Unimplemented exception for insn %08x at 0x%08lx in %s.\n", - insn, regs->cp0_epc, current->comm); - simfp(insn); + if (unlikely(get_insn_opcode(regs, &opcode))) + return -EFAULT; + + if ((opcode & OPCODE) == LL) { + simulate_ll(regs, opcode); + return 0; + } + if ((opcode & OPCODE) == SC) { + simulate_sc(regs, opcode); + return 0; } - if (compute_return_epc(regs)) + return -EFAULT; /* Strange things going on ... */ +} + +asmlinkage void do_ov(struct pt_regs *regs) +{ + siginfo_t info; + + info.si_code = FPE_INTOVF; + info.si_signo = SIGFPE; + info.si_errno = 0; + info.si_addr = (void *)regs->cp0_epc; + force_sig_info(SIGFPE, &info, current); +} + +/* + * XXX Delayed fp exceptions when doing a lazy ctx switch XXX + */ +asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) +{ + if (fcr31 & FPU_CSR_UNI_X) { + int sig; + + /* + * Unimplemented operation exception. If we've got the full + * software emulator on-board, let's use it... + * + * Force FPU to dump state into task/thread context. We're + * moving a lot of data here for what is probably a single + * instruction, but the alternative is to pre-decode the FP + * register operands before invoking the emulator, which seems + * a bit extreme for what should be an infrequent event. + */ + save_fp(current); + + /* Run the emulator */ + sig = fpu_emulator_cop1Handler (0, regs, + ¤t->thread.fpu.soft); + + /* + * We can't allow the emulated instruction to leave any of + * the cause bit set in $fcr31. + */ + current->thread.fpu.soft.sr &= ~FPU_CSR_ALL_X; + + /* Restore the hardware register state */ + restore_fp(current); + + /* If something went wrong, signal */ + if (sig) + force_sig(sig, current); + return; - //force_sig(SIGFPE, current); - printk(KERN_DEBUG "Should send SIGFPE to %s\n", current->comm); + } + + force_sig(SIGFPE, current); } -void do_bp(struct pt_regs *regs) +asmlinkage void do_bp(struct pt_regs *regs) { unsigned int opcode, bcode; - unsigned int *epc; siginfo_t info; - epc = (unsigned int *) regs->cp0_epc + - ((regs->cp0_cause & CAUSEF_BD) != 0); - if (get_user(opcode, epc)) - goto sigsegv; + die_if_kernel("Break instruction in kernel code", regs); + + if (get_insn_opcode(regs, &opcode)) + return; /* * There is the ancient bug in the MIPS assemblers that the break @@ -290,160 +536,243 @@ void do_bp(struct pt_regs *regs) info.si_code = FPE_INTOVF; info.si_signo = SIGFPE; info.si_errno = 0; - info.si_addr = (void *)compute_return_epc(regs); + info.si_addr = (void *)regs->cp0_epc; force_sig_info(SIGFPE, &info, current); break; default: force_sig(SIGTRAP, current); } - - force_sig(SIGTRAP, current); - return; - -sigsegv: - force_sig(SIGSEGV, current); } -void do_tr(struct pt_regs *regs) +asmlinkage void do_tr(struct pt_regs *regs) { - unsigned int opcode, bcode; - unsigned int *epc; + unsigned int opcode, tcode = 0; siginfo_t info; - epc = (unsigned int *) regs->cp0_epc + - ((regs->cp0_cause & CAUSEF_BD) != 0); - if (get_user(opcode, epc)) - goto sigsegv; + die_if_kernel("Trap instruction in kernel code", regs); - bcode = ((opcode >> 6) & ((1 << 20) - 1)); + if (get_insn_opcode(regs, &opcode)) + return; + + /* Immediate versions don't provide a code. */ + if (!(opcode & OPCODE)) + tcode = ((opcode >> 6) & ((1 << 20) - 1)); /* - * (A short test says that IRIX 5.3 sends SIGTRAP for all break - * insns, even for break codes that indicate arithmetic failures. - * Wiered ...) + * (A short test says that IRIX 5.3 sends SIGTRAP for all trap + * insns, even for trap codes that indicate arithmetic failures. + * Weird ...) * But should we continue the brokenness??? --macro */ - switch (bcode) { + switch (tcode) { case 6: case 7: - if (bcode == 7) + if (tcode == 7) info.si_code = FPE_INTDIV; else info.si_code = FPE_INTOVF; info.si_signo = SIGFPE; info.si_errno = 0; - info.si_addr = (void *)compute_return_epc(regs); + info.si_addr = (void *)regs->cp0_epc; force_sig_info(SIGFPE, &info, current); break; default: force_sig(SIGTRAP, current); } - return; - -sigsegv: - force_sig(SIGSEGV, current); } -void do_ri(struct pt_regs *regs) +asmlinkage void do_ri(struct pt_regs *regs) { - printk("Cpu%d[%s:%d] Illegal instruction at %08lx ra=%08lx\n", - smp_processor_id(), current->comm, current->pid, regs->cp0_epc, - regs->regs[31]); - if (compute_return_epc(regs)) - return; + die_if_kernel("Reserved instruction in kernel code", regs); + + if (!cpu_has_llsc) + if (!simulate_llsc(regs)) + return; + force_sig(SIGILL, current); } -void do_cpu(struct pt_regs *regs) +asmlinkage void do_cpu(struct pt_regs *regs) { - u32 cpid; + unsigned int cpid; + + die_if_kernel("do_cpu invoked from kernel context!", regs); cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; - if (cpid != 1) - goto bad_cid; - regs->cp0_status |= ST0_CU1; -#ifndef CONFIG_SMP - if (last_task_used_math == current) + switch (cpid) { + case 0: + if (cpu_has_llsc) + break; + + if (!simulate_llsc(regs)) + return; + break; + + case 1: + own_fpu(); + if (current->used_math) { /* Using the FPU again. */ + restore_fp(current); + } else { /* First time FPU user. */ + init_fpu(); + current->used_math = 1; + } + + if (!cpu_has_fpu) { + int sig = fpu_emulator_cop1Handler(0, regs, + ¤t->thread.fpu.soft); + if (sig) + force_sig(sig, current); + } + return; - if (current->used_math) { /* Using the FPU again. */ - lazy_fpu_switch(last_task_used_math, current); - } else { /* First time FPU user. */ - lazy_fpu_switch(last_task_used_math, 0); - init_fpu(); - current->used_math = 1; - } - last_task_used_math = current; -#else - if (current->used_math) { - lazy_fpu_switch(0, current); - } else { - init_fpu(); - current->used_math = 1; + case 2: + case 3: + break; } - current->flags |= PF_USEDFPU; -#endif - return; -bad_cid: force_sig(SIGILL, current); } -void do_watch(struct pt_regs *regs) +asmlinkage void do_mdmx(struct pt_regs *regs) +{ + force_sig(SIGILL, current); +} + +asmlinkage void do_watch(struct pt_regs *regs) { /* * We use the watch exception where available to detect stack * overflows. */ + dump_tlb_all(); show_regs(regs); panic("Caught WATCH exception - probably caused by stack overflow."); } -void do_reserved(struct pt_regs *regs) +asmlinkage void do_mcheck(struct pt_regs *regs) +{ + show_regs(regs); + dump_tlb_all(); + /* + * Some chips may have other causes of machine check (e.g. SB1 + * graduation timer) + */ + panic("Caught Machine Check exception - %scaused by multiple " + "matching entries in the TLB.", + (regs->cp0_status & ST0_TS) ? "" : "not "); +} + +asmlinkage void do_reserved(struct pt_regs *regs) { /* * Game over - no way to handle this if it ever occurs. Most probably * caused by a new unknown cpu type or after another deadly * hard/software error. */ + show_regs(regs); panic("Caught reserved exception %ld - should not happen.", - (regs->cp0_cause & 0x1f) >> 2); + (regs->cp0_cause & 0x7f) >> 2); } -static inline void watch_init(unsigned long cputype) +/* + * Some MIPS CPUs can enable/disable for cache parity detection, but do + * it different ways. + */ +static inline void parity_protection_init(void) { - switch(cputype) { - case CPU_R10000: - case CPU_R4000MC: - case CPU_R4400MC: - case CPU_R4000SC: - case CPU_R4400SC: - case CPU_R4000PC: - case CPU_R4400PC: - case CPU_R4200: - case CPU_R4300: - set_except_vector(23, handle_watch); - watch_available = 1; + switch (current_cpu_data.cputype) { + case CPU_5KC: + /* Set the PE bit (bit 31) in the c0_ecc register. */ + printk(KERN_INFO "Enable the cache parity protection for " + "MIPS 5KC CPUs.\n"); + write_c0_ecc(read_c0_ecc() | 0x80000000); + break; + default: break; } } +asmlinkage void cache_parity_error(void) +{ + const int field = 2 * sizeof(unsigned long); + unsigned int reg_val; + + /* For the moment, report the problem and hang. */ + printk("Cache error exception:\n"); + printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); + reg_val = read_c0_cacheerr(); + printk("c0_cacheerr == %08x\n", reg_val); + + printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", + reg_val & (1<<30) ? "secondary" : "primary", + reg_val & (1<<31) ? "data" : "insn"); + printk("Error bits: %s%s%s%s%s%s%s\n", + reg_val & (1<<29) ? "ED " : "", + reg_val & (1<<28) ? "ET " : "", + reg_val & (1<<26) ? "EE " : "", + reg_val & (1<<25) ? "EB " : "", + reg_val & (1<<24) ? "EI " : "", + reg_val & (1<<23) ? "E1 " : "", + reg_val & (1<<22) ? "E0 " : ""); + printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); + +#if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64) + if (reg_val & (1<<22)) + printk("DErrAddr0: 0x%08x\n", read_c0_derraddr0()); + + if (reg_val & (1<<23)) + printk("DErrAddr1: 0x%08x\n", read_c0_derraddr1()); +#endif + + panic("Can't handle the cache error!"); +} + /* - * Some MIPS CPUs have a dedicated interrupt vector which reduces the - * interrupt processing overhead. Use it where available. - * FIXME: more CPUs than just the Nevada have this feature. + * SDBBP EJTAG debug exception handler. + * We skip the instruction and return to the next instruction. */ -static inline void setup_dedicated_int(void) +void ejtag_exception_handler(struct pt_regs *regs) { - extern void except_vec4(void); + const int field = 2 * sizeof(unsigned long); + unsigned long depc, old_epc; + unsigned int debug; + + printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); + depc = read_c0_depc(); + debug = read_c0_debug(); + printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); + if (debug & 0x80000000) { + /* + * In branch delay slot. + * We cheat a little bit here and use EPC to calculate the + * debug return address (DEPC). EPC is restored after the + * calculation. + */ + old_epc = regs->cp0_epc; + regs->cp0_epc = depc; + __compute_return_epc(regs); + depc = regs->cp0_epc; + regs->cp0_epc = old_epc; + } else + depc += 4; + write_c0_depc(depc); + +#if 0 + printk("\n\n----- Enable EJTAG single stepping ----\n\n"); + write_c0_debug(debug | 0x100); +#endif +} - switch(mips_cputype) { - case CPU_NEVADA: - memcpy((void *)(KSEG0 + 0x200), except_vec4, 8); - set_cp0_cause(CAUSEF_IV, CAUSEF_IV); - dedicated_iv_available = 1; - } +/* + * NMI exception handler. + */ +void nmi_exception_handler(struct pt_regs *regs) +{ + printk("NMI taken!!!!\n"); + die("NMI", regs); + while(1) ; } unsigned long exception_handlers[32]; @@ -453,139 +782,160 @@ unsigned long exception_handlers[32]; * to interrupt handlers in the address range from * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... */ -void set_except_vector(int n, void *addr) +void *set_except_vector(int n, void *addr) { unsigned long handler = (unsigned long) addr; + unsigned long old_handler = exception_handlers[n]; + exception_handlers[n] = handler; - if (n == 0 && dedicated_iv_available) { + if (n == 0 && cpu_has_divec) { *(volatile u32 *)(KSEG0+0x200) = 0x08000000 | (0x03ffffff & (handler >> 2)); flush_icache_range(KSEG0+0x200, KSEG0 + 0x204); } + return (void *)old_handler; } -static inline void mips4_setup(void) -{ - switch (mips_cputype) { - case CPU_R5000: - case CPU_R5000A: - case CPU_NEVADA: - case CPU_R8000: - case CPU_R10000: - mips4_available = 1; - set_cp0_status(ST0_XX, ST0_XX); - } -} +asmlinkage int (*save_fp_context)(struct sigcontext *sc); +asmlinkage int (*restore_fp_context)(struct sigcontext *sc); + +extern asmlinkage int _save_fp_context(struct sigcontext *sc); +extern asmlinkage int _restore_fp_context(struct sigcontext *sc); -static inline void go_64(void) +extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc); +extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc); + +void __init per_cpu_trap_init(void) { - unsigned int bits; + unsigned int cpu = smp_processor_id(); + + /* Some firmware leaves the BEV flag set, clear it. */ + clear_c0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_BEV); + set_c0_status(ST0_CU0|ST0_FR|ST0_KX|ST0_SX|ST0_UX); + + /* + * Some MIPS CPUs have a dedicated interrupt vector which reduces the + * interrupt processing overhead. Use it where available. + */ + if (cpu_has_divec) + set_c0_cause(CAUSEF_IV); - bits = ST0_KX|ST0_SX|ST0_UX; - set_cp0_status(bits, bits); - printk("Entering 64-bit mode.\n"); + cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; + write_c0_context(((long)(&pgd_current[cpu])) << 23); + write_c0_wired(0); } void __init trap_init(void) { - extern char except_vec0; - extern char except_vec1_r10k; - extern char except_vec2_generic; + extern char except_vec0_generic; extern char except_vec3_generic, except_vec3_r4000; - extern void bus_error_init(void); + extern char except_vec_ejtag_debug; + extern char except_vec4; unsigned long i; - /* Some firmware leaves the BEV flag set, clear it. */ - set_cp0_status(ST0_BEV, 0); + per_cpu_trap_init(); - /* Copy the generic exception handler code to its final destination. */ - memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80); + /* Copy the generic exception handlers to their final destination. */ + memcpy((void *) KSEG0 , &except_vec0_generic, 0x80); memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80); /* * Setup default vectors */ - for(i = 0; i <= 31; i++) + for (i = 0; i <= 31; i++) set_except_vector(i, handle_reserved); /* + * Copy the EJTAG debug exception vector handler code to it's final + * destination. + */ + if (cpu_has_ejtag) + memcpy((void *)(KSEG0 + 0x300), &except_vec_ejtag_debug, 0x80); + + /* * Only some CPUs have the watch exceptions or a dedicated * interrupt vector. */ - watch_init(mips_cputype); - setup_dedicated_int(); - mips4_setup(); - go_64(); /* In memoriam C128 ;-) */ + if (cpu_has_watch) + set_except_vector(23, handle_watch); /* - * Handling the following exceptions depends mostly of the cpu type + * Some MIPS CPUs have a dedicated interrupt vector which reduces the + * interrupt processing overhead. Use it where available. */ - switch(mips_cputype) { - case CPU_R10000: - /* - * The R10000 is in most aspects similar to the R4400. It - * should get some special optimizations. - */ - write_32bit_cp0_register(CP0_FRAMEMASK, 0); - set_cp0_status(ST0_XX, ST0_XX); - goto r4k; - - case CPU_R4000MC: - case CPU_R4400MC: - case CPU_R4000SC: - case CPU_R4400SC: - vce_available = 1; - /* Fall through ... */ - case CPU_R4000PC: - case CPU_R4400PC: - case CPU_R4200: - case CPU_R4300: - case CPU_R4600: - case CPU_R5000: - case CPU_NEVADA: -r4k: - /* Debug TLB refill handler. */ - memcpy((void *)KSEG0, &except_vec0, 0x80); - memcpy((void *)KSEG0 + 0x080, &except_vec1_r10k, 0x80); - - /* Cache error vector */ - memcpy((void *)(KSEG0 + 0x100), (void *) KSEG0, 0x80); - - if (vce_available) { - memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, - 0x180); - } else { - memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, - 0x100); - } + if (cpu_has_divec) + memcpy((void *)(KSEG0 + 0x200), &except_vec4, 0x8); + + /* + * Some CPUs can enable/disable for cache parity detection, but does + * it different ways. + */ + parity_protection_init(); + + /* + * The Data Bus Errors / Instruction Bus Errors are signaled + * by external hardware. Therefore these two exceptions + * may have board specific handlers. + */ + if (board_be_init) + board_be_init(); - set_except_vector(1, __xtlb_mod); - set_except_vector(2, __xtlb_tlbl); - set_except_vector(3, __xtlb_tlbs); - set_except_vector(4, handle_adel); - set_except_vector(5, handle_ades); - - /* DBE / IBE exception handler are system specific. */ - bus_error_init(); - - set_except_vector(8, handle_sys); - set_except_vector(9, handle_bp); - set_except_vector(10, handle_ri); - set_except_vector(11, handle_cpu); - set_except_vector(12, handle_ov); - set_except_vector(13, handle_tr); + set_except_vector(1, __xtlb_mod); + set_except_vector(2, __xtlb_tlbl); + set_except_vector(3, __xtlb_tlbs); + set_except_vector(4, handle_adel); + set_except_vector(5, handle_ades); + + set_except_vector(6, handle_ibe); + set_except_vector(7, handle_dbe); + + set_except_vector(8, handle_sys); + set_except_vector(9, handle_bp); + set_except_vector(10, handle_ri); + set_except_vector(11, handle_cpu); + set_except_vector(12, handle_ov); + set_except_vector(13, handle_tr); + set_except_vector(22, handle_mdmx); + + if (cpu_has_fpu && !cpu_has_nofpuex) set_except_vector(15, handle_fpe); - break; - case CPU_R8000: - panic("unsupported CPU type %s.\n", cpu_names[mips_cputype]); - break; + if (cpu_has_mcheck) + set_except_vector(24, handle_mcheck); - case CPU_UNKNOWN: - default: - panic("Unknown CPU type"); + if (cpu_has_vce) + memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x100); + else if (cpu_has_4kex) + memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80); + else + memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80); + + if (current_cpu_data.cputype == CPU_R6000 || + current_cpu_data.cputype == CPU_R6000A) { + /* + * The R6000 is the only R-series CPU that features a machine + * check exception (similar to the R4000 cache error) and + * unaligned ldc1/sdc1 exception. The handlers have not been + * written yet. Well, anyway there is no R6000 machine on the + * current list of targets for Linux/MIPS. + * (Duh, crap, there is someone with a tripple R6k machine) + */ + //set_except_vector(14, handle_mc); + //set_except_vector(15, handle_ndc); + } + + if (cpu_has_fpu) { + save_fp_context = _save_fp_context; + restore_fp_context = _restore_fp_context; + } else { + save_fp_context = fpu_emulator_save_context; + restore_fp_context = fpu_emulator_restore_context; } - flush_icache_range(KSEG0, KSEG0 + 0x200); + + flush_icache_range(KSEG0, KSEG0 + 0x400); + + if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) + set_c0_status(ST0_XX); atomic_inc(&init_mm.mm_count); /* XXX UP? */ current->active_mm = &init_mm; --- linux-2.5.73/arch/mips64/kernel/unaligned.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/kernel/unaligned.c 2003-06-27 15:56:23.000000000 -0700 @@ -5,7 +5,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 1998, 1999 by Ralf Baechle + * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. * * This file contains exception handler for address error exception with the @@ -41,7 +41,7 @@ * * #include * #include - * + * * struct foo { * unsigned char bar[8]; * }; @@ -74,6 +74,7 @@ */ #include #include +#include #include #include #include @@ -88,23 +89,22 @@ #define STR(x) __STR(x) #define __STR(x) #x -/* - * User code may only access USEG; kernel code may access the - * entire address space. - */ -#define check_axs(pc,a,s) \ - if ((long)(~(pc) & ((a) | ((a)+(s)))) < 0) \ - goto sigbus; +#ifdef CONFIG_PROC_FS +unsigned long unaligned_instructions; +#endif -static inline void -emulate_load_store_insn(struct pt_regs *regs, - unsigned long addr, - unsigned long pc) +static inline int emulate_load_store_insn(struct pt_regs *regs, + void *addr, unsigned long pc, + unsigned long **regptr, unsigned long *newvalue) { union mips_instruction insn; - unsigned long value, fixup; + unsigned long value; + const struct exception_table_entry *fixup; + unsigned int res; regs->regs[0] = 0; + *regptr=NULL; + /* * This load never faults. */ @@ -144,186 +144,295 @@ emulate_load_store_insn(struct pt_regs * * The remaining opcodes are the ones that are really of interest. */ case lh_op: - check_axs(pc, addr, 2); - __asm__( - ".set\tnoat\n" + if (verify_area(VERIFY_READ, addr, 2)) + goto sigbus; + + __asm__ __volatile__ (".set\tnoat\n" #ifdef __BIG_ENDIAN - "1:\tlb\t%0,0(%1)\n" - "2:\tlbu\t$1,1(%1)\n\t" + "1:\tlb\t%0, 0(%2)\n" + "2:\tlbu\t$1, 1(%2)\n\t" #endif #ifdef __LITTLE_ENDIAN - "1:\tlb\t%0,1(%1)\n" - "2:\tlbu\t$1,0(%1)\n\t" + "1:\tlb\t%0, 1(%2)\n" + "2:\tlbu\t$1, 0(%2)\n\t" #endif - "sll\t%0,0x8\n\t" - "or\t%0,$1\n\t" - ".set\tat\n\t" + "sll\t%0, 0x8\n\t" + "or\t%0, $1\n\t" + "li\t%1, 0\n" + "3:\t.set\tat\n\t" + ".section\t.fixup,\"ax\"\n\t" + "4:\tli\t%1, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - :"=&r" (value) - :"r" (addr), "i" (&&fault) - :"$1"); - regs->regs[insn.i_format.rt] = value; - return; + : "=&r" (value), "=r" (res) + : "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + *newvalue = value; + *regptr = ®s->regs[insn.i_format.rt]; + break; case lw_op: - check_axs(pc, addr, 4); - __asm__( + if (verify_area(VERIFY_READ, addr, 4)) + goto sigbus; + + __asm__ __volatile__ ( #ifdef __BIG_ENDIAN - "1:\tlwl\t%0,(%1)\n" - "2:\tlwr\t%0,3(%1)\n\t" + "1:\tlwl\t%0, (%2)\n" + "2:\tlwr\t%0, 3(%2)\n\t" #endif #ifdef __LITTLE_ENDIAN - "1:\tlwl\t%0,3(%1)\n" - "2:\tlwr\t%0,(%1)\n\t" + "1:\tlwl\t%0, 3(%2)\n" + "2:\tlwr\t%0, (%2)\n\t" #endif + "li\t%1, 0\n" + "3:\t.section\t.fixup,\"ax\"\n\t" + "4:\tli\t%1, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - :"=&r" (value) - :"r" (addr), "i" (&&fault)); - regs->regs[insn.i_format.rt] = value; - return; + : "=&r" (value), "=r" (res) + : "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + *newvalue = value; + *regptr = ®s->regs[insn.i_format.rt]; + break; case lhu_op: - check_axs(pc, addr, 2); - __asm__( + if (verify_area(VERIFY_READ, addr, 2)) + goto sigbus; + + __asm__ __volatile__ ( ".set\tnoat\n" #ifdef __BIG_ENDIAN - "1:\tlbu\t%0,0(%1)\n" - "2:\tlbu\t$1,1(%1)\n\t" + "1:\tlbu\t%0, 0(%2)\n" + "2:\tlbu\t$1, 1(%2)\n\t" #endif #ifdef __LITTLE_ENDIAN - "1:\tlbu\t%0,1(%1)\n" - "2:\tlbu\t$1,0(%1)\n\t" + "1:\tlbu\t%0, 1(%2)\n" + "2:\tlbu\t$1, 0(%2)\n\t" #endif - "sll\t%0,0x8\n\t" - "or\t%0,$1\n\t" - ".set\tat\n\t" + "sll\t%0, 0x8\n\t" + "or\t%0, $1\n\t" + "li\t%1, 0\n" + "3:\t.set\tat\n\t" + ".section\t.fixup,\"ax\"\n\t" + "4:\tli\t%1, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - :"=&r" (value) - :"r" (addr), "i" (&&fault) - :"$1"); - regs->regs[insn.i_format.rt] = value; - return; + : "=&r" (value), "=r" (res) + : "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + *newvalue = value; + *regptr = ®s->regs[insn.i_format.rt]; + break; case lwu_op: - check_axs(pc, addr, 4); - __asm__( +#ifdef CONFIG_MIPS64 + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (verify_area(VERIFY_READ, addr, 4)) + goto sigbus; + + __asm__ __volatile__ ( #ifdef __BIG_ENDIAN - "1:\tlwl\t%0,(%1)\n" - "2:\tlwr\t%0,3(%1)\n\t" + "1:\tlwl\t%0, (%2)\n" + "2:\tlwr\t%0, 3(%2)\n\t" #endif #ifdef __LITTLE_ENDIAN - "1:\tlwl\t%0,3(%1)\n" - "2:\tlwr\t%0,(%1)\n\t" + "1:\tlwl\t%0, 3(%2)\n" + "2:\tlwr\t%0, (%2)\n\t" #endif + "dsll\t%0, %0, 32\n\t" + "dsrl\t%0, %0, 32\n\t" + "li\t%1, 0\n" + "3:\t.section\t.fixup,\"ax\"\n\t" + "4:\tli\t%1, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - :"=&r" (value) - :"r" (addr), "i" (&&fault)); - value &= 0xffffffff; - regs->regs[insn.i_format.rt] = value; - return; + : "=&r" (value), "=r" (res) + : "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + *newvalue = value; + *regptr = ®s->regs[insn.i_format.rt]; + break; +#endif /* CONFIG_MIPS64 */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; case ld_op: - check_axs(pc, addr, 8); - __asm__( - ".set\tmips3\n" +#ifdef CONFIG_MIPS64 + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (verify_area(VERIFY_READ, addr, 8)) + goto sigbus; + + __asm__ __volatile__ ( #ifdef __BIG_ENDIAN - "1:\tldl\t%0,(%1)\n" - "2:\tldr\t%0,7(%1)\n\t" + "1:\tldl\t%0, (%2)\n" + "2:\tldr\t%0, 7(%2)\n\t" #endif #ifdef __LITTLE_ENDIAN - "1:\tldl\t%0,7(%1)\n" - "2:\tldr\t%0,(%1)\n\t" + "1:\tldl\t%0, 7(%2)\n" + "2:\tldr\t%0, (%2)\n\t" #endif - ".set\tmips0\n\t" + "li\t%1, 0\n" + "3:\t.section\t.fixup,\"ax\"\n\t" + "4:\tli\t%1, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - :"=&r" (value) - :"r" (addr), "i" (&&fault)); - regs->regs[insn.i_format.rt] = value; - return; + : "=&r" (value), "=r" (res) + : "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + *newvalue = value; + *regptr = ®s->regs[insn.i_format.rt]; + break; +#endif /* CONFIG_MIPS64 */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; case sh_op: - check_axs(pc, addr, 2); + if (verify_area(VERIFY_WRITE, addr, 2)) + goto sigbus; + value = regs->regs[insn.i_format.rt]; - __asm__( + __asm__ __volatile__ ( #ifdef __BIG_ENDIAN ".set\tnoat\n" - "1:\tsb\t%0,1(%1)\n\t" - "srl\t$1,%0,0x8\n" - "2:\tsb\t$1,0(%1)\n\t" + "1:\tsb\t%1, 1(%2)\n\t" + "srl\t$1, %1, 0x8\n" + "2:\tsb\t$1, 0(%2)\n\t" ".set\tat\n\t" #endif #ifdef __LITTLE_ENDIAN ".set\tnoat\n" - "1:\tsb\t%0,0(%1)\n\t" - "srl\t$1,%0,0x8\n" - "2:\tsb\t$1,1(%1)\n\t" + "1:\tsb\t%1, 0(%2)\n\t" + "srl\t$1,%1, 0x8\n" + "2:\tsb\t$1, 1(%2)\n\t" ".set\tat\n\t" #endif + "li\t%0, 0\n" + "3:\n\t" + ".section\t.fixup,\"ax\"\n\t" + "4:\tli\t%0, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - : /* no outputs */ - :"r" (value), "r" (addr), "i" (&&fault) - :"$1"); - return; + : "=r" (res) + : "r" (value), "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + break; case sw_op: - check_axs(pc, addr, 4); + if (verify_area(VERIFY_WRITE, addr, 4)) + goto sigbus; + value = regs->regs[insn.i_format.rt]; - __asm__( + __asm__ __volatile__ ( #ifdef __BIG_ENDIAN - "1:\tswl\t%0,(%1)\n" - "2:\tswr\t%0,3(%1)\n\t" + "1:\tswl\t%1,(%2)\n" + "2:\tswr\t%1, 3(%2)\n\t" #endif #ifdef __LITTLE_ENDIAN - "1:\tswl\t%0,3(%1)\n" - "2:\tswr\t%0,(%1)\n\t" + "1:\tswl\t%1, 3(%2)\n" + "2:\tswr\t%1, (%2)\n\t" #endif + "li\t%0, 0\n" + "3:\n\t" + ".section\t.fixup,\"ax\"\n\t" + "4:\tli\t%0, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - : /* no outputs */ - :"r" (value), "r" (addr), "i" (&&fault)); - return; + : "=r" (res) + : "r" (value), "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + break; case sd_op: - check_axs(pc, addr, 8); +#ifdef CONFIG_MIPS64 + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (verify_area(VERIFY_WRITE, addr, 8)) + goto sigbus; + value = regs->regs[insn.i_format.rt]; - __asm__( - ".set\tmips3\n" + __asm__ __volatile__ ( #ifdef __BIG_ENDIAN - "1:\tsdl\t%0,(%1)\n" - "2:\tsdr\t%0,7(%1)\n\t" + "1:\tsdl\t%1,(%2)\n" + "2:\tsdr\t%1, 7(%2)\n\t" #endif #ifdef __LITTLE_ENDIAN - "1:\tsdl\t%0,7(%1)\n" - "2:\tsdr\t%0,(%1)\n\t" + "1:\tsdl\t%1, 7(%2)\n" + "2:\tsdr\t%1, (%2)\n\t" #endif - ".set\tmips0\n\t" + "li\t%0, 0\n" + "3:\n\t" + ".section\t.fixup,\"ax\"\n\t" + "4:\tli\t%0, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - : /* no outputs */ - :"r" (value), "r" (addr), "i" (&&fault)); - return; + : "=r" (res) + : "r" (value), "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + break; +#endif /* CONFIG_MIPS64 */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; case lwc1_op: case ldc1_op: @@ -352,63 +461,97 @@ emulate_load_store_insn(struct pt_regs * */ goto sigill; } - return; + +#ifdef CONFIG_PROC_FS + unaligned_instructions++; +#endif + + return 0; fault: /* Did we have an exception handler installed? */ - fixup = search_exception_table(regs->cp0_epc); + fixup = search_exception_tables(exception_epc(regs)); if (fixup) { - long new_epc; - new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc); + unsigned long new_epc = fixup->nextinsn; printk(KERN_DEBUG "%s: Forwarding exception at [<%lx>] (%lx)\n", current->comm, regs->cp0_epc, new_epc); regs->cp0_epc = new_epc; - return; + return 1; } die_if_kernel ("Unhandled kernel unaligned access", regs); send_sig(SIGSEGV, current, 1); - return; + + return 0; + sigbus: - die_if_kernel ("Unhandled kernel unaligned access", regs); + die_if_kernel("Unhandled kernel unaligned access", regs); send_sig(SIGBUS, current, 1); - return; + + return 0; + sigill: - die_if_kernel ("Unhandled kernel unaligned access or invalid instruction", regs); + die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs); send_sig(SIGILL, current, 1); - return; -} -#ifdef CONFIG_PROC_FS -unsigned long unaligned_instructions; -#endif + return 0; +} asmlinkage void do_ade(struct pt_regs *regs) { + unsigned long *regptr, newval; + extern int do_dsemulret(struct pt_regs *); + mm_segment_t seg; unsigned long pc; /* + * Address errors may be deliberately induced by the FPU emulator to + * retake control of the CPU after executing the instruction in the + * delay slot of an emulated branch. + */ + /* Terminate if exception was recognized as a delay slot return */ + if (do_dsemulret(regs)) + return; + + /* Otherwise handle as normal */ + + /* * Did we catch a fault trying to load an instruction? - * This also catches attempts to activate MIPS16 code on - * CPUs which don't support it. + * Or are we running in MIPS16 mode? */ - if (regs->cp0_badvaddr == regs->cp0_epc) + if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1)) goto sigbus; - pc = regs->cp0_epc + ((regs->cp0_cause & CAUSEF_BD) ? 4 : 0); - if (compute_return_epc(regs)) - return; + pc = exception_epc(regs); if ((current->thread.mflags & MF_FIXADE) == 0) goto sigbus; - emulate_load_store_insn(regs, regs->cp0_badvaddr, pc); -#ifdef CONFIG_PROC_FS - unaligned_instructions++; -#endif + /* + * Do branch emulation only if we didn't forward the exception. + * This is all so but ugly ... + */ + seg = get_fs(); + if (!user_mode(regs)) + set_fs(KERNEL_DS); + if (!emulate_load_store_insn(regs, (void *)regs->cp0_badvaddr, pc, + ®ptr, &newval)) { + compute_return_epc(regs); + /* + * Now that branch is evaluated, update the dest + * register if necessary + */ + if (regptr) + *regptr = newval; + } + set_fs(seg); return; sigbus: - die_if_kernel ("Kernel unaligned instruction access", regs); + die_if_kernel("Kernel unaligned instruction access", regs); force_sig(SIGBUS, current); + + /* + * XXX On return from the signal handler we should advance the epc + */ } --- linux-2.5.73/arch/mips64/ld.script.elf64 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,143 +0,0 @@ -OUTPUT_ARCH(mips) -ENTRY(kernel_entry) -jiffies = jiffies_64; -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - /* . = 0xc000000000000000; */ - - /* This is the value for an Origin kernel, taken from an IRIX kernel. */ - /* . = 0xc00000000001c000; */ - - /* Set the vaddr for the text segment to a value - >= 0xa800 0000 0001 9000 if no symmon is going to configured - >= 0xa800 0000 0030 0000 otherwise */ - - /* . = 0xa800000000300000; */ - /* . = 0xa800000000300000; */ - . = 0xffffffff80300000; - .text : { - *(.text) - *(.rodata) - *(.rodata.*) - *(.rodata1) - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - } = 0 - .kstrtab : { *(.kstrtab) } - __vermagic : { *(__vermagic) } - - . = ALIGN(16); /* Exception table */ - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - __start___dbe_table = .; /* Exception table for data bus errors */ - __dbe_table : { *(__dbe_table) } - __stop___dbe_table = .; - - _etext = .; - - . = ALIGN(16384); - .data.init_task : { *(.data.init_task) } - - /* Startup code */ - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(16); - __setup_start = .; - .setup.init : { *(.setup.init) } - __setup_end = .; - __initcall_start = .; - .initcall.init : { - *(.initcall1.init) - *(.initcall2.init) - *(.initcall3.init) - *(.initcall4.init) - *(.initcall5.init) - *(.initcall6.init) - *(.initcall7.init) - } - __initcall_end = .; - . = ALIGN(4096); /* Align double page for init_task_union */ - __init_end = .; - - . = ALIGN(4096); - .data.page_aligned : { *(.data.idt) } - - . = ALIGN(32); - .data.cacheline_aligned : { *(.data.cacheline_aligned) } - - .fini : { *(.fini) } =0 - .reginfo : { *(.reginfo) } - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. It would - be more correct to do this: - . = .; - The current expression does not correctly handle the case of a - text segment ending precisely at the end of a page; it causes the - data segment to skip a page. The above expression does not have - this problem, but it will currently (2/95) cause BFD to allocate - a single segment, combining both text and data, for this case. - This will prevent the text segment from being shared among - multiple executions of the program; I think that is more - important than losing a page of the virtual address space (note - that no actual memory is lost; the page which is skipped can not - be referenced). */ - . = .; - .data : - { - _fdata = . ; - *(.data) - CONSTRUCTORS - } - .data1 : { *(.data1) } - .lit8 : { *(.lit8) } - .lit4 : { *(.lit4) } - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - .got : { *(.got.plt) *(.got) } - .dynamic : { *(.dynamic) } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata : { *(.sdata) } - _edata = .; - - .sbss : { *(.sbss) *(.scommon) } - .bss : - { - *(.dynbss) - *(.bss) - *(COMMON) - _end = . ; - } - - /* Sections to be discarded */ - /DISCARD/ : - { - *(.text.exit) - *(.data.exit) - *(.exitcall.exit) - } - - /* These are needed for ELF backends which have not yet been - converted to the new style linker. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - /* DWARF debug sections. - Symbols in the .debug DWARF section are relative to the beginning of the - section so we begin .debug at 0. It's not clear yet what needs to happen - for the others. */ - .debug 0 : { *(.debug) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .line 0 : { *(.line) } - /* These must appear regardless of . */ - .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } - .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } -} --- linux-2.5.73/arch/mips64/lib/csum_partial_copy.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/lib/csum_partial_copy.c 2003-06-27 15:56:23.000000000 -0700 @@ -16,8 +16,8 @@ /* * copy while checksumming, otherwise like csum_partial */ -unsigned int csum_partial_copy_nocheck(const char *src, char *dst, - int len, unsigned int sum) +unsigned int csum_partial_copy_nocheck(const char *src, char *dst, + int len, unsigned int sum) { /* * It's 2:30 am and I don't feel like doing it real ... @@ -44,6 +44,6 @@ unsigned int csum_partial_copy_from_user memset(dst + len - missing, 0, missing); *err_ptr = -EFAULT; } - + return csum_partial(dst, len, sum); } --- linux-2.5.73/arch/mips64/lib/dump_tlb.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/lib/dump_tlb.c 2003-06-27 15:56:23.000000000 -0700 @@ -11,34 +11,47 @@ #include #include +#include #include #include #include -#define mips_tlb_entries 64 +static inline const char *msk2str(unsigned int mask) +{ + switch (mask) { + case PM_4K: return "4kb"; + case PM_16K: return "16kb"; + case PM_64K: return "64kb"; + case PM_256K: return "256kb"; + case PM_1M: return "1Mb"; + case PM_4M: return "4Mb"; + case PM_16M: return "16Mb"; + case PM_64M: return "64Mb"; + case PM_256M: return "256Mb"; + } +} -void -dump_tlb(int first, int last) +void dump_tlb(int first, int last) { unsigned long s_entryhi, entryhi, entrylo0, entrylo1, asid; unsigned int s_index, pagemask, c0, c1, i; - s_entryhi = get_entryhi(); - s_index = get_index(); + s_entryhi = read_c0_entryhi(); + s_index = read_c0_index(); asid = s_entryhi & 0xff; for (i = first; i <= last; i++) { - write_32bit_cp0_register(CP0_INDEX, i); + write_c0_index(i); __asm__ __volatile__( ".set\tnoreorder\n\t" "nop;nop;nop;nop\n\t" "tlbr\n\t" "nop;nop;nop;nop\n\t" ".set\treorder"); - pagemask = read_32bit_cp0_register(CP0_PAGEMASK); - entryhi = get_entryhi(); - entrylo0 = get_entrylo0(); - entrylo1 = get_entrylo1(); + pagemask = read_c0_pagemask(); + entryhi = read_c0_entryhi(); + entrylo0 = read_c0_entrylo0(); + entrylo1 = read_c0_entrylo1(); /* Unused entries have a virtual address of CKSEG0. */ if ((entryhi & ~0x1ffffUL) != CKSEG0 @@ -46,47 +59,44 @@ dump_tlb(int first, int last) /* * Only print entries in use */ - printk("Index: %2d pgmask=%08x ", i, pagemask); + printk("Index: %2d pgmask=%s ", i, msk2str(pagemask)); c0 = (entrylo0 >> 3) & 7; c1 = (entrylo1 >> 3) & 7; - printk("va=%08lx asid=%02lx" - " [pa=%06lx c=%d d=%d v=%d g=%ld]" - " [pa=%06lx c=%d d=%d v=%d g=%ld]\n", + printk("va=%011lx asid=%02lx\n", (entryhi & ~0x1fffUL), - entryhi & 0xff, - entrylo0 & PAGE_MASK, c0, + entryhi & 0xff); + printk("\t[pa=%011lx c=%d d=%d v=%d g=%ld] ", + (entrylo0 << 6) & PAGE_MASK, c0, (entrylo0 & 4) ? 1 : 0, (entrylo0 & 2) ? 1 : 0, - (entrylo0 & 1), - entrylo1 & PAGE_MASK, c1, + (entrylo0 & 1)); + printk("[pa=%011lx c=%d d=%d v=%d g=%ld]\n", + (entrylo1 << 6) & PAGE_MASK, c1, (entrylo1 & 4) ? 1 : 0, (entrylo1 & 2) ? 1 : 0, (entrylo1 & 1)); - } } printk("\n"); - set_entryhi(s_entryhi); - set_index(s_index); + write_c0_entryhi(s_entryhi); + write_c0_index(s_index); } -void -dump_tlb_all(void) +void dump_tlb_all(void) { - dump_tlb(0, mips_tlb_entries - 1); + dump_tlb(0, current_cpu_data.tlbsize - 1); } -void -dump_tlb_wired(void) +void dump_tlb_wired(void) { int wired; - wired = read_32bit_cp0_register(CP0_WIRED); + wired = read_c0_wired(); printk("Wired: %d", wired); - dump_tlb(0, read_32bit_cp0_register(CP0_WIRED)); + dump_tlb(0, read_c0_wired()); } #define BARRIER \ @@ -95,21 +105,20 @@ dump_tlb_wired(void) "nop;nop;nop;nop;nop;nop;nop\n\t" \ ".set\treorder"); -void -dump_tlb_addr(unsigned long addr) +void dump_tlb_addr(unsigned long addr) { unsigned int flags, oldpid; int index; local_irq_save(flags); - oldpid = get_entryhi() & 0xff; + oldpid = read_c0_entryhi() & 0xff; BARRIER; - set_entryhi((addr & PAGE_MASK) | oldpid); + write_c0_entryhi((addr & PAGE_MASK) | oldpid); BARRIER; tlb_probe(); BARRIER; - index = get_index(); - set_entryhi(oldpid); + index = read_c0_index(); + write_c0_entryhi(oldpid); local_irq_restore(flags); if (index < 0) { @@ -121,14 +130,12 @@ dump_tlb_addr(unsigned long addr) dump_tlb(index, index); } -void -dump_tlb_nonwired(void) +void dump_tlb_nonwired(void) { - dump_tlb(read_32bit_cp0_register(CP0_WIRED), mips_tlb_entries - 1); + dump_tlb(read_c0_wired(), current_cpu_data.tlbsize - 1); } -void -dump_list_process(struct task_struct *t, void *address) +void dump_list_process(struct task_struct *t, void *address) { pgd_t *page_dir, *pgd; pmd_t *pmd; @@ -154,7 +161,7 @@ dump_list_process(struct task_struct *t, printk("pte == %08lx, ", (unsigned long) pte); page = *pte; - printk("page == %08lx\n", (unsigned long) pte_val(page)); + printk("page == %08lx\n", pte_val(page)); val = pte_val(page); if (val & _PAGE_PRESENT) printk("present "); @@ -194,8 +201,7 @@ void dump16(unsigned long *p) { int i; - for(i=0;i<8;i++) - { + for(i = 0; i < 8; i++) { printk("*%08lx == %08lx, ", (unsigned long)p, (unsigned long)*p); p++; --- linux-2.5.73/arch/mips64/lib/floppy-std.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/lib/floppy-std.c 2003-06-27 15:56:23.000000000 -0700 @@ -15,11 +15,11 @@ #include #include #include + #include #include #include #include -#include #include #include #include @@ -100,23 +100,9 @@ static unsigned long std_fd_getfdaddr1(v return 0x3f0; } -/* Pure 2^n version of get_order */ -static int __get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - static unsigned long std_fd_dma_mem_alloc(unsigned long size) { - int order = __get_order(size); + int order = get_order(size); unsigned long mem; mem = __get_dma_pages(GFP_KERNEL,order); @@ -125,8 +111,8 @@ static unsigned long std_fd_dma_mem_allo } static void std_fd_dma_mem_free(unsigned long addr, unsigned long size) -{ - free_pages(addr, __get_order(size)); +{ + free_pages(addr, get_order(size)); } static unsigned long std_fd_drive_type(unsigned long n) --- linux-2.5.73/arch/mips64/lib/ide-no.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/lib/ide-no.c 2003-06-27 15:56:23.000000000 -0700 @@ -12,7 +12,6 @@ #include #include #include -#include static int no_ide_default_irq(ide_ioreg_t base) { --- linux-2.5.73/arch/mips64/lib/ide-std.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/lib/ide-std.c 2003-06-27 15:56:23.000000000 -0700 @@ -11,7 +11,6 @@ #include #include #include -#include #include static int std_ide_default_irq(ide_ioreg_t base) @@ -30,16 +29,11 @@ static int std_ide_default_irq(ide_ioreg static ide_ioreg_t std_ide_default_io_base(int index) { - switch (index) { - case 0: return 0x1f0; - case 1: return 0x170; - case 2: return 0x1e8; - case 3: return 0x168; - case 4: return 0x1e0; - case 5: return 0x160; - default: - return 0; - } + static unsigned long ata_io_base[MAX_HWIFS] = { + 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 + }; + + return ata_io_base[index]; } static void std_ide_init_hwif_ports (hw_regs_t *hw, ide_ioreg_t data_port, --- linux-2.5.73/arch/mips64/lib/kbd-no.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,62 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Stub keyboard and psaux routines to keep Linux from crashing on machines - * without a keyboard. - * - * Copyright (C) 1998 by Ralf Baechle - */ -#include -#include - -static void no_kbd_request_region(void) -{ - /* No I/O ports are being used on the Indy. */ -} - -static int no_kbd_request_irq(void (*handler)(int, void *, struct pt_regs *)) -{ - return -ENODEV; -} - -static int no_aux_request_irq(void (*handler)(int, void *, struct pt_regs *)) -{ - return -ENODEV; -} - -static void no_aux_free_irq(void) -{ -} - -static unsigned char no_kbd_read_input(void) -{ - return 0; -} - -static void no_kbd_write_output(unsigned char val) -{ -} - -static void no_kbd_write_command(unsigned char val) -{ -} - -static unsigned char no_kbd_read_status(void) -{ - return 0; -} - -struct kbd_ops no_kbd_ops = { - no_kbd_request_region, - no_kbd_request_irq, - - no_aux_request_irq, - no_aux_free_irq, - - no_kbd_read_input, - no_kbd_write_output, - no_kbd_write_command, - no_kbd_read_status -}; --- linux-2.5.73/arch/mips64/lib/kbd-std.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,80 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Routines for standard PC style keyboards accessible via I/O ports. - * - * Copyright (C) 1998, 1999 by Ralf Baechle - */ -#include -#include -#include -#include -#include - -#define KEYBOARD_IRQ 1 -#define AUX_IRQ 12 - -static void std_kbd_request_region(void) -{ - request_region(0x60, 16, "keyboard"); -} - -static int std_kbd_request_irq(void (*handler)(int, void *, struct pt_regs *)) -{ - return request_irq(KEYBOARD_IRQ, handler, 0, "keyboard", NULL); -} - -static int std_aux_request_irq(void (*handler)(int, void *, struct pt_regs *)) -{ - return request_irq(AUX_IRQ, handler, 0, "PS/2 Mouse", NULL); -} - -static void std_aux_free_irq(void) -{ - free_irq(AUX_IRQ, NULL); -} - -static unsigned char std_kbd_read_input(void) -{ - return inb(KBD_DATA_REG); -} - -static void std_kbd_write_output(unsigned char val) -{ - int status; - - do { - status = inb(KBD_CNTL_REG); - } while (status & KBD_STAT_IBF); - outb(val, KBD_DATA_REG); -} - -static void std_kbd_write_command(unsigned char val) -{ - int status; - - do { - status = inb(KBD_CNTL_REG); - } while (status & KBD_STAT_IBF); - outb(val, KBD_CNTL_REG); -} - -static unsigned char std_kbd_read_status(void) -{ - return inb(KBD_STATUS_REG); -} - -struct kbd_ops std_kbd_ops = { - std_kbd_request_region, - std_kbd_request_irq, - - std_aux_request_irq, - std_aux_free_irq, - - std_kbd_read_input, - std_kbd_write_output, - std_kbd_write_command, - std_kbd_read_status -}; --- linux-2.5.73/arch/mips64/lib/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/lib/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -2,9 +2,17 @@ # Makefile for MIPS-specific library files.. # -EXTRA_AFLAGS := $(CFLAGS) +lib-y += csum_partial.o csum_partial_copy.o memcpy.o \ + memset.o promlib.o rtc-std.o rtc-no.o strlen_user.o \ + strncpy_user.o strnlen_user.o watch.o + +ifeq ($(CONFIG_CPU_R3000)$(CONFIG_CPU_TX39XX),y) + lib-y += r3k_dump_tlb.o +else + lib-y += dump_tlb.o +endif -lib-y += csum_partial.o csum_partial_copy.o dump_tlb.o floppy-std.o \ - floppy-no.o ide-std.o ide-no.o kbd-std.o kbd-no.o rtc-std.o \ - rtc-no.o memset.o memcpy.o strlen_user.o strncpy_user.o \ - strnlen_user.o watch.o +lib-$(CONFIG_BLK_DEV_FD) += floppy-no.o floppy-std.o +lib-$(subst m,y,$(CONFIG_IDE)) += ide-std.o ide-no.o # needed for ide module + +EXTRA_AFLAGS := $(CFLAGS) --- linux-2.5.73/arch/mips64/lib/memcpy.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/lib/memcpy.S 2003-06-27 15:56:23.000000000 -0700 @@ -5,766 +5,502 @@ * * Unified implementation of memcpy, memmove and the __copy_user backend. * - * Copyright (C) 1998, 1999, 2000, 2001 Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 1998, 99, 2000, 01, 2002 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc. + * Copyright (C) 2002 Broadcom, Inc. + * memcpy/copy_user author: Mark Vandevoorde * - * For __rmemcpy and memmove an exception is always a kernel bug, therefore - * they're not protected. In order to keep the exception fixup routine - * simple all memory accesses in __copy_user to src rsp. dst are stricly - * incremental. The fixup routine depends on $at not being changed. + * Mnemonic names for arguments to memcpy/__copy_user */ +#include #include #include #include +#define dst a0 +#define src a1 +#define len a2 + /* - * The fixup routine for copy_to_user depends on copying strictly in - * increasing order. Gas expands the ulw/usw macros in the wrong order for - * little endian machines, so we cannot depend on them. + * Spec + * + * memcpy copies len bytes from src to dst and sets v0 to dst. + * It assumes that + * - src and dst don't overlap + * - src is readable + * - dst is writable + * memcpy uses the standard calling convention + * + * __copy_user copies up to len bytes from src to dst and sets a2 (len) to + * the number of uncopied bytes due to an exception caused by a read or write. + * __copy_user assumes that src and dst don't overlap, and that the call is + * implementing one of the following: + * copy_to_user + * - src is readable (no exceptions when reading src) + * copy_from_user + * - dst is writable (no exceptions when writing dst) + * __copy_user uses a non-standard calling convention; see + * include/asm-mips/uaccess.h + * + * When an exception happens on a load, the handler must + # ensure that all of the destination buffer is overwritten to prevent + * leaking information to user mode programs. */ -#ifdef __MIPSEB__ -#define uswL swl -#define uswU swr -#define ulwL lwl -#define ulwU lwr -#define usdL sdl -#define usdU sdr -#define uldL ldl -#define uldU ldr -#endif -#ifdef __MIPSEL__ -#define uswL swr -#define uswU swl -#define ulwL lwr -#define ulwU lwl -#define usdL sdr -#define usdU sdl -#define uldL ldr -#define uldU ldl -#endif -#define EX(insn,reg,addr,handler) \ -9: insn reg, addr; \ - .section __ex_table,"a"; \ - PTR 9b, handler; \ - .previous +/* + * Implementation + */ -#define UEX(insn,reg,addr,handler) \ -9: insn ## L reg, addr; \ -10: insn ## U reg, 3 + addr; \ - .section __ex_table,"a"; \ - PTR 9b, handler; \ - PTR 10b, handler; \ - .previous +/* + * The exception handler for loads requires that: + * 1- AT contain the address of the byte just past the end of the source + * of the copy, + * 2- src_entry <= src < AT, and + * 3- (dst - src) == (dst_entry - src_entry), + * The _entry suffix denotes values when __copy_user was called. + * + * (1) is set up up by uaccess.h and maintained by not writing AT in copy_user + * (2) is met by incrementing src by the number of bytes copied + * (3) is met by not doing loads between a pair of increments of dst and src + * + * The exception handlers for stores adjust len (if necessary) and return. + * These handlers do not need to overwrite any data. + * + * For __rmemcpy and memmove an exception is always a kernel bug, therefore + * they're not protected. + */ -#define UEXD(insn,reg,addr,handler) \ -9: insn ## L reg, addr; \ -10: insn ## U reg, 7 + addr; \ - .section __ex_table,"a"; \ - PTR 9b, handler; \ - PTR 10b, handler; \ +#define EXC(inst_reg,addr,handler) \ +9: inst_reg, addr; \ + .section __ex_table,"a"; \ + PTR 9b, handler; \ .previous -/* ascending order, destination aligned */ -#define MOVE_BIGGERCHUNK(src, dst, offset, t0, t1, t2, t3) \ - EX(ld, t0, (offset + 0x00)(src), l_fixup); \ - EX(ld, t1, (offset + 0x08)(src), l_fixup); \ - EX(ld, t2, (offset + 0x10)(src), l_fixup); \ - EX(ld, t3, (offset + 0x18)(src), l_fixup); \ - EX(sd, t0, (offset + 0x00)(dst), s_fixup); \ - EX(sd, t1, (offset + 0x08)(dst), s_fixup); \ - EX(sd, t2, (offset + 0x10)(dst), s_fixup); \ - EX(sd, t3, (offset + 0x18)(dst), s_fixup); \ - EX(ld, t0, (offset + 0x20)(src), l_fixup); \ - EX(ld, t1, (offset + 0x28)(src), l_fixup); \ - EX(ld, t2, (offset + 0x30)(src), l_fixup); \ - EX(ld, t3, (offset + 0x38)(src), l_fixup); \ - EX(sd, t0, (offset + 0x20)(dst), s_fixup); \ - EX(sd, t1, (offset + 0x28)(dst), s_fixup); \ - EX(sd, t2, (offset + 0x30)(dst), s_fixup); \ - EX(sd, t3, (offset + 0x38)(dst), s_fixup) - -/* ascending order, destination aligned */ -#define MOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3) \ - EX(lw, t0, (offset + 0x00)(src), l_fixup); \ - EX(lw, t1, (offset + 0x04)(src), l_fixup); \ - EX(lw, t2, (offset + 0x08)(src), l_fixup); \ - EX(lw, t3, (offset + 0x0c)(src), l_fixup); \ - EX(sw, t0, (offset + 0x00)(dst), s_fixup); \ - EX(sw, t1, (offset + 0x04)(dst), s_fixup); \ - EX(sw, t2, (offset + 0x08)(dst), s_fixup); \ - EX(sw, t3, (offset + 0x0c)(dst), s_fixup); \ - EX(lw, t0, (offset + 0x10)(src), l_fixup); \ - EX(lw, t1, (offset + 0x14)(src), l_fixup); \ - EX(lw, t2, (offset + 0x18)(src), l_fixup); \ - EX(lw, t3, (offset + 0x1c)(src), l_fixup); \ - EX(sw, t0, (offset + 0x10)(dst), s_fixup); \ - EX(sw, t1, (offset + 0x14)(dst), s_fixup); \ - EX(sw, t2, (offset + 0x18)(dst), s_fixup); \ - EX(sw, t3, (offset + 0x1c)(dst), s_fixup) - -/* ascending order, destination unaligned */ -#define UMOVE_BIGGERCHUNK(src, dst, offset, t0, t1, t2, t3) \ - EX(ld, t0, (offset + 0x00)(src), l_fixup); \ - EX(ld, t1, (offset + 0x08)(src), l_fixup); \ - EX(ld, t2, (offset + 0x10)(src), l_fixup); \ - EX(ld, t3, (offset + 0x18)(src), l_fixup); \ - UEXD(usd, t0, (offset + 0x00)(dst), s_fixup); \ - UEXD(usd, t1, (offset + 0x08)(dst), s_fixup); \ - UEXD(usd, t2, (offset + 0x10)(dst), s_fixup); \ - UEXD(usd, t3, (offset + 0x18)(dst), s_fixup); \ - EX(ld, t0, (offset + 0x20)(src), l_fixup); \ - EX(ld, t1, (offset + 0x28)(src), l_fixup); \ - EX(ld, t2, (offset + 0x30)(src), l_fixup); \ - EX(ld, t3, (offset + 0x38)(src), l_fixup); \ - UEXD(usd, t0, (offset + 0x20)(dst), s_fixup); \ - UEXD(usd, t1, (offset + 0x28)(dst), s_fixup); \ - UEXD(usd, t2, (offset + 0x30)(dst), s_fixup); \ - UEXD(usd, t3, (offset + 0x38)(dst), s_fixup) - -/* ascending order, destination unaligned */ -#define UMOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3) \ - EX(lw, t0, (offset + 0x00)(src), l_fixup); \ - EX(lw, t1, (offset + 0x04)(src), l_fixup); \ - EX(lw, t2, (offset + 0x08)(src), l_fixup); \ - EX(lw, t3, (offset + 0x0c)(src), l_fixup); \ - UEX(usw, t0, (offset + 0x00)(dst), s_fixup); \ - UEX(usw, t1, (offset + 0x04)(dst), s_fixup); \ - UEX(usw, t2, (offset + 0x08)(dst), s_fixup); \ - UEX(usw, t3, (offset + 0x0c)(dst), s_fixup); \ - EX(lw, t0, (offset + 0x10)(src), l_fixup); \ - EX(lw, t1, (offset + 0x14)(src), l_fixup); \ - EX(lw, t2, (offset + 0x18)(src), l_fixup); \ - EX(lw, t3, (offset + 0x1c)(src), l_fixup); \ - UEX(usw, t0, (offset + 0x10)(dst), s_fixup); \ - UEX(usw, t1, (offset + 0x14)(dst), s_fixup); \ - UEX(usw, t2, (offset + 0x18)(dst), s_fixup); \ - UEX(usw, t3, (offset + 0x1c)(dst), s_fixup) +/* + * Only on the 64-bit kernel we can made use of 64-bit registers. + */ +#ifdef CONFIG_MIPS64 +#define USE_DOUBLE +#endif + +#ifdef USE_DOUBLE + +#define LOAD ld +#define LOADL ldl +#define LOADR ldr +#define STOREL sdl +#define STORER sdr +#define STORE sd +#define ADD daddu +#define SUB dsubu +#define SRL dsrl +#define SRA dsra +#define SLL dsll +#define SLLV dsllv +#define SRLV dsrlv +#define NBYTES 8 +#define LOG_NBYTES 3 + +/* + * As we are sharing code base with the mips32 tree (which use the o32 ABI + * register definitions). We need to redefine the register definitions from + * the n64 ABI register naming to the o32 ABI register naming. + */ +#undef t0 +#undef t1 +#undef t2 +#undef t3 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 + +#else + +#define LOAD lw +#define LOADL lwl +#define LOADR lwr +#define STOREL swl +#define STORER swr +#define STORE sw +#define ADD addu +#define SUB subu +#define SRL srl +#define SLL sll +#define SRA sra +#define SLLV sllv +#define SRLV srlv +#define NBYTES 4 +#define LOG_NBYTES 2 + +#endif /* USE_DOUBLE */ + +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define LDFIRST LOADR +#define LDREST LOADL +#define STFIRST STORER +#define STREST STOREL +#define SHIFT_DISCARD SLLV +#else +#define LDFIRST LOADL +#define LDREST LOADR +#define STFIRST STOREL +#define STREST STORER +#define SHIFT_DISCARD SRLV +#endif + +#define FIRST(unit) ((unit)*NBYTES) +#define REST(unit) (FIRST(unit)+NBYTES-1) +#define UNIT(unit) FIRST(unit) + +#define ADDRMASK (NBYTES-1) .text .set noreorder .set noat +/* + * A combined memcpy/__copy_user + * __copy_user sets len to 0 for success; else to an upper bound of + * the number of uncopied bytes. + * memcpy sets v0 to dst. + */ .align 5 LEAF(memcpy) /* a0=dst a1=src a2=len */ - move v0, a0 /* return value */ + move v0, dst /* return value */ __memcpy: FEXPORT(__copy_user) - xor ta0, a0, a1 - andi ta0, ta0, 0x7 - move t3, a0 - beqz ta0, can_align - sltiu t8, a2, 0x8 - - b memcpy_u_src # bad alignment - move ta2, a2 - -can_align: - bnez t8, small_memcpy # < 8 bytes to copy - move ta2, a2 - - beqz a2, out - andi t8, a1, 0x1 - -hword_align: - beqz t8, word_align - andi t8, a1, 0x2 - - EX(lb, ta0, (a1), l_fixup) - dsubu a2, a2, 0x1 - EX(sb, ta0, (a0), s_fixup) - daddu a1, a1, 0x1 - daddu a0, a0, 0x1 - andi t8, a1, 0x2 - -word_align: - beqz t8, dword_align - sltiu t8, a2, 56 - - EX(lh, ta0, (a1), l_fixup) - dsubu a2, a2, 0x2 - EX(sh, ta0, (a0), s_fixup) - sltiu t8, a2, 56 - daddu a0, a0, 0x2 - daddu a1, a1, 0x2 - -dword_align: - bnez t8, do_end_words - move t8, a2 - - andi t8, a1, 0x4 - beqz t8, qword_align - andi t8, a1, 0x8 - - EX(lw, ta0, 0x00(a1), l_fixup) - dsubu a2, a2, 0x4 - EX(sw, ta0, 0x00(a0), s_fixup) - daddu a1, a1, 0x4 - daddu a0, a0, 0x4 - andi t8, a1, 0x8 - -qword_align: - beqz t8, oword_align - andi t8, a1, 0x10 - - EX(lw, ta0, 0x00(a1), l_fixup) - EX(lw, ta1, 0x04(a1), l_fixup) - dsubu a2, a2, 0x8 - EX(sw, ta0, 0x00(a0), s_fixup) - EX(sw, ta1, 0x04(a0), s_fixup) - daddu a1, a1, 0x8 - andi t8, a1, 0x10 - daddu a0, a0, 0x8 - -oword_align: - beqz t8, begin_movement - srl t8, a2, 0x7 - - EX(lw, ta3, 0x00(a1), l_fixup) - EX(lw, t0, 0x04(a1), l_fixup) - EX(lw, ta0, 0x08(a1), l_fixup) - EX(lw, ta1, 0x0c(a1), l_fixup) - EX(sw, ta3, 0x00(a0), s_fixup) - EX(sw, t0, 0x04(a0), s_fixup) - EX(sw, ta0, 0x08(a0), s_fixup) - EX(sw, ta1, 0x0c(a0), s_fixup) - dsubu a2, a2, 0x10 - daddu a1, a1, 0x10 - srl t8, a2, 0x7 - daddu a0, a0, 0x10 - -begin_movement: - beqz t8, 0f - andi ta2, a2, 0x40 - -move_128bytes: - PREF (0, 2*128(a0)) - PREF (1, 2*128(a1)) - MOVE_BIGGERCHUNK(a1, a0, 0x00, ta0, ta1, ta3, t0) - MOVE_BIGGERCHUNK(a1, a0, 0x40, ta0, ta1, ta3, t0) - dsubu t8, t8, 0x01 - daddu a1, a1, 0x80 - bnez t8, move_128bytes - daddu a0, a0, 0x80 - -0: - beqz ta2, 1f - andi ta2, a2, 0x20 - -move_64bytes: - MOVE_BIGGERCHUNK(a1, a0, 0x00, ta0, ta1, ta3, t0) - daddu a1, a1, 0x40 - daddu a0, a0, 0x40 - + /* + * Note: dst & src may be unaligned, len may be 0 + * Temps + */ +#define rem t8 + + /* + * The "issue break"s below are very approximate. + * Issue delays for dcache fills will perturb the schedule, as will + * load queue full replay traps, etc. + * + * If len < NBYTES use byte operations. + */ + PREF( 0, 0(src) ) + PREF( 1, 0(dst) ) + sltu t2, len, NBYTES + and t1, dst, ADDRMASK + PREF( 0, 1*32(src) ) + PREF( 1, 1*32(dst) ) + bnez t2, copy_bytes_checklen + and t0, src, ADDRMASK + PREF( 0, 2*32(src) ) + PREF( 1, 2*32(dst) ) + bnez t1, dst_unaligned + nop + bnez t0, src_unaligned_dst_aligned + /* + * use delay slot for fall-through + * src and dst are aligned; need to compute rem + */ +both_aligned: + SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter + beqz t0, cleanup_both_aligned # len < 8*NBYTES + and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES) + PREF( 0, 3*32(src) ) + PREF( 1, 3*32(dst) ) + .align 4 1: - beqz ta2, do_end_words - andi t8, a2, 0x1c - -move_32bytes: - MOVE_BIGCHUNK(a1, a0, 0x00, ta0, ta1, ta3, t0) - andi t8, a2, 0x1c - daddu a1, a1, 0x20 - daddu a0, a0, 0x20 - -do_end_words: - beqz t8, maybe_end_cruft - srl t8, t8, 0x2 - -end_words: - EX(lw, ta0, (a1), l_fixup) - dsubu t8, t8, 0x1 - EX(sw, ta0, (a0), s_fixup) - daddu a1, a1, 0x4 - bnez t8, end_words - daddu a0, a0, 0x4 - -maybe_end_cruft: - andi ta2, a2, 0x3 - -small_memcpy: - beqz ta2, out - move a2, ta2 - -end_bytes: - EX(lb, ta0, (a1), l_fixup) - dsubu a2, a2, 0x1 - EX(sb, ta0, (a0), s_fixup) - daddu a1, a1, 0x1 - bnez a2, end_bytes - daddu a0, a0, 0x1 - -out: jr ra - move a2, zero - -/* ------------------------------------------------------------------------- */ +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) + SUB len, len, 8*NBYTES +EXC( LOAD t4, UNIT(4)(src), l_exc_copy) +EXC( LOAD t7, UNIT(5)(src), l_exc_copy) +EXC( STORE t0, UNIT(0)(dst), s_exc_p8u) +EXC( STORE t1, UNIT(1)(dst), s_exc_p7u) +EXC( LOAD t0, UNIT(6)(src), l_exc_copy) +EXC( LOAD t1, UNIT(7)(src), l_exc_copy) + ADD src, src, 8*NBYTES + ADD dst, dst, 8*NBYTES +EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u) +EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u) +EXC( STORE t4, UNIT(-4)(dst), s_exc_p4u) +EXC( STORE t7, UNIT(-3)(dst), s_exc_p3u) +EXC( STORE t0, UNIT(-2)(dst), s_exc_p2u) +EXC( STORE t1, UNIT(-1)(dst), s_exc_p1u) + PREF( 0, 8*32(src) ) + PREF( 1, 8*32(dst) ) + bne len, rem, 1b + nop -/* Bad, bad. At least try to align the source */ + /* + * len == rem == the number of bytes left to copy < 8*NBYTES + */ +cleanup_both_aligned: + beqz len, done + sltu t0, len, 4*NBYTES + bnez t0, less_than_4units + and rem, len, (NBYTES-1) # rem = len % NBYTES + /* + * len >= 4*NBYTES + */ +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) + SUB len, len, 4*NBYTES + ADD src, src, 4*NBYTES +EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) +EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) +EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) +EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) + beqz len, done + ADD dst, dst, 4*NBYTES +less_than_4units: + /* + * rem = len % NBYTES + */ + beq rem, len, copy_bytes + nop +1: +EXC( LOAD t0, 0(src), l_exc) + ADD src, src, NBYTES + SUB len, len, NBYTES +EXC( STORE t0, 0(dst), s_exc_p1u) + bne rem, len, 1b + ADD dst, dst, NBYTES + + /* + * src and dst are aligned, need to copy rem bytes (rem < NBYTES) + * A loop would do only a byte at a time with possible branch + * mispredicts. Can't do an explicit LOAD dst,mask,or,STORE + * because can't assume read-access to dst. Instead, use + * STREST dst, which doesn't require read access to dst. + * + * This code should perform better than a simple loop on modern, + * wide-issue mips processors because the code has fewer branches and + * more instruction-level parallelism. + */ +#define bits t2 + beqz len, done + ADD t1, dst, len # t1 is just past last byte of dst + li bits, 8*NBYTES + SLL rem, len, 3 # rem = number of bits to keep +EXC( LOAD t0, 0(src), l_exc) + SUB bits, bits, rem # bits = number of bits to discard + SHIFT_DISCARD t0, t0, bits +EXC( STREST t0, -1(t1), s_exc) + jr ra + move len, zero +dst_unaligned: + /* + * dst is unaligned + * t0 = src & ADDRMASK + * t1 = dst & ADDRMASK; T1 > 0 + * len >= NBYTES + * + * Copy enough bytes to align dst + * Set match = (src and dst have same alignment) + */ +#define match rem +EXC( LDFIRST t3, FIRST(0)(src), l_exc) + ADD t2, zero, NBYTES +EXC( LDREST t3, REST(0)(src), l_exc_copy) + SUB t2, t2, t1 # t2 = number of bytes copied + xor match, t0, t1 +EXC( STFIRST t3, FIRST(0)(dst), s_exc) + beq len, t2, done + SUB len, len, t2 + ADD dst, dst, t2 + beqz match, both_aligned + ADD src, src, t2 + +src_unaligned_dst_aligned: + SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter + PREF( 0, 3*32(src) ) + beqz t0, cleanup_src_unaligned + and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES + PREF( 1, 3*32(dst) ) +1: +/* + * Avoid consecutive LD*'s to the same register since some mips + * implementations can't issue them in the same cycle. + * It's OK to load FIRST(N+1) before REST(N) because the two addresses + * are to the same unit (unless src is aligned, but it's not). + */ +EXC( LDFIRST t0, FIRST(0)(src), l_exc) +EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) + SUB len, len, 4*NBYTES +EXC( LDREST t0, REST(0)(src), l_exc_copy) +EXC( LDREST t1, REST(1)(src), l_exc_copy) +EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) +EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) +EXC( LDREST t2, REST(2)(src), l_exc_copy) +EXC( LDREST t3, REST(3)(src), l_exc_copy) + PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed) + ADD src, src, 4*NBYTES +#ifdef CONFIG_CPU_SB1 + nop # improves slotting +#endif +EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) +EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) +EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) +EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) + PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed) + bne len, rem, 1b + ADD dst, dst, 4*NBYTES + +cleanup_src_unaligned: + beqz len, done + and rem, len, NBYTES-1 # rem = len % NBYTES + beq rem, len, copy_bytes + nop +1: +EXC( LDFIRST t0, FIRST(0)(src), l_exc) +EXC( LDREST t0, REST(0)(src), l_exc_copy) + ADD src, src, NBYTES + SUB len, len, NBYTES +EXC( STORE t0, 0(dst), s_exc_p1u) + bne len, rem, 1b + ADD dst, dst, NBYTES -memcpy_u_src: - bnez t8, small_memcpy # < 8 bytes? - move ta2, a2 - - daddiu ta0, a1, 7 # ta0: how much to align - ori ta0, 7 - xori ta0, 7 - dsubu ta0, a1 - - UEXD(uld, ta1, 0(a1), l_fixup) # dword alignment - UEXD(usd, ta1, 0(a0), s_fixup) - - daddu a1, ta0 # src - daddu a0, ta0 # dst - dsubu a2, ta0 # len - - sltiu t8, a2, 56 - bnez t8, u_do_end_words - andi t8, a2, 0x3c - - andi t8, a1, 8 # now qword aligned? - -u_qword_align: - beqz t8, u_oword_align - andi t8, a1, 0x10 - - EX(ld, ta0, 0x00(a1), l_fixup) - dsubu a2, a2, 0x8 - UEXD(usd, ta0, 0x00(a0), s_fixup) - daddu a1, a1, 0x8 - andi t8, a1, 0x10 - daddu a0, a0, 0x8 - -u_oword_align: - beqz t8, u_begin_movement - srl t8, a2, 0x7 - - EX(lw, ta3, 0x08(a1), l_fixup) - EX(lw, t0, 0x0c(a1), l_fixup) - EX(lw, ta0, 0x00(a1), l_fixup) - EX(lw, ta1, 0x04(a1), l_fixup) - UEX(usw, ta3, 0x08(a0), s_fixup) - UEX(usw, t0, 0x0c(a0), s_fixup) - UEX(usw, ta0, 0x00(a0), s_fixup) - UEX(usw, ta1, 0x04(a0), s_fixup) - dsubu a2, a2, 0x10 - daddu a1, a1, 0x10 - srl t8, a2, 0x7 - daddu a0, a0, 0x10 - -u_begin_movement: - beqz t8, 0f - andi ta2, a2, 0x40 - -u_move_128bytes: - UMOVE_BIGGERCHUNK(a1, a0, 0x00, ta0, ta1, ta3, t0) - UMOVE_BIGGERCHUNK(a1, a0, 0x40, ta0, ta1, ta3, t0) - dsubu t8, t8, 0x01 - daddu a1, a1, 0x80 - bnez t8, u_move_128bytes - daddu a0, a0, 0x80 - -0: - beqz ta2, 1f - andi ta2, a2, 0x20 - -u_move_64bytes: - UMOVE_BIGGERCHUNK(a1, a0, 0x00, ta0, ta1, ta3, t0) - daddu a1, a1, 0x40 - daddu a0, a0, 0x40 +copy_bytes_checklen: + beqz len, done + nop +copy_bytes: + /* 0 < len < NBYTES */ +#define COPY_BYTE(N) \ +EXC( lb t0, N(src), l_exc); \ + SUB len, len, 1; \ + beqz len, done; \ +EXC( sb t0, N(dst), s_exc_p1) + + COPY_BYTE(0) + COPY_BYTE(1) +#ifdef USE_DOUBLE + COPY_BYTE(2) + COPY_BYTE(3) + COPY_BYTE(4) + COPY_BYTE(5) +#endif +EXC( lb t0, NBYTES-2(src), l_exc) + SUB len, len, 1 + jr ra +EXC( sb t0, NBYTES-2(dst), s_exc_p1) +done: + jr ra + nop + END(memcpy) +l_exc_copy: + /* + * Copy bytes from src until faulting load address (or until a + * lb faults) + * + * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28) + * may be more than a byte beyond the last address. + * Hence, the lb below may get an exception. + * + * Assumes src < THREAD_BUADDR($28) + */ + LOAD t0, TI_TASK($28) + LOAD t0, THREAD_BUADDR(t0) 1: - beqz ta2, u_do_end_words - andi t8, a2, 0x1c +EXC( lb t1, 0(src), l_exc) + ADD src, src, 1 + sb t1, 0(dst) # can't fault -- we're copy_from_user + bne src, t0, 1b + ADD dst, dst, 1 +l_exc: + LOAD t0, THREAD_BUADDR($28) # t0 is just past last good address + LOAD t0, THREAD_BUADDR(t0) + nop + SUB len, AT, t0 # len number of uncopied bytes + /* + * Here's where we rely on src and dst being incremented in tandem, + * See (3) above. + * dst += (fault addr - src) to put dst at first byte to clear + */ + ADD dst, t0 # compute start address in a1 + SUB dst, src + /* + * Clear len bytes starting at dst. Can't call __bzero because it + * might modify len. An inefficient loop for these rare times... + */ + beqz len, done + SUB src, len, 1 +1: sb zero, 0(dst) + ADD dst, dst, 1 + bnez src, 1b + SUB src, src, 1 + jr ra + nop -u_move_32bytes: - UMOVE_BIGCHUNK(a1, a0, 0x00, ta0, ta1, ta3, t0) - andi t8, a2, 0x1c - daddu a1, a1, 0x20 - daddu a0, a0, 0x20 - -u_do_end_words: - beqz t8, u_maybe_end_cruft - srl t8, t8, 0x2 - -u_end_words: - EX(lw, ta0, 0x00(a1), l_fixup) - dsubu t8, t8, 0x1 - UEX(usw, ta0, 0x00(a0), s_fixup) - daddu a1, a1, 0x4 - bnez t8, u_end_words - daddu a0, a0, 0x4 - -u_maybe_end_cruft: - andi ta2, a2, 0x3 - -u_cannot_optimize: - beqz ta2, out - move a2, ta2 - -u_end_bytes: - EX(lb, ta0, (a1), l_fixup) - dsubu a2, a2, 0x1 - EX(sb, ta0, (a0), s_fixup) - daddu a1, a1, 0x1 - bnez a2, u_end_bytes - daddu a0, a0, 0x1 - jr ra - move a2, zero - END(memcpy) +#define SEXC(n) \ +s_exc_p ## n ## u: \ + jr ra; \ + ADD len, len, n*NBYTES + +SEXC(8) +SEXC(7) +SEXC(6) +SEXC(5) +SEXC(4) +SEXC(3) +SEXC(2) +SEXC(1) -/* descending order, destination aligned */ -#define RMOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3) \ - lw t0, (offset + 0x10)(src); \ - lw t1, (offset + 0x14)(src); \ - lw t2, (offset + 0x18)(src); \ - lw t3, (offset + 0x1c)(src); \ - sw t0, (offset + 0x10)(dst); \ - sw t1, (offset + 0x14)(dst); \ - sw t2, (offset + 0x18)(dst); \ - sw t3, (offset + 0x1c)(dst); \ - lw t0, (offset + 0x00)(src); \ - lw t1, (offset + 0x04)(src); \ - lw t2, (offset + 0x08)(src); \ - lw t3, (offset + 0x0c)(src); \ - sw t0, (offset + 0x00)(dst); \ - sw t1, (offset + 0x04)(dst); \ - sw t2, (offset + 0x08)(dst); \ - sw t3, (offset + 0x0c)(dst) - -/* descending order, destination ununaligned */ -#define RUMOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3) \ - lw t0, (offset + 0x10)(src); \ - lw t1, (offset + 0x14)(src); \ - lw t2, (offset + 0x18)(src); \ - lw t3, (offset + 0x1c)(src); \ - usw t0, (offset + 0x10)(dst); \ - usw t1, (offset + 0x14)(dst); \ - usw t2, (offset + 0x18)(dst); \ - usw t3, (offset + 0x1c)(dst); \ - lw t0, (offset + 0x00)(src); \ - lw t1, (offset + 0x04)(src); \ - lw t2, (offset + 0x08)(src); \ - lw t3, (offset + 0x0c)(src); \ - usw t0, (offset + 0x00)(dst); \ - usw t1, (offset + 0x04)(dst); \ - usw t2, (offset + 0x08)(dst); \ - usw t3, (offset + 0x0c)(dst) +s_exc_p1: + jr ra + ADD len, len, 1 +s_exc: + jr ra + nop .align 5 LEAF(memmove) - daddu t0, a0, a2 + ADD t0, a0, a2 + ADD t1, a1, a2 sltu t0, a1, t0 # dst + len <= src -> memcpy - daddu t1, a1, a2 sltu t1, a0, t1 # dst >= src + len -> memcpy and t0, t1 beqz t0, __memcpy - move v0, a0 /* return value */ beqz a2, r_out END(memmove) + /* fall through to __rmemcpy */ LEAF(__rmemcpy) /* a0=dst a1=src a2=len */ - sltu t0, a1, a0 + sltu t0, a1, a0 beqz t0, r_end_bytes_up # src >= dst nop - daddu a0, a2 # dst = dst + len - daddu a1, a2 # src = src + len - -#if 0 /* Horror fix */ - xor ta0, a0, a1 - andi ta0, ta0, 0x3 - move t3, a0 - beqz ta0, r_can_align - sltiu t8, a2, 0x8 - - b r_memcpy_u_src # bad alignment - move ta2, a2 - -r_can_align: - bnez t8, r_small_memcpy # < 8 bytes to copy - move ta2, a2 - - beqz a2, r_out - andi t8, a1, 0x1 - -r_hword_align: - beqz t8, r_word_align - andi t8, a1, 0x2 - - lb ta0, -1(a1) - dsubu a2, a2, 0x1 - sb ta0, -1(a0) - dsubu a1, a1, 0x1 - dsubu a0, a0, 0x1 - andi t8, a1, 0x2 - -r_word_align: - beqz t8, r_dword_align - sltiu t8, a2, 56 - - lh ta0, -2(a1) - dsubu a2, a2, 0x2 - sh ta0, -2(a0) - sltiu t8, a2, 56 - dsubu a0, a0, 0x2 - dsubu a1, a1, 0x2 - -r_dword_align: - bnez t8, r_do_end_words - move t8, a2 - - andi t8, a1, 0x4 - beqz t8, r_qword_align - andi t8, a1, 0x8 - - lw ta0, -4(a1) - dsubu a2, a2, 0x4 - sw ta0, -4(a0) - dsubu a1, a1, 0x4 - dsubu a0, a0, 0x4 - andi t8, a1, 0x8 - -r_qword_align: - beqz t8, r_oword_align - andi t8, a1, 0x10 - - dsubu a1, a1, 0x8 - lw ta0, 0x04(a1) - lw ta1, 0x00(a1) - dsubu a0, a0, 0x8 - sw ta0, 0x04(a0) - sw ta1, 0x00(a0) - dsubu a2, a2, 0x8 - - andi t8, a1, 0x10 - -r_oword_align: - beqz t8, r_begin_movement - srl t8, a2, 0x7 - - dsubu a1, a1, 0x10 - lw ta3, 0x08(a1) # assumes subblock ordering - lw t0, 0x0c(a1) - lw ta0, 0x00(a1) - lw ta1, 0x04(a1) - dsubu a0, a0, 0x10 - sw ta3, 0x08(a0) - sw t0, 0x0c(a0) - sw ta0, 0x00(a0) - sw ta1, 0x04(a0) - dsubu a2, a2, 0x10 - srl t8, a2, 0x7 - -r_begin_movement: - beqz t8, 0f - andi ta2, a2, 0x40 - -r_move_128bytes: - RMOVE_BIGCHUNK(a1, a0, -0x80, ta0, ta1, ta3, t0) - RMOVE_BIGCHUNK(a1, a0, -0x60, ta0, ta1, ta3, t0) - RMOVE_BIGCHUNK(a1, a0, -0x40, ta0, ta1, ta3, t0) - RMOVE_BIGCHUNK(a1, a0, -0x20, ta0, ta1, ta3, t0) - dsubu t8, t8, 0x01 - dsubu a1, a1, 0x80 - bnez t8, r_move_128bytes - dsubu a0, a0, 0x80 - -0: - beqz ta2, 1f - andi ta2, a2, 0x20 - -r_move_64bytes: - dsubu a1, a1, 0x40 - dsubu a0, a0, 0x40 - RMOVE_BIGCHUNK(a1, a0, 0x20, ta0, ta1, ta3, t0) - RMOVE_BIGCHUNK(a1, a0, 0x00, ta0, ta1, ta3, t0) - -1: - beqz ta2, r_do_end_words - andi t8, a2, 0x1c - -r_move_32bytes: - dsubu a1, a1, 0x20 - dsubu a0, a0, 0x20 - RMOVE_BIGCHUNK(a1, a0, 0x00, ta0, ta1, ta3, t0) - andi t8, a2, 0x1c - -r_do_end_words: - beqz t8, r_maybe_end_cruft - srl t8, t8, 0x2 - -r_end_words: - lw ta0, -4(a1) - dsubu t8, t8, 0x1 - sw ta0, -4(a0) - dsubu a1, a1, 0x4 - bnez t8, r_end_words - dsubu a0, a0, 0x4 - -r_maybe_end_cruft: - andi ta2, a2, 0x3 - -r_small_memcpy: - beqz ta2, r_out - move a2, ta2 -#endif /* Horror fix */ + ADD a0, a2 # dst = dst + len + ADD a1, a2 # src = src + len r_end_bytes: - lb ta0, -1(a1) - dsubu a2, a2, 0x1 - sb ta0, -1(a0) - dsubu a1, a1, 0x1 + lb t0, -1(a1) + SUB a2, a2, 0x1 + sb t0, -1(a0) + SUB a1, a1, 0x1 bnez a2, r_end_bytes - dsubu a0, a0, 0x1 + SUB a0, a0, 0x1 r_out: - jr ra - move a2, zero + jr ra + move a2, zero r_end_bytes_up: lb t0, (a1) - dsubu a2, a2, 0x1 + SUB a2, a2, 0x1 sb t0, (a0) - daddu a1, a1, 0x1 + ADD a1, a1, 0x1 bnez a2, r_end_bytes_up - daddu a0, a0, 0x1 + ADD a0, a0, 0x1 jr ra move a2, zero - -#if 0 /* Horror fix */ -/* ------------------------------------------------------------------------- */ - -/* Bad, bad. At least try to align the source */ - -r_memcpy_u_src: - bnez t8, r_small_memcpy # < 8 bytes? - move ta2, a2 - - andi ta0, a1, 7 # ta0: how much to align - - ulw ta1, -8(a1) # dword alignment - ulw ta2, -4(a1) - usw ta1, -8(a0) - usw ta2, -4(a0) - - dsubu a1, ta0 # src - dsubu a0, ta0 # dst - dsubu a2, ta0 # len - - sltiu t8, a2, 56 - bnez t8, ru_do_end_words - andi t8, a2, 0x3c - - andi t8, a1, 8 # now qword aligned? - -ru_qword_align: - beqz t8, ru_oword_align - andi t8, a1, 0x10 - - dsubu a1, a1, 0x8 - lw ta0, 0x00(a1) - lw ta1, 0x04(a1) - dsubu a0, a0, 0x8 - usw ta0, 0x00(a0) - usw ta1, 0x04(a0) - dsubu a2, a2, 0x8 - - andi t8, a1, 0x10 - -ru_oword_align: - beqz t8, ru_begin_movement - srl t8, a2, 0x7 - - dsubu a1, a1, 0x10 - lw ta3, 0x08(a1) # assumes subblock ordering - lw t0, 0x0c(a1) - lw ta0, 0x00(a1) - lw ta1, 0x04(a1) - dsubu a0, a0, 0x10 - usw ta3, 0x08(a0) - usw t0, 0x0c(a0) - usw ta0, 0x00(a0) - usw ta1, 0x04(a0) - dsubu a2, a2, 0x10 - - srl t8, a2, 0x7 - -ru_begin_movement: - beqz t8, 0f - andi ta2, a2, 0x40 - -ru_move_128bytes: - RUMOVE_BIGCHUNK(a1, a0, -0x80, ta0, ta1, ta3, t0) - RUMOVE_BIGCHUNK(a1, a0, -0x60, ta0, ta1, ta3, t0) - RUMOVE_BIGCHUNK(a1, a0, -0x40, ta0, ta1, ta3, t0) - RUMOVE_BIGCHUNK(a1, a0, -0x20, ta0, ta1, ta3, t0) - dsubu t8, t8, 0x01 - dsubu a1, a1, 0x80 - bnez t8, ru_move_128bytes - dsubu a0, a0, 0x80 - -0: - beqz ta2, 1f - andi ta2, a2, 0x20 - -ru_move_64bytes: - dsubu a1, a1, 0x40 - dsubu a0, a0, 0x40 - RUMOVE_BIGCHUNK(a1, a0, 0x20, ta0, ta1, ta3, t0) - RUMOVE_BIGCHUNK(a1, a0, 0x00, ta0, ta1, ta3, t0) - -1: - beqz ta2, ru_do_end_words - andi t8, a2, 0x1c - -ru_move_32bytes: - dsubu a1, a1, 0x20 - dsubu a0, a0, 0x20 - RUMOVE_BIGCHUNK(a1, a0, 0x00, ta0, ta1, ta3, t0) - andi t8, a2, 0x1c - -ru_do_end_words: - beqz t8, ru_maybe_end_cruft - srl t8, t8, 0x2 - -ru_end_words: - lw ta0, -4(a1) - usw ta0, -4(a0) - dsubu t8, t8, 0x1 - dsubu a1, a1, 0x4 - bnez t8, ru_end_words - dsubu a0, a0, 0x4 - -ru_maybe_end_cruft: - andi ta2, a2, 0x3 - -ru_cannot_optimize: - beqz ta2, r_out - move a2, ta2 - -ru_end_bytes: - lb ta0, -1(a1) - dsubu a2, a2, 0x1 - sb ta0, -1(a0) - dsubu a1, a1, 0x1 - bnez a2, ru_end_bytes - dsubu a0, a0, 0x1 - - jr ra - move a2, zero -#endif /* Horror fix */ END(__rmemcpy) - -l_fixup: # clear the rest of the buffer - ld ta0, THREAD_BUADDR($28) - nop - dsubu a2, AT, ta0 # a2 bytes to go - daddu a0, ta0 # compute start address in a1 - dsubu a0, a1 - j __bzero - move a1, zero - -s_fixup: - jr ra - nop --- linux-2.5.73/arch/mips64/lib/memset.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/lib/memset.S 2003-06-27 15:56:23.000000000 -0700 @@ -52,7 +52,6 @@ LEAF(memset) 1: FEXPORT(__bzero) - .type __bzero, @function sltiu t0, a2, 8 /* very small region? */ bnez t0, small_memset andi t0, a0, 7 /* aligned? */ @@ -82,7 +81,7 @@ FEXPORT(__bzero) .set noreorder memset_partial: - la t1, 2f /* where to start */ + PTR_LA t1, 2f /* where to start */ .set noat dsrl AT, t0, 1 dsubu t1, AT @@ -90,8 +89,12 @@ memset_partial: jr t1 daddu a0, t0 /* dest ptr */ + .set push + .set noreorder + .set nomacro F_FILL64(a0, -64, a1, partial_fixup) /* ... but first do dwds ... */ -2: andi a2, 7 /* 0 <= n <= 7 to go */ +2: .set pop + andi a2, 7 /* 0 <= n <= 7 to go */ beqz a2, 1f daddu a0, a2 /* What's left */ @@ -121,14 +124,16 @@ first_fixup: nop fwd_fixup: - ld t0, THREAD_BUADDR($28) + ld t2, TI_TASK($28) + ld t0, THREAD_BUADDR(t2) andi a2, 0x3f daddu a2, t1 jr ra dsubu a2, t0 partial_fixup: - ld t0, THREAD_BUADDR($28) + ld t2, TI_TASK($28) + ld t0, THREAD_BUADDR(t2) andi a2, 7 daddu a2, t1 jr ra --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/lib/promlib.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,24 @@ +#include +#include + +extern void prom_putchar(char); + +void prom_printf(char *fmt, ...) +{ + va_list args; + char ppbuf[1024]; + char *bptr; + + va_start(args, fmt); + vsprintf(ppbuf, fmt, args); + + bptr = ppbuf; + + while (*bptr != 0) { + if (*bptr == '\n') + prom_putchar('\r'); + + prom_putchar(*bptr++); + } + va_end(args); +} --- linux-2.5.73/arch/mips64/lib/strlen_user.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/lib/strlen_user.S 2003-06-27 15:56:23.000000000 -0700 @@ -23,9 +23,9 @@ * Return 0 for error */ LEAF(__strlen_user_asm) - ld v0, THREAD_CURDS($28) # pointer ok? + ld v0, TI_ADDR_LIMIT($28) # pointer ok? and v0, a0 - bltz v0, fault + bnez v0, fault FEXPORT(__strlen_user_nocheck_asm) move v0, a0 @@ -36,9 +36,5 @@ FEXPORT(__strlen_user_nocheck_asm) jr ra END(__strlen_user_asm) - .section __ex_table,"a" - PTR 1b, fault - .previous - fault: move v0, zero jr ra --- linux-2.5.73/arch/mips64/lib/strncpy_user.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/lib/strncpy_user.S 2003-06-27 15:56:23.000000000 -0700 @@ -28,9 +28,9 @@ */ LEAF(__strncpy_from_user_asm) - ld v0, THREAD_CURDS($28) # pointer ok? + ld v0, TI_ADDR_LIMIT($28) # pointer ok? and v0, a1 - bltz v0, fault + bnez v0, fault FEXPORT(__strncpy_from_user_nocheck_asm) move v0, zero --- linux-2.5.73/arch/mips64/lib/strnlen_user.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/lib/strnlen_user.S 2003-06-27 15:56:23.000000000 -0700 @@ -23,11 +23,11 @@ * Return 0 for error, len on string but at max a1 otherwise */ LEAF(__strnlen_user_asm) - ld v0, THREAD_CURDS($28) # pointer ok? - and v0, ta0 - bltz v0, fault + ld v0, TI_ADDR_LIMIT($28) # pointer ok? + and v0, a0 + bnez v0, fault -EXPORT(__strnlen_user_nocheck_asm) +FEXPORT(__strnlen_user_nocheck_asm) move v0, a0 daddu a1, a0 # stop pointer 1: beq v0, a1, 1f # limit reached? @@ -38,9 +38,5 @@ EXPORT(__strnlen_user_nocheck_asm) jr ra END(__strnlen_user_asm) - .section __ex_table,"a" - PTR 1b, fault - .previous - fault: move v0, zero jr ra --- linux-2.5.73/arch/mips64/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -3,10 +3,11 @@ # License. See the file "COPYING" in the main directory of this archive # for more details. # +# Copyright (C) 2002 Maciej W. Rozycki +# # This file is included by the global makefile so that you can add your own # architecture-specific flags and dependencies. Remember to do have actions -# for "archclean" and "archdep" for cleaning up and making dependencies for -# this architecture +# for "archclean" cleaning up for this architecture. # # @@ -14,16 +15,20 @@ # ifdef CONFIG_CPU_LITTLE_ENDIAN tool-prefix = mips64el-linux- +32bit-bfd = elf32-tradlittlemips +64bit-bfd = elf64-tradlittlemips else tool-prefix = mips64-linux- +32bit-bfd = elf32-tradbigmips +64bit-bfd = elf64-tradbigmips endif ifdef CONFIG_CROSSCOMPILE -CROSS_COMPILE = $(tool-prefix) +CROSS_COMPILE := $(tool-prefix) endif # -# The ELF GCC uses -G0 -mabicalls -fpic as default. We don't need PIC +# The ELF GCC uses -G 0 -mabicalls -fpic as default. We don't need PIC # code in the kernel since it only slows down the whole thing. For the # old GCC these options are just the defaults. At some point we might # make use of global pointer optimizations. @@ -32,117 +37,235 @@ endif # machines may also. Since BFD is incredibly buggy with respect to # crossformat linking we rely on the elf2ecoff tool for format conversion. # -CFLAGS += -I $(TOPDIR)/include/asm/gcc $(CFLAGS) -CFLAGS += -mabi=64 -G 0 -mno-abicalls -fno-pic -Wa,--trap -pipe -LDFLAGS_vmlinux += -G 0 -static # -N -MODFLAGS += -mlong-calls +cflags-y := -I $(TOPDIR)/include/asm/gcc +cflags-y += -mabi=64 -G 0 -mno-abicalls -fno-pic -Wa,--trap -pipe +LDFLAGS_vmlinux += -G 0 -static # -N +MODFLAGS += -mlong-calls -ifdef CONFIG_REMOTE_DEBUG -CFLAGS := $(CFLAGS) -g -endif +cflags-$(CONFIG_KGDB) += -g +cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer + +check_gcc = $(shell if $(AS) $(1) -o /dev/null -xc /dev/null > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi) +check_warning = $(shell if $(CC) $(1) -c -o /dev/null -xc /dev/null > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi) # # CPU-dependent compiler/assembler options for optimization. # -ifdef CONFIG_CPU_R4300 -CFLAGS := $(CFLAGS) -mcpu=r4300 -mips3 -endif -ifdef CONFIG_CPU_R4X00 -CFLAGS := $(CFLAGS) -mcpu=r4600 -mips3 -endif -ifdef CONFIG_CPU_R5000 -CFLAGS := $(CFLAGS) -mcpu=r8000 -mips4 +cflags-$(CONFIG_CPU_R4300) += -mcpu=r4300 -mips3 +cflags-$(CONFIG_CPU_R4X00) += -mcpu=r4600 -mips3 +cflags-$(CONFIG_CPU_R5000) += -mcpu=r8000 -mips4 +cflags-$(CONFIG_CPU_NEVADA) += -mcpu=r8000 -mips3 -mmad +cflags-$(CONFIG_CPU_RM7000) += $(call check_gcc, -mcpu=r7000, -mcpu=r5000) \ + -mips4 +cflags-$(CONFIG_CPU_SB1) += $(call check_gcc, -mcpu=sb1, -mcpu=r8000) \ + $(call check_gcc, -mips64, -mips4) +cflags-$(CONFIG_CPU_R8000) += -mcpu=r8000 -mips4 +cflags-$(CONFIG_CPU_R10000) += -mcpu=r8000 -mips4 +ifdef CONFIG_CPU_SB1 +ifdef CONFIG_SB1_PASS_1_WORKAROUNDS +MODFLAGS += -msb1-pass1-workarounds endif -ifdef CONFIG_CPU_NEVADA -CFLAGS := $(CFLAGS) -mcpu=r8000 -mips3 -mmad endif -ifdef CONFIG_CPU_R8000 -CFLAGS := $(CFLAGS) -mcpu=r8000 -mips4 -endif -ifdef CONFIG_CPU_R10000 -CFLAGS := $(CFLAGS) -mcpu=r8000 -mips4 +# Should be used then we get a MIPS64 compiler +#cflags-$(CONFIG_CPU_MIPS64) += -mips64 +cflags-$(CONFIG_CPU_MIPS64) += -mcpu=r8000 -mips4 + +# +# ramdisk/initrd support +# You need a compressed ramdisk image, named ramdisk.gz in +# arch/mips/ramdisk +# +ifdef CONFIG_EMBEDDED_RAMDISK +CORE_FILES += arch/mips/ramdisk/ramdisk.o +SUBDIRS += arch/mips/ramdisk endif -core-$(CONFIG_MIPS_FPU_EMULATOR) += arch/mips64/math-emu/ +# +# Firmware support +# +libs-$(CONFIG_ARC) += arch/mips/arc/ +libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/ # # Board-dependent options and extra files # -ifdef CONFIG_SGI_IP22 -libs-y += arch/mips64/sgi-ip22/ \ - arch/mips64/arc/ -# -# Set LOADADDR to >= 0x88069000 if you want to leave space for symmon, -# 0x88004000 for production kernels. Note that the value must be -# 16kb aligned or the handling of the current variable will break. # -LOADADDR += 0x88004000 +# DECstation family +# +ifdef CONFIG_DECSTATION +CORE_FILES += arch/mips/dec/dec.o +SUBDIRS += arch/mips/dec arch/mips/dec/prom +LIBS += arch/mips/dec/prom/rexlib.a +LOADADDR := 0x80040000 endif -ifdef CONFIG_SGI_IP27 -core-y += arch/mips64/sgi-ip27/ -libs-y += arch/mips64/arc/ # -# Set LOADADDR to >= 0xc000000000300000 if you want to leave space for +# MIPS Atlas board +# +core-$(CONFIG_MIPS_BOARDS_GEN) += arch/mips/mips-boards/generic/ +core-$(CONFIG_MIPS_ATLAS) += arch/mips/mips-boards/atlas/ +load-$(CONFIG_MIPS_ATLAS) += 0x80100000 + +# +# MIPS Malta board +# +core-$(CONFIG_MIPS_MALTA) += arch/mips/mips-boards/malta/ +load-$(CONFIG_MIPS_MALTA) += 0x80100000 + +# +# MIPS SEAD board +# +core-$(CONFIG_MIPS_SEAD) += arch/mips/mips-boards/sead/ +load-$(CONFIG_MIPS_SEAD) += 0x80100000 + +# +# Momentum Ocelot board +# +# The Ocelot setup.o must be linked early - it does the ioremap() for the +# mips_io_port_base. +# +core-$(CONFIG_MOMENCO_OCELOT) += arch/mips/gt64120/common/ \ + arch/mips/gt64120/momenco_ocelot/ +load-$(CONFIG_MOMENCO_OCELOT) += 0x80100000 + +# +# Momentum Ocelot-G board +# +# The Ocelot-G setup.o must be linked early - it does the ioremap() for the +# mips_io_port_base. +# +core-$(CONFIG_MOMENCO_OCELOT_G) += arch/mips/momentum/ocelot_g/ +load-$(CONFIG_MOMENCO_OCELOT_G) += 0x80100000 + +# +# Momentum Ocelot-C and -CS boards +# +# The Ocelot-C[S] setup.o must be linked early - it does the ioremap() for the +# mips_io_port_base. +core-$(CONFIG_MOMENCO_OCELOT_C) += arch/mips/momentum/ocelot_c/ +load-$(CONFIG_MOMENCO_OCELOT_C) += 0x80100000 + +# +# SGI IP22 (Indy/Indigo2) +# +# Set the load address to >= 0x88069000 if you want to leave space for symmon, +# 0x88004000 for production kernels. Note that the value must be 16kb aligned +# or the handling of the current variable will break. +# +core-$(CONFIG_SGI_IP22) += arch/mips/sgi-ip22/ +load-$(CONFIG_SGI_IP22) += 0x88004000 + +# +# SGI-IP27 (Origin200/2000) +# +# Set the load address to >= 0xc000000000300000 if you want to leave space for # symmon, 0xc00000000001c000 for production kernels. Note that the value # must be 16kb aligned or the handling of the current variable will break. # -#LOADADDR += 0xa80000000001c000 +ifdef CONFIG_SGI_IP27 +core-$(CONFIG_SGI_IP27) += arch/mips/sgi-ip27/ +#load-$(CONFIG_SGI_IP27) += 0xa80000000001c000 ifdef CONFIG_MAPPED_KERNEL -LOADADDR += 0xc001c000 +load-$(CONFIG_SGI_IP27) += 0xc001c000 else -LOADADDR += 0x8001c000 +load-$(CONFIG_SGI_IP27) += 0x8001c000 endif endif -ifdef CONFIG_SGI_IP32 -libs-y += arch/mips64/sgi-ip32/ - arch/mips64/arc/ # -# Set LOADADDR to >= 0x????????? if you want to leave space for symmon, -# 0x80002000 for production kernels. Note that the value must be -# 16kb aligned or the handling of the current variable will break. +# SGI-IP32 (O2) # -LOADADDR += 0x80002000 +# Set the load address to >= 0x????????? if you want to leave space for symmon, +# 0x80002000 for production kernels. Note that the value must be 16kb aligned +# or the handling of the current variable will break. +# +core-$(CONFIG_SGI_IP32) += arch/mips/sgi-ip32/ +load-$(CONFIG_SGI_IP32) += 0x80002000 + +# +# Sibyte SB1250 SOC +# +# This is a LIB so that it links at the end, and initcalls are later +# the sequence; but it is built as an object so that modules don't get +# removed (as happens, even if they have __initcall/module_init) +# +core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/sb1250/ +ifdef CONFIG_SIBYTE_BCM112X +ifdef CONFIG_MIPS_UNCACHED +load-y += 0xa0100000 +else +load-y += 0x80100000 +endif +endif +ifdef CONFIG_SIBYTE_SB1250 +ifdef CONFIG_MIPS_UNCACHED +load-y += 0xa0100000 +else +load-y += 0x80100000 +endif endif # +# Sibyte BCM91120x (Carmel) board +# Sibyte BCM91120C (CRhine) board +# Sibyte BCM91125C (CRhone) board +# Sibyte BCM91125E (Rhone) board +# Sibyte SWARM board +# +libs-$(CONFIG_SIBYTE_CARMEL) += arch/mips/sibyte/swarm/ +load-$(CONFIG_SIBYTE_CARMEL) := 0x80100000 +libs-$(CONFIG_SIBYTE_CRHINE) += arch/mips/sibyte/swarm/ +load-$(CONFIG_SIBYTE_CRHINE) := 0x80100000 +libs-$(CONFIG_SIBYTE_CRHONE) += arch/mips/sibyte/swarm/ +load-$(CONFIG_SIBYTE_CRHONE) := 0x80100000 +libs-$(CONFIG_SIBYTE_RHONE) += arch/mips/sibyte/swarm/ +load-$(CONFIG_SIBYTE_RHONE) := 0x80100000 +libs-$(CONFIG_SIBYTE_SENTOSA) += arch/mips/sibyte/swarm/ +load-$(CONFIG_SIBYTE_SENTOSA) := 0x80100000 +libs-$(CONFIG_SIBYTE_SWARM) += arch/mips/sibyte/swarm/ +load-$(CONFIG_SIBYTE_SWARM) := 0x80100000 + +# +# SNI RM200 PCI +# +core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/ +load-$(CONFIG_SNI_RM200_PCI) += 0x80080000 + +drivers-$(CONFIG_PCI) += arch/mips/pci/ + +# # Some machines like the Indy need 32-bit ELF binaries for booting purposes. # Other need ECOFF, so we build a 32-bit ELF binary for them which we then # convert to ECOFF using elf2ecoff. # -ifdef CONFIG_BOOT_ELF32 -CFLAGS += -Wa,-32 -endif -# # The 64-bit ELF tools are pretty broken so at this time we generate 64-bit # ELF files from 32-bit files by conversion. # -ifdef CONFIG_BOOT_ELF64 -CFLAGS += -Wa,-32 #AS += -64 #LDFLAGS += -m elf64bmip -#LDFLAGS_vmlinux += -T arch/mips64/ld.script.elf64 -endif +cflags-$(CONFIG_BOOT_ELF32) += -Wa,-32 +cflags-$(CONFIG_BOOT_ELF64) += -Wa,-32 -LDFLAGS_vmlinux += -Ttext $(LOADADDR) +GRRR=-Wa,-mgp64 +cflags-$(CONFIG_BOOT_ELF32) += -Wa,-32 $(call check_warning, $(GRRR),) +cflags-$(CONFIG_BOOT_ELF64) += -Wa,-32 $(call check_warning, $(GRRR),) -head-y := arch/mips64/kernel/head.o arch/mips64/kernel/init_task.o +AFLAGS_vmlinux.lds.o := -imacros $(srctree)/include/asm-mips64/sn/mapped_kernel.h \ + -D"LOADADDR=$(load-y)" -SUBDIRS := arch/mips64/tools $(SUBDIRS) -core-y += arch/mips64/kernel/ arch/mips64/mm/ -libs-y += arch/mips64/lib/lib.a +AFLAGS += $(cflags-y) +CFLAGS += $(cflags-y) -MAKEBOOT = $(MAKE) -C arch/$(ARCH)/boot +LDFLAGS += --oformat $(32bit-bfd) +LDFLAGS_BLOB := --format binary --oformat $(64bit-bfd) -ifdef CONFIG_CPU_LITTLE_ENDIAN -64bit-bfd = elf64-littlemips -else -64bit-bfd = elf64-bigmips -endif +head-y := arch/mips64/kernel/head.o arch/mips64/kernel/init_task.o + +libs-y += arch/mips64/lib/ +core-y += arch/mips64/kernel/ arch/mips64/mm/ arch/mips/math-emu/ -AFLAGS_vmlinux.lds.o := -imacros $(srctree)/include/asm-mips64/sn/mapped_kernel.h +MAKEBOOT = $(MAKE) -C arch/$(ARCH)/boot ifdef CONFIG_MAPPED_KERNEL vmlinux.64: vmlinux @@ -152,18 +275,59 @@ vmlinux.64: vmlinux $(OBJCOPY) -O $(64bit-bfd) --change-addresses=0xa7ffffff80000000 $< $@ endif -zImage: vmlinux - @$(MAKEBOOT) zImage +makeboot =$(Q)$(MAKE) -f scripts/Makefile.build obj=arch/mips/boot $(1) -compressed: zImage +# +# SNI firmware is f*cked in interesting ways ... +# +ifdef CONFIG_SNI_RM200_PCI +all: vmlinux.rm200 +endif + +vmlinux.ecoff vmlinux.rm200: vmlinux + +@$(call makeboot,$@) -zdisk: vmlinux - @$(MAKEBOOT) zdisk +CLEAN_FILES += vmlinux.ecoff \ + vmlinux.rm200.tmp \ + vmlinux.rm200 archclean: - @$(MAKEBOOT) clean - $(MAKE) -C arch/$(ARCH)/tools clean + @$(MAKE) -f scripts/Makefile.clean obj=arch/mips/boot + @$(MAKE) -f scripts/Makefile.clean obj=arch/mips/baget + @$(MAKE) -f scripts/Makefile.clean obj=arch/mips/lasat archmrproper: @$(MAKEBOOT) mrproper - $(MAKE) -C arch/$(ARCH)/tools mrproper + +# Generate -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "ieee754.h" - -/* Strap kernel emulator for full MIPS IV emulation */ - -#ifdef __mips -#undef __mips -#endif -#define __mips 4 - -typedef void *vaddr_t; - -/* Function which emulates the instruction in a branch delay slot. */ - -static int mips_dsemul(struct pt_regs *, mips_instruction, vaddr_t); - -/* Function which emulates a floating point instruction. */ - -static int fpu_emu(struct pt_regs *, struct mips_fpu_soft_struct *, - mips_instruction); - -#if __mips >= 4 && __mips != 32 -static int fpux_emu(struct pt_regs *, - struct mips_fpu_soft_struct *, mips_instruction); -#endif - -/* Further private data for which no space exists in mips_fpu_soft_struct */ - -struct mips_fpu_emulator_private fpuemuprivate; - -/* Control registers */ - -#define FPCREG_RID 0 /* $0 = revision id */ -#define FPCREG_CSR 31 /* $31 = csr */ - -/* Convert Mips rounding mode (0..3) to IEEE library modes. */ -static const unsigned char ieee_rm[4] = { - IEEE754_RN, IEEE754_RZ, IEEE754_RU, IEEE754_RD -}; - -#if __mips >= 4 -/* convert condition code register number to csr bit */ -static const unsigned int fpucondbit[8] = { - FPU_CSR_COND0, - FPU_CSR_COND1, - FPU_CSR_COND2, - FPU_CSR_COND3, - FPU_CSR_COND4, - FPU_CSR_COND5, - FPU_CSR_COND6, - FPU_CSR_COND7 -}; -#endif - - - -/* - * Redundant with logic already in kernel/branch.c, - * embedded in compute_return_epc. At some point, - * a single subroutine should be used across both - * modules. - */ -static int isBranchInstr(mips_instruction * i) -{ - switch (MIPSInst_OPCODE(*i)) { - case spec_op: - switch (MIPSInst_FUNC(*i)) { - case jalr_op: - case jr_op: - return 1; - } - break; - - case bcond_op: - switch (MIPSInst_RT(*i)) { - case bltz_op: - case bgez_op: - case bltzl_op: - case bgezl_op: - case bltzal_op: - case bgezal_op: - case bltzall_op: - case bgezall_op: - return 1; - } - break; - - case j_op: - case jal_op: - case jalx_op: - case beq_op: - case bne_op: - case blez_op: - case bgtz_op: - case beql_op: - case bnel_op: - case blezl_op: - case bgtzl_op: - return 1; - - case cop0_op: - case cop1_op: - case cop2_op: - case cop1x_op: - if (MIPSInst_RS(*i) == bc_op) - return 1; - break; - } - - return 0; -} - -#define REG_TO_VA (vaddr_t) -#define VA_TO_REG (unsigned long) - -static unsigned long -mips_get_word(struct pt_regs *xcp, void *va, int *perr) -{ - unsigned long temp; - - if (!user_mode(xcp)) { - *perr = 0; - return (*(unsigned long *) va); - } else { - /* Use kernel get_user() macro */ - *perr = (int) get_user(temp, (unsigned long *) va); - return temp; - } -} - -static unsigned long long -mips_get_dword(struct pt_regs *xcp, void *va, int *perr) -{ - unsigned long long temp; - - if (!user_mode(xcp)) { - *perr = 0; - return (*(unsigned long long *) va); - } else { - /* Use kernel get_user() macro */ - *perr = (int) get_user(temp, (unsigned long long *) va); - return temp; - } -} - -static int mips_put_word(struct pt_regs *xcp, void *va, unsigned long val) -{ - if (!user_mode(xcp)) { - *(unsigned long *) va = val; - return 0; - } else { - /* Use kernel get_user() macro */ - return (int) put_user(val, (unsigned long *) va); - } -} - -static int mips_put_dword(struct pt_regs *xcp, void *va, long long val) -{ - if (!user_mode(xcp)) { - *(unsigned long long *) va = val; - return 0; - } else { - /* Use kernel get_user() macro */ - return (int) put_user(val, (unsigned long long *) va); - } -} - - -/* - * In the Linux kernel, we support selection of FPR format on the - * basis of the Status.FR bit. This does imply that, if a full 32 - * FPRs are desired, there needs to be a flip-flop that can be written - * to one at that bit position. In any case, normal MIPS ABI uses - * only the even FPRs (Status.FR = 0). - */ - -#define CP0_STATUS_FR_SUPPORT - -/* - * Emulate the single floating point instruction pointed at by EPC. - * Two instructions if the instruction is in a branch delay slot. - */ - -static int -cop1Emulate(int xcptno, struct pt_regs *xcp, - struct mips_fpu_soft_struct *ctx) -{ - mips_instruction ir; - vaddr_t emulpc; - vaddr_t contpc; - unsigned int cond; - int err = 0; - - - ir = mips_get_word(xcp, REG_TO_VA xcp->cp0_epc, &err); - if (err) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } - - /* XXX NEC Vr54xx bug workaround */ - if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir)) - xcp->cp0_cause &= ~CAUSEF_BD; - - if (xcp->cp0_cause & CAUSEF_BD) { - /* - * The instruction to be emulated is in a branch delay slot - * which means that we have to emulate the branch instruction - * BEFORE we do the cop1 instruction. - * - * This branch could be a COP1 branch, but in that case we - * would have had a trap for that instruction, and would not - * come through this route. - * - * Linux MIPS branch emulator operates on context, updating the - * cp0_epc. - */ - emulpc = REG_TO_VA(xcp->cp0_epc + 4); /* Snapshot emulation target */ - - if (__compute_return_epc(xcp)) { -#ifdef CP1DBG - printk("failed to emulate branch at %p\n", - REG_TO_VA(xcp->cp0_epc)); -#endif - return SIGILL;; - } - ir = mips_get_word(xcp, emulpc, &err); - if (err) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } - contpc = REG_TO_VA xcp->cp0_epc; - } else { - emulpc = REG_TO_VA xcp->cp0_epc; - contpc = REG_TO_VA xcp->cp0_epc + 4; - } - - emul: - fpuemuprivate.stats.emulated++; - switch (MIPSInst_OPCODE(ir)) { -#ifdef CP0_STATUS_FR_SUPPORT - /* R4000+ 64-bit fpu registers */ -#ifndef SINGLE_ONLY_FPU - case ldc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - int ft = MIPSInst_RT(ir); - if (!(xcp->cp0_status & ST0_FR)) - ft &= ~1; - ctx->regs[ft] = mips_get_dword(xcp, va, &err); - fpuemuprivate.stats.loads++; - if (err) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } - } - break; - - case sdc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - int ft = MIPSInst_RT(ir); - if (!(xcp->cp0_status & ST0_FR)) - ft &= ~1; - fpuemuprivate.stats.stores++; - if (mips_put_dword(xcp, va, ctx->regs[ft])) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } - } - break; -#endif - - case lwc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - fpureg_t val; - int ft = MIPSInst_RT(ir); - fpuemuprivate.stats.loads++; - val = mips_get_word(xcp, va, &err); - if (err) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } - if (xcp->cp0_status & ST0_FR) { - /* load whole register */ - ctx->regs[ft] = val; - } else if (ft & 1) { - /* load to m.s. 32 bits */ -#ifdef SINGLE_ONLY_FPU - /* illegal register in single-float mode */ - return SIGILL; -#else - ctx->regs[(ft & ~1)] &= 0xffffffff; - ctx->regs[(ft & ~1)] |= val << 32; -#endif - } else { - /* load to l.s. 32 bits */ - ctx->regs[ft] &= ~0xffffffffLL; - ctx->regs[ft] |= val; - } - } - break; - - case swc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - unsigned int val; - int ft = MIPSInst_RT(ir); - fpuemuprivate.stats.stores++; - if (xcp->cp0_status & ST0_FR) { - /* store whole register */ - val = ctx->regs[ft]; - } else if (ft & 1) { -#ifdef SINGLE_ONLY_FPU - /* illegal register in single-float mode */ - return SIGILL; -#else - /* store from m.s. 32 bits */ - val = ctx->regs[(ft & ~1)] >> 32; -#endif - } else { - /* store from l.s. 32 bits */ - val = ctx->regs[ft]; - } - if (mips_put_word(xcp, va, val)) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } - } - break; -#else /* old 32-bit fpu registers */ - case lwc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - ctx->regs[MIPSInst_RT(ir)] = - mips_get_word(xcp, va, &err); - fpuemuprivate.stats.loads++; - if (err) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } - } - break; - - case swc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - fpuemuprivate.stats.stores++; - if (mips_put_word - (xcp, va, ctx->regs[MIPSInst_RT(ir)])) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } - } - break; - case ldc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - unsigned int rt = MIPSInst_RT(ir) & ~1; - int errs = 0; - fpuemuprivate.stats.loads++; -#if (defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN) || defined(__MIPSEB__) - ctx->regs[rt + 1] = - mips_get_word(xcp, va + 0, &err); - errs += err; - ctx->regs[rt + 0] = - mips_get_word(xcp, va + 4, &err); - errs += err; -#else - ctx->regs[rt + 0] = - mips_get_word(xcp, va + 0, &err); - errs += err; - ctx->regs[rt + 1] = - mips_get_word(xcp, va + 4, &err); - errs += err; -#endif - if (err) - return SIGBUS; - } - break; - - case sdc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - unsigned int rt = MIPSInst_RT(ir) & ~1; - fpuemuprivate.stats.stores++; -#if (defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN) || defined(__MIPSEB__) - if (mips_put_word(xcp, va + 0, ctx->regs[rt + 1])) - return SIGBUS; - if (mips_put_word(xcp, va + 4, ctx->regs[rt + 0])) - return SIGBUS; -#else - if (mips_put_word(xcp, va + 0, ctx->regs[rt + 0])) - return SIGBUS; - if (mips_put_word(xcp, va + 4, ctx->regs[rt + 1])) - return SIGBUS; -#endif - } - break; -#endif - - case cop1_op: - switch (MIPSInst_RS(ir)) { - -#ifdef CP0_STATUS_FR_SUPPORT -#if __mips64 && !defined(SINGLE_ONLY_FPU) - case dmfc_op: - /* copregister fs -> gpr[rt] */ - if (MIPSInst_RT(ir) != 0) { - int fs = MIPSInst_RD(ir); - if (!(xcp->cp0_status & ST0_FR)) - fs &= ~1; - xcp->regs[MIPSInst_RT(ir)] = ctx->regs[fs]; - } - break; - - case dmtc_op: - /* copregister fs <- rt */ - { - fpureg_t value; - int fs = MIPSInst_RD(ir); - if (!(xcp->cp0_status & ST0_FR)) - fs &= ~1; - value = - (MIPSInst_RT(ir) == - 0) ? 0 : xcp->regs[MIPSInst_RT(ir)]; - ctx->regs[fs] = value; - } - break; -#endif - - case mfc_op: - /* copregister rd -> gpr[rt] */ - if (MIPSInst_RT(ir) != 0) { - /* default value from l.s. 32 bits */ - int value = ctx->regs[MIPSInst_RD(ir)]; - if (MIPSInst_RD(ir) & 1) { -#ifdef SINGLE_ONLY_FPU - /* illegal register in single-float mode */ - return SIGILL; -#else - if (!(xcp->cp0_status & ST0_FR)) { - /* move from m.s. 32 bits */ - value = - ctx-> - regs[MIPSInst_RD(ir) & - ~1] >> 32; - } -#endif - } - xcp->regs[MIPSInst_RT(ir)] = value; - } - break; - - case mtc_op: - /* copregister rd <- rt */ - { - fpureg_t value; - if (MIPSInst_RT(ir) == 0) - value = 0; - else - value = - (unsigned int) xcp-> - regs[MIPSInst_RT(ir)]; - if (MIPSInst_RD(ir) & 1) { -#ifdef SINGLE_ONLY_FPU - /* illegal register in single-float mode */ - return SIGILL; -#else - if (!(xcp->cp0_status & ST0_FR)) { - /* move to m.s. 32 bits */ - ctx-> - regs[ - (MIPSInst_RD(ir) & - ~1)] &= - 0xffffffff; - ctx-> - regs[ - (MIPSInst_RD(ir) & - ~1)] |= - value << 32; - break; - } -#endif - } - /* move to l.s. 32 bits */ - ctx->regs[MIPSInst_RD(ir)] &= - ~0xffffffffLL; - ctx->regs[MIPSInst_RD(ir)] |= value; - } - break; -#else - - case mfc_op: - /* copregister rd -> gpr[rt] */ - if (MIPSInst_RT(ir) != 0) { - unsigned value = - ctx->regs[MIPSInst_RD(ir)]; - xcp->regs[MIPSInst_RT(ir)] = value; - } - break; - - case mtc_op: - /* copregister rd <- rt */ - { - unsigned value; - value = - (MIPSInst_RT(ir) == - 0) ? 0 : xcp->regs[MIPSInst_RT(ir)]; - ctx->regs[MIPSInst_RD(ir)] = value; - } - break; -#endif - - case cfc_op: - /* cop control register rd -> gpr[rt] */ - { - unsigned value; - - if (MIPSInst_RD(ir) == FPCREG_CSR) { - value = ctx->sr; -#ifdef CSRTRACE - printk - ("%p gpr[%d]<-csr=%08x\n", - REG_TO_VA(xcp->cp0_epc), - MIPSInst_RT(ir), value); -#endif - } else if (MIPSInst_RD(ir) == FPCREG_RID) - value = 0; - else - value = 0; - if (MIPSInst_RT(ir)) - xcp->regs[MIPSInst_RT(ir)] = value; - } - break; - - case ctc_op: - /* copregister rd <- rt */ - { - unsigned value; - - if (MIPSInst_RT(ir) == 0) - value = 0; - else - value = xcp->regs[MIPSInst_RT(ir)]; - - /* we only have one writable control reg - */ - if (MIPSInst_RD(ir) == FPCREG_CSR) { -#ifdef CSRTRACE - printk - ("%p gpr[%d]->csr=%08x\n", - REG_TO_VA(xcp->cp0_epc), - MIPSInst_RT(ir), value); -#endif - ctx->sr = value; - /* copy new rounding mode to ieee library state! */ - ieee754_csr.rm = - ieee_rm[value & 0x3]; - } - } - break; - - case bc_op: - if (xcp->cp0_cause & CAUSEF_BD) { - return SIGILL; - } - { - int likely = 0; - -#if __mips >= 4 - cond = - ctx-> - sr & fpucondbit[MIPSInst_RT(ir) >> 2]; -#else - cond = ctx->sr & FPU_CSR_COND; -#endif - switch (MIPSInst_RT(ir) & 3) { - case bcfl_op: - likely = 1; - case bcf_op: - cond = !cond; - break; - case bctl_op: - likely = 1; - case bct_op: - break; - default: - /* thats an illegal instruction */ - return SIGILL; - } - - xcp->cp0_cause |= CAUSEF_BD; - if (cond) { - /* branch taken: emulate dslot instruction */ - xcp->cp0_epc += 4; - contpc = - REG_TO_VA xcp->cp0_epc + - (MIPSInst_SIMM(ir) << 2); - - ir = - mips_get_word(xcp, - REG_TO_VA(xcp-> - cp0_epc), - &err); - if (err) { - fpuemuprivate.stats. - errors++; - return SIGBUS; - } - - switch (MIPSInst_OPCODE(ir)) { - case lwc1_op: - case swc1_op: -#if (__mips >= 2 || __mips64) && !defined(SINGLE_ONLY_FPU) - case ldc1_op: - case sdc1_op: -#endif - case cop1_op: -#if __mips >= 4 && __mips != 32 - case cop1x_op: -#endif - /* its one of ours */ - goto emul; -#if __mips >= 4 - case spec_op: - if (MIPSInst_FUNC(ir) == - movc_op) goto emul; - break; -#endif - } - - /* single step the non-cp1 instruction in the dslot */ - return mips_dsemul(xcp, ir, contpc); - } else { - /* branch not taken */ - if (likely) - /* branch likely nullifies dslot if not taken */ - xcp->cp0_epc += 4; - /* else continue & execute dslot as normal insn */ - } - } - break; - - default: - if (!(MIPSInst_RS(ir) & 0x10)) { - return SIGILL; - } - /* a real fpu computation instruction */ - { - int sig; - if ((sig = fpu_emu(xcp, ctx, ir))) - return sig; - } - } - break; - -#if __mips >= 4 && __mips != 32 - case cop1x_op: - { - int sig; - if ((sig = fpux_emu(xcp, ctx, ir))) - return sig; - } - break; -#endif - -#if __mips >= 4 - case spec_op: - if (MIPSInst_FUNC(ir) != movc_op) - return SIGILL; - cond = fpucondbit[MIPSInst_RT(ir) >> 2]; - if (((ctx->sr & cond) != 0) != - ((MIPSInst_RT(ir) & 1) != 0)) return 0; - xcp->regs[MIPSInst_RD(ir)] = xcp->regs[MIPSInst_RS(ir)]; - break; -#endif - - default: - return SIGILL; - } - - /* we did it !! */ - xcp->cp0_epc = VA_TO_REG(contpc); - xcp->cp0_cause &= ~CAUSEF_BD; - return 0; -} - -/* - * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when - * we have to emulate the instruction in a COP1 branch delay slot. Do - * not change cp0_epc due to the instruction - * - * According to the spec: - * 1) it shouldnt be a branch :-) - * 2) it can be a COP instruction :-( - * 3) if we are tring to run a protected memory space we must take - * special care on memory access instructions :-( - */ - -/* - * "Trampoline" return routine to catch exception following - * execution of delay-slot instruction execution. - */ - -int do_dsemulret(struct pt_regs *xcp) -{ -#ifdef DSEMUL_TRACE - printk("desemulret\n"); -#endif - /* Set EPC to return to post-branch instruction */ - xcp->cp0_epc = current->thread.dsemul_epc; - /* - * Clear the state that got us here. - */ - current->thread.dsemul_aerpc = (unsigned long) 0; - - return 0; -} - - -#define AdELOAD 0x8c000001 /* lw $0,1($0) */ - -static int -mips_dsemul(struct pt_regs *xcp, mips_instruction ir, vaddr_t cpc) -{ - mips_instruction *dsemul_insns; - mips_instruction forcetrap; - extern asmlinkage void handle_dsemulret(void); - - if (ir == 0) { /* a nop is easy */ - xcp->cp0_epc = VA_TO_REG(cpc); - return 0; - } -#ifdef DSEMUL_TRACE - printk("desemul %p %p\n", REG_TO_VA(xcp->cp0_epc), cpc); -#endif - - /* - * The strategy is to push the instruction onto the user stack - * and put a trap after it which we can catch and jump to - * the required address any alternative apart from full - * instruction emulation!!. - */ - dsemul_insns = (mips_instruction *) (xcp->regs[29] & ~3); - dsemul_insns -= 3; /* Two instructions, plus one for luck ;-) */ - /* Verify that the stack pointer is not competely insane */ - if (verify_area - (VERIFY_WRITE, dsemul_insns, sizeof(mips_instruction) * 2)) - return SIGBUS; - - if (mips_put_word(xcp, &dsemul_insns[0], ir)) { - fpuemuprivate.stats.errors++; - return (SIGBUS); - } - - /* - * Algorithmics used a system call instruction, and - * borrowed that vector. MIPS/Linux version is a bit - * more heavyweight in the interests of portability and - * multiprocessor support. We flag the thread for special - * handling in the unaligned access handler and force an - * address error excpetion. - */ - - /* If one is *really* paranoid, one tests for a bad stack pointer */ - if ((xcp->regs[29] & 0x3) == 0x3) - forcetrap = AdELOAD - 1; - else - forcetrap = AdELOAD; - - if (mips_put_word(xcp, &dsemul_insns[1], forcetrap)) { - fpuemuprivate.stats.errors++; - return (SIGBUS); - } - - /* Set thread state to catch and handle the exception */ - current->thread.dsemul_epc = (unsigned long) cpc; - current->thread.dsemul_aerpc = (unsigned long) &dsemul_insns[1]; - xcp->cp0_epc = VA_TO_REG & dsemul_insns[0]; - flush_cache_sigtramp((unsigned long) dsemul_insns); - - return SIGILL; /* force out of emulation loop */ -} - -/* - * Conversion table from MIPS compare ops 48-63 - * cond = ieee754dp_cmp(x,y,IEEE754_UN); - */ -static const unsigned char cmptab[8] = { - 0, /* cmp_0 (sig) cmp_sf */ - IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ - IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ - IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ - IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ - IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ - IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ - IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ -}; - -#define SIFROMREG(si,x) ((si) = ctx->regs[x]) -#define SITOREG(si,x) (ctx->regs[x] = (int)(si)) - -#if __mips64 && !defined(SINGLE_ONLY_FPU) -#define DIFROMREG(di,x) ((di) = ctx->regs[x]) -#define DITOREG(di,x) (ctx->regs[x] = (di)) -#endif - -#define SPFROMREG(sp,x) ((sp).bits = ctx->regs[x]) -#define SPTOREG(sp,x) (ctx->regs[x] = (sp).bits) - -#ifdef CP0_STATUS_FR_SUPPORT -#define DPFROMREG(dp,x) ((dp).bits = \ - ctx->regs[(xcp->cp0_status & ST0_FR) ? x : (x & ~1)]) -#define DPTOREG(dp,x) (ctx->regs[(xcp->cp0_status & ST0_FR) ? x : (x & ~1)]\ - = (dp).bits) -#else -/* Beware: MIPS COP1 doubles are always little_word endian in registers */ -#define DPFROMREG(dp,x) \ - ((dp).bits = ((unsigned long long)ctx->regs[(x)+1] << 32) | ctx->regs[x]) -#define DPTOREG(dp,x) \ - (ctx->regs[x] = (dp).bits, ctx->regs[(x)+1] = (dp).bits >> 32) -#endif - -#if __mips >= 4 && __mips != 32 - -/* - * Additional MIPS4 instructions - */ - -static ieee754dp fpemu_dp_recip(ieee754dp d) -{ - return ieee754dp_div(ieee754dp_one(0), d); -} - -static ieee754dp fpemu_dp_rsqrt(ieee754dp d) -{ - return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); -} - -static ieee754sp fpemu_sp_recip(ieee754sp s) -{ - return ieee754sp_div(ieee754sp_one(0), s); -} - -static ieee754sp fpemu_sp_rsqrt(ieee754sp s) -{ - return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); -} - - -static ieee754dp fpemu_dp_madd(ieee754dp r, ieee754dp s, ieee754dp t) -{ - return ieee754dp_add(ieee754dp_mul(s, t), r); -} - -static ieee754dp fpemu_dp_msub(ieee754dp r, ieee754dp s, ieee754dp t) -{ - return ieee754dp_sub(ieee754dp_mul(s, t), r); -} - -static ieee754dp fpemu_dp_nmadd(ieee754dp r, ieee754dp s, ieee754dp t) -{ - return ieee754dp_neg(ieee754dp_add(ieee754dp_mul(s, t), r)); -} - -static ieee754dp fpemu_dp_nmsub(ieee754dp r, ieee754dp s, ieee754dp t) -{ - return ieee754dp_neg(ieee754dp_sub(ieee754dp_mul(s, t), r)); -} - - -static ieee754sp fpemu_sp_madd(ieee754sp r, ieee754sp s, ieee754sp t) -{ - return ieee754sp_add(ieee754sp_mul(s, t), r); -} - -static ieee754sp fpemu_sp_msub(ieee754sp r, ieee754sp s, ieee754sp t) -{ - return ieee754sp_sub(ieee754sp_mul(s, t), r); -} - -static ieee754sp fpemu_sp_nmadd(ieee754sp r, ieee754sp s, ieee754sp t) -{ - return ieee754sp_neg(ieee754sp_add(ieee754sp_mul(s, t), r)); -} - -static ieee754sp fpemu_sp_nmsub(ieee754sp r, ieee754sp s, ieee754sp t) -{ - return ieee754sp_neg(ieee754sp_sub(ieee754sp_mul(s, t), r)); -} - -static int -fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, - mips_instruction ir) -{ - unsigned rcsr = 0; /* resulting csr */ - - fpuemuprivate.stats.cp1xops++; - - switch (MIPSInst_FMA_FFMT(ir)) { - case s_fmt: /* 0 */ - { - ieee754sp(*handler) (ieee754sp, ieee754sp, - ieee754sp); - ieee754sp fd, fr, fs, ft; - - switch (MIPSInst_FUNC(ir)) { - case lwxc1_op: - { - void *va = - REG_TO_VA(xcp-> - regs[MIPSInst_FR(ir)] - + - xcp-> - regs[MIPSInst_FT - (ir)]); - fpureg_t val; - int err = 0; - val = mips_get_word(xcp, va, &err); - if (err) { - fpuemuprivate.stats. - errors++; - return SIGBUS; - } - if (xcp->cp0_status & ST0_FR) { - /* load whole register */ - ctx-> - regs[MIPSInst_FD(ir)] = - val; - } else if (MIPSInst_FD(ir) & 1) { - /* load to m.s. 32 bits */ -#if defined(SINGLE_ONLY_FPU) - /* illegal register in single-float mode */ - return SIGILL; -#else - ctx-> - regs[ - (MIPSInst_FD(ir) & - ~1)] &= - 0xffffffff; - ctx-> - regs[ - (MIPSInst_FD(ir) & - ~1)] |= - val << 32; -#endif - } else { - /* load to l.s. 32 bits */ - ctx-> - regs[MIPSInst_FD(ir)] - &= ~0xffffffffLL; - ctx-> - regs[MIPSInst_FD(ir)] - |= val; - } - } - break; - - case swxc1_op: - { - void *va = - REG_TO_VA(xcp-> - regs[MIPSInst_FR(ir)] - + - xcp-> - regs[MIPSInst_FT - (ir)]); - unsigned int val; - if (xcp->cp0_status & ST0_FR) { - /* store whole register */ - val = - ctx-> - regs[MIPSInst_FS(ir)]; - } else if (MIPSInst_FS(ir) & 1) { -#if defined(SINGLE_ONLY_FPU) - /* illegal register in single-float mode */ - return SIGILL; -#else - /* store from m.s. 32 bits */ - val = - ctx-> - regs[ - (MIPSInst_FS(ir) & - ~1)] >> 32; -#endif - } else { - /* store from l.s. 32 bits */ - val = - ctx-> - regs[MIPSInst_FS(ir)]; - } - if (mips_put_word(xcp, va, val)) { - fpuemuprivate.stats. - errors++; - return SIGBUS; - } - } - break; - - case madd_s_op: - handler = fpemu_sp_madd; - goto scoptop; - case msub_s_op: - handler = fpemu_sp_msub; - goto scoptop; - case nmadd_s_op: - handler = fpemu_sp_nmadd; - goto scoptop; - case nmsub_s_op: - handler = fpemu_sp_nmsub; - goto scoptop; - - scoptop: - SPFROMREG(fr, MIPSInst_FR(ir)); - SPFROMREG(fs, MIPSInst_FS(ir)); - SPFROMREG(ft, MIPSInst_FT(ir)); - fd = (*handler) (fr, fs, ft); - SPTOREG(fd, MIPSInst_FD(ir)); - - copcsr: - if (ieee754_cxtest(IEEE754_INEXACT)) - rcsr |= - FPU_CSR_INE_X | FPU_CSR_INE_S; - if (ieee754_cxtest(IEEE754_UNDERFLOW)) - rcsr |= - FPU_CSR_UDF_X | FPU_CSR_UDF_S; - if (ieee754_cxtest(IEEE754_OVERFLOW)) - rcsr |= - FPU_CSR_OVF_X | FPU_CSR_OVF_S; - if (ieee754_cxtest - (IEEE754_INVALID_OPERATION)) rcsr |= - FPU_CSR_INV_X | FPU_CSR_INV_S; - - ctx->sr = - (ctx->sr & ~FPU_CSR_ALL_X) | rcsr; - if ((ctx->sr >> 5) & ctx-> - sr & FPU_CSR_ALL_E) { - /*printk ("SIGFPE: fpu csr = %08x\n",ctx->sr); */ - return SIGFPE; - } - - break; - - default: - return SIGILL; - } - } - break; - -#if !defined(SINGLE_ONLY_FPU) - case d_fmt: /* 1 */ - { - ieee754dp(*handler) (ieee754dp, ieee754dp, - ieee754dp); - ieee754dp fd, fr, fs, ft; - - switch (MIPSInst_FUNC(ir)) { - case ldxc1_op: - { - void *va = - REG_TO_VA(xcp-> - regs[MIPSInst_FR(ir)] - + - xcp-> - regs[MIPSInst_FT - (ir)]); - int err = 0; - ctx->regs[MIPSInst_FD(ir)] = - mips_get_dword(xcp, va, &err); - if (err) { - fpuemuprivate.stats. - errors++; - return SIGBUS; - } - } - break; - - case sdxc1_op: - { - void *va = - REG_TO_VA(xcp-> - regs[MIPSInst_FR(ir)] - + - xcp-> - regs[MIPSInst_FT - (ir)]); - if (mips_put_dword - (xcp, va, - ctx->regs[MIPSInst_FS(ir)])) { - fpuemuprivate.stats. - errors++; - return SIGBUS; - } - } - break; - - case madd_d_op: - handler = fpemu_dp_madd; - goto dcoptop; - case msub_d_op: - handler = fpemu_dp_msub; - goto dcoptop; - case nmadd_d_op: - handler = fpemu_dp_nmadd; - goto dcoptop; - case nmsub_d_op: - handler = fpemu_dp_nmsub; - goto dcoptop; - - dcoptop: - DPFROMREG(fr, MIPSInst_FR(ir)); - DPFROMREG(fs, MIPSInst_FS(ir)); - DPFROMREG(ft, MIPSInst_FT(ir)); - fd = (*handler) (fr, fs, ft); - DPTOREG(fd, MIPSInst_FD(ir)); - goto copcsr; - - default: - return SIGILL; - } - } - break; -#endif - - case 0x7: /* 7 */ - { - if (MIPSInst_FUNC(ir) != pfetch_op) { - return SIGILL; - } - /* ignore prefx operation */ - } - break; - - default: - return SIGILL; - } - - return 0; -} -#endif - - - -/* - * Emulate a single COP1 arithmetic instruction. - */ -static int -fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, - mips_instruction ir) -{ - int rfmt; /* resulting format */ - unsigned rcsr = 0; /* resulting csr */ - unsigned cond; - union { - ieee754dp d; - ieee754sp s; - int w; -#if __mips64 - long long l; -#endif - } rv; /* resulting value */ - - fpuemuprivate.stats.cp1ops++; - switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { - - case s_fmt:{ /* 0 */ - ieee754sp(*handler) (); - - switch (MIPSInst_FUNC(ir)) { - /* binary ops */ - case fadd_op: - handler = ieee754sp_add; - goto scopbop; - case fsub_op: - handler = ieee754sp_sub; - goto scopbop; - case fmul_op: - handler = ieee754sp_mul; - goto scopbop; - case fdiv_op: - handler = ieee754sp_div; - goto scopbop; - - /* unary ops */ -#if __mips >= 2 || __mips64 - case fsqrt_op: - handler = ieee754sp_sqrt; - goto scopuop; -#endif -#if __mips >= 4 && __mips != 32 - case frsqrt_op: - handler = fpemu_sp_rsqrt; - goto scopuop; - case frecip_op: - handler = fpemu_sp_recip; - goto scopuop; -#endif -#if __mips >= 4 - case fmovc_op: - cond = fpucondbit[MIPSInst_FT(ir) >> 2]; - if (((ctx->sr & cond) != 0) != - ((MIPSInst_FT(ir) & 1) != 0)) - return 0; - SPFROMREG(rv.s, MIPSInst_FS(ir)); - break; - case fmovz_op: - if (xcp->regs[MIPSInst_FT(ir)] != 0) - return 0; - SPFROMREG(rv.s, MIPSInst_FS(ir)); - break; - case fmovn_op: - if (xcp->regs[MIPSInst_FT(ir)] == 0) - return 0; - SPFROMREG(rv.s, MIPSInst_FS(ir)); - break; -#endif - case fabs_op: - handler = ieee754sp_abs; - goto scopuop; - case fneg_op: - handler = ieee754sp_neg; - goto scopuop; - case fmov_op: - /* an easy one */ - SPFROMREG(rv.s, MIPSInst_FS(ir)); - break; - /* binary op on handler */ -scopbop: - { - ieee754sp fs, ft; - - SPFROMREG(fs, MIPSInst_FS(ir)); - SPFROMREG(ft, MIPSInst_FT(ir)); - - rv.s = (*handler) (fs, ft); - goto copcsr; - } -scopuop: - { - ieee754sp fs; - - SPFROMREG(fs, MIPSInst_FS(ir)); - rv.s = (*handler) (fs); - goto copcsr; - } -copcsr: - if (ieee754_cxtest(IEEE754_INEXACT)) - rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; - if (ieee754_cxtest(IEEE754_UNDERFLOW)) - rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; - if (ieee754_cxtest(IEEE754_OVERFLOW)) - rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; - if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) - rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; - if (ieee754_cxtest - (IEEE754_INVALID_OPERATION)) rcsr |= - FPU_CSR_INV_X | FPU_CSR_INV_S; - break; - - /* unary conv ops */ - case fcvts_op: - return SIGILL; /* not defined */ - case fcvtd_op: -#if defined(SINGLE_ONLY_FPU) - return SIGILL; /* not defined */ -#else - { - ieee754sp fs; - - SPFROMREG(fs, MIPSInst_FS(ir)); - rv.d = ieee754dp_fsp(fs); - rfmt = d_fmt; - goto copcsr; - } -#endif - case fcvtw_op: - { - ieee754sp fs; - - SPFROMREG(fs, MIPSInst_FS(ir)); - rv.w = ieee754sp_tint(fs); - rfmt = w_fmt; - goto copcsr; - } - -#if __mips >= 2 || __mips64 - case fround_op: - case ftrunc_op: - case fceil_op: - case ffloor_op: - { - unsigned int oldrm = ieee754_csr.rm; - ieee754sp fs; - - SPFROMREG(fs, MIPSInst_FS(ir)); - ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; - rv.w = ieee754sp_tint(fs); - ieee754_csr.rm = oldrm; - rfmt = w_fmt; - goto copcsr; - } -#endif /* __mips >= 2 */ - -#if __mips64 && !defined(SINGLE_ONLY_FPU) - case fcvtl_op: - { - ieee754sp fs; - - SPFROMREG(fs, MIPSInst_FS(ir)); - rv.l = ieee754sp_tlong(fs); - rfmt = l_fmt; - goto copcsr; - } - - case froundl_op: - case ftruncl_op: - case fceill_op: - case ffloorl_op: - { - unsigned int oldrm = ieee754_csr.rm; - ieee754sp fs; - - SPFROMREG(fs, MIPSInst_FS(ir)); - ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; - rv.l = ieee754sp_tlong(fs); - ieee754_csr.rm = oldrm; - rfmt = l_fmt; - goto copcsr; - } -#endif /* __mips64 && !fpu(single) */ - - default: - if (MIPSInst_FUNC(ir) >= fcmp_op) { - unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; - ieee754sp fs, ft; - - SPFROMREG(fs, MIPSInst_FS(ir)); - SPFROMREG(ft, MIPSInst_FT(ir)); - rv.w = ieee754sp_cmp(fs, ft, cmptab[cmpop & 0x7]); - rfmt = -1; - if ((cmpop & 0x8) && ieee754_cxtest(IEEE754_INVALID_OPERATION)) - rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; - } else { - return SIGILL; - } - break; - } - break; - } - -#if !defined(SINGLE_ONLY_FPU) - case d_fmt: { - ieee754dp(*handler) (); - - switch (MIPSInst_FUNC(ir)) { - /* binary ops */ - case fadd_op: - handler = ieee754dp_add; - goto dcopbop; - case fsub_op: - handler = ieee754dp_sub; - goto dcopbop; - case fmul_op: - handler = ieee754dp_mul; - goto dcopbop; - case fdiv_op: - handler = ieee754dp_div; - goto dcopbop; - - /* unary ops */ -#if __mips >= 2 || __mips64 - case fsqrt_op: - handler = ieee754dp_sqrt; - goto dcopuop; -#endif -#if __mips >= 4 && __mips != 32 - case frsqrt_op: - handler = fpemu_dp_rsqrt; - goto dcopuop; - case frecip_op: - handler = fpemu_dp_recip; - goto dcopuop; -#endif -#if __mips >= 4 - case fmovc_op: - cond = fpucondbit[MIPSInst_FT(ir) >> 2]; - if (((ctx->sr & cond) != 0) != ((MIPSInst_FT(ir) & 1) != 0)) - return 0; - DPFROMREG(rv.d, MIPSInst_FS(ir)); - break; - case fmovz_op: - if (xcp->regs[MIPSInst_FT(ir)] != 0) - return 0; - DPFROMREG(rv.d, MIPSInst_FS(ir)); - break; - case fmovn_op: - if (xcp->regs[MIPSInst_FT(ir)] == 0) - return 0; - DPFROMREG(rv.d, MIPSInst_FS(ir)); - break; -#endif - case fabs_op: - handler = ieee754dp_abs; - goto dcopuop; - case fneg_op: - handler = ieee754dp_neg; - goto dcopuop; - case fmov_op: - /* an easy one */ - DPFROMREG(rv.d, MIPSInst_FS(ir)); - break; - - /* binary op on handler */ -dcopbop: - { - ieee754dp fs, ft; - - DPFROMREG(fs, MIPSInst_FS(ir)); - DPFROMREG(ft, MIPSInst_FT(ir)); - - rv.d = (*handler) (fs, ft); - goto copcsr; - } -dcopuop: - { - ieee754dp fs; - - DPFROMREG(fs, MIPSInst_FS(ir)); - rv.d = (*handler) (fs); - goto copcsr; - } - - /* unary conv ops */ - case fcvts_op: - { - ieee754dp fs; - - DPFROMREG(fs, MIPSInst_FS(ir)); - rv.s = ieee754sp_fdp(fs); - rfmt = s_fmt; - goto copcsr; - } - case fcvtd_op: - return SIGILL; /* not defined */ - case fcvtw_op: - { - ieee754dp fs; - - DPFROMREG(fs, MIPSInst_FS(ir)); - rv.w = ieee754dp_tint(fs); /* wrong */ - rfmt = w_fmt; - goto copcsr; - } - -#if __mips >= 2 || __mips64 - case fround_op: - case ftrunc_op: - case fceil_op: - case ffloor_op: - { - unsigned int oldrm = ieee754_csr.rm; - ieee754dp fs; - - DPFROMREG(fs, MIPSInst_FS(ir)); - ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; - rv.w = ieee754dp_tint(fs); - ieee754_csr.rm = oldrm; - rfmt = w_fmt; - goto copcsr; - } -#endif - -#if __mips64 && !defined(SINGLE_ONLY_FPU) - case fcvtl_op: - { - ieee754dp fs; - - DPFROMREG(fs, MIPSInst_FS(ir)); - rv.l = ieee754dp_tlong(fs); - rfmt = l_fmt; - goto copcsr; - } - - case froundl_op: - case ftruncl_op: - case fceill_op: - case ffloorl_op: - { - unsigned int oldrm = ieee754_csr.rm; - ieee754dp fs; - - DPFROMREG(fs, MIPSInst_FS(ir)); - ieee754_csr.rm = ieee_rm[MIPSInst_FUNC(ir) & 0x3]; - rv.l = ieee754dp_tlong(fs); - ieee754_csr.rm = oldrm; - rfmt = l_fmt; - goto copcsr; - } -#endif /* __mips >= 3 && !fpu(single) */ - - default: - if (MIPSInst_FUNC(ir) >= fcmp_op) { - unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; - ieee754dp fs, ft; - - DPFROMREG(fs, MIPSInst_FS(ir)); - DPFROMREG(ft, MIPSInst_FT(ir)); - rv.w = ieee754dp_cmp(fs, ft, cmptab[cmpop & 0x7]); - rfmt = -1; - if ((cmpop & 0x8) && ieee754_cxtest (IEEE754_INVALID_OPERATION)) - rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; - } else { - return SIGILL; - } - break; - } - break; - } -#endif /* !defined(SINGLE_ONLY_FPU) */ - - case w_fmt: { - switch (MIPSInst_FUNC(ir)) { - case fcvts_op: - /* convert word to single precision real */ - rv.s = ieee754sp_fint(ctx-> regs[MIPSInst_FS(ir)]); - rfmt = s_fmt; - goto copcsr; -#if !defined(SINGLE_ONLY_FPU) - case fcvtd_op: - /* convert word to double precision real */ - rv.d = ieee754dp_fint(ctx-> regs[MIPSInst_FS(ir)]); - rfmt = d_fmt; - goto copcsr; -#endif - default: - return SIGILL; - } - break; - } - -#if __mips64 && !defined(SINGLE_ONLY_FPU) - case l_fmt: { - switch (MIPSInst_FUNC(ir)) { - case fcvts_op: - /* convert long to single precision real */ - rv.s = ieee754sp_flong(ctx-> regs[MIPSInst_FS(ir)]); - rfmt = s_fmt; - goto copcsr; - case fcvtd_op: - /* convert long to double precision real */ - rv.d = ieee754dp_flong(ctx-> regs[MIPSInst_FS(ir)]); - rfmt = d_fmt; - goto copcsr; - default: - return SIGILL; - } - break; - } -#endif - - default: - return SIGILL; - } - - /* - * Update the fpu CSR register for this operation. - * If an exception is required, generate a tidy SIGFPE exception, - * without updating the result register. - * Note: cause exception bits do not accumulate, they are rewritten - * for each op; only the flag/sticky bits accumulate. - */ - ctx->sr = (ctx->sr & ~FPU_CSR_ALL_X) | rcsr; - if ((ctx->sr >> 5) & ctx->sr & FPU_CSR_ALL_E) { - /*printk ("SIGFPE: fpu csr = %08x\n",ctx->sr); */ - return SIGFPE; - } - - /* - * Now we can safely write the result back to the register file. - */ - switch (rfmt) { - case -1: { -#if __mips >= 4 - cond = fpucondbit[MIPSInst_FD(ir) >> 2]; -#else - cond = FPU_CSR_COND; -#endif - if (rv.w) - ctx->sr |= cond; - else - ctx->sr &= ~cond; - break; - } -#if !defined(SINGLE_ONLY_FPU) - case d_fmt: - DPTOREG(rv.d, MIPSInst_FD(ir)); - break; -#endif - case s_fmt: - SPTOREG(rv.s, MIPSInst_FD(ir)); - break; - case w_fmt: - SITOREG(rv.w, MIPSInst_FD(ir)); - break; -#if __mips64 && !defined(SINGLE_ONLY_FPU) - case l_fmt: - DITOREG(rv.l, MIPSInst_FD(ir)); - break; -#endif - default: - return SIGILL; - } - - return 0; -} - - -/* - * Emulate the floating point instruction at EPC, and continue - * to run until we hit a non-fp instruction, or a backward - * branch. This cuts down dramatically on the per instruction - * exception overhead. - */ -int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp) -{ - struct mips_fpu_soft_struct *ctx = ¤t->thread.fpu.soft; - unsigned long oldepc, prevepc; - unsigned int insn; - int sig = 0; - int err = 0; - - oldepc = xcp->cp0_epc; - do { - cond_resched(); - - prevepc = xcp->cp0_epc; - insn = mips_get_word(xcp, REG_TO_VA(xcp->cp0_epc), &err); - if (err) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } - if (insn != 0) - sig = cop1Emulate(xcptno, xcp, ctx); - else - xcp->cp0_epc += 4; /* skip nops */ - - if (mips_cpu.options & MIPS_CPU_FPU) - break; - } while (xcp->cp0_epc > prevepc && sig == 0); - - /* SIGILL indicates a non-fpu instruction */ - if (sig == SIGILL && xcp->cp0_epc != oldepc) - /* but if epc has advanced, then ignore it */ - sig = 0; - - return sig; -} - - -#ifdef NOTDEF -/* - * Patch up the hardware fpu state when an f.p. exception occurs. - */ -static int cop1Patcher(int xcptno, struct pt_regs *xcp) -{ - struct mips_fpu_soft_struct *ctx = ¤t->thread.fpu.soft; - unsigned sr; - int sig; - - /* reenable Cp1, else fpe_save() will get nested exception */ - sr = mips_bissr(ST0_CU1); - - /* get fpu registers and status, then clear pending exceptions */ - fpe_save(ctx); - fpe_setsr(ctx->sr &= ~FPU_CSR_ALL_X); - - /* get current rounding mode for IEEE library, and emulate insn */ - ieee754_csr.rm = ieee_rm[ctx->sr & 0x3]; - sig = cop1Emulate(xcptno, xcp, ctx); - - /* don't return with f.p. exceptions pending */ - ctx->sr &= ~FPU_CSR_ALL_X; - fpe_restore(ctx); - - mips_setsr(sr); - return sig; -} - -void _cop1_init(int emulate) -{ - extern int _nofpu; - - if (emulate) { - /* - * Install cop1 emulator to handle "coprocessor unusable" exception - */ - xcption(XCPTCPU, cop1Handler); - fpuemuactive = 1; /* tell dbg.c that we are in charge */ - _nofpu = 0; /* tell setjmp() it "has" an fpu */ - } else { - /* - * Install cop1 emulator for floating point exceptions only, - * i.e. denormalised results, underflow, overflow etc, which - * must be emulated in s/w. - */ -#ifdef 1 - /* r4000 or above use dedicate exception */ - xcption(XCPTFPE, cop1Patcher); -#else - /* r3000 et al use interrupt */ - extern int _sbd_getfpuintr(void); - int intno = _sbd_getfpuintr(); - intrupt(intno, cop1Patcher, 0); - mips_bissr(SR_IM0 << intno); -#endif - -#if (#cpu(r4640) || #cpu(r4650)) && !defined(SINGLE_ONLY_FPU) - /* For R4640/R4650 compiled *without* the -msingle-float flag, - then we share responsibility: the h/w handles the single - precision operations, and the trap emulator handles the - double precision. We set fpuemuactive so that dbg.c first - fetches the s/w state before saving the h/w state. */ - fpuemuactive = 1; - { - int i; - /* initialise the unused d.p high order words to be NaN */ - for (i = 0; i < 32; i++) - current->thread.fpu.soft.regs[i] = - 0x7ff80bad00000000LL; - } -#endif /* (r4640 || r4650) && !fpu(single) */ - } -} -#endif - --- linux-2.5.73/arch/mips64/math-emu/dp_add.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,186 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - */ - - -#include "ieee754dp.h" - -ieee754dp ieee754dp_add(ieee754dp x, ieee754dp y) -{ - COMPXDP; - COMPYDP; - - EXPLODEXDP; - EXPLODEYDP; - - CLEARCX; - - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(ieee754dp_bestnan(x, y), "add", x, - y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(y, "add", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754dp_nanxcpt(x, "add", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754dp_bestnan(x, y); - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): - return y; - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF): - return x; - - - /* Inifity handling - */ - - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): - if (xs == ys) - return x; - SETCX(IEEE754_INVALID_OPERATION); - return ieee754dp_xcpt(ieee754dp_indef(), "add", x, y); - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF): - return y; - - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): - return x; - - /* Zero handling - */ - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): - if (xs == ys) - return x; - else - return ieee754dp_zero(ieee754_csr.rm == - IEEE754_RD); - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO): - return x; - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM): - return y; - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM): - DPDNORMX; - - /* FALL THROUGH */ - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM): - DPDNORMY; - break; - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM): - DPDNORMX; - break; - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM): - break; - } - assert(xm & DP_HIDDEN_BIT); - assert(ym & DP_HIDDEN_BIT); - - /* provide guard,round and stick bit space */ - xm <<= 3; - ym <<= 3; - - if (xe > ye) { - /* have to shift y fraction right to align - */ - int s = xe - ye; - ym = XDPSRS(ym, s); - ye += s; - } else if (ye > xe) { - /* have to shift x fraction right to align - */ - int s = ye - xe; - xm = XDPSRS(xm, s); - xe += s; - } - assert(xe == ye); - assert(xe <= DP_EMAX); - - if (xs == ys) { - /* generate 28 bit result of adding two 27 bit numbers - * leaving result in xm,xs,xe - */ - xm = xm + ym; - xe = xe; - xs = xs; - - if (xm >> (DP_MBITS + 1 + 3)) { /* carry out */ - xm = XDPSRS1(xm); - xe++; - } - } else { - if (xm >= ym) { - xm = xm - ym; - xe = xe; - xs = xs; - } else { - xm = ym - xm; - xe = xe; - xs = ys; - } - if (xm == 0) - return ieee754dp_zero(ieee754_csr.rm == - IEEE754_RD); - - /* normalize to rounding precision */ - while ((xm >> (DP_MBITS + 3)) == 0) { - xm <<= 1; - xe--; - } - - } - DPNORMRET2(xs, xe, xm, "add", x, y); -} --- linux-2.5.73/arch/mips64/math-emu/dp_cmp.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,58 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -int ieee754dp_cmp(ieee754dp x, ieee754dp y, int cmp) -{ - CLEARCX; - - if (ieee754dp_isnan(x) || ieee754dp_isnan(y)) { - if (cmp & IEEE754_CUN) - return 1; - if (cmp & (IEEE754_CLT | IEEE754_CGT)) { - if (SETCX(IEEE754_INVALID_OPERATION)) - return ieee754si_xcpt(0, "fcmpf", x); - } - return 0; - } else { - long long int vx = x.bits; - long long int vy = y.bits; - - if (vx < 0) - vx = -vx ^ DP_SIGN_BIT; - if (vy < 0) - vy = -vy ^ DP_SIGN_BIT; - - if (vx < vy) - return (cmp & IEEE754_CLT) != 0; - else if (vx == vy) - return (cmp & IEEE754_CEQ) != 0; - else - return (cmp & IEEE754_CGT) != 0; - } -} --- linux-2.5.73/arch/mips64/math-emu/dp_div.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,160 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -ieee754dp ieee754dp_div(ieee754dp x, ieee754dp y) -{ - COMPXDP; - COMPYDP; - - CLEARCX; - - EXPLODEXDP; - EXPLODEYDP; - - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(ieee754dp_bestnan(x, y), "div", x, - y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(y, "div", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754dp_nanxcpt(x, "div", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754dp_bestnan(x, y); - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): - return y; - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF): - return x; - - - /* Infinity handling - */ - - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): - SETCX(IEEE754_INVALID_OPERATION); - return ieee754dp_xcpt(ieee754dp_indef(), "div", x, y); - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF): - return ieee754dp_zero(xs ^ ys); - - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): - return ieee754dp_inf(xs ^ ys); - - /* Zero handling - */ - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): - SETCX(IEEE754_INVALID_OPERATION); - return ieee754dp_xcpt(ieee754dp_indef(), "div", x, y); - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO): - SETCX(IEEE754_ZERO_DIVIDE); - return ieee754dp_xcpt(ieee754dp_inf(xs ^ ys), "div", x, y); - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM): - return ieee754dp_zero(xs == ys ? 0 : 1); - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM): - DPDNORMX; - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM): - DPDNORMY; - break; - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM): - DPDNORMX; - break; - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM): - break; - } - assert(xm & DP_HIDDEN_BIT); - assert(ym & DP_HIDDEN_BIT); - - /* provide rounding space */ - xm <<= 3; - ym <<= 3; - - { - /* now the dirty work */ - - unsigned long long rm = 0; - int re = xe - ye; - unsigned long long bm; - - for (bm = DP_MBIT(DP_MBITS + 2); bm; bm >>= 1) { - if (xm >= ym) { - xm -= ym; - rm |= bm; - if (xm == 0) - break; - } - xm <<= 1; - } - rm <<= 1; - if (xm) - rm |= 1; /* have remainder, set sticky */ - - assert(rm); - - /* normalise rm to rounding precision ? - */ - while ((rm >> (DP_MBITS + 3)) == 0) { - rm <<= 1; - re--; - } - - DPNORMRET2(xs == ys ? 0 : 1, re, rm, "div", x, y); - } -} --- linux-2.5.73/arch/mips64/math-emu/dp_fint.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,78 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -ieee754dp ieee754dp_fint(int x) -{ - COMPXDP; - - CLEARCX; - - if (x == 0) - return ieee754dp_zero(0); - if (x == 1 || x == -1) - return ieee754dp_one(x < 0); - if (x == 10 || x == -10) - return ieee754dp_ten(x < 0); - - xs = (x < 0); - if (xs) { - if (x == (1 << 31)) - xm = ((unsigned) 1 << 31); /* max neg can't be safely negated */ - else - xm = -x; - } else { - xm = x; - } - -#if 1 - /* normalize - result can never be inexact or overflow */ - xe = DP_MBITS; - while ((xm >> DP_MBITS) == 0) { - xm <<= 1; - xe--; - } - return builddp(xs, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT); -#else - /* normalize */ - xe = DP_MBITS + 3; - while ((xm >> (DP_MBITS + 3)) == 0) { - xm <<= 1; - xe--; - } - DPNORMRET1(xs, xe, xm, "fint", x); -#endif -} - -ieee754dp ieee754dp_funs(unsigned int u) -{ - if ((int) u < 0) - return ieee754dp_add(ieee754dp_1e31(), - ieee754dp_fint(u & ~(1 << 31))); - return ieee754dp_fint(u); -} --- linux-2.5.73/arch/mips64/math-emu/dp_flong.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,76 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -ieee754dp ieee754dp_flong(long long x) -{ - COMPXDP; - - CLEARCX; - - if (x == 0) - return ieee754dp_zero(0); - if (x == 1 || x == -1) - return ieee754dp_one(x < 0); - if (x == 10 || x == -10) - return ieee754dp_ten(x < 0); - - xs = (x < 0); - if (xs) { - if (x == (1ULL << 63)) - xm = (1ULL << 63); /* max neg can't be safely negated */ - else - xm = -x; - } else { - xm = x; - } - - /* normalize */ - xe = DP_MBITS + 3; - if (xm >> (DP_MBITS + 1 + 3)) { - /* shunt out overflow bits */ - while (xm >> (DP_MBITS + 1 + 3)) { - XDPSRSX1(); - } - } else { - /* normalize in grs extended double precision */ - while ((xm >> (DP_MBITS + 3)) == 0) { - xm <<= 1; - xe--; - } - } - DPNORMRET1(xs, xe, xm, "dp_flong", x); -} - -ieee754dp ieee754dp_fulong(unsigned long long u) -{ - if ((long long) u < 0) - return ieee754dp_add(ieee754dp_1e63(), - ieee754dp_flong(u & ~(1ULL << 63))); - return ieee754dp_flong(u); -} --- linux-2.5.73/arch/mips64/math-emu/dp_frexp.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,53 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -/* close to ieeep754dp_logb -*/ -ieee754dp ieee754dp_frexp(ieee754dp x, int *eptr) -{ - COMPXDP; - CLEARCX; - EXPLODEXDP; - - switch (xc) { - case IEEE754_CLASS_SNAN: - case IEEE754_CLASS_QNAN: - case IEEE754_CLASS_INF: - case IEEE754_CLASS_ZERO: - *eptr = 0; - return x; - case IEEE754_CLASS_DNORM: - DPDNORMX; - break; - case IEEE754_CLASS_NORM: - break; - } - *eptr = xe + 1; - return builddp(xs, -1 + DP_EBIAS, xm & ~DP_HIDDEN_BIT); -} --- linux-2.5.73/arch/mips64/math-emu/dp_fsp.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,70 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -ieee754dp ieee754dp_fsp(ieee754sp x) -{ - COMPXSP; - - CLEARCX; - - EXPLODEXSP; - - switch (xc) { - case IEEE754_CLASS_QNAN: - case IEEE754_CLASS_SNAN: - return ieee754dp_nanxcpt(builddp(xs, - DP_EMAX + 1 + DP_EBIAS, - ((unsigned long long) xm - << (DP_MBITS - - SP_MBITS))), "fsp", - x); - case IEEE754_CLASS_INF: - return ieee754dp_inf(xs); - case IEEE754_CLASS_ZERO: - return ieee754dp_zero(xs); - case IEEE754_CLASS_DNORM: - /* normalize */ - while ((xm >> SP_MBITS) == 0) { - xm <<= 1; - xe--; - } - break; - case IEEE754_CLASS_NORM: - break; - } - - /* CANT possibly overflow,underflow, or need rounding - */ - - /* drop the hidden bit */ - xm &= ~SP_HIDDEN_BIT; - - return builddp(xs, xe + DP_EBIAS, - (unsigned long long) xm << (DP_MBITS - SP_MBITS)); -} --- linux-2.5.73/arch/mips64/math-emu/dp_logb.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,54 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -ieee754dp ieee754dp_logb(ieee754dp x) -{ - COMPXDP; - - CLEARCX; - - EXPLODEXDP; - - switch (xc) { - case IEEE754_CLASS_SNAN: - return ieee754dp_nanxcpt(x, "logb", x); - case IEEE754_CLASS_QNAN: - return x; - case IEEE754_CLASS_INF: - return ieee754dp_inf(0); - case IEEE754_CLASS_ZERO: - return ieee754dp_inf(1); - case IEEE754_CLASS_DNORM: - DPDNORMX; - break; - case IEEE754_CLASS_NORM: - break; - } - return ieee754dp_fint(xe); -} --- linux-2.5.73/arch/mips64/math-emu/dp_modf.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,80 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -/* modf function is always exact for a finite number -*/ -ieee754dp ieee754dp_modf(ieee754dp x, ieee754dp * ip) -{ - COMPXDP; - - CLEARCX; - - EXPLODEXDP; - - switch (xc) { - case IEEE754_CLASS_SNAN: - case IEEE754_CLASS_QNAN: - case IEEE754_CLASS_INF: - case IEEE754_CLASS_ZERO: - *ip = x; - return x; - case IEEE754_CLASS_DNORM: - /* far to small */ - *ip = ieee754dp_zero(xs); - return x; - case IEEE754_CLASS_NORM: - break; - } - if (xe < 0) { - *ip = ieee754dp_zero(xs); - return x; - } - if (xe >= DP_MBITS) { - *ip = x; - return ieee754dp_zero(xs); - } - /* generate ipart mantissa by clearing bottom bits - */ - *ip = builddp(xs, xe + DP_EBIAS, - ((xm >> (DP_MBITS - xe)) << (DP_MBITS - xe)) & - ~DP_HIDDEN_BIT); - - /* generate fpart mantissa by clearing top bits - * and normalizing (must be able to normalize) - */ - xm = (xm << (64 - (DP_MBITS - xe))) >> (64 - (DP_MBITS - xe)); - if (xm == 0) - return ieee754dp_zero(xs); - - while ((xm >> DP_MBITS) == 0) { - xm <<= 1; - xe--; - } - return builddp(xs, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT); -} --- linux-2.5.73/arch/mips64/math-emu/dp_mul.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,180 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -ieee754dp ieee754dp_mul(ieee754dp x, ieee754dp y) -{ - COMPXDP; - COMPYDP; - - CLEARCX; - - EXPLODEXDP; - EXPLODEYDP; - - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(ieee754dp_bestnan(x, y), "mul", x, - y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(y, "mul", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754dp_nanxcpt(x, "mul", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754dp_bestnan(x, y); - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): - return y; - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF): - return x; - - - /* Infinity handling */ - - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF): - SETCX(IEEE754_INVALID_OPERATION); - return ieee754dp_xcpt(ieee754dp_indef(), "mul", x, y); - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): - return ieee754dp_inf(xs ^ ys); - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO): - return ieee754dp_zero(xs ^ ys); - - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM): - DPDNORMX; - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM): - DPDNORMY; - break; - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM): - DPDNORMX; - break; - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM): - break; - } - /* rm = xm * ym, re = xe+ye basicly */ - assert(xm & DP_HIDDEN_BIT); - assert(ym & DP_HIDDEN_BIT); - { - int re = xe + ye; - int rs = xs ^ ys; - unsigned long long rm; - - /* shunt to top of word */ - xm <<= 64 - (DP_MBITS + 1); - ym <<= 64 - (DP_MBITS + 1); - - /* multiply 32bits xm,ym to give high 32bits rm with stickness - */ - - /* 32 * 32 => 64 */ -#define DPXMULT(x,y) ((unsigned long long)(x) * (unsigned long long)y) - - { - unsigned lxm = xm; - unsigned hxm = xm >> 32; - unsigned lym = ym; - unsigned hym = ym >> 32; - unsigned long long lrm; - unsigned long long hrm; - - lrm = DPXMULT(lxm, lym); - hrm = DPXMULT(hxm, hym); - - { - unsigned long long t = DPXMULT(lxm, hym); - { - unsigned long long at = - lrm + (t << 32); - hrm += at < lrm; - lrm = at; - } - hrm = hrm + (t >> 32); - } - - { - unsigned long long t = DPXMULT(hxm, lym); - { - unsigned long long at = - lrm + (t << 32); - hrm += at < lrm; - lrm = at; - } - hrm = hrm + (t >> 32); - } - rm = hrm | (lrm != 0); - } - - /* - * sticky shift down to normal rounding precision - */ - if ((signed long long) rm < 0) { - rm = - (rm >> (64 - (DP_MBITS + 1 + 3))) | - ((rm << (DP_MBITS + 1 + 3)) != 0); - re++; - } else { - rm = - (rm >> (64 - (DP_MBITS + 1 + 3 + 1))) | - ((rm << (DP_MBITS + 1 + 3 + 1)) != 0); - } - assert(rm & (DP_HIDDEN_BIT << 3)); - DPNORMRET2(rs, re, rm, "mul", x, y); - } -} --- linux-2.5.73/arch/mips64/math-emu/dp_scalb.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,58 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -ieee754dp ieee754dp_scalb(ieee754dp x, int n) -{ - COMPXDP; - - CLEARCX; - - EXPLODEXDP; - - switch (xc) { - case IEEE754_CLASS_SNAN: - return ieee754dp_nanxcpt(x, "scalb", x, n); - case IEEE754_CLASS_QNAN: - case IEEE754_CLASS_INF: - case IEEE754_CLASS_ZERO: - return x; - case IEEE754_CLASS_DNORM: - DPDNORMX; - break; - case IEEE754_CLASS_NORM: - break; - } - DPNORMRET2(xs, xe + n, xm << 3, "scalb", x, n); -} - - -ieee754dp ieee754dp_ldexp(ieee754dp x, int n) -{ - return ieee754dp_scalb(x, n); -} --- linux-2.5.73/arch/mips64/math-emu/dp_simple.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,66 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -int ieee754dp_finite(ieee754dp x) -{ - return DPBEXP(x) != DP_EMAX + 1 + DP_EBIAS; -} - -ieee754dp ieee754dp_copysign(ieee754dp x, ieee754dp y) -{ - CLEARCX; - DPSIGN(x) = DPSIGN(y); - return x; -} - - -ieee754dp ieee754dp_neg(ieee754dp x) -{ - CLEARCX; - - if (ieee754dp_isnan(x)) /* but not infinity */ - return ieee754dp_nanxcpt(x, "neg", x); - - /* quick fix up */ - DPSIGN(x) ^= 1; - return x; -} - - -ieee754dp ieee754dp_abs(ieee754dp x) -{ - CLEARCX; - - if (ieee754dp_isnan(x)) /* but not infinity */ - return ieee754dp_nanxcpt(x, "abs", x); - - /* quick fix up */ - DPSIGN(x) = 0; - return x; -} --- linux-2.5.73/arch/mips64/math-emu/dp_sqrt.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,167 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision square root - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -static const struct ieee754dp_konst knan = { -#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__) - 0, 0, DP_EBIAS + DP_EMAX + 1, 0 -#else - 0, DP_EBIAS + DP_EMAX + 1, 0, 0 -#endif -}; - -#define nan ((ieee754dp)knan) - -static const unsigned table[] = { - 0, 1204, 3062, 5746, 9193, 13348, 18162, 23592, - 29598, 36145, 43202, 50740, 58733, 67158, 75992, - 85215, 83599, 71378, 60428, 50647, 41945, 34246, - 27478, 21581, 16499, 12183, 8588, 5674, 3403, - 1742, 661, 130 -}; - -ieee754dp ieee754dp_sqrt(ieee754dp x) -{ - struct ieee754_csr oldcsr; - ieee754dp y, z, t; - unsigned scalx, yh; - COMPXDP; - - EXPLODEXDP; - - /* x == INF or NAN? */ - switch (xc) { - case IEEE754_CLASS_QNAN: - case IEEE754_CLASS_SNAN: - /* sqrt(Nan) = Nan */ - return ieee754dp_nanxcpt(x, "sqrt"); - case IEEE754_CLASS_ZERO: - /* sqrt(0) = 0 */ - return x; - case IEEE754_CLASS_INF: - if (xs) - /* sqrt(-Inf) = Nan */ - return ieee754dp_nanxcpt(nan, "sqrt"); - /* sqrt(+Inf) = Inf */ - return x; - case IEEE754_CLASS_DNORM: - DPDNORMX; - /* fall through */ - case IEEE754_CLASS_NORM: - if (xs) - /* sqrt(-x) = Nan */ - return ieee754dp_nanxcpt(nan, "sqrt"); - break; - } - - /* save old csr; switch off INX enable & flag; set RN rounding */ - oldcsr = ieee754_csr; - ieee754_csr.mx &= ~IEEE754_INEXACT; - ieee754_csr.sx &= ~IEEE754_INEXACT; - ieee754_csr.rm = IEEE754_RN; - - /* adjust exponent to prevent overflow */ - scalx = 0; - if (xe > 512) { /* x > 2**-512? */ - xe -= 512; /* x = x / 2**512 */ - scalx += 256; - } else if (xe < -512) { /* x < 2**-512? */ - xe += 512; /* x = x * 2**512 */ - scalx -= 256; - } - - y = x = builddp(0, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT); - - /* magic initial approximation to almost 8 sig. bits */ - yh = y.bits >> 32; - yh = (yh >> 1) + 0x1ff80000; - yh = yh - table[(yh >> 15) & 31]; - y.bits = ((unsigned long long) yh << 32) | (y.bits & 0xffffffff); - - /* Heron's rule once with correction to improve to ~18 sig. bits */ - /* t=x/y; y=y+t; py[n0]=py[n0]-0x00100006; py[n1]=0; */ - t = ieee754dp_div(x, y); - y = ieee754dp_add(y, t); - y.bits -= 0x0010000600000000LL; - y.bits &= 0xffffffff00000000LL; - - /* triple to almost 56 sig. bits: y ~= sqrt(x) to within 1 ulp */ - /* t=y*y; z=t; pt[n0]+=0x00100000; t+=z; z=(x-z)*y; */ - z = t = ieee754dp_mul(y, y); - t.parts.bexp += 0x001; - t = ieee754dp_add(t, z); - z = ieee754dp_mul(ieee754dp_sub(x, z), y); - - /* t=z/(t+x) ; pt[n0]+=0x00100000; y+=t; */ - t = ieee754dp_div(z, ieee754dp_add(t, x)); - t.parts.bexp += 0x001; - y = ieee754dp_add(y, t); - - /* twiddle last bit to force y correctly rounded */ - - /* set RZ, clear INEX flag */ - ieee754_csr.rm = IEEE754_RZ; - ieee754_csr.sx &= ~IEEE754_INEXACT; - - /* t=x/y; ...chopped quotient, possibly inexact */ - t = ieee754dp_div(x, y); - - if (ieee754_csr.sx & IEEE754_INEXACT || t.bits != y.bits) { - - if (!(ieee754_csr.sx & IEEE754_INEXACT)) - /* t = t-ulp */ - t.bits -= 1; - - /* add inexact to result status */ - oldcsr.cx |= IEEE754_INEXACT; - oldcsr.sx |= IEEE754_INEXACT; - - switch (oldcsr.rm) { - case IEEE754_RP: - y.bits += 1; - /* drop through */ - case IEEE754_RN: - t.bits += 1; - break; - } - - /* y=y+t; ...chopped sum */ - y = ieee754dp_add(y, t); - - /* adjust scalx for correctly rounded sqrt(x) */ - scalx -= 1; - } - - /* py[n0]=py[n0]+scalx; ...scale back y */ - y.parts.bexp += scalx; - - /* restore rounding mode, possibly set inexact */ - ieee754_csr = oldcsr; - - return y; -} --- linux-2.5.73/arch/mips64/math-emu/dp_sub.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,194 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -ieee754dp ieee754dp_sub(ieee754dp x, ieee754dp y) -{ - COMPXDP; - COMPYDP; - - CLEARCX; - - EXPLODEXDP; - EXPLODEYDP; - - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(ieee754dp_bestnan(x, y), "sub", x, - y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(y, "sub", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754dp_nanxcpt(x, "sub", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754dp_bestnan(x, y); - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): - return y; - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF): - return x; - - - /* Inifity handling - */ - - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): - if (xs != ys) - return x; - SETCX(IEEE754_INVALID_OPERATION); - return ieee754dp_xcpt(ieee754dp_indef(), "sub", x, y); - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF): - return ieee754dp_inf(ys ^ 1); - - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): - return x; - - /* Zero handling - */ - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): - if (xs != ys) - return x; - else - return ieee754dp_zero(ieee754_csr.rm == - IEEE754_RD); - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO): - return x; - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM): - /* quick fix up */ - DPSIGN(y) ^= 1; - return y; - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM): - DPDNORMX; - /* FAAL THOROUGH */ - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM): - /* normalize ym,ye */ - DPDNORMY; - break; - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM): - /* normalize xm,xe */ - DPDNORMX; - break; - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM): - break; - } - /* flip sign of y and handle as add */ - ys ^= 1; - - assert(xm & DP_HIDDEN_BIT); - assert(ym & DP_HIDDEN_BIT); - - - /* provide guard,round and stick bit dpace */ - xm <<= 3; - ym <<= 3; - - if (xe > ye) { - /* have to shift y fraction right to align - */ - int s = xe - ye; - ym = XDPSRS(ym, s); - ye += s; - } else if (ye > xe) { - /* have to shift x fraction right to align - */ - int s = ye - xe; - xm = XDPSRS(xm, s); - xe += s; - } - assert(xe == ye); - assert(xe <= DP_EMAX); - - if (xs == ys) { - /* generate 28 bit result of adding two 27 bit numbers - */ - xm = xm + ym; - xe = xe; - xs = xs; - - if (xm >> (DP_MBITS + 1 + 3)) { /* carry out */ - xm = XDPSRS1(xm); /* shift preserving sticky */ - xe++; - } - } else { - if (xm >= ym) { - xm = xm - ym; - xe = xe; - xs = xs; - } else { - xm = ym - xm; - xe = xe; - xs = ys; - } - if (xm == 0) { - if (ieee754_csr.rm == IEEE754_RD) - return ieee754dp_zero(1); /* round negative inf. => sign = -1 */ - else - return ieee754dp_zero(0); /* other round modes => sign = 1 */ - } - - /* normalize to rounding precision - */ - while ((xm >> (DP_MBITS + 3)) == 0) { - xm <<= 1; - xe--; - } - } - DPNORMRET2(xs, xe, xm, "sub", x, y); -} --- linux-2.5.73/arch/mips64/math-emu/dp_tint.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,88 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include -#include "ieee754dp.h" - -int ieee754dp_tint(ieee754dp x) -{ - COMPXDP; - - CLEARCX; - - EXPLODEXDP; - - switch (xc) { - case IEEE754_CLASS_SNAN: - case IEEE754_CLASS_QNAN: - SETCX(IEEE754_INVALID_OPERATION); - return ieee754si_xcpt(ieee754si_indef(), "fixdp", x); - case IEEE754_CLASS_INF: - SETCX(IEEE754_OVERFLOW); - return ieee754si_xcpt(ieee754si_indef(), "fixdp", x); - case IEEE754_CLASS_ZERO: - return 0; - case IEEE754_CLASS_DNORM: /* much to small */ - SETCX(IEEE754_UNDERFLOW); - return ieee754si_xcpt(0, "fixdp", x); - case IEEE754_CLASS_NORM: - break; - } - if (xe >= 31) { - SETCX(IEEE754_OVERFLOW); - return ieee754si_xcpt(ieee754si_indef(), "fix", x); - } - if (xe < 0) { - SETCX(IEEE754_UNDERFLOW); - return ieee754si_xcpt(0, "fix", x); - } - /* oh gawd */ - if (xe > DP_MBITS) { - xm <<= xe - DP_MBITS; - } else if (xe < DP_MBITS) { - /* XXX no rounding - */ - xm >>= DP_MBITS - xe; - } - if (xs) - return -xm; - else - return xm; -} - - -unsigned int ieee754dp_tuns(ieee754dp x) -{ - ieee754dp hb = ieee754dp_1e31(); - - /* what if x < 0 ?? */ - if (ieee754dp_lt(x, hb)) - return (unsigned) ieee754dp_tint(x); - - return (unsigned) ieee754dp_tint(ieee754dp_sub(x, hb)) | - ((unsigned) 1 << 31); -} --- linux-2.5.73/arch/mips64/math-emu/dp_tlong.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,141 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -long long ieee754dp_tlong(ieee754dp x) -{ - COMPXDP; - - CLEARCX; - - EXPLODEXDP; - - switch (xc) { - case IEEE754_CLASS_SNAN: - case IEEE754_CLASS_QNAN: - SETCX(IEEE754_INVALID_OPERATION); - return ieee754di_xcpt(ieee754di_indef(), "dp_tlong", x); - case IEEE754_CLASS_INF: - SETCX(IEEE754_OVERFLOW); - return ieee754di_xcpt(ieee754di_indef(), "dp_tlong", x); - case IEEE754_CLASS_ZERO: - return 0; - case IEEE754_CLASS_DNORM: /* much too small */ - SETCX(IEEE754_UNDERFLOW); - return ieee754di_xcpt(0, "dp_tlong", x); - case IEEE754_CLASS_NORM: - break; - } - if (xe >= 63) { - SETCX(IEEE754_OVERFLOW); - return ieee754di_xcpt(ieee754di_indef(), "dp_tlong", x); - } - if (xe < 0) { - if (ieee754_csr.rm == IEEE754_RU) { - if (xs) { /* Negative */ - return 0x0000000000000000LL; - } else { /* Positive */ - return 0x0000000000000001LL; - } - } else if (ieee754_csr.rm == IEEE754_RD) { - if (xs) { /* Negative , return -1 */ - return 0xffffffffffffffffLL; - } else { /* Positive */ - return 0x0000000000000000LL; - } - } else { - SETCX(IEEE754_UNDERFLOW); - return ieee754di_xcpt(0, "dp_tlong", x); - } - } - /* oh gawd */ - if (xe > DP_MBITS) { - xm <<= xe - DP_MBITS; - } else if (xe < DP_MBITS) { - unsigned long long residue; - unsigned long long mask = 0; - int i; - int round; - int sticky; - int odd; - - /* compute mask */ - for (i = 0; i < DP_MBITS - xe; i++) { - mask = mask << 1; - mask = mask | 0x1; - } - residue = (xm & mask) << (64 - (DP_MBITS - xe)); - round = - ((0x8000000000000000LL & residue) != - 0x0000000000000000LL); - sticky = - ((0x7fffffffffffffffLL & residue) != - 0x0000000000000000LL); - - xm >>= DP_MBITS - xe; - - odd = ((xm & 0x1) != 0x0000000000000000LL); - - /* Do the rounding */ - if (!round && sticky) { - if ((ieee754_csr.rm == IEEE754_RU && !xs) - || (ieee754_csr.rm == IEEE754_RD && xs)) { - xm++; - } - } else if (round && !sticky) { - if ((ieee754_csr.rm == IEEE754_RU && !xs) - || (ieee754_csr.rm == IEEE754_RD && xs) - || (ieee754_csr.rm == IEEE754_RN && odd)) { - xm++; - } - } else if (round && sticky) { - if ((ieee754_csr.rm == IEEE754_RU && !xs) - || (ieee754_csr.rm == IEEE754_RD && xs) - || (ieee754_csr.rm == IEEE754_RN)) { - xm++; - } - } - } - if (xs) - return -xm; - else - return xm; -} - - -unsigned long long ieee754dp_tulong(ieee754dp x) -{ - ieee754dp hb = ieee754dp_1e63(); - - /* what if x < 0 ?? */ - if (ieee754dp_lt(x, hb)) - return (unsigned long long) ieee754dp_tlong(x); - - return (unsigned long long) ieee754dp_tlong(ieee754dp_sub(x, hb)) | - (1ULL << 63); -} --- linux-2.5.73/arch/mips64/math-emu/ieee754.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,138 +0,0 @@ -/* ieee754 floating point arithmetic - * single and double precision - * - * BUGS - * not much dp done - * doesn't generate IEEE754_INEXACT - * - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754int.h" - -#define DP_EBIAS 1023 -#define DP_EMIN (-1022) -#define DP_EMAX 1023 - -#define SP_EBIAS 127 -#define SP_EMIN (-126) -#define SP_EMAX 127 - -/* indexed by class */ -const char *const ieee754_cname[] = { - "Normal", - "Zero", - "Denormal", - "Infinity", - "QNaN", - "SNaN", -}; - -/* the control status register -*/ -struct ieee754_csr ieee754_csr; - -/* special constants -*/ - - -#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__) -#define SPSTR(s,b,m) {m,b,s} -#define DPSTR(s,b,mh,ml) {ml,mh,b,s} -#endif - -#ifdef __MIPSEB__ -#define SPSTR(s,b,m) {s,b,m} -#define DPSTR(s,b,mh,ml) {s,b,mh,ml} -#endif - -const struct ieee754dp_konst __ieee754dp_spcvals[] = { - DPSTR(0, DP_EMIN - 1 + DP_EBIAS, 0, 0), /* + zero */ - DPSTR(1, DP_EMIN - 1 + DP_EBIAS, 0, 0), /* - zero */ - DPSTR(0, DP_EBIAS, 0, 0), /* + 1.0 */ - DPSTR(1, DP_EBIAS, 0, 0), /* - 1.0 */ - DPSTR(0, 3 + DP_EBIAS, 0x40000, 0), /* + 10.0 */ - DPSTR(1, 3 + DP_EBIAS, 0x40000, 0), /* - 10.0 */ - DPSTR(0, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* + infinity */ - DPSTR(1, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* - infinity */ - DPSTR(0, DP_EMAX + 1 + DP_EBIAS, 0x40000, 0), /* + indef quiet Nan */ - DPSTR(0, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* + max */ - DPSTR(1, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* - max */ - DPSTR(0, DP_EMIN + DP_EBIAS, 0, 0), /* + min normal */ - DPSTR(1, DP_EMIN + DP_EBIAS, 0, 0), /* - min normal */ - DPSTR(0, DP_EMIN - 1 + DP_EBIAS, 0, 1), /* + min denormal */ - DPSTR(1, DP_EMIN - 1 + DP_EBIAS, 0, 1), /* - min denormal */ - DPSTR(0, 31 + DP_EBIAS, 0, 0), /* + 1.0e31 */ - DPSTR(0, 63 + DP_EBIAS, 0, 0), /* + 1.0e63 */ -}; - -const struct ieee754sp_konst __ieee754sp_spcvals[] = { - SPSTR(0, SP_EMIN - 1 + SP_EBIAS, 0), /* + zero */ - SPSTR(1, SP_EMIN - 1 + SP_EBIAS, 0), /* - zero */ - SPSTR(0, SP_EBIAS, 0), /* + 1.0 */ - SPSTR(1, SP_EBIAS, 0), /* - 1.0 */ - SPSTR(0, 3 + SP_EBIAS, 0x200000), /* + 10.0 */ - SPSTR(1, 3 + SP_EBIAS, 0x200000), /* - 10.0 */ - SPSTR(0, SP_EMAX + 1 + SP_EBIAS, 0), /* + infinity */ - SPSTR(1, SP_EMAX + 1 + SP_EBIAS, 0), /* - infinity */ - SPSTR(0, SP_EMAX + 1 + SP_EBIAS, 0x200000), /* + indef quiet Nan */ - SPSTR(0, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* + max normal */ - SPSTR(1, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* - max normal */ - SPSTR(0, SP_EMIN + SP_EBIAS, 0), /* + min normal */ - SPSTR(1, SP_EMIN + SP_EBIAS, 0), /* - min normal */ - SPSTR(0, SP_EMIN - 1 + SP_EBIAS, 1), /* + min denormal */ - SPSTR(1, SP_EMIN - 1 + SP_EBIAS, 1), /* - min denormal */ - SPSTR(0, 31 + SP_EBIAS, 0), /* + 1.0e31 */ - SPSTR(0, 63 + SP_EBIAS, 0), /* + 1.0e63 */ -}; - - -int ieee754si_xcpt(int r, const char *op, ...) -{ - struct ieee754xctx ax; - - if (!TSTX()) - return r; - ax.op = op; - ax.rt = IEEE754_RT_SI; - ax.rv.si = r; - va_start(ax.ap, op); - ieee754_xcpt(&ax); - return ax.rv.si; -} - -long long ieee754di_xcpt(long long r, const char *op, ...) -{ - struct ieee754xctx ax; - - if (!TSTX()) - return r; - ax.op = op; - ax.rt = IEEE754_RT_DI; - ax.rv.di = r; - va_start(ax.ap, op); - ieee754_xcpt(&ax); - return ax.rv.di; -} --- linux-2.5.73/arch/mips64/math-emu/ieee754d.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,142 +0,0 @@ -/* some debug functions -*/ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - -/************************************************************************** - * Nov 7, 2000 - * Modified to build and operate in Linux kernel environment. - * - * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - *************************************************************************/ - -#include "ieee754.h" - -#define DP_EBIAS 1023 -#define DP_EMIN (-1022) -#define DP_EMAX 1023 -#define DP_FBITS 52 - -#define SP_EBIAS 127 -#define SP_EMIN (-126) -#define SP_EMAX 127 -#define SP_FBITS 23 - -#define DP_MBIT(x) ((unsigned long long)1 << (x)) -#define DP_HIDDEN_BIT DP_MBIT(DP_FBITS) -#define DP_SIGN_BIT DP_MBIT(63) - - -#define SP_MBIT(x) ((unsigned long)1 << (x)) -#define SP_HIDDEN_BIT SP_MBIT(SP_FBITS) -#define SP_SIGN_BIT SP_MBIT(31) - - -#define SPSIGN(sp) (sp.parts.sign) -#define SPBEXP(sp) (sp.parts.bexp) -#define SPMANT(sp) (sp.parts.mant) - -#define DPSIGN(dp) (dp.parts.sign) -#define DPBEXP(dp) (dp.parts.bexp) -#define DPMANT(dp) (dp.parts.mant) - -ieee754dp ieee754dp_dump(char *m, ieee754dp x) -{ - int i; - - printk("%s", m); - printk("<%08x,%08x>\n", (unsigned) (x.bits >> 32), - (unsigned) x.bits); - printk("\t="); - switch (ieee754dp_class(x)) { - case IEEE754_CLASS_QNAN: - case IEEE754_CLASS_SNAN: - printk("Nan %c", DPSIGN(x) ? '-' : '+'); - for (i = DP_FBITS - 1; i >= 0; i--) - printk("%c", DPMANT(x) & DP_MBIT(i) ? '1' : '0'); - break; - case IEEE754_CLASS_INF: - printk("%cInfinity", DPSIGN(x) ? '-' : '+'); - break; - case IEEE754_CLASS_ZERO: - printk("%cZero", DPSIGN(x) ? '-' : '+'); - break; - case IEEE754_CLASS_DNORM: - printk("%c0.", DPSIGN(x) ? '-' : '+'); - for (i = DP_FBITS - 1; i >= 0; i--) - printk("%c", DPMANT(x) & DP_MBIT(i) ? '1' : '0'); - printk("e%d", DPBEXP(x) - DP_EBIAS); - break; - case IEEE754_CLASS_NORM: - printk("%c1.", DPSIGN(x) ? '-' : '+'); - for (i = DP_FBITS - 1; i >= 0; i--) - printk("%c", DPMANT(x) & DP_MBIT(i) ? '1' : '0'); - printk("e%d", DPBEXP(x) - DP_EBIAS); - break; - default: - printk("Illegal/Unknown IEEE754 value class"); - } - printk("\n"); - return x; -} - -ieee754sp ieee754sp_dump(char *m, ieee754sp x) -{ - int i; - - printk("%s=", m); - printk("<%08x>\n", (unsigned) x.bits); - printk("\t="); - switch (ieee754sp_class(x)) { - case IEEE754_CLASS_QNAN: - case IEEE754_CLASS_SNAN: - printk("Nan %c", SPSIGN(x) ? '-' : '+'); - for (i = SP_FBITS - 1; i >= 0; i--) - printk("%c", SPMANT(x) & SP_MBIT(i) ? '1' : '0'); - break; - case IEEE754_CLASS_INF: - printk("%cInfinity", SPSIGN(x) ? '-' : '+'); - break; - case IEEE754_CLASS_ZERO: - printk("%cZero", SPSIGN(x) ? '-' : '+'); - break; - case IEEE754_CLASS_DNORM: - printk("%c0.", SPSIGN(x) ? '-' : '+'); - for (i = SP_FBITS - 1; i >= 0; i--) - printk("%c", SPMANT(x) & SP_MBIT(i) ? '1' : '0'); - printk("e%d", SPBEXP(x) - SP_EBIAS); - break; - case IEEE754_CLASS_NORM: - printk("%c1.", SPSIGN(x) ? '-' : '+'); - for (i = SP_FBITS - 1; i >= 0; i--) - printk("%c", SPMANT(x) & SP_MBIT(i) ? '1' : '0'); - printk("e%d", SPBEXP(x) - SP_EBIAS); - break; - default: - printk("Illegal/Unknown IEEE754 value class"); - } - printk("\n"); - return x; -} - --- linux-2.5.73/arch/mips64/math-emu/ieee754dp.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,197 +0,0 @@ -/* IEEE754 floating point arithmetic - * double precision: common utilities - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754dp.h" - -int ieee754dp_class(ieee754dp x) -{ - COMPXDP; - EXPLODEXDP; - return xc; -} - -int ieee754dp_isnan(ieee754dp x) -{ - return ieee754dp_class(x) >= IEEE754_CLASS_SNAN; -} - -int ieee754dp_issnan(ieee754dp x) -{ - assert(ieee754dp_isnan(x)); - if (ieee754_csr.noq) - return 1; - return !(DPMANT(x) & DP_MBIT(DP_MBITS - 1)); -} - - -ieee754dp ieee754dp_xcpt(ieee754dp r, const char *op, ...) -{ - struct ieee754xctx ax; - if (!TSTX()) - return r; - - ax.op = op; - ax.rt = IEEE754_RT_DP; - ax.rv.dp = r; - va_start(ax.ap, op); - ieee754_xcpt(&ax); - return ax.rv.dp; -} - -ieee754dp ieee754dp_nanxcpt(ieee754dp r, const char *op, ...) -{ - struct ieee754xctx ax; - - assert(ieee754dp_isnan(r)); - - if (!ieee754dp_issnan(r)) /* QNAN does not cause invalid op !! */ - return r; - - if (!SETCX(IEEE754_INVALID_OPERATION)) { - /* not enabled convert to a quiet NaN */ - if (ieee754_csr.noq) - return r; - DPMANT(r) |= DP_MBIT(DP_MBITS - 1); - return r; - } - - ax.op = op; - ax.rt = 0; - ax.rv.dp = r; - va_start(ax.ap, op); - ieee754_xcpt(&ax); - return ax.rv.dp; -} - -ieee754dp ieee754dp_bestnan(ieee754dp x, ieee754dp y) -{ - assert(ieee754dp_isnan(x)); - assert(ieee754dp_isnan(y)); - - if (DPMANT(x) > DPMANT(y)) - return x; - else - return y; -} - - -/* generate a normal/denormal number with over,under handling - * sn is sign - * xe is an unbiased exponent - * xm is 3bit extended precision value. - */ -ieee754dp ieee754dp_format(int sn, int xe, unsigned long long xm) -{ - assert(xm); /* we don't gen exact zeros (probably should) */ - - assert((xm >> (DP_MBITS + 1 + 3)) == 0); /* no execess */ - assert(xm & (DP_HIDDEN_BIT << 3)); - - if (xe < DP_EMIN) { - /* strip lower bits */ - int es = DP_EMIN - xe; - - if (ieee754_csr.nod) { - SETCX(IEEE754_UNDERFLOW); - return ieee754dp_zero(sn); - } - - /* sticky right shift es bits - */ - xm = XDPSRS(xm, es); - xe += es; - - assert((xm & (DP_HIDDEN_BIT << 3)) == 0); - assert(xe == DP_EMIN); - } - if (xm & (DP_MBIT(3) - 1)) { - SETCX(IEEE754_INEXACT); - /* inexact must round of 3 bits - */ - switch (ieee754_csr.rm) { - case IEEE754_RZ: - break; - case IEEE754_RN: - xm += 0x3 + ((xm >> 3) & 1); - /* xm += (xm&0x8)?0x4:0x3 */ - break; - case IEEE754_RU: /* toward +Infinity */ - if (!sn) /* ?? */ - xm += 0x8; - break; - case IEEE754_RD: /* toward -Infinity */ - if (sn) /* ?? */ - xm += 0x8; - break; - } - /* adjust exponent for rounding add overflowing - */ - if (xm >> (DP_MBITS + 3 + 1)) { /* add causes mantissa overflow */ - xm >>= 1; - xe++; - } - } - /* strip grs bits */ - xm >>= 3; - - assert((xm >> (DP_MBITS + 1)) == 0); /* no execess */ - assert(xe >= DP_EMIN); - - if (xe > DP_EMAX) { - SETCX(IEEE754_OVERFLOW); - /* -O can be table indexed by (rm,sn) */ - switch (ieee754_csr.rm) { - case IEEE754_RN: - return ieee754dp_inf(sn); - case IEEE754_RZ: - return ieee754dp_max(sn); - case IEEE754_RU: /* toward +Infinity */ - if (sn == 0) - return ieee754dp_inf(0); - else - return ieee754dp_max(1); - case IEEE754_RD: /* toward -Infinity */ - if (sn == 0) - return ieee754dp_max(0); - else - return ieee754dp_inf(1); - } - } - /* gen norm/denorm/zero */ - - if ((xm & DP_HIDDEN_BIT) == 0) { - /* we underflow (tiny/zero) */ - assert(xe == DP_EMIN); - SETCX(IEEE754_UNDERFLOW); - return builddp(sn, DP_EMIN - 1 + DP_EBIAS, xm); - } else { - assert((xm >> (DP_MBITS + 1)) == 0); /* no execess */ - assert(xm & DP_HIDDEN_BIT); - - return builddp(sn, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT); - } -} --- linux-2.5.73/arch/mips64/math-emu/ieee754dp.h 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,83 +0,0 @@ -/* - * IEEE754 floating point - * double precision internal header file - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754int.h" - -#define assert(expr) ((void)0) - -/* 3bit extended double precision sticky right shift */ -#define XDPSRS(v,rs) \ - ((rs > (DP_MBITS+3))?1:((v) >> (rs)) | ((v) << (64-(rs)) != 0)) - -#define XDPSRSX1() \ - (xe++, (xm = (xm >> 1) | (xm & 1))) - -#define XDPSRS1(v) \ - (((v) >> 1) | ((v) & 1)) - -/* convert denormal to normalized with extended exponent */ -#define DPDNORMx(m,e) \ - while( (m >> DP_MBITS) == 0) { m <<= 1; e--; } -#define DPDNORMX DPDNORMx(xm,xe) -#define DPDNORMY DPDNORMx(ym,ye) - -static __inline ieee754dp builddp(int s, int bx, unsigned long long m) -{ - ieee754dp r; - - assert((s) == 0 || (s) == 1); - assert((bx) >= DP_EMIN - 1 + DP_EBIAS - && (bx) <= DP_EMAX + 1 + DP_EBIAS); - assert(((m) >> DP_MBITS) == 0); - - r.parts.sign = s; - r.parts.bexp = bx; - r.parts.mant = m; - return r; -} - -extern int ieee754dp_isnan(ieee754dp); -extern int ieee754dp_issnan(ieee754dp); -extern int ieee754si_xcpt(int, const char *, ...); -extern long long ieee754di_xcpt(long long, const char *, ...); -extern ieee754dp ieee754dp_xcpt(ieee754dp, const char *, ...); -extern ieee754dp ieee754dp_nanxcpt(ieee754dp, const char *, ...); -extern ieee754dp ieee754dp_bestnan(ieee754dp, ieee754dp); -extern ieee754dp ieee754dp_format(int, int, unsigned long long); - - -#define DPNORMRET2(s,e,m,name,a0,a1) \ -{ \ - ieee754dp V = ieee754dp_format(s,e,m); \ - if(TSTX()) \ - return ieee754dp_xcpt(V,name,a0,a1); \ - else \ - return V; \ -} - -#define DPNORMRET1(s,e,m,name,a0) DPNORMRET2(s,e,m,name,a0,a0) --- linux-2.5.73/arch/mips64/math-emu/ieee754.h 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,490 +0,0 @@ -/* single and double precision fp ops - * missing extended precision. -*/ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - -/************************************************************************** - * Nov 7, 2000 - * Modification to allow integration with Linux kernel - * - * Kevin D. Kissell, kevink@mips.com and Carsten Langgard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - *************************************************************************/ - -#ifdef __KERNEL__ -/* Going from Algorithmics to Linux native environment, add this */ -#include - -/* - * Not very pretty, but the Linux kernel's normal va_list definition - * does not allow it to be used as a structure element, as it is here. - */ -#ifndef _STDARG_H -#include -#endif - -#else - -/* Note that __KERNEL__ is taken to mean Linux kernel */ - -#if #system(OpenBSD) -#include -#endif -#include - -#endif /* __KERNEL__ */ - -#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__) -struct ieee754dp_konst { - unsigned mantlo:32; - unsigned manthi:20; - unsigned bexp:11; - unsigned sign:1; -}; -struct ieee754sp_konst { - unsigned mant:23; - unsigned bexp:8; - unsigned sign:1; -}; - -typedef union _ieee754dp { - struct ieee754dp_konst oparts; - struct { - unsigned long long mant:52; - unsigned int bexp:11; - unsigned int sign:1; - } parts; - unsigned long long bits; - double d; -} ieee754dp; - -typedef union _ieee754sp { - struct ieee754sp_konst parts; - float f; - unsigned long bits; -} ieee754sp; -#endif - -#if (defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN) || defined(__MIPSEB__) -struct ieee754dp_konst { - unsigned sign:1; - unsigned bexp:11; - unsigned manthi:20; - unsigned mantlo:32; -}; -typedef union _ieee754dp { - struct ieee754dp_konst oparts; - struct { - unsigned int sign:1; - unsigned int bexp:11; - unsigned long long mant:52; - } parts; - double d; - unsigned long long bits; -} ieee754dp; - -struct ieee754sp_konst { - unsigned sign:1; - unsigned bexp:8; - unsigned mant:23; -}; - -typedef union _ieee754sp { - struct ieee754sp_konst parts; - float f; - unsigned long bits; -} ieee754sp; -#endif - -/* - * single precision (often aka float) -*/ -int ieee754sp_finite(ieee754sp x); -int ieee754sp_class(ieee754sp x); - -ieee754sp ieee754sp_abs(ieee754sp x); -ieee754sp ieee754sp_neg(ieee754sp x); -ieee754sp ieee754sp_scalb(ieee754sp x, int); -ieee754sp ieee754sp_logb(ieee754sp x); - -/* x with sign of y */ -ieee754sp ieee754sp_copysign(ieee754sp x, ieee754sp y); - -ieee754sp ieee754sp_add(ieee754sp x, ieee754sp y); -ieee754sp ieee754sp_sub(ieee754sp x, ieee754sp y); -ieee754sp ieee754sp_mul(ieee754sp x, ieee754sp y); -ieee754sp ieee754sp_div(ieee754sp x, ieee754sp y); - -ieee754sp ieee754sp_fint(int x); -ieee754sp ieee754sp_funs(unsigned x); -ieee754sp ieee754sp_flong(long long x); -ieee754sp ieee754sp_fulong(unsigned long long x); -ieee754sp ieee754sp_fdp(ieee754dp x); - -int ieee754sp_tint(ieee754sp x); -unsigned int ieee754sp_tuns(ieee754sp x); -long long ieee754sp_tlong(ieee754sp x); -unsigned long long ieee754sp_tulong(ieee754sp x); - -int ieee754sp_cmp(ieee754sp x, ieee754sp y, int cop); -/* - * basic sp math - */ -ieee754sp ieee754sp_modf(ieee754sp x, ieee754sp * ip); -ieee754sp ieee754sp_frexp(ieee754sp x, int *exp); -ieee754sp ieee754sp_ldexp(ieee754sp x, int exp); - -ieee754sp ieee754sp_ceil(ieee754sp x); -ieee754sp ieee754sp_floor(ieee754sp x); -ieee754sp ieee754sp_trunc(ieee754sp x); - -ieee754sp ieee754sp_sqrt(ieee754sp x); - -/* - * double precision (often aka double) -*/ -int ieee754dp_finite(ieee754dp x); -int ieee754dp_class(ieee754dp x); - -/* x with sign of y */ -ieee754dp ieee754dp_copysign(ieee754dp x, ieee754dp y); - -ieee754dp ieee754dp_add(ieee754dp x, ieee754dp y); -ieee754dp ieee754dp_sub(ieee754dp x, ieee754dp y); -ieee754dp ieee754dp_mul(ieee754dp x, ieee754dp y); -ieee754dp ieee754dp_div(ieee754dp x, ieee754dp y); - -ieee754dp ieee754dp_abs(ieee754dp x); -ieee754dp ieee754dp_neg(ieee754dp x); -ieee754dp ieee754dp_scalb(ieee754dp x, int); - -/* return exponent as integer in floating point format - */ -ieee754dp ieee754dp_logb(ieee754dp x); - -ieee754dp ieee754dp_fint(int x); -ieee754dp ieee754dp_funs(unsigned x); -ieee754dp ieee754dp_flong(long long x); -ieee754dp ieee754dp_fulong(unsigned long long x); -ieee754dp ieee754dp_fsp(ieee754sp x); - -ieee754dp ieee754dp_ceil(ieee754dp x); -ieee754dp ieee754dp_floor(ieee754dp x); -ieee754dp ieee754dp_trunc(ieee754dp x); - -int ieee754dp_tint(ieee754dp x); -unsigned int ieee754dp_tuns(ieee754dp x); -long long ieee754dp_tlong(ieee754dp x); -unsigned long long ieee754dp_tulong(ieee754dp x); - -int ieee754dp_cmp(ieee754dp x, ieee754dp y, int cop); -/* - * basic sp math - */ -ieee754dp ieee754dp_modf(ieee754dp x, ieee754dp * ip); -ieee754dp ieee754dp_frexp(ieee754dp x, int *exp); -ieee754dp ieee754dp_ldexp(ieee754dp x, int exp); - -ieee754dp ieee754dp_ceil(ieee754dp x); -ieee754dp ieee754dp_floor(ieee754dp x); -ieee754dp ieee754dp_trunc(ieee754dp x); - -ieee754dp ieee754dp_sqrt(ieee754dp x); - - - -/* 5 types of floating point number -*/ -#define IEEE754_CLASS_NORM 0x00 -#define IEEE754_CLASS_ZERO 0x01 -#define IEEE754_CLASS_DNORM 0x02 -#define IEEE754_CLASS_INF 0x03 -#define IEEE754_CLASS_SNAN 0x04 -#define IEEE754_CLASS_QNAN 0x05 -extern const char *const ieee754_cname[]; - -/* exception numbers */ -#define IEEE754_INEXACT 0x01 -#define IEEE754_UNDERFLOW 0x02 -#define IEEE754_OVERFLOW 0x04 -#define IEEE754_ZERO_DIVIDE 0x08 -#define IEEE754_INVALID_OPERATION 0x10 - -/* cmp operators -*/ -#define IEEE754_CLT 0x01 -#define IEEE754_CEQ 0x02 -#define IEEE754_CGT 0x04 -#define IEEE754_CUN 0x08 - -/* rounding mode -*/ -#define IEEE754_RN 0 /* round to nearest */ -#define IEEE754_RZ 1 /* round toward zero */ -#define IEEE754_RD 2 /* round toward -Infinity */ -#define IEEE754_RU 3 /* round toward +Infinity */ - -/* other naming */ -#define IEEE754_RM IEEE754_RD -#define IEEE754_RP IEEE754_RU - -/* "normal" comparisons -*/ -static __inline int ieee754sp_eq(ieee754sp x, ieee754sp y) -{ - return ieee754sp_cmp(x, y, IEEE754_CEQ); -} - -static __inline int ieee754sp_ne(ieee754sp x, ieee754sp y) -{ - return ieee754sp_cmp(x, y, - IEEE754_CLT | IEEE754_CGT | IEEE754_CUN); -} - -static __inline int ieee754sp_lt(ieee754sp x, ieee754sp y) -{ - return ieee754sp_cmp(x, y, IEEE754_CLT); -} - -static __inline int ieee754sp_le(ieee754sp x, ieee754sp y) -{ - return ieee754sp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ); -} - -static __inline int ieee754sp_gt(ieee754sp x, ieee754sp y) -{ - return ieee754sp_cmp(x, y, IEEE754_CGT); -} - - -static __inline int ieee754sp_ge(ieee754sp x, ieee754sp y) -{ - return ieee754sp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ); -} - -static __inline int ieee754dp_eq(ieee754dp x, ieee754dp y) -{ - return ieee754dp_cmp(x, y, IEEE754_CEQ); -} - -static __inline int ieee754dp_ne(ieee754dp x, ieee754dp y) -{ - return ieee754dp_cmp(x, y, - IEEE754_CLT | IEEE754_CGT | IEEE754_CUN); -} - -static __inline int ieee754dp_lt(ieee754dp x, ieee754dp y) -{ - return ieee754dp_cmp(x, y, IEEE754_CLT); -} - -static __inline int ieee754dp_le(ieee754dp x, ieee754dp y) -{ - return ieee754dp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ); -} - -static __inline int ieee754dp_gt(ieee754dp x, ieee754dp y) -{ - return ieee754dp_cmp(x, y, IEEE754_CGT); -} - -static __inline int ieee754dp_ge(ieee754dp x, ieee754dp y) -{ - return ieee754dp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ); -} - - -/* like strtod -*/ -ieee754dp ieee754dp_fstr(const char *s, char **endp); -char *ieee754dp_tstr(ieee754dp x, int prec, int fmt, int af); - - -/* the control status register -*/ -struct ieee754_csr { - unsigned pad:13; - unsigned noq:1; /* set 1 for no quiet NaN's */ - unsigned nod:1; /* set 1 for no denormalised numbers */ - unsigned cx:5; /* exceptions this operation */ - unsigned mx:5; /* exception enable mask */ - unsigned sx:5; /* exceptions total */ - unsigned rm:2; /* current rounding mode */ -}; -extern struct ieee754_csr ieee754_csr; - -static __inline unsigned ieee754_getrm(void) -{ - return (ieee754_csr.rm); -} -static __inline unsigned ieee754_setrm(unsigned rm) -{ - return (ieee754_csr.rm = rm); -} - -/* - * get current exceptions - */ -static __inline unsigned ieee754_getcx(void) -{ - return (ieee754_csr.cx); -} - -/* test for current exception condition - */ -static __inline int ieee754_cxtest(unsigned n) -{ - return (ieee754_csr.cx & n); -} - -/* - * get sticky exceptions - */ -static __inline unsigned ieee754_getsx(void) -{ - return (ieee754_csr.sx); -} - -/* clear sticky conditions -*/ -static __inline unsigned ieee754_clrsx(void) -{ - return (ieee754_csr.sx = 0); -} - -/* test for sticky exception condition - */ -static __inline int ieee754_sxtest(unsigned n) -{ - return (ieee754_csr.sx & n); -} - -/* debugging */ -ieee754sp ieee754sp_dump(char *s, ieee754sp x); -ieee754dp ieee754dp_dump(char *s, ieee754dp x); - -#define IEEE754_SPCVAL_PZERO 0 -#define IEEE754_SPCVAL_NZERO 1 -#define IEEE754_SPCVAL_PONE 2 -#define IEEE754_SPCVAL_NONE 3 -#define IEEE754_SPCVAL_PTEN 4 -#define IEEE754_SPCVAL_NTEN 5 -#define IEEE754_SPCVAL_PINFINITY 6 -#define IEEE754_SPCVAL_NINFINITY 7 -#define IEEE754_SPCVAL_INDEF 8 -#define IEEE754_SPCVAL_PMAX 9 /* +max norm */ -#define IEEE754_SPCVAL_NMAX 10 /* -max norm */ -#define IEEE754_SPCVAL_PMIN 11 /* +min norm */ -#define IEEE754_SPCVAL_NMIN 12 /* +min norm */ -#define IEEE754_SPCVAL_PMIND 13 /* +min denorm */ -#define IEEE754_SPCVAL_NMIND 14 /* +min denorm */ -#define IEEE754_SPCVAL_P1E31 15 /* + 1.0e31 */ -#define IEEE754_SPCVAL_P1E63 16 /* + 1.0e63 */ - -extern const struct ieee754dp_konst __ieee754dp_spcvals[]; -extern const struct ieee754sp_konst __ieee754sp_spcvals[]; -#define ieee754dp_spcvals ((const ieee754dp *)__ieee754dp_spcvals) -#define ieee754sp_spcvals ((const ieee754sp *)__ieee754sp_spcvals) - -/* return infinity with given sign -*/ -#define ieee754dp_inf(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)]) -#define ieee754dp_zero(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PZERO+(sn)]) -#define ieee754dp_one(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PONE+(sn)]) -#define ieee754dp_ten(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PTEN+(sn)]) -#define ieee754dp_indef() \ - (ieee754dp_spcvals[IEEE754_SPCVAL_INDEF]) -#define ieee754dp_max(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PMAX+(sn)]) -#define ieee754dp_min(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PMIN+(sn)]) -#define ieee754dp_mind(sn) \ - (ieee754dp_spcvals[IEEE754_SPCVAL_PMIND+(sn)]) -#define ieee754dp_1e31() \ - (ieee754dp_spcvals[IEEE754_SPCVAL_P1E31]) -#define ieee754dp_1e63() \ - (ieee754dp_spcvals[IEEE754_SPCVAL_P1E63]) - -#define ieee754sp_inf(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PINFINITY+(sn)]) -#define ieee754sp_zero(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PZERO+(sn)]) -#define ieee754sp_one(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PONE+(sn)]) -#define ieee754sp_ten(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PTEN+(sn)]) -#define ieee754sp_indef() \ - (ieee754sp_spcvals[IEEE754_SPCVAL_INDEF]) -#define ieee754sp_max(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PMAX+(sn)]) -#define ieee754sp_min(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PMIN+(sn)]) -#define ieee754sp_mind(sn) \ - (ieee754sp_spcvals[IEEE754_SPCVAL_PMIND+(sn)]) -#define ieee754sp_1e31() \ - (ieee754sp_spcvals[IEEE754_SPCVAL_P1E31]) -#define ieee754sp_1e63() \ - (ieee754sp_spcvals[IEEE754_SPCVAL_P1E63]) - -/* indefinite integer value -*/ -#define ieee754si_indef() INT_MIN -#ifdef LONG_LONG_MIN -#define ieee754di_indef() LONG_LONG_MIN -#else -#define ieee754di_indef() (-9223372036854775807LL-1) -#endif - -/* IEEE exception context, passed to handler */ -struct ieee754xctx { - const char *op; /* operation name */ - int rt; /* result type */ - union { - ieee754sp sp; /* single precision */ - ieee754dp dp; /* double precision */ -#ifdef IEEE854_XP - ieee754xp xp; /* extended precision */ -#endif - int si; /* standard signed integer (32bits) */ - long long di; /* extended signed integer (64bits) */ - } rv; /* default result format implied by op */ - va_list ap; -}; - -/* result types for xctx.rt */ -#define IEEE754_RT_SP 0 -#define IEEE754_RT_DP 1 -#define IEEE754_RT_XP 2 -#define IEEE754_RT_SI 3 -#define IEEE754_RT_DI 4 - -extern void ieee754_xcpt(struct ieee754xctx *xcp); - -/* compat */ -#define ieee754dp_fix(x) ieee754dp_tint(x) -#define ieee754sp_fix(x) ieee754sp_tint(x) --- linux-2.5.73/arch/mips64/math-emu/ieee754int.h 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,135 +0,0 @@ -/* - * IEEE754 floating point - * common internal header file - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754.h" - -#define DP_EBIAS 1023 -#define DP_EMIN (-1022) -#define DP_EMAX 1023 -#define DP_MBITS 52 - -#define SP_EBIAS 127 -#define SP_EMIN (-126) -#define SP_EMAX 127 -#define SP_MBITS 23 - -#define DP_MBIT(x) ((unsigned long long)1 << (x)) -#define DP_HIDDEN_BIT DP_MBIT(DP_MBITS) -#define DP_SIGN_BIT DP_MBIT(63) - -#define SP_MBIT(x) ((unsigned long)1 << (x)) -#define SP_HIDDEN_BIT SP_MBIT(SP_MBITS) -#define SP_SIGN_BIT SP_MBIT(31) - - -#define SPSIGN(sp) (sp.parts.sign) -#define SPBEXP(sp) (sp.parts.bexp) -#define SPMANT(sp) (sp.parts.mant) - -#define DPSIGN(dp) (dp.parts.sign) -#define DPBEXP(dp) (dp.parts.bexp) -#define DPMANT(dp) (dp.parts.mant) - -#define CLPAIR(x,y) ((x)*6+(y)) - -#define CLEARCX \ - (ieee754_csr.cx = 0) - -#define SETCX(x) \ - (ieee754_csr.cx |= (x),ieee754_csr.sx |= (x),ieee754_csr.mx & (x)) - -#define TSTX() \ - (ieee754_csr.cx & ieee754_csr.mx) - - -#define COMPXSP \ - unsigned xm; int xe; int xs; int xc - -#define COMPYSP \ - unsigned ym; int ye; int ys; int yc - -#define EXPLODESP(v,vc,vs,ve,vm) \ -{\ - vs = SPSIGN(v);\ - ve = SPBEXP(v);\ - vm = SPMANT(v);\ - if(ve == SP_EMAX+1+SP_EBIAS){\ - if(vm == 0)\ - vc = IEEE754_CLASS_INF;\ - else if(vm & SP_MBIT(SP_MBITS-1)) \ - vc = IEEE754_CLASS_QNAN;\ - else \ - vc = IEEE754_CLASS_SNAN;\ - } else if(ve == SP_EMIN-1+SP_EBIAS) {\ - if(vm) {\ - ve = SP_EMIN;\ - vc = IEEE754_CLASS_DNORM;\ - } else\ - vc = IEEE754_CLASS_ZERO;\ - } else {\ - ve -= SP_EBIAS;\ - vm |= SP_HIDDEN_BIT;\ - vc = IEEE754_CLASS_NORM;\ - }\ -} -#define EXPLODEXSP EXPLODESP(x,xc,xs,xe,xm) -#define EXPLODEYSP EXPLODESP(y,yc,ys,ye,ym) - - -#define COMPXDP \ -unsigned long long xm; int xe; int xs; int xc - -#define COMPYDP \ -unsigned long long ym; int ye; int ys; int yc - -#define EXPLODEDP(v,vc,vs,ve,vm) \ -{\ - vm = DPMANT(v);\ - vs = DPSIGN(v);\ - ve = DPBEXP(v);\ - if(ve == DP_EMAX+1+DP_EBIAS){\ - if(vm == 0)\ - vc = IEEE754_CLASS_INF;\ - else if(vm & DP_MBIT(DP_MBITS-1)) \ - vc = IEEE754_CLASS_QNAN;\ - else \ - vc = IEEE754_CLASS_SNAN;\ - } else if(ve == DP_EMIN-1+DP_EBIAS) {\ - if(vm) {\ - ve = DP_EMIN;\ - vc = IEEE754_CLASS_DNORM;\ - } else\ - vc = IEEE754_CLASS_ZERO;\ - } else {\ - ve -= DP_EBIAS;\ - vm |= DP_HIDDEN_BIT;\ - vc = IEEE754_CLASS_NORM;\ - }\ -} -#define EXPLODEXDP EXPLODEDP(x,xc,xs,xe,xm) -#define EXPLODEYDP EXPLODEDP(y,yc,ys,ye,ym) --- linux-2.5.73/arch/mips64/math-emu/ieee754m.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,56 +0,0 @@ -/* - * floor, trunc, ceil - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754.h" - -ieee754dp ieee754dp_floor(ieee754dp x) -{ - ieee754dp i; - - if (ieee754dp_lt(ieee754dp_modf(x, &i), ieee754dp_zero(0))) - return ieee754dp_sub(i, ieee754dp_one(0)); - else - return i; -} - -ieee754dp ieee754dp_ceil(ieee754dp x) -{ - ieee754dp i; - - if (ieee754dp_gt(ieee754dp_modf(x, &i), ieee754dp_zero(0))) - return ieee754dp_add(i, ieee754dp_one(0)); - else - return i; -} - -ieee754dp ieee754dp_trunc(ieee754dp x) -{ - ieee754dp i; - - (void) ieee754dp_modf(x, &i); - return i; -} --- linux-2.5.73/arch/mips64/math-emu/ieee754sp.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,197 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -int ieee754sp_class(ieee754sp x) -{ - COMPXSP; - EXPLODEXSP; - return xc; -} - -int ieee754sp_isnan(ieee754sp x) -{ - return ieee754sp_class(x) >= IEEE754_CLASS_SNAN; -} - -int ieee754sp_issnan(ieee754sp x) -{ - assert(ieee754sp_isnan(x)); - if (ieee754_csr.noq) - return 1; - return !(SPMANT(x) & SP_MBIT(SP_MBITS - 1)); -} - - -ieee754sp ieee754sp_xcpt(ieee754sp r, const char *op, ...) -{ - struct ieee754xctx ax; - - if (!TSTX()) - return r; - - ax.op = op; - ax.rt = IEEE754_RT_SP; - ax.rv.sp = r; - va_start(ax.ap, op); - ieee754_xcpt(&ax); - return ax.rv.sp; -} - -ieee754sp ieee754sp_nanxcpt(ieee754sp r, const char *op, ...) -{ - struct ieee754xctx ax; - - assert(ieee754sp_isnan(r)); - - if (!ieee754sp_issnan(r)) /* QNAN does not cause invalid op !! */ - return r; - - if (!SETCX(IEEE754_INVALID_OPERATION)) { - /* not enabled convert to a quiet NaN */ - if (ieee754_csr.noq) - return r; - SPMANT(r) |= SP_MBIT(SP_MBITS - 1); - return r; - } - - ax.op = op; - ax.rt = 0; - ax.rv.sp = r; - va_start(ax.ap, op); - ieee754_xcpt(&ax); - return ax.rv.sp; -} - -ieee754sp ieee754sp_bestnan(ieee754sp x, ieee754sp y) -{ - assert(ieee754sp_isnan(x)); - assert(ieee754sp_isnan(y)); - - if (SPMANT(x) > SPMANT(y)) - return x; - else - return y; -} - - -/* generate a normal/denormal number with over,under handling - * sn is sign - * xe is an unbiased exponent - * xm is 3bit extended precision value. - */ -ieee754sp ieee754sp_format(int sn, int xe, unsigned xm) -{ - assert(xm); /* we don't gen exact zeros (probably should) */ - - assert((xm >> (SP_MBITS + 1 + 3)) == 0); /* no execess */ - assert(xm & (SP_HIDDEN_BIT << 3)); - - if (xe < SP_EMIN) { - /* strip lower bits */ - int es = SP_EMIN - xe; - - if (ieee754_csr.nod) { - SETCX(IEEE754_UNDERFLOW); - return ieee754sp_zero(sn); - } - - /* sticky right shift es bits - */ - SPXSRSXn(es); - - assert((xm & (SP_HIDDEN_BIT << 3)) == 0); - assert(xe == SP_EMIN); - } - if (xm & (SP_MBIT(3) - 1)) { - SETCX(IEEE754_INEXACT); - /* inexact must round of 3 bits - */ - switch (ieee754_csr.rm) { - case IEEE754_RZ: - break; - case IEEE754_RN: - xm += 0x3 + ((xm >> 3) & 1); - /* xm += (xm&0x8)?0x4:0x3 */ - break; - case IEEE754_RU: /* toward +Infinity */ - if (!sn) /* ?? */ - xm += 0x8; - break; - case IEEE754_RD: /* toward -Infinity */ - if (sn) /* ?? */ - xm += 0x8; - break; - } - /* adjust exponent for rounding add overflowing - */ - if (xm >> (SP_MBITS + 1 + 3)) { /* add causes mantissa overflow */ - xm >>= 1; - xe++; - } - } - /* strip grs bits */ - xm >>= 3; - - assert((xm >> (SP_MBITS + 1)) == 0); /* no execess */ - assert(xe >= SP_EMIN); - - if (xe > SP_EMAX) { - SETCX(IEEE754_OVERFLOW); - /* -O can be table indexed by (rm,sn) */ - switch (ieee754_csr.rm) { - case IEEE754_RN: - return ieee754sp_inf(sn); - case IEEE754_RZ: - return ieee754sp_max(sn); - case IEEE754_RU: /* toward +Infinity */ - if (sn == 0) - return ieee754sp_inf(0); - else - return ieee754sp_max(1); - case IEEE754_RD: /* toward -Infinity */ - if (sn == 0) - return ieee754sp_max(0); - else - return ieee754sp_inf(1); - } - } - /* gen norm/denorm/zero */ - - if ((xm & SP_HIDDEN_BIT) == 0) { - /* we underflow (tiny/zero) */ - assert(xe == SP_EMIN); - SETCX(IEEE754_UNDERFLOW); - return buildsp(sn, SP_EMIN - 1 + SP_EBIAS, xm); - } else { - assert((xm >> (SP_MBITS + 1)) == 0); /* no execess */ - assert(xm & SP_HIDDEN_BIT); - - return buildsp(sn, xe + SP_EBIAS, xm & ~SP_HIDDEN_BIT); - } -} --- linux-2.5.73/arch/mips64/math-emu/ieee754sp.h 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,89 +0,0 @@ -/* - * IEEE754 floating point - * double precision internal header file - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754int.h" - -#define assert(expr) ((void)0) - -/* 3bit extended single precision sticky right shift */ -#define SPXSRSXn(rs) \ - (xe += rs, \ - xm = (rs > (SP_MBITS+3))?1:((xm) >> (rs)) | ((xm) << (32-(rs)) != 0)) - -#define SPXSRSX1() \ - (xe++, (xm = (xm >> 1) | (xm & 1))) - -#define SPXSRSYn(rs) \ - (ye+=rs, \ - ym = (rs > (SP_MBITS+3))?1:((ym) >> (rs)) | ((ym) << (32-(rs)) != 0)) - -#define SPXSRSY1() \ - (ye++, (ym = (ym >> 1) | (ym & 1))) - -/* convert denormal to normalized with extended exponent */ -#define SPDNORMx(m,e) \ - while( (m >> SP_MBITS) == 0) { m <<= 1; e--; } -#define SPDNORMX SPDNORMx(xm,xe) -#define SPDNORMY SPDNORMx(ym,ye) - -static __inline ieee754sp buildsp(int s, int bx, unsigned m) -{ - ieee754sp r; - - assert((s) == 0 || (s) == 1); - assert((bx) >= SP_EMIN - 1 + SP_EBIAS - && (bx) <= SP_EMAX + 1 + SP_EBIAS); - assert(((m) >> SP_MBITS) == 0); - - r.parts.sign = s; - r.parts.bexp = bx; - r.parts.mant = m; - - return r; -} - -extern int ieee754sp_isnan(ieee754sp); -extern int ieee754sp_issnan(ieee754sp); -extern int ieee754si_xcpt(int, const char *, ...); -extern long long ieee754di_xcpt(long long, const char *, ...); -extern ieee754sp ieee754sp_xcpt(ieee754sp, const char *, ...); -extern ieee754sp ieee754sp_nanxcpt(ieee754sp, const char *, ...); -extern ieee754sp ieee754sp_bestnan(ieee754sp, ieee754sp); -extern ieee754sp ieee754sp_format(int, int, unsigned); - - -#define SPNORMRET2(s,e,m,name,a0,a1) \ -{ \ - ieee754sp V = ieee754sp_format(s,e,m); \ - if(TSTX()) \ - return ieee754sp_xcpt(V,name,a0,a1); \ - else \ - return V; \ -} - -#define SPNORMRET1(s,e,m,name,a0) SPNORMRET2(s,e,m,name,a0,a0) --- linux-2.5.73/arch/mips64/math-emu/ieee754xcpt.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,48 +0,0 @@ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - -/************************************************************************** - * Nov 7, 2000 - * Added preprocessor hacks to map to Linux kernel diagnostics. - * - * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - *************************************************************************/ - -#include "ieee754.h" - -/* - * Very naff exception handler (you can plug in your own and - * override this). - */ - -static const char *const rtnames[] = { - "sp", "dp", "xp", "si", "di" -}; - -void ieee754_xcpt(struct ieee754xctx *xcp) -{ - printk("floating point exception in \"%s\", type=%s\n", - xcp->op, rtnames[xcp->rt]); -} - --- linux-2.5.73/arch/mips64/math-emu/kernel_linkage.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,95 +0,0 @@ -/************************************************************************** - * - * arch/mips/math_emu/kernel_linkage.c - * - * Kevin D. Kissell, kevink@mips and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - *************************************************************************/ -/* - * Routines corresponding to Linux kernel FP context - * manipulation primitives for the Algorithmics MIPS - * FPU Emulator - */ - -#include -#include -#include -#include - -#include - -extern struct mips_fpu_emulator_private fpuemuprivate; - -#define SIGNALLING_NAN 0x7ff800007ff80000LL - -void fpu_emulator_init_fpu(void) -{ - static int first = 1; - int i; - - if (first) { - first = 0; - printk("Algorithmics/MIPS FPU Emulator v1.4\n"); - } - - current->thread.fpu.soft.sr = 0; - for (i = 0; i < 32; i++) { - current->thread.fpu.soft.regs[i] = SIGNALLING_NAN; - } -} - - -/* - * Emulator context save/restore to/from a signal context - * presumed to be on the user stack, and therefore accessed - * with appropriate macros from uaccess.h - */ - -int fpu_emulator_save_context(struct sigcontext *sc) -{ - int i; - int err = 0; - - for (i = 0; i < 32; i++) { - err |= - __put_user(current->thread.fpu.soft.regs[i], - &sc->sc_fpregs[i]); - } - err |= __put_user(current->thread.fpu.soft.sr, &sc->sc_fpc_csr); - err |= __put_user(fpuemuprivate.eir, &sc->sc_fpc_eir); - - return err; -} - -int fpu_emulator_restore_context(struct sigcontext *sc) -{ - int i; - int err = 0; - - for (i = 0; i < 32; i++) { - err |= - __get_user(current->thread.fpu.soft.regs[i], - &sc->sc_fpregs[i]); - } - err |= __get_user(current->thread.fpu.soft.sr, &sc->sc_fpc_csr); - err |= __get_user(fpuemuprivate.eir, &sc->sc_fpc_eir); - - return err; -} - --- linux-2.5.73/arch/mips64/math-emu/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,11 +0,0 @@ -# -# Makefile for the Linux/MIPS kernel FPU emulation. -# - -obj-y := cp1emu.o ieee754m.o ieee754d.o ieee754dp.o ieee754sp.o ieee754.o \ - ieee754xcpt.o dp_frexp.o dp_modf.o dp_div.o dp_mul.o dp_sub.o \ - dp_add.o dp_fsp.o dp_cmp.o dp_logb.o dp_scalb.o dp_simple.o \ - dp_tint.o dp_fint.o dp_tlong.o dp_flong.o sp_frexp.o sp_modf.o \ - sp_div.o sp_mul.o sp_sub.o sp_add.o sp_fdp.o sp_cmp.o sp_logb.o \ - sp_scalb.o sp_simple.o sp_tint.o sp_fint.o sp_tlong.o sp_flong.o \ - dp_sqrt.o sp_sqrt.o kernel_linkage.o --- linux-2.5.73/arch/mips64/math-emu/sp_add.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,180 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -ieee754sp ieee754sp_add(ieee754sp x, ieee754sp y) -{ - COMPXSP; - COMPYSP; - - EXPLODEXSP; - EXPLODEYSP; - - CLEARCX; - - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(ieee754sp_bestnan(x, y), "add", x, - y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(y, "add", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754sp_nanxcpt(x, "add", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754sp_bestnan(x, y); - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): - return y; - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF): - return x; - - - /* Inifity handling - */ - - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): - if (xs == ys) - return x; - SETCX(IEEE754_INVALID_OPERATION); - return ieee754sp_xcpt(ieee754sp_indef(), "add", x, y); - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF): - return y; - - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): - return x; - - /* Zero handling - */ - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): - if (xs == ys) - return x; - else - return ieee754sp_zero(ieee754_csr.rm == - IEEE754_RD); - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO): - return x; - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM): - return y; - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM): - SPDNORMX; - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM): - SPDNORMY; - break; - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM): - SPDNORMX; - break; - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM): - break; - } - assert(xm & SP_HIDDEN_BIT); - assert(ym & SP_HIDDEN_BIT); - - /* provide guard,round and stick bit space */ - xm <<= 3; - ym <<= 3; - - if (xe > ye) { - /* have to shift y fraction right to align - */ - int s = xe - ye; - SPXSRSYn(s); - } else if (ye > xe) { - /* have to shift x fraction right to align - */ - int s = ye - xe; - SPXSRSXn(s); - } - assert(xe == ye); - assert(xe <= SP_EMAX); - - if (xs == ys) { - /* generate 28 bit result of adding two 27 bit numbers - * leaving result in xm,xs,xe - */ - xm = xm + ym; - xe = xe; - xs = xs; - - if (xm >> (SP_MBITS + 1 + 3)) { /* carry out */ - SPXSRSX1(); - } - } else { - if (xm >= ym) { - xm = xm - ym; - xe = xe; - xs = xs; - } else { - xm = ym - xm; - xe = xe; - xs = ys; - } - if (xm == 0) - return ieee754sp_zero(ieee754_csr.rm == - IEEE754_RD); - - /* normalize in extended single precision */ - while ((xm >> (SP_MBITS + 3)) == 0) { - xm <<= 1; - xe--; - } - - } - SPNORMRET2(xs, xe, xm, "add", x, y); -} --- linux-2.5.73/arch/mips64/math-emu/sp_cmp.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,58 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -int ieee754sp_cmp(ieee754sp x, ieee754sp y, int cmp) -{ - CLEARCX; - - if (ieee754sp_isnan(x) || ieee754sp_isnan(y)) { - if (cmp & IEEE754_CUN) - return 1; - if (cmp & (IEEE754_CLT | IEEE754_CGT)) { - if (SETCX(IEEE754_INVALID_OPERATION)) - return ieee754si_xcpt(0, "fcmpf", x); - } - return 0; - } else { - int vx = x.bits; - int vy = y.bits; - - if (vx < 0) - vx = -vx ^ SP_SIGN_BIT; - if (vy < 0) - vy = -vy ^ SP_SIGN_BIT; - - if (vx < vy) - return (cmp & IEEE754_CLT) != 0; - else if (vx == vy) - return (cmp & IEEE754_CEQ) != 0; - else - return (cmp & IEEE754_CGT) != 0; - } -} --- linux-2.5.73/arch/mips64/math-emu/sp_div.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,160 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -ieee754sp ieee754sp_div(ieee754sp x, ieee754sp y) -{ - COMPXSP; - COMPYSP; - - CLEARCX; - - EXPLODEXSP; - EXPLODEYSP; - - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(ieee754sp_bestnan(x, y), "div", x, - y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(y, "div", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754sp_nanxcpt(x, "div", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754sp_bestnan(x, y); - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): - return y; - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF): - return x; - - - /* Infinity handling - */ - - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): - SETCX(IEEE754_INVALID_OPERATION); - return ieee754sp_xcpt(ieee754sp_indef(), "div", x, y); - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF): - return ieee754sp_zero(xs ^ ys); - - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): - return ieee754sp_inf(xs ^ ys); - - /* Zero handling - */ - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): - SETCX(IEEE754_INVALID_OPERATION); - return ieee754sp_xcpt(ieee754sp_indef(), "div", x, y); - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO): - SETCX(IEEE754_ZERO_DIVIDE); - return ieee754sp_xcpt(ieee754sp_inf(xs ^ ys), "div", x, y); - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM): - return ieee754sp_zero(xs == ys ? 0 : 1); - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM): - SPDNORMX; - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM): - SPDNORMY; - break; - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM): - SPDNORMX; - break; - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM): - break; - } - assert(xm & SP_HIDDEN_BIT); - assert(ym & SP_HIDDEN_BIT); - - /* provide rounding space */ - xm <<= 3; - ym <<= 3; - - { - /* now the dirty work */ - - unsigned rm = 0; - int re = xe - ye; - unsigned bm; - - for (bm = SP_MBIT(SP_MBITS + 2); bm; bm >>= 1) { - if (xm >= ym) { - xm -= ym; - rm |= bm; - if (xm == 0) - break; - } - xm <<= 1; - } - rm <<= 1; - if (xm) - rm |= 1; /* have remainder, set sticky */ - - assert(rm); - - /* normalise rm to rounding precision ? - */ - while ((rm >> (SP_MBITS + 3)) == 0) { - rm <<= 1; - re--; - } - - SPNORMRET2(xs == ys ? 0 : 1, re, rm, "div", x, y); - } -} --- linux-2.5.73/arch/mips64/math-emu/sp_fdp.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,69 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -ieee754sp ieee754sp_fdp(ieee754dp x) -{ - COMPXDP; - - CLEARCX; - - EXPLODEXDP; - - switch (xc) { - case IEEE754_CLASS_QNAN: - case IEEE754_CLASS_SNAN: - return ieee754sp_nanxcpt(buildsp(xs, - SP_EMAX + 1 + SP_EBIAS, - (unsigned long) - (xm >> - (DP_MBITS - SP_MBITS))), - "fdp", x); - case IEEE754_CLASS_INF: - return ieee754sp_inf(xs); - case IEEE754_CLASS_ZERO: - return ieee754sp_zero(xs); - case IEEE754_CLASS_DNORM: - /* can't possibly be sp representable */ - SETCX(IEEE754_UNDERFLOW); - return ieee754sp_xcpt(ieee754sp_zero(xs), "fdp", x); - case IEEE754_CLASS_NORM: - break; - } - - { - unsigned long rm; - - /* convert from DP_MBITS to SP_MBITS+3 with sticky right shift - */ - rm = (xm >> (DP_MBITS - (SP_MBITS + 3))) | - ((xm << (64 - (DP_MBITS - (SP_MBITS + 3)))) != 0); - - SPNORMRET1(xs, xe, rm, "fdp", x); - } -} --- linux-2.5.73/arch/mips64/math-emu/sp_fint.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,78 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -ieee754sp ieee754sp_fint(int x) -{ - COMPXSP; - - CLEARCX; - - if (x == 0) - return ieee754sp_zero(0); - if (x == 1 || x == -1) - return ieee754sp_one(x < 0); - if (x == 10 || x == -10) - return ieee754sp_ten(x < 0); - - xs = (x < 0); - if (xs) { - if (x == (1 << 31)) - xm = ((unsigned) 1 << 31); /* max neg can't be safely negated */ - else - xm = -x; - } else { - xm = x; - } - xe = SP_MBITS + 3; - - if (xm >> (SP_MBITS + 1 + 3)) { - /* shunt out overflow bits - */ - while (xm >> (SP_MBITS + 1 + 3)) { - SPXSRSX1(); - } - } else { - /* normalize in grs extended single precision - */ - while ((xm >> (SP_MBITS + 3)) == 0) { - xm <<= 1; - xe--; - } - } - SPNORMRET1(xs, xe, xm, "fint", x); -} - - -ieee754sp ieee754sp_funs(unsigned int u) -{ - if ((int) u < 0) - return ieee754sp_add(ieee754sp_1e31(), - ieee754sp_fint(u & ~(1 << 31))); - return ieee754sp_fint(u); -} --- linux-2.5.73/arch/mips64/math-emu/sp_flong.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,77 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -ieee754sp ieee754sp_flong(long long x) -{ - COMPXDP; /* <--- need 64-bit mantissa temp */ - - CLEARCX; - - if (x == 0) - return ieee754sp_zero(0); - if (x == 1 || x == -1) - return ieee754sp_one(x < 0); - if (x == 10 || x == -10) - return ieee754sp_ten(x < 0); - - xs = (x < 0); - if (xs) { - if (x == (1ULL << 63)) - xm = (1ULL << 63); /* max neg can't be safely negated */ - else - xm = -x; - } else { - xm = x; - } - xe = SP_MBITS + 3; - - if (xm >> (SP_MBITS + 1 + 3)) { - /* shunt out overflow bits - */ - while (xm >> (SP_MBITS + 1 + 3)) { - SPXSRSX1(); - } - } else { - /* normalize in grs extended single precision */ - while ((xm >> (SP_MBITS + 3)) == 0) { - xm <<= 1; - xe--; - } - } - SPNORMRET1(xs, xe, xm, "sp_flong", x); -} - - -ieee754sp ieee754sp_fulong(unsigned long long u) -{ - if ((long long) u < 0) - return ieee754sp_add(ieee754sp_1e63(), - ieee754sp_flong(u & ~(1ULL << 63))); - return ieee754sp_flong(u); -} --- linux-2.5.73/arch/mips64/math-emu/sp_frexp.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,53 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -/* close to ieeep754sp_logb -*/ -ieee754sp ieee754sp_frexp(ieee754sp x, int *eptr) -{ - COMPXSP; - CLEARCX; - EXPLODEXSP; - - switch (xc) { - case IEEE754_CLASS_SNAN: - case IEEE754_CLASS_QNAN: - case IEEE754_CLASS_INF: - case IEEE754_CLASS_ZERO: - *eptr = 0; - return x; - case IEEE754_CLASS_DNORM: - SPDNORMX; - break; - case IEEE754_CLASS_NORM: - break; - } - *eptr = xe + 1; - return buildsp(xs, -1 + SP_EBIAS, xm & ~SP_HIDDEN_BIT); -} --- linux-2.5.73/arch/mips64/math-emu/sp_logb.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,54 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -ieee754sp ieee754sp_logb(ieee754sp x) -{ - COMPXSP; - - CLEARCX; - - EXPLODEXSP; - - switch (xc) { - case IEEE754_CLASS_SNAN: - return ieee754sp_nanxcpt(x, "logb", x); - case IEEE754_CLASS_QNAN: - return x; - case IEEE754_CLASS_INF: - return ieee754sp_inf(0); - case IEEE754_CLASS_ZERO: - return ieee754sp_inf(1); - case IEEE754_CLASS_DNORM: - SPDNORMX; - break; - case IEEE754_CLASS_NORM: - break; - } - return ieee754sp_fint(xe); -} --- linux-2.5.73/arch/mips64/math-emu/sp_modf.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,80 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -/* modf function is always exact for a finite number -*/ -ieee754sp ieee754sp_modf(ieee754sp x, ieee754sp * ip) -{ - COMPXSP; - - CLEARCX; - - EXPLODEXSP; - - switch (xc) { - case IEEE754_CLASS_SNAN: - case IEEE754_CLASS_QNAN: - case IEEE754_CLASS_INF: - case IEEE754_CLASS_ZERO: - *ip = x; - return x; - case IEEE754_CLASS_DNORM: - /* far to small */ - *ip = ieee754sp_zero(xs); - return x; - case IEEE754_CLASS_NORM: - break; - } - if (xe < 0) { - *ip = ieee754sp_zero(xs); - return x; - } - if (xe >= SP_MBITS) { - *ip = x; - return ieee754sp_zero(xs); - } - /* generate ipart mantissa by clearing bottom bits - */ - *ip = buildsp(xs, xe + SP_EBIAS, - ((xm >> (SP_MBITS - xe)) << (SP_MBITS - xe)) & - ~SP_HIDDEN_BIT); - - /* generate fpart mantissa by clearing top bits - * and normalizing (must be able to normalize) - */ - xm = (xm << (32 - (SP_MBITS - xe))) >> (32 - (SP_MBITS - xe)); - if (xm == 0) - return ieee754sp_zero(xs); - - while ((xm >> SP_MBITS) == 0) { - xm <<= 1; - xe--; - } - return buildsp(xs, xe + SP_EBIAS, xm & ~SP_HIDDEN_BIT); -} --- linux-2.5.73/arch/mips64/math-emu/sp_mul.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,174 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -ieee754sp ieee754sp_mul(ieee754sp x, ieee754sp y) -{ - COMPXSP; - COMPYSP; - - CLEARCX; - - EXPLODEXSP; - EXPLODEYSP; - - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(ieee754sp_bestnan(x, y), "mul", x, - y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(y, "mul", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754sp_nanxcpt(x, "mul", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754sp_bestnan(x, y); - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): - return y; - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF): - return x; - - - /* Infinity handling */ - - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF): - SETCX(IEEE754_INVALID_OPERATION); - return ieee754sp_xcpt(ieee754sp_indef(), "mul", x, y); - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): - return ieee754sp_inf(xs ^ ys); - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO): - return ieee754sp_zero(xs ^ ys); - - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM): - SPDNORMX; - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM): - SPDNORMY; - break; - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM): - SPDNORMX; - break; - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM): - break; - } - /* rm = xm * ym, re = xe+ye basicly */ - assert(xm & SP_HIDDEN_BIT); - assert(ym & SP_HIDDEN_BIT); - - { - int re = xe + ye; - int rs = xs ^ ys; - unsigned rm; - - /* shunt to top of word */ - xm <<= 32 - (SP_MBITS + 1); - ym <<= 32 - (SP_MBITS + 1); - - /* multiply 32bits xm,ym to give high 32bits rm with stickness - */ - { - unsigned short lxm = xm & 0xffff; - unsigned short hxm = xm >> 16; - unsigned short lym = ym & 0xffff; - unsigned short hym = ym >> 16; - unsigned lrm; - unsigned hrm; - - lrm = lxm * lym; /* 16 * 16 => 32 */ - hrm = hxm * hym; /* 16 * 16 => 32 */ - - { - unsigned t = lxm * hym; /* 16 * 16 => 32 */ - { - unsigned at = lrm + (t << 16); - hrm += at < lrm; - lrm = at; - } - hrm = hrm + (t >> 16); - } - - { - unsigned t = hxm * lym; /* 16 * 16 => 32 */ - { - unsigned at = lrm + (t << 16); - hrm += at < lrm; - lrm = at; - } - hrm = hrm + (t >> 16); - } - rm = hrm | (lrm != 0); - } - - /* - * sticky shift down to normal rounding precision - */ - if ((int) rm < 0) { - rm = (rm >> (32 - (SP_MBITS + 1 + 3))) | - ((rm << (SP_MBITS + 1 + 3)) != 0); - re++; - } else { - rm = (rm >> (32 - (SP_MBITS + 1 + 3 + 1))) | - ((rm << (SP_MBITS + 1 + 3 + 1)) != 0); - } - assert(rm & (SP_HIDDEN_BIT << 3)); - - SPNORMRET2(rs, re, rm, "mul", x, y); - } -} --- linux-2.5.73/arch/mips64/math-emu/sp_scalb.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,58 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -ieee754sp ieee754sp_scalb(ieee754sp x, int n) -{ - COMPXSP; - - CLEARCX; - - EXPLODEXSP; - - switch (xc) { - case IEEE754_CLASS_SNAN: - return ieee754sp_nanxcpt(x, "scalb", x, n); - case IEEE754_CLASS_QNAN: - case IEEE754_CLASS_INF: - case IEEE754_CLASS_ZERO: - return x; - case IEEE754_CLASS_DNORM: - SPDNORMX; - break; - case IEEE754_CLASS_NORM: - break; - } - SPNORMRET2(xs, xe + n, xm << 3, "scalb", x, n); -} - - -ieee754sp ieee754sp_ldexp(ieee754sp x, int n) -{ - return ieee754sp_scalb(x, n); -} --- linux-2.5.73/arch/mips64/math-emu/sp_simple.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,66 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -int ieee754sp_finite(ieee754sp x) -{ - return SPBEXP(x) != SP_EMAX + 1 + SP_EBIAS; -} - -ieee754sp ieee754sp_copysign(ieee754sp x, ieee754sp y) -{ - CLEARCX; - SPSIGN(x) = SPSIGN(y); - return x; -} - - -ieee754sp ieee754sp_neg(ieee754sp x) -{ - CLEARCX; - - if (ieee754sp_isnan(x)) /* but not infinity */ - return ieee754sp_nanxcpt(x, "neg", x); - - /* quick fix up */ - SPSIGN(x) ^= 1; - return x; -} - - -ieee754sp ieee754sp_abs(ieee754sp x) -{ - CLEARCX; - - if (ieee754sp_isnan(x)) /* but not infinity */ - return ieee754sp_nanxcpt(x, "abs", x); - - /* quick fix up */ - SPSIGN(x) = 0; - return x; -} --- linux-2.5.73/arch/mips64/math-emu/sp_sqrt.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,115 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision square root - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -static const struct ieee754sp_konst knan = { - 0, SP_EBIAS + SP_EMAX + 1, 0 -}; - -#define nan ((ieee754sp)knan) - -ieee754sp ieee754sp_sqrt(ieee754sp x) -{ - int sign = (int) 0x80000000; - int ix, s, q, m, t, i; - unsigned int r; - COMPXDP; - - /* take care of Inf and NaN */ - - EXPLODEXDP; - - /* x == INF or NAN? */ - switch (xc) { - case IEEE754_CLASS_QNAN: - case IEEE754_CLASS_SNAN: - /* sqrt(Nan) = Nan */ - return ieee754sp_nanxcpt(x, "sqrt"); - case IEEE754_CLASS_ZERO: - /* sqrt(0) = 0 */ - return x; - case IEEE754_CLASS_INF: - if (xs) - /* sqrt(-Inf) = Nan */ - return ieee754sp_nanxcpt(nan, "sqrt"); - /* sqrt(+Inf) = Inf */ - return x; - case IEEE754_CLASS_DNORM: - case IEEE754_CLASS_NORM: - if (xs) - /* sqrt(-x) = Nan */ - return ieee754sp_nanxcpt(nan, "sqrt"); - break; - } - - ix = x.bits; - - /* normalize x */ - m = (ix >> 23); - if (m == 0) { /* subnormal x */ - for (i = 0; (ix & 0x00800000) == 0; i++) - ix <<= 1; - m -= i - 1; - } - m -= 127; /* unbias exponent */ - ix = (ix & 0x007fffff) | 0x00800000; - if (m & 1) /* odd m, double x to make it even */ - ix += ix; - m >>= 1; /* m = [m/2] */ - - /* generate sqrt(x) bit by bit */ - ix += ix; - q = s = 0; /* q = sqrt(x) */ - r = 0x01000000; /* r = moving bit from right to left */ - - while (r != 0) { - t = s + r; - if (t <= ix) { - s = t + r; - ix -= t; - q += r; - } - ix += ix; - r >>= 1; - } - - if (ix != 0) { - switch (ieee754_csr.rm) { - case IEEE754_RP: - q += 2; - break; - case IEEE754_RN: - q += (q & 1); - break; - } - } - ix = (q >> 1) + 0x3f000000; - ix += (m << 23); - x.bits = ix; - return x; -} --- linux-2.5.73/arch/mips64/math-emu/sp_sub.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,187 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -ieee754sp ieee754sp_sub(ieee754sp x, ieee754sp y) -{ - COMPXSP; - COMPYSP; - - CLEARCX; - - EXPLODEXSP; - EXPLODEYSP; - - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(ieee754sp_bestnan(x, y), "sub", x, - y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(y, "sub", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754sp_nanxcpt(x, "sub", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754sp_bestnan(x, y); - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): - return y; - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF): - return x; - - - /* Inifity handling - */ - - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): - if (xs != ys) - return x; - SETCX(IEEE754_INVALID_OPERATION); - return ieee754sp_xcpt(ieee754sp_indef(), "sub", x, y); - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF): - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF): - return ieee754sp_inf(ys ^ 1); - - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): - return x; - - /* Zero handling - */ - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): - if (xs != ys) - return x; - else - return ieee754sp_zero(ieee754_csr.rm == - IEEE754_RD); - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO): - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO): - return x; - - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM): - case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM): - /* quick fix up */ - DPSIGN(y) ^= 1; - return y; - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM): - SPDNORMX; - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM): - SPDNORMY; - break; - - case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM): - SPDNORMX; - break; - - case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM): - break; - } - /* flip sign of y and handle as add */ - ys ^= 1; - - assert(xm & SP_HIDDEN_BIT); - assert(ym & SP_HIDDEN_BIT); - - - /* provide guard,round and stick bit space */ - xm <<= 3; - ym <<= 3; - - if (xe > ye) { - /* have to shift y fraction right to align - */ - int s = xe - ye; - SPXSRSYn(s); - } else if (ye > xe) { - /* have to shift x fraction right to align - */ - int s = ye - xe; - SPXSRSXn(s); - } - assert(xe == ye); - assert(xe <= SP_EMAX); - - if (xs == ys) { - /* generate 28 bit result of adding two 27 bit numbers - */ - xm = xm + ym; - xe = xe; - xs = xs; - - if (xm >> (SP_MBITS + 1 + 3)) { /* carry out */ - SPXSRSX1(); /* shift preserving sticky */ - } - } else { - if (xm >= ym) { - xm = xm - ym; - xe = xe; - xs = xs; - } else { - xm = ym - xm; - xe = xe; - xs = ys; - } - if (xm == 0) - if (ieee754_csr.rm == IEEE754_RD) - return ieee754sp_zero(1); /* round negative inf. => sign = -1 */ - else - return ieee754sp_zero(0); /* other round modes => sign = 1 */ - - /* normalize to rounding precision - */ - while ((xm >> (SP_MBITS + 3)) == 0) { - xm <<= 1; - xe--; - } - } - SPNORMRET2(xs, xe, xm, "sub", x, y); -} --- linux-2.5.73/arch/mips64/math-emu/sp_tint.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,88 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include -#include "ieee754sp.h" - -int ieee754sp_tint(ieee754sp x) -{ - COMPXSP; - - CLEARCX; - - EXPLODEXSP; - - switch (xc) { - case IEEE754_CLASS_SNAN: - case IEEE754_CLASS_QNAN: - SETCX(IEEE754_INVALID_OPERATION); - return ieee754si_xcpt(ieee754si_indef(), "fixsp", x); - case IEEE754_CLASS_INF: - SETCX(IEEE754_OVERFLOW); - return ieee754si_xcpt(ieee754si_indef(), "fixsp", x); - case IEEE754_CLASS_ZERO: - return 0; - case IEEE754_CLASS_DNORM: /* much to small */ - SETCX(IEEE754_UNDERFLOW); - return ieee754si_xcpt(0, "fixsp", x); - case IEEE754_CLASS_NORM: - break; - } - if (xe >= 31) { - SETCX(IEEE754_OVERFLOW); - return ieee754si_xcpt(ieee754si_indef(), "fix", x); - } - if (xe < 0) { - SETCX(IEEE754_UNDERFLOW); - return ieee754si_xcpt(0, "fix", x); - } - /* oh gawd */ - if (xe > SP_MBITS) { - xm <<= xe - SP_MBITS; - } else if (xe < SP_MBITS) { - /* XXX no rounding - */ - xm >>= SP_MBITS - xe; - } - if (xs) - return -xm; - else - return xm; -} - - -unsigned int ieee754sp_tuns(ieee754sp x) -{ - ieee754sp hb = ieee754sp_1e31(); - - /* what if x < 0 ?? */ - if (ieee754sp_lt(x, hb)) - return (unsigned) ieee754sp_tint(x); - - return (unsigned) ieee754sp_tint(ieee754sp_sub(x, hb)) | - ((unsigned) 1 << 31); -} --- linux-2.5.73/arch/mips64/math-emu/sp_tlong.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,87 +0,0 @@ -/* IEEE754 floating point arithmetic - * single precision - */ -/* - * MIPS floating point support - * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. - * http://www.algor.co.uk - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - */ - - -#include "ieee754sp.h" - -long long ieee754sp_tlong(ieee754sp x) -{ - COMPXDP; /* <-- need 64-bit mantissa tmp */ - - CLEARCX; - - EXPLODEXSP; - - switch (xc) { - case IEEE754_CLASS_SNAN: - case IEEE754_CLASS_QNAN: - SETCX(IEEE754_INVALID_OPERATION); - return ieee754di_xcpt(ieee754di_indef(), "sp_tlong", x); - case IEEE754_CLASS_INF: - SETCX(IEEE754_OVERFLOW); - return ieee754di_xcpt(ieee754di_indef(), "sp_tlong", x); - case IEEE754_CLASS_ZERO: - return 0; - case IEEE754_CLASS_DNORM: /* much to small */ - SETCX(IEEE754_UNDERFLOW); - return ieee754di_xcpt(0, "sp_tlong", x); - case IEEE754_CLASS_NORM: - break; - } - if (xe >= 63) { - SETCX(IEEE754_OVERFLOW); - return ieee754di_xcpt(ieee754di_indef(), "sp_tlong", x); - } - if (xe < 0) { - SETCX(IEEE754_UNDERFLOW); - return ieee754di_xcpt(0, "sp_tlong", x); - } - /* oh gawd */ - if (xe > SP_MBITS) { - xm <<= xe - SP_MBITS; - } else if (xe < SP_MBITS) { - /* XXX no rounding - */ - xm >>= SP_MBITS - xe; - } - if (xs) - return -xm; - else - return xm; -} - - -unsigned long long ieee754sp_tulong(ieee754sp x) -{ - ieee754sp hb = ieee754sp_1e63(); - - /* what if x < 0 ?? */ - if (ieee754sp_lt(x, hb)) - return (unsigned long long) ieee754sp_tlong(x); - - return (unsigned long long) ieee754sp_tlong(ieee754sp_sub(x, hb)) | - (1ULL << 63); -} --- linux-2.5.73/arch/mips64/mips-boards/atlas/atlas_int.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,255 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Routines for generic manipulation of the interrupts found on the MIPS - * Atlas board. - * - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#ifdef CONFIG_REMOTE_DEBUG -#include -#endif - -struct atlas_ictrl_regs *atlas_hw0_icregs - = (struct atlas_ictrl_regs *)ATLAS_ICTRL_REGS_BASE; - -extern asmlinkage void mipsIRQ(void); -extern void do_IRQ(int irq, struct pt_regs *regs); - -unsigned long spurious_count = 0; -irq_desc_t irq_desc[NR_IRQS]; - -#if 0 -#define DEBUG_INT(x...) printk(x) -#else -#define DEBUG_INT(x...) -#endif - -void disable_atlas_irq(unsigned int irq_nr) -{ - atlas_hw0_icregs->intrsten = (1 << irq_nr); -} - -void enable_atlas_irq(unsigned int irq_nr) -{ - atlas_hw0_icregs->intseten = (1 << irq_nr); -} - -static unsigned int startup_atlas_irq(unsigned int irq) -{ - enable_atlas_irq(irq); - return 0; /* never anything pending */ -} - -#define shutdown_atlas_irq disable_atlas_irq - -#define mask_and_ack_atlas_irq disable_atlas_irq - -static void end_atlas_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_atlas_irq(irq); -} - -static struct hw_interrupt_type atlas_irq_type = { - "Atlas", - startup_atlas_irq, - shutdown_atlas_irq, - enable_atlas_irq, - disable_atlas_irq, - mask_and_ack_atlas_irq, - end_atlas_irq, - NULL -}; - -int show_interrupts(struct seq_file *p, void *v) -{ - int i; - int num = 0; - struct irqaction *action; - unsigned long flags; - - for (i = 0; i < ATLASINT_END; i++, num++) { - spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; - if (!action) - goto unlock; - seq_printf(p, "%2d: %8d %c %s", - num, kstat_cpu(0).irqs[num], - (action->flags & SA_INTERRUPT) ? '+' : ' ', - action->name); - for (action=action->next; action; action = action->next) { - seq_printf(p, ",%s %s", - (action->flags & SA_INTERRUPT) ? " +" : "", - action->name); - } - seq_puts(p, " [hw0]\n"); -unlock: - spin_unlock_irqrestore(&irq_desc[i].lock, flags); - } - return 0; -} - -int request_irq(unsigned int irq, - void (*handler)(int, void *, struct pt_regs *), - unsigned long irqflags, - const char * devname, - void *dev_id) -{ - struct irqaction *action; - - DEBUG_INT("request_irq: irq=%d, devname = %s\n", irq, devname); - - if (irq >= ATLASINT_END) - return -EINVAL; - if (!handler) - return -EINVAL; - - action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL); - if(!action) - return -ENOMEM; - - action->handler = handler; - action->flags = irqflags; - action->mask = 0; - action->name = devname; - action->dev_id = dev_id; - action->next = 0; - irq_desc[irq].action = action; - enable_atlas_irq(irq); - - return 0; -} - -void free_irq(unsigned int irq, void *dev_id) -{ - struct irqaction *action; - - if (irq >= ATLASINT_END) { - printk("Trying to free IRQ%d\n",irq); - return; - } - - action = irq_desc[irq].action; - irq_desc[irq].action = NULL; - disable_atlas_irq(irq); - kfree(action); -} - -static inline int ls1bit32(unsigned int x) -{ - int b = 31, s; - - s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s; - s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s; - s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s; - s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s; - s = 1; if (x << 1 == 0) s = 0; b -= s; - - return b; -} - -void atlas_hw0_irqdispatch(struct pt_regs *regs) -{ - struct irqaction *action; - unsigned long int_status; - int irq, cpu = smp_processor_id(); - - int_status = atlas_hw0_icregs->intstatus; - - /* if int_status == 0, then the interrupt has already been cleared */ - if (int_status == 0) - return; - - irq = ls1bit32(int_status); - action = irq_desc[irq].action; - - DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq); - - /* if action == NULL, then we don't have a handler for the irq */ - if ( action == NULL ) { - printk("No handler for hw0 irq: %i\n", irq); - spurious_count++; - return; - } - - irq_enter(cpu, irq); - kstat_cpu(0).irqs[irq]++; - action->handler(irq, action->dev_id, regs); - irq_exit(cpu, irq); - - return; -} - -unsigned long probe_irq_on (void) -{ - return 0; -} - - -int probe_irq_off (unsigned long irqs) -{ - return 0; -} - -#ifdef CONFIG_REMOTE_DEBUG -extern void breakpoint(void); -extern int remote_debug; -#endif - -void __init init_IRQ(void) -{ - int i; - - /* - * Mask out all interrupt by writing "1" to all bit position in - * the interrupt reset reg. - */ - atlas_hw0_icregs->intrsten = 0xffffffff; - - /* Now safe to set the exception vector. */ - set_except_vector(0, mipsIRQ); - - for (i = 0; i <= ATLASINT_END; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].handler = &atlas_irq_type; - spin_lock_init(&irq_desc[i].lock); - } - -#ifdef CONFIG_REMOTE_DEBUG - if (remote_debug) { - set_debug_traps(); - breakpoint(); - } -#endif -} --- linux-2.5.73/arch/mips64/mips-boards/atlas/atlas_rtc.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,58 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * RTC routines for Atlas style attached Dallas chip. - * - */ -#include -#include - - -static unsigned char atlas_rtc_read_data(unsigned long addr) -{ - volatile unsigned int *rtc_adr_reg = (void *)ATLAS_RTC_ADR_REG; - volatile unsigned int *rtc_dat_reg = (void *)ATLAS_RTC_DAT_REG; - - *rtc_adr_reg = addr; - - return *rtc_dat_reg; -} - -static void atlas_rtc_write_data(unsigned char data, unsigned long addr) -{ - volatile unsigned int *rtc_adr_reg = (void *)ATLAS_RTC_ADR_REG; - volatile unsigned int *rtc_dat_reg = (void *)ATLAS_RTC_DAT_REG; - - *rtc_adr_reg = addr; - *rtc_dat_reg = data; -} - -static int atlas_rtc_bcd_mode(void) -{ - return 0; -} - -struct rtc_ops atlas_rtc_ops = { - &atlas_rtc_read_data, - &atlas_rtc_write_data, - &atlas_rtc_bcd_mode -}; - --- linux-2.5.73/arch/mips64/mips-boards/atlas/atlas_setup.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,123 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Atlas specific setup, including init of the feature struct. - * - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE) -extern void console_setup(char *, int *); -char serial_console[20]; -#endif - -#ifdef CONFIG_REMOTE_DEBUG -extern void rs_kgdb_hook(int); -extern void saa9730_kgdb_hook(void); -extern void breakpoint(void); -int remote_debug = 0; -#endif - -extern struct rtc_ops atlas_rtc_ops; - -extern void mips_reboot_setup(void); - -void __init atlas_setup(void) -{ -#ifdef CONFIG_REMOTE_DEBUG - int rs_putDebugChar(char); - char rs_getDebugChar(void); - int saa9730_putDebugChar(char); - char saa9730_getDebugChar(void); - extern int (*putDebugChar)(char); - extern char (*getDebugChar)(void); -#endif - char *argptr; - - current_cpu_data.asid_cache = ASID_FIRST_VERSION; - TLBMISS_HANDLER_SETUP(); - - ioport_resource.end = 0x7fffffff; - -#ifdef CONFIG_SERIAL_CONSOLE - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "console=ttyS0")) == NULL) { - int i = 0; - char *s = prom_getenv("modetty0"); - while(s[i] >= '0' && s[i] <= '9') - i++; - strcpy(serial_console, "ttyS0,"); - strncpy(serial_console + 6, s, i); - prom_printf("Config serial console: %s\n", serial_console); - console_setup(serial_console, NULL); - } -#endif - -#ifdef CONFIG_REMOTE_DEBUG - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { - int line; - argptr += strlen("kgdb=ttyS"); - if (*argptr != '0' && *argptr != '1') - printk("KGDB: Uknown serial line /dev/ttyS%c, " - "falling back to /dev/ttyS1\n", *argptr); - line = *argptr == '0' ? 0 : 1; - printk("KGDB: Using serial line /dev/ttyS%d for session\n", - line ? 1 : 0); - - if(line == 0) { - rs_kgdb_hook(line); - putDebugChar = rs_putDebugChar; - getDebugChar = rs_getDebugChar; - } else { - saa9730_kgdb_hook(); - putDebugChar = saa9730_putDebugChar; - getDebugChar = saa9730_getDebugChar; - } - - prom_printf("KGDB: Using serial line /dev/ttyS%d for session, " - "please connect your debugger\n", line ? 1 : 0); - - remote_debug = 1; - /* Breakpoints and stuff are in atlas_irq_setup() */ - } -#endif - argptr = prom_getcmdline(); - - if ((argptr = strstr(argptr, "nofpu")) != NULL) - mips_cpu.options &= ~MIPS_CPU_FPU; - - rtc_ops = &atlas_rtc_ops; -} --- linux-2.5.73/arch/mips64/mips-boards/atlas/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,26 +0,0 @@ -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. -# -# ######################################################################## -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# -# ####################################################################### -# -# Makefile for the MIPS Atlas specific kernel interface routines -# under Linux. -# - -obj-y := atlas_int.o atlas_rtc.o atlas_setup.o --- linux-2.5.73/arch/mips64/mips-boards/generic/cmdline.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,71 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Kernel command line creation using the prom monitor (YAMON) argc/argv. - * - */ -#include -#include -#include - -#include - -/*#define DEBUG_CMDLINE*/ - -extern int prom_argc; -extern int *_prom_argv; - -/* - * A 32-bit PROM pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension. - */ -#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)])) - -char arcs_cmdline[CL_SIZE]; - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - - -void __init prom_init_cmdline(void) -{ - char *cp; - int actr; - - actr = 1; /* Always ignore argv[0] */ - - cp = &(arcs_cmdline[0]); - while(actr < prom_argc) { - strcpy(cp, prom_argv(actr)); - cp += strlen(prom_argv(actr)); - *cp++ = ' '; - actr++; - } - if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ - --cp; - *cp = '\0'; - -#ifdef DEBUG_CMDLINE - prom_printf("prom_init_cmdline: %s\n", &(arcs_cmdline[0])); -#endif -} --- linux-2.5.73/arch/mips64/mips-boards/generic/display.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,47 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Display routines for display messages in MIPS boards ascii display. - * - */ - -#include - - -void mips_display_message(const char *str) -{ - volatile unsigned int *display = (void *)ASCII_DISPLAY_POS_BASE; - int i; - - for (i = 0; i <= 14; i=i+2) { - if (*str) - display[i] = *str++; - else - display[i] = ' '; - } -} - -void mips_display_word(unsigned int num) -{ - volatile unsigned int *display = (void *)ASCII_DISPLAY_WORD_BASE; - - *display = num; -} --- linux-2.5.73/arch/mips64/mips-boards/generic/gdb_hook.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,202 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * This is the interface to the remote debugger stub. - * - */ - -#include -#include - -#include -#include - -static struct serial_state rs_table[RS_TABLE_SIZE] = { - SERIAL_PORT_DFNS /* Defined in serial.h */ -}; - -static struct async_struct kdb_port_info = {0}; - - -static __inline__ unsigned int serial_in(struct async_struct *info, int offset) -{ - return inb(info->port + offset); -} - -static __inline__ void serial_out(struct async_struct *info, int offset, - int value) -{ - outb(value, info->port+offset); -} - -void rs_kgdb_hook(int tty_no) { - int t; - struct serial_state *ser = &rs_table[tty_no]; - - kdb_port_info.state = ser; - kdb_port_info.magic = SERIAL_MAGIC; - kdb_port_info.port = ser->port; - kdb_port_info.flags = ser->flags; - - /* - * Clear all interrupts - */ - serial_in(&kdb_port_info, UART_LSR); - serial_in(&kdb_port_info, UART_RX); - serial_in(&kdb_port_info, UART_IIR); - serial_in(&kdb_port_info, UART_MSR); - - /* - * Now, initialize the UART - */ - serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */ - if (kdb_port_info.flags & ASYNC_FOURPORT) { - kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS; - t = UART_MCR_DTR | UART_MCR_OUT1; - } else { - kdb_port_info.MCR - = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2; - t = UART_MCR_DTR | UART_MCR_RTS; - } - - kdb_port_info.MCR = t; /* no interrupts, please */ - serial_out(&kdb_port_info, UART_MCR, kdb_port_info.MCR); - - /* - * and set the speed of the serial port - * (currently hardwired to 9600 8N1 - */ - - /* baud rate is fixed to 9600 (is this sufficient?)*/ - t = kdb_port_info.state->baud_base / 9600; - /* set DLAB */ - serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB); - serial_out(&kdb_port_info, UART_DLL, t & 0xff);/* LS of divisor */ - serial_out(&kdb_port_info, UART_DLM, t >> 8); /* MS of divisor */ - /* reset DLAB */ - serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); -} - -int rs_putDebugChar(char c) -{ - - if (!kdb_port_info.state) { /* need to init device first */ - return 0; - } - - while ((serial_in(&kdb_port_info, UART_LSR) & UART_LSR_THRE) == 0) - ; - - serial_out(&kdb_port_info, UART_TX, c); - - return 1; -} - -char rs_getDebugChar(void) -{ - if (!kdb_port_info.state) { /* need to init device first */ - return 0; - } - - while (!(serial_in(&kdb_port_info, UART_LSR) & 1)) - ; - - return(serial_in(&kdb_port_info, UART_RX)); -} - - -#ifdef CONFIG_MIPS_ATLAS - -#include -#include - -#define INB(a) inb((unsigned long)a) -#define OUTB(x,a) outb(x,(unsigned long)a) - -/* - * This is the interface to the remote debugger stub - * if the Philips part is used for the debug port, - * called from the platform setup code. - * - * PCI init will not have been done yet, we make a - * universal assumption about the way the bootloader (YAMON) - * have located and set up the chip. - */ -static t_uart_saa9730_regmap *kgdb_uart = (void *)(ATLAS_SAA9730_REG + SAA9730_UART_REGS_ADDR); - -static int saa9730_kgdb_active = 0; - -void saa9730_kgdb_hook(void) -{ - volatile unsigned char t; - - /* - * Clear all interrupts - */ - t = INB(&kgdb_uart->Lsr); - t += INB(&kgdb_uart->Msr); - t += INB(&kgdb_uart->Thr_Rbr); - t += INB(&kgdb_uart->Iir_Fcr); - - /* - * Now, initialize the UART - */ - /* 8 data bits, one stop bit, no parity */ - OUTB(SAA9730_LCR_DATA8, &kgdb_uart->Lcr); - - /* baud rate is fixed to 9600 (is this sufficient?)*/ - OUTB(0, &kgdb_uart->BaudDivMsb); /* HACK - Assumes standard crystal */ - OUTB(23, &kgdb_uart->BaudDivLsb); /* HACK - known for MIPS Atlas */ - - /* Set RTS/DTR active */ - OUTB(SAA9730_MCR_DTR | SAA9730_MCR_RTS, &kgdb_uart->Mcr); - saa9730_kgdb_active = 1; -} - -int saa9730_putDebugChar(char c) -{ - - if (!saa9730_kgdb_active) { /* need to init device first */ - return 0; - } - - while (!(INB(&kgdb_uart->Lsr) & SAA9730_LSR_THRE)) - ; - OUTB(c, &kgdb_uart->Thr_Rbr); - - return 1; -} - -char saa9730_getDebugChar(void) -{ - char c; - - if (!saa9730_kgdb_active) { /* need to init device first */ - return 0; - } - while (!(INB(&kgdb_uart->Lsr) & SAA9730_LSR_DR)) - ; - - c = INB(&kgdb_uart->Thr_Rbr); - return(c); -} - -#endif --- linux-2.5.73/arch/mips64/mips-boards/generic/init.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,152 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * PROM library initialisation code. - */ -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -/* Environment variable */ -typedef struct -{ - char *name; - char *val; -}t_env_var; - -int prom_argc; -int *_prom_argv, *_prom_envp; - -/* - * A 32-bit PROM pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension. - */ -#define prom_envp(index) ((char *)(((int *)(int)_prom_envp)[(index)])) - -int init_debug = 0; - -char *prom_getenv(char *envname) -{ - /* - * Return a pointer to the given environment variable. - * We're using 64-bit pointers, but all pointers in the PROM - * structures are only 32-bit, so we need some workarounds. - */ - int i, index=0; - - i = strlen(envname); - - while(prom_envp(index)) { - if(strncmp(envname, prom_envp(index), i) == 0) { - return(prom_envp(index+1)); - } - index += 2; - } - - return(NULL); -} - -static inline unsigned char str2hexnum(unsigned char c) -{ - if(c >= '0' && c <= '9') - return c - '0'; - if(c >= 'a' && c <= 'f') - return c - 'a' + 10; - return 0; /* foo */ -} - -static inline void str2eaddr(unsigned char *ea, unsigned char *str) -{ - int i; - - for(i = 0; i < 6; i++) { - unsigned char num; - - if((*str == '.') || (*str == ':')) - str++; - num = str2hexnum(*str++) << 4; - num |= (str2hexnum(*str++)); - ea[i] = num; - } -} - -int get_ethernet_addr(char *ethernet_addr) -{ - char *ethaddr_str; - - ethaddr_str = prom_getenv("ethaddr"); - if (!ethaddr_str) { - printk("ethaddr not set in boot prom\n"); - return -1; - } - str2eaddr(ethernet_addr, ethaddr_str); - - if (init_debug > 1) - { - int i; - printk("get_ethernet_addr: "); - for (i=0; i<5; i++) - printk("%02x:", (unsigned char)*(ethernet_addr+i)); - printk("%02x\n", *(ethernet_addr+i)); - } - - return 0; -} - -int __init prom_init(int argc, char **argv, char **envp) -{ - prom_argc = argc; - _prom_argv = (int *)argv; - _prom_envp = (int *)envp; - - mips_display_message("LINUX"); - - /* - * Setup the North bridge to do Master byte-lane swapping when - * running in bigendian. - */ -#if defined(__MIPSEL__) - GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | - GT_PCI0_CMD_SBYTESWAP_BIT); -#else - GT_WRITE(GT_PCI0_CMD_OFS, 0); -#endif - -#if defined(CONFIG_MIPS_MALTA) - mips_io_port_base = MALTA_PORT_BASE; -#else - mips_io_port_base = KSEG1; -#endif - - setup_prom_printf(0); - prom_printf("\nLINUX started...\n"); - prom_init_cmdline(); - prom_meminit(); - - return 0; -} --- linux-2.5.73/arch/mips64/mips-boards/generic/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,29 +0,0 @@ -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. -# -# ######################################################################## -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# -# ####################################################################### -# -# Makefile for the MIPS boards generic routines under Linux. -# - -obj-y := mipsIRQ.o pci.o reset.o display.o init.o \ - memory.o printf.o cmdline.o time.o -obj-$(CONFIG_REMOTE_DEBUG) += gdb_hook.o - -EXTRA_AFLAGS := $(CFLAGS) --- linux-2.5.73/arch/mips64/mips-boards/generic/memory.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,263 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * PROM library functions for acquiring/using memory descriptors given to - * us from the YAMON. - * - */ -#include -#include -#include -#include - -#include -#include - -#include - -/*#define DEBUG*/ - -enum yamon_memtypes { - yamon_dontuse, - yamon_prom, - yamon_free, -}; -struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS]; - -#define MEMTYPE_DONTUSE 0 -#define MEMTYPE_PROM 1 -#define MEMTYPE_FREE 2 - -#ifdef DEBUG -static char *mtypes[3] = { - "Dont use memory", - "YAMON PROM memory", - "Free memmory", -}; -#endif - -/* References to section boundaries */ -extern char _end; - -#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK) - -struct prom_pmemblock * __init prom_getmdesc(void) -{ - char *memsize_str; - unsigned int memsize; - - memsize_str = prom_getenv("memsize"); - if (!memsize_str) { - prom_printf("memsize not set in boot prom, set to default (32Mb)\n"); - memsize = 0x02000000; - } else { -#ifdef DEBUG - prom_printf("prom_memsize = %s\n", memsize_str); -#endif - memsize = simple_strtol(memsize_str, NULL, 0); - } - - memset(mdesc, 0, sizeof(mdesc)); - - mdesc[0].type = yamon_dontuse; - mdesc[0].base = 0x00000000; - mdesc[0].size = 0x00001000; - - mdesc[1].type = yamon_prom; - mdesc[1].base = 0x00001000; - mdesc[1].size = 0x000ef000; - -#if (CONFIG_MIPS_MALTA) - /* - * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the - * south bridge and PCI access always forwarded to the ISA Bus and - * BIOSCS# is always generated. - * This mean that this area can't be used as DMA memory for PCI - * devices. - */ - mdesc[2].type = yamon_dontuse; - mdesc[2].base = 0x000f0000; - mdesc[2].size = 0x00010000; -#else - mdesc[2].type = yamon_prom; - mdesc[2].base = 0x000f0000; - mdesc[2].size = 0x00010000; -#endif - - mdesc[3].type = yamon_dontuse; - mdesc[3].base = 0x00100000; - mdesc[3].size = CPHYSADDR(PFN_ALIGN(&_end)) - mdesc[3].base; - - mdesc[4].type = yamon_free; - mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end)); - mdesc[4].size = memsize - mdesc[4].base; - - return &mdesc[0]; -} - -int __init page_is_ram(unsigned long pagenr) -{ - if ((pagenr << PAGE_SHIFT) < mdesc[4].base + mdesc[4].size) - return 1; - - return 0; -} - -static struct prom_pmemblock pblocks[PROM_MAX_PMEMBLOCKS]; - -static int __init prom_memtype_classify (unsigned int type) -{ - switch (type) { - case yamon_free: - return MEMTYPE_FREE; - case yamon_prom: - return MEMTYPE_PROM; - default: - return MEMTYPE_DONTUSE; - } -} - -static inline unsigned long find_max_low_pfn(void) -{ - struct prom_pmemblock *p, *highest; - unsigned long pfn; - - p = pblocks; - highest = 0; - while (p->size != 0) { - if (!highest || p->base > highest->base) - highest = p; - p++; - } - - pfn = (highest->base + highest->size) >> PAGE_SHIFT; -#ifdef DEBUG - prom_printf("find_max_low_pfn: 0x%lx pfns.\n", pfn); -#endif - return pfn; -} - -static inline struct prom_pmemblock *find_largest_memblock(void) -{ - struct prom_pmemblock *p, *largest; - - p = pblocks; - largest = 0; - while (p->size != 0) { - if (!largest || p->size > largest->size) - largest = p; - p++; - } - - return largest; -} - -void __init prom_meminit(void) -{ - struct prom_pmemblock *largest, *p; - unsigned long bootmap_size; - int totram; - int i = 0; - -#ifdef DEBUG - prom_printf("YAMON MEMORY DESCRIPTOR dump:\n"); - p = prom_getmdesc(); - while (p->size) { - prom_printf("[%d,%p]: base<%08lx> size<%08lx> type<%s>\n", - i, p, p->base, p->size, mtypes[p->type]); - p++; - i++; - } -#endif - totram = 0; - i = 0; - p = prom_getmdesc(); - - while (p->size) { - pblocks[i].type = prom_memtype_classify (p->type); - pblocks[i].base = p->base; - pblocks[i].size = p->size; - switch (pblocks[i].type) { - case MEMTYPE_FREE: - totram += pblocks[i].size; -#ifdef DEBUG - prom_printf("free_chunk[%d]: base=%08lx size=%d\n", - i, pblocks[i].base, pblocks[i].size); -#endif - i++; - break; - case MEMTYPE_PROM: -#ifdef DEBUG - prom_printf("prom_chunk[%d]: base=%08lx size=%d\n", - i, pblocks[i].base, pblocks[i].size); -#endif - i++; - break; - default: - break; - } - p++; - } - pblocks[i].base = 0xdeadbeef; - pblocks[i].size = 0; /* indicates last elem. of array */ - - max_low_pfn = find_max_low_pfn(); - largest = find_largest_memblock(); - bootmap_size = init_bootmem(largest->base >> PAGE_SHIFT, max_low_pfn); - - for (i = 0; pblocks[i].size; i++) - if (pblocks[i].type == MEMTYPE_FREE) - free_bootmem(pblocks[i].base, pblocks[i].size); - - /* This test is simpleminded. It will fail if the bootmem bitmap - falls into multiple adjacent PROM memory areas. */ - if (bootmap_size > largest->size) { - prom_printf("CRITIAL: overwriting PROM data.\n"); - BUG(); - } - - /* Reserve the memory bootmap itself */ - reserve_bootmem(largest->base, bootmap_size); - printk("PROMLIB: Total free ram %d bytes (%dK,%dMB)\n", - totram, (totram/1024), (totram/1024/1024)); -} - -void prom_free_prom_memory (void) -{ - struct prom_pmemblock *p; - unsigned long freed = 0; - unsigned long addr; - - for (p = pblocks; p->size != 0; p++) { - if (p->type != MEMTYPE_PROM) - continue; - - addr = p->base; - while (addr < p->base + p->size) { - ClearPageReserved(virt_to_page(__va(addr))); - set_page_count(virt_to_page(__va(addr)), 1); - free_page(__va(addr)); - addr += PAGE_SIZE; - freed += PAGE_SIZE; - } - } - printk("Freeing prom memory: %ldkb freed\n", freed >> 10); -} --- linux-2.5.73/arch/mips64/mips-boards/generic/mipsIRQ.S 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,122 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Interrupt exception dispatch code. - * - */ -#include - -#include -#include -#include -#include - -/* A lot of complication here is taken away because: - * - * 1) We handle one interrupt and return, sitting in a loop and moving across - * all the pending IRQ bits in the cause register is _NOT_ the answer, the - * common case is one pending IRQ so optimize in that direction. - * - * 2) We need not check against bits in the status register IRQ mask, that - * would make this routine slow as hell. - * - * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in - * between like BSD spl() brain-damage. - * - * Furthermore, the IRQs on the MIPS board look basically (barring software - * IRQs which we don't use at all and all external interrupt sources are - * combined together on hardware interrupt 0 (MIPS IRQ 2)) like: - * - * MIPS IRQ Source - * -------- ------ - * 0 Software (ignored) - * 1 Software (ignored) - * 2 Combined hardware interrupt (hw0) - * 3 Hardware (ignored) - * 4 Hardware (ignored) - * 5 Hardware (ignored) - * 6 Hardware (ignored) - * 7 R4k timer (what we use) - * - * We handle the IRQ according to _our_ priority which is: - * - * Highest ---- R4k Timer - * Lowest ---- Combined hardware interrupt - * - * then we just return, if multiple IRQs are pending then we will just take - * another exception, big deal. - */ - - .text - .set noreorder - .set noat - .align 5 - NESTED(mipsIRQ, PT_SIZE, sp) - SAVE_ALL - CLI - .set at - - mfc0 s0, CP0_CAUSE # get irq mask - - /* First we check for r4k counter/timer IRQ. */ - andi a0, s0, CAUSEF_IP7 - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt - - /* Wheee, a timer interrupt. */ - move a0, sp - jal mips_timer_interrupt - nop - - j ret_from_irq - nop - -1: - beq a0, zero, 1f - nop - - /* Wheee, combined hardware level zero interrupt. */ -#if defined(CONFIG_MIPS_ATLAS) - jal atlas_hw0_irqdispatch -#elif defined(CONFIG_MIPS_MALTA) - jal malta_hw0_irqdispatch -#else -#error "MIPS board not supported\n" -#endif - move a0, sp # delay slot - - j ret_from_irq - nop # delay slot - -1: - /* - * Here by mistake? This is possible, what can happen is that by the - * time we take the exception the IRQ pin goes low, so just leave if - * this is the case. - */ - move a1,s0 - PRINT("Got interrupt: c0_cause = %08x\n") - mfc0 a1, CP0_EPC - PRINT("c0_epc = %08x\n") - - j ret_from_irq - nop - END(mipsIRQ) --- linux-2.5.73/arch/mips64/mips-boards/generic/pci.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,326 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * MIPS boards specific PCI support. - * - */ -#include - -#ifdef CONFIG_PCI - -#include -#include -#include -#include - -#include -#include -#ifdef CONFIG_MIPS_MALTA -#include -#endif - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -static int -mips_pcibios_config_access(unsigned char access_type, struct pci_dev *dev, - unsigned char where, u32 *data) -{ - unsigned char bus = dev->bus->number; - unsigned char dev_fn = dev->devfn; - u32 intr; - - if ((bus == 0) && (dev_fn >= PCI_DEVFN(31,0))) - return -1; /* Because of a bug in the galileo (for slot 31). */ - - /* Clear cause register bits */ - GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | - GT_INTRCAUSE_TARABORT0_BIT)); - - /* Setup address */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, - (bus << GT_PCI0_CFGADDR_BUSNUM_SHF) | - (dev_fn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | - ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | - GT_PCI0_CFGADDR_CONFIGEN_BIT); - - if (access_type == PCI_ACCESS_WRITE) { - if (bus == 0 && dev_fn == 0) { - /* - * Galileo is acting differently than other devices. - */ - GT_WRITE(GT_PCI0_CFGDATA_OFS, *data); - } else { - GT_PCI_WRITE(GT_PCI0_CFGDATA_OFS, *data); - } - } else { - if (bus == 0 && dev_fn == 0) { - /* - * Galileo is acting differently than other devices. - */ - GT_READ(GT_PCI0_CFGDATA_OFS, *data); - } else { - GT_PCI_READ(GT_PCI0_CFGDATA_OFS, *data); - } - } - - /* Check for master or target abort */ - GT_READ(GT_INTRCAUSE_OFS, intr); - - if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) - { - /* Error occurred */ - - /* Clear bits */ - GT_WRITE( GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | - GT_INTRCAUSE_TARABORT0_BIT) ); - - return -1; - } - - return 0; -} - - -/* - * We can't address 8 and 16 bit words directly. Instead we have to - * read/write a 32bit word and mask/modify the data we actually want. - */ -static int -mips_pcibios_read_config_byte (struct pci_dev *dev, int where, u8 *val) -{ - u32 data = 0; - - if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data)) - return -1; - - *val = (data >> ((where & 3) << 3)) & 0xff; - - return PCIBIOS_SUCCESSFUL; -} - - -static int -mips_pcibios_read_config_word (struct pci_dev *dev, int where, u16 *val) -{ - u32 data = 0; - - if (where & 1) - return PCIBIOS_BAD_REGISTER_NUMBER; - - if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data)) - return -1; - - *val = (data >> ((where & 3) << 3)) & 0xffff; - - return PCIBIOS_SUCCESSFUL; -} - -static int -mips_pcibios_read_config_dword (struct pci_dev *dev, int where, u32 *val) -{ - u32 data = 0; - - if (where & 3) - return PCIBIOS_BAD_REGISTER_NUMBER; - - if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data)) - return -1; - - *val = data; - - return PCIBIOS_SUCCESSFUL; -} - - -static int -mips_pcibios_write_config_byte (struct pci_dev *dev, int where, u8 val) -{ - u32 data = 0; - - if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data)) - return -1; - - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - - if (mips_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &data)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -static int -mips_pcibios_write_config_word (struct pci_dev *dev, int where, u16 val) -{ - u32 data = 0; - - if (where & 1) - return PCIBIOS_BAD_REGISTER_NUMBER; - - if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data)) - return -1; - - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - - if (mips_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &data)) - return -1; - - - return PCIBIOS_SUCCESSFUL; -} - -static int -mips_pcibios_write_config_dword(struct pci_dev *dev, int where, u32 val) -{ - if (where & 3) - return PCIBIOS_BAD_REGISTER_NUMBER; - - if (mips_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &val)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops mips_pci_ops = { - mips_pcibios_read_config_byte, - mips_pcibios_read_config_word, - mips_pcibios_read_config_dword, - mips_pcibios_write_config_byte, - mips_pcibios_write_config_word, - mips_pcibios_write_config_dword -}; - -void __init pcibios_init(void) -{ -#ifdef CONFIG_MIPS_MALTA - struct pci_dev *pdev = NULL; - unsigned char reg_val; -#endif - - printk("PCI: Probing PCI hardware on host bus 0.\n"); - pci_scan_bus(0, &mips_pci_ops, NULL); - - /* - * Due to a bug in the Galileo system controller, we need to setup - * the PCI BAR for the Galileo internal registers. - * This should be done in the bios/bootprom and will be fixed in - * a later revision of YAMON (the MIPS boards boot prom). - */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, - (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ - (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 device */ - (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0 */ - ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4 */ - GT_PCI0_CFGADDR_CONFIGEN_BIT ); - - /* Perform the write */ - GT_WRITE( GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); - -#ifdef CONFIG_MIPS_MALTA - while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) { - if ((pdev->vendor == PCI_VENDOR_ID_INTEL) - && (pdev->device == PCI_DEVICE_ID_INTEL_82371AB) - && (PCI_SLOT(pdev->devfn) == 0x0a)) { - /* - * IDE Decode enable. - */ - pci_read_config_byte(pdev, 0x41, ®_val); - pci_write_config_byte(pdev, 0x41, reg_val | 0x80); - pci_read_config_byte(pdev, 0x43, ®_val); - pci_write_config_byte(pdev, 0x43, reg_val | 0x80); - } - - if ((pdev->vendor == PCI_VENDOR_ID_INTEL) - && (pdev->device == PCI_DEVICE_ID_INTEL_82371AB_0) - && (PCI_SLOT(pdev->devfn) == 0x0a)) { - /* - * Set top of main memory accessible by ISA or DMA - * devices to 16 Mb. - */ - pci_read_config_byte(pdev, 0x69, ®_val); - pci_write_config_byte(pdev, 0x69, reg_val | 0xf0); - } - } - - /* - * Activate Floppy Controller in the SMSC FDC37M817 Super I/O - * Controller. - * This should be done in the bios/bootprom and will be fixed in - * a later revision of YAMON (the MIPS boards boot prom). - */ - /* Entering config state. */ - SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG); - - /* Activate floppy controller. */ - SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG); - SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG); - SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG); - SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG); - - /* Exit config state. */ - SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG); -#endif -} - -int __init -pcibios_enable_device(struct pci_dev *dev) -{ - /* Not needed, since we enable all devices at startup. */ - return 0; -} - -void __init -pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) -{ -} - -char * __init -pcibios_setup(char *str) -{ - /* Nothing to do for now. */ - - return str; -} - -struct pci_fixup pcibios_fixups[] = { - { 0 } -}; - -#warning pcibios_update_resource() is now a generic implementation - please check - -unsigned __init int pcibios_assign_all_busses(void) -{ - return 1; -} - -/* - * Called after each bus is probed, but before its children - * are examined. - */ -void __init pcibios_fixup_bus(struct pci_bus *b) -{ - pci_read_bridge_bases(b); -} - -#endif /* CONFIG_PCI */ --- linux-2.5.73/arch/mips64/mips-boards/generic/printf.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,140 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Putting things on the screen/serial line using YAMONs facilities. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include - - -#ifdef CONFIG_MIPS_ATLAS -/* - * Atlas registers are memory mapped on 64-bit aligned boundaries and - * only word access are allowed. - * When reading the UART 8 bit registers only the LSB are valid. - */ -unsigned int atlas_serial_in(struct async_struct *info, int offset) -{ - return (*(volatile unsigned int *)(info->port + mips_io_port_base + offset*8) & 0xff); -} - -void atlas_serial_out(struct async_struct *info, int offset, int value) -{ - *(volatile unsigned int *)(info->port + mips_io_port_base + offset*8) = value; -} - -#define serial_in atlas_serial_in -#define serial_out atlas_serial_out - -#else - -static unsigned int serial_in(struct async_struct *info, int offset) -{ - return inb(info->port + offset); -} - -static void serial_out(struct async_struct *info, int offset, - int value) -{ - outb(value, info->port + offset); -} -#endif - -static struct serial_state rs_table[] = { - SERIAL_PORT_DFNS /* Defined in serial.h */ -}; - -/* - * Hooks to fake "prom" console I/O before devices - * are fully initialized. - */ -static struct async_struct prom_port_info = {0}; - -void __init setup_prom_printf(int tty_no) { - struct serial_state *ser = &rs_table[tty_no]; - - prom_port_info.state = ser; - prom_port_info.magic = SERIAL_MAGIC; - prom_port_info.port = ser->port; - prom_port_info.flags = ser->flags; - - /* No setup of UART - assume YAMON left in sane state */ -} - -int putPromChar(char c) -{ - if (!prom_port_info.state) { /* need to init device first */ - return 0; - } - - while ((serial_in(&prom_port_info, UART_LSR) & UART_LSR_THRE) == 0) - ; - - serial_out(&prom_port_info, UART_TX, c); - - return 1; -} - -char getPromChar(void) -{ - if (!prom_port_info.state) { /* need to init device first */ - return 0; - } - - while (!(serial_in(&prom_port_info, UART_LSR) & 1)) - ; - - return(serial_in(&prom_port_info, UART_RX)); -} - -static char buf[1024]; - -void __init prom_printf(char *fmt, ...) -{ - va_list args; - int l; - char *p, *buf_end; - long flags; - - int putPromChar(char); - - /* Low level, brute force, not SMP safe... */ - save_and_cli(flags); - va_start(args, fmt); - l = vsprintf(buf, fmt, args); /* hopefully i < sizeof(buf) */ - va_end(args); - - buf_end = buf + l; - - for (p = buf; p < buf_end; p++) { - /* Crude cr/nl handling is better than none */ - if(*p == '\n')putPromChar('\r'); - putPromChar(*p); - } - restore_flags(flags); -} --- linux-2.5.73/arch/mips64/mips-boards/generic/reset.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,61 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Reset the MIPS boards. - * - */ -#include - -#include -#if defined(CONFIG_MIPS_ATLAS) -#include -#endif - -void machine_restart(char *command) __attribute__((noreturn)); -void machine_halt(void) __attribute__((noreturn)); -#if defined(CONFIG_MIPS_ATLAS) -void machine_power_off(void) __attribute__((noreturn)); -#endif - -void machine_restart(char *command) -{ - volatile unsigned int *softres_reg = (void *)SOFTRES_REG; - - *softres_reg = GORESET; -} - -void machine_halt(void) -{ - volatile unsigned int *softres_reg = (void *)SOFTRES_REG; - - *softres_reg = GORESET; -} - -void machine_power_off(void) -{ -#if defined(CONFIG_MIPS_ATLAS) - volatile unsigned int *psustby_reg = (void *)ATLAS_PSUSTBY_REG; - - *psustby_reg = ATLAS_GOSTBY; -#else - machine_halt(); -#endif -} --- linux-2.5.73/arch/mips64/mips-boards/generic/time.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,409 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Setting up the clock on the MIPS boards. - * - */ - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include -#include - -extern volatile unsigned long wall_jiffies; -static long last_rtc_update = 0; -unsigned long missed_heart_beats = 0; - -static unsigned long r4k_offset; /* Amount to increment compare reg each time */ -static unsigned long r4k_cur; /* What counter should be at next timer irq */ - -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) - -#if defined(CONFIG_MIPS_ATLAS) -static char display_string[] = " LINUX ON ATLAS "; -#endif -#if defined(CONFIG_MIPS_MALTA) -static char display_string[] = " LINUX ON MALTA "; -#endif -static unsigned int display_count = 0; -#define MAX_DISPLAY_COUNT (sizeof(display_string) - 8) - -static unsigned int timer_tick_count=0; - - -static inline void ack_r4ktimer(unsigned long newval) -{ - write_32bit_cp0_register(CP0_COMPARE, newval); -} - - -/* - * In order to set the CMOS clock precisely, set_rtc_mmss has to be - * called 500 ms after the second nowtime has started, because when - * nowtime is written into the registers of the CMOS clock, it will - * jump to the next second precisely 500 ms later. Check the Motorola - * MC146818A or Dallas DS12887 data sheet for details. - * - * BUG: This routine does not handle hour overflow properly; it just - * sets the minutes. Usually you won't notice until after reboot! - */ -static int set_rtc_mmss(unsigned long nowtime) -{ - int retval = 0; - int real_seconds, real_minutes, cmos_minutes; - unsigned char save_control, save_freq_select; - - save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */ - CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL); - - save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */ - CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); - - cmos_minutes = CMOS_READ(RTC_MINUTES); - - /* - * since we're only adjusting minutes and seconds, - * don't interfere with hour overflow. This avoids - * messing with unknown time zones but requires your - * RTC not to be off by more than 15 minutes - */ - real_seconds = nowtime % 60; - real_minutes = nowtime / 60; - if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) - real_minutes += 30; /* correct for half hour time zone */ - real_minutes %= 60; - - if (abs(real_minutes - cmos_minutes) < 30) { - CMOS_WRITE(real_seconds,RTC_SECONDS); - CMOS_WRITE(real_minutes,RTC_MINUTES); - } else { - printk(KERN_WARNING - "set_rtc_mmss: can't update from %d to %d\n", - cmos_minutes, real_minutes); - retval = -1; - } - - /* The following flags have to be released exactly in this order, - * otherwise the DS12887 (popular MC146818A clone with integrated - * battery and quartz) will not reset the oscillator and will not - * update precisely 500 ms later. You won't find this mentioned in - * the Dallas Semiconductor data sheets, but who believes data - * sheets anyway ... -- Markus Kuhn - */ - CMOS_WRITE(save_control, RTC_CONTROL); - CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); - - return retval; -} - -/* - * There are a lot of conceptually broken versions of the MIPS timer interrupt - * handler floating around. This one is rather different, but the algorithm - * is provably more robust. - */ -void mips_timer_interrupt(struct pt_regs *regs) -{ - unsigned long flags; - unsigned long seq; - int irq = 7; - - if (r4k_offset == 0) - goto null; - - do { - kstat_cpu(0).irqs[irq]++; - do_timer(regs); - - /* Historical comment/code: - * RTC time of day s updated approx. every 11 - * minutes. Because of how the numbers work out - * we need to make absolutely sure we do this update - * within 500ms before the * next second starts, - * thus the following code. - */ - do { - seq = read_seqbegin_irqsave(&xtime_lock, flags); - - if ((time_status & STA_UNSYNC) == 0 - && xtime.tv_sec > last_rtc_update + 660 - && xtime.tv_usec >= 500000 - (tick >> 1) - && xtime.tv_usec <= 500000 + (tick >> 1)) - if (set_rtc_mmss(xtime.tv_sec) == 0) - last_rtc_update = xtime.tv_sec; - else - /* do it again in 60 s */ - last_rtc_update = xtime.tv_sec - 600; - } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); - - - if ((timer_tick_count++ % HZ) == 0) { - mips_display_message(&display_string[display_count++]); - if (display_count == MAX_DISPLAY_COUNT) - display_count = 0; - } - - r4k_cur += r4k_offset; - ack_r4ktimer(r4k_cur); - - } while (((unsigned int)read_32bit_cp0_register(CP0_COUNT) - - (unsigned int)r4k_cur) < 0x7fffffff); - - return; - -null: - ack_r4ktimer(0); -} - -/* - * Figure out the r4k offset, the amount to increment the compare - * register for each time tick. - * Use the RTC to calculate offset. - */ -static unsigned long __init cal_r4koff(void) -{ - unsigned long count; - unsigned int flags; - - local_irq_save(flags); - - /* Start counter exactly on falling edge of update flag */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); - while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - - /* Start r4k counter. */ - write_32bit_cp0_register(CP0_COUNT, 0); - - /* Read counter exactly on falling edge of update flag */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); - while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - - count = read_32bit_cp0_register(CP0_COUNT); - - /* restore interrupts */ - local_irq_restore(flags); - - return (count / HZ); -} - -static unsigned long __init get_mips_time(void) -{ - unsigned int year, mon, day, hour, min, sec; - unsigned char save_control; - - save_control = CMOS_READ(RTC_CONTROL); - - /* Freeze it. */ - CMOS_WRITE(save_control | RTC_SET, RTC_CONTROL); - - /* Read regs. */ - sec = CMOS_READ(RTC_SECONDS); - min = CMOS_READ(RTC_MINUTES); - hour = CMOS_READ(RTC_HOURS); - - if (!(save_control & RTC_24H)) - { - if ((hour & 0xf) == 0xc) - hour &= 0x80; - if (hour & 0x80) - hour = (hour & 0xf) + 12; - } - day = CMOS_READ(RTC_DAY_OF_MONTH); - mon = CMOS_READ(RTC_MONTH); - year = CMOS_READ(RTC_YEAR); - - /* Unfreeze clock. */ - CMOS_WRITE(save_control, RTC_CONTROL); - - if ((year += 1900) < 1970) - year += 100; - - return mktime(year, mon, day, hour, min, sec); -} - -void __init time_init(void) -{ - unsigned int est_freq, flags; - - /* Set Data mode - binary. */ - CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); - - printk("calculating r4koff... "); - r4k_offset = cal_r4koff(); - printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); - - est_freq = 2*r4k_offset*HZ; - est_freq += 5000; /* round */ - est_freq -= est_freq%10000; - printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, - (est_freq%1000000)*100/1000000); - r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset); - - write_32bit_cp0_register(CP0_COMPARE, r4k_cur); - set_cp0_status(ST0_IM, ALLINTS); - - /* Read time from the RTC chipset. */ - write_seqlock_irqsave (&xtime_lock, flags); - xtime.tv_sec = get_mips_time(); - xtime.tv_usec = 0; - write_sequnlock_irqrestore(&xtime_lock, flags); -} - -/* This is for machines which generate the exact clock. */ -#define USECS_PER_JIFFY (1000000/HZ) -#define USECS_PER_JIFFY_FRAC (0x100000000*1000000/HZ&0xffffffff) - -/* Cycle counter value at the previous timer interrupt.. */ - -static unsigned int timerhi = 0, timerlo = 0; - -/* - * FIXME: Does playing with the RP bit in c0_status interfere with this code? - */ -static unsigned long do_fast_gettimeoffset(void) -{ - u32 count; - unsigned long res, tmp; - - /* Last jiffy when do_fast_gettimeoffset() was called. */ - static unsigned long last_jiffies=0; - unsigned long quotient; - - /* - * Cached "1/(clocks per usec)*2^32" value. - * It has to be recalculated once each jiffy. - */ - static unsigned long cached_quotient=0; - - tmp = jiffies; - - quotient = cached_quotient; - - if (tmp && last_jiffies != tmp) { - last_jiffies = tmp; - __asm__(".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "lwu\t%0,%2\n\t" - "dsll32\t$1,%1,0\n\t" - "or\t$1,$1,%0\n\t" - "ddivu\t$0,$1,%3\n\t" - "mflo\t$1\n\t" - "dsll32\t%0,%4,0\n\t" - "nop\n\t" - "ddivu\t$0,%0,$1\n\t" - "mflo\t%0\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=&r" (quotient) - :"r" (timerhi), - "m" (timerlo), - "r" (tmp), - "r" (USECS_PER_JIFFY) - :"$1"); - cached_quotient = quotient; - } - - /* Get last timer tick in absolute kernel time */ - count = read_32bit_cp0_register(CP0_COUNT); - - /* .. relative to previous jiffy (32 bits is enough) */ - count -= timerlo; - - __asm__("multu\t%1,%2\n\t" - "mfhi\t%0" - :"=r" (res) - :"r" (count), - "r" (quotient)); - - /* - * Due to possible jiffies inconsistencies, we need to check - * the result so that we'll get a timer that is monotonic. - */ - if (res >= USECS_PER_JIFFY) - res = USECS_PER_JIFFY-1; - - return res; -} - -void do_gettimeofday(struct timeval *tv) -{ - unsigned long flags; - unsigned long seq; - - do { - seq = read_seqbegin_irqsave(&xtime_lock, flags); - - *tv = xtime; - tv->tv_usec += do_fast_gettimeoffset(); - - /* - * xtime is atomically updated in timer_bh. - * jiffies - wall_jiffies - * is nonzero if the timer bottom half hasnt executed yet. - */ - if (jiffies - wall_jiffies) - tv->tv_usec += USECS_PER_JIFFY; - - } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); - - - if (tv->tv_usec >= 1000000) { - tv->tv_usec -= 1000000; - tv->tv_sec++; - } -} - -void do_settimeofday(struct timeval *tv) -{ - write_seqlock_irq (&xtime_lock); - - /* This is revolting. We need to set the xtime.tv_usec correctly. - * However, the value in this location is is value at the last tick. - * Discover what correction gettimeofday would have done, and then - * undo it! - */ - tv->tv_usec -= do_fast_gettimeoffset(); - - if (tv->tv_usec < 0) { - tv->tv_usec += 1000000; - tv->tv_sec--; - } - - xtime = *tv; - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; - - write_sequnlock_irq (&xtime_lock); -} --- linux-2.5.73/arch/mips64/mips-boards/malta/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,26 +0,0 @@ -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. -# -# ######################################################################## -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# -# ####################################################################### -# -# Makefile for the MIPS Malta specific kernel interface routines -# under Linux. -# - -obj-y := malta_int.o malta_rtc.o malta_setup.o --- linux-2.5.73/arch/mips64/mips-boards/malta/malta_int.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,391 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Routines for generic manipulation of the interrupts found on the MIPS - * Malta board. - * The interrupt controller is located in the South Bridge a PIIX4 device - * with two internal 82C95 interrupt controllers. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -extern asmlinkage void mipsIRQ(void); - -unsigned int local_bh_count[NR_CPUS]; -unsigned int local_irq_count[NR_CPUS]; -unsigned long spurious_count = 0; - -static struct irqaction *hw0_irq_action[MALTAINT_END] = { - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL -}; - -static struct irqaction r4ktimer_action = { - NULL, 0, 0, "R4000 timer/counter", NULL, NULL, -}; - -static struct irqaction *irq_action[8] = { - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, &r4ktimer_action -}; - -#if 0 -#define DEBUG_INT(x...) printk(x) -#else -#define DEBUG_INT(x...) -#endif - -/* - * This contains the interrupt mask for both 82C59 interrupt controllers. - */ -static unsigned int cached_int_mask = 0xffff; - - -void disable_irq(unsigned int irq_nr) -{ - unsigned long flags; - - if(irq_nr >= MALTAINT_END) { - printk("whee, invalid irq_nr %d\n", irq_nr); - panic("IRQ, you lose..."); - } - - save_and_cli(flags); - cached_int_mask |= (1 << irq_nr); - if (irq_nr & 8) { - outb((cached_int_mask >> 8) & 0xff, PIIX4_ICTLR2_OCW1); - } else { - outb(cached_int_mask & 0xff, PIIX4_ICTLR1_OCW1); - } - restore_flags(flags); -} - - -void enable_irq(unsigned int irq_nr) -{ - unsigned long flags; - - if(irq_nr >= MALTAINT_END) { - printk("whee, invalid irq_nr %d\n", irq_nr); - panic("IRQ, you lose..."); - } - - save_and_cli(flags); - cached_int_mask &= ~(1 << irq_nr); - if (irq_nr & 8) { - outb((cached_int_mask >> 8) & 0xff, PIIX4_ICTLR2_OCW1); - - /* Enable irq 2 (cascade interrupt). */ - cached_int_mask &= ~(1 << 2); - outb(cached_int_mask & 0xff, PIIX4_ICTLR1_OCW1); - } else { - outb(cached_int_mask & 0xff, PIIX4_ICTLR1_OCW1); - } - restore_flags(flags); -} - - -int show_interrupts(struct seq_file *p, void *v) -{ - int i; - int num = 0; - struct irqaction *action; - unsigned long flags; - - for (i = 0; i < 8; i++, num++) { - local_irq_save(flags); - action = irq_action[i]; - if (!action) - goto skip_1; - seq_printf(p, "%2d: %8d %c %s", - num, kstat_cpu(0).irqs[num], - (action->flags & SA_INTERRUPT) ? '+' : ' ', - action->name); - for (action=action->next; action; action = action->next) { - seq_printf(p, ",%s %s", - (action->flags & SA_INTERRUPT) ? " +" : "", - action->name); - } - seq_puts(p, " [on-chip]\n"); -skip_1: - local_irq_restore(flags); - } - for (i = 0; i < MALTAINT_END; i++, num++) { - local_irq_save(flags); - action = hw0_irq_action[i]; - if (!action) - goto skip_2; - seq_printf(p, "%2d: %8d %c %s", - num, kstat_cpu(0).irqs[num], - (action->flags & SA_INTERRUPT) ? '+' : ' ', - action->name); - for (action=action->next; action; action = action->next) { - seq_printf(p, ",%s %s", - (action->flags & SA_INTERRUPT) ? " +" : "", - action->name); - } - seq_puts(p, " [hw0]\n"); -skip_2: - local_irq_restore(flags); - } - return 0; -} - -int request_irq(unsigned int irq, - void (*handler)(int, void *, struct pt_regs *), - unsigned long irqflags, - const char * devname, - void *dev_id) -{ - struct irqaction *action; - int retval; - - DEBUG_INT("request_irq: irq=%d, devname = %s\n", irq, devname); - - if (irq >= MALTAINT_END) - return -EINVAL; - if (!handler) - return -EINVAL; - - action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL); - if(!action) - return -ENOMEM; - - action->handler = handler; - action->flags = irqflags; - action->mask = 0; - action->name = devname; - action->dev_id = dev_id; - action->next = 0; - - retval = setup_irq(irq, action); - if (retval) - kfree(action); - - return retval; -} - - -void free_irq(unsigned int irq, void *dev_id) -{ - struct irqaction *action, **p; - - if (irq >= MALTAINT_END) { - printk("Trying to free IRQ%d\n",irq); - return; - } - - for (p = &hw0_irq_action[irq]; (action = *p) != NULL; - p = &action->next) - { - if (action->dev_id != dev_id) - continue; - - /* Found it - now free it */ - *p = action->next; - kfree(action); - if (!hw0_irq_action[irq]) - disable_irq(irq); - return; - } - printk("Trying to free IRQ%d\n",irq); -} - -void __init init_IRQ(void) -{ - irq_setup(); -} - -static int setup_irq(unsigned int irq, struct irqaction * new) -{ - int shared = 0; - struct irqaction *old, **p; - - p = &hw0_irq_action[irq]; - if ((old = *p) != NULL) { - /* Can't share interrupts unless both agree to */ - if (!(old->flags & new->flags & SA_SHIRQ)) - return -EBUSY; - - /* Can't share interrupts unless both are same type */ - if ((old->flags ^ new->flags) & SA_INTERRUPT) - return -EBUSY; - - /* add new interrupt at end of irq queue */ - do { - p = &old->next; - old = *p; - } while (old); - shared = 1; - } - - if (new->flags & SA_SAMPLE_RANDOM) - rand_initialize_irq(irq); - - *p = new; - if (!shared) - enable_irq(irq); - - return 0; -} - -static inline int get_int(int *irq) -{ - /* - * Determine highest priority pending interrupt by performing - * a PCI Interrupt Acknowledge cycle. - */ - GT_READ(GT_PCI0_IACK_OFS, *irq); - *irq &= 0xFF; - - /* - * IRQ7 is used to detect spurious interrupts. - * The interrupt acknowledge cycle returns IRQ7, if no - * interrupts is requested. - * We can differentiate between this situation and a - * "Normal" IRQ7 by reading the ISR. - */ - if (*irq == 7) - { - outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR, PIIX4_ICTLR1_OCW3); - if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) - return -1; /* Spurious interrupt. */ - } - - return 0; -} - -static inline void ack_int(int irq) -{ - if (irq & 8) { - /* Specific EOI to cascade */ - outb(PIIX4_OCW2_SEL | PIIX4_OCW2_NSEOI | PIIX4_OCW2_ILS_2, - PIIX4_ICTLR1_OCW2); - - /* Non specific EOI to cascade */ - outb(PIIX4_OCW2_SEL | PIIX4_OCW2_NSEOI, PIIX4_ICTLR2_OCW2); - } else { - /* Non specific EOI to cascade */ - outb(PIIX4_OCW2_SEL | PIIX4_OCW2_NSEOI, PIIX4_ICTLR1_OCW2); - } -} - -void malta_hw0_irqdispatch(struct pt_regs *regs) -{ - struct irqaction *action; - int irq=0, cpu = smp_processor_id(); - - DEBUG_INT("malta_hw0_irqdispatch\n"); - - if (get_int(&irq)) - return; /* interrupt has already been cleared */ - - disable_irq(irq); - ack_int(irq); - - DEBUG_INT("malta_hw0_irqdispatch: irq=%d\n", irq); - action = hw0_irq_action[irq]; - - /* - * if action == NULL, then we don't have a handler - * for the irq - */ - if ( action == NULL ) - return; - - irq_enter(cpu, irq); - kstat_cpu(0).irqs[irq + 8]++; - do { - action->handler(irq, action->dev_id, regs); - action = action->next; - } while (action); - - enable_irq(irq); - irq_exit(cpu, irq); -} - - -unsigned long probe_irq_on (void) -{ - unsigned int i, irqs = 0; - unsigned long delay; - - /* first, enable any unassigned irqs */ - for (i = MALTAINT_END-1; i > 0; i--) { - if (!hw0_irq_action[i]) { - enable_irq(i); - irqs |= (1 << i); - } - } - - /* wait for spurious interrupts to mask themselves out again */ - for (delay = jiffies + HZ/10; time_before(jiffies, delay); ) - /* about 100ms delay */; - - /* now filter out any obviously spurious interrupts */ - return irqs & ~cached_int_mask; -} - - -int probe_irq_off (unsigned long irqs) -{ - unsigned int i; - - irqs &= cached_int_mask; - if (!irqs) - return 0; - i = ffz(~irqs); - if (irqs != (irqs & (1 << i))) - i = -i; - - return i; -} - - -void __init maltaint_init(void) -{ - /* - * Mask out all interrupt by writing "1" to all bit position in - * the IMR register. - */ - outb(cached_int_mask & 0xff, PIIX4_ICTLR1_OCW1); - outb((cached_int_mask >> 8) & 0xff, PIIX4_ICTLR2_OCW1); - - /* Now safe to set the exception vector. */ - set_except_vector(0, mipsIRQ); -} --- linux-2.5.73/arch/mips64/mips-boards/malta/malta_rtc.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,50 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * RTC routines for Malta style attached PIIX4 device, which contains a - * Motorola MC146818A-compatible Real Time Clock. - * - */ -#include -#include - -static unsigned char malta_rtc_read_data(unsigned long addr) -{ - outb(addr, MALTA_RTC_ADR_REG); - return inb(MALTA_RTC_DAT_REG); -} - -static void malta_rtc_write_data(unsigned char data, unsigned long addr) -{ - outb(addr, MALTA_RTC_ADR_REG); - outb(data, MALTA_RTC_DAT_REG); -} - -static int malta_rtc_bcd_mode(void) -{ - return 0; -} - -struct rtc_ops malta_rtc_ops = { - &malta_rtc_read_data, - &malta_rtc_write_data, - &malta_rtc_bcd_mode -}; --- linux-2.5.73/arch/mips64/mips-boards/malta/malta_setup.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,170 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * Malta specific setup, including init of the feature struct. - * - */ -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_BLK_DEV_IDE -#include -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_BLK_DEV_FD -#include -#endif -#include -#include - -#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE) -extern void console_setup(char *, int *); -char serial_console[20]; -#endif - -#ifdef CONFIG_REMOTE_DEBUG -extern void set_debug_traps(void); -extern void rs_kgdb_hook(int); -extern void breakpoint(void); -static int remote_debug = 0; -#endif - -#ifdef CONFIG_BLK_DEV_IDE -extern struct ide_ops std_ide_ops; -#endif -#ifdef CONFIG_BLK_DEV_FD -extern struct fd_ops std_fd_ops; -#endif -extern struct rtc_ops malta_rtc_ops; - -extern void mips_reboot_setup(void); - -struct resource standard_io_resources[] = { - { "dma1", 0x00, 0x1f, IORESOURCE_BUSY }, - { "pic1", 0x20, 0x3f, IORESOURCE_BUSY }, - { "timer", 0x40, 0x5f, IORESOURCE_BUSY }, - { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY }, - { "pic2", 0xa0, 0xbf, IORESOURCE_BUSY }, - { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY }, -}; - -#define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource)) - -static void __init malta_irq_setup(void) -{ - maltaint_init(); - -#ifdef CONFIG_REMOTE_DEBUG - if (remote_debug) { - set_debug_traps(); - breakpoint(); - } -#endif -} - - -void __init malta_setup(void) -{ -#ifdef CONFIG_REMOTE_DEBUG - int rs_putDebugChar(char); - char rs_getDebugChar(void); - extern int (*putDebugChar)(char); - extern char (*getDebugChar)(void); -#endif - char *argptr; - int i; - - current_cpu_data.asid_cache = ASID_FIRST_VERSION; - TLBMISS_HANDLER_SETUP(); - - irq_setup = malta_irq_setup; - - /* Request I/O space for devices used on the Malta board. */ - for (i = 0; i < STANDARD_IO_RESOURCES; i++) - request_resource(&ioport_resource, standard_io_resources+i); - - /* - * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge. - */ - enable_dma(4); - -#ifdef CONFIG_SERIAL_CONSOLE - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "console=ttyS0")) == NULL) - { - int i=0; - char *s = prom_getenv("modetty0"); - while(s[i] >= '0' && s[i] <= '9') - i++; - strcpy(serial_console, "ttyS0,"); - strncpy(serial_console + 6, s, i); - prom_printf("Config serial console: %s\n", serial_console); - console_setup(serial_console, NULL); - } -#endif - -#ifdef CONFIG_REMOTE_DEBUG - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { - int line; - argptr += strlen("kgdb=ttyS"); - if (*argptr != '0' && *argptr != '1') - printk("KGDB: Uknown serial line /dev/ttyS%c, " - "falling back to /dev/ttyS1\n", *argptr); - line = *argptr == '0' ? 0 : 1; - printk("KGDB: Using serial line /dev/ttyS%d for session\n", - line ? 1 : 0); - - rs_kgdb_hook(line); - putDebugChar = rs_putDebugChar; - getDebugChar = rs_getDebugChar; - - prom_printf("KGDB: Using serial line /dev/ttyS%d for session, " - "please connect your debugger\n", line ? 1 : 0); - - remote_debug = 1; - /* Breakpoints and stuff are in malta_irq_setup() */ - } -#endif - - argptr = prom_getcmdline(); - if ((argptr = strstr(argptr, "nofpu")) != NULL) - mips_cpu.options &= ~MIPS_CPU_FPU; - - rtc_ops = &malta_rtc_ops; -#ifdef CONFIG_BLK_DEV_IDE - ide_ops = &std_ide_ops; -#endif -#ifdef CONFIG_BLK_DEV_FD - fd_ops = &std_fd_ops; -#endif -} --- linux-2.5.73/arch/mips64/mm/andes.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,391 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 1998, 1999 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2000 Kanoj Sarcar (kanoj@sgi.com) - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static int scache_lsz64; - -/* - * This version has been tuned on an Origin. For other machines the arguments - * of the pref instructin may have to be tuned differently. - */ -static void andes_clear_page(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tpref 7,512(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), "I" (PAGE_SIZE) - :"$1", "memory"); -} - -/* R10000 has no Create_Dirty type cacheops. */ -static void andes_copy_page(void * to, void * from) -{ - unsigned long dummy1, dummy2, reg1, reg2, reg3, reg4; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%8\n" - "1:\tpref\t0,2*128(%1)\n\t" - "pref\t1,2*128(%0)\n\t" - "ld\t%2,(%1)\n\t" - "ld\t%3,8(%1)\n\t" - "ld\t%4,16(%1)\n\t" - "ld\t%5,24(%1)\n\t" - "sd\t%2,(%0)\n\t" - "sd\t%3,8(%0)\n\t" - "sd\t%4,16(%0)\n\t" - "sd\t%5,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "ld\t%2,-32(%1)\n\t" - "ld\t%3,-24(%1)\n\t" - "ld\t%4,-16(%1)\n\t" - "ld\t%5,-8(%1)\n\t" - "sd\t%2,-32(%0)\n\t" - "sd\t%3,-24(%0)\n\t" - "sd\t%4,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - " sd\t%5,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2), - "=&r" (reg3), "=&r" (reg4) - :"0" (to), "1" (from), "I" (PAGE_SIZE)); -} - -/* Cache operations. These are only used with the virtual memory system, - not for non-coherent I/O so it's ok to ignore the secondary caches. */ -static void -andes_flush_cache_l1(void) -{ - blast_dcache32(); blast_icache64(); -} - -/* - * This is only used during initialization time. vmalloc() also calls - * this, but that will be changed pretty soon. - */ -static void -andes_flush_cache_l2(void) -{ - switch (sc_lsize()) { - case 64: - blast_scache64(); - break; - case 128: - blast_scache128(); - break; - default: - printk("Unknown L2 line size\n"); - while(1); - } -} - -void -andes_flush_icache_page(unsigned long page) -{ - if (scache_lsz64) - blast_scache64_page(page); - else - blast_scache128_page(page); -} - -static void -andes_flush_cache_sigtramp(unsigned long addr) -{ - protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); - protected_flush_icache_line(addr & ~(ic_lsize - 1)); -} - -#define NTLB_ENTRIES 64 -#define NTLB_ENTRIES_HALF 32 - -static inline void -andes_flush_tlb_all(void) -{ - unsigned long flags; - unsigned long old_ctx; - unsigned long entry; - -#ifdef DEBUG_TLB - printk("[tlball]"); -#endif - - local_irq_save(flags); - /* Save old context and create impossible VPN2 value */ - old_ctx = get_entryhi() & 0xff; - set_entryhi(CKSEG0); - set_entrylo0(0); - set_entrylo1(0); - - entry = get_wired(); - - /* Blast 'em all away. */ - while(entry < NTLB_ENTRIES) { - set_index(entry); - tlb_write_indexed(); - entry++; - } - set_entryhi(old_ctx); - local_irq_restore(flags); -} - -static void andes_flush_tlb_mm(struct mm_struct *mm) -{ - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { - unsigned long flags; - -#ifdef DEBUG_TLB - printk("[tlbmm<%d>]", mm->context); -#endif - local_irq_save(flags); - get_new_cpu_mmu_context(mm, smp_processor_id()); - if(mm == current->mm) - set_entryhi(CPU_CONTEXT(smp_processor_id(), mm) & 0xff); - local_irq_restore(flags); - } -} - -static void -andes_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { - unsigned long flags; - int size; - -#ifdef DEBUG_TLB - printk("[tlbrange<%02x,%08lx,%08lx>]", (mm->context & 0xff), - start, end); -#endif - local_irq_save(flags); - size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - size = (size + 1) >> 1; - if(size <= NTLB_ENTRIES_HALF) { - int oldpid = (get_entryhi() & 0xff); - int newpid = (CPU_CONTEXT(smp_processor_id(), mm) & 0xff); - - start &= (PAGE_MASK << 1); - end += ((PAGE_SIZE << 1) - 1); - end &= (PAGE_MASK << 1); - while(start < end) { - int idx; - - set_entryhi(start | newpid); - start += (PAGE_SIZE << 1); - tlb_probe(); - idx = get_index(); - set_entrylo0(0); - set_entrylo1(0); - set_entryhi(KSEG0); - if(idx < 0) - continue; - tlb_write_indexed(); - } - set_entryhi(oldpid); - } else { - get_new_cpu_mmu_context(mm, smp_processor_id()); - if(mm == current->mm) - set_entryhi(CPU_CONTEXT(smp_processor_id(), mm) & - 0xff); - } - local_irq_restore(flags); - } -} - -static void -andes_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) -{ - if (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) != 0) { - unsigned long flags; - int oldpid, newpid, idx; - -#ifdef DEBUG_TLB - printk("[tlbpage<%d,%08lx>]", vma->vm_mm->context, page); -#endif - newpid = (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) & 0xff); - page &= (PAGE_MASK << 1); - local_irq_save(flags); - oldpid = (get_entryhi() & 0xff); - set_entryhi(page | newpid); - tlb_probe(); - idx = get_index(); - set_entrylo0(0); - set_entrylo1(0); - set_entryhi(KSEG0); - if(idx < 0) - goto finish; - tlb_write_indexed(); - - finish: - set_entryhi(oldpid); - local_irq_restore(flags); - } -} - -/* XXX Simplify this. On the R10000 writing a TLB entry for an virtual - address that already exists will overwrite the old entry and not result - in TLB malfunction or TLB shutdown. */ -static void andes_update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) -{ - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - int idx, pid; - - /* - * Handle debugger faulting in for debugee. - */ - if (current->active_mm != vma->vm_mm) - return; - - local_irq_save(flags); - pid = get_entryhi() & 0xff; - - if((pid != (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) & 0xff)) || - (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) == 0)) { - printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d " - "tlbpid=%d\n", (int) (CPU_CONTEXT(smp_processor_id(), - vma->vm_mm) & 0xff), pid); - } - - address &= (PAGE_MASK << 1); - set_entryhi(address | (pid)); - pgdp = pgd_offset(vma->vm_mm, address); - tlb_probe(); - pmdp = pmd_offset(pgdp, address); - idx = get_index(); - ptep = pte_offset(pmdp, address); - set_entrylo0(pte_val(*ptep++) >> 6); - set_entrylo1(pte_val(*ptep) >> 6); - set_entryhi(address | (pid)); - if(idx < 0) { - tlb_write_random(); - } else { - tlb_write_indexed(); - } - set_entryhi(pid); - local_irq_restore(flags); -} - -static void andes_show_regs(struct pt_regs *regs) -{ - printk("Cpu %d\n", smp_processor_id()); - /* Saved main processor registers. */ - printk("$0 : %016lx %016lx %016lx %016lx\n", - 0UL, regs->regs[1], regs->regs[2], regs->regs[3]); - printk("$4 : %016lx %016lx %016lx %016lx\n", - regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); - printk("$8 : %016lx %016lx %016lx %016lx\n", - regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11]); - printk("$12 : %016lx %016lx %016lx %016lx\n", - regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]); - printk("$16 : %016lx %016lx %016lx %016lx\n", - regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19]); - printk("$20 : %016lx %016lx %016lx %016lx\n", - regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]); - printk("$24 : %016lx %016lx\n", - regs->regs[24], regs->regs[25]); - printk("$28 : %016lx %016lx %016lx %016lx\n", - regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]); - printk("Hi : %016lx\n", regs->hi); - printk("Lo : %016lx\n", regs->lo); - - /* Saved cp0 registers. */ - printk("epc : %016lx %s\nbadvaddr: %016lx\n", - regs->cp0_epc, print_tainted(), regs->cp0_badvaddr); - printk("Status : %08x\nCause : %08x\n", - (unsigned int) regs->cp0_status, (unsigned int) regs->cp0_cause); -} - -void __init ld_mmu_andes(void) -{ - printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID)); - - printk("Primary instruction cache %dkb, linesize %d bytes\n", - icache_size >> 10, ic_lsize); - printk("Primary data cache %dkb, linesize %d bytes\n", - dcache_size >> 10, dc_lsize); - printk("Secondary cache sized at %ldK, linesize %ld\n", - scache_size() >> 10, sc_lsize()); - - _clear_page = andes_clear_page; - _copy_page = andes_copy_page; - - _flush_cache_l1 = andes_flush_cache_l1; - _flush_cache_l2 = andes_flush_cache_l2; - _flush_cache_sigtramp = andes_flush_cache_sigtramp; - - _flush_tlb_all = andes_flush_tlb_all; - _flush_tlb_mm = andes_flush_tlb_mm; - _flush_tlb_range = andes_flush_tlb_range; - _flush_tlb_page = andes_flush_tlb_page; - - switch (sc_lsize()) { - case 64: - scache_lsz64 = 1; - break; - case 128: - scache_lsz64 = 0; - break; - default: - printk("Unknown L2 line size\n"); - while(1); - } - - update_mmu_cache = andes_update_mmu_cache; - - _show_regs = andes_show_regs; - - flush_cache_l1(); - - /* - * You should never change this register: - * - On R4600 1.7 the tlbp never hits for pages smaller than - * the value in the c0_pagemask register. - * - The entire mm handling assumes the c0_pagemask register to - * be set for 4kb pages. - */ - write_32bit_cp0_register(CP0_PAGEMASK, PM_4K); - - /* From this point on the ARC firmware is dead. */ - _flush_tlb_all(); - - /* Did I tell you that ARC SUCKS? */ -} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/cache.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,60 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 2003 by Ralf Baechle + */ +#include +#include +#include + +#include + +asmlinkage int sys_cacheflush(void *addr, int bytes, int cache) +{ + /* This should flush more selectivly ... */ + __flush_cache_all(); + + return 0; +} + +void flush_dcache_page(struct page *page) +{ + unsigned long addr; + + if (page->mapping && + list_empty(&page->mapping->i_mmap) && + list_empty(&page->mapping->i_mmap_shared)) { + SetPageDcacheDirty(page); + + return; + } + + /* + * We could delay the flush for the !page->mapping case too. But that + * case is for exec env/arg pages and those are %99 certainly going to + * get faulted into the tlb (and thus flushed) anyways. + */ + addr = (unsigned long) page_address(page); + flush_data_cache_page(addr); +} + +void __update_cache(struct vm_area_struct *vma, unsigned long address, + pte_t pte) +{ + struct page *page; + unsigned long pfn, addr; + + pfn = pte_pfn(pte); + if (pfn_valid(pfn) && (page = pfn_to_page(pfn), page->mapping) && + Page_dcache_dirty(page)) { + if (pages_do_alias((unsigned long)page_address(page), + address & PAGE_MASK)) { + addr = (unsigned long) page_address(page); + flush_data_cache_page(addr); + } + + ClearPageDcacheDirty(page); + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/cerr-sb1.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,542 @@ +/* + * Copyright (C) 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include + +#ifndef CONFIG_SIBYTE_BUS_WATCHER +#include +#include +#include +#include +#endif + +/* SB1 definitions */ + +/* XXX should come from config1 XXX */ +#define SB1_CACHE_INDEX_MASK 0x1fe0 + +#define CP0_ERRCTL_RECOVERABLE (1 << 31) +#define CP0_ERRCTL_DCACHE (1 << 30) +#define CP0_ERRCTL_ICACHE (1 << 29) +#define CP0_ERRCTL_MULTIBUS (1 << 23) +#define CP0_ERRCTL_MC_TLB (1 << 15) +#define CP0_ERRCTL_MC_TIMEOUT (1 << 14) + +#define CP0_CERRI_TAG_PARITY (1 << 29) +#define CP0_CERRI_DATA_PARITY (1 << 28) +#define CP0_CERRI_EXTERNAL (1 << 26) + +#define CP0_CERRI_IDX_VALID(c) (!((c) & CP0_CERRI_EXTERNAL)) +#define CP0_CERRI_DATA (CP0_CERRI_DATA_PARITY) + +#define CP0_CERRD_MULTIPLE (1 << 31) +#define CP0_CERRD_TAG_STATE (1 << 30) +#define CP0_CERRD_TAG_ADDRESS (1 << 29) +#define CP0_CERRD_DATA_SBE (1 << 28) +#define CP0_CERRD_DATA_DBE (1 << 27) +#define CP0_CERRD_EXTERNAL (1 << 26) +#define CP0_CERRD_LOAD (1 << 25) +#define CP0_CERRD_STORE (1 << 24) +#define CP0_CERRD_FILLWB (1 << 23) +#define CP0_CERRD_COHERENCY (1 << 22) +#define CP0_CERRD_DUPTAG (1 << 21) + +#define CP0_CERRD_DPA_VALID(c) (!((c) & CP0_CERRD_EXTERNAL)) +#define CP0_CERRD_IDX_VALID(c) \ + (((c) & (CP0_CERRD_LOAD | CP0_CERRD_STORE)) ? (!((c) & CP0_CERRD_EXTERNAL)) : 0) +#define CP0_CERRD_CAUSES \ + (CP0_CERRD_LOAD | CP0_CERRD_STORE | CP0_CERRD_FILLWB | CP0_CERRD_COHERENCY | CP0_CERRD_DUPTAG) +#define CP0_CERRD_TYPES \ + (CP0_CERRD_TAG_STATE | CP0_CERRD_TAG_ADDRESS | CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE | CP0_CERRD_EXTERNAL) +#define CP0_CERRD_DATA (CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE) + +static uint32_t extract_ic(unsigned short addr, int data); +static uint32_t extract_dc(unsigned short addr, int data); + +static inline void breakout_errctl(unsigned int val) +{ + if (val & CP0_ERRCTL_RECOVERABLE) + prom_printf(" recoverable"); + if (val & CP0_ERRCTL_DCACHE) + prom_printf(" dcache"); + if (val & CP0_ERRCTL_ICACHE) + prom_printf(" icache"); + if (val & CP0_ERRCTL_MULTIBUS) + prom_printf(" multiple-buserr"); + prom_printf("\n"); +} + +static inline void breakout_cerri(unsigned int val) +{ + if (val & CP0_CERRI_TAG_PARITY) + prom_printf(" tag-parity"); + if (val & CP0_CERRI_DATA_PARITY) + prom_printf(" data-parity"); + if (val & CP0_CERRI_EXTERNAL) + prom_printf(" external"); + prom_printf("\n"); +} + +static inline void breakout_cerrd(unsigned int val) +{ + switch (val & CP0_CERRD_CAUSES) { + case CP0_CERRD_LOAD: + prom_printf(" load,"); + break; + case CP0_CERRD_STORE: + prom_printf(" store,"); + break; + case CP0_CERRD_FILLWB: + prom_printf(" fill/wb,"); + break; + case CP0_CERRD_COHERENCY: + prom_printf(" coherency,"); + break; + case CP0_CERRD_DUPTAG: + prom_printf(" duptags,"); + break; + default: + prom_printf(" NO CAUSE,"); + break; + } + if (!(val & CP0_CERRD_TYPES)) + prom_printf(" NO TYPE"); + else { + if (val & CP0_CERRD_MULTIPLE) + prom_printf(" multi-err"); + if (val & CP0_CERRD_TAG_STATE) + prom_printf(" tag-state"); + if (val & CP0_CERRD_TAG_ADDRESS) + prom_printf(" tag-address"); + if (val & CP0_CERRD_DATA_SBE) + prom_printf(" data-SBE"); + if (val & CP0_CERRD_DATA_DBE) + prom_printf(" data-DBE"); + if (val & CP0_CERRD_EXTERNAL) + prom_printf(" external"); + } + prom_printf("\n"); +} + +#ifndef CONFIG_SIBYTE_BUS_WATCHER + +static void check_bus_watcher(void) +{ + uint32_t status, l2_err, memio_err; + + /* Destructive read, clears register and interrupt */ + status = csr_in32(IO_SPACE_BASE | A_SCD_BUS_ERR_STATUS); + /* Bit 31 is always on, but there's no #define for that */ + if (status & ~(1UL << 31)) { + l2_err = csr_in32(IO_SPACE_BASE | A_BUS_L2_ERRORS); + memio_err = csr_in32(IO_SPACE_BASE | A_BUS_MEM_IO_ERRORS); + prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); + prom_printf("\nLast recorded signature:\n"); + prom_printf("Request %02x from %d, answered by %d with Dcode %d\n", + (unsigned int)(G_SCD_BERR_TID(status) & 0x3f), + (int)(G_SCD_BERR_TID(status) >> 6), + (int)G_SCD_BERR_RID(status), + (int)G_SCD_BERR_DCODE(status)); + } else { + prom_printf("Bus watcher indicates no error\n"); + } +} +#else +extern void check_bus_watcher(void); +#endif + +asmlinkage void sb1_cache_error(void) +{ + uint64_t cerr_dpa; + uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res; + + prom_printf("Cache error exception on CPU %x:\n", + (read_c0_prid() >> 25) & 0x7); + + __asm__ __volatile__ ( + " .set push\n\t" + " .set mips64\n\t" + " .set noat\n\t" + " mfc0 %0, $26\n\t" + " mfc0 %1, $27\n\t" + " mfc0 %2, $27, 1\n\t" + " dmfc0 $1, $27, 3\n\t" + " dsrl32 %3, $1, 0 \n\t" + " sll %4, $1, 0 \n\t" + " mfc0 %5, $30\n\t" + " .set pop" + : "=r" (errctl), "=r" (cerr_i), "=r" (cerr_d), + "=r" (dpahi), "=r" (dpalo), "=r" (eepc)); + + cerr_dpa = (((uint64_t)dpahi) << 32) | dpalo; + prom_printf(" c0_errorepc == %08x\n", eepc); + prom_printf(" c0_errctl == %08x", errctl); + breakout_errctl(errctl); + if (errctl & CP0_ERRCTL_ICACHE) { + prom_printf(" c0_cerr_i == %08x", cerr_i); + breakout_cerri(cerr_i); + if (CP0_CERRI_IDX_VALID(cerr_i)) { + if ((eepc & SB1_CACHE_INDEX_MASK) != (cerr_i & SB1_CACHE_INDEX_MASK)) + prom_printf(" cerr_i idx doesn't match eepc\n"); + else { + res = extract_ic(cerr_i & SB1_CACHE_INDEX_MASK, + (cerr_i & CP0_CERRI_DATA) != 0); + if (!(res & cerr_i)) + prom_printf("...didn't see indicated icache problem\n"); + } + } + } + if (errctl & CP0_ERRCTL_DCACHE) { + prom_printf(" c0_cerr_d == %08x", cerr_d); + breakout_cerrd(cerr_d); + if (CP0_CERRD_DPA_VALID(cerr_d)) { + prom_printf(" c0_cerr_dpa == %010llx\n", cerr_dpa); + if (!CP0_CERRD_IDX_VALID(cerr_d)) { + res = extract_dc(cerr_dpa & SB1_CACHE_INDEX_MASK, + (cerr_d & CP0_CERRD_DATA) != 0); + if (!(res & cerr_d)) + prom_printf("...didn't see indicated dcache problem\n"); + } else { + if ((cerr_dpa & SB1_CACHE_INDEX_MASK) != (cerr_d & SB1_CACHE_INDEX_MASK)) + prom_printf(" cerr_d idx doesn't match cerr_dpa\n"); + else { + res = extract_dc(cerr_d & SB1_CACHE_INDEX_MASK, + (cerr_d & CP0_CERRD_DATA) != 0); + if (!(res & cerr_d)) + prom_printf("...didn't see indicated problem\n"); + } + } + } + } + + check_bus_watcher(); + + while (1); + /* + * This tends to make things get really ugly; let's just stall instead. + * panic("Can't handle the cache error!"); + */ +} + + +/* Parity lookup table. */ +static const uint8_t parity[256] = { + 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, + 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, + 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, + 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, + 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, + 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, + 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, + 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0 +}; + +/* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */ +static const uint64_t mask_72_64[8] = { + 0x0738C808099264FFL, + 0x38C808099264FF07L, + 0xC808099264FF0738L, + 0x08099264FF0738C8L, + 0x099264FF0738C808L, + 0x9264FF0738C80809L, + 0x64FF0738C8080992L, + 0xFF0738C808099264L +}; + +/* Calculate the parity on a range of bits */ +static char range_parity(uint64_t dword, int max, int min) +{ + char parity = 0; + int i; + dword >>= min; + for (i=max-min; i>=0; i--) { + if (dword & 0x1) + parity = !parity; + dword >>= 1; + } + return parity; +} + +/* Calculate the 4-bit even byte-parity for an instruction */ +static unsigned char inst_parity(uint32_t word) +{ + int i, j; + char parity = 0; + for (j=0; j<4; j++) { + char byte_parity = 0; + for (i=0; i<8; i++) { + if (word & 0x80000000) + byte_parity = !byte_parity; + word <<= 1; + } + parity <<= 1; + parity |= byte_parity; + } + return parity; +} + +static uint32_t extract_ic(unsigned short addr, int data) +{ + unsigned short way; + int valid; + uint64_t taglo, va, tlo_tmp; + uint32_t taghi, taglolo, taglohi; + uint8_t lru; + int res = 0; + + prom_printf("Icache index 0x%04x ", addr); + for (way = 0; way < 4; way++) { + /* Index-load-tag-I */ + __asm__ __volatile__ ( + " .set push \n\t" + " .set noreorder \n\t" + " .set mips64 \n\t" + " .set noat \n\t" + " cache 4, 0(%3) \n\t" + " mfc0 %0, $29 \n\t" + " dmfc0 $1, $28 \n\t" + " dsrl32 %1, $1, 0 \n\t" + " sll %2, $1, 0 \n\t" + " .set pop" + : "=r" (taghi), "=r" (taglohi), "=r" (taglolo) + : "r" ((way << 13) | addr)); + + taglo = ((unsigned long long)taglohi << 32) | taglolo; + if (way == 0) { + lru = (taghi >> 14) & 0xff; + prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", + ((addr >> 5) & 0x3), /* bank */ + ((addr >> 7) & 0x3f), /* index */ + (lru & 0x3), + ((lru >> 2) & 0x3), + ((lru >> 4) & 0x3), + ((lru >> 6) & 0x3)); + } + va = (taglo & 0xC0000FFFFFFFE000) | addr; + if ((taglo & (1 << 31)) && (((taglo >> 62) & 0x3) == 3)) + va |= 0x3FFFF00000000000; + valid = ((taghi >> 29) & 1); + if (valid) { + tlo_tmp = taglo & 0xfff3ff; + if (((taglo >> 10) & 1) ^ range_parity(tlo_tmp, 23, 0)) { + prom_printf(" ** bad parity in VTag0/G/ASID\n"); + res |= CP0_CERRI_TAG_PARITY; + } + if (((taglo >> 11) & 1) ^ range_parity(taglo, 63, 24)) { + prom_printf(" ** bad parity in R/VTag1\n"); + res |= CP0_CERRI_TAG_PARITY; + } + } + if (valid ^ ((taghi >> 27) & 1)) { + prom_printf(" ** bad parity for valid bit\n"); + res |= CP0_CERRI_TAG_PARITY; + } + prom_printf(" %d [VA %016llx] [Vld? %d] raw tags: %08X-%016llX\n", + way, va, valid, taghi, taglo); + + if (data) { + uint32_t datahi, insta, instb; + uint8_t predecode; + int offset; + + /* (hit all banks and ways) */ + for (offset = 0; offset < 4; offset++) { + /* Index-load-data-I */ + __asm__ __volatile__ ( + " .set push\n\t" + " .set noreorder\n\t" + " .set mips64\n\t" + " .set noat\n\t" + " cache 6, 0(%3) \n\t" + " mfc0 %0, $29, 1\n\t" + " dmfc0 $1, $28, 1\n\t" + " dsrl32 %1, $1, 0 \n\t" + " sll %2, $1, 0 \n\t" + " .set pop \n" + : "=r" (datahi), "=r" (insta), "=r" (instb) + : "r" ((way << 13) | addr | (offset << 3))); + predecode = (datahi >> 8) & 0xff; + if (((datahi >> 16) & 1) != (uint32_t)range_parity(predecode, 7, 0)) { + prom_printf(" ** bad parity in predecode\n"); + res |= CP0_CERRI_DATA_PARITY; + } + /* XXXKW should/could check predecode bits themselves */ + if (((datahi >> 4) & 0xf) ^ inst_parity(insta)) { + prom_printf(" ** bad parity in instruction a\n"); + res |= CP0_CERRI_DATA_PARITY; + } + if ((datahi & 0xf) ^ inst_parity(instb)) { + prom_printf(" ** bad parity in instruction b\n"); + res |= CP0_CERRI_DATA_PARITY; + } + prom_printf(" %05X-%08X%08X", datahi, insta, instb); + } + prom_printf("\n"); + } + } + return res; +} + +/* Compute the ECC for a data doubleword */ +static uint8_t dc_ecc(uint64_t dword) +{ + uint64_t t; + uint32_t w; + uint8_t p; + int i; + + p = 0; + for (i = 7; i >= 0; i--) + { + p <<= 1; + t = dword & mask_72_64[i]; + w = (uint32_t)(t >> 32); + p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF] + ^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]); + w = (uint32_t)(t & 0xFFFFFFFF); + p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF] + ^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]); + } + return p; +} + +struct dc_state { + unsigned char val; + char *name; +}; + +static struct dc_state dc_states[] = { + { 0x00, "INVALID" }, + { 0x0f, "COH-SHD" }, + { 0x13, "NCO-E-C" }, + { 0x19, "NCO-E-D" }, + { 0x16, "COH-E-C" }, + { 0x1c, "COH-E-D" }, + { 0xff, "*ERROR*" } +}; + +#define DC_TAG_VALID(state) \ + (((state) == 0xf) || ((state) == 0x13) || ((state) == 0x19) || ((state == 0x16)) || ((state) == 0x1c)) + +static char *dc_state_str(unsigned char state) +{ + struct dc_state *dsc = dc_states; + while (dsc->val != 0xff) { + if (dsc->val == state) + break; + dsc++; + } + return dsc->name; +} + +static uint32_t extract_dc(unsigned short addr, int data) +{ + int valid, way; + unsigned char state; + uint64_t taglo, pa; + uint32_t taghi, taglolo, taglohi; + uint8_t ecc, lru; + int res = 0; + + prom_printf("Dcache index 0x%04x ", addr); + for (way = 0; way < 4; way++) { + __asm__ __volatile__ ( + " .set push\n\t" + " .set noreorder\n\t" + " .set mips64\n\t" + " .set noat\n\t" + " cache 5, 0(%3)\n\t" /* Index-load-tag-D */ + " mfc0 %0, $29, 2\n\t" + " dmfc0 $1, $28, 2\n\t" + " dsrl32 %1, $1, 0\n\t" + " sll %2, $1, 0\n\t" + " .set pop" + : "=r" (taghi), "=r" (taglohi), "=r" (taglolo) + : "r" ((way << 13) | addr)); + + taglo = ((unsigned long long)taglohi << 32) | taglolo; + pa = (taglo & 0xFFFFFFE000) | addr; + if (way == 0) { + lru = (taghi >> 14) & 0xff; + prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", + ((addr >> 11) & 0x2) | ((addr >> 5) & 1), /* bank */ + ((addr >> 6) & 0x3f), /* index */ + (lru & 0x3), + ((lru >> 2) & 0x3), + ((lru >> 4) & 0x3), + ((lru >> 6) & 0x3)); + } + state = (taghi >> 25) & 0x1f; + valid = DC_TAG_VALID(state); + prom_printf(" %d [PA %010llx] [state %s (%02x)] raw tags: %08X-%016llX\n", + way, pa, dc_state_str(state), state, taghi, taglo); + if (valid) { + if (((taglo >> 11) & 1) ^ range_parity(taglo, 39, 26)) { + prom_printf(" ** bad parity in PTag1\n"); + res |= CP0_CERRD_TAG_ADDRESS; + } + if (((taglo >> 10) & 1) ^ range_parity(taglo, 25, 13)) { + prom_printf(" ** bad parity in PTag0\n"); + res |= CP0_CERRD_TAG_ADDRESS; + } + } else { + res |= CP0_CERRD_TAG_STATE; + } + + if (data) { + uint64_t datalo; + uint32_t datalohi, datalolo, datahi; + int offset; + + for (offset = 0; offset < 4; offset++) { + /* Index-load-data-D */ + __asm__ __volatile__ ( + " .set push\n\t" + " .set noreorder\n\t" + " .set mips64\n\t" + " .set noat\n\t" + " cache 7, 0(%3)\n\t" /* Index-load-data-D */ + " mfc0 %0, $29, 3\n\t" + " dmfc0 $1, $28, 3\n\t" + " dsrl32 %1, $1, 0 \n\t" + " sll %2, $1, 0 \n\t" + " .set pop" + : "=r" (datahi), "=r" (datalohi), "=r" (datalolo) + : "r" ((way << 13) | addr | (offset << 3))); + datalo = ((unsigned long long)datalohi << 32) | datalolo; + ecc = dc_ecc(datalo); + if (ecc != datahi) { + int bits = 0; + prom_printf(" ** bad ECC (%02x %02x) ->", + datahi, ecc); + ecc ^= datahi; + while (ecc) { + if (ecc & 1) bits++; + ecc >>= 1; + } + res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE; + } + prom_printf(" %02X-%016llX", datahi, datalo); + } + prom_printf("\n"); + } + } + return res; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/cex-sb1.S 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2001,2002,2003 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include +#include + +#include +#include +#include +#include +#include + + .text + .set noat + .set mips4 + + __INIT + + /* Cache Error handler for SB1 */ + LEAF(except_vec2_sb1) + mfc0 k1, $26 + # check if error was recoverable + bltz k1, leave_cerr +#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS + # look for signature of spurious CErr + lui k0, 0x4000 + bne k0, k1, 1f + .word 0x401Bd801 # mfc0 k1, $27, 1 + lui k0, 0xffe0 + and k1, k0, k1 + lui k0, 0x0200 + beq k0, k1, leave_cerr +1: +#endif + j handle_vec2_sb1 + +leave_cerr: + # clear/unlock the registers + mtc0 zero, $26 + mtc0 zero, $27 + .word 0x4080d801 # mtc0 zero, $27, 1 + .word 0x4080d803 # mtc0 zero, $27, 3 + eret + END(except_vec2_sb1) + + __FINIT + + LEAF(handle_vec2_sb1) + mfc0 k0,CP0_CONFIG + li k1,~CONF_CM_CMASK + and k0,k0,k1 + ori k0,k0,CONF_CM_UNCACHED + mtc0 k0,CP0_CONFIG + + SSNOP + SSNOP + SSNOP + SSNOP + bnezl $0, 1f +1: + mfc0 k0, CP0_STATUS + sll k0, k0, 3 # check CU0 (kernel?) + bltz k0, 2f + get_saved_sp + move sp, k1 # want Kseg SP (so uncached) +2: + j sb1_cache_error + + END(handle_vec2_sb1) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/c-r4k.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,1161 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Primary cache parameters. */ +static unsigned long icache_size, dcache_size, scache_size; +unsigned long icache_way_size, dcache_way_size, scache_way_size; +static unsigned long scache_size; + +#include +#include + +extern void andes_clear_page(void * page); +extern void r4k_clear_page32_d16(void * page); +extern void r4k_clear_page32_d32(void * page); +extern void r4k_clear_page_d16(void * page); +extern void r4k_clear_page_d32(void * page); +extern void r4k_clear_page_r4600_v1(void * page); +extern void r4k_clear_page_r4600_v2(void * page); +extern void r4k_clear_page_s16(void * page); +extern void r4k_clear_page_s32(void * page); +extern void r4k_clear_page_s64(void * page); +extern void r4k_clear_page_s128(void * page); +extern void andes_copy_page(void * to, void * from); +extern void r4k_copy_page_d16(void * to, void * from); +extern void r4k_copy_page_d32(void * to, void * from); +extern void r4k_copy_page_r4600_v1(void * to, void * from); +extern void r4k_copy_page_r4600_v2(void * to, void * from); +extern void r4k_copy_page_s16(void * to, void * from); +extern void r4k_copy_page_s32(void * to, void * from); +extern void r4k_copy_page_s64(void * to, void * from); +extern void r4k_copy_page_s128(void * to, void * from); + +/* + * Dummy cache handling routines for machines without boardcaches + */ +static void no_sc_noop(void) {} + +static struct bcache_ops no_sc_ops = { + .bc_enable = (void *)no_sc_noop, + .bc_disable = (void *)no_sc_noop, + .bc_wback_inv = (void *)no_sc_noop, + .bc_inv = (void *)no_sc_noop +}; + +struct bcache_ops *bcops = &no_sc_ops; + +#define R4600_HIT_CACHEOP_WAR_IMPL \ +do { \ + if (R4600_V2_HIT_CACHEOP_WAR && \ + (read_c0_prid() & 0xfff0) == 0x2020) { /* R4600 V2.0 */\ + *(volatile unsigned long *)KSEG1; \ + } \ + if (R4600_V1_HIT_CACHEOP_WAR) \ + __asm__ __volatile__("nop;nop;nop;nop"); \ +} while (0) + +static void r4k_blast_dcache_page(unsigned long addr) +{ + static void *l = &&init; + unsigned long dc_lsize; + + goto *l; + +dc_16: + blast_dcache16_page(addr); + return; + +dc_32: + R4600_HIT_CACHEOP_WAR_IMPL; + blast_dcache32_page(addr); + return; + +init: + dc_lsize = current_cpu_data.dcache.linesz; + + if (dc_lsize == 16) + l = &&dc_16; + else if (dc_lsize == 32) + l = &&dc_32; + goto *l; +} + +static void r4k_blast_dcache_page_indexed(unsigned long addr) +{ + static void *l = &&init; + unsigned long dc_lsize; + + goto *l; + +dc_16: + blast_dcache16_page_indexed(addr); + return; + +dc_32: + blast_dcache32_page_indexed(addr); + return; + +init: + dc_lsize = current_cpu_data.dcache.linesz; + + if (dc_lsize == 16) + l = &&dc_16; + else if (dc_lsize == 32) + l = &&dc_32; + goto *l; +} + +static void r4k_blast_dcache(void) +{ + static void *l = &&init; + unsigned long dc_lsize; + + goto *l; + +dc_16: + blast_dcache16(); + return; + +dc_32: + blast_dcache32(); + return; + +init: + dc_lsize = current_cpu_data.dcache.linesz; + + if (dc_lsize == 16) + l = &&dc_16; + else if (dc_lsize == 32) + l = &&dc_32; + goto *l; +} + +static void r4k_blast_icache_page(unsigned long addr) +{ + unsigned long ic_lsize = current_cpu_data.icache.linesz; + static void *l = &&init; + + goto *l; + +ic_16: + blast_icache16_page(addr); + return; + +ic_32: + blast_icache32_page(addr); + return; + +ic_64: + blast_icache64_page(addr); + return; + +init: + if (ic_lsize == 16) + l = &&ic_16; + else if (ic_lsize == 32) + l = &&ic_32; + else if (ic_lsize == 64) + l = &&ic_64; + goto *l; +} + +static void r4k_blast_icache_page_indexed(unsigned long addr) +{ + unsigned long ic_lsize = current_cpu_data.icache.linesz; + static void *l = &&init; + + goto *l; + +ic_16: + blast_icache16_page_indexed(addr); + return; + +ic_32: + blast_icache32_page_indexed(addr); + return; + +ic_64: + blast_icache64_page_indexed(addr); + return; + +init: + if (ic_lsize == 16) + l = &&ic_16; + else if (ic_lsize == 32) + l = &&ic_32; + else if (ic_lsize == 64) + l = &&ic_64; + goto *l; +} + +static void r4k_blast_icache(void) +{ + unsigned long ic_lsize = current_cpu_data.icache.linesz; + static void *l = &&init; + + goto *l; + +ic_16: + blast_icache16(); + return; + +ic_32: + blast_icache32(); + return; + +ic_64: + blast_icache64(); + return; + +init: + if (ic_lsize == 16) + l = &&ic_16; + else if (ic_lsize == 32) + l = &&ic_32; + else if (ic_lsize == 64) + l = &&ic_64; + goto *l; +} + +static void r4k_blast_scache_page(unsigned long addr) +{ + unsigned long sc_lsize = current_cpu_data.scache.linesz; + static void *l = &&init; + + goto *l; + +sc_16: + blast_scache16_page(addr); + return; + +sc_32: + blast_scache32_page(addr); + return; + +sc_64: + blast_scache64_page(addr); + return; + +sc_128: + blast_scache128_page(addr); + return; + +init: + if (sc_lsize == 16) + l = &&sc_16; + else if (sc_lsize == 32) + l = &&sc_32; + else if (sc_lsize == 64) + l = &&sc_64; + else if (sc_lsize == 128) + l = &&sc_128; + goto *l; +} + +static void r4k_blast_scache(void) +{ + unsigned long sc_lsize = current_cpu_data.scache.linesz; + static void *l = &&init; + + goto *l; + +sc_16: + blast_scache16(); + return; + +sc_32: + blast_scache32(); + return; + +sc_64: + blast_scache64(); + return; + +sc_128: + blast_scache128(); + return; + +init: + if (sc_lsize == 16) + l = &&sc_16; + else if (sc_lsize == 32) + l = &&sc_32; + else if (sc_lsize == 64) + l = &&sc_64; + else if (sc_lsize == 128) + l = &&sc_128; + goto *l; +} + +static void r4k_flush_cache_all(void) +{ + if (!cpu_has_dc_aliases) + return; + + r4k_blast_dcache(); + r4k_blast_icache(); +} + +static void r4k___flush_cache_all(void) +{ + r4k_blast_dcache(); + r4k_blast_icache(); + + switch (current_cpu_data.cputype) { + case CPU_R4000SC: + case CPU_R4000MC: + case CPU_R4400SC: + case CPU_R4400MC: + case CPU_R10000: + case CPU_R12000: + r4k_blast_scache(); + } +} + +static void r4k_flush_cache_range(struct vm_area_struct *vma, + unsigned long start, unsigned long end) +{ + if (cpu_context(smp_processor_id(), vma->vm_mm) != 0) { + r4k_blast_dcache(); + if (vma->vm_flags & VM_EXEC) + r4k_blast_icache(); + } +} + +static void r4k_flush_cache_mm(struct mm_struct *mm) +{ + if (!cpu_has_dc_aliases) + return; + + if (!cpu_context(smp_processor_id(), mm)) + return; + + r4k_blast_dcache(); + r4k_blast_icache(); + + /* + * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we + * only flush the primary caches but R10000 and R12000 behave sane ... + */ + if (current_cpu_data.cputype == CPU_R4000SC || + current_cpu_data.cputype == CPU_R4000MC || + current_cpu_data.cputype == CPU_R4400SC || + current_cpu_data.cputype == CPU_R4400MC) + r4k_blast_scache(); +} + +static void r4k_flush_cache_page(struct vm_area_struct *vma, + unsigned long page) +{ + int exec = vma->vm_flags & VM_EXEC; + struct mm_struct *mm = vma->vm_mm; + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + + /* + * If ownes no valid ASID yet, cannot possibly have gotten + * this page into the cache. + */ + if (cpu_context(smp_processor_id(), mm) == 0) + return; + + page &= PAGE_MASK; + pgdp = pgd_offset(mm, page); + pmdp = pmd_offset(pgdp, page); + ptep = pte_offset(pmdp, page); + + /* + * If the page isn't marked valid, the page cannot possibly be + * in the cache. + */ + if (!(pte_val(*ptep) & _PAGE_PRESENT)) + return; + + /* + * Doing flushes for another ASID than the current one is + * too difficult since stupid R4k caches do a TLB translation + * for every cache flush operation. So we do indexed flushes + * in that case, which doesn't overly flush the cache too much. + */ + if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { + if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) + r4k_blast_dcache_page(page); + if (exec) + r4k_blast_icache_page(page); + + return; + } + + /* + * Do indexed flush, too much work to get the (possible) TLB refills + * to work correctly. + */ + page = (KSEG0 + (page & (dcache_size - 1))); + if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) + r4k_blast_dcache_page_indexed(page); + if (exec) { + if (cpu_has_vtag_icache) { + int cpu = smp_processor_id(); + + if (cpu_context(cpu, vma->vm_mm) != 0) + drop_mmu_context(vma->vm_mm, cpu); + } else + r4k_blast_icache_page_indexed(page); + } +} + +static void r4k_flush_data_cache_page(unsigned long addr) +{ + r4k_blast_dcache_page(addr); +} + +static void r4k_flush_icache_range(unsigned long start, unsigned long end) +{ + unsigned long dc_lsize = current_cpu_data.dcache.linesz; + unsigned long addr, aend; + + if (!cpu_has_ic_fills_f_dc) { + if (end - start > dcache_size) + r4k_blast_dcache(); + else { + addr = start & ~(dc_lsize - 1); + aend = (end - 1) & ~(dc_lsize - 1); + + while (1) { + /* Hit_Writeback_Inv_D */ + protected_writeback_dcache_line(addr); + if (addr == aend) + break; + addr += dc_lsize; + } + } + } + + if (end - start > icache_size) + r4k_blast_icache(); + else { + addr = start & ~(dc_lsize - 1); + aend = (end - 1) & ~(dc_lsize - 1); + while (1) { + /* Hit_Invalidate_I */ + protected_flush_icache_line(addr); + if (addr == aend) + break; + addr += dc_lsize; + } + } +} + +/* + * Ok, this seriously sucks. We use them to flush a user page but don't + * know the virtual address, so we have to blast away the whole icache + * which is significantly more expensive than the real thing. Otoh we at + * least know the kernel address of the page so we can flush it + * selectivly. + */ +static void r4k_flush_icache_page(struct vm_area_struct *vma, + struct page *page) +{ + /* + * If there's no context yet, or the page isn't executable, no icache + * flush is needed. + */ + if (!(vma->vm_flags & VM_EXEC)) + return; + + /* + * Tricky ... Because we don't know the virtual address we've got the + * choice of either invalidating the entire primary and secondary + * caches or invalidating the secondary caches also. With the subset + * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the + * secondary cache will result in any entries in the primary caches + * also getting invalidated which hopefully is a bit more economical. + */ + if (cpu_has_subset_pcaches) { + unsigned long addr = (unsigned long) page_address(page); + r4k_blast_scache_page(addr); + + return; + } + + if (!cpu_has_ic_fills_f_dc) { + unsigned long addr = (unsigned long) page_address(page); + r4k_blast_dcache_page(addr); + } + + /* + * We're not sure of the virtual address(es) involved here, so + * we have to flush the entire I-cache. + */ + if (cpu_has_vtag_icache) { + int cpu = smp_processor_id(); + + if (cpu_context(cpu, vma->vm_mm) != 0) + drop_mmu_context(vma->vm_mm, cpu); + } else + r4k_blast_icache(); +} + +#ifdef CONFIG_NONCOHERENT_IO + +static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + + if (cpu_has_subset_pcaches) { + unsigned long sc_lsize = current_cpu_data.scache.linesz; + + if (size >= scache_size) { + r4k_blast_scache(); + return; + } + + a = addr & ~(sc_lsize - 1); + end = (addr + size - 1) & ~(sc_lsize - 1); + while (1) { + flush_scache_line(a); /* Hit_Writeback_Inv_SD */ + if (a == end) + break; + a += sc_lsize; + } + return; + } + + /* + * Either no secondary cache or the available caches don't have the + * subset property so we have to flush the primary caches + * explicitly + */ + if (size >= dcache_size) { + r4k_blast_dcache(); + } else { + unsigned long dc_lsize = current_cpu_data.dcache.linesz; + + R4600_HIT_CACHEOP_WAR_IMPL; + a = addr & ~(dc_lsize - 1); + end = (addr + size - 1) & ~(dc_lsize - 1); + while (1) { + flush_dcache_line(a); /* Hit_Writeback_Inv_D */ + if (a == end) + break; + a += dc_lsize; + } + } + + bc_wback_inv(addr, size); +} + +static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + + if (cpu_has_subset_pcaches) { + unsigned long sc_lsize = current_cpu_data.scache.linesz; + + if (size >= scache_size) { + r4k_blast_scache(); + return; + } + + a = addr & ~(sc_lsize - 1); + end = (addr + size - 1) & ~(sc_lsize - 1); + while (1) { + flush_scache_line(a); /* Hit_Writeback_Inv_SD */ + if (a == end) + break; + a += sc_lsize; + } + return; + } + + if (size >= dcache_size) { + r4k_blast_dcache(); + } else { + unsigned long dc_lsize = current_cpu_data.dcache.linesz; + + R4600_HIT_CACHEOP_WAR_IMPL; + a = addr & ~(dc_lsize - 1); + end = (addr + size - 1) & ~(dc_lsize - 1); + while (1) { + flush_dcache_line(a); /* Hit_Writeback_Inv_D */ + if (a == end) + break; + a += dc_lsize; + } + } + + bc_inv(addr, size); +} +#endif /* CONFIG_NONCOHERENT_IO */ + +/* + * While we're protected against bad userland addresses we don't care + * very much about what happens in that case. Usually a segmentation + * fault will dump the process later on anyway ... + */ +static void r4k_flush_cache_sigtramp(unsigned long addr) +{ + unsigned long ic_lsize = current_cpu_data.icache.linesz; + unsigned long dc_lsize = current_cpu_data.dcache.linesz; + + R4600_HIT_CACHEOP_WAR_IMPL; + protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); + protected_flush_icache_line(addr & ~(ic_lsize - 1)); +} + +static void r4k_flush_icache_all(void) +{ + if (cpu_has_vtag_icache) + r4k_blast_icache(); +} + +static inline void rm7k_erratum31(void) +{ + const unsigned long ic_lsize = 32; + unsigned long addr; + + /* RM7000 erratum #31. The icache is screwed at startup. */ + write_c0_taglo(0); + write_c0_taghi(0); + + for (addr = KSEG0; addr <= KSEG0 + 4096; addr += ic_lsize) { + __asm__ __volatile__ ( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache\t%1, 0(%0)\n\t" + "cache\t%1, 0x1000(%0)\n\t" + "cache\t%1, 0x2000(%0)\n\t" + "cache\t%1, 0x3000(%0)\n\t" + "cache\t%2, 0(%0)\n\t" + "cache\t%2, 0x1000(%0)\n\t" + "cache\t%2, 0x2000(%0)\n\t" + "cache\t%2, 0x3000(%0)\n\t" + "cache\t%1, 0(%0)\n\t" + "cache\t%1, 0x1000(%0)\n\t" + "cache\t%1, 0x2000(%0)\n\t" + "cache\t%1, 0x3000(%0)\n\t" + ".set\tmips0\n\t" + ".set\treorder\n\t" + : + : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); + } +} + +static char *way_string[] = { NULL, "direct mapped", "2-way", "3-way", "4-way", + "5-way", "6-way", "7-way", "8-way" +}; + +static void __init probe_pcache(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int config = read_c0_config(); + unsigned int prid = read_c0_prid(); + unsigned long config1; + unsigned int lsize; + + switch (current_cpu_data.cputype) { + case CPU_R4600: /* QED style two way caches? */ + case CPU_R4700: + case CPU_R5000: + case CPU_NEVADA: + icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + c->icache.ways = 2; + c->icache.waybit = ffs(icache_size/2) - 1; + + dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + c->dcache.ways = 2; + c->dcache.waybit= ffs(dcache_size/2) - 1; + break; + + case CPU_R5432: + case CPU_R5500: + icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + c->icache.ways = 2; + c->icache.waybit= 0; + + dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + c->dcache.ways = 2; + c->dcache.waybit = 0; + break; + + case CPU_TX49XX: + icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + c->icache.ways = 4; + c->icache.waybit= 0; + + dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + c->dcache.ways = 4; + c->dcache.waybit = 0; + break; + + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: + case CPU_R4400PC: + case CPU_R4400SC: + case CPU_R4400MC: + icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + c->icache.ways = 1; + c->icache.waybit = 0; /* doesn't matter */ + + dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + c->dcache.ways = 1; + c->dcache.waybit = 0; /* does not matter */ + break; + + case CPU_R10000: + case CPU_R12000: + icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); + c->icache.linesz = 64; + c->icache.ways = 2; + c->icache.waybit = 0; + + dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); + c->dcache.linesz = 32; + c->dcache.ways = 2; + c->dcache.waybit = 0; + break; + + case CPU_VR4131: + icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + c->icache.ways = 2; + c->icache.waybit = ffs(icache_size/2) - 1; + + dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + c->dcache.ways = 2; + c->dcache.waybit = ffs(dcache_size/2) - 1; + break; + + case CPU_VR41XX: + case CPU_VR4111: + case CPU_VR4121: + case CPU_VR4122: + case CPU_VR4181: + case CPU_VR4181A: + icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + c->icache.ways = 1; + c->icache.waybit = 0; /* doesn't matter */ + + dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + c->dcache.ways = 1; + c->dcache.waybit = 0; /* does not matter */ + break; + + case CPU_RM7000: + rm7k_erratum31(); + + icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + c->icache.ways = 4; + c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; + + dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + c->dcache.ways = 4; + c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1; + break; + + default: + if (!(config & MIPS_CONF_M)) + panic("Don't know how to probe P-caches on this cpu."); + + /* + * So we seem to be a MIPS32 or MIPS64 CPU + * So let's probe the I-cache ... + */ + config1 = read_c0_config1(); + + if ((lsize = ((config1 >> 19) & 7))) + c->icache.linesz = 2 << lsize; + else + c->icache.linesz = lsize; + c->icache.sets = 64 << ((config1 >> 22) & 7); + c->icache.ways = 1 + ((config1 >> 16) & 7); + + icache_size = c->icache.sets * + c->icache.ways * + c->icache.linesz; + c->icache.waybit = ffs(icache_size/c->icache.ways) - 1; + + /* + * Now probe the MIPS32 / MIPS64 data cache. + */ + c->dcache.flags = 0; + + if ((lsize = ((config1 >> 10) & 7))) + c->dcache.linesz = 2 << lsize; + else + c->dcache.linesz= lsize; + c->dcache.sets = 64 << ((config1 >> 13) & 7); + c->dcache.ways = 1 + ((config1 >> 7) & 7); + + dcache_size = c->dcache.sets * + c->dcache.ways * + c->dcache.linesz; + c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1; + break; + } + + /* + * Processor configuration sanity check for the R4000SC erratum + * #5. With page sizes larger than 32kB there is no possibility + * to get a VCE exception anymore so we don't care about this + * misconfiguration. The case is rather theoretical anyway; + * presumably no vendor is shipping his hardware in the "bad" + * configuration. + */ + if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 && + !(config & CONF_SC) && c->icache.linesz != 16 && + PAGE_SIZE <= 0x8000) + panic("Improper R4000SC processor configuration detected"); + + /* compute a couple of other cache variables */ + icache_way_size = icache_size / c->icache.ways; + dcache_way_size = dcache_size / c->dcache.ways; + + c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways); + c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways); + + /* + * R10000 and R12000 P-caches are odd in a positive way. They're 32kB + * 2-way virtually indexed so normally would suffer from aliases. So + * normally they'd suffer from aliases but magic in the hardware deals + * with that for us so we don't need to take care ourselves. + */ + if (current_cpu_data.cputype != CPU_R10000 && + current_cpu_data.cputype != CPU_R12000) + if (dcache_way_size > PAGE_SIZE) + c->dcache.flags |= MIPS_CACHE_ALIASES; + + if (config & 0x8) /* VI bit */ + c->icache.flags |= MIPS_CACHE_VTAG; + + switch (c->cputype) { + case CPU_20KC: + /* + * Some older 20Kc chips doesn't have the 'VI' bit in + * the config register. + */ + c->icache.flags |= MIPS_CACHE_VTAG; + break; + + case CPU_AU1500: + c->icache.flags |= MIPS_CACHE_IC_F_DC; + break; + } + + printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", + icache_size >> 10, + cpu_has_vtag_icache ? "virtually tagged" : "physically tagged", + way_string[c->icache.ways], c->icache.linesz); + + printk("Primary data cache %ldkB %s, linesize %d bytes.\n", + dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz); +} + +/* + * If you even _breathe_ on this function, look at the gcc output and make sure + * it does not pop things on and off the stack for the cache sizing loop that + * executes in KSEG1 space or else you will crash and burn badly. You have + * been warned. + */ +static int __init probe_scache(void) +{ + extern unsigned long stext; + unsigned long flags, addr, begin, end, pow2; + unsigned int config = read_c0_config(); + struct cpuinfo_mips *c = ¤t_cpu_data; + int tmp; + + if (config & CONF_SC) + return 0; + + begin = (unsigned long) &stext; + begin &= ~((4 * 1024 * 1024) - 1); + end = begin + (4 * 1024 * 1024); + + /* + * This is such a bitch, you'd think they would make it easy to do + * this. Away you daemons of stupidity! + */ + local_irq_save(flags); + + /* Fill each size-multiple cache line with a valid tag. */ + pow2 = (64 * 1024); + for (addr = begin; addr < end; addr = (begin + pow2)) { + unsigned long *p = (unsigned long *) addr; + __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ + pow2 <<= 1; + } + + /* Load first line with zero (therefore invalid) tag. */ + write_c0_taglo(0); + write_c0_taghi(0); + __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ + cache_op(Index_Store_Tag_I, begin); + cache_op(Index_Store_Tag_D, begin); + cache_op(Index_Store_Tag_SD, begin); + + /* Now search for the wrap around point. */ + pow2 = (128 * 1024); + tmp = 0; + for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { + cache_op(Index_Load_Tag_SD, addr); + __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ + if (!read_c0_taglo()) + break; + pow2 <<= 1; + } + local_irq_restore(flags); + addr -= begin; + + c = ¤t_cpu_data; + scache_size = addr; + c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); + c->scache.ways = 1; + c->dcache.waybit = 0; /* does not matter */ + + return 1; +} + +static void __init setup_noscache_funcs(void) +{ + unsigned int prid; + + switch (current_cpu_data.dcache.linesz) { + case 16: + if (cpu_has_64bits) + _clear_page = r4k_clear_page_d16; + else + _clear_page = r4k_clear_page32_d16; + _copy_page = r4k_copy_page_d16; + + break; + case 32: + prid = read_c0_prid() & 0xfff0; + if (prid == 0x2010) { /* R4600 V1.7 */ + _clear_page = r4k_clear_page_r4600_v1; + _copy_page = r4k_copy_page_r4600_v1; + } else if (prid == 0x2020) { /* R4600 V2.0 */ + _clear_page = r4k_clear_page_r4600_v2; + _copy_page = r4k_copy_page_r4600_v2; + } else { + if (cpu_has_64bits) + _clear_page = r4k_clear_page_d32; + else + _clear_page = r4k_clear_page32_d32; + _copy_page = r4k_copy_page_d32; + } + break; + } +} + +static void __init setup_scache_funcs(void) +{ + if (current_cpu_data.dcache.linesz > current_cpu_data.scache.linesz) + panic("Invalid primary cache configuration detected"); + + if (current_cpu_data.cputype == CPU_R10000 || + current_cpu_data.cputype == CPU_R12000) { + _clear_page = andes_clear_page; + _copy_page = andes_copy_page; + return; + } + + switch (current_cpu_data.scache.linesz) { + case 16: + _clear_page = r4k_clear_page_s16; + _copy_page = r4k_copy_page_s16; + break; + case 32: + _clear_page = r4k_clear_page_s32; + _copy_page = r4k_copy_page_s32; + break; + case 64: + _clear_page = r4k_clear_page_s64; + _copy_page = r4k_copy_page_s64; + break; + case 128: + _clear_page = r4k_clear_page_s128; + _copy_page = r4k_copy_page_s128; + break; + } +} + +typedef int (*probe_func_t)(unsigned long); +extern int r5k_sc_init(void); +extern int rm7k_sc_init(void); + +static void __init setup_scache(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int config = read_c0_config(); + probe_func_t probe_scache_kseg1; + int sc_present = 0; + + /* + * Do the probing thing on R4000SC and R4400SC processors. Other + * processors don't have a S-cache that would be relevant to the + * Linux memory managment. + */ + switch (current_cpu_data.cputype) { + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: + case CPU_R4400PC: + case CPU_R4400SC: + case CPU_R4400MC: + probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache)); + sc_present = probe_scache_kseg1(config); + break; + + case CPU_R10000: + case CPU_R12000: + scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); + c->scache.linesz = 64 << ((config >> 13) & 1); + c->scache.ways = 2; + c->scache.waybit= 0; + sc_present = 1; + break; + + case CPU_R5000: + case CPU_NEVADA: + setup_noscache_funcs(); +#ifdef CONFIG_R5000_CPU_SCACHE + r5k_sc_init(); +#endif + return; + + case CPU_RM7000: + setup_noscache_funcs(); +#ifdef CONFIG_RM7000_CPU_SCACHE + rm7k_sc_init(); +#endif + return; + + default: + sc_present = 0; + } + + if (!sc_present) { + setup_noscache_funcs(); + return; + } + + if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32 || + current_cpu_data.isa_level == MIPS_CPU_ISA_M64) && + !(current_cpu_data.scache.flags & MIPS_CACHE_NOT_PRESENT)) + panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); + + printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", + scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); + + current_cpu_data.options |= MIPS_CPU_SUBSET_CACHES; + setup_scache_funcs(); +} + +static inline void coherency_setup(void) +{ + change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); + + /* + * c0_status.cu=0 specifies that updates by the sc instruction use + * the coherency mode specified by the TLB; 1 means cachable + * coherent update on write will be used. Not all processors have + * this bit and; some wire it to zero, others like Toshiba had the + * silly idea of putting something else there ... + */ + switch (current_cpu_data.cputype) { + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: + case CPU_R4400PC: + case CPU_R4400SC: + case CPU_R4400MC: + clear_c0_config(CONF_CU); + break; + } + +} + +void __init ld_mmu_r4xx0(void) +{ + extern char except_vec2_generic; + + /* Default cache error handler for R4000 and R5000 family */ + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80); + memcpy((void *)(KSEG1 + 0x100), &except_vec2_generic, 0x80); + + probe_pcache(); + setup_scache(); + coherency_setup(); + + if (current_cpu_data.dcache.sets * + current_cpu_data.dcache.ways > PAGE_SIZE) + current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES; + + /* + * Some MIPS32 and MIPS64 processors have physically indexed caches. + * This code supports virtually indexed processors and will be + * unnecessarily unefficient on physically indexed processors. + */ + shm_align_mask = max_t(unsigned long, + current_cpu_data.dcache.sets * current_cpu_data.dcache.linesz - 1, + PAGE_SIZE - 1); + + flush_cache_all = r4k_flush_cache_all; + __flush_cache_all = r4k___flush_cache_all; + flush_cache_mm = r4k_flush_cache_mm; + flush_cache_page = r4k_flush_cache_page; + flush_icache_page = r4k_flush_icache_page; + flush_cache_range = r4k_flush_cache_range; + + flush_cache_sigtramp = r4k_flush_cache_sigtramp; + flush_icache_all = r4k_flush_icache_all; + flush_data_cache_page = r4k_flush_data_cache_page; + flush_icache_range = r4k_flush_icache_range; + +#ifdef CONFIG_NONCOHERENT_IO + _dma_cache_wback_inv = r4k_dma_cache_wback_inv; + _dma_cache_wback = r4k_dma_cache_wback_inv; + _dma_cache_inv = r4k_dma_cache_inv; +#endif + + __flush_cache_all(); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/c-sb1.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,594 @@ +/* + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include + +extern void sb1_clear_page(void * page); +extern void sb1_copy_page(void * to, void * from); + +/* These are probed at ld_mmu time */ +static unsigned long icache_size; +static unsigned long dcache_size; + +static unsigned long icache_line_size; +static unsigned long dcache_line_size; + +static unsigned int icache_index_mask; +static unsigned int dcache_index_mask; + +static unsigned long icache_assoc; +static unsigned long dcache_assoc; + +static unsigned int icache_sets; +static unsigned int dcache_sets; + +static unsigned int icache_range_cutoff; +static unsigned int dcache_range_cutoff; + +/* + * The dcache is fully coherent to the system, with one + * big caveat: the instruction stream. In other words, + * if we miss in the icache, and have dirty data in the + * L1 dcache, then we'll go out to memory (or the L2) and + * get the not-as-recent data. + * + * So the only time we have to flush the dcache is when + * we're flushing the icache. Since the L2 is fully + * coherent to everything, including I/O, we never have + * to flush it + */ + +/* + * Writeback and invalidate the entire dcache + */ +static inline void __sb1_writeback_inv_dcache_all(void) +{ + __asm__ __volatile__ ( + ".set push \n" + ".set noreorder \n" + ".set noat \n" + ".set mips4 \n" + " move $1, $0 \n" /* Start at index 0 */ + "1: cache %2, 0($1) \n" /* Invalidate this index */ + " cache %2, (1<<13)($1)\n" /* Invalidate this index */ + " cache %2, (2<<13)($1)\n" /* Invalidate this index */ + " cache %2, (3<<13)($1)\n" /* Invalidate this index */ + " daddiu %1, %1, -1 \n" /* Decrement loop count */ + " bnez %1, 1b \n" /* loop test */ + " daddu $1, $1, %0 \n" /* Next address */ + ".set pop \n" + : + : "r" (dcache_line_size), "r" (dcache_sets), + "i" (Index_Writeback_Inv_D)); +} + +/* + * Writeback and invalidate a range of the dcache. The addresses are + * virtual, and since we're using index ops and bit 12 is part of both + * the virtual frame and physical index, we have to clear both sets + * (bit 12 set and cleared). + */ +static inline void __sb1_writeback_inv_dcache_range(unsigned long start, + unsigned long end) +{ + __asm__ __volatile__ ( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips4 \n" + " and $1, %0, %3 \n" /* mask non-index bits */ + "1: cache %4, (0<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (1<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (2<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (3<<13)($1) \n" /* Index-WB-inval this address */ + " xori $1, $1, 1<<12 \n" + " cache %4, (0<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (1<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (2<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (3<<13)($1) \n" /* Index-WB-inval this address */ + " daddu %0, %0, %2 \n" /* next line */ + " bne %0, %1, 1b \n" /* loop test */ + " and $1, %0, %3 \n" /* mask non-index bits */ + " sync \n" + " .set pop \n" + : + : "r" (start & ~(dcache_line_size - 1)), + "r" ((end + dcache_line_size - 1) & ~(dcache_line_size - 1)), + "r" (dcache_line_size), + "r" (dcache_index_mask), + "i" (Index_Writeback_Inv_D)); +} + +/* + * Writeback and invalidate a range of the dcache. With physical + * addresseses, we don't have to worry about possible bit 12 aliasing. + * XXXKW is it worth turning on KX and using hit ops with xkphys? + */ +static inline void __sb1_writeback_inv_dcache_phys_range(unsigned long start, + unsigned long end) +{ + __asm__ __volatile__ ( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips4 \n" + " and $1, %0, %3 \n" /* mask non-index bits */ + "1: cache %4, (0<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (1<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (2<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (3<<13)($1) \n" /* Index-WB-inval this address */ + " daddu %0, %0, %2 \n" /* next line */ + " bne %0, %1, 1b \n" /* loop test */ + " and $1, %0, %3 \n" /* mask non-index bits */ + " sync \n" + " .set pop \n" + : + : "r" (start & ~(dcache_line_size - 1)), + "r" ((end + dcache_line_size - 1) & ~(dcache_line_size - 1)), + "r" (dcache_line_size), + "r" (dcache_index_mask), + "i" (Index_Writeback_Inv_D)); +} + + +/* + * Invalidate the entire icache + */ +static inline void __sb1_flush_icache_all(void) +{ + __asm__ __volatile__ ( + ".set push \n" + ".set noreorder \n" + ".set noat \n" + ".set mips4 \n" + " move $1, $0 \n" /* Start at index 0 */ + "1: cache %2, 0($1) \n" /* Invalidate this index */ + " cache %2, (1<<13)($1)\n" /* Invalidate this index */ + " cache %2, (2<<13)($1)\n" /* Invalidate this index */ + " cache %2, (3<<13)($1)\n" /* Invalidate this index */ + " daddiu %1, %1, -1 \n" /* Decrement loop count */ + " bnez %1, 1b \n" /* loop test */ + " daddu $1, $1, %0 \n" /* Next address */ + " bnezl $0, 2f \n" /* Force mispredict */ + " nop \n" + "2: sync \n" + ".set pop \n" + : + : "r" (icache_line_size), "r" (icache_sets), + "i" (Index_Invalidate_I)); +} + +/* + * Flush the icache for a given physical page. Need to writeback the + * dcache first, then invalidate the icache. If the page isn't + * executable, nothing is required. + */ +static void local_sb1_flush_cache_page(struct vm_area_struct *vma, + unsigned long addr) +{ + int cpu = smp_processor_id(); + +#ifndef CONFIG_SMP + if (!(vma->vm_flags & VM_EXEC)) + return; +#endif + + __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE); + + /* + * Bumping the ASID is probably cheaper than the flush ... + */ + if (cpu_context(cpu, vma->vm_mm) != 0) + drop_mmu_context(vma->vm_mm, cpu); +} + +#ifdef CONFIG_SMP +struct flush_cache_page_args { + struct vm_area_struct *vma; + unsigned long addr; +}; + +static void sb1_flush_cache_page_ipi(void *info) +{ + struct flush_cache_page_args *args = info; + + local_sb1_flush_cache_page(args->vma, args->addr); +} + +/* Dirty dcache could be on another CPU, so do the IPIs */ +static void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr) +{ + struct flush_cache_page_args args; + + if (!(vma->vm_flags & VM_EXEC)) + return; + + args.vma = vma; + args.addr = addr; + on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1); +} +#else +void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr); +asm("sb1_flush_cache_page = local_sb1_flush_cache_page"); +#endif + +/* + * Invalidate a range of the icache. The addresses are virtual, and + * the cache is virtually indexed and tagged. However, we don't + * necessarily have the right ASID context, so use index ops instead + * of hit ops. + */ +static inline void __sb1_flush_icache_range(unsigned long start, + unsigned long end) +{ + __asm__ __volatile__ ( + ".set push \n" + ".set noreorder \n" + ".set noat \n" + ".set mips4 \n" + " and $1, %0, %3 \n" /* mask non-index bits */ + "1: cache %4, (0<<13)($1) \n" /* Index-inval this address */ + " cache %4, (1<<13)($1) \n" /* Index-inval this address */ + " cache %4, (2<<13)($1) \n" /* Index-inval this address */ + " cache %4, (3<<13)($1) \n" /* Index-inval this address */ + " daddu %0, %0, %2 \n" /* next line */ + " bne %0, %1, 1b \n" /* loop test */ + " and $1, %0, %3 \n" /* mask non-index bits */ + " bnezl $0, 2f \n" /* Force mispredict */ + " nop \n" + "2: sync \n" + ".set pop \n" + : + : "r" (start & ~(icache_line_size - 1)), + "r" ((end + icache_line_size - 1) & ~(icache_line_size - 1)), + "r" (icache_line_size), + "r" (icache_index_mask), + "i" (Index_Invalidate_I)); +} + + +/* + * Invalidate all caches on this CPU + */ +static void local_sb1___flush_cache_all(void) +{ + __sb1_writeback_inv_dcache_all(); + __sb1_flush_icache_all(); +} + +#ifdef CONFIG_SMP +extern void sb1___flush_cache_all_ipi(void *ignored); +asm("sb1___flush_cache_all_ipi = local_sb1___flush_cache_all"); + +static void sb1___flush_cache_all(void) +{ + on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1); +} +#else +extern void sb1___flush_cache_all(void); +asm("sb1___flush_cache_all = local_sb1___flush_cache_all"); +#endif + +/* + * When flushing a range in the icache, we have to first writeback + * the dcache for the same range, so new ifetches will see any + * data that was dirty in the dcache. + * + * The start/end arguments are Kseg addresses (possibly mapped Kseg). + */ + +static void local_sb1_flush_icache_range(unsigned long start, + unsigned long end) +{ + /* Just wb-inv the whole dcache if the range is big enough */ + if ((end - start) > dcache_range_cutoff) + __sb1_writeback_inv_dcache_all(); + else + __sb1_writeback_inv_dcache_range(start, end); + + /* Just flush the whole icache if the range is big enough */ + if ((end - start) > icache_range_cutoff) + __sb1_flush_icache_all(); + else + __sb1_flush_icache_range(start, end); +} + +#ifdef CONFIG_SMP +struct flush_icache_range_args { + unsigned long start; + unsigned long end; +}; + +static void sb1_flush_icache_range_ipi(void *info) +{ + struct flush_icache_range_args *args = info; + + local_sb1_flush_icache_range(args->start, args->end); +} + +void sb1_flush_icache_range(unsigned long start, unsigned long end) +{ + struct flush_icache_range_args args; + + args.start = start; + args.end = end; + on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1); +} +#else +void sb1_flush_icache_range(unsigned long start, unsigned long end); +asm("sb1_flush_icache_range = local_sb1_flush_icache_range"); +#endif + +/* + * Flush the icache for a given physical page. Need to writeback the + * dcache first, then invalidate the icache. If the page isn't + * executable, nothing is required. + */ +static void local_sb1_flush_icache_page(struct vm_area_struct *vma, + struct page *page) +{ + unsigned long start; + int cpu = smp_processor_id(); + +#ifndef CONFIG_SMP + if (!(vma->vm_flags & VM_EXEC)) + return; +#endif + + /* Need to writeback any dirty data for that page, we have the PA */ + start = (unsigned long)(page-mem_map) << PAGE_SHIFT; + __sb1_writeback_inv_dcache_phys_range(start, start + PAGE_SIZE); + /* + * If there's a context, bump the ASID (cheaper than a flush, + * since we don't know VAs!) + */ + if (cpu_context(cpu, vma->vm_mm) != 0) { + drop_mmu_context(vma->vm_mm, cpu); + } +} + +#ifdef CONFIG_SMP +struct flush_icache_page_args { + struct vm_area_struct *vma; + struct page *page; +}; + +static void sb1_flush_icache_page_ipi(void *info) +{ + struct flush_icache_page_args *args = info; + local_sb1_flush_icache_page(args->vma, args->page); +} + +/* Dirty dcache could be on another CPU, so do the IPIs */ +static void sb1_flush_icache_page(struct vm_area_struct *vma, + struct page *page) +{ + struct flush_icache_page_args args; + + if (!(vma->vm_flags & VM_EXEC)) + return; + args.vma = vma; + args.page = page; + on_each_cpu(sb1_flush_icache_page_ipi, (void *) &args, 1, 1); +} +#else +void sb1_flush_icache_page(struct vm_area_struct *vma, struct page *page); +asm("sb1_flush_icache_page = local_sb1_flush_icache_page"); +#endif + +/* + * A signal trampoline must fit into a single cacheline. + */ +static void local_sb1_flush_cache_sigtramp(unsigned long addr) +{ + __asm__ __volatile__ ( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips4 \n" + " cache %2, (0<<13)(%0) \n" /* Index-inval this address */ + " cache %2, (1<<13)(%0) \n" /* Index-inval this address */ + " cache %2, (2<<13)(%0) \n" /* Index-inval this address */ + " cache %2, (3<<13)(%0) \n" /* Index-inval this address */ + " xori $1, %0, 1<<12 \n" /* Flip index bit 12 */ + " cache %2, (0<<13)($1) \n" /* Index-inval this address */ + " cache %2, (1<<13)($1) \n" /* Index-inval this address */ + " cache %2, (2<<13)($1) \n" /* Index-inval this address */ + " cache %2, (3<<13)($1) \n" /* Index-inval this address */ + " cache %3, (0<<13)(%1) \n" /* Index-inval this address */ + " cache %3, (1<<13)(%1) \n" /* Index-inval this address */ + " cache %3, (2<<13)(%1) \n" /* Index-inval this address */ + " cache %3, (3<<13)(%1) \n" /* Index-inval this address */ + " bnezl $0, 1f \n" /* Force mispredict */ + " nop \n" + "1: \n" + " .set pop \n" + : + : "r" (addr & dcache_index_mask), "r" (addr & icache_index_mask), + "i" (Index_Writeback_Inv_D), "i" (Index_Invalidate_I)); +} + +#ifdef CONFIG_SMP +static void sb1_flush_cache_sigtramp_ipi(void *info) +{ + unsigned long iaddr = (unsigned long) info; + local_sb1_flush_cache_sigtramp(iaddr); +} + +static void sb1_flush_cache_sigtramp(unsigned long addr) +{ + on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1); +} +#else +void sb1_flush_cache_sigtramp(unsigned long addr); +asm("sb1_flush_cache_sigtramp = local_sb1_flush_cache_sigtramp"); +#endif + + +/* + * Anything that just flushes dcache state can be ignored, as we're always + * coherent in dcache space. This is just a dummy function that all the + * nop'ed routines point to + */ +static void sb1_nop(void) +{ +} + +/* + * Cache set values (from the mips64 spec) + * 0 - 64 + * 1 - 128 + * 2 - 256 + * 3 - 512 + * 4 - 1024 + * 5 - 2048 + * 6 - 4096 + * 7 - Reserved + */ + +static unsigned int decode_cache_sets(unsigned int config_field) +{ + if (config_field == 7) { + /* JDCXXX - Find a graceful way to abort. */ + return 0; + } + return (1<<(config_field + 6)); +} + +/* + * Cache line size values (from the mips64 spec) + * 0 - No cache present. + * 1 - 4 bytes + * 2 - 8 bytes + * 3 - 16 bytes + * 4 - 32 bytes + * 5 - 64 bytes + * 6 - 128 bytes + * 7 - Reserved + */ + +static unsigned int decode_cache_line_size(unsigned int config_field) +{ + if (config_field == 0) { + return 0; + } else if (config_field == 7) { + /* JDCXXX - Find a graceful way to abort. */ + return 0; + } + return (1<<(config_field + 1)); +} + +/* + * Relevant bits of the config1 register format (from the MIPS32/MIPS64 specs) + * + * 24:22 Icache sets per way + * 21:19 Icache line size + * 18:16 Icache Associativity + * 15:13 Dcache sets per way + * 12:10 Dcache line size + * 9:7 Dcache Associativity + */ + +static __init void probe_cache_sizes(void) +{ + u32 config1; + + config1 = read_c0_config1(); + icache_line_size = decode_cache_line_size((config1 >> 19) & 0x7); + dcache_line_size = decode_cache_line_size((config1 >> 10) & 0x7); + icache_sets = decode_cache_sets((config1 >> 22) & 0x7); + dcache_sets = decode_cache_sets((config1 >> 13) & 0x7); + icache_assoc = ((config1 >> 16) & 0x7) + 1; + dcache_assoc = ((config1 >> 7) & 0x7) + 1; + icache_size = icache_line_size * icache_sets * icache_assoc; + dcache_size = dcache_line_size * dcache_sets * dcache_assoc; + /* Need to remove non-index bits for index ops */ + icache_index_mask = (icache_sets - 1) * icache_line_size; + dcache_index_mask = (dcache_sets - 1) * dcache_line_size; + /* + * These are for choosing range (index ops) versus all. + * icache flushes all ways for each set, so drop icache_assoc. + * dcache flushes all ways and each setting of bit 12 for each + * index, so drop dcache_assoc and halve the dcache_sets. + */ + icache_range_cutoff = icache_sets * icache_line_size; + dcache_range_cutoff = (dcache_sets / 2) * icache_line_size; +} + +/* + * This is called from loadmmu.c. We have to set up all the + * memory management function pointers, as well as initialize + * the caches and tlbs + */ +void ld_mmu_sb1(void) +{ + extern char except_vec2_sb1; + unsigned long temp; + + /* Special cache error handler for SB1 */ + memcpy((void *)(KSEG0 + 0x100), &except_vec2_sb1, 0x80); + memcpy((void *)(KSEG1 + 0x100), &except_vec2_sb1, 0x80); + + probe_cache_sizes(); + + _clear_page = sb1_clear_page; + _copy_page = sb1_copy_page; + + /* + * None of these are needed for the SB1 - the Dcache is + * physically indexed and tagged, so no virtual aliasing can + * occur + */ + flush_cache_range = (void *) sb1_nop; + flush_cache_page = sb1_flush_cache_page; + flush_cache_mm = (void (*)(struct mm_struct *))sb1_nop; + flush_cache_all = sb1_nop; + + /* These routines are for Icache coherence with the Dcache */ + flush_icache_range = sb1_flush_icache_range; + flush_icache_page = sb1_flush_icache_page; + flush_icache_all = __sb1_flush_icache_all; /* local only */ + + flush_cache_sigtramp = sb1_flush_cache_sigtramp; + flush_data_cache_page = (void *) sb1_nop; + + /* Full flush */ + __flush_cache_all = sb1___flush_cache_all; + + change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); + /* + * This is the only way to force the update of K0 to complete + * before subsequent instruction fetch. + */ + __asm__ __volatile__ ( + " .set push \n" + " .set mips4 \n" + " dla %0, 1f \n" + " dmtc0 %0, $14 \n" + " eret \n" + "1: .set pop \n" + : "=r" (temp)); + flush_cache_all(); +} --- linux-2.5.73/arch/mips64/mm/extable.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/mm/extable.c 2003-06-27 15:56:24.000000000 -0700 @@ -1,65 +1,30 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle - * Copyright (C) 1999 by Silicon Graphics + * linux/arch/i386/mm/extable.c */ + #include #include #include #include -extern const struct exception_table_entry __start___ex_table[]; -extern const struct exception_table_entry __stop___ex_table[]; - -static inline unsigned long -search_one_table(const struct exception_table_entry *first, - const struct exception_table_entry *last, - unsigned long value) +/* Simple binary search */ +const struct exception_table_entry * +search_extable(const struct exception_table_entry *first, + const struct exception_table_entry *last, + unsigned long value) { - while (first <= last) { + while (first <= last) { const struct exception_table_entry *mid; long diff; mid = (last - first) / 2 + first; diff = mid->insn - value; - if (diff == 0) - return mid->nextinsn; - else if (diff < 0) - first = mid+1; - else - last = mid-1; - } - return 0; -} - -extern spinlock_t modlist_lock; - -unsigned long search_exception_table(unsigned long addr) -{ - unsigned long ret = 0; - unsigned long flags; - -#ifndef CONFIG_MODULES - /* There is only the kernel to search. */ - ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr); - return ret; -#else - /* The kernel is the last "module" -- no need to treat it special. */ - struct module *mp; - - spin_lock_irqsave(&modlist_lock, flags); - for (mp = module_list; mp != NULL; mp = mp->next) { - if (mp->ex_table_start == NULL) - continue; - ret = search_one_table(mp->ex_table_start, - mp->ex_table_end - 1, addr); - if (ret) - break; - } - spin_unlock_irqrestore(&modlist_lock, flags); - return ret; -#endif + if (diff == 0) + return mid; + else if (diff < 0) + first = mid+1; + else + last = mid-1; + } + return NULL; } --- linux-2.5.73/arch/mips64/mm/fault.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/mm/fault.c 2003-06-27 15:56:24.000000000 -0700 @@ -20,7 +20,10 @@ #include #include #include +#include /* For unblank_screen() */ +#include +#include #include #include #include @@ -30,60 +33,34 @@ #define development_version (LINUX_VERSION_CODE & 0x100) -extern void die(char *, struct pt_regs *, unsigned long write); - /* * Macro for exception fixup code to access integer registers. */ #define dpf_reg(r) (regs->regs[r]) -asmlinkage void -dodebug(abi64_no_regargs, struct pt_regs regs) -{ - printk("Got syscall %ld, cpu %d proc %s:%d epc 0x%lx\n", regs.regs[2], - smp_processor_id(), current->comm, current->pid, regs.cp0_epc); -} - -asmlinkage void -dodebug2(abi64_no_regargs, struct pt_regs regs) -{ - unsigned long retaddr; - - __asm__ __volatile__( - ".set noreorder\n\t" - "add %0,$0,$31\n\t" - ".set reorder" - : "=r" (retaddr)); - printk("Got exception 0x%lx at 0x%lx\n", retaddr, regs.cp0_epc); -} - -extern spinlock_t timerlist_lock; - /* - * Unlock any spinlocks which will prevent us from getting the - * message out (timerlist_lock is acquired through the - * console unblank code) + * Unlock any spinlocks which will prevent us from getting the out */ void bust_spinlocks(int yes) { - spin_lock_init(&timerlist_lock); + int loglevel_save = console_loglevel; + if (yes) { oops_in_progress = 1; - } else { - int loglevel_save = console_loglevel; + return; + } #ifdef CONFIG_VT - unblank_screen(); + unblank_screen(); #endif - oops_in_progress = 0; - /* - * OK, the message is on the console. Now we call printk() - * without oops_in_progress set so that printk will give klogd - * a poke. Hold onto your hats... - */ - console_loglevel = 15; /* NMI oopser may have shut the console up */ - printk(" "); - console_loglevel = loglevel_save; - } + oops_in_progress = 0; + /* + * OK, the message is on the console. Now we call printk() + * without oops_in_progress set so that printk will give klogd + * a poke. Hold onto your hats... + */ + console_loglevel = 15; /* NMI oopser may have shut the console up */ + printk(" "); + console_loglevel = loglevel_save; } /* @@ -91,15 +68,20 @@ void bust_spinlocks(int yes) * and the problem, and then passes it off to one of the appropriate * routines. */ -asmlinkage void -do_page_fault(struct pt_regs *regs, unsigned long write, unsigned long address) +asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write, + unsigned long address) { struct vm_area_struct * vma; struct task_struct *tsk = current; struct mm_struct *mm = tsk->mm; - unsigned long fixup; + const struct exception_table_entry *fixup; siginfo_t info; +#if 0 + printk("Cpu%d[%s:%d:%08lx:%ld:%08lx]\n", smp_processor_id(), + current->comm, current->pid, address, write, regs->cp0_epc); +#endif + /* * We fault-in kernel-space virtual memory on-demand. The * 'reference' page table is init_mm.pgd. @@ -109,7 +91,7 @@ do_page_fault(struct pt_regs *regs, unsi * only copy the information from the master page table, * nothing more. */ - if (address >= TASK_SIZE) + if (address >= VMALLOC_START) goto vmalloc_fault; info.si_code = SEGV_MAPERR; @@ -117,12 +99,9 @@ do_page_fault(struct pt_regs *regs, unsi * If we're in an interrupt or have no user * context, we must not take the fault.. */ - if (in_interrupt() || mm == &init_mm) + if (in_atomic() || !mm) goto no_context; -#if DEBUG_MIPS64 - printk("Cpu%d[%s:%d:%08lx:%ld:%08lx]\n", smp_processor_id(), current->comm, - current->pid, address, write, regs->cp0_epc); -#endif + down_read(&mm->mmap_sem); vma = find_vma(mm, address); if (!vma) @@ -148,22 +127,25 @@ good_area: goto bad_area; } +survive: /* * If for any reason at all we couldn't handle the fault, * make sure we exit gracefully rather than endlessly redo * the fault. */ switch (handle_mm_fault(mm, vma, address, write)) { - case 1: + case VM_FAULT_MINOR: tsk->min_flt++; break; - case 2: + case VM_FAULT_MAJOR: tsk->maj_flt++; break; - case 0: + case VM_FAULT_SIGBUS: goto do_sigbus; - default: + case VM_FAULT_OOM: goto out_of_memory; + default: + BUG(); } up_read(&mm->mmap_sem); @@ -176,7 +158,7 @@ good_area: bad_area: up_read(&mm->mmap_sem); -bad_area_nosemaphore: + /* User mode accesses just cause a SIGSEGV */ if (user_mode(regs)) { tsk->thread.cp0_badvaddr = address; tsk->thread.error_code = write; @@ -199,12 +181,11 @@ bad_area_nosemaphore: no_context: /* Are we prepared to handle this kernel fault? */ - fixup = search_exception_table(regs->cp0_epc); + fixup = search_exception_tables(exception_epc(regs)); if (fixup) { - long new_epc; + unsigned long new_epc = fixup->nextinsn; tsk->thread.cp0_baduaddr = address; - new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc); if (development_version) printk(KERN_DEBUG "%s: Exception at [<%lx>] (%lx)\n", tsk->comm, regs->cp0_epc, new_epc); @@ -220,12 +201,9 @@ no_context: bust_spinlocks(1); printk(KERN_ALERT "Cpu %d Unable to handle kernel paging request at " - "address %08lx, epc == %08x, ra == %08x\n", - smp_processor_id(), address, (unsigned int) regs->cp0_epc, - (unsigned int) regs->regs[31]); - die("Oops", regs, write); - do_exit(SIGKILL); - bust_spinlocks(0); + "address %016lx, epc == %016lx, ra == %016lx\n", + smp_processor_id(), address, regs->cp0_epc, regs->regs[31]); + die("Oops", regs); /* * We ran out of memory, or some other thing happened to us that made @@ -233,6 +211,11 @@ no_context: */ out_of_memory: up_read(&mm->mmap_sem); + if (tsk->pid == 1) { + yield(); + down_read(&mm->mmap_sem); + goto survive; + } printk("VM: killing process %s\n", tsk->comm); if (user_mode(regs)) do_exit(SIGKILL); --- linux-2.5.73/arch/mips64/mm/init.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/mm/init.c 2003-06-27 15:56:24.000000000 -0700 @@ -27,13 +27,12 @@ #include #include #include +#include #include #include -#ifdef CONFIG_SGI_IP22 -#include -#endif #include #include +#include DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); @@ -57,20 +56,6 @@ void pgd_init(unsigned long page) } } -pgd_t *get_pgd_slow(void) -{ - pgd_t *ret, *init; - - ret = (pgd_t *) __get_free_pages(GFP_KERNEL, 1); - if (ret) { - init = pgd_offset(&init_mm, 0); - pgd_init((unsigned long)ret); - memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD, - (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); - } - return ret; -} - void pmd_init(unsigned long addr, unsigned long pagetable) { unsigned long *p, *end; @@ -91,31 +76,6 @@ void pmd_init(unsigned long addr, unsign } } -int do_check_pgt_cache(int low, int high) -{ - int freed = 0; - - if (pgtable_cache_size > high) { - do { - if (pgd_quicklist) - free_pgd_slow(get_pgd_fast()), freed++; - if (pmd_quicklist) - free_pmd_slow(get_pmd_fast()), freed++; - if (pte_quicklist) - free_pte_slow(get_pte_fast()), freed++; - } while (pgtable_cache_size > low); - } - return freed; -} - - -asmlinkage int sys_cacheflush(void *addr, int bytes, int cache) -{ - /* XXX Just get it working for now... */ - flush_cache_l1(); - return 0; -} - /* * We have up to 8 empty zeroed pages so we can map one of the right colour * when needed. This is necessary only on R4000 / R4400 SC and MC versions @@ -130,16 +90,10 @@ unsigned long setup_zero_pages(void) unsigned long order, size; struct page *page; - switch (mips_cputype) { - case CPU_R4000SC: - case CPU_R4000MC: - case CPU_R4400SC: - case CPU_R4400MC: + if (cpu_has_vce) order = 3; - break; - default: + else order = 0; - } empty_zero_page = __get_free_pages(GFP_KERNEL, order); if (!empty_zero_page) @@ -159,185 +113,6 @@ unsigned long setup_zero_pages(void) return 1UL << order; } -void __init add_memory_region(unsigned long start, unsigned long size, - long type) -{ - int x = boot_mem_map.nr_map; - - if (x == BOOT_MEM_MAP_MAX) { - printk("Ooops! Too many entries in the memory map!\n"); - return; - } - - boot_mem_map.map[x].addr = start; - boot_mem_map.map[x].size = size; - boot_mem_map.map[x].type = type; - boot_mem_map.nr_map++; -} - -static void __init print_memory_map(void) -{ - int i; - - for (i = 0; i < boot_mem_map.nr_map; i++) { - printk(" memory: %08lx @ %08lx ", - boot_mem_map.map[i].size, boot_mem_map.map[i].addr); - switch (boot_mem_map.map[i].type) { - case BOOT_MEM_RAM: - printk("(usable)\n"); - break; - case BOOT_MEM_ROM_DATA: - printk("(ROM data)\n"); - break; - case BOOT_MEM_RESERVED: - printk("(reserved)\n"); - break; - default: - printk("type %lu\n", boot_mem_map.map[i].type); - break; - } - } -} - -void bootmem_init(void) { -#ifdef CONFIG_BLK_DEV_INITRD - unsigned long tmp; - unsigned long *initrd_header; -#endif - unsigned long bootmap_size; - unsigned long start_pfn, max_pfn; - int i; - extern int _end; - -#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT) -#define PFN_DOWN(x) ((x) >> PAGE_SHIFT) -#define PFN_PHYS(x) ((x) << PAGE_SHIFT) - - /* - * Partially used pages are not usable - thus - * we are rounding upwards. - */ - start_pfn = PFN_UP(__pa(&_end)); - - /* Find the highest page frame number we have available. */ - max_pfn = 0; - for (i = 0; i < boot_mem_map.nr_map; i++) { - unsigned long start, end; - - if (boot_mem_map.map[i].type != BOOT_MEM_RAM) - continue; - - start = PFN_UP(boot_mem_map.map[i].addr); - end = PFN_DOWN(boot_mem_map.map[i].addr - + boot_mem_map.map[i].size); - - if (start >= end) - continue; - if (end > max_pfn) - max_pfn = end; - } - - /* Initialize the boot-time allocator. */ - bootmap_size = init_bootmem(start_pfn, max_pfn); - - /* - * Register fully available low RAM pages with the bootmem allocator. - */ - for (i = 0; i < boot_mem_map.nr_map; i++) { - unsigned long curr_pfn, last_pfn, size; - - /* - * Reserve usable memory. - */ - if (boot_mem_map.map[i].type != BOOT_MEM_RAM) - continue; - - /* - * We are rounding up the start address of usable memory: - */ - curr_pfn = PFN_UP(boot_mem_map.map[i].addr); - if (curr_pfn >= max_pfn) - continue; - if (curr_pfn < start_pfn) - curr_pfn = start_pfn; - - /* - * ... and at the end of the usable range downwards: - */ - last_pfn = PFN_DOWN(boot_mem_map.map[i].addr - + boot_mem_map.map[i].size); - - if (last_pfn > max_pfn) - last_pfn = max_pfn; - - /* - * ... finally, did all the rounding and playing - * around just make the area go away? - */ - if (last_pfn <= curr_pfn) - continue; - - size = last_pfn - curr_pfn; - free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size)); - } - - /* Reserve the bootmap memory. */ - reserve_bootmem(PFN_PHYS(start_pfn), bootmap_size); - -#ifdef CONFIG_BLK_DEV_INITRD -#error "Initrd is broken, please fit it." - tmp = (((unsigned long)&_end + PAGE_SIZE-1) & PAGE_MASK) - 8; - if (tmp < (unsigned long)&_end) - tmp += PAGE_SIZE; - initrd_header = (unsigned long *)tmp; - if (initrd_header[0] == 0x494E5244) { - initrd_start = (unsigned long)&initrd_header[2]; - initrd_end = initrd_start + initrd_header[1]; - initrd_below_start_ok = 1; - if (initrd_end > memory_end) { - printk("initrd extends beyond end of memory " - "(0x%08lx > 0x%08lx)\ndisabling initrd\n", - initrd_end,memory_end); - initrd_start = 0; - } else - *memory_start_p = initrd_end; - } -#endif - -#undef PFN_UP -#undef PFN_DOWN -#undef PFN_PHYS - -} - -void show_mem(void) -{ - int i, free = 0, total = 0, reserved = 0; - int shared = 0, cached = 0; - - printk("Mem-info:\n"); - show_free_areas(); - printk("Free swap: %6dkB\n", nr_swap_pages<<(PAGE_SHIFT-10)); - i = max_mapnr; - while (i-- > 0) { - total++; - if (PageReserved(mem_map+i)) - reserved++; - else if (PageSwapCache(mem_map+i)) - cached++; - else if (!page_count(mem_map + i)) - free++; - else - shared += page_count(mem_map + i) - 1; - } - printk("%d pages of RAM\n", total); - printk("%d reserved pages\n", reserved); - printk("%d pages shared\n", shared); - printk("%d pages swap cached\n",cached); - printk("%ld pages in page table cache\n", pgtable_cache_size); - printk("%d free pages\n", free); -} - #ifndef CONFIG_DISCONTIGMEM /* References to section boundaries */ @@ -361,7 +136,7 @@ void __init paging_init(void) max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT; low = max_low_pfn; -#if defined(CONFIG_PCI) || defined(CONFIG_ISA) +#ifdef CONFIG_ISA if (low < max_dma) zones_size[ZONE_DMA] = low; else { @@ -373,15 +148,38 @@ void __init paging_init(void) #endif free_area_init(zones_size); - - memset((void *)kptbl, 0, PAGE_SIZE << KPTBL_PAGE_ORDER); + + memset((void *)kptbl, 0, PAGE_SIZE << PGD_ORDER); memset((void *)kpmdtbl, 0, PAGE_SIZE); - pgd_set(swapper_pg_dir, kpmdtbl); - for (i = 0; i < (1 << KPTBL_PAGE_ORDER); pmd++,i++,pte+=PTRS_PER_PTE) + set_pgd(swapper_pg_dir, __pgd(kpmdtbl)); + for (i = 0; i < (1 << PGD_ORDER); pmd++,i++,pte+=PTRS_PER_PTE) pmd_val(*pmd) = (unsigned long)pte; } -extern int page_is_ram(unsigned long pagenr); +#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT) +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT) + +static inline int page_is_ram(unsigned long pagenr) +{ + int i; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + unsigned long addr, end; + + if (boot_mem_map.map[i].type != BOOT_MEM_RAM) + /* not usable memory */ + continue; + + addr = PFN_UP(boot_mem_map.map[i].addr); + end = PFN_DOWN(boot_mem_map.map[i].addr + + boot_mem_map.map[i].size); + + if (pagenr >= addr && pagenr < end) + return 1; + } + + return 0; +} void __init mem_init(void) { @@ -402,12 +200,12 @@ void __init mem_init(void) reservedpages++; } - codesize = (unsigned long) &_etext - (unsigned long) &_stext; - datasize = (unsigned long) &_edata - (unsigned long) &_fdata; + codesize = (unsigned long) &_etext - (unsigned long) &_text; + datasize = (unsigned long) &_edata - (unsigned long) &_etext; initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin; - printk("Memory: %luk/%luk available (%ldk kernel code, %ldk reserved, " - "%ldk data, %ldk init)\n", + printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, " + "%ldk reserved, %ldk data, %ldk init)\n", (unsigned long) nr_free_pages() << (PAGE_SHIFT-10), ram << (PAGE_SHIFT-10), codesize >> 10, @@ -420,26 +218,30 @@ void __init mem_init(void) #ifdef CONFIG_BLK_DEV_INITRD void free_initrd_mem(unsigned long start, unsigned long end) { + /* Switch from KSEG0 to XKPHYS addresses */ + start = (unsigned long)phys_to_virt(CPHYSADDR(start)); + end = (unsigned long)phys_to_virt(CPHYSADDR(end)); + if (start < end) + printk(KERN_INFO "Freeing initrd memory: %ldk freed\n", + (end - start) >> 10); + for (; start < end; start += PAGE_SIZE) { ClearPageReserved(virt_to_page(start)); set_page_count(virt_to_page(start), 1); free_page(start); totalram_pages++; } - printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10); } #endif -extern char __init_begin, __init_end; -extern void prom_free_prom_memory(void); +extern void prom_free_prom_memory(void) __init; -void -free_initmem(void) +void free_initmem(void) { unsigned long addr, page; prom_free_prom_memory(); - + addr = (unsigned long)(&__init_begin); while (addr < (unsigned long)&__init_end) { page = PAGE_OFFSET | CPHYSADDR(addr); @@ -449,6 +251,6 @@ free_initmem(void) totalram_pages++; addr += PAGE_SIZE; } - printk("Freeing unused kernel memory: %ldk freed\n", + printk(KERN_INFO "Freeing unused kernel memory: %ldk freed\n", (&__init_end - &__init_begin) >> 10); } --- linux-2.5.73/arch/mips64/mm/loadmmu.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/mm/loadmmu.c 2003-06-27 15:56:24.000000000 -0700 @@ -4,101 +4,117 @@ * for more details. * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997, 1999 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1997, 1999, 2000, 2001, 2002, 2003 Ralf Baechle (ralf@gnu.org) * Copyright (C) 1999 Silicon Graphics, Inc. + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. */ #include #include #include #include #include +#include +#include +#include #include #include #include -#include -#include /* memory functions */ void (*_clear_page)(void * page); void (*_copy_page)(void * to, void * from); /* Cache operations. */ -void (*_flush_cache_mm)(struct mm_struct *mm); -void (*_flush_cache_range)(struct vm_area_struct *vma, unsigned long start, - unsigned long end); -void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page); -void (*_flush_page_to_ram)(struct page * page); +void (*flush_cache_all)(void); +void (*__flush_cache_all)(void); +void (*flush_cache_mm)(struct mm_struct *mm); +void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, + unsigned long end); +void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page); +void (*flush_icache_range)(unsigned long start, unsigned long end); +void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); /* MIPS specific cache operations */ -void (*_flush_cache_sigtramp)(unsigned long addr); -void (*_flush_cache_l2)(void); -void (*_flush_cache_l1)(void); +void (*flush_cache_sigtramp)(unsigned long addr); +void (*flush_data_cache_page)(unsigned long addr); +void (*flush_icache_all)(void); +#ifdef CONFIG_NONCOHERENT_IO /* DMA cache operations. */ void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); void (*_dma_cache_wback)(unsigned long start, unsigned long size); void (*_dma_cache_inv)(unsigned long start, unsigned long size); -/* TLB operations. */ -void (*_flush_tlb_all)(void); -void (*_flush_tlb_mm)(struct mm_struct *mm); -void (*_flush_tlb_range)(struct vm_area_struct *vma, unsigned long start, - unsigned long end); -void (*_flush_tlb_page)(struct vm_area_struct *vma, unsigned long page); - -/* Miscellaneous. */ -void (*update_mmu_cache)(struct vm_area_struct * vma, - unsigned long address, pte_t pte); +EXPORT_SYMBOL(_dma_cache_wback_inv); +EXPORT_SYMBOL(_dma_cache_wback); +EXPORT_SYMBOL(_dma_cache_inv); -void (*_show_regs)(struct pt_regs *); +#endif /* CONFIG_NONCOHERENT_IO */ +extern void ld_mmu_r23000(void); extern void ld_mmu_r4xx0(void); +extern void ld_mmu_tx39(void); +extern void ld_mmu_r6000(void); +extern void ld_mmu_tfp(void); extern void ld_mmu_andes(void); +extern void ld_mmu_sb1(void); +extern void sb1_tlb_init(void); +extern void r3k_tlb_init(void); +extern void r4k_tlb_init(void); +extern void sb1_tlb_init(void); void __init load_mmu(void) { - switch(mips_cputype) { -#if defined (CONFIG_CPU_R4300) \ - || defined (CONFIG_CPU_R4X00) \ - || defined (CONFIG_CPU_R5000) \ - || defined (CONFIG_CPU_NEVADA) - case CPU_R4000PC: - case CPU_R4000SC: - case CPU_R4000MC: - case CPU_R4200: - case CPU_R4300: - case CPU_R4400PC: - case CPU_R4400SC: - case CPU_R4400MC: - case CPU_R4600: - case CPU_R4640: - case CPU_R4650: - case CPU_R4700: - case CPU_R5000: - case CPU_R5000A: - case CPU_NEVADA: - printk("Loading R4000 MMU routines.\n"); + if (cpu_has_4ktlb) { +#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \ + defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \ + defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \ + defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32) || \ + defined(CONFIG_CPU_MIPS64) || defined(CONFIG_CPU_TX49XX) || \ + defined(CONFIG_CPU_RM7000) ld_mmu_r4xx0(); + r4k_tlb_init(); +#endif + } else switch (current_cpu_data.cputype) { +#ifdef CONFIG_CPU_R3000 + case CPU_R2000: + case CPU_R3000: + case CPU_R3000A: + case CPU_R3081E: + ld_mmu_r23000(); + r3k_tlb_init(); break; #endif - -#if defined (CONFIG_CPU_R10000) +#ifdef CONFIG_CPU_TX39XX + case CPU_TX3912: + case CPU_TX3922: + case CPU_TX3927: + ld_mmu_tx39(); + r3k_tlb_init(); + break; +#endif +#ifdef CONFIG_CPU_R10000 case CPU_R10000: - printk("Loading R10000 MMU routines.\n"); - ld_mmu_andes(); + case CPU_R12000: + ld_mmu_r4xx0(); + andes_tlb_init(); + break; +#endif +#ifdef CONFIG_CPU_SB1 + case CPU_SB1: + ld_mmu_sb1(); + sb1_tlb_init(); break; #endif + case CPU_R8000: + panic("R8000 is unsupported"); + break; + default: - /* XXX We need an generic routine in the MIPS port - * XXX to jabber stuff onto the screen on all machines - * XXX before the console is setup. The ARCS prom - * XXX routines look good for this, but only the SGI - * XXX code has a full library for that at this time. - */ - panic("Yeee, unsupported mmu/cache architecture or " - "wrong compiletime kernel configuration."); + panic("Yeee, unsupported mmu/cache architecture."); } } --- linux-2.5.73/arch/mips64/mm/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/mm/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -2,11 +2,31 @@ # Makefile for the Linux/MIPS-specific parts of the memory manager. # -obj-y := extable.o init.o fault.o loadmmu.o +obj-y := cache.o extable.o init.o fault.o loadmmu.o \ + pgtable.o tlbex-r4k.o -obj-$(CONFIG_CPU_R4300) += r4xx0.o -obj-$(CONFIG_CPU_R4X00) += r4xx0.o -obj-$(CONFIG_CPU_R5000) += r4xx0.o -obj-$(CONFIG_CPU_NEVADA) += r4xx0.o -obj-$(CONFIG_CPU_R10000) += andes.o -obj-$(CONFIG_SGI_IP22) += umap.o +obj-$(CONFIG_CPU_R4300) += c-r4k.o pg-r4k.o tlb-r4k.o tlb-glue-r4k.o +obj-$(CONFIG_CPU_R4X00) += c-r4k.o pg-r4k.o tlb-r4k.o tlb-glue-r4k.o +obj-$(CONFIG_CPU_R5000) += c-r4k.o pg-r4k.o tlb-r4k.o sc-r5k.o \ + tlb-glue-r4k.o +obj-$(CONFIG_CPU_NEVADA) += c-r4k.o pg-r4k.o tlb-r4k.o sc-r5k.o \ + tlb-glue-r4k.o +obj-$(CONFIG_CPU_R5432) += c-r4k.o pg-r4k.o tlb-r4k.o tlb-glue-r4k.o +obj-$(CONFIG_CPU_RM7000) += c-r4k.o pg-r4k.o tlb-r4k.o tlb-glue-r4k.o +obj-$(CONFIG_CPU_R10000) += c-r4k.o pg-r4k.o tlb-andes.o tlb-glue-r4k.o +obj-$(CONFIG_CPU_SB1) += c-sb1.o pg-sb1.o tlb-sb1.o tlb-glue-sb1.o \ + cex-sb1.o cerr-sb1.o +obj-$(CONFIG_CPU_MIPS64) += c-r4k.o pg-r4k.o tlb-r4k.o tlb-glue-r4k.o + +# +# Debug TLB exception handler, currently unused +# +#obj-y += tlb-dbg-r4k.o + +obj-$(CONFIG_CPU_RM7000) += sc-rm7k.o +obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o +obj-$(CONFIG_SGI_IP22) += sc-ip22.o + +AFLAGS_tlb-glue-r4k.o := -P + +EXTRA_AFLAGS := $(CFLAGS) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/pg-r4k.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,708 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 98, 99, 2000, 01, 02, 03 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 Kanoj Sarcar (kanoj@sgi.com) + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Zero an entire page. Basically a simple unrolled loop should do the + * job but we want more performance by saving memory bus bandwidth. We + * have five flavours of the routine available for: + * + * - 16byte cachelines and no second level cache + * - 32byte cachelines second level cache + * - a version which handles the buggy R4600 v1.x + * - a version which handles the buggy R4600 v2.0 + * - Finally a last version without fancy cache games for the SC and MC + * versions of R4000 and R4400. + */ + +void r4k_clear_page_d16(void * page) +{ + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%2\n" + "1:\tcache\t%3,(%0)\n\t" + "sd\t$0,(%0)\n\t" + "sd\t$0,8(%0)\n\t" + "cache\t%3,16(%0)\n\t" + "sd\t$0,16(%0)\n\t" + "sd\t$0,24(%0)\n\t" + "daddiu\t%0,64\n\t" + "cache\t%3,-32(%0)\n\t" + "sd\t$0,-32(%0)\n\t" + "sd\t$0,-24(%0)\n\t" + "cache\t%3,-16(%0)\n\t" + "sd\t$0,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + "sd\t$0,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (page) + : "0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_D) + : "memory"); +} + +void r4k_clear_page_d32(void * page) +{ + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%2\n" + "1:\tcache\t%3,(%0)\n\t" + "sd\t$0,(%0)\n\t" + "sd\t$0,8(%0)\n\t" + "sd\t$0,16(%0)\n\t" + "sd\t$0,24(%0)\n\t" + "daddiu\t%0,64\n\t" + "cache\t%3,-32(%0)\n\t" + "sd\t$0,-32(%0)\n\t" + "sd\t$0,-24(%0)\n\t" + "sd\t$0,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + "sd\t$0,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (page) + : "0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_D) + : "memory"); +} + + +/* + * This flavour of r4k_clear_page is for the R4600 V1.x. Cite from the + * IDT R4600 V1.7 errata: + * + * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, + * Hit_Invalidate_D and Create_Dirty_Excl_D should only be + * executed if there is no other dcache activity. If the dcache is + * accessed for another instruction immeidately preceding when these + * cache instructions are executing, it is possible that the dcache + * tag match outputs used by these cache instructions will be + * incorrect. These cache instructions should be preceded by at least + * four instructions that are not any kind of load or store + * instruction. + * + * This is not allowed: lw + * nop + * nop + * nop + * cache Hit_Writeback_Invalidate_D + * + * This is allowed: lw + * nop + * nop + * nop + * nop + * cache Hit_Writeback_Invalidate_D + */ +void r4k_clear_page_r4600_v1(void * page) +{ + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%2\n" + "1:\tnop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "cache\t%3,(%0)\n\t" + "sd\t$0,(%0)\n\t" + "sd\t$0,8(%0)\n\t" + "sd\t$0,16(%0)\n\t" + "sd\t$0,24(%0)\n\t" + "daddiu\t%0,64\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "cache\t%3,-32(%0)\n\t" + "sd\t$0,-32(%0)\n\t" + "sd\t$0,-24(%0)\n\t" + "sd\t$0,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + "sd\t$0,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (page) + : "0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_D) + : "memory"); +} + +/* + * And this one is for the R4600 V2.0 + */ +void r4k_clear_page_r4600_v2(void * page) +{ + unsigned int flags; + + local_irq_save(flags); + *(volatile unsigned int *)KSEG1; + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%2\n" + "1:\tcache\t%3,(%0)\n\t" + "sd\t$0,(%0)\n\t" + "sd\t$0,8(%0)\n\t" + "sd\t$0,16(%0)\n\t" + "sd\t$0,24(%0)\n\t" + "daddiu\t%0,64\n\t" + "cache\t%3,-32(%0)\n\t" + "sd\t$0,-32(%0)\n\t" + "sd\t$0,-24(%0)\n\t" + "sd\t$0,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + "sd\t$0,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (page) + : "0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_D) + : "memory"); + local_irq_restore(flags); +} + +/* + * The next 4 versions are optimized for all possible scache configurations + * of the SC / MC versions of R4000 and R4400 ... + * + * Todo: For even better performance we should have a routine optimized for + * every legal combination of dcache / scache linesize. When I (Ralf) tried + * this the kernel crashed shortly after mounting the root filesystem. CPU + * bug? Weirdo cache instruction semantics? + */ +void r4k_clear_page_s16(void * page) +{ + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%2\n" + "1:\tcache\t%3,(%0)\n\t" + "sd\t$0,(%0)\n\t" + "sd\t$0,8(%0)\n\t" + "cache\t%3,16(%0)\n\t" + "sd\t$0,16(%0)\n\t" + "sd\t$0,24(%0)\n\t" + "daddiu\t%0,64\n\t" + "cache\t%3,-32(%0)\n\t" + "sd\t$0,-32(%0)\n\t" + "sd\t$0,-24(%0)\n\t" + "cache\t%3,-16(%0)\n\t" + "sd\t$0,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + "sd\t$0,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (page) + : "0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_SD) + : "memory"); +} + +void r4k_clear_page_s32(void * page) +{ + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%2\n" + "1:\tcache\t%3,(%0)\n\t" + "sd\t$0,(%0)\n\t" + "sd\t$0,8(%0)\n\t" + "sd\t$0,16(%0)\n\t" + "sd\t$0,24(%0)\n\t" + "daddiu\t%0,64\n\t" + "cache\t%3,-32(%0)\n\t" + "sd\t$0,-32(%0)\n\t" + "sd\t$0,-24(%0)\n\t" + "sd\t$0,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + "sd\t$0,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (page) + : "0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_SD) + : "memory"); +} + +void r4k_clear_page_s64(void * page) +{ + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%2\n" + "1:\tcache\t%3,(%0)\n\t" + "sd\t$0,(%0)\n\t" + "sd\t$0,8(%0)\n\t" + "sd\t$0,16(%0)\n\t" + "sd\t$0,24(%0)\n\t" + "daddiu\t%0,64\n\t" + "sd\t$0,-32(%0)\n\t" + "sd\t$0,-24(%0)\n\t" + "sd\t$0,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + "sd\t$0,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (page) + : "0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_SD) + : "memory"); +} + +void r4k_clear_page_s128(void * page) +{ + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%2\n" + "1:\tcache\t%3,(%0)\n\t" + "sd\t$0,(%0)\n\t" + "sd\t$0,8(%0)\n\t" + "sd\t$0,16(%0)\n\t" + "sd\t$0,24(%0)\n\t" + "sd\t$0,32(%0)\n\t" + "sd\t$0,40(%0)\n\t" + "sd\t$0,48(%0)\n\t" + "sd\t$0,56(%0)\n\t" + "daddiu\t%0,128\n\t" + "sd\t$0,-64(%0)\n\t" + "sd\t$0,-56(%0)\n\t" + "sd\t$0,-48(%0)\n\t" + "sd\t$0,-40(%0)\n\t" + "sd\t$0,-32(%0)\n\t" + "sd\t$0,-24(%0)\n\t" + "sd\t$0,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + "sd\t$0,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (page) + : "0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_SD) + : "memory"); +} + +/* + * This version has been tuned on an Origin. For other machines the arguments + * of the pref instructin may have to be tuned differently. + */ +void andes_clear_page(void * page) +{ + __asm__ __volatile__( + ".set\tpush\n\t" + ".set\tmips4\n\t" + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%2\n" + "1:\tpref 7,512(%0)\n\t" + "sd\t$0,(%0)\n\t" + "sd\t$0,8(%0)\n\t" + "sd\t$0,16(%0)\n\t" + "sd\t$0,24(%0)\n\t" + "daddiu\t%0,64\n\t" + "sd\t$0,-32(%0)\n\t" + "sd\t$0,-24(%0)\n\t" + "sd\t$0,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + "sd\t$0,-8(%0)\n\t" + ".set\tpop" + : "=r" (page) + : "0" (page), "I" (PAGE_SIZE) + : "memory"); +} + + +/* + * This is still inefficient. We only can do better if we know the + * virtual address where the copy will be accessed. + */ + +void r4k_copy_page_d16(void * to, void * from) +{ + unsigned long dummy1, dummy2, reg1, reg2; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%6\n" + "1:\tcache\t%7,(%0)\n\t" + "ld\t%2,(%1)\n\t" + "ld\t%3,8(%1)\n\t" + "sd\t%2,(%0)\n\t" + "sd\t%3,8(%0)\n\t" + "cache\t%7,16(%0)\n\t" + "ld\t%2,16(%1)\n\t" + "ld\t%3,24(%1)\n\t" + "sd\t%2,16(%0)\n\t" + "sd\t%3,24(%0)\n\t" + "cache\t%7,32(%0)\n\t" + "daddiu\t%0,64\n\t" + "daddiu\t%1,64\n\t" + "ld\t%2,-32(%1)\n\t" + "ld\t%3,-24(%1)\n\t" + "sd\t%2,-32(%0)\n\t" + "sd\t%3,-24(%0)\n\t" + "cache\t%7,-16(%0)\n\t" + "ld\t%2,-16(%1)\n\t" + "ld\t%3,-8(%1)\n\t" + "sd\t%2,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + " sd\t%3,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2) + :"0" (to), "1" (from), "I" (PAGE_SIZE), + "i" (Create_Dirty_Excl_D)); +} + +void r4k_copy_page_d32(void * to, void * from) +{ + unsigned long dummy1, dummy2, reg1, reg2; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%6\n" + "1:\tcache\t%7,(%0)\n\t" + "ld\t%2,(%1)\n\t" + "ld\t%3,8(%1)\n\t" + "sd\t%2,(%0)\n\t" + "sd\t%3,8(%0)\n\t" + "ld\t%2,16(%1)\n\t" + "ld\t%3,24(%1)\n\t" + "sd\t%2,16(%0)\n\t" + "sd\t%3,24(%0)\n\t" + "cache\t%7,32(%0)\n\t" + "daddiu\t%0,64\n\t" + "daddiu\t%1,64\n\t" + "ld\t%2,-32(%1)\n\t" + "ld\t%3,-24(%1)\n\t" + "sd\t%2,-32(%0)\n\t" + "sd\t%3,-24(%0)\n\t" + "ld\t%2,-16(%1)\n\t" + "ld\t%3,-8(%1)\n\t" + "sd\t%2,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + " sd\t%3,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2) + :"0" (to), "1" (from), "I" (PAGE_SIZE), + "i" (Create_Dirty_Excl_D)); +} + +/* + * Again a special version for the R4600 V1.x + */ +void r4k_copy_page_r4600_v1(void * to, void * from) +{ + unsigned long dummy1, dummy2, reg1, reg2; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%6\n" + "1:\tnop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "\tcache\t%7,(%0)\n\t" + "ld\t%2,(%1)\n\t" + "ld\t%3,8(%1)\n\t" + "sd\t%2,(%0)\n\t" + "sd\t%3,8(%0)\n\t" + "ld\t%2,16(%1)\n\t" + "ld\t%3,24(%1)\n\t" + "sd\t%2,16(%0)\n\t" + "sd\t%3,24(%0)\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "cache\t%7,32(%0)\n\t" + "daddiu\t%0,64\n\t" + "daddiu\t%1,64\n\t" + "ld\t%2,-32(%1)\n\t" + "ld\t%3,-24(%1)\n\t" + "sd\t%2,-32(%0)\n\t" + "sd\t%3,-24(%0)\n\t" + "ld\t%2,-16(%1)\n\t" + "ld\t%3,-8(%1)\n\t" + "sd\t%2,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + " sd\t%3,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2) + :"0" (to), "1" (from), "I" (PAGE_SIZE), + "i" (Create_Dirty_Excl_D)); +} + +void r4k_copy_page_r4600_v2(void * to, void * from) +{ + unsigned long dummy1, dummy2, reg1, reg2; + unsigned int flags; + + local_irq_save(flags); + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%6\n" + "1:\tnop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "\tcache\t%7,(%0)\n\t" + "ld\t%2,(%1)\n\t" + "ld\t%3,8(%1)\n\t" + "sd\t%2,(%0)\n\t" + "sd\t%3,8(%0)\n\t" + "ld\t%2,16(%1)\n\t" + "ld\t%3,24(%1)\n\t" + "sd\t%2,16(%0)\n\t" + "sd\t%3,24(%0)\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "cache\t%7,32(%0)\n\t" + "daddiu\t%0,64\n\t" + "daddiu\t%1,64\n\t" + "ld\t%2,-32(%1)\n\t" + "ld\t%3,-24(%1)\n\t" + "sd\t%2,-32(%0)\n\t" + "sd\t%3,-24(%0)\n\t" + "ld\t%2,-16(%1)\n\t" + "ld\t%3,-8(%1)\n\t" + "sd\t%2,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + " sd\t%3,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2) + :"0" (to), "1" (from), "I" (PAGE_SIZE), + "i" (Create_Dirty_Excl_D)); + local_irq_restore(flags); +} + +/* + * These are for R4000SC / R4400MC + */ +void r4k_copy_page_s16(void * to, void * from) +{ + unsigned long dummy1, dummy2, reg1, reg2; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%6\n" + "1:\tcache\t%7,(%0)\n\t" + "ld\t%2,(%1)\n\t" + "ld\t%3,8(%1)\n\t" + "sd\t%2,(%0)\n\t" + "sd\t%3,8(%0)\n\t" + "cache\t%7,16(%0)\n\t" + "ld\t%2,16(%1)\n\t" + "ld\t%3,24(%1)\n\t" + "sd\t%2,16(%0)\n\t" + "sd\t%3,24(%0)\n\t" + "cache\t%7,32(%0)\n\t" + "daddiu\t%0,64\n\t" + "daddiu\t%1,64\n\t" + "ld\t%2,-32(%1)\n\t" + "ld\t%3,-24(%1)\n\t" + "sd\t%2,-32(%0)\n\t" + "sd\t%3,-24(%0)\n\t" + "cache\t%7,-16(%0)\n\t" + "ld\t%2,-16(%1)\n\t" + "ld\t%3,-8(%1)\n\t" + "sd\t%2,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + " sd\t%3,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2) + :"0" (to), "1" (from), "I" (PAGE_SIZE), + "i" (Create_Dirty_Excl_SD)); +} + +void r4k_copy_page_s32(void * to, void * from) +{ + unsigned long dummy1, dummy2, reg1, reg2; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%6\n" + "1:\tcache\t%7,(%0)\n\t" + "ld\t%2,(%1)\n\t" + "ld\t%3,8(%1)\n\t" + "sd\t%2,(%0)\n\t" + "sd\t%3,8(%0)\n\t" + "ld\t%2,16(%1)\n\t" + "ld\t%3,24(%1)\n\t" + "sd\t%2,16(%0)\n\t" + "sd\t%3,24(%0)\n\t" + "cache\t%7,32(%0)\n\t" + "daddiu\t%0,64\n\t" + "daddiu\t%1,64\n\t" + "ld\t%2,-32(%1)\n\t" + "ld\t%3,-24(%1)\n\t" + "sd\t%2,-32(%0)\n\t" + "sd\t%3,-24(%0)\n\t" + "ld\t%2,-16(%1)\n\t" + "ld\t%3,-8(%1)\n\t" + "sd\t%2,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + " sd\t%3,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2) + :"0" (to), "1" (from), "I" (PAGE_SIZE), + "i" (Create_Dirty_Excl_SD)); +} + +void r4k_copy_page_s64(void * to, void * from) +{ + unsigned long dummy1, dummy2, reg1, reg2; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%6\n" + "1:\tcache\t%7,(%0)\n\t" + "ld\t%2,(%1)\n\t" + "ld\t%3,8(%1)\n\t" + "sd\t%2,(%0)\n\t" + "sd\t%3,8(%0)\n\t" + "ld\t%2,16(%1)\n\t" + "ld\t%3,24(%1)\n\t" + "sd\t%2,16(%0)\n\t" + "sd\t%3,24(%0)\n\t" + "daddiu\t%0,64\n\t" + "daddiu\t%1,64\n\t" + "ld\t%2,-32(%1)\n\t" + "ld\t%3,-24(%1)\n\t" + "sd\t%2,-32(%0)\n\t" + "sd\t%3,-24(%0)\n\t" + "ld\t%2,-16(%1)\n\t" + "ld\t%3,-8(%1)\n\t" + "sd\t%2,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + " sd\t%3,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2) + :"0" (to), "1" (from), "I" (PAGE_SIZE), + "i" (Create_Dirty_Excl_SD)); +} + +void r4k_copy_page_s128(void * to, void * from) +{ + unsigned long dummy1, dummy2; + unsigned long reg1, reg2, reg3, reg4; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%8\n" + "1:\tcache\t%9,(%0)\n\t" + "ld\t%2,(%1)\n\t" + "ld\t%3,8(%1)\n\t" + "ld\t%4,16(%1)\n\t" + "ld\t%5,24(%1)\n\t" + "sd\t%2,(%0)\n\t" + "sd\t%3,8(%0)\n\t" + "sd\t%4,16(%0)\n\t" + "sd\t%5,24(%0)\n\t" + "ld\t%2,32(%1)\n\t" + "ld\t%3,40(%1)\n\t" + "ld\t%4,48(%1)\n\t" + "ld\t%5,56(%1)\n\t" + "sd\t%2,32(%0)\n\t" + "sd\t%3,40(%0)\n\t" + "sd\t%4,48(%0)\n\t" + "sd\t%5,56(%0)\n\t" + "daddiu\t%0,128\n\t" + "daddiu\t%1,128\n\t" + "ld\t%2,-64(%1)\n\t" + "ld\t%3,-56(%1)\n\t" + "ld\t%4,-48(%1)\n\t" + "ld\t%5,-40(%1)\n\t" + "sd\t%2,-64(%0)\n\t" + "sd\t%3,-56(%0)\n\t" + "sd\t%4,-48(%0)\n\t" + "sd\t%5,-40(%0)\n\t" + "ld\t%2,-32(%1)\n\t" + "ld\t%3,-24(%1)\n\t" + "ld\t%4,-16(%1)\n\t" + "ld\t%5,-8(%1)\n\t" + "sd\t%2,-32(%0)\n\t" + "sd\t%3,-24(%0)\n\t" + "sd\t%4,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + " sd\t%5,-8(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=r" (dummy1), "=r" (dummy2), + "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) + :"0" (to), "1" (from), + "I" (PAGE_SIZE), + "i" (Create_Dirty_Excl_SD)); +} + +/* + * This version has been tuned on an Origin. For other machines the arguments + * of the pref instructin may have to be tuned differently. + */ +void andes_copy_page(void * to, void * from) +{ + unsigned long dummy1, dummy2, reg1, reg2, reg3, reg4; + + __asm__ __volatile__( + ".set\tpush\n\t" + ".set\tmips4\n\t" + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "daddiu\t$1,%0,%8\n" + "1:\tpref\t0,2*128(%1)\n\t" + "pref\t1,2*128(%0)\n\t" + "ld\t%2,(%1)\n\t" + "ld\t%3,8(%1)\n\t" + "ld\t%4,16(%1)\n\t" + "ld\t%5,24(%1)\n\t" + "sd\t%2,(%0)\n\t" + "sd\t%3,8(%0)\n\t" + "sd\t%4,16(%0)\n\t" + "sd\t%5,24(%0)\n\t" + "daddiu\t%0,64\n\t" + "daddiu\t%1,64\n\t" + "ld\t%2,-32(%1)\n\t" + "ld\t%3,-24(%1)\n\t" + "ld\t%4,-16(%1)\n\t" + "ld\t%5,-8(%1)\n\t" + "sd\t%2,-32(%0)\n\t" + "sd\t%3,-24(%0)\n\t" + "sd\t%4,-16(%0)\n\t" + "bne\t$1,%0,1b\n\t" + " sd\t%5,-8(%0)\n\t" + ".set\tpop\n\t" + :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2), + "=&r" (reg3), "=&r" (reg4) + :"0" (to), "1" (from), "I" (PAGE_SIZE)); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/pg-sb1.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,131 @@ +/* + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 2000 Sibyte + * + * Written by Justin Carlson (carlson@sibyte.com) + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include +#include + +#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS +#define SB1_PREF_LOAD_STREAMED_HINT "0" +#define SB1_PREF_STORE_STREAMED_HINT "1" +#else +#define SB1_PREF_LOAD_STREAMED_HINT "4" +#define SB1_PREF_STORE_STREAMED_HINT "5" +#endif + +/* These are the functions hooked by the memory management function pointers */ +void sb1_clear_page(void *page) +{ + /* + * JDCXXX - This should be bottlenecked by the write buffer, but these + * things tend to be mildly unpredictable...should check this on the + * performance model + * + * We prefetch 4 lines ahead. We're also "cheating" slightly here... + * since we know we're on an SB1, we force the assembler to take + * 64-bit operands to speed things up + */ + __asm__ __volatile__( + ".set push \n" + ".set noreorder \n" + ".set noat \n" + ".set mips4 \n" + " daddiu $1, %0, %2 \n" /* Calculate the end of the page to clear */ +#ifdef CONFIG_CPU_HAS_PREFETCH + " pref " SB1_PREF_STORE_STREAMED_HINT ", 0(%0) \n" /* Prefetch the first 4 lines */ + " pref " SB1_PREF_STORE_STREAMED_HINT ", 32(%0) \n" + " pref " SB1_PREF_STORE_STREAMED_HINT ", 64(%0) \n" + " pref " SB1_PREF_STORE_STREAMED_HINT ", 96(%0) \n" +#endif + "1: sd $0, 0(%0) \n" /* Throw out a cacheline of 0's */ + " sd $0, 8(%0) \n" + " sd $0, 16(%0) \n" + " sd $0, 24(%0) \n" +#ifdef CONFIG_CPU_HAS_PREFETCH + " pref " SB1_PREF_STORE_STREAMED_HINT ",128(%0) \n" /* Prefetch 4 lines ahead */ +#endif + " bne $1, %0, 1b \n" + " daddiu %0, %0, 32\n" /* Next cacheline (This instruction better be short piped!) */ + ".set pop \n" + : "=r" (page) + : "0" (page), "I" (PAGE_SIZE-32) + : "memory"); + +} + +void sb1_copy_page(void *to, void *from) +{ + /* + * This should be optimized in assembly...can't use ld/sd, though, + * because the top 32 bits could be nuked if we took an interrupt + * during the routine. And this is not a good place to be cli()'ing + * + * The pref's used here are using "streaming" hints, which cause the + * copied data to be kicked out of the cache sooner. A page copy often + * ends up copying a lot more data than is commonly used, so this seems + * to make sense in terms of reducing cache pollution, but I've no real + * performance data to back this up + */ + + __asm__ __volatile__( + ".set push \n" + ".set noreorder \n" + ".set noat \n" + ".set mips4 \n" + " daddiu $1, %0, %4 \n" /* Calculate the end of the page to copy */ +#ifdef CONFIG_CPU_HAS_PREFETCH + " pref " SB1_PREF_LOAD_STREAMED_HINT ", 0(%0) \n" /* Prefetch the first 3 lines */ + " pref " SB1_PREF_STORE_STREAMED_HINT ", 0(%1) \n" + " pref " SB1_PREF_LOAD_STREAMED_HINT ", 32(%0) \n" + " pref " SB1_PREF_STORE_STREAMED_HINT ", 32(%1) \n" + " pref " SB1_PREF_LOAD_STREAMED_HINT ", 64(%0) \n" + " pref " SB1_PREF_STORE_STREAMED_HINT ", 64(%1) \n" +#endif + "1: lw $2, 0(%0) \n" /* Block copy a cacheline */ + " lw $3, 4(%0) \n" + " lw $4, 8(%0) \n" + " lw $5, 12(%0) \n" + " lw $6, 16(%0) \n" + " lw $7, 20(%0) \n" + " lw $8, 24(%0) \n" + " lw $9, 28(%0) \n" +#ifdef CONFIG_CPU_HAS_PREFETCH + " pref " SB1_PREF_LOAD_STREAMED_HINT ", 96(%0) \n" /* Prefetch ahead */ + " pref " SB1_PREF_STORE_STREAMED_HINT ", 96(%1) \n" +#endif + " sw $2, 0(%1) \n" + " sw $3, 4(%1) \n" + " sw $4, 8(%1) \n" + " sw $5, 12(%1) \n" + " sw $6, 16(%1) \n" + " sw $7, 20(%1) \n" + " sw $8, 24(%1) \n" + " sw $9, 28(%1) \n" + " daddiu %1, %1, 32 \n" /* Next cacheline */ + " nop \n" /* Force next add to short pipe */ + " nop \n" /* Force next add to short pipe */ + " bne $1, %0, 1b \n" + " daddiu %0, %0, 32 \n" /* Next cacheline */ + ".set pop \n" + : "=r" (to), "=r" (from) + : "0" (from), "1" (to), "I" (PAGE_SIZE-32) + : "$2","$3","$4","$5","$6","$7","$8","$9","memory"); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/pgtable.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,33 @@ +#include +#include +#include + +void show_mem(void) +{ + int pfn, total = 0, reserved = 0; + int shared = 0, cached = 0; + int highmem = 0; + struct page *page; + + printk("Mem-info:\n"); + show_free_areas(); + printk("Free swap: %6dkB\n",nr_swap_pages<<(PAGE_SHIFT-10)); + pfn = max_mapnr; + while (pfn-- > 0) { + page = pfn_to_page(pfn); + total++; + if (PageHighMem(page)) + highmem++; + if (PageReserved(page)) + reserved++; + else if (PageSwapCache(page)) + cached++; + else if (page_count(page)) + shared += page_count(page) - 1; + } + printk("%d pages of RAM\n", total); + printk("%d pages of HIGHMEM\n",highmem); + printk("%d reserved pages\n",reserved); + printk("%d pages shared\n",shared); + printk("%d pages swap cached\n",cached); +} --- linux-2.5.73/arch/mips64/mm/r4xx0.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,2414 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * r4xx0.c: R4000 processor variant specific MMU/Cache routines. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997, 1998, 1999, 2000, 2001 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -/* CP0 hazard avoidance. */ -#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ - "nop; nop; nop; nop; nop; nop;\n\t" \ - ".set reorder\n\t") - -/* Primary cache parameters. */ -static int icache_size, dcache_size; /* Size in bytes */ -static int ic_lsize, dc_lsize; /* LineSize in bytes */ - -/* Secondary cache (if present) parameters. */ -static unsigned int scache_size, sc_lsize; /* Again, in bytes */ - -#include -#include - -#undef DEBUG_CACHE - -/* - * Dummy cache handling routines for machines without boardcaches - */ -static void no_sc_noop(void) {} - -static struct bcache_ops no_sc_ops = { - (void *)no_sc_noop, (void *)no_sc_noop, - (void *)no_sc_noop, (void *)no_sc_noop -}; - -struct bcache_ops *bcops = &no_sc_ops; - -/* - * On processors with QED R4600 style two set assosicative cache - * this is the bit which selects the way in the cache for the - * indexed cachops. - */ -#define icache_waybit (icache_size >> 1) -#define dcache_waybit (dcache_size >> 1) - -/* - * Zero an entire page. Basically a simple unrolled loop should do the - * job but we want more performance by saving memory bus bandwidth. We - * have five flavours of the routine available for: - * - * - 16byte cachelines and no second level cache - * - 32byte cachelines second level cache - * - a version which handles the buggy R4600 v1.x - * - a version which handles the buggy R4600 v2.0 - * - Finally a last version without fancy cache games for the SC and MC - * versions of R4000 and R4400. - */ - -static void r4k_clear_page_d16(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "cache\t%3,16(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "cache\t%3,-32(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "cache\t%3,-16(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_D) - :"$1", "memory"); -} - -static void r4k_clear_page_d32(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "cache\t%3,-32(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_D) - :"$1", "memory"); -} - - -/* - * This flavour of r4k_clear_page is for the R4600 V1.x. Cite from the - * IDT R4600 V1.7 errata: - * - * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, - * Hit_Invalidate_D and Create_Dirty_Excl_D should only be - * executed if there is no other dcache activity. If the dcache is - * accessed for another instruction immeidately preceding when these - * cache instructions are executing, it is possible that the dcache - * tag match outputs used by these cache instructions will be - * incorrect. These cache instructions should be preceded by at least - * four instructions that are not any kind of load or store - * instruction. - * - * This is not allowed: lw - * nop - * nop - * nop - * cache Hit_Writeback_Invalidate_D - * - * This is allowed: lw - * nop - * nop - * nop - * nop - * cache Hit_Writeback_Invalidate_D - */ -static void r4k_clear_page_r4600_v1(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tnop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "cache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "cache\t%3,-32(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D) - :"$1", "memory"); -} - -/* - * And this one is for the R4600 V2.0 - */ -static void r4k_clear_page_r4600_v2(void * page) -{ - unsigned int flags; - - local_irq_save(flags); - *(volatile unsigned int *)KSEG1; - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "cache\t%3,-32(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_D) - :"$1", "memory"); - local_irq_restore(flags); -} - -/* - * The next 4 versions are optimized for all possible scache configurations - * of the SC / MC versions of R4000 and R4400 ... - * - * Todo: For even better performance we should have a routine optimized for - * every legal combination of dcache / scache linesize. When I (Ralf) tried - * this the kernel crashed shortly after mounting the root filesystem. CPU - * bug? Weirdo cache instruction semantics? - */ -static void r4k_clear_page_s16(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "cache\t%3,16(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "cache\t%3,-32(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "cache\t%3,-16(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_SD) - :"$1","memory"); -} - -static void r4k_clear_page_s32(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "cache\t%3,-32(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_SD) - :"$1","memory"); -} - -static void r4k_clear_page_s64(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_SD) - :"$1","memory"); -} - -static void r4k_clear_page_s128(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "sd\t$0,32(%0)\n\t" - "sd\t$0,40(%0)\n\t" - "sd\t$0,48(%0)\n\t" - "sd\t$0,56(%0)\n\t" - "daddiu\t%0,128\n\t" - "sd\t$0,-64(%0)\n\t" - "sd\t$0,-56(%0)\n\t" - "sd\t$0,-48(%0)\n\t" - "sd\t$0,-40(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_SD) - :"$1", "memory"); -} - - -/* - * This is still inefficient. We only can do better if we know the - * virtual address where the copy will be accessed. - */ - -static void r4k_copy_page_d16(void * to, void * from) -{ - unsigned long dummy1, dummy2, reg1, reg2; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%6\n" - "1:\tcache\t%7,(%0)\n\t" - "ld\t%2,(%1)\n\t" - "ld\t%3,8(%1)\n\t" - "sd\t%2,(%0)\n\t" - "sd\t%3,8(%0)\n\t" - "cache\t%7,16(%0)\n\t" - "ld\t%2,16(%1)\n\t" - "ld\t%3,24(%1)\n\t" - "sd\t%2,16(%0)\n\t" - "sd\t%3,24(%0)\n\t" - "cache\t%7,32(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "ld\t%2,-32(%1)\n\t" - "ld\t%3,-24(%1)\n\t" - "sd\t%2,-32(%0)\n\t" - "sd\t%3,-24(%0)\n\t" - "cache\t%7,-16(%0)\n\t" - "ld\t%2,-16(%1)\n\t" - "ld\t%3,-8(%1)\n\t" - "sd\t%2,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - " sd\t%3,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2) - :"0" (to), "1" (from), "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D)); -} - -static void r4k_copy_page_d32(void * to, void * from) -{ - unsigned long dummy1, dummy2, reg1, reg2; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%6\n" - "1:\tcache\t%7,(%0)\n\t" - "ld\t%2,(%1)\n\t" - "ld\t%3,8(%1)\n\t" - "sd\t%2,(%0)\n\t" - "sd\t%3,8(%0)\n\t" - "ld\t%2,16(%1)\n\t" - "ld\t%3,24(%1)\n\t" - "sd\t%2,16(%0)\n\t" - "sd\t%3,24(%0)\n\t" - "cache\t%7,32(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "ld\t%2,-32(%1)\n\t" - "ld\t%3,-24(%1)\n\t" - "sd\t%2,-32(%0)\n\t" - "sd\t%3,-24(%0)\n\t" - "ld\t%2,-16(%1)\n\t" - "ld\t%3,-8(%1)\n\t" - "sd\t%2,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - " sd\t%3,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2) - :"0" (to), "1" (from), "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D)); -} - -/* - * Again a special version for the R4600 V1.x - */ -static void r4k_copy_page_r4600_v1(void * to, void * from) -{ - unsigned long dummy1, dummy2, reg1, reg2; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%6\n" - "1:\tnop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "\tcache\t%7,(%0)\n\t" - "ld\t%2,(%1)\n\t" - "ld\t%3,8(%1)\n\t" - "sd\t%2,(%0)\n\t" - "sd\t%3,8(%0)\n\t" - "ld\t%2,16(%1)\n\t" - "ld\t%3,24(%1)\n\t" - "sd\t%2,16(%0)\n\t" - "sd\t%3,24(%0)\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "cache\t%7,32(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "ld\t%2,-32(%1)\n\t" - "ld\t%3,-24(%1)\n\t" - "sd\t%2,-32(%0)\n\t" - "sd\t%3,-24(%0)\n\t" - "ld\t%2,-16(%1)\n\t" - "ld\t%3,-8(%1)\n\t" - "sd\t%2,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - " sd\t%3,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2) - :"0" (to), "1" (from), "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D)); -} - -static void r4k_copy_page_r4600_v2(void * to, void * from) -{ - unsigned long dummy1, dummy2, reg1, reg2; - unsigned int flags; - - local_irq_save(flags); - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%6\n" - "1:\tnop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "\tcache\t%7,(%0)\n\t" - "ld\t%2,(%1)\n\t" - "ld\t%3,8(%1)\n\t" - "sd\t%2,(%0)\n\t" - "sd\t%3,8(%0)\n\t" - "ld\t%2,16(%1)\n\t" - "ld\t%3,24(%1)\n\t" - "sd\t%2,16(%0)\n\t" - "sd\t%3,24(%0)\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "cache\t%7,32(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "ld\t%2,-32(%1)\n\t" - "ld\t%3,-24(%1)\n\t" - "sd\t%2,-32(%0)\n\t" - "sd\t%3,-24(%0)\n\t" - "ld\t%2,-16(%1)\n\t" - "ld\t%3,-8(%1)\n\t" - "sd\t%2,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - " sd\t%3,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2) - :"0" (to), "1" (from), "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D)); - local_irq_restore(flags); -} - -/* - * These are for R4000SC / R4400MC - */ -static void r4k_copy_page_s16(void * to, void * from) -{ - unsigned long dummy1, dummy2, reg1, reg2; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%6\n" - "1:\tcache\t%7,(%0)\n\t" - "ld\t%2,(%1)\n\t" - "ld\t%3,8(%1)\n\t" - "sd\t%2,(%0)\n\t" - "sd\t%3,8(%0)\n\t" - "cache\t%7,16(%0)\n\t" - "ld\t%2,16(%1)\n\t" - "ld\t%3,24(%1)\n\t" - "sd\t%2,16(%0)\n\t" - "sd\t%3,24(%0)\n\t" - "cache\t%7,32(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "ld\t%2,-32(%1)\n\t" - "ld\t%3,-24(%1)\n\t" - "sd\t%2,-32(%0)\n\t" - "sd\t%3,-24(%0)\n\t" - "cache\t%7,-16(%0)\n\t" - "ld\t%2,-16(%1)\n\t" - "ld\t%3,-8(%1)\n\t" - "sd\t%2,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - " sd\t%3,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2) - :"0" (to), "1" (from), "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_SD)); -} - -static void r4k_copy_page_s32(void * to, void * from) -{ - unsigned long dummy1, dummy2, reg1, reg2; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%6\n" - "1:\tcache\t%7,(%0)\n\t" - "ld\t%2,(%1)\n\t" - "ld\t%3,8(%1)\n\t" - "sd\t%2,(%0)\n\t" - "sd\t%3,8(%0)\n\t" - "ld\t%2,16(%1)\n\t" - "ld\t%3,24(%1)\n\t" - "sd\t%2,16(%0)\n\t" - "sd\t%3,24(%0)\n\t" - "cache\t%7,32(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "ld\t%2,-32(%1)\n\t" - "ld\t%3,-24(%1)\n\t" - "sd\t%2,-32(%0)\n\t" - "sd\t%3,-24(%0)\n\t" - "ld\t%2,-16(%1)\n\t" - "ld\t%3,-8(%1)\n\t" - "sd\t%2,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - " sd\t%3,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2) - :"0" (to), "1" (from), "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_SD)); -} - -static void r4k_copy_page_s64(void * to, void * from) -{ - unsigned long dummy1, dummy2, reg1, reg2; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%6\n" - "1:\tcache\t%7,(%0)\n\t" - "ld\t%2,(%1)\n\t" - "ld\t%3,8(%1)\n\t" - "sd\t%2,(%0)\n\t" - "sd\t%3,8(%0)\n\t" - "ld\t%2,16(%1)\n\t" - "ld\t%3,24(%1)\n\t" - "sd\t%2,16(%0)\n\t" - "sd\t%3,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "ld\t%2,-32(%1)\n\t" - "ld\t%3,-24(%1)\n\t" - "sd\t%2,-32(%0)\n\t" - "sd\t%3,-24(%0)\n\t" - "ld\t%2,-16(%1)\n\t" - "ld\t%3,-8(%1)\n\t" - "sd\t%2,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - " sd\t%3,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), "=&r" (reg1), "=&r" (reg2) - :"0" (to), "1" (from), "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_SD)); -} - -static void r4k_copy_page_s128(void * to, void * from) -{ - unsigned long dummy1, dummy2; - unsigned long reg1, reg2, reg3, reg4; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "daddiu\t$1,%0,%8\n" - "1:\tcache\t%9,(%0)\n\t" - "ld\t%2,(%1)\n\t" - "ld\t%3,8(%1)\n\t" - "ld\t%4,16(%1)\n\t" - "ld\t%5,24(%1)\n\t" - "sd\t%2,(%0)\n\t" - "sd\t%3,8(%0)\n\t" - "sd\t%4,16(%0)\n\t" - "sd\t%5,24(%0)\n\t" - "ld\t%2,32(%1)\n\t" - "ld\t%3,40(%1)\n\t" - "ld\t%4,48(%1)\n\t" - "ld\t%5,56(%1)\n\t" - "sd\t%2,32(%0)\n\t" - "sd\t%3,40(%0)\n\t" - "sd\t%4,48(%0)\n\t" - "sd\t%5,56(%0)\n\t" - "daddiu\t%0,128\n\t" - "daddiu\t%1,128\n\t" - "ld\t%2,-64(%1)\n\t" - "ld\t%3,-56(%1)\n\t" - "ld\t%4,-48(%1)\n\t" - "ld\t%5,-40(%1)\n\t" - "sd\t%2,-64(%0)\n\t" - "sd\t%3,-56(%0)\n\t" - "sd\t%4,-48(%0)\n\t" - "sd\t%5,-40(%0)\n\t" - "ld\t%2,-32(%1)\n\t" - "ld\t%3,-24(%1)\n\t" - "ld\t%4,-16(%1)\n\t" - "ld\t%5,-8(%1)\n\t" - "sd\t%2,-32(%0)\n\t" - "sd\t%3,-24(%0)\n\t" - "sd\t%4,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - " sd\t%5,-8(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), - "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) - :"0" (to), "1" (from), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_SD)); -} - - -/* - * If you think for one second that this stuff coming up is a lot - * of bulky code eating too many kernel cache lines. Think _again_. - * - * Consider: - * 1) Taken branches have a 3 cycle penalty on R4k - * 2) The branch itself is a real dead cycle on even R4600/R5000. - * 3) Only one of the following variants of each type is even used by - * the kernel based upon the cache parameters we detect at boot time. - * - * QED. - */ - -static inline void r4k_flush_cache_all_s16d16i16(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache16(); blast_icache16(); blast_scache16(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_s32d16i16(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache16(); blast_icache16(); blast_scache32(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_s64d16i16(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache16(); blast_icache16(); blast_scache64(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_s128d16i16(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache16(); blast_icache16(); blast_scache128(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_s32d32i32(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache32(); blast_icache32(); blast_scache32(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_s64d32i32(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache32(); blast_icache32(); blast_scache64(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_s128d32i32(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache32(); blast_icache32(); blast_scache128(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_d16i16(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache16(); blast_icache16(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_d32i32(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache32(); blast_icache32(); - local_irq_restore(flags); -} - -static void r4k_flush_cache_range_s16d16i16(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (vma) { - if (CPU_CONTEXT(smp_processor_id(), mm) != - CPU_CONTEXT(smp_processor_id(), current->mm)) { - r4k_flush_cache_all_s16d16i16(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache16_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void r4k_flush_cache_range_s32d16i16(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (vma) { - if (CPU_CONTEXT(smp_processor_id(), mm) != - CPU_CONTEXT(smp_processor_id(), current->mm)) { - r4k_flush_cache_all_s32d16i16(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache32_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void r4k_flush_cache_range_s64d16i16(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (vma) { - if (CPU_CONTEXT(smp_processor_id(), mm) != - CPU_CONTEXT(smp_processor_id(), current->mm)) { - r4k_flush_cache_all_s64d16i16(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache64_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void r4k_flush_cache_range_s128d16i16(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (vma) { - if (CPU_CONTEXT(smp_processor_id(), mm) != - CPU_CONTEXT(smp_processor_id(), current->mm)) { - r4k_flush_cache_all_s128d16i16(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache128_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void r4k_flush_cache_range_s32d32i32(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (vma) { - if (CPU_CONTEXT(smp_processor_id(), mm) != - CPU_CONTEXT(smp_processor_id(), current->mm)) { - r4k_flush_cache_all_s32d32i32(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache32_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void r4k_flush_cache_range_s64d32i32(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (vma) { - if (CPU_CONTEXT(smp_processor_id(), mm) != - CPU_CONTEXT(smp_processor_id(), current->mm)) { - r4k_flush_cache_all_s64d32i32(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache64_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void r4k_flush_cache_range_s128d32i32(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (vma) { - if (CPU_CONTEXT(smp_processor_id(), mm) != - CPU_CONTEXT(smp_processor_id(), current->mm)) { - r4k_flush_cache_all_s128d32i32(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache128_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void r4k_flush_cache_range_d16i16(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { - unsigned long flags; - -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - local_irq_save(flags); - blast_dcache16(); blast_icache16(); - local_irq_restore(flags); - } -} - -static void r4k_flush_cache_range_d32i32(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { - unsigned long flags; - -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - local_irq_save(flags); - blast_dcache32(); blast_icache32(); - local_irq_restore(flags); - } -} - -/* - * On architectures like the Sparc, we could get rid of lines in - * the cache created only by a certain context, but on the MIPS - * (and actually certain Sparc's) we cannot. - */ -static void r4k_flush_cache_mm_s16d16i16(struct mm_struct *mm) -{ - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_s16d16i16(); - } -} - -static void r4k_flush_cache_mm_s32d16i16(struct mm_struct *mm) -{ - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_s32d16i16(); - } -} - -static void r4k_flush_cache_mm_s64d16i16(struct mm_struct *mm) -{ - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_s64d16i16(); - } -} - -static void r4k_flush_cache_mm_s128d16i16(struct mm_struct *mm) -{ - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_s128d16i16(); - } -} - -static void r4k_flush_cache_mm_s32d32i32(struct mm_struct *mm) -{ - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_s32d32i32(); - } -} - -static void r4k_flush_cache_mm_s64d32i32(struct mm_struct *mm) -{ - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_s64d32i32(); - } -} - -static void r4k_flush_cache_mm_s128d32i32(struct mm_struct *mm) -{ - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_s128d32i32(); - } -} - -static void r4k_flush_cache_mm_d16i16(struct mm_struct *mm) -{ - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_d16i16(); - } -} - -static void r4k_flush_cache_mm_d32i32(struct mm_struct *mm) -{ - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_d32i32(); - } -} - -static void r4k_flush_cache_page_s16d16i16(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if(!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) != - CPU_CONTEXT(smp_processor_id(), current->mm)) { - /* Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache16_page_indexed(page); - blast_scache16_page_indexed(page); - } else - blast_scache16_page(page); -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_s32d16i16(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if(!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) != - CPU_CONTEXT(smp_processor_id(), current->mm)) { - /* Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache16_page_indexed(page); - blast_scache32_page_indexed(page); - } else - blast_scache32_page(page); -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_s64d16i16(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if(!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) != - CPU_CONTEXT(smp_processor_id(), current->mm)) { - /* Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache16_page_indexed(page); - blast_scache64_page_indexed(page); - } else - blast_scache64_page(page); -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_s128d16i16(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if(!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) != - CPU_CONTEXT(smp_processor_id(), current->mm)) { - /* - * Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache16_page_indexed(page); - blast_scache128_page_indexed(page); - } else - blast_scache128_page(page); -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_s32d32i32(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if(!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) != - CPU_CONTEXT(smp_processor_id(), current->mm)) { - /* - * Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache32_page_indexed(page); - blast_scache32_page_indexed(page); - } else - blast_scache32_page(page); -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_s64d32i32(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if(!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) != - CPU_CONTEXT(smp_processor_id(), current->mm)) { - /* - * Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache32_page_indexed(page); - blast_scache64_page_indexed(page); - } else - blast_scache64_page(page); -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_s128d32i32(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if(!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) != - CPU_CONTEXT(smp_processor_id(), current->mm)) { - /* Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache32_page_indexed(page); - blast_scache128_page_indexed(page); - } else - blast_scache128_page(page); -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_d16i16(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if(!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if(mm == current->mm) { - blast_dcache16_page(page); - } else { - /* Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (dcache_size - 1))); - blast_dcache16_page_indexed(page); - } -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_d32i32(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if(!(pte_val(*ptep) & _PAGE_PRESENT)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if((mm == current->mm) && (pte_val(*ptep) & _PAGE_VALID)) { - blast_dcache32_page(page); - } else { - /* - * Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (dcache_size - 1))); - blast_dcache32_page_indexed(page); - } -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_d32i32_r4600(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (CPU_CONTEXT(smp_processor_id(), mm) == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if(!(pte_val(*ptep) & _PAGE_PRESENT)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if((mm == current->mm) && (pte_val(*ptep) & _PAGE_VALID)) { - blast_dcache32_page(page); - } else { - /* Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (dcache_size - 1))); - blast_dcache32_page_indexed(page); - blast_dcache32_page_indexed(page ^ dcache_waybit); - } -out: - local_irq_restore(flags); -} - -static void r4k_flush_page_to_ram_s16(struct page *page) -{ - blast_scache16_page((unsigned long)page_address(page)); -} - -static void r4k_flush_page_to_ram_s32(struct page *page) -{ - blast_scache32_page((unsigned long)page_address(page)); -} - -static void r4k_flush_page_to_ram_s64(struct page *page) -{ - blast_scache64_page((unsigned long)page_address(page)); -} - -static void r4k_flush_page_to_ram_s128(struct page *page) -{ - blast_scache128_page((unsigned long)page_address(page)); -} - -static void r4k_flush_page_to_ram_d16(struct page *page) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache16_page((unsigned long)page_address(page)); - local_irq_restore(flags); -} - -static void r4k_flush_page_to_ram_d32(struct page *page) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache32_page((unsigned long)page_address(page)); - local_irq_restore(flags); -} - -/* - * Writeback and invalidate the primary cache dcache before DMA. - * - * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, - * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only - * operate correctly if the internal data cache refill buffer is empty. These - * CACHE instructions should be separated from any potential data cache miss - * by a load instruction to an uncached address to empty the response buffer." - * (Revision 2.0 device errata from IDT available on http://www.idt.com/ - * in .pdf format.) - */ -static void r4k_dma_cache_wback_inv_pc(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - unsigned int flags; - - if (size >= (unsigned long)dcache_size) { - flush_cache_l1(); - } else { - /* Workaround for R4600 bug. See comment above. */ - local_irq_save(flags); - *(volatile unsigned long *)KSEG1; - - a = addr & ~((unsigned long)dc_lsize - 1); - end = (addr + size) & ~((unsigned long)dc_lsize - 1); - while (1) { - flush_dcache_line(a); /* Hit_Writeback_Inv_D */ - if (a == end) break; - a += dc_lsize; - } - local_irq_restore(flags); - } - bc_wback_inv(addr, size); -} - -static void r4k_dma_cache_wback_inv_sc(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - - if (size >= (unsigned long)scache_size) { - flush_cache_l1(); - return; - } - - a = addr & ~((unsigned long)sc_lsize - 1); - end = (addr + size) & ~((unsigned long)sc_lsize - 1); - while (1) { - flush_scache_line(a); /* Hit_Writeback_Inv_SD */ - if (a == end) break; - a += sc_lsize; - } -} - -static void r4k_dma_cache_inv_pc(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - unsigned int flags; - - if (size >= (unsigned long)dcache_size) { - flush_cache_l1(); - } else { - /* Workaround for R4600 bug. See comment above. */ - local_irq_save(flags); - *(volatile unsigned long *)KSEG1; - - a = addr & ~((unsigned long)dc_lsize - 1); - end = (addr + size) & ~((unsigned long)dc_lsize - 1); - while (1) { - flush_dcache_line(a); /* Hit_Writeback_Inv_D */ - if (a == end) break; - a += dc_lsize; - } - local_irq_restore(flags); - } - - bc_inv(addr, size); -} - -static void r4k_dma_cache_inv_sc(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - - if (size >= (unsigned long)scache_size) { - flush_cache_l1(); - return; - } - - a = addr & ~((unsigned long)sc_lsize - 1); - end = (addr + size) & ~((unsigned long)sc_lsize - 1); - while (1) { - flush_scache_line(a); /* Hit_Writeback_Inv_SD */ - if (a == end) break; - a += sc_lsize; - } -} - -static void r4k_dma_cache_wback(unsigned long addr, unsigned long size) -{ - panic("r4k_dma_cache called - should not happen.\n"); -} - -/* - * While we're protected against bad userland addresses we don't care - * very much about what happens in that case. Usually a segmentation - * fault will dump the process later on anyway ... - */ -static void r4k_flush_cache_sigtramp(unsigned long addr) -{ - __asm__ __volatile__("nop;nop;nop;nop"); /* R4600 V1.7 */ - - protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); - protected_flush_icache_line(addr & ~(ic_lsize - 1)); -} - -static void r4600v20k_flush_cache_sigtramp(unsigned long addr) -{ - unsigned int flags; - - local_irq_save(flags); - - /* Clear internal cache refill buffer */ - *(volatile unsigned int *)KSEG1; - - protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); - protected_flush_icache_line(addr & ~(ic_lsize - 1)); - - local_irq_restore(flags); -} - -#undef DEBUG_TLB - -#define NTLB_ENTRIES 48 /* Fixed on all R4XX0 variants... */ - -#define NTLB_ENTRIES_HALF 24 /* Fixed on all R4XX0 variants... */ - -static inline void r4k_flush_tlb_all(void) -{ - unsigned long flags; - unsigned long old_ctx; - int entry; - -#ifdef DEBUG_TLB - printk("[tlball]"); -#endif - - local_irq_save(flags); - /* Save old context and create impossible VPN2 value */ - old_ctx = (get_entryhi() & 0xff); - set_entryhi(KSEG0); - set_entrylo0(0); - set_entrylo1(0); - BARRIER; - - entry = get_wired(); - - /* Blast 'em all away. */ - while(entry < NTLB_ENTRIES) { - set_index(entry); - BARRIER; - tlb_write_indexed(); - BARRIER; - entry++; - } - BARRIER; - set_entryhi(old_ctx); - local_irq_restore(flags); -} - -static void r4k_flush_tlb_mm(struct mm_struct *mm) -{ - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { - unsigned long flags; - -#ifdef DEBUG_TLB - printk("[tlbmm<%d>]", mm->context); -#endif - local_irq_save(flags); - get_new_cpu_mmu_context(mm, smp_processor_id()); - if(mm == current->mm) - set_entryhi(CPU_CONTEXT(smp_processor_id(), mm) & 0xff); - local_irq_restore(flags); - } -} - -static void r4k_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - - if (CPU_CONTEXT(smp_processor_id(), mm) != 0) { - unsigned long flags; - int size; - -#ifdef DEBUG_TLB - printk("[tlbrange<%02x,%08lx,%08lx>]", (mm->context & 0xff), - start, end); -#endif - local_irq_save(flags); - size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - size = (size + 1) >> 1; - if(size <= NTLB_ENTRIES_HALF) { - int oldpid = (get_entryhi() & 0xff); - int newpid = (CPU_CONTEXT(smp_processor_id(), mm) & 0xff); - - start &= (PAGE_MASK << 1); - end += ((PAGE_SIZE << 1) - 1); - end &= (PAGE_MASK << 1); - while(start < end) { - int idx; - - set_entryhi(start | newpid); - start += (PAGE_SIZE << 1); - BARRIER; - tlb_probe(); - BARRIER; - idx = get_index(); - set_entrylo0(0); - set_entrylo1(0); - set_entryhi(KSEG0); - BARRIER; - if(idx < 0) - continue; - tlb_write_indexed(); - BARRIER; - } - set_entryhi(oldpid); - } else { - get_new_cpu_mmu_context(mm, smp_processor_id()); - if(mm == current->mm) - set_entryhi(CPU_CONTEXT(smp_processor_id(), - mm) & 0xff); - } - local_irq_restore(flags); - } -} - -static void r4k_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) -{ - if (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) != 0) { - unsigned long flags; - int oldpid, newpid, idx; - -#ifdef DEBUG_TLB - printk("[tlbpage<%d,%08lx>]", vma->vm_mm->context, page); -#endif - newpid = (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) & 0xff); - page &= (PAGE_MASK << 1); - local_irq_save(flags); - oldpid = (get_entryhi() & 0xff); - set_entryhi(page | newpid); - BARRIER; - tlb_probe(); - BARRIER; - idx = get_index(); - set_entrylo0(0); - set_entrylo1(0); - set_entryhi(KSEG0); - if(idx < 0) - goto finish; - BARRIER; - tlb_write_indexed(); - - finish: - BARRIER; - set_entryhi(oldpid); - local_irq_restore(flags); - } -} - -static void r4k_flush_cache_l2(void) -{ -} - -/* We will need multiple versions of update_mmu_cache(), one that just - * updates the TLB with the new pte(s), and another which also checks - * for the R4k "end of page" hardware bug and does the needy. - */ -static void r4k_update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) -{ - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - int idx, pid; - - /* - * Handle debugger faulting in for debugee. - */ - if (current->active_mm != vma->vm_mm) - return; - - local_irq_save(flags); - pid = (get_entryhi() & 0xff); - -#ifdef DEBUG_TLB - if((pid != (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) & 0xff)) || - (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) == 0)) { - printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d - tlbpid=%d\n", (int) (CPU_CONTEXT(smp_processor_id(), - vma->vm_mm) & 0xff), pid); - } -#endif - - address &= (PAGE_MASK << 1); - set_entryhi(address | (pid)); - pgdp = pgd_offset(vma->vm_mm, address); - BARRIER; - tlb_probe(); - BARRIER; - pmdp = pmd_offset(pgdp, address); - idx = get_index(); - ptep = pte_offset(pmdp, address); - BARRIER; - set_entrylo0(pte_val(*ptep++) >> 6); - set_entrylo1(pte_val(*ptep) >> 6); - set_entryhi(address | (pid)); - BARRIER; - if(idx < 0) { - tlb_write_random(); - } else { - tlb_write_indexed(); - } - BARRIER; - set_entryhi(pid); - BARRIER; - local_irq_restore(flags); -} - -#if 0 -static void r4k_update_mmu_cache_hwbug(struct vm_area_struct * vma, - unsigned long address, pte_t pte) -{ - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - int idx; - - local_irq_save(flags); - address &= (PAGE_MASK << 1); - set_entryhi(address | (get_entryhi() & 0xff)); - pgdp = pgd_offset(vma->vm_mm, address); - tlb_probe(); - pmdp = pmd_offset(pgdp, address); - idx = get_index(); - ptep = pte_offset(pmdp, address); - set_entrylo0(pte_val(*ptep++) >> 6); - set_entrylo1(pte_val(*ptep) >> 6); - BARRIER; - if(idx < 0) - tlb_write_random(); - else - tlb_write_indexed(); - BARRIER; - local_irq_restore(flags); -} -#endif - -static void r4k_show_regs(struct pt_regs *regs) -{ - /* Saved main processor registers. */ - printk("$0 : %016lx %016lx %016lx %016lx\n", - 0UL, regs->regs[1], regs->regs[2], regs->regs[3]); - printk("$4 : %016lx %016lx %016lx %016lx\n", - regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); - printk("$8 : %016lx %016lx %016lx %016lx\n", - regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11]); - printk("$12 : %016lx %016lx %016lx %016lx\n", - regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]); - printk("$16 : %016lx %016lx %016lx %016lx\n", - regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19]); - printk("$20 : %016lx %016lx %016lx %016lx\n", - regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]); - printk("$24 : %016lx %016lx\n", - regs->regs[24], regs->regs[25]); - printk("$28 : %016lx %016lx %016lx %016lx\n", - regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]); - printk("Hi : %016lx\n", regs->hi); - printk("Lo : %016lx\n", regs->lo); - - /* Saved cp0 registers. */ - printk("epc : %016lx %s\nbadvaddr: %016lx\n", - regs->cp0_epc, print_tainted(), regs->cp0_badvaddr); - printk("Status : %08x\nCause : %08x\n", - (unsigned int) regs->cp0_status, (unsigned int) regs->cp0_cause); -} - -/* Detect and size the various r4k caches. */ -static void __init probe_icache(unsigned long config) -{ - icache_size = 1 << (12 + ((config >> 9) & 7)); - ic_lsize = 16 << ((config >> 5) & 1); - - printk("Primary instruction cache %dkb, linesize %d bytes)\n", - icache_size >> 10, ic_lsize); -} - -static void __init probe_dcache(unsigned long config) -{ - dcache_size = 1 << (12 + ((config >> 6) & 7)); - dc_lsize = 16 << ((config >> 4) & 1); - - printk("Primary data cache %dkb, linesize %d bytes)\n", - dcache_size >> 10, dc_lsize); -} - - -/* If you even _breathe_ on this function, look at the gcc output - * and make sure it does not pop things on and off the stack for - * the cache sizing loop that executes in KSEG1 space or else - * you will crash and burn badly. You have been warned. - */ -static int __init probe_scache(unsigned long config) -{ - extern unsigned long stext; - unsigned long flags, addr, begin, end, pow2; - int tmp; - - tmp = ((config >> 17) & 1); - if(tmp) - return 0; - tmp = ((config >> 22) & 3); - switch(tmp) { - case 0: - sc_lsize = 16; - break; - case 1: - sc_lsize = 32; - break; - case 2: - sc_lsize = 64; - break; - case 3: - sc_lsize = 128; - break; - } - - begin = (unsigned long) &stext; - begin &= ~((4 * 1024 * 1024) - 1); - end = begin + (4 * 1024 * 1024); - - /* This is such a bitch, you'd think they would make it - * easy to do this. Away you daemons of stupidity! - */ - local_irq_save(flags); - - /* Fill each size-multiple cache line with a valid tag. */ - pow2 = (64 * 1024); - for(addr = begin; addr < end; addr = (begin + pow2)) { - unsigned long *p = (unsigned long *) addr; - __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ - pow2 <<= 1; - } - - /* Load first line with zero (therefore invalid) tag. */ - set_taglo(0); - set_taghi(0); - __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ - __asm__ __volatile__("\n\t.set noreorder\n\t" - "cache 8, (%0)\n\t" - ".set reorder\n\t" : : "r" (begin)); - __asm__ __volatile__("\n\t.set noreorder\n\t" - "cache 9, (%0)\n\t" - ".set reorder\n\t" : : "r" (begin)); - __asm__ __volatile__("\n\t.set noreorder\n\t" - "cache 11, (%0)\n\t" - ".set reorder\n\t" : : "r" (begin)); - - /* Now search for the wrap around point. */ - pow2 = (128 * 1024); - tmp = 0; - for(addr = (begin + (128 * 1024)); addr < (end); addr = (begin + pow2)) { - __asm__ __volatile__("\n\t.set noreorder\n\t" - "cache 7, (%0)\n\t" - ".set reorder\n\t" : : "r" (addr)); - __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ - if(!get_taglo()) - break; - pow2 <<= 1; - } - local_irq_restore(flags); - addr -= begin; - printk("Secondary cache sized at %dK linesize %d\n", - (int) (addr >> 10), sc_lsize); - scache_size = addr; - return 1; -} - -static void __init setup_noscache_funcs(void) -{ - unsigned int prid; - - switch(dc_lsize) { - case 16: - _clear_page = r4k_clear_page_d16; - _copy_page = r4k_copy_page_d16; - _flush_cache_l1 = r4k_flush_cache_all_d16i16; - _flush_cache_mm = r4k_flush_cache_mm_d16i16; - _flush_cache_range = r4k_flush_cache_range_d16i16; - _flush_cache_page = r4k_flush_cache_page_d16i16; - break; - case 32: - prid = read_32bit_cp0_register(CP0_PRID) & 0xfff0; - if (prid == 0x2010) { /* R4600 V1.7 */ - _clear_page = r4k_clear_page_r4600_v1; - _copy_page = r4k_copy_page_r4600_v1; - } else if (prid == 0x2020) { /* R4600 V2.0 */ - _clear_page = r4k_clear_page_r4600_v2; - _copy_page = r4k_copy_page_r4600_v2; - } else { - _clear_page = r4k_clear_page_d32; - _copy_page = r4k_copy_page_d32; - } - _flush_cache_l1 = r4k_flush_cache_all_d32i32; - _flush_cache_mm = r4k_flush_cache_mm_d32i32; - _flush_cache_range = r4k_flush_cache_range_d32i32; - _flush_cache_page = r4k_flush_cache_page_d32i32; - break; - } - - switch(ic_lsize) { - case 16: - _flush_page_to_ram = r4k_flush_page_to_ram_d16; - break; - case 32: - _flush_page_to_ram = r4k_flush_page_to_ram_d32; - break; - } - - _dma_cache_wback_inv = r4k_dma_cache_wback_inv_pc; - _dma_cache_wback = r4k_dma_cache_wback; - _dma_cache_inv = r4k_dma_cache_inv_pc; -} - -static void __init setup_scache_funcs(void) -{ - switch(sc_lsize) { - case 16: - switch(dc_lsize) { - case 16: - _flush_cache_l1 = r4k_flush_cache_all_s16d16i16; - _flush_cache_mm = r4k_flush_cache_mm_s16d16i16; - _flush_cache_range = r4k_flush_cache_range_s16d16i16; - _flush_cache_page = r4k_flush_cache_page_s16d16i16; - break; - case 32: - panic("Invalid cache configuration detected"); - }; - _flush_page_to_ram = r4k_flush_page_to_ram_s16; - _clear_page = r4k_clear_page_s16; - _copy_page = r4k_copy_page_s16; - break; - case 32: - switch(dc_lsize) { - case 16: - _flush_cache_l1 = r4k_flush_cache_all_s32d16i16; - _flush_cache_mm = r4k_flush_cache_mm_s32d16i16; - _flush_cache_range = r4k_flush_cache_range_s32d16i16; - _flush_cache_page = r4k_flush_cache_page_s32d16i16; - break; - case 32: - _flush_cache_l1 = r4k_flush_cache_all_s32d32i32; - _flush_cache_mm = r4k_flush_cache_mm_s32d32i32; - _flush_cache_range = r4k_flush_cache_range_s32d32i32; - _flush_cache_page = r4k_flush_cache_page_s32d32i32; - break; - }; - _flush_page_to_ram = r4k_flush_page_to_ram_s32; - _clear_page = r4k_clear_page_s32; - _copy_page = r4k_copy_page_s32; - break; - case 64: - switch(dc_lsize) { - case 16: - _flush_cache_l1 = r4k_flush_cache_all_s64d16i16; - _flush_cache_mm = r4k_flush_cache_mm_s64d16i16; - _flush_cache_range = r4k_flush_cache_range_s64d16i16; - _flush_cache_page = r4k_flush_cache_page_s64d16i16; - break; - case 32: - _flush_cache_l1 = r4k_flush_cache_all_s64d32i32; - _flush_cache_mm = r4k_flush_cache_mm_s64d32i32; - _flush_cache_range = r4k_flush_cache_range_s64d32i32; - _flush_cache_page = r4k_flush_cache_page_s64d32i32; - break; - }; - _flush_page_to_ram = r4k_flush_page_to_ram_s64; - _clear_page = r4k_clear_page_s64; - _copy_page = r4k_copy_page_s64; - break; - case 128: - switch(dc_lsize) { - case 16: - _flush_cache_l1 = r4k_flush_cache_all_s128d16i16; - _flush_cache_mm = r4k_flush_cache_mm_s128d16i16; - _flush_cache_range = r4k_flush_cache_range_s128d16i16; - _flush_cache_page = r4k_flush_cache_page_s128d16i16; - break; - case 32: - _flush_cache_l1 = r4k_flush_cache_all_s128d32i32; - _flush_cache_mm = r4k_flush_cache_mm_s128d32i32; - _flush_cache_range = r4k_flush_cache_range_s128d32i32; - _flush_cache_page = r4k_flush_cache_page_s128d32i32; - break; - }; - _flush_page_to_ram = r4k_flush_page_to_ram_s128; - _clear_page = r4k_clear_page_s128; - _copy_page = r4k_copy_page_s128; - break; - } - _dma_cache_wback_inv = r4k_dma_cache_wback_inv_sc; - _dma_cache_wback = r4k_dma_cache_wback; - _dma_cache_inv = r4k_dma_cache_inv_sc; -} - -typedef int (*probe_func_t)(unsigned long); - -static inline void __init setup_scache(unsigned int config) -{ - probe_func_t probe_scache_kseg1; - int sc_present = 0; - - /* Maybe the cpu knows about a l2 cache? */ - probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache)); - sc_present = probe_scache_kseg1(config); - - if (sc_present) { - setup_scache_funcs(); - return; - } - - setup_noscache_funcs(); -} - -void __init ld_mmu_r4xx0(void) -{ - unsigned long config = read_32bit_cp0_register(CP0_CONFIG); - - printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID)); - -#ifdef CONFIG_MIPS_UNCACHED - set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); -#else - set_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); -#endif /* UNCACHED */ - - probe_icache(config); - probe_dcache(config); - setup_scache(config); - - switch(mips_cputype) { - case CPU_R4600: /* QED style two way caches? */ - case CPU_R4700: - case CPU_R5000: - case CPU_NEVADA: - _flush_cache_page = r4k_flush_cache_page_d32i32_r4600; - } - - _flush_cache_sigtramp = r4k_flush_cache_sigtramp; - if ((read_32bit_cp0_register(CP0_PRID) & 0xfff0) == 0x2020) { - _flush_cache_sigtramp = r4600v20k_flush_cache_sigtramp; - } - - _flush_tlb_all = r4k_flush_tlb_all; - _flush_tlb_mm = r4k_flush_tlb_mm; - _flush_tlb_range = r4k_flush_tlb_range; - _flush_tlb_page = r4k_flush_tlb_page; - _flush_cache_l2 = r4k_flush_cache_l2; - - update_mmu_cache = r4k_update_mmu_cache; - - _show_regs = r4k_show_regs; - - flush_cache_l1(); - - /* - * You should never change this register: - * - On R4600 1.7 the tlbp never hits for pages smaller than - * the value in the c0_pagemask register. - * - The entire mm handling assumes the c0_pagemask register to - * be set for 4kb pages. - */ - write_32bit_cp0_register(CP0_PAGEMASK, PM_4K); - _flush_tlb_all(); -} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/sc-ip22.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,177 @@ +/* + * sc-ip22.c: Indy cache management functions. + * + * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org), + * derived from r4xx0.c by David S. Miller (dm@engr.sgi.com). + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* Secondary cache size in bytes, if present. */ +static unsigned long scache_size; + +#undef DEBUG_CACHE + +#define SC_SIZE 0x00080000 +#define SC_LINE 32 +#define CI_MASK (SC_SIZE - SC_LINE) +#define SC_INDEX(n) ((n) & CI_MASK) + +static inline void indy_sc_wipe(unsigned long first, unsigned long last) +{ + unsigned long tmp; + + __asm__ __volatile__( + ".set\tpush\t\t\t# indy_sc_wipe\n\t" + ".set\tnoreorder\n\t" + ".set\tmips3\n\t" + ".set\tnoat\n\t" + "mfc0\t%2, $12\n\t" + "li\t$1, 0x80\t\t\t# Go 64 bit\n\t" + "mtc0\t$1, $12\n\t" + + "dli\t$1, 0x9000000080000000\n\t" + "or\t%0, $1\t\t\t# first line to flush\n\t" + "or\t%1, $1\t\t\t# last line to flush\n\t" + ".set\tat\n\t" + + "1:\tsw\t$0, 0(%0)\n\t" + "bne\t%0, %1, 1b\n\t" + " daddu\t%0, 32\n\t" + + "mtc0\t%2, $12\t\t\t# Back to 32 bit\n\t" + "nop; nop; nop; nop;\n\t" + ".set\tpop" + : "=r" (first), "=r" (last), "=&r" (tmp) + : "0" (first), "1" (last)); +} + +static void indy_sc_wback_invalidate(unsigned long addr, unsigned long size) +{ + unsigned long first_line, last_line; + unsigned int flags; + +#ifdef DEBUG_CACHE + printk("indy_sc_wback_invalidate[%08lx,%08lx]", addr, size); +#endif + + if (!size) + return; + + /* Which lines to flush? */ + first_line = SC_INDEX(addr); + last_line = SC_INDEX(addr + size - 1); + + local_irq_save(flags); + if (first_line <= last_line) { + indy_sc_wipe(first_line, last_line); + goto out; + } + + indy_sc_wipe(first_line, SC_SIZE - SC_LINE); + indy_sc_wipe(0, last_line); +out: + local_irq_restore(flags); +} + +static void indy_sc_enable(void) +{ + unsigned long addr, tmp1, tmp2; + + /* This is really cool... */ +#ifdef DEBUG_CACHE + printk("Enabling R4600 SCACHE\n"); +#endif + __asm__ __volatile__( + ".set\tpush\n\t" + ".set\tnoreorder\n\t" + ".set\tmips3\n\t" + "mfc0\t%2, $12\n\t" + "nop; nop; nop; nop;\n\t" + "li\t%1, 0x80\n\t" + "mtc0\t%1, $12\n\t" + "nop; nop; nop; nop;\n\t" + "li\t%0, 0x1\n\t" + "dsll\t%0, 31\n\t" + "lui\t%1, 0x9000\n\t" + "dsll32\t%1, 0\n\t" + "or\t%0, %1, %0\n\t" + "sb\t$0, 0(%0)\n\t" + "mtc0\t$0, $12\n\t" + "nop; nop; nop; nop;\n\t" + "mtc0\t%2, $12\n\t" + "nop; nop; nop; nop;\n\t" + ".set\tpop" + : "=r" (tmp1), "=r" (tmp2), "=r" (addr)); +} + +static void indy_sc_disable(void) +{ + unsigned long tmp1, tmp2, tmp3; + +#ifdef DEBUG_CACHE + printk("Disabling R4600 SCACHE\n"); +#endif + __asm__ __volatile__( + ".set\tpush\n\t" + ".set\tnoreorder\n\t" + ".set\tmips3\n\t" + "li\t%0, 0x1\n\t" + "dsll\t%0, 31\n\t" + "lui\t%1, 0x9000\n\t" + "dsll32\t%1, 0\n\t" + "or\t%0, %1, %0\n\t" + "mfc0\t%2, $12\n\t" + "nop; nop; nop; nop\n\t" + "li\t%1, 0x80\n\t" + "mtc0\t%1, $12\n\t" + "nop; nop; nop; nop\n\t" + "sh\t$0, 0(%0)\n\t" + "mtc0\t$0, $12\n\t" + "nop; nop; nop; nop\n\t" + "mtc0\t%2, $12\n\t" + "nop; nop; nop; nop\n\t" + ".set\tpop" + : "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)); +} + +static inline int __init indy_sc_probe(void) +{ + unsigned int size = ip22_eeprom_read(&sgimc->eeprom, 17); + if (size == 0) + return 0; + + size <<= PAGE_SHIFT; + printk(KERN_INFO "R4600/R5000 SCACHE size %ldK, linesize 32 bytes.\n", + size >> 10); + scache_size = size; + + return 1; +} + +/* XXX Check with wje if the Indy caches can differenciate between + writeback + invalidate and just invalidate. */ +struct bcache_ops indy_sc_ops = { + .bc_enable = indy_sc_enable, + .bc_disable = indy_sc_disable, + .bc_wback_inv = indy_sc_wback_invalidate, + .bc_inv = indy_sc_wback_invalidate +}; + +void __init indy_sc_init(void) +{ + if (indy_sc_probe()) { + indy_sc_enable(); + bcops = &indy_sc_ops; + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/sc-r5k.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,115 @@ +/* + * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org), + * derived from r4xx0.c by David S. Miller (dm@engr.sgi.com). + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* Secondary cache size in bytes, if present. */ +static unsigned long scache_size; + +#define SC_LINE 32 +#define SC_PAGE (128*SC_LINE) + +#define cache_op(base,op) \ +__asm__ __volatile__(" \ + .set noreorder; \ + .set mips3; \ + cache %1, (%0); \ + .set mips0; \ + .set reorder" \ + : \ + : "r" (base), \ + "i" (op)); + +static inline void blast_r5000_scache(void) +{ + unsigned long start = KSEG0; + unsigned long end = KSEG0 + scache_size; + + while(start < end) { + cache_op(start, R5K_Page_Invalidate_S); + start += SC_PAGE; + } +} + +static void r5k_dma_cache_inv_sc(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + + if (size >= scache_size) { + blast_r5000_scache(); + return; + } + + /* On the R5000 secondary cache we cannot + * invalidate less than a page at a time. + * The secondary cache is physically indexed, write-through. + */ + a = addr & ~(SC_PAGE - 1); + end = (addr + size - 1) & ~(SC_PAGE - 1); + while (a <= end) { + cache_op(a, R5K_Page_Invalidate_S); + a += SC_PAGE; + } +} + +static void r5k_sc_enable(void) +{ + unsigned long flags; + + local_irq_save(flags); + change_c0_config(R5K_CONF_SE, R5K_CONF_SE); + blast_r5000_scache(); + local_irq_restore(flags); +} + +static void r5k_sc_disable(void) +{ + unsigned long flags; + + local_irq_save(flags); + blast_r5000_scache(); + change_c0_config(R5K_CONF_SE, 0); + local_irq_restore(flags); +} + +static inline int __init r5k_sc_probe(void) +{ + unsigned long config = read_c0_config(); + + if (config & CONF_SC) + return(0); + + scache_size = (512 * 1024) << ((config & R5K_CONF_SS) >> 20); + + printk("R5000 SCACHE size %ldkB, linesize 32 bytes.\n", + scache_size >> 10); + + return 1; +} + +static struct bcache_ops r5k_sc_ops = { + .bc_enable = r5k_sc_enable, + .bc_disable = r5k_sc_disable, + .bc_wback_inv = r5k_dma_cache_inv_sc, + .bc_inv = r5k_dma_cache_inv_sc +}; + +void __init r5k_sc_init(void) +{ + if (r5k_sc_probe()) { + r5k_sc_enable(); + bcops = &r5k_sc_ops; + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/sc-rm7k.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,191 @@ +/* + * sc-rm7k.c: RM7000 cache management functions. + * + * Copyright (C) 1997, 2001, 2003 Ralf Baechle (ralf@gnu.org), + */ +#include +#include +#include + +#include +#include +#include +#include +#include + +/* Primary cache parameters. */ +#define sc_lsize 32 +#define tc_pagesize (32*128) + +/* Secondary cache parameters. */ +#define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */ + +extern unsigned long icache_way_size, dcache_way_size; + +#include + +int rm7k_tcache_enabled; + +/* + * Writeback and invalidate the primary cache dcache before DMA. + * (XXX These need to be fixed ...) + */ +static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + +#ifdef DEBUG_CACHE + printk("rm7k_sc_wback_inv[%08lx,%08lx]", addr, size); +#endif + + a = addr & ~(sc_lsize - 1); + end = (addr + size - 1) & ~(sc_lsize - 1); + while (1) { + flush_scache_line(a); /* Hit_Writeback_Inv_SD */ + if (a == end) + break; + a += sc_lsize; + } + + if (!rm7k_tcache_enabled) + return; + + a = addr & ~(tc_pagesize - 1); + end = (addr + size - 1) & ~(tc_pagesize - 1); + while(1) { + invalidate_tcache_page(a); /* Page_Invalidate_T */ + if (a == end) + break; + a += tc_pagesize; + } +} + +static void rm7k_sc_inv(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + +#ifdef DEBUG_CACHE + printk("rm7k_sc_inv[%08lx,%08lx]", addr, size); +#endif + + a = addr & ~(sc_lsize - 1); + end = (addr + size - 1) & ~(sc_lsize - 1); + while (1) { + invalidate_scache_line(a); /* Hit_Invalidate_SD */ + if (a == end) + break; + a += sc_lsize; + } + + if (!rm7k_tcache_enabled) + return; + + a = addr & ~(tc_pagesize - 1); + end = (addr + size - 1) & ~(tc_pagesize - 1); + while(1) { + invalidate_tcache_page(a); /* Page_Invalidate_T */ + if (a == end) + break; + a += tc_pagesize; + } +} + +/* + * This function is executed in the uncached segment KSEG1. + * It must not touch the stack, because the stack pointer still points + * into KSEG0. + * + * Three options: + * - Write it in assembly and guarantee that we don't use the stack. + * - Disable caching for KSEG0 before calling it. + * - Pray that GCC doesn't randomly start using the stack. + * + * This being Linux, we obviously take the least sane of those options - + * following DaveM's lead in c-r4k.c + * + * It seems we get our kicks from relying on unguaranteed behaviour in GCC + */ +static __init void rm7k_sc_enable(void) +{ + int i; + + set_c0_config(1<<3); /* CONF_SE */ + + write_c0_taglo(0); + write_c0_taghi(0); + + for (i=0; i> 31) & 1) + return 0; + + printk(KERN_INFO "Secondary cache size %ldK, linesize 32 bytes.\n", + (scache_size >> 10), sc_lsize); + + if ((config >> 3) & 1) + return; + + printk(KERN_INFO "Enabling secondary cache..."); + func(); + printk(" done\n"); + + /* + * While we're at it let's deal with the tertiary cache. + */ + if ((config >> 17) & 1) + return 1; + + /* + * We can't enable the L3 cache yet. There may be board-specific + * magic necessary to turn it on, and blindly asking the CPU to + * start using it would may give cache errors. + * + * Also, board-specific knowledge may allow us to use the + * CACHE Flash_Invalidate_T instruction if the tag RAM supports + * it, and may specify the size of the L3 cache so we don't have + * to probe it. + */ + printk(KERN_INFO "Tertiary cache present, %s enabled\n", + config&(1<<12) ? "already" : "not (yet)"); + + if ((config >> 12) & 1) + rm7k_tcache_enabled = 1; + + return 1; +} + +struct bcache_ops rm7k_sc_ops = { + .bc_enable = rm7k_sc_enable, + .bc_disable = rm7k_sc_disable, + .bc_wback_inv = rm7k_sc_wback_inv, + .bc_inv = rm7k_sc_inv +}; + +void __init rm7k_sc_init(void) +{ + if (rm7k_sc_probe()) { + rm7k_sc_enable(); + bcops = &rm7k_sc_ops; + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/tlb-andes.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,257 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1997, 1998, 1999 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2000 Kanoj Sarcar (kanoj@sgi.com) + */ +#include +#include +#include +#include +#include +#include +#include +#include + +extern void except_vec1_r10k(void); + +#define NTLB_ENTRIES 64 +#define NTLB_ENTRIES_HALF 32 + +void local_flush_tlb_all(void) +{ + unsigned long flags; + unsigned long old_ctx; + unsigned long entry; + + local_irq_save(flags); + /* Save old context and create impossible VPN2 value */ + old_ctx = read_c0_entryhi() & ASID_MASK; + write_c0_entryhi(CKSEG0); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + + entry = read_c0_wired(); + + /* Blast 'em all away. */ + while (entry < NTLB_ENTRIES) { + write_c0_index(entry); + tlb_write_indexed(); + entry++; + } + write_c0_entryhi(old_ctx); + local_irq_restore(flags); +} + +void local_flush_tlb_mm(struct mm_struct *mm) +{ + int cpu = smp_processor_id(); + if (cpu_context(cpu, mm) != 0) { + drop_mmu_context(mm,cpu); + } +} + +void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end) +{ + struct mm_struct *mm = vma->vm_mm; + int cpu = smp_processor_id(); + + if (cpu_context(cpu, mm) != 0) { + unsigned long flags; + int size; + + local_irq_save(flags); + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + size = (size + 1) >> 1; + if (size <= NTLB_ENTRIES_HALF) { + int oldpid = (read_c0_entryhi() & ASID_MASK); + int newpid = (cpu_context(smp_processor_id(), mm) + & ASID_MASK); + + start &= (PAGE_MASK << 1); + end += ((PAGE_SIZE << 1) - 1); + end &= (PAGE_MASK << 1); + while(start < end) { + int idx; + + write_c0_entryhi(start | newpid); + start += (PAGE_SIZE << 1); + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + write_c0_entryhi(KSEG0); + if(idx < 0) + continue; + tlb_write_indexed(); + } + write_c0_entryhi(oldpid); + } else { + drop_mmu_context(mm, cpu); + } + local_irq_restore(flags); + } +} + +void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) +{ + unsigned long flags; + int size; + + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + size = (size + 1) >> 1; + + local_irq_save(flags); + if (size <= NTLB_ENTRIES_HALF) { + int pid = read_c0_entryhi(); + + start &= (PAGE_MASK << 1); + end += ((PAGE_SIZE << 1) - 1); + end &= (PAGE_MASK << 1); + + while (start < end) { + int idx; + + write_c0_entryhi(start); + start += (PAGE_SIZE << 1); + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + write_c0_entryhi(KSEG0 + (idx << (PAGE_SHIFT+1))); + if (idx < 0) + continue; + tlb_write_indexed(); + } + write_c0_entryhi(pid); + } else { + local_flush_tlb_all(); + } + local_irq_restore(flags); +} + +void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) +{ + if (cpu_context(smp_processor_id(), vma->vm_mm) != 0) { + unsigned long flags; + int oldpid, newpid, idx; + + newpid = (cpu_context(smp_processor_id(), vma->vm_mm) & + ASID_MASK); + page &= (PAGE_MASK << 1); + local_irq_save(flags); + oldpid = (read_c0_entryhi() & ASID_MASK); + write_c0_entryhi(page | newpid); + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + write_c0_entryhi(KSEG0); + if (idx < 0) + goto finish; + tlb_write_indexed(); + + finish: + write_c0_entryhi(oldpid); + local_irq_restore(flags); + } +} + +/* + * This one is only used for pages with the global bit set so we don't care + * much about the ASID. + */ +void local_flush_tlb_one(unsigned long page) +{ + unsigned long flags; + int oldpid, idx; + + local_irq_save(flags); + page &= (PAGE_MASK << 1); + oldpid = read_c0_entryhi() & 0xff; + write_c0_entryhi(page); + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + if (idx >= 0) { + /* Make sure all entries differ. */ + write_c0_entryhi(KSEG0+(idx<<(PAGE_SHIFT+1))); + tlb_write_indexed(); + } + write_c0_entryhi(oldpid); + + local_irq_restore(flags); +} + +/* XXX Simplify this. On the R10000 writing a TLB entry for an virtual + address that already exists will overwrite the old entry and not result + in TLB malfunction or TLB shutdown. */ +void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) +{ + unsigned long flags; + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + int idx, pid; + + /* + * Handle debugger faulting in for debugee. + */ + if (current->active_mm != vma->vm_mm) + return; + + pid = read_c0_entryhi() & ASID_MASK; + + if ((pid != (cpu_context(smp_processor_id(), vma->vm_mm) & ASID_MASK)) + || (cpu_context(smp_processor_id(), vma->vm_mm) == 0)) { + printk(KERN_WARNING + "%s: Wheee, bogus tlbpid mmpid=%d tlbpid=%d\n", + __FUNCTION__, (int) (cpu_context(smp_processor_id(), + vma->vm_mm) & ASID_MASK), pid); + } + + local_irq_save(flags); + address &= (PAGE_MASK << 1); + write_c0_entryhi(address | (pid)); + pgdp = pgd_offset(vma->vm_mm, address); + tlb_probe(); + pmdp = pmd_offset(pgdp, address); + idx = read_c0_index(); + ptep = pte_offset_map(pmdp, address); + write_c0_entrylo0(pte_val(*ptep++) >> 6); + write_c0_entrylo1(pte_val(*ptep) >> 6); + write_c0_entryhi(address | (pid)); + if (idx < 0) { + tlb_write_random(); + } else { + tlb_write_indexed(); + } + write_c0_entryhi(pid); + local_irq_restore(flags); +} + +void __init andes_tlb_init(void) +{ + /* + * You should never change this register: + * - On R4600 1.7 the tlbp never hits for pages smaller than + * the value in the c0_pagemask register. + * - The entire mm handling assumes the c0_pagemask register to + * be set for 4kb pages. + */ + write_c0_pagemask(PM_4K); + write_c0_wired(0); + write_c0_framemask(0); + + /* From this point on the ARC firmware is dead. */ + local_flush_tlb_all(); + + /* Did I tell you that ARC SUCKS? */ + + memcpy((void *)KSEG1 + 0x080, except_vec1_r10k, 0x80); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/tlb-dbg-r4k.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,71 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999 Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + * + * TLB debugging routines. These perform horribly slow but can easily be + * modified for debugging purposes. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write, + unsigned long address); + +asmlinkage void tlb_refill_debug(struct pt_regs regs) +{ + show_regs(®s); + panic(__FUNCTION__ " called. This Does Not Happen (TM)."); +} + +asmlinkage void xtlb_refill_debug(struct pt_regs *regs) +{ + unsigned long addr; + pgd_t *pgd; + pmd_t *pmd; + pte_t *pte; + + addr = regs->cp0_badvaddr & ~((PAGE_SIZE << 1) - 1); + pgd = pgd_offset(current->active_mm, addr); + pmd = pmd_offset(pgd, addr); + pte = pte_offset(pmd, addr); + + write_c0_entrylo0(pte_val(pte[0]) >> 6); + write_c0_entrylo1(pte_val(pte[1]) >> 6); + __asm__ __volatile__("nop;nop;nop"); + + tlb_write_random(); +} + +asmlinkage void xtlb_mod_debug(struct pt_regs *regs) +{ + unsigned long addr; + + addr = regs->cp0_badvaddr; + do_page_fault(regs, 1, addr); +} + +asmlinkage void xtlb_tlbl_debug(struct pt_regs *regs) +{ + unsigned long addr; + + addr = regs->cp0_badvaddr; + do_page_fault(regs, 0, addr); +} + +asmlinkage void xtlb_tlbs_debug(struct pt_regs *regs) +{ + unsigned long addr; + + addr = regs->cp0_badvaddr; + do_page_fault(regs, 1, addr); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/tlbex-r4k.S 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,208 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Silicon Graphics, Inc. + * Written by Ulf Carlsson (ulfc@engr.sgi.com) + * Copyright (C) 2002 Maciej W. Rozycki + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + + .data + .comm pgd_current, NR_CPUS * 8, 8 + + /* + * After this macro runs we have a pointer to the pte of the address + * that caused the fault in PTR. + */ + .macro LOAD_PTE2, ptr, tmp, kaddr +#ifdef CONFIG_SMP + dmfc0 \ptr, CP0_CONTEXT + dmfc0 \tmp, CP0_BADVADDR + dsra \ptr, 23 # get pgd_current[cpu] +#else + dmfc0 \tmp, CP0_BADVADDR + dla \ptr, pgd_current +#endif + bltz \tmp, \kaddr + ld \ptr, (\ptr) + dsrl \tmp, (PGDIR_SHIFT-3) # get pgd offset in bytes + andi \tmp, ((PTRS_PER_PGD - 1)<<3) + daddu \ptr, \tmp # add in pgd offset + dmfc0 \tmp, CP0_BADVADDR + ld \ptr, (\ptr) # get pmd pointer + dsrl \tmp, (PMD_SHIFT-3) # get pmd offset in bytes + andi \tmp, ((PTRS_PER_PMD - 1)<<3) + daddu \ptr, \tmp # add in pmd offset + dmfc0 \tmp, CP0_XCONTEXT + ld \ptr, (\ptr) # get pte pointer + andi \tmp, 0xff0 # get pte offset + daddu \ptr, \tmp + .endm + + + /* + * Ditto for the kernel table. + */ + .macro LOAD_KPTE2, ptr, tmp, not_vmalloc + /* + * First, determine that the address is in/above vmalloc range. + */ + dmfc0 \tmp, CP0_BADVADDR + dli \ptr, VMALLOC_START + + /* + * Now find offset into kptbl. + */ + dsubu \tmp, \tmp, \ptr + dla \ptr, kptbl + dsrl \tmp, (PAGE_SHIFT+1) # get vpn2 + dsll \tmp, 4 # byte offset of pte + daddu \ptr, \ptr, \tmp + + /* + * Determine that fault address is within vmalloc range. + */ + dla \tmp, ekptbl + slt \tmp, \ptr, \tmp + beqz \tmp, \not_vmalloc # not vmalloc + nop + .endm + + + /* + * This places the even/odd pte pair in the page table at the pte + * entry pointed to by PTE into ENTRYLO0 and ENTRYLO1. + */ + .macro PTE_RELOAD, pte0, pte1 + dsrl \pte0, 6 # convert to entrylo0 + dmtc0 \pte0, CP0_ENTRYLO0 # load it + dsrl \pte1, 6 # convert to entrylo1 + dmtc0 \pte1, CP0_ENTRYLO1 # load it + .endm + + + .text + .set noreorder + .set mips3 + + __INIT + + .align 5 +LEAF(except_vec0_generic) + .set noat + PANIC("Unused vector called") +1: b 1b + nop +END(except_vec0_generic) + + + /* + * TLB refill handlers for the R4000 and SB1. + * Attention: We may only use 32 instructions / 128 bytes. + */ + .align 5 +LEAF(except_vec1_r4k) + .set noat + dla k0, handle_vec1_r4k + jr k0 + nop +END(except_vec1_r4k) + +LEAF(except_vec1_sb1) +#if BCM1250_M3_WAR + dmfc0 k0, CP0_BADVADDR + dmfc0 k1, CP0_ENTRYHI + xor k0, k1 + dsrl k0, k0, PAGE_SHIFT+1 + bnez k0, 1f +#endif + .set noat + dla k0, handle_vec1_r4k + jr k0 + nop + +1: eret + nop +END(except_vec1_sb1) + + __FINIT + + .align 5 +LEAF(handle_vec1_r4k) + .set noat + LOAD_PTE2 k1 k0 9f + ld k0, 0(k1) # get even pte + ld k1, 8(k1) # get odd pte + PTE_RELOAD k0 k1 + b 1f + tlbwr +1: nop + eret + +9: # handle the vmalloc range + LOAD_KPTE2 k1 k0 invalid_vmalloc_address + ld k0, 0(k1) # get even pte + ld k1, 8(k1) # get odd pte + PTE_RELOAD k0 k1 + b 1f + tlbwr +1: nop + eret +END(handle_vec1_r4k) + + + __INIT + + /* + * TLB refill handler for the R10000. + * Attention: We may only use 32 instructions / 128 bytes. + */ + .align 5 +LEAF(except_vec1_r10k) + .set noat + dla k0, handle_vec1_r10k + jr k0 + nop +END(except_vec1_r10k) + + __FINIT + + .align 5 +LEAF(handle_vec1_r10k) + .set noat + LOAD_PTE2 k1 k0 9f + ld k0, 0(k1) # get even pte + ld k1, 8(k1) # get odd pte + PTE_RELOAD k0 k1 + nop + tlbwr + eret + +9: # handle the vmalloc range + LOAD_KPTE2 k1 k0 invalid_vmalloc_address + ld k0, 0(k1) # get even pte + ld k1, 8(k1) # get odd pte + PTE_RELOAD k0 k1 + nop + tlbwr + eret +END(handle_vec1_r10k) + + + .align 5 +LEAF(invalid_vmalloc_address) + .set noat + PANIC("Invalid kernel address") +1: b 1b + nop +END(invalid_vmalloc_address) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/tlb-glue-r4k.S 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,41 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999 Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#include +#include +#include +#include + + .macro __BUILD_cli + CLI + .endm + + .macro __BUILD_sti + STI + .endm + + .macro __BUILD_kmode + KMODE + .endm + + .macro tlb_handler name interruptible writebit + NESTED(__\name, PT_SIZE, sp) + SAVE_ALL + dmfc0 a2, CP0_BADVADDR + __BUILD_\interruptible + li a1, \writebit + sd a2, PT_BVADDR(sp) + move a0, sp + jal do_page_fault + j ret_from_exception + END(__\name) + .endm + + tlb_handler xtlb_mod kmode 1 + tlb_handler xtlb_tlbl kmode 0 + tlb_handler xtlb_tlbs kmode 1 --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/tlb-glue-sb1.S 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,66 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999 Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#include +#include +#include +#include +#include +#include + + .macro __BUILD_cli + CLI + .endm + + .macro __BUILD_sti + STI + .endm + + .macro __BUILD_kmode + KMODE + .endm + + .macro tlb_handler name interruptible writebit + NESTED(__\name, PT_SIZE, sp) + SAVE_ALL + dmfc0 a2, CP0_BADVADDR + __BUILD_\interruptible + li a1, \writebit + sd a2, PT_BVADDR(sp) + move a0, sp + jal do_page_fault + j ret_from_exception + END(__\name) + .endm + + .macro tlb_handler_m3 name interruptible writebit + NESTED(__\name, PT_SIZE, sp) + dmfc0 k0, CP0_BADVADDR + dmfc0 k1, CP0_ENTRYHI + xor k0, k1 + dsrl k0, k0, PAGE_SHIFT + 1 + bnez k0, 1f + SAVE_ALL + dmfc0 a2, CP0_BADVADDR + __BUILD_\interruptible + li a1, \writebit + sd a2, PT_BVADDR(sp) + move a0, sp + jal do_page_fault +1: + j ret_from_exception + END(__\name) + .endm + + tlb_handler xtlb_mod kmode 1 +#if BCM1250_M3_WAR + tlb_handler_m3 xtlb_tlbl kmode 0 +#else + tlb_handler xtlb_tlbl kmode 0 +#endif + tlb_handler xtlb_tlbs kmode 1 --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/tlb-r4k.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,415 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * MIPS64 CPU variant specific MMU routines. + * These routine are not optimized in any way, they are done in a generic way + * so they can be used on all MIPS64 compliant CPUs, and also done in an + * attempt not to break anything for the R4xx0 style CPUs. + */ +#include +#include +#include + +#include +#include +#include +#include +#include + +#undef DEBUG_TLB +#undef DEBUG_TLBUPDATE + +extern void except_vec1_r4k(void); + +/* CP0 hazard avoidance. */ +#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ + "nop; nop; nop; nop; nop; nop;\n\t" \ + ".set reorder\n\t") + +void local_flush_tlb_all(void) +{ + unsigned long flags; + unsigned long old_ctx; + int entry; + +#ifdef DEBUG_TLB + printk("[tlball]"); +#endif + + local_irq_save(flags); + /* Save old context and create impossible VPN2 value */ + old_ctx = read_c0_entryhi() & ASID_MASK; + write_c0_entryhi(XKPHYS); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + BARRIER; + + entry = read_c0_wired(); + + /* Blast 'em all away. */ + while(entry < current_cpu_data.tlbsize) { + /* Make sure all entries differ. */ + write_c0_entryhi(XKPHYS+entry*0x2000); + write_c0_index(entry); + BARRIER; + tlb_write_indexed(); + BARRIER; + entry++; + } + BARRIER; + write_c0_entryhi(old_ctx); + local_irq_restore(flags); +} + +void local_flush_tlb_mm(struct mm_struct *mm) +{ + int cpu = smp_processor_id(); + + if (cpu_context(cpu, mm) != 0) { +#ifdef DEBUG_TLB + printk("[tlbmm<%d>]", cpu_context(cpu, mm)); +#endif + drop_mmu_context(mm,cpu); + } +} + +void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end) +{ + struct mm_struct *mm = vma->vm_mm; + int cpu = smp_processor_id(); + + if (cpu_context(cpu, mm) != 0) { + unsigned long flags; + int size; + +#ifdef DEBUG_TLB + printk("[tlbrange<%02x,%08lx,%08lx>]", cpu_context(cpu, mm) & ASID_MASK, + start, end); +#endif + local_irq_save(flags); + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + size = (size + 1) >> 1; + if(size <= current_cpu_data.tlbsize/2) { + int oldpid = read_c0_entryhi() & ASID_MASK; + int newpid = cpu_asid(cpu, mm); + + start &= (PAGE_MASK << 1); + end += ((PAGE_SIZE << 1) - 1); + end &= (PAGE_MASK << 1); + while (start < end) { + int idx; + + write_c0_entryhi(start | newpid); + start += (PAGE_SIZE << 1); + BARRIER; + tlb_probe(); + BARRIER; + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + if(idx < 0) + continue; + /* Make sure all entries differ. */ + write_c0_entryhi(XKPHYS+idx*0x2000); + BARRIER; + tlb_write_indexed(); + BARRIER; + } + write_c0_entryhi(oldpid); + } else { + drop_mmu_context(mm, cpu); + } + local_irq_restore(flags); + } +} + +void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) +{ + unsigned long flags; + int size; + +#ifdef DEBUG_TLB + printk("[tlbkernelrange<%08lx,%08lx>]", start, end); +#endif + local_irq_save(flags); + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + size = (size + 1) >> 1; + if (size <= current_cpu_data.tlbsize/2) { + int pid = read_c0_entryhi(); + + start &= (PAGE_MASK << 1); + end += ((PAGE_SIZE << 1) - 1); + end &= (PAGE_MASK << 1); + + while (start < end) { + int idx; + + write_c0_entryhi(start); + start += (PAGE_SIZE << 1); + BARRIER; + tlb_probe(); + BARRIER; + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + if (idx < 0) + continue; + /* Make sure all entries differ. */ + write_c0_entryhi(XKPHYS+idx*0x2000); + BARRIER; + tlb_write_indexed(); + BARRIER; + } + write_c0_entryhi(pid); + } else { + local_flush_tlb_all(); + } + local_irq_restore(flags); +} + +void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) +{ + int cpu = smp_processor_id(); + + if (cpu_context(cpu, vma->vm_mm) != 0) { + unsigned long flags; + unsigned long oldpid, newpid, idx; + +#ifdef DEBUG_TLB + printk("[tlbpage<%d,%08lx>]", cpu_asid(cpu, vma->vm_mm), page); +#endif + newpid = cpu_asid(cpu, vma->vm_mm); + page &= (PAGE_MASK << 1); + local_irq_save(flags); + oldpid = read_c0_entryhi() & ASID_MASK; + write_c0_entryhi(page | newpid); + BARRIER; + tlb_probe(); + BARRIER; + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + if(idx < 0) + goto finish; + /* Make sure all entries differ. */ + write_c0_entryhi(XKPHYS+idx*0x2000); + BARRIER; + tlb_write_indexed(); + finish: + BARRIER; + write_c0_entryhi(oldpid); + local_irq_restore(flags); + } +} + +/* + * This one is only used for pages with the global bit set so we don't care + * much about the ASID. + */ +void local_flush_tlb_one(unsigned long page) +{ + unsigned long flags; + int oldpid, idx; + + local_irq_save(flags); + page &= (PAGE_MASK << 1); + oldpid = read_c0_entryhi() & 0xff; + write_c0_entryhi(page); + BARRIER; + tlb_probe(); + BARRIER; + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + if (idx >= 0) { + /* Make sure all entries differ. */ + write_c0_entryhi(KSEG0+(idx<<(PAGE_SHIFT+1))); + BARRIER; + tlb_write_indexed(); + } + BARRIER; + write_c0_entryhi(oldpid); + + local_irq_restore(flags); +} + +/* + * Updates the TLB with the new pte(s). + */ +void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) +{ + unsigned long flags; + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + int idx, pid; + + /* + * Handle debugger faulting in for debugee. + */ + if (current->active_mm != vma->vm_mm) + return; + + pid = read_c0_entryhi() & ASID_MASK; + +#ifdef DEBUG_TLB + if ((pid != cpu_asid(smp_processor_id(), vma->vm_mm))) || + (cpu_context(smp_processor_id(), vma->vm_mm) == 0)) { + printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d " + "tlbpid=%d\n", (int) cpu_asid(smp_processor_id(), + vma->vm_mm), pid); + } +#endif + + local_irq_save(flags); + address &= (PAGE_MASK << 1); + write_c0_entryhi(address | (pid)); + pgdp = pgd_offset(vma->vm_mm, address); + BARRIER; + tlb_probe(); + BARRIER; + pmdp = pmd_offset(pgdp, address); + idx = read_c0_index(); + ptep = pte_offset_map(pmdp, address); + BARRIER; + write_c0_entrylo0(pte_val(*ptep++) >> 6); + write_c0_entrylo1(pte_val(*ptep) >> 6); + write_c0_entryhi(address | (pid)); + BARRIER; + if(idx < 0) { + tlb_write_random(); + } else { + tlb_write_indexed(); + } + BARRIER; + write_c0_entryhi(pid); + BARRIER; + local_irq_restore(flags); +} + +void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask) +{ + unsigned long flags; + unsigned long wired; + unsigned long old_pagemask; + unsigned long old_ctx; + + local_irq_save(flags); + /* Save old context and create impossible VPN2 value */ + old_ctx = read_c0_entryhi() & ASID_MASK; + old_pagemask = read_c0_pagemask(); + wired = read_c0_wired(); + write_c0_wired(wired + 1); + write_c0_index(wired); + BARRIER; + write_c0_pagemask(pagemask); + write_c0_entryhi(entryhi); + write_c0_entrylo0(entrylo0); + write_c0_entrylo1(entrylo1); + BARRIER; + tlb_write_indexed(); + BARRIER; + + write_c0_entryhi(old_ctx); + BARRIER; + write_c0_pagemask(old_pagemask); + local_flush_tlb_all(); + local_irq_restore(flags); +} + +/* + * Used for loading TLB entries before trap_init() has started, when we + * don't actually want to add a wired entry which remains throughout the + * lifetime of the system + */ + +static int temp_tlb_entry __initdata; + +__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask) +{ + int ret = 0; + unsigned long flags; + unsigned long wired; + unsigned long old_pagemask; + unsigned long old_ctx; + + local_irq_save(flags); + /* Save old context and create impossible VPN2 value */ + old_ctx = read_c0_entryhi() & ASID_MASK; + old_pagemask = read_c0_pagemask(); + wired = read_c0_wired(); + if (--temp_tlb_entry < wired) { + printk(KERN_WARNING "No TLB space left for add_temporary_entry\n"); + ret = -ENOSPC; + goto out; + } + + write_c0_index(temp_tlb_entry); + BARRIER; + write_c0_pagemask(pagemask); + write_c0_entryhi(entryhi); + write_c0_entrylo0(entrylo0); + write_c0_entrylo1(entrylo1); + BARRIER; + tlb_write_indexed(); + BARRIER; + + write_c0_entryhi(old_ctx); + BARRIER; + write_c0_pagemask(old_pagemask); +out: + local_irq_restore(flags); + return ret; +} + +static void __init probe_tlb(unsigned long config) +{ + unsigned long config1; + + if (!(config & (1 << 31))) { + /* + * Not a MIPS64 complainant CPU. + * Config 1 register not supported, we assume R4k style. + */ + current_cpu_data.tlbsize = 48; + } else { + config1 = read_c0_config1(); + if (!((config >> 7) & 3)) + panic("No MMU present"); + else + current_cpu_data.tlbsize = ((config1 >> 25) & 0x3f) + 1; + } + + printk("Number of TLB entries %d.\n", current_cpu_data.tlbsize); +} + +void __init r4k_tlb_init(void) +{ + unsigned long config = read_c0_config(); + + probe_tlb(config); + write_c0_pagemask(PM_4K); + write_c0_wired(0); + temp_tlb_entry = current_cpu_data.tlbsize - 1; + local_flush_tlb_all(); + + memcpy((void *)(KSEG0 + 0x80), except_vec1_r4k, 0x80); + flush_icache_range(KSEG0, KSEG0 + 0x80); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips64/mm/tlb-sb1.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,342 @@ +/* + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include +#include +#include +#include + +extern void except_vec1_sb1(void); + +/* Dump the current entry* and pagemask registers */ +static inline void dump_cur_tlb_regs(void) +{ + unsigned int entryhihi, entryhilo, entrylo0hi, entrylo0lo, entrylo1hi; + unsigned int entrylo1lo, pagemask; + + __asm__ __volatile__ ( + ".set push \n" + ".set noreorder \n" + "#.set mips64 \n" + ".set mips4 \n" + ".set noat \n" + " tlbr \n" + " dmfc0 $1, $10 \n" + " dsrl32 %0, $1, 0 \n" + " sll %1, $1, 0 \n" + " dmfc0 $1, $2 \n" + " dsrl32 %2, $1, 0 \n" + " sll %3, $1, 0 \n" + " dmfc0 $1, $3 \n" + " dsrl32 %4, $1, 0 \n" + " sll %5, $1, 0 \n" + " mfc0 %6, $5 \n" + ".set pop \n" + : "=r" (entryhihi), + "=r" (entryhilo), + "=r" (entrylo0hi), + "=r" (entrylo0lo), + "=r" (entrylo1hi), + "=r" (entrylo1lo), + "=r" (pagemask)); + printk("%08X%08X %08X%08X %08X%08X %08X", + entryhihi, entryhilo, + entrylo0hi, entrylo0lo, + entrylo1hi, entrylo1lo, + pagemask); +} + +void sb1_dump_tlb(void) +{ + unsigned long old_ctx; + unsigned long flags; + int entry; + local_irq_save(flags); + old_ctx = read_c0_entryhi(); + printk("Current TLB registers state:\n" + " EntryHi EntryLo0 EntryLo1 PageMask Index\n" + "--------------------------------------------------------------------\n"); + dump_cur_tlb_regs(); + printk(" %08X\n", read_c0_index()); + printk("\n\nFull TLB Dump:\n" + "Idx EntryHi EntryLo0 EntryLo1 PageMask\n" + "--------------------------------------------------------------\n"); + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { + write_c0_index(entry); + printk("\n%02i ", entry); + dump_cur_tlb_regs(); + } + printk("\n"); + write_c0_entryhi(old_ctx); + local_irq_restore(flags); +} + +void local_flush_tlb_all(void) +{ + unsigned long flags; + unsigned long old_ctx; + int entry; + + local_irq_save(flags); + /* Save old context and create impossible VPN2 value */ + old_ctx = read_c0_entryhi() & ASID_MASK; + write_c0_entrylo0(0); + write_c0_entrylo1(0); + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { + write_c0_entryhi(KSEG0 + (PAGE_SIZE << 1) * entry); + write_c0_index(entry); + tlb_write_indexed(); + } + write_c0_entryhi(old_ctx); + local_irq_restore(flags); +} + + +/* + * Use a bogus region of memory (starting at 0) to sanitize the TLB's. + * Use increments of the maximum page size (16MB), and check for duplicate + * entries before doing a given write. Then, when we're safe from collisions + * with the firmware, go back and give all the entries invalid addresses with + * the normal flush routine. + */ +void sb1_sanitize_tlb(void) +{ + int entry; + long addr = 0; + + long inc = 1<<24; /* 16MB */ + /* Save old context and create impossible VPN2 value */ + write_c0_entrylo0(0); + write_c0_entrylo1(0); + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { + do { + addr += inc; + write_c0_entryhi(addr); + tlb_probe(); + } while ((int)(read_c0_index()) >= 0); + write_c0_index(entry); + tlb_write_indexed(); + } + /* Now that we know we're safe from collisions, we can safely flush + the TLB with the "normal" routine. */ + local_flush_tlb_all(); +} + +void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end) +{ + struct mm_struct *mm = vma->vm_mm; + unsigned long flags; + int cpu; + + local_irq_save(flags); + cpu = smp_processor_id(); + if (cpu_context(cpu, mm) != 0) { + int size; + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + size = (size + 1) >> 1; + if (size <= (current_cpu_data.tlbsize/2)) { + int oldpid = read_c0_entryhi() & ASID_MASK; + int newpid = cpu_asid(cpu, mm); + + start &= (PAGE_MASK << 1); + end += ((PAGE_SIZE << 1) - 1); + end &= (PAGE_MASK << 1); + while (start < end) { + int idx; + + write_c0_entryhi(start | newpid); + start += (PAGE_SIZE << 1); + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + write_c0_entryhi(KSEG0 + (idx << (PAGE_SHIFT+1))); + if (idx < 0) + continue; + tlb_write_indexed(); + } + write_c0_entryhi(oldpid); + } else { + drop_mmu_context(mm, cpu); + } + } + local_irq_restore(flags); +} + +void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) +{ + unsigned long flags; + int size; + + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + size = (size + 1) >> 1; + + local_irq_save(flags); + if (size <= (current_cpu_data.tlbsize/2)) { + int pid = read_c0_entryhi(); + + start &= (PAGE_MASK << 1); + end += ((PAGE_SIZE << 1) - 1); + end &= (PAGE_MASK << 1); + + while (start < end) { + int idx; + + write_c0_entryhi(start); + start += (PAGE_SIZE << 1); + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + write_c0_entryhi(KSEG0 + (idx << (PAGE_SHIFT+1))); + if (idx < 0) + continue; + tlb_write_indexed(); + } + write_c0_entryhi(pid); + } else { + local_flush_tlb_all(); + } + local_irq_restore(flags); +} + +void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) +{ + unsigned long flags; + int cpu = smp_processor_id(); + + local_irq_save(flags); + if (cpu_context(cpu, vma->vm_mm) != 0) { + int oldpid, newpid, idx; + newpid = cpu_asid(cpu, vma->vm_mm); + page &= (PAGE_MASK << 1); + oldpid = read_c0_entryhi() & ASID_MASK; + write_c0_entryhi(page | newpid); + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + if(idx < 0) + goto finish; + /* Make sure all entries differ. */ + write_c0_entryhi(KSEG0+(idx<<(PAGE_SHIFT+1))); + tlb_write_indexed(); + finish: + write_c0_entryhi(oldpid); + } + local_irq_restore(flags); +} + +/* + * This one is only used for pages with the global bit set so we don't care + * much about the ASID. + */ +void local_flush_tlb_one(unsigned long page) +{ + unsigned long flags; + int oldpid, idx; + + local_irq_save(flags); + page &= (PAGE_MASK << 1); + oldpid = read_c0_entryhi() & 0xff; + write_c0_entryhi(page); + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + if (idx >= 0) { + /* Make sure all entries differ. */ + write_c0_entryhi(KSEG0+(idx<<(PAGE_SHIFT+1))); + tlb_write_indexed(); + } + write_c0_entryhi(oldpid); + + local_irq_restore(flags); +} + +/* All entries common to a mm share an asid. To effectively flush + these entries, we just bump the asid. */ +void local_flush_tlb_mm(struct mm_struct *mm) +{ + int cpu = smp_processor_id(); + if (cpu_context(cpu, mm) != 0) { + drop_mmu_context(mm, cpu); + } +} + +/* Stolen from mips32 routines */ + +void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) +{ + unsigned long flags; + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + int idx, pid; + + /* + * Handle debugger faulting in for debugee. + */ + if (current->active_mm != vma->vm_mm) + return; + + local_irq_save(flags); + + pid = read_c0_entryhi() & ASID_MASK; + address &= (PAGE_MASK << 1); + write_c0_entryhi(address | (pid)); + pgdp = pgd_offset(vma->vm_mm, address); + tlb_probe(); + pmdp = pmd_offset(pgdp, address); + idx = read_c0_index(); + ptep = pte_offset_map(pmdp, address); + write_c0_entrylo0(pte_val(*ptep++) >> 6); + write_c0_entrylo1(pte_val(*ptep) >> 6); + if (idx < 0) { + tlb_write_random(); + } else { + tlb_write_indexed(); + } + local_irq_restore(flags); +} + +/* + * This is called from loadmmu.c. We have to set up all the + * memory management function pointers, as well as initialize + * the caches and tlbs + */ +void sb1_tlb_init(void) +{ + u32 config1; + + write_c0_pagemask(PM_4K); + config1 = read_c0_config1(); + current_cpu_data.tlbsize = ((config1 >> 25) & 0x3f) + 1; + + /* + * We don't know what state the firmware left the TLB's in, so this is + * the ultra-conservative way to flush the TLB's and avoid machine + * check exceptions due to duplicate TLB entries + */ + sb1_sanitize_tlb(); + + memcpy((void *)KSEG0 + 0x080, except_vec1_sb1, 0x80); + flush_icache_range(KSEG0, KSEG0 + 0x80); +} --- linux-2.5.73/arch/mips64/mm/umap.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,221 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 Linus Torvalds - * Copyright (C) 1997 Miguel de Icaza - * Copyright (C) 2001 Ralf Baechle - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -static inline void remove_mapping_pte_range (pmd_t *pmd, unsigned long address, - unsigned long size) -{ - pte_t *pte; - unsigned long end; - - if (pmd_none (*pmd)) - return; - if (pmd_bad (*pmd)){ - printk ("remove_graphics_pte_range: bad pmd (%08lx)\n", - pmd_val (*pmd)); - pmd_clear (pmd); - return; - } - pte = pte_offset (pmd, address); - address &= ~PMD_MASK; - end = address + size; - if (end > PMD_SIZE) - end = PMD_SIZE; - do { - pte_t entry = *pte; - if (pte_present (entry)) - set_pte (pte, pte_modify (entry, PAGE_NONE)); - address += PAGE_SIZE; - pte++; - } while (address < end); - -} - -static inline void remove_mapping_pmd_range (pgd_t *pgd, unsigned long address, - unsigned long size) -{ - pmd_t *pmd; - unsigned long end; - - if (pgd_none (*pgd)) - return; - - if (pgd_bad (*pgd)){ - printk ("remove_graphics_pmd_range: bad pgd (%08lx)\n", - pgd_val (*pgd)); - pgd_clear (pgd); - return; - } - pmd = pmd_offset (pgd, address); - address &= ~PGDIR_MASK; - end = address + size; - if (end > PGDIR_SIZE) - end = PGDIR_SIZE; - do { - remove_mapping_pte_range (pmd, address, end - address); - address = (address + PMD_SIZE) & PMD_MASK; - pmd++; - } while (address < end); - -} - -/* - * This routine is called from the page fault handler to remove a - * range of active mappings at this point - */ -void remove_mapping (struct vm_area_struct *vma, struct task_struct *task, unsigned long start, - unsigned long end) -{ - unsigned long beg = start; - pgd_t *dir; - - down_write (&task->mm->mmap_sem); - dir = pgd_offset (task->mm, start); - flush_cache_range (vma, beg, end); - while (start < end){ - remove_mapping_pmd_range (dir, start, end - start); - start = (start + PGDIR_SIZE) & PGDIR_MASK; - dir++; - } - flush_tlb_range (vma, beg, end); - up_write (&task->mm->mmap_sem); -} - -EXPORT_SYMBOL(remove_mapping); - -void *vmalloc_uncached (unsigned long size) -{ - return __vmalloc (size, GFP_KERNEL | __GFP_HIGHMEM, - PAGE_KERNEL_UNCACHED); -} - -static inline void free_pte(pte_t page) -{ - if (pte_present(page)) { - unsigned long pfn = pte_pfn(page); - struct page *ptpage; - if (!pfn_valid(pfn)) - return; - ptpage = pfn_to_page(pfn); - if (PageReserved(ptpage)) - return; - __free_page(ptpage); - if (current->mm->rss <= 0) - return; - current->mm->rss--; - return; - } - swap_free(pte_to_swp_entry(page)); -} - -static inline void forget_pte(pte_t page) -{ - if (!pte_none(page)) { - printk("forget_pte: old mapping existed!\n"); - free_pte(page); - } -} - -/* - * maps a range of vmalloc()ed memory into the requested pages. the old - * mappings are removed. - */ -static inline void vmap_pte_range (pte_t *pte, unsigned long address, - unsigned long size, unsigned long vaddr) -{ - unsigned long end; - pgd_t *vdir; - pmd_t *vpmd; - pte_t *vpte; - - address &= ~PMD_MASK; - end = address + size; - if (end > PMD_SIZE) - end = PMD_SIZE; - do { - pte_t oldpage = *pte; - struct page * page; - pte_clear(pte); - - vdir = pgd_offset_k (vaddr); - vpmd = pmd_offset (vdir, vaddr); - vpte = pte_offset (vpmd, vaddr); - page = pte_page (*vpte); - - set_pte(pte, mk_pte(page, PAGE_USERIO)); - forget_pte(oldpage); - address += PAGE_SIZE; - vaddr += PAGE_SIZE; - pte++; - } while (address < end); -} - -static inline int vmap_pmd_range (pmd_t *pmd, unsigned long address, - unsigned long size, unsigned long vaddr) -{ - unsigned long end; - - address &= ~PGDIR_MASK; - end = address + size; - if (end > PGDIR_SIZE) - end = PGDIR_SIZE; - vaddr -= address; - do { - pte_t * pte = pte_alloc(current->mm, pmd, address); - if (!pte) - return -ENOMEM; - vmap_pte_range(pte, address, end - address, address + vaddr); - address = (address + PMD_SIZE) & PMD_MASK; - pmd++; - } while (address < end); - return 0; -} - -int vmap_page_range (struct vm_area_struct *vma, unsigned long from, unsigned long size, - unsigned long vaddr) -{ - int error = 0; - pgd_t * dir; - unsigned long beg = from; - unsigned long end = from + size; - - vaddr -= from; - dir = pgd_offset(current->mm, from); - flush_cache_range(vma, beg, end); - while (from < end) { - pmd_t *pmd = pmd_alloc(current->mm, dir, from); - error = -ENOMEM; - if (!pmd) - break; - error = vmap_pmd_range(pmd, from, end - from, vaddr + from); - if (error) - break; - from = (from + PGDIR_SIZE) & PGDIR_MASK; - dir++; - } - flush_tlb_range(vma, beg, end); - return error; -} --- linux-2.5.73/arch/mips64/sgi-ip22/ip22-berr.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,125 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1999, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 by Silicon Graphics - */ -#include -#include -#include - -#include -#include -#include -#include -#include - -extern asmlinkage void handle_ibe(void); -extern asmlinkage void handle_dbe(void); - -extern const struct exception_table_entry __start___dbe_table[]; -extern const struct exception_table_entry __stop___dbe_table[]; - -static inline unsigned long -search_one_table(const struct exception_table_entry *first, - const struct exception_table_entry *last, - unsigned long value) -{ - while (first <= last) { - const struct exception_table_entry *mid; - long diff; - - mid = (last - first) / 2 + first; - diff = mid->insn - value; - if (diff == 0) - return mid->nextinsn; - else if (diff < 0) - first = mid+1; - else - last = mid-1; - } - return 0; -} - -extern spinlock_t modlist_lock; - -static inline unsigned long -search_dbe_table(unsigned long addr) -{ - unsigned long ret = 0; - -#ifndef CONFIG_MODULES - /* There is only the kernel to search. */ - ret = search_one_table(__start___dbe_table, __stop___dbe_table-1, addr); - return ret; -#else - unsigned long flags; - - /* The kernel is the last "module" -- no need to treat it special. */ - struct module *mp; - struct archdata *ap; - - spin_lock_irqsave(&modlist_lock, flags); - for (mp = module_list; mp != NULL; mp = mp->next) { - if (!mod_member_present(mp, archdata_end) || - !mod_archdata_member_present(mp, struct archdata, - dbe_table_end)) - continue; - ap = (struct archdata *)(mod->archdata_start); - - if (ap->dbe_table_start == NULL || - !(mp->flags & (MOD_RUNNING | MOD_INITIALIZING))) - continue; - ret = search_one_table(ap->dbe_table_start, - ap->dbe_table_end - 1, addr); - if (ret) - break; - } - spin_unlock_irqrestore(&modlist_lock, flags); - return ret; -#endif -} - -void do_ibe(struct pt_regs *regs) -{ - printk("Got ibe at 0x%lx\n", regs->cp0_epc); - show_regs(regs); - dump_tlb_addr(regs->cp0_epc); - force_sig(SIGBUS, current); - while(1); -} - -void do_dbe(struct pt_regs *regs) -{ - unsigned long fixup; - - fixup = search_dbe_table(regs->cp0_epc); - if (fixup) { - long new_epc; - - new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc); - regs->cp0_epc = new_epc; - return; - } - - printk("Got dbe at 0x%lx\n", regs->cp0_epc); - show_regs(regs); - dump_tlb_all(); - while(1); - force_sig(SIGBUS, current); -} - -void __init -bus_error_init(void) -{ - int dummy; - - set_except_vector(6, handle_ibe); - set_except_vector(7, handle_dbe); - - /* At this time nothing uses the DBE protection mechanism on the - Indy, so this here is needed to make the kernel link. */ - get_dbe(dummy, (int *)KSEG0); -} --- linux-2.5.73/arch/mips64/sgi-ip22/ip22-hpc.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,104 +0,0 @@ -/* - * ip22-hpc.c: Routines for generic manipulation of the HPC controllers. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1998, 1999, 2001 Ralf Baechle - */ -#include -#include - -#include -#include -#include -#include - -#undef DEBUG_SGIHPC - -struct hpc3_regs *hpc3c0, *hpc3c1; -struct hpc3_miscregs *hpc3mregs; - -/* We need software copies of these because they are write only. */ -unsigned int sgi_hpc_write1, sgi_hpc_write2; - -/* Machine specific identifier knobs. */ -int sgi_has_ioc2 = 0; -int sgi_guiness = 0; -int sgi_boardid; - -void __init sgihpc_init(void) -{ - unsigned long sid, crev, brev; - - hpc3c0 = (struct hpc3_regs *) (KSEG1 + HPC3_CHIP0_PBASE); - hpc3c1 = (struct hpc3_regs *) (KSEG1 + HPC3_CHIP1_PBASE); - hpc3mregs = (struct hpc3_miscregs *) (KSEG1 + HPC3_MREGS_PBASE); - sid = hpc3mregs->sysid; - - sid &= 0xff; - crev = (sid & 0xe0) >> 5; - brev = (sid & 0x1e) >> 1; - -#ifdef DEBUG_SGIHPC - prom_printf("sgihpc_init: crev<%2x> brev<%2x>\n", crev, brev); - prom_printf("sgihpc_init: "); -#endif - - /* This test works now thanks to William J. Earl */ - if ((sid & 1) == 0 ) { -#ifdef DEBUG_SGIHPC - prom_printf("GUINESS "); -#endif - sgi_guiness = 1; - mips_machtype = MACH_SGI_INDY; - } else { -#ifdef DEBUG_SGIHPC - prom_printf("FULLHOUSE "); -#endif - mips_machtype = MACH_SGI_INDIGO2; - sgi_guiness = 0; - } - sgi_boardid = brev; - -#ifdef DEBUG_SGIHPC - prom_printf("sgi_boardid<%d> ", sgi_boardid); -#endif - - if(crev == 1) { - if((sid & 1) || (brev >= 2)) { -#ifdef DEBUG_SGIHPC - prom_printf("IOC2 "); -#endif - sgi_has_ioc2 = 1; - } else { -#ifdef DEBUG_SGIHPC - prom_printf("IOC1 revision 1 "); -#endif - } - } else { -#ifdef DEBUG_SGIHPC - prom_printf("IOC1 revision 0 "); -#endif - } -#ifdef DEBUG_SGIHPC - prom_printf("\n"); -#endif - - sgi_hpc_write1 = (HPC3_WRITE1_PRESET | - HPC3_WRITE1_KMRESET | - HPC3_WRITE1_ERESET | - HPC3_WRITE1_LC0OFF); - - sgi_hpc_write2 = (HPC3_WRITE2_EASEL | - HPC3_WRITE2_NTHRESH | - HPC3_WRITE2_TPSPEED | - HPC3_WRITE2_EPSEL | - HPC3_WRITE2_U0AMODE | - HPC3_WRITE2_U1AMODE); - - if(!sgi_guiness) - sgi_hpc_write1 |= HPC3_WRITE1_GRESET; - hpc3mregs->write1 = sgi_hpc_write1; - hpc3mregs->write2 = sgi_hpc_write2; - - hpc3c0->pbus_piocfgs[0][6] |= HPC3_PIOPCFG_HW; -} --- linux-2.5.73/arch/mips64/sgi-ip22/ip22-int.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,616 +0,0 @@ -/* - * indy_int.c: Routines for generic manipulation of the INT[23] ASIC - * found on INDY workstations.. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes - */ -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -/* - * Linux has a controller-independent x86 interrupt architecture. - * every controller has a 'controller-template', that is used - * by the main code to do the right thing. Each driver-visible - * interrupt source is transparently wired to the apropriate - * controller. Thus drivers need not be aware of the - * interrupt-controller. - * - * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC, - * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC. - * (IO-APICs assumed to be messaging to Pentium local-APICs) - * - * the code is designed to be easily extended with new/different - * interrupt controllers, without having to do assembly magic. - */ - -struct sgi_int2_regs *sgi_i2regs; -struct sgi_int3_regs *sgi_i3regs; -struct sgi_ioc_ints *ioc_icontrol; -struct sgi_ioc_timers *ioc_timers; -volatile unsigned char *ioc_tclear; - -static char lc0msk_to_irqnr[256]; -static char lc1msk_to_irqnr[256]; -static char lc2msk_to_irqnr[256]; -static char lc3msk_to_irqnr[256]; - -extern asmlinkage void indyIRQ(void); - -#ifdef CONFIG_REMOTE_DEBUG -extern void rs_kgdb_hook(int); -#endif - -unsigned long spurious_count = 0; - -/* Local IRQ's are layed out logically like this: - * - * 0 --> 7 == local 0 interrupts - * 8 --> 15 == local 1 interrupts - * 16 --> 23 == vectored level 2 interrupts - * 24 --> 31 == vectored level 3 interrupts (not used) - */ -void disable_local_irq(unsigned int irq_nr) -{ - unsigned long flags; - - save_and_cli(flags); - switch(irq_nr) { - case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: - ioc_icontrol->imask0 &= ~(1 << irq_nr); - break; - - case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15: - ioc_icontrol->imask1 &= ~(1 << (irq_nr - 8)); - break; - - case 16: case 17: case 18: case 19: case 20: case 21: case 22: case 23: - ioc_icontrol->cmeimask0 &= ~(1 << (irq_nr - 16)); - break; - - default: - /* This way we'll see if anyone would ever want vectored - * level 3 interrupts. Highly unlikely. - */ - printk("Yeeee, got passed irq_nr %d at disable_irq\n", irq_nr); - panic("INVALID IRQ level!"); - }; - restore_flags(flags); -} - -void enable_local_irq(unsigned int irq_nr) -{ - unsigned long flags; - save_and_cli(flags); - switch(irq_nr) { - case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: - ioc_icontrol->imask0 |= (1 << irq_nr); - break; - - case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15: - ioc_icontrol->imask1 |= (1 << (irq_nr - 8)); - break; - - case 16: case 17: case 18: case 19: case 20: case 21: case 22: case 23: - enable_local_irq(7); - ioc_icontrol->cmeimask0 |= (1 << (irq_nr - 16)); - break; - - default: - printk("Yeeee, got passed irq_nr %d at disable_irq\n", irq_nr); - panic("INVALID IRQ level!"); - }; - restore_flags(flags); -} - -void disable_gio_irq(unsigned int irq_nr) -{ - /* XXX TODO XXX */ -} - -void enable_gio_irq(unsigned int irq_nr) -{ - /* XXX TODO XXX */ -} - -void disable_hpcdma_irq(unsigned int irq_nr) -{ - /* XXX TODO XXX */ -} - -void enable_hpcdma_irq(unsigned int irq_nr) -{ - /* XXX TODO XXX */ -} - -void disable_irq(unsigned int irq_nr) -{ - unsigned int n = irq_nr; - if(n >= SGINT_END) { - printk("whee, invalid irq_nr %d\n", irq_nr); - panic("IRQ, you lose..."); - } - if(n >= SGINT_LOCAL0 && n < SGINT_GIO) { - disable_local_irq(n - SGINT_LOCAL0); - } else if(n >= SGINT_GIO && n < SGINT_HPCDMA) { - disable_gio_irq(n - SGINT_GIO); - } else if(n >= SGINT_HPCDMA && n < SGINT_END) { - disable_hpcdma_irq(n - SGINT_HPCDMA); - } else { - panic("how did I get here?"); - } -} - -void enable_irq(unsigned int irq_nr) -{ - unsigned int n = irq_nr; - if(n >= SGINT_END) { - printk("whee, invalid irq_nr %d\n", irq_nr); - panic("IRQ, you lose..."); - } - if(n >= SGINT_LOCAL0 && n < SGINT_GIO) { - enable_local_irq(n - SGINT_LOCAL0); - } else if(n >= SGINT_GIO && n < SGINT_HPCDMA) { - enable_gio_irq(n - SGINT_GIO); - } else if(n >= SGINT_HPCDMA && n < SGINT_END) { - enable_hpcdma_irq(n - SGINT_HPCDMA); - } else { - panic("how did I get here?"); - } -} - -#if 0 -/* - * Currently unused. - */ -static void local_unex(int irq, void *data, struct pt_regs *regs) -{ - printk("Whee: unexpected local IRQ at %08lx\n", - (unsigned long) regs->cp0_epc); - printk("DUMP: stat0<%x> stat1<%x> vmeistat<%x>\n", - ioc_icontrol->istat0, ioc_icontrol->istat1, - ioc_icontrol->vmeistat); -} -#endif - -static struct irqaction *local_irq_action[24] = { - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL -}; - -int setup_indy_irq(int irq, struct irqaction * new) -{ - printk("setup_indy_irq: Yeee, don't know how to setup irq<%d> for %s %p\n", - irq, new->name, new->handler); - return 0; -} - -static struct irqaction r4ktimer_action = { - NULL, 0, 0, "R4000 timer/counter", NULL, NULL, -}; - -static struct irqaction indy_berr_action = { - NULL, 0, 0, "IP22 Bus Error", NULL, NULL, -}; - -static struct irqaction *irq_action[16] = { - NULL, NULL, NULL, NULL, - NULL, NULL, &indy_berr_action, &r4ktimer_action, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL -}; - -int show_interrupts(struct seq_file *p, void *v) -{ - int i; - int num = 0; - struct irqaction * action; - unsigned long flags; - - for (i = 0 ; i < 16 ; i++, num++) { - local_irq_save(flags); - action = irq_action[i]; - if (!action) - goto skip_1; - seq_printf(p, "%2d: %8d %c %s", - num, kstat_cpu(0).irqs[num], - (action->flags & SA_INTERRUPT) ? '+' : ' ', - action->name); - for (action=action->next; action; action = action->next) { - seq_printf(p, ",%s %s", - (action->flags & SA_INTERRUPT) ? " +" : "", - action->name); - } - seq_puts(p, " [on-chip]\n"); -skip_1: - local_irq_restore(flags); - } - for (i = 0 ; i < 24 ; i++, num++) { - local_irq_save(flags); - action = local_irq_action[i]; - if (!action) - goto skip_2; - seq_printf(p, "%2d: %8d %c %s", - num, kstat_cpu(0).irqs[num], - (action->flags & SA_INTERRUPT) ? '+' : ' ', - action->name); - for (action=action->next; action; action = action->next) { - seq_printf(p, ",%s %s", - (action->flags & SA_INTERRUPT) ? " +" : "", - action->name); - } - seq_puts(p, " [local]\n"); -skip_2: - local_irq_restore(flags); - } - return 0; -} - -/* - * do_IRQ handles IRQ's that have been installed without the - * SA_INTERRUPT flag: it uses the full signal-handling return - * and runs with other interrupts enabled. All relatively slow - * IRQ's should use this format: notably the keyboard/timer - * routines. - */ -asmlinkage void do_IRQ(int irq, struct pt_regs * regs) -{ - struct irqaction *action; - int do_random, cpu; - - cpu = smp_processor_id(); - irq_enter(cpu, irq); - kstat_cpu(0).irqs[irq]++; - - panic(KERN_DEBUG "Got irq %d, press a key.", irq); - - /* - * mask and ack quickly, we don't want the irq controller - * thinking we're snobs just because some other CPU has - * disabled global interrupts (we have already done the - * INT_ACK cycles, it's too late to try to pretend to the - * controller that we aren't taking the interrupt). - * - * Commented out because we've already done this in the - * machinespecific part of the handler. It's reasonable to - * do this here in a highlevel language though because that way - * we could get rid of a good part of duplicated code ... - */ - /* mask_and_ack_irq(irq); */ - - action = *(irq + irq_action); - if (action) { - if (!(action->flags & SA_INTERRUPT)) - local_irq_enable(); - action = *(irq + irq_action); - do_random = 0; - do { - do_random |= action->flags; - action->handler(irq, action->dev_id, regs); - action = action->next; - } while (action); - if (do_random & SA_SAMPLE_RANDOM) - add_interrupt_randomness(irq); - local_irq_disable(); - } - irq_exit(cpu, irq); - - /* unmasking and bottom half handling is done magically for us. */ -} - -int request_local_irq(unsigned int lirq, void (*func)(int, void *, struct pt_regs *), - unsigned long iflags, const char *dname, void *devid) -{ - struct irqaction *action; - - lirq -= SGINT_LOCAL0; - if(lirq >= 24 || !func) - return -EINVAL; - - action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL); - if(!action) - return -ENOMEM; - - action->handler = func; - action->flags = iflags; - action->mask = 0; - action->name = dname; - action->dev_id = devid; - action->next = 0; - local_irq_action[lirq] = action; - enable_irq(lirq + SGINT_LOCAL0); - return 0; -} - -void free_local_irq(unsigned int lirq, void *dev_id) -{ - struct irqaction *action; - - lirq -= SGINT_LOCAL0; - if(lirq >= 24) { - printk("Aieee: trying to free bogus local irq %d\n", - lirq + SGINT_LOCAL0); - return; - } - action = local_irq_action[lirq]; - local_irq_action[lirq] = NULL; - disable_irq(lirq + SGINT_LOCAL0); - kfree(action); -} - -int request_irq(unsigned int irq, - void (*handler)(int, void *, struct pt_regs *), - unsigned long irqflags, - const char * devname, - void *dev_id) -{ - int retval; - struct irqaction * action; - - if (irq >= SGINT_END) - return -EINVAL; - if (!handler) - return -EINVAL; - - if((irq >= SGINT_LOCAL0) && (irq < SGINT_GIO)) - return request_local_irq(irq, handler, irqflags, devname, dev_id); - - action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL); - if (!action) - return -ENOMEM; - - action->handler = handler; - action->flags = irqflags; - action->mask = 0; - action->name = devname; - action->next = NULL; - action->dev_id = dev_id; - - retval = setup_indy_irq(irq, action); - - if (retval) - kfree(action); - return retval; -} - -void free_irq(unsigned int irq, void *dev_id) -{ - struct irqaction * action, **p; - unsigned long flags; - - if (irq >= SGINT_END) { - printk("Trying to free IRQ%d\n",irq); - return; - } - if((irq >= SGINT_LOCAL0) && (irq < SGINT_GIO)) { - free_local_irq(irq, dev_id); - return; - } - for (p = irq + irq_action; (action = *p) != NULL; p = &action->next) { - if (action->dev_id != dev_id) - continue; - - /* Found it - now free it */ - save_and_cli(flags); - *p = action->next; - restore_flags(flags); - kfree(action); - return; - } - printk("Trying to free free IRQ%d\n",irq); -} - -void indy_local0_irqdispatch(struct pt_regs *regs) -{ - struct irqaction *action; - unsigned char mask = ioc_icontrol->istat0; - unsigned char mask2 = 0; - int irq, cpu = smp_processor_id();; - - mask &= ioc_icontrol->imask0; - if(mask & ISTAT0_LIO2) { - mask2 = ioc_icontrol->vmeistat; - mask2 &= ioc_icontrol->cmeimask0; - irq = lc2msk_to_irqnr[mask2]; - action = local_irq_action[irq]; - } else { - irq = lc0msk_to_irqnr[mask]; - action = local_irq_action[irq]; - } - - irq_enter(cpu, irq); - kstat_cpu(0).irqs[irq + 16]++; - action->handler(irq, action->dev_id, regs); - irq_exit(cpu, irq); -} - -void indy_local1_irqdispatch(struct pt_regs *regs) -{ - struct irqaction *action; - unsigned char mask = ioc_icontrol->istat1; - unsigned char mask2 = 0; - int irq, cpu = smp_processor_id();; - - mask &= ioc_icontrol->imask1; - if(mask & ISTAT1_LIO3) { - printk("WHee: Got an LIO3 irq, winging it...\n"); - mask2 = ioc_icontrol->vmeistat; - mask2 &= ioc_icontrol->cmeimask1; - irq = lc3msk_to_irqnr[ioc_icontrol->vmeistat]; - action = local_irq_action[irq]; - } else { - irq = lc1msk_to_irqnr[mask]; - action = local_irq_action[irq]; - } - irq_enter(cpu, irq); - kstat_cpu(0).irqs[irq + 24]++; - action->handler(irq, action->dev_id, regs); - irq_exit(cpu, irq); -} - -void indy_buserror_irq(struct pt_regs *regs) -{ - int cpu = smp_processor_id(); - int irq = 6; - - irq_enter(cpu, irq); - kstat_cpu(0).irqs[irq]++; - printk("Got a bus error IRQ, shouldn't happen yet\n"); - show_regs(regs); - printk("Spinning...\n"); - while(1); - irq_exit(cpu, irq); -} - -/* Misc. crap just to keep the kernel linking... */ -unsigned long probe_irq_on (void) -{ - return 0; -} - -int probe_irq_off (unsigned long irqs) -{ - return 0; -} - -static inline void sgint_init(void) -{ - int i; -#ifdef CONFIG_REMOTE_DEBUG - char *ctype; -#endif - - sgi_i2regs = (struct sgi_int2_regs *) (KSEG1 + SGI_INT2_BASE); - sgi_i3regs = (struct sgi_int3_regs *) (KSEG1 + SGI_INT3_BASE); - - /* Init local mask --> irq tables. */ - for(i = 0; i < 256; i++) { - if(i & 0x80) { - lc0msk_to_irqnr[i] = 7; - lc1msk_to_irqnr[i] = 15; - lc2msk_to_irqnr[i] = 23; - lc3msk_to_irqnr[i] = 31; - } else if(i & 0x40) { - lc0msk_to_irqnr[i] = 6; - lc1msk_to_irqnr[i] = 14; - lc2msk_to_irqnr[i] = 22; - lc3msk_to_irqnr[i] = 30; - } else if(i & 0x20) { - lc0msk_to_irqnr[i] = 5; - lc1msk_to_irqnr[i] = 13; - lc2msk_to_irqnr[i] = 21; - lc3msk_to_irqnr[i] = 29; - } else if(i & 0x10) { - lc0msk_to_irqnr[i] = 4; - lc1msk_to_irqnr[i] = 12; - lc2msk_to_irqnr[i] = 20; - lc3msk_to_irqnr[i] = 28; - } else if(i & 0x08) { - lc0msk_to_irqnr[i] = 3; - lc1msk_to_irqnr[i] = 11; - lc2msk_to_irqnr[i] = 19; - lc3msk_to_irqnr[i] = 27; - } else if(i & 0x04) { - lc0msk_to_irqnr[i] = 2; - lc1msk_to_irqnr[i] = 10; - lc2msk_to_irqnr[i] = 18; - lc3msk_to_irqnr[i] = 26; - } else if(i & 0x02) { - lc0msk_to_irqnr[i] = 1; - lc1msk_to_irqnr[i] = 9; - lc2msk_to_irqnr[i] = 17; - lc3msk_to_irqnr[i] = 25; - } else if(i & 0x01) { - lc0msk_to_irqnr[i] = 0; - lc1msk_to_irqnr[i] = 8; - lc2msk_to_irqnr[i] = 16; - lc3msk_to_irqnr[i] = 24; - } else { - lc0msk_to_irqnr[i] = 0; - lc1msk_to_irqnr[i] = 0; - lc2msk_to_irqnr[i] = 0; - lc3msk_to_irqnr[i] = 0; - } - } - - /* Indy uses an INT3, Indigo2 uses an INT2 */ - if (sgi_guiness) { - ioc_icontrol = &sgi_i3regs->ints; - ioc_timers = &sgi_i3regs->timers; - ioc_tclear = &sgi_i3regs->tclear; - } else { - ioc_icontrol = &sgi_i2regs->ints; - ioc_timers = &sgi_i2regs->timers; - ioc_tclear = &sgi_i2regs->tclear; - } - - /* Mask out all interrupts. */ - ioc_icontrol->imask0 = 0; - ioc_icontrol->imask1 = 0; - ioc_icontrol->cmeimask0 = 0; - ioc_icontrol->cmeimask1 = 0; - - /* Now safe to set the exception vector. */ - set_except_vector(0, indyIRQ); - -#ifdef CONFIG_REMOTE_DEBUG - ctype = prom_getcmdline(); - for(i = 0; i < strlen(ctype); i++) { - if(ctype[i]=='k' && ctype[i+1]=='g' && - ctype[i+2]=='d' && ctype[i+3]=='b' && - ctype[i+4]=='=' && ctype[i+5]=='t' && - ctype[i+6]=='t' && ctype[i+7]=='y' && - ctype[i+8]=='d' && - (ctype[i+9] == '1' || ctype[i+9] == '2')) { - printk("KGDB: Using serial line /dev/ttyd%d for " - "session\n", (ctype[i+9] - '0')); - if(ctype[i+9]=='1') - rs_kgdb_hook(1); - else if(ctype[i+9]=='2') - rs_kgdb_hook(0); - else { - printk("KGDB: whoops bogon tty line " - "requested, disabling session\n"); - } - - } - } -#endif -} - -void __init init_IRQ(void) -{ - sgint_init(); -} --- linux-2.5.73/arch/mips64/sgi-ip22/ip22-irq.S 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,128 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * indyIRQ.S: Interrupt exception dispatch code for FullHouse and - * Guiness. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include -#include -#include - -/* A lot of complication here is taken away because: - * - * 1) We handle one interrupt and return, sitting in a loop and moving across - * all the pending IRQ bits in the cause register is _NOT_ the answer, the - * common case is one pending IRQ so optimize in that direction. - * - * 2) We need not check against bits in the status register IRQ mask, that - * would make this routine slow as hell. - * - * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in - * between like BSD spl() brain-damage. - * - * Furthermore, the IRQs on the INDY look basically (barring software IRQs - * which we don't use at all) like: - * - * MIPS IRQ Source - * -------- ------ - * 0 Software (ignored) - * 1 Software (ignored) - * 2 Local IRQ level zero - * 3 Local IRQ level one - * 4 8254 Timer zero - * 5 8254 Timer one - * 6 Bus Error - * 7 R4k timer (what we use) - * - * We handle the IRQ according to _our_ priority which is: - * - * Highest ---- R4k Timer - * Local IRQ zero - * Local IRQ one - * Bus Error - * 8254 Timer zero - * Lowest ---- 8254 Timer one - * - * then we just return, if multiple IRQs are pending then we will just take - * another exception, big deal. - */ - - .text - .set noreorder - .set noat - .align 5 - NESTED(indyIRQ, PT_SIZE, sp) - SAVE_ALL - CLI - .set at - mfc0 s0, CP0_CAUSE # get irq mask - - /* First we check for r4k counter/timer IRQ. */ - andi a0, s0, CAUSEF_IP7 - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP2 # delay slot, check local level zero - - /* Wheee, a timer interrupt. */ - move a0, sp - jal indy_timer_interrupt - nop # delay slot - - j ret_from_irq - nop # delay slot - -1: - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP3 # delay slot, check local level one - - /* Wheee, local level zero interrupt. */ - jal indy_local0_irqdispatch - move a0, sp # delay slot - - j ret_from_irq - nop # delay slot - -1: - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP6 # delay slot, check bus error - - /* Wheee, local level one interrupt. */ - move a0, sp - jal indy_local1_irqdispatch - nop - - j ret_from_irq - nop - -1: - beq a0, zero, 1f - nop - - /* Wheee, an asynchronous bus error... */ - move a0, sp - jal indy_buserror_irq - nop - - j ret_from_irq - nop - -1: - /* Here by mistake? This is possible, what can happen - * is that by the time we take the exception the IRQ - * pin goes low, so just leave if this is the case. - */ - andi a0, s0, (CAUSEF_IP4 | CAUSEF_IP5) - beq a0, zero, 1f - - /* Must be one of the 8254 timers... */ - move a0, sp - jal indy_8254timer_irq - nop -1: - j ret_from_irq - nop - END(indyIRQ) --- linux-2.5.73/arch/mips64/sgi-ip22/ip22-mc.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,158 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 2001 Ralf Baechle (ralf@gnu.org) - */ -#include -#include - -#include -#include -#include -#include - -/* #define DEBUG_SGIMC */ - -struct sgimc_misc_ctrl *mcmisc_regs; -u32 *rpsscounter; -struct sgimc_dma_ctrl *dmactrlregs; - -static inline char *mconfig_string(unsigned long val) -{ - switch(val & SGIMC_MCONFIG_RMASK) { - case SGIMC_MCONFIG_FOURMB: - return "4MB"; - - case SGIMC_MCONFIG_EIGHTMB: - return "8MB"; - - case SGIMC_MCONFIG_SXTEENMB: - return "16MB"; - - case SGIMC_MCONFIG_TTWOMB: - return "32MB"; - - case SGIMC_MCONFIG_SFOURMB: - return "64MB"; - - case SGIMC_MCONFIG_OTEIGHTMB: - return "128MB"; - - default: - return "wheee, unknown"; - }; -} - -void __init sgimc_init(void) -{ - unsigned long tmpreg; - - mcmisc_regs = (struct sgimc_misc_ctrl *)(KSEG1+0x1fa00000); - rpsscounter = (u32 *) (KSEG1 + 0x1fa01004); - dmactrlregs = (struct sgimc_dma_ctrl *) (KSEG1+0x1fa02000); - - printk("MC: SGI memory controller Revision %d\n", - (int) mcmisc_regs->systemid & SGIMC_SYSID_MASKREV); - -#if 0 /* XXX Until I figure out what this bit really indicates XXX */ - /* XXX Is this systemid bit reliable? */ - if(mcmisc_regs->systemid & SGIMC_SYSID_EPRESENT) { - EISA_bus = 1; - printk("with EISA\n"); - } else { - EISA_bus = 0; - printk("no EISA\n"); - } -#endif - -#ifdef DEBUG_SGIMC - prom_printf("sgimc_init: memconfig0<%s> mconfig1<%s>\n", - mconfig_string(mcmisc_regs->mconfig0), - mconfig_string(mcmisc_regs->mconfig1)); - - prom_printf("mcdump: cpuctrl0<%08lx> cpuctrl1<%08lx>\n", - mcmisc_regs->cpuctrl0, mcmisc_regs->cpuctrl1); - prom_printf("mcdump: divider<%08lx>, gioparm<%04x>\n", - mcmisc_regs->divider, mcmisc_regs->gioparm); -#endif - - /* Place the MC into a known state. This must be done before - * interrupts are first enabled etc. - */ - - /* Step 1: The CPU/GIO error status registers will not latch - * up a new error status until the register has been - * cleared by the cpu. These status registers are - * cleared by writing any value to them. - */ - mcmisc_regs->cstat = mcmisc_regs->gstat = 0; - - /* Step 2: Enable all parity checking in cpu control register - * zero. - */ - tmpreg = mcmisc_regs->cpuctrl0; - tmpreg |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM | - SGIMC_CCTRL0_R4KNOCHKPARR); - mcmisc_regs->cpuctrl0 = tmpreg; - - /* Step 3: Setup the MC write buffer depth, this is controlled - * in cpu control register 1 in the lower 4 bits. - */ - tmpreg = mcmisc_regs->cpuctrl1; - tmpreg &= ~0xf; - tmpreg |= 0xd; - mcmisc_regs->cpuctrl1 = tmpreg; - - /* Step 4: Initialize the RPSS divider register to run as fast - * as it can correctly operate. The register is laid - * out as follows: - * - * ---------------------------------------- - * | RESERVED | INCREMENT | DIVIDER | - * ---------------------------------------- - * 31 16 15 8 7 0 - * - * DIVIDER determines how often a 'tick' happens, - * INCREMENT determines by how the RPSS increment - * registers value increases at each 'tick'. Thus, - * for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101 - */ - mcmisc_regs->divider = 0x101; - - /* Step 5: Initialize GIO64 arbitrator configuration register. - * - * NOTE: If you dork with startup code the HPC init code in - * sgihpc_init() must run before us because of how we - * need to know Guiness vs. FullHouse and the board - * revision on this machine. You have been warned. - */ - - /* First the basic invariants across all gio64 implementations. */ - tmpreg = SGIMC_GIOPARM_HPC64; /* All 1st HPC's interface at 64bits. */ - tmpreg |= SGIMC_GIOPARM_ONEBUS; /* Only one physical GIO bus exists. */ - - if(sgi_guiness) { - /* Guiness specific settings. */ - tmpreg |= SGIMC_GIOPARM_EISA64; /* MC talks to EISA at 64bits */ - tmpreg |= SGIMC_GIOPARM_MASTEREISA; /* EISA bus can act as master */ - } else { - /* Fullhouse specific settings. */ - if(sgi_boardid < 2) { - tmpreg |= SGIMC_GIOPARM_HPC264; /* 2nd HPC at 64bits */ - tmpreg |= SGIMC_GIOPARM_PLINEEXP0; /* exp0 pipelines */ - tmpreg |= SGIMC_GIOPARM_MASTEREXP1;/* exp1 masters */ - tmpreg |= SGIMC_GIOPARM_RTIMEEXP0; /* exp0 is realtime */ - } else { - tmpreg |= SGIMC_GIOPARM_HPC264; /* 2nd HPC 64bits */ - tmpreg |= SGIMC_GIOPARM_PLINEEXP0; /* exp[01] pipelined */ - tmpreg |= SGIMC_GIOPARM_PLINEEXP1; - tmpreg |= SGIMC_GIOPARM_MASTEREISA;/* EISA masters */ - /* someone forgot this poor little guy... */ - tmpreg |= SGIMC_GIOPARM_GFX64; /* GFX at 64 bits */ - } - } - mcmisc_regs->gioparm = tmpreg; /* poof */ -} --- linux-2.5.73/arch/mips64/sgi-ip22/ip22-reset.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,238 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Reset an IP22. - * - * Copyright (C) 1997, 1998, 1999, 2001 by Ralf Baechle - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Just powerdown if init hasn't done after POWERDOWN_TIMEOUT seconds. - * I'm not shure if this feature is a good idea, for now it's here just to - * make the power button make behave just like under IRIX. - */ -#define POWERDOWN_TIMEOUT 120 - -/* - * Blink frequency during reboot grace period and when paniced. - */ -#define POWERDOWN_FREQ (HZ / 4) -#define PANIC_FREQ (HZ / 8) - -static unsigned char sgi_volume; - -static struct timer_list power_timer, blink_timer, debounce_timer, volume_timer; -static int shuting_down, has_paniced; - -void machine_restart(char *command) __attribute__((noreturn)); -void machine_halt(void) __attribute__((noreturn)); -void machine_power_off(void) __attribute__((noreturn)); - -/* XXX How to pass the reboot command to the firmware??? */ -void machine_restart(char *command) -{ - if (shuting_down) - machine_power_off(); - ArcReboot(); -} - -void machine_halt(void) -{ - if (shuting_down) - machine_power_off(); - ArcEnterInteractiveMode(); -} - -void machine_power_off(void) -{ - struct indy_clock *clock = (struct indy_clock *)INDY_CLOCK_REGS; - - cli(); - - clock->cmd |= 0x08; /* Disable watchdog */ - clock->whsec = 0; - clock->wsec = 0; - - while(1) { - hpc3mregs->panel=0xfe; - /* Good bye cruel world ... */ - - /* If we're still running, we probably got sent an alarm - interrupt. Read the flag to clear it. */ - clock->halarm; - } -} - -static void power_timeout(unsigned long data) -{ - machine_power_off(); -} - -static void blink_timeout(unsigned long data) -{ - /* XXX Fix this for Fullhouse */ - sgi_hpc_write1 ^= (HPC3_WRITE1_LC0OFF|HPC3_WRITE1_LC1OFF); - hpc3mregs->write1 = sgi_hpc_write1; - - mod_timer(&blink_timer, jiffies+data); -} - -static void debounce(unsigned long data) -{ - del_timer(&debounce_timer); - if (ioc_icontrol->istat1 & 2) { /* Interrupt still being sent. */ - debounce_timer.expires = jiffies + 5; /* 0.05s */ - add_timer(&debounce_timer); - - hpc3mregs->panel = 0xf3; - - return; - } - - if (has_paniced) - ArcReboot(); - - enable_irq(9); -} - -static inline void power_button(void) -{ - if (has_paniced) - return; - - if (shuting_down || kill_proc(1, SIGINT, 1)) { - /* No init process or button pressed twice. */ - machine_power_off(); - } - - shuting_down = 1; - blink_timer.data = POWERDOWN_FREQ; - blink_timeout(POWERDOWN_FREQ); - - init_timer(&power_timer); - power_timer.function = power_timeout; - power_timer.expires = jiffies + POWERDOWN_TIMEOUT * HZ; - add_timer(&power_timer); -} - -void inline ip22_volume_set(unsigned char volume) -{ - sgi_volume = volume; - - hpc3c0->pbus_extregs[2][0] = sgi_volume; - hpc3c0->pbus_extregs[2][1] = sgi_volume; -} - -void inline ip22_volume_get(unsigned char *volume) -{ - *volume = sgi_volume; -} - -static inline void volume_up_button(unsigned long data) -{ - del_timer(&volume_timer); - - if (sgi_volume < 0xff) - sgi_volume++; - - hpc3c0->pbus_extregs[2][0] = sgi_volume; - hpc3c0->pbus_extregs[2][1] = sgi_volume; - - if (ioc_icontrol->istat1 & 2) { - volume_timer.expires = jiffies + 1; - add_timer(&volume_timer); - } - -} - -static inline void volume_down_button(unsigned long data) -{ - del_timer(&volume_timer); - - if (sgi_volume > 0) - sgi_volume--; - - hpc3c0->pbus_extregs[2][0] = sgi_volume; - hpc3c0->pbus_extregs[2][1] = sgi_volume; - - if (ioc_icontrol->istat1 & 2) { - volume_timer.expires = jiffies + 1; - add_timer(&volume_timer); - } -} - -static void panel_int(int irq, void *dev_id, struct pt_regs *regs) -{ - unsigned int buttons; - - buttons = hpc3mregs->panel; - hpc3mregs->panel = 3; /* power_interrupt | power_supply_on */ - - if (ioc_icontrol->istat1 & 2) { /* Wait until interrupt goes away */ - disable_irq(9); - init_timer(&debounce_timer); - debounce_timer.function = debounce; - debounce_timer.expires = jiffies + 5; - add_timer(&debounce_timer); - } - - if (!(buttons & 2)) /* Power button was pressed */ - power_button(); - if (!(buttons & 0x40)) { /* Volume up button was pressed */ - init_timer(&volume_timer); - volume_timer.function = volume_up_button; - volume_timer.expires = jiffies + 1; - add_timer(&volume_timer); - } - if (!(buttons & 0x10)) { /* Volume down button was pressed */ - init_timer(&volume_timer); - volume_timer.function = volume_down_button; - volume_timer.expires = jiffies + 1; - add_timer(&volume_timer); - } -} - -static int panic_event(struct notifier_block *this, unsigned long event, - void *ptr) -{ - if (has_paniced) - return NOTIFY_DONE; - has_paniced = 1; - - blink_timer.data = PANIC_FREQ; - blink_timeout(PANIC_FREQ); - - return NOTIFY_DONE; -} - -static struct notifier_block panic_block = { - panic_event, - NULL, - 0 -}; - -void ip22_reboot_setup(void) -{ - static int setup_done; - - if (setup_done) - return; - setup_done = 1; - - request_irq(9, panel_int, 0, "Front Panel", NULL); - init_timer(&blink_timer); - blink_timer.function = blink_timeout; - notifier_chain_register(&panic_notifier_list, &panic_block); -} --- linux-2.5.73/arch/mips64/sgi-ip22/ip22-rtc.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,36 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * RTC routines for Indy style attached Dallas chip. - * - * Copyright (C) 1998, 2001 by Ralf Baechle - */ -#include -#include - -static unsigned char indy_rtc_read_data(unsigned long addr) -{ - volatile unsigned int *rtcregs = (void *)INDY_CLOCK_REGS; - - return rtcregs[addr]; -} - -static void indy_rtc_write_data(unsigned char data, unsigned long addr) -{ - volatile unsigned int *rtcregs = (void *)INDY_CLOCK_REGS; - - rtcregs[addr] = data; -} - -static int indy_rtc_bcd_mode(void) -{ - return 0; -} - -struct rtc_ops indy_rtc_ops = { - &indy_rtc_read_data, - &indy_rtc_write_data, - &indy_rtc_bcd_mode -}; --- linux-2.5.73/arch/mips64/sgi-ip22/ip22-sc.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,164 +0,0 @@ -/* - * indy_sc.c: Indy cache management functions. - * - * Copyright (C) 1997 Ralf Baechle (ralf@gnu.org), - * derived from r4xx0.c by David S. Miller (dm@engr.sgi.com). - */ -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -/* Secondary cache size in bytes, if present. */ -static unsigned long scache_size; - -#undef DEBUG_CACHE - -#define SC_SIZE 0x00080000 -#define SC_LINE 32 -#define CI_MASK (SC_SIZE - SC_LINE) -#define SC_INDEX(n) ((n) & CI_MASK) - -static inline void indy_sc_wipe(unsigned long first, unsigned long last) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - "or\t%0, %4\t\t\t# first line to flush\n\t" - "or\t%1, %4\t\t\t# last line to flush\n" - "1:\tsw $0, 0(%0)\n\t" - "bne\t%0, %1, 1b\n\t" - "daddu\t%0, 32\n\t" - ".set reorder" - : "=r" (first), "=r" (last) - : "0" (first), "1" (last), "r" (0x9000000080000000) - : "$1"); -} - -static void indy_sc_wback_invalidate(unsigned long addr, unsigned long size) -{ - unsigned long first_line, last_line; - unsigned int flags; - -#ifdef DEBUG_CACHE - printk("indy_sc_wback_invalidate[%08lx,%08lx]", addr, size); -#endif - - if (!size) - return; - - /* Which lines to flush? */ - first_line = SC_INDEX(addr); - last_line = SC_INDEX(addr + size - 1); - - local_irq_save(flags); - if (first_line <= last_line) { - indy_sc_wipe(first_line, last_line); - goto out; - } - - indy_sc_wipe(first_line, SC_SIZE - SC_LINE); - indy_sc_wipe(0, last_line); -out: - local_irq_restore(flags); -} - -static void inline indy_sc_enable(void) -{ -#ifdef DEBUG_CACHE - printk("Enabling R4600 SCACHE\n"); -#endif - *(volatile unsigned char *) 0x9000000080000000 = 0; -} - -static void indy_sc_disable(void) -{ -#ifdef DEBUG_CACHE - printk("Disabling R4600 SCACHE\n"); -#endif - *(volatile unsigned short *) 0x9000000080000000 = 0; -} - -static inline __init int indy_sc_probe(void) -{ - volatile u32 *cpu_control; - unsigned short cmd = 0xc220; - unsigned long data = 0; - int i, n; - -#ifdef __MIPSEB__ - cpu_control = (volatile u32 *) KSEG1ADDR(0x1fa00034); -#else - cpu_control = (volatile u32 *) KSEG1ADDR(0x1fa00030); -#endif -#define DEASSERT(bit) (*(cpu_control) &= (~(bit))) -#define ASSERT(bit) (*(cpu_control) |= (bit)) -#define DELAY for(n = 0; n < 100000; n++) __asm__ __volatile__("") - DEASSERT(SGIMC_EEPROM_PRE); - DEASSERT(SGIMC_EEPROM_SDATAO); - DEASSERT(SGIMC_EEPROM_SECLOCK); - DEASSERT(SGIMC_EEPROM_PRE); - DELAY; - ASSERT(SGIMC_EEPROM_CSEL); ASSERT(SGIMC_EEPROM_SECLOCK); - for(i = 0; i < 11; i++) { - if(cmd & (1<<15)) - ASSERT(SGIMC_EEPROM_SDATAO); - else - DEASSERT(SGIMC_EEPROM_SDATAO); - DEASSERT(SGIMC_EEPROM_SECLOCK); - ASSERT(SGIMC_EEPROM_SECLOCK); - cmd <<= 1; - } - DEASSERT(SGIMC_EEPROM_SDATAO); - for(i = 0; i < (sizeof(unsigned short) * 8); i++) { - unsigned int tmp; - - DEASSERT(SGIMC_EEPROM_SECLOCK); - DELAY; - ASSERT(SGIMC_EEPROM_SECLOCK); - DELAY; - data <<= 1; - tmp = *cpu_control; - if(tmp & SGIMC_EEPROM_SDATAI) - data |= 1; - } - DEASSERT(SGIMC_EEPROM_SECLOCK); - DEASSERT(SGIMC_EEPROM_CSEL); - ASSERT(SGIMC_EEPROM_PRE); - ASSERT(SGIMC_EEPROM_SECLOCK); - - data <<= PAGE_SHIFT; - if (data == 0) - return 0; - - scache_size = data; - - printk("R4600/R5000 SCACHE size %ldK, linesize 32 bytes.\n", - scache_size >> 10); - - return 1; -} - -/* XXX Check with wje if the Indy caches can differenciate between - writeback + invalidate and just invalidate. */ -static struct bcache_ops indy_sc_ops = { - indy_sc_enable, - indy_sc_disable, - indy_sc_wback_invalidate, - indy_sc_wback_invalidate -}; - -void __init indy_sc_init(void) -{ - if (indy_sc_probe()) { - indy_sc_enable(); - bcops = &indy_sc_ops; - } -} --- linux-2.5.73/arch/mips64/sgi-ip22/ip22-setup.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,189 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * SGI IP22 specific setup. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997, 1998, 1999 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999 Silcon Graphics, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern struct rtc_ops indy_rtc_ops; -extern void ip22_reboot_setup(void); -extern void ip22_volume_set(unsigned char); - -#define sgi_kh ((struct hpc_keyb *) (KSEG1 + 0x1fbd9800 + 64)) - -#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ - -static void ip22_request_region(void) -{ - /* No I/O ports are being used on the Indy. */ -} - -static int ip22_request_irq(void (*handler)(int, void *, struct pt_regs *)) -{ - /* Dirty hack, this get's called as a callback from the keyboard - driver. We piggyback the initialization of the front panel - button handling on it even though they're technically not - related with the keyboard driver in any way. Doing it from - indy_setup wouldn't work since kmalloc isn't initialized yet. */ - ip22_reboot_setup(); - - return request_irq(SGI_KEYBOARD_IRQ, handler, 0, "keyboard", NULL); -} - -static int ip22_aux_request_irq(void (*handler)(int, void *, struct pt_regs *)) -{ - /* Nothing to do, interrupt is shared with the keyboard hw */ - return 0; -} - -static void ip22_aux_free_irq(void) -{ - /* Nothing to do, interrupt is shared with the keyboard hw */ -} - -static unsigned char ip22_read_input(void) -{ - return sgi_kh->data; -} - -static void ip22_write_output(unsigned char val) -{ - int status; - - do { - status = sgi_kh->command; - } while (status & KBD_STAT_IBF); - sgi_kh->data = val; -} - -static void ip22_write_command(unsigned char val) -{ - int status; - - do { - status = sgi_kh->command; - } while (status & KBD_STAT_IBF); - sgi_kh->command = val; -} - -static unsigned char ip22_read_status(void) -{ - return sgi_kh->command; -} - -struct kbd_ops sgi_kbd_ops = { - ip22_request_region, - ip22_request_irq, - - ip22_aux_request_irq, - ip22_aux_free_irq, - - ip22_read_input, - ip22_write_output, - ip22_write_command, - ip22_read_status -}; - -int __init page_is_ram(unsigned long pagenr) -{ - if ((pagenr< 0x08002000) - return 1; - return 0; -} - -void __init ip22_setup(void) -{ -#ifdef CONFIG_SERIAL_CONSOLE - char *ctype; -#endif - TLBMISS_HANDLER_SETUP(); - - /* Init the INDY HPC I/O controller. Need to call this before - * fucking with the memory controller because it needs to know the - * boardID and whether this is a Guiness or a FullHouse machine. - */ - sgihpc_init(); - - /* Init INDY memory controller. */ - sgimc_init(); - - /* Now enable boardcaches, if any. */ - indy_sc_init(); - -#ifdef CONFIG_SERIAL_CONSOLE - /* ARCS console environment variable is set to "g?" for - * graphics console, it is set to "d" for the first serial - * line and "d2" for the second serial line. - */ - ctype = ArcGetEnvironmentVariable("console"); - if(*ctype == 'd') { - if(*(ctype+1)=='2') - console_setup ("ttyS1"); - else - console_setup ("ttyS0"); - } -#endif -#ifdef CONFIG_ARC_CONSOLE - console_setup("ttyS0"); -#endif - - ip22_volume_set(simple_strtoul(ArcGetEnvironmentVariable("volume"), - NULL, 10)); - -#ifdef CONFIG_VT -#ifdef CONFIG_SGI_NEWPORT_CONSOLE - conswitchp = &newport_con; - - screen_info = (struct screen_info) { - 0, 0, /* orig-x, orig-y */ - 0, /* unused */ - 0, /* orig_video_page */ - 0, /* orig_video_mode */ - 160, /* orig_video_cols */ - 0, 0, 0, /* unused, ega_bx, unused */ - 64, /* orig_video_lines */ - 0, /* orig_video_isVGA */ - 16 /* orig_video_points */ - }; -#else - conswitchp = &dummy_con; -#endif -#endif - rtc_ops = &indy_rtc_ops; - kbd_ops = &sgi_kbd_ops; -#ifdef CONFIG_PSMOUSE - aux_device_present = 0xaa; -#endif -#ifdef CONFIG_VIDEO_VINO - init_vino(); -#endif -} --- linux-2.5.73/arch/mips64/sgi-ip22/ip22-timer.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,262 +0,0 @@ -/* - * indy_timer.c: Setting up the clock on the INDY 8254 controller. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copytight (C) 1997, 1998 Ralf Baechle (ralf@gnu.org) - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -/* Because of a bug in the i8254 timer we need to use the onchip r4k - * counter as our system wide timer interrupt running at 100HZ. - */ -static unsigned long r4k_offset; /* Amount to increment compare reg each time */ -static unsigned long r4k_cur; /* What counter should be at next timer irq */ - -static inline void ack_r4ktimer(unsigned long newval) -{ - write_32bit_cp0_register(CP0_COMPARE, newval); -} - -static int set_rtc_mmss(unsigned long nowtime) -{ - struct indy_clock *clock = (struct indy_clock *)INDY_CLOCK_REGS; - int retval = 0; - int real_seconds, real_minutes, clock_minutes; - -#define FROB_FROM_CLOCK(x) (((x) & 0xf) | ((((x) & 0xf0) >> 4) * 10)); -#define FROB_TO_CLOCK(x) ((((((x) & 0xff) / 10)<<4) | (((x) & 0xff) % 10)) & 0xff) - - clock->cmd &= ~(0x80); - clock_minutes = clock->min; - clock->cmd |= (0x80); - - clock_minutes = FROB_FROM_CLOCK(clock_minutes); - real_seconds = nowtime % 60; - real_minutes = nowtime / 60; - - if(((abs(real_minutes - clock_minutes) + 15)/30) & 1) - real_minutes += 30; /* correct for half hour time zone */ - - real_minutes %= 60; - if(abs(real_minutes - clock_minutes) < 30) { - /* Force clock oscillator to be on. */ - clock->month &= ~(0x80); - - /* Write real_seconds and real_minutes into the Dallas. */ - clock->cmd &= ~(0x80); - clock->sec = real_seconds; - clock->min = real_minutes; - clock->cmd |= (0x80); - } else - return -1; - -#undef FROB_FROM_CLOCK -#undef FROB_TO_CLOCK - - return retval; -} - -static long last_rtc_update; -unsigned long missed_heart_beats; - -void indy_timer_interrupt(struct pt_regs *regs) -{ - unsigned long count; - int irq = 7; - - write_seqlock(&xtime_lock); - /* Ack timer and compute new compare. */ - count = read_32bit_cp0_register(CP0_COUNT); - /* This has races. */ - if ((count - r4k_cur) >= r4k_offset) { - /* If this happens to often we'll need to compensate. */ - missed_heart_beats++; - r4k_cur = count + r4k_offset; - } - else - r4k_cur += r4k_offset; - ack_r4ktimer(r4k_cur); - kstat_cpu(0).irqs[irq]++; - do_timer(regs); - - /* We update the Dallas time of day approx. every 11 minutes, - * because of how the numbers work out we need to make - * absolutely sure we do this update within 500ms before the - * next second starts, thus the following code. - */ - if ((time_status & STA_UNSYNC) == 0 && - xtime.tv_sec > last_rtc_update + 660 && - xtime.tv_usec >= 500000 - (tick >> 1) && - xtime.tv_usec <= 500000 + (tick >> 1)) { - if (set_rtc_mmss(xtime.tv_sec) == 0) - last_rtc_update = xtime.tv_sec; - else - /* do it again in 60s */ - last_rtc_update = xtime.tv_sec - 600; - } - write_sequnlock(&xtime_lock); -} - -static unsigned long dosample(volatile unsigned char *tcwp, - volatile unsigned char *tc2p) -{ - unsigned long ct0, ct1; - unsigned char msb, lsb; - - /* Start the counter. */ - *tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MRGEN); - *tc2p = (SGINT_TCSAMP_COUNTER & 0xff); - *tc2p = (SGINT_TCSAMP_COUNTER >> 8); - - /* Get initial counter invariant */ - ct0 = read_32bit_cp0_register(CP0_COUNT); - - /* Latch and spin until top byte of counter2 is zero */ - do { - *tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT); - lsb = *tc2p; - msb = *tc2p; - ct1 = read_32bit_cp0_register(CP0_COUNT); - } while(msb); - - /* Stop the counter. */ - *tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MSWST); - - /* Return the difference, this is how far the r4k counter increments - * for every one HZ. - */ - return ct1 - ct0; -} - -static unsigned long __init get_indy_time(void) -{ - struct indy_clock *clock = (struct indy_clock *)INDY_CLOCK_REGS; - unsigned int year, mon, day, hour, min, sec; - - /* Freeze it. */ - clock->cmd &= ~(0x80); - - /* Read regs. */ - sec = clock->sec; - min = clock->min; - hour = (clock->hr & 0x3f); - day = (clock->date & 0x3f); - mon = (clock->month & 0x1f); - year = clock->year; - - /* Unfreeze clock. */ - clock->cmd |= 0x80; - - /* Frob the bits. */ -#define FROB1(x) (((x) & 0xf) + ((((x) & 0xf0) >> 4) * 10)); -#define FROB2(x) (((x) & 0xf) + (((((x) & 0xf0) >> 4) & 0x3) * 10)); - - /* XXX Should really check that secs register is the same - * XXX as when we first read it and if not go back and - * XXX read the regs above again. - */ - sec = FROB1(sec); min = FROB1(min); day = FROB1(day); - mon = FROB1(mon); year = FROB1(year); - hour = FROB2(hour); - -#undef FROB1 -#undef FROB2 - - /* Wheee... */ - if(year < 45) - year += 30; - if ((year += 1940) < 1970) - year += 100; - - return mktime(year, mon, day, hour, min, sec); -} - -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) - -void __init indy_timer_init(void) -{ - struct sgi_ioc_timers *p; - volatile unsigned char *tcwp, *tc2p; - - /* Figure out the r4k offset, the algorithm is very simple and works - * in _all_ cases as long as the 8254 counter register itself works ok - * (as an interrupt driving timer it does not because of bug, this is - * why we are using the onchip r4k counter/compare register to serve - * this purpose, but for r4k_offset calculation it will work ok for us). - * There are other very complicated ways of performing this calculation - * but this one works just fine so I am not going to futz around. ;-) - */ - p = ioc_timers; - tcwp = &p->tcword; - tc2p = &p->tcnt2; - - printk("calculating r4koff... "); - dosample(tcwp, tc2p); /* First sample. */ - dosample(tcwp, tc2p); /* Eat one. */ - r4k_offset = dosample(tcwp, tc2p); /* Second sample. */ - - printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); - - r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset); - write_32bit_cp0_register(CP0_COMPARE, r4k_cur); - set_cp0_status(ST0_IM, ALLINTS); - sti(); - - write_seqlock_irq(&xtime_lock); - xtime.tv_sec = get_indy_time(); /* Read time from RTC. */ - xtime.tv_usec = 0; - write_sequnlock_irq(&xtime_lock); -} - -void indy_8254timer_irq(void) -{ - int cpu = smp_processor_id(); - int irq = 4; - - irq_enter(cpu, irq); - kstat_cpu(0).irqs[irq]++; - panic("indy_8254timer_irq: Whoops, should not have gotten this IRQ\n"); - irq_exit(cpu, irq); -} - -void do_gettimeofday(struct timeval *tv) -{ - unsigned long seq; - - do { - seq = read_seqbegin(&xtime_lock); - *tv = xtime; - } while (read_seqretry(&xtime_lock, seq)); -} - -void do_settimeofday(struct timeval *tv) -{ - write_seqlock_irq(&xtime_lock); - xtime = *tv; - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; - write_sequnlock_irq(&xtime_lock); -} --- linux-2.5.73/arch/mips64/sgi-ip22/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,9 +0,0 @@ -# -# Makefile for the SGI specific kernel interface routines -# under Linux. -# - -EXTRA_AFLAGS := $(CFLAGS) - -lib-y += ip22-berr.o ip22-mc.o ip22-sc.o ip22-hpc.o ip22-int.o ip22-rtc.o \ - ip22-setup.o system.o ip22-timer.o ip22-irq.o ip22-reset.o time.o --- linux-2.5.73/arch/mips64/sgi-ip22/system.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,123 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * system.c: Probe the system type using ARCS prom interface library. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) - */ -#include -#include -#include -#include - -#include -#include -#include - -struct smatch { - char *name; - int type; -}; - -static struct smatch sgi_cputable[] = { - { "MIPS-R2000", CPU_R2000 }, - { "MIPS-R3000", CPU_R3000 }, - { "MIPS-R3000A", CPU_R3000A }, - { "MIPS-R4000", CPU_R4000SC }, - { "MIPS-R4400", CPU_R4400SC }, - { "MIPS-R4600", CPU_R4600 }, - { "MIPS-R8000", CPU_R8000 }, - { "MIPS-R5000", CPU_R5000 }, - { "MIPS-R5000A", CPU_R5000A } -}; - -#define NUM_CPUS 9 /* for now */ - -static int __init string_to_cpu(char *s) -{ - int i; - - for(i = 0; i < NUM_CPUS; i++) { - if(!strcmp(s, sgi_cputable[i].name)) - return sgi_cputable[i].type; - } - panic("\nYeee, could not determine MIPS cpu type <%s>", s); - return 0; -} - -/* - * We' call this early before loadmmu(). If we do the other way around - * the firmware will crash and burn. - */ -void __init sgi_sysinit(void) -{ - pcomponent *p, *toplev, *cpup = 0; - int cputype = -1; - - - /* The root component tells us what machine architecture we - * have here. - */ - p = ArcGetChild(PROM_NULL_COMPONENT); - - /* Now scan for cpu(s). */ - toplev = p = ArcGetChild(p); - while(p) { - int ncpus = 0; - - if(p->type == Cpu) { - if (++ncpus > 1) - panic("\nYeee, SGI MP not ready yet"); - printk("CPU: %s ", p->iname); - cpup = p; - cputype = string_to_cpu(cpup->iname); - } - p = ArcGetPeer(p); - } - if (cputype == -1) { - panic("\nYeee, could not find cpu ARCS component"); - } - p = ArcGetChild(cpup); - while(p) { - switch(p->class) { - case processor: - switch(p->type) { - case Fpu: - printk("FPU<%s> ", p->iname); - break; - - default: - break; - }; - break; - - case cache: - switch(p->type) { - case picache: - printk("ICACHE "); - break; - - case pdcache: - printk("DCACHE "); - break; - - case sccache: - printk("SCACHE "); - break; - - default: - break; - - }; - break; - - default: - break; - }; - p = ArcGetPeer(p); - } - printk("\n"); -} --- linux-2.5.73/arch/mips64/sgi-ip22/time.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,19 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * time.c: Generic SGI time_init() code, this will dispatch to the - * appropriate per-architecture time/counter init code. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include - -extern void indy_timer_init(void); - -void __init time_init(void) -{ - /* XXX assume INDY for now XXX */ - indy_timer_init(); -} --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-berr.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,172 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1999, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 by Silicon Graphics - */ -#include -#include -#include - -#include -#include -#include -#include -#include - -extern void dump_tlb_addr(unsigned long addr); -extern void dump_tlb_all(void); - -extern asmlinkage void handle_ibe(void); -extern asmlinkage void handle_dbe(void); - -extern const struct exception_table_entry __start___dbe_table[]; -extern const struct exception_table_entry __stop___dbe_table[]; - -static inline unsigned long -search_one_table(const struct exception_table_entry *first, - const struct exception_table_entry *last, - unsigned long value) -{ - while (first <= last) { - const struct exception_table_entry *mid; - long diff; - - mid = (last - first) / 2 + first; - diff = mid->insn - value; - if (diff == 0) - return mid->nextinsn; - else if (diff < 0) - first = mid+1; - else - last = mid-1; - } - return 0; -} - -extern spinlock_t modlist_lock; - -static inline unsigned long -search_dbe_table(unsigned long addr) -{ - unsigned long ret; - -#ifndef CONFIG_MODULES - /* There is only the kernel to search. */ - ret = search_one_table(__start___dbe_table, __stop___dbe_table-1, addr); - return ret; -#else - unsigned long flags; - - /* The kernel is the last "module" -- no need to treat it special. */ - struct module *mp; - struct archdata *ap; - - spin_lock_irqsave(&modlist_lock, flags); - for (mp = module_list; mp != NULL; mp = mp->next) { - if (!mod_member_present(mp, archdata_end) || - !mod_archdata_member_present(mp, struct archdata, - dbe_table_end)) - continue; - ap = (struct archdata *)(mod->archdata_start); - - if (ap->dbe_table_start == NULL || - !(mp->flags & (MOD_RUNNING | MOD_INITIALIZING))) - continue; - ret = search_one_table(ap->dbe_table_start, - ap->dbe_table_end - 1, addr); - if (ret) - break; - } - spin_unlock_irqrestore(&modlist_lock, flags); - return ret; -#endif -} - -void do_ibe(struct pt_regs *regs) -{ - printk("Got ibe at 0x%lx\n", regs->cp0_epc); - show_regs(regs); - dump_tlb_addr(regs->cp0_epc); - force_sig(SIGBUS, current); - while(1); -} - -static void dump_hub_information(unsigned long errst0, unsigned long errst1) -{ - static char *err_type[2][8] = { - { NULL, "Uncached Partial Read PRERR", "DERR", "Read Timeout", - NULL, NULL, NULL, NULL }, - { "WERR", "Uncached Partial Write", "PWERR", "Write Timeout", - NULL, NULL, NULL, NULL } - }; - int wrb = errst1 & PI_ERR_ST1_WRBRRB_MASK; - - if (!(errst0 & PI_ERR_ST0_VALID_MASK)) { - printk("Hub does not contain valid error information\n"); - return; - } - - - printk("Hub has valid error information:\n"); - if (errst0 & PI_ERR_ST0_OVERRUN_MASK) - printk("Overrun is set. Error stack may contain additional " - "information.\n"); - printk("Hub error address is %08lx\n", - (errst0 & PI_ERR_ST0_ADDR_MASK) >> (PI_ERR_ST0_ADDR_SHFT - 3)); - printk("Incoming message command 0x%lx\n", - (errst0 & PI_ERR_ST0_CMD_MASK) >> PI_ERR_ST0_CMD_SHFT); - printk("Supplemental field of incoming message is 0x%lx\n", - (errst0 & PI_ERR_ST0_SUPPL_MASK) >> PI_ERR_ST0_SUPPL_SHFT); - printk("T5 Rn (for RRB only) is 0x%lx\n", - (errst0 & PI_ERR_ST0_REQNUM_MASK) >> PI_ERR_ST0_REQNUM_SHFT); - printk("Error type is %s\n", err_type[wrb] - [(errst0 & PI_ERR_ST0_TYPE_MASK) >> PI_ERR_ST0_TYPE_SHFT] - ? : "invalid"); -} - -void do_dbe(struct pt_regs *regs) -{ - unsigned long fixup, errst0, errst1; - int cpu = LOCAL_HUB_L(PI_CPU_NUM); - - fixup = search_dbe_table(regs->cp0_epc); - if (fixup) { - long new_epc; - - new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc); - regs->cp0_epc = new_epc; - return; - } - - printk("Slice %c got dbe at 0x%lx\n", 'A' + cpu, regs->cp0_epc); - printk("Hub information:\n"); - printk("ERR_INT_PEND = 0x%06lx\n", LOCAL_HUB_L(PI_ERR_INT_PEND)); - errst0 = LOCAL_HUB_L(cpu ? PI_ERR_STATUS0_B : PI_ERR_STATUS0_A); - errst1 = LOCAL_HUB_L(cpu ? PI_ERR_STATUS1_B : PI_ERR_STATUS1_A); - dump_hub_information(errst0, errst1); - show_regs(regs); - dump_tlb_all(); - while(1); - force_sig(SIGBUS, current); -} - -void __init -bus_error_init(void) -{ - /* XXX Initialize all the Hub & Bridge error handling here. */ - int cpu = LOCAL_HUB_L(PI_CPU_NUM); - int cpuoff = cpu << 8; - - set_except_vector(6, handle_ibe); - set_except_vector(7, handle_dbe); - - LOCAL_HUB_S(PI_ERR_INT_PEND, - cpu ? PI_ERR_CLEAR_ALL_B : PI_ERR_CLEAR_ALL_A); - LOCAL_HUB_S(PI_ERR_INT_MASK_A + cpuoff, 0); - LOCAL_HUB_S(PI_ERR_STACK_ADDR_A + cpuoff, 0); - LOCAL_HUB_S(PI_ERR_STACK_SIZE, 0); /* Disable error stack */ - LOCAL_HUB_S(PI_SYSAD_ERRCHK_EN, PI_SYSAD_CHECK_ALL); -} --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-console.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,58 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2001 Ralf Baechle - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void prom_putchar(char c) -{ - struct ioc3 *ioc3; - struct ioc3_uartregs *uart; - - ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(master_nasid)->memory_base; - uart = &ioc3->sregs.uarta; - - while ((uart->iu_lsr & 0x20) == 0); - uart->iu_thr = c; -} - -char __init prom_getchar(void) -{ - return 0; -} - -static void -ip27prom_console_write(struct console *con, const char *s, unsigned n) -{ - prom_printf("%s", s); -} - -static kdev_t -ip27prom_console_dev(struct console *c) -{ - return MKDEV(TTY_MAJOR, 64 + c->index); -} - -static struct console ip27_prom_console = { - .name = "prom", - .write = ip27prom_console_write, - .device = ip27prom_console_dev, - .flags = CON_PRINTBUFFER, - .index = -1, -}; - -__init void ip27_setup_console(void) -{ - register_console(&ip27_prom_console); -} --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-init.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,840 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file "COPYING" in the main directory of this - * archive for more details. - * - * Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com) - * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc. - */ - -#include -#include -#include -#include -#include /* for numnodes */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define CPU_NONE (cpuid_t)-1 - -/* - * The following should work till 64 nodes, ie 128p SN0s. - */ -#define CNODEMASK_CLRALL(p) (p) = 0 -#define CNODEMASK_TSTB(p, bit) ((p) & (1ULL << (bit))) -#define CNODEMASK_SETB(p, bit) ((p) |= 1ULL << (bit)) - -cpumask_t boot_cpumask; -hubreg_t region_mask = 0; -static int fine_mode = 0; -int maxcpus; -static spinlock_t hub_mask_lock = SPIN_LOCK_UNLOCKED; -static cnodemask_t hub_init_mask; -static atomic_t numstarted = ATOMIC_INIT(1); -static int router_distance; -nasid_t master_nasid = INVALID_NASID; - -cnodeid_t nasid_to_compact_node[MAX_NASIDS]; -nasid_t compact_to_nasid_node[MAX_COMPACT_NODES]; -cnodeid_t cpuid_to_compact_node[MAXCPUS]; -char node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES]; - -hubreg_t get_region(cnodeid_t cnode) -{ - if (fine_mode) - return COMPACT_TO_NASID_NODEID(cnode) >> NASID_TO_FINEREG_SHFT; - else - return COMPACT_TO_NASID_NODEID(cnode) >> NASID_TO_COARSEREG_SHFT; -} - -static void gen_region_mask(hubreg_t *region_mask, int maxnodes) -{ - cnodeid_t cnode; - - (*region_mask) = 0; - for (cnode = 0; cnode < maxnodes; cnode++) { - (*region_mask) |= 1ULL << get_region(cnode); - } -} - -int is_fine_dirmode(void) -{ - return (((LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_REGIONSIZE_MASK) - >> NSRI_REGIONSIZE_SHFT) & REGIONSIZE_FINE); -} - -nasid_t get_actual_nasid(lboard_t *brd) -{ - klhub_t *hub; - - if (!brd) - return INVALID_NASID; - - /* find out if we are a completely disabled brd. */ - hub = (klhub_t *)find_first_component(brd, KLSTRUCT_HUB); - if (!hub) - return INVALID_NASID; - if (!(hub->hub_info.flags & KLINFO_ENABLE)) /* disabled node brd */ - return hub->hub_info.physid; - else - return brd->brd_nasid; -} - -/* Tweak this for maximum number of CPUs to activate */ -static int max_cpus = NR_CPUS; - -int do_cpumask(cnodeid_t cnode, nasid_t nasid, cpumask_t *boot_cpumask, - int *highest) -{ - static int tot_cpus_found = 0; - lboard_t *brd; - klcpu_t *acpu; - int cpus_found = 0; - cpuid_t cpuid; - - brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IP27); - - do { - acpu = (klcpu_t *)find_first_component(brd, KLSTRUCT_CPU); - while (acpu) { - cpuid = acpu->cpu_info.virtid; - /* cnode is not valid for completely disabled brds */ - if (get_actual_nasid(brd) == brd->brd_nasid) - cpuid_to_compact_node[cpuid] = cnode; - if (cpuid > *highest) - *highest = cpuid; - /* Only let it join in if it's marked enabled */ - if ((acpu->cpu_info.flags & KLINFO_ENABLE) && - (tot_cpus_found != max_cpus)) { - CPUMASK_SETB(*boot_cpumask, cpuid); - cpus_found++; - tot_cpus_found++; - } - acpu = (klcpu_t *)find_component(brd, (klinfo_t *)acpu, - KLSTRUCT_CPU); - } - brd = KLCF_NEXT(brd); - if (brd) - brd = find_lboard(brd,KLTYPE_IP27); - else - break; - } while (brd); - - return cpus_found; -} - -cpuid_t cpu_node_probe(cpumask_t *boot_cpumask, int *numnodes) -{ - int i, cpus = 0, highest = 0; - gda_t *gdap = GDA; - nasid_t nasid; - - /* - * Initialize the arrays to invalid nodeid (-1) - */ - for (i = 0; i < MAX_COMPACT_NODES; i++) - compact_to_nasid_node[i] = INVALID_NASID; - for (i = 0; i < MAX_NASIDS; i++) - nasid_to_compact_node[i] = INVALID_CNODEID; - for (i = 0; i < MAXCPUS; i++) - cpuid_to_compact_node[i] = INVALID_CNODEID; - - *numnodes = 0; - for (i = 0; i < MAX_COMPACT_NODES; i++) { - if ((nasid = gdap->g_nasidtable[i]) == INVALID_NASID) { - break; - } else { - compact_to_nasid_node[i] = nasid; - nasid_to_compact_node[nasid] = i; - (*numnodes)++; - cpus += do_cpumask(i, nasid, boot_cpumask, &highest); - } - } - - /* - * Cpus are numbered in order of cnodes. Currently, disabled - * cpus are not numbered. - */ - - return(highest + 1); -} - -int cpu_enabled(cpuid_t cpu) -{ - if (cpu == CPU_NONE) - return 0; - return (CPUMASK_TSTB(boot_cpumask, cpu) != 0); -} - -void mlreset (void) -{ - int i; - void init_topology_matrix(void); - void dump_topology(void); - - - master_nasid = get_nasid(); - fine_mode = is_fine_dirmode(); - - /* - * Probe for all CPUs - this creates the cpumask and - * sets up the mapping tables. - */ - CPUMASK_CLRALL(boot_cpumask); - maxcpus = cpu_node_probe(&boot_cpumask, &numnodes); - printk("Discovered %d cpus on %d nodes\n", maxcpus, numnodes); - - init_topology_matrix(); - dump_topology(); - - gen_region_mask(®ion_mask, numnodes); - CNODEMASK_CLRALL(hub_init_mask); - - setup_replication_mask(numnodes); - - /* - * Set all nodes' calias sizes to 8k - */ - for (i = 0; i < numnodes; i++) { - nasid_t nasid; - - nasid = COMPACT_TO_NASID_NODEID(i); - - /* - * Always have node 0 in the region mask, otherwise - * CALIAS accesses get exceptions since the hub - * thinks it is a node 0 address. - */ - REMOTE_HUB_S(nasid, PI_REGION_PRESENT, (region_mask | 1)); -#ifdef CONFIG_REPLICATE_EXHANDLERS - REMOTE_HUB_S(nasid, PI_CALIAS_SIZE, PI_CALIAS_SIZE_8K); -#else - REMOTE_HUB_S(nasid, PI_CALIAS_SIZE, PI_CALIAS_SIZE_0); -#endif - -#ifdef LATER - /* - * Set up all hubs to have a big window pointing at - * widget 0. Memory mode, widget 0, offset 0 - */ - REMOTE_HUB_S(nasid, IIO_ITTE(SWIN0_BIGWIN), - ((HUB_PIO_MAP_TO_MEM << IIO_ITTE_IOSP_SHIFT) | - (0 << IIO_ITTE_WIDGET_SHIFT))); -#endif - } -} - - -void intr_clear_bits(nasid_t nasid, volatile hubreg_t *pend, int base_level, - char *name) -{ - volatile hubreg_t bits; - int i; - - /* Check pending interrupts */ - if ((bits = HUB_L(pend)) != 0) - for (i = 0; i < N_INTPEND_BITS; i++) - if (bits & (1 << i)) - LOCAL_HUB_CLR_INTR(base_level + i); -} - -void intr_clear_all(nasid_t nasid) -{ - REMOTE_HUB_S(nasid, PI_INT_MASK0_A, 0); - REMOTE_HUB_S(nasid, PI_INT_MASK0_B, 0); - REMOTE_HUB_S(nasid, PI_INT_MASK1_A, 0); - REMOTE_HUB_S(nasid, PI_INT_MASK1_B, 0); - intr_clear_bits(nasid, REMOTE_HUB_ADDR(nasid, PI_INT_PEND0), - INT_PEND0_BASELVL, "INT_PEND0"); - intr_clear_bits(nasid, REMOTE_HUB_ADDR(nasid, PI_INT_PEND1), - INT_PEND1_BASELVL, "INT_PEND1"); -} - -void sn_mp_setup(void) -{ - cnodeid_t cnode; -#if 0 - cpuid_t cpu; -#endif - - for (cnode = 0; cnode < numnodes; cnode++) { -#if 0 - init_platform_nodepda(); -#endif - intr_clear_all(COMPACT_TO_NASID_NODEID(cnode)); - } -#if 0 - for (cpu = 0; cpu < maxcpus; cpu++) { - init_platform_pda(); - } -#endif -} - -void per_hub_init(cnodeid_t cnode) -{ - extern void pcibr_setup(cnodeid_t); - cnodemask_t done; - nasid_t nasid; - - nasid = COMPACT_TO_NASID_NODEID(cnode); - - spin_lock(&hub_mask_lock); - /* Test our bit. */ - if (!(done = CNODEMASK_TSTB(hub_init_mask, cnode))) { - /* Turn our bit on in the mask. */ - CNODEMASK_SETB(hub_init_mask, cnode); - /* - * Do the actual initialization if it hasn't been done yet. - * We don't need to hold a lock for this work. - */ - /* - * Set CRB timeout at 5ms, (< PI timeout of 10ms) - */ - REMOTE_HUB_S(nasid, IIO_ICTP, 0x800); - REMOTE_HUB_S(nasid, IIO_ICTO, 0xff); - hub_rtc_init(cnode); - pcibr_setup(cnode); -#ifdef CONFIG_REPLICATE_EXHANDLERS - /* - * If this is not a headless node initialization, - * copy over the caliased exception handlers. - */ - if (get_compact_nodeid() == cnode) { - extern char except_vec0, except_vec1_r10k; - extern char except_vec2_generic, except_vec3_generic; - - memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, - 0x80); - memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, - 0x80); - memcpy((void *)KSEG0, &except_vec0, 0x80); - memcpy((void *)KSEG0 + 0x080, &except_vec1_r10k, 0x80); - memcpy((void *)(KSEG0 + 0x100), (void *) KSEG0, 0x80); - memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, - 0x100); - flush_cache_l1(); - flush_cache_l2(); - } -#endif - } - spin_unlock(&hub_mask_lock); -} - -/* - * This is similar to hard_smp_processor_id(). - */ -cpuid_t getcpuid(void) -{ - klcpu_t *klcpu; - - klcpu = nasid_slice_to_cpuinfo(get_nasid(),LOCAL_HUB_L(PI_CPU_NUM)); - return klcpu->cpu_info.virtid; -} - -void per_cpu_init(void) -{ - extern void install_cpu_nmi_handler(int slice); - extern void load_mmu(void); - static int is_slave = 0; - int cpu = smp_processor_id(); - cnodeid_t cnode = get_compact_nodeid(); - - current_cpu_data.asid_cache = ASID_FIRST_VERSION; - TLBMISS_HANDLER_SETUP(); -#if 0 - intr_init(); -#endif - set_cp0_status(ST0_IM, 0); - per_hub_init(cnode); - cpu_time_init(); - if (smp_processor_id()) /* master can't do this early, no kmalloc */ - install_cpuintr(cpu); - /* Install our NMI handler if symmon hasn't installed one. */ - install_cpu_nmi_handler(cputoslice(cpu)); -#if 0 - install_tlbintr(cpu); -#endif - set_cp0_status(SRB_DEV0 | SRB_DEV1, SRB_DEV0 | SRB_DEV1); - if (is_slave) { - set_cp0_status(ST0_BEV, 0); - if (mips4_available) - set_cp0_status(ST0_XX, ST0_XX); - set_cp0_status(ST0_KX|ST0_SX|ST0_UX, ST0_KX|ST0_SX|ST0_UX); - sti(); - load_mmu(); - atomic_inc(&numstarted); - } else { - is_slave = 1; - } -} - -cnodeid_t get_compact_nodeid(void) -{ - nasid_t nasid; - - nasid = get_nasid(); - /* - * Map the physical node id to a virtual node id (virtual node ids - * are contiguous). - */ - return NASID_TO_COMPACT_NODEID(nasid); -} - -#ifdef CONFIG_SMP - -/* - * Takes as first input the PROM assigned cpu id, and the kernel - * assigned cpu id as the second. - */ -static void alloc_cpupda(cpuid_t cpu, int cpunum) -{ - cnodeid_t node; - nasid_t nasid; - - node = get_cpu_cnode(cpu); - nasid = COMPACT_TO_NASID_NODEID(node); - - cputonasid(cpunum) = nasid; - cputocnode(cpunum) = node; - cputoslice(cpunum) = get_cpu_slice(cpu); - cpu_data[cpunum].p_cpuid = cpu; -} - -void __init smp_callin(void) -{ -#if 0 - calibrate_delay(); - smp_store_cpu_info(cpuid); -#endif -} - -int __init start_secondary(void) -{ - extern int cpu_idle(void); - extern atomic_t smp_commenced; - - smp_callin(); - while (!atomic_read(&smp_commenced)); - return cpu_idle(); -} - -static volatile cpumask_t boot_barrier; - -void cboot(void) -{ - CPUMASK_CLRB(boot_barrier, getcpuid()); /* needs atomicity */ - per_cpu_init(); -#if 0 - ecc_init(); - bte_lateinit(); - init_mfhi_war(); -#endif - _flush_tlb_all(); - flush_cache_l1(); - flush_cache_l2(); - start_secondary(); -} - -void allowboot(void) -{ - int num_cpus = 0; - cpuid_t cpu, mycpuid = getcpuid(); - cnodeid_t cnode; - extern void bootstrap(void); - - sn_mp_setup(); - /* Master has already done per_cpu_init() */ - install_cpuintr(smp_processor_id()); -#if 0 - bte_lateinit(); - ecc_init(); -#endif - - replicate_kernel_text(numnodes); - boot_barrier = boot_cpumask; - /* Launch slaves. */ - for (cpu = 0; cpu < maxcpus; cpu++) { - if (cpu == mycpuid) { - alloc_cpupda(cpu, num_cpus); - num_cpus++; - /* We're already started, clear our bit */ - CPUMASK_CLRB(boot_barrier, cpu); - continue; - } - - /* Skip holes in CPU space */ - if (CPUMASK_TSTB(boot_cpumask, cpu)) { - struct task_struct *p; - - /* - * The following code is purely to make sure - * Linux can schedule processes on this slave. - */ - kernel_thread(0, NULL, CLONE_IDLETASK); - p = prev_task(&init_task); - sprintf(p->comm, "%s%d", "Idle", num_cpus); - init_tasks[num_cpus] = p; - alloc_cpupda(cpu, num_cpus); - del_from_runqueue(p); - p->processor = num_cpus; - p->cpus_runnable = 1 << num_cpus; /* we schedule the first task manually */ - unhash_process(p); - /* Attach to the address space of init_task. */ - atomic_inc(&init_mm.mm_count); - p->active_mm = &init_mm; - - /* - * Launch a slave into bootstrap(). - * It doesn't take an argument, and we - * set sp to the kernel stack of the newly - * created idle process, gp to the proc struct - * (so that current-> works). - */ - LAUNCH_SLAVE(cputonasid(num_cpus),cputoslice(num_cpus), - (launch_proc_t)MAPPED_KERN_RW_TO_K0(bootstrap), - 0, (void *)((unsigned long)p + - KERNEL_STACK_SIZE - 32), (void *)p); - - /* - * Now optimistically set the mapping arrays. We - * need to wait here, verify the cpu booted up, then - * fire up the next cpu. - */ - __cpu_number_map[cpu] = num_cpus; - __cpu_logical_map[num_cpus] = cpu; - num_cpus++; - /* - * Wait this cpu to start up and initialize its hub, - * and discover the io devices it will control. - * - * XXX: We really want to fire up launch all the CPUs - * at once. We have to preserve the order of the - * devices on the bridges first though. - */ - while(atomic_read(&numstarted) != num_cpus); - } - } - - -#ifdef LATER - Wait logic goes here. -#endif - for (cnode = 0; cnode < numnodes; cnode++) { -#if 0 - if (cnodetocpu(cnode) == -1) { - printk("Initializing headless hub,cnode %d", cnode); - per_hub_init(cnode); - } -#endif - } -#if 0 - cpu_io_setup(); - init_mfhi_war(); -#endif - smp_num_cpus = num_cpus; -} - -#else /* CONFIG_SMP */ -void cboot(void) {} -#endif /* CONFIG_SMP */ - - -#define rou_rflag rou_flags - -void -router_recurse(klrou_t *router_a, klrou_t *router_b, int depth) -{ - klrou_t *router; - lboard_t *brd; - int port; - - if (router_a->rou_rflag == 1) - return; - - if (depth >= router_distance) - return; - - router_a->rou_rflag = 1; - - for (port = 1; port <= MAX_ROUTER_PORTS; port++) { - if (router_a->rou_port[port].port_nasid == INVALID_NASID) - continue; - - brd = (lboard_t *)NODE_OFFSET_TO_K0( - router_a->rou_port[port].port_nasid, - router_a->rou_port[port].port_offset); - - if (brd->brd_type == KLTYPE_ROUTER) { - router = (klrou_t *)NODE_OFFSET_TO_K0(NASID_GET(brd), brd->brd_compts[0]); - if (router == router_b) { - if (depth < router_distance) - router_distance = depth; - } - else - router_recurse(router, router_b, depth + 1); - } - } - - router_a->rou_rflag = 0; -} - -int -node_distance(nasid_t nasid_a, nasid_t nasid_b) -{ - nasid_t nasid; - cnodeid_t cnode; - lboard_t *brd, *dest_brd; - int port; - klrou_t *router, *router_a = NULL, *router_b = NULL; - - /* Figure out which routers nodes in question are connected to */ - for (cnode = 0; cnode < numnodes; cnode++) { - nasid = COMPACT_TO_NASID_NODEID(cnode); - - if (nasid == -1) continue; - - brd = find_lboard_class((lboard_t *)KL_CONFIG_INFO(nasid), - KLTYPE_ROUTER); - - if (!brd) - continue; - - do { - if (brd->brd_flags & DUPLICATE_BOARD) - continue; - - router = (klrou_t *)NODE_OFFSET_TO_K0(NASID_GET(brd), brd->brd_compts[0]); - router->rou_rflag = 0; - - for (port = 1; port <= MAX_ROUTER_PORTS; port++) { - if (router->rou_port[port].port_nasid == INVALID_NASID) - continue; - - dest_brd = (lboard_t *)NODE_OFFSET_TO_K0( - router->rou_port[port].port_nasid, - router->rou_port[port].port_offset); - - if (dest_brd->brd_type == KLTYPE_IP27) { - if (dest_brd->brd_nasid == nasid_a) - router_a = router; - if (dest_brd->brd_nasid == nasid_b) - router_b = router; - } - } - - } while ( (brd = find_lboard_class(KLCF_NEXT(brd), KLTYPE_ROUTER)) ); - } - - if (router_a == NULL) { - printk("node_distance: router_a NULL\n"); - return -1; - } - if (router_b == NULL) { - printk("node_distance: router_b NULL\n"); - return -1; - } - - if (nasid_a == nasid_b) - return 0; - - if (router_a == router_b) - return 1; - - router_distance = 100; - router_recurse(router_a, router_b, 2); - - return router_distance; -} - -void -init_topology_matrix(void) -{ - nasid_t nasid, nasid2; - cnodeid_t row, col; - - for (row = 0; row < MAX_COMPACT_NODES; row++) - for (col = 0; col < MAX_COMPACT_NODES; col++) - node_distances[row][col] = -1; - - for (row = 0; row < numnodes; row++) { - nasid = COMPACT_TO_NASID_NODEID(row); - for (col = 0; col < numnodes; col++) { - nasid2 = COMPACT_TO_NASID_NODEID(col); - node_distances[row][col] = node_distance(nasid, nasid2); - } - } -} - -void -dump_topology(void) -{ - nasid_t nasid; - cnodeid_t cnode; - lboard_t *brd, *dest_brd; - int port; - int router_num = 0; - klrou_t *router; - cnodeid_t row, col; - - printk("************** Topology ********************\n"); - - printk(" "); - for (col = 0; col < numnodes; col++) - printk("%02d ", col); - printk("\n"); - for (row = 0; row < numnodes; row++) { - printk("%02d ", row); - for (col = 0; col < numnodes; col++) - printk("%2d ", node_distances[row][col]); - printk("\n"); - } - - for (cnode = 0; cnode < numnodes; cnode++) { - nasid = COMPACT_TO_NASID_NODEID(cnode); - - if (nasid == -1) continue; - - brd = find_lboard_class((lboard_t *)KL_CONFIG_INFO(nasid), - KLTYPE_ROUTER); - - if (!brd) - continue; - - do { - if (brd->brd_flags & DUPLICATE_BOARD) - continue; - printk("Router %d:", router_num); - router_num++; - - router = (klrou_t *)NODE_OFFSET_TO_K0(NASID_GET(brd), brd->brd_compts[0]); - - for (port = 1; port <= MAX_ROUTER_PORTS; port++) { - if (router->rou_port[port].port_nasid == INVALID_NASID) - continue; - - dest_brd = (lboard_t *)NODE_OFFSET_TO_K0( - router->rou_port[port].port_nasid, - router->rou_port[port].port_offset); - - if (dest_brd->brd_type == KLTYPE_IP27) - printk(" %d", dest_brd->brd_nasid); - if (dest_brd->brd_type == KLTYPE_ROUTER) - printk(" r"); - } - printk("\n"); - - } while ( (brd = find_lboard_class(KLCF_NEXT(brd), KLTYPE_ROUTER)) ); - } -} - -#if 0 -#define brd_widgetnum brd_slot -#define NODE_OFFSET_TO_KLINFO(n,off) ((klinfo_t*) TO_NODE_CAC(n,off)) -void -dump_klcfg(void) -{ - cnodeid_t cnode; - int i; - nasid_t nasid; - lboard_t *lbptr; - gda_t *gdap; - - gdap = (gda_t *)GDA_ADDR(get_nasid()); - if (gdap->g_magic != GDA_MAGIC) { - printk("dumpklcfg_cmd: Invalid GDA MAGIC\n"); - return; - } - - for (cnode = 0; cnode < MAX_COMPACT_NODES; cnode ++) { - nasid = gdap->g_nasidtable[cnode]; - - if (nasid == INVALID_NASID) - continue; - - printk("\nDumpping klconfig Nasid %d:\n", nasid); - - lbptr = KL_CONFIG_INFO(nasid); - - while (lbptr) { - printk(" %s, Nasid %d, Module %d, widget 0x%x, partition %d, NIC 0x%x lboard 0x%lx", - "board name here", /* BOARD_NAME(lbptr->brd_type), */ - lbptr->brd_nasid, lbptr->brd_module, - lbptr->brd_widgetnum, - lbptr->brd_partition, - (lbptr->brd_nic), lbptr); - if (lbptr->brd_flags & DUPLICATE_BOARD) - printk(" -D"); - printk("\n"); - for (i = 0; i < lbptr->brd_numcompts; i++) { - klinfo_t *kli; - kli = NODE_OFFSET_TO_KLINFO(NASID_GET(lbptr), lbptr->brd_compts[i]); - printk(" type %2d, flags 0x%04x, diagval %3d, physid %4d, virtid %2d: %s\n", - kli->struct_type, - kli->flags, - kli->diagval, - kli->physid, - kli->virtid, - "comp. name here"); - /* COMPONENT_NAME(kli->struct_type)); */ - } - lbptr = KLCF_NEXT(lbptr); - } - } - printk("\n"); - - /* Useful to print router maps also */ - - for (cnode = 0; cnode < MAX_COMPACT_NODES; cnode ++) { - klrou_t *kr; - int i; - - nasid = gdap->g_nasidtable[cnode]; - if (nasid == INVALID_NASID) - continue; - lbptr = KL_CONFIG_INFO(nasid); - - while (lbptr) { - - lbptr = find_lboard_class(lbptr, KLCLASS_ROUTER); - if(!lbptr) - break; - if (!KL_CONFIG_DUPLICATE_BOARD(lbptr)) { - printk("%llx -> \n", lbptr->brd_nic); - kr = (klrou_t *)find_first_component(lbptr, - KLSTRUCT_ROU); - for (i = 1; i <= MAX_ROUTER_PORTS; i++) { - printk("[%d, %llx]; ", - kr->rou_port[i].port_nasid, - kr->rou_port[i].port_offset); - } - printk("\n"); - } - lbptr = KLCF_NEXT(lbptr); - } - printk("\n"); - } - - dump_topology(); -} -#endif - --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-irq.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,769 +0,0 @@ -/* - * ip27-irq.c: Highlevel interrupt handling for IP27 architecture. - * - * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 1999 - 2001 Kanoj Sarcar - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#undef DEBUG_IRQ -#ifdef DEBUG_IRQ -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -/* These should die */ -unsigned char bus_to_wid[256]; /* widget id for linux pci bus */ -unsigned char bus_to_nid[256]; /* nasid for linux pci bus */ -unsigned char num_bridges; /* number of bridges in the system */ - -/* - * Linux has a controller-independent x86 interrupt architecture. - * every controller has a 'controller-template', that is used - * by the main code to do the right thing. Each driver-visible - * interrupt source is transparently wired to the apropriate - * controller. Thus drivers need not be aware of the - * interrupt-controller. - * - * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC, - * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC. - * (IO-APICs assumed to be messaging to Pentium local-APICs) - * - * the code is designed to be easily extended with new/different - * interrupt controllers, without having to do assembly magic. - */ - -extern asmlinkage void ip27_irq(void); -extern int irq_to_bus[], irq_to_slot[], bus_to_cpu[]; -int intr_connect_level(int cpu, int bit); -int intr_disconnect_level(int cpu, int bit); - -unsigned long spurious_count = 0; - -/* - * There is a single intpend register per node, and we want to have - * distinct levels for intercpu intrs for both cpus A and B on a node. - */ -int node_level_to_irq[MAX_COMPACT_NODES][PERNODE_LEVELS]; - -/* - * use these macros to get the encoded nasid and widget id - * from the irq value - */ -#define IRQ_TO_BUS(i) irq_to_bus[(i)] -#define IRQ_TO_CPU(i) bus_to_cpu[IRQ_TO_BUS(i)] -#define NASID_FROM_PCI_IRQ(i) bus_to_nid[IRQ_TO_BUS(i)] -#define WID_FROM_PCI_IRQ(i) bus_to_wid[IRQ_TO_BUS(i)] -#define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i] - -static inline int alloc_level(cpuid_t cpunum, int irq) -{ - cnodeid_t nodenum = CPUID_TO_COMPACT_NODEID(cpunum); - int j = LEAST_LEVEL + 3; /* resched & crosscall entries taken */ - - while (++j < PERNODE_LEVELS) { - if (node_level_to_irq[nodenum][j] == -1) { - node_level_to_irq[nodenum][j] = irq; - return j; - } - } - printk("Cpu %ld flooded with devices\n", cpunum); - while(1); - return -1; -} - -static inline int find_level(cpuid_t *cpunum, int irq) -{ - int j; - cnodeid_t nodenum = INVALID_CNODEID; - - while (++nodenum < MAX_COMPACT_NODES) { - j = LEAST_LEVEL + 3; /* resched & crosscall entries taken */ - while (++j < PERNODE_LEVELS) - if (node_level_to_irq[nodenum][j] == irq) { - *cpunum = 0; /* XXX Fixme */ - return(j); - } - } - printk("Could not identify cpu/level for irq %d\n", irq); - while(1); - return(-1); -} - - -void disable_irq(unsigned int irq_nr) -{ - panic("disable_irq() called ..."); -} - -void enable_irq(unsigned int irq_nr) -{ - panic("enable_irq() called ..."); -} - -/* This is stupid for an Origin which can have thousands of IRQs ... */ -static struct irqaction *irq_action[NR_IRQS]; - -int show_interrupts(struct seq_file *p, void *v) -{ - int i; - struct irqaction * action; - unsigned long flags; - - for (i = 0 ; i < NR_IRQS ; i++) { - local_irq_save(flags); - action = irq_action[i]; - if (!action) - goto skip; - seq_printf(p, "%2d: %8d %c %s", i, kstat_cpu(0).irqs[i], - (action->flags & SA_INTERRUPT) ? '+' : ' ', - action->name); - for (action=action->next; action; action = action->next) { - seq_printf(p, ",%s %s", - (action->flags & SA_INTERRUPT) - ? " +" : "", - action->name); - } - seq_putc(p, '\n'); -skip: - local_irq_restore(flags); - } - return 0; -} - -/* - * do_IRQ handles all normal device IRQ's (the special SMP cross-CPU interrupts - * have their own specific handlers). - */ -static void do_IRQ(cpuid_t thiscpu, int irq, struct pt_regs * regs) -{ - struct irqaction *action; - int do_random; - - irq_enter(thiscpu, irq); - kstat_cpu(thiscpu).irqs[irq]++; - - action = *(irq + irq_action); - if (action) { - if (!(action->flags & SA_INTERRUPT)) - local_irq_enable(); - do_random = 0; - do { - do_random |= action->flags; - action->handler(irq, action->dev_id, regs); - action = action->next; - } while (action); - if (do_random & SA_SAMPLE_RANDOM) - add_interrupt_randomness(irq); - local_irq_disable(); - } - irq_exit(thiscpu, irq); - - if (softirq_pending(thiscpu)) - do_softirq(); -} - -/* - * Find first bit set - */ -static int ms1bit(unsigned long x) -{ - int b; - - if (x >> 32) b = 32, x >>= 32; - else b = 0; - if (x >> 16) b += 16, x >>= 16; - if (x >> 8) b += 8, x >>= 8; - if (x >> 4) b += 4, x >>= 4; - if (x >> 2) b += 2, x >>= 2; - - return b + (int) (x >> 1); -} - -/* - * This code is unnecessarily complex, because we do SA_INTERRUPT - * intr enabling. Basically, once we grab the set of intrs we need - * to service, we must mask _all_ these interrupts; firstly, to make - * sure the same intr does not intr again, causing recursion that - * can lead to stack overflow. Secondly, we can not just mask the - * one intr we are do_IRQing, because the non-masked intrs in the - * first set might intr again, causing multiple servicings of the - * same intr. This effect is mostly seen for intercpu intrs. - * Kanoj 05.13.00 - */ -void ip27_do_irq(struct pt_regs *regs) -{ - int irq, swlevel; - hubreg_t pend0, mask0; - cpuid_t thiscpu = smp_processor_id(); - int pi_int_mask0 = ((cputoslice(thiscpu) == 0) ? - PI_INT_MASK0_A : PI_INT_MASK0_B); - - /* copied from Irix intpend0() */ - while (((pend0 = LOCAL_HUB_L(PI_INT_PEND0)) & - (mask0 = LOCAL_HUB_L(pi_int_mask0))) != 0) { - pend0 &= mask0; /* Pick intrs we should look at */ - if (pend0) { - /* Prevent any of the picked intrs from recursing */ - LOCAL_HUB_S(pi_int_mask0, mask0 & ~(pend0)); - do { - swlevel = ms1bit(pend0); - LOCAL_HUB_CLR_INTR(swlevel); - /* "map" swlevel to irq */ - irq = LEVEL_TO_IRQ(thiscpu, swlevel); - do_IRQ(thiscpu, irq, regs); - /* clear bit in pend0 */ - pend0 ^= 1ULL << swlevel; - } while(pend0); - /* Now allow the set of serviced intrs again */ - LOCAL_HUB_S(pi_int_mask0, mask0); - LOCAL_HUB_L(PI_INT_PEND0); - } - } -} - - -/* Startup one of the (PCI ...) IRQs routes over a bridge. */ -static unsigned int bridge_startup(unsigned int irq) -{ - bridgereg_t device; - bridge_t *bridge; - int pin, swlevel; - cpuid_t cpu; - nasid_t master = NASID_FROM_PCI_IRQ(irq); - - bridge = (bridge_t *) NODE_SWIN_BASE(master, WID_FROM_PCI_IRQ(irq)); - pin = SLOT_FROM_PCI_IRQ(irq); - cpu = IRQ_TO_CPU(irq); - - DBG("bridge_startup(): irq= 0x%x pin=%d\n", irq, pin); - /* - * "map" irq to a swlevel greater than 6 since the first 6 bits - * of INT_PEND0 are taken - */ - swlevel = alloc_level(cpu, irq); - intr_connect_level(cpu, swlevel); - - bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (master << 8)); - bridge->b_int_enable |= (1 << pin); - /* more stuff in int_enable reg */ - bridge->b_int_enable |= 0x7ffffe00; - - /* - * XXX This only works if b_int_device is initialized to 0! - * We program the bridge to have a 1:1 mapping between devices - * (slots) and intr pins. - */ - device = bridge->b_int_device; - device |= (pin << (pin*3)); - bridge->b_int_device = device; - - bridge->b_widget.w_tflush; /* Flush */ - - return 0; /* Never anything pending. */ -} - -/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */ -static unsigned int bridge_shutdown(unsigned int irq) -{ - bridge_t *bridge; - int pin, swlevel; - cpuid_t cpu; - - bridge = (bridge_t *) NODE_SWIN_BASE(NASID_FROM_PCI_IRQ(irq), - WID_FROM_PCI_IRQ(irq)); - DBG("bridge_shutdown: irq 0x%x\n", irq); - pin = SLOT_FROM_PCI_IRQ(irq); - - /* - * map irq to a swlevel greater than 6 since the first 6 bits - * of INT_PEND0 are taken - */ - swlevel = find_level(&cpu, irq); - intr_disconnect_level(cpu, swlevel); - LEVEL_TO_IRQ(cpu, swlevel) = -1; - - bridge->b_int_enable &= ~(1 << pin); - bridge->b_widget.w_tflush; /* Flush */ - - return 0; /* Never anything pending. */ -} - -void irq_debug(void) -{ - bridge_t *bridge = (bridge_t *) 0x9200000008000000; - - printk("bridge->b_int_status = 0x%x\n", bridge->b_int_status); - printk("bridge->b_int_enable = 0x%x\n", bridge->b_int_enable); - printk("PI_INT_PEND0 = 0x%lx\n", LOCAL_HUB_L(PI_INT_PEND0)); - printk("PI_INT_MASK0_A = 0x%lx\n", LOCAL_HUB_L(PI_INT_MASK0_A)); -} - -int setup_irq(unsigned int irq, struct irqaction *new) -{ - int shared = 0; - struct irqaction *old, **p; - unsigned long flags; - - DBG("setup_irq: 0x%x\n", irq); - if (irq >= NR_IRQS) { - printk("IRQ array overflow %d\n", irq); - while(1); - } - if (new->flags & SA_SAMPLE_RANDOM) - rand_initialize_irq(irq); - - save_and_cli(flags); - p = irq_action + irq; - if ((old = *p) != NULL) { - /* Can't share interrupts unless both agree to */ - if (!(old->flags & new->flags & SA_SHIRQ)) { - restore_flags(flags); - return -EBUSY; - } - - /* Add new interrupt at end of irq queue */ - do { - p = &old->next; - old = *p; - } while (old); - shared = 1; - } - - *p = new; - - if ((!shared) && (irq >= BASE_PCI_IRQ)) { - bridge_startup(irq); - } - restore_flags(flags); - - return 0; -} - -int request_irq(unsigned int irq, - void (*handler)(int, void *, struct pt_regs *), - unsigned long irqflags, const char * devname, void *dev_id) -{ - int retval; - struct irqaction *action; - - DBG("request_irq(): irq= 0x%x\n", irq); - if (!handler) - return -EINVAL; - - action = (struct irqaction *)kmalloc(sizeof(*action), GFP_KERNEL); - if (!action) - return -ENOMEM; - - action->handler = handler; - action->flags = irqflags; - action->mask = 0; - action->name = devname; - action->next = NULL; - action->dev_id = dev_id; - - DBG("request_irq(): %s devid= 0x%x\n", devname, dev_id); - retval = setup_irq(irq, action); - DBG("request_irq(): retval= %d\n", retval); - if (retval) - kfree(action); - return retval; -} - -void free_irq(unsigned int irq, void *dev_id) -{ - struct irqaction * action, **p; - unsigned long flags; - - if (irq >= NR_IRQS) { - printk("Trying to free IRQ%d\n", irq); - return; - } - for (p = irq + irq_action; (action = *p) != NULL; p = &action->next) { - if (action->dev_id != dev_id) - continue; - - /* Found it - now free it */ - save_and_cli(flags); - *p = action->next; - if (irq >= BASE_PCI_IRQ) - bridge_shutdown(irq); - restore_flags(flags); - kfree(action); - return; - } - printk("Trying to free free IRQ%d\n",irq); -} - -/* Useless ISA nonsense. */ -unsigned long probe_irq_on (void) -{ - panic("probe_irq_on called!\n"); - return 0; -} - -int probe_irq_off (unsigned long irqs) -{ - return 0; -} - -void __init init_IRQ(void) -{ - set_except_vector(0, ip27_irq); -} - -#ifdef CONFIG_SMP - -/* - * This following are the global intr on off routines, copied almost - * entirely from i386 code. - */ - -int global_irq_holder = NO_PROC_ID; -spinlock_t global_irq_lock = SPIN_LOCK_UNLOCKED; - -extern void show_stack(unsigned long* esp); - -static void show(char * str) -{ - int i; - int cpu = smp_processor_id(); - - printk("\n%s, CPU %d:\n", str, cpu); - printk("irq: %d [",irqs_running()); - for(i=0;i < smp_num_cpus;i++) - printk(" %d",local_irq_count(i)); - printk(" ]\nbh: %d [",spin_is_locked(&global_bh_lock) ? 1 : 0); - for(i=0;i < smp_num_cpus;i++) - printk(" %d",local_bh_count(i)); - - printk(" ]\nStack dumps:"); - for(i = 0; i < smp_num_cpus; i++) { - if (i == cpu) - continue; - printk("\nCPU %d:",i); - printk("Code not developed yet\n"); - /* show_stack(0); */ - } - printk("\nCPU %d:",cpu); - printk("Code not developed yet\n"); - /* show_stack(NULL); */ - printk("\n"); -} - -#define MAXCOUNT 100000000 -#define SYNC_OTHER_CORES(x) udelay(x+1) - -static inline void wait_on_irq(int cpu) -{ - int count = MAXCOUNT; - - for (;;) { - - /* - * Wait until all interrupts are gone. Wait - * for bottom half handlers unless we're - * already executing in one.. - */ - if (!irqs_running()) - if (local_bh_count(cpu) || !spin_is_locked(&global_bh_lock)) - break; - - /* Duh, we have to loop. Release the lock to avoid deadlocks */ - spin_unlock(&global_irq_lock); - - for (;;) { - if (!--count) { - show("wait_on_irq"); - count = ~0; - } - local_irq_enable(); - SYNC_OTHER_CORES(cpu); - local_irq_disable(); - if (irqs_running()) - continue; - if (spin_is_locked(&global_irq_lock)) - continue; - if (!local_bh_count(cpu) && spin_is_locked(&global_bh_lock)) - continue; - if (spin_trylock(&global_irq_lock)) - break; - } - } -} - -void synchronize_irq(void) -{ - if (irqs_running()) { - /* Stupid approach */ - cli(); - sti(); - } -} - -static inline void get_irqlock(int cpu) -{ - if (!spin_trylock(&global_irq_lock)) { - /* do we already hold the lock? */ - if ((unsigned char) cpu == global_irq_holder) - return; - /* Uhhuh.. Somebody else got it. Wait.. */ - spin_lock(&global_irq_lock); - } - /* - * We also to make sure that nobody else is running - * in an interrupt context. - */ - wait_on_irq(cpu); - - /* - * Ok, finally.. - */ - global_irq_holder = cpu; -} - -void __global_cli(void) -{ - unsigned int flags; - - local_save_flags(flags); - if (flags & ST0_IE) { - int cpu = smp_processor_id(); - local_irq_disable(); - if (!local_irq_count(cpu)) - get_irqlock(cpu); - } -} - -void __global_sti(void) -{ - int cpu = smp_processor_id(); - - if (!local_irq_count(cpu)) - release_irqlock(cpu); - local_irq_enable(); -} - -/* - * SMP flags value to restore to: - * 0 - global cli - * 1 - global sti - * 2 - local cli - * 3 - local sti - */ -unsigned long __global_save_flags(void) -{ - int retval; - int local_enabled; - unsigned long flags; - int cpu = smp_processor_id(); - - local_save_flags(flags); - local_enabled = (flags & ST0_IE); - /* default to local */ - retval = 2 + local_enabled; - - /* check for global flags if we're not in an interrupt */ - if (!local_irq_count(cpu)) { - if (local_enabled) - retval = 1; - if (global_irq_holder == cpu) - retval = 0; - } - return retval; -} - -void __global_restore_flags(unsigned long flags) -{ - switch (flags) { - case 0: - __global_cli(); - break; - case 1: - __global_sti(); - break; - case 2: - local_irq_disable(); - break; - case 3: - local_irq_enable(); - break; - default: - printk("global_restore_flags: %08lx\n", flags); - } -} - -#endif /* CONFIG_SMP */ - -/* - * Get values that vary depending on which CPU and bit we're operating on. - */ -static hub_intmasks_t *intr_get_ptrs(cpuid_t cpu, int bit, int *new_bit, - hubreg_t **intpend_masks, int *ip) -{ - hub_intmasks_t *hub_intmasks; - - hub_intmasks = &cpu_data[cpu].p_intmasks; - if (bit < N_INTPEND_BITS) { - *intpend_masks = hub_intmasks->intpend0_masks; - *ip = 0; - *new_bit = bit; - } else { - *intpend_masks = hub_intmasks->intpend1_masks; - *ip = 1; - *new_bit = bit - N_INTPEND_BITS; - } - return hub_intmasks; -} - -int intr_connect_level(int cpu, int bit) -{ - int ip; - int slice = cputoslice(cpu); - volatile hubreg_t *mask_reg; - hubreg_t *intpend_masks; - nasid_t nasid = COMPACT_TO_NASID_NODEID(cputocnode(cpu)); - - (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks, &ip); - - /* Make sure it's not already pending when we connect it. */ - REMOTE_HUB_CLR_INTR(nasid, bit + ip * N_INTPEND_BITS); - - intpend_masks[0] |= (1ULL << (u64)bit); - - if (ip == 0) { - mask_reg = REMOTE_HUB_ADDR(nasid, PI_INT_MASK0_A + - PI_INT_MASK_OFFSET * slice); - } else { - mask_reg = REMOTE_HUB_ADDR(nasid, PI_INT_MASK1_A + - PI_INT_MASK_OFFSET * slice); - } - HUB_S(mask_reg, intpend_masks[0]); - return(0); -} - -int intr_disconnect_level(int cpu, int bit) -{ - int ip; - int slice = cputoslice(cpu); - volatile hubreg_t *mask_reg; - hubreg_t *intpend_masks; - nasid_t nasid = COMPACT_TO_NASID_NODEID(cputocnode(cpu)); - - (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks, &ip); - intpend_masks[0] &= ~(1ULL << (u64)bit); - if (ip == 0) { - mask_reg = REMOTE_HUB_ADDR(nasid, PI_INT_MASK0_A + - PI_INT_MASK_OFFSET * slice); - } else { - mask_reg = REMOTE_HUB_ADDR(nasid, PI_INT_MASK1_A + - PI_INT_MASK_OFFSET * slice); - } - HUB_S(mask_reg, intpend_masks[0]); - return(0); -} - - -void handle_resched_intr(int irq, void *dev_id, struct pt_regs *regs) -{ - /* Nothing, the return from intr will work for us */ -} - -extern void smp_call_function_interrupt(void); - -void install_cpuintr(int cpu) -{ -#ifdef CONFIG_SMP -#if (CPUS_PER_NODE == 2) - static int done = 0; - - /* - * This is a hack till we have a pernode irqlist. Currently, - * just have the master cpu set up the handlers for the per - * cpu irqs. - */ - if (done == 0) { - int j; - - if (request_irq(CPU_RESCHED_A_IRQ, handle_resched_intr, - 0, "resched", 0)) - panic("intercpu intr unconnectible\n"); - if (request_irq(CPU_RESCHED_B_IRQ, handle_resched_intr, - 0, "resched", 0)) - panic("intercpu intr unconnectible\n"); - if (request_irq(CPU_CALL_A_IRQ, smp_call_function_interrupt, - 0, "callfunc", 0)) - panic("intercpu intr unconnectible\n"); - if (request_irq(CPU_CALL_B_IRQ, smp_call_function_interrupt, - 0, "callfunc", 0)) - panic("intercpu intr unconnectible\n"); - - for (j = 0; j < PERNODE_LEVELS; j++) - LEVEL_TO_IRQ(0, j) = -1; - LEVEL_TO_IRQ(0, FAST_IRQ_TO_LEVEL(CPU_RESCHED_A_IRQ)) = - CPU_RESCHED_A_IRQ; - LEVEL_TO_IRQ(0, FAST_IRQ_TO_LEVEL(CPU_RESCHED_B_IRQ)) = - CPU_RESCHED_B_IRQ; - LEVEL_TO_IRQ(0, FAST_IRQ_TO_LEVEL(CPU_CALL_A_IRQ)) = - CPU_CALL_A_IRQ; - LEVEL_TO_IRQ(0, FAST_IRQ_TO_LEVEL(CPU_CALL_B_IRQ)) = - CPU_CALL_B_IRQ; - for (j = 1; j < MAX_COMPACT_NODES; j++) - memcpy(&node_level_to_irq[j][0], - &node_level_to_irq[0][0], - sizeof(node_level_to_irq[0][0])*PERNODE_LEVELS); - - done = 1; - } - - intr_connect_level(cpu, FAST_IRQ_TO_LEVEL(CPU_RESCHED_A_IRQ + - cputoslice(cpu))); - intr_connect_level(cpu, FAST_IRQ_TO_LEVEL(CPU_CALL_A_IRQ + - cputoslice(cpu))); -#else /* CPUS_PER_NODE */ -#error Must redefine this for more than 2 CPUS. -#endif /* CPUS_PER_NODE */ -#endif /* CONFIG_SMP */ -} - -void install_tlbintr(int cpu) -{ -#if 0 - int intr_bit = N_INTPEND_BITS + TLB_INTR_A + cputoslice(cpu); - - intr_connect_level(cpu, intr_bit); -#endif -} --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-irq-glue.S 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,64 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#include -#include -#include -#include - - .text - .set noat - .align 5 -NESTED(ip27_irq, PT_SIZE, sp) - SAVE_ALL - CLI - .set at - - /* IP27 may signal interrupt which we're not interested in. - Mask them out. */ - mfc0 s0, CP0_CAUSE - mfc0 t0, CP0_STATUS - and s0, t0 - - /* First check for RT interrupt. */ - andi a0, s0, CAUSEF_IP4 - beqz a0, 1f - - /* Ok, a timer interrupt. */ - move a0, sp - jal rt_timer_interrupt - - j ret_from_irq - -1: andi a0, s0, (CAUSEF_IP2 | CAUSEF_IP3) - beqz a0, 1f - - /* ... a device interrupt ... */ - move a0, sp - jal ip27_do_irq - - j ret_from_irq - -1: -#if 1 - mfc0 a1, CP0_STATUS - srl a1, a1, 8 - andi a1, 0xff - - mfc0 a2, CP0_CAUSE - srl a2, a2, 8 - andi a2, 0xff - - move a3, s0 - PRINT("Spurious interrupt, c0_status = %02x, c0_cause = %02x, pending %02x.\n") - ld a1, PT_EPC(sp) -0: b 0b -#endif - - j ret_from_irq - END(ip27_irq) --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-klconfig.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,135 +0,0 @@ -/* - * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -klinfo_t *find_component(lboard_t *brd, klinfo_t *kli, unsigned char struct_type) -{ - int index, j; - - if (kli == (klinfo_t *)NULL) { - index = 0; - } else { - for (j = 0; j < KLCF_NUM_COMPS(brd); j++) - if (kli == KLCF_COMP(brd, j)) - break; - index = j; - if (index == KLCF_NUM_COMPS(brd)) { - printk("find_component: Bad pointer: 0x%p\n", kli); - return (klinfo_t *)NULL; - } - index++; /* next component */ - } - - for (; index < KLCF_NUM_COMPS(brd); index++) { - kli = KLCF_COMP(brd, index); - if (KLCF_COMP_TYPE(kli) == struct_type) - return kli; - } - - /* Didn't find it. */ - return (klinfo_t *)NULL; -} - -klinfo_t *find_first_component(lboard_t *brd, unsigned char struct_type) -{ - return find_component(brd, (klinfo_t *)NULL, struct_type); -} - -lboard_t * find_lboard(lboard_t *start, unsigned char brd_type) -{ - /* Search all boards stored on this node. */ - while (start) { - if (start->brd_type == brd_type) - return start; - start = KLCF_NEXT(start); - } - /* Didn't find it. */ - return (lboard_t *)NULL; -} - -lboard_t * find_lboard_class(lboard_t *start, unsigned char brd_type) -{ - /* Search all boards stored on this node. */ - while (start) { - if (KLCLASS(start->brd_type) == KLCLASS(brd_type)) - return start; - start = KLCF_NEXT(start); - } - - /* Didn't find it. */ - return (lboard_t *)NULL; -} - -cnodeid_t get_cpu_cnode(cpuid_t cpu) -{ - return CPUID_TO_COMPACT_NODEID(cpu); -} - -klcpu_t * nasid_slice_to_cpuinfo(nasid_t nasid, int slice) -{ - lboard_t *brd; - klcpu_t *acpu; - - if (!(brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IP27))) - return (klcpu_t *)NULL; - - if (!(acpu = (klcpu_t *)find_first_component(brd, KLSTRUCT_CPU))) - return (klcpu_t *)NULL; - - do { - if ((acpu->cpu_info.physid) == slice) - return acpu; - } while ((acpu = (klcpu_t *)find_component(brd, (klinfo_t *)acpu, - KLSTRUCT_CPU))); - return (klcpu_t *)NULL; -} - -klcpu_t * sn_get_cpuinfo(cpuid_t cpu) -{ - nasid_t nasid; - int slice; - klcpu_t *acpu; - gda_t *gdap = GDA; - cnodeid_t cnode; - - if (!(cpu < MAXCPUS)) { - printk("sn_get_cpuinfo: illegal cpuid 0x%lx\n", cpu); - return NULL; - } - - cnode = get_cpu_cnode(cpu); - if (cnode == INVALID_CNODEID) - return NULL; - - if ((nasid = gdap->g_nasidtable[cnode]) == INVALID_NASID) - return NULL; - - for (slice = 0; slice < CPUS_PER_NODE; slice++) { - acpu = nasid_slice_to_cpuinfo(nasid, slice); - if (acpu && acpu->cpu_info.virtid == cpu) - return acpu; - } - return NULL; -} - -int get_cpu_slice(cpuid_t cpu) -{ - klcpu_t *acpu; - - if ((acpu = sn_get_cpuinfo(cpu)) == NULL) - return -1; - return acpu->cpu_info.physid; -} --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-klnuma.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,143 +0,0 @@ -/* - * Ported from IRIX to Linux by Kanoj Sarcar, 06/08/00. - * Copyright 2000 - 2001 Silicon Graphics, Inc. - * Copyright 2000 - 2001 Kanoj Sarcar (kanoj@sgi.com) - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern char _end; -static cpumask_t ktext_repmask; - -/* - * XXX - This needs to be much smarter about where it puts copies of the - * kernel. For example, we should never put a copy on a headless node, - * and we should respect the topology of the machine. - */ -void __init setup_replication_mask(int maxnodes) -{ - static int numa_kernel_replication_ratio; - cnodeid_t cnode; - - /* Set only the master cnode's bit. The master cnode is always 0. */ - CPUMASK_CLRALL(ktext_repmask); - CPUMASK_SETB(ktext_repmask, 0); - - numa_kernel_replication_ratio = 0; -#ifdef CONFIG_REPLICATE_KTEXT -#ifndef CONFIG_MAPPED_KERNEL -#error Kernel replication works with mapped kernel support. No calias support. -#endif - numa_kernel_replication_ratio = 1; -#endif - - for (cnode = 1; cnode < numnodes; cnode++) { - /* See if this node should get a copy of the kernel */ - if (numa_kernel_replication_ratio && - !(cnode % numa_kernel_replication_ratio)) { - - /* Advertise that we have a copy of the kernel */ - CPUMASK_SETB(ktext_repmask, cnode); - } - } - - /* Set up a GDA pointer to the replication mask. */ - GDA->g_ktext_repmask = &ktext_repmask; -} - - -static __init void set_ktext_source(nasid_t client_nasid, nasid_t server_nasid) -{ - kern_vars_t *kvp; - cnodeid_t client_cnode; - - client_cnode = NASID_TO_COMPACT_NODEID(client_nasid); - - kvp = &(PLAT_NODE_DATA(client_cnode)->kern_vars); - - KERN_VARS_ADDR(client_nasid) = (unsigned long)kvp; - - kvp->kv_magic = KV_MAGIC; - - kvp->kv_ro_nasid = server_nasid; - kvp->kv_rw_nasid = master_nasid; - kvp->kv_ro_baseaddr = NODE_CAC_BASE(server_nasid); - kvp->kv_rw_baseaddr = NODE_CAC_BASE(master_nasid); - printk("REPLICATION: ON nasid %d, ktext from nasid %d, kdata from nasid %d\n", client_nasid, server_nasid, master_nasid); -} - -/* XXX - When the BTE works, we should use it instead of this. */ -static __init void copy_kernel(nasid_t dest_nasid) -{ - extern char _stext, _etext; - unsigned long dest_kern_start, source_start, source_end, kern_size; - - source_start = (unsigned long)&_stext; - source_end = (unsigned long)&_etext; - kern_size = source_end - source_start; - - dest_kern_start = CHANGE_ADDR_NASID(MAPPED_KERN_RO_TO_K0(source_start), - dest_nasid); - memcpy((void *)dest_kern_start, (void *)source_start, kern_size); -} - -void __init replicate_kernel_text(int maxnodes) -{ - cnodeid_t cnode; - nasid_t client_nasid; - nasid_t server_nasid; - - server_nasid = master_nasid; - - /* Record where the master node should get its kernel text */ - set_ktext_source(master_nasid, master_nasid); - - for (cnode = 1; cnode < maxnodes; cnode++) { - client_nasid = COMPACT_TO_NASID_NODEID(cnode); - - /* Check if this node should get a copy of the kernel */ - if (CPUMASK_TSTB(ktext_repmask, cnode)) { - server_nasid = client_nasid; - copy_kernel(server_nasid); - } - - /* Record where this node should get its kernel text */ - set_ktext_source(client_nasid, server_nasid); - } -} - -/* - * Return pfn of first free page of memory on a node. PROM may allocate - * data structures on the first couple of pages of the first slot of each - * node. If this is the case, getfirstfree(node) > getslotstart(node, 0). - */ -pfn_t node_getfirstfree(cnodeid_t cnode) -{ - unsigned long loadbase = CKSEG0; - nasid_t nasid = COMPACT_TO_NASID_NODEID(cnode); - unsigned long offset; - -#ifdef CONFIG_MAPPED_KERNEL - loadbase = CKSSEG + 16777216; -#endif - offset = PAGE_ALIGN((unsigned long)(&_end)) - loadbase; - if ((cnode == 0) || (CPUMASK_TSTB(ktext_repmask, cnode))) - return (TO_NODE(nasid, offset) >> PAGE_SHIFT); - else - return (KDM_TO_PHYS(PAGE_ALIGN(SYMMON_STK_ADDR(nasid, 0))) >> - PAGE_SHIFT); -} - --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-memory.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,337 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 by Ralf Baechle - * Copyright (C) 2000 by Silicon Graphics, Inc. - * - * On SGI IP27 the ARC memory configuration data is completly bogus but - * alternate easier to use mechanisms are available. - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* ip27-klnuma.c */ -extern pfn_t node_getfirstfree(cnodeid_t cnode); - -#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT) -#define SLOT_IGNORED 0xffff - -short slot_lastfilled_cache[MAX_COMPACT_NODES]; -unsigned short slot_psize_cache[MAX_COMPACT_NODES][MAX_MEM_SLOTS]; -static pfn_t numpages; - -plat_pg_data_t *plat_node_data[MAX_COMPACT_NODES]; -bootmem_data_t plat_node_bdata[MAX_COMPACT_NODES]; - -int numa_debug(void) -{ - printk("NUMA debug\n"); - *(int *)0 = 0; - return(0); -} - -/* - * Return the number of pages of memory provided by the given slot - * on the specified node. - */ -pfn_t slot_getsize(cnodeid_t node, int slot) -{ - return (pfn_t) slot_psize_cache[node][slot]; -} - -/* - * Return highest slot filled - */ -int node_getlastslot(cnodeid_t node) -{ - return (int) slot_lastfilled_cache[node]; -} - -/* - * Return the pfn of the last free page of memory on a node. - */ -pfn_t node_getmaxclick(cnodeid_t node) -{ - pfn_t slot_psize; - int slot; - - /* - * Start at the top slot. When we find a slot with memory in it, - * that's the winner. - */ - for (slot = (node_getnumslots(node) - 1); slot >= 0; slot--) { - if ((slot_psize = slot_getsize(node, slot))) { - if (slot_psize == SLOT_IGNORED) - continue; - /* Return the basepfn + the slot size, minus 1. */ - return slot_getbasepfn(node, slot) + slot_psize - 1; - } - } - - /* - * If there's no memory on the node, return 0. This is likely - * to cause problems. - */ - return (pfn_t)0; -} - -static pfn_t slot_psize_compute(cnodeid_t node, int slot) -{ - nasid_t nasid; - lboard_t *brd; - klmembnk_t *banks; - unsigned long size; - - nasid = COMPACT_TO_NASID_NODEID(node); - /* Find the node board */ - brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IP27); - if (!brd) - return 0; - - /* Get the memory bank structure */ - banks = (klmembnk_t *)find_first_component(brd, KLSTRUCT_MEMBNK); - if (!banks) - return 0; - - /* Size in _Megabytes_ */ - size = (unsigned long)banks->membnk_bnksz[slot/4]; - - /* hack for 128 dimm banks */ - if (size <= 128) { - if (slot%4 == 0) { - size <<= 20; /* size in bytes */ - return(size >> PAGE_SHIFT); - } else { - return 0; - } - } else { - size /= 4; - size <<= 20; - return(size >> PAGE_SHIFT); - } -} - -pfn_t szmem(pfn_t fpage, pfn_t maxpmem) -{ - cnodeid_t node; - int slot, numslots; - pfn_t num_pages = 0, slot_psize; - pfn_t slot0sz = 0, nodebytes; /* Hack to detect problem configs */ - int ignore; - - for (node = 0; node < numnodes; node++) { - numslots = node_getnumslots(node); - ignore = nodebytes = 0; - for (slot = 0; slot < numslots; slot++) { - slot_psize = slot_psize_compute(node, slot); - if (slot == 0) slot0sz = slot_psize; - /* - * We need to refine the hack when we have replicated - * kernel text. - */ - nodebytes += SLOT_SIZE; - if ((nodebytes >> PAGE_SHIFT) * (sizeof(struct page)) > - (slot0sz << PAGE_SHIFT)) - ignore = 1; - if (ignore && slot_psize) { - printk("Ignoring slot %d onwards on node %d\n", - slot, node); - slot_psize_cache[node][slot] = SLOT_IGNORED; - slot = numslots; - continue; - } - num_pages += slot_psize; - slot_psize_cache[node][slot] = - (unsigned short) slot_psize; - if (slot_psize) - slot_lastfilled_cache[node] = slot; - } - } - if (maxpmem) - return((maxpmem > num_pages) ? num_pages : maxpmem); - else - return num_pages; -} - -/* - * Currently, the intranode memory hole support assumes that each slot - * contains at least 32 MBytes of memory. We assume all bootmem data - * fits on the first slot. - */ -void __init prom_meminit(void) -{ - extern void mlreset(void); - cnodeid_t node; - pfn_t slot_firstpfn, slot_lastpfn, slot_freepfn; - unsigned long bootmap_size; - int node_datasz; - - node_datasz = PFN_UP(sizeof(plat_pg_data_t)); - mlreset(); - numpages = szmem(0, 0); - for (node = (numnodes - 1); node >= 0; node--) { - slot_firstpfn = slot_getbasepfn(node, 0); - slot_lastpfn = slot_firstpfn + slot_getsize(node, 0); - slot_freepfn = node_getfirstfree(node); - /* Foll line hack for non discontigmem; remove once discontigmem - * becomes the default. */ - max_low_pfn = (slot_lastpfn - slot_firstpfn); - - /* - * Allocate the node data structure on the node first. - */ - plat_node_data[node] = (plat_pg_data_t *)(__va(slot_freepfn \ - << PAGE_SHIFT)); - NODE_DATA(node)->bdata = plat_node_bdata + node; - slot_freepfn += node_datasz; - bootmap_size = init_bootmem_node(NODE_DATA(node), slot_freepfn, - slot_firstpfn, slot_lastpfn); - free_bootmem_node(NODE_DATA(node), slot_firstpfn << PAGE_SHIFT, - (slot_lastpfn - slot_firstpfn) << PAGE_SHIFT); - reserve_bootmem_node(NODE_DATA(node), slot_firstpfn << PAGE_SHIFT, - ((slot_freepfn - slot_firstpfn) << PAGE_SHIFT) + bootmap_size); - } - printk("Total memory probed : 0x%lx pages\n", numpages); -} - -int __init page_is_ram(unsigned long pagenr) -{ - return 1; -} - -void __init -prom_free_prom_memory (void) -{ - /* We got nothing to free here ... */ -} - -#ifdef CONFIG_DISCONTIGMEM - -static pfn_t pagenr = 0; - -void __init paging_init(void) -{ - pmd_t *pmd = kpmdtbl; - pte_t *pte = kptbl; - - cnodeid_t node; - unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0}; - int i; - - /* Initialize the entire pgd. */ - pgd_init((unsigned long)swapper_pg_dir); - pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table); - memset((void *)invalid_pte_table, 0, sizeof(pte_t) * PTRS_PER_PTE); - - /* This is for vmalloc */ - memset((void *)kptbl, 0, PAGE_SIZE << KPTBL_PAGE_ORDER); - memset((void *)kpmdtbl, 0, PAGE_SIZE); - pgd_set(swapper_pg_dir, kpmdtbl); - for (i = 0; i < (1 << KPTBL_PAGE_ORDER); pmd++,i++,pte+=PTRS_PER_PTE) - pmd_val(*pmd) = (unsigned long)pte; - - for (node = 0; node < numnodes; node++) { - pfn_t start_pfn = slot_getbasepfn(node, 0); - pfn_t end_pfn = node_getmaxclick(node); - - zones_size[ZONE_DMA] = end_pfn + 1 - start_pfn; - free_area_init_node(node, NODE_DATA(node), 0, zones_size, - start_pfn, 0); - } -} - -void __init mem_init(void) -{ - extern char _stext, _etext, _fdata, _edata; - extern char __init_begin, __init_end; - extern unsigned long setup_zero_pages(void); - cnodeid_t nid; - unsigned long tmp; - unsigned long codesize, datasize, initsize; - int slot, numslots; - struct page *pg, *pslot; - - num_physpages = numpages; /* memory already sized by szmem */ - max_mapnr = pagenr; /* already found during paging_init */ - high_memory = (void *) __va(max_mapnr << PAGE_SHIFT); - - for (nid = 0; nid < numnodes; nid++) { - - /* - * Hack till free_area_init_core() zeroes free_pages - */ - for (tmp = 0; tmp < MAX_NR_ZONES; tmp++) - PLAT_NODE_DATA(nid)->gendata.node_zones[tmp].free_pages=0; - /* - * This will free up the bootmem, ie, slot 0 memory. - */ - totalram_pages += free_all_bootmem_node(NODE_DATA(nid)); - - /* - * We need to manually do the other slots. - */ - pg = NODE_DATA(nid)->node_mem_map + slot_getsize(nid, 0); - numslots = node_getlastslot(nid); - for (slot = 1; slot <= numslots; slot++) { - pslot = NODE_DATA(nid)->node_mem_map + - slot_getbasepfn(nid, slot) - slot_getbasepfn(nid, 0); - - /* - * Mark holes in previous slot. May also want to - * free up the pages that hold the memmap entries. - */ - while (pg < pslot) { - pg++; - } - - /* - * Free valid memory in current slot. - */ - pslot += slot_getsize(nid, slot); - while (pg < pslot) { - /* if (!page_is_ram(pgnr)) continue; */ - /* commented out until page_is_ram works */ - ClearPageReserved(pg); - atomic_set(&pg->count, 1); - __free_page(pg); - totalram_pages++; - pg++; pgnr++; - } - } - } - - totalram_pages -= setup_zero_pages(); /* This comes from node 0 */ - - codesize = (unsigned long) &_etext - (unsigned long) &_stext; - datasize = (unsigned long) &_edata - (unsigned long) &_fdata; - initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin; - - tmp = (unsigned long) nr_free_pages(); - printk("Memory: %luk/%luk available (%ldk kernel code, %ldk reserved, " - "%ldk data, %ldk init)\n", - tmp << (PAGE_SHIFT-10), - num_physpages << (PAGE_SHIFT-10), - codesize >> 10, - (num_physpages - tmp) << (PAGE_SHIFT-10), - datasize >> 10, - initsize >> 10); -} - -#endif /* CONFIG_DISCONTIGMEM */ --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-nmi.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,168 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if 0 -#define NODE_NUM_CPUS(n) CNODE_NUM_CPUS(n) -#else -#define NODE_NUM_CPUS(n) CPUS_PER_NODE -#endif - -#define CNODEID_NONE (cnodeid_t)-1 -#define enter_panic_mode() spin_lock(&nmi_lock) - -typedef unsigned long machreg_t; - -spinlock_t nmi_lock = SPIN_LOCK_UNLOCKED; - -/* - * Lets see what else we need to do here. Set up sp, gp? - */ -void nmi_dump(void) -{ - void cont_nmi_dump(void); - - cont_nmi_dump(); -} - -void install_cpu_nmi_handler(int slice) -{ - nmi_t *nmi_addr; - - nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice); - if (nmi_addr->call_addr) - return; - nmi_addr->magic = NMI_MAGIC; - nmi_addr->call_addr = (void *)nmi_dump; - nmi_addr->call_addr_c = - (void *)(~((unsigned long)(nmi_addr->call_addr))); - nmi_addr->call_parm = 0; -} - -/* - * Copy the cpu registers which have been saved in the IP27prom format - * into the eframe format for the node under consideration. - */ - -void -nmi_cpu_eframe_save(nasid_t nasid, - int slice) -{ - int i, numberof_nmi_cpu_regs; - machreg_t *prom_format; - - /* Get the total number of registers being saved by the prom */ - numberof_nmi_cpu_regs = sizeof(struct reg_struct) / sizeof(machreg_t); - - /* Get the pointer to the current cpu's register set. */ - prom_format = - (machreg_t *)(TO_UNCAC(TO_NODE(nasid, IP27_NMI_KREGS_OFFSET)) + - slice * IP27_NMI_KREGS_CPU_SIZE); - - printk("NMI nasid %d: slice %d\n", nasid, slice); - for (i = 0; i < numberof_nmi_cpu_regs; i++) - printk("0x%lx ", prom_format[i]); - printk("\n\n"); -} - -/* - * Copy the cpu registers which have been saved in the IP27prom format - * into the eframe format for the node under consideration. - */ -void -nmi_node_eframe_save(cnodeid_t cnode) -{ - int cpu; - nasid_t nasid; - - /* Make sure that we have a valid node */ - if (cnode == CNODEID_NONE) - return; - - nasid = COMPACT_TO_NASID_NODEID(cnode); - if (nasid == INVALID_NASID) - return; - - /* Save the registers into eframe for each cpu */ - for(cpu = 0; cpu < NODE_NUM_CPUS(cnode); cpu++) - nmi_cpu_eframe_save(nasid, cpu); -} - -/* - * Save the nmi cpu registers for all cpus in the system. - */ -void -nmi_eframes_save(void) -{ - cnodeid_t cnode; - - for(cnode = 0 ; cnode < numnodes; cnode++) - nmi_node_eframe_save(cnode); -} - -void -cont_nmi_dump(void) -{ -#ifndef REAL_NMI_SIGNAL - static atomic_t nmied_cpus = ATOMIC_INIT(0); - - atomic_inc(&nmied_cpus); -#endif - /* - * Use enter_panic_mode to allow only 1 cpu to proceed - */ - enter_panic_mode(); - -#ifdef REAL_NMI_SIGNAL - /* - * Wait up to 15 seconds for the other cpus to respond to the NMI. - * If a cpu has not responded after 10 sec, send it 1 additional NMI. - * This is for 2 reasons: - * - sometimes a MMSC fail to NMI all cpus. - * - on 512p SN0 system, the MMSC will only send NMIs to - * half the cpus. Unfortunately, we don't know which cpus may be - * NMIed - it depends on how the site chooses to configure. - * - * Note: it has been measure that it takes the MMSC up to 2.3 secs to - * send NMIs to all cpus on a 256p system. - */ - for (i=0; i < 1500; i++) { - for (node=0; node < numnodes; node++) - if (NODEPDA(node)->dump_count == 0) - break; - if (node == numnodes) - break; - if (i == 1000) { - for (node=0; node < numnodes; node++) - if (NODEPDA(node)->dump_count == 0) { - cpu = CNODE_TO_CPU_BASE(node); - for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) { - CPUMASK_SETB(nmied_cpus, cpu); - /* - * cputonasid, cputoslice - * needs kernel cpuid - */ - SEND_NMI((cputonasid(cpu)), (cputoslice(cpu))); - } - } - - } - udelay(10000); - } -#else - while (atomic_read(&nmied_cpus) != smp_num_cpus); -#endif - - /* - * Save the nmi cpu registers for all cpu in the eframe format. - */ - nmi_eframes_save(); - LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET); -} --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-pci.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,406 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Max #PCI busses we can handle; ie, max #PCI bridges. - */ -#define MAX_PCI_BUSSES 40 - -/* - * Max #PCI devices (like scsi controllers) we handle on a bus. - */ -#define MAX_DEVICES_PER_PCIBUS 8 - -/* - * No locking needed until PCI initialization is done parallely. - */ -int irqstore[MAX_PCI_BUSSES][MAX_DEVICES_PER_PCIBUS]; -int lastirq = BASE_PCI_IRQ; - -/* - * Translate from irq to software PCI bus number and PCI slot. - */ -int irq_to_bus[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS]; -int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS]; - -/* - * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is - * not really documented, so right now I can't write code which uses it. - * Therefore we use type 0 accesses for now even though they won't work - * correcly for PCI-to-PCI bridges. - */ -#define CF0_READ_PCI_CFG(dev,where,value,bm,mask) \ -do { \ - bridge_t *bridge; \ - int slot = PCI_SLOT(dev->devfn); \ - int fn = PCI_FUNC(dev->devfn); \ - volatile u32 *addr; \ - u32 cf, __bit; \ - unsigned int bus_id = (unsigned) dev->bus->number; \ - \ - bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], \ - bus_to_wid[bus_id]); \ - \ - if (dev->vendor == PCI_VENDOR_ID_SGI \ - && dev->device == PCI_DEVICE_ID_SGI_IOC3 \ - && ((where >= 0x14 && where < 0x40) || (where >= 0x48))) { \ - *value = 0; \ - return PCIBIOS_SUCCESSFUL; \ - } \ - \ - __bit = (((where) & (bm)) << 3); \ - addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; \ - if (get_dbe(cf, addr)) \ - return PCIBIOS_DEVICE_NOT_FOUND; \ - *value = (cf >> __bit) & (mask); \ - return PCIBIOS_SUCCESSFUL; \ -} while (0) - -static int -pci_conf0_read_config_byte(struct pci_dev *dev, int where, u8 *value) -{ - CF0_READ_PCI_CFG(dev,where,value,3,0xff); -} - -static int -pci_conf0_read_config_word(struct pci_dev *dev, int where, u16 *value) -{ - CF0_READ_PCI_CFG(dev,where,value,2,0xffff); -} - -static int -pci_conf0_read_config_dword(struct pci_dev *dev, int where, u32 *value) -{ - CF0_READ_PCI_CFG(dev,where,value,0,0xffffffff); -} - -#define CF0_WRITE_PCI_CFG(dev,where,value,bm,mask) \ -do { \ - bridge_t *bridge; \ - int slot = PCI_SLOT(dev->devfn); \ - int fn = PCI_FUNC(dev->devfn); \ - volatile u32 *addr; \ - u32 cf, __bit; \ - unsigned int bus_id = (unsigned) dev->bus->number; \ - \ - bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], \ - bus_to_wid[bus_id]); \ - \ - if (dev->vendor == PCI_VENDOR_ID_SGI \ - && dev->device == PCI_DEVICE_ID_SGI_IOC3 \ - && ((where >= 0x14 && where < 0x40) || (where >= 0x48))) \ - return PCIBIOS_SUCCESSFUL; \ - \ - __bit = (((where) & (bm)) << 3); \ - addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; \ - if (get_dbe(cf, addr)) \ - return PCIBIOS_DEVICE_NOT_FOUND; \ - cf &= (~mask); \ - cf |= (value); \ - put_dbe(cf, addr); \ - return PCIBIOS_SUCCESSFUL; \ -} while (0) - -static int -pci_conf0_write_config_byte(struct pci_dev *dev, int where, u8 value) -{ - CF0_WRITE_PCI_CFG(dev,where,value,3,0xff); -} - -static int -pci_conf0_write_config_word(struct pci_dev *dev, int where, u16 value) -{ - CF0_WRITE_PCI_CFG(dev,where,value,2,0xffff); -} - -static int -pci_conf0_write_config_dword(struct pci_dev *dev, int where, u32 value) -{ - CF0_WRITE_PCI_CFG(dev,where,value,0,0xffffffff); -} - - -static struct pci_ops bridge_pci_ops = { - pci_conf0_read_config_byte, - pci_conf0_read_config_word, - pci_conf0_read_config_dword, - pci_conf0_write_config_byte, - pci_conf0_write_config_word, - pci_conf0_write_config_dword -}; - -void __init pcibios_init(void) -{ - struct pci_ops *ops = &bridge_pci_ops; - int i; - - ioport_resource.end = ~0UL; - - for (i=0; ibus->self) { /* Move up the chain of bridges. */ - pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); - dev = dev->bus->self; - } - *pinp = pin; - - return PCI_SLOT(dev->devfn); -} - -/* - * All observed requests have pin == 1. We could have a global here, that - * gets incremented and returned every time - unfortunately, pci_map_irq - * may be called on the same device over and over, and need to return the - * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7]. - * - * A given PCI device, in general, should be able to intr any of the cpus - * on any one of the hubs connected to its xbow. - */ -static int __init -pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - if ((dev->bus->number >= MAX_PCI_BUSSES) - || (pin != 1) - || (slot >= MAX_DEVICES_PER_PCIBUS)) - panic("Increase supported PCI busses %d,%d,%d\n", - dev->bus->number, slot, pin); - - /* - * Already assigned? Then return previously assigned value ... - */ - if (irqstore[dev->bus->number][slot]) - return irqstore[dev->bus->number][slot]; - - irq_to_bus[lastirq] = dev->bus->number; - irq_to_slot[lastirq] = slot; - irqstore[dev->bus->number][slot] = lastirq; - lastirq++; - return lastirq - 1; -} - -void __init -pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - -#warning pcibios_update_resource() is now a generic implementation - please check - -void __init -pcibios_fixup_bus(struct pci_bus *b) -{ - pci_fixup_irqs(pci_swizzle, pci_map_irq); -} - -int __init -pcibios_enable_device(struct pci_dev *dev) -{ - /* Not needed, since we enable all devices at startup. */ - return 0; -} - -void __init -pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) -{ -} - -unsigned __init int pcibios_assign_all_busses(void) -{ - return 0; -} - -char * __init -pcibios_setup(char *str) -{ - /* Nothing to do for now. */ - - return str; -} - -/* - * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses - * to find the slot number in sense of the bridge device register. - * XXX This also means multiple devices might rely on conflicting bridge - * settings. - */ - -static void __init -pci_disable_swapping(struct pci_dev *dev) -{ - unsigned int bus_id = (unsigned) dev->bus->number; - bridge_t *bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], - bus_to_wid[bus_id]); - int slot = PCI_SLOT(dev->devfn); - - /* Turn off byte swapping */ - bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR; - bridge->b_widget.w_tflush; /* Flush */ -} - -static void __init -pci_enable_swapping(struct pci_dev *dev) -{ - unsigned int bus_id = (unsigned) dev->bus->number; - bridge_t *bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], - bus_to_wid[bus_id]); - int slot = PCI_SLOT(dev->devfn); - - /* Turn on byte swapping */ - bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR; - bridge->b_widget.w_tflush; /* Flush */ -} - -static void __init -pci_fixup_ioc3(struct pci_dev *d) -{ - unsigned long bus_id = (unsigned) d->bus->number; - - printk("PCI: Fixing base addresses for IOC3 device %s\n", d->slot_name); - - d->resource[0].start |= NODE_OFFSET(bus_to_nid[bus_id]); - d->resource[0].end |= NODE_OFFSET(bus_to_nid[bus_id]); - - pci_disable_swapping(d); -} - -static void __init -pci_fixup_isp1020(struct pci_dev *d) -{ - unsigned short command; - - d->resource[0].start |= ((unsigned long)(bus_to_nid[d->bus->number])<<32); - printk("PCI: Fixing isp1020 in [bus:slot.fn] %s\n", d->slot_name); - - /* - * Configure device to allow bus mastering, i/o and memory mapping. - * Older qlogicisp driver expects to have the IO space enable - * bit set. Things stop working if we program the controllers as not - * having PCI_COMMAND_MEMORY, so we have to fudge the mem_flags. - */ - - pci_set_master(d); - pci_read_config_word(d, PCI_COMMAND, &command); - command |= PCI_COMMAND_MEMORY; - command |= PCI_COMMAND_IO; - pci_write_config_word(d, PCI_COMMAND, command); - d->resource[1].flags |= 1; - - pci_enable_swapping(d); -} - -static void __init -pci_fixup_isp2x00(struct pci_dev *d) -{ - unsigned int bus_id = (unsigned) d->bus->number; - bridge_t *bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], - bus_to_wid[bus_id]); - bridgereg_t devreg; - int i; - int slot = PCI_SLOT(d->devfn); - unsigned int start; - unsigned short command; - - printk("PCI: Fixing isp2x00 in [bus:slot.fn] %s\n", d->slot_name); - - /* set the resource struct for this device */ - start = (u32) (u64)bridge; /* yes, we want to lose the upper 32 bits here */ - start |= BRIDGE_DEVIO(slot); - - d->resource[0].start = start; - d->resource[0].end = d->resource[0].start + 0xff; - d->resource[0].flags = IORESOURCE_IO; - - d->resource[1].start = start; - d->resource[1].end = d->resource[0].start + 0xfff; - d->resource[1].flags = IORESOURCE_MEM; - - /* - * set the bridge device(x) reg for this device - */ - devreg = bridge->b_device[slot].reg; - /* point device(x) to it appropriate small window */ - devreg &= ~BRIDGE_DEV_OFF_MASK; - devreg |= (start >> 20) & BRIDGE_DEV_OFF_MASK; - bridge->b_device[slot].reg = devreg; - - pci_enable_swapping(d); - - /* set card's base addr reg */ - //pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_0, 0x500001); - //pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_1, 0x8b00000); - //pci_conf0_write_config_dword(d, PCI_ROM_ADDRESS, 0x8b20000); - - /* I got these from booting irix on system...*/ - pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_0, 0x200001); - //pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_1, 0xf800000); - pci_conf0_write_config_dword(d, PCI_ROM_ADDRESS, 0x10200000); - - pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_1, start); - //pci_conf0_write_config_dword(d, PCI_ROM_ADDRESS, (start | 0x20000)); - - /* set cache line size */ - pci_conf0_write_config_dword(d, PCI_CACHE_LINE_SIZE, 0xf080); - - /* set pci bus timeout */ - bridge->b_bus_timeout |= BRIDGE_BUS_PCI_RETRY_HLD(0x3); - bridge->b_wid_tflush; - printk("PCI: bridge bus timeout= 0x%x \n", bridge->b_bus_timeout); - - /* set host error field */ - bridge->b_int_host_err = 0x44; - bridge->b_wid_tflush; - - bridge->b_wid_tflush; /* wait until Bridge PIO complete */ - for (i=0; i<8; i++) - printk("PCI: device(%d)= 0x%x\n",i,bridge->b_device[i].reg); - - /* configure device to allow bus mastering, i/o and memory mapping */ - pci_set_master(d); - pci_read_config_word(d, PCI_COMMAND, &command); - command |= PCI_COMMAND_MEMORY; - command |= PCI_COMMAND_IO; - pci_write_config_word(d, PCI_COMMAND, command); - /*d->resource[1].flags |= 1;*/ -} - -struct pci_fixup pcibios_fixups[] = { - { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, - pci_fixup_ioc3 }, - { PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP1020, - pci_fixup_isp1020 }, - { PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100, - pci_fixup_isp2x00 }, - { PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200, - pci_fixup_isp2x00 }, - { 0 } -}; --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-pci-dma.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,164 +0,0 @@ -/* - * Dynamic DMA mapping support. - * - * On the Origin there is dynamic DMA address translation for all PCI DMA. - * However we don't use this facility yet but rely on the 2gb direct - * mapped DMA window for PCI64. So consistent alloc/free are merely page - * allocation/freeing. The rest of the dynamic DMA mapping interface is - * implemented in . So this code will fail with more than - * 2gb of memory. - */ -#include -#include -#include -#include -#include - -/* Pure 2^n version of get_order */ -extern __inline__ int __get_order(unsigned long size) -{ - int order; - - size = (size-1) >> (PAGE_SHIFT-1); - order = -1; - do { - size >>= 1; - order++; - } while (size); - return order; -} - -void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, - dma_addr_t *dma_handle) -{ - void *ret; - int gfp = GFP_ATOMIC; - int order = __get_order(size); - - if (hwdev == NULL || hwdev->dma_mask != 0xffffffff) - gfp |= GFP_DMA; - ret = (void *)__get_free_pages(gfp, order); - - if (ret != NULL) { - memset(ret, 0, size); - *dma_handle = (bus_to_baddr[hwdev->bus->number] | __pa(ret)); - } - - return ret; -} - -void pci_free_consistent(struct pci_dev *hwdev, size_t size, - void *vaddr, dma_addr_t dma_handle) -{ - free_pages((unsigned long)vaddr, __get_order(size)); -} - -/* - * Map a single buffer of the indicated size for DMA in streaming mode. - * The 32-bit bus address to use is returned. - * - * Once the device is given the dma address, the device owns this memory - * until either pci_unmap_single or pci_dma_sync_single is performed. - */ -dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, - int direction) -{ - if (direction == PCI_DMA_NONE) - BUG(); - - return (bus_to_baddr[hwdev->bus->number] | __pa(ptr)); -} - -/* - * Unmap a single streaming mode DMA translation. The dma_addr and size - * must match what was provided for in a previous pci_map_single call. All - * other usages are undefined. - * - * After this call, reads by the cpu to the buffer are guaranteed to see - * whatever the device wrote there. - */ -void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, - size_t size, int direction) -{ - if (direction == PCI_DMA_NONE) - BUG(); - - /* Nothing to do */ -} - -/* - * Map a set of buffers described by scatterlist in streaming - * mode for DMA. This is the scather-gather version of the - * above pci_map_single interface. Here the scatter gather list - * elements are each tagged with the appropriate dma address - * and length. They are obtained via sg_dma_{address,length}(SG). - * - * NOTE: An implementation may be able to use a smaller number of - * DMA address/length pairs than there are SG table elements. - * (for example via virtual mapping capabilities) - * The routine returns the number of addr/length pairs actually - * used, at most nents. - * - * Device ownership issues as mentioned above for pci_map_single are - * the same here. - */ -int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, - int direction) -{ - int i; - - if (direction == PCI_DMA_NONE) - BUG(); - - /* Make sure that gcc doesn't leave the empty loop body. */ - for (i = 0; i < nents; i++, sg++) { - sg->address = (char *)(bus_to_baddr[hwdev->bus->number] | __pa(sg->address)); - } - - return nents; -} - -/* - * Unmap a set of streaming mode DMA translations. - * Again, cpu read rules concerning calls here are the same as for - * pci_unmap_single() above. - */ -void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, - int direction) -{ - if (direction == PCI_DMA_NONE) - BUG(); - - /* Nothing to do */ -} - -/* - * Make physical memory consistent for a single - * streaming mode DMA translation after a transfer. - * - * If you perform a pci_map_single() but wish to interrogate the - * buffer using the cpu, yet do not wish to teardown the PCI dma - * mapping, you must call this function before doing so. At the - * next point you give the PCI dma address back to the card, the - * device again owns the buffer. - */ -void pci_dma_sync_single(struct pci_dev *hwdev, dma_addr_t dma_handle, - size_t size, int direction) -{ - if (direction == PCI_DMA_NONE) - BUG(); -} - -/* - * Make physical memory consistent for a set of streaming - * mode DMA translations after a transfer. - * - * The same as pci_dma_sync_single but for a scatter-gather list, - * same rules and usage. - */ -void pci_dma_sync_sg(struct pci_dev *hwdev, struct scatterlist *sg, - int nelems, int direction) -{ - if (direction == PCI_DMA_NONE) - BUG(); -} --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-reset.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,76 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Reset an IP27. - * - * Copyright (C) 1997, 1998, 1999, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void machine_restart(char *command) __attribute__((noreturn)); -void machine_halt(void) __attribute__((noreturn)); -void machine_power_off(void) __attribute__((noreturn)); - -#define noreturn while(1); /* Silence gcc. */ - -/* XXX How to pass the reboot command to the firmware??? */ -void machine_restart(char *command) -{ -#if 0 - int i; -#endif - - printk("Reboot started from CPU %d\n", smp_processor_id()); -#ifdef CONFIG_SMP - smp_send_stop(); -#endif -#if 0 - for (i = 0; i < numnodes; i++) - REMOTE_HUB_S(COMPACT_TO_NASID_NODEID(i), PROMOP_REG, - PROMOP_REBOOT); -#else - LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET); -#endif - noreturn; -} - -void machine_halt(void) -{ - int i; - -#ifdef CONFIG_SMP - smp_send_stop(); -#endif - for (i = 0; i < numnodes; i++) - REMOTE_HUB_S(COMPACT_TO_NASID_NODEID(i), PROMOP_REG, - PROMOP_RESTART); - LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET); - noreturn; -} - -void machine_power_off(void) -{ - /* To do ... */ - noreturn; -} - -void ip27_reboot_setup(void) -{ - /* Nothing to do on IP27. */ -} --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-rtc.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,319 +0,0 @@ -/* - * Driver for the SGS-Thomson M48T35 Timekeeper RAM chip - * - * Real Time Clock interface for Linux - * - * TODO: Implement periodic interrupts. - * - * Copyright (C) 2000 Silicon Graphics, Inc. - * Written by Ulf Carlsson (ulfc@engr.sgi.com) - * - * Based on code written by Paul Gortmaker. - * - * This driver allows use of the real time clock (built into - * nearly all computers) from user space. It exports the /dev/rtc - * interface supporting various ioctl() and also the /proc/rtc - * pseudo-file for status information. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#define RTC_VERSION "1.09b" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -static int rtc_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg); - -static int rtc_read_proc(char *page, char **start, off_t off, - int count, int *eof, void *data); - -static void get_rtc_time(struct rtc_time *rtc_tm); - -static atomic_t rtc_ready = ATOMIC_INIT(1); -static unsigned long rtc_freq; /* Current periodic IRQ rate */ -static struct m48t35_rtc *rtc; - -/* - * If this driver ever becomes modularised, it will be really nice - * to make the epoch retain its value across module reload... - */ - -static unsigned long epoch = 1970; /* year corresponding to 0x00 */ - -static const unsigned char days_in_mo[] = -{0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; - -static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) -{ - - struct rtc_time wtime; - - switch (cmd) { - case RTC_RD_TIME: /* Read the time/date from RTC */ - { - get_rtc_time(&wtime); - break; - } - case RTC_SET_TIME: /* Set the RTC */ - { - struct rtc_time rtc_tm; - unsigned char mon, day, hrs, min, sec, leap_yr; - unsigned int yrs; - unsigned long flags; - - if (!capable(CAP_SYS_TIME)) - return -EACCES; - - if (copy_from_user(&rtc_tm, (struct rtc_time*)arg, - sizeof(struct rtc_time))) - return -EFAULT; - - yrs = rtc_tm.tm_year + 1900; - mon = rtc_tm.tm_mon + 1; /* tm_mon starts at zero */ - day = rtc_tm.tm_mday; - hrs = rtc_tm.tm_hour; - min = rtc_tm.tm_min; - sec = rtc_tm.tm_sec; - - if (yrs < 1970) - return -EINVAL; - - leap_yr = ((!(yrs % 4) && (yrs % 100)) || !(yrs % 400)); - - if ((mon > 12) || (day == 0)) - return -EINVAL; - - if (day > (days_in_mo[mon] + ((mon == 2) && leap_yr))) - return -EINVAL; - - if ((hrs >= 24) || (min >= 60) || (sec >= 60)) - return -EINVAL; - - if ((yrs -= epoch) > 255) /* They are unsigned */ - return -EINVAL; - - save_flags(flags); - cli(); - if (yrs > 169) { - restore_flags(flags); - return -EINVAL; - } - if (yrs >= 100) - yrs -= 100; - - BIN_TO_BCD(sec); - BIN_TO_BCD(min); - BIN_TO_BCD(hrs); - BIN_TO_BCD(day); - BIN_TO_BCD(mon); - BIN_TO_BCD(yrs); - - rtc->control &= ~M48T35_RTC_SET; - rtc->year = yrs; - rtc->month = mon; - rtc->date = day; - rtc->hour = hrs; - rtc->min = min; - rtc->sec = sec; - rtc->control &= ~M48T35_RTC_SET; - - restore_flags(flags); - return 0; - } - default: - return -EINVAL; - } - return copy_to_user((void *)arg, &wtime, sizeof wtime) ? -EFAULT : 0; -} - -/* - * We enforce only one user at a time here with the open/close. - * Also clear the previous interrupt data on an open, and clean - * up things on a close. - */ - -static int rtc_open(struct inode *inode, struct file *file) -{ - if( atomic_dec_and_test( &rtc_ready ) ) - { - atomic_inc( &rtc_ready ); - return -EBUSY; - } - return 0; -} - -static int rtc_release(struct inode *inode, struct file *file) -{ - atomic_inc( &rtc_ready ); - return 0; -} - -/* - * The various file operations we support. - */ - -static struct file_operations rtc_fops = { - .owner = THIS_MODULE, - .ioctl = rtc_ioctl, - .open = rtc_open, - .release = rtc_release, -}; - -static struct miscdevice rtc_dev= -{ - RTC_MINOR, - "rtc", - &rtc_fops -}; - -static int __init rtc_init(void) -{ - unsigned long flags; - nasid_t nid; - - nid = get_nasid(); - rtc = (struct m48t35_rtc *) - KL_CONFIG_CH_CONS_INFO(nid)->memory_base + IOC3_BYTEBUS_DEV0; - - printk(KERN_INFO "Real Time Clock Driver v%s\n", RTC_VERSION); - if (misc_register(&rtc_dev)) { - printk(KERN_ERR "rtc: cannot register misc device.\n"); - return -ENODEV; - } - if (!create_proc_read_entry ("rtc", 0, NULL, rtc_read_proc, NULL)) { - printk(KERN_ERR "rtc: cannot create /proc/rtc.\n"); - misc_deregister(&rtc_dev); - return -ENOENT; - } - - save_flags(flags); - cli(); - restore_flags(flags); - rtc_freq = 1024; - return 0; -} - -static void __exit rtc_exit (void) -{ - /* interrupts and timer disabled at this point by rtc_release */ - - remove_proc_entry ("rtc", NULL); - misc_deregister(&rtc_dev); -} - -module_init(rtc_init); -module_exit(rtc_exit); - -/* - * Info exported via "/proc/rtc". - */ - -static int rtc_get_status(char *buf) -{ - char *p; - struct rtc_time tm; - - /* - * Just emulate the standard /proc/rtc - */ - - p = buf; - - get_rtc_time(&tm); - - /* - * There is no way to tell if the luser has the RTC set for local - * time or for Universal Standard Time (GMT). Probably local though. - */ - p += sprintf(p, - "rtc_time\t: %02d:%02d:%02d\n" - "rtc_date\t: %04d-%02d-%02d\n" - "rtc_epoch\t: %04lu\n" - "24hr\t\t: yes\n", - tm.tm_hour, tm.tm_min, tm.tm_sec, - tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday, epoch); - - return p - buf; -} - -static int rtc_read_proc(char *page, char **start, off_t off, - int count, int *eof, void *data) -{ - int len = rtc_get_status(page); - if (len <= off+count) *eof = 1; - *start = page + off; - len -= off; - if (len>count) len = count; - if (len<0) len = 0; - return len; -} - -static void get_rtc_time(struct rtc_time *rtc_tm) -{ - - unsigned long flags; - - /* - * Do we need to wait for the last update to finish? - */ - - /* - * Only the values that we read from the RTC are set. We leave - * tm_wday, tm_yday and tm_isdst untouched. Even though the - * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated - * by the RTC when initially set to a non-zero value. - */ - save_flags(flags); - cli(); - rtc->control |= M48T35_RTC_READ; - rtc_tm->tm_sec = rtc->sec; - rtc_tm->tm_min = rtc->min; - rtc_tm->tm_hour = rtc->hour; - rtc_tm->tm_mday = rtc->date; - rtc_tm->tm_mon = rtc->month; - rtc_tm->tm_year = rtc->year; - rtc->control &= ~M48T35_RTC_READ; - restore_flags(flags); - - BCD_TO_BIN(rtc_tm->tm_sec); - BCD_TO_BIN(rtc_tm->tm_min); - BCD_TO_BIN(rtc_tm->tm_hour); - BCD_TO_BIN(rtc_tm->tm_mday); - BCD_TO_BIN(rtc_tm->tm_mon); - BCD_TO_BIN(rtc_tm->tm_year); - - /* - * Account for differences between how the RTC uses the values - * and how they are defined in a struct rtc_time; - */ - if ((rtc_tm->tm_year += (epoch - 1900)) <= 69) - rtc_tm->tm_year += 100; - - rtc_tm->tm_mon--; -} --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-setup.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,310 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * SGI IP27 specific setup. - * - * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999, 2000 Silcon Graphics, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Check against user dumbness. */ -#ifdef CONFIG_VT -#error CONFIG_VT not allowed for IP27. -#endif - -#undef DEBUG_SETUP -#ifdef DEBUG_SETUP -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -unsigned long mips_io_port_base = IO_BASE; - -/* - * get_nasid() returns the physical node id number of the caller. - */ -nasid_t -get_nasid(void) -{ - return (nasid_t)((LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_NODEID_MASK) - >> NSRI_NODEID_SHFT); -} - -/* Extracted from the IOC3 meta driver. FIXME. */ -static inline void ioc3_sio_init(void) -{ - struct ioc3 *ioc3; - nasid_t nid; - long loops; - - nid = get_nasid(); - ioc3 = (struct ioc3 *) KL_CONFIG_CH_CONS_INFO(nid)->memory_base; - - ioc3->sscr_a = 0; /* PIO mode for uarta. */ - ioc3->sscr_b = 0; /* PIO mode for uartb. */ - ioc3->sio_iec = ~0; - ioc3->sio_ies = (SIO_IR_SA_INT | SIO_IR_SB_INT); - - loops=1000000; while(loops--); - ioc3->sregs.uarta.iu_fcr = 0; - ioc3->sregs.uartb.iu_fcr = 0; - loops=1000000; while(loops--); -} - -static inline void ioc3_eth_init(void) -{ - struct ioc3 *ioc3; - nasid_t nid; - - nid = get_nasid(); - ioc3 = (struct ioc3 *) KL_CONFIG_CH_CONS_INFO(nid)->memory_base; - - ioc3->eier = 0; -} - -/* Try to catch kernel missconfigurations and give user an indication what - option to select. */ -static void __init verify_mode(void) -{ - int n_mode; - - n_mode = LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_MORENODES_MASK; - printk("Machine is in %c mode.\n", n_mode ? 'N' : 'M'); -#ifdef CONFIG_SGI_SN0_N_MODE - if (!n_mode) - panic("Kernel compiled for M mode."); -#else - if (n_mode) - panic("Kernel compiled for N mode."); -#endif -} - -#define XBOW_WIDGET_PART_NUM 0x0 -#define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */ -#define BASE_XBOW_PORT 8 /* Lowest external port */ - -unsigned int bus_to_cpu[256]; -unsigned long bus_to_baddr[256]; - -void __init pcibr_setup(cnodeid_t nid) -{ - int i, start, num; - unsigned long masterwid; - bridge_t *bridge; - volatile u64 hubreg; - nasid_t nasid, masternasid; - xwidget_part_num_t partnum; - widgetreg_t widget_id; - static spinlock_t pcibr_setup_lock = SPIN_LOCK_UNLOCKED; - - /* - * If the master is doing this for headless node, nothing to do. - * This is because currently we require at least one of the hubs - * (master hub) connected to the xbow to have at least one enabled - * cpu to receive intrs. Else we need an array bus_to_intrnasid[] - * that bridge_startup() needs to use to target intrs. All dma is - * routed thru the widget of the master hub. The master hub wid - * is selectable by WIDGET_A below. - */ - if (nid != get_compact_nodeid()) - return; - /* - * find what's on our local node - */ - spin_lock(&pcibr_setup_lock); - start = num_bridges; /* Remember where we start from */ - nasid = COMPACT_TO_NASID_NODEID(nid); - hubreg = REMOTE_HUB_L(nasid, IIO_LLP_CSR); - if (hubreg & IIO_LLP_CSR_IS_UP) { - /* link is up */ - widget_id = *(volatile widgetreg_t *) - (RAW_NODE_SWIN_BASE(nasid, 0x0) + WIDGET_ID); - partnum = XWIDGET_PART_NUM(widget_id); - printk("Cpu %d, Nasid 0x%x, pcibr_setup(): found partnum= 0x%x", - smp_processor_id(), nasid, partnum); - if (partnum == BRIDGE_WIDGET_PART_NUM) { - /* - * found direct connected bridge so must be Origin200 - */ - printk("...is bridge\n"); - num_bridges = 1; - bus_to_wid[0] = 0x8; - bus_to_nid[0] = 0; - masterwid = 0xa; - bus_to_baddr[0] = 0xa100000000000000UL; - } else if (partnum == XBOW_WIDGET_PART_NUM) { - lboard_t *brd; - klxbow_t *xbow_p; - /* - * found xbow, so may have multiple bridges - * need to probe xbow - */ - printk("...is xbow\n"); - - if ((brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), - KLTYPE_MIDPLANE8)) == NULL) - printk("argh\n"); - else - printk("brd = 0x%lx\n", (unsigned long) brd); - if ((xbow_p = (klxbow_t *) - find_component(brd, NULL, KLSTRUCT_XBOW)) == NULL) - printk("argh\n"); - else { - /* - * Okay, here's a xbow. Lets arbitrate and find - * out if we should initialize it. Set enabled - * hub connected at highest or lowest widget as - * master. - */ -#ifdef WIDGET_A - i = HUB_WIDGET_ID_MAX + 1; - do { - i--; - } while ((!XBOW_PORT_TYPE_HUB(xbow_p, i)) || - (!XBOW_PORT_IS_ENABLED(xbow_p, i))); -#else - i = HUB_WIDGET_ID_MIN - 1; - do { - i++; - } while ((!XBOW_PORT_TYPE_HUB(xbow_p, i)) || - (!XBOW_PORT_IS_ENABLED(xbow_p, i))); -#endif - masterwid = i; - masternasid = XBOW_PORT_NASID(xbow_p, i); - if (nasid == masternasid) - for (i=HUB_WIDGET_ID_MIN; i<=HUB_WIDGET_ID_MAX; i++) { - if (!XBOW_PORT_IS_ENABLED(xbow_p, i)) - continue; - if (XBOW_PORT_TYPE_IO(xbow_p, i)) { - widget_id = *(volatile widgetreg_t *) - (RAW_NODE_SWIN_BASE(nasid, i) + WIDGET_ID); - partnum = XWIDGET_PART_NUM(widget_id); - if (partnum == BRIDGE_WIDGET_PART_NUM) { - printk("widget 0x%x is a bridge\n", i); - bus_to_wid[num_bridges] = i; - bus_to_nid[num_bridges] = nasid; - bus_to_baddr[num_bridges] = ((masterwid << 60) | (1UL << 56)); /* Barrier set */ - num_bridges++; - } - } - } - } - } else if (partnum == XXBOW_WIDGET_PART_NUM) { - /* - * found xbridge, assume ibrick for now - */ - printk("...is xbridge\n"); - bus_to_wid[0] = 0xb; - bus_to_wid[1] = 0xe; - bus_to_wid[2] = 0xf; - - bus_to_nid[0] = 0; - bus_to_nid[1] = 0; - bus_to_nid[2] = 0; - - bus_to_baddr[0] = 0xa100000000000000UL; - bus_to_baddr[1] = 0xa100000000000000UL; - bus_to_baddr[2] = 0xa100000000000000UL; - masterwid = 0xa; - num_bridges = 3; - } - } - num = num_bridges - start; - spin_unlock(&pcibr_setup_lock); - /* - * set bridge registers - */ - for (i = start; i < (start + num); i++) { - - DBG("pcibr_setup: bus= %d bus_to_wid[%2d]= %d bus_to_nid[%2d]= %d\n", - i, i, bus_to_wid[i], i, bus_to_nid[i]); - - bus_to_cpu[i] = smp_processor_id(); - /* - * point to this bridge - */ - bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[i],bus_to_wid[i]); - /* - * Clear all pending interrupts. - */ - bridge->b_int_rst_stat = (BRIDGE_IRR_ALL_CLR); - /* - * Until otherwise set up, assume all interrupts are from slot 0 - */ - bridge->b_int_device = (u32) 0x0; - /* - * swap pio's to pci mem and io space (big windows) - */ - bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP; - bridge->b_wid_control |= BRIDGE_CTRL_MEM_SWAP; - - /* - * Hmm... IRIX sets additional bits in the address which - * are documented as reserved in the bridge docs. - */ - bridge->b_int_mode = 0x0; /* Don't clear ints */ - bridge->b_wid_int_upper = 0x8000 | (masterwid << 16); - bridge->b_wid_int_lower = 0x01800090; /* PI_INT_PEND_MOD off*/ - bridge->b_dir_map = (masterwid << 20); /* DMA */ - bridge->b_int_enable = 0; - - bridge->b_wid_tflush; /* wait until Bridge PIO complete */ - } -} - -extern void ip27_setup_console(void); - -void __init ip27_setup(void) -{ - nasid_t nid; - hubreg_t p, e; - - ip27_setup_console(); - - num_bridges = 0; - /* - * hub_rtc init and cpu clock intr enabled for later calibrate_delay. - */ - DBG("ip27_setup(): Entered.\n"); - nid = get_nasid(); - printk("IP27: Running on node %d.\n", nid); - - p = LOCAL_HUB_L(PI_CPU_PRESENT_A) & 1; - e = LOCAL_HUB_L(PI_CPU_ENABLE_A) & 1; - printk("Node %d has %s primary CPU%s.\n", nid, - p ? "a" : "no", - e ? ", CPU is running" : ""); - - p = LOCAL_HUB_L(PI_CPU_PRESENT_B) & 1; - e = LOCAL_HUB_L(PI_CPU_ENABLE_B) & 1; - printk("Node %d has %s secondary CPU%s.\n", nid, - p ? "a" : "no", - e ? ", CPU is running" : ""); - - verify_mode(); - ioc3_sio_init(); - ioc3_eth_init(); - per_cpu_init(); -} --- linux-2.5.73/arch/mips64/sgi-ip27/ip27-timer.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,294 +0,0 @@ -/* - * Copytight (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) - * Copytight (C) 1999, 2000 Silicon Graphics, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * This is a hack; we really need to figure these values out dynamically - * - * Since 800 ns works very well with various HUB frequencies, such as - * 360, 380, 390 and 400 MHZ, we use 800 ns rtc cycle time. - * - * Ralf: which clock rate is used to feed the counter? - */ -#define NSEC_PER_CYCLE 800 -#define NSEC_PER_SEC 1000000000 -#define CYCLES_PER_SEC (NSEC_PER_SEC/NSEC_PER_CYCLE) -#define CYCLES_PER_JIFFY (CYCLES_PER_SEC/HZ) - -static unsigned long ct_cur[NR_CPUS]; /* What counter should be at next timer irq */ -static long last_rtc_update; /* Last time the rtc clock got updated */ - -extern volatile unsigned long wall_jiffies; - - -static int set_rtc_mmss(unsigned long nowtime) -{ - int retval = 0; - int real_seconds, real_minutes, cmos_minutes; - struct m48t35_rtc *rtc; - nasid_t nid; - - nid = get_nasid(); - rtc = (struct m48t35_rtc *)(KL_CONFIG_CH_CONS_INFO(nid)->memory_base + - IOC3_BYTEBUS_DEV0); - - rtc->control |= M48T35_RTC_READ; - cmos_minutes = rtc->min; - BCD_TO_BIN(cmos_minutes); - rtc->control &= ~M48T35_RTC_READ; - - /* - * Since we're only adjusting minutes and seconds, don't interfere with - * hour overflow. This avoids messing with unknown time zones but - * requires your RTC not to be off by more than 15 minutes - */ - real_seconds = nowtime % 60; - real_minutes = nowtime / 60; - if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) - real_minutes += 30; /* correct for half hour time zone */ - real_minutes %= 60; - - if (abs(real_minutes - cmos_minutes) < 30) { - BIN_TO_BCD(real_seconds); - BIN_TO_BCD(real_minutes); - rtc->control |= M48T35_RTC_SET; - rtc->sec = real_seconds; - rtc->min = real_minutes; - rtc->control &= ~M48T35_RTC_SET; - } else { - printk(KERN_WARNING - "set_rtc_mmss: can't update from %d to %d\n", - cmos_minutes, real_minutes); - retval = -1; - } - - return retval; -} - -void rt_timer_interrupt(struct pt_regs *regs) -{ - int cpu = smp_processor_id(); - int cpuA = ((cputoslice(cpu)) == 0); - int irq = 7; /* XXX Assign number */ - - write_seqlock(&xtime_lock); - -again: - LOCAL_HUB_S(cpuA ? PI_RT_PEND_A : PI_RT_PEND_B, 0); /* Ack */ - ct_cur[cpu] += CYCLES_PER_JIFFY; - LOCAL_HUB_S(cpuA ? PI_RT_COMPARE_A : PI_RT_COMPARE_B, ct_cur[cpu]); - - if (LOCAL_HUB_L(PI_RT_COUNT) >= ct_cur[cpu]) - goto again; - - kstat_cpu(cpu).irqs[irq]++; /* kstat only for bootcpu? */ - - if (cpu == 0) - do_timer(regs); - -#ifdef CONFIG_SMP - { - int user = user_mode(regs); - - /* - * update_process_times() expects us to have done irq_enter(). - * Besides, if we don't timer interrupts ignore the global - * interrupt lock, which is the WrongThing (tm) to do. - * Picked from i386 code. - */ - irq_enter(cpu, 0); - update_process_times(user); - irq_exit(cpu, 0); - } -#endif /* CONFIG_SMP */ - - /* - * If we have an externally synchronized Linux clock, then update - * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be - * called as close as possible to when a second starts. - */ - if ((time_status & STA_UNSYNC) == 0 && - xtime.tv_sec > last_rtc_update + 660) { - if (xtime.tv_usec >= 1000000 - ((unsigned) tick) / 2) { - if (set_rtc_mmss(xtime.tv_sec + 1) == 0) - last_rtc_update = xtime.tv_sec; - else - last_rtc_update = xtime.tv_sec - 600; - } else if (xtime.tv_usec <= ((unsigned) tick) / 2) { - if (set_rtc_mmss(xtime.tv_sec) == 0) - last_rtc_update = xtime.tv_sec; - else - last_rtc_update = xtime.tv_sec - 600; - } - } - - write_sequnlock(&xtime_lock); - - if (softirq_pending(cpu)) - do_softirq(); -} - -unsigned long inline do_gettimeoffset(void) -{ - unsigned long ct_cur1; - ct_cur1 = REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT) + CYCLES_PER_JIFFY; - return (ct_cur1 - ct_cur[0]) * NSEC_PER_CYCLE / 1000; -} - -void do_gettimeofday(struct timeval *tv) -{ - unsigned long flags; - unsigned long usec, sec; - unsigned long seq; - - do { - seq = read_seqbegin_irqsave(&xtime_lock, flags); - - usec = do_gettimeoffset(); - { - unsigned long lost = jiffies - wall_jiffies; - if (lost) - usec += lost * (1000000 / HZ); - } - sec = xtime.tv_sec; - usec += xtime.tv_usec; - } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); - - while (usec >= 1000000) { - usec -= 1000000; - sec++; - } - - tv->tv_sec = sec; - tv->tv_usec = usec; -} - -void do_settimeofday(struct timeval *tv) -{ - write_seqlock_irq(&xtime_lock); - tv->tv_usec -= do_gettimeoffset(); - tv->tv_usec -= (jiffies - wall_jiffies) * (1000000 / HZ); - - while (tv->tv_usec < 0) { - tv->tv_usec += 1000000; - tv->tv_sec--; - } - - xtime = *tv; - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; - write_sequnlock_irq(&xtime_lock); -} - -/* Includes for ioc3_init(). */ -#include -#include -#include -#include -#include - -static __init unsigned long get_m48t35_time(void) -{ - unsigned int year, month, date, hour, min, sec; - struct m48t35_rtc *rtc; - nasid_t nid; - - nid = get_nasid(); - rtc = (struct m48t35_rtc *)(KL_CONFIG_CH_CONS_INFO(nid)->memory_base + - IOC3_BYTEBUS_DEV0); - - rtc->control |= M48T35_RTC_READ; - sec = rtc->sec; - min = rtc->min; - hour = rtc->hour; - date = rtc->date; - month = rtc->month; - year = rtc->year; - rtc->control &= ~M48T35_RTC_READ; - - BCD_TO_BIN(sec); - BCD_TO_BIN(min); - BCD_TO_BIN(hour); - BCD_TO_BIN(date); - BCD_TO_BIN(month); - BCD_TO_BIN(year); - - year += 1970; - - return mktime(year, month, date, hour, min, sec); -} - -void __init time_init(void) -{ - xtime.tv_sec = get_m48t35_time(); - xtime.tv_usec = 0; -} - -void __init cpu_time_init(void) -{ - lboard_t *board; - klcpu_t *cpu; - int cpuid; - - /* Don't use ARCS. ARCS is fragile. Klconfig is simple and sane. */ - board = find_lboard(KL_CONFIG_INFO(get_nasid()), KLTYPE_IP27); - if (!board) - panic("Can't find board info for myself."); - - cpuid = LOCAL_HUB_L(PI_CPU_NUM) ? IP27_CPU0_INDEX : IP27_CPU1_INDEX; - cpu = (klcpu_t *) KLCF_COMP(board, cpuid); - if (!cpu) - panic("No information about myself?"); - - printk("CPU %d clock is %dMHz.\n", smp_processor_id(), cpu->cpu_speed); - - set_cp0_status(SRB_TIMOCLK, SRB_TIMOCLK); -} - -void __init hub_rtc_init(cnodeid_t cnode) -{ - /* - * We only need to initialize the current node. - * If this is not the current node then it is a cpuless - * node and timeouts will not happen there. - */ - if (get_compact_nodeid() == cnode) { - int cpu = smp_processor_id(); - LOCAL_HUB_S(PI_RT_EN_A, 1); - LOCAL_HUB_S(PI_RT_EN_B, 1); - LOCAL_HUB_S(PI_PROF_EN_A, 0); - LOCAL_HUB_S(PI_PROF_EN_B, 0); - ct_cur[cpu] = CYCLES_PER_JIFFY; - LOCAL_HUB_S(PI_RT_COMPARE_A, ct_cur[cpu]); - LOCAL_HUB_S(PI_RT_COUNT, 0); - LOCAL_HUB_S(PI_RT_PEND_A, 0); - LOCAL_HUB_S(PI_RT_COMPARE_B, ct_cur[cpu]); - LOCAL_HUB_S(PI_RT_COUNT, 0); - LOCAL_HUB_S(PI_RT_PEND_B, 0); - } -} --- linux-2.5.73/arch/mips64/sgi-ip27/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,9 +0,0 @@ -# -# Makefile for the IP27 specific kernel interface routines under Linux. -# - -EXTRA_AFLAGS := $(CFLAGS) - -obj-y := ip27-berr.o ip27-console.o ip27-irq.o ip27-init.o ip27-irq-glue.o \ - ip27-klconfig.o ip27-klnuma.o ip27-memory.o ip27-nmi.o ip27-pci.o \ - ip27-pci-dma.o ip27-reset.o ip27-setup.o ip27-timer.o --- linux-2.5.73/arch/mips64/sgi-ip27/TODO 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,23 +0,0 @@ -1. Need to figure out why PCI writes to the IOC3 hang, and if it is okay -not to write to the IOC3 ever. -2. Need to figure out RRB allocation in bridge_startup(). -3. Need to figure out why address swaizzling is needed in inw/outw for -Qlogic scsi controllers. -4. Need to integrate ip27-klconfig.c:find_lboard and -ip27-init.c:find_lbaord_real. DONE -5. Is it okay to set calias space on all nodes as 0, instead of 8k as -in irix? -6. Investigate why things do not work without the setup_test() call -being invoked on all nodes in ip27-memory.c. -7. Too many CLIs in the locore handlers : -For the low level handlers set up by set_except_vector(), -__tlb_refill_debug_tramp, __xtlb_refill_debug_tramp and cacheerror, -investigate whether the code should do CLI, STI or KMODE. -8. Too many do_page_faults invoked - investigate. -9. start_thread must turn off UX64 ... and define tlb_refill_debug. -10. Need a bad pmd table, bad pte table. __bad_pmd_table/__bad_pagetable -does not agree with pgd_bad/pmd_bad. -11. All intrs (ip27_do_irq handlers) are targetted at cpu A on the node. -This might need to change later. Only the timer intr is set up to be -received on both Cpu A and B. (ip27_do_irq()/bridge_startup()) -13. Cache flushing (specially the SMP version) has to be investigated. --- linux-2.5.73/arch/mips64/sgi-ip32/crime.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,50 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2001 Keith M Wesolowski - */ -#include -#include -#include -#include -#include -#include - -void __init crime_init (void) -{ - u64 id = crime_read_64 (CRIME_ID); - u64 rev = id & CRIME_ID_REV; - - id = (id & CRIME_ID_IDBITS) >> 4; - - printk ("CRIME id %1lx rev %ld detected at %016lx\n", id, rev, - (unsigned long) CRIME_BASE); -} - -/* XXX Like on Sun, these give us various useful information to printk. */ -void crime_memerr_intr (unsigned int irq, void *dev_id, struct pt_regs *regs) -{ - u64 memerr = crime_read_64 (CRIME_MEM_ERROR_STAT); - u64 addr = crime_read_64 (CRIME_MEM_ERROR_ADDR); - memerr &= CRIME_MEM_ERROR_STAT_MASK; - - printk ("CRIME memory error at physaddr 0x%08lx status %08lx\n", - addr << 2, memerr); - - crime_write_64 (CRIME_MEM_ERROR_STAT, 0); -} - -void crime_cpuerr_intr (unsigned int irq, void *dev_id, struct pt_regs *regs) -{ - u64 cpuerr = crime_read_64 (CRIME_CPU_ERROR_STAT); - u64 addr = crime_read_64 (CRIME_CPU_ERROR_ADDR); - cpuerr &= CRIME_CPU_ERROR_MASK; - addr <<= 2UL; - - printk ("CRIME CPU interface error detected at %09lx status %08lx\n", - addr, cpuerr); - - crime_write_64 (CRIME_CPU_ERROR_STAT, 0); -} --- linux-2.5.73/arch/mips64/sgi-ip32/ip32-berr.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,97 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1999, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 by Silicon Graphics - */ -#include -#include -#include -#include -#include -#include - -/* XXX I have no idea what this does --kmw */ - -extern asmlinkage void handle_ibe(void); -extern asmlinkage void handle_dbe(void); - -extern const struct exception_table_entry __start___dbe_table[]; -extern const struct exception_table_entry __stop___dbe_table[]; - -static inline unsigned long -search_one_table(const struct exception_table_entry *first, - const struct exception_table_entry *last, - unsigned long value) -{ - while (first <= last) { - const struct exception_table_entry *mid; - long diff; - - mid = (last - first) / 2 + first; - diff = mid->insn - value; - if (diff == 0) - return mid->nextinsn; - else if (diff < 0) - first = mid+1; - else - last = mid-1; - } - return 0; -} - -static inline unsigned long -search_dbe_table(unsigned long addr) -{ - unsigned long ret; - - /* There is only the kernel to search. */ - ret = search_one_table(__start___dbe_table, __stop___dbe_table-1, addr); - if (ret) return ret; - - return 0; -} - -void do_ibe(struct pt_regs *regs) -{ - printk("Got ibe at 0x%lx\n", regs->cp0_epc); - show_regs(regs); - dump_tlb_addr(regs->cp0_epc); - force_sig(SIGBUS, current); - while(1); -} - -void do_dbe(struct pt_regs *regs) -{ - unsigned long fixup; - - fixup = search_dbe_table(regs->cp0_epc); - if (fixup) { - long new_epc; - - new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc); - regs->cp0_epc = new_epc; - return; - } - - printk("Got dbe at 0x%lx\n", regs->cp0_epc); - show_regs(regs); - dump_tlb_all(); - while(1); - force_sig(SIGBUS, current); -} - -void __init -bus_error_init(void) -{ - int dummy; - - set_except_vector(6, handle_ibe); - set_except_vector(7, handle_dbe); - - /* At this time nothing uses the DBE protection mechanism on the - O2, so this here is needed to make the kernel link. */ - get_dbe(dummy, (int *)KSEG0); -} --- linux-2.5.73/arch/mips64/sgi-ip32/ip32-irq.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,556 +0,0 @@ -/* - * Code to handle IP32 IRQs - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Harald Koerfgen - * Copyright (C) 2001 Keith M Wesolowski - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#undef DEBUG_IRQ -#ifdef DEBUG_IRQ -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -/* O2 irq map - * - * IP0 -> software (ignored) - * IP1 -> software (ignored) - * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ??? - * IP3 -> (irq1) X unknown - * IP4 -> (irq2) X unknown - * IP5 -> (irq3) X unknown - * IP6 -> (irq4) X unknown - * IP7 -> (irq5) 0 CPU count/compare timer (system timer) - * - * crime: (C) - * - * CRIME_INT_STAT 31:0: - * - * 0 -> 1 Video in 1 - * 1 -> 2 Video in 2 - * 2 -> 3 Video out - * 3 -> 4 Mace ethernet - * 4 -> S SuperIO sub-interrupt - * 5 -> M Miscellaneous sub-interrupt - * 6 -> A Audio sub-interrupt - * 7 -> 8 PCI bridge errors - * 8 -> 9 PCI SCSI aic7xxx 0 - * 9 -> 10 PCI SCSI aic7xxx 1 - * 10 -> 11 PCI slot 0 - * 11 -> 12 unused (PCI slot 1) - * 12 -> 13 unused (PCI slot 2) - * 13 -> 14 unused (PCI shared 0) - * 14 -> 15 unused (PCI shared 1) - * 15 -> 16 unused (PCI shared 2) - * 16 -> 17 GBE0 (E) - * 17 -> 18 GBE1 (E) - * 18 -> 19 GBE2 (E) - * 19 -> 20 GBE3 (E) - * 20 -> 21 CPU errors - * 21 -> 22 Memory errors - * 22 -> 23 RE empty edge (E) - * 23 -> 24 RE full edge (E) - * 24 -> 25 RE idle edge (E) - * 25 -> 26 RE empty level - * 26 -> 27 RE full level - * 27 -> 28 RE idle level - * 28 -> 29 unused (software 0) (E) - * 29 -> 30 unused (software 1) (E) - * 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E) - * 31 -> 32 VICE - * - * S, M, A: Use the MACE ISA interrupt register - * MACE_ISA_INT_STAT 31:0 - * - * 0-7 -> 33-40 Audio - * 8 -> 41 RTC - * 9 -> 42 Keyboard - * 10 -> X Keyboard polled - * 11 -> 44 Mouse - * 12 -> X Mouse polled - * 13-15 -> 46-48 Count/compare timers - * 16-19 -> 49-52 Parallel (16 E) - * 20-25 -> 53-58 Serial 1 (22 E) - * 26-31 -> 59-64 Serial 2 (28 E) - * - * Note that this means IRQs 5-7, 43, and 45 do not exist. This is a - * different IRQ map than IRIX uses, but that's OK as Linux irq handling - * is quite different anyway. - */ - -/* Some initial interrupts to set up */ -extern void crime_memerr_intr (unsigned int irq, void *dev_id, - struct pt_regs *regs); -extern void crime_cpuerr_intr (unsigned int irq, void *dev_id, - struct pt_regs *regs); - -struct irqaction memerr_irq = { crime_memerr_intr, SA_INTERRUPT, - 0, "CRIME memory error", NULL, - NULL }; -struct irqaction cpuerr_irq = { crime_cpuerr_intr, SA_INTERRUPT, - 0, "CRIME CPU error", NULL, - NULL }; - -unsigned long spurious_count = 0; -extern void ip32_handle_int (void); -extern void do_IRQ (unsigned int irq, struct pt_regs *regs); - -/* For interrupts wired from a single device to the CPU. Only the clock - * uses this it seems, which is IRQ 0 and IP7. - */ - -static void enable_cpu_irq (unsigned int irq) -{ - set_cp0_status (STATUSF_IP7); -} - -static unsigned int startup_cpu_irq (unsigned int irq) { - enable_cpu_irq (irq); - return 0; -} - -static void disable_cpu_irq (unsigned int irq) -{ - clear_cp0_status (STATUSF_IP7); -} - -static void end_cpu_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_cpu_irq (irq); -} - -#define shutdown_cpu_irq disable_cpu_irq -#define mask_and_ack_cpu_irq disable_cpu_irq - -static struct hw_interrupt_type ip32_cpu_interrupt = { - "IP32 CPU", - startup_cpu_irq, - shutdown_cpu_irq, - enable_cpu_irq, - disable_cpu_irq, - mask_and_ack_cpu_irq, - end_cpu_irq, - NULL -}; - -/* - * This is for pure CRIME interrupts - ie not MACE. The advantage? - * We get to split the register in half and do faster lookups. - */ - -static void enable_crime_irq (unsigned int irq) -{ - u64 crime_mask; - unsigned long flags; - - save_and_cli (flags); - crime_mask = crime_read_64 (CRIME_INT_MASK); - crime_mask |= 1 << (irq - 1); - crime_write_64 (CRIME_INT_MASK, crime_mask); - restore_flags (flags); -} - -static unsigned int startup_crime_irq (unsigned int irq) -{ - enable_crime_irq (irq); - return 0; /* This is probably not right; we could have pending irqs */ -} - -static void disable_crime_irq (unsigned int irq) -{ - u64 crime_mask; - unsigned long flags; - - save_and_cli (flags); - crime_mask = crime_read_64 (CRIME_INT_MASK); - crime_mask &= ~(1 << (irq - 1)); - crime_write_64 (CRIME_INT_MASK, crime_mask); - restore_flags (flags); -} - -static void mask_and_ack_crime_irq (unsigned int irq) -{ - u64 crime_mask; - unsigned long flags; - - /* Edge triggered interrupts must be cleared. */ - if ((irq <= CRIME_GBE0_IRQ && irq >= CRIME_GBE3_IRQ) - || (irq <= CRIME_RE_EMPTY_E_IRQ && irq >= CRIME_RE_IDLE_E_IRQ) - || (irq <= CRIME_SOFT0_IRQ && irq >= CRIME_SOFT2_IRQ)) { - save_and_cli (flags); - crime_mask = crime_read_64 (CRIME_HARD_INT); - crime_mask &= ~(1 << (irq - 1)); - crime_write_64 (CRIME_HARD_INT, crime_mask); - restore_flags (flags); - } - disable_crime_irq (irq); -} - -static void end_crime_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_crime_irq (irq); -} - -#define shutdown_crime_irq disable_crime_irq - -static struct hw_interrupt_type ip32_crime_interrupt = { - "IP32 CRIME", - startup_crime_irq, - shutdown_crime_irq, - enable_crime_irq, - disable_crime_irq, - mask_and_ack_crime_irq, - end_crime_irq, - NULL -}; - -/* This is for MACE PCI interrupts. We can decrease bus traffic by masking - * as close to the source as possible. This also means we can take the - * next chunk of the CRIME register in one piece. - */ - -static void enable_macepci_irq (unsigned int irq) -{ - u32 mace_mask; - u64 crime_mask; - unsigned long flags; - - save_and_cli (flags); - mace_mask = mace_read_32 (MACEPCI_CONTROL); - mace_mask |= MACEPCI_CONTROL_INT (irq - 9); - mace_write_32 (MACEPCI_CONTROL, mace_mask); - /* In case the CRIME interrupt isn't enabled, we must enable it; - * however, we never disable interrupts at that level. - */ - crime_mask = crime_read_64 (CRIME_INT_MASK); - crime_mask |= 1 << (irq - 1); - crime_write_64 (CRIME_INT_MASK, crime_mask); - restore_flags (flags); -} - -static unsigned int startup_macepci_irq (unsigned int irq) { - enable_macepci_irq (irq); - return 0; /* XXX */ -} - -static void disable_macepci_irq (unsigned int irq) -{ - u32 mace_mask; - unsigned long flags; - - save_and_cli (flags); - mace_mask = mace_read_32 (MACEPCI_CONTROL); - mace_mask &= ~MACEPCI_CONTROL_INT (irq - 9); - mace_write_32 (MACEPCI_CONTROL, mace_mask); - restore_flags (flags); -} - -static void end_macepci_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_macepci_irq (irq); -} - -#define shutdown_macepci_irq disable_macepci_irq -#define mask_and_ack_macepci_irq disable_macepci_irq - -static struct hw_interrupt_type ip32_macepci_interrupt = { - "IP32 MACE PCI", - startup_macepci_irq, - shutdown_macepci_irq, - enable_macepci_irq, - disable_macepci_irq, - mask_and_ack_macepci_irq, - end_macepci_irq, - NULL -}; - -/* This is used for MACE ISA interrupts. That means bits 4-6 in the - * CRIME register. - */ - -static void enable_maceisa_irq (unsigned int irq) -{ - u64 crime_mask; - u32 mace_mask; - unsigned int crime_int = 0; - unsigned long flags; - - DBG ("maceisa enable: %u\n", irq); - - switch (irq) { - case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: - crime_int = MACE_AUDIO_INT; - break; - case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ: - crime_int = MACE_MISC_INT; - break; - case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ: - crime_int = MACE_SUPERIO_INT; - break; - } - DBG ("crime_int %016lx enabled\n", crime_int); - save_and_cli (flags); - crime_mask = crime_read_64 (CRIME_INT_MASK); - crime_mask |= crime_int; - crime_write_64 (CRIME_INT_MASK, crime_mask); - mace_mask = mace_read_32 (MACEISA_INT_MASK); - mace_mask |= 1 << (irq - 33); - mace_write_32 (MACEISA_INT_MASK, mace_mask); - restore_flags (flags); -} - -static unsigned int startup_maceisa_irq (unsigned int irq) { - enable_maceisa_irq (irq); - return 0; -} - -static void disable_maceisa_irq (unsigned int irq) -{ - u32 mace_mask; - unsigned long flags; - - save_and_cli (flags); - mace_mask = mace_read_32 (MACEISA_INT_MASK); - mace_mask &= ~(1 << (irq - 33)); - mace_write_32 (MACEISA_INT_MASK, mace_mask); - restore_flags (flags); -} - -static void mask_and_ack_maceisa_irq (unsigned int irq) -{ - u32 mace_mask; - unsigned long flags; - - switch (irq) { - case MACEISA_PARALLEL_IRQ: - case MACEISA_SERIAL1_TDMAPR_IRQ: - case MACEISA_SERIAL2_TDMAPR_IRQ: - save_and_cli (flags); - mace_mask = mace_read_32 (MACEISA_INT_STAT); - mace_mask &= ~(1 << (irq - 33)); - mace_write_32 (MACEISA_INT_STAT, mace_mask); - restore_flags (flags); - break; - } - disable_maceisa_irq (irq); -} - -static void end_maceisa_irq (unsigned irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_maceisa_irq (irq); -} - -#define shutdown_maceisa_irq disable_maceisa_irq - -static struct hw_interrupt_type ip32_maceisa_interrupt = { - "IP32 MACE ISA", - startup_maceisa_irq, - shutdown_maceisa_irq, - enable_maceisa_irq, - disable_maceisa_irq, - mask_and_ack_maceisa_irq, - end_maceisa_irq, - NULL -}; - -/* This is used for regular non-ISA, non-PCI MACE interrupts. That means - * bits 0-3 and 7 in the CRIME register. - */ - -static void enable_mace_irq (unsigned int irq) -{ - u64 crime_mask; - unsigned long flags; - - save_and_cli (flags); - crime_mask = crime_read_64 (CRIME_INT_MASK); - crime_mask |= 1 << (irq - 1); - crime_write_64 (CRIME_INT_MASK, crime_mask); - restore_flags (flags); -} - -static unsigned int startup_mace_irq (unsigned int irq) -{ - enable_mace_irq (irq); - return 0; -} - -static void disable_mace_irq (unsigned int irq) -{ - u64 crime_mask; - unsigned long flags; - - save_and_cli (flags); - crime_mask = crime_read_64 (CRIME_INT_MASK); - crime_mask &= ~(1 << (irq - 1)); - crime_write_64 (CRIME_INT_MASK, crime_mask); - restore_flags (flags); -} - -static void end_mace_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_mace_irq (irq); -} - -#define shutdown_mace_irq disable_mace_irq -#define mask_and_ack_mace_irq disable_mace_irq - -static struct hw_interrupt_type ip32_mace_interrupt = { - "IP32 MACE", - startup_mace_irq, - shutdown_mace_irq, - enable_mace_irq, - disable_mace_irq, - mask_and_ack_mace_irq, - end_mace_irq, - NULL -}; - -static void ip32_unknown_interrupt (struct pt_regs *regs) -{ - u64 crime; - u32 mace; - - printk ("Unknown interrupt occurred!\n"); - printk ("cp0_status: %08x\tcp0_cause: %08x\n", - read_32bit_cp0_register (CP0_STATUS), - read_32bit_cp0_register (CP0_CAUSE)); - crime = crime_read_64 (CRIME_INT_MASK); - printk ("CRIME interrupt mask: %016lx\n", crime); - crime = crime_read_64 (CRIME_INT_STAT); - printk ("CRIME interrupt status: %016lx\n", crime); - crime = crime_read_64 (CRIME_HARD_INT); - printk ("CRIME hardware interrupt register: %016lx\n", crime); - mace = mace_read_32 (MACEISA_INT_MASK); - printk ("MACE ISA interrupt mask: %08x\n", mace); - mace = mace_read_32 (MACEISA_INT_STAT); - printk ("MACE ISA interrupt status: %08x\n", mace); - mace = mace_read_32 (MACEPCI_CONTROL); - printk ("MACE PCI control register: %08x\n", mace); - - printk ("Register dump:\n"); - show_regs (regs); - - printk ("Please mail this report to linux-mips@oss.sgi.com\n"); - printk ("Spinning..."); - while (1) ; -} - -void __init ip32_irq_init(void) -{ - unsigned int irq; - extern void init_generic_irq (void); - - /* Install our interrupt handler, then clear and disable all - * CRIME and MACE interrupts. - */ - crime_write_64 (CRIME_INT_MASK, 0); - crime_write_64 (CRIME_HARD_INT, 0); - crime_write_64 (CRIME_SOFT_INT, 0); - mace_write_32 (MACEISA_INT_STAT, 0); - mace_write_32 (MACEISA_INT_MASK, 0); - set_except_vector(0, ip32_handle_int); - - init_generic_irq (); - - for (irq = 0; irq <= IP32_IRQ_MAX; irq++) { - hw_irq_controller *controller; - - if (irq == CLOCK_IRQ) - controller = &ip32_cpu_interrupt; - else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ) - controller = &ip32_mace_interrupt; - else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ) - controller = &ip32_macepci_interrupt; - else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ) - controller = &ip32_crime_interrupt; - else - controller = &ip32_maceisa_interrupt; - - irq_desc[irq].status = IRQ_DISABLED; - irq_desc[irq].action = 0; - irq_desc[irq].depth = 0; - irq_desc[irq].handler = controller; - } - setup_irq (CRIME_MEMERR_IRQ, &memerr_irq); - setup_irq (CRIME_CPUERR_IRQ, &cpuerr_irq); -} - -/* CRIME 1.1 appears to deliver all interrupts to this one pin. */ -void ip32_irq0 (struct pt_regs *regs) -{ - u64 crime_int = crime_read_64 (CRIME_INT_STAT); - int irq = 0; - - if (crime_int & CRIME_MACE_INT_MASK) { - crime_int &= CRIME_MACE_INT_MASK; - irq = ffs (crime_int); - } else if (crime_int & CRIME_MACEISA_INT_MASK) { - u32 mace_int; - mace_int = mace_read_32 (MACEISA_INT_STAT); - if (mace_int == 0) - irq = 0; - else - irq = ffs (mace_int) + 32; - } else if (crime_int & CRIME_MACEPCI_INT_MASK) { - crime_int &= CRIME_MACEPCI_INT_MASK; - crime_int >>= 8; - irq = ffs (crime_int) + 8; - } else if (crime_int & 0xffff0000) { - crime_int >>= 16; - irq = ffs (crime_int) + 16; - } - if (irq == 0) - ip32_unknown_interrupt (regs); - DBG ("*irq %u*\n", irq); - do_IRQ (irq, regs); -} - -void ip32_irq1 (struct pt_regs *regs) -{ - ip32_unknown_interrupt (regs); -} - -void ip32_irq2 (struct pt_regs *regs) -{ - ip32_unknown_interrupt (regs); -} - -void ip32_irq3 (struct pt_regs *regs) -{ - ip32_unknown_interrupt (regs); -} - -void ip32_irq4 (struct pt_regs *regs) -{ - ip32_unknown_interrupt (regs); -} - -void ip32_irq5 (struct pt_regs *regs) -{ - do_IRQ (CLOCK_IRQ, regs); -} --- linux-2.5.73/arch/mips64/sgi-ip32/ip32-irq-glue.S 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,87 +0,0 @@ -/* - * Low level interrupt handler for the SGI O2 aka IP32 aka Moosehead - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Harald Koerfgen - * Copyright (C) 2001 Keith M Wesolowski - */ -#include -#include -#include -#include -#include -#include - - .text - .set noreorder - .set noat - .align 5 - NESTED(ip32_handle_int, PT_SIZE, ra) - .set noat - SAVE_ALL - CLI # TEST: interrupts should be off - .set at - .set noreorder - - mfc0 s0,CP0_CAUSE - - andi t1, s0, IE_IRQ0 - bnez t1, handle_irq0 - andi t1, s0, IE_IRQ1 - bnez t1, handle_irq1 - andi t1, s0, IE_IRQ2 - bnez t1, handle_irq2 - andi t1, s0, IE_IRQ3 - bnez t1, handle_irq3 - andi t1, s0, IE_IRQ4 - bnez t1, handle_irq4 - andi t1, s0, IE_IRQ5 - bnez t1, handle_irq5 - nop - - /* Either someone has triggered the "software interrupts" - * or we lost an interrupt somehow. Ignore it. - */ - j ret_from_irq - nop - -handle_irq0: - jal ip32_irq0 - move a0, sp - j ret_from_irq - nop - -handle_irq1: - jal ip32_irq1 - move a0, sp - j ret_from_irq - nop - -handle_irq2: - jal ip32_irq2 - move a0, sp - j ret_from_irq - nop - -handle_irq3: - jal ip32_irq3 - move a0, sp - j ret_from_irq - nop - -handle_irq4: - jal ip32_irq4 - move a0, sp - j ret_from_irq - nop - -handle_irq5: - jal ip32_irq5 - move a0, sp - j ret_from_irq - nop - - END(ip32_handle_int) --- linux-2.5.73/arch/mips64/sgi-ip32/ip32-pci.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,425 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000, 2001 Keith M Wesolowski - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#undef DEBUG_MACE_PCI - -/* - * O2 has up to 5 PCI devices connected into the MACE bridge. The device - * map looks like this: - * - * 0 aic7xxx 0 - * 1 aic7xxx 1 - * 2 expansion slot - * 3 N/C - * 4 N/C - */ - -#define chkslot(dev) \ -do { \ - if ((dev)->bus->number > 0 || PCI_SLOT ((dev)->devfn) < 1 \ - || PCI_SLOT ((dev)->devfn) > 3) \ - return PCIBIOS_DEVICE_NOT_FOUND; \ -} while (0) - -#define mkaddr(dev, where) \ -((((dev)->devfn & 0xffUL) << 8) | ((where) & 0xfcUL)) - -void macepci_error (int irq, void *dev, struct pt_regs *regs); - -static int macepci_read_config_byte (struct pci_dev *dev, int where, - u8 *val) -{ - *val = 0xff; - chkslot (dev); - mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (dev, where)); - *val = mace_read_8 (MACEPCI_CONFIG_DATA + ((where & 3UL) ^ 3UL)); - - return PCIBIOS_SUCCESSFUL; -} - -static int macepci_read_config_word (struct pci_dev *dev, int where, - u16 *val) -{ - *val = 0xffff; - chkslot (dev); - if (where & 1) - return PCIBIOS_BAD_REGISTER_NUMBER; - mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (dev, where)); - *val = mace_read_16 (MACEPCI_CONFIG_DATA + ((where & 2UL) ^ 2UL)); - - return PCIBIOS_SUCCESSFUL; -} - -static int macepci_read_config_dword (struct pci_dev *dev, int where, - u32 *val) -{ - *val = 0xffffffff; - chkslot (dev); - if (where & 3) - return PCIBIOS_BAD_REGISTER_NUMBER; - mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (dev, where)); - *val = mace_read_32 (MACEPCI_CONFIG_DATA); - - return PCIBIOS_SUCCESSFUL; -} - -static int macepci_write_config_byte (struct pci_dev *dev, int where, - u8 val) -{ - chkslot (dev); - mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (dev, where)); - mace_write_8 (MACEPCI_CONFIG_DATA + ((where & 3UL) ^ 3UL), val); - - return PCIBIOS_SUCCESSFUL; -} - -static int macepci_write_config_word (struct pci_dev *dev, int where, - u16 val) -{ - chkslot (dev); - if (where & 1) - return PCIBIOS_BAD_REGISTER_NUMBER; - mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (dev, where)); - mace_write_16 (MACEPCI_CONFIG_DATA + ((where & 2UL) ^ 2UL), val); - - return PCIBIOS_SUCCESSFUL; -} - -static int macepci_write_config_dword (struct pci_dev *dev, int where, - u32 val) -{ - chkslot (dev); - if (where & 3) - return PCIBIOS_BAD_REGISTER_NUMBER; - mace_write_32 (MACEPCI_CONFIG_ADDR, mkaddr (dev, where)); - mace_write_32 (MACEPCI_CONFIG_DATA, val); - - return PCIBIOS_SUCCESSFUL; -} - -static struct pci_ops macepci_ops = { - macepci_read_config_byte, - macepci_read_config_word, - macepci_read_config_dword, - macepci_write_config_byte, - macepci_write_config_word, - macepci_write_config_dword -}; - -struct pci_fixup pcibios_fixups[] = { { 0 } }; - -void __init pcibios_init (void) -{ - struct pci_dev *dev = NULL; - u32 start, size; - u16 cmd; - u32 base_io = 0x3000; /* The first i/o address to assign after SCSI */ - u32 base_mem = 0x80100000; /* Likewise */ - u32 rev = mace_read_32 (MACEPCI_REV); - int i; - - printk ("MACE: PCI rev %d detected at %016lx\n", rev, - (u64) MACE_BASE + MACE_PCI); - - /* These are *bus* addresses */ - ioport_resource.start = 0; - ioport_resource.end = 0xffffffffUL; - iomem_resource.start = 0x80000000UL; - iomem_resource.end = 0xffffffffUL; - - /* Clear any outstanding errors and enable interrupts */ - mace_write_32 (MACEPCI_ERROR_ADDR, 0); - mace_write_32 (MACEPCI_ERROR_FLAGS, 0); - mace_write_32 (MACEPCI_CONTROL, 0xff008500); - crime_write_64 (CRIME_HARD_INT, 0UL); - crime_write_64 (CRIME_SOFT_INT, 0UL); - crime_write_64 (CRIME_INT_STAT, 0x000000000000ff00UL); - - if (request_irq (MACE_PCI_BRIDGE_IRQ, macepci_error, 0, - "MACE PCI error", NULL)) - panic ("PCI bridge can't get interrupt; can't happen.\n"); - - pci_scan_bus (0, &macepci_ops, NULL); - -#ifdef DEBUG_MACE_PCI - while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { - printk ("Device: %d/%d/%d ARCS-assigned bus resource map\n", - dev->bus->number, PCI_SLOT (dev->devfn), - PCI_FUNC (dev->devfn)); - for (i=0; i < DEVICE_COUNT_RESOURCE; i++) { - if (dev->resource[i].start == 0) - continue; - printk ("%d: %016lx - %016lx (flags %04lx)\n", - i, dev->resource[i].start, - dev->resource[i].end, dev->resource[i].flags); - } - } -#endif - /* - * Assign sane resources to and enable all devices. The requirement - * for the SCSI controllers is well-known: a 256-byte I/O region - * which we must assign, and a 1-page memory region which is - * assigned by the system firmware. - */ - dev = NULL; - while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { - switch (PCI_SLOT (dev->devfn)) { - case 1: /* SCSI bus 0 */ - dev->resource[0].start = 0x1000UL; - dev->resource[0].end = 0x10ffUL; - break; - case 2: /* SCSI bus 1 */ - dev->resource[0].start = 0x2000UL; - dev->resource[0].end = 0x20ffUL; - break; - default: /* Slots - I guess we have only 1 */ - for (i=0; i < 6; i++) { - size = dev->resource[i].end - - dev->resource[i].start; - if (!size - || !(dev->resource[i].flags - & (IORESOURCE_IO|IORESOURCE_MEM))) { - dev->resource[i].start - = dev->resource[i].end = 0UL; - continue; - } - if (dev->resource[i].flags & IORESOURCE_IO) { - dev->resource[i].start = base_io; - base_io += PAGE_ALIGN (size); - } else { - dev->resource[i].start = base_mem; - base_mem += 0x100000UL; - } - dev->resource[i].end = - dev->resource[i].start + size; - } - break; - } - for (i=0; i < 6; i++) { - if (dev->resource[i].start == 0) - continue; - start = dev->resource[i].start; - if (dev->resource[i].flags & IORESOURCE_IO) - start |= 1; - pci_write_config_dword (dev, - PCI_BASE_ADDRESS_0 + (i << 2), (u32) start); - } - pci_write_config_byte (dev, PCI_CACHE_LINE_SIZE, 0x20); - pci_write_config_byte (dev, PCI_LATENCY_TIMER, 0x30); - pci_read_config_word (dev, PCI_COMMAND, &cmd); - cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY); - pci_write_config_word (dev, PCI_COMMAND, cmd); - pci_set_master (dev); - } - -#ifdef DEBUG_MACE_PCI - printk ("Triggering PCI bridge interrupt...\n"); - mace_write_32 (MACEPCI_ERROR_FLAGS, MACEPCI_ERROR_INTERRUPT_TEST); - - dev = NULL; - while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { - printk ("Device: %d/%d/%d final bus resource map\n", - dev->bus->number, PCI_SLOT (dev->devfn), - PCI_FUNC (dev->devfn)); - for (i=0; i < DEVICE_COUNT_RESOURCE; i++) { - if (dev->resource[i].start == 0) - continue; - printk ("%d: %016lx - %016lx (flags %04lx)\n", - i, dev->resource[i].start, - dev->resource[i].end, dev->resource[i].flags); - } - } -#endif -} - -/* - * Given a PCI slot number (a la PCI_SLOT(...)) and the interrupt pin of - * the device (1-4 => A-D), tell what irq to use. Note that we don't - * in theory have slots 4 and 5, and we never normally use the shared - * irqs. I suppose a device without a pin A will thank us for doing it - * right if there exists such a broken piece of crap. - */ -static int __init macepci_map_irq (struct pci_dev *dev, u8 slot, u8 pin) -{ - chkslot (dev); - if (pin == 0) - pin = 1; - switch (slot) { - case 1: - return MACEPCI_SCSI0_IRQ; - case 2: - return MACEPCI_SCSI1_IRQ; - case 3: - switch (pin) { - case 2: - return MACEPCI_SHARED0_IRQ; - case 3: - return MACEPCI_SHARED1_IRQ; - case 4: - return MACEPCI_SHARED2_IRQ; - case 1: - default: - return MACEPCI_SLOT0_IRQ; - } - case 4: - switch (pin) { - case 2: - return MACEPCI_SHARED2_IRQ; - case 3: - return MACEPCI_SHARED0_IRQ; - case 4: - return MACEPCI_SHARED1_IRQ; - case 1: - default: - return MACEPCI_SLOT1_IRQ; - } - return MACEPCI_SLOT1_IRQ; - case 5: - switch (pin) { - case 2: - return MACEPCI_SHARED1_IRQ; - case 3: - return MACEPCI_SHARED2_IRQ; - case 4: - return MACEPCI_SHARED0_IRQ; - case 1: - default: - return MACEPCI_SLOT2_IRQ; - } - default: - return 0; - } -} - -/* - * It's not entirely clear what this does in a system with no bridges. - * In any case, bridges are not supported by Linux in O2. - */ -static u8 __init macepci_swizzle (struct pci_dev *dev, u8 *pinp) -{ - if (PCI_SLOT (dev->devfn) == 2) - *pinp = 2; - else - *pinp = 1; - return PCI_SLOT (dev->devfn); -} - -/* All devices are enabled during initialization. */ -int pcibios_enable_device (struct pci_dev *dev) -{ - return PCIBIOS_SUCCESSFUL; -} - -char * __init pcibios_setup (char *str) -{ - return str; -} - -void __init pcibios_align_resource (void *data, struct resource *res, - unsigned long size, unsigned long align) -{ -} - -void __init pcibios_update_irq (struct pci_dev *dev, int irq) -{ - pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); -} - -void __init pcibios_fixup_bus (struct pci_bus *b) -{ - pci_fixup_irqs (macepci_swizzle, macepci_map_irq); -} - -/* - * Handle errors from the bridge. This includes master and target aborts, - * various command and address errors, and the interrupt test. This gets - * registered on the bridge error irq. It's conceivable that some of these - * conditions warrant a panic. Anybody care to say which ones? - */ -void macepci_error (int irq, void *dev, struct pt_regs *regs) { - u32 flags, error_addr; - char space; - - flags = mace_read_32 (MACEPCI_ERROR_FLAGS); - error_addr = mace_read_32 (MACEPCI_ERROR_ADDR); - - if (flags & MACEPCI_ERROR_MEMORY_ADDR) - space = 'M'; - else if (flags & MACEPCI_ERROR_CONFIG_ADDR) - space = 'C'; - else space = 'X'; - - if (flags & MACEPCI_ERROR_MASTER_ABORT) { - printk ("MACEPCI: Master abort at 0x%08x (%c)\n", error_addr, - space); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_MASTER_ABORT); - } - if (flags & MACEPCI_ERROR_TARGET_ABORT) { - printk ("MACEPCI: Target abort at 0x%08x (%c)\n", error_addr, - space); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_TARGET_ABORT); - } - if (flags & MACEPCI_ERROR_DATA_PARITY_ERR) { - printk ("MACEPCI: Data parity error at 0x%08x (%c)\n", - error_addr, space); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_DATA_PARITY_ERR); - } - if (flags & MACEPCI_ERROR_RETRY_ERR) { - printk ("MACEPCI: Retry error at 0x%08x (%c)\n", error_addr, - space); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_RETRY_ERR); - } - if (flags & MACEPCI_ERROR_ILLEGAL_CMD) { - printk ("MACEPCI: Illegal command at 0x%08x (%c)\n", - error_addr, space); - mace_write_32 (MACEPCI_ERROR_FLAGS, - flags & ~MACEPCI_ERROR_ILLEGAL_CMD); - } - if (flags & MACEPCI_ERROR_SYSTEM_ERR) { - printk ("MACEPCI: System error at 0x%08x (%c)\n", - error_addr, space); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_SYSTEM_ERR); - } - if (flags & MACEPCI_ERROR_PARITY_ERR) { - printk ("MACEPCI: Parity error at 0x%08x (%c)\n", error_addr, - space); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_PARITY_ERR); - } - if (flags & MACEPCI_ERROR_OVERRUN) { - printk ("MACEPCI: Overrun error at 0x%08x (%c)\n", - error_addr, space); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_OVERRUN); - } - if (flags & MACEPCI_ERROR_SIG_TABORT) { - printk ("MACEPCI: Signaled target abort (clearing)\n"); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_SIG_TABORT); - } - if (flags & MACEPCI_ERROR_INTERRUPT_TEST) { - printk ("MACEPCI: Interrupt test triggered (clearing)\n"); - mace_write_32 (MACEPCI_ERROR_FLAGS, flags - & ~MACEPCI_ERROR_INTERRUPT_TEST); - } -} --- linux-2.5.73/arch/mips64/sgi-ip32/ip32-pci-dma.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,41 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Ani Joshi - * Copyright (C) 2000 Ralf Baechle - * swiped from i386, and cloned for MIPS by Geert, polished by Ralf. - */ -#include -#include -#include -#include - -#include -#include -#include - -void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, - dma_addr_t * dma_handle) -{ - void *ret; - int gfp = GFP_ATOMIC; - - if (hwdev == NULL || hwdev->dma_mask != 0xffffffff) - gfp |= GFP_DMA; - ret = (void *) __get_free_pages(gfp, get_order(size)); - - if (ret != NULL) { - memset(ret, 0, size); - dma_cache_wback_inv((unsigned long) ret, size); - *dma_handle = virt_to_bus(ret); - } - return ret; -} - -void pci_free_consistent(struct pci_dev *hwdev, size_t size, - void *vaddr, dma_addr_t dma_handle) -{ - free_pages((unsigned long) vaddr, get_order(size)); -} --- linux-2.5.73/arch/mips64/sgi-ip32/ip32-rtc.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,32 +0,0 @@ -/* - * RTC routines for IP32 style attached Dallas chip. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Harald Koerfgen - */ -#include -#include - -static unsigned char ip32_rtc_read_data(unsigned long addr) -{ - return (unsigned char) mace_read_8 (MACEISA_RTC_BASE + (addr << 8)); -} - -static void ip32_rtc_write_data(unsigned char data, unsigned long addr) -{ - mace_write_8 (MACEISA_RTC_BASE + (addr << 8), data); -} - -static int ip32_rtc_bcd_mode(void) -{ - return 0; -} - -struct rtc_ops ip32_rtc_ops = { - &ip32_rtc_read_data, - &ip32_rtc_write_data, - &ip32_rtc_bcd_mode -}; --- linux-2.5.73/arch/mips64/sgi-ip32/ip32-setup.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,62 +0,0 @@ -/* - * IP32 basic setup - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Harald Koerfgen - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern struct rtc_ops ip32_rtc_ops; -extern u32 cc_interval; - -void __init ip32_init (int argc, char **argv, char **envp) { - arc_meminit (); -} - -void __init ip32_setup(void) -{ -#ifdef CONFIG_SERIAL_CONSOLE - char *ctype; -#endif - TLBMISS_HANDLER_SETUP (); - -#ifdef CONFIG_SERIAL_CONSOLE - ctype = ArcGetEnvironmentVariable("console"); - if (*ctype == 'd') { - if (ctype[1] == '2') - console_setup ("ttyS1"); - else - console_setup ("ttyS0"); - } -#endif - -#ifdef CONFIG_VT - conswitchp = &dummy_con; -#endif - - rtc_ops = &ip32_rtc_ops; - - crime_init (); -} - -int __init page_is_ram (unsigned long pagenr) -{ - /* XXX: to do? */ - return 1; -} --- linux-2.5.73/arch/mips64/sgi-ip32/ip32-timer.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,47 +0,0 @@ -/* - * IP32 timer calibration - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2001 Keith M Wesolowski - */ -#include -#include -#include -#include -#include -#include -#include - -extern u32 cc_interval; - -/* An arbitrary time; this can be decreased if reliability looks good */ -#define WAIT_MS 10 -#define PER_MHZ (1000000 / 2 / HZ) - -void __init ip32_timer_setup (struct irqaction *irq) { - u64 crime_time; - u32 cc_tick; - - printk("Calibrating system timer... "); - - crime_time = crime_read_64 (CRIME_TIME) & CRIME_TIME_MASK; - cc_tick = read_32bit_cp0_register (CP0_COUNT); - - while ((crime_read_64 (CRIME_TIME) & CRIME_TIME_MASK) - crime_time - < WAIT_MS * 1000000 / CRIME_NS_PER_TICK) - ; - cc_tick = read_32bit_cp0_register (CP0_COUNT) - cc_tick; - cc_interval = cc_tick / HZ * (1000 / WAIT_MS); - /* The round-off seems unnecessary; in testing, the error of the - * above procedure is < 100 ticks, which means it gets filtered - * out by the HZ adjustment. - */ - cc_interval = (cc_interval / PER_MHZ) * PER_MHZ; - - printk("%d MHz CPU detected\n", (int) (cc_interval / PER_MHZ)); - - setup_irq (CLOCK_IRQ, irq); -} --- linux-2.5.73/arch/mips64/sgi-ip32/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,13 +0,0 @@ -# -# Makefile for the SGI specific kernel interface routines -# under Linux. -# - -extra-y := ip32-irq-glue.o - -obj-y += ip32-irq.o ip32-rtc.o ip32-setup.o ip32-irq-glue.o \ - ip32-berr.o ip32-timer.o crime.o - -obj-$(CONFIG_PCI) += ip32-pci.o ip32-pci-dma.o - -EXTRA_AFLAGS := $(CFLAGS) --- linux-2.5.73/arch/mips64/tools/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,23 +0,0 @@ -# -# Makefile for MIPS kernel build tools. -# -# Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) -# Copyright (C) 1997, 1999 Ralf Baechle (ralf@gnu.org) -# Copyright (C) 1999 Silicon Graphics, Inc. -# -TARGET := $(TOPDIR)/include/asm-$(ARCH)/offset.h - -$(TARGET): offset.h - cmp -s $^ $@ || (cp $^ $(TARGET).new && mv $(TARGET).new $(TARGET)) - -offset.h: offset.s - sed -n '/^@@@/s///p' $^ >$@ - -offset.s: offset.c $(TOPDIR)/include/linux/autoconf.h - -clean: - rm -f offset.[hs] $(TARGET).new - -mrproper: - rm -f offset.[hs] $(TARGET).new - rm -f $(TARGET) --- linux-2.5.73/arch/mips64/tools/offset.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,150 +0,0 @@ -/* - * offset.c: Calculate pt_regs and task_struct offsets. - * - * Copyright (C) 1996 David S. Miller - * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#include -#include - -#include -#include - -#define text(t) __asm__("\n@@@" t) -#define _offset(type, member) (&(((type *)NULL)->member)) - -#define offset(string, ptr, member) \ - __asm__("\n@@@" string "%0" : : "i" (_offset(ptr, member))) -#define size(string, size) \ - __asm__("\n@@@" string "%0" : : "i" (sizeof(size))) -#define linefeed text("") - -text("/* DO NOT TOUCH, AUTOGENERATED BY OFFSET.C */"); -linefeed; -text("#ifndef _MIPS_OFFSET_H"); -text("#define _MIPS_OFFSET_H"); -linefeed; - -void output_ptreg_defines(void) -{ - text("/* MIPS pt_regs offsets. */"); - offset("#define PT_R0 ", struct pt_regs, regs[0]); - offset("#define PT_R1 ", struct pt_regs, regs[1]); - offset("#define PT_R2 ", struct pt_regs, regs[2]); - offset("#define PT_R3 ", struct pt_regs, regs[3]); - offset("#define PT_R4 ", struct pt_regs, regs[4]); - offset("#define PT_R5 ", struct pt_regs, regs[5]); - offset("#define PT_R6 ", struct pt_regs, regs[6]); - offset("#define PT_R7 ", struct pt_regs, regs[7]); - offset("#define PT_R8 ", struct pt_regs, regs[8]); - offset("#define PT_R9 ", struct pt_regs, regs[9]); - offset("#define PT_R10 ", struct pt_regs, regs[10]); - offset("#define PT_R11 ", struct pt_regs, regs[11]); - offset("#define PT_R12 ", struct pt_regs, regs[12]); - offset("#define PT_R13 ", struct pt_regs, regs[13]); - offset("#define PT_R14 ", struct pt_regs, regs[14]); - offset("#define PT_R15 ", struct pt_regs, regs[15]); - offset("#define PT_R16 ", struct pt_regs, regs[16]); - offset("#define PT_R17 ", struct pt_regs, regs[17]); - offset("#define PT_R18 ", struct pt_regs, regs[18]); - offset("#define PT_R19 ", struct pt_regs, regs[19]); - offset("#define PT_R20 ", struct pt_regs, regs[20]); - offset("#define PT_R21 ", struct pt_regs, regs[21]); - offset("#define PT_R22 ", struct pt_regs, regs[22]); - offset("#define PT_R23 ", struct pt_regs, regs[23]); - offset("#define PT_R24 ", struct pt_regs, regs[24]); - offset("#define PT_R25 ", struct pt_regs, regs[25]); - offset("#define PT_R26 ", struct pt_regs, regs[26]); - offset("#define PT_R27 ", struct pt_regs, regs[27]); - offset("#define PT_R28 ", struct pt_regs, regs[28]); - offset("#define PT_R29 ", struct pt_regs, regs[29]); - offset("#define PT_R30 ", struct pt_regs, regs[30]); - offset("#define PT_R31 ", struct pt_regs, regs[31]); - offset("#define PT_LO ", struct pt_regs, lo); - offset("#define PT_HI ", struct pt_regs, hi); - offset("#define PT_EPC ", struct pt_regs, cp0_epc); - offset("#define PT_BVADDR ", struct pt_regs, cp0_badvaddr); - offset("#define PT_STATUS ", struct pt_regs, cp0_status); - offset("#define PT_CAUSE ", struct pt_regs, cp0_cause); - size("#define PT_SIZE ", struct pt_regs); - linefeed; -} - -void output_task_defines(void) -{ - text("/* MIPS task_struct offsets. */"); - offset("#define TASK_STATE ", struct task_struct, state); - offset("#define TASK_FLAGS ", struct task_struct, flags); -#error offset("#define TASK_SIGPENDING ", struct task_struct, sigpending); -#error offset("#define TASK_NEED_RESCHED ", struct task_struct, need_resched); -#error offset("#define TASK_PTRACE ", struct task_struct, ptrace); - offset("#define TASK_COUNTER ", struct task_struct, counter); - offset("#define TASK_NICE ", struct task_struct, nice); - offset("#define TASK_MM ", struct task_struct, mm); - offset("#define TASK_PROCESSOR ", struct task_struct, processor); - size("#define TASK_STRUCT_SIZE ", struct task_struct); - linefeed; -} - -void output_thread_defines(void) -{ - text("/* MIPS specific thread_struct offsets. */"); - offset("#define THREAD_REG16 ", struct task_struct, thread.reg16); - offset("#define THREAD_REG17 ", struct task_struct, thread.reg17); - offset("#define THREAD_REG18 ", struct task_struct, thread.reg18); - offset("#define THREAD_REG19 ", struct task_struct, thread.reg19); - offset("#define THREAD_REG20 ", struct task_struct, thread.reg20); - offset("#define THREAD_REG21 ", struct task_struct, thread.reg21); - offset("#define THREAD_REG22 ", struct task_struct, thread.reg22); - offset("#define THREAD_REG23 ", struct task_struct, thread.reg23); - offset("#define THREAD_REG29 ", struct task_struct, thread.reg29); - offset("#define THREAD_REG30 ", struct task_struct, thread.reg30); - offset("#define THREAD_REG31 ", struct task_struct, thread.reg31); - offset("#define THREAD_STATUS ", struct task_struct, \ - thread.cp0_status); - offset("#define THREAD_FPU ", struct task_struct, thread.fpu); - offset("#define THREAD_BVADDR ", struct task_struct, \ - thread.cp0_badvaddr); - offset("#define THREAD_BUADDR ", struct task_struct, \ - thread.cp0_baduaddr); - offset("#define THREAD_ECODE ", struct task_struct, \ - thread.error_code); - offset("#define THREAD_TRAPNO ", struct task_struct, thread.trap_no); - offset("#define THREAD_MFLAGS ", struct task_struct, thread.mflags); - offset("#define THREAD_CURDS ", struct task_struct, \ - thread.current_ds); - offset("#define THREAD_TRAMP ", struct task_struct, \ - thread.irix_trampoline); - offset("#define THREAD_OLDCTX ", struct task_struct, \ - thread.irix_oldctx); - linefeed; -} - -void output_mm_defines(void) -{ - text("/* Linux mm_struct offsets. */"); - offset("#define MM_USERS ", struct mm_struct, mm_users); - offset("#define MM_PGD ", struct mm_struct, pgd); - offset("#define MM_CONTEXT ", struct mm_struct, context); - linefeed; -} - -void output_sc_defines(void) -{ - text("/* Linux sigcontext offsets. */"); - offset("#define SC_REGS ", struct sigcontext, sc_regs); - offset("#define SC_FPREGS ", struct sigcontext, sc_fpregs); - offset("#define SC_MDHI ", struct sigcontext, sc_mdhi); - offset("#define SC_MDLO ", struct sigcontext, sc_mdlo); - offset("#define SC_PC ", struct sigcontext, sc_pc); - offset("#define SC_STATUS ", struct sigcontext, sc_status); - offset("#define SC_OWNEDFP ", struct sigcontext, sc_ownedfp); - offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr); - offset("#define SC_FPC_EIR ", struct sigcontext, sc_fpc_eir); - offset("#define SC_CAUSE ", struct sigcontext, sc_cause); - offset("#define SC_BADVADDR ", struct sigcontext, sc_badvaddr); - linefeed; -} - -text("#endif /* !(_MIPS_OFFSET_H) */"); --- linux-2.5.73/arch/mips64/vmlinux.lds.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips64/vmlinux.lds.S 2003-06-27 15:56:24.000000000 -0700 @@ -1,18 +1,38 @@ #include +#undef mips /* CPP really sucks for this job */ +#define mips mips OUTPUT_ARCH(mips) ENTRY(kernel_entry) +jiffies = jiffies_64; SECTIONS { +#ifdef CONFIG_BOOT_ELF64 /* Read-only sections, merged into text segment: */ - .init : { *(.init) } =0 - .text : - { + /* . = 0xc000000000000000; */ + + /* This is the value for an Origin kernel, taken from an IRIX kernel. */ + /* . = 0xc00000000001c000; */ + + /* Set the vaddr for the text segment to a value + >= 0xa800 0000 0001 9000 if no symmon is going to configured + >= 0xa800 0000 0030 0000 otherwise */ + + /* . = 0xa800000000300000; */ + /* . = 0xa800000000300000; */ + . = 0xffffffff80300000; +#endif + . = LOADADDR; + /* read-only */ + _text = .; /* Text and read-only data */ + .text : { *(.text) - /* .gnu.warning sections are handled specially by elf32.em. */ + *(.fixup) *(.gnu.warning) } =0 + _etext = .; /* End of text section */ + . = ALIGN(16); /* Exception table */ __start___ex_table = .; __ex_table : { *(__ex_table) } @@ -23,30 +43,74 @@ SECTIONS __stop___dbe_table = .; RODATA - - _etext = .; - . = ALIGN(16384); - . = . + MAPPED_OFFSET; /* for CONFIG_MAPPED_KERNEL */ - .data.init_task : { *(.data.init_task) } + . = ALIGN(64); + + /* writeable */ + .data : { /* Data */ + *(.data) + + /* Align the initial ramdisk image (INITRD) on page boundaries. */ + . = ALIGN(4096); + __rd_start = .; + *(.initrd) + . = ALIGN(4096); + __rd_end = .; + + CONSTRUCTORS + } + _gp = . + 0x8000; + .lit8 : { *(.lit8) } + .lit4 : { *(.lit4) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata : { *(.sdata) } + + . = ALIGN(4096); + __nosave_begin = .; + .data_nosave : { *(.data.nosave) } + . = ALIGN(4096); + __nosave_end = .; - /* Startup code */ . = ALIGN(4096); + .data.page_aligned : { *(.data.idt) } + + . = ALIGN(32); + .data.cacheline_aligned : { *(.data.cacheline_aligned) } + + _edata = .; /* End of data section */ + + . = ALIGN(16384); /* init_task */ + . = . + MAPPED_OFFSET; /* for CONFIG_MAPPED_KERNEL */ + .data.init_task : { *(.data.init_task) } + + /* will be freed after init */ + . = ALIGN(4096); /* Init code and data */ __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } + /* /DISCARD/ doesn't work for .reginfo */ + .reginfo : { *(.reginfo) } + .init.text : { + _sinittext = .; + *(.init.text) + _einittext = .; + } + .init.data : { *(.init.data) } . = ALIGN(16); __setup_start = .; - .setup.init : { *(.setup.init) } + .init.setup : { *(.init.setup) } __setup_end = .; + __start___param = .; + __param : { *(__param) } + __stop___param = .; __initcall_start = .; .initcall.init : { - *(.initcall1.init) - *(.initcall2.init) - *(.initcall3.init) - *(.initcall4.init) - *(.initcall5.init) - *(.initcall6.init) + *(.initcall1.init) + *(.initcall2.init) + *(.initcall3.init) + *(.initcall4.init) + *(.initcall5.init) + *(.initcall6.init) *(.initcall7.init) } __initcall_end = .; @@ -54,68 +118,40 @@ SECTIONS .con_initcall.init : { *(.con_initcall.init) } __con_initcall_end = .; SECURITY_INIT - . = ALIGN(4096); /* Align double page for init_task_union */ - __init_end = .; - . = ALIGN(4096); - .data.page_aligned : { *(.data.idt) } - + __initramfs_start = .; + .init.ramfs : { *(.init.ramfs) } + __initramfs_end = .; . = ALIGN(32); - .data.cacheline_aligned : { *(.data.cacheline_aligned) } + __per_cpu_start = .; + .data.percpu : { *(.data.percpu) } + __per_cpu_end = .; + . = ALIGN(4096); + __init_end = .; + /* freed after init ends here */ - .fini : { *(.fini) } =0 - .reginfo : { *(.reginfo) } - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. It would - be more correct to do this: - . = .; - The current expression does not correctly handle the case of a - text segment ending precisely at the end of a page; it causes the - data segment to skip a page. The above expression does not have - this problem, but it will currently (2/95) cause BFD to allocate - a single segment, combining both text and data, for this case. - This will prevent the text segment from being shared among - multiple executions of the program; I think that is more - important than losing a page of the virtual address space (note - that no actual memory is lost; the page which is skipped can not - be referenced). */ - . = .; - .data : - { - _fdata = . ; - *(.data) - CONSTRUCTORS + __bss_start = .; /* BSS */ + .sbss : { + *(.sbss) + *(.scommon) } - .data1 : { *(.data1) } - .lit8 : { *(.lit8) } - .lit4 : { *(.lit4) } - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - .got : { *(.got.plt) *(.got) } - .dynamic : { *(.dynamic) } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata : { *(.sdata) } - _edata = .; + .bss : { + *(.bss) + *(COMMON) + } + __bss_stop = .; - .sbss : { *(.sbss) *(.scommon) } - .bss : - { - *(.dynbss) - *(.bss) - *(COMMON) _end = . ; - } /* Sections to be discarded */ - /DISCARD/ : - { - *(.text.exit) - *(.data.exit) + /DISCARD/ : { + *(.exit.text) + *(.exit.data) *(.exitcall.exit) } + /* This is the MIPS specific mdebug section. */ + .mdebug : { *(.mdebug) } /* These are needed for ELF backends which have not yet been converted to the new style linker. */ .stab 0 : { *(.stab) } @@ -133,4 +169,6 @@ SECTIONS /* These must appear regardless of . */ .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } + .comment : { *(.comment) } + .note : { *(.note) } } --- linux-2.5.73/arch/mips/algor/README 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,5 +0,0 @@ -The code for the Algorithmics P4032 evaluation board is currently under -development. I'll release it when it's up to the same strength as -the other ports. - - Ralf --- linux-2.5.73/arch/mips/arc/arc_con.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/arc/arc_con.c 2003-06-27 15:56:23.000000000 -0700 @@ -2,69 +2,49 @@ * Wrap-around code for a console using the * ARC io-routines. * - * Copyright (c) 1998 Harald Koerfgen + * Copyright (c) 1998 Harald Koerfgen + * Copyright (c) 2001 Ralf Baechle + * Copyright (c) 2002 Thiemo Seufer */ - #include #include -#include #include #include #include - -extern char prom_getchar (void); -extern void prom_printf (char *, ...); +#include static void prom_console_write(struct console *co, const char *s, unsigned count) { - unsigned i; - - /* - * Now, do each character - */ - for (i = 0; i < count; i++) { - if (*s == 10) - prom_printf("%c", 13); - prom_printf("%c", *s++); + /* Do each character */ + while (count--) { + if (*s == '\n') + prom_putchar('\r'); + prom_putchar(*s++); } } -static int prom_console_wait_key(struct console *co) -{ - return prom_getchar(); -} - static int __init prom_console_setup(struct console *co, char *options) { - return 0; -} - -static kdev_t prom_console_device(struct console *c) -{ - return MKDEV(TTY_MAJOR, 64 + c->index); + return !(prom_flags & PROM_FLAG_USE_AS_CONSOLE); } static struct console arc_cons = { - "ttyS", - prom_console_write, - NULL, - prom_console_device, - prom_console_wait_key, - NULL, - prom_console_setup, - CON_PRINTBUFFER, - -1, - 0, - NULL + .name = "arc", + .write = prom_console_write, + .setup = prom_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, }; /* * Register console. */ -static void __init arc_console_init(void) +static int __init arc_console_init(void) { register_console(&arc_cons); + + return 0; } console_initcall(arc_console_init); --- linux-2.5.73/arch/mips/arc/cmdline.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/arc/cmdline.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,4 +1,8 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * cmdline.c: Kernel command line creation using ARCS argc/argv. * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) @@ -12,11 +16,11 @@ #undef DEBUG_CMDLINE -char arcs_cmdline[COMMAND_LINE_SIZE]; +char arcs_cmdline[CL_SIZE]; char * __init prom_getcmdline(void) { - return &(arcs_cmdline[0]); + return arcs_cmdline; } static char *ignored[] = { @@ -28,7 +32,6 @@ static char *ignored[] = { "OSLoadFilename=", "OSLoadOptions=" }; -#define NENTS(foo) ((sizeof((foo)) / (sizeof((foo[0]))))) static char *used_arc[][2] = { { "OSLoadPartition=", "root=" }, @@ -43,16 +46,16 @@ static char * __init move_firmware_args( actr = 1; /* Always ignore argv[0] */ while (actr < prom_argc) { - for(i = 0; i < NENTS(used_arc); i++) { + for(i = 0; i < ARRAY_SIZE(used_arc); i++) { int len = strlen(used_arc[i][0]); - if(!strncmp(prom_argv[actr], used_arc[i][0], len)) { + if (!strncmp(prom_argv(actr), used_arc[i][0], len)) { /* Ok, we want it. First append the replacement... */ strcat(cp, used_arc[i][1]); cp += strlen(used_arc[i][1]); /* ... and now the argument */ - s = strstr(prom_argv[actr], "="); - if(s) { + s = strstr(prom_argv(actr), "="); + if (s) { s++; strcpy(cp, s); cp += strlen(s); @@ -67,7 +70,6 @@ static char * __init move_firmware_args( return cp; } - void __init prom_init_cmdline(void) { char *cp; @@ -75,33 +77,34 @@ void __init prom_init_cmdline(void) actr = 1; /* Always ignore argv[0] */ - cp = &(arcs_cmdline[0]); - /* + cp = arcs_cmdline; + /* * Move ARC variables to the beginning to make sure they can be * overridden by later arguments. */ cp = move_firmware_args(cp); while (actr < prom_argc) { - for (i = 0; i < NENTS(ignored); i++) { + for (i = 0; i < ARRAY_SIZE(ignored); i++) { int len = strlen(ignored[i]); - if(!strncmp(prom_argv[actr], ignored[i], len)) + if (!strncmp(prom_argv(actr), ignored[i], len)) goto pic_cont; } /* Ok, we want it. */ - strcpy(cp, prom_argv[actr]); - cp += strlen(prom_argv[actr]); + strcpy(cp, prom_argv(actr)); + cp += strlen(prom_argv(actr)); *cp++ = ' '; pic_cont: actr++; } - if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ + + if (cp != arcs_cmdline) /* get rid of trailing space */ --cp; *cp = '\0'; #ifdef DEBUG_CMDLINE - prom_printf("prom_init_cmdline: %s\n", &(arcs_cmdline[0])); + printk(KERN_DEBUG "prom cmdline: %s\n", arcs_cmdline); #endif } --- linux-2.5.73/arch/mips/arc/console.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/arc/console.c 2003-06-27 15:56:23.000000000 -0700 @@ -6,14 +6,9 @@ * Copyright (C) 1996 David S. Miller (dm@sgi.com) * Compability with board caches, Ulf Carlsson */ -#include -#include #include #include #include -#include -#include -#include /* * IP22 boardcache is not compatible with board caches. Thus we disable it @@ -27,44 +22,42 @@ void prom_putchar(char c) { - long cnt; - char it = c; + ULONG cnt; + CHAR it = c; bc_disable(); - romvec->write(1, &it, 1, &cnt); + ArcWrite(1, &it, 1, &cnt); bc_enable(); } -char __init prom_getchar(void) +char prom_getchar(void) { - long cnt; - char c; + ULONG cnt; + CHAR c; bc_disable(); - romvec->read(0, &c, 1, &cnt); + ArcRead(0, &c, 1, &cnt); bc_enable(); return c; } -static char ppbuf[1024]; - void prom_printf(char *fmt, ...) { va_list args; - char ch, *bptr; - int i; + char ppbuf[1024]; + char *bptr; va_start(args, fmt); - i = vsprintf(ppbuf, fmt, args); + vsprintf(ppbuf, fmt, args); bptr = ppbuf; - while ((ch = *(bptr++)) != 0) { - if (ch == '\n') + while (*bptr != 0) { + if (*bptr == '\n') prom_putchar('\r'); - prom_putchar(ch); + prom_putchar(*bptr++); } va_end(args); } --- linux-2.5.73/arch/mips/arc/env.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/arc/env.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,24 +1,27 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * env.c: ARCS environment variable routines. * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * - * $Id: env.c,v 1.2 1999/10/09 00:00:57 ralf Exp $ */ #include #include #include +#include #include PCHAR __init ArcGetEnvironmentVariable(CHAR *name) { - return romvec->get_evar(name); + return (CHAR *) ARC_CALL1(get_evar, name); } LONG __init ArcSetEnvironmentVariable(PCHAR name, PCHAR value) { - return romvec->set_evar(name, value); + return ARC_CALL2(set_evar, name, value); } --- linux-2.5.73/arch/mips/arc/file.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/arc/file.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,59 +1,75 @@ /* - * file.c: ARCS firmware interface to files. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * ARC firmware interface. * - * $Id: file.c,v 1.1 1998/10/18 13:32:08 tsbogend Exp $ + * Copyright (C) 1994, 1995, 1996, 1999 Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. */ #include + +#include #include -long __init prom_getvdirent(unsigned long fd, struct linux_vdirent *ent, unsigned long num, unsigned long *cnt) +LONG __init +ArcGetDirectoryEntry(ULONG FileID, struct linux_vdirent *Buffer, + ULONG N, ULONG *Count) { - return romvec->get_vdirent(fd, ent, num, cnt); + return ARC_CALL4(get_vdirent, FileID, Buffer, N, Count); } -long __init prom_open(char *name, enum linux_omode md, unsigned long *fd) +LONG __init +ArcOpen(CHAR *Path, enum linux_omode OpenMode, ULONG *FileID) { - return romvec->open(name, md, fd); + return ARC_CALL3(open, Path, OpenMode, FileID); } -long __init prom_close(unsigned long fd) +LONG __init +ArcClose(ULONG FileID) { - return romvec->close(fd); + return ARC_CALL1(close, FileID); } -long __init prom_read(unsigned long fd, void *buf, unsigned long num, unsigned long *cnt) +LONG __init +ArcRead(ULONG FileID, VOID *Buffer, ULONG N, ULONG *Count) { - return romvec->read(fd, buf, num, cnt); + return ARC_CALL4(read, FileID, Buffer, N, Count); } -long __init prom_getrstatus(unsigned long fd) +LONG __init +ArcGetReadStatus(ULONG FileID) { - return romvec->get_rstatus(fd); + return ARC_CALL1(get_rstatus, FileID); } -long __init prom_write(unsigned long fd, void *buf, unsigned long num, unsigned long *cnt) +LONG __init +ArcWrite(ULONG FileID, PVOID Buffer, ULONG N, PULONG Count) { - return romvec->write(fd, buf, num, cnt); + return ARC_CALL4(write, FileID, Buffer, N, Count); } -long __init prom_seek(unsigned long fd, struct linux_bigint *off, enum linux_seekmode sm) +LONG __init +ArcSeek(ULONG FileID, struct linux_bigint *Position, enum linux_seekmode SeekMode) { - return romvec->seek(fd, off, sm); + return ARC_CALL3(seek, FileID, Position, SeekMode); } -long __init prom_mount(char *name, enum linux_mountops op) +LONG __init +ArcMount(char *name, enum linux_mountops op) { - return romvec->mount(name, op); + return ARC_CALL2(mount, name, op); } -long __init prom_getfinfo(unsigned long fd, struct linux_finfo *buf) +LONG __init +ArcGetFileInformation(ULONG FileID, struct linux_finfo *Information) { - return romvec->get_finfo(fd, buf); + return ARC_CALL2(get_finfo, FileID, Information); } -long __init prom_setfinfo(unsigned long fd, unsigned long flags, unsigned long msk) +LONG __init ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags, + ULONG AttributeMask) { - return romvec->set_finfo(fd, flags, msk); + return ARC_CALL3(set_finfo, FileID, AttributeFlags, AttributeMask); } --- linux-2.5.73/arch/mips/arc/identify.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/arc/identify.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,65 +1,117 @@ /* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * identify.c: identify machine by looking up system identifier * * Copyright (C) 1998 Thomas Bogendoerfer - * + * * This code is based on arch/mips/sgi/kernel/system.c, which is - * + * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) */ +#include #include #include #include #include -#include #include #include struct smatch { - char *name; + char *arcname; + char *liname; int group; int type; int flags; }; static struct smatch mach_table[] = { - {"SGI-IP22", MACH_GROUP_SGI, MACH_SGI_INDY, PROM_FLAG_ARCS}, - {"Microsoft-Jazz", MACH_GROUP_JAZZ, MACH_MIPS_MAGNUM_4000, 0}, - {"PICA-61", MACH_GROUP_JAZZ, MACH_ACER_PICA_61, 0}, - {"RM200PCI", MACH_GROUP_SNI_RM, MACH_SNI_RM200_PCI, 0} + { "SGI-IP22", + "SGI Indy", + MACH_GROUP_SGI, + MACH_SGI_IP22, + PROM_FLAG_ARCS + }, { "SGI-IP27", + "SGI Origin", + MACH_GROUP_SGI, + MACH_SGI_IP27, + PROM_FLAG_ARCS + }, { "SGI-IP28", + "SGI IP28", + MACH_GROUP_SGI, + MACH_SGI_IP28, + PROM_FLAG_ARCS + }, { "SGI-IP32", + "SGI IP32", + MACH_GROUP_SGI, + MACH_SGI_IP32, + PROM_FLAG_ARCS + }, { "Microsoft-Jazz", + "Jazz MIPS_Magnum_4000", + MACH_GROUP_JAZZ, + MACH_MIPS_MAGNUM_4000, + 0 + }, { "PICA-61", + "Jazz Acer_PICA_61", + MACH_GROUP_JAZZ, + MACH_ACER_PICA_61, + 0 + }, { "RM200PCI", + "SNI RM200_PCI", + MACH_GROUP_SNI_RM, + MACH_SNI_RM200_PCI, + 0 + } }; int prom_flags; -static struct smatch *__init string_to_mach(char *s) +static struct smatch * __init string_to_mach(const char *s) { int i; for (i = 0; i < (sizeof(mach_table) / sizeof (mach_table[0])); i++) { - if (!strcmp(s, mach_table[i].name)) + if (!strcmp(s, mach_table[i].arcname)) return &mach_table[i]; } - prom_printf("\nYeee, could not determine architecture type <%s>\n", - s); - prom_printf("press a key to reboot\n"); - prom_getchar(); - romvec->imode(); - return NULL; + + panic("Yeee, could not determine architecture type <%s>", s); +} + +char *system_type; + +const char *get_system_type(void) +{ + return system_type; } void __init prom_identify_arch(void) { pcomponent *p; struct smatch *mach; + const char *iname; /* - * The root component tells us what machine architecture we - * have here. + * The root component tells us what machine architecture we have here. */ - p = prom_getchild(PROM_NULL_COMPONENT); - printk("ARCH: %s\n", p->iname); - mach = string_to_mach(p->iname); + p = ArcGetChild(PROM_NULL_COMPONENT); + if (p == NULL) { +#ifdef CONFIG_SGI_IP27 + /* IP27 PROM misbehaves, seems to not implement ARC + GetChild(). So we just assume it's an IP27. */ + iname = "SGI-IP27"; +#else + iname = "Unknown"; +#endif + } else + iname = (char *) (long) p->iname; + + printk("ARCH: %s\n", iname); + mach = string_to_mach(iname); + system_type = mach->liname; mips_machgroup = mach->group; mips_machtype = mach->type; --- linux-2.5.73/arch/mips/arc/init.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/arc/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,5 +1,5 @@ /* - * This file is subject to the terms and conditions of the GNU General Public+ + * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * @@ -16,38 +16,17 @@ /* Master romvec interface. */ struct linux_romvec *romvec; -struct linux_promblock *sgi_pblock; int prom_argc; -char **prom_argv, **prom_envp; -unsigned short prom_vers, prom_rev; - -extern void prom_testtree(void); - -extern void arc_setup_console(void); +LONG *_prom_argv, *_prom_envp; void __init prom_init(int argc, char **argv, char **envp, int *prom_vec) { - struct linux_promblock *pb; - + PSYSTEM_PARAMETER_BLOCK pb = PROMBLOCK; romvec = ROMVECTOR; - pb = sgi_pblock = PROMBLOCK; prom_argc = argc; - prom_argv = argv; - prom_envp = envp; - -#if 0 - /* arc_printf should not use prom_printf as soon as we free - * the prom buffers - This horribly breaks on Indys with framebuffer - * as it simply stops after initialising swap - On the Indigo2 serial - * console you will get A LOT illegal instructions - Only enable - * this for early init crashes - This also brings up artefacts of - * printing everything twice on serial console and on GFX Console - * this has the effect of having the prom printing everything - * in the small rectangle and the kernel printing around. - */ + _prom_argv = (LONG *) argv; + _prom_envp = (LONG *) envp; - arc_setup_console(); -#endif if (pb->magic != 0x53435241) { prom_printf("Aieee, bad prom vector magic %08lx\n", pb->magic); while(1) @@ -55,19 +34,14 @@ void __init prom_init(int argc, char **a } prom_init_cmdline(); - - prom_vers = pb->ver; - prom_rev = pb->rev; prom_identify_arch(); - printk("PROMLIB: ARC firmware Version %d Revision %d\n", - prom_vers, prom_rev); + printk(KERN_INFO "PROMLIB: ARC firmware Version %d Revision %d\n", + pb->ver, pb->rev); prom_meminit(); #ifdef DEBUG_PROM_INIT - { - prom_printf("Press a key to reboot\n"); - (void) prom_getchar(); - romvec->imode(); - } + prom_printf("Press a key to reboot\n"); + prom_getchar(); + ArcEnterInteractiveMode(); #endif } --- linux-2.5.73/arch/mips/arc/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/arc/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -1,9 +1,10 @@ # -# Makefile for the SGI arcs prom monitor library routines -# under Linux. +# Makefile for the ARC prom monitor library routines under Linux. # -lib-y += console.o init.o memory.o tree.o env.o cmdline.o misc.o \ - time.o file.o identify.o +lib-y += cmdline.o env.o file.o identify.o init.o \ + misc.o time.o tree.o -lib-$(CONFIG_ARC_CONSOLE) += arc_con.o +lib-$(CONFIG_ARC_MEMORY) += memory.o +lib-$(CONFIG_ARC_CONSOLE) += arc_con.o +lib-$(CONFIG_ARC_PROMLIB) += promlib.o --- linux-2.5.73/arch/mips/arc/memory.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/arc/memory.c 2003-06-27 15:56:23.000000000 -0700 @@ -2,7 +2,14 @@ * memory.c: PROM library functions for acquiring/using memory descriptors * given to us from the ARCS firmware. * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1996 by David S. Miller + * Copyright (C) 1999, 2000, 2001 by Ralf Baechle + * Copyright (C) 1999, 2000 by Silicon Graphics, Inc. + * + * PROM library functions for acquiring/using memory descriptors given to us + * from the ARCS firmware. This is only used when CONFIG_ARC_MEMORY is set + * because on some machines like SGI IP27 the ARC memory configuration data + * completly bogus and alternate easier to use mechanisms are available. */ #include #include @@ -19,10 +26,9 @@ #undef DEBUG -struct linux_mdesc * __init -ArcGetMemoryDescriptor(struct linux_mdesc *Current) +struct linux_mdesc * __init ArcGetMemoryDescriptor(struct linux_mdesc *Current) { - return romvec->get_mdesc(Current); + return (struct linux_mdesc *) ARC_CALL1(get_mdesc, Current); } #ifdef DEBUG /* convenient for debugging */ @@ -47,7 +53,8 @@ static char *arc_mtypes[8] = { "FirmwarePermanent", "FreeContiguous" }; -#define mtypes(a) (prom_flags & PROM_FLAG_ARCS) ? arcs_mtypes[a.arcs] : arc_mtypes[a.arc] +#define mtypes(a) (prom_flags & PROM_FLAG_ARCS) ? arcs_mtypes[a.arcs] \ + : arc_mtypes[a.arc] #endif static inline int memtype_classify_arcs (union linux_memtypes type) @@ -92,7 +99,7 @@ static inline int memtype_classify_arc ( static int __init prom_memtype_classify (union linux_memtypes type) { - if (prom_flags & PROM_FLAG_ARCS) /* SGI is ``different'' ... */ + if (prom_flags & PROM_FLAG_ARCS) /* SGI is ``different'' ... */ return memtype_classify_arcs(type); return memtype_classify_arc(type); @@ -128,8 +135,7 @@ void __init prom_meminit(void) } } -void __init -prom_free_prom_memory (void) +void __init prom_free_prom_memory (void) { unsigned long freed = 0; unsigned long addr; @@ -149,5 +155,5 @@ prom_free_prom_memory (void) freed += PAGE_SIZE; } } - printk("Freeing prom memory: %ldkb freed\n", freed >> 10); + printk(KERN_INFO "Freeing prom memory: %ldkb freed\n", freed >> 10); } --- linux-2.5.73/arch/mips/arc/misc.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/arc/misc.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,13 +1,21 @@ /* - * misc.c: Miscellaneous ARCS PROM routines. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Miscellaneous ARCS PROM routines. * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999 Silicon Graphics, Inc. */ #include #include #include #include + +#include #include #include #include @@ -15,68 +23,81 @@ extern void *sgiwd93_host; extern void reset_wd33c93(void *instance); -void prom_halt(void) +VOID +ArcHalt(VOID) { bc_disable(); - cli(); + local_irq_disable(); #ifdef CONFIG_SCSI_SGIWD93 reset_wd33c93(sgiwd93_host); #endif - romvec->halt(); + ARC_CALL0(halt); +never: goto never; } -void prom_powerdown(void) +VOID +ArcPowerDown(VOID) { bc_disable(); - cli(); + local_irq_disable(); #ifdef CONFIG_SCSI_SGIWD93 reset_wd33c93(sgiwd93_host); #endif - romvec->pdown(); + ARC_CALL0(pdown); +never: goto never; } /* XXX is this a soft reset basically? XXX */ -void prom_restart(void) +VOID +ArcRestart(VOID) { bc_disable(); - cli(); + local_irq_disable(); #ifdef CONFIG_SCSI_SGIWD93 reset_wd33c93(sgiwd93_host); #endif - romvec->restart(); + ARC_CALL0(restart); +never: goto never; } -void prom_reboot(void) +VOID +ArcReboot(VOID) { bc_disable(); - cli(); + local_irq_disable(); #ifdef CONFIG_SCSI_SGIWD93 reset_wd33c93(sgiwd93_host); #endif - romvec->reboot(); + ARC_CALL0(reboot); +never: goto never; } -void ArcEnterInteractiveMode(void) +VOID +ArcEnterInteractiveMode(VOID) { bc_disable(); - cli(); + local_irq_disable(); #ifdef CONFIG_SCSI_SGIWD93 reset_wd33c93(sgiwd93_host); #endif - romvec->imode(); + ARC_CALL0(imode); +never: goto never; } -long prom_cfgsave(void) +LONG +ArcSaveConfiguration(VOID) { - return romvec->cfg_save(); + return ARC_CALL0(cfg_save); } -struct linux_sysid *prom_getsysid(void) +struct linux_sysid * +ArcGetSystemId(VOID) { - return romvec->get_sysid(); + return (struct linux_sysid *) ARC_CALL0(get_sysid); } -void __init prom_cacheflush(void) +VOID __init +ArcFlushAllCaches(VOID) { - romvec->cache_flush(); + ARC_CALL0(cache_flush); } --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/arc/promlib.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,43 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 David S. Miller (dm@sgi.com) + * Compability with board caches, Ulf Carlsson + */ +#include +#include +#include + +/* + * IP22 boardcache is not compatible with board caches. Thus we disable it + * during romvec action. Since r4xx0.c is always compiled and linked with your + * kernel, this shouldn't cause any harm regardless what MIPS processor you + * have. + * + * The ARC write and read functions seem to interfere with the serial lines + * in some way. You should be careful with them. + */ + +void prom_putchar(char c) +{ + ULONG cnt; + CHAR it = c; + + bc_disable(); + ArcWrite(1, &it, 1, &cnt); + bc_enable(); +} + +char prom_getchar(void) +{ + ULONG cnt; + CHAR c; + + bc_disable(); + ArcRead(0, &c, 1, &cnt); + bc_enable(); + + return c; +} --- linux-2.5.73/arch/mips/arc/salone.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/arc/salone.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,25 +1,24 @@ /* - * salone.c: Routines to load into memory and execute stand-along - * program images using ARCS PROM firmware. + * Routines to load into memory and execute stand-along program images using + * ARCS PROM firmware. * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * - * $Id: salone.c,v 1.1 1998/10/18 13:32:09 tsbogend Exp $ */ #include #include -long __init prom_load(char *name, unsigned long end, unsigned long *pc, unsigned long *eaddr) +LONG __init ArcLoad(CHAR *Path, ULONG TopAddr, ULONG *ExecAddr, ULONG *LowAddr) { - return romvec->load(name, end, pc, eaddr); + return ARC_CALL4(load, Path, TopAddr, ExecAddr, LowAddr); } -long __init prom_invoke(unsigned long pc, unsigned long sp, long argc, char **argv, char **envp) +LONG __init ArcInvoke(ULONG ExecAddr, ULONG StackAddr, ULONG Argc, CHAR *Argv[], + CHAR *Envp[]) { - return romvec->invoke(pc, sp, argc, argv, envp); + return ARC_CALL5(invoke, ExecAddr, StackAddr, Argc, Argv, Envp); } -long __init prom_exec(char *name, long argc, char **argv, char **envp) +LONG __init ArcExecute(CHAR *Path, LONG Argc, CHAR *Argv[], CHAR *Envp[]) { - return romvec->exec(name, argc, argv, envp); + return ARC_CALL4(exec, Path, Argc, Argv, Envp); } --- linux-2.5.73/arch/mips/arc/time.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/arc/time.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,19 +1,25 @@ /* - * time.c: Extracting time information from ARCS prom. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Extracting time information from ARCS prom. * - * $Id: time.c,v 1.1 1998/10/18 13:32:10 tsbogend Exp $ + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) */ #include + +#include #include -struct linux_tinfo * __init prom_gettinfo(void) +struct linux_tinfo * __init +ArcGetTime(VOID) { - return romvec->get_tinfo(); + return (struct linux_tinfo *) ARC_CALL0(get_tinfo); } -unsigned long __init prom_getrtime(void) +ULONG __init +ArcGetRelativeTime(VOID) { - return romvec->get_rtime(); + return ARC_CALL0(get_rtime); } --- linux-2.5.73/arch/mips/arc/tree.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/arc/tree.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,72 +1,88 @@ /* - * tree.c: PROM component device tree code. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * PROM component device tree code. * - * $Id: tree.c,v 1.1 1998/10/18 13:32:10 tsbogend Exp $ + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999 Silicon Graphics, Inc. */ #include +#include #include -#define DEBUG_PROM_TREE +#undef DEBUG_PROM_TREE -pcomponent * __init prom_getsibling(pcomponent *this) +pcomponent * __init +ArcGetPeer(pcomponent *Current) { - if(this == PROM_NULL_COMPONENT) + if (Current == PROM_NULL_COMPONENT) return PROM_NULL_COMPONENT; - return romvec->next_component(this); + + return (pcomponent *) ARC_CALL1(next_component, Current); } -pcomponent * __init prom_getchild(pcomponent *this) +pcomponent * __init +ArcGetChild(pcomponent *Current) { - return romvec->child_component(this); + return (pcomponent *) ARC_CALL1(child_component, Current); } -pcomponent * __init prom_getparent(pcomponent *child) +pcomponent * __init +ArcGetParent(pcomponent *Current) { - if(child == PROM_NULL_COMPONENT) + if (Current == PROM_NULL_COMPONENT) return PROM_NULL_COMPONENT; - return romvec->parent_component(child); + + return (pcomponent *) ARC_CALL1(parent_component, Current); } -long __init prom_getcdata(void *buffer, pcomponent *this) +LONG __init +ArcGetConfigurationData(VOID *Buffer, pcomponent *Current) { - return romvec->component_data(buffer, this); + return ARC_CALL2(component_data, Buffer, Current); } -pcomponent * __init prom_childadd(pcomponent *this, pcomponent *tmp, void *data) +pcomponent * __init +ArcAddChild(pcomponent *Current, pcomponent *Template, VOID *ConfigurationData) { - return romvec->child_add(this, tmp, data); + return (pcomponent *) + ARC_CALL3(child_add, Current, Template, ConfigurationData); } -long __init prom_delcomponent(pcomponent *this) +LONG __init +ArcDeleteComponent(pcomponent *ComponentToDelete) { - return romvec->comp_del(this); + return ARC_CALL1(comp_del, ComponentToDelete); } -pcomponent * __init prom_componentbypath(char *path) +pcomponent * __init +ArcGetComponent(CHAR *Path) { - return romvec->component_by_path(path); + return (pcomponent *)ARC_CALL1(component_by_path, Path); } #ifdef DEBUG_PROM_TREE + static char *classes[] = { "system", "processor", "cache", "adapter", "controller", "peripheral", "memory" }; static char *types[] = { - "arc", "cpu", "fpu", "picache", "pdcache", "sicache", "sdcache", "sccache", - "memdev", "eisa adapter", "tc adapter", "scsi adapter", "dti adapter", - "multi-func adapter", "disk controller", "tp controller", - "cdrom controller", "worm controller", "serial controller", - "net controller", "display controller", "parallel controller", - "pointer controller", "keyboard controller", "audio controller", - "misc controller", "disk peripheral", "floppy peripheral", - "tp peripheral", "modem peripheral", "monitor peripheral", - "printer peripheral", "pointer peripheral", "keyboard peripheral", - "terminal peripheral", "line peripheral", "net peripheral", - "misc peripheral", "anonymous" + "arc", "cpu", "fpu", "picache", "pdcache", "sicache", "sdcache", + "sccache", "memdev", "eisa adapter", "tc adapter", "scsi adapter", + "dti adapter", "multi-func adapter", "disk controller", + "tp controller", "cdrom controller", "worm controller", + "serial controller", "net controller", "display controller", + "parallel controller", "pointer controller", "keyboard controller", + "audio controller", "misc controller", "disk peripheral", + "floppy peripheral", "tp peripheral", "modem peripheral", + "monitor peripheral", "printer peripheral", "pointer peripheral", + "keyboard peripheral", "terminal peripheral", "line peripheral", + "net peripheral", "misc peripheral", "anonymous" }; static char *iflags[] = { @@ -74,7 +90,8 @@ static char *iflags[] = { "input", "output" }; -static void __init dump_component(pcomponent *p) +static void __init +dump_component(pcomponent *p) { prom_printf("[%p]:class<%s>type<%s>flags<%s>ver<%d>rev<%d>", p, classes[p->class], types[p->type], @@ -83,27 +100,28 @@ static void __init dump_component(pcompo p->key, p->amask, (int)p->cdsize, (int)p->ilen, p->iname); } -static void __init traverse(pcomponent *p, int op) +static void __init +traverse(pcomponent *p, int op) { dump_component(p); - if(prom_getchild(p)) - traverse(prom_getchild(p), 1); - if(prom_getsibling(p) && op) - traverse(prom_getsibling(p), 1); + if(ArcGetChild(p)) + traverse(ArcGetChild(p), 1); + if(ArcGetPeer(p) && op) + traverse(ArcGetPeer(p), 1); } -void __init prom_testtree(void) +void __init +prom_testtree(void) { pcomponent *p; - p = prom_getchild(PROM_NULL_COMPONENT); + p = ArcGetChild(PROM_NULL_COMPONENT); dump_component(p); - p = prom_getchild(p); + p = ArcGetChild(p); while(p) { dump_component(p); - p = prom_getsibling(p); + p = ArcGetPeer(p); } - prom_printf("press a key\n"); - prom_getchar(); } -#endif + +#endif /* DEBUG_PROM_TREE */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/au1000/common/clocks.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,97 @@ +/* + * BRIEF MODULE DESCRIPTION + * Simple Au1000 clocks routines. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +static unsigned int au1x00_clock; // Hz +static unsigned int lcd_clock; // KHz +static unsigned long uart_baud_base; + +/* + * Set the au1000_clock + */ +void set_au1x00_speed(unsigned int new_freq) +{ + au1x00_clock = new_freq; +} + +unsigned int get_au1x00_speed(void) +{ + return au1x00_clock; +} + + + +/* + * The UART baud base is not known at compile time ... if + * we want to be able to use the same code on different + * speed CPUs. + */ +unsigned long get_au1x00_uart_baud_base(void) +{ + return uart_baud_base; +} + +void set_au1x00_uart_baud_base(unsigned long new_baud_base) +{ + uart_baud_base = new_baud_base; +} + +/* + * Calculate the Au1x00's LCD clock based on the current + * cpu clock and the system bus clock, and try to keep it + * below 40 MHz (the Pb1000 board can lock-up if the LCD + * clock is over 40 MHz). + */ +void set_au1x00_lcd_clock(void) +{ + unsigned int static_cfg0; + unsigned int sys_busclk = + (get_au1x00_speed()/1000) / + ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2); + + static_cfg0 = au_readl(MEM_STCFG0); + + if (static_cfg0 & (1<<11)) + lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */ + else + lcd_clock = sys_busclk / 4; + + if (lcd_clock > 50000) /* Epson MAX */ + printk("%s: warning: LCD clock too high (%d KHz)\n", + __FUNCTION__, lcd_clock); +} + +unsigned int get_au1x00_lcd_clock(void) +{ + return lcd_clock; +} + +EXPORT_SYMBOL(get_au1x00_lcd_clock); --- linux-2.5.73/arch/mips/au1000/common/dbg_io.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/au1000/common/dbg_io.c 2003-06-27 15:56:23.000000000 -0700 @@ -3,13 +3,13 @@ #include #include -#ifdef CONFIG_REMOTE_DEBUG +#ifdef CONFIG_KGDB /* * FIXME the user should be able to select the * uart to be used for debugging. */ -#define DEBUG_BASE UART2_ADDR +#define DEBUG_BASE UART_DEBUG_BASE /**/ /* we need uint32 uint8 */ @@ -53,8 +53,11 @@ typedef unsigned int uint32; #define UART_MOD_CNTRL 0x100 /* Module Control */ /* memory-mapped read/write of the port */ -#define UART16550_READ(y) (inl(DEBUG_BASE + y) & 0xff) -#define UART16550_WRITE(y,z) (outl(z&0xff, DEBUG_BASE + y)) +#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff) +#define UART16550_WRITE(y,z) (au_writel(z&0xff, DEBUG_BASE + y)) + +extern unsigned long get_au1x00_uart_baud_base(void); +extern unsigned long cal_r4koff(void); void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) { @@ -68,16 +71,16 @@ void debugInit(uint32 baud, uint8 data, UART16550_WRITE(UART_IER, 0); /* set up baud rate */ - { + { uint32 divisor; /* set divisor */ - divisor = get_au1000_uart_baud() / baud; + divisor = get_au1x00_uart_baud_base() / baud; UART16550_WRITE(UART_CLK, divisor & 0xffff); } /* set data format */ - UART16550_WRITE(UART_LCR, data | parity | stop); + UART16550_WRITE(UART_LCR, (data | parity | stop)); } static int remoteDebugInitialized = 0; @@ -99,7 +102,8 @@ uint8 getDebugChar(void) int putDebugChar(uint8 byte) { - int i; +// int i; + if (!remoteDebugInitialized) { remoteDebugInitialized = 1; debugInit(UART16550_BAUD_115200, --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/au1000/common/dma.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,217 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * A DMA channel allocator for Au1000. API is modeled loosely off of + * linux/kernel/dma.c. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * stevel@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + + +/* + * A note on resource allocation: + * + * All drivers needing DMA channels, should allocate and release them + * through the public routines `request_dma()' and `free_dma()'. + * + * In order to avoid problems, all processes should allocate resources in + * the same sequence and release them in the reverse order. + * + * So, when allocating DMAs and IRQs, first allocate the DMA, then the IRQ. + * When releasing them, first release the IRQ, then release the DMA. The + * main reason for this order is that, if you are requesting the DMA buffer + * done interrupt, you won't know the irq number until the DMA channel is + * returned from request_dma. + */ + + +spinlock_t au1000_dma_spin_lock = SPIN_LOCK_UNLOCKED; + +struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = { + {dev_id:-1,}, + {dev_id:-1,}, + {dev_id:-1,}, + {dev_id:-1,}, + {dev_id:-1,}, + {dev_id:-1,}, + {dev_id:-1,}, + {dev_id:-1,} +}; + +// Device FIFO addresses and default DMA modes +static const struct { + unsigned int fifo_addr; + unsigned int dma_mode; +} dma_dev_table[DMA_NUM_DEV] = { + {UART0_ADDR + UART_TX, 0}, + {UART0_ADDR + UART_RX, 0}, + {0, 0}, + {0, 0}, + {AC97C_DATA, DMA_DW16 }, // coherent + {AC97C_DATA, DMA_DR | DMA_DW16 }, // coherent + {UART3_ADDR + UART_TX, DMA_DW8 | DMA_NC}, + {UART3_ADDR + UART_RX, DMA_DR | DMA_DW8 | DMA_NC}, + {USBD_EP0RD, DMA_DR | DMA_DW8 | DMA_NC}, + {USBD_EP0WR, DMA_DW8 | DMA_NC}, + {USBD_EP2WR, DMA_DW8 | DMA_NC}, + {USBD_EP3WR, DMA_DW8 | DMA_NC}, + {USBD_EP4RD, DMA_DR | DMA_DW8 | DMA_NC}, + {USBD_EP5RD, DMA_DR | DMA_DW8 | DMA_NC}, + {I2S_DATA, DMA_DW32 | DMA_NC}, + {I2S_DATA, DMA_DR | DMA_DW32 | DMA_NC} +}; + + +int au1000_dma_read_proc(char *buf, char **start, off_t fpos, + int length, int *eof, void *data) +{ + int i, len = 0; + struct dma_chan *chan; + + for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) { + if ((chan = get_dma_chan(i)) != NULL) { + len += sprintf(buf + len, "%2d: %s\n", + i, chan->dev_str); + } + } + + if (fpos >= len) { + *start = buf; + *eof = 1; + return 0; + } + *start = buf + fpos; + if ((len -= fpos) > length) + return length; + *eof = 1; + return len; +} + + +void dump_au1000_dma_channel(unsigned int dmanr) +{ + struct dma_chan *chan; + + if (dmanr > NUM_AU1000_DMA_CHANNELS) + return; + chan = &au1000_dma_table[dmanr]; + + printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr); + printk(KERN_INFO " mode = 0x%08x\n", + au_readl(chan->io + DMA_MODE_SET)); + printk(KERN_INFO " addr = 0x%08x\n", + au_readl(chan->io + DMA_PERIPHERAL_ADDR)); + printk(KERN_INFO " start0 = 0x%08x\n", + au_readl(chan->io + DMA_BUFFER0_START)); + printk(KERN_INFO " start1 = 0x%08x\n", + au_readl(chan->io + DMA_BUFFER1_START)); + printk(KERN_INFO " count0 = 0x%08x\n", + au_readl(chan->io + DMA_BUFFER0_COUNT)); + printk(KERN_INFO " count1 = 0x%08x\n", + au_readl(chan->io + DMA_BUFFER1_COUNT)); +} + + +/* + * Finds a free channel, and binds the requested device to it. + * Returns the allocated channel number, or negative on error. + * Requests the DMA done IRQ if irqhandler != NULL. + */ +int request_au1000_dma(int dev_id, const char *dev_str, + void (*irqhandler)(int, void *, struct pt_regs *), + unsigned long irqflags, + void *irq_dev_id) +{ + struct dma_chan *chan; + int i, ret; + + if (dev_id < 0 || dev_id >= DMA_NUM_DEV) + return -EINVAL; + + for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) { + if (au1000_dma_table[i].dev_id < 0) + break; + } + if (i == NUM_AU1000_DMA_CHANNELS) + return -ENODEV; + + chan = &au1000_dma_table[i]; + + if (irqhandler) { + chan->irq = AU1000_DMA_INT_BASE + i; + chan->irq_dev = irq_dev_id; + if ((ret = request_irq(chan->irq, irqhandler, irqflags, + dev_str, chan->irq_dev))) { + chan->irq = 0; + chan->irq_dev = NULL; + return ret; + } + } else { + chan->irq = 0; + chan->irq_dev = NULL; + } + + // fill it in + chan->io = DMA_CHANNEL_BASE + i * DMA_CHANNEL_LEN; + chan->dev_id = dev_id; + chan->dev_str = dev_str; + chan->fifo_addr = dma_dev_table[dev_id].fifo_addr; + chan->mode = dma_dev_table[dev_id].dma_mode; + + /* initialize the channel before returning */ + init_dma(i); + + return i; +} + + +void free_au1000_dma(unsigned int dmanr) +{ + struct dma_chan *chan = get_dma_chan(dmanr); + if (!chan) { + printk("Trying to free DMA%d\n", dmanr); + return; + } + + disable_dma(dmanr); + if (chan->irq) + free_irq(chan->irq, chan->irq_dev); + + chan->irq = 0; + chan->irq_dev = NULL; + chan->dev_id = -1; +} --- linux-2.5.73/arch/mips/au1000/common/int-handler.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/au1000/common/int-handler.S 2003-06-27 15:56:23.000000000 -0700 @@ -9,7 +9,6 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ -#include #include #include #include @@ -40,32 +39,30 @@ NESTED(au1000_IRQ, PT_SIZE, sp) 1: andi a0, t0, CAUSEF_IP2 # Interrupt Controller 0, Request 0 - beq a0, zero, 2f - move a0,sp + beq a0, zero, 2f + move a0,sp jal intc0_req0_irqdispatch j ret_from_irq 2: andi a0, t0, CAUSEF_IP3 # Interrupt Controller 0, Request 1 - beq a0, zero, 3f - move a0,sp + beq a0, zero, 3f + move a0,sp jal intc0_req1_irqdispatch j ret_from_irq 3: andi a0, t0, CAUSEF_IP4 # Interrupt Controller 1, Request 0 - beq a0, zero, 4f - move a0,sp + beq a0, zero, 4f + move a0,sp jal intc1_req0_irqdispatch j ret_from_irq 4: andi a0, t0, CAUSEF_IP5 # Interrupt Controller 1, Request 1 - beq a0, zero, 5f - move a0, sp + beq a0, zero, 5f + move a0, sp jal intc1_req1_irqdispatch j ret_from_irq -5: +5: move a0, sp - jal mips_spurious_interrupt -done: - j ret_from_irq + j spurious_interrupt END(au1000_IRQ) --- linux-2.5.73/arch/mips/au1000/common/irq.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/au1000/common/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -28,6 +28,7 @@ */ #include #include +#include #include #include #include @@ -47,7 +48,21 @@ #include #include -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) +#if defined(CONFIG_MIPS_PB1000) +#include +#elif defined(CONFIG_MIPS_PB1500) +#include +#elif defined(CONFIG_MIPS_PB1100) +#include +#elif defined(CONFIG_MIPS_DB1000) +#include +#elif defined(CONFIG_MIPS_DB1100) +#include +#elif defined(CONFIG_MIPS_DB1500) +#include +#else +#error unsupported Alchemy board +#endif #undef DEBUG_IRQ #ifdef DEBUG_IRQ @@ -63,16 +78,13 @@ #define EXT_INTC1_REQ1 5 /* IP 5 */ #define MIPS_TIMER_IP 7 /* IP 7 */ -#ifdef CONFIG_REMOTE_DEBUG +#ifdef CONFIG_KGDB extern void breakpoint(void); #endif extern asmlinkage void au1000_IRQ(void); - extern void set_debug_traps(void); -extern irq_cpustat_t irq_stat []; -extern irq_desc_t irq_desc[NR_IRQS]; - +extern irq_cpustat_t irq_stat [NR_CPUS]; unsigned int local_bh_count[NR_CPUS]; unsigned int local_irq_count[NR_CPUS]; @@ -82,154 +94,113 @@ static void end_irq(unsigned int irq_nr) static inline void mask_and_ack_level_irq(unsigned int irq_nr); static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr); static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr); -static inline void local_enable_irq(unsigned int irq_nr); -static inline void local_disable_irq(unsigned int irq_nr); +inline void local_enable_irq(unsigned int irq_nr); +inline void local_disable_irq(unsigned int irq_nr); -unsigned long spurious_interrupts; -extern unsigned int do_IRQ(int irq, struct pt_regs *regs); extern void __init init_generic_irq(void); -static inline void sync(void) -{ - __asm volatile ("sync"); -} - - -/* Function for careful CP0 interrupt mask access */ -static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask) -{ - unsigned long status = read_32bit_cp0_register(CP0_STATUS); - status &= ~((clr_mask & 0xFF) << 8); - status |= (set_mask & 0xFF) << 8; - write_32bit_cp0_register(CP0_STATUS, status); -} - - -static inline void mask_cpu_irq_input(unsigned int irq_nr) -{ - modify_cp0_intmask(irq_nr, 0); -} - - -static inline void unmask_cpu_irq_input(unsigned int irq_nr) -{ - modify_cp0_intmask(0, irq_nr); -} - - -static void disable_cpu_irq_input(unsigned int irq_nr) -{ - unsigned long flags; - - save_and_cli(flags); - mask_cpu_irq_input(irq_nr); - restore_flags(flags); -} - - -static void enable_cpu_irq_input(unsigned int irq_nr) -{ - unsigned long flags; - - save_and_cli(flags); - unmask_cpu_irq_input(irq_nr); - restore_flags(flags); -} +#ifdef CONFIG_PM +extern void counter0_irq(int irq, void *dev_id, struct pt_regs *regs); +#endif +static spinlock_t irq_lock = SPIN_LOCK_UNLOCKED; static void setup_local_irq(unsigned int irq_nr, int type, int int_req) { + if (irq_nr > AU1000_MAX_INTR) return; /* Config2[n], Config1[n], Config0[n] */ if (irq_nr > AU1000_LAST_INTC0_INT) { switch (type) { case INTC_INT_RISE_EDGE: /* 0:0:1 */ - outl(1< AU1000_LAST_INTC0_INT) { - outl(1< AU1000_LAST_INTC0_INT) { - outl(1< AU1000_LAST_INTC0_INT) { - outl(1< AU1000_LAST_INTC0_INT) { - outl(1<>= 1; } } @@ -417,55 +548,84 @@ void intc0_req0_irqdispatch(struct pt_re void intc0_req1_irqdispatch(struct pt_regs *regs) { int irq = 0, i; - unsigned long int_request; + static unsigned long intc0_req1 = 0; - int_request = inl(INTC0_REQ1_INT); + intc0_req1 = au_readl(IC0_REQ1INT); - if (!int_request) return; + if (!intc0_req1) return; for (i=0; i<32; i++) { - if ((int_request & 0x1)) { - do_IRQ(irq, regs); + if ((intc0_req1 & (1<>= 1; } } +/* + * Interrupt Controller 1: + * interrupts 32 - 63 + */ void intc1_req0_irqdispatch(struct pt_regs *regs) { int irq = 0, i; - unsigned long int_request; + static unsigned long intc1_req0 = 0; - int_request = inl(INTC1_REQ0_INT); + intc1_req0 |= au_readl(IC1_REQ0INT); - if (!int_request) return; + if (!intc1_req0) return; +#if defined(CONFIG_MIPS_PB1000) && defined(DEBUG_IRQ) + au_writel(1, CPLD_AUX0); /* debug led 0 */ +#endif for (i=0; i<32; i++) { - if ((int_request & 0x1)) { - do_IRQ(irq, regs); + if ((intc1_req0 & (1<>= 1; } +#if defined(CONFIG_MIPS_PB1000) && defined(DEBUG_IRQ) + au_writel(0, CPLD_AUX0); +#endif } void intc1_req1_irqdispatch(struct pt_regs *regs) { int irq = 0, i; - unsigned long int_request; + static unsigned long intc1_req1 = 0; - int_request = inl(INTC1_REQ1_INT); + intc1_req1 |= au_readl(IC1_REQ1INT); - if (!int_request) return; + if (!intc1_req1) return; for (i=0; i<32; i++) { - if ((int_request & 0x1)) { - do_IRQ(irq, regs); + if ((intc1_req1 & (1<>= 1; } } --- linux-2.5.73/arch/mips/au1000/common/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/au1000/common/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -5,14 +5,14 @@ # # Makefile for the Alchemy Au1000 CPU, generic files. # +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# -obj-y := prom.o dbg_io.o int-handler.o irq.o puts.o time.o reset.o - -obj-$(CONFIG_AU1000_UART) += serial.o -obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o -obj-$(CONFIG_BLK_DEV_INITRD) += ramdisk.o - -EXTRA_AFLAGS := $(CFLAGS) +obj-y += prom.o int-handler.o dma.o irq.o puts.o \ + time.o reset.o clocks.o power.o -ramdisk.o: - mkramobj ramdisk ramdisk.o +obj-$(CONFIG_AU1X00_USB_DEVICE) += usbdev.o +obj-$(CONFIG_KGDB) += dbg_io.o +obj-$(CONFIG_RTC) += rtc.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/au1000/common/power.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,332 @@ +/* + * BRIEF MODULE DESCRIPTION + * Au1000 Power Management routines. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * Some of the routines are right out of init/main.c, whose + * copyrights apply here. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define DEBUG 1 +#ifdef DEBUG +# define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args) +#else +# define DPRINTK(fmt, args...) +#endif + +extern void au1k_wait(void); +static void calibrate_delay(void); + +extern void set_au1000_speed(unsigned int new_freq); +extern unsigned int get_au1000_speed(void); +extern unsigned long get_au1000_uart_baud_base(void); +extern void set_au1000_uart_baud_base(unsigned long new_baud_base); +extern unsigned long save_local_and_disable(int controller); +extern void restore_local_and_enable(int controller, unsigned long mask); +extern void local_enable_irq(unsigned int irq_nr); + +/* Quick acpi hack. This will have to change! */ +#define CTL_ACPI 9999 +#define ACPI_S1_SLP_TYP 19 +#define ACPI_SLEEP 21 + +#ifdef CONFIG_PM + +static spinlock_t pm_lock = SPIN_LOCK_UNLOCKED; + +unsigned long suspend_mode; + +void wakeup_from_suspend(void) +{ + suspend_mode = 0; +} + +int au_sleep(void) +{ + unsigned long wakeup, flags; + spin_lock_irqsave(&pm_lock,flags); + + flush_cache_all(); + /* pin 6 is gpio */ + au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD); + + /* gpio 6 can cause a wake up event */ + wakeup = au_readl(SYS_WAKEMSK); + wakeup &= ~(1 << 8); /* turn off match20 wakeup */ + wakeup |= 1 << 6; /* turn on gpio 6 wakeup */ + au_writel(wakeup, SYS_WAKEMSK); + + au_writel(1, SYS_WAKESRC); /* clear cause */ + au_writel(1, SYS_SLPPWR); /* prepare to sleep */ + + __asm__("la $4, 1f\n\t" + "lui $5, 0xb190\n\t" + "ori $5, 0x18\n\t" + "sw $4, 0($5)\n\t" + "li $4, 1\n\t" + "lui $5, 0xb190\n\t" + "ori $5, 0x7c\n\t" + "sw $4, 0($5)\n\t" "sync\n\t" "1:\t\n\t" "nop\n\t"); + + /* after a wakeup, the cpu vectors back to 0x1fc00000 so + * it's up to the boot code to get us back here. + */ + spin_unlock_irqrestore(&pm_lock, flags); + return 0; +} + +static int pm_do_sleep(ctl_table * ctl, int write, struct file *file, + void *buffer, size_t * len) +{ + int retval = 0; + + if (!write) { + *len = 0; + } else { + retval = pm_send_all(PM_SUSPEND, (void *) 2); + if (retval) + return retval; + + au_sleep(); + retval = pm_send_all(PM_RESUME, (void *) 0); + } + return retval; +} + +static int pm_do_suspend(ctl_table * ctl, int write, struct file *file, + void *buffer, size_t * len) +{ + int retval = 0; + + if (!write) { + *len = 0; + } else { + retval = pm_send_all(PM_SUSPEND, (void *) 2); + if (retval) + return retval; + suspend_mode = 1; + au1k_wait(); + retval = pm_send_all(PM_RESUME, (void *) 0); + } + return retval; +} + + +static int pm_do_freq(ctl_table * ctl, int write, struct file *file, + void *buffer, size_t * len) +{ + int retval = 0, i; + unsigned long val, pll; +#define TMPBUFLEN 64 +#define MAX_CPU_FREQ 396 + char buf[8], *p; + unsigned long flags, intc0_mask, intc1_mask; + unsigned long old_baud_base, old_cpu_freq, baud_rate, old_clk, + old_refresh; + unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh; + + spin_lock_irqsave(&pm_lock, flags); + if (!write) { + *len = 0; + } else { + /* Parse the new frequency */ + if (*len > TMPBUFLEN - 1) { + spin_unlock_irqrestore(&pm_lock, flags); + return -EFAULT; + } + if (copy_from_user(buf, buffer, *len)) { + spin_unlock_irqrestore(&pm_lock, flags); + return -EFAULT; + } + buf[*len] = 0; + p = buf; + val = simple_strtoul(p, &p, 0); + if (val > MAX_CPU_FREQ) { + spin_unlock_irqrestore(&pm_lock, flags); + return -EFAULT; + } + + pll = val / 12; + if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */ + /* revisit this for higher speed cpus */ + spin_unlock_irqrestore(&pm_lock, flags); + return -EFAULT; + } + + old_baud_base = get_au1000_uart_baud_base(); + old_cpu_freq = get_au1000_speed(); + + new_cpu_freq = pll * 12 * 1000000; + new_baud_base = (new_cpu_freq / 4) / 16; + set_au1000_speed(new_cpu_freq); + set_au1000_uart_baud_base(new_baud_base); + + old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff; + new_refresh = + ((old_refresh * new_cpu_freq) / + old_cpu_freq) | (au_readl(MEM_SDREFCFG) & ~0x1ffffff); + + au_writel(pll, SYS_CPUPLL); + au_sync_delay(1); + au_writel(new_refresh, MEM_SDREFCFG); + au_sync_delay(1); + + for (i = 0; i < 4; i++) { + if (au_readl + (UART_BASE + UART_MOD_CNTRL + + i * 0x00100000) == 3) { + old_clk = + au_readl(UART_BASE + UART_CLK + + i * 0x00100000); + // baud_rate = baud_base/clk + baud_rate = old_baud_base / old_clk; + /* we won't get an exact baud rate and the error + * could be significant enough that our new + * calculation will result in a clock that will + * give us a baud rate that's too far off from + * what we really want. + */ + if (baud_rate > 100000) + baud_rate = 115200; + else if (baud_rate > 50000) + baud_rate = 57600; + else if (baud_rate > 30000) + baud_rate = 38400; + else if (baud_rate > 17000) + baud_rate = 19200; + else + (baud_rate = 9600); + // new_clk = new_baud_base/baud_rate + new_clk = new_baud_base / baud_rate; + au_writel(new_clk, + UART_BASE + UART_CLK + + i * 0x00100000); + au_sync_delay(10); + } + } + } + + + /* We don't want _any_ interrupts other than + * match20. Otherwise our calibrate_delay() + * calculation will be off, potentially a lot. + */ + intc0_mask = save_local_and_disable(0); + intc1_mask = save_local_and_disable(1); + local_enable_irq(AU1000_TOY_MATCH2_INT); + spin_unlock_irqrestore(&pm_lock, flags); + calibrate_delay(); + restore_local_and_enable(0, intc0_mask); + restore_local_and_enable(1, intc1_mask); + return retval; +} + + +static struct ctl_table pm_table[] = { + {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, &pm_do_suspend}, + {ACPI_SLEEP, "sleep", NULL, 0, 0600, NULL, &pm_do_sleep}, + {CTL_ACPI, "freq", NULL, 0, 0600, NULL, &pm_do_freq}, + {0} +}; + +static struct ctl_table pm_dir_table[] = { + {CTL_ACPI, "pm", NULL, 0, 0555, pm_table}, + {0} +}; + +/* + * Initialize power interface + */ +static int __init pm_init(void) +{ + register_sysctl_table(pm_dir_table, 1); + return 0; +} + +__initcall(pm_init); + + +/* + * This is right out of init/main.c + */ + +/* This is the number of bits of precision for the loops_per_jiffy. Each + bit takes on average 1.5/HZ seconds. This (like the original) is a little + better than 1% */ +#define LPS_PREC 8 + +static void calibrate_delay(void) +{ + unsigned long ticks, loopbit; + int lps_precision = LPS_PREC; + + loops_per_jiffy = (1 << 12); + + while (loops_per_jiffy <<= 1) { + /* wait for "start of" clock tick */ + ticks = jiffies; + while (ticks == jiffies) + /* nothing */ ; + /* Go .. */ + ticks = jiffies; + __delay(loops_per_jiffy); + ticks = jiffies - ticks; + if (ticks) + break; + } + +/* Do a binary approximation to get loops_per_jiffy set to equal one clock + (up to lps_precision bits) */ + loops_per_jiffy >>= 1; + loopbit = loops_per_jiffy; + while (lps_precision-- && (loopbit >>= 1)) { + loops_per_jiffy |= loopbit; + ticks = jiffies; + while (ticks == jiffies); + ticks = jiffies; + __delay(loops_per_jiffy); + if (jiffies != ticks) /* longer than 1 tick */ + loops_per_jiffy &= ~loopbit; + } +} + +void au1k_wait(void) +{ + __asm__("nop\n\t" "nop\n\t"); +} + +#endif /* CONFIG_PM */ --- linux-2.5.73/arch/mips/au1000/common/prom.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/au1000/common/prom.c 2003-06-27 15:56:23.000000000 -0700 @@ -4,11 +4,11 @@ * PROM library initialisation code, assuming a version of * pmon is the boot code. * - * Copyright 2000 MontaVista Software Inc. + * Copyright 2000,2001 MontaVista Software Inc. * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com * - * This file was derived from Carsten Langgaard's + * This file was derived from Carsten Langgaard's * arch/mips/mips-boards/xx files. * * Carsten Langgaard, carstenl@mips.com @@ -35,7 +35,7 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include +#include #include #include #include @@ -44,22 +44,23 @@ /* #define DEBUG_CMDLINE */ -char arcs_cmdline[COMMAND_LINE_SIZE]; -int prom_argc; -char **prom_argv, **prom_envp; +char arcs_cmdline[CL_SIZE]; +extern int prom_argc; +extern char **prom_argv, **prom_envp; -typedef struct { - char *name; -/* char *val; */ -} t_env_var; +typedef struct +{ + char *name; +/* char *val; */ +}t_env_var; -char * __init prom_getcmdline(void) +char * prom_getcmdline(void) { return &(arcs_cmdline[0]); } -void __init prom_init_cmdline(void) +void prom_init_cmdline(void) { char *cp; int actr; @@ -101,20 +102,57 @@ char *prom_getenv(char *envname) return(NULL); } -static inline unsigned char str2hexnum(unsigned char c) +inline unsigned char str2hexnum(unsigned char c) { if(c >= '0' && c <= '9') - return c - '0'; + return c - '0'; if(c >= 'a' && c <= 'f') - return c - 'a' + 10; + return c - 'a' + 10; + if(c >= 'A' && c <= 'F') + return c - 'A' + 10; return 0; /* foo */ } -int __init page_is_ram(unsigned long pagenr) +inline void str2eaddr(unsigned char *ea, unsigned char *str) { - return 1; + int i; + + for(i = 0; i < 6; i++) { + unsigned char num; + + if((*str == '.') || (*str == ':')) + str++; + num = str2hexnum(*str++) << 4; + num |= (str2hexnum(*str++)); + ea[i] = num; + } } -void prom_free_prom_memory (void) +int get_ethernet_addr(char *ethernet_addr) { + char *ethaddr_str; + + ethaddr_str = prom_getenv("ethaddr"); + if (!ethaddr_str) { + printk("ethaddr not set in boot prom\n"); + return -1; + } + str2eaddr(ethernet_addr, ethaddr_str); + +#if 0 + { + int i; + + printk("get_ethernet_addr: "); + for (i=0; i<5; i++) + printk("%02x:", (unsigned char)*(ethernet_addr+i)); + printk("%02x\n", *(ethernet_addr+i)); + } +#endif + + return 0; } + +void prom_free_prom_memory (void) {} +EXPORT_SYMBOL(prom_getcmdline); +EXPORT_SYMBOL(get_ethernet_addr); --- linux-2.5.73/arch/mips/au1000/common/puts.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/au1000/common/puts.c 2003-06-27 15:56:23.000000000 -0700 @@ -29,8 +29,9 @@ */ #include +#include -#define SERIAL_BASE 0xB1100000 /* au1000, uart 0 */ +#define SERIAL_BASE UART_BASE #define SER_CMD 0x7 #define SER_DATA 0x1 #define TX_BUSY 0x20 --- linux-2.5.73/arch/mips/au1000/common/reset.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/au1000/common/reset.c 2003-06-27 15:56:23.000000000 -0700 @@ -27,7 +27,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ - +#include #include #include #include @@ -35,23 +35,107 @@ #include #include #include +#include + +extern int au_sleep(void); void au1000_restart(char *command) { - set_cp0_status(ST0_BEV | ST0_ERL); - set_cp0_config(CONF_CM_UNCACHED); + /* Set all integrated peripherals to disabled states */ + u32 prid = read_c0_prid(); + + printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n"); + switch (prid & 0xFF000000) + { + case 0x00000000: /* Au1000 */ + au_writel(0x02, 0xb0000010); /* ac97_enable */ + au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */ + asm("sync"); + au_writel(0x00, 0xb017fffc); /* usbh_enable */ + au_writel(0x00, 0xb0200058); /* usbd_enable */ + au_writel(0x00, 0xb0300040); /* ir_enable */ + au_writel(0x00, 0xb0520000); /* macen0 */ + au_writel(0x00, 0xb0520004); /* macen1 */ + au_writel(0x00, 0xb1000008); /* i2s_enable */ + au_writel(0x00, 0xb1100100); /* uart0_enable */ + au_writel(0x00, 0xb1200100); /* uart1_enable */ + au_writel(0x00, 0xb1300100); /* uart2_enable */ + au_writel(0x00, 0xb1400100); /* uart3_enable */ + au_writel(0x02, 0xb1600100); /* ssi0_enable */ + au_writel(0x02, 0xb1680100); /* ssi1_enable */ + au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */ + au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */ + au_writel(0x00, 0xb1900028); /* sys_clksrc */ + au_writel(0x00, 0xb1900100); /* sys_pininputen */ + break; + case 0x01000000: /* Au1500 */ + au_writel(0x02, 0xb0000010); /* ac97_enable */ + au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */ + asm("sync"); + au_writel(0x00, 0xb017fffc); /* usbh_enable */ + au_writel(0x00, 0xb0200058); /* usbd_enable */ + au_writel(0x00, 0xb1520000); /* macen0 */ + au_writel(0x00, 0xb1520004); /* macen1 */ + au_writel(0x00, 0xb1100100); /* uart0_enable */ + au_writel(0x00, 0xb1400100); /* uart3_enable */ + au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */ + au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */ + au_writel(0x00, 0xb1900028); /* sys_clksrc */ + au_writel(0x00, 0xb1900100); /* sys_pininputen */ + break; + case 0x02000000: /* Au1100 */ + au_writel(0x02, 0xb0000010); /* ac97_enable */ + au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */ + asm("sync"); + au_writel(0x00, 0xb017fffc); /* usbh_enable */ + au_writel(0x00, 0xb0200058); /* usbd_enable */ + au_writel(0x00, 0xb0300040); /* ir_enable */ + au_writel(0x00, 0xb0520000); /* macen0 */ + au_writel(0x00, 0xb1000008); /* i2s_enable */ + au_writel(0x00, 0xb1100100); /* uart0_enable */ + au_writel(0x00, 0xb1200100); /* uart1_enable */ + au_writel(0x00, 0xb1400100); /* uart3_enable */ + au_writel(0x02, 0xb1600100); /* ssi0_enable */ + au_writel(0x02, 0xb1680100); /* ssi1_enable */ + au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */ + au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */ + au_writel(0x00, 0xb1900028); /* sys_clksrc */ + au_writel(0x00, 0xb1900100); /* sys_pininputen */ + break; + + default: + break; + } + + set_c0_status(ST0_BEV | ST0_ERL); + set_c0_config(CONF_CM_UNCACHED); flush_cache_all(); - write_32bit_cp0_register(CP0_WIRED, 0); + write_c0_wired(0); + +#if defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) + /* Do a HW reset if the board can do it */ + + au_writel(0x00000000, 0xAE00001C); +#endif + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); } void au1000_halt(void) { printk(KERN_NOTICE "\n** You can safely turn off the power\n"); +#ifdef CONFIG_PM + au_sleep(); + + /* should not get here */ + printk(KERN_ERR "Unable to put cpu in sleep mode\n"); + while(1); +#else while (1) __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0"); +#endif } void au1000_power_off(void) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/au1000/common/rtc.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,37 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * RTC routines for PC style attached Dallas chip. + * + * Copyright (C) 1998, 2001 by Ralf Baechle + */ +#include +#include +#include + +#define PB1500_RTC_ADDR 0xAC000000 + +unsigned char std_rtc_read_data(unsigned long offset) +{ + offset <<= 2; + return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff); +} + +static void std_rtc_write_data(unsigned char data, unsigned long offset) +{ + offset <<= 2; + au_writel(data, offset + PB1500_RTC_ADDR); +} + +static int std_rtc_bcd_mode(void) +{ + return 1; +} + +struct rtc_ops pb1500_rtc_ops = { + &std_rtc_read_data, + &std_rtc_write_data, + &std_rtc_bcd_mode +}; --- linux-2.5.73/arch/mips/au1000/common/serial.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,2980 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Au1000 serial port driver. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * Derived almost entirely from drivers/char/serial.c: - * - * Copyright (C) 1991, 1992 Linus Torvalds - * Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, - * 1998, 1999 Theodore Ts'o - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -static char *serial_version = "1.01"; -static char *serial_revdate = "2001-02-08"; - - -#include -#include - -#undef SERIAL_PARANOIA_CHECK -#define CONFIG_SERIAL_NOPAUSE_IO -#define SERIAL_DO_RESTART - - -/* Set of debugging defines */ - -#undef SERIAL_DEBUG_INTR -#undef SERIAL_DEBUG_OPEN -#undef SERIAL_DEBUG_FLOW -#undef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT -#undef SERIAL_DEBUG_PCI -#undef SERIAL_DEBUG_AUTOCONF - -#ifdef MODULE -#undef CONFIG_AU1000_SERIAL_CONSOLE -#endif - -#define CONFIG_SERIAL_RSA - -#define RS_STROBE_TIME (10*HZ) -#define RS_ISR_PASS_LIMIT 256 - -/* - * End of serial driver configuration section. - */ - -#include - -#include -#ifdef LOCAL_HEADERS -#include "serial_local.h" -#else -#include -#include -#include -#include -#define LOCAL_VERSTRING "" -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_AU1000_SERIAL_CONSOLE -#include -#endif -#ifdef CONFIG_MAGIC_SYSRQ -#include -#endif - -#include -#include -#include -#include - -#ifdef CONFIG_MAC_SERIAL -#define SERIAL_DEV_OFFSET 2 -#else -#define SERIAL_DEV_OFFSET 0 -#endif - -#ifdef SERIAL_INLINE -#define _INLINE_ inline -#else -#define _INLINE_ -#endif - -static char *serial_name = "Serial driver"; - -static DECLARE_TASK_QUEUE(tq_serial); - -static struct tty_driver *serial_driver; - -static struct timer_list serial_timer; - -extern unsigned long get_au1000_uart_baud(void); - -/* serial subtype definitions */ -#ifndef SERIAL_TYPE_NORMAL -#define SERIAL_TYPE_NORMAL 1 -#endif - -/* number of characters left in xmit buffer before we ask for more */ -#define WAKEUP_CHARS 256 - -/* - * IRQ_timeout - How long the timeout should be for each IRQ - * should be after the IRQ has been active. - */ - -static struct async_struct *IRQ_ports[NR_IRQS]; -static int IRQ_timeout[NR_IRQS]; -#ifdef CONFIG_AU1000_SERIAL_CONSOLE -static struct console sercons; -static int lsr_break_flag; -#endif -#if defined(CONFIG_AU1000_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) -static unsigned long break_pressed; /* break, really ... */ -#endif - -static void autoconfig(struct serial_state * state); -static void change_speed(struct async_struct *info, struct termios *old); -static void rs_wait_until_sent(struct tty_struct *tty, int timeout); - -/* - * Here we define the default xmit fifo size used for each type of - * UART - */ -static struct serial_uart_config uart_config[] = { - { "unknown", 1, 0 }, - { "8250", 1, 0 }, - { "16450", 1, 0 }, - { "16550", 1, 0 }, - { 0, 0} -}; - - -static struct serial_state rs_table[RS_TABLE_SIZE] = { - SERIAL_PORT_DFNS /* Defined in serial.h */ -}; - -#define NR_PORTS (sizeof(rs_table)/sizeof(struct serial_state)) - -#ifndef PREPARE_FUNC -#define PREPARE_FUNC(dev) (dev->prepare) -#define ACTIVATE_FUNC(dev) (dev->activate) -#define DEACTIVATE_FUNC(dev) (dev->deactivate) -#endif - -#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8) - -#if defined(MODULE) && defined(SERIAL_DEBUG_MCOUNT) -#define DBG_CNT(s) printk("(%s): [%x], refc=%d, serc=%d, ttyc=%d -> %s\n", \ - tty->name, (info->flags), serial_driver->refcount, info->count,tty->count,s) -#else -#define DBG_CNT(s) -#endif - -/* - * tmp_buf is used as a temporary buffer by serial_write. We need to - * lock it in case the copy_from_user blocks while swapping in a page, - * and some other program tries to do a serial write at the same time. - * Since the lock will only come under contention when the system is - * swapping and available memory is low, it makes sense to share one - * buffer across all the serial ports, since it significantly saves - * memory if large numbers of serial ports are open. - */ -static unsigned char *tmp_buf; -#ifdef DECLARE_MUTEX -static DECLARE_MUTEX(tmp_buf_sem); -#else -static struct semaphore tmp_buf_sem = MUTEX; -#endif - - -static inline int serial_paranoia_check(struct async_struct *info, - char *name, const char *routine) -{ -#ifdef SERIAL_PARANOIA_CHECK - static const char *badmagic = - "Warning: bad magic number for serial struct (%s) in %s\n"; - static const char *badinfo = - "Warning: null async_struct for (%s) in %s\n"; - - if (!info) { - printk(badinfo, name, routine); - return 1; - } - if (info->magic != SERIAL_MAGIC) { - printk(badmagic, name, routine); - return 1; - } -#endif - return 0; -} - - -static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset) -{ - return (inl(info->port+offset) & 0xff); -} - -static _INLINE_ void serial_out(struct async_struct *info, int offset, int value) -{ - outl(value & 0xff, info->port+offset); -} - - -/* - * We used to support using pause I/O for certain machines. We - * haven't supported this for a while, but just in case it's badly - * needed for certain old 386 machines, I've left these #define's - * in.... - */ -#define serial_inp(info, offset) serial_in(info, offset) -#define serial_outp(info, offset, value) serial_out(info, offset, value) - - -/* - * ------------------------------------------------------------ - * rs_stop() and rs_start() - * - * This routines are called before setting or resetting tty->stopped. - * They enable or disable transmitter interrupts, as necessary. - * ------------------------------------------------------------ - */ -static void rs_stop(struct tty_struct *tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_stop")) - return; - - save_flags(flags); cli(); - if (info->IER & UART_IER_THRI) { - info->IER &= ~UART_IER_THRI; - serial_out(info, UART_IER, info->IER); - } - restore_flags(flags); -} - -static void rs_start(struct tty_struct *tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_start")) - return; - - save_flags(flags); cli(); - if (info->xmit.head != info->xmit.tail - && info->xmit.buf - && !(info->IER & UART_IER_THRI)) { - info->IER |= UART_IER_THRI; - serial_out(info, UART_IER, info->IER); - } - restore_flags(flags); -} - -/* - * ---------------------------------------------------------------------- - * - * Here starts the interrupt handling routines. All of the following - * subroutines are declared as inline and are folded into - * rs_interrupt(). They were separated out for readability's sake. - * - * Note: rs_interrupt() is a "fast" interrupt, which means that it - * runs with interrupts turned off. People who may want to modify - * rs_interrupt() should try to keep the interrupt handler as fast as - * possible. After you are done making modifications, it is not a bad - * idea to do: - * - * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c - * - * and look at the resulting assemble code in serial.s. - * - * - Ted Ts'o (tytso@mit.edu), 7-Mar-93 - * ----------------------------------------------------------------------- - */ - -/* - * This routine is used by the interrupt handler to schedule - * processing in the software interrupt portion of the driver. - */ -static _INLINE_ void rs_sched_event(struct async_struct *info, - int event) -{ - info->event |= 1 << event; - queue_task(&info->tqueue, &tq_serial); - mark_bh(SERIAL_BH); -} - -static _INLINE_ void receive_chars(struct async_struct *info, - int *status, struct pt_regs * regs) -{ - struct tty_struct *tty = info->tty; - unsigned char ch; - int ignored = 0; - struct async_icount *icount; - - icount = &info->state->icount; - do { - ch = serial_inp(info, UART_RX); - if (tty->flip.count >= TTY_FLIPBUF_SIZE) - goto ignore_char; - *tty->flip.char_buf_ptr = ch; - icount->rx++; - -#ifdef SERIAL_DEBUG_INTR - printk("DR%02x:%02x...", ch, *status); -#endif - *tty->flip.flag_buf_ptr = 0; - if (*status & (UART_LSR_BI | UART_LSR_PE | - UART_LSR_FE | UART_LSR_OE)) { - /* - * For statistics only - */ - if (*status & UART_LSR_BI) { - *status &= ~(UART_LSR_FE | UART_LSR_PE); - icount->brk++; - /* - * We do the SysRQ and SAK checking - * here because otherwise the break - * may get masked by ignore_status_mask - * or read_status_mask. - */ -#if defined(CONFIG_AU1000_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) - if (info->line == sercons.index) { - if (!break_pressed) { - break_pressed = jiffies; - goto ignore_char; - } - break_pressed = 0; - } -#endif - if (info->flags & ASYNC_SAK) - do_SAK(tty); - } else if (*status & UART_LSR_PE) - icount->parity++; - else if (*status & UART_LSR_FE) - icount->frame++; - if (*status & UART_LSR_OE) - icount->overrun++; - - /* - * Now check to see if character should be - * ignored, and mask off conditions which - * should be ignored. - */ - if (*status & info->ignore_status_mask) { - if (++ignored > 100) - break; - goto ignore_char; - } - *status &= info->read_status_mask; - -#ifdef CONFIG_AU1000_SERIAL_CONSOLE - if (info->line == sercons.index) { - /* Recover the break flag from console xmit */ - *status |= lsr_break_flag; - lsr_break_flag = 0; - } -#endif - if (*status & (UART_LSR_BI)) { -#ifdef SERIAL_DEBUG_INTR - printk("handling break...."); -#endif - *tty->flip.flag_buf_ptr = TTY_BREAK; - } else if (*status & UART_LSR_PE) - *tty->flip.flag_buf_ptr = TTY_PARITY; - else if (*status & UART_LSR_FE) - *tty->flip.flag_buf_ptr = TTY_FRAME; - if (*status & UART_LSR_OE) { - /* - * Overrun is special, since it's - * reported immediately, and doesn't - * affect the current character - */ - tty->flip.count++; - tty->flip.flag_buf_ptr++; - tty->flip.char_buf_ptr++; - *tty->flip.flag_buf_ptr = TTY_OVERRUN; - if (tty->flip.count >= TTY_FLIPBUF_SIZE) - goto ignore_char; - } - } -#if defined(CONFIG_AU1000_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) - if (break_pressed && info->line == sercons.index) { - if (ch != 0 && - time_before(jiffies, break_pressed + HZ*5)) { - handle_sysrq(ch, regs, NULL); - break_pressed = 0; - goto ignore_char; - } - break_pressed = 0; - } -#endif - tty->flip.flag_buf_ptr++; - tty->flip.char_buf_ptr++; - tty->flip.count++; - ignore_char: - *status = serial_inp(info, UART_LSR); - } while (*status & UART_LSR_DR); - tty_flip_buffer_push(tty); -} - -static _INLINE_ void transmit_chars(struct async_struct *info, int *intr_done) -{ - int count; - - if (info->x_char) { - serial_outp(info, UART_TX, info->x_char); - info->state->icount.tx++; - info->x_char = 0; - if (intr_done) - *intr_done = 0; - return; - } - if (info->xmit.head == info->xmit.tail - || info->tty->stopped - || info->tty->hw_stopped) { - info->IER &= ~UART_IER_THRI; - serial_out(info, UART_IER, info->IER); - return; - } - - count = info->xmit_fifo_size; - do { - serial_out(info, UART_TX, info->xmit.buf[info->xmit.tail]); - info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1); - info->state->icount.tx++; - if (info->xmit.head == info->xmit.tail) - break; - } while (--count > 0); - - if (CIRC_CNT(info->xmit.head, - info->xmit.tail, - SERIAL_XMIT_SIZE) < WAKEUP_CHARS) - rs_sched_event(info, RS_EVENT_WRITE_WAKEUP); - -#ifdef SERIAL_DEBUG_INTR - printk("THRE..."); -#endif - if (intr_done) - *intr_done = 0; - - if (info->xmit.head == info->xmit.tail) { - info->IER &= ~UART_IER_THRI; - serial_out(info, UART_IER, info->IER); - } -} - -static _INLINE_ void check_modem_status(struct async_struct *info) -{ - int status; - struct async_icount *icount; - - status = serial_in(info, UART_MSR); - - if (status & UART_MSR_ANY_DELTA) { - icount = &info->state->icount; - /* update input line counters */ - if (status & UART_MSR_TERI) - icount->rng++; - if (status & UART_MSR_DDSR) - icount->dsr++; - if (status & UART_MSR_DDCD) { - icount->dcd++; -#ifdef CONFIG_HARD_PPS - if ((info->flags & ASYNC_HARDPPS_CD) && - (status & UART_MSR_DCD)) - hardpps(); -#endif - } - if (status & UART_MSR_DCTS) - icount->cts++; - wake_up_interruptible(&info->delta_msr_wait); - } - - if ((info->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) { -#if (defined(SERIAL_DEBUG_OPEN) || defined(SERIAL_DEBUG_INTR)) - printk("ttys%d CD now %s...", info->line, - (status & UART_MSR_DCD) ? "on" : "off"); -#endif - if (status & UART_MSR_DCD) - wake_up_interruptible(&info->open_wait); - else { -#ifdef SERIAL_DEBUG_OPEN - printk("doing serial hangup..."); -#endif - if (info->tty) - tty_hangup(info->tty); - } - } - if (info->flags & ASYNC_CTS_FLOW) { - if (info->tty->hw_stopped) { - if (status & UART_MSR_CTS) { -#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW)) - printk("CTS tx start..."); -#endif - info->tty->hw_stopped = 0; - info->IER |= UART_IER_THRI; - serial_out(info, UART_IER, info->IER); - rs_sched_event(info, RS_EVENT_WRITE_WAKEUP); - return; - } - } else { - if (!(status & UART_MSR_CTS)) { -#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW)) - printk("CTS tx stop..."); -#endif - info->tty->hw_stopped = 1; - info->IER &= ~UART_IER_THRI; - serial_out(info, UART_IER, info->IER); - } - } - } -} - - - -/* - * This is the serial driver's interrupt routine for a single port - */ -static void rs_interrupt_single(int irq, void *dev_id, struct pt_regs * regs) -{ - int status; - int pass_counter = 0; - struct async_struct * info; - -#ifdef SERIAL_DEBUG_INTR - printk("rs_interrupt_single(%d)...", irq); -#endif - - info = IRQ_ports[irq]; - if (!info || !info->tty) - return; - - do { - status = serial_inp(info, UART_LSR); -#ifdef SERIAL_DEBUG_INTR - printk("status = %x...", status); -#endif - if (status & UART_LSR_DR) - receive_chars(info, &status, regs); - check_modem_status(info); - if (status & UART_LSR_THRE) - transmit_chars(info, 0); - if (pass_counter++ > RS_ISR_PASS_LIMIT) { -#if 0 - printk("rs_single loop break.\n"); -#endif - break; - } - } while (!(serial_in(info, UART_IIR) & UART_IIR_NO_INT)); - info->last_active = jiffies; -#ifdef SERIAL_DEBUG_INTR - printk("end.\n"); -#endif -} - - -/* - * ------------------------------------------------------------------- - * Here ends the serial interrupt routines. - * ------------------------------------------------------------------- - */ - -/* - * This routine is used to handle the "bottom half" processing for the - * serial driver, known also the "software interrupt" processing. - * This processing is done at the kernel interrupt level, after the - * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This - * is where time-consuming activities which can not be done in the - * interrupt driver proper are done; the interrupt driver schedules - * them using rs_sched_event(), and they get done here. - */ -static void do_serial_bh(void) -{ - run_task_queue(&tq_serial); -} - -static void do_softint(void *private_) -{ - struct async_struct *info = (struct async_struct *) private_; - struct tty_struct *tty; - - tty = info->tty; - if (!tty) - return; - - if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event)) { - if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && - tty->ldisc.write_wakeup) - (tty->ldisc.write_wakeup)(tty); - wake_up_interruptible(&tty->write_wait); -#ifdef SERIAL_HAVE_POLL_WAIT - wake_up_interruptible(&tty->poll_wait); -#endif - } -} - -/* - * This subroutine is called when the RS_TIMER goes off. It is used - * by the serial driver to handle ports that do not have an interrupt - * (irq=0). This doesn't work very well for 16450's, but gives barely - * passable results for a 16550A. (Although at the expense of much - * CPU overhead). - */ -static void rs_timer(unsigned long dummy) -{ - static unsigned long last_strobe; - struct async_struct *info; - unsigned int i; - unsigned long flags; - - if ((jiffies - last_strobe) >= RS_STROBE_TIME) { - for (i=0; i < NR_IRQS; i++) { - info = IRQ_ports[i]; - if (!info) - continue; - save_flags(flags); cli(); - rs_interrupt_single(i, NULL, NULL); - restore_flags(flags); - } - } - last_strobe = jiffies; - mod_timer(&serial_timer, jiffies + RS_STROBE_TIME); - -#if 0 - if (IRQ_ports[0]) { - save_flags(flags); cli(); - rs_interrupt_single(0, NULL, NULL); - restore_flags(flags); - - mod_timer(&serial_timer, jiffies + IRQ_timeout[0]); - } -#endif -} - -/* - * --------------------------------------------------------------- - * Low level utility subroutines for the serial driver: routines to - * figure out the appropriate timeout for an interrupt chain, routines - * to initialize and startup a serial port, and routines to shutdown a - * serial port. Useful stuff like that. - * --------------------------------------------------------------- - */ - -/* - * This routine figures out the correct timeout for a particular IRQ. - * It uses the smallest timeout of all of the serial ports in a - * particular interrupt chain. Now only used for IRQ 0.... - */ -static void figure_IRQ_timeout(int irq) -{ - struct async_struct *info; - int timeout = 60*HZ; /* 60 seconds === a long time :-) */ - - info = IRQ_ports[irq]; - if (!info) { - IRQ_timeout[irq] = 60*HZ; - return; - } - while (info) { - if (info->timeout < timeout) - timeout = info->timeout; - info = info->next_port; - } - if (!irq) - timeout = timeout / 2; - IRQ_timeout[irq] = (timeout > 3) ? timeout-2 : 1; -} - - -static int startup(struct async_struct * info) -{ - unsigned long flags; - int retval=0; - void (*handler)(int, void *, struct pt_regs *); - struct serial_state *state= info->state; - unsigned long page; - - page = get_zeroed_page(GFP_KERNEL); - if (!page) - return -ENOMEM; - - save_flags(flags); cli(); - - if (info->flags & ASYNC_INITIALIZED) { - free_page(page); - goto errout; - } - - if (!CONFIGURED_SERIAL_PORT(state) || !state->type) { - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); - free_page(page); - goto errout; - } - if (info->xmit.buf) - free_page(page); - else - info->xmit.buf = (unsigned char *) page; - - - if (inl(UART_MOD_CNTRL + state->port) != 0x3) { - outl(3, UART_MOD_CNTRL + state->port); - } -#ifdef SERIAL_DEBUG_OPEN - printk("starting up ttys%d (irq %d)...", info->line, state->irq); -#endif - - - /* - * Clear the FIFO buffers and disable them - * (they will be reenabled in change_speed()) - */ - if (uart_config[state->type].flags & UART_CLEAR_FIFO) { - serial_outp(info, UART_FCR, UART_FCR_ENABLE_FIFO); - serial_outp(info, UART_FCR, (UART_FCR_ENABLE_FIFO | - UART_FCR_CLEAR_RCVR | - UART_FCR_CLEAR_XMIT)); - serial_outp(info, UART_FCR, 0); - } - - /* - * Clear the interrupt registers. - */ - (void) serial_inp(info, UART_LSR); - (void) serial_inp(info, UART_RX); - (void) serial_inp(info, UART_IIR); - (void) serial_inp(info, UART_MSR); - - /* - * At this point there's no way the LSR could still be 0xFF; - * if it is, then bail out, because there's likely no UART - * here. - */ - if (!(info->flags & ASYNC_BUGGY_UART) && - (serial_inp(info, UART_LSR) == 0xff)) { - printk("LSR safety check engaged!\n"); - if (capable(CAP_SYS_ADMIN)) { - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); - } else - retval = -ENODEV; - goto errout; - } - - /* - * Allocate the IRQ if necessary - */ -#if 0 - /* au1000, uart0 irq is 0 */ - if (state->irq && (!IRQ_ports[state->irq] || !IRQ_ports[state->irq]->next_port)) { -#endif - if ((!IRQ_ports[state->irq] || !IRQ_ports[state->irq]->next_port)) { - if (IRQ_ports[state->irq]) { - retval = -EBUSY; - goto errout; - } else - handler = rs_interrupt_single; - - retval = request_irq(state->irq, handler, SA_SHIRQ, - "serial", &IRQ_ports[state->irq]); - if (retval) { - if (capable(CAP_SYS_ADMIN)) { - if (info->tty) - set_bit(TTY_IO_ERROR, - &info->tty->flags); - retval = 0; - } - goto errout; - } - } - - /* - * Insert serial port into IRQ chain. - */ - info->prev_port = 0; - info->next_port = IRQ_ports[state->irq]; - if (info->next_port) - info->next_port->prev_port = info; - IRQ_ports[state->irq] = info; - figure_IRQ_timeout(state->irq); - - /* - * Now, initialize the UART - */ - serial_outp(info, UART_LCR, UART_LCR_WLEN8); - - info->MCR = 0; - if (info->tty->termios->c_cflag & CBAUD) - info->MCR = UART_MCR_DTR | UART_MCR_RTS; - { - if (state->irq != 0) - info->MCR |= UART_MCR_OUT2; - } - info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */ - serial_outp(info, UART_MCR, info->MCR); - - /* - * Finally, enable interrupts - */ - info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; - serial_outp(info, UART_IER, info->IER); /* enable interrupts */ - - - /* - * And clear the interrupt registers again for luck. - */ - (void)serial_inp(info, UART_LSR); - (void)serial_inp(info, UART_RX); - (void)serial_inp(info, UART_IIR); - (void)serial_inp(info, UART_MSR); - - if (info->tty) - clear_bit(TTY_IO_ERROR, &info->tty->flags); - info->xmit.head = info->xmit.tail = 0; - - /* - * Set up serial timers... - */ - mod_timer(&serial_timer, jiffies + 2*HZ/100); - - /* - * Set up the tty->alt_speed kludge - */ - if (info->tty) { - if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI) - info->tty->alt_speed = 57600; - if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI) - info->tty->alt_speed = 115200; - if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI) - info->tty->alt_speed = 230400; - if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP) - info->tty->alt_speed = 460800; - } - - /* - * and set the speed of the serial port - */ - change_speed(info, 0); - - info->flags |= ASYNC_INITIALIZED; - restore_flags(flags); - return 0; - -errout: - restore_flags(flags); - return retval; -} - -/* - * This routine will shutdown a serial port; interrupts are disabled, and - * DTR is dropped if the hangup on close termio flag is on. - */ -static void shutdown(struct async_struct * info) -{ - unsigned long flags; - struct serial_state *state; - int retval; - - if (!(info->flags & ASYNC_INITIALIZED)) - return; - - state = info->state; - -#ifdef SERIAL_DEBUG_OPEN - printk("Shutting down serial port %d (irq %d)....", info->line, - state->irq); -#endif - - save_flags(flags); cli(); /* Disable interrupts */ - - /* - * clear delta_msr_wait queue to avoid mem leaks: we may free the irq - * here so the queue might never be waken up - */ - wake_up_interruptible(&info->delta_msr_wait); - - /* - * First unlink the serial port from the IRQ chain... - */ - if (info->next_port) - info->next_port->prev_port = info->prev_port; - if (info->prev_port) - info->prev_port->next_port = info->next_port; - else - IRQ_ports[state->irq] = info->next_port; - figure_IRQ_timeout(state->irq); - - /* - * Free the IRQ, if necessary - */ -// if (state->irq && (!IRQ_ports[state->irq] || - if ((!IRQ_ports[state->irq] || - !IRQ_ports[state->irq]->next_port)) { - if (IRQ_ports[state->irq]) { - free_irq(state->irq, &IRQ_ports[state->irq]); - retval = request_irq(state->irq, rs_interrupt_single, - SA_SHIRQ, "serial", - &IRQ_ports[state->irq]); - - if (retval) - printk("serial shutdown: request_irq: error %d" - " Couldn't reacquire IRQ.\n", retval); - } else - free_irq(state->irq, &IRQ_ports[state->irq]); - } - - if (info->xmit.buf) { - unsigned long pg = (unsigned long) info->xmit.buf; - info->xmit.buf = 0; - free_page(pg); - } - - info->IER = 0; - serial_outp(info, UART_IER, 0x00); /* disable all intrs */ - info->MCR &= ~UART_MCR_OUT2; - info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */ - - /* disable break condition */ - serial_out(info, UART_LCR, serial_inp(info, UART_LCR) & ~UART_LCR_SBC); - - if (!info->tty || (info->tty->termios->c_cflag & HUPCL)) - info->MCR &= ~(UART_MCR_DTR|UART_MCR_RTS); - serial_outp(info, UART_MCR, info->MCR); - - /* disable FIFO's */ - serial_outp(info, UART_FCR, (UART_FCR_ENABLE_FIFO | - UART_FCR_CLEAR_RCVR | - UART_FCR_CLEAR_XMIT)); - serial_outp(info, UART_FCR, 0); - - (void)serial_in(info, UART_RX); /* read data port to reset things */ - - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); - - info->flags &= ~ASYNC_INITIALIZED; - restore_flags(flags); -} - - -/* - * This routine is called to set the UART divisor registers to match - * the specified baud rate for a serial port. - */ -static void change_speed(struct async_struct *info, - struct termios *old_termios) -{ - int quot = 0, baud_base, baud; - unsigned cflag, cval, fcr = 0; - int bits; - unsigned long flags; - - if (!info->tty || !info->tty->termios) - return; - cflag = info->tty->termios->c_cflag; - if (!CONFIGURED_SERIAL_PORT(info)) - return; - - /* byte size and parity */ - switch (cflag & CSIZE) { - case CS5: cval = 0x00; bits = 7; break; - case CS6: cval = 0x01; bits = 8; break; - case CS7: cval = 0x02; bits = 9; break; - case CS8: cval = 0x03; bits = 10; break; - /* Never happens, but GCC is too dumb to figure it out */ - default: cval = 0x00; bits = 7; break; - } - if (cflag & CSTOPB) { - cval |= 0x04; - bits++; - } - if (cflag & PARENB) { - cval |= UART_LCR_PARITY; - bits++; - } - if (!(cflag & PARODD)) - cval |= UART_LCR_EPAR; -#ifdef CMSPAR - if (cflag & CMSPAR) - cval |= UART_LCR_SPAR; -#endif - - /* Determine divisor based on baud rate */ - baud = tty_get_baud_rate(info->tty); - if (!baud) { - baud = 9600; /* B0 transition handled in rs_set_termios */ - } - baud_base = info->state->baud_base; - //if (baud == 38400 && - if (((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST)) { - quot = info->state->custom_divisor; - } - else { - if (baud == 134) - /* Special case since 134 is really 134.5 */ - quot = (2*baud_base / 269); - else if (baud) - quot = baud_base / baud; - } - /* If the quotient is zero refuse the change */ - if (!quot && old_termios) { - info->tty->termios->c_cflag &= ~CBAUD; - info->tty->termios->c_cflag |= (old_termios->c_cflag & CBAUD); - baud = tty_get_baud_rate(info->tty); - if (!baud) - baud = 9600; - if (baud == 38400 && - ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST)) - quot = info->state->custom_divisor; - else { - if (baud == 134) - /* Special case since 134 is really 134.5 */ - quot = (2*baud_base / 269); - else if (baud) - quot = baud_base / baud; - } - } - /* As a last resort, if the quotient is zero, default to 9600 bps */ - if (!quot) - quot = baud_base / 9600; - - info->quot = quot; - info->timeout = ((info->xmit_fifo_size*HZ*bits*quot) / baud_base); - info->timeout += HZ/50; /* Add .02 seconds of slop */ - - /* Set up FIFO's */ - if (uart_config[info->state->type].flags & UART_USE_FIFO) { - if ((info->state->baud_base / quot) < 2400) - fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIGGER_1; - else - fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIGGER_8; - } - - /* CTS flow control flag and modem status interrupts */ - info->IER &= ~UART_IER_MSI; - if (info->flags & ASYNC_HARDPPS_CD) - info->IER |= UART_IER_MSI; - if (cflag & CRTSCTS) { - info->flags |= ASYNC_CTS_FLOW; - info->IER |= UART_IER_MSI; - } else - info->flags &= ~ASYNC_CTS_FLOW; - if (cflag & CLOCAL) - info->flags &= ~ASYNC_CHECK_CD; - else { - info->flags |= ASYNC_CHECK_CD; - info->IER |= UART_IER_MSI; - } - serial_out(info, UART_IER, info->IER); - - /* - * Set up parity check flag - */ -#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) - - info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; - if (I_INPCK(info->tty)) - info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; - if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) - info->read_status_mask |= UART_LSR_BI; - - /* - * Characters to ignore - */ - info->ignore_status_mask = 0; - if (I_IGNPAR(info->tty)) - info->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; - if (I_IGNBRK(info->tty)) { - info->ignore_status_mask |= UART_LSR_BI; - /* - * If we're ignore parity and break indicators, ignore - * overruns too. (For real raw support). - */ - if (I_IGNPAR(info->tty)) - info->ignore_status_mask |= UART_LSR_OE; - } - /* - * !!! ignore all characters if CREAD is not set - */ - if ((cflag & CREAD) == 0) - info->ignore_status_mask |= UART_LSR_DR; - save_flags(flags); cli(); - - serial_outp(info, UART_CLK, quot & 0xffff); - serial_outp(info, UART_LCR, cval); - info->LCR = cval; /* Save LCR */ - restore_flags(flags); -} - -static void rs_put_char(struct tty_struct *tty, unsigned char ch) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_put_char")) - return; - - if (!tty || !info->xmit.buf) - return; - - save_flags(flags); cli(); - if (CIRC_SPACE(info->xmit.head, - info->xmit.tail, - SERIAL_XMIT_SIZE) == 0) { - restore_flags(flags); - return; - } - - info->xmit.buf[info->xmit.head] = ch; - info->xmit.head = (info->xmit.head + 1) & (SERIAL_XMIT_SIZE-1); - restore_flags(flags); -} - -static void rs_flush_chars(struct tty_struct *tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_flush_chars")) - return; - - if (info->xmit.head == info->xmit.tail - || tty->stopped - || tty->hw_stopped - || !info->xmit.buf) - return; - - save_flags(flags); cli(); - info->IER |= UART_IER_THRI; - serial_out(info, UART_IER, info->IER); - restore_flags(flags); -} - -static int rs_write(struct tty_struct * tty, int from_user, - const unsigned char *buf, int count) -{ - int c, ret = 0; - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_write")) - return 0; - - if (!tty || !info->xmit.buf || !tmp_buf) - return 0; - - save_flags(flags); - if (from_user) { - down(&tmp_buf_sem); - while (1) { - int c1; - c = CIRC_SPACE_TO_END(info->xmit.head, - info->xmit.tail, - SERIAL_XMIT_SIZE); - if (count < c) - c = count; - if (c <= 0) - break; - - c -= copy_from_user(tmp_buf, buf, c); - if (!c) { - if (!ret) - ret = -EFAULT; - break; - } - cli(); - c1 = CIRC_SPACE_TO_END(info->xmit.head, - info->xmit.tail, - SERIAL_XMIT_SIZE); - if (c1 < c) - c = c1; - memcpy(info->xmit.buf + info->xmit.head, tmp_buf, c); - info->xmit.head = ((info->xmit.head + c) & - (SERIAL_XMIT_SIZE-1)); - restore_flags(flags); - buf += c; - count -= c; - ret += c; - } - up(&tmp_buf_sem); - } else { - cli(); - while (1) { - c = CIRC_SPACE_TO_END(info->xmit.head, - info->xmit.tail, - SERIAL_XMIT_SIZE); - if (count < c) - c = count; - if (c <= 0) { - break; - } - memcpy(info->xmit.buf + info->xmit.head, buf, c); - info->xmit.head = ((info->xmit.head + c) & - (SERIAL_XMIT_SIZE-1)); - buf += c; - count -= c; - ret += c; - } - restore_flags(flags); - } - if (info->xmit.head != info->xmit.tail - && !tty->stopped - && !tty->hw_stopped - && !(info->IER & UART_IER_THRI)) { - info->IER |= UART_IER_THRI; - serial_out(info, UART_IER, info->IER); - } - return ret; -} - -static int rs_write_room(struct tty_struct *tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - - if (serial_paranoia_check(info, tty->name, "rs_write_room")) - return 0; - return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); -} - -static int rs_chars_in_buffer(struct tty_struct *tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - - if (serial_paranoia_check(info, tty->name, "rs_chars_in_buffer")) - return 0; - return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); -} - -static void rs_flush_buffer(struct tty_struct *tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_flush_buffer")) - return; - save_flags(flags); cli(); - info->xmit.head = info->xmit.tail = 0; - restore_flags(flags); - wake_up_interruptible(&tty->write_wait); -#ifdef SERIAL_HAVE_POLL_WAIT - wake_up_interruptible(&tty->poll_wait); -#endif - if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && - tty->ldisc.write_wakeup) - (tty->ldisc.write_wakeup)(tty); -} - -/* - * This function is used to send a high-priority XON/XOFF character to - * the device - */ -static void rs_send_xchar(struct tty_struct *tty, char ch) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - - if (serial_paranoia_check(info, tty->name, "rs_send_char")) - return; - - info->x_char = ch; - if (ch) { - /* Make sure transmit interrupts are on */ - info->IER |= UART_IER_THRI; - serial_out(info, UART_IER, info->IER); - } -} - -/* - * ------------------------------------------------------------ - * rs_throttle() - * - * This routine is called by the upper-layer tty layer to signal that - * incoming characters should be throttled. - * ------------------------------------------------------------ - */ -static void rs_throttle(struct tty_struct * tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; -#ifdef SERIAL_DEBUG_THROTTLE - char buf[64]; - - printk("throttle %s: %d....\n", tty_name(tty, buf), - tty->ldisc.chars_in_buffer(tty)); -#endif - - if (serial_paranoia_check(info, tty->name, "rs_throttle")) - return; - - if (I_IXOFF(tty)) - rs_send_xchar(tty, STOP_CHAR(tty)); - - if (tty->termios->c_cflag & CRTSCTS) - info->MCR &= ~UART_MCR_RTS; - - save_flags(flags); cli(); - serial_out(info, UART_MCR, info->MCR); - restore_flags(flags); -} - -static void rs_unthrottle(struct tty_struct * tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; -#ifdef SERIAL_DEBUG_THROTTLE - char buf[64]; - - printk("unthrottle %s: %d....\n", tty_name(tty, buf), - tty->ldisc.chars_in_buffer(tty)); -#endif - - if (serial_paranoia_check(info, tty->name, "rs_unthrottle")) - return; - - if (I_IXOFF(tty)) { - if (info->x_char) - info->x_char = 0; - else - rs_send_xchar(tty, START_CHAR(tty)); - } - if (tty->termios->c_cflag & CRTSCTS) - info->MCR |= UART_MCR_RTS; - save_flags(flags); cli(); - serial_out(info, UART_MCR, info->MCR); - restore_flags(flags); -} - -/* - * ------------------------------------------------------------ - * rs_ioctl() and friends - * ------------------------------------------------------------ - */ - -static int get_serial_info(struct async_struct * info, - struct serial_struct * retinfo) -{ - struct serial_struct tmp; - struct serial_state *state = info->state; - - if (!retinfo) - return -EFAULT; - memset(&tmp, 0, sizeof(tmp)); - tmp.type = state->type; - tmp.line = state->line; - tmp.port = state->port; - if (HIGH_BITS_OFFSET) - tmp.port_high = state->port >> HIGH_BITS_OFFSET; - else - tmp.port_high = 0; - tmp.irq = state->irq; - tmp.flags = state->flags; - tmp.xmit_fifo_size = state->xmit_fifo_size; - tmp.baud_base = state->baud_base; - tmp.close_delay = state->close_delay; - tmp.closing_wait = state->closing_wait; - tmp.custom_divisor = state->custom_divisor; - tmp.hub6 = state->hub6; - tmp.io_type = state->io_type; - if (copy_to_user(retinfo,&tmp,sizeof(*retinfo))) - return -EFAULT; - return 0; -} - -static int set_serial_info(struct async_struct * info, - struct serial_struct * new_info) -{ - struct serial_struct new_serial; - struct serial_state old_state, *state; - unsigned int i,change_irq,change_port; - int retval = 0; - unsigned long new_port; - - if (copy_from_user(&new_serial,new_info,sizeof(new_serial))) - return -EFAULT; - state = info->state; - old_state = *state; - - new_port = new_serial.port; - if (HIGH_BITS_OFFSET) - new_port += (unsigned long) new_serial.port_high << HIGH_BITS_OFFSET; - - change_irq = new_serial.irq != state->irq; - change_port = (new_port != ((int) state->port)) || - (new_serial.hub6 != state->hub6); - - if (!capable(CAP_SYS_ADMIN)) { - if (change_irq || change_port || - (new_serial.baud_base != state->baud_base) || - (new_serial.type != state->type) || - (new_serial.close_delay != state->close_delay) || - (new_serial.xmit_fifo_size != state->xmit_fifo_size) || - ((new_serial.flags & ~ASYNC_USR_MASK) != - (state->flags & ~ASYNC_USR_MASK))) - return -EPERM; - state->flags = ((state->flags & ~ASYNC_USR_MASK) | - (new_serial.flags & ASYNC_USR_MASK)); - info->flags = ((info->flags & ~ASYNC_USR_MASK) | - (new_serial.flags & ASYNC_USR_MASK)); - state->custom_divisor = new_serial.custom_divisor; - goto check_and_exit; - } - - new_serial.irq = irq_canonicalize(new_serial.irq); - - if ((new_serial.irq >= NR_IRQS) || (new_serial.irq < 0) || - (new_serial.baud_base < 9600)|| (new_serial.type < PORT_UNKNOWN) || - (new_serial.type > PORT_MAX) || (new_serial.type == PORT_CIRRUS) || - (new_serial.type == PORT_STARTECH)) { - return -EINVAL; - } - - if ((new_serial.type != state->type) || - (new_serial.xmit_fifo_size <= 0)) - new_serial.xmit_fifo_size = - uart_config[new_serial.type].dfl_xmit_fifo_size; - - /* Make sure address is not already in use */ - if (new_serial.type) { - for (i = 0 ; i < NR_PORTS; i++) - if ((state != &rs_table[i]) && - (rs_table[i].port == new_port) && - rs_table[i].type) - return -EADDRINUSE; - } - - if ((change_port || change_irq) && (state->count > 1)) - return -EBUSY; - - /* - * OK, past this point, all the error checking has been done. - * At this point, we start making changes..... - */ - - state->baud_base = new_serial.baud_base; - state->flags = ((state->flags & ~ASYNC_FLAGS) | - (new_serial.flags & ASYNC_FLAGS)); - info->flags = ((state->flags & ~ASYNC_INTERNAL_FLAGS) | - (info->flags & ASYNC_INTERNAL_FLAGS)); - state->custom_divisor = new_serial.custom_divisor; - state->close_delay = new_serial.close_delay * HZ/100; - state->closing_wait = new_serial.closing_wait * HZ/100; - info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; - info->xmit_fifo_size = state->xmit_fifo_size = - new_serial.xmit_fifo_size; - - if ((state->type != PORT_UNKNOWN) && state->port) { - release_region(state->port,8); - } - state->type = new_serial.type; - if (change_port || change_irq) { - /* - * We need to shutdown the serial port at the old - * port/irq combination. - */ - shutdown(info); - state->irq = new_serial.irq; - info->port = state->port = new_port; - info->hub6 = state->hub6 = new_serial.hub6; - if (info->hub6) - info->io_type = state->io_type = SERIAL_IO_HUB6; - else if (info->io_type == SERIAL_IO_HUB6) - info->io_type = state->io_type = SERIAL_IO_PORT; - } - if ((state->type != PORT_UNKNOWN) && state->port) { - request_region(state->port,8,"serial(set)"); - } - - -check_and_exit: - if (!state->port || !state->type) - return 0; - if (info->flags & ASYNC_INITIALIZED) { - if (((old_state.flags & ASYNC_SPD_MASK) != - (state->flags & ASYNC_SPD_MASK)) || - (old_state.custom_divisor != state->custom_divisor)) { - if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI) - info->tty->alt_speed = 57600; - if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI) - info->tty->alt_speed = 115200; - if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI) - info->tty->alt_speed = 230400; - if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP) - info->tty->alt_speed = 460800; - change_speed(info, 0); - } - } else { - retval = startup(info); - } - return retval; -} - - -/* - * get_lsr_info - get line status register info - * - * Purpose: Let user call ioctl() to get info when the UART physically - * is emptied. On bus types like RS485, the transmitter must - * release the bus after transmitting. This must be done when - * the transmit shift register is empty, not be done when the - * transmit holding register is empty. This functionality - * allows an RS485 driver to be written in user space. - */ -static int get_lsr_info(struct async_struct * info, unsigned int *value) -{ - unsigned char status; - unsigned int result; - unsigned long flags; - - save_flags(flags); cli(); - status = serial_in(info, UART_LSR); - restore_flags(flags); - result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0); - - /* - * If we're about to load something into the transmit - * register, we'll pretend the transmitter isn't empty to - * avoid a race condition (depending on when the transmit - * interrupt happens). - */ - if (info->x_char || - ((CIRC_CNT(info->xmit.head, info->xmit.tail, - SERIAL_XMIT_SIZE) > 0) && - !info->tty->stopped && !info->tty->hw_stopped)) - result &= TIOCSER_TEMT; - - if (copy_to_user(value, &result, sizeof(int))) - return -EFAULT; - return 0; -} - - -static int get_modem_info(struct async_struct * info, unsigned int *value) -{ - unsigned char control, status; - unsigned int result; - unsigned long flags; - - control = info->MCR; - save_flags(flags); cli(); - status = serial_in(info, UART_MSR); - restore_flags(flags); - result = ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) - | ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) -#ifdef TIOCM_OUT1 - | ((control & UART_MCR_OUT1) ? TIOCM_OUT1 : 0) - | ((control & UART_MCR_OUT2) ? TIOCM_OUT2 : 0) -#endif - | ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) - | ((status & UART_MSR_RI) ? TIOCM_RNG : 0) - | ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) - | ((status & UART_MSR_CTS) ? TIOCM_CTS : 0); - - if (copy_to_user(value, &result, sizeof(int))) - return -EFAULT; - return 0; -} - -static int set_modem_info(struct async_struct * info, unsigned int cmd, - unsigned int *value) -{ - unsigned int arg; - unsigned long flags; - - if (copy_from_user(&arg, value, sizeof(int))) - return -EFAULT; - - switch (cmd) { - case TIOCMBIS: - if (arg & TIOCM_RTS) - info->MCR |= UART_MCR_RTS; - if (arg & TIOCM_DTR) - info->MCR |= UART_MCR_DTR; -#ifdef TIOCM_OUT1 - if (arg & TIOCM_OUT1) - info->MCR |= UART_MCR_OUT1; - if (arg & TIOCM_OUT2) - info->MCR |= UART_MCR_OUT2; -#endif - if (arg & TIOCM_LOOP) - info->MCR |= UART_MCR_LOOP; - break; - case TIOCMBIC: - if (arg & TIOCM_RTS) - info->MCR &= ~UART_MCR_RTS; - if (arg & TIOCM_DTR) - info->MCR &= ~UART_MCR_DTR; -#ifdef TIOCM_OUT1 - if (arg & TIOCM_OUT1) - info->MCR &= ~UART_MCR_OUT1; - if (arg & TIOCM_OUT2) - info->MCR &= ~UART_MCR_OUT2; -#endif - if (arg & TIOCM_LOOP) - info->MCR &= ~UART_MCR_LOOP; - break; - case TIOCMSET: - info->MCR = ((info->MCR & ~(UART_MCR_RTS | -#ifdef TIOCM_OUT1 - UART_MCR_OUT1 | - UART_MCR_OUT2 | -#endif - UART_MCR_LOOP | - UART_MCR_DTR)) - | ((arg & TIOCM_RTS) ? UART_MCR_RTS : 0) -#ifdef TIOCM_OUT1 - | ((arg & TIOCM_OUT1) ? UART_MCR_OUT1 : 0) - | ((arg & TIOCM_OUT2) ? UART_MCR_OUT2 : 0) -#endif - | ((arg & TIOCM_LOOP) ? UART_MCR_LOOP : 0) - | ((arg & TIOCM_DTR) ? UART_MCR_DTR : 0)); - break; - default: - return -EINVAL; - } - save_flags(flags); cli(); - info->MCR |= ALPHA_KLUDGE_MCR; /* Don't ask */ - serial_out(info, UART_MCR, info->MCR); - restore_flags(flags); - return 0; -} - -static int do_autoconfig(struct async_struct * info) -{ - int retval; - - if (!capable(CAP_SYS_ADMIN)) - return -EPERM; - - if (info->state->count > 1) - return -EBUSY; - - shutdown(info); - - autoconfig(info->state); - retval = startup(info); - if (retval) - return retval; - return 0; -} - -/* - * rs_break() --- routine which turns the break handling on or off - */ -static void rs_break(struct tty_struct *tty, int break_state) -{ - struct async_struct * info = (struct async_struct *)tty->driver_data; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_break")) - return; - - if (!CONFIGURED_SERIAL_PORT(info)) - return; - save_flags(flags); cli(); - if (break_state == -1) - info->LCR |= UART_LCR_SBC; - else - info->LCR &= ~UART_LCR_SBC; - serial_out(info, UART_LCR, info->LCR); - restore_flags(flags); -} - - -static int rs_ioctl(struct tty_struct *tty, struct file * file, - unsigned int cmd, unsigned long arg) -{ - struct async_struct * info = (struct async_struct *)tty->driver_data; - struct async_icount cprev, cnow; /* kernel counter temps */ - struct serial_icounter_struct icount; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_ioctl")) - return -ENODEV; - - if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && - (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGSTRUCT) && - (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { - if (tty->flags & (1 << TTY_IO_ERROR)) - return -EIO; - } - - switch (cmd) { - case TIOCMGET: - return get_modem_info(info, (unsigned int *) arg); - case TIOCMBIS: - case TIOCMBIC: - case TIOCMSET: - return set_modem_info(info, cmd, (unsigned int *) arg); - case TIOCGSERIAL: - return get_serial_info(info, - (struct serial_struct *) arg); - case TIOCSSERIAL: - return set_serial_info(info, - (struct serial_struct *) arg); - case TIOCSERCONFIG: - return do_autoconfig(info); - - case TIOCSERGETLSR: /* Get line status register */ - return get_lsr_info(info, (unsigned int *) arg); - - case TIOCSERGSTRUCT: - if (copy_to_user((struct async_struct *) arg, - info, sizeof(struct async_struct))) - return -EFAULT; - return 0; - - - /* - * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change - * - mask passed in arg for lines of interest - * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) - * Caller should use TIOCGICOUNT to see which one it was - */ - case TIOCMIWAIT: - save_flags(flags); cli(); - /* note the counters on entry */ - cprev = info->state->icount; - restore_flags(flags); - /* Force modem status interrupts on */ - info->IER |= UART_IER_MSI; - serial_out(info, UART_IER, info->IER); - while (1) { - interruptible_sleep_on(&info->delta_msr_wait); - /* see if a signal did it */ - if (signal_pending(current)) - return -ERESTARTSYS; - save_flags(flags); cli(); - cnow = info->state->icount; /* atomic copy */ - restore_flags(flags); - if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && - cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) - return -EIO; /* no change => error */ - if ( ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) || - ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) || - ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) || - ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts)) ) { - return 0; - } - cprev = cnow; - } - /* NOTREACHED */ - - /* - * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) - * Return: write counters to the user passed counter struct - * NB: both 1->0 and 0->1 transitions are counted except for - * RI where only 0->1 is counted. - */ - case TIOCGICOUNT: - save_flags(flags); cli(); - cnow = info->state->icount; - restore_flags(flags); - icount.cts = cnow.cts; - icount.dsr = cnow.dsr; - icount.rng = cnow.rng; - icount.dcd = cnow.dcd; - icount.rx = cnow.rx; - icount.tx = cnow.tx; - icount.frame = cnow.frame; - icount.overrun = cnow.overrun; - icount.parity = cnow.parity; - icount.brk = cnow.brk; - icount.buf_overrun = cnow.buf_overrun; - - if (copy_to_user((void *)arg, &icount, sizeof(icount))) - return -EFAULT; - return 0; - case TIOCSERGWILD: - case TIOCSERSWILD: - /* "setserial -W" is called in Debian boot */ - printk ("TIOCSER?WILD ioctl obsolete, ignored.\n"); - return 0; - - default: - return -ENOIOCTLCMD; - } - return 0; -} - -static void rs_set_termios(struct tty_struct *tty, struct termios *old_termios) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; - unsigned int cflag = tty->termios->c_cflag; - - if ( (cflag == old_termios->c_cflag) - && ( RELEVANT_IFLAG(tty->termios->c_iflag) - == RELEVANT_IFLAG(old_termios->c_iflag))) - return; - - change_speed(info, old_termios); - - /* Handle transition to B0 status */ - if ((old_termios->c_cflag & CBAUD) && - !(cflag & CBAUD)) { - info->MCR &= ~(UART_MCR_DTR|UART_MCR_RTS); - save_flags(flags); cli(); - serial_out(info, UART_MCR, info->MCR); - restore_flags(flags); - } - - /* Handle transition away from B0 status */ - if (!(old_termios->c_cflag & CBAUD) && - (cflag & CBAUD)) { - info->MCR |= UART_MCR_DTR; - if (!(tty->termios->c_cflag & CRTSCTS) || - !test_bit(TTY_THROTTLED, &tty->flags)) { - info->MCR |= UART_MCR_RTS; - } - save_flags(flags); cli(); - serial_out(info, UART_MCR, info->MCR); - restore_flags(flags); - } - - /* Handle turning off CRTSCTS */ - if ((old_termios->c_cflag & CRTSCTS) && - !(tty->termios->c_cflag & CRTSCTS)) { - tty->hw_stopped = 0; - rs_start(tty); - } -} - -/* - * ------------------------------------------------------------ - * rs_close() - * - * This routine is called when the serial port gets closed. First, we - * wait for the last remaining data to be sent. Then, we unlink its - * async structure from the interrupt chain if necessary, and we free - * that IRQ if nothing is left in the chain. - * ------------------------------------------------------------ - */ -static void rs_close(struct tty_struct *tty, struct file * filp) -{ - struct async_struct * info = (struct async_struct *)tty->driver_data; - struct serial_state *state; - unsigned long flags; - - if (!info || serial_paranoia_check(info, tty->name, "rs_close")) - return; - - state = info->state; - - save_flags(flags); cli(); - - if (tty_hung_up_p(filp)) { - DBG_CNT("before DEC-hung"); - MOD_DEC_USE_COUNT; - restore_flags(flags); - return; - } - -#ifdef SERIAL_DEBUG_OPEN - printk("rs_close ttys%d, count = %d\n", info->line, state->count); -#endif - if ((tty->count == 1) && (state->count != 1)) { - /* - * Uh, oh. tty->count is 1, which means that the tty - * structure will be freed. state->count should always - * be one in these conditions. If it's greater than - * one, we've got real problems, since it means the - * serial port won't be shutdown. - */ - printk("rs_close: bad serial port count; tty->count is 1, " - "state->count is %d\n", state->count); - state->count = 1; - } - if (--state->count < 0) { - printk("rs_close: bad serial port count for ttys%d: %d\n", - info->line, state->count); - state->count = 0; - } - if (state->count) { - DBG_CNT("before DEC-2"); - MOD_DEC_USE_COUNT; - restore_flags(flags); - return; - } - info->flags |= ASYNC_CLOSING; - restore_flags(flags); - /* - * Now we wait for the transmit buffer to clear; and we notify - * the line discipline to only process XON/XOFF characters. - */ - tty->closing = 1; - if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) - tty_wait_until_sent(tty, info->closing_wait); - /* - * At this point we stop accepting input. To do this, we - * disable the receive line status interrupts, and tell the - * interrupt driver to stop checking the data ready bit in the - * line status register. - */ - info->IER &= ~UART_IER_RLSI; - info->read_status_mask &= ~UART_LSR_DR; - if (info->flags & ASYNC_INITIALIZED) { - serial_out(info, UART_IER, info->IER); - /* - * Before we drop DTR, make sure the UART transmitter - * has completely drained; this is especially - * important if there is a transmit FIFO! - */ - rs_wait_until_sent(tty, info->timeout); - } - shutdown(info); - if (tty->driver->flush_buffer) - tty->driver->flush_buffer(tty); - if (tty->ldisc.flush_buffer) - tty->ldisc.flush_buffer(tty); - tty->closing = 0; - info->event = 0; - info->tty = 0; - if (info->blocked_open) { - if (info->close_delay) { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(info->close_delay); - } - wake_up_interruptible(&info->open_wait); - } - info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING); - wake_up_interruptible(&info->close_wait); - MOD_DEC_USE_COUNT; -} - -/* - * rs_wait_until_sent() --- wait until the transmitter is empty - */ -static void rs_wait_until_sent(struct tty_struct *tty, int timeout) -{ - struct async_struct * info = (struct async_struct *)tty->driver_data; - unsigned long orig_jiffies, char_time; - int lsr; - - if (serial_paranoia_check(info, tty->name, "rs_wait_until_sent")) - return; - - if (info->state->type == PORT_UNKNOWN) - return; - - if (info->xmit_fifo_size == 0) - return; /* Just in case.... */ - - orig_jiffies = jiffies; - /* - * Set the check interval to be 1/5 of the estimated time to - * send a single character, and make it at least 1. The check - * interval should also be less than the timeout. - * - * Note: we have to use pretty tight timings here to satisfy - * the NIST-PCTS. - */ - char_time = (info->timeout - HZ/50) / info->xmit_fifo_size; - char_time = char_time / 5; - if (char_time == 0) - char_time = 1; - if (timeout && timeout < char_time) - char_time = timeout; - /* - * If the transmitter hasn't cleared in twice the approximate - * amount of time to send the entire FIFO, it probably won't - * ever clear. This assumes the UART isn't doing flow - * control, which is currently the case. Hence, if it ever - * takes longer than info->timeout, this is probably due to a - * UART bug of some kind. So, we clamp the timeout parameter at - * 2*info->timeout. - */ - if (!timeout || timeout > 2*info->timeout) - timeout = 2*info->timeout; -#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT - printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time); - printk("jiff=%lu...", jiffies); -#endif - while (!((lsr = serial_inp(info, UART_LSR)) & UART_LSR_TEMT)) { -#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT - printk("lsr = %d (jiff=%lu)...", lsr, jiffies); -#endif - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(char_time); - if (signal_pending(current)) - break; - if (timeout && time_after(jiffies, orig_jiffies + timeout)) - break; - } - set_current_state(TASK_RUNNING); -#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT - printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies); -#endif -} - -/* - * rs_hangup() --- called by tty_hangup() when a hangup is signaled. - */ -static void rs_hangup(struct tty_struct *tty) -{ - struct async_struct * info = (struct async_struct *)tty->driver_data; - struct serial_state *state = info->state; - - if (serial_paranoia_check(info, tty->name, "rs_hangup")) - return; - - state = info->state; - - rs_flush_buffer(tty); - if (info->flags & ASYNC_CLOSING) - return; - shutdown(info); - info->event = 0; - state->count = 0; - info->flags &= ~ASYNC_NORMAL_ACTIVE; - info->tty = 0; - wake_up_interruptible(&info->open_wait); -} - -/* - * ------------------------------------------------------------ - * rs_open() and friends - * ------------------------------------------------------------ - */ -static int block_til_ready(struct tty_struct *tty, struct file * filp, - struct async_struct *info) -{ - DECLARE_WAITQUEUE(wait, current); - struct serial_state *state = info->state; - int retval; - int do_clocal = 0, extra_count = 0; - unsigned long flags; - - /* - * If the device is in the middle of being closed, then block - * until it's done, and then try again. - */ - if (tty_hung_up_p(filp) || - (info->flags & ASYNC_CLOSING)) { - if (info->flags & ASYNC_CLOSING) - interruptible_sleep_on(&info->close_wait); -#ifdef SERIAL_DO_RESTART - return ((info->flags & ASYNC_HUP_NOTIFY) ? - -EAGAIN : -ERESTARTSYS); -#else - return -EAGAIN; -#endif - } - - /* - * If non-blocking mode is set, or the port is not enabled, - * then make the check up front and then exit. - */ - if ((filp->f_flags & O_NONBLOCK) || - (tty->flags & (1 << TTY_IO_ERROR))) { - info->flags |= ASYNC_NORMAL_ACTIVE; - return 0; - } - - if (tty->termios->c_cflag & CLOCAL) - do_clocal = 1; - - /* - * Block waiting for the carrier detect and the line to become - * free (i.e., not in use by the callout). While we are in - * this loop, state->count is dropped by one, so that - * rs_close() knows when to free things. We restore it upon - * exit, either normal or abnormal. - */ - retval = 0; - add_wait_queue(&info->open_wait, &wait); -#ifdef SERIAL_DEBUG_OPEN - printk("block_til_ready before block: ttys%d, count = %d\n", - state->line, state->count); -#endif - save_flags(flags); cli(); - if (!tty_hung_up_p(filp)) { - extra_count = 1; - state->count--; - } - restore_flags(flags); - info->blocked_open++; - while (1) { - save_flags(flags); cli(); - if (tty->termios->c_cflag & CBAUD) - serial_out(info, UART_MCR, - serial_inp(info, UART_MCR) | - (UART_MCR_DTR | UART_MCR_RTS)); - restore_flags(flags); - set_current_state(TASK_INTERRUPTIBLE); - if (tty_hung_up_p(filp) || - !(info->flags & ASYNC_INITIALIZED)) { -#ifdef SERIAL_DO_RESTART - if (info->flags & ASYNC_HUP_NOTIFY) - retval = -EAGAIN; - else - retval = -ERESTARTSYS; -#else - retval = -EAGAIN; -#endif - break; - } - if (!(info->flags & ASYNC_CLOSING) && - (do_clocal || (serial_in(info, UART_MSR) & - UART_MSR_DCD))) - break; - if (signal_pending(current)) { - retval = -ERESTARTSYS; - break; - } -#ifdef SERIAL_DEBUG_OPEN - printk("block_til_ready blocking: ttys%d, count = %d\n", - info->line, state->count); -#endif - schedule(); - } - set_current_state(TASK_RUNNING); - remove_wait_queue(&info->open_wait, &wait); - if (extra_count) - state->count++; - info->blocked_open--; -#ifdef SERIAL_DEBUG_OPEN - printk("block_til_ready after blocking: ttys%d, count = %d\n", - info->line, state->count); -#endif - if (retval) - return retval; - info->flags |= ASYNC_NORMAL_ACTIVE; - return 0; -} - -static int get_async_struct(int line, struct async_struct **ret_info) -{ - struct async_struct *info; - struct serial_state *sstate; - - sstate = rs_table + line; - sstate->count++; - if (sstate->info) { - *ret_info = sstate->info; - return 0; - } - info = kmalloc(sizeof(struct async_struct), GFP_KERNEL); - if (!info) { - sstate->count--; - return -ENOMEM; - } - memset(info, 0, sizeof(struct async_struct)); - init_waitqueue_head(&info->open_wait); - init_waitqueue_head(&info->close_wait); - init_waitqueue_head(&info->delta_msr_wait); - info->magic = SERIAL_MAGIC; - info->port = sstate->port; - info->flags = sstate->flags; - info->io_type = sstate->io_type; - info->iomem_base = sstate->iomem_base; - info->iomem_reg_shift = sstate->iomem_reg_shift; - info->xmit_fifo_size = sstate->xmit_fifo_size; - info->line = line; - info->tqueue.routine = do_softint; - info->tqueue.data = info; - info->state = sstate; - if (sstate->info) { - kfree(info); - *ret_info = sstate->info; - return 0; - } - *ret_info = sstate->info = info; - return 0; -} - -/* - * This routine is called whenever a serial port is opened. It - * enables interrupts for a serial port, linking in its async structure into - * the IRQ chain. It also performs the serial-specific - * initialization for the tty structure. - */ -static int rs_open(struct tty_struct *tty, struct file * filp) -{ - struct async_struct *info; - int retval, line; - unsigned long page; - - MOD_INC_USE_COUNT; - line = tty->index; - if ((line < 0) || (line >= NR_PORTS)) { - MOD_DEC_USE_COUNT; - return -ENODEV; - } - retval = get_async_struct(line, &info); - if (retval) { - MOD_DEC_USE_COUNT; - return retval; - } - tty->driver_data = info; - info->tty = tty; - if (serial_paranoia_check(info, tty->name, "rs_open")) { - MOD_DEC_USE_COUNT; - return -ENODEV; - } - -#ifdef SERIAL_DEBUG_OPEN - printk("rs_open %s, count = %d\n", tty->name, info->state->count); -#endif - info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; - - if (!tmp_buf) { - page = get_zeroed_page(GFP_KERNEL); - if (!page) { - MOD_DEC_USE_COUNT; - return -ENOMEM; - } - if (tmp_buf) - free_page(page); - else - tmp_buf = (unsigned char *) page; - } - - /* - * If the port is the middle of closing, bail out now - */ - if (tty_hung_up_p(filp) || - (info->flags & ASYNC_CLOSING)) { - if (info->flags & ASYNC_CLOSING) - interruptible_sleep_on(&info->close_wait); - MOD_DEC_USE_COUNT; -#ifdef SERIAL_DO_RESTART - return ((info->flags & ASYNC_HUP_NOTIFY) ? - -EAGAIN : -ERESTARTSYS); -#else - return -EAGAIN; -#endif - } - - /* - * Start up serial port - */ - retval = startup(info); - if (retval) { - MOD_DEC_USE_COUNT; - return retval; - } - - retval = block_til_ready(tty, filp, info); - if (retval) { -#ifdef SERIAL_DEBUG_OPEN - printk("rs_open returning after block_til_ready with %d\n", - retval); -#endif - MOD_DEC_USE_COUNT; - return retval; - } - -#ifdef CONFIG_AU1000_SERIAL_CONSOLE - if (sercons.cflag && sercons.index == line) { - tty->termios->c_cflag = sercons.cflag; - sercons.cflag = 0; - change_speed(info, 0); - } -#endif - -#ifdef SERIAL_DEBUG_OPEN - printk("rs_open %s successful...", tty->name); -#endif - return 0; -} - -/* - * /proc fs routines.... - */ - -static inline int line_info(char *buf, struct serial_state *state) -{ - struct async_struct *info = state->info, scr_info; - char stat_buf[30], control, status; - int ret; - unsigned long flags; - - ret = sprintf(buf, "%d: uart:%s port:%lX irq:%d", - state->line, uart_config[state->type].name, - state->port, state->irq); - - if (!state->port || (state->type == PORT_UNKNOWN)) { - ret += sprintf(buf+ret, "\n"); - return ret; - } - - /* - * Figure out the current RS-232 lines - */ - if (!info) { - info = &scr_info; /* This is just for serial_{in,out} */ - - info->magic = SERIAL_MAGIC; - info->port = state->port; - info->flags = state->flags; - info->quot = 0; - info->tty = 0; - } - save_flags(flags); cli(); - status = serial_in(info, UART_MSR); - control = info != &scr_info ? info->MCR : serial_in(info, UART_MCR); - restore_flags(flags); - - stat_buf[0] = 0; - stat_buf[1] = 0; - if (control & UART_MCR_RTS) - strcat(stat_buf, "|RTS"); - if (status & UART_MSR_CTS) - strcat(stat_buf, "|CTS"); - if (control & UART_MCR_DTR) - strcat(stat_buf, "|DTR"); - if (status & UART_MSR_DSR) - strcat(stat_buf, "|DSR"); - if (status & UART_MSR_DCD) - strcat(stat_buf, "|CD"); - if (status & UART_MSR_RI) - strcat(stat_buf, "|RI"); - - if (info->quot) { - ret += sprintf(buf+ret, " baud:%d", - state->baud_base / info->quot); - } - - ret += sprintf(buf+ret, " tx:%d rx:%d", - state->icount.tx, state->icount.rx); - - if (state->icount.frame) - ret += sprintf(buf+ret, " fe:%d", state->icount.frame); - - if (state->icount.parity) - ret += sprintf(buf+ret, " pe:%d", state->icount.parity); - - if (state->icount.brk) - ret += sprintf(buf+ret, " brk:%d", state->icount.brk); - - if (state->icount.overrun) - ret += sprintf(buf+ret, " oe:%d", state->icount.overrun); - - /* - * Last thing is the RS-232 status lines - */ - ret += sprintf(buf+ret, " %s\n", stat_buf+1); - return ret; -} - -int rs_read_proc(char *page, char **start, off_t off, int count, - int *eof, void *data) -{ - int i, len = 0, l; - off_t begin = 0; - - len += sprintf(page, "serinfo:1.0 driver:%s%s revision:%s\n", - serial_version, LOCAL_VERSTRING, serial_revdate); - for (i = 0; i < NR_PORTS && len < 4000; i++) { - l = line_info(page + len, &rs_table[i]); - len += l; - if (len+begin > off+count) - goto done; - if (len+begin < off) { - begin += len; - len = 0; - } - } - *eof = 1; -done: - if (off >= len+begin) - return 0; - *start = page + (off-begin); - return ((count < begin+len-off) ? count : begin+len-off); -} - -/* - * --------------------------------------------------------------------- - * rs_init() and friends - * - * rs_init() is called at boot-time to initialize the serial driver. - * --------------------------------------------------------------------- - */ - -/* - * This routine prints out the appropriate serial driver version - * number, and identifies which options were configured into this - * driver. - */ -static char serial_options[] __initdata = - " no serial options enabled\n"; -#undef SERIAL_OPT - -static _INLINE_ void show_serial_version(void) -{ - printk(KERN_INFO "%s version %s%s (%s) with%s", serial_name, - serial_version, LOCAL_VERSTRING, serial_revdate, - serial_options); -} - - -/* - * This routine is called by rs_init() to initialize a specific serial - * port. It determines what type of UART chip this serial port is - * using: 8250, 16450, 16550, 16550A. The important question is - * whether or not this UART is a 16550A or not, since this will - * determine whether or not we can use its FIFO features or not. - */ -static void autoconfig(struct serial_state * state) -{ - struct async_struct *info, scr_info; - unsigned long flags; - - -#ifdef SERIAL_DEBUG_AUTOCONF - printk("Testing ttyS%d (0x%04lx, 0x%04x)...\n", state->line, - state->port, (unsigned) state->iomem_base); -#endif - - if (!CONFIGURED_SERIAL_PORT(state)) - return; - - if (inl(UART_MOD_CNTRL + state->port) != 0x3) { - outl(3, UART_MOD_CNTRL + state->port); - } - - state->type = PORT_16550; - info = &scr_info; /* This is just for serial_{in,out} */ - - info->magic = SERIAL_MAGIC; - info->state = state; - info->port = state->port; - info->flags = state->flags; - info->io_type = state->io_type; - info->iomem_base = state->iomem_base; - info->iomem_reg_shift = state->iomem_reg_shift; - - - save_flags(flags); cli(); - state->xmit_fifo_size = uart_config[state->type].dfl_xmit_fifo_size; - - if (info->port) { - request_region(info->port,8,"serial(auto)"); - } - - /* - * Reset the UART. - */ - serial_outp(info, UART_FCR, (UART_FCR_ENABLE_FIFO | - UART_FCR_CLEAR_RCVR | - UART_FCR_CLEAR_XMIT)); - serial_outp(info, UART_FCR, 0); - (void)serial_in(info, UART_RX); - serial_outp(info, UART_IER, 0); - - restore_flags(flags); -} - -int register_serial(struct serial_struct *req); -void unregister_serial(int line); - -EXPORT_SYMBOL(register_serial); -EXPORT_SYMBOL(unregister_serial); - -static struct tty_operations serial_ops = { - .open = rs_open, - .close = rs_close, - .write = rs_write, - .put_char = rs_put_char, - .flush_chars = rs_flush_chars, - .write_room = rs_write_room, - .chars_in_buffer = rs_chars_in_buffer, - .flush_buffer = rs_flush_buffer, - .ioctl = rs_ioctl, - .throttle = rs_throttle, - .unthrottle = rs_unthrottle, - .set_termios = rs_set_termios, - .stop = rs_stop, - .start = rs_start, - .hangup = rs_hangup, - .break_ctl = rs_break, - .send_xchar = rs_send_xchar, - .wait_until_sent = rs_wait_until_sent, - .read_proc = rs_read_proc, -}; - - -/* - * The serial driver boot-time initialization code! - */ -static int __init rs_init(void) -{ - int i; - struct serial_state * state; - - serial_driver = alloc_tty_driver(NR_PORTS); - if (!serial_driver) - return -ENOMEM; - - init_bh(SERIAL_BH, do_serial_bh); - init_timer(&serial_timer); - serial_timer.function = rs_timer; - mod_timer(&serial_timer, jiffies + RS_STROBE_TIME); - - for (i = 0; i < NR_IRQS; i++) { - IRQ_ports[i] = 0; - IRQ_timeout[i] = 0; - } -#ifdef CONFIG_AU1000_SERIAL_CONSOLE - /* - * The interrupt of the serial console port - * can't be shared. - */ - if (sercons.flags & CON_CONSDEV) { - for(i = 0; i < NR_PORTS; i++) - if (i != sercons.index && - rs_table[i].irq == rs_table[sercons.index].irq) - rs_table[i].irq = 0; - } -#endif - show_serial_version(); - - /* Initialize the tty_driver structure */ - - serial_driver->driver_name = "serial"; - serial_driver->devfs_name = "tts/"; - serial_driver->name = "ttyS"; - serial_driver->major = TTY_MAJOR; - serial_driver->minor_start = 64 + SERIAL_DEV_OFFSET; - serial_driver->type = TTY_DRIVER_TYPE_SERIAL; - serial_driver->subtype = SERIAL_TYPE_NORMAL; - serial_driver->init_termios = tty_std_termios; - serial_driver->init_termios.c_cflag = - B9600 | CS8 | CREAD | HUPCL | CLOCAL; - serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS; - tty_set_operations(serial_driver, &serial_ops); - - if (tty_register_driver(serial_driver)) - panic("Couldn't register serial driver\n"); - - for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) { - state->baud_base = get_au1000_uart_baud(); - state->magic = SSTATE_MAGIC; - state->line = i; - state->type = PORT_UNKNOWN; - state->custom_divisor = 0; - state->close_delay = 5*HZ/10; - state->closing_wait = 30*HZ; - state->icount.cts = state->icount.dsr = - state->icount.rng = state->icount.dcd = 0; - state->icount.rx = state->icount.tx = 0; - state->icount.frame = state->icount.parity = 0; - state->icount.overrun = state->icount.brk = 0; - state->irq = irq_canonicalize(state->irq); - if (state->hub6) - state->io_type = SERIAL_IO_HUB6; - if (state->port && check_region(state->port,8)) { - continue; - } - - if (state->flags & ASYNC_BOOT_AUTOCONF) { - autoconfig(state); - } - } - for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) { - if (state->type == PORT_UNKNOWN) { - continue; - } - printk(KERN_INFO "ttyS%02d%s at 0x%04lx (irq = %d) is a %s\n", - state->line + SERIAL_DEV_OFFSET, - (state->flags & ASYNC_FOURPORT) ? " FourPort" : "", - state->port, state->irq, - uart_config[state->type].name); - tty_register_device(serial_driver, state->line, NULL); - } - return 0; -} - -/* - * register_serial and unregister_serial allows for 16x50 serial ports to be - * configured at run-time, to support PCMCIA modems. - */ - -/** - * register_serial - configure a 16x50 serial port at runtime - * @req: request structure - * - * Configure the serial port specified by the request. If the - * port exists and is in use an error is returned. If the port - * is not currently in the table it is added. - * - * The port is then probed and if necessary the IRQ is autodetected - * If this fails an error is returned. - * - * On success the port is ready to use and the line number is returned. - */ - -int register_serial(struct serial_struct *req) -{ - int i; - unsigned long flags; - struct serial_state *state; - struct async_struct *info; - unsigned long port; - - port = req->port; - if (HIGH_BITS_OFFSET) - port += (unsigned long) req->port_high << HIGH_BITS_OFFSET; - - save_flags(flags); cli(); - for (i = 0; i < NR_PORTS; i++) { - if ((rs_table[i].port == port) && - (rs_table[i].iomem_base == req->iomem_base)) - break; - } - if (i == NR_PORTS) { - for (i = 0; i < NR_PORTS; i++) - if ((rs_table[i].type == PORT_UNKNOWN) && - (rs_table[i].count == 0)) - break; - } - if (i == NR_PORTS) { - restore_flags(flags); - return -1; - } - state = &rs_table[i]; - if (rs_table[i].count) { - restore_flags(flags); - printk("Couldn't configure serial #%d (port=%ld,irq=%d): " - "device already open\n", i, port, req->irq); - return -1; - } - state->irq = req->irq; - state->port = port; - state->flags = req->flags; - state->io_type = req->io_type; - state->iomem_base = req->iomem_base; - state->iomem_reg_shift = req->iomem_reg_shift; - if (req->baud_base) - state->baud_base = req->baud_base; - if ((info = state->info) != NULL) { - info->port = port; - info->flags = req->flags; - info->io_type = req->io_type; - info->iomem_base = req->iomem_base; - info->iomem_reg_shift = req->iomem_reg_shift; - } - autoconfig(state); - if (state->type == PORT_UNKNOWN) { - restore_flags(flags); - printk("register_serial(): autoconfig failed\n"); - return -1; - } - restore_flags(flags); - - printk(KERN_INFO "ttyS%02d at %s 0x%04lx (irq = %d) is a %s\n", - state->line + SERIAL_DEV_OFFSET, - state->iomem_base ? "iomem" : "port", - state->iomem_base ? (unsigned long)state->iomem_base : - state->port, state->irq, uart_config[state->type].name); - tty_register_device(serial_driver, state->line, NULL); - return state->line + SERIAL_DEV_OFFSET; -} - -/** - * unregister_serial - deconfigure a 16x50 serial port - * @line: line to deconfigure - * - * The port specified is deconfigured and its resources are freed. Any - * user of the port is disconnected as if carrier was dropped. Line is - * the port number returned by register_serial(). - */ - -void unregister_serial(int line) -{ - unsigned long flags; - struct serial_state *state = &rs_table[line]; - - save_flags(flags); cli(); - if (state->info && state->info->tty) - tty_hangup(state->info->tty); - state->type = PORT_UNKNOWN; - printk(KERN_INFO "tty%02d unloaded\n", state->line); - /* These will be hidden, because they are devices that will no longer - * be available to the system. (ie, PCMCIA modems, once ejected) - */ - tty_unregister_device(serial_driver, state->line); - restore_flags(flags); -} - -static void __exit rs_fini(void) -{ - unsigned long flags; - int e1, e2; - int i; - struct async_struct *info; - - /* printk("Unloading %s: version %s\n", serial_name, serial_version); */ - del_timer_sync(&serial_timer); - save_flags(flags); cli(); - remove_bh(SERIAL_BH); - if ((e1 = tty_unregister_driver(serial_driver))) - printk("serial: failed to unregister serial driver (%d)\n", - e1); - restore_flags(flags); - put_tty_driver(serial_driver); - - for (i = 0; i < NR_PORTS; i++) { - if ((info = rs_table[i].info)) { - rs_table[i].info = NULL; - kfree(info); - } - if ((rs_table[i].type != PORT_UNKNOWN) && rs_table[i].port) { - release_region(rs_table[i].port, 8); - } - } - if (tmp_buf) { - unsigned long pg = (unsigned long) tmp_buf; - tmp_buf = NULL; - free_page(pg); - } -} - -module_init(rs_init); -module_exit(rs_fini); -MODULE_DESCRIPTION("Au1000 serial driver"); - - -/* - * ------------------------------------------------------------ - * Serial console driver - * ------------------------------------------------------------ - */ -#ifdef CONFIG_AU1000_SERIAL_CONSOLE - -#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) - -static struct async_struct async_sercons; - -/* - * Wait for transmitter & holding register to empty - */ -static inline void wait_for_xmitr(struct async_struct *info) -{ - unsigned int status, tmout = 0xffffff; - - do { - status = serial_in(info, UART_LSR); - - if (status & UART_LSR_BI) - lsr_break_flag = UART_LSR_BI; - - if (--tmout == 0) - break; - } while((status & BOTH_EMPTY) != BOTH_EMPTY); -} - - -/* - * Print a string to the serial port trying not to disturb - * any possible real use of the port... - * - * The console_lock must be held when we get here. - */ -static void serial_console_write(struct console *co, const char *s, - unsigned count) -{ - static struct async_struct *info = &async_sercons; - int ier; - unsigned i; - - /* - * First save the IER then disable the interrupts - */ - ier = serial_in(info, UART_IER); - serial_out(info, UART_IER, 0x00); - - /* - * Now, do each character - */ - for (i = 0; i < count; i++, s++) { - wait_for_xmitr(info); - - /* - * Send the character out. - * If a LF, also do CR... - */ - serial_out(info, UART_TX, *s); - if (*s == 10) { - wait_for_xmitr(info); - serial_out(info, UART_TX, 13); - } - } - - /* - * Finally, Wait for transmitter & holding register to empty - * and restore the IER - */ - wait_for_xmitr(info); - serial_out(info, UART_IER, ier); -} - -static struct tty_driver *serial_console_device(struct console *c, int *index) -{ - *index = c->index - SERIAL_DEV_OFFSET; - return serial_driver; -} - -/* - * Setup initial baud/bits/parity. We do two things here: - * - construct a cflag setting for the first rs_open() - * - initialize the serial port - * Return non-zero if we didn't find a serial port. - */ -static int __init serial_console_setup(struct console *co, char *options) -{ - static struct async_struct *info; - struct serial_state *state; - unsigned cval; - int baud = 9600; - int bits = 8; - int parity = 'n'; - int cflag = CREAD | HUPCL | CLOCAL; - int quot = 0; - char *s; - - if (options) { - baud = simple_strtoul(options, NULL, 10); - s = options; - while(*s >= '0' && *s <= '9') - s++; - if (*s) parity = *s++; - if (*s) bits = *s - '0'; - } - - /* - * Now construct a cflag setting. - */ - switch(baud) { - case 1200: - cflag |= B1200; - break; - case 2400: - cflag |= B2400; - break; - case 4800: - cflag |= B4800; - break; - case 19200: - cflag |= B19200; - break; - case 38400: - cflag |= B38400; - break; - case 57600: - cflag |= B57600; - break; - case 115200: - cflag |= B115200; - break; - case 9600: - default: - cflag |= B9600; - break; - } - switch(bits) { - case 7: - cflag |= CS7; - break; - default: - case 8: - cflag |= CS8; - break; - } - switch(parity) { - case 'o': case 'O': - cflag |= PARODD; - break; - case 'e': case 'E': - cflag |= PARENB; - break; - } - co->cflag = cflag; - - /* - * Divisor, bytesize and parity - */ - state = rs_table + co->index; - info = &async_sercons; - info->magic = SERIAL_MAGIC; - info->state = state; - info->port = state->port; - info->flags = state->flags; - info->io_type = state->io_type; - info->iomem_base = state->iomem_base; - info->iomem_reg_shift = state->iomem_reg_shift; - state->baud_base = get_au1000_uart_baud(); - quot = state->baud_base / baud; - - cval = cflag & (CSIZE | CSTOPB); - cval >>= 4; - if (cflag & PARENB) - cval |= UART_LCR_PARITY; - if (!(cflag & PARODD)) - cval |= UART_LCR_EPAR; - - /* - * Disable UART interrupts, set DTR and RTS high - * and set speed. - */ - serial_out(info, UART_CLK, quot & 0xffff); - serial_out(info, UART_IER, 0); - serial_out(info, UART_MCR, UART_MCR_DTR | UART_MCR_RTS); - - /* - * If we read 0xff from the LSR, there is no UART here. - */ - if (serial_in(info, UART_LSR) == 0xff) - return -1; - - return 0; -} - -static struct console sercons = { - .name = "ttyS", - .write = serial_console_write, - .device = serial_console_device, - .setup = serial_console_setup, - .flags = CON_PRINTBUFFER, - .index = -1, -}; - -/* - * Register console. - */ -static void __init au1000_serial_console_init(void) -{ - register_console(&sercons); -} -console_initcall(au1000_serial_console_init); -#endif - -/* - Local variables: - compile-command: "gcc -D__KERNEL__ -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -fno-strict-aliasing -pipe -fno-strength-reduce -march=i586 -DMODULE -DMODVERSIONS -include ../../include/linux/modversions.h -DEXPORT_SYMTAB -c serial.c" - End: -*/ --- linux-2.5.73/arch/mips/au1000/common/time.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/au1000/common/time.c 2003-06-27 15:56:23.000000000 -0700 @@ -5,8 +5,6 @@ * Carsten Langgaard, carstenl@mips.com * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. * - * ######################################################################## - * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. @@ -20,10 +18,9 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * ######################################################################## - * * Setting up the clock on the MIPS boards. */ +#include #include #include #include @@ -33,27 +30,39 @@ #include #include +#include +#include #include #include #include #include +extern void startup_match20_interrupt(void); +extern void do_softirq(void); extern volatile unsigned long wall_jiffies; unsigned long missed_heart_beats = 0; -unsigned long uart_baud_base; static unsigned long r4k_offset; /* Amount to increment compare reg each time */ static unsigned long r4k_cur; /* What counter should be at next timer irq */ +extern unsigned int mips_counter_frequency; + +/* Cycle counter value at the previous timer interrupt.. */ +static unsigned int timerhi = 0, timerlo = 0; -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) +#ifdef CONFIG_PM +#define MATCH20_INC 328 +extern void startup_match20_interrupt(void); +static unsigned long last_pc0, last_match20; +#endif + +static spinlock_t time_lock = SPIN_LOCK_UNLOCKED; static inline void ack_r4ktimer(unsigned long newval) { - write_32bit_cp0_register(CP0_COMPARE, newval); + write_c0_compare(newval); } - /* * There are a lot of conceptually broken versions of the MIPS timer interrupt * handler floating around. This one is rather different, but the algorithm @@ -62,108 +71,201 @@ static inline void ack_r4ktimer(unsigned unsigned long wtimer; void mips_timer_interrupt(struct pt_regs *regs) { - int irq = 7; + int irq = 63; + unsigned long count; + int cpu = smp_processor_id(); + + irq_enter(); + kstat_cpu(cpu).irqs[irq]++; + +#ifdef CONFIG_PM + printk(KERN_ERR "Unexpected CP0 interrupt\n"); + regs->cp0_status &= ~IE_IRQ5; /* disable CP0 interrupt */ + return; +#endif if (r4k_offset == 0) goto null; do { + count = read_c0_count(); + timerhi += (count < timerlo); /* Wrap around */ + timerlo = count; + kstat_cpu(0).irqs[irq]++; do_timer(regs); r4k_cur += r4k_offset; ack_r4ktimer(r4k_cur); - } while (((unsigned long)read_32bit_cp0_register(CP0_COUNT) + } while (((unsigned long)read_c0_count() - r4k_cur) < 0x7fffffff); + irq_exit(); + + if (softirq_pending(cpu)) + do_softirq(); return; null: ack_r4ktimer(0); } -/* +#ifdef CONFIG_PM +void counter0_irq(int irq, void *dev_id, struct pt_regs *regs) +{ + unsigned long pc0; + int time_elapsed; + static int jiffie_drift = 0; + + kstat_cpu(0).irqs[irq]++; + if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) { + /* should never happen! */ + printk(KERN_WARNING "counter 0 w status eror\n"); + return; + } + + pc0 = au_readl(SYS_TOYREAD); + if (pc0 < last_match20) { + /* counter overflowed */ + time_elapsed = (0xffffffff - last_match20) + pc0; + } + else { + time_elapsed = pc0 - last_match20; + } + + while (time_elapsed > 0) { + do_timer(regs); + time_elapsed -= MATCH20_INC; + last_match20 += MATCH20_INC; + jiffie_drift++; + } + + last_pc0 = pc0; + au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); + au_sync(); + + /* our counter ticks at 10.009765625 ms/tick, we we're running + * almost 10uS too slow per tick. + */ + + if (jiffie_drift >= 999) { + jiffie_drift -= 999; + do_timer(regs); /* increment jiffies by one */ + } +} +#endif + +/* * Figure out the r4k offset, the amount to increment the compare - * register for each time tick. + * register for each time tick. * Use the Programmable Counter 1 to do this. */ unsigned long cal_r4koff(void) { unsigned long count; - unsigned long cpu_pll; unsigned long cpu_speed; unsigned long start, end; unsigned long counter; - int i; int trim_divide = 16; + unsigned long flags; - counter = inl(PC_COUNTER_CNTRL); - outl(counter | PC_CNTRL_EN1, PC_COUNTER_CNTRL); + spin_lock_irqsave(&time_lock, flags); - while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_T1S); - outl(trim_divide-1, PC1_TRIM); /* RTC now ticks at 32.768/16 kHz */ - while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_T1S); - - while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_C1S); - outl (0, PC1_COUNTER_WRITE); - while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_C1S); + counter = au_readl(SYS_COUNTER_CNTRL); + au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL); - start = inl(PC1_COUNTER_READ); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); + au_writel(trim_divide-1, SYS_RTCTRIM); /* RTC now ticks at 32.768/16 kHz */ + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); + + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); + au_writel (0, SYS_TOYWRITE); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); + + start = au_readl(SYS_RTCREAD); start += 2; /* wait for the beginning of a new tick */ - while (inl(PC1_COUNTER_READ) < start); + while (au_readl(SYS_RTCREAD) < start); /* Start r4k counter. */ - write_32bit_cp0_register(CP0_COUNT, 0); + write_c0_count(0); end = start + (32768 / trim_divide)/2; /* wait 0.5 seconds */ - while (end > inl(PC1_COUNTER_READ)); + while (end > au_readl(SYS_RTCREAD)); - count = read_32bit_cp0_register(CP0_COUNT); + count = read_c0_count(); cpu_speed = count * 2; - uart_baud_base = (((cpu_speed) / 4) / 16); + mips_counter_frequency = count; + set_au1x00_uart_baud_base(((cpu_speed) / 4) / 16); + spin_unlock_irqrestore(&time_lock, flags); return (cpu_speed / HZ); } -static unsigned long __init get_mips_time(void) -{ - return inl(PC0_COUNTER_READ); -} - -void __init time_init(void) +void __init au1x_time_init(void) { - unsigned int est_freq, flags; + unsigned int est_freq; printk("calculating r4koff... "); r4k_offset = cal_r4koff(); printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); - //est_freq = 2*r4k_offset*HZ; - est_freq = r4k_offset*HZ; + //est_freq = 2*r4k_offset*HZ; + est_freq = r4k_offset*HZ; est_freq += 5000; /* round */ est_freq -= est_freq%10000; - printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, (est_freq%1000000)*100/1000000); - r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset); + set_au1x00_speed(est_freq); + set_au1x00_lcd_clock(); // program the LCD clock + r4k_cur = (read_c0_count() + r4k_offset); - write_32bit_cp0_register(CP0_COMPARE, r4k_cur); - set_cp0_status(ALLINTS); + write_c0_compare(r4k_cur); - /* Read time from the RTC chipset. */ - write_seqlock_irqsave (&xtime_lock, flags); - xtime.tv_sec = get_mips_time(); - xtime.tv_usec = 0; - write_sequnlock_irqrestore(&xtime_lock, flags); + /* no RTC on the pb1000 */ + xtime.tv_sec = 0; + //xtime.tv_usec = 0; + +#ifdef CONFIG_PM + /* + * setup counter 0, since it keeps ticking after a + * 'wait' instruction has been executed. The CP0 timer and + * counter 1 do NOT continue running after 'wait' + * + * It's too early to call request_irq() here, so we handle + * counter 0 interrupt as a special irq and it doesn't show + * up under /proc/interrupts. + */ + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); + au_writel(0, SYS_TOYWRITE); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); + + au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK); + au_writel(~0, SYS_WAKESRC); + au_sync(); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); + + /* setup match20 to interrupt once every 10ms */ + last_pc0 = last_match20 = au_readl(SYS_TOYREAD); + au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); + au_sync(); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); + startup_match20_interrupt(); +#endif + + //set_c0_status(ALLINTS); + au_sync(); } -/* This is for machines which generate the exact clock. */ -#define USECS_PER_JIFFY (1000000/HZ) -#define USECS_PER_JIFFY_FRAC ((1000000ULL << 32) / HZ & 0xffffffff) +void __init au1x_timer_setup(struct irqaction *irq) +{ -/* Cycle counter value at the previous timer interrupt.. */ +} -static unsigned int timerhi = 0, timerlo = 0; +/* This is for machines which generate the exact clock. */ +#define USECS_PER_JIFFY (1000000/HZ) +#define USECS_PER_JIFFY_FRAC (0x100000000*1000000/HZ&0xffffffff) +#ifndef CONFIG_PM static unsigned long div64_32(unsigned long v1, unsigned long v2, unsigned long v3) { @@ -171,13 +273,30 @@ div64_32(unsigned long v1, unsigned long do_div64_32(r0, v1, v2, v3); return r0; } +#endif - -/* - * FIXME: Does playing with the RP bit in c0_status interfere with this code? - */ static unsigned long do_fast_gettimeoffset(void) { +#ifdef CONFIG_PM + unsigned long pc0; + unsigned long offset; + + pc0 = au_readl(SYS_TOYREAD); + if (pc0 < last_pc0) { + offset = 0xffffffff - last_pc0 + pc0; + printk("offset over: %x\n", (unsigned)offset); + } + else { + offset = (unsigned long)(((pc0 - last_pc0) * 305) / 10); + } + if ((pc0-last_pc0) > 2*MATCH20_INC) { + printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n", + (unsigned)offset, (unsigned)last_pc0, + (unsigned)last_match20, (unsigned)pc0); + } + au_sync(); + return offset; +#else u32 count; unsigned long res, tmp; unsigned long r0; @@ -206,7 +325,7 @@ static unsigned long do_fast_gettimeoffs } /* Get last timer tick in absolute kernel time */ - count = read_32bit_cp0_register(CP0_COUNT); + count = read_c0_count(); /* .. relative to previous jiffy (32 bits is enough) */ count -= timerlo; @@ -218,73 +337,12 @@ static unsigned long do_fast_gettimeoffs "r" (quotient)); /* - * Due to possible jiffies inconsistencies, we need to check + * Due to possible jiffies inconsistencies, we need to check * the result so that we'll get a timer that is monotonic. */ if (res >= USECS_PER_JIFFY) res = USECS_PER_JIFFY-1; return res; -} - -void do_gettimeofday(struct timeval *tv) -{ - unsigned long flags; - unsigned long seq; - - do { - seq = read_seqbegin_irqsave(&xtime_lock, flags); - - *tv = xtime; - tv->tv_usec += do_fast_gettimeoffset(); - - /* - * xtime is atomically updated in timer_bh. jiffies - wall_jiffies - * is nonzero if the timer bottom half hasnt executed yet. - */ - if (jiffies - wall_jiffies) - tv->tv_usec += USECS_PER_JIFFY; - - } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); - - - if (tv->tv_usec >= 1000000) { - tv->tv_usec -= 1000000; - tv->tv_sec++; - } -} - -void do_settimeofday(struct timeval *tv) -{ - write_seqlock_irq (&xtime_lock); - - /* This is revolting. We need to set the xtime.tv_usec correctly. - * However, the value in this location is is value at the last tick. - * Discover what correction gettimeofday would have done, and then - * undo it! - */ - tv->tv_usec -= do_fast_gettimeoffset(); - - if (tv->tv_usec < 0) { - tv->tv_usec += 1000000; - tv->tv_sec--; - } - - xtime = *tv; - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; - - write_sequnlock_irq (&xtime_lock); -} - -/* - * The UART baud base is not known at compile time ... if - * we want to be able to use the same code on different - * speed CPUs. - */ -unsigned long get_au1000_uart_baud() -{ - return uart_baud_base; +#endif } --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/au1000/common/usbdev.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,1562 @@ +/* + * BRIEF MODULE DESCRIPTION + * Au1000 USB Device-Side (device layer) + * + * Copyright 2001-2002 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * stevel@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#define DEBUG +#include + +#include +#include +#include +#include +#include +#include +#include + +#ifdef DEBUG +#undef VDEBUG +#ifdef VDEBUG +#define vdbg(fmt, arg...) printk(KERN_DEBUG __FILE__ ": " fmt "\n" , ## arg) +#else +#define vdbg(fmt, arg...) do {} while (0) +#endif +#else +#define vdbg(fmt, arg...) do {} while (0) +#endif + +#define MAX(a,b) (((a)>(b))?(a):(b)) + +#define ALLOC_FLAGS (in_interrupt () ? GFP_ATOMIC : GFP_KERNEL) + +#define EP_FIFO_DEPTH 8 + +typedef enum { + SETUP_STAGE = 0, + DATA_STAGE, + STATUS_STAGE +} ep0_stage_t; + +typedef struct { + int read_fifo; + int write_fifo; + int ctrl_stat; + int read_fifo_status; + int write_fifo_status; +} endpoint_reg_t; + +typedef struct { + usbdev_pkt_t *head; + usbdev_pkt_t *tail; + int count; +} pkt_list_t; + +typedef struct { + int active; + struct usb_endpoint_descriptor *desc; + endpoint_reg_t *reg; + /* Only one of these are used, unless this is the control ep */ + pkt_list_t inlist; + pkt_list_t outlist; + unsigned int indma, outdma; /* DMA channel numbers for IN, OUT */ + /* following are extracted from endpoint descriptor for easy access */ + int max_pkt_size; + int type; + int direction; + /* WE assign endpoint addresses! */ + int address; + spinlock_t lock; +} endpoint_t; + + +static struct usb_dev { + endpoint_t ep[6]; + ep0_stage_t ep0_stage; + + struct usb_device_descriptor * dev_desc; + struct usb_interface_descriptor* if_desc; + struct usb_config_descriptor * conf_desc; + u8 * full_conf_desc; + struct usb_string_descriptor * str_desc[6]; + + /* callback to function layer */ + void (*func_cb)(usbdev_cb_type_t type, unsigned long arg, + void *cb_data); + void* cb_data; + + usbdev_state_t state; // device state + int suspended; // suspended flag + int address; // device address + int interface; + int num_ep; + u8 alternate_setting; + u8 configuration; // configuration value + int remote_wakeup_en; +} usbdev; + + +static endpoint_reg_t ep_reg[] = { + // FIFO's 0 and 1 are EP0 default control + {USBD_EP0RD, USBD_EP0WR, USBD_EP0CS, USBD_EP0RDSTAT, USBD_EP0WRSTAT }, + {0}, + // FIFO 2 is EP2, IN + { -1, USBD_EP2WR, USBD_EP2CS, -1, USBD_EP2WRSTAT }, + // FIFO 3 is EP3, IN + { -1, USBD_EP3WR, USBD_EP3CS, -1, USBD_EP3WRSTAT }, + // FIFO 4 is EP4, OUT + {USBD_EP4RD, -1, USBD_EP4CS, USBD_EP4RDSTAT, -1 }, + // FIFO 5 is EP5, OUT + {USBD_EP5RD, -1, USBD_EP5CS, USBD_EP5RDSTAT, -1 } +}; + +static struct { + unsigned int id; + const char *str; +} ep_dma_id[] = { + { DMA_ID_USBDEV_EP0_TX, "USBDev EP0 IN" }, + { DMA_ID_USBDEV_EP0_RX, "USBDev EP0 OUT" }, + { DMA_ID_USBDEV_EP2_TX, "USBDev EP2 IN" }, + { DMA_ID_USBDEV_EP3_TX, "USBDev EP3 IN" }, + { DMA_ID_USBDEV_EP4_RX, "USBDev EP4 OUT" }, + { DMA_ID_USBDEV_EP5_RX, "USBDev EP5 OUT" } +}; + +#define DIR_OUT 0 +#define DIR_IN (1<<3) + +#define CONTROL_EP USB_ENDPOINT_XFER_CONTROL +#define BULK_EP USB_ENDPOINT_XFER_BULK + +static inline endpoint_t * +epaddr_to_ep(struct usb_dev* dev, int ep_addr) +{ + if (ep_addr >= 0 && ep_addr < 2) + return &dev->ep[0]; + if (ep_addr < 6) + return &dev->ep[ep_addr]; + return NULL; +} + +static const char* std_req_name[] = { + "GET_STATUS", + "CLEAR_FEATURE", + "RESERVED", + "SET_FEATURE", + "RESERVED", + "SET_ADDRESS", + "GET_DESCRIPTOR", + "SET_DESCRIPTOR", + "GET_CONFIGURATION", + "SET_CONFIGURATION", + "GET_INTERFACE", + "SET_INTERFACE", + "SYNCH_FRAME" +}; + +static inline const char* +get_std_req_name(int req) +{ + return (req >= 0 && req <= 12) ? std_req_name[req] : "UNKNOWN"; +} + +#if 0 +static void +dump_setup(struct usb_ctrlrequest* s) +{ + dbg(__FUNCTION__ ": requesttype=%d", s->requesttype); + dbg(__FUNCTION__ ": request=%d %s", s->request, + get_std_req_name(s->request)); + dbg(__FUNCTION__ ": value=0x%04x", s->wValue); + dbg(__FUNCTION__ ": index=%d", s->index); + dbg(__FUNCTION__ ": length=%d", s->length); +} +#endif + +static inline usbdev_pkt_t * +alloc_packet(endpoint_t * ep, int data_size, void* data) +{ + usbdev_pkt_t* pkt = + (usbdev_pkt_t *)kmalloc(sizeof(usbdev_pkt_t) + data_size, + ALLOC_FLAGS); + if (!pkt) + return NULL; + pkt->ep_addr = ep->address; + pkt->size = data_size; + pkt->status = 0; + pkt->next = NULL; + if (data) + memcpy(pkt->payload, data, data_size); + + return pkt; +} + + +/* + * Link a packet to the tail of the enpoint's packet list. + * EP spinlock must be held when calling. + */ +static void +link_tail(endpoint_t * ep, pkt_list_t * list, usbdev_pkt_t * pkt) +{ + if (!list->tail) { + list->head = list->tail = pkt; + list->count = 1; + } else { + list->tail->next = pkt; + list->tail = pkt; + list->count++; + } +} + +/* + * Unlink and return a packet from the head of the given packet + * list. It is the responsibility of the caller to free the packet. + * EP spinlock must be held when calling. + */ +static usbdev_pkt_t * +unlink_head(pkt_list_t * list) +{ + usbdev_pkt_t *pkt; + + pkt = list->head; + if (!pkt || !list->count) { + return NULL; + } + + list->head = pkt->next; + if (!list->head) { + list->head = list->tail = NULL; + list->count = 0; + } else + list->count--; + + return pkt; +} + +/* + * Create and attach a new packet to the tail of the enpoint's + * packet list. EP spinlock must be held when calling. + */ +static usbdev_pkt_t * +add_packet(endpoint_t * ep, pkt_list_t * list, int size) +{ + usbdev_pkt_t *pkt = alloc_packet(ep, size, NULL); + if (!pkt) + return NULL; + + link_tail(ep, list, pkt); + return pkt; +} + + +/* + * Unlink and free a packet from the head of the enpoint's + * packet list. EP spinlock must be held when calling. + */ +static inline void +free_packet(pkt_list_t * list) +{ + kfree(unlink_head(list)); +} + +/* EP spinlock must be held when calling. */ +static inline void +flush_pkt_list(pkt_list_t * list) +{ + while (list->count) + free_packet(list); +} + +/* EP spinlock must be held when calling */ +static inline void +flush_write_fifo(endpoint_t * ep) +{ + if (ep->reg->write_fifo_status >= 0) { + au_writel(USBDEV_FSTAT_FLUSH | USBDEV_FSTAT_UF | + USBDEV_FSTAT_OF, + ep->reg->write_fifo_status); + //udelay(100); + //au_writel(USBDEV_FSTAT_UF | USBDEV_FSTAT_OF, + // ep->reg->write_fifo_status); + } +} + +/* EP spinlock must be held when calling */ +static inline void +flush_read_fifo(endpoint_t * ep) +{ + if (ep->reg->read_fifo_status >= 0) { + au_writel(USBDEV_FSTAT_FLUSH | USBDEV_FSTAT_UF | + USBDEV_FSTAT_OF, + ep->reg->read_fifo_status); + //udelay(100); + //au_writel(USBDEV_FSTAT_UF | USBDEV_FSTAT_OF, + // ep->reg->read_fifo_status); + } +} + + +/* EP spinlock must be held when calling. */ +static void +endpoint_flush(endpoint_t * ep) +{ + // First, flush all packets + flush_pkt_list(&ep->inlist); + flush_pkt_list(&ep->outlist); + + // Now flush the endpoint's h/w FIFO(s) + flush_write_fifo(ep); + flush_read_fifo(ep); +} + +/* EP spinlock must be held when calling. */ +static void +endpoint_stall(endpoint_t * ep) +{ + u32 cs; + + warn(__FUNCTION__); + + cs = au_readl(ep->reg->ctrl_stat) | USBDEV_CS_STALL; + au_writel(cs, ep->reg->ctrl_stat); +} + +/* EP spinlock must be held when calling. */ +static void +endpoint_unstall(endpoint_t * ep) +{ + u32 cs; + + warn(__FUNCTION__); + + cs = au_readl(ep->reg->ctrl_stat) & ~USBDEV_CS_STALL; + au_writel(cs, ep->reg->ctrl_stat); +} + +static void +endpoint_reset_datatoggle(endpoint_t * ep) +{ + // FIXME: is this possible? +} + + +/* EP spinlock must be held when calling. */ +static int +endpoint_fifo_read(endpoint_t * ep) +{ + int read_count = 0; + u8 *bufptr; + usbdev_pkt_t *pkt = ep->outlist.tail; + + if (!pkt) + return -EINVAL; + + bufptr = &pkt->payload[pkt->size]; + while (au_readl(ep->reg->read_fifo_status) & USBDEV_FSTAT_FCNT_MASK) { + *bufptr++ = au_readl(ep->reg->read_fifo) & 0xff; + read_count++; + pkt->size++; + } + + return read_count; +} + +#if 0 +/* EP spinlock must be held when calling. */ +static int +endpoint_fifo_write(endpoint_t * ep, int index) +{ + int write_count = 0; + u8 *bufptr; + usbdev_pkt_t *pkt = ep->inlist.head; + + if (!pkt) + return -EINVAL; + + bufptr = &pkt->payload[index]; + while ((au_readl(ep->reg->write_fifo_status) & + USBDEV_FSTAT_FCNT_MASK) < EP_FIFO_DEPTH) { + if (bufptr < pkt->payload + pkt->size) { + au_writel(*bufptr++, ep->reg->write_fifo); + write_count++; + } else { + break; + } + } + + return write_count; +} +#endif + +/* + * This routine is called to restart transmission of a packet. + * The endpoint's TSIZE must be set to the new packet's size, + * and DMA to the write FIFO needs to be restarted. + * EP spinlock must be held when calling. + */ +static void +kickstart_send_packet(endpoint_t * ep) +{ + u32 cs; + usbdev_pkt_t *pkt = ep->inlist.head; + + vdbg(__FUNCTION__ ": ep%d, pkt=%p", ep->address, pkt); + + if (!pkt) { + err(__FUNCTION__ ": head=NULL! list->count=%d", + ep->inlist.count); + return; + } + + dma_cache_wback_inv((unsigned long)pkt->payload, pkt->size); + + /* + * make sure FIFO is empty + */ + flush_write_fifo(ep); + + cs = au_readl(ep->reg->ctrl_stat) & USBDEV_CS_STALL; + cs |= (pkt->size << USBDEV_CS_TSIZE_BIT); + au_writel(cs, ep->reg->ctrl_stat); + + if (get_dma_active_buffer(ep->indma) == 1) { + set_dma_count1(ep->indma, pkt->size); + set_dma_addr1(ep->indma, virt_to_phys(pkt->payload)); + enable_dma_buffer1(ep->indma); // reenable + } else { + set_dma_count0(ep->indma, pkt->size); + set_dma_addr0(ep->indma, virt_to_phys(pkt->payload)); + enable_dma_buffer0(ep->indma); // reenable + } + if (dma_halted(ep->indma)) + start_dma(ep->indma); +} + + +/* + * This routine is called when a packet in the inlist has been + * completed. Frees the completed packet and starts sending the + * next. EP spinlock must be held when calling. + */ +static usbdev_pkt_t * +send_packet_complete(endpoint_t * ep) +{ + usbdev_pkt_t *pkt = unlink_head(&ep->inlist); + + if (pkt) { + pkt->status = + (au_readl(ep->reg->ctrl_stat) & USBDEV_CS_NAK) ? + PKT_STATUS_NAK : PKT_STATUS_ACK; + + vdbg(__FUNCTION__ ": ep%d, %s pkt=%p, list count=%d", + ep->address, (pkt->status & PKT_STATUS_NAK) ? + "NAK" : "ACK", pkt, ep->inlist.count); + } + + /* + * The write fifo should already be drained if things are + * working right, but flush it anyway just in case. + */ + flush_write_fifo(ep); + + // begin transmitting next packet in the inlist + if (ep->inlist.count) { + kickstart_send_packet(ep); + } + + return pkt; +} + +/* + * Add a new packet to the tail of the given ep's packet + * inlist. The transmit complete interrupt frees packets from + * the head of this list. EP spinlock must be held when calling. + */ +static int +send_packet(struct usb_dev* dev, usbdev_pkt_t *pkt, int async) +{ + pkt_list_t *list; + endpoint_t* ep; + + if (!pkt || !(ep = epaddr_to_ep(dev, pkt->ep_addr))) + return -EINVAL; + + if (!pkt->size) + return 0; + + list = &ep->inlist; + + if (!async && list->count) { + halt_dma(ep->indma); + flush_pkt_list(list); + } + + link_tail(ep, list, pkt); + + vdbg(__FUNCTION__ ": ep%d, pkt=%p, size=%d, list count=%d", + ep->address, pkt, pkt->size, list->count); + + if (list->count == 1) { + /* + * if the packet count is one, it means the list was empty, + * and no more data will go out this ep until we kick-start + * it again. + */ + kickstart_send_packet(ep); + } + + return pkt->size; +} + +/* + * This routine is called to restart reception of a packet. + * EP spinlock must be held when calling. + */ +static void +kickstart_receive_packet(endpoint_t * ep) +{ + usbdev_pkt_t *pkt; + + // get and link a new packet for next reception + if (!(pkt = add_packet(ep, &ep->outlist, ep->max_pkt_size))) { + err(__FUNCTION__ ": could not alloc new packet"); + return; + } + + if (get_dma_active_buffer(ep->outdma) == 1) { + clear_dma_done1(ep->outdma); + set_dma_count1(ep->outdma, ep->max_pkt_size); + set_dma_count0(ep->outdma, 0); + set_dma_addr1(ep->outdma, virt_to_phys(pkt->payload)); + enable_dma_buffer1(ep->outdma); // reenable + } else { + clear_dma_done0(ep->outdma); + set_dma_count0(ep->outdma, ep->max_pkt_size); + set_dma_count1(ep->outdma, 0); + set_dma_addr0(ep->outdma, virt_to_phys(pkt->payload)); + enable_dma_buffer0(ep->outdma); // reenable + } + if (dma_halted(ep->outdma)) + start_dma(ep->outdma); +} + + +/* + * This routine is called when a packet in the outlist has been + * completed (received) and we need to prepare for a new packet + * to be received. Halts DMA and computes the packet size from the + * remaining DMA counter. Then prepares a new packet for reception + * and restarts DMA. FIXME: what if another packet comes in + * on top of the completed packet? Counter would be wrong. + * EP spinlock must be held when calling. + */ +static usbdev_pkt_t * +receive_packet_complete(endpoint_t * ep) +{ + usbdev_pkt_t *pkt = ep->outlist.tail; + u32 cs; + + halt_dma(ep->outdma); + + cs = au_readl(ep->reg->ctrl_stat); + + if (!pkt) + return NULL; + + pkt->size = ep->max_pkt_size - get_dma_residue(ep->outdma); + if (pkt->size) + dma_cache_inv((unsigned long)pkt->payload, pkt->size); + /* + * need to pull out any remaining bytes in the FIFO. + */ + endpoint_fifo_read(ep); + /* + * should be drained now, but flush anyway just in case. + */ + flush_read_fifo(ep); + + pkt->status = (cs & USBDEV_CS_NAK) ? PKT_STATUS_NAK : PKT_STATUS_ACK; + if (ep->address == 0 && (cs & USBDEV_CS_SU)) + pkt->status |= PKT_STATUS_SU; + + vdbg(__FUNCTION__ ": ep%d, %s pkt=%p, size=%d", + ep->address, (pkt->status & PKT_STATUS_NAK) ? + "NAK" : "ACK", pkt, pkt->size); + + kickstart_receive_packet(ep); + + return pkt; +} + + +/* + **************************************************************************** + * Here starts the standard device request handlers. They are + * all called by do_setup() via a table of function pointers. + **************************************************************************** + */ + +static ep0_stage_t +do_get_status(struct usb_dev* dev, struct usb_ctrlrequest* setup) +{ + switch (setup->bRequestType) { + case 0x80: // Device + // FIXME: send device status + break; + case 0x81: // Interface + // FIXME: send interface status + break; + case 0x82: // End Point + // FIXME: send endpoint status + break; + default: + // Invalid Command + endpoint_stall(&dev->ep[0]); // Stall End Point 0 + break; + } + + return STATUS_STAGE; +} + +static ep0_stage_t +do_clear_feature(struct usb_dev* dev, struct usb_ctrlrequest* setup) +{ + switch (setup->bRequestType) { + case 0x00: // Device + if ((le16_to_cpu(setup->wValue) & 0xff) == 1) + dev->remote_wakeup_en = 0; + else + endpoint_stall(&dev->ep[0]); + break; + case 0x02: // End Point + if ((le16_to_cpu(setup->wValue) & 0xff) == 0) { + endpoint_t *ep = + epaddr_to_ep(dev, + le16_to_cpu(setup->wIndex) & 0xff); + + endpoint_unstall(ep); + endpoint_reset_datatoggle(ep); + } else + endpoint_stall(&dev->ep[0]); + break; + } + + return SETUP_STAGE; +} + +static ep0_stage_t +do_reserved(struct usb_dev* dev, struct usb_ctrlrequest* setup) +{ + // Invalid request, stall End Point 0 + endpoint_stall(&dev->ep[0]); + return SETUP_STAGE; +} + +static ep0_stage_t +do_set_feature(struct usb_dev* dev, struct usb_ctrlrequest* setup) +{ + switch (setup->bRequestType) { + case 0x00: // Device + if ((le16_to_cpu(setup->wValue) & 0xff) == 1) + dev->remote_wakeup_en = 1; + else + endpoint_stall(&dev->ep[0]); + break; + case 0x02: // End Point + if ((le16_to_cpu(setup->wValue) & 0xff) == 0) { + endpoint_t *ep = + epaddr_to_ep(dev, + le16_to_cpu(setup->wIndex) & 0xff); + + endpoint_stall(ep); + } else + endpoint_stall(&dev->ep[0]); + break; + } + + return SETUP_STAGE; +} + +static ep0_stage_t +do_set_address(struct usb_dev* dev, struct usb_ctrlrequest* setup) +{ + int new_state = dev->state; + int new_addr = le16_to_cpu(setup->wValue); + + dbg(__FUNCTION__ ": our address=%d", new_addr); + + if (new_addr > 127) { + // usb spec doesn't tell us what to do, so just go to + // default state + new_state = DEFAULT; + dev->address = 0; + } else if (dev->address != new_addr) { + dev->address = new_addr; + new_state = ADDRESS; + } + + if (dev->state != new_state) { + dev->state = new_state; + /* inform function layer of usbdev state change */ + dev->func_cb(CB_NEW_STATE, dev->state, dev->cb_data); + } + + return SETUP_STAGE; +} + +static ep0_stage_t +do_get_descriptor(struct usb_dev* dev, struct usb_ctrlrequest* setup) +{ + int strnum, desc_len = le16_to_cpu(setup->wLength); + + switch (le16_to_cpu(setup->wValue) >> 8) { + case USB_DT_DEVICE: + // send device descriptor! + desc_len = desc_len > dev->dev_desc->bLength ? + dev->dev_desc->bLength : desc_len; + dbg("sending device desc, size=%d", desc_len); + send_packet(dev, alloc_packet(&dev->ep[0], desc_len, + dev->dev_desc), 0); + break; + case USB_DT_CONFIG: + // If the config descr index in low-byte of + // setup->wValue is valid, send config descr, + // otherwise stall ep0. + if ((le16_to_cpu(setup->wValue) & 0xff) == 0) { + // send config descriptor! + if (desc_len <= USB_DT_CONFIG_SIZE) { + dbg("sending partial config desc, size=%d", + desc_len); + send_packet(dev, + alloc_packet(&dev->ep[0], + desc_len, + dev->conf_desc), + 0); + } else { + int len = dev->conf_desc->wTotalLength; + dbg("sending whole config desc," + " size=%d, our size=%d", desc_len, len); + desc_len = desc_len > len ? len : desc_len; + send_packet(dev, + alloc_packet(&dev->ep[0], + desc_len, + dev->full_conf_desc), + 0); + } + } else + endpoint_stall(&dev->ep[0]); + break; + case USB_DT_STRING: + // If the string descr index in low-byte of setup->wValue + // is valid, send string descr, otherwise stall ep0. + strnum = le16_to_cpu(setup->wValue) & 0xff; + if (strnum >= 0 && strnum < 6) { + struct usb_string_descriptor *desc = + dev->str_desc[strnum]; + desc_len = desc_len > desc->bLength ? + desc->bLength : desc_len; + dbg("sending string desc %d", strnum); + send_packet(dev, + alloc_packet(&dev->ep[0], desc_len, + desc), 0); + } else + endpoint_stall(&dev->ep[0]); + break; + default: + // Invalid request + err("invalid get desc=%d, stalled", + le16_to_cpu(setup->wValue) >> 8); + endpoint_stall(&dev->ep[0]); // Stall endpoint 0 + break; + } + + return STATUS_STAGE; +} + +static ep0_stage_t +do_set_descriptor(struct usb_dev* dev, struct usb_ctrlrequest* setup) +{ + // TODO: implement + // there will be an OUT data stage (the descriptor to set) + return DATA_STAGE; +} + +static ep0_stage_t +do_get_configuration(struct usb_dev* dev, struct usb_ctrlrequest* setup) +{ + // send dev->configuration + dbg("sending config"); + send_packet(dev, alloc_packet(&dev->ep[0], 1, &dev->configuration), + 0); + return STATUS_STAGE; +} + +static ep0_stage_t +do_set_configuration(struct usb_dev* dev, struct usb_ctrlrequest* setup) +{ + // set active config to low-byte of setup->wValue + dev->configuration = le16_to_cpu(setup->wValue) & 0xff; + dbg("set config, config=%d", dev->configuration); + if (!dev->configuration && dev->state > DEFAULT) { + dev->state = ADDRESS; + /* inform function layer of usbdev state change */ + dev->func_cb(CB_NEW_STATE, dev->state, dev->cb_data); + } else if (dev->configuration == 1) { + dev->state = CONFIGURED; + /* inform function layer of usbdev state change */ + dev->func_cb(CB_NEW_STATE, dev->state, dev->cb_data); + } else { + // FIXME: "respond with request error" - how? + } + + return SETUP_STAGE; +} + +static ep0_stage_t +do_get_interface(struct usb_dev* dev, struct usb_ctrlrequest* setup) +{ + // interface must be zero. + if ((le16_to_cpu(setup->wIndex) & 0xff) || dev->state == ADDRESS) { + // FIXME: respond with "request error". how? + } else if (dev->state == CONFIGURED) { + // send dev->alternate_setting + dbg("sending alt setting"); + send_packet(dev, alloc_packet(&dev->ep[0], 1, + &dev->alternate_setting), 0); + } + + return STATUS_STAGE; + +} + +static ep0_stage_t +do_set_interface(struct usb_dev* dev, struct usb_ctrlrequest* setup) +{ + if (dev->state == ADDRESS) { + // FIXME: respond with "request error". how? + } else if (dev->state == CONFIGURED) { + dev->interface = le16_to_cpu(setup->wIndex) & 0xff; + dev->alternate_setting = + le16_to_cpu(setup->wValue) & 0xff; + // interface and alternate_setting must be zero + if (dev->interface || dev->alternate_setting) { + // FIXME: respond with "request error". how? + } + } + + return SETUP_STAGE; +} + +static ep0_stage_t +do_synch_frame(struct usb_dev* dev, struct usb_ctrlrequest* setup) +{ + // TODO + return SETUP_STAGE; +} + +typedef ep0_stage_t (*req_method_t)(struct usb_dev* dev, + struct usb_ctrlrequest* setup); + + +/* Table of the standard device request handlers */ +static const req_method_t req_method[] = { + do_get_status, + do_clear_feature, + do_reserved, + do_set_feature, + do_reserved, + do_set_address, + do_get_descriptor, + do_set_descriptor, + do_get_configuration, + do_set_configuration, + do_get_interface, + do_set_interface, + do_synch_frame +}; + + +// SETUP packet request dispatcher +static void +do_setup (struct usb_dev* dev, struct usb_ctrlrequest* setup) +{ + req_method_t m; + + dbg(__FUNCTION__ ": req %d %s", setup->bRequestType, + get_std_req_name(setup->bRequestType)); + + if ((setup->bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD || + (setup->bRequestType & USB_RECIP_MASK) != USB_RECIP_DEVICE) { + err(__FUNCTION__ ": invalid requesttype 0x%02x", + setup->bRequestType); + return; + } + + if ((setup->bRequestType & 0x80) == USB_DIR_OUT && setup->wLength) + dbg(__FUNCTION__ ": OUT phase! length=%d", setup->wLength); + + if (setup->bRequestType < sizeof(req_method)/sizeof(req_method_t)) + m = req_method[setup->bRequestType]; + else + m = do_reserved; + + dev->ep0_stage = (*m)(dev, setup); +} + +/* + * A SETUP, DATA0, or DATA1 packet has been received + * on the default control endpoint's fifo. + */ +static void +process_ep0_receive (struct usb_dev* dev) +{ + endpoint_t *ep0 = &dev->ep[0]; + usbdev_pkt_t *pkt; + + spin_lock(&ep0->lock); + + // complete packet and prepare a new packet + pkt = receive_packet_complete(ep0); + if (!pkt) { + // FIXME: should put a warn/err here. + spin_unlock(&ep0->lock); + return; + } + + // unlink immediately from endpoint. + unlink_head(&ep0->outlist); + + // override current stage if h/w says it's a setup packet + if (pkt->status & PKT_STATUS_SU) + dev->ep0_stage = SETUP_STAGE; + + switch (dev->ep0_stage) { + case SETUP_STAGE: + vdbg("SU bit is %s in setup stage", + (pkt->status & PKT_STATUS_SU) ? "set" : "not set"); + + if (pkt->size == sizeof(struct usb_ctrlrequest)) { +#ifdef VDEBUG + if (pkt->status & PKT_STATUS_ACK) + vdbg("received SETUP"); + else + vdbg("received NAK SETUP"); +#endif + do_setup(dev, (struct usb_ctrlrequest*)pkt->payload); + } else + err(__FUNCTION__ ": wrong size SETUP received"); + break; + case DATA_STAGE: + /* + * this setup has an OUT data stage. Of the standard + * device requests, only set_descriptor has this stage, + * so this packet is that descriptor. TODO: drop it for + * now, set_descriptor not implemented. + * + * Need to place a byte in the write FIFO here, to prepare + * to send a zero-length DATA ack packet to the host in the + * STATUS stage. + */ + au_writel(0, ep0->reg->write_fifo); + dbg("received OUT stage DATAx on EP0, size=%d", pkt->size); + dev->ep0_stage = SETUP_STAGE; + break; + case STATUS_STAGE: + // this setup had an IN data stage, and host is ACK'ing + // the packet we sent during that stage. + if (pkt->size != 0) + warn("received non-zero ACK on EP0??"); +#ifdef VDEBUG + else + vdbg("received ACK on EP0"); +#endif + dev->ep0_stage = SETUP_STAGE; + break; + } + + spin_unlock(&ep0->lock); + // we're done processing the packet, free it + kfree(pkt); +} + + +/* + * A DATA0/1 packet has been received on one of the OUT endpoints (4 or 5) + */ +static void +process_ep_receive (struct usb_dev* dev, endpoint_t *ep) +{ + usbdev_pkt_t *pkt; + + spin_lock(&ep->lock); + pkt = receive_packet_complete(ep); + spin_unlock(&ep->lock); + + dev->func_cb(CB_PKT_COMPLETE, (unsigned long)pkt, dev->cb_data); +} + + + +/* This ISR handles the receive complete and suspend events */ +static void +req_sus_intr (int irq, void *dev_id, struct pt_regs *regs) +{ + struct usb_dev *dev = (struct usb_dev *) dev_id; + u32 status; + + status = au_readl(USBD_INTSTAT); + au_writel(status, USBD_INTSTAT); // ack'em + + if (status & (1<<0)) + process_ep0_receive(dev); + if (status & (1<<4)) + process_ep_receive(dev, &dev->ep[4]); + if (status & (1<<5)) + process_ep_receive(dev, &dev->ep[5]); +} + + +/* This ISR handles the DMA done events on EP0 */ +static void +dma_done_ep0_intr(int irq, void *dev_id, struct pt_regs *regs) +{ + struct usb_dev *dev = (struct usb_dev *) dev_id; + usbdev_pkt_t* pkt; + endpoint_t *ep0 = &dev->ep[0]; + u32 cs0, buff_done; + + spin_lock(&ep0->lock); + cs0 = au_readl(ep0->reg->ctrl_stat); + + // first check packet transmit done + if ((buff_done = get_dma_buffer_done(ep0->indma)) != 0) { + // transmitted a DATAx packet during DATA stage + // on control endpoint 0 + // clear DMA done bit + if (buff_done & DMA_D0) + clear_dma_done0(ep0->indma); + if (buff_done & DMA_D1) + clear_dma_done1(ep0->indma); + + pkt = send_packet_complete(ep0); + if (pkt) + kfree(pkt); + } + + /* + * Now check packet receive done. Shouldn't get these, + * the receive packet complete intr should happen + * before the DMA done intr occurs. + */ + if ((buff_done = get_dma_buffer_done(ep0->outdma)) != 0) { + // clear DMA done bit + if (buff_done & DMA_D0) + clear_dma_done0(ep0->outdma); + if (buff_done & DMA_D1) + clear_dma_done1(ep0->outdma); + + //process_ep0_receive(dev); + } + + spin_unlock(&ep0->lock); +} + +/* This ISR handles the DMA done events on endpoints 2,3,4,5 */ +static void +dma_done_ep_intr(int irq, void *dev_id, struct pt_regs *regs) +{ + struct usb_dev *dev = (struct usb_dev *) dev_id; + int i; + + for (i = 2; i < 6; i++) { + u32 buff_done; + usbdev_pkt_t* pkt; + endpoint_t *ep = &dev->ep[i]; + + if (!ep->active) continue; + + spin_lock(&ep->lock); + + if (ep->direction == USB_DIR_IN) { + buff_done = get_dma_buffer_done(ep->indma); + if (buff_done != 0) { + // transmitted a DATAx pkt on the IN ep + // clear DMA done bit + if (buff_done & DMA_D0) + clear_dma_done0(ep->indma); + if (buff_done & DMA_D1) + clear_dma_done1(ep->indma); + + pkt = send_packet_complete(ep); + + spin_unlock(&ep->lock); + dev->func_cb(CB_PKT_COMPLETE, + (unsigned long)pkt, + dev->cb_data); + spin_lock(&ep->lock); + } + } else { + /* + * Check packet receive done (OUT ep). Shouldn't get + * these, the rx packet complete intr should happen + * before the DMA done intr occurs. + */ + buff_done = get_dma_buffer_done(ep->outdma); + if (buff_done != 0) { + // received a DATAx pkt on the OUT ep + // clear DMA done bit + if (buff_done & DMA_D0) + clear_dma_done0(ep->outdma); + if (buff_done & DMA_D1) + clear_dma_done1(ep->outdma); + + //process_ep_receive(dev, ep); + } + } + + spin_unlock(&ep->lock); + } +} + + +/*************************************************************************** + * Here begins the external interface functions + *************************************************************************** + */ + +/* + * allocate a new packet + */ +int +usbdev_alloc_packet(int ep_addr, int data_size, usbdev_pkt_t** pkt) +{ + endpoint_t * ep = epaddr_to_ep(&usbdev, ep_addr); + usbdev_pkt_t* lpkt = NULL; + + if (!ep || !ep->active || ep->address < 2) + return -ENODEV; + if (data_size > ep->max_pkt_size) + return -EINVAL; + + lpkt = *pkt = alloc_packet(ep, data_size, NULL); + if (!lpkt) + return -ENOMEM; + return 0; +} + + +/* + * packet send + */ +int +usbdev_send_packet(int ep_addr, usbdev_pkt_t * pkt) +{ + unsigned long flags; + int count; + endpoint_t * ep; + + if (!pkt || !(ep = epaddr_to_ep(&usbdev, pkt->ep_addr)) || + !ep->active || ep->address < 2) + return -ENODEV; + if (ep->direction != USB_DIR_IN) + return -EINVAL; + + spin_lock_irqsave(&ep->lock, flags); + count = send_packet(&usbdev, pkt, 1); + spin_unlock_irqrestore(&ep->lock, flags); + + return count; +} + +/* + * packet receive + */ +int +usbdev_receive_packet(int ep_addr, usbdev_pkt_t** pkt) +{ + unsigned long flags; + usbdev_pkt_t* lpkt = NULL; + endpoint_t *ep = epaddr_to_ep(&usbdev, ep_addr); + + if (!ep || !ep->active || ep->address < 2) + return -ENODEV; + if (ep->direction != USB_DIR_OUT) + return -EINVAL; + + spin_lock_irqsave(&ep->lock, flags); + if (ep->outlist.count > 1) + lpkt = unlink_head(&ep->outlist); + spin_unlock_irqrestore(&ep->lock, flags); + + if (!lpkt) { + /* no packet available */ + *pkt = NULL; + return -ENODATA; + } + + *pkt = lpkt; + + return lpkt->size; +} + + +/* + * return total queued byte count on the endpoint. + */ +int +usbdev_get_byte_count(int ep_addr) +{ + unsigned long flags; + pkt_list_t *list; + usbdev_pkt_t *scan; + int count = 0; + endpoint_t * ep = epaddr_to_ep(&usbdev, ep_addr); + + if (!ep || !ep->active || ep->address < 2) + return -ENODEV; + + if (ep->direction == USB_DIR_IN) { + list = &ep->inlist; + + spin_lock_irqsave(&ep->lock, flags); + for (scan = list->head; scan; scan = scan->next) + count += scan->size; + spin_unlock_irqrestore(&ep->lock, flags); + } else { + list = &ep->outlist; + + spin_lock_irqsave(&ep->lock, flags); + if (list->count > 1) { + for (scan = list->head; scan != list->tail; + scan = scan->next) + count += scan->size; + } + spin_unlock_irqrestore(&ep->lock, flags); + } + + return count; +} + + +void +usbdev_exit(void) +{ + endpoint_t *ep; + int i; + + au_writel(0, USBD_INTEN); // disable usb dev ints + au_writel(0, USBD_ENABLE); // disable usb dev + + free_irq(AU1000_USB_DEV_REQ_INT, &usbdev); + free_irq(AU1000_USB_DEV_SUS_INT, &usbdev); + + // free all control endpoint resources + ep = &usbdev.ep[0]; + free_au1000_dma(ep->indma); + free_au1000_dma(ep->outdma); + endpoint_flush(ep); + + // free ep resources + for (i = 2; i < 6; i++) { + ep = &usbdev.ep[i]; + if (!ep->active) continue; + + if (ep->direction == USB_DIR_IN) { + free_au1000_dma(ep->indma); + } else { + free_au1000_dma(ep->outdma); + } + endpoint_flush(ep); + } + + if (usbdev.full_conf_desc) + kfree(usbdev.full_conf_desc); +} + +int +usbdev_init(struct usb_device_descriptor* dev_desc, + struct usb_config_descriptor* config_desc, + struct usb_interface_descriptor* if_desc, + struct usb_endpoint_descriptor* ep_desc, + struct usb_string_descriptor* str_desc[], + void (*cb)(usbdev_cb_type_t, unsigned long, void *), + void* cb_data) +{ + endpoint_t *ep0; + int i, ret=0; + u8* fcd; + + if (dev_desc->bNumConfigurations > 1 || + config_desc->bNumInterfaces > 1 || + if_desc->bNumEndpoints > 4) { + err("Only one config, one i/f, and no more " + "than 4 ep's allowed"); + ret = -EINVAL; + goto out; + } + + if (!cb) { + err("Function-layer callback required"); + ret = -EINVAL; + goto out; + } + + if (dev_desc->bMaxPacketSize0 != USBDEV_EP0_MAX_PACKET_SIZE) { + warn("EP0 Max Packet size must be %d", + USBDEV_EP0_MAX_PACKET_SIZE); + dev_desc->bMaxPacketSize0 = USBDEV_EP0_MAX_PACKET_SIZE; + } + + memset(&usbdev, 0, sizeof(struct usb_dev)); + + usbdev.state = DEFAULT; + usbdev.dev_desc = dev_desc; + usbdev.if_desc = if_desc; + usbdev.conf_desc = config_desc; + for (i=0; i<6; i++) + usbdev.str_desc[i] = str_desc[i]; + usbdev.func_cb = cb; + usbdev.cb_data = cb_data; + + /* Initialize default control endpoint */ + ep0 = &usbdev.ep[0]; + ep0->active = 1; + ep0->type = CONTROL_EP; + ep0->max_pkt_size = USBDEV_EP0_MAX_PACKET_SIZE; + spin_lock_init(&ep0->lock); + ep0->desc = NULL; // ep0 has no descriptor + ep0->address = 0; + ep0->direction = 0; + ep0->reg = &ep_reg[0]; + + /* Initialize the other requested endpoints */ + for (i = 0; i < if_desc->bNumEndpoints; i++) { + struct usb_endpoint_descriptor* epd = &ep_desc[i]; + endpoint_t *ep; + + if ((epd->bEndpointAddress & 0x80) == USB_DIR_IN) { + ep = &usbdev.ep[2]; + ep->address = 2; + if (ep->active) { + ep = &usbdev.ep[3]; + ep->address = 3; + if (ep->active) { + err("too many IN ep's requested"); + ret = -ENODEV; + goto out; + } + } + } else { + ep = &usbdev.ep[4]; + ep->address = 4; + if (ep->active) { + ep = &usbdev.ep[5]; + ep->address = 5; + if (ep->active) { + err("too many OUT ep's requested"); + ret = -ENODEV; + goto out; + } + } + } + + ep->active = 1; + epd->bEndpointAddress &= ~0x0f; + epd->bEndpointAddress |= (u8)ep->address; + ep->direction = epd->bEndpointAddress & 0x80; + ep->type = epd->bmAttributes & 0x03; + ep->max_pkt_size = epd->wMaxPacketSize; + spin_lock_init(&ep->lock); + ep->desc = epd; + ep->reg = &ep_reg[ep->address]; + } + + /* + * initialize the full config descriptor + */ + usbdev.full_conf_desc = fcd = kmalloc(config_desc->wTotalLength, + ALLOC_FLAGS); + if (!fcd) { + err("failed to alloc full config descriptor"); + ret = -ENOMEM; + goto out; + } + + memcpy(fcd, config_desc, USB_DT_CONFIG_SIZE); + fcd += USB_DT_CONFIG_SIZE; + memcpy(fcd, if_desc, USB_DT_INTERFACE_SIZE); + fcd += USB_DT_INTERFACE_SIZE; + for (i = 0; i < if_desc->bNumEndpoints; i++) { + memcpy(fcd, &ep_desc[i], USB_DT_ENDPOINT_SIZE); + fcd += USB_DT_ENDPOINT_SIZE; + } + + /* Now we're ready to enable the controller */ + au_writel(0x0002, USBD_ENABLE); + udelay(100); + au_writel(0x0003, USBD_ENABLE); + udelay(100); + + /* build and send config table based on ep descriptors */ + for (i = 0; i < 6; i++) { + endpoint_t *ep; + if (i == 1) + continue; // skip dummy ep + ep = &usbdev.ep[i]; + if (ep->active) { + au_writel((ep->address << 4) | 0x04, USBD_CONFIG); + au_writel(((ep->max_pkt_size & 0x380) >> 7) | + (ep->direction >> 4) | (ep->type << 4), + USBD_CONFIG); + au_writel((ep->max_pkt_size & 0x7f) << 1, USBD_CONFIG); + au_writel(0x00, USBD_CONFIG); + au_writel(ep->address, USBD_CONFIG); + } else { + u8 dir = (i==2 || i==3) ? DIR_IN : DIR_OUT; + au_writel((i << 4) | 0x04, USBD_CONFIG); + au_writel(((16 & 0x380) >> 7) | dir | + (BULK_EP << 4), USBD_CONFIG); + au_writel((16 & 0x7f) << 1, USBD_CONFIG); + au_writel(0x00, USBD_CONFIG); + au_writel(i, USBD_CONFIG); + } + } + + /* + * Enable Receive FIFO Complete interrupts only. Transmit + * complete is being handled by the DMA done interrupts. + */ + au_writel(0x31, USBD_INTEN); + + /* + * Controller is now enabled, request DMA and IRQ + * resources. + */ + + /* request the USB device transfer complete interrupt */ + if (request_irq(AU1000_USB_DEV_REQ_INT, req_sus_intr, SA_INTERRUPT, + "USBdev req", &usbdev)) { + err("Can't get device request intr"); + ret = -ENXIO; + goto out; + } + /* request the USB device suspend interrupt */ + if (request_irq(AU1000_USB_DEV_SUS_INT, req_sus_intr, SA_INTERRUPT, + "USBdev sus", &usbdev)) { + err("Can't get device suspend intr"); + ret = -ENXIO; + goto out; + } + + /* Request EP0 DMA and IRQ */ + if ((ep0->indma = request_au1000_dma(ep_dma_id[0].id, + ep_dma_id[0].str, + dma_done_ep0_intr, + SA_INTERRUPT, + &usbdev)) < 0) { + err("Can't get %s DMA", ep_dma_id[0].str); + ret = -ENXIO; + goto out; + } + if ((ep0->outdma = request_au1000_dma(ep_dma_id[1].id, + ep_dma_id[1].str, + NULL, 0, NULL)) < 0) { + err("Can't get %s DMA", ep_dma_id[1].str); + ret = -ENXIO; + goto out; + } + + // Flush the ep0 buffers and FIFOs + endpoint_flush(ep0); + // start packet reception on ep0 + kickstart_receive_packet(ep0); + + /* Request DMA and IRQ for the other endpoints */ + for (i = 2; i < 6; i++) { + endpoint_t *ep = &usbdev.ep[i]; + if (!ep->active) + continue; + + // Flush the endpoint buffers and FIFOs + endpoint_flush(ep); + + if (ep->direction == USB_DIR_IN) { + ep->indma = + request_au1000_dma(ep_dma_id[ep->address].id, + ep_dma_id[ep->address].str, + dma_done_ep_intr, + SA_INTERRUPT, + &usbdev); + if (ep->indma < 0) { + err("Can't get %s DMA", + ep_dma_id[ep->address].str); + ret = -ENXIO; + goto out; + } + } else { + ep->outdma = + request_au1000_dma(ep_dma_id[ep->address].id, + ep_dma_id[ep->address].str, + NULL, 0, NULL); + if (ep->outdma < 0) { + err("Can't get %s DMA", + ep_dma_id[ep->address].str); + ret = -ENXIO; + goto out; + } + + // start packet reception on OUT endpoint + kickstart_receive_packet(ep); + } + } + + out: + if (ret) + usbdev_exit(); + return ret; +} + +EXPORT_SYMBOL(usbdev_init); +EXPORT_SYMBOL(usbdev_exit); +EXPORT_SYMBOL(usbdev_alloc_packet); +EXPORT_SYMBOL(usbdev_receive_packet); +EXPORT_SYMBOL(usbdev_send_packet); +EXPORT_SYMBOL(usbdev_get_byte_count); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/au1000/db1x00/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,73 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * PB1000 board setup + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int prom_argc; +char **prom_argv, **prom_envp; +extern void __init prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "Alchemy Db1000"; +} + +int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = argc; + prom_argv = argv; + prom_envp = envp; + + mips_machgroup = MACH_GROUP_ALCHEMY; + mips_machtype = MACH_DB1000; /* set the platform # */ + prom_init_cmdline(); + + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + memsize = 0x04000000; + } else { + memsize = simple_strtol(memsize_str, NULL, 0); + } + add_memory_region(0, memsize, BOOT_MEM_RAM); + return 0; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/au1000/db1x00/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,20 @@ +# +# Copyright 2000 MontaVista Software Inc. +# Author: MontaVista Software, Inc. +# ppopov@mvista.com or source@mvista.com +# +# Makefile for the Alchemy Semiconductor PB1000 board. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +.S.s: + $(CPP) $(CFLAGS) $< -o $*.s +.S.o: + $(CC) $(CFLAGS) -c $< -o $*.o + +O_TARGET := db1x00.o + +obj-y := init.o setup.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/au1000/db1x00/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,230 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Alchemy Db1000 board setup. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_BLK_DEV_INITRD +extern unsigned long initrd_start, initrd_end; +extern void * __rd_start, * __rd_end; +#endif + +#ifdef CONFIG_BLK_DEV_IDE +extern struct ide_ops std_ide_ops; +extern struct ide_ops *ide_ops; +#endif + +extern struct rtc_ops no_rtc_ops; +extern char * __init prom_getcmdline(void); +extern void au1000_restart(char *); +extern void au1000_halt(void); +extern void au1000_power_off(void); +extern struct resource ioport_resource; +extern struct resource iomem_resource; +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_SOC_AU1500) +extern phys_t (*fixup_bigphys_addr)(phys_t phys_addr, phys_t size); +static phys_t db_fixup_bigphys_addr(phys_t phys_addr, phys_t size); +#endif + +void __init au1x00_setup(void) +{ + char *argptr; + u32 pin_func, static_cfg0; + u32 sys_freqctrl, sys_clksrc; + u32 prid = read_c0_prid(); + + argptr = prom_getcmdline(); + + /* Various early Au1000 Errata corrected by this */ + set_c0_config(1<<19); /* Config[OD] */ + +#ifdef CONFIG_AU1X00_SERIAL_CONSOLE + if ((argptr = strstr(argptr, "console=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " console=ttyS0,115200"); + } +#endif + +#ifdef CONFIG_FB_AU1100 + if ((argptr = strstr(argptr, "video=")) == NULL) { + argptr = prom_getcmdline(); + /* default panel */ + //strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16"); + strcat(argptr, " video=au1100fb:panel:s10,nohwcursor"); + } +#endif + +#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) + // au1000 does not support vra, au1500 and au1100 do + strcat(argptr, " au1000_audio=vra"); + argptr = prom_getcmdline(); +#endif + + rtc_ops = &no_rtc_ops; + _machine_restart = au1000_restart; + _machine_halt = au1000_halt; + _machine_power_off = au1000_power_off; +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_SOC_AU1500) + fixup_bigphys_addr = db_fixup_bigphys_addr; +#endif + + // IO/MEM resources. + set_io_port_base(0); +#ifdef CONFIG_SOC_AU1500 + ioport_resource.start = 0x00000000; +#else + /* don't allow any legacy ports probing */ + ioport_resource.start = 0x10000000; +#endif + ioport_resource.end = 0xffffffff; + iomem_resource.start = 0x10000000; + iomem_resource.end = 0xffffffff; + +#ifdef CONFIG_BLK_DEV_INITRD + ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; +#endif + + // + // NOTE: + // + // YAMON (specifically reset_db1500.s) enables 32khz osc + // YAMON (specifically reset_db1x00.s) setups all clocking and GPIOs + // YAMON (specifically reset_db1500.s) setups all PCI + // + +#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) +#ifdef CONFIG_USB_OHCI + if ((argptr = strstr(argptr, "usb_ohci=")) == NULL) { + char usb_args[80]; + argptr = prom_getcmdline(); + memset(usb_args, 0, sizeof(usb_args)); + sprintf(usb_args, " usb_ohci=base:0x%x,len:0x%x,irq:%d", + USB_OHCI_BASE, USB_OHCI_LEN, AU1000_USB_HOST_INT); + strcat(argptr, usb_args); + } +#endif + +#ifdef CONFIG_USB_OHCI + // enable host controller and wait for reset done + au_writel(0x08, USB_HOST_CONFIG); + udelay(1000); + au_writel(0x0E, USB_HOST_CONFIG); + udelay(1000); + au_readl(USB_HOST_CONFIG); // throw away first read + while (!(au_readl(USB_HOST_CONFIG) & 0x10)) + au_readl(USB_HOST_CONFIG); +#endif + +#ifdef CONFIG_AU1X00_USB_DEVICE + // 2nd USB port is USB device + pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000); + au_writel(pin_func, SYS_PINFUNC); +#endif + +#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) + +#ifdef CONFIG_FB + // Needed if PCI video card in use + conswitchp = &dummy_con; +#endif + +#ifndef CONFIG_SERIAL_NONSTANDARD + /* don't touch the default serial console */ + au_writel(0, UART_ADDR + UART_CLK); +#endif + //au_writel(0, UART3_ADDR + UART_CLK); + +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &std_ide_ops; +#endif + +#if 0 + //// FIX!!! must be valid for au1000, au1500 and au1100 + /* Enable Au1000 BCLK switching */ + switch (prid & 0x000000FF) + { + case 0x00: /* DA */ + case 0x01: /* HA */ + case 0x02: /* HB */ + break; + default: /* HC and newer */ + au_writel(0x00000060, 0xb190003c); + break; + } +#endif + + au_writel(0, 0xAE000010); /* turn off pcmcia power */ + +#ifdef CONFIG_MIPS_DB1000 + printk("AMD Alchemy Au1000/Db1000 Board\n"); +#endif +#ifdef CONFIG_MIPS_DB1500 + printk("AMD Alchemy Au1500/Db1500 Board\n"); +#endif +#ifdef CONFIG_MIPS_DB1100 + printk("AMD Alchemy Au1100/Db1100 Board\n"); +#endif +} + +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_SOC_AU1500) +static phys_t db_fixup_bigphys_addr(phys_t phys_addr, phys_t size) +{ + u32 pci_start = (u32)Au1500_PCI_MEM_START; + u32 pci_end = (u32)Au1500_PCI_MEM_END; + + /* Don't fixup 36 bit addresses */ + if ((phys_addr >> 32) != 0) return phys_addr; + + /* check for pci memory window */ + if ((phys_addr >= pci_start) && ((phys_addr + size) < pci_end)) { + return (phys_t)((phys_addr - pci_start) + + Au1500_PCI_MEM_START); + } + else + return phys_addr; +} +#endif --- linux-2.5.73/arch/mips/au1000/pb1000/init.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/au1000/pb1000/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -33,27 +33,39 @@ #include #include #include -#include #include #include #include -extern int prom_argc; -extern char **prom_argv, **prom_envp; +int prom_argc; +char **prom_argv, **prom_envp; extern void __init prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "Alchemy Pb1000"; +} int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) { + unsigned char *memsize_str; + unsigned long memsize; + prom_argc = argc; prom_argv = argv; prom_envp = envp; mips_machgroup = MACH_GROUP_ALCHEMY; - mips_machtype = MACH_PB1000; + mips_machtype = MACH_PB1000; prom_init_cmdline(); - - add_memory_region(1, 64 << 20, BOOT_MEM_RAM); - + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + memsize = 0x04000000; + } else { + memsize = simple_strtol(memsize_str, NULL, 0); + } + add_memory_region(0, memsize, BOOT_MEM_RAM); return 0; } --- linux-2.5.73/arch/mips/au1000/pb1000/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/au1000/pb1000/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -5,5 +5,13 @@ # # Makefile for the Alchemy Semiconductor PB1000 board. # +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +USE_STANDARD_AS_RULE := true + +O_TARGET := pb1000.o obj-y := init.o setup.o --- linux-2.5.73/arch/mips/au1000/pb1000/setup.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/au1000/pb1000/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,7 +1,7 @@ /* * * BRIEF MODULE DESCRIPTION - * Au1000-based board setup. + * Alchemy Pb1000 board setup. * * Copyright 2000 MontaVista Software Inc. * Author: MontaVista Software, Inc. @@ -31,88 +31,271 @@ #include #include #include +#include #include #include +#include +#include #include +#include #include #include #include #include #include +#include #include +#include -#if defined(CONFIG_AU1000_SERIAL_CONSOLE) -extern void console_setup(char *, int *); +#ifdef CONFIG_USB_OHCI +// Enable the workaround for the OHCI DoneHead +// register corruption problem. +#define CONFIG_AU1000_OHCI_FIX +#endif + +#if defined(CONFIG_AU1X00_SERIAL_CONSOLE) char serial_console[20]; #endif -void (*__wbflush) (void); +#ifdef CONFIG_BLK_DEV_INITRD +extern unsigned long initrd_start, initrd_end; +extern void * __rd_start, * __rd_end; +#endif + +#ifdef CONFIG_BLK_DEV_IDE +extern struct ide_ops std_ide_ops; +extern struct ide_ops *ide_ops; +#endif + extern struct rtc_ops no_rtc_ops; extern char * __init prom_getcmdline(void); -extern void au1000_restart(void); +extern void au1000_restart(char *); extern void au1000_halt(void); extern void au1000_power_off(void); +extern struct resource ioport_resource; +extern struct resource iomem_resource; -struct { - struct resource ram; - struct resource io; - struct resource sram; - struct resource flash; - struct resource boot; - struct resource pcmcia; - struct resource lcd; -} au1000_resources = { - { "RAM", 0, 0x3FFFFFF, IORESOURCE_MEM }, - { "I/O", 0x10000000, 0x119FFFFF }, - { "SRAM", 0x1e000000, 0x1E03FFFF }, - { "System Flash", 0x1F800000, 0x1FBFFFFF }, - { "Boot ROM", 0x1FC00000, 0x1FFFFFFF }, - { "PCMCIA", 0x20000000, 0x27FFFFFF }, - { "LCD", 0x60000000, 0x603FFFFF }, -}; - -void au1000_wbflush(void) -{ - __asm__ volatile ("sync"); -} - -void __init au1000_setup(void) +void __init au1x00_setup(void) { char *argptr; + u32 pin_func, static_cfg0; + u32 sys_freqctrl, sys_clksrc; + u32 prid = read_c0_prid(); argptr = prom_getcmdline(); -#ifdef CONFIG_AU1000_SERIAL_CONSOLE - if ((argptr = strstr(argptr, "console=ttyS0")) == NULL) { + /* Various early Au1000 Errata corrected by this */ + set_c0_config(1<<19); /* Config[OD] */ + +#ifdef CONFIG_AU1X00_SERIAL_CONSOLE + if ((argptr = strstr(argptr, "console=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " console=ttyS0,115200"); } -#endif +#endif - //set_cp0_status(ST0_FR,0); rtc_ops = &no_rtc_ops; - __wbflush = au1000_wbflush; _machine_restart = au1000_restart; _machine_halt = au1000_halt; _machine_power_off = au1000_power_off; - /* - * IO/MEM resources. - */ - mips_io_port_base = KSEG1; - ioport_resource.start = au1000_resources.io.start; - ioport_resource.end = au1000_resources.lcd.end; + // IO/MEM resources. + set_io_port_base(0); + ioport_resource.start = 0x10000000; + ioport_resource.end = 0xffffffff; + iomem_resource.start = 0x10000000; + iomem_resource.end = 0xffffffff; #ifdef CONFIG_BLK_DEV_INITRD ROOT_DEV = Root_RAM0; + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; #endif - outl(PC_CNTRL_E0 | PC_CNTRL_EN0 | PC_CNTRL_EN0, PC_COUNTER_CNTRL); - while (inl(PC_COUNTER_CNTRL) & PC_CNTRL_T0S); - outl(0x8000-1, PC0_TRIM); + // set AUX clock to 12MHz * 8 = 96 MHz + au_writel(8, SYS_AUXPLL); + au_writel(0, SYS_PINSTATERD); + udelay(100); + +#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) +#ifdef CONFIG_USB_OHCI + if ((argptr = strstr(argptr, "usb_ohci=")) == NULL) { + char usb_args[80]; + argptr = prom_getcmdline(); + memset(usb_args, 0, sizeof(usb_args)); + sprintf(usb_args, " usb_ohci=base:0x%x,len:0x%x,irq:%d", + USB_OHCI_BASE, USB_OHCI_LEN, AU1000_USB_HOST_INT); + strcat(argptr, usb_args); + } +#endif - printk("Alchemy Semi PB1000 Board\n"); - printk("Au1000/PB1000 port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n"); -} + /* zero and disable FREQ2 */ + sys_freqctrl = au_readl(SYS_FREQCTRL0); + sys_freqctrl &= ~0xFFF00000; + au_writel(sys_freqctrl, SYS_FREQCTRL0); + + /* zero and disable USBH/USBD clocks */ + sys_clksrc = au_readl(SYS_CLKSRC); + sys_clksrc &= ~0x00007FE0; + au_writel(sys_clksrc, SYS_CLKSRC); + + sys_freqctrl = au_readl(SYS_FREQCTRL0); + sys_freqctrl &= ~0xFFF00000; + + sys_clksrc = au_readl(SYS_CLKSRC); + sys_clksrc &= ~0x00007FE0; + + switch (prid & 0x000000FF) + { + case 0x00: /* DA */ + case 0x01: /* HA */ + case 0x02: /* HB */ + /* CPU core freq to 48MHz to slow it way down... */ + au_writel(4, SYS_CPUPLL); + + /* + * Setup 48MHz FREQ2 from CPUPLL for USB Host + */ + /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */ + sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20)); + au_writel(sys_freqctrl, SYS_FREQCTRL0); + + /* CPU core freq to 384MHz */ + au_writel(0x20, SYS_CPUPLL); + + printk("Au1000: 48MHz OHCI workaround enabled\n"); + break; + + default: /* HC and newer */ + // FREQ2 = aux/2 = 48 MHz + sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20)); + au_writel(sys_freqctrl, SYS_FREQCTRL0); + break; + } + + /* + * Route 48MHz FREQ2 into USB Host and/or Device + */ +#ifdef CONFIG_USB_OHCI + sys_clksrc |= ((4<<12) | (0<<11) | (0<<10)); +#endif +#ifdef CONFIG_AU1X00_USB_DEVICE + sys_clksrc |= ((4<<7) | (0<<6) | (0<<5)); +#endif + au_writel(sys_clksrc, SYS_CLKSRC); +#ifdef CONFIG_USB_OHCI + // enable host controller and wait for reset done + au_writel(0x08, USB_HOST_CONFIG); + udelay(1000); + au_writel(0x0E, USB_HOST_CONFIG); + udelay(1000); + au_readl(USB_HOST_CONFIG); // throw away first read + while (!(au_readl(USB_HOST_CONFIG) & 0x10)) + au_readl(USB_HOST_CONFIG); +#endif + + // configure pins GPIO[14:9] as GPIO + pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080); + +#ifndef CONFIG_AU1X00_USB_DEVICE + // 2nd USB port is USB host + pin_func |= 0x8000; +#endif + au_writel(pin_func, SYS_PINFUNC); + au_writel(0x2800, SYS_TRIOUTCLR); + au_writel(0x0030, SYS_OUTPUTCLR); +#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) + + // make gpio 15 an input (for interrupt line) + pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100); + // we don't need I2S, so make it available for GPIO[31:29] + pin_func |= (1<<5); + au_writel(pin_func, SYS_PINFUNC); + + au_writel(0x8000, SYS_TRIOUTCLR); + +#ifdef CONFIG_FB + conswitchp = &dummy_con; +#endif + + static_cfg0 = au_readl(MEM_STCFG0) & (u32)(~0xc00); + au_writel(static_cfg0, MEM_STCFG0); + + // configure RCE2* for LCD + au_writel(0x00000004, MEM_STCFG2); + + // MEM_STTIME2 + au_writel(0x09000000, MEM_STTIME2); + + // Set 32-bit base address decoding for RCE2* + au_writel(0x10003ff0, MEM_STADDR2); + + // PCI CPLD setup + // expand CE0 to cover PCI + au_writel(0x11803e40, MEM_STADDR1); + + // burst visibility on + au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0); + + au_writel(0x83, MEM_STCFG1); // ewait enabled, flash timing + au_writel(0x33030a10, MEM_STTIME1); // slower timing for FPGA + + /* setup the static bus controller */ + au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */ + au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */ + au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */ + +#ifdef CONFIG_FB_E1356 + if ((argptr = strstr(argptr, "video=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " video=e1356fb:system:pb1000,mmunalign:1"); + } +#endif // CONFIG_FB_E1356 + + +#ifdef CONFIG_PCI + au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0 + au_writel(0, SDRAM_MBAR); // set mbar to 0 + au_writel(0x2, SDRAM_CMD); // enable memory accesses + au_sync_delay(1); +#endif + +#ifndef CONFIG_SERIAL_NONSTANDARD + /* don't touch the default serial console */ + au_writel(0, UART0_ADDR + UART_CLK); +#endif + au_writel(0, UART1_ADDR + UART_CLK); + au_writel(0, UART2_ADDR + UART_CLK); + au_writel(0, UART3_ADDR + UART_CLK); + +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &std_ide_ops; +#endif + + // setup irda clocks + // aux clock, divide by 2, clock from 2/4 divider + au_writel(au_readl(SYS_CLKSRC) | 0x7, SYS_CLKSRC); + pin_func = au_readl(SYS_PINFUNC) & (u32)(~(1<<2)); // clear IRTXD + au_writel(pin_func, SYS_PINFUNC); + + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S); + au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL); + au_sync(); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); + au_writel(0, SYS_TOYTRIM); + + /* Enable Au1000 BCLK switching - note: sed1356 must not use + * its BCLK (Au1000 LCLK) for any timings */ + switch (prid & 0x000000FF) + { + case 0x00: /* DA */ + case 0x01: /* HA */ + case 0x02: /* HB */ + break; + default: /* HC and newer */ + au_writel(0x00000060, 0xb190003c); + break; + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/au1000/pb1100/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,73 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Pb1100 board setup + * + * Copyright 2002 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int prom_argc; +char **prom_argv, **prom_envp; +extern void __init prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "Alchemy Pb1100"; +} + +int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = argc; + prom_argv = argv; + prom_envp = envp; + + mips_machgroup = MACH_GROUP_ALCHEMY; + mips_machtype = MACH_PB1100; + + prom_init_cmdline(); + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + memsize = 0x04000000; + } else { + memsize = simple_strtol(memsize_str, NULL, 0); + } + add_memory_region(0, memsize, BOOT_MEM_RAM); + return 0; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/au1000/pb1100/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,17 @@ +# +# Copyright 2000,2001 MontaVista Software Inc. +# Author: MontaVista Software, Inc. +# ppopov@mvista.com or source@mvista.com +# +# Makefile for the Alchemy Semiconductor Pb1100 board. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +USE_STANDARD_AS_RULE := true + +O_TARGET := pb1100.o + +obj-y := init.o setup.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/au1000/pb1100/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,248 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Alchemy Pb1100 board setup. + * + * Copyright 2002 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_USB_OHCI +// Enable the workaround for the OHCI DoneHead +// register corruption problem. +#define CONFIG_AU1000_OHCI_FIX +#endif + +#if defined(CONFIG_AU1X00_SERIAL_CONSOLE) +extern void console_setup(char *, int *); +char serial_console[20]; +#endif + +#ifdef CONFIG_BLK_DEV_INITRD +extern unsigned long initrd_start, initrd_end; +extern void * __rd_start, * __rd_end; +#endif + +#ifdef CONFIG_BLK_DEV_IDE +extern struct ide_ops std_ide_ops; +extern struct ide_ops *ide_ops; +#endif + +#ifdef CONFIG_RTC +extern struct rtc_ops pb1500_rtc_ops; +#endif + +extern char * __init prom_getcmdline(void); +extern void au1000_restart(char *); +extern void au1000_halt(void); +extern void au1000_power_off(void); +extern struct resource ioport_resource; +extern struct resource iomem_resource; + + +void __init au1x00_setup(void) +{ + char *argptr; + u32 pin_func, static_cfg0; + u32 sys_freqctrl, sys_clksrc; + + argptr = prom_getcmdline(); + + /* NOTE: The memory map is established by YAMON 2.08+ */ + + /* Various early Au1000 Errata corrected by this */ + set_c0_config(1<<19); /* Config[OD] */ + +#ifdef CONFIG_AU1X00_SERIAL_CONSOLE + if ((argptr = strstr(argptr, "console=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " console=ttyS0,115200"); + } +#endif + +#ifdef CONFIG_SOUND_AU1X00 + strcat(argptr, " au1000_audio=vra"); + argptr = prom_getcmdline(); +#endif + + _machine_restart = au1000_restart; + _machine_halt = au1000_halt; + _machine_power_off = au1000_power_off; + + // IO/MEM resources. + set_io_port_base(0); + ioport_resource.start = 0x10000000; + ioport_resource.end = 0xffffffff; + iomem_resource.start = 0x10000000; + iomem_resource.end = 0xffffffff; + +#ifdef CONFIG_BLK_DEV_INITRD + ROOT_DEV = Root_RAM0; + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; +#endif + + // set AUX clock to 12MHz * 8 = 96 MHz + au_writel(8, SYS_AUXPLL); + au_writel(0, SYS_PININPUTEN); + udelay(100); + +#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) +#ifdef CONFIG_USB_OHCI + if ((argptr = strstr(argptr, "usb_ohci=")) == NULL) { + char usb_args[80]; + argptr = prom_getcmdline(); + memset(usb_args, 0, sizeof(usb_args)); + sprintf(usb_args, " usb_ohci=base:0x%x,len:0x%x,irq:%d", + USB_OHCI_BASE, USB_OHCI_LEN, AU1000_USB_HOST_INT); + strcat(argptr, usb_args); + } +#endif + // configure pins GPIO[14:9] as GPIO + pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x80); + + /* zero and disable FREQ2 */ + sys_freqctrl = au_readl(SYS_FREQCTRL0); + sys_freqctrl &= ~0xFFF00000; + au_writel(sys_freqctrl, SYS_FREQCTRL0); + + /* zero and disable USBH/USBD/IrDA clock */ + sys_clksrc = au_readl(SYS_CLKSRC); + sys_clksrc &= ~0x0000001F; + au_writel(sys_clksrc, SYS_CLKSRC); + + sys_freqctrl = au_readl(SYS_FREQCTRL0); + sys_freqctrl &= ~0xFFF00000; + + sys_clksrc = au_readl(SYS_CLKSRC); + sys_clksrc &= ~0x0000001F; + + // FREQ2 = aux/2 = 48 MHz + sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20)); + au_writel(sys_freqctrl, SYS_FREQCTRL0); + + /* + * Route 48MHz FREQ2 into USBH/USBD/IrDA + */ + sys_clksrc |= ((4<<2) | (0<<1) | 0 ); + au_writel(sys_clksrc, SYS_CLKSRC); + + /* setup the static bus controller */ + au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */ + au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */ + au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */ + + // get USB Functionality pin state (device vs host drive pins) + pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000); +#ifndef CONFIG_AU1X00_USB_DEVICE + // 2nd USB port is USB host + pin_func |= 0x8000; +#endif + au_writel(pin_func, SYS_PINFUNC); +#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) + +#ifdef CONFIG_USB_OHCI + // enable host controller and wait for reset done + au_writel(0x08, USB_HOST_CONFIG); + udelay(1000); + au_writel(0x0c, USB_HOST_CONFIG); + udelay(1000); + au_readl(USB_HOST_CONFIG); + while (!(au_readl(USB_HOST_CONFIG) & 0x10)) + ; + au_readl(USB_HOST_CONFIG); +#endif + +#ifdef CONFIG_FB + conswitchp = &dummy_con; +#endif + +#ifdef CONFIG_FB_AU1100 + if ((argptr = strstr(argptr, "video=")) == NULL) { + argptr = prom_getcmdline(); + /* default panel */ + strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16"); + } +#endif + +#ifdef CONFIG_FB_E1356 + if ((argptr = strstr(argptr, "video=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " video=e1356fb:system:pb1500"); + } +#endif + +#ifndef CONFIG_SERIAL_NONSTANDARD + /* don't touch the default serial console */ + au_writel(0, UART0_ADDR + UART_CLK); +#endif + au_writel(0, UART1_ADDR + UART_CLK); + au_writel(0, UART3_ADDR + UART_CLK); + +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &std_ide_ops; +#endif + + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S); + au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL); + au_sync(); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); + au_writel(0, SYS_TOYTRIM); + + au_writel(0x00000060, 0xb190003c); + +#ifdef CONFIG_RTC + rtc_ops = &pb1500_rtc_ops; + // Enable the RTC if not already enabled + if (!(readb(0xac000028) & 0x20)) { + writeb(readb(0xac000028) | 0x20, 0xac000028); + au_sync(); + } + // Put the clock in BCD mode + if (readb(0xac00002C) & 0x4) { /* reg B */ + writeb(readb(0xac00002c) & ~0x4, 0xac00002c); + au_sync(); + } +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/au1000/pb1500/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,71 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * PB1500 board setup + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int prom_argc; +char **prom_argv, **prom_envp; +extern void __init prom_init_cmdline(void); +extern char *prom_getenv(char *envname); + +const char *get_system_type(void) +{ + return "Alchemy Pb1500"; +} + +int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = argc; + prom_argv = argv; + prom_envp = envp; + + mips_machgroup = MACH_GROUP_ALCHEMY; + mips_machtype = MACH_PB1500; + + prom_init_cmdline(); + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + memsize = 0x04000000; + } else { + memsize = simple_strtol(memsize_str, NULL, 0); + } + add_memory_region(0, memsize, BOOT_MEM_RAM); + return 0; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/au1000/pb1500/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,13 @@ +# +# Copyright 2000,2001 MontaVista Software Inc. +# Author: MontaVista Software, Inc. +# ppopov@mvista.com or source@mvista.com +# +# Makefile for the Alchemy Semiconductor Pb1500 board. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +lib-y := init.o setup.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/au1000/pb1500/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,293 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Alchemy Pb1000 board setup. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_USB_OHCI +// Enable the workaround for the OHCI DoneHead +// register corruption problem. +#define CONFIG_AU1000_OHCI_FIX +#endif + +#ifdef CONFIG_BLK_DEV_INITRD +extern unsigned long initrd_start, initrd_end; +extern void * __rd_start, * __rd_end; +#endif + +#ifdef CONFIG_BLK_DEV_IDE +extern struct ide_ops std_ide_ops; +extern struct ide_ops *ide_ops; +#endif + +#ifdef CONFIG_RTC +extern struct rtc_ops pb1500_rtc_ops; +#endif + +extern char * __init prom_getcmdline(void); +extern void __init au1x_time_init(void); +extern void __init au1x_timer_setup(struct irqaction *irq); +extern void au1000_restart(char *); +extern void au1000_halt(void); +extern void au1000_power_off(void); +extern struct resource ioport_resource; +extern struct resource iomem_resource; +#ifdef CONFIG_64BIT_PHYS_ADDR +extern phys_t (*fixup_bigphys_addr)(phys_t phys_addr, phys_t size); +static phys_t pb1500_fixup_bigphys_addr(phys_t phys_addr, phys_t size); +#endif + + +void __init au1x00_setup(void) +{ + char *argptr; + u32 pin_func, static_cfg0; + u32 sys_freqctrl, sys_clksrc; + + argptr = prom_getcmdline(); + + /* NOTE: The memory map is established by YAMON 2.08+ */ + + /* Various early Au1500 Errata corrected by this */ + set_c0_config(1<<19); /* Config[OD] */ + + board_time_init = au1x_time_init; + board_timer_setup = au1x_timer_setup; + +#ifdef CONFIG_SERIAL_AU1X00_CONSOLE + if ((argptr = strstr(argptr, "console=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " console=ttyS0,115200"); + } +#endif + +#ifdef CONFIG_SOUND_AU1X00 + strcat(argptr, " au1000_audio=vra"); + argptr = prom_getcmdline(); +#endif + + _machine_restart = au1000_restart; + _machine_halt = au1000_halt; + _machine_power_off = au1000_power_off; +#ifdef CONFIG_64BIT_PHYS_ADDR + fixup_bigphys_addr = pb1500_fixup_bigphys_addr; +#endif + + // IO/MEM resources. + set_io_port_base(0); + ioport_resource.start = 0x00000000; + ioport_resource.end = 0xffffffff; + iomem_resource.start = 0x10000000; + iomem_resource.end = 0xffffffff; + +#ifdef CONFIG_BLK_DEV_INITRD + ROOT_DEV = Root_RAM0; + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; +#endif + + // set AUX clock to 12MHz * 8 = 96 MHz + au_writel(8, SYS_AUXPLL); + au_writel(0, SYS_PINSTATERD); + udelay(100); + +#if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) +#ifdef CONFIG_USB_OHCI + if ((argptr = strstr(argptr, "usb_ohci=")) == NULL) { + char usb_args[80]; + argptr = prom_getcmdline(); + memset(usb_args, 0, sizeof(usb_args)); + sprintf(usb_args, " usb_ohci=base:0x%x,len:0x%x,irq:%d", + USB_OHCI_BASE, USB_OHCI_LEN, AU1000_USB_HOST_INT); + strcat(argptr, usb_args); + } +#endif + + /* GPIO201 is input for PCMCIA card detect */ + /* GPIO203 is input for PCMCIA interrupt request */ + au_writel(au_readl(GPIO2_DIR) & (u32)(~((1<<1)|(1<<3))), GPIO2_DIR); + + /* zero and disable FREQ2 */ + sys_freqctrl = au_readl(SYS_FREQCTRL0); + sys_freqctrl &= ~0xFFF00000; + au_writel(sys_freqctrl, SYS_FREQCTRL0); + + /* zero and disable USBH/USBD clocks */ + sys_clksrc = au_readl(SYS_CLKSRC); + sys_clksrc &= ~0x00007FE0; + au_writel(sys_clksrc, SYS_CLKSRC); + + sys_freqctrl = au_readl(SYS_FREQCTRL0); + sys_freqctrl &= ~0xFFF00000; + + sys_clksrc = au_readl(SYS_CLKSRC); + sys_clksrc &= ~0x00007FE0; + + // FREQ2 = aux/2 = 48 MHz + sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20)); + au_writel(sys_freqctrl, SYS_FREQCTRL0); + + /* + * Route 48MHz FREQ2 into USB Host and/or Device + */ +#ifdef CONFIG_USB_OHCI + sys_clksrc |= ((4<<12) | (0<<11) | (0<<10)); +#endif +#ifdef CONFIG_AU1X00_USB_DEVICE + sys_clksrc |= ((4<<7) | (0<<6) | (0<<5)); +#endif + au_writel(sys_clksrc, SYS_CLKSRC); + + + pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000); +#ifndef CONFIG_AU1X00_USB_DEVICE + // 2nd USB port is USB host + pin_func |= 0x8000; +#endif + au_writel(pin_func, SYS_PINFUNC); +#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) + + +#ifdef CONFIG_USB_OHCI + // enable host controller and wait for reset done + au_writel(0x08, USB_HOST_CONFIG); + udelay(1000); + au_writel(0x0c, USB_HOST_CONFIG); + udelay(1000); + au_readl(USB_HOST_CONFIG); + while (!(au_readl(USB_HOST_CONFIG) & 0x10)) + ; + au_readl(USB_HOST_CONFIG); +#endif + +#ifdef CONFIG_FB + conswitchp = &dummy_con; +#endif + +#ifdef CONFIG_FB_E1356 + if ((argptr = strstr(argptr, "video=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " video=e1356fb:system:pb1500"); + } +#elif defined (CONFIG_FB_XPERT98) + if ((argptr = strstr(argptr, "video=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " video=atyfb:1024x768-8@70"); + } +#endif // CONFIG_FB_E1356 + +#ifndef CONFIG_SERIAL_AU1X00_CONSOLE + /* don't touch the default serial console */ + au_writel(0, UART0_ADDR + UART_CLK); +#endif + au_writel(0, UART3_ADDR + UART_CLK); + +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &std_ide_ops; +#endif + +#ifdef CONFIG_PCI + // Setup PCI bus controller + au_writel(0, Au1500_PCI_CMEM); + au_writel(0x00003fff, Au1500_CFG_BASE); +#if defined(__MIPSEB__) + au_writel(0xf | (2<<6) | (1<<4), Au1500_PCI_CFG); +#else + au_writel(0xf, Au1500_PCI_CFG); +#endif + au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV); + au_writel(0, Au1500_PCI_MWBASE_REV_CCL); + au_writel(0x02a00356, Au1500_PCI_STATCMD); + au_writel(0x00003c04, Au1500_PCI_HDRTYPE); + au_writel(0x00000008, Au1500_PCI_MBAR); + au_sync(); +#endif + + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S); + au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL); + au_sync(); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); + au_writel(0, SYS_TOYTRIM); + + /* Enable BCLK switching */ + au_writel(0x00000060, 0xb190003c); + +#ifdef CONFIG_RTC + rtc_ops = &pb1500_rtc_ops; + // Enable the RTC if not already enabled + if (!(au_readl(0xac000028) & 0x20)) { + printk("enabling clock ...\n"); + au_writel((au_readl(0xac000028) | 0x20), 0xac000028); + } + // Put the clock in BCD mode + if (readl(0xac00002C) & 0x4) { /* reg B */ + au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c); + au_sync(); + } +#endif +} + +#ifdef CONFIG_64BIT_PHYS_ADDR +static phys_t pb1500_fixup_bigphys_addr(phys_t phys_addr, + phys_t size) +{ + u32 pci_start = (u32)Au1500_PCI_MEM_START; + u32 pci_end = (u32)Au1500_PCI_MEM_END; + + /* Don't fixup 36 bit addresses */ + if ((phys_addr >> 32) != 0) return phys_addr; + + /* check for pci memory window */ + if ((phys_addr >= pci_start) && ((phys_addr + size) < pci_end)) { + return (phys_t)((phys_addr - pci_start) + + Au1500_PCI_MEM_START); + } + else + return phys_addr; +} +#endif --- linux-2.5.73/arch/mips/baget/baget.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/baget/baget.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,5 +1,4 @@ -/* $Id: baget.c,v 1.1 1999/01/17 03:49:37 ralf Exp $ - * +/* * baget.c: Baget low level stuff * * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov @@ -21,7 +20,7 @@ * Following code is based on routines from 'mm/vmalloc.c' * Additional parameters ioaddr is needed to iterate across real I/O address. */ -static inline int alloc_area_pte(pte_t * pte, unsigned long address, +static inline int alloc_area_pte(pte_t * pte, unsigned long address, unsigned long size, unsigned long ioaddr) { unsigned long end; @@ -36,7 +35,7 @@ static inline int alloc_area_pte(pte_t * printk("kseg2_alloc_io: page already exists\n"); /* * For MIPS looks pretty to have transparent mapping - * for KSEG2 areas -- user can't access one, and no + * for KSEG2 areas -- user can't access one, and no * problems with virtual <--> physical translation. */ page = ioaddr & PAGE_MASK; @@ -50,7 +49,7 @@ static inline int alloc_area_pte(pte_t * return 0; } -static inline int alloc_area_pmd(pmd_t * pmd, unsigned long address, +static inline int alloc_area_pmd(pmd_t * pmd, unsigned long address, unsigned long size, unsigned long ioaddr) { unsigned long end; --- linux-2.5.73/arch/mips/baget/bagetIRQ.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/baget/bagetIRQ.S 2003-06-27 15:56:23.000000000 -0700 @@ -1,9 +1,8 @@ -/* $Id: bagetIRQ.S,v 1.1 1999/01/17 03:49:37 ralf Exp $ +/* * bagetIRQ.S: Interrupt exception dispatch code for Baget/MIPS * * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov */ - #include #include #include @@ -25,28 +24,28 @@ NESTED(bagetIRQ, PT_SIZE, sp) .set push .set noreorder jal a1 - .set pop - move a0, sp + .set pop + move a0, sp la a1, ret_from_irq jr a1 END(bagetIRQ) - + #define DBE_HANDLER 0x1C - + NESTED(try_read, PT_SIZE, sp) mfc0 t3, CP0_STATUS # save flags and CLI # disable interrupts li t0, KSEG2 - sltu t1, t0, a0 # Is it KSEG2 address ? - beqz t1, mapped # No - already mapped ! - - move t0, a0 + sltu t1, t0, a0 # Is it KSEG2 address ? + beqz t1, mapped # No - already mapped ! + + move t0, a0 ori t0, 0xfff xori t0, 0xfff # round address to page - ori t1, t0, 0xf00 # prepare EntryLo (N,V,D,G) + ori t1, t0, 0xf00 # prepare EntryLo (N,V,D,G) mfc0 t2, CP0_ENTRYHI # save ASID value mtc0 zero, CP0_INDEX @@ -57,15 +56,15 @@ NESTED(try_read, PT_SIZE, sp) tlbwi # ... and write ones nop nop - mtc0 t2, CP0_ENTRYHI - -mapped: + mtc0 t2, CP0_ENTRYHI + +mapped: la t0, exception_handlers lw t1, DBE_HANDLER(t0) # save real handler - la t2, dbe_handler + la t2, dbe_handler sw t2, DBE_HANDLER(t0) # set temporary local handler li v0, -1 # default (failure) value - + li t2, 1 beq t2, a1, 1f li t2, 2 @@ -81,13 +80,13 @@ mapped: b out 4: lw v0, (a0) # word - -out: + +out: sw t1, DBE_HANDLER(t0) # restore real handler mtc0 t3, CP0_STATUS # restore CPU flags - jr ra - -dbe_handler: + jr ra + +dbe_handler: li v0, -1 # mark our failure .set push .set noreorder --- linux-2.5.73/arch/mips/baget/balo.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/baget/balo.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,9 +1,7 @@ -/* $Id$ - * +/* * balo.c: BAget LOader * * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov - * */ #include #include @@ -18,7 +16,7 @@ static char *banner = "\nBaget Linux Loa static void mem_move (long *to, long *from, long size) { - while (size > 0) { + while (size > 0) { *to++ = *from++; size -= sizeof(long); } @@ -42,27 +40,29 @@ static volatile enum balo_state_enum { static __inline__ void reset_and_jump(int start, int mem_upper) { + unsigned long tmp; + __asm__ __volatile__( ".set\tnoreorder\n\t" ".set\tnoat\n\t" - "mfc0\t$1,$12\n\t" + "mfc0\t$1, $12\n\t" "nop\n\t" "nop\n\t" "nop\n\t" - "ori\t$1,$1,0xff00\n\t" - "xori\t$1,$1,0xff00\n\t" - "mtc0\t$1,$12\n\t" + "ori\t$1, $1, 0xff00\n\t" + "xori\t$1, $1, 0xff00\n\t" + "mtc0\t$1, $12\n\t" "nop\n\t" "nop\n\t" "nop\n\t" - "move\t$4,%1\n\t" - "jr\t%0\n\t" + "move\t%0, %2\n\t" + "jr\t%1\n\t" "nop\n\t" ".set\tat\n\t" - ".set\treorder" - : /* no outputs */ - :"Ir" (start), "Ir" (mem_upper) - :"$1", "$4", "memory"); + ".set\treorder" + : "=&r" (tmp) + : "Ir" (start), "Ir" (mem_upper) + : "memory"); } static void start_kernel(void) @@ -71,7 +71,7 @@ static void start_kernel(void) extern char _ramdisk_start, _ramdisk_end; outs( "Relocating Linux... " ); - mem_move((long*)KSEG0, (long*)&_vmlinux_start, + mem_move((long*)KSEG0, (long*)&_vmlinux_start, &_vmlinux_end-&_vmlinux_start); outs("done.\n"); @@ -86,7 +86,7 @@ static void start_kernel(void) outs("done.\n"); } - { + { extern void flush_cache_low(int isize, int dsize); flush_cache_low(256*1024,256*1024); } @@ -102,10 +102,10 @@ static void mem_probe(void) balo_state = MEM_PROBE; outs("RAM: <"); while(mem_limit < mem_limit_dbe) { - if (can_write(mem_limit) && *mem_limit != 0) + if (can_write(mem_limit) && *mem_limit != 0) break; /* cycle found */ outc('.'); - if (can_write(mem_limit)) + if (can_write(mem_limit)) *mem_limit = -1; /* mark */ mem_limit += 0x40000; } @@ -124,7 +124,7 @@ static void print_regs(void) } void int_handler(struct pt_regs *regs) -{ +{ switch (balo_state) { case BALO_INIT: balo_printf("\nBALO: trap in balo itself.\n"); @@ -162,7 +162,7 @@ static void mem_init(void) while(1) { *mem_limit_dbe; - if (can_write(mem_limit_dbe)) + if (can_write(mem_limit_dbe)) *mem_limit_dbe = 0; mem_limit_dbe += 0x40000; /* +1M */ @@ -174,7 +174,7 @@ void balo_entry(void) { extern void except_vec3_generic(void); - cli(); + cli(); outs(banner); memcpy((void *)(KSEG0 + 0x80), &except_vec3_generic, 0x80); mem_init(); --- linux-2.5.73/arch/mips/baget/balo_supp.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/baget/balo_supp.S 2003-06-27 15:56:23.000000000 -0700 @@ -1,18 +1,17 @@ -/* $Id: balo_supp.S,v 1.1 1999/01/17 03:49:38 ralf Exp $ +/* * balo_supp.S: BAget Loader supplement * * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov */ - #include #include #include #include #include - + .text .set mips1 - + /* General exception vector. */ NESTED(except_vec3_generic, 0, sp) .set noat @@ -21,7 +20,7 @@ NESTED(except_vec3_generic, 0, sp) END(except_vec3_generic) NESTED(except_vec3_generic_code, 0, sp) - SAVE_ALL + SAVE_ALL mfc0 k1, CP0_CAUSE la k0, int_cause sw k1, (k0) @@ -34,7 +33,7 @@ NESTED(except_vec3_generic_code, 0, sp) la k0, badvaddr sw k1, (k0) - la k0, int_handler + la k0, int_handler .set noreorder jal k0 .set reorder @@ -48,7 +47,7 @@ NESTED(flush_cache_low, PT_SIZE, sp) .set at .set macro .set noreorder - + move t1, a0 # ISIZE move t2, a1 # DSIZE @@ -89,7 +88,7 @@ NESTED(flush_cache_low, PT_SIZE, sp) sb zero, -8(t0) bne t0, t1, 1b sb zero, -4(t0) - + la v0, 1f or v0, KSEG1 j v0 # Run uncached --- linux-2.5.73/arch/mips/baget/irq.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/baget/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -17,7 +17,6 @@ #include #include #include -#include #include #include @@ -28,24 +27,24 @@ #include -unsigned long spurious_count = 0; +volatile unsigned long irq_err_count; /* * This table is a correspondence between IRQ numbers and CPU PILs */ - -static int irq_to_pil_map[BAGET_IRQ_NR] = { + +static int irq_to_pil_map[BAGET_IRQ_NR] = { 7/*fixme: dma_err -1*/,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1, /* 0x00 - 0x0f */ -1,-1,-1,-1, 3,-1,-1,-1, 2, 2, 2,-1, 3,-1,-1,3/*fixme: lance*/, /* 0x10 - 0x1f */ -1,-1,-1,-1,-1,-1, 5,-1,-1,-1,-1,-1, 7,-1,-1,-1, /* 0x20 - 0x2f */ -1, 3, 2/*fixme systimer:3*/, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 /* 0x30 - 0x3f */ }; -static inline int irq_to_pil(int irq_nr) +static inline int irq_to_pil(int irq_nr) { int pil = -1; - if (irq_nr >= BAGET_IRQ_NR) + if (irq_nr >= BAGET_IRQ_NR) baget_printk("irq_to_pil: too large irq_nr = 0x%x\n", irq_nr); else { pil = irq_to_pil_map[irq_nr]; @@ -60,13 +59,13 @@ static inline int irq_to_pil(int irq_nr) static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask) { - unsigned long status = read_32bit_cp0_register(CP0_STATUS); + unsigned long status = read_c0_status(); status &= ~((clr_mask & 0xFF) << 8); status |= (set_mask & 0xFF) << 8; - write_32bit_cp0_register(CP0_STATUS, status); + write_c0_status(status); } -/* +/* * These two functions may be used for unconditional IRQ * masking via their PIL protection. */ @@ -92,26 +91,26 @@ static inline void unmask_irq(unsigned i static volatile unsigned int pil_in_use[BAGET_PIL_NR] = { 0, }; -void mask_irq_count(int irq_nr) +void mask_irq_count(int irq_nr) { unsigned long flags; int pil = irq_to_pil(irq_nr); - - save_and_cli(flags); + + local_irq_save(flags); if (!--pil_in_use[pil]) mask_irq(irq_nr); - restore_flags(flags); + local_irq_restore(flags); } -void unmask_irq_count(int irq_nr) +void unmask_irq_count(int irq_nr) { unsigned long flags; int pil = irq_to_pil(irq_nr); - - save_and_cli(flags); + + local_irq_save(flags); if (!pil_in_use[pil]++) unmask_irq(irq_nr); - restore_flags(flags); + local_irq_restore(flags); } /* @@ -122,18 +121,18 @@ void disable_irq(unsigned int irq_nr) { unsigned long flags; - save_and_cli(flags); + local_irq_save(flags); mask_irq(irq_nr); - restore_flags(flags); + local_irq_restore(flags); } void enable_irq(unsigned int irq_nr) { unsigned long flags; - save_and_cli(flags); + local_irq_save(flags); unmask_irq(irq_nr); - restore_flags(flags); + local_irq_restore(flags); } /* @@ -142,31 +141,31 @@ void enable_irq(unsigned int irq_nr) */ static struct irqaction *irq_action[BAGET_IRQ_NR] = { NULL, }; -int show_interrupts(struct seq_file *p, void *v) +int get_irq_list(char *buf) { - int i; + int i, len = 0; struct irqaction * action; unsigned long flags; for (i = 0 ; i < BAGET_IRQ_NR ; i++) { local_irq_save(flags); action = irq_action[i]; - if (!action) - goto skip; - seq_printf(p, "%2d: %8d %c %s", + if (!action) + gotos skip; + len += sprintf(buf+len, "%2d: %8d %c %s", i, kstat_cpu(0).irqs[i], (action->flags & SA_INTERRUPT) ? '+' : ' ', action->name); for (action=action->next; action; action = action->next) { - seq_printf(p, ",%s %s", + len += sprintf(buf+len, ",%s %s", (action->flags & SA_INTERRUPT) ? " +" : "", action->name); } - seq_putc(p, '\n'); + len += sprintf(buf+len, "\n"); skip: local_irq_restore(flags); } - return 0; + return len; } @@ -183,10 +182,10 @@ static void do_IRQ(int irq, struct pt_re int do_random, cpu; cpu = smp_processor_id(); - irq_enter(cpu, irq); - kstat_cpu(cpu).irqs[irq]++; + irq_enter(); + kstat_cpus(cpu)[irq]++; - mask_irq(irq); + mask_irq(irq); action = *(irq + irq_action); if (action) { if (!(action->flags & SA_INTERRUPT)) @@ -205,7 +204,7 @@ static void do_IRQ(int irq, struct pt_re printk("do_IRQ: Unregistered IRQ (0x%X) occurred\n", irq); } unmask_irq(irq); - irq_exit(cpu, irq); + irq_exit(); /* unmasking and bottom half handling is done magically for us. */ } @@ -213,14 +212,14 @@ static void do_IRQ(int irq, struct pt_re /* * What to do in case of 'no VIC register available' for current interrupt */ -static void vic_reg_error(unsigned long address, unsigned char active_pils) +static void vic_reg_error(unsigned long address, unsigned char active_pils) { printk("\nNo VIC register found: reg=%08lx active_pils=%02x\n" - "Current interrupt mask from CP0_CAUSE: %02x\n", - address, 0xff & active_pils, - 0xff & (read_32bit_cp0_register(CP0_CAUSE)>>8)); + "Current interrupt mask from CP0_CAUSE: %02x\n", + address, 0xff & active_pils, + 0xff & (read_c0_cause()>>8)); { int i; for (i=0; i<10000; i++) udelay(1000); } -} +} static char baget_fpu_irq = BAGET_FPU_IRQ; #define BAGET_INT_FPU {(unsigned long)&baget_fpu_irq, 1} @@ -230,27 +229,27 @@ static char baget_fpu_irq = BAGET_FPU_IR */ asmlinkage void baget_interrupt(struct pt_regs *regs) { - static struct baget_int_reg int_reg[BAGET_PIL_NR] = { + static struct baget_int_reg int_reg[BAGET_PIL_NR] = { BAGET_INT_NONE, BAGET_INT_NONE, BAGET_INT0_ACK, BAGET_INT1_ACK, - BAGET_INT_NONE, BAGET_INT_FPU, BAGET_INT_NONE, BAGET_INT5_ACK + BAGET_INT_NONE, BAGET_INT_FPU, BAGET_INT_NONE, BAGET_INT5_ACK }; unsigned char active_pils; - while ((active_pils = read_32bit_cp0_register(CP0_CAUSE)>>8)) { + while ((active_pils = read_c0_cause()>>8)) { int pil; struct baget_int_reg* reg; for (pil = 0; pil < BAGET_PIL_NR; pil++) { if (!(active_pils & (1<address) { extern int try_read(unsigned long,int); int irq = try_read(reg->address, reg->size); - if (irq != -1) + if (irq != -1) do_IRQ(BAGET_IRQ_MASK(irq), regs); - else + else vic_reg_error(reg->address, active_pils); } else { printk("baget_interrupt: unknown interrupt " @@ -291,9 +290,9 @@ int setup_baget_irq(int irq, struct irqa if (new->flags & SA_SAMPLE_RANDOM) rand_initialize_irq(irq); - save_and_cli(flags); + local_irq_save(flags); *p = new; - restore_flags(flags); + local_irq_restore(flags); if (!shared) { unmask_irq_count(irq); @@ -302,9 +301,9 @@ int setup_baget_irq(int irq, struct irqa return 0; } -int request_irq(unsigned int irq, +int request_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *), - unsigned long irqflags, + unsigned long irqflags, const char * devname, void *dev_id) { @@ -315,12 +314,12 @@ int request_irq(unsigned int irq, return -EINVAL; if (!handler) return -EINVAL; - if (irq_to_pil_map[irq] < 0) + if (irq_to_pil_map[irq] < 0) return -EINVAL; action = (struct irqaction *) kmalloc(sizeof(struct irqaction), GFP_KERNEL); - if (!action) + if (!action) return -ENOMEM; action->handler = handler; @@ -337,13 +336,13 @@ int request_irq(unsigned int irq, return retval; } - + void free_irq(unsigned int irq, void *dev_id) { struct irqaction * action, **p; unsigned long flags; - if (irq >= BAGET_IRQ_NR) + if (irq >= BAGET_IRQ_NR) printk("Trying to free IRQ%d\n",irq); for (p = irq + irq_action; (action = *p) != NULL; p = &action->next) { @@ -351,11 +350,11 @@ void free_irq(unsigned int irq, void *de continue; /* Found it - now free it */ - save_and_cli(flags); + local_irq_save(flags); *p = action->next; if (!irq[irq_action]) unmask_irq_count(irq); - restore_flags(flags); + local_irq_restore(flags); kfree(action); return; } @@ -380,7 +379,7 @@ static void write_err_interrupt(int irq, *(volatile char*) BAGET_WRERR_ACK = 0; } -static struct irqaction irq0 = +static struct irqaction irq0 = { write_err_interrupt, SA_INTERRUPT, 0, "bus write error", NULL, NULL}; void __init init_IRQ(void) @@ -393,6 +392,6 @@ void __init init_IRQ(void) /* Enable interrupts for pils 2 and 3 (lines 0 and 1) */ modify_cp0_intmask(0, (1<<2)|(1<<3)); - if (setup_baget_irq(0, &irq0) < 0) + if (setup_baget_irq(0, &irq0) < 0) printk("init_IRQ: unable to register write_err irq\n"); } --- linux-2.5.73/arch/mips/baget/ld.script.balo 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/baget/ld.script.balo 2003-06-27 15:56:23.000000000 -0700 @@ -1,4 +1,4 @@ -OUTPUT_FORMAT("elf32-bigmips") +OUTPUT_FORMAT("elf32-tradbigmips") OUTPUT_ARCH(mips) ENTRY(balo_entry) SECTIONS @@ -42,13 +42,13 @@ SECTIONS /* Startup code */ . = ALIGN(4096); __init_begin = .; - *(.text.init) - *(.data.init) + *(.text.init) + *(.data.init) . = ALIGN(4096); /* Align double page for init_task_union */ __init_end = .; - *(.fini) - *(.reginfo) + *(.fini) + *(.reginfo) /* Adjust the address for the data segment. We want to adjust up to the same address within the page on the next page up. It would be more correct to do this: @@ -68,18 +68,18 @@ SECTIONS *(.data) CONSTRUCTORS - *(.data1) + *(.data1) _gp = . + 0x8000; - *(.lit8) - *(.lit4) - *(.ctors) - *(.dtors) - *(.got.plt) *(.got) - *(.dynamic) + *(.lit8) + *(.lit4) + *(.ctors) + *(.dtors) + *(.got.plt) *(.got) + *(.dynamic) /* We want the small data sections together, so single-instruction offsets can access them all, and initialized data all before uninitialized, so we can shorten the on-disk segment size. */ - *(.sdata) + *(.sdata) _edata = .; PROVIDE (edata = .); @@ -96,21 +96,21 @@ SECTIONS /* These are needed for ELF backends which have not yet been converted to the new style linker. */ - *(.stab) - *(.stabstr) + *(.stab) + *(.stabstr) /* DWARF debug sections. Symbols in the .debug DWARF section are relative to the beginning of the section so we begin .debug at 0. It's not clear yet what needs to happen for the others. */ - *(.debug) - *(.debug_srcinfo) - *(.debug_aranges) - *(.debug_pubnames) - *(.debug_sfnames) - *(.line) + *(.debug) + *(.debug_srcinfo) + *(.debug_aranges) + *(.debug_pubnames) + *(.debug_sfnames) + *(.line) /* These must appear regardless of . */ - *(.gptab.data) *(.gptab.sdata) - *(.gptab.bss) *(.gptab.sbss) + *(.gptab.data) *(.gptab.sdata) + *(.gptab.bss) *(.gptab.sbss) _vmlinux_start = .; *(.vmlinux) --- linux-2.5.73/arch/mips/baget/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/baget/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -4,10 +4,11 @@ # obj-y := baget.o print.o setup.o time.o irq.o bagetIRQ.o \ - reset.o wbflush.o -obj-$(CONFIG_SERIAL) += vacserial.o + reset.o obj-$(CONFIG_VAC_RTC) += vacrtc.o +EXTRA_AFLAGS := $(CFLAGS) + bagetIRQ.o : bagetIRQ.S $(CC) $(CFLAGS) -c -o $@ $< @@ -28,7 +29,7 @@ dummy.c: dummy.o: dummy.c image.bin ramdisk.bin $(CC) $(CFLAGS) -c -o $@ $< $(OBJCOPY) --add-section=.vmlinux=image.bin \ - --add-section=.ramdisk=ramdisk.bin $@ + --add-section=.ramdisk=ramdisk.bin $@ balo.h: image $(NM) $< | awk ' \ @@ -39,13 +40,13 @@ balo.h: image /balo_ramdisk_size/ { printf "#define RAMDISK_SIZE 0x%s\n", $$1 } \ ' > $@ balo.o: balo.c balo.h - $(CC) $(CFLAGS) -c $< + $(CC) $(CFLAGS) -c $< balo_supp.o: balo_supp.S $(CC) $(CFLAGS) -c $< balo: balo.o dummy.o balo_supp.o print.o - $(LD) $(LDFLAGS) -T ld.script.balo -o $@ $^ + $(LD) $(LDFLAGS) -T ld.script.balo -o $@ $^ clean: rm -f balo balo.h dummy.c image image.bin --- linux-2.5.73/arch/mips/baget/print.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/baget/print.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,9 +1,7 @@ -/* $Id: print.c,v 1.1 1999/01/17 03:49:38 ralf Exp $ - * +/* * print.c: Simple print fascility * * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov - * */ #include #include @@ -16,7 +14,7 @@ */ // #define BAGET_PRINTK -/* +/* * This function is same for BALO and Linux baget_printk, * and normally prints characted to second (UART A) console. */ @@ -27,7 +25,7 @@ static void outc_low(char c) { int i; vac_outb(c, VAC_UART_B_TX); - for (i=0; i<10000; i++) + for (i=0; i<10000; i++) delay(); } @@ -38,7 +36,7 @@ void outc(char c) outc_low(c); } -void outs(char *s) +void outs(char *s) { while(*s) outc(*s++); } @@ -79,7 +77,7 @@ static __inline__ void puthex( int a ) void __init balo_printf( char *f, ... ) { int *arg = (int*)&f + 1; - char c; + char c; int format = 0; while((c = *f++) != 0) { @@ -112,7 +110,7 @@ void __init balo_printf( char *f, ... ) } void __init balo_hungup(void) -{ +{ outs("Hunging up.\n"); - while(1); + while(1); } --- linux-2.5.73/arch/mips/baget/prom/init.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/baget/prom/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,13 +1,19 @@ /* * init.c: PROM library initialisation code. * - * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov + * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov */ #include #include #include -char arcs_cmdline[COMMAND_LINE_SIZE]; +char arcs_cmdline[CL_SIZE]; + +const char *get_system_type(void) +{ + /* Should probably return one of "BT23-201", "BT23-202" */ + return "Baget"; +} void __init prom_init(unsigned int mem_upper) { --- linux-2.5.73/arch/mips/baget/setup.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/baget/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,9 +1,7 @@ -/* $Id: setup.c,v 1.4 1999/10/09 00:00:57 ralf Exp $ - * +/* * setup.c: Baget/MIPS specific setup, including init of the feature struct. * * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov - * */ #include #include @@ -17,9 +15,9 @@ long int vac_memory_upper; #define CACHEABLE_STR(val) ((val) ? "not cached" : "cached") - + static void __init vac_show(void) -{ +{ int i; unsigned short val, decode = vac_inw(VAC_DECODE_CTRL); unsigned short a24_base = vac_inw(VAC_A24_BASE); @@ -38,7 +36,7 @@ static void __init vac_show(void) VAC_IOSEL3_CTRL, VAC_IOSEL4_CTRL, VAC_IOSEL5_CTRL }; - + printk("[DSACKi %s, DRAMCS%s qualified, boundary%s qualified%s]\n", (decode & VAC_DECODE_DSACKI) ? "on" : "off", (decode & VAC_DECODE_QFY_DRAMCS) ? "" : " not", @@ -72,24 +70,24 @@ static void __init vac_show(void) VAC_ICFSEL_MODULE_VAL(vac_inw(VAC_ICFSEL_BASE)))<<4, (decode & VAC_DECODE_QFY_ICFSEL) ? "qualified" : ""); - + printk("region0 at 00000000 (%dMB)\t[dram, %s, delay %d cpuclk" ", cached]\n", (vac_inw(VAC_DRAM_MASK)+1)>>4, (decode & VAC_DECODE_DSACK) ? "D32" : "3state", VAC_DECODE_CPUCLK_VAL(decode)); - + for (i = 0; i < sizeof(regs)/sizeof(regs[0]); i++) { - unsigned long from = + unsigned long from = ((unsigned long)vac_inw(bndr[i]))<<16; - unsigned long to = + unsigned long to = ((unsigned long) - ((i+1 == sizeof(bndr)/sizeof(bndr[0])) ? + ((i+1 == sizeof(bndr)/sizeof(bndr[0])) ? 0xff00 : vac_inw(bndr[i+1])))<<16; - - + + val = vac_inw(regs[i]); - printk("region%d at %08lx (%dMB)\t[%s %s/%s, %s]\n", + printk("region%d at %08lx (%dMB)\t[%s %s/%s, %s]\n", i+1, from, (unsigned int)((to - from) >> 20), @@ -97,13 +95,13 @@ static void __init vac_show(void) asiz[VAC_REG_ASIZ_VAL(val)], ((val & VAC_REG_WORD) ? "D16" : "D32"), CACHEABLE_STR(val&VAC_A24_A24_CACHINH)); - + if (a24_addr >= from && a24_addr < to) printk("\ta24 at %08lx (%dMB)\t[vme, A24/%s, %s]\n", a24_addr, min((unsigned int)(a24_addr - from)>>20, 32U), (a24_base & VAC_A24_DATAPATH) ? "user" : - ((a24_base & VAC_A24_D32_ENABLE) ? + ((a24_base & VAC_A24_D32_ENABLE) ? "D32" : "D16"), CACHEABLE_STR(a24_base & VAC_A24_A24_CACHINH)); } @@ -123,7 +121,7 @@ static void __init vac_show(void) (VAC_CTRL_DELAY_IOWR_VAL(val)&1) ? ".5" : "", VAC_CTRL_DELAY_IOSELI_VAL(val)/2, (VAC_CTRL_DELAY_IOSELI_VAL(val)&1) ? ".5" : ""); - + printk("region5 at fff00000 (896KB)\t[local io, %s]\n", CACHEABLE_STR(vac_inw(VAC_A24_BASE) & VAC_A24_IO_CACHINH)); @@ -132,7 +130,7 @@ static void __init vac_show(void) printk("\tio%d[ack %d cpuclk%s, %s%srecovery %d cpuclk, " "\n\t read %d%s cpuclk, write %d%s cpuclk, " "assert %d%s%s cpuclk]\n", - i, + i, VAC_CTRL_DELAY_DSACKI_VAL(val), state[val & (VAC_CTRL_IORD|VAC_CTRL_IOWR)], (val & VAC_CTRL_DSACK0) ? "dsack0*, " : "", @@ -144,15 +142,15 @@ static void __init vac_show(void) (VAC_CTRL_DELAY_IOWR_VAL(val)&1) ? ".5" : "", VAC_CTRL_DELAY_IOSELI_VAL(val)/2, (VAC_CTRL_DELAY_IOSELI_VAL(val)&1) ? ".5" : "", - (vac_inw(VAC_DEV_LOC) & VAC_DEV_LOC_IOSEL(i)) ? + (vac_inw(VAC_DEV_LOC) & VAC_DEV_LOC_IOSEL(i)) ? ", id" : ""); } - + printk("region6 at fffe0000 (128KB)\t[vme, A16/%s, " "not cached]\n", - (a24_base & VAC_A24_A16D32_ENABLE) ? + (a24_base & VAC_A24_A16D32_ENABLE) ? ((a24_base & VAC_A24_A16D32) ? "D32" : "D16") : "user"); - + val = vac_inw(VAC_SHRCS_CTRL); printk("shared[ack %d cpuclk%s, %s%srecovery %d cpuclk, " "read %d%s, write %d%s, assert %d%s]\n", @@ -183,8 +181,8 @@ static void __init vac_init(void) default: panic("Unknown VAC revision number"); } - - vac_outw(mem_limit-1, VAC_DRAM_MASK); + + vac_outw(mem_limit-1, VAC_DRAM_MASK); vac_outw(mem_limit, VAC_BNDR2); vac_outw(mem_limit, VAC_BNDR3); vac_outw(((BAGET_A24M_BASE>>16)&~VAC_A24_D32_ENABLE)|VAC_A24_DATAPATH, @@ -294,19 +292,19 @@ static void __init vac_start(void) vac_outw(VAC_INT_CTRL_TIMER_PIO10| VAC_INT_CTRL_UART_B_PIO7| VAC_INT_CTRL_UART_A_PIO7,VAC_INT_CTRL); - /* + /* * Set quadro speed for both UARTs. * To do it we need use formulae from VIC/VAC manual, * keeping in mind Baget's 50MHz frequency... */ - vac_outw((500000/(384*16))<<8,VAC_CPU_CLK_DIV); + vac_outw((500000/(384*16))<<8,VAC_CPU_CLK_DIV); } static void __init vic_show(void) { unsigned char val; char *timeout[] = { "4", "16", "32", "64", "128", "256", "disabled" }; - char *deadlock[] = { "[dedlk only]", "[dedlk only]", + char *deadlock[] = { "[dedlk only]", "[dedlk only]", "[dedlk], [halt w/ rmc], [lberr]", "[dedlk], [halt w/o rmc], [lberr]" }; @@ -319,7 +317,7 @@ static void __init vic_show(void) printk("metastability delay "); printk("%s ", deadlock[VIC_IFACE_CFG_DEADLOCK_VAL(val)]); - + printk("interrupts: "); val = vic_inb(VIC_ERR_INT); @@ -332,7 +330,7 @@ static void __init vic_show(void) if (!(val & VIC_ERR_INT_ACFAIL)) printk("[acfail] "); printk("\n"); - + printk("timeouts: "); val = vic_inb(VIC_XFER_TIMO); printk("local %s, vme %s ", @@ -358,7 +356,7 @@ static void __init vic_show(void) printk("[local boundary cross]"); if (val & VIC_BXFER_DEF_VME_CROSS) printk("[vme boundary cross]"); - + } static void __init vic_init(void) @@ -373,7 +371,7 @@ static void __init vic_init(void) vic_outb(VIC_INT_IPL(3)|VIC_INT_DISABLE,VIC_VME_INT2); vic_outb(VIC_INT_IPL(3)|VIC_INT_DISABLE,VIC_VME_INT3); vic_outb(VIC_INT_IPL(3)|VIC_INT_DISABLE,VIC_VME_INT4); -/* +/* vic_outb(VIC_INT_IPL(3)|VIC_INT_DISABLE, VIC_VME_INT5); */ vic_outb(VIC_INT_IPL(3)|VIC_INT_DISABLE, VIC_VME_INT6); @@ -388,7 +386,7 @@ static void __init vic_init(void) VIC_INT_HIGH|VIC_INT_DISABLE, VIC_LINT3); vic_outb(VIC_INT_IPL(3)|VIC_INT_NOAUTO|VIC_INT_EDGE| VIC_INT_LOW|VIC_INT_DISABLE, VIC_LINT4); -/* +/* vic_outb(VIC_INT_IPL(3)|VIC_INT_NOAUTO|VIC_INT_LEVEL| VIC_INT_LOW|VIC_INT_DISABLE, VIC_LINT5); */ @@ -447,7 +445,7 @@ static void __init vic_init(void) VIC_RELEASE_RWD, VIC_RELEASE); vic_outb(VIC_IC6_RUN, VIC_IC6); vic_outb(0, VIC_IC7); - + vic_show(); } @@ -471,7 +469,7 @@ void __init baget_irq_setup(void) extern void baget_machine_restart(char *command); extern void baget_machine_halt(void); extern void baget_machine_power_off(void); - + void __init baget_setup(void) { printk("BT23/63-201n found.\n"); --- linux-2.5.73/arch/mips/baget/time.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/baget/time.c 2003-06-27 15:56:23.000000000 -0700 @@ -20,23 +20,23 @@ #include #include #include -#include +#include #include -/* +/* * To have precision clock, we need to fix available clock frequency */ #define FREQ_NOM 79125 /* Baget frequency ratio */ #define FREQ_DEN 10000 -static inline int timer_intr_valid(void) +static inline int timer_intr_valid(void) { static unsigned long long ticks, valid_ticks; if (ticks++ * FREQ_DEN >= valid_ticks * FREQ_NOM) { - /* - * We need no overflow checks, + /* + * We need no overflow checks, * due baget unable to work 3000 years... * At least without reboot... */ @@ -62,10 +62,10 @@ static void __init timer_enable(void) vic_outb(ss0cr0, VIC_SS0CR0); vic_outb(VIC_INT_IPL(6)|VIC_INT_NOAUTO|VIC_INT_EDGE| - VIC_INT_LOW|VIC_INT_ENABLE, VIC_LINT2); + VIC_INT_LOW|VIC_INT_ENABLE, VIC_LINT2); } -static struct irqaction timer_irq = +static struct irqaction timer_irq = { timer_interrupt, SA_INTERRUPT, 0, "timer", NULL, NULL}; void __init time_init(void) @@ -82,17 +82,19 @@ void do_gettimeofday(struct timeval *tv) do { seq = read_seqbegin(&xtime_lock); - *tv = xtime; + tv->tv_sec = xtime.tv_sec; + tv->tv_usec = xtime.tv_nsec / 1000; } while (read_seqretry(&xtime_lock, seq)); } void do_settimeofday(struct timeval *tv) { - write_seqlock_irq (&xtime_lock); - xtime = *tv; + write_seqlock_irq(&xtime_lock); + xtime.tv_usec = tv->tv_sec; + xtime.tv_nsec = tv->tv_usec; time_adjust = 0; /* stop active adjtime() */ time_status |= STA_UNSYNC; time_maxerror = NTP_PHASE_LIMIT; time_esterror = NTP_PHASE_LIMIT; - write_sequnlock_irq (&xtime_lock); + write_sequnlock_irq(&xtime_lock); } --- linux-2.5.73/arch/mips/baget/vacserial.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,2837 +0,0 @@ -/* - * vacserial.c: VAC UART serial driver - * This code stealed and adopted from linux/drivers/char/serial.c - * See that for author info - * - * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov - */ - -#undef SERIAL_PARANOIA_CHECK -#define CONFIG_SERIAL_NOPAUSE_IO -#define SERIAL_DO_RESTART - -#define CONFIG_SERIAL_SHARE_IRQ - -/* Set of debugging defines */ - -#undef SERIAL_DEBUG_INTR -#undef SERIAL_DEBUG_OPEN -#undef SERIAL_DEBUG_FLOW -#undef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT - -#define RS_STROBE_TIME (10*HZ) -#define RS_ISR_PASS_LIMIT 2 /* Beget is not a super-computer (old=256) */ - -#define IRQ_T(state) \ - ((state->flags & ASYNC_SHARE_IRQ) ? SA_SHIRQ : SA_INTERRUPT) - -#define SERIAL_INLINE - -#if defined(MODULE) && defined(SERIAL_DEBUG_MCOUNT) -#define DBG_CNT(s) baget_printk("(%s):[%x] refc=%d, serc=%d, ttyc=%d-> %s\n", \ - tty->name,(info->flags),serial_driver->refcount,info->count,tty->count,s) -#else -#define DBG_CNT(s) -#endif - -#define QUAD_UART_SPEED /* Useful for Baget */ - -/* - * End of serial driver configuration section. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_SERIAL_CONSOLE -#include -#endif - -#include -#include -#include -#include -#include -#include -#include - -#define BAGET_VAC_UART_IRQ 0x35 - -/* - * Implementation note: - * It was descovered by means of advanced electronic tools, - * if the driver works via TX_READY interrupts then VIC generates - * strange self-eliminating traps. Thus, the driver is rewritten to work - * via TX_EMPTY - */ - -/* VAC-specific check/debug switches */ - -#undef CHECK_REG_INDEX -#undef DEBUG_IO_PORT_A - -#ifdef SERIAL_INLINE -#define _INLINE_ inline -#endif - -static char *serial_name = "VAC Serial driver"; -static char *serial_version = "4.26"; - -static DECLARE_TASK_QUEUE(tq_serial); - -static struct tty_driver *serial_driver; - -/* number of characters left in xmit buffer before we ask for more */ -#define WAKEUP_CHARS 256 - -/* - * IRQ_timeout - How long the timeout should be for each IRQ - * should be after the IRQ has been active. - */ - -static struct async_struct *IRQ_ports[NR_IRQS]; -static int IRQ_timeout[NR_IRQS]; -#ifdef CONFIG_SERIAL_CONSOLE -static struct console sercons; -#endif - -static void autoconfig(struct serial_state * info); -static void change_speed(struct async_struct *info); -static void rs_wait_until_sent(struct tty_struct *tty, int timeout); -static void rs_timer(unsigned long dummy); - -static struct timer_list vacs_timer; - -/* - * Here we define the default xmit fifo size used for each type of - * UART - */ -static struct serial_uart_config uart_config[] = { - { "unknown", 1, 0 }, /* Must go first -- used as unassigned */ - { "VAC UART", 1, 0 } -}; -#define VAC_UART_TYPE 1 /* Just index in above array */ - -static struct serial_state rs_table[] = { -/* - * VAC has tricky layout for pair of his SIO registers, - * so we need special function to access ones. - * To identify port we use their TX offset - */ - { 0, 9600, VAC_UART_B_TX, BAGET_VAC_UART_IRQ, - STD_COM_FLAGS }, /* VAC UART B */ - { 0, 9600, VAC_UART_A_TX, BAGET_VAC_UART_IRQ, - STD_COM_FLAGS } /* VAC UART A */ -}; - -#define NR_PORTS (sizeof(rs_table)/sizeof(struct serial_state)) - -#ifndef MIN -#define MIN(a,b) ((a) < (b) ? (a) : (b)) -#endif - -/* - * tmp_buf is used as a temporary buffer by serial_write. We need to - * lock it in case the copy_from_user blocks while swapping in a page, - * and some other program tries to do a serial write at the same time. - * Since the lock will only come under contention when the system is - * swapping and available memory is low, it makes sense to share one - * buffer across all the serial ports, since it significantly saves - * memory if large numbers of serial ports are open. - */ -static unsigned char *tmp_buf; -static DECLARE_MUTEX(tmp_buf_sem); - -static inline int serial_paranoia_check(struct async_struct *info, - char *name, const char *routine) -{ -#ifdef SERIAL_PARANOIA_CHECK - static const char *badmagic = - "Warning: bad magic number for serial struct (%s) in %s\n"; - static const char *badinfo = - "Warning: null async_struct for (%s) in %s\n"; - - if (!info) { - printk(badinfo, name, routine); - return 1; - } - if (info->magic != SERIAL_MAGIC) { - printk(badmagic, name, routine); - return 1; - } -#endif - return 0; -} - -/* - To unify UART A/B access we will use following function - to compute register offsets by register index. - */ - -#define VAC_UART_MODE 0 -#define VAC_UART_TX 1 -#define VAC_UART_RX 2 -#define VAC_UART_INT_MASK 3 -#define VAC_UART_INT_STATUS 4 - -#define VAC_UART_REG_NR 5 - -static inline int uart_offset_map(unsigned long port, int reg_index) -{ - static const unsigned int ind_to_reg[VAC_UART_REG_NR][NR_PORTS] = { - { VAC_UART_B_MODE, VAC_UART_A_MODE }, - { VAC_UART_B_TX, VAC_UART_A_TX }, - { VAC_UART_B_RX, VAC_UART_A_RX }, - { VAC_UART_B_INT_MASK, VAC_UART_A_INT_MASK }, - { VAC_UART_B_INT_STATUS, VAC_UART_A_INT_STATUS } - }; -#ifdef CHECK_REG_INDEX - if (reg_index > VAC_UART_REG_NR) panic("vacserial: bad reg_index"); -#endif - return ind_to_reg[reg_index][port == VAC_UART_B_TX ? 0 : 1]; -} - -static inline unsigned int serial_inw(struct async_struct *info, int offset) -{ - int val = vac_inw(uart_offset_map(info->port,offset)); -#ifdef DEBUG_IO_PORT_A - if (info->port == VAC_UART_A_TX) - printk("UART_A_IN: reg = 0x%04x, val = 0x%04x\n", - uart_offset_map(info->port,offset), val); -#endif - return val; -} - -static inline unsigned int serial_inp(struct async_struct *info, int offset) -{ - return serial_inw(info, offset); -} - -static inline unsigned int serial_in(struct async_struct *info, int offset) -{ - return serial_inw(info, offset); -} - -static inline void serial_outw(struct async_struct *info,int offset, int value) -{ -#ifdef DEBUG_IO_PORT_A - if (info->port == VAC_UART_A_TX) - printk("UART_A_OUT: offset = 0x%04x, val = 0x%04x\n", - uart_offset_map(info->port,offset), value); -#endif - vac_outw(value, uart_offset_map(info->port,offset)); -} - -static inline void serial_outp(struct async_struct *info,int offset, int value) -{ - serial_outw(info,offset,value); -} - -static inline void serial_out(struct async_struct *info,int offset, int value) -{ - serial_outw(info,offset,value); -} - -/* - * ------------------------------------------------------------ - * rs_stop() and rs_start() - * - * This routines are called before setting or resetting tty->stopped. - * They enable or disable transmitter interrupts, as necessary. - * ------------------------------------------------------------ - */ -static void rs_stop(struct tty_struct *tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_stop")) - return; - - save_flags(flags); cli(); - if (info->IER & VAC_UART_INT_TX_EMPTY) { - info->IER &= ~VAC_UART_INT_TX_EMPTY; - serial_out(info, VAC_UART_INT_MASK, info->IER); - } - restore_flags(flags); -} - -static void rs_start(struct tty_struct *tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_start")) - return; - - save_flags(flags); cli(); - if (info->xmit_cnt && info->xmit_buf - && !(info->IER & VAC_UART_INT_TX_EMPTY)) { - info->IER |= VAC_UART_INT_TX_EMPTY; - serial_out(info, VAC_UART_INT_MASK, info->IER); - } - restore_flags(flags); -} - -/* - * ---------------------------------------------------------------------- - * - * Here starts the interrupt handling routines. All of the following - * subroutines are declared as inline and are folded into - * rs_interrupt(). They were separated out for readability's sake. - * - * Note: rs_interrupt() is a "fast" interrupt, which means that it - * runs with interrupts turned off. People who may want to modify - * rs_interrupt() should try to keep the interrupt handler as fast as - * possible. After you are done making modifications, it is not a bad - * idea to do: - * - * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c - * - * and look at the resulting assemble code in serial.s. - * - * - Ted Ts'o (tytso@mit.edu), 7-Mar-93 - * ----------------------------------------------------------------------- - */ - -/* - * This routine is used by the interrupt handler to schedule - * processing in the software interrupt portion of the driver. - */ -static _INLINE_ void rs_sched_event(struct async_struct *info, - int event) -{ - info->event |= 1 << event; - queue_task(&info->tqueue, &tq_serial); - mark_bh(SERIAL_BH); -} - -static _INLINE_ void receive_chars(struct async_struct *info, - int *status) -{ - struct tty_struct *tty = info->tty; - unsigned short rx; - unsigned char ch; - int ignored = 0; - struct async_icount *icount; - - icount = &info->state->icount; - do { - rx = serial_inw(info, VAC_UART_RX); - ch = VAC_UART_RX_DATA_MASK & rx; - - if (tty->flip.count >= TTY_FLIPBUF_SIZE) - break; - *tty->flip.char_buf_ptr = ch; - icount->rx++; - -#ifdef SERIAL_DEBUG_INTR - baget_printk("DR%02x:%02x...", rx, *status); -#endif - *tty->flip.flag_buf_ptr = 0; - if (*status & (VAC_UART_STATUS_RX_BREAK_CHANGE - | VAC_UART_STATUS_RX_ERR_PARITY - | VAC_UART_STATUS_RX_ERR_FRAME - | VAC_UART_STATUS_RX_ERR_OVERRUN)) { - /* - * For statistics only - */ - if (*status & VAC_UART_STATUS_RX_BREAK_CHANGE) { - *status &= ~(VAC_UART_STATUS_RX_ERR_FRAME - | VAC_UART_STATUS_RX_ERR_PARITY); - icount->brk++; - } else if (*status & VAC_UART_STATUS_RX_ERR_PARITY) - icount->parity++; - else if (*status & VAC_UART_STATUS_RX_ERR_FRAME) - icount->frame++; - if (*status & VAC_UART_STATUS_RX_ERR_OVERRUN) - icount->overrun++; - - /* - * Now check to see if character should be - * ignored, and mask off conditions which - * should be ignored. - */ - if (*status & info->ignore_status_mask) { - if (++ignored > 100) - break; - goto ignore_char; - } - *status &= info->read_status_mask; - - if (*status & (VAC_UART_STATUS_RX_BREAK_CHANGE)) { -#ifdef SERIAL_DEBUG_INTR - baget_printk("handling break...."); -#endif - *tty->flip.flag_buf_ptr = TTY_BREAK; - if (info->flags & ASYNC_SAK) - do_SAK(tty); - } else if (*status & VAC_UART_STATUS_RX_ERR_PARITY) - *tty->flip.flag_buf_ptr = TTY_PARITY; - else if (*status & VAC_UART_STATUS_RX_ERR_FRAME) - *tty->flip.flag_buf_ptr = TTY_FRAME; - if (*status & VAC_UART_STATUS_RX_ERR_OVERRUN) { - /* - * Overrun is special, since it's - * reported immediately, and doesn't - * affect the current character - */ - if (tty->flip.count < TTY_FLIPBUF_SIZE) { - tty->flip.count++; - tty->flip.flag_buf_ptr++; - tty->flip.char_buf_ptr++; - *tty->flip.flag_buf_ptr = TTY_OVERRUN; - } - } - } - tty->flip.flag_buf_ptr++; - tty->flip.char_buf_ptr++; - tty->flip.count++; - ignore_char: - *status = serial_inw(info, VAC_UART_INT_STATUS); - } while ((*status & VAC_UART_STATUS_RX_READY)); - tty_flip_buffer_push(tty); -} - -static _INLINE_ void transmit_chars(struct async_struct *info, int *intr_done) -{ - int count; - - if (info->x_char) { - serial_outw(info, VAC_UART_TX, - (((unsigned short)info->x_char)<<8)); - info->state->icount.tx++; - info->x_char = 0; - if (intr_done) - *intr_done = 0; - return; - } - if ((info->xmit_cnt <= 0) || info->tty->stopped || - info->tty->hw_stopped) { - info->IER &= ~VAC_UART_INT_TX_EMPTY; - serial_outw(info, VAC_UART_INT_MASK, info->IER); - return; - } - count = info->xmit_fifo_size; - do { - serial_out(info, VAC_UART_TX, - (unsigned short)info->xmit_buf[info->xmit_tail++] \ - << 8); - info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1); - info->state->icount.tx++; - if (--info->xmit_cnt <= 0) - break; - } while (--count > 0); - - if (info->xmit_cnt < WAKEUP_CHARS) - rs_sched_event(info, RS_EVENT_WRITE_WAKEUP); - -#ifdef SERIAL_DEBUG_INTR - baget_printk("THRE..."); -#endif - if (intr_done) - *intr_done = 0; - - if (info->xmit_cnt <= 0) { - info->IER &= ~VAC_UART_INT_TX_EMPTY; - serial_outw(info, VAC_UART_INT_MASK, info->IER); - } -} - -static _INLINE_ void check_modem_status(struct async_struct *info) -{ -#if 0 /* VAC hasn't modem control */ - wake_up_interruptible(&info->open_wait); - rs_sched_event(info, RS_EVENT_WRITE_WAKEUP); -#endif -} - -#ifdef CONFIG_SERIAL_SHARE_IRQ - - -/* - * Specific functions needed for VAC UART interrupt enter/leave - */ - -#define VAC_INT_CTRL_UART_ENABLE \ - (VAC_INT_CTRL_TIMER_PIO10|VAC_INT_CTRL_UART_B_PIO7|VAC_INT_CTRL_UART_A_PIO7) - -#define VAC_INT_CTRL_UART_DISABLE(info) \ - (VAC_INT_CTRL_TIMER_PIO10 | \ - ((info->port == VAC_UART_A_TX) ? \ - (VAC_INT_CTRL_UART_A_DISABLE|VAC_INT_CTRL_UART_B_PIO7) : \ - (VAC_INT_CTRL_UART_A_PIO7|VAC_INT_CTRL_UART_B_DISABLE))) - -/* - * Following two functions were proposed by Pavel Osipenko - * to make VAC/VIC behaviour more regular. - */ -static void intr_begin(struct async_struct* info) -{ - serial_outw(info, VAC_UART_INT_MASK, 0); -} - -static void intr_end(struct async_struct* info) -{ - vac_outw(VAC_INT_CTRL_UART_DISABLE(info), VAC_INT_CTRL); - vac_outw(VAC_INT_CTRL_UART_ENABLE, VAC_INT_CTRL); - - serial_outw(info, VAC_UART_INT_MASK, info->IER); -} - -/* - * This is the serial driver's generic interrupt routine - */ -static void rs_interrupt(int irq, void *dev_id, struct pt_regs * regs) -{ - int status; - struct async_struct * info; - int pass_counter = 0; - struct async_struct *end_mark = 0; - -#ifdef SERIAL_DEBUG_INTR - baget_printk("rs_interrupt(%d)...", irq); -#endif - - info = IRQ_ports[irq]; - if (!info) - return; - - do { - intr_begin(info); /* Mark we begin port handling */ - - if (!info->tty || - (serial_inw (info, VAC_UART_INT_STATUS) - & VAC_UART_STATUS_INTS) == 0) - { - if (!end_mark) - end_mark = info; - goto next; - } - end_mark = 0; - - info->last_active = jiffies; - - status = serial_inw(info, VAC_UART_INT_STATUS); -#ifdef SERIAL_DEBUG_INTR - baget_printk("status = %x...", status); -#endif - if (status & VAC_UART_STATUS_RX_READY) { - receive_chars(info, &status); - } - check_modem_status(info); - if (status & VAC_UART_STATUS_TX_EMPTY) - transmit_chars(info, 0); - - next: - intr_end(info); /* Mark this port handled */ - - info = info->next_port; - if (!info) { - info = IRQ_ports[irq]; - if (pass_counter++ > RS_ISR_PASS_LIMIT) { - break; /* Prevent infinite loops */ - } - continue; - } - } while (end_mark != info); -#ifdef SERIAL_DEBUG_INTR - baget_printk("end.\n"); -#endif - - -} -#endif /* #ifdef CONFIG_SERIAL_SHARE_IRQ */ - - -/* The original driver was simplified here: - two functions were joined to reduce code */ - -#define rs_interrupt_single rs_interrupt - - -/* - * ------------------------------------------------------------------- - * Here ends the serial interrupt routines. - * ------------------------------------------------------------------- - */ - -/* - * This routine is used to handle the "bottom half" processing for the - * serial driver, known also the "software interrupt" processing. - * This processing is done at the kernel interrupt level, after the - * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This - * is where time-consuming activities which can not be done in the - * interrupt driver proper are done; the interrupt driver schedules - * them using rs_sched_event(), and they get done here. - */ -static void do_serial_bh(void) -{ - run_task_queue(&tq_serial); -} - -static void do_softint(void *private_) -{ - struct async_struct *info = (struct async_struct *) private_; - struct tty_struct *tty; - - tty = info->tty; - if (!tty) - return; - - if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event)) { - if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && - tty->ldisc.write_wakeup) - (tty->ldisc.write_wakeup)(tty); - wake_up_interruptible(&tty->write_wait); - } -} - -/* - * --------------------------------------------------------------- - * Low level utility subroutines for the serial driver: routines to - * figure out the appropriate timeout for an interrupt chain, routines - * to initialize and startup a serial port, and routines to shutdown a - * serial port. Useful stuff like that. - * --------------------------------------------------------------- - */ - -/* - * This routine figures out the correct timeout for a particular IRQ. - * It uses the smallest timeout of all of the serial ports in a - * particular interrupt chain. Now only used for IRQ 0.... - */ -static void figure_IRQ_timeout(int irq) -{ - struct async_struct *info; - int timeout = 60*HZ; /* 60 seconds === a long time :-) */ - - info = IRQ_ports[irq]; - if (!info) { - IRQ_timeout[irq] = 60*HZ; - return; - } - while (info) { - if (info->timeout < timeout) - timeout = info->timeout; - info = info->next_port; - } - if (!irq) - timeout = timeout / 2; - IRQ_timeout[irq] = timeout ? timeout : 1; -} - -static int startup(struct async_struct * info) -{ - unsigned long flags; - int retval=0; - void (*handler)(int, void *, struct pt_regs *); - struct serial_state *state= info->state; - unsigned long page; - - page = get_zeroed_page(GFP_KERNEL); - if (!page) - return -ENOMEM; - - save_flags(flags); cli(); - - if (info->flags & ASYNC_INITIALIZED) { - free_page(page); - goto errout; - } - if (!state->port || !state->type) { - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); - free_page(page); - goto errout; - } - if (info->xmit_buf) - free_page(page); - else - info->xmit_buf = (unsigned char *) page; - -#ifdef SERIAL_DEBUG_OPEN - baget_printk("starting up ttys%d (irq %d)...", info->line, state->irq); -#endif - - if (uart_config[info->state->type].flags & UART_STARTECH) { - /* Wake up UART */ - serial_outp(info, VAC_UART_MODE, 0); - serial_outp(info, VAC_UART_INT_MASK, 0); - } - - /* - * Allocate the IRQ if necessary - */ - if (state->irq && (!IRQ_ports[state->irq] || - !IRQ_ports[state->irq]->next_port)) { - - if (IRQ_ports[state->irq]) { -#ifdef CONFIG_SERIAL_SHARE_IRQ - free_irq(state->irq, NULL); - handler = rs_interrupt; -#else - retval = -EBUSY; - goto errout; -#endif /* CONFIG_SERIAL_SHARE_IRQ */ - } else - handler = rs_interrupt_single; - - - retval = request_irq(state->irq, handler, IRQ_T(state), - "serial", NULL); - if (retval) { - if (capable(CAP_SYS_ADMIN)) { - if (info->tty) - set_bit(TTY_IO_ERROR, - &info->tty->flags); - retval = 0; - } - goto errout; - } - } - - /* - * Insert serial port into IRQ chain. - */ - info->prev_port = 0; - info->next_port = IRQ_ports[state->irq]; - if (info->next_port) - info->next_port->prev_port = info; - IRQ_ports[state->irq] = info; - figure_IRQ_timeout(state->irq); - - /* - * Clear the interrupt registers. - */ - /* (void) serial_inw(info, VAC_UART_INT_STATUS); */ /* (see above) */ - (void) serial_inw(info, VAC_UART_RX); - - /* - * Now, initialize the UART - */ - serial_outp(info, VAC_UART_MODE, VAC_UART_MODE_INITIAL); /*reset DLAB*/ - - /* - * Finally, enable interrupts - */ - info->IER = VAC_UART_INT_RX_BREAK_CHANGE | VAC_UART_INT_RX_ERRS | \ - VAC_UART_INT_RX_READY; - serial_outp(info, VAC_UART_INT_MASK, info->IER); /*enable interrupts*/ - - /* - * And clear the interrupt registers again for luck. - */ - (void)serial_inp(info, VAC_UART_INT_STATUS); - (void)serial_inp(info, VAC_UART_RX); - - if (info->tty) - clear_bit(TTY_IO_ERROR, &info->tty->flags); - info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; - - /* - * Set up serial timers... - */ - mod_timer(&vacs_timer, jiffies + 2*HZ/100); - - /* - * and set the speed of the serial port - */ - change_speed(info); - - info->flags |= ASYNC_INITIALIZED; - restore_flags(flags); - return 0; - -errout: - restore_flags(flags); - return retval; -} - -/* - * This routine will shutdown a serial port; interrupts are disabled, and - * DTR is dropped if the hangup on close termio flag is on. - */ -static void shutdown(struct async_struct * info) -{ - unsigned long flags; - struct serial_state *state; - int retval; - - if (!(info->flags & ASYNC_INITIALIZED)) - return; - - state = info->state; - -#ifdef SERIAL_DEBUG_OPEN - baget_printk("Shutting down serial port %d (irq %d)....", info->line, - state->irq); -#endif - - save_flags(flags); cli(); /* Disable interrupts */ - - /* - * clear delta_msr_wait queue to avoid mem leaks: we may free the irq - * here so the queue might never be waken up - */ - wake_up_interruptible(&info->delta_msr_wait); - - /* - * First unlink the serial port from the IRQ chain... - */ - if (info->next_port) - info->next_port->prev_port = info->prev_port; - if (info->prev_port) - info->prev_port->next_port = info->next_port; - else - IRQ_ports[state->irq] = info->next_port; - figure_IRQ_timeout(state->irq); - - /* - * Free the IRQ, if necessary - */ - if (state->irq && (!IRQ_ports[state->irq] || - !IRQ_ports[state->irq]->next_port)) { - if (IRQ_ports[state->irq]) { - free_irq(state->irq, NULL); - retval = request_irq(state->irq, rs_interrupt_single, - IRQ_T(state), "serial", NULL); - - if (retval) - printk("serial shutdown: request_irq: error %d" - " Couldn't reacquire IRQ.\n", retval); - } else - free_irq(state->irq, NULL); - } - - if (info->xmit_buf) { - free_page((unsigned long) info->xmit_buf); - info->xmit_buf = 0; - } - - info->IER = 0; - serial_outp(info, VAC_UART_INT_MASK, 0x00); /* disable all intrs */ - - /* disable break condition */ - serial_out(info, VAC_UART_MODE, serial_inp(info, VAC_UART_MODE) & \ - ~VAC_UART_MODE_SEND_BREAK); - - if (info->tty) - set_bit(TTY_IO_ERROR, &info->tty->flags); - - info->flags &= ~ASYNC_INITIALIZED; - restore_flags(flags); -} - -/* - * When we set line mode, we call this function - * for Baget-specific adjustments. - */ - -static inline unsigned short vac_uart_mode_fixup (unsigned short cval) -{ -#ifdef QUAD_UART_SPEED - /* - * When we are using 4-x advantage in speed: - * - * Disadvantage : can't support 75, 150 bauds - * Advantage : can support 19200, 38400 bauds - */ - char speed = 7 & (cval >> 10); - cval &= ~(7 << 10); - cval |= VAC_UART_MODE_BAUD(speed-2); -#endif - - /* - * In general, we have Tx and Rx ON all time - * and use int mask flag for their disabling. - */ - cval |= VAC_UART_MODE_RX_ENABLE; - cval |= VAC_UART_MODE_TX_ENABLE; - cval |= VAC_UART_MODE_CHAR_RX_ENABLE; - cval |= VAC_UART_MODE_CHAR_TX_ENABLE; - - /* Low 4 bits are not used in UART */ - cval &= ~0xf; - - return cval; -} - -/* - * This routine is called to set the UART divisor registers to match - * the specified baud rate for a serial port. - */ -static void change_speed(struct async_struct *info) -{ - unsigned short port; - int quot = 0, baud_base, baud; - unsigned cflag, cval; - int bits; - unsigned long flags; - - if (!info->tty || !info->tty->termios) - return; - cflag = info->tty->termios->c_cflag; - if (!(port = info->port)) - return; - - /* byte size and parity */ - switch (cflag & CSIZE) { - case CS7: cval = 0x0; bits = 9; break; - case CS8: cval = VAC_UART_MODE_8BIT_CHAR; bits = 10; break; - /* Never happens, but GCC is too dumb to figure it out */ - case CS5: - case CS6: - default: cval = 0x0; bits = 9; break; - } - cval &= ~VAC_UART_MODE_PARITY_ENABLE; - if (cflag & PARENB) { - cval |= VAC_UART_MODE_PARITY_ENABLE; - bits++; - } - if (cflag & PARODD) - cval |= VAC_UART_MODE_PARITY_ODD; - - /* Determine divisor based on baud rate */ - baud = tty_get_baud_rate(info->tty); - if (!baud) - baud = 9600; /* B0 transition handled in rs_set_termios */ - baud_base = info->state->baud_base; - if (baud == 38400 && - ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST)) - quot = info->state->custom_divisor; - else { - if (baud == 134) - /* Special case since 134 is really 134.5 */ - quot = (2*baud_base / 269); - else if (baud) - quot = baud_base / baud; - } - /* If the quotient is ever zero, default to 9600 bps */ - if (!quot) - quot = baud_base / 9600; - info->quot = quot; - info->timeout = ((info->xmit_fifo_size*HZ*bits*quot) / baud_base); - info->timeout += HZ/50; /* Add .02 seconds of slop */ - - serial_out(info, VAC_UART_INT_MASK, info->IER); - - /* - * Set up parity check flag - */ -#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) - - info->read_status_mask = VAC_UART_STATUS_RX_ERR_OVERRUN | \ - VAC_UART_STATUS_TX_EMPTY | VAC_UART_STATUS_RX_READY; - if (I_INPCK(info->tty)) - info->read_status_mask |= VAC_UART_STATUS_RX_ERR_FRAME | \ - VAC_UART_STATUS_RX_ERR_PARITY; - if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) - info->read_status_mask |= VAC_UART_STATUS_RX_BREAK_CHANGE; - - /* - * Characters to ignore - */ - info->ignore_status_mask = 0; - if (I_IGNPAR(info->tty)) - info->ignore_status_mask |= VAC_UART_STATUS_RX_ERR_PARITY | \ - VAC_UART_STATUS_RX_ERR_FRAME; - if (I_IGNBRK(info->tty)) { - info->ignore_status_mask |= VAC_UART_STATUS_RX_BREAK_CHANGE; - /* - * If we're ignore parity and break indicators, ignore - * overruns too. (For real raw support). - */ - if (I_IGNPAR(info->tty)) - info->ignore_status_mask |= \ - VAC_UART_STATUS_RX_ERR_OVERRUN; - } - /* - * !!! ignore all characters if CREAD is not set - */ - if ((cflag & CREAD) == 0) - info->ignore_status_mask |= VAC_UART_STATUS_RX_READY; - save_flags(flags); cli(); - - - switch (baud) { - default: - case 9600: - cval |= VAC_UART_MODE_BAUD(7); - break; - case 4800: - cval |= VAC_UART_MODE_BAUD(6); - break; - case 2400: - cval |= VAC_UART_MODE_BAUD(5); - break; - case 1200: - cval |= VAC_UART_MODE_BAUD(4); - break; - case 600: - cval |= VAC_UART_MODE_BAUD(3); - break; - case 300: - cval |= VAC_UART_MODE_BAUD(2); - break; -#ifndef QUAD_UART_SPEED - case 150: -#else - case 38400: -#endif - cval |= VAC_UART_MODE_BAUD(1); - break; -#ifndef QUAD_UART_SPEED - case 75: -#else - case 19200: -#endif - cval |= VAC_UART_MODE_BAUD(0); - break; - } - - /* Baget VAC need some adjustments for computed value */ - cval = vac_uart_mode_fixup(cval); - - serial_outp(info, VAC_UART_MODE, cval); - restore_flags(flags); -} - -static void rs_put_char(struct tty_struct *tty, unsigned char ch) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_put_char")) - return; - - if (!tty || !info->xmit_buf) - return; - - save_flags(flags); cli(); - if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1) { - restore_flags(flags); - return; - } - - info->xmit_buf[info->xmit_head++] = ch; - info->xmit_head &= SERIAL_XMIT_SIZE-1; - info->xmit_cnt++; - restore_flags(flags); -} - -static void rs_flush_chars(struct tty_struct *tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_flush_chars")) - return; - - if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped || - !info->xmit_buf) - return; - - save_flags(flags); cli(); - info->IER |= VAC_UART_INT_TX_EMPTY; - serial_out(info, VAC_UART_INT_MASK, info->IER); - restore_flags(flags); -} - -static int rs_write(struct tty_struct * tty, int from_user, - const unsigned char *buf, int count) -{ - int c, ret = 0; - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_write")) - return 0; - - if (!tty || !info->xmit_buf || !tmp_buf) - return 0; - - save_flags(flags); - if (from_user) { - down(&tmp_buf_sem); - while (1) { - c = MIN(count, - MIN(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, - SERIAL_XMIT_SIZE - info->xmit_head)); - if (c <= 0) - break; - - c -= copy_from_user(tmp_buf, buf, c); - if (!c) { - if (!ret) - ret = -EFAULT; - break; - } - cli(); - c = MIN(c, MIN(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, - SERIAL_XMIT_SIZE - info->xmit_head)); - memcpy(info->xmit_buf + info->xmit_head, tmp_buf, c); - info->xmit_head = ((info->xmit_head + c) & - (SERIAL_XMIT_SIZE-1)); - info->xmit_cnt += c; - restore_flags(flags); - buf += c; - count -= c; - ret += c; - } - up(&tmp_buf_sem); - } else { - while (1) { - cli(); - c = MIN(count, - MIN(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, - SERIAL_XMIT_SIZE - info->xmit_head)); - if (c <= 0) { - restore_flags(flags); - break; - } - memcpy(info->xmit_buf + info->xmit_head, buf, c); - info->xmit_head = ((info->xmit_head + c) & - (SERIAL_XMIT_SIZE-1)); - info->xmit_cnt += c; - restore_flags(flags); - buf += c; - count -= c; - ret += c; - } - } - if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped && - !(info->IER & VAC_UART_INT_TX_EMPTY)) { - info->IER |= VAC_UART_INT_TX_EMPTY; - serial_out(info, VAC_UART_INT_MASK, info->IER); - } - return ret; -} - -static int rs_write_room(struct tty_struct *tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - int ret; - - if (serial_paranoia_check(info, tty->name, "rs_write_room")) - return 0; - ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1; - if (ret < 0) - ret = 0; - return ret; -} - -static int rs_chars_in_buffer(struct tty_struct *tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - - if (serial_paranoia_check(info, tty->name, "rs_chars_in_buffer")) - return 0; - return info->xmit_cnt; -} - -static void rs_flush_buffer(struct tty_struct *tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_flush_buffer")) - return; - - save_flags(flags); cli(); - info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; - restore_flags(flags); - - wake_up_interruptible(&tty->write_wait); - if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && - tty->ldisc.write_wakeup) - (tty->ldisc.write_wakeup)(tty); -} - -/* - * This function is used to send a high-priority XON/XOFF character to - * the device - */ -static void rs_send_xchar(struct tty_struct *tty, char ch) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - - if (serial_paranoia_check(info, tty->name, "rs_send_char")) - return; - - info->x_char = ch; - if (ch) { - /* Make sure transmit interrupts are on */ - info->IER |= VAC_UART_INT_TX_EMPTY; - serial_out(info, VAC_UART_INT_MASK, info->IER); - } -} - -/* - * ------------------------------------------------------------ - * rs_throttle() - * - * This routine is called by the upper-layer tty layer to signal that - * incoming characters should be throttled. - * ------------------------------------------------------------ - */ -static void rs_throttle(struct tty_struct * tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - -#ifdef SERIAL_DEBUG_THROTTLE - char buf[64]; - - baget_printk("throttle %s: %d....\n", tty_name(tty, buf), - tty->ldisc.chars_in_buffer(tty)); -#endif - - if (serial_paranoia_check(info, tty->name, "rs_throttle")) - return; - - if (I_IXOFF(tty)) - rs_send_xchar(tty, STOP_CHAR(tty)); -} - -static void rs_unthrottle(struct tty_struct * tty) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; -#ifdef SERIAL_DEBUG_THROTTLE - char buf[64]; - - baget_printk("unthrottle %s: %d....\n", tty_name(tty, buf), - tty->ldisc.chars_in_buffer(tty)); -#endif - - if (serial_paranoia_check(info, tty->name, "rs_unthrottle")) - return; - - if (I_IXOFF(tty)) { - if (info->x_char) - info->x_char = 0; - else - rs_send_xchar(tty, START_CHAR(tty)); - } -} - -/* - * ------------------------------------------------------------ - * rs_ioctl() and friends - * ------------------------------------------------------------ - */ - -static int get_serial_info(struct async_struct * info, - struct serial_struct * retinfo) -{ - struct serial_struct tmp; - struct serial_state *state = info->state; - - if (!retinfo) - return -EFAULT; - memset(&tmp, 0, sizeof(tmp)); - tmp.type = state->type; - tmp.line = state->line; - tmp.port = state->port; - tmp.irq = state->irq; - tmp.flags = state->flags; - tmp.xmit_fifo_size = state->xmit_fifo_size; - tmp.baud_base = state->baud_base; - tmp.close_delay = state->close_delay; - tmp.closing_wait = state->closing_wait; - tmp.custom_divisor = state->custom_divisor; - tmp.hub6 = state->hub6; - if (copy_to_user(retinfo,&tmp,sizeof(*retinfo))) - return -EFAULT; - return 0; -} - -static int set_serial_info(struct async_struct * info, - struct serial_struct * new_info) -{ - struct serial_struct new_serial; - struct serial_state old_state, *state; - unsigned int i,change_irq,change_port; - int retval = 0; - - if (copy_from_user(&new_serial,new_info,sizeof(new_serial))) - return -EFAULT; - state = info->state; - old_state = *state; - - change_irq = new_serial.irq != state->irq; - change_port = (new_serial.port != state->port) || - (new_serial.hub6 != state->hub6); - - if (!capable(CAP_SYS_ADMIN)) { - if (change_irq || change_port || - (new_serial.baud_base != state->baud_base) || - (new_serial.type != state->type) || - (new_serial.close_delay != state->close_delay) || - (new_serial.xmit_fifo_size != state->xmit_fifo_size) || - ((new_serial.flags & ~ASYNC_USR_MASK) != - (state->flags & ~ASYNC_USR_MASK))) - return -EPERM; - state->flags = ((state->flags & ~ASYNC_USR_MASK) | - (new_serial.flags & ASYNC_USR_MASK)); - info->flags = ((state->flags & ~ASYNC_USR_MASK) | - (info->flags & ASYNC_USR_MASK)); - state->custom_divisor = new_serial.custom_divisor; - goto check_and_exit; - } - - new_serial.irq = new_serial.irq; - - if ((new_serial.irq >= NR_IRQS) || (new_serial.port > 0xffff) || - (new_serial.baud_base == 0) || (new_serial.type < PORT_UNKNOWN) || - (new_serial.type > PORT_MAX) || (new_serial.type == PORT_CIRRUS) || - (new_serial.type == PORT_STARTECH)) { - return -EINVAL; - } - - if ((new_serial.type != state->type) || - (new_serial.xmit_fifo_size <= 0)) - new_serial.xmit_fifo_size = - uart_config[state->type].dfl_xmit_fifo_size; - - /* Make sure address is not already in use */ - if (new_serial.type) { - for (i = 0 ; i < NR_PORTS; i++) - if ((state != &rs_table[i]) && - (rs_table[i].port == new_serial.port) && - rs_table[i].type) - return -EADDRINUSE; - } - - if ((change_port || change_irq) && (state->count > 1)) - return -EBUSY; - - /* - * OK, past this point, all the error checking has been done. - * At this point, we start making changes..... - */ - - state->baud_base = new_serial.baud_base; - state->flags = ((state->flags & ~ASYNC_FLAGS) | - (new_serial.flags & ASYNC_FLAGS)); - info->flags = ((state->flags & ~ASYNC_INTERNAL_FLAGS) | - (info->flags & ASYNC_INTERNAL_FLAGS)); - state->custom_divisor = new_serial.custom_divisor; - state->type = new_serial.type; - state->close_delay = new_serial.close_delay * HZ/100; - state->closing_wait = new_serial.closing_wait * HZ/100; - info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; - info->xmit_fifo_size = state->xmit_fifo_size = - new_serial.xmit_fifo_size; - - release_region(state->port,8); - if (change_port || change_irq) { - /* - * We need to shutdown the serial port at the old - * port/irq combination. - */ - shutdown(info); - state->irq = new_serial.irq; - info->port = state->port = new_serial.port; - info->hub6 = state->hub6 = new_serial.hub6; - } - if (state->type != PORT_UNKNOWN) - request_region(state->port,8,"serial(set)"); - - -check_and_exit: - if (!state->port || !state->type) - return 0; - if (info->flags & ASYNC_INITIALIZED) { - if (((old_state.flags & ASYNC_SPD_MASK) != - (state->flags & ASYNC_SPD_MASK)) || - (old_state.custom_divisor != state->custom_divisor)) { - if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI) - info->tty->alt_speed = 57600; - if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI) - info->tty->alt_speed = 115200; - if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI) - info->tty->alt_speed = 230400; - if ((state->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP) - info->tty->alt_speed = 460800; - change_speed(info); - } - } else - retval = startup(info); - return retval; -} - - -/* - * get_lsr_info - get line status register info - * - * Purpose: Let user call ioctl() to get info when the UART physically - * is emptied. On bus types like RS485, the transmitter must - * release the bus after transmitting. This must be done when - * the transmit shift register is empty, not be done when the - * transmit holding register is empty. This functionality - * allows an RS485 driver to be written in user space. - */ -static int get_lsr_info(struct async_struct * info, unsigned int *value) -{ - unsigned short status; - unsigned int result; - unsigned long flags; - - save_flags(flags); cli(); - status = serial_inw(info, VAC_UART_INT_STATUS); - restore_flags(flags); - result = ((status & VAC_UART_STATUS_TX_EMPTY) ? TIOCSER_TEMT : 0); - return put_user(result,value); -} - - -static int get_modem_info(struct async_struct * info, unsigned int *value) -{ - unsigned int result; - - result = TIOCM_CAR | TIOCM_DSR; - return put_user(result,value); -} - -static int set_modem_info(struct async_struct * info, unsigned int cmd, - unsigned int *value) -{ - unsigned int arg; - - if (get_user(arg, value)) - return -EFAULT; - switch (cmd) { - default: - return -EINVAL; - } - return 0; -} - -static int do_autoconfig(struct async_struct * info) -{ - int retval; - - if (!capable(CAP_SYS_ADMIN)) - return -EPERM; - - if (info->state->count > 1) - return -EBUSY; - - shutdown(info); - - autoconfig(info->state); - - retval = startup(info); - if (retval) - return retval; - return 0; -} - -/* - * rs_break() --- routine which turns the break handling on or off - */ -static void rs_break(struct tty_struct *tty, int break_state) -{ - struct async_struct * info = (struct async_struct *)tty->driver_data; - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_break")) - return; - - if (!info->port) - return; - save_flags(flags); cli(); - if (break_state == -1) - serial_outp(info, VAC_UART_MODE, - serial_inp(info, VAC_UART_MODE) | \ - VAC_UART_MODE_SEND_BREAK); - else - serial_outp(info, VAC_UART_MODE, - serial_inp(info, VAC_UART_MODE) & \ - ~VAC_UART_MODE_SEND_BREAK); - restore_flags(flags); -} - -static int rs_ioctl(struct tty_struct *tty, struct file * file, - unsigned int cmd, unsigned long arg) -{ - int error; - struct async_struct * info = (struct async_struct *)tty->driver_data; - struct async_icount cprev, cnow; /* kernel counter temps */ - struct serial_icounter_struct *p_cuser; /* user space */ - unsigned long flags; - - if (serial_paranoia_check(info, tty->name, "rs_ioctl")) - return -ENODEV; - - if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && - (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGSTRUCT) && - (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { - if (tty->flags & (1 << TTY_IO_ERROR)) - return -EIO; - } - - switch (cmd) { - case TIOCMGET: - return get_modem_info(info, (unsigned int *) arg); - case TIOCMBIS: - case TIOCMBIC: - case TIOCMSET: - return set_modem_info(info, cmd, (unsigned int *) arg); - case TIOCGSERIAL: - return get_serial_info(info, - (struct serial_struct *) arg); - case TIOCSSERIAL: - return set_serial_info(info, - (struct serial_struct *) arg); - case TIOCSERCONFIG: - return do_autoconfig(info); - - case TIOCSERGETLSR: /* Get line status register */ - return get_lsr_info(info, (unsigned int *) arg); - - case TIOCSERGSTRUCT: - if (copy_to_user((struct async_struct *) arg, - info, sizeof(struct async_struct))) - return -EFAULT; - return 0; - - /* - * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS)to change - * - mask passed in arg for lines of interest - * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) - * Caller should use TIOCGICOUNT to see which one it was - */ - case TIOCMIWAIT: - save_flags(flags); cli(); - /* note the counters on entry */ - cprev = info->state->icount; - restore_flags(flags); - while (1) { - interruptible_sleep_on(&info->delta_msr_wait); - /* see if a signal did it */ - if (signal_pending(current)) - return -ERESTARTSYS; - save_flags(flags); cli(); - cnow = info->state->icount; /* atomic copy */ - restore_flags(flags); - if (cnow.rng == cprev.rng && - cnow.dsr == cprev.dsr && - cnow.dcd == cprev.dcd && - cnow.cts == cprev.cts) - return -EIO; /* no change => error */ - if ( ((arg & TIOCM_RNG) && - (cnow.rng != cprev.rng)) || - ((arg & TIOCM_DSR) && - (cnow.dsr != cprev.dsr)) || - ((arg & TIOCM_CD) && - (cnow.dcd != cprev.dcd)) || - ((arg & TIOCM_CTS) && - (cnow.cts != cprev.cts)) ) { - return 0; - } - cprev = cnow; - } - /* NOTREACHED */ - - /* - * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) - * Return: write counters to the user passed counter struct - * NB: both 1->0 and 0->1 transitions are counted except for - * RI where only 0->1 is counted. - */ - case TIOCGICOUNT: - save_flags(flags); cli(); - cnow = info->state->icount; - restore_flags(flags); - p_cuser = (struct serial_icounter_struct *) arg; - error = put_user(cnow.cts, &p_cuser->cts); - if (error) return error; - error = put_user(cnow.dsr, &p_cuser->dsr); - if (error) return error; - error = put_user(cnow.rng, &p_cuser->rng); - if (error) return error; - error = put_user(cnow.dcd, &p_cuser->dcd); - if (error) return error; - error = put_user(cnow.rx, &p_cuser->rx); - if (error) return error; - error = put_user(cnow.tx, &p_cuser->tx); - if (error) return error; - error = put_user(cnow.frame, &p_cuser->frame); - if (error) return error; - error = put_user(cnow.overrun, &p_cuser->overrun); - if (error) return error; - error = put_user(cnow.parity, &p_cuser->parity); - if (error) return error; - error = put_user(cnow.brk, &p_cuser->brk); - if (error) return error; - error = put_user(cnow.buf_overrun, &p_cuser->buf_overrun); - - if (error) return error; - return 0; - - case TIOCSERGWILD: - case TIOCSERSWILD: - /* "setserial -W" is called in Debian boot */ - printk ("TIOCSER?WILD ioctl obsolete, ignored.\n"); - return 0; - - default: - return -ENOIOCTLCMD; - } - return 0; -} - -static void rs_set_termios(struct tty_struct *tty, struct termios *old_termios) -{ - struct async_struct *info = (struct async_struct *)tty->driver_data; - unsigned int cflag = tty->termios->c_cflag; - - if ( (cflag == old_termios->c_cflag) - && ( RELEVANT_IFLAG(tty->termios->c_iflag) - == RELEVANT_IFLAG(old_termios->c_iflag))) - return; - - change_speed(info); - - /* Handle turning off CRTSCTS */ - if ((old_termios->c_cflag & CRTSCTS) && - !(cflag & CRTSCTS)) { - tty->hw_stopped = 0; - rs_start(tty); - } - -} - -/* - * ------------------------------------------------------------ - * rs_close() - * - * This routine is called when the serial port gets closed. First, we - * wait for the last remaining data to be sent. Then, we unlink its - * async structure from the interrupt chain if necessary, and we free - * that IRQ if nothing is left in the chain. - * ------------------------------------------------------------ - */ -static void rs_close(struct tty_struct *tty, struct file * filp) -{ - struct async_struct * info = (struct async_struct *)tty->driver_data; - struct serial_state *state; - unsigned long flags; - - if (!info || serial_paranoia_check(info, tty->name, "rs_close")) - return; - - state = info->state; - - save_flags(flags); cli(); - - if (tty_hung_up_p(filp)) { - DBG_CNT("before DEC-hung"); - MOD_DEC_USE_COUNT; - restore_flags(flags); - return; - } - -#ifdef SERIAL_DEBUG_OPEN - baget_printk("rs_close ttys%d, count = %d\n", - info->line, state->count); -#endif - if ((tty->count == 1) && (state->count != 1)) { - /* - * Uh, oh. tty->count is 1, which means that the tty - * structure will be freed. state->count should always - * be one in these conditions. If it's greater than - * one, we've got real problems, since it means the - * serial port won't be shutdown. - */ - baget_printk("rs_close: bad serial port count; " - "tty->count is 1, " - "state->count is %d\n", state->count); - state->count = 1; - } - if (--state->count < 0) { - baget_printk("rs_close: bad serial port count for " - "ttys%d: %d\n", - info->line, state->count); - state->count = 0; - } - if (state->count) { - DBG_CNT("before DEC-2"); - MOD_DEC_USE_COUNT; - restore_flags(flags); - return; - } - info->flags |= ASYNC_CLOSING; - /* - * Now we wait for the transmit buffer to clear; and we notify - * the line discipline to only process XON/XOFF characters. - */ - tty->closing = 1; - if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) - tty_wait_until_sent(tty, info->closing_wait); - /* - * At this point we stop accepting input. To do this, we - * disable the receive line status interrupts, and tell the - * interrupt driver to stop checking the data ready bit in the - * line status register. - */ - info->IER &= ~(VAC_UART_INT_RX_BREAK_CHANGE | VAC_UART_INT_RX_ERRS); - info->read_status_mask &= ~VAC_UART_STATUS_RX_READY; - if (info->flags & ASYNC_INITIALIZED) { - serial_outw(info, VAC_UART_INT_MASK, info->IER); - /* - * Before we drop DTR, make sure the UART transmitter - * has completely drained; this is especially - * important if there is a transmit FIFO! - */ - rs_wait_until_sent(tty, info->timeout); - } - shutdown(info); - if (tty->driver->flush_buffer) - tty->driver->flush_buffer(tty); - if (tty->ldisc.flush_buffer) - tty->ldisc.flush_buffer(tty); - tty->closing = 0; - info->event = 0; - info->tty = 0; - if (info->blocked_open) { - if (info->close_delay) { - current->state = TASK_INTERRUPTIBLE; - schedule_timeout(info->close_delay); - } - wake_up_interruptible(&info->open_wait); - } - info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING); - wake_up_interruptible(&info->close_wait); - MOD_DEC_USE_COUNT; - restore_flags(flags); -} - -/* - * rs_wait_until_sent() --- wait until the transmitter is empty - */ -static void rs_wait_until_sent(struct tty_struct *tty, int timeout) -{ - struct async_struct * info = (struct async_struct *)tty->driver_data; - unsigned long orig_jiffies, char_time; - int lsr; - - if (serial_paranoia_check(info, tty->name, "rs_wait_until_sent")) - return; - - if (info->state->type == PORT_UNKNOWN) - return; - - if (info->xmit_fifo_size == 0) - return; /* Just in case.... */ - - orig_jiffies = jiffies; - /* - * Set the check interval to be 1/5 of the estimated time to - * send a single character, and make it at least 1. The check - * interval should also be less than the timeout. - * - * Note: we have to use pretty tight timings here to satisfy - * the NIST-PCTS. - */ - char_time = (info->timeout - HZ/50) / info->xmit_fifo_size; - char_time = char_time / 5; - if (char_time == 0) - char_time = 1; - if (timeout) - char_time = MIN(char_time, timeout); -#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT - baget_printk("In rs_wait_until_sent(%d) check=%lu...", - timeout, char_time); - baget_printk("jiff=%lu...", jiffies); -#endif - while (!((lsr = serial_inp(info, VAC_UART_INT_STATUS)) & \ - VAC_UART_STATUS_TX_EMPTY)) { -#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT - baget_printk("lsr = %d (jiff=%lu)...", lsr, jiffies); -#endif - current->state = TASK_INTERRUPTIBLE; - schedule_timeout(char_time); - if (signal_pending(current)) - break; - if (timeout && time_after(jiffies, orig_jiffies + timeout)) - break; - } - current->state = TASK_RUNNING; -#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT - baget_printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies); -#endif -} - -/* - * rs_hangup() --- called by tty_hangup() when a hangup is signaled. - */ -static void rs_hangup(struct tty_struct *tty) -{ - struct async_struct * info = (struct async_struct *)tty->driver_data; - struct serial_state *state = info->state; - - if (serial_paranoia_check(info, tty->name, "rs_hangup")) - return; - - state = info->state; - - rs_flush_buffer(tty); - shutdown(info); - info->event = 0; - state->count = 0; - info->flags &= ~ASYNC_NORMAL_ACTIVE; - info->tty = 0; - wake_up_interruptible(&info->open_wait); -} - -/* - * ------------------------------------------------------------ - * rs_open() and friends - * ------------------------------------------------------------ - */ -static int block_til_ready(struct tty_struct *tty, struct file * filp, - struct async_struct *info) -{ - DECLARE_WAITQUEUE(wait, current); - struct serial_state *state = info->state; - int retval; - int do_clocal = 0, extra_count = 0; - unsigned long flags; - - /* - * If the device is in the middle of being closed, then block - * until it's done, and then try again. - */ - if (tty_hung_up_p(filp) || - (info->flags & ASYNC_CLOSING)) { - if (info->flags & ASYNC_CLOSING) - interruptible_sleep_on(&info->close_wait); -#ifdef SERIAL_DO_RESTART - return ((info->flags & ASYNC_HUP_NOTIFY) ? - -EAGAIN : -ERESTARTSYS); -#else - return -EAGAIN; -#endif - } - - /* - * If non-blocking mode is set, or the port is not enabled, - * then make the check up front and then exit. - */ - if ((filp->f_flags & O_NONBLOCK) || - (tty->flags & (1 << TTY_IO_ERROR))) { - info->flags |= ASYNC_NORMAL_ACTIVE; - return 0; - } - - if (tty->termios->c_cflag & CLOCAL) - do_clocal = 1; - - /* - * Block waiting for the carrier detect and the line to become - * free (i.e., not in use by the callout). While we are in - * this loop, state->count is dropped by one, so that - * rs_close() knows when to free things. We restore it upon - * exit, either normal or abnormal. - */ - retval = 0; - add_wait_queue(&info->open_wait, &wait); -#ifdef SERIAL_DEBUG_OPEN - baget_printk("block_til_ready before block: ttys%d, count = %d\n", - state->line, state->count); -#endif - save_flags(flags); cli(); - if (!tty_hung_up_p(filp)) { - extra_count = 1; - state->count--; - } - restore_flags(flags); - info->blocked_open++; - while (1) { - set_current_state(TASK_INTERRUPTIBLE); - if (tty_hung_up_p(filp) || - !(info->flags & ASYNC_INITIALIZED)) { -#ifdef SERIAL_DO_RESTART - if (info->flags & ASYNC_HUP_NOTIFY) - retval = -EAGAIN; - else - retval = -ERESTARTSYS; -#else - retval = -EAGAIN; -#endif - break; - } - if (!(info->flags & ASYNC_CLOSING)) - break; - if (signal_pending(current)) { - retval = -ERESTARTSYS; - break; - } -#ifdef SERIAL_DEBUG_OPEN - baget_printk("block_til_ready blocking: ttys%d, count = %d\n", - info->line, state->count); -#endif - schedule(); - } - current->state = TASK_RUNNING; - remove_wait_queue(&info->open_wait, &wait); - if (extra_count) - state->count++; - info->blocked_open--; -#ifdef SERIAL_DEBUG_OPEN - baget_printk("block_til_ready after blocking: ttys%d, count = %d\n", - info->line, state->count); -#endif - if (retval) - return retval; - info->flags |= ASYNC_NORMAL_ACTIVE; - return 0; -} - -static int get_async_struct(int line, struct async_struct **ret_info) -{ - struct async_struct *info; - struct serial_state *sstate; - - sstate = rs_table + line; - sstate->count++; - if (sstate->info) { - *ret_info = sstate->info; - return 0; - } - info = kmalloc(sizeof(struct async_struct), GFP_KERNEL); - if (!info) { - sstate->count--; - return -ENOMEM; - } - memset(info, 0, sizeof(struct async_struct)); - init_waitqueue_head(&info->open_wait); - init_waitqueue_head(&info->close_wait); - init_waitqueue_head(&info->delta_msr_wait); - info->magic = SERIAL_MAGIC; - info->port = sstate->port; - info->flags = sstate->flags; - info->xmit_fifo_size = sstate->xmit_fifo_size; - info->line = line; - info->tqueue.routine = do_softint; - info->tqueue.data = info; - info->state = sstate; - if (sstate->info) { - kfree(info); - *ret_info = sstate->info; - return 0; - } - *ret_info = sstate->info = info; - return 0; -} - -/* - * This routine is called whenever a serial port is opened. It - * enables interrupts for a serial port, linking in its async structure into - * the IRQ chain. It also performs the serial-specific - * initialization for the tty structure. - */ -static int rs_open(struct tty_struct *tty, struct file * filp) -{ - struct async_struct *info; - int retval, line; - unsigned long page; - - MOD_INC_USE_COUNT; - line = tty->index; - if ((line < 0) || (line >= NR_PORTS)) { - MOD_DEC_USE_COUNT; - return -ENODEV; - } - retval = get_async_struct(line, &info); - if (retval) { - MOD_DEC_USE_COUNT; - return retval; - } - tty->driver_data = info; - info->tty = tty; - if (serial_paranoia_check(info, tty->name, "rs_open")) { - /* MOD_DEC_USE_COUNT; "info->tty" will cause this */ - return -ENODEV; - } - -#ifdef SERIAL_DEBUG_OPEN - baget_printk("rs_open %s, count = %d\n", tty->name, - info->state->count); -#endif - info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; - - if (!tmp_buf) { - page = get_zeroed_page(GFP_KERNEL); - if (!page) { - /* MOD_DEC_USE_COUNT; "info->tty" will cause this */ - return -ENOMEM; - } - if (tmp_buf) - free_page(page); - else - tmp_buf = (unsigned char *) page; - } - - /* - * If the port is the middle of closing, bail out now - */ - if (tty_hung_up_p(filp) || - (info->flags & ASYNC_CLOSING)) { - if (info->flags & ASYNC_CLOSING) - interruptible_sleep_on(&info->close_wait); - /* MOD_DEC_USE_COUNT; "info->tty" will cause this */ -#ifdef SERIAL_DO_RESTART - return ((info->flags & ASYNC_HUP_NOTIFY) ? - -EAGAIN : -ERESTARTSYS); -#else - return -EAGAIN; -#endif - } - - /* - * Start up serial port - */ - retval = startup(info); - if (retval) { - /* MOD_DEC_USE_COUNT; "info->tty" will cause this */ - return retval; - } - - retval = block_til_ready(tty, filp, info); - if (retval) { - /* MOD_DEC_USE_COUNT; "info->tty" will cause this */ -#ifdef SERIAL_DEBUG_OPEN - baget_printk("rs_open returning after block_til_ready " - "with %d\n", - retval); -#endif - return retval; - } - -#ifdef CONFIG_SERIAL_CONSOLE - if (sercons.cflag && sercons.index == line) { - tty->termios->c_cflag = sercons.cflag; - sercons.cflag = 0; - change_speed(info); - } -#endif - -#ifdef SERIAL_DEBUG_OPEN - baget_printk("rs_open %s successful...", tty->name); -#endif - return 0; -} - -/* - * /proc fs routines.... - */ - -static inline int line_info(char *buf, struct serial_state *state) -{ - struct async_struct *info = state->info, scr_info; - int ret; - - ret = sprintf(buf, "%d: uart:%s port:%X irq:%d", - state->line, uart_config[state->type].name, - state->port, state->irq); - - if (!state->port || (state->type == PORT_UNKNOWN)) { - ret += sprintf(buf+ret, "\n"); - return ret; - } - - /* - * Figure out the current RS-232 lines - */ - if (!info) { - info = &scr_info; /* This is just for serial_{in,out} */ - - info->magic = SERIAL_MAGIC; - info->port = state->port; - info->flags = state->flags; - info->quot = 0; - info->tty = 0; - } - - if (info->quot) { - ret += sprintf(buf+ret, " baud:%d", - state->baud_base / info->quot); - } - - ret += sprintf(buf+ret, " tx:%d rx:%d", - state->icount.tx, state->icount.rx); - - if (state->icount.frame) - ret += sprintf(buf+ret, " fe:%d", state->icount.frame); - - if (state->icount.parity) - ret += sprintf(buf+ret, " pe:%d", state->icount.parity); - - if (state->icount.brk) - ret += sprintf(buf+ret, " brk:%d", state->icount.brk); - - if (state->icount.overrun) - ret += sprintf(buf+ret, " oe:%d", state->icount.overrun); - - return ret; -} - -int rs_read_proc(char *page, char **start, off_t off, int count, - int *eof, void *data) -{ - int i, len = 0, l; - off_t begin = 0; - - len += sprintf(page, "serinfo:1.0 driver:%s\n", serial_version); - for (i = 0; i < NR_PORTS && len < 4000; i++) { - l = line_info(page + len, &rs_table[i]); - len += l; - if (len+begin > off+count) - goto done; - if (len+begin < off) { - begin += len; - len = 0; - } - } - *eof = 1; -done: - if (off >= len+begin) - return 0; - *start = page + (off-begin); - return ((count < begin+len-off) ? count : begin+len-off); -} - -/* - * --------------------------------------------------------------------- - * rs_init() and friends - * - * rs_init() is called at boot-time to initialize the serial driver. - * --------------------------------------------------------------------- - */ - -/* - * This routine prints out the appropriate serial driver version - * number, and identifies which options were configured into this - * driver. - */ -static _INLINE_ void show_serial_version(void) -{ - printk(KERN_INFO "%s version %s with", serial_name, serial_version); -#ifdef CONFIG_SERIAL_SHARE_IRQ - printk(" SHARE_IRQ"); -#endif -#define SERIAL_OPT -#ifdef CONFIG_SERIAL_DETECT_IRQ - printk(" DETECT_IRQ"); -#endif -#ifdef SERIAL_OPT - printk(" enabled\n"); -#else - printk(" no serial options enabled\n"); -#endif -#undef SERIAL_OPT -} - - -/* - * This routine is called by rs_init() to initialize a specific serial - * port. It determines what type of UART chip this serial port is - * using: 8250, 16450, 16550, 16550A. The important question is - * whether or not this UART is a 16550A or not, since this will - * determine whether or not we can use its FIFO features or not. - */ - -/* - * Functionality of this function is reduced: we already know we have a VAC, - * but still need to perform some important actions (see code :-). - */ -static void autoconfig(struct serial_state * state) -{ - struct async_struct *info, scr_info; - unsigned long flags; - - /* Setting up important parameters */ - state->type = VAC_UART_TYPE; - state->xmit_fifo_size = uart_config[state->type].dfl_xmit_fifo_size; - - info = &scr_info; /* This is just for serial_{in,out} */ - - info->magic = SERIAL_MAGIC; - info->port = state->port; - info->flags = state->flags; - - save_flags(flags); cli(); - - /* + Flush VAC input fifo */ - (void)serial_in(info, VAC_UART_RX); - (void)serial_in(info, VAC_UART_RX); - (void)serial_in(info, VAC_UART_RX); - (void)serial_in(info, VAC_UART_RX); - - /* Disable interrupts */ - serial_outp(info, VAC_UART_INT_MASK, 0); - - restore_flags(flags); -} - -int register_serial(struct serial_struct *req); -void unregister_serial(int line); - -EXPORT_SYMBOL(register_serial); -EXPORT_SYMBOL(unregister_serial); - -/* - * Important function for VAC UART check and reanimation. - */ - -static void rs_timer(unsigned long dummy) -{ - static unsigned long last_strobe = 0; - struct async_struct *info; - unsigned int i; - unsigned long flags; - - if ((jiffies - last_strobe) >= RS_STROBE_TIME) { - for (i=1; i < NR_IRQS; i++) { - info = IRQ_ports[i]; - if (!info) - continue; - save_flags(flags); cli(); -#ifdef CONFIG_SERIAL_SHARE_IRQ - if (info->next_port) { - do { - serial_out(info, VAC_UART_INT_MASK, 0); - info->IER |= VAC_UART_INT_TX_EMPTY; - serial_out(info, VAC_UART_INT_MASK, - info->IER); - info = info->next_port; - } while (info); - rs_interrupt(i, NULL, NULL); - } else -#endif /* CONFIG_SERIAL_SHARE_IRQ */ - rs_interrupt_single(i, NULL, NULL); - restore_flags(flags); - } - } - last_strobe = jiffies; - mod_timer(&vacs_timer, jiffies + RS_STROBE_TIME); - - /* - * It looks this code for case we share IRQ with console... - */ - - if (IRQ_ports[0]) { - save_flags(flags); cli(); -#ifdef CONFIG_SERIAL_SHARE_IRQ - rs_interrupt(0, NULL, NULL); -#else - rs_interrupt_single(0, NULL, NULL); -#endif - restore_flags(flags); - - mod_timer(&vacs_timer, jiffies + IRQ_timeout[0] - 2); - } -} - -static struct tty_operations rs_ops = { - .open = rs_open, - .close = rs_close, - .write = rs_write, - .put_char = rs_put_char, - .flush_chars = rs_flush_chars, - .write_room = rs_write_room, - .chars_in_buffer = rs_chars_in_buffer, - .flush_buffer = rs_flush_buffer, - .ioctl = rs_ioctl, - .throttle = rs_throttle, - .unthrottle = rs_unthrottle, - .send_xchar = rs_send_xchar, - .set_termios = rs_set_termios, - .stop = rs_stop, - .start = rs_start, - .hangup = rs_hangup, - .break_ctl = rs_break, - .wait_until_sent = rs_wait_until_sent, - .read_proc = rs_read_proc, -}; - -/* - * The serial driver boot-time initialization code! - */ -int __init rs_init(void) -{ - int i; - struct serial_state * state; - extern void atomwide_serial_init (void); - extern void dualsp_serial_init (void); - -#ifdef CONFIG_ATOMWIDE_SERIAL - atomwide_serial_init (); -#endif -#ifdef CONFIG_DUALSP_SERIAL - dualsp_serial_init (); -#endif - - init_bh(SERIAL_BH, do_serial_bh); - init_timer(&vacs_timer); - vacs_timer.function = rs_timer; - vacs_timer.expires = 0; - - for (i = 0; i < NR_IRQS; i++) { - IRQ_ports[i] = 0; - IRQ_timeout[i] = 0; - } - - -/* - * It is not a good idea to share interrupts with console, - * but it looks we cannot avoid it. - */ -#if 0 - -#ifdef CONFIG_SERIAL_CONSOLE - /* - * The interrupt of the serial console port - * can't be shared. - */ - if (sercons.flags & CON_CONSDEV) { - for(i = 0; i < NR_PORTS; i++) - if (i != sercons.index && - rs_table[i].irq == rs_table[sercons.index].irq) - rs_table[i].irq = 0; - } -#endif - -#endif - serial_driver = alloc_tty_driver(NR_PORTS); - if (!serial_driver) - return -ENOMEM; - - show_serial_version(); - - /* Initialize the tty_driver structure */ - - serial_driver->driver_name = "serial"; - serial_driver->name = "ttyS"; - serial_driver->major = TTY_MAJOR; - serial_driver->minor_start = 64; - serial_driver->type = TTY_DRIVER_TYPE_SERIAL; - serial_driver->subtype = SERIAL_TYPE_NORMAL; - serial_driver->init_termios = tty_std_termios; - serial_driver->init_termios.c_cflag = - B9600 | CS8 | CREAD | HUPCL | CLOCAL; - serial_driver->flags = TTY_DRIVER_REAL_RAW; - tty_set_operations(serial_driver, &rs_ops); - - if (tty_register_driver(serial_driver)) - panic("Couldn't register serial driver\n"); - - for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) { - state->magic = SSTATE_MAGIC; - state->line = i; - state->type = PORT_UNKNOWN; - state->custom_divisor = 0; - state->close_delay = 5*HZ/10; - state->closing_wait = 30*HZ; - state->icount.cts = state->icount.dsr = - state->icount.rng = state->icount.dcd = 0; - state->icount.rx = state->icount.tx = 0; - state->icount.frame = state->icount.parity = 0; - state->icount.overrun = state->icount.brk = 0; - state->irq = state->irq; - if (check_region(state->port,8)) - continue; - if (state->flags & ASYNC_BOOT_AUTOCONF) - autoconfig(state); - } - - /* - * Detect the IRQ only once every port is initialised, - * because some 16450 do not reset to 0 the MCR register. - */ - for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) { - if (state->type == PORT_UNKNOWN) - continue; - printk(KERN_INFO "ttyS%02d%s at 0x%04x (irq = %d) is a %s\n", - state->line, - (state->flags & ASYNC_FOURPORT) ? " FourPort" : "", - state->port, state->irq, - uart_config[state->type].name); - } - return 0; -} - -/* - * register_serial and unregister_serial allows for serial ports to be - * configured at run-time, to support PCMCIA modems. - */ -int register_serial(struct serial_struct *req) -{ - int i; - unsigned long flags; - struct serial_state *state; - - save_flags(flags); - cli(); - for (i = 0; i < NR_PORTS; i++) { - if (rs_table[i].port == req->port) - break; - } - if (i == NR_PORTS) { - for (i = 0; i < NR_PORTS; i++) - if ((rs_table[i].type == PORT_UNKNOWN) && - (rs_table[i].count == 0)) - break; - } - if (i == NR_PORTS) { - restore_flags(flags); - return -1; - } - state = &rs_table[i]; - if (rs_table[i].count) { - restore_flags(flags); - printk("Couldn't configure serial #%d (port=%d,irq=%d): " - "device already open\n", i, req->port, req->irq); - return -1; - } - state->irq = req->irq; - state->port = req->port; - state->flags = req->flags; - - autoconfig(state); - if (state->type == PORT_UNKNOWN) { - restore_flags(flags); - printk("register_serial(): autoconfig failed\n"); - return -1; - } - restore_flags(flags); - - printk(KERN_INFO "tty%02d at 0x%04x (irq = %d) is a %s\n", - state->line, state->port, state->irq, - uart_config[state->type].name); - return state->line; -} - -void unregister_serial(int line) -{ - unsigned long flags; - struct serial_state *state = &rs_table[line]; - - save_flags(flags); - cli(); - if (state->info && state->info->tty) - tty_hangup(state->info->tty); - state->type = PORT_UNKNOWN; - printk(KERN_INFO "tty%02d unloaded\n", state->line); - restore_flags(flags); -} - -#ifdef MODULE -int init_module(void) -{ - return rs_init(); -} - -void cleanup_module(void) -{ - unsigned long flags; - int e1, e2; - int i; - - printk("Unloading %s: version %s\n", serial_name, serial_version); - save_flags(flags); - cli(); - - del_timer_sync(&vacs_timer); - remove_bh(SERIAL_BH); - - if ((e1 = tty_unregister_driver(serial_driver))) - printk("SERIAL: failed to unregister serial driver (%d)\n", - e1); - restore_flags(flags); - put_tty_driver(serial_driver); - - for (i = 0; i < NR_PORTS; i++) { - if (rs_table[i].type != PORT_UNKNOWN) - release_region(rs_table[i].port, 8); - } - if (tmp_buf) { - free_page((unsigned long) tmp_buf); - tmp_buf = NULL; - } -} -#endif /* MODULE */ - - -/* - * ------------------------------------------------------------ - * Serial console driver - * ------------------------------------------------------------ - */ -#ifdef CONFIG_SERIAL_CONSOLE - -#define BOTH_EMPTY (VAC_UART_STATUS_TX_EMPTY | VAC_UART_STATUS_TX_EMPTY) - -/* - * Wait for transmitter & holding register to empty - */ -static inline void wait_for_xmitr(struct async_struct *info) -{ - int lsr; - unsigned int tmout = 1000000; - - do { - lsr = serial_inp(info, VAC_UART_INT_STATUS); - if (--tmout == 0) break; - } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY); -} - -/* - * Print a string to the serial port trying not to disturb - * any possible real use of the port... - */ -static void serial_console_write(struct console *co, const char *s, - unsigned count) -{ - struct serial_state *ser; - int ier; - unsigned i; - struct async_struct scr_info; /* serial_{in,out} because HUB6 */ - - ser = rs_table + co->index; - scr_info.magic = SERIAL_MAGIC; - scr_info.port = ser->port; - scr_info.flags = ser->flags; - - /* - * First save the IER then disable the interrupts - */ - ier = serial_inp(&scr_info, VAC_UART_INT_MASK); - serial_outw(&scr_info, VAC_UART_INT_MASK, 0x00); - - /* - * Now, do each character - */ - for (i = 0; i < count; i++, s++) { - wait_for_xmitr(&scr_info); - - /* - * Send the character out. - * If a LF, also do CR... - */ - serial_outp(&scr_info, VAC_UART_TX, (unsigned short)*s << 8); - if (*s == 10) { - wait_for_xmitr(&scr_info); - serial_outp(&scr_info, VAC_UART_TX, 13 << 8); - } - } - - /* - * Finally, Wait for transmitter & holding register to empty - * and restore the IER - */ - wait_for_xmitr(&scr_info); - serial_outp(&scr_info, VAC_UART_INT_MASK, ier); -} - -static struct tty_driver *serial_console_device(struct console *c, int *index) -{ - *index = c->index; - return serial_driver; -} - -/* - * Setup initial baud/bits/parity. We do two things here: - * - construct a cflag setting for the first rs_open() - * - initialize the serial port - * Return non-zero if we didn't find a serial port. - */ -static int __init serial_console_setup(struct console *co, char *options) -{ - struct serial_state *ser; - unsigned cval; - int baud = 9600; - int bits = 8; - int parity = 'n'; - int cflag = CREAD | HUPCL | CLOCAL; - int quot = 0; - char *s; - struct async_struct scr_info; /* serial_{in,out} because HUB6 */ - - if (options) { - baud = simple_strtoul(options, NULL, 10); - s = options; - while(*s >= '0' && *s <= '9') - s++; - if (*s) parity = *s++; - if (*s) bits = *s - '0'; - } - - /* - * Now construct a cflag setting. - */ - switch(baud) { - case 1200: - cflag |= B1200; - break; - case 2400: - cflag |= B2400; - break; - case 4800: - cflag |= B4800; - break; - case 19200: - cflag |= B19200; - break; - case 38400: - cflag |= B38400; - break; - case 57600: - cflag |= B57600; - break; - case 115200: - cflag |= B115200; - break; - case 9600: - default: - cflag |= B9600; - break; - } - switch(bits) { - case 7: - cflag |= CS7; - break; - default: - case 8: - cflag |= CS8; - break; - } - switch(parity) { - case 'o': case 'O': - cflag |= PARODD; - break; - case 'e': case 'E': - cflag |= PARENB; - break; - } - co->cflag = cflag; - - /* - * Divisor, bytesize and parity - */ - ser = rs_table + co->index; - scr_info.magic = SERIAL_MAGIC; - scr_info.port = ser->port; - scr_info.flags = ser->flags; - - quot = ser->baud_base / baud; - cval = cflag & (CSIZE | CSTOPB); - - cval >>= 4; - - cval &= ~VAC_UART_MODE_PARITY_ENABLE; - if (cflag & PARENB) - cval |= VAC_UART_MODE_PARITY_ENABLE; - if (cflag & PARODD) - cval |= VAC_UART_MODE_PARITY_ODD; - - /* - * Disable UART interrupts, set DTR and RTS high - * and set speed. - */ - switch (baud) { - default: - case 9600: - cval |= VAC_UART_MODE_BAUD(7); - break; - case 4800: - cval |= VAC_UART_MODE_BAUD(6); - break; - case 2400: - cval |= VAC_UART_MODE_BAUD(5); - break; - case 1200: - cval |= VAC_UART_MODE_BAUD(4); - break; - case 600: - cval |= VAC_UART_MODE_BAUD(3); - break; - case 300: - cval |= VAC_UART_MODE_BAUD(2); - break; -#ifndef QUAD_UART_SPEED - case 150: -#else - case 38400: -#endif - cval |= VAC_UART_MODE_BAUD(1); - break; -#ifndef QUAD_UART_SPEED - case 75: -#else - case 19200: -#endif - cval |= VAC_UART_MODE_BAUD(0); - break; - } - - /* Baget VAC need some adjustments for computed value */ - cval = vac_uart_mode_fixup(cval); - - serial_outp(&scr_info, VAC_UART_MODE, cval); - serial_outp(&scr_info, VAC_UART_INT_MASK, 0); - - return 0; -} - -static struct console sercons = { - .name = "ttyS", - .write = serial_console_write, - .device = serial_console_device, - .setup = serial_console_setup, - .flags = CON_PRINTBUFFER, - .index = -1, -}; - -/* - * Register console. - */ -long __init serial_console_init(long kmem_start, long kmem_end) -{ - register_console(&sercons); - return kmem_start; -} -#endif - -#ifdef CONFIG_REMOTE_DEBUG -#undef PRINT_DEBUG_PORT_INFO - -/* - * This is the interface to the remote debugger stub. - * I've put that here to be able to control the serial - * device more directly. - */ - -static int initialized; - -static int rs_debug_init(struct async_struct *info) -{ - int quot; - - autoconfig(info); /* autoconfigure ttyS0, whatever that is */ - -#ifdef PRINT_DEBUG_PORT_INFO - baget_printk("kgdb debug interface:: tty%02d at 0x%04x", - info->line, info->port); - switch (info->type) { - case PORT_8250: - baget_printk(" is a 8250\n"); - break; - case PORT_16450: - baget_printk(" is a 16450\n"); - break; - case PORT_16550: - baget_printk(" is a 16550\n"); - break; - case PORT_16550A: - baget_printk(" is a 16550A\n"); - break; - case PORT_16650: - baget_printk(" is a 16650\n"); - break; - default: - baget_printk(" is of unknown type -- unusable\n"); - break; - } -#endif - - if (info->port == PORT_UNKNOWN) - return -1; - - /* - * Clear all interrupts - */ - - (void)serial_inp(info, VAC_UART_INT_STATUS); - (void)serial_inp(info, VAC_UART_RX); - - /* - * Now, initialize the UART - */ - serial_outp(info,VAC_UART_MODE,VAC_UART_MODE_INITIAL); /* reset DLAB */ - if (info->flags & ASYNC_FOURPORT) { - info->MCR = UART_MCR_DTR | UART_MCR_RTS; - info->MCR_noint = UART_MCR_DTR | UART_MCR_OUT1; - } else { - info->MCR = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2; - info->MCR_noint = UART_MCR_DTR | UART_MCR_RTS; - } - - info->MCR = info->MCR_noint; /* no interrupts, please */ - /* - * and set the speed of the serial port - * (currently hardwired to 9600 8N1 - */ - - quot = info->baud_base / 9600; /* baud rate is fixed to 9600 */ - /* FIXME: if rs_debug interface is needed, we need to set speed here */ - - return 0; -} - -int putDebugChar(char c) -{ - struct async_struct *info = rs_table; - - if (!initialized) { /* need to init device first */ - if (rs_debug_init(info) == 0) - initialized = 1; - else - return 0; - } - - while ((serial_inw(info, VAC_UART_INT_STATUS) & \ - VAC_UART_STATUS_TX_EMPTY) == 0) - ; - serial_out(info, VAC_UART_TX, (unsigned short)c << 8); - - return 1; -} - -char getDebugChar(void) -{ - struct async_struct *info = rs_table; - - if (!initialized) { /* need to init device first */ - if (rs_debug_init(info) == 0) - initialized = 1; - else - return 0; - } - while (!(serial_inw(info, VAC_UART_INT_STATUS) & \ - VAC_UART_STATUS_RX_READY)) - ; - - return(serial_inp(info, VAC_UART_RX)); -} - -#endif /* CONFIG_REMOTE_DEBUG */ --- linux-2.5.73/arch/mips/baget/wbflush.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,24 +0,0 @@ -/* - * Setup the right wbflush routine for Baget/MIPS. - * - * Copyright (C) 1999 Gleb Raiko & Vladimir Roganov - */ - -#include -#include - -void (*__wbflush) (void); - -static void wbflush_baget(void); - -void __init wbflush_setup(void) -{ - __wbflush = wbflush_baget; -} - -/* - * Baget/MIPS doesn't need to write back the WB. - */ -static void wbflush_baget(void) -{ -} --- linux-2.5.73/arch/mips/boot/addinitrd.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/boot/addinitrd.c 2003-06-27 15:56:23.000000000 -0700 @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include "ecoff.h" @@ -44,7 +46,7 @@ int main (int argc, char *argv[]) char buf[1024]; unsigned long loadaddr; unsigned long initrd_header[2]; - int i; + int i,cnt; int swab = 0; if (argc != 4) { @@ -60,7 +62,6 @@ int main (int argc, char *argv[]) die ("read aout header"); if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs) die ("read section headers"); - /* * check whether the file is good for us */ @@ -81,7 +82,7 @@ int main (int argc, char *argv[]) die ("open initrd"); if (fstat (fd_initrd, &st) < 0) die ("fstat initrd"); - loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size) + loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size) + MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8; if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size))) loadaddr += MIPS_PAGE_SIZE; @@ -98,9 +99,20 @@ int main (int argc, char *argv[]) die ("write aout header"); if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs) die ("write section headers"); - while ((i = read (fd_vmlinux, buf, sizeof buf)) > 0) + /* skip padding */ + if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1) + die ("lseek vmlinux"); + if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1) + die ("lseek outfile"); + /* copy text segment */ + cnt = SWAB(eaout.tsize); + while (cnt) { + if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0) + die ("read vmlinux"); if (write (fd_outfile, buf, i) != i) die ("write vmlinux"); + cnt -= i; + } if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header) die ("write initrd header"); while ((i = read (fd_initrd, buf, sizeof buf)) > 0) --- linux-2.5.73/arch/mips/boot/elf2ecoff.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/boot/elf2ecoff.c 2003-06-27 15:56:23.000000000 -0700 @@ -41,487 +41,114 @@ #include #include #include +#include +#include #include "ecoff.h" /* * Some extra ELF definitions */ -#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ +#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ /* -------------------------------------------------------------------- */ struct sect { - unsigned long vaddr; - unsigned long len; + unsigned long vaddr; + unsigned long len; }; -int phcmp (); -char *saveRead (int file, off_t offset, off_t len, char *name); -int copy (int, int, off_t, off_t); -int translate_syms (int, int, off_t, off_t, off_t, off_t); -void convert_elf_hdr (Elf32_Ehdr *); -void convert_elf_phdrs (Elf32_Phdr *, int); -void convert_elf_shdrs (Elf32_Shdr *, int); -void convert_ecoff_filehdr(struct filehdr *); -void convert_ecoff_aouthdr(struct aouthdr *); -void convert_ecoff_esecs(struct scnhdr *, int); -extern int errno; int *symTypeTable; int must_convert_endian = 0; int format_bigendian = 0; -main (int argc, char **argv, char **envp) +static void copy(int out, int in, off_t offset, off_t size) { - Elf32_Ehdr ex; - Elf32_Phdr *ph; - Elf32_Shdr *sh; - Elf32_Sym *symtab; - char *shstrtab; - int strtabix, symtabix; - int i, pad; - struct sect text, data, bss; - struct filehdr efh; - struct aouthdr eah; - struct scnhdr esecs [6]; - int infile, outfile; - unsigned long cur_vma = ULONG_MAX; - int addflag = 0; - int nosecs; - - text.len = data.len = bss.len = 0; - text.vaddr = data.vaddr = bss.vaddr = 0; - - /* Check args... */ - if (argc < 3 || argc > 4) - { - usage: - fprintf (stderr, - "usage: elf2aout [-a]\n"); - exit (1); - } - if (argc == 4) - { - if (strcmp (argv [3], "-a")) - goto usage; - addflag = 1; - } - - /* Try the input file... */ - if ((infile = open (argv [1], O_RDONLY)) < 0) - { - fprintf (stderr, "Can't open %s for read: %s\n", - argv [1], strerror (errno)); - exit (1); - } - - /* Read the header, which is at the beginning of the file... */ - i = read (infile, &ex, sizeof ex); - if (i != sizeof ex) - { - fprintf (stderr, "ex: %s: %s.\n", - argv [1], i ? strerror (errno) : "End of file reached"); - exit (1); - } - - if (ex.e_ident[EI_DATA] == ELFDATA2MSB) - format_bigendian = 1; - - if (ntohs (0xaa55) == 0xaa55) { - if (!format_bigendian) - must_convert_endian = 1; - } else { - if (format_bigendian) - must_convert_endian = 1; - } - if (must_convert_endian) - convert_elf_hdr (&ex); - - /* Read the program headers... */ - ph = (Elf32_Phdr *)saveRead (infile, ex.e_phoff, - ex.e_phnum * sizeof (Elf32_Phdr), "ph"); - if (must_convert_endian) - convert_elf_phdrs (ph, ex.e_phnum); - /* Read the section headers... */ - sh = (Elf32_Shdr *)saveRead (infile, ex.e_shoff, - ex.e_shnum * sizeof (Elf32_Shdr), "sh"); - if (must_convert_endian) - convert_elf_shdrs (sh, ex.e_shnum); - /* Read in the section string table. */ - shstrtab = saveRead (infile, sh [ex.e_shstrndx].sh_offset, - sh [ex.e_shstrndx].sh_size, "shstrtab"); - - /* Figure out if we can cram the program header into an ECOFF - header... Basically, we can't handle anything but loadable - segments, but we can ignore some kinds of segments. We can't - handle holes in the address space. Segments may be out of order, - so we sort them first. */ - - qsort (ph, ex.e_phnum, sizeof (Elf32_Phdr), phcmp); - - for (i = 0; i < ex.e_phnum; i++) - { - /* Section types we can ignore... */ - if (ph [i].p_type == PT_NULL || ph [i].p_type == PT_NOTE || - ph [i].p_type == PT_PHDR || ph [i].p_type == PT_MIPS_REGINFO) - continue; - /* Section types we can't handle... */ - else if (ph [i].p_type != PT_LOAD) - { - fprintf (stderr, "Program header %d type %d can't be converted.\n"); - exit (1); - } - /* Writable (data) segment? */ - if (ph [i].p_flags & PF_W) - { - struct sect ndata, nbss; + char ibuf[4096]; + int remaining, cur, count; - ndata.vaddr = ph [i].p_vaddr; - ndata.len = ph [i].p_filesz; - nbss.vaddr = ph [i].p_vaddr + ph [i].p_filesz; - nbss.len = ph [i].p_memsz - ph [i].p_filesz; + /* Go to the start of the ELF symbol table... */ + if (lseek(in, offset, SEEK_SET) < 0) { + perror("copy: lseek"); + exit(1); + } + + remaining = size; + while (remaining) { + cur = remaining; + if (cur > sizeof ibuf) + cur = sizeof ibuf; + remaining -= cur; + if ((count = read(in, ibuf, cur)) != cur) { + fprintf(stderr, "copy: read: %s\n", + count ? strerror(errno) : + "premature end of file"); + exit(1); + } + if ((count = write(out, ibuf, cur)) != cur) { + perror("copy: write"); + exit(1); + } + } +} - combine (&data, &ndata, 0); - combine (&bss, &nbss, 1); +/* + * Combine two segments, which must be contiguous. If pad is true, it's + * okay for there to be padding between. + */ +static void combine(struct sect *base, struct sect *new, int pad) +{ + if (!base->len) + *base = *new; + else if (new->len) { + if (base->vaddr + base->len != new->vaddr) { + if (pad) + base->len = new->vaddr - base->vaddr; + else { + fprintf(stderr, + "Non-contiguous data can't be converted.\n"); + exit(1); + } + } + base->len += new->len; } - else - { - struct sect ntxt; +} - ntxt.vaddr = ph [i].p_vaddr; - ntxt.len = ph [i].p_filesz; +static int phcmp(const void *v1, const void *v2) +{ + const Elf32_Phdr *h1 = v1; + const Elf32_Phdr *h2 = v2; - combine (&text, &ntxt, 0); - } - /* Remember the lowest segment start address. */ - if (ph [i].p_vaddr < cur_vma) - cur_vma = ph [i].p_vaddr; - } - - /* Sections must be in order to be converted... */ - if (text.vaddr > data.vaddr || data.vaddr > bss.vaddr || - text.vaddr + text.len > data.vaddr || data.vaddr + data.len > bss.vaddr) - { - fprintf (stderr, "Sections ordering prevents a.out conversion.\n"); - exit (1); - } - - /* If there's a data section but no text section, then the loader - combined everything into one section. That needs to be the - text section, so just make the data section zero length following - text. */ - if (data.len && !text.len) - { - text = data; - data.vaddr = text.vaddr + text.len; - data.len = 0; - } - - /* If there is a gap between text and data, we'll fill it when we copy - the data, so update the length of the text segment as represented in - a.out to reflect that, since a.out doesn't allow gaps in the program - address space. */ - if (text.vaddr + text.len < data.vaddr) - text.len = data.vaddr - text.vaddr; - - /* We now have enough information to cons up an a.out header... */ - eah.magic = OMAGIC; - eah.vstamp = 200; - eah.tsize = text.len; - eah.dsize = data.len; - eah.bsize = bss.len; - eah.entry = ex.e_entry; - eah.text_start = text.vaddr; - eah.data_start = data.vaddr; - eah.bss_start = bss.vaddr; - eah.gprmask = 0xf3fffffe; - memset (&eah.cprmask, '\0', sizeof eah.cprmask); - eah.gp_value = 0; /* unused. */ - - if (format_bigendian) - efh.f_magic = MIPSEBMAGIC; - else - efh.f_magic = MIPSELMAGIC; - if (addflag) - nosecs = 6; - else - nosecs = 3; - efh.f_nscns = nosecs; - efh.f_timdat = 0; /* bogus */ - efh.f_symptr = 0; - efh.f_nsyms = 0; - efh.f_opthdr = sizeof eah; - efh.f_flags = 0x100f; /* Stripped, not sharable. */ - - memset (esecs, 0, sizeof esecs); - strcpy (esecs [0].s_name, ".text"); - strcpy (esecs [1].s_name, ".data"); - strcpy (esecs [2].s_name, ".bss"); - if (addflag) { - strcpy (esecs [3].s_name, ".rdata"); - strcpy (esecs [4].s_name, ".sdata"); - strcpy (esecs [5].s_name, ".sbss"); - } - esecs [0].s_paddr = esecs [0].s_vaddr = eah.text_start; - esecs [1].s_paddr = esecs [1].s_vaddr = eah.data_start; - esecs [2].s_paddr = esecs [2].s_vaddr = eah.bss_start; - if (addflag) { - esecs [3].s_paddr = esecs [3].s_vaddr = 0; - esecs [4].s_paddr = esecs [4].s_vaddr = 0; - esecs [5].s_paddr = esecs [5].s_vaddr = 0; - } - esecs [0].s_size = eah.tsize; - esecs [1].s_size = eah.dsize; - esecs [2].s_size = eah.bsize; - if (addflag) { - esecs [3].s_size = 0; - esecs [4].s_size = 0; - esecs [5].s_size = 0; - } - esecs [0].s_scnptr = N_TXTOFF (efh, eah); - esecs [1].s_scnptr = N_DATOFF (efh, eah); -#define ECOFF_SEGMENT_ALIGNMENT(a) 0x10 -#define ECOFF_ROUND(s,a) (((s)+(a)-1)&~((a)-1)) - esecs [2].s_scnptr = esecs [1].s_scnptr + - ECOFF_ROUND (esecs [1].s_size, ECOFF_SEGMENT_ALIGNMENT (&eah)); - if (addflag) { - esecs [3].s_scnptr = 0; - esecs [4].s_scnptr = 0; - esecs [5].s_scnptr = 0; - } - esecs [0].s_relptr = esecs [1].s_relptr - = esecs [2].s_relptr = 0; - esecs [0].s_lnnoptr = esecs [1].s_lnnoptr - = esecs [2].s_lnnoptr = 0; - esecs [0].s_nreloc = esecs [1].s_nreloc = esecs [2].s_nreloc = 0; - esecs [0].s_nlnno = esecs [1].s_nlnno = esecs [2].s_nlnno = 0; - if (addflag) { - esecs [3].s_relptr = esecs [4].s_relptr - = esecs [5].s_relptr = 0; - esecs [3].s_lnnoptr = esecs [4].s_lnnoptr - = esecs [5].s_lnnoptr = 0; - esecs [3].s_nreloc = esecs [4].s_nreloc = esecs [5].s_nreloc = 0; - esecs [3].s_nlnno = esecs [4].s_nlnno = esecs [5].s_nlnno = 0; - } - esecs [0].s_flags = 0x20; - esecs [1].s_flags = 0x40; - esecs [2].s_flags = 0x82; - if (addflag) { - esecs [3].s_flags = 0x100; - esecs [4].s_flags = 0x200; - esecs [5].s_flags = 0x400; - } - - /* Make the output file... */ - if ((outfile = open (argv [2], O_WRONLY | O_CREAT, 0777)) < 0) - { - fprintf (stderr, "Unable to create %s: %s\n", argv [2], strerror (errno)); - exit (1); - } - - if (must_convert_endian) - convert_ecoff_filehdr (&efh); - /* Write the headers... */ - i = write (outfile, &efh, sizeof efh); - if (i != sizeof efh) - { - perror ("efh: write"); - exit (1); - - for (i = 0; i < nosecs; i++) - { - printf ("Section %d: %s phys %x size %x file offset %x\n", - i, esecs [i].s_name, esecs [i].s_paddr, - esecs [i].s_size, esecs [i].s_scnptr); - } - } - fprintf (stderr, "wrote %d byte file header.\n", i); - - if (must_convert_endian) - convert_ecoff_aouthdr (&eah); - i = write (outfile, &eah, sizeof eah); - if (i != sizeof eah) - { - perror ("eah: write"); - exit (1); - } - fprintf (stderr, "wrote %d byte a.out header.\n", i); - - if (must_convert_endian) - convert_ecoff_esecs (&esecs[0], nosecs); - i = write (outfile, &esecs, nosecs * sizeof(struct scnhdr)); - if (i != nosecs * sizeof(struct scnhdr)) - { - perror ("esecs: write"); - exit (1); - } - fprintf (stderr, "wrote %d bytes of section headers.\n", i); - - if (pad = ((sizeof efh + sizeof eah + nosecs * sizeof(struct scnhdr)) & 15)) - { - pad = 16 - pad; - i = write (outfile, "\0\0\0\0\0\0\0\0\0\0\0\0\0\0", pad); - if (i < 0) - { - perror ("ipad: write"); - exit (1); - } - fprintf (stderr, "wrote %d byte pad.\n", i); - } + if (h1->p_vaddr > h2->p_vaddr) + return 1; + else if (h1->p_vaddr < h2->p_vaddr) + return -1; + else + return 0; +} - /* Copy the loadable sections. Zero-fill any gaps less than 64k; - complain about any zero-filling, and die if we're asked to zero-fill - more than 64k. */ - for (i = 0; i < ex.e_phnum; i++) - { - /* Unprocessable sections were handled above, so just verify that - the section can be loaded before copying. */ - if (ph [i].p_type == PT_LOAD && ph [i].p_filesz) - { - if (cur_vma != ph [i].p_vaddr) - { - unsigned long gap = ph [i].p_vaddr - cur_vma; - char obuf [1024]; - if (gap > 65536) - { - fprintf (stderr, "Intersegment gap (%d bytes) too large.\n", - gap); - exit (1); - } - fprintf (stderr, "Warning: %d byte intersegment gap.\n", gap); - memset (obuf, 0, sizeof obuf); - while (gap) - { - int count = write (outfile, obuf, (gap > sizeof obuf - ? sizeof obuf : gap)); - if (count < 0) - { - fprintf (stderr, "Error writing gap: %s\n", - strerror (errno)); - exit (1); - } - gap -= count; - } - } -fprintf (stderr, "writing %d bytes...\n", ph [i].p_filesz); - copy (outfile, infile, ph [i].p_offset, ph [i].p_filesz); - cur_vma = ph [i].p_vaddr + ph [i].p_filesz; - } - } - - /* - * Write a page of padding for boot PROMS that read entire pages. - * Without this, they may attempt to read past the end of the - * data section, incur an error, and refuse to boot. - */ - { - char obuf[4096]; - memset(obuf, 0, sizeof obuf); - if (write(outfile, obuf, sizeof(obuf)) != sizeof(obuf)) { - fprintf(stderr, "Error writing PROM padding: %s\n", - strerror(errno)); - exit(1); - } - } - - /* Looks like we won... */ - exit (0); -} - -copy (out, in, offset, size) - int out, in; - off_t offset, size; -{ - char ibuf [4096]; - int remaining, cur, count; - - /* Go to the start of the ELF symbol table... */ - if (lseek (in, offset, SEEK_SET) < 0) - { - perror ("copy: lseek"); - exit (1); - } - - remaining = size; - while (remaining) - { - cur = remaining; - if (cur > sizeof ibuf) - cur = sizeof ibuf; - remaining -= cur; - if ((count = read (in, ibuf, cur)) != cur) - { - fprintf (stderr, "copy: read: %s\n", - count ? strerror (errno) : "premature end of file"); - exit (1); +static char *saveRead(int file, off_t offset, off_t len, char *name) +{ + char *tmp; + int count; + off_t off; + if ((off = lseek(file, offset, SEEK_SET)) < 0) { + fprintf(stderr, "%s: fseek: %s\n", name, strerror(errno)); + exit(1); } - if ((count = write (out, ibuf, cur)) != cur) - { - perror ("copy: write"); - exit (1); + if (!(tmp = (char *) malloc(len))) { + fprintf(stderr, "%s: Can't allocate %ld bytes.\n", name, + len); + exit(1); } - } -} - -/* Combine two segments, which must be contiguous. If pad is true, it's - okay for there to be padding between. */ -combine (base, new, pad) - struct sect *base, *new; - int pad; -{ - if (!base -> len) - *base = *new; - else if (new -> len) - { - if (base -> vaddr + base -> len != new -> vaddr) - { - if (pad) - base -> len = new -> vaddr - base -> vaddr; - else - { - fprintf (stderr, - "Non-contiguous data can't be converted.\n"); - exit (1); - } - } - base -> len += new -> len; - } -} - -phcmp (h1, h2) - Elf32_Phdr *h1, *h2; -{ - if (h1 -> p_vaddr > h2 -> p_vaddr) - return 1; - else if (h1 -> p_vaddr < h2 -> p_vaddr) - return -1; - else - return 0; -} - -char *saveRead (int file, off_t offset, off_t len, char *name) -{ - char *tmp; - int count; - off_t off; - if ((off = lseek (file, offset, SEEK_SET)) < 0) - { - fprintf (stderr, "%s: fseek: %s\n", name, strerror (errno)); - exit (1); - } - if (!(tmp = (char *)malloc (len))) - { - fprintf (stderr, "%s: Can't allocate %d bytes.\n", name, len); - exit (1); - } - count = read (file, tmp, len); - if (count != len) - { - fprintf (stderr, "%s: read: %s.\n", - name, count ? strerror (errno) : "End of file reached"); - exit (1); - } - return tmp; + count = read(file, tmp, len); + if (count != len) { + fprintf(stderr, "%s: read: %s.\n", + name, + count ? strerror(errno) : "End of file reached"); + exit(1); + } + return tmp; } #define swab16(x) \ @@ -536,101 +163,454 @@ char *saveRead (int file, off_t offset, (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \ (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) )) -void convert_elf_hdr (Elf32_Ehdr *e) +static void convert_elf_hdr(Elf32_Ehdr * e) { - e->e_type = swab16(e->e_type); - e->e_machine = swab16(e->e_machine); - e->e_version = swab32(e->e_version); - e->e_entry = swab32(e->e_entry); - e->e_phoff = swab32(e->e_phoff); - e->e_shoff = swab32(e->e_shoff); - e->e_flags = swab32(e->e_flags); - e->e_ehsize = swab16(e->e_ehsize); + e->e_type = swab16(e->e_type); + e->e_machine = swab16(e->e_machine); + e->e_version = swab32(e->e_version); + e->e_entry = swab32(e->e_entry); + e->e_phoff = swab32(e->e_phoff); + e->e_shoff = swab32(e->e_shoff); + e->e_flags = swab32(e->e_flags); + e->e_ehsize = swab16(e->e_ehsize); e->e_phentsize = swab16(e->e_phentsize); - e->e_phnum = swab16(e->e_phnum); + e->e_phnum = swab16(e->e_phnum); e->e_shentsize = swab16(e->e_shentsize); - e->e_shnum = swab16(e->e_shnum); - e->e_shstrndx = swab16(e->e_shstrndx); + e->e_shnum = swab16(e->e_shnum); + e->e_shstrndx = swab16(e->e_shstrndx); } -void convert_elf_phdrs (Elf32_Phdr *p, int num) +static void convert_elf_phdrs(Elf32_Phdr * p, int num) { int i; - for (i = 0; i < num; i++,p++) { - p->p_type = swab32(p->p_type); + for (i = 0; i < num; i++, p++) { + p->p_type = swab32(p->p_type); p->p_offset = swab32(p->p_offset); - p->p_vaddr = swab32(p->p_vaddr); - p->p_paddr = swab32(p->p_paddr); + p->p_vaddr = swab32(p->p_vaddr); + p->p_paddr = swab32(p->p_paddr); p->p_filesz = swab32(p->p_filesz); - p->p_memsz = swab32(p->p_memsz); - p->p_flags = swab32(p->p_flags); - p->p_align = swab32(p->p_align); + p->p_memsz = swab32(p->p_memsz); + p->p_flags = swab32(p->p_flags); + p->p_align = swab32(p->p_align); } } -void convert_elf_shdrs (Elf32_Shdr *s, int num) +static void convert_elf_shdrs(Elf32_Shdr * s, int num) { int i; - for (i = 0; i < num; i++,s++) { - s->sh_name = swab32(s->sh_name); - s->sh_type = swab32(s->sh_type); - s->sh_flags = swab32(s->sh_flags); - s->sh_addr = swab32(s->sh_addr); - s->sh_offset = swab32(s->sh_offset); - s->sh_size = swab32(s->sh_size); - s->sh_link = swab32(s->sh_link); - s->sh_info = swab32(s->sh_info); + for (i = 0; i < num; i++, s++) { + s->sh_name = swab32(s->sh_name); + s->sh_type = swab32(s->sh_type); + s->sh_flags = swab32(s->sh_flags); + s->sh_addr = swab32(s->sh_addr); + s->sh_offset = swab32(s->sh_offset); + s->sh_size = swab32(s->sh_size); + s->sh_link = swab32(s->sh_link); + s->sh_info = swab32(s->sh_info); s->sh_addralign = swab32(s->sh_addralign); - s->sh_entsize = swab32(s->sh_entsize); + s->sh_entsize = swab32(s->sh_entsize); } } -void convert_ecoff_filehdr(struct filehdr *f) +static void convert_ecoff_filehdr(struct filehdr *f) { - f->f_magic = swab16(f->f_magic); - f->f_nscns = swab16(f->f_nscns); + f->f_magic = swab16(f->f_magic); + f->f_nscns = swab16(f->f_nscns); f->f_timdat = swab32(f->f_timdat); f->f_symptr = swab32(f->f_symptr); - f->f_nsyms = swab32(f->f_nsyms); + f->f_nsyms = swab32(f->f_nsyms); f->f_opthdr = swab16(f->f_opthdr); - f->f_flags = swab16(f->f_flags); + f->f_flags = swab16(f->f_flags); } -void convert_ecoff_aouthdr(struct aouthdr *a) +static void convert_ecoff_aouthdr(struct aouthdr *a) { - a->magic = swab16(a->magic); - a->vstamp = swab16(a->vstamp); - a->tsize = swab32(a->tsize); - a->dsize = swab32(a->dsize); - a->bsize = swab32(a->bsize); - a->entry = swab32(a->entry); + a->magic = swab16(a->magic); + a->vstamp = swab16(a->vstamp); + a->tsize = swab32(a->tsize); + a->dsize = swab32(a->dsize); + a->bsize = swab32(a->bsize); + a->entry = swab32(a->entry); a->text_start = swab32(a->text_start); a->data_start = swab32(a->data_start); - a->bss_start = swab32(a->bss_start); - a->gprmask = swab32(a->gprmask); + a->bss_start = swab32(a->bss_start); + a->gprmask = swab32(a->gprmask); a->cprmask[0] = swab32(a->cprmask[0]); a->cprmask[1] = swab32(a->cprmask[1]); a->cprmask[2] = swab32(a->cprmask[2]); a->cprmask[3] = swab32(a->cprmask[3]); - a->gp_value = swab32(a->gp_value); + a->gp_value = swab32(a->gp_value); } -void convert_ecoff_esecs(struct scnhdr *s, int num) +static void convert_ecoff_esecs(struct scnhdr *s, int num) { int i; for (i = 0; i < num; i++, s++) { - s->s_paddr = swab32(s->s_paddr); - s->s_vaddr = swab32(s->s_vaddr); - s->s_size = swab32(s->s_size); - s->s_scnptr = swab32(s->s_scnptr); - s->s_relptr = swab32(s->s_relptr); + s->s_paddr = swab32(s->s_paddr); + s->s_vaddr = swab32(s->s_vaddr); + s->s_size = swab32(s->s_size); + s->s_scnptr = swab32(s->s_scnptr); + s->s_relptr = swab32(s->s_relptr); s->s_lnnoptr = swab32(s->s_lnnoptr); - s->s_nreloc = swab16(s->s_nreloc); - s->s_nlnno = swab16(s->s_nlnno); - s->s_flags = swab32(s->s_flags); + s->s_nreloc = swab16(s->s_nreloc); + s->s_nlnno = swab16(s->s_nlnno); + s->s_flags = swab32(s->s_flags); + } +} + +int main(int argc, char *argv[]) +{ + Elf32_Ehdr ex; + Elf32_Phdr *ph; + Elf32_Shdr *sh; + char *shstrtab; + int i, pad; + struct sect text, data, bss; + struct filehdr efh; + struct aouthdr eah; + struct scnhdr esecs[6]; + int infile, outfile; + unsigned long cur_vma = ULONG_MAX; + int addflag = 0; + int nosecs; + + text.len = data.len = bss.len = 0; + text.vaddr = data.vaddr = bss.vaddr = 0; + + /* Check args... */ + if (argc < 3 || argc > 4) { + usage: + fprintf(stderr, + "usage: elf2ecoff [-a]\n"); + exit(1); + } + if (argc == 4) { + if (strcmp(argv[3], "-a")) + goto usage; + addflag = 1; + } + + /* Try the input file... */ + if ((infile = open(argv[1], O_RDONLY)) < 0) { + fprintf(stderr, "Can't open %s for read: %s\n", + argv[1], strerror(errno)); + exit(1); + } + + /* Read the header, which is at the beginning of the file... */ + i = read(infile, &ex, sizeof ex); + if (i != sizeof ex) { + fprintf(stderr, "ex: %s: %s.\n", + argv[1], + i ? strerror(errno) : "End of file reached"); + exit(1); + } + + if (ex.e_ident[EI_DATA] == ELFDATA2MSB) + format_bigendian = 1; + + if (ntohs(0xaa55) == 0xaa55) { + if (!format_bigendian) + must_convert_endian = 1; + } else { + if (format_bigendian) + must_convert_endian = 1; + } + if (must_convert_endian) + convert_elf_hdr(&ex); + + /* Read the program headers... */ + ph = (Elf32_Phdr *) saveRead(infile, ex.e_phoff, + ex.e_phnum * sizeof(Elf32_Phdr), + "ph"); + if (must_convert_endian) + convert_elf_phdrs(ph, ex.e_phnum); + /* Read the section headers... */ + sh = (Elf32_Shdr *) saveRead(infile, ex.e_shoff, + ex.e_shnum * sizeof(Elf32_Shdr), + "sh"); + if (must_convert_endian) + convert_elf_shdrs(sh, ex.e_shnum); + /* Read in the section string table. */ + shstrtab = saveRead(infile, sh[ex.e_shstrndx].sh_offset, + sh[ex.e_shstrndx].sh_size, "shstrtab"); + + /* Figure out if we can cram the program header into an ECOFF + header... Basically, we can't handle anything but loadable + segments, but we can ignore some kinds of segments. We can't + handle holes in the address space. Segments may be out of order, + so we sort them first. */ + + qsort(ph, ex.e_phnum, sizeof(Elf32_Phdr), phcmp); + + for (i = 0; i < ex.e_phnum; i++) { + /* Section types we can ignore... */ + if (ph[i].p_type == PT_NULL || ph[i].p_type == PT_NOTE || + ph[i].p_type == PT_PHDR + || ph[i].p_type == PT_MIPS_REGINFO) + continue; + /* Section types we can't handle... */ + else if (ph[i].p_type != PT_LOAD) { + fprintf(stderr, + "Program header %d type %d can't be converted.\n", + ex.e_phnum, ph[i].p_type); + exit(1); + } + /* Writable (data) segment? */ + if (ph[i].p_flags & PF_W) { + struct sect ndata, nbss; + + ndata.vaddr = ph[i].p_vaddr; + ndata.len = ph[i].p_filesz; + nbss.vaddr = ph[i].p_vaddr + ph[i].p_filesz; + nbss.len = ph[i].p_memsz - ph[i].p_filesz; + + combine(&data, &ndata, 0); + combine(&bss, &nbss, 1); + } else { + struct sect ntxt; + + ntxt.vaddr = ph[i].p_vaddr; + ntxt.len = ph[i].p_filesz; + + combine(&text, &ntxt, 0); + } + /* Remember the lowest segment start address. */ + if (ph[i].p_vaddr < cur_vma) + cur_vma = ph[i].p_vaddr; + } + + /* Sections must be in order to be converted... */ + if (text.vaddr > data.vaddr || data.vaddr > bss.vaddr || + text.vaddr + text.len > data.vaddr + || data.vaddr + data.len > bss.vaddr) { + fprintf(stderr, + "Sections ordering prevents a.out conversion.\n"); + exit(1); + } + + /* If there's a data section but no text section, then the loader + combined everything into one section. That needs to be the + text section, so just make the data section zero length following + text. */ + if (data.len && !text.len) { + text = data; + data.vaddr = text.vaddr + text.len; + data.len = 0; + } + + /* If there is a gap between text and data, we'll fill it when we copy + the data, so update the length of the text segment as represented in + a.out to reflect that, since a.out doesn't allow gaps in the program + address space. */ + if (text.vaddr + text.len < data.vaddr) + text.len = data.vaddr - text.vaddr; + + /* We now have enough information to cons up an a.out header... */ + eah.magic = OMAGIC; + eah.vstamp = 200; + eah.tsize = text.len; + eah.dsize = data.len; + eah.bsize = bss.len; + eah.entry = ex.e_entry; + eah.text_start = text.vaddr; + eah.data_start = data.vaddr; + eah.bss_start = bss.vaddr; + eah.gprmask = 0xf3fffffe; + memset(&eah.cprmask, '\0', sizeof eah.cprmask); + eah.gp_value = 0; /* unused. */ + + if (format_bigendian) + efh.f_magic = MIPSEBMAGIC; + else + efh.f_magic = MIPSELMAGIC; + if (addflag) + nosecs = 6; + else + nosecs = 3; + efh.f_nscns = nosecs; + efh.f_timdat = 0; /* bogus */ + efh.f_symptr = 0; + efh.f_nsyms = 0; + efh.f_opthdr = sizeof eah; + efh.f_flags = 0x100f; /* Stripped, not sharable. */ + + memset(esecs, 0, sizeof esecs); + strcpy(esecs[0].s_name, ".text"); + strcpy(esecs[1].s_name, ".data"); + strcpy(esecs[2].s_name, ".bss"); + if (addflag) { + strcpy(esecs[3].s_name, ".rdata"); + strcpy(esecs[4].s_name, ".sdata"); + strcpy(esecs[5].s_name, ".sbss"); + } + esecs[0].s_paddr = esecs[0].s_vaddr = eah.text_start; + esecs[1].s_paddr = esecs[1].s_vaddr = eah.data_start; + esecs[2].s_paddr = esecs[2].s_vaddr = eah.bss_start; + if (addflag) { + esecs[3].s_paddr = esecs[3].s_vaddr = 0; + esecs[4].s_paddr = esecs[4].s_vaddr = 0; + esecs[5].s_paddr = esecs[5].s_vaddr = 0; + } + esecs[0].s_size = eah.tsize; + esecs[1].s_size = eah.dsize; + esecs[2].s_size = eah.bsize; + if (addflag) { + esecs[3].s_size = 0; + esecs[4].s_size = 0; + esecs[5].s_size = 0; + } + esecs[0].s_scnptr = N_TXTOFF(efh, eah); + esecs[1].s_scnptr = N_DATOFF(efh, eah); +#define ECOFF_SEGMENT_ALIGNMENT(a) 0x10 +#define ECOFF_ROUND(s,a) (((s)+(a)-1)&~((a)-1)) + esecs[2].s_scnptr = esecs[1].s_scnptr + + ECOFF_ROUND(esecs[1].s_size, ECOFF_SEGMENT_ALIGNMENT(&eah)); + if (addflag) { + esecs[3].s_scnptr = 0; + esecs[4].s_scnptr = 0; + esecs[5].s_scnptr = 0; + } + esecs[0].s_relptr = esecs[1].s_relptr = esecs[2].s_relptr = 0; + esecs[0].s_lnnoptr = esecs[1].s_lnnoptr = esecs[2].s_lnnoptr = 0; + esecs[0].s_nreloc = esecs[1].s_nreloc = esecs[2].s_nreloc = 0; + esecs[0].s_nlnno = esecs[1].s_nlnno = esecs[2].s_nlnno = 0; + if (addflag) { + esecs[3].s_relptr = esecs[4].s_relptr + = esecs[5].s_relptr = 0; + esecs[3].s_lnnoptr = esecs[4].s_lnnoptr + = esecs[5].s_lnnoptr = 0; + esecs[3].s_nreloc = esecs[4].s_nreloc = esecs[5].s_nreloc = + 0; + esecs[3].s_nlnno = esecs[4].s_nlnno = esecs[5].s_nlnno = 0; + } + esecs[0].s_flags = 0x20; + esecs[1].s_flags = 0x40; + esecs[2].s_flags = 0x82; + if (addflag) { + esecs[3].s_flags = 0x100; + esecs[4].s_flags = 0x200; + esecs[5].s_flags = 0x400; + } + + /* Make the output file... */ + if ((outfile = open(argv[2], O_WRONLY | O_CREAT, 0777)) < 0) { + fprintf(stderr, "Unable to create %s: %s\n", argv[2], + strerror(errno)); + exit(1); + } + + if (must_convert_endian) + convert_ecoff_filehdr(&efh); + /* Write the headers... */ + i = write(outfile, &efh, sizeof efh); + if (i != sizeof efh) { + perror("efh: write"); + exit(1); + + for (i = 0; i < nosecs; i++) { + printf + ("Section %d: %s phys %lx size %lx file offset %lx\n", + i, esecs[i].s_name, esecs[i].s_paddr, + esecs[i].s_size, esecs[i].s_scnptr); + } } + fprintf(stderr, "wrote %d byte file header.\n", i); + + if (must_convert_endian) + convert_ecoff_aouthdr(&eah); + i = write(outfile, &eah, sizeof eah); + if (i != sizeof eah) { + perror("eah: write"); + exit(1); + } + fprintf(stderr, "wrote %d byte a.out header.\n", i); + + if (must_convert_endian) + convert_ecoff_esecs(&esecs[0], nosecs); + i = write(outfile, &esecs, nosecs * sizeof(struct scnhdr)); + if (i != nosecs * sizeof(struct scnhdr)) { + perror("esecs: write"); + exit(1); + } + fprintf(stderr, "wrote %d bytes of section headers.\n", i); + + pad = (sizeof(efh) + sizeof(eah) + nosecs * sizeof(struct scnhdr)) & 15; + if (pad) { + pad = 16 - pad; + i = write(outfile, "\0\0\0\0\0\0\0\0\0\0\0\0\0\0", pad); + if (i < 0) { + perror("ipad: write"); + exit(1); + } + fprintf(stderr, "wrote %d byte pad.\n", i); + } + + /* + * Copy the loadable sections. Zero-fill any gaps less than 64k; + * complain about any zero-filling, and die if we're asked to zero-fill + * more than 64k. + */ + for (i = 0; i < ex.e_phnum; i++) { + /* Unprocessable sections were handled above, so just verify that + the section can be loaded before copying. */ + if (ph[i].p_type == PT_LOAD && ph[i].p_filesz) { + if (cur_vma != ph[i].p_vaddr) { + unsigned long gap = + ph[i].p_vaddr - cur_vma; + char obuf[1024]; + if (gap > 65536) { + fprintf(stderr, + "Intersegment gap (%ld bytes) too large.\n", + gap); + exit(1); + } + fprintf(stderr, + "Warning: %ld byte intersegment gap.\n", + gap); + memset(obuf, 0, sizeof obuf); + while (gap) { + int count = + write(outfile, obuf, + (gap > + sizeof obuf ? sizeof + obuf : gap)); + if (count < 0) { + fprintf(stderr, + "Error writing gap: %s\n", + strerror(errno)); + exit(1); + } + gap -= count; + } + } + fprintf(stderr, "writing %d bytes...\n", + ph[i].p_filesz); + copy(outfile, infile, ph[i].p_offset, + ph[i].p_filesz); + cur_vma = ph[i].p_vaddr + ph[i].p_filesz; + } + } + + /* + * Write a page of padding for boot PROMS that read entire pages. + * Without this, they may attempt to read past the end of the + * data section, incur an error, and refuse to boot. + */ + { + char obuf[4096]; + memset(obuf, 0, sizeof obuf); + if (write(outfile, obuf, sizeof(obuf)) != sizeof(obuf)) { + fprintf(stderr, "Error writing PROM padding: %s\n", + strerror(errno)); + exit(1); + } + } + + /* Looks like we won... */ + exit(0); } --- linux-2.5.73/arch/mips/boot/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/boot/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -3,11 +3,9 @@ # License. See the file "COPYING" in the main directory of this archive # for more details. # -# Copyright (C) 1995, 1998, 2001 by Ralf Baechle +# Copyright (C) 1995, 1998, 2001, 2002 by Ralf Baechle # -OBJS = milo.o a.out.o - # # Some DECstations need all possible sections of an ECOFF executable # @@ -21,25 +19,33 @@ endif # Drop some uninteresting sections in the kernel. # This is only relevant for ELF kernels but doesn't hurt a.out # -drop-sections = .reginfo .mdebug +drop-sections = .reginfo .mdebug .comment .note strip-flags = $(addprefix --remove-section=,$(drop-sections)) all: vmlinux.ecoff addinitrd -vmlinux.ecoff: elf2ecoff $(TOPDIR)/vmlinux - ./elf2ecoff $(TOPDIR)/vmlinux vmlinux.ecoff $(E2EFLAGS) +vmlinux.rm200: vmlinux + $(OBJCOPY) \ + --change-addresses=0xfffffffc \ + -O elf32-tradlittlemips \ + $(strip-flags) \ + $< $@ + +vmlinux.ecoff: $(obj)/elf2ecoff vmlinux + ./elf2ecoff vmlinux $(obj)/vmlinux.ecoff $(E2EFLAGS) -elf2ecoff: elf2ecoff.c +$(obj)/elf2ecoff: $(obj)/elf2ecoff.c $(HOSTCC) -o $@ $^ -addinitrd: addinitrd.c +$(obj)/addinitrd: $(obj)/addinitrd.c $(HOSTCC) -o $@ $^ -clean: - rm -f vmlinux.ecoff - rm -f zImage zImage.tmp - -mrproper: - rm -f vmlinux.ecoff - rm -f addinitrd - rm -f elf2ecoff +archhelp: + @echo '* vmlinux.rm200 - Bootable kernel image for RM200C' + +CLEAN_FILES += addinitrd \ + elf2ecoff \ + vmlinux.ecoff \ + vmlinux.rm200 \ + zImage.tmp \ + zImage --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/cobalt/int-handler.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,104 @@ +/* + * Cobalt interrupt handler + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996, 1997 by Ralf Baechle + * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) + */ +#include +#include +#include +#include +#include + +/* + * cobalt_handle_int: Interrupt handler for Cobalt boards + */ + .text + .set noreorder + .set noat + .align 5 + NESTED(cobalt_handle_int, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + + /* + * Get pending Interrupts + */ + mfc0 s0,CP0_CAUSE # get raw irq status + mfc0 a0,CP0_STATUS # get irq mask + and s0,s0,a0 # compute masked irq status + + andi a0,s0,CAUSEF_IP2 /* Check for Galileo timer */ + beq a0,zero,1f + andi a0,s0,CAUSEF_IP6 /* Check for Via chip */ + + /* Galileo interrupt */ + jal galileo_irq + move a0,sp + j ret_from_irq + nop + +1: + beq a0,zero,1f /* Check IP6 */ + andi a0,s0,CAUSEF_IP3 + + /* Via interrupt */ + jal via_irq + move a0,sp + j ret_from_irq + nop + +1: + beq a0,zero,1f /* Check IP3 */ + andi a0,s0,CAUSEF_IP4 + + /* Ethernet 0 interrupt */ + li a0,COBALT_ETH0_IRQ + jal do_IRQ + move a1,sp + + j ret_from_irq + nop + +1: + beq a0,zero,1f /* Check IP4 */ + andi a0,s0,CAUSEF_IP5 + + /* Ethernet 1 interrupt */ + li a0,COBALT_ETH1_IRQ + jal do_IRQ + move a1,sp + + j ret_from_irq + nop +1: + beq a0,zero,1f /* Check IP5 */ + andi a0,s0,CAUSEF_IP7 + + /* Serial interrupt */ + li a0,COBALT_SERIAL_IRQ + jal do_IRQ + move a1,sp + + j ret_from_irq + nop +1: + beq a0,zero,1f /* Check IP7 */ + nop + + /* PCI interrupt */ + li a0,COBALT_QUBE_SLOT_IRQ + jal do_IRQ + move a1,sp + +1: + j ret_from_irq + nop + + END(cobalt_handle_int) + --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/cobalt/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,143 @@ +/* + * IRQ vector handles + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996, 1997 by Ralf Baechle + * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv) + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +/* Cobalt Exception handler */ +extern void cobalt_handle_int(void); + +/* Via masking routines */ +extern void unmask_irq(unsigned int irqr); +extern void mask_irq(unsigned int irq); + + +/* + * We have two types of interrupts that we handle, ones that come + * in through the CPU interrupt lines, and ones that come in on + * the via chip. The CPU mappings are: + * 0,1 - S/W (ignored) + * 2 - Galileo chip (timer) + * 3 - Tulip 0 + NCR SCSI + * 4 - Tulip 1 + * 5 - 16550 UART + * 6 - VIA southbridge PIC + * 7 - unused + * + * The VIA chip is a master/slave 8259 setup and has the + * following interrupts + * 8 - RTC + * 9 - PCI + * 14 - IDE0 + * 15 - IDE1 + * + * In the table we use a 1 to indicate that we use a VIA interrupt + * line, and IE_IRQx to indicate that we use a CPU interrupt line + * + * We map all of these onto linux IRQ #s 0-15 and forget the rest + */ +#define NOINT_LINE 0 +#define CPUINT_LINE(x) IE_IRQ##x +#define VIAINT_LINE 1 + +#define COBALT_IRQS 16 + +static unsigned short irqnr_to_type[COBALT_IRQS] = +{ CPUINT_LINE(0), NOINT_LINE, VIAINT_LINE, NOINT_LINE, + CPUINT_LINE(1), NOINT_LINE, NOINT_LINE, CPUINT_LINE(3), + VIAINT_LINE, VIAINT_LINE, NOINT_LINE, NOINT_LINE, + NOINT_LINE, CPUINT_LINE(2), VIAINT_LINE, VIAINT_LINE }; + +/* + * Cobalt CPU irq + */ + +static void enable_cpu_irq(unsigned int irq) +{ + unsigned long flags; + + local_irq_save(flags); + change_c0_status(irqnr_to_type[irq], irqnr_to_type[irq]); + local_irq_restore(flags); +} + +static unsigned startup_cpu_irq(unsigned int irq) +{ + enable_cpu_irq(irq); + + return 0; +} + +static void disable_cpu_irq(unsigned int irq) +{ + unsigned long flags; + + local_irq_save(flags); + change_c0_status(irqnr_to_type[irq], ~(irqnr_to_type[irq])); + local_irq_restore(flags); +} + +#define shutdown_cpu_irq disable_cpu_irq +#define mask_and_ack_cpu_irq disable_cpu_irq + +static void end_cpu_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_cpu_irq(irq); +} + +static struct hw_interrupt_type cobalt_cpu_irq_type = { + "Cobalt CPU", + startup_cpu_irq, + shutdown_cpu_irq, + enable_cpu_irq, + disable_cpu_irq, + mask_and_ack_cpu_irq, + end_cpu_irq, + NULL +}; + +void __init init_IRQ(void) +{ + int i; + + /* Initialise all of the IRQ descriptors */ + init_i8259_irqs(); + + /* Map the irqnr to the type int we have */ + for (i=0; i < COBALT_IRQS; i++) { + if (irqnr_to_type[i] >= CPUINT_LINE(0)) + /* cobalt_cpu_irq_type */ + irq_desc[i].handler = &cobalt_cpu_irq_type; + } + + /* Mask all cpu interrupts + (except IE4, we already masked those at VIA level) */ + clear_c0_status(ST0_IM); + set_c0_status(IE_IRQ4); + + cli(); + + set_except_vector(0, cobalt_handle_int); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/cobalt/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,7 @@ +# +# Makefile for the Cobalt micro systems family specific parts of the kernel +# + +obj-y := irq.o int-handler.o reset.o setup.o via.o promcon.o + +EXTRA_AFLAGS := $(CFLAGS) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/cobalt/promcon.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,91 @@ +/* + * PROM console for Cobalt Raq2 + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996, 1997 by Ralf Baechle + * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv) + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +static unsigned long port = 0xc800000; + +static __inline__ void ns16550_cons_put_char(char ch, unsigned long ioaddr) +{ + char lsr; + + do { + lsr = inb(ioaddr + UART_LSR); + } while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE)); + outb(ch, ioaddr + UART_TX); +} + +static __inline__ char ns16550_cons_get_char(unsigned long ioaddr) +{ + while ((inb(ioaddr + UART_LSR) & UART_LSR_DR) == 0) + udelay(1); + return inb(ioaddr + UART_RX); +} + +void ns16550_console_write(struct console *co, const char *s, unsigned count) +{ + char lsr, ier; + unsigned i; + + ier = inb(port + UART_IER); + outb(0x00, port + UART_IER); + for (i=0; i < count; i++, s++) { + + if(*s == '\n') + ns16550_cons_put_char('\r', port); + ns16550_cons_put_char(*s, port); + } + + do { + lsr = inb(port + UART_LSR); + } while ((lsr & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE)); + + outb(ier, port + UART_IER); +} + +char getDebugChar(void) +{ + return ns16550_cons_get_char(port); +} + +void putDebugChar(char kgdb_char) +{ + ns16550_cons_put_char(kgdb_char, port); +} + +static kdev_t +ns16550_console_dev(struct console *c) +{ + return mk_kdev(TTY_MAJOR, 64 + c->index); +} + +static struct console ns16550_console = { + .name = "prom", + .setup = NULL, + .write = ns16550_console_write, + .device = ns16550_console_dev, + .flags = CON_PRINTBUFFER, + .index = -1, +}; + +void __init ns16550_setup_console(void) +{ + register_console(&ns16550_console); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/cobalt/reset.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,68 @@ +/* + * Cobalt Reset operations + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996, 1997 by Ralf Baechle + * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv) + */ +#include +#include +#include +#include +#include +#include +#include +#include + +void cobalt_machine_restart(char *command) +{ + *(volatile char *)0xbc000000 = 0x0f; + + /* + * Ouch, we're still alive ... This time we take the silver bullet ... + * ... and find that we leave the hardware in a state in which the + * kernel in the flush locks up somewhen during of after the PCI + * detection stuff. + */ + set_c0_status(ST0_BEV | ST0_ERL); + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + flush_cache_all(); + write_c0_wired(0); + __asm__ __volatile__( + "jr\t%0" + : + : "r" (0xbfc00000)); +} + +extern int led_state; +#define kLED 0xBC000000 +#define LEDSet(x) (*(volatile unsigned char *) kLED) = (( unsigned char)x) + +void cobalt_machine_halt(void) +{ + int mark; + + /* Blink our cute? little LED (number 3)... */ + while (1) { + led_state = led_state | ( 1 << 3 ); + LEDSet(led_state); + mark = jiffies; + while (jiffies<(mark+HZ)); + led_state = led_state & ~( 1 << 3 ); + LEDSet(led_state); + mark = jiffies; + while (jiffies<(mark+HZ)); + } +} + +/* + * This triggers the luser mode device driver for the power switch ;-) + */ +void cobalt_machine_power_off(void) +{ + printk("You can switch the machine off now.\n"); + cobalt_machine_halt(); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/cobalt/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,113 @@ +/* + * Setup pointers to hardware dependent routines. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 1997 by Ralf Baechle + * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +extern void cobalt_machine_restart(char *command); +extern void cobalt_machine_halt(void); +extern void cobalt_machine_power_off(void); + +extern struct rtc_ops std_rtc_ops; +extern struct ide_ops std_ide_ops; + + +char arcs_cmdline[CL_SIZE] = { + "console=ttyS0,115200 " +#ifdef CONFIG_IP_PNP + "ip=on " +#endif +#ifdef CONFIG_ROOT_NFS + "root=/dev/nfs " +#else + "root=/dev/hda1 " +#endif + }; + +const char *get_system_type(void) +{ + return "MIPS Cobalt"; +} + + +static void __init cobalt_time_init(void) +{ + rtc_ops = &std_rtc_ops; +} + +static void __init cobalt_timer_setup(struct irqaction *irq) +{ + /* Load timer value for 150 Hz */ + GALILEO_OUTL(500000, GT_TC0_OFS); + + /* Register our timer interrupt */ + setup_irq(COBALT_TIMER_IRQ, irq); + + /* Enable timer ints */ + GALILEO_OUTL((GALILEO_ENTC0 | GALILEO_SELTC0), GT_TC_CONTROL_OFS); + /* Unmask timer int */ + GALILEO_OUTL(0x100, GT_INTRMASK_OFS); +} + + +void __init cobalt_setup(void) +{ + + _machine_restart = cobalt_machine_restart; + _machine_halt = cobalt_machine_halt; + _machine_power_off = cobalt_machine_power_off; + + board_time_init = cobalt_time_init; + board_timer_setup = cobalt_timer_setup; + +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &std_ide_ops; +#endif + + set_io_port_base(KSEG1ADDR(0x10000000)); + + /* + * This is a prom style console. We just poke at the + * UART to make it talk. + * Only use this console if you really screw up and can't + * get to the stage of setting up a real serial console. + */ + /*ns16550_setup_console();*/ +} + +/* Prom init. We read our one and only communication with the + firmware. Grab the amount of installed memory */ +void __init prom_init(int argc) +{ + mips_machgroup = MACH_GROUP_COBALT; + + add_memory_region(0x0, argc & 0x7fffffff, BOOT_MEM_RAM); +} + +void __init prom_free_prom_memory(void) +{ + /* Nothing to do! */ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/cobalt/via.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,67 @@ +/* + * VIA chipset irq handling + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 1997 by Ralf Baechle + * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) + * + */ + +#include +#include + +#include +#include +#include + +#include + +asmlinkage void via_irq(struct pt_regs *regs) +{ + char mstat, sstat; + + /* Read Master Status */ + outb(0x0C, 0x20); + mstat = inb(0x20); + + if (mstat < 0) { + mstat &= 0x7f; + if (mstat != 2) { + do_IRQ(mstat, regs); + outb(mstat | 0x20, 0x20); + } else { + sstat = inb(0xA0); + + /* Slave interrupt */ + outb(0x0C, 0xA0); + sstat = inb(0xA0); + + if (sstat < 0) { + do_IRQ((sstat + 8) & 0x7f, regs); + outb(0x22, 0x20); + outb((sstat & 0x7f) | 0x20, 0xA0); + } else { + printk("Spurious slave interrupt...\n"); + } + } + } else + printk("Spurious master interrupt..."); +} + +asmlinkage void galileo_irq(struct pt_regs *regs) +{ + unsigned long irq_src; + + irq_src = GALILEO_INL(GT_INTRCAUSE_OFS); + + /* Check for timer irq ... */ + if (irq_src & GALILEO_T0EXP) { + /* Clear the int line */ + GALILEO_OUTL(0, GT_INTRCAUSE_OFS); + do_IRQ(COBALT_TIMER_IRQ, regs); + } else + printk("Spurious Galileo interrupt...\n"); +} --- linux-2.5.73/arch/mips/ddb5074/int-handler.S 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,120 +0,0 @@ -/* - * arch/mips/ddb5074/int-handler.S -- NEC DDB Vrc-5074 interrupt handler - * - * Based on arch/mips/sgi/kernel/indyIRQ.S - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * - * Copyright (C) 2000 Geert Uytterhoeven - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include -#include -#include -#include - -/* A lot of complication here is taken away because: - * - * 1) We handle one interrupt and return, sitting in a loop and moving across - * all the pending IRQ bits in the cause register is _NOT_ the answer, the - * common case is one pending IRQ so optimize in that direction. - * - * 2) We need not check against bits in the status register IRQ mask, that - * would make this routine slow as hell. - * - * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in - * between like BSD spl() brain-damage. - * - * Furthermore, the IRQs on the INDY look basically (barring software IRQs - * which we don't use at all) like: - * - * MIPS IRQ Source - * -------- ------ - * 0 Software (ignored) - * 1 Software (ignored) - * 2 Local IRQ level zero - * 3 Local IRQ level one - * 4 8254 Timer zero - * 5 8254 Timer one - * 6 Bus Error - * 7 R4k timer (what we use) - * - * We handle the IRQ according to _our_ priority which is: - * - * Highest ---- R4k Timer - * Local IRQ zero - * Local IRQ one - * Bus Error - * 8254 Timer zero - * Lowest ---- 8254 Timer one - * - * then we just return, if multiple IRQs are pending then we will just take - * another exception, big deal. - */ - - .text - .set noreorder - .set noat - .align 5 - NESTED(ddbIRQ, PT_SIZE, sp) - SAVE_ALL - CLI - .set at - mfc0 s0, CP0_CAUSE # get irq mask - -#if 1 - mfc0 t2,CP0_STATUS # get enabled interrupts - and s0,t2 # isolate allowed ones -#endif - /* First we check for r4k counter/timer IRQ. */ - andi a0, s0, CAUSEF_IP2 # delay slot, check local level zero - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP3 # delay slot, check local level one - - /* Wheee, local level zero interrupt. */ - jal ddb_local0_irqdispatch - move a0, sp # delay slot - - j ret_from_irq - nop # delay slot - -1: - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP6 # delay slot, check bus error - - /* Wheee, local level one interrupt. */ - move a0, sp - jal ddb_local1_irqdispatch - nop - - j ret_from_irq - nop - -1: - beq a0, zero, 1f - nop - - /* Wheee, an asynchronous bus error... */ - move a0, sp - jal ddb_buserror_irq - nop - - j ret_from_irq - nop - -1: - /* Here by mistake? This is possible, what can happen - * is that by the time we take the exception the IRQ - * pin goes low, so just leave if this is the case. - */ - andi a0, s0, (CAUSEF_IP4 | CAUSEF_IP5) - beq a0, zero, 1f - - /* Must be one of the 8254 timers... */ - move a0, sp - jal ddb_8254timer_irq - nop -1: - j ret_from_irq - nop - END(ddbIRQ) --- linux-2.5.73/arch/mips/ddb5074/irq.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,226 +0,0 @@ -/* - * arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines - * - * Copyright (C) 2000 Geert Uytterhoeven - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - - -extern void __init i8259_init(void); -extern void i8259_disable_irq(unsigned int irq_nr); -extern void i8259_enable_irq(unsigned int irq_nr); - -extern asmlinkage void ddbIRQ(void); -extern asmlinkage void i8259_do_irq(int irq, struct pt_regs *regs); -extern asmlinkage void do_IRQ(int irq, struct pt_regs *regs); - - -void no_action(int cpl, void *dev_id, struct pt_regs *regs) -{ -} - - -#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */ -#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */ -#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */ - -#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */ -#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */ -#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */ - -#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */ -#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */ - -#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */ -#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */ - -#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */ -#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */ - - -static void m1543_irq_setup(void) -{ - /* - * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all - * the possible IO sources in the M1543 are in use by us. We will - * use the following mapping: - * - * IRQ1 - keyboard (default set by M1543) - * IRQ3 - reserved for UART B (default set by M1543) (note that - * the schematics for the DDB Vrc-5074 board seem to - * indicate that IRQ3 is connected to the DS1386 - * watchdog timer interrupt output so we might have - * a conflict) - * IRQ4 - reserved for UART A (default set by M1543) - * IRQ5 - parallel (default set by M1543) - * IRQ8 - DS1386 time of day (RTC) interrupt - * IRQ12 - mouse - */ - - /* - * Assing mouse interrupt to IRQ12 - */ - - /* Enter configuration mode */ - outb(0x51, M1543_PNP_CONFIG); - outb(0x23, M1543_PNP_CONFIG); - - /* Select logical device 7 (Keyboard) */ - outb(0x07, M1543_PNP_INDEX); - outb(0x07, M1543_PNP_DATA); - - /* Select IRQ12 */ - outb(0x72, M1543_PNP_INDEX); - outb(0x0c, M1543_PNP_DATA); - - /* Leave configration mode */ - outb(0xbb, M1543_PNP_CONFIG); - - - /* Initialize the 8259 PIC in the M1543 */ - i8259_init(); - - /* Enable the interrupt cascade */ - nile4_enable_irq(NILE4_INT_INTE); - - request_region(M1543_PNP_CONFIG, 2, "M1543 config"); - request_region(M1543_INT1_MASTER_ELCR, 2, "pic ELCR"); -} - -static void nile4_irq_setup(void) -{ - int i; - - /* Map all interrupts to CPU int #0 */ - nile4_map_irq_all(0); - - /* PCI INTA#-E# must be level triggered */ - nile4_set_pci_irq_level_or_edge(0, 1); - nile4_set_pci_irq_level_or_edge(1, 1); - nile4_set_pci_irq_level_or_edge(2, 1); - nile4_set_pci_irq_level_or_edge(3, 1); - nile4_set_pci_irq_level_or_edge(4, 1); - - /* PCI INTA#-D# must be active low, INTE# must be active high */ - nile4_set_pci_irq_polarity(0, 0); - nile4_set_pci_irq_polarity(1, 0); - nile4_set_pci_irq_polarity(2, 0); - nile4_set_pci_irq_polarity(3, 0); - nile4_set_pci_irq_polarity(4, 1); - - for (i = 0; i < 16; i++) - nile4_clear_irq(i); - - /* Enable CPU int #0 */ - nile4_enable_irq_output(0); - - request_mem_region(NILE4_BASE, NILE4_SIZE, "Nile 4"); -} - - -/* - * IRQ2 is cascade interrupt to second interrupt controller - */ -static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL }; - - -void disable_irq(unsigned int irq_nr) -{ - if (is_i8259_irq(irq_nr)) - i8259_disable_irq(irq_nr); - else - nile4_disable_irq(irq_to_nile4(irq_nr)); -} - -void enable_irq(unsigned int irq_nr) -{ - if (is_i8259_irq(irq_nr)) - i8259_enable_irq(irq_nr); - else - nile4_enable_irq(irq_to_nile4(irq_nr)); -} - -int table[16] = { 0, }; - -void ddb_local0_irqdispatch(struct pt_regs *regs) -{ - u32 mask; - int nile4_irq; -#if 1 - volatile static int nesting = 0; - if (nesting++ == 0) - ddb5074_led_d3(1); - ddb5074_led_hex(nesting < 16 ? nesting : 15); -#endif - - mask = nile4_get_irq_stat(0); - nile4_clear_irq_mask(mask); - - /* Handle the timer interrupt first */ - if (mask & (1 << NILE4_INT_GPT)) { - nile4_disable_irq(NILE4_INT_GPT); - do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs); - nile4_enable_irq(NILE4_INT_GPT); - mask &= ~(1 << NILE4_INT_GPT); - } - for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) - if (mask & 1) { - nile4_disable_irq(nile4_irq); - if (nile4_irq == NILE4_INT_INTE) { - int i8259_irq = nile4_i8259_iack(); - i8259_do_irq(i8259_irq, regs); - } else - do_IRQ(nile4_to_irq(nile4_irq), regs); - nile4_enable_irq(nile4_irq); - } -#if 1 - if (--nesting == 0) - ddb5074_led_d3(0); - ddb5074_led_hex(nesting < 16 ? nesting : 15); -#endif -} - -void ddb_local1_irqdispatch(void) -{ - printk("ddb_local1_irqdispatch called\n"); -} - -void ddb_buserror_irq(void) -{ - printk("ddb_buserror_irq called\n"); -} - -void ddb_8254timer_irq(void) -{ - printk("ddb_8254timer_irq called\n"); -} - -void __init ddb_irq_setup(void) -{ -#ifdef CONFIG_REMOTE_DEBUG - if (remote_debug) - set_debug_traps(); - breakpoint(); /* you may move this line to whereever you want :-) */ -#endif - request_region(0x20, 0x20, "pic1"); - request_region(0xa0, 0x20, "pic2"); - i8259_setup_irq(2, &irq2); - - nile4_irq_setup(); - m1543_irq_setup(); - - set_except_vector(0, ddbIRQ); -} --- linux-2.5.73/arch/mips/ddb5074/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,8 +0,0 @@ -# -# Makefile for the NEC DDB Vrc-5074 specific kernel interface routines -# under Linux. -# - -EXTRA_AFLAGS := $(CFLAGS) - -obj-y := setup.o irq.o time.o prom.o pci.o int-handler.o nile4.o --- linux-2.5.73/arch/mips/ddb5074/nile4.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,292 +0,0 @@ -/* - * arch/mips/ddb5074/nile4.c -- NEC Vrc-5074 Nile 4 support routines - * - * Copyright (C) 2000 Geert Uytterhoeven - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include -#include - -#include - - -/* - * Physical Device Address Registers - * - * Note: 32 bit addressing only! - */ -void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width, - int on_memory_bus, int visible) -{ - u32 maskbits; - u32 widthbits; - - if (pdar > NILE4_BOOTCS || (pdar & 7)) { - printk("nile4_set_pdar: invalid pdar %d\n", pdar); - return; - } - if (pdar == NILE4_INTCS && size != 0x00200000) { - printk("nile4_set_pdar: INTCS size must be 2 MB\n"); - return; - } - switch (size) { -#if 0 /* We don't support 4 GB yet */ - case 0x100000000: /* 4 GB */ - maskbits = 4; - break; -#endif - case 0x80000000: /* 2 GB */ - maskbits = 5; - break; - case 0x40000000: /* 1 GB */ - maskbits = 6; - break; - case 0x20000000: /* 512 MB */ - maskbits = 7; - break; - case 0x10000000: /* 256 MB */ - maskbits = 8; - break; - case 0x08000000: /* 128 MB */ - maskbits = 9; - break; - case 0x04000000: /* 64 MB */ - maskbits = 10; - break; - case 0x02000000: /* 32 MB */ - maskbits = 11; - break; - case 0x01000000: /* 16 MB */ - maskbits = 12; - break; - case 0x00800000: /* 8 MB */ - maskbits = 13; - break; - case 0x00400000: /* 4 MB */ - maskbits = 14; - break; - case 0x00200000: /* 2 MB */ - maskbits = 15; - break; - case 0: /* OFF */ - maskbits = 0; - break; - default: - printk("nile4_set_pdar: unsupported size %p\n", (void *) size); - return; - } - switch (width) { - case 8: - widthbits = 0; - break; - case 16: - widthbits = 1; - break; - case 32: - widthbits = 2; - break; - case 64: - widthbits = 3; - break; - default: - printk("nile4_set_pdar: unsupported width %d\n", width); - return; - } - nile4_out32(pdar, maskbits | (on_memory_bus ? 0x10 : 0) | - (visible ? 0x20 : 0) | (widthbits << 6) | - (phys & 0xffe00000)); - nile4_out32(pdar + 4, 0); - /* - * When programming a PDAR, the register should be read immediately - * after writing it. This ensures that address decoders are properly - * configured. - */ - nile4_in32(pdar); - nile4_in32(pdar + 4); -} - - -/* - * PCI Master Registers - * - * Note: 32 bit addressing only! - */ -void nile4_set_pmr(u32 pmr, u32 type, u32 addr) -{ - if (pmr != NILE4_PCIINIT0 && pmr != NILE4_PCIINIT1) { - printk("nile4_set_pmr: invalid pmr %d\n", pmr); - return; - } - switch (type) { - case NILE4_PCICMD_IACK: /* PCI Interrupt Acknowledge */ - case NILE4_PCICMD_IO: /* PCI I/O Space */ - case NILE4_PCICMD_MEM: /* PCI Memory Space */ - case NILE4_PCICMD_CFG: /* PCI Configuration Space */ - break; - default: - printk("nile4_set_pmr: invalid type %d\n", type); - return; - } - nile4_out32(pmr, (type << 1) | 0x10 | (addr & 0xffe00000)); - nile4_out32(pmr + 4, 0); -} - - -/* - * Interrupt Programming - */ -void nile4_map_irq(int nile4_irq, int cpu_irq) -{ - u32 offset, t; - - offset = NILE4_INTCTRL; - if (nile4_irq >= 8) { - offset += 4; - nile4_irq -= 8; - } - t = nile4_in32(offset); - t &= ~(7 << (nile4_irq * 4)); - t |= cpu_irq << (nile4_irq * 4); - nile4_out32(offset, t); -} - -void nile4_map_irq_all(int cpu_irq) -{ - u32 all, t; - - all = cpu_irq; - all |= all << 4; - all |= all << 8; - all |= all << 16; - t = nile4_in32(NILE4_INTCTRL); - t &= 0x88888888; - t |= all; - nile4_out32(NILE4_INTCTRL, t); - t = nile4_in32(NILE4_INTCTRL + 4); - t &= 0x88888888; - t |= all; - nile4_out32(NILE4_INTCTRL + 4, t); -} - -void nile4_enable_irq(int nile4_irq) -{ - u32 offset, t; - - offset = NILE4_INTCTRL; - if (nile4_irq >= 8) { - offset += 4; - nile4_irq -= 8; - } - t = nile4_in32(offset); - t |= 8 << (nile4_irq * 4); - nile4_out32(offset, t); -} - -void nile4_disable_irq(int nile4_irq) -{ - u32 offset, t; - - offset = NILE4_INTCTRL; - if (nile4_irq >= 8) { - offset += 4; - nile4_irq -= 8; - } - t = nile4_in32(offset); - t &= ~(8 << (nile4_irq * 4)); - nile4_out32(offset, t); -} - -void nile4_disable_irq_all(void) -{ - nile4_out32(NILE4_INTCTRL, 0); - nile4_out32(NILE4_INTCTRL + 4, 0); -} - -u16 nile4_get_irq_stat(int cpu_irq) -{ - return nile4_in16(NILE4_INTSTAT0 + cpu_irq * 2); -} - -void nile4_enable_irq_output(int cpu_irq) -{ - u32 t; - - t = nile4_in32(NILE4_INTSTAT1 + 4); - t |= 1 << (16 + cpu_irq); - nile4_out32(NILE4_INTSTAT1, t); -} - -void nile4_disable_irq_output(int cpu_irq) -{ - u32 t; - - t = nile4_in32(NILE4_INTSTAT1 + 4); - t &= ~(1 << (16 + cpu_irq)); - nile4_out32(NILE4_INTSTAT1, t); -} - -void nile4_set_pci_irq_polarity(int pci_irq, int high) -{ - u32 t; - - t = nile4_in32(NILE4_INTPPES); - if (high) - t &= ~(1 << (pci_irq * 2)); - else - t |= 1 << (pci_irq * 2); - nile4_out32(NILE4_INTPPES, t); -} - -void nile4_set_pci_irq_level_or_edge(int pci_irq, int level) -{ - u32 t; - - t = nile4_in32(NILE4_INTPPES); - if (level) - t |= 2 << (pci_irq * 2); - else - t &= ~(2 << (pci_irq * 2)); - nile4_out32(NILE4_INTPPES, t); -} - -void nile4_clear_irq(int nile4_irq) -{ - nile4_out32(NILE4_INTCLR, 1 << nile4_irq); -} - -void nile4_clear_irq_mask(u32 mask) -{ - nile4_out32(NILE4_INTCLR, mask); -} - -u8 nile4_i8259_iack(void) -{ - u8 irq; - - /* Set window 0 for interrupt acknowledge */ - nile4_set_pmr(NILE4_PCIINIT0, NILE4_PCICMD_IACK, 0); - irq = *(volatile u8 *) NILE4_PCI_IACK_BASE; - /* Set window 0 for PCI I/O space */ - nile4_set_pmr(NILE4_PCIINIT0, NILE4_PCICMD_IO, 0); - return irq; -} - -#if 0 -void nile4_dump_irq_status(void) -{ - printk("CPUSTAT = %p:%p\n", (void *) nile4_in32(NILE4_CPUSTAT + 4), - (void *) nile4_in32(NILE4_CPUSTAT)); - printk("INTCTRL = %p:%p\n", (void *) nile4_in32(NILE4_INTCTRL + 4), - (void *) nile4_in32(NILE4_INTCTRL)); - printk("INTSTAT0 = %p:%p\n", - (void *) nile4_in32(NILE4_INTSTAT0 + 4), - (void *) nile4_in32(NILE4_INTSTAT0)); - printk("INTSTAT1 = %p:%p\n", - (void *) nile4_in32(NILE4_INTSTAT1 + 4), - (void *) nile4_in32(NILE4_INTSTAT1)); - printk("INTCLR = %p:%p\n", (void *) nile4_in32(NILE4_INTCLR + 4), - (void *) nile4_in32(NILE4_INTCLR)); - printk("INTPPES = %p:%p\n", (void *) nile4_in32(NILE4_INTPPES + 4), - (void *) nile4_in32(NILE4_INTPPES)); -} -#endif --- linux-2.5.73/arch/mips/ddb5074/pci.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,366 +0,0 @@ -/* - * arch/mips/ddb5074/pci.c -- NEC DDB Vrc-5074 PCI access routines - * - * Copyright (C) 2000 Geert Uytterhoeven - * Albert Dorofeev - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include -#include -#include -#include -#include -#include - -#include - - -static u32 nile4_pre_pci_access0(int slot_num) -{ - u32 pci_addr = 0; - u32 virt_addr = NILE4_PCI_CFG_BASE; - - /* Set window 1 address 8000000 - 64 bit - 2 MB (PCI config space) */ - nile4_set_pdar(NILE4_PCIW1, PHYSADDR(virt_addr), 0x00200000, 64, 0, - 0); - if (slot_num > 2) - pci_addr = 0x00040000 << slot_num; - else - virt_addr += 0x00040000 << slot_num; - nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_CFG, pci_addr); - return virt_addr; -} - -static void nile4_post_pci_access0(void) -{ - /* - * Set window 1 back to address 8000000 - 64 bit - 128 MB - * (PCI IO space) - */ - nile4_set_pdar(NILE4_PCIW1, PHYSADDR(NILE4_PCI_MEM_BASE), - 0x08000000, 64, 1, 1); - nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0); -} - - -static int nile4_pci_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 * val) -{ - int status, slot_num, func_num; - u32 result, base; - - switch (size) { - case 4: - /* - * For starters let's do configuration cycle 0 only - * (one bus only) - */ - if (bus->number) - return PCIBIOS_FUNC_NOT_SUPPORTED; - - slot_num = PCI_SLOT(devfn); - func_num = PCI_FUNC(devfn); - if (slot_num == 5) { - /* - * This is Nile 4 and it will crash if we access it - * like other devices - */ - *val = nile4_in32(NILE4_PCI_BASE + where); - return PCIBIOS_SUCCESSFUL; - } - base = nile4_pre_pci_access0(slot_num); - *val = *((volatile u32 *) (base + (func_num << 8) + - (where & 0xfc))); - nile4_post_pci_access0(); - return PCIBIOS_SUCCESSFUL; - - case 2: - status = nile4_pci_read(bus, devfn, where, 4, &result); - if (status != PCIBIOS_SUCCESSFUL) - return status; - if (where & 2) - result >>= 16; - *val = (u16)(result & 0xffff); - break; - case 1: - status = nile4_pci_read(bus, devfn, where, 4, &result); - if (status != PCIBIOS_SUCCESSFUL) - return status; - if (where & 1) - result >>= 8; - if (where & 2) - result >>= 16; - *val = (u8)(result & 0xff); - break; - } - return PCIBIOS_SUCCESSFUL; -} - - -static int nile4_pci_write(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) -{ - int status, slot_num, func_num, shift = 0; - u32 result, base; - - switch (size) { - case 4: - /* - * For starters let's do configuration cycle 0 only - * (one bus only) - */ - if (bus->number) - return PCIBIOS_FUNC_NOT_SUPPORTED; - - slot_num = PCI_SLOT(devfn); - func_num = PCI_FUNC(devfn); - if (slot_num == 5) { - /* - * This is Nile 4 and it will crash if we access - * it like other devices - */ - nile4_out32(NILE4_PCI_BASE + where, val); - return PCIBIOS_SUCCESSFUL; - } - base = nile4_pre_pci_access0(slot_num); - *((volatile u32 *) (base + (func_num << 8) + - (where & 0xfc))) = val; - nile4_post_pci_access0(); - return PCIBIOS_SUCCESSFUL; - - case 2: - status = nile4_pci_read(bus, devfn, where, 4, &result); - if (status != PCIBIOS_SUCCESSFUL) - return status; - if (where & 2) - shift += 16; - result &= ~(0xffff << shift); - result |= (u16)(val << shift); - break; - case 1: - status = nile4_pci_read(bus, devfn, where, 4, &result); - if (status != PCIBIOS_SUCCESSFUL) - return status; - if (where & 2) - shift += 16; - if (where & 1) - shift += 8; - result &= ~(0xff << shift); - result |= (u8)(val << shift); - break; - } - return nile4_pci_write(bus, devfn, where, 4, result); -} - -struct pci_ops nile4_pci_ops = { - .read = nile4_pci_read, - .write = nile4_pci_write, -}; - -struct { - struct resource ram; - struct resource flash; - struct resource isa_io; - struct resource pci_io; - struct resource isa_mem; - struct resource pci_mem; - struct resource nile4; - struct resource boot; -} ddb5074_resources = { - { "RAM", 0x00000000, 0x03ffffff, - IORESOURCE_MEM | PCI_BASE_ADDRESS_MEM_TYPE_64}, - { "Flash ROM", 0x04000000, 0x043fffff}, - { "Nile4 ISA I/O", 0x06000000, 0x060fffff}, - { "Nile4 PCI I/O", 0x06100000, 0x07ffffff}, - { "Nile4 ISA mem", 0x08000000, 0x08ffffff, IORESOURCE_MEM}, - { "Nile4 PCI mem", 0x09000000, 0x0fffffff, IORESOURCE_MEM}, - { "Nile4 ctrl", 0x1fa00000, 0x1fbfffff, - IORESOURCE_MEM | PCI_BASE_ADDRESS_MEM_TYPE_64}, - { "Boot ROM", 0x1fc00000, 0x1fffffff} -}; - -static void __init ddb5074_pci_fixup(void) -{ - struct pci_dev *dev = NULL; - - while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { - if (dev->vendor == PCI_VENDOR_ID_NEC && - dev->device == PCI_DEVICE_ID_NEC_NILE4) { - /* - * The first 64-bit PCI base register should point to - * the Nile4 control registers. Unfortunately this - * isn't the case, so we fix it ourselves. This allows - * the serial driver to find the UART. - */ - dev->resource[0] = ddb5074_resources.nile4; - request_resource(&iomem_resource, - &dev->resource[0]); - /* - * The second 64-bit PCI base register points to the - * first memory bank. Unfortunately the address is - * wrong, so we fix it (again). - */ - dev->resource[2] = ddb5074_resources.ram; - request_resource(&iomem_resource, - &dev->resource[2]); - } else if (dev->vendor == PCI_VENDOR_ID_AL - && dev->device == PCI_DEVICE_ID_AL_M7101) { - /* - * It's nice to have the LEDs on the GPIO pins - * available for debugging - */ - extern struct pci_dev *pci_pmu; - u8 t8; - - pci_pmu = dev; /* for LEDs D2 and D3 */ - /* Program the lines for LEDs D2 and D3 to output */ - nile4_pci_read_config_byte(dev, 0x7d, &t8); - t8 |= 0xc0; - nile4_pci_write_config_byte(dev, 0x7d, t8); - /* Turn LEDs D2 and D3 off */ - nile4_pci_read_config_byte(dev, 0x7e, &t8); - t8 |= 0xc0; - nile4_pci_write_config_byte(dev, 0x7e, t8); - } - } -} - -static void __init pcibios_fixup_irqs(void) -{ - struct pci_dev *dev = NULL; - int slot_num; - - while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { - slot_num = PCI_SLOT(dev->devfn); - switch (slot_num) { - case 0: - dev->irq = nile4_to_irq(NILE4_INT_INTE); - break; - case 1: - dev->irq = nile4_to_irq(NILE4_INT_INTA); - break; - case 2: /* slot 1 */ - dev->irq = nile4_to_irq(NILE4_INT_INTA); - break; - case 3: /* slot 2 */ - dev->irq = nile4_to_irq(NILE4_INT_INTB); - break; - case 4: /* slot 3 */ - dev->irq = nile4_to_irq(NILE4_INT_INTC); - break; - case 5: - /* - * Fixup so the serial driver can use the UART - */ - dev->irq = nile4_to_irq(NILE4_INT_UART); - break; - case 13: - dev->irq = nile4_to_irq(NILE4_INT_INTE); - break; - default: - break; - } - } -} - -void __init pcibios_init(void) -{ - printk("PCI: Probing PCI hardware\n"); - ioport_resource.end = 0x1ffffff; /* 32 MB */ - iomem_resource.end = 0x1fffffff; /* 512 MB */ - /* `ram' and `nile4' are requested through the Nile4 pci_dev */ - request_resource(&iomem_resource, &ddb5074_resources.flash); - request_resource(&iomem_resource, &ddb5074_resources.isa_io); - request_resource(&iomem_resource, &ddb5074_resources.pci_io); - request_resource(&iomem_resource, &ddb5074_resources.isa_mem); - request_resource(&iomem_resource, &ddb5074_resources.pci_mem); - request_resource(&iomem_resource, &ddb5074_resources.boot); - - pci_scan_bus(0, &nile4_pci_ops, NULL); - ddb5074_pci_fixup(); - pci_assign_unassigned_resources(); - pcibios_fixup_irqs(); -} - -void __init pcibios_fixup_bus(struct pci_bus *bus) -{ - bus->resource[1] = &ddb5074_resources.pci_mem; -} - -char *pcibios_setup(char *str) -{ - return str; -} - -void __init pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - -int pcibios_enable_resources(struct pci_dev *dev) -{ - u16 cmd, old_cmd; - int idx; - struct resource *r; - - /* - * Don't touch the Nile 4 - */ - if (dev->vendor == PCI_VENDOR_ID_NEC && - dev->device == PCI_DEVICE_ID_NEC_NILE4) return 0; - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - old_cmd = cmd; - for (idx = 0; idx < 6; idx++) { - r = &dev->resource[idx]; - if (!r->start && r->end) { - printk(KERN_ERR "PCI: Device %s not available because " - "of resource collisions\n", dev->slot_name); - return -EINVAL; - } - if (r->flags & IORESOURCE_IO) - cmd |= PCI_COMMAND_IO; - if (r->flags & IORESOURCE_MEM) - cmd |= PCI_COMMAND_MEMORY; - } - if (cmd != old_cmd) { - printk("PCI: Enabling device %s (%04x -> %04x)\n", - dev->slot_name, old_cmd, cmd); - pci_write_config_word(dev, PCI_COMMAND, cmd); - } - return 0; -} - -int pcibios_enable_device(struct pci_dev *dev) -{ - return pcibios_enable_resources(dev); -} - -void pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) -{ - struct pci_dev *dev = data; - - if (res->flags & IORESOURCE_IO) { - unsigned long start = res->start; - - /* We need to avoid collisions with `mirrored' VGA ports - and other strange ISA hardware, so we always want the - addresses kilobyte aligned. */ - if (size > 0x100) { - printk(KERN_ERR "PCI: I/O Region %s/%d too large" - " (%ld bytes)\n", dev->slot_name, - dev->resource - res, size); - } - - start = (start + 1024 - 1) & ~(1024 - 1); - res->start = start; - } -} - -unsigned __init int pcibios_assign_all_busses(void) -{ - return 1; -} - -struct pci_fixup pcibios_fixups[] = { }; --- linux-2.5.73/arch/mips/ddb5074/prom.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,36 +0,0 @@ -/* - * arch/mips/ddb5074/prom.c -- NEC DDB Vrc-5074 PROM routines - * - * Copyright (C) 2000 Geert Uytterhoeven - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include -#include -#include -#include - -#include -#include - - -char arcs_cmdline[COMMAND_LINE_SIZE]; - -void __init prom_init(const char *s) -{ - int i = 0; - - if (s != (void *) -1) - while (*s && i < sizeof(arcs_cmdline) - 1) - arcs_cmdline[i++] = *s++; - arcs_cmdline[i] = '\0'; - - mips_machgroup = MACH_GROUP_NEC_DDB; - mips_machtype = MACH_NEC_DDB5074; - - /* 64 MB non-upgradable */ - add_memory_region(0, 64 << 20, BOOT_MEM_RAM); -} - -void __init prom_free_prom_memory(void) -{ -} --- linux-2.5.73/arch/mips/ddb5074/setup.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,246 +0,0 @@ -/* - * arch/mips/ddb5074/setup.c -- NEC DDB Vrc-5074 setup routines - * - * Copyright (C) 2000 Geert Uytterhoeven - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - - -#ifdef CONFIG_REMOTE_DEBUG -extern void rs_kgdb_hook(int); -extern void breakpoint(void); -#endif - -#if defined(CONFIG_SERIAL_CONSOLE) -extern void console_setup(char *); -#endif - -extern struct ide_ops std_ide_ops; -extern struct rtc_ops ddb_rtc_ops; - -static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000; - -static void ddb_machine_restart(char *command) -{ - u32 t; - - /* PCI cold reset */ - t = nile4_in32(NILE4_PCICTRL + 4); - t |= 0x40000000; - nile4_out32(NILE4_PCICTRL + 4, t); - /* CPU cold reset */ - t = nile4_in32(NILE4_CPUSTAT); - t |= 1; - nile4_out32(NILE4_CPUSTAT, t); - /* Call the PROM */ - back_to_prom(); -} - -static void ddb_machine_halt(void) -{ - printk("DDB Vrc-5074 halted.\n"); - do { - } while (1); -} - -static void ddb_machine_power_off(void) -{ - printk("DDB Vrc-5074 halted. Please turn off the power.\n"); - do { - } while (1); -} - -extern void ddb_irq_setup(void); - -void (*board_time_init) (struct irqaction * irq); - - -static void __init ddb_time_init(struct irqaction *irq) -{ - /* set the clock to 1 Hz */ - nile4_out32(NILE4_T2CTRL, 1000000); - /* enable the General-Purpose Timer */ - nile4_out32(NILE4_T2CTRL + 4, 0x00000001); - /* reset timer */ - nile4_out32(NILE4_T2CNTR, 0); - /* enable interrupt */ - nile4_enable_irq(NILE4_INT_GPT); - i8259_setup_irq(nile4_to_irq(NILE4_INT_GPT), irq); - change_cp0_status(ST0_IM, - IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); -} - -void __init ddb_setup(void) -{ - extern int panic_timeout; - - irq_setup = ddb_irq_setup; - mips_io_port_base = NILE4_PCI_IO_BASE; - isa_slot_offset = NILE4_PCI_MEM_BASE; - request_region(0x00, 0x20, "dma1"); - request_region(0x40, 0x20, "timer"); - request_region(0x70, 0x10, "rtc"); - request_region(0x80, 0x10, "dma page reg"); - request_region(0xc0, 0x20, "dma2"); - board_time_init = ddb_time_init; - - _machine_restart = ddb_machine_restart; - _machine_halt = ddb_machine_halt; - _machine_power_off = ddb_machine_power_off; - -#ifdef CONFIG_BLK_DEV_IDE - ide_ops = &std_ide_ops; -#endif - rtc_ops = &ddb_rtc_ops; - - /* Reboot on panic */ - panic_timeout = 180; -} - - -#define USE_NILE4_SERIAL 0 - -#if USE_NILE4_SERIAL -#define ns16550_in(reg) nile4_in8((reg)*8) -#define ns16550_out(reg, val) nile4_out8((reg)*8, (val)) -#else -#define NS16550_BASE (NILE4_PCI_IO_BASE+0x03f8) -static inline u8 ns16550_in(u32 reg) -{ - return *(volatile u8 *) (NS16550_BASE + reg); -} - -static inline void ns16550_out(u32 reg, u8 val) -{ - *(volatile u8 *) (NS16550_BASE + reg) = val; -} -#endif - -#define NS16550_RBR 0 -#define NS16550_THR 0 -#define NS16550_DLL 0 -#define NS16550_IER 1 -#define NS16550_DLM 1 -#define NS16550_FCR 2 -#define NS16550_IIR 2 -#define NS16550_LCR 3 -#define NS16550_MCR 4 -#define NS16550_LSR 5 -#define NS16550_MSR 6 -#define NS16550_SCR 7 - -#define NS16550_LSR_DR 0x01 /* Data ready */ -#define NS16550_LSR_OE 0x02 /* Overrun */ -#define NS16550_LSR_PE 0x04 /* Parity error */ -#define NS16550_LSR_FE 0x08 /* Framing error */ -#define NS16550_LSR_BI 0x10 /* Break */ -#define NS16550_LSR_THRE 0x20 /* Xmit holding register empty */ -#define NS16550_LSR_TEMT 0x40 /* Xmitter empty */ -#define NS16550_LSR_ERR 0x80 /* Error */ - - -void _serinit(void) -{ -#if USE_NILE4_SERIAL - ns16550_out(NS16550_LCR, 0x80); - ns16550_out(NS16550_DLM, 0x00); - ns16550_out(NS16550_DLL, 0x36); /* 9600 baud */ - ns16550_out(NS16550_LCR, 0x00); - ns16550_out(NS16550_LCR, 0x03); - ns16550_out(NS16550_FCR, 0x47); -#else - /* done by PMON */ -#endif -} - -void _putc(char c) -{ - while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE)); - ns16550_out(NS16550_THR, c); - if (c == '\n') { - while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE)); - ns16550_out(NS16550_THR, '\r'); - } -} - -void _puts(const char *s) -{ - char c; - while ((c = *s++)) - _putc(c); -} - -char _getc(void) -{ - while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR)); - return ns16550_in(NS16550_RBR); -} - -int _testc(void) -{ - return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0; -} - - -/* - * Hexadecimal 7-segment LED - */ -void ddb5074_led_hex(int hex) -{ - outb(hex, 0x80); -} - - -/* - * LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543 - */ -struct pci_dev *pci_pmu = NULL; - -void ddb5074_led_d2(int on) -{ - u8 t; - - if (pci_pmu) { - pci_read_config_byte(pci_pmu, 0x7e, &t); - if (on) - t &= 0x7f; - else - t |= 0x80; - pci_write_config_byte(pci_pmu, 0x7e, t); - } -} - -void ddb5074_led_d3(int on) -{ - u8 t; - - if (pci_pmu) { - pci_read_config_byte(pci_pmu, 0x7e, &t); - if (on) - t &= 0xbf; - else - t |= 0x40; - pci_write_config_byte(pci_pmu, 0x7e, t); - } -} --- linux-2.5.73/arch/mips/ddb5074/time.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,32 +0,0 @@ -/* - * arch/mips/ddb5074/time.c -- Timer routines - * - * Copyright (C) 2000 Geert Uytterhoeven - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include -#include - -static unsigned char ddb_rtc_read_data(unsigned long addr) -{ - outb_p(addr, RTC_PORT(0)); - - return inb_p(RTC_PORT(1)); -} - -static void ddb_rtc_write_data(unsigned char data, unsigned long addr) -{ - outb_p(addr, RTC_PORT(0)); - outb_p(data, RTC_PORT(1)); -} - -static int ddb_rtc_bcd_mode(void) -{ - return 1; -} - -struct rtc_ops ddb_rtc_ops = { - ddb_rtc_read_data, - ddb_rtc_write_data, - ddb_rtc_bcd_mode -}; --- linux-2.5.73/arch/mips/ddb5476/dbg_io.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,125 +0,0 @@ - -#include - -#if (defined(CONFIG_DDB5476) && defined(CONFIG_REMOTE_DEBUG)) - -/* --- CONFIG --- */ - -/* we need uint32 uint8 */ -/* #include "types.h" */ -typedef unsigned char uint8; -typedef unsigned int uint32; - -/* --- END OF CONFIG --- */ - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* ----------------------------------------------------- */ - -/* === CONFIG === */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE 0xa60002f8 -#define MAX_BAUD 115200 - -/* === END OF CONFIG === */ - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE 1 -#define OFS_INTR_ID 2 -#define OFS_DATA_FORMAT 3 -#define OFS_LINE_CONTROL 3 -#define OFS_MODEM_CONTROL 4 -#define OFS_RS232_OUTPUT 4 -#define OFS_LINE_STATUS 5 -#define OFS_MODEM_STATUS 6 -#define OFS_RS232_INPUT 6 -#define OFS_SCRATCH_PAD 7 - -#define OFS_DIVISOR_LSB 0 -#define OFS_DIVISOR_MSB 1 - - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) -#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) - -void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) -{ - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up buad rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - -static int remoteDebugInitialized = 0; - -uint8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - return UART16550_READ(OFS_RCV_BUFFER); -} - - -int putDebugChar(uint8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_9600, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} - -#endif --- linux-2.5.73/arch/mips/ddb5476/int-handler.S 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,136 +0,0 @@ -/* - * arch/mips/ddb5074/int-handler.S -- NEC DDB Vrc-5074 interrupt handler - * - * Based on arch/mips/sgi/kernel/indyIRQ.S - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * - * Copyright (C) 2000 Geert Uytterhoeven - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include -#include -#include -#include - -/* - * A lot of complication here is taken away because: - * - * 1) We handle one interrupt and return, sitting in a loop and moving across - * all the pending IRQ bits in the cause register is _NOT_ the answer, the - * common case is one pending IRQ so optimize in that direction. - * - * 2) We need not check against bits in the status register IRQ mask, that - * would make this routine slow as hell. - * - * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in - * between like BSD spl() brain-damage. - * - * Furthermore, the IRQs on the INDY look basically (barring software IRQs - * which we don't use at all) like: - * - * MIPS IRQ Source - * -------- ------ - * 0 Software (ignored) - * 1 Software (ignored) - * 2 Local IRQ level zero - * 3 Local IRQ level one - * 4 8254 Timer zero - * 5 8254 Timer one - * 6 Bus Error - * 7 R4k timer (what we use) - * - * We handle the IRQ according to _our_ priority which is: - * - * Highest ---- R4k Timer - * Local IRQ zero - * Local IRQ one - * Bus Error - * 8254 Timer zero - * Lowest ---- 8254 Timer one - * - * then we just return, if multiple IRQs are pending then we will just take - * another exception, big deal. - */ - - .text - .set noreorder - .set noat - .align 5 - NESTED(ddbIRQ, PT_SIZE, sp) - SAVE_ALL - CLI - .set at - mfc0 s1, CP0_CAUSE # get irq mask - -#if 1 - mfc0 t2,CP0_STATUS # get enabled interrupts - and s0, s1, t2 # isolate allowed ones -#endif - /* First we check for r4k counter/timer IRQ. */ - andi a0, s0, CAUSEF_IP7 # cpu timer */ - bnez a0, cpu_timer_irq - andi a0, s0, CAUSEF_IP2 # delay slot, check local level zero - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP3 # delay slot, check local level one - - /* Wheee, local level zero interrupt. */ - jal ddb_local0_irqdispatch - move a0, sp # delay slot - - j ret_from_irq - nop # delay slot - -1: - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP6 # delay slot, check bus error - - /* Wheee, local level one interrupt. */ - move a0, sp - jal ddb_local1_irqdispatch - nop - - j ret_from_irq - nop - -1: - beq a0, zero, 1f - nop - - /* Wheee, an asynchronous bus error... */ - move a0, sp - jal ddb_buserror_irq - nop - - j ret_from_irq - nop - -1: - /* Here by mistake? This is possible, what can happen - * is that by the time we take the exception the IRQ - * pin goes low, so just leave if this is the case. - */ - andi a0, s0, (CAUSEF_IP4 | CAUSEF_IP5) - beq a0, zero, 1f - - /* Must be one of the 8254 timers... */ - move a0, sp - jal ddb_8254timer_irq - nop -1: - /* phamtom interrupt */ - move a0, s1 - jal ddb_phantom_irq - nop - j ret_from_irq - nop - -cpu_timer_irq: - li a0, 0 - move a1, sp - jal do_IRQ - /* jal ll_timer_interrupt */ - nop - j ret_from_irq - nop - END(ddbIRQ) --- linux-2.5.73/arch/mips/ddb5476/irq.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,251 +0,0 @@ -/* - * arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines - * - * Copyright (C) 2000 Geert Uytterhoeven - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -extern void __init i8259_init(void); -extern void i8259_disable_irq(unsigned int irq_nr); -extern void i8259_enable_irq(unsigned int irq_nr); - -extern asmlinkage void ddbIRQ(void); -extern asmlinkage void i8259_do_irq(int irq, struct pt_regs *regs); -extern asmlinkage void do_IRQ(int irq, struct pt_regs *regs); - - -void no_action(int cpl, void *dev_id, struct pt_regs *regs) -{ -} - - -#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */ -#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */ -#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */ - -#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */ -#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */ -#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */ - -#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */ -#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */ - -#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */ -#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */ - -#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */ -#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */ - -static struct { - struct resource m1543_config; - struct resource pic_elcr; -} m1543_ioport = { - { "M1543 config", M1543_PNP_CONFIG, M1543_PNP_CONFIG + 1, - IORESOURCE_BUSY}, - { "pic ELCR", M1543_INT1_MASTER_ELCR, M1543_INT1_MASTER_ELCR + 1, - IORESOURCE_BUSY} -}; - -static void m1543_irq_setup(void) -{ - /* - * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all - * the possible IO sources in the M1543 are in use by us. We will - * use the following mapping: - * - * IRQ1 - keyboard (default set by M1543) - * IRQ3 - reserved for UART B (default set by M1543) (note that - * the schematics for the DDB Vrc-5476 board seem to - * indicate that IRQ3 is connected to the DS1386 - * watchdog timer interrupt output so we might have - * a conflict) - * IRQ4 - reserved for UART A (default set by M1543) - * IRQ5 - parallel (default set by M1543) - * IRQ8 - DS1386 time of day (RTC) interrupt - * IRQ9 - USB (hardwired in ddb_setup) - * IRQ10 - PMU (hardwired in ddb_setup) - * IRQ12 - mouse - * IRQ14,15 - IDE controller (need to be confirmed, jsun) - */ - - /* - * Assing mouse interrupt to IRQ12 - */ - - /* Enter configuration mode */ - outb(0x51, M1543_PNP_CONFIG); - outb(0x23, M1543_PNP_CONFIG); - - /* Select logical device 7 (Keyboard) */ - outb(0x07, M1543_PNP_INDEX); - outb(0x07, M1543_PNP_DATA); - - /* Select IRQ12 */ - outb(0x72, M1543_PNP_INDEX); - outb(0x0c, M1543_PNP_DATA); - - /* Leave configration mode */ - outb(0xbb, M1543_PNP_CONFIG); - - - /* Initialize the 8259 PIC in the M1543 */ - i8259_init(); - - /* Enable the interrupt cascade from M1543 */ - nile4_enable_irq(NILE4_INT_INTC); - - /* request io ports */ - if (request_resource(&ioport_resource, &m1543_ioport.m1543_config) - || request_resource(&ioport_resource, &m1543_ioport.pic_elcr)) { - printk("m1543_irq_setup : requesting io ports failed.\n"); - for (;;); - } -} - -static void nile4_irq_setup(void) -{ - int i; - - /* Map all interrupts to CPU int #0 */ - nile4_map_irq_all(0); - - /* PCI INTA#-E# must be level triggered */ - nile4_set_pci_irq_level_or_edge(0, 1); - nile4_set_pci_irq_level_or_edge(1, 1); - nile4_set_pci_irq_level_or_edge(2, 1); - nile4_set_pci_irq_level_or_edge(3, 1); - - /* PCI INTA#, B#, D# must be active low, INTC# must be active high */ - nile4_set_pci_irq_polarity(0, 0); - nile4_set_pci_irq_polarity(1, 0); - nile4_set_pci_irq_polarity(2, 1); - nile4_set_pci_irq_polarity(3, 0); - - for (i = 0; i < 16; i++) - nile4_clear_irq(i); - - /* Enable CPU int #0 */ - nile4_enable_irq_output(0); - - /* memory resource acquire in ddb_setup */ -} - - -/* - * IRQ2 is cascade interrupt to second interrupt controller - */ -static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL }; - - -void disable_irq(unsigned int irq_nr) -{ - if (is_i8259_irq(irq_nr)) - i8259_disable_irq(irq_nr); - else - nile4_disable_irq(irq_to_nile4(irq_nr)); -} - -void enable_irq(unsigned int irq_nr) -{ - if (is_i8259_irq(irq_nr)) - i8259_enable_irq(irq_nr); - else - nile4_enable_irq(irq_to_nile4(irq_nr)); -} - -int table[16] = { 0, }; - -void ddb_local0_irqdispatch(struct pt_regs *regs) -{ - u32 mask; - int nile4_irq; -#if 0 - volatile static int nesting = 0; - if (nesting++ == 0) - ddb5476_led_d3(1); - ddb5476_led_hex(nesting < 16 ? nesting : 15); -#endif - - mask = nile4_get_irq_stat(0); - nile4_clear_irq_mask(mask); - - /* Handle the timer interrupt first */ - if (mask & (1 << NILE4_INT_GPT)) { - nile4_disable_irq(NILE4_INT_GPT); - do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs); - nile4_enable_irq(NILE4_INT_GPT); - mask &= ~(1 << NILE4_INT_GPT); - } - for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) - if (mask & 1) { - nile4_disable_irq(nile4_irq); - if (nile4_irq == NILE4_INT_INTC) { - int i8259_irq = nile4_i8259_iack(); - i8259_do_irq(i8259_irq, regs); - } else { - do_IRQ(nile4_to_irq(nile4_irq), regs); - } - nile4_enable_irq(nile4_irq); - } -#if 0 - if (--nesting == 0) - ddb5476_led_d3(0); - ddb5476_led_hex(nesting < 16 ? nesting : 15); -#endif -} - -void ddb_local1_irqdispatch(void) -{ - printk("ddb_local1_irqdispatch called\n"); -} - -void ddb_buserror_irq(void) -{ - printk("ddb_buserror_irq called\n"); -} - -void ddb_8254timer_irq(void) -{ - printk("ddb_8254timer_irq called\n"); -} - -void ddb_phantom_irq(unsigned long cause) -{ - printk("phantom interrupts detected : \n"); - printk("\tcause \t\t0x%08x\n", cause); - printk("\tcause reg\t0x%08x\n", - read_32bit_cp0_register(CP0_CAUSE)); - printk("\tstatus reg\t0x%08x\n", - read_32bit_cp0_register(CP0_STATUS)); -} - -void __init ddb_irq_setup(void) -{ -#ifdef CONFIG_REMOTE_DEBUG - printk("Wait for gdb client connection ...\n"); - set_debug_traps(); - breakpoint(); /* you may move this line to whereever you want :-) */ -#endif - i8259_setup_irq(2, &irq2); - - nile4_irq_setup(); - m1543_irq_setup(); - - /* we pin #0 - #4 (no internal timer) */ - change_cp0_status(ST0_IM, - IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); - - set_except_vector(0, ddbIRQ); -} --- linux-2.5.73/arch/mips/ddb5476/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,10 +0,0 @@ -# -# Makefile for the NEC DDB Vrc-5074 specific kernel interface routines -# under Linux. -# - -EXTRA_AFLAGS := $(CFLAGS) - -obj-y += setup.o irq.o time.o prom.o pci.o \ - int-handler.o nile4.o -obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o --- linux-2.5.73/arch/mips/ddb5476/nile4.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,293 +0,0 @@ -/* - * arch/mips/ddb5074/nile4.c -- NEC Vrc-5074 Nile 4 support routines - * - * Copyright (C) 2000 Geert Uytterhoeven - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include -#include - -#include - - -/* - * Physical Device Address Registers - * - * Note: 32 bit addressing only! - */ -void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width, - int on_memory_bus, int visible) -{ - u32 maskbits; - u32 widthbits; - - if (pdar > NILE4_BOOTCS || (pdar & 7)) { - printk("nile4_set_pdar: invalid pdar %d\n", pdar); - return; - } - if (pdar == NILE4_INTCS && size != 0x00200000) { - printk("nile4_set_pdar: INTCS size must be 2 MB\n"); - return; - } - switch (size) { -#if 0 /* We don't support 4 GB yet */ - case 0x100000000: /* 4 GB */ - maskbits = 4; - break; -#endif - case 0x80000000: /* 2 GB */ - maskbits = 5; - break; - case 0x40000000: /* 1 GB */ - maskbits = 6; - break; - case 0x20000000: /* 512 MB */ - maskbits = 7; - break; - case 0x10000000: /* 256 MB */ - maskbits = 8; - break; - case 0x08000000: /* 128 MB */ - maskbits = 9; - break; - case 0x04000000: /* 64 MB */ - maskbits = 10; - break; - case 0x02000000: /* 32 MB */ - maskbits = 11; - break; - case 0x01000000: /* 16 MB */ - maskbits = 12; - break; - case 0x00800000: /* 8 MB */ - maskbits = 13; - break; - case 0x00400000: /* 4 MB */ - maskbits = 14; - break; - case 0x00200000: /* 2 MB */ - maskbits = 15; - break; - case 0: /* OFF */ - maskbits = 0; - break; - default: - printk("nile4_set_pdar: unsupported size %p\n", - (void *) size); - return; - } - switch (width) { - case 8: - widthbits = 0; - break; - case 16: - widthbits = 1; - break; - case 32: - widthbits = 2; - break; - case 64: - widthbits = 3; - break; - default: - printk("nile4_set_pdar: unsupported width %d\n", width); - return; - } - nile4_out32(pdar, maskbits | (on_memory_bus ? 0x10 : 0) | - (visible ? 0x20 : 0) | (widthbits << 6) | - (phys & 0xffe00000)); - nile4_out32(pdar + 4, 0); - /* - * When programming a PDAR, the register should be read immediately - * after writing it. This ensures that address decoders are properly - * configured. - */ - nile4_in32(pdar); - nile4_in32(pdar + 4); -} - - -/* - * PCI Master Registers - * - * Note: 32 bit addressing only! - */ -void nile4_set_pmr(u32 pmr, u32 type, u32 addr) -{ - if (pmr != NILE4_PCIINIT0 && pmr != NILE4_PCIINIT1) { - printk("nile4_set_pmr: invalid pmr %d\n", pmr); - return; - } - switch (type) { - case NILE4_PCICMD_IACK: /* PCI Interrupt Acknowledge */ - case NILE4_PCICMD_IO: /* PCI I/O Space */ - case NILE4_PCICMD_MEM: /* PCI Memory Space */ - case NILE4_PCICMD_CFG: /* PCI Configuration Space */ - break; - default: - printk("nile4_set_pmr: invalid type %d\n", type); - return; - } - nile4_out32(pmr, (type << 1) | 0x10 | (addr & 0xffe00000)); - nile4_out32(pmr + 4, 0); -} - - -/* - * Interrupt Programming - */ -void nile4_map_irq(int nile4_irq, int cpu_irq) -{ - u32 offset, t; - - offset = NILE4_INTCTRL; - if (nile4_irq >= 8) { - offset += 4; - nile4_irq -= 8; - } - t = nile4_in32(offset); - t &= ~(7 << (nile4_irq * 4)); - t |= cpu_irq << (nile4_irq * 4); - nile4_out32(offset, t); -} - -void nile4_map_irq_all(int cpu_irq) -{ - u32 all, t; - - all = cpu_irq; - all |= all << 4; - all |= all << 8; - all |= all << 16; - t = nile4_in32(NILE4_INTCTRL); - t &= 0x88888888; - t |= all; - nile4_out32(NILE4_INTCTRL, t); - t = nile4_in32(NILE4_INTCTRL + 4); - t &= 0x88888888; - t |= all; - nile4_out32(NILE4_INTCTRL + 4, t); -} - -void nile4_enable_irq(int nile4_irq) -{ - u32 offset, t; - - offset = NILE4_INTCTRL; - if (nile4_irq >= 8) { - offset += 4; - nile4_irq -= 8; - } - t = nile4_in32(offset); - t |= 8 << (nile4_irq * 4); - nile4_out32(offset, t); -} - -void nile4_disable_irq(int nile4_irq) -{ - u32 offset, t; - - offset = NILE4_INTCTRL; - if (nile4_irq >= 8) { - offset += 4; - nile4_irq -= 8; - } - t = nile4_in32(offset); - t &= ~(8 << (nile4_irq * 4)); - nile4_out32(offset, t); -} - -void nile4_disable_irq_all(void) -{ - nile4_out32(NILE4_INTCTRL, 0); - nile4_out32(NILE4_INTCTRL + 4, 0); -} - -u16 nile4_get_irq_stat(int cpu_irq) -{ - return nile4_in16(NILE4_INTSTAT0 + cpu_irq * 2); -} - -void nile4_enable_irq_output(int cpu_irq) -{ - u32 t; - - t = nile4_in32(NILE4_INTSTAT1 + 4); - t |= 1 << (16 + cpu_irq); - nile4_out32(NILE4_INTSTAT1, t); -} - -void nile4_disable_irq_output(int cpu_irq) -{ - u32 t; - - t = nile4_in32(NILE4_INTSTAT1 + 4); - t &= ~(1 << (16 + cpu_irq)); - nile4_out32(NILE4_INTSTAT1, t); -} - -void nile4_set_pci_irq_polarity(int pci_irq, int high) -{ - u32 t; - - t = nile4_in32(NILE4_INTPPES); - if (high) - t &= ~(1 << (pci_irq * 2)); - else - t |= 1 << (pci_irq * 2); - nile4_out32(NILE4_INTPPES, t); -} - -void nile4_set_pci_irq_level_or_edge(int pci_irq, int level) -{ - u32 t; - - t = nile4_in32(NILE4_INTPPES); - if (level) - t |= 2 << (pci_irq * 2); - else - t &= ~(2 << (pci_irq * 2)); - nile4_out32(NILE4_INTPPES, t); -} - -void nile4_clear_irq(int nile4_irq) -{ - nile4_out32(NILE4_INTCLR, 1 << nile4_irq); -} - -void nile4_clear_irq_mask(u32 mask) -{ - nile4_out32(NILE4_INTCLR, mask); -} - -u8 nile4_i8259_iack(void) -{ - u8 irq; - - /* Set window 0 for interrupt acknowledge */ - nile4_set_pmr(NILE4_PCIINIT0, NILE4_PCICMD_IACK, 0); - irq = *(volatile u8 *) NILE4_PCI_IACK_BASE; - /* Set window 0 for PCI I/O space */ - nile4_set_pmr(NILE4_PCIINIT0, NILE4_PCICMD_IO, 0); - return irq; -} - -#if 0 -void nile4_dump_irq_status(void) -{ - printk("CPUSTAT = %p:%p\n", (void *) nile4_in32(NILE4_CPUSTAT + 4), - (void *) nile4_in32(NILE4_CPUSTAT)); - printk("INTCTRL = %p:%p\n", (void *) nile4_in32(NILE4_INTCTRL + 4), - (void *) nile4_in32(NILE4_INTCTRL)); - printk("INTSTAT0 = %p:%p\n", - (void *) nile4_in32(NILE4_INTSTAT0 + 4), - (void *) nile4_in32(NILE4_INTSTAT0)); - printk("INTSTAT1 = %p:%p\n", - (void *) nile4_in32(NILE4_INTSTAT1 + 4), - (void *) nile4_in32(NILE4_INTSTAT1)); - printk("INTCLR = %p:%p\n", (void *) nile4_in32(NILE4_INTCLR + 4), - (void *) nile4_in32(NILE4_INTCLR)); - printk("INTPPES = %p:%p\n", (void *) nile4_in32(NILE4_INTPPES + 4), - (void *) nile4_in32(NILE4_INTPPES)); -} -#endif --- linux-2.5.73/arch/mips/ddb5476/pci.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,430 +0,0 @@ -/* - * arch/mips/ddb5476/pci.c -- NEC DDB Vrc-5074 PCI access routines - * - * Copyright (C) 2000 Geert Uytterhoeven - * Albert Dorofeev - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include -#include -#include -#include -#include -#include - -#include - -static u32 nile4_pre_pci_access0(int slot_num) -{ - u32 pci_addr = 0; - u32 virt_addr = NILE4_PCI_CFG_BASE; - - /* work around the bug for Vrc5476 */ - if (slot_num == 13) - return NILE4_BASE + NILE4_PCI_BASE; - - /* Set window 1 address 08000000 - 32 bit - 128 MB (PCI config space) */ - nile4_set_pdar(NILE4_PCIW1, PHYSADDR(virt_addr), 0x08000000, 32, 0, - 0); - - // [jsun] we start scanning from addr:10, - // with 128M we can go up to addr:26 (slot 16) - if (slot_num <= 16) { - virt_addr += 0x00000400 << slot_num; - } else { - /* for high slot, we have to set higher PCI base addr */ - pci_addr = 0x00000400 << slot_num; - } - nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_CFG, pci_addr); - return virt_addr; -} - -static void nile4_post_pci_access0(void) -{ - /* - * Set window 1 back to address 08000000 - 32 bit - 128 MB - * (PCI IO space) - */ - nile4_set_pdar(NILE4_PCIW1, PHYSADDR(NILE4_PCI_MEM_BASE), - 0x08000000, 32, 1, 1); - // nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0); - nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0x08000000); -} - -static int nile4_pci_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 * val) -{ - int status, slot_num, func_num; - u32 result, base, addr; - - if(size == 4) { - /* Do we need to generate type 1 configure transaction? */ - if (bus->number) { - /* FIXME - not working yet */ - return PCIBIOS_FUNC_NOT_SUPPORTED; - /* - * the largest type 1 configuration addr is 16M, - * < 256M config space - */ - slot_num = 0; - addr = (bus->number << 16) | (devfn < 8) | where | 1; - } else { - slot_num = PCI_SLOT(devfn); - func_num = PCI_FUNC(devfn); - addr = (func_num << 8) + where; - } - base = nile4_pre_pci_access0(slot_num); - *val = *(volatile u32 *) (base + addr); - nile4_post_pci_access0(); - return PCIBIOS_SUCCESSFUL; - } - - status = nile4_pci_read(bus, devfn, where & ~3, 4, &result); - if (status != PCIBIOS_SUCCESSFUL) - return status; - switch (size) { - case 1: - if (where & 1) - result >>= 8; - if (where & 2) - result >>= 16; - *val = (u8)(result & 0xff); - break; - case 2: - if (where & 2) - result >>= 16; - *val = (u16)(result & 0xffff); - break; - } - return PCIBIOS_SUCCESSFUL; -} - -static int nile4_pci_write(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) -{ - int status, slot_num, func_num, shift = 0; - u32 result, base, addr; - - status = nile4_pci_read(bus, devfn, where & ~3, 4, &result); - if (status != PCIBIOS_SUCCESSFUL) - return status; - switch (size) { - case 1: - if (where & 2) - shift += 16; - if (where & 1) - shift += 8; - result &= ~(0xff << shift); - result |= val << shift; - break; - case 2: - if (where & 2) - shift += 16; - result &= ~(0xffff << shift); - result |= val << shift; - break; - case 4: - /* Do we need to generate type 1 configure transaction? */ - if (bus->number) { - /* FIXME - not working yet */ - return PCIBIOS_FUNC_NOT_SUPPORTED; - - /* the largest type 1 configuration addr is 16M, - * < 256M config space */ - slot_num = 0; - addr = (bus->number << 16) | (devfn < 8) | - where | 1; - } else { - slot_num = PCI_SLOT(devfn); - func_num = PCI_FUNC(devfn); - addr = (func_num << 8) + where; - } - - base = nile4_pre_pci_access0(slot_num); - *(volatile u32 *) (base + addr) = val; - nile4_post_pci_access0(); - return PCIBIOS_SUCCESSFUL; - } - return nile4_pci_write(bus, devfn, where & ~3, 4, result); -} - -struct pci_ops nile4_pci_ops = { - .read = nile4_pci_read, - .write = nile4_pci_write, -}; - -struct { - struct resource ram; - struct resource flash; - struct resource isa_io; - struct resource pci_io; - struct resource isa_mem; - struct resource pci_mem; - struct resource nile4; - struct resource boot; -} ddb5476_resources = { - // { "RAM", 0x00000000, 0x03ffffff, IORESOURCE_MEM | PCI_BASE_ADDRESS_MEM_TYPE_64 }, - { - "RAM", 0x00000000, 0x03ffffff, IORESOURCE_MEM}, { - "Flash ROM", 0x04000000, 0x043fffff}, { - "Nile4 ISA I/O", 0x06000000, 0x060fffff}, { - "Nile4 PCI I/O", 0x06100000, 0x07ffffff}, { - "Nile4 ISA mem", 0x08000000, 0x08ffffff, IORESOURCE_MEM}, { - "Nile4 PCI mem", 0x09000000, 0x0fffffff, IORESOURCE_MEM}, - // { "Nile4 ctrl", 0x1fa00000, 0x1fbfffff, IORESOURCE_MEM | PCI_BASE_ADDRESS_MEM_TYPE_64 }, - { - "Nile4 ctrl", 0x1fa00000, 0x1fbfffff, IORESOURCE_MEM}, { - "Boot ROM", 0x1fc00000, 0x1fffffff} -}; - -struct resource M5229_resources[5] = { - {"M5229 BAR0", 0x1f0, 0x1f3, IORESOURCE_IO}, - {"M5229 BAR1", 0x3f4, 0x3f7, IORESOURCE_IO}, - {"M5229 BAR2", 0x170, 0x173, IORESOURCE_IO}, - {"M5229 BAR3", 0x374, 0x377, IORESOURCE_IO}, - {"M5229 BAR4", 0xf000, 0xf00f, IORESOURCE_IO} -}; - -static void __init ddb5476_pci_fixup(void) -{ - struct pci_dev *dev = NULL; - - while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { - if (dev->vendor == PCI_VENDOR_ID_NEC && - dev->device == PCI_DEVICE_ID_NEC_VRC5476) { - /* - * The first 64-bit PCI base register should point to - * the Nile4 control registers. Unfortunately this - * isn't the case, so we fix it ourselves. This allows - * the serial driver to find the UART. - */ - dev->resource[0] = ddb5476_resources.nile4; - request_resource(&iomem_resource, - &dev->resource[0]); - /* - * The second 64-bit PCI base register points to the - * first memory bank. Unfortunately the address is - * wrong, so we fix it (again). - */ - - /* [jsun] We cannot request the resource anymore, - * because kernel/setup.c has already reserved "System - * RAM" resource at the same spot. - * The fundamental problem here is that PCI host - * controller should not put system RAM mapping in BAR - * and make subject to PCI resource assignement. - * Current fix is a total hack. We set parent to 1 so - * so that PCI resource assignement code is fooled to - * think the resource is assigned, and will not attempt - * to mess with it. - */ - dev->resource[2] = ddb5476_resources.ram; - if (request_resource(&iomem_resource, - &dev->resource[2]) ) { - dev->resource[2].parent = 0x1; - } - - } else if (dev->vendor == PCI_VENDOR_ID_AL - && dev->device == PCI_DEVICE_ID_AL_M7101) { - /* - * It's nice to have the LEDs on the GPIO pins - * available for debugging - */ - extern struct pci_dev *pci_pmu; - u8 t8; - - pci_pmu = dev; /* for LEDs D2 and D3 */ - /* Program the lines for LEDs D2 and D3 to output */ - nile4_pci_read(dev->bus, dev->devfn, 0x7d, 1, &t8); - t8 |= 0xc0; - nile4_pci_write(dev->bus, dev->devfn, 0x7d, 1, t8); - /* Turn LEDs D2 and D3 off */ - nile4_pci_read(dev->bus, dev->devfn, 0x7e, 1, &t8); - t8 |= 0xc0; - nile4_pci_write(dev->bus, dev->devfn, 0x7e, 1, t8); - } else if (dev->vendor == PCI_VENDOR_ID_AL && - dev->device == 0x5229) { - int i; - for (i = 0; i < 5; i++) { - dev->resource[i] = M5229_resources[i]; - request_resource(&ioport_resource, - &dev->resource[i]); - } - } - } -} - -static void __init pcibios_fixup_irqs(void) -{ - struct pci_dev *dev = NULL; - int slot_num; - - while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { - slot_num = PCI_SLOT(dev->devfn); - switch (slot_num) { - case 3: /* re-programmed to USB */ - dev->irq = 9; /* hard-coded; see irq.c */ - break; - case 4: /* re-programmed to PMU */ - dev->irq = 10; /* hard-coded; see irq.c */ - break; - case 6: /* on-board pci-pci bridge */ - dev->irq = 0xff; - break; - case 7: /* on-board ether */ - dev->irq = nile4_to_irq(NILE4_INT_INTB); - break; - case 8: /* ISA-PCI bridge */ - dev->irq = nile4_to_irq(NILE4_INT_INTC); - break; - case 9: /* ext slot #3 */ - dev->irq = nile4_to_irq(NILE4_INT_INTD); - break; - case 10: /* ext slot #4 */ - dev->irq = nile4_to_irq(NILE4_INT_INTA); - break; - case 13: /* Vrc5476 */ - dev->irq = 0xff; - break; - case 14: /* HD controller, M5229 */ - dev->irq = 14; - break; - default: - printk - ("JSUN : in pcibios_fixup_irqs - unkown slot %d\n", - slot_num); - panic - ("JSUN : in pcibios_fixup_irqs - unkown slot.\n"); - } - } -} - -void __init pcibios_init(void) -{ - printk("PCI: Emulate bios initialization \n"); - /* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */ - *(long *) (NILE4_BASE + NILE4_BAR0) = 0x8; - - printk("PCI: Probing PCI hardware\n"); - ioport_resource.end = 0x1ffffff; /* 32 MB */ - iomem_resource.end = 0x1fffffff; /* 512 MB */ - - /* `ram' and `nile4' are requested through the Nile4 pci_dev */ - request_resource(&iomem_resource, &ddb5476_resources.flash); - request_resource(&iomem_resource, &ddb5476_resources.isa_io); - request_resource(&iomem_resource, &ddb5476_resources.pci_io); - request_resource(&iomem_resource, &ddb5476_resources.isa_mem); - request_resource(&iomem_resource, &ddb5476_resources.pci_mem); - request_resource(&iomem_resource, &ddb5476_resources.boot); - - pci_scan_bus(0, &nile4_pci_ops, NULL); - ddb5476_pci_fixup(); - pci_assign_unassigned_resources(); - pcibios_fixup_irqs(); -} - -void __init pcibios_fixup_bus(struct pci_bus *bus) -{ - /* [jsun] we don't know how to fix sub-buses yet */ - if (bus->number == 0) { - bus->resource[1] = &ddb5476_resources.pci_mem; - } -} - -char *pcibios_setup(char *str) -{ - return str; -} - -void __init pcibios_update_irq(struct pci_dev *dev, int irq) -{ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); -} - -#if 0 /* original DDB5074 code */ -void __devinit -pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, - struct resource *res) -{ - /* - * our caller figure out range by going through the dev structures. - * I guess this is the place to fix things up if the bus is using a - * different view of the addressing space. - */ - - if (bus->number == 0) { - ranges->io_start -= bus->resource[0]->start; - ranges->io_end -= bus->resource[0]->start; - ranges->mem_start -= bus->resource[1]->start; - ranges->mem_end -= bus->resource[1]->start; - } -} -#endif - -int pcibios_enable_resources(struct pci_dev *dev) -{ - u16 cmd, old_cmd; - int idx; - struct resource *r; - - /* - * Don't touch the Nile 4 - */ - if (dev->vendor == PCI_VENDOR_ID_NEC && - dev->device == PCI_DEVICE_ID_NEC_VRC5476) return 0; - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - old_cmd = cmd; - for (idx = 0; idx < 6; idx++) { - r = &dev->resource[idx]; - if (!r->start && r->end) { - printk(KERN_ERR "PCI: Device %s not available because " - "of resource collisions\n", dev->slot_name); - return -EINVAL; - } - if (r->flags & IORESOURCE_IO) - cmd |= PCI_COMMAND_IO; - if (r->flags & IORESOURCE_MEM) - cmd |= PCI_COMMAND_MEMORY; - } - if (cmd != old_cmd) { - printk("PCI: Enabling device %s (%04x -> %04x)\n", - dev->slot_name, old_cmd, cmd); - pci_write_config_word(dev, PCI_COMMAND, cmd); - } - return 0; -} - -int pcibios_enable_device(struct pci_dev *dev) -{ - return pcibios_enable_resources(dev); -} - -void pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) -{ - struct pci_dev *dev = data; - - if (res->flags & IORESOURCE_IO) { - unsigned long start = res->start; - - /* We need to avoid collisions with `mirrored' VGA ports - and other strange ISA hardware, so we always want the - addresses kilobyte aligned. */ - if (size > 0x100) { - printk(KERN_ERR "PCI: I/O Region %s/%d too large" - " (%ld bytes)\n", dev->slot_name, - dev->resource - res, size); - } - - start = (start + 1024 - 1) & ~(1024 - 1); - res->start = start; - } -} - -unsigned __init int pcibios_assign_all_busses(void) -{ - return 1; -} - -struct pci_fixup pcibios_fixups[] = { {0} }; --- linux-2.5.73/arch/mips/ddb5476/prom.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,43 +0,0 @@ -/* - * arch/mips/ddb5476/prom.c -- NEC DDB Vrc-5476 PROM routines - * - * Copyright (C) 2000 Geert Uytterhoeven - * Sony Software Development Center Europe (SDCE), Brussels - * - * Jun Sun - modified for DDB5476. - */ -#include -#include -#include -#include - -#include -#include - - -char arcs_cmdline[COMMAND_LINE_SIZE]; - -/* [jsun@junsun.net] PMON passes arguments in C main() style */ -void __init prom_init(int argc, const char **arg) -{ - int i; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - if (strlen(arcs_cmdline) + strlen(arg[i] + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, arg[i]); - strcat(arcs_cmdline, " "); - } - - mips_machgroup = MACH_GROUP_NEC_DDB; - mips_machtype = MACH_NEC_DDB5476; - /* 64 MB non-upgradable */ - add_memory_region(0, 64 << 20, BOOT_MEM_RAM); -} - -void __init prom_free_prom_memory(void) -{ -} --- linux-2.5.73/arch/mips/ddb5476/setup.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,393 +0,0 @@ -/* - * arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines - * - * Copyright (C) 2000 Geert Uytterhoeven - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - - -#ifdef CONFIG_REMOTE_DEBUG -extern void rs_kgdb_hook(int); -extern void breakpoint(void); -#endif - -#if defined(CONFIG_SERIAL_CONSOLE) -extern void console_setup(char *); -#endif - -extern struct ide_ops std_ide_ops; -extern struct rtc_ops ddb_rtc_ops; -extern struct kbd_ops std_kbd_ops; - -static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000; - -static void ddb_machine_restart(char *command) -{ - u32 t; - - /* PCI cold reset */ - t = nile4_in32(NILE4_PCICTRL + 4); - t |= 0x40000000; - nile4_out32(NILE4_PCICTRL + 4, t); - /* CPU cold reset */ - t = nile4_in32(NILE4_CPUSTAT); - t |= 1; - nile4_out32(NILE4_CPUSTAT, t); - /* Call the PROM */ - back_to_prom(); -} - -static void ddb_machine_halt(void) -{ - printk("DDB Vrc-5476 halted.\n"); - while (1); -} - -static void ddb_machine_power_off(void) -{ - printk("DDB Vrc-5476 halted. Please turn off the power.\n"); - while (1); -} - -extern void ddb_irq_setup(void); - -static void __init ddb_time_init(struct irqaction *irq) -{ - printk("ddb_time_init invoked.\n"); - mips_counter_frequency = 83000000; -} - -static void __init ddb_timer_setup(struct irqaction *irq) -{ - unsigned int count; - - /* we are using the cpu counter for timer interrupts */ - i8259_setup_irq(0, irq); - set_cp0_status(IE_IRQ5); - - /* to generate the first timer interrupt */ - count = read_32bit_cp0_register(CP0_COUNT); - write_32bit_cp0_register(CP0_COMPARE, count + 1000); - -#if 0 /* the old way to do timer interrupt */ - /* set the clock to 100 Hz */ - nile4_out32(NILE4_T2CTRL, 830000); - /* enable the General-Purpose Timer */ - nile4_out32(NILE4_T2CTRL + 4, 0x00000001); - /* reset timer */ - nile4_out32(NILE4_T2CNTR, 0); - /* enable interrupt */ - nile4_enable_irq(NILE4_INT_GPT); - i8259_setup_irq(nile4_to_irq(NILE4_INT_GPT), irq); -#endif -} - -static struct { - struct resource dma1; - struct resource pic1; - struct resource timer; - struct resource rtc; - struct resource dma_page_reg; - struct resource pic2; - struct resource dma2; -} ddb5476_ioport = { - { - "dma1", 0x00, 0x1f, IORESOURCE_BUSY}, { - "pic1", 0x20, 0x3f, IORESOURCE_BUSY}, { - "timer", 0x40, 0x5f, IORESOURCE_BUSY}, { - "rtc", 0x70, 0x7f, IORESOURCE_BUSY}, { - "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, { - "pic2", 0xa0, 0xbf, IORESOURCE_BUSY}, { - "dma2", 0xc0, 0xdf, IORESOURCE_BUSY} -}; - -static struct { - struct resource nile4; -} ddb5476_iomem = { - { "Nile 4", NILE4_BASE, NILE4_BASE + NILE4_SIZE - 1, IORESOURCE_BUSY} -}; - -void __init ddb_setup(void) -{ - extern int panic_timeout; - - irq_setup = ddb_irq_setup; - mips_io_port_base = NILE4_PCI_IO_BASE; - isa_slot_offset = NILE4_PCI_MEM_BASE; - - board_time_init = ddb_time_init; - board_timer_setup = ddb_timer_setup; - - _machine_restart = ddb_machine_restart; - _machine_halt = ddb_machine_halt; - _machine_power_off = ddb_machine_power_off; - - /* request io port/mem resources */ - if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) || - request_resource(&ioport_resource, &ddb5476_ioport.pic1) || - request_resource(&ioport_resource, &ddb5476_ioport.timer) || - request_resource(&ioport_resource, &ddb5476_ioport.rtc) || - request_resource(&ioport_resource, - &ddb5476_ioport.dma_page_reg) - || request_resource(&ioport_resource, &ddb5476_ioport.pic2) - || request_resource(&ioport_resource, &ddb5476_ioport.dma2) - || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) { - printk - ("ddb_setup - requesting oo port resources failed.\n"); - for (;;); - } -#ifdef CONFIG_BLK_DEV_IDE - ide_ops = &std_ide_ops; -#endif - rtc_ops = &ddb_rtc_ops; - -#ifdef CONFIG_PC_KEYB - kbd_ops = &std_kbd_ops; -#endif - - /* Reboot on panic */ - panic_timeout = 180; - - /* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */ - /* *(long*)0xbfa00218 = 0x8; */ - -#ifdef CONFIG_FB - conswitchp = &dummy_con; -#endif - - - /* board initialization stuff - non-fundamental, but need to be set - * before kernel runs */ - - /* setup I/O space */ - nile4_set_pdar(NILE4_PCIW0, - PHYSADDR(NILE4_PCI_IO_BASE), 0x02000000, 32, 0, 0); - nile4_set_pmr(NILE4_PCIINIT0, NILE4_PCICMD_IO, 0); - - /* map config space to 0xa8000000, 128MB */ - nile4_set_pdar(NILE4_PCIW1, - PHYSADDR(NILE4_PCI_CFG_BASE), 0x08000000, 32, 0, 0); - nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_CFG, 0x0); - - /* ----- M1543 PCI setup ------ */ - - /* we know M1543 PCI-ISA controller is at addr:18 */ - /* xxxx1010 makes USB at addr:13 and PMU at addr:14 */ - *(volatile unsigned char *) 0xa8040072 &= 0xf0; - *(volatile unsigned char *) 0xa8040072 |= 0xa; - - /* setup USB interrupt to IRQ 9, (bit 0:3 - 0001) - * no IOCHRDY signal, (bit 7 - 1) - * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1) - * Bypass USB Master INTAJ level to edge conversion (bit 4 - 0) - */ - *(unsigned char *) 0xa8040074 = 0xc1; - - /* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011) - * SCI routing to IRQ 13 disabled (bit 7 - 1) - * SCI interrupt level to edge conversion bypassed (bit 4 - 0) - */ - *(unsigned char *) 0xa8040076 = 0x83; - - /* setup IDE controller - * enable IDE controller (bit 6 - 1) - * IDE IDSEL to be addr:24 (bit 4:5 - 11) - * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0) - * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0) - * primary IRQ is 14, secondary is 15 (bit 1:0 - 01 - */ - // *(unsigned char*)0xa8040058 = 0x71; - // *(unsigned char*)0xa8040058 = 0x79; - // *(unsigned char*)0xa8040058 = 0x74; // use SIRQ, primary tri-state - *(unsigned char *) 0xa8040058 = 0x75; // primary tri-state - -#if 0 - /* this is not necessary if M5229 does not use SIRQ */ - *(unsigned char *) 0xa8040044 = 0x0d; // primary to IRQ 14 - *(unsigned char *) 0xa8040075 = 0x0d; // secondary to IRQ 14 -#endif - - /* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */ - /* M5229 IDSEL is addr:24; see above setting */ - *(unsigned char *) 0xa9000050 |= 0x1; - - /* enable bus master (bit 2) and IO decoding (bit 0) */ - *(unsigned char *) 0xa9000004 |= 0x5; - - /* enable native, copied from arch/ppc/k2boot/head.S */ - /* TODO - need volatile, need to be portable */ - *(unsigned char *) 0xa9000009 = 0xff; - - /* ----- end of M1543 PCI setup ------ */ - - /* ----- reset on-board ether chip ------ */ - *((volatile u32 *) 0xa8020004) |= 1; /* decode I/O */ - *((volatile u32 *) 0xa8020010) = 0; /* set BAR address */ - - /* send reset command */ - *((volatile u32 *) 0xa6000000) = 1; /* do a soft reset */ - - /* disable ether chip */ - *((volatile u32 *) 0xa8020004) = 0; /* disable any decoding */ - - /* put it into sleep */ - *((volatile u32 *) 0xa8020040) = 0x80000000; - - /* ----- end of reset on-board ether chip ------ */ - - /* ----- set pci window 1 to pci memory space -------- */ - nile4_set_pdar(NILE4_PCIW1, - PHYSADDR(NILE4_PCI_MEM_BASE), 0x08000000, 32, 0, 0); - // nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0); - nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0x08000000); - -} - -#define USE_NILE4_SERIAL 0 - -#if USE_NILE4_SERIAL -#define ns16550_in(reg) nile4_in8((reg)*8) -#define ns16550_out(reg, val) nile4_out8((reg)*8, (val)) -#else -#define NS16550_BASE (NILE4_PCI_IO_BASE+0x03f8) -static inline u8 ns16550_in(u32 reg) -{ - return *(volatile u8 *) (NS16550_BASE + reg); -} - -static inline void ns16550_out(u32 reg, u8 val) -{ - *(volatile u8 *) (NS16550_BASE + reg) = val; -} -#endif - -#define NS16550_RBR 0 -#define NS16550_THR 0 -#define NS16550_DLL 0 -#define NS16550_IER 1 -#define NS16550_DLM 1 -#define NS16550_FCR 2 -#define NS16550_IIR 2 -#define NS16550_LCR 3 -#define NS16550_MCR 4 -#define NS16550_LSR 5 -#define NS16550_MSR 6 -#define NS16550_SCR 7 - -#define NS16550_LSR_DR 0x01 /* Data ready */ -#define NS16550_LSR_OE 0x02 /* Overrun */ -#define NS16550_LSR_PE 0x04 /* Parity error */ -#define NS16550_LSR_FE 0x08 /* Framing error */ -#define NS16550_LSR_BI 0x10 /* Break */ -#define NS16550_LSR_THRE 0x20 /* Xmit holding register empty */ -#define NS16550_LSR_TEMT 0x40 /* Xmitter empty */ -#define NS16550_LSR_ERR 0x80 /* Error */ - - -void _serinit(void) -{ -#if USE_NILE4_SERIAL - ns16550_out(NS16550_LCR, 0x80); - ns16550_out(NS16550_DLM, 0x00); - ns16550_out(NS16550_DLL, 0x36); /* 9600 baud */ - ns16550_out(NS16550_LCR, 0x00); - ns16550_out(NS16550_LCR, 0x03); - ns16550_out(NS16550_FCR, 0x47); -#else - /* done by PMON */ -#endif -} - -void _putc(char c) -{ - while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE)); - ns16550_out(NS16550_THR, c); - if (c == '\n') { - while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE)); - ns16550_out(NS16550_THR, '\r'); - } -} - -void _puts(const char *s) -{ - char c; - - while ((c = *s++)) - _putc(c); -} - -char _getc(void) -{ - while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR)); - - return ns16550_in(NS16550_RBR); -} - -int _testc(void) -{ - return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0; -} - - -/* - * Hexadecimal 7-segment LED - */ -void ddb5476_led_hex(int hex) -{ - outb(hex, 0x80); -} - - -/* - * LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543 - */ -struct pci_dev *pci_pmu = NULL; - -void ddb5476_led_d2(int on) -{ - u8 t; - - if (pci_pmu) { - pci_read_config_byte(pci_pmu, 0x7e, &t); - if (on) - t &= 0x7f; - else - t |= 0x80; - pci_write_config_byte(pci_pmu, 0x7e, t); - } -} - -void ddb5476_led_d3(int on) -{ - u8 t; - - if (pci_pmu) { - pci_read_config_byte(pci_pmu, 0x7e, &t); - if (on) - t &= 0xbf; - else - t |= 0x40; - pci_write_config_byte(pci_pmu, 0x7e, t); - } -} --- linux-2.5.73/arch/mips/ddb5476/time.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,32 +0,0 @@ -/* - * arch/mips/ddb5074/time.c -- Timer routines - * - * Copyright (C) 2000 Geert Uytterhoeven - * Sony Software Development Center Europe (SDCE), Brussels - */ -#include - -#include - -static unsigned char ddb_rtc_read_data(unsigned long addr) -{ - outb_p(addr, RTC_PORT(0)); - return inb_p(RTC_PORT(1)); -} - -static void ddb_rtc_write_data(unsigned char data, unsigned long addr) -{ - outb_p(addr, RTC_PORT(0)); - outb_p(data, RTC_PORT(1)); -} - -static int ddb_rtc_bcd_mode(void) -{ - return 1; -} - -struct rtc_ops ddb_rtc_ops = { - ddb_rtc_read_data, - ddb_rtc_write_data, - ddb_rtc_bcd_mode -}; --- linux-2.5.73/arch/mips/ddb5xxx/common/irq.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/ddb5xxx/common/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -13,12 +13,13 @@ */ #include #include +#include void (*irq_setup)(void); void __init init_IRQ(void) { -#ifdef CONFIG_REMOTE_DEBUG +#ifdef CONFIG_KGDB extern void breakpoint(void); extern void set_debug_traps(void); @@ -26,6 +27,8 @@ void __init init_IRQ(void) set_debug_traps(); breakpoint(); #endif + /* set up default irq controller */ + init_generic_irq(); /* invoke board-specific irq setup */ irq_setup(); --- linux-2.5.73/arch/mips/ddb5xxx/common/irq_cpu.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,115 +0,0 @@ -/*********************************************************************** - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/ddb5xxx/common/irq_cpu.c - * This file define the irq handler for MIPS CPU interrupts. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - *********************************************************************** - */ - -/* - * Almost all MIPS CPUs define 8 interrupt sources. They are typically - * level triggered (i.e., cannot be cleared from CPU; must be cleared from - * device). The first two are software interrupts. The last one is - * usually cpu timer interrupt if coutner register is present. - * - * This file exports one global function: - * mips_cpu_irq_init(u32 irq_base); - */ - -#include -#include -#include - -#include - -/* [jsun] sooner or later we should move this debug stuff to MIPS common */ -#include - -static int mips_cpu_irq_base=-1; - -static void -mips_cpu_irq_enable(unsigned int irq) -{ - MIPS_ASSERT(mips_cpu_irq_base != -1); - MIPS_ASSERT(irq >= mips_cpu_irq_base); - MIPS_ASSERT(irq < mips_cpu_irq_base+8); - - clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8)); - set_cp0_status(1 << (irq - mips_cpu_irq_base + 8)); -} - -static void -mips_cpu_irq_disable(unsigned int irq) -{ - MIPS_ASSERT(mips_cpu_irq_base != -1); - MIPS_ASSERT(irq >= mips_cpu_irq_base); - MIPS_ASSERT(irq < mips_cpu_irq_base+8); - - clear_cp0_status(1 << (irq - mips_cpu_irq_base + 8)); -} - -static unsigned int mips_cpu_irq_startup(unsigned int irq) -{ - mips_cpu_irq_enable(irq); - return 0; -} - -#define mips_cpu_irq_shutdown mips_cpu_irq_disable - -static void -mips_cpu_irq_ack(unsigned int irq) -{ - MIPS_ASSERT(mips_cpu_irq_base != -1); - MIPS_ASSERT(irq >= mips_cpu_irq_base); - MIPS_ASSERT(irq < mips_cpu_irq_base+8); - - /* although we attemp to clear the IP bit in cause reigster, I think - * usually it is cleared by device (irq source) - */ - clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8)); - - /* I am not fully convinced that I should disable irq here */ -} - -static void -mips_cpu_irq_end(unsigned int irq) -{ - MIPS_ASSERT(mips_cpu_irq_base != -1); - MIPS_ASSERT(irq >= mips_cpu_irq_base); - MIPS_ASSERT(irq < mips_cpu_irq_base+8); - /* I am not fully convinced that I should enable irq here */ -} - -static hw_irq_controller mips_cpu_irq_controller = { - "CPU_irq", - mips_cpu_irq_startup, - mips_cpu_irq_shutdown, - mips_cpu_irq_enable, - mips_cpu_irq_disable, - mips_cpu_irq_ack, - mips_cpu_irq_end, - NULL /* no affinity stuff for UP */ -}; - - -void -mips_cpu_irq_init(u32 irq_base) -{ - extern irq_desc_t irq_desc[]; - u32 i; - - for (i= irq_base; i< irq_base+8; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = NULL; - irq_desc[i].depth = 1; - irq_desc[i].handler = &mips_cpu_irq_controller; - } - - mips_cpu_irq_base = irq_base; -} --- linux-2.5.73/arch/mips/ddb5xxx/common/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/ddb5xxx/common/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -2,4 +2,4 @@ # Makefile for the common code of NEC DDB-Vrc5xxx board # -obj-y += irq.o irq_cpu.o nile4.o prom.o pci.o pci_auto.o rtc_ds1386.o +obj-y += irq.o nile4.o prom.o rtc_ds1386.o --- linux-2.5.73/arch/mips/ddb5xxx/common/nile4.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/ddb5xxx/common/nile4.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,4 +1,4 @@ -/*********************************************************************** +/* * * Copyright 2001 MontaVista Software Inc. * Author: jsun@mvista.com or jsun@junsun.net @@ -12,19 +12,14 @@ * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. - * - *********************************************************************** */ - -#include #include #include #include -#include u32 -ddb_calc_pdar(u32 phys, u32 size, int width, +ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible) { u32 maskbits; @@ -73,7 +68,7 @@ ddb_calc_pdar(u32 phys, u32 size, int wi maskbits = 0; break; default: - panic("nile4_set_pdar: unsupported size %p\n", (void *) size); + panic("nile4_set_pdar: unsupported size %p", (void *) size); } switch (width) { case 8: @@ -89,7 +84,7 @@ ddb_calc_pdar(u32 phys, u32 size, int wi widthbits = 3; break; default: - panic("nile4_set_pdar: unsupported width %d\n", width); + panic("nile4_set_pdar: unsupported width %d", width); } return maskbits | (on_memory_bus ? 0x10 : 0) | @@ -128,7 +123,7 @@ void ddb_set_pmr(u32 pmr, u32 type, u32 case DDB_PCICMD_CFG: /* PCI Configuration Space */ break; default: - panic("nile4_set_pmr: invalid type %d\n", type); + panic("nile4_set_pmr: invalid type %d", type); } ddb_out32(pmr, (type << 1) | (addr & 0xffe00000) | options ); ddb_out32(pmr + 4, 0); --- linux-2.5.73/arch/mips/ddb5xxx/common/pci_auto.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,396 +0,0 @@ -/* - * arch/ppc/kernel/pci_auto.c - * - * PCI autoconfiguration library - * - * Author: Matt Porter - * - * Copyright 2000, 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/* - * Modified for MIPS by Jun Sun, jsun@mvista.com - * - * . Simplify the interface between pci_auto and the rest: a single function. - * . Assign resources from low address to upper address. - * . change most int to u32. - */ - -#include -#include -#include -#include - -#include -#include - -#define DEBUG -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -/* These are used for config access before all the PCI probing - has been done. */ -int early_read_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 *val); -int early_read_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 *val); -int early_read_config_dword(struct pci_channel *hose, int bus, int dev_fn, int where, u32 *val); -int early_write_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 val); -int early_write_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 val); -int early_write_config_dword(struct pci_channel *hose, int bus, int dev_fn, int where, u32 val); - -static u32 pciauto_lower_iospc; -static u32 pciauto_upper_iospc; - -static u32 pciauto_lower_memspc; -static u32 pciauto_upper_memspc; - -void __init -pciauto_setup_bars(struct pci_channel *hose, - int current_bus, - int pci_devfn) -{ - u32 bar_response, bar_size, bar_value; - u32 bar, addr_mask, bar_nr = 0; - u32 * upper_limit; - u32 * lower_limit; - int found_mem64 = 0; - - DBG("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n", - current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) ); - - for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar+=4) - { - /* Tickle the BAR and get the response */ - early_write_config_dword(hose, - current_bus, - pci_devfn, - bar, - 0xffffffff); - early_read_config_dword(hose, - current_bus, - pci_devfn, - bar, - &bar_response); - - /* If BAR is not implemented go to the next BAR */ - if (!bar_response) - continue; - - /* Check the BAR type and set our address mask */ - if (bar_response & PCI_BASE_ADDRESS_SPACE) - { - addr_mask = PCI_BASE_ADDRESS_IO_MASK; - upper_limit = &pciauto_upper_iospc; - lower_limit = &pciauto_lower_iospc; - DBG("PCI Autoconfig: BAR %d, I/O, ", bar_nr); - } - else - { - if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == - PCI_BASE_ADDRESS_MEM_TYPE_64) - found_mem64 = 1; - - addr_mask = PCI_BASE_ADDRESS_MEM_MASK; - upper_limit = &pciauto_upper_memspc; - lower_limit = &pciauto_lower_memspc; - DBG("PCI Autoconfig: BAR %d, Mem, ", bar_nr); - } - - /* Calculate requested size */ - bar_size = ~(bar_response & addr_mask) + 1; - - /* Allocate a base address */ - bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size; - MIPS_ASSERT(bar_value + bar_size <= *upper_limit); - - /* Write it out and update our limit */ - early_write_config_dword(hose, - current_bus, - pci_devfn, - bar, - bar_value); - - *lower_limit = bar_value + bar_size; - - /* - * If we are a 64-bit decoder then increment to the - * upper 32 bits of the bar and force it to locate - * in the lower 4GB of memory. - */ - if (found_mem64) - { - bar += 4; - early_write_config_dword(hose, - current_bus, - pci_devfn, - bar, - 0x00000000); - } - - bar_nr++; - - DBG("size=0x%x, address=0x%x\n", - bar_size, bar_value); - } - -} - -void __init -pciauto_prescan_setup_bridge(struct pci_channel *hose, - int current_bus, - int pci_devfn, - int sub_bus) -{ - int cmdstat; - - /* Configure bus number registers */ - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_PRIMARY_BUS, - current_bus); - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_SECONDARY_BUS, - sub_bus + 1); - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_SUBORDINATE_BUS, - 0xff); - - /* Round memory allocator to 1MB boundary */ - pciauto_upper_memspc &= ~(0x100000 - 1); - - /* Round I/O allocator to 4KB boundary */ - pciauto_upper_iospc &= ~(0x1000 - 1); - - /* Set up memory and I/O filter limits, assume 32-bit I/O space */ - early_write_config_word(hose, - current_bus, - pci_devfn, - PCI_MEMORY_LIMIT, - ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16); - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_IO_LIMIT, - ((pciauto_upper_iospc - 1) & 0x0000f000) >> 8); - early_write_config_word(hose, - current_bus, - pci_devfn, - PCI_IO_LIMIT_UPPER16, - ((pciauto_upper_iospc - 1) & 0xffff0000) >> 16); - - /* We don't support prefetchable memory for now, so disable */ - early_write_config_word(hose, - current_bus, - pci_devfn, - PCI_PREF_MEMORY_BASE, - 0x1000); - early_write_config_word(hose, - current_bus, - pci_devfn, - PCI_PREF_MEMORY_LIMIT, - 0x1000); - - /* Enable memory and I/O accesses, enable bus master */ - early_read_config_dword(hose, - current_bus, - pci_devfn, - PCI_COMMAND, - &cmdstat); - early_write_config_dword(hose, - current_bus, - pci_devfn, - PCI_COMMAND, - cmdstat | - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); -} - -void __init -pciauto_postscan_setup_bridge(struct pci_channel *hose, - int current_bus, - int pci_devfn, - int sub_bus) -{ - /* Configure bus number registers */ - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_SUBORDINATE_BUS, - sub_bus); - - /* Round memory allocator to 1MB boundary */ - pciauto_upper_memspc &= ~(0x100000 - 1); - early_write_config_word(hose, - current_bus, - pci_devfn, - PCI_MEMORY_BASE, - pciauto_upper_memspc >> 16); - - /* Round I/O allocator to 4KB boundary */ - pciauto_upper_iospc &= ~(0x1000 - 1); - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_IO_BASE, - (pciauto_upper_iospc & 0x0000f000) >> 8); - early_write_config_word(hose, - current_bus, - pci_devfn, - PCI_IO_BASE_UPPER16, - pciauto_upper_iospc >> 16); -} - -#define PCIAUTO_IDE_MODE_MASK 0x05 - -int __init -pciauto_bus_scan(struct pci_channel *hose, int current_bus) -{ - int sub_bus; - u32 pci_devfn, pci_class, cmdstat, found_multi=0; - unsigned short vid; - unsigned char header_type; - - sub_bus = current_bus; - - for (pci_devfn=0; pci_devfn<0xff; pci_devfn++) { - - if (PCI_FUNC(pci_devfn) && !found_multi) - continue; - - early_read_config_byte(hose, - current_bus, - pci_devfn, - PCI_HEADER_TYPE, - &header_type); - - if (!PCI_FUNC(pci_devfn)) - found_multi = header_type & 0x80; - - early_read_config_word(hose, - current_bus, - pci_devfn, - PCI_VENDOR_ID, - &vid); - - if (vid == 0xffff) continue; - - early_read_config_dword(hose, - current_bus, - pci_devfn, - PCI_CLASS_REVISION, &pci_class); - if ( (pci_class >> 16) == PCI_CLASS_BRIDGE_PCI ) { - DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_SLOT(pci_devfn)); - pciauto_prescan_setup_bridge(hose, - current_bus, - pci_devfn, - sub_bus); - sub_bus = pciauto_bus_scan(hose, sub_bus+1); - pciauto_postscan_setup_bridge(hose, - current_bus, - pci_devfn, - sub_bus); - - } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) { - - unsigned char prg_iface; - - early_read_config_byte(hose, - current_bus, - pci_devfn, - PCI_CLASS_PROG, - &prg_iface); - if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) { - DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n"); - continue; - } - } - - /* - * Found a peripheral, enable some standard - * settings - */ - early_read_config_dword(hose, - current_bus, - pci_devfn, - PCI_COMMAND, - &cmdstat); - early_write_config_dword(hose, - current_bus, - pci_devfn, - PCI_COMMAND, - cmdstat | - PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); - early_write_config_byte(hose, - current_bus, - pci_devfn, - PCI_LATENCY_TIMER, - 0x80); - - /* Allocate PCI I/O and/or memory space */ - pciauto_setup_bars(hose, - current_bus, - pci_devfn); - } - return sub_bus; -} - -int __init -pciauto_assign_resources(int busno, struct pci_channel *hose) -{ - /* setup resource limits */ - pciauto_lower_iospc = hose->io_resource->start; - pciauto_upper_iospc = hose->io_resource->end + 1; - pciauto_lower_memspc = hose->mem_resource->start; - pciauto_upper_memspc = hose->mem_resource->end + 1; - - return pciauto_bus_scan(hose, busno); -} - - -/* - * These functions are used early on before PCI scanning is done - * and all of the pci_dev and pci_bus structures have been created. - */ -static struct pci_dev * -fake_pci_dev(struct pci_channel *hose, int busnr, int devfn) -{ - static struct pci_dev dev; - static struct pci_bus bus; - - dev.bus = &bus; - dev.sysdata = hose; - dev.devfn = devfn; - bus.number = busnr; - bus.ops = hose->pci_ops; - return &dev; -} - -#define EARLY_PCI_OP(rw, size, type) \ -int early_##rw##_config_##size(struct pci_channel *hose, int bus, \ - int devfn, int offset, type value) \ -{ \ - return pci_##rw##_config_##size(fake_pci_dev(hose, bus, devfn), \ - offset, value); \ -} - -EARLY_PCI_OP(read, byte, u8 *) -EARLY_PCI_OP(read, word, u16 *) -EARLY_PCI_OP(read, dword, u32 *) -EARLY_PCI_OP(write, byte, u8) -EARLY_PCI_OP(write, word, u16) -EARLY_PCI_OP(write, dword, u32) --- linux-2.5.73/arch/mips/ddb5xxx/common/pci.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,172 +0,0 @@ -/*********************************************************************** - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/ddb5xxx/common/pci.c - * Common PCI routines for DDB5xxx - as a matter of fact, meant for all - * MIPS machines. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - *********************************************************************** - */ - -/* - * This file contains common PCI routines meant to be shared for - * all MIPS machines. - * - * Strategies: - * - * . We rely on pci_auto.c file to assign PCI resources (MEM and IO) - * TODO: this should be optional for some machines where they do have - * a real "pcibios" that does resource assignment. - * - * . We then use pci_scan_bus() to "discover" all the resources for - * later use by Linux. - * - * . We finally reply on a board supplied function, pcibios_fixup_irq(), to - * to assign the interrupts. We may use setup-irq.c under drivers/pci - * later. - * - * . Specifically, we will *NOT* use pci_assign_unassigned_resources(), - * because we assume all PCI devices should have the resources correctly - * assigned and recorded. - * - * Limitations: - * - * . We "collapse" all IO and MEM spaces in sub-buses under a top-level bus - * into a contiguous range. - * - * . In the case of Memory space, the rnage is 1:1 mapping with CPU physical - * address space. - * - * . In the case of IO space, it starts from 0, and the beginning address - * is mapped to KSEG0ADDR(mips_io_port) in the CPU physical address. - * - * . These are the current MIPS limitations (by ioremap, etc). In the - * future, we may remove them. - * - * Credits: - * Most of the code are derived from the pci routines from PPC and Alpha, - * which were mostly writtne by - * Cort Dougan, cort@fsmlabs.com - * Matt Porter, mporter@mvista.com - * Dave Rusling david.rusling@reo.mts.dec.com - * David Mosberger davidm@cs.arizona.edu - */ - -#include -#include -#include -#include - -#include -#include - - -struct pci_fixup pcibios_fixups[] = { {0} }; - - -extern int pciauto_assign_resources(int busno, struct pci_channel * hose); -void __init pcibios_init(void) -{ - struct pci_channel *p; - struct pci_bus *bus; - int busno; - - /* assign resources */ - busno=0; - for (p= mips_pci_channels; p->pci_ops != NULL; p++) { - busno = pciauto_assign_resources(busno, p) + 1; - } - - /* scan the buses */ - busno = 0; - for (p= mips_pci_channels; p->pci_ops != NULL; p++) { - bus = pci_scan_bus(busno, p->pci_ops, p); - busno = bus->subordinate+1; - } - - /* fixup irqs (board specific routines) */ - pcibios_fixup_irqs(); - - /* - * should we do a fixup of ioport_resource and iomem_resource - * based on mips_pci_channels? - * Let us wait and see if this is a common need and whether there - * are exceptions. Until then, each board should adjust them - * perhaps in their setup() function. - */ -} - -int pcibios_enable_device(struct pci_dev *dev) -{ - /* pciauto_assign_resources() will enable all devices found */ - return 0; -} - -unsigned long __init -pci_bridge_check_io(struct pci_dev *bridge) -{ - u16 io; - - pci_read_config_word(bridge, PCI_IO_BASE, &io); - if (!io) { - pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); - pci_read_config_word(bridge, PCI_IO_BASE, &io); - pci_write_config_word(bridge, PCI_IO_BASE, 0x0); - } - if (io) - return IORESOURCE_IO; - printk(KERN_WARNING "PCI: bridge %s does not support I/O forwarding!\n", - bridge->name); - return 0; -} - -void __init pcibios_fixup_bus(struct pci_bus *bus) -{ - /* Propogate hose info into the subordinate devices. */ - - struct pci_channel *hose = bus->sysdata; - struct pci_dev *dev = bus->self; - - if (!dev) { - /* Root bus */ - bus->resource[0] = hose->io_resource; - bus->resource[1] = hose->mem_resource; - } else { - /* This is a bridge. Do not care how it's initialized, - just link its resources to the bus ones */ - int i; - - for(i=0; i<3; i++) { - bus->resource[i] = - &dev->resource[PCI_BRIDGE_RESOURCES+i]; - bus->resource[i]->name = bus->name; - } - bus->resource[0]->flags |= pci_bridge_check_io(dev); - bus->resource[1]->flags |= IORESOURCE_MEM; - /* For now, propagate hose limits to the bus; - we'll adjust them later. */ - bus->resource[0]->end = hose->io_resource->end; - bus->resource[1]->end = hose->mem_resource->end; - /* Turn off downstream PF memory address range by default */ - bus->resource[2]->start = 1024*1024; - bus->resource[2]->end = bus->resource[2]->start - 1; - } -} - -char *pcibios_setup(char *str) -{ - return str; -} - -void -pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) -{ - /* this should not be called */ - MIPS_ASSERT(1 == 0); -} --- linux-2.5.73/arch/mips/ddb5xxx/common/prom.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/ddb5xxx/common/prom.c 2003-06-27 15:56:23.000000000 -0700 @@ -22,8 +22,21 @@ #include #include #include +#include -char arcs_cmdline[COMMAND_LINE_SIZE]; +char arcs_cmdline[CL_SIZE]; + +const char *get_system_type(void) +{ + switch (mips_machtype) { + case MACH_NEC_DDB5074: return "NEC DDB Vrc-5074"; + case MACH_NEC_DDB5476: return "NEC DDB Vrc-5476"; + case MACH_NEC_DDB5477: return "NEC DDB Vrc-5477"; + case MACH_NEC_ROCKHOPPER: return "NEC Rockhopper"; + case MACH_NEC_ROCKHOPPERII: return "NEC RockhopperII"; + default: return "Unknown NEC board"; + } +} /* [jsun@junsun.net] PMON passes arguments in C main() style */ void __init prom_init(int argc, const char **arg) @@ -40,19 +53,91 @@ void __init prom_init(int argc, const ch strcat(arcs_cmdline, " "); } + /* by default all these boards use dhcp/nfs root fs */ + strcat(arcs_cmdline, "ip=bootp"); + mips_machgroup = MACH_GROUP_NEC_DDB; #if defined(CONFIG_DDB5074) mips_machtype = MACH_NEC_DDB5074; + add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM); #elif defined(CONFIG_DDB5476) mips_machtype = MACH_NEC_DDB5476; + add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM); #elif defined(CONFIG_DDB5477) - mips_machtype = MACH_NEC_DDB5477; + ddb5477_runtime_detection(); + add_memory_region(0, board_ram_size, BOOT_MEM_RAM); #endif - - add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM); } void __init prom_free_prom_memory(void) { } + +#if defined(CONFIG_DDB5477) + +#define DEFAULT_LCS1_BASE 0x19000000 +#define TESTVAL1 'K' +#define TESTVAL2 'S' + +int board_ram_size; +void ddb5477_runtime_detection(void) +{ + volatile char *test_offset; + char saved_test_byte; + + /* Determine if this is a DDB5477 board, or a BSB-VR0300 + base board. We can tell by checking for the location of + the NVRAM. It lives at the beginning of LCS1 on the DDB5477, + and the beginning of LCS1 on the BSB-VR0300 is flash memory. + The first 2K of the NVRAM are reserved, so don't we'll poke + around just after that. + */ + + /* We can only use the PCI bus to distinquish between + the Rockhopper and RockhopperII backplanes and this must + wait until ddb5477_board_init() in setup.c after the 5477 + is initialized. So, until then handle + both Rockhopper and RockhopperII backplanes as Rockhopper 1 + */ + + test_offset = (char *)KSEG1ADDR(DEFAULT_LCS1_BASE + 0x800); + saved_test_byte = *test_offset; + + *test_offset = TESTVAL1; + if (*test_offset != TESTVAL1) { + /* We couldn't set our test value, so it must not be NVRAM, + so it's a BSB_VR0300 */ + mips_machtype = MACH_NEC_ROCKHOPPER; + } else { + /* We may have gotten lucky, and the TESTVAL1 was already + stored at the test location, so we must check a second + test value */ + *test_offset = TESTVAL2; + if (*test_offset != TESTVAL2) { + /* OK, we couldn't set this value either, so it must + definately be a BSB_VR0300 */ + mips_machtype = MACH_NEC_ROCKHOPPER; + } else { + /* We could change the value twice, so it must be + NVRAM, so it's a DDB_VRC5477 */ + mips_machtype = MACH_NEC_DDB5477; + } + } + /* Restore the original byte */ + *test_offset = saved_test_byte; + + /* before we know a better way, we will trust PMON for getting + * RAM size + */ + board_ram_size = 1 << (36 - (ddb_in32(DDB_SDRAM0) & 0xf)); + + db_run(printk("DDB run-time detection : %s, %d MB RAM\n", + mips_machtype == MACH_NEC_DDB5477 ? + "DDB5477" : "Rockhopper", + board_ram_size >> 20)); + + /* we can't handle ram size > 128 MB */ + db_assert(board_ram_size <= (128 << 20)); +} +#endif --- linux-2.5.73/arch/mips/ddb5xxx/common/rtc_ds1386.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/ddb5xxx/common/rtc_ds1386.c 2003-06-27 15:56:23.000000000 -0700 @@ -25,7 +25,8 @@ #include #include -#include +#include +#include #define EPOCH 2000 @@ -36,7 +37,7 @@ static unsigned long rtc_base; static unsigned long rtc_ds1386_get_time(void) -{ +{ u8 byte; u8 temp; unsigned int year, month, day, hour, minute, second; @@ -73,7 +74,7 @@ rtc_ds1386_get_time(void) return mktime(year, month, day, hour, minute, second); } -static int +static int rtc_ds1386_set_time(unsigned long t) { struct rtc_time tm; @@ -89,6 +90,7 @@ rtc_ds1386_set_time(unsigned long t) /* convert */ to_tm(t, &tm); + /* check each field one by one */ year = BIN2BCD(tm.tm_year - EPOCH); if (year != READ_RTC(0xA)) { @@ -96,7 +98,7 @@ rtc_ds1386_set_time(unsigned long t) } temp = READ_RTC(0x9); - month = BIN2BCD(tm.tm_mon); + month = BIN2BCD(tm.tm_mon+1); /* tm_mon starts from 0 to 11 */ if (month != (temp & 0x1f)) { WRITE_RTC( 0x9, (month & 0x1f) | (temp & ~0x1f) ); @@ -131,7 +133,7 @@ rtc_ds1386_set_time(unsigned long t) if (second != READ_RTC(0x1)) { WRITE_RTC(0x1, second); } - + return 0; } @@ -139,10 +141,10 @@ void rtc_ds1386_init(unsigned long base) { unsigned char byte; - + /* remember the base */ rtc_base = base; - MIPS_ASSERT((rtc_base & 0xe0000000) == KSEG1); + db_assert((rtc_base & 0xe0000000) == KSEG1); /* turn on RTC if it is not on */ byte = READ_RTC(0x9); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5074/int-handler.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,120 @@ +/* + * arch/mips/ddb5074/int-handler.S -- NEC DDB Vrc-5074 interrupt handler + * + * Based on arch/mips/sgi/kernel/indyIRQ.S + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * + * Copyright (C) 2000 Geert Uytterhoeven + * Sony Software Development Center Europe (SDCE), Brussels + */ +#include +#include +#include +#include + +/* A lot of complication here is taken away because: + * + * 1) We handle one interrupt and return, sitting in a loop and moving across + * all the pending IRQ bits in the cause register is _NOT_ the answer, the + * common case is one pending IRQ so optimize in that direction. + * + * 2) We need not check against bits in the status register IRQ mask, that + * would make this routine slow as hell. + * + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in + * between like BSD spl() brain-damage. + * + * Furthermore, the IRQs on the INDY look basically (barring software IRQs + * which we don't use at all) like: + * + * MIPS IRQ Source + * -------- ------ + * 0 Software (ignored) + * 1 Software (ignored) + * 2 Local IRQ level zero + * 3 Local IRQ level one + * 4 8254 Timer zero + * 5 8254 Timer one + * 6 Bus Error + * 7 R4k timer (what we use) + * + * We handle the IRQ according to _our_ priority which is: + * + * Highest ---- R4k Timer + * Local IRQ zero + * Local IRQ one + * Bus Error + * 8254 Timer zero + * Lowest ---- 8254 Timer one + * + * then we just return, if multiple IRQs are pending then we will just take + * another exception, big deal. + */ + + .text + .set noreorder + .set noat + .align 5 + NESTED(ddbIRQ, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + mfc0 s0, CP0_CAUSE # get irq mask + +#if 1 + mfc0 t2,CP0_STATUS # get enabled interrupts + and s0,t2 # isolate allowed ones +#endif + /* First we check for r4k counter/timer IRQ. */ + andi a0, s0, CAUSEF_IP2 # delay slot, check local level zero + beq a0, zero, 1f + andi a0, s0, CAUSEF_IP3 # delay slot, check local level one + + /* Wheee, local level zero interrupt. */ + jal ddb_local0_irqdispatch + move a0, sp # delay slot + + j ret_from_irq + nop # delay slot + +1: + beq a0, zero, 1f + andi a0, s0, CAUSEF_IP6 # delay slot, check bus error + + /* Wheee, local level one interrupt. */ + move a0, sp + jal ddb_local1_irqdispatch + nop + + j ret_from_irq + nop + +1: + beq a0, zero, 1f + nop + + /* Wheee, an asynchronous bus error... */ + move a0, sp + jal ddb_buserror_irq + nop + + j ret_from_irq + nop + +1: + /* Here by mistake? This is possible, what can happen + * is that by the time we take the exception the IRQ + * pin goes low, so just leave if this is the case. + */ + andi a0, s0, (CAUSEF_IP4 | CAUSEF_IP5) + beq a0, zero, 1f + + /* Must be one of the 8254 timers... */ + move a0, sp + jal ddb_8254timer_irq + nop +1: + j ret_from_irq + nop + END(ddbIRQ) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5074/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,168 @@ +/* + * arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines + * + * Copyright (C) 2000 Geert Uytterhoeven + * Sony Software Development Center Europe (SDCE), Brussels + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + + +extern asmlinkage void ddbIRQ(void); + +static struct irqaction irq_cascade = { no_action, 0, 0, "cascade", NULL, NULL }; + +#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */ +#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */ +#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */ + +#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */ +#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */ +#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */ + +#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */ +#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */ + +#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */ +#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */ + +#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */ +#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */ + + +static void m1543_irq_setup(void) +{ + /* + * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all + * the possible IO sources in the M1543 are in use by us. We will + * use the following mapping: + * + * IRQ1 - keyboard (default set by M1543) + * IRQ3 - reserved for UART B (default set by M1543) (note that + * the schematics for the DDB Vrc-5074 board seem to + * indicate that IRQ3 is connected to the DS1386 + * watchdog timer interrupt output so we might have + * a conflict) + * IRQ4 - reserved for UART A (default set by M1543) + * IRQ5 - parallel (default set by M1543) + * IRQ8 - DS1386 time of day (RTC) interrupt + * IRQ12 - mouse + */ + + /* + * Assing mouse interrupt to IRQ12 + */ + + /* Enter configuration mode */ + outb(0x51, M1543_PNP_CONFIG); + outb(0x23, M1543_PNP_CONFIG); + + /* Select logical device 7 (Keyboard) */ + outb(0x07, M1543_PNP_INDEX); + outb(0x07, M1543_PNP_DATA); + + /* Select IRQ12 */ + outb(0x72, M1543_PNP_INDEX); + outb(0x0c, M1543_PNP_DATA); + + outb(0x30, M1543_PNP_INDEX); + printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA)); + + outb(0x70, M1543_PNP_INDEX); + printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA)); + + /* Leave configration mode */ + outb(0xbb, M1543_PNP_CONFIG); + + +} + +void ddb_local0_irqdispatch(struct pt_regs *regs) +{ + u32 mask; + int nile4_irq; + + mask = nile4_get_irq_stat(0); + + /* Handle the timer interrupt first */ +#if 0 + if (mask & (1 << NILE4_INT_GPT)) { + do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs); + mask &= ~(1 << NILE4_INT_GPT); + } +#endif + for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) + if (mask & 1) { + if (nile4_irq == NILE4_INT_INTE) { + int i8259_irq; + + nile4_clear_irq(NILE4_INT_INTE); + i8259_irq = nile4_i8259_iack(); + do_IRQ(i8259_irq, regs); + } else + do_IRQ(nile4_to_irq(nile4_irq), regs); + + } +} + +void ddb_local1_irqdispatch(void) +{ + printk("ddb_local1_irqdispatch called\n"); +} + +void ddb_buserror_irq(void) +{ + printk("ddb_buserror_irq called\n"); +} + +void ddb_8254timer_irq(void) +{ + printk("ddb_8254timer_irq called\n"); +} + +void __init ddb_irq_setup(void) +{ +#ifdef CONFIG_KGDB + if (remote_debug) + set_debug_traps(); + breakpoint(); /* you may move this line to whereever you want :-) */ +#endif + + /* setup cascade interrupts */ + setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade); + setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade); + + set_except_vector(0, ddbIRQ); + + nile4_irq_setup(NILE4_IRQ_BASE); + m1543_irq_setup(); + init_i8259_irqs(); + + + printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE); + + mips_cpu_irq_init(CPU_IRQ_BASE); + + printk("enabling 8259 cascade\n"); + + ddb5074_led_hex(0); + + /* Enable the interrupt cascade */ + nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE); + + +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5074/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,8 @@ +# +# Makefile for the NEC DDB Vrc-5074 specific kernel interface routines +# under Linux. +# + +obj-y += setup.o irq.o int-handler.o nile4_pic.o time.o + +EXTRA_AFLAGS := $(CFLAGS) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5074/nile4_pic.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,288 @@ +/* + * arch/mips/ddb5476/nile4.c -- + * low-level PIC code for NEC Vrc-5476 (Nile 4) + * + * Copyright (C) 2000 Geert Uytterhoeven + * Sony Software Development Center Europe (SDCE), Brussels + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + */ +#include +#include +#include +#include + +#include + +#include + +static int irq_base; + +/* + * Interrupt Programming + */ +void nile4_map_irq(int nile4_irq, int cpu_irq) +{ + u32 offset, t; + + offset = DDB_INTCTRL; + if (nile4_irq >= 8) { + offset += 4; + nile4_irq -= 8; + } + t = ddb_in32(offset); + t &= ~(7 << (nile4_irq * 4)); + t |= cpu_irq << (nile4_irq * 4); + ddb_out32(offset, t); +} + +void nile4_map_irq_all(int cpu_irq) +{ + u32 all, t; + + all = cpu_irq; + all |= all << 4; + all |= all << 8; + all |= all << 16; + t = ddb_in32(DDB_INTCTRL); + t &= 0x88888888; + t |= all; + ddb_out32(DDB_INTCTRL, t); + t = ddb_in32(DDB_INTCTRL + 4); + t &= 0x88888888; + t |= all; + ddb_out32(DDB_INTCTRL + 4, t); +} + +void nile4_enable_irq(unsigned int nile4_irq) +{ + u32 offset, t; + + nile4_irq-=irq_base; + + ddb5074_led_hex(8); + + offset = DDB_INTCTRL; + if (nile4_irq >= 8) { + offset += 4; + nile4_irq -= 8; + } + ddb5074_led_hex(9); + t = ddb_in32(offset); + ddb5074_led_hex(0xa); + t |= 8 << (nile4_irq * 4); + ddb_out32(offset, t); + ddb5074_led_hex(0xb); +} + +void nile4_disable_irq(unsigned int nile4_irq) +{ + u32 offset, t; + + nile4_irq-=irq_base; + + offset = DDB_INTCTRL; + if (nile4_irq >= 8) { + offset += 4; + nile4_irq -= 8; + } + t = ddb_in32(offset); + t &= ~(8 << (nile4_irq * 4)); + ddb_out32(offset, t); +} + +void nile4_disable_irq_all(void) +{ + ddb_out32(DDB_INTCTRL, 0); + ddb_out32(DDB_INTCTRL + 4, 0); +} + +u16 nile4_get_irq_stat(int cpu_irq) +{ + return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2); +} + +void nile4_enable_irq_output(int cpu_irq) +{ + u32 t; + + t = ddb_in32(DDB_INTSTAT1 + 4); + t |= 1 << (16 + cpu_irq); + ddb_out32(DDB_INTSTAT1, t); +} + +void nile4_disable_irq_output(int cpu_irq) +{ + u32 t; + + t = ddb_in32(DDB_INTSTAT1 + 4); + t &= ~(1 << (16 + cpu_irq)); + ddb_out32(DDB_INTSTAT1, t); +} + +void nile4_set_pci_irq_polarity(int pci_irq, int high) +{ + u32 t; + + t = ddb_in32(DDB_INTPPES); + if (high) + t &= ~(1 << (pci_irq * 2)); + else + t |= 1 << (pci_irq * 2); + ddb_out32(DDB_INTPPES, t); +} + +void nile4_set_pci_irq_level_or_edge(int pci_irq, int level) +{ + u32 t; + + t = ddb_in32(DDB_INTPPES); + if (level) + t |= 2 << (pci_irq * 2); + else + t &= ~(2 << (pci_irq * 2)); + ddb_out32(DDB_INTPPES, t); +} + +void nile4_clear_irq(int nile4_irq) +{ + nile4_irq-=irq_base; + ddb_out32(DDB_INTCLR, 1 << nile4_irq); +} + +void nile4_clear_irq_mask(u32 mask) +{ + ddb_out32(DDB_INTCLR, mask); +} + +u8 nile4_i8259_iack(void) +{ + u8 irq; + u32 reg; + + /* Set window 0 for interrupt acknowledge */ + reg = ddb_in32(DDB_PCIINIT0); + + ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32); + irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE); + /* restore window 0 for PCI I/O space */ + // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32); + ddb_out32(DDB_PCIINIT0, reg); + + /* i8269.c set the base vector to be 0x0 */ + return irq ; +} + +static unsigned int nile4_irq_startup(unsigned int irq) { + + nile4_enable_irq(irq); + return 0; + +} + +static void nile4_ack_irq(unsigned int irq) { + + ddb5074_led_hex(4); + + nile4_clear_irq(irq); + ddb5074_led_hex(2); + nile4_disable_irq(irq); + + ddb5074_led_hex(0); +} + +static void nile4_irq_end(unsigned int irq) { + + ddb5074_led_hex(3); + if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + ddb5074_led_hex(5); + nile4_enable_irq(irq); + ddb5074_led_hex(7); + } + + ddb5074_led_hex(1); +} + +#define nile4_irq_shutdown nile4_disable_irq + +static hw_irq_controller nile4_irq_controller = { + "nile4", + nile4_irq_startup, + nile4_irq_shutdown, + nile4_enable_irq, + nile4_disable_irq, + nile4_ack_irq, + nile4_irq_end, + NULL +}; + +void nile4_irq_setup(u32 base) { + + int i; + extern irq_desc_t irq_desc[]; + + irq_base=base; + + /* Map all interrupts to CPU int #0 */ + nile4_map_irq_all(0); + + /* PCI INTA#-E# must be level triggered */ + nile4_set_pci_irq_level_or_edge(0, 1); + nile4_set_pci_irq_level_or_edge(1, 1); + nile4_set_pci_irq_level_or_edge(2, 1); + nile4_set_pci_irq_level_or_edge(3, 1); + nile4_set_pci_irq_level_or_edge(4, 1); + + /* PCI INTA#-D# must be active low, INTE# must be active high */ + nile4_set_pci_irq_polarity(0, 0); + nile4_set_pci_irq_polarity(1, 0); + nile4_set_pci_irq_polarity(2, 0); + nile4_set_pci_irq_polarity(3, 0); + nile4_set_pci_irq_polarity(4, 1); + + + for (i = 0; i < 16; i++) { + nile4_clear_irq(i); + nile4_disable_irq(i); + } + + /* Enable CPU int #0 */ + nile4_enable_irq_output(0); + + for (i= base; i< base + NUM_NILE4_INTERRUPTS; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].handler = &nile4_irq_controller; + } + +} + +#if defined(CONFIG_RUNTIME_DEBUG) +void nile4_dump_irq_status(void) +{ + printk(KERN_DEBUG " + CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4), + (void *) ddb_in32(DDB_CPUSTAT)); + printk(KERN_DEBUG " + INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4), + (void *) ddb_in32(DDB_INTCTRL)); + printk(KERN_DEBUG + "INTSTAT0 = %p:%p\n", + (void *) ddb_in32(DDB_INTSTAT0 + 4), + (void *) ddb_in32(DDB_INTSTAT0)); + printk(KERN_DEBUG + "INTSTAT1 = %p:%p\n", + (void *) ddb_in32(DDB_INTSTAT1 + 4), + (void *) ddb_in32(DDB_INTSTAT1)); + printk(KERN_DEBUG + "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4), + (void *) ddb_in32(DDB_INTCLR)); + printk(KERN_DEBUG + "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4), + (void *) ddb_in32(DDB_INTPPES)); +} + +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5074/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,265 @@ +/* + * arch/mips/ddb5074/setup.c -- NEC DDB Vrc-5074 setup routines + * + * Copyright (C) 2000 Geert Uytterhoeven + * Sony Software Development Center Europe (SDCE), Brussels + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#ifdef CONFIG_KGDB +extern void rs_kgdb_hook(int); +extern void breakpoint(void); +#endif + +#if defined(CONFIG_SERIAL_CONSOLE) +extern void console_setup(char *); +#endif + +extern struct ide_ops std_ide_ops; +extern struct kbd_ops std_kbd_ops; +extern struct rtc_ops ddb_rtc_ops; + +static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000; + +static void ddb_machine_restart(char *command) +{ + u32 t; + + /* PCI cold reset */ + t = nile4_in32(NILE4_PCICTRL + 4); + t |= 0x40000000; + nile4_out32(NILE4_PCICTRL + 4, t); + /* CPU cold reset */ + t = nile4_in32(NILE4_CPUSTAT); + t |= 1; + nile4_out32(NILE4_CPUSTAT, t); + /* Call the PROM */ + back_to_prom(); +} + +static void ddb_machine_halt(void) +{ + printk("DDB Vrc-5074 halted.\n"); + do { + } while (1); +} + +static void ddb_machine_power_off(void) +{ + printk("DDB Vrc-5074 halted. Please turn off the power.\n"); + do { + } while (1); +} + +extern void ddb_irq_setup(void); +extern void rtc_ds1386_init(unsigned long base); + +extern void (*board_timer_setup) (struct irqaction * irq); + +static void __init ddb_timer_init(struct irqaction *irq) +{ + /* set the clock to 1 Hz */ + nile4_out32(NILE4_T2CTRL, 1000000); + /* enable the General-Purpose Timer */ + nile4_out32(NILE4_T2CTRL + 4, 0x00000001); + /* reset timer */ + nile4_out32(NILE4_T2CNTR, 0); + /* enable interrupt */ + setup_irq(nile4_to_irq(NILE4_INT_GPT), irq); + nile4_enable_irq(nile4_to_irq(NILE4_INT_GPT)); + change_c0_status(ST0_IM, + IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); + +} + +static void __init ddb_time_init(void) +{ + /* we have ds1396 RTC chip */ + rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE)); +} + + + +void __init ddb_setup(void) +{ + extern int panic_timeout; + + irq_setup = ddb_irq_setup; + set_io_port_base(NILE4_PCI_IO_BASE); + isa_slot_offset = NILE4_PCI_MEM_BASE; + board_timer_setup = ddb_timer_init; + board_time_init = ddb_time_init; + + + _machine_restart = ddb_machine_restart; + _machine_halt = ddb_machine_halt; + _machine_power_off = ddb_machine_power_off; + +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &std_ide_ops; +#endif + + rtc_ops = &ddb_rtc_ops; + + ddb_out32(DDB_BAR0, 0); + + ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, 0x10); + ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE , 0x10); + +#ifdef CONFIG_FB + conswitchp = &dummy_con; +#endif + + /* Reboot on panic */ + panic_timeout = 180; +} + + +#define USE_NILE4_SERIAL 0 + +#if USE_NILE4_SERIAL +#define ns16550_in(reg) nile4_in8((reg)*8) +#define ns16550_out(reg, val) nile4_out8((reg)*8, (val)) +#else +#define NS16550_BASE (NILE4_PCI_IO_BASE+0x03f8) +static inline u8 ns16550_in(u32 reg) +{ + return *(volatile u8 *) (NS16550_BASE + reg); +} + +static inline void ns16550_out(u32 reg, u8 val) +{ + *(volatile u8 *) (NS16550_BASE + reg) = val; +} +#endif + +#define NS16550_RBR 0 +#define NS16550_THR 0 +#define NS16550_DLL 0 +#define NS16550_IER 1 +#define NS16550_DLM 1 +#define NS16550_FCR 2 +#define NS16550_IIR 2 +#define NS16550_LCR 3 +#define NS16550_MCR 4 +#define NS16550_LSR 5 +#define NS16550_MSR 6 +#define NS16550_SCR 7 + +#define NS16550_LSR_DR 0x01 /* Data ready */ +#define NS16550_LSR_OE 0x02 /* Overrun */ +#define NS16550_LSR_PE 0x04 /* Parity error */ +#define NS16550_LSR_FE 0x08 /* Framing error */ +#define NS16550_LSR_BI 0x10 /* Break */ +#define NS16550_LSR_THRE 0x20 /* Xmit holding register empty */ +#define NS16550_LSR_TEMT 0x40 /* Xmitter empty */ +#define NS16550_LSR_ERR 0x80 /* Error */ + + +void _serinit(void) +{ +#if USE_NILE4_SERIAL + ns16550_out(NS16550_LCR, 0x80); + ns16550_out(NS16550_DLM, 0x00); + ns16550_out(NS16550_DLL, 0x36); /* 9600 baud */ + ns16550_out(NS16550_LCR, 0x00); + ns16550_out(NS16550_LCR, 0x03); + ns16550_out(NS16550_FCR, 0x47); +#else + /* done by PMON */ +#endif +} + +void _putc(char c) +{ + while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE)); + ns16550_out(NS16550_THR, c); + if (c == '\n') { + while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE)); + ns16550_out(NS16550_THR, '\r'); + } +} + +void _puts(const char *s) +{ + char c; + while ((c = *s++)) + _putc(c); +} + +char _getc(void) +{ + while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR)); + return ns16550_in(NS16550_RBR); +} + +int _testc(void) +{ + return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0; +} + + +/* + * Hexadecimal 7-segment LED + */ +void ddb5074_led_hex(int hex) +{ + outb(hex, 0x80); +} + + +/* + * LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543 + */ +struct pci_dev *pci_pmu = NULL; + +void ddb5074_led_d2(int on) +{ + u8 t; + + if (pci_pmu) { + pci_read_config_byte(pci_pmu, 0x7e, &t); + if (on) + t &= 0x7f; + else + t |= 0x80; + pci_write_config_byte(pci_pmu, 0x7e, t); + } +} + +void ddb5074_led_d3(int on) +{ + u8 t; + + if (pci_pmu) { + pci_read_config_byte(pci_pmu, 0x7e, &t); + if (on) + t &= 0xbf; + else + t |= 0x40; + pci_write_config_byte(pci_pmu, 0x7e, t); + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5074/time.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,33 @@ +/* + * arch/mips/ddb5074/time.c -- Timer routines + * + * Copyright (C) 2000 Geert Uytterhoeven + * Sony Software Development Center Europe (SDCE), Brussels + * + */ +#include +#include +#include +#include + + +static unsigned char ddb_rtc_read_data(unsigned long addr) +{ + return *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr); +} + +static void ddb_rtc_write_data(unsigned char data, unsigned long addr) +{ + *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr)=data; +} + +static int ddb_rtc_bcd_mode(void) +{ + return 1; +} + +struct rtc_ops ddb_rtc_ops = { + ddb_rtc_read_data, + ddb_rtc_write_data, + ddb_rtc_bcd_mode +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5476/dbg_io.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,136 @@ +/* + * kgdb io functions for DDB5476. We use the second serial port. + * + * Copyright (C) 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +/* ======================= CONFIG ======================== */ + +/* [jsun] we use the second serial port for kdb */ +#define BASE 0xa60002f8 +#define MAX_BAUD 115200 + +/* distance in bytes between two serial registers */ +#define REG_OFFSET 1 + +/* + * 0 - kgdb does serial init + * 1 - kgdb skip serial init + */ +static int remoteDebugInitialized = 0; + +/* + * the default baud rate *if* kgdb does serial init + */ +#define BAUD_DEFAULT UART16550_BAUD_38400 + +/* ======================= END OF CONFIG ======================== */ + +typedef unsigned char uint8; +typedef unsigned int uint32; + +#define UART16550_BAUD_2400 2400 +#define UART16550_BAUD_4800 4800 +#define UART16550_BAUD_9600 9600 +#define UART16550_BAUD_19200 19200 +#define UART16550_BAUD_38400 38400 +#define UART16550_BAUD_57600 57600 +#define UART16550_BAUD_115200 115200 + +#define UART16550_PARITY_NONE 0 +#define UART16550_PARITY_ODD 0x08 +#define UART16550_PARITY_EVEN 0x18 +#define UART16550_PARITY_MARK 0x28 +#define UART16550_PARITY_SPACE 0x38 + +#define UART16550_DATA_5BIT 0x0 +#define UART16550_DATA_6BIT 0x1 +#define UART16550_DATA_7BIT 0x2 +#define UART16550_DATA_8BIT 0x3 + +#define UART16550_STOP_1BIT 0x0 +#define UART16550_STOP_2BIT 0x4 + +/* register offset */ +#define OFS_RCV_BUFFER 0 +#define OFS_TRANS_HOLD 0 +#define OFS_SEND_BUFFER 0 +#define OFS_INTR_ENABLE (1*REG_OFFSET) +#define OFS_INTR_ID (2*REG_OFFSET) +#define OFS_DATA_FORMAT (3*REG_OFFSET) +#define OFS_LINE_CONTROL (3*REG_OFFSET) +#define OFS_MODEM_CONTROL (4*REG_OFFSET) +#define OFS_RS232_OUTPUT (4*REG_OFFSET) +#define OFS_LINE_STATUS (5*REG_OFFSET) +#define OFS_MODEM_STATUS (6*REG_OFFSET) +#define OFS_RS232_INPUT (6*REG_OFFSET) +#define OFS_SCRATCH_PAD (7*REG_OFFSET) + +#define OFS_DIVISOR_LSB (0*REG_OFFSET) +#define OFS_DIVISOR_MSB (1*REG_OFFSET) + + +/* memory-mapped read/write of the port */ +#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) +#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) + +void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) +{ + /* disable interrupts */ + UART16550_WRITE(OFS_INTR_ENABLE, 0); + + /* set up buad rate */ + { + uint32 divisor; + + /* set DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x80); + + /* set divisor */ + divisor = MAX_BAUD / baud; + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); + + /* clear DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x0); + } + + /* set data format */ + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); +} + + +uint8 getDebugChar(void) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(BAUD_DEFAULT, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); + return UART16550_READ(OFS_RCV_BUFFER); +} + + +int putDebugChar(uint8 byte) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(BAUD_DEFAULT, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); + UART16550_WRITE(OFS_SEND_BUFFER, byte); + return 1; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5476/int-handler.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,112 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * First-level interrupt dispatcher for ddb5476 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include + +#include + +/* + * first level interrupt dispatcher for ocelot board - + * We check for the timer first, then check PCI ints A and D. + * Then check for serial IRQ and fall through. + */ + .align 5 + NESTED(ddb5476_handle_int, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + .set noreorder + mfc0 t0, CP0_CAUSE + mfc0 t2, CP0_STATUS + + and t0, t2 + + andi t1, t0, STATUSF_IP7 /* cpu timer */ + bnez t1, ll_cpu_ip7 + andi t1, t0, STATUSF_IP2 /* vrc5476 & i8259 */ + bnez t1, ll_cpu_ip2 + andi t1, t0, STATUSF_IP3 + bnez t1, ll_cpu_ip3 + andi t1, t0, STATUSF_IP4 + bnez t1, ll_cpu_ip4 + andi t1, t0, STATUSF_IP5 + bnez t1, ll_cpu_ip5 + andi t1, t0, STATUSF_IP6 + bnez t1, ll_cpu_ip6 + andi t1, t0, STATUSF_IP0 /* software int 0 */ + bnez t1, ll_cpu_ip0 + andi t1, t0, STATUSF_IP1 /* software int 1 */ + bnez t1, ll_cpu_ip1 + nop + + .set reorder + + /* wrong alarm or masked ... */ + // j spurious_interrupt + move a0, sp + jal vrc5476_irq_dispatch + j ret_from_irq + nop + + .align 5 + +ll_cpu_ip0: + li a0, CPU_IRQ_BASE + 0 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpu_ip1: + li a0, CPU_IRQ_BASE + 1 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpu_ip2: /* jump to second-level dispatching */ + move a0, sp + jal vrc5476_irq_dispatch + j ret_from_irq + +ll_cpu_ip3: + li a0, CPU_IRQ_BASE + 3 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpu_ip4: + li a0, CPU_IRQ_BASE + 4 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpu_ip5: + li a0, CPU_IRQ_BASE + 5 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpu_ip6: + li a0, CPU_IRQ_BASE + 6 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpu_ip7: + li a0, CPU_IRQ_BASE + 7 + move a1, sp + jal do_IRQ + j ret_from_irq + + END(ddb5476_handle_int) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5476/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,143 @@ +/* + * arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines + * + * Copyright (C) 2000 Geert Uytterhoeven + * Sony Software Development Center Europe (SDCE), Brussels + * + * Re-write the whole thing to use new irq.c file. + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + */ +#include +#include +#include +#include + +#include +#include +#include + +#include + +#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */ +#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */ +#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */ + +#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */ +#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */ +#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */ + +#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */ +#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */ + +#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */ +#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */ + +#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */ +#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */ + +static void m1543_irq_setup(void) +{ + /* + * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all + * the possible IO sources in the M1543 are in use by us. We will + * use the following mapping: + * + * IRQ1 - keyboard (default set by M1543) + * IRQ3 - reserved for UART B (default set by M1543) (note that + * the schematics for the DDB Vrc-5476 board seem to + * indicate that IRQ3 is connected to the DS1386 + * watchdog timer interrupt output so we might have + * a conflict) + * IRQ4 - reserved for UART A (default set by M1543) + * IRQ5 - parallel (default set by M1543) + * IRQ8 - DS1386 time of day (RTC) interrupt + * IRQ9 - USB (hardwired in ddb_setup) + * IRQ10 - PMU (hardwired in ddb_setup) + * IRQ12 - mouse + * IRQ14,15 - IDE controller (need to be confirmed, jsun) + */ + + /* + * Assing mouse interrupt to IRQ12 + */ + + /* Enter configuration mode */ + outb(0x51, M1543_PNP_CONFIG); + outb(0x23, M1543_PNP_CONFIG); + + /* Select logical device 7 (Keyboard) */ + outb(0x07, M1543_PNP_INDEX); + outb(0x07, M1543_PNP_DATA); + + /* Select IRQ12 */ + outb(0x72, M1543_PNP_INDEX); + outb(0x0c, M1543_PNP_DATA); + + /* Leave configration mode */ + outb(0xbb, M1543_PNP_CONFIG); +} + +static void nile4_irq_setup(void) +{ + int i; + + /* Map all interrupts to CPU int #0 (IP2) */ + nile4_map_irq_all(0); + + /* PCI INTA#-E# must be level triggered */ + nile4_set_pci_irq_level_or_edge(0, 1); + nile4_set_pci_irq_level_or_edge(1, 1); + nile4_set_pci_irq_level_or_edge(2, 1); + nile4_set_pci_irq_level_or_edge(3, 1); + + /* PCI INTA#, B#, D# must be active low, INTC# must be active high */ + nile4_set_pci_irq_polarity(0, 0); + nile4_set_pci_irq_polarity(1, 0); + nile4_set_pci_irq_polarity(2, 1); + nile4_set_pci_irq_polarity(3, 0); + + for (i = 0; i < 16; i++) + nile4_clear_irq(i); + + /* Enable CPU int #0 */ + nile4_enable_irq_output(0); + + /* memory resource acquire in ddb_setup */ +} + +static struct irqaction irq_cascade = { no_action, 0, 0, "cascade", NULL, NULL }; +static struct irqaction irq_error = { no_action, 0, 0, "error", NULL, NULL }; + +extern asmlinkage void ddb5476_handle_int(void); +extern int setup_irq(unsigned int irq, struct irqaction *irqaction); +extern void mips_cpu_irq_init(u32 irq_base); +extern void vrc5476_irq_init(u32 irq_base); + +void __init ddb5476_irq_setup(void) +{ + /* hardware initialization */ + nile4_irq_setup(); + m1543_irq_setup(); + + /* controller setup */ + init_i8259_irqs(); + vrc5476_irq_init(VRC5476_IRQ_BASE); + mips_cpu_irq_init(CPU_IRQ_BASE); + + /* setup cascade interrupts */ + setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade); + setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade); + + /* setup error interrupts for debugging */ + setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error); + setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error); + setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error); + setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error); + setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error); + setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error); + + /* setup the grandpa intr vector */ + set_except_vector(0, ddb5476_handle_int); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5476/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,9 @@ +# +# Makefile for the NEC DDB Vrc-5476 specific kernel interface routines +# under Linux. +# + +obj-y += setup.o irq.o int-handler.o nile4_pic.o vrc5476_irq.o +obj-$(CONFIG_KGDB) += dbg_io.o + +EXTRA_AFLAGS := $(CFLAGS) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5476/nile4_pic.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,190 @@ +/* + * arch/mips/ddb5476/nile4.c -- + * low-level PIC code for NEC Vrc-5476 (Nile 4) + * + * Copyright (C) 2000 Geert Uytterhoeven + * Sony Software Development Center Europe (SDCE), Brussels + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + */ +#include +#include +#include + +#include + +#include + + +/* + * Interrupt Programming + */ +void nile4_map_irq(int nile4_irq, int cpu_irq) +{ + u32 offset, t; + + offset = DDB_INTCTRL; + if (nile4_irq >= 8) { + offset += 4; + nile4_irq -= 8; + } + t = ddb_in32(offset); + t &= ~(7 << (nile4_irq * 4)); + t |= cpu_irq << (nile4_irq * 4); + ddb_out32(offset, t); +} + +void nile4_map_irq_all(int cpu_irq) +{ + u32 all, t; + + all = cpu_irq; + all |= all << 4; + all |= all << 8; + all |= all << 16; + t = ddb_in32(DDB_INTCTRL); + t &= 0x88888888; + t |= all; + ddb_out32(DDB_INTCTRL, t); + t = ddb_in32(DDB_INTCTRL + 4); + t &= 0x88888888; + t |= all; + ddb_out32(DDB_INTCTRL + 4, t); +} + +void nile4_enable_irq(int nile4_irq) +{ + u32 offset, t; + + offset = DDB_INTCTRL; + if (nile4_irq >= 8) { + offset += 4; + nile4_irq -= 8; + } + t = ddb_in32(offset); + t |= 8 << (nile4_irq * 4); + ddb_out32(offset, t); +} + +void nile4_disable_irq(int nile4_irq) +{ + u32 offset, t; + + offset = DDB_INTCTRL; + if (nile4_irq >= 8) { + offset += 4; + nile4_irq -= 8; + } + t = ddb_in32(offset); + t &= ~(8 << (nile4_irq * 4)); + ddb_out32(offset, t); +} + +void nile4_disable_irq_all(void) +{ + ddb_out32(DDB_INTCTRL, 0); + ddb_out32(DDB_INTCTRL + 4, 0); +} + +u16 nile4_get_irq_stat(int cpu_irq) +{ + return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2); +} + +void nile4_enable_irq_output(int cpu_irq) +{ + u32 t; + + t = ddb_in32(DDB_INTSTAT1 + 4); + t |= 1 << (16 + cpu_irq); + ddb_out32(DDB_INTSTAT1, t); +} + +void nile4_disable_irq_output(int cpu_irq) +{ + u32 t; + + t = ddb_in32(DDB_INTSTAT1 + 4); + t &= ~(1 << (16 + cpu_irq)); + ddb_out32(DDB_INTSTAT1, t); +} + +void nile4_set_pci_irq_polarity(int pci_irq, int high) +{ + u32 t; + + t = ddb_in32(DDB_INTPPES); + if (high) + t &= ~(1 << (pci_irq * 2)); + else + t |= 1 << (pci_irq * 2); + ddb_out32(DDB_INTPPES, t); +} + +void nile4_set_pci_irq_level_or_edge(int pci_irq, int level) +{ + u32 t; + + t = ddb_in32(DDB_INTPPES); + if (level) + t |= 2 << (pci_irq * 2); + else + t &= ~(2 << (pci_irq * 2)); + ddb_out32(DDB_INTPPES, t); +} + +void nile4_clear_irq(int nile4_irq) +{ + ddb_out32(DDB_INTCLR, 1 << nile4_irq); +} + +void nile4_clear_irq_mask(u32 mask) +{ + ddb_out32(DDB_INTCLR, mask); +} + +u8 nile4_i8259_iack(void) +{ + u8 irq; + u32 reg; + + /* Set window 0 for interrupt acknowledge */ + reg = ddb_in32(DDB_PCIINIT0); + + ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32); + irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE); + /* restore window 0 for PCI I/O space */ + // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32); + ddb_out32(DDB_PCIINIT0, reg); + + /* i8269.c set the base vector to be 0x0 */ + return irq + I8259_IRQ_BASE; +} + +#if defined(CONFIG_RUNTIME_DEBUG) +void nile4_dump_irq_status(void) +{ + printk(KERN_DEBUG " + CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4), + (void *) ddb_in32(DDB_CPUSTAT)); + printk(KERN_DEBUG " + INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4), + (void *) ddb_in32(DDB_INTCTRL)); + printk(KERN_DEBUG + "INTSTAT0 = %p:%p\n", + (void *) ddb_in32(DDB_INTSTAT0 + 4), + (void *) ddb_in32(DDB_INTSTAT0)); + printk(KERN_DEBUG + "INTSTAT1 = %p:%p\n", + (void *) ddb_in32(DDB_INTSTAT1 + 4), + (void *) ddb_in32(DDB_INTSTAT1)); + printk(KERN_DEBUG + "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4), + (void *) ddb_in32(DDB_INTCLR)); + printk(KERN_DEBUG + "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4), + (void *) ddb_in32(DDB_INTPPES)); +} +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5476/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,326 @@ +/* + * arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines + * + * Copyright (C) 2000 Geert Uytterhoeven + * Sony Software Development Center Europe (SDCE), Brussels + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +// #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */ + +#ifdef USE_CPU_COUNTER_TIMER + +#define CPU_COUNTER_FREQUENCY 83000000 +#else +/* otherwise we use general purpose timer */ +#define TIMER_FREQUENCY 83000000 +#define TIMER_BASE DDB_T2CTRL +#define TIMER_IRQ (VRC5476_IRQ_BASE + VRC5476_IRQ_GPT) +#endif + +#ifdef CONFIG_KGDB +extern void breakpoint(void); +#endif + +extern struct ide_ops std_ide_ops; +extern struct kbd_ops std_kbd_ops; + +static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000; + +static void ddb_machine_restart(char *command) +{ + u32 t; + + /* PCI cold reset */ + t = ddb_in32(DDB_PCICTRL + 4); + t |= 0x40000000; + ddb_out32(DDB_PCICTRL + 4, t); + /* CPU cold reset */ + t = ddb_in32(DDB_CPUSTAT); + t |= 1; + ddb_out32(DDB_CPUSTAT, t); + /* Call the PROM */ + back_to_prom(); +} + +static void ddb_machine_halt(void) +{ + printk(KERN_NOTICE "DDB Vrc-5476 halted.\n"); + while (1); +} + +static void ddb_machine_power_off(void) +{ + printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n"); + while (1); +} + +extern void ddb_irq_setup(void); +extern void rtc_ds1386_init(unsigned long base); + +static void __init ddb_time_init(void) +{ +#if defined(USE_CPU_COUNTER_TIMER) + mips_counter_frequency = CPU_COUNTER_FREQUENCY; +#endif + + /* we have ds1396 RTC chip */ + rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE)); +} + + +extern int setup_irq(unsigned int irq, struct irqaction *irqaction); +static void __init ddb_timer_setup(struct irqaction *irq) +{ +#if defined(USE_CPU_COUNTER_TIMER) + + unsigned int count; + + /* we are using the cpu counter for timer interrupts */ + setup_irq(CPU_IRQ_BASE + 7, irq); + + /* to generate the first timer interrupt */ + count = read_c0_count(); + write_c0_compare(count + 1000); + +#else + + ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ); + ddb_out32(TIMER_BASE+4, 0x1); /* enable timer */ + setup_irq(TIMER_IRQ, irq); +#endif +} + +static struct { + struct resource dma1; + struct resource pic1; + struct resource timer; + struct resource rtc; + struct resource dma_page_reg; + struct resource pic2; + struct resource dma2; +} ddb5476_ioport = { + { + "dma1", 0x00, 0x1f, IORESOURCE_BUSY}, { + "pic1", 0x20, 0x3f, IORESOURCE_BUSY}, { + "timer", 0x40, 0x5f, IORESOURCE_BUSY}, { + "rtc", 0x70, 0x7f, IORESOURCE_BUSY}, { + "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, { + "pic2", 0xa0, 0xbf, IORESOURCE_BUSY}, { + "dma2", 0xc0, 0xdf, IORESOURCE_BUSY} +}; + +static struct { + struct resource nile4; +} ddb5476_iomem = { + { "Nile 4", DDB_BASE, DDB_BASE + DDB_SIZE - 1, IORESOURCE_BUSY} +}; + + +static void ddb5476_board_init(void); +extern void ddb5476_irq_setup(void); +extern void (*irq_setup)(void); + +void __init +ddb_setup(void) +{ + extern int panic_timeout; + + irq_setup = ddb5476_irq_setup; + set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE)); + + board_time_init = ddb_time_init; + board_timer_setup = ddb_timer_setup; + + _machine_restart = ddb_machine_restart; + _machine_halt = ddb_machine_halt; + _machine_power_off = ddb_machine_power_off; + + /* request io port/mem resources */ + if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) || + request_resource(&ioport_resource, &ddb5476_ioport.pic1) || + request_resource(&ioport_resource, &ddb5476_ioport.timer) || + request_resource(&ioport_resource, &ddb5476_ioport.rtc) || + request_resource(&ioport_resource, + &ddb5476_ioport.dma_page_reg) + || request_resource(&ioport_resource, &ddb5476_ioport.pic2) + || request_resource(&ioport_resource, &ddb5476_ioport.dma2) + || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) { + printk + ("ddb_setup - requesting oo port resources failed.\n"); + for (;;); + } +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &std_ide_ops; +#endif + + /* Reboot on panic */ + panic_timeout = 180; + + /* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */ + /* *(long*)0xbfa00218 = 0x8; */ + +#ifdef CONFIG_FB + conswitchp = &dummy_con; +#endif + + /* board initialization stuff */ + ddb5476_board_init(); +} + +/* + * We don't trust bios. We essentially does hardware re-initialization + * as complete as possible, as far as we know we can safely do. + */ +static void ddb5476_board_init(void) +{ + /* ----------- setup PDARs ------------ */ + /* check SDRAM0, whether we are on MEM bus does not matter */ + db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) == + ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1)); + + /* SDRAM1 should be turned off. What is this for anyway ? */ + db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0); + + /* flash 1&2, DDB status, DDB control */ + ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0); + ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0); + ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0); + ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0); + + /* shut off other pdar so they don't accidentally get into the way */ + ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0); + ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0); + ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0); + + /* verify VRC5477 base addr */ + /* don't care about some details */ + db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) == + ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0)); + + /* verify BOOT ROM addr */ + /* don't care about some details */ + db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) == + ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0)); + + /* setup PCI windows - window1 for MEM/config, window0 for IO */ + ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1); + ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32); + + ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1); + ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32); + + /* ----------- setup PDARs ------------ */ + /* this is problematic - it will reset Aladin which cause we loose + * serial port, and we don't know how to set up Aladin chip again. + */ + // ddb_pci_reset_bus(); + + ddb_out32(DDB_BAR0, 0x00000008); + + ddb_out32(DDB_BARC, 0xffffffff); + ddb_out32(DDB_BARB, 0xffffffff); + ddb_out32(DDB_BAR1, 0xffffffff); + ddb_out32(DDB_BAR2, 0xffffffff); + ddb_out32(DDB_BAR3, 0xffffffff); + ddb_out32(DDB_BAR4, 0xffffffff); + ddb_out32(DDB_BAR5, 0xffffffff); + ddb_out32(DDB_BAR6, 0xffffffff); + ddb_out32(DDB_BAR7, 0xffffffff); + ddb_out32(DDB_BAR8, 0xffffffff); + + /* ----------- switch PCI1 to PCI CONFIG space ------------ */ + ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1); + ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32); + + /* ----- M1543 PCI setup ------ */ + + /* we know M1543 PCI-ISA controller is at addr:18 */ + /* xxxx1010 makes USB at addr:13 and PMU at addr:14 */ + *(volatile unsigned char *) 0xa8040072 &= 0xf0; + *(volatile unsigned char *) 0xa8040072 |= 0xa; + + /* setup USB interrupt to IRQ 9, (bit 0:3 - 0001) + * no IOCHRDY signal, (bit 7 - 1) + * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1) + * Make USB Master INTAJ level to edge conversion (bit 4 - 1) + */ + *(unsigned char *) 0xa8040074 = 0xd1; + + /* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011) + * SCI routing to IRQ 13 disabled (bit 7 - 1) + * SCI interrupt level to edge conversion bypassed (bit 4 - 0) + */ + *(unsigned char *) 0xa8040076 = 0x83; + + /* setup IDE controller + * enable IDE controller (bit 6 - 1) + * IDE IDSEL to be addr:24 (bit 4:5 - 11) + * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0) + * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0) + * primary IRQ is 14, secondary is 15 (bit 1:0 - 01 + */ + // *(unsigned char*)0xa8040058 = 0x71; + // *(unsigned char*)0xa8040058 = 0x79; + // *(unsigned char*)0xa8040058 = 0x74; // use SIRQ, primary tri-state + *(unsigned char *) 0xa8040058 = 0x75; // primary tri-state + +#if 0 + /* this is not necessary if M5229 does not use SIRQ */ + *(unsigned char *) 0xa8040044 = 0x0d; // primary to IRQ 14 + *(unsigned char *) 0xa8040075 = 0x0d; // secondary to IRQ 14 +#endif + + /* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */ + /* M5229 IDSEL is addr:24; see above setting */ + *(unsigned char *) 0xa9000050 |= 0x1; + + /* enable bus master (bit 2) and IO decoding (bit 0) */ + *(unsigned char *) 0xa9000004 |= 0x5; + + /* enable native, copied from arch/ppc/k2boot/head.S */ + /* TODO - need volatile, need to be portable */ + *(unsigned char *) 0xa9000009 = 0xff; + + /* ----- end of M1543 PCI setup ------ */ + + /* ----- reset on-board ether chip ------ */ + *((volatile u32 *) 0xa8020004) |= 1; /* decode I/O */ + *((volatile u32 *) 0xa8020010) = 0; /* set BAR address */ + + /* send reset command */ + *((volatile u32 *) 0xa6000000) = 1; /* do a soft reset */ + + /* disable ether chip */ + *((volatile u32 *) 0xa8020004) = 0; /* disable any decoding */ + + /* put it into sleep */ + *((volatile u32 *) 0xa8020040) = 0x80000000; + + /* ----- end of reset on-board ether chip ------ */ + + /* ----------- switch PCI1 back to PCI MEM space ------------ */ + ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1); + ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,113 @@ +/* + * The irq controller for vrc5476. + * + * Copyright (C) 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include +#include +#include + +#include + +#include + +static int irq_base; + +static void vrc5476_irq_enable(uint irq) +{ + nile4_enable_irq(irq - irq_base); +} + +static void vrc5476_irq_disable(uint irq) +{ + nile4_disable_irq(irq - irq_base); +} + +static unsigned int vrc5476_irq_startup(uint irq) +{ + nile4_enable_irq(irq - irq_base); + return 0; +} + +#define vrc5476_irq_shutdown vrc5476_irq_disable + +static void vrc5476_irq_ack(uint irq) +{ + nile4_clear_irq(irq - irq_base); + nile4_disable_irq(irq - irq_base); +} + +static void vrc5476_irq_end(uint irq) +{ + if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + vrc5476_irq_enable(irq); +} + +static hw_irq_controller vrc5476_irq_controller = { + "vrc5476", + vrc5476_irq_startup, + vrc5476_irq_shutdown, + vrc5476_irq_enable, + vrc5476_irq_disable, + vrc5476_irq_ack, + vrc5476_irq_end, + NULL /* no affinity stuff for UP */ +}; + +void __init +vrc5476_irq_init(u32 base) +{ + extern irq_desc_t irq_desc[]; + u32 i; + + irq_base = base; + for (i= base; i< base + NUM_VRC5476_IRQ; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].handler = &vrc5476_irq_controller; + } +} + + +asmlinkage void +vrc5476_irq_dispatch(struct pt_regs *regs) +{ + extern void spurious_interrupt(void); + + u32 mask; + int nile4_irq; + + mask = nile4_get_irq_stat(0); + + /* quick check for possible time interrupt */ + if (mask & (1 << VRC5476_IRQ_GPT)) { + do_IRQ(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT, regs); + return; + } + + /* check for i8259 interrupts */ + if (mask & (1 << VRC5476_I8259_CASCADE)) { + int i8259_irq = nile4_i8259_iack(); + do_IRQ(I8259_IRQ_BASE + i8259_irq, regs); + return; + } + + /* regular nile4 interrupts (we should not really have any */ + for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) { + if (mask & 1) { + do_IRQ(VRC5476_IRQ_BASE + nile4_irq, regs); + return; + } + } + spurious_interrupt(); +} --- linux-2.5.73/arch/mips/ddb5xxx/ddb5477/debug.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5477/debug.c 2003-06-27 15:56:23.000000000 -0700 @@ -15,8 +15,6 @@ */ #include -#include -#include /* SA_INTERRUPT */ #include #include @@ -32,9 +30,9 @@ void jsun_show_regs(char *name, Register printk("\nshow regs: %s\n", name); for(i=0;regs[i].regname!= NULL; i++) { - printk("%-16s= %08x\t\t(@%08x)\n", - regs[i].regname, - *(unsigned *)(regs[i].regaddr), + printk("%-16s= %08x\t\t(@%08x)\n", + regs[i].regname, + *(unsigned *)(regs[i].regaddr), regs[i].regaddr); } } @@ -58,15 +56,15 @@ static Register int_regs[] = { void vrc5477_show_int_regs() { jsun_show_regs("interrupt registers", int_regs); - printk("CPU CAUSE = %08x\n", read_32bit_cp0_register(CP0_CAUSE)); - printk("CPU STATUS = %08x\n", read_32bit_cp0_register(CP0_STATUS)); + printk("CPU CAUSE = %08x\n", read_c0_cause()); + printk("CPU STATUS = %08x\n", read_c0_status()); } static Register pdar_regs[] = { {"DDB_SDRAM0", DDB_BASE + DDB_SDRAM0}, {"DDB_SDRAM1", DDB_BASE + DDB_SDRAM1}, - {"DDB_LDCS0", DDB_BASE + DDB_LDCS0}, - {"DDB_LDCS1", DDB_BASE + DDB_LDCS1}, - {"DDB_LDCS2", DDB_BASE + DDB_LDCS2}, + {"DDB_LCS0", DDB_BASE + DDB_LCS0}, + {"DDB_LCS1", DDB_BASE + DDB_LCS1}, + {"DDB_LCS2", DDB_BASE + DDB_LCS2}, {"DDB_INTCS", DDB_BASE + DDB_INTCS}, {"DDB_BOOTCS", DDB_BASE + DDB_BOOTCS}, {"DDB_PCIW0", DDB_BASE + DDB_PCIW0}, --- linux-2.5.73/arch/mips/ddb5xxx/ddb5477/int-handler.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5477/int-handler.S 2003-06-27 15:56:23.000000000 -0700 @@ -9,13 +9,12 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ -#include - #include #include #include #include #include +#include /* * first level interrupt dispatcher for ocelot board - @@ -28,14 +27,14 @@ CLI .set at .set noreorder - mfc0 t0, CP0_CAUSE + mfc0 t0, CP0_CAUSE mfc0 t2, CP0_STATUS and t0, t2 - + andi t1, t0, STATUSF_IP7 /* cpu timer */ bnez t1, ll_cputimer_irq - andi t1, t0, (STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6 ) + andi t1, t0, (STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6 ) bnez t1, ll_vrc5477_irq andi t1, t0, STATUSF_IP0 /* software int 0 */ bnez t1, ll_cpu_ip0 @@ -51,26 +50,26 @@ .align 5 -ll_vrc5477_irq: +ll_vrc5477_irq: move a0, sp jal vrc5477_irq_dispatch j ret_from_irq ll_cputimer_irq: - li a0, 7 + li a0, CPU_IRQ_BASE + 7 move a1, sp jal do_IRQ j ret_from_irq -ll_cpu_ip0: - li a0, 0 +ll_cpu_ip0: + li a0, CPU_IRQ_BASE + 0 move a1, sp jal do_IRQ j ret_from_irq -ll_cpu_ip1: - li a0, 1 +ll_cpu_ip1: + li a0, CPU_IRQ_BASE + 1 move a1, sp jal do_IRQ j ret_from_irq --- linux-2.5.73/arch/mips/ddb5xxx/ddb5477/irq_5477.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5477/irq_5477.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,4 +1,4 @@ -/*********************************************************************** +/* * Copyright 2001 MontaVista Software Inc. * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net * @@ -9,7 +9,7 @@ * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. - *********************************************************************** + * */ /* @@ -19,37 +19,36 @@ * vrc5477_irq_init(u32 irq_base); */ -#include +#include #include #include -#include +#include -/* [jsun] sooner or later we should move this debug stuff to MIPS common */ -#include +#include /* number of total irqs supported by Vrc5477 */ #define NUM_5477_IRQ 32 -static int vrc5477_irq_base=-1; +static int vrc5477_irq_base = -1; -static void +static void vrc5477_irq_enable(unsigned int irq) { - MIPS_ASSERT(vrc5477_irq_base != -1); - MIPS_ASSERT(irq >= vrc5477_irq_base); - MIPS_ASSERT(irq < vrc5477_irq_base+ NUM_5477_IRQ); + db_assert(vrc5477_irq_base != -1); + db_assert(irq >= vrc5477_irq_base); + db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ); ll_vrc5477_irq_enable(irq - vrc5477_irq_base); } -static void +static void vrc5477_irq_disable(unsigned int irq) { - MIPS_ASSERT(vrc5477_irq_base != -1); - MIPS_ASSERT(irq >= vrc5477_irq_base); - MIPS_ASSERT(irq < vrc5477_irq_base + NUM_5477_IRQ); + db_assert(vrc5477_irq_base != -1); + db_assert(irq >= vrc5477_irq_base); + db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ); ll_vrc5477_irq_disable(irq - vrc5477_irq_base); } @@ -65,9 +64,9 @@ static unsigned int vrc5477_irq_startup( static void vrc5477_irq_ack(unsigned int irq) { - MIPS_ASSERT(vrc5477_irq_base != -1); - MIPS_ASSERT(irq >= vrc5477_irq_base); - MIPS_ASSERT(irq < vrc5477_irq_base+ NUM_5477_IRQ); + db_assert(vrc5477_irq_base != -1); + db_assert(irq >= vrc5477_irq_base); + db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ); /* clear the interrupt bit */ /* some irqs require the driver to clear the sources */ @@ -82,11 +81,12 @@ vrc5477_irq_ack(unsigned int irq) static void vrc5477_irq_end(unsigned int irq) { - MIPS_ASSERT(vrc5477_irq_base != -1); - MIPS_ASSERT(irq >= vrc5477_irq_base); - MIPS_ASSERT(irq < vrc5477_irq_base + NUM_5477_IRQ); + db_assert(vrc5477_irq_base != -1); + db_assert(irq >= vrc5477_irq_base); + db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ); - ll_vrc5477_irq_enable( irq - vrc5477_irq_base); + if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + ll_vrc5477_irq_enable( irq - vrc5477_irq_base); } hw_irq_controller vrc5477_irq_controller = { @@ -100,7 +100,7 @@ hw_irq_controller vrc5477_irq_controller NULL /* no affinity stuff for UP */ }; -void +void vrc5477_irq_init(u32 irq_base) { extern irq_desc_t irq_desc[]; @@ -112,17 +112,8 @@ vrc5477_irq_init(u32 irq_base) irq_desc[i].depth = 1; irq_desc[i].handler = &vrc5477_irq_controller; } - - vrc5477_irq_base = irq_base; -} - -int vrc5477_irq_to_irq(int irq) -{ - MIPS_ASSERT(irq >= 0); - MIPS_ASSERT(irq < NUM_5477_IRQ); - - return irq + vrc5477_irq_base; + vrc5477_irq_base = irq_base; } void ll_vrc5477_irq_route(int vrc5477_irq, int ip) @@ -131,10 +122,10 @@ void ll_vrc5477_irq_route(int vrc5477_ir u32 reg_bitmask; u32 reg_index; - MIPS_ASSERT(vrc5477_irq >= 0); - MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ); - MIPS_ASSERT(ip >= 0); - MIPS_ASSERT((ip < 5) || (ip == 6)); + db_assert(vrc5477_irq >= 0); + db_assert(vrc5477_irq < NUM_5477_IRQ); + db_assert(ip >= 0); + db_assert((ip < 5) || (ip == 6)); reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; reg_value = ddb_in32(reg_index); @@ -150,13 +141,13 @@ void ll_vrc5477_irq_enable(int vrc5477_i u32 reg_bitmask; u32 reg_index; - MIPS_ASSERT(vrc5477_irq >= 0); - MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ); + db_assert(vrc5477_irq >= 0); + db_assert(vrc5477_irq < NUM_5477_IRQ); reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; reg_value = ddb_in32(reg_index); reg_bitmask = 8 << (vrc5477_irq % 8 * 4); - MIPS_ASSERT((reg_value & reg_bitmask) == 0); + db_assert((reg_value & reg_bitmask) == 0); ddb_out32(reg_index, reg_value | reg_bitmask); } @@ -166,14 +157,14 @@ void ll_vrc5477_irq_disable(int vrc5477_ u32 reg_bitmask; u32 reg_index; - MIPS_ASSERT(vrc5477_irq >= 0); - MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ); + db_assert(vrc5477_irq >= 0); + db_assert(vrc5477_irq < NUM_5477_IRQ); reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; reg_value = ddb_in32(reg_index); reg_bitmask = 8 << (vrc5477_irq % 8 * 4); /* we assert that the interrupt is enabled (perhaps over-zealous) */ - MIPS_ASSERT( (reg_value & reg_bitmask) != 0); + db_assert( (reg_value & reg_bitmask) != 0); ddb_out32(reg_index, reg_value & ~reg_bitmask); } --- linux-2.5.73/arch/mips/ddb5xxx/ddb5477/irq.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5477/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -12,16 +12,20 @@ */ #include #include +#include #include #include #include +#include #include #include +#include +#include +#include + #include -/* [jsun] sooner or later we should move this debug stuff to MIPS common */ -#include /* * IRQ mapping @@ -37,7 +41,7 @@ * 7 - cpu timer (used by default) * * 8-39: 32 Vrc5477 interrupt sources - * (refer to the Vrc5477 manual) + * (refer to the Vrc5477 manual) */ #define PCI0 DDB_INTPPES0 @@ -55,7 +59,7 @@ #define INTD 3 #define INTE 4 -static inline void +static inline void set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger) { u32 reg_value; @@ -63,7 +67,7 @@ set_pci_int_attr(u32 pci, u32 intn, u32 reg_value = ddb_in32(pci); reg_bitmask = 0x3 << (intn * 2); - + reg_value &= ~reg_bitmask; reg_value |= (active | trigger) << (intn * 2); ddb_out32(pci, reg_value); @@ -72,26 +76,31 @@ set_pci_int_attr(u32 pci, u32 intn, u32 extern void vrc5477_irq_init(u32 base); extern void mips_cpu_irq_init(u32 base); extern asmlinkage void ddb5477_handle_int(void); +extern int setup_irq(unsigned int irq, struct irqaction *irqaction); +static struct irqaction irq_cascade = { no_action, 0, 0, "cascade", NULL, NULL }; void ddb5477_irq_setup(void) { - MIPS_DEBUG(printk("ddb5477_irq_setup invoked.\n")); + db_run(printk("ddb5477_irq_setup invoked.\n")); - /* by default, we disable all interrupts and route all vrc5477 + /* by default, we disable all interrupts and route all vrc5477 * interrupts to pin 0 (irq 2) */ ddb_out32(DDB_INTCTRL0, 0); ddb_out32(DDB_INTCTRL1, 0); ddb_out32(DDB_INTCTRL2, 0); ddb_out32(DDB_INTCTRL3, 0); - clear_cp0_status(0xff00); - set_cp0_status(0x0400); + clear_c0_status(0xff00); + set_c0_status(0x0400); /* setup PCI interrupt attributes */ set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE); - set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE); + if (mips_machtype == MACH_NEC_ROCKHOPPERII) + set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE); + else + set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE); @@ -101,9 +110,9 @@ ddb5477_irq_setup(void) set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE); - /* + /* * for debugging purpose, we enable several error interrupts - * and route them to pin 1. (IP3) + * and route them to pin 1. (IP3) */ /* cpu parity check - 0 */ ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0); @@ -121,13 +130,34 @@ ddb5477_irq_setup(void) ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31); /* init all controllers */ - mips_cpu_irq_init(0); - vrc5477_irq_init(8); + init_i8259_irqs(); + mips_cpu_irq_init(CPU_IRQ_BASE); + vrc5477_irq_init(VRC5477_IRQ_BASE); + + + /* setup cascade interrupts */ + setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade); + setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); /* hook up the first-level interrupt handler */ set_except_vector(0, ddb5477_handle_int); } +u8 i8259_interrupt_ack(void) +{ + u8 irq; + u32 reg; + + /* Set window 0 for interrupt acknowledge */ + reg = ddb_in32(DDB_PCIINIT10); + + ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32); + irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE); + ddb_out32(DDB_PCIINIT10, reg); + + /* i8259.c set the base vector to be 0x0 */ + return irq + I8259_IRQ_BASE; +} /* * the first level int-handler will jump here if it is a vrc5477 irq */ @@ -135,29 +165,38 @@ ddb5477_irq_setup(void) asmlinkage void vrc5477_irq_dispatch(struct pt_regs *regs) { - extern unsigned int do_IRQ(int irq, struct pt_regs *regs); - u32 intStatus; u32 bitmask; u32 i; - MIPS_ASSERT(ddb_in32(DDB_INT2STAT) == 0); - MIPS_ASSERT(ddb_in32(DDB_INT3STAT) == 0); - MIPS_ASSERT(ddb_in32(DDB_INT4STAT) == 0); - MIPS_ASSERT(ddb_in32(DDB_NMISTAT) == 0); + db_assert(ddb_in32(DDB_INT2STAT) == 0); + db_assert(ddb_in32(DDB_INT3STAT) == 0); + db_assert(ddb_in32(DDB_INT4STAT) == 0); + db_assert(ddb_in32(DDB_NMISTAT) == 0); if (ddb_in32(DDB_INT1STAT) != 0) { -#if defined(CONFIG_LL_DEBUG) +#if defined(CONFIG_RUNTIME_DEBUG) vrc5477_show_int_regs(); #endif - panic("error interrupt has happened.\n"); + panic("error interrupt has happened."); } intStatus = ddb_in32(DDB_INT0STAT); + + if (mips_machtype == MACH_NEC_ROCKHOPPERII) { + /* check for i8259 interrupts */ + if (intStatus & (1 << VRC5477_I8259_CASCADE)) { + int i8259_irq = i8259_interrupt_ack(); + do_IRQ(I8259_IRQ_BASE + i8259_irq, regs); + return; + } + } + for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) { /* do we need to "and" with the int mask? */ if (intStatus & bitmask) { - do_IRQ(8 + i, regs); + do_IRQ(VRC5477_IRQ_BASE + i, regs); + return; } } } --- linux-2.5.73/arch/mips/ddb5xxx/ddb5477/kgdb_io.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5477/kgdb_io.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,17 +1,41 @@ +/* + * kgdb io functions for DDB5477. We use the second serial port (upper one). + * + * Copyright (C) 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ -#include +/* ======================= CONFIG ======================== */ -#if (defined(CONFIG_DDB5477) && defined(CONFIG_REMOTE_DEBUG)) +/* [jsun] we use the second serial port for kdb */ +#define BASE 0xbfa04240 +#define MAX_BAUD 115200 -/* --- CONFIG --- */ +/* distance in bytes between two serial registers */ +#define REG_OFFSET 8 + +/* + * 0 - kgdb does serial init + * 1 - kgdb skip serial init + */ +static int remoteDebugInitialized = 0; + +/* + * the default baud rate *if* kgdb does serial init + */ +#define BAUD_DEFAULT UART16550_BAUD_38400 + +/* ======================= END OF CONFIG ======================== */ -/* we need uint32 uint8 */ -/* #include "types.h" */ typedef unsigned char uint8; typedef unsigned int uint32; -/* --- END OF CONFIG --- */ - #define UART16550_BAUD_2400 2400 #define UART16550_BAUD_4800 4800 #define UART16550_BAUD_9600 9600 @@ -34,21 +58,10 @@ typedef unsigned int uint32; #define UART16550_STOP_1BIT 0x0 #define UART16550_STOP_2BIT 0x4 -/* ----------------------------------------------------- */ - -/* === CONFIG === */ - -/* [jsun] we use the second serial port for kdb */ -#define BASE 0xbfa04240 -#define MAX_BAUD 115200 -#define REG_OFFSET 8 - -/* === END OF CONFIG === */ - /* register offset */ -#define OFS_RCV_BUFFER (0*REG_OFFSET) -#define OFS_TRANS_HOLD (0*REG_OFFSET) -#define OFS_SEND_BUFFER (0*REG_OFFSET) +#define OFS_RCV_BUFFER 0 +#define OFS_TRANS_HOLD 0 +#define OFS_SEND_BUFFER 0 #define OFS_INTR_ENABLE (1*REG_OFFSET) #define OFS_INTR_ID (2*REG_OFFSET) #define OFS_DATA_FORMAT (3*REG_OFFSET) @@ -70,73 +83,54 @@ typedef unsigned int uint32; void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) { - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); + /* disable interrupts */ + UART16550_WRITE(OFS_INTR_ENABLE, 0); - /* set up buad rate */ - { - uint32 divisor; - - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - } + /* set up buad rate */ + { + uint32 divisor; + + /* set DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x80); + + /* set divisor */ + divisor = MAX_BAUD / baud; + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); + + /* clear DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x0); + } - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); + /* set data format */ + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); } -static int remoteDebugInitialized = 0; - -int debug_state = -1; uint8 getDebugChar(void) { - uint8 c; - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_38400, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(BAUD_DEFAULT, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); - c= UART16550_READ(OFS_RCV_BUFFER); -/* - if (state != 1) { - state = 1; - debug_out("\ngetDebugChar: ", 15); - } - debug_out(&c, 1); -*/ - return c; + while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); + return UART16550_READ(OFS_RCV_BUFFER); } int putDebugChar(uint8 byte) { - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_9600, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); - UART16550_WRITE(OFS_SEND_BUFFER, byte); - if (debug_state != 2) { - debug_state = 2; - // debug_out("\nputDebugChar: ", 15); - } - // debug_out(&byte, 1); - return 1; + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(BAUD_DEFAULT, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); + UART16550_WRITE(OFS_SEND_BUFFER, byte); + return 1; } - -#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5477/lcd44780.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,92 @@ +/* + * lcd44780.c + * Simple "driver" for a memory-mapped 44780-style LCD display. + * + * Copyright 2001 Bradley D. LaRonde + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#define LCD44780_COMMAND ((volatile unsigned char *)0xbe020000) +#define LCD44780_DATA ((volatile unsigned char *)0xbe020001) + +#define LCD44780_4BIT_1LINE 0x20 +#define LCD44780_4BIT_2LINE 0x28 +#define LCD44780_8BIT_1LINE 0x30 +#define LCD44780_8BIT_2LINE 0x38 +#define LCD44780_MODE_DEC 0x04 +#define LCD44780_MODE_DEC_SHIFT 0x05 +#define LCD44780_MODE_INC 0x06 +#define LCD44780_MODE_INC_SHIFT 0x07 +#define LCD44780_SCROLL_LEFT 0x18 +#define LCD44780_SCROLL_RIGHT 0x1e +#define LCD44780_CURSOR_UNDERLINE 0x0e +#define LCD44780_CURSOR_BLOCK 0x0f +#define LCD44780_CURSOR_OFF 0x0c +#define LCD44780_CLEAR 0x01 +#define LCD44780_BLANK 0x08 +#define LCD44780_RESTORE 0x0c // Same as CURSOR_OFF +#define LCD44780_HOME 0x02 +#define LCD44780_LEFT 0x10 +#define LCD44780_RIGHT 0x14 + +void lcd44780_wait(void) +{ + int i, j; + for(i=0; i < 400; i++) + for(j=0; j < 10000; j++); +} + +void lcd44780_command(unsigned char c) +{ + *LCD44780_COMMAND = c; + lcd44780_wait(); +} + +void lcd44780_data(unsigned char c) +{ + *LCD44780_DATA = c; + lcd44780_wait(); +} + +void lcd44780_puts(const char* s) +{ + int i,j; + int pos = 0; + + lcd44780_command(LCD44780_CLEAR); + while(*s) { + lcd44780_data(*s); + s++; + pos++; + if (pos == 8) { + /* We must write 32 of spaces to get cursor to 2nd line */ + for (j=0; j<32; j++) { + lcd44780_data(' '); + } + } + if (pos == 16) { + /* We have filled all 16 character positions, so stop + outputing data */ + break; + } + } +#ifdef LCD44780_PUTS_PAUSE + for(i = 1; i < 2000; i++) + lcd44780_wait(); +#endif +} + +void lcd44780_init(void) +{ + // The display on the RockHopper is physically a single + // 16 char line (two 8 char lines concatenated). bdl + lcd44780_command(LCD44780_8BIT_2LINE); + lcd44780_command(LCD44780_MODE_INC); + lcd44780_command(LCD44780_CURSOR_BLOCK); + lcd44780_command(LCD44780_CLEAR); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5477/lcd44780.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,15 @@ +/* + * lcd44780.h + * Simple "driver" for a memory-mapped 44780-style LCD display. + * + * Copyright 2001 Bradley D. LaRonde + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +void lcd44780_puts(const char* s); +void lcd44780_init(void); --- linux-2.5.73/arch/mips/ddb5xxx/ddb5477/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5477/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -2,10 +2,9 @@ # Makefile for NEC DDB-Vrc5477 board # -EXTRA_AFLAGS := $(CFLAGS) +obj-y += int-handler.o irq.o irq_5477.o setup.o lcd44780.o -obj-y += int-handler.o irq.o irq_5477.o setup.o pci.o pci_ops.o +obj-$(CONFIG_RUNTIME_DEBUG) += debug.o +obj-$(CONFIG_KGDB) += kgdb_io.o -obj-$(CONFIG_LL_DEBUG) += debug.o -obj-$(CONFIG_REMOTE_DEBUG) += kgdb_io.o -obj-$(CONFIG_BLK_DEV_INITRD) += ramdisk.o +EXTRA_AFLAGS := $(CFLAGS) --- linux-2.5.73/arch/mips/ddb5xxx/ddb5477/pci.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,147 +0,0 @@ -#include -#include -#include -#include - -#include -#include -#include - -static struct resource extpci_io_resource = { - "ext pci IO space", - DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE, - DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE -1, - IORESOURCE_IO}; - -static struct resource extpci_mem_resource = { - "ext pci memory space", - DDB_PCI0_MEM_BASE, - DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE -1, - IORESOURCE_MEM}; - -static struct resource iopci_io_resource = { - "io pci IO space", - DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE, - DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE -1, - IORESOURCE_IO}; - -static struct resource iopci_mem_resource = { - "ext pci memory space", - DDB_PCI1_MEM_BASE, - DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE -1, - IORESOURCE_MEM}; - -extern struct pci_ops ddb5477_ext_pci_ops; -extern struct pci_ops ddb5477_io_pci_ops; - -struct pci_channel mips_pci_channels[] = { - { &ddb5477_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource }, - { &ddb5477_io_pci_ops, &iopci_io_resource, &iopci_mem_resource }, - { NULL, NULL, NULL} -}; - - -/* - * we fix up irqs based on the slot number. - * The first entry is at AD:11. - * Fortunately this works because, although we have two pci buses, - * they all have different slot numbers. - * - * This does not work for devices on sub-buses. - * - * Note that the irq number in the array is relative number in vrc5477. - * We need to translate it to global irq number. - */ - -/* - * irq mapping : PCI int # -> vrc5477 irq # - * based on vrc5477 manual page 46 - */ -#define PCI_EXT_INTA 8 -#define PCI_EXT_INTB 9 -#define PCI_EXT_INTC 10 -#define PCI_EXT_INTD 11 -#define PCI_EXT_INTE 12 - -#define PCI_IO_INTA 16 -#define PCI_IO_INTB 17 -#define PCI_IO_INTC 18 -#define PCI_IO_INTD 19 - -/* - * irq mapping : device -> pci int #, - * ddb5477 board manual page 4 and vrc5477 manual page 46 - */ -#define INT_ONBOARD_TULIP PCI_EXT_INTA -#define INT_SLOT1 PCI_EXT_INTB -#define INT_SLOT2 PCI_EXT_INTC -#define INT_SLOT3 PCI_EXT_INTD -#define INT_SLOT4 PCI_EXT_INTE - -#define INT_USB_HOST PCI_IO_INTA -#define INT_USB_PERI PCI_IO_INTB -#define INT_AC97 PCI_IO_INTC - -/* - * based on ddb5477 manual page 11 - */ -#define MAX_SLOT_NUM 21 -static unsigned char irq_map[MAX_SLOT_NUM] = { - /* AD:11 */ 0xff, 0xff, 0xff, 0xff, - /* AD:15 */ INT_ONBOARD_TULIP, INT_SLOT1, INT_SLOT2, INT_SLOT3, - /* AD:19 */ INT_SLOT4, 0xff, 0xff, 0xff, - /* AD:23 */ 0xff, 0xff, 0xff, 0xff, - /* AD:27 */ 0xff, 0xff, INT_AC97, INT_USB_PERI, - /* AD:31 */ INT_USB_HOST -}; - -extern int vrc5477_irq_to_irq(int irq); -void __init pcibios_fixup_irqs(void) -{ - struct pci_dev *dev = NULL; - int slot_num; - - while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { - slot_num = PCI_SLOT(dev->devfn); - MIPS_ASSERT(slot_num < MAX_SLOT_NUM); - MIPS_ASSERT(irq_map[slot_num] != 0xff); - - pci_write_config_byte(dev, - PCI_INTERRUPT_LINE, - irq_map[slot_num]); - dev->irq = vrc5477_irq_to_irq(irq_map[slot_num]); - } -} - -#if defined(CONFIG_LL_DEBUG) -extern void jsun_scan_pci_bus(void); -extern void jsun_assign_pci_resource(void); -#endif -void __init ddb_pci_reset_bus(void) -{ - u32 temp; - - /* - * I am not sure about the "official" procedure, the following - * steps work as far as I know: - * We first set PCI cold reset bit (bit 31) in PCICTRL-H. - * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. - * The same is true for both PCI channels. - */ - temp = ddb_in32(DDB_PCICTL0_H); - temp |= 0x80000000; - ddb_out32(DDB_PCICTL0_H, temp); - temp &= ~0xc0000000; - ddb_out32(DDB_PCICTL0_H, temp); - - temp = ddb_in32(DDB_PCICTL1_H); - temp |= 0x80000000; - ddb_out32(DDB_PCICTL1_H, temp); - temp &= ~0xc0000000; - ddb_out32(DDB_PCICTL1_H, temp); -} - -unsigned __init int pcibios_assign_all_busses(void) -{ - return 1; -} --- linux-2.5.73/arch/mips/ddb5xxx/ddb5477/pci_ops.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,381 +0,0 @@ -/*********************************************************************** - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/ddb5xxx/ddb5477/pci_ops.c - * Define the pci_ops for DB5477. - * - * Much of the code is derived from the original DDB5074 port by - * Geert Uytterhoeven - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - *********************************************************************** - */ - -/* - * DDB5477 has two PCI channels, external PCI and IOPIC (internal) - * Therefore we provide two sets of pci_ops. - */ - -#include -#include -#include -#include - -#include -#include -#include - -/* - * config_swap structure records what set of pdar/pmr are used - * to access pci config space. It also provides a place hold the - * original values for future restoring. - */ -struct pci_config_swap { - u32 pdar; - u32 pmr; - u32 config_base; - u32 config_size; - u32 pdar_backup; - u32 pmr_backup; -}; - -/* - * On DDB5477, we have two sets of swap registers, for ext PCI and IOPCI. - */ -struct pci_config_swap ext_pci_swap = { - DDB_PCIW0, - DDB_PCIINIT00, - DDB_PCI0_CONFIG_BASE, - DDB_PCI0_CONFIG_SIZE -}; -struct pci_config_swap io_pci_swap = { - DDB_IOPCIW0, - DDB_PCIINIT01, - DDB_PCI1_CONFIG_BASE, - DDB_PCI1_CONFIG_SIZE -}; - - -/* - * access config space - */ -static inline u32 ddb_access_config_base(struct pci_config_swap *swap, - u32 bus,/* 0 means top level bus */ - u32 slot_num) -{ - u32 pci_addr = 0; - u32 pciinit_offset = 0; - u32 virt_addr = swap->config_base; - u32 option; - - /* [jsun] hack for testing */ - // if (slot_num == 4) slot_num = 0; - - /* minimum pdar (window) size is 2MB */ - MIPS_ASSERT(swap->config_size >= (2 << 20)); - - MIPS_ASSERT(slot_num < (1 << 5)); - MIPS_ASSERT(bus < (1 << 8)); - - /* backup registers */ - swap->pdar_backup = ddb_in32(swap->pdar); - swap->pmr_backup = ddb_in32(swap->pmr); - - /* set the pdar (pci window) register */ - ddb_set_pdar(swap->pdar, - swap->config_base, - swap->config_size, - 32, /* 32 bit wide */ - 0, /* not on local memory bus */ - 0); /* not visible from PCI bus (N/A) */ - - /* - * calcuate the absolute pci config addr; - * according to the spec, we start scanning from adr:11 (0x800) - */ - if (bus == 0) { - /* type 0 config */ - pci_addr = 0x800 << slot_num; - } else { - /* type 1 config */ - pci_addr = (bus << 16) | (slot_num << 11); - panic("ddb_access_config_base: we don't support type 1 config Yet"); - } - - /* - * if pci_addr is less than pci config window size, we set - * pciinit_offset to 0 and adjust the virt_address. - * Otherwise we will try to adjust pciinit_offset. - */ - if (pci_addr < swap->config_size) { - virt_addr = KSEG1ADDR(swap->config_base + pci_addr); - pciinit_offset = 0; - } else { - MIPS_ASSERT( (pci_addr & (swap->config_size - 1)) == 0); - virt_addr = KSEG1ADDR(swap->config_base); - pciinit_offset = pci_addr; - } - - /* set the pmr register */ - option = DDB_PCI_ACCESS_32; - if (bus != 0) option |= DDB_PCI_CFGTYPE1; - ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option); - - return virt_addr; -} - -static inline void ddb_close_config_base(struct pci_config_swap *swap) -{ - ddb_out32(swap->pdar, swap->pdar_backup); - ddb_out32(swap->pmr, swap->pmr_backup); -} - -static int read_config(struct pci_config_swap *swap, - struct pci_bus *bus, - unsigned int devfn, - u32 where, - int size, - u32 *val) -{ - u32 busnum, slot_num, func_num, base, result; - int status - - switch (size) { - case 4: - MIPS_ASSERT((where & 3) == 0); - MIPS_ASSERT(where < (1 << 8)); - - /* check if the bus is top-level */ - if (bus->parent != NULL) { - busnum = bus->number; - MIPS_ASSERT(busnum != 0); - } else { - busnum = 0; - } - - slot_num = PCI_SLOT(devfn); - func_num = PCI_FUNC(devfn); - base = ddb_access_config_base(swap, busnum, slot_num); - *val = *(volatile u32*) (base + (func_num << 8) + where); - ddb_close_config_base(swap); - return PCIBIOS_SUCCESSFUL; - - case 2: - MIPS_ASSERT((where & 1) == 0); - - status = read_config(swap, bus, devfn, where & ~3, 4, - &result); - if (where & 2) result >>= 16; - *val = (u16)(result & 0xffff); - return status; - - case 1: - status = read_config(swap, bus, devfn, where & ~3, 4, - &result); - if (where & 1) result >>= 8; - if (where & 2) result >>= 16; - *val = (u8)(result & 0xff); - return status; - } -} - -static int write_config(struct pci_config_swap *swap, - struct pci_bus *bus, - unsigned int devfn, - u32 where, - int size, - u32 val) -{ - u32 busnum, slot_num, func_num, base, results; - int status, shift = 0; - - switch (size) { - case 4: - MIPS_ASSERT((where & 3) == 0); - MIPS_ASSERT(where < (1 << 8)); - - /* check if the bus is top-level */ - if (bus->parent != NULL) { - busnum = bus->number; - MIPS_ASSERT(busnum != 0); - } else { - busnum = 0; - } - - slot_num = PCI_SLOT(devfn); - func_num = PCI_FUNC(devfn); - base = ddb_access_config_base(swap, busnum, slot_num); - *(volatile u32*) (base + (func_num << 8) + where) = val; - ddb_close_config_base(swap); - return PCIBIOS_SUCCESSFUL; - - case 2: - MIPS_ASSERT((where & 1) == 0); - - status = read_config(swap, bus, devfn, where & ~3, 4, - &result); - if (status != PCIBIOS_SUCCESSFUL) return status; - - if (where & 2) - shift += 16; - result &= ~(0xffff << shift); - result |= (u16)(val << shift); - return write_config(swap, bus, devfn, where & ~3, size, - result); - - case 1: - status = read_config(swap, bus, devfn, where & ~3, 4, - &result); - if (status != PCIBIOS_SUCCESSFUL) return status; - - if (where & 2) - shift += 16; - if (where & 1) - shift += 8; - result &= ~(0xff << shift); - result |= (u8)(val << shift); - return write_config(swap, bus, devfn, where & ~3, size, - result); - } -} - -#define MAKE_PCI_OPS(prefix, rw, pciswap) \ -static int prefix##_##rw##_config(struct pci_bus *bus, unsigned int devfn, \ - int where, int size, u32 val) \ -{ \ - return rw##_config(pciswap, bus, devfn, \ - where, size, val); \ -} - -MAKE_PCI_OPS(extpci, read, &ext_pci_swap) -MAKE_PCI_OPS(extpci, write, &ext_pci_swap) - -MAKE_PCI_OPS(iopci, read, &io_pci_swap) -MAKE_PCI_OPS(iopci, write, &io_pci_swap) - -struct pci_ops ddb5477_ext_pci_ops ={ - .read = extpci_read_config, - .write = extpci_write_config, -}; - - -struct pci_ops ddb5477_io_pci_ops ={ - .read = iopci_read_config, - .write = iopci_write_config, -}; - -#if defined(CONFIG_LL_DEBUG) -void jsun_scan_pci_bus(void) -{ - struct pci_bus bus; - struct pci_dev dev; - unsigned int devfn; - int j; - - bus.parent = NULL; /* we scan the top level only */ - dev.bus = &bus; - dev.sysdata = NULL; - - /* scan ext pci bus and io pci bus*/ - for (j=0; j< 2; j++) { - if (j == 0) { - printk("scan ddb5477 external PCI bus:\n"); - bus.ops = &ddb5477_ext_pci_ops; - } else { - printk("scan ddb5477 IO PCI bus:\n"); - bus.ops = &ddb5477_io_pci_ops; - } - - for (devfn = 0; devfn < 0x100; devfn += 8) { - u32 temp; - u16 temp16; - u8 temp8; - int i; - - dev.devfn = devfn; - MIPS_VERIFY(pci_read_config_dword(&dev, 0, &temp), - == PCIBIOS_SUCCESSFUL); - if (temp == 0xffffffff) continue; - - printk("slot %d: (addr %d) \n", devfn/8, 11+devfn/8); - - /* verify read word and byte */ - MIPS_VERIFY(pci_read_config_word(&dev, 2, &temp16), - == PCIBIOS_SUCCESSFUL); - MIPS_ASSERT(temp16 == (temp >> 16)); - MIPS_VERIFY(pci_read_config_byte(&dev, 3, &temp8), - == PCIBIOS_SUCCESSFUL); - MIPS_ASSERT(temp8 == (temp >> 24)); - MIPS_VERIFY(pci_read_config_byte(&dev, 1, &temp8), - == PCIBIOS_SUCCESSFUL); - MIPS_ASSERT(temp8 == ((temp >> 8) & 0xff)); - - for (i=0; i < 16; i++) { - MIPS_VERIFY(pci_read_config_dword(&dev, i*4, &temp), - == PCIBIOS_SUCCESSFUL); - printk("\t%08X", temp); - if ((i%4) == 3) printk("\n"); - } - } - } -} - - -static void jsun_hardcode_pci_resources_eepro(void) -{ - struct pci_bus bus; - struct pci_dev dev; - u32 temp; - - bus.parent = NULL; /* we scan the top level only */ - bus.ops = &ddb5477_ext_pci_ops; - dev.bus = &bus; - dev.sysdata = NULL; - - /* for slot 5 (ext pci 1) eepro card */ - dev.devfn = 5*8; - pci_read_config_dword(&dev, 0, &temp); - MIPS_ASSERT(temp == 0x12298086); - - pci_write_config_dword(&dev, PCI_BASE_ADDRESS_0, DDB_PCI0_MEM_BASE); - pci_write_config_dword(&dev, PCI_BASE_ADDRESS_1, 0); - pci_write_config_dword(&dev, PCI_BASE_ADDRESS_2, DDB_PCI0_MEM_BASE+0x100000); - pci_write_config_dword(&dev, PCI_INTERRUPT_LINE, 17); -} - -static void jsun_hardcode_pci_resources_onboard_tulip(void) -{ - struct pci_bus bus; - struct pci_dev dev; - u32 temp; - - bus.parent = NULL; /* we scan the top level only */ - bus.ops = &ddb5477_ext_pci_ops; - dev.bus = &bus; - dev.sysdata = NULL; - - /* for slot 4 on board ether chip */ - dev.devfn = 4*8; - pci_read_config_dword(&dev, 0, &temp); - MIPS_ASSERT(temp == 0x00191011); - - pci_write_config_dword(&dev, PCI_BASE_ADDRESS_0, 0x1000); - pci_write_config_dword(&dev, PCI_BASE_ADDRESS_1, DDB_PCI0_MEM_BASE); - pci_write_config_dword(&dev, PCI_INTERRUPT_LINE, 16); -} - -static void jsun_hardcode_pci_resources(void) -{ - jsun_hardcode_pci_resources_onboard_tulip(); -} - -void jsun_assign_pci_resource(void) -{ - jsun_hardcode_pci_resources(); -} - -#endif --- linux-2.5.73/arch/mips/ddb5xxx/ddb5477/setup.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/ddb5xxx/ddb5477/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,4 +1,4 @@ -/*********************************************************************** +/* * * Copyright 2001 MontaVista Software Inc. * Author: jsun@mvista.com or jsun@junsun.net @@ -10,14 +10,10 @@ * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. - * - *********************************************************************** */ - #include #include #include -#include #include #include #include @@ -26,29 +22,35 @@ #include #include #include /* for HZ */ +#include +#include #include +#include +#include #include #include #include #include #include #include +#include +#include +#ifdef CONFIG_PC_KEYB +#include +#endif #include +#include "lcd44780.h" #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */ -#ifdef USE_CPU_COUNTER_TIMER -#define CPU_COUNTER_FREQUENCY 83000000 -#else -/* otherwise we use special timer 1 */ -#define SP_TIMER_FREQUENCY 83000000 #define SP_TIMER_BASE DDB_SPT1CTRL_L -#define SP_TIMER_IRQ (8 + 6) -#endif +#define SP_TIMER_IRQ VRC5477_IRQ_SPT1 + +static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000; static void ddb_machine_restart(char *command) { @@ -61,7 +63,7 @@ static void ddb_machine_restart(char *co /* CPU cold reset */ t = ddb_in32(DDB_CPUSTAT); - MIPS_ASSERT((t&1)); + db_assert((t&1)); ddb_out32(DDB_CPUSTAT, t); /* Call the PROM */ @@ -81,44 +83,89 @@ static void ddb_machine_power_off(void) } extern void rtc_ds1386_init(unsigned long base); + +static unsigned int __init detect_bus_frequency(unsigned long rtc_base) +{ + unsigned int freq; + unsigned char c; + unsigned int t1, t2; + unsigned i; + + ddb_out32(SP_TIMER_BASE, 0xffffffff); + ddb_out32(SP_TIMER_BASE+4, 0x1); + ddb_out32(SP_TIMER_BASE+8, 0xffffffff); + + /* check if rtc is running */ + c= *(volatile unsigned char*)rtc_base; + for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++); + if (c == *(volatile unsigned char*)rtc_base) { + printk("Failed to detect bus frequency. Use default 83.3MHz.\n"); + return 83333000; + } + + c= *(volatile unsigned char*)rtc_base; + while (c == *(volatile unsigned char*)rtc_base); + /* we are now at the turn of 1/100th second, if no error. */ + t1 = ddb_in32(SP_TIMER_BASE+8); + + for (i=0; i< 10; i++) { + c= *(volatile unsigned char*)rtc_base; + while (c == *(volatile unsigned char*)rtc_base); + /* we are now at the turn of another 1/100th second */ + t2 = ddb_in32(SP_TIMER_BASE+8); + } + + ddb_out32(SP_TIMER_BASE+4, 0x0); /* disable it again */ + + freq = (t1 - t2)*10; + printk("DDB bus frequency detection : %u \n", freq); + return freq; +} + static void __init ddb_time_init(void) { -#if defined(USE_CPU_COUNTER_TIMER) - mips_counter_frequency = CPU_COUNTER_FREQUENCY; -#endif + unsigned long rtc_base; + unsigned int i; /* we have ds1396 RTC chip */ - rtc_ds1386_init(KSEG1ADDR(DDB_LCS1_BASE)); + if (mips_machtype == MACH_NEC_ROCKHOPPER + || mips_machtype == MACH_NEC_ROCKHOPPERII) { + rtc_base = KSEG1ADDR(DDB_LCS2_BASE); + } else { + rtc_base = KSEG1ADDR(DDB_LCS1_BASE); + } + rtc_ds1386_init(rtc_base); + + /* do we need to do run-time detection of bus speed? */ + if (bus_frequency == 0) { + bus_frequency = detect_bus_frequency(rtc_base); + } + + /* mips_counter_frequency is 1/2 of the cpu core freq */ + i = (read_32bit_cp0_register(CP0_CONFIG) >> 28 ) & 7; + if ((current_cpu_data.cputype == CPU_R5432) && (i == 3)) + i = 4; + mips_counter_frequency = bus_frequency*(i+4)/4; } -#if defined(CONFIG_LL_DEBUG) -int board_init_done_flag = 0; -#endif - extern int setup_irq(unsigned int irq, struct irqaction *irqaction); + static void __init ddb_timer_setup(struct irqaction *irq) { #if defined(USE_CPU_COUNTER_TIMER) unsigned int count; /* we are using the cpu counter for timer interrupts */ - setup_irq(7, irq); - - /* to generate the first timer interrupt */ - count = read_32bit_cp0_register(CP0_COUNT); - write_32bit_cp0_register(CP0_COMPARE, count + 1000); + setup_irq(CPU_IRQ_BASE + 7, irq); #else - /* if we don't use Special purpose timer 1 */ - ddb_out32(SP_TIMER_BASE, SP_TIMER_FREQUENCY/HZ); + /* if we use Special purpose timer 1 */ + ddb_out32(SP_TIMER_BASE, bus_frequency/HZ); ddb_out32(SP_TIMER_BASE+4, 0x1); setup_irq(SP_TIMER_IRQ, irq); #endif - - /* this is the last board dependent code */ - MIPS_DEBUG(board_init_done_flag = 1); } static void ddb5477_board_init(void); @@ -126,14 +173,20 @@ extern void ddb5477_irq_setup(void); #if defined(CONFIG_BLK_DEV_INITRD) extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end; -#endif +#endif void __init ddb_setup(void) { extern int panic_timeout; +#ifdef CONFIG_BLK_DEV_IDE + extern struct ide_ops std_ide_ops; +#endif + + /* initialize board - we don't trust the loader */ + ddb5477_board_init(); irq_setup = ddb5477_irq_setup; - mips_io_port_base = KSEG1ADDR(DDB_PCI_IO_BASE); + set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE)); board_time_init = ddb_time_init; board_timer_setup = ddb_timer_setup; @@ -145,47 +198,69 @@ void __init ddb_setup(void) /* setup resource limits */ ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1; iomem_resource.end = 0xffffffff; - + /* Reboot on panic */ panic_timeout = 180; - /* initialize board - we don't trust the loader */ - ddb5477_board_init(); +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &std_ide_ops; +#endif + + +#ifdef CONFIG_FB + conswitchp = &dummy_con; +#endif #if defined(CONFIG_BLK_DEV_INITRD) ROOT_DEV = Root_RAM0; initrd_start = (unsigned long)&__rd_start; initrd_end = (unsigned long)&__rd_end; #endif - } -static void __init ddb5477_board_init() +static void __init ddb5477_board_init(void) { +#ifdef CONFIG_PC_KEYB + extern struct kbd_ops std_kbd_ops; +#endif /* ----------- setup PDARs ------------ */ /* SDRAM should have been set */ - MIPS_ASSERT(ddb_in32(DDB_SDRAM0) == - ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1)); + db_assert(ddb_in32(DDB_SDRAM0) == + ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1)); /* SDRAM1 should be turned off. What is this for anyway ? */ - MIPS_ASSERT( (ddb_in32(DDB_SDRAM1) & 0xf) == 0); + db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0); - /* Set LDCSs */ - /* flash */ + /* Setup local bus. */ + + /* Flash U12 PDAR and timing. */ ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0); - /* misc */ - ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0); - /* mezzanie (?) */ - ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0); + ddb_out32(DDB_LCST0, 0x00090842); + + /* We need to setup LCS1 and LCS2 differently based on the + board_version */ + if (mips_machtype == MACH_NEC_ROCKHOPPER) { + /* Flash U13 PDAR and timing. */ + ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0); + ddb_out32(DDB_LCST1, 0x00090842); + + /* EPLD (NVRAM, switch, LCD, and mezzanie). */ + ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0); + } else { + /* misc */ + ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0); + /* mezzanie (?) */ + ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0); + } /* verify VRC5477 base addr */ - MIPS_ASSERT(ddb_in32(DDB_VRC5477) == - ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1)); - + db_assert(ddb_in32(DDB_VRC5477) == + ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1)); + /* verify BOOT ROM addr */ - MIPS_ASSERT(ddb_in32(DDB_BOOTCS) == - ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0)); + db_assert(ddb_in32(DDB_BOOTCS) == + ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0)); /* setup PCI windows - window0 for MEM/config, window1 for IO */ ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1); @@ -219,7 +294,7 @@ static void __init ddb5477_board_init() ddb_out32(DDB_BAR51, 0xffffffff); ddb_out32(DDB_BARB1, 0xffffffff); - /* + /* * We use pci master register 0 for memory space / config space * And we use register 1 for IO space. * Note that for memory space, we bump up the pci base address @@ -227,26 +302,133 @@ static void __init ddb5477_board_init() * For PCI IO space, it starts from 0 in PCI IO space but with * DDB_xx_IO_BASE in CPU physical address space. */ - ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE, + ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE, DDB_PCI_ACCESS_32); ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32); - ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE, + ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE, DDB_PCI_ACCESS_32); - ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE, + ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE, DDB_PCI_ACCESS_32); - + /* PCI cross window should be set properly */ ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1); ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1); ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1); ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1); + if (mips_machtype == MACH_NEC_ROCKHOPPER + || mips_machtype == MACH_NEC_ROCKHOPPERII) { + /* Disable bus diagnostics. */ + ddb_out32(DDB_PCICTL0_L, 0); + ddb_out32(DDB_PCICTL0_H, 0); + ddb_out32(DDB_PCICTL1_L, 0); + ddb_out32(DDB_PCICTL1_H, 0); + } + + if (mips_machtype == MACH_NEC_ROCKHOPPER) { + u16 vid; + struct pci_bus bus; + struct pci_dev dev_m1533; + extern struct pci_ops ddb5477_ext_pci_ops; + + bus.parent = NULL; /* we scan the top level only */ + bus.ops = &ddb5477_ext_pci_ops; + dev_m1533.bus = &bus; + dev_m1533.sysdata = NULL; + dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge. + pci_read_config_word(&dev_m1533, 0, &vid); + if (vid == PCI_VENDOR_ID_AL) { + printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n"); + mips_machtype = MACH_NEC_ROCKHOPPERII; + } + } + /* enable USB input buffers */ ddb_out32(DDB_PIBMISC, 0x00000007); /* For dual-function pins, make them all non-GPIO */ ddb_out32(DDB_GIUFUNSEL, 0x0); // ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */ + + if (mips_machtype == MACH_NEC_ROCKHOPPERII) { +#ifdef CONFIG_PC_KEYB + printk("kdb_ops is std\n"); + kbd_ops = &std_kbd_ops; +#endif + } + + if (mips_machtype == MACH_NEC_ROCKHOPPERII) { + + /* enable IDE controller on Ali chip (south bridge) */ + u8 temp8; + struct pci_bus bus; + struct pci_dev dev_m1533; + struct pci_dev dev_m5229; + extern struct pci_ops ddb5477_ext_pci_ops; + + /* Setup M1535 registers */ + bus.parent = NULL; /* we scan the top level only */ + bus.ops = &ddb5477_ext_pci_ops; + dev_m1533.bus = &bus; + dev_m1533.sysdata = NULL; + dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge. + + /* setup IDE controller + * enable IDE controller (bit 6 - 1) + * IDE IDSEL to be addr:A15 (bit 4:5 - 11) + * disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0) + * enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1) + */ + pci_write_config_byte(&dev_m1533, 0x58, 0x74); + + /* + * positive decode (bit6 -0) + * enable IDE controler interrupt (bit 4 -1) + * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101) + */ + pci_write_config_byte(&dev_m1533, 0x44, 0x1d); + + /* Setup M5229 registers */ + dev_m5229.bus = &bus; + dev_m5229.sysdata = NULL; + dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE + + /* + * enable IDE in the M5229 config register 0x50 (bit 0 - 1) + * M5229 IDSEL is addr:15; see above setting + */ + pci_read_config_byte(&dev_m5229, 0x50, &temp8); + pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1); + + /* + * enable bus master (bit 2) and IO decoding (bit 0) + */ + pci_read_config_byte(&dev_m5229, 0x04, &temp8); + pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5); + + /* + * enable native, copied from arch/ppc/k2boot/head.S + * TODO - need volatile, need to be portable + */ + pci_write_config_byte(&dev_m5229, 0x09, 0xef); + + /* Set Primary Channel Command Block Timing */ + pci_write_config_byte(&dev_m5229, 0x59, 0x31); + + /* + * Enable primary channel 40-pin cable + * M5229 register 0x4a (bit 0) + */ + pci_read_config_byte(&dev_m5229, 0x4a, &temp8); + pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1); + } + + if (mips_machtype == MACH_NEC_ROCKHOPPER + || mips_machtype == MACH_NEC_ROCKHOPPERII) { + printk("lcd44780: initializing\n"); + lcd44780_init(); + lcd44780_puts("MontaVista Linux"); + } } --- linux-2.5.73/arch/mips/dec/boot/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/boot/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -3,8 +3,8 @@ # netboot: all - mipsel-linux-ld -N -G 0 -T ld.ecoff ../../boot/zImage \ - built-in.o ramdisk.img -o nbImage + $(LD) -N -G 0 -T ld.ecoff ../../boot/zImage \ + dec_boot.o ramdisk.img -o nbImage obj-y := decstation.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/dec/ecc-berr.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,280 @@ +/* + * linux/arch/mips/dec/ecc-berr.c + * + * Bus error event handling code for systems equipped with ECC + * handling logic, i.e. DECstation/DECsystem 5000/200 (KN02), + * 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03), + * 5900/260 (KN05) systems. + * + * Copyright (c) 2003 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static volatile u32 *kn0x_erraddr; +static volatile u32 *kn0x_chksyn; + +static inline void dec_ecc_be_ack(void) +{ + *kn0x_erraddr = 0; /* any write clears the IRQ */ + iob(); +} + +static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker) +{ + static const char excstr[] = "exception"; + static const char intstr[] = "interrupt"; + static const char cpustr[] = "CPU"; + static const char dmastr[] = "DMA"; + static const char readstr[] = "read"; + static const char mreadstr[] = "memory read"; + static const char writestr[] = "write"; + static const char mwritstr[] = "partial memory write"; + static const char timestr[] = "timeout"; + static const char overstr[] = "overrun"; + static const char eccstr[] = "ECC error"; + + const char *kind, *agent, *cycle, *event; + const char *status = "", *xbit = "", *fmt = ""; + dma_addr_t address; + u16 syn = 0, sngl; + + int i = 0; + + u32 erraddr = *kn0x_erraddr; + u32 chksyn = *kn0x_chksyn; + int action = MIPS_BE_FATAL; + + /* For non-ECC ack ASAP, so any subsequent errors get caught. */ + if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID) + dec_ecc_be_ack(); + + kind = invoker ? intstr : excstr; + + if (!(erraddr & KN0X_EAR_VALID)) { + /* No idea what happened. */ + printk(KERN_ALERT "Unindentified bus error %s.\n", kind); + return action; + } + + agent = (erraddr & KN0X_EAR_CPU) ? cpustr : dmastr; + + if (erraddr & KN0X_EAR_ECCERR) { + /* An ECC error on a CPU or DMA transaction. */ + cycle = (erraddr & KN0X_EAR_WRITE) ? mwritstr : mreadstr; + event = eccstr; + } else { + /* A CPU timeout or a DMA overrun. */ + cycle = (erraddr & KN0X_EAR_WRITE) ? writestr : readstr; + event = (erraddr & KN0X_EAR_CPU) ? timestr : overstr; + } + + address = erraddr & KN0X_EAR_ADDRESS; + /* For ECC errors on reads adjust for MT pipelining. */ + if ((erraddr & (KN0X_EAR_WRITE | KN0X_EAR_ECCERR)) == KN0X_EAR_ECCERR) + address = (address & ~0xfffLL) | ((address - 5) & 0xfffLL); + address <<= 2; + + /* Only CPU errors are fixable. */ + if (erraddr & KN0X_EAR_CPU && is_fixup) + action = MIPS_BE_FIXUP; + + if (erraddr & KN0X_EAR_ECCERR) { + static const u8 data_sbit[32] = { + 0x4f, 0x4a, 0x52, 0x54, 0x57, 0x58, 0x5b, 0x5d, + 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c, 0x31, 0x34, + 0x0e, 0x0b, 0x13, 0x15, 0x16, 0x19, 0x1a, 0x1c, + 0x62, 0x64, 0x67, 0x68, 0x6b, 0x6d, 0x70, 0x75, + }; + static const u8 data_mbit[25] = { + 0x07, 0x0d, 0x1f, + 0x2f, 0x32, 0x37, 0x38, 0x3b, 0x3d, 0x3e, + 0x43, 0x45, 0x46, 0x49, 0x4c, 0x51, 0x5e, + 0x61, 0x6e, 0x73, 0x76, 0x79, 0x7a, 0x7c, 0x7f, + }; + static const char sbestr[] = "corrected single"; + static const char dbestr[] = "uncorrectable double"; + static const char mbestr[] = "uncorrectable multiple"; + + if (!(address & 0x4)) + syn = chksyn; /* Low bank. */ + else + syn = chksyn >> 16; /* High bank. */ + + if (!(syn & KN0X_ESR_VLDLO)) { + /* Ack now, no rewrite will happen. */ + dec_ecc_be_ack(); + + fmt = KERN_ALERT "%s" "invalid.\n"; + } else { + sngl = syn & KN0X_ESR_SNGLO; + syn &= KN0X_ESR_SYNLO; + + /* + * Multibit errors may be tagged incorrectly; + * check the syndrome explicitly. + */ + for (i = 0; i < 25; i++) + if (syn == data_mbit[i]) + break; + + if (i < 25) { + status = mbestr; + } else if (!sngl) { + status = dbestr; + } else { + volatile u32 *ptr = (void *)KSEG1ADDR(address); + + *ptr = *ptr; /* Rewrite. */ + iob(); + + status = sbestr; + action = MIPS_BE_DISCARD; + } + + /* Ack now, now we've rewritten (or not). */ + dec_ecc_be_ack(); + + if (syn && syn == (syn & -syn)) { + if (syn == 0x01) { + fmt = KERN_ALERT "%s" + "%#04x -- %s bit error " + "at check bit C%s.\n"; + xbit = "X"; + } else { + fmt = KERN_ALERT "%s" + "%#04x -- %s bit error " + "at check bit C%s%u.\n"; + } + i = syn >> 2; + } else { + for (i = 0; i < 32; i++) + if (syn == data_sbit[i]) + break; + if (i < 32) + fmt = KERN_ALERT "%s" + "%#04x -- %s bit error " + "at data bit D%s%u.\n"; + else + fmt = KERN_ALERT "%s" + "%#04x -- %s bit error.\n"; + } + } + } + + if (action != MIPS_BE_FIXUP) + printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx.\n", + kind, agent, cycle, event, address); + + if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR) + printk(fmt, " ECC syndrome ", syn, status, xbit, i); + + return action; +} + +int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup) +{ + return dec_ecc_be_backend(regs, is_fixup, 0); +} + +void dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + int action = dec_ecc_be_backend(regs, 0, 1); + + if (action == MIPS_BE_DISCARD) + return; + + /* + * FIXME: Find affected processes and kill them, otherwise we + * must die. + * + * The interrupt is asynchronously delivered thus EPC and RA + * may be irrelevant, but are printed for a reference. + */ + printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n", + regs->cp0_epc, regs->regs[31]); + die("Unrecoverable bus error", regs); +} + + +/* + * Initialization differs a bit between KN02 and KN03/KN05, so we + * need two variants. Once set up, all systems can be handled the + * same way. + */ +static inline void dec_kn02_be_init(void) +{ + volatile u32 *csr = (void *)KN02_CSR_BASE; + unsigned long flags; + + kn0x_erraddr = (void *)(KN02_SLOT_BASE + KN02_ERRADDR); + kn0x_chksyn = (void *)(KN02_SLOT_BASE + KN02_CHKSYN); + + spin_lock_irqsave(&kn02_lock, flags); + + /* Preset write-only bits of the Control Register cache. */ + cached_kn02_csr = *csr | KN03_CSR_LEDS; + + /* Set normal ECC detection and generation. */ + cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN); + /* Enable ECC correction. */ + cached_kn02_csr |= KN02_CSR_CORRECT; + *csr = cached_kn02_csr; + iob(); + + spin_unlock_irqrestore(&kn02_lock, flags); +} + +static inline void dec_kn03_be_init(void) +{ + volatile u32 *mcr = (void *)(KN03_SLOT_BASE + IOASIC_MCR); + volatile u32 *mbcs = (void *)(KN03_SLOT_BASE + KN05_MB_CSR); + + kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); + kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); + + /* + * Set normal ECC detection and generation, enable ECC correction. + * For KN05 we also need to make sure EE (?) is enabled in the MB. + * Otherwise DBE/IBE exceptions would be masked but bus error + * interrupts would still arrive, resulting in an inevitable crash + * if get_dbe() triggers one. + */ + *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) | + KN03_MCR_CORRECT; + if (current_cpu_data.cputype == CPU_R4400SC) + *mbcs |= KN05_MB_CSR_EE; + fast_iob(); +} + +void __init dec_ecc_be_init(void) +{ + if (mips_machtype == MACH_DS5000_200) + dec_kn02_be_init(); + else + dec_kn03_be_init(); + + /* Clear any leftover errors from the firmware. */ + dec_ecc_be_ack(); +} --- linux-2.5.73/arch/mips/dec/int-handler.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/int-handler.S 2003-06-27 15:56:23.000000000 -0700 @@ -2,7 +2,7 @@ * arch/mips/dec/int-handler.S * * Copyright (C) 1995, 1996, 1997 Paul M. Antoine and Harald Koerfgen - * Copyright (C) 2000 Maciej W. Rozycki + * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki * * Written by Ralf Baechle and Andreas Busse, modified for DECStation * support by Paul Antoine and Harald Koerfgen. @@ -10,6 +10,8 @@ * completly rewritten: * Copyright (C) 1998 Harald Koerfgen * + * Rewritten extensively for controller-driven IRQ support + * by Maciej W. Rozycki. */ #include #include @@ -17,12 +19,13 @@ #include #include +#include +#include +#include #include #include #include #include -#include -#include .text @@ -84,7 +87,7 @@ * 4 TurboChannel Slot 2 * 5 TurboChannel Slot 3 (ASIC) * 6 Halt button - * 7 FPU + * 7 FPU/R4k timer * * DS5000/2x's, aka kn02ca, aka maxine: * @@ -97,7 +100,7 @@ * 4 I/O write timeout * 5 TurboChannel (ASIC) * 6 Halt Keycode from Access.Bus keyboard (CTRL-ALT-ENTER) - * 7 FPU + * 7 FPU/R4k timer * * DS5000/2xx's, aka kn03, aka 3maxplus: * @@ -110,22 +113,11 @@ * 4 Reserved * 5 Memory * 6 Halt Button - * 7 FPU - * - * We handle the IRQ according to _our_ priority. - * Priority is: - * - * Highest ---- RTC - * SCSI (if separate from TC) - * Ethernet (if separate from TC) - * Serial (if separate from TC) - * TurboChannel (if there is one!) - * Memory Controller (execept kmin) - * Lowest ---- Halt (if there is one!) - * - * then we just return, if multiple IRQs are pending then we will just take - * another exception, big deal. + * 7 FPU/R4k timer * + * We handle the IRQ according to _our_ priority (see setup.c), + * then we just return. If multiple IRQs are pending then we will + * just take another exception, big deal. */ .align 5 NESTED(decstation_handle_int, PT_SIZE, ra) @@ -139,226 +131,166 @@ * Get pending Interrupts */ mfc0 t0,CP0_CAUSE # get pending interrupts - mfc0 t2,CP0_STATUS - la t1,cpu_mask_tbl - and t0,t2 # isolate allowed ones + mfc0 t1,CP0_STATUS +#ifdef CONFIG_MIPS32 + lw t2,cpu_fpu_mask +#endif + andi t0,ST0_IM # CAUSE.CE may be non-zero! + and t0,t1 # isolate allowed ones beqz t0,spurious +#ifdef CONFIG_MIPS32 + and t2,t0 + bnez t2,fpu # handle FPU immediately +#endif + /* * Find irq with highest priority */ -1: lw t2,(t1) - move t3,t0 - and t3,t2 - beq t3,zero,1b - addu t1,PTRSIZE # delay slot + PTR_LA t1,cpu_mask_nr_tbl +1: lw t2,(t1) + nop + and t2,t0 + beqz t2,1b + addu t1,2*PTRSIZE # delay slot /* * Do the low-level stuff */ - lw a0,%lo(cpu_irq_nr-cpu_mask_tbl-PTRSIZE)(t1) - lw t0,%lo(cpu_ivec_tbl-cpu_mask_tbl-PTRSIZE)(t1) - bgez a0, handle_it # irq_nr >= 0? - # irq_nr < 0: t0 contains an address + lw a0,(-PTRSIZE)(t1) + nop + bgez a0,handle_it # irq_nr >= 0? + # irq_nr < 0: it is an address nop - jr t0 - nop # delay slot + jr a0 + # a trick to save a branch: + lui t2,(KN03_IOASIC_BASE>>16)&0xffff + # upper part of IOASIC Address /* * Handle "IRQ Controller" Interrupts * Masked Interrupts are still visible and have to be masked "by hand". */ - EXPORT(kn02_io_int) -kn02_io_int: # 3max - lui t0,KN02_CSR_ADDR>>16 # get interrupt status and mask + FEXPORT(kn02_io_int) # 3max + lui t0,(KN02_CSR_BASE>>16)&0xffff + # get interrupt status and mask lw t0,(t0) - la t1,asic_mask_tbl - move t3,t0 - sll t3,16 # shift interrupt status - b find_int - and t0,t3 # mask out allowed ones - - EXPORT(kn03_io_int) -kn03_io_int: # 3max+ - lui t2,KN03_IOASIC_BASE>>16 # upper part of IOASIC Address - lw t0,SIR(t2) # get status: IOASIC isr - lw t3,SIMR(t2) # get mask: IOASIC isrm - la t1,asic_mask_tbl - b find_int - and t0,t3 # mask out allowed ones - - EXPORT(kn02xa_io_int) -kn02xa_io_int: # 3min/maxine - lui t2,KN02XA_IOASIC_BASE>>16 + nop + andi t1,t0,KN02_IRQ_ALL + b 1f + srl t0,16 # shift interrupt mask + + FEXPORT(kn02xa_io_int) # 3min/maxine + lui t2,(KN02XA_IOASIC_BASE>>16)&0xffff # upper part of IOASIC Address - lw t0,SIR(t2) # get status: IOASIC isr - lw t3,SIMR(t2) # get mask: IOASIC isrm - la t1,asic_mask_tbl - and t0,t3 + + FEXPORT(kn03_io_int) # 3max+ (t2 loaded earlier) + lw t0,IO_REG_SIR(t2) # get status: IOASIC sir + lw t1,IO_REG_SIMR(t2) # get mask: IOASIC simr + nop + +1: and t0,t1 # mask out allowed ones + + beqz t0,spurious /* * Find irq with highest priority */ -find_int: beqz t0,spurious - -1: lw t2,(t1) - move t3,t0 - and t3,t2 - beq zero,t3,1b - addu t1,PTRSIZE # delay slot + PTR_LA t1,asic_mask_nr_tbl +2: lw t2,(t1) + nop + and t2,t0 + beq zero,t2,2b + addu t1,2*PTRSIZE # delay slot /* * Do the low-level stuff */ - lw a0,%lo(asic_irq_nr-asic_mask_tbl-PTRSIZE)(t1) - nop + lw a0,%lo(-PTRSIZE)(t1) + nop + bgez a0,handle_it # irq_nr >= 0? + # irq_nr < 0: it is an address + nop + jr a0 + nop # delay slot + +/* + * Dispatch low-priority interrupts. We reconsider all status + * bits again, which looks like a lose, but it makes the code + * simple and O(log n), so it gets compensated. + */ + FEXPORT(cpu_all_int) # HALT, timers, software junk + li a0,DEC_CPU_IRQ_BASE + srl t0,CAUSEB_IP + li t1,CAUSEF_IP>>CAUSEB_IP # mask + b 1f + li t2,4 # nr of bits / 2 + + FEXPORT(kn02_all_int) # impossible ? + li a0,KN02_IRQ_BASE + li t1,KN02_IRQ_ALL # mask + b 1f + li t2,4 # nr of bits / 2 + + FEXPORT(asic_all_int) # various I/O ASIC junk + li a0,IO_IRQ_BASE + li t1,IO_IRQ_ALL # mask + b 1f + li t2,8 # nr of bits / 2 + +/* + * Dispatch DMA interrupts -- O(log n). + */ + FEXPORT(asic_dma_int) # I/O ASIC DMA events + li a0,IO_IRQ_BASE+IO_INR_DMA + srl t0,IO_INR_DMA + li t1,IO_IRQ_DMA>>IO_INR_DMA # mask + li t2,8 # nr of bits / 2 + + /* + * Find irq with highest priority. + * Highest irq number takes precedence. + */ +1: srlv t3,t1,t2 +2: xor t1,t3 + and t3,t0,t1 + beqz t3,3f + nop + move t0,t3 + addu a0,t2 +3: srl t2,1 + bnez t2,2b + srlv t3,t1,t2 -handle_it: jal do_IRQ +handle_it: + jal do_IRQ move a1,sp + j ret_from_irq nop +#ifdef CONFIG_MIPS32 +fpu: + j handle_fpe_int + nop +#endif + spurious: j spurious_interrupt nop END(decstation_handle_int) -/* - * Interrupt routines common to all DECStations first. - */ - EXPORT(dec_intr_fpu) -dec_intr_fpu: PANIC("Unimplemented FPU interrupt handler") /* - * Generic unimplemented interrupt routines - ivec_tbl is initialised to - * point all interrupts here. The table is then filled in by machine-specific - * initialisation in dec_setup(). + * Generic unimplemented interrupt routines -- cpu_mask_nr_tbl + * and asic_mask_nr_tbl are initialized to point all interrupts here. + * The tables are then filled in by machine-specific initialisation + * in dec_setup(). */ - EXPORT(dec_intr_unimplemented) -dec_intr_unimplemented: - mfc0 a1,CP0_CAUSE # cheats way of printing an arg! - nop # to be sure... - PANIC("Unimplemented cpu interrupt! CP0_CAUSE: 0x%x"); - - EXPORT(asic_intr_unimplemented) -asic_intr_unimplemented: + FEXPORT(dec_intr_unimplemented) move a1,t0 # cheats way of printing an arg! - PANIC("Unimplemented asic interrupt! ASIC ISR: 0x%x"); + PANIC("Unimplemented cpu interrupt! CP0_CAUSE: 0x%08x"); -/* - * FIXME: This interrupt vector table is experimental. It is initialised with - * *_intr_unimplemented and filled in with the addresses of - * machine-specific interrupt routines in dec_setup() Paul 10/5/97. - * - * The mask_tbls contain the interrupt masks which are used. It is - * initialised with all possible interrupt status bits set, so that - * unused Interrupts are catched. Harald - */ - .data - EXPORT(cpu_mask_tbl) -cpu_mask_tbl: - .word 0x00000000 - .word 0x00000000 - .word 0x00000000 - .word 0x00000000 - .word 0x00000000 - .word 0x00000000 - .word 0x00000000 # these two are unlikely - .word 0x00000000 # to be used - .word 0x0000ff00 # End of list - - EXPORT(cpu_irq_nr) -cpu_irq_nr: - .word 0x00000000 - .word 0x00000000 - .word 0x00000000 - .word 0x00000000 - .word 0x00000000 - .word 0x00000000 - .word 0x00000000 # these two are unlikely - .word 0x00000000 # to be used - .word 0x00ffffff # End of list - - EXPORT(cpu_ivec_tbl) -cpu_ivec_tbl: - PTR dec_intr_unimplemented - PTR dec_intr_unimplemented - PTR dec_intr_unimplemented - PTR dec_intr_unimplemented - PTR dec_intr_unimplemented - PTR dec_intr_unimplemented - PTR dec_intr_unimplemented # these two are unlikely - PTR dec_intr_unimplemented # to be used - PTR dec_intr_unimplemented # EOL - - EXPORT(asic_mask_tbl) -asic_mask_tbl: - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0xffffffff # EOL - - EXPORT(asic_irq_nr) -asic_irq_nr: - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0xffffffff # EOL + FEXPORT(asic_intr_unimplemented) + move a1,t0 # cheats way of printing an arg! + PANIC("Unimplemented asic interrupt! ASIC ISR: 0x%08x"); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/dec/ioasic-irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,157 @@ +/* + * linux/arch/mips/dec/ioasic-irq.c + * + * DEC I/O ASIC interrupts. + * + * Copyright (c) 2002, 2003 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include + +#include +#include +#include + + +static spinlock_t ioasic_lock = SPIN_LOCK_UNLOCKED; + +static int ioasic_irq_base; + + +static inline void unmask_ioasic_irq(unsigned int irq) +{ + u32 simr; + + simr = ioasic_read(IO_REG_SIMR); + simr |= (1 << (irq - ioasic_irq_base)); + ioasic_write(IO_REG_SIMR, simr); +} + +static inline void mask_ioasic_irq(unsigned int irq) +{ + u32 simr; + + simr = ioasic_read(IO_REG_SIMR); + simr &= ~(1 << (irq - ioasic_irq_base)); + ioasic_write(IO_REG_SIMR, simr); +} + +static inline void clear_ioasic_irq(unsigned int irq) +{ + u32 sir; + + sir = ~(1 << (irq - ioasic_irq_base)); + ioasic_write(IO_REG_SIR, sir); +} + +static inline void enable_ioasic_irq(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&ioasic_lock, flags); + unmask_ioasic_irq(irq); + spin_unlock_irqrestore(&ioasic_lock, flags); +} + +static inline void disable_ioasic_irq(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&ioasic_lock, flags); + mask_ioasic_irq(irq); + spin_unlock_irqrestore(&ioasic_lock, flags); +} + + +static inline unsigned int startup_ioasic_irq(unsigned int irq) +{ + enable_ioasic_irq(irq); + return 0; +} + +#define shutdown_ioasic_irq disable_ioasic_irq + +static inline void ack_ioasic_irq(unsigned int irq) +{ + spin_lock(&ioasic_lock); + mask_ioasic_irq(irq); + spin_unlock(&ioasic_lock); + fast_iob(); +} + +static inline void end_ioasic_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + enable_ioasic_irq(irq); +} + +static struct hw_interrupt_type ioasic_irq_type = { + .typename = "IO-ASIC", + .startup = startup_ioasic_irq, + .shutdown = shutdown_ioasic_irq, + .enable = enable_ioasic_irq, + .disable = disable_ioasic_irq, + .ack = ack_ioasic_irq, + .end = end_ioasic_irq, +}; + + +#define startup_ioasic_dma_irq startup_ioasic_irq + +#define shutdown_ioasic_dma_irq shutdown_ioasic_irq + +#define enable_ioasic_dma_irq enable_ioasic_irq + +#define disable_ioasic_dma_irq disable_ioasic_irq + +#define ack_ioasic_dma_irq ack_ioasic_irq + +static inline void end_ioasic_dma_irq(unsigned int irq) +{ + clear_ioasic_irq(irq); + fast_iob(); + end_ioasic_irq(irq); +} + +static struct hw_interrupt_type ioasic_dma_irq_type = { + .typename = "IO-ASIC-DMA", + .startup = startup_ioasic_dma_irq, + .shutdown = shutdown_ioasic_dma_irq, + .enable = enable_ioasic_dma_irq, + .disable = disable_ioasic_dma_irq, + .ack = ack_ioasic_dma_irq, + .end = end_ioasic_dma_irq, +}; + + +void __init init_ioasic_irqs(int base) +{ + int i; + + /* Mask interrupts. */ + ioasic_write(IO_REG_SIMR, 0); + fast_iob(); + + for (i = base; i < base + IO_INR_DMA; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &ioasic_irq_type; + } + for (; i < base + IO_IRQ_LINES; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &ioasic_dma_irq_type; + } + + ioasic_irq_base = base; +} --- linux-2.5.73/arch/mips/dec/irq.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,302 +0,0 @@ -/* - * Code to handle DECstation IRQs plus some generic interrupt stuff. - * - * Copyright (C) 1992 Linus Torvalds - * Copyright (C) 1994, 1995, 1996, 1997, 2000 Ralf Baechle - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -extern void dec_init_kn01(void); -extern void dec_init_kn230(void); -extern void dec_init_kn02(void); -extern void dec_init_kn02ba(void); -extern void dec_init_kn02ca(void); -extern void dec_init_kn03(void); - -extern asmlinkage void decstation_handle_int(void); - -unsigned long spurious_count = 0; - -static inline void mask_irq(unsigned int irq_nr) -{ - unsigned int dummy; - - if (dec_interrupt[irq_nr].iemask) { /* This is an ASIC interrupt */ - *imr &= ~dec_interrupt[irq_nr].iemask; - dummy = *imr; - dummy = *imr; - } else /* This is a cpu interrupt */ - change_cp0_status(ST0_IM, read_32bit_cp0_register(CP0_STATUS) & ~dec_interrupt[irq_nr].cpu_mask); -} - -static inline void unmask_irq(unsigned int irq_nr) -{ - unsigned int dummy; - - if (dec_interrupt[irq_nr].iemask) { /* This is an ASIC interrupt */ - *imr |= dec_interrupt[irq_nr].iemask; - dummy = *imr; - dummy = *imr; - } - change_cp0_status(ST0_IM, read_32bit_cp0_register(CP0_STATUS) | dec_interrupt[irq_nr].cpu_mask); -} - -void disable_irq(unsigned int irq_nr) -{ - unsigned long flags; - - save_and_cli(flags); - mask_irq(irq_nr); - restore_flags(flags); -} - -void enable_irq(unsigned int irq_nr) -{ - unsigned long flags; - - save_and_cli(flags); - unmask_irq(irq_nr); - restore_flags(flags); -} - -/* - * Pointers to the low-level handlers: first the general ones, then the - * fast ones, then the bad ones. - */ -extern void interrupt(void); - -static struct irqaction *irq_action[32] = -{ - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL -}; - -int show_interrupts(struct seq_file *p, void *v) -{ - int i; - struct irqaction *action; - unsigned long flags; - - for (i = 0; i < 32; i++) { - local_irq_save(flags); - action = irq_action[i]; - if (!action) - goto skip; - seq_printf(p, "%2d: %8d %c %s", - i, kstat_cpu(0).irqs[i], - (action->flags & SA_INTERRUPT) ? '+' : ' ', - action->name); - for (action = action->next; action; action = action->next) { - seq_printf(p, ",%s %s", - (action->flags & SA_INTERRUPT) ? " +" : "", - action->name); - } - seq_putc(p, '\n'); -skip: - local_irq_restore(flags); - } - return 0; -} - -/* - * do_IRQ handles IRQ's that have been installed without the - * SA_INTERRUPT flag: it uses the full signal-handling return - * and runs with other interrupts enabled. All relatively slow - * IRQ's should use this format: notably the keyboard/timer - * routines. - */ -asmlinkage void do_IRQ(int irq, struct pt_regs *regs) -{ - struct irqaction *action; - int do_random, cpu; - - cpu = smp_processor_id(); - irq_enter(cpu, irq); - kstat_cpu(cpu).irqs[irq]++; - - mask_irq(irq); - action = *(irq + irq_action); - if (action) { - if (!(action->flags & SA_INTERRUPT)) - local_irq_enable(); - action = *(irq + irq_action); - do_random = 0; - do { - do_random |= action->flags; - action->handler(irq, action->dev_id, regs); - action = action->next; - } while (action); - if (do_random & SA_SAMPLE_RANDOM) - add_interrupt_randomness(irq); - local_irq_disable(); - unmask_irq(irq); - } - irq_exit(cpu, irq); - - /* unmasking and bottom half handling is done magically for us. */ -} - -/* - * Idea is to put all interrupts - * in a single table and differenciate them just by number. - */ -int setup_dec_irq(int irq, struct irqaction *new) -{ - int shared = 0; - struct irqaction *old, **p; - unsigned long flags; - - p = irq_action + irq; - if ((old = *p) != NULL) { - /* Can't share interrupts unless both agree to */ - if (!(old->flags & new->flags & SA_SHIRQ)) - return -EBUSY; - - /* Can't share interrupts unless both are same type */ - if ((old->flags ^ new->flags) & SA_INTERRUPT) - return -EBUSY; - - /* add new interrupt at end of irq queue */ - do { - p = &old->next; - old = *p; - } while (old); - shared = 1; - } - if (new->flags & SA_SAMPLE_RANDOM) - rand_initialize_irq(irq); - - save_and_cli(flags); - *p = new; - - if (!shared) { - unmask_irq(irq); - } - restore_flags(flags); - return 0; -} - -int request_irq(unsigned int irq, - void (*handler) (int, void *, struct pt_regs *), - unsigned long irqflags, - const char *devname, - void *dev_id) -{ - int retval; - struct irqaction *action; - - if (irq >= 32) - return -EINVAL; - if (!handler) - return -EINVAL; - - action = (struct irqaction *) kmalloc(sizeof(struct irqaction), GFP_KERNEL); - if (!action) - return -ENOMEM; - - action->handler = handler; - action->flags = irqflags; - action->mask = 0; - action->name = devname; - action->next = NULL; - action->dev_id = dev_id; - - retval = setup_dec_irq(irq, action); - - if (retval) - kfree(action); - return retval; -} - -void free_irq(unsigned int irq, void *dev_id) -{ - struct irqaction *action, **p; - unsigned long flags; - - if (irq > 39) { - printk("Trying to free IRQ%d\n", irq); - return; - } - for (p = irq + irq_action; (action = *p) != NULL; p = &action->next) { - if (action->dev_id != dev_id) - continue; - - /* Found it - now free it */ - save_and_cli(flags); - *p = action->next; - if (!irq[irq_action]) - mask_irq(irq); - restore_flags(flags); - kfree(action); - return; - } - printk("Trying to free free IRQ%d\n", irq); -} - -unsigned long probe_irq_on(void) -{ - /* TODO */ - return 0; -} - -int probe_irq_off(unsigned long irqs) -{ - /* TODO */ - return 0; -} - -void __init init_IRQ(void) -{ - switch (mips_machtype) { - case MACH_DS23100: - dec_init_kn01(); - break; - case MACH_DS5100: /* DS5100 MIPSMATE */ - dec_init_kn230(); - break; - case MACH_DS5000_200: /* DS5000 3max */ - dec_init_kn02(); - break; - case MACH_DS5000_1XX: /* DS5000/100 3min */ - dec_init_kn02ba(); - break; - case MACH_DS5000_2X0: /* DS5000/240 3max+ */ - dec_init_kn03(); - break; - case MACH_DS5000_XX: /* Personal DS5000/2x */ - dec_init_kn02ca(); - break; - case MACH_DS5800: /* DS5800 Isis */ - panic("Don't know how to set this up!"); - break; - case MACH_DS5400: /* DS5400 MIPSfair */ - panic("Don't know how to set this up!"); - break; - case MACH_DS5500: /* DS5500 MIPSfair-2 */ - panic("Don't know how to set this up!"); - break; - } - set_except_vector(0, decstation_handle_int); -} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/dec/kn02-irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,127 @@ +/* + * linux/arch/mips/dec/kn02-irq.c + * + * DECstation 5000/200 (KN02) Control and Status Register + * interrupts. + * + * Copyright (c) 2002, 2003 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include + +#include + + +/* + * Bits 7:0 of the Control Register are write-only -- the + * corresponding bits of the Status Register have a different + * meaning. Hence we use a cache. It speeds up things a bit + * as well. + * + * There is no default value -- it has to be initialized. + */ +u32 cached_kn02_csr; +spinlock_t kn02_lock = SPIN_LOCK_UNLOCKED; + + +static int kn02_irq_base; + + +static inline void unmask_kn02_irq(unsigned int irq) +{ + volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; + + cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16)); + *csr = cached_kn02_csr; +} + +static inline void mask_kn02_irq(unsigned int irq) +{ + volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; + + cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16)); + *csr = cached_kn02_csr; +} + +static inline void enable_kn02_irq(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&kn02_lock, flags); + unmask_kn02_irq(irq); + spin_unlock_irqrestore(&kn02_lock, flags); +} + +static inline void disable_kn02_irq(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&kn02_lock, flags); + mask_kn02_irq(irq); + spin_unlock_irqrestore(&kn02_lock, flags); +} + + +static unsigned int startup_kn02_irq(unsigned int irq) +{ + enable_kn02_irq(irq); + return 0; +} + +#define shutdown_kn02_irq disable_kn02_irq + +static void ack_kn02_irq(unsigned int irq) +{ + spin_lock(&kn02_lock); + mask_kn02_irq(irq); + spin_unlock(&kn02_lock); + iob(); +} + +static void end_kn02_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + enable_kn02_irq(irq); +} + +static struct hw_interrupt_type kn02_irq_type = { + .typename = "KN02-CSR", + .startup = startup_kn02_irq, + .shutdown = shutdown_kn02_irq, + .enable = enable_kn02_irq, + .disable = disable_kn02_irq, + .ack = ack_kn02_irq, + .end = end_kn02_irq, +}; + + +void __init init_kn02_irqs(int base) +{ + volatile u32 *csr = (volatile u32 *)KN02_CSR_BASE; + unsigned long flags; + int i; + + /* Mask interrupts. */ + spin_lock_irqsave(&kn02_lock, flags); + cached_kn02_csr &= ~KN03_CSR_IOINTEN; + *csr = cached_kn02_csr; + iob(); + spin_unlock_irqrestore(&kn02_lock, flags); + + for (i = base; i < base + KN02_IRQ_LINES; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &kn02_irq_type; + } + + kn02_irq_base = base; +} --- linux-2.5.73/arch/mips/dec/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -2,6 +2,10 @@ # Makefile for the DECstation family specific parts of the kernel # -obj-y := int-handler.o setup.o irq.o time.o reset.o rtc-dec.o wbflush.o +obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn02-irq.o reset.o \ + rtc-dec.o setup.o time.o obj-$(CONFIG_PROM_CONSOLE) += promcon.o +obj-$(CONFIG_CPU_HAS_WB) += wbflush.o + +EXTRA_AFLAGS := $(CFLAGS) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/dec/prom/call_o32.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,91 @@ +/* + * arch/mips/dec/call_o32.S + * + * O32 interface for the 64 (or N32) ABI. + * + * Copyright (C) 2002 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include + +/* Maximum number of arguments supported. Must be even! */ +#define O32_ARGC 32 +/* Number of static registers we save. */ +#define O32_STATC 11 +/* Frame size for both of the above. */ +#define O32_FRAMESZ (4 * O32_ARGC + SZREG * O32_STATC) + + .text + +/* + * O32 function call dispatcher, for interfacing 32-bit ROM routines. + * + * The standard 64 (N32) calling sequence is supported, with a0 + * holding a function pointer, a1-a7 -- its first seven arguments + * and the stack -- remaining ones (up to O32_ARGC, including a1-a7). + * Static registers, gp and fp are preserved, v0 holds a result. + * This code relies on the called o32 function for sp and ra + * restoration and thus both this dispatcher and the current stack + * have to be placed in a KSEGx (or KUSEG) address space. Any + * pointers passed have to point to addresses within one of these + * spaces as well. + */ +NESTED(call_o32, O32_FRAMESZ, ra) + REG_SUBU sp,O32_FRAMESZ + + REG_S ra,O32_FRAMESZ-1*SZREG(sp) + REG_S fp,O32_FRAMESZ-2*SZREG(sp) + REG_S gp,O32_FRAMESZ-3*SZREG(sp) + REG_S s7,O32_FRAMESZ-4*SZREG(sp) + REG_S s6,O32_FRAMESZ-5*SZREG(sp) + REG_S s5,O32_FRAMESZ-6*SZREG(sp) + REG_S s4,O32_FRAMESZ-7*SZREG(sp) + REG_S s3,O32_FRAMESZ-8*SZREG(sp) + REG_S s2,O32_FRAMESZ-9*SZREG(sp) + REG_S s1,O32_FRAMESZ-10*SZREG(sp) + REG_S s0,O32_FRAMESZ-11*SZREG(sp) + + move jp,a0 + + sll a0,a1,zero + sll a1,a2,zero + sll a2,a3,zero + sll a3,a4,zero + sw a5,0x10(sp) + sw a6,0x14(sp) + sw a7,0x18(sp) + + PTR_LA t0,O32_FRAMESZ(sp) + PTR_LA t1,0x1c(sp) + li t2,O32_ARGC-7 +1: + lw t3,(t0) + REG_ADDU t0,SZREG + sw t3,(t1) + REG_SUBU t2,1 + REG_ADDU t1,4 + bnez t2,1b + + jalr jp + + REG_L s0,O32_FRAMESZ-11*SZREG(sp) + REG_L s1,O32_FRAMESZ-10*SZREG(sp) + REG_L s2,O32_FRAMESZ-9*SZREG(sp) + REG_L s3,O32_FRAMESZ-8*SZREG(sp) + REG_L s4,O32_FRAMESZ-7*SZREG(sp) + REG_L s5,O32_FRAMESZ-6*SZREG(sp) + REG_L s6,O32_FRAMESZ-5*SZREG(sp) + REG_L s7,O32_FRAMESZ-4*SZREG(sp) + REG_L gp,O32_FRAMESZ-3*SZREG(sp) + REG_L fp,O32_FRAMESZ-2*SZREG(sp) + REG_L ra,O32_FRAMESZ-1*SZREG(sp) + + REG_ADDU sp,O32_FRAMESZ + jr ra +END(call_o32) --- linux-2.5.73/arch/mips/dec/prom/cmdline.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/prom/cmdline.c 2003-06-27 15:56:23.000000000 -0700 @@ -6,32 +6,30 @@ #include #include #include +#include #include - -#include "prom.h" +#include #undef PROM_DEBUG -#ifdef PROM_DEBUG -extern int (*prom_printf)(char *, ...); -#endif - -char arcs_cmdline[COMMAND_LINE_SIZE]; +char arcs_cmdline[CL_SIZE]; -void __init prom_init_cmdline(int argc, char **argv, unsigned long magic) +void __init prom_init_cmdline(s32 argc, s32 *argv, u32 magic) { + char *arg; int start_arg, i; /* * collect args and prepare cmd_line */ - if (magic != REX_PROM_MAGIC) + if (!prom_is_rex(magic)) start_arg = 1; else start_arg = 2; for (i = start_arg; i < argc; i++) { - strcat(arcs_cmdline, argv[i]); + arg = (void *)(long)(argv[i]); + strcat(arcs_cmdline, arg); if (i < (argc - 1)) strcat(arcs_cmdline, " "); } @@ -39,6 +37,4 @@ void __init prom_init_cmdline(int argc, #ifdef PROM_DEBUG prom_printf("arcs_cmdline: %s\n", &(arcs_cmdline[0])); #endif - } - --- linux-2.5.73/arch/mips/dec/promcon.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/promcon.c 2003-06-27 15:56:23.000000000 -0700 @@ -2,7 +2,7 @@ * Wrap-around code for a console using the * DECstation PROM io-routines. * - * Copyright (c) 1998 Harald Koerfgen + * Copyright (c) 1998 Harald Koerfgen */ #include @@ -12,50 +12,45 @@ #include #include -extern int (*prom_getchar) (void); -extern int (*prom_printf) (char *,...); +#include static void prom_console_write(struct console *co, const char *s, unsigned count) { - unsigned i; + unsigned i; - /* - * Now, do each character - */ - for (i = 0; i < count; i++) { - if (*s == 10) - prom_printf("%c", 13); - prom_printf("%c", *s++); - } + /* + * Now, do each character + */ + for (i = 0; i < count; i++) { + if (*s == 10) + prom_printf("%c", 13); + prom_printf("%c", *s++); + } } static int __init prom_console_setup(struct console *co, char *options) { - return 0; -} - -static kdev_t prom_console_device(struct console *c) -{ - return MKDEV(TTY_MAJOR, 64 + c->index); + return 0; } static struct console sercons = { - .name = "ttyS", - .write = prom_console_write, - .device = prom_console_device, - .setup = prom_console_setup, - .flags = CON_PRINTBUFFER, - .index = -1, + .name = "ttyS", + .write = prom_console_write, + .setup = prom_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, }; /* * Register console. */ -long __init prom_console_init(long kmem_start, long kmem_end) +static int __init prom_console_init(void) { - register_console(&sercons); - return kmem_start; + register_console(&sercons); + + return 0; } +console_initcall(prom_console_init); --- linux-2.5.73/arch/mips/dec/prom/identify.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/prom/identify.c 2003-06-27 15:56:23.000000000 -0700 @@ -2,32 +2,104 @@ * identify.c: machine identification code. * * Copyright (C) 1998 Harald Koerfgen and Paul M. Antoine - * - * $Id: identify.c,v 1.2 1999/10/09 00:00:58 ralf Exp $ + * Copyright (C) 2002, 2003 Maciej W. Rozycki */ #include #include +#include #include +#include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include "dectypes.h" -#include "prom.h" - -extern char *(*prom_getenv)(char *); -extern int (*prom_printf)(char *, ...); -extern int (*rex_getsysid)(void); extern unsigned long mips_machgroup; extern unsigned long mips_machtype; -void __init prom_identify_arch (unsigned int magic) +static const char *dec_system_strings[] = { + [MACH_DSUNKNOWN] "unknown DECstation", + [MACH_DS23100] "DECstation 2100/3100", + [MACH_DS5100] "DECsystem 5100", + [MACH_DS5000_200] "DECstation 5000/200", + [MACH_DS5000_1XX] "DECstation 5000/1xx", + [MACH_DS5000_XX] "Personal DECstation 5000/xx", + [MACH_DS5000_2X0] "DECstation 5000/2x0", + [MACH_DS5400] "DECsystem 5400", + [MACH_DS5500] "DECsystem 5500", + [MACH_DS5800] "DECsystem 5800", + [MACH_DS5900] "DECsystem 5900", +}; + +const char *get_system_type(void) +{ +#define STR_BUF_LEN 64 + static char system[STR_BUF_LEN]; + static int called = 0; + + if (called == 0) { + called = 1; + snprintf(system, STR_BUF_LEN, "Digital %s", + dec_system_strings[mips_machtype]); + } + + return system; +} + + +/* + * Setup essential system-specific memory addresses. We need them + * early. Semantically the functions belong to prom/init.c, but they + * are compact enough we want them inlined. --macro + */ +static inline void prom_init_kn01(void) +{ + dec_rtc_base = (void *)KN01_RTC_BASE; + dec_kn_slot_size = KN01_SLOT_SIZE; +} + +static inline void prom_init_kn230(void) +{ + dec_rtc_base = (void *)KN01_RTC_BASE; + dec_kn_slot_size = KN01_SLOT_SIZE; +} + +static inline void prom_init_kn02(void) +{ + dec_rtc_base = (void *)KN02_RTC_BASE; + dec_kn_slot_size = KN02_SLOT_SIZE; +} + +static inline void prom_init_kn02xa(void) { - unsigned char dec_cpunum, dec_firmrev, dec_etc; - int dec_systype; - unsigned long dec_sysid; + ioasic_base = (void *)KN02XA_IOASIC_BASE; + dec_rtc_base = (void *)KN02XA_RTC_BASE; + dec_kn_slot_size = IOASIC_SLOT_SIZE; +} + +static inline void prom_init_kn03(void) +{ + ioasic_base = (void *)KN03_IOASIC_BASE; + dec_rtc_base = (void *)KN03_RTC_BASE; + dec_kn_slot_size = IOASIC_SLOT_SIZE; +} - if (magic != REX_PROM_MAGIC) { + +void __init prom_identify_arch(u32 magic) +{ + unsigned char dec_cpunum, dec_firmrev, dec_etc, dec_systype; + u32 dec_sysid; + + if (!prom_is_rex(magic)) { dec_sysid = simple_strtoul(prom_getenv("systype"), (char **)0, 0); } else { dec_sysid = rex_getsysid(); @@ -49,50 +121,52 @@ void __init prom_identify_arch (unsigned * FIXME: This may not be an exhaustive list of DECStations/Servers! * Put all model-specific initialisation calls here. */ - prom_printf("This DECstation is a "); - switch (dec_systype) { case DS2100_3100: - prom_printf("DS2100/3100\n"); mips_machtype = MACH_DS23100; + prom_init_kn01(); break; case DS5100: /* DS5100 MIPSMATE */ - prom_printf("DS5100\n"); mips_machtype = MACH_DS5100; + prom_init_kn230(); break; case DS5000_200: /* DS5000 3max */ - prom_printf("DS5000/200\n"); mips_machtype = MACH_DS5000_200; + prom_init_kn02(); break; case DS5000_1XX: /* DS5000/100 3min */ - prom_printf("DS5000/1xx\n"); mips_machtype = MACH_DS5000_1XX; + prom_init_kn02xa(); break; - case DS5000_2X0: /* DS5000/240 3max+ */ - prom_printf("DS5000/2x0\n"); + case DS5000_2X0: /* DS5000/240 3max+ or DS5900 bigmax */ mips_machtype = MACH_DS5000_2X0; + prom_init_kn03(); + if (!(ioasic_read(IO_REG_SIR) & KN03_IO_INR_3MAXP)) + mips_machtype = MACH_DS5900; break; - case DS5000_XX: /* Personal DS5000/2x */ - prom_printf("Personal DS5000/xx\n"); + case DS5000_XX: /* Personal DS5000/xx maxine */ mips_machtype = MACH_DS5000_XX; + prom_init_kn02xa(); break; case DS5800: /* DS5800 Isis */ - prom_printf("DS5800\n"); mips_machtype = MACH_DS5800; break; case DS5400: /* DS5400 MIPSfair */ - prom_printf("DS5400\n"); mips_machtype = MACH_DS5400; break; case DS5500: /* DS5500 MIPSfair-2 */ - prom_printf("DS5500\n"); mips_machtype = MACH_DS5500; break; default: - prom_printf("unknown, id is %x", dec_systype); mips_machtype = MACH_DSUNKNOWN; break; } -} - + if (mips_machtype == MACH_DSUNKNOWN) + prom_printf("This is an %s, id is %x\n", + dec_system_strings[mips_machtype], + dec_systype); + else + prom_printf("This is a %s\n", + dec_system_strings[mips_machtype]); +} --- linux-2.5.73/arch/mips/dec/prom/init.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/prom/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -2,98 +2,103 @@ * init.c: PROM library initialisation code. * * Copyright (C) 1998 Harald Koerfgen + * Copyright (C) 2002 Maciej W. Rozycki */ -#include #include +#include +#include +#include + #include #include -#include "prom.h" +#include + +#include + + +int (*__rex_bootinit)(void); +int (*__rex_bootread)(void); +int (*__rex_getbitmap)(memmap *); +unsigned long *(*__rex_slot_address)(int); +void *(*__rex_gettcinfo)(void); +int (*__rex_getsysid)(void); +void (*__rex_clear_cache)(void); + +int (*__prom_getchar)(void); +char *(*__prom_getenv)(char *); +int (*__prom_printf)(char *, ...); + +int (*__pmax_open)(char*, int); +int (*__pmax_lseek)(int, long, int); +int (*__pmax_read)(int, void *, int); +int (*__pmax_close)(int); -/* - * PROM Interface (whichprom.c) - */ -typedef struct { - int pagesize; - unsigned char bitmap[0]; -} memmap; - -int (*rex_bootinit)(void); -int (*rex_bootread)(void); -int (*rex_getbitmap)(memmap *); -unsigned long *(*rex_slot_address)(int); -void *(*rex_gettcinfo)(void); -int (*rex_getsysid)(void); -void (*rex_clear_cache)(void); - -int (*prom_getchar)(void); -char *(*prom_getenv)(char *); -int (*prom_printf)(char *, ...); - -int (*pmax_open)(char*, int); -int (*pmax_lseek)(int, long, int); -int (*pmax_read)(int, void *, int); -int (*pmax_close)(int); - -extern void prom_meminit(unsigned int); -extern void prom_identify_arch(unsigned int); -extern void prom_init_cmdline(int, char **, unsigned long); /* * Detect which PROM's the DECSTATION has, and set the callback vectors * appropriately. */ -void __init which_prom(unsigned long magic, int *prom_vec) +void __init which_prom(s32 magic, s32 *prom_vec) { /* * No sign of the REX PROM's magic number means we assume a non-REX * machine (i.e. we're on a DS2100/3100, DS5100 or DS5000/2xx) */ - if (magic == REX_PROM_MAGIC) - { + if (prom_is_rex(magic)) { /* * Set up prom abstraction structure with REX entry points. */ - rex_bootinit = (int (*)(void)) *(prom_vec + REX_PROM_BOOTINIT); - rex_bootread = (int (*)(void)) *(prom_vec + REX_PROM_BOOTREAD); - rex_getbitmap = (int (*)(memmap *)) *(prom_vec + REX_PROM_GETBITMAP); - prom_getchar = (int (*)(void)) *(prom_vec + REX_PROM_GETCHAR); - prom_getenv = (char *(*)(char *)) *(prom_vec + REX_PROM_GETENV); - rex_getsysid = (int (*)(void)) *(prom_vec + REX_PROM_GETSYSID); - rex_gettcinfo = (void *(*)(void)) *(prom_vec + REX_PROM_GETTCINFO); - prom_printf = (int (*)(char *, ...)) *(prom_vec + REX_PROM_PRINTF); - rex_slot_address = (unsigned long *(*)(int)) *(prom_vec + REX_PROM_SLOTADDR); - rex_clear_cache = (void (*)(void)) * (prom_vec + REX_PROM_CLEARCACHE); - } - else - { + __rex_bootinit = + (void *)(long)*(prom_vec + REX_PROM_BOOTINIT); + __rex_bootread = + (void *)(long)*(prom_vec + REX_PROM_BOOTREAD); + __rex_getbitmap = + (void *)(long)*(prom_vec + REX_PROM_GETBITMAP); + __prom_getchar = + (void *)(long)*(prom_vec + REX_PROM_GETCHAR); + __prom_getenv = + (void *)(long)*(prom_vec + REX_PROM_GETENV); + __rex_getsysid = + (void *)(long)*(prom_vec + REX_PROM_GETSYSID); + __rex_gettcinfo = + (void *)(long)*(prom_vec + REX_PROM_GETTCINFO); + __prom_printf = + (void *)(long)*(prom_vec + REX_PROM_PRINTF); + __rex_slot_address = + (void *)(long)*(prom_vec + REX_PROM_SLOTADDR); + __rex_clear_cache = + (void *)(long)*(prom_vec + REX_PROM_CLEARCACHE); + } else { /* * Set up prom abstraction structure with non-REX entry points. */ - prom_getchar = (int (*)(void)) PMAX_PROM_GETCHAR; - prom_getenv = (char *(*)(char *)) PMAX_PROM_GETENV; - prom_printf = (int (*)(char *, ...)) PMAX_PROM_PRINTF; - pmax_open = (int (*)(char *, int)) PMAX_PROM_OPEN; - pmax_lseek = (int (*)(int, long, int)) PMAX_PROM_LSEEK; - pmax_read = (int (*)(int, void *, int)) PMAX_PROM_READ; - pmax_close = (int (*)(int)) PMAX_PROM_CLOSE; + __prom_getchar = (void *)PMAX_PROM_GETCHAR; + __prom_getenv = (void *)PMAX_PROM_GETENV; + __prom_printf = (void *)PMAX_PROM_PRINTF; + __pmax_open = (void *)PMAX_PROM_OPEN; + __pmax_lseek = (void *)PMAX_PROM_LSEEK; + __pmax_read = (void *)PMAX_PROM_READ; + __pmax_close = (void *)PMAX_PROM_CLOSE; } -} +} -int __init prom_init(int argc, char **argv, - unsigned long magic, int *prom_vec) +int __init prom_init(s32 argc, s32 *argv, u32 magic, s32 *prom_vec) { extern void dec_machine_halt(void); - /* Determine which PROM's we have (and therefore which machine we're on!) */ + /* + * Determine which PROM's we have + * (and therefore which machine we're on!) + */ which_prom(magic, prom_vec); - if (magic == REX_PROM_MAGIC) + if (prom_is_rex(magic)) rex_clear_cache(); /* Were we compiled with the right CPU option? */ #if defined(CONFIG_CPU_R3000) - if ((mips_cpu.cputype == CPU_R4000SC) || - (mips_cpu.cputype == CPU_R4400SC)) { + if ((current_cpu_data.cputype == CPU_R4000SC) || + (current_cpu_data.cputype == CPU_R4400SC)) { prom_printf("Sorry, this kernel is compiled for the wrong CPU type!\n"); prom_printf("Please recompile with \"CONFIG_CPU_R4x00 = y\"\n"); dec_machine_halt(); @@ -101,8 +106,8 @@ int __init prom_init(int argc, char **ar #endif #if defined(CONFIG_CPU_R4X00) - if ((mips_cpu.cputype == CPU_R3000) || - (mips_cpu.cputype == CPU_R3000A)) { + if ((current_cpu_data.cputype == CPU_R3000) || + (current_cpu_data.cputype == CPU_R3000A)) { prom_printf("Sorry, this kernel is compiled for the wrong CPU type!\n"); prom_printf("Please recompile with \"CONFIG_CPU_R3000 = y\"\n"); dec_machine_halt(); @@ -115,4 +120,3 @@ int __init prom_init(int argc, char **ar return 0; } - --- linux-2.5.73/arch/mips/dec/prom/locore.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/prom/locore.S 2003-06-27 15:56:23.000000000 -0700 @@ -19,11 +19,11 @@ NESTED(genexcept_early, 0, sp) mfc0 k0, CP0_STATUS la k1, mem_err - sw k0,0(k1) + sw k0, 0(k1) mfc0 k0, CP0_EPC nop - addiu k0,4 # skip the causing instruction + addiu k0, 4 # skip the causing instruction jr k0 rfe END(genexcept_early) --- linux-2.5.73/arch/mips/dec/prom/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/prom/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -1,11 +1,11 @@ -# $Id: Makefile,v 1.1 1999/01/17 03:49:44 ralf Exp $ +# # Makefile for the DECstation prom monitor library routines # under Linux. # -lib-y := init.o memory.o cmdline.o identify.o locore.o +lib-y += init.o memory.o cmdline.o identify.o -EXTRA_AFLAGS := $(CFLAGS) +lib-$(CONFIG_MIPS32) += locore.o +lib-$(CONFIG_MIPS64) += call_o32.o -dep: - $(CPP) $(CPPFLAGS) -M *.c > .depend +EXTRA_AFLAGS := $(CFLAGS) --- linux-2.5.73/arch/mips/dec/prom/memory.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/prom/memory.c 2003-06-27 15:56:23.000000000 -0700 @@ -2,37 +2,22 @@ * memory.c: memory initialisation code. * * Copyright (C) 1998 Harald Koerfgen, Frieder Streffer and Paul M. Antoine - * Copyright (C) 2000 Maciej W. Rozycki - * - * $Id: memory.c,v 1.3 1999/10/09 00:00:58 ralf Exp $ + * Copyright (C) 2000, 2002 Maciej W. Rozycki */ -#include #include +#include #include #include #include +#include #include -#include - #include - #include +#include +#include +#include -#include "prom.h" - -typedef struct { - int pagesize; - unsigned char bitmap[0]; -} memmap; - -extern int (*rex_getbitmap)(memmap *); - -#undef PROM_DEBUG - -#ifdef PROM_DEBUG -extern int (*prom_printf)(char *, ...); -#endif volatile unsigned long mem_err = 0; /* So we know an error occurred */ @@ -43,10 +28,10 @@ volatile unsigned long mem_err = 0; /* S #define CHUNK_SIZE 0x400000 -static void __init pmax_setup_memory_region(void) +static inline void pmax_setup_memory_region(void) { volatile unsigned char *memory_page, dummy; - char old_handler[0x80]; + char old_handler[0x80]; extern char genexcept_early; /* Install exception handler */ @@ -73,14 +58,14 @@ static void __init pmax_setup_memory_reg * Use the REX prom calls to get hold of the memory bitmap, and thence * determine memory size. */ -static void __init rex_setup_memory_region(void) +static inline void rex_setup_memory_region(void) { int i, bitmap_size; unsigned long mem_start = 0, mem_size = 0; memmap *bm; /* some free 64k */ - bm = (memmap *) 0x80028000; + bm = (memmap *)KSEG0ADDR(0x28000); bitmap_size = rex_getbitmap(bm); @@ -100,9 +85,9 @@ static void __init rex_setup_memory_regi add_memory_region(mem_start, mem_size, BOOT_MEM_RAM); } -void __init prom_meminit(unsigned int magic) +void __init prom_meminit(u32 magic) { - if (magic != REX_PROM_MAGIC) + if (!prom_is_rex(magic)) pmax_setup_memory_region(); else rex_setup_memory_region(); @@ -111,14 +96,13 @@ void __init prom_meminit(unsigned int ma void __init prom_free_prom_memory (void) { unsigned long addr, end; - extern char _ftext; /* * Free everything below the kernel itself but leave * the first page reserved for the exception handlers. */ -#ifdef CONFIG_DECLANCE +#if defined(CONFIG_DECLANCE) || defined(CONFIG_DECLANCE_MODULE) /* * Leave 128 KB reserved for Lance memory for * IOASIC DECstations. @@ -126,10 +110,10 @@ void __init prom_free_prom_memory (void) * XXX: save this address for use in dec_lance.c? */ if (IOASIC) - end = __pa(&_ftext) - 0x00020000; + end = __pa(&_text) - 0x00020000; else #endif - end = __pa(&_ftext); + end = __pa(&_text); addr = PAGE_SIZE; while (addr < end) { --- linux-2.5.73/arch/mips/dec/prom/prom.h 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,51 +0,0 @@ -/* - * Miscellaneous definitions used to call the routines contained in the boot - * PROMs on various models of DECSTATION's. - * the rights to redistribute these changes. - */ - -#ifndef __ASM_DEC_PROM_H -#define __ASM_DEC_PROM_H - -/* - * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's. Many of - * these will work for MIPSen as well! - */ -#define VEC_RESET 0xBFC00000 /* Prom base address */ -#define PMAX_PROM_ENTRY(x) (VEC_RESET+((x)*8)) /* Prom jump table */ - -#define PMAX_PROM_HALT PMAX_PROM_ENTRY(2) /* valid on MIPSen */ -#define PMAX_PROM_AUTOBOOT PMAX_PROM_ENTRY(5) /* valid on MIPSen */ -#define PMAX_PROM_OPEN PMAX_PROM_ENTRY(6) -#define PMAX_PROM_READ PMAX_PROM_ENTRY(7) -#define PMAX_PROM_CLOSE PMAX_PROM_ENTRY(10) -#define PMAX_PROM_LSEEK PMAX_PROM_ENTRY(11) -#define PMAX_PROM_GETCHAR PMAX_PROM_ENTRY(12) -#define PMAX_PROM_PUTCHAR PMAX_PROM_ENTRY(13) /* 12 on MIPSen */ -#define PMAX_PROM_GETS PMAX_PROM_ENTRY(15) -#define PMAX_PROM_PRINTF PMAX_PROM_ENTRY(17) -#define PMAX_PROM_GETENV PMAX_PROM_ENTRY(33) /* valid on MIPSen */ - -/* - * Magic number indicating REX PROM available on DECSTATION. Found in - * register a2 on transfer of control to program from PROM. - */ -#define REX_PROM_MAGIC 0x30464354 - -/* - * 3MIN/MAXINE PROM entry points for DS5000/1xx's, DS5000/xx's, and - * DS5000/2x0. - */ -#define REX_PROM_GETBITMAP 0x84/4 /* get mem bitmap */ -#define REX_PROM_GETCHAR 0x24/4 /* getch() */ -#define REX_PROM_GETENV 0x64/4 /* get env. variable */ -#define REX_PROM_GETSYSID 0x80/4 /* get system id */ -#define REX_PROM_GETTCINFO 0xa4/4 -#define REX_PROM_PRINTF 0x30/4 /* printf() */ -#define REX_PROM_SLOTADDR 0x6c/4 /* slotaddr */ -#define REX_PROM_BOOTINIT 0x54/4 /* open() */ -#define REX_PROM_BOOTREAD 0x58/4 /* read() */ -#define REX_PROM_CLEARCACHE 0x7c/4 - -#endif /* __ASM_DEC_PROM_H */ - --- linux-2.5.73/arch/mips/dec/reset.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/reset.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,11 +1,14 @@ /* - * $Id: $ - * - * Reset a DECstation machine. + * Reset a DECstation machine. * + * Copyright (C) 199x the Anonymous + * Copyright (C) 2001, 2002, 2003 Maciej W. Rozycki */ -void (*back_to_prom)(void) = (void (*)(void))0xBFC00000; +#include +#include + +#define back_to_prom() (((void (*)(void))KSEG1ADDR(0x1fc00000))()) void dec_machine_restart(char *command) { --- linux-2.5.73/arch/mips/dec/rtc-dec.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/rtc-dec.c 2003-06-27 15:56:23.000000000 -0700 @@ -3,33 +3,38 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * RTC routines for DECstation style attached Dallas chip. + * RTC routines for DECstation style attached Dallas DS1287 chip. * * Copyright (C) 1998, 2001 by Ralf Baechle * Copyright (C) 1998 by Harald Koerfgen + * Copyright (C) 2002 Maciej W. Rozycki */ + #include +#include +#include -extern char *dec_rtc_base; +volatile u8 *dec_rtc_base; static unsigned char dec_rtc_read_data(unsigned long addr) { - return (dec_rtc_base[addr * 4]); + return dec_rtc_base[addr * 4]; } static void dec_rtc_write_data(unsigned char data, unsigned long addr) { - dec_rtc_base[addr * 4] = data; + dec_rtc_base[addr * 4] = data; } static int dec_rtc_bcd_mode(void) { - return 0; + return 0; } -struct rtc_ops dec_rtc_ops = -{ - &dec_rtc_read_data, - &dec_rtc_write_data, - &dec_rtc_bcd_mode +struct rtc_ops dec_rtc_ops = { + &dec_rtc_read_data, + &dec_rtc_write_data, + &dec_rtc_bcd_mode }; + +EXPORT_SYMBOL(dec_rtc_base); --- linux-2.5.73/arch/mips/dec/setup.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -6,478 +6,768 @@ * for more details. * * Copyright (C) 1998 Harald Koerfgen - * Copyright (C) 2000 Maciej W. Rozycki + * Copyright (C) 2000, 2001, 2002, 2003 Maciej W. Rozycki */ +#include #include #include #include #include #include -#include -#include #include +#include +#include +#include + +#include +#include #include +#include +#include #include +#include +#include #include -#include -#include -#include -#include #include #include #include +#include +#include +#include +#include +#include +#include -char *dec_rtc_base = (void *) KN01_RTC_BASE; /* Assume DS2100/3100 initially */ - -volatile unsigned int *ioasic_base; - -decint_t dec_interrupt[NR_INTS]; - -/* - * Information regarding the IRQ Controller - */ - -volatile unsigned int *isr = 0L; /* address of the interrupt status register */ -volatile unsigned int *imr = 0L; /* address of the interrupt mask register */ - extern void dec_machine_restart(char *command); extern void dec_machine_halt(void); extern void dec_machine_power_off(void); extern void dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs); -extern void wbflush_setup(void); +extern asmlinkage void decstation_handle_int(void); -extern struct rtc_ops dec_rtc_ops; +spinlock_t ioasic_ssr_lock; -extern int setup_dec_irq(int, struct irqaction *); +volatile u32 *ioasic_base; +unsigned long dec_kn_slot_size; -void (*board_time_init) (struct irqaction * irq); +/* + * IRQ routing and priority tables. Priorites are set as follows: + * + * KN01 KN230 KN02 KN02-BA KN02-CA KN03 + * + * MEMORY CPU CPU CPU ASIC CPU CPU + * RTC CPU CPU CPU ASIC CPU CPU + * DMA - - - ASIC ASIC ASIC + * SERIAL0 CPU CPU CSR ASIC ASIC ASIC + * SERIAL1 - - - ASIC - ASIC + * SCSI CPU CPU CSR ASIC ASIC ASIC + * ETHERNET CPU * CSR ASIC ASIC ASIC + * other - - - ASIC - - + * TC2 - - CSR CPU ASIC ASIC + * TC1 - - CSR CPU ASIC ASIC + * TC0 - - CSR CPU ASIC ASIC + * other - CPU - CPU ASIC ASIC + * other - - - - CPU CPU + * + * * -- shared with SCSI + */ + +int dec_interrupt[DEC_NR_INTS] = { + [0 ... DEC_NR_INTS - 1] = -1 +}; +int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = { + { { .i = ~0 }, { .p = dec_intr_unimplemented } }, +}; +int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = { + { { .i = ~0 }, { .p = asic_intr_unimplemented } }, +}; +int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU); + +static struct irqaction ioirq = { + .handler = no_action, + .name = "cascade", +}; +static struct irqaction fpuirq = { + .handler = no_action, + .name = "fpu", +}; + +static struct irqaction busirq = { + .flags = SA_INTERRUPT, + .name = "bus error", +}; + +static struct irqaction haltirq = { + .handler = dec_intr_halt, + .name = "halt", +}; + + +void (*board_time_init)(struct irqaction *irq); -static struct irqaction irq10 = {dec_intr_halt, 0, 0, "halt", NULL, NULL}; /* * enable the periodic interrupts */ static void __init dec_time_init(struct irqaction *irq) { - /* - * Here we go, enable periodic rtc interrupts. - */ + /* + * Here we go, enable periodic rtc interrupts. + */ #ifndef LOG_2_HZ # define LOG_2_HZ 7 #endif - CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - LOG_2_HZ), RTC_REG_A); - CMOS_WRITE(CMOS_READ(RTC_REG_B) | RTC_PIE, RTC_REG_B); - setup_dec_irq(CLOCK, irq); + CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - LOG_2_HZ), RTC_REG_A); + CMOS_WRITE(CMOS_READ(RTC_REG_B) | RTC_PIE, RTC_REG_B); + setup_irq(dec_interrupt[DEC_IRQ_RTC], irq); } + /* - * Enable the halt interrupt. + * Bus error (DBE/IBE exceptions and bus interrupts) handling setup. */ -static void __init dec_halt_init(struct irqaction *irq) +void __init dec_be_init(void) { - setup_dec_irq(HALT, irq); + switch (mips_machtype) { + case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ + busirq.flags |= SA_SHIRQ; + break; + case MACH_DS5000_200: /* DS5000/200 3max */ + case MACH_DS5000_2X0: /* DS5000/240 3max+ */ + case MACH_DS5900: /* DS5900 bigmax */ + board_be_handler = dec_ecc_be_handler; + busirq.handler = dec_ecc_be_interrupt; + dec_ecc_be_init(); + break; + } } + void __init decstation_setup(void) { - board_time_init = dec_time_init; + board_be_init = dec_be_init; + board_time_init = dec_time_init; - wbflush_setup(); + wbflush_setup(); - _machine_restart = dec_machine_restart; - _machine_halt = dec_machine_halt; - _machine_power_off = dec_machine_power_off; + _machine_restart = dec_machine_restart; + _machine_halt = dec_machine_halt; + _machine_power_off = dec_machine_power_off; #ifdef CONFIG_FB - conswitchp = &dummy_con; + conswitchp = &dummy_con; #endif - rtc_ops = &dec_rtc_ops; + rtc_ops = &dec_rtc_ops; } + /* - * Machine-specific initialisation for kn01, aka Pmax, aka DS2100, DS3100, - * and possibly also the DS5100. + * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin) + * or DS3100 (aka Pmax). */ +static int kn01_interrupt[DEC_NR_INTS] __initdata = { + [DEC_IRQ_CASCADE] = -1, + [DEC_IRQ_AB_RECV] = -1, + [DEC_IRQ_AB_XMIT] = -1, + [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11), + [DEC_IRQ_ASC] = -1, + [DEC_IRQ_FLOPPY] = -1, + [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), + [DEC_IRQ_HALT] = -1, + [DEC_IRQ_ISDN] = -1, + [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE), + [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS), + [DEC_IRQ_PSU] = -1, + [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC), + [DEC_IRQ_SCC0] = -1, + [DEC_IRQ_SCC1] = -1, + [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII), + [DEC_IRQ_TC0] = -1, + [DEC_IRQ_TC1] = -1, + [DEC_IRQ_TC2] = -1, + [DEC_IRQ_TIMER] = -1, + [DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO), + [DEC_IRQ_ASC_MERR] = -1, + [DEC_IRQ_ASC_ERR] = -1, + [DEC_IRQ_ASC_DMA] = -1, + [DEC_IRQ_FLOPPY_ERR] = -1, + [DEC_IRQ_ISDN_ERR] = -1, + [DEC_IRQ_ISDN_RXDMA] = -1, + [DEC_IRQ_ISDN_TXDMA] = -1, + [DEC_IRQ_LANCE_MERR] = -1, + [DEC_IRQ_SCC0A_RXERR] = -1, + [DEC_IRQ_SCC0A_RXDMA] = -1, + [DEC_IRQ_SCC0A_TXERR] = -1, + [DEC_IRQ_SCC0A_TXDMA] = -1, + [DEC_IRQ_AB_RXERR] = -1, + [DEC_IRQ_AB_RXDMA] = -1, + [DEC_IRQ_AB_TXERR] = -1, + [DEC_IRQ_AB_TXDMA] = -1, + [DEC_IRQ_SCC1A_RXERR] = -1, + [DEC_IRQ_SCC1A_RXDMA] = -1, + [DEC_IRQ_SCC1A_TXERR] = -1, + [DEC_IRQ_SCC1A_TXDMA] = -1, +}; + +static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = { + { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) }, + { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } }, + { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) }, + { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } }, + { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) }, + { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } }, + { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) }, + { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } }, + { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) }, + { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } }, + { { .i = DEC_CPU_IRQ_ALL }, + { .p = cpu_all_int } }, +}; + void __init dec_init_kn01(void) { - /* - * Setup some memory addresses. - */ - dec_rtc_base = (char *) KN01_RTC_BASE; - - /* - * Setup interrupt structure - */ - dec_interrupt[CLOCK].cpu_mask = IE_IRQ3; - dec_interrupt[CLOCK].iemask = 0; - cpu_mask_tbl[0] = IE_IRQ3; - cpu_irq_nr[0] = CLOCK; - - dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0; - dec_interrupt[SCSI_INT].iemask = 0; - cpu_mask_tbl[1] = IE_IRQ0; - cpu_irq_nr[1] = SCSI_INT; - - dec_interrupt[ETHER].cpu_mask = IE_IRQ1; - dec_interrupt[ETHER].iemask = 0; - cpu_mask_tbl[2] = IE_IRQ1; - cpu_irq_nr[2] = ETHER; - - dec_interrupt[SERIAL].cpu_mask = IE_IRQ2; - dec_interrupt[SERIAL].iemask = 0; - cpu_mask_tbl[3] = IE_IRQ2; - cpu_irq_nr[3] = SERIAL; - - dec_interrupt[MEMORY].cpu_mask = IE_IRQ4; - dec_interrupt[MEMORY].iemask = 0; - cpu_mask_tbl[4] = IE_IRQ4; - cpu_irq_nr[4] = MEMORY; - - dec_interrupt[FPU].cpu_mask = IE_IRQ5; - dec_interrupt[FPU].iemask = 0; - cpu_mask_tbl[5] = IE_IRQ5; - cpu_irq_nr[5] = FPU; + /* IRQ routing. */ + memcpy(&dec_interrupt, &kn01_interrupt, + sizeof(kn01_interrupt)); + + /* CPU IRQ priorities. */ + memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl, + sizeof(kn01_cpu_mask_nr_tbl)); + + mips_cpu_irq_init(DEC_CPU_IRQ_BASE); + } /* dec_init_kn01 */ + /* - * Machine-specific initialisation for kn230, aka MIPSmate, aka DS5100 - * - * There are a lot of experiments to do, this is definitely incomplete. + * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate. */ +static int kn230_interrupt[DEC_NR_INTS] __initdata = { + [DEC_IRQ_CASCADE] = -1, + [DEC_IRQ_AB_RECV] = -1, + [DEC_IRQ_AB_XMIT] = -1, + [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11), + [DEC_IRQ_ASC] = -1, + [DEC_IRQ_FLOPPY] = -1, + [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), + [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT), + [DEC_IRQ_ISDN] = -1, + [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE), + [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS), + [DEC_IRQ_PSU] = -1, + [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC), + [DEC_IRQ_SCC0] = -1, + [DEC_IRQ_SCC1] = -1, + [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII), + [DEC_IRQ_TC0] = -1, + [DEC_IRQ_TC1] = -1, + [DEC_IRQ_TC2] = -1, + [DEC_IRQ_TIMER] = -1, + [DEC_IRQ_VIDEO] = -1, + [DEC_IRQ_ASC_MERR] = -1, + [DEC_IRQ_ASC_ERR] = -1, + [DEC_IRQ_ASC_DMA] = -1, + [DEC_IRQ_FLOPPY_ERR] = -1, + [DEC_IRQ_ISDN_ERR] = -1, + [DEC_IRQ_ISDN_RXDMA] = -1, + [DEC_IRQ_ISDN_TXDMA] = -1, + [DEC_IRQ_LANCE_MERR] = -1, + [DEC_IRQ_SCC0A_RXERR] = -1, + [DEC_IRQ_SCC0A_RXDMA] = -1, + [DEC_IRQ_SCC0A_TXERR] = -1, + [DEC_IRQ_SCC0A_TXDMA] = -1, + [DEC_IRQ_AB_RXERR] = -1, + [DEC_IRQ_AB_RXDMA] = -1, + [DEC_IRQ_AB_TXERR] = -1, + [DEC_IRQ_AB_TXDMA] = -1, + [DEC_IRQ_SCC1A_RXERR] = -1, + [DEC_IRQ_SCC1A_RXDMA] = -1, + [DEC_IRQ_SCC1A_TXERR] = -1, + [DEC_IRQ_SCC1A_TXDMA] = -1, +}; + +static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = { + { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) }, + { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } }, + { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) }, + { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } }, + { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) }, + { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } }, + { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) }, + { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } }, + { { .i = DEC_CPU_IRQ_ALL }, + { .p = cpu_all_int } }, +}; + void __init dec_init_kn230(void) { - /* - * Setup some memory addresses. - */ - dec_rtc_base = (char *) KN01_RTC_BASE; - - /* - * Setup interrupt structure - */ - dec_interrupt[CLOCK].cpu_mask = IE_IRQ2; - dec_interrupt[CLOCK].iemask = 0; - cpu_mask_tbl[0] = IE_IRQ2; - cpu_irq_nr[0] = CLOCK; - - dec_interrupt[FPU].cpu_mask = IE_IRQ5; - dec_interrupt[FPU].iemask = 0; - cpu_mask_tbl[5] = IE_IRQ5; - cpu_irq_nr[5] = FPU; + /* IRQ routing. */ + memcpy(&dec_interrupt, &kn230_interrupt, + sizeof(kn230_interrupt)); + + /* CPU IRQ priorities. */ + memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl, + sizeof(kn230_cpu_mask_nr_tbl)); + + mips_cpu_irq_init(DEC_CPU_IRQ_BASE); + } /* dec_init_kn230 */ + /* - * Machine-specific initialisation for kn02, aka 3max, aka DS5000/2xx. + * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max. */ +static int kn02_interrupt[DEC_NR_INTS] __initdata = { + [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE), + [DEC_IRQ_AB_RECV] = -1, + [DEC_IRQ_AB_XMIT] = -1, + [DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11), + [DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC), + [DEC_IRQ_FLOPPY] = -1, + [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), + [DEC_IRQ_HALT] = -1, + [DEC_IRQ_ISDN] = -1, + [DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE), + [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS), + [DEC_IRQ_PSU] = -1, + [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC), + [DEC_IRQ_SCC0] = -1, + [DEC_IRQ_SCC1] = -1, + [DEC_IRQ_SII] = -1, + [DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0), + [DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1), + [DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2), + [DEC_IRQ_TIMER] = -1, + [DEC_IRQ_VIDEO] = -1, + [DEC_IRQ_ASC_MERR] = -1, + [DEC_IRQ_ASC_ERR] = -1, + [DEC_IRQ_ASC_DMA] = -1, + [DEC_IRQ_FLOPPY_ERR] = -1, + [DEC_IRQ_ISDN_ERR] = -1, + [DEC_IRQ_ISDN_RXDMA] = -1, + [DEC_IRQ_ISDN_TXDMA] = -1, + [DEC_IRQ_LANCE_MERR] = -1, + [DEC_IRQ_SCC0A_RXERR] = -1, + [DEC_IRQ_SCC0A_RXDMA] = -1, + [DEC_IRQ_SCC0A_TXERR] = -1, + [DEC_IRQ_SCC0A_TXDMA] = -1, + [DEC_IRQ_AB_RXERR] = -1, + [DEC_IRQ_AB_RXDMA] = -1, + [DEC_IRQ_AB_TXERR] = -1, + [DEC_IRQ_AB_TXDMA] = -1, + [DEC_IRQ_SCC1A_RXERR] = -1, + [DEC_IRQ_SCC1A_RXDMA] = -1, + [DEC_IRQ_SCC1A_TXERR] = -1, + [DEC_IRQ_SCC1A_TXDMA] = -1, +}; + +static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = { + { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) }, + { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } }, + { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) }, + { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } }, + { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) }, + { .p = kn02_io_int } }, + { { .i = DEC_CPU_IRQ_ALL }, + { .p = cpu_all_int } }, +}; + +static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = { + { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) }, + { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } }, + { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) }, + { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } }, + { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) }, + { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } }, + { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) }, + { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } }, + { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) }, + { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } }, + { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) }, + { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } }, + { { .i = KN02_IRQ_ALL }, + { .p = kn02_all_int } }, +}; + void __init dec_init_kn02(void) { - /* - * Setup some memory addresses. FIXME: probably incomplete! - */ - dec_rtc_base = (char *) KN02_RTC_BASE; - isr = (void *) KN02_CSR_ADDR; - imr = (void *) KN02_CSR_ADDR; - - /* - * Setup IOASIC interrupt - */ - cpu_ivec_tbl[1] = kn02_io_int; - cpu_mask_tbl[1] = IE_IRQ0; - cpu_irq_nr[1] = -1; - *imr = *imr & 0xff00ff00; - - /* - * Setup interrupt structure - */ - dec_interrupt[CLOCK].cpu_mask = IE_IRQ1; - dec_interrupt[CLOCK].iemask = 0; - cpu_mask_tbl[0] = IE_IRQ1; - cpu_irq_nr[0] = CLOCK; - - dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0; - dec_interrupt[SCSI_INT].iemask = KN02_SLOT5; - asic_mask_tbl[0] = KN02_SLOT5; - asic_irq_nr[0] = SCSI_INT; - - dec_interrupt[ETHER].cpu_mask = IE_IRQ0; - dec_interrupt[ETHER].iemask = KN02_SLOT6; - asic_mask_tbl[1] = KN02_SLOT6; - asic_irq_nr[1] = ETHER; - - dec_interrupt[SERIAL].cpu_mask = IE_IRQ0; - dec_interrupt[SERIAL].iemask = KN02_SLOT7; - asic_mask_tbl[2] = KN02_SLOT7; - asic_irq_nr[2] = SERIAL; - - dec_interrupt[TC0].cpu_mask = IE_IRQ0; - dec_interrupt[TC0].iemask = KN02_SLOT0; - asic_mask_tbl[3] = KN02_SLOT0; - asic_irq_nr[3] = TC0; - - dec_interrupt[TC1].cpu_mask = IE_IRQ0; - dec_interrupt[TC1].iemask = KN02_SLOT1; - asic_mask_tbl[4] = KN02_SLOT1; - asic_irq_nr[4] = TC1; - - dec_interrupt[TC2].cpu_mask = IE_IRQ0; - dec_interrupt[TC2].iemask = KN02_SLOT2; - asic_mask_tbl[5] = KN02_SLOT2; - asic_irq_nr[5] = TC2; - - dec_interrupt[MEMORY].cpu_mask = IE_IRQ3; - dec_interrupt[MEMORY].iemask = 0; - cpu_mask_tbl[2] = IE_IRQ3; - cpu_irq_nr[2] = MEMORY; - - dec_interrupt[FPU].cpu_mask = IE_IRQ5; - dec_interrupt[FPU].iemask = 0; - cpu_mask_tbl[3] = IE_IRQ5; - cpu_irq_nr[3] = FPU; + /* IRQ routing. */ + memcpy(&dec_interrupt, &kn02_interrupt, + sizeof(kn02_interrupt)); + + /* CPU IRQ priorities. */ + memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl, + sizeof(kn02_cpu_mask_nr_tbl)); + + /* KN02 CSR IRQ priorities. */ + memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl, + sizeof(kn02_asic_mask_nr_tbl)); + + mips_cpu_irq_init(DEC_CPU_IRQ_BASE); + init_kn02_irqs(KN02_IRQ_BASE); } /* dec_init_kn02 */ + /* - * Machine-specific initialisation for kn02ba, aka 3min, aka DS5000/1xx. + * Machine-specific initialisation for KN02-BA, aka DS5000/1xx + * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka + * DS5000/150, aka 4min. */ +static int kn02ba_interrupt[DEC_NR_INTS] __initdata = { + [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE), + [DEC_IRQ_AB_RECV] = -1, + [DEC_IRQ_AB_XMIT] = -1, + [DEC_IRQ_DZ11] = -1, + [DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC), + [DEC_IRQ_FLOPPY] = -1, + [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), + [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT), + [DEC_IRQ_ISDN] = -1, + [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE), + [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS), + [DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU), + [DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC), + [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0), + [DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1), + [DEC_IRQ_SII] = -1, + [DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0), + [DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1), + [DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2), + [DEC_IRQ_TIMER] = -1, + [DEC_IRQ_VIDEO] = -1, + [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), + [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), + [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), + [DEC_IRQ_FLOPPY_ERR] = -1, + [DEC_IRQ_ISDN_ERR] = -1, + [DEC_IRQ_ISDN_RXDMA] = -1, + [DEC_IRQ_ISDN_TXDMA] = -1, + [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), + [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), + [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), + [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), + [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), + [DEC_IRQ_AB_RXERR] = -1, + [DEC_IRQ_AB_RXDMA] = -1, + [DEC_IRQ_AB_TXERR] = -1, + [DEC_IRQ_AB_TXDMA] = -1, + [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR), + [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA), + [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR), + [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA), +}; + +static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = { + { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) }, + { .p = kn02xa_io_int } }, + { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) }, + { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } }, + { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) }, + { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } }, + { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) }, + { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } }, + { { .i = DEC_CPU_IRQ_ALL }, + { .p = cpu_all_int } }, +}; + +static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = { + { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) }, + { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } }, + { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) }, + { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } }, + { { .i = IO_IRQ_DMA }, + { .p = asic_dma_int } }, + { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) }, + { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } }, + { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) }, + { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } }, + { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) }, + { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } }, + { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) }, + { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } }, + { { .i = IO_IRQ_ALL }, + { .p = asic_all_int } }, +}; + void __init dec_init_kn02ba(void) { - /* - * Setup some memory addresses. - */ - ioasic_base = (void *) KN02XA_IOASIC_BASE; - dec_rtc_base = (char *) KN02XA_RTC_BASE; - isr = (void *) KN02XA_IOASIC_REG(SIR); - imr = (void *) KN02XA_IOASIC_REG(SIMR); - - /* - * Setup IOASIC interrupt - */ - cpu_mask_tbl[0] = IE_IRQ3; - cpu_irq_nr[0] = -1; - cpu_ivec_tbl[0] = kn02xa_io_int; - *imr = 0; - - /* - * Setup interrupt structure - */ - dec_interrupt[CLOCK].cpu_mask = IE_IRQ3; - dec_interrupt[CLOCK].iemask = KMIN_CLOCK; - asic_mask_tbl[0] = KMIN_CLOCK; - asic_irq_nr[0] = CLOCK; - - dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ3; - dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS; - asic_mask_tbl[1] = SCSI_DMA_INTS; - asic_irq_nr[1] = SCSI_DMA_INT; - - dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ3; - dec_interrupt[SCSI_INT].iemask = SCSI_CHIP; - asic_mask_tbl[2] = SCSI_CHIP; - asic_irq_nr[2] = SCSI_INT; - - dec_interrupt[ETHER].cpu_mask = IE_IRQ3; - dec_interrupt[ETHER].iemask = LANCE_INTS; - asic_mask_tbl[3] = LANCE_INTS; - asic_irq_nr[3] = ETHER; - - dec_interrupt[SERIAL].cpu_mask = IE_IRQ3; - dec_interrupt[SERIAL].iemask = SERIAL_INTS; - asic_mask_tbl[4] = SERIAL_INTS; - asic_irq_nr[4] = SERIAL; - - dec_interrupt[MEMORY].cpu_mask = IE_IRQ3; - dec_interrupt[MEMORY].iemask = KMIN_TIMEOUT; - asic_mask_tbl[5] = KMIN_TIMEOUT; - asic_irq_nr[5] = MEMORY; - - dec_interrupt[TC0].cpu_mask = IE_IRQ0; - dec_interrupt[TC0].iemask = 0; - cpu_mask_tbl[1] = IE_IRQ0; - cpu_irq_nr[1] = TC0; - - dec_interrupt[TC1].cpu_mask = IE_IRQ1; - dec_interrupt[TC1].iemask = 0; - cpu_mask_tbl[2] = IE_IRQ1; - cpu_irq_nr[2] = TC1; - - dec_interrupt[TC2].cpu_mask = IE_IRQ2; - dec_interrupt[TC2].iemask = 0; - cpu_mask_tbl[3] = IE_IRQ2; - cpu_irq_nr[3] = TC2; - - dec_interrupt[HALT].cpu_mask = IE_IRQ4; - dec_interrupt[HALT].iemask = 0; - cpu_mask_tbl[4] = IE_IRQ4; - cpu_irq_nr[4] = HALT; - - dec_interrupt[FPU].cpu_mask = IE_IRQ5; - dec_interrupt[FPU].iemask = 0; - cpu_mask_tbl[5] = IE_IRQ5; - cpu_irq_nr[5] = FPU; + /* IRQ routing. */ + memcpy(&dec_interrupt, &kn02ba_interrupt, + sizeof(kn02ba_interrupt)); + + /* CPU IRQ priorities. */ + memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl, + sizeof(kn02ba_cpu_mask_nr_tbl)); + + /* I/O ASIC IRQ priorities. */ + memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl, + sizeof(kn02ba_asic_mask_nr_tbl)); + + mips_cpu_irq_init(DEC_CPU_IRQ_BASE); + init_ioasic_irqs(IO_IRQ_BASE); - dec_halt_init(&irq10); } /* dec_init_kn02ba */ + /* - * Machine-specific initialisation for kn02ca, aka maxine, aka DS5000/2x. + * Machine-specific initialisation for KN02-CA, aka DS5000/xx, + * (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka + * DS5000/50, aka 4MAXine. */ +static int kn02ca_interrupt[DEC_NR_INTS] __initdata = { + [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE), + [DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV), + [DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT), + [DEC_IRQ_DZ11] = -1, + [DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC), + [DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY), + [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), + [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT), + [DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN), + [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE), + [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS), + [DEC_IRQ_PSU] = -1, + [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC), + [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0), + [DEC_IRQ_SCC1] = -1, + [DEC_IRQ_SII] = -1, + [DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0), + [DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1), + [DEC_IRQ_TC2] = -1, + [DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER), + [DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO), + [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), + [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), + [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), + [DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR), + [DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR), + [DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA), + [DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA), + [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), + [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), + [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), + [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), + [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), + [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR), + [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA), + [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR), + [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA), + [DEC_IRQ_SCC1A_RXERR] = -1, + [DEC_IRQ_SCC1A_RXDMA] = -1, + [DEC_IRQ_SCC1A_TXERR] = -1, + [DEC_IRQ_SCC1A_TXDMA] = -1, +}; + +static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = { + { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) }, + { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } }, + { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) }, + { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } }, + { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) }, + { .p = kn02xa_io_int } }, + { { .i = DEC_CPU_IRQ_ALL }, + { .p = cpu_all_int } }, +}; + +static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = { + { { .i = IO_IRQ_DMA }, + { .p = asic_dma_int } }, + { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) }, + { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } }, + { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) }, + { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } }, + { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) }, + { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } }, + { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) }, + { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } }, + { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) }, + { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } }, + { { .i = IO_IRQ_ALL }, + { .p = asic_all_int } }, +}; + void __init dec_init_kn02ca(void) { - /* - * Setup some memory addresses. FIXME: probably incomplete! - */ - ioasic_base = (void *) KN02XA_IOASIC_BASE; - dec_rtc_base = (char *) KN02XA_RTC_BASE; - isr = (void *) KN02XA_IOASIC_REG(SIR); - imr = (void *) KN02XA_IOASIC_REG(SIMR); - - /* - * Setup IOASIC interrupt - */ - cpu_ivec_tbl[1] = kn02xa_io_int; - cpu_irq_nr[1] = -1; - cpu_mask_tbl[1] = IE_IRQ3; - *imr = 0; - - /* - * Setup interrupt structure - */ - dec_interrupt[CLOCK].cpu_mask = IE_IRQ1; - dec_interrupt[CLOCK].iemask = 0; - cpu_mask_tbl[0] = IE_IRQ1; - cpu_irq_nr[0] = CLOCK; - - dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ3; - dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS; - asic_mask_tbl[0] = SCSI_DMA_INTS; - asic_irq_nr[0] = SCSI_DMA_INT; - - dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ3; - dec_interrupt[SCSI_INT].iemask = SCSI_CHIP; - asic_mask_tbl[1] = SCSI_CHIP; - asic_irq_nr[1] = SCSI_INT; - - dec_interrupt[ETHER].cpu_mask = IE_IRQ3; - dec_interrupt[ETHER].iemask = LANCE_INTS; - asic_mask_tbl[2] = LANCE_INTS; - asic_irq_nr[2] = ETHER; - - dec_interrupt[SERIAL].cpu_mask = IE_IRQ3; - dec_interrupt[SERIAL].iemask = XINE_SERIAL_INTS; - asic_mask_tbl[3] = XINE_SERIAL_INTS; - asic_irq_nr[3] = SERIAL; - - dec_interrupt[TC0].cpu_mask = IE_IRQ3; - dec_interrupt[TC0].iemask = MAXINE_TC0; - asic_mask_tbl[4] = MAXINE_TC0; - asic_irq_nr[4] = TC0; - - dec_interrupt[TC1].cpu_mask = IE_IRQ3; - dec_interrupt[TC1].iemask = MAXINE_TC1; - asic_mask_tbl[5] = MAXINE_TC1; - asic_irq_nr[5] = TC1; - - dec_interrupt[MEMORY].cpu_mask = IE_IRQ2; - dec_interrupt[MEMORY].iemask = 0; - cpu_mask_tbl[2] = IE_IRQ2; - cpu_irq_nr[2] = MEMORY; - - dec_interrupt[HALT].cpu_mask = IE_IRQ4; - dec_interrupt[HALT].iemask = 0; - cpu_mask_tbl[3] = IE_IRQ4; - cpu_irq_nr[3] = HALT; - - dec_interrupt[FPU].cpu_mask = IE_IRQ5; - dec_interrupt[FPU].iemask = 0; - cpu_mask_tbl[4] = IE_IRQ5; - cpu_irq_nr[4] = FPU; + /* IRQ routing. */ + memcpy(&dec_interrupt, &kn02ca_interrupt, + sizeof(kn02ca_interrupt)); + + /* CPU IRQ priorities. */ + memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl, + sizeof(kn02ca_cpu_mask_nr_tbl)); + + /* I/O ASIC IRQ priorities. */ + memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl, + sizeof(kn02ca_asic_mask_nr_tbl)); + + mips_cpu_irq_init(DEC_CPU_IRQ_BASE); + init_ioasic_irqs(IO_IRQ_BASE); - dec_halt_init(&irq10); } /* dec_init_kn02ca */ + /* - * Machine-specific initialisation for kn03, aka 3max+, aka DS5000/240. + * Machine-specific initialisation for KN03, aka DS5000/240, + * aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka + * DS5000/260, aka 4max+ and DS5900/260. */ +static int kn03_interrupt[DEC_NR_INTS] __initdata = { + [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE), + [DEC_IRQ_AB_RECV] = -1, + [DEC_IRQ_AB_XMIT] = -1, + [DEC_IRQ_DZ11] = -1, + [DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC), + [DEC_IRQ_FLOPPY] = -1, + [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU), + [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT), + [DEC_IRQ_ISDN] = -1, + [DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE), + [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS), + [DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU), + [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC), + [DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0), + [DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1), + [DEC_IRQ_SII] = -1, + [DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0), + [DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1), + [DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2), + [DEC_IRQ_TIMER] = -1, + [DEC_IRQ_VIDEO] = -1, + [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR), + [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR), + [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA), + [DEC_IRQ_FLOPPY_ERR] = -1, + [DEC_IRQ_ISDN_ERR] = -1, + [DEC_IRQ_ISDN_RXDMA] = -1, + [DEC_IRQ_ISDN_TXDMA] = -1, + [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR), + [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR), + [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA), + [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR), + [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA), + [DEC_IRQ_AB_RXERR] = -1, + [DEC_IRQ_AB_RXDMA] = -1, + [DEC_IRQ_AB_TXERR] = -1, + [DEC_IRQ_AB_TXDMA] = -1, + [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR), + [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA), + [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR), + [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA), +}; + +static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = { + { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) }, + { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } }, + { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) }, + { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } }, + { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) }, + { .p = kn03_io_int } }, + { { .i = DEC_CPU_IRQ_ALL }, + { .p = cpu_all_int } }, +}; + +static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = { + { { .i = IO_IRQ_DMA }, + { .p = asic_dma_int } }, + { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) }, + { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } }, + { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) }, + { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } }, + { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) }, + { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } }, + { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) }, + { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } }, + { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) }, + { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } }, + { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) }, + { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } }, + { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) }, + { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } }, + { { .i = IO_IRQ_ALL }, + { .p = asic_all_int } }, +}; + void __init dec_init_kn03(void) { - /* - * Setup some memory addresses. FIXME: probably incomplete! - */ - ioasic_base = (void *) KN03_IOASIC_BASE; - dec_rtc_base = (char *) KN03_RTC_BASE; - isr = (void *) KN03_IOASIC_REG(SIR); - imr = (void *) KN03_IOASIC_REG(SIMR); - - /* - * Setup IOASIC interrupt - */ - cpu_ivec_tbl[1] = kn03_io_int; - cpu_mask_tbl[1] = IE_IRQ0; - cpu_irq_nr[1] = -1; - *imr = 0; - - /* - * Setup interrupt structure - */ - dec_interrupt[CLOCK].cpu_mask = IE_IRQ1; - dec_interrupt[CLOCK].iemask = 0; - cpu_mask_tbl[0] = IE_IRQ1; - cpu_irq_nr[0] = CLOCK; - - dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ0; - dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS; - asic_mask_tbl[0] = SCSI_DMA_INTS; - asic_irq_nr[0] = SCSI_DMA_INT; - - dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0; - dec_interrupt[SCSI_INT].iemask = SCSI_CHIP; - asic_mask_tbl[1] = SCSI_CHIP; - asic_irq_nr[1] = SCSI_INT; - - dec_interrupt[ETHER].cpu_mask = IE_IRQ0; - dec_interrupt[ETHER].iemask = LANCE_INTS; - asic_mask_tbl[2] = LANCE_INTS; - asic_irq_nr[2] = ETHER; - - dec_interrupt[SERIAL].cpu_mask = IE_IRQ0; - dec_interrupt[SERIAL].iemask = SERIAL_INTS; - asic_mask_tbl[3] = SERIAL_INTS; - asic_irq_nr[3] = SERIAL; - - dec_interrupt[TC0].cpu_mask = IE_IRQ0; - dec_interrupt[TC0].iemask = KN03_TC0; - asic_mask_tbl[4] = KN03_TC0; - asic_irq_nr[4] = TC0; - - dec_interrupt[TC1].cpu_mask = IE_IRQ0; - dec_interrupt[TC1].iemask = KN03_TC1; - asic_mask_tbl[5] = KN03_TC1; - asic_irq_nr[5] = TC1; - - dec_interrupt[TC2].cpu_mask = IE_IRQ0; - dec_interrupt[TC2].iemask = KN03_TC2; - asic_mask_tbl[6] = KN03_TC2; - asic_irq_nr[6] = TC2; - - dec_interrupt[MEMORY].cpu_mask = IE_IRQ3; - dec_interrupt[MEMORY].iemask = 0; - cpu_mask_tbl[2] = IE_IRQ3; - cpu_irq_nr[2] = MEMORY; - - dec_interrupt[HALT].cpu_mask = IE_IRQ4; - dec_interrupt[HALT].iemask = 0; - cpu_mask_tbl[3] = IE_IRQ4; - cpu_irq_nr[3] = HALT; - - dec_interrupt[FPU].cpu_mask = IE_IRQ5; - dec_interrupt[FPU].iemask = 0; - cpu_mask_tbl[4] = IE_IRQ5; - cpu_irq_nr[4] = FPU; + /* IRQ routing. */ + memcpy(&dec_interrupt, &kn03_interrupt, + sizeof(kn03_interrupt)); + + /* CPU IRQ priorities. */ + memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl, + sizeof(kn03_cpu_mask_nr_tbl)); + + /* I/O ASIC IRQ priorities. */ + memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl, + sizeof(kn03_asic_mask_nr_tbl)); + + mips_cpu_irq_init(DEC_CPU_IRQ_BASE); + init_ioasic_irqs(IO_IRQ_BASE); - dec_halt_init(&irq10); } /* dec_init_kn03 */ + + +void __init init_IRQ(void) +{ + switch (mips_machtype) { + case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */ + dec_init_kn01(); + break; + case MACH_DS5100: /* DS5100 MIPSmate */ + dec_init_kn230(); + break; + case MACH_DS5000_200: /* DS5000/200 3max */ + dec_init_kn02(); + break; + case MACH_DS5000_1XX: /* DS5000/1xx 3min */ + dec_init_kn02ba(); + break; + case MACH_DS5000_2X0: /* DS5000/240 3max+ */ + case MACH_DS5900: /* DS5900 bigmax */ + dec_init_kn03(); + break; + case MACH_DS5000_XX: /* Personal DS5000/xx */ + dec_init_kn02ca(); + break; + case MACH_DS5800: /* DS5800 Isis */ + panic("Don't know how to set this up!"); + break; + case MACH_DS5400: /* DS5400 MIPSfair */ + panic("Don't know how to set this up!"); + break; + case MACH_DS5500: /* DS5500 MIPSfair-2 */ + panic("Don't know how to set this up!"); + break; + } + set_except_vector(0, decstation_handle_int); + + /* Free the FPU interrupt if the exception is present. */ + if (!cpu_has_nofpuex) { + cpu_fpu_mask = 0; + dec_interrupt[DEC_IRQ_FPU] = -1; + } + + /* Register board interrupts: FPU and cascade. */ + if (dec_interrupt[DEC_IRQ_FPU] >= 0) + setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq); + if (dec_interrupt[DEC_IRQ_CASCADE] >= 0) + setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq); + + /* Register the bus error interrupt. */ + if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler) + setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq); + + /* Register the HALT interrupt. */ + if (dec_interrupt[DEC_IRQ_HALT] >= 0) + setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); +} + +EXPORT_SYMBOL(ioasic_base); +EXPORT_SYMBOL(dec_kn_slot_size); +EXPORT_SYMBOL(dec_interrupt); --- linux-2.5.73/arch/mips/dec/time.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/time.c 2003-06-27 15:56:23.000000000 -0700 @@ -2,12 +2,14 @@ * linux/arch/mips/dec/time.c * * Copyright (C) 1991, 1992, 1995 Linus Torvalds - * Copyright (C) 2000 Maciej W. Rozycki + * Copyright (C) 2000, 2003 Maciej W. Rozycki * * This file contains the time handling details for PC-style clocks as * found in some MIPS systems. * */ +#include +#include #include #include #include @@ -45,7 +47,9 @@ extern volatile unsigned long wall_jiffi /* This is for machines which generate the exact clock. */ #define USECS_PER_JIFFY (1000000/HZ) -#define USECS_PER_JIFFY_FRAC ((1000000ULL << 32) / HZ & 0xffffffff) +#define USECS_PER_JIFFY_FRAC ((u32)((1000000ULL << 32) / HZ)) + +#define TICK_SIZE (tick_nsec / 1000) /* Cycle counter value at the previous timer interrupt.. */ @@ -99,7 +103,7 @@ static unsigned long do_fast_gettimeoffs } } /* Get last timer tick in absolute kernel time */ - count = read_32bit_cp0_register(CP0_COUNT); + count = read_c0_count(); /* .. relative to previous jiffy (32 bits is enough) */ count -= timerlo; @@ -110,7 +114,7 @@ static unsigned long do_fast_gettimeoffs : "r" (count), "r" (quotient)); /* - * Due to possible jiffies inconsistencies, we need to check + * Due to possible jiffies inconsistencies, we need to check * the result so that we'll get a timer that is monotonic. */ if (res >= USECS_PER_JIFFY) @@ -140,7 +144,7 @@ static unsigned long do_ioasic_gettimeof } } /* Get last timer tick in absolute kernel time */ - count = ioasic_read(FCTR); + count = ioasic_read(IO_REG_FCTR); /* .. relative to previous jiffy (32 bits is enough) */ count -= timerlo; @@ -160,9 +164,9 @@ static unsigned long do_ioasic_gettimeof return res; } -/* This function must be called with interrupts disabled +/* This function must be called with interrupts disabled * It was inspired by Steve McCanne's microtime-i386 for BSD. -- jrs - * + * * However, the pc-audio speaker driver changes the divisor so that * it gets interrupted rather more often - it loads 64 into the * counter rather than 11932! This has an adverse impact on @@ -176,7 +180,7 @@ static unsigned long do_ioasic_gettimeof * using either the RTC or the 8253 timer. The decision would be * based on whether there was any other device around that needed * to trample on the 8253. I'd set up the RTC to interrupt at 1024 Hz, - * and then do some jiggery to have a version of do_timer that + * and then do some jiggery to have a version of do_timer that * advanced the clock by 1/1024 s. Every time that reached over 1/100 * of a second, then do all the old code. If the time was kept correct * then do_gettimeoffset could just return 0 - there is no low order @@ -187,13 +191,11 @@ static unsigned long do_ioasic_gettimeof * often than every 120 us or so. * * Anyway, this needs more thought.... pjsg (1993-08-28) - * + * * If you are really that interested, you should be reading * comp.protocols.time.ntp! */ -#define TICK_SIZE tick - static unsigned long do_slow_gettimeoffset(void) { /* @@ -206,57 +208,58 @@ static unsigned long do_slow_gettimeoffs static unsigned long (*do_gettimeoffset) (void) = do_slow_gettimeoffset; /* - * This version of gettimeofday has near microsecond resolution. + * This version of gettimeofday has microsecond resolution + * and better than microsecond precision on fast x86 machines with TSC. */ void do_gettimeofday(struct timeval *tv) { - unsigned long flags; unsigned long seq; + unsigned long usec, sec; do { - seq = read_seqbegin_irqsave(&xtime_lock, flags); - *tv = xtime; - tv->tv_usec += do_gettimeoffset(); - - /* - * xtime is atomically updated in timer_bh. jiffies - wall_jiffies - * is nonzero if the timer bottom half hasnt executed yet. - */ - if (jiffies - wall_jiffies) - tv->tv_usec += USECS_PER_JIFFY; - - } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); - + seq = read_seqbegin(&xtime_lock); + usec = do_gettimeoffset(); + { + unsigned long lost = jiffies - wall_jiffies; + if (lost) + usec += lost * (1000000 / HZ); + } + sec = xtime.tv_sec; + usec += (xtime.tv_nsec / 1000); + } while (read_seqretry(&xtime_lock, seq)); - if (tv->tv_usec >= 1000000) { - tv->tv_usec -= 1000000; - tv->tv_sec++; + while (usec >= 1000000) { + usec -= 1000000; + sec++; } + + tv->tv_sec = sec; + tv->tv_usec = usec; } void do_settimeofday(struct timeval *tv) { write_seqlock_irq(&xtime_lock); - - /* This is revolting. We need to set the xtime.tv_usec - * correctly. However, the value in this location is - * is value at the last tick. - * Discover what correction gettimeofday - * would have done, and then undo it! + /* + * This is revolting. We need to set "xtime" correctly. However, the + * value in this location is the value at the most recent update of + * wall time. Discover what correction gettimeofday() would have + * made, and then undo it! */ tv->tv_usec -= do_gettimeoffset(); + tv->tv_usec -= (jiffies - wall_jiffies) * (1000000 / HZ); - if (tv->tv_usec < 0) { + while (tv->tv_usec < 0) { tv->tv_usec += 1000000; tv->tv_sec--; } - xtime = *tv; + xtime.tv_sec = tv->tv_sec; + xtime.tv_nsec = (tv->tv_usec * 1000); time_adjust = 0; /* stop active adjtime() */ time_status |= STA_UNSYNC; time_maxerror = NTP_PHASE_LIMIT; time_esterror = NTP_PHASE_LIMIT; - write_sequnlock_irq(&xtime_lock); } @@ -281,7 +284,7 @@ static int set_rtc_mmss(unsigned long no cmos_minutes = CMOS_READ(RTC_MINUTES); if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) - BCD_TO_BIN(cmos_minutes); + cmos_minutes = BCD2BIN(cmos_minutes); /* * since we're only adjusting minutes and seconds, @@ -297,8 +300,8 @@ static int set_rtc_mmss(unsigned long no if (abs(real_minutes - cmos_minutes) < 30) { if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { - BIN_TO_BCD(real_seconds); - BIN_TO_BCD(real_minutes); + real_seconds = BIN2BCD(real_seconds); + real_minutes = BIN2BCD(real_minutes); } CMOS_WRITE(real_seconds, RTC_SECONDS); CMOS_WRITE(real_minutes, RTC_MINUTES); @@ -366,8 +369,8 @@ timer_interrupt(int irq, void *dev_id, s if ((time_status & STA_UNSYNC) == 0 && xtime.tv_sec > last_rtc_update + 660 - && xtime.tv_usec >= 500000 - tick / 2 - && xtime.tv_usec <= 500000 + tick / 2) { + && (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 + && (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { if (set_rtc_mmss(xtime.tv_sec) == 0) last_rtc_update = xtime.tv_sec; else @@ -381,7 +384,7 @@ timer_interrupt(int irq, void *dev_id, s rigged to be safe on the 386 - basically it's a hack, so don't look closely for now.. */ /*smp_message_pass(MSG_ALL_BUT_SELF, MSG_RESCHEDULE, 0L, 0); */ - + write_sequnlock(&xtime_lock); } static void r4k_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) @@ -392,7 +395,7 @@ static void r4k_timer_interrupt(int irq, * The cycle counter is only 32 bit which is good for about * a minute at current count rates of upto 150MHz or so. */ - count = read_32bit_cp0_register(CP0_COUNT); + count = read_c0_count(); timerhi += (count < timerlo); /* Wrap around */ timerlo = count; @@ -402,7 +405,7 @@ static void r4k_timer_interrupt(int irq, * update the timer[hi]/[lo] to make do_fast_gettimeoffset() * quotient calc still valid. -arca */ - write_32bit_cp0_register(CP0_COUNT, 0); + write_c0_count(0); timerhi = timerlo = 0; } @@ -417,7 +420,7 @@ static void ioasic_timer_interrupt(int i * The free-running counter is 32 bit which is good for about * 2 minutes, 50 seconds at possible count rates of upto 25MHz. */ - count = ioasic_read(FCTR); + count = ioasic_read(IO_REG_FCTR); timerhi += (count < timerlo); /* Wrap around */ timerlo = count; @@ -427,15 +430,18 @@ static void ioasic_timer_interrupt(int i * update the timer[hi]/[lo] to make do_fast_gettimeoffset() * quotient calc still valid. -arca */ - ioasic_write(FCTR, 0); + ioasic_write(IO_REG_FCTR, 0); timerhi = timerlo = 0; } timer_interrupt(irq, dev_id, regs); } -struct irqaction irq0 = {timer_interrupt, SA_INTERRUPT, 0, - "timer", NULL, NULL}; +struct irqaction irq0 = { + .handler = timer_interrupt, + .flags = SA_INTERRUPT, + .name = "timer", +}; void __init time_init(void) { @@ -463,12 +469,12 @@ void __init time_init(void) year = CMOS_READ(RTC_YEAR); } while (sec != CMOS_READ(RTC_SECONDS)); if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { - BCD_TO_BIN(sec); - BCD_TO_BIN(min); - BCD_TO_BIN(hour); - BCD_TO_BIN(day); - BCD_TO_BIN(mon); - BCD_TO_BIN(year); + sec = BCD2BIN(sec); + min = BCD2BIN(min); + hour = BCD2BIN(hour); + day = BCD2BIN(day); + mon = BCD2BIN(mon); + year = BCD2BIN(year); } /* * The PROM will reset the year to either '72 or '73. @@ -480,15 +486,15 @@ void __init time_init(void) write_seqlock_irq(&xtime_lock); xtime.tv_sec = mktime(year, mon, day, hour, min, sec); - xtime.tv_usec = 0; + xtime.tv_nsec = 0; write_sequnlock_irq(&xtime_lock); - if (mips_cpu.options & MIPS_CPU_COUNTER) { - write_32bit_cp0_register(CP0_COUNT, 0); + if (cpu_has_counter) { + write_c0_count(0); do_gettimeoffset = do_fast_gettimeoffset; irq0.handler = r4k_timer_interrupt; } else if (IOASIC) { - ioasic_write(FCTR, 0); + ioasic_write(IO_REG_FCTR, 0); do_gettimeoffset = do_ioasic_gettimeoffset; irq0.handler = ioasic_timer_interrupt; } --- linux-2.5.73/arch/mips/dec/wbflush.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/dec/wbflush.c 2003-06-27 15:56:23.000000000 -0700 @@ -11,15 +11,18 @@ * for more details. * * Copyright (C) 1998 Harald Koerfgen + * Copyright (C) 2002 Maciej W. Rozycki */ -#include #include +#include +#include +#include + static void wbflush_kn01(void); static void wbflush_kn210(void); -static void wbflush_kn02ba(void); -static void wbflush_kn03(void); +static void wbflush_mips(void); void (*__wbflush) (void); @@ -27,28 +30,24 @@ void __init wbflush_setup(void) { switch (mips_machtype) { case MACH_DS23100: - __wbflush = wbflush_kn01; - break; - case MACH_DS5100: /* DS5100 MIPSMATE */ - __wbflush = wbflush_kn210; - break; case MACH_DS5000_200: /* DS5000 3max */ - __wbflush = wbflush_kn01; - break; + __wbflush = wbflush_kn01; + break; + case MACH_DS5100: /* DS5100 MIPSMATE */ + __wbflush = wbflush_kn210; + break; case MACH_DS5000_1XX: /* DS5000/100 3min */ - __wbflush = wbflush_kn02ba; - break; - case MACH_DS5000_2X0: /* DS5000/240 3max+ */ - __wbflush = wbflush_kn03; - break; case MACH_DS5000_XX: /* Personal DS5000/2x */ - __wbflush = wbflush_kn02ba; - break; + case MACH_DS5000_2X0: /* DS5000/240 3max+ */ + case MACH_DS5900: /* DS5900 bigmax */ + default: + __wbflush = wbflush_mips; + break; } } /* - * For the DS3100 and DS5000/200 the writeback buffer functions + * For the DS3100 and DS5000/200 the R2020/R3220 writeback buffer functions * as part of Coprocessor 0. */ static void wbflush_kn01(void) @@ -78,29 +77,16 @@ static void wbflush_kn210(void) "mtc0\t$2,$12\n\t" "nop\n\t" ".set\tpop" - : : :"$2", "$3"); -} - -/* - * Looks like some magic with the System Interrupt Mask Register - * in the famous IOASIC for kmins and maxines. - */ -static void wbflush_kn02ba(void) -{ - asm(".set\tpush\n\t" - ".set\tnoreorder\n\t" - "lui\t$2,0xbc04\n\t" - "lw\t$3,0x120($2)\n\t" - "lw\t$3,0x120($2)\n\t" - ".set\tpop" - : : :"$2", "$3"); + : : : "$2", "$3"); } /* - * The DS500/2x0 doesn't need to write back the WB. + * I/O ASIC systems use a standard writeback buffer that gets flushed + * upon an uncached read. */ -static void wbflush_kn03(void) +static void wbflush_mips(void) { + __fast_iob(); } #include --- linux-2.5.73/arch/mips/defconfig 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/defconfig 2003-06-27 15:56:23.000000000 -0700 @@ -2,7 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -# CONFIG_SMP is not set +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set # # Code maturity level options @@ -10,89 +11,123 @@ CONFIG_MIPS=y CONFIG_EXPERIMENTAL=y # +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# # Machine selection # # CONFIG_ACER_PICA_61 is not set -# CONFIG_ALGOR_P4032 is not set # CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set # CONFIG_DECSTATION is not set -# CONFIG_DDB5074 is not set -# CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set # CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_NINO is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set # CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set # CONFIG_OLIVETTI_M700 is not set CONFIG_SGI_IP22=y +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set # CONFIG_SNI_RM200_PCI is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_PB1000 is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set +CONFIG_ARC=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_NONCOHERENT_IO=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_IRQ_CPU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_L1_CACHE_SHIFT=5 CONFIG_ARC32=y +# CONFIG_FB is not set +CONFIG_ARC_CONSOLE=y +CONFIG_ARC_PROMLIB=y CONFIG_BOARD_SCACHE=y -CONFIG_PC_KEYB=y -CONFIG_SGI=y -CONFIG_NEW_IRQ=y -CONFIG_OLD_TIME_C=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_PCI is not set -# CONFIG_I8259 is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y # # CPU selection # +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set CONFIG_CPU_R5000=y # CONFIG_CPU_R5432 is not set -# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set # CONFIG_CPU_SB1 is not set -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y -# CONFIG_CPU_HAS_WB is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set # -# General setup +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ISA is not set +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats # -# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_KCORE_ELF=y -CONFIG_ELF_KERNEL=y -CONFIG_BINFMT_IRIX=y -CONFIG_FORWARD_KEYBOARD=y -# CONFIG_ARC_CONSOLE is not set -# CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set -CONFIG_NET=y -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y +CONFIG_BINFMT_IRIX=y # # Memory Technology Devices (MTD) @@ -105,41 +140,90 @@ CONFIG_SYSCTL=y # CONFIG_PARPORT is not set # +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=y +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +# CONFIG_CHR_DEV_SG is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_REPORT_LUNS is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI low-level drivers +# +CONFIG_SGIWD93_SCSI=y +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_EATA_PIO is not set +# CONFIG_SCSI_DEBUG is not set + +# # Multi-device support (RAID and LVM) # # CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_BLK_DEV_LVM is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y # # Networking options # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK=y -CONFIG_RTNETLINK=y CONFIG_NETLINK_DEV=y # CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set CONFIG_UNIX=y +CONFIG_NET_KEY=y CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set @@ -153,20 +237,24 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_ARPD is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set # CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set +# CONFIG_XFRM_USER is not set # -# +# SCTP Configuration (EXPERIMENTAL) # -# CONFIG_IPX is not set -# CONFIG_ATALK is not set +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set # CONFIG_DECNET is not set # CONFIG_BRIDGE is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_LLC is not set # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set @@ -179,87 +267,10 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_NET_SCHED is not set # -# Telephony Support -# -# CONFIG_PHONE is not set -# CONFIG_PHONE_IXJ is not set -# CONFIG_PHONE_IXJ_PCMCIA is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -CONFIG_CHR_DEV_ST=y -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set -CONFIG_SR_EXTRA_DEVS=2 -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -CONFIG_SGIWD93_SCSI=y -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR_D700 is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Network device support +# Network testing # +# CONFIG_NET_PKTGEN is not set CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set @@ -270,33 +281,16 @@ CONFIG_NETDEVICES=y # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -# CONFIG_SUNLANCE is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set +# CONFIG_MII is not set CONFIG_SGISEEQ=y # # Ethernet (1000 Mbit) # -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set + +# +# Ethernet (10000 Mbit) +# # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -306,11 +300,8 @@ CONFIG_SGISEEQ=y # CONFIG_NET_RADIO is not set # -# Token Ring devices +# Token Ring devices (depends on LLC=y) # -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set # CONFIG_SHAPER is not set # @@ -331,21 +322,69 @@ CONFIG_SGISEEQ=y # # ISDN subsystem # -# CONFIG_ISDN is not set +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set # -# Old CD-ROM drivers (not SCSI, not IDE) +# Input device support +# +CONFIG_INPUT=y + # -# CONFIG_CD_NO_IDESCSI is not set +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Character devices # CONFIG_VT=y CONFIG_VT_CONSOLE=y -# CONFIG_SERIAL is not set -# CONFIG_SERIAL_EXTENDED is not set +CONFIG_HW_CONSOLE=y # CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_IP22_ZILOG=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 @@ -355,36 +394,58 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_I2C is not set # -# Mice +# I2C Hardware Sensors Mainboard support # -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set # -# Joysticks +# I2C Hardware Sensors Chip support # -# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_I2C_SENSOR is not set # -# Input core support is needed for gameports +# Mice # +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set # -# Input core support is needed for joysticks +# IPMI # -# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set # # Watchdog Cards # -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_WDT is not set +# CONFIG_WDTPCI is not set +# CONFIG_PCWATCHDOG is not set +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_ADVANTECH_WDT is not set +# CONFIG_EUROTECH_WDT is not set +# CONFIG_IB700_WDT is not set +# CONFIG_I810_TCO is not set +# CONFIG_MIXCOMWD is not set +# CONFIG_SCx200_WDT is not set +# CONFIG_60XX_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_MACHZ_WDT is not set +CONFIG_INDYDOG=y +# CONFIG_SC520_WDT is not set +# CONFIG_AMD7XX_TCO is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_SC1200_WDT is not set +# CONFIG_WAFER_WDT is not set +# CONFIG_CPU5_WDT is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +CONFIG_SGI_DS1286=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_SONYPI is not set # # Ftape, the floppy tape device driver @@ -392,6 +453,8 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set # # Multimedia devices @@ -399,89 +462,92 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_VIDEO_DEV is not set # -# SGI Character devices +# Digital Video Broadcasting Devices # -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_SGI_NEWPORT_CONSOLE=y -CONFIG_FONT_8x16=y -# CONFIG_PSMOUSE is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 +# CONFIG_DVB is not set # # File systems # +# CONFIG_EXT2_FS is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set -# CONFIG_CMS_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_JBD_DEBUG is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_TMPFS is not set -# CONFIG_RAMFS is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_FREEVXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set +# CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set # # Network File Systems # -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set -CONFIG_ROOT_NFS=y +# CONFIG_NFS_V4 is not set CONFIG_NFSD=y # CONFIG_NFSD_V3 is not set -CONFIG_SUNRPC=y +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y CONFIG_LOCKD=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set # CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set # CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types @@ -498,22 +564,33 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_LDM_PARTITION is not set +# CONFIG_NEC98_PARTITION is not set CONFIG_SGI_PARTITION=y # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set +# CONFIG_EFI_PARTITION is not set # -# Console drivers +# Graphics support +# + +# +# Console display driver support # # CONFIG_VGA_CONSOLE is not set # CONFIG_MDA_CONSOLE is not set +CONFIG_SGI_NEWPORT_CONSOLE=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_FONT_8x16=y # -# Frame-buffer support +# Logo configuration # -# CONFIG_FB is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_LOGO_SGI_CLUT224=y # # Sound @@ -521,124 +598,48 @@ CONFIG_SGI_PARTITION=y # CONFIG_SOUND is not set # -# SGI devices -# -CONFIG_SGI_SERIAL=y -# CONFIG_SERIAL_CONSOLE is not set -CONFIG_SGI_DS1286=y -# CONFIG_SGI_NEWPORT_GFX is not set - -# # USB support # -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set +# CONFIG_USB_GADGET is not set # -# USB Multimedia devices +# Bluetooth support # +# CONFIG_BT is not set # -# Video4Linux support is needed for USB Multimedia device support -# -# CONFIG_USB_DABUSB is not set - -# -# USB Network adaptors -# -# CONFIG_USB_PLUSB is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support +# Kernel hacking # -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_OMNINET is not set +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set # -# Miscellaneous USB drivers +# Security options # -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_ID75 is not set +# CONFIG_SECURITY is not set # -# Input core support +# Cryptographic options # -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_TEST is not set # -# Kernel hacking +# Library routines # -CONFIG_CROSSCOMPILE=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_MIPS_UNCACHED is not set +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y --- linux-2.5.73/arch/mips/defconfig-atlas 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/defconfig-atlas 2003-06-27 15:56:23.000000000 -0700 @@ -2,7 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -# CONFIG_SMP is not set +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set # # Code maturity level options @@ -10,82 +11,116 @@ CONFIG_MIPS=y CONFIG_EXPERIMENTAL=y # +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# # Machine selection # # CONFIG_ACER_PICA_61 is not set -# CONFIG_ALGOR_P4032 is not set # CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set # CONFIG_DECSTATION is not set -# CONFIG_DDB5074 is not set -# CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set CONFIG_MIPS_ATLAS=y -# CONFIG_MIPS_MALTA is not set -# CONFIG_NINO is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set # CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set # CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set # CONFIG_SNI_RM200_PCI is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_PB1000 is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_PCI=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_NONCOHERENT_IO=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_MIPS_BOARDS_GEN=y CONFIG_SWAP_IO_SPACE=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_I8259 is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set +CONFIG_BOOT_ELF32=y +CONFIG_L1_CACHE_SHIFT=5 +# CONFIG_FB is not set # # CPU selection # +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set -CONFIG_CPU_R5000=y +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set -# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set # CONFIG_CPU_SB1 is not set -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_VTAG_ICACHE is not set +# CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_LLDSCD=y -# CONFIG_CPU_HAS_WB is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set # -# General setup +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_NAMES=y +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats # -# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_KCORE_ELF=y -CONFIG_ELF_KERNEL=y -CONFIG_BINFMT_IRIX=y -# CONFIG_FORWARD_KEYBOARD is not set -# CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set -CONFIG_NET=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set +# CONFIG_BINFMT_IRIX is not set # # Memory Technology Devices (MTD) @@ -98,91 +133,36 @@ CONFIG_SYSVIPC=y # CONFIG_PARPORT is not set # +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_UMEM is not set +CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_INITRD is not set # -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# Networking options -# -# CONFIG_PACKET is not set -# CONFIG_NETLINK is not set -# CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_INET_ECN is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set - -# -# -# -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_DECNET is not set -# CONFIG_BRIDGE is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_LLC is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_FASTROUTE is not set -# CONFIG_NET_HW_FLOWCONTROL is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set -# CONFIG_PHONE_IXJ is not set -# CONFIG_PHONE_IXJ_PCMCIA is not set - -# -# ATA/IDE/MFM/RLL support +# ATA/ATAPI/MFM/RLL support # # CONFIG_IDE is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_HD is not set # -# SCSI support +# SCSI device support # CONFIG_SCSI=y @@ -190,7 +170,6 @@ CONFIG_SCSI=y # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set @@ -199,8 +178,8 @@ CONFIG_SD_EXTRA_DEVS=40 # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs # -# CONFIG_SCSI_DEBUG_QUEUES is not set # CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_REPORT_LUNS is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -208,53 +187,115 @@ CONFIG_SD_EXTRA_DEVS=40 # SCSI low-level drivers # # CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set # CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set +# CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set # CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set # CONFIG_SCSI_MEGARAID is not set # CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_CPQFCTS is not set # CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set # CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set # CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR_D700 is not set -# CONFIG_SCSI_NCR53C7xx is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_NCR53C8XX is not set # CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set # CONFIG_SCSI_PCI2000 is not set # CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set # CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set +# CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set +# CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # -# Network device support +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support # +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set CONFIG_NETDEVICES=y # @@ -265,39 +306,43 @@ CONFIG_NETDEVICES=y # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -# CONFIG_SUNLANCE is not set +# CONFIG_MII is not set # CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set # CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set # # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set # CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set +# CONFIG_E1000 is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set # CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set -# CONFIG_PLIP is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -307,9 +352,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_NET_RADIO is not set # -# Token Ring devices +# Token Ring devices (depends on LLC=y) # -# CONFIG_TR is not set # CONFIG_NET_FC is not set # CONFIG_RCPCI is not set # CONFIG_SHAPER is not set @@ -332,21 +376,65 @@ CONFIG_NET_ETHERNET=y # # ISDN subsystem # -# CONFIG_ISDN is not set +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set # -# Old CD-ROM drivers (not SCSI, not IDE) +# Input Device Drivers # -# CONFIG_CD_NO_IDESCSI is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Character devices # # CONFIG_VT is not set -CONFIG_SERIAL=y -CONFIG_SERIAL_CONSOLE=y -# CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 @@ -356,36 +444,35 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_I2C is not set # -# Mice +# I2C Hardware Sensors Mainboard support # -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set # -# Joysticks +# I2C Hardware Sensors Chip support # -# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_I2C_SENSOR is not set # -# Input core support is needed for gameports +# Mice # +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set # -# Input core support is needed for joysticks +# IPMI # -# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set -CONFIG_RTC=y +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_SONYPI is not set # # Ftape, the floppy tape device driver @@ -393,6 +480,8 @@ CONFIG_RTC=y # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set # # Multimedia devices @@ -400,86 +489,94 @@ CONFIG_RTC=y # CONFIG_VIDEO_DEV is not set # +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# # File systems # +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set -CONFIG_AUTOFS_FS=y +# CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set -# CONFIG_CMS_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_JBD_DEBUG is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set -CONFIG_EFS_FS=y -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set +# CONFIG_EFS_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_TMPFS is not set -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_FREEVXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set +# CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set # # Network File Systems # -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -CONFIG_ROOT_NFS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set # CONFIG_NFSD is not set -# CONFIG_NFSD_V3 is not set -CONFIG_SUNRPC=y +CONFIG_ROOT_NFS=y CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set # CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set # CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set + +# +# Graphics support +# # # Sound @@ -490,116 +587,30 @@ CONFIG_MSDOS_PARTITION=y # USB support # # CONFIG_USB is not set +# CONFIG_USB_GADGET is not set # -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices +# Bluetooth support # +# CONFIG_BT is not set # -# Video4Linux support is needed for USB Multimedia device support -# -# CONFIG_USB_DABUSB is not set - -# -# USB Network adaptors -# -# CONFIG_USB_PLUSB is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support +# Kernel hacking # -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_OMNINET is not set +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set # -# Miscellaneous USB drivers +# Security options # -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_ID75 is not set +# CONFIG_SECURITY is not set # -# Input core support +# Cryptographic options # -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set +# CONFIG_CRYPTO is not set # -# Kernel hacking +# Library routines # -CONFIG_CROSSCOMPILE=y -# CONFIG_REMOTE_DEBUG is not set -# CONFIG_GDB_CONSOLE is not set -# CONFIG_LL_DEBUG is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_MIPS_UNCACHED is not set +# CONFIG_CRC32 is not set --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-capcella 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,612 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +CONFIG_ZAO_CAPCELLA=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_VR41XX_TIME_C=y +CONFIG_DUMMY_KEYB=y +CONFIG_VR41XX_COMMON=y +CONFIG_NEW_PCI=y +# CONFIG_FB is not set + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +CONFIG_CPU_VR41XX=y +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_NAMES=y +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_IDEDISK_STROKE is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_TASKFILE_IO=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_BLK_DEV_IDEPCI is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_WDT is not set +# CONFIG_WDTPCI is not set +# CONFIG_PCWATCHDOG is not set +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_ADVANTECH_WDT is not set +# CONFIG_EUROTECH_WDT is not set +# CONFIG_IB700_WDT is not set +# CONFIG_I810_TCO is not set +# CONFIG_MIXCOMWD is not set +# CONFIG_SCx200_WDT is not set +# CONFIG_60XX_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_MACHZ_WDT is not set +# CONFIG_SC520_WDT is not set +# CONFIG_AMD7XX_TCO is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_SC1200_WDT is not set +# CONFIG_WAFER_WDT is not set +# CONFIG_CPU5_WDT is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_NFSD=y +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-cobalt 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,576 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +CONFIG_MIPS_COBALT=y +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_I8259=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_COBALT_LCD=y +# CONFIG_FB is not set + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +CONFIG_CPU_NEVADA=y +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_NAMES=y +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_IDEDISK_STROKE is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_TASKFILE_IO=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_BLK_DEV_IDEPCI is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=16 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +CONFIG_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +CONFIG_HANGCHECK_TIMER=y + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set --- linux-2.5.73/arch/mips/defconfig-ddb5476 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/defconfig-ddb5476 2003-06-27 15:56:23.000000000 -0700 @@ -2,7 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -# CONFIG_SMP is not set +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set # # Code maturity level options @@ -10,90 +11,113 @@ CONFIG_MIPS=y CONFIG_EXPERIMENTAL=y # +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# # Machine selection # # CONFIG_ACER_PICA_61 is not set -# CONFIG_ALGOR_P4032 is not set # CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set # CONFIG_DECSTATION is not set -# CONFIG_DDB5074 is not set -# CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set # CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_NINO is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set # CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set CONFIG_DDB5476=y # CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set # CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set # CONFIG_SNI_RM200_PCI is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_PB1000 is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_ISA=y -CONFIG_PCI=y -CONFIG_PC_KEYB=y -CONFIG_ROTTEN_IRQ=y +CONFIG_I8259=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_DDB5XXX_COMMON=y +CONFIG_NEW_PCI=y +CONFIG_FB=y CONFIG_HAVE_STD_PC_SERIAL_PORT=y -CONFIG_NEW_TIME_C=y -CONFIG_EISA=y -# CONFIG_I8259 is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set # # CPU selection # +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set CONFIG_CPU_R5432=y -# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set # CONFIG_CPU_SB1 is not set -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y -# CONFIG_CPU_HAS_WB is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set # -# General setup +# Bus options (PCI, PCMCIA, EISA, ISA, TC) # -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_KCORE_ELF=y -CONFIG_ELF_KERNEL=y -# CONFIG_BINFMT_AOUT is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set -CONFIG_NET=y -# CONFIG_PCI_NAMES is not set +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_NAMES=y +CONFIG_MMU=y # CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y # -# Plug and Play configuration +# Executable file formats # -# CONFIG_PNP is not set -# CONFIG_ISAPNP is not set -# CONFIG_PNPBIOS is not set +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set # # Memory Technology Devices (MTD) @@ -106,39 +130,93 @@ CONFIG_SYSCTL=y # CONFIG_PARPORT is not set # +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_IDEDISK_STROKE is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_TASKFILE_IO=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_BLK_DEV_IDEPCI is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# # Multi-device support (RAID and LVM) # # CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_BLK_DEV_LVM is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y # # Networking options # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK is not set +CONFIG_NETLINK_DEV=y # CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set CONFIG_UNIX=y +CONFIG_NET_KEY=y CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set @@ -148,22 +226,27 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set # CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set +# CONFIG_XFRM_USER is not set # -# +# SCTP Configuration (EXPERIMENTAL) # -# CONFIG_IPX is not set -# CONFIG_ATALK is not set +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set # CONFIG_DECNET is not set # CONFIG_BRIDGE is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_LLC is not set # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set @@ -176,84 +259,9 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_NET_SCHED is not set # -# Telephony Support -# -# CONFIG_PHONE is not set -# CONFIG_PHONE_IXJ is not set -# CONFIG_PHONE_IXJ_PCMCIA is not set - -# -# ATA/IDE/MFM/RLL support -# -CONFIG_IDE=y - -# -# IDE, ATA and ATAPI Block devices -# -CONFIG_BLK_DEV_IDE=y - -# -# Please see Documentation/ide.txt for help/info on IDE drives -# -# CONFIG_BLK_DEV_HD_IDE is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_BLK_DEV_IDEDISK=y -# CONFIG_IDEDISK_MULTI_MODE is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD640_ENHANCED is not set -# CONFIG_BLK_DEV_ISAPNP is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_IDEPCI_SHARE_IRQ is not set -# CONFIG_BLK_DEV_IDEDMA_PCI is not set -# CONFIG_BLK_DEV_OFFBOARD is not set -# CONFIG_IDEDMA_PCI_AUTO is not set -# CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set -# CONFIG_BLK_DEV_AEC62XX is not set -# CONFIG_AEC62XX_TUNING is not set -# CONFIG_BLK_DEV_ALI15X3 is not set -# CONFIG_WDC_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set -# CONFIG_AMD74XX_OVERRIDE is not set -# CONFIG_BLK_DEV_CMD64X is not set -# CONFIG_BLK_DEV_CY82C693 is not set -# CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set -# CONFIG_HPT34X_AUTODMA is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_OPTI621 is not set -# CONFIG_BLK_DEV_PDC202XX is not set -# CONFIG_PDC202XX_BURST is not set -# CONFIG_PDC202XX_FORCE is not set -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SIS5513 is not set -# CONFIG_BLK_DEV_TRM290 is not set -# CONFIG_BLK_DEV_VIA82CXXX is not set -# CONFIG_IDE_CHIPSETS is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_ATARAID is not set -# CONFIG_BLK_DEV_ATARAID_PDC is not set -# CONFIG_BLK_DEV_ATARAID_HPT is not set - -# -# SCSI support -# -# CONFIG_SCSI is not set - -# -# Network device support +# Network testing # +# CONFIG_NET_PKTGEN is not set CONFIG_NETDEVICES=y # @@ -264,70 +272,43 @@ CONFIG_NETDEVICES=y # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -# CONFIG_SUNLANCE is not set +# CONFIG_MII is not set # CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_AT1700 is not set -# CONFIG_DEPCA is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_AC3200 is not set -# CONFIG_APRICOT is not set -# CONFIG_CS89x0 is not set -CONFIG_TULIP=y -# CONFIG_TULIP_MWI is not set -# CONFIG_TULIP_MMIO is not set -# CONFIG_DE4X5 is not set -# CONFIG_DGRS is not set -# CONFIG_DM9102 is not set -CONFIG_EEPRO100=y -# CONFIG_LNE390 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -CONFIG_NE2K_PCI=y -# CONFIG_NE3210 is not set -# CONFIG_ES3210 is not set -# CONFIG_8139TOO is not set -# CONFIG_8139TOO_PIO is not set -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139TOO_8129 is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_LAN_SAA9730 is not set -# CONFIG_NET_POCKET is not set +# CONFIG_NET_PCI is not set # # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set # CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set +# CONFIG_E1000 is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set # CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set -# CONFIG_PLIP is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -337,10 +318,8 @@ CONFIG_NE2K_PCI=y # CONFIG_NET_RADIO is not set # -# Token Ring devices +# Token Ring devices (depends on LLC=y) # -# CONFIG_TR is not set -# CONFIG_NET_FC is not set # CONFIG_RCPCI is not set # CONFIG_SHAPER is not set @@ -362,22 +341,67 @@ CONFIG_NE2K_PCI=y # # ISDN subsystem # -# CONFIG_ISDN is not set +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set # -# Old CD-ROM drivers (not SCSI, not IDE) +# Input I/O drivers # -# CONFIG_CD_NO_IDESCSI is not set +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Character devices # CONFIG_VT=y # CONFIG_VT_CONSOLE is not set -CONFIG_SERIAL=y -CONFIG_SERIAL_CONSOLE=y -# CONFIG_SERIAL_EXTENDED is not set +CONFIG_HW_CONSOLE=y # CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 @@ -387,39 +411,35 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_I2C is not set # -# Mice +# I2C Hardware Sensors Mainboard support # -# CONFIG_BUSMOUSE is not set -CONFIG_MOUSE=y -CONFIG_PSMOUSE=y -# CONFIG_82C710_MOUSE is not set -# CONFIG_PC110_PAD is not set # -# Joysticks +# I2C Hardware Sensors Chip support # -# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_I2C_SENSOR is not set # -# Input core support is needed for gameports +# Mice # +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set # -# Input core support is needed for joysticks +# IPMI # -# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_SONYPI is not set # # Ftape, the floppy tape device driver @@ -427,6 +447,8 @@ CONFIG_PSMOUSE=y # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set # # Multimedia devices @@ -434,238 +456,157 @@ CONFIG_PSMOUSE=y # CONFIG_VIDEO_DEV is not set # +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# # File systems # +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set -# CONFIG_CMS_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_JBD_DEBUG is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_TMPFS is not set -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_FREEVXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set +# CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set # # Network File Systems # -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set -CONFIG_ROOT_NFS=y +# CONFIG_NFS_V4 is not set # CONFIG_NFSD is not set -# CONFIG_NFSD_V3 is not set -CONFIG_SUNRPC=y +CONFIG_ROOT_NFS=y CONFIG_LOCKD=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set # CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set # CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set - -# -# Console drivers -# -# CONFIG_VGA_CONSOLE is not set -# CONFIG_MDA_CONSOLE is not set # -# Frame-buffer support +# Graphics support # -CONFIG_FB=y -CONFIG_DUMMY_CONSOLE=y -# CONFIG_FB_RIVA is not set -# CONFIG_FB_CLGEN is not set +# CONFIG_FB_CIRRUS is not set # CONFIG_FB_PM2 is not set # CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_E1355 is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_RIVA is not set # CONFIG_FB_MATROX is not set -# CONFIG_FB_ATY is not set # CONFIG_FB_RADEON is not set # CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set # CONFIG_FB_SIS is not set -CONFIG_FB_3DFX=y +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_E1356 is not set # CONFIG_FB_VIRTUAL is not set -# CONFIG_FBCON_ADVANCED is not set -CONFIG_FBCON_CFB8=y -CONFIG_FBCON_CFB16=y -CONFIG_FBCON_CFB32=y -# CONFIG_FBCON_FONTWIDTH8_ONLY is not set -# CONFIG_FBCON_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y - -# -# Sound -# -# CONFIG_SOUND is not set # -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - +# Console display driver support # -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set # -# USB Multimedia devices +# Logo configuration # +# CONFIG_LOGO is not set # -# Video4Linux support is needed for USB Multimedia device support +# Sound # -# CONFIG_USB_DABUSB is not set +# CONFIG_SOUND is not set # -# USB Network adaptors +# USB support # -# CONFIG_USB_PLUSB is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set # -# USB port drivers +# Bluetooth support # -# CONFIG_USB_USS720 is not set +# CONFIG_BT is not set # -# USB Serial Converter support +# Kernel hacking # -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_OMNINET is not set +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set # -# Miscellaneous USB drivers +# Security options # -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_ID75 is not set +# CONFIG_SECURITY is not set # -# Input core support +# Cryptographic options # -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set +# CONFIG_CRYPTO is not set # -# Kernel hacking +# Library routines # -CONFIG_CROSSCOMPILE=y -# CONFIG_REMOTE_DEBUG is not set -# CONFIG_GDB_CONSOLE is not set -# CONFIG_LL_DEBUG is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_MIPS_UNCACHED is not set +# CONFIG_CRC32 is not set --- linux-2.5.73/arch/mips/defconfig-ddb5477 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/defconfig-ddb5477 2003-06-27 15:56:23.000000000 -0700 @@ -2,7 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -# CONFIG_SMP is not set +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set # # Code maturity level options @@ -10,82 +11,114 @@ CONFIG_MIPS=y CONFIG_EXPERIMENTAL=y # +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# # Machine selection # # CONFIG_ACER_PICA_61 is not set -# CONFIG_ALGOR_P4032 is not set # CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set # CONFIG_DECSTATION is not set -# CONFIG_DDB5074 is not set -# CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set # CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_NINO is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set # CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set CONFIG_DDB5477=y +CONFIG_DDB5477_BUS_FREQUENCY=0 +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set # CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set # CONFIG_SNI_RM200_PCI is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_PB1000 is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set +CONFIG_I8259=y +CONFIG_NONCOHERENT_IO=y CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_PCI=y -CONFIG_NEW_TIME_C=y -CONFIG_NEW_IRQ=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_I8259 is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set +CONFIG_IRQ_CPU=y +CONFIG_DUMMY_KEYB=y +CONFIG_DDB5XXX_COMMON=y +CONFIG_NEW_PCI=y +# CONFIG_FB is not set # # CPU selection # +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set CONFIG_CPU_R5432=y -# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set # CONFIG_CPU_SB1 is not set -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y -# CONFIG_CPU_HAS_WB is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set # -# General setup +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_NAMES=y +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats # -CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_KCORE_ELF=y -CONFIG_ELF_KERNEL=y -# CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set -CONFIG_NET=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y # # Memory Technology Devices (MTD) @@ -98,39 +131,71 @@ CONFIG_SYSCTL=y # CONFIG_PARPORT is not set # +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# # Multi-device support (RAID and LVM) # # CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_BLK_DEV_LVM is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y # # Networking options # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK is not set +CONFIG_NETLINK_DEV=y # CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set CONFIG_UNIX=y +CONFIG_NET_KEY=y CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set @@ -140,22 +205,27 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set # CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set +# CONFIG_XFRM_USER is not set # -# +# SCTP Configuration (EXPERIMENTAL) # -# CONFIG_IPX is not set -# CONFIG_ATALK is not set +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set # CONFIG_DECNET is not set # CONFIG_BRIDGE is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_LLC is not set # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set @@ -168,27 +238,9 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_NET_SCHED is not set # -# Telephony Support -# -# CONFIG_PHONE is not set -# CONFIG_PHONE_IXJ is not set -# CONFIG_PHONE_IXJ_PCMCIA is not set - -# -# ATA/IDE/MFM/RLL support -# -# CONFIG_IDE is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI support -# -# CONFIG_SCSI is not set - -# -# Network device support +# Network testing # +# CONFIG_NET_PKTGEN is not set CONFIG_NETDEVICES=y # @@ -199,67 +251,43 @@ CONFIG_NETDEVICES=y # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -# CONFIG_SUNLANCE is not set +# CONFIG_MII is not set # CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set # CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_APRICOT is not set -# CONFIG_CS89x0 is not set -CONFIG_TULIP=y -# CONFIG_TULIP_MWI is not set -# CONFIG_TULIP_MMIO is not set -# CONFIG_DE4X5 is not set -# CONFIG_DGRS is not set -# CONFIG_DM9102 is not set -# CONFIG_EEPRO100 is not set -# CONFIG_LNE390 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_NE3210 is not set -# CONFIG_ES3210 is not set -# CONFIG_8139TOO is not set -# CONFIG_8139TOO_PIO is not set -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139TOO_8129 is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_LAN_SAA9730 is not set -# CONFIG_NET_POCKET is not set +# CONFIG_NET_PCI is not set # # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set # CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set +# CONFIG_E1000 is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set # CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set -# CONFIG_PLIP is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -269,10 +297,8 @@ CONFIG_TULIP=y # CONFIG_NET_RADIO is not set # -# Token Ring devices +# Token Ring devices (depends on LLC=y) # -# CONFIG_TR is not set -# CONFIG_NET_FC is not set # CONFIG_RCPCI is not set # CONFIG_SHAPER is not set @@ -294,22 +320,67 @@ CONFIG_TULIP=y # # ISDN subsystem # -# CONFIG_ISDN is not set +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set # -# Old CD-ROM drivers (not SCSI, not IDE) +# Input device support # -# CONFIG_CD_NO_IDESCSI is not set +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Character devices # # CONFIG_VT is not set -CONFIG_SERIAL=y -CONFIG_SERIAL_CONSOLE=y -# CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_UNIX98_PTYS is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 # # I2C support @@ -317,36 +388,35 @@ CONFIG_SERIAL_CONSOLE=y # CONFIG_I2C is not set # -# Mice +# I2C Hardware Sensors Mainboard support # -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set # -# Joysticks +# I2C Hardware Sensors Chip support # -# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_I2C_SENSOR is not set # -# Input core support is needed for gameports +# Mice # +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set # -# Input core support is needed for joysticks +# IPMI # -# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_SONYPI is not set # # Ftape, the floppy tape device driver @@ -354,6 +424,8 @@ CONFIG_SERIAL_CONSOLE=y # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set # # Multimedia devices @@ -361,206 +433,158 @@ CONFIG_SERIAL_CONSOLE=y # CONFIG_VIDEO_DEV is not set # +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# # File systems # +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set -# CONFIG_CMS_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_JBD_DEBUG is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_TMPFS is not set -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_FREEVXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set +# CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -# CONFIG_DEVPTS_FS is not set # CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set # # Network File Systems # -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set -CONFIG_ROOT_NFS=y +# CONFIG_NFS_V4 is not set CONFIG_NFSD=y # CONFIG_NFSD_V3 is not set -CONFIG_SUNRPC=y +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y CONFIG_LOCKD=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set # CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set # CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set # -# Sound +# Graphics support # -# CONFIG_SOUND is not set # -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices +# Sound # -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set +CONFIG_SOUND=y # -# USB Multimedia devices +# Advanced Linux Sound Architecture # +# CONFIG_SND is not set # -# Video4Linux support is needed for USB Multimedia device support -# -# CONFIG_USB_DABUSB is not set +# Open Sound System +# +CONFIG_SOUND_PRIME=y +# CONFIG_SOUND_BT878 is not set +# CONFIG_SOUND_CMPCI is not set +# CONFIG_SOUND_EMU10K1 is not set +# CONFIG_SOUND_FUSION is not set +# CONFIG_SOUND_CS4281 is not set +# CONFIG_SOUND_ES1370 is not set +# CONFIG_SOUND_ES1371 is not set +# CONFIG_SOUND_ESSSOLO1 is not set +# CONFIG_SOUND_MAESTRO is not set +# CONFIG_SOUND_MAESTRO3 is not set +# CONFIG_SOUND_ICH is not set +# CONFIG_SOUND_RME96XX is not set +# CONFIG_SOUND_SONICVIBES is not set +CONFIG_SOUND_VRC5477=y +# CONFIG_SOUND_TRIDENT is not set +# CONFIG_SOUND_MSNDCLAS is not set +# CONFIG_SOUND_MSNDPIN is not set +# CONFIG_SOUND_VIA82CXXX is not set +# CONFIG_SOUND_OSS is not set # -# USB Network adaptors +# USB support # -# CONFIG_USB_PLUSB is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set # -# USB port drivers +# Bluetooth support # -# CONFIG_USB_USS720 is not set +# CONFIG_BT is not set # -# USB Serial Converter support +# Kernel hacking # -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_OMNINET is not set +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set # -# Miscellaneous USB drivers +# Security options # -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_ID75 is not set +# CONFIG_SECURITY is not set # -# Input core support +# Cryptographic options # -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set +# CONFIG_CRYPTO is not set # -# Kernel hacking +# Library routines # -CONFIG_CROSSCOMPILE=y -# CONFIG_REMOTE_DEBUG is not set -# CONFIG_GDB_CONSOLE is not set -CONFIG_LL_DEBUG=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_MIPS_UNCACHED is not set +# CONFIG_CRC32 is not set --- linux-2.5.73/arch/mips/defconfig-decstation 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/defconfig-decstation 2003-06-27 15:56:23.000000000 -0700 @@ -2,7 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -# CONFIG_SMP is not set +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set # # Code maturity level options @@ -10,81 +11,113 @@ CONFIG_MIPS=y CONFIG_EXPERIMENTAL=y # +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# # Machine selection # # CONFIG_ACER_PICA_61 is not set -# CONFIG_ALGOR_P4032 is not set # CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set CONFIG_DECSTATION=y -# CONFIG_DDB5074 is not set -# CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set # CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_NINO is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set # CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set # CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set # CONFIG_SNI_RM200_PCI is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_PB1000 is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_PCI is not set -# CONFIG_I8259 is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_BOOT_ELF32=y +CONFIG_L1_CACHE_SHIFT=4 +# CONFIG_FB is not set # # CPU selection # +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set CONFIG_CPU_R3000=y -# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set -# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set # CONFIG_CPU_SB1 is not set -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_ADVANCED is not set -# CONFIG_CPU_HAS_LLSC is not set -# CONFIG_CPU_HAS_LLDSCD is not set -# CONFIG_CPU_HAS_WB is not set +CONFIG_CPU_HAS_WB=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set # -# General setup +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_TC=y +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats # -CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_KCORE_ELF=y -CONFIG_ELF_KERNEL=y -# CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set -CONFIG_NET=y -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -CONFIG_TC=y # # Memory Technology Devices (MTD) @@ -97,39 +130,90 @@ CONFIG_TC=y # CONFIG_PARPORT is not set # +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_REPORT_LUNS is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI low-level drivers +# +CONFIG_SCSI_DECNCR=y +# CONFIG_SCSI_DECSII is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_EATA_PIO is not set +# CONFIG_SCSI_DEBUG is not set + +# # Multi-device support (RAID and LVM) # # CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_BLK_DEV_LVM is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y # # Networking options # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK is not set +CONFIG_NETLINK_DEV=y # CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set CONFIG_UNIX=y +CONFIG_NET_KEY=y CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set @@ -139,22 +223,27 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set # CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set +# CONFIG_XFRM_USER is not set # -# +# SCTP Configuration (EXPERIMENTAL) # -# CONFIG_IPX is not set -# CONFIG_ATALK is not set +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set # CONFIG_DECNET is not set # CONFIG_BRIDGE is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_LLC is not set # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set @@ -167,122 +256,30 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_NET_SCHED is not set # -# Telephony Support -# -# CONFIG_PHONE is not set -# CONFIG_PHONE_IXJ is not set -# CONFIG_PHONE_IXJ_PCMCIA is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -CONFIG_SCSI_DECNCR=y -# CONFIG_SCSI_DECSII is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR_D700 is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Network device support +# Network testing # +# CONFIG_NET_PKTGEN is not set CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -# CONFIG_SUNLANCE is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set +# CONFIG_MII is not set CONFIG_DECLANCE=y # # Ethernet (1000 Mbit) # -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set + +# +# Ethernet (10000 Mbit) +# # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -292,11 +289,8 @@ CONFIG_DECLANCE=y # CONFIG_NET_RADIO is not set # -# Token Ring devices +# Token Ring devices (depends on LLC=y) # -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set # CONFIG_SHAPER is not set # @@ -317,21 +311,64 @@ CONFIG_DECLANCE=y # # ISDN subsystem # -# CONFIG_ISDN is not set +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y # -# Old CD-ROM drivers (not SCSI, not IDE) +# Userland interfaces # -# CONFIG_CD_NO_IDESCSI is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Character devices # # CONFIG_VT is not set -CONFIG_SERIAL=y -CONFIG_SERIAL_CONSOLE=y -# CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_DZ=y +CONFIG_SERIAL_DZ_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 @@ -341,36 +378,35 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_I2C is not set # -# Mice +# I2C Hardware Sensors Mainboard support # -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set # -# Joysticks +# I2C Hardware Sensors Chip support # -# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_I2C_SENSOR is not set # -# Input core support is needed for gameports +# Mice # +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set # -# Input core support is needed for joysticks +# IPMI # -# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_SONYPI is not set # # Ftape, the floppy tape device driver @@ -378,6 +414,8 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set # # Multimedia devices @@ -385,90 +423,81 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_VIDEO_DEV is not set # -# DECStation Character devices +# Digital Video Broadcasting Devices # -# CONFIG_VT is not set -CONFIG_SERIAL=y -# CONFIG_DZ is not set -CONFIG_ZS=y -CONFIG_SERIAL_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 -# CONFIG_RTC is not set +# CONFIG_DVB is not set # # File systems # +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set -# CONFIG_CMS_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_JBD_DEBUG is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_TMPFS is not set -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_FREEVXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set +# CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set # # Network File Systems # -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set # CONFIG_NFS_FS is not set -# CONFIG_NFS_V3 is not set -# CONFIG_ROOT_NFS is not set # CONFIG_NFSD is not set -# CONFIG_NFSD_V3 is not set -# CONFIG_SUNRPC is not set -# CONFIG_LOCKD is not set +# CONFIG_EXPORTFS is not set # CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set # CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types @@ -485,126 +514,48 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_LDM_PARTITION is not set +# CONFIG_NEC98_PARTITION is not set # CONFIG_SGI_PARTITION is not set CONFIG_ULTRIX_PARTITION=y # CONFIG_SUN_PARTITION is not set -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set - -# -# USB support -# -# CONFIG_USB is not set +# CONFIG_EFI_PARTITION is not set # -# USB Controllers +# Graphics support # -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set # -# USB Device Class drivers +# Sound # -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set +# CONFIG_SOUND is not set # -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# -# CONFIG_USB_DABUSB is not set - -# -# USB Network adaptors +# USB support # -# CONFIG_USB_PLUSB is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set +# CONFIG_USB_GADGET is not set # -# USB port drivers +# Bluetooth support # -# CONFIG_USB_USS720 is not set +# CONFIG_BT is not set # -# USB Serial Converter support +# Kernel hacking # -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_OMNINET is not set +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set # -# Miscellaneous USB drivers +# Security options # -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_ID75 is not set +# CONFIG_SECURITY is not set # -# Input core support +# Cryptographic options # -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set +# CONFIG_CRYPTO is not set # -# Kernel hacking +# Library routines # -CONFIG_CROSSCOMPILE=y -# CONFIG_REMOTE_DEBUG is not set -# CONFIG_GDB_CONSOLE is not set -# CONFIG_LL_DEBUG is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_MIPS_UNCACHED is not set +# CONFIG_CRC32 is not set --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-e55 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,564 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +CONFIG_CASIO_E55=y +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_VR41XX_TIME_C=y +CONFIG_DUMMY_KEYB=y +CONFIG_VR41XX_COMMON=y +# CONFIG_FB is not set + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +CONFIG_CPU_VR41XX=y +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_IDEDISK_STROKE is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_TASKFILE_IO=y + +# +# IDE chipset support/bugfixes +# + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_WDT is not set +# CONFIG_WDTPCI is not set +# CONFIG_PCWATCHDOG is not set +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_ADVANTECH_WDT is not set +# CONFIG_EUROTECH_WDT is not set +# CONFIG_IB700_WDT is not set +# CONFIG_I810_TCO is not set +# CONFIG_MIXCOMWD is not set +# CONFIG_SCx200_WDT is not set +# CONFIG_60XX_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_MACHZ_WDT is not set +# CONFIG_SC520_WDT is not set +# CONFIG_AMD7XX_TCO is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_SC1200_WDT is not set +# CONFIG_WAFER_WDT is not set +# CONFIG_CPU5_WDT is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_NFSD=y +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_LOCKD=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-eagle 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,728 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +CONFIG_NEC_EAGLE=y +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_VR41XX_TIME_C=y +CONFIG_DUMMY_KEYB=y +CONFIG_VR41XX_COMMON=y +CONFIG_VRC4173=y +CONFIG_NEW_PCI=y +# CONFIG_FB is not set + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +CONFIG_CPU_VR41XX=y +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_NAMES=y +CONFIG_MMU=y +CONFIG_HOTPLUG=y + +# +# PCMCIA/CardBus support +# +CONFIG_PCMCIA=y +# CONFIG_YENTA is not set +# CONFIG_I82092 is not set +# CONFIG_TCIC is not set +# CONFIG_PCMCIA_VRC4173 is not set + +# +# PCI Hotplug Support +# +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_PARTITIONS is not set +# CONFIG_MTD_CONCAT is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x1c000000 +CONFIG_MTD_PHYSMAP_LEN=0x2000000 +CONFIG_MTD_PHYSMAP_BUSWIDTH=4 + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +CONFIG_IDEDISK_MULTI_MODE=y +# CONFIG_IDEDISK_STROKE is not set +CONFIG_BLK_DEV_IDECS=y +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_TASKFILE_IO=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_BLK_DEV_IDEPCI is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# PCMCIA network device support +# +CONFIG_NET_PCMCIA=y +# CONFIG_PCMCIA_3C589 is not set +# CONFIG_PCMCIA_3C574 is not set +CONFIG_PCMCIA_FMVJ18X=y +CONFIG_PCMCIA_PCNET=m +# CONFIG_PCMCIA_NMCLAN is not set +# CONFIG_PCMCIA_SMC91C92 is not set +# CONFIG_PCMCIA_XIRC2PS is not set +# CONFIG_PCMCIA_AXNET is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_CS is not set +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_WDT is not set +# CONFIG_WDTPCI is not set +# CONFIG_PCWATCHDOG is not set +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_ADVANTECH_WDT is not set +# CONFIG_EUROTECH_WDT is not set +# CONFIG_IB700_WDT is not set +# CONFIG_I810_TCO is not set +# CONFIG_MIXCOMWD is not set +# CONFIG_SCx200_WDT is not set +# CONFIG_60XX_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_MACHZ_WDT is not set +# CONFIG_SC520_WDT is not set +# CONFIG_AMD7XX_TCO is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_SC1200_WDT is not set +# CONFIG_WAFER_WDT is not set +# CONFIG_CPU5_WDT is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS_FS=y +CONFIG_JFFS_FS_VERBOSE=0 +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_NAND is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_NFSD=y +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_BLOWFISH is not set +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_TEST is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-ev64120 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,571 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +# CONFIG_KMOD is not set + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +CONFIG_MIPS_EV64120=y +# CONFIG_EVB_PCI1 is not set +CONFIG_SYSCLK_100=y +# CONFIG_SYSCLK_75 is not set +# CONFIG_SYSCLK_83 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_CONFIG_GT64120=y +CONFIG_NONCOHERENT_IO=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_MIPS_GT64120=y +# CONFIG_FB is not set + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +CONFIG_CPU_R5000=y +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_NAMES=y +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_BINFMT_IRIX is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=y +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=y +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_PPP_DEFLATE is not set +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPPOE is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_CONSOLE is not set +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-ev96100 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,523 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +# CONFIG_KMOD is not set + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +CONFIG_MIPS_EV96100=y +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_NONCOHERENT_IO=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_NEW_PCI=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_MIPS_GT96100=y +# CONFIG_FB is not set +CONFIG_BOARD_SCACHE=y + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +CONFIG_CPU_RM7000=y +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_PCI is not set +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_BINFMT_IRIX is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +CONFIG_MIPS_GT96100ETH=y + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set --- linux-2.5.73/arch/mips/defconfig-ip22 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/defconfig-ip22 2003-06-27 15:56:23.000000000 -0700 @@ -2,7 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -# CONFIG_SMP is not set +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set # # Code maturity level options @@ -10,89 +11,123 @@ CONFIG_MIPS=y CONFIG_EXPERIMENTAL=y # +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# # Machine selection # # CONFIG_ACER_PICA_61 is not set -# CONFIG_ALGOR_P4032 is not set # CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set # CONFIG_DECSTATION is not set -# CONFIG_DDB5074 is not set -# CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set # CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_NINO is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set # CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set # CONFIG_OLIVETTI_M700 is not set CONFIG_SGI_IP22=y +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set # CONFIG_SNI_RM200_PCI is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_PB1000 is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set +CONFIG_ARC=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_NONCOHERENT_IO=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_IRQ_CPU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_L1_CACHE_SHIFT=5 CONFIG_ARC32=y +# CONFIG_FB is not set +CONFIG_ARC_CONSOLE=y +CONFIG_ARC_PROMLIB=y CONFIG_BOARD_SCACHE=y -CONFIG_PC_KEYB=y -CONFIG_SGI=y -CONFIG_NEW_IRQ=y -CONFIG_OLD_TIME_C=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_PCI is not set -# CONFIG_I8259 is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y # # CPU selection # +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set CONFIG_CPU_R5000=y # CONFIG_CPU_R5432 is not set -# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set # CONFIG_CPU_SB1 is not set -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set +# CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_LLDSCD=y -# CONFIG_CPU_HAS_WB is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set # -# General setup +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ISA is not set +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats # -# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_KCORE_ELF=y -CONFIG_ELF_KERNEL=y -CONFIG_BINFMT_IRIX=y -CONFIG_FORWARD_KEYBOARD=y -# CONFIG_ARC_CONSOLE is not set -# CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set -CONFIG_NET=y -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y +CONFIG_BINFMT_IRIX=y # # Memory Technology Devices (MTD) @@ -105,41 +140,90 @@ CONFIG_SYSCTL=y # CONFIG_PARPORT is not set # +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=y +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +# CONFIG_CHR_DEV_SG is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_REPORT_LUNS is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI low-level drivers +# +CONFIG_SGIWD93_SCSI=y +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_EATA_PIO is not set +# CONFIG_SCSI_DEBUG is not set + +# # Multi-device support (RAID and LVM) # # CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_BLK_DEV_LVM is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y # # Networking options # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y -CONFIG_NETLINK=y -CONFIG_RTNETLINK=y CONFIG_NETLINK_DEV=y # CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set CONFIG_UNIX=y +CONFIG_NET_KEY=y CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set @@ -153,20 +237,24 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_ARPD is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set # CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set +# CONFIG_XFRM_USER is not set # -# +# SCTP Configuration (EXPERIMENTAL) # -# CONFIG_IPX is not set -# CONFIG_ATALK is not set +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set # CONFIG_DECNET is not set # CONFIG_BRIDGE is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_LLC is not set # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set @@ -179,87 +267,10 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_NET_SCHED is not set # -# Telephony Support -# -# CONFIG_PHONE is not set -# CONFIG_PHONE_IXJ is not set -# CONFIG_PHONE_IXJ_PCMCIA is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -CONFIG_CHR_DEV_ST=y -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set -CONFIG_SR_EXTRA_DEVS=2 -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -CONFIG_SGIWD93_SCSI=y -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR_D700 is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Network device support +# Network testing # +# CONFIG_NET_PKTGEN is not set CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set @@ -270,33 +281,16 @@ CONFIG_NETDEVICES=y # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -# CONFIG_SUNLANCE is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set +# CONFIG_MII is not set CONFIG_SGISEEQ=y # # Ethernet (1000 Mbit) # -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set + +# +# Ethernet (10000 Mbit) +# # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -306,11 +300,8 @@ CONFIG_SGISEEQ=y # CONFIG_NET_RADIO is not set # -# Token Ring devices +# Token Ring devices (depends on LLC=y) # -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set # CONFIG_SHAPER is not set # @@ -331,21 +322,69 @@ CONFIG_SGISEEQ=y # # ISDN subsystem # -# CONFIG_ISDN is not set +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set # -# Old CD-ROM drivers (not SCSI, not IDE) +# Input device support +# +CONFIG_INPUT=y + # -# CONFIG_CD_NO_IDESCSI is not set +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Character devices # CONFIG_VT=y CONFIG_VT_CONSOLE=y -# CONFIG_SERIAL is not set -# CONFIG_SERIAL_EXTENDED is not set +CONFIG_HW_CONSOLE=y # CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_IP22_ZILOG=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 @@ -355,36 +394,58 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_I2C is not set # -# Mice +# I2C Hardware Sensors Mainboard support # -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set # -# Joysticks +# I2C Hardware Sensors Chip support # -# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_I2C_SENSOR is not set # -# Input core support is needed for gameports +# Mice # +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set # -# Input core support is needed for joysticks +# IPMI # -# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set # # Watchdog Cards # -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_WDT is not set +# CONFIG_WDTPCI is not set +# CONFIG_PCWATCHDOG is not set +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_ADVANTECH_WDT is not set +# CONFIG_EUROTECH_WDT is not set +# CONFIG_IB700_WDT is not set +# CONFIG_I810_TCO is not set +# CONFIG_MIXCOMWD is not set +# CONFIG_SCx200_WDT is not set +# CONFIG_60XX_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_MACHZ_WDT is not set +CONFIG_INDYDOG=y +# CONFIG_SC520_WDT is not set +# CONFIG_AMD7XX_TCO is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_SC1200_WDT is not set +# CONFIG_WAFER_WDT is not set +# CONFIG_CPU5_WDT is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +CONFIG_SGI_DS1286=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_SONYPI is not set # # Ftape, the floppy tape device driver @@ -392,6 +453,8 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set # # Multimedia devices @@ -399,89 +462,92 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_VIDEO_DEV is not set # -# SGI Character devices +# Digital Video Broadcasting Devices # -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_SGI_NEWPORT_CONSOLE=y -CONFIG_FONT_8x16=y -# CONFIG_PSMOUSE is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 +# CONFIG_DVB is not set # # File systems # +# CONFIG_EXT2_FS is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set -# CONFIG_CMS_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_JBD_DEBUG is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_TMPFS is not set -# CONFIG_RAMFS is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_FREEVXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set +# CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set # # Network File Systems # -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set -CONFIG_ROOT_NFS=y +# CONFIG_NFS_V4 is not set CONFIG_NFSD=y # CONFIG_NFSD_V3 is not set -CONFIG_SUNRPC=y +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y CONFIG_LOCKD=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set # CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set # CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types @@ -498,22 +564,33 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_LDM_PARTITION is not set +# CONFIG_NEC98_PARTITION is not set CONFIG_SGI_PARTITION=y # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set +# CONFIG_EFI_PARTITION is not set # -# Console drivers +# Graphics support +# + +# +# Console display driver support # # CONFIG_VGA_CONSOLE is not set # CONFIG_MDA_CONSOLE is not set +CONFIG_SGI_NEWPORT_CONSOLE=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_FONT_8x16=y # -# Frame-buffer support +# Logo configuration # -# CONFIG_FB is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_LOGO_SGI_CLUT224=y # # Sound @@ -521,124 +598,48 @@ CONFIG_SGI_PARTITION=y # CONFIG_SOUND is not set # -# SGI devices -# -CONFIG_SGI_SERIAL=y -# CONFIG_SERIAL_CONSOLE is not set -CONFIG_SGI_DS1286=y -# CONFIG_SGI_NEWPORT_GFX is not set - -# # USB support # -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set +# CONFIG_USB_GADGET is not set # -# USB Multimedia devices +# Bluetooth support # +# CONFIG_BT is not set # -# Video4Linux support is needed for USB Multimedia device support -# -# CONFIG_USB_DABUSB is not set - -# -# USB Network adaptors -# -# CONFIG_USB_PLUSB is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support +# Kernel hacking # -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_OMNINET is not set +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set # -# Miscellaneous USB drivers +# Security options # -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_ID75 is not set +# CONFIG_SECURITY is not set # -# Input core support +# Cryptographic options # -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_TEST is not set # -# Kernel hacking +# Library routines # -CONFIG_CROSSCOMPILE=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_MIPS_UNCACHED is not set +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-jmr3927 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,598 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +CONFIG_TOSHIBA_JMR3927=y +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_NONCOHERENT_IO=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_NEW_PCI=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_FB=y +CONFIG_TOSHIBA_BOARDS=y + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +CONFIG_CPU_TX39XX=y +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +CONFIG_RTC_DS1742=y + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_NAMES=y +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_BINFMT_IRIX is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_COMPUTONE is not set +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_DIGIEPCA is not set +# CONFIG_DIGI is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_SYNCLINK is not set +# CONFIG_SYNCLINKMP is not set +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_SX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set +# CONFIG_SERIAL_TX3912 is not set +CONFIG_TXX927_SERIAL=y +CONFIG_TXX927_SERIAL_CONSOLE=y +# CONFIG_SERIAL_TXX9 is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_E1356 is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set + +# +# Logo configuration +# +# CONFIG_LOGO is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-lasat200 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,679 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +CONFIG_LASAT=y +# CONFIG_LASAT_100 is not set +CONFIG_LASAT_200=y +CONFIG_PICVUE=y +CONFIG_PICVUE_PROC=y +CONFIG_DS1603=y +CONFIG_LASAT_SYSCTL=y +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_FB is not set +CONFIG_BOARD_SCACHE=y + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +CONFIG_CPU_R5000=y +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_R5000_CPU_SCACHE=y +# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y +# CONFIG_PCI_NAMES is not set +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_LASAT=y +# CONFIG_MTD_UCLINUX is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +CONFIG_IDEDISK_MULTI_MODE=y +# CONFIG_IDEDISK_STROKE is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_TASKFILE_IO=y + +# +# IDE chipset support/bugfixes +# +CONFIG_BLK_DEV_IDEPCI=y +CONFIG_BLK_DEV_GENERIC=y +# CONFIG_IDEPCI_SHARE_IRQ is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_IDE_TCQ is not set +# CONFIG_BLK_DEV_OFFBOARD is not set +# CONFIG_BLK_DEV_IDEDMA_FORCED is not set +CONFIG_IDEDMA_PCI_AUTO=y +# CONFIG_IDEDMA_ONLYDISK is not set +CONFIG_BLK_DEV_IDEDMA=y +# CONFIG_IDEDMA_PCI_WIP is not set +CONFIG_BLK_DEV_ADMA=y +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +CONFIG_BLK_DEV_CMD64X=y +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_HPT34X is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_OPTI621 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +CONFIG_IDEDMA_AUTO=y +# CONFIG_IDEDMA_IVB is not set +CONFIG_BLK_DEV_IDE_MODES=y + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +# CONFIG_NETLINK_DEV is not set +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +CONFIG_EXT3_FS_SECURITY=y +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_CRC32=y --- linux-2.5.73/arch/mips/defconfig-malta 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/defconfig-malta 2003-06-27 15:56:23.000000000 -0700 @@ -2,7 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -# CONFIG_SMP is not set +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set # # Code maturity level options @@ -10,82 +11,120 @@ CONFIG_MIPS=y CONFIG_EXPERIMENTAL=y # +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# # Machine selection # # CONFIG_ACER_PICA_61 is not set -# CONFIG_ALGOR_P4032 is not set # CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set # CONFIG_DECSTATION is not set -# CONFIG_DDB5074 is not set -# CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set # CONFIG_MIPS_ATLAS is not set -CONFIG_MIPS_MALTA=y -# CONFIG_NINO is not set # CONFIG_MIPS_MAGNUM_4000 is not set +CONFIG_MIPS_MALTA=y +# CONFIG_MIPS_SEAD is not set # CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set # CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set # CONFIG_SNI_RM200_PCI is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_PB1000 is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set +CONFIG_GENERIC_ISA_DMA=y CONFIG_I8259=y -CONFIG_PCI=y -CONFIG_HAVE_STD_PC_SERIAL_PORT=y -CONFIG_NEW_IRQ=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_MIPS_BOARDS_GEN=y CONFIG_SWAP_IO_SPACE=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set +CONFIG_BOOT_ELF32=y +CONFIG_L1_CACHE_SHIFT=5 +# CONFIG_FB is not set +CONFIG_HAVE_STD_PC_SERIAL_PORT=y # # CPU selection # +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set -# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set # CONFIG_CPU_SB1 is not set -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64 is not set +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_VTAG_ICACHE is not set +# CONFIG_64BIT_PHYS_ADDR is not set # CONFIG_CPU_ADVANCED is not set CONFIG_CPU_HAS_LLSC=y -# CONFIG_CPU_HAS_LLDSCD is not set -# CONFIG_CPU_HAS_WB is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set # -# General setup +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_PCI is not set +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats # -CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_KCORE_ELF=y -CONFIG_ELF_KERNEL=y -# CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set -CONFIG_NET=y -# CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set # # Memory Technology Devices (MTD) @@ -98,14 +137,19 @@ CONFIG_SYSVIPC=y # CONFIG_PARPORT is not set # +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# # Block devices # CONFIG_BLK_DEV_FD=y -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y @@ -113,49 +157,98 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_INITRD is not set # +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_REPORT_LUNS is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI low-level drivers +# +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_EATA_PIO is not set +# CONFIG_SCSI_DEBUG is not set + +# # Multi-device support (RAID and LVM) # # CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_BLK_DEV_LVM is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y # # Networking options # # CONFIG_PACKET is not set -# CONFIG_NETLINK is not set +CONFIG_NETLINK_DEV=y # CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set CONFIG_UNIX=y +CONFIG_NET_KEY=y CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -# CONFIG_IP_PNP_BOOTP is not set +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set # CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set +# CONFIG_XFRM_USER is not set # -# +# SCTP Configuration (EXPERIMENTAL) # -# CONFIG_IPX is not set -# CONFIG_ATALK is not set +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set # CONFIG_DECNET is not set # CONFIG_BRIDGE is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_LLC is not set # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set @@ -168,162 +261,29 @@ CONFIG_IP_PNP=y # CONFIG_NET_SCHED is not set # -# Telephony Support -# -# CONFIG_PHONE is not set -# CONFIG_PHONE_IXJ is not set -# CONFIG_PHONE_IXJ_PCMCIA is not set - -# -# ATA/IDE/MFM/RLL support -# -# CONFIG_IDE is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI support -# -CONFIG_SCSI=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -CONFIG_SD_EXTRA_DEVS=40 -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_DEBUG_QUEUES is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set - -# -# SCSI low-level drivers -# -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AHA1740 is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC7XXX_OLD is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_MEGARAID is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CPQFCTS is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_DMA is not set -# CONFIG_SCSI_EATA_PIO is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NCR_D700 is not set -# CONFIG_SCSI_NCR53C7xx is not set -# CONFIG_SCSI_NCR53C8XX is not set -# CONFIG_SCSI_SYM53C8XX is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PCI2000 is not set -# CONFIG_SCSI_PCI2220I is not set -# CONFIG_SCSI_PSI240I is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_QLOGIC_ISP is not set -# CONFIG_SCSI_QLOGIC_FC is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_SIM710 is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_DC390T is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_DEBUG is not set - -# -# Network device support +# Network testing # +# CONFIG_NET_PKTGEN is not set CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -# CONFIG_SUNLANCE is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -CONFIG_NET_PCI=y -CONFIG_PCNET32=y -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_APRICOT is not set -# CONFIG_CS89x0 is not set -# CONFIG_TULIP is not set -# CONFIG_DE4X5 is not set -# CONFIG_DGRS is not set -# CONFIG_DM9102 is not set -# CONFIG_EEPRO100 is not set -# CONFIG_LNE390 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_NE3210 is not set -# CONFIG_ES3210 is not set -# CONFIG_8139TOO is not set -# CONFIG_8139TOO_PIO is not set -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139TOO_8129 is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_LAN_SAA9730 is not set -# CONFIG_NET_POCKET is not set +# CONFIG_MII is not set # # Ethernet (1000 Mbit) # -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set + +# +# Ethernet (10000 Mbit) +# # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -333,11 +293,8 @@ CONFIG_PCNET32=y # CONFIG_NET_RADIO is not set # -# Token Ring devices +# Token Ring devices (depends on LLC=y) # -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set # CONFIG_SHAPER is not set # @@ -358,21 +315,64 @@ CONFIG_PCNET32=y # # ISDN subsystem # -# CONFIG_ISDN is not set +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set # -# Old CD-ROM drivers (not SCSI, not IDE) +# Input Device Drivers # -# CONFIG_CD_NO_IDESCSI is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Character devices # # CONFIG_VT is not set -CONFIG_SERIAL=y -CONFIG_SERIAL_CONSOLE=y -# CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 @@ -382,36 +382,34 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_I2C is not set # -# Mice +# I2C Hardware Sensors Mainboard support # -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set # -# Joysticks +# I2C Hardware Sensors Chip support # -# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_I2C_SENSOR is not set # -# Input core support is needed for gameports +# Mice # +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set # -# Input core support is needed for joysticks +# IPMI # -# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set CONFIG_RTC=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_SONYPI is not set # # Ftape, the floppy tape device driver @@ -419,6 +417,8 @@ CONFIG_RTC=y # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set # # Multimedia devices @@ -426,206 +426,130 @@ CONFIG_RTC=y # CONFIG_VIDEO_DEV is not set # +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# # File systems # +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set CONFIG_AUTOFS_FS=y # CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set -# CONFIG_CMS_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_JBD_DEBUG is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set CONFIG_EFS_FS=y -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_TMPFS is not set -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_FREEVXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set +# CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set # # Network File Systems # -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V4 is not set +# CONFIG_NFSD_TCP is not set CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -# CONFIG_NFSD_V3 is not set -CONFIG_SUNRPC=y CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set # CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set # CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set # -# Sound +# Graphics support # -# CONFIG_SOUND is not set # -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support +# Sound # -# CONFIG_USB_DABUSB is not set +# CONFIG_SOUND is not set # -# USB Network adaptors +# USB support # -# CONFIG_USB_PLUSB is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set +# CONFIG_USB_GADGET is not set # -# USB port drivers +# Bluetooth support # -# CONFIG_USB_USS720 is not set +# CONFIG_BT is not set # -# USB Serial Converter support +# Kernel hacking # -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_OMNINET is not set +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set # -# Miscellaneous USB drivers +# Security options # -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_ID75 is not set +# CONFIG_SECURITY is not set # -# Input core support +# Cryptographic options # -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set +# CONFIG_CRYPTO is not set # -# Kernel hacking +# Library routines # -CONFIG_CROSSCOMPILE=y -# CONFIG_REMOTE_DEBUG is not set -# CONFIG_GDB_CONSOLE is not set -# CONFIG_LL_DEBUG is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_MIPS_UNCACHED is not set +# CONFIG_CRC32 is not set --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-mpc30x 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,543 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +CONFIG_VICTOR_MPC30X=y +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_VR41XX_TIME_C=y +CONFIG_DUMMY_KEYB=y +CONFIG_VR41XX_COMMON=y +CONFIG_VRC4173=y +CONFIG_NEW_PCI=y +# CONFIG_FB is not set + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +CONFIG_CPU_VR41XX=y +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_PCI is not set +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_BLOWFISH is not set +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_TEST is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y --- linux-2.5.73/arch/mips/defconfig-nino 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,416 +0,0 @@ -# -# Automatically generated make config: don't edit -# -CONFIG_MIPS=y -# CONFIG_SMP is not set - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y - -# -# Machine selection -# -# CONFIG_ACER_PICA_61 is not set -# CONFIG_ALGOR_P4032 is not set -# CONFIG_BAGET_MIPS is not set -# CONFIG_DECSTATION is not set -# CONFIG_DDB5074 is not set -# CONFIG_MIPS_EV96100 is not set -# CONFIG_MIPS_EV64120 is not set -# CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -CONFIG_NINO=y -# CONFIG_NINO_4MB is not set -CONFIG_NINO_8MB=y -# CONFIG_NINO_16MB is not set -# CONFIG_MIPS_MAGNUM_4000 is not set -# CONFIG_MOMENCO_OCELOT is not set -# CONFIG_DDB5476 is not set -# CONFIG_DDB5477 is not set -# CONFIG_OLIVETTI_M700 is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SNI_RM200_PCI is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MIPS_IVR is not set -# CONFIG_MIPS_PB1000 is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_PC_KEYB=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_PCI is not set -# CONFIG_I8259 is not set - -# -# Loadable module support -# -CONFIG_MODULES=y -# CONFIG_MODVERSIONS is not set -CONFIG_KMOD=y - -# -# CPU selection -# -CONFIG_CPU_R3000=y -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_SB1 is not set -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS64 is not set -# CONFIG_CPU_ADVANCED is not set -# CONFIG_CPU_HAS_LLSC is not set -# CONFIG_CPU_HAS_LLDSCD is not set -# CONFIG_CPU_HAS_WB is not set - -# -# General setup -# -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_KCORE_ELF=y -CONFIG_ELF_KERNEL=y -# CONFIG_BINFMT_AOUT is not set -CONFIG_BINFMT_ELF=y -CONFIG_BINFMT_MISC=y -# CONFIG_NET is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=2048 -CONFIG_BLK_DEV_INITRD=y - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_BLK_DEV_LVM is not set - -# -# Telephony Support -# -# CONFIG_PHONE is not set -# CONFIG_PHONE_IXJ is not set -# CONFIG_PHONE_IXJ_PCMCIA is not set - -# -# ATA/IDE/MFM/RLL support -# -# CONFIG_IDE is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI support -# -# CONFIG_SCSI is not set - -# -# Amateur Radio support -# -# CONFIG_HAMRADIO is not set - -# -# ISDN subsystem -# - -# -# Old CD-ROM drivers (not SCSI, not IDE) -# -# CONFIG_CD_NO_IDESCSI is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL is not set -# CONFIG_SERIAL_EXTENDED is not set -CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_COMPUTONE is not set -# CONFIG_ROCKETPORT is not set -# CONFIG_CYCLADES is not set -# CONFIG_DIGIEPCA is not set -# CONFIG_DIGI is not set -# CONFIG_ESPSERIAL is not set -# CONFIG_MOXA_INTELLIO is not set -# CONFIG_MOXA_SMARTIO is not set -# CONFIG_ISI is not set -# CONFIG_SYNCLINK is not set -# CONFIG_N_HDLC is not set -# CONFIG_RISCOM8 is not set -# CONFIG_SPECIALIX is not set -# CONFIG_SX is not set -# CONFIG_RIO is not set -# CONFIG_STALDRV is not set -CONFIG_SERIAL_TX3912=y -CONFIG_SERIAL_TX3912_CONSOLE=y -# CONFIG_AU1000_UART is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Mice -# -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set - -# -# Joysticks -# -# CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# - -# -# Input core support is needed for joysticks -# -# CONFIG_QIC02_TAPE is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set -# CONFIG_SONYPI is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_FTAPE is not set -# CONFIG_AGP is not set -# CONFIG_DRM is not set - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# File systems -# -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_CMS_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_JBD_DEBUG is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_TMPFS is not set -# CONFIG_RAMFS is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_FREEVXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set -# CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y -# CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set -# CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_SMB_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -# CONFIG_USB is not set - -# -# USB Controllers -# -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set - -# -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices -# -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set - -# -# USB Multimedia devices -# - -# -# Video4Linux support is needed for USB Multimedia device support -# -# CONFIG_USB_DABUSB is not set - -# -# USB Network adaptors -# - -# -# Networking support is needed for USB Networking device support -# - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set - -# -# USB Serial Converter support -# -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_OMNINET is not set - -# -# Miscellaneous USB drivers -# -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_ID75 is not set - -# -# Input core support -# -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set - -# -# Kernel hacking -# -CONFIG_CROSSCOMPILE=y -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_MIPS_UNCACHED is not set --- linux-2.5.73/arch/mips/defconfig-pb1000 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/defconfig-pb1000 2003-06-27 15:56:23.000000000 -0700 @@ -2,7 +2,8 @@ # Automatically generated make config: don't edit # CONFIG_MIPS=y -# CONFIG_SMP is not set +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set # # Code maturity level options @@ -10,85 +11,183 @@ CONFIG_MIPS=y CONFIG_EXPERIMENTAL=y # +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# # Machine selection # # CONFIG_ACER_PICA_61 is not set -# CONFIG_ALGOR_P4032 is not set # CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set # CONFIG_DECSTATION is not set -# CONFIG_DDB5074 is not set -# CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set # CONFIG_MIPS_ATLAS is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_NINO is not set # CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set # CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set # CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set # CONFIG_SNI_RM200_PCI is not set -# CONFIG_MIPS_ITE8172 is not set -# CONFIG_MIPS_IVR is not set -CONFIG_MIPS_PB1000=y +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -# CONFIG_MCA is not set -# CONFIG_SBUS is not set -CONFIG_MIPS_AU1000=y -CONFIG_NEW_IRQ=y -# CONFIG_ISA is not set -# CONFIG_EISA is not set -# CONFIG_PCI is not set -# CONFIG_I8259 is not set - -# -# Loadable module support -# -# CONFIG_MODULES is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_FB=y # # CPU selection # +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set -# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set # CONFIG_CPU_SB1 is not set -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64 is not set +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_VTAG_ICACHE is not set +CONFIG_64BIT_PHYS_ADDR=y CONFIG_CPU_ADVANCED=y CONFIG_CPU_HAS_LLSC=y # CONFIG_CPU_HAS_LLDSCD is not set CONFIG_CPU_HAS_WB=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set # -# General setup +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_MMU=y +CONFIG_HOTPLUG=y + +# +# PCMCIA/CardBus support +# +CONFIG_PCMCIA=m +# CONFIG_TCIC is not set + +# +# PCI Hotplug Support +# + +# +# Executable file formats # -CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_KCORE_ELF=y -CONFIG_ELF_KERNEL=y -# CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set -CONFIG_NET=y -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set -CONFIG_SYSVIPC=y -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y # # Memory Technology Devices (MTD) # -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_UCLINUX is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set # # Parallel port support @@ -96,39 +195,83 @@ CONFIG_SYSCTL=y # CONFIG_PARPORT is not set # +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# # Block devices # # CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_PARIDE is not set -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_IDEDISK_STROKE is not set +CONFIG_BLK_DEV_IDECS=m +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_TASKFILE_IO=y + +# +# IDE chipset support/bugfixes +# + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# # Multi-device support (RAID and LVM) # # CONFIG_MD is not set -# CONFIG_BLK_DEV_MD is not set -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID5 is not set -# CONFIG_BLK_DEV_LVM is not set + +# +# Fusion MPT device support +# + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y # # Networking options # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK is not set +# CONFIG_NETLINK_DEV is not set # CONFIG_NETFILTER is not set -# CONFIG_FILTER is not set CONFIG_UNIX=y +CONFIG_NET_KEY=y CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set @@ -138,22 +281,27 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set # CONFIG_IPV6 is not set -# CONFIG_KHTTPD is not set -# CONFIG_ATM is not set +# CONFIG_XFRM_USER is not set # -# +# SCTP Configuration (EXPERIMENTAL) # -# CONFIG_IPX is not set -# CONFIG_ATALK is not set +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set # CONFIG_DECNET is not set # CONFIG_BRIDGE is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_LLC is not set # CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set @@ -166,69 +314,29 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_NET_SCHED is not set # -# Telephony Support -# -# CONFIG_PHONE is not set -# CONFIG_PHONE_IXJ is not set -# CONFIG_PHONE_IXJ_PCMCIA is not set - -# -# ATA/IDE/MFM/RLL support -# -# CONFIG_IDE is not set -# CONFIG_BLK_DEV_IDE_MODES is not set -# CONFIG_BLK_DEV_HD is not set - -# -# SCSI support -# -# CONFIG_SCSI is not set - -# -# Network device support +# Network testing # +# CONFIG_NET_PKTGEN is not set CONFIG_NETDEVICES=y - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y -CONFIG_MIPS_AU1000_ENET=y -# CONFIG_SUNLANCE is not set -# CONFIG_SUNBMAC is not set -# CONFIG_SUNQE is not set -# CONFIG_SUNLANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set +# CONFIG_MII is not set # # Ethernet (1000 Mbit) # -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_MYRI_SBUS is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_SK98LIN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PLIP is not set + +# +# Ethernet (10000 Mbit) +# # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -238,11 +346,8 @@ CONFIG_MIPS_AU1000_ENET=y # CONFIG_NET_RADIO is not set # -# Token Ring devices +# Token Ring devices (depends on LLC=y) # -# CONFIG_TR is not set -# CONFIG_NET_FC is not set -# CONFIG_RCPCI is not set # CONFIG_SHAPER is not set # @@ -251,6 +356,19 @@ CONFIG_MIPS_AU1000_ENET=y # CONFIG_WAN is not set # +# PCMCIA network device support +# +CONFIG_NET_PCMCIA=y +CONFIG_PCMCIA_3C589=m +# CONFIG_PCMCIA_3C574 is not set +# CONFIG_PCMCIA_FMVJ18X is not set +# CONFIG_PCMCIA_PCNET is not set +# CONFIG_PCMCIA_NMCLAN is not set +# CONFIG_PCMCIA_SMC91C92 is not set +# CONFIG_PCMCIA_XIRC2PS is not set +# CONFIG_PCMCIA_AXNET is not set + +# # Amateur Radio support # # CONFIG_HAMRADIO is not set @@ -258,44 +376,131 @@ CONFIG_MIPS_AU1000_ENET=y # # IrDA (infrared) support # -# CONFIG_IRDA is not set +CONFIG_IRDA=y + +# +# IrDA protocols +# +CONFIG_IRLAN=m +CONFIG_IRCOMM=m +# CONFIG_IRDA_ULTRA is not set + +# +# IrDA options +# +CONFIG_IRDA_CACHE_LAST_LSAP=y +CONFIG_IRDA_FAST_RR=y +# CONFIG_IRDA_DEBUG is not set + +# +# Infrared-port device drivers +# + +# +# SIR device drivers +# +# CONFIG_IRTTY_SIR is not set + +# +# Dongle support +# +# CONFIG_DONGLE is not set + +# +# Old SIR device drivers +# +# CONFIG_IRTTY_OLD is not set +# CONFIG_IRPORT_SIR is not set + +# +# Old Serial dongle support +# +# CONFIG_DONGLE_OLD is not set + +# +# FIR device drivers +# +# CONFIG_NSC_FIR is not set +# CONFIG_WINBOND_FIR is not set +# CONFIG_TOSHIBA_OLD is not set +# CONFIG_TOSHIBA_FIR is not set +# CONFIG_SMC_IRCC_OLD is not set +# CONFIG_SMC_IRCC_FIR is not set +# CONFIG_ALI_FIR is not set +# CONFIG_VLSI_FIR is not set # # ISDN subsystem # -# CONFIG_ISDN is not set +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set # -# Old CD-ROM drivers (not SCSI, not IDE) +# Input Device Drivers # -# CONFIG_CD_NO_IDESCSI is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set # # Character devices # -# CONFIG_VT is not set -# CONFIG_SERIAL is not set -# CONFIG_SERIAL_EXTENDED is not set +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y CONFIG_SERIAL_NONSTANDARD=y # CONFIG_COMPUTONE is not set # CONFIG_ROCKETPORT is not set # CONFIG_CYCLADES is not set # CONFIG_DIGIEPCA is not set # CONFIG_DIGI is not set -# CONFIG_ESPSERIAL is not set # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set +# CONFIG_ISI is not set # CONFIG_SYNCLINK is not set +# CONFIG_SYNCLINKMP is not set # CONFIG_N_HDLC is not set # CONFIG_RISCOM8 is not set # CONFIG_SPECIALIX is not set # CONFIG_SX is not set # CONFIG_RIO is not set # CONFIG_STALDRV is not set -# CONFIG_SERIAL_TX3912 is not set -# CONFIG_SERIAL_TX3912_CONSOLE is not set -CONFIG_AU1000_UART=y -CONFIG_AU1000_SERIAL_CONSOLE=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 @@ -305,36 +510,35 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_I2C is not set # -# Mice +# I2C Hardware Sensors Mainboard support # -# CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set # -# Joysticks +# I2C Hardware Sensors Chip support # -# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_I2C_SENSOR is not set # -# Input core support is needed for gameports +# Mice # +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set # -# Input core support is needed for joysticks +# IPMI # -# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set -# CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_SONYPI is not set # # Ftape, the floppy tape device driver @@ -344,223 +548,168 @@ CONFIG_UNIX98_PTY_COUNT=256 # CONFIG_DRM is not set # +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set # +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# # File systems # +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_QUOTA is not set CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set -# CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set -# CONFIG_CMS_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_JBD_DEBUG is not set -# CONFIG_FAT_FS is not set -# CONFIG_MSDOS_FS is not set -# CONFIG_UMSDOS_FS is not set -# CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set -# CONFIG_JFFS2_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_NAND is not set # CONFIG_CRAMFS is not set -# CONFIG_TMPFS is not set -# CONFIG_RAMFS is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_MINIX_FS is not set -# CONFIG_FREEVXFS_FS is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set +# CONFIG_VXFS_FS is not set # CONFIG_HPFS_FS is not set -CONFIG_PROC_FS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVFS_MOUNT is not set -# CONFIG_DEVFS_DEBUG is not set -# CONFIG_DEVPTS_FS is not set # CONFIG_QNX4FS_FS is not set -# CONFIG_QNX4FS_RW is not set -# CONFIG_ROMFS_FS is not set -CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set -# CONFIG_UFS_FS_WRITE is not set # # Network File Systems # -# CONFIG_CODA_FS is not set -# CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set -CONFIG_ROOT_NFS=y +# CONFIG_NFS_V4 is not set # CONFIG_NFSD is not set -# CONFIG_NFSD_V3 is not set -CONFIG_SUNRPC=y +CONFIG_ROOT_NFS=y CONFIG_LOCKD=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set # CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set # CONFIG_NCP_FS is not set -# CONFIG_NCPFS_PACKET_SIGNING is not set -# CONFIG_NCPFS_IOCTL_LOCKING is not set -# CONFIG_NCPFS_STRONG is not set -# CONFIG_NCPFS_NFS_NS is not set -# CONFIG_NCPFS_OS2_NS is not set -# CONFIG_NCPFS_SMALLDOS is not set -# CONFIG_NCPFS_NLS is not set -# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set # # Partition Types # -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set +# CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -CONFIG_SGI_PARTITION=y -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_SMB_NLS is not set -# CONFIG_NLS is not set - -# -# Sound -# -# CONFIG_SOUND is not set # -# USB support +# Graphics support # -# CONFIG_USB is not set +# CONFIG_FB_VIRTUAL is not set # -# USB Controllers +# Console display driver support # -# CONFIG_USB_UHCI is not set -# CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set # -# USB Device Class drivers +# Logo configuration # -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_BLUETOOTH is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set +# CONFIG_LOGO is not set # -# USB Human Interface Devices (HID) -# - -# -# Input core support is needed for USB HID -# - -# -# USB Imaging devices +# Sound # -# CONFIG_USB_DC2XX is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_SCANNER is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_HPUSBSCSI is not set +CONFIG_SOUND=y # -# USB Multimedia devices +# Advanced Linux Sound Architecture # +# CONFIG_SND is not set # -# Video4Linux support is needed for USB Multimedia device support +# Open Sound System # -# CONFIG_USB_DABUSB is not set +# CONFIG_SOUND_PRIME is not set # -# USB Network adaptors +# USB support # -# CONFIG_USB_PLUSB is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDCETHER is not set -# CONFIG_USB_USBNET is not set +# CONFIG_USB_GADGET is not set # -# USB port drivers +# Bluetooth support # -# CONFIG_USB_USS720 is not set +# CONFIG_BT is not set # -# USB Serial Converter support +# Kernel hacking # -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_OMNINET is not set +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set # -# Miscellaneous USB drivers +# Security options # -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_ID75 is not set +# CONFIG_SECURITY is not set # -# Input core support +# Cryptographic options # -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set +# CONFIG_CRYPTO is not set # -# Kernel hacking +# Library routines # -CONFIG_CROSSCOMPILE=y -# CONFIG_REMOTE_DEBUG is not set -# CONFIG_GDB_CONSOLE is not set -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_MIPS_UNCACHED is not set +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-pb1100 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,789 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_FB=y + +# +# CPU selection +# +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_VTAG_ICACHE is not set +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_CPU_ADVANCED=y +CONFIG_CPU_HAS_LLSC=y +# CONFIG_CPU_HAS_LLDSCD is not set +CONFIG_CPU_HAS_WB=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_MMU=y +CONFIG_HOTPLUG=y + +# +# PCMCIA/CardBus support +# +CONFIG_PCMCIA=m +# CONFIG_TCIC is not set + +# +# PCI Hotplug Support +# + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_UCLINUX is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_IDEDISK_STROKE is not set +CONFIG_BLK_DEV_IDECS=m +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_TASKFILE_IO=y + +# +# IDE chipset support/bugfixes +# + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +# CONFIG_NETLINK_DEV is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_COMPAT_IPCHAINS is not set +# CONFIG_IP_NF_COMPAT_IPFWADM is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +# CONFIG_PPP_SYNC_TTY is not set +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_BSDCOMP is not set +CONFIG_PPPOE=m +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# PCMCIA network device support +# +CONFIG_NET_PCMCIA=y +CONFIG_PCMCIA_3C589=m +# CONFIG_PCMCIA_3C574 is not set +# CONFIG_PCMCIA_FMVJ18X is not set +# CONFIG_PCMCIA_PCNET is not set +# CONFIG_PCMCIA_NMCLAN is not set +# CONFIG_PCMCIA_SMC91C92 is not set +# CONFIG_PCMCIA_XIRC2PS is not set +# CONFIG_PCMCIA_AXNET is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +CONFIG_IRDA=y + +# +# IrDA protocols +# +CONFIG_IRLAN=m +# CONFIG_IRNET is not set +CONFIG_IRCOMM=m +# CONFIG_IRDA_ULTRA is not set + +# +# IrDA options +# +CONFIG_IRDA_CACHE_LAST_LSAP=y +CONFIG_IRDA_FAST_RR=y +# CONFIG_IRDA_DEBUG is not set + +# +# Infrared-port device drivers +# + +# +# SIR device drivers +# +# CONFIG_IRTTY_SIR is not set + +# +# Dongle support +# +# CONFIG_DONGLE is not set + +# +# Old SIR device drivers +# +# CONFIG_IRTTY_OLD is not set +# CONFIG_IRPORT_SIR is not set + +# +# Old Serial dongle support +# +# CONFIG_DONGLE_OLD is not set + +# +# FIR device drivers +# +# CONFIG_NSC_FIR is not set +# CONFIG_WINBOND_FIR is not set +# CONFIG_TOSHIBA_OLD is not set +# CONFIG_TOSHIBA_FIR is not set +# CONFIG_SMC_IRCC_OLD is not set +# CONFIG_SMC_IRCC_FIR is not set +# CONFIG_ALI_FIR is not set +# CONFIG_VLSI_FIR is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_COMPUTONE is not set +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_DIGIEPCA is not set +# CONFIG_DIGI is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_ISI is not set +# CONFIG_SYNCLINK is not set +# CONFIG_SYNCLINKMP is not set +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_SX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +CONFIG_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +CONFIG_EXT3_FS_SECURITY=y +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=m +CONFIG_AUTOFS4_FS=m + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +CONFIG_TMPFS=y +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS_FS=m +CONFIG_JFFS_FS_VERBOSE=0 +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_NAND is not set +CONFIG_CRAMFS=m +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_NFSD=m +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_EXPORTFS=m +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_SMB_NLS=y +CONFIG_NLS=y + +# +# Native Language Support +# +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Graphics support +# +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set + +# +# Logo configuration +# +# CONFIG_LOGO is not set + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +# CONFIG_SND is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# USB support +# +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-pb1500 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,664 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +CONFIG_SOC_AU1X00=y +# CONFIG_SOC_AU1000 is not set +# CONFIG_SOC_AU1100 is not set +CONFIG_SOC_AU1500=y +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +CONFIG_MIPS_PB1500=y +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_NEW_PCI=y +# CONFIG_AU1000_USB_DEVICE is not set +# CONFIG_FB is not set + +# +# CPU selection +# +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_VTAG_ICACHE is not set +# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_PCI is not set +CONFIG_MMU=y +CONFIG_HOTPLUG=y + +# +# PCMCIA/CardBus support +# +CONFIG_PCMCIA=m +# CONFIG_TCIC is not set + +# +# PCI Hotplug Support +# + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_PM is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_NETLINK_DEV=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_IP_NF_CONNTRACK is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_COMPAT_IPCHAINS is not set +# CONFIG_IP_NF_COMPAT_IPFWADM is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +CONFIG_MIPS_AU1X00_ENET=y + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +# CONFIG_PPP_SYNC_TTY is not set +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_BSDCOMP is not set +CONFIG_PPPOE=m +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# PCMCIA network device support +# +CONFIG_NET_PCMCIA=y +CONFIG_PCMCIA_3C589=m +# CONFIG_PCMCIA_3C574 is not set +# CONFIG_PCMCIA_FMVJ18X is not set +# CONFIG_PCMCIA_PCNET is not set +# CONFIG_PCMCIA_NMCLAN is not set +# CONFIG_PCMCIA_SMC91C92 is not set +# CONFIG_PCMCIA_XIRC2PS is not set +# CONFIG_PCMCIA_AXNET is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_AU1X00_GPIO is not set +# CONFIG_TS_AU1X00_ADS7846 is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_AU1X00=y +CONFIG_SERIAL_AU1X00_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +CONFIG_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +# CONFIG_EXT2_FS_SECURITY is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=m +CONFIG_AUTOFS4_FS=m + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +CONFIG_TMPFS=y +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=m +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_NFSD=m +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_EXPORTFS=m +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_SMB_NLS=y +CONFIG_NLS=y + +# +# Native Language Support +# +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Graphics support +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_BLOWFISH is not set +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_TEST is not set + +# +# Library routines +# +CONFIG_CRC32=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-sb1250-swarm 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,613 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=15 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +CONFIG_SIBYTE_SB1xxx_SOC=y +CONFIG_SIBYTE_SB1250=y +# CONFIG_SIMULATION is not set +CONFIG_SIBYTE_CFE=y +# CONFIG_SIBYTE_CFE_CONSOLE is not set +# CONFIG_SIBYTE_BUS_WATCHER is not set +# CONFIG_SIBYTE_SB1250_PROF is not set +# CONFIG_SIBYTE_TBPROF is not set +CONFIG_SIBYTE_SWARM=y +CONFIG_SIBYTE_BOARD=y +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_DUMMY_KEYB=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +# CONFIG_FB is not set + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +CONFIG_CPU_SB1=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_VTAG_ICACHE=y +CONFIG_CPU_SB1_PASS_1=y +# CONFIG_CPU_SB1_PASS_2 is not set +# CONFIG_CPU_SB1_PASS_2_2 is not set +CONFIG_SB1_PASS_1_WORKAROUNDS=y +CONFIG_SB1_CACHE_ERROR=y +CONFIG_SB1_CERR_IGNORE_RECOVERABLE=y +# CONFIG_SB1_CERR_SPIN is not set +# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_LLDSCD=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_HIGHMEM is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_NAMES=y +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_BINFMT_IRIX is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=9220 +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +CONFIG_NET_SB1250_MAC=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PCIPS2 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_COMPUTONE is not set +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_DIGIEPCA is not set +# CONFIG_DIGI is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_ISI is not set +# CONFIG_SYNCLINK is not set +# CONFIG_SYNCLINKMP is not set +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_SX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set +CONFIG_SIBYTE_SB1250_DUART=y +CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y +CONFIG_SERIAL_CONSOLE=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_TEST is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-sead 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,393 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +CONFIG_MIPS_SEAD=y +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_MIPS_BOARDS_GEN=y +CONFIG_L1_CACHE_SHIFT=5 +# CONFIG_FB is not set + +# +# CPU selection +# +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_VTAG_ICACHE is not set +# CONFIG_64BIT_PHYS_ADDR is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=18432 +CONFIG_BLK_DEV_INITRD=y + +# +# MIPS initrd options +# +CONFIG_EMBEDDED_RAMDISK=y +CONFIG_EMBEDDED_RAMDISK_IMAGE="ramdisk.gz" + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# I2O device support +# + +# +# Networking support +# +# CONFIG_NET is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# ISDN subsystem +# + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB_GADGET is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-tb0226 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,667 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +CONFIG_TANBAC_TB0226=y +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_VR41XX_TIME_C=y +CONFIG_DUMMY_KEYB=y +CONFIG_VR41XX_COMMON=y +CONFIG_NEW_PCI=y +CONFIG_FB=y + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +CONFIG_CPU_VR41XX=y +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_PCI is not set +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +CONFIG_BLK_DEV_FD=y +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +CONFIG_IDEDISK_MULTI_MODE=y +# CONFIG_IDEDISK_STROKE is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +CONFIG_BLK_DEV_IDESCSI=y +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_TASKFILE_IO=y + +# +# IDE chipset support/bugfixes +# + +# +# SCSI device support +# +CONFIG_SCSI=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_REPORT_LUNS is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI low-level drivers +# +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_EATA_PIO is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_NETLINK_DEV=m +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_NAT=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_TOS=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPPOE=m +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=m +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1280 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=1024 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +CONFIG_ROMFS_FS=m +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=y + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_ZISOFS_FS=y +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +CONFIG_TMPFS=y +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=m +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V4 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +CONFIG_SMB_FS=m +CONFIG_SMB_NLS_DEFAULT=y +CONFIG_SMB_NLS_REMOTE="cp932" +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_SMB_NLS=y +CONFIG_NLS=y + +# +# Native Language Support +# +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +CONFIG_NLS_CODEPAGE_932=m +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Graphics support +# +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set + +# +# Logo configuration +# +# CONFIG_LOGO is not set + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +# CONFIG_SND is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set + +# +# USB support +# +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-tb0229 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,657 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +# CONFIG_IBM_WORKPAD is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +CONFIG_TANBAC_TB0229=y +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_VR41XX_TIME_C=y +CONFIG_DUMMY_KEYB=y +CONFIG_VR41XX_COMMON=y +CONFIG_NEW_PCI=y +# CONFIG_FB is not set +CONFIG_TANBAC_TB0219=y + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +CONFIG_CPU_VR41XX=y +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_PCI=y +CONFIG_PCI_LEGACY_PROC=y +CONFIG_PCI_NAMES=y +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support (EXPERIMENTAL) +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_NETLINK_DEV=m +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_NAT=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_TOS=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +# CONFIG_NET_IPGRE_BROADCAST is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +CONFIG_DUMMY=m +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_NET_PCI is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_IXGB is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPPOE=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=m +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1280 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=1024 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT3_FS=m +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +CONFIG_EXT3_FS_SECURITY=y +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +CONFIG_JFS_FS=m +# CONFIG_JFS_POSIX_ACL is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_RT is not set +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_MINIX_FS is not set +CONFIG_ROMFS_FS=m +# CONFIG_QUOTA is not set +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=y + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_ZISOFS_FS=y +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +CONFIG_TMPFS=y +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=m +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V4 is not set +CONFIG_NFSD_TCP=y +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +CONFIG_SMB_FS=m +CONFIG_SMB_NLS_DEFAULT=y +CONFIG_SMB_NLS_REMOTE="cp932" +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_SMB_NLS=y +CONFIG_NLS=y + +# +# Native Language Support +# +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +CONFIG_NLS_CODEPAGE_932=m +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Graphics support +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/defconfig-workpad 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,568 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_MIPS=y +CONFIG_MIPS32=y +# CONFIG_MIPS64 is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# General setup +# +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_EMBEDDED is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_OBSOLETE_MODPARM=y +CONFIG_MODVERSIONS=y +CONFIG_KMOD=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_CASIO_E55 is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_LASAT is not set +# CONFIG_HP_LASERJET is not set +CONFIG_IBM_WORKPAD=y +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SOC_AU1X00 is not set +# CONFIG_SIBYTE_SB1xxx_SOC is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TANBAC_TB0226 is not set +# CONFIG_TANBAC_TB0229 is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_VICTOR_MPC30X is not set +# CONFIG_ZAO_CAPCELLA is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_NONCOHERENT_IO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_VR41XX_TIME_C=y +CONFIG_DUMMY_KEYB=y +CONFIG_VR41XX_COMMON=y +# CONFIG_FB is not set + +# +# CPU selection +# +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_MIPS64 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +CONFIG_CPU_VR41XX=y +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_PREEMPT is not set +CONFIG_KALLSYMS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_MMU=y +# CONFIG_HOTPLUG is not set + +# +# Executable file formats +# +CONFIG_KCORE_ELF=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNP is not set + +# +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_IDEDISK_STROKE is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_TASKFILE_IO=y + +# +# IDE chipset support/bugfixes +# + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# + +# +# I2O device support +# + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_NETLINK_DEV=y +# CONFIG_NETFILTER is not set +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_XFRM_USER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices (depends on LLC=y) +# +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN_BOOL is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX98_PTY_COUNT=256 + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# I2C Hardware Sensors Mainboard support +# + +# +# I2C Hardware Sensors Chip support +# +# CONFIG_I2C_SENSOR is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_WDT is not set +# CONFIG_WDTPCI is not set +# CONFIG_PCWATCHDOG is not set +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_ADVANTECH_WDT is not set +# CONFIG_EUROTECH_WDT is not set +# CONFIG_IB700_WDT is not set +# CONFIG_I810_TCO is not set +# CONFIG_MIXCOMWD is not set +# CONFIG_SCx200_WDT is not set +# CONFIG_60XX_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_MACHZ_WDT is not set +# CONFIG_SC520_WDT is not set +# CONFIG_AMD7XX_TCO is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_SC1200_WDT is not set +# CONFIG_WAFER_WDT is not set +# CONFIG_CPU5_WDT is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HANGCHECK_TIMER is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_FAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +CONFIG_DEVPTS_FS=y +CONFIG_DEVPTS_FS_XATTR=y +CONFIG_DEVPTS_FS_SECURITY=y +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_NFSD=y +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_LOCKD=y +CONFIG_EXPORTFS=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Graphics support +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB_GADGET is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_KERNEL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +# CONFIG_CRC32 is not set --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev64120/dma.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,168 @@ +/* DMA.C - DMA functions and definitions */ + +/* Copyright Galileo Technology. */ + +/* +DESCRIPTION +This file gives the user a complete interface to the powerful DMA engines, +including functions for controling the priority mechanism. +To fully understand the capabilities of the DMA engines please spare some +time to go trough the spec. +*/ + +/* includes */ + +#ifdef __linux__ +#include +#include +#else +#include "Core.h" +#include "DMA.h" +#endif +/******************************************************************** +* dmaCommand - Write a command to a DMA channel +* +* Inputs: DMA_ENGINE channel - choosing one of the four engine. +* unsigned int command - The command to be written to the control register. +* Returns: false if one of the parameters is erroneous else returns true. +*********************************************************************/ + +bool dmaCommand(DMA_ENGINE channel, unsigned int command) +{ + if (channel > LAST_DMA_ENGINE) + return false; + GT_REG_WRITE(CHANNEL0CONTROL + channel * 4, command); + return true; +} + +/******************************************************************** +* dmaTransfer - transfer data from sourceAddr to destAddr on DMA channel +* Inputs: +* DMA_RECORED *nextRecoredPointer: If we are using chain mode DMA transfer, +* then this pointer should point to the next recored,otherwise it should be +* NULL. +* VERY IMPORTANT !!! When using chain mode, the records must be 16 Bytes +* aligned, the function will take care of that for you, but you need to +* allocate one more record for that, meaning: if you are having 3 records , +* declare 4 (see the example bellow) and start using the second one. +* Example: +* Performing a chain mode DMA transfer(Copy a 1/4 mega of data using +* chain mode DMA): +* DMA_RECORED dmaRecoredArray[4]; +* dmaRecoredArray[1].ByteCnt = _64KB; +* dmaRecoredArray[1].DestAdd = destAddress + _64KB; +* dmaRecoredArray[1].SrcAdd = sourceAddress + _64KB; +* dmaRecoredArray[1].NextRecPtr = &dmaRecoredArray[2]; +* dmaRecoredArray[2].ByteCnt = _64KB; +* dmaRecoredArray[2].DestAdd = destAddress + 2*_64KB; +* dmaRecoredArray[2].SrcAdd = sourceAddress + 2*_64KB; +* dmaRecoredArray[2].NextRecPtr = &dmaRecoredArray[3]; +* dmaRecoredArray[3].ByteCnt = _64KB; +* dmaRecoredArray[3].DestAdd = destAddress + 3*_64KB; +* dmaRecoredArray[3].SrcAdd = sourceAddress + 3*_64KB; +* dmaRecoredArray[3].NextRecPtr = NULL; +* performCmDma(0,sourceAddress,destAddress,_64KB,PLAIN,WAIT_TO_END, +* &dmaRecoredArray[1]); +* Returns: NO_SUCH_CHANNEL if channel does not exist, CHANNEL_BUSY if channel +* is active and true if the transfer ended successfully +*********************************************************************/ + +DMA_STATUS dmaTransfer(DMA_ENGINE channel, unsigned int sourceAddr, + unsigned int destAddr, unsigned int numOfBytes, + unsigned int command, + DMA_RECORED * nextRecoredPointer) +{ + unsigned int tempData, checkBits, alignmentOffset = 0; + DMA_RECORED *next = nextRecoredPointer; + + if (channel > LAST_DMA_ENGINE) + return NO_SUCH_CHANNEL; + if (numOfBytes > 0xffff) + return GENERAL_ERROR; + if (isDmaChannelActive(channel)) + return CHANNEL_BUSY; + if (next != NULL) { /* case of chain Mode */ + alignmentOffset = ((unsigned int) next % 16); + } + checkBits = command & 0x6000000; + if (checkBits == 0) { + while (next != NULL) { + WRITE_WORD((unsigned int) next - alignmentOffset, + next->ByteCnt); + tempData = (unsigned int) next->SrcAdd; + WRITE_WORD((unsigned int) next + 4 - + alignmentOffset, tempData & 0x5fffffff); + tempData = (unsigned int) next->DestAdd; + WRITE_WORD((unsigned int) next + 8 - + alignmentOffset, tempData & 0x5fffffff); + tempData = (unsigned int) next->NextRecPtr; + WRITE_WORD((unsigned int) next + 12 - + alignmentOffset, + tempData & 0x5fffffff - + alignmentOffset); + next = (DMA_RECORED *) tempData; + if (next == nextRecoredPointer) + next = NULL; + } + } + GT_REG_WRITE(CHANNEL0_DMA_BYTE_COUNT + channel * 4, numOfBytes); + tempData = sourceAddr; + GT_REG_WRITE(CHANNEL0_DMA_SOURCE_ADDRESS + channel * 4, + tempData & 0x5fffffff); + tempData = destAddr; + GT_REG_WRITE(CHANNEL0_DMA_DESTINATION_ADDRESS + channel * 4, + tempData & 0x5fffffff); + if (nextRecoredPointer != NULL) { + tempData = + (unsigned int) nextRecoredPointer - alignmentOffset; + GT_REG_WRITE(CHANNEL0NEXT_RECORD_POINTER + 4 * channel, + tempData & 0x5fffffff); + command = command | CHANNEL_ENABLE; + } else { + command = command | CHANNEL_ENABLE | NON_CHAIN_MOD; + } + /* Activate DMA engine By writting to dmaControlRegister */ + GT_REG_WRITE(CHANNEL0CONTROL + channel * 4, command); + + return DMA_OK; +} + +/******************************************************************** +* isDmaChannelActive - check if channel is busy +* +* Inputs: channel number +* RETURNS: True if the channel is busy, false otherwise. +*********************************************************************/ + +bool isDmaChannelActive(DMA_ENGINE channel) +{ + unsigned int data; + + if (channel > LAST_DMA_ENGINE) + return false; + GT_REG_READ(CHANNEL0CONTROL + 4 * channel, &data); + if (data & DMA_ACTIVITY_STATUS) + return true; + else + return false; +} + + +/******************************************************************** +* changeDmaPriority - update the arbiter`s priority for channels 0-3 +* +* Inputs: priority for channels 0-1, priority for channels 2-3, + priority for groups and other priority options +* RETURNS: false if one of the parameters is erroneous and true else +*********************************************************************/ + +bool changeDmaPriority(PRIO_CHAN_0_1 prio_01, PRIO_CHAN_2_3 prio_23, + PRIO_GROUP prioGrp, PRIO_OPT prioOpt) +{ + unsigned int prioReg = 0; + + prioReg = (prio_01 & 0x3) + ((prio_23 & 0x3) << 2) + + ((prioGrp & 0x3) << 4) + (prioOpt << 6); + GT_REG_WRITE(ARBITER_CONTROL, prioReg); + return true; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev64120/i2o.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,689 @@ +/* i2o.c - Drivers for the I2O */ + +/* Copyright - Galileo technology. */ + +/*includes*/ + +#include + +#ifdef __linux__ +#include +#include +#else +#include "Core.h" +#include "i2o.h" +#endif + +/******************************************************************** +* getInBoundMessage - When the GT is configured for I2O support +* it can receive a message from an agent on the pci bus. +* This message is a 32 bit wide and can be read by +* the CPU. +* The messaging unit contains two sets of registers +* so, actually it can receive a 64 bit message. +* +* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. +* OUTPUT: N/A. +* RETURNS: Data received from the remote agent. +*********************************************************************/ +unsigned int getInBoundMessage(I2O_MESSAGE_REG messageRegNum) +{ + unsigned int regValue; + + GT_REG_READ(INBOUND_MESSAGE_REGISTER0_CPU_SIDE + 4 * messageRegNum, + ®Value); + return (regValue); +} + + +/******************************************************************** +* checkInboundIntAndClear - When a message is received an interrupt is +* generated, to enable polling instead the use of +* an interrupt handler the user can use this fuction. +* You will need to mask the incomming interrupt for +* proper use. +* +* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. +* OUTPUT: N/A. +* RETURNS: true if the corresponding bit in the cause register is set otherwise +* false. +*********************************************************************/ +bool checkInBoundIntAndClear(I2O_MESSAGE_REG messageRegNum) +{ + unsigned int regValue; + + GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, ®Value); + /* clears bit 0 for message register 0 or bit 1 for message register 1 */ + GT_REG_WRITE(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, + BIT1 * messageRegNum); + switch (messageRegNum) { + case MESSAGE_REG_0: + if (regValue & BIT0) + return true; + break; + case MESSAGE_REG_1: + if (regValue & BIT1) + return true; + break; + } + return false; +} + +/******************************************************************** +* sendOutBoundMessage - When the GT is configured for I2O support +* it can send a message to an agent on the pci bus. +* This message is a 32 bit wide and can be read by +* the PCI agent. +* The messaging unit contains two sets of registers +* so, actually it can send a 64 bit message. +* +* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. +* unsigned int message - Message to be sent. +* OUTPUT: N/A. +* RETURNS: true. +*********************************************************************/ +bool sendOutBoundMessage(I2O_MESSAGE_REG messageRegNum, + unsigned int message) +{ + GT_REG_WRITE(OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE + + 4 * messageRegNum, message); + return true; +} + +/******************************************************************** +* checkOutboundInt - When the CPU sends a message to the Outbound +* register it generates an interrupt which is refelcted on +* the Outbound Interrupt cause register, the interrupt can +* be cleard only by the PCI agent which read the message. +* After sending the message you can acknowledge it by +* monitoring the corresponding bit in the cause register. +* +* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. +* OUTPUT: N/A. +* RETURNS: true if the corresponding bit in the cause register is set otherwise +* false. +*********************************************************************/ +bool outBoundMessageAcknowledge(I2O_MESSAGE_REG messageRegNum) +{ + unsigned int regValue; + + GT_REG_READ(OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, ®Value); + switch (messageRegNum) { + case MESSAGE_REG_0: + if (regValue & BIT0) + return true; + break; + case MESSAGE_REG_1: + if (regValue & BIT1) + return true; + break; + } + return false; +} + +/******************************************************************** +* maskInBoundMessageInterrupt - Mask the inbound interrupt, when masking +* the interrupt you can work in polling mode +* using the checkInboundIntAndClear function. +* +* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. +* OUTPUT: N/A. +* RETURNS: true. +*********************************************************************/ +bool maskInBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum) +{ + switch (messageRegNum) { + case MESSAGE_REG_0: + SET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, + BIT0); + break; + case MESSAGE_REG_1: + SET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, + BIT1); + break; + } + return true; +} + +/******************************************************************** +* enableInBoundMessageInterrupt - unMask the inbound interrupt. +* +* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. +* OUTPUT: N/A. +* RETURNS: true. +*********************************************************************/ +bool enableInBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum) +{ + switch (messageRegNum) { + case MESSAGE_REG_0: + RESET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, + BIT0); + break; + case MESSAGE_REG_1: + RESET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, + BIT1); + break; + } + return true; +} + +/******************************************************************** +* maskOutboundMessageInterrupt - Mask the out bound interrupt, when doing so +* the PCI agent needs to poll on the interrupt +* cause register to monitor an incoming message. +* +* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. +* OUTPUT: N/A. +* RETURNS: true. +*********************************************************************/ +bool maskOutBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum) +{ + switch (messageRegNum) { + case MESSAGE_REG_0: + SET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, + BIT0); + break; + case MESSAGE_REG_1: + SET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, + BIT1); + break; + } + return true; +} + +/******************************************************************** +* enableOutboundMessageInterrupt - Mask the out bound interrupt, when doing so +* the PCI agent needs to poll on the interrupt +* cause register to monitor an incoming message. +* +* INPUTS: I2O_MESSAGE_REG messageRegNum - Selected set (0 or 1) register. +* OUTPUT: N/A. +* RETURNS: true. +*********************************************************************/ +bool enableOutBoundMessageInterrupt(I2O_MESSAGE_REG messageRegNum) +{ + switch (messageRegNum) { + case MESSAGE_REG_0: + RESET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, + BIT0); + break; + case MESSAGE_REG_1: + RESET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, + BIT1); + break; + } + return true; +} + +/******************************************************************** +* initiateOutBoundDoorBellInt - Setting a bit in this register to '1' by the +* CPU generates a PCI interrupt (if it is not masked by +* the Outbound interrupt Mask register) +* Only the PCI agent which recieved the interrupt can +* clear it, only after clearing all the bits the +* interrupt will be de-asserted. +* +* INPUTS: unsigned int data - Requested interrupt bits. +* OUTPUT: N/A. +* RETURNS: true. +*********************************************************************/ +bool initiateOutBoundDoorBellInt(unsigned int data) +{ + GT_REG_WRITE(OUTBOUND_DOORBELL_REGISTER_CPU_SIDE, data); + return true; +} + +/******************************************************************** +* readInBoundDoorBellInt - Read the in bound door bell interrupt cause +* register. +* +* OUTPUT: N/A. +* RETURNS: The 32 bit interrupt cause register. +*********************************************************************/ +unsigned int readInBoundDoorBellInt() +{ + unsigned int regData; + GT_REG_READ(INBOUND_DOORBELL_REGISTER_CPU_SIDE, ®Data); + return regData; +} + +/******************************************************************** +* clearInBoundDoorBellInt - An interrupt generated by a PCI agent through +* the in bound door bell mechanisem can be cleared +* only by the CPU. The interrupt will be de-asserted +* only if all the bits which where set by the PCI +* agent are cleared. +* +* INPUTS: unsigned int data - Bits to be cleared. +* OUTPUT: N/A. +* RETURNS: true. +*********************************************************************/ +bool clearInBoundDoorBellInt(unsigned int data) +{ + GT_REG_WRITE(INBOUND_DOORBELL_REGISTER_CPU_SIDE, data); + return true; +} + +/******************************************************************** +* isInBoundDoorBellInterruptSet - Check if Inbound Doorbell Interrupt is set, +* can be used for polling mode. +* +* INPUTS: N/A. +* OUTPUT: N/A. +* RETURNS: true if the corresponding bit in the cause register is set otherwise +* false. +*********************************************************************/ +bool isInBoundDoorBellInterruptSet() +{ + unsigned int regData; + + GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, ®Data); + return (regData & BIT2); +} + +/******************************************************************** +* isOutBoundDoorBellInterruptSet - Check if out bound Doorbell Interrupt is +* set, can be used for acknowledging interrupt +* handling by the agent who recieived the +* interrupt. +* +* INPUTS: N/A. +* OUTPUT: N/A. +* RETURNS: true if the corresponding bit in the cause register is set otherwise +* false. +*********************************************************************/ +bool isOutBoundDoorBellInterruptSet() +{ + unsigned int regData; + + GT_REG_READ(OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, ®Data); + return (regData & BIT2); +} + +/******************************************************************** +* maskInboundDoorBellInterrupt - Mask the Inbound Doorbell Interrupt. +* +* INPUTS: N/A. +* OUTPUT: N/A. +* RETURNS: true. +*********************************************************************/ +bool maskInBoundDoorBellInterrupt() +{ + SET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2); + return true; +} + +/******************************************************************** +* enableInboundDoorBellInterrupt - unMask the Inbound Doorbell Interrupt. +* +* INPUTS: N/A. +* OUTPUT: N/A. +* RETURNS: true. +*********************************************************************/ +bool enableInBoundDoorBellInterrupt() +{ + RESET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2); + return true; +} + +/******************************************************************** +* maskOutboundDoorBellInterrupt - Mask the Outbound Doorbell Interrupt. +* +* INPUTS: N/A. +* OUTPUT: N/A. +* RETURNS: true. +*********************************************************************/ +bool maskOutBoundDoorBellInterrupt() +{ + SET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2); + return true; +} + +/******************************************************************** +* enableOutboundDoorBellInterrupt - unMask the Outbound Doorbell Interrupt. +* +* INPUTS: N/A. +* OUTPUT: N/A. +* RETURNS: true. +*********************************************************************/ +bool enableOutBoundDoorBellInterrupt() +{ + RESET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2); + return true; +} + +/******************************************************************** +* circularQueueEnable - Initialize the I2O messaging mechanism. +* +* INPUTS: CIRCULE_QUEUE_SIZE cirQueSize - Bits 5:1 in the: +* Queue Control Register, Offset 0x50 (0x1c50). +* Defines the queues size (refer to the data sheet +* for more information) +* unsigned int queueBaseAddr - The base address for the first queue. +* The other queues base Address will be determined as follows: +* Inbound Free = queueBaseAddr +* Inbound Post = queueBaseAddr + cirQueSize +* Outbound Post = queueBaseAddr + cirQueSize +* +* OUTPUT: N/A. +* RETURNS: true. +* +* The Circular Queue Starting Addresses as written in the spec: +* ---------------------------------------- +* | Queue | Starting Address | +* |----------------|---------------------| +* | Inbound Free | QBAR | +* | Inbound Post | QBAR + Queue Size | +* | Outbound Post | QBAR + 2*Queue Size | +* | Outbound Free | QBAR + 3*Queue Size | +* ---------------------------------------- +*********************************************************************/ +bool circularQueueEnable(CIRCULAR_QUEUE_SIZE cirQueSize, + unsigned int queueBaseAddr) +{ + unsigned int regData; + + regData = BIT0 | (cirQueSize << 1); + /* Enable Queue Operation */ + GT_REG_WRITE(QUEUE_CONTROL_REGISTER_CPU_SIDE, regData); + /* Writing The base Address for the 4 Queues */ + GT_REG_WRITE(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, queueBaseAddr); + /* Update The Inbound Free Queue Base Address, offset=0 */ + GT_REG_WRITE(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE, 0); + GT_REG_WRITE(INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE, 0); + /* Update The Inbound Post Queue Base Address, offset=_16K*cirQueSize */ + GT_REG_WRITE(INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE, + _16K * cirQueSize); + GT_REG_WRITE(INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE, + _16K * cirQueSize); + /* Update The Outbound Post Queue Base Address, offset=2*_16K*cirQueSize */ + GT_REG_WRITE(OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE, + 2 * _16K * cirQueSize); + GT_REG_WRITE(OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE, + 2 * _16K * cirQueSize); + /* Update The Outbound Free Queue Base Address, offset=3*_16K*cirQueSize */ + GT_REG_WRITE(OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE, + 3 * _16K * cirQueSize); + GT_REG_WRITE(OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE, + 3 * _16K * cirQueSize); + return true; +} + +/******************************************************************** +* inBoundPostQueuePop - Two actions are being taken upon pop: +* 1) Getting out the data from the Queue`s head. +* 2) Increment the tail pointer in a cyclic way (The HEAD is +* incremented automaticaly by the GT) +* +* INPUTS: N/A. +* OUTPUT: N/A. +* RETURNS: Data pointed by tail. +*********************************************************************/ +unsigned int inBoundPostQueuePop() +{ + unsigned int tailAddrPointer; + unsigned int data; + unsigned int cirQueSize; + unsigned int qBar; + unsigned int inBoundPostQbase; + + /* Gets the Inbound Post TAIL pointer */ + GT_REG_READ(INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE, + &tailAddrPointer); + /* Gets the Data From the pointer Address */ + READ_WORD(tailAddrPointer, &data); + /* incrementing head process: */ + /* Gets the fifo's base Address */ + GT_REG_READ(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, &qBar); + qBar = qBar & 0xfff00000; + /* Gets the fifo's size */ + GT_REG_READ(QUEUE_CONTROL_REGISTER_CPU_SIDE, &cirQueSize); + cirQueSize = 0x1f && (cirQueSize >> 1); + /* calculating The Inbound Post Queue Base Address */ + inBoundPostQbase = qBar + 1 * cirQueSize * _16K; + /* incrementing Inbound Post queue TAIL in a cyclic loop */ + tailAddrPointer = inBoundPostQbase + ((tailAddrPointer + 4) % + (_16K * cirQueSize)); + /* updating the pointer back to INBOUND_POST_TAIL_POINTER_REGISTER */ + GT_REG_WRITE(INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE, + tailAddrPointer); + return data; +} + +/******************************************************************** +* isInBoundPostQueueInterruptSet - Check if in bound interrupt is set. +* can be used for polling mode. +* +* INPUTS: N/A. +* OUTPUT: N/A. +* RETURNS: true if the corresponding bit in the cause register is set otherwise +* false. +*********************************************************************/ +bool isInBoundPostQueueInterruptSet() +{ + unsigned int regData; + + GT_REG_READ(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, ®Data); + return (regData & BIT4); /* if set return '1' (true), else '0' (false) */ +} + +/******************************************************************** +* clearInBoundPostQueueInterrupt - Clears the Post queue interrupt. +* +* INPUTS: N/A. +* OUTPUT: N/A. +* RETURNS: true. +*********************************************************************/ +bool clearInBoundPostQueueInterrupt() +{ + GT_REG_WRITE(INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE, BIT4); + return true; +} + +/******************************************************************** +* maskInBoundPostQueueInterrupt - Mask the inbound interrupt, when masking +* the interrupt you can work in polling mode. +* +* INPUTS: N/A. +* OUTPUT: N/A. +* RETURNS: +*********************************************************************/ +void maskInBoundPostQueueInterrupt() +{ + unsigned int regData; + + GT_REG_READ(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, ®Data); + GT_REG_WRITE(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, + regData | BIT4); + +} + +/******************************************************************** +* enableInBoundPostQueueInterrupt - Enable interrupt when ever there is a new +* message from the PCI agent. +* +* INPUTS: N/A. +* OUTPUT: N/A. +* RETURNS: +*********************************************************************/ +void enableInBoundPostQueueInterrupt() +{ + unsigned int regData; + + GT_REG_READ(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, ®Data); + GT_REG_WRITE(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, + regData & 0xfffffffb); +} + +/******************************************************************** +* inBoundFreeQueuePush - Two actions are being taken upon push: +* 1) Place the user`s data on the Queue`s head. +* 2) Increment the haed pointer in a cyclic way (The tail is +* decremented automaticaly by the GT) +* +* INPUTS: unsigned int data - Data to be placed in the queue. +* OUTPUT: N/A. +* RETURNS: true. +*********************************************************************/ +bool inBoundFreeQueuePush(unsigned int data) +{ + unsigned int headPointer; + unsigned int cirQueSize; + unsigned int qBar; + unsigned int inBoundFreeQbase; + + GT_REG_READ(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE, + &headPointer); + /* placing the data in the queue */ + WRITE_WORD(headPointer, data); + /* incrementing head process: */ + /* Gets the fifo's base Address */ + GT_REG_READ(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, &qBar); + qBar = qBar & 0xfff00000; + /* Gets the fifo's size */ + GT_REG_READ(QUEUE_CONTROL_REGISTER_CPU_SIDE, &cirQueSize); + cirQueSize = 0x1f && (cirQueSize >> 1); + /* calculating The Inbound Free Queue Base Address */ + inBoundFreeQbase = qBar; + /* incrementing Inbound Free queue HEAD in a cyclic loop */ + headPointer = + inBoundFreeQbase + ((headPointer + 4) % (_16K * cirQueSize)); + /* updating the pointer back to OUTBOUND_POST_HEAD_POINTER_REGISTER */ + GT_REG_WRITE(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE, + headPointer); + return true; +} + +/******************************************************************** +* isInBoundFreeQueueEmpty - Check if Inbound Free Queue Empty. +* Can be used for acknowledging the messages +* being sent by us to the PCI agent. +* +* INPUTS: N/A. +* OUTPUT: N/A. +* RETURNS: true if the queue is empty , otherwise false. +*********************************************************************/ +bool isInBoundFreeQueueEmpty() +{ + unsigned int inBoundFreeQueHead; + unsigned int inBoundFreeQueTail; + + GT_REG_READ(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE, + &inBoundFreeQueHead); + GT_REG_READ(INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE, + &inBoundFreeQueTail); + if (inBoundFreeQueHead == inBoundFreeQueTail) { + return true; + } else + return false; +} + +/******************************************************************** +* outBoundPostQueuePush - Two actions are being taken upon push: +* 1) Place the user`s data on the Queue`s head. +* 2) Increment the haed pointer in a cyclic way (The tail is +* decremented automaticaly by the GT when the Agent on the +* PCI have read data from the Outbound Port). +* +* INPUTS: unsigned int data - Data to be placed in the queue`s head. +* OUTPUT: N/A. +* RETURNS: true. +*********************************************************************/ +bool outBoundPostQueuePush(unsigned int data) +{ + unsigned int headPointer; + unsigned int cirQueSize; + unsigned int qBar; + unsigned int outBoundPostQbase; + + GT_REG_READ(OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE, + &headPointer); + /* placing the data in the queue (where the head point to..) */ + WRITE_WORD(headPointer, data); + /* incrementing head process: */ + /* Gets the fifo's base Address */ + GT_REG_READ(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, &qBar); + qBar = qBar & 0xfff00000; + /* Gets the fifo's size */ + GT_REG_READ(QUEUE_CONTROL_REGISTER_CPU_SIDE, &cirQueSize); + cirQueSize = 0x1f && (cirQueSize >> 1); + /* calculating The Outbound Post Queue Base Address */ + outBoundPostQbase = qBar + 2 * cirQueSize * _16K; + /* incrementing Outbound Post queue in a cyclic loop */ + headPointer = + outBoundPostQbase + ((headPointer + 4) % (_16K * cirQueSize)); + /* updating the pointer back to OUTBOUND_POST_HEAD_POINTER_REGISTER */ + GT_REG_WRITE(OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE, + headPointer); + return true; +} + +/******************************************************************** +* isOutBoundPostQueueEmpty - Check if Outbound Post Queue Empty. +* Can be used for acknowledging the messages +* being sent by us to the PCI agent. +* +* INPUTS: N/A. +* OUTPUT: N/A. +* RETURNS: true if the queue is empty , otherwise false. +*********************************************************************/ +bool isOutBoundPostQueueEmpty() +{ + unsigned int outBoundPostQueHead; + unsigned int outBoundPostQueTail; + + GT_REG_READ(INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE, + &outBoundPostQueHead); + GT_REG_READ(INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE, + &outBoundPostQueTail); + if (outBoundPostQueHead == outBoundPostQueTail) { + return true; + } else + return false; +} + +/******************************************************************** +* outBoundFreeQueuePop - Two actions are being taken upon pop: +* 1) Getting out the data from the Queue`s head. +* 2) Increment the tail pointer in a cyclic way (The HEAD is +* incremented automaticaly by the GT) +* +* INPUTS: N/A. +* OUTPUT: N/A. +* RETURNS: Data pointed by tail. +*********************************************************************/ +unsigned int outBoundFreeQueuePop() +{ + unsigned int tailAddrPointer; + unsigned int data; + unsigned int cirQueSize; + unsigned int qBar; + unsigned int outBoundFreeQbase; + + /* Gets the Inbound Post TAIL pointer */ + GT_REG_READ(OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE, + &tailAddrPointer); + /* Gets the Data From the pointer Address */ + READ_WORD(tailAddrPointer, &data); + /* incrementing head process: */ + /* Gets the fifo's base Address */ + GT_REG_READ(QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE, &qBar); + qBar = qBar & 0xfff00000; + /* Gets the fifo's size */ + GT_REG_READ(QUEUE_CONTROL_REGISTER_CPU_SIDE, &cirQueSize); + cirQueSize = 0x1f && (cirQueSize >> 1); + /* calculating The Inbound Post Queue Base Address */ + outBoundFreeQbase = qBar + 3 * cirQueSize * _16K; + /* incrementing Outbound Free queue TAlL in a cyclic loop */ + tailAddrPointer = outBoundFreeQbase + ((tailAddrPointer + 4) % + (_16K * cirQueSize)); + /* updating the pointer back to OUTBOUND_FREE_TAIL_POINTER_REGISTER */ + GT_REG_WRITE(OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE, + tailAddrPointer); + return data; +} + + +EXPORT_SYMBOL(isInBoundDoorBellInterruptSet); +EXPORT_SYMBOL(initiateOutBoundDoorBellInt); +EXPORT_SYMBOL(clearInBoundDoorBellInt); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev64120/int-handler.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,85 @@ +/* + * int-handler.S + * + * Based on the cobalt handler. + */ +#include +#include +#include +#include +#include + +/* + * We check for the timer first, then check PCI ints A and D. + * Then check for serial IRQ and fall through. + */ + .align 5 + .set reorder + .set noat + NESTED(galileo_handle_int, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + + mfc0 t0, CP0_CAUSE + mfc0 t2, CP0_STATUS + + and t0, t2 + + .set noreorder + andi t1, t0, STATUSF_IP4 /* int2 hardware line (timer) */ + andi t2, t0, STATUSF_IP2 /* int0 hardware line */ + bnez t1, ll_galileo_irq + andi t1, t0, STATUSF_IP5 /* int3 hardware line */ + bnez t2, ll_pci_intA + andi t2, t0, STATUSF_IP6 /* int4 hardware line */ + bnez t1, ll_pci_intD + andi t1, t0, STATUSF_IP7 /* compare int */ + bnez t2, ll_serial_irq + nop + bnez t1, ll_compare_irq + nop + .set reorder + + j spurious_interrupt + END(galileo_handle_int) + + .align 5 +ll_galileo_irq: li a0, 4 + move a1, sp + jal do_IRQ + j ret_from_irq + + .align 5 +ll_compare_irq: li a0, 7 + move a1, sp + jal do_IRQ + j ret_from_irq + + .align 5 +ll_pci_intA: move a0, sp + jal pci_intA + j ret_from_irq + +#if 0 + .align 5 +ll_pci_intB: move a0, sp + jal pci_intB + j ret_from_irq + + .align 5 +ll_pci_intC: move a0, sp + jal pci_intC + j ret_from_irq +#endif + + .align 5 +ll_pci_intD: move a0, sp + jal pci_intD + j ret_from_irq + + .align 5 +ll_serial_irq: li a0, 6 + move a1, sp + jal do_IRQ + j ret_from_irq --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev64120/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,184 @@ +/* + * BRIEF MODULE DESCRIPTION + * Code to handle irqs on GT64120A boards + * Derived from mips/orion and Cort + * + * Copyright (C) 2000 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_AGENTS_PER_INT 21 /* Random number */ +unsigned char pci_int_irq[MAX_AGENTS_PER_INT]; +static int max_interrupts = 0; + +asmlinkage void pci_intA(struct pt_regs *regs) +{ + unsigned int count = 0; + + /* This must be a joke - Ralf */ + for (count = 0; count < max_interrupts; count++) + do_IRQ(pci_int_irq[count], regs); +} + +asmlinkage void pci_intD(struct pt_regs *regs) +{ + unsigned int count = 0; + + /* Encore une fois - This must be a joke - Ralf */ + for (count = 0; count < max_interrupts; count++) + do_IRQ(pci_int_irq[count], regs); +} + +/* + * Now this is scarry. A disable_irq(2) or disable_irq(5) would just + * accidently disable a pci irq. It shouldn't happen but may just leaving + * these always enabled or use some reference counting wouldn't be such a + * bad thing. + */ +static void disable_ev64120_irq(unsigned int irq_nr) +{ + unsigned long flags; + + local_irq_save(flags); + if (irq_nr >= 8) { + /* All PCI interrupts are on line 5 or 2 */ + clear_c0_status(IE_IRQ0 | IE_IRQ3); + } else { + clear_c0_status(0x100 << irq_nr); + } + local_irq_restore(flags); +} + +#define mask_and_ack_ev64120_irq disable_ev64120_irq + +static inline void enable_ev64120_irq(unsigned int irq_nr) +{ + unsigned long flags; + + local_irq_save(flags); + if (irq_nr >= 8) { + /* All PCI interrupts are on line 5 or 2 */ + set_c0_status(IE_IRQ0 | IE_IRQ3); + } else { + set_c0_status(IE_SW0 << irq_nr); + } + local_irq_restore(flags); +} + +static unsigned int startup_ev64120_irq(unsigned int irq) +{ + if (irq >= 8) { + // NOTE: Add error-handling if > max + pci_int_irq[max_interrupts++] = irq; + } + enable_ev64120_irq(irq); + + return 0; +} + +static void shutdown_ev64120_irq(unsigned int irq) +{ + int count, tmp; + + /* + * Remove PCI interrupts from the pci_int_irq list. Make sure + * that some handler was removed before decrementing max_interrupts. + */ + if (irq >= 8) { + for (count = 0; count < max_interrupts; count++) { + if (pci_int_irq[count] == irq) { + for (tmp = count; tmp < max_interrupts; tmp++) { + pci_int_irq[tmp] = + pci_int_irq[tmp + 1]; + } + } + } + max_interrupts--; + } +} + +static void end_ev64120_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_ev64120_irq(irq); +} + +static struct hw_interrupt_type ev64120_irq_type = { + "EV64120", + startup_ev64120_irq, + shutdown_ev64120_irq, + enable_ev64120_irq, + disable_ev64120_irq, + mask_and_ack_ev64120_irq, + end_ev64120_irq +}; + +/* + * galileo_irq_setup - Initializes CPU interrupts + */ +void __init init_IRQ(void) +{ + extern asmlinkage void galileo_handle_int(void); + int i; + + init_generic_irq(); + + /* Yes, how many interrupts does this beast actually have? -- Ralf */ + for (i = 0; i < NR_IRQS; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &ev64120_irq_type; + } + + /* + * Clear all of the interrupts while we change the able around a bit. + * Enable timer. Other interrupts will be enabled as they are + * registered. + */ + change_c0_status(ST0_IM | IE_IRQ2, IE_IRQ2); + + /* Sets the exception_handler array. */ + set_except_vector(0, galileo_handle_int); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev64120/irq-handler.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,270 @@ +/* + * Galileo Technology chip interrupt handler + * + * Modified by RidgeRun, Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * These are interrupt handlers for the GT on-chip interrupts. They all come + * in to the MIPS on a single interrupt line, and have to be handled and ack'ed + * differently than other MIPS interrupts. + */ + +#if CURRENTLY_UNUSED + +struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH]; +void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr); + +/* + * hook_irq_handler + * + * Hooks IRQ handler to the system. When the system is interrupted + * the interrupt service routine is called. + * + * Inputs : + * int_cause - The interrupt cause number. In EVB64120 two parameters + * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. + * bit_num - Indicates which bit number in the cause register + * isr_ptr - Pointer to the interrupt service routine + * + * Outputs : + */ +void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr) +{ + irq_handlers[int_cause][bit_num].routine = isr_ptr; +} + + +/* + * enable_galileo_irq + * + * Enables the IRQ on Galileo Chip + * + * Inputs : + * int_cause - The interrupt cause number. In EVB64120 two parameters + * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. + * bit_num - Indicates which bit number in the cause register + * + * Outputs : + * 1 if succesful, 0 if failure + */ +int enable_galileo_irq(int int_cause, int bit_num) +{ + if (int_cause == INT_CAUSE_MAIN) + SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num)); + else if (int_cause == INT_CAUSE_HIGH) + SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER, + (1 << bit_num)); + else + return 0; + return 1; +} + +/* + * disable_galileo_irq + * + * Disables the IRQ on Galileo Chip + * + * Inputs : + * int_cause - The interrupt cause number. In EVB64120 two parameters + * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. + * bit_num - Indicates which bit number in the cause register + * + * Outputs : + * 1 if succesful, 0 if failure + */ +int disable_galileo_irq(int int_cause, int bit_num) +{ + if (int_cause == INT_CAUSE_MAIN) + RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, + (1 << bit_num)); + else if (int_cause == INT_CAUSE_HIGH) + RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER, + (1 << bit_num)); + else + return 0; + return 1; +} + +#endif /* UNUSED */ + +/* + * galileo_irq - + * + * Interrupt handler for interrupts coming from the Galileo chip. + * It could be timer interrupt, built in ethernet ports etc... + * + * Inputs : + * + * Outputs : + * + */ +static void galileo_irq(int irq, void *dev_id, struct pt_regs *regs) +{ + unsigned int irq_src, int_high_src, irq_src_mask, + int_high_src_mask; + int handled; + unsigned int count; + static int counter = 0; + + GT_READ(GT_INTRCAUSE_OFS, &irq_src); + GT_READ(GT_INTRMASK_OFS, &irq_src_mask); + GT_READ(GT_HINTRCAUSE_OFS, &int_high_src); + GT_READ(GT_HINTRMASK_OFS, &int_high_src_mask); + irq_src = irq_src & irq_src_mask; + int_high_src = int_high_src & int_high_src_mask; + + handled = 0; + + /* Execute all interrupt handlers */ + /* Check for timer interrupt */ + if (irq_src & 0x00000800) { + handled = 1; + irq_src &= ~0x00000800; + // RESET_REG_BITS (INTERRUPT_CAUSE_REGISTER,BIT8); + do_timer(regs); + } + + if (irq_src) { + printk(KERN_INFO + "Other Galileo interrupt received irq_src %x\n", + irq_src); +#if CURRENTLY_UNUSED + for (count = 0; count < MAX_CAUSE_REG_WIDTH; count++) { + if (irq_src & (1 << count)) { + if (irq_handlers[INT_CAUSE_MAIN][count]. + routine) { + queue_task(&irq_handlers + [INT_CAUSE_MAIN][count], + &tq_immediate); + mark_bh(IMMEDIATE_BH); + handled = 1; + } + } + } +#endif /* UNUSED */ + } + GT_WRITE(GT_INTRCAUSE_OFS, 0); + GT_WRITE(GT_HINTRCAUSE_OFS, 0); + +#undef GALILEO_I2O +#ifdef GALILEO_I2O + /* + Future I2O support. We currently attach I2O interrupt handlers to the + Galileo interrupt (int 4) and handle them in do_IRQ. + */ + if (isInBoundDoorBellInterruptSet()) { + printk(KERN_INFO "I2O doorbell interrupt received.\n"); + handled = 1; + } + + if (isInBoundPostQueueInterruptSet()) { + printk(KERN_INFO "I2O Queue interrupt received.\n"); + handled = 1; + } + + /* + This normally would be outside of the ifdef, but since + we're handling I2O outside of this handler, this + printk shows up every time we get a valid I2O + interrupt. So turn this off for now. + */ + if (handled == 0) { + if (counter < 50) { + printk("Spurious Galileo interrupt...\n"); + counter++; + } + } +#endif +} + +/* + * galileo_time_init - + * + * Initializes timer using galileo's built in timer. + * + * + * Inputs : + * irq - number of irq to be used by the timer + * + * Outpus : + * + */ +#ifdef CONFIG_SYSCLK_100 +#define Sys_clock (100 * 1000000) // 100 MHz +#endif +#ifdef CONFIG_SYSCLK_83 +#define Sys_clock (83.333 * 1000000) // 83.333 MHz +#endif +#ifdef CONFIG_SYSCLK_75 +#define Sys_clock (75 * 1000000) // 75 MHz +#endif + +/* + * This will ignore the standard MIPS timer interrupt handler that is passed + * in as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt + * handling. + */ +void galileo_time_init(struct irqaction *irq) +{ + extern irq_desc_t irq_desc[NR_IRQS]; + static struct irqaction timer; + + /* Disable timer first */ + GT_WRITE(GT_TC_CONTROL_OFS, 0); + /* Load timer value for 100 Hz */ + GT_WRITE(GT_TC3_OFS, Sys_clock / 100); + + /* + * Create the IRQ structure entry for the timer. Since we're too early + * in the boot process to use the "request_irq()" call, we'll hard-code + * the values to the correct interrupt line. + */ + timer.handler = &galileo_irq; + timer.flags = SA_SHIRQ; + timer.name = "timer"; + timer.dev_id = NULL; + timer.next = NULL; + timer.mask = 0; + irq_desc[TIMER].action = &timer; + + /* Enable timer ints */ + GT_WRITE(GT_TC_CONTROL_OFS, 0xc0); + /* clear Cause register first */ + GT_WRITE(GT_INTRCAUSE_OFS, 0x0); + /* Unmask timer int */ + GT_WRITE(GT_INTRMASK_OFS, 0x800); + /* Clear High int register */ + GT_WRITE(GT_HINTRCAUSE_OFS, 0x0); + /* Mask All interrupts at High cause interrupt */ + GT_WRITE(GT_HINTRMASK_OFS, 0x0); + +} + +void galileo_irq_init(void) +{ +#if CURRENTLY_UNUSED + int i, j; + + /* Reset irq handlers pointers to NULL */ + for (i = 0; i < MAX_CAUSE_REGS; i++) { + for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) { + irq_handlers[i][j].next = NULL; + irq_handlers[i][j].sync = 0; + irq_handlers[i][j].routine = NULL; + irq_handlers[i][j].data = NULL; + } + } +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev64120/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,12 @@ +# +# Copyright 2000 RidgeRun, Inc. +# Author: RidgeRun, Inc. +# glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com +# +# Makefile for the Galileo EV64120 board. +# + +obj-y := serialGT.o int-handler.o promcon.o reset.o setup.o irq.o \ + irq-handler.o + +EXTRA_AFLAGS := $(CFLAGS) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev64120/promcon.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,70 @@ +/* + * Wrap-around code for a console using the + * SGI PROM io-routines. + * + * Copyright (c) 1999 Ulf Carlsson + * + * Derived from DECstation promcon.c + * Copyright (c) 1998 Harald Koerfgen + * Copyright (c) 2002 Ralf Baechle + */ + +#include +#include +#include +#include +#include +#include +/* +#include +*/ + +static void prom_console_write(struct console *co, const char *s, + unsigned count) +{ + extern int CONSOLE_CHANNEL; // The default serial port + unsigned i; + /* + * Now, do each character + */ + for (i = 0; i < count; i++) { + if (*s == 10) + serial_putc(CONSOLE_CHANNEL, 13); + serial_putc(CONSOLE_CHANNEL, *s++); + } +} +int prom_getchar(void) +{ + return 0; +} +static int __init prom_console_setup(struct console *co, char *options) +{ + return 0; +} + +static kdev_t prom_console_device(struct console *c) +{ + return mk_kdev(TTY_MAJOR, 64 + c->index); +} + +static struct console sercons = { + .name = "ttyS", + .write = prom_console_write, + .device = prom_console_device, + .setup = prom_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, +}; + + +/* + * Register console. + */ + +void gal_serial_console_init(void) +{ + // serial_init(); + //serial_set(115200); + + register_console(&sercons); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev64120/README 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,2 @@ +The compressed boot code was such a mess I deleted it. Feel free to +reimplement it -- Ralf --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev64120/reset.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,45 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1997, 2002 Ralf Baechle + */ +#include +#include +#include +#include +#include +#include +#include + +void galileo_machine_restart(char *command) +{ + *(volatile char *) 0xbc000000 = 0x0f; + /* + * Ouch, we're still alive ... This time we take the silver bullet ... + * ... and find that we leave the hardware in a state in which the + * kernel in the flush locks up somewhen during of after the PCI + * detection stuff. + */ + set_c0_status(ST0_BEV | ST0_ERL); + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + flush_cache_all(); + write_c0_wired(0); + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); +} + +void galileo_machine_halt(void) +{ + printk(KERN_NOTICE "You can safely turn off the power\n"); + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); + +} + +void galileo_machine_power_off(void) +{ + galileo_machine_halt(); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev64120/serialGT.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,212 @@ +/* + * serialGT.c + * + * BRIEF MODULE DESCRIPTION + * Low Level Serial Port control for use + * with the Galileo EVB64120A MIPS eval board and + * its on board two channel 16552 Uart. + * + * Copyright (C) 2000 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +// Note: +// Serial CHANNELS - 0 is the bottom connector of evb64120A. +// (The one that maps to the "B" channel of the +// board's uart) +// 1 is the top connector of evb64120A. +// (The one that maps to the "A" channel of the +// board's uart) +int DEBUG_CHANNEL = 0; // See Note Above +int CONSOLE_CHANNEL = 1; // See Note Above + +#define DUART 0xBD000000 /* Base address of Uart. */ +#define CHANNELOFFSET 0x20 /* DUART+CHANNELOFFSET gets you to the ChanA + register set of the 16552 Uart device. + DUART+0 gets you to the ChanB register set. + */ +#define DUART_DELTA 0x4 +#define FIFO_ENABLE 0x07 +#define INT_ENABLE 0x04 /* default interrupt mask */ + +#define RBR 0x00 +#define THR 0x00 +#define DLL 0x00 +#define IER 0x01 +#define DLM 0x01 +#define IIR 0x02 +#define FCR 0x02 +#define LCR 0x03 +#define MCR 0x04 +#define LSR 0x05 +#define MSR 0x06 +#define SCR 0x07 + +#define LCR_DLAB 0x80 +#define XTAL 1843200 +#define LSR_THRE 0x20 +#define LSR_BI 0x10 +#define LSR_DR 0x01 +#define MCR_LOOP 0x10 +#define ACCESS_DELAY 0x10000 + +/****************************** + Routine: + Description: + ******************************/ +int inreg(int channel, int reg) +{ + int val; + val = + *((volatile unsigned char *) DUART + + (channel * CHANNELOFFSET) + (reg * DUART_DELTA)); + return val; +} + +/****************************** + Routine: + Description: + ******************************/ +void outreg(int channel, int reg, unsigned char val) +{ + *((volatile unsigned char *) DUART + (channel * CHANNELOFFSET) + + (reg * DUART_DELTA)) = val; +} + +/****************************** + Routine: + Description: + Initialize the device driver. + ******************************/ +void serial_init(int channel) +{ + /* + * Configure active port, (CHANNELOFFSET already set.) + * + * Set 8 bits, 1 stop bit, no parity. + * + * LCR<7> 0 divisor latch access bit + * LCR<6> 0 break control (1=send break) + * LCR<5> 0 stick parity (0=space, 1=mark) + * LCR<4> 0 parity even (0=odd, 1=even) + * LCR<3> 0 parity enable (1=enabled) + * LCR<2> 0 # stop bits (0=1, 1=1.5) + * LCR<1:0> 11 bits per character(00=5, 01=6, 10=7, 11=8) + */ + outreg(channel, LCR, 0x3); + + outreg(channel, FCR, FIFO_ENABLE); /* Enable the FIFO */ + + outreg(channel, IER, INT_ENABLE); /* Enable appropriate interrupts */ +} + +/****************************** + Routine: + Description: + Set the baud rate. + ******************************/ +void serial_set(int channel, unsigned long baud) +{ + unsigned char sav_lcr; + + /* + * Enable access to the divisor latches by setting DLAB in LCR. + * + */ + sav_lcr = inreg(channel, LCR); + +#if 0 + /* + * Set baud rate + */ + outreg(channel, LCR, LCR_DLAB | sav_lcr); + // outreg(DLL,(XTAL/(16*2*(baud))-2)); + outreg(channel, DLL, XTAL / (16 * baud)); + // outreg(DLM,(XTAL/(16*2*(baud))-2)>>8); + outreg(channel, DLM, (XTAL / (16 * baud)) >> 8); +#else + /* + * Note: Set baud rate, hardcoded here for rate of 115200 + * since became unsure of above "buad rate" algorithm (??). + */ + outreg(channel, LCR, 0x83); + outreg(channel, DLM, 0x00); // See note above + outreg(channel, DLL, 0x02); // See note above. + outreg(channel, LCR, 0x03); +#endif + + /* + * Restore line control register + */ + outreg(channel, LCR, sav_lcr); +} + + +/****************************** + Routine: + Description: + Transmit a character. + ******************************/ +void serial_putc(int channel, int c) +{ + while ((inreg(channel, LSR) & LSR_THRE) == 0); + outreg(channel, THR, c); +} + +/****************************** + Routine: + Description: + Read a received character if one is + available. Return -1 otherwise. + ******************************/ +int serial_getc(int channel) +{ + if (inreg(channel, LSR) & LSR_DR) { + return inreg(channel, RBR); + } + return -1; +} + +/****************************** + Routine: + Description: + Used by embedded gdb client. (example; gdb-stub.c) + ******************************/ +char getDebugChar() +{ + int val; + while ((val = serial_getc(DEBUG_CHANNEL)) == -1); // loop until we get a character in. + return (char) val; +} + +/****************************** + Routine: + Description: + Used by embedded gdb target. (example; gdb-stub.c) + ******************************/ +void putDebugChar(char c) +{ + serial_putc(DEBUG_CHANNEL, (int) c); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev64120/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,176 @@ +/* + * BRIEF MODULE DESCRIPTION + * Galileo Evaluation Boards - board dependent boot routines + * + * Copyright (C) 2000 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern struct rtc_ops no_rtc_ops; + +/* These functions are used for rebooting or halting the machine*/ +extern void galileo_machine_restart(char *command); +extern void galileo_machine_halt(void); +extern void galileo_machine_power_off(void); +/* + *This structure holds pointers to the pci configuration space accesses + *and interrupts allocating routine for device over the PCI + */ +extern struct pci_ops galileo_pci_ops; + +extern unsigned long mips_machgroup; + +char arcs_cmdline[CL_SIZE] = { "console=ttyS0,115200 " + "root=/dev/nfs rw nfsroot=192.168.1.1:/mnt/disk2/fs.gal " + "ip=192.168.1.211:192.168.1.1:::gt::" +}; + +//struct eeprom_parameters eeprom_param; + +/* + * This function is added because arch/mips/mm/init.c needs it + * basically it does nothing + */ +void prom_free_prom_memory(void) +{ +} + +extern void (*board_time_init) (struct irqaction * irq); + +static unsigned char galileo_rtc_read_data(unsigned long addr) +{ + return 0; +} + +static void galileo_rtc_write_data(unsigned char data, unsigned long addr) +{ +} + +static int galileo_rtc_bcd_mode(void) +{ + return 0; +} + +struct rtc_ops galileo_rtc_ops = { + &galileo_rtc_read_data, + &galileo_rtc_write_data, + &galileo_rtc_bcd_mode +}; + +/******************************************************************** + *ev64120_setup - + * + *Initializes basic routines and structures pointers, memory size (as + *given by the bios and saves the command line. + * + * + *Inputs : + * + *Outpus : + * + *********************************************************************/ +extern void galileo_time_init(); + +void __init ev64120_setup(void) +{ + _machine_restart = galileo_machine_restart; + _machine_halt = galileo_machine_halt; + _machine_power_off = galileo_machine_power_off; + + rtc_ops = &galileo_rtc_ops; + + board_time_init = galileo_time_init; + set_io_port_base(KSEG1); + +#ifdef CONFIG_L2_L3_CACHE +#error "external cache not implemented yet" + config_register = read_c0_config(); + printk("\n\n\nchecking second level cache cp0_config = %08lx\n", + config_register); + if (config_register & CONF_SC) { // second/third level cache available + config_register = config_register & (1 << 12); + write_c0_config(config_register); + printk + ("\n\n\nchecking second level cache c0_config = %08lx\n", + config_register); + } +#endif +} + +const char *get_system_type(void) +{ + return "Galileo EV64120A"; +} + +/* + * SetUpBootInfo - + * + * This function is called at very first stages of kernel startup. + * It specifies for the kernel the evaluation board that the linux + * is running on. Then it saves the eprom parameters that holds the + * command line, memory size etc... + * + * Inputs : + * argc - nothing + * argv - holds a pointer to the eprom parameters + * envp - nothing + */ + +void SetUpBootInfo(int argc, char **argv, char **envp) +{ + mips_machgroup = MACH_GROUP_GALILEO; + mips_machtype = MACH_EV64120A; +} + +void __init prom_init(int a, char **b, char **c, int *d) +{ + mips_machgroup = MACH_GROUP_GALILEO; + add_memory_region(0, 32 << 20, BOOT_MEM_RAM); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev96100/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,174 @@ +/* + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/generic/generic.c + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + + +/* Environment variable */ + +typedef struct { + char *name; + char *val; +} t_env_var; + +int prom_argc; +char **prom_argv, **prom_envp; +char arcs_cmdline[CL_SIZE]; + +int init_debug = 0; + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +void prom_free_prom_memory (void) +{ +} + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while(actr < prom_argc) { + strcpy(cp, prom_argv[actr]); + cp += strlen(prom_argv[actr]); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ + --cp; + *cp = '\0'; +} + +char *prom_getenv(char *envname) +{ + /* + * Return a pointer to the given environment variable. + */ + + t_env_var *env = (t_env_var *) prom_envp; + int i; + + i = strlen(envname); + + while (env->name) { + if (strncmp(envname, env->name, i) == 0) { + return (env->val); + } + env++; + } + return (NULL); +} + +static inline unsigned char str2hexnum(unsigned char c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + return 0; /* foo */ +} + +static inline void str2eaddr(unsigned char *ea, unsigned char *str) +{ + int i; + + for (i = 0; i < 6; i++) { + unsigned char num; + + if ((*str == '.') || (*str == ':')) + str++; + num = str2hexnum(*str++) << 4; + num |= (str2hexnum(*str++)); + ea[i] = num; + } +} + +int get_ethernet_addr(char *ethernet_addr) +{ + char *ethaddr_str; + + ethaddr_str = prom_getenv("ethaddr"); + if (!ethaddr_str) { + printk("ethaddr not set in boot prom\n"); + return -1; + } + str2eaddr(ethernet_addr, ethaddr_str); + + if (init_debug > 1) { + int i; + printk("get_ethernet_addr: "); + for (i = 0; i < 5; i++) + printk("%02x:", + (unsigned char) *(ethernet_addr + i)); + printk("%02x\n", *(ethernet_addr + i)); + } + + return 0; +} + +const char *get_system_type(void) +{ + return "Galileo EV96100"; +} + +void __init prom_init(int argc, char **argv, char **envp, int *prom_vec) +{ + volatile unsigned char *uart; + char ppbuf[8]; + + prom_argc = argc; + prom_argv = argv; + prom_envp = envp; + + mips_machgroup = MACH_GROUP_GALILEO; + mips_machtype = MACH_EV96100; + + prom_init_cmdline(); + + /* 32 MB upgradable */ + add_memory_region(0, 32 << 20, BOOT_MEM_RAM); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev96100/int-handler.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,32 @@ +#include +#include +#include +#include + + .set noat + .align 5 + +NESTED(ev96100IRQ, PT_SIZE, sp) + SAVE_ALL + CLI # Important: mark KERNEL mode ! + + mfc0 t0, CP0_CAUSE # get pending interrupts + mfc0 t1, CP0_STATUS # get enabled interrupts + and t0, t1 # isolate allowed ones + + # FIX ME add R7000 extensions + andi t0,0xff00 # isolate pending bits + andi a0, t0, CAUSEF_IP7 + beq a0, zero, 1f + move a0, sp + jal mips_timer_interrupt + j ret_from_irq + +1: beqz t0, 3f # spurious interrupt + move a0, t0 + move a1, sp # delay slot + jal ev96100_cpu_irq + j ret_from_irq + +3: j spurious_interrupt + END(ev96100IRQ) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev96100/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,133 @@ +/* + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/atlas/atlas_int.c. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +extern void mips_timer_interrupt(int irq, struct pt_regs *regs); +extern asmlinkage void ev96100IRQ(void); + +static void disable_ev96100_irq(unsigned int irq_nr) +{ + unsigned long flags; + + local_irq_save(flags); + clear_c0_status(0x100 << irq_nr); + local_irq_restore(flags); +} + +static inline void enable_ev96100_irq(unsigned int irq_nr) +{ + unsigned long flags; + + local_irq_save(flags); + set_c0_status(0x100 << irq_nr); + local_irq_restore(flags); +} + +static unsigned int startup_ev96100_irq(unsigned int irq) +{ + enable_ev96100_irq(irq); + + return 0; /* never anything pending */ +} + +#define shutdown_ev96100_irq disable_ev96100_irq +#define mask_and_ack_ev96100_irq disable_ev96100_irq + +static void end_ev96100_irq (unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_ev96100_irq(irq); +} + +static inline unsigned int ffz8(unsigned int word) +{ + unsigned long k; + + k = 7; + if (word & 0x0fUL) { k -= 4; word <<= 4; } + if (word & 0x30UL) { k -= 2; word <<= 2; } + if (word & 0x40UL) { k -= 1; } + + return k; +} + +asmlinkage void ev96100_cpu_irq(unsigned long cause, struct pt_regs * regs) +{ + if (!(cause & 0xff00)) + return; + + do_IRQ(ffz8((cause >> 8) & 0xff), regs); +} + +static struct hw_interrupt_type ev96100_irq_type = { + "EV96100", + startup_ev96100_irq, + shutdown_ev96100_irq, + enable_ev96100_irq, + disable_ev96100_irq, + mask_and_ack_ev96100_irq, + end_ev96100_irq +}; + +void __init init_IRQ(void) +{ + int i; + + set_except_vector(0, ev96100IRQ); + init_generic_irq(); + + for (i = 0; i < 8; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &ev96100_irq_type; + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev96100/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,11 @@ +# +# Copyright 2000 MontaVista Software Inc. +# Author: MontaVista Software, Inc. +# ppopov@mvista.com or source@mvista.com +# +# Makefile for the Galileo EV96100 board. +# + +obj-y += init.o time.o irq.o int-handler.o setup.o puts.o + +EXTRA_AFLAGS := $(CFLAGS) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev96100/puts.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,144 @@ + +/* + * Debug routines which directly access the uart. + */ + +#include +#include + + +//#define SERIAL_BASE EV96100_UART0_REGS_BASE +#define SERIAL_BASE 0xBD000020 +#define NS16550_BASE SERIAL_BASE + +#define SERA_CMD 0x0D +#define SERA_DATA 0x08 +//#define SERB_CMD 0x05 +#define SERB_CMD 20 +#define SERB_DATA 0x00 +#define TX_BUSY 0x20 + +#define TIMEOUT 0xffff +#undef SLOW_DOWN + +static const char digits[16] = "0123456789abcdef"; +static volatile unsigned char * const com1 = (unsigned char *)SERIAL_BASE; + + +#ifdef SLOW_DOWN +static inline void slow_down() +{ + int k; + for (k=0; k<10000; k++); +} +#else +#define slow_down() +#endif + +void +putch(const unsigned char c) +{ + unsigned char ch; + int i = 0; + + do { + ch = com1[SERB_CMD]; + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (0 == (ch & TX_BUSY)); + com1[SERB_DATA] = c; +} + +void +putchar(const unsigned char c) +{ + unsigned char ch; + int i = 0; + + do { + ch = com1[SERB_CMD]; + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (0 == (ch & TX_BUSY)); + com1[SERB_DATA] = c; +} + +void +puts(unsigned char *cp) +{ + unsigned char ch; + int i = 0; + + while (*cp) { + do { + ch = com1[SERB_CMD]; + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (0 == (ch & TX_BUSY)); + com1[SERB_DATA] = *cp++; + } + putch('\r'); + putch('\n'); +} + +void +fputs(unsigned char *cp) +{ + unsigned char ch; + int i = 0; + + while (*cp) { + + do { + ch = com1[SERB_CMD]; + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (0 == (ch & TX_BUSY)); + com1[SERB_DATA] = *cp++; + } +} + + +void +put64(uint64_t ul) +{ + int cnt; + unsigned ch; + + cnt = 16; /* 16 nibbles in a 64 bit long */ + putch('0'); + putch('x'); + do { + cnt--; + ch = (unsigned char)(ul >> cnt * 4) & 0x0F; + putch(digits[ch]); + } while (cnt > 0); +} + +void +put32(unsigned u) +{ + int cnt; + unsigned ch; + + cnt = 8; /* 8 nibbles in a 32 bit long */ + putch('0'); + putch('x'); + do { + cnt--; + ch = (unsigned char)(u >> cnt * 4) & 0x0F; + putch(digits[ch]); + } while (cnt > 0); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev96100/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,206 @@ +/* + * BRIEF MODULE DESCRIPTION + * Galileo EV96100 setup. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/atlas/atlas_setup.c. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE) +extern void console_setup(char *, int *); +char serial_console[20]; +#endif + +extern char * __init prom_getcmdline(void); + +extern void mips_reboot_setup(void); +extern struct rtc_ops no_rtc_ops; +extern struct resource ioport_resource; + +unsigned char mac_0_1[12]; + +void __init ev96100_setup(void) +{ + unsigned long config = read_c0_config(); + unsigned long status = read_c0_status(); + unsigned long info = read_c0_info(); + u32 tmp; + + char *argptr; + + clear_c0_status(ST0_FR); + + if (config & 0x8) { + printk("Secondary cache is enabled\n"); + } + else { + printk("Secondary cache is disabled\n"); + } + + if (status & (1<<27)) { + printk("User-mode cache ops enabled\n"); + } + else { + printk("User-mode cache ops disabled\n"); + } + + printk("CP0 info reg: %x\n", (unsigned)info); + if (info & (1<<28)) { + printk("burst mode Scache RAMS\n"); + } + else { + printk("pipelined Scache RAMS\n"); + } + + if ((info & (0x3<<26)) >> 26 == 0) { + printk("67 percent drive strength\n"); + } + else if ((info & (0x3<<26)) >> 26 == 1) { + printk("50 percent drive strength\n"); + } + else if ((info & (0x3<<26)) >> 26 == 2) { + printk("100 percent drive strength\n"); + } + else if ((info & (0x3<<26)) >> 26 == 3) { + printk("83 percent drive strength\n"); + } + + + if ((info & (0x3<<23)) >> 23 == 0) { + printk("Write Protocol: R4000 compatible\n"); + } + else if ((info & (0x3<<23)) >> 23 == 1) { + printk("Write Protocol: Reserved\n"); + } + else if ((info & (0x3<<23)) >> 23 == 2) { + printk("Write Protocol: Pipelined\n"); + } + else if ((info & (0x3<<23)) >> 23 == 3) { + printk("Write Protocol: Write re-issue\n"); + } + + if (info & 0x1) { + printk("Atomic Enable is set\n"); + } + + argptr = prom_getcmdline(); +#ifdef CONFIG_SERIAL_CONSOLE + if (strstr(argptr, "console=") == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " console=ttyS0,115200"); + } +#endif + + rtc_ops = &no_rtc_ops; + mips_reboot_setup(); + set_io_port_base(KSEG1); + ioport_resource.start = GT_PCI_IO_BASE; + ioport_resource.end = GT_PCI_IO_BASE + 0x01ffffff; + +#ifdef CONFIG_BLK_DEV_INITRD + ROOT_DEV = Root_RAM0; +#endif + + + /* + * setup gt controller master bit so we can do config cycles + */ + + /* Clear cause register bits */ + GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | + GT_INTRCAUSE_TARABORT0_BIT)); + /* Setup address */ + GT_WRITE(GT_PCI0_CFGADDR_OFS, + (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | + (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | + ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | + GT_PCI0_CFGADDR_CONFIGEN_BIT); + + udelay(2); + tmp = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS)); + + tmp |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SERR); + GT_WRITE(GT_PCI0_CFGADDR_OFS, + (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | + (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | + ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | + GT_PCI0_CFGADDR_CONFIGEN_BIT); + udelay(2); + *(volatile u32 *)(MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS) = cpu_to_le32(tmp); + + /* Setup address */ + GT_WRITE(GT_PCI0_CFGADDR_OFS, + (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | + (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | + ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | + GT_PCI0_CFGADDR_CONFIGEN_BIT); + + udelay(2); + tmp = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS)); +} + +unsigned short get_gt_devid(void) +{ + u32 gt_devid; + + /* Figure out if this is a gt96100 or gt96100A */ + GT_WRITE(GT_PCI0_CFGADDR_OFS, + (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | + (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | + ((PCI_VENDOR_ID / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | + GT_PCI0_CFGADDR_CONFIGEN_BIT); + + udelay(4); + gt_devid = le32_to_cpu(*(volatile u32 *) + (MIPS_GT_BASE+GT_PCI0_CFGDATA_OFS)); + return (unsigned short)(gt_devid>>16); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/ev96100/time.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,276 @@ +/* + * BRIEF MODULE DESCRIPTION + * Galileo EV96100 rtc routines. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/atlas/atlas_rtc.c. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include + +#include +#include + +#include + + +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) + +extern volatile unsigned long wall_jiffies; +unsigned long missed_heart_beats = 0; + +static unsigned long r4k_offset; /* Amount to increment compare reg each time */ +static unsigned long r4k_cur; /* What counter should be at next timer irq */ + +static inline void ack_r4ktimer(unsigned long newval) +{ + write_c0_compare(newval); +} + +static int set_rtc_mmss(unsigned long nowtime) +{ + /* EV96100 does not have a real time clock */ + int retval = 0; + + return retval; +} + + + +/* + * Figure out the r4k offset, the amount to increment the compare + * register for each time tick. + * Use the RTC to calculate offset. + */ +static unsigned long __init cal_r4koff(void) +{ + unsigned long count; + count = 300000000/2; + return (count / HZ); +} + + +static unsigned long __init get_mips_time(void) +{ + unsigned int year, mon, day, hour, min, sec; + + year = 2000; + mon = 10; + day = 31; + hour = 0; + min = 0; + sec = 0; + return mktime(year, mon, day, hour, min, sec); +} + + +/* + * called from start_kernel() + */ +void __init time_init(void) +{ + + unsigned int est_freq; + + r4k_offset = cal_r4koff(); + + est_freq = 2*r4k_offset*HZ; + est_freq += 5000; /* round */ + est_freq -= est_freq%10000; + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, + (est_freq%1000000)*100/1000000); + r4k_cur = (read_c0_count() + r4k_offset); + + write_c0_compare(r4k_cur); + + change_c0_status(ST0_IM, IE_IRQ5); /* FIX ME */ +} + +/* This is for machines which generate the exact clock. */ +#define USECS_PER_JIFFY (1000000/HZ) + +/* Cycle counter value at the previous timer interrupt.. */ + +static unsigned int timerhi = 0, timerlo = 0; + +/* + * FIXME: Does playing with the RP bit in c0_status interfere with this code? + */ +static unsigned long do_fast_gettimeoffset(void) +{ + u32 count; + unsigned long res, tmp; + + /* Last jiffy when do_fast_gettimeoffset() was called. */ + static unsigned long last_jiffies=0; + unsigned long quotient; + + /* + * Cached "1/(clocks per usec)*2^32" value. + * It has to be recalculated once each jiffy. + */ + static unsigned long cached_quotient=0; + + tmp = jiffies; + + quotient = cached_quotient; + + if (tmp && last_jiffies != tmp) { + last_jiffies = tmp; + __asm__(".set\tnoreorder\n\t" + ".set\tnoat\n\t" + ".set\tmips3\n\t" + "lwu\t%0,%2\n\t" + "dsll32\t$1,%1,0\n\t" + "or\t$1,$1,%0\n\t" + "ddivu\t$0,$1,%3\n\t" + "mflo\t$1\n\t" + "dsll32\t%0,%4,0\n\t" + "nop\n\t" + "ddivu\t$0,%0,$1\n\t" + "mflo\t%0\n\t" + ".set\tmips0\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=&r" (quotient) + :"r" (timerhi), + "m" (timerlo), + "r" (tmp), + "r" (USECS_PER_JIFFY)); + cached_quotient = quotient; + } + + /* Get last timer tick in absolute kernel time */ + count = read_c0_count(); + + /* .. relative to previous jiffy (32 bits is enough) */ + count -= timerlo; + + __asm__("multu\t%1,%2\n\t" + "mfhi\t%0" + :"=r" (res) + :"r" (count), + "r" (quotient)); + + /* + * Due to possible jiffies inconsistencies, we need to check + * the result so that we'll get a timer that is monotonic. + */ + if (res >= USECS_PER_JIFFY) + res = USECS_PER_JIFFY-1; + + return res; +} + +/* + * This version of gettimeofday has microsecond resolution + * and better than microsecond precision on fast x86 machines with TSC. + */ +void do_gettimeofday(struct timeval *tv) +{ + unsigned long seq; + unsigned long usec, sec; + + do { + seq = read_seqbegin(&xtime_lock); + + usec = do_gettimeoffset(); + { + unsigned long lost = jiffies - wall_jiffies; + if (lost) + usec += lost * (1000000 / HZ); + } + sec = xtime.tv_sec; + usec += (xtime.tv_nsec / 1000); + } while (read_seqretry(&xtime_lock, seq)); + + while (usec >= 1000000) { + usec -= 1000000; + sec++; + } + + tv->tv_sec = sec; + tv->tv_usec = usec; +} + +void do_settimeofday(struct timeval *tv) +{ + write_seqlock_irq(&xtime_lock); + /* + * This is revolting. We need to set "xtime" correctly. However, the + * value in this location is the value at the most recent update of + * wall time. Discover what correction gettimeofday() would have + * made, and then undo it! + */ + tv->tv_usec -= do_gettimeoffset(); + tv->tv_usec -= (jiffies - wall_jiffies) * (1000000 / HZ); + + while (tv->tv_usec < 0) { + tv->tv_usec += 1000000; + tv->tv_sec--; + } + + xtime.tv_sec = tv->tv_sec; + xtime.tv_nsec = (tv->tv_usec * 1000); + time_adjust = 0; /* stop active adjtime() */ + time_status |= STA_UNSYNC; + time_maxerror = NTP_PHASE_LIMIT; + time_esterror = NTP_PHASE_LIMIT; + write_sequnlock_irq(&xtime_lock); +} + +/* + * There are a lot of conceptually broken versions of the MIPS timer interrupt + * handler floating around. This one is rather different, but the algorithm + * is probably more robust. + */ +void mips_timer_interrupt(struct pt_regs *regs) +{ + int irq = 7; /* FIX ME */ + + if (r4k_offset == 0) { + goto null; + } + + do { + kstat_cpu(0).irqs[irq]++; + do_timer(regs); + r4k_cur += r4k_offset; + ack_r4ktimer(r4k_cur); + + } while (((unsigned long)read_c0_count() + - r4k_cur) < 0x7fffffff); + return; + +null: + ack_r4ktimer(0); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/generic/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,25 @@ +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. +# +# ######################################################################## +# +# This program is free software; you can distribute it and/or modify it +# under the terms of the GNU General Public License (Version 2) as +# published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. +# +# ####################################################################### +# +# Makefile for the MIPS boards generic routines under Linux. +# + +obj-y := reset.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/galileo-boards/generic/reset.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,72 @@ +/* + * BRIEF MODULE DESCRIPTION + * Galileo EV96100 reset routines. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/generic/reset.c + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static void mips_machine_restart(char *command); +static void mips_machine_halt(void); + +static void mips_machine_restart(char *command) +{ + set_c0_status(ST0_BEV | ST0_ERL); + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + flush_cache_all(); + write_c0_wired(0); + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); + while (1); +} + +static void mips_machine_halt(void) +{ + printk(KERN_NOTICE "You can safely turn off the power\n"); + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void mips_reboot_setup(void) +{ + _machine_restart = mips_machine_restart; + _machine_halt = mips_machine_halt; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/jmr3927/common/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,5 @@ +# +# Makefile for the common code of TOSHIBA JMR-TX3927 board +# + +obj-y += prom.o puts.o rtc_ds1742.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/jmr3927/common/prom.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,88 @@ +/* + * BRIEF MODULE DESCRIPTION + * PROM library initialisation code, assuming a version of + * pmon is the boot code. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * Based on arch/mips/au1000/common/prom.c + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/xx files. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include + +#include + +/* #define DEBUG_CMDLINE */ + +char arcs_cmdline[CL_SIZE]; +extern int prom_argc; +extern char **prom_argv, **prom_envp; + +typedef struct +{ + char *name; +/* char *val; */ +}t_env_var; + + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while(actr < prom_argc) { + strcpy(cp, prom_argv[actr]); + cp += strlen(prom_argv[actr]); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ + --cp; + *cp = '\0'; +} + +int __init page_is_ram(unsigned long pagenr) +{ + return 1; +} + +void prom_free_prom_memory (void) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/jmr3927/common/puts.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,168 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Low level uart routines to directly access a TX[34]927 SIO. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com or source@mvista.com + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * Based on arch/mips/au1000/common/puts.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +#define TIMEOUT 0xffffff +#define SLOW_DOWN + +static const char digits[16] = "0123456789abcdef"; + +#ifdef SLOW_DOWN +#define slow_down() { int k; for (k=0; k<10000; k++); } +#else +#define slow_down() +#endif + +void +putch(const unsigned char c) +{ + int i = 0; + + do { + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS)); + tx3927_sioptr(1)->tfifo = c; + return; +} + +unsigned char getch(void) +{ + int i = 0; + int dicr; + char c; + + /* diable RX int. */ + dicr = tx3927_sioptr(1)->dicr; + tx3927_sioptr(1)->dicr = 0; + + do { + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (tx3927_sioptr(1)->disr & TXx927_SIDISR_UVALID) + ; + c = tx3927_sioptr(1)->rfifo; + + /* clear RX int. status */ + tx3927_sioptr(1)->disr &= ~TXx927_SIDISR_RDIS; + /* enable RX int. */ + tx3927_sioptr(1)->dicr = dicr; + + return c; +} +void +do_jmr3927_led_set(char n) +{ + /* and with current leds */ + jmr3927_led_and_set(n); +} + +void +puts(unsigned char *cp) +{ + int i = 0; + + while (*cp) { + do { + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS)); + tx3927_sioptr(1)->tfifo = *cp++; + } + putch('\r'); + putch('\n'); +} + +void +fputs(unsigned char *cp) +{ + int i = 0; + + while (*cp) { + do { + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS)); + tx3927_sioptr(1)->tfifo = *cp++; + } +} + + +void +put64(uint64_t ul) +{ + int cnt; + unsigned ch; + + cnt = 16; /* 16 nibbles in a 64 bit long */ + putch('0'); + putch('x'); + do { + cnt--; + ch = (unsigned char)(ul >> cnt * 4) & 0x0F; + putch(digits[ch]); + } while (cnt > 0); +} + +void +put32(unsigned u) +{ + int cnt; + unsigned ch; + + cnt = 8; /* 8 nibbles in a 32 bit long */ + putch('0'); + putch('x'); + do { + cnt--; + ch = (unsigned char)(u >> cnt * 4) & 0x0F; + putch(digits[ch]); + } while (cnt > 0); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/jmr3927/common/rtc_ds1742.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,165 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * arch/mips/jmr3927/common/rtc_ds1742.c + * Based on arch/mips/ddb5xxx/common/rtc_ds1386.c + * low-level RTC hookups for s for Dallas 1742 chip. + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + +/* + * This file exports a function, rtc_ds1386_init(), which expects an + * uncached base address as the argument. It will set the two function + * pointers expected by the MIPS generic timer code. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#define EPOCH 2000 + +static unsigned long rtc_base; + +static unsigned long +rtc_ds1742_get_time(void) +{ + unsigned int year, month, day, hour, minute, second; + unsigned int century; + + CMOS_WRITE(RTC_READ, RTC_CONTROL); + second = BCD2BIN(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK); + minute = BCD2BIN(CMOS_READ(RTC_MINUTES)); + hour = BCD2BIN(CMOS_READ(RTC_HOURS)); + day = BCD2BIN(CMOS_READ(RTC_DATE)); + month = BCD2BIN(CMOS_READ(RTC_MONTH)); + year = BCD2BIN(CMOS_READ(RTC_YEAR)); + century = BCD2BIN(CMOS_READ(RTC_CENTURY) & RTC_CENTURY_MASK); + CMOS_WRITE(0, RTC_CONTROL); + + year += century * 100; + + return mktime(year, month, day, hour, minute, second); +} +extern void to_tm(unsigned long tim, struct rtc_time * tm); + +static int +rtc_ds1742_set_time(unsigned long t) +{ + struct rtc_time tm; + u8 year, month, day, hour, minute, second; + u8 cmos_year, cmos_month, cmos_day, cmos_hour, cmos_minute, cmos_second; + int cmos_century; + + CMOS_WRITE(RTC_READ, RTC_CONTROL); + cmos_second = (u8)(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK); + cmos_minute = (u8)CMOS_READ(RTC_MINUTES); + cmos_hour = (u8)CMOS_READ(RTC_HOURS); + cmos_day = (u8)CMOS_READ(RTC_DATE); + cmos_month = (u8)CMOS_READ(RTC_MONTH); + cmos_year = (u8)CMOS_READ(RTC_YEAR); + cmos_century = CMOS_READ(RTC_CENTURY) & RTC_CENTURY_MASK; + + CMOS_WRITE(RTC_WRITE, RTC_CONTROL); + + /* convert */ + to_tm(t, &tm); + + /* check each field one by one */ + year = BIN2BCD(tm.tm_year - EPOCH); + if (year != cmos_year) { + CMOS_WRITE(year,RTC_YEAR); + } + + month = BIN2BCD(tm.tm_mon); + if (month != (cmos_month & 0x1f)) { + CMOS_WRITE((month & 0x1f) | (cmos_month & ~0x1f),RTC_MONTH); + } + + day = BIN2BCD(tm.tm_mday); + if (day != cmos_day) { + + CMOS_WRITE(day, RTC_DATE); + } + + if (cmos_hour & 0x40) { + /* 12 hour format */ + hour = 0x40; + if (tm.tm_hour > 12) { + hour |= 0x20 | (BIN2BCD(hour-12) & 0x1f); + } else { + hour |= BIN2BCD(tm.tm_hour); + } + } else { + /* 24 hour format */ + hour = BIN2BCD(tm.tm_hour) & 0x3f; + } + if (hour != cmos_hour) CMOS_WRITE(hour, RTC_HOURS); + + minute = BIN2BCD(tm.tm_min); + if (minute != cmos_minute) { + CMOS_WRITE(minute, RTC_MINUTES); + } + + second = BIN2BCD(tm.tm_sec); + if (second != cmos_second) { + CMOS_WRITE(second & RTC_SECONDS_MASK,RTC_SECONDS); + } + + /* RTC_CENTURY and RTC_CONTROL share same address... */ + CMOS_WRITE(cmos_century, RTC_CONTROL); + + return 0; +} + +void +rtc_ds1742_init(unsigned long base) +{ + u8 cmos_second; + + /* remember the base */ + rtc_base = base; + db_assert((rtc_base & 0xe0000000) == KSEG1); + + /* set the function pointers */ + rtc_get_time = rtc_ds1742_get_time; + rtc_set_time = rtc_ds1742_set_time; + + /* clear oscillator stop bit */ + CMOS_WRITE(RTC_READ, RTC_CONTROL); + cmos_second = (u8)(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK); + CMOS_WRITE(RTC_WRITE, RTC_CONTROL); + CMOS_WRITE(cmos_second, RTC_SECONDS); /* clear msb */ + CMOS_WRITE(0, RTC_CONTROL); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/jmr3927/rbhma3100/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,80 @@ +/*********************************************************************** + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * arch/mips/jmr3927/common/init.c + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + *********************************************************************** + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +int prom_argc; +char **prom_argv, **prom_envp; +extern void __init prom_init_cmdline(void); +extern char *prom_getenv(char *envname); +unsigned long mips_nofpu = 0; + +const char *get_system_type(void) +{ + return "Toshiba" +#ifdef CONFIG_TOSHIBA_JMR3927 + " JMR_TX3927" +#endif + ; +} + +extern void puts(unsigned char *cp); +int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) +{ +#ifdef CONFIG_TOSHIBA_JMR3927 + /* CCFG */ + if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) + puts("Warning: TX3927 TLB off\n"); +#endif + prom_argc = argc; + prom_argv = argv; + prom_envp = envp; + + mips_machgroup = MACH_GROUP_TOSHIBA; + +#ifdef CONFIG_TOSHIBA_JMR3927 + mips_machtype = MACH_TOSHIBA_JMR3927; +#endif + + prom_init_cmdline(); + add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); + return 0; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/jmr3927/rbhma3100/int-handler.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,74 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * Based on arch/mips/tsdb/kernel/int-handler.S + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + + /* A lot of complication here is taken away because: + * + * 1) We handle one interrupt and return, sitting in a loop + * and moving across all the pending IRQ bits in the cause + * register is _NOT_ the answer, the common case is one + * pending IRQ so optimize in that direction. + * + * 2) We need not check against bits in the status register + * IRQ mask, that would make this routine slow as hell. + * + * 3) Linux only thinks in terms of all IRQs on or all IRQs + * off, nothing in between like BSD spl() brain-damage. + * + */ + +/* Flush write buffer (needed?) + * NOTE: TX39xx performs "non-blocking load", so explicitly use the target + * register of LBU to flush immediately. + */ +#define FLUSH_WB(tmp) \ + la tmp, JMR3927_IOC_REV_ADDR; \ + lbu tmp, (tmp); \ + move tmp, zero; + + .text + .set noreorder + .set noat + .align 5 + NESTED(jmr3927_IRQ, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + jal jmr3927_irc_irqdispatch + move a0, sp + FLUSH_WB(t0) + j ret_from_irq + nop + END(jmr3927_IRQ) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/jmr3927/rbhma3100/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,514 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#if JMR3927_IRQ_END > NR_IRQS +#error JMR3927_IRQ_END > NR_IRQS +#endif + +struct tb_irq_space* tb_irq_spaces; + +unsigned int local_bh_count[NR_CPUS]; +unsigned int local_irq_count[NR_CPUS]; + +static int jmr3927_irq_base=-1; + +#ifdef CONFIG_PCI +static int jmr3927_gen_iack(void) +{ + /* generate ACK cycle */ +#ifdef __BIG_ENDIAN + return (tx3927_pcicptr->iiadp >> 24) & 0xff; +#else + return tx3927_pcicptr->iiadp & 0xff; +#endif +} +#endif + +extern asmlinkage void jmr3927_IRQ(void); + +#define irc_dlevel 0 +#define irc_elevel 1 +static unsigned char irc_level[TX3927_NUM_IR] = { + 5, 5, 5, 5, 5, 5, /* INT[5:0] */ + 7, 7, /* SIO */ + 5, 5, 5, 0, 0, /* DMA, PIO, PCI */ + 6, 6, 6 /* TMR */ +}; + +static inline void mask_irq(unsigned int irq_nr) +{ + struct tb_irq_space* sp; + for (sp = tb_irq_spaces; sp; sp = sp->next) { + if (sp->start_irqno <= irq_nr && + irq_nr < sp->start_irqno + sp->nr_irqs) { + if (sp->mask_func) + sp->mask_func(irq_nr - sp->start_irqno, + sp->space_id); + break; + } + } +} + +static inline void unmask_irq(unsigned int irq_nr) +{ + struct tb_irq_space* sp; + for (sp = tb_irq_spaces; sp; sp = sp->next) { + if (sp->start_irqno <= irq_nr && + irq_nr < sp->start_irqno + sp->nr_irqs) { + if (sp->unmask_func) + sp->unmask_func(irq_nr - sp->start_irqno, + sp->space_id); + break; + } + } +} + +static void jmr3927_irq_disable(unsigned int irq_nr); +static void jmr3927_irq_enable(unsigned int irq_nr); + +static unsigned int jmr3927_irq_startup(unsigned int irq) +{ + jmr3927_irq_enable(irq); + return 0; +} + +#define jmr3927_irq_shutdown jmr3927_irq_disable + +static void jmr3927_irq_ack(unsigned int irq) +{ + db_assert(jmr3927_irq_base != -1); + db_assert(irq >= jmr3927_irq_base); + db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC); + + if (irq == JMR3927_IRQ_IRC_TMR0) { + jmr3927_tmrptr->tisr = 0; /* ack interrupt */ + } + + jmr3927_irq_disable(irq); +} + +static void jmr3927_irq_end(unsigned int irq) +{ + db_assert(jmr3927_irq_base != -1); + db_assert(irq >= jmr3927_irq_base); + db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC); + + jmr3927_irq_enable(irq); +} + +static void jmr3927_irq_disable(unsigned int irq_nr) +{ + unsigned long flags; + + db_assert(jmr3927_irq_base != -1); + db_assert(irq >= jmr3927_irq_base); + db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC); + + local_irq_save(flags); + mask_irq(irq_nr); + local_irq_restore(flags); +} + +static void jmr3927_irq_enable(unsigned int irq_nr) +{ + unsigned long flags; + + db_assert(jmr3927_irq_base != -1); + db_assert(irq >= jmr3927_irq_base); + db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC); + + local_irq_save(flags); + unmask_irq(irq_nr); + local_irq_restore(flags); +} + +/* + * CP0_STATUS is a thread's resource (saved/restored on context switch). + * So disable_irq/enable_irq MUST handle IOC/ISAC/IRC registers. + */ +static void mask_irq_isac(int irq_nr, int space_id) +{ + /* 0: mask */ + unsigned char imask = + jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR); + unsigned int bit = 1 << irq_nr; + jmr3927_isac_reg_out(imask & ~bit, JMR3927_ISAC_INTM_ADDR); + /* flush write buffer */ + (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); +} +static void unmask_irq_isac(int irq_nr, int space_id) +{ + /* 0: mask */ + unsigned char imask = + jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR); + unsigned int bit = 1 << irq_nr; + jmr3927_isac_reg_out(imask | bit, JMR3927_ISAC_INTM_ADDR); + /* flush write buffer */ + (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); +} + +static void mask_irq_ioc(int irq_nr, int space_id) +{ + /* 0: mask */ + unsigned char imask = + jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); + unsigned int bit = 1 << irq_nr; + jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR); + /* flush write buffer */ + (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); +} +static void unmask_irq_ioc(int irq_nr, int space_id) +{ + /* 0: mask */ + unsigned char imask = + jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR); + unsigned int bit = 1 << irq_nr; + jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR); + /* flush write buffer */ + (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR); +} + +static void mask_irq_irc(int irq_nr, int space_id) +{ + volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2]; + if (irq_nr & 1) + *ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8); + else + *ilrp = (*ilrp & 0xff00) | irc_dlevel; + /* update IRCSR */ + tx3927_ircptr->imr = 0; + tx3927_ircptr->imr = irc_elevel; +} +static void unmask_irq_irc(int irq_nr, int space_id) +{ + volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2]; + if (irq_nr & 1) + *ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8); + else + *ilrp = (*ilrp & 0xff00) | irc_level[irq_nr]; + /* update IRCSR */ + tx3927_ircptr->imr = 0; + tx3927_ircptr->imr = irc_elevel; +} + +struct tb_irq_space jmr3927_isac_irqspace = { + .next = NULL, + .start_irqno = JMR3927_IRQ_ISAC, + nr_irqs : JMR3927_NR_IRQ_ISAC, + .mask_func = mask_irq_isac, + .unmask_func = unmask_irq_isac, + .name = "ISAC", + .space_id = 0, + can_share : 0 +}; +struct tb_irq_space jmr3927_ioc_irqspace = { + .next = NULL, + .start_irqno = JMR3927_IRQ_IOC, + nr_irqs : JMR3927_NR_IRQ_IOC, + .mask_func = mask_irq_ioc, + .unmask_func = unmask_irq_ioc, + .name = "IOC", + .space_id = 0, + can_share : 1 +}; +struct tb_irq_space jmr3927_irc_irqspace = { + .next = NULL, + .start_irqno = JMR3927_IRQ_IRC, + nr_irqs : JMR3927_NR_IRQ_IRC, + .mask_func = mask_irq_irc, + .unmask_func = unmask_irq_irc, + .name = "on-chip", + .space_id = 0, + can_share : 0 +}; + +void jmr3927_spurious(struct pt_regs *regs) +{ +#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND + tx_branch_likely_bug_fixup(regs); +#endif + printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n", + regs->cp0_cause, regs->cp0_epc, regs->regs[31]); +} + +void jmr3927_irc_irqdispatch(struct pt_regs *regs) +{ + int irq; + +#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND + tx_branch_likely_bug_fixup(regs); +#endif + if ((regs->cp0_cause & CAUSEF_IP7) == 0) { +#if 0 + jmr3927_spurious(regs); +#endif + return; + } + irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f; + + do_IRQ(irq + JMR3927_IRQ_IRC, regs); +} + +static void jmr3927_ioc_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR); + int i; + + for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) { + if (istat & (1 << i)) { + irq = JMR3927_IRQ_IOC + i; + do_IRQ(irq, regs); + } + } +} + +static struct irqaction ioc_action = { + jmr3927_ioc_interrupt, 0, 0, "IOC", NULL, NULL, +}; + +static void jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR); + int i; + + for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) { + if (istat & (1 << i)) { + irq = JMR3927_IRQ_ISAC + i; + do_IRQ(irq, regs); + } + } +} + +static struct irqaction isac_action = { + jmr3927_isac_interrupt, 0, 0, "ISAC", NULL, NULL, +}; + + +static void jmr3927_isaerr_interrupt(int irq, void * dev_id, struct pt_regs * regs) +{ + printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq); +} +static struct irqaction isaerr_action = { + jmr3927_isaerr_interrupt, 0, 0, "ISA error", NULL, NULL, +}; + +static void jmr3927_pcierr_interrupt(int irq, void * dev_id, struct pt_regs * regs) +{ + printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); + printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", + tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat); +} +static struct irqaction pcierr_action = { + jmr3927_pcierr_interrupt, 0, 0, "PCI error", NULL, NULL, +}; + +int jmr3927_ether1_irq = 0; + +void jmr3927_irq_init(u32 irq_base); +void jmr3927_irq_setup(void) +{ + /* look for io board's presence */ + int have_isac = jmr3927_have_isac(); + + /* Now, interrupt control disabled, */ + /* all IRC interrupts are masked, */ + /* all IRC interrupt mode are Low Active. */ + + if (have_isac) { + + /* ETHER1 (NE2000 compatible 10M-Ether) parameter setup */ + /* temporary enable interrupt control */ + tx3927_ircptr->cer = 1; + /* ETHER1 Int. Is High-Active. */ + if (tx3927_ircptr->ssr & (1 << 0)) + jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT0; +#if 0 /* INT3 may be asserted by ether0 (even after reboot...) */ + else if (tx3927_ircptr->ssr & (1 << 3)) + jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT3; +#endif + /* disable interrupt control */ + tx3927_ircptr->cer = 0; + + /* Ether1: High Active */ + if (jmr3927_ether1_irq) { + int ether1_irc = jmr3927_ether1_irq - JMR3927_IRQ_IRC; + tx3927_ircptr->cr[ether1_irc / 8] |= + TX3927_IRCR_HIGH << ((ether1_irc % 8) * 2); + } + } + + /* mask all IOC interrupts */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR); + /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */ + jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR); + + if (have_isac) { + /* mask all ISAC interrupts */ + jmr3927_isac_reg_out(0, JMR3927_ISAC_INTM_ADDR); + /* setup ISAC interrupt mode (ISAIRQ3,ISAIRQ5:Low Active ???) */ + jmr3927_isac_reg_out(JMR3927_ISAC_INTF_IRQ3|JMR3927_ISAC_INTF_IRQ5, JMR3927_ISAC_INTP_ADDR); + } + + /* clear PCI Soft interrupts */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR); + /* clear PCI Reset interrupts */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + + /* enable interrupt control */ + tx3927_ircptr->cer = TX3927_IRCER_ICE; + tx3927_ircptr->imr = irc_elevel; + + jmr3927_irq_init(NR_ISA_IRQS); + + set_except_vector(0, jmr3927_IRQ); + + /* setup irq space */ + add_tb_irq_space(&jmr3927_isac_irqspace); + add_tb_irq_space(&jmr3927_ioc_irqspace); + add_tb_irq_space(&jmr3927_irc_irqspace); + + /* setup IOC interrupt 1 (PCI, MODEM) */ + setup_irq(JMR3927_IRQ_IOCINT, &ioc_action); + + if (have_isac) { + setup_irq(JMR3927_IRQ_ISACINT, &isac_action); + setup_irq(JMR3927_IRQ_ISAC_ISAER, &isaerr_action); + } + +#ifdef CONFIG_PCI + setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action); +#endif + + /* enable all CPU interrupt bits. */ + set_c0_status(ST0_IM); /* IE bit is still 0. */ +} + +void (*irq_setup)(void); +void __init init_IRQ(void) +{ + +#ifdef CONFIG_KGDB + extern void breakpoint(void); + extern void set_debug_traps(void); + + puts("Wait for gdb client connection ...\n"); + set_debug_traps(); + breakpoint(); +#endif + + /* invoke board-specific irq setup */ + irq_setup(); +} + +hw_irq_controller jmr3927_irq_controller = { + "jmr3927_irq", + jmr3927_irq_startup, + jmr3927_irq_shutdown, + jmr3927_irq_enable, + jmr3927_irq_disable, + jmr3927_irq_ack, + jmr3927_irq_end, + NULL /* no affinity stuff for UP */ +}; + +void +jmr3927_irq_init(u32 irq_base) +{ + extern irq_desc_t irq_desc[]; + u32 i; + + for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].handler = &jmr3927_irq_controller; + } + + jmr3927_irq_base = irq_base; +} + +#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND +static int tx_branch_likely_bug_count = 0; +static int have_tx_branch_likely_bug = 0; +void tx_branch_likely_bug_fixup(struct pt_regs *regs) +{ + /* TX39/49-BUG: Under this condition, the insn in delay slot + of the branch likely insn is executed (not nullified) even + the branch condition is false. */ + if (!have_tx_branch_likely_bug) + return; + if ((regs->cp0_epc & 0xfff) == 0xffc && + KSEGX(regs->cp0_epc) != KSEG0 && + KSEGX(regs->cp0_epc) != KSEG1) { + unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4); + /* beql,bnel,blezl,bgtzl */ + /* bltzl,bgezl,blezall,bgezall */ + /* bczfl, bcztl */ + if ((insn & 0xf0000000) == 0x50000000 || + (insn & 0xfc0e0000) == 0x04020000 || + (insn & 0xf3fe0000) == 0x41020000) { + regs->cp0_epc -= 4; + tx_branch_likely_bug_count++; + printk(KERN_INFO + "fix branch-likery bug in %s (insn %08x)\n", + current->comm, insn); + } + } +} +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/jmr3927/rbhma3100/kgdb_io.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,155 @@ +/* + * BRIEF MODULE DESCRIPTION + * Low level uart routines to directly access a TX[34]927 SIO. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com or source@mvista.com + * + * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +#define TIMEOUT 0xffffff +#define SLOW_DOWN + +static const char digits[16] = "0123456789abcdef"; + +#ifdef SLOW_DOWN +#define slow_down() { int k; for (k=0; k<10000; k++); } +#else +#define slow_down() +#endif + +static int remoteDebugInitialized = 0; + +int putDebugChar(unsigned char c) +{ + int i = 0; + + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(38400); + } + + do { + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS)); + tx3927_sioptr(0)->tfifo = c; + + return 1; +} + +unsigned char getDebugChar(void) +{ + int i = 0; + int dicr; + char c; + + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(38400); + } + + /* diable RX int. */ + dicr = tx3927_sioptr(0)->dicr; + tx3927_sioptr(0)->dicr = 0; + + do { + slow_down(); + i++; + if (i>TIMEOUT) { + break; + } + } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID) + ; + c = tx3927_sioptr(0)->rfifo; + + /* clear RX int. status */ + tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS; + /* enable RX int. */ + tx3927_sioptr(0)->dicr = dicr; + + return c; +} + +void debugInit(int baud) +{ + /* + volatile unsigned long lcr; + volatile unsigned long dicr; + volatile unsigned long disr; + volatile unsigned long cisr; + volatile unsigned long fcr; + volatile unsigned long flcr; + volatile unsigned long bgr; + volatile unsigned long tfifo; + volatile unsigned long rfifo; + */ + + tx3927_sioptr(0)->lcr = 0x020; + tx3927_sioptr(0)->dicr = 0; + tx3927_sioptr(0)->disr = 0x4100; + tx3927_sioptr(0)->cisr = 0x014; + tx3927_sioptr(0)->fcr = 0; + tx3927_sioptr(0)->flcr = 0x02; + tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) | + TXx927_SIBGR_BCLK_T0; +#if 0 + /* + * Reset the UART. + */ + tx3927_sioptr(0)->fcr = TXx927_SIFCR_SWRST; + while (tx3927_sioptr(0)->fcr & TXx927_SIFCR_SWRST) + ; + + /* + * and set the speed of the serial port + * (currently hardwired to 9600 8N1 + */ + + tx3927_sioptr(0)->lcr = TXx927_SILCR_UMODE_8BIT | + TXx927_SILCR_USBL_1BIT | + TXx927_SILCR_SCS_IMCLK_BG; + tx3927_sioptr(0)->bgr = + ((JMR3927_BASE_BAUD + baud / 2) / baud) | + TXx927_SIBGR_BCLK_T0; + + /* HW RTS/CTS control */ + if (ser->flags & ASYNC_HAVE_CTS_LINE) + tx3927_sioptr(0)->flcr = TXx927_SIFLCR_RCS | TXx927_SIFLCR_TES | + TXx927_SIFLCR_RTSTL_MAX /* 15 */; + /* Enable RX/TX */ + tx3927_sioptr(0)->flcr &= ~(TXx927_SIFLCR_RSDE | TXx927_SIFLCR_TSDE); +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/jmr3927/rbhma3100/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,9 @@ +# +# Makefile for TOSHIBA JMR-TX3927 board +# + +obj-y += init.o int-handler.o irq.o setup.o rtc.o +obj-$(CONFIG_RUNTIME_DEBUG) += debug.o +obj-$(CONFIG_KGDB) += kgdb_io.o + +EXTRA_AFLAGS := $(CFLAGS) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/jmr3927/rbhma3100/rtc.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,56 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * RTC routines for Dallas chip. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 200-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include /* bad name... */ +#include + +static unsigned char jmr3927_rtc_read_data(unsigned long addr) +{ + return jmr3927_nvram_in(addr); +} + +static void jmr3927_rtc_write_data(unsigned char data, unsigned long addr) +{ + jmr3927_nvram_out(data, addr); +} + +static int jmr3927_rtc_bcd_mode(void) +{ + return 1; +} + +struct rtc_ops jmr3927_rtc_ops = { + &jmr3927_rtc_read_data, + &jmr3927_rtc_write_data, + &jmr3927_rtc_bcd_mode +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/jmr3927/rbhma3100/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,528 @@ +/*********************************************************************** + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * Based on arch/mips/ddb5xxx/ddb5477/setup.c + * + * Setup file for JMR3927. + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + *********************************************************************** + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* for HZ */ +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Tick Timer divider */ +#define JMR3927_TIMER_CCD 0 /* 1/2 */ +#define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD)) + +unsigned char led_state = 0xf; + +struct { + struct resource ram0; + struct resource ram1; + struct resource pcimem; + struct resource iob; + struct resource ioc; + struct resource pciio; + struct resource jmy1394; + struct resource rom1; + struct resource rom0; + struct resource sio0; + struct resource sio1; +} jmr3927_resources = { + { "RAM0", 0, 0x01FFFFFF, IORESOURCE_MEM }, + { "RAM1", 0x02000000, 0x03FFFFFF, IORESOURCE_MEM }, + { "PCIMEM", 0x08000000, 0x07FFFFFF, IORESOURCE_MEM }, + { "IOB", 0x10000000, 0x13FFFFFF }, + { "IOC", 0x14000000, 0x14FFFFFF }, + { "PCIIO", 0x15000000, 0x15FFFFFF }, + { "JMY1394", 0x1D000000, 0x1D3FFFFF }, + { "ROM1", 0x1E000000, 0x1E3FFFFF }, + { "ROM0", 0x1FC00000, 0x1FFFFFFF }, + { "SIO0", 0xFFFEF300, 0xFFFEF3FF }, + { "SIO1", 0xFFFEF400, 0xFFFEF4FF }, +}; + +/* don't enable - see errata */ +int jmr3927_ccfg_toeon = 0; + +static inline void do_reset(void) +{ +#ifdef CONFIG_TC35815 + extern void tc35815_killall(void); + tc35815_killall(); +#endif +#if 1 /* Resetting PCI bus */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); + (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */ + mdelay(1); + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); +#endif + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); +} + +static void jmr3927_machine_restart(char *command) +{ + cli(); + puts("Rebooting..."); + do_reset(); +} + +static void jmr3927_machine_halt(void) +{ + puts("JMR-TX3927 halted.\n"); + while (1); +} + +static void jmr3927_machine_power_off(void) +{ + puts("JMR-TX3927 halted. Please turn off the power.\n"); + while (1); +} + +#define USE_RTC_DS1742 +#ifdef USE_RTC_DS1742 +extern void rtc_ds1742_init(unsigned long base); +#endif +static void __init jmr3927_time_init(void) +{ +#ifdef USE_RTC_DS1742 + if (jmr3927_have_nvram()) { + rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR); + } +#endif +} + +unsigned long jmr3927_do_gettimeoffset(void); +extern int setup_irq(unsigned int irq, struct irqaction *irqaction); + +static void __init jmr3927_timer_setup(struct irqaction *irq) +{ + do_gettimeoffset = jmr3927_do_gettimeoffset; + + jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ; + jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE; + jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD; + jmr3927_tmrptr->tcr = + TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL; + + setup_irq(JMR3927_IRQ_TICK, irq); +} + +#define USECS_PER_JIFFY (1000000/HZ) + +unsigned long jmr3927_do_gettimeoffset(void) +{ + unsigned long count; + unsigned long res = 0; + + /* MUST read TRR before TISR. */ + count = jmr3927_tmrptr->trr; + + if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) { + /* timer interrupt is pending. use Max value. */ + res = USECS_PER_JIFFY - 1; + } else { + /* convert to usec */ + /* res = count / (JMR3927_TIMER_CLK / 1000000); */ + res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000); + + /* + * Due to possible jiffies inconsistencies, we need to check + * the result so that we'll get a timer that is monotonic. + */ + if (res >= USECS_PER_JIFFY) + res = USECS_PER_JIFFY-1; + } + + return res; +} + + +#if defined(CONFIG_BLK_DEV_INITRD) +extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end; +#endif + +//#undef DO_WRITE_THROUGH +#define DO_WRITE_THROUGH +#define DO_ENABLE_CACHE + +extern char * __init prom_getcmdline(void); +static void jmr3927_board_init(void); +extern void jmr3927_irq_setup(void); +extern struct resource pci_io_resource; +extern struct resource pci_mem_resource; + +void __init jmr3927_setup(void) +{ + extern int panic_timeout; + char *argptr; + + irq_setup = jmr3927_irq_setup; + set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); + + board_time_init = jmr3927_time_init; + board_timer_setup = jmr3927_timer_setup; + + _machine_restart = jmr3927_machine_restart; + _machine_halt = jmr3927_machine_halt; + _machine_power_off = jmr3927_machine_power_off; + + /* + * IO/MEM resources. + */ + ioport_resource.start = pci_io_resource.start; + ioport_resource.end = pci_io_resource.end; + iomem_resource.start = pci_mem_resource.start; + iomem_resource.end = pci_mem_resource.end; + + /* Reboot on panic */ + panic_timeout = 180; + + { + unsigned int conf; + conf = read_c0_conf(); + } + +#if 1 + /* cache setup */ + { + unsigned int conf; +#ifdef DO_ENABLE_CACHE + int mips_ic_disable = 0, mips_dc_disable = 0; +#else + int mips_ic_disable = 1, mips_dc_disable = 1; +#endif +#ifdef DO_WRITE_THROUGH + int mips_config_cwfon = 0; + int mips_config_wbon = 0; +#else + int mips_config_cwfon = 1; + int mips_config_wbon = 1; +#endif + + conf = read_c0_conf(); + conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON); + conf |= mips_ic_disable ? 0 : TX39_CONF_ICE; + conf |= mips_dc_disable ? 0 : TX39_CONF_DCE; + conf |= mips_config_wbon ? TX39_CONF_WBON : 0; + conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0; + + write_c0_conf(conf); + write_c0_cache(0); + } +#endif + + /* initialize board */ + jmr3927_board_init(); + + argptr = prom_getcmdline(); + + if ((argptr = strstr(argptr, "toeon")) != NULL) { + jmr3927_ccfg_toeon = 1; + } + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "ip=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " ip=bootp"); + } + +#ifdef CONFIG_TXX927_SERIAL_CONSOLE + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "console=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " console=ttyS1,115200"); + } +#endif +} + + +static void tx3927_setup(void); + +#ifdef CONFIG_PCI +unsigned long mips_pci_io_base; +unsigned long mips_pci_io_size; +unsigned long mips_pci_mem_base; +unsigned long mips_pci_mem_size; +/* for legacy I/O, PCI I/O PCI Bus address must be 0 */ +unsigned long mips_pci_io_pciaddr = 0; +#endif + +extern struct rtc_ops *rtc_ops; +extern struct rtc_ops jmr3927_rtc_ops; + +static void __init jmr3927_board_init(void) +{ + char *argptr; + +#ifdef CONFIG_PCI + mips_pci_io_base = JMR3927_PCIIO; + mips_pci_io_size = JMR3927_PCIIO_SIZE; + mips_pci_mem_base = JMR3927_PCIMEM; + mips_pci_mem_size = JMR3927_PCIMEM_SIZE; +#endif + + tx3927_setup(); + +#ifdef CONFIG_VT + conswitchp = &dummy_con; +#endif + + if (jmr3927_have_isac()) { + +#ifdef CONFIG_FB_E1355 + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "video=")) == NULL) { + argptr = prom_getcmdline(); + strcat(argptr, " video=e1355fb:crt16h"); + } +#endif + +#ifdef CONFIG_BLK_DEV_IDE + /* overrides PCI-IDE */ +#endif + } +#ifdef USE_RTC_DS1742 + if (jmr3927_have_nvram()) { + rtc_ops = &jmr3927_rtc_ops; + } +#endif + + /* SIO0 DTR on */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); + + jmr3927_led_set(0); + + + if (jmr3927_have_isac()) + jmr3927_io_led_set(0); + printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", + jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, + jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, + jmr3927_dipsw1(), jmr3927_dipsw2(), + jmr3927_dipsw3(), jmr3927_dipsw4()); + if (jmr3927_have_isac()) + printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n", + jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK, + jmr3927_io_dipsw()); +} + +static void __init tx3927_setup(void) +{ + int i; + + /* SDRAMC are configured by PROM */ + + /* ROMC */ + tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048; + tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8; + tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; + tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; + + /* CCFG */ + /* enable Timeout BusError */ + if (jmr3927_ccfg_toeon) + tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE; + + /* clear BusErrorOnWrite flag */ + tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; + /* Disable PCI snoop */ + tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; + +#ifdef DO_WRITE_THROUGH + /* Enable PCI SNOOP - with write through only */ + tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP; +#endif + + /* Pin selection */ + tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; + tx3927_ccfgptr->pcfg |= + TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | + (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); + + printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n", + tx3927_ccfgptr->crir, + tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg); + + /* IRC */ + /* disable interrupt control */ + tx3927_ircptr->cer = 0; + /* mask all IRC interrupts */ + tx3927_ircptr->imr = 0; + for (i = 0; i < TX3927_NUM_IR / 2; i++) { + tx3927_ircptr->ilr[i] = 0; + } + /* setup IRC interrupt mode (Low Active) */ + for (i = 0; i < TX3927_NUM_IR / 8; i++) { + tx3927_ircptr->cr[i] = 0; + } + + /* TMR */ + /* disable all timers */ + for (i = 0; i < TX3927_NR_TMR; i++) { + tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE; + tx3927_tmrptr(i)->tisr = 0; + tx3927_tmrptr(i)->cpra = 0xffffffff; + tx3927_tmrptr(i)->itmr = 0; + tx3927_tmrptr(i)->ccdr = 0; + tx3927_tmrptr(i)->pgmr = 0; + } + + /* DMA */ + tx3927_dmaptr->mcr = 0; + for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) { + /* reset channel */ + tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST; + tx3927_dmaptr->ch[i].ccr = 0; + } + /* enable DMA */ +#ifdef __BIG_ENDIAN + tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; +#else + tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; +#endif + +#ifdef CONFIG_PCI + /* PCIC */ + printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:", + tx3927_pcicptr->did, tx3927_pcicptr->vid, + tx3927_pcicptr->rid); + if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) { + printk("External\n"); + /* XXX */ + } else { + printk("Internal\n"); + + /* Reset PCI Bus */ + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + udelay(100); + jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, + JMR3927_IOC_RESET_ADDR); + udelay(100); + jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); + + + /* Disable External PCI Config. Access */ + tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD; +#ifdef __BIG_ENDIAN + tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE | + TX3927_PCIC_LBC_TIBSE | + TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE; +#endif + /* LB->PCI mappings */ + tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1); + tx3927_pcicptr->ilbioma = mips_pci_io_base; + tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr; + tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1); + tx3927_pcicptr->ilbmma = mips_pci_mem_base; + tx3927_pcicptr->ipbmma = mips_pci_mem_base; + /* PCI->LB mappings */ + tx3927_pcicptr->iobas = 0xffffffff; + tx3927_pcicptr->ioba = 0; + tx3927_pcicptr->tlbioma = 0; + tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1); + tx3927_pcicptr->mba = 0; + tx3927_pcicptr->tlbmma = 0; +#ifndef JMR3927_INIT_INDIRECT_PCI + /* Enable Direct mapping Address Space Decoder */ + tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE; +#endif + + /* Clear All Local Bus Status */ + tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL; + /* Enable All Local Bus Interrupts */ + tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL; + /* Clear All PCI Status Error */ + tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL; + /* Enable All PCI Status Error Interrupts */ + tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL; + + /* PCIC Int => IRC IRQ10 */ + tx3927_pcicptr->il = TX3927_IR_PCI; +#if 1 + /* Target Control (per errata) */ + tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E; +#endif + + /* Enable Bus Arbiter */ +#if 0 + tx3927_pcicptr->req_trace = 0x73737373; +#endif + tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN; + + tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | +#if 1 + PCI_COMMAND_IO | +#endif + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; + } +#endif /* CONFIG_PCI */ + + /* PIO */ + /* PIO[15:12] connected to LEDs */ + tx3927_pioptr->dir = 0x0000f000; + tx3927_pioptr->maskcpu = 0; + tx3927_pioptr->maskext = 0; + { + unsigned int conf; + + conf = read_c0_conf(); + if (!(conf & TX39_CONF_ICE)) + printk("TX3927 I-Cache disabled.\n"); + if (!(conf & TX39_CONF_DCE)) + printk("TX3927 D-Cache disabled.\n"); + else if (!(conf & TX39_CONF_WBON)) + printk("TX3927 D-Cache WriteThrough.\n"); + else if (!(conf & TX39_CONF_CWFON)) + printk("TX3927 D-Cache WriteBack.\n"); + else + printk("TX3927 D-Cache WriteBack (CWF) .\n"); + } +} --- linux-2.5.73/arch/mips/Kconfig 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/Kconfig 2003-06-27 15:56:23.000000000 -0700 @@ -6,1113 +6,12 @@ config MIPS bool default y -config MMU +config MIPS32 bool default y -config SMP +config MIPS64 bool - ---help--- - This enables support for systems with more than one CPU. If you have - a system with only one CPU, like most personal computers, say N. If - you have a system with more than one CPU, say Y. - - If you say N here, the kernel will run on single and multiprocessor - machines, but will use only one CPU of a multiprocessor machine. If - you say Y here, the kernel will run on many, but not all, - singleprocessor machines. On a singleprocessor machine, the kernel - will run faster if you say N here. - - Note that if you say Y here and choose architecture "586" or - "Pentium" under "Processor family", the kernel will not work on 486 - architectures. Similarly, multiprocessor kernels for the "PPro" - architecture may not work on all Pentium based boards. - - People using multiprocessor machines who say Y here should also say - Y to "Enhanced Real Time Clock Support", below. The "Advanced Power - Management" code will be disabled if you say Y here. - - See also the , - , , - and the SMP-HOWTO available at - . - - If you don't know what to do here, say N. - -config GENERIC_ISA_DMA - bool - default y - - -mainmenu "Linux Kernel Configuration" - -source "init/Kconfig" - - -menu "Machine selection" - -config ACER_PICA_61 - bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)" - depends on EXPERIMENTAL - help - This is a machine with a R4400 133/150 MHz CPU. To compile a Linux - kernel that runs on these, say Y here. For details about Linux on - the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at - . - -config ALGOR_P4032 - bool "Support for Algorithmics P4032 (EXPERIMENTAL)" - depends on EXPERIMENTAL - help - This is an evaluation board of the British company Algorithmics. - The board uses the R4300 and a R5230 CPUs. For more information - about this board see . - -config BAGET_MIPS - bool "Support for BAGET MIPS series (EXPERIMENTAL)" - depends on EXPERIMENTAL - help - This enables support for the Baget, a Russian embedded system. For - more details about the Baget see the Linux/MIPS FAQ on - . - -config DECSTATION - bool "Support for DECstations (EXPERIMENTAL)" - depends on EXPERIMENTAL - ---help--- - This enables support for DEC's MIPS based workstations. For details - see the Linux/MIPS FAQ on and the - DECstation porting pages on . - - If you have one of the following DECstation Models you definitely - want to choose R4xx0 for the CPU Type: - - DECstation 5000/50 - DECstation 5000/150 - DECstation 5000/260 - DECsystem 5900/260 - - otherwise choose R3000. - -config DDB5074 - bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)" - depends on EXPERIMENTAL - help - This enables support for the VR5000-based NEC DDB Vrc-5074 - evaluation board. - -config MIPS_EV96100 - bool "Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)" - depends on EXPERIMENTAL - help - This is an evaluation board based on the Galielo GT-96100 LAN/WAN - communications controllers containing a MIPS R5000 compatible core - running at 83MHz. Their website is . Say Y - here if you wish to build a kernel for this platform. - -config MIPS_EV64120 - bool "Support for Galileo EV64120 Evaluation board (EXPERIMENTAL)" - depends on EXPERIMENTAL - help - This is an evaluation board based on the Galileo GT-64120 - single-chip system controller that contains a MIPS R5000 compatible - core running at 75/100MHz. Their website is located at - . Say Y here if you wish to build a - kernel for this platform. - -config EVB_PCI1 - bool "Enable Second PCI (PCI1)" - depends on MIPS_EV64120 - -choice - prompt "Galileo Chip Clock" - depends on MIPS_EV64120 - -config SYSCLK_75 - bool "75" - -config SYSCLK_83 - bool "83.3" - -config SYSCLK_100_1 - bool "100" - -endchoice - -config MIPS_ATLAS - bool "Support for MIPS Atlas board (EXPERIMENTAL)" - depends on EXPERIMENTAL - help - This enables support for the QED R5231-based MIPS Atlas evaluation - board. - -config MIPS_MALTA - bool "Support for MIPS Malta board (EXPERIMENTAL)" - depends on EXPERIMENTAL - help - This enables support for the VR5000-based MIPS Malta evaluation - board. - -config NINO - bool "Support for Philips Nino (EXPERIMENTAL)" - depends on EXPERIMENTAL - help - Say Y here to select a kernel for the Philips Nino Palm PC. The - website at - will have more information. - -choice - prompt "Nino Model Number" - depends on NINO - -config NINO_4MB - bool "Model-300/301/302/319" - help - Say Y here to build a kernel specifically for Nino Palm PCs with - 4MB of memory. These include models 300/301/302/319. - -config NINO_8MB - bool "Model-200/210/312/320/325/350/390" - help - Say Y here to build a kernel specifically for Nino Palm PCs with - 8MB of memory. These include models 200/210/312/320/325/350/390. - -config NINO_16MB - bool "Model-500/510" - help - Say Y here to build a kernel specifically for Nino 500/501 color - Palm PCs from Philips (INCOMPLETE). - -endchoice - -config MIPS_MAGNUM_4000 - bool "Support for Mips Magnum 4000" - help - This is a machine with a R4000 100 MHz CPU. To compile a Linux - kernel that runs on these, say Y here. For details about Linux on - the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at - . - -config MOMENCO_OCELOT - bool "Support for Momentum Ocelot board" - help - The Ocelot is a MIPS-based Single Board Computer (SBC) made by - Momentum Computer . - -config DDB5476 - bool "Support for NEC DDB Vrc-5476" - help - This enables support for the R5432-based NEC DDB Vrc-5476 - evaluation board. - - Features : kernel debugging, serial terminal, NFS root fs, on-board - ether port (Need an additional patch at ), - USB, AC97, PCI, PCI VGA card & framebuffer console, IDE controller, - PS2 keyboard, PS2 mouse, etc. - -config DDB5477 - bool "Support for NEC DDB Vrc-5477" - help - This enables support for the R5432-based NEC DDB Vrc-5477 - evaluation board. - - Features : kernel debugging, serial terminal, NFS root fs, on-board - ether port (Need an additional patch at ), - USB, AC97, PCI, etc. - -config OLIVETTI_M700 - bool "Support for Olivetti M700-10" - help - This is a machine with a R4000 100 MHz CPU. To compile a Linux - kernel that runs on these, say Y here. For details about Linux on - the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at - . - -config SGI_IP22 - bool "Support for SGI IP22" - help - This are the SGI Indy, Challenge S and Indigo2, as well as certain - OEM variants like the Tandem CMN B006S. To compile a Linux kernel - that runs on these, say Y here. - -config SNI_RM200_PCI - bool "Support for SNI RM200 PCI" - help - The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens - Nixdorf Informationssysteme (SNI), parent company of Pyramid - Technology and now in turn merged with Fujitsu. Say Y here to - support this machine type. - -config MIPS_ITE8172 - bool "Support for ITE 8172G board" - help - Ths is an evaluation board made by ITE - with ATX form factor that utilizes a MIPS R5000 to work with its - ITE8172G companion internet appliance chip. The MIPS core can be - either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build - a kernel for this platform. - -config IT8172_REVC - bool "Support for older IT8172 (Rev C)" - depends on MIPS_ITE8172 - help - Say Y here to support the older, Revision C version of the Integrated - Technology Express, Inc. ITE8172 SBC. Vendor page at - ; picture of the - board at . - -config QTRONIX_KEYBOARD - bool "Enable Qtronix 990P Keyboard Support" - depends on MIPS_IVR || MIPS_ITE8172 - help - Images of Qtronix keyboards are at - . - -config IT8172_CIR - bool - depends on QTRONIX_KEYBOARD && (MIPS_IVR || MIPS_ITE8172) - default y - -config PC_KEYB - bool "Enable PS2 Keyboard Support" if MIPS_ITE8172 && !QTRONIX_KEYBOARD - default y if NINO || MIPS_ITE8172 || DDB5476 || DDB5074 || SNI_RM200_PCI || SGI_IP22 || ACER_PICA_61 || MIPS_MAGNUM_4000 || OLIVETTI_M700 - -config IT8172_SCR0 - bool "Enable Smart Card Reader 0 Support " - depends on MIPS_IVR || MIPS_ITE8172 - help - Say Y here to support smart-card reader 0 (SCR0) on the Integrated - Technology Express, Inc. ITE8172 SBC. Vendor page at - ; picture of the - board at . - -config IT8172_SCR1 - bool "Enable Smart Card Reader 1 Support " - depends on MIPS_ITE8172 - help - Say Y here to support smart-card reader 1 (SCR1) on the Integrated - Technology Express, Inc. ITE8172 SBC. Vendor page at - ; picture of the - board at . - -config MIPS_IVR - bool "Support for Globespan IVR board" - help - This is an evaluation board built by Globespan to showcase thir - iVR (Internet Video Recorder) design. It utilizes a QED RM5231 - R5000 MIPS core. More information can be found out their website - located at P. Say Y - here if you wish to build a kernel for this platform. - -config MIPS_PB1000 - bool "Support for Alchemy Semi PB1000 board" - help - This is an evaluation board built by Alchemy Semiconducttor to - showcase their Au1000 Internet Edge Processor. It is SOC design - containing a MIPS32 core running at 266/400/500MHz with many - integrated peripherals. Further information can be found at their - website, . Say Y here if you wish to - build a kernel for this platform. - -config RWSEM_GENERIC_SPINLOCK - bool - default y - -config RWSEM_XCHGADD_ALGORITHM - bool - -# -# Select some configuration options automatically for certain systems. -# -config ISA - bool - depends on DDB5476 || DDB5074 || SNI_RM200_PCI || ACER_PICA_61 || MIPS_MAGNUM_4000 || OLIVETTI_M700 - default y - help - Find out whether you have ISA slots on your motherboard. ISA is the - name of a bus system, i.e. the way the CPU talks to the other stuff - inside your box. Other bus systems are PCI, EISA, MicroChannel - (MCA) or VESA. ISA is an older system, now being displaced by PCI; - newer boards don't support it. If you have ISA, say Y, otherwise N. - -config EISA - bool - depends on ISA - default y - ---help--- - The Extended Industry Standard Architecture (EISA) bus was - developed as an open alternative to the IBM MicroChannel bus. - - The EISA bus provided some of the features of the IBM MicroChannel - bus while maintaining backward compatibility with cards made for - the older ISA bus. The EISA bus saw limited use between 1988 and - 1995 when it was made obsolete by the PCI bus. - - Say Y here if you are building a kernel for an EISA-based machine. - - Otherwise, say N. - -config PCI - bool - depends on MIPS_IVR || MIPS_ITE8172 || DDB5477 || DDB5476 || DDB5074 || SNI_RM200_PCI || MOMENCO_OCELOT || MIPS_MALTA || MIPS_ATLAS || ALGOR_P4032 || MIPS_EV64120 || MIPS_EV96100 - default y - help - Find out whether you have a PCI motherboard. PCI is the name of a - bus system, i.e. the way the CPU talks to the other stuff inside - your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or - VESA. If you have PCI, say Y, otherwise N. - - The PCI-HOWTO, available from - , contains valuable - information about which PCI hardware does work under Linux and which - doesn't. - -config MCA - bool - help - MicroChannel Architecture is found in some IBM PS/2 machines and - laptops. It is a bus system similar to PCI or ISA. See - (and especially the web page given - there) before attempting to build an MCA bus kernel. - -config SBUS - bool - -config I8259 - bool - depends on DDB5074 || SNI_RM200_PCI || MIPS_MALTA || ACER_PICA_61 || MIPS_MAGNUM_4000 || OLIVETTI_M700 - default y - -config MIPS_GT96100 - bool - depends on MIPS_EV96100 - default y - help - Say Y here to support the Galileo Technology GT96100 communications - controller card. There is a web page at . - -config SWAP_IO_SPACE - bool - depends on MOMENCO_OCELOT || MIPS_MALTA || MIPS_ATLAS || MIPS_EV96100 - default y - -config NEW_PCI - bool - depends on MIPS_ITE8172 || MIPS_EV96100 - default y - -config PCI_AUTO - bool - depends on MIPS_ITE8172 || MIPS_EV96100 - default y - -config MIPS_GT64120 - bool - depends on MIPS_EV64120 - default y - -config OLD_TIME_C - bool - depends on DDB5074 || SNI_RM200_PCI || SGI_IP22 || MOMENCO_OCELOT || ACER_PICA_61 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ALGOR_P4032 || MIPS_EV64120 - default y - -config ARC32 - bool - depends on SNI_RM200_PCI || SGI_IP22 || ACER_PICA_61 || MIPS_MAGNUM_4000 || OLIVETTI_M700 - default y - -config FB - bool - depends on MIPS_MAGNUM_4000 || OLIVETTI_M700 - default y - ---help--- - The frame buffer device provides an abstraction for the graphics - hardware. It represents the frame buffer of some video hardware and - allows application software to access the graphics hardware through - a well-defined interface, so the software doesn't need to know - anything about the low-level (hardware register) stuff. - - Frame buffer devices work identically across the different - architectures supported by Linux and make the implementation of - application programs easier and more portable; at this point, an X - server exists which uses the frame buffer device exclusively. - On several non-X86 architectures, the frame buffer device is the - only way to use the graphics hardware. - - The device is accessed through special device nodes, usually located - in the /dev directory, i.e. /dev/fb*. - - You need an utility program called fbset to make full use of frame - buffer devices. Please read - and the Framebuffer-HOWTO at - for more - information. - - Say Y here and to the driver for your graphics board below if you - are compiling a kernel for a non-x86 architecture. - - If you are compiling for the x86 architecture, you can say Y if you - want to play with it, but it is not essential. Please note that - running graphical applications that directly touch the hardware - (e.g. an accelerated X server) and that are not frame buffer - device-aware may cause unexpected results. If unsure, say N. - -config FB_G364 - bool - depends on MIPS_MAGNUM_4000 || OLIVETTI_M700 - default y - -config MIPS_JAZZ - bool - depends on ACER_PICA_61 || MIPS_MAGNUM_4000 || OLIVETTI_M700 - default y - -config ROTTEN_IRQ - bool - depends on DDB5476 || DDB5074 || SNI_RM200_PCI || ACER_PICA_61 - default y - -config HAVE_STD_PC_SERIAL_PORT - bool - depends on DDB5476 || DDB5074 || MIPS_MALTA - default y - -config NEW_IRQ - bool - depends on MIPS_PB1000 || DDB5477 || SGI_IP22 || MOMENCO_OCELOT || MIPS_MALTA - default y - -config SYSCLK_100_2 - bool - depends on MOMENCO_OCELOT - default y - -config BOARD_SCACHE - bool - depends on SGI_IP22 - default y - -config SGI - bool - depends on SGI_IP22 - default y - -config NEW_TIME_C - bool - depends on DDB5477 || DDB5476 - default y - -config CPU_LITTLE_ENDIAN - bool - depends on DDB5477 - default y - help - Some MIPS machines can be configured for either little or big endian - byte order. These modes require different kernels. Say Y if your - machine is little endian, N if it's a big endian machine. - -config IT8712 - bool - depends on MIPS_ITE8172 - default y - -config MIPS_AU1000 - bool - depends on MIPS_PB1000 - default y - -config SYSCLK_100 - bool - depends on SYSCLK_100_1 || SYSCLK_100_2 - default y - -endmenu - - -menu "CPU selection" - -choice - prompt "CPU type" - default CPU_R4X00 - -config CPU_R3000 - bool "R3000" - ---help--- - Please make sure to pick the right CPU type. Linux/MIPS is not - designed to be generic, i.e. Kernels compiled for R3000 CPUs will - *not* work on R4000 machines and vice versa. However, since most - of the supported machines have an R4000 (or similar) CPU, R4x00 - might be a safe bet. If the resulting kernel does not work, - try to recompile with R3000. - - R3000 MIPS Technologies R3000-series processors, - including the 3041, 3051, and 3081. - - R6000 MIPS Technologies R6000-series processors, - including the 64474, 64475, 64574 and 64575. - - R4300 MIPS Technologies R4300-series processors. - - R4x00 MIPS Technologies R4000-series processors other than 4300, - including the 4640, 4650, and 4700. - - R5000 MIPS Technologies R5000-series processors other than the - Nevada. - - R52xx MIPS Technologies R52xx-series ("Nevada") processors. - - R10000 MIPS Technologies R10000-series processors. - -config CPU_R6000 - bool "R6000" - help - MIPS Technologies R6000-series processors, including the 64474, - 64475, 64574 and 64575. - -config CPU_VR41XX - bool "R41xx" - help - The options selects support for the NEC VR41xx series of processors. - Only choose this option if you have one of these processors as a - kernel built with this option will not run on any other type of - processor or vice versa. - -config CPU_R4300 - bool "R4300" - help - MIPS Technologies R4300-series processors. - -config CPU_R4X00 - bool "R4x00" - help - MIPS Technologies R4000-series processors other than 4300, including - the 4640, 4650, and 4700. - -config CPU_R5000 - bool "R5000" - help - MIPS Technologies R5000-series processors other than the Nevada. - -config CPU_R5432 - bool "R5432" - -config CPU_RM7000 - bool "RM7000" - -config CPU_NEVADA - bool "R52xx" - help - MIPS Technologies R52x0-series ("Nevada") processors. - -config CPU_R10000 - bool "R10000" - help - MIPS Technologies R10000-series processors. - -config CPU_SB1 - bool "SB1" - -config CPU_MIPS32 - bool "MIPS32" - -config CPU_MIPS64 - bool "MIPS64" - -endchoice - -config CPU_ADVANCED - bool "Override CPU Options" - help - Saying yes here allows you to select support for various features - your CPU may or may not have. Most people should say N here. - -config CPU_HAS_LLSC - bool "ll/sc Instructions available" if CPU_ADVANCED - default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX - help - MIPS R4000 series and later provide the Load Linked (ll) - and Store Conditional (sc) instructions. More information is - available at . - - Say Y here if your CPU has the ll and sc instructions. Say Y here - for better performance, N if you don't know. You must say Y here - for multiprocessor machines. - -config CPU_HAS_LLDSCD - bool "lld/scd Instructions available" if CPU_ADVANCED - default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_MIPS32 - help - Say Y here if your CPU has the lld and scd instructions, the 64-bit - equivalents of ll and sc. Say Y here for better performance, N if - you don't know. You must say Y here for multiprocessor machines. - -config CPU_HAS_WB - bool "Writeback Buffer available" if CPU_ADVANCED - default y if !CPU_ADVANCED && (CPU_R3000 || CPU_VR41XX) && CONFIG_DECSTATION=y - help - Say N here for slightly better performance. You must say Y here for - machines which require flushing of write buffers in software. Saying - Y is the safe option; N may result in kernel malfunction and crashes. - -endmenu - - -menu "General setup" - -config CPU_LITTLE_ENDIAN - bool "Generate little endian code" if !DECSTATION && !DDB5074 && !DDB5476 && !NINO - default y if DECSTATION || DDB5074 || DDB5476 || NINO - -config KCORE_ELF - bool - depends on PROC_FS - default y - ---help--- - If you enabled support for /proc file system then the file - /proc/kcore will contain the kernel core image. This can be used - in gdb: - - $ cd /usr/src/linux ; gdb vmlinux /proc/kcore - - You have two choices here: ELF and A.OUT. Selecting ELF will make - /proc/kcore appear in ELF core format as defined by the Executable - and Linking Format specification. Selecting A.OUT will choose the - old "a.out" format which may be necessary for some old versions - of binutils or on some architectures. - - This is especially useful if you have compiled the kernel with the - "-g" option to preserve debugging information. It is mainly used - for examining kernel data structures on the live kernel so if you - don't understand what this means or are not a kernel hacker, just - leave it at its default value ELF. - -config ELF_KERNEL - bool - default y - -config BINFMT_IRIX - bool "Include IRIX binary compatibility" - depends on !CPU_LITTLE_ENDIAN - -config FORWARD_KEYBOARD - bool "Include forward keyboard" - depends on !CPU_LITTLE_ENDIAN - -config ARC_CONSOLE - bool "ARC console support" - depends on ARC32 - -source "fs/Kconfig.binfmt" - -source "drivers/pci/Kconfig" - -config HOTPLUG - bool "Support for hot-pluggable devices" - ---help--- - Say Y here if you want to plug devices into your computer while - the system is running, and be able to use them quickly. In many - cases, the devices can likewise be unplugged at any time too. - - One well known example of this is PCMCIA- or PC-cards, credit-card - size devices such as network cards, modems or hard drives which are - plugged into slots found on all modern laptop computers. Another - example, used on modern desktops as well as laptops, is USB. - - Enable HOTPLUG and KMOD, and build a modular kernel. Get agent - software (at ) and install it. - Then your kernel will automatically call out to a user mode "policy - agent" (/sbin/hotplug) to load modules and set up software needed - to use devices as you hotplug them. - -source "drivers/pcmcia/Kconfig" - -config TC - bool "TURBOchannel support" - depends on DECSTATION - help - TurboChannel is a DEC (now Compaq) bus for Alpha and MIPS processors. - Documentation on writing device drivers for TurboChannel is available at: - . - -# if [ "$CONFIG_TC" = "y" ]; then -# bool ' Access.Bus support' CONFIG_ACCESSBUS -# fi -endmenu - - -if ISA -source "drivers/pnp/Kconfig" -endif - -source "drivers/base/Kconfig" - -source "drivers/mtd/Kconfig" - -source "drivers/parport/Kconfig" - -source "drivers/block/Kconfig" - -source "drivers/md/Kconfig" - -if !SGI_IP22 && !DECSTATION -source "drivers/ide/Kconfig" -endif - - -menu "SCSI support" - -config SCSI - tristate "SCSI support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - -source "drivers/scsi/Kconfig" - -endmenu - - -if !DECSTATION && !SGI_IP22 -source "drivers/message/i2o/Kconfig" -endif - -source "net/Kconfig" - -source "net/ax25/Kconfig" - -source "net/irda/Kconfig" - -source "drivers/isdn/Kconfig" - -source "drivers/telephony/Kconfig" - - -menu "Old CD-ROM drivers (not SCSI, not IDE)" - -config CD_NO_IDESCSI - bool "Support non-SCSI/IDE/ATAPI CDROM drives" - ---help--- - If you have a CD-ROM drive that is neither SCSI nor IDE/ATAPI, say Y - here, otherwise N. Read the CD-ROM-HOWTO, available from - . - - Note that the answer to this question doesn't directly affect the - kernel: saying N will just cause the configurator to skip all - the questions about these CD-ROM drives. If you are unsure what you - have, say Y and find out whether you have one of the following - drives. - - For each of these drivers, a file Documentation/cdrom/{driver_name} - exists. Especially in cases where you do not know exactly which kind - of drive you have you should read there. Most of these drivers use a - file drivers/cdrom/{driver_name}.h where you can define your - interface parameters and switch some internal goodies. - - All these CD-ROM drivers are also usable as a module ( = code which - can be inserted in and removed from the running kernel whenever you - want). If you want to compile them as module, say M instead of Y and - read . - - If you want to use any of these CD-ROM drivers, you also have to - answer Y or M to "ISO 9660 CD-ROM file system support" below (this - answer will get "defaulted" for you if you enable any of the Linux - CD-ROM drivers). - -source "drivers/cdrom/Kconfig" - -endmenu - -source "drivers/input/Kconfig" - -source "drivers/char/Kconfig" - -source "drivers/media/Kconfig" - - -menu "DECStation Character devices" - depends on DECSTATION - -config VT - bool "Virtual terminal" - -config VT_CONSOLE - bool "Support for console on virtual terminal" - depends on VT - -config SERIAL - tristate "Standard/generic (dumb) serial support" - ---help--- - This selects whether you want to include the driver for the standard - serial ports. The standard answer is Y. People who might say N - here are those that are setting up dedicated Ethernet WWW/FTP - servers, or users that have one of the various bus mice instead of a - serial mouse and don't intend to use their machine's standard serial - port for anything. (Note that the Cyclades and Stallion multi - serial port drivers do not need this driver built in for them to - work.) - - If you want to compile this driver as a module, say M here and read - . The module will be called - serial. - [WARNING: Do not compile this driver as a module if you are using - non-standard serial ports, since the configuration information will - be lost when the driver is unloaded. This limitation may be lifted - in the future.] - - BTW1: If you have a mouseman serial mouse which is not recognized by - the X window system, try running gpm first. - - BTW2: If you intend to use a software modem (also called Winmodem) - under Linux, forget it. These modems are crippled and require - proprietary drivers which are only available under Windows. - - Most people will say Y or M here, so that they can use serial mice, - modems and similar devices connecting to the standard serial ports. - -config DZ - bool "DZ11 Serial Support" - depends on SERIAL=y - help - DZ11-family serial controllers for VAXstations, including the - DC7085, M7814, and M7819. - -config ZS - bool "Z85C30 Serial Support" - depends on SERIAL=y && TC - help - Documentation on the Zilog 85C350 serial communications controller - is downloadable at . - -config SERIAL_CONSOLE - bool "Support for console on serial port" - depends on SERIAL=y - ---help--- - If you say Y here, it will be possible to use a serial port as the - system console (the system console is the device which receives all - kernel messages and warnings and which allows logins in single user - mode). This could be useful if some terminal or printer is connected - to that serial port. - - Even if you say Y here, the currently visible virtual console - (/dev/tty0) will still be used as the system console by default, but - you can alter that using a kernel command line option such as - "console=ttyS1". (Try "man bootparam" or see the documentation of - your boot loader (lilo or loadlin) about how to pass options to the - kernel at boot time.) - - If you don't have a VGA card installed and you say Y here, the - kernel will automatically use the first serial line, /dev/ttyS0, as - system console. - - If unsure, say N. - -config UNIX98_PTYS - bool "Unix98 PTY support" - -config UNIX98_PTY_COUNT - int "Maximum number of Unix98 PTYs in use (0-2048)" - depends on UNIX98_PTYS - default "256" - -# if [ "$CONFIG_ACCESSBUS" = "y" ]; then -# bool 'MAXINE Access.Bus mouse (VSXXX-BB/GB) support' CONFIG_DTOP_MOUSE -# fi -config RTC - tristate "Enhanced Real Time Clock Support" - -endmenu - - -menu "SGI Character devices" - depends on SGI_IP22 - -config VT - bool "Virtual terminal" - -config VT_CONSOLE - bool "Support for console on virtual terminal" - depends on VT - -config PSMOUSE - bool "PS/2 mouse support (aka \"auxiliary device\")" - ---help--- - The PS/2 mouse connects to a special mouse port that looks much like - the keyboard port (small circular connector with 6 pins). This way, - the mouse does not use any serial ports. This port can also be used - for other input devices like light pens, tablets, keypads. Compaq, - AST and IBM all use this as their mouse port on currently shipping - machines. The trackballs of some laptops are PS/2 mice also. In - particular, the C&T 82C710 mouse on TI Travelmates is a PS/2 mouse. - - Although PS/2 mice are not technically bus mice, they are explained - in detail in the Busmouse-HOWTO, available from - . - - When using a PS/2 mouse, you can get problems if you want to use the - mouse both on the Linux console and under X. Using the "-R" option - of the Linux mouse managing program gpm (available from - ) solves this problem, or you can get - the "mconv2" utility from . - -config MOUSE - bool - depends on PSMOUSE - default y - ---help--- - This is for machines with a mouse which is neither a serial nor a - bus mouse. Examples are PS/2 mice (such as the track balls on some - laptops) and some digitizer pads. Most people have a regular serial - MouseSystem or Microsoft mouse (made by Logitech) that plugs into a - COM port (rectangular with 9 or 25 pins). These people say N here. - If you have something else, read the Busmouse-HOWTO, available from - . This HOWTO contains - information about all non-serial mice, not just bus mice. - - If you have a laptop, you either have to check the documentation or - experiment a bit to find out whether the trackball is a serial mouse - or not; it's best to say Y here for you. - - Note that the answer to this question won't directly affect the - kernel: saying N will just cause the configurator to skip all - the questions about non-serial mice. If unsure, say Y. - -config UNIX98_PTYS - bool "Unix98 PTY support" - -config UNIX98_PTY_COUNT - int "Maximum number of Unix98 PTYs in use (0-2048)" - depends on UNIX98_PTYS - default "256" - -endmenu - -source "fs/Kconfig" - -source "drivers/video/Kconfig" - -menu "Sound" - depends on !DECSTATION - -config SOUND - tristate "Sound card support" - ---help--- - If you have a sound card in your computer, i.e. if it can say more - than an occasional beep, say Y. Be sure to have all the information - about your sound card and its configuration down (I/O port, - interrupt and DMA channel), because you will be asked for it. - - You want to read the Sound-HOWTO, available from - . General information about - the modular sound system is contained in the files - . The file - contains some slightly - outdated but still useful information as well. - - If you have a PnP sound card and you want to configure it at boot - time using the ISA PnP tools (read - ), then you need to - compile the sound card support as a module ( = code which can be - inserted in and removed from the running kernel whenever you want) - and load that module after the PnP configuration is finished. To do - this, say M here and read as well - as ; the module will be - called soundcore. - - I'm told that even without a sound card, you can make your computer - say more than an occasional beep, by programming the PC speaker. - Kernel patches and supporting utilities to do that are in the pcsp - package, available at . - -source "sound/Kconfig" - -endmenu - -source "drivers/sgi/Kconfig" - -source "drivers/usb/Kconfig" - - -menu "Kernel hacking" - -config CROSSCOMPILE - bool "Are you using a crosscompiler" - help - Say Y here if you are compiling the kernel on a different - architecture than the one it is intended to run on. - -config REMOTE_DEBUG - bool "Remote GDB kernel debugging" - depends on SERIAL=y || AU1000_UART - help - If you say Y here, it will be possible to remotely debug the MIPS - kernel using gdb. This enlarges your kernel image disk size by - several megabytes and requires a machine with more than 16 MB, - better 32 MB RAM to avoid excessive linking time. This is only - useful for kernel hackers. If unsure, say N. - -config GDB_CONSOLE - bool "Console output to GDB" - depends on REMOTE_DEBUG - help - If you are using GDB for remote debugging over a serial port and - would like kernel messages to be formatted into GDB $O packets so - that GDB prints them as program output, say 'Y'. - -config LL_DEBUG - bool "Low-level debugging" - depends on SERIAL=y - help - Enable low-level debugging assertion macros in the kernel code. - Currently used only by the time services code in the MIPS port. - Don't turn this on unless you know what you are doing. - -config MAGIC_SYSRQ - bool "Magic SysRq key" - help - If you say Y here, you will have some control over the system even - if the system crashes for example during kernel debugging (e.g., you - will be able to flush the buffer cache to disk, reboot the system - immediately or dump some status information). This is accomplished - by pressing various keys while holding SysRq (Alt+PrintScreen). It - also works on a serial console (on PC hardware at least), if you - send a BREAK and then within 5 seconds a command keypress. The - keys are documented in . Don't say Y - unless you really know what this hack does. - -config MIPS_UNCACHED - bool "Run uncached" - depends on !SMP - help - If you say Y here there kernel will disable all CPU caches. This will - reduce the system's performance dramatically but can help finding - otherwise hard to track bugs. It can also useful if you're doing - hardware debugging with a logic analyzer and need to see all traffic - on the bus. - -config NR_CPUS - int "Maximum number of CPUs (2-32)" - depends on SMP - default "32" - -endmenu - -source "security/Kconfig" - -source "crypto/Kconfig" - -source "lib/Kconfig" + default n +source "arch/mips/Kconfig-shared" --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/Kconfig-shared 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,1371 @@ +mainmenu "Linux/MIPS Kernel Configuration" + +source "init/Kconfig" + +menu "Machine selection" + +config ACER_PICA_61 + bool "Support for Acer PICA 1 chipset (EXPERIMENTAL)" + depends on EXPERIMENTAL + help + This is a machine with a R4400 133/150 MHz CPU. To compile a Linux + kernel that runs on these, say Y here. For details about Linux on + the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at + . + +config BAGET_MIPS + bool "Support for BAGET MIPS series (EXPERIMENTAL)" + depends on MIPS32 && EXPERIMENTAL + help + This enables support for the Baget, a Russian embedded system. For + more details about the Baget see the Linux/MIPS FAQ on + . + +config CASIO_E55 + bool "Support for CASIO CASSIOPEIA E-10/15/55/65" + +config MIPS_COBALT + bool "Support for Cobalt Server (EXPERIMENTAL)" + depends on EXPERIMENTAL + +config DECSTATION + bool "Support for DECstations" + depends on MIPS32 || EXPERIMENTAL + ---help--- + This enables support for DEC's MIPS based workstations. For details + see the Linux/MIPS FAQ on and the + DECstation porting pages on . + + If you have one of the following DECstation Models you definitely + want to choose R4xx0 for the CPU Type: + + DECstation 5000/50 + DECstation 5000/150 + DECstation 5000/260 + DECsystem 5900/260 + + otherwise choose R3000. + +config MIPS_EV64120 + bool "Support for Galileo EV64120 Evaluation board (EXPERIMENTAL)" + depends on EXPERIMENTAL + help + This is an evaluation board based on the Galileo GT-64120 + single-chip system controller that contains a MIPS R5000 compatible + core running at 75/100MHz. Their website is located at + . Say Y here if you wish to build a + kernel for this platform. + +config EVB_PCI1 + bool "Enable Second PCI (PCI1)" + depends on MIPS_EV64120 + +if MOMENCO_OCELOT_G || MOMENCO_OCELOT + +config SYSCLK_100 + bool + default y + +endif +if MIPS_EV64120 + +choice + prompt "Galileo Chip Clock" + default SYSCLK_83 + +config SYSCLK_75 + bool "75" + +config SYSCLK_83 + bool "83.3" + +config SYSCLK_100 + bool "100" if MIPS_EV64120 + +endchoice + +endif + +config MIPS_EV96100 + bool "Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)" + depends on EXPERIMENTAL + help + This is an evaluation board based on the Galielo GT-96100 LAN/WAN + communications controllers containing a MIPS R5000 compatible core + running at 83MHz. Their website is . Say Y + here if you wish to build a kernel for this platform. + +config MIPS_IVR + bool "Support for Globespan IVR board" + help + This is an evaluation board built by Globespan to showcase thir + iVR (Internet Video Recorder) design. It utilizes a QED RM5231 + R5000 MIPS core. More information can be found out their website + located at P. Say Y + here if you wish to build a kernel for this platform. + +config LASAT + bool "Support for LASAT Networks platforms" + +config LASAT_100 + bool "Support for LASAT Networks 100 series" + depends on LASAT + +config LASAT_200 + bool "Support for LASAT Networks 200 series" + depends on LASAT + +config PICVUE + tristate "PICVUE LCD display driver" + depends on LASAT + +config PICVUE_PROC + tristate "PICVUE LCD display driver /proc interface" + depends on PICVUE + +config DS1603 + bool "DS1603 RTC driver" + depends on LASAT + +config LASAT_SYSCTL + bool "LASAT sysctl interface" + depends on LASAT + +config HP_LASERJET + bool "Support for Hewlett Packard LaserJet board" + +config IBM_WORKPAD + bool "Support for IBM WorkPad z50" + +config MIPS_ITE8172 + bool "Support for ITE 8172G board" + help + Ths is an evaluation board made by ITE + with ATX form factor that utilizes a MIPS R5000 to work with its + ITE8172G companion internet appliance chip. The MIPS core can be + either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build + a kernel for this platform. + +config IT8172_REVC + bool "Support for older IT8172 (Rev C)" + depends on MIPS_ITE8172 + help + Say Y here to support the older, Revision C version of the Integrated + Technology Express, Inc. ITE8172 SBC. Vendor page at + ; picture of the + board at . + +config MIPS_ATLAS + bool "Support for MIPS Atlas board" + help + This enables support for the QED R5231-based MIPS Atlas evaluation + board. + +config MIPS_MAGNUM_4000 + bool "Support for MIPS Magnum 4000" + help + This is a machine with a R4000 100 MHz CPU. To compile a Linux + kernel that runs on these, say Y here. For details about Linux on + the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at + . + +config MIPS_MALTA + bool "Support for MIPS Malta board" + help + This enables support for the VR5000-based MIPS Malta evaluation + board. + +config MIPS_SEAD + bool "Support for MIPS SEAD board (EXPERIMENTAL)" + depends on EXPERIMENTAL + +config MOMENCO_OCELOT + bool "Support for Momentum Ocelot board" + help + The Ocelot is a MIPS-based Single Board Computer (SBC) made by + Momentum Computer . + +config MOMENCO_OCELOT_G + bool "Support for Momentum Ocelot-G board" + help + The Ocelot is a MIPS-based Single Board Computer (SBC) made by + Momentum Computer . + +config MOMENCO_OCELOT_C + bool "Support for Momentum Ocelot-C board" + help + The Ocelot is a MIPS-based Single Board Computer (SBC) made by + Momentum Computer . + +config DDB5074 + bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)" + depends on EXPERIMENTAL + help + This enables support for the VR5000-based NEC DDB Vrc-5074 + evaluation board. + +config DDB5476 + bool "Support for NEC DDB Vrc-5476" + help + This enables support for the R5432-based NEC DDB Vrc-5476 + evaluation board. + + Features : kernel debugging, serial terminal, NFS root fs, on-board + ether port USB, AC97, PCI, PCI VGA card & framebuffer console, + IDE controller, PS2 keyboard, PS2 mouse, etc. + +config DDB5477 + bool "Support for NEC DDB Vrc-5477" + help + This enables support for the R5432-based NEC DDB Vrc-5477, + or Rockhopper/SolutionGear boards with R5432/R5500 CPUs. + + Features : kernel debugging, serial terminal, NFS root fs, on-board + ether port USB, AC97, PCI, etc. + +config DDB5477_BUS_FREQUENCY + int "bus frequency (in kHZ, 0 for auto-detect)" + depends on DDB5477 + default 0 + +config NEC_OSPREY + bool "Support for NEC Osprey board" + +config NEC_EAGLE + bool "Support for NEC Eagle/Hawk board" + +config OLIVETTI_M700 + bool "Support for Olivetti M700-10" + help + This is a machine with a R4000 100 MHz CPU. To compile a Linux + kernel that runs on these, say Y here. For details about Linux on + the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at + . + +config SGI_IP22 + bool "Support for SGI IP22 (Indy/Indigo2)" + help + This are the SGI Indy, Challenge S and Indigo2, as well as certain + OEM variants like the Tandem CMN B006S. To compile a Linux kernel + that runs on these, say Y here. + +config SGI_IP27 + bool "Support for SGI IP27 (Origin200/2000)" + depends on MIPS64 + help + This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics + workstations. To compile a Linux kernel that runs on these, say Y + here. + +#config SGI_SN0_XXL +# bool "IP27 XXL" +# depends on SGI_IP27 +# This options adds support for userspace processes upto 16TB size. +# Normally the limit is just .5TB. + +config SGI_SN0_N_MODE + bool "IP27 N-Mode" + depends on SGI_IP27 + help + The nodes of Origin 200, Origin 2000 and Onyx 2 systems can be + configured in either N-Modes which allows for more nodes or M-Mode + which allows for more memory. Your system is most probably + running in M-Mode, so you should say N here. + +config DISCONTIGMEM + bool "Discontiguous Memory Support" + depends on SGI_IP27 + help + Say Y to upport efficient handling of discontiguous physical memory, + for architectures which are either NUMA (Non-Uniform Memory Access) + or have huge holes in the physical address space for other reasons. + See for more. + +config NUMA + bool "NUMA Support" + depends on SGI_IP27 + help + Say Y to compile the kernel to support NUMA (Non-Uniform Memory + Access). This option is for configuring high-end multiprocessor + server machines. If in doubt, say N. + +config MAPPED_KERNEL + bool "Mapped kernel support" + depends on SGI_IP27 + help + Change the way a Linux kernel is loaded unto memory on a MIPS64 + machine. This is required in order to support text replication and + NUMA. If you need to undersatand it, read the source code. + +config REPLICATE_KTEXT + bool "Kernel text replication support" + depends on SGI_IP27 + help + Say Y here to enable replicating the kernel text across multiple + nodes in a NUMA cluster. This trades memory for speed. + +config REPLICATE_EXHANDLERS + bool "Exception handler replication support" + depends on SGI_IP27 + help + Say Y here to enable replicating the kernel exception handlers + across multiple nodes in a NUMA cluster. This trades memory for + speed. + +config SGI_IP32 + bool "Support for SGI IP32 (O2) (EXPERIMENTAL)" + depends on EXPERIMENTAL + help + If you want this kernel to run on SGI O2 workstation, say Y here. + +config SOC_AU1X00 + depends on MIPS32 + bool "Support for AMD/Alchemy Au1X00 SOCs" + +choice + prompt "Au1X00 SOC Type" + depends on SOC_AU1X00 + help + Say Y here to enable support for one of three AMD/Alchemy + SOCs. For additional documentation see www.amd.com. + +config SOC_AU1000 + bool "SOC_AU1000" +config SOC_AU1100 + bool "SOC_AU1100" +config SOC_AU1500 + bool "SOC_AU1500" + +endchoice + +choice + prompt "AMD/Alchemy Pb1x and Db1x board support" + depends on SOC_AU1X00 + help + These are evaluation boards built by AMD/Alchemy to + showcase their Au1X00 Internet Edge Processors. The SOC design + is based on the MIPS32 architecture running at 266/400/500MHz + with many integrated peripherals. Further information can be + found at their website, . Say Y here if you + wish to build a kernel for this platform. + +config MIPS_PB1000 + bool "PB1000 board" + depends on SOC_AU1000 + +config MIPS_PB1100 + bool "PB1100 board" + depends on SOC_AU1100 + +config MIPS_PB1500 + bool "PB1500 board" + depends on SOC_AU1500 + +config MIPS_DB1000 + bool "DB1000 board" + depends on SOC_AU1000 + +config MIPS_DB1100 + bool "DB1100 board" + depends on SOC_AU1100 + +config MIPS_DB1500 + bool "DB1500 board" + depends on SOC_AU1500 + +endchoice + +config SIBYTE_SB1xxx_SOC + bool "Support for Broadcom BCM1xxx SOCs (EXPERIMENTAL)" + depends on EXPERIMENTAL + +choice + prompt "BCM1xxx SOC Type" + depends on SIBYTE_SB1xxx_SOC + default SIBYTE_SB1250 + +config SIBYTE_SB1250 + bool "BCM1250" + +endchoice + +config SIMULATION + bool "Running under simulation" + depends on SIBYTE_SB1xxx_SOC + +config SIBYTE_CFE + bool "Booting from CFE" + depends on SIBYTE_SB1xxx_SOC + +config SIBYTE_CFE_CONSOLE + bool "Use firmware console" + depends on SIBYTE_CFE + +config SIBYTE_STANDALONE + bool + depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE + default y + +config SIBYTE_STANDALONE_RAM_SIZE + int "Memory size (in megabytes)" + depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE + default "32" + +config SIBYTE_BUS_WATCHER + bool "Support for Bus Watcher statistics" + depends on SIBYTE_SB1xxx_SOC + +config SIBYTE_SB1250_PROF + bool "Support for SB1/SOC profiling - SB1/SCD perf counters" + depends on SIBYTE_SB1xxx_SOC + +config SIBYTE_TBPROF + bool "Support for ZBbus profiling" + depends on SIBYTE_SB1xxx_SOC + +config SIBYTE_SWARM + bool "Support for SWARM board" + depends on SIBYTE_SB1250 + +config SIBYTE_BOARD + bool + depends on SIBYTE_SWARM + default y + +config SNI_RM200_PCI + bool "Support for SNI RM200 PCI" + help + The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens + Nixdorf Informationssysteme (SNI), parent company of Pyramid + Technology and now in turn merged with Fujitsu. Say Y here to + support this machine type. + +config TANBAC_TB0226 + bool "Support for TANBAC TB0226 (Mbase)" + help + The TANBAC TB0226 (Mbase) is a MIPS-based platform manufactured by TANBAC. + Please refer to about Mbase. + +config TANBAC_TB0229 + bool "Support for TANBAC TB0229 (VR4131DIMM)" + help + The TANBAC TB0229 (VR4131DIMM) is a MIPS-based platform manufactured by TANBAC. + Please refer to about VR4131DIMM. + +config TOSHIBA_JMR3927 + bool "Support for Toshiba JMR-TX3927 board" + depends on MIPS32 + +config TOSHIBA_RBTX4927 + bool "Support for Toshiba TBTX49[23]7 board" + depends on MIPS32 + +config VICTOR_MPC30X + bool "Support for Victor MP-C303/304" + +config ZAO_CAPCELLA + bool "Support for ZAO Networks Capcella" + +config RWSEM_GENERIC_SPINLOCK + bool + default y + +config RWSEM_XCHGADD_ALGORITHM + bool + +# +# Select some configuration options automatically based on user selections. +# +config ARC + bool + depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP27 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 + default y + +config GENERIC_ISA_DMA + bool + depends on SNI_RM200_PCI || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 + default y + +config CONFIG_GT64120 + bool + depends on MIPS_EV64120 || MOMENCO_OCELOT + default y + +config I8259 + bool + depends on SNI_RM200_PCI || DDB5477 || DDB5476 || DDB5074 || MIPS_MALTA || MIPS_MAGNUM_4000 || OLIVETTI_M700 || MIPS_COBALT || ACER_PICA_61 + default y + +config MIPS_JAZZ + bool + depends on MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 + default y + +config NONCOHERENT_IO + bool + depends on ZAO_CAPCELLA || VICTOR_MPC30X || TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 || SNI_RM200_PCI || SGI_IP32 || SGI_IP22 || NEC_EAGLE || NEC_OSPREY || DDB5477 || DDB5476 || DDB5074 || MOMENCO_OCELOT || MOMENCO_OCELOT_C || MOMENCO_OCELOT_G || MIPS_SEAD || MIPS_MALTA || MIPS_MAGNUM_4000 || OLIVETTI_M700 || MIPS_ATLAS || LASAT || MIPS_ITE8172 || IBM_WORKPAD || HP_LASERJET || MIPS_IVR || MIPS_EV96100 || MIPS_EV64120 || DECSTATION || MIPS_COBALT || MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000 || CASIO_E55 || ACER_PICA_61 || TANBAC_TB0226 || TANBAC_TB0229 + default y if ZAO_CAPCELLA || VICTOR_MPC30X || TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 || SNI_RM200_PCI || SGI_IP32 || SGI_IP22 || NEC_EAGLE || NEC_OSPREY || DDB5477 || DDB5476 || DDB5074 || MOMENCO_OCELOT_G || MOMENCO_OCELOT || MIPS_SEAD || MIPS_MALTA || MIPS_MAGNUM_4000 || OLIVETTI_M700 || MIPS_ATLAS || LASAT || MIPS_ITE8172 || IBM_WORKPAD || HP_LASERJET || MIPS_IVR || MIPS_EV96100 || MIPS_EV64120 || DECSTATION || MIPS_COBALT || MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000 || CASIO_E55 || ACER_PICA_61 || TANBAC_TB0226 || TANBAC_TB0229 + default n if (SIBYTE_SB1250 || SGI_IP27) + +config CPU_LITTLE_ENDIAN + bool "Generate little endian code" + default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || DECSTATION || HP_LASERJET || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || MIPS_PB1000 || MIPS_PB1100 || MIPS_PB1500 || NEC_OSPREY || NEC_EAGLE || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA + default n if BAGET_MIPS || MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927 + help + Some MIPS machines can be configured for either little or big endian + byte order. These modes require different kernels. Say Y if your + machine is little endian, N if it's a big endian machine. + +config IRQ_CPU + bool + depends on ZAO_CAPCELLA || VICTOR_MPC30X || SGI_IP22 || NEC_EAGLE || NEC_OSPREY || DDB5477 || DDB5476 || DDB5074 || IBM_WORKPAD || HP_LASERJET || DECSTATION || CASIO_E55 || TANBAC_TB0226 || TANBAC_TB0229 + default y + +config VR41XX_TIME_C + bool + depends on ZAO_CAPCELLA || VICTOR_MPC30X || NEC_EAGLE || IBM_WORKPAD || CASIO_E55 || TANBAC_TB0226 || TANBAC_TB0229 + default y + +config DUMMY_KEYB + bool + depends on ZAO_CAPCELLA || VICTOR_MPC30X || SIBYTE_SB1250 || NEC_EAGLE || NEC_OSPREY || DDB5477 || IBM_WORKPAD || CASIO_E55 || TANBAC_TB0226 || TANBAC_TB0229 + default y + +config VR41XX_COMMON + bool + depends on NEC_EAGLE || ZAO_CAPCELLA || VICTOR_MPC30X || IBM_WORKPAD || CASIO_E55 || TANBAC_TB0226 || TANBAC_TB0229 + default y + +config VRC4173 + tristate "NEC VRC4173 Support" + depends on NEC_EAGLE || VICTOR_MPC30X + +config DDB5XXX_COMMON + bool + depends on DDB5074 || DDB5476 || DDB5477 + default y + +config MIPS_BOARDS_GEN + bool + depends on MIPS_ATLAS || MIPS_MALTA || MIPS_SEAD + default y + +config ITE_BOARD_GEN + bool + depends on MIPS_IVR || MIPS_ITE8172 + default y + +config NEW_PCI + bool + depends on ZAO_CAPCELLA || VICTOR_MPC30X || TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 || NEC_EAGLE || DDB5477 || DDB5476 || DDB5074 || MIPS_ITE8172 || HP_LASERJET || MIPS_IVR || MIPS_EV96100 || MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000 || TANBAC_TB0226 || TANBAC_TB0229 + default y + +config SWAP_IO_SPACE + bool "Support for paging of anonymous memory" + depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 || SIBYTE_SB1250 || SGI_IP22 || MOMENCO_OCELOT_C || MOMENCO_OCELOT_G || MOMENCO_OCELOT || MIPS_MALTA || MIPS_ATLAS || MIPS_EV96100 || MIPS_PB1100 || MIPS_PB1000 + default y + help + This option allows you to choose whether you want to have support + for socalled swap devices or swap files in your kernel that are + used to provide more virtual memory than the actual RAM present + in your computer. If unusre say Y. + +config AU1000_USB_DEVICE + bool + depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000 + default n + +config COBALT_LCD + bool + depends on MIPS_COBALT + default y + +config MIPS_GT64120 + bool + depends on MIPS_EV64120 + default y + +config MIPS_GT96100 + bool + depends on MIPS_EV96100 + default y + help + Say Y here to support the Galileo Technology GT96100 communications + controller card. There is a web page at . + +config IT8172_CIR + bool + depends on MIPS_ITE8172 || MIPS_IVR + default y + +config IT8712 + bool + depends on MIPS_ITE8172 + default y + +config BOOT_ELF32 + bool + depends on DECSTATION || MIPS_ATLAS || MIPS_MALTA || SIBYTE_SB1250 || SGI_IP32 || SGI_IP22 || SNI_RM200_PCI + default y + +config L1_CACHE_SHIFT + int + default "4" if DECSTATION + default "5" if SGI_IP32 || SGI_IP22 || MIPS_SEAD || MIPS_MALTA || MIPS_ATLAS + default "7" if SGI_IP27 + +config ARC32 + bool + depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 + default y + +config FB + bool + depends on MIPS_MAGNUM_4000 || OLIVETTI_M700 + default y + ---help--- + The frame buffer device provides an abstraction for the graphics + hardware. It represents the frame buffer of some video hardware and + allows application software to access the graphics hardware through + a well-defined interface, so the software doesn't need to know + anything about the low-level (hardware register) stuff. + + Frame buffer devices work identically across the different + architectures supported by Linux and make the implementation of + application programs easier and more portable; at this point, an X + server exists which uses the frame buffer device exclusively. + On several non-X86 architectures, the frame buffer device is the + only way to use the graphics hardware. + + The device is accessed through special device nodes, usually located + in the /dev directory, i.e. /dev/fb*. + + You need an utility program called fbset to make full use of frame + buffer devices. Please read + and the Framebuffer-HOWTO at + for more + information. + + Say Y here and to the driver for your graphics board below if you + are compiling a kernel for a non-x86 architecture. + + If you are compiling for the x86 architecture, you can say Y if you + want to play with it, but it is not essential. Please note that + running graphical applications that directly touch the hardware + (e.g. an accelerated X server) and that are not frame buffer + device-aware may cause unexpected results. If unsure, say N. + +config FB_G364 + bool + depends on MIPS_MAGNUM_4000 || OLIVETTI_M700 + default y + +config HAVE_STD_PC_SERIAL_PORT + bool + depends on DDB5476 || DDB5074 || MIPS_MALTA + default y + +config VR4181 + bool + depends on NEC_OSPREY + default y + +config ARC_CONSOLE + bool "ARC console support" + depends on SGI_IP22 || SNI_RM200_PCI + +config ARC_MEMORY + bool + depends on SNI_RM200_PCI || SGI_IP32 + default y + +config ARC_PROMLIB + bool + depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP22 + default y + +config BOARD_SCACHE + bool + depends on MIPS_EV96100 || MOMENCO_OCELOT || SGI_IP22 + default y + +config ARC64 + bool + depends on SGI_IP27 + default y + +config BOOT_ELF64 + bool + depends on SGI_IP27 + default y + +#config MAPPED_PCI_IO y +# bool +# depends on SGI_IP27 +# default y + +config QL_ISP_A64 + bool + depends on SGI_IP27 + default y + +config TOSHIBA_BOARDS + bool + depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 + default y + +config TANBAC_TB0219 + bool "Added TANBAC TB0219 Base board support" + depends on TANBAC_TB0229 + +endmenu + + +menu "CPU selection" + +choice + prompt "CPU type" + default CPU_R4X00 + +config CPU_MIPS32 + bool "MIPS32" + +config CPU_MIPS64 + bool "MIPS64" + +config CPU_R3000 + bool "R3000" + depends on MIPS32 + help + Please make sure to pick the right CPU type. Linux/MIPS is not + designed to be generic, i.e. Kernels compiled for R3000 CPUs will + *not* work on R4000 machines and vice versa. However, since most + of the supported machines have an R4000 (or similar) CPU, R4x00 + might be a safe bet. If the resulting kernel does not work, + try to recompile with R3000. + +config CPU_TX39XX + bool "R39XX" + depends on MIPS32 + +config CPU_VR41XX + bool "R41xx" + help + The options selects support for the NEC VR41xx series of processors. + Only choose this option if you have one of these processors as a + kernel built with this option will not run on any other type of + processor or vice versa. + +config CPU_R4300 + bool "R4300" + help + MIPS Technologies R4300-series processors. + +config CPU_R4X00 + bool "R4x00" + help + MIPS Technologies R4000-series processors other than 4300, including + the R4000, R4400, R4600, and 4700. + +config CPU_TX49XX + bool "R49XX" + +config CPU_R5000 + bool "R5000" + help + MIPS Technologies R5000-series processors other than the Nevada. + +config CPU_R5432 + bool "R5432" + +config CPU_R6000 + bool "R6000" + depends on MIPS32 && EXPERIMENTAL + help + MIPS Technologies R6000 and R6000A series processors. Note these + processors are extremly rare and the support for them is incomplete. + +config CPU_NEVADA + bool "R52xx" + help + MIPS Technologies R52x0-series ("Nevada") processors. + +config CPU_R8000 + bool "R8000" + depends on MIPS64 && EXPERIMENTAL + help + MIPS Technologies R8000 processors. Note these processors are + uncommon and the support for them is incomplete. + +config CPU_R10000 + bool "R10000" + help + MIPS Technologies R10000-series processors. + +config CPU_RM7000 + bool "RM7000" + +config CPU_SB1 + bool "SB1" + +endchoice + +config R5000_CPU_SCACHE + bool + depends on CPU_NEVADA || CPU_R5000 + default y if SGI_IP32 || LASAT + +config BOARD_SCACHE + bool + depends on CPU_NEVADA || CPU_R4X00 || CPU_R5000 + default y if SGI_IP22 || (SGI_IP32 && CPU_R5000) || R5000_CPU_SCACHE + +config CPU_HAS_PREFETCH + bool "Enable prefetches" if CPU_SB1 && !CPU_SB1_PASS_2 + default y if CPU_RM7000 || CPU_MIPS64 || CPU_MIPS32 + +config VTAG_ICACHE + bool "Support for Virtual Tagged I-cache" if CPU_MIPS64 || CPU_MIPS32 + default y if CPU_SB1 + +choice + prompt "SB1 Pass" + depends on CPU_SB1 + default CPU_SB1_PASS_1 + +config CPU_SB1_PASS_1 + bool "Pass1" + +config CPU_SB1_PASS_2 + bool "Pass2" + +config CPU_SB1_PASS_2_2 + bool "Pass2.2" + +endchoice + +config SB1_PASS_1_WORKAROUNDS + bool + depends on CPU_SB1_PASS_1 + default y + +config SB1_PASS_2_WORKAROUNDS + bool + depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2) + default y + +# Avoid prefetches on Pass 2 (before 2.2) +# XXXKW for now, let 2.2 use same WORKAROUNDS flag as pre-2.2 +config SB1_CACHE_ERROR + bool "Support for SB1 Cache Error handler" + depends on CPU_SB1 + +config SB1_CERR_IGNORE_RECOVERABLE + bool "Ignore recoverable cache errors" + depends on SB1_CACHE_ERROR + +config SB1_CERR_SPIN + bool "Spin instead of running handler" + depends on SB1_CACHE_ERROR + +config 64BIT_PHYS_ADDR + bool "Support for 64-bit physical address space" + depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && MIPS32 + +config CPU_ADVANCED + bool "Override CPU Options" + depends on MIPS32 + help + Saying yes here allows you to select support for various features + your CPU may or may not have. Most people should say N here. + +config CPU_HAS_LLSC + bool "ll/sc Instructions available" if CPU_ADVANCED + default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX + help + MIPS R4000 series and later provide the Load Linked (ll) + and Store Conditional (sc) instructions. More information is + available at . + + Say Y here if your CPU has the ll and sc instructions. Say Y here + for better performance, N if you don't know. You must say Y here + for multiprocessor machines. + +config CPU_HAS_LLDSCD + bool "lld/scd Instructions available" if CPU_ADVANCED + default y if !CPU_ADVANCED && !CPU_R3000 && !CPU_VR41XX && !CPU_TX39XX && !CPU_MIPS32 + help + Say Y here if your CPU has the lld and scd instructions, the 64-bit + equivalents of ll and sc. Say Y here for better performance, N if + you don't know. You must say Y here for multiprocessor machines. + +config CPU_HAS_WB + bool "Writeback Buffer available" if CPU_ADVANCED + default y if !CPU_ADVANCED && (CPU_R3000 || CPU_VR41XX || CPU_TX39XX) && DECSTATION + help + Say N here for slightly better performance. You must say Y here for + machines which require flushing of write buffers in software. Saying + Y is the safe option; N may result in kernel malfunction and crashes. + +config CPU_HAS_SYNC + bool + depends on !CPU_R3000 + default y + +# +# - Highmem only makes sense for the 32-bit kernel. +# - The current highmem code will only work properly on physically indexed +# caches such as R3000, SB1, R7000 or those that look like they're virtually +# indexed such as R4000/R4400 SC and MC versions or R10000. So for the +# moment we protect the user and offer the highmem option only on machines +# where it's known to be safe. This will not offer highmem on a few systems +# such as MIPS32 and MIPS64 CPUs which may have virtual and physically +# indexed CPUs but we're playing safe. +# - We should not offer highmem for system of which we already know that they +# don't have memory configurations that could gain from highmem support in +# the kernel because they don't support configurations with RAM at physical +# addresses > 0x20000000. +# +config HIGHMEM + bool "High Memory Support" + depends on MIPS32 && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_R10000) && !(BAGET_MIPS || DECSTATION) + +config SMP + bool "Multi-Processing support" + depends on SIBYTE_SB1xxx_SOC && SIBYTE_SB1250 && !SIBYTE_STANDALONE || SGI_IP27 + ---help--- + This enables support for systems with more than one CPU. If you have + a system with only one CPU, like most personal computers, say N. If + you have a system with more than one CPU, say Y. + + If you say N here, the kernel will run on single and multiprocessor + machines, but will use only one CPU of a multiprocessor machine. If + you say Y here, the kernel will run on many, but not all, + singleprocessor machines. On a singleprocessor machine, the kernel + will run faster if you say N here. + + People using multiprocessor machines who say Y here should also say + Y to "Enhanced Real Time Clock Support", below. + + See also the , + and the SMP-HOWTO available at + . + + If you don't know what to do here, say N. + +config NR_CPUS + int "Maximum number of CPUs (2-32)" + depends on SMP + default "32" + help + This allows you to specify the maximum number of CPUs which this + kernel will support. The maximum supported value is 32 and the + minimum value which makes sense is 2. + + This is purely to save memory - each supported CPU adds + approximately eight kilobytes to the kernel image. + +config PREEMPT + bool "Preemptible Kernel" + help + This option reduces the latency of the kernel when reacting to + real-time or interactive events by allowing a low priority process to + be preempted even if it is in kernel mode executing a system call. + This allows applications to run more reliably even when the system is + under load. + +config KALLSYMS + bool "Load all symbols for debugging/kksymoops" + help + Say Y here to let the kernel print out symbolic crash information and + symbolic stack backtraces. This increases the size of the kernel + somewhat, as all symbols have to be loaded into the kernel image. + +config DEBUG_SPINLOCK_SLEEP + bool "Sleep-inside-spinlock checking" + help + If you say Y here, various routines which may sleep will become very + noisy if they are called with a spinlock held. + +config RTC_DS1742 + bool "DS1742 BRAM/RTC support" + depends on TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 + +config MIPS_INSANE_LARGE + bool "Support for large 64-bit configurations" + depends on CPU_R10000 && MIPS64 + help + MIPS R10000 does support a 44 bit / 16TB address space as opposed to + previous 64-bit processors which only supported 40 bit / 1TB. If you + need processes of more than 1TB virtual address space, say Y here. + This will result in additional memory usage, so it is not + recommended for normal users. + +config RWSEM_GENERIC_SPINLOCK + bool + default y + +endmenu + +menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)" + +config PCI + bool "Support for PCI controller" + depends on MIPS_DB1000 || DDB5074 || DDB5476 || DDB5477 || HP_LASERJET || LASAT || MIPS_IVR || MIPS_ATLAS || MIPS_COBALT || MIPS_EV64120 || MIPS_EV96100 || MIPS_ITE8172 || MIPS_MALTA || MOMENCO_OCELOT || MOMENCO_OCELOT_C || MOMENCO_OCELOT_G || MIPS_PB1000 || MIPS_PB1100 || MIPS_PB1500 || NEC_EAGLE || SGI_IP27 || SGI_IP32 || SIBYTE_SB1250 || SNI_RM200_PCI || TANBAC_TB0226 || TANBAC_TB0229 || TOSHIBA_JMR3927 || TOSHIBA_RBTX4927 || VICTOR_MPC30X || ZAO_CAPCELLA + help + Find out whether you have a PCI motherboard. PCI is the name of a + bus system, i.e. the way the CPU talks to the other stuff inside + your box. Other bus systems are ISA, EISA, or VESA. If you have PCI, + say Y, otherwise N. + + The PCI-HOWTO, available from + , contains valuable + information about which PCI hardware does work under Linux and which + doesn't. + +source "drivers/pci/Kconfig" + +config ISA + bool "ISA bus support" + depends on ACER_PICA_61 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || SNI_RM200_PCI + default y if TOSHIBA_RBTX4927 || DDB5476 || DDB5074 || IBM_WORKPAD || CASIO_E55 + help + Find out whether you have ISA slots on your motherboard. ISA is the + name of a bus system, i.e. the way the CPU talks to the other stuff + inside your box. Other bus systems are PCI, EISA, or VESA. ISA is + an older system, now being displaced by PCI; newer boards don't + support it. If you have ISA, say Y, otherwise N. + +# +# The SCSI bits are needed to get the SCSI code to link ... +# +config GENERIC_ISA_DMA + bool + default y if ACER_PICA_61 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || SNI_RM200_PCI || SCSI + +config EISA + bool "EISA support" + depends on ISA && (SGI_IP22 || SNI_RM200_PCI) + ---help--- + The Extended Industry Standard Architecture (EISA) bus was + developed as an open alternative to the IBM MicroChannel bus. + + The EISA bus provided some of the features of the IBM MicroChannel + bus while maintaining backward compatibility with cards made for + the older ISA bus. The EISA bus saw limited use between 1988 and + 1995 when it was made obsolete by the PCI bus. + + Say Y here if you are building a kernel for an EISA-based machine. + + Otherwise, say N. + +source "drivers/eisa/Kconfig" + +config TC + bool "TURBOchannel support" + depends on DECSTATION + help + TurboChannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS + processors. Documentation on writing device drivers for TurboChannel + is available at: + . + +#config ACCESSBUS +# bool "Access.Bus support" +# depends on TC + +config MMU + bool + default y + +config MCA + bool + +config SBUS + bool + +config HOTPLUG + bool "Support for hot-pluggable devices" + ---help--- + Say Y here if you want to plug devices into your computer while + the system is running, and be able to use them quickly. In many + cases, the devices can likewise be unplugged at any time too. + + One well known example of this is PCMCIA- or PC-cards, credit-card + size devices such as network cards, modems or hard drives which are + plugged into slots found on all modern laptop computers. Another + example, used on modern desktops as well as laptops, is USB. + + Enable HOTPLUG and KMOD, and build a modular kernel. Get agent + software (at ) and install it. + Then your kernel will automatically call out to a user mode "policy + agent" (/sbin/hotplug) to load modules and set up software needed + to use devices as you hotplug them. + +source "drivers/pcmcia/Kconfig" + +source "drivers/pci/hotplug/Kconfig" + +endmenu + +menu "Executable file formats" + +config KCORE_ELF + bool + default y + ---help--- + If you enabled support for /proc file system then the file + /proc/kcore will contain the kernel core image. This can be used + in gdb: + + $ cd /usr/src/linux ; gdb vmlinux /proc/kcore + + You have two choices here: ELF and A.OUT. Selecting ELF will make + /proc/kcore appear in ELF core format as defined by the Executable + and Linking Format specification. Selecting A.OUT will choose the + old "a.out" format which may be necessary for some old versions + of binutils or on some architectures. + + This is especially useful if you have compiled the kernel with the + "-g" option to preserve debugging information. It is mainly used + for examining kernel data structures on the live kernel so if you + don't understand what this means or are not a kernel hacker, just + leave it at its default value ELF. + +config KCORE_AOUT + bool + +source "fs/Kconfig.binfmt" + +config BINFMT_IRIX + bool "Include IRIX binary compatibility" + depends on !CPU_LITTLE_ENDIAN && MIPS32 + +config MIPS32_COMPAT + bool "Kernel support for Linux/MIPS 32-bit binary compatibility" + depends on MIPS64 + help + Select this option if you want Linux/MIPS 32-bit binary + compatibility. Since all software available for Linux/MIPS is + currently 32-bit you should say Y here. + +config COMPAT + bool + depends on MIPS32_COMPAT + default y + +config MIPS32_O32 + bool "Kernel support for o32 binaries" + depends on MIPS32_COMPAT + help + Select this option if you want to run o32 binaries. These are pure + 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of + existing binaries are in this format. + + If unsure, say Y. + +config MIPS32_N32 + bool "Kernel support for n32 binaries" + depends on MIPS32_COMPAT + help + Select this option if you want to run n32 binaries. These are + 64-bit binaries using 32-bit quantities for addressing and certain + data that would normally be 64-bit. They are used in special + cases. + + If unsure, say N. + +config BINFMT_ELF32 + bool + default y if MIPS32_O32 || MIPS32_N32 + +config PM + bool "Power Management support (EXPERIMENTAL)" + depends on EXPERIMENTAL && SOC_AU1X00 + +endmenu + +source "drivers/mtd/Kconfig" + +source "drivers/parport/Kconfig" + +source "drivers/pnp/Kconfig" + +source "drivers/base/Kconfig" + +source "drivers/block/Kconfig" + + +menu "MIPS initrd options" + depends on BLK_DEV_INITRD + +config EMBEDDED_RAMDISK + bool "Embed root filesystem ramdisk into the kernel" + +config EMBEDDED_RAMDISK_IMAGE + string "Filename of gziped ramdisk image" + depends on EMBEDDED_RAMDISK + default "ramdisk.gz" + help + This is the filename of the ramdisk image to be built into the + kernel. Relative pathnames are relative to arch/mips/ramdisk/. + The ramdisk image is not part of the kernel distribution; you must + provide one yourself. + +endmenu + +source "drivers/ide/Kconfig" + +source "drivers/scsi/Kconfig" + +source "drivers/cdrom/Kconfig" + +source "drivers/md/Kconfig" + +source "drivers/message/fusion/Kconfig" + +source "drivers/ieee1394/Kconfig" + +source "drivers/message/i2o/Kconfig" + +source "net/Kconfig" + +source "net/ax25/Kconfig" + +source "net/irda/Kconfig" + +source "drivers/isdn/Kconfig" + +source "drivers/telephony/Kconfig" + +# +# input before char - char/joystick depends on it. As does USB. +# +source "drivers/input/Kconfig" + +source "drivers/char/Kconfig" + +#source drivers/misc/Config.in + +source "drivers/media/Kconfig" + +source "fs/Kconfig" + +source "drivers/video/Kconfig" + + +menu "Sound" + +config SOUND + tristate "Sound card support" + ---help--- + If you have a sound card in your computer, i.e. if it can say more + than an occasional beep, say Y. Be sure to have all the information + about your sound card and its configuration down (I/O port, + interrupt and DMA channel), because you will be asked for it. + + You want to read the Sound-HOWTO, available from + . General information about + the modular sound system is contained in the files + . The file + contains some slightly + outdated but still useful information as well. + + If you have a PnP sound card and you want to configure it at boot + time using the ISA PnP tools (read + ), then you need to + compile the sound card support as a module ( = code which can be + inserted in and removed from the running kernel whenever you want) + and load that module after the PnP configuration is finished. To do + this, say M here and read as well + as ; the module will be + called soundcore. + + I'm told that even without a sound card, you can make your computer + say more than an occasional beep, by programming the PC speaker. + Kernel patches and supporting utilities to do that are in the pcsp + package, available at . + +source "sound/Kconfig" + +endmenu + +source "drivers/usb/Kconfig" + +source "net/bluetooth/Kconfig" + + +menu "Kernel hacking" + +config CROSSCOMPILE + bool "Are you using a crosscompiler" + help + Say Y here if you are compiling the kernel on a different + architecture than the one it is intended to run on. + +config DEBUG_KERNEL + bool "Kernel debugging" + +config KGDB + bool "Remote GDB kernel debugging" + depends on DEBUG_KERNEL + help + If you say Y here, it will be possible to remotely debug the MIPS + kernel using gdb. This enlarges your kernel image disk size by + several megabytes and requires a machine with more than 16 MB, + better 32 MB RAM to avoid excessive linking time. This is only + useful for kernel hackers. If unsure, say N. + +config GDB_CONSOLE + bool "Console output to GDB" + depends on KGDB + help + If you are using GDB for remote debugging over a serial port and + would like kernel messages to be formatted into GDB $O packets so + that GDB prints them as program output, say 'Y'. + +config RUNTIME_DEBUG + bool "Enable run-time debugging" + depends on DEBUG_KERNEL + help + If you say Y here, some debugging macros will do run-time checking. + If you say N here, those macros will mostly turn to no-ops. See + include/asm-mips/debug.h for debuging macros. + If unsure, say N. + + +config MAGIC_SYSRQ + bool "Magic SysRq key" + depends on DEBUG_KERNEL + help + If you say Y here, you will have some control over the system even + if the system crashes for example during kernel debugging (e.g., you + will be able to flush the buffer cache to disk, reboot the system + immediately or dump some status information). This is accomplished + by pressing various keys while holding SysRq (Alt+PrintScreen). It + also works on a serial console (on PC hardware at least), if you + send a BREAK and then within 5 seconds a command keypress. The + keys are documented in . Don't say Y + unless you really know what this hack does. + +config MIPS_UNCACHED + bool "Run uncached" + depends on DEBUG_KERNEL && !SMP && !SGI_IP27 + help + If you say Y here there kernel will disable all CPU caches. This will + reduce the system's performance dramatically but can help finding + otherwise hard to track bugs. It can also useful if you're doing + hardware debugging with a logic analyzer and need to see all traffic + on the bus. + +config DEBUG_HIGHMEM + bool "Highmem debugging" + depends on DEBUG_KERNEL && HIGHMEM + +endmenu + +source "security/Kconfig" + +source "crypto/Kconfig" + +source "lib/Kconfig" --- linux-2.5.73/arch/mips/kernel/branch.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/branch.c 2003-06-27 15:56:23.000000000 -0700 @@ -16,7 +16,6 @@ #include #include #include -#include #include /* @@ -164,10 +163,10 @@ int __compute_return_epc(struct pt_regs * And now the FPA/cp1 branch instructions. */ case cop1_op: - if(!(mips_cpu.options & MIPS_CPU_FPU)) + if (!cpu_has_fpu) fcr31 = current->thread.fpu.soft.sr; else - asm ("cfc1\t%0,$31":"=r" (fcr31)); + asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); bit = (insn.i_format.rt >> 2); bit += (bit != 0); bit += 23; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/kernel/cpu-probe.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,509 @@ +#include +#include +#include +#include +#include +#include +#include + +/* + * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, + * the implementation of the "wait" feature differs between CPU families. This + * points to the function that implements CPU specific wait. + * The wait instruction stops the pipeline and reduces the power consumption of + * the CPU very much. + */ +void (*cpu_wait)(void) = NULL; + +static void r3081_wait(void) +{ + unsigned long cfg = read_c0_conf(); + write_c0_conf(cfg | R30XX_CONF_HALT); +} + +static void r39xx_wait(void) +{ + unsigned long cfg = read_c0_conf(); + write_c0_conf(cfg | TX39_CONF_HALT); +} + +static void r4k_wait(void) +{ + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void au1k_wait(void) +{ +#ifdef CONFIG_PM + /* using the wait instruction makes CP0 counter unusable */ + __asm__(".set\tmips3\n\t" + "wait\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + "nop\n\t" + ".set\tmips0"); +#else + __asm__("nop\n\t" + "nop"); +#endif +} + +static inline void check_wait(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + + printk("Checking for 'wait' instruction... "); + switch (c->cputype) { + case CPU_R3081: + case CPU_R3081E: + cpu_wait = r3081_wait; + printk(" available.\n"); + break; + case CPU_TX3927: + cpu_wait = r39xx_wait; + printk(" available.\n"); + break; + case CPU_R4200: +/* case CPU_R4300: */ + case CPU_R4600: + case CPU_R4640: + case CPU_R4650: + case CPU_R4700: + case CPU_R5000: + case CPU_NEVADA: + case CPU_RM7000: + case CPU_TX49XX: + case CPU_4KC: + case CPU_4KEC: + case CPU_4KSC: + case CPU_5KC: +/* case CPU_20KC:*/ + cpu_wait = r4k_wait; + printk(" available.\n"); + break; + case CPU_AU1000: + case CPU_AU1100: + case CPU_AU1500: + cpu_wait = au1k_wait; + printk(" available.\n"); + break; + default: + printk(" unavailable.\n"); + break; + } +} + +void __init check_bugs(void) +{ + check_wait(); +} + +/* + * Probe whether cpu has config register by trying to play with + * alternate cache bit and see whether it matters. + * It's used by cpu_probe to distinguish between R3000A and R3081. + */ +static inline int cpu_has_confreg(void) +{ +#ifdef CONFIG_CPU_R3000 + extern unsigned long r3k_cache_size(unsigned long); + unsigned long size1, size2; + unsigned long cfg = read_c0_conf(); + + size1 = r3k_cache_size(ST0_ISC); + write_c0_conf(cfg ^ R30XX_CONF_AC); + size2 = r3k_cache_size(ST0_ISC); + write_c0_conf(cfg); + return size1 != size2; +#else + return 0; +#endif +} + +/* + * Get the FPU Implementation/Revision. + */ +static inline unsigned long cpu_get_fpu_id(void) +{ + unsigned long tmp, fpu_id; + + tmp = read_c0_status(); + __enable_fpu(); + fpu_id = read_32bit_cp1_register(CP1_REVISION); + write_c0_status(tmp); + return fpu_id; +} + +/* + * Check the CPU has an FPU the official way. + */ +static inline int __cpu_has_fpu(void) +{ + return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); +} + +#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \ + | MIPS_CPU_COUNTER | MIPS_CPU_CACHE_CDEX) + +__init void cpu_probe(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned long config0 = read_c0_config(); + unsigned long config1; + + c->processor_id = PRID_IMP_UNKNOWN; + c->fpu_id = FPIR_IMP_NONE; + c->cputype = CPU_UNKNOWN; + + if (config0 & (1 << 31)) { + /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */ + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | + MIPS_CPU_LLSC; + config1 = read_c0_config1(); + if (config1 & (1 << 3)) + c->options |= MIPS_CPU_WATCH; + if (config1 & (1 << 2)) + c->options |= MIPS_CPU_MIPS16; + if (config1 & (1 << 1)) + c->options |= MIPS_CPU_EJTAG; + if (config1 & 1) { + c->options |= MIPS_CPU_FPU; + c->options |= MIPS_CPU_32FPR; + } + c->scache.flags = MIPS_CACHE_NOT_PRESENT; + + c->tlbsize = ((config1 >> 25) & 0x3f) + 1; + } + + c->processor_id = read_c0_prid(); + switch (c->processor_id & 0xff0000) { + case PRID_COMP_LEGACY: + switch (c->processor_id & 0xff00) { + case PRID_IMP_R2000: + c->cputype = CPU_R2000; + c->isa_level = MIPS_CPU_ISA_I; + c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX | + MIPS_CPU_LLSC; + if (__cpu_has_fpu()) + c->options |= MIPS_CPU_FPU; + c->tlbsize = 64; + break; + case PRID_IMP_R3000: + if ((c->processor_id & 0xff) == PRID_REV_R3000A) + if (cpu_has_confreg()) + c->cputype = CPU_R3081E; + else + c->cputype = CPU_R3000A; + else + c->cputype = CPU_R3000; + c->isa_level = MIPS_CPU_ISA_I; + c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX | + MIPS_CPU_LLSC; + if (__cpu_has_fpu()) + c->options |= MIPS_CPU_FPU; + c->tlbsize = 64; + break; + case PRID_IMP_R4000: + if ((c->processor_id & 0xff) >= PRID_REV_R4400) + c->cputype = CPU_R4400SC; + else + c->cputype = CPU_R4000SC; + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_WATCH | MIPS_CPU_VCE | + MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + case PRID_IMP_VR41XX: + switch (c->processor_id & 0xf0) { +#ifndef CONFIG_VR4181 + case PRID_REV_VR4111: + c->cputype = CPU_VR4111; + break; +#else + case PRID_REV_VR4181: + c->cputype = CPU_VR4181; + break; +#endif + case PRID_REV_VR4121: + c->cputype = CPU_VR4121; + break; + case PRID_REV_VR4122: + if ((c->processor_id & 0xf) < 0x3) + c->cputype = CPU_VR4122; + else + c->cputype = CPU_VR4181A; + break; + case PRID_REV_VR4131: + c->cputype = CPU_VR4131; + break; + default: + printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); + c->cputype = CPU_VR41XX; + break; + } + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS; + c->tlbsize = 32; + break; + case PRID_IMP_R4300: + c->cputype = CPU_R4300; + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; + c->tlbsize = 32; + break; + case PRID_IMP_R4600: + c->cputype = CPU_R4600; + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + #if 0 + case PRID_IMP_R4650: + /* + * This processor doesn't have an MMU, so it's not + * "real easy" to run Linux on it. It is left purely + * for documentation. Commented out because it shares + * it's c0_prid id number with the TX3900. + */ + c->cputype = CPU_R4650; + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + #endif + case PRID_IMP_TX39: + c->isa_level = MIPS_CPU_ISA_I; + c->options = MIPS_CPU_TLB; + + if ((c->processor_id & 0xf0) == + (PRID_REV_TX3927 & 0xf0)) { + c->cputype = CPU_TX3927; + c->tlbsize = 64; + } else { + switch (c->processor_id & 0xff) { + case PRID_REV_TX3912: + c->cputype = CPU_TX3912; + c->tlbsize = 32; + break; + case PRID_REV_TX3922: + c->cputype = CPU_TX3922; + c->tlbsize = 64; + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } + } + break; + case PRID_IMP_R4700: + c->cputype = CPU_R4700; + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + case PRID_IMP_TX49: + c->cputype = CPU_TX49XX; + c->isa_level = MIPS_CPU_ISA_III; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + case PRID_IMP_R5000: + c->cputype = CPU_R5000; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + case PRID_IMP_R5432: + c->cputype = CPU_R5432; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_WATCH | MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + case PRID_IMP_R5500: + c->cputype = CPU_R5500; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_WATCH | MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + case PRID_IMP_NEVADA: + c->cputype = CPU_NEVADA; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_DIVEC | MIPS_CPU_LLSC; + c->tlbsize = 48; + break; + case PRID_IMP_R6000: + c->cputype = CPU_R6000; + c->isa_level = MIPS_CPU_ISA_II; + c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | + MIPS_CPU_LLSC; + c->tlbsize = 32; + break; + case PRID_IMP_R6000A: + c->cputype = CPU_R6000A; + c->isa_level = MIPS_CPU_ISA_II; + c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | + MIPS_CPU_LLSC; + c->tlbsize = 32; + break; + case PRID_IMP_RM7000: + c->cputype = CPU_RM7000; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; + /* + * Undocumented RM7000: Bit 29 in the info register of + * the RM7000 v2.0 indicates if the TLB has 48 or 64 + * entries. + * + * 29 1 => 64 entry JTLB + * 0 => 48 entry JTLB + */ + c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; + break; + case PRID_IMP_R8000: + c->cputype = CPU_R8000; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_LLSC; + c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ + break; + case PRID_IMP_R10000: + c->cputype = CPU_R10000; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_COUNTER | MIPS_CPU_WATCH | + MIPS_CPU_LLSC; + c->tlbsize = 64; + break; + case PRID_IMP_R12000: + c->cputype = CPU_R12000; + c->isa_level = MIPS_CPU_ISA_IV; + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + MIPS_CPU_FPU | MIPS_CPU_32FPR | + MIPS_CPU_COUNTER | MIPS_CPU_WATCH | + MIPS_CPU_LLSC; + c->tlbsize = 64; + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } + break; + case PRID_COMP_MIPS: + switch (c->processor_id & 0xff00) { + case PRID_IMP_4KC: + c->cputype = CPU_4KC; + c->isa_level = MIPS_CPU_ISA_M32; + break; + case PRID_IMP_4KEC: + c->cputype = CPU_4KEC; + c->isa_level = MIPS_CPU_ISA_M32; + break; + case PRID_IMP_4KSC: + c->cputype = CPU_4KSC; + c->isa_level = MIPS_CPU_ISA_M32; + break; + case PRID_IMP_5KC: + c->cputype = CPU_5KC; + c->isa_level = MIPS_CPU_ISA_M64; + break; + case PRID_IMP_20KC: + c->cputype = CPU_20KC; + c->isa_level = MIPS_CPU_ISA_M64; + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } + break; + case PRID_COMP_ALCHEMY: + switch (c->processor_id & 0xff00) { + case PRID_IMP_AU1_REV1: + case PRID_IMP_AU1_REV2: + switch ((c->processor_id >> 24) & 0xff) { + case 0: + c->cputype = CPU_AU1000; + break; + case 1: + c->cputype = CPU_AU1500; + break; + case 2: + c->cputype = CPU_AU1100; + break; + default: + panic("Unknown Au Core!"); + break; + } + c->isa_level = MIPS_CPU_ISA_M32; + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } + break; + case PRID_COMP_SIBYTE: + switch (c->processor_id & 0xff00) { + case PRID_IMP_SB1: + c->cputype = CPU_SB1; + c->isa_level = MIPS_CPU_ISA_M64; + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | + MIPS_CPU_MCHECK | MIPS_CPU_EJTAG | + MIPS_CPU_WATCH | MIPS_CPU_LLSC; +#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS + /* FPU in pass1 is known to have issues. */ + c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; +#endif + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } + break; + + case PRID_COMP_SANDCRAFT: + switch (c->processor_id & 0xff00) { + case PRID_IMP_SR71000: + c->cputype = CPU_SR71000; + c->isa_level = MIPS_CPU_ISA_M64; + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + MIPS_CPU_4KTLB | MIPS_CPU_FPU | + MIPS_CPU_COUNTER | MIPS_CPU_MCHECK; + c->scache.ways = 8; + c->tlbsize = 64; + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } + break; + default: + c->cputype = CPU_UNKNOWN; + c->tlbsize = ((config1 >> 25) & 0x3f) + 1; + } + if (c->options & MIPS_CPU_FPU) + c->fpu_id = cpu_get_fpu_id(); +} + +__init void cpu_report(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + + printk("CPU revision is: %08x\n", c->processor_id); + if (c->options & MIPS_CPU_FPU) + printk("FPU revision is: %08x\n", c->fpu_id); +} --- linux-2.5.73/arch/mips/kernel/entry.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/entry.S 2003-06-27 15:56:23.000000000 -0700 @@ -1,5 +1,4 @@ /* -/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. @@ -9,79 +8,155 @@ * Copyright (C) 2001 MIPS Technologies, Inc. */ #include +#include #include #include #include -#include +#include #include #include #include -#include +#include +#include #include #include -#include #include #include #include +#include -/* This duplicates the definition from */ -#define PT_TRACESYS 0x00000002 /* tracing system calls */ +#ifdef CONFIG_PREEMPT + .macro preempt_stop + cli + .endm + .macro init_ret_intr temp + mfc0 t0, CP0_STATUS # cli + ori t0, t0, 1 + xori t0, t0, 1 + mtc0 t0, CP0_STATUS + SSNOP; SSNOP; SSNOP + + lw \temp, TI_PRE_COUNT($28) + subu \temp, \temp, 1 + sw \temp, TI_PRE_COUNT($28) + .endm +#else + .macro preempt_stop + .endm + + .macro init_ret_intr + .endm + +#define resume_kernel restore_all +#endif .text - .align 4 + .align 5 .set push .set reorder -EXPORT(ret_from_fork) - move a0, v0 # prev - jal schedule_tail -#error lw t0, TASK_PTRACE($28) # syscall tracing enabled? - andi t0, PT_TRACESYS - bnez t0, tracesys_exit - j ret_from_sys_call - -tracesys_exit: jal syscall_trace - b ret_from_sys_call - -EXPORT(ret_from_irq) -EXPORT(ret_from_exception) +FEXPORT(ret_from_irq) +FEXPORT(ret_from_exception) lw t0, PT_STATUS(sp) # returning to kernel mode? andi t0, t0, KU_USER - bnez t0, ret_from_sys_call + beqz t0, resume_kernel + +FEXPORT(resume_userspace) + mfc0 t0, CP0_STATUS # make sure we dont miss an + ori t0, t0, 1 # interrupt setting need_resched + xori t0, t0, 1 # between sampling and return + mtc0 t0, CP0_STATUS + SSNOP; SSNOP; SSNOP + + LONG_L a2, TI_FLAGS($28) + andi a2, _TIF_WORK_MASK # current->work (ignoring + # syscall_trace) + bnez a2, work_pending j restore_all -reschedule: jal schedule +#ifdef CONFIG_PREEMPT +ENTRY(resume_kernel) + lw t0, TI_PRE_COUNT($28) + bnez t0, restore_all + LONG_L t0, TI_FLAGS($28) + andi t1, t0, _TIF_NEED_RESCHED + beqz restore_all +#ifdef CONFIG_SMP + lw t0, TI_CPU($28) + la t1, irq_stat + sll t0, 5 # *sizeof(irq_cpustat_t) + addu t0, t1 + lw t1, local_bh_count(t0) + addl t0, local_irq_count(t0) +#else + lw t1, irq_stat+local_bh_count + addl t0, irq_stat+local_irq_count +#endif + addu t0, t1 + bnez t0, restore_all + lw t0, TI_PRE_COUNT($28) + addiu t0, 1 + sw t0, TI_PRE_COUNT($28) + sti + movl t0, TI_TASK($28) # ti->task + sw zero, TASK_STATE(t0) # current->state = TASK_RUNNING + jal schedule + j ret_from_intr +#endif -EXPORT(ret_from_sys_call) - .type ret_from_irq,@function +FEXPORT(ret_from_fork) + jal schedule_tail - mfc0 t0, CP0_STATUS # need_resched and signals atomic test - ori t0, t0, 1 - xori t0, t0, 1 +FEXPORT(syscall_exit) + mfc0 t0, CP0_STATUS # make sure need_resched and + ori t0, t0, 1 # signals dont change between + xori t0, t0, 1 # sampling and return mtc0 t0, CP0_STATUS - nop; nop; nop + SSNOP; SSNOP; SSNOP -#error lw v0, TASK_NEED_RESCHED($28) -#error lw v1, TASK_SIGPENDING($28) - bnez v0, reschedule - bnez v1, signal_return -restore_all: .set noat + LONG_L a2, TI_FLAGS($28) # current->work + bnez a2, syscall_exit_work + +FEXPORT(restore_all) + .set noat RESTORE_ALL_AND_RET .set at -/* Put this behind restore_all for the sake of the branch prediction. */ -signal_return: - .type signal_return, @function - - mfc0 t0, CP0_STATUS - ori t0, t0, 1 +FEXPORT(work_pending) + andi t0, a2, _TIF_NEED_RESCHED + bnez t0, work_notifysig +work_resched: + jal schedule + + mfc0 t0, CP0_STATUS # make sure need_resched and + ori t0, t0, 1 # signals dont change between + xori t0, t0, 1 # sampling and return mtc0 t0, CP0_STATUS + SSNOP; SSNOP; SSNOP - move a0, zero - move a1, sp -#error jal do_signal - b restore_all + LONG_L a2, TI_FLAGS($28) + andi a2, _TIF_WORK_MASK # is there any work to be done + # other than syscall tracing? + beqz a2, restore_all + andi t0, a2, _TIF_NEED_RESCHED + bnez t0, work_resched + +work_notifysig: # deal with pending signals and + # notify-resume requests + move a0, sp + li a1, 0 + jal do_notify_resume # a2 already loaded + j restore_all + +FEXPORT(syscall_exit_work) + LONG_L t0, TI_FLAGS($28) + bgez t0, work_pending # trace bit is set + mfc0 t0, CP0_STATUS # could let do_syscall_trace() + ori t0, t0, 1 # call schedule() instead + mtc0 t0, CP0_STATUS + jal do_syscall_trace + b resume_userspace /* * Common spurious interrupt handler. @@ -93,25 +168,105 @@ LEAF(spurious_interrupt) * Someone tried to fool us by sending an interrupt but we * couldn't find a cause for it. */ - lui t1,%hi(spurious_count) - .set reorder - lw t0,%lo(spurious_count)(t1) - .set noreorder + lui t1,%hi(irq_err_count) + lw t0,%lo(irq_err_count)(t1) addiu t0,1 - sw t0,%lo(spurious_count)(t1) + sw t0,%lo(irq_err_count)(t1) j ret_from_irq END(spurious_interrupt) + __INIT + + .set reorder + + NESTED(except_vec1_generic, 0, sp) + PANIC("Exception vector 1 called") + END(except_vec1_generic) + + /* + * General exception vector. Used for all CPUs except R4000 + * and R4400 SC and MC versions. + */ + NESTED(except_vec3_generic, 0, sp) +#if R5432_CP0_INTERRUPT_WAR + mfc0 k0, CP0_INDEX +#endif + mfc0 k1, CP0_CAUSE + la k0, exception_handlers + andi k1, k1, 0x7c + addu k0, k0, k1 + lw k0, (k0) + jr k0 + END(except_vec3_generic) + .set at + + /* General exception vector R4000 version. */ + NESTED(except_vec3_r4000, 0, sp) + .set push + .set mips3 + .set noat + mfc0 k1, CP0_CAUSE + li k0, 31<<2 + andi k1, k1, 0x7c + .set noreorder + beq k1, k0, handle_vced + li k0, 14<<2 + beq k1, k0, handle_vcei + lui k0, %hi(exception_handlers) + addiu k0, %lo(exception_handlers) + .set reorder + addu k0, k0, k1 + lw k0, (k0) + jr k0 + + /* + * Big shit, we now may have two dirty primary cache lines for + * the same physical address. We can savely invalidate the + * line pointed to by c0_badvaddr because after return from + * this exception handler the load / store will be re-executed. + */ +handle_vced: + mfc0 k0, CP0_BADVADDR + li k1, -4 + and k0, k1 + mtc0 zero, CP0_TAGLO + cache Index_Store_Tag_D,(k0) + cache Hit_Writeback_Inv_SD,(k0) +#ifdef CONFIG_PROC_FS + lui k0, %hi(vced_count) + lw k1, %lo(vced_count)(k0) + addiu k1, 1 + sw k1, %lo(vced_count)(k0) +#endif + eret + +handle_vcei: + mfc0 k0, CP0_BADVADDR + cache Hit_Writeback_Inv_SD, (k0) # also cleans pi +#ifdef CONFIG_PROC_FS + lui k0, %hi(vcei_count) + lw k1, %lo(vcei_count)(k0) + addiu k1, 1 + sw k1, %lo(vcei_count)(k0) +#endif + eret + .set pop + END(except_vec3_r4000) + + __FINIT + /* * Build a default exception handler for the exceptions that don't need * special handlers. If you didn't know yet - I *like* playing games with * the C preprocessor ... */ #define __BUILD_clear_none(exception) -#define __BUILD_clear_sti(exception) \ +#define __BUILD_clear_sti(exception) \ STI -#define __BUILD_clear_cli(exception) \ +#define __BUILD_clear_cli(exception) \ CLI +#define __BUILD_clear_kmode(exception) \ + KMODE #define __BUILD_clear_fpe(exception) \ cfc1 a1,fcr31; \ li a2,~(0x3f<<12); \ @@ -148,6 +303,7 @@ EXPORT(exception_count_##exception); NESTED(handle_##exception, PT_SIZE, sp); \ .set noat; \ SAVE_ALL; \ + FEXPORT(handle_##exception##_int); \ __BUILD_clear_##clear(exception); \ .set at; \ __BUILD_##verbose(exception); \ @@ -159,16 +315,18 @@ EXPORT(exception_count_##exception); BUILD_HANDLER(adel,ade,ade,silent) /* #4 */ BUILD_HANDLER(ades,ade,ade,silent) /* #5 */ - BUILD_HANDLER(ibe,ibe,cli,verbose) /* #6 */ - BUILD_HANDLER(dbe,dbe,cli,silent) /* #7 */ - BUILD_HANDLER(bp,bp,sti,silent) /* #9 */ - BUILD_HANDLER(ri,ri,sti,silent) /* #10 */ - BUILD_HANDLER(cpu,cpu,sti,silent) /* #11 */ - BUILD_HANDLER(ov,ov,sti,silent) /* #12 */ - BUILD_HANDLER(tr,tr,sti,silent) /* #13 */ + BUILD_HANDLER(ibe,be,cli,silent) /* #6 */ + BUILD_HANDLER(dbe,be,cli,silent) /* #7 */ + BUILD_HANDLER(bp,bp,kmode,silent) /* #9 */ + BUILD_HANDLER(ri,ri,kmode,silent) /* #10 */ + BUILD_HANDLER(cpu,cpu,kmode,silent) /* #11 */ + BUILD_HANDLER(ov,ov,kmode,silent) /* #12 */ + BUILD_HANDLER(tr,tr,kmode,silent) /* #13 */ BUILD_HANDLER(fpe,fpe,fpe,silent) /* #15 */ - BUILD_HANDLER(watch,watch,sti,verbose) /* #23 */ - BUILD_HANDLER(reserved,reserved,sti,verbose) /* others */ + BUILD_HANDLER(mdmx,mdmx,sti,silent) /* #22 */ + BUILD_HANDLER(watch,watch,sti,silent) /* #23 */ + BUILD_HANDLER(mcheck,mcheck,cli,silent) /* #24 */ + BUILD_HANDLER(reserved,reserved,kmode,silent) /* others */ .set pop --- linux-2.5.73/arch/mips/kernel/gdb-low.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/gdb-low.S 2003-06-27 15:56:23.000000000 -0700 @@ -14,6 +14,16 @@ #include /* + * [jsun] We reserves about 2x GDB_FR_SIZE in stack. The lower (addressed) + * part is used to store registers and passed to exception handler. + * The upper part is reserved for "call func" feature where gdb client + * saves some of the regs, setups call frame and passes args. + * + * A trace shows about 200 bytes are used to store about half of all regs. + * The rest should be big enough for frame setup and passing args. + */ + +/* * The low level trap handler */ .align 5 @@ -38,7 +48,7 @@ nop 1: move k0,sp - subu sp,k1,GDB_FR_SIZE + subu sp,k1,GDB_FR_SIZE*2 # see comment above sw k0,GDB_FR_REG29(sp) sw v0,GDB_FR_REG2(sp) @@ -97,7 +107,7 @@ sw ra,GDB_FR_REG31(sp) CLI /* disable interrupts */ - + /* * Followed by the floating point registers */ @@ -145,9 +155,9 @@ * FPU control registers */ - mfc1 v0,CP1_STATUS + cfc1 v0,CP1_STATUS sw v0,GDB_FR_FSR(sp) - mfc1 v0,CP1_REVISION + cfc1 v0,CP1_REVISION sw v0,GDB_FR_FIR(sp) /* @@ -211,7 +221,7 @@ lw v0,GDB_FR_CP0_CONTEXT(sp) mtc0 v1,CP0_INDEX mtc0 v0,CP0_CONTEXT - + /* * Next, the floating point registers @@ -304,7 +314,7 @@ lw v1,GDB_FR_REG3(sp) lw v0,GDB_FR_REG2(sp) lw $1,GDB_FR_REG1(sp) -#ifdef CONFIG_CPU_R3000 +#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) lw k0, GDB_FR_EPC(sp) lw sp, GDB_FR_REG29(sp) /* Deallocate stack */ jr k0 @@ -321,11 +331,7 @@ END(trap_low) LEAF(kgdb_read_byte) - .set push - .set noreorder - .set nomacro 4: lb t0, (a0) - .set pop sb t0, (a1) li v0, 0 jr ra @@ -335,11 +341,7 @@ LEAF(kgdb_read_byte) END(kgdb_read_byte) LEAF(kgdb_write_byte) - .set push - .set noreorder - .set nomacro 5: sb a0, (a1) - .set pop li v0, 0 jr ra .section __ex_table,"a" @@ -349,6 +351,7 @@ LEAF(kgdb_write_byte) .type kgdbfault@function .ent kgdbfault + kgdbfault: li v0, -EFAULT jr ra .end kgdbfault --- linux-2.5.73/arch/mips/kernel/gdb-stub.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/gdb-stub.c 2003-06-27 15:56:23.000000000 -0700 @@ -11,8 +11,6 @@ * Send complaints, suggestions etc. to * * Copyright (C) 1995 Andreas Busse - * - * $Id: gdb-stub.c,v 1.6 1999/05/01 22:40:35 ralf Exp $ */ /* @@ -64,7 +62,7 @@ * Host: Reply: * $m0,10#2a +$00010203040506070809101112131415#42 * - * + * * ============== * MORE EXAMPLES: * ============== @@ -74,11 +72,11 @@ * going. In this scenario the host machine was a PC and the * target platform was a Galileo EVB64120A MIPS evaluation * board. - * + * * Step 1: * First download gdb-5.0.tar.gz from the internet. * and then build/install the package. - * + * * Example: * $ tar zxf gdb-5.0.tar.gz * $ cd gdb-5.0 @@ -87,40 +85,39 @@ * $ install * $ which mips-linux-elf-gdb * /usr/local/bin/mips-linux-elf-gdb - * + * * Step 2: * Configure linux for remote debugging and build it. - * + * * Example: * $ cd ~/linux * $ make menuconfig * $ make dep; make vmlinux - * + * * Step 3: * Download the kernel to the remote target and start - * the kernel running. It will promptly halt and wait + * the kernel running. It will promptly halt and wait * for the host gdb session to connect. It does this - * since the "Kernel Hacking" option has defined - * CONFIG_REMOTE_DEBUG which in turn enables your calls + * since the "Kernel Hacking" option has defined + * CONFIG_KGDB which in turn enables your calls * to: * set_debug_traps(); * breakpoint(); - * + * * Step 4: * Start the gdb session on the host. - * + * * Example: * $ mips-linux-elf-gdb vmlinux * (gdb) set remotebaud 115200 * (gdb) target remote /dev/ttyS1 - * ...at this point you are connected to + * ...at this point you are connected to * the remote target and can use gdb - * in the normal fasion. Setting + * in the normal fasion. Setting * breakpoints, single stepping, * printing variables, etc. - * */ - +#include #include #include #include @@ -128,6 +125,8 @@ #include #include #include +#include +#include #include #include @@ -176,8 +175,8 @@ static const char hexchars[]="0123456789 /* Used to prevent crashes in memory access. Note that they'll crash anyway if we haven't set up fault handlers yet... */ -int kgdb_read_byte(unsigned *address, unsigned *dest); -int kgdb_write_byte(unsigned val, unsigned *dest); +int kgdb_read_byte(unsigned char *address, unsigned char *dest); +int kgdb_write_byte(unsigned char val, unsigned char *dest); /* * Convert ch from a hex digit to an int @@ -214,7 +213,7 @@ static void getpacket(char *buffer) checksum = 0; xmitcsum = -1; count = 0; - + /* * now, read until a # or end of buffer is found */ @@ -376,10 +375,10 @@ void set_debug_traps(void) unsigned long flags; unsigned char c; - save_and_cli(flags); + local_irq_save(flags); for (ht = hard_trap_info; ht->tt && ht->signo; ht++) saved_vectors[ht->tt] = set_except_vector(ht->tt, trap_low); - + putDebugChar('+'); /* 'hello world' */ /* * In case GDB is started before us, ack any packets @@ -392,7 +391,7 @@ void set_debug_traps(void) putDebugChar('+'); /* ack it */ initialized = 1; - restore_flags(flags); + local_irq_restore(flags); } /* @@ -548,7 +547,7 @@ static void single_step(struct gdb_regs targ += 4 + (insn.i_format.simmediate << 2); break; } - + if (is_branch) { i = 0; if (is_cond && targ != (regs->cp0_epc + 8)) { @@ -568,7 +567,7 @@ static void single_step(struct gdb_regs /* * If asynchronously interrupted by gdb, then we need to set a breakpoint - * at the interrupted instruction so that we wind up stopped with a + * at the interrupted instruction so that we wind up stopped with a * reasonable stack frame. */ static struct gdb_bp_save async_bp; @@ -578,7 +577,7 @@ void set_async_breakpoint(unsigned int e async_bp.addr = epc; async_bp.val = *(unsigned *)epc; *(unsigned *)epc = BP; - flush_cache_all(); + __flush_cache_all(); } @@ -596,31 +595,11 @@ void handle_exception (struct gdb_regs * char *ptr; unsigned long *stack; -#if 0 - printk("in handle_exception()\n"); - show_gdbregs(regs); -#endif - - /* - * First check trap type. If this is CPU_UNUSABLE and CPU_ID is 1, - * the simply switch the FPU on and return since this is no error - * condition. kernel/traps.c does the same. - * FIXME: This doesn't work yet, so we don't catch CPU_UNUSABLE - * traps for now. - */ - trap = (regs->cp0_cause & 0x7c) >> 2; -/* printk("trap=%d\n",trap); */ - if (trap == 11) { - if (((regs->cp0_cause >> CAUSEB_CE) & 3) == 1) { - regs->cp0_status |= ST0_CU1; - return; - } - } - /* * If we're in breakpoint() increment the PC */ - if (trap == 9 && regs->cp0_epc == (unsigned long)breakinst) + trap = (regs->cp0_cause & 0x7c) >> 2; + if (trap == 9 && regs->cp0_epc == (unsigned long)breakinst) regs->cp0_epc += 4; /* @@ -630,7 +609,7 @@ void handle_exception (struct gdb_regs * if (step_bp[0].addr) { *(unsigned *)step_bp[0].addr = step_bp[0].val; step_bp[0].addr = 0; - + if (step_bp[1].addr) { *(unsigned *)step_bp[1].addr = step_bp[1].val; step_bp[1].addr = 0; @@ -708,6 +687,11 @@ void handle_exception (struct gdb_regs * output_buffer[3] = 0; break; + case 'D': + /* detach; let CPU run */ + putpacket(output_buffer); + return; + case 'd': /* toggle debug flag */ break; @@ -724,29 +708,24 @@ void handle_exception (struct gdb_regs * ptr = mem2hex((char *)®s->frame_ptr, ptr, 2*4, 0); /* frp */ ptr = mem2hex((char *)®s->cp0_index, ptr, 16*4, 0); /* cp0 */ break; - + /* * set the value of the CPU registers - return OK - * FIXME: Needs to be written */ case 'G': { -#if 0 - unsigned long *newsp, psr; - ptr = &input_buffer[1]; - hex2mem(ptr, (char *)registers, 16 * 4, 0); /* G & O regs */ - - /* - * See if the stack pointer has moved. If so, then copy the - * saved locals and ins to the new location. - */ - - newsp = (unsigned long *)registers[SP]; - if (sp != newsp) - sp = memcpy(newsp, sp, 16 * 4); - -#endif + hex2mem(ptr, (char *)®s->reg0, 32*4, 0); + ptr += 32*8; + hex2mem(ptr, (char *)®s->cp0_status, 6*4, 0); + ptr += 6*8; + hex2mem(ptr, (char *)®s->fpr0, 32*4, 0); + ptr += 32*8; + hex2mem(ptr, (char *)®s->cp1_fsr, 2*4, 0); + ptr += 2*8; + hex2mem(ptr, (char *)®s->frame_ptr, 2*4, 0); + ptr += 2*8; + hex2mem(ptr, (char *)®s->cp0_index, 16*4, 0); strcpy(output_buffer,"OK"); } break; @@ -770,7 +749,7 @@ void handle_exception (struct gdb_regs * /* * MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */ - case 'M': + case 'M': ptr = &input_buffer[1]; if (hexToInt(&ptr, &addr) @@ -789,13 +768,13 @@ void handle_exception (struct gdb_regs * /* * cAA..AA Continue at address AA..AA(optional) */ - case 'c': + case 'c': /* try to read optional parameter, pc unchanged if no parm */ ptr = &input_buffer[1]; if (hexToInt(&ptr, &addr)) regs->cp0_epc = addr; - + /* * Need to flush the instruction cache here, as we may * have deposited a breakpoint, and the icache probably @@ -805,26 +784,21 @@ void handle_exception (struct gdb_regs * * NB: We flush both caches, just to be sure... */ - flush_cache_all(); + __flush_cache_all(); return; /* NOTREACHED */ break; /* - * kill the program - */ - case 'k' : - break; /* do nothing */ - - - /* - * Reset the whole machine (FIXME: system dependent) + * kill the program; let us try to restart the machine + * Reset the whole machine. */ + case 'k': case 'r': + machine_restart("kgdb restarts machine"); break; - /* * Step to next instruction */ @@ -834,7 +808,7 @@ void handle_exception (struct gdb_regs * * use breakpoints and continue, instead. */ single_step(regs); - flush_cache_all(); + __flush_cache_all(); return; /* NOTREACHED */ @@ -844,7 +818,7 @@ void handle_exception (struct gdb_regs * */ case 'b': { -#if 0 +#if 0 int baudrate; extern void set_timer_3(); @@ -904,30 +878,43 @@ void breakpoint(void) if (!initialized) return; - __asm__ __volatile__(" - .globl breakinst - .set noreorder - nop -breakinst: break - nop - .set reorder - "); + __asm__ __volatile__( + ".globl breakinst\n\t" + ".set\tnoreorder\n\t" + "nop\n\t" + "breakinst:\tbreak\n\t" + "nop\n\t" + ".set\treorder" + ); } void adel(void) { - __asm__ __volatile__(" - .globl adel - la $8,0x80000001 - lw $9,0($8) - "); + __asm__ __volatile__( + ".globl\tadel\n\t" + "la\t$8,0x80000001\n\t" + "lw\t$9,0($8)\n\t" + ); +} + +/* + * malloc is needed by gdb client in "call func()", even a private one + * will make gdb happy + */ +static void *malloc(size_t size) +{ + return kmalloc(size, GFP_ATOMIC); +} + +static void free(void *where) +{ + kfree(where); } #ifdef CONFIG_GDB_CONSOLE -void gdb_puts(const char *str) +void gdb_putsn(const char *str, int l) { - int l = strlen(str); char outbuf[18]; outbuf[0]='O'; @@ -936,7 +923,7 @@ void gdb_puts(const char *str) int i = (l>8)?8:l; mem2hex((char *)str, &outbuf[1], i, 0); outbuf[(i*2)+1]=0; - putpacket(outbuf); + putpacket(outbuf); str += i; l -= i; } @@ -944,7 +931,7 @@ void gdb_puts(const char *str) static void gdb_console_write(struct console *con, const char *s, unsigned n) { - gdb_puts(s); + gdb_putsn(s, n); } static struct console gdb_console = { @@ -958,5 +945,5 @@ __init void register_gdb_console(void) { register_console(&gdb_console); } - + #endif --- linux-2.5.73/arch/mips/kernel/head.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/head.S 2003-06-27 15:56:23.000000000 -0700 @@ -1,6 +1,4 @@ /* - * arch/mips/kernel/head.S - * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. @@ -13,550 +11,224 @@ * Further modifications by David S. Miller and Harald Koerfgen * Copyright (C) 1999 Silicon Graphics, Inc. * - * Head.S contains the MIPS exception handler and startup code. - * - ************************************************************************** - * 9 Nov, 2000. - * Added Cache Error exception handler and SBDDP EJTAG debug exception. - * - * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - ************************************************************************** + * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. */ #include +#include #include #include -#include -#include #include +#include #include #include #include #include #include -#include - - .text - /* - * Reserved space for exception handlers. - * Necessary for machines which link their kernels at KSEG0. - * FIXME: Use the initcode feature to get rid of unused handler - * variants. - */ - .fill 0x280 -/* - * This is space for the interrupt handlers. - * After trap_init() they are located at virtual address KSEG0. - * - * These handlers much be written in a relocatable manner - * because based upon the cpu type an arbitrary one of the - * following pieces of code will be copied to the KSEG0 - * vector location. - */ - /* TLB refill, EXL == 0, R4xx0, non-R4600 version */ - .set noreorder - .set noat - LEAF(except_vec0_r4000) - .set mips3 -#ifdef CONFIG_SMP - mfc0 k1, CP0_CONTEXT - la k0, current_pgd - srl k1, 23 - sll k1, 2 - addu k1, k0, k1 - lw k1, (k1) -#else - lw k1, current_pgd # get pgd pointer -#endif - mfc0 k0, CP0_BADVADDR # Get faulting address - srl k0, k0, 22 # get pgd only bits - - sll k0, k0, 2 - addu k1, k1, k0 # add in pgd offset - mfc0 k0, CP0_CONTEXT # get context reg - lw k1, (k1) -#if defined(CONFIG_CPU_VR41XX) - srl k0, k0, 3 # get pte offset -#else - srl k0, k0, 1 # get pte offset -#endif - and k0, k0, 0xff8 - addu k1, k1, k0 # add in offset - lw k0, 0(k1) # get even pte - lw k1, 4(k1) # get odd pte - srl k0, k0, 6 # convert to entrylo0 - mtc0 k0, CP0_ENTRYLO0 # load it - srl k1, k1, 6 # convert to entrylo1 - mtc0 k1, CP0_ENTRYLO1 # load it - b 1f - tlbwr # write random tlb entry -1: - nop - eret # return from trap - END(except_vec0_r4000) - - /* TLB refill, EXL == 0, R4600 version */ - LEAF(except_vec0_r4600) - .set mips3 - mfc0 k0, CP0_BADVADDR - srl k0, k0, 22 - lw k1, current_pgd # get pgd pointer - sll k0, k0, 2 - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) - srl k0, k0, 1 - and k0, k0, 0xff8 - addu k1, k1, k0 - lw k0, 0(k1) - lw k1, 4(k1) - srl k0, k0, 6 - mtc0 k0, CP0_ENTRYLO0 - srl k1, k1, 6 - mtc0 k1, CP0_ENTRYLO1 - nop - tlbwr - nop - eret - END(except_vec0_r4600) - - /* TLB refill, EXL == 0, R52x0 "Nevada" version */ - /* - * This version has a bug workaround for the Nevada. It seems - * as if under certain circumstances the move from cp0_context - * might produce a bogus result when the mfc0 instruction and - * it's consumer are in a different cacheline or a load instruction, - * probably any memory reference, is between them. This is - * potencially slower than the R4000 version, so we use this - * special version. - */ - .set noreorder - .set noat - LEAF(except_vec0_nevada) - .set mips3 - mfc0 k0, CP0_BADVADDR # Get faulting address - srl k0, k0, 22 # get pgd only bits - lw k1, current_pgd # get pgd pointer - sll k0, k0, 2 - addu k1, k1, k0 # add in pgd offset - lw k1, (k1) - mfc0 k0, CP0_CONTEXT # get context reg - srl k0, k0, 1 # get pte offset - and k0, k0, 0xff8 - addu k1, k1, k0 # add in offset - lw k0, 0(k1) # get even pte - lw k1, 4(k1) # get odd pte - srl k0, k0, 6 # convert to entrylo0 - mtc0 k0, CP0_ENTRYLO0 # load it - srl k1, k1, 6 # convert to entrylo1 - mtc0 k1, CP0_ENTRYLO1 # load it - nop # QED specified nops - nop - tlbwr # write random tlb entry - nop # traditional nop - eret # return from trap - END(except_vec0_nevada) - - /* TLB refill, EXL == 0, R4[40]00/R5000 badvaddr hwbug version */ - LEAF(except_vec0_r45k_bvahwbug) - .set mips3 - mfc0 k0, CP0_BADVADDR - srl k0, k0, 22 - lw k1, current_pgd # get pgd pointer - sll k0, k0, 2 - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) - srl k0, k0, 1 - and k0, k0, 0xff8 - addu k1, k1, k0 - lw k0, 0(k1) - lw k1, 4(k1) - nop /* XXX */ - tlbp - srl k0, k0, 6 - mtc0 k0, CP0_ENTRYLO0 - srl k1, k1, 6 - mfc0 k0, CP0_INDEX - mtc0 k1, CP0_ENTRYLO1 - bltzl k0, 1f - tlbwr -1: - nop - eret - END(except_vec0_r45k_bvahwbug) - -#ifdef CONFIG_SMP - /* TLB refill, EXL == 0, R4000 MP badvaddr hwbug version */ - LEAF(except_vec0_r4k_mphwbug) - .set mips3 - mfc0 k0, CP0_BADVADDR - srl k0, k0, 22 - lw k1, current_pgd # get pgd pointer - sll k0, k0, 2 - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) - srl k0, k0, 1 - and k0, k0, 0xff8 - addu k1, k1, k0 - lw k0, 0(k1) - lw k1, 4(k1) - nop /* XXX */ - tlbp - srl k0, k0, 6 - mtc0 k0, CP0_ENTRYLO0 - srl k1, k1, 6 - mfc0 k0, CP0_INDEX - mtc0 k1, CP0_ENTRYLO1 - bltzl k0, 1f - tlbwr -1: - nop - eret - END(except_vec0_r4k_mphwbug) -#endif - - /* TLB refill, EXL == 0, R4000 UP 250MHZ entrylo[01] hwbug version */ - LEAF(except_vec0_r4k_250MHZhwbug) - .set mips3 - mfc0 k0, CP0_BADVADDR - srl k0, k0, 22 - lw k1, current_pgd # get pgd pointer - sll k0, k0, 2 - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) - srl k0, k0, 1 - and k0, k0, 0xff8 - addu k1, k1, k0 - lw k0, 0(k1) - lw k1, 4(k1) - srl k0, k0, 6 - mtc0 zero, CP0_ENTRYLO0 - mtc0 k0, CP0_ENTRYLO0 - srl k1, k1, 6 - mtc0 zero, CP0_ENTRYLO1 - mtc0 k1, CP0_ENTRYLO1 - b 1f - tlbwr -1: - nop - eret - END(except_vec0_r4k_250MHZhwbug) - -#ifdef CONFIG_SMP - /* TLB refill, EXL == 0, R4000 MP 250MHZ entrylo[01]+badvaddr bug version */ - LEAF(except_vec0_r4k_MP250MHZhwbug) - .set mips3 - mfc0 k0, CP0_BADVADDR - srl k0, k0, 22 - lw k1, current_pgd # get pgd pointer - sll k0, k0, 2 - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) - srl k0, k0, 1 - and k0, k0, 0xff8 - addu k1, k1, k0 - lw k0, 0(k1) - lw k1, 4(k1) - nop /* XXX */ - tlbp - srl k0, k0, 6 - mtc0 zero, CP0_ENTRYLO0 - mtc0 k0, CP0_ENTRYLO0 - mfc0 k0, CP0_INDEX - srl k1, k1, 6 - mtc0 zero, CP0_ENTRYLO1 - mtc0 k1, CP0_ENTRYLO1 - bltzl k0, 1f - tlbwr -1: - nop - eret - END(except_vec0_r4k_MP250MHZhwbug) -#endif - - /* TLB refill, R[23]00 version */ - LEAF(except_vec0_r2300) - .set noat - .set mips1 - mfc0 k0, CP0_BADVADDR - lw k1, current_pgd # get pgd pointer - srl k0, k0, 22 - sll k0, k0, 2 - addu k1, k1, k0 - mfc0 k0, CP0_CONTEXT - lw k1, (k1) - and k0, k0, 0xffc - addu k1, k1, k0 - lw k0, (k1) - nop - mtc0 k0, CP0_ENTRYLO0 - mfc0 k1, CP0_EPC - tlbwr - jr k1 - rfe - END(except_vec0_r2300) - - - /* XTLB refill, EXL == 0, R4xx0 cpus only use this... */ - NESTED(except_vec1_generic, 0, sp) - .set noat - .set mips3 - /* Register saving is delayed as long as we don't know - * which registers really need to be saved. - */ - mfc0 k1, CP0_CONTEXT - dsra k1, 1 - lwu k0, (k1) # May cause another exception - lwu k1, 4(k1) - dsrl k0, 6 # Convert to EntryLo format - dsrl k1, 6 # Convert to EntryLo format - dmtc0 k0, CP0_ENTRYLO0 - dmtc0 k1, CP0_ENTRYLO1 - nop # Needed for R4[04]00 pipeline - tlbwr - nop # Needed for R4[04]00 pipeline - nop - nop - eret - nop /* Workaround for R4000 bug. */ - eret - END(except_vec1_generic) - - /* Cache Error */ - LEAF(except_vec2_generic) - .set noat - .set mips0 - /* - * This is a very bad place to be. Our cache error - * detection has triggered. If we have write-back data - * in the cache, we may not be able to recover. As a - * first-order desperate measure, turn off KSEG0 cacheing. - */ - mfc0 k0,CP0_CONFIG - li k1,~CONF_CM_CMASK - and k0,k0,k1 - ori k0,k0,CONF_CM_UNCACHED - mtc0 k0,CP0_CONFIG - /* Give it a few cycles to sink in... */ - nop - nop - nop - - j cache_parity_error - nop - END(except_vec2_generic) - - /* General exception vector R4000 version. */ - NESTED(except_vec3_r4000, 0, sp) - .set noat - mfc0 k1, CP0_CAUSE - andi k1, k1, 0x7c - li k0, 31<<2 - beq k1, k0, handle_vced - li k0, 14<<2 - beq k1, k0, handle_vcei - la k0, exception_handlers - addu k0, k0, k1 - lw k0, (k0) - nop - jr k0 - nop -/* - * Big shit, we now may have two dirty primary cache lines for the same - * physical address. We can savely invalidate the line pointed to by - * c0_badvaddr because after return from this exception handler the load / - * store will be re-executed. - */ - .set mips3 -handle_vced: - mfc0 k0, CP0_BADVADDR - li k1, -4 - and k0, k1 - mtc0 zero, CP0_TAGLO - cache Index_Store_Tag_D,(k0) - cache Hit_Writeback_Inv_SD,(k0) -#ifdef CONFIG_PROC_FS - lui k0, %hi(vced_count) - lw k1, %lo(vced_count)(k0) - addiu k1, 1 - sw k1, %lo(vced_count)(k0) -#endif - eret - -handle_vcei: - mfc0 k0, CP0_BADVADDR - cache Hit_Writeback_Inv_SD,(k0) # also cleans pi -#ifdef CONFIG_PROC_FS - lui k0, %hi(vcei_count) - lw k1, %lo(vcei_count)(k0) - addiu k1, 1 - sw k1, %lo(vcei_count)(k0) -#endif - eret - - END(except_vec3_r4000) - .set at - - /* General exception vector. */ - NESTED(except_vec3_generic, 0, sp) - .set noat - .set mips0 - mfc0 k1, CP0_CAUSE - la k0, exception_handlers - andi k1, k1, 0x7c - addu k0, k0, k1 - lw k0, (k0) - nop - jr k0 - nop - END(except_vec3_generic) - .set at - - /* - * Special interrupt vector for embedded MIPS. This is a - * dedicated interrupt vector which reduces interrupt processing - * overhead. The jump instruction will be inserted here at - * initialization time. This handler may only be 8 bytes in size! - */ - NESTED(except_vec4, 0, sp) -1: j 1b /* Dummy, will be replaced */ - nop - END(except_vec4) - - /* - * SBDDP EJTAG debug exception handler. - * The EJTAG debug exception entry point is 0xbfc00480, which - * normally is in the boot PROM, so the boot PROM must do a - * unconditional jump to this vector. - */ - NESTED(except_vec_ejtag_debug, 0, sp) - j ejtag_debug_handler - nop - END(except_vec_ejtag_debug) - - /* - * EJTAG debug exception handler. - */ - NESTED(ejtag_debug_handler, PT_SIZE, sp) - .set noat - .set noreorder - SAVE_ALL - PRINT("SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); - mfc0 k0, $23 # Get EJTAG Debug register. - mfc0 k1, $24 # Get DEPC register. - bgez k0, 1f - addiu k1, k1, 4 # SBDDP inst. in delay slot. - addiu k1, k1, 4 -1: mtc0 k1, $24 - RESTORE_ALL - .word 0x4200001f # deret, return EJTAG debug exception. - nop - .set at - END(ejtag_debug_handler) - - -/* - * Kernel entry point - */ -NESTED(kernel_entry, 16, sp) - .set noreorder - /* The following two symbols are used for kernel profiling. */ - EXPORT(stext) - EXPORT(_stext) - - /* - * Stack for kernel and init, current variable - */ - la $28, init_task_union - addiu t0, $28, KERNEL_STACK_SIZE-32 - subu sp, t0, 4*SZREG - - sw t0, kernelsp - /* The firmware/bootloader passes argc/argp/envp - * to us as arguments. But clear bss first because - * the romvec and other important info is stored there - * by prom_init(). - */ - la t0, _edata - sw zero, (t0) - la t1, (_end - 4) -1: - addiu t0, 4 - bne t0, t1, 1b - sw zero, (t0) - - jal init_arch - nop - END(kernel_entry) + .text + /* + * Reserved space for exception handlers. + * Necessary for machines which link their kernels at KSEG0. + */ + .fill 0x400 + + /* The following two symbols are used for kernel profiling. */ + EXPORT(stext) + EXPORT(_stext) + + __INIT + + /* Cache Error */ + LEAF(except_vec2_generic) + .set noreorder + .set noat + .set mips0 + /* + * This is a very bad place to be. Our cache error + * detection has triggered. If we have write-back data + * in the cache, we may not be able to recover. As a + * first-order desperate measure, turn off KSEG0 cacheing. + */ + mfc0 k0,CP0_CONFIG + li k1,~CONF_CM_CMASK + and k0,k0,k1 + ori k0,k0,CONF_CM_UNCACHED + mtc0 k0,CP0_CONFIG + /* Give it a few cycles to sink in... */ + nop + nop + nop + + j cache_parity_error + nop + END(except_vec2_generic) + + .set at + + /* + * Special interrupt vector for embedded MIPS. This is a + * dedicated interrupt vector which reduces interrupt processing + * overhead. The jump instruction will be inserted here at + * initialization time. This handler may only be 8 bytes in + * size! + */ + NESTED(except_vec4, 0, sp) +1: j 1b /* Dummy, will be replaced */ + nop + END(except_vec4) + + /* + * EJTAG debug exception handler. + * The EJTAG debug exception entry point is 0xbfc00480, which + * normally is in the boot PROM, so the boot PROM must do a + * unconditional jump to this vector. + */ + NESTED(except_vec_ejtag_debug, 0, sp) + j ejtag_debug_handler + nop + END(except_vec_ejtag_debug) + + __FINIT + + /* + * EJTAG debug exception handler. + */ + NESTED(ejtag_debug_handler, PT_SIZE, sp) + .set noat + .set noreorder + mtc0 k0, CP0_DESAVE + mfc0 k0, CP0_DEBUG + + sll k0, k0, 30 # Check for SDBBP. + bgez k0, ejtag_return + + la k0, ejtag_debug_buffer + sw k1, 0(k0) + SAVE_ALL + jal ejtag_exception_handler + move a0, sp + RESTORE_ALL + la k0, ejtag_debug_buffer + lw k1, 0(k0) + +ejtag_return: + mfc0 k0, CP0_DESAVE + .set mips32 + deret + .set mips0 + nop + .set at + END(ejtag_debug_handler) + + __INIT + + /* + * NMI debug exception handler for MIPS reference boards. + * The NMI debug exception entry point is 0xbfc00000, which + * normally is in the boot PROM, so the boot PROM must do a + * unconditional jump to this vector. + */ + NESTED(except_vec_nmi, 0, sp) + j nmi_handler + nop + END(except_vec_nmi) + + __FINIT + + NESTED(nmi_handler, PT_SIZE, sp) + .set noat + .set noreorder + .set mips3 + SAVE_ALL + jal nmi_exception_handler + move a0, sp + RESTORE_ALL + eret + .set at + .set mips0 + END(nmi_handler) + + __INIT + + /* + * Kernel entry point + */ + NESTED(kernel_entry, 16, sp) + .set noreorder + + /* + * Stack for kernel and init, current variable + */ + la $28, init_thread_union + addiu t0, $28, KERNEL_STACK_SIZE-32 + subu sp, t0, 4*SZREG + sw t0, kernelsp + + /* The firmware/bootloader passes argc/argp/envp + * to us as arguments. But clear bss first because + * the romvec and other important info is stored there + * by prom_init(). + */ + la t0, __bss_start + sw zero, (t0) + la t1, __bss_stop - 4 +1: + addiu t0, 4 + bne t0, t1, 1b + sw zero, (t0) + + jal init_arch + nop + END(kernel_entry) #ifdef CONFIG_SMP /* - * SMP slave cpus entry point. Board specific code - * for bootstrap calls this function after setting up - * the stack and gp registers. - */ - LEAF(smp_bootstrap) - .set push - .set noreorder - mtc0 zero, CP0_WIRED - CLI - mfc0 t0, CP0_STATUS - li t1, ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_BEV); - and t0, t1 - or t0, (ST0_CU0|ST0_KX|ST0_SX|ST0_FR); - addiu a0, zero, 0 - jal start_secondary - mtc0 t0, CP0_STATUS - .set pop - END(smp_bootstrap) -#endif - -/* - * This buffer is reserved for the use of the cache error handler. + * SMP slave cpus entry point. Board specific code for bootstrap calls this + * function after setting up the stack and gp registers. */ + LEAF(smp_bootstrap) + .set push + .set noreorder + mtc0 zero, CP0_WIRED + CLI + mfc0 t0, CP0_STATUS + li t1, ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX) + and t0, t1 + or t0, (ST0_CU0); + jal start_secondary + mtc0 t0, CP0_STATUS + .set pop + END(smp_bootstrap) +#endif + + __FINIT + + /* + * This buffer is reserved for the use of the EJTAG debug + * handler. + */ .data - EXPORT(cache_error_buffer) - .fill 32*4,1,0 - -#ifndef CONFIG_SMP -EXPORT(kernelsp) - PTR 0 -EXPORT(current_pgd) - PTR 0 -#else - /* There's almost certainly a better way to do this with the macros...*/ - .globl kernelsp - .comm kernelsp, NR_CPUS * 8, 8 - .globl current_pgd - .comm current_pgd, NR_CPUS * 8, 8 -#endif - .text - .org 0x1000 -EXPORT(swapper_pg_dir) - - .org 0x2000 -EXPORT(empty_bad_page) + EXPORT(ejtag_debug_buffer) + .fill 4 - .org 0x3000 -EXPORT(empty_bad_page_table) + .comm kernelsp, NR_CPUS * 8, 8 + .comm pgd_current, NR_CPUS * 8, 8 - .org 0x4000 -EXPORT(invalid_pte_table) - - .org 0x5000 -/* XXX This label is required to keep GAS trying to be too clever ... - Bug? */ -dummy: -/* - * Align to 8kb boundary for init_task_union which follows in the - * .text segment. - */ - .align 13 + .macro page name, order=0 + .globl \name +\name: .size \name, (_PAGE_SIZE << \order) + .org . + (_PAGE_SIZE << \order) + .type \name, @object + .endm + + .data + .align PAGE_SHIFT + + page swapper_pg_dir, _PGD_ORDER + page empty_bad_page, 0 + page empty_bad_page_table, 0 + page invalid_pte_table, 0 --- linux-2.5.73/arch/mips/kernel/i8259.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/i8259.c 2003-06-27 15:56:23.000000000 -0700 @@ -11,11 +11,12 @@ #include #include #include -#include #include #include #include +#include +#include #include void enable_8259A_irq(unsigned int irq); @@ -30,11 +31,12 @@ void disable_8259A_irq(unsigned int irq) * moves to arch independent land */ -spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED; +static spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED; static void end_8259A_irq (unsigned int irq) { - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) && + irq_desc[irq].action) enable_8259A_irq(irq); } @@ -43,7 +45,7 @@ static void end_8259A_irq (unsigned int void mask_and_ack_8259A(unsigned int); static unsigned int startup_8259A_irq(unsigned int irq) -{ +{ enable_8259A_irq(irq); return 0; /* never anything pending */ @@ -69,9 +71,8 @@ static struct hw_interrupt_type i8259A_i */ static unsigned int cached_irq_mask = 0xffff; -#define __byte(x,y) (((unsigned char *)&(y))[x]) -#define cached_21 (__byte(0,cached_irq_mask)) -#define cached_A1 (__byte(1,cached_irq_mask)) +#define cached_21 (cached_irq_mask) +#define cached_A1 (cached_irq_mask >> 8) void disable_8259A_irq(unsigned int irq) { @@ -211,7 +212,7 @@ spurious_8259A_irq: printk("spurious 8259A interrupt: IRQ%d.\n", irq); spurious_irq_mask |= irqmask; } - irq_err_count++; + atomic_inc(&irq_err_count); /* * Theoretically we do not have to handle this IRQ, * but in Linux this does not cause problems and is @@ -221,6 +222,32 @@ spurious_8259A_irq: } } +static int i8259A_resume(struct sys_device *dev) +{ + init_8259A(0); + return 0; +} + +static struct sysdev_class i8259_sysdev_class = { + set_kset_name("i8259"), + .resume = i8259A_resume, +}; + +static struct sys_device device_i8259A = { + .id = 0, + .cls = &i8259_sysdev_class, +}; + +static int __init i8259A_init_sysfs(void) +{ + int error = sysdev_class_register(&i8259_sysdev_class); + if (!error) + error = sys_device_register(&device_i8259A); + return error; +} + +device_initcall(i8259A_init_sysfs); + void __init init_8259A(int auto_eoi) { unsigned long flags; @@ -234,7 +261,7 @@ void __init init_8259A(int auto_eoi) * outb_p - this has to work on a wide range of PC hardware. */ outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */ - outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */ + outb_p(0x00, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x00-0x07 */ outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */ if (auto_eoi) outb_p(0x03, 0x21); /* master does Auto EOI */ @@ -242,7 +269,7 @@ void __init init_8259A(int auto_eoi) outb_p(0x01, 0x21); /* master expects normal EOI */ outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */ - outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */ + outb_p(0x08, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x08-0x0f */ outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */ outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode is to be investigated) */ --- linux-2.5.73/arch/mips/kernel/init_task.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/init_task.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,17 +1,19 @@ #include #include #include +#include #include #include static struct fs_struct init_fs = INIT_FS; static struct files_struct init_files = INIT_FILES; -static struct signal_struct init_signals = INIT_SIGNALS; +static struct signal_struct init_signals = INIT_SIGNALS(init_signals); +static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); struct mm_struct init_mm = INIT_MM(init_mm); /* - * Initial task structure. + * Initial thread structure. * * We need to make sure that this is 8192-byte aligned due to the * way process stacks are handled. This is done by making sure @@ -20,6 +22,13 @@ struct mm_struct init_mm = INIT_MM(init_ * * The things we do for performance.. */ -union task_union init_task_union - __attribute__((__section__(".text"))) = - { INIT_TASK(init_task_union.task) }; +union thread_union init_thread_union + __attribute__((__section__(".data.init_task"))) = + { INIT_THREAD_INFO(init_task) }; + +/* + * Initial task structure. + * + * All other task structs will be allocated on slabs in fork.c + */ +struct task_struct init_task = INIT_TASK(init_task); --- linux-2.5.73/arch/mips/kernel/ioport.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,34 +0,0 @@ -/* - * linux/arch/mips/kernel/ioport.c - */ -#include -#include -#include -#include -#include - -/* - * This changes the io permissions bitmap in the current task. - */ -asmlinkage int sys_ioperm(unsigned long from, unsigned long num, int turn_on) -{ - return -ENOSYS; -} - -/* - * sys_iopl has to be used when you want to access the IO ports - * beyond the 0x3ff range: to get the full 65536 ports bitmapped - * you'd need 8kB of bitmaps/process, which is a bit excessive. - * - * Here we just change the eflags value on the stack: we allow - * only the super-user to do it. This depends on the stack-layout - * on system-call entry - see also fork() and the signal handling - * code. - */ -asmlinkage int sys_iopl(long ebx,long ecx,long edx, - long esi, long edi, long ebp, long eax, long ds, - long es, long fs, long gs, long orig_eax, - long eip,long cs,long eflags,long esp,long ss) -{ - return -ENOSYS; -} --- linux-2.5.73/arch/mips/kernel/ipc.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/ipc.c 2003-06-27 15:56:23.000000000 -0700 @@ -45,7 +45,7 @@ asmlinkage int sys_ipc (uint call, int f } case MSGSND: - return sys_msgsnd (first, (struct msgbuf *) ptr, + return sys_msgsnd (first, (struct msgbuf *) ptr, second, third); case MSGRCV: switch (version) { @@ -53,9 +53,9 @@ asmlinkage int sys_ipc (uint call, int f struct ipc_kludge tmp; if (!ptr) return -EINVAL; - + if (copy_from_user(&tmp, - (struct ipc_kludge *) ptr, + (struct ipc_kludge *) ptr, sizeof (tmp))) return -EFAULT; return sys_msgrcv (first, tmp.msgp, second, @@ -85,7 +85,7 @@ asmlinkage int sys_ipc (uint call, int f return -EINVAL; return sys_shmat (first, (char *) ptr, second, (ulong *) third); } - case SHMDT: + case SHMDT: return sys_shmdt ((char *)ptr); case SHMGET: return sys_shmget (first, second, third); @@ -93,6 +93,6 @@ asmlinkage int sys_ipc (uint call, int f return sys_shmctl (first, second, (struct shmid_ds *) ptr); default: - return -EINVAL; + return -ENOSYS; } } --- linux-2.5.73/arch/mips/kernel/irix5sys.h 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/irix5sys.h 2003-06-27 15:56:23.000000000 -0700 @@ -1,5 +1,4 @@ -/* $Id: irix5sys.h,v 1.2 1998/08/17 10:16:25 ralf Exp $ - * +/* * irix5sys.h: 32-bit IRIX5 ABI system call table. * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) --- linux-2.5.73/arch/mips/kernel/irixelf.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/irixelf.c 2003-06-27 15:56:23.000000000 -0700 @@ -45,7 +45,6 @@ static int load_irix_binary(struct linux static int load_irix_library(struct file *); static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file); -extern int dump_fpu (elf_fpregset_t *); static struct linux_binfmt irix_format = { NULL, THIS_MODULE, load_irix_binary, load_irix_library, @@ -127,7 +126,7 @@ static void set_brk(unsigned long start, { start = PAGE_ALIGN(start); end = PAGE_ALIGN(end); - if (end <= start) + if (end <= start) return; do_brk(start, end - start); } @@ -157,7 +156,7 @@ unsigned long * create_irix_tables(char elf_addr_t *argv; elf_addr_t *envp; elf_addr_t *sp, *csp; - + #ifdef DEBUG_ELF printk("create_irix_tables: p[%p] argc[%d] envc[%d] " "load_addr[%08x] interp_load_addr[%08x]\n", @@ -246,7 +245,7 @@ static unsigned int load_irix_interp(str elf_bss = 0; last_bss = 0; error = load_addr = 0; - + #ifdef DEBUG_ELF print_elfhdr(interp_elf_ex); #endif @@ -267,7 +266,7 @@ static unsigned int load_irix_interp(str return 0xffffffff; } - elf_phdata = (struct elf_phdr *) + elf_phdata = (struct elf_phdr *) kmalloc(sizeof(struct elf_phdr) * interp_elf_ex->e_phnum, GFP_KERNEL); @@ -393,7 +392,7 @@ static int verify_binary(struct elfhdr * return -ENOEXEC; /* First of all, some simple consistency checks */ - if((ehp->e_type != ET_EXEC && ehp->e_type != ET_DYN) || + if((ehp->e_type != ET_EXEC && ehp->e_type != ET_DYN) || !irix_elf_check_arch(ehp) || !bprm->file->f_op->mmap) { return -ENOEXEC; } @@ -557,7 +556,7 @@ static inline int map_interpreter(struct } /* - * IRIX maps a page at 0x200000 that holds information about the + * IRIX maps a page at 0x200000 that holds information about the * process and the system, here we map the page and fill the * structure */ @@ -567,20 +566,20 @@ void irix_map_prda_page (void) struct prda *pp; v = do_brk (PRDA_ADDRESS, PAGE_SIZE); - + if (v < 0) return; pp = (struct prda *) v; pp->prda_sys.t_pid = current->pid; - pp->prda_sys.t_prid = read_32bit_cp0_register (CP0_PRID); + pp->prda_sys.t_prid = read_c0_prid(); pp->prda_sys.t_rpid = current->pid; /* We leave the rest set to zero */ } - - + + /* These are the functions used to load ELF style executables and shared * libraries. There is no binary dependent code anywhere else. */ @@ -595,7 +594,7 @@ static int load_irix_binary(struct linux int retval, has_interp, has_ephdr, size, i; char *elf_interpreter; mm_segment_t old_fs; - + load_addr = 0; has_interp = has_ephdr = 0; elf_ihdr = elf_ephdr = 0; @@ -684,7 +683,7 @@ static int load_irix_binary(struct linux current->mm->mmap = NULL; current->flags &= ~PF_FORKNOEXEC; elf_entry = (unsigned int) elf_ex.e_entry; - + /* Do this so that we can load the interpreter, if need be. We will * change some of these later. */ @@ -723,7 +722,7 @@ static int load_irix_binary(struct linux set_binfmt(&irix_format); compute_creds(bprm); current->flags &= ~PF_FORKNOEXEC; - bprm->p = (unsigned long) + bprm->p = (unsigned long) create_irix_tables((char *)bprm->p, bprm->argc, bprm->envc, (elf_interpreter ? &elf_ex : NULL), load_addr, interp_load_addr, regs, elf_ephdr); @@ -811,30 +810,30 @@ static int load_irix_library(struct file if(elf_ex.e_type != ET_EXEC || elf_ex.e_phnum > 2 || !irix_elf_check_arch(&elf_ex) || !file->f_op->mmap) return -ENOEXEC; - + /* Now read in all of the header information. */ if(sizeof(struct elf_phdr) * elf_ex.e_phnum > PAGE_SIZE) return -ENOEXEC; - - elf_phdata = (struct elf_phdr *) + + elf_phdata = (struct elf_phdr *) kmalloc(sizeof(struct elf_phdr) * elf_ex.e_phnum, GFP_KERNEL); if (elf_phdata == NULL) return -ENOMEM; - + retval = kernel_read(file, elf_ex.e_phoff, (char *) elf_phdata, sizeof(struct elf_phdr) * elf_ex.e_phnum); - + j = 0; for(i=0; ip_type == PT_LOAD) j++; - + if(j != 1) { kfree(elf_phdata); return -ENOEXEC; } - + while(elf_phdata->p_type != PT_LOAD) elf_phdata++; - + /* Now use mmap to map the library into memory. */ down_write(¤t->mm->mmap_sem); error = do_mmap(file, @@ -862,7 +861,7 @@ static int load_irix_library(struct file kfree(elf_phdata); return 0; } - + /* Called through irix_syssgi() to map an elf image given an FD, * a phdr ptr USER_PHDRP in userspace, and a count CNT telling how many * phdrs there are in the USER_PHDRP array. We return the vaddr the @@ -1025,7 +1024,7 @@ static int writenote(struct memelfnote * DUMP_SEEK(roundup((unsigned long)file->f_pos, 4)); /* XXX */ DUMP_WRITE(men->data, men->datasz); DUMP_SEEK(roundup((unsigned long)file->f_pos, 4)); /* XXX */ - + return 1; end_coredump: @@ -1071,13 +1070,13 @@ static int irix_core_dump(long signr, st if (maydump(vma)) { int sz = vma->vm_end-vma->vm_start; - + if (size+sz >= limit) break; else size += sz; } - + segs++; } #ifdef DEBUG @@ -1104,7 +1103,7 @@ static int irix_core_dump(long signr, st elf.e_shentsize = 0; elf.e_shnum = 0; elf.e_shstrndx = 0; - + fs = get_fs(); set_fs(KERNEL_DS); @@ -1129,24 +1128,24 @@ static int irix_core_dump(long signr, st prstatus.pr_sigpend = current->pending.signal.sig[0]; prstatus.pr_sighold = current->blocked.sig[0]; psinfo.pr_pid = prstatus.pr_pid = current->pid; - psinfo.pr_ppid = prstatus.pr_ppid = current->p_pptr->pid; + psinfo.pr_ppid = prstatus.pr_ppid = current->parent->pid; psinfo.pr_pgrp = prstatus.pr_pgrp = current->pgrp; psinfo.pr_sid = prstatus.pr_sid = current->session; - prstatus.pr_utime.tv_sec = CT_TO_SECS(current->times.tms_utime); - prstatus.pr_utime.tv_usec = CT_TO_USECS(current->times.tms_utime); - prstatus.pr_stime.tv_sec = CT_TO_SECS(current->times.tms_stime); - prstatus.pr_stime.tv_usec = CT_TO_USECS(current->times.tms_stime); - prstatus.pr_cutime.tv_sec = CT_TO_SECS(current->times.tms_cutime); - prstatus.pr_cutime.tv_usec = CT_TO_USECS(current->times.tms_cutime); - prstatus.pr_cstime.tv_sec = CT_TO_SECS(current->times.tms_cstime); - prstatus.pr_cstime.tv_usec = CT_TO_USECS(current->times.tms_cstime); + prstatus.pr_utime.tv_sec = CT_TO_SECS(current->utime); + prstatus.pr_utime.tv_usec = CT_TO_USECS(current->utime); + prstatus.pr_stime.tv_sec = CT_TO_SECS(current->stime); + prstatus.pr_stime.tv_usec = CT_TO_USECS(current->stime); + prstatus.pr_cutime.tv_sec = CT_TO_SECS(current->cutime); + prstatus.pr_cutime.tv_usec = CT_TO_USECS(current->cutime); + prstatus.pr_cstime.tv_sec = CT_TO_SECS(current->cstime); + prstatus.pr_cstime.tv_usec = CT_TO_USECS(current->cstime); if (sizeof(elf_gregset_t) != sizeof(struct pt_regs)) { printk("sizeof(elf_gregset_t) (%d) != sizeof(struct pt_regs) " "(%d)\n", sizeof(elf_gregset_t), sizeof(struct pt_regs)); } else { *(struct pt_regs *)&prstatus.pr_reg = *regs; } - + notes[1].name = "CORE"; notes[1].type = NT_PRPSINFO; notes[1].datasz = sizeof(psinfo); @@ -1155,7 +1154,7 @@ static int irix_core_dump(long signr, st psinfo.pr_state = i; psinfo.pr_sname = (i < 0 || i > 5) ? '.' : "RSDZTD"[i]; psinfo.pr_zomb = psinfo.pr_sname == 'Z'; - psinfo.pr_nice = current->nice; + psinfo.pr_nice = task_nice(current); psinfo.pr_flag = current->flags; psinfo.pr_uid = current->uid; psinfo.pr_gid = current->gid; @@ -1163,7 +1162,7 @@ static int irix_core_dump(long signr, st int i, len; set_fs(fs); - + len = current->mm->arg_end - current->mm->arg_start; len = len >= ELF_PRARGSZ ? ELF_PRARGSZ : len; copy_from_user(&psinfo.pr_psargs, @@ -1183,7 +1182,7 @@ static int irix_core_dump(long signr, st notes[2].data = current; /* Try to dump the FPU. */ - prstatus.pr_fpvalid = dump_fpu (&fpu); + prstatus.pr_fpvalid = dump_fpu (regs, &fpu); if (!prstatus.pr_fpvalid) { numnote--; } else { @@ -1200,7 +1199,7 @@ static int irix_core_dump(long signr, st for(i = 0; i < numnote; i++) sz += notesize(¬es[i]); - + phdr.p_type = PT_NOTE; phdr.p_offset = offset; phdr.p_vaddr = 0; @@ -1216,7 +1215,7 @@ static int irix_core_dump(long signr, st /* Page-align dumped data. */ dataoff = offset = roundup(offset, PAGE_SIZE); - + /* Write program headers for segments dump. */ for(vma = current->mm->mmap, i = 0; i < segs && vma != NULL; vma = vma->vm_next) { @@ -1226,7 +1225,7 @@ static int irix_core_dump(long signr, st i++; sz = vma->vm_end - vma->vm_start; - + phdr.p_type = PT_LOAD; phdr.p_offset = offset; phdr.p_vaddr = vma->vm_start; @@ -1245,17 +1244,17 @@ static int irix_core_dump(long signr, st for(i = 0; i < numnote; i++) if (!writenote(¬es[i], file)) goto end_coredump; - + set_fs(fs); DUMP_SEEK(dataoff); - + for(i = 0, vma = current->mm->mmap; i < segs && vma != NULL; vma = vma->vm_next) { unsigned long addr = vma->vm_start; unsigned long len = vma->vm_end - vma->vm_start; - + if (!maydump(vma)) continue; i++; --- linux-2.5.73/arch/mips/kernel/irixinv.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/irixinv.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,11 +1,9 @@ /* * Support the inventory interface for IRIX binaries * This is invoked before the mm layer is working, so we do not - * use the linked lists for the inventory yet. + * use the linked lists for the inventory yet. * * Miguel de Icaza, 1997. - * - * $Id: irixinv.c,v 1.3 1998/04/05 11:23:51 ralf Exp $ */ #include #include @@ -18,14 +16,13 @@ int inventory_items = 0; static inventory_t inventory [MAX_INVENTORY]; -void -add_to_inventory (int class, int type, int controller, int unit, int state) +void add_to_inventory (int class, int type, int controller, int unit, int state) { inventory_t *ni = &inventory [inventory_items]; if (inventory_items == MAX_INVENTORY) return; - + ni->inv_class = class; ni->inv_type = type; ni->inv_controller = controller; @@ -35,8 +32,7 @@ add_to_inventory (int class, int type, i inventory_items++; } -int -dump_inventory_to_user (void *userbuf, int size) +int dump_inventory_to_user (void *userbuf, int size) { inventory_t *inv = &inventory [0]; inventory_t *user = userbuf; @@ -53,13 +49,13 @@ dump_inventory_to_user (void *userbuf, i return inventory_items * sizeof (inventory_t); } -void __init init_inventory (void) +static int __init init_inventory(void) { - /* gross hack while we put the right bits all over the kernel + /* + * gross hack while we put the right bits all over the kernel * most likely this will not let just anyone run the X server * until we put the right values all over the place */ - add_to_inventory (10, 3, 0, 0, 16400); add_to_inventory (1, 1, 150, -1, 12); add_to_inventory (1, 3, 0, 0, 8976); @@ -78,4 +74,8 @@ void __init init_inventory (void) add_to_inventory (2, 2, 0, 2, 0); add_to_inventory (2, 2, 0, 1, 0); add_to_inventory (7, 14, 0, 0, 6); + + return 0; } + +module_init(init_inventory); --- linux-2.5.73/arch/mips/kernel/irixioctl.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/irixioctl.c 2003-06-27 15:56:23.000000000 -0700 @@ -10,6 +10,7 @@ #include #include #include +#include #include #include --- linux-2.5.73/arch/mips/kernel/irixsig.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/irixsig.c 2003-06-27 15:56:23.000000000 -0700 @@ -17,7 +17,7 @@ #include #include -extern asmlinkage void syscall_trace(void); +extern asmlinkage void do_syscall_trace(void); #undef DEBUG_SIG @@ -117,7 +117,8 @@ static void setup_irix_frame(struct k_si regs->regs[5] = 0; /* XXX sigcode XXX */ regs->regs[6] = regs->regs[29] = sp; regs->regs[7] = (unsigned long) ka->sa.sa_handler; - regs->regs[25] = regs->cp0_epc = (unsigned long) ka->sa.sa_restorer; + regs->regs[25] = regs->cp0_epc = (unsigned long) ka->sa_restorer; + return; segv_and_exit: @@ -134,27 +135,11 @@ setup_irix_rt_frame(struct k_sigaction * do_exit(SIGSEGV); } -static inline void handle_signal(unsigned long sig, struct k_sigaction *ka, - siginfo_t *info, sigset_t *oldset, struct pt_regs * regs) +static inline void handle_signal(unsigned long sig, siginfo_t *info, + sigset_t *oldset, struct pt_regs * regs) { - if (ka->sa.sa_flags & SA_SIGINFO) - setup_irix_rt_frame(ka, regs, sig, oldset, info); - else - setup_irix_frame(ka, regs, sig, oldset); + struct k_sigaction *ka = ¤t->sighand->action[sig-1]; - if (ka->sa.sa_flags & SA_ONESHOT) - ka->sa.sa_handler = SIG_DFL; - if (!(ka->sa.sa_flags & SA_NODEFER)) { - spin_lock_irq(¤t->sigmask_lock); - sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); - sigaddset(¤t->blocked,sig); - recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); - } -} - -static inline void syscall_restart(struct pt_regs *regs, struct k_sigaction *ka) -{ switch(regs->regs[0]) { case ERESTARTNOHAND: regs->regs[2] = EINTR; @@ -170,111 +155,34 @@ static inline void syscall_restart(struc } regs->regs[0] = 0; /* Don't deal with this again. */ + + if (ka->sa.sa_flags & SA_SIGINFO) + setup_irix_rt_frame(ka, regs, sig, oldset, info); + else + setup_irix_frame(ka, regs, sig, oldset); + + if (ka->sa.sa_flags & SA_ONESHOT) + ka->sa.sa_handler = SIG_DFL; + if (!(ka->sa.sa_flags & SA_NODEFER)) { + spin_lock_irq(¤t->sighand->siglock); + sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); + sigaddset(¤t->blocked,sig); + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + } } asmlinkage int do_irix_signal(sigset_t *oldset, struct pt_regs *regs) { - struct k_sigaction *ka; siginfo_t info; + int signr; if (!oldset) oldset = ¤t->blocked; - for (;;) { - unsigned long signr; - - spin_lock_irq(¤t->sigmask_lock); - signr = dequeue_signal(current, ¤t->blocked, &info); - spin_unlock_irq(¤t->sigmask_lock); - - if (!signr) - break; - - if ((current->ptrace & PT_PTRACED) && signr != SIGKILL) { - /* Let the debugger run. */ - current->exit_code = signr; - current->state = TASK_STOPPED; - notify_parent(current, SIGCHLD); - schedule(); - - /* We're back. Did the debugger cancel the sig? */ - if (!(signr = current->exit_code)) - continue; - current->exit_code = 0; - - /* The debugger continued. Ignore SIGSTOP. */ - if (signr == SIGSTOP) - continue; - - /* Update the siginfo structure. Is this good? */ - if (signr != info.si_signo) { - info.si_signo = signr; - info.si_errno = 0; - info.si_code = SI_USER; - info.si_pid = current->p_pptr->pid; - info.si_uid = current->p_pptr->uid; - } - - /* If the (new) signal is now blocked, requeue it. */ - if (sigismember(¤t->blocked, signr)) { - send_sig_info(signr, &info, current); - continue; - } - } - - ka = ¤t->sig->action[signr-1]; - if (ka->sa.sa_handler == SIG_IGN) { - if (signr != SIGCHLD) - continue; - /* Check for SIGCHLD: it's special. */ - while (sys_wait4(-1, NULL, WNOHANG, NULL) > 0) - /* nothing */; - continue; - } - - if (ka->sa.sa_handler == SIG_DFL) { - int exit_code = signr; - - /* Init gets no signals it doesn't want. */ - if (current->pid == 1) - continue; - - switch (signr) { - case SIGCONT: case SIGCHLD: case SIGWINCH: - continue; - - case SIGTSTP: case SIGTTIN: case SIGTTOU: - if (is_orphaned_pgrp(current->pgrp)) - continue; - /* FALLTHRU */ - - case SIGSTOP: - current->state = TASK_STOPPED; - current->exit_code = signr; - if (!(current->p_pptr->sig->action[SIGCHLD-1].sa.sa_flags & SA_NOCLDSTOP)) - notify_parent(current, SIGCHLD); - schedule(); - continue; - - case SIGQUIT: case SIGILL: case SIGTRAP: - case SIGABRT: case SIGFPE: case SIGSEGV: - if (do_coredump(signr, regs)) - exit_code |= 0x80; - /* FALLTHRU */ - - default: - sigaddset(¤t->pending.signal, signr); - recalc_sigpending(); - current->flags |= PF_SIGNALED; - do_exit(exit_code); - /* NOTREACHED */ - } - } - - if (regs->regs[0]) - syscall_restart(regs, ka); - /* Whee! Actually deliver the signal. */ - handle_signal(signr, ka, &info, oldset, regs); + signr = get_signal_to_deliver(&info, regs, NULL); + if (signr > 0) { + handle_signal(signr, &info, oldset, regs); return 1; } @@ -343,19 +251,19 @@ irix_sigreturn(struct pt_regs *regs) goto badframe; sigdelsetmask(&blocked, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); + spin_lock_irq(¤t->sighand->siglock); current->blocked = blocked; recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); + spin_unlock_irq(¤t->sighand->siglock); /* * Don't let your children do this ... */ - if (current->ptrace & PT_TRACESYS) - syscall_trace(); + if (current_thread_info()->flags & TIF_SYSCALL_TRACE) + do_syscall_trace(); __asm__ __volatile__( "move\t$29,%0\n\t" - "j\tret_from_sys_call" + "j\tsyscall_exit" :/* no outputs */ :"r" (®s)); /* Unreached */ @@ -380,7 +288,7 @@ static inline void dump_sigact_irix5(str } #endif -asmlinkage int +asmlinkage int irix_sigaction(int sig, const struct sigaction *act, struct sigaction *oact, void *trampoline) { @@ -408,7 +316,7 @@ irix_sigaction(int sig, const struct sig * value for all invocations of sigaction. Will have to * investigate. POSIX POSIX, die die die... */ - new_ka.sa.sa_restorer = trampoline; + new_ka.sa_restorer = trampoline; } /* XXX Implement SIG_SETMASK32 for IRIX compatibility */ @@ -443,7 +351,7 @@ asmlinkage int irix_sigprocmask(int how, __copy_from_user(&newbits, new, sizeof(unsigned long)*4); sigdelsetmask(&newbits, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); + spin_lock_irq(¤t->sighand->siglock); oldbits = current->blocked; switch(how) { @@ -466,7 +374,7 @@ asmlinkage int irix_sigprocmask(int how, return -EINVAL; } recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); + spin_unlock_irq(¤t->sighand->siglock); } if(old) { error = verify_area(VERIFY_WRITE, old, sizeof(*old)); @@ -487,11 +395,11 @@ asmlinkage int irix_sigsuspend(struct pt return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); + spin_lock_irq(¤t->sighand->siglock); saveset = current->blocked; current->blocked = newset; recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); + spin_unlock_irq(¤t->sighand->siglock); regs->regs[2] = -EINTR; while (1) { @@ -640,7 +548,9 @@ asmlinkage int irix_waitsys(int type, in { int flag, retval; DECLARE_WAITQUEUE(wait, current); + struct task_struct *tsk; struct task_struct *p; + struct list_head *_p; if (!info) { retval = -EINVAL; @@ -667,7 +577,9 @@ repeat: flag = 0; current->state = TASK_INTERRUPTIBLE; read_lock(&tasklist_lock); - for (p = current->p_cptr; p; p = p->p_osptr) { + tsk = current; + list_for_each(_p,&tsk->children) { + p = list_entry(_p,struct task_struct,sibling); if ((type == P_PID) && p->pid != pid) continue; if ((type == P_PGID) && p->pgrp != pid) @@ -676,50 +588,63 @@ repeat: continue; flag = 1; switch (p->state) { - case TASK_STOPPED: - if (!p->exit_code) - continue; - if (!(options & (W_TRAPPED|W_STOPPED)) && - !(p->ptrace & PT_PTRACED)) - continue; - if (ru != NULL) - getrusage(p, RUSAGE_BOTH, ru); - __put_user(SIGCHLD, &info->sig); - __put_user(0, &info->code); - __put_user(p->pid, &info->stuff.procinfo.pid); - __put_user((p->exit_code >> 8) & 0xff, + case TASK_STOPPED: + if (!p->exit_code) + continue; + if (!(options & (W_TRAPPED|W_STOPPED)) && + !(p->ptrace & PT_PTRACED)) + continue; + read_unlock(&tasklist_lock); + + /* move to end of parent's list to avoid starvation */ + write_lock_irq(&tasklist_lock); + remove_parent(p); + add_parent(p, p->parent); + write_unlock_irq(&tasklist_lock); + retval = ru ? getrusage(p, RUSAGE_BOTH, ru) : 0; + if (!retval && ru) { + retval |= __put_user(SIGCHLD, &info->sig); + retval |= __put_user(0, &info->code); + retval |= __put_user(p->pid, &info->stuff.procinfo.pid); + retval |= __put_user((p->exit_code >> 8) & 0xff, &info->stuff.procinfo.procdata.child.status); - __put_user(p->times.tms_utime, &info->stuff.procinfo.procdata.child.utime); - __put_user(p->times.tms_stime, &info->stuff.procinfo.procdata.child.stime); + retval |= __put_user(p->utime, &info->stuff.procinfo.procdata.child.utime); + retval |= __put_user(p->stime, &info->stuff.procinfo.procdata.child.stime); + } + if (!retval) { p->exit_code = 0; - retval = 0; - goto end_waitsys; - case TASK_ZOMBIE: - current->times.tms_cutime += p->times.tms_utime + p->times.tms_cutime; - current->times.tms_cstime += p->times.tms_stime + p->times.tms_cstime; - if (ru != NULL) - getrusage(p, RUSAGE_BOTH, ru); - __put_user(SIGCHLD, &info->sig); - __put_user(1, &info->code); /* CLD_EXITED */ - __put_user(p->pid, &info->stuff.procinfo.pid); - __put_user((p->exit_code >> 8) & 0xff, - &info->stuff.procinfo.procdata.child.status); - __put_user(p->times.tms_utime, - &info->stuff.procinfo.procdata.child.utime); - __put_user(p->times.tms_stime, - &info->stuff.procinfo.procdata.child.stime); - retval = 0; - if (p->p_opptr != p->p_pptr) { - REMOVE_LINKS(p); - p->p_pptr = p->p_opptr; - SET_LINKS(p); - notify_parent(p, SIGCHLD); - } else - release_task(p); - goto end_waitsys; - default: - continue; + } + goto end_waitsys; + + case TASK_ZOMBIE: + current->cutime += p->utime + p->cutime; + current->cstime += p->stime + p->cstime; + if (ru != NULL) + getrusage(p, RUSAGE_BOTH, ru); + __put_user(SIGCHLD, &info->sig); + __put_user(1, &info->code); /* CLD_EXITED */ + __put_user(p->pid, &info->stuff.procinfo.pid); + __put_user((p->exit_code >> 8) & 0xff, + &info->stuff.procinfo.procdata.child.status); + __put_user(p->utime, + &info->stuff.procinfo.procdata.child.utime); + __put_user(p->stime, + &info->stuff.procinfo.procdata.child.stime); + retval = 0; + if (p->real_parent != p->parent) { + write_lock_irq(&tasklist_lock); + remove_parent(p); + p->parent = p->real_parent; + add_parent(p, p->parent); + do_notify_parent(p, SIGCHLD); + write_unlock_irq(&tasklist_lock); + } else + release_task(p); + goto end_waitsys; + default: + continue; } + tsk = next_thread(tsk); } read_unlock(&tasklist_lock); if (flag) { --- linux-2.5.73/arch/mips/kernel/irq.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -8,18 +8,24 @@ * Copyright (C) 1992 Linus Torvalds * Copyright (C) 1994 - 2000 Ralf Baechle */ +#include #include -#include +#include #include #include #include +#include +#include #include #include #include #include #include +#include +#include #include +#include /* * Controller mappings for all interrupt sources: @@ -31,11 +37,14 @@ irq_desc_t irq_desc[NR_IRQS] __cacheline } }; +static void register_irq_proc (unsigned int irq); + /* * Special irq handlers. */ -void no_action(int cpl, void *dev_id, struct pt_regs *regs) { } +irqreturn_t no_action(int cpl, void *dev_id, struct pt_regs *regs) +{ return IRQ_NONE; } /* * Generic no controller code @@ -68,7 +77,7 @@ struct hw_interrupt_type no_irq_type = { end_none }; -volatile unsigned long irq_err_count, spurious_count; +atomic_t irq_err_count; /* * Generic, controller-independent functions: @@ -76,35 +85,53 @@ volatile unsigned long irq_err_count, sp int show_interrupts(struct seq_file *p, void *v) { + int i, j; struct irqaction * action; unsigned long flags; - int i; - - seq_puts(p, " "); - for (i=0; i < 1 /*smp_num_cpus*/; i++) - seq_printf(p, "CPU%d ", i); + + seq_printf(p, " "); + for (j=0; jtypename); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) seq_printf(p, ", %s", action->name); + seq_putc(p, '\n'); -unlock: +skip: spin_unlock_irqrestore(&irq_desc[i].lock, flags); } - seq_printf(p, "ERR: %10lu\n", irq_err_count); + seq_putc(p, '\n'); + seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); + return 0; } +#ifdef CONFIG_SMP +inline void synchronize_irq(unsigned int irq) +{ + while (irq_desc[irq].status & IRQ_INPROGRESS) + cpu_relax(); +} +#endif + /* * This should really return information about whether * we should do bottom half handling etc. Right now we @@ -114,37 +141,112 @@ unlock: */ int handle_IRQ_event(unsigned int irq, struct pt_regs * regs, struct irqaction * action) { - int status; - int cpu = smp_processor_id(); - - irq_enter(cpu, irq); - - status = 1; /* Force the "do bottom halves" bit */ + int status = 1; /* Force the "do bottom halves" bit */ + int retval = 0; if (!(action->flags & SA_INTERRUPT)) local_irq_enable(); do { status |= action->flags; - action->handler(irq, action->dev_id, regs); + retval |= action->handler(irq, action->dev_id, regs); action = action->next; } while (action); if (status & SA_SAMPLE_RANDOM) add_interrupt_randomness(irq); local_irq_disable(); - irq_exit(cpu, irq); + return retval; +} + +static void __report_bad_irq(int irq, irq_desc_t *desc, irqreturn_t action_ret) +{ + struct irqaction *action; + + if (action_ret != IRQ_HANDLED && action_ret != IRQ_NONE) { + printk(KERN_ERR "irq event %d: bogus return value %x\n", + irq, action_ret); + } else { + printk(KERN_ERR "irq %d: nobody cared!\n", irq); + } + dump_stack(); + printk(KERN_ERR "handlers:\n"); + action = desc->action; + do { + printk(KERN_ERR "[<%p>]", action->handler); + print_symbol(" (%s)", + (unsigned long)action->handler); + printk("\n"); + action = action->next; + } while (action); +} + +static void report_bad_irq(int irq, irq_desc_t *desc, irqreturn_t action_ret) +{ + static int count = 100; + + if (count) { + count--; + __report_bad_irq(irq, desc, action_ret); + } +} + +static int noirqdebug; - return status; +static int __init noirqdebug_setup(char *str) +{ + noirqdebug = 1; + printk("IRQ lockup detection disabled\n"); + return 1; +} + +__setup("noirqdebug", noirqdebug_setup); + +/* + * If 99,900 of the previous 100,000 interrupts have not been handled then + * assume that the IRQ is stuck in some manner. Drop a diagnostic and try to + * turn the IRQ off. + * + * (The other 100-of-100,000 interrupts may have been a correctly-functioning + * device sharing an IRQ with the failing one) + * + * Called under desc->lock + */ +static void note_interrupt(int irq, irq_desc_t *desc, irqreturn_t action_ret) +{ + if (action_ret != IRQ_HANDLED) { + desc->irqs_unhandled++; + if (action_ret != IRQ_NONE) + report_bad_irq(irq, desc, action_ret); + } + + desc->irq_count++; + if (desc->irq_count < 100000) + return; + + desc->irq_count = 0; + if (desc->irqs_unhandled > 99900) { + /* + * The interrupt is stuck + */ + __report_bad_irq(irq, desc, action_ret); + /* + * Now kill the IRQ + */ + printk(KERN_EMERG "Disabling IRQ #%d\n", irq); + desc->status |= IRQ_DISABLED; + desc->handler->disable(irq); + } + desc->irqs_unhandled = 0; } /* * Generic enable/disable code: this just calls * down into the PIC-specific version for the actual * hardware disable after having gotten the irq - * controller lock. + * controller lock. */ - + /** * disable_irq_nosync - disable an irq without waiting * @irq: Interrupt to disable @@ -155,7 +257,7 @@ int handle_IRQ_event(unsigned int irq, s * * This function may be called from IRQ context. */ - + void inline disable_irq_nosync(unsigned int irq) { irq_desc_t *desc = irq_desc + irq; @@ -181,16 +283,11 @@ void inline disable_irq_nosync(unsigned * * This function may be called - with care - from IRQ context. */ - + void disable_irq(unsigned int irq) { disable_irq_nosync(irq); - - if (!local_irq_count(smp_processor_id())) { - do { - barrier(); - } while (irq_desc[irq].status & IRQ_INPROGRESS); - } + synchronize_irq(irq); } /** @@ -202,7 +299,7 @@ void disable_irq(unsigned int irq) * * This function may be called from IRQ context. */ - + void enable_irq(unsigned int irq) { irq_desc_t *desc = irq_desc + irq; @@ -237,7 +334,7 @@ void enable_irq(unsigned int irq) */ asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs) { - /* + /* * We ack quickly, we don't want the irq controller * thinking we're snobs just because some other CPU has * disabled global interrupts (we have already done the @@ -252,6 +349,7 @@ asmlinkage unsigned int do_IRQ(int irq, struct irqaction * action; unsigned int status; + irq_enter(); kstat_cpu(cpu).irqs[irq]++; spin_lock(&desc->lock); desc->handler->ack(irq); @@ -267,7 +365,7 @@ asmlinkage unsigned int do_IRQ(int irq, * use the action we have. */ action = NULL; - if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + if (likely(!(status & (IRQ_DISABLED | IRQ_INPROGRESS)))) { action = desc->action; status &= ~IRQ_PENDING; /* we commit to handling */ status |= IRQ_INPROGRESS; /* we are handling it */ @@ -280,7 +378,7 @@ asmlinkage unsigned int do_IRQ(int irq, a different instance of this same irq, the other processor will take care of it. */ - if (!action) + if (unlikely(!action)) goto out; /* @@ -294,15 +392,19 @@ asmlinkage unsigned int do_IRQ(int irq, * SMP environment. */ for (;;) { + irqreturn_t action_ret; + spin_unlock(&desc->lock); - handle_IRQ_event(irq, regs, action); + action_ret = handle_IRQ_event(irq, ®s, action); spin_lock(&desc->lock); - - if (!(desc->status & IRQ_PENDING)) + if (!noirqdebug) + note_interrupt(irq, desc, action_ret); + if (likely(!(desc->status & IRQ_PENDING))) break; desc->status &= ~IRQ_PENDING; } desc->status &= ~IRQ_INPROGRESS; + out: /* * The ->end() handler has to deal with interrupts which got @@ -311,8 +413,8 @@ out: desc->handler->end(irq); spin_unlock(&desc->lock); - if (softirq_pending(cpu)) - do_softirq(); + irq_exit(); + return 1; } @@ -327,7 +429,7 @@ out: * This call allocates interrupt resources and enables the * interrupt line and IRQ handling. From the point this * call is made your handler function may be invoked. Since - * your handler function must clear any interrupt the board + * your handler function must clear any interrupt the board * raises, you must take care both to initialise your hardware * and to set up the interrupt handler in the right order. * @@ -347,10 +449,10 @@ out: * SA_SAMPLE_RANDOM The interrupt can be used for entropy * */ - -int request_irq(unsigned int irq, - void (*handler)(int, void *, struct pt_regs *), - unsigned long irqflags, + +int request_irq(unsigned int irq, + irqreturn_t (*handler)(int, void *, struct pt_regs *), + unsigned long irqflags, const char * devname, void *dev_id) { @@ -376,7 +478,7 @@ int request_irq(unsigned int irq, return -EINVAL; action = (struct irqaction *) - kmalloc(sizeof(struct irqaction), GFP_KERNEL); + kmalloc(sizeof(struct irqaction), GFP_ATOMIC); if (!action) return -ENOMEM; @@ -405,12 +507,9 @@ int request_irq(unsigned int irq, * does not return until any executing interrupts for this IRQ * have completed. * - * This function may be called from interrupt context. - * - * Bugs: Attempting to free an irq in a handler for the same irq hangs - * the machine. + * This function must not be called from interrupt context. */ - + void free_irq(unsigned int irq, void *dev_id) { irq_desc_t *desc; @@ -439,11 +538,8 @@ void free_irq(unsigned int irq, void *de } spin_unlock_irqrestore(&desc->lock,flags); -#ifdef CONFIG_SMP /* Wait to make sure it's not being used on another CPU */ - while (desc->status & IRQ_INPROGRESS) - barrier(); -#endif + synchronize_irq(irq); kfree(action); return; } @@ -471,7 +567,7 @@ static DECLARE_MUTEX(probe_sem); * and a mask of potential interrupt lines is returned. * */ - + unsigned long probe_irq_on(void) { unsigned int i; @@ -480,22 +576,22 @@ unsigned long probe_irq_on(void) unsigned long delay; down(&probe_sem); - /* + /* * something may have generated an irq long ago and we want to - * flush such a longstanding irq before considering it as spurious. + * flush such a longstanding irq before considering it as spurious. */ for (i = NR_IRQS-1; i > 0; i--) { desc = irq_desc + i; spin_lock_irq(&desc->lock); - if (!irq_desc[i].action) + if (!irq_desc[i].action) irq_desc[i].handler->startup(i); spin_unlock_irq(&desc->lock); } /* Wait for longstanding interrupts to trigger. */ for (delay = jiffies + HZ/50; time_after(delay, jiffies); ) - /* about 20ms delay */ synchronize_irq(); + /* about 20ms delay */ barrier(); /* * enable any unassigned irqs @@ -518,7 +614,7 @@ unsigned long probe_irq_on(void) * Wait for spurious interrupts to trigger */ for (delay = jiffies + HZ/10; time_after(delay, jiffies); ) - /* about 100ms delay */ synchronize_irq(); + /* about 100ms delay */ barrier(); /* * Now filter out any obviously spurious interrupts @@ -550,7 +646,7 @@ unsigned long probe_irq_on(void) * Return a mask of triggered interrupts (this * can handle only legacy ISA interrupts). */ - + /** * probe_irq_mask - scan a bitmap of interrupt lines * @val: mask of interrupts to consider @@ -612,7 +708,7 @@ unsigned int probe_irq_mask(unsigned lon * nothing prevents two IRQ probe callers from overlapping. The * results of this are non-optimal. */ - + int probe_irq_off(unsigned long val) { int i, irq_found, nr_irqs; @@ -693,12 +789,12 @@ int setup_irq(unsigned int irq, struct i if (!shared) { desc->depth = 0; - desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING); + desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS); desc->handler->startup(irq); } spin_unlock_irqrestore(&desc->lock,flags); - /* register_irq_proc(irq); */ + register_irq_proc(irq); return 0; } @@ -713,3 +809,176 @@ void __init init_generic_irq(void) irq_desc[i].handler = &no_irq_type; } } + +EXPORT_SYMBOL(disable_irq_nosync); +EXPORT_SYMBOL(disable_irq); +EXPORT_SYMBOL(enable_irq); +EXPORT_SYMBOL(probe_irq_mask); + +static struct proc_dir_entry * root_irq_dir; +static struct proc_dir_entry * irq_dir [NR_IRQS]; + +#define HEX_DIGITS 8 + +static unsigned int parse_hex_value (const char *buffer, + unsigned long count, unsigned long *ret) +{ + unsigned char hexnum [HEX_DIGITS]; + unsigned long value; + int i; + + if (!count) + return -EINVAL; + if (count > HEX_DIGITS) + count = HEX_DIGITS; + if (copy_from_user(hexnum, buffer, count)) + return -EFAULT; + + /* + * Parse the first 8 characters as a hex string, any non-hex char + * is end-of-string. '00e1', 'e1', '00E1', 'E1' are all the same. + */ + value = 0; + + for (i = 0; i < count; i++) { + unsigned int c = hexnum[i]; + + switch (c) { + case '0' ... '9': c -= '0'; break; + case 'a' ... 'f': c -= 'a'-10; break; + case 'A' ... 'F': c -= 'A'-10; break; + default: + goto out; + } + value = (value << 4) | c; + } +out: + *ret = value; + return 0; +} + +#ifdef CONFIG_SMP + +static struct proc_dir_entry * smp_affinity_entry [NR_IRQS]; + +static unsigned long irq_affinity [NR_IRQS] = { [0 ... NR_IRQS-1] = ~0UL }; +static int irq_affinity_read_proc (char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + if (count < HEX_DIGITS+1) + return -EINVAL; + return sprintf (page, "%08lx\n", irq_affinity[(long)data]); +} + +static int irq_affinity_write_proc (struct file *file, const char *buffer, + unsigned long count, void *data) +{ + int irq = (long) data, full_count = count, err; + unsigned long new_value; + + if (!irq_desc[irq].handler->set_affinity) + return -EIO; + + err = parse_hex_value(buffer, count, &new_value); + + /* + * Do not allow disabling IRQs completely - it's a too easy + * way to make the system unusable accidentally :-) At least + * one online CPU still has to be targeted. + */ + if (!(new_value & cpu_online_map)) + return -EINVAL; + + irq_affinity[irq] = new_value; + irq_desc[irq].handler->set_affinity(irq, new_value); + + return full_count; +} + +#endif + +static int prof_cpu_mask_read_proc (char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + unsigned long *mask = (unsigned long *) data; + if (count < HEX_DIGITS+1) + return -EINVAL; + return sprintf (page, "%08lx\n", *mask); +} + +static int prof_cpu_mask_write_proc (struct file *file, const char *buffer, + unsigned long count, void *data) +{ + unsigned long *mask = (unsigned long *) data, full_count = count, err; + unsigned long new_value; + + err = parse_hex_value(buffer, count, &new_value); + if (err) + return err; + + *mask = new_value; + return full_count; +} + +#define MAX_NAMELEN 10 + +static void register_irq_proc (unsigned int irq) +{ + char name [MAX_NAMELEN]; + + if (!root_irq_dir || (irq_desc[irq].handler == &no_irq_type) || + irq_dir[irq]) + return; + + memset(name, 0, MAX_NAMELEN); + sprintf(name, "%d", irq); + + /* create /proc/irq/1234 */ + irq_dir[irq] = proc_mkdir(name, root_irq_dir); + +#ifdef CONFIG_SMP + { + struct proc_dir_entry *entry; + + /* create /proc/irq/1234/smp_affinity */ + entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]); + + if (entry) { + entry->nlink = 1; + entry->data = (void *)(long)irq; + entry->read_proc = irq_affinity_read_proc; + entry->write_proc = irq_affinity_write_proc; + } + + smp_affinity_entry[irq] = entry; + } +#endif +} + +unsigned long prof_cpu_mask = -1; + +void init_irq_proc (void) +{ + struct proc_dir_entry *entry; + int i; + + /* create /proc/irq */ + root_irq_dir = proc_mkdir("irq", 0); + + /* create /proc/irq/prof_cpu_mask */ + entry = create_proc_entry("prof_cpu_mask", 0600, root_irq_dir); + + if (!entry) + return; + + entry->nlink = 1; + entry->data = (void *)&prof_cpu_mask; + entry->read_proc = prof_cpu_mask_read_proc; + entry->write_proc = prof_cpu_mask_write_proc; + + /* + * Create entries for all existing IRQs. + */ + for (i = 0; i < NR_IRQS; i++) + register_irq_proc(i); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/kernel/irq_cpu.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,117 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * Copyright (C) 2001 Ralf Baechle + * + * This file define the irq handler for MIPS CPU interrupts. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/* + * Almost all MIPS CPUs define 8 interrupt sources. They are typically + * level triggered (i.e., cannot be cleared from CPU; must be cleared from + * device). The first two are software interrupts which we don't really + * use or support. The last one is usually the CPU timer interrupt if + * counter register is present or, for CPUs with an external FPU, by + * convention it's the FPU exception interrupt. + * + * Don't even think about using this on SMP. You have been warned. + * + * This file exports one global function: + * void mips_cpu_irq_init(int irq_base); + */ +#include +#include +#include + +#include +#include +#include + +static int mips_cpu_irq_base; + +static inline void unmask_mips_irq(unsigned int irq) +{ + clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); + set_c0_status(0x100 << (irq - mips_cpu_irq_base)); +} + +static inline void mask_mips_irq(unsigned int irq) +{ + clear_c0_status(0x100 << (irq - mips_cpu_irq_base)); +} + +static inline void mips_cpu_irq_enable(unsigned int irq) +{ + unsigned long flags; + + local_irq_save(flags); + unmask_mips_irq(irq); + local_irq_restore(flags); +} + +static void mips_cpu_irq_disable(unsigned int irq) +{ + unsigned long flags; + + local_irq_save(flags); + mask_mips_irq(irq); + local_irq_restore(flags); +} + +static unsigned int mips_cpu_irq_startup(unsigned int irq) +{ + mips_cpu_irq_enable(irq); + + return 0; +} + +#define mips_cpu_irq_shutdown mips_cpu_irq_disable + +/* + * While we ack the interrupt interrupts are disabled and thus we don't need + * to deal with concurrency issues. Same for mips_cpu_irq_end. + */ +static void mips_cpu_irq_ack(unsigned int irq) +{ + /* Only necessary for soft interrupts */ + clear_c0_cause(1 << (irq - mips_cpu_irq_base + 8)); + + mask_mips_irq(irq); +} + +static void mips_cpu_irq_end(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + unmask_mips_irq(irq); +} + +static hw_irq_controller mips_cpu_irq_controller = { + "MIPS", + mips_cpu_irq_startup, + mips_cpu_irq_shutdown, + mips_cpu_irq_enable, + mips_cpu_irq_disable, + mips_cpu_irq_ack, + mips_cpu_irq_end, + NULL /* no affinity stuff for UP */ +}; + +void __init mips_cpu_irq_init(int irq_base) +{ + int i; + + for (i = irq_base; i < irq_base + 8; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].handler = &mips_cpu_irq_controller; + } + + mips_cpu_irq_base = irq_base; +} --- linux-2.5.73/arch/mips/kernel/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -2,45 +2,45 @@ # Makefile for the Linux/MIPS kernel. # -# EXTRA_AFLAGS = -mips3 -mcpu=r4000 # not used? +extra-y := head.o init_task.o + +obj-y += branch.o cpu-probe.o process.o signal.o entry.o traps.o \ + ptrace.o irq.o reset.o semaphore.o setup.o syscall.o \ + sysmips.o ipc.o scall_o32.o time.o unaligned.o -extra-y := head.o init_task.o -obj-y += branch.o process.o signal.o entry.o \ - traps.o ptrace.o vm86.o ioport.o reset.o \ - semaphore.o setup.o syscall.o sysmips.o \ - ipc.o scall_o32.o unaligned.o obj-$(CONFIG_MODULES) += mips_ksyms.o -ifdef CONFIG_CPU_R3000 -obj-y += r2300_misc.o r2300_fpu.o r2300_switch.o -else -obj-y += r4k_misc.o r4k_switch.o -ifdef CONFIG_CPU_R6000 -obj-y += r6000_fpu.o -else -obj-y += r4k_fpu.o -endif -endif +obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o +obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o +obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_R4000) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_R4300) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o +obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o obj-$(CONFIG_SMP) += smp.o -# Old style irq support, going to die in 2.5. -obj-$(CONFIG_NEW_IRQ) += irq.o -obj-$(CONFIG_ROTTEN_IRQ) += old-irq.o obj-$(CONFIG_I8259) += i8259.o - -# transition from old time.c to new time.c -# some boards uses old-time.c, some use time.c, and some use their own ones -obj-$(CONFIG_OLD_TIME_C) += old-time.o -obj-$(CONFIG_NEW_TIME_C) += time.o +obj-$(CONFIG_IRQ_CPU) += irq_cpu.o obj-$(CONFIG_BINFMT_IRIX) += irixelf.o irixioctl.o irixsig.o sysirix.o \ irixinv.o -obj-$(CONFIG_REMOTE_DEBUG) += gdb-low.o gdb-stub.o -obj-$(CONFIG_PCI) += pci-dma.o +obj-$(CONFIG_KGDB) += gdb-low.o gdb-stub.o obj-$(CONFIG_PROC_FS) += proc.o -ifdef CONFIG_PCI -obj-$(CONFIG_NEW_PCI) += pci.o -obj-$(CONFIG_PCI_AUTO) += pci_auto.o +ifndef CONFIG_MAPPED_PCI_IO +obj-y += pci-dma.o endif + +obj-$(CONFIG_MODULES) += module.o + +EXTRA_AFLAGS := $(CFLAGS) --- linux-2.5.73/arch/mips/kernel/mips_ksyms.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/mips_ksyms.c 2003-06-27 15:56:23.000000000 -0700 @@ -12,9 +12,9 @@ #include #include #include -#include #include #include +#include #include #include @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #ifdef CONFIG_BLK_DEV_FD #include @@ -41,7 +41,9 @@ extern long __strnlen_user_nocheck_asm(c extern long __strnlen_user_asm(const char *s); EXPORT_SYMBOL(mips_machtype); +#ifdef CONFIG_EISA EXPORT_SYMBOL(EISA_bus); +#endif /* * String functions @@ -58,11 +60,8 @@ EXPORT_SYMBOL_NOVERS(strncat); EXPORT_SYMBOL_NOVERS(strnlen); EXPORT_SYMBOL_NOVERS(strrchr); EXPORT_SYMBOL_NOVERS(strstr); -EXPORT_SYMBOL_NOVERS(strsep); EXPORT_SYMBOL(_clear_page); -EXPORT_SYMBOL(enable_irq); -EXPORT_SYMBOL(disable_irq); EXPORT_SYMBOL(kernel_thread); /* @@ -77,15 +76,6 @@ EXPORT_SYMBOL_NOVERS(__strlen_user_asm); EXPORT_SYMBOL_NOVERS(__strnlen_user_nocheck_asm); EXPORT_SYMBOL_NOVERS(__strnlen_user_asm); - -/* - * Functions to control caches. - */ -EXPORT_SYMBOL(_flush_page_to_ram); -EXPORT_SYMBOL(_flush_cache_all); -EXPORT_SYMBOL(_dma_cache_wback_inv); -EXPORT_SYMBOL(_dma_cache_inv); - EXPORT_SYMBOL(invalid_pte_table); /* @@ -97,32 +87,11 @@ EXPORT_SYMBOL(__down_trylock); EXPORT_SYMBOL(__up); /* - * Base address of ports for Intel style I/O. - */ -EXPORT_SYMBOL(mips_io_port_base); - -/* - * Architecture specific stuff. - */ -#ifdef CONFIG_MIPS_JAZZ -EXPORT_SYMBOL(vdma_alloc); -EXPORT_SYMBOL(vdma_free); -EXPORT_SYMBOL(vdma_log2phys); -#endif - -#ifdef CONFIG_SGI_IP22 -EXPORT_SYMBOL(hpc3c0); -#endif - -/* * Kernel hacking ... */ #include #include -int register_fpe(void (*handler)(struct pt_regs *regs, unsigned int fcr31)); -int unregister_fpe(void (*handler)(struct pt_regs *regs, unsigned int fcr31)); - #ifdef CONFIG_VT EXPORT_SYMBOL(screen_info); #endif @@ -132,4 +101,3 @@ EXPORT_SYMBOL(ide_ops); #endif EXPORT_SYMBOL(get_wchan); -EXPORT_SYMBOL(flush_tlb_page); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/kernel/module.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,242 @@ +/* Kernel module help for MIPS. + Copyright (C) 2001 Rusty Russell. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ +#include +#include +#include +#include +#include +#include +#include + +struct mips_hi16 { + struct mips_hi16 *next; + Elf32_Addr *addr; + Elf32_Addr value; +}; + +static struct mips_hi16 *mips_hi16_list; + +#if 0 +#define DEBUGP printk +#else +#define DEBUGP(fmt , ...) +#endif + +void *module_alloc(unsigned long size) +{ + if (size == 0) + return NULL; + return vmalloc(size); +} + + +/* Free memory returned from module_alloc */ +void module_free(struct module *mod, void *module_region) +{ + vfree(module_region); + /* FIXME: If module_region == mod->init_region, trim exception + table entries. */ +} + +/* We don't need anything special. */ +long module_core_size(const Elf32_Ehdr *hdr, + const Elf32_Shdr *sechdrs, + const char *secstrings, + struct module *module) +{ + return module->core_size; +} + +long module_init_size(const Elf32_Ehdr *hdr, + const Elf32_Shdr *sechdrs, + const char *secstrings, + struct module *module) +{ + return module->init_size; +} + +int module_frob_arch_sections(Elf_Ehdr *hdr, + Elf_Shdr *sechdrs, + char *secstrings, + struct module *mod) +{ + return 0; +} + +int apply_relocate(Elf32_Shdr *sechdrs, + const char *strtab, + unsigned int symindex, + unsigned int relsec, + struct module *me) +{ + unsigned int i; + Elf32_Rel *rel = (void *)sechdrs[relsec].sh_offset; + Elf32_Sym *sym; + uint32_t *location; + Elf32_Addr v; + + DEBUGP("Applying relocate section %u to %u\n", relsec, + sechdrs[relsec].sh_info); + for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { + /* This is where to make the change */ + location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_offset + + rel[i].r_offset; + /* This is the symbol it is referring to */ + sym = (Elf32_Sym *)sechdrs[symindex].sh_offset + + ELF32_R_SYM(rel[i].r_info); + if (!sym->st_value) { + printk(KERN_WARNING "%s: Unknown symbol %s\n", + me->name, strtab + sym->st_name); + return -ENOENT; + } + + v = sym->st_value; + + switch (ELF32_R_TYPE(rel[i].r_info)) { + case R_MIPS_NONE: + break; + + case R_MIPS_32: + *location += v; + break; + + case R_MIPS_26: + if (v % 4) + printk(KERN_ERR + "module %s: dangerous relocation\n", + me->name); + return -ENOEXEC; + if ((v & 0xf0000000) != + (((unsigned long)location + 4) & 0xf0000000)) + printk(KERN_ERR + "module %s: relocation overflow\n", + me->name); + return -ENOEXEC; + *location = (*location & ~0x03ffffff) | + ((*location + (v >> 2)) & 0x03ffffff); + break; + + case R_MIPS_HI16: { + struct mips_hi16 *n; + + /* + * We cannot relocate this one now because we don't + * know the value of the carry we need to add. Save + * the information, and let LO16 do the actual + * relocation. + */ + n = (struct mips_hi16 *) kmalloc(sizeof *n, GFP_KERNEL); + n->addr = location; + n->value = v; + n->next = mips_hi16_list; + mips_hi16_list = n; + break; + } + + case R_MIPS_LO16: { + unsigned long insnlo = *location; + Elf32_Addr val, vallo; + + /* Sign extend the addend we extract from the lo insn. */ + vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000; + + if (mips_hi16_list != NULL) { + struct mips_hi16 *l; + + l = mips_hi16_list; + while (l != NULL) { + struct mips_hi16 *next; + unsigned long insn; + + /* + * The value for the HI16 had best be + * the same. + */ + printk(KERN_ERR "module %s: dangerous " + "relocation\n", me->name); + return -ENOEXEC; + + /* + * Do the HI16 relocation. Note that + * we actually don't need to know + * anything about the LO16 itself, + * except where to find the low 16 bits + * of the addend needed by the LO16. + */ + insn = *l->addr; + val = ((insn & 0xffff) << 16) + vallo; + val += v; + + /* + * Account for the sign extension that + * will happen in the low bits. + */ + val = ((val >> 16) + ((val & 0x8000) != + 0)) & 0xffff; + + insn = (insn & ~0xffff) | val; + *l->addr = insn; + + next = l->next; + kfree(l); + l = next; + } + + mips_hi16_list = NULL; + } + + /* + * Ok, we're done with the HI16 relocs. Now deal with + * the LO16. + */ + val = v + vallo; + insnlo = (insnlo & ~0xffff) | (val & 0xffff); + *location = insnlo; + break; + } + + default: + printk(KERN_ERR "module %s: Unknown relocation: %u\n", + me->name, ELF32_R_TYPE(rel[i].r_info)); + return -ENOEXEC; + } + } + return 0; +} + +int apply_relocate_add(Elf32_Shdr *sechdrs, + const char *strtab, + unsigned int symindex, + unsigned int relsec, + struct module *me) +{ + printk(KERN_ERR "module %s: ADD RELOCATION unsupported\n", + me->name); + return -ENOEXEC; +} + +int module_finalize(const Elf_Ehdr *hdr, + const Elf_Shdr *sechdrs, + struct module *me) +{ + return 0; +} + +void module_arch_cleanup(struct module *mod) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/kernel/offset.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,207 @@ +/* + * offset.c: Calculate pt_regs and task_struct offsets. + * + * Copyright (C) 1996 David S. Miller + * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * + * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. + */ +#include +#include +#include +#include + +#include +#include + +#define text(t) __asm__("\n@@@" t) +#define _offset(type, member) (&(((type *)NULL)->member)) + +#define offset(string, ptr, member) \ + __asm__("\n@@@" string "%0" : : "i" (_offset(ptr, member))) +#define constant(string, member) \ + __asm__("\n@@@" string "%x0" : : "i" (member)) +#define size(string, size) \ + __asm__("\n@@@" string "%0" : : "i" (sizeof(size))) +#define linefeed text("") + +void output_ptreg_defines(void) +{ + text("/* MIPS pt_regs offsets. */"); + offset("#define PT_R0 ", struct pt_regs, regs[0]); + offset("#define PT_R1 ", struct pt_regs, regs[1]); + offset("#define PT_R2 ", struct pt_regs, regs[2]); + offset("#define PT_R3 ", struct pt_regs, regs[3]); + offset("#define PT_R4 ", struct pt_regs, regs[4]); + offset("#define PT_R5 ", struct pt_regs, regs[5]); + offset("#define PT_R6 ", struct pt_regs, regs[6]); + offset("#define PT_R7 ", struct pt_regs, regs[7]); + offset("#define PT_R8 ", struct pt_regs, regs[8]); + offset("#define PT_R9 ", struct pt_regs, regs[9]); + offset("#define PT_R10 ", struct pt_regs, regs[10]); + offset("#define PT_R11 ", struct pt_regs, regs[11]); + offset("#define PT_R12 ", struct pt_regs, regs[12]); + offset("#define PT_R13 ", struct pt_regs, regs[13]); + offset("#define PT_R14 ", struct pt_regs, regs[14]); + offset("#define PT_R15 ", struct pt_regs, regs[15]); + offset("#define PT_R16 ", struct pt_regs, regs[16]); + offset("#define PT_R17 ", struct pt_regs, regs[17]); + offset("#define PT_R18 ", struct pt_regs, regs[18]); + offset("#define PT_R19 ", struct pt_regs, regs[19]); + offset("#define PT_R20 ", struct pt_regs, regs[20]); + offset("#define PT_R21 ", struct pt_regs, regs[21]); + offset("#define PT_R22 ", struct pt_regs, regs[22]); + offset("#define PT_R23 ", struct pt_regs, regs[23]); + offset("#define PT_R24 ", struct pt_regs, regs[24]); + offset("#define PT_R25 ", struct pt_regs, regs[25]); + offset("#define PT_R26 ", struct pt_regs, regs[26]); + offset("#define PT_R27 ", struct pt_regs, regs[27]); + offset("#define PT_R28 ", struct pt_regs, regs[28]); + offset("#define PT_R29 ", struct pt_regs, regs[29]); + offset("#define PT_R30 ", struct pt_regs, regs[30]); + offset("#define PT_R31 ", struct pt_regs, regs[31]); + offset("#define PT_LO ", struct pt_regs, lo); + offset("#define PT_HI ", struct pt_regs, hi); + offset("#define PT_EPC ", struct pt_regs, cp0_epc); + offset("#define PT_BVADDR ", struct pt_regs, cp0_badvaddr); + offset("#define PT_STATUS ", struct pt_regs, cp0_status); + offset("#define PT_CAUSE ", struct pt_regs, cp0_cause); + size("#define PT_SIZE ", struct pt_regs); + linefeed; +} + +void output_task_defines(void) +{ + text("/* MIPS task_struct offsets. */"); + offset("#define TASK_STATE ", struct task_struct, state); + offset("#define TASK_THREAD_INFO ", struct task_struct, thread_info); + offset("#define TASK_FLAGS ", struct task_struct, flags); + offset("#define TASK_MM ", struct task_struct, mm); + offset("#define TASK_PID ", struct task_struct, pid); + size( "#define TASK_STRUCT_SIZE ", struct task_struct); + linefeed; +} + +void output_thread_info_defines(void) +{ + text("/* MIPS thread_info offsets. */"); + offset("#define TI_TASK ", struct thread_info, task); + offset("#define TI_EXEC_DOMAIN ", struct thread_info, exec_domain); + offset("#define TI_FLAGS ", struct thread_info, flags); + offset("#define TI_CPU ", struct thread_info, cpu); + offset("#define TI_PRE_COUNT ", struct thread_info, preempt_count); + offset("#define TI_ADDR_LIMIT ", struct thread_info, addr_limit); + offset("#define TI_RESTART_BLOCK ", struct thread_info, restart_block); + linefeed; +} + +void output_thread_defines(void) +{ + text("/* MIPS specific thread_struct offsets. */"); + offset("#define THREAD_REG16 ", struct task_struct, thread.reg16); + offset("#define THREAD_REG17 ", struct task_struct, thread.reg17); + offset("#define THREAD_REG18 ", struct task_struct, thread.reg18); + offset("#define THREAD_REG19 ", struct task_struct, thread.reg19); + offset("#define THREAD_REG20 ", struct task_struct, thread.reg20); + offset("#define THREAD_REG21 ", struct task_struct, thread.reg21); + offset("#define THREAD_REG22 ", struct task_struct, thread.reg22); + offset("#define THREAD_REG23 ", struct task_struct, thread.reg23); + offset("#define THREAD_REG29 ", struct task_struct, thread.reg29); + offset("#define THREAD_REG30 ", struct task_struct, thread.reg30); + offset("#define THREAD_REG31 ", struct task_struct, thread.reg31); + offset("#define THREAD_STATUS ", struct task_struct, \ + thread.cp0_status); + offset("#define THREAD_FPU ", struct task_struct, thread.fpu); + offset("#define THREAD_BVADDR ", struct task_struct, \ + thread.cp0_badvaddr); + offset("#define THREAD_BUADDR ", struct task_struct, \ + thread.cp0_baduaddr); + offset("#define THREAD_ECODE ", struct task_struct, \ + thread.error_code); + offset("#define THREAD_TRAPNO ", struct task_struct, thread.trap_no); + offset("#define THREAD_MFLAGS ", struct task_struct, thread.mflags); + offset("#define THREAD_TRAMP ", struct task_struct, \ + thread.irix_trampoline); + offset("#define THREAD_OLDCTX ", struct task_struct, \ + thread.irix_oldctx); + linefeed; +} + +void output_mm_defines(void) +{ + text("/* Linux mm_struct offsets. */"); + offset("#define MM_USERS ", struct mm_struct, mm_users); + offset("#define MM_PGD ", struct mm_struct, pgd); + offset("#define MM_CONTEXT ", struct mm_struct, context); + linefeed; + constant("#define _PAGE_SIZE ", PAGE_SIZE); + constant("#define _PGD_ORDER ", PGD_ORDER); + constant("#define _PGDIR_SHIFT ", PGDIR_SHIFT); + linefeed; +} + +void output_sc_defines(void) +{ + text("/* Linux sigcontext offsets. */"); + offset("#define SC_REGS ", struct sigcontext, sc_regs); + offset("#define SC_FPREGS ", struct sigcontext, sc_fpregs); + offset("#define SC_MDHI ", struct sigcontext, sc_mdhi); + offset("#define SC_MDLO ", struct sigcontext, sc_mdlo); + offset("#define SC_PC ", struct sigcontext, sc_pc); + offset("#define SC_STATUS ", struct sigcontext, sc_status); + offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr); + offset("#define SC_FPC_EIR ", struct sigcontext, sc_fpc_eir); + offset("#define SC_CAUSE ", struct sigcontext, sc_cause); + offset("#define SC_BADVADDR ", struct sigcontext, sc_badvaddr); + linefeed; +} + +void output_signal_defined(void) +{ + text("/* Linux signal numbers. */"); + constant("#define _SIGHUP ", SIGHUP); + constant("#define _SIGINT ", SIGINT); + constant("#define _SIGQUIT ", SIGQUIT); + constant("#define _SIGILL ", SIGILL); + constant("#define _SIGTRAP ", SIGTRAP); + constant("#define _SIGIOT ", SIGIOT); + constant("#define _SIGABRT ", SIGABRT); + constant("#define _SIGEMT ", SIGEMT); + constant("#define _SIGFPE ", SIGFPE); + constant("#define _SIGKILL ", SIGKILL); + constant("#define _SIGBUS ", SIGBUS); + constant("#define _SIGSEGV ", SIGSEGV); + constant("#define _SIGSYS ", SIGSYS); + constant("#define _SIGPIPE ", SIGPIPE); + constant("#define _SIGALRM ", SIGALRM); + constant("#define _SIGTERM ", SIGTERM); + constant("#define _SIGUSR1 ", SIGUSR1); + constant("#define _SIGUSR2 ", SIGUSR2); + constant("#define _SIGCHLD ", SIGCHLD); + constant("#define _SIGPWR ", SIGPWR); + constant("#define _SIGWINCH ", SIGWINCH); + constant("#define _SIGURG ", SIGURG); + constant("#define _SIGIO ", SIGIO); + constant("#define _SIGSTOP ", SIGSTOP); + constant("#define _SIGTSTP ", SIGTSTP); + constant("#define _SIGCONT ", SIGCONT); + constant("#define _SIGTTIN ", SIGTTIN); + constant("#define _SIGTTOU ", SIGTTOU); + constant("#define _SIGVTALRM ", SIGVTALRM); + constant("#define _SIGPROF ", SIGPROF); + constant("#define _SIGXCPU ", SIGXCPU); + constant("#define _SIGXFSZ ", SIGXFSZ); + linefeed; +} + +void output_irq_cpustat_t_defines(void) +{ + text("/* Linux irq_cpustat_t offsets. */"); + offset("#define IC_SOFTIRQ_PENDING ", irq_cpustat_t, __softirq_pending); + offset("#define IC_SYSCALL_COUNT ", irq_cpustat_t, __syscall_count); + offset("#define IC_KSOFTIRQD_TASK ", irq_cpustat_t, __ksoftirqd_task); + size("#define IC_IRQ_CPUSTAT_T ", irq_cpustat_t); + linefeed; +} --- linux-2.5.73/arch/mips/kernel/old-irq.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,410 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Code to handle x86 style IRQs plus some generic interrupt stuff. - * - * Copyright (C) 1992 Linus Torvalds - * Copyright (C) 1994 - 2001 Ralf Baechle - * - * Old rotten IRQ code. To be killed as soon as everybody had converted or - * in 2.5.0, whatever comes first. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -/* - * The board specific setup routine sets irq_setup to point to a board - * specific setup routine. - */ -void (*irq_setup)(void); - -/* - * Linux has a controller-independent x86 interrupt architecture. - * every controller has a 'controller-template', that is used - * by the main code to do the right thing. Each driver-visible - * interrupt source is transparently wired to the apropriate - * controller. Thus drivers need not be aware of the - * interrupt-controller. - * - * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC, - * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC. - * (IO-APICs assumed to be messaging to Pentium local-APICs) - * - * the code is designed to be easily extended with new/different - * interrupt controllers, without having to do assembly magic. - */ - -/* - * This contains the irq mask for both 8259A irq controllers, it's an - * int so we can deal with the third PIC in some systems like the RM300. - * (XXX This is broken for big endian.) - */ -static unsigned int cached_irq_mask = 0xffff; - -#define __byte(x,y) (((unsigned char *)&(y))[x]) -#define __word(x,y) (((unsigned short *)&(y))[x]) -#define __long(x,y) (((unsigned int *)&(y))[x]) - -#define cached_21 (__byte(0,cached_irq_mask)) -#define cached_A1 (__byte(1,cached_irq_mask)) - -unsigned long spurious_count = 0; - -/* - * (un)mask_irq, disable_irq() and enable_irq() only handle (E)ISA and - * PCI devices. Other onboard hardware needs specific routines. - */ -static inline void mask_irq(unsigned int irq) -{ - cached_irq_mask |= 1 << irq; - if (irq & 8) { - outb(cached_A1, 0xa1); - } else { - outb(cached_21, 0x21); - } -} - -static inline void unmask_irq(unsigned int irq) -{ - cached_irq_mask &= ~(1 << irq); - if (irq & 8) { - outb(cached_A1, 0xa1); - } else { - outb(cached_21, 0x21); - } -} - -void i8259_disable_irq(unsigned int irq_nr) -{ - unsigned long flags; - - save_and_cli(flags); - mask_irq(irq_nr); - restore_flags(flags); -} - -void i8259_enable_irq(unsigned int irq_nr) -{ - unsigned long flags; - save_and_cli(flags); - unmask_irq(irq_nr); - restore_flags(flags); -} - -static struct irqaction *irq_action[NR_IRQS] = { - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL -}; - -int show_interrupts(struct seq_file *p, void *v) -{ - int i; - struct irqaction * action; - unsigned long flags; - - for (i = 0 ; i < 32 ; i++) { - local_irq_save(flags); - action = irq_action[i]; - if (!action) - goto skip; - seq_printf(p, "%2d: %8d %c %s", - i, kstat_cpu(0).irqs[i], - (action->flags & SA_INTERRUPT) ? '+' : ' ', - action->name); - for (action=action->next; action; action = action->next) { - seq_printf(p, ",%s %s", - (action->flags & SA_INTERRUPT) ? " +" : "", - action->name); - } - seq_putc(p, '\n'); -skip: - local_irq_restore(flags); - } - return 0; -} - -static inline void i8259_mask_and_ack_irq(int irq) -{ - cached_irq_mask |= 1 << irq; - - if (irq & 8) { - inb(0xa1); - outb(cached_A1, 0xa1); - outb(0x62, 0x20); /* Specific EOI to cascade */ - outb(0x20, 0xa0); - } else { - inb(0x21); - outb(cached_21, 0x21); - outb(0x20, 0x20); - } -} - -asmlinkage void i8259_do_irq(int irq, struct pt_regs *regs) -{ - struct irqaction *action; - int do_random, cpu; - - cpu = smp_processor_id(); - irq_enter(cpu, irq); - - if (irq >= 16) - goto out; - - i8259_mask_and_ack_irq(irq); - - kstat_cpu(cpu).irqs[irq]++; - - action = *(irq + irq_action); - if (!action) - goto out; - - if (!(action->flags & SA_INTERRUPT)) - local_irq_enable(); - action = *(irq + irq_action); - do_random = 0; - do { - do_random |= action->flags; - action->handler(irq, action->dev_id, regs); - action = action->next; - } while (action); - if (do_random & SA_SAMPLE_RANDOM) - add_interrupt_randomness(irq); - local_irq_disable(); - unmask_irq (irq); - -out: - irq_exit(cpu, irq); -} - -/* - * do_IRQ handles IRQ's that have been installed without the - * SA_INTERRUPT flag: it uses the full signal-handling return - * and runs with other interrupts enabled. All relatively slow - * IRQ's should use this format: notably the keyboard/timer - * routines. - */ -asmlinkage void do_IRQ(int irq, struct pt_regs * regs) -{ - struct irqaction *action; - int do_random, cpu; - - cpu = smp_processor_id(); - irq_enter(cpu, irq); - kstat_cpu(cpu).irqs[irq]++; - - action = *(irq + irq_action); - if (action) { - if (!(action->flags & SA_INTERRUPT)) - local_irq_enable(); - action = *(irq + irq_action); - do_random = 0; - do { - do_random |= action->flags; - action->handler(irq, action->dev_id, regs); - action = action->next; - } while (action); - if (do_random & SA_SAMPLE_RANDOM) - add_interrupt_randomness(irq); - local_irq_disable(); - } - irq_exit(cpu, irq); - - if (softirq_pending(cpu)) - do_softirq(); - - /* unmasking and bottom half handling is done magically for us. */ -} - -int i8259_setup_irq(int irq, struct irqaction * new) -{ - int shared = 0; - struct irqaction *old, **p; - unsigned long flags; - - p = irq_action + irq; - if ((old = *p) != NULL) { - /* Can't share interrupts unless both agree to */ - if (!(old->flags & new->flags & SA_SHIRQ)) - return -EBUSY; - - /* Can't share interrupts unless both are same type */ - if ((old->flags ^ new->flags) & SA_INTERRUPT) - return -EBUSY; - - /* add new interrupt at end of irq queue */ - do { - p = &old->next; - old = *p; - } while (old); - shared = 1; - } - - if (new->flags & SA_SAMPLE_RANDOM) - rand_initialize_irq(irq); - - save_and_cli(flags); - *p = new; - - if (!shared) { - if (is_i8259_irq(irq)) - unmask_irq(irq); -#if (defined(CONFIG_DDB5074) || defined(CONFIG_DDB5476)) - else - nile4_enable_irq(irq_to_nile4(irq)); -#endif - } - restore_flags(flags); - return 0; -} - -/* - * Request_interrupt and free_interrupt ``sort of'' handle interrupts of - * non i8259 devices. They will have to be replaced by architecture - * specific variants. For now we still use this as broken as it is because - * it used to work ... - */ -int request_irq(unsigned int irq, - void (*handler)(int, void *, struct pt_regs *), - unsigned long irqflags, const char * devname, void *dev_id) -{ - int retval; - struct irqaction * action; - - if (irq >= 32) - return -EINVAL; - if (!handler) - return -EINVAL; - - action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL); - if (!action) - return -ENOMEM; - - action->handler = handler; - action->flags = irqflags; - action->mask = 0; - action->name = devname; - action->next = NULL; - action->dev_id = dev_id; - - retval = i8259_setup_irq(irq, action); - - if (retval) - kfree(action); - return retval; -} - -void free_irq(unsigned int irq, void *dev_id) -{ - struct irqaction * action, **p; - unsigned long flags; - - if (irq > 31) { - printk("Trying to free IRQ%d\n",irq); - return; - } - for (p = irq + irq_action; (action = *p) != NULL; p = &action->next) { - if (action->dev_id != dev_id) - continue; - - /* Found it - now free it */ - save_and_cli(flags); - *p = action->next; - if (!irq[irq_action]) - mask_irq(irq); - restore_flags(flags); - kfree(action); - return; - } - printk("Trying to free free IRQ%d\n",irq); -} - -unsigned long probe_irq_on (void) -{ - unsigned int i, irqs = 0; - unsigned long delay; - - /* first, enable any unassigned (E)ISA irqs */ - for (i = 15; i > 0; i--) { - if (!irq_action[i]) { - i8259_enable_irq(i); - irqs |= (1 << i); - } - } - - /* wait for spurious interrupts to mask themselves out again */ - for (delay = jiffies + HZ/10; time_before(jiffies, delay); ) - /* about 100ms delay */; - - /* now filter out any obviously spurious interrupts */ - return irqs & ~cached_irq_mask; -} - -int probe_irq_off (unsigned long irqs) -{ - unsigned int i; - -#ifdef DEBUG - printk("probe_irq_off: irqs=0x%04x irqmask=0x%04x\n", irqs, irqmask); -#endif - irqs &= cached_irq_mask; - if (!irqs) - return 0; - i = ffz(~irqs); - if (irqs != (irqs & (1 << i))) - i = -i; - return i; -} - -void __init i8259_init(void) -{ - /* Init master interrupt controller */ - outb(0x11, 0x20); /* Start init sequence */ - outb(0x00, 0x21); /* Vector base */ - outb(0x04, 0x21); /* edge tiggered, Cascade (slave) on IRQ2 */ - outb(0x01, 0x21); /* Select 8086 mode */ - outb(0xff, 0x21); /* Mask all */ - - /* Init slave interrupt controller */ - outb(0x11, 0xa0); /* Start init sequence */ - outb(0x08, 0xa1); /* Vector base */ - outb(0x02, 0xa1); /* edge triggered, Cascade (slave) on IRQ2 */ - outb(0x01, 0xa1); /* Select 8086 mode */ - outb(0xff, 0xa1); /* Mask all */ - - outb(cached_A1, 0xa1); - outb(cached_21, 0x21); -} - -void __init init_IRQ(void) -{ - /* i8259_init(); */ - irq_setup(); -} --- linux-2.5.73/arch/mips/kernel/old-time.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,518 +0,0 @@ -/* - * Copyright (C) 1991, 1992, 1995 Linus Torvalds - * Copyright (C) 1996 - 2000 Ralf Baechle - * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * Don't use. Deprecated. Dead meat. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -extern volatile unsigned long wall_jiffies; -unsigned long r4k_interval; -extern rwlock_t xtime_lock; - -/* - * Change this if you have some constant time drift - */ -/* This is the value for the PC-style PICs. */ -/* #define USECS_PER_JIFFY (1000020/HZ) */ - -/* This is for machines which generate the exact clock. */ -#define USECS_PER_JIFFY (1000000/HZ) - -/* Cycle counter value at the previous timer interrupt.. */ - -static unsigned int timerhi, timerlo; - -/* - * On MIPS only R4000 and better have a cycle counter. - * - * FIXME: Does playing with the RP bit in c0_status interfere with this code? - */ -static unsigned long do_fast_gettimeoffset(void) -{ - u32 count; - unsigned long res, tmp; - - /* Last jiffy when do_fast_gettimeoffset() was called. */ - static unsigned long last_jiffies; - unsigned long quotient; - - /* - * Cached "1/(clocks per usec)*2^32" value. - * It has to be recalculated once each jiffy. - */ - static unsigned long cached_quotient; - - tmp = jiffies; - - quotient = cached_quotient; - - if (tmp && last_jiffies != tmp) { - last_jiffies = tmp; - __asm__(".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "lwu\t%0,%2\n\t" - "dsll32\t$1,%1,0\n\t" - "or\t$1,$1,%0\n\t" - "ddivu\t$0,$1,%3\n\t" - "mflo\t$1\n\t" - "dsll32\t%0,%4,0\n\t" - "nop\n\t" - "ddivu\t$0,%0,$1\n\t" - "mflo\t%0\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=&r" (quotient) - :"r" (timerhi), - "m" (timerlo), - "r" (tmp), - "r" (USECS_PER_JIFFY) - :"$1"); - cached_quotient = quotient; - } - - /* Get last timer tick in absolute kernel time */ - count = read_32bit_cp0_register(CP0_COUNT); - - /* .. relative to previous jiffy (32 bits is enough) */ - count -= timerlo; - - __asm__("multu\t%1,%2\n\t" - "mfhi\t%0" - :"=r" (res) - :"r" (count), - "r" (quotient)); - - /* - * Due to possible jiffies inconsistencies, we need to check - * the result so that we'll get a timer that is monotonic. - */ - if (res >= USECS_PER_JIFFY) - res = USECS_PER_JIFFY-1; - - return res; -} - -/* This function must be called with interrupts disabled - * It was inspired by Steve McCanne's microtime-i386 for BSD. -- jrs - * - * However, the pc-audio speaker driver changes the divisor so that - * it gets interrupted rather more often - it loads 64 into the - * counter rather than 11932! This has an adverse impact on - * do_gettimeoffset() -- it stops working! What is also not - * good is that the interval that our timer function gets called - * is no longer 10.0002 ms, but 9.9767 ms. To get around this - * would require using a different timing source. Maybe someone - * could use the RTC - I know that this can interrupt at frequencies - * ranging from 8192Hz to 2Hz. If I had the energy, I'd somehow fix - * it so that at startup, the timer code in sched.c would select - * using either the RTC or the 8253 timer. The decision would be - * based on whether there was any other device around that needed - * to trample on the 8253. I'd set up the RTC to interrupt at 1024 Hz, - * and then do some jiggery to have a version of do_timer that - * advanced the clock by 1/1024 s. Every time that reached over 1/100 - * of a second, then do all the old code. If the time was kept correct - * then do_gettimeoffset could just return 0 - there is no low order - * divider that can be accessed. - * - * Ideally, you would be able to use the RTC for the speaker driver, - * but it appears that the speaker driver really needs interrupt more - * often than every 120 us or so. - * - * Anyway, this needs more thought.... pjsg (1993-08-28) - * - * If you are really that interested, you should be reading - * comp.protocols.time.ntp! - */ - -#define TICK_SIZE tick - -static unsigned long do_slow_gettimeoffset(void) -{ - int count; - - static int count_p = LATCH; /* for the first call after boot */ - static unsigned long jiffies_p; - - /* - * cache volatile jiffies temporarily; we have IRQs turned off. - */ - unsigned long jiffies_t; - - /* timer count may underflow right here */ - outb_p(0x00, 0x43); /* latch the count ASAP */ - - count = inb_p(0x40); /* read the latched count */ - - /* - * We do this guaranteed double memory access instead of a _p - * postfix in the previous port access. Wheee, hackady hack - */ - jiffies_t = jiffies; - - count |= inb_p(0x40) << 8; - - /* - * avoiding timer inconsistencies (they are rare, but they happen)... - * there are two kinds of problems that must be avoided here: - * 1. the timer counter underflows - * 2. hardware problem with the timer, not giving us continuous time, - * the counter does small "jumps" upwards on some Pentium systems, - * (see c't 95/10 page 335 for Neptun bug.) - */ - - if( jiffies_t == jiffies_p ) { - if( count > count_p ) { - /* the nutcase */ - - outb_p(0x0A, 0x20); - - /* assumption about timer being IRQ1 */ - if (inb(0x20) & 0x01) { - /* - * We cannot detect lost timer interrupts ... - * well, that's why we call them lost, don't we? :) - * [hmm, on the Pentium and Alpha we can ... sort of] - */ - count -= LATCH; - } else { - printk("do_slow_gettimeoffset(): hardware timer problem?\n"); - } - } - } else - jiffies_p = jiffies_t; - - count_p = count; - - count = ((LATCH-1) - count) * TICK_SIZE; - count = (count + LATCH/2) / LATCH; - - return count; -} - -static unsigned long (*do_gettimeoffset)(void) = do_slow_gettimeoffset; - -/* - * This version of gettimeofday has near microsecond resolution. - */ -void do_gettimeofday(struct timeval *tv) -{ - unsigned long flags; - - read_lock_irqsave (&xtime_lock, flags); - *tv = xtime; - tv->tv_usec += do_gettimeoffset(); - - /* - * xtime is atomically updated in timer_bh. jiffies - wall_jiffies - * is nonzero if the timer bottom half hasnt executed yet. - */ - if (jiffies - wall_jiffies) - tv->tv_usec += USECS_PER_JIFFY; - - read_unlock_irqrestore (&xtime_lock, flags); - - if (tv->tv_usec >= 1000000) { - tv->tv_usec -= 1000000; - tv->tv_sec++; - } -} - -void do_settimeofday(struct timeval *tv) -{ - write_lock_irq (&xtime_lock); - - /* This is revolting. We need to set the xtime.tv_usec - * correctly. However, the value in this location is - * is value at the last tick. - * Discover what correction gettimeofday - * would have done, and then undo it! - */ - tv->tv_usec -= do_gettimeoffset(); - - if (tv->tv_usec < 0) { - tv->tv_usec += 1000000; - tv->tv_sec--; - } - - xtime = *tv; - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; - - write_unlock_irq (&xtime_lock); -} - -/* - * In order to set the CMOS clock precisely, set_rtc_mmss has to be - * called 500 ms after the second nowtime has started, because when - * nowtime is written into the registers of the CMOS clock, it will - * jump to the next second precisely 500 ms later. Check the Motorola - * MC146818A or Dallas DS12887 data sheet for details. - * - * BUG: This routine does not handle hour overflow properly; it just - * sets the minutes. Usually you won't notice until after reboot! - */ -static int set_rtc_mmss(unsigned long nowtime) -{ - int retval = 0; - int real_seconds, real_minutes, cmos_minutes; - unsigned char save_control, save_freq_select; - - save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */ - CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL); - - save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */ - CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); - - cmos_minutes = CMOS_READ(RTC_MINUTES); - if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) - BCD_TO_BIN(cmos_minutes); - - /* - * since we're only adjusting minutes and seconds, - * don't interfere with hour overflow. This avoids - * messing with unknown time zones but requires your - * RTC not to be off by more than 15 minutes - */ - real_seconds = nowtime % 60; - real_minutes = nowtime / 60; - if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) - real_minutes += 30; /* correct for half hour time zone */ - real_minutes %= 60; - - if (abs(real_minutes - cmos_minutes) < 30) { - if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { - BIN_TO_BCD(real_seconds); - BIN_TO_BCD(real_minutes); - } - CMOS_WRITE(real_seconds,RTC_SECONDS); - CMOS_WRITE(real_minutes,RTC_MINUTES); - } else { - printk(KERN_WARNING - "set_rtc_mmss: can't update from %d to %d\n", - cmos_minutes, real_minutes); - retval = -1; - } - - /* The following flags have to be released exactly in this order, - * otherwise the DS12887 (popular MC146818A clone with integrated - * battery and quartz) will not reset the oscillator and will not - * update precisely 500 ms later. You won't find this mentioned in - * the Dallas Semiconductor data sheets, but who believes data - * sheets anyway ... -- Markus Kuhn - */ - CMOS_WRITE(save_control, RTC_CONTROL); - CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); - - return retval; -} - -/* last time the cmos clock got updated */ -static long last_rtc_update; - -/* - * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "do_timer()" routine every clocktick - */ -static void inline -timer_interrupt(int irq, void *dev_id, struct pt_regs * regs) -{ -#ifdef CONFIG_DDB5074 - static unsigned cnt, period, dist; - - if (cnt == 0 || cnt == dist) - ddb5074_led_d2(1); - else if (cnt == 7 || cnt == dist+7) - ddb5074_led_d2(0); - - if (++cnt > period) { - cnt = 0; - /* The hyperbolic function below modifies the heartbeat period - * length in dependency of the current (5min) load. It goes - * through the points f(0)=126, f(1)=86, f(5)=51, - * f(inf)->30. */ - period = ((672<pid) { - extern int _stext; - unsigned long pc = regs->cp0_epc; - - pc -= (unsigned long) &_stext; - pc >>= prof_shift; - /* - * Dont ignore out-of-bounds pc values silently, - * put them into the last histogram slot, so if - * present, they will show up as a sharp peak. - */ - if (pc > prof_len-1) - pc = prof_len-1; - atomic_inc((atomic_t *)&prof_buffer[pc]); - } - } - do_timer(regs); - - /* - * If we have an externally synchronized Linux clock, then update - * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be - * called as close as possible to 500 ms before the new second starts. - */ - read_lock (&xtime_lock); - if ((time_status & STA_UNSYNC) == 0 && - xtime.tv_sec > last_rtc_update + 660 && - xtime.tv_usec >= 500000 - ((unsigned) tick) / 2 && - xtime.tv_usec <= 500000 + ((unsigned) tick) / 2) { - if (set_rtc_mmss(xtime.tv_sec) == 0) - last_rtc_update = xtime.tv_sec; - else - last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */ - } - /* As we return to user mode fire off the other CPU schedulers.. this is - basically because we don't yet share IRQ's around. This message is - rigged to be safe on the 386 - basically it's a hack, so don't look - closely for now.. */ - /*smp_message_pass(MSG_ALL_BUT_SELF, MSG_RESCHEDULE, 0L, 0); */ - read_unlock (&xtime_lock); -} - -static inline void -r4k_timer_interrupt(int irq, void *dev_id, struct pt_regs * regs) -{ - unsigned int count; - - /* - * The cycle counter is only 32 bit which is good for about - * a minute at current count rates of upto 150MHz or so. - */ - count = read_32bit_cp0_register(CP0_COUNT); - timerhi += (count < timerlo); /* Wrap around */ - timerlo = count; - -#ifdef CONFIG_SGI_IP22 - /* Since we don't get anything but r4k timer interrupts, we need to - * set this up so that we'll get one next time. Fortunately since we - * have timerhi/timerlo, we don't care so much if we miss one. So - * we need only ask for the next in r4k_interval counts. On other - * archs we have a real timer, so we don't want this. - */ - write_32bit_cp0_register (CP0_COMPARE, - (unsigned long) (count + r4k_interval)); - kstat_cpu(0).irqs[irq]++; -#endif - - timer_interrupt(irq, dev_id, regs); - - if (!jiffies) - { - /* - * If jiffies has overflowed in this timer_interrupt we must - * update the timer[hi]/[lo] to make do_fast_gettimeoffset() - * quotient calc still valid. -arca - */ - timerhi = timerlo = 0; - } -} - -void indy_r4k_timer_interrupt (struct pt_regs *regs) -{ - static const int INDY_R4K_TIMER_IRQ = 7; - int cpu = smp_processor_id(); - - r4k_timer_interrupt (INDY_R4K_TIMER_IRQ, NULL, regs); - - if (softirq_pending(cpu)) - do_softirq(); -} - -struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, 0, - "timer", NULL, NULL}; - - -void (*board_time_init)(struct irqaction *irq); - -void __init time_init(void) -{ - unsigned int epoch = 0, year, mon, day, hour, min, sec; - int i; - - /* The Linux interpretation of the CMOS clock register contents: - * When the Update-In-Progress (UIP) flag goes from 1 to 0, the - * RTC registers show the second which has precisely just started. - * Let's hope other operating systems interpret the RTC the same way. - */ - /* read RTC exactly on falling edge of update flag */ - for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */ - if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP) - break; - for (i = 0 ; i < 1000000 ; i++) /* must try at least 2.228 ms */ - if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)) - break; - do { /* Isn't this overkill ? UIP above should guarantee consistency */ - sec = CMOS_READ(RTC_SECONDS); - min = CMOS_READ(RTC_MINUTES); - hour = CMOS_READ(RTC_HOURS); - day = CMOS_READ(RTC_DAY_OF_MONTH); - mon = CMOS_READ(RTC_MONTH); - year = CMOS_READ(RTC_YEAR); - } while (sec != CMOS_READ(RTC_SECONDS)); - if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) - { - BCD_TO_BIN(sec); - BCD_TO_BIN(min); - BCD_TO_BIN(hour); - BCD_TO_BIN(day); - BCD_TO_BIN(mon); - BCD_TO_BIN(year); - } - - /* Attempt to guess the epoch. This is the same heuristic as in rtc.c so - no stupid things will happen to timekeeping. Who knows, maybe Ultrix - also uses 1952 as epoch ... */ - if (year > 10 && year < 44) { - epoch = 1980; - } else if (year < 96) { - epoch = 1952; - } - year += epoch; - - write_lock_irq (&xtime_lock); - xtime.tv_sec = mktime(year, mon, day, hour, min, sec); - xtime.tv_usec = 0; - write_unlock_irq (&xtime_lock); - - if (mips_cpu.options & MIPS_CPU_COUNTER) { - write_32bit_cp0_register(CP0_COUNT, 0); - do_gettimeoffset = do_fast_gettimeoffset; - irq0.handler = r4k_timer_interrupt; - } - - board_time_init(&irq0); -} --- linux-2.5.73/arch/mips/kernel/pci_auto.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,323 +0,0 @@ -/* - * PCI autoconfiguration library - * - * Author: Matt Porter - * - * Copyright 2000, 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/* - * Modified for MIPS by Jun Sun, jsun@mvista.com - * - * . Simplify the interface between pci_auto and the rest: a single function. - * . Assign resources from low address to upper address. - * . change most int to u32. - * - * Further modified to include it as mips generic code, ppopov@mvista.com. - */ - -#include -#include -#include -#include - -#include - -#define DEBUG -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - -/* These are used for config access before all the PCI probing has been done. */ -int early_read_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 *val); -int early_read_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 *val); -int early_read_config_dword(struct pci_channel *hose, int bus, int dev_fn, int where, u32 *val); -int early_write_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 val); -int early_write_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 val); -int early_write_config_dword(struct pci_channel *hose, int bus, int dev_fn, int where, u32 val); - -static u32 pciauto_lower_iospc; -static u32 pciauto_upper_iospc; - -static u32 pciauto_lower_memspc; -static u32 pciauto_upper_memspc; - -void __init -pciauto_setup_bars(struct pci_channel *hose, - int current_bus, - int pci_devfn) -{ - u32 bar_response, bar_size, bar_value; - u32 bar, addr_mask, bar_nr = 0; - u32 * upper_limit; - u32 * lower_limit; - int found_mem64 = 0; - - DBG("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n", - current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) ); - - for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar+=4) { - /* Tickle the BAR and get the response */ - early_write_config_dword(hose, - current_bus, - pci_devfn, - bar, - 0xffffffff); - early_read_config_dword(hose, - current_bus, - pci_devfn, - bar, - &bar_response); - - /* If BAR is not implemented go to the next BAR */ - if (!bar_response) - continue; - - /* Check the BAR type and set our address mask */ - if (bar_response & PCI_BASE_ADDRESS_SPACE) { - addr_mask = PCI_BASE_ADDRESS_IO_MASK; - upper_limit = &pciauto_upper_iospc; - lower_limit = &pciauto_lower_iospc; - DBG("PCI Autoconfig: BAR %d, I/O, ", bar_nr); - } else { - if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == - PCI_BASE_ADDRESS_MEM_TYPE_64) - found_mem64 = 1; - - addr_mask = PCI_BASE_ADDRESS_MEM_MASK; - upper_limit = &pciauto_upper_memspc; - lower_limit = &pciauto_lower_memspc; - DBG("PCI Autoconfig: BAR %d, Mem, ", bar_nr); - } - - /* Calculate requested size */ - bar_size = ~(bar_response & addr_mask) + 1; - - /* Allocate a base address */ - bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size; - - /* Write it out and update our limit */ - early_write_config_dword(hose, current_bus, pci_devfn, - bar, bar_value); - - *lower_limit = bar_value + bar_size; - - /* - * If we are a 64-bit decoder then increment to the - * upper 32 bits of the bar and force it to locate - * in the lower 4GB of memory. - */ - if (found_mem64) { - bar += 4; - early_write_config_dword(hose, - current_bus, - pci_devfn, - bar, - 0x00000000); - } - - bar_nr++; - - DBG("size=0x%x, address=0x%x\n", - bar_size, bar_value); - } - -} - -void __init -pciauto_prescan_setup_bridge(struct pci_channel *hose, - int current_bus, - int pci_devfn, - int sub_bus) -{ - int cmdstat; - - /* Configure bus number registers */ - early_write_config_byte(hose, current_bus, pci_devfn, - PCI_PRIMARY_BUS, current_bus); - early_write_config_byte(hose, current_bus, pci_devfn, - PCI_SECONDARY_BUS, sub_bus + 1); - early_write_config_byte(hose, current_bus, pci_devfn, - PCI_SUBORDINATE_BUS, 0xff); - - /* Round memory allocator to 1MB boundary */ - pciauto_upper_memspc &= ~(0x100000 - 1); - - /* Round I/O allocator to 4KB boundary */ - pciauto_upper_iospc &= ~(0x1000 - 1); - - /* Set up memory and I/O filter limits, assume 32-bit I/O space */ - early_write_config_word(hose, current_bus, pci_devfn, PCI_MEMORY_LIMIT, - ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16); - early_write_config_byte(hose, current_bus, pci_devfn, PCI_IO_LIMIT, - ((pciauto_upper_iospc - 1) & 0x0000f000) >> 8); - early_write_config_word(hose, current_bus, pci_devfn, - PCI_IO_LIMIT_UPPER16, - ((pciauto_upper_iospc - 1) & 0xffff0000) >> 16); - - /* We don't support prefetchable memory for now, so disable */ - early_write_config_word(hose, current_bus, pci_devfn, - PCI_PREF_MEMORY_BASE, 0x1000); - early_write_config_word(hose, current_bus, pci_devfn, - PCI_PREF_MEMORY_LIMIT, 0x1000); - - /* Enable memory and I/O accesses, enable bus master */ - early_read_config_dword(hose, current_bus, pci_devfn, PCI_COMMAND, - &cmdstat); - early_write_config_dword(hose, current_bus, pci_devfn, PCI_COMMAND, - cmdstat | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); -} - -void __init -pciauto_postscan_setup_bridge(struct pci_channel *hose, - int current_bus, - int pci_devfn, - int sub_bus) -{ - /* Configure bus number registers */ - early_write_config_byte(hose, current_bus, pci_devfn, - PCI_SUBORDINATE_BUS, sub_bus); - - /* Round memory allocator to 1MB boundary */ - pciauto_upper_memspc &= ~(0x100000 - 1); - early_write_config_word(hose, current_bus, pci_devfn, PCI_MEMORY_BASE, - pciauto_upper_memspc >> 16); - - /* Round I/O allocator to 4KB boundary */ - pciauto_upper_iospc &= ~(0x1000 - 1); - early_write_config_byte(hose, current_bus, pci_devfn, PCI_IO_BASE, - (pciauto_upper_iospc & 0x0000f000) >> 8); - early_write_config_word(hose, current_bus, pci_devfn, - PCI_IO_BASE_UPPER16, pciauto_upper_iospc >> 16); -} - -#define PCIAUTO_IDE_MODE_MASK 0x05 - -int __init -pciauto_bus_scan(struct pci_channel *hose, int current_bus) -{ - int sub_bus; - u32 pci_devfn, pci_class, cmdstat, found_multi=0; - unsigned short vid; - unsigned char header_type; - int devfn_start = 0; - int devfn_stop = 0xff; - - sub_bus = current_bus; - - if (hose->first_devfn) - devfn_start = hose->first_devfn; - if (hose->last_devfn) - devfn_stop = hose->last_devfn; - - for (pci_devfn=devfn_start; pci_devfn> 16) == PCI_CLASS_BRIDGE_PCI) { - DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_SLOT(pci_devfn)); - pciauto_prescan_setup_bridge(hose, current_bus, - pci_devfn, sub_bus); - sub_bus = pciauto_bus_scan(hose, sub_bus+1); - pciauto_postscan_setup_bridge(hose, current_bus, - pci_devfn, sub_bus); - - } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) { - - unsigned char prg_iface; - - early_read_config_byte(hose, current_bus, pci_devfn, - PCI_CLASS_PROG, &prg_iface); - if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) { - DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n"); - continue; - } - } - - /* - * Found a peripheral, enable some standard - * settings - */ - early_read_config_dword(hose, current_bus, pci_devfn, - PCI_COMMAND, &cmdstat); - early_write_config_dword(hose, current_bus, pci_devfn, - PCI_COMMAND, cmdstat | PCI_COMMAND_IO | - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); - early_write_config_byte(hose, current_bus, pci_devfn, - PCI_LATENCY_TIMER, 0x80); - - /* Allocate PCI I/O and/or memory space */ - pciauto_setup_bars(hose, current_bus, pci_devfn); - } - return sub_bus; -} - -int __init -pciauto_assign_resources(int busno, struct pci_channel *hose) -{ - /* setup resource limits */ - pciauto_lower_iospc = hose->io_resource->start; - pciauto_upper_iospc = hose->io_resource->end + 1; - pciauto_lower_memspc = hose->mem_resource->start; - pciauto_upper_memspc = hose->mem_resource->end + 1; - - return pciauto_bus_scan(hose, busno); -} - - -/* - * These functions are used early on before PCI scanning is done - * and all of the pci_dev and pci_bus structures have been created. - */ -static struct pci_dev *fake_pci_dev(struct pci_channel *hose, int busnr, - int devfn) -{ - static struct pci_dev dev; - static struct pci_bus bus; - - dev.bus = &bus; - dev.sysdata = hose; - dev.devfn = devfn; - bus.number = busnr; - bus.ops = hose->pci_ops; - - return &dev; -} - -#define EARLY_PCI_OP(rw, size, type) \ -int early_##rw##_config_##size(struct pci_channel *hose, int bus, \ - int devfn, int offset, type value) \ -{ \ - return pci_##rw##_config_##size(fake_pci_dev(hose, bus, devfn), \ - offset, value); \ -} - -EARLY_PCI_OP(read, byte, u8 *) -EARLY_PCI_OP(read, word, u16 *) -EARLY_PCI_OP(read, dword, u32 *) -EARLY_PCI_OP(write, byte, u8) -EARLY_PCI_OP(write, word, u16) -EARLY_PCI_OP(write, dword, u32) --- linux-2.5.73/arch/mips/kernel/pci.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,168 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * Modified to be mips generic, ppopov@mvista.com - * arch/mips/kernel/pci.c - * Common MIPS PCI routines. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -/* - * This file contains common PCI routines meant to be shared for - * all MIPS machines. - * - * Strategies: - * - * . We rely on pci_auto.c file to assign PCI resources (MEM and IO) - * TODO: this should be optional for some machines where they do have - * a real "pcibios" that does resource assignment. - * - * . We then use pci_scan_bus() to "discover" all the resources for - * later use by Linux. - * - * . We finally reply on a board supplied function, pcibios_fixup_irq(), to - * to assign the interrupts. We may use setup-irq.c under drivers/pci - * later. - * - * . Specifically, we will *NOT* use pci_assign_unassigned_resources(), - * because we assume all PCI devices should have the resources correctly - * assigned and recorded. - * - * Limitations: - * - * . We "collapse" all IO and MEM spaces in sub-buses under a top-level bus - * into a contiguous range. - * - * . In the case of Memory space, the rnage is 1:1 mapping with CPU physical - * address space. - * - * . In the case of IO space, it starts from 0, and the beginning address - * is mapped to KSEG0ADDR(mips_io_port) in the CPU physical address. - * - * . These are the current MIPS limitations (by ioremap, etc). In the - * future, we may remove them. - * - * Credits: - * Most of the code are derived from the pci routines from PPC and Alpha, - * which were mostly writtne by - * Cort Dougan, cort@fsmlabs.com - * Matt Porter, mporter@mvista.com - * Dave Rusling david.rusling@reo.mts.dec.com - * David Mosberger davidm@cs.arizona.edu - */ -#include -#include -#include -#include - -#include - -extern void pcibios_fixup(void); -extern void pcibios_fixup_irqs(void); - -struct pci_fixup pcibios_fixups[] = { - { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources }, - { 0 } -}; - -extern int pciauto_assign_resources(int busno, struct pci_channel * hose); - -void __init pcibios_init(void) -{ - struct pci_channel *p; - struct pci_bus *bus; - int busno; - -#ifdef CONFIG_PCI_AUTO - /* assign resources */ - busno=0; - for (p= mips_pci_channels; p->pci_ops != NULL; p++) { - busno = pciauto_assign_resources(busno, p) + 1; - } -#endif - - /* scan the buses */ - busno = 0; - for (p= mips_pci_channels; p->pci_ops != NULL; p++) { - bus = pci_scan_bus(busno, p->pci_ops, p); - busno = bus->subordinate+1; - } - - /* machine dependent fixups */ - pcibios_fixup(); - /* fixup irqs (board specific routines) */ - pcibios_fixup_irqs(); -} - -int pcibios_enable_device(struct pci_dev *dev) -{ - /* pciauto_assign_resources() will enable all devices found */ - return 0; -} - -unsigned long __init pci_bridge_check_io(struct pci_dev *bridge) -{ - u16 io; - - pci_read_config_word(bridge, PCI_IO_BASE, &io); - if (!io) { - pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); - pci_read_config_word(bridge, PCI_IO_BASE, &io); - pci_write_config_word(bridge, PCI_IO_BASE, 0x0); - } - if (io) - return IORESOURCE_IO; - printk(KERN_WARNING "PCI: bridge %s does not support I/O forwarding!\n", - bridge->name); - return 0; -} - -void __init pcibios_fixup_bus(struct pci_bus *bus) -{ - /* Propogate hose info into the subordinate devices. */ - - struct pci_channel *hose = bus->sysdata; - struct pci_dev *dev = bus->self; - - if (!dev) { - /* Root bus */ - bus->resource[0] = hose->io_resource; - bus->resource[1] = hose->mem_resource; - } else { - /* This is a bridge. Do not care how it's initialized, - just link its resources to the bus ones */ - int i; - - for(i=0; i<3; i++) { - bus->resource[i] = - &dev->resource[PCI_BRIDGE_RESOURCES+i]; - bus->resource[i]->name = bus->name; - } - bus->resource[0]->flags |= pci_bridge_check_io(dev); - bus->resource[1]->flags |= IORESOURCE_MEM; - /* For now, propagate hose limits to the bus; - we'll adjust them later. */ - bus->resource[0]->end = hose->io_resource->end; - bus->resource[1]->end = hose->mem_resource->end; - /* Turn off downstream PF memory address range by default */ - bus->resource[2]->start = 1024*1024; - bus->resource[2]->end = bus->resource[2]->start - 1; - } -} - -char *pcibios_setup(char *str) -{ - return str; -} - -void -pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) -{ - /* this should not be called */ -} --- linux-2.5.73/arch/mips/kernel/pci-dma.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/pci-dma.c 2003-06-27 15:56:23.000000000 -0700 @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -20,18 +21,23 @@ void *pci_alloc_consistent(struct pci_de { void *ret; int gfp = GFP_ATOMIC; + struct pci_bus *bus = NULL; +#ifdef CONFIG_ISA if (hwdev == NULL || hwdev->dma_mask != 0xffffffff) gfp |= GFP_DMA; +#endif ret = (void *) __get_free_pages(gfp, get_order(size)); if (ret != NULL) { memset(ret, 0, size); -#ifndef CONFIG_COHERENT_IO + if (hwdev) + bus = hwdev->bus; + *dma_handle = bus_to_baddr(bus, __pa(ret)); +#ifdef CONFIG_NONCOHERENT_IO dma_cache_wback_inv((unsigned long) ret, size); - ret = KSEG1ADDR(ret); + ret = UNCAC_ADDR(ret); #endif - *dma_handle = virt_to_bus(ret); } return ret; @@ -42,8 +48,11 @@ void pci_free_consistent(struct pci_dev { unsigned long addr = (unsigned long) vaddr; -#ifndef CONFIG_COHERENT_IO - addr = KSEG0ADDR(addr); +#ifdef CONFIG_NONCOHERENT_IO + addr = CAC_ADDR(addr); #endif free_pages(addr, get_order(size)); } + +EXPORT_SYMBOL(pci_alloc_consistent); +EXPORT_SYMBOL(pci_free_consistent); --- linux-2.5.73/arch/mips/kernel/proc.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/proc.c 2003-06-27 15:56:23.000000000 -0700 @@ -8,102 +8,136 @@ #include #include #include +#include #include #include #include #include #include -extern unsigned long unaligned_instructions; unsigned int vced_count, vcei_count; -#ifndef CONFIG_CPU_HAS_LLSC -unsigned long ll_ops, sc_ops; -#endif -/* - * BUFFER is PAGE_SIZE bytes long. - * - * Currently /proc/cpuinfo is being abused to print data about the - * number of date/instruction cacheflushes. - */ -int get_cpuinfo(char *buffer) +static const char *cpu_name[] = { + [CPU_UNKNOWN] "unknown", + [CPU_R2000] "R2000", + [CPU_R3000] "R3000", + [CPU_R3000A] "R3000A", + [CPU_R3041] "R3041", + [CPU_R3051] "R3051", + [CPU_R3052] "R3052", + [CPU_R3081] "R3081", + [CPU_R3081E] "R3081E", + [CPU_R4000PC] "R4000PC", + [CPU_R4000SC] "R4000SC", + [CPU_R4000MC] "R4000MC", + [CPU_R4200] "R4200", + [CPU_R4400PC] "R4400PC", + [CPU_R4400SC] "R4400SC", + [CPU_R4400MC] "R4400MC", + [CPU_R4600] "R4600", + [CPU_R6000] "R6000", + [CPU_R6000A] "R6000A", + [CPU_R8000] "R8000", + [CPU_R10000] "R10000", + [CPU_R4300] "R4300", + [CPU_R4650] "R4650", + [CPU_R4700] "R4700", + [CPU_R5000] "R5000", + [CPU_R5000A] "R5000A", + [CPU_R4640] "R4640", + [CPU_NEVADA] "Nevada", + [CPU_RM7000] "RM7000", + [CPU_R5432] "R5432", + [CPU_4KC] "MIPS 4Kc", + [CPU_5KC] "MIPS 5Kc", + [CPU_R4310] "R4310", + [CPU_SB1] "SiByte SB1", + [CPU_TX3912] "TX3912", + [CPU_TX3922] "TX3922", + [CPU_TX3927] "TX3927", + [CPU_AU1000] "Au1000", + [CPU_AU1500] "Au1500", + [CPU_4KEC] "MIPS 4KEc", + [CPU_4KSC] "MIPS 4KSc", + [CPU_VR41XX] "NEC Vr41xx", + [CPU_R5500] "R5500", + [CPU_TX49XX] "TX49xx", + [CPU_20KC] "MIPS 20Kc", + [CPU_VR4111] "NEC VR4111", + [CPU_VR4121] "NEC VR4121", + [CPU_VR4122] "NEC VR4122", + [CPU_VR4131] "NEC VR4131", + [CPU_VR4181] "NEC VR4181", + [CPU_VR4181A] "NEC VR4181A", + [CPU_SR71000] "Sandcraft SR71000" +}; + + +static int show_cpuinfo(struct seq_file *m, void *v) { + unsigned int version = current_cpu_data.processor_id; + unsigned int fp_vers = current_cpu_data.fpu_id; + unsigned long n = (unsigned long) v - 1; char fmt [64]; - const char *cpu_name[] = CPU_NAMES; - const char *mach_group_names[] = GROUP_NAMES; - const char *mach_unknown_names[] = GROUP_UNKNOWN_NAMES; - const char *mach_jazz_names[] = GROUP_JAZZ_NAMES; - const char *mach_dec_names[] = GROUP_DEC_NAMES; - const char *mach_arc_names[] = GROUP_ARC_NAMES; - const char *mach_sni_rm_names[] = GROUP_SNI_RM_NAMES; - const char *mach_acn_names[] = GROUP_ACN_NAMES; - const char *mach_sgi_names[] = GROUP_SGI_NAMES; - const char *mach_cobalt_names[] = GROUP_COBALT_NAMES; - const char *mach_nec_ddb_names[] = GROUP_NEC_DDB_NAMES; - const char *mach_baget_names[] = GROUP_BAGET_NAMES; - const char *mach_cosine_names[] = GROUP_COSINE_NAMES; - const char *mach_galileo_names[] = GROUP_GALILEO_NAMES; - const char *mach_momenco_names[] = GROUP_MOMENCO_NAMES; - const char *mach_ite_names[] = GROUP_ITE_NAMES; - const char *mach_philips_names[] = GROUP_PHILIPS_NAMES; - const char *mach_globespan_names[] = GROUP_GLOBESPAN_NAMES; - const char *mach_sibyte_names[] = GROUP_SIBYTE_NAMES; - const char *mach_toshiba_names[] = GROUP_TOSHIBA_NAMES; - const char *mach_alchemy_names[] = GROUP_ALCHEMY_NAMES; - const char **mach_group_to_name[] = { mach_unknown_names, - mach_jazz_names, mach_dec_names, mach_arc_names, - mach_sni_rm_names, mach_acn_names, mach_sgi_names, - mach_cobalt_names, mach_nec_ddb_names, mach_baget_names, - mach_cosine_names, mach_galileo_names, mach_momenco_names, - mach_ite_names, mach_philips_names, mach_globespan_names, - mach_sibyte_names, mach_toshiba_names, mach_alchemy_names}; - unsigned int version = read_32bit_cp0_register(CP0_PRID); - int len; - - len = sprintf(buffer, "cpu\t\t\t: MIPS\n"); - len += sprintf(buffer + len, "cpu model\t\t: %s V%d.%d\n", - cpu_name[mips_cpu.cputype <= CPU_LAST ? - mips_cpu.cputype : CPU_UNKNOWN], - (version >> 4) & 0x0f, version & 0x0f); - len += sprintf(buffer + len, "system type\t\t: %s %s\n", - mach_group_names[mips_machgroup], - mach_group_to_name[mips_machgroup][mips_machtype]); - len += sprintf(buffer + len, "BogoMIPS\t\t: %lu.%02lu\n", - loops_per_jiffy/(500000/HZ), - (loops_per_jiffy/(5000/HZ)) % 100); -#if defined (__MIPSEB__) - len += sprintf(buffer + len, "byteorder\t\t: big endian\n"); -#endif -#if defined (__MIPSEL__) - len += sprintf(buffer + len, "byteorder\t\t: little endian\n"); +#ifdef CONFIG_SMP + if (!CPUMASK_TSTB(cpu_online_map, n)) + return 0; #endif - len += sprintf(buffer + len, "unaligned accesses\t: %lu\n", - unaligned_instructions); - len += sprintf(buffer + len, "wait instruction\t: %s\n", - cpu_wait ? "yes" : "no"); - len += sprintf(buffer + len, "microsecond timers\t: %s\n", - (mips_cpu.options & MIPS_CPU_COUNTER) ? "yes" : "no"); - len += sprintf(buffer + len, "extra interrupt vector\t: %s\n", - (mips_cpu.options & MIPS_CPU_DIVEC) ? "yes" : "no"); - len += sprintf(buffer + len, "hardware watchpoint\t: %s\n", - watch_available ? "yes" : "no"); + + /* + * For the first processor also print the system type + */ + if (n == 0) + seq_printf(m, "system type\t\t: %s\n", get_system_type()); + + seq_printf(m, "processor\t\t: %ld\n", n); + sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", + cpu_has_fpu ? " FPU V%d.%d" : ""); + seq_printf(m, fmt, cpu_name[current_cpu_data.cputype <= CPU_LAST ? + current_cpu_data.cputype : CPU_UNKNOWN], + (version >> 4) & 0x0f, version & 0x0f, + (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); + seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n", + loops_per_jiffy / (500000/HZ), + (loops_per_jiffy / (5000/HZ)) % 100); + seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); + seq_printf(m, "microsecond timers\t: %s\n", + cpu_has_counter ? "yes" : "no"); + seq_printf(m, "tlb_entries\t\t: %d\n", current_cpu_data.tlbsize); + seq_printf(m, "extra interrupt vector\t: %s\n", + cpu_has_divec ? "yes" : "no"); + seq_printf(m, "hardware watchpoint\t: %s\n", + cpu_has_watch ? "yes" : "no"); sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", - (mips_cpu.options & MIPS_CPU_VCE) ? "%d" : "not available"); - len += sprintf(buffer + len, fmt, 'D', vced_count); - len += sprintf(buffer + len, fmt, 'I', vcei_count); - -#ifndef CONFIG_CPU_HAS_LLSC - len += sprintf(buffer + len, "ll emulations\t\t: %lu\n", - ll_ops); - len += sprintf(buffer + len, "sc emulations\t\t: %lu\n", - sc_ops); -#endif - return len; + cpu_has_vce ? "%d" : "not available"); + seq_printf(m, fmt, 'D', vced_count); + seq_printf(m, fmt, 'I', vcei_count); + + return 0; } -void init_irq_proc(void) +static void *c_start(struct seq_file *m, loff_t *pos) { - /* Nothing, for now. */ + unsigned long i = *pos; + + return i < NR_CPUS ? (void *) (i + 1) : NULL; } + +static void *c_next(struct seq_file *m, void *v, loff_t *pos) +{ + ++*pos; + return c_start(m, pos); +} + +static void c_stop(struct seq_file *m, void *v) +{ +} + +struct seq_operations cpuinfo_op = { + .start = c_start, + .next = c_next, + .stop = c_stop, + .show = show_cpuinfo, +}; --- linux-2.5.73/arch/mips/kernel/process.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/process.c 2003-06-27 15:56:23.000000000 -0700 @@ -6,86 +6,95 @@ * Copyright (C) 1994 - 2000 by Ralf Baechle and others. * Copyright (C) 1999 Silicon Graphics, Inc. */ -#include #include #include #include #include #include #include -#include +#include #include #include #include #include #include +#include +#include #include #include +#include #include #include #include #include -#include +#include #include #include #include #include +#include -void cpu_idle(void) +/* + * We use this if we don't have any better idle routine.. + * (This to kill: kernel/platform.c. + */ +void default_idle (void) +{ +} + +/* + * The idle thread. There's no useful work to be done, so just try to conserve + * power and have a low exit latency (ie sit in a loop waiting for somebody to + * say that they'd like to reschedule) + */ +ATTRIB_NORET void cpu_idle(void) { /* endless idle loop with no priority at all */ - current->nice = 20; - init_idle(); while (1) { while (!need_resched()) if (cpu_wait) (*cpu_wait)(); schedule(); - check_pgt_cache(); } } -struct task_struct *last_task_used_math = NULL; - asmlinkage void ret_from_fork(void); +void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) +{ + regs->cp0_status &= ~(ST0_CU0|ST0_KSU|ST0_CU1); + regs->cp0_status |= KU_USER; + current->used_math = 0; + loose_fpu(); + regs->cp0_epc = pc; + regs->regs[29] = sp; + current_thread_info()->addr_limit = USER_DS; +} + void exit_thread(void) { - /* Forget lazy fpu state */ - if (last_task_used_math == current) { - set_cp0_status(ST0_CU1); - __asm__ __volatile__("cfc1\t$0,$31"); - last_task_used_math = NULL; - } } void flush_thread(void) { - /* Forget lazy fpu state */ - if (last_task_used_math == current) { - set_cp0_status(ST0_CU1); - __asm__ __volatile__("cfc1\t$0,$31"); - last_task_used_math = NULL; - } } int copy_thread(int nr, unsigned long clone_flags, unsigned long usp, unsigned long unused, struct task_struct * p, struct pt_regs * regs) { + struct thread_info *ti = p->thread_info; struct pt_regs * childregs; long childksp; - extern void save_fp(void*); - childksp = (unsigned long)p + KERNEL_STACK_SIZE - 32; + childksp = (unsigned long)ti + KERNEL_STACK_SIZE - 32; + + if (is_fpu_owner()) { + save_fp(p); + } - if (last_task_used_math == current) - if (mips_cpu.options & MIPS_CPU_FPU) { - set_cp0_status(ST0_CU1); - save_fp(p); - } /* set up new TSS. */ childregs = (struct pt_regs *) childksp - 1; *childregs = *regs; @@ -101,12 +110,12 @@ int copy_thread(int nr, unsigned long cl regs->regs[3] = 0; } if (childregs->cp0_status & ST0_CU0) { - childregs->regs[28] = (unsigned long) p; + childregs->regs[28] = (unsigned long) ti; childregs->regs[29] = childksp; - p->thread.current_ds = KERNEL_DS; + ti->addr_limit = KERNEL_DS; } else { childregs->regs[29] = usp; - p->thread.current_ds = USER_DS; + ti->addr_limit = USER_DS; } p->thread.reg29 = (unsigned long) childregs; p->thread.reg31 = (unsigned long) ret_from_fork; @@ -115,9 +124,10 @@ int copy_thread(int nr, unsigned long cl * New tasks lose permission to use the fpu. This accelerates context * switching for most programs since they don't use the fpu. */ - p->thread.cp0_status = read_32bit_cp0_register(CP0_STATUS) & + p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1|KU_MASK); childregs->cp0_status &= ~(ST0_CU2|ST0_CU1); + p->set_child_tid = p->clear_child_tid = NULL; return 0; } @@ -125,29 +135,8 @@ int copy_thread(int nr, unsigned long cl /* Fill in the fpu structure for a core dump.. */ int dump_fpu(struct pt_regs *regs, elf_fpregset_t *r) { - /* We actually store the FPU info in the task->thread - * area. - */ - if(regs->cp0_status & ST0_CU1) { - memcpy(r, ¤t->thread.fpu, sizeof(current->thread.fpu)); - return 1; - } - return 0; /* Task didn't use the fpu at all. */ -} - -/* Fill in the user structure for a core dump.. */ -void dump_thread(struct pt_regs *regs, struct user *dump) -{ - dump->magic = CMAGIC; - dump->start_code = current->mm->start_code; - dump->start_data = current->mm->start_data; - dump->start_stack = regs->regs[29] & ~(PAGE_SIZE - 1); - dump->u_tsize = (current->mm->end_code - dump->start_code) >> PAGE_SHIFT; - dump->u_dsize = (current->mm->brk + (PAGE_SIZE - 1) - dump->start_data) >> PAGE_SHIFT; - dump->u_ssize = - (current->mm->start_stack - dump->start_stack + PAGE_SIZE - 1) >> PAGE_SHIFT; - memcpy(&dump->regs[0], regs, sizeof(struct pt_regs)); - memcpy(&dump->regs[EF_SIZE/4], ¤t->thread.fpu, sizeof(current->thread.fpu)); + memcpy(r, ¤t->thread.fpu, sizeof(current->thread.fpu)); + return 1; } /* @@ -158,35 +147,107 @@ int kernel_thread(int (*fn)(void *), voi long retval; __asm__ __volatile__( - ".set noreorder \n" - " move $6,$sp \n" - " move $4,%5 \n" - " li $2,%1 \n" - " syscall \n" - " beq $6,$sp,1f \n" - " subu $sp,32 \n" /* delay slot */ - " jalr %4 \n" - " move $4,%3 \n" /* delay slot */ - " move $4,$2 \n" - " li $2,%2 \n" - " syscall \n" - "1: addiu $sp,32 \n" - " move %0,$2 \n" - ".set reorder" - :"=r" (retval) - :"i" (__NR_clone), "i" (__NR_exit), - "r" (arg), "r" (fn), - "r" (flags | CLONE_VM | CLONE_UNTRACED) + " .set noreorder \n" + " move $6, $sp \n" + " move $4, %5 \n" + " li $2, %1 \n" + " syscall \n" + " beq $6, $sp, 1f \n" + " subu $sp, 32 \n" + " jalr %4 \n" + " move $4, %3 \n" + " move $4, $2 \n" + " li $2, %2 \n" + " syscall \n" + "1: addiu $sp, 32 \n" + " move %0, $2 \n" + " .set reorder" + : "=r" (retval) + : "i" (__NR_clone), "i" (__NR_exit), "r" (arg), "r" (fn), + "r" (flags | CLONE_VM | CLONE_UNTRACED) /* * The called subroutine might have destroyed any of the * at, result, argument or temporary registers ... */ - :"$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", - "$9","$10","$11","$12","$13","$14","$15","$24","$25"); + : "$2", "$3", "$4", "$5", "$6", "$7", "$8", + "$9","$10","$11","$12","$13","$14","$15","$24","$25", "$31"); return retval; } +struct mips_frame_info { + int frame_offset; + int pc_offset; +}; +static struct mips_frame_info schedule_frame; +static struct mips_frame_info schedule_timeout_frame; +static struct mips_frame_info sleep_on_frame; +static struct mips_frame_info sleep_on_timeout_frame; +static struct mips_frame_info wait_for_completion_frame; +static int mips_frame_info_initialized; +static int __init get_frame_info(struct mips_frame_info *info, void *func) +{ + int i; + union mips_instruction *ip = (union mips_instruction *)func; + info->pc_offset = -1; + info->frame_offset = -1; + for (i = 0; i < 128; i++, ip++) { + /* if jal, jalr, jr, stop. */ + if (ip->j_format.opcode == jal_op || + (ip->r_format.opcode == spec_op && + (ip->r_format.func == jalr_op || + ip->r_format.func == jr_op))) + break; + if (ip->i_format.opcode == sw_op && + ip->i_format.rs == 29) { + /* sw $ra, offset($sp) */ + if (ip->i_format.rt == 31) { + if (info->pc_offset != -1) + break; + info->pc_offset = + ip->i_format.simmediate / sizeof(long); + } + /* sw $s8, offset($sp) */ + if (ip->i_format.rt == 30) { + if (info->frame_offset != -1) + break; + info->frame_offset = + ip->i_format.simmediate / sizeof(long); + } + } + } + if (info->pc_offset == -1 || info->frame_offset == -1) { + printk("Can't analyze prologue code at %p\n", func); + info->pc_offset = -1; + info->frame_offset = -1; + return -1; + } + + return 0; +} +void __init frame_info_init(void) +{ + mips_frame_info_initialized = + !get_frame_info(&schedule_frame, schedule) && + !get_frame_info(&schedule_timeout_frame, schedule_timeout) && + !get_frame_info(&sleep_on_frame, sleep_on) && + !get_frame_info(&sleep_on_timeout_frame, sleep_on_timeout) && + !get_frame_info(&wait_for_completion_frame, wait_for_completion); +} + +unsigned long thread_saved_pc(struct thread_struct *t) +{ + extern void ret_from_fork(void); + + /* New born processes are a special case */ + if (t->reg31 == (unsigned long) ret_from_fork) + return t->reg31; + + if (schedule_frame.pc_offset < 0) + return 0; + return ((unsigned long *)t->reg29)[schedule_frame.pc_offset]; +} + /* * These bracket the sleeping functions.. */ @@ -195,7 +256,7 @@ extern void scheduling_functions_end_her #define first_sched ((unsigned long) scheduling_functions_start_here) #define last_sched ((unsigned long) scheduling_functions_end_here) -/* get_wchan - a maintenance nightmare ... */ +/* get_wchan - a maintenance nightmare^W^Wpain in the ass ... */ unsigned long get_wchan(struct task_struct *p) { unsigned long frame, pc; @@ -203,6 +264,8 @@ unsigned long get_wchan(struct task_stru if (!p || p == current || p->state == TASK_RUNNING) return 0; + if (!mips_frame_info_initialized) + return 0; pc = thread_saved_pc(&p->thread); if (pc < first_sched || pc >= last_sched) { return pc; @@ -216,26 +279,33 @@ unsigned long get_wchan(struct task_stru goto schedule_timeout_caller; if (pc >= (unsigned long)interruptible_sleep_on) goto schedule_caller; + if (pc >= (unsigned long)wait_for_completion) + goto schedule_caller; goto schedule_timeout_caller; schedule_caller: - frame = ((unsigned long *)p->thread.reg30)[9]; - pc = ((unsigned long *)frame)[11]; + frame = ((unsigned long *)p->thread.reg30)[schedule_frame.frame_offset]; + if (pc >= (unsigned long) sleep_on) + pc = ((unsigned long *)frame)[sleep_on_frame.pc_offset]; + else + pc = ((unsigned long *)frame)[wait_for_completion_frame.pc_offset]; return pc; schedule_timeout_caller: - /* Must be schedule_timeout ... */ - pc = ((unsigned long *)p->thread.reg30)[10]; - frame = ((unsigned long *)p->thread.reg30)[9]; - - /* The schedule_timeout frame ... */ - pc = ((unsigned long *)frame)[14]; - frame = ((unsigned long *)frame)[13]; + /* + * The schedule_timeout frame + */ + frame = ((unsigned long *)p->thread.reg30)[schedule_frame.frame_offset]; + + /* + * frame now points to sleep_on_timeout's frame + */ + pc = ((unsigned long *)frame)[schedule_timeout_frame.pc_offset]; if (pc >= first_sched && pc < last_sched) { - /* schedule_timeout called by interruptible_sleep_on_timeout */ - pc = ((unsigned long *)frame)[11]; - frame = ((unsigned long *)frame)[10]; + /* schedule_timeout called by [interruptible_]sleep_on_timeout */ + frame = ((unsigned long *)frame)[schedule_timeout_frame.frame_offset]; + pc = ((unsigned long *)frame)[sleep_on_timeout_frame.pc_offset]; } return pc; --- linux-2.5.73/arch/mips/kernel/ptrace.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/ptrace.c 2003-06-27 15:56:23.000000000 -0700 @@ -11,6 +11,7 @@ * Copyright (C) 1999 MIPS Technologies, Inc. */ #include +#include #include #include #include @@ -19,8 +20,8 @@ #include #include #include +#include -#include #include #include #include @@ -28,6 +29,7 @@ #include #include #include +#include /* * Called by kernel/ptrace.c when detaching.. @@ -42,27 +44,27 @@ void ptrace_disable(struct task_struct * asmlinkage int sys_ptrace(long request, long pid, long addr, long data) { struct task_struct *child; - int res; - extern void save_fp(struct task_struct *); + int ret; - lock_kernel(); #if 0 printk("ptrace(r=%d,pid=%d,addr=%08lx,data=%08lx)\n", (int) request, (int) pid, (unsigned long) addr, (unsigned long) data); #endif + lock_kernel(); + ret = -EPERM; if (request == PTRACE_TRACEME) { /* are we already being traced? */ - if (current->ptrace & PT_PTRACED) { - res = -EPERM; + if (current->ptrace & PT_PTRACED) + goto out; + if ((ret = security_ptrace(current->parent, current))) goto out; - } /* set the ptrace bit in the process flags. */ current->ptrace |= PT_PTRACED; - res = 0; + ret = 0; goto out; } - res = -ESRCH; + ret = -ESRCH; read_lock(&tasklist_lock); child = find_task_by_pid(pid); if (child) @@ -71,36 +73,31 @@ asmlinkage int sys_ptrace(long request, if (!child) goto out; - res = -EPERM; + ret = -EPERM; if (pid == 1) /* you may not mess with init */ - goto out; + goto out_tsk; if (request == PTRACE_ATTACH) { - res = ptrace_attach(child); - goto out_tsk; - } - res = -ESRCH; - if (!(child->ptrace & PT_PTRACED)) + ret = ptrace_attach(child); goto out_tsk; - if (child->state != TASK_STOPPED) { - if (request != PTRACE_KILL) - goto out_tsk; } - if (child->p_pptr != current) + + ret = ptrace_check_attach(child, request == PTRACE_KILL); + if (ret < 0) goto out_tsk; + switch (request) { - case PTRACE_PEEKTEXT: /* read word at location addr. */ + case PTRACE_PEEKTEXT: /* read word at location addr. */ case PTRACE_PEEKDATA: { unsigned long tmp; int copied; copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0); - res = -EIO; + ret = -EIO; if (copied != sizeof(tmp)) break; - res = put_user(tmp,(unsigned long *) data); - - goto out; + ret = put_user(tmp,(unsigned long *) data); + break; } /* Read the word at location addr in the USER area. */ @@ -108,7 +105,7 @@ asmlinkage int sys_ptrace(long request, struct pt_regs *regs; unsigned long tmp; - regs = (struct pt_regs *) ((unsigned long) child + + regs = (struct pt_regs *) ((unsigned long) child->thread_info + KERNEL_STACK_SIZE - 32 - sizeof(struct pt_regs)); tmp = 0; /* Default return value. */ @@ -118,30 +115,12 @@ asmlinkage int sys_ptrace(long request, break; case FPR_BASE ... FPR_BASE + 31: if (child->used_math) { - unsigned long long *fregs - = (unsigned long long *) - &child->thread.fpu.hard.fp_regs[0]; - if(!(mips_cpu.options & MIPS_CPU_FPU)) { - fregs = (unsigned long long *) - child->thread.fpu.soft.regs; - } else - if (last_task_used_math == child) { - enable_cp1(); - save_fp(child); - disable_cp1(); - last_task_used_math = NULL; - regs->cp0_status &= ~ST0_CU1; - } + unsigned long long *fregs = get_fpu_regs(child); /* * The odd registers are actually the high * order bits of the values stored in the even * registers - unless we're using r2k_switch.S. */ -#ifdef CONFIG_CPU_R3000 - if (mips_cpu.options & MIPS_CPU_FPU) - tmp = *(unsigned long *)(fregs + addr); - else -#endif if (addr & 1) tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32); else @@ -166,7 +145,7 @@ asmlinkage int sys_ptrace(long request, tmp = regs->lo; break; case FPC_CSR: - if (!(mips_cpu.options & MIPS_CPU_FPU)) + if (!cpu_has_fpu) tmp = child->thread.fpu.soft.sr; else tmp = child->thread.fpu.hard.control; @@ -174,34 +153,37 @@ asmlinkage int sys_ptrace(long request, case FPC_EIR: { /* implementation / version register */ unsigned int flags; - local_save_flags(flags); - enable_cp1(); + if (!cpu_has_fpu) + break; + + flags = read_c0_status(); + __enable_fpu(); __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); - local_irq_restore(flags); + write_c0_status(flags); break; } default: tmp = 0; - res = -EIO; - goto out; + ret = -EIO; + goto out_tsk; } - res = put_user(tmp, (unsigned long *) data); - goto out; + ret = put_user(tmp, (unsigned long *) data); + break; } case PTRACE_POKETEXT: /* write the word at location addr. */ case PTRACE_POKEDATA: - res = 0; + ret = 0; if (access_process_vm(child, addr, &data, sizeof(data), 1) == sizeof(data)) break; - res = -EIO; - goto out; + ret = -EIO; + break; case PTRACE_POKEUSR: { struct pt_regs *regs; - res = 0; - regs = (struct pt_regs *) ((unsigned long) child + + ret = 0; + regs = (struct pt_regs *) ((unsigned long) child->thread_info + KERNEL_STACK_SIZE - 32 - sizeof(struct pt_regs)); switch (addr) { @@ -210,21 +192,8 @@ asmlinkage int sys_ptrace(long request, break; case FPR_BASE ... FPR_BASE + 31: { unsigned long long *fregs; - fregs = (unsigned long long *)&child->thread.fpu.hard.fp_regs[0]; - if (child->used_math) { - if (last_task_used_math == child) { - if(!(mips_cpu.options & MIPS_CPU_FPU)) { - fregs = (unsigned long long *) - child->thread.fpu.soft.regs; - } else { - enable_cp1(); - save_fp(child); - disable_cp1(); - last_task_used_math = NULL; - regs->cp0_status &= ~ST0_CU1; - } - } - } else { + fregs = (unsigned long long *)get_fpu_regs(child); + if (!child->used_math) { /* FP not yet used */ memset(&child->thread.fpu.hard, ~0, sizeof(child->thread.fpu.hard)); @@ -235,11 +204,6 @@ asmlinkage int sys_ptrace(long request, * of the values stored in the even registers - unless * we're using r2k_switch.S. */ -#ifdef CONFIG_CPU_R3000 - if (mips_cpu.options & MIPS_CPU_FPU) - *(unsigned long *)(fregs + addr) = data; - else -#endif if (addr & 1) { fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff; fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32; @@ -259,14 +223,14 @@ asmlinkage int sys_ptrace(long request, regs->lo = data; break; case FPC_CSR: - if (!(mips_cpu.options & MIPS_CPU_FPU)) + if (!cpu_has_fpu) child->thread.fpu.soft.sr = data; else child->thread.fpu.hard.control = data; break; default: /* The rest are not allowed. */ - res = -EIO; + ret = -EIO; break; } break; @@ -274,26 +238,28 @@ asmlinkage int sys_ptrace(long request, case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ case PTRACE_CONT: { /* restart after signal. */ - res = -EIO; + ret = -EIO; if ((unsigned long) data > _NSIG) break; - if (request == PTRACE_SYSCALL) - child->ptrace |= PT_TRACESYS; - else - child->ptrace &= ~PT_TRACESYS; + if (request == PTRACE_SYSCALL) { + set_tsk_thread_flag(child, TIF_SYSCALL_TRACE); + } + else { + clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE); + } child->exit_code = data; wake_up_process(child); - res = 0; + ret = 0; break; } /* - * make the child exit. Best I can do is send it a sigkill. - * perhaps it should be put in the status that it wants to + * make the child exit. Best I can do is send it a sigkill. + * perhaps it should be put in the status that it wants to * exit. */ case PTRACE_KILL: - res = 0; + ret = 0; if (child->state == TASK_ZOMBIE) /* already dead */ break; child->exit_code = SIGKILL; @@ -301,32 +267,40 @@ asmlinkage int sys_ptrace(long request, break; case PTRACE_DETACH: /* detach a process that was attached. */ - res = ptrace_detach(child, data); + ret = ptrace_detach(child, data); break; default: - res = ptrace_request(child, request, addr, data); - goto out; + ret = ptrace_request(child, request, addr, data); + break; } out_tsk: - free_task_struct(child); + put_task_struct(child); out: unlock_kernel(); - return res; + return ret; } -asmlinkage void syscall_trace(void) +/* + * Notification of system call entry/exit + * - triggered by current->work.syscall_trace + */ +asmlinkage void do_syscall_trace(void) { - if ((current->ptrace & (PT_PTRACED|PT_TRACESYS)) - != (PT_PTRACED|PT_TRACESYS)) + if (!test_thread_flag(TIF_SYSCALL_TRACE)) return; + if (!(current->ptrace & PT_PTRACED)) + return; + /* The 0x80 provides a way for the tracing parent to distinguish between a syscall stop and SIGTRAP delivery */ current->exit_code = SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ? 0x80 : 0); + preempt_disable(); current->state = TASK_STOPPED; notify_parent(current, SIGCHLD); schedule(); + preempt_enable(); /* * this isn't the same as continuing with a signal, but it will do * for normal use. strace only continues with a signal if the --- linux-2.5.73/arch/mips/kernel/r2300_misc.S 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,199 +0,0 @@ -/* $Id: r2300_misc.S,v 1.8 1999/12/08 22:05:10 harald Exp $ - * misc.S: Misc. exception handling code for R3000/R2000. - * - * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Andreas Busse - * - * Multi-CPU abstraction reworking: - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * - * Further modifications to make this work: - * Copyright (c) 1998 Harald Koerfgen - * Copyright (c) 1998, 1999 Gleb Raiko & Vladimir Roganov - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - .text - .set mips1 - .set noreorder - -#undef NOTLB_OPTIMIZE /* If you are paranoid, define this. */ - - /* ABUSE of CPP macros 101. */ - - /* After this macro runs, the pte faulted on is - * in register PTE, a ptr into the table in which - * the pte belongs is in PTR. - */ -#define LOAD_PTE(pte, ptr) \ - mfc0 pte, CP0_BADVADDR; \ - lw ptr, current_pgd; \ - srl pte, pte, 22; \ - sll pte, pte, 2; \ - addu ptr, ptr, pte; \ - mfc0 pte, CP0_CONTEXT; \ - lw ptr, (ptr); \ - andi pte, pte, 0xffc; \ - addu ptr, ptr, pte; \ - lw pte, (ptr); \ - nop; - - /* This places the even/odd pte pair in the page - * table at PTR into ENTRYLO0 and ENTRYLO1 using - * TMP as a scratch register. - */ -#define PTE_RELOAD(ptr) \ - lw ptr, (ptr) ; \ - nop ; \ - mtc0 ptr, CP0_ENTRYLO0; \ - nop; - -#define DO_FAULT(write) \ - .set noat; \ - .set macro; \ - SAVE_ALL; \ - mfc0 a2, CP0_BADVADDR; \ - STI; \ - .set at; \ - move a0, sp; \ - jal do_page_fault; \ - li a1, write; \ - j ret_from_sys_call; \ - nop; \ - .set noat; \ - .set nomacro; - - /* Check is PTE is present, if not then jump to LABEL. - * PTR points to the page table where this PTE is located, - * when the macro is done executing PTE will be restored - * with its original value. - */ -#define PTE_PRESENT(pte, ptr, label) \ - andi pte, pte, (_PAGE_PRESENT | _PAGE_READ); \ - xori pte, pte, (_PAGE_PRESENT | _PAGE_READ); \ - bnez pte, label; \ - .set push; \ - .set reorder; \ - lw pte, (ptr); \ - .set pop; - - /* Make PTE valid, store result in PTR. */ -#define PTE_MAKEVALID(pte, ptr) \ - ori pte, pte, (_PAGE_VALID | _PAGE_ACCESSED); \ - sw pte, (ptr); - - /* Check if PTE can be written to, if not branch to LABEL. - * Regardless restore PTE with value from PTR when done. - */ -#define PTE_WRITABLE(pte, ptr, label) \ - andi pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \ - xori pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \ - bnez pte, label; \ - .set push; \ - .set reorder; \ - lw pte, (ptr); \ - .set pop; - - - /* Make PTE writable, update software status bits as well, - * then store at PTR. - */ -#define PTE_MAKEWRITE(pte, ptr) \ - ori pte, pte, (_PAGE_ACCESSED | _PAGE_MODIFIED | \ - _PAGE_VALID | _PAGE_DIRTY); \ - sw pte, (ptr); - -/* - * The index register may have the probe fail bit set, - * because we would trap on access kseg2, i.e. without refill. - */ -#define TLB_WRITE(reg) \ - mfc0 reg, CP0_INDEX; \ - nop; \ - bltz reg, 1f; \ - nop; \ - tlbwi; \ - j 2f; \ - nop; \ -1: tlbwr; \ -2: - -#define RET(reg) \ - mfc0 reg, CP0_EPC; \ - nop; \ - jr reg; \ - rfe - - .set noreorder - - .align 5 -NESTED(handle_tlbl, PT_SIZE, sp) - .set noat - -#ifndef NOTLB_OPTIMIZE - /* Test present bit in entry. */ - LOAD_PTE(k0, k1) - tlbp - PTE_PRESENT(k0, k1, nopage_tlbl) - PTE_MAKEVALID(k0, k1) - PTE_RELOAD(k1) - TLB_WRITE(k0) - RET(k0) -nopage_tlbl: -#endif - - DO_FAULT(0) -END(handle_tlbl) - -NESTED(handle_tlbs, PT_SIZE, sp) - .set noat - -#ifndef NOTLB_OPTIMIZE - LOAD_PTE(k0, k1) - tlbp # find faulting entry - PTE_WRITABLE(k0, k1, nopage_tlbs) - PTE_MAKEWRITE(k0, k1) - PTE_RELOAD(k1) - TLB_WRITE(k0) - RET(k0) -nopage_tlbs: -#endif - - DO_FAULT(1) -END(handle_tlbs) - - .align 5 -NESTED(handle_mod, PT_SIZE, sp) - .set noat -#ifndef NOTLB_OPTIMIZE - LOAD_PTE(k0, k1) - tlbp # find faulting entry - andi k0, k0, _PAGE_WRITE - beqz k0, nowrite_mod - .set push - .set reorder - lw k0, (k1) - .set pop - - /* Present and writable bits set, set accessed and dirty bits. */ - PTE_MAKEWRITE(k0, k1) - - /* Now reload the entry into the tlb. */ - PTE_RELOAD(k1) - tlbwi - RET(k0) -#endif - -nowrite_mod: - DO_FAULT(1) -END(handle_mod) --- linux-2.5.73/arch/mips/kernel/r2300_switch.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/r2300_switch.S 2003-06-27 15:56:23.000000000 -0700 @@ -10,18 +10,17 @@ * Further modifications to make this work: * Copyright (c) 1998-2000 Harald Koerfgen */ +#include #include -#include #include -#include #include #include #include #include -#include #include #include #include +#include #include @@ -29,8 +28,24 @@ .align 5 /* - * task_struct *resume(task_struct *prev, - * task_struct *next) + * Offset to the current process status flags, the first 32 bytes of the + * stack are not used. + */ +#define ST_OFF (KERNEL_STACK_SIZE - 32 - PT_SIZE + PT_STATUS) + +/* + * FPU context is saved iff the process has used it's FPU in the current + * time slice as indicated by TIF_USEDFPU. In any case, the CU1 bit for user + * space STATUS register should be 0, so that a process *always* starts its + * userland with FPU disabled after each context switch. + * + * FPU will be enabled as soon as the process accesses FPU again, through + * do_cpu() trap. + */ + +/* + * task_struct *resume(task_struct *prev, task_struct *next, + * struct thread_info *next_ti) ) */ LEAF(resume) #ifndef CONFIG_CPU_HAS_LLSC @@ -41,84 +56,81 @@ LEAF(resume) CPU_SAVE_NONSCRATCH(a0) sw ra, THREAD_REG31(a0) + /* + * check if we need to save FPU registers + */ + lw t3, TASK_THREAD_INFO(a0) + lw t0, TI_FLAGS(t3) + li t1, TIF_USEDFPU + and t2, t0, t1 + beqz t2, 1f + nor t1, zero, t1 + + and t0, t0, t1 + sw t0, TI_FLAGS(t3) + + /* + * clear saved user stack CU1 bit + */ + lw t0, ST_OFF(t3) + li t1, ~ST0_CU1 + and t0, t0, t1 + sw t0, ST_OFF(t3) + + FPU_SAVE_SINGLE(a0, t0) # clobbers t0 + +1: /* * The order of restoring the registers takes care of the race * updating $28, $29 and kernelsp without disabling ints. */ - move $28, a1 - CPU_RESTORE_NONSCRATCH($28) - addiu t0, $28, KERNEL_STACK_SIZE-32 - sw t0, kernelsp + move $28, a2 + CPU_RESTORE_NONSCRATCH(a1) + + addiu t1, $28, KERNEL_STACK_SIZE-32 + sw t1, kernelsp + mfc0 t1, CP0_STATUS /* Do we really need this? */ li a3, 0xff00 and t1, a3 - lw a2, THREAD_STATUS($28) + lw a2, THREAD_STATUS(a1) nor a3, $0, a3 and a2, a3 or a2, t1 mtc0 a2, CP0_STATUS - .set noreorder + move v0, a0 jr ra - move v0, a0 - .set reorder END(resume) /* - * Do lazy fpu context switch. Saves FPU context to the process in a0 - * and loads the new context of the current process. - */ - -#define ST_OFF (KERNEL_STACK_SIZE - 32 - PT_SIZE + PT_STATUS) - -LEAF(lazy_fpu_switch) - mfc0 t0, CP0_STATUS # enable cp1 - li t3, 0x20000000 - or t0, t3 - mtc0 t0, CP0_STATUS - - .set noreorder - beqz a0, 2f # Save floating point state - nor t3, zero, t3 - .set reorder - lw t1, ST_OFF(a0) # last thread loses fpu - and t1, t3 - sw t1, ST_OFF(a0) - FPU_SAVE_SINGLE(a0, t1) # clobbers t1 - -2: - FPU_RESTORE_SINGLE($28, t0) # clobbers t0 - jr ra - END(lazy_fpu_switch) - -/* * Save a thread's fp context. */ -LEAF(save_fp) +LEAF(_save_fp) FPU_SAVE_SINGLE(a0, t1) # clobbers t1 jr ra - END(save_fp) + END(_save_fp) /* * Restore a thread's fp context. */ -LEAF(restore_fp) +LEAF(_restore_fp) FPU_RESTORE_SINGLE(a0, t1) # clobbers t1 jr ra - END(restore_fp) + END(_restore_fp) /* * Load the FPU with signalling NANS. This bit pattern we're using has * the property that no matter whether considered as single or as double - * precission represents signaling NANS. + * precision represents signaling NANS. * * We initialize fcr31 to rounding to nearest, no exceptions. */ #define FPU_DEFAULT 0x00000000 -LEAF(init_fpu) +LEAF(_init_fpu) mfc0 t0, CP0_STATUS - li t1, 0x20000000 + li t1, ST0_CU1 or t0, t1 mtc0 t0, CP0_STATUS @@ -158,8 +170,6 @@ LEAF(init_fpu) mtc1 t0, $f28 mtc1 t0, $f29 mtc1 t0, $f30 - .set noreorder + mtc1 t0, $f31 jr ra - mtc1 t0, $f31 - .set reorder - END(init_fpu) + END(_init_fpu) --- linux-2.5.73/arch/mips/kernel/r4k_misc.S 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,236 +0,0 @@ -/* $Id: r4k_misc.S,v 1.8 1999/10/09 00:00:58 ralf Exp $ - * - * r4k_misc.S: Misc. exception handling code for r4k. - * - * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Andreas Busse - * - * Multi-cpu abstraction and reworking: - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -/************************************************************************** - * 14 Nov, 2000. - * Made support for MIPS32 CPUs. - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - *************************************************************************/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#undef NOTLB_OPTIMIZE /* If you are paranoid, define this. */ - - /* ABUSE of CPP macros 101. */ - - /* After this macro runs, the pte faulted on is - * in register PTE, a ptr into the table in which - * the pte belongs is in PTR. - */ - -#ifdef CONFIG_SMP -#define GET_PGD(scratch, ptr) \ - mfc0 ptr, CP0_CONTEXT; \ - la scratch, current_pgd;\ - srl ptr, 23; \ - sll ptr, 2; \ - addu ptr, scratch, ptr; \ - lw ptr, (ptr); -#else -#define GET_PGD(scratch, ptr) \ - lw ptr, current_pgd; -#endif - - -#define LOAD_PTE(pte, ptr) \ - GET_PGD(pte, ptr) \ - mfc0 pte, CP0_BADVADDR; \ - srl pte, pte, 22; \ - sll pte, pte, 2; \ - addu ptr, ptr, pte; \ - mfc0 pte, CP0_BADVADDR; \ - lw ptr, (ptr); \ - srl pte, pte, 10; \ - and pte, pte, 0xffc; \ - addu ptr, ptr, pte; \ - lw pte, (ptr); - - /* This places the even/odd pte pair in the page - * table at PTR into ENTRYLO0 and ENTRYLO1 using - * TMP as a scratch register. - */ -#define PTE_RELOAD(ptr, tmp) \ - ori ptr, ptr, 0x4; \ - xori ptr, ptr, 0x4; \ - lw tmp, 4(ptr); \ - lw ptr, 0(ptr); \ - srl tmp, tmp, 6; \ - mtc0 tmp, CP0_ENTRYLO1; \ - srl ptr, ptr, 6; \ - mtc0 ptr, CP0_ENTRYLO0; - -#define DO_FAULT(write) \ - .set noat; \ - SAVE_ALL; \ - mfc0 a2, CP0_BADVADDR; \ - STI; \ - .set at; \ - move a0, sp; \ - jal do_page_fault; \ - li a1, write; \ - j ret_from_sys_call; \ - nop; \ - .set noat; - - /* Check is PTE is present, if not then jump to LABEL. - * PTR points to the page table where this PTE is located, - * when the macro is done executing PTE will be restored - * with its original value. - */ -#define PTE_PRESENT(pte, ptr, label) \ - andi pte, pte, (_PAGE_PRESENT | _PAGE_READ); \ - xori pte, pte, (_PAGE_PRESENT | _PAGE_READ); \ - bnez pte, label; \ - lw pte, (ptr); - - /* Make PTE valid, store result in PTR. */ -#define PTE_MAKEVALID(pte, ptr) \ - ori pte, pte, (_PAGE_VALID | _PAGE_ACCESSED); \ - sw pte, (ptr); - - /* Check if PTE can be written to, if not branch to LABEL. - * Regardless restore PTE with value from PTR when done. - */ -#define PTE_WRITABLE(pte, ptr, label) \ - andi pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \ - xori pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \ - bnez pte, label; \ - lw pte, (ptr); - - /* Make PTE writable, update software status bits as well, - * then store at PTR. - */ -#define PTE_MAKEWRITE(pte, ptr) \ - ori pte, pte, (_PAGE_ACCESSED | _PAGE_MODIFIED | \ - _PAGE_VALID | _PAGE_DIRTY); \ - sw pte, (ptr); - - .set noreorder - -/* - * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: - * 2. A timing hazard exists for the TLBP instruction. - * - * stalling_instruction - * TLBP - * - * The JTLB is being read for the TLBP throughout the stall generated by the - * previous instruction. This is not really correct as the stalling instruction - * can modify the address used to access the JTLB. The failure symptom is that - * the TLBP instruction will use an address created for the stalling instruction - * and not the address held in C0_ENHI and thus report the wrong results. - * - * The software work-around is to not allow the instruction preceding the TLBP - * to stall - make it an NOP or some other instruction guaranteed not to stall. - * - * Errata 2 will not be fixed. This errata is also on the R5000. - * - * As if we MIPS hackers wouldn't know how to nop pipelines happy ... - */ -#define R5K_HAZARD nop - - /* - * Note for many R4k variants tlb probes cannot be executed out - * of the instruction cache else you get bogus results. - */ - .align 5 - NESTED(handle_tlbl, PT_SIZE, sp) - .set noat -invalid_tlbl: -#ifndef NOTLB_OPTIMIZE - /* Test present bit in entry. */ - LOAD_PTE(k0, k1) - R5K_HAZARD - tlbp - PTE_PRESENT(k0, k1, nopage_tlbl) - PTE_MAKEVALID(k0, k1) - PTE_RELOAD(k1, k0) - nop - b 1f - tlbwi -1: - nop - .set mips3 - eret - .set mips0 -#endif - -nopage_tlbl: - DO_FAULT(0) - END(handle_tlbl) - - .align 5 - NESTED(handle_tlbs, PT_SIZE, sp) - .set noat -#ifndef NOTLB_OPTIMIZE - LOAD_PTE(k0, k1) - R5K_HAZARD - tlbp # find faulting entry - PTE_WRITABLE(k0, k1, nopage_tlbs) - PTE_MAKEWRITE(k0, k1) - PTE_RELOAD(k1, k0) - nop - b 1f - tlbwi -1: - nop - .set mips3 - eret - .set mips0 -#endif - -nopage_tlbs: - DO_FAULT(1) - END(handle_tlbs) - - .align 5 - NESTED(handle_mod, PT_SIZE, sp) - .set noat -#ifndef NOTLB_OPTIMIZE - LOAD_PTE(k0, k1) - R5K_HAZARD - tlbp # find faulting entry - andi k0, k0, _PAGE_WRITE - beqz k0, nowrite_mod - lw k0, (k1) - - /* Present and writable bits set, set accessed and dirty bits. */ - PTE_MAKEWRITE(k0, k1) -#if 0 - ori k0, k0, (_PAGE_ACCESSED | _PAGE_DIRTY) - sw k0, (k1) -#endif - - /* Now reload the entry into the tlb. */ - PTE_RELOAD(k1, k0) - nop - b 1f - tlbwi -1: - nop - .set mips3 - eret - .set mips0 -#endif - -nowrite_mod: - DO_FAULT(1) - END(handle_mod) --- linux-2.5.73/arch/mips/kernel/r4k_switch.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/r4k_switch.S 2003-06-27 15:56:23.000000000 -0700 @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 1995, 1996, 1998, 1999 by Ralf Baechle + * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002 by Ralf Baechle * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * Copyright (C) 1994, 1995, 1996, by Andreas Busse * Copyright (C) 1999 Silicon Graphics, Inc. @@ -12,24 +12,35 @@ */ #include #include -#include #include -#include #include #include #include #include -#include +#include #include #include #include +#include #include +#define ST_OFF (KERNEL_STACK_SIZE - 32 - PT_SIZE + PT_STATUS) + +/* + * FPU context is saved iff the process has used it's FPU in the current + * time slice as indicated by TIF_USEDFPU. In any case, the CU1 bit for user + * space STATUS register should be 0, so that a process *always* starts its + * userland with FPU disabled after each context switch. + * + * FPU will be enabled as soon as the process accesses FPU again, through + * do_cpu() trap. + */ + /* - * task_struct *r4xx0_resume(task_struct *prev, task_struct *next) + * task_struct *r4xx0_resume(task_struct *prev, task_struct *next, + * struct thread_info *next_ti) */ - .set noreorder .align 5 LEAF(resume) #ifndef CONFIG_CPU_HAS_LLSC @@ -40,79 +51,76 @@ CPU_SAVE_NONSCRATCH(a0) sw ra, THREAD_REG31(a0) + /* + * check if we need to save FPU registers + */ + lw t3, TASK_THREAD_INFO(a0) + lw t0, TI_FLAGS(t3) + li t1, _TIF_USEDFPU + and t2, t0, t1 + beqz t2, 1f + nor t1, zero, t1 + + and t0, t0, t1 + sw t0, TI_FLAGS(t3) + + /* + * clear saved user stack CU1 bit + */ + lw t0, ST_OFF(t3) + li t1, ~ST0_CU1 + and t0, t0, t1 + sw t0, ST_OFF(t3) + + FPU_SAVE_DOUBLE(a0, t0) # clobbers t0 + +1: /* * The order of restoring the registers takes care of the race * updating $28, $29 and kernelsp without disabling ints. */ - move $28, a1 - CPU_RESTORE_NONSCRATCH($28) + move $28, a2 + CPU_RESTORE_NONSCRATCH(a1) + addiu t0, $28, KERNEL_STACK_SIZE-32 -#ifdef CONFIG_SMP +#ifdef CONFIG_SMP mfc0 a3, CP0_CONTEXT la t1, kernelsp srl a3, 23 sll a3, 2 addu t1, a3, t1 - sw t0, (t1) + sw t0, (t1) #else sw t0, kernelsp -#endif +#endif + mfc0 t1, CP0_STATUS /* Do we really need this? */ li a3, 0xff00 and t1, a3 - lw a2, THREAD_STATUS($28) + lw a2, THREAD_STATUS(a1) nor a3, $0, a3 and a2, a3 or a2, t1 mtc0 a2, CP0_STATUS + move v0, a0 jr ra - move v0, a0 END(resume) /* - * Do lazy fpu context switch. Saves FPU context to the process in a0 - * and loads the new context of the current process. - */ - -#define ST_OFF (KERNEL_STACK_SIZE - 32 - PT_SIZE + PT_STATUS) - -LEAF(lazy_fpu_switch) - mfc0 t0, CP0_STATUS # enable cp1 - li t3, 0x20000000 - or t0, t3 - mtc0 t0, CP0_STATUS - - beqz a0, 2f # Save floating point state - nor t3, zero, t3 - - lw t1, ST_OFF(a0) # last thread loses fpu - and t1, t3 - sw t1, ST_OFF(a0) - - - FPU_SAVE_DOUBLE(a0, t1) # clobbers t1 -2: - - .set reorder - FPU_RESTORE_DOUBLE($28, t0) # clobbers t0 - jr ra - END(lazy_fpu_switch) - -/* * Save a thread's fp context. */ -LEAF(save_fp) +LEAF(_save_fp) FPU_SAVE_DOUBLE(a0, t1) # clobbers t1 jr ra - END(save_fp) + END(_save_fp) /* * Restore a thread's fp context. */ -LEAF(restore_fp) +LEAF(_restore_fp) FPU_RESTORE_DOUBLE(a0, t1) # clobbers t1 jr ra - END(restore_fp) + END(_restore_fp) /* * Load the FPU with signalling NANS. This bit pattern we're using has @@ -124,12 +132,13 @@ LEAF(restore_fp) #define FPU_DEFAULT 0x00000000 -LEAF(init_fpu) +LEAF(_init_fpu) .set mips3 mfc0 t0, CP0_STATUS - li t1, 0x20000000 + li t1, ST0_CU1 or t0, t1 mtc0 t0, CP0_STATUS + FPU_ENABLE_HAZARD li t1, FPU_DEFAULT ctc1 t1, fcr31 @@ -151,9 +160,6 @@ LEAF(init_fpu) dmtc1 t0, $f24 dmtc1 t0, $f26 dmtc1 t0, $f28 - .set noreorder + dmtc1 t0, $f30 jr ra - dmtc1 t0, $f30 - .set reorder - END(init_fpu) - + END(_init_fpu) --- linux-2.5.73/arch/mips/kernel/scall_o32.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/scall_o32.S 2003-06-27 15:56:23.000000000 -0700 @@ -3,124 +3,107 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1997, 1998, 1999, 2000 by Ralf Baechle + * Copyright (C) 1997, 1998, 1999, 2000, 2001 by Ralf Baechle + * Copyright (C) 2001 MIPS Technologies, Inc. */ -#include +#include #include -#include +#include #include #include #include #include +#include #include - -/* This duplicates the definition from */ -#define PT_TRACESYS 0x00000002 /* tracing system calls */ - -/* This duplicates the definition from */ -#define SIGILL 4 /* Illegal instruction (ANSI). */ +#include /* Highest syscall used of any syscall flavour */ #define MAX_SYSCALL_NO __NR_Linux + __NR_Linux_syscalls .align 5 NESTED(handle_sys, PT_SIZE, sp) - .set noat - SAVE_SOME - STI - .set at - - lw t1, PT_EPC(sp) # skip syscall on return - - sltiu t0, v0, MAX_SYSCALL_NO + 1 # check syscall number - addiu t1, 4 # skip to next instruction - beqz t0, illegal_syscall - sw t1, PT_EPC(sp) - - /* XXX Put both in one cacheline, should save a bit. */ - sll t0, v0, 2 - lw t2, sys_call_table(t0) # syscall routine - lbu t3, sys_narg_table(v0) # number of arguments - beqz t2, illegal_syscall; - - subu t0, t3, 5 # 5 or more arguments? - sw a3, PT_R26(sp) # save a3 for syscall restarting - bgez t0, stackargs + .set noat + SAVE_SOME + STI + .set at + + lw t1, PT_EPC(sp) # skip syscall on return + + sltiu t0, v0, MAX_SYSCALL_NO + 1 # check syscall number + addiu t1, 4 # skip to next instruction + beqz t0, illegal_syscall + sw t1, PT_EPC(sp) + + /* XXX Put both in one cacheline, should save a bit. */ + sll t0, v0, 2 + lw t2, sys_call_table(t0) # syscall routine + lbu t3, sys_narg_table(v0) # number of arguments + beqz t2, illegal_syscall; + + subu t0, t3, 5 # 5 or more arguments? + sw a3, PT_R26(sp) # save a3 for syscall restarting + bgez t0, stackargs stack_done: - sw a3, PT_R26(sp) # save for syscall restart -#error lw t0, TASK_PTRACE($28) # syscall tracing enabled? - andi t0, PT_TRACESYS - bnez t0, trace_a_syscall - - jalr t2 # Do The Real Thing (TM) - - li t0, -EMAXERRNO - 1 # error? - sltu t0, t0, v0 - sw t0, PT_R7(sp) # set error flag - beqz t0, 1f - - negu v0 # error - sw v0, PT_R0(sp) # set flag for syscall restarting -1: sw v0, PT_R2(sp) # result - -EXPORT(o32_ret_from_sys_call) - mfc0 t0, CP0_STATUS # need_resched and signals atomic test - ori t0, t0, 1 - xori t0, t0, 1 - mtc0 t0, CP0_STATUS - -#error lw t2, TASK_NEED_RESCHED($28) - bnez t2, o32_reschedule -#error lw v0, TASK_SIGPENDING($28) - bnez v0, signal_return -restore_all: - RESTORE_SOME - RESTORE_SP_AND_RET - -/* Put this behind restore_all for the sake of the branch prediction. */ -signal_return: - .type signal_return, @function - - mfc0 t0, CP0_STATUS - ori t0, t0, 1 - mtc0 t0, CP0_STATUS - - move a0, zero - move a1, sp -#error jal do_signal - b restore_all - -o32_reschedule: - SAVE_STATIC - jal schedule - b o32_ret_from_sys_call + sw a3, PT_R26(sp) # save for syscall restart + LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? + bltz t0, syscall_trace_entry # -> yes + + jalr t2 # Do The Real Thing (TM) + + li t0, -EMAXERRNO - 1 # error? + sltu t0, t0, v0 + sw t0, PT_R7(sp) # set error flag + beqz t0, 1f + + negu v0 # error + sw v0, PT_R0(sp) # set flag for syscall + # restarting +1: sw v0, PT_R2(sp) # result + +EXPORT(o32_syscall_exit) + mfc0 t0, CP0_STATUS # make sure need_resched and + ori t0, t0, 1 # signals dont change between + xori t0, t0, 1 # sampling and return + mtc0 t0, CP0_STATUS + SSNOP; SSNOP; SSNOP + + LONG_L a2, TI_FLAGS($28) # current->work + bnez a2, o32_syscall_exit_work + +o32_restore_all: + RESTORE_SOME + RESTORE_SP_AND_RET + +o32_syscall_exit_work: + SAVE_STATIC + j syscall_exit_work /* ------------------------------------------------------------------------ */ -trace_a_syscall: - SAVE_STATIC - sw t2, PT_R1(sp) -#error jal syscall_trace - lw t2, PT_R1(sp) - - lw a0, PT_R4(sp) # Restore argument registers - lw a1, PT_R5(sp) - lw a2, PT_R6(sp) - lw a3, PT_R7(sp) - jalr t2 - - li t0, -EMAXERRNO - 1 # error? - sltu t0, t0, v0 - sw t0, PT_R7(sp) # set error flag - beqz t0, 1f - - negu v0 # error - sw v0, PT_R0(sp) # set flag for syscall restarting -1: sw v0, PT_R2(sp) # result +syscall_trace_entry: + SAVE_STATIC + sw t2, PT_R1(sp) + jal do_syscall_trace + lw t2, PT_R1(sp) + + lw a0, PT_R4(sp) # Restore argument registers + lw a1, PT_R5(sp) + lw a2, PT_R6(sp) + lw a3, PT_R7(sp) + jalr t2 + + li t0, -EMAXERRNO - 1 # error? + sltu t0, t0, v0 + sw t0, PT_R7(sp) # set error flag + beqz t0, 1f + + negu v0 # error + sw v0, PT_R0(sp) # set flag for syscall + # restarting +1: sw v0, PT_R2(sp) # result -#error jal syscall_trace - j ret_from_sys_call + j syscall_exit /* ------------------------------------------------------------------------ */ @@ -139,7 +122,7 @@ stackargs: bltz t0, bad_stack # -> sp is bad lw t0, PT_R29(sp) # get old user stack pointer - la t1, 3f # copy 1 to 2 arguments + PTR_LA t1, 3f # copy 1 to 2 arguments sll t3, t3, 4 subu t1, t3 jr t1 @@ -153,6 +136,7 @@ stackargs: */ .set push .set noreorder + .set nomacro 1: lw t1, 20(t0) # argument #6 from usp nop sw t1, 20(sp) @@ -161,9 +145,9 @@ stackargs: nop sw t1, 16(sp) nop - .set pop +3: .set pop -3: j stack_done # go back + j stack_done # go back .section __ex_table,"a" PTR 1b,bad_stack @@ -180,7 +164,7 @@ bad_stack: sw v0, PT_R2(sp) li t0, 1 # set error flag sw t0, PT_R7(sp) - j ret_from_sys_call + j o32_syscall_exit /* * The system call does not exist in this kernel @@ -190,5 +174,147 @@ illegal_syscall: sw v0, PT_R2(sp) li t0, 1 # set error flag sw t0, PT_R7(sp) - j ret_from_sys_call + j o32_syscall_exit END(handle_sys) + + LEAF(mips_atomic_set) + andi v0, a1, 3 # must be word aligned + bnez v0, bad_alignment + + lw v1, TI_ADDR_LIMIT($28) # in legal address range? + addiu a0, a1, 4 + or a0, a0, a1 + and a0, a0, v1 + bltz a0, bad_address + +#ifdef CONFIG_CPU_HAS_LLSC + /* Ok, this is the ll/sc case. World is sane :-) */ +1: ll v0, (a1) + move a0, a2 +2: sc a0, (a1) + beqz a0, 1b + + .section __ex_table,"a" + PTR 1b, bad_stack + PTR 2b, bad_stack + .previous +#else + sw a1, 16(sp) + sw a2, 20(sp) + + move a0, sp + move a2, a1 + li a1, 1 + jal do_page_fault + + lw a1, 16(sp) + lw a2, 20(sp) + + /* + * At this point the page should be readable and writable unless + * there was no more memory available. + */ +1: lw v0, (a1) +2: sw a2, (a1) + + .section __ex_table,"a" + PTR 1b, no_mem + PTR 2b, no_mem + .previous +#endif + + sw v0, PT_R2(sp) # result +1: + + /* Success, so skip usual error handling garbage. */ + LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? + bltz t0, 1f + b o32_syscall_exit + +1: SAVE_STATIC + jal do_syscall_trace + li a3, 0 # success + j syscall_exit + +no_mem: li v0, -ENOMEM + jr ra + +bad_address: + li v0, -EFAULT + jr ra + +bad_alignment: + li v0, -EINVAL + jr ra + END(mips_atomic_set) + + LEAF(sys_sysmips) + beq a0, MIPS_ATOMIC_SET, mips_atomic_set + j _sys_sysmips + END(sys_sysmips) + + LEAF(sys_syscall) + lw t0, PT_R29(sp) # user sp + + sltu v0, a0, __NR_Linux + __NR_Linux_syscalls + 1 + beqz v0, enosys + + sll v0, a0, 2 + la v1, sys_syscall + lw t2, sys_call_table(v0) # function pointer + lbu t4, sys_narg_table(a0) # number of arguments + + li v0, -EINVAL + beq t2, v1, out # do not recurse + + beqz t2, enosys # null function pointer? + + andi v0, t0, 0x3 # unaligned stack pointer? + bnez v0, sigsegv + + addu v0, t0, 16 # v0 = usp + 16 + addu t1, v0, 12 # 3 32-bit arguments + lw v1, TI_ADDR_LIMIT($28) + or v0, v0, t1 + and v1, v1, v0 + bltz v1, efault + + move a0, a1 # shift argument registers + move a1, a2 + move a2, a3 + +1: lw a3, 16(t0) +2: lw t3, 20(t0) +3: lw t4, 24(t0) + + .section __ex_table, "a" + .word 1b, efault + .word 2b, efault + .word 3b, efault + .previous + + sw t3, 16(sp) # put into new stackframe + sw t4, 20(sp) + + bnez t4, 1f # zero arguments? + addu a0, sp, 32 # then pass sp in a0 +1: + + sw t3, 16(sp) + sw v1, 20(sp) + jr t2 + /* Unreached */ + +enosys: li v0, -ENOSYS + b out + +sigsegv: + li a0, _SIGSEGV + move a1, $28 + jal force_sig + /* Fall through */ + +efault: li v0, -EFAULT + +out: jr ra + END(sys_syscall) --- linux-2.5.73/arch/mips/kernel/setup.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -4,9 +4,10 @@ * for more details. * * Copyright (C) 1995 Linus Torvalds - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Ralf Baechle + * Copyright (C) 1995 Waldorf Electronics + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001 Ralf Baechle * Copyright (C) 1996 Stoned Elipot - * Copyright (C) 2000 Maciej W. Rozycki + * Copyright (C) 2000, 2001, 2002 Maciej W. Rozycki */ #include #include @@ -16,10 +17,10 @@ #include #include #include +#include #include #include #include -#include #include #include #include @@ -29,6 +30,8 @@ #include #include #include +#include +#include #include #include @@ -36,23 +39,11 @@ #include #include #include -#include +#include +#include #include -#ifdef CONFIG_SGI_IP22 -#include -#endif - -struct mips_cpuinfo boot_cpu_data = { 0, NULL, NULL, 0 }; - -/* - * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, - * the implementation of the "wait" feature differs between CPU families. This - * points to the function that implements CPU specific wait. - * The wait instruction stops the pipeline and reduces the power consumption of - * the CPU very much. - */ -void (*cpu_wait)(void) = NULL; +struct cpuinfo_mips cpu_data[NR_CPUS]; /* * There are several bus types available for MIPS machines. "RISC PC" @@ -61,7 +52,9 @@ void (*cpu_wait)(void) = NULL; * boxes ... * This flag is set if a EISA slots are available. */ +#ifdef CONFIG_EISA int EISA_bus = 0; +#endif struct screen_info screen_info; @@ -78,11 +71,6 @@ extern void * __rd_start, * __rd_end; extern struct rtc_ops no_rtc_ops; struct rtc_ops *rtc_ops; -#ifdef CONFIG_PC_KEYB -extern struct kbd_ops no_kbd_ops; -struct kbd_ops *kbd_ops; -#endif - /* * Setup information * @@ -94,333 +82,59 @@ unsigned long mips_machgroup = MACH_GROU struct boot_mem_map boot_mem_map; unsigned char aux_device_present; -extern char _ftext, _etext, _fdata, _edata, _end; -static char command_line[COMMAND_LINE_SIZE]; - char saved_command_line[COMMAND_LINE_SIZE]; -extern char arcs_cmdline[COMMAND_LINE_SIZE]; +static char command_line[CL_SIZE]; + char saved_command_line[CL_SIZE]; +extern char arcs_cmdline[CL_SIZE]; /* * mips_io_port_base is the begin of the address space to which x86 style * I/O ports are mapped. */ -unsigned long mips_io_port_base; +const unsigned long mips_io_port_base = -1; +EXPORT_SYMBOL(mips_io_port_base); + /* - * isa_slot_offset is the address where E(ISA) busaddress 0 is is mapped + * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped * for the processor. */ unsigned long isa_slot_offset; +EXPORT_SYMBOL(isa_slot_offset); -extern void sgi_sysinit(void); extern void SetUpBootInfo(void); -extern void loadmmu(void); +extern void load_mmu(void); extern asmlinkage void start_kernel(void); extern void prom_init(int, char **, char **, int *); static struct resource code_resource = { "Kernel code" }; static struct resource data_resource = { "Kernel data" }; -/* - * Probe whether cpu has config register by trying to play with - * alternate cache bit and see whether it matters. - * It's used by cpu_probe to distinguish between R3000A and R3081. - */ -static inline int cpu_has_confreg(void) -{ -#ifdef CONFIG_CPU_R3000 - extern unsigned long r3k_cache_size(unsigned long); - unsigned long size1, size2; - unsigned long cfg = read_32bit_cp0_register(CP0_CONF); - - size1 = r3k_cache_size(ST0_ISC); - write_32bit_cp0_register(CP0_CONF, cfg^CONF_AC); - size2 = r3k_cache_size(ST0_ISC); - write_32bit_cp0_register(CP0_CONF, cfg); - return size1 != size2; -#else - return 0; -#endif -} - -/* declaration of the global struct */ -struct mips_cpu mips_cpu = {PRID_IMP_UNKNOWN, CPU_UNKNOWN, 0, 0, 0, - {0,0,0,0}, {0,0,0,0}, {0,0,0,0}, {0,0,0,0}}; - -/* Shortcut for assembler access to mips_cpu.options */ -int *cpuoptions = &mips_cpu.options; - -#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \ - | MIPS_CPU_COUNTER | MIPS_CPU_CACHE_CDEX) - -static inline void cpu_probe(void) -{ - -#ifdef CONFIG_CPU_MIPS32 - unsigned long config1; -#endif - - mips_cpu.processor_id = read_32bit_cp0_register(CP0_PRID); - switch (mips_cpu.processor_id & 0xff0000) { - case PRID_COMP_LEGACY: - switch (mips_cpu.processor_id & 0xff00) { - case PRID_IMP_R2000: - mips_cpu.cputype = CPU_R2000; - mips_cpu.isa_level = MIPS_CPU_ISA_I; - mips_cpu.options = MIPS_CPU_TLB; - mips_cpu.tlbsize = 64; - break; - case PRID_IMP_R3000: - if ((mips_cpu.processor_id & 0xff) == PRID_REV_R3000A) - if (cpu_has_confreg()) - mips_cpu.cputype = CPU_R3081E; - else - mips_cpu.cputype = CPU_R3000A; - else - mips_cpu.cputype = CPU_R3000; - mips_cpu.isa_level = MIPS_CPU_ISA_I; - mips_cpu.options = MIPS_CPU_TLB; - mips_cpu.tlbsize = 64; - break; - case PRID_IMP_R4000: - if ((mips_cpu.processor_id & 0xff) == PRID_REV_R4400) - mips_cpu.cputype = CPU_R4400SC; - else - mips_cpu.cputype = CPU_R4000SC; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | - MIPS_CPU_WATCH | MIPS_CPU_VCE; - mips_cpu.tlbsize = 48; - break; - case PRID_IMP_VR41XX: - mips_cpu.cputype = CPU_VR41XX; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS; - mips_cpu.tlbsize = 32; - break; - case PRID_IMP_R4600: - mips_cpu.cputype = CPU_R4600; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU; - mips_cpu.tlbsize = 48; - break; -/* - * This processor doesn't have an MMU, so it's not "real easy" to - * run Linux on it. It is left purely for documentation. - * case PRID_IMP_R4650: - mips_cpu.cputype = CPU_R4650; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU; - mips_cpu.tlbsize = 48; - break; -*/ - case PRID_IMP_TX39: - mips_cpu.isa_level = MIPS_CPU_ISA_I; - mips_cpu.options = MIPS_CPU_TLB; - - switch (mips_cpu.processor_id & 0xff) { - case PRID_REV_TX3912: - mips_cpu.cputype = CPU_TX3912; - mips_cpu.tlbsize = 32; - break; - case PRID_REV_TX3922: - mips_cpu.cputype = CPU_TX3922; - mips_cpu.tlbsize = 64; - break; - case PRID_REV_TX3927: - mips_cpu.cputype = CPU_TX3927; - mips_cpu.tlbsize = 64; - break; - default: - mips_cpu.cputype = CPU_UNKNOWN; - break; - } - break; - case PRID_IMP_R4700: - mips_cpu.cputype = CPU_R4700; - mips_cpu.isa_level = MIPS_CPU_ISA_III; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR; - mips_cpu.tlbsize = 48; - break; - case PRID_IMP_R5000: - mips_cpu.cputype = CPU_R5000; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR; - mips_cpu.tlbsize = 48; - break; - case PRID_IMP_R5432: - mips_cpu.cputype = CPU_R5432; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR; - mips_cpu.tlbsize = 48; - break; - case PRID_IMP_NEVADA: - mips_cpu.cputype = CPU_NEVADA; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | - MIPS_CPU_DIVEC; - mips_cpu.tlbsize = 48; - mips_cpu.icache.ways = 2; - mips_cpu.dcache.ways = 2; - break; - case PRID_IMP_R6000: - mips_cpu.cputype = CPU_R6000; - mips_cpu.isa_level = MIPS_CPU_ISA_II; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU; - mips_cpu.tlbsize = 32; - break; - case PRID_IMP_R6000A: - mips_cpu.cputype = CPU_R6000A; - mips_cpu.isa_level = MIPS_CPU_ISA_II; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_FPU; - mips_cpu.tlbsize = 32; - break; - case PRID_IMP_RM7000: - mips_cpu.cputype = CPU_RM7000; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR; - break; - case PRID_IMP_R8000: - mips_cpu.cputype = CPU_R8000; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_FPU | MIPS_CPU_32FPR; - mips_cpu.tlbsize = 384; /* has weird TLB: 3-way x 128 */ - break; - case PRID_IMP_R10000: - mips_cpu.cputype = CPU_R10000; - mips_cpu.isa_level = MIPS_CPU_ISA_IV; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_FPU | MIPS_CPU_32FPR | - MIPS_CPU_COUNTER | MIPS_CPU_WATCH; - mips_cpu.tlbsize = 64; - break; - default: - mips_cpu.cputype = CPU_UNKNOWN; - break; - } - break; -#ifdef CONFIG_CPU_MIPS32 - case PRID_COMP_MIPS: - switch (mips_cpu.processor_id & 0xff00) { - case PRID_IMP_4KC: - mips_cpu.cputype = CPU_4KC; - goto cpu_4kc; - case PRID_IMP_4KEC: - mips_cpu.cputype = CPU_4KEC; - goto cpu_4kc; - case PRID_IMP_4KSC: - mips_cpu.cputype = CPU_4KSC; -cpu_4kc: - /* Why do we set all these options by default, THEN query them?? */ - mips_cpu.cputype = MIPS_CPU_ISA_M32; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | - MIPS_CPU_DIVEC | MIPS_CPU_WATCH; - config1 = read_mips32_cp0_config1(); - if (config1 & (1 << 3)) - mips_cpu.options |= MIPS_CPU_WATCH; - if (config1 & (1 << 2)) - mips_cpu.options |= MIPS_CPU_MIPS16; - if (config1 & 1) - mips_cpu.options |= MIPS_CPU_FPU; - mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT; - break; - case PRID_IMP_5KC: - mips_cpu.cputype = CPU_5KC; - mips_cpu.cputype = MIPS_CPU_ISA_M64; - /* See comment above about querying options */ - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | - MIPS_CPU_DIVEC | MIPS_CPU_WATCH; - config1 = read_mips32_cp0_config1(); - if (config1 & (1 << 3)) - mips_cpu.options |= MIPS_CPU_WATCH; - if (config1 & (1 << 2)) - mips_cpu.options |= MIPS_CPU_MIPS16; - if (config1 & 1) - mips_cpu.options |= MIPS_CPU_FPU; - break; - mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT; - default: - mips_cpu.cputype = CPU_UNKNOWN; - break; - } - break; -#endif - case PRID_COMP_ALCHEMY: - switch (mips_cpu.processor_id & 0xff00) { -#ifdef CONFIG_CPU_MIPS32 - case PRID_IMP_AU1000: - mips_cpu.cputype = CPU_AU1000; - mips_cpu.isa_level = MIPS_CPU_ISA_M32; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | - MIPS_CPU_DIVEC | MIPS_CPU_WATCH; - config1 = read_mips32_cp0_config1(); - if (config1 & (1 << 3)) - mips_cpu.options |= MIPS_CPU_WATCH; - if (config1 & (1 << 2)) - mips_cpu.options |= MIPS_CPU_MIPS16; - if (config1 & 1) - mips_cpu.options |= MIPS_CPU_FPU; - mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT; - break; -#endif - default: - mips_cpu.cputype = CPU_UNKNOWN; - break; - } - break; - case PRID_COMP_SIBYTE: - switch (mips_cpu.processor_id & 0xff00) { - case PRID_IMP_SB1: - mips_cpu.cputype = CPU_SB1; - mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | - MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | MIPS_CPU_FPU | - MIPS_CPU_VCE; - break; - default: - mips_cpu.cputype = CPU_UNKNOWN; - break; - } - break; - default: - mips_cpu.cputype = CPU_UNKNOWN; - } -} - asmlinkage void __init init_arch(int argc, char **argv, char **envp, int *prom_vec) { - unsigned int s; - /* Determine which MIPS variant we are running on. */ cpu_probe(); prom_init(argc, argv, envp, prom_vec); -#ifdef CONFIG_SGI_IP22 - sgi_sysinit(); -#endif + cpu_report(); /* * Determine the mmu/cache attached to this machine, * then flush the tlb and caches. On the r4xx0 * variants this also sets CP0_WIRED to zero. */ - loadmmu(); + load_mmu(); - /* Disable coprocessors and set FPU for 16 FPRs */ - s = read_32bit_cp0_register(CP0_STATUS); - s &= ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR); - s |= ST0_CU0; - write_32bit_cp0_register(CP0_STATUS, s); + /* Disable coprocessors and set FPU for 16/32 FPR register model */ + clear_c0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR); + set_c0_status(ST0_CU0); start_kernel(); } -void __init add_memory_region(unsigned long start, unsigned long size, +void __init add_memory_region(phys_t start, phys_t size, long type) { int x = boot_mem_map.nr_map; @@ -441,8 +155,10 @@ static void __init print_memory_map(void int i; for (i = 0; i < boot_mem_map.nr_map; i++) { - printk(" memory: %08lx @ %08lx ", - boot_mem_map.map[i].size, boot_mem_map.map[i].addr); + printk(" memory: %08Lx @ %08Lx ", + (u64) boot_mem_map.map[i].size, + (u64) boot_mem_map.map[i].addr); + switch (boot_mem_map.map[i].type) { case BOOT_MEM_RAM: printk("(usable)\n"); @@ -460,7 +176,7 @@ static void __init print_memory_map(void } } -static inline void parse_mem_cmdline(void) +static inline void parse_cmdline_early(void) { char c = ' ', *to = command_line, *from = saved_command_line; unsigned long start_at, mem_size; @@ -499,7 +215,7 @@ static inline void parse_mem_cmdline(voi c = *(from++); if (!c) break; - if (COMMAND_LINE_SIZE <= ++len) + if (CL_SIZE <= ++len) break; *(to++) = c; } @@ -511,143 +227,41 @@ static inline void parse_mem_cmdline(voi } } -void __init setup_arch(char **cmdline_p) -{ - void atlas_setup(void); - void baget_setup(void); - void ddb_setup(void); - void decstation_setup(void); - void deskstation_setup(void); - void jazz_setup(void); - void sni_rm200_pci_setup(void); - void sgi_setup(void); - void ev96100_setup(void); - void malta_setup(void); - void momenco_ocelot_setup(void); - void nino_setup(void); - - unsigned long bootmap_size; - unsigned long start_pfn, max_pfn, first_usable_pfn; - int i; - -#ifdef CONFIG_BLK_DEV_FD - fd_ops = &no_fd_ops; -#endif +#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT) +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT) +#define PFN_PHYS(x) ((x) << PAGE_SHIFT) -#ifdef CONFIG_BLK_DEV_IDE - ide_ops = &no_ide_ops; -#endif +#define MAXMEM HIGHMEM_START +#define MAXMEM_PFN PFN_DOWN(MAXMEM) -#ifdef CONFIG_PC_KEYB - kbd_ops = &no_kbd_ops; +static inline void bootmem_init(void) +{ +#ifdef CONFIG_BLK_DEV_INITRD + unsigned long tmp; + unsigned long *initrd_header; #endif - - rtc_ops = &no_rtc_ops; + unsigned long bootmap_size; + unsigned long start_pfn, max_low_pfn, first_usable_pfn; + int i; - switch(mips_machgroup) - { -#ifdef CONFIG_BAGET_MIPS - case MACH_GROUP_BAGET: - baget_setup(); - break; -#endif -#ifdef CONFIG_DECSTATION - case MACH_GROUP_DEC: - decstation_setup(); - break; -#endif -#ifdef CONFIG_MIPS_ATLAS - case MACH_GROUP_UNKNOWN: - atlas_setup(); - break; -#endif -#ifdef CONFIG_MIPS_JAZZ - case MACH_GROUP_JAZZ: - jazz_setup(); - break; -#endif -#ifdef CONFIG_MIPS_MALTA - case MACH_GROUP_UNKNOWN: - malta_setup(); - break; -#endif -#ifdef CONFIG_MOMENCO_OCELOT - case MACH_GROUP_MOMENCO: - momenco_ocelot_setup(); - break; -#endif -#ifdef CONFIG_SGI_IP22 - /* As of now this is only IP22. */ - case MACH_GROUP_SGI: - sgi_setup(); - break; -#endif -#ifdef CONFIG_SNI_RM200_PCI - case MACH_GROUP_SNI_RM: - sni_rm200_pci_setup(); - break; -#endif -#ifdef CONFIG_DDB5074 - case MACH_GROUP_NEC_DDB: - ddb_setup(); - break; -#endif -#ifdef CONFIG_DDB5476 - case MACH_GROUP_NEC_DDB: - ddb_setup(); - break; -#endif -#ifdef CONFIG_DDB5477 - case MACH_GROUP_NEC_DDB: - ddb_setup(); - break; -#endif -#ifdef CONFIG_MIPS_EV96100 - case MACH_GROUP_GALILEO: - ev96100_setup(); - break; -#endif -#ifdef CONFIG_MIPS_EV64120 - case MACH_GROUP_GALILEO: - ev64120_setup(); - break; -#endif -#if defined(CONFIG_MIPS_IVR) || defined(CONFIG_MIPS_ITE8172) - case MACH_GROUP_ITE: - case MACH_GROUP_GLOBESPAN: - it8172_setup(); - break; -#endif -#ifdef CONFIG_NINO - case MACH_GROUP_PHILIPS: - nino_setup(); - break; -#endif -#ifdef CONFIG_MIPS_PB1000 - case MACH_GROUP_ALCHEMY: - au1000_setup(); - break; -#endif - default: - panic("Unsupported architecture"); +#ifdef CONFIG_BLK_DEV_INITRD + tmp = (((unsigned long)&_end + PAGE_SIZE-1) & PAGE_MASK) - 8; + if (tmp < (unsigned long)&_end) + tmp += PAGE_SIZE; + initrd_header = (unsigned long *)tmp; + if (initrd_header[0] == 0x494E5244) { + initrd_start = (unsigned long)&initrd_header[2]; + initrd_end = initrd_start + initrd_header[1]; } - - strlcpy(command_line, arcs_cmdline, sizeof command_line); - strlcpy(saved_command_line, command_line, sizeof saved_command_line); - *cmdline_p = command_line; - - parse_mem_cmdline(); - -#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT) -#define PFN_DOWN(x) ((x) >> PAGE_SHIFT) -#define PFN_PHYS(x) ((x) << PAGE_SHIFT) - + start_pfn = PFN_UP(__pa((&_end)+(initrd_end - initrd_start) + PAGE_SIZE)); +#else /* * Partially used pages are not usable - thus * we are rounding upwards. */ start_pfn = PFN_UP(__pa(&_end)); +#endif /* CONFIG_BLK_DEV_INITRD */ /* Find the highest page frame number we have available. */ max_pfn = 0; @@ -674,9 +288,36 @@ void __init setup_arch(char **cmdline_p) } } } - - /* Initialize the boot-time allocator. */ - bootmap_size = init_bootmem(first_usable_pfn, max_pfn); + + /* + * Determine low and high memory ranges + */ + max_low_pfn = max_pfn; + if (max_low_pfn > MAXMEM_PFN) { + max_low_pfn = MAXMEM_PFN; +#ifndef CONFIG_HIGHMEM + /* Maximum memory usable is what is directly addressable */ + printk(KERN_WARNING "Warning only %dMB will be used.\n", + MAXMEM>>20); + printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n"); +#endif + } + +#ifdef CONFIG_HIGHMEM + /* + * Crude, we really should make a better attempt at detecting + * highstart_pfn + */ + highstart_pfn = highend_pfn = max_pfn; + if (max_pfn > MAXMEM_PFN) { + highstart_pfn = MAXMEM_PFN; + printk(KERN_NOTICE "%ldMB HIGHMEM available.\n", + (highend_pfn - highstart_pfn) >> (20 - PAGE_SHIFT)); + } +#endif + + /* Initialize the boot-time allocator with low memory only. */ + bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn); /* * Register fully available low RAM pages with the bootmem allocator. @@ -694,7 +335,7 @@ void __init setup_arch(char **cmdline_p) * We are rounding up the start address of usable memory: */ curr_pfn = PFN_UP(boot_mem_map.map[i].addr); - if (curr_pfn >= max_pfn) + if (curr_pfn >= max_low_pfn) continue; if (curr_pfn < start_pfn) curr_pfn = start_pfn; @@ -705,8 +346,19 @@ void __init setup_arch(char **cmdline_p) last_pfn = PFN_DOWN(boot_mem_map.map[i].addr + boot_mem_map.map[i].size); - if (last_pfn > max_pfn) - last_pfn = max_pfn; + if (last_pfn > max_low_pfn) + last_pfn = max_low_pfn; + + /* + * Only register lowmem part of lowmem segment with bootmem. + */ + size = last_pfn - curr_pfn; + if (curr_pfn > PFN_DOWN(HIGHMEM_START)) + continue; + if (curr_pfn + size - 1 > PFN_DOWN(HIGHMEM_START)) + size = PFN_DOWN(HIGHMEM_START) - curr_pfn; + if (!size) + continue; /* * ... finally, did all the rounding and playing @@ -715,7 +367,7 @@ void __init setup_arch(char **cmdline_p) if (last_pfn <= curr_pfn) continue; - size = last_pfn - curr_pfn; + /* Register lowmem ranges */ free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size)); } @@ -725,38 +377,49 @@ void __init setup_arch(char **cmdline_p) #ifdef CONFIG_BLK_DEV_INITRD /* Board specific code should have set up initrd_start and initrd_end */ ROOT_DEV = Root_RAM0; - if( __rd_start != __rd_end ) { + if (&__rd_start != &__rd_end) { initrd_start = (unsigned long)&__rd_start; initrd_end = (unsigned long)&__rd_end; } initrd_below_start_ok = 1; if (initrd_start) { - unsigned long initrd_size = ((unsigned char *)initrd_end) - ((unsigned char *)initrd_start); + unsigned long initrd_size = ((unsigned char *)initrd_end) - ((unsigned char *)initrd_start); printk("Initial ramdisk at: 0x%p (%lu bytes)\n", - (void *)initrd_start, + (void *)initrd_start, initrd_size); - if ((void *)initrd_end > phys_to_virt(PFN_PHYS(max_low_pfn))) { + if (PHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) { printk("initrd extends beyond end of memory " - "(0x%lx > 0x%p)\ndisabling initrd\n", - initrd_end, - phys_to_virt(PFN_PHYS(max_low_pfn))); + "(0x%08lx > 0x%08lx)\ndisabling initrd\n", + PHYSADDR(initrd_end), + PFN_PHYS(max_low_pfn)); initrd_start = initrd_end = 0; - } + } } #endif /* CONFIG_BLK_DEV_INITRD */ +} - paging_init(); +static inline void resource_init(void) +{ + int i; - code_resource.start = virt_to_bus(&_ftext); - code_resource.end = virt_to_bus(&_etext) - 1; - data_resource.start = virt_to_bus(&_fdata); - data_resource.end = virt_to_bus(&_edata) - 1; + code_resource.start = virt_to_phys(&_text); + code_resource.end = virt_to_phys(&_etext) - 1; + data_resource.start = virt_to_phys(&_etext); + data_resource.end = virt_to_phys(&_edata) - 1; /* * Request address space for all standard RAM. */ for (i = 0; i < boot_mem_map.nr_map; i++) { struct resource *res; + unsigned long start, end; + + start = boot_mem_map.map[i].addr; + end = boot_mem_map.map[i].addr + boot_mem_map.map[i].size - 1; + if (start >= MAXMEM) + continue; + if (end >= MAXMEM) + end = MAXMEM - 1; res = alloc_bootmem(sizeof(struct resource)); switch (boot_mem_map.map[i].type) { @@ -768,8 +431,10 @@ void __init setup_arch(char **cmdline_p) default: res->name = "reserved"; } - res->start = boot_mem_map.map[i].addr; - res->end = res->start + boot_mem_map.map[i].size - 1; + + res->start = start; + res->end = end; + res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; request_resource(&iomem_resource, res); @@ -783,15 +448,244 @@ void __init setup_arch(char **cmdline_p) } } -void r3081_wait(void) +#undef PFN_UP +#undef PFN_DOWN +#undef PFN_PHYS + +#undef MAXMEM +#undef MAXMEM_PFN + + +void __init setup_arch(char **cmdline_p) { - unsigned long cfg = read_32bit_cp0_register(CP0_CONF); - write_32bit_cp0_register(CP0_CONF, cfg|CONF_HALT); + void atlas_setup(void); + void baget_setup(void); + void cobalt_setup(void); + void lasat_setup(void); + void ddb_setup(void); + void decstation_setup(void); + void deskstation_setup(void); + void jazz_setup(void); + void sni_rm200_pci_setup(void); + void ip22_setup(void); + void ev96100_setup(void); + void malta_setup(void); + void sead_setup(void); + void ikos_setup(void); + void momenco_ocelot_setup(void); + void momenco_ocelot_g_setup(void); + void momenco_ocelot_c_setup(void); + void nec_osprey_setup(void); + void nec_eagle_setup(void); + void zao_capcella_setup(void); + void victor_mpc30x_setup(void); + void ibm_workpad_setup(void); + void casio_e55_setup(void); + void jmr3927_setup(void); + void it8172_setup(void); + void swarm_setup(void); + void hp_setup(void); + void au1x00_setup(void); + void frame_info_init(void); + + frame_info_init(); + +#ifdef CONFIG_BLK_DEV_FD + fd_ops = &no_fd_ops; +#endif + +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &no_ide_ops; +#endif + + rtc_ops = &no_rtc_ops; + + switch(mips_machgroup) + { +#ifdef CONFIG_BAGET_MIPS + case MACH_GROUP_BAGET: + baget_setup(); + break; +#endif +#ifdef CONFIG_MIPS_COBALT + case MACH_GROUP_COBALT: + cobalt_setup(); + break; +#endif +#ifdef CONFIG_DECSTATION + case MACH_GROUP_DEC: + decstation_setup(); + break; +#endif +#ifdef CONFIG_MIPS_ATLAS + case MACH_GROUP_UNKNOWN: + atlas_setup(); + break; +#endif +#ifdef CONFIG_MIPS_JAZZ + case MACH_GROUP_JAZZ: + jazz_setup(); + break; +#endif +#ifdef CONFIG_MIPS_MALTA + case MACH_GROUP_UNKNOWN: + malta_setup(); + break; +#endif +#ifdef CONFIG_MOMENCO_OCELOT + case MACH_GROUP_MOMENCO: + momenco_ocelot_setup(); + break; +#endif +#ifdef CONFIG_MOMENCO_OCELOT_G + case MACH_GROUP_MOMENCO: + momenco_ocelot_g_setup(); + break; +#endif +#ifdef CONFIG_MOMENCO_OCELOT_C + case MACH_GROUP_MOMENCO: + momenco_ocelot_c_setup(); + break; +#endif +#ifdef CONFIG_MIPS_SEAD + case MACH_GROUP_UNKNOWN: + sead_setup(); + break; +#endif +#ifdef CONFIG_SGI_IP22 + /* As of now this is only IP22. */ + case MACH_GROUP_SGI: + ip22_setup(); + break; +#endif +#ifdef CONFIG_SNI_RM200_PCI + case MACH_GROUP_SNI_RM: + sni_rm200_pci_setup(); + break; +#endif +#ifdef CONFIG_DDB5074 + case MACH_GROUP_NEC_DDB: + ddb_setup(); + break; +#endif +#ifdef CONFIG_DDB5476 + case MACH_GROUP_NEC_DDB: + ddb_setup(); + break; +#endif +#ifdef CONFIG_DDB5477 + case MACH_GROUP_NEC_DDB: + ddb_setup(); + break; +#endif +#ifdef CONFIG_CPU_VR41XX + case MACH_GROUP_NEC_VR41XX: + switch (mips_machtype) { +#ifdef CONFIG_NEC_OSPREY + case MACH_NEC_OSPREY: + nec_osprey_setup(); + break; +#endif +#ifdef CONFIG_NEC_EAGLE + case MACH_NEC_EAGLE: + nec_eagle_setup(); + break; +#endif +#ifdef CONFIG_ZAO_CAPCELLA + case MACH_ZAO_CAPCELLA: + zao_capcella_setup(); + break; +#endif +#ifdef CONFIG_VICTOR_MPC30X + case MACH_VICTOR_MPC30X: + victor_mpc30x_setup(); + break; +#endif +#ifdef CONFIG_IBM_WORKPAD + case MACH_IBM_WORKPAD: + ibm_workpad_setup(); + break; +#endif +#ifdef CONFIG_CASIO_E55 + case MACH_CASIO_E55: + casio_e55_setup(); + break; +#endif +#ifdef CONFIG_TANBAC_TB0229 + case MACH_TANBAC_TB0229: + tanbac_tb0229_setup(); + break; +#endif + } + break; +#endif +#ifdef CONFIG_MIPS_EV96100 + case MACH_GROUP_GALILEO: + ev96100_setup(); + break; +#endif +#ifdef CONFIG_MIPS_EV64120 + case MACH_GROUP_GALILEO: + ev64120_setup(); + break; +#endif +#if defined(CONFIG_MIPS_IVR) || defined(CONFIG_MIPS_ITE8172) + case MACH_GROUP_ITE: + case MACH_GROUP_GLOBESPAN: + it8172_setup(); + break; +#endif +#ifdef CONFIG_LASAT + case MACH_GROUP_LASAT: + lasat_setup(); + break; +#endif +#ifdef CONFIG_SOC_AU1X00 + case MACH_GROUP_ALCHEMY: + au1x00_setup(); + break; +#endif +#ifdef CONFIG_TOSHIBA_JMR3927 + case MACH_GROUP_TOSHIBA: + jmr3927_setup(); + break; +#endif +#ifdef CONFIG_TOSHIBA_RBTX4927 + case MACH_GROUP_TOSHIBA: + tx4927_setup(); + break; +#endif +#ifdef CONFIG_SIBYTE_BOARD + case MACH_GROUP_SIBYTE: + swarm_setup(); + break; +#endif +#ifdef CONFIG_HP_LASERJET + case MACH_GROUP_HP_LJ: + hp_setup(); + break; +#endif + default: + panic("Unsupported architecture"); + } + + strlcpy(command_line, arcs_cmdline, sizeof command_line); + strlcpy(saved_command_line, command_line, sizeof saved_command_line); + *cmdline_p = command_line; + + parse_cmdline_early(); + + bootmem_init(); + + paging_init(); + + resource_init(); } -void r4k_wait(void) +int __init fpu_disable(char *s) { - __asm__(".set\tmips3\n\t" - "wait\n\t" - ".set\tmips0"); + cpu_data[0].options &= ~MIPS_CPU_FPU; + + return 1; } +__setup("nofpu", fpu_disable); --- linux-2.5.73/arch/mips/kernel/signal.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/signal.c 2003-06-27 15:56:23.000000000 -0700 @@ -10,19 +10,22 @@ #include #include #include +#include #include #include #include #include #include #include -#include #include #include #include -#include -#include +#include +#include +#include +#include +#include #include #include @@ -32,17 +35,13 @@ extern asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs); -extern asmlinkage int (*save_fp_context)(struct sigcontext *sc); -extern asmlinkage int (*restore_fp_context)(struct sigcontext *sc); - -extern asmlinkage void syscall_trace(void); +extern asmlinkage void do_syscall_trace(void); /* * Atomically swap in the new signal mask, and wait for a signal. */ save_static_function(sys_sigsuspend); -static_unused int -_sys_sigsuspend(struct pt_regs regs) +static_unused int _sys_sigsuspend(struct pt_regs regs) { sigset_t *uset, saveset, newset; @@ -51,11 +50,11 @@ _sys_sigsuspend(struct pt_regs regs) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); + spin_lock_irq(¤t->sighand->siglock); saveset = current->blocked; current->blocked = newset; recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); + spin_unlock_irq(¤t->sighand->siglock); regs.regs[2] = EINTR; regs.regs[7] = 1; @@ -67,10 +66,8 @@ _sys_sigsuspend(struct pt_regs regs) } } - save_static_function(sys_rt_sigsuspend); -static_unused int -_sys_rt_sigsuspend(struct pt_regs regs) +static_unused int _sys_rt_sigsuspend(struct pt_regs regs) { sigset_t *unewset, saveset, newset; size_t sigsetsize; @@ -85,11 +82,11 @@ _sys_rt_sigsuspend(struct pt_regs regs) return -EFAULT; sigdelsetmask(&newset, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); + spin_lock_irq(¤t->sighand->siglock); saveset = current->blocked; current->blocked = newset; recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); + spin_unlock_irq(¤t->sighand->siglock); regs.regs[2] = EINTR; regs.regs[7] = 1; @@ -101,8 +98,8 @@ _sys_rt_sigsuspend(struct pt_regs regs) } } -asmlinkage int -sys_sigaction(int sig, const struct sigaction *act, struct sigaction *oact) +asmlinkage int sys_sigaction(int sig, const struct sigaction *act, + struct sigaction *oact) { struct k_sigaction new_ka, old_ka; int ret; @@ -116,7 +113,6 @@ sys_sigaction(int sig, const struct siga err |= __get_user(new_ka.sa.sa_handler, &act->sa_handler); err |= __get_user(new_ka.sa.sa_flags, &act->sa_flags); err |= __get_user(mask, &act->sa_mask.sig[0]); - err |= __get_user(new_ka.sa.sa_restorer, &act->sa_restorer); if (err) return -EFAULT; @@ -134,7 +130,6 @@ sys_sigaction(int sig, const struct siga err |= __put_user(0, &oact->sa_mask.sig[1]); err |= __put_user(0, &oact->sa_mask.sig[2]); err |= __put_user(0, &oact->sa_mask.sig[3]); - err |= __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer); if (err) return -EFAULT; } @@ -142,8 +137,7 @@ sys_sigaction(int sig, const struct siga return ret; } -asmlinkage int -sys_sigaltstack(struct pt_regs regs) +asmlinkage int sys_sigaltstack(struct pt_regs regs) { const stack_t *uss = (const stack_t *) regs.regs[4]; stack_t *uoss = (stack_t *) regs.regs[5]; @@ -152,10 +146,8 @@ sys_sigaltstack(struct pt_regs regs) return do_sigaltstack(uss, uoss, usp); } -asmlinkage int -restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) +static int restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) { - int owned_fp; int err = 0; u64 reg; @@ -183,10 +175,15 @@ restore_sigcontext(struct pt_regs *regs, restore_gp_reg(31); #undef restore_gp_reg - err |= __get_user(owned_fp, &sc->sc_ownedfp); - if (owned_fp) { + err |= __get_user(current->used_math, &sc->sc_used_math); + + if (current->used_math) { + /* restore fpu context if we have used it before */ + own_fpu(); err |= restore_fp_context(sc); - last_task_used_math = current; + } else { + /* signal handler may have used FPU. Give it up. */ + loose_fpu(); } return err; @@ -206,8 +203,7 @@ struct rt_sigframe { struct ucontext rs_uc; }; -asmlinkage void -sys_sigreturn(struct pt_regs regs) +asmlinkage void sys_sigreturn(struct pt_regs regs) { struct sigframe *frame; sigset_t blocked; @@ -219,10 +215,10 @@ sys_sigreturn(struct pt_regs regs) goto badframe; sigdelsetmask(&blocked, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); + spin_lock_irq(¤t->sighand->siglock); current->blocked = blocked; recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); + spin_unlock_irq(¤t->sighand->siglock); if (restore_sigcontext(®s, &frame->sf_sc)) goto badframe; @@ -230,11 +226,11 @@ sys_sigreturn(struct pt_regs regs) /* * Don't let your children do this ... */ - if (current->ptrace & PT_TRACESYS) - syscall_trace(); + if (current_thread_info()->flags & TIF_SYSCALL_TRACE) + do_syscall_trace(); __asm__ __volatile__( "move\t$29, %0\n\t" - "j\tret_from_sys_call" + "j\tsyscall_exit" :/* no outputs */ :"r" (®s)); /* Unreached */ @@ -243,8 +239,7 @@ badframe: force_sig(SIGSEGV, current); } -asmlinkage void -sys_rt_sigreturn(struct pt_regs regs) +asmlinkage void sys_rt_sigreturn(struct pt_regs regs) { struct rt_sigframe *frame; sigset_t set; @@ -257,10 +252,10 @@ sys_rt_sigreturn(struct pt_regs regs) goto badframe; sigdelsetmask(&set, ~_BLOCKABLE); - spin_lock_irq(¤t->sigmask_lock); + spin_lock_irq(¤t->sighand->siglock); current->blocked = set; recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); + spin_unlock_irq(¤t->sighand->siglock); if (restore_sigcontext(®s, &frame->rs_uc.uc_mcontext)) goto badframe; @@ -276,7 +271,7 @@ sys_rt_sigreturn(struct pt_regs regs) */ __asm__ __volatile__( "move\t$29, %0\n\t" - "j\tret_from_sys_call" + "j\tsyscall_exit" :/* no outputs */ :"r" (®s)); /* Unreached */ @@ -285,21 +280,20 @@ badframe: force_sig(SIGSEGV, current); } -static inline int -setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc) +static inline int setup_sigcontext(struct pt_regs *regs, struct sigcontext *sc) { - int owned_fp; int err = 0; u64 reg; - err |= __put_user(regs->cp0_epc, &sc->sc_pc); + reg = regs->cp0_epc; err |= __put_user(reg, &sc->sc_pc); err |= __put_user(regs->cp0_status, &sc->sc_status); #define save_gp_reg(i) { \ reg = regs->regs[i]; \ err |= __put_user(reg, &sc->sc_regs[i]); \ } while(0) - __put_user(0, &sc->sc_regs[0]); save_gp_reg(1); save_gp_reg(2); + reg = 0; err |= __put_user(reg, &sc->sc_regs[0]); + save_gp_reg(1); save_gp_reg(2); save_gp_reg(3); save_gp_reg(4); save_gp_reg(5); save_gp_reg(6); save_gp_reg(7); save_gp_reg(8); save_gp_reg(9); save_gp_reg(10); save_gp_reg(11); save_gp_reg(12); save_gp_reg(13); save_gp_reg(14); @@ -310,36 +304,48 @@ setup_sigcontext(struct pt_regs *regs, s save_gp_reg(31); #undef save_gp_reg - err |= __put_user(regs->hi, &sc->sc_mdhi); - err |= __put_user(regs->lo, &sc->sc_mdlo); + reg = regs->hi; err |= __put_user(reg, &sc->sc_mdhi); + reg = regs->lo; err |= __put_user(reg, &sc->sc_mdlo); err |= __put_user(regs->cp0_cause, &sc->sc_cause); err |= __put_user(regs->cp0_badvaddr, &sc->sc_badvaddr); - owned_fp = (current == last_task_used_math); - err |= __put_user(owned_fp, &sc->sc_ownedfp); + err |= __put_user(current->used_math, &sc->sc_used_math); + + if (!current->used_math) + goto out; - if (current->used_math) { /* fp is active. */ - set_cp0_status(ST0_CU1); - err |= save_fp_context(sc); - last_task_used_math = NULL; - regs->cp0_status &= ~ST0_CU1; - current->used_math = 0; + /* + * Save FPU state to signal context. Signal handler will "inherit" + * current FPU state. + */ + if (!is_fpu_owner()) { + own_fpu(); + restore_fp(current); } + err |= save_fp_context(sc); +out: return err; } /* * Determine which stack to use.. */ -static inline void * -get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size) +static inline void * get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, + size_t frame_size) { unsigned long sp; /* Default to using normal stack */ sp = regs->regs[29]; + /* + * FPU emulator may have it's own trampoline active just + * above the user stack, 16-bytes before the next lowest + * 16 byte boundary. Try to avoid trashing it. + */ + sp -= 32; + /* This is the X/Open sanctioned signal stack switching. */ if ((ka->sa.sa_flags & SA_ONSTACK) && ! on_sig_stack(sp)) sp = current->sas_ss_sp + current->sas_ss_size; @@ -347,9 +353,8 @@ get_sigframe(struct k_sigaction *ka, str return (void *)((sp - frame_size) & ALMASK); } -static void inline -setup_frame(struct k_sigaction * ka, struct pt_regs *regs, - int signr, sigset_t *set) +static void inline setup_frame(struct k_sigaction * ka, struct pt_regs *regs, + int signr, sigset_t *set) { struct sigframe *frame; int err = 0; @@ -358,23 +363,15 @@ setup_frame(struct k_sigaction * ka, str if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - /* Set up to return from userspace. If provided, use a stub already - in userspace. */ - if (ka->sa.sa_flags & SA_RESTORER) - regs->regs[31] = (unsigned long) ka->sa.sa_restorer; - else { - /* - * Set up the return code ... - * - * li v0, __NR_sigreturn - * syscall - */ - err |= __put_user(0x24020000 + __NR_sigreturn, - frame->sf_code + 0); - err |= __put_user(0x0000000c , - frame->sf_code + 1); - flush_cache_sigtramp((unsigned long) frame->sf_code); - } + /* + * Set up the return code ... + * + * li v0, __NR_sigreturn + * syscall + */ + err |= __put_user(0x24020000 + __NR_sigreturn, frame->sf_code + 0); + err |= __put_user(0x0000000c , frame->sf_code + 1); + flush_cache_sigtramp((unsigned long) frame->sf_code); err |= setup_sigcontext(regs, &frame->sf_sc); err |= __copy_to_user(&frame->sf_mask, set, sizeof(*set)); @@ -399,8 +396,9 @@ setup_frame(struct k_sigaction * ka, str regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler; #if DEBUG_SIG - printk("SIG deliver (%s:%d): sp=0x%p pc=0x%p ra=0x%p\n", - current->comm, current->pid, frame, regs->cp0_epc, frame->code); + printk("SIG deliver (%s:%d): sp=0x%p pc=0x%lx ra=0x%p\n", + current->comm, current->pid, + frame, regs->cp0_epc, frame->sf_code); #endif return; @@ -410,9 +408,8 @@ give_sigsegv: force_sig(SIGSEGV, current); } -static void inline -setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, - int signr, sigset_t *set, siginfo_t *info) +static void inline setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, + int signr, sigset_t *set, siginfo_t *info) { struct rt_sigframe *frame; int err = 0; @@ -421,23 +418,15 @@ setup_rt_frame(struct k_sigaction * ka, if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - /* Set up to return from userspace. If provided, use a stub already - in userspace. */ - if (ka->sa.sa_flags & SA_RESTORER) - regs->regs[31] = (unsigned long) ka->sa.sa_restorer; - else { - /* - * Set up the return code ... - * - * li v0, __NR_rt_sigreturn - * syscall - */ - err |= __put_user(0x24020000 + __NR_rt_sigreturn, - frame->rs_code + 0); - err |= __put_user(0x0000000c , - frame->rs_code + 1); - flush_cache_sigtramp((unsigned long) frame->rs_code); - } + /* + * Set up the return code ... + * + * li v0, __NR_rt_sigreturn + * syscall + */ + err |= __put_user(0x24020000 + __NR_rt_sigreturn, frame->rs_code + 0); + err |= __put_user(0x0000000c , frame->rs_code + 1); + flush_cache_sigtramp((unsigned long) frame->rs_code); /* Create siginfo. */ err |= copy_siginfo_to_user(&frame->rs_info, info); @@ -475,8 +464,9 @@ setup_rt_frame(struct k_sigaction * ka, regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler; #if DEBUG_SIG - printk("SIG deliver (%s:%d): sp=0x%p pc=0x%p ra=0x%p\n", - current->comm, current->pid, frame, regs->cp0_epc, frame->code); + printk("SIG deliver (%s:%d): sp=0x%p pc=0x%lx ra=0x%p\n", + current->comm, current->pid, + frame, regs->cp0_epc, frame->rs_code); #endif return; @@ -486,31 +476,11 @@ give_sigsegv: force_sig(SIGSEGV, current); } -static inline void -handle_signal(unsigned long sig, siginfo_t *info, sigset_t *oldset, - struct pt_regs * regs) +static inline void handle_signal(unsigned long sig, siginfo_t *info, + sigset_t *oldset, struct pt_regs * regs) { - struct k_sigaction *ka = ¤t->sig->action[sig-1]; + struct k_sigaction *ka = ¤t->sighand->action[sig-1]; - if (ka->sa.sa_flags & SA_SIGINFO) - setup_rt_frame(ka, regs, sig, oldset, info); - else - setup_frame(ka, regs, sig, oldset); - - if (ka->sa.sa_flags & SA_ONESHOT) - ka->sa.sa_handler = SIG_DFL; - if (!(ka->sa.sa_flags & SA_NODEFER)) { - spin_lock_irq(¤t->sigmask_lock); - sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); - sigaddset(¤t->blocked,sig); - recalc_sigpending(); - spin_unlock_irq(¤t->sigmask_lock); - } -} - -static inline void -syscall_restart(struct pt_regs *regs, struct k_sigaction *ka) -{ switch(regs->regs[0]) { case ERESTARTNOHAND: regs->regs[2] = EINTR; @@ -527,27 +497,33 @@ syscall_restart(struct pt_regs *regs, st } regs->regs[0] = 0; /* Don't deal with this again. */ -} -extern int do_irix_signal(sigset_t *oldset, struct pt_regs *regs); + if (ka->sa.sa_flags & SA_SIGINFO) + setup_rt_frame(ka, regs, sig, oldset, info); + else + setup_frame(ka, regs, sig, oldset); + + if (ka->sa.sa_flags & SA_ONESHOT) + ka->sa.sa_handler = SIG_DFL; + if (!(ka->sa.sa_flags & SA_NODEFER)) { + spin_lock_irq(¤t->sighand->siglock); + sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); + sigaddset(¤t->blocked,sig); + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + } +} asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs) { siginfo_t info; - int sig_nr; - -#ifdef CONFIG_BINFMT_IRIX - if (current->personality != PER_LINUX) - return do_irix_signal(oldset, regs); -#endif + int signr; if (!oldset) oldset = ¤t->blocked; signr = get_signal_to_deliver(&info, regs, NULL); if (signr > 0) { - if (regs->regs[0]) - syscall_restart(regs, ka); /* Whee! Actually deliver the signal. */ handle_signal(signr, &info, oldset, regs); return 1; @@ -568,3 +544,24 @@ asmlinkage int do_signal(sigset_t *oldse } return 0; } + +extern int do_irix_signal(sigset_t *oldset, struct pt_regs *regs); + +/* + * notification of userspace execution resumption + * - triggered by current->work.notify_resume + */ +asmlinkage void do_notify_resume(struct pt_regs *regs, sigset_t *oldset, + __u32 thread_info_flags) +{ + /* deal with pending signal delivery */ + if (thread_info_flags & _TIF_SIGPENDING) { +#ifdef CONFIG_BINFMT_IRIX + if (unlikely(current->personality != PER_LINUX)) { + do_irix_signal(oldset, regs); + return; + } +#endif + do_signal(oldset, regs); + } +} --- linux-2.5.73/arch/mips/kernel/smp.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/smp.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,11 +1,4 @@ /* - * - * arch/mips/kernel/smp.c - * - * Copyright (C) 2000 Sibyte - * - * Written by Justin Carlson (carlson@sibyte.com) - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 @@ -15,229 +8,256 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - */ - - + * Copyright (C) 2000, 2001 Kanoj Sarcar + * Copyright (C) 2000, 2001 Ralf Baechle + * Copyright (C) 2000, 2001 Silicon Graphics, Inc. + * Copyright (C) 2000, 2001 Broadcom Corporation + */ #include +#include +#include #include +#include #include #include +#include #include #include #include -#include -#include #include +#include #include #include #include #include -#include #include -/* - * This was written with the BRCM12500 MP SOC in mind, but tries to - * be generic. It's modelled on the mips64 smp.c code, which is - * derived from Sparc, I'm guessing, which is derived from... - * - * It's probably horribly designed for very large ccNUMA systems - * as it doesn't take any node clustering into account. -*/ - - -/* Ze Big Kernel Lock! */ -int smp_threads_ready; /* Not used */ -int smp_num_cpus; -int global_irq_holder = NO_PROC_ID; -spinlock_t global_irq_lock = SPIN_LOCK_UNLOCKED; -struct mips_cpuinfo cpu_data[NR_CPUS]; - -struct smp_fn_call_struct smp_fn_call = -{ SPIN_LOCK_UNLOCKED, ATOMIC_INIT(0), NULL, NULL}; +int smp_threads_ready; /* Not used */ -static atomic_t cpus_booted = ATOMIC_INIT(0); +// static atomic_t cpus_booted = ATOMIC_INIT(0); +atomic_t cpus_booted = ATOMIC_INIT(0); +cpumask_t phys_cpu_present_map; /* Bitmask of physically CPUs */ +cpumask_t cpu_online_map; /* Bitmask of currently online CPUs */ +int __cpu_number_map[NR_CPUS]; +int __cpu_logical_map[NR_CPUS]; /* These are defined by the board-specific code. */ -/* Cause the function described by smp_fn_call - to be executed on the passed cpu. When the function - has finished, increment the finished field of - smp_fn_call. */ - -void core_call_function(int cpu); +/* + * Cause the function described by call_data to be executed on the passed + * cpu. When the function has finished, increment the finished field of + * call_data. + */ +void core_send_ipi(int cpu, unsigned int action); /* * Clear all undefined state in the cpu, set up sp and gp to the passed - * values, and kick the cpu into smp_bootstrap(); + * values, and kick the cpu into smp_bootstrap(); */ void prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp); /* * After we've done initial boot, this function is called to allow the - * board code to clean up state, if needed + * board code to clean up state, if needed */ - void prom_init_secondary(void); +void prom_smp_finish(void); -void cpu_idle(void); - -/* Do whatever setup needs to be done for SMP at the board level. Return - the number of cpus in the system, including this one */ -int prom_setup_smp(void); - -int start_secondary(void *unused) -{ - prom_init_secondary(); - write_32bit_cp0_register(CP0_CONTEXT, smp_processor_id()<<23); - current_pgd[smp_processor_id()] = init_mm.pgd; - printk("Slave cpu booted successfully\n"); - atomic_inc(&cpus_booted); - cpu_idle(); - return 0; -} +cycles_t cacheflush_time; +unsigned long cache_decay_ticks; -void __init smp_boot_cpus(void) +void smp_tune_scheduling (void) { - int i; - - smp_num_cpus = prom_setup_smp(); - init_new_context(current, &init_mm); - current->processor = 0; - atomic_set(&cpus_booted, 1); /* Master CPU is already booted... */ - init_idle(); - for (i = 1; i < smp_num_cpus; i++) { - struct task_struct *p; - struct pt_regs regs; - printk("Starting CPU %d... ", i); - - /* Spawn a new process normally. Grab a pointer to - its task struct so we can mess with it */ - p = do_fork(CLONE_VM|CLONE_IDLETASK, 0, ®s, 0); - - /* Schedule the first task manually */ - p->processor = i; - p->cpus_runnable = 1 << i; /* we schedule the first task manually */ - - /* Attach to the address space of init_task. */ - atomic_inc(&init_mm.mm_count); - p->active_mm = &init_mm; - init_tasks[i] = p; - - del_from_runqueue(p); - unhash_process(p); - - prom_boot_secondary(i, - (unsigned long)p + KERNEL_STACK_SIZE - 32, - (unsigned long)p); + struct cache_desc *cd = ¤t_cpu_data.scache; + unsigned long cachesize; /* kB */ + unsigned long bandwidth = 350; /* MB/s */ + unsigned long cpu_khz; -#if 0 - - /* This is copied from the ip-27 code in the mips64 tree */ - - struct task_struct *p; + /* + * Crude estimate until we actually meassure ... + */ + cpu_khz = loops_per_jiffy * 2 * HZ / 1000; + /* + * Rough estimation for SMP scheduling, this is the number of + * cycles it takes for a fully memory-limited process to flush + * the SMP-local cache. + * + * (For a P5 this pretty much means we will choose another idle + * CPU almost always at wakeup time (this is due to the small + * L1 cache), on PIIs it's around 50-100 usecs, depending on + * the cache size) + */ + if (!cpu_khz) { /* - * The following code is purely to make sure - * Linux can schedule processes on this slave. + * This basically disables processor-affinity scheduling on SMP + * without a cycle counter. Currently all SMP capable MIPS + * processors have a cycle counter. */ - kernel_thread(0, NULL, CLONE_IDLETASK); - p = prev_task(&init_task); - sprintf(p->comm, "%s%d", "Idle", i); - init_tasks[i] = p; - p->processor = i; - p->cpus_runnable = 1 << i; /* we schedule the first task manually */ - del_from_runqueue(p); - unhash_process(p); - /* Attach to the address space of init_task. */ - atomic_inc(&init_mm.mm_count); - p->active_mm = &init_mm; - prom_boot_secondary(i, - (unsigned long)p + KERNEL_STACK_SIZE - 32, - (unsigned long)p); -#endif + cacheflush_time = 0; + return; } - /* Wait for everyone to come up */ - while (atomic_read(&cpus_booted) != smp_num_cpus); + cachesize = cd->linesz * cd->sets * cd->ways; + cacheflush_time = (cpu_khz>>10) * (cachesize<<10) / bandwidth; + cache_decay_ticks = (long)cacheflush_time/cpu_khz * HZ / 1000; + + printk("per-CPU timeslice cutoff: %ld.%02ld usecs.\n", + (long)cacheflush_time/(cpu_khz/1000), + ((long)cacheflush_time*100/(cpu_khz/1000)) % 100); + printk("task migration cache decay timeout: %ld msecs.\n", + (cache_decay_ticks + 1) * 1000 / HZ); } -void __init smp_commence(void) +void __init smp_callin(void) { - /* Not sure what to do here yet */ +#if 0 + calibrate_delay(); + smp_store_cpu_info(cpuid); +#endif } -static void reschedule_this_cpu(void *dummy) +#ifndef CONFIG_SGI_IP27 +/* + * Hook for doing final board-specific setup after the generic smp setup + * is done + */ +asmlinkage void start_secondary(void) { - current->work.need_resched = 1; + unsigned int cpu = smp_processor_id(); + + cpu_probe(); + prom_init_secondary(); + per_cpu_trap_init(); + + /* + * XXX parity protection should be folded in here when it's converted + * to an option instead of something based on .cputype + */ + pgd_current[cpu] = init_mm.pgd; + cpu_data[cpu].udelay_val = loops_per_jiffy; + prom_smp_finish(); + printk("Slave cpu booted successfully\n"); + CPUMASK_SETB(cpu_online_map, cpu); + atomic_inc(&cpus_booted); + cpu_idle(); } +#endif /* CONFIG_SGI_IP27 */ -void FASTCALL(smp_send_reschedule(int cpu)) +/* + * this function sends a 'reschedule' IPI to another CPU. + * it goes straight through and wastes no time serializing + * anything. Worst case is that we lose a reschedule ... + */ +void smp_send_reschedule(int cpu) { - smp_call_function(reschedule_this_cpu, NULL, 0, 0); + core_send_ipi(cpu, SMP_RESCHEDULE_YOURSELF); } +static spinlock_t call_lock = SPIN_LOCK_UNLOCKED; + +struct call_data_struct *call_data; /* - * The caller of this wants the passed function to run on every cpu. If wait - * is set, wait until all cpus have finished the function before returning. - * The lock is here to protect the call structure. + * Run a function on all other CPUs. + * The function to run. This must be fast and non-blocking. + * An arbitrary pointer to pass to the function. + * If true, keep retrying until ready. + * If true, wait until function has completed on other CPUs. + * [RETURNS] 0 on success, else a negative status code. + * + * Does not return until remote CPUs are nearly ready to execute + * or are or have executed. + * * You must not call this function with disabled interrupts or from a * hardware interrupt handler or from a bottom half handler. */ -int smp_call_function (void (*func) (void *info), void *info, int retry, +int smp_call_function (void (*func) (void *info), void *info, int retry, int wait) { - int cpus = smp_num_cpus - 1; - int i; + struct call_data_struct data; + int i, cpus = num_online_cpus() - 1; + int cpu = smp_processor_id(); - if (smp_num_cpus < 2) { + if (!cpus) return 0; - } - - spin_lock(&smp_fn_call.lock); - atomic_set(&smp_fn_call.finished, 0); - smp_fn_call.fn = func; - smp_fn_call.data = info; - - for (i = 0; i < smp_num_cpus; i++) { - if (i != smp_processor_id()) { - /* Call the board specific routine */ - core_call_function(i); - } - } - - if (wait) { - while(atomic_read(&smp_fn_call.finished) != cpus) {} - } + data.func = func; + data.info = info; + atomic_set(&data.started, 0); + data.wait = wait; + if (wait) + atomic_set(&data.finished, 0); + + spin_lock(&call_lock); + call_data = &data; + + /* Send a message to all other CPUs and wait for them to respond */ + for (i = 0; i < NR_CPUS; i++) + if (cpu_online(cpu) && cpu != smp_processor_id()) + core_send_ipi(i, SMP_CALL_FUNCTION); + + /* Wait for response */ + /* FIXME: lock-up detection, backtrace on lock-up */ + while (atomic_read(&data.started) != cpus) + barrier(); + + if (wait) + while (atomic_read(&data.finished) != cpus) + barrier(); + spin_unlock(&call_lock); - spin_unlock(&smp_fn_call.lock); return 0; } -void synchronize_irq(void) +void smp_call_function_interrupt(void) { - panic("synchronize_irq"); + void (*func) (void *info) = call_data->func; + void *info = call_data->info; + int wait = call_data->wait; + + irq_enter(); + /* + * Notify initiating CPU that I've grabbed the data and am + * about to execute the function. + */ + mb(); + atomic_inc(&call_data->started); + + /* + * At this point the info structure may be out of scope unless wait==1. + */ + irq_enter(); + (*func)(info); + irq_exit(); + + if (wait) { + mb(); + atomic_inc(&call_data->finished); + } } static void stop_this_cpu(void *dummy) { - printk("Cpu stopping\n"); - for (;;); + /* + * Remove this CPU: + */ + clear_bit(smp_processor_id(), &cpu_online_map); + local_irq_enable(); /* May need to service _machine_restart IPI */ + for (;;); /* Wait if available. */ } void smp_send_stop(void) { smp_call_function(stop_this_cpu, NULL, 1, 0); - smp_num_cpus = 1; } /* Not really SMP stuff ... */ @@ -246,157 +266,142 @@ int setup_profiling_timer(unsigned int m return 0; } +static void flush_tlb_all_ipi(void *info) +{ + local_flush_tlb_all(); +} + +void flush_tlb_all(void) +{ + on_each_cpu(flush_tlb_all_ipi, 0, 1, 1); +} + +static void flush_tlb_mm_ipi(void *mm) +{ + local_flush_tlb_mm((struct mm_struct *)mm); +} /* - * Most of this code is take from the mips64 tree (ip27-irq.c). It's virtually - * identical to the i386 implentation in arh/i386/irq.c, with translations for - * the interrupt enable bit + * The following tlb flush calls are invoked when old translations are + * being torn down, or pte attributes are changing. For single threaded + * address spaces, a new context is obtained on the current cpu, and tlb + * context on other cpus are invalidated to force a new context allocation + * at switch_mm time, should the mm ever be used on other cpus. For + * multithreaded address spaces, intercpu interrupts have to be sent. + * Another case where intercpu interrupts are required is when the target + * mm might be active on another cpu (eg debuggers doing the flushes on + * behalf of debugees, kswapd stealing pages from another process etc). + * Kanoj 07/00. */ -#define MAXCOUNT 100000000 -#define SYNC_OTHER_CORES(x) udelay(x+1) - -static inline void wait_on_irq(int cpu) +void flush_tlb_mm(struct mm_struct *mm) { - int count = MAXCOUNT; - - for (;;) { + preempt_disable(); - /* - * Wait until all interrupts are gone. Wait - * for bottom half handlers unless we're - * already executing in one.. - */ - if (!irqs_running()) - if (local_bh_count(cpu) || !spin_is_locked(&global_bh_lock)) - break; - - /* Duh, we have to loop. Release the lock to avoid deadlocks */ - spin_unlock(&global_irq_lock); - - for (;;) { - if (!--count) { - printk("Count spun out. Huh?\n"); - count = ~0; - } - local_irq_enable(); - SYNC_OTHER_CORES(cpu); - local_irq_disable(); - if (irqs_running()) - continue; - if (spin_is_locked(&global_irq_lock)) - continue; - if (!local_bh_count(cpu) && spin_is_locked(&global_bh_lock)) - continue; - if (spin_trylock(&global_irq_lock)) - break; - } + if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { + smp_call_function(flush_tlb_mm_ipi, (void *)mm, 1, 1); + } else { + int i; + for (i = 0; i < num_online_cpus(); i++) + if (smp_processor_id() != i) + cpu_context(i, mm) = 0; } + local_flush_tlb_mm(mm); + + preempt_enable(); } +struct flush_tlb_data { + struct vm_area_struct *vma; + unsigned long addr1; + unsigned long addr2; +}; -static inline void get_irqlock(int cpu) +static void flush_tlb_range_ipi(void *info) { - if (!spin_trylock(&global_irq_lock)) { - /* do we already hold the lock? */ - if ((unsigned char) cpu == global_irq_holder) - return; - /* Uhhuh.. Somebody else got it. Wait.. */ - spin_lock(&global_irq_lock); - } - /* - * We also to make sure that nobody else is running - * in an interrupt context. - */ - wait_on_irq(cpu); + struct flush_tlb_data *fd = (struct flush_tlb_data *)info; - /* - * Ok, finally.. - */ - global_irq_holder = cpu; + local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); } - -/* - * A global "cli()" while in an interrupt context - * turns into just a local cli(). Interrupts - * should use spinlocks for the (very unlikely) - * case that they ever want to protect against - * each other. - * - * If we already have local interrupts disabled, - * this will not turn a local disable into a - * global one (problems with spinlocks: this makes - * save_flags+cli+sti usable inside a spinlock). - */ -void __global_cli(void) +void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - unsigned int flags; + struct mm_struct *mm = vma->vm_mm; - local_save_flags(flags); - if (flags & ST0_IE) { - int cpu = smp_processor_id(); - local_irq_disable(); - if (!local_irq_count(cpu)) - get_irqlock(cpu); + preempt_disable(); + if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { + struct flush_tlb_data fd; + + fd.vma = vma; + fd.addr1 = start; + fd.addr2 = end; + smp_call_function(flush_tlb_range_ipi, (void *)&fd, 1, 1); + } else { + int i; + for (i = 0; i < num_online_cpus(); i++) + if (smp_processor_id() != i) + cpu_context(i, mm) = 0; } + local_flush_tlb_range(vma, start, end); + preempt_enable(); } -void __global_sti(void) +static void flush_tlb_kernel_range_ipi(void *info) { - int cpu = smp_processor_id(); + struct flush_tlb_data *fd = (struct flush_tlb_data *)info; - if (!local_irq_count(cpu)) - release_irqlock(cpu); - local_irq_enable(); + local_flush_tlb_kernel_range(fd->addr1, fd->addr2); } -/* - * SMP flags value to restore to: - * 0 - global cli - * 1 - global sti - * 2 - local cli - * 3 - local sti - */ -unsigned long __global_save_flags(void) +void flush_tlb_kernel_range(unsigned long start, unsigned long end) { - int retval; - int local_enabled; - unsigned long flags; - int cpu = smp_processor_id(); + struct flush_tlb_data fd; - local_save_flags(flags); - local_enabled = (flags & ST0_IE); - /* default to local */ - retval = 2 + local_enabled; - - /* check for global flags if we're not in an interrupt */ - if (!local_irq_count(cpu)) { - if (local_enabled) - retval = 1; - if (global_irq_holder == cpu) - retval = 0; - } + fd.addr1 = start; + fd.addr2 = end; + on_each_cpu(flush_tlb_kernel_range_ipi, (void *)&fd, 1, 1); +} + +static void flush_tlb_page_ipi(void *info) +{ + struct flush_tlb_data *fd = (struct flush_tlb_data *)info; - return retval; + local_flush_tlb_page(fd->vma, fd->addr1); } -void __global_restore_flags(unsigned long flags) +void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) { - switch (flags) { - case 0: - __global_cli(); - break; - case 1: - __global_sti(); - break; - case 2: - local_irq_disable(); - break; - case 3: - local_irq_enable(); - break; - default: - printk("global_restore_flags: %08lx\n", flags); + preempt_disable(); + if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { + struct flush_tlb_data fd; + + fd.vma = vma; + fd.addr1 = page; + smp_call_function(flush_tlb_page_ipi, (void *)&fd, 1, 1); + } else { + int i; + for (i = 0; i < num_online_cpus(); i++) + if (smp_processor_id() != i) + cpu_context(i, vma->vm_mm) = 0; } + local_flush_tlb_page(vma, page); + preempt_enable(); } + +static void flush_tlb_one_ipi(void *info) +{ + unsigned long vaddr = (unsigned long) info; + + local_flush_tlb_one(vaddr); +} + +void flush_tlb_one(unsigned long vaddr) +{ + smp_call_function(flush_tlb_one_ipi, (void *) vaddr, 1, 1); + local_flush_tlb_one(vaddr); +} + +EXPORT_SYMBOL(flush_tlb_page); +EXPORT_SYMBOL(flush_tlb_one); +EXPORT_SYMBOL(cpu_data); +EXPORT_SYMBOL(synchronize_irq); --- linux-2.5.73/arch/mips/kernel/syscall.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/syscall.c 2003-06-27 15:56:23.000000000 -0700 @@ -14,6 +14,7 @@ #undef CONF_DEBUG_IRIX #include +#include #include #include #include @@ -28,7 +29,7 @@ #include #include #include -#include +#include #include extern asmlinkage void syscall_trace(void); @@ -54,6 +55,61 @@ out: return res; } +unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */ + +#define COLOUR_ALIGN(addr,pgoff) \ + ((((addr) + shm_align_mask) & ~shm_align_mask) + \ + (((pgoff) << PAGE_SHIFT) & shm_align_mask)) + +unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, + unsigned long len, unsigned long pgoff, unsigned long flags) +{ + struct vm_area_struct * vmm; + int do_color_align; + + if (flags & MAP_FIXED) { + /* + * We do not accept a shared mapping if it would violate + * cache aliasing constraints. + */ + if ((flags & MAP_SHARED) && (addr & shm_align_mask)) + return -EINVAL; + return addr; + } + + if (len > TASK_SIZE) + return -ENOMEM; + do_color_align = 0; + if (filp || (flags & MAP_SHARED)) + do_color_align = 1; + if (addr) { + if (do_color_align) + addr = COLOUR_ALIGN(addr, pgoff); + else + addr = PAGE_ALIGN(addr); + vmm = find_vma(current->mm, addr); + if (TASK_SIZE - len >= addr && + (!vmm || addr + len <= vmm->vm_start)) + return addr; + } + addr = TASK_UNMAPPED_BASE; + if (do_color_align) + addr = COLOUR_ALIGN(addr, pgoff); + else + addr = PAGE_ALIGN(addr); + + for (vmm = find_vma(current->mm, addr); ; vmm = vmm->vm_next) { + /* At this point: (!vmm || addr < vmm->vm_end). */ + if (TASK_SIZE - len < addr) + return -ENOMEM; + if (!vmm || addr + len <= vmm->vm_start) + return addr; + addr = vmm->vm_end; + if (do_color_align) + addr = COLOUR_ALIGN(addr, pgoff); + } +} + /* common code for old and new mmaps */ static inline long do_mmap2(unsigned long addr, unsigned long len, unsigned long prot, @@ -82,7 +138,16 @@ out: asmlinkage unsigned long old_mmap(unsigned long addr, size_t len, int prot, int flags, int fd, off_t offset) { - return do_mmap2(addr, len, prot, flags, fd, offset >> PAGE_SHIFT); + int result; + + result = -EINVAL; + if (offset & ~PAGE_MASK) + goto out; + + result = do_mmap2(addr, len, prot, flags, fd, offset >> PAGE_SHIFT); + +out: + return result; } asmlinkage long @@ -95,10 +160,7 @@ sys_mmap2(unsigned long addr, unsigned l save_static_function(sys_fork); static_unused int _sys_fork(struct pt_regs regs) { - struct task_struct *p; - - p = do_fork(SIGCHLD, regs.regs[29], ®s, 0); - return IS_ERR(p) ? PTR_ERR(p) : p->pid; + return do_fork(SIGCHLD, regs.regs[29], ®s, 0, NULL, NULL); } @@ -107,14 +169,16 @@ static_unused int _sys_clone(struct pt_r { unsigned long clone_flags; unsigned long newsp; - struct task_struct *p; + int *parent_tidptr, *child_tidptr; clone_flags = regs.regs[4]; newsp = regs.regs[5]; if (!newsp) newsp = regs.regs[29]; - p = do_fork(clone_flags & ~CLONE_IDLETASK, newsp, ®s, 0); - return IS_ERR(p) ? PTR_ERR(p) : p->pid; + parent_tidptr = (int *) regs.regs[6]; + child_tidptr = (int *) regs.regs[7]; + return do_fork(clone_flags & ~CLONE_IDLETASK, newsp, ®s, 0, + parent_tidptr, child_tidptr); } /* @@ -158,7 +222,7 @@ asmlinkage int sys_olduname(struct oldol return -EFAULT; if (!access_ok(VERIFY_WRITE,name,sizeof(struct oldold_utsname))) return -EFAULT; - + error = __copy_to_user(&name->sysname,&system_utsname.sysname,__OLD_UTS_LEN); error -= __put_user(0,name->sysname+__OLD_UTS_LEN); error -= __copy_to_user(&name->nodename,&system_utsname.nodename,__OLD_UTS_LEN); @@ -175,76 +239,6 @@ asmlinkage int sys_olduname(struct oldol } /* - * Do the indirect syscall syscall. - * Don't care about kernel locking; the actual syscall will do it. - * - * XXX This is borken. - */ -asmlinkage int sys_syscall(struct pt_regs regs) -{ - syscall_t syscall; - unsigned long syscallnr = regs.regs[4]; - unsigned long a0, a1, a2, a3, a4, a5, a6; - int nargs, errno; - - if (syscallnr > __NR_Linux + __NR_Linux_syscalls) - return -ENOSYS; - - syscall = sys_call_table[syscallnr]; - nargs = sys_narg_table[syscallnr]; - /* - * Prevent stack overflow by recursive - * syscall(__NR_syscall, __NR_syscall,...); - */ - if (syscall == (syscall_t) sys_syscall) { - return -EINVAL; - } - - if (syscall == NULL) { - return -ENOSYS; - } - - if(nargs > 3) { - unsigned long usp = regs.regs[29]; - unsigned long *sp = (unsigned long *) usp; - if(usp & 3) { - printk("unaligned usp -EFAULT\n"); - force_sig(SIGSEGV, current); - return -EFAULT; - } - errno = verify_area(VERIFY_READ, (void *) (usp + 16), - (nargs - 3) * sizeof(unsigned long)); - if(errno) { - return -EFAULT; - } - switch(nargs) { - case 7: - a3 = sp[4]; a4 = sp[5]; a5 = sp[6]; a6 = sp[7]; - break; - case 6: - a3 = sp[4]; a4 = sp[5]; a5 = sp[6]; a6 = 0; - break; - case 5: - a3 = sp[4]; a4 = sp[5]; a5 = a6 = 0; - break; - case 4: - a3 = sp[4]; a4 = a5 = a6 = 0; - break; - - default: - a3 = a4 = a5 = a6 = 0; - break; - } - } else { - a3 = a4 = a5 = a6 = 0; - } - a0 = regs.regs[5]; a1 = regs.regs[6]; a2 = regs.regs[7]; - if(nargs == 0) - a0 = (unsigned long) ®s; - return syscall((void *)a0, a1, a2, a3, a4, a5, a6); -} - -/* * If we ever come here the user sp is bad. Zap the process right away. * Due to the bad stack signaling wouldn't work. * XXX kernel locking??? --- linux-2.5.73/arch/mips/kernel/syscalls.h 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/syscalls.h 2003-06-27 15:56:23.000000000 -0700 @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001, 2002 by Ralf Baechle */ /* @@ -20,7 +20,7 @@ SYS(sys_fork, 0) SYS(sys_read, 3) SYS(sys_write, 3) SYS(sys_open, 3) /* 4005 */ -SYS(sys_close, 3) +SYS(sys_close, 1) SYS(sys_waitpid, 3) SYS(sys_creat, 2) SYS(sys_link, 2) @@ -32,7 +32,7 @@ SYS(sys_mknod, 3) SYS(sys_chmod, 2) /* 4015 */ SYS(sys_lchown, 3) SYS(sys_ni_syscall, 0) -SYS(sys_stat, 2) +SYS(sys_ni_syscall, 0) /* was sys_stat */ SYS(sys_lseek, 3) SYS(sys_getpid, 0) /* 4020 */ SYS(sys_mount, 5) @@ -42,7 +42,7 @@ SYS(sys_getuid, 0) SYS(sys_stime, 1) /* 4025 */ SYS(sys_ptrace, 4) SYS(sys_alarm, 1) -SYS(sys_fstat, 2) +SYS(sys_ni_syscall, 0) /* was sys_fstat */ SYS(sys_pause, 0) SYS(sys_utime, 2) /* 4030 */ SYS(sys_ni_syscall, 0) @@ -96,9 +96,9 @@ SYS(sys_gettimeofday, 2) SYS(sys_settimeofday, 2) SYS(sys_getgroups, 2) /* 4080 */ SYS(sys_setgroups, 2) -SYS(sys_ni_syscall, 0) /* old_select */ +SYS(sys_ni_syscall, 0) /* old_select */ SYS(sys_symlink, 2) -SYS(sys_lstat, 2) +SYS(sys_ni_syscall, 0) /* was sys_lstat */ SYS(sys_readlink, 3) /* 4085 */ SYS(sys_uselib, 1) SYS(sys_swapon, 2) @@ -115,7 +115,7 @@ SYS(sys_setpriority, 3) SYS(sys_ni_syscall, 0) SYS(sys_statfs, 2) SYS(sys_fstatfs, 2) /* 4100 */ -SYS(sys_ioperm, 3) +SYS(sys_ni_syscall, 0) /* was ioperm(2) */ SYS(sys_socketcall, 2) SYS(sys_syslog, 3) SYS(sys_setitimer, 3) @@ -124,10 +124,10 @@ SYS(sys_newstat, 2) SYS(sys_newlstat, 2) SYS(sys_newfstat, 2) SYS(sys_uname, 1) -SYS(sys_iopl, 0) /* Well, actually 17 args ... */ /* 4110 */ +SYS(sys_ni_syscall, 0) /* 4110 was iopl(2) */ SYS(sys_vhangup, 0) -SYS(sys_ni_syscall, 0) /* was sys_idle() */ -SYS(sys_vm86, 1) +SYS(sys_ni_syscall, 0) /* was sys_idle() */ +SYS(sys_ni_syscall, 0) /* was sys_vm86 */ SYS(sys_wait4, 4) SYS(sys_swapoff, 1) /* 4115 */ SYS(sys_sysinfo, 1) @@ -141,10 +141,10 @@ SYS(sys_ni_syscall, 0) /* sys_modify_ldt SYS(sys_adjtimex, 1) SYS(sys_mprotect, 3) /* 4125 */ SYS(sys_sigprocmask, 3) -SYS(sys_create_module, 2) +SYS(sys_ni_syscall, 0) /* was create_module */ SYS(sys_init_module, 5) SYS(sys_delete_module, 1) -SYS(sys_get_kernel_syms, 1) /* 4130 */ +SYS(sys_ni_syscall, 0) /* 4130, was get_kernel_syms */ SYS(sys_quotactl, 0) SYS(sys_getpgid, 1) SYS(sys_fchdir, 1) @@ -201,7 +201,7 @@ SYS(sys_socket, 3) SYS(sys_socketpair, 4) SYS(sys_setresuid, 3) /* 4185 */ SYS(sys_getresuid, 3) -SYS(sys_query_module, 5) +SYS(sys_ni_syscall, 0) /* sys_query_module */ SYS(sys_poll, 3) SYS(sys_nfsservctl, 3) SYS(sys_setresgid, 3) /* 4190 */ @@ -214,19 +214,19 @@ SYS(sys_rt_sigpending, 2) SYS(sys_rt_sigtimedwait, 4) SYS(sys_rt_sigqueueinfo, 3) SYS(sys_rt_sigsuspend, 0) -SYS(sys_pread, 6) /* 4200 */ -SYS(sys_pwrite, 6) +SYS(sys_pread64, 6) /* 4200 */ +SYS(sys_pwrite64, 6) SYS(sys_chown, 3) SYS(sys_getcwd, 2) SYS(sys_capget, 2) SYS(sys_capset, 2) /* 4205 */ SYS(sys_sigaltstack, 0) -SYS(sys_sendfile, 3) +SYS(sys_sendfile, 4) SYS(sys_ni_syscall, 0) SYS(sys_ni_syscall, 0) SYS(sys_mmap2, 6) /* 4210 */ -SYS(sys_truncate64, 2) -SYS(sys_ftruncate64, 2) +SYS(sys_truncate64, 4) +SYS(sys_ftruncate64, 4) SYS(sys_stat64, 2) SYS(sys_lstat64, 2) SYS(sys_fstat64, 2) /* 4215 */ @@ -235,5 +235,39 @@ SYS(sys_mincore, 3) SYS(sys_madvise, 3) SYS(sys_getdents64, 3) SYS(sys_fcntl64, 3) /* 4220 */ +SYS(sys_ni_syscall, 0) SYS(sys_gettid, 0) +SYS(sys_readahead, 5) +SYS(sys_setxattr, 5) +SYS(sys_lsetxattr, 5) /* 4225 */ +SYS(sys_fsetxattr, 5) +SYS(sys_getxattr, 4) +SYS(sys_lgetxattr, 4) +SYS(sys_fgetxattr, 4) +SYS(sys_listxattr, 3) /* 4230 */ +SYS(sys_llistxattr, 3) +SYS(sys_flistxattr, 3) +SYS(sys_removexattr, 2) +SYS(sys_lremovexattr, 2) +SYS(sys_fremovexattr, 2) /* 4235 */ SYS(sys_tkill, 2) +SYS(sys_sendfile64, 5) +SYS(sys_futex, 2) +SYS(sys_sched_setaffinity, 3) +SYS(sys_sched_getaffinity, 3) /* 4240 */ +SYS(sys_io_setup, 2) +SYS(sys_io_destroy, 1) +SYS(sys_io_getevents, 5) +SYS(sys_io_submit, 3) +SYS(sys_io_cancel, 3) /* 4245 */ +SYS(sys_exit_group, 1) +SYS(sys_lookup_dcookie, 3) +SYS(sys_epoll_create, 1) +SYS(sys_epoll_ctl, 4) +SYS(sys_epoll_wait, 3) /* 4250 */ +SYS(sys_remap_file_pages, 5) +SYS(sys_set_tid_address, 1) +SYS(sys_restart_syscall, 0) /* XXX */ +SYS(sys_fadvise64, 6) +SYS(sys_statfs64, 3) /* 4255 */ +SYS(sys_fstatfs64, 2) --- linux-2.5.73/arch/mips/kernel/sysirix.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/sysirix.c 2003-06-27 15:56:23.000000000 -0700 @@ -7,6 +7,8 @@ */ #include #include +#include +#include #include #include #include @@ -24,6 +26,8 @@ #include #include #include +#include +#include #include #include @@ -55,7 +59,7 @@ asmlinkage int irix_sysmp(struct pt_regs break; case MP_NPROCS: case MP_NAPROCS: - error = smp_num_cpus; + error = num_online_cpus(); break; default: printk("SYSMP[%s:%d]: Unsupported opcode %d\n", @@ -111,7 +115,7 @@ asmlinkage int irix_prctl(struct pt_regs if (error) error = (task->run_list.next != NULL); read_unlock(&tasklist_lock); - /* Can _your_ OS find this out that fast? */ + /* Can _your_ OS find this out that fast? */ break; } @@ -334,7 +338,7 @@ asmlinkage int irix_syssgi(struct pt_reg current->comm, current->pid, name, value, retval); /* if (retval == PROM_ENOENT) retval = -ENOENT; */ - break; + break; } #endif @@ -507,7 +511,7 @@ asmlinkage int irix_syssgi(struct pt_reg } break; } - + default: printk("irix_syssgi: Unsupported command %d\n", (int)cmd); retval = -EINVAL; @@ -600,7 +604,7 @@ out: asmlinkage int irix_getpid(struct pt_regs *regs) { - regs->regs[3] = current->p_opptr->pid; + regs->regs[3] = current->real_parent->pid; return current->pid; } @@ -623,9 +627,11 @@ asmlinkage int irix_stime(int value) write_seqlock_irq(&xtime_lock); xtime.tv_sec = value; - xtime.tv_usec = 0; - time_maxerror = MAXPHASE; - time_esterror = MAXPHASE; + xtime.tv_nsec = 0; + time_adjust = 0; /* stop active adjtime() */ + time_status |= STA_UNSYNC; + time_maxerror = NTP_PHASE_LIMIT; + time_esterror = NTP_PHASE_LIMIT; write_sequnlock_irq(&xtime_lock); return 0; @@ -819,10 +825,10 @@ asmlinkage int irix_times(struct tms * t err = verify_area(VERIFY_WRITE,tbuf,sizeof *tbuf); if (err) return err; - err |= __put_user(current->times.tms_utime,&tbuf->tms_utime); - err |= __put_user(current->times.tms_stime,&tbuf->tms_stime); - err |= __put_user(current->times.tms_cutime,&tbuf->tms_cutime); - err |= __put_user(current->times.tms_cstime,&tbuf->tms_cstime); + err |= __put_user(current->utime, &tbuf->tms_utime); + err |= __put_user(current->stime, &tbuf->tms_stime); + err |= __put_user(current->cutime, &tbuf->tms_cutime); + err |= __put_user(current->cstime, &tbuf->tms_cstime); } return err; @@ -1048,7 +1054,23 @@ asmlinkage int irix_sgikopt(char *istrin asmlinkage int irix_gettimeofday(struct timeval *tv) { - return copy_to_user(tv, &xtime, sizeof(*tv)) ? -EFAULT : 0; + time_t sec; + long nsec, seq; + int err; + + if (verify_area(VERIFY_WRITE, tv, sizeof(struct timeval))) + return -EFAULT; + + do { + seq = read_seqbegin(&xtime_lock); + sec = xtime.tv_sec; + nsec = xtime.tv_nsec; + } while (read_seqretry(&xtime_lock, seq)); + + err = __put_user(sec, &tv->tv_sec); + err |= __put_user((nsec / 1000), &tv->tv_usec); + + return err; } #define IRIX_MAP_AUTOGROW 0x40 @@ -1068,7 +1090,7 @@ asmlinkage unsigned long irix_mmap32(uns if (flags & IRIX_MAP_AUTOGROW) { unsigned long old_pos; long max_size = offset + len; - + if (max_size > file->f_dentry->d_inode->i_size) { old_pos = sys_lseek (fd, max_size - 1, 0); sys_write (fd, "", 1); @@ -1198,14 +1220,14 @@ static inline int irix_xstat32_xlate(str #if BITS_PER_LONG == 32 if (stat->size > MAX_NON_LFS) return -EOVERFLOW; -#endif +#endif ub.st_size = stat->size; - ub.st_atime0 = stat->atime; - ub.st_atime1 = 0; - ub.st_mtime0 = stat->mtime; - ub.st_mtime1 = 0; - ub.st_ctime0 = stat->ctime; - ub.st_ctime1 = 0; + ub.st_atime0 = stat->atime.tv_sec; + ub.st_atime1 = stat->atime.tv_nsec; + ub.st_mtime0 = stat->mtime.tv_sec; + ub.st_mtime1 = stat->atime.tv_nsec; + ub.st_ctime0 = stat->ctime.tv_sec; + ub.st_ctime1 = stat->atime.tv_nsec; ub.st_blksize = stat->blksize; ub.st_blocks = stat->blocks; strcpy (ub.st_fstype, "efs"); @@ -1243,9 +1265,12 @@ static inline void irix_xstat64_xlate(st ks.st_pad3 = 0; /* XXX hackety hack... */ - ks.st_atime.tv_sec = (s32) stat->atime; ks.st_atime.tv_nsec = 0; - ks.st_mtime.tv_sec = (s32) stat->atime; ks.st_mtime.tv_nsec = 0; - ks.st_ctime.tv_sec = (s32) stat->atime; ks.st_ctime.tv_nsec = 0; + ks.st_atime.tv_sec = (s32) stat->atime.tv_sec; + ks.st_atime.tv_nsec = stat->atime.tv_nsec; + ks.st_mtime.tv_sec = (s32) stat->mtime.tv_sec; + ks.st_mtime.tv_nsec = stat->mtime.tv_nsec;; + ks.st_ctime.tv_sec = (s32) stat->ctime.tv_sec; + ks.st_ctime.tv_nsec = stat->ctime.tv_nsec;; ks.st_blksize = (s32) stat->blksize; ks.st_blocks = (long long) stat->blocks; @@ -1812,7 +1837,8 @@ static int irix_filldir32(void *__buf, c return 0; } -asmlinkage int irix_ngetdents(unsigned int fd, void * dirent, unsigned int count, int *eob) +asmlinkage int irix_ngetdents(unsigned int fd, void * dirent, + unsigned int count, int *eob) { struct file *file; struct irix_dirent32 *lastdirent; @@ -1836,6 +1862,7 @@ asmlinkage int irix_ngetdents(unsigned i error = vfs_readdir(file, irix_filldir32, &buf); if (error < 0) goto out_putf; + error = buf.error; lastdirent = buf.previous; if (lastdirent) { @@ -1844,11 +1871,10 @@ asmlinkage int irix_ngetdents(unsigned i } if (put_user(0, eob) < 0) { - error = EFAULT; + error = -EFAULT; goto out_putf; } - #ifdef DEBUG_GETDENTS printk("eob=%d returning %d\n", *eob, count - buf.count); #endif --- linux-2.5.73/arch/mips/kernel/sysmips.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/sysmips.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,13 +1,11 @@ /* - * MIPS specific syscalls - * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1995, 1996, 1997, 2000 by Ralf Baechle + * Copyright (C) 1995, 1996, 1997, 2000, 2001 by Ralf Baechle + * Copyright (C) 2001 MIPS Technologies, Inc. */ -#include #include #include #include @@ -19,7 +17,7 @@ #include #include -#include +#include #include #include @@ -49,11 +47,10 @@ get_max_hostname(unsigned long address) } asmlinkage int -sys_sysmips(int cmd, int arg1, int arg2, int arg3) +_sys_sysmips(int cmd, int arg1, int arg2, int arg3) { - int *p; char *name; - int tmp, len, retval, errno; + int tmp, len, retval; switch(cmd) { case SETNAME: { @@ -65,66 +62,22 @@ sys_sysmips(int cmd, int arg1, int arg2, name = (char *) arg1; len = strncpy_from_user(nodename, name, __NEW_UTS_LEN); - if (len < 0) + if (len < 0) return -EFAULT; - nodename[__NEW_UTS_LEN] = '\0'; down_write(&uts_sem); + strncpy(system_utsname.nodename, nodename, len); + nodename[__NEW_UTS_LEN] = '\0'; strlcpy(system_utsname.nodename, nodename, - sizeof(system_utsname.nodename)); + sizeof(system_utsname.nodename)); up_write(&uts_sem); return 0; } - case MIPS_ATOMIC_SET: { -#ifdef CONFIG_CPU_HAS_LLSC - unsigned int tmp; - - p = (int *) arg1; - errno = verify_area(VERIFY_WRITE, p, sizeof(*p)); - if (errno) - return errno; - errno = 0; - - __asm__(".set\tpush\t\t\t# sysmips(MIPS_ATOMIC, ...)\n\t" - ".set\tmips2\n\t" - ".set\tnoat\n\t" - "1:\tll\t%0, %4\n\t" - "move\t$1, %3\n\t" - "2:\tsc\t$1, %1\n\t" - "beqz\t$1, 1b\n\t" - ".set\tpop\n\t" - ".section\t.fixup,\"ax\"\n" - "3:\tli\t%2, 1\t\t\t# error\n\t" - ".previous\n\t" - ".section\t__ex_table,\"a\"\n\t" - ".word\t1b, 3b\n\t" - ".word\t2b, 3b\n\t" - ".previous\n\t" - : "=&r" (tmp), "=o" (* (u32 *) p), "=r" (errno) - : "r" (arg2), "o" (* (u32 *) p), "2" (errno) - : "$1"); - - if (errno) - return -EFAULT; - - /* We're skipping error handling etc. */ - if (current->ptrace & PT_TRACESYS) - syscall_trace(); - - ((struct pt_regs *)&cmd)->regs[2] = tmp; - ((struct pt_regs *)&cmd)->regs[7] = 0; - - __asm__ __volatile__( - "move\t$29, %0\n\t" - "j\to32_ret_from_sys_call" - : /* No outputs */ - : "r" (&cmd)); - /* Unreached */ -#else - printk("sys_sysmips(MIPS_ATOMIC_SET, ...) not ready for !CONFIG_CPU_HAS_LLSC\n"); -#endif - } + case MIPS_ATOMIC_SET: + printk(KERN_CRIT "How did I get here?\n"); + retval = -EINVAL; + goto out; case MIPS_FIXADE: tmp = current->thread.mflags & ~3; @@ -133,7 +86,7 @@ sys_sysmips(int cmd, int arg1, int arg2, goto out; case FLUSH_CACHE: - flush_cache_all(); + __flush_cache_all(); retval = 0; goto out; --- linux-2.5.73/arch/mips/kernel/time.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/time.c 2003-06-27 15:56:23.000000000 -0700 @@ -2,8 +2,8 @@ * Copyright 2001 MontaVista Software Inc. * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net * - * Common time service routines for MIPS machines. See - * Documentation/mips/time.README. + * Common time service routines for MIPS machines. See + * Documents/mips/README.txt. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -30,7 +31,9 @@ /* This is for machines which generate the exact clock. */ #define USECS_PER_JIFFY (1000000/HZ) -#define USECS_PER_JIFFY_FRAC ((1000000ULL << 32) / HZ & 0xffffffff) +#define USECS_PER_JIFFY_FRAC ((u32)((1000000ULL << 32) / HZ)) + +#define TICK_SIZE (tick_nsec / 1000) u64 jiffies_64 = INITIAL_JIFFIES; @@ -39,6 +42,13 @@ u64 jiffies_64 = INITIAL_JIFFIES; */ extern volatile unsigned long wall_jiffies; +spinlock_t rtc_lock = SPIN_LOCK_UNLOCKED; + +/* + * whether we emulate local_timer_interrupts for SMP machines. + */ +int emulate_local_timer_interrupt; + /* * By default we provide the null RTC ops */ @@ -57,58 +67,64 @@ int (*rtc_set_time)(unsigned long) = nul /* - * timeofday services, for syscalls. + * This version of gettimeofday has microsecond resolution and better than + * microsecond precision on fast machines with cycle counter. */ void do_gettimeofday(struct timeval *tv) { - unsigned long flags; unsigned long seq; + unsigned long usec, sec; do { - seq = read_seqbegin_irqsave(&xtime_lock, flags); - - *tv = xtime; - tv->tv_usec += do_gettimeoffset(); - - /* - * xtime is atomically updated in timer_bh. - * jiffies - wall_jiffies - * is nonzero if the timer bottom half hasnt executed yet. - */ - if (jiffies - wall_jiffies) - tv->tv_usec += USECS_PER_JIFFY; - } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); - + seq = read_seqbegin(&xtime_lock); + usec = do_gettimeoffset(); + { + unsigned long lost = jiffies - wall_jiffies; + if (lost) + usec += lost * (1000000 / HZ); + } + sec = xtime.tv_sec; + usec += (xtime.tv_nsec / 1000); + } while (read_seqretry(&xtime_lock, seq)); - if (tv->tv_usec >= 1000000) { - tv->tv_usec -= 1000000; - tv->tv_sec++; + while (usec >= 1000000) { + usec -= 1000000; + sec++; } + + tv->tv_sec = sec; + tv->tv_usec = usec; } -void do_settimeofday(struct timeval *tv) +int do_settimeofday(struct timespec *tv) { - write_seqlock_irq (&xtime_lock); + if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC) + return -EINVAL; - /* This is revolting. We need to set the xtime.tv_usec - * correctly. However, the value in this location is - * is value at the last tick. - * Discover what correction gettimeofday - * would have done, and then undo it! + write_seqlock_irq(&xtime_lock); + /* + * This is revolting. We need to set "xtime" correctly. However, the + * value in this location is the value at the most recent update of + * wall time. Discover what correction gettimeofday() would have + * made, and then undo it! */ - tv->tv_usec -= do_gettimeoffset(); + tv->tv_nsec -= do_gettimeoffset() * NSEC_PER_USEC; + tv->tv_nsec -= (jiffies - wall_jiffies) * TICK_NSEC; - if (tv->tv_usec < 0) { - tv->tv_usec += 1000000; + while (tv->tv_nsec < 0) { + tv->tv_nsec += NSEC_PER_SEC; tv->tv_sec--; } - xtime = *tv; - time_adjust = 0; /* stop active adjtime() */ + + xtime.tv_sec = tv->tv_sec; + xtime.tv_nsec = tv->tv_nsec; + time_adjust = 0; /* stop active adjtime() */ time_status |= STA_UNSYNC; time_maxerror = NTP_PHASE_LIMIT; time_esterror = NTP_PHASE_LIMIT; + write_sequnlock_irq(&xtime_lock); - write_sequnlock_irq (&xtime_lock); + return 0; } @@ -137,6 +153,9 @@ static unsigned long cycles_per_jiffy=0; /* Cycle counter value at the previous timer interrupt.. */ static unsigned int timerhi, timerlo; +/* expirelo is the count value for next CPU timer interrupt */ +static unsigned int expirelo; + /* last time when xtime and rtc are sync'ed up */ static long last_rtc_update; @@ -154,7 +173,7 @@ unsigned long fixed_rate_gettimeoffset(v unsigned long res; /* Get last timer tick in absolute kernel time */ - count = read_32bit_cp0_register(CP0_COUNT); + count = read_c0_count(); /* .. relative to previous jiffy (32 bits is enough) */ count -= timerlo; @@ -210,7 +229,7 @@ unsigned long calibrate_div32_gettimeoff } /* Get last timer tick in absolute kernel time */ - count = read_32bit_cp0_register(CP0_COUNT); + count = read_c0_count(); /* .. relative to previous jiffy (32 bits is enough) */ count -= timerlo; @@ -260,13 +279,12 @@ unsigned long calibrate_div64_gettimeoff :"r" (timerhi), "m" (timerlo), "r" (tmp), - "r" (USECS_PER_JIFFY) - :"$1"); + "r" (USECS_PER_JIFFY)); cached_quotient = quotient; } /* Get last timer tick in absolute kernel time */ - count = read_32bit_cp0_register(CP0_COUNT); + count = read_c0_count(); /* .. relative to previous jiffy (32 bits is enough) */ count -= timerlo; @@ -289,35 +307,18 @@ unsigned long calibrate_div64_gettimeoff /* - * high-level timer interrupt service routines. This function - * is set as irqaction->handler and is invoked through do_IRQ. + * local_timer_interrupt() does profiling and process accounting + * on a per-CPU basis. + * + * In UP mode, it is invoked from the (global) timer_interrupt. + * + * In SMP mode, it might invoked by per-CPU timer interrupt, or + * a broadcasted inter-processor interrupt which itself is triggered + * by the global timer interrupt. */ -void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +void local_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { - unsigned long seq; - - if (mips_cpu.options & MIPS_CPU_COUNTER) { - unsigned int count; - - /* - * The cycle counter is only 32 bit which is good for about - * a minute at current count rates of upto 150MHz or so. - */ - count = read_32bit_cp0_register(CP0_COUNT); - timerhi += (count < timerlo); /* Wrap around */ - timerlo = count; - - /* - * set up for next timer interrupt - no harm if the machine - * is using another timer interrupt source. - * Note that writing to COMPARE register clears the interrupt - */ - write_32bit_cp0_register (CP0_COMPARE, - count + cycles_per_jiffy); - - } - - if(!user_mode(regs)) { + if (!user_mode(regs)) { if (prof_buffer && current->pid) { extern int _stext; unsigned long pc = regs->cp0_epc; @@ -335,6 +336,38 @@ void timer_interrupt(int irq, void *dev_ } } +#ifdef CONFIG_SMP + /* in UP mode, update_process_times() is invoked by do_timer() */ + update_process_times(user_mode(regs)); +#endif +} + +/* + * high-level timer interrupt service routines. This function + * is set as irqaction->handler and is invoked through do_IRQ. + */ +irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + if (cpu_has_counter) { + unsigned int count; + + /* ack timer interrupt, and try to set next interrupt */ + expirelo += cycles_per_jiffy; + write_c0_compare(expirelo); + count = read_c0_count(); + + /* check to see if we have missed any timer interrupts */ + if ((count - expirelo) < 0x7fffffff) { + /* missed_timer_count ++; */ + expirelo = count + cycles_per_jiffy; + write_c0_compare(expirelo); + } + + /* Update timerhi/timerlo for intra-jiffy calibration. */ + timerhi += count < timerlo; /* Wrap around */ + timerlo = count; + } + /* * call the generic timer interrupt handling */ @@ -345,21 +378,19 @@ void timer_interrupt(int irq, void *dev_ * CMOS clock accordingly every ~11 minutes. rtc_set_time() has to be * called as close as possible to 500 ms before the new second starts. */ - do { - seq = read_seqbegin(&xtime_lock); - - if ((time_status & STA_UNSYNC) == 0 && - xtime.tv_sec > last_rtc_update + 660 && - xtime.tv_usec >= 500000 - ((unsigned) tick) / 2 && - xtime.tv_usec <= 500000 + ((unsigned) tick) / 2) { - if (rtc_set_time(xtime.tv_sec) == 0) { - last_rtc_update = xtime.tv_sec; - } else { - last_rtc_update = xtime.tv_sec - 600; - /* do it again in 60 s */ - } + write_seqlock(&xtime_lock); + if ((time_status & STA_UNSYNC) == 0 && + xtime.tv_sec > last_rtc_update + 660 && + (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && + (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { + if (rtc_set_time(xtime.tv_sec) == 0) { + last_rtc_update = xtime.tv_sec; + } else { + last_rtc_update = xtime.tv_sec - 600; + /* do it again in 60 s */ } - } while (read_seqretry(&xtime_lock, seq)); + } + write_sequnlock(&xtime_lock); /* * If jiffies has overflowed in this timer_interrupt we must @@ -369,41 +400,83 @@ void timer_interrupt(int irq, void *dev_ if (!jiffies) { timerhi = timerlo = 0; } + +#if !defined(CONFIG_SMP) + /* + * In UP mode, we call local_timer_interrupt() to do profiling + * and process accouting. + * + * In SMP mode, local_timer_interrupt() is invoked by appropriate + * low-level local timer interrupt handler. + */ + local_timer_interrupt(0, NULL, regs); + +#else /* CONFIG_SMP */ + + if (emulate_local_timer_interrupt) { + /* + * this is the place where we send out inter-process + * interrupts and let each CPU do its own profiling + * and process accouting. + * + * Obviously we need to call local_timer_interrupt() for + * the current CPU too. + */ + panic("Not implemented yet!!!"); + } +#endif /* CONFIG_SMP */ + + return IRQ_HANDLED; } asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs) { int cpu = smp_processor_id(); - irq_enter(cpu, irq); + irq_enter(); kstat_cpu(cpu).irqs[irq]++; /* we keep interrupt disabled all the time */ timer_interrupt(irq, NULL, regs); - - irq_exit(cpu, irq); + + irq_exit(); if (softirq_pending(cpu)) do_softirq(); } +asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs) +{ + int cpu = smp_processor_id(); + + irq_enter(); + kstat_cpu(cpu).irqs[irq]++; + + /* we keep interrupt disabled all the time */ + local_timer_interrupt(irq, NULL, regs); + + irq_exit(); + + if (softirq_pending(cpu)) + do_softirq(); +} /* * time_init() - it does the following things. * - * 1) board_time_init() - - * a) (optional) set up RTC routines, + * 1) board_time_init() - + * a) (optional) set up RTC routines, * b) (optional) calibrate and set the mips_counter_frequency * (only needed if you intended to use fixed_rate_gettimeoffset * or use cpu counter as timer interrupt source) * 2) setup xtime based on rtc_get_time(). * 3) choose a appropriate gettimeoffset routine. * 4) calculate a couple of cached variables for later usage - * 5) board_timer_setup() - + * 5) board_timer_setup() - * a) (optional) over-write any choices made above by time_init(). * b) machine specific code should setup the timer irqaction. * c) enable the timer interrupt - */ + */ void (*board_time_init)(void) = NULL; void (*board_timer_setup)(struct irqaction *irq) = NULL; @@ -416,7 +489,8 @@ static struct irqaction timer_irqaction 0, "timer", NULL, - NULL}; + NULL +}; void __init time_init(void) { @@ -424,18 +498,18 @@ void __init time_init(void) board_time_init(); xtime.tv_sec = rtc_get_time(); - xtime.tv_usec = 0; + xtime.tv_nsec = 0; /* choose appropriate gettimeoffset routine */ - if (!(mips_cpu.options & MIPS_CPU_COUNTER)) { + if (!cpu_has_counter) { /* no cpu counter - sorry */ do_gettimeoffset = null_gettimeoffset; } else if (mips_counter_frequency != 0) { /* we have cpu counter and know counter frequency! */ do_gettimeoffset = fixed_rate_gettimeoffset; - } else if ((mips_cpu.isa_level == MIPS_CPU_ISA_M32) || - (mips_cpu.isa_level == MIPS_CPU_ISA_I) || - (mips_cpu.isa_level == MIPS_CPU_ISA_II) ) { + } else if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32) || + (current_cpu_data.isa_level == MIPS_CPU_ISA_I) || + (current_cpu_data.isa_level == MIPS_CPU_ISA_II) ) { /* we need to calibrate the counter but we don't have * 64-bit division. */ do_gettimeoffset = calibrate_div32_gettimeoffset; @@ -443,7 +517,7 @@ void __init time_init(void) /* we need to calibrate the counter but we *do* have * 64-bit division. */ do_gettimeoffset = calibrate_div64_gettimeoffset; - } + } /* caclulate cache parameters */ if (mips_counter_frequency) { @@ -454,16 +528,24 @@ void __init time_init(void) sll32_usecs_per_cycle = mips_counter_frequency / 100000; sll32_usecs_per_cycle = 0xffffffff / sll32_usecs_per_cycle; sll32_usecs_per_cycle *= 10; + + /* + * For those using cpu counter as timer, this sets up the + * first interrupt + */ + write_c0_compare(cycles_per_jiffy); + write_c0_count(0); + expirelo = cycles_per_jiffy; } - /* + /* * Call board specific timer interrupt setup. * - * this pointer must be setup in machine setup routine. + * this pointer must be setup in machine setup routine. * * Even if the machine choose to use low-level timer interrupt, * it still needs to setup the timer_irqaction. - * In that case, it might be better to set timer_irqaction.handler + * In that case, it might be better to set timer_irqaction.handler * to be NULL function so that we are sure the high-level code * is not invoked accidentally. */ @@ -484,10 +566,10 @@ static int month_days[12] = { void to_tm(unsigned long tim, struct rtc_time * tm) { - long hms, day; + long hms, day, gday; int i; - day = tim / SECDAY; + gday = day = tim / SECDAY; hms = tim % SECDAY; /* Hours, minutes, seconds are easy */ @@ -506,7 +588,7 @@ void to_tm(unsigned long tim, struct rtc for (i = 1; day >= days_in_month(i); i++) day -= days_in_month(i); days_in_month(FEBRUARY) = 28; - tm->tm_mon = i; + tm->tm_mon = i-1; /* tm_mon starts from 0 to 11 */ /* Days are what is left over (+1) from all that. */ tm->tm_mday = day + 1; @@ -514,5 +596,7 @@ void to_tm(unsigned long tim, struct rtc /* * Determine the day of week */ - tm->tm_wday = (day + 3) % 7; + tm->tm_wday = (gday + 4) % 7; /* 1970/1/1 was Thursday */ } + +EXPORT_SYMBOL(rtc_lock); --- linux-2.5.73/arch/mips/kernel/traps.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/traps.c 2003-06-27 15:56:23.000000000 -0700 @@ -4,12 +4,12 @@ * for more details. * * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle - * Modified for R3000 by Paul M. Antoine, 1995, 1996 - * Complete output from die() by Ulf Carlsson, 1998 + * Copyright (C) 1995, 1996 Paul M. Antoine + * Copyright (C) 1998 Ulf Carlsson * Copyright (C) 1999 Silicon Graphics, Inc. - * * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000, 01 MIPS Technologies, Inc. + * Copyright (C) 2002, 2003 Maciej W. Rozycki */ #include #include @@ -19,30 +19,23 @@ #include #include #include +#include #include #include #include -#include -#include -#include +#include #include #include -#include -#include -#include +#include +#include #include +#include +#include #include #include - -/* - * Machine specific interrupt handlers - */ -extern asmlinkage void acer_pica_61_handle_int(void); -extern asmlinkage void decstation_handle_int(void); -extern asmlinkage void deskstation_rpc44_handle_int(void); -extern asmlinkage void deskstation_tyne_handle_int(void); -extern asmlinkage void mips_magnum_4000_handle_int(void); +#include +#include extern asmlinkage void handle_mod(void); extern asmlinkage void handle_tlbl(void); @@ -58,16 +51,16 @@ extern asmlinkage void handle_cpu(void); extern asmlinkage void handle_ov(void); extern asmlinkage void handle_tr(void); extern asmlinkage void handle_fpe(void); +extern asmlinkage void handle_mdmx(void); extern asmlinkage void handle_watch(void); extern asmlinkage void handle_mcheck(void); extern asmlinkage void handle_reserved(void); -extern int fpu_emulator_cop1Handler(struct pt_regs *); - -char watch_available = 0; +extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, + struct mips_fpu_soft_struct *ctx); -void (*ibe_board_handler)(struct pt_regs *regs); -void (*dbe_board_handler)(struct pt_regs *regs); +void (*board_be_init)(void); +int (*board_be_handler)(struct pt_regs *regs, int is_fixup); /* * These constant is for searching for possible module text segments. @@ -75,99 +68,74 @@ void (*dbe_board_handler)(struct pt_regs */ #define MODULE_RANGE (8*1024*1024) -#ifndef CONFIG_CPU_HAS_LLSC -/* - * This stuff is needed for the userland ll-sc emulation for R2300 - */ -void simulate_ll(struct pt_regs *regs, unsigned int opcode); -void simulate_sc(struct pt_regs *regs, unsigned int opcode); - -#define OPCODE 0xfc000000 -#define BASE 0x03e00000 -#define RT 0x001f0000 -#define OFFSET 0x0000ffff -#define LL 0xc0000000 -#define SC 0xe0000000 -#endif - /* * This routine abuses get_user()/put_user() to reference pointers * with at least a bit of error checking ... */ -void show_stack(unsigned int *sp) +void show_stack(struct task_struct *task, unsigned long *sp) { + const int field = 2 * sizeof(unsigned long); + long stackdata; int i; - unsigned int *stack; - - stack = sp; - i = 0; - printk("Stack:"); - while ((unsigned long) stack & (PAGE_SIZE - 1)) { - unsigned long stackdata; + sp = sp ? sp : (unsigned long *) &sp; - if (__get_user(stackdata, stack++)) { - printk(" (Bad stack address)"); + printk("Stack: "); + i = 1; + while ((unsigned long) sp & (PAGE_SIZE - 1)) { + if (i && ((i % (64 / sizeof(unsigned long))) == 0)) + printk("\n "); + if (i > 40) { + printk(" ..."); break; } - printk(" %08lx", stackdata); - - if (++i > 40) { - printk(" ..."); + if (__get_user(stackdata, sp++)) { + printk(" (Bad stack address)"); break; } - if (i % 8 == 0) - printk("\n "); + printk(" %0*lx", field, stackdata); + i++; } + printk("\n"); } -void show_trace(unsigned int *sp) +void show_trace(struct task_struct *task, unsigned long *stack) { - int i; - unsigned int *stack; - unsigned long kernel_start, kernel_end; - unsigned long module_start, module_end; - extern char _stext, _etext; - - stack = sp; - i = 0; - - kernel_start = (unsigned long) &_stext; - kernel_end = (unsigned long) &_etext; - module_start = VMALLOC_START; - module_end = module_start + MODULE_RANGE; - - printk("\nCall Trace:"); + const int field = 2 * sizeof(unsigned long); + unsigned long addr; - while ((unsigned long) stack & (PAGE_SIZE -1)) { - unsigned long addr; + if (!stack) + stack = (unsigned long*)&stack; - if (__get_user(addr, stack++)) { - printk(" (Bad stack address)\n"); - break; + printk("Call Trace:"); +#ifdef CONFIG_KALLSYMS + printk("\n"); +#endif + while (((long) stack & (THREAD_SIZE-1)) != 0) { + addr = *stack++; + if (kernel_text_address(addr)) { + printk(" [<%0*lx>] ", field, addr); + print_symbol("%s\n", addr); } + } + printk("\n"); +} - /* - * If the address is either in the text segment of the - * kernel, or in the region which contains vmalloc'ed - * memory, it *may* be the address of a calling - * routine; if so, print it so that someone tracing - * down the cause of the crash will be able to figure - * out the call path that was taken. - */ +void show_trace_task(struct task_struct *tsk) +{ + show_trace(tsk, (long *)tsk->thread.reg29); +} - if ((addr >= kernel_start && addr < kernel_end) || - (addr >= module_start && addr < module_end)) { +/* + * The architecture-independent dump_stack generator + */ +void dump_stack(void) +{ + unsigned long stack; - printk(" [<%08lx>]", addr); - if (++i > 40) { - printk(" ..."); - break; - } - } - } + show_trace(current, &stack); } void show_code(unsigned int *pc) @@ -177,43 +145,114 @@ void show_code(unsigned int *pc) printk("\nCode:"); for(i = -3 ; i < 6 ; i++) { - unsigned long insn; + unsigned int insn; if (__get_user(insn, pc + i)) { printk(" (Bad address in epc)\n"); break; } - printk("%c%08lx%c",(i?' ':'<'),insn,(i?' ':'>')); + printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); } } -spinlock_t die_lock; +void show_regs(struct pt_regs *regs) +{ + const int field = 2 * sizeof(unsigned long); + int i; + + printk("Cpu %d\n", smp_processor_id()); + + /* + * Saved main processor registers + */ + for (i = 0; i < 32; i++) { + if ((i % 4) == 0) + printk("$%2d :", i); + if (i == 0) + printk(" %0*lx", field, 0UL); + else if (i == 26 || i == 27) + printk(" %*s", field, ""); + else + printk(" %0*lx", field, regs->regs[i]); -extern void __die(const char * str, struct pt_regs * regs, const char *where, - unsigned long line) + i++; + if ((i % 4) == 0) + printk("\n"); + } + + printk("Hi : %0*lx\n", field, regs->hi); + printk("Lo : %0*lx\n", field, regs->lo); + + /* + * Saved cp0 registers + */ + printk("epc : %0*lx %s\n", field, regs->cp0_epc, print_tainted()); + printk("Status: %0*lx\n", field, regs->cp0_status); + printk("Cause : %0*lx\n", field, regs->cp0_cause); + + if (regs->cp0_status & ST0_KX) + printk("KX "); + if (regs->cp0_status & ST0_SX) + printk("SX "); + if (regs->cp0_status & ST0_UX) + printk("UX "); + switch (regs->cp0_status & ST0_KSU) { + case KSU_USER: + printk("USER "); + break; + case KSU_SUPERVISOR: + printk("SUPERVISOR "); + break; + case KSU_KERNEL: + printk("KERNEL "); + break; + default: + printk("BAD_MODE "); + break; + } + if (regs->cp0_status & ST0_ERL) + printk("ERL "); + if (regs->cp0_status & ST0_EXL) + printk("EXL "); + if (regs->cp0_status & ST0_IE) + printk("IE "); +} + +void show_registers(struct pt_regs *regs) +{ + const int field = 2 * sizeof(unsigned long); + + show_regs(regs); + printk("Process %s (pid: %d, stackpage=%0*lx)\n", + current->comm, current->pid, field, (unsigned long) current); + show_stack(current, (long *) regs->regs[29]); + show_trace(current, (long *) regs->regs[29]); + show_code((unsigned int *) regs->cp0_epc); + printk("\n"); +} + +static spinlock_t die_lock = SPIN_LOCK_UNLOCKED; + +void __die(const char * str, struct pt_regs * regs, const char * file, + const char * func, unsigned long line) { static int die_counter; + console_verbose(); spin_lock_irq(&die_lock); printk("%s", str); - if (where) - printk(" in %s, line %ld", where, line); + if (file && func) + printk(" in %s:%s, line %ld", file, func, line); printk("[#%d]:\n", ++die_counter); - show_regs(regs); - printk("Process %s (pid: %d, stackpage=%08lx)\n", - current->comm, current->pid, (unsigned long) current); - show_stack((unsigned int *) regs->regs[29]); - show_trace((unsigned int *) regs->regs[29]); - show_code((unsigned int *) regs->cp0_epc); - printk("\n"); + show_registers(regs); spin_unlock_irq(&die_lock); do_exit(SIGSEGV); } -void __die_if_kernel(const char * str, struct pt_regs * regs, const char *where, - unsigned long line) +void __die_if_kernel(const char * str, struct pt_regs * regs, + const char * file, const char * func, unsigned long line) { if (!user_mode(regs)) - __die(str, regs, where, line); + __die(str, regs, file, func, line); } extern const struct exception_table_entry __start___dbe_table[]; @@ -227,106 +266,199 @@ void __declare_dbe_table(void) ); } -static inline unsigned long -search_one_table(const struct exception_table_entry *first, - const struct exception_table_entry *last, - unsigned long value) -{ - const struct exception_table_entry *mid; - long diff; - - while (first < last) { - mid = (last - first) / 2 + first; - diff = mid->insn - value; - if (diff < 0) - first = mid + 1; - else - last = mid; - } - return (first == last && first->insn == value) ? first->nextinsn : 0; -} +asmlinkage void do_be(struct pt_regs *regs) +{ + const int field = 2 * sizeof(unsigned long); + const struct exception_table_entry *fixup = NULL; + int data = regs->cp0_cause & 4; + int action = MIPS_BE_FATAL; -extern spinlock_t modlist_lock; + /* XXX For now. Fixme, this searches the wrong table ... */ + if (data && !user_mode(regs)) + fixup = search_exception_tables(regs->cp0_epc); -static inline unsigned long -search_dbe_table(unsigned long addr) -{ - unsigned long ret = 0; - -#ifndef CONFIG_MODULES - /* There is only the kernel to search. */ - ret = search_one_table(__start___dbe_table, __stop___dbe_table-1, addr); - return ret; -#else - unsigned long flags; - - /* The kernel is the last "module" -- no need to treat it special. */ - struct module *mp; - struct archdata *ap; - - spin_lock_irqsave(&modlist_lock, flags); - for (mp = module_list; mp != NULL; mp = mp->next) { - if (!mod_member_present(mp, archdata_end) || - !mod_archdata_member_present(mp, struct archdata, - dbe_table_end)) - continue; - ap = (struct archdata *)(mp->archdata_start); - - if (ap->dbe_table_start == NULL || - !(mp->flags & (MOD_RUNNING | MOD_INITIALIZING))) - continue; - ret = search_one_table(ap->dbe_table_start, - ap->dbe_table_end - 1, addr); - if (ret) - break; - } - spin_unlock_irqrestore(&modlist_lock, flags); - return ret; -#endif -} + if (fixup) + action = MIPS_BE_FIXUP; -static void default_be_board_handler(struct pt_regs *regs) -{ - unsigned long new_epc; - unsigned long fixup; - int data = regs->cp0_cause & 4; + if (board_be_handler) + action = board_be_handler(regs, fixup != 0); - if (data && !user_mode(regs)) { - fixup = search_dbe_table(regs->cp0_epc); + switch (action) { + case MIPS_BE_DISCARD: + return; + case MIPS_BE_FIXUP: if (fixup) { - new_epc = fixup_exception(dpf_reg, fixup, - regs->cp0_epc); - regs->cp0_epc = new_epc; + regs->cp0_epc = fixup->nextinsn; return; } + break; + default: + break; } /* * Assume it would be too dangerous to continue ... */ - printk(KERN_ALERT "%s bus error, epc == %08lx, ra == %08lx\n", + printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", data ? "Data" : "Instruction", - regs->cp0_epc, regs->regs[31]); + field, regs->cp0_epc, field, regs->regs[31]); die_if_kernel("Oops", regs); force_sig(SIGBUS, current); } -asmlinkage void do_ibe(struct pt_regs *regs) +static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode) { - ibe_board_handler(regs); + unsigned int *epc; + + epc = (unsigned int *) regs->cp0_epc + + ((regs->cp0_cause & CAUSEF_BD) != 0); + if (!get_user(*opcode, epc)) + return 0; + + force_sig(SIGSEGV, current); + return 1; } -asmlinkage void do_dbe(struct pt_regs *regs) +/* + * ll/sc emulation + */ + +#define OPCODE 0xfc000000 +#define BASE 0x03e00000 +#define RT 0x001f0000 +#define OFFSET 0x0000ffff +#define LL 0xc0000000 +#define SC 0xe0000000 + +/* + * The ll_bit is cleared by r*_switch.S + */ + +unsigned long ll_bit; + +static struct task_struct *ll_task = NULL; + +static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) { - dbe_board_handler(regs); + unsigned long value, *vaddr; + long offset; + int signal = 0; + + /* + * analyse the ll instruction that just caused a ri exception + * and put the referenced address to addr. + */ + + /* sign extend offset */ + offset = opcode & OFFSET; + offset <<= 16; + offset >>= 16; + + vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset); + + if ((unsigned long)vaddr & 3) { + signal = SIGBUS; + goto sig; + } + if (get_user(value, vaddr)) { + signal = SIGSEGV; + goto sig; + } + + if (ll_task == NULL || ll_task == current) { + ll_bit = 1; + } else { + ll_bit = 0; + } + ll_task = current; + + regs->regs[(opcode & RT) >> 16] = value; + + compute_return_epc(regs); + return; + +sig: + force_sig(signal, current); } -asmlinkage void do_ov(struct pt_regs *regs) +static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) { - if (compute_return_epc(regs)) + unsigned long *vaddr, reg; + long offset; + int signal = 0; + + /* + * analyse the sc instruction that just caused a ri exception + * and put the referenced address to addr. + */ + + /* sign extend offset */ + offset = opcode & OFFSET; + offset <<= 16; + offset >>= 16; + + vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset); + reg = (opcode & RT) >> 16; + + if ((unsigned long)vaddr & 3) { + signal = SIGBUS; + goto sig; + } + if (ll_bit == 0 || ll_task != current) { + regs->regs[reg] = 0; + compute_return_epc(regs); return; + } - force_sig(SIGFPE, current); + if (put_user(regs->regs[reg], vaddr)) { + signal = SIGSEGV; + goto sig; + } + + regs->regs[reg] = 1; + + compute_return_epc(regs); + return; + +sig: + force_sig(signal, current); +} + +/* + * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both + * opcodes are supposed to result in coprocessor unusable exceptions if + * executed on ll/sc-less processors. That's the theory. In practice a + * few processors such as NEC's VR4100 throw reserved instruction exceptions + * instead, so we're doing the emulation thing in both exception handlers. + */ +static inline int simulate_llsc(struct pt_regs *regs) +{ + unsigned int opcode; + + if (unlikely(get_insn_opcode(regs, &opcode))) + return -EFAULT; + + if ((opcode & OPCODE) == LL) { + simulate_ll(regs, opcode); + return 0; + } + if ((opcode & OPCODE) == SC) { + simulate_sc(regs, opcode); + return 0; + } + + return -EFAULT; /* Strange things going on ... */ +} + +asmlinkage void do_ov(struct pt_regs *regs) +{ + siginfo_t info; + + info.si_code = FPE_INTOVF; + info.si_signo = SIGFPE; + info.si_errno = 0; + info.si_addr = (void *)regs->cp0_epc; + force_sig_info(SIGFPE, &info, current); } /* @@ -335,30 +467,29 @@ asmlinkage void do_ov(struct pt_regs *re asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) { if (fcr31 & FPU_CSR_UNI_X) { - extern void save_fp(struct task_struct *); - extern void restore_fp(struct task_struct *); int sig; + /* - * Unimplemented operation exception. If we've got the - * full software emulator on-board, let's use it... + * Unimplemented operation exception. If we've got the full + * software emulator on-board, let's use it... * - * Force FPU to dump state into task/thread context. - * We're moving a lot of data here for what is probably - * a single instruction, but the alternative is to - * pre-decode the FP register operands before invoking - * the emulator, which seems a bit extreme for what - * should be an infrequent event. + * Force FPU to dump state into task/thread context. We're + * moving a lot of data here for what is probably a single + * instruction, but the alternative is to pre-decode the FP + * register operands before invoking the emulator, which seems + * a bit extreme for what should be an infrequent event. */ save_fp(current); - + /* Run the emulator */ - sig = fpu_emulator_cop1Handler(regs); + sig = fpu_emulator_cop1Handler (0, regs, + ¤t->thread.fpu.soft); - /* - * We can't allow the emulated instruction to leave the - * Unimplemented Operation bit set in $fcr31. + /* + * We can't allow the emulated instruction to leave any of + * the cause bit set in $fcr31. */ - current->thread.fpu.soft.sr &= ~FPU_CSR_UNI_X; + current->thread.fpu.soft.sr &= ~FPU_CSR_ALL_X; /* Restore the hardware register state */ restore_fp(current); @@ -370,36 +501,18 @@ asmlinkage void do_fpe(struct pt_regs *r return; } - if (compute_return_epc(regs)) - return; - force_sig(SIGFPE, current); - printk(KERN_DEBUG "Sent send SIGFPE to %s\n", current->comm); -} - -static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode) -{ - unsigned int *epc; - - epc = (unsigned int *) regs->cp0_epc + - ((regs->cp0_cause & CAUSEF_BD) != 0); - if (!get_user(*opcode, epc)) - return 0; - - force_sig(SIGSEGV, current); - return 1; } asmlinkage void do_bp(struct pt_regs *regs) { - siginfo_t info; unsigned int opcode, bcode; - unsigned int *epc; + siginfo_t info; - epc = (unsigned int *) regs->cp0_epc + - ((regs->cp0_cause & CAUSEF_BD) != 0); - if (get_user(opcode, epc)) - goto sigsegv; + die_if_kernel("Break instruction in kernel code", regs); + + if (get_insn_opcode(regs, &opcode)) + return; /* * There is the ancient bug in the MIPS assemblers that the break @@ -423,241 +536,107 @@ asmlinkage void do_bp(struct pt_regs *re info.si_code = FPE_INTOVF; info.si_signo = SIGFPE; info.si_errno = 0; - info.si_addr = (void *)compute_return_epc(regs); + info.si_addr = (void *)regs->cp0_epc; force_sig_info(SIGFPE, &info, current); break; default: force_sig(SIGTRAP, current); } - return; - -sigsegv: - force_sig(SIGSEGV, current); } asmlinkage void do_tr(struct pt_regs *regs) { + unsigned int opcode, tcode = 0; siginfo_t info; - unsigned int opcode, bcode; - unsigned *epc; - epc = (unsigned int *) regs->cp0_epc + - ((regs->cp0_cause & CAUSEF_BD) != 0); - if (get_user(opcode, epc)) - goto sigsegv; + die_if_kernel("Trap instruction in kernel code", regs); + + if (get_insn_opcode(regs, &opcode)) + return; - bcode = ((opcode >> 6) & ((1 << 20) - 1)); + /* Immediate versions don't provide a code. */ + if (!(opcode & OPCODE)) + tcode = ((opcode >> 6) & ((1 << 20) - 1)); /* - * (A short test says that IRIX 5.3 sends SIGTRAP for all break - * insns, even for break codes that indicate arithmetic failures. + * (A short test says that IRIX 5.3 sends SIGTRAP for all trap + * insns, even for trap codes that indicate arithmetic failures. * Weird ...) * But should we continue the brokenness??? --macro */ - switch (bcode) { + switch (tcode) { case 6: case 7: - if (bcode == 7) + if (tcode == 7) info.si_code = FPE_INTDIV; else info.si_code = FPE_INTOVF; info.si_signo = SIGFPE; info.si_errno = 0; - info.si_addr = (void *)compute_return_epc(regs); + info.si_addr = (void *)regs->cp0_epc; force_sig_info(SIGFPE, &info, current); break; default: force_sig(SIGTRAP, current); } - return; - -sigsegv: - force_sig(SIGSEGV, current); } -#ifndef CONFIG_CPU_HAS_LLSC - -#ifdef CONFIG_SMP -#error "ll/sc emulation is not SMP safe" -#endif - -/* - * userland emulation for R2300 CPUs - * needed for the multithreading part of glibc - * - * this implementation can handle only sychronization between 2 or more - * user contexts and is not SMP safe. - */ asmlinkage void do_ri(struct pt_regs *regs) { - unsigned int opcode; - - if (!user_mode(regs)) - BUG(); + die_if_kernel("Reserved instruction in kernel code", regs); - if (!get_insn_opcode(regs, &opcode)) { - if ((opcode & OPCODE) == LL) { - simulate_ll(regs, opcode); - return; - } - if ((opcode & OPCODE) == SC) { - simulate_sc(regs, opcode); + if (!cpu_has_llsc) + if (!simulate_llsc(regs)) return; - } - } - if (compute_return_epc(regs)) - return; force_sig(SIGILL, current); } -/* - * The ll_bit is cleared by r*_switch.S - */ - -unsigned long ll_bit; -#ifdef CONFIG_PROC_FS -extern unsigned long ll_ops; -extern unsigned long sc_ops; -#endif - -static struct task_struct *ll_task = NULL; - -void simulate_ll(struct pt_regs *regp, unsigned int opcode) +asmlinkage void do_cpu(struct pt_regs *regs) { - unsigned long value, *vaddr; - long offset; - int signal = 0; + unsigned int cpid; - /* - * analyse the ll instruction that just caused a ri exception - * and put the referenced address to addr. - */ + die_if_kernel("do_cpu invoked from kernel context!", regs); - /* sign extend offset */ - offset = opcode & OFFSET; - offset <<= 16; - offset >>= 16; + cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; - vaddr = (unsigned long *)((long)(regp->regs[(opcode & BASE) >> 21]) + offset); + switch (cpid) { + case 0: + if (cpu_has_llsc) + break; -#ifdef CONFIG_PROC_FS - ll_ops++; -#endif + if (!simulate_llsc(regs)) + return; + break; - if ((unsigned long)vaddr & 3) - signal = SIGBUS; - else if (get_user(value, vaddr)) - signal = SIGSEGV; - else { - if (ll_task == NULL || ll_task == current) { - ll_bit = 1; - } else { - ll_bit = 0; + case 1: + own_fpu(); + if (current->used_math) { /* Using the FPU again. */ + restore_fp(current); + } else { /* First time FPU user. */ + init_fpu(); + current->used_math = 1; } - ll_task = current; - regp->regs[(opcode & RT) >> 16] = value; - } - if (compute_return_epc(regp)) - return; - if (signal) - send_sig(signal, current, 1); -} - -void simulate_sc(struct pt_regs *regp, unsigned int opcode) -{ - unsigned long *vaddr, reg; - long offset; - int signal = 0; - - /* - * analyse the sc instruction that just caused a ri exception - * and put the referenced address to addr. - */ - - /* sign extend offset */ - offset = opcode & OFFSET; - offset <<= 16; - offset >>= 16; - - vaddr = (unsigned long *)((long)(regp->regs[(opcode & BASE) >> 21]) + offset); - reg = (opcode & RT) >> 16; -#ifdef CONFIG_PROC_FS - sc_ops++; -#endif + if (!cpu_has_fpu) { + int sig = fpu_emulator_cop1Handler(0, regs, + ¤t->thread.fpu.soft); + if (sig) + force_sig(sig, current); + } - if ((unsigned long)vaddr & 3) - signal = SIGBUS; - else if (ll_bit == 0 || ll_task != current) - regp->regs[reg] = 0; - else if (put_user(regp->regs[reg], vaddr)) - signal = SIGSEGV; - else - regp->regs[reg] = 1; - if (compute_return_epc(regp)) return; - if (signal) - send_sig(signal, current, 1); -} -#else /* MIPS 2 or higher */ - -asmlinkage void do_ri(struct pt_regs *regs) -{ - unsigned int opcode; - - get_insn_opcode(regs, &opcode); - if (compute_return_epc(regs)) - return; + case 2: + case 3: + break; + } force_sig(SIGILL, current); } -#endif - -asmlinkage void do_cpu(struct pt_regs *regs) +asmlinkage void do_mdmx(struct pt_regs *regs) { - unsigned int cpid; - extern void lazy_fpu_switch(void *); - extern void init_fpu(void); - void fpu_emulator_init_fpu(void); - int sig; - - cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; - if (cpid != 1) - goto bad_cid; - - if (!(mips_cpu.options & MIPS_CPU_FPU)) - goto fp_emul; - - regs->cp0_status |= ST0_CU1; - if (last_task_used_math == current) - return; - - if (current->used_math) { /* Using the FPU again. */ - lazy_fpu_switch(last_task_used_math); - } else { /* First time FPU user. */ - init_fpu(); - current->used_math = 1; - } - last_task_used_math = current; - return; - -fp_emul: - if (last_task_used_math != current) { - if (!current->used_math) { - fpu_emulator_init_fpu(); - current->used_math = 1; - } - } - sig = fpu_emulator_cop1Handler(regs); - last_task_used_math = current; - if (sig) - force_sig(sig, current); - return; - -bad_cid: force_sig(SIGILL, current); } @@ -667,6 +646,7 @@ asmlinkage void do_watch(struct pt_regs * We use the watch exception where available to detect stack * overflows. */ + dump_tlb_all(); show_regs(regs); panic("Caught WATCH exception - probably caused by stack overflow."); } @@ -674,8 +654,14 @@ asmlinkage void do_watch(struct pt_regs asmlinkage void do_mcheck(struct pt_regs *regs) { show_regs(regs); - panic("Caught Machine Check exception - probably caused by multiple " - "matching entries in the TLB."); + dump_tlb_all(); + /* + * Some chips may have other causes of machine check (e.g. SB1 + * graduation timer) + */ + panic("Caught Machine Check exception - %scaused by multiple " + "matching entries in the TLB.", + (regs->cp0_status & ST0_TS) ? "" : "not "); } asmlinkage void do_reserved(struct pt_regs *regs) @@ -686,15 +672,8 @@ asmlinkage void do_reserved(struct pt_re * hard/software error. */ show_regs(regs); - panic("Caught reserved exception - should not happen."); -} - -static inline void watch_init(void) -{ - if (mips_cpu.options & MIPS_CPU_WATCH ) { - set_except_vector(23, handle_watch); - watch_available = 1; - } + panic("Caught reserved exception %ld - should not happen.", + (regs->cp0_cause & 0x7f) >> 2); } /* @@ -703,14 +682,12 @@ static inline void watch_init(void) */ static inline void parity_protection_init(void) { - switch (mips_cpu.cputype) { + switch (current_cpu_data.cputype) { case CPU_5KC: - /* Set the PE bit (bit 31) in the CP0_ECC register. */ + /* Set the PE bit (bit 31) in the c0_ecc register. */ printk(KERN_INFO "Enable the cache parity protection for " "MIPS 5KC CPUs.\n"); - write_32bit_cp0_register(CP0_ECC, - read_32bit_cp0_register(CP0_ECC) - | 0x80000000); + write_c0_ecc(read_c0_ecc() | 0x80000000); break; default: break; @@ -719,16 +696,16 @@ static inline void parity_protection_ini asmlinkage void cache_parity_error(void) { + const int field = 2 * sizeof(unsigned long); unsigned int reg_val; /* For the moment, report the problem and hang. */ - reg_val = read_32bit_cp0_register(CP0_ERROREPC); printk("Cache error exception:\n"); - printk("cp0_errorepc == %08x\n", reg_val); - reg_val = read_32bit_cp0_register(CP0_CACHEERR); - printk("cp0_cacheerr == %08x\n", reg_val); + printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); + reg_val = read_c0_cacheerr(); + printk("c0_cacheerr == %08x\n", reg_val); - printk("Decoded CP0_CACHEERR: %s cache fault in %s reference.\n", + printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", reg_val & (1<<30) ? "secondary" : "primary", reg_val & (1<<31) ? "data" : "insn"); printk("Error bits: %s%s%s%s%s%s%s\n", @@ -741,17 +718,63 @@ asmlinkage void cache_parity_error(void) reg_val & (1<<22) ? "E0 " : ""); printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); - if (reg_val&(1<<22)) - printk("DErrAddr0: 0x%08x\n", - read_32bit_cp0_set1_register(CP0_S1_DERRADDR0)); - - if (reg_val&(1<<23)) - printk("DErrAddr1: 0x%08x\n", - read_32bit_cp0_set1_register(CP0_S1_DERRADDR1)); +#if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64) + if (reg_val & (1<<22)) + printk("DErrAddr0: 0x%08x\n", read_c0_derraddr0()); + + if (reg_val & (1<<23)) + printk("DErrAddr1: 0x%08x\n", read_c0_derraddr1()); +#endif panic("Can't handle the cache error!"); } +/* + * SDBBP EJTAG debug exception handler. + * We skip the instruction and return to the next instruction. + */ +void ejtag_exception_handler(struct pt_regs *regs) +{ + const int field = 2 * sizeof(unsigned long); + unsigned long depc, old_epc; + unsigned int debug; + + printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); + depc = read_c0_depc(); + debug = read_c0_debug(); + printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); + if (debug & 0x80000000) { + /* + * In branch delay slot. + * We cheat a little bit here and use EPC to calculate the + * debug return address (DEPC). EPC is restored after the + * calculation. + */ + old_epc = regs->cp0_epc; + regs->cp0_epc = depc; + __compute_return_epc(regs); + depc = regs->cp0_epc; + regs->cp0_epc = old_epc; + } else + depc += 4; + write_c0_depc(depc); + +#if 0 + printk("\n\n----- Enable EJTAG single stepping ----\n\n"); + write_c0_debug(debug | 0x100); +#endif +} + +/* + * NMI exception handler. + */ +void nmi_exception_handler(struct pt_regs *regs) +{ + printk("NMI taken!!!!\n"); + die("NMI", regs); + while(1) ; +} + unsigned long exception_handlers[32]; /* @@ -761,11 +784,11 @@ unsigned long exception_handlers[32]; */ void *set_except_vector(int n, void *addr) { - unsigned handler = (unsigned long) addr; - unsigned old_handler = exception_handlers[n]; - exception_handlers[n] = handler; + unsigned long handler = (unsigned long) addr; + unsigned long old_handler = exception_handlers[n]; - if (n == 0 && mips_cpu.options & MIPS_CPU_DIVEC) { + exception_handlers[n] = handler; + if (n == 0 && cpu_has_divec) { *(volatile u32 *)(KSEG0+0x200) = 0x08000000 | (0x03ffffff & (handler >> 2)); flush_icache_range(KSEG0+0x200, KSEG0 + 0x204); @@ -775,56 +798,70 @@ void *set_except_vector(int n, void *add asmlinkage int (*save_fp_context)(struct sigcontext *sc); asmlinkage int (*restore_fp_context)(struct sigcontext *sc); + extern asmlinkage int _save_fp_context(struct sigcontext *sc); extern asmlinkage int _restore_fp_context(struct sigcontext *sc); extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc); extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc); +void __init per_cpu_trap_init(void) +{ + unsigned int cpu = smp_processor_id(); + + /* Some firmware leaves the BEV flag set, clear it. */ + clear_c0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_BEV); + + /* + * Some MIPS CPUs have a dedicated interrupt vector which reduces the + * interrupt processing overhead. Use it where available. + */ + if (cpu_has_divec) + set_c0_cause(CAUSEF_IV); + + cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; + write_c0_context(cpu << 23); +} + void __init trap_init(void) { - extern char except_vec0_nevada, except_vec0_r4000; - extern char except_vec0_r4600, except_vec0_r2300; - extern char except_vec1_generic, except_vec2_generic; + extern char except_vec1_generic; extern char except_vec3_generic, except_vec3_r4000; - extern char except_vec4; extern char except_vec_ejtag_debug; + extern char except_vec4; unsigned long i; - /* Some firmware leaves the BEV flag set, clear it. */ - clear_cp0_status(ST0_BEV); + per_cpu_trap_init(); /* Copy the generic exception handler code to its final destination. */ memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80); - memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80); - memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80); - flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200); + /* * Setup default vectors */ for (i = 0; i <= 31; i++) set_except_vector(i, handle_reserved); - /* - * Copy the EJTAG debug exception vector handler code to its final + /* + * Copy the EJTAG debug exception vector handler code to it's final * destination. */ - memcpy((void *)(KSEG0 + 0x300), &except_vec_ejtag_debug, 0x80); + if (cpu_has_ejtag) + memcpy((void *)(KSEG0 + 0x300), &except_vec_ejtag_debug, 0x80); /* * Only some CPUs have the watch exceptions or a dedicated * interrupt vector. */ - watch_init(); + if (cpu_has_watch) + set_except_vector(23, handle_watch); /* * Some MIPS CPUs have a dedicated interrupt vector which reduces the * interrupt processing overhead. Use it where available. */ - if (mips_cpu.options & MIPS_CPU_DIVEC) { - memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8); - set_cp0_cause(CAUSEF_IV); - } + if (cpu_has_divec) + memcpy((void *)(KSEG0 + 0x200), &except_vec4, 0x8); /* * Some CPUs can enable/disable for cache parity detection, but does @@ -832,21 +869,22 @@ void __init trap_init(void) */ parity_protection_init(); + /* + * The Data Bus Errors / Instruction Bus Errors are signaled + * by external hardware. Therefore these two exceptions + * may have board specific handlers. + */ + if (board_be_init) + board_be_init(); + set_except_vector(1, handle_mod); set_except_vector(2, handle_tlbl); set_except_vector(3, handle_tlbs); set_except_vector(4, handle_adel); set_except_vector(5, handle_ades); - /* - * The Data Bus Error/ Instruction Bus Errors are signaled - * by external hardware. Therefore these two expection have - * board specific handlers. - */ set_except_vector(6, handle_ibe); set_except_vector(7, handle_dbe); - ibe_board_handler = default_be_board_handler; - dbe_board_handler = default_be_board_handler; set_except_vector(8, handle_sys); set_except_vector(9, handle_bp); @@ -854,59 +892,23 @@ void __init trap_init(void) set_except_vector(11, handle_cpu); set_except_vector(12, handle_ov); set_except_vector(13, handle_tr); + set_except_vector(22, handle_mdmx); - if (mips_cpu.options & MIPS_CPU_FPU) + if (cpu_has_fpu && !cpu_has_nofpuex) set_except_vector(15, handle_fpe); - /* - * Handling the following exceptions depends mostly of the cpu type - */ - if ((mips_cpu.options & MIPS_CPU_4KEX) - && (mips_cpu.options & MIPS_CPU_4KTLB)) { - if (mips_cpu.cputype == CPU_NEVADA) { - memcpy((void *)KSEG0, &except_vec0_nevada, 0x80); - } else if (mips_cpu.cputype == CPU_R4600) - memcpy((void *)KSEG0, &except_vec0_r4600, 0x80); - else - memcpy((void *)KSEG0, &except_vec0_r4000, 0x80); - - /* Cache error vector already set above. */ - - if (mips_cpu.options & MIPS_CPU_VCE) { - memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, - 0x80); - } else { - memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, - 0x80); - } + if (cpu_has_mcheck) + set_except_vector(24, handle_mcheck); - if (mips_cpu.options & MIPS_CPU_FPU) { - save_fp_context = _save_fp_context; - restore_fp_context = _restore_fp_context; - } else { - save_fp_context = fpu_emulator_save_context; - restore_fp_context = fpu_emulator_restore_context; - } - } else switch (mips_cpu.cputype) { - case CPU_SB1: - /* - * XXX - This should be folded in to the "cleaner" handling, - * above - */ - memcpy((void *)KSEG0, &except_vec0_r4000, 0x80); + if (cpu_has_vce) memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80); - save_fp_context = _save_fp_context; - restore_fp_context = _restore_fp_context; + else if (cpu_has_4kex) + memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80); + else + memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80); - /* Enable timer interrupt and scd mapped interrupt */ - clear_cp0_status(0xf000); - set_cp0_status(0xc00); - break; - case CPU_R6000: - case CPU_R6000A: - save_fp_context = _save_fp_context; - restore_fp_context = _restore_fp_context; - + if (current_cpu_data.cputype == CPU_R6000 || + current_cpu_data.cputype == CPU_R6000A) { /* * The R6000 is the only R-series CPU that features a machine * check exception (similar to the R4000 cache error) and @@ -917,34 +919,24 @@ void __init trap_init(void) */ //set_except_vector(14, handle_mc); //set_except_vector(15, handle_ndc); - case CPU_R2000: - case CPU_R3000: - case CPU_R3000A: - case CPU_R3041: - case CPU_R3051: - case CPU_R3052: - case CPU_R3081: - case CPU_R3081E: - case CPU_TX3912: - case CPU_TX3922: - case CPU_TX3927: + } + + if (cpu_has_fpu) { save_fp_context = _save_fp_context; restore_fp_context = _restore_fp_context; - memcpy((void *)KSEG0, &except_vec0_r2300, 0x80); - memcpy((void *)(KSEG0 + 0x80), &except_vec3_generic, 0x80); - break; - - case CPU_UNKNOWN: - default: - panic("Unknown CPU type"); + } else { + save_fp_context = fpu_emulator_save_context; + restore_fp_context = fpu_emulator_restore_context; } - flush_icache_range(KSEG0, KSEG0 + 0x200); - if (mips_cpu.isa_level == MIPS_CPU_ISA_IV) - set_cp0_status(ST0_XX); + flush_icache_range(KSEG0, KSEG0 + 0x400); + + if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) + set_c0_status(ST0_XX); - atomic_inc(&init_mm.mm_count); /* XXX UP? */ + atomic_inc(&init_mm.mm_count); /* XXX UP? */ current->active_mm = &init_mm; - write_32bit_cp0_register(CP0_CONTEXT, smp_processor_id()<<23); - current_pgd[0] = init_mm.pgd; + + /* XXX Must be done for all CPUs */ + TLBMISS_HANDLER_SETUP(); } --- linux-2.5.73/arch/mips/kernel/unaligned.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/kernel/unaligned.c 2003-06-27 15:56:23.000000000 -0700 @@ -5,7 +5,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 1998 by Ralf Baechle + * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. * * This file contains exception handler for address error exception with the @@ -41,7 +41,7 @@ * * #include * #include - * + * * struct foo { * unsigned char bar[8]; * }; @@ -74,6 +74,7 @@ */ #include #include +#include #include #include #include @@ -88,23 +89,22 @@ #define STR(x) __STR(x) #define __STR(x) #x -/* - * User code may only access USEG; kernel code may access the - * entire address space. - */ -#define check_axs(pc,a,s) \ - if ((long)(~(pc) & ((a) | ((a)+(s)))) < 0) \ - goto sigbus; +#ifdef CONFIG_PROC_FS +unsigned long unaligned_instructions; +#endif -static inline void -emulate_load_store_insn(struct pt_regs *regs, - unsigned long addr, - unsigned long pc) +static inline int emulate_load_store_insn(struct pt_regs *regs, + void *addr, unsigned long pc, + unsigned long **regptr, unsigned long *newvalue) { union mips_instruction insn; - unsigned long value, fixup; + unsigned long value; + const struct exception_table_entry *fixup; + unsigned int res; regs->regs[0] = 0; + *regptr=NULL; + /* * This load never faults. */ @@ -144,186 +144,295 @@ emulate_load_store_insn(struct pt_regs * * The remaining opcodes are the ones that are really of interest. */ case lh_op: - check_axs(pc, addr, 2); - __asm__( - ".set\tnoat\n" + if (verify_area(VERIFY_READ, addr, 2)) + goto sigbus; + + __asm__ __volatile__ (".set\tnoat\n" #ifdef __BIG_ENDIAN - "1:\tlb\t%0,0(%1)\n" - "2:\tlbu\t$1,1(%1)\n\t" + "1:\tlb\t%0, 0(%2)\n" + "2:\tlbu\t$1, 1(%2)\n\t" #endif #ifdef __LITTLE_ENDIAN - "1:\tlb\t%0,1(%1)\n" - "2:\tlbu\t$1,0(%1)\n\t" + "1:\tlb\t%0, 1(%2)\n" + "2:\tlbu\t$1, 0(%2)\n\t" #endif - "sll\t%0,0x8\n\t" - "or\t%0,$1\n\t" - ".set\tat\n\t" + "sll\t%0, 0x8\n\t" + "or\t%0, $1\n\t" + "li\t%1, 0\n" + "3:\t.set\tat\n\t" + ".section\t.fixup,\"ax\"\n\t" + "4:\tli\t%1, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - :"=&r" (value) - :"r" (addr), "i" (&&fault) - :"$1"); - regs->regs[insn.i_format.rt] = value; - return; + : "=&r" (value), "=r" (res) + : "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + *newvalue = value; + *regptr = ®s->regs[insn.i_format.rt]; + break; case lw_op: - check_axs(pc, addr, 4); - __asm__( + if (verify_area(VERIFY_READ, addr, 4)) + goto sigbus; + + __asm__ __volatile__ ( #ifdef __BIG_ENDIAN - "1:\tlwl\t%0,(%1)\n" - "2:\tlwr\t%0,3(%1)\n\t" + "1:\tlwl\t%0, (%2)\n" + "2:\tlwr\t%0, 3(%2)\n\t" #endif #ifdef __LITTLE_ENDIAN - "1:\tlwl\t%0,3(%1)\n" - "2:\tlwr\t%0,(%1)\n\t" + "1:\tlwl\t%0, 3(%2)\n" + "2:\tlwr\t%0, (%2)\n\t" #endif + "li\t%1, 0\n" + "3:\t.section\t.fixup,\"ax\"\n\t" + "4:\tli\t%1, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - :"=&r" (value) - :"r" (addr), "i" (&&fault)); - regs->regs[insn.i_format.rt] = value; - return; + : "=&r" (value), "=r" (res) + : "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + *newvalue = value; + *regptr = ®s->regs[insn.i_format.rt]; + break; case lhu_op: - check_axs(pc, addr, 2); - __asm__( + if (verify_area(VERIFY_READ, addr, 2)) + goto sigbus; + + __asm__ __volatile__ ( ".set\tnoat\n" #ifdef __BIG_ENDIAN - "1:\tlbu\t%0,0(%1)\n" - "2:\tlbu\t$1,1(%1)\n\t" + "1:\tlbu\t%0, 0(%2)\n" + "2:\tlbu\t$1, 1(%2)\n\t" #endif #ifdef __LITTLE_ENDIAN - "1:\tlbu\t%0,1(%1)\n" - "2:\tlbu\t$1,0(%1)\n\t" + "1:\tlbu\t%0, 1(%2)\n" + "2:\tlbu\t$1, 0(%2)\n\t" #endif - "sll\t%0,0x8\n\t" - "or\t%0,$1\n\t" - ".set\tat\n\t" + "sll\t%0, 0x8\n\t" + "or\t%0, $1\n\t" + "li\t%1, 0\n" + "3:\t.set\tat\n\t" + ".section\t.fixup,\"ax\"\n\t" + "4:\tli\t%1, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - :"=&r" (value) - :"r" (addr), "i" (&&fault) - :"$1"); - regs->regs[insn.i_format.rt] = value; - return; + : "=&r" (value), "=r" (res) + : "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + *newvalue = value; + *regptr = ®s->regs[insn.i_format.rt]; + break; case lwu_op: - check_axs(pc, addr, 4); - __asm__( +#ifdef CONFIG_MIPS64 + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (verify_area(VERIFY_READ, addr, 4)) + goto sigbus; + + __asm__ __volatile__ ( #ifdef __BIG_ENDIAN - "1:\tlwl\t%0,(%1)\n" - "2:\tlwr\t%0,3(%1)\n\t" + "1:\tlwl\t%0, (%2)\n" + "2:\tlwr\t%0, 3(%2)\n\t" #endif #ifdef __LITTLE_ENDIAN - "1:\tlwl\t%0,3(%1)\n" - "2:\tlwr\t%0,(%1)\n\t" + "1:\tlwl\t%0, 3(%2)\n" + "2:\tlwr\t%0, (%2)\n\t" #endif + "dsll\t%0, %0, 32\n\t" + "dsrl\t%0, %0, 32\n\t" + "li\t%1, 0\n" + "3:\t.section\t.fixup,\"ax\"\n\t" + "4:\tli\t%1, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - :"=&r" (value) - :"r" (addr), "i" (&&fault)); - value &= 0xffffffff; - regs->regs[insn.i_format.rt] = value; - return; + : "=&r" (value), "=r" (res) + : "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + *newvalue = value; + *regptr = ®s->regs[insn.i_format.rt]; + break; +#endif /* CONFIG_MIPS64 */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; case ld_op: - check_axs(pc, addr, 8); - __asm__( - ".set\tmips3\n" +#ifdef CONFIG_MIPS64 + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (verify_area(VERIFY_READ, addr, 8)) + goto sigbus; + + __asm__ __volatile__ ( #ifdef __BIG_ENDIAN - "1:\tldl\t%0,(%1)\n" - "2:\tldr\t%0,7(%1)\n\t" + "1:\tldl\t%0, (%2)\n" + "2:\tldr\t%0, 7(%2)\n\t" #endif #ifdef __LITTLE_ENDIAN - "1:\tldl\t%0,7(%1)\n" - "2:\tldr\t%0,(%1)\n\t" + "1:\tldl\t%0, 7(%2)\n" + "2:\tldr\t%0, (%2)\n\t" #endif - ".set\tmips0\n\t" + "li\t%1, 0\n" + "3:\t.section\t.fixup,\"ax\"\n\t" + "4:\tli\t%1, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - :"=&r" (value) - :"r" (addr), "i" (&&fault)); - regs->regs[insn.i_format.rt] = value; - return; + : "=&r" (value), "=r" (res) + : "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + *newvalue = value; + *regptr = ®s->regs[insn.i_format.rt]; + break; +#endif /* CONFIG_MIPS64 */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; case sh_op: - check_axs(pc, addr, 2); + if (verify_area(VERIFY_WRITE, addr, 2)) + goto sigbus; + value = regs->regs[insn.i_format.rt]; - __asm__( + __asm__ __volatile__ ( #ifdef __BIG_ENDIAN ".set\tnoat\n" - "1:\tsb\t%0,1(%1)\n\t" - "srl\t$1,%0,0x8\n" - "2:\tsb\t$1,0(%1)\n\t" + "1:\tsb\t%1, 1(%2)\n\t" + "srl\t$1, %1, 0x8\n" + "2:\tsb\t$1, 0(%2)\n\t" ".set\tat\n\t" #endif #ifdef __LITTLE_ENDIAN ".set\tnoat\n" - "1:\tsb\t%0,0(%1)\n\t" - "srl\t$1,%0,0x8\n" - "2:\tsb\t$1,1(%1)\n\t" + "1:\tsb\t%1, 0(%2)\n\t" + "srl\t$1,%1, 0x8\n" + "2:\tsb\t$1, 1(%2)\n\t" ".set\tat\n\t" #endif + "li\t%0, 0\n" + "3:\n\t" + ".section\t.fixup,\"ax\"\n\t" + "4:\tli\t%0, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - : /* no outputs */ - :"r" (value), "r" (addr), "i" (&&fault) - :"$1"); - return; + : "=r" (res) + : "r" (value), "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + break; case sw_op: - check_axs(pc, addr, 4); + if (verify_area(VERIFY_WRITE, addr, 4)) + goto sigbus; + value = regs->regs[insn.i_format.rt]; - __asm__( + __asm__ __volatile__ ( #ifdef __BIG_ENDIAN - "1:\tswl\t%0,(%1)\n" - "2:\tswr\t%0,3(%1)\n\t" + "1:\tswl\t%1,(%2)\n" + "2:\tswr\t%1, 3(%2)\n\t" #endif #ifdef __LITTLE_ENDIAN - "1:\tswl\t%0,3(%1)\n" - "2:\tswr\t%0,(%1)\n\t" + "1:\tswl\t%1, 3(%2)\n" + "2:\tswr\t%1, (%2)\n\t" #endif + "li\t%0, 0\n" + "3:\n\t" + ".section\t.fixup,\"ax\"\n\t" + "4:\tli\t%0, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - : /* no outputs */ - :"r" (value), "r" (addr), "i" (&&fault)); - return; + : "=r" (res) + : "r" (value), "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + break; case sd_op: - check_axs(pc, addr, 8); +#ifdef CONFIG_MIPS64 + /* + * A 32-bit kernel might be running on a 64-bit processor. But + * if we're on a 32-bit processor and an i-cache incoherency + * or race makes us see a 64-bit instruction here the sdl/sdr + * would blow up, so for now we don't handle unaligned 64-bit + * instructions on 32-bit kernels. + */ + if (verify_area(VERIFY_WRITE, addr, 8)) + goto sigbus; + value = regs->regs[insn.i_format.rt]; - __asm__( - ".set\tmips3\n" + __asm__ __volatile__ ( #ifdef __BIG_ENDIAN - "1:\tsdl\t%0,(%1)\n" - "2:\tsdr\t%0,7(%1)\n\t" + "1:\tsdl\t%1,(%2)\n" + "2:\tsdr\t%1, 7(%2)\n\t" #endif #ifdef __LITTLE_ENDIAN - "1:\tsdl\t%0,7(%1)\n" - "2:\tsdr\t%0,(%1)\n\t" + "1:\tsdl\t%1, 7(%2)\n" + "2:\tsdr\t%1, (%2)\n\t" #endif - ".set\tmips0\n\t" + "li\t%0, 0\n" + "3:\n\t" + ".section\t.fixup,\"ax\"\n\t" + "4:\tli\t%0, %3\n\t" + "j\t3b\n\t" + ".previous\n\t" ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,%2\n\t" - STR(PTR)"\t2b,%2\n\t" + STR(PTR)"\t1b, 4b\n\t" + STR(PTR)"\t2b, 4b\n\t" ".previous" - : /* no outputs */ - :"r" (value), "r" (addr), "i" (&&fault)); - return; + : "=r" (res) + : "r" (value), "r" (addr), "i" (-EFAULT)); + if (res) + goto fault; + break; +#endif /* CONFIG_MIPS64 */ + + /* Cannot handle 64-bit instructions in 32-bit kernel */ + goto sigill; case lwc1_op: case ldc1_op: @@ -352,78 +461,97 @@ emulate_load_store_insn(struct pt_regs * */ goto sigill; } - return; + +#ifdef CONFIG_PROC_FS + unaligned_instructions++; +#endif + + return 0; fault: /* Did we have an exception handler installed? */ - fixup = search_exception_table(regs->cp0_epc); + fixup = search_exception_tables(exception_epc(regs)); if (fixup) { - long new_epc; - new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc); + unsigned long new_epc = fixup->nextinsn; printk(KERN_DEBUG "%s: Forwarding exception at [<%lx>] (%lx)\n", current->comm, regs->cp0_epc, new_epc); regs->cp0_epc = new_epc; - return; + return 1; } die_if_kernel ("Unhandled kernel unaligned access", regs); send_sig(SIGSEGV, current, 1); - return; + + return 0; + sigbus: - die_if_kernel ("Unhandled kernel unaligned access", regs); + die_if_kernel("Unhandled kernel unaligned access", regs); send_sig(SIGBUS, current, 1); - return; + + return 0; + sigill: - die_if_kernel ("Unhandled kernel unaligned access or invalid instruction", regs); + die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs); send_sig(SIGILL, current, 1); - return; -} -#ifdef CONFIG_PROC_FS -unsigned long unaligned_instructions; -#endif + return 0; +} asmlinkage void do_ade(struct pt_regs *regs) { - unsigned long pc; + unsigned long *regptr, newval; extern int do_dsemulret(struct pt_regs *); + mm_segment_t seg; + unsigned long pc; - /* - * Address errors may be deliberately induced - * by the FPU emulator to take retake control - * of the CPU after executing the instruction - * in the delay slot of an emulated branch. + /* + * Address errors may be deliberately induced by the FPU emulator to + * retake control of the CPU after executing the instruction in the + * delay slot of an emulated branch. */ - - if ((unsigned long)regs->cp0_epc == current->thread.dsemul_aerpc) { - do_dsemulret(regs); + /* Terminate if exception was recognized as a delay slot return */ + if (do_dsemulret(regs)) return; - } + + /* Otherwise handle as normal */ /* * Did we catch a fault trying to load an instruction? - * This also catches attempts to activate MIPS16 code on - * CPUs which don't support it. + * Or are we running in MIPS16 mode? */ - if (regs->cp0_badvaddr == regs->cp0_epc) + if ((regs->cp0_badvaddr == regs->cp0_epc) || (regs->cp0_epc & 0x1)) goto sigbus; - pc = regs->cp0_epc + ((regs->cp0_cause & CAUSEF_BD) ? 4 : 0); - if (compute_return_epc(regs)) - return; + pc = exception_epc(regs); if ((current->thread.mflags & MF_FIXADE) == 0) goto sigbus; - emulate_load_store_insn(regs, regs->cp0_badvaddr, pc); -#ifdef CONFIG_PROC_FS - unaligned_instructions++; -#endif + /* + * Do branch emulation only if we didn't forward the exception. + * This is all so but ugly ... + */ + seg = get_fs(); + if (!user_mode(regs)) + set_fs(KERNEL_DS); + if (!emulate_load_store_insn(regs, (void *)regs->cp0_badvaddr, pc, + ®ptr, &newval)) { + compute_return_epc(regs); + /* + * Now that branch is evaluated, update the dest + * register if necessary + */ + if (regptr) + *regptr = newval; + } + set_fs(seg); return; sigbus: - die_if_kernel ("Kernel unaligned instruction access", regs); + die_if_kernel("Kernel unaligned instruction access", regs); force_sig(SIGBUS, current); - return; + /* + * XXX On return from the signal handler we should advance the epc + */ } --- linux-2.5.73/arch/mips/kernel/vm86.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,13 +0,0 @@ -/* - * arch/mips/vm86.c - * - * Copyright (C) 1994 Waldorf GMBH, - * written by Ralf Baechle - */ -#include -#include - -asmlinkage int sys_vm86(void *v86) -{ - return -ENOSYS; -} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/at93c.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,148 @@ +/* + * Atmel AT93C46 serial eeprom driver + * + * Brian Murphy + * + */ +#include +#include +#include +#include +#include + +#include "at93c.h" + +#define AT93C_ADDR_SHIFT 7 +#define AT93C_ADDR_MAX ((1 << AT93C_ADDR_SHIFT) - 1) +#define AT93C_RCMD (0x6 << AT93C_ADDR_SHIFT) +#define AT93C_WCMD (0x5 << AT93C_ADDR_SHIFT) +#define AT93C_WENCMD 0x260 +#define AT93C_WDSCMD 0x200 + +struct at93c_defs *at93c; + +static void at93c_reg_write(u32 val) +{ + *at93c->reg = val; +} + +static u32 at93c_reg_read(void) +{ + u32 tmp = *at93c->reg; + return tmp; +} + +static u32 at93c_datareg_read(void) +{ + u32 tmp = *at93c->rdata_reg; + return tmp; +} + +static void at93c_cycle_clk(u32 data) +{ + at93c_reg_write(data | at93c->clk); + ndelay(250); + at93c_reg_write(data & ~at93c->clk); + ndelay(250); +} + +static void at93c_write_databit(u8 bit) +{ + u32 data = at93c_reg_read(); + if (bit) + data |= 1 << at93c->wdata_shift; + else + data &= ~(1 << at93c->wdata_shift); + + at93c_reg_write(data); + ndelay(100); + at93c_cycle_clk(data); +} + +static unsigned int at93c_read_databit(void) +{ + u32 data; + + at93c_cycle_clk(at93c_reg_read()); + data = (at93c_datareg_read() >> at93c->rdata_shift) & 1; + return data; +} + +static u8 at93c_read_byte(void) +{ + int i; + u8 data = 0; + + for (i = 0; i<=7; i++) { + data <<= 1; + data |= at93c_read_databit(); + } + return data; +} + +static void at93c_write_bits(u32 data, int size) +{ + int i; + int shift = size - 1; + u32 mask = (1 << shift); + + for (i = 0; i < size; i++) { + at93c_write_databit((data & mask) >> shift); + data <<= 1; + } +} + +static void at93c_init_op(void) +{ + at93c_reg_write((at93c_reg_read() | at93c->cs) & ~at93c->clk & ~(1 << at93c->rdata_shift)); + ndelay(50); +} + +static void at93c_end_op(void) +{ + at93c_reg_write(at93c_reg_read() & ~at93c->cs); + ndelay(250); +} + +static void at93c_wait(void) +{ + at93c_init_op(); + while (!at93c_read_databit()) + ; + at93c_end_op(); +}; + +static void at93c_disable_wp(void) +{ + at93c_init_op(); + at93c_write_bits(AT93C_WENCMD, 10); + at93c_end_op(); +} + +static void at93c_enable_wp(void) +{ + at93c_init_op(); + at93c_write_bits(AT93C_WDSCMD, 10); + at93c_end_op(); +} + +u8 at93c_read(u8 addr) +{ + u8 byte; + at93c_init_op(); + at93c_write_bits((addr & AT93C_ADDR_MAX)|AT93C_RCMD, 10); + byte = at93c_read_byte(); + at93c_end_op(); + return byte; +} + +void at93c_write(u8 addr, u8 data) +{ + at93c_disable_wp(); + at93c_init_op(); + at93c_write_bits((addr & AT93C_ADDR_MAX)|AT93C_WCMD, 10); + at93c_write_bits(data, 8); + at93c_end_op(); + at93c_wait(); + at93c_enable_wp(); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/at93c.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,18 @@ +/* + * Atmel AT93C46 serial eeprom driver + * + * Brian Murphy + * + */ + +extern struct at93c_defs { + volatile u32 *reg; + volatile u32 *rdata_reg; + int rdata_shift; + int wdata_shift; + u32 cs; + u32 clk; +} *at93c; + +u8 at93c_read(u8 addr); +void at93c_write(u8 addr, u8 data); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/ds1603.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,174 @@ +/* + * Dallas Semiconductors 1603 RTC driver + * + * Brian Murphy + * + */ +#include +#include +#include +#include + +#include "ds1603.h" + +#define READ_TIME_CMD 0x81 +#define SET_TIME_CMD 0x80 +#define TRIMMER_SET_CMD 0xC0 +#define TRIMMER_VALUE_MASK 0x38 +#define TRIMMER_SHIFT 3 + +struct ds_defs *ds1603 = NULL; + +/* HW specific register functions */ +static void rtc_reg_write(unsigned long val) +{ + *ds1603->reg = val; +} + +static unsigned long rtc_reg_read(void) +{ + unsigned long tmp = *ds1603->reg; + return tmp; +} + +static unsigned long rtc_datareg_read(void) +{ + unsigned long tmp = *ds1603->data_reg; + return tmp; +} + +static void rtc_nrst_high(void) +{ + rtc_reg_write(rtc_reg_read() | ds1603->rst); +} + +static void rtc_nrst_low(void) +{ + rtc_reg_write(rtc_reg_read() & ~ds1603->rst); +} + +static void rtc_cycle_clock(unsigned long data) +{ + data |= ds1603->clk; + rtc_reg_write(data); + ndelay(250); + if (ds1603->data_reversed) + data &= ~ds1603->data; + else + data |= ds1603->data; + data &= ~ds1603->clk; + rtc_reg_write(data); + ndelay(250 + ds1603->huge_delay); +} + +static void rtc_write_databit(unsigned int bit) +{ + unsigned long data = rtc_reg_read(); + if (ds1603->data_reversed) + bit = !bit; + if (bit) + data |= ds1603->data; + else + data &= ~ds1603->data; + + rtc_reg_write(data); + ndelay(50 + ds1603->huge_delay); + rtc_cycle_clock(data); +} + +static unsigned int rtc_read_databit(void) +{ + unsigned int data; + + data = (rtc_datareg_read() & (1 << ds1603->data_read_shift)) + >> ds1603->data_read_shift; + rtc_cycle_clock(rtc_reg_read()); + return data; +} + +static void rtc_write_byte(unsigned int byte) +{ + int i; + + for (i = 0; i<=7; i++) { + rtc_write_databit(byte & 1L); + byte >>= 1; + } +} + +static void rtc_write_word(unsigned long word) +{ + int i; + + for (i = 0; i<=31; i++) { + rtc_write_databit(word & 1L); + word >>= 1; + } +} + +static unsigned long rtc_read_word(void) +{ + int i; + unsigned long word = 0; + unsigned long shift = 0; + + for (i = 0; i<=31; i++) { + word |= rtc_read_databit() << shift; + shift++; + } + return word; +} + +static void rtc_init_op(void) +{ + rtc_nrst_high(); + + rtc_reg_write(rtc_reg_read() & ~ds1603->clk); + + ndelay(50); +} + +static void rtc_end_op(void) +{ + rtc_nrst_low(); + ndelay(1000); +} + +/* interface */ +unsigned long ds1603_read(void) +{ + unsigned long word; + rtc_init_op(); + rtc_write_byte(READ_TIME_CMD); + word = rtc_read_word(); + rtc_end_op(); + return word; +} + +int ds1603_set(unsigned long time) +{ + rtc_init_op(); + rtc_write_byte(SET_TIME_CMD); + rtc_write_word(time); + rtc_end_op(); + + return 0; +} + +void ds1603_set_trimmer(unsigned int trimval) +{ + rtc_init_op(); + rtc_write_byte(((trimval << TRIMMER_SHIFT) & TRIMMER_VALUE_MASK) + | (TRIMMER_SET_CMD)); + rtc_end_op(); +} + +void ds1603_disable(void) +{ + ds1603_set_trimmer(TRIMMER_DISABLE_RTC); +} + +void ds1603_enable(void) +{ + ds1603_set_trimmer(TRIMMER_DEFAULT); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/ds1603.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,33 @@ +/* + * Dallas Semiconductors 1603 RTC driver + * + * Brian Murphy + * + */ +#ifndef __DS1603_H +#define __DS1603_H + +struct ds_defs { + volatile u32 *reg; + volatile u32 *data_reg; + u32 rst; + u32 clk; + u32 data; + u32 data_read_shift; + char data_reversed; + u32 huge_delay; +}; + +extern struct ds_defs *ds1603; + +unsigned long ds1603_read(void); +int ds1603_set(unsigned long); +void ds1603_set_trimmer(unsigned int); +void ds1603_enable(void); +void ds1603_disable(void); +void ds1603_init(struct ds_defs *); + +#define TRIMMER_DEFAULT 3 +#define TRIMMER_DISABLE_RTC 0 + +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/image/head.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,31 @@ +#include + + .text + .section .text.start, "ax" + .set noreorder + .set mips3 + + /* Magic words identifying a software image */ + .word LASAT_K_MAGIC0_VAL + .word LASAT_K_MAGIC1_VAL + + /* Image header version */ + .word 0x00000002 + + /* image start and size */ + .word _image_start + .word _image_size + + /* start of kernel and entrypoint in uncompressed image */ + .word _kernel_start + .word _kernel_entry + + /* Here we have room for future flags */ + + .org 0x40 +reldate: + .word TIMESTAMP + + .org 0x50 +release: + .string VERSION --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/image/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,52 @@ +# +# MAKEFILE FOR THE MIPS LINUX BOOTLOADER AND ROM DEBUGGER +# +# i-data Networks +# +# Author: Thomas Horsten +# + +ifndef Version + Version = "$(USER)-test" +endif + +MKLASATIMG = mklasatimg +MKLASATIMG_ARCH = mq2,mqpro,sp100,sp200 +KERNEL_IMAGE = $(TOPDIR)/vmlinux +KERNEL_START = $(shell $(NM) $(KERNEL_IMAGE) | grep " _text" | cut -f1 -d\ ) +KERNEL_ENTRY = $(shell $(NM) $(KERNEL_IMAGE) | grep kernel_entry | cut -f1 -d\ ) + +LDSCRIPT= -L$(obj) -Tromscript.normal + +AFLAGS_head.o += -D_kernel_start=0x$(KERNEL_START) \ + -D_kernel_entry=0x$(KERNEL_ENTRY) \ + -D VERSION="\"$(Version)\"" \ + -D TIMESTAMP=$(shell date +%s) + +head.o: $(KERNEL_IMAGE) + +obj-y = head.o kImage.o + +rom.sw: $(obj)/rom.sw + +$(obj)/rom.sw: $(obj)/rom.bin + $(MKLASATIMG) -o $@ -k $^ -m $(MKLASATIMG_ARCH) + +$(obj)/rom.bin: $(obj)/rom + $(OBJCOPY) -O binary -S $^ $@ + +# Rule to make the bootloader +$(obj)/rom: $(addprefix $(obj)/,$(obj-y)) + $(LD) $(LDFLAGS) $(LDSCRIPT) -o $@ $^ + +$(obj)/%.o: $(obj)/%.gz + $(LD) -r -o $@ -b binary $< + +$(obj)/%.gz: $(obj)/%.bin + gzip -cf -9 $< > $@ + +$(obj)/kImage.bin: $(KERNEL_IMAGE) + $(OBJCOPY) -O binary -S $^ $@ + +clean: + rm -f rom rom.bin rom.sw kImage.bin kImage.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/image/romscript.normal 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,22 @@ +OUTPUT_ARCH(mips) + +SECTIONS +{ + .text : + { + *(.text.start) + } + + /* Data in ROM */ + + .data ALIGN(0x10) : + { + *(.data) + } + _image_start = ADDR(.data); + _image_size = SIZEOF(.data); + + .other : { + *(.*) + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/interrupt.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,194 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Routines for generic manipulation of the interrupts found on the + * Lasat boards. + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static volatile int *lasat_int_status = NULL; +static volatile int *lasat_int_mask = NULL; +static volatile int lasat_int_mask_shift; + +extern asmlinkage void mipsIRQ(void); + +#if 0 +#define DEBUG_INT(x...) printk(x) +#else +#define DEBUG_INT(x...) +#endif + +void disable_lasat_irq(unsigned int irq_nr) +{ + unsigned long flags; + DEBUG_INT("disable_lasat_irq: %d", irq_nr); + + local_irq_save(flags); + *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift; + local_irq_restore(flags); +} + +void enable_lasat_irq(unsigned int irq_nr) +{ + unsigned long flags; + DEBUG_INT("enable_lasat_irq: %d", irq_nr); + + local_irq_save(flags); + *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift; + local_irq_restore(flags); +} + +static unsigned int startup_lasat_irq(unsigned int irq) +{ + enable_lasat_irq(irq); + return 0; /* never anything pending */ +} + +#define shutdown_lasat_irq disable_lasat_irq + +#define mask_and_ack_lasat_irq disable_lasat_irq + +static void end_lasat_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_lasat_irq(irq); +} + +static struct hw_interrupt_type lasat_irq_type = { + "Lasat", + startup_lasat_irq, + shutdown_lasat_irq, + enable_lasat_irq, + disable_lasat_irq, + mask_and_ack_lasat_irq, + end_lasat_irq, + NULL +}; + +static inline int ls1bit32(unsigned int x) +{ + int b = 31, s; + + s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s; + s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s; + s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s; + s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s; + s = 1; if (x << 1 == 0) s = 0; b -= s; + + return b; +} + +static unsigned long (* get_int_status)(void); + +static unsigned long get_int_status_100(void) +{ + return (*lasat_int_status & *lasat_int_mask); +} + +static unsigned long get_int_status_200(void) +{ + unsigned long int_status; + + int_status = *lasat_int_status; + int_status &= (int_status >> LASATINT_MASK_SHIFT_200) & 0xffff; + return int_status; +} + +void lasat_hw0_irqdispatch(struct pt_regs *regs) +{ + struct irqaction *action; + unsigned long int_status; + int irq; + + int_status = get_int_status(); + + /* if int_status == 0, then the interrupt has already been cleared */ + if (int_status == 0) + return; + + irq = ls1bit32(int_status); + action = irq_desc[irq].action; + + DEBUG_INT("lasat_hw0_irqdispatch: irq=%d\n", irq); + + /* if action == NULL, then we don't have a handler for the irq */ + if (action == NULL) { + printk("No handler for hw0 irq: %i\n", irq); + atomic_inc(&irq_err_count); + disable_lasat_irq(irq); + return; + } + + irq_enter(); + kstat_cpu(0).irqs[irq]++; + action->handler(irq, action->dev_id, regs); + irq_exit(); + + return; +} + +void __init init_IRQ(void) +{ + int i; + + init_generic_irq(); + + switch (mips_machtype) { + case MACH_LASAT_100: + lasat_int_status = (void *)LASAT_INT_STATUS_REG_100; + lasat_int_mask = (void *)LASAT_INT_MASK_REG_100; + lasat_int_mask_shift = LASATINT_MASK_SHIFT_100; + get_int_status = get_int_status_100; + *lasat_int_mask = 0; + break; + case MACH_LASAT_200: + printk("**** MACH_LASAT_200 interrupt routines\n"); + lasat_int_status = (void *)LASAT_INT_STATUS_REG_200; + lasat_int_mask = (void *)LASAT_INT_MASK_REG_200; + lasat_int_mask_shift = LASATINT_MASK_SHIFT_200; + get_int_status = get_int_status_200; + *lasat_int_mask &= 0xffff; + break; + default: + panic("init_IRQ: mips_machtype incorrect"); + } + + /* Now safe to set the exception vector. */ + set_except_vector(0, mipsIRQ); + + for (i = 0; i <= LASATINT_END; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &lasat_irq_type; + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/lasat_board.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,282 @@ +/* + * lasat_board.c + * + * Thomas Horsten + * Copyright (C) 2000 LASAT Networks A/S. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Routines specific to the LASAT boards + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "at93c.h" +/* New model description table */ +#include "lasat_models.h" + +#define EEPROM_CRC(data, len) (~0 ^ crc32(~0, data, len)) + +struct lasat_info lasat_board_info; + +void update_bcastaddr(void); + +int EEPROMRead(unsigned int pos, unsigned char *data, int len) +{ + int i; + + for (i=0; i 0x200000) { + ls[LASAT_MTD_CONFIG] = 0x100000; + ls[LASAT_MTD_FS] = 0x500000; + } + } else { + lasat_board_info.li_flash_base = KSEG1ADDR(0x10000000); + + if (lasat_board_info.li_flash_size < 0x1000000) { + lb[LASAT_MTD_BOOTLOADER] = KSEG1ADDR(0x10000000); + ls[LASAT_MTD_CONFIG] = 0x100000; + if (lasat_board_info.li_flash_size >= 0x400000) { + ls[LASAT_MTD_FS] = lasat_board_info.li_flash_size - 0x300000; + } + } + } + + for (i = 1; i < LASAT_MTD_LAST; i++) + lb[i] = lb[i-1] + ls[i-1]; +} + +int lasat_init_board_info(void) +{ + int c; + unsigned long crc; + unsigned long cfg0, cfg1; + const product_info_t *ppi; + int i_n_base_models = N_BASE_MODELS; + const char * const * i_txt_base_models = txt_base_models; + int i_n_prids = N_PRIDS; + + memset(&lasat_board_info, 0, sizeof(lasat_board_info)); + + /* First read the EEPROM info */ + EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info, + sizeof(struct lasat_eeprom_struct)); + + /* Check the CRC */ + crc = EEPROM_CRC((unsigned char *)(&lasat_board_info.li_eeprom_info), + sizeof(struct lasat_eeprom_struct) - 4); + + if (crc != lasat_board_info.li_eeprom_info.crc32) { + prom_printf("WARNING...\nWARNING...\nEEPROM CRC does not match calculated, attempting to soldier on...\n"); + } + + if (lasat_board_info.li_eeprom_info.version != LASAT_EEPROM_VERSION) + { + prom_printf("WARNING...\nWARNING...\nEEPROM version %d, wanted version %d, attempting to soldier on...\n", + (unsigned int)lasat_board_info.li_eeprom_info.version, + LASAT_EEPROM_VERSION); + } + + cfg0 = lasat_board_info.li_eeprom_info.cfg[0]; + cfg1 = lasat_board_info.li_eeprom_info.cfg[1]; + + if ( LASAT_W0_DSCTYPE(cfg0) != 1) { + prom_printf("WARNING...\nWARNING...\nInvalid configuration read from EEPROM, attempting to soldier on..."); + } + /* We have a valid configuration */ + + switch (LASAT_W0_SDRAMBANKSZ(cfg0)) { + case 0: + lasat_board_info.li_memsize = 0x0800000; + break; + case 1: + lasat_board_info.li_memsize = 0x1000000; + break; + case 2: + lasat_board_info.li_memsize = 0x2000000; + break; + case 3: + lasat_board_info.li_memsize = 0x4000000; + break; + case 4: + lasat_board_info.li_memsize = 0x8000000; + break; + default: + lasat_board_info.li_memsize = 0; + } + + switch (LASAT_W0_SDRAMBANKS(cfg0)) { + case 0: + break; + case 1: + lasat_board_info.li_memsize *= 2; + break; + default: + break; + } + + switch (LASAT_W0_BUSSPEED(cfg0)) { + case 0x0: + lasat_board_info.li_bus_hz = 60000000; + break; + case 0x1: + lasat_board_info.li_bus_hz = 66000000; + break; + case 0x2: + lasat_board_info.li_bus_hz = 66666667; + break; + case 0x3: + lasat_board_info.li_bus_hz = 80000000; + break; + case 0x4: + lasat_board_info.li_bus_hz = 83333333; + break; + case 0x5: + lasat_board_info.li_bus_hz = 100000000; + break; + } + + switch (LASAT_W0_CPUCLK(cfg0)) { + case 0x0: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz; + break; + case 0x1: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz + + (lasat_board_info.li_bus_hz >> 1); + break; + case 0x2: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz + + lasat_board_info.li_bus_hz; + break; + case 0x3: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz + + lasat_board_info.li_bus_hz + + (lasat_board_info.li_bus_hz >> 1); + break; + case 0x4: + lasat_board_info.li_cpu_hz = + lasat_board_info.li_bus_hz + + lasat_board_info.li_bus_hz + + lasat_board_info.li_bus_hz; + break; + } + + /* Flash size */ + switch (LASAT_W1_FLASHSIZE(cfg1)) { + case 0: + lasat_board_info.li_flash_size = 0x200000; + break; + case 1: + lasat_board_info.li_flash_size = 0x400000; + break; + case 2: + lasat_board_info.li_flash_size = 0x800000; + break; + case 3: + lasat_board_info.li_flash_size = 0x1000000; + break; + case 4: + lasat_board_info.li_flash_size = 0x2000000; + break; + } + + init_flash_sizes(); + + lasat_board_info.li_bmid = LASAT_W0_BMID(cfg0); + lasat_board_info.li_prid = lasat_board_info.li_eeprom_info.prid; + if (lasat_board_info.li_prid == 0xffff || lasat_board_info.li_prid == 0) + lasat_board_info.li_prid = lasat_board_info.li_bmid; + + /* Base model stuff */ + if (lasat_board_info.li_bmid > i_n_base_models) + lasat_board_info.li_bmid = i_n_base_models; + strcpy(lasat_board_info.li_bmstr, i_txt_base_models[lasat_board_info.li_bmid]); + + /* Product ID dependent values */ + c = lasat_board_info.li_prid; + if (c >= i_n_prids) { + strcpy(lasat_board_info.li_namestr, "Unknown Model"); + strcpy(lasat_board_info.li_typestr, "Unknown Type"); + } else { + ppi = &vendor_info_table[0].vi_product_info[c]; + strcpy(lasat_board_info.li_namestr, ppi->pi_name); + if (ppi->pi_type) + strcpy(lasat_board_info.li_typestr, ppi->pi_type); + else + sprintf(lasat_board_info.li_typestr, "%d",10*c); + } + +#if defined(CONFIG_INET) && defined(CONFIG_SYSCTL) + update_bcastaddr(); +#endif + + return 0; +} + +void lasat_write_eeprom_info(void) +{ + unsigned long crc; + + /* Generate the CRC */ + crc = EEPROM_CRC((unsigned char *)(&lasat_board_info.li_eeprom_info), + sizeof(struct lasat_eeprom_struct) - 4); + lasat_board_info.li_eeprom_info.crc32 = crc; + + /* Write the EEPROM info */ + EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info, + sizeof(struct lasat_eeprom_struct)); +} + --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/lasatIRQ.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,75 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Interrupt exception dispatch code. + * + */ +#include + +#include +#include +#include +#include + + .text + .set noreorder + .set noat + .align 5 + NESTED(mipsIRQ, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + + mfc0 s0, CP0_CAUSE # get irq mask + + /* First we check for r4k counter/timer IRQ. */ + andi a0, s0, CAUSEF_IP7 + beq a0, zero, 1f + andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt + + /* Wheee, a timer interrupt. */ + move a0, sp + jal lasat_timer_interrupt + nop + + j ret_from_irq + nop + +1: + /* Wheee, combined hardware level zero interrupt. */ + jal lasat_hw0_irqdispatch + move a0, sp # delay slot + + j ret_from_irq + nop # delay slot + +1: + /* + * Here by mistake? This is possible, what can happen is that by the + * time we take the exception the IRQ pin goes low, so just leave if + * this is the case. + */ + move a1,s0 + mfc0 a1, CP0_EPC + + j ret_from_irq + nop + END(mipsIRQ) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/lasat_models.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,63 @@ +/* + * Model description tables + */ + +typedef struct product_info_t { + const char *pi_name; + const char *pi_type; +} product_info_t; + +typedef struct vendor_info_t { + const char *vi_name; + const product_info_t *vi_product_info; +} vendor_info_t; + +/* + * Base models + */ +static const char * const txt_base_models[] = { + "MQ 2", "MQ Pro", "SP 25", "SP 50", "SP 100", "SP 5000", "SP 7000", "SP 1000", "Unknown" +}; +#define N_BASE_MODELS (sizeof(txt_base_models)/sizeof(char*)-1) + +/* + * Eicon Networks + */ +static const char txt_en_mq[] = "Masquerade"; +static const char txt_en_sp[] = "Safepipe"; + +static const product_info_t product_info_eicon[] = { + { txt_en_mq, "II" }, /* 0 */ + { txt_en_mq, "Pro" }, /* 1 */ + { txt_en_sp, "25" }, /* 2 */ + { txt_en_sp, "50" }, /* 3 */ + { txt_en_sp, "100" }, /* 4 */ + { txt_en_sp, "5000" }, /* 5 */ + { txt_en_sp, "7000" }, /* 6 */ + { txt_en_sp, "30" }, /* 7 */ + { txt_en_sp, "5100" }, /* 8 */ + { txt_en_sp, "7100" }, /* 9 */ + { txt_en_sp, "1110" }, /* 10 */ + { txt_en_sp, "3020" }, /* 11 */ + { txt_en_sp, "3030" }, /* 12 */ + { txt_en_sp, "5020" }, /* 13 */ + { txt_en_sp, "5030" }, /* 14 */ + { txt_en_sp, "1120" }, /* 15 */ + { txt_en_sp, "1130" }, /* 16 */ + { txt_en_sp, "6010" }, /* 17 */ + { txt_en_sp, "6110" }, /* 18 */ + { txt_en_sp, "6210" }, /* 19 */ + { txt_en_sp, "1020" }, /* 20 */ + { txt_en_sp, "1040" }, /* 21 */ + { txt_en_sp, "1050" }, /* 22 */ + { txt_en_sp, "1060" }, /* 23 */ +}; +#define N_PRIDS (sizeof(product_info_eicon)/sizeof(product_info_t)) + +/* + * The vendor table + */ +static vendor_info_t const vendor_info_table[] = { + { "Eicon Networks", product_info_eicon }, +}; +#define N_VENDORS (sizeof(vendor_info_table)/sizeof(vendor_info_t)) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,14 @@ +# +# Makefile for the LASAT specific kernel interface routines under Linux. +# + +obj-y += reset.o setup.o prom.o lasat_board.o \ + at93c.o interrupt.o lasatIRQ.o + +obj-$(CONFIG_LASAT_SYSCTL) += sysctl.o +obj-$(CONFIG_DS1603) += ds1603.o +obj-$(CONFIG_PICVUE) += picvue.o +obj-$(CONFIG_PICVUE_PROC) += picvue_proc.o + +clean: + make -C image clean --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/picvue.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,240 @@ +/* + * Picvue PVC160206 display driver + * + * Brian Murphy + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "picvue.h" + +#define PVC_BUSY 0x80 +#define PVC_NLINES 2 +#define PVC_DISPMEM 80 +#define PVC_LINELEN PVC_DISPMEM / PVC_NLINES + +struct pvc_defs *picvue = NULL; + +DECLARE_MUTEX(pvc_sem); + +static void pvc_reg_write(u32 val) +{ + *picvue->reg = val; +} + +static u32 pvc_reg_read(void) +{ + u32 tmp = *picvue->reg; + return tmp; +} + +static void pvc_write_byte(u32 data, u8 byte) +{ + data |= picvue->e; + pvc_reg_write(data); + data &= ~picvue->data_mask; + data |= byte << picvue->data_shift; + pvc_reg_write(data); + ndelay(220); + pvc_reg_write(data & ~picvue->e); + ndelay(220); +} + +static u8 pvc_read_byte(u32 data) +{ + u8 byte; + + data |= picvue->e; + pvc_reg_write(data); + ndelay(220); + byte = (pvc_reg_read() & picvue->data_mask) >> picvue->data_shift; + data &= ~picvue->e; + pvc_reg_write(data); + ndelay(220); + return byte; +} + +static u8 pvc_read_data(void) +{ + u32 data = pvc_reg_read(); + u8 byte; + data |= picvue->rw; + data &= ~picvue->rs; + pvc_reg_write(data); + ndelay(40); + byte = pvc_read_byte(data); + data |= picvue->rs; + pvc_reg_write(data); + return byte; +} + +#define TIMEOUT 1000 +static int pvc_wait(void) +{ + int i = TIMEOUT; + int err = 0; + + while ((pvc_read_data() & PVC_BUSY) && i) + i--; + if (i == 0) + err = -ETIME; + + return err; +} + +#define MODE_INST 0 +#define MODE_DATA 1 +static void pvc_write(u8 byte, int mode) +{ + u32 data = pvc_reg_read(); + data &= ~picvue->rw; + if (mode == MODE_DATA) + data |= picvue->rs; + else + data &= ~picvue->rs; + pvc_reg_write(data); + ndelay(40); + pvc_write_byte(data, byte); + if (mode == MODE_DATA) + data &= ~picvue->rs; + else + data |= picvue->rs; + pvc_reg_write(data); + pvc_wait(); +} + +void pvc_write_string(const unsigned char *str, u8 addr, int line) +{ + int i = 0; + + if (line > 0 && (PVC_NLINES > 1)) + addr += 0x40 * line; + pvc_write(0x80 | addr, MODE_INST); + + while (*str != 0 && i < PVC_LINELEN) { + pvc_write(*str++, MODE_DATA); + i++; + } +} + +void pvc_write_string_centered(const unsigned char *str, int line) +{ + int len = strlen(str); + u8 addr; + + if (len > PVC_VISIBLE_CHARS) + addr = 0; + else + addr = (PVC_VISIBLE_CHARS - strlen(str))/2; + + pvc_write_string(str, addr, line); +} + +void pvc_dump_string(const unsigned char *str) +{ + int len = strlen(str); + + pvc_write_string(str, 0, 0); + if (len > PVC_VISIBLE_CHARS) + pvc_write_string(&str[PVC_VISIBLE_CHARS], 0, 1); +} + +#define BM_SIZE 8 +#define MAX_PROGRAMMABLE_CHARS 8 +int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE]) +{ + int i; + int addr; + + if (charnum > MAX_PROGRAMMABLE_CHARS) + return -ENOENT; + + addr = charnum * 8; + pvc_write(0x40 | addr, MODE_INST); + + for (i=0; i + * + */ +#include + +struct pvc_defs { + volatile u32 *reg; + u32 data_shift; + u32 data_mask; + u32 e; + u32 rw; + u32 rs; +}; + +extern struct pvc_defs *picvue; + +#define PVC_NLINES 2 +#define PVC_DISPMEM 80 +#define PVC_LINELEN PVC_DISPMEM / PVC_NLINES +#define PVC_VISIBLE_CHARS 16 + +void pvc_write_string(const unsigned char *str, u8 addr, int line); +void pvc_write_string_centered(const unsigned char *str, int line); +void pvc_dump_string(const unsigned char *str); + +#define BM_SIZE 8 +#define MAX_PROGRAMMABLE_CHARS 8 +int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE]); + +void pvc_dispcnt(u8 cmd); +#define DISP_OFF 0 +#define DISP_ON (1 << 2) +#define CUR_ON (1 << 1) +#define CUR_BLINK (1 << 0) + +void pvc_move(u8 cmd); +#define DISPLAY (1 << 3) +#define CURSOR 0 +#define RIGHT (1 << 2) +#define LEFT 0 + +void pvc_clear(void); +void pvc_home(void); + +extern struct semaphore pvc_sem; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/picvue_proc.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,186 @@ +/* + * Picvue PVC160206 display driver + * + * Brian Murphy + * + */ +#include +#include +#include +#include + +#include +#include + +#include + +#include "picvue.h" + +static char pvc_lines[PVC_NLINES][PVC_LINELEN+1]; +static int pvc_linedata[PVC_NLINES]; +static struct proc_dir_entry *pvc_display_dir; +static char *pvc_linename[PVC_NLINES] = {"line1", "line2"}; +#define DISPLAY_DIR_NAME "display" +static int scroll_dir = 0, scroll_interval = 0; + +static struct timer_list timer; + +static void pvc_display(unsigned long data) { + int i; + + pvc_clear(); + for (i=0; i PVC_NLINES) { + printk("proc_read_line: invalid lineno %d\n", lineno); + return 0; + } + + down(&pvc_sem); + page += sprintf(page, "%s\n", pvc_lines[lineno]); + up(&pvc_sem); + + return page - origpage; +} + +static int pvc_proc_write_line(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + int origcount = count; + int lineno = *(int *)data; + + if (lineno < 0 || lineno > PVC_NLINES) { + printk("proc_write_line: invalid lineno %d\n", lineno); + return origcount; + } + + if (count > PVC_LINELEN) + count = PVC_LINELEN; + + if (buffer[count-1] == '\n') + count--; + + down(&pvc_sem); + strncpy(pvc_lines[lineno], buffer, count); + pvc_lines[lineno][count] = '\0'; + up(&pvc_sem); + + tasklet_schedule(&pvc_display_tasklet); + + return origcount; +} + +static int pvc_proc_write_scroll(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + int origcount = count; + int cmd = simple_strtol(buffer, NULL, 10); + + down(&pvc_sem); + if (scroll_interval != 0) + del_timer(&timer); + + if (cmd == 0) { + scroll_dir = 0; + scroll_interval = 0; + } else { + if (cmd < 0) { + scroll_dir = -1; + scroll_interval = -cmd; + } else { + scroll_dir = 1; + scroll_interval = cmd; + } + add_timer(&timer); + } + up(&pvc_sem); + + return origcount; +} + +static int pvc_proc_read_scroll(char *page, char **start, + off_t off, int count, + int *eof, void *data) +{ + char *origpage = page; + + down(&pvc_sem); + page += sprintf(page, "%d\n", scroll_dir * scroll_interval); + up(&pvc_sem); + + return page - origpage; +} + + +void pvc_proc_timerfunc(unsigned long data) +{ + if (scroll_dir < 0) + pvc_move(DISPLAY|RIGHT); + else if (scroll_dir > 0) + pvc_move(DISPLAY|LEFT); + + timer.expires = jiffies + scroll_interval; + add_timer(&timer); +} + +static void pvc_proc_cleanup(void) +{ + int i; + for (i=0; iread_proc = pvc_proc_read_line; + proc_entry->write_proc = pvc_proc_write_line; + proc_entry->data = &pvc_linedata[i]; + } + proc_entry = create_proc_entry("scroll", 0644, pvc_display_dir); + if (proc_entry == NULL) + goto error; + proc_entry->write_proc = pvc_proc_write_scroll; + proc_entry->read_proc = pvc_proc_read_scroll; + + init_timer(&timer); + timer.function = pvc_proc_timerfunc; + + return 0; +error: + pvc_proc_cleanup(); + return -ENOMEM; +} + +module_init(pvc_proc_init); +module_exit(pvc_proc_cleanup); +MODULE_LICENSE("GPL"); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/prom.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,135 @@ +/* + * PROM interface routines. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "at93c.h" +#include +#include "prom.h" + +#define RESET_VECTOR 0xbfc00000 +#define PROM_JUMP_TABLE_ENTRY(n) (*((u32 *)(RESET_VECTOR + 0x20) + n)) +#define PROM_DISPLAY_ADDR PROM_JUMP_TABLE_ENTRY(0) +#define PROM_PUTC_ADDR PROM_JUMP_TABLE_ENTRY(1) +#define PROM_MONITOR_ADDR PROM_JUMP_TABLE_ENTRY(2) + +static void null_prom_printf(const char * fmt, ...) +{ +} + +static void null_prom_display(const char *string, int pos, int clear) +{ +} + +static void null_prom_monitor(void) +{ +} + +static void null_prom_putc(char c) +{ +} + +/* these are functions provided by the bootloader */ +static void (* prom_putc)(char c) = null_prom_putc; +void (* prom_printf)(const char * fmt, ...) = null_prom_printf; +void (* prom_display)(const char *string, int pos, int clear) = + null_prom_display; +void (* prom_monitor)(void) = null_prom_monitor; + +#define PROM_PRINTFBUF_SIZE 256 +static char prom_printfbuf[PROM_PRINTFBUF_SIZE]; + +static void real_prom_printf(const char * fmt, ...) +{ + va_list ap; + int len; + char *c = prom_printfbuf; + int i; + + va_start(ap, fmt); + len = vsnprintf(prom_printfbuf, PROM_PRINTFBUF_SIZE, fmt, ap); + va_end(ap); + + /* output overflowed the buffer */ + if (len < 0 || len > PROM_PRINTFBUF_SIZE) + len = PROM_PRINTFBUF_SIZE; + + for (i=0; i < len; i++) { + if (*c == '\n') + prom_putc('\r'); + prom_putc(*c++); + } +} + +static void setup_prom_vectors(void) +{ + u32 version = *(u32 *)(RESET_VECTOR + 0x90); + + if (version == 306) { + prom_display = (void *)PROM_DISPLAY_ADDR; + prom_putc = (void *)PROM_PUTC_ADDR; + prom_printf = real_prom_printf; + prom_monitor = (void *)PROM_MONITOR_ADDR; + } + prom_printf("prom vectors set up\n"); +} + +char arcs_cmdline[CL_SIZE]; + +static struct at93c_defs at93c_defs[N_MACHTYPES] = { + {(void *)AT93C_REG_100, (void *)AT93C_RDATA_REG_100, AT93C_RDATA_SHIFT_100, + AT93C_WDATA_SHIFT_100, AT93C_CS_M_100, AT93C_CLK_M_100}, + {(void *)AT93C_REG_200, (void *)AT93C_RDATA_REG_200, AT93C_RDATA_SHIFT_200, + AT93C_WDATA_SHIFT_200, AT93C_CS_M_200, AT93C_CLK_M_200}, +}; + +void __init prom_init(int argc, char **argv, char **envp, int *prom_vec) +{ + setup_prom_vectors(); + + if (current_cpu_data.cputype == CPU_R5000) + mips_machtype = MACH_LASAT_200; + else + mips_machtype = MACH_LASAT_100; + + at93c = &at93c_defs[mips_machtype]; + + lasat_init_board_info(); /* Read info from EEPROM */ + + mips_machgroup = MACH_GROUP_LASAT; + + /* Get the command line */ + if (argc>0) { + strncpy(arcs_cmdline, argv[0], CL_SIZE-1); + arcs_cmdline[CL_SIZE-1] = '\0'; + } + + /* Set the I/O base address */ + set_io_port_base(KSEG1); + + /* Set memory regions */ + ioport_resource.start = 0; /* Should be KSEGx ??? */ + ioport_resource.end = 0xffffffff; /* Should be ??? */ + + add_memory_region(0, lasat_board_info.li_memsize, BOOT_MEM_RAM); +} + +void prom_free_prom_memory(void) +{ +} + +const char *get_system_type(void) +{ + return lasat_board_info.li_bmstr; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/prom.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,6 @@ +#ifndef PROM_H +#define PROM_H +extern void (* prom_display)(const char *string, int pos, int clear); +extern void (* prom_monitor)(void); +extern void (* prom_printf)(const char * fmt, ...); +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/reset.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,73 @@ +/* + * + * Thomas Horsten + * Copyright (C) 2000 LASAT Networks A/S. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Reset the LASAT board. + * + */ + +#include +#include +#include +#include +#include "picvue.h" +#include "prom.h" + +static void lasat_machine_restart(char *command); +static void lasat_machine_halt(void); + +/* Used to set machine to boot in service mode via /proc interface */ +int lasat_boot_to_service = 0; + +static void lasat_machine_restart(char *command) +{ + local_irq_disable(); + + if (lasat_boot_to_service) { + printk("machine_restart: Rebooting to service mode\n"); + *(volatile unsigned int *)0xa0000024 = 0xdeadbeef; + *(volatile unsigned int *)0xa00000fc = 0xfedeabba; + } + *lasat_misc->reset_reg = 0xbedead; + for (;;) ; +} + +#define MESSAGE "System halted" +static void lasat_machine_halt(void) +{ + local_irq_disable(); + + /* Disable interrupts and loop forever */ + printk(KERN_NOTICE MESSAGE "\n"); +#ifdef CONFIG_PICVUE + pvc_clear(); + pvc_write_string(MESSAGE, 0, 0); +#endif + prom_monitor(); + for (;;) ; +} + +void lasat_reboot_setup(void) +{ + _machine_restart = lasat_machine_restart; + _machine_halt = lasat_machine_halt; + _machine_power_off = lasat_machine_halt; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,221 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved. + * + * Thomas Horsten + * Copyright (C) 2000 LASAT Networks A/S. + * + * Brian Murphy + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Lasat specific setup. + */ +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_PICVUE +#include +#endif + +#include "ds1603.h" +#include "at93c.h" +#include +#include +#include + +#include "prom.h" + +int lasat_command_line = 0; +void lasatint_init(void); + +#ifdef CONFIG_BLK_DEV_IDE +extern struct ide_ops std_ide_ops; +extern struct ide_ops *ide_ops; +#endif + +extern char arcs_cmdline[CL_SIZE]; + +extern void lasat_reboot_setup(void); +extern void pcisetup(void); +extern void edhac_init(void *, void *, void *); +extern void addrflt_init(void); + +struct lasat_misc lasat_misc_info[N_MACHTYPES] = { + {(void *)KSEG1ADDR(0x1c840000), (void *)KSEG1ADDR(0x1c800000), 2}, + {(void *)KSEG1ADDR(0x11080000), (void *)KSEG1ADDR(0x11000000), 6} +}; + +struct lasat_misc *lasat_misc = NULL; + +#ifdef CONFIG_DS1603 +static struct ds_defs ds_defs[N_MACHTYPES] = { + { (void *)DS1603_REG_100, (void *)DS1603_REG_100, + DS1603_RST_100, DS1603_CLK_100, DS1603_DATA_100, + DS1603_DATA_SHIFT_100, 0, 0 }, + { (void *)DS1603_REG_200, (void *)DS1603_DATA_REG_200, + DS1603_RST_200, DS1603_CLK_200, DS1603_DATA_200, + DS1603_DATA_READ_SHIFT_200, 1, 2000 } +}; +#endif + +#ifdef CONFIG_PICVUE +#include "picvue.h" +static struct pvc_defs pvc_defs[N_MACHTYPES] = { + { (void *)PVC_REG_100, PVC_DATA_SHIFT_100, PVC_DATA_M_100, + PVC_E_100, PVC_RW_100, PVC_RS_100 }, + { (void *)PVC_REG_200, PVC_DATA_SHIFT_200, PVC_DATA_M_200, + PVC_E_200, PVC_RW_200, PVC_RS_200 } +}; +#endif + +static int lasat_panic_display(struct notifier_block *this, + unsigned long event, void *ptr) +{ +#ifdef CONFIG_PICVUE + unsigned char *string = ptr; + if (string == NULL) + string = "Kernel Panic"; + pvc_dump_string(string); +#endif + return NOTIFY_DONE; +} + +static int lasat_panic_prom_monitor(struct notifier_block *this, + unsigned long event, void *ptr) +{ + prom_monitor(); + return NOTIFY_DONE; +} + +static struct notifier_block lasat_panic_block[] = +{ + { lasat_panic_display, NULL, INT_MAX }, + { lasat_panic_prom_monitor, NULL, INT_MIN } +}; + +#ifdef CONFIG_BLK_DEV_IDE +static int lasat_ide_default_irq(ide_ioreg_t base) { + return 0; +} + +static ide_ioreg_t lasat_ide_default_io_base(int index) { + return 0; +} +#endif + +static void lasat_time_init(void) +{ + mips_counter_frequency = lasat_board_info.li_cpu_hz / 2; +} + +static void lasat_timer_setup(struct irqaction *irq) +{ + + write_c0_compare( + read_c0_count() + + mips_counter_frequency / HZ); + change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); +} + +#define MIPS_CPU_TIMER_IRQ 7 +asmlinkage void lasat_timer_interrupt(struct pt_regs *regs) +{ + ll_timer_interrupt(MIPS_CPU_TIMER_IRQ, regs); +} + +//#define DYNAMIC_SERIAL_INIT +#ifdef DYNAMIC_SERIAL_INIT +void __init serial_init(void) +{ +#ifdef CONFIG_SERIAL + struct serial_struct s; + + memset(&s, 0, sizeof(s)); + + s.flags = STD_COM_FLAGS; + s.io_type = SERIAL_IO_MEM; + + if (mips_machtype == MACH_LASAT_100) { + s.baud_base = LASAT_BASE_BAUD_100; + s.irq = LASATINT_UART_100; + s.iomem_reg_shift = LASAT_UART_REGS_SHIFT_100; + s.iomem_base = (u8 *)KSEG1ADDR(LASAT_UART_REGS_BASE_100); + } else { + s.baud_base = LASAT_BASE_BAUD_200; + s.irq = LASATINT_UART_200; + s.iomem_reg_shift = LASAT_UART_REGS_SHIFT_200; + s.iomem_base = (u8 *)KSEG1ADDR(LASAT_UART_REGS_BASE_200); + } + + if (early_serial_setup(&s) != 0) + printk(KERN_ERR "Serial setup failed!\n"); +#endif +} +#endif + +void __init lasat_setup(void) +{ + int i; + lasat_misc = &lasat_misc_info[mips_machtype]; +#ifdef CONFIG_PICVUE + picvue = &pvc_defs[mips_machtype]; +#endif + + /* Set up panic notifier */ + for (i = 0; i < sizeof(lasat_panic_block) / sizeof(struct notifier_block); i++) + notifier_chain_register(&panic_notifier_list, &lasat_panic_block[i]); + +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &std_ide_ops; + ide_ops->ide_default_irq = &lasat_ide_default_irq; + ide_ops->ide_default_io_base = &lasat_ide_default_io_base; +#endif + + lasat_reboot_setup(); + + board_time_init = lasat_time_init; + board_timer_setup = lasat_timer_setup; + +#ifdef CONFIG_DS1603 + ds1603 = &ds_defs[mips_machtype]; + rtc_get_time = ds1603_read; + rtc_set_time = ds1603_set; +#endif + +#ifdef DYNAMIC_SERIAL_INIT + serial_init(); +#endif + /* Switch from prom exception handler to normal mode */ + change_c0_status(ST0_BEV,0); + + prom_printf("Lasat specific initialization complete\n"); +} + + --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/sysctl.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,355 @@ +/* + * Thomas Horsten + * Copyright (C) 2000 LASAT Networks A/S. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Routines specific to the LASAT boards + */ +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sysctl.h" +#include "ds1603.h" + +static DECLARE_MUTEX(lasat_info_sem); + +/* Strategy function to write EEPROM after changing string entry */ +int sysctl_lasatstring(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, + void *newval, size_t newlen, void **context) +{ + int r; + down(&lasat_info_sem); + r = sysctl_string(table, name, + nlen, oldval, oldlenp, newval, newlen, context); + if (r < 0) { + up(&lasat_info_sem); + return r; + } + if (newval && newlen) { + lasat_write_eeprom_info(); + } + up(&lasat_info_sem); + return 1; +} + + +/* And the same for proc */ +int proc_dolasatstring(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp) +{ + int r; + down(&lasat_info_sem); + r = proc_dostring(table, write, filp, buffer, lenp); + if ( (!write) || r) { + up(&lasat_info_sem); + return r; + } + lasat_write_eeprom_info(); + up(&lasat_info_sem); + return 0; +} + +/* proc function to write EEPROM after changing int entry */ +int proc_dolasatint(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp) +{ + int r; + down(&lasat_info_sem); + r = proc_dointvec(table, write, filp, buffer, lenp); + if ( (!write) || r) { + up(&lasat_info_sem); + return r; + } + lasat_write_eeprom_info(); + up(&lasat_info_sem); + return 0; +} + +static int rtctmp; + +#ifdef CONFIG_DS1603 +/* proc function to read/write RealTime Clock */ +int proc_dolasatrtc(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp) +{ + int r; + down(&lasat_info_sem); + if (!write) { + rtctmp = ds1603_read(); + /* check for time < 0 and set to 0 */ + if (rtctmp < 0) + rtctmp = 0; + } + r = proc_dointvec(table, write, filp, buffer, lenp); + if ( (!write) || r) { + up(&lasat_info_sem); + return r; + } + ds1603_set(rtctmp); + up(&lasat_info_sem); + return 0; +} +#endif + +/* Sysctl for setting the IP addresses */ +int sysctl_lasat_intvec(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, + void *newval, size_t newlen, void **context) +{ + int r; + down(&lasat_info_sem); + r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen, context); + if (r < 0) { + up(&lasat_info_sem); + return r; + } + if (newval && newlen) { + lasat_write_eeprom_info(); + } + up(&lasat_info_sem); + return 1; +} + +#ifdef CONFIG_DS1603 +/* Same for RTC */ +int sysctl_lasat_rtc(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, + void *newval, size_t newlen, void **context) +{ + int r; + down(&lasat_info_sem); + rtctmp = ds1603_read(); + if (rtctmp < 0) + rtctmp = 0; + r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen, context); + if (r < 0) { + up(&lasat_info_sem); + return r; + } + if (newval && newlen) { + ds1603_set(rtctmp); + } + up(&lasat_info_sem); + return 1; +} +#endif + +#ifdef CONFIG_INET +static char lasat_bcastaddr[16]; + +void update_bcastaddr(void) +{ + unsigned int ip; + + ip = (lasat_board_info.li_eeprom_info.ipaddr & + lasat_board_info.li_eeprom_info.netmask) | + ~lasat_board_info.li_eeprom_info.netmask; + + sprintf(lasat_bcastaddr, "%d.%d.%d.%d", + (ip ) & 0xff, + (ip >> 8) & 0xff, + (ip >> 16) & 0xff, + (ip >> 24) & 0xff); +} + +static char proc_lasat_ipbuf[32]; +/* Parsing of IP address */ +int proc_lasat_ip(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp) +{ + int len; + unsigned int ip; + char *p, c; + + if (!table->data || !table->maxlen || !*lenp || + (filp->f_pos && !write)) { + *lenp = 0; + return 0; + } + + down(&lasat_info_sem); + if (write) { + len = 0; + p = buffer; + while (len < *lenp) { + if(get_user(c, p++)) { + up(&lasat_info_sem); + return -EFAULT; + } + if (c == 0 || c == '\n') + break; + len++; + } + if (len >= sizeof(proc_lasat_ipbuf)-1) + len = sizeof(proc_lasat_ipbuf) - 1; + if (copy_from_user(proc_lasat_ipbuf, buffer, len)) + { + up(&lasat_info_sem); + return -EFAULT; + } + proc_lasat_ipbuf[len] = 0; + filp->f_pos += *lenp; + /* Now see if we can convert it to a valid IP */ + ip = in_aton(proc_lasat_ipbuf); + *(unsigned int *)(table->data) = ip; + lasat_write_eeprom_info(); + } else { + ip = *(unsigned int *)(table->data); + sprintf(proc_lasat_ipbuf, "%d.%d.%d.%d", + (ip ) & 0xff, + (ip >> 8) & 0xff, + (ip >> 16) & 0xff, + (ip >> 24) & 0xff); + len = strlen(proc_lasat_ipbuf); + if (len > *lenp) + len = *lenp; + if (len) + if(copy_to_user(buffer, proc_lasat_ipbuf, len)) { + up(&lasat_info_sem); + return -EFAULT; + } + if (len < *lenp) { + if(put_user('\n', ((char *) buffer) + len)) { + up(&lasat_info_sem); + return -EFAULT; + } + len++; + } + *lenp = len; + filp->f_pos += len; + } + update_bcastaddr(); + up(&lasat_info_sem); + return 0; +} +#endif /* defined(CONFIG_INET) */ + +static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen, + void *oldval, size_t *oldlenp, + void *newval, size_t newlen, + void **context) +{ + int r; + + down(&lasat_info_sem); + r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen, context); + if (r < 0) { + up(&lasat_info_sem); + return r; + } + + if (newval && newlen) + { + if (name && *name == LASAT_PRID) + lasat_board_info.li_eeprom_info.prid = *(int*)newval; + + lasat_write_eeprom_info(); + lasat_init_board_info(); + } + up(&lasat_info_sem); + + return 0; +} + +int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp, + void *buffer, size_t *lenp) +{ + int r; + down(&lasat_info_sem); + r = proc_dointvec(table, write, filp, buffer, lenp); + if ( (!write) || r) { + up(&lasat_info_sem); + return r; + } + if (filp && filp->f_dentry) + { + if (!strcmp(filp->f_dentry->d_name.name, "prid")) + lasat_board_info.li_eeprom_info.prid = lasat_board_info.li_prid; + if (!strcmp(filp->f_dentry->d_name.name, "debugaccess")) + lasat_board_info.li_eeprom_info.debugaccess = lasat_board_info.li_debugaccess; + } + lasat_write_eeprom_info(); + up(&lasat_info_sem); + return 0; +} + +extern int lasat_boot_to_service; + +#ifdef CONFIG_SYSCTL + +static ctl_table lasat_table[] = { + {LASAT_CPU_HZ, "cpu-hz", &lasat_board_info.li_cpu_hz, sizeof(int), + 0444, NULL, &proc_dointvec, &sysctl_intvec}, + {LASAT_BUS_HZ, "bus-hz", &lasat_board_info.li_bus_hz, sizeof(int), + 0444, NULL, &proc_dointvec, &sysctl_intvec}, + {LASAT_MODEL, "bmid", &lasat_board_info.li_bmid, sizeof(int), + 0444, NULL, &proc_dointvec, &sysctl_intvec}, + {LASAT_PRID, "prid", &lasat_board_info.li_prid, sizeof(int), + 0644, NULL, &proc_lasat_eeprom_value, &sysctl_lasat_eeprom_value}, +#ifdef CONFIG_INET + {LASAT_IPADDR, "ipaddr", &lasat_board_info.li_eeprom_info.ipaddr, sizeof(int), + 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec}, + {LASAT_NETMASK, "netmask", &lasat_board_info.li_eeprom_info.netmask, sizeof(int), + 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec}, + {LASAT_BCAST, "bcastaddr", &lasat_bcastaddr, + sizeof(lasat_bcastaddr), 0600, NULL, + &proc_dostring, &sysctl_string}, +#endif + {LASAT_PASSWORD, "passwd_hash", &lasat_board_info.li_eeprom_info.passwd_hash, sizeof(lasat_board_info.li_eeprom_info.passwd_hash), + 0600, NULL, &proc_dolasatstring, &sysctl_lasatstring}, + {LASAT_SBOOT, "boot-service", &lasat_boot_to_service, sizeof(int), + 0644, NULL, &proc_dointvec, &sysctl_intvec}, +#ifdef CONFIG_DS1603 + {LASAT_RTC, "rtc", &rtctmp, sizeof(int), + 0644, NULL, &proc_dolasatrtc, &sysctl_lasat_rtc}, +#endif + {LASAT_NAMESTR, "namestr", &lasat_board_info.li_namestr, sizeof(lasat_board_info.li_namestr), + 0444, NULL, &proc_dostring, &sysctl_string}, + {LASAT_TYPESTR, "typestr", &lasat_board_info.li_typestr, sizeof(lasat_board_info.li_typestr), + 0444, NULL, &proc_dostring, &sysctl_string}, + {0} +}; + +#define CTL_LASAT 1 // CTL_ANY ??? +static ctl_table lasat_root_table[] = { + { CTL_LASAT, "lasat", NULL, 0, 0555, lasat_table }, + { 0 } +}; + +static int __init lasat_register_sysctl(void) +{ + struct ctl_table_header *lasat_table_header; + + lasat_table_header = + register_sysctl_table(lasat_root_table, 0); + + return 0; +} + +__initcall(lasat_register_sysctl); +#endif /* CONFIG_SYSCTL */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lasat/sysctl.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,24 @@ +/* + * LASAT sysctl values + */ + +#ifndef _LASAT_SYSCTL_H +#define _LASAT_SYSCTL_H + +/* /proc/sys/lasat */ +enum { + LASAT_CPU_HZ=1, + LASAT_BUS_HZ, + LASAT_MODEL, + LASAT_PRID, + LASAT_IPADDR, + LASAT_NETMASK, + LASAT_BCAST, + LASAT_PASSWORD, + LASAT_SBOOT, + LASAT_RTC, + LASAT_NAMESTR, + LASAT_TYPESTR, +}; + +#endif /* _LASAT_SYSCTL_H */ --- linux-2.5.73/arch/mips/lib/csum_partial_copy.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/csum_partial_copy.c 2003-06-27 15:56:23.000000000 -0700 @@ -13,8 +13,6 @@ * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. - * - * $Id: csum_partial_copy.c,v 1.2 1998/09/19 19:16:17 ralf Exp $ */ #include #include @@ -25,8 +23,8 @@ /* * copy while checksumming, otherwise like csum_partial */ -unsigned int csum_partial_copy_nocheck(const char *src, char *dst, - int len, unsigned int sum) +unsigned int csum_partial_copy_nocheck(const char *src, char *dst, + int len, unsigned int sum) { /* * It's 2:30 am and I don't feel like doing it real ... @@ -43,8 +41,7 @@ unsigned int csum_partial_copy_nocheck(c * then zero the rest of the buffer. */ unsigned int csum_partial_copy_from_user (const char *src, char *dst, - int len, unsigned int sum, - int *err_ptr) + int len, unsigned int sum, int *err_ptr) { int missing; @@ -53,6 +50,6 @@ unsigned int csum_partial_copy_from_user memset(dst + len - missing, 0, missing); *err_ptr = -EFAULT; } - + return csum_partial(dst, len, sum); } --- linux-2.5.73/arch/mips/lib/csum_partial.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/csum_partial.S 2003-06-27 15:56:23.000000000 -0700 @@ -1,5 +1,4 @@ -/* $Id: csum_partial.S,v 1.1 1998/05/04 09:12:52 ralf Exp $ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. --- linux-2.5.73/arch/mips/lib/dump_tlb.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/dump_tlb.c 2003-06-27 15:56:23.000000000 -0700 @@ -4,31 +4,48 @@ * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle. * Copyright (C) 1999 by Silicon Graphics, Inc. */ +#include #include #include #include #include #include +#include #include #include #include #include -#define mips_tlb_entries 48 +static inline const char *msg2str(unsigned int mask) +{ + switch (mask) { + case PM_4K: return "4kb"; + case PM_16K: return "16kb"; + case PM_64K: return "64kb"; + case PM_256K: return "256kb"; +#ifndef CONFIG_CPU_VR41XX + case PM_1M: return "1Mb"; + case PM_4M: return "4Mb"; + case PM_16M: return "16Mb"; + case PM_64M: return "64Mb"; + case PM_256M: return "256Mb"; +#endif + } +} -void -dump_tlb(int first, int last) +void dump_tlb(int first, int last) { int i; unsigned int pagemask, c0, c1, asid; - unsigned long entryhi, entrylo0, entrylo1; + unsigned long long entrylo0, entrylo1; + unsigned long entryhi; - asid = get_entryhi() & 0xff; + asid = read_c0_entryhi() & 0xff; - for(i=first;i<=last;i++) - { - write_32bit_cp0_register(CP0_INDEX, i); + printk("\n"); + for(i=first;i<=last;i++) { + write_c0_index(i); __asm__ __volatile__( ".set\tmips3\n\t" ".set\tnoreorder\n\t" @@ -37,57 +54,53 @@ dump_tlb(int first, int last) "nop;nop;nop;nop\n\t" ".set\treorder\n\t" ".set\tmips0\n\t"); - pagemask = read_32bit_cp0_register(CP0_PAGEMASK); - entryhi = read_32bit_cp0_register(CP0_ENTRYHI); - entrylo0 = read_32bit_cp0_register(CP0_ENTRYLO0); - entrylo1 = read_32bit_cp0_register(CP0_ENTRYLO1); + pagemask = read_c0_pagemask(); + entryhi = read_c0_entryhi(); + entrylo0 = read_c0_entrylo0(); + entrylo1 = read_c0_entrylo1(); - /* Unused entries have a virtual address of KSEG0. */ - if ((entryhi & 0xffffe000) != 0x80000000 + /* Unused entries have a virtual address in KSEG0. */ + if ((entryhi & 0xf0000000) != 0x80000000 && (entryhi & 0xff) == asid) { /* * Only print entries in use */ - printk("Index: %2d pgmask=%08x ", i, pagemask); + printk("Index: %2d pgmask=%s ", i, msg2str(pagemask)); c0 = (entrylo0 >> 3) & 7; c1 = (entrylo1 >> 3) & 7; - printk("va=%08lx asid=%08lx" - " [pa=%06lx c=%d d=%d v=%d g=%ld]" - " [pa=%06lx c=%d d=%d v=%d g=%ld]", - (entryhi & 0xffffe000), - entryhi & 0xff, - entrylo0 & PAGE_MASK, c0, + printk("va=%08lx asid=%02lx\n", + (entryhi & 0xffffe000), (entryhi & 0xff)); + printk("\t\t\t[pa=%08Lx c=%d d=%d v=%d g=%Ld]\n", + (entrylo0 << 6) & PAGE_MASK, c0, (entrylo0 & 4) ? 1 : 0, (entrylo0 & 2) ? 1 : 0, - (entrylo0 & 1), - entrylo1 & PAGE_MASK, c1, + (entrylo0 & 1)); + printk("\t\t\t[pa=%08Lx c=%d d=%d v=%d g=%Ld]\n", + (entrylo1 << 6) & PAGE_MASK, c1, (entrylo1 & 4) ? 1 : 0, (entrylo1 & 2) ? 1 : 0, (entrylo1 & 1)); - + printk("\n"); } } - printk("\n"); - set_entryhi(asid); + write_c0_entryhi(asid); } -void -dump_tlb_all(void) +void dump_tlb_all(void) { - dump_tlb(0, mips_tlb_entries - 1); + dump_tlb(0, current_cpu_data.tlbsize - 1); } -void -dump_tlb_wired(void) +void dump_tlb_wired(void) { int wired; - wired = read_32bit_cp0_register(CP0_WIRED); + wired = read_c0_wired(); printk("Wired: %d", wired); - dump_tlb(0, read_32bit_cp0_register(CP0_WIRED)); + dump_tlb(0, read_c0_wired()); } #define BARRIER \ @@ -103,14 +116,14 @@ dump_tlb_addr(unsigned long addr) int index; local_irq_save(flags); - oldpid = get_entryhi() & 0xff; + oldpid = read_c0_entryhi() & 0xff; BARRIER; - set_entryhi((addr & PAGE_MASK) | oldpid); + write_c0_entryhi((addr & PAGE_MASK) | oldpid); BARRIER; tlb_probe(); BARRIER; - index = get_index(); - set_entryhi(oldpid); + index = read_c0_index(); + write_c0_entryhi(oldpid); local_irq_restore(flags); if (index < 0) { @@ -125,7 +138,7 @@ dump_tlb_addr(unsigned long addr) void dump_tlb_nonwired(void) { - dump_tlb(read_32bit_cp0_register(CP0_WIRED), mips_tlb_entries - 1); + dump_tlb(read_c0_wired(), current_cpu_data.tlbsize - 1); } void @@ -140,12 +153,20 @@ dump_list_process(struct task_struct *t, addr = (unsigned int) address; printk("Addr == %08x\n", addr); - printk("tasks->mm.pgd == %08x\n", (unsigned int) t->mm->pgd); - - page_dir = pgd_offset(t->mm, 0); + printk("task == %8p\n", t); + printk("task->mm == %8p\n", t->mm); + //printk("tasks->mm.pgd == %08x\n", (unsigned int) t->mm->pgd); + + if (addr > KSEG0) + page_dir = pgd_offset_k(0); + else + page_dir = pgd_offset(t->mm, 0); printk("page_dir == %08x\n", (unsigned int) page_dir); - pgd = pgd_offset(t->mm, addr); + if (addr > KSEG0) + pgd = pgd_offset_k(addr); + else + pgd = pgd_offset(t->mm, addr); printk("pgd == %08x, ", (unsigned int) pgd); pmd = pmd_offset(pgd, addr); @@ -155,7 +176,11 @@ dump_list_process(struct task_struct *t, printk("pte == %08x, ", (unsigned int) pte); page = *pte; - printk("page == %08x\n", (unsigned int) pte_val(page)); +#ifdef CONFIG_64BIT_PHYS_ADDR + printk("page == %08Lx\n", pte_val(page)); +#else + printk("page == %08lx\n", pte_val(page)); +#endif val = pte_val(page); if (val & _PAGE_PRESENT) printk("present "); @@ -200,9 +225,7 @@ dump16(unsigned long *p) for(i=0;i<8;i++) { - printk("*%08lx == %08lx, ", - (unsigned long)p, (unsigned long)*p++); - printk("*%08lx == %08lx\n", - (unsigned long)p, (unsigned long)*p++); + printk("*%8p = %08lx, ", p, *p); p++; + printk("*%8p = %08lx\n", p, *p); p++; } } --- linux-2.5.73/arch/mips/lib/floppy-no.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/floppy-no.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,5 +1,4 @@ -/* $Id: floppy-no.c,v 1.1 1998/05/07 18:38:32 ralf Exp $ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. --- linux-2.5.73/arch/mips/lib/floppy-std.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/floppy-std.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,5 +1,4 @@ -/* $Id: floppy-std.c,v 1.2 1999/01/04 16:03:51 ralf Exp $ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. @@ -20,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -112,8 +110,8 @@ static unsigned long std_fd_dma_mem_allo } static void std_fd_dma_mem_free(unsigned long addr, unsigned long size) -{ - free_pages(addr, get_order(size)); +{ + free_pages(addr, get_order(size)); } static unsigned long std_fd_drive_type(unsigned long n) --- linux-2.5.73/arch/mips/lib/ide-no.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/ide-no.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,5 +1,4 @@ -/* $Id: ide-no.c,v 1.2 1998/06/30 00:21:54 ralf Exp $ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. @@ -13,7 +12,6 @@ #include #include #include -#include static int no_ide_default_irq(ide_ioreg_t base) { --- linux-2.5.73/arch/mips/lib/ide-std.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/ide-std.c 2003-06-27 15:56:23.000000000 -0700 @@ -11,7 +11,6 @@ #include #include #include -#include #include static int std_ide_default_irq(ide_ioreg_t base) @@ -30,16 +29,11 @@ static int std_ide_default_irq(ide_ioreg static ide_ioreg_t std_ide_default_io_base(int index) { - switch (index) { - case 0: return 0x1f0; - case 1: return 0x170; - case 2: return 0x1e8; - case 3: return 0x168; - case 4: return 0x1e0; - case 5: return 0x160; - default: - return 0; - } + static unsigned long ata_io_base[MAX_HWIFS] = { + 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 + }; + + return ata_io_base[index]; } static void std_ide_init_hwif_ports (hw_regs_t *hw, ide_ioreg_t data_port, --- linux-2.5.73/arch/mips/lib/kbd-no.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,63 +0,0 @@ -/* $Id: kbd-no.c,v 1.1 1998/10/28 12:38:14 ralf Exp $ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Stub keyboard and psaux routines to keep Linux from crashing on machines - * without a keyboard. - * - * Copyright (C) 1998 by Ralf Baechle - */ -#include -#include - -static void no_kbd_request_region(void) -{ - /* No I/O ports are being used on the Indy. */ -} - -static int no_kbd_request_irq(void (*handler)(int, void *, struct pt_regs *)) -{ - return -ENODEV; -} - -static int no_aux_request_irq(void (*handler)(int, void *, struct pt_regs *)) -{ - return -ENODEV; -} - -static void no_aux_free_irq(void) -{ -} - -static unsigned char no_kbd_read_input(void) -{ - return 0; -} - -static void no_kbd_write_output(unsigned char val) -{ -} - -static void no_kbd_write_command(unsigned char val) -{ -} - -static unsigned char no_kbd_read_status(void) -{ - return 0; -} - -struct kbd_ops no_kbd_ops = { - no_kbd_request_region, - no_kbd_request_irq, - - no_aux_request_irq, - no_aux_free_irq, - - no_kbd_read_input, - no_kbd_write_output, - no_kbd_write_command, - no_kbd_read_status -}; --- linux-2.5.73/arch/mips/lib/kbd-std.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,85 +0,0 @@ -/* $Id: kbd-std.c,v 1.2 1999/06/11 14:29:45 ralf Exp $ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Routines for standard PC style keyboards accessible via I/O ports. - * - * Copyright (C) 1998, 1999 by Ralf Baechle - */ -#include -#include -#include -#include -#include - -#define KEYBOARD_IRQ 1 -#define AUX_IRQ 12 - -static void std_kbd_request_region(void) -{ -#ifdef CONFIG_MIPS_ITE8172 - request_region(0x14000060, 16, "keyboard"); -#else - request_region(0x60, 16, "keyboard"); -#endif -} - -static int std_kbd_request_irq(void (*handler)(int, void *, struct pt_regs *)) -{ - return request_irq(KEYBOARD_IRQ, handler, 0, "keyboard", NULL); -} - -static int std_aux_request_irq(void (*handler)(int, void *, struct pt_regs *)) -{ - return request_irq(AUX_IRQ, handler, 0, "PS/2 Mouse", NULL); -} - -static void std_aux_free_irq(void) -{ - free_irq(AUX_IRQ, NULL); -} - -static unsigned char std_kbd_read_input(void) -{ - return inb(KBD_DATA_REG); -} - -static void std_kbd_write_output(unsigned char val) -{ - int status; - - do { - status = inb(KBD_CNTL_REG); - } while (status & KBD_STAT_IBF); - outb(val, KBD_DATA_REG); -} - -static void std_kbd_write_command(unsigned char val) -{ - int status; - - do { - status = inb(KBD_CNTL_REG); - } while (status & KBD_STAT_IBF); - outb(val, KBD_CNTL_REG); -} - -static unsigned char std_kbd_read_status(void) -{ - return inb(KBD_STATUS_REG); -} - -struct kbd_ops std_kbd_ops = { - std_kbd_request_region, - std_kbd_request_irq, - - std_aux_request_irq, - std_aux_free_irq, - - std_kbd_read_input, - std_kbd_write_output, - std_kbd_write_command, - std_kbd_read_status -}; --- linux-2.5.73/arch/mips/lib/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -2,19 +2,17 @@ # Makefile for MIPS-specific library files.. # -EXTRA_AFLAGS := $(CFLAGS) - -lib-y += csum_partial.o csum_partial_copy.o \ - rtc-std.o rtc-no.o memcpy.o memset.o \ - watch.o strlen_user.o strncpy_user.o \ - strnlen_user.o +lib-y += csum_partial.o csum_partial_copy.o memcpy.o \ + memset.o promlib.o rtc-std.o rtc-no.o strlen_user.o \ + strncpy_user.o strnlen_user.o watch.o -ifdef CONFIG_CPU_R3000 - lib-y += r3k_dump_tlb.o +ifeq ($(CONFIG_CPU_R3000)$(CONFIG_CPU_TX39XX),y) + lib-y += r3k_dump_tlb.o else - lib-y += dump_tlb.o + lib-y += dump_tlb.o endif lib-$(CONFIG_BLK_DEV_FD) += floppy-no.o floppy-std.o -lib-$(CONFIG_IDE) += ide-std.o ide-no.o -lib-$(CONFIG_PC_KEYB) += kbd-std.o kbd-no.o +lib-$(subst m,y,$(CONFIG_IDE)) += ide-std.o ide-no.o # needed for ide module + +EXTRA_AFLAGS := $(CFLAGS) --- linux-2.5.73/arch/mips/lib/memcpy.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/memcpy.S 2003-06-27 15:56:23.000000000 -0700 @@ -4,407 +4,468 @@ * for more details. * * Unified implementation of memcpy, memmove and the __copy_user backend. - * For __rmemcpy and memmove an exception is always a kernel bug, therefore - * they're not protected. In order to keep the exception fixup routine - * simple all memory accesses in __copy_user to src rsp. dst are stricly - * incremental. The fixup routine depends on $at not being changed. + * + * Copyright (C) 1998, 99, 2000, 01, 2002 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc. + * Copyright (C) 2002 Broadcom, Inc. + * memcpy/copy_user author: Mark Vandevoorde + * + * Mnemonic names for arguments to memcpy/__copy_user */ +#include #include #include #include +#define dst a0 +#define src a1 +#define len a2 + /* - * The fixup routine for copy_to_user depends on copying strictly in - * increasing order. Gas expands the ulw/usw macros in the wrong order for - * little endian machines, so we cannot depend on them. + * Spec + * + * memcpy copies len bytes from src to dst and sets v0 to dst. + * It assumes that + * - src and dst don't overlap + * - src is readable + * - dst is writable + * memcpy uses the standard calling convention + * + * __copy_user copies up to len bytes from src to dst and sets a2 (len) to + * the number of uncopied bytes due to an exception caused by a read or write. + * __copy_user assumes that src and dst don't overlap, and that the call is + * implementing one of the following: + * copy_to_user + * - src is readable (no exceptions when reading src) + * copy_from_user + * - dst is writable (no exceptions when writing dst) + * __copy_user uses a non-standard calling convention; see + * include/asm-mips/uaccess.h + * + * When an exception happens on a load, the handler must + # ensure that all of the destination buffer is overwritten to prevent + * leaking information to user mode programs. */ -#ifdef __MIPSEB__ -#define uswL swl -#define uswU swr -#define ulwL lwl -#define ulwU lwr -#endif -#ifdef __MIPSEL__ -#define uswL swr -#define uswU swl -#define ulwL lwr -#define ulwU lwl -#endif -#define EX(insn,reg,addr,handler) \ -9: insn reg, addr; \ - .section __ex_table,"a"; \ - PTR 9b, handler; \ - .previous +/* + * Implementation + */ -#define UEX(insn,reg,addr,handler) \ -9: insn ## L reg, addr; \ -10: insn ## U reg, 3 + addr; \ - .section __ex_table,"a"; \ - PTR 9b, handler; \ - PTR 10b, handler; \ +/* + * The exception handler for loads requires that: + * 1- AT contain the address of the byte just past the end of the source + * of the copy, + * 2- src_entry <= src < AT, and + * 3- (dst - src) == (dst_entry - src_entry), + * The _entry suffix denotes values when __copy_user was called. + * + * (1) is set up up by uaccess.h and maintained by not writing AT in copy_user + * (2) is met by incrementing src by the number of bytes copied + * (3) is met by not doing loads between a pair of increments of dst and src + * + * The exception handlers for stores adjust len (if necessary) and return. + * These handlers do not need to overwrite any data. + * + * For __rmemcpy and memmove an exception is always a kernel bug, therefore + * they're not protected. + */ + +#define EXC(inst_reg,addr,handler) \ +9: inst_reg, addr; \ + .section __ex_table,"a"; \ + PTR 9b, handler; \ .previous -/* ascending order, destination aligned */ -#define MOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3) \ - EX(lw, t0, (offset + 0x00)(src), l_fixup); \ - EX(lw, t1, (offset + 0x04)(src), l_fixup); \ - EX(lw, t2, (offset + 0x08)(src), l_fixup); \ - EX(lw, t3, (offset + 0x0c)(src), l_fixup); \ - EX(sw, t0, (offset + 0x00)(dst), s_fixup); \ - EX(sw, t1, (offset + 0x04)(dst), s_fixup); \ - EX(sw, t2, (offset + 0x08)(dst), s_fixup); \ - EX(sw, t3, (offset + 0x0c)(dst), s_fixup); \ - EX(lw, t0, (offset + 0x10)(src), l_fixup); \ - EX(lw, t1, (offset + 0x14)(src), l_fixup); \ - EX(lw, t2, (offset + 0x18)(src), l_fixup); \ - EX(lw, t3, (offset + 0x1c)(src), l_fixup); \ - EX(sw, t0, (offset + 0x10)(dst), s_fixup); \ - EX(sw, t1, (offset + 0x14)(dst), s_fixup); \ - EX(sw, t2, (offset + 0x18)(dst), s_fixup); \ - EX(sw, t3, (offset + 0x1c)(dst), s_fixup) - -/* ascending order, destination unaligned */ -#define UMOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3) \ - EX(lw, t0, (offset + 0x00)(src), l_fixup); \ - EX(lw, t1, (offset + 0x04)(src), l_fixup); \ - EX(lw, t2, (offset + 0x08)(src), l_fixup); \ - EX(lw, t3, (offset + 0x0c)(src), l_fixup); \ - UEX(usw, t0, (offset + 0x00)(dst), s_fixup); \ - UEX(usw, t1, (offset + 0x04)(dst), s_fixup); \ - UEX(usw, t2, (offset + 0x08)(dst), s_fixup); \ - UEX(usw, t3, (offset + 0x0c)(dst), s_fixup); \ - EX(lw, t0, (offset + 0x10)(src), l_fixup); \ - EX(lw, t1, (offset + 0x14)(src), l_fixup); \ - EX(lw, t2, (offset + 0x18)(src), l_fixup); \ - EX(lw, t3, (offset + 0x1c)(src), l_fixup); \ - UEX(usw, t0, (offset + 0x10)(dst), s_fixup); \ - UEX(usw, t1, (offset + 0x14)(dst), s_fixup); \ - UEX(usw, t2, (offset + 0x18)(dst), s_fixup); \ - UEX(usw, t3, (offset + 0x1c)(dst), s_fixup) +/* + * Only on the 64-bit kernel we can made use of 64-bit registers. + */ +#ifdef CONFIG_MIPS64 +#define USE_DOUBLE +#endif + +#ifdef USE_DOUBLE + +#define LOAD ld +#define LOADL ldl +#define LOADR ldr +#define STOREL sdl +#define STORER sdr +#define STORE sd +#define ADD daddu +#define SUB dsubu +#define SRL dsrl +#define SRA dsra +#define SLL dsll +#define SLLV dsllv +#define SRLV dsrlv +#define NBYTES 8 +#define LOG_NBYTES 3 + +/* + * As we are sharing code base with the mips32 tree (which use the o32 ABI + * register definitions). We need to redefine the register definitions from + * the n64 ABI register naming to the o32 ABI register naming. + */ +#undef t0 +#undef t1 +#undef t2 +#undef t3 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 + +#else + +#define LOAD lw +#define LOADL lwl +#define LOADR lwr +#define STOREL swl +#define STORER swr +#define STORE sw +#define ADD addu +#define SUB subu +#define SRL srl +#define SLL sll +#define SRA sra +#define SLLV sllv +#define SRLV srlv +#define NBYTES 4 +#define LOG_NBYTES 2 + +#endif /* USE_DOUBLE */ + +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define LDFIRST LOADR +#define LDREST LOADL +#define STFIRST STORER +#define STREST STOREL +#define SHIFT_DISCARD SLLV +#else +#define LDFIRST LOADL +#define LDREST LOADR +#define STFIRST STOREL +#define STREST STORER +#define SHIFT_DISCARD SRLV +#endif + +#define FIRST(unit) ((unit)*NBYTES) +#define REST(unit) (FIRST(unit)+NBYTES-1) +#define UNIT(unit) FIRST(unit) + +#define ADDRMASK (NBYTES-1) .text .set noreorder .set noat +/* + * A combined memcpy/__copy_user + * __copy_user sets len to 0 for success; else to an upper bound of + * the number of uncopied bytes. + * memcpy sets v0 to dst. + */ .align 5 LEAF(memcpy) /* a0=dst a1=src a2=len */ - move v0, a0 /* return value */ + move v0, dst /* return value */ __memcpy: -EXPORT(__copy_user) - xor t0, a0, a1 - andi t0, t0, 0x3 - move t7, a0 - beqz t0, can_align - sltiu t8, a2, 0x8 - - b memcpy_u_src # bad alignment - move t2, a2 - -can_align: - bnez t8, small_memcpy # < 8 bytes to copy - move t2, a2 - - beqz a2, out - andi t8, a1, 0x1 - -hword_align: - beqz t8, word_align - andi t8, a1, 0x2 - - EX(lb, t0, (a1), l_fixup) - subu a2, a2, 0x1 - EX(sb, t0, (a0), s_fixup) - addu a1, a1, 0x1 - addu a0, a0, 0x1 - andi t8, a1, 0x2 - -word_align: - beqz t8, dword_align - sltiu t8, a2, 56 - - EX(lh, t0, (a1), l_fixup) - subu a2, a2, 0x2 - EX(sh, t0, (a0), s_fixup) - sltiu t8, a2, 56 - addu a0, a0, 0x2 - addu a1, a1, 0x2 - -dword_align: - bnez t8, do_end_words - move t8, a2 - - andi t8, a1, 0x4 - beqz t8, qword_align - andi t8, a1, 0x8 - - EX(lw, t0, 0x00(a1), l_fixup) - subu a2, a2, 0x4 - EX(sw, t0, 0x00(a0), s_fixup) - addu a1, a1, 0x4 - addu a0, a0, 0x4 - andi t8, a1, 0x8 - -qword_align: - beqz t8, oword_align - andi t8, a1, 0x10 - - EX(lw, t0, 0x00(a1), l_fixup) - EX(lw, t1, 0x04(a1), l_fixup) - subu a2, a2, 0x8 - EX(sw, t0, 0x00(a0), s_fixup) - EX(sw, t1, 0x04(a0), s_fixup) - addu a1, a1, 0x8 - andi t8, a1, 0x10 - addu a0, a0, 0x8 - -oword_align: - beqz t8, begin_movement - srl t8, a2, 0x7 - - EX(lw, t3, 0x00(a1), l_fixup) - EX(lw, t4, 0x04(a1), l_fixup) - EX(lw, t0, 0x08(a1), l_fixup) - EX(lw, t1, 0x0c(a1), l_fixup) - EX(sw, t3, 0x00(a0), s_fixup) - EX(sw, t4, 0x04(a0), s_fixup) - EX(sw, t0, 0x08(a0), s_fixup) - EX(sw, t1, 0x0c(a0), s_fixup) - subu a2, a2, 0x10 - addu a1, a1, 0x10 - srl t8, a2, 0x7 - addu a0, a0, 0x10 - -begin_movement: - beqz t8, 0f - andi t2, a2, 0x40 - -move_128bytes: - MOVE_BIGCHUNK(a1, a0, 0x00, t0, t1, t3, t4) - MOVE_BIGCHUNK(a1, a0, 0x20, t0, t1, t3, t4) - MOVE_BIGCHUNK(a1, a0, 0x40, t0, t1, t3, t4) - MOVE_BIGCHUNK(a1, a0, 0x60, t0, t1, t3, t4) - subu t8, t8, 0x01 - addu a1, a1, 0x80 - bnez t8, move_128bytes - addu a0, a0, 0x80 - -0: - beqz t2, 1f - andi t2, a2, 0x20 - -move_64bytes: - MOVE_BIGCHUNK(a1, a0, 0x00, t0, t1, t3, t4) - MOVE_BIGCHUNK(a1, a0, 0x20, t0, t1, t3, t4) - addu a1, a1, 0x40 - addu a0, a0, 0x40 - +FEXPORT(__copy_user) + /* + * Note: dst & src may be unaligned, len may be 0 + * Temps + */ +#define rem t8 + + /* + * The "issue break"s below are very approximate. + * Issue delays for dcache fills will perturb the schedule, as will + * load queue full replay traps, etc. + * + * If len < NBYTES use byte operations. + */ + PREF( 0, 0(src) ) + PREF( 1, 0(dst) ) + sltu t2, len, NBYTES + and t1, dst, ADDRMASK + PREF( 0, 1*32(src) ) + PREF( 1, 1*32(dst) ) + bnez t2, copy_bytes_checklen + and t0, src, ADDRMASK + PREF( 0, 2*32(src) ) + PREF( 1, 2*32(dst) ) + bnez t1, dst_unaligned + nop + bnez t0, src_unaligned_dst_aligned + /* + * use delay slot for fall-through + * src and dst are aligned; need to compute rem + */ +both_aligned: + SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter + beqz t0, cleanup_both_aligned # len < 8*NBYTES + and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES) + PREF( 0, 3*32(src) ) + PREF( 1, 3*32(dst) ) + .align 4 1: - beqz t2, do_end_words - andi t8, a2, 0x1c - -move_32bytes: - MOVE_BIGCHUNK(a1, a0, 0x00, t0, t1, t3, t4) - andi t8, a2, 0x1c - addu a1, a1, 0x20 - addu a0, a0, 0x20 - -do_end_words: - beqz t8, maybe_end_cruft - srl t8, t8, 0x2 - -end_words: - EX(lw, t0, (a1), l_fixup) - subu t8, t8, 0x1 - EX(sw, t0, (a0), s_fixup) - addu a1, a1, 0x4 - bnez t8, end_words - addu a0, a0, 0x4 - -maybe_end_cruft: - andi t2, a2, 0x3 - -small_memcpy: - beqz t2, out - move a2, t2 - -end_bytes: - EX(lb, t0, (a1), l_fixup) - subu a2, a2, 0x1 - EX(sb, t0, (a0), s_fixup) - addu a1, a1, 0x1 - bnez a2, end_bytes - addu a0, a0, 0x1 - -out: jr ra - move a2, zero - -/* ------------------------------------------------------------------------- */ +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) + SUB len, len, 8*NBYTES +EXC( LOAD t4, UNIT(4)(src), l_exc_copy) +EXC( LOAD t7, UNIT(5)(src), l_exc_copy) +EXC( STORE t0, UNIT(0)(dst), s_exc_p8u) +EXC( STORE t1, UNIT(1)(dst), s_exc_p7u) +EXC( LOAD t0, UNIT(6)(src), l_exc_copy) +EXC( LOAD t1, UNIT(7)(src), l_exc_copy) + ADD src, src, 8*NBYTES + ADD dst, dst, 8*NBYTES +EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u) +EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u) +EXC( STORE t4, UNIT(-4)(dst), s_exc_p4u) +EXC( STORE t7, UNIT(-3)(dst), s_exc_p3u) +EXC( STORE t0, UNIT(-2)(dst), s_exc_p2u) +EXC( STORE t1, UNIT(-1)(dst), s_exc_p1u) + PREF( 0, 8*32(src) ) + PREF( 1, 8*32(dst) ) + bne len, rem, 1b + nop -/* Bad, bad. At least try to align the source */ + /* + * len == rem == the number of bytes left to copy < 8*NBYTES + */ +cleanup_both_aligned: + beqz len, done + sltu t0, len, 4*NBYTES + bnez t0, less_than_4units + and rem, len, (NBYTES-1) # rem = len % NBYTES + /* + * len >= 4*NBYTES + */ +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) + SUB len, len, 4*NBYTES + ADD src, src, 4*NBYTES +EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) +EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) +EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) +EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) + beqz len, done + ADD dst, dst, 4*NBYTES +less_than_4units: + /* + * rem = len % NBYTES + */ + beq rem, len, copy_bytes + nop +1: +EXC( LOAD t0, 0(src), l_exc) + ADD src, src, NBYTES + SUB len, len, NBYTES +EXC( STORE t0, 0(dst), s_exc_p1u) + bne rem, len, 1b + ADD dst, dst, NBYTES + + /* + * src and dst are aligned, need to copy rem bytes (rem < NBYTES) + * A loop would do only a byte at a time with possible branch + * mispredicts. Can't do an explicit LOAD dst,mask,or,STORE + * because can't assume read-access to dst. Instead, use + * STREST dst, which doesn't require read access to dst. + * + * This code should perform better than a simple loop on modern, + * wide-issue mips processors because the code has fewer branches and + * more instruction-level parallelism. + */ +#define bits t2 + beqz len, done + ADD t1, dst, len # t1 is just past last byte of dst + li bits, 8*NBYTES + SLL rem, len, 3 # rem = number of bits to keep +EXC( LOAD t0, 0(src), l_exc) + SUB bits, bits, rem # bits = number of bits to discard + SHIFT_DISCARD t0, t0, bits +EXC( STREST t0, -1(t1), s_exc) + jr ra + move len, zero +dst_unaligned: + /* + * dst is unaligned + * t0 = src & ADDRMASK + * t1 = dst & ADDRMASK; T1 > 0 + * len >= NBYTES + * + * Copy enough bytes to align dst + * Set match = (src and dst have same alignment) + */ +#define match rem +EXC( LDFIRST t3, FIRST(0)(src), l_exc) + ADD t2, zero, NBYTES +EXC( LDREST t3, REST(0)(src), l_exc_copy) + SUB t2, t2, t1 # t2 = number of bytes copied + xor match, t0, t1 +EXC( STFIRST t3, FIRST(0)(dst), s_exc) + beq len, t2, done + SUB len, len, t2 + ADD dst, dst, t2 + beqz match, both_aligned + ADD src, src, t2 + +src_unaligned_dst_aligned: + SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter + PREF( 0, 3*32(src) ) + beqz t0, cleanup_src_unaligned + and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES + PREF( 1, 3*32(dst) ) +1: +/* + * Avoid consecutive LD*'s to the same register since some mips + * implementations can't issue them in the same cycle. + * It's OK to load FIRST(N+1) before REST(N) because the two addresses + * are to the same unit (unless src is aligned, but it's not). + */ +EXC( LDFIRST t0, FIRST(0)(src), l_exc) +EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) + SUB len, len, 4*NBYTES +EXC( LDREST t0, REST(0)(src), l_exc_copy) +EXC( LDREST t1, REST(1)(src), l_exc_copy) +EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) +EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) +EXC( LDREST t2, REST(2)(src), l_exc_copy) +EXC( LDREST t3, REST(3)(src), l_exc_copy) + PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed) + ADD src, src, 4*NBYTES +#ifdef CONFIG_CPU_SB1 + nop # improves slotting +#endif +EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) +EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) +EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) +EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) + PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed) + bne len, rem, 1b + ADD dst, dst, 4*NBYTES + +cleanup_src_unaligned: + beqz len, done + and rem, len, NBYTES-1 # rem = len % NBYTES + beq rem, len, copy_bytes + nop +1: +EXC( LDFIRST t0, FIRST(0)(src), l_exc) +EXC( LDREST t0, REST(0)(src), l_exc_copy) + ADD src, src, NBYTES + SUB len, len, NBYTES +EXC( STORE t0, 0(dst), s_exc_p1u) + bne len, rem, 1b + ADD dst, dst, NBYTES -memcpy_u_src: - bnez t8, small_memcpy # < 8 bytes? - move t2, a2 - - addiu t0, a1, 7 # t0: how much to align - ori t0, 7 - xori t0, 7 - subu t0, a1 - - UEX(ulw, t1, 0(a1), l_fixup) # dword alignment - UEX(ulw, t2, 4(a1), l_fixup) - UEX(usw, t1, 0(a0), s_fixup) - UEX(usw, t2, 4(a0), s_fixup) - - addu a1, t0 # src - addu a0, t0 # dst - subu a2, t0 # len - - sltiu t8, a2, 56 - bnez t8, u_do_end_words - andi t8, a2, 0x3c - - andi t8, a1, 8 # now qword aligned? - -u_qword_align: - beqz t8, u_oword_align - andi t8, a1, 0x10 - - EX(lw, t0, 0x00(a1), l_fixup) - EX(lw, t1, 0x04(a1), l_fixup) - subu a2, a2, 0x8 - UEX(usw, t0, 0x00(a0), s_fixup) - UEX(usw, t1, 0x04(a0), s_fixup) - addu a1, a1, 0x8 - andi t8, a1, 0x10 - addu a0, a0, 0x8 - -u_oword_align: - beqz t8, u_begin_movement - srl t8, a2, 0x7 - - EX(lw, t3, 0x08(a1), l_fixup) - EX(lw, t4, 0x0c(a1), l_fixup) - EX(lw, t0, 0x00(a1), l_fixup) - EX(lw, t1, 0x04(a1), l_fixup) - UEX(usw, t3, 0x08(a0), s_fixup) - UEX(usw, t4, 0x0c(a0), s_fixup) - UEX(usw, t0, 0x00(a0), s_fixup) - UEX(usw, t1, 0x04(a0), s_fixup) - subu a2, a2, 0x10 - addu a1, a1, 0x10 - srl t8, a2, 0x7 - addu a0, a0, 0x10 - -u_begin_movement: - beqz t8, 0f - andi t2, a2, 0x40 - -u_move_128bytes: - UMOVE_BIGCHUNK(a1, a0, 0x00, t0, t1, t3, t4) - UMOVE_BIGCHUNK(a1, a0, 0x20, t0, t1, t3, t4) - UMOVE_BIGCHUNK(a1, a0, 0x40, t0, t1, t3, t4) - UMOVE_BIGCHUNK(a1, a0, 0x60, t0, t1, t3, t4) - subu t8, t8, 0x01 - addu a1, a1, 0x80 - bnez t8, u_move_128bytes - addu a0, a0, 0x80 - -0: - beqz t2, 1f - andi t2, a2, 0x20 - -u_move_64bytes: - UMOVE_BIGCHUNK(a1, a0, 0x00, t0, t1, t3, t4) - UMOVE_BIGCHUNK(a1, a0, 0x20, t0, t1, t3, t4) - addu a1, a1, 0x40 - addu a0, a0, 0x40 +copy_bytes_checklen: + beqz len, done + nop +copy_bytes: + /* 0 < len < NBYTES */ +#define COPY_BYTE(N) \ +EXC( lb t0, N(src), l_exc); \ + SUB len, len, 1; \ + beqz len, done; \ +EXC( sb t0, N(dst), s_exc_p1) + + COPY_BYTE(0) + COPY_BYTE(1) +#ifdef USE_DOUBLE + COPY_BYTE(2) + COPY_BYTE(3) + COPY_BYTE(4) + COPY_BYTE(5) +#endif +EXC( lb t0, NBYTES-2(src), l_exc) + SUB len, len, 1 + jr ra +EXC( sb t0, NBYTES-2(dst), s_exc_p1) +done: + jr ra + nop + END(memcpy) +l_exc_copy: + /* + * Copy bytes from src until faulting load address (or until a + * lb faults) + * + * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28) + * may be more than a byte beyond the last address. + * Hence, the lb below may get an exception. + * + * Assumes src < THREAD_BUADDR($28) + */ + LOAD t0, TI_TASK($28) + LOAD t0, THREAD_BUADDR(t0) 1: - beqz t2, u_do_end_words - andi t8, a2, 0x1c +EXC( lb t1, 0(src), l_exc) + ADD src, src, 1 + sb t1, 0(dst) # can't fault -- we're copy_from_user + bne src, t0, 1b + ADD dst, dst, 1 +l_exc: + LOAD t0, THREAD_BUADDR($28) # t0 is just past last good address + LOAD t0, THREAD_BUADDR(t0) + nop + SUB len, AT, t0 # len number of uncopied bytes + /* + * Here's where we rely on src and dst being incremented in tandem, + * See (3) above. + * dst += (fault addr - src) to put dst at first byte to clear + */ + ADD dst, t0 # compute start address in a1 + SUB dst, src + /* + * Clear len bytes starting at dst. Can't call __bzero because it + * might modify len. An inefficient loop for these rare times... + */ + beqz len, done + SUB src, len, 1 +1: sb zero, 0(dst) + ADD dst, dst, 1 + bnez src, 1b + SUB src, src, 1 + jr ra + nop -u_move_32bytes: - UMOVE_BIGCHUNK(a1, a0, 0x00, t0, t1, t3, t4) - andi t8, a2, 0x1c - addu a1, a1, 0x20 - addu a0, a0, 0x20 - -u_do_end_words: - beqz t8, u_maybe_end_cruft - srl t8, t8, 0x2 - -u_end_words: - EX(lw, t0, 0x00(a1), l_fixup) - subu t8, t8, 0x1 - UEX(usw, t0, 0x00(a0), s_fixup) - addu a1, a1, 0x4 - bnez t8, u_end_words - addu a0, a0, 0x4 - -u_maybe_end_cruft: - andi t2, a2, 0x3 - -u_cannot_optimize: - beqz t2, out - move a2, t2 - -u_end_bytes: - EX(lb, t0, (a1), l_fixup) - subu a2, a2, 0x1 - EX(sb, t0, (a0), s_fixup) - addu a1, a1, 0x1 - bnez a2, u_end_bytes - addu a0, a0, 0x1 - jr ra - move a2, zero - END(memcpy) +#define SEXC(n) \ +s_exc_p ## n ## u: \ + jr ra; \ + ADD len, len, n*NBYTES + +SEXC(8) +SEXC(7) +SEXC(6) +SEXC(5) +SEXC(4) +SEXC(3) +SEXC(2) +SEXC(1) -/* descending order, destination aligned */ -#define RMOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3) \ - lw t0, (offset + 0x10)(src); \ - lw t1, (offset + 0x14)(src); \ - lw t2, (offset + 0x18)(src); \ - lw t3, (offset + 0x1c)(src); \ - sw t0, (offset + 0x10)(dst); \ - sw t1, (offset + 0x14)(dst); \ - sw t2, (offset + 0x18)(dst); \ - sw t3, (offset + 0x1c)(dst); \ - lw t0, (offset + 0x00)(src); \ - lw t1, (offset + 0x04)(src); \ - lw t2, (offset + 0x08)(src); \ - lw t3, (offset + 0x0c)(src); \ - sw t0, (offset + 0x00)(dst); \ - sw t1, (offset + 0x04)(dst); \ - sw t2, (offset + 0x08)(dst); \ - sw t3, (offset + 0x0c)(dst) - -/* descending order, destination ununaligned */ -#define RUMOVE_BIGCHUNK(src, dst, offset, t0, t1, t2, t3) \ - lw t0, (offset + 0x10)(src); \ - lw t1, (offset + 0x14)(src); \ - lw t2, (offset + 0x18)(src); \ - lw t3, (offset + 0x1c)(src); \ - usw t0, (offset + 0x10)(dst); \ - usw t1, (offset + 0x14)(dst); \ - usw t2, (offset + 0x18)(dst); \ - usw t3, (offset + 0x1c)(dst); \ - lw t0, (offset + 0x00)(src); \ - lw t1, (offset + 0x04)(src); \ - lw t2, (offset + 0x08)(src); \ - lw t3, (offset + 0x0c)(src); \ - usw t0, (offset + 0x00)(dst); \ - usw t1, (offset + 0x04)(dst); \ - usw t2, (offset + 0x08)(dst); \ - usw t3, (offset + 0x0c)(dst) +s_exc_p1: + jr ra + ADD len, len, 1 +s_exc: + jr ra + nop .align 5 LEAF(memmove) - addu t0, a0, a2 + ADD t0, a0, a2 + ADD t1, a1, a2 sltu t0, a1, t0 # dst + len <= src -> memcpy - addu t1, a1, a2 sltu t1, a0, t1 # dst >= src + len -> memcpy and t0, t1 beqz t0, __memcpy @@ -412,159 +473,21 @@ LEAF(memmove) beqz a2, r_out END(memmove) + /* fall through to __rmemcpy */ LEAF(__rmemcpy) /* a0=dst a1=src a2=len */ - sltu t0, a1, a0 + sltu t0, a1, a0 beqz t0, r_end_bytes_up # src >= dst nop - addu a0, a2 # dst = dst + len - addu a1, a2 # src = src + len - -#if 0 /* Horror fix */ - xor t0, a0, a1 - andi t0, t0, 0x3 - move t7, a0 - beqz t0, r_can_align - sltiu t8, a2, 0x8 - - b r_memcpy_u_src # bad alignment - move t2, a2 - -r_can_align: - bnez t8, r_small_memcpy # < 8 bytes to copy - move t2, a2 - - beqz a2, r_out - andi t8, a1, 0x1 - -r_hword_align: - beqz t8, r_word_align - andi t8, a1, 0x2 - - lb t0, -1(a1) - subu a2, a2, 0x1 - sb t0, -1(a0) - subu a1, a1, 0x1 - subu a0, a0, 0x1 - andi t8, a1, 0x2 - -r_word_align: - beqz t8, r_dword_align - sltiu t8, a2, 56 - - lh t0, -2(a1) - subu a2, a2, 0x2 - sh t0, -2(a0) - sltiu t8, a2, 56 - subu a0, a0, 0x2 - subu a1, a1, 0x2 - -r_dword_align: - bnez t8, r_do_end_words - move t8, a2 - - andi t8, a1, 0x4 - beqz t8, r_qword_align - andi t8, a1, 0x8 - - lw t0, -4(a1) - subu a2, a2, 0x4 - sw t0, -4(a0) - subu a1, a1, 0x4 - subu a0, a0, 0x4 - andi t8, a1, 0x8 - -r_qword_align: - beqz t8, r_oword_align - andi t8, a1, 0x10 - - subu a1, a1, 0x8 - lw t0, 0x04(a1) - lw t1, 0x00(a1) - subu a0, a0, 0x8 - sw t0, 0x04(a0) - sw t1, 0x00(a0) - subu a2, a2, 0x8 - - andi t8, a1, 0x10 - -r_oword_align: - beqz t8, r_begin_movement - srl t8, a2, 0x7 - - subu a1, a1, 0x10 - lw t3, 0x08(a1) # assumes subblock ordering - lw t4, 0x0c(a1) - lw t0, 0x00(a1) - lw t1, 0x04(a1) - subu a0, a0, 0x10 - sw t3, 0x08(a0) - sw t4, 0x0c(a0) - sw t0, 0x00(a0) - sw t1, 0x04(a0) - subu a2, a2, 0x10 - srl t8, a2, 0x7 - -r_begin_movement: - beqz t8, 0f - andi t2, a2, 0x40 - -r_move_128bytes: - RMOVE_BIGCHUNK(a1, a0, -0x80, t0, t1, t3, t4) - RMOVE_BIGCHUNK(a1, a0, -0x60, t0, t1, t3, t4) - RMOVE_BIGCHUNK(a1, a0, -0x40, t0, t1, t3, t4) - RMOVE_BIGCHUNK(a1, a0, -0x20, t0, t1, t3, t4) - subu t8, t8, 0x01 - subu a1, a1, 0x80 - bnez t8, r_move_128bytes - subu a0, a0, 0x80 - -0: - beqz t2, 1f - andi t2, a2, 0x20 - -r_move_64bytes: - subu a1, a1, 0x40 - subu a0, a0, 0x40 - RMOVE_BIGCHUNK(a1, a0, 0x20, t0, t1, t3, t4) - RMOVE_BIGCHUNK(a1, a0, 0x00, t0, t1, t3, t4) - -1: - beqz t2, r_do_end_words - andi t8, a2, 0x1c - -r_move_32bytes: - subu a1, a1, 0x20 - subu a0, a0, 0x20 - RMOVE_BIGCHUNK(a1, a0, 0x00, t0, t1, t3, t4) - andi t8, a2, 0x1c - -r_do_end_words: - beqz t8, r_maybe_end_cruft - srl t8, t8, 0x2 - -r_end_words: - lw t0, -4(a1) - subu t8, t8, 0x1 - sw t0, -4(a0) - subu a1, a1, 0x4 - bnez t8, r_end_words - subu a0, a0, 0x4 - -r_maybe_end_cruft: - andi t2, a2, 0x3 - -r_small_memcpy: - beqz t2, r_out - move a2, t2 -#endif /* Horror fix */ + ADD a0, a2 # dst = dst + len + ADD a1, a2 # src = src + len r_end_bytes: lb t0, -1(a1) - subu a2, a2, 0x1 + SUB a2, a2, 0x1 sb t0, -1(a0) - subu a1, a1, 0x1 + SUB a1, a1, 0x1 bnez a2, r_end_bytes - subu a0, a0, 0x1 + SUB a0, a0, 0x1 r_out: jr ra @@ -572,148 +495,12 @@ r_out: r_end_bytes_up: lb t0, (a1) - subu a2, a2, 0x1 + SUB a2, a2, 0x1 sb t0, (a0) - addu a1, a1, 0x1 + ADD a1, a1, 0x1 bnez a2, r_end_bytes_up - addu a0, a0, 0x1 + ADD a0, a0, 0x1 jr ra move a2, zero - -#if 0 /* Horror fix */ -/* ------------------------------------------------------------------------- */ - -/* Bad, bad. At least try to align the source */ - -r_memcpy_u_src: - bnez t8, r_small_memcpy # < 8 bytes? - move t2, a2 - - andi t0, a1, 7 # t0: how much to align - - ulw t1, -8(a1) # dword alignment - ulw t2, -4(a1) - usw t1, -8(a0) - usw t2, -4(a0) - - subu a1, t0 # src - subu a0, t0 # dst - subu a2, t0 # len - - sltiu t8, a2, 56 - bnez t8, ru_do_end_words - andi t8, a2, 0x3c - - andi t8, a1, 8 # now qword aligned? - -ru_qword_align: - beqz t8, ru_oword_align - andi t8, a1, 0x10 - - subu a1, a1, 0x8 - lw t0, 0x00(a1) - lw t1, 0x04(a1) - subu a0, a0, 0x8 - usw t0, 0x00(a0) - usw t1, 0x04(a0) - subu a2, a2, 0x8 - - andi t8, a1, 0x10 - -ru_oword_align: - beqz t8, ru_begin_movement - srl t8, a2, 0x7 - - subu a1, a1, 0x10 - lw t3, 0x08(a1) # assumes subblock ordering - lw t4, 0x0c(a1) - lw t0, 0x00(a1) - lw t1, 0x04(a1) - subu a0, a0, 0x10 - usw t3, 0x08(a0) - usw t4, 0x0c(a0) - usw t0, 0x00(a0) - usw t1, 0x04(a0) - subu a2, a2, 0x10 - - srl t8, a2, 0x7 - -ru_begin_movement: - beqz t8, 0f - andi t2, a2, 0x40 - -ru_move_128bytes: - RUMOVE_BIGCHUNK(a1, a0, -0x80, t0, t1, t3, t4) - RUMOVE_BIGCHUNK(a1, a0, -0x60, t0, t1, t3, t4) - RUMOVE_BIGCHUNK(a1, a0, -0x40, t0, t1, t3, t4) - RUMOVE_BIGCHUNK(a1, a0, -0x20, t0, t1, t3, t4) - subu t8, t8, 0x01 - subu a1, a1, 0x80 - bnez t8, ru_move_128bytes - subu a0, a0, 0x80 - -0: - beqz t2, 1f - andi t2, a2, 0x20 - -ru_move_64bytes: - subu a1, a1, 0x40 - subu a0, a0, 0x40 - RUMOVE_BIGCHUNK(a1, a0, 0x20, t0, t1, t3, t4) - RUMOVE_BIGCHUNK(a1, a0, 0x00, t0, t1, t3, t4) - -1: - beqz t2, ru_do_end_words - andi t8, a2, 0x1c - -ru_move_32bytes: - subu a1, a1, 0x20 - subu a0, a0, 0x20 - RUMOVE_BIGCHUNK(a1, a0, 0x00, t0, t1, t3, t4) - andi t8, a2, 0x1c - -ru_do_end_words: - beqz t8, ru_maybe_end_cruft - srl t8, t8, 0x2 - -ru_end_words: - lw t0, -4(a1) - usw t0, -4(a0) - subu t8, t8, 0x1 - subu a1, a1, 0x4 - bnez t8, ru_end_words - subu a0, a0, 0x4 - -ru_maybe_end_cruft: - andi t2, a2, 0x3 - -ru_cannot_optimize: - beqz t2, r_out - move a2, t2 - -ru_end_bytes: - lb t0, -1(a1) - subu a2, a2, 0x1 - sb t0, -1(a0) - subu a1, a1, 0x1 - bnez a2, ru_end_bytes - subu a0, a0, 0x1 - - jr ra - move a2, zero -#endif /* Horror fix */ END(__rmemcpy) - -l_fixup: # clear the rest of the buffer - lw t0, THREAD_BUADDR($28) - nop - subu a2, AT, t0 # a2 bytes to go - addu a0, t0 # compute start address in a1 - subu a0, a1 - j __bzero - move a1, zero - -s_fixup: - jr ra - nop --- linux-2.5.73/arch/mips/lib/memset.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/memset.S 2003-06-27 15:56:23.000000000 -0700 @@ -54,7 +54,6 @@ LEAF(memset) 1: EXPORT(__bzero) - .type __bzero, @function sltiu t0, a2, 4 /* very small region? */ bnez t0, small_memset andi t0, a0, 3 /* aligned? */ @@ -84,13 +83,17 @@ EXPORT(__bzero) .set noreorder memset_partial: - la t1, 2f /* where to start */ + PTR_LA t1, 2f /* where to start */ subu t1, t0 jr t1 addu a0, t0 /* dest ptr */ + .set push + .set noreorder + .set nomacro F_FILL64(a0, -64, a1, partial_fixup) /* ... but first do wrds ... */ -2: andi a2, 3 /* 0 <= n <= 3 to go */ +2: .set pop + andi a2, 3 /* 0 <= n <= 3 to go */ beqz a2, 1f addu a0, a2 /* What's left */ @@ -120,14 +123,16 @@ first_fixup: nop fwd_fixup: - lw t0, THREAD_BUADDR($28) + lw t0, TI_TASK($28) + lw t0, THREAD_BUADDR(t0) andi a2, 0x3f addu a2, t1 jr ra subu a2, t0 partial_fixup: - lw t0, THREAD_BUADDR($28) + lw t0, TI_TASK($28) + lw t0, THREAD_BUADDR(t0) andi a2, 3 addu a2, t1 jr ra --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/lib/promlib.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,24 @@ +#include +#include + +extern void prom_putchar(char); + +void prom_printf(char *fmt, ...) +{ + va_list args; + char ppbuf[1024]; + char *bptr; + + va_start(args, fmt); + vsprintf(ppbuf, fmt, args); + + bptr = ppbuf; + + while (*bptr != 0) { + if (*bptr == '\n') + prom_putchar('\r'); + + prom_putchar(*bptr++); + } + va_end(args); +} --- linux-2.5.73/arch/mips/lib/r3k_dump_tlb.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/r3k_dump_tlb.c 2003-06-27 15:56:23.000000000 -0700 @@ -12,11 +12,12 @@ #include #include +#include #include #include #include -#define mips_tlb_entries 64 +extern int r3k_have_wired_reg; /* defined in tlb-r3k.c */ void dump_tlb(int first, int last) @@ -25,18 +26,18 @@ dump_tlb(int first, int last) unsigned int asid; unsigned long entryhi, entrylo0; - asid = get_entryhi() & 0xfc0; + asid = read_c0_entryhi() & 0xfc0; for(i=first;i<=last;i++) { - write_32bit_cp0_register(CP0_INDEX, i<<8); + write_c0_index(i<<8); __asm__ __volatile__( ".set\tnoreorder\n\t" "tlbr\n\t" "nop\n\t" ".set\treorder"); - entryhi = read_32bit_cp0_register(CP0_ENTRYHI); - entrylo0 = read_32bit_cp0_register(CP0_ENTRYLO0); + entryhi = read_c0_entryhi(); + entrylo0 = read_c0_entrylo0(); /* Unused entries have a virtual address of KSEG0. */ if ((entryhi & 0xffffe000) != 0x80000000 @@ -59,22 +60,22 @@ dump_tlb(int first, int last) } printk("\n"); - set_entryhi(asid); + write_c0_entryhi(asid); } void dump_tlb_all(void) { - dump_tlb(0, mips_tlb_entries - 1); + dump_tlb(0, current_cpu_data.tlbsize - 1); } void dump_tlb_wired(void) { - int wired = 7; + int wired = r3k_have_wired_reg ? read_c0_wired() : 8; printk("Wired: %d", wired); - dump_tlb(0, read_32bit_cp0_register(CP0_WIRED)); + dump_tlb(0, wired - 1); } void @@ -84,11 +85,11 @@ dump_tlb_addr(unsigned long addr) int index; local_irq_save(flags); - oldpid = get_entryhi() & 0xff; - set_entryhi((addr & PAGE_MASK) | oldpid); + oldpid = read_c0_entryhi() & 0xff; + write_c0_entryhi((addr & PAGE_MASK) | oldpid); tlb_probe(); - index = get_index(); - set_entryhi(oldpid); + index = read_c0_index(); + write_c0_entryhi(oldpid); local_irq_restore(flags); if (index < 0) { @@ -103,7 +104,8 @@ dump_tlb_addr(unsigned long addr) void dump_tlb_nonwired(void) { - dump_tlb(8, mips_tlb_entries - 1); + int wired = r3k_have_wired_reg ? read_c0_wired() : 8; + dump_tlb(wired, current_cpu_data.tlbsize - 1); } void --- linux-2.5.73/arch/mips/lib/strlen_user.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/strlen_user.S 2003-06-27 15:56:23.000000000 -0700 @@ -1,5 +1,4 @@ -/* $Id: strlen_user.S,v 1.3 1999/08/21 22:19:11 ralf Exp $ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. @@ -24,22 +23,18 @@ * Return 0 for error */ LEAF(__strlen_user_asm) - lw v0, THREAD_CURDS($28) # pointer ok? + lw v0, TI_ADDR_LIMIT($28) # pointer ok? and v0, a0 bltz v0, fault -EXPORT(__strlen_user_nocheck_asm) +FEXPORT(__strlen_user_nocheck_asm) move v0, a0 1: EX(lb, t0, (v0), fault) addiu v0, 1 bnez t0, 1b subu v0, a0 jr ra - END(__strlen_user_nocheck_asm) - - .section __ex_table,"a" - PTR 1b, fault - .previous + END(__strlen_user_asm) fault: move v0, zero jr ra --- linux-2.5.73/arch/mips/lib/strncpy_user.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/strncpy_user.S 2003-06-27 15:56:23.000000000 -0700 @@ -1,5 +1,4 @@ -/* $Id: strncpy_user.S,v 1.3 1999/08/21 22:19:11 ralf Exp $ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. @@ -29,7 +28,7 @@ */ LEAF(__strncpy_from_user_asm) - lw v0, THREAD_CURDS($28) # pointer ok? + lw v0, TI_ADDR_LIMIT($28) # pointer ok? and v0, a1 bltz v0, fault --- linux-2.5.73/arch/mips/lib/strnlen_user.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/strnlen_user.S 2003-06-27 15:56:23.000000000 -0700 @@ -1,5 +1,4 @@ -/* $Id: strnlen_user.S,v 1.2 1999/11/19 20:35:21 ralf Exp $ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. @@ -28,11 +27,11 @@ * bytes. There's nothing secret there ... */ LEAF(__strnlen_user_asm) - lw v0, THREAD_CURDS($28) # pointer ok? + lw v0, TI_ADDR_LIMIT($28) # pointer ok? and v0, a0 bltz v0, fault -EXPORT(__strnlen_user_nocheck_asm) +FEXPORT(__strnlen_user_nocheck_asm) .type __strnlen_user_nocheck_asm,@function move v0, a0 addu a1, a0 # stop pointer @@ -46,9 +45,5 @@ EXPORT(__strnlen_user_nocheck_asm) jr ra END(__strnlen_user_asm) - .section __ex_table,"a" - PTR 1b, fault - .previous - fault: move v0, zero jr ra --- linux-2.5.73/arch/mips/lib/tinycon.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/lib/tinycon.c 2003-06-27 15:56:23.000000000 -0700 @@ -38,7 +38,7 @@ void init_console(void) cursor_y = 0; vram_addr = (unsigned short *)0xb00b8000; - + console_needs_init = 0; } @@ -87,7 +87,7 @@ scroll(void) *(caddr++) = *(caddr + size_x); /* blank last line */ - + caddr = vram_addr + (size_x * (size_y-1)); for(i=0; i /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi) # # CPU-dependent compiler/assembler options for optimization. # -ifdef CONFIG_CPU_R3000 -GCCFLAGS += -mcpu=r3000 -mips1 -endif -ifdef CONFIG_CPU_R6000 -GCCFLAGS += -mcpu=r6000 -mips2 -Wa,--trap -endif -ifdef CONFIG_CPU_R4300 -GCCFLAGS += -mcpu=r4300 -mips2 -Wa,--trap -endif -ifdef CONFIG_CPU_VR41XX -GCCFLAGS += -mcpu=r4600 -mips2 -Wa,--trap -endif -ifdef CONFIG_CPU_R4X00 -GCCFLAGS += -mcpu=r4600 -mips2 -Wa,--trap -endif -ifdef CONFIG_CPU_MIPS32 -GCCFLAGS += -mcpu=r4600 -mips2 -Wa,--trap -endif -ifdef CONFIG_CPU_MIPS64 -GCCFLAGS += -mcpu=r4600 -mips2 -Wa,--trap -endif -ifdef CONFIG_CPU_R5000 -GCCFLAGS += -mcpu=r5000 -mips2 -Wa,--trap -endif -ifdef CONFIG_CPU_R5432 -GCCFLAGS += -mcpu=r5000 -mips2 -Wa,--trap -endif -ifdef CONFIG_CPU_NEVADA +cflags-$(CONFIG_CPU_R3000) += -mcpu=r3000 -mips1 +cflags-$(CONFIG_CPU_TX39XX) += -mcpu=r3000 -mips1 +cflags-$(CONFIG_CPU_R6000) += -mcpu=r6000 -mips2 -Wa,--trap +cflags-$(CONFIG_CPU_R4300) += -mcpu=r4300 -mips2 -Wa,--trap +cflags-$(CONFIG_CPU_VR41XX) += -mcpu=r4600 -mips2 -Wa,--trap +cflags-$(CONFIG_CPU_R4X00) += -mcpu=r4600 -mips2 -Wa,--trap +cflags-$(CONFIG_CPU_TX49XX) += -mcpu=r4600 -mips2 -Wa,--trap +cflags-$(CONFIG_CPU_MIPS32) += -mcpu=r4600 -mips2 -Wa,--trap +cflags-$(CONFIG_CPU_MIPS64) += -mcpu=r4600 -mips2 -Wa,--trap +cflags-$(CONFIG_CPU_R5000) += -mcpu=r5000 -mips2 -Wa,--trap +cflags-$(CONFIG_CPU_R5432) += -mcpu=r5000 -mips2 -Wa,--trap # Cannot use -mmad with currently recommended tools -GCCFLAGS += -mcpu=r5000 -mips2 -Wa,--trap -endif -ifdef CONFIG_CPU_RM7000 -GCCFLAGS += -mcpu=r5000 -mips2 -Wa,--trap -endif +cflags-$(CONFIG_CPU_NEVADA) += -mcpu=r5000 -mips2 -Wa,--trap +cflags-$(CONFIG_CPU_RM7000) += -mcpu=r5000 -mips2 -Wa,--trap +cflags-$(CONFIG_CPU_RM7000) += $(call check_gcc, -mcpu=r7000, -mcpu=r5000) \ + -mips2 -Wa,--trap +cflags-$(CONFIG_CPU_SB1) += $(call check_gcc, -mcpu=sb1, -mcpu=r8000) \ + -mips2 -Wa,--trap ifdef CONFIG_CPU_SB1 -GCCFLAGS += -mcpu=sb1 -mips2 -Wa,--trap +ifdef CONFIG_SB1_PASS_1_WORKAROUNDS +MODFLAGS += -msb1-pass1-workarounds endif +endif + +AFLAGS += $(cflags-y) +CFLAGS += $(cflags-y) -GCCFLAGS += -pipe -CFLAGS := -I $(TOPDIR)/include/asm/gcc $(CFLAGS) $(GCCFLAGS) -AFLAGS += $(GCCFLAGS) -ASFLAGS += $(GCCFLAGS) +# +# ramdisk/initrd support +# You need a compressed ramdisk image, named ramdisk.gz in +# arch/mips/ramdisk +# +ifdef CONFIG_EMBEDDED_RAMDISK +CORE_FILES += arch/mips/ramdisk/ramdisk.o +SUBDIRS += arch/mips/ramdisk +endif # -# We unconditionally build the math emulator +# Firmware support # -core-y += arch/mips/math-emu/ +libs-$(CONFIG_ARC) += arch/mips/arc/ +libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/ # # Board-dependent options and extra files # -ifdef CONFIG_ALGOR_P4032 -core-y += arch/mips/algor/ -LOADADDR += 0x80000000 -endif # -# DECstation family +# Acer PICA 61, Mips Magnum 4000 and Olivetti M700. # -ifdef CONFIG_DECSTATION -core-y += arch/mips/dec/ -libs-y += arch/mips/dec/prom/ -LOADADDR += 0x80040000 -endif +core-$(CONFIG_MIPS_JAZZ) += arch/mips/jazz/ +load-$(CONFIG_MIPS_JAZZ) += 0x80080000 -ifdef CONFIG_MIPS_ATLAS -core-y += arch/mips/mips-boards/atlas/ arch/mips/mips-boards/generic/ -LOADADDR += 0x80100000 -endif -ifdef CONFIG_MIPS_MALTA -core-y += arch/mips/mips-boards/malta/ arch/mips/mips-boards/generic/ -LOADADDR += 0x80100000 -endif +# +# Au1500 (Alchemy Semi PB1500) eval board +# +core-$(CONFIG_MIPS_PB1500) += arch/mips/au1000/common/ +libs-$(CONFIG_MIPS_PB1500) += arch/mips/au1000/pb1500/ +load-$(CONFIG_MIPS_PB1500) += 0x80100000 # -# Acer PICA 61, Mips Magnum 4000 and Olivetti M700. +# Baget/MIPS # -ifdef CONFIG_MIPS_JAZZ -core-y += arch/mips/jazz/ -libs-y += arch/mips/arc/ -LOADADDR += 0x80080000 -endif +libs-$(CONFIG_BAGET_MIPS) += arch/mips/baget/ arch/mips/baget/prom/ +load-$(CONFIG_BAGET_MIPS) += 0x80001000 -ifdef CONFIG_SNI_RM200_PCI -core-y += arch/mips/sni/ -libs-y += arch/mips/arc/ -LOADADDR += 0x80080000 -endif +# +# Cobalt Server +# +core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/ +load-$(CONFIG_MIPS_COBALT) += 0x80080000 -ifdef CONFIG_SGI_IP22 -core-y += arch/mips/sgi/kernel/ -libs-y += arch/mips/arc/ -# -# Set LOADADDR to >= 0x88069000 if you want to leave space for symmon, -# 0x88002000 for production kernels. Note that the value must be -# 8kb aligned or the handling of the current variable will break. # -LOADADDR += 0x88002000 -endif +# DECstation family +# +core-$(CONFIG_DECSTATION) += arch/mips/dec/ +libs-$(CONFIG_DECSTATION) += arch/mips/dec/prom/ +load-$(CONFIG_DECSTATION) += 0x80040000 +CLEAN_FILES += drivers/tc/lk201-map.c # -# Baget/MIPS +# Galileo EV64120 Board # -ifdef CONFIG_BAGET_MIPS -core-y += arch/mips/baget/ -libs-y += arch/mips/baget/prom/ -LOADADDR += 0x80001000 -endif +core-$(CONFIG_MIPS_EV64120) += arch/mips/galileo-boards/ev64120/ +load-$(CONFIG_MIPS_EV64120) += 0x80100000 # -# NEC DDB Vrc-5074 +# Galileo EV96100 Board # -ifdef CONFIG_DDB5074 -core-y += arch/mips/ddb5074/ -LOADADDR += 0x80080000 -endif +core-$(CONFIG_MIPS_EV96100) += arch/mips/galileo-boards/generic/ \ + arch/mips/galileo-boards/ev96100/ +load-$(CONFIG_MIPS_EV96100) += 0x80100000 # +# Globespan IVR eval board with QED 5231 CPU # -# NEC DDB Vrc-5476 +core-$(CONFIG_ITE_BOARD_GEN) += arch/mips/ite-boards/generic/ +core-$(CONFIG_MIPS_IVR) += arch/mips/ite-boards/ivr/ +load-$(CONFIG_MIPS_IVR) += 0x80100000 + # -ifdef CONFIG_DDB5476 -core-y += arch/mips/ddb5476/ -LOADADDR += 0x80080000 -endif +# HP LaserJet +# +core-$(CONFIG_HP_LASERJET) += arch/mips/hp-lj/ +load-$(CONFIG_HP_LASERJET) += 0x80030000 # +# ITE 8172 eval board with QED 5231 CPU # -# NEC DDB Vrc-5477 +core-$(CONFIG_MIPS_ITE8172) += arch/mips/ite-boards/qed-4n-s01b/ +load-$(CONFIG_MIPS_ITE8172) += 0x80100000 + # -ifdef CONFIG_DDB5477 -core-y += arch/mips/ddb5xxx/common/ \ - arch/mips/ddb5xxx/ddb5477/ -LOADADDR += 0x80080000 -endif +# MIPS Atlas board +# +core-$(CONFIG_MIPS_BOARDS_GEN) += arch/mips/mips-boards/generic/ +core-$(CONFIG_MIPS_ATLAS) += arch/mips/mips-boards/atlas/ +load-$(CONFIG_MIPS_ATLAS) += 0x80100000 # -# Galileo EV64120 Board +# MIPS Malta board # -ifdef CONFIG_MIPS_EV64120 -core-y += arch/mips/galileo-boards/ev64120/ -LOADADDR += 0x80100000 -endif +core-$(CONFIG_MIPS_MALTA) += arch/mips/mips-boards/malta/ +load-$(CONFIG_MIPS_MALTA) := 0x80100000 # -# Galileo EV96100 Board +# MIPS SEAD board # -ifdef CONFIG_MIPS_EV96100 -core-y += arch/mips/galileo-boards/ev96100/ \ - arch/mips/galileo-boards/generic/ -LOADADDR += 0x80100000 -endif +core-$(CONFIG_MIPS_SEAD) += arch/mips/mips-boards/sead/ +load-$(CONFIG_MIPS_SEAD) += 0x80100000 # # Momentum Ocelot board # -ifdef CONFIG_MOMENCO_OCELOT # The Ocelot setup.o must be linked early - it does the ioremap() for the # mips_io_port_base. -core-y += arch/mips/gt64120/common/ \ - arch/mips/gt64120/momenco_ocelot/ -LOADADDR += 0x80100000 -endif +# +core-$(CONFIG_MOMENCO_OCELOT) += arch/mips/gt64120/common/ \ + arch/mips/gt64120/momenco_ocelot/ +load-$(CONFIG_MOMENCO_OCELOT) += 0x80100000 # -# Philips Nino +# Momentum Ocelot-G board # -ifdef CONFIG_NINO -core-y += arch/mips/philips/nino/ -LOADADDR += 0x80000000 -endif +# The Ocelot-G setup.o must be linked early - it does the ioremap() for the +# mips_io_port_base. +# +core-$(CONFIG_MOMENCO_OCELOT_G) += arch/mips/momentum/ocelot_g/ +load-$(CONFIG_MOMENCO_OCELOT_G) += 0x80100000 # -# ITE 8172 eval board with QED 5231 CPU +# Momentum Ocelot-C and -CS boards # -ifdef CONFIG_MIPS_ITE8172 -core-y += arch/mips/ite-boards/qed-4n-s01b/ \ - arch/mips/ite-boards/generic/ -LOADADDR += 0x80100000 -endif +# The Ocelot-C[S] setup.o must be linked early - it does the ioremap() for the +# mips_io_port_base. +core-$(CONFIG_MOMENCO_OCELOT_C) += arch/mips/momentum/ocelot_c/ +load-$(CONFIG_MOMENCO_OCELOT_C) += 0x80100000 # -# Globespan IVR eval board with QED 5231 CPU +# NEC DDB Vrc-5074 # -ifdef CONFIG_MIPS_IVR -core-y += arch/mips/ite-boards/ivr/ \ - arch/mips/ite-boards/generic/ -LOADADDR += 0x80100000 -endif +core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/ +core-$(CONFIG_DDB5074) += arch/mips/ddb5xxx/ddb5074/ +load-$(CONFIG_DDB5074) += 0x80080000 # -# Au1000 eval board +# NEC DDB Vrc-5476 # -ifdef CONFIG_MIPS_PB1000 -core-y += arch/mips/au1000/pb1000/ \ - arch/mips/au1000/common/ -LOADADDR += 0x80100000 -endif +core-$(CONFIG_DDB5476) += arch/mips/ddb5xxx/ddb5476/ +load-$(CONFIG_DDB5476) += 0x80080000 + +# +# NEC DDB Vrc-5477 +# +core-$(CONFIG_DDB5477) += arch/mips/ddb5xxx/ddb5477/ +load-$(CONFIG_DDB5477) += 0x80100000 + +core-$(CONFIG_LASAT) += arch/mips/lasat/ +load-$(CONFIG_LASAT) += 0x80000000 + +# +# NEC Osprey (vr4181) board +# +core-$(CONFIG_NEC_OSPREY) += arch/mips/vr4181/common/ \ + arch/mips/vr4181/osprey/ +load-$(CONFIG_NEC_OSPREY) += 0x80002000 + +# +# NEC Eagle/Hawk (VR4122/VR4131) board +# +core-$(CONFIG_VR41XX_COMMON) += arch/mips/vr41xx/common/ +core-$(CONFIG_NEC_EAGLE) += arch/mips/vr41xx/nec-eagle/ +load-$(CONFIG_NEC_EAGLE) += 0x80000000 + +# +# ZAO Networks Capcella (VR4131) +# +core-$(CONFIG_ZAO_CAPCELLA) += arch/mips/vr41xx/zao-capcella/ +load-$(CONFIG_ZAO_CAPCELLA) += 0x80000000 + +# +# Victor MP-C303/304 (VR4122) +# +core-$(CONFIG_VICTOR_MPC30X) += arch/mips/vr41xx/victor-mpc30x/ +load-$(CONFIG_VICTOR_MPC30X) += 0x80001000 + +# +# IBM WorkPad z50 (VR4121) +# +core-$(CONFIG_IBM_WORKPAD) += arch/mips/vr41xx/ibm-workpad/ +load-$(CONFIG_IBM_WORKPAD) += 0x80004000 + +# +# CASIO CASSIPEIA E-55/65 (VR4111) +# +core-$(CONFIG_CASIO_E55) += arch/mips/vr41xx/casio-e55/ +load-$(CONFIG_CASIO_E55) += 0x80004000 + +# +# TANBAC TB0226 Mbase (VR4131) +# +core-$(CONFIG_TANBAC_TB0226) += arch/mips/vr41xx/tanbac-tb0226/ +load-$(CONFIG_TANBAC_TB0226) += 0x80000000 + +# +# TANBAC TB0229 VR4131DIMM (VR4131) +# +core-$(CONFIG_TANBAC_TB0229) += arch/mips/vr41xx/tanbac-tb0229/ +load-$(CONFIG_TANBAC_TB0229) += 0x80000000 + +# +# SGI IP22 (Indy/Indigo2) +# +# Set the load address to >= 0x88069000 if you want to leave space for symmon, +# 0x88002000 for production kernels. Note that the value must be 8kb aligned +# or the handling of the current variable will break. +# +core-$(CONFIG_SGI_IP22) += arch/mips/sgi-ip22/ +load-$(CONFIG_SGI_IP22) += 0x88002000 + +# +# Sibyte SB1250 SOC +# +# This is a LIB so that it links at the end, and initcalls are later +# the sequence; but it is built as an object so that modules don't get +# removed (as happens, even if they have __initcall/module_init) +# +core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/sb1250/ +core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/sb1250/ + +# +# Sibyte BCM91120x (Carmel) board +# Sibyte BCM91120C (CRhine) board +# Sibyte BCM91125C (CRhone) board +# Sibyte BCM91125E (Rhone) board +# Sibyte SWARM board +# +libs-$(CONFIG_SIBYTE_CARMEL) += arch/mips/sibyte/swarm/ +load-$(CONFIG_SIBYTE_CARMEL) := 0x80100000 +libs-$(CONFIG_SIBYTE_CRHINE) += arch/mips/sibyte/swarm/ +load-$(CONFIG_SIBYTE_CRHINE) := 0x80100000 +libs-$(CONFIG_SIBYTE_CRHONE) += arch/mips/sibyte/swarm/ +load-$(CONFIG_SIBYTE_CRHONE) := 0x80100000 +libs-$(CONFIG_SIBYTE_RHONE) += arch/mips/sibyte/swarm/ +load-$(CONFIG_SIBYTE_RHONE) := 0x80100000 +libs-$(CONFIG_SIBYTE_SENTOSA) += arch/mips/sibyte/swarm/ +load-$(CONFIG_SIBYTE_SENTOSA) := 0x80100000 +libs-$(CONFIG_SIBYTE_SWARM) += arch/mips/sibyte/swarm/ +load-$(CONFIG_SIBYTE_SWARM) := 0x80100000 + +# +# SNI RM200 PCI +# +core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/ +load-$(CONFIG_SNI_RM200_PCI) += 0x80080000 + +# +# Toshiba JMR-TX3927 board +# +core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/jmr3927/rbhma3100/ \ + arch/mips/jmr3927/common/ +load-$(CONFIG_TOSHIBA_JMR3927) += 0x80050000 + +# +# Toshiba RBTX4927 board or +# Toshiba RBTX4937 board +# +core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/toshiba_rbtx4927/ +core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/ +load-$(CONFIG_TOSHIBA_RBTX4927) := 0x80020000 + +drivers-$(CONFIG_PCI) += arch/mips/pci/ + # # Choosing incompatible machines durings configuration will result in @@ -254,42 +354,79 @@ endif # none has been choosen above. # -AFLAGS_vmlinux.lds.o := -DLOADADDR=$(LOADADDR) +AFLAGS_vmlinux.lds.o := -D"LOADADDR=$(load-y)" -D"JIFFIES32=$(JIFFIES32)" head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o -SUBDIRS := arch/mips/tools - -core-y += arch/mips/kernel/ arch/mips/mm/ -libs-y += arch/mips/lib/lib.a +libs-y += arch/mips/lib/ +core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/ ifdef CONFIG_BAGET_MIPS BAGETBOOT = $(MAKE) -C arch/$(ARCH)/baget -balo: vmlinux +balo: vmlinux $(BAGETBOOT) balo endif -ifdef CONFIG_MIPS_EV64120 -GALILEOBOOT = $(MAKE) -C arch/$(ARCH)/galileo-boards/ev64120 +ifdef CONFIG_LASAT +rom.bin rom.sw: vmlinux + $(call descend,arch/mips/lasat/image,$@) +endif + +makeboot =$(Q)$(MAKE) -f scripts/Makefile.build obj=arch/mips/boot $(1) -gboot: vmlinux - $(MAKE) -C arch/$(ARCH)/galileo-boards/ev64120/compressed +# +# SNI firmware is f*cked in interesting ways ... +# +ifdef CONFIG_SNI_RM200_PCI +all: vmlinux.rm200 endif -MAKEBOOT = $(MAKE) -C arch/$(ARCH)/boot +vmlinux.ecoff vmlinux.rm200: vmlinux + +@$(call makeboot,$@) -vmlinux.ecoff: vmlinux - @$(MAKEBOOT) $@ +CLEAN_FILES += vmlinux.ecoff \ + vmlinux.rm200.tmp \ + vmlinux.rm200 archclean: - @$(MAKEBOOT) clean - rm -f arch/$(ARCH)/ld.script - $(MAKE) -C arch/$(ARCH)/tools clean - $(MAKE) -C arch/mips/baget clean + @$(MAKE) -f scripts/Makefile.clean obj=arch/mips/boot + @$(MAKE) -f scripts/Makefile.clean obj=arch/mips/baget + @$(MAKE) -f scripts/Makefile.clean obj=arch/mips/lasat archmrproper: - @$(MAKEBOOT) mrproper - $(MAKE) -C arch/$(ARCH)/tools mrproper + +# Generate -#include -#include -#include +#include -#include -#include +#include #include -#include #include -#include -#include #include +#include +#include #include -#include -#include - #include +#include +#include #include "ieee754.h" +#include "dsemul.h" /* Strap kernel emulator for full MIPS IV emulation */ @@ -62,20 +57,14 @@ #endif #define __mips 4 -typedef void *vaddr_t; - -/* Function which emulates the instruction in a branch delay slot. */ - -static int mips_dsemul(struct pt_regs *, mips_instruction, vaddr_t); - /* Function which emulates a floating point instruction. */ static int fpu_emu(struct pt_regs *, struct mips_fpu_soft_struct *, - mips_instruction); + mips_instruction); #if __mips >= 4 && __mips != 32 static int fpux_emu(struct pt_regs *, - struct mips_fpu_soft_struct *, mips_instruction); + struct mips_fpu_soft_struct *, mips_instruction); #endif /* Further private data for which no space exists in mips_fpu_soft_struct */ @@ -107,8 +96,7 @@ static const unsigned int fpucondbit[8] #endif - -/* +/* * Redundant with logic already in kernel/branch.c, * embedded in compute_return_epc. At some point, * a single subroutine should be used across both @@ -164,67 +152,45 @@ static int isBranchInstr(mips_instructio return 0; } -#define REG_TO_VA (vaddr_t) -#define VA_TO_REG (unsigned long) - -static unsigned long mips_get_word(struct pt_regs *xcp, void *va, int *perr) -{ - unsigned long temp; - - if (!user_mode(xcp)) { - *perr = 0; - return (*(unsigned long *) va); - } - - *perr = (int) get_user(temp, (unsigned long *) va); - return temp; -} - -static unsigned long long -mips_get_dword(struct pt_regs *xcp, void *va, int *perr) -{ - unsigned long long temp; - - if (!user_mode(xcp)) { - *perr = 0; - return (*(unsigned long long *) va); - } - - *perr = (int) get_user(temp, (unsigned long long *) va); - return temp; -} - -static int mips_put_word(struct pt_regs *xcp, void *va, unsigned long val) -{ - if (!user_mode(xcp)) { - *(unsigned long *) va = val; - return 0; - } - - return put_user(val, (unsigned long *) va); -} - -static int mips_put_dword(struct pt_regs *xcp, void *va, long long val) -{ - if (!user_mode(xcp)) { - *(unsigned long long *) va = val; - return 0; - } - - return put_user(val, (unsigned long long *) va); -} - - /* * In the Linux kernel, we support selection of FPR format on the * basis of the Status.FR bit. This does imply that, if a full 32 * FPRs are desired, there needs to be a flip-flop that can be written - * to one at that bit position. In any case, normal MIPS ABI uses + * to one at that bit position. In any case, O32 MIPS ABI uses * only the even FPRs (Status.FR = 0). */ #define CP0_STATUS_FR_SUPPORT +#ifdef CP0_STATUS_FR_SUPPORT +#define FR_BIT ST0_FR +#else +#define FR_BIT 0 +#endif + +#define SIFROMREG(si,x) ((si) = \ + (xcp->cp0_status & FR_BIT) || !(x & 1) ? \ + (int)ctx->regs[x] : \ + (int)(ctx->regs[x & ~1] >> 32 )) +#define SITOREG(si,x) (ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \ + (xcp->cp0_status & FR_BIT) || !(x & 1) ? \ + ctx->regs[x & ~1] >> 32 << 32 | (u32)(si) : \ + ctx->regs[x & ~1] << 32 >> 32 | (u64)(si) << 32) + +#define DIFROMREG(di,x) ((di) = \ + ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)]) +#define DITOREG(di,x) (ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)] \ + = (di)) +#define DIFROMREG(di,x) ((di) = \ + ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)]) +#define DITOREG(di,x) (ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)] \ + = (di)) + +#define SPFROMREG(sp,x) SIFROMREG((sp).bits,x) +#define SPTOREG(sp,x) SITOREG((sp).bits,x) +#define DPFROMREG(dp,x) DIFROMREG((dp).bits,x) +#define DPTOREG(dp,x) DITOREG((dp).bits,x) + /* * Emulate the single floating point instruction pointed at by EPC. * Two instructions if the instruction is in a branch delay slot. @@ -233,13 +199,10 @@ static int mips_put_dword(struct pt_regs static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) { mips_instruction ir; - vaddr_t emulpc; - vaddr_t contpc; + vaddr_t emulpc, contpc; unsigned int cond; - int err = 0; - ir = mips_get_word(xcp, REG_TO_VA xcp->cp0_epc, &err); - if (err) { + if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) { fpuemuprivate.stats.errors++; return SIGBUS; } @@ -252,7 +215,7 @@ static int cop1Emulate(struct pt_regs *x /* * The instruction to be emulated is in a branch delay slot * which means that we have to emulate the branch instruction - * BEFORE we do the cop1 instruction. + * BEFORE we do the cop1 instruction. * * This branch could be a COP1 branch, but in that case we * would have had a trap for that instruction, and would not @@ -266,363 +229,201 @@ static int cop1Emulate(struct pt_regs *x if (__compute_return_epc(xcp)) { #ifdef CP1DBG printk("failed to emulate branch at %p\n", - REG_TO_VA(xcp->cp0_epc)); + REG_TO_VA(xcp->cp0_epc)); #endif - return SIGILL;; + return SIGILL; } - ir = mips_get_word(xcp, emulpc, &err); - if (err) { + if (get_user(ir, (mips_instruction *) emulpc)) { fpuemuprivate.stats.errors++; return SIGBUS; } + /* __computer_return_epc() will have updated cp0_epc */ contpc = REG_TO_VA xcp->cp0_epc; - } else { + /* In order not to confuse ptrace() et al, tweak context */ + xcp->cp0_epc = VA_TO_REG emulpc - 4; + } + else { emulpc = REG_TO_VA xcp->cp0_epc; - contpc = REG_TO_VA xcp->cp0_epc + 4; + contpc = REG_TO_VA(xcp->cp0_epc + 4); } -emul: + emul: fpuemuprivate.stats.emulated++; switch (MIPSInst_OPCODE(ir)) { -#ifdef CP0_STATUS_FR_SUPPORT - /* R4000+ 64-bit fpu registers */ #ifndef SINGLE_ONLY_FPU - case ldc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - int ft = MIPSInst_RT(ir); - if (!(xcp->cp0_status & ST0_FR)) - ft &= ~1; - ctx->regs[ft] = mips_get_dword(xcp, va, &err); - fpuemuprivate.stats.loads++; - if (err) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } + case ldc1_op:{ + u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + + MIPSInst_SIMM(ir)); + u64 val; + + fpuemuprivate.stats.loads++; + if (get_user(val, va)) { + fpuemuprivate.stats.errors++; + return SIGBUS; } + DITOREG(val, MIPSInst_RT(ir)); break; + } - case sdc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - int ft = MIPSInst_RT(ir); - if (!(xcp->cp0_status & ST0_FR)) - ft &= ~1; - fpuemuprivate.stats.stores++; - if (mips_put_dword(xcp, va, ctx->regs[ft])) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } + case sdc1_op:{ + u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + + MIPSInst_SIMM(ir)); + u64 val; + + fpuemuprivate.stats.stores++; + DIFROMREG(val, MIPSInst_RT(ir)); + if (put_user(val, va)) { + fpuemuprivate.stats.errors++; + return SIGBUS; } break; + } #endif - case lwc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - fpureg_t val; - int ft = MIPSInst_RT(ir); - fpuemuprivate.stats.loads++; - val = mips_get_word(xcp, va, &err); - if (err) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } - if (xcp->cp0_status & ST0_FR) { - /* load whole register */ - ctx->regs[ft] = val; - } else if (ft & 1) { - /* load to m.s. 32 bits */ -#ifdef SINGLE_ONLY_FPU - /* illegal register in single-float mode */ - return SIGILL; -#else - ctx->regs[(ft & ~1)] &= 0xffffffff; - ctx->regs[(ft & ~1)] |= val << 32; -#endif - } else { - /* load to l.s. 32 bits */ - ctx->regs[ft] &= ~0xffffffffLL; - ctx->regs[ft] |= val; - } - } - break; + case lwc1_op:{ + u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + + MIPSInst_SIMM(ir)); + u32 val; - case swc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - unsigned int val; - int ft = MIPSInst_RT(ir); - fpuemuprivate.stats.stores++; - if (xcp->cp0_status & ST0_FR) { - /* store whole register */ - val = ctx->regs[ft]; - } else if (ft & 1) { -#ifdef SINGLE_ONLY_FPU - /* illegal register in single-float mode */ - return SIGILL; -#else - /* store from m.s. 32 bits */ - val = ctx->regs[(ft & ~1)] >> 32; -#endif - } else { - /* store from l.s. 32 bits */ - val = ctx->regs[ft]; - } - if (mips_put_word(xcp, va, val)) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } - } - break; -#else /* old 32-bit fpu registers */ - case lwc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - ctx->regs[MIPSInst_RT(ir)] = - mips_get_word(xcp, va, &err); - fpuemuprivate.stats.loads++; - if (err) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } + fpuemuprivate.stats.loads++; + if (get_user(val, va)) { + fpuemuprivate.stats.errors++; + return SIGBUS; } - break; - - case swc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - fpuemuprivate.stats.stores++; - if (mips_put_word - (xcp, va, ctx->regs[MIPSInst_RT(ir)])) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } +#ifdef SINGLE_ONLY_FPU + if (MIPSInst_RT(ir) & 1) { + /* illegal register in single-float mode */ + return SIGILL; } - break; - case ldc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - unsigned int rt = MIPSInst_RT(ir) & ~1; - int errs = 0; - fpuemuprivate.stats.loads++; -#if (defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN) || defined(__MIPSEB__) - ctx->regs[rt + 1] = - mips_get_word(xcp, va + 0, &err); - errs += err; - ctx->regs[rt + 0] = - mips_get_word(xcp, va + 4, &err); - errs += err; -#else - ctx->regs[rt + 0] = - mips_get_word(xcp, va + 0, &err); - errs += err; - ctx->regs[rt + 1] = - mips_get_word(xcp, va + 4, &err); - errs += err; #endif - if (err) - return SIGBUS; - } + SITOREG(val, MIPSInst_RT(ir)); break; + } - case sdc1_op: - { - void *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)]) - + MIPSInst_SIMM(ir); - unsigned int rt = MIPSInst_RT(ir) & ~1; - fpuemuprivate.stats.stores++; -#if (defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN) || defined(__MIPSEB__) - if (mips_put_word(xcp, va + 0, ctx->regs[rt + 1])) - return SIGBUS; - if (mips_put_word(xcp, va + 4, ctx->regs[rt + 0])) - return SIGBUS; -#else - if (mips_put_word(xcp, va + 0, ctx->regs[rt + 0])) - return SIGBUS; - if (mips_put_word(xcp, va + 4, ctx->regs[rt + 1])) - return SIGBUS; + case swc1_op:{ + u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + + MIPSInst_SIMM(ir)); + u32 val; + + fpuemuprivate.stats.stores++; +#ifdef SINGLE_ONLY_FPU + if (MIPSInst_RT(ir) & 1) { + /* illegal register in single-float mode */ + return SIGILL; + } #endif + SIFROMREG(val, MIPSInst_RT(ir)); + if (put_user(val, va)) { + fpuemuprivate.stats.errors++; + return SIGBUS; } break; -#endif + } case cop1_op: switch (MIPSInst_RS(ir)) { -#ifdef CP0_STATUS_FR_SUPPORT #if __mips64 && !defined(SINGLE_ONLY_FPU) case dmfc_op: /* copregister fs -> gpr[rt] */ if (MIPSInst_RT(ir) != 0) { - int fs = MIPSInst_RD(ir); - if (!(xcp->cp0_status & ST0_FR)) - fs &= ~1; - xcp->regs[MIPSInst_RT(ir)] = ctx->regs[fs]; + DIFROMREG(xcp->regs[MIPSInst_RT(ir)], + MIPSInst_RD(ir)); } break; - case dmtc_op: { + case dmtc_op: /* copregister fs <- rt */ - fpureg_t value; - int fs = MIPSInst_RD(ir); - if (!(xcp->cp0_status & ST0_FR)) - fs &= ~1; - value = - (MIPSInst_RT(ir) == - 0) ? 0 : xcp->regs[MIPSInst_RT(ir)]; - ctx->regs[fs] = value; + DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); break; - } #endif case mfc_op: /* copregister rd -> gpr[rt] */ - if (MIPSInst_RT(ir) != 0) { - /* default value from l.s. 32 bits */ - int value = ctx->regs[MIPSInst_RD(ir)]; - if (MIPSInst_RD(ir) & 1) { #ifdef SINGLE_ONLY_FPU - /* illegal register in single-float mode */ - return SIGILL; -#else - if (!(xcp->cp0_status & ST0_FR)) { - /* move from m.s. 32 bits */ - value = - ctx-> - regs[MIPSInst_RD(ir) & - ~1] >> 32; - } -#endif - } - xcp->regs[MIPSInst_RT(ir)] = value; + if (MIPSInst_RD(ir) & 1) { + /* illegal register in single-float mode */ + return SIGILL; } - break; - - case mtc_op: - /* copregister rd <- rt */ - { - fpureg_t value; - if (MIPSInst_RT(ir) == 0) - value = 0; - else - value = - (unsigned int) xcp-> - regs[MIPSInst_RT(ir)]; - if (MIPSInst_RD(ir) & 1) { -#ifdef SINGLE_ONLY_FPU - /* illegal register in single-float mode */ - return SIGILL; -#else - if (!(xcp->cp0_status & ST0_FR)) { - /* move to m.s. 32 bits */ - ctx-> - regs[ - (MIPSInst_RD(ir) & - ~1)] &= - 0xffffffff; - ctx-> - regs[ - (MIPSInst_RD(ir) & - ~1)] |= - value << 32; - break; - } #endif - } - /* move to l.s. 32 bits */ - ctx->regs[MIPSInst_RD(ir)] &= - ~0xffffffffLL; - ctx->regs[MIPSInst_RD(ir)] |= value; - } - break; -#else - - case mfc_op: - /* copregister rd -> gpr[rt] */ if (MIPSInst_RT(ir) != 0) { - unsigned value = - ctx->regs[MIPSInst_RD(ir)]; - xcp->regs[MIPSInst_RT(ir)] = value; + SIFROMREG(xcp->regs[MIPSInst_RT(ir)], + MIPSInst_RD(ir)); } break; case mtc_op: /* copregister rd <- rt */ - { - unsigned value; - value = - (MIPSInst_RT(ir) == - 0) ? 0 : xcp->regs[MIPSInst_RT(ir)]; - ctx->regs[MIPSInst_RD(ir)] = value; +#ifdef SINGLE_ONLY_FPU + if (MIPSInst_RD(ir) & 1) { + /* illegal register in single-float mode */ + return SIGILL; } - break; #endif + SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); + break; - case cfc_op: + case cfc_op:{ /* cop control register rd -> gpr[rt] */ - { - unsigned value; + u32 value; - if (MIPSInst_RD(ir) == FPCREG_CSR) { - value = ctx->sr; + if (ir == CP1UNDEF) { + return do_dsemulret(xcp); + } + if (MIPSInst_RD(ir) == FPCREG_CSR) { + value = ctx->sr; #ifdef CSRTRACE - printk - ("%p gpr[%d]<-csr=%08x\n", - REG_TO_VA(xcp->cp0_epc), - MIPSInst_RT(ir), value); + printk("%p gpr[%d]<-csr=%08x\n", + REG_TO_VA(xcp->cp0_epc), + MIPSInst_RT(ir), value); #endif - } else if (MIPSInst_RD(ir) == FPCREG_RID) - value = 0; - else - value = 0; - if (MIPSInst_RT(ir)) - xcp->regs[MIPSInst_RT(ir)] = value; } + else if (MIPSInst_RD(ir) == FPCREG_RID) + value = 0; + else + value = 0; + if (MIPSInst_RT(ir)) + xcp->regs[MIPSInst_RT(ir)] = value; break; + } - case ctc_op: + case ctc_op:{ /* copregister rd <- rt */ - { - unsigned value; - - if (MIPSInst_RT(ir) == 0) - value = 0; - else - value = xcp->regs[MIPSInst_RT(ir)]; + u32 value; - /* we only have one writable control reg - */ - if (MIPSInst_RD(ir) == FPCREG_CSR) { + if (MIPSInst_RT(ir) == 0) + value = 0; + else + value = xcp->regs[MIPSInst_RT(ir)]; + + /* we only have one writable control reg + */ + if (MIPSInst_RD(ir) == FPCREG_CSR) { #ifdef CSRTRACE - printk - ("%p gpr[%d]->csr=%08x\n", - REG_TO_VA(xcp->cp0_epc), - MIPSInst_RT(ir), value); -#endif - ctx->sr = value; - /* copy new rounding mode to ieee library state! */ - ieee754_csr.rm = - ieee_rm[value & 0x3]; - } + printk("%p gpr[%d]->csr=%08x\n", + REG_TO_VA(xcp->cp0_epc), + MIPSInst_RT(ir), value); +#endif + ctx->sr = value; + /* copy new rounding mode and + flush bit to ieee library state! */ + ieee754_csr.nod = (ctx->sr & 0x1000000) != 0; + ieee754_csr.rm = ieee_rm[value & 0x3]; + } + if ((ctx->sr >> 5) & ctx->sr & FPU_CSR_ALL_E) { + return SIGFPE; } break; + } - case bc_op: { + case bc_op:{ int likely = 0; if (xcp->cp0_cause & CAUSEF_BD) return SIGILL; #if __mips >= 4 - cond = ctx-> sr & fpucondbit[MIPSInst_RT(ir) >> 2]; + cond = ctx->sr & fpucondbit[MIPSInst_RT(ir) >> 2]; #else cond = ctx->sr & FPU_CSR_COND; #endif @@ -643,14 +444,16 @@ emul: xcp->cp0_cause |= CAUSEF_BD; if (cond) { - /* branch taken: emulate dslot instruction */ + /* branch taken: emulate dslot + * instruction + */ xcp->cp0_epc += 4; - contpc = REG_TO_VA xcp->cp0_epc + - (MIPSInst_SIMM(ir) << 2); + contpc = REG_TO_VA + (xcp->cp0_epc + + (MIPSInst_SIMM(ir) << 2)); - ir = mips_get_word(xcp, REG_TO_VA(xcp->cp0_epc), - &err); - if (err) { + if (get_user(ir, (mips_instruction *) + REG_TO_VA xcp->cp0_epc)) { fpuemuprivate.stats.errors++; return SIGBUS; } @@ -677,30 +480,36 @@ emul: } /* - * Single step the non-cp1 instruction in the - * dslot + * Single step the non-cp1 + * instruction in the dslot */ - return mips_dsemul(xcp, ir, contpc); - } else { + return mips_dsemul(xcp, ir, VA_TO_REG contpc); + } + else { /* branch not taken */ - if (likely) + if (likely) { /* - * branch likely nullifies dslot if not - * taken + * branch likely nullifies + * dslot if not taken */ xcp->cp0_epc += 4; - /* else continue & execute dslot as normal insn */ + contpc += 4; + /* + * else continue & execute + * dslot as normal insn + */ + } } break; } - default: { - int sig; - + default: if (!(MIPSInst_RS(ir) & 0x10)) return SIGILL; + { + int sig; - /* a real fpu computation instruction */ + /* a real fpu computation instruction */ if ((sig = fpu_emu(xcp, ctx, ir))) return sig; } @@ -708,13 +517,13 @@ emul: break; #if __mips >= 4 && __mips != 32 - case cop1x_op: - { - int sig; - if ((sig = fpux_emu(xcp, ctx, ir))) - return sig; - } + case cop1x_op:{ + int sig; + + if ((sig = fpux_emu(xcp, ctx, ir))) + return sig; break; + } #endif #if __mips >= 4 @@ -722,8 +531,8 @@ emul: if (MIPSInst_FUNC(ir) != movc_op) return SIGILL; cond = fpucondbit[MIPSInst_RT(ir) >> 2]; - if (((ctx->sr & cond) != 0) != - ((MIPSInst_RT(ir) & 1) != 0)) return 0; + if (((ctx->sr & cond) != 0) != ((MIPSInst_RT(ir) & 1) != 0)) + return 0; xcp->regs[MIPSInst_RD(ir)] = xcp->regs[MIPSInst_RS(ir)]; break; #endif @@ -739,141 +548,20 @@ emul: } /* - * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when - * we have to emulate the instruction in a COP1 branch delay slot. Do - * not change cp0_epc due to the instruction - * - * According to the spec: - * 1) it shouldnt be a branch :-) - * 2) it can be a COP instruction :-( - * 3) if we are tring to run a protected memory space we must take - * special care on memory access instructions :-( - */ - -/* - * "Trampoline" return routine to catch exception following - * execution of delay-slot instruction execution. - */ - -int do_dsemulret(struct pt_regs *xcp) -{ -#ifdef DSEMUL_TRACE - printk("desemulret\n"); -#endif - /* Set EPC to return to post-branch instruction */ - xcp->cp0_epc = current->thread.dsemul_epc; - /* - * Clear the state that got us here. - */ - current->thread.dsemul_aerpc = (unsigned long) 0; - - return 0; -} - - -#define AdELOAD 0x8c000001 /* lw $0,1($0) */ - -static int -mips_dsemul(struct pt_regs *xcp, mips_instruction ir, vaddr_t cpc) -{ - mips_instruction *dsemul_insns; - mips_instruction forcetrap; - extern asmlinkage void handle_dsemulret(void); - - if (ir == 0) { /* a nop is easy */ - xcp->cp0_epc = VA_TO_REG(cpc); - return 0; - } -#ifdef DSEMUL_TRACE - printk("desemul %p %p\n", REG_TO_VA(xcp->cp0_epc), cpc); -#endif - - /* - * The strategy is to push the instruction onto the user stack - * and put a trap after it which we can catch and jump to - * the required address any alternative apart from full - * instruction emulation!!. - */ - dsemul_insns = (mips_instruction *) (xcp->regs[29] & ~3); - dsemul_insns -= 3; /* Two instructions, plus one for luck ;-) */ - - /* Verify that the stack pointer is not competely insane */ - if (verify_area(VERIFY_WRITE, dsemul_insns, - sizeof(mips_instruction) * 2)) - return SIGBUS; - - if (mips_put_word(xcp, &dsemul_insns[0], ir)) { - fpuemuprivate.stats.errors++; - return SIGBUS; - } - - /* - * Algorithmics used a system call instruction, and - * borrowed that vector. MIPS/Linux version is a bit - * more heavyweight in the interests of portability and - * multiprocessor support. We flag the thread for special - * handling in the unaligned access handler and force an - * address error excpetion. - */ - - /* If one is *really* paranoid, one tests for a bad stack pointer */ - if ((xcp->regs[29] & 0x3) == 0x3) - forcetrap = AdELOAD - 1; - else - forcetrap = AdELOAD; - - if (mips_put_word(xcp, &dsemul_insns[1], forcetrap)) { - fpuemuprivate.stats.errors++; - return (SIGBUS); - } - - /* Set thread state to catch and handle the exception */ - current->thread.dsemul_epc = (unsigned long) cpc; - current->thread.dsemul_aerpc = (unsigned long) &dsemul_insns[1]; - xcp->cp0_epc = VA_TO_REG & dsemul_insns[0]; - flush_cache_sigtramp((unsigned long) dsemul_insns); - - return SIGILL; /* force out of emulation loop */ -} - -/* * Conversion table from MIPS compare ops 48-63 - * cond = ieee754dp_cmp(x,y,IEEE754_UN); + * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); */ static const unsigned char cmptab[8] = { - 0, /* cmp_0 (sig) cmp_sf */ - IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ - IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ - IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ - IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ - IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ - IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ - IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ + 0, /* cmp_0 (sig) cmp_sf */ + IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ + IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ + IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ + IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ + IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ + IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ + IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ }; -#define SIFROMREG(si,x) ((si) = ctx->regs[x]) -#define SITOREG(si,x) (ctx->regs[x] = (int)(si)) - -#if __mips64 && !defined(SINGLE_ONLY_FPU) -#define DIFROMREG(di,x) ((di) = ctx->regs[x]) -#define DITOREG(di,x) (ctx->regs[x] = (di)) -#endif - -#define SPFROMREG(sp,x) ((sp).bits = ctx->regs[x]) -#define SPTOREG(sp,x) (ctx->regs[x] = (sp).bits) - -#ifdef CP0_STATUS_FR_SUPPORT -#define DPFROMREG(dp,x) ((dp).bits = \ - ctx->regs[(xcp->cp0_status & ST0_FR) ? x : (x & ~1)]) -#define DPTOREG(dp,x) (ctx->regs[(xcp->cp0_status & ST0_FR) ? x : (x & ~1)]\ - = (dp).bits) -#else -/* Beware: MIPS COP1 doubles are always little_word endian in registers */ -#define DPFROMREG(dp,x) \ - ((dp).bits = ((unsigned long long)ctx->regs[(x)+1] << 32) | ctx->regs[x]) -#define DPTOREG(dp,x) \ - (ctx->regs[x] = (dp).bits, ctx->regs[(x)+1] = (dp).bits >> 32) -#endif #if __mips >= 4 && __mips != 32 @@ -881,6 +569,22 @@ static const unsigned char cmptab[8] = { * Additional MIPS4 instructions */ +#define DEF3OP(name, p, f1, f2, f3) \ +static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \ + ieee754##p t) \ +{ \ + struct ieee754_csr ieee754_csr_save; \ + s = f1 (s, t); \ + ieee754_csr_save = ieee754_csr; \ + s = f2 (s, r); \ + ieee754_csr_save.cx |= ieee754_csr.cx; \ + ieee754_csr_save.sx |= ieee754_csr.sx; \ + s = f3 (s); \ + ieee754_csr.cx |= ieee754_csr_save.cx; \ + ieee754_csr.sx |= ieee754_csr_save.sx; \ + return s; \ +} + static ieee754dp fpemu_dp_recip(ieee754dp d) { return ieee754dp_div(ieee754dp_one(0), d); @@ -901,287 +605,184 @@ static ieee754sp fpemu_sp_rsqrt(ieee754s return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); } +DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add,); +DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub,); +DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); +DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); +DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add,); +DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub,); +DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); +DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); -static ieee754dp fpemu_dp_madd(ieee754dp r, ieee754dp s, ieee754dp t) +static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, + mips_instruction ir) { - return ieee754dp_add(ieee754dp_mul(s, t), r); -} + unsigned rcsr = 0; /* resulting csr */ -static ieee754dp fpemu_dp_msub(ieee754dp r, ieee754dp s, ieee754dp t) -{ - return ieee754dp_sub(ieee754dp_mul(s, t), r); -} + fpuemuprivate.stats.cp1xops++; -static ieee754dp fpemu_dp_nmadd(ieee754dp r, ieee754dp s, ieee754dp t) -{ - return ieee754dp_neg(ieee754dp_add(ieee754dp_mul(s, t), r)); -} + switch (MIPSInst_FMA_FFMT(ir)) { + case s_fmt:{ /* 0 */ -static ieee754dp fpemu_dp_nmsub(ieee754dp r, ieee754dp s, ieee754dp t) -{ - return ieee754dp_neg(ieee754dp_sub(ieee754dp_mul(s, t), r)); -} + ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp); + ieee754sp fd, fr, fs, ft; + u32 *va; + u32 val; + switch (MIPSInst_FUNC(ir)) { + case lwxc1_op: + va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + + xcp->regs[MIPSInst_FT(ir)]); -static ieee754sp fpemu_sp_madd(ieee754sp r, ieee754sp s, ieee754sp t) -{ - return ieee754sp_add(ieee754sp_mul(s, t), r); -} + fpuemuprivate.stats.loads++; + if (get_user(val, va)) { + fpuemuprivate.stats.errors++; + return SIGBUS; + } +#ifdef SINGLE_ONLY_FPU + if (MIPSInst_FD(ir) & 1) { + /* illegal register in single-float + * mode + */ + return SIGILL; + } +#endif + SITOREG(val, MIPSInst_FD(ir)); + break; -static ieee754sp fpemu_sp_msub(ieee754sp r, ieee754sp s, ieee754sp t) -{ - return ieee754sp_sub(ieee754sp_mul(s, t), r); -} + case swxc1_op: + va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + + xcp->regs[MIPSInst_FT(ir)]); -static ieee754sp fpemu_sp_nmadd(ieee754sp r, ieee754sp s, ieee754sp t) -{ - return ieee754sp_neg(ieee754sp_add(ieee754sp_mul(s, t), r)); -} + fpuemuprivate.stats.stores++; +#ifdef SINGLE_ONLY_FPU + if (MIPSInst_FS(ir) & 1) { + /* illegal register in single-float + * mode + */ + return SIGILL; + } +#endif -static ieee754sp fpemu_sp_nmsub(ieee754sp r, ieee754sp s, ieee754sp t) -{ - return ieee754sp_neg(ieee754sp_sub(ieee754sp_mul(s, t), r)); -} + SIFROMREG(val, MIPSInst_FS(ir)); + if (put_user(val, va)) { + fpuemuprivate.stats.errors++; + return SIGBUS; + } + break; -static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, - mips_instruction ir) -{ - unsigned rcsr = 0; /* resulting csr */ + case madd_s_op: + handler = fpemu_sp_madd; + goto scoptop; + case msub_s_op: + handler = fpemu_sp_msub; + goto scoptop; + case nmadd_s_op: + handler = fpemu_sp_nmadd; + goto scoptop; + case nmsub_s_op: + handler = fpemu_sp_nmsub; + goto scoptop; - fpuemuprivate.stats.cp1xops++; + scoptop: + SPFROMREG(fr, MIPSInst_FR(ir)); + SPFROMREG(fs, MIPSInst_FS(ir)); + SPFROMREG(ft, MIPSInst_FT(ir)); + fd = (*handler) (fr, fs, ft); + SPTOREG(fd, MIPSInst_FD(ir)); - switch (MIPSInst_FMA_FFMT(ir)) { - case s_fmt: /* 0 */ - { - ieee754sp(*handler) (ieee754sp, ieee754sp, - ieee754sp); - ieee754sp fd, fr, fs, ft; - - switch (MIPSInst_FUNC(ir)) { - case lwxc1_op: - { - void *va = - REG_TO_VA(xcp-> - regs[MIPSInst_FR(ir)] - + - xcp-> - regs[MIPSInst_FT - (ir)]); - fpureg_t val; - int err = 0; - val = mips_get_word(xcp, va, &err); - if (err) { - fpuemuprivate.stats. - errors++; - return SIGBUS; - } - if (xcp->cp0_status & ST0_FR) { - /* load whole register */ - ctx-> - regs[MIPSInst_FD(ir)] = - val; - } else if (MIPSInst_FD(ir) & 1) { - /* load to m.s. 32 bits */ -#if defined(SINGLE_ONLY_FPU) - /* illegal register in single-float mode */ - return SIGILL; -#else - ctx-> - regs[ - (MIPSInst_FD(ir) & - ~1)] &= - 0xffffffff; - ctx-> - regs[ - (MIPSInst_FD(ir) & - ~1)] |= - val << 32; -#endif - } else { - /* load to l.s. 32 bits */ - ctx-> - regs[MIPSInst_FD(ir)] - &= ~0xffffffffLL; - ctx-> - regs[MIPSInst_FD(ir)] - |= val; - } - } - break; + copcsr: + if (ieee754_cxtest(IEEE754_INEXACT)) + rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; + if (ieee754_cxtest(IEEE754_UNDERFLOW)) + rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; + if (ieee754_cxtest(IEEE754_OVERFLOW)) + rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; + if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) + rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; - case swxc1_op: - { - void *va = - REG_TO_VA(xcp-> - regs[MIPSInst_FR(ir)] - + - xcp-> - regs[MIPSInst_FT - (ir)]); - unsigned int val; - if (xcp->cp0_status & ST0_FR) { - /* store whole register */ - val = - ctx-> - regs[MIPSInst_FS(ir)]; - } else if (MIPSInst_FS(ir) & 1) { -#if defined(SINGLE_ONLY_FPU) - /* illegal register in single-float mode */ - return SIGILL; -#else - /* store from m.s. 32 bits */ - val = - ctx-> - regs[ - (MIPSInst_FS(ir) & - ~1)] >> 32; -#endif - } else { - /* store from l.s. 32 bits */ - val = - ctx-> - regs[MIPSInst_FS(ir)]; - } - if (mips_put_word(xcp, va, val)) { - fpuemuprivate.stats. - errors++; - return SIGBUS; - } - } - break; + ctx->sr = (ctx->sr & ~FPU_CSR_ALL_X) | rcsr; + if (ieee754_csr.nod) + ctx->sr |= 0x1000000; + if ((ctx->sr >> 5) & ctx->sr & FPU_CSR_ALL_E) { + /*printk ("SIGFPE: fpu csr = %08x\n", + ctx->sr); */ + return SIGFPE; + } - case madd_s_op: - handler = fpemu_sp_madd; - goto scoptop; - case msub_s_op: - handler = fpemu_sp_msub; - goto scoptop; - case nmadd_s_op: - handler = fpemu_sp_nmadd; - goto scoptop; - case nmsub_s_op: - handler = fpemu_sp_nmsub; - goto scoptop; + break; - scoptop: - SPFROMREG(fr, MIPSInst_FR(ir)); - SPFROMREG(fs, MIPSInst_FS(ir)); - SPFROMREG(ft, MIPSInst_FT(ir)); - fd = (*handler) (fr, fs, ft); - SPTOREG(fd, MIPSInst_FD(ir)); + default: + return SIGILL; + } + break; + } - copcsr: - if (ieee754_cxtest(IEEE754_INEXACT)) - rcsr |= - FPU_CSR_INE_X | FPU_CSR_INE_S; - if (ieee754_cxtest(IEEE754_UNDERFLOW)) - rcsr |= - FPU_CSR_UDF_X | FPU_CSR_UDF_S; - if (ieee754_cxtest(IEEE754_OVERFLOW)) - rcsr |= - FPU_CSR_OVF_X | FPU_CSR_OVF_S; - if (ieee754_cxtest - (IEEE754_INVALID_OPERATION)) rcsr |= - FPU_CSR_INV_X | FPU_CSR_INV_S; - - ctx->sr = - (ctx->sr & ~FPU_CSR_ALL_X) | rcsr; - if ((ctx->sr >> 5) & ctx-> - sr & FPU_CSR_ALL_E) { - /*printk ("SIGFPE: fpu csr = %08x\n",ctx->sr); */ - return SIGFPE; - } +#ifndef SINGLE_ONLY_FPU + case d_fmt:{ /* 1 */ + ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp); + ieee754dp fd, fr, fs, ft; + u64 *va; + u64 val; - break; + switch (MIPSInst_FUNC(ir)) { + case ldxc1_op: + va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + + xcp->regs[MIPSInst_FT(ir)]); - default: - return SIGILL; + fpuemuprivate.stats.loads++; + if (get_user(val, va)) { + fpuemuprivate.stats.errors++; + return SIGBUS; } - } - break; + DITOREG(val, MIPSInst_FD(ir)); + break; -#if !defined(SINGLE_ONLY_FPU) - case d_fmt: /* 1 */ - { - ieee754dp(*handler) (ieee754dp, ieee754dp, - ieee754dp); - ieee754dp fd, fr, fs, ft; - - switch (MIPSInst_FUNC(ir)) { - case ldxc1_op: - { - void *va = - REG_TO_VA(xcp-> - regs[MIPSInst_FR(ir)] - + - xcp-> - regs[MIPSInst_FT - (ir)]); - int err = 0; - ctx->regs[MIPSInst_FD(ir)] = - mips_get_dword(xcp, va, &err); - if (err) { - fpuemuprivate.stats. - errors++; - return SIGBUS; - } - } - break; + case sdxc1_op: + va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + + xcp->regs[MIPSInst_FT(ir)]); - case sdxc1_op: - { - void *va = - REG_TO_VA(xcp-> - regs[MIPSInst_FR(ir)] - + - xcp-> - regs[MIPSInst_FT - (ir)]); - if (mips_put_dword - (xcp, va, - ctx->regs[MIPSInst_FS(ir)])) { - fpuemuprivate.stats. - errors++; - return SIGBUS; - } - } - break; + fpuemuprivate.stats.stores++; + DIFROMREG(val, MIPSInst_FS(ir)); + if (put_user(val, va)) { + fpuemuprivate.stats.errors++; + return SIGBUS; + } + break; - case madd_d_op: - handler = fpemu_dp_madd; - goto dcoptop; - case msub_d_op: - handler = fpemu_dp_msub; - goto dcoptop; - case nmadd_d_op: - handler = fpemu_dp_nmadd; - goto dcoptop; - case nmsub_d_op: - handler = fpemu_dp_nmsub; - goto dcoptop; + case madd_d_op: + handler = fpemu_dp_madd; + goto dcoptop; + case msub_d_op: + handler = fpemu_dp_msub; + goto dcoptop; + case nmadd_d_op: + handler = fpemu_dp_nmadd; + goto dcoptop; + case nmsub_d_op: + handler = fpemu_dp_nmsub; + goto dcoptop; - dcoptop: - DPFROMREG(fr, MIPSInst_FR(ir)); - DPFROMREG(fs, MIPSInst_FS(ir)); - DPFROMREG(ft, MIPSInst_FT(ir)); - fd = (*handler) (fr, fs, ft); - DPTOREG(fd, MIPSInst_FD(ir)); - goto copcsr; + dcoptop: + DPFROMREG(fr, MIPSInst_FR(ir)); + DPFROMREG(fs, MIPSInst_FS(ir)); + DPFROMREG(ft, MIPSInst_FT(ir)); + fd = (*handler) (fr, fs, ft); + DPTOREG(fd, MIPSInst_FD(ir)); + goto copcsr; - default: - return SIGILL; - } + default: + return SIGILL; } break; + } #endif case 0x7: /* 7 */ - { - if (MIPSInst_FUNC(ir) != pfetch_op) { - return SIGILL; - } - /* ignore prefx operation */ + if (MIPSInst_FUNC(ir) != pfetch_op) { + return SIGILL; } + /* ignore prefx operation */ break; default: @@ -1198,7 +799,7 @@ static int fpux_emu(struct pt_regs *xcp, * Emulate a single COP1 arithmetic instruction. */ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, - mips_instruction ir) + mips_instruction ir) { int rfmt; /* resulting format */ unsigned rcsr = 0; /* resulting csr */ @@ -1208,49 +809,52 @@ static int fpu_emu(struct pt_regs *xcp, ieee754sp s; int w; #if __mips64 - long long l; + s64 l; #endif } rv; /* resulting value */ fpuemuprivate.stats.cp1ops++; switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { - case s_fmt: { /* 0 */ - ieee754sp(*handler) (); + case s_fmt:{ /* 0 */ + union { + ieee754sp(*b) (ieee754sp, ieee754sp); + ieee754sp(*u) (ieee754sp); + } handler; switch (MIPSInst_FUNC(ir)) { /* binary ops */ case fadd_op: - handler = ieee754sp_add; + handler.b = ieee754sp_add; goto scopbop; case fsub_op: - handler = ieee754sp_sub; + handler.b = ieee754sp_sub; goto scopbop; case fmul_op: - handler = ieee754sp_mul; + handler.b = ieee754sp_mul; goto scopbop; case fdiv_op: - handler = ieee754sp_div; + handler.b = ieee754sp_div; goto scopbop; /* unary ops */ #if __mips >= 2 || __mips64 case fsqrt_op: - handler = ieee754sp_sqrt; + handler.u = ieee754sp_sqrt; goto scopuop; #endif #if __mips >= 4 && __mips != 32 case frsqrt_op: - handler = fpemu_sp_rsqrt; + handler.u = fpemu_sp_rsqrt; goto scopuop; case frecip_op: - handler = fpemu_sp_recip; + handler.u = fpemu_sp_recip; goto scopuop; #endif #if __mips >= 4 case fmovc_op: cond = fpucondbit[MIPSInst_FT(ir) >> 2]; if (((ctx->sr & cond) != 0) != - ((MIPSInst_FT(ir) & 1) != 0)) + ((MIPSInst_FT(ir) & 1) != 0)) return 0; SPFROMREG(rv.s, MIPSInst_FS(ir)); break; @@ -1266,35 +870,36 @@ static int fpu_emu(struct pt_regs *xcp, break; #endif case fabs_op: - handler = ieee754sp_abs; + handler.u = ieee754sp_abs; goto scopuop; case fneg_op: - handler = ieee754sp_neg; + handler.u = ieee754sp_neg; goto scopuop; case fmov_op: /* an easy one */ SPFROMREG(rv.s, MIPSInst_FS(ir)); - break; + goto copcsr; + /* binary op on handler */ -scopbop: + scopbop: { ieee754sp fs, ft; SPFROMREG(fs, MIPSInst_FS(ir)); SPFROMREG(ft, MIPSInst_FT(ir)); - rv.s = (*handler) (fs, ft); + rv.s = (*handler.b) (fs, ft); goto copcsr; } -scopuop: + scopuop: { ieee754sp fs; SPFROMREG(fs, MIPSInst_FS(ir)); - rv.s = (*handler) (fs); + rv.s = (*handler.u) (fs); goto copcsr; } -copcsr: + copcsr: if (ieee754_cxtest(IEEE754_INEXACT)) rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; if (ieee754_cxtest(IEEE754_UNDERFLOW)) @@ -1303,15 +908,14 @@ copcsr: rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; - if (ieee754_cxtest - (IEEE754_INVALID_OPERATION)) rcsr |= - FPU_CSR_INV_X | FPU_CSR_INV_S; - break; + if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) + rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; + break; - /* unary conv ops */ + /* unary conv ops */ case fcvts_op: return SIGILL; /* not defined */ - case fcvtd_op: { + case fcvtd_op:{ #ifdef SINGLE_ONLY_FPU return SIGILL; /* not defined */ #else @@ -1323,7 +927,7 @@ copcsr: goto copcsr; } #endif - case fcvtw_op: { + case fcvtw_op:{ ieee754sp fs; SPFROMREG(fs, MIPSInst_FS(ir)); @@ -1336,7 +940,7 @@ copcsr: case fround_op: case ftrunc_op: case fceil_op: - case ffloor_op: { + case ffloor_op:{ unsigned int oldrm = ieee754_csr.rm; ieee754sp fs; @@ -1350,7 +954,7 @@ copcsr: #endif /* __mips >= 2 */ #if __mips64 && !defined(SINGLE_ONLY_FPU) - case fcvtl_op: { + case fcvtl_op:{ ieee754sp fs; SPFROMREG(fs, MIPSInst_FS(ir)); @@ -1362,7 +966,7 @@ copcsr: case froundl_op: case ftruncl_op: case fceill_op: - case ffloorl_op: { + case ffloorl_op:{ unsigned int oldrm = ieee754_csr.rm; ieee754sp fs; @@ -1382,55 +986,65 @@ copcsr: SPFROMREG(fs, MIPSInst_FS(ir)); SPFROMREG(ft, MIPSInst_FT(ir)); - rv.w = ieee754sp_cmp(fs, ft, cmptab[cmpop & 0x7]); + rv.w = ieee754sp_cmp(fs, ft, + cmptab[cmpop & 0x7], cmpop & 0x8); rfmt = -1; - if ((cmpop & 0x8) && ieee754_cxtest(IEEE754_INVALID_OPERATION)) + if ((cmpop & 0x8) && ieee754_cxtest + (IEEE754_INVALID_OPERATION)) rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; - } else { - return SIGILL; - } - break; + else + goto copcsr; + + } + else { + return SIGILL; } break; } + break; + } -#if !defined(SINGLE_ONLY_FPU) - case d_fmt: { - ieee754dp(*handler) (); +#ifndef SINGLE_ONLY_FPU + case d_fmt:{ + union { + ieee754dp(*b) (ieee754dp, ieee754dp); + ieee754dp(*u) (ieee754dp); + } handler; switch (MIPSInst_FUNC(ir)) { /* binary ops */ case fadd_op: - handler = ieee754dp_add; + handler.b = ieee754dp_add; goto dcopbop; case fsub_op: - handler = ieee754dp_sub; + handler.b = ieee754dp_sub; goto dcopbop; case fmul_op: - handler = ieee754dp_mul; + handler.b = ieee754dp_mul; goto dcopbop; case fdiv_op: - handler = ieee754dp_div; + handler.b = ieee754dp_div; goto dcopbop; /* unary ops */ #if __mips >= 2 || __mips64 case fsqrt_op: - handler = ieee754dp_sqrt; + handler.u = ieee754dp_sqrt; goto dcopuop; #endif #if __mips >= 4 && __mips != 32 case frsqrt_op: - handler = fpemu_dp_rsqrt; + handler.u = fpemu_dp_rsqrt; goto dcopuop; case frecip_op: - handler = fpemu_dp_recip; + handler.u = fpemu_dp_recip; goto dcopuop; #endif #if __mips >= 4 case fmovc_op: cond = fpucondbit[MIPSInst_FT(ir) >> 2]; - if (((ctx->sr & cond) != 0) != ((MIPSInst_FT(ir) & 1) != 0)) + if (((ctx->sr & cond) != 0) != + ((MIPSInst_FT(ir) & 1) != 0)) return 0; DPFROMREG(rv.d, MIPSInst_FS(ir)); break; @@ -1446,40 +1060,38 @@ copcsr: break; #endif case fabs_op: - handler = ieee754dp_abs; + handler.u = ieee754dp_abs; goto dcopuop; case fneg_op: - handler = ieee754dp_neg; + handler.u = ieee754dp_neg; goto dcopuop; case fmov_op: /* an easy one */ DPFROMREG(rv.d, MIPSInst_FS(ir)); - break; + goto copcsr; /* binary op on handler */ -dcopbop: - { + dcopbop:{ ieee754dp fs, ft; DPFROMREG(fs, MIPSInst_FS(ir)); DPFROMREG(ft, MIPSInst_FT(ir)); - rv.d = (*handler) (fs, ft); + rv.d = (*handler.b) (fs, ft); goto copcsr; } -dcopuop: - { + dcopuop:{ ieee754dp fs; DPFROMREG(fs, MIPSInst_FS(ir)); - rv.d = (*handler) (fs); + rv.d = (*handler.u) (fs); goto copcsr; } - /* unary conv ops */ - case fcvts_op: { + /* unary conv ops */ + case fcvts_op:{ ieee754dp fs; DPFROMREG(fs, MIPSInst_FS(ir)); @@ -1490,7 +1102,7 @@ dcopuop: case fcvtd_op: return SIGILL; /* not defined */ - case fcvtw_op: { + case fcvtw_op:{ ieee754dp fs; DPFROMREG(fs, MIPSInst_FS(ir)); @@ -1503,7 +1115,7 @@ dcopuop: case fround_op: case ftrunc_op: case fceil_op: - case ffloor_op: { + case ffloor_op:{ unsigned int oldrm = ieee754_csr.rm; ieee754dp fs; @@ -1517,7 +1129,7 @@ dcopuop: #endif #if __mips64 && !defined(SINGLE_ONLY_FPU) - case fcvtl_op: { + case fcvtl_op:{ ieee754dp fs; DPFROMREG(fs, MIPSInst_FS(ir)); @@ -1529,7 +1141,7 @@ dcopuop: case froundl_op: case ftruncl_op: case fceill_op: - case ffloorl_op: { + case ffloorl_op:{ unsigned int oldrm = ieee754_csr.rm; ieee754dp fs; @@ -1549,30 +1161,42 @@ dcopuop: DPFROMREG(fs, MIPSInst_FS(ir)); DPFROMREG(ft, MIPSInst_FT(ir)); - rv.w = ieee754dp_cmp(fs, ft, cmptab[cmpop & 0x7]); + rv.w = ieee754dp_cmp(fs, ft, + cmptab[cmpop & 0x7], cmpop & 0x8); rfmt = -1; - if ((cmpop & 0x8) && ieee754_cxtest (IEEE754_INVALID_OPERATION)) + if ((cmpop & 0x8) + && + ieee754_cxtest + (IEEE754_INVALID_OPERATION)) rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; - } else { + else + goto copcsr; + + } + else { return SIGILL; } break; } break; } -#endif /* !defined(SINGLE_ONLY_FPU) */ +#endif /* ifndef SINGLE_ONLY_FPU */ + + case w_fmt:{ + ieee754sp fs; - case w_fmt: { switch (MIPSInst_FUNC(ir)) { case fcvts_op: /* convert word to single precision real */ - rv.s = ieee754sp_fint(ctx-> regs[MIPSInst_FS(ir)]); + SPFROMREG(fs, MIPSInst_FS(ir)); + rv.s = ieee754sp_fint(fs.bits); rfmt = s_fmt; goto copcsr; -#if !defined(SINGLE_ONLY_FPU) +#ifndef SINGLE_ONLY_FPU case fcvtd_op: /* convert word to double precision real */ - rv.d = ieee754dp_fint(ctx-> regs[MIPSInst_FS(ir)]); + SPFROMREG(fs, MIPSInst_FS(ir)); + rv.d = ieee754dp_fint(fs.bits); rfmt = d_fmt; goto copcsr; #endif @@ -1583,16 +1207,16 @@ dcopuop: } #if __mips64 && !defined(SINGLE_ONLY_FPU) - case l_fmt: { + case l_fmt:{ switch (MIPSInst_FUNC(ir)) { case fcvts_op: /* convert long to single precision real */ - rv.s = ieee754sp_flong(ctx-> regs[MIPSInst_FS(ir)]); + rv.s = ieee754sp_flong(ctx->regs[MIPSInst_FS(ir)]); rfmt = s_fmt; goto copcsr; case fcvtd_op: /* convert long to double precision real */ - rv.d = ieee754dp_flong(ctx-> regs[MIPSInst_FS(ir)]); + rv.d = ieee754dp_flong(ctx->regs[MIPSInst_FS(ir)]); rfmt = d_fmt; goto copcsr; default: @@ -1619,11 +1243,11 @@ dcopuop: return SIGFPE; } - /* + /* * Now we can safely write the result back to the register file. */ switch (rfmt) { - case -1: { + case -1:{ #if __mips >= 4 cond = fpucondbit[MIPSInst_FD(ir) >> 2]; #else @@ -1635,7 +1259,7 @@ dcopuop: ctx->sr &= ~cond; break; } -#if !defined(SINGLE_ONLY_FPU) +#ifndef SINGLE_ONLY_FPU case d_fmt: DPTOREG(rv.d, MIPSInst_FD(ir)); break; @@ -1658,38 +1282,39 @@ dcopuop: return 0; } - -/* - * Emulate the floating point instruction at EPC, and continue to run until we - * hit a non-fp instruction, or a backward branch. This cuts down dramatically - * on the per instruction exception overhead. - */ -int fpu_emulator_cop1Handler(struct pt_regs *xcp) +int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, + struct mips_fpu_soft_struct *ctx) { - struct mips_fpu_soft_struct *ctx = ¤t->thread.fpu.soft; - unsigned long oldepc, prevepc; - unsigned int insn; + gpreg_t oldepc, prevepc; + mips_instruction insn; int sig = 0; - int err = 0; oldepc = xcp->cp0_epc; do { - cond_resched(); - prevepc = xcp->cp0_epc; - insn = mips_get_word(xcp, REG_TO_VA(xcp->cp0_epc), &err); - if (err) { + + if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) { fpuemuprivate.stats.errors++; return SIGBUS; } - if (insn != 0) - sig = cop1Emulate(xcp, ctx); - else + if (insn == 0) xcp->cp0_epc += 4; /* skip nops */ + else { + /* Update ieee754_csr. Only relevant if we have a + h/w FPU */ + ieee754_csr.nod = (ctx->sr & 0x1000000) != 0; + ieee754_csr.rm = ieee_rm[ctx->sr & 0x3]; + ieee754_csr.cx = (ctx->sr >> 12) & 0x1f; + sig = cop1Emulate(xcp, ctx); + } - if (mips_cpu.options & MIPS_CPU_FPU) + if (cpu_has_fpu) + break; + if (sig) break; - } while (xcp->cp0_epc > prevepc && sig == 0); + + cond_resched(); + } while (xcp->cp0_epc > prevepc); /* SIGILL indicates a non-fpu instruction */ if (sig == SIGILL && xcp->cp0_epc != oldepc) @@ -1698,80 +1323,3 @@ int fpu_emulator_cop1Handler(struct pt_r return sig; } - - -#ifdef NOTDEF -/* - * Patch up the hardware fpu state when an f.p. exception occurs. - */ -static int cop1Patcher(int xcptno, struct pt_regs *xcp) -{ - struct mips_fpu_soft_struct *ctx = ¤t->thread.fpu.soft; - unsigned sr; - int sig; - - /* reenable Cp1, else fpe_save() will get nested exception */ - sr = mips_bissr(ST0_CU1); - - /* get fpu registers and status, then clear pending exceptions */ - fpe_save(ctx); - fpe_setsr(ctx->sr &= ~FPU_CSR_ALL_X); - - /* get current rounding mode for IEEE library, and emulate insn */ - ieee754_csr.rm = ieee_rm[ctx->sr & 0x3]; - sig = cop1Emulate(xcp, ctx); - - /* don't return with f.p. exceptions pending */ - ctx->sr &= ~FPU_CSR_ALL_X; - fpe_restore(ctx); - - mips_setsr(sr); - return sig; -} - -void _cop1_init(int emulate) -{ - extern int _nofpu; - - if (emulate) { - /* - * Install cop1 emulator to handle "coprocessor unusable" exception - */ - xcption(XCPTCPU, cop1Handler); - fpuemuactive = 1; /* tell dbg.c that we are in charge */ - _nofpu = 0; /* tell setjmp() it "has" an fpu */ - } else { - /* - * Install cop1 emulator for floating point exceptions only, - * i.e. denormalised results, underflow, overflow etc, which - * must be emulated in s/w. - */ -#ifdef 1 - /* r4000 or above use dedicate exception */ - xcption(XCPTFPE, cop1Patcher); -#else - /* r3000 et al use interrupt */ - extern int _sbd_getfpuintr(void); - int intno = _sbd_getfpuintr(); - intrupt(intno, cop1Patcher, 0); - mips_bissr(SR_IM0 << intno); -#endif - -#if (#cpu(r4640) || #cpu(r4650)) && !defined(SINGLE_ONLY_FPU) - /* For R4640/R4650 compiled *without* the -msingle-float flag, - then we share responsibility: the h/w handles the single - precision operations, and the trap emulator handles the - double precision. We set fpuemuactive so that dbg.c first - fetches the s/w state before saving the h/w state. */ - fpuemuactive = 1; - { - int i; - /* initialise the unused d.p high order words to be NaN */ - for (i = 0; i < 32; i++) - current->thread.fpu.soft.regs[i] = - 0x7ff80bad00000000LL; - } -#endif /* (r4640 || r4650) && !fpu(single) */ - } -} -#endif --- linux-2.5.73/arch/mips/math-emu/dp_add.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/dp_add.c 2003-06-27 15:56:23.000000000 -0700 @@ -38,27 +38,23 @@ ieee754dp ieee754dp_add(ieee754dp x, iee CLEARCX; - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(ieee754dp_bestnan(x, y), "add", x, - y); + FLUSHXDP; + FLUSHYDP; + switch (CLPAIR(xc, yc)) { + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(y, "add", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754dp_nanxcpt(x, "add", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754dp_bestnan(x, y); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754dp_nanxcpt(ieee754dp_indef(), "add", x, y); case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): @@ -66,6 +62,7 @@ ieee754dp ieee754dp_add(ieee754dp x, iee case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): return y; + case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): @@ -73,7 +70,7 @@ ieee754dp ieee754dp_add(ieee754dp x, iee return x; - /* Inifity handling + /* Infinity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): --- linux-2.5.73/arch/mips/math-emu/dp_cmp.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/dp_cmp.c 2003-06-27 15:56:23.000000000 -0700 @@ -27,21 +27,30 @@ #include "ieee754dp.h" -int ieee754dp_cmp(ieee754dp x, ieee754dp y, int cmp) +int ieee754dp_cmp(ieee754dp x, ieee754dp y, int cmp, int sig) { - CLEARCX; + COMPXDP; + COMPYDP; + + EXPLODEXDP; + EXPLODEYDP; + FLUSHXDP; + FLUSHYDP; + CLEARCX; /* Even clear inexact flag here */ if (ieee754dp_isnan(x) || ieee754dp_isnan(y)) { + if (sig || xc == IEEE754_CLASS_SNAN || yc == IEEE754_CLASS_SNAN) + SETCX(IEEE754_INVALID_OPERATION); if (cmp & IEEE754_CUN) return 1; if (cmp & (IEEE754_CLT | IEEE754_CGT)) { - if (SETCX(IEEE754_INVALID_OPERATION)) + if (sig && SETANDTESTCX(IEEE754_INVALID_OPERATION)) return ieee754si_xcpt(0, "fcmpf", x); } return 0; } else { - long long int vx = x.bits; - long long int vy = y.bits; + s64 vx = x.bits; + s64 vy = y.bits; if (vx < 0) vx = -vx ^ DP_SIGN_BIT; --- linux-2.5.73/arch/mips/math-emu/dp_div.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/dp_div.c 2003-06-27 15:56:23.000000000 -0700 @@ -32,32 +32,28 @@ ieee754dp ieee754dp_div(ieee754dp x, iee COMPXDP; COMPYDP; - CLEARCX; - EXPLODEXDP; EXPLODEYDP; - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(ieee754dp_bestnan(x, y), "div", x, - y); + CLEARCX; + + FLUSHXDP; + FLUSHYDP; + switch (CLPAIR(xc, yc)) { + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(y, "div", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754dp_nanxcpt(x, "div", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754dp_bestnan(x, y); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754dp_nanxcpt(ieee754dp_indef(), "div", x, y); case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): @@ -65,6 +61,7 @@ ieee754dp ieee754dp_div(ieee754dp x, iee case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): return y; + case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): @@ -129,9 +126,9 @@ ieee754dp ieee754dp_div(ieee754dp x, iee { /* now the dirty work */ - unsigned long long rm = 0; + u64 rm = 0; int re = xe - ye; - unsigned long long bm; + u64 bm; for (bm = DP_MBIT(DP_MBITS + 2); bm; bm >>= 1) { if (xm >= ym) { --- linux-2.5.73/arch/mips/math-emu/dp_flong.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/dp_flong.c 2003-06-27 15:56:23.000000000 -0700 @@ -27,7 +27,7 @@ #include "ieee754dp.h" -ieee754dp ieee754dp_flong(long long x) +ieee754dp ieee754dp_flong(s64 x) { COMPXDP; @@ -67,9 +67,9 @@ ieee754dp ieee754dp_flong(long long x) DPNORMRET1(xs, xe, xm, "dp_flong", x); } -ieee754dp ieee754dp_fulong(unsigned long long u) +ieee754dp ieee754dp_fulong(u64 u) { - if ((long long) u < 0) + if ((s64) u < 0) return ieee754dp_add(ieee754dp_1e63(), ieee754dp_flong(u & ~(1ULL << 63))); return ieee754dp_flong(u); --- linux-2.5.73/arch/mips/math-emu/dp_frexp.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/dp_frexp.c 2003-06-27 15:56:23.000000000 -0700 @@ -27,7 +27,7 @@ #include "ieee754dp.h" -/* close to ieeep754dp_logb +/* close to ieeep754dp_logb */ ieee754dp ieee754dp_frexp(ieee754dp x, int *eptr) { --- linux-2.5.73/arch/mips/math-emu/dp_fsp.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/dp_fsp.c 2003-06-27 15:56:23.000000000 -0700 @@ -31,16 +31,20 @@ ieee754dp ieee754dp_fsp(ieee754sp x) { COMPXSP; + EXPLODEXSP; + CLEARCX; - EXPLODEXSP; + FLUSHXSP; switch (xc) { - case IEEE754_CLASS_QNAN: case IEEE754_CLASS_SNAN: + SETCX(IEEE754_INVALID_OPERATION); + return ieee754dp_nanxcpt(ieee754dp_indef(), "fsp"); + case IEEE754_CLASS_QNAN: return ieee754dp_nanxcpt(builddp(xs, DP_EMAX + 1 + DP_EBIAS, - ((unsigned long long) xm + ((u64) xm << (DP_MBITS - SP_MBITS))), "fsp", x); @@ -66,5 +70,5 @@ ieee754dp ieee754dp_fsp(ieee754sp x) xm &= ~SP_HIDDEN_BIT; return builddp(xs, xe + DP_EBIAS, - (unsigned long long) xm << (DP_MBITS - SP_MBITS)); + (u64) xm << (DP_MBITS - SP_MBITS)); } --- linux-2.5.73/arch/mips/math-emu/dp_modf.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/dp_modf.c 2003-06-27 15:56:23.000000000 -0700 @@ -59,7 +59,7 @@ ieee754dp ieee754dp_modf(ieee754dp x, ie *ip = x; return ieee754dp_zero(xs); } - /* generate ipart mantissa by clearing bottom bits + /* generate ipart mantissa by clearing bottom bits */ *ip = builddp(xs, xe + DP_EBIAS, ((xm >> (DP_MBITS - xe)) << (DP_MBITS - xe)) & --- linux-2.5.73/arch/mips/math-emu/dp_mul.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/dp_mul.c 2003-06-27 15:56:23.000000000 -0700 @@ -32,32 +32,28 @@ ieee754dp ieee754dp_mul(ieee754dp x, iee COMPXDP; COMPYDP; - CLEARCX; - EXPLODEXDP; EXPLODEYDP; - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(ieee754dp_bestnan(x, y), "mul", x, - y); + CLEARCX; + + FLUSHXDP; + FLUSHYDP; + switch (CLPAIR(xc, yc)) { + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(y, "mul", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754dp_nanxcpt(x, "mul", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754dp_bestnan(x, y); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754dp_nanxcpt(ieee754dp_indef(), "mul", x, y); case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): @@ -65,6 +61,7 @@ ieee754dp ieee754dp_mul(ieee754dp x, iee case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): return y; + case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): @@ -114,7 +111,7 @@ ieee754dp ieee754dp_mul(ieee754dp x, iee { int re = xe + ye; int rs = xs ^ ys; - unsigned long long rm; + u64 rm; /* shunt to top of word */ xm <<= 64 - (DP_MBITS + 1); @@ -124,23 +121,23 @@ ieee754dp ieee754dp_mul(ieee754dp x, iee */ /* 32 * 32 => 64 */ -#define DPXMULT(x,y) ((unsigned long long)(x) * (unsigned long long)y) +#define DPXMULT(x,y) ((u64)(x) * (u64)y) { unsigned lxm = xm; unsigned hxm = xm >> 32; unsigned lym = ym; unsigned hym = ym >> 32; - unsigned long long lrm; - unsigned long long hrm; + u64 lrm; + u64 hrm; lrm = DPXMULT(lxm, lym); hrm = DPXMULT(hxm, hym); { - unsigned long long t = DPXMULT(lxm, hym); + u64 t = DPXMULT(lxm, hym); { - unsigned long long at = + u64 at = lrm + (t << 32); hrm += at < lrm; lrm = at; @@ -149,9 +146,9 @@ ieee754dp ieee754dp_mul(ieee754dp x, iee } { - unsigned long long t = DPXMULT(hxm, lym); + u64 t = DPXMULT(hxm, lym); { - unsigned long long at = + u64 at = lrm + (t << 32); hrm += at < lrm; lrm = at; @@ -164,7 +161,7 @@ ieee754dp ieee754dp_mul(ieee754dp x, iee /* * sticky shift down to normal rounding precision */ - if ((signed long long) rm < 0) { + if ((s64) rm < 0) { rm = (rm >> (64 - (DP_MBITS + 1 + 3))) | ((rm << (DP_MBITS + 1 + 3)) != 0); --- linux-2.5.73/arch/mips/math-emu/dp_simple.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/dp_simple.c 2003-06-27 15:56:23.000000000 -0700 @@ -42,7 +42,16 @@ ieee754dp ieee754dp_copysign(ieee754dp x ieee754dp ieee754dp_neg(ieee754dp x) { + COMPXDP; + + EXPLODEXDP; CLEARCX; + FLUSHXDP; + + if (xc == IEEE754_CLASS_SNAN) { + SETCX(IEEE754_INVALID_OPERATION); + return ieee754dp_nanxcpt(ieee754dp_indef(), "neg"); + } if (ieee754dp_isnan(x)) /* but not infinity */ return ieee754dp_nanxcpt(x, "neg", x); @@ -55,7 +64,16 @@ ieee754dp ieee754dp_neg(ieee754dp x) ieee754dp ieee754dp_abs(ieee754dp x) { + COMPXDP; + + EXPLODEXDP; CLEARCX; + FLUSHXDP; + + if (xc == IEEE754_CLASS_SNAN) { + SETCX(IEEE754_INVALID_OPERATION); + return ieee754dp_nanxcpt(ieee754dp_indef(), "neg"); + } if (ieee754dp_isnan(x)) /* but not infinity */ return ieee754dp_nanxcpt(x, "abs", x); --- linux-2.5.73/arch/mips/math-emu/dp_sqrt.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/dp_sqrt.c 2003-06-27 15:56:23.000000000 -0700 @@ -27,16 +27,6 @@ #include "ieee754dp.h" -static const struct ieee754dp_konst knan = { -#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__) - 0, 0, DP_EBIAS + DP_EMAX + 1, 0 -#else - 0, DP_EBIAS + DP_EMAX + 1, 0, 0 -#endif -}; - -#define nan ((ieee754dp)knan) - static const unsigned table[] = { 0, 1204, 3062, 5746, 9193, 13348, 18162, 23592, 29598, 36145, 43202, 50740, 58733, 67158, 75992, @@ -53,29 +43,37 @@ ieee754dp ieee754dp_sqrt(ieee754dp x) COMPXDP; EXPLODEXDP; + CLEARCX; + FLUSHXDP; /* x == INF or NAN? */ switch (xc) { case IEEE754_CLASS_QNAN: - case IEEE754_CLASS_SNAN: /* sqrt(Nan) = Nan */ return ieee754dp_nanxcpt(x, "sqrt"); + case IEEE754_CLASS_SNAN: + SETCX(IEEE754_INVALID_OPERATION); + return ieee754dp_nanxcpt(ieee754dp_indef(), "sqrt"); case IEEE754_CLASS_ZERO: /* sqrt(0) = 0 */ return x; case IEEE754_CLASS_INF: - if (xs) + if (xs) { /* sqrt(-Inf) = Nan */ - return ieee754dp_nanxcpt(nan, "sqrt"); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754dp_nanxcpt(ieee754dp_indef(), "sqrt"); + } /* sqrt(+Inf) = Inf */ return x; case IEEE754_CLASS_DNORM: DPDNORMX; /* fall through */ case IEEE754_CLASS_NORM: - if (xs) + if (xs) { /* sqrt(-x) = Nan */ - return ieee754dp_nanxcpt(nan, "sqrt"); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754dp_nanxcpt(ieee754dp_indef(), "sqrt"); + } break; } @@ -101,7 +99,7 @@ ieee754dp ieee754dp_sqrt(ieee754dp x) yh = y.bits >> 32; yh = (yh >> 1) + 0x1ff80000; yh = yh - table[(yh >> 15) & 31]; - y.bits = ((unsigned long long) yh << 32) | (y.bits & 0xffffffff); + y.bits = ((u64) yh << 32) | (y.bits & 0xffffffff); /* Heron's rule once with correction to improve to ~18 sig. bits */ /* t=x/y; y=y+t; py[n0]=py[n0]-0x00100006; py[n1]=0; */ --- linux-2.5.73/arch/mips/math-emu/dp_sub.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/dp_sub.c 2003-06-27 15:56:23.000000000 -0700 @@ -32,32 +32,28 @@ ieee754dp ieee754dp_sub(ieee754dp x, iee COMPXDP; COMPYDP; - CLEARCX; - EXPLODEXDP; EXPLODEYDP; - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(ieee754dp_bestnan(x, y), "sub", x, - y); + CLEARCX; + + FLUSHXDP; + FLUSHYDP; + switch (CLPAIR(xc, yc)) { + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754dp_nanxcpt(y, "sub", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754dp_nanxcpt(x, "sub", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754dp_bestnan(x, y); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754dp_nanxcpt(ieee754dp_indef(), "sub", x, y); case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): @@ -65,6 +61,7 @@ ieee754dp ieee754dp_sub(ieee754dp x, iee case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): return y; + case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): @@ -72,7 +69,7 @@ ieee754dp ieee754dp_sub(ieee754dp x, iee return x; - /* Inifity handling + /* Infinity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): @@ -183,7 +180,7 @@ ieee754dp ieee754dp_sub(ieee754dp x, iee return ieee754dp_zero(0); /* other round modes => sign = 1 */ } - /* normalize to rounding precision + /* normalize to rounding precision */ while ((xm >> (DP_MBITS + 3)) == 0) { xm <<= 1; --- linux-2.5.73/arch/mips/math-emu/dp_tint.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/dp_tint.c 2003-06-27 15:56:23.000000000 -0700 @@ -35,38 +35,74 @@ int ieee754dp_tint(ieee754dp x) CLEARCX; EXPLODEXDP; + FLUSHXDP; switch (xc) { case IEEE754_CLASS_SNAN: case IEEE754_CLASS_QNAN: - SETCX(IEEE754_INVALID_OPERATION); - return ieee754si_xcpt(ieee754si_indef(), "fixdp", x); case IEEE754_CLASS_INF: - SETCX(IEEE754_OVERFLOW); - return ieee754si_xcpt(ieee754si_indef(), "fixdp", x); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754si_xcpt(ieee754si_indef(), "dp_tint", x); case IEEE754_CLASS_ZERO: return 0; - case IEEE754_CLASS_DNORM: /* much to small */ - SETCX(IEEE754_UNDERFLOW); - return ieee754si_xcpt(0, "fixdp", x); + case IEEE754_CLASS_DNORM: case IEEE754_CLASS_NORM: break; } - if (xe >= 31) { - SETCX(IEEE754_OVERFLOW); - return ieee754si_xcpt(ieee754si_indef(), "fix", x); - } - if (xe < 0) { - SETCX(IEEE754_UNDERFLOW); - return ieee754si_xcpt(0, "fix", x); + if (xe > 31) { + /* Set invalid. We will only use overflow for floating + point overflow */ + SETCX(IEEE754_INVALID_OPERATION); + return ieee754si_xcpt(ieee754si_indef(), "dp_tint", x); } /* oh gawd */ if (xe > DP_MBITS) { xm <<= xe - DP_MBITS; } else if (xe < DP_MBITS) { - /* XXX no rounding - */ - xm >>= DP_MBITS - xe; + u64 residue; + int round; + int sticky; + int odd; + + if (xe < -1) { + residue = xm; + round = 0; + sticky = residue != 0; + xm = 0; + } + else { + residue = xm << (64 - DP_MBITS + xe); + round = (residue >> 63) != 0; + sticky = (residue << 1) != 0; + xm >>= DP_MBITS - xe; + } + /* Note: At this point upper 32 bits of xm are guaranteed + to be zero */ + odd = (xm & 0x1) != 0x0; + switch (ieee754_csr.rm) { + case IEEE754_RN: + if (round && (sticky || odd)) + xm++; + break; + case IEEE754_RZ: + break; + case IEEE754_RU: /* toward +Infinity */ + if ((round || sticky) && !xs) + xm++; + break; + case IEEE754_RD: /* toward -Infinity */ + if ((round || sticky) && xs) + xm++; + break; + } + /* look for valid corner case 0x80000000 */ + if ((xm >> 31) != 0 && (xs == 0 || xm != 0x80000000)) { + /* This can happen after rounding */ + SETCX(IEEE754_INVALID_OPERATION); + return ieee754si_xcpt(ieee754si_indef(), "dp_tint", x); + } + if (round || sticky) + SETCX(IEEE754_INEXACT); } if (xs) return -xm; --- linux-2.5.73/arch/mips/math-emu/dp_tlong.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/dp_tlong.c 2003-06-27 15:56:23.000000000 -0700 @@ -27,99 +27,85 @@ #include "ieee754dp.h" -long long ieee754dp_tlong(ieee754dp x) +s64 ieee754dp_tlong(ieee754dp x) { COMPXDP; CLEARCX; EXPLODEXDP; + FLUSHXDP; switch (xc) { case IEEE754_CLASS_SNAN: case IEEE754_CLASS_QNAN: - SETCX(IEEE754_INVALID_OPERATION); - return ieee754di_xcpt(ieee754di_indef(), "dp_tlong", x); case IEEE754_CLASS_INF: - SETCX(IEEE754_OVERFLOW); + SETCX(IEEE754_INVALID_OPERATION); return ieee754di_xcpt(ieee754di_indef(), "dp_tlong", x); case IEEE754_CLASS_ZERO: return 0; - case IEEE754_CLASS_DNORM: /* much too small */ - SETCX(IEEE754_UNDERFLOW); - return ieee754di_xcpt(0, "dp_tlong", x); + case IEEE754_CLASS_DNORM: case IEEE754_CLASS_NORM: break; } if (xe >= 63) { - SETCX(IEEE754_OVERFLOW); + /* look for valid corner case */ + if (xe == 63 && xs && xm == DP_HIDDEN_BIT) + return -0x8000000000000000LL; + /* Set invalid. We will only use overflow for floating + point overflow */ + SETCX(IEEE754_INVALID_OPERATION); return ieee754di_xcpt(ieee754di_indef(), "dp_tlong", x); } - if (xe < 0) { - if (ieee754_csr.rm == IEEE754_RU) { - if (xs) { /* Negative */ - return 0x0000000000000000LL; - } else { /* Positive */ - return 0x0000000000000001LL; - } - } else if (ieee754_csr.rm == IEEE754_RD) { - if (xs) { /* Negative , return -1 */ - return 0xffffffffffffffffLL; - } else { /* Positive */ - return 0x0000000000000000LL; - } - } else { - SETCX(IEEE754_UNDERFLOW); - return ieee754di_xcpt(0, "dp_tlong", x); - } - } /* oh gawd */ if (xe > DP_MBITS) { xm <<= xe - DP_MBITS; } else if (xe < DP_MBITS) { - unsigned long long residue; - unsigned long long mask = 0; - int i; + u64 residue; int round; int sticky; int odd; - /* compute mask */ - for (i = 0; i < DP_MBITS - xe; i++) { - mask = mask << 1; - mask = mask | 0x1; + if (xe < -1) { + residue = xm; + round = 0; + sticky = residue != 0; + xm = 0; } - residue = (xm & mask) << (64 - (DP_MBITS - xe)); - round = - ((0x8000000000000000LL & residue) != - 0x0000000000000000LL); - sticky = - ((0x7fffffffffffffffLL & residue) != - 0x0000000000000000LL); - - xm >>= DP_MBITS - xe; - - odd = ((xm & 0x1) != 0x0000000000000000LL); - - /* Do the rounding */ - if (!round && sticky) { - if ((ieee754_csr.rm == IEEE754_RU && !xs) - || (ieee754_csr.rm == IEEE754_RD && xs)) { + else { + /* Shifting a u64 64 times does not work, + * so we do it in two steps. Be aware that xe + * may be -1 */ + residue = xm << (xe + 1); + residue <<= 63 - DP_MBITS; + round = (residue >> 63) != 0; + sticky = (residue << 1) != 0; + xm >>= DP_MBITS - xe; + } + odd = (xm & 0x1) != 0x0; + switch (ieee754_csr.rm) { + case IEEE754_RN: + if (round && (sticky || odd)) xm++; - } - } else if (round && !sticky) { - if ((ieee754_csr.rm == IEEE754_RU && !xs) - || (ieee754_csr.rm == IEEE754_RD && xs) - || (ieee754_csr.rm == IEEE754_RN && odd)) { + break; + case IEEE754_RZ: + break; + case IEEE754_RU: /* toward +Infinity */ + if ((round || sticky) && !xs) xm++; - } - } else if (round && sticky) { - if ((ieee754_csr.rm == IEEE754_RU && !xs) - || (ieee754_csr.rm == IEEE754_RD && xs) - || (ieee754_csr.rm == IEEE754_RN)) { + break; + case IEEE754_RD: /* toward -Infinity */ + if ((round || sticky) && xs) xm++; - } + break; + } + if ((xm >> 63) != 0) { + /* This can happen after rounding */ + SETCX(IEEE754_INVALID_OPERATION); + return ieee754di_xcpt(ieee754di_indef(), "dp_tlong", x); } + if (round || sticky) + SETCX(IEEE754_INEXACT); } if (xs) return -xm; @@ -128,14 +114,14 @@ long long ieee754dp_tlong(ieee754dp x) } -unsigned long long ieee754dp_tulong(ieee754dp x) +u64 ieee754dp_tulong(ieee754dp x) { ieee754dp hb = ieee754dp_1e63(); /* what if x < 0 ?? */ if (ieee754dp_lt(x, hb)) - return (unsigned long long) ieee754dp_tlong(x); + return (u64) ieee754dp_tlong(x); - return (unsigned long long) ieee754dp_tlong(ieee754dp_sub(x, hb)) | + return (u64) ieee754dp_tlong(ieee754dp_sub(x, hb)) | (1ULL << 63); } --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/math-emu/dsemul.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,173 @@ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "ieee754.h" +#include "dsemul.h" + +/* Strap kernel emulator for full MIPS IV emulation */ + +#ifdef __mips +#undef __mips +#endif +#define __mips 4 + +extern struct mips_fpu_emulator_private fpuemuprivate; + + +/* + * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when + * we have to emulate the instruction in a COP1 branch delay slot. Do + * not change cp0_epc due to the instruction + * + * According to the spec: + * 1) it shouldnt be a branch :-) + * 2) it can be a COP instruction :-( + * 3) if we are tring to run a protected memory space we must take + * special care on memory access instructions :-( + */ + +/* + * "Trampoline" return routine to catch exception following + * execution of delay-slot instruction execution. + */ + +struct emuframe { + mips_instruction emul; + mips_instruction badinst; + mips_instruction cookie; + gpreg_t epc; +}; + +int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc) +{ + extern asmlinkage void handle_dsemulret(void); + mips_instruction *dsemul_insns; + struct emuframe *fr; + int err; + + if (ir == 0) { /* a nop is easy */ + regs->cp0_epc = cpc; + regs->cp0_cause &= ~CAUSEF_BD; + return 0; + } +#ifdef DSEMUL_TRACE + printk("dsemul %lx %lx\n", regs->cp0_epc, cpc); + +#endif + + /* + * The strategy is to push the instruction onto the user stack + * and put a trap after it which we can catch and jump to + * the required address any alternative apart from full + * instruction emulation!!. + * + * Algorithmics used a system call instruction, and + * borrowed that vector. MIPS/Linux version is a bit + * more heavyweight in the interests of portability and + * multiprocessor support. For Linux we generate a + * an unaligned access and force an address error exception. + * + * For embedded systems (stand-alone) we prefer to use a + * non-existing CP1 instruction. This prevents us from emulating + * branches, but gives us a cleaner interface to the exception + * handler (single entry point). + */ + + /* Ensure that the two instructions are in the same cache line */ + dsemul_insns = (mips_instruction *) REG_TO_VA ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); + fr = (struct emuframe *) dsemul_insns; + + /* Verify that the stack pointer is not competely insane */ + if (unlikely(verify_area(VERIFY_WRITE, fr, sizeof(struct emuframe)))) + return SIGBUS; + + err = __put_user(ir, &fr->emul); + err |= __put_user((mips_instruction)BADINST, &fr->badinst); + err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); + err |= __put_user(cpc, &fr->epc); + + if (unlikely(err)) { + fpuemuprivate.stats.errors++; + return SIGBUS; + } + + regs->cp0_epc = VA_TO_REG & fr->emul; + + flush_cache_sigtramp((unsigned long)&fr->badinst); + + return SIGILL; /* force out of emulation loop */ +} + +int do_dsemulret(struct pt_regs *xcp) +{ + struct emuframe *fr; + gpreg_t epc; + u32 insn, cookie; + int err = 0; + + fr = (struct emuframe *) (xcp->cp0_epc - sizeof(mips_instruction)); + + /* + * If we can't even access the area, something is very wrong, but we'll + * leave that to the default handling + */ + if (verify_area(VERIFY_READ, fr, sizeof(struct emuframe))) + return 0; + + /* + * Do some sanity checking on the stackframe: + * + * - Is the instruction pointed to by the EPC an BADINST? + * - Is the following memory word the BD_COOKIE? + */ + err = __get_user(insn, &fr->badinst); + err |= __get_user(cookie, &fr->cookie); + + if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) { + fpuemuprivate.stats.errors++; + + return 0; + } + + /* + * At this point, we are satisfied that it's a BD emulation trap. Yes, + * a user might have deliberately put two malformed and useless + * instructions in a row in his program, in which case he's in for a + * nasty surprise - the next instruction will be treated as a + * continuation address! Alas, this seems to be the only way that we + * can handle signals, recursion, and longjmps() in the context of + * emulating the branch delay instruction. + */ + +#ifdef DSEMUL_TRACE + printk("dsemulret\n"); +#endif + if (__get_user(epc, &fr->epc)) { /* Saved EPC */ + /* This is not a good situation to be in */ + force_sig(SIGBUS, current); + + return 0; + } + + /* Set EPC to return to post-branch instruction */ + xcp->cp0_epc = epc; + + return 1; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/math-emu/dsemul.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,23 @@ +typedef long gpreg_t; +typedef void *vaddr_t; + +#define REG_TO_VA (vaddr_t) +#define VA_TO_REG (gpreg_t) + +int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc); +int do_dsemulret(struct pt_regs *xcp); + +/* Instruction which will always cause an address error */ +#define AdELOAD 0x8c000001 /* lw $0,1($0) */ +/* Instruction which will plainly cause a CP1 exception when FPU is disabled */ +#define CP1UNDEF 0x44400001 /* cfc1 $0,$0 undef */ + +/* Instruction inserted following the badinst to further tag the sequence */ +#define BD_COOKIE 0x0000bd36 /* tne $0,$0 with baggage */ + +/* Setup which instruction to use for trampoline */ +#ifdef STANDALONE_EMULATOR +#define BADINST CP1UNDEF +#else +#define BADINST AdELOAD +#endif --- linux-2.5.73/arch/mips/math-emu/ieee754.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/ieee754.c 2003-06-27 15:56:23.000000000 -0700 @@ -50,7 +50,7 @@ const char *const ieee754_cname[] = { "SNaN", }; -/* the control status register +/* the control status register */ struct ieee754_csr ieee754_csr; @@ -77,7 +77,7 @@ const struct ieee754dp_konst __ieee754dp DPSTR(1, 3 + DP_EBIAS, 0x40000, 0), /* - 10.0 */ DPSTR(0, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* + infinity */ DPSTR(1, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* - infinity */ - DPSTR(0, DP_EMAX + 1 + DP_EBIAS, 0x40000, 0), /* + indef quiet Nan */ + DPSTR(0,DP_EMAX+1+DP_EBIAS,0x7FFFF,0xFFFFFFFF), /* + indef quiet Nan */ DPSTR(0, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* + max */ DPSTR(1, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* - max */ DPSTR(0, DP_EMIN + DP_EBIAS, 0, 0), /* + min normal */ @@ -97,7 +97,7 @@ const struct ieee754sp_konst __ieee754sp SPSTR(1, 3 + SP_EBIAS, 0x200000), /* - 10.0 */ SPSTR(0, SP_EMAX + 1 + SP_EBIAS, 0), /* + infinity */ SPSTR(1, SP_EMAX + 1 + SP_EBIAS, 0), /* - infinity */ - SPSTR(0, SP_EMAX + 1 + SP_EBIAS, 0x200000), /* + indef quiet Nan */ + SPSTR(0,SP_EMAX+1+SP_EBIAS,0x3FFFFF), /* + indef quiet Nan */ SPSTR(0, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* + max normal */ SPSTR(1, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* - max normal */ SPSTR(0, SP_EMIN + SP_EBIAS, 0), /* + min normal */ @@ -123,7 +123,7 @@ int ieee754si_xcpt(int r, const char *op return ax.rv.si; } -long long ieee754di_xcpt(long long r, const char *op, ...) +s64 ieee754di_xcpt(s64 r, const char *op, ...) { struct ieee754xctx ax; --- linux-2.5.73/arch/mips/math-emu/ieee754d.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/ieee754d.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,12 +1,11 @@ -/* some debug functions -*/ /* + * Some debug functions + * * MIPS floating point support + * * Copyright (C) 1994-2000 Algorithmics Ltd. All rights reserved. * http://www.algor.co.uk * - * ######################################################################## - * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. @@ -20,17 +19,14 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * ######################################################################## - */ - -/************************************************************************** * Nov 7, 2000 - * Modified to build and operate in Linux kernel environment. + * Modified to build and operate in Linux kernel environment. * * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - *************************************************************************/ + */ +#include #include "ieee754.h" #define DP_EBIAS 1023 @@ -43,12 +39,12 @@ #define SP_EMAX 127 #define SP_FBITS 23 -#define DP_MBIT(x) ((unsigned long long)1 << (x)) +#define DP_MBIT(x) ((u64)1 << (x)) #define DP_HIDDEN_BIT DP_MBIT(DP_FBITS) #define DP_SIGN_BIT DP_MBIT(63) -#define SP_MBIT(x) ((unsigned long)1 << (x)) +#define SP_MBIT(x) ((u32)1 << (x)) #define SP_HIDDEN_BIT SP_MBIT(SP_FBITS) #define SP_SIGN_BIT SP_MBIT(31) --- linux-2.5.73/arch/mips/math-emu/ieee754dp.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/ieee754dp.c 2003-06-27 15:56:23.000000000 -0700 @@ -42,9 +42,7 @@ int ieee754dp_isnan(ieee754dp x) int ieee754dp_issnan(ieee754dp x) { assert(ieee754dp_isnan(x)); - if (ieee754_csr.noq) - return 1; - return !(DPMANT(x) & DP_MBIT(DP_MBITS - 1)); + return ((DPMANT(x) & DP_MBIT(DP_MBITS-1)) == DP_MBIT(DP_MBITS-1)); } @@ -71,12 +69,13 @@ ieee754dp ieee754dp_nanxcpt(ieee754dp r, if (!ieee754dp_issnan(r)) /* QNAN does not cause invalid op !! */ return r; - if (!SETCX(IEEE754_INVALID_OPERATION)) { + if (!SETANDTESTCX(IEEE754_INVALID_OPERATION)) { /* not enabled convert to a quiet NaN */ - if (ieee754_csr.noq) + DPMANT(r) &= (~DP_MBIT(DP_MBITS-1)); + if (ieee754dp_isnan(r)) return r; - DPMANT(r) |= DP_MBIT(DP_MBITS - 1); - return r; + else + return ieee754dp_indef(); } ax.op = op; @@ -99,12 +98,38 @@ ieee754dp ieee754dp_bestnan(ieee754dp x, } +static u64 get_rounding(int sn, u64 xm) +{ + /* inexact must round of 3 bits + */ + if (xm & (DP_MBIT(3) - 1)) { + switch (ieee754_csr.rm) { + case IEEE754_RZ: + break; + case IEEE754_RN: + xm += 0x3 + ((xm >> 3) & 1); + /* xm += (xm&0x8)?0x4:0x3 */ + break; + case IEEE754_RU: /* toward +Infinity */ + if (!sn) /* ?? */ + xm += 0x8; + break; + case IEEE754_RD: /* toward -Infinity */ + if (sn) /* ?? */ + xm += 0x8; + break; + } + } + return xm; +} + + /* generate a normal/denormal number with over,under handling * sn is sign * xe is an unbiased exponent * xm is 3bit extended precision value. */ -ieee754dp ieee754dp_format(int sn, int xe, unsigned long long xm) +ieee754dp ieee754dp_format(int sn, int xe, u64 xm) { assert(xm); /* we don't gen exact zeros (probably should) */ @@ -117,40 +142,59 @@ ieee754dp ieee754dp_format(int sn, int x if (ieee754_csr.nod) { SETCX(IEEE754_UNDERFLOW); - return ieee754dp_zero(sn); - } + SETCX(IEEE754_INEXACT); - /* sticky right shift es bits - */ - xm = XDPSRS(xm, es); - xe += es; + switch(ieee754_csr.rm) { + case IEEE754_RN: + return ieee754dp_zero(sn); + case IEEE754_RZ: + return ieee754dp_zero(sn); + case IEEE754_RU: /* toward +Infinity */ + if(sn == 0) + return ieee754dp_min(0); + else + return ieee754dp_zero(1); + case IEEE754_RD: /* toward -Infinity */ + if(sn == 0) + return ieee754dp_zero(0); + else + return ieee754dp_min(1); + } + } - assert((xm & (DP_HIDDEN_BIT << 3)) == 0); - assert(xe == DP_EMIN); + if (xe == DP_EMIN - 1 + && get_rounding(sn, xm) >> (DP_MBITS + 1 + 3)) + { + /* Not tiny after rounding */ + SETCX(IEEE754_INEXACT); + xm = get_rounding(sn, xm); + xm >>= 1; + /* Clear grs bits */ + xm &= ~(DP_MBIT(3) - 1); + xe++; + } + else { + /* sticky right shift es bits + */ + xm = XDPSRS(xm, es); + xe += es; + assert((xm & (DP_HIDDEN_BIT << 3)) == 0); + assert(xe == DP_EMIN); + } } if (xm & (DP_MBIT(3) - 1)) { SETCX(IEEE754_INEXACT); - /* inexact must round of 3 bits - */ - switch (ieee754_csr.rm) { - case IEEE754_RZ: - break; - case IEEE754_RN: - xm += 0x3 + ((xm >> 3) & 1); - /* xm += (xm&0x8)?0x4:0x3 */ - break; - case IEEE754_RU: /* toward +Infinity */ - if (!sn) /* ?? */ - xm += 0x8; - break; - case IEEE754_RD: /* toward -Infinity */ - if (sn) /* ?? */ - xm += 0x8; - break; + if ((xm & (DP_HIDDEN_BIT << 3)) == 0) { + SETCX(IEEE754_UNDERFLOW); } - /* adjust exponent for rounding add overflowing + + /* inexact must round of 3 bits */ - if (xm >> (DP_MBITS + 3 + 1)) { /* add causes mantissa overflow */ + xm = get_rounding(sn, xm); + /* adjust exponent for rounding add overflowing + */ + if (xm >> (DP_MBITS + 3 + 1)) { + /* add causes mantissa overflow */ xm >>= 1; xe++; } @@ -163,6 +207,7 @@ ieee754dp ieee754dp_format(int sn, int x if (xe > DP_EMAX) { SETCX(IEEE754_OVERFLOW); + SETCX(IEEE754_INEXACT); /* -O can be table indexed by (rm,sn) */ switch (ieee754_csr.rm) { case IEEE754_RN: @@ -186,7 +231,8 @@ ieee754dp ieee754dp_format(int sn, int x if ((xm & DP_HIDDEN_BIT) == 0) { /* we underflow (tiny/zero) */ assert(xe == DP_EMIN); - SETCX(IEEE754_UNDERFLOW); + if (ieee754_csr.mx & IEEE754_UNDERFLOW) + SETCX(IEEE754_UNDERFLOW); return builddp(sn, DP_EMIN - 1 + DP_EBIAS, xm); } else { assert((xm >> (DP_MBITS + 1)) == 0); /* no execess */ --- linux-2.5.73/arch/mips/math-emu/ieee754dp.h 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/ieee754dp.h 2003-06-27 15:56:23.000000000 -0700 @@ -1,4 +1,4 @@ -/* +/* * IEEE754 floating point * double precision internal header file */ @@ -46,7 +46,7 @@ #define DPDNORMX DPDNORMx(xm,xe) #define DPDNORMY DPDNORMx(ym,ye) -static __inline ieee754dp builddp(int s, int bx, unsigned long long m) +static __inline ieee754dp builddp(int s, int bx, u64 m) { ieee754dp r; @@ -64,11 +64,11 @@ static __inline ieee754dp builddp(int s, extern int ieee754dp_isnan(ieee754dp); extern int ieee754dp_issnan(ieee754dp); extern int ieee754si_xcpt(int, const char *, ...); -extern long long ieee754di_xcpt(long long, const char *, ...); +extern s64 ieee754di_xcpt(s64, const char *, ...); extern ieee754dp ieee754dp_xcpt(ieee754dp, const char *, ...); extern ieee754dp ieee754dp_nanxcpt(ieee754dp, const char *, ...); extern ieee754dp ieee754dp_bestnan(ieee754dp, ieee754dp); -extern ieee754dp ieee754dp_format(int, int, unsigned long long); +extern ieee754dp ieee754dp_format(int, int, u64); #define DPNORMRET2(s,e,m,name,a0,a1) \ --- linux-2.5.73/arch/mips/math-emu/ieee754.h 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/ieee754.h 2003-06-27 15:56:23.000000000 -0700 @@ -26,7 +26,7 @@ /************************************************************************** * Nov 7, 2000 - * Modification to allow integration with Linux kernel + * Modification to allow integration with Linux kernel * * Kevin D. Kissell, kevink@mips.com and Carsten Langgard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. @@ -36,8 +36,8 @@ /* Going from Algorithmics to Linux native environment, add this */ #include -/* - * Not very pretty, but the Linux kernel's normal va_list definition +/* + * Not very pretty, but the Linux kernel's normal va_list definition * does not allow it to be used as a structure element, as it is here. */ #ifndef _STDARG_H @@ -71,18 +71,18 @@ struct ieee754sp_konst { typedef union _ieee754dp { struct ieee754dp_konst oparts; struct { - unsigned long long mant:52; + u64 mant:52; unsigned int bexp:11; unsigned int sign:1; } parts; - unsigned long long bits; + u64 bits; double d; } ieee754dp; typedef union _ieee754sp { struct ieee754sp_konst parts; float f; - unsigned long bits; + u32 bits; } ieee754sp; #endif @@ -98,10 +98,10 @@ typedef union _ieee754dp { struct { unsigned int sign:1; unsigned int bexp:11; - unsigned long long mant:52; + u64 mant:52; } parts; double d; - unsigned long long bits; + u64 bits; } ieee754dp; struct ieee754sp_konst { @@ -113,7 +113,7 @@ struct ieee754sp_konst { typedef union _ieee754sp { struct ieee754sp_konst parts; float f; - unsigned long bits; + u32 bits; } ieee754sp; #endif @@ -138,16 +138,16 @@ ieee754sp ieee754sp_div(ieee754sp x, iee ieee754sp ieee754sp_fint(int x); ieee754sp ieee754sp_funs(unsigned x); -ieee754sp ieee754sp_flong(long long x); -ieee754sp ieee754sp_fulong(unsigned long long x); +ieee754sp ieee754sp_flong(s64 x); +ieee754sp ieee754sp_fulong(u64 x); ieee754sp ieee754sp_fdp(ieee754dp x); int ieee754sp_tint(ieee754sp x); unsigned int ieee754sp_tuns(ieee754sp x); -long long ieee754sp_tlong(ieee754sp x); -unsigned long long ieee754sp_tulong(ieee754sp x); +s64 ieee754sp_tlong(ieee754sp x); +u64 ieee754sp_tulong(ieee754sp x); -int ieee754sp_cmp(ieee754sp x, ieee754sp y, int cop); +int ieee754sp_cmp(ieee754sp x, ieee754sp y, int cop, int sig); /* * basic sp math */ @@ -179,14 +179,14 @@ ieee754dp ieee754dp_abs(ieee754dp x); ieee754dp ieee754dp_neg(ieee754dp x); ieee754dp ieee754dp_scalb(ieee754dp x, int); -/* return exponent as integer in floating point format +/* return exponent as integer in floating point format */ ieee754dp ieee754dp_logb(ieee754dp x); ieee754dp ieee754dp_fint(int x); ieee754dp ieee754dp_funs(unsigned x); -ieee754dp ieee754dp_flong(long long x); -ieee754dp ieee754dp_fulong(unsigned long long x); +ieee754dp ieee754dp_flong(s64 x); +ieee754dp ieee754dp_fulong(u64 x); ieee754dp ieee754dp_fsp(ieee754sp x); ieee754dp ieee754dp_ceil(ieee754dp x); @@ -195,10 +195,10 @@ ieee754dp ieee754dp_trunc(ieee754dp x); int ieee754dp_tint(ieee754dp x); unsigned int ieee754dp_tuns(ieee754dp x); -long long ieee754dp_tlong(ieee754dp x); -unsigned long long ieee754dp_tulong(ieee754dp x); +s64 ieee754dp_tlong(ieee754dp x); +u64 ieee754dp_tulong(ieee754dp x); -int ieee754dp_cmp(ieee754dp x, ieee754dp y, int cop); +int ieee754dp_cmp(ieee754dp x, ieee754dp y, int cop, int sig); /* * basic sp math */ @@ -214,7 +214,7 @@ ieee754dp ieee754dp_sqrt(ieee754dp x); -/* 5 types of floating point number +/* 5 types of floating point number */ #define IEEE754_CLASS_NORM 0x00 #define IEEE754_CLASS_ZERO 0x01 @@ -238,7 +238,7 @@ extern const char *const ieee754_cname[] #define IEEE754_CGT 0x04 #define IEEE754_CUN 0x08 -/* rounding mode +/* rounding mode */ #define IEEE754_RN 0 /* round to nearest */ #define IEEE754_RZ 1 /* round toward zero */ @@ -253,65 +253,65 @@ extern const char *const ieee754_cname[] */ static __inline int ieee754sp_eq(ieee754sp x, ieee754sp y) { - return ieee754sp_cmp(x, y, IEEE754_CEQ); + return ieee754sp_cmp(x, y, IEEE754_CEQ, 0); } static __inline int ieee754sp_ne(ieee754sp x, ieee754sp y) { return ieee754sp_cmp(x, y, - IEEE754_CLT | IEEE754_CGT | IEEE754_CUN); + IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 0); } static __inline int ieee754sp_lt(ieee754sp x, ieee754sp y) { - return ieee754sp_cmp(x, y, IEEE754_CLT); + return ieee754sp_cmp(x, y, IEEE754_CLT, 0); } static __inline int ieee754sp_le(ieee754sp x, ieee754sp y) { - return ieee754sp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ); + return ieee754sp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ, 0); } static __inline int ieee754sp_gt(ieee754sp x, ieee754sp y) { - return ieee754sp_cmp(x, y, IEEE754_CGT); + return ieee754sp_cmp(x, y, IEEE754_CGT, 0); } static __inline int ieee754sp_ge(ieee754sp x, ieee754sp y) { - return ieee754sp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ); + return ieee754sp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ, 0); } static __inline int ieee754dp_eq(ieee754dp x, ieee754dp y) { - return ieee754dp_cmp(x, y, IEEE754_CEQ); + return ieee754dp_cmp(x, y, IEEE754_CEQ, 0); } static __inline int ieee754dp_ne(ieee754dp x, ieee754dp y) { return ieee754dp_cmp(x, y, - IEEE754_CLT | IEEE754_CGT | IEEE754_CUN); + IEEE754_CLT | IEEE754_CGT | IEEE754_CUN, 0); } static __inline int ieee754dp_lt(ieee754dp x, ieee754dp y) { - return ieee754dp_cmp(x, y, IEEE754_CLT); + return ieee754dp_cmp(x, y, IEEE754_CLT, 0); } static __inline int ieee754dp_le(ieee754dp x, ieee754dp y) { - return ieee754dp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ); + return ieee754dp_cmp(x, y, IEEE754_CLT | IEEE754_CEQ, 0); } static __inline int ieee754dp_gt(ieee754dp x, ieee754dp y) { - return ieee754dp_cmp(x, y, IEEE754_CGT); + return ieee754dp_cmp(x, y, IEEE754_CGT, 0); } static __inline int ieee754dp_ge(ieee754dp x, ieee754dp y) { - return ieee754dp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ); + return ieee754dp_cmp(x, y, IEEE754_CGT | IEEE754_CEQ, 0); } @@ -321,11 +321,10 @@ ieee754dp ieee754dp_fstr(const char *s, char *ieee754dp_tstr(ieee754dp x, int prec, int fmt, int af); -/* the control status register +/* the control status register */ struct ieee754_csr { unsigned pad:13; - unsigned noq:1; /* set 1 for no quiet NaN's */ unsigned nod:1; /* set 1 for no denormalised numbers */ unsigned cx:5; /* exceptions this operation */ unsigned mx:5; /* exception enable mask */ @@ -351,7 +350,7 @@ static __inline unsigned ieee754_getcx(v return (ieee754_csr.cx); } -/* test for current exception condition +/* test for current exception condition */ static __inline int ieee754_cxtest(unsigned n) { @@ -373,7 +372,7 @@ static __inline unsigned ieee754_clrsx(v return (ieee754_csr.sx = 0); } -/* test for sticky exception condition +/* test for sticky exception condition */ static __inline int ieee754_sxtest(unsigned n) { @@ -451,13 +450,13 @@ extern const struct ieee754sp_konst __ie #define ieee754sp_1e63() \ (ieee754sp_spcvals[IEEE754_SPCVAL_P1E63]) -/* indefinite integer value +/* indefinite integer value */ -#define ieee754si_indef() INT_MIN -#ifdef LONG_LONG_MIN -#define ieee754di_indef() LONG_LONG_MIN +#define ieee754si_indef() INT_MAX +#ifdef LONG_LONG_MAX +#define ieee754di_indef() LONG_LONG_MAX #else -#define ieee754di_indef() (-9223372036854775807LL-1) +#define ieee754di_indef() ((s64)(~0ULL>>1)) #endif /* IEEE exception context, passed to handler */ @@ -471,7 +470,7 @@ struct ieee754xctx { ieee754xp xp; /* extended precision */ #endif int si; /* standard signed integer (32bits) */ - long long di; /* extended signed integer (64bits) */ + s64 di; /* extended signed integer (64bits) */ } rv; /* default result format implied by op */ va_list ap; }; --- linux-2.5.73/arch/mips/math-emu/ieee754int.h 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/ieee754int.h 2003-06-27 15:56:23.000000000 -0700 @@ -1,4 +1,4 @@ -/* +/* * IEEE754 floating point * common internal header file */ @@ -38,11 +38,11 @@ #define SP_EMAX 127 #define SP_MBITS 23 -#define DP_MBIT(x) ((unsigned long long)1 << (x)) +#define DP_MBIT(x) ((u64)1 << (x)) #define DP_HIDDEN_BIT DP_MBIT(DP_MBITS) #define DP_SIGN_BIT DP_MBIT(63) -#define SP_MBIT(x) ((unsigned long)1 << (x)) +#define SP_MBIT(x) ((u32)1 << (x)) #define SP_HIDDEN_BIT SP_MBIT(SP_MBITS) #define SP_SIGN_BIT SP_MBIT(31) @@ -61,7 +61,10 @@ (ieee754_csr.cx = 0) #define SETCX(x) \ - (ieee754_csr.cx |= (x),ieee754_csr.sx |= (x),ieee754_csr.mx & (x)) + (ieee754_csr.cx |= (x),ieee754_csr.sx |= (x)) + +#define SETANDTESTCX(x) \ + (SETCX(x),ieee754_csr.mx & (x)) #define TSTX() \ (ieee754_csr.cx & ieee754_csr.mx) @@ -82,9 +85,9 @@ if(vm == 0)\ vc = IEEE754_CLASS_INF;\ else if(vm & SP_MBIT(SP_MBITS-1)) \ - vc = IEEE754_CLASS_QNAN;\ - else \ vc = IEEE754_CLASS_SNAN;\ + else \ + vc = IEEE754_CLASS_QNAN;\ } else if(ve == SP_EMIN-1+SP_EBIAS) {\ if(vm) {\ ve = SP_EMIN;\ @@ -102,10 +105,10 @@ #define COMPXDP \ -unsigned long long xm; int xe; int xs; int xc +u64 xm; int xe; int xs; int xc #define COMPYDP \ -unsigned long long ym; int ye; int ys; int yc +u64 ym; int ye; int ys; int yc #define EXPLODEDP(v,vc,vs,ve,vm) \ {\ @@ -116,9 +119,9 @@ unsigned long long ym; int ye; int ys; i if(vm == 0)\ vc = IEEE754_CLASS_INF;\ else if(vm & DP_MBIT(DP_MBITS-1)) \ - vc = IEEE754_CLASS_QNAN;\ - else \ vc = IEEE754_CLASS_SNAN;\ + else \ + vc = IEEE754_CLASS_QNAN;\ } else if(ve == DP_EMIN-1+DP_EBIAS) {\ if(vm) {\ ve = DP_EMIN;\ @@ -133,3 +136,30 @@ unsigned long long ym; int ye; int ys; i } #define EXPLODEXDP EXPLODEDP(x,xc,xs,xe,xm) #define EXPLODEYDP EXPLODEDP(y,yc,ys,ye,ym) + +#define FLUSHDP(v,vc,vs,ve,vm) \ + if(vc==IEEE754_CLASS_DNORM) {\ + if(ieee754_csr.nod) {\ + SETCX(IEEE754_INEXACT);\ + vc = IEEE754_CLASS_ZERO;\ + ve = DP_EMIN-1+DP_EBIAS;\ + vm = 0;\ + v = ieee754dp_zero(vs);\ + }\ + } + +#define FLUSHSP(v,vc,vs,ve,vm) \ + if(vc==IEEE754_CLASS_DNORM) {\ + if(ieee754_csr.nod) {\ + SETCX(IEEE754_INEXACT);\ + vc = IEEE754_CLASS_ZERO;\ + ve = SP_EMIN-1+SP_EBIAS;\ + vm = 0;\ + v = ieee754sp_zero(vs);\ + }\ + } + +#define FLUSHXDP FLUSHDP(x,xc,xs,xe,xm) +#define FLUSHYDP FLUSHDP(y,yc,ys,ye,ym) +#define FLUSHXSP FLUSHSP(x,xc,xs,xe,xm) +#define FLUSHYSP FLUSHSP(y,yc,ys,ye,ym) --- linux-2.5.73/arch/mips/math-emu/ieee754sp.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/ieee754sp.c 2003-06-27 15:56:23.000000000 -0700 @@ -42,9 +42,7 @@ int ieee754sp_isnan(ieee754sp x) int ieee754sp_issnan(ieee754sp x) { assert(ieee754sp_isnan(x)); - if (ieee754_csr.noq) - return 1; - return !(SPMANT(x) & SP_MBIT(SP_MBITS - 1)); + return (SPMANT(x) & SP_MBIT(SP_MBITS-1)); } @@ -72,12 +70,13 @@ ieee754sp ieee754sp_nanxcpt(ieee754sp r, if (!ieee754sp_issnan(r)) /* QNAN does not cause invalid op !! */ return r; - if (!SETCX(IEEE754_INVALID_OPERATION)) { + if (!SETANDTESTCX(IEEE754_INVALID_OPERATION)) { /* not enabled convert to a quiet NaN */ - if (ieee754_csr.noq) + SPMANT(r) &= (~SP_MBIT(SP_MBITS-1)); + if (ieee754sp_isnan(r)) return r; - SPMANT(r) |= SP_MBIT(SP_MBITS - 1); - return r; + else + return ieee754sp_indef(); } ax.op = op; @@ -100,6 +99,32 @@ ieee754sp ieee754sp_bestnan(ieee754sp x, } +static unsigned get_rounding(int sn, unsigned xm) +{ + /* inexact must round of 3 bits + */ + if (xm & (SP_MBIT(3) - 1)) { + switch (ieee754_csr.rm) { + case IEEE754_RZ: + break; + case IEEE754_RN: + xm += 0x3 + ((xm >> 3) & 1); + /* xm += (xm&0x8)?0x4:0x3 */ + break; + case IEEE754_RU: /* toward +Infinity */ + if (!sn) /* ?? */ + xm += 0x8; + break; + case IEEE754_RD: /* toward -Infinity */ + if (sn) /* ?? */ + xm += 0x8; + break; + } + } + return xm; +} + + /* generate a normal/denormal number with over,under handling * sn is sign * xe is an unbiased exponent @@ -118,39 +143,58 @@ ieee754sp ieee754sp_format(int sn, int x if (ieee754_csr.nod) { SETCX(IEEE754_UNDERFLOW); - return ieee754sp_zero(sn); - } + SETCX(IEEE754_INEXACT); - /* sticky right shift es bits - */ - SPXSRSXn(es); + switch(ieee754_csr.rm) { + case IEEE754_RN: + return ieee754sp_zero(sn); + case IEEE754_RZ: + return ieee754sp_zero(sn); + case IEEE754_RU: /* toward +Infinity */ + if(sn == 0) + return ieee754sp_min(0); + else + return ieee754sp_zero(1); + case IEEE754_RD: /* toward -Infinity */ + if(sn == 0) + return ieee754sp_zero(0); + else + return ieee754sp_min(1); + } + } - assert((xm & (SP_HIDDEN_BIT << 3)) == 0); - assert(xe == SP_EMIN); + if (xe == SP_EMIN - 1 + && get_rounding(sn, xm) >> (SP_MBITS + 1 + 3)) + { + /* Not tiny after rounding */ + SETCX(IEEE754_INEXACT); + xm = get_rounding(sn, xm); + xm >>= 1; + /* Clear grs bits */ + xm &= ~(SP_MBIT(3) - 1); + xe++; + } + else { + /* sticky right shift es bits + */ + SPXSRSXn(es); + assert((xm & (SP_HIDDEN_BIT << 3)) == 0); + assert(xe == SP_EMIN); + } } if (xm & (SP_MBIT(3) - 1)) { SETCX(IEEE754_INEXACT); - /* inexact must round of 3 bits - */ - switch (ieee754_csr.rm) { - case IEEE754_RZ: - break; - case IEEE754_RN: - xm += 0x3 + ((xm >> 3) & 1); - /* xm += (xm&0x8)?0x4:0x3 */ - break; - case IEEE754_RU: /* toward +Infinity */ - if (!sn) /* ?? */ - xm += 0x8; - break; - case IEEE754_RD: /* toward -Infinity */ - if (sn) /* ?? */ - xm += 0x8; - break; + if ((xm & (SP_HIDDEN_BIT << 3)) == 0) { + SETCX(IEEE754_UNDERFLOW); } - /* adjust exponent for rounding add overflowing + + /* inexact must round of 3 bits */ - if (xm >> (SP_MBITS + 1 + 3)) { /* add causes mantissa overflow */ + xm = get_rounding(sn, xm); + /* adjust exponent for rounding add overflowing + */ + if (xm >> (SP_MBITS + 1 + 3)) { + /* add causes mantissa overflow */ xm >>= 1; xe++; } @@ -163,6 +207,7 @@ ieee754sp ieee754sp_format(int sn, int x if (xe > SP_EMAX) { SETCX(IEEE754_OVERFLOW); + SETCX(IEEE754_INEXACT); /* -O can be table indexed by (rm,sn) */ switch (ieee754_csr.rm) { case IEEE754_RN: @@ -186,7 +231,8 @@ ieee754sp ieee754sp_format(int sn, int x if ((xm & SP_HIDDEN_BIT) == 0) { /* we underflow (tiny/zero) */ assert(xe == SP_EMIN); - SETCX(IEEE754_UNDERFLOW); + if (ieee754_csr.mx & IEEE754_UNDERFLOW) + SETCX(IEEE754_UNDERFLOW); return buildsp(sn, SP_EMIN - 1 + SP_EBIAS, xm); } else { assert((xm >> (SP_MBITS + 1)) == 0); /* no execess */ --- linux-2.5.73/arch/mips/math-emu/ieee754sp.h 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/ieee754sp.h 2003-06-27 15:56:23.000000000 -0700 @@ -1,4 +1,4 @@ -/* +/* * IEEE754 floating point * double precision internal header file */ @@ -70,7 +70,7 @@ static __inline ieee754sp buildsp(int s, extern int ieee754sp_isnan(ieee754sp); extern int ieee754sp_issnan(ieee754sp); extern int ieee754si_xcpt(int, const char *, ...); -extern long long ieee754di_xcpt(long long, const char *, ...); +extern s64 ieee754di_xcpt(s64, const char *, ...); extern ieee754sp ieee754sp_xcpt(ieee754sp, const char *, ...); extern ieee754sp ieee754sp_nanxcpt(ieee754sp, const char *, ...); extern ieee754sp ieee754sp_bestnan(ieee754sp, ieee754sp); --- linux-2.5.73/arch/mips/math-emu/ieee754xcpt.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/ieee754xcpt.c 2003-06-27 15:56:23.000000000 -0700 @@ -23,12 +23,13 @@ /************************************************************************** * Nov 7, 2000 - * Added preprocessor hacks to map to Linux kernel diagnostics. + * Added preprocessor hacks to map to Linux kernel diagnostics. * * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. *************************************************************************/ +#include #include "ieee754.h" /* @@ -42,7 +43,7 @@ static const char *const rtnames[] = { void ieee754_xcpt(struct ieee754xctx *xcp) { - printk("floating point exception in \"%s\", type=%s\n", + printk(KERN_DEBUG "floating point exception in \"%s\", type=%s\n", xcp->op, rtnames[xcp->rt]); } --- linux-2.5.73/arch/mips/math-emu/kernel_linkage.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/kernel_linkage.c 2003-06-27 15:56:23.000000000 -0700 @@ -20,13 +20,10 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - *************************************************************************/ -/* * Routines corresponding to Linux kernel FP context * manipulation primitives for the Algorithmics MIPS * FPU Emulator */ - #include #include #include @@ -42,10 +39,10 @@ void fpu_emulator_init_fpu(void) { static int first = 1; int i; - + if (first) { first = 0; - printk("Algorithmics/MIPS FPU Emulator v1.4\n"); + printk("Algorithmics/MIPS FPU Emulator v1.5\n"); } current->thread.fpu.soft.sr = 0; --- linux-2.5.73/arch/mips/math-emu/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -8,4 +8,4 @@ obj-y := cp1emu.o ieee754m.o ieee754d.o dp_tint.o dp_fint.o dp_tlong.o dp_flong.o sp_frexp.o sp_modf.o \ sp_div.o sp_mul.o sp_sub.o sp_add.o sp_fdp.o sp_cmp.o sp_logb.o \ sp_scalb.o sp_simple.o sp_tint.o sp_fint.o sp_tlong.o sp_flong.o \ - dp_sqrt.o sp_sqrt.o kernel_linkage.o + dp_sqrt.o sp_sqrt.o kernel_linkage.o dsemul.o --- linux-2.5.73/arch/mips/math-emu/sp_add.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/sp_add.c 2003-06-27 15:56:23.000000000 -0700 @@ -37,27 +37,23 @@ ieee754sp ieee754sp_add(ieee754sp x, iee CLEARCX; - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(ieee754sp_bestnan(x, y), "add", x, - y); + FLUSHXSP; + FLUSHYSP; + switch (CLPAIR(xc, yc)) { + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(y, "add", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754sp_nanxcpt(x, "add", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754sp_bestnan(x, y); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754sp_nanxcpt(ieee754sp_indef(), "add", x, y); case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): @@ -65,6 +61,7 @@ ieee754sp ieee754sp_add(ieee754sp x, iee case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): return y; + case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): @@ -72,7 +69,7 @@ ieee754sp ieee754sp_add(ieee754sp x, iee return x; - /* Inifity handling + /* Infinity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): --- linux-2.5.73/arch/mips/math-emu/sp_cmp.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/sp_cmp.c 2003-06-27 15:56:23.000000000 -0700 @@ -27,15 +27,24 @@ #include "ieee754sp.h" -int ieee754sp_cmp(ieee754sp x, ieee754sp y, int cmp) +int ieee754sp_cmp(ieee754sp x, ieee754sp y, int cmp, int sig) { - CLEARCX; + COMPXSP; + COMPYSP; + + EXPLODEXSP; + EXPLODEYSP; + FLUSHXSP; + FLUSHYSP; + CLEARCX; /* Even clear inexact flag here */ if (ieee754sp_isnan(x) || ieee754sp_isnan(y)) { + if (sig || xc == IEEE754_CLASS_SNAN || yc == IEEE754_CLASS_SNAN) + SETCX(IEEE754_INVALID_OPERATION); if (cmp & IEEE754_CUN) return 1; if (cmp & (IEEE754_CLT | IEEE754_CGT)) { - if (SETCX(IEEE754_INVALID_OPERATION)) + if (sig && SETANDTESTCX(IEEE754_INVALID_OPERATION)) return ieee754si_xcpt(0, "fcmpf", x); } return 0; --- linux-2.5.73/arch/mips/math-emu/sp_div.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/sp_div.c 2003-06-27 15:56:23.000000000 -0700 @@ -32,32 +32,28 @@ ieee754sp ieee754sp_div(ieee754sp x, iee COMPXSP; COMPYSP; - CLEARCX; - EXPLODEXSP; EXPLODEYSP; - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(ieee754sp_bestnan(x, y), "div", x, - y); + CLEARCX; + + FLUSHXSP; + FLUSHYSP; + switch (CLPAIR(xc, yc)) { + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(y, "div", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754sp_nanxcpt(x, "div", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754sp_bestnan(x, y); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754sp_nanxcpt(ieee754sp_indef(), "div", x, y); case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): @@ -65,6 +61,7 @@ ieee754sp ieee754sp_div(ieee754sp x, iee case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): return y; + case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): --- linux-2.5.73/arch/mips/math-emu/sp_fdp.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/sp_fdp.c 2003-06-27 15:56:23.000000000 -0700 @@ -30,20 +30,24 @@ ieee754sp ieee754sp_fdp(ieee754dp x) { COMPXDP; + ieee754sp nan; + + EXPLODEXDP; CLEARCX; - EXPLODEXDP; + FLUSHXDP; switch (xc) { - case IEEE754_CLASS_QNAN: case IEEE754_CLASS_SNAN: - return ieee754sp_nanxcpt(buildsp(xs, - SP_EMAX + 1 + SP_EBIAS, - (unsigned long) - (xm >> - (DP_MBITS - SP_MBITS))), - "fdp", x); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754sp_nanxcpt(ieee754sp_indef(), "fdp"); + case IEEE754_CLASS_QNAN: + nan = buildsp(xs, SP_EMAX + 1 + SP_EBIAS, (u32) + (xm >> (DP_MBITS - SP_MBITS))); + if (!ieee754sp_isnan(nan)) + nan = ieee754sp_indef(); + return ieee754sp_nanxcpt(nan, "fdp", x); case IEEE754_CLASS_INF: return ieee754sp_inf(xs); case IEEE754_CLASS_ZERO: @@ -51,15 +55,19 @@ ieee754sp ieee754sp_fdp(ieee754dp x) case IEEE754_CLASS_DNORM: /* can't possibly be sp representable */ SETCX(IEEE754_UNDERFLOW); + SETCX(IEEE754_INEXACT); + if ((ieee754_csr.rm == IEEE754_RU && !xs) || + (ieee754_csr.rm == IEEE754_RD && xs)) + return ieee754sp_xcpt(ieee754sp_mind(xs), "fdp", x); return ieee754sp_xcpt(ieee754sp_zero(xs), "fdp", x); case IEEE754_CLASS_NORM: break; } { - unsigned long rm; + u32 rm; - /* convert from DP_MBITS to SP_MBITS+3 with sticky right shift + /* convert from DP_MBITS to SP_MBITS+3 with sticky right shift */ rm = (xm >> (DP_MBITS - (SP_MBITS + 3))) | ((xm << (64 - (DP_MBITS - (SP_MBITS + 3)))) != 0); --- linux-2.5.73/arch/mips/math-emu/sp_fint.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/sp_fint.c 2003-06-27 15:56:23.000000000 -0700 @@ -52,13 +52,13 @@ ieee754sp ieee754sp_fint(int x) xe = SP_MBITS + 3; if (xm >> (SP_MBITS + 1 + 3)) { - /* shunt out overflow bits + /* shunt out overflow bits */ while (xm >> (SP_MBITS + 1 + 3)) { SPXSRSX1(); } } else { - /* normalize in grs extended single precision + /* normalize in grs extended single precision */ while ((xm >> (SP_MBITS + 3)) == 0) { xm <<= 1; --- linux-2.5.73/arch/mips/math-emu/sp_flong.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/sp_flong.c 2003-06-27 15:56:23.000000000 -0700 @@ -27,7 +27,7 @@ #include "ieee754sp.h" -ieee754sp ieee754sp_flong(long long x) +ieee754sp ieee754sp_flong(s64 x) { COMPXDP; /* <--- need 64-bit mantissa temp */ @@ -52,7 +52,7 @@ ieee754sp ieee754sp_flong(long long x) xe = SP_MBITS + 3; if (xm >> (SP_MBITS + 1 + 3)) { - /* shunt out overflow bits + /* shunt out overflow bits */ while (xm >> (SP_MBITS + 1 + 3)) { SPXSRSX1(); @@ -68,9 +68,9 @@ ieee754sp ieee754sp_flong(long long x) } -ieee754sp ieee754sp_fulong(unsigned long long u) +ieee754sp ieee754sp_fulong(u64 u) { - if ((long long) u < 0) + if ((s64) u < 0) return ieee754sp_add(ieee754sp_1e63(), ieee754sp_flong(u & ~(1ULL << 63))); return ieee754sp_flong(u); --- linux-2.5.73/arch/mips/math-emu/sp_frexp.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/sp_frexp.c 2003-06-27 15:56:23.000000000 -0700 @@ -27,7 +27,7 @@ #include "ieee754sp.h" -/* close to ieeep754sp_logb +/* close to ieeep754sp_logb */ ieee754sp ieee754sp_frexp(ieee754sp x, int *eptr) { --- linux-2.5.73/arch/mips/math-emu/sp_modf.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/sp_modf.c 2003-06-27 15:56:23.000000000 -0700 @@ -59,7 +59,7 @@ ieee754sp ieee754sp_modf(ieee754sp x, ie *ip = x; return ieee754sp_zero(xs); } - /* generate ipart mantissa by clearing bottom bits + /* generate ipart mantissa by clearing bottom bits */ *ip = buildsp(xs, xe + SP_EBIAS, ((xm >> (SP_MBITS - xe)) << (SP_MBITS - xe)) & --- linux-2.5.73/arch/mips/math-emu/sp_mul.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/sp_mul.c 2003-06-27 15:56:23.000000000 -0700 @@ -32,32 +32,28 @@ ieee754sp ieee754sp_mul(ieee754sp x, iee COMPXSP; COMPYSP; - CLEARCX; - EXPLODEXSP; EXPLODEYSP; - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(ieee754sp_bestnan(x, y), "mul", x, - y); + CLEARCX; + + FLUSHXSP; + FLUSHYSP; + switch (CLPAIR(xc, yc)) { + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(y, "mul", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754sp_nanxcpt(x, "mul", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754sp_bestnan(x, y); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754sp_nanxcpt(ieee754sp_indef(), "mul", x, y); case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): @@ -65,6 +61,7 @@ ieee754sp ieee754sp_mul(ieee754sp x, iee case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): return y; + case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): --- linux-2.5.73/arch/mips/math-emu/sp_simple.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/sp_simple.c 2003-06-27 15:56:23.000000000 -0700 @@ -42,7 +42,16 @@ ieee754sp ieee754sp_copysign(ieee754sp x ieee754sp ieee754sp_neg(ieee754sp x) { + COMPXSP; + + EXPLODEXSP; CLEARCX; + FLUSHXSP; + + if (xc == IEEE754_CLASS_SNAN) { + SETCX(IEEE754_INVALID_OPERATION); + return ieee754sp_nanxcpt(ieee754sp_indef(), "neg"); + } if (ieee754sp_isnan(x)) /* but not infinity */ return ieee754sp_nanxcpt(x, "neg", x); @@ -55,7 +64,16 @@ ieee754sp ieee754sp_neg(ieee754sp x) ieee754sp ieee754sp_abs(ieee754sp x) { + COMPXSP; + + EXPLODEXSP; CLEARCX; + FLUSHXSP; + + if (xc == IEEE754_CLASS_SNAN) { + SETCX(IEEE754_INVALID_OPERATION); + return ieee754sp_nanxcpt(ieee754sp_indef(), "abs"); + } if (ieee754sp_isnan(x)) /* but not infinity */ return ieee754sp_nanxcpt(x, "abs", x); --- linux-2.5.73/arch/mips/math-emu/sp_sqrt.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/sp_sqrt.c 2003-06-27 15:56:23.000000000 -0700 @@ -27,43 +27,44 @@ #include "ieee754sp.h" -static const struct ieee754sp_konst knan = { - 0, SP_EBIAS + SP_EMAX + 1, 0 -}; - -#define nan ((ieee754sp)knan) - ieee754sp ieee754sp_sqrt(ieee754sp x) { - int sign = (int) 0x80000000; int ix, s, q, m, t, i; unsigned int r; - COMPXDP; + COMPXSP; /* take care of Inf and NaN */ - EXPLODEXDP; + EXPLODEXSP; + CLEARCX; + FLUSHXSP; /* x == INF or NAN? */ switch (xc) { case IEEE754_CLASS_QNAN: - case IEEE754_CLASS_SNAN: /* sqrt(Nan) = Nan */ return ieee754sp_nanxcpt(x, "sqrt"); + case IEEE754_CLASS_SNAN: + SETCX(IEEE754_INVALID_OPERATION); + return ieee754sp_nanxcpt(ieee754sp_indef(), "sqrt"); case IEEE754_CLASS_ZERO: /* sqrt(0) = 0 */ return x; case IEEE754_CLASS_INF: - if (xs) + if (xs) { /* sqrt(-Inf) = Nan */ - return ieee754sp_nanxcpt(nan, "sqrt"); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754sp_nanxcpt(ieee754sp_indef(), "sqrt"); + } /* sqrt(+Inf) = Inf */ return x; case IEEE754_CLASS_DNORM: case IEEE754_CLASS_NORM: - if (xs) + if (xs) { /* sqrt(-x) = Nan */ - return ieee754sp_nanxcpt(nan, "sqrt"); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754sp_nanxcpt(ieee754sp_indef(), "sqrt"); + } break; } @@ -99,6 +100,7 @@ ieee754sp ieee754sp_sqrt(ieee754sp x) } if (ix != 0) { + SETCX(IEEE754_INEXACT); switch (ieee754_csr.rm) { case IEEE754_RP: q += 2; --- linux-2.5.73/arch/mips/math-emu/sp_sub.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/sp_sub.c 2003-06-27 15:56:23.000000000 -0700 @@ -32,32 +32,28 @@ ieee754sp ieee754sp_sub(ieee754sp x, iee COMPXSP; COMPYSP; - CLEARCX; - EXPLODEXSP; EXPLODEYSP; - switch (CLPAIR(xc, yc)) { - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(ieee754sp_bestnan(x, y), "sub", x, - y); + CLEARCX; + FLUSHXSP; + FLUSHYSP; + + switch (CLPAIR(xc, yc)) { + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN): + case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN): case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN): - return ieee754sp_nanxcpt(y, "sub", x, y); - - case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM): case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF): - return ieee754sp_nanxcpt(x, "sub", x, y); - - case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): - return ieee754sp_bestnan(x, y); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754sp_nanxcpt(ieee754sp_indef(), "sub", x, y); case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN): @@ -65,6 +61,7 @@ ieee754sp ieee754sp_sub(ieee754sp x, iee case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN): return y; + case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM): case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM): @@ -72,7 +69,7 @@ ieee754sp ieee754sp_sub(ieee754sp x, iee return x; - /* Inifity handling + /* Infinity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): @@ -170,13 +167,13 @@ ieee754sp ieee754sp_sub(ieee754sp x, iee xe = xe; xs = ys; } - if (xm == 0) + if (xm == 0) { if (ieee754_csr.rm == IEEE754_RD) return ieee754sp_zero(1); /* round negative inf. => sign = -1 */ else return ieee754sp_zero(0); /* other round modes => sign = 1 */ - - /* normalize to rounding precision + } + /* normalize to rounding precision */ while ((xm >> (SP_MBITS + 3)) == 0) { xm <<= 1; --- linux-2.5.73/arch/mips/math-emu/sp_tint.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/sp_tint.c 2003-06-27 15:56:23.000000000 -0700 @@ -35,38 +35,78 @@ int ieee754sp_tint(ieee754sp x) CLEARCX; EXPLODEXSP; + FLUSHXSP; switch (xc) { case IEEE754_CLASS_SNAN: case IEEE754_CLASS_QNAN: - SETCX(IEEE754_INVALID_OPERATION); - return ieee754si_xcpt(ieee754si_indef(), "fixsp", x); case IEEE754_CLASS_INF: - SETCX(IEEE754_OVERFLOW); - return ieee754si_xcpt(ieee754si_indef(), "fixsp", x); + SETCX(IEEE754_INVALID_OPERATION); + return ieee754si_xcpt(ieee754si_indef(), "sp_tint", x); case IEEE754_CLASS_ZERO: return 0; - case IEEE754_CLASS_DNORM: /* much to small */ - SETCX(IEEE754_UNDERFLOW); - return ieee754si_xcpt(0, "fixsp", x); + case IEEE754_CLASS_DNORM: case IEEE754_CLASS_NORM: break; } if (xe >= 31) { - SETCX(IEEE754_OVERFLOW); - return ieee754si_xcpt(ieee754si_indef(), "fix", x); - } - if (xe < 0) { - SETCX(IEEE754_UNDERFLOW); - return ieee754si_xcpt(0, "fix", x); + /* look for valid corner case */ + if (xe == 31 && xs && xm == SP_HIDDEN_BIT) + return -0x80000000; + /* Set invalid. We will only use overflow for floating + point overflow */ + SETCX(IEEE754_INVALID_OPERATION); + return ieee754si_xcpt(ieee754si_indef(), "sp_tint", x); } /* oh gawd */ if (xe > SP_MBITS) { xm <<= xe - SP_MBITS; - } else if (xe < SP_MBITS) { - /* XXX no rounding - */ - xm >>= SP_MBITS - xe; + } else { + u32 residue; + int round; + int sticky; + int odd; + + if (xe < -1) { + residue = xm; + round = 0; + sticky = residue != 0; + xm = 0; + } + else { + /* Shifting a u32 32 times does not work, + * so we do it in two steps. Be aware that xe + * may be -1 */ + residue = xm << (xe + 1); + residue <<= 31 - SP_MBITS; + round = (residue >> 31) != 0; + sticky = (residue << 1) != 0; + xm >>= SP_MBITS - xe; + } + odd = (xm & 0x1) != 0x0; + switch (ieee754_csr.rm) { + case IEEE754_RN: + if (round && (sticky || odd)) + xm++; + break; + case IEEE754_RZ: + break; + case IEEE754_RU: /* toward +Infinity */ + if ((round || sticky) && !xs) + xm++; + break; + case IEEE754_RD: /* toward -Infinity */ + if ((round || sticky) && xs) + xm++; + break; + } + if ((xm >> 31) != 0) { + /* This can happen after rounding */ + SETCX(IEEE754_INVALID_OPERATION); + return ieee754si_xcpt(ieee754si_indef(), "sp_tint", x); + } + if (round || sticky) + SETCX(IEEE754_INEXACT); } if (xs) return -xm; --- linux-2.5.73/arch/mips/math-emu/sp_tlong.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/math-emu/sp_tlong.c 2003-06-27 15:56:23.000000000 -0700 @@ -27,45 +27,81 @@ #include "ieee754sp.h" -long long ieee754sp_tlong(ieee754sp x) +s64 ieee754sp_tlong(ieee754sp x) { COMPXDP; /* <-- need 64-bit mantissa tmp */ CLEARCX; EXPLODEXSP; + FLUSHXSP; switch (xc) { case IEEE754_CLASS_SNAN: case IEEE754_CLASS_QNAN: - SETCX(IEEE754_INVALID_OPERATION); - return ieee754di_xcpt(ieee754di_indef(), "sp_tlong", x); case IEEE754_CLASS_INF: - SETCX(IEEE754_OVERFLOW); + SETCX(IEEE754_INVALID_OPERATION); return ieee754di_xcpt(ieee754di_indef(), "sp_tlong", x); case IEEE754_CLASS_ZERO: return 0; - case IEEE754_CLASS_DNORM: /* much to small */ - SETCX(IEEE754_UNDERFLOW); - return ieee754di_xcpt(0, "sp_tlong", x); + case IEEE754_CLASS_DNORM: case IEEE754_CLASS_NORM: break; } if (xe >= 63) { - SETCX(IEEE754_OVERFLOW); + /* look for valid corner case */ + if (xe == 63 && xs && xm == SP_HIDDEN_BIT) + return -0x8000000000000000LL; + /* Set invalid. We will only use overflow for floating + point overflow */ + SETCX(IEEE754_INVALID_OPERATION); return ieee754di_xcpt(ieee754di_indef(), "sp_tlong", x); } - if (xe < 0) { - SETCX(IEEE754_UNDERFLOW); - return ieee754di_xcpt(0, "sp_tlong", x); - } /* oh gawd */ if (xe > SP_MBITS) { xm <<= xe - SP_MBITS; } else if (xe < SP_MBITS) { - /* XXX no rounding - */ - xm >>= SP_MBITS - xe; + u32 residue; + int round; + int sticky; + int odd; + + if (xe < -1) { + residue = xm; + round = 0; + sticky = residue != 0; + xm = 0; + } + else { + residue = xm << (32 - SP_MBITS + xe); + round = (residue >> 31) != 0; + sticky = (residue << 1) != 0; + xm >>= SP_MBITS - xe; + } + odd = (xm & 0x1) != 0x0; + switch (ieee754_csr.rm) { + case IEEE754_RN: + if (round && (sticky || odd)) + xm++; + break; + case IEEE754_RZ: + break; + case IEEE754_RU: /* toward +Infinity */ + if ((round || sticky) && !xs) + xm++; + break; + case IEEE754_RD: /* toward -Infinity */ + if ((round || sticky) && xs) + xm++; + break; + } + if ((xm >> 63) != 0) { + /* This can happen after rounding */ + SETCX(IEEE754_INVALID_OPERATION); + return ieee754di_xcpt(ieee754di_indef(), "sp_tlong", x); + } + if (round || sticky) + SETCX(IEEE754_INEXACT); } if (xs) return -xm; @@ -74,14 +110,14 @@ long long ieee754sp_tlong(ieee754sp x) } -unsigned long long ieee754sp_tulong(ieee754sp x) +u64 ieee754sp_tulong(ieee754sp x) { ieee754sp hb = ieee754sp_1e63(); /* what if x < 0 ?? */ if (ieee754sp_lt(x, hb)) - return (unsigned long long) ieee754sp_tlong(x); + return (u64) ieee754sp_tlong(x); - return (unsigned long long) ieee754sp_tlong(ieee754sp_sub(x, hb)) | + return (u64) ieee754sp_tlong(ieee754sp_sub(x, hb)) | (1ULL << 63); } --- linux-2.5.73/arch/mips/mips-boards/atlas/atlas_int.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/atlas/atlas_int.c 2003-06-27 15:56:23.000000000 -0700 @@ -19,17 +19,17 @@ * * ######################################################################## * - * Routines for generic manipulation of the interrupts found on the MIPS + * Routines for generic manipulation of the interrupts found on the MIPS * Atlas board. * */ #include +#include #include #include #include #include #include -#include #include #include @@ -41,10 +41,6 @@ struct atlas_ictrl_regs *atlas_hw0_icreg = (struct atlas_ictrl_regs *)ATLAS_ICTRL_REGS_BASE; extern asmlinkage void mipsIRQ(void); -extern void do_IRQ(int irq, struct pt_regs *regs); - -unsigned long spurious_count = 0; -irq_desc_t irq_desc[NR_IRQS]; #if 0 #define DEBUG_INT(x...) printk(x) @@ -52,11 +48,6 @@ irq_desc_t irq_desc[NR_IRQS]; #define DEBUG_INT(x...) #endif -void inline disable_irq_nosync(unsigned int irq_nr) -{ - disable_atlas_irq(irq_nr); -} - void disable_atlas_irq(unsigned int irq_nr) { atlas_hw0_icregs->intrsten = (1 << irq_nr); @@ -94,80 +85,6 @@ static struct hw_interrupt_type atlas_ir NULL }; -int show_interrupts(struct seq_file *p, void *v) -{ - int i; - int num = 0; - struct irqaction *action; - unsigned long flags; - - for (i = 0; i < ATLASINT_END; i++, num++) { - spin_lock_irqsave(&irq_desc[i].lock, flags); - action = irq_desc[i].action; - if (!action) - goto skip; - seq_printf(p, "%2d: %8d %c %s", - num, kstat_cpu(0).irqs[num], - (action->flags & SA_INTERRUPT) ? '+' : ' ', - action->name); - for (action=action->next; action; action = action->next) { - seq_printf(p, ",%s %s", - (action->flags & SA_INTERRUPT) ? " +" : "", - action->name); - } - seq_printf(p, " [hw0]\n"); -skip: - spin_unlock_irqrestore(&irq_desc[i].lock, flags); - } - return 0; -} - -int request_irq(unsigned int irq, - void (*handler)(int, void *, struct pt_regs *), - unsigned long irqflags, - const char * devname, - void *dev_id) -{ - struct irqaction *action; - - DEBUG_INT("request_irq: irq=%d, devname = %s\n", irq, devname); - - if (irq >= ATLASINT_END) - return -EINVAL; - if (!handler) - return -EINVAL; - - action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL); - if(!action) - return -ENOMEM; - - action->handler = handler; - action->flags = irqflags; - action->mask = 0; - action->name = devname; - action->dev_id = dev_id; - action->next = 0; - irq_desc[irq].action = action; - enable_atlas_irq(irq); - - return 0; -} - -void free_irq(unsigned int irq, void *dev_id) -{ - struct irqaction *action; - - if (irq >= ATLASINT_END) { - printk("Trying to free IRQ%d\n",irq); - return; - } - - action = irq_desc[irq].action; - irq_desc[irq].action = NULL; - disable_atlas_irq(irq); - kfree(action); -} - static inline int ls1bit32(unsigned int x) { int b = 31, s; @@ -183,48 +100,23 @@ static inline int ls1bit32(unsigned int void atlas_hw0_irqdispatch(struct pt_regs *regs) { - struct irqaction *action; unsigned long int_status; - int irq, cpu = smp_processor_id(); + int irq; - int_status = atlas_hw0_icregs->intstatus; + int_status = atlas_hw0_icregs->intstatus; /* if int_status == 0, then the interrupt has already been cleared */ - if (int_status == 0) + if (unlikely(int_status == 0)) return; irq = ls1bit32(int_status); - action = irq_desc[irq].action; DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq); - /* if action == NULL, then we don't have a handler for the irq */ - if ( action == NULL ) { - printk("No handler for hw0 irq: %i\n", irq); - spurious_count++; - return; - } - - irq_enter(cpu, irq); - kstat_cpu(0).irqs[irq]++; - action->handler(irq, action->dev_id, regs); - irq_exit(cpu, irq); - - return; -} - -unsigned long probe_irq_on (void) -{ - return 0; -} - - -int probe_irq_off (unsigned long irqs) -{ - return 0; + do_IRQ(irq, regs); } -#ifdef CONFIG_REMOTE_DEBUG +#ifdef CONFIG_KGDB extern void breakpoint(void); extern int remote_debug; #endif @@ -233,11 +125,11 @@ void __init init_IRQ(void) { int i; - /* - * Mask out all interrupt by writing "1" to all bit position in - * the interrupt reset reg. + /* + * Mask out all interrupt by writing "1" to all bit position in + * the interrupt reset reg. */ - atlas_hw0_icregs->intrsten = 0xffffffff; + atlas_hw0_icregs->intrsten = 0xffffffff; /* Now safe to set the exception vector. */ set_except_vector(0, mipsIRQ); @@ -250,7 +142,7 @@ void __init init_IRQ(void) spin_lock_init(&irq_desc[i].lock); } -#ifdef CONFIG_REMOTE_DEBUG +#ifdef CONFIG_KGDB if (remote_debug) { set_debug_traps(); breakpoint(); --- linux-2.5.73/arch/mips/mips-boards/atlas/atlas_setup.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/atlas/atlas_setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -19,6 +19,7 @@ */ #include #include +#include #include #include #include @@ -28,15 +29,17 @@ #include #include #include -#include #include +#include +#include +#include #if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE) extern void console_setup(char *, int *); char serial_console[20]; #endif -#ifdef CONFIG_REMOTE_DEBUG +#ifdef CONFIG_KGDB extern void rs_kgdb_hook(int); extern void saa9730_kgdb_hook(void); extern void breakpoint(void); @@ -47,9 +50,18 @@ extern struct rtc_ops atlas_rtc_ops; extern void mips_reboot_setup(void); +const char *get_system_type(void) +{ + return "MIPS Atlas"; +} + +extern void mips_time_init(void); +extern void mips_timer_setup(struct irqaction *irq); +extern unsigned long mips_rtc_get_time(void); + void __init atlas_setup(void) { -#ifdef CONFIG_REMOTE_DEBUG +#ifdef CONFIG_KGDB int rs_putDebugChar(char); char rs_getDebugChar(void); int saa9730_putDebugChar(char); @@ -73,9 +85,9 @@ void __init atlas_setup(void) prom_printf("Config serial console: %s\n", serial_console); console_setup(serial_console, NULL); } -#endif +#endif -#ifdef CONFIG_REMOTE_DEBUG +#ifdef CONFIG_KGDB argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { int line; @@ -107,9 +119,12 @@ void __init atlas_setup(void) argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "nofpu")) != NULL) - mips_cpu.options &= ~MIPS_CPU_FPU; + cpu_data[0].options &= ~MIPS_CPU_FPU; rtc_ops = &atlas_rtc_ops; + board_time_init = mips_time_init; + board_timer_setup = mips_timer_setup; + rtc_get_time = mips_rtc_get_time; mips_reboot_setup(); } --- linux-2.5.73/arch/mips/mips-boards/atlas/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/atlas/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -7,12 +7,12 @@ # This program is free software; you can distribute it and/or modify it # under the terms of the GNU General Public License (Version 2) as # published by the Free Software Foundation. -# +# # This program is distributed in the hope it will be useful, but WITHOUT # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License # for more details. -# +# # You should have received a copy of the GNU General Public License along # with this program; if not, write to the Free Software Foundation, Inc., # 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. --- linux-2.5.73/arch/mips/mips-boards/generic/cmdline.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/generic/cmdline.c 2003-06-27 15:56:23.000000000 -0700 @@ -17,16 +17,21 @@ * * Kernel command line creation using the prom monitor (YAMON) argc/argv. */ -#include #include #include #include extern int prom_argc; -extern char **prom_argv; +extern int *_prom_argv; -char arcs_cmdline[COMMAND_LINE_SIZE]; +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension. + */ +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)])) + +char arcs_cmdline[CL_SIZE]; char * __init prom_getcmdline(void) { @@ -43,8 +48,8 @@ void __init prom_init_cmdline(void) cp = &(arcs_cmdline[0]); while(actr < prom_argc) { - strcpy(cp, prom_argv[actr]); - cp += strlen(prom_argv[actr]); + strcpy(cp, prom_argv(actr)); + cp += strlen(prom_argv(actr)); *cp++ = ' '; actr++; } --- linux-2.5.73/arch/mips/mips-boards/generic/display.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/generic/display.c 2003-06-27 15:56:23.000000000 -0700 @@ -18,7 +18,7 @@ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * * ######################################################################## - * + * * Display routines for display messages in MIPS boards ascii display. * */ @@ -39,9 +39,11 @@ void mips_display_message(const char *st } } +#ifndef CONFIG_MIPS_SEAD void mips_display_word(unsigned int num) { volatile unsigned int *display = (void *)ASCII_DISPLAY_WORD_BASE; - + *display = num; } +#endif --- linux-2.5.73/arch/mips/mips-boards/generic/gdb_hook.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/generic/gdb_hook.c 2003-06-27 15:56:23.000000000 -0700 @@ -2,8 +2,6 @@ * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. * - * ######################################################################## - * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. @@ -17,12 +15,9 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * ######################################################################## - * * This is the interface to the remote debugger stub. - * */ - +#include #include #include @@ -67,28 +62,28 @@ void rs_kgdb_hook(int tty_no) { serial_in(&kdb_port_info, UART_MSR); /* - * Now, initialize the UART + * Now, initialize the UART */ serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */ if (kdb_port_info.flags & ASYNC_FOURPORT) { kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS; t = UART_MCR_DTR | UART_MCR_OUT1; } else { - kdb_port_info.MCR + kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2; t = UART_MCR_DTR | UART_MCR_RTS; } kdb_port_info.MCR = t; /* no interrupts, please */ serial_out(&kdb_port_info, UART_MCR, kdb_port_info.MCR); - + /* * and set the speed of the serial port * (currently hardwired to 9600 8N1 */ /* baud rate is fixed to 9600 (is this sufficient?)*/ - t = kdb_port_info.state->baud_base / 9600; + t = kdb_port_info.state->baud_base / 9600; /* set DLAB */ serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB); serial_out(&kdb_port_info, UART_DLL, t & 0xff);/* LS of divisor */ @@ -102,7 +97,7 @@ int putDebugChar(char c) return generic_putDebugChar(c); } -char getDebugChar(void) +char getDebugChar(void) { return generic_getDebugChar(); } @@ -156,7 +151,7 @@ static t_uart_saa9730_regmap *kgdb_uart static int saa9730_kgdb_active = 0; -void saa9730_kgdb_hook(void) +void saa9730_kgdb_hook(void) { volatile unsigned char t; --- linux-2.5.73/arch/mips/mips-boards/generic/init.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/generic/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -27,6 +27,8 @@ #include #include #include +#include +#include /* Environment variable */ typedef struct @@ -36,27 +38,37 @@ typedef struct } t_env_var; int prom_argc; -char **prom_argv, **prom_envp; +int *_prom_argv, *_prom_envp; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension, if running in 64-bit mode. + */ +#define prom_envp(index) ((char *)(((int *)(int)_prom_envp)[(index)])) int init_debug = 0; +unsigned int mips_revision_corid; + char *prom_getenv(char *envname) { - /* + /* * Return a pointer to the given environment variable. + * In 64-bit mode: we're using 64-bit pointers, but all pointers + * in the PROM structures are only 32-bit, so we need some + * workarounds, if we are running in 64-bit mode. */ - - t_env_var *env = (t_env_var *)prom_envp; - int i; + int i, index=0; i = strlen(envname); - while(env->name) { - if(strncmp(envname, env->name, i) == 0) { - return(env->val); + while(prom_envp(index)) { + if(strncmp(envname, prom_envp(index), i) == 0) { + return(prom_envp(index+1)); } - env++; + index += 2; } + return(NULL); } @@ -83,7 +95,7 @@ static inline void str2eaddr(unsigned ch ea[i] = num; } } - + int get_ethernet_addr(char *ethernet_addr) { char *ethaddr_str; @@ -109,28 +121,84 @@ int get_ethernet_addr(char *ethernet_add int __init prom_init(int argc, char **argv, char **envp) { prom_argc = argc; - prom_argv = argv; - prom_envp = envp; + _prom_argv = (int *)argv; + _prom_envp = (int *)envp; mips_display_message("LINUX"); - /* - * Setup the North bridge to do Master byte-lane swapping when - * running in bigendian. - */ +#ifdef CONFIG_MIPS_SEAD + set_io_port_base(KSEG1); +#else + mips_revision_corid = MIPS_REVISION_CORID; + switch(mips_revision_corid) { + case MIPS_REVISION_CORID_QED_RM5261: + case MIPS_REVISION_CORID_CORE_LV: + case MIPS_REVISION_CORID_CORE_FPGA: + /* + * Setup the North bridge to do Master byte-lane swapping + * when running in bigendian. + */ +#if defined(__MIPSEL__) + GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | + GT_PCI0_CMD_SBYTESWAP_BIT); +#else + GT_WRITE(GT_PCI0_CMD_OFS, 0); +#endif + +#if defined(CONFIG_MIPS_MALTA) + set_io_port_base(MALTA_GT_PORT_BASE); +#else + set_io_port_base(KSEG1); +#endif + + break; + case MIPS_REVISION_CORID_BONITO64: + case MIPS_REVISION_CORID_CORE_20K: + /* + * Disable Bonito IOBC. + */ + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + + /* + * Setup the North bridge to do Master byte-lane swapping + * when running in bigendian. + */ #if defined(__MIPSEL__) - GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | - GT_PCI0_CMD_SBYTESWAP_BIT); + BONITO_BONGENCFG = BONITO_BONGENCFG & + ~(BONITO_BONGENCFG_MSTRBYTESWAP | + BONITO_BONGENCFG_BYTESWAP); #else - GT_WRITE(GT_PCI0_CMD_OFS, 0); + BONITO_BONGENCFG = BONITO_BONGENCFG | + BONITO_BONGENCFG_MSTRBYTESWAP | + BONITO_BONGENCFG_BYTESWAP; #endif #if defined(CONFIG_MIPS_MALTA) - mips_io_port_base = MALTA_PORT_BASE; + set_io_port_base(MALTA_BONITO_PORT_BASE); #else - mips_io_port_base = KSEG1; + set_io_port_base(KSEG1); +#endif + break; + + case MIPS_REVISION_CORID_CORE_MSC: + set_io_port_base(MALTA_MSC_PORT_BASE); +#if defined(__MIPSEL__) + MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); +#else + MSC_WRITE(MSC01_PCI_SWAP, + MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | + MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | + MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); +#endif + break; + default: + /* Unknown Core card */ + mips_display_message("CC Error"); + while(1); /* We die here... */ + } #endif - setup_prom_printf(0); prom_printf("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); --- linux-2.5.73/arch/mips/mips-boards/generic/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/generic/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -2,28 +2,26 @@ # Carsten Langgaard, carstenl@mips.com # Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. # -# ######################################################################## -# # This program is free software; you can distribute it and/or modify it # under the terms of the GNU General Public License (Version 2) as # published by the Free Software Foundation. -# +# # This program is distributed in the hope it will be useful, but WITHOUT # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License # for more details. -# +# # You should have received a copy of the GNU General Public License along # with this program; if not, write to the Free Software Foundation, Inc., # 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. # -# ####################################################################### -# # Makefile for the MIPS boards generic routines under Linux. # -EXTRA_AFLAGS := $(CFLAGS) +obj-y := mipsIRQ.o reset.o display.o init.o memory.o \ + printf.o cmdline.o +obj-$(CONFIG_MIPS_ATLAS) += time.o +obj-$(CONFIG_MIPS_MALTA) += time.o +obj-$(CONFIG_KGDB) += gdb_hook.o -obj-y := mipsIRQ.o pci.o reset.o display.o init.o \ - memory.o printf.o cmdline.o time.o -obj-$(CONFIG_REMOTE_DEBUG) += gdb_hook.o +EXTRA_AFLAGS := $(CFLAGS) --- linux-2.5.73/arch/mips/mips-boards/generic/memory.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/generic/memory.c 2003-06-27 15:56:23.000000000 -0700 @@ -2,8 +2,6 @@ * Carsten Langgaard, carstenl@mips.com * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. * - * ######################################################################## - * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. @@ -17,11 +15,8 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * ######################################################################## - * - * PROM library functions for acquiring/using memory descriptors given to + * PROM library functions for acquiring/using memory descriptors given to * us from the YAMON. - * */ #include #include @@ -83,11 +78,11 @@ struct prom_pmemblock * __init prom_getm mdesc[1].size = 0x000ef000; #if (CONFIG_MIPS_MALTA) - /* + /* * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the - * south bridge and PCI access always forwarded to the ISA Bus and + * south bridge and PCI access always forwarded to the ISA Bus and * BIOSCS# is always generated. - * This mean that this area can't be used as DMA memory for PCI + * This mean that this area can't be used as DMA memory for PCI * devices. */ mdesc[2].type = yamon_dontuse; @@ -148,7 +143,7 @@ void __init prom_meminit(void) size = p->size; add_memory_region(base, size, type); - p++; + p++; } } @@ -168,7 +163,7 @@ prom_free_prom_memory (void) + boot_mem_map.map[i].size) { ClearPageReserved(virt_to_page(__va(addr))); set_page_count(virt_to_page(__va(addr)), 1); - free_page(__va(addr)); + free_page((unsigned long)__va(addr)); addr += PAGE_SIZE; freed += PAGE_SIZE; } --- linux-2.5.73/arch/mips/mips-boards/generic/mipsIRQ.S 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/generic/mipsIRQ.S 2003-06-27 15:56:23.000000000 -0700 @@ -56,6 +56,10 @@ * 6 Hardware (ignored) * 7 R4k timer (what we use) * + * Note: On the SEAD board thing are a little bit different. + * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired + * wired to UART1. + * * We handle the IRQ according to _our_ priority which is: * * Highest ---- R4k Timer @@ -74,7 +78,9 @@ CLI .set at - mfc0 s0, CP0_CAUSE # get irq mask + mfc0 s0, CP0_CAUSE # get irq bits + mfc0 s1, CP0_STATUS # get irq mask + and s0, s1 /* First we check for r4k counter/timer IRQ. */ andi a0, s0, CAUSEF_IP7 @@ -90,16 +96,23 @@ nop 1: +#if defined(CONFIG_MIPS_SEAD) beq a0, zero, 1f - nop + andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt +#else + beq a0, zero, 1f # delay slot, check hw3 interrupt + andi a0, s0, CAUSEF_IP5 +#endif /* Wheee, combined hardware level zero interrupt. */ #if defined(CONFIG_MIPS_ATLAS) jal atlas_hw0_irqdispatch #elif defined(CONFIG_MIPS_MALTA) jal malta_hw0_irqdispatch +#elif defined(CONFIG_MIPS_SEAD) + jal sead_hw0_irqdispatch #else -#error "MIPS board not supported\n" +#error "MIPS board not supported\n" #endif move a0, sp # delay slot @@ -107,6 +120,24 @@ nop # delay slot 1: +#if defined(CONFIG_MIPS_SEAD) + beq a0, zero, 1f + andi a0, s0, CAUSEF_IP5 # delay slot, check hw3 interrupt + jal sead_hw1_irqdispatch + move a0, sp # delay slot + j ret_from_irq + nop # delay slot +1: +#endif +#if defined(CONFIG_MIPS_MALTA) + beq a0, zero, 1f # check hw3 (coreHI) interrupt + nop + jal corehi_irqdispatch + move a0, sp + j ret_from_irq + nop +1: +#endif /* * Here by mistake? This is possible, what can happen is that by the * time we take the exception the IRQ pin goes low, so just leave if --- linux-2.5.73/arch/mips/mips-boards/generic/pci.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,267 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * MIPS boards specific PCI support. - * - */ -#include - -#ifdef CONFIG_PCI - -#include -#include -#include -#include - -#include -#include -#ifdef CONFIG_MIPS_MALTA -#include -#endif - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -static int -mips_pcibios_config_access(unsigned char access_type, struct pci_bus *bus_dev, unsigned int dev_fn, unsigned char where, u32 *data) -{ - unsigned char bus = bus_dev->number; - u32 intr; - - if ((bus == 0) && (dev_fn >= PCI_DEVFN(31,0))) - return -1; /* Because of a bug in the galileo (for slot 31). */ - - /* Clear cause register bits */ - GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | - GT_INTRCAUSE_TARABORT0_BIT)); - - /* Setup address */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, - (bus << GT_PCI0_CFGADDR_BUSNUM_SHF) | - (dev_fn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | - ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | - GT_PCI0_CFGADDR_CONFIGEN_BIT); - - if (access_type == PCI_ACCESS_WRITE) { - if (bus == 0 && dev_fn == 0) { - /* - * Galileo is acting differently than other devices. - */ - GT_WRITE(GT_PCI0_CFGDATA_OFS, *data); - } else { - GT_PCI_WRITE(GT_PCI0_CFGDATA_OFS, *data); - } - } else { - if (bus == 0 && dev_fn == 0) { - /* - * Galileo is acting differently than other devices. - */ - GT_READ(GT_PCI0_CFGDATA_OFS, *data); - } else { - GT_PCI_READ(GT_PCI0_CFGDATA_OFS, *data); - } - } - - /* Check for master or target abort */ - GT_READ(GT_INTRCAUSE_OFS, intr); - - if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) - { - /* Error occurred */ - - /* Clear bits */ - GT_WRITE( GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | - GT_INTRCAUSE_TARABORT0_BIT) ); - - return -1; - } - - return 0; -} - - -/* - * We can't address 8 and 16 bit words directly. Instead we have to - * read/write a 32bit word and mask/modify the data we actually want. - */ -static int -mips_pcibios_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) -{ - u32 data = 0; - - if((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - if (mips_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return -1; - if(size == 1) - *val = (u8)(data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) - *val = (u16)(data >> ((where & 3) << 3)) & 0xffff; - else if (size == 4) - *val = data; - - return PCIBIOS_SUCCESSFUL; -} - - -static int -mips_pcibios_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) -{ - u32 data = 0; - - if((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if (size == 4) { - if(where & 3) - return PCIBIOS_BAD_REGISTER_NUMBER; - if(mips_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, &val)) - return -1; - return PCIBIOS_SUCCESSFUL; - } - if (mips_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return -1; - if(size == 1) { - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - } else if (size == 2) { - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - } - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops mips_pci_ops = { - .read = mips_pcibios_read, - .write = mips_pcibios_write, -}; - -void __init pcibios_init(void) -{ -#ifdef CONFIG_MIPS_MALTA - struct pci_dev *pdev = NULL; - unsigned char reg_val; -#endif - - printk("PCI: Probing PCI hardware on host bus 0.\n"); - pci_scan_bus(0, &mips_pci_ops, NULL); - - /* - * Due to a bug in the Galileo system controller, we need to setup - * the PCI BAR for the Galileo internal registers. - * This should be done in the bios/bootprom and will be fixed in - * a later revision of YAMON (the MIPS boards boot prom). - */ - GT_WRITE(GT_PCI0_CFGADDR_OFS, - (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ - (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 device */ - (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0 */ - ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4 */ - GT_PCI0_CFGADDR_CONFIGEN_BIT ); - - /* Perform the write */ - GT_WRITE( GT_PCI0_CFGDATA_OFS, PHYSADDR(MIPS_GT_BASE)); - -#ifdef CONFIG_MIPS_MALTA - while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) { - if ((pdev->vendor == PCI_VENDOR_ID_INTEL) - && (pdev->device == PCI_DEVICE_ID_INTEL_82371AB) - && (PCI_SLOT(pdev->devfn) == 0x0a)) { - /* - * IDE Decode enable. - */ - pci_read_config_byte(pdev, 0x41, ®_val); - pci_write_config_byte(pdev, 0x41, reg_val | 0x80); - pci_read_config_byte(pdev, 0x43, ®_val); - pci_write_config_byte(pdev, 0x43, reg_val | 0x80); - } - - if ((pdev->vendor == PCI_VENDOR_ID_INTEL) - && (pdev->device == PCI_DEVICE_ID_INTEL_82371AB_0) - && (PCI_SLOT(pdev->devfn) == 0x0a)) { - /* - * Set top of main memory accessible by ISA or DMA - * devices to 16 Mb. - */ - pci_read_config_byte(pdev, 0x69, ®_val); - pci_write_config_byte(pdev, 0x69, reg_val | 0xf0); - } - } - - /* - * Activate Floppy Controller in the SMSC FDC37M817 Super I/O - * Controller. - * This should be done in the bios/bootprom and will be fixed in - * a later revision of YAMON (the MIPS boards boot prom). - */ - /* Entering config state. */ - SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG); - - /* Activate floppy controller. */ - SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG); - SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG); - SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG); - SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG); - - /* Exit config state. */ - SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG); -#endif -} - -int __init -pcibios_enable_device(struct pci_dev *dev) -{ - /* Not needed, since we enable all devices at startup. */ - return 0; -} - -void __init -pcibios_align_resource(void *data, struct resource *res, - unsigned long size, unsigned long align) -{ -} - -char * __init -pcibios_setup(char *str) -{ - /* Nothing to do for now. */ - - return str; -} - -struct pci_fixup pcibios_fixups[] = { - { 0 } -}; - -#warning pcibios_update_resource() is now a generic implementation - please check - -/* - * Called after each bus is probed, but before its children - * are examined. - */ -void __init pcibios_fixup_bus(struct pci_bus *b) -{ - pci_read_bridge_bases(b); -} - -unsigned __init int pcibios_assign_all_busses(void) -{ - return 1; -} - -#endif /* CONFIG_PCI */ --- linux-2.5.73/arch/mips/mips-boards/generic/printf.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/generic/printf.c 2003-06-27 15:56:23.000000000 -0700 @@ -2,8 +2,6 @@ * Carsten Langgaard, carstenl@mips.com * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. * - * ######################################################################## - * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. @@ -17,101 +15,84 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * ######################################################################## - * * Putting things on the screen/serial line using YAMONs facilities. - * */ #include #include #include -#include #include -#include +#include #include -#include +#ifdef CONFIG_MIPS_ATLAS -#ifdef CONFIG_MIPS_ATLAS -/* - * Atlas registers are memory mapped on 64-bit aligned boundaries and +#include + +/* + * Atlas registers are memory mapped on 64-bit aligned boundaries and * only word access are allowed. * When reading the UART 8 bit registers only the LSB are valid. */ -unsigned int atlas_serial_in(struct async_struct *info, int offset) +static inline unsigned int serial_in(int offset) { - return (*(volatile unsigned int *)(info->port + mips_io_port_base + offset*8) & 0xff); + return (*(volatile unsigned int *)(mips_io_port_base + ATLAS_UART_REGS_BASE + offset*8) & 0xff); } -void atlas_serial_out(struct async_struct *info, int offset, int value) +static inline void serial_out(int offset, int value) { - *(volatile unsigned int *)(info->port + mips_io_port_base + offset*8) = value; + *(volatile unsigned int *)(mips_io_port_base + ATLAS_UART_REGS_BASE + offset*8) = value; } -#define serial_in atlas_serial_in -#define serial_out atlas_serial_out +#elif defined(CONFIG_MIPS_SEAD) -#else +#include -static unsigned int serial_in(struct async_struct *info, int offset) +/* + * SEAD registers are just like Atlas registers. + */ +static inline unsigned int serial_in(int offset) { - return inb(info->port + offset); + return (*(volatile unsigned int *)(mips_io_port_base + SEAD_UART0_REGS_BASE + offset*8) & 0xff); } -static void serial_out(struct async_struct *info, int offset, - int value) +static inline void serial_out(int offset, int value) { - outb(value, info->port + offset); + *(volatile unsigned int *)(mips_io_port_base + SEAD_UART0_REGS_BASE + offset*8) = value; } -#endif -static struct serial_state rs_table[] = { - SERIAL_PORT_DFNS /* Defined in serial.h */ -}; - -/* - * Hooks to fake "prom" console I/O before devices - * are fully initialized. - */ -static struct async_struct prom_port_info = {0}; - -void __init setup_prom_printf(int tty_no) { - struct serial_state *ser = &rs_table[tty_no]; +#else - prom_port_info.state = ser; - prom_port_info.magic = SERIAL_MAGIC; - prom_port_info.port = ser->port; - prom_port_info.flags = ser->flags; +static inline unsigned int serial_in(int offset) +{ + return inb(0x3f8 + offset); +} - /* No setup of UART - assume YAMON left in sane state */ +static inline void serial_out(int offset, int value) +{ + outb(value, 0x3f8 + offset); } +#endif int putPromChar(char c) { - if (!prom_port_info.state) { /* need to init device first */ - return 0; - } - - while ((serial_in(&prom_port_info, UART_LSR) & UART_LSR_THRE) == 0) + while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) ; - serial_out(&prom_port_info, UART_TX, c); + serial_out(UART_TX, c); return 1; } char getPromChar(void) { - if (!prom_port_info.state) { /* need to init device first */ - return 0; - } - - while (!(serial_in(&prom_port_info, UART_LSR) & 1)) + while (!(serial_in(UART_LSR) & 1)) ; - return(serial_in(&prom_port_info, UART_RX)); + return serial_in(UART_RX); } +static spinlock_t con_lock = SPIN_LOCK_UNLOCKED; + static char buf[1024]; void __init prom_printf(char *fmt, ...) @@ -123,8 +104,7 @@ void __init prom_printf(char *fmt, ...) int putPromChar(char); - /* Low level, brute force, not SMP safe... */ - save_and_cli(flags); + spin_lock_irqsave(con_lock, flags); va_start(args, fmt); l = vsprintf(buf, fmt, args); /* hopefully i < sizeof(buf) */ va_end(args); @@ -133,8 +113,9 @@ void __init prom_printf(char *fmt, ...) for (p = buf; p < buf_end; p++) { /* Crude cr/nl handling is better than none */ - if(*p == '\n')putPromChar('\r'); + if (*p == '\n') + putPromChar('\r'); putPromChar(*p); } - restore_flags(flags); + spin_unlock_irqrestore(con_lock, flags); } --- linux-2.5.73/arch/mips/mips-boards/generic/time.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/generic/time.c 2003-06-27 15:56:23.000000000 -0700 @@ -23,29 +23,29 @@ * */ +#include #include #include #include #include #include +#include +#include +#include +#include #include #include +#include #include - -#include -#include -#include +#include +#include #include #include -extern volatile unsigned long wall_jiffies; -static long last_rtc_update = 0; -unsigned long missed_heart_beats = 0; - -static unsigned long r4k_offset; /* Amount to increment compare reg each time */ -static unsigned long r4k_cur; /* What counter should be at next timer irq */ +static unsigned int r4k_offset; /* Amount to increment compare reg each time */ +static unsigned int r4k_cur; /* What counter should be at next timer irq */ #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) @@ -56,142 +56,37 @@ static char display_string[] = " static char display_string[] = " LINUX ON MALTA "; #endif static unsigned int display_count = 0; -#define MAX_DISPLAY_COUNT (sizeof(display_string) - 8) +#define MAX_DISPLAY_COUNT (sizeof(display_string) - 8) + +#define MIPS_CPU_TIMER_IRQ 7 static unsigned int timer_tick_count=0; -static inline void ack_r4ktimer(unsigned long newval) +static inline void ack_r4ktimer(unsigned int newval) { - write_32bit_cp0_register(CP0_COMPARE, newval); + write_c0_compare(newval); } - -/* - * In order to set the CMOS clock precisely, set_rtc_mmss has to be - * called 500 ms after the second nowtime has started, because when - * nowtime is written into the registers of the CMOS clock, it will - * jump to the next second precisely 500 ms later. Check the Motorola - * MC146818A or Dallas DS12887 data sheet for details. - * - * BUG: This routine does not handle hour overflow properly; it just - * sets the minutes. Usually you won't notice until after reboot! - */ -static int set_rtc_mmss(unsigned long nowtime) -{ - int retval = 0; - int real_seconds, real_minutes, cmos_minutes; - unsigned char save_control, save_freq_select; - - save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */ - CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL); - - save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */ - CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); - - cmos_minutes = CMOS_READ(RTC_MINUTES); - - /* - * since we're only adjusting minutes and seconds, - * don't interfere with hour overflow. This avoids - * messing with unknown time zones but requires your - * RTC not to be off by more than 15 minutes - */ - real_seconds = nowtime % 60; - real_minutes = nowtime / 60; - if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) - real_minutes += 30; /* correct for half hour time zone */ - real_minutes %= 60; - - if (abs(real_minutes - cmos_minutes) < 30) { - CMOS_WRITE(real_seconds,RTC_SECONDS); - CMOS_WRITE(real_minutes,RTC_MINUTES); - } else { - printk(KERN_WARNING - "set_rtc_mmss: can't update from %d to %d\n", - cmos_minutes, real_minutes); - retval = -1; - } - - /* The following flags have to be released exactly in this order, - * otherwise the DS12887 (popular MC146818A clone with integrated - * battery and quartz) will not reset the oscillator and will not - * update precisely 500 ms later. You won't find this mentioned in - * the Dallas Semiconductor data sheets, but who believes data - * sheets anyway ... -- Markus Kuhn - */ - CMOS_WRITE(save_control, RTC_CONTROL); - CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); - - return retval; -} - -/* - * There are a lot of conceptually broken versions of the MIPS timer interrupt - * handler floating around. This one is rather different, but the algorithm - * is provably more robust. - */ void mips_timer_interrupt(struct pt_regs *regs) { - unsigned long flags; - int irq = 7; - unsigned long seq; - - if (r4k_offset == 0) - goto null; - - do { - kstat_cpu(0).irqs[irq]++; - do_timer(regs); - - /* Historical comment/code: - * RTC time of day s updated approx. every 11 - * minutes. Because of how the numbers work out - * we need to make absolutely sure we do this update - * within 500ms before the * next second starts, - * thus the following code. - */ - - do { - seq = read_seqbegin_irqsave(&xtime_lock, flags); - - if ((time_status & STA_UNSYNC) == 0 - && xtime.tv_sec > last_rtc_update + 660 - && xtime.tv_usec >= 500000 - (tick >> 1) - && xtime.tv_usec <= 500000 + (tick >> 1)) - if (set_rtc_mmss(xtime.tv_sec) == 0) - last_rtc_update = xtime.tv_sec; - else - /* do it again in 60 s */ - last_rtc_update = xtime.tv_sec - 600; - } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); - - if ((timer_tick_count++ % HZ) == 0) { - mips_display_message(&display_string[display_count++]); - if (display_count == MAX_DISPLAY_COUNT) + if ((timer_tick_count++ % HZ) == 0) { + mips_display_message(&display_string[display_count++]); + if (display_count == MAX_DISPLAY_COUNT) display_count = 0; - } - r4k_cur += r4k_offset; - ack_r4ktimer(r4k_cur); - - } while (((unsigned long)read_32bit_cp0_register(CP0_COUNT) - - r4k_cur) < 0x7fffffff); - - return; + } -null: - ack_r4ktimer(0); + ll_timer_interrupt(MIPS_CPU_TIMER_IRQ, regs); } -/* +/* * Figure out the r4k offset, the amount to increment the compare - * register for each time tick. + * register for each time tick. * Use the RTC to calculate offset. */ -static unsigned long __init cal_r4koff(void) +static unsigned int __init cal_r4koff(void) { - unsigned long count; unsigned int flags; local_irq_save(flags); @@ -201,21 +96,21 @@ static unsigned long __init cal_r4koff(v while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); /* Start r4k counter. */ - write_32bit_cp0_register(CP0_COUNT, 0); + write_c0_count(0); /* Read counter exactly on falling edge of update flag */ while (CMOS_READ(RTC_REG_A) & RTC_UIP); while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); - count = read_32bit_cp0_register(CP0_COUNT); + mips_counter_frequency = read_c0_count(); /* restore interrupts */ local_irq_restore(flags); - return (count / HZ); + return (mips_counter_frequency / HZ); } -static unsigned long __init get_mips_time(void) +unsigned long __init mips_rtc_get_time(void) { unsigned int year, mon, day, hour, min, sec; unsigned char save_control; @@ -235,7 +130,7 @@ static unsigned long __init get_mips_tim if ((hour & 0xf) == 0xc) hour &= 0x80; if (hour & 0x80) - hour = (hour & 0xf) + 12; + hour = (hour & 0xf) + 12; } day = CMOS_READ(RTC_DAY_OF_MONTH); mon = CMOS_READ(RTC_MONTH); @@ -250,170 +145,41 @@ static unsigned long __init get_mips_tim return mktime(year, mon, day, hour, min, sec); } -void __init time_init(void) +void __init mips_time_init(void) { unsigned int est_freq, flags; - /* Set Data mode - binary. */ + local_irq_save(flags); + + /* Set Data mode - binary. */ CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); printk("calculating r4koff... "); r4k_offset = cal_r4koff(); - printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); + printk("%08x(%d)\n", r4k_offset, r4k_offset); + + if ((read_c0_prid() & 0xffff00) == + (PRID_COMP_MIPS | PRID_IMP_20KC)) + est_freq = r4k_offset*HZ; + else + est_freq = 2*r4k_offset*HZ; - est_freq = 2*r4k_offset*HZ; est_freq += 5000; /* round */ est_freq -= est_freq%10000; - printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, (est_freq%1000000)*100/1000000); - r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset); - write_32bit_cp0_register(CP0_COMPARE, r4k_cur); - change_cp0_status(ST0_IM, ALLINTS); - - /* Read time from the RTC chipset. */ - write_seqlock_irqsave (&xtime_lock, flags); - xtime.tv_sec = get_mips_time(); - xtime.tv_usec = 0; - write_sequnlock_irqrestore(&xtime_lock, flags); -} - -/* This is for machines which generate the exact clock. */ -#define USECS_PER_JIFFY (1000000/HZ) -#define USECS_PER_JIFFY_FRAC ((1000000 << 32) / HZ & 0xffffffff) - -/* Cycle counter value at the previous timer interrupt.. */ - -static unsigned int timerhi = 0, timerlo = 0; - -/* - * FIXME: Does playing with the RP bit in c0_status interfere with this code? - */ -static unsigned long do_fast_gettimeoffset(void) -{ - u32 count; - unsigned long res, tmp; - - /* Last jiffy when do_fast_gettimeoffset() was called. */ - static unsigned long last_jiffies=0; - unsigned long quotient; - - /* - * Cached "1/(clocks per usec)*2^32" value. - * It has to be recalculated once each jiffy. - */ - static unsigned long cached_quotient=0; - - tmp = jiffies; - - quotient = cached_quotient; - - if (tmp && last_jiffies != tmp) { - last_jiffies = tmp; -#ifdef CONFIG_CPU_MIPS32 - if (last_jiffies != 0) { - unsigned long r0; - do_div64_32(r0, timerhi, timerlo, tmp); - do_div64_32(quotient, USECS_PER_JIFFY, - USECS_PER_JIFFY_FRAC, r0); - cached_quotient = quotient; - } -#else - __asm__(".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "lwu\t%0,%2\n\t" - "dsll32\t$1,%1,0\n\t" - "or\t$1,$1,%0\n\t" - "ddivu\t$0,$1,%3\n\t" - "mflo\t$1\n\t" - "dsll32\t%0,%4,0\n\t" - "nop\n\t" - "ddivu\t$0,%0,$1\n\t" - "mflo\t%0\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=&r" (quotient) - :"r" (timerhi), - "m" (timerlo), - "r" (tmp), - "r" (USECS_PER_JIFFY) - :"$1"); - cached_quotient = quotient; -#endif - } - - /* Get last timer tick in absolute kernel time */ - count = read_32bit_cp0_register(CP0_COUNT); - - /* .. relative to previous jiffy (32 bits is enough) */ - count -= timerlo; - - __asm__("multu\t%1,%2\n\t" - "mfhi\t%0" - :"=r" (res) - :"r" (count), - "r" (quotient)); - - /* - * Due to possible jiffies inconsistencies, we need to check - * the result so that we'll get a timer that is monotonic. - */ - if (res >= USECS_PER_JIFFY) - res = USECS_PER_JIFFY-1; - - return res; -} - -void do_gettimeofday(struct timeval *tv) -{ - unsigned long flags; - unsigned long seq; - - do { - seq = read_seqbegin_irqsave(&xtime_lock, flags); - - *tv = xtime; - tv->tv_usec += do_fast_gettimeoffset(); - - /* - * xtime is atomically updated in timer_bh. - * jiffies - wall_jiffies - * is nonzero if the timer bottom half hasnt executed yet. - */ - if (jiffies - wall_jiffies) - tv->tv_usec += USECS_PER_JIFFY; - - } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); - - if (tv->tv_usec >= 1000000) { - tv->tv_usec -= 1000000; - tv->tv_sec++; - } + local_irq_restore(flags); } -void do_settimeofday(struct timeval *tv) +void __init mips_timer_setup(struct irqaction *irq) { - write_seqlock_irq (&xtime_lock); - - /* This is revolting. We need to set the xtime.tv_usec correctly. - * However, the value in this location is is value at the last tick. - * Discover what correction gettimeofday would have done, and then - * undo it! - */ - tv->tv_usec -= do_fast_gettimeoffset(); - - if (tv->tv_usec < 0) { - tv->tv_usec += 1000000; - tv->tv_sec--; - } - - xtime = *tv; - time_adjust = 0; /* stop active adjtime() */ - time_status |= STA_UNSYNC; - time_maxerror = NTP_PHASE_LIMIT; - time_esterror = NTP_PHASE_LIMIT; - - write_sequnlock_irq (&xtime_lock); + /* we are using the cpu counter for timer interrupts */ + irq->handler = no_action; /* we use our own handler */ + setup_irq(MIPS_CPU_TIMER_IRQ, irq); + + /* to generate the first timer interrupt */ + r4k_cur = (read_c0_count() + r4k_offset); + write_c0_compare(r4k_cur); + set_c0_status(ALLINTS); } --- linux-2.5.73/arch/mips/mips-boards/malta/Makefile 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/malta/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -7,12 +7,12 @@ # This program is free software; you can distribute it and/or modify it # under the terms of the GNU General Public License (Version 2) as # published by the Free Software Foundation. -# +# # This program is distributed in the hope it will be useful, but WITHOUT # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License # for more details. -# +# # You should have received a copy of the GNU General Public License along # with this program; if not, write to the Free Software Foundation, Inc., # 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. --- linux-2.5.73/arch/mips/mips-boards/malta/malta_int.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/malta/malta_int.c 2003-06-27 15:56:23.000000000 -0700 @@ -16,65 +16,137 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * Routines for generic manipulation of the interrupts found on the MIPS + * Routines for generic manipulation of the interrupts found on the MIPS * Malta board. - * The interrupt controller is located in the South Bridge a PIIX4 device + * The interrupt controller is located in the South Bridge a PIIX4 device * with two internal 82C95 interrupt controllers. */ #include #include +#include #include #include #include #include #include -#include +#include #include +#include #include #include #include +#include #include -#include extern asmlinkage void mipsIRQ(void); +extern int mips_pcibios_iack(void); -void malta_hw0_irqdispatch(struct pt_regs *regs) +#ifdef CONFIG_KGDB +extern void breakpoint(void); +extern void set_debug_traps(void); +extern int remote_debug; +#endif + +static spinlock_t mips_irq_lock = SPIN_LOCK_UNLOCKED; + +static inline int get_int(int *irq) { - int irq; + unsigned long flags; - /* - * Determine highest priority pending interrupt by performing a PCI - * Interrupt Acknowledge cycle. - */ - GT_READ(GT_PCI0_IACK_OFS, irq); - irq &= 0xFF; + spin_lock_irqsave(&mips_irq_lock, flags); + + *irq = mips_pcibios_iack(); - /* - * IRQ7 is used to detect spurious interrupts. The interrupt - * acknowledge cycle returns IRQ7, if no interrupts is requested. We - * can differentiate between this situation and a "normal" IRQ7 by - * reading the ISR. + /* + * IRQ7 is used to detect spurious interrupts. + * The interrupt acknowledge cycle returns IRQ7, if no + * interrupts is requested. + * We can differentiate between this situation and a + * "Normal" IRQ7 by reading the ISR. */ - if (irq == 7) { - outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR, PIIX4_ICTLR1_OCW3); - if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) - return; /* Spurious interrupt. */ + if (*irq == 7) + { + outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR, + PIIX4_ICTLR1_OCW3); + if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) { + spin_unlock_irqrestore(&mips_irq_lock, flags); + printk("We got a spurious interrupt from PIIX4.\n"); + atomic_inc(&irq_err_count); + return -1; /* Spurious interrupt. */ + } } + spin_unlock_irqrestore(&mips_irq_lock, flags); + + return 0; +} + +void malta_hw0_irqdispatch(struct pt_regs *regs) +{ + int irq; + + if (get_int(&irq)) + return; /* interrupt has already been cleared */ + do_IRQ(irq, regs); } +void corehi_irqdispatch(struct pt_regs *regs) +{ + unsigned int data,datahi; + + /* Mask out corehi interrupt. */ + clear_c0_status(IE_IRQ3); + + printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); + printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n" +, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr); + switch(mips_revision_corid) { + case MIPS_REVISION_CORID_CORE_MSC: + break; + case MIPS_REVISION_CORID_QED_RM5261: + case MIPS_REVISION_CORID_CORE_LV: + case MIPS_REVISION_CORID_CORE_FPGA: + GT_READ(GT_INTRCAUSE_OFS, data); + printk("GT_INTRCAUSE = %08x\n", data); + GT_READ(0x70, data); + GT_READ(0x78, datahi); + printk("GT_CPU_ERR_ADDR = %0x2%08x\n", datahi,data); + break; + case MIPS_REVISION_CORID_BONITO64: + case MIPS_REVISION_CORID_CORE_20K: + data = BONITO_INTISR; + printk("BONITO_INTISR = %08x\n", data); + data = BONITO_INTEN; + printk("BONITO_INTEN = %08x\n", data); + data = BONITO_INTPOL; + printk("BONITO_INTPOL = %08x\n", data); + data = BONITO_INTEDGE; + printk("BONITO_INTEDGE = %08x\n", data); + data = BONITO_INTSTEER; + printk("BONITO_INTSTEER = %08x\n", data); + data = BONITO_PCICMD; + printk("BONITO_PCICMD = %08x\n", data); + break; + } + + /* We die here*/ + die("CoreHi interrupt", regs); +} + void __init init_IRQ(void) { set_except_vector(0, mipsIRQ); init_generic_irq(); init_i8259_irqs(); -#ifdef CONFIG_REMOTE_DEBUG +#ifdef CONFIG_KGDB if (remote_debug) { set_debug_traps(); breakpoint(); } #endif } + + --- linux-2.5.73/arch/mips/mips-boards/malta/malta_setup.c 2003-06-26 22:07:23.000000000 -0700 +++ 25/arch/mips/mips-boards/malta/malta_setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -36,17 +36,20 @@ #include #endif #include +#include +#include +#ifdef CONFIG_VT +#include +#endif #if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE) extern void console_setup(char *, int *); char serial_console[20]; #endif -#ifdef CONFIG_REMOTE_DEBUG -extern void set_debug_traps(void); +#ifdef CONFIG_KGDB extern void rs_kgdb_hook(int); -extern void breakpoint(void); -static int remote_debug = 0; +int remote_debug = 0; #endif extern struct ide_ops std_ide_ops; @@ -56,6 +59,10 @@ extern struct kbd_ops std_kbd_ops; extern void mips_reboot_setup(void); +extern void mips_time_init(void); +extern void mips_timer_setup(struct irqaction *irq); +extern unsigned long mips_rtc_get_time(void); + struct resource standard_io_resources[] = { { "dma1", 0x00, 0x1f, IORESOURCE_BUSY }, { "timer", 0x40, 0x5f, IORESOURCE_BUSY }, @@ -65,9 +72,14 @@ struct resource standard_io_resources[] #define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource)) +const char *get_system_type(void) +{ + return "MIPS Malta"; +} + void __init malta_setup(void) { -#ifdef CONFIG_REMOTE_DEBUG +#ifdef CONFIG_KGDB int rs_putDebugChar(char); char rs_getDebugChar(void); extern int (*generic_putDebugChar)(char); @@ -80,7 +92,7 @@ void __init malta_setup(void) for (i = 0; i < STANDARD_IO_RESOURCES; i++) request_resource(&ioport_resource, standard_io_resources+i); - /* + /* * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge. */ enable_dma(4); @@ -93,7 +105,7 @@ void __init malta_setup(void) } #endif -#ifdef CONFIG_REMOTE_DEBUG +#ifdef CONFIG_KGDB argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { int line; @@ -119,17 +131,38 @@ void __init malta_setup(void) argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "nofpu")) != NULL) - mips_cpu.options &= ~MIPS_CPU_FPU; - + cpu_data[0].options &= ~MIPS_CPU_FPU; + rtc_ops = &malta_rtc_ops; + #ifdef CONFIG_BLK_DEV_IDE ide_ops = &std_ide_ops; #endif #ifdef CONFIG_BLK_DEV_FD fd_ops = &std_fd_ops; #endif -#ifdef CONFIG_PC_KEYB - kbd_ops = &std_kbd_ops; +#ifdef CONFIG_VT +#if defined(CONFIG_VGA_CONSOLE) + conswitchp = &vga_con; + + screen_info = (struct screen_info) { + 0, 25, /* orig-x, orig-y */ + 0, /* unused */ + 0, /* orig-video-page */ + 0, /* orig-video-mode */ + 80, /* orig-video-cols */ + 0,0,0, /* ega_ax, ega_bx, ega_cx */ + 25, /* orig-video-lines */ + 1, /* orig-video-isVGA */ + 16 /* orig-video-points */ + }; +#elif defined(CONFIG_DUMMY_CONSOLE) + conswitchp = &dummy_con; +#endif #endif mips_reboot_setup(); + + board_time_init = mips_time_init; + board_timer_setup = mips_timer_setup; + rtc_get_time = mips_rtc_get_time; } --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mips-boards/sead/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,26 @@ +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. +# +# ######################################################################## +# +# This program is free software; you can distribute it and/or modify it +# under the terms of the GNU General Public License (Version 2) as +# published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. +# +# ####################################################################### +# +# Makefile for the MIPS SEAD specific kernel interface routines +# under Linux. +# + +obj-y := sead_int.o sead_setup.o sead_time.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mips-boards/sead/sead_int.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,115 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Routines for generic manipulation of the interrupts found on the MIPS + * Sead board. + * + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +extern asmlinkage void mipsIRQ(void); + +void disable_sead_irq(unsigned int irq_nr) +{ + if (irq_nr == SEADINT_UART0) + clear_c0_status(0x00000400); + else + if (irq_nr == SEADINT_UART1) + clear_c0_status(0x00000800); +} + +void enable_sead_irq(unsigned int irq_nr) +{ + if (irq_nr == SEADINT_UART0) + set_c0_status(0x00000400); + else + if (irq_nr == SEADINT_UART1) + set_c0_status(0x00000800); +} + +static unsigned int startup_sead_irq(unsigned int irq) +{ + enable_sead_irq(irq); + return 0; /* never anything pending */ +} + +#define shutdown_sead_irq disable_sead_irq + +#define mask_and_ack_sead_irq disable_sead_irq + +static void end_sead_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_sead_irq(irq); +} + +static struct hw_interrupt_type sead_irq_type = { + "SEAD", + startup_sead_irq, + shutdown_sead_irq, + enable_sead_irq, + disable_sead_irq, + mask_and_ack_sead_irq, + end_sead_irq, + NULL +}; + +void sead_hw0_irqdispatch(struct pt_regs *regs) +{ + do_IRQ(0, regs); +} + +void sead_hw1_irqdispatch(struct pt_regs *regs) +{ + do_IRQ(1, regs); +} + +void __init init_IRQ(void) +{ + int i; + + /* + * Mask out all interrupt + */ + clear_c0_status(0x0000ff00); + + /* Now safe to set the exception vector. */ + set_except_vector(0, mipsIRQ); + + init_generic_irq(); + + for (i = 0; i <= SEADINT_END; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].lock = SPIN_LOCK_UNLOCKED; + irq_desc[i].handler = &sead_irq_type; + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mips-boards/sead/sead_setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,77 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * SEAD specific setup. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE) +extern void console_setup(char *, int *); +char serial_console[20]; +#endif + +extern void mips_reboot_setup(void); +extern void mips_time_init(void); +extern void mips_timer_setup(struct irqaction *irq); + +const char *get_system_type(void) +{ + return "MIPS SEAD"; +} + +void __init sead_setup(void) +{ + char *argptr; + + ioport_resource.end = 0x7fffffff; + +#ifdef CONFIG_SERIAL_CONSOLE + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "console=ttyS0")) == NULL) { + int i = 0; + char *s = prom_getenv("modetty0"); + while(s[i] >= '0' && s[i] <= '9') + i++; + strcpy(serial_console, "ttyS0,"); + strncpy(serial_console + 6, s, i); + prom_printf("Config serial console: %s\n", serial_console); + console_setup(serial_console, NULL); + } +#endif + + argptr = prom_getcmdline(); + + if ((argptr = strstr(argptr, "nofpu")) != NULL) + cpu_data[0].options &= ~MIPS_CPU_FPU; + + board_time_init = mips_time_init; + board_timer_setup = mips_timer_setup; + + mips_reboot_setup(); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mips-boards/sead/sead_time.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,142 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Setting up the clock on the MIPS boards. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include + +extern volatile unsigned long wall_jiffies; + +static unsigned long r4k_offset; /* Amount to increment compare reg each time */ +static unsigned long r4k_cur; /* What counter should be at next timer irq */ + +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ5) + +static char display_string[] = " LINUX ON SEAD "; + +static unsigned int display_count = 0; +#define MAX_DISPLAY_COUNT (sizeof(display_string) - 8) + +#define MIPS_CPU_TIMER_IRQ 7 + +static unsigned int timer_tick_count=0; + +static inline void ack_r4ktimer(unsigned long newval) +{ + write_c0_compare(newval); +} + +/* + * There are a lot of conceptually broken versions of the MIPS timer interrupt + * handler floating around. This one is rather different, but the algorithm + * is provably more robust. + */ +void mips_timer_interrupt(struct pt_regs *regs) +{ + int cpu = smp_processor_id(); + int irq = MIPS_CPU_TIMER_IRQ; + + irq_enter(); + + do { + kstat_cpu(cpu).irqs[irq]++; + do_timer(regs); + + if ((timer_tick_count++ % HZ) == 0) { + mips_display_message(&display_string[display_count++]); + if (display_count == MAX_DISPLAY_COUNT) + display_count = 0; + } + + r4k_cur += r4k_offset; + ack_r4ktimer(r4k_cur); + + } while (((unsigned long)read_c0_count() + - r4k_cur) < 0x7fffffff); + + irq_exit(); + if (softirq_pending(cpu)) + do_softirq(); +} + +/* + * Figure out the r4k offset, the amount to increment the compare + * register for each time tick. + */ +static unsigned long __init cal_r4koff(void) +{ + /* + * The SEAD board doesn't have a real time clock, so we can't + * really calculate the timer offset. + * For now we hardwire the SEAD board frequency to 12MHz. + */ + return(6000000/HZ); +} + +void __init mips_time_init(void) +{ + unsigned int est_freq, flags; + + local_irq_save(flags); + + /* Start r4k counter. */ + write_c0_count(0); + + printk("calculating r4koff... "); + r4k_offset = cal_r4koff(); + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); + + if ((read_c0_prid() & 0xffff00) == + (PRID_COMP_MIPS | PRID_IMP_20KC)) + est_freq = r4k_offset*HZ; + else + est_freq = 2*r4k_offset*HZ; + + est_freq += 5000; /* round */ + est_freq -= est_freq%10000; + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, + (est_freq%1000000)*100/1000000); + + local_irq_restore(flags); +} + +void __init mips_timer_setup(struct irqaction *irq) +{ + /* we are using the cpu counter for timer interrupts */ + irq->handler = no_action; /* we use our own handler */ + setup_irq(MIPS_CPU_TIMER_IRQ, irq); + + /* to generate the first timer interrupt */ + r4k_cur = (read_c0_count() + r4k_offset); + write_c0_compare(r4k_cur); + set_c0_status(ALLINTS); +} --- linux-2.5.73/arch/mips/mm/andes.c 2003-06-26 22:07:23.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,196 +0,0 @@ -/* - * andes.c: MMU and cache operations for the R10000 (ANDES). - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* page functions */ -void andes_clear_page(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "addiu\t$1,%0,%2\n" - "1:\tsw\t$0,(%0)\n\t" - "sw\t$0,4(%0)\n\t" - "sw\t$0,8(%0)\n\t" - "sw\t$0,12(%0)\n\t" - "addiu\t%0,32\n\t" - "sw\t$0,-16(%0)\n\t" - "sw\t$0,-12(%0)\n\t" - "sw\t$0,-8(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sw\t$0,-4(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE) - :"$1","memory"); -} - -static void andes_copy_page(void * to, void * from) -{ - unsigned long dummy1, dummy2; - unsigned long reg1, reg2, reg3, reg4; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "addiu\t$1,%0,%8\n" - "1:\tlw\t%2,(%1)\n\t" - "lw\t%3,4(%1)\n\t" - "lw\t%4,8(%1)\n\t" - "lw\t%5,12(%1)\n\t" - "sw\t%2,(%0)\n\t" - "sw\t%3,4(%0)\n\t" - "sw\t%4,8(%0)\n\t" - "sw\t%5,12(%0)\n\t" - "lw\t%2,16(%1)\n\t" - "lw\t%3,20(%1)\n\t" - "lw\t%4,24(%1)\n\t" - "lw\t%5,28(%1)\n\t" - "sw\t%2,16(%0)\n\t" - "sw\t%3,20(%0)\n\t" - "sw\t%4,24(%0)\n\t" - "sw\t%5,28(%0)\n\t" - "addiu\t%0,64\n\t" - "addiu\t%1,64\n\t" - "lw\t%2,-32(%1)\n\t" - "lw\t%3,-28(%1)\n\t" - "lw\t%4,-24(%1)\n\t" - "lw\t%5,-20(%1)\n\t" - "sw\t%2,-32(%0)\n\t" - "sw\t%3,-28(%0)\n\t" - "sw\t%4,-24(%0)\n\t" - "sw\t%5,-20(%0)\n\t" - "lw\t%2,-16(%1)\n\t" - "lw\t%3,-12(%1)\n\t" - "lw\t%4,-8(%1)\n\t" - "lw\t%5,-4(%1)\n\t" - "sw\t%2,-16(%0)\n\t" - "sw\t%3,-12(%0)\n\t" - "sw\t%4,-8(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sw\t%5,-4(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), - "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) - :"0" (to), "1" (from), - "I" (PAGE_SIZE)); -} - -/* Cache operations. XXX Write these dave... */ -static inline void andes_flush_cache_all(void) -{ - /* XXX */ -} - -static void andes_flush_cache_mm(struct mm_struct *mm) -{ - /* XXX */ -} - -static void andes_flush_cache_range(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - /* XXX */ -} - -static void andes_flush_cache_page(struct vm_area_struct *vma, - unsigned long page) -{ - /* XXX */ -} - -static void andes_flush_page_to_ram(struct page * page) -{ - /* XXX */ -} - -static void __andes_flush_icache_range(unsigned long start, unsigned long end) -{ - /* XXX */ -} - -static void andes_flush_icache_page(struct vm_area_struct *vma, - struct page *page) -{ - /* XXX */ -} - -static void andes_flush_cache_sigtramp(unsigned long page) -{ - protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); - protected_flush_icache_line(addr & ~(ic_lsize - 1)); -} - -/* TLB operations. XXX Write these dave... */ -void flush_tlb_all(void) -{ - /* XXX */ -} - -void flush_tlb_mm(struct mm_struct *mm) -{ - /* XXX */ -} - -void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) -{ - /* XXX */ -} - -void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) -{ - /* XXX */ -} - -void pgd_init(unsigned long page) -{ -} - -void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask) -{ - /* XXX */ -} - -void __init ld_mmu_andes(void) -{ - _clear_page = andes_clear_page; - _copy_page = andes_copy_page; - - _flush_cache_all = andes_flush_cache_all; - ___flush_cache_all = andes_flush_cache_all; - _flush_cache_mm = andes_flush_cache_mm; - _flush_cache_range = andes_flush_cache_range; - _flush_cache_page = andes_flush_cache_page; - _flush_cache_sigtramp = andes_flush_cache_sigtramp; - _flush_page_to_ram = andes_flush_page_to_ram; - _flush_icache_page = andes_flush_icache_page; - _flush_icache_range = andes_flush_icache_range; - - write_32bit_cp0_register(CP0_FRAMEMASK, 0); - - flush_cache_all(); - flush_tlb_all(); - - /* - * The R10k might even work for Linux/MIPS - but we're paranoid - * and refuse to run until this is tested on real silicon - */ - panic("CPU too expensive - making holiday in the ANDES!"); -} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/cache.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,60 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 2003 by Ralf Baechle + */ +#include +#include +#include + +#include + +asmlinkage int sys_cacheflush(void *addr, int bytes, int cache) +{ + /* This should flush more selectivly ... */ + __flush_cache_all(); + + return 0; +} + +void flush_dcache_page(struct page *page) +{ + unsigned long addr; + + if (page->mapping && + list_empty(&page->mapping->i_mmap) && + list_empty(&page->mapping->i_mmap_shared)) { + SetPageDcacheDirty(page); + + return; + } + + /* + * We could delay the flush for the !page->mapping case too. But that + * case is for exec env/arg pages and those are %99 certainly going to + * get faulted into the tlb (and thus flushed) anyways. + */ + addr = (unsigned long) page_address(page); + flush_data_cache_page(addr); +} + +void __update_cache(struct vm_area_struct *vma, unsigned long address, + pte_t pte) +{ + struct page *page; + unsigned long pfn, addr; + + pfn = pte_pfn(pte); + if (pfn_valid(pfn) && (page = pfn_to_page(pfn), page->mapping) && + Page_dcache_dirty(page)) { + if (pages_do_alias((unsigned long)page_address(page), + address & PAGE_MASK)) { + addr = (unsigned long) page_address(page); + flush_data_cache_page(addr); + } + + ClearPageDcacheDirty(page); + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/cerr-sb1.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,542 @@ +/* + * Copyright (C) 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include + +#ifndef CONFIG_SIBYTE_BUS_WATCHER +#include +#include +#include +#include +#endif + +/* SB1 definitions */ + +/* XXX should come from config1 XXX */ +#define SB1_CACHE_INDEX_MASK 0x1fe0 + +#define CP0_ERRCTL_RECOVERABLE (1 << 31) +#define CP0_ERRCTL_DCACHE (1 << 30) +#define CP0_ERRCTL_ICACHE (1 << 29) +#define CP0_ERRCTL_MULTIBUS (1 << 23) +#define CP0_ERRCTL_MC_TLB (1 << 15) +#define CP0_ERRCTL_MC_TIMEOUT (1 << 14) + +#define CP0_CERRI_TAG_PARITY (1 << 29) +#define CP0_CERRI_DATA_PARITY (1 << 28) +#define CP0_CERRI_EXTERNAL (1 << 26) + +#define CP0_CERRI_IDX_VALID(c) (!((c) & CP0_CERRI_EXTERNAL)) +#define CP0_CERRI_DATA (CP0_CERRI_DATA_PARITY) + +#define CP0_CERRD_MULTIPLE (1 << 31) +#define CP0_CERRD_TAG_STATE (1 << 30) +#define CP0_CERRD_TAG_ADDRESS (1 << 29) +#define CP0_CERRD_DATA_SBE (1 << 28) +#define CP0_CERRD_DATA_DBE (1 << 27) +#define CP0_CERRD_EXTERNAL (1 << 26) +#define CP0_CERRD_LOAD (1 << 25) +#define CP0_CERRD_STORE (1 << 24) +#define CP0_CERRD_FILLWB (1 << 23) +#define CP0_CERRD_COHERENCY (1 << 22) +#define CP0_CERRD_DUPTAG (1 << 21) + +#define CP0_CERRD_DPA_VALID(c) (!((c) & CP0_CERRD_EXTERNAL)) +#define CP0_CERRD_IDX_VALID(c) \ + (((c) & (CP0_CERRD_LOAD | CP0_CERRD_STORE)) ? (!((c) & CP0_CERRD_EXTERNAL)) : 0) +#define CP0_CERRD_CAUSES \ + (CP0_CERRD_LOAD | CP0_CERRD_STORE | CP0_CERRD_FILLWB | CP0_CERRD_COHERENCY | CP0_CERRD_DUPTAG) +#define CP0_CERRD_TYPES \ + (CP0_CERRD_TAG_STATE | CP0_CERRD_TAG_ADDRESS | CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE | CP0_CERRD_EXTERNAL) +#define CP0_CERRD_DATA (CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE) + +static uint32_t extract_ic(unsigned short addr, int data); +static uint32_t extract_dc(unsigned short addr, int data); + +static inline void breakout_errctl(unsigned int val) +{ + if (val & CP0_ERRCTL_RECOVERABLE) + prom_printf(" recoverable"); + if (val & CP0_ERRCTL_DCACHE) + prom_printf(" dcache"); + if (val & CP0_ERRCTL_ICACHE) + prom_printf(" icache"); + if (val & CP0_ERRCTL_MULTIBUS) + prom_printf(" multiple-buserr"); + prom_printf("\n"); +} + +static inline void breakout_cerri(unsigned int val) +{ + if (val & CP0_CERRI_TAG_PARITY) + prom_printf(" tag-parity"); + if (val & CP0_CERRI_DATA_PARITY) + prom_printf(" data-parity"); + if (val & CP0_CERRI_EXTERNAL) + prom_printf(" external"); + prom_printf("\n"); +} + +static inline void breakout_cerrd(unsigned int val) +{ + switch (val & CP0_CERRD_CAUSES) { + case CP0_CERRD_LOAD: + prom_printf(" load,"); + break; + case CP0_CERRD_STORE: + prom_printf(" store,"); + break; + case CP0_CERRD_FILLWB: + prom_printf(" fill/wb,"); + break; + case CP0_CERRD_COHERENCY: + prom_printf(" coherency,"); + break; + case CP0_CERRD_DUPTAG: + prom_printf(" duptags,"); + break; + default: + prom_printf(" NO CAUSE,"); + break; + } + if (!(val & CP0_CERRD_TYPES)) + prom_printf(" NO TYPE"); + else { + if (val & CP0_CERRD_MULTIPLE) + prom_printf(" multi-err"); + if (val & CP0_CERRD_TAG_STATE) + prom_printf(" tag-state"); + if (val & CP0_CERRD_TAG_ADDRESS) + prom_printf(" tag-address"); + if (val & CP0_CERRD_DATA_SBE) + prom_printf(" data-SBE"); + if (val & CP0_CERRD_DATA_DBE) + prom_printf(" data-DBE"); + if (val & CP0_CERRD_EXTERNAL) + prom_printf(" external"); + } + prom_printf("\n"); +} + +#ifndef CONFIG_SIBYTE_BUS_WATCHER + +static void check_bus_watcher(void) +{ + uint32_t status, l2_err, memio_err; + + /* Destructive read, clears register and interrupt */ + status = csr_in32(IO_SPACE_BASE | A_SCD_BUS_ERR_STATUS); + /* Bit 31 is always on, but there's no #define for that */ + if (status & ~(1UL << 31)) { + l2_err = csr_in32(IO_SPACE_BASE | A_BUS_L2_ERRORS); + memio_err = csr_in32(IO_SPACE_BASE | A_BUS_MEM_IO_ERRORS); + prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); + prom_printf("\nLast recorded signature:\n"); + prom_printf("Request %02x from %d, answered by %d with Dcode %d\n", + (unsigned int)(G_SCD_BERR_TID(status) & 0x3f), + (int)(G_SCD_BERR_TID(status) >> 6), + (int)G_SCD_BERR_RID(status), + (int)G_SCD_BERR_DCODE(status)); + } else { + prom_printf("Bus watcher indicates no error\n"); + } +} +#else +extern void check_bus_watcher(void); +#endif + +asmlinkage void sb1_cache_error(void) +{ + uint64_t cerr_dpa; + uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res; + + prom_printf("Cache error exception on CPU %x:\n", + (read_c0_prid() >> 25) & 0x7); + + __asm__ __volatile__ ( + " .set push\n\t" + " .set mips64\n\t" + " .set noat\n\t" + " mfc0 %0, $26\n\t" + " mfc0 %1, $27\n\t" + " mfc0 %2, $27, 1\n\t" + " dmfc0 $1, $27, 3\n\t" + " dsrl32 %3, $1, 0 \n\t" + " sll %4, $1, 0 \n\t" + " mfc0 %5, $30\n\t" + " .set pop" + : "=r" (errctl), "=r" (cerr_i), "=r" (cerr_d), + "=r" (dpahi), "=r" (dpalo), "=r" (eepc)); + + cerr_dpa = (((uint64_t)dpahi) << 32) | dpalo; + prom_printf(" cp0_errorepc == %08x\n", eepc); + prom_printf(" cp0_errctl == %08x", errctl); + breakout_errctl(errctl); + if (errctl & CP0_ERRCTL_ICACHE) { + prom_printf(" cp0_cerr_i == %08x", cerr_i); + breakout_cerri(cerr_i); + if (CP0_CERRI_IDX_VALID(cerr_i)) { + if ((eepc & SB1_CACHE_INDEX_MASK) != (cerr_i & SB1_CACHE_INDEX_MASK)) + prom_printf(" cerr_i idx doesn't match eepc\n"); + else { + res = extract_ic(cerr_i & SB1_CACHE_INDEX_MASK, + (cerr_i & CP0_CERRI_DATA) != 0); + if (!(res & cerr_i)) + prom_printf("...didn't see indicated icache problem\n"); + } + } + } + if (errctl & CP0_ERRCTL_DCACHE) { + prom_printf(" cp0_cerr_d == %08x", cerr_d); + breakout_cerrd(cerr_d); + if (CP0_CERRD_DPA_VALID(cerr_d)) { + prom_printf(" cp0_cerr_dpa == %010llx\n", cerr_dpa); + if (!CP0_CERRD_IDX_VALID(cerr_d)) { + res = extract_dc(cerr_dpa & SB1_CACHE_INDEX_MASK, + (cerr_d & CP0_CERRD_DATA) != 0); + if (!(res & cerr_d)) + prom_printf("...didn't see indicated dcache problem\n"); + } else { + if ((cerr_dpa & SB1_CACHE_INDEX_MASK) != (cerr_d & SB1_CACHE_INDEX_MASK)) + prom_printf(" cerr_d idx doesn't match cerr_dpa\n"); + else { + res = extract_dc(cerr_d & SB1_CACHE_INDEX_MASK, + (cerr_d & CP0_CERRD_DATA) != 0); + if (!(res & cerr_d)) + prom_printf("...didn't see indicated problem\n"); + } + } + } + } + + check_bus_watcher(); + + while (1); + /* + * This tends to make things get really ugly; let's just stall instead. + * panic("Can't handle the cache error!"); + */ +} + + +/* Parity lookup table. */ +static const uint8_t parity[256] = { + 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, + 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, + 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, + 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, + 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, + 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, + 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, + 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0 +}; + +/* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */ +static const uint64_t mask_72_64[8] = { + 0x0738C808099264FFL, + 0x38C808099264FF07L, + 0xC808099264FF0738L, + 0x08099264FF0738C8L, + 0x099264FF0738C808L, + 0x9264FF0738C80809L, + 0x64FF0738C8080992L, + 0xFF0738C808099264L +}; + +/* Calculate the parity on a range of bits */ +static char range_parity(uint64_t dword, int max, int min) +{ + char parity = 0; + int i; + dword >>= min; + for (i=max-min; i>=0; i--) { + if (dword & 0x1) + parity = !parity; + dword >>= 1; + } + return parity; +} + +/* Calculate the 4-bit even byte-parity for an instruction */ +static unsigned char inst_parity(uint32_t word) +{ + int i, j; + char parity = 0; + for (j=0; j<4; j++) { + char byte_parity = 0; + for (i=0; i<8; i++) { + if (word & 0x80000000) + byte_parity = !byte_parity; + word <<= 1; + } + parity <<= 1; + parity |= byte_parity; + } + return parity; +} + +static uint32_t extract_ic(unsigned short addr, int data) +{ + unsigned short way; + int valid; + uint64_t taglo, va, tlo_tmp; + uint32_t taghi, taglolo, taglohi; + uint8_t lru; + int res = 0; + + prom_printf("Icache index 0x%04x ", addr); + for (way = 0; way < 4; way++) { + /* Index-load-tag-I */ + __asm__ __volatile__ ( + " .set push \n\t" + " .set noreorder \n\t" + " .set mips64 \n\t" + " .set noat \n\t" + " cache 4, 0(%3) \n\t" + " mfc0 %0, $29 \n\t" + " dmfc0 $1, $28 \n\t" + " dsrl32 %1, $1, 0 \n\t" + " sll %2, $1, 0 \n\t" + " .set pop" + : "=r" (taghi), "=r" (taglohi), "=r" (taglolo) + : "r" ((way << 13) | addr)); + + taglo = ((unsigned long long)taglohi << 32) | taglolo; + if (way == 0) { + lru = (taghi >> 14) & 0xff; + prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", + ((addr >> 5) & 0x3), /* bank */ + ((addr >> 7) & 0x3f), /* index */ + (lru & 0x3), + ((lru >> 2) & 0x3), + ((lru >> 4) & 0x3), + ((lru >> 6) & 0x3)); + } + va = (taglo & 0xC0000FFFFFFFE000) | addr; + if ((taglo & (1 << 31)) && (((taglo >> 62) & 0x3) == 3)) + va |= 0x3FFFF00000000000; + valid = ((taghi >> 29) & 1); + if (valid) { + tlo_tmp = taglo & 0xfff3ff; + if (((taglo >> 10) & 1) ^ range_parity(tlo_tmp, 23, 0)) { + prom_printf(" ** bad parity in VTag0/G/ASID\n"); + res |= CP0_CERRI_TAG_PARITY; + } + if (((taglo >> 11) & 1) ^ range_parity(taglo, 63, 24)) { + prom_printf(" ** bad parity in R/VTag1\n"); + res |= CP0_CERRI_TAG_PARITY; + } + } + if (valid ^ ((taghi >> 27) & 1)) { + prom_printf(" ** bad parity for valid bit\n"); + res |= CP0_CERRI_TAG_PARITY; + } + prom_printf(" %d [VA %016llx] [Vld? %d] raw tags: %08X-%016llX\n", + way, va, valid, taghi, taglo); + + if (data) { + uint32_t datahi, insta, instb; + uint8_t predecode; + int offset; + + /* (hit all banks and ways) */ + for (offset = 0; offset < 4; offset++) { + /* Index-load-data-I */ + __asm__ __volatile__ ( + " .set push\n\t" + " .set noreorder\n\t" + " .set mips64\n\t" + " .set noat\n\t" + " cache 6, 0(%3) \n\t" + " mfc0 %0, $29, 1\n\t" + " dmfc0 $1, $28, 1\n\t" + " dsrl32 %1, $1, 0 \n\t" + " sll %2, $1, 0 \n\t" + " .set pop \n" + : "=r" (datahi), "=r" (insta), "=r" (instb) + : "r" ((way << 13) | addr | (offset << 3))); + predecode = (datahi >> 8) & 0xff; + if (((datahi >> 16) & 1) != (uint32_t)range_parity(predecode, 7, 0)) { + prom_printf(" ** bad parity in predecode\n"); + res |= CP0_CERRI_DATA_PARITY; + } + /* XXXKW should/could check predecode bits themselves */ + if (((datahi >> 4) & 0xf) ^ inst_parity(insta)) { + prom_printf(" ** bad parity in instruction a\n"); + res |= CP0_CERRI_DATA_PARITY; + } + if ((datahi & 0xf) ^ inst_parity(instb)) { + prom_printf(" ** bad parity in instruction b\n"); + res |= CP0_CERRI_DATA_PARITY; + } + prom_printf(" %05X-%08X%08X", datahi, insta, instb); + } + prom_printf("\n"); + } + } + return res; +} + +/* Compute the ECC for a data doubleword */ +static uint8_t dc_ecc(uint64_t dword) +{ + uint64_t t; + uint32_t w; + uint8_t p; + int i; + + p = 0; + for (i = 7; i >= 0; i--) + { + p <<= 1; + t = dword & mask_72_64[i]; + w = (uint32_t)(t >> 32); + p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF] + ^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]); + w = (uint32_t)(t & 0xFFFFFFFF); + p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF] + ^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]); + } + return p; +} + +struct dc_state { + unsigned char val; + char *name; +}; + +static struct dc_state dc_states[] = { + { 0x00, "INVALID" }, + { 0x0f, "COH-SHD" }, + { 0x13, "NCO-E-C" }, + { 0x19, "NCO-E-D" }, + { 0x16, "COH-E-C" }, + { 0x1c, "COH-E-D" }, + { 0xff, "*ERROR*" } +}; + +#define DC_TAG_VALID(state) \ + (((state) == 0xf) || ((state) == 0x13) || ((state) == 0x19) || ((state == 0x16)) || ((state) == 0x1c)) + +static char *dc_state_str(unsigned char state) +{ + struct dc_state *dsc = dc_states; + while (dsc->val != 0xff) { + if (dsc->val == state) + break; + dsc++; + } + return dsc->name; +} + +static uint32_t extract_dc(unsigned short addr, int data) +{ + int valid, way; + unsigned char state; + uint64_t taglo, pa; + uint32_t taghi, taglolo, taglohi; + uint8_t ecc, lru; + int res = 0; + + prom_printf("Dcache index 0x%04x ", addr); + for (way = 0; way < 4; way++) { + __asm__ __volatile__ ( + " .set push\n\t" + " .set noreorder\n\t" + " .set mips64\n\t" + " .set noat\n\t" + " cache 5, 0(%3)\n\t" /* Index-load-tag-D */ + " mfc0 %0, $29, 2\n\t" + " dmfc0 $1, $28, 2\n\t" + " dsrl32 %1, $1, 0\n\t" + " sll %2, $1, 0\n\t" + " .set pop" + : "=r" (taghi), "=r" (taglohi), "=r" (taglolo) + : "r" ((way << 13) | addr)); + + taglo = ((unsigned long long)taglohi << 32) | taglolo; + pa = (taglo & 0xFFFFFFE000) | addr; + if (way == 0) { + lru = (taghi >> 14) & 0xff; + prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", + ((addr >> 11) & 0x2) | ((addr >> 5) & 1), /* bank */ + ((addr >> 6) & 0x3f), /* index */ + (lru & 0x3), + ((lru >> 2) & 0x3), + ((lru >> 4) & 0x3), + ((lru >> 6) & 0x3)); + } + state = (taghi >> 25) & 0x1f; + valid = DC_TAG_VALID(state); + prom_printf(" %d [PA %010llx] [state %s (%02x)] raw tags: %08X-%016llX\n", + way, pa, dc_state_str(state), state, taghi, taglo); + if (valid) { + if (((taglo >> 11) & 1) ^ range_parity(taglo, 39, 26)) { + prom_printf(" ** bad parity in PTag1\n"); + res |= CP0_CERRD_TAG_ADDRESS; + } + if (((taglo >> 10) & 1) ^ range_parity(taglo, 25, 13)) { + prom_printf(" ** bad parity in PTag0\n"); + res |= CP0_CERRD_TAG_ADDRESS; + } + } else { + res |= CP0_CERRD_TAG_STATE; + } + + if (data) { + uint64_t datalo; + uint32_t datalohi, datalolo, datahi; + int offset; + + for (offset = 0; offset < 4; offset++) { + /* Index-load-data-D */ + __asm__ __volatile__ ( + " .set push\n\t" + " .set noreorder\n\t" + " .set mips64\n\t" + " .set noat\n\t" + " cache 7, 0(%3)\n\t" /* Index-load-data-D */ + " mfc0 %0, $29, 3\n\t" + " dmfc0 $1, $28, 3\n\t" + " dsrl32 %1, $1, 0 \n\t" + " sll %2, $1, 0 \n\t" + " .set pop" + : "=r" (datahi), "=r" (datalohi), "=r" (datalolo) + : "r" ((way << 13) | addr | (offset << 3))); + datalo = ((unsigned long long)datalohi << 32) | datalolo; + ecc = dc_ecc(datalo); + if (ecc != datahi) { + int bits = 0; + prom_printf(" ** bad ECC (%02x %02x) ->", + datahi, ecc); + ecc ^= datahi; + while (ecc) { + if (ecc & 1) bits++; + ecc >>= 1; + } + res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE; + } + prom_printf(" %02X-%016llX", datahi, datalo); + } + prom_printf("\n"); + } + } + return res; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/cex-sb1.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2001,2002,2003 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include +#include + +#include +#include +#include +#include +#include + + .text + .set noat + .set mips4 + + __INIT + + /* Cache Error handler for SB1 */ + LEAF(except_vec2_sb1) + mfc0 k1, $26 + # check if error was recoverable + bltz k1, leave_cerr +#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS + # look for signature of spurious CErr + lui k0, 0x4000 + bne k0, k1, 1f + .word 0x401Bd801 # mfc0 k1, $27, 1 + lui k0, 0xffe0 + and k1, k0, k1 + lui k0, 0x0200 + beq k0, k1, leave_cerr +1: +#endif + j handle_vec2_sb1 + +leave_cerr: + # clear/unlock the registers + mtc0 zero, $26 + mtc0 zero, $27 + .word 0x4080d801 # mtc0 zero, $27, 1 + .word 0x4080d803 # mtc0 zero, $27, 3 + eret + END(except_vec2_sb1) + + __FINIT + + LEAF(handle_vec2_sb1) + mfc0 k0,CP0_CONFIG + li k1,~CONF_CM_CMASK + and k0,k0,k1 + ori k0,k0,CONF_CM_UNCACHED + mtc0 k0,CP0_CONFIG + + SSNOP + SSNOP + SSNOP + SSNOP + bnezl $0, 1f +1: + mfc0 k0, CP0_STATUS + sll k0, k0, 3 # check CU0 (kernel?) + bltz k0, 2f + GET_SAVED_SP + move sp, k0 # want Kseg SP (so uncached) +2: + j sb1_cache_error + + END(handle_vec2_sb1) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/c-r3k.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,344 @@ +/* + * r2300.c: R2000 and R3000 specific mmu/cache code. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * + * with a lot of changes to make this thing work for R3000s + * Tx39XX R4k style caches added. HK + * Copyright (C) 1998, 1999, 2000 Harald Koerfgen + * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov + * Copyright (C) 2001 Maciej W. Rozycki + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +void r3k_clear_page(void * page); +void r3k_copy_page(void * to, void * from); + +static unsigned long icache_size, dcache_size; /* Size in bytes */ +static unsigned long icache_lsize, dcache_lsize; /* Size in bytes */ + +#undef DEBUG_CACHE + +unsigned long __init r3k_cache_size(unsigned long ca_flags) +{ + unsigned long flags, status, dummy, size; + volatile unsigned long *p; + + p = (volatile unsigned long *) KSEG0; + + flags = read_c0_status(); + + /* isolate cache space */ + write_c0_status((ca_flags|flags)&~ST0_IEC); + + *p = 0xa5a55a5a; + dummy = *p; + status = read_c0_status(); + + if (dummy != 0xa5a55a5a || (status & ST0_CM)) { + size = 0; + } else { + for (size = 128; size <= 0x40000; size <<= 1) + *(p + size) = 0; + *p = -1; + for (size = 128; + (size <= 0x40000) && (*(p + size) == 0); + size <<= 1) + ; + if (size > 0x40000) + size = 0; + } + + write_c0_status(flags); + + return size * sizeof(*p); +} + +unsigned long __init r3k_cache_lsize(unsigned long ca_flags) +{ + unsigned long flags, status, lsize, i; + volatile unsigned long *p; + + p = (volatile unsigned long *) KSEG0; + + flags = read_c0_status(); + + /* isolate cache space */ + write_c0_status((ca_flags|flags)&~ST0_IEC); + + for (i = 0; i < 128; i++) + *(p + i) = 0; + *(volatile unsigned char *)p = 0; + for (lsize = 1; lsize < 128; lsize <<= 1) { + *(p + lsize); + status = read_c0_status(); + if (!(status & ST0_CM)) + break; + } + for (i = 0; i < 128; i += lsize) + *(volatile unsigned char *)(p + i) = 0; + + write_c0_status(flags); + + return lsize * sizeof(*p); +} + +static void __init r3k_probe_cache(void) +{ + dcache_size = r3k_cache_size(ST0_ISC); + if (dcache_size) + dcache_lsize = r3k_cache_lsize(ST0_ISC); + + icache_size = r3k_cache_size(ST0_ISC|ST0_SWC); + if (icache_size) + icache_lsize = r3k_cache_lsize(ST0_ISC|ST0_SWC); +} + +static void r3k_flush_icache_range(unsigned long start, unsigned long end) +{ + unsigned long size, i, flags; + volatile unsigned char *p; + + size = end - start; + if (size > icache_size || KSEGX(start) != KSEG0) { + start = KSEG0; + size = icache_size; + } + p = (char *)start; + + flags = read_c0_status(); + + /* isolate cache space */ + write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC); + + for (i = 0; i < size; i += 0x080) { + asm ( "sb\t$0, 0x000(%0)\n\t" + "sb\t$0, 0x004(%0)\n\t" + "sb\t$0, 0x008(%0)\n\t" + "sb\t$0, 0x00c(%0)\n\t" + "sb\t$0, 0x010(%0)\n\t" + "sb\t$0, 0x014(%0)\n\t" + "sb\t$0, 0x018(%0)\n\t" + "sb\t$0, 0x01c(%0)\n\t" + "sb\t$0, 0x020(%0)\n\t" + "sb\t$0, 0x024(%0)\n\t" + "sb\t$0, 0x028(%0)\n\t" + "sb\t$0, 0x02c(%0)\n\t" + "sb\t$0, 0x030(%0)\n\t" + "sb\t$0, 0x034(%0)\n\t" + "sb\t$0, 0x038(%0)\n\t" + "sb\t$0, 0x03c(%0)\n\t" + "sb\t$0, 0x040(%0)\n\t" + "sb\t$0, 0x044(%0)\n\t" + "sb\t$0, 0x048(%0)\n\t" + "sb\t$0, 0x04c(%0)\n\t" + "sb\t$0, 0x050(%0)\n\t" + "sb\t$0, 0x054(%0)\n\t" + "sb\t$0, 0x058(%0)\n\t" + "sb\t$0, 0x05c(%0)\n\t" + "sb\t$0, 0x060(%0)\n\t" + "sb\t$0, 0x064(%0)\n\t" + "sb\t$0, 0x068(%0)\n\t" + "sb\t$0, 0x06c(%0)\n\t" + "sb\t$0, 0x070(%0)\n\t" + "sb\t$0, 0x074(%0)\n\t" + "sb\t$0, 0x078(%0)\n\t" + "sb\t$0, 0x07c(%0)\n\t" + : : "r" (p) ); + p += 0x080; + } + + write_c0_status(flags); +} + +static void r3k_flush_dcache_range(unsigned long start, unsigned long end) +{ + unsigned long size, i, flags; + volatile unsigned char *p; + + size = end - start; + if (size > dcache_size || KSEGX(start) != KSEG0) { + start = KSEG0; + size = dcache_size; + } + p = (char *)start; + + flags = read_c0_status(); + + /* isolate cache space */ + write_c0_status((ST0_ISC|flags)&~ST0_IEC); + + for (i = 0; i < size; i += 0x080) { + asm ( "sb\t$0, 0x000(%0)\n\t" + "sb\t$0, 0x004(%0)\n\t" + "sb\t$0, 0x008(%0)\n\t" + "sb\t$0, 0x00c(%0)\n\t" + "sb\t$0, 0x010(%0)\n\t" + "sb\t$0, 0x014(%0)\n\t" + "sb\t$0, 0x018(%0)\n\t" + "sb\t$0, 0x01c(%0)\n\t" + "sb\t$0, 0x020(%0)\n\t" + "sb\t$0, 0x024(%0)\n\t" + "sb\t$0, 0x028(%0)\n\t" + "sb\t$0, 0x02c(%0)\n\t" + "sb\t$0, 0x030(%0)\n\t" + "sb\t$0, 0x034(%0)\n\t" + "sb\t$0, 0x038(%0)\n\t" + "sb\t$0, 0x03c(%0)\n\t" + "sb\t$0, 0x040(%0)\n\t" + "sb\t$0, 0x044(%0)\n\t" + "sb\t$0, 0x048(%0)\n\t" + "sb\t$0, 0x04c(%0)\n\t" + "sb\t$0, 0x050(%0)\n\t" + "sb\t$0, 0x054(%0)\n\t" + "sb\t$0, 0x058(%0)\n\t" + "sb\t$0, 0x05c(%0)\n\t" + "sb\t$0, 0x060(%0)\n\t" + "sb\t$0, 0x064(%0)\n\t" + "sb\t$0, 0x068(%0)\n\t" + "sb\t$0, 0x06c(%0)\n\t" + "sb\t$0, 0x070(%0)\n\t" + "sb\t$0, 0x074(%0)\n\t" + "sb\t$0, 0x078(%0)\n\t" + "sb\t$0, 0x07c(%0)\n\t" + : : "r" (p) ); + p += 0x080; + } + + write_c0_status(flags); +} + +static inline unsigned long get_phys_page (unsigned long addr, + struct mm_struct *mm) +{ + pgd_t *pgd; + pmd_t *pmd; + pte_t *pte; + unsigned long physpage; + + pgd = pgd_offset(mm, addr); + pmd = pmd_offset(pgd, addr); + pte = pte_offset(pmd, addr); + + if ((physpage = pte_val(*pte)) & _PAGE_VALID) + return KSEG0ADDR(physpage & PAGE_MASK); + + return 0; +} + +static inline void r3k_flush_cache_all(void) +{ +} + +static inline void r3k___flush_cache_all(void) +{ + r3k_flush_icache_range(KSEG0, KSEG0 + icache_size); +} + +static void r3k_flush_cache_mm(struct mm_struct *mm) +{ +} + +static void r3k_flush_cache_range(struct vm_area_struct *vma, + unsigned long start, unsigned long end) +{ +} + +static void r3k_flush_cache_page(struct vm_area_struct *vma, + unsigned long page) +{ +} + +static void r3k_flush_data_cache_page(unsigned long addr) +{ +} + +static void r3k_flush_icache_page(struct vm_area_struct *vma, struct page *page) +{ + struct mm_struct *mm = vma->vm_mm; + unsigned long physpage; + + if (cpu_context(smp_processor_id(), mm) == 0) + return; + + if (!(vma->vm_flags & VM_EXEC)) + return; + +#ifdef DEBUG_CACHE + printk("cpage[%d,%08lx]", cpu_context(smp_processor_id(), mm), page); +#endif + + physpage = (unsigned long) page_address(page); + if (physpage) + r3k_flush_icache_range(physpage, physpage + PAGE_SIZE); +} + +static void r3k_flush_cache_sigtramp(unsigned long addr) +{ + unsigned long flags; + +#ifdef DEBUG_CACHE + printk("csigtramp[%08lx]", addr); +#endif + + flags = read_c0_status(); + + write_c0_status(flags&~ST0_IEC); + + /* Fill the TLB to avoid an exception with caches isolated. */ + asm ( "lw\t$0, 0x000(%0)\n\t" + "lw\t$0, 0x004(%0)\n\t" + : : "r" (addr) ); + + write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC); + + asm ( "sb\t$0, 0x000(%0)\n\t" + "sb\t$0, 0x004(%0)\n\t" + : : "r" (addr) ); + + write_c0_status(flags); +} + +static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size) +{ + iob(); + r3k_flush_dcache_range(start, start + size); +} + +void __init ld_mmu_r23000(void) +{ + _clear_page = r3k_clear_page; + _copy_page = r3k_copy_page; + + r3k_probe_cache(); + + flush_cache_all = r3k_flush_cache_all; + __flush_cache_all = r3k___flush_cache_all; + flush_cache_mm = r3k_flush_cache_mm; + flush_cache_range = r3k_flush_cache_range; + flush_cache_page = r3k_flush_cache_page; + flush_icache_page = r3k_flush_icache_page; + flush_icache_range = r3k_flush_icache_range; + + flush_cache_sigtramp = r3k_flush_cache_sigtramp; + flush_data_cache_page = r3k_flush_data_cache_page; + + _dma_cache_wback_inv = r3k_dma_cache_wback_inv; + + printk("Primary instruction cache %ldkB, linesize %ld bytes.\n", + icache_size >> 10, icache_lsize); + printk("Primary data cache %ldkB, linesize %ld bytes.\n", + dcache_size >> 10, dcache_lsize); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/c-r4k.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,1161 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Primary cache parameters. */ +static unsigned long icache_size, dcache_size, scache_size; +unsigned long icache_way_size, dcache_way_size, scache_way_size; +static unsigned long scache_size; + +#include +#include + +extern void andes_clear_page(void * page); +extern void r4k_clear_page32_d16(void * page); +extern void r4k_clear_page32_d32(void * page); +extern void r4k_clear_page_d16(void * page); +extern void r4k_clear_page_d32(void * page); +extern void r4k_clear_page_r4600_v1(void * page); +extern void r4k_clear_page_r4600_v2(void * page); +extern void r4k_clear_page_s16(void * page); +extern void r4k_clear_page_s32(void * page); +extern void r4k_clear_page_s64(void * page); +extern void r4k_clear_page_s128(void * page); +extern void andes_copy_page(void * to, void * from); +extern void r4k_copy_page_d16(void * to, void * from); +extern void r4k_copy_page_d32(void * to, void * from); +extern void r4k_copy_page_r4600_v1(void * to, void * from); +extern void r4k_copy_page_r4600_v2(void * to, void * from); +extern void r4k_copy_page_s16(void * to, void * from); +extern void r4k_copy_page_s32(void * to, void * from); +extern void r4k_copy_page_s64(void * to, void * from); +extern void r4k_copy_page_s128(void * to, void * from); + +/* + * Dummy cache handling routines for machines without boardcaches + */ +static void no_sc_noop(void) {} + +static struct bcache_ops no_sc_ops = { + .bc_enable = (void *)no_sc_noop, + .bc_disable = (void *)no_sc_noop, + .bc_wback_inv = (void *)no_sc_noop, + .bc_inv = (void *)no_sc_noop +}; + +struct bcache_ops *bcops = &no_sc_ops; + +#define R4600_HIT_CACHEOP_WAR_IMPL \ +do { \ + if (R4600_V2_HIT_CACHEOP_WAR && \ + (read_c0_prid() & 0xfff0) == 0x2020) { /* R4600 V2.0 */\ + *(volatile unsigned long *)KSEG1; \ + } \ + if (R4600_V1_HIT_CACHEOP_WAR) \ + __asm__ __volatile__("nop;nop;nop;nop"); \ +} while (0) + +static void r4k_blast_dcache_page(unsigned long addr) +{ + static void *l = &&init; + unsigned long dc_lsize; + + goto *l; + +dc_16: + blast_dcache16_page(addr); + return; + +dc_32: + R4600_HIT_CACHEOP_WAR_IMPL; + blast_dcache32_page(addr); + return; + +init: + dc_lsize = current_cpu_data.dcache.linesz; + + if (dc_lsize == 16) + l = &&dc_16; + else if (dc_lsize == 32) + l = &&dc_32; + goto *l; +} + +static void r4k_blast_dcache_page_indexed(unsigned long addr) +{ + static void *l = &&init; + unsigned long dc_lsize; + + goto *l; + +dc_16: + blast_dcache16_page_indexed(addr); + return; + +dc_32: + blast_dcache32_page_indexed(addr); + return; + +init: + dc_lsize = current_cpu_data.dcache.linesz; + + if (dc_lsize == 16) + l = &&dc_16; + else if (dc_lsize == 32) + l = &&dc_32; + goto *l; +} + +static void r4k_blast_dcache(void) +{ + static void *l = &&init; + unsigned long dc_lsize; + + goto *l; + +dc_16: + blast_dcache16(); + return; + +dc_32: + blast_dcache32(); + return; + +init: + dc_lsize = current_cpu_data.dcache.linesz; + + if (dc_lsize == 16) + l = &&dc_16; + else if (dc_lsize == 32) + l = &&dc_32; + goto *l; +} + +static void r4k_blast_icache_page(unsigned long addr) +{ + unsigned long ic_lsize = current_cpu_data.icache.linesz; + static void *l = &&init; + + goto *l; + +ic_16: + blast_icache16_page(addr); + return; + +ic_32: + blast_icache32_page(addr); + return; + +ic_64: + blast_icache64_page(addr); + return; + +init: + if (ic_lsize == 16) + l = &&ic_16; + else if (ic_lsize == 32) + l = &&ic_32; + else if (ic_lsize == 64) + l = &&ic_64; + goto *l; +} + +static void r4k_blast_icache_page_indexed(unsigned long addr) +{ + unsigned long ic_lsize = current_cpu_data.icache.linesz; + static void *l = &&init; + + goto *l; + +ic_16: + blast_icache16_page_indexed(addr); + return; + +ic_32: + blast_icache32_page_indexed(addr); + return; + +ic_64: + blast_icache64_page_indexed(addr); + return; + +init: + if (ic_lsize == 16) + l = &&ic_16; + else if (ic_lsize == 32) + l = &&ic_32; + else if (ic_lsize == 64) + l = &&ic_64; + goto *l; +} + +static void r4k_blast_icache(void) +{ + unsigned long ic_lsize = current_cpu_data.icache.linesz; + static void *l = &&init; + + goto *l; + +ic_16: + blast_icache16(); + return; + +ic_32: + blast_icache32(); + return; + +ic_64: + blast_icache64(); + return; + +init: + if (ic_lsize == 16) + l = &&ic_16; + else if (ic_lsize == 32) + l = &&ic_32; + else if (ic_lsize == 64) + l = &&ic_64; + goto *l; +} + +static void r4k_blast_scache_page(unsigned long addr) +{ + unsigned long sc_lsize = current_cpu_data.scache.linesz; + static void *l = &&init; + + goto *l; + +sc_16: + blast_scache16_page(addr); + return; + +sc_32: + blast_scache32_page(addr); + return; + +sc_64: + blast_scache64_page(addr); + return; + +sc_128: + blast_scache128_page(addr); + return; + +init: + if (sc_lsize == 16) + l = &&sc_16; + else if (sc_lsize == 32) + l = &&sc_32; + else if (sc_lsize == 64) + l = &&sc_64; + else if (sc_lsize == 128) + l = &&sc_128; + goto *l; +} + +static void r4k_blast_scache(void) +{ + unsigned long sc_lsize = current_cpu_data.scache.linesz; + static void *l = &&init; + + goto *l; + +sc_16: + blast_scache16(); + return; + +sc_32: + blast_scache32(); + return; + +sc_64: + blast_scache64(); + return; + +sc_128: + blast_scache128(); + return; + +init: + if (sc_lsize == 16) + l = &&sc_16; + else if (sc_lsize == 32) + l = &&sc_32; + else if (sc_lsize == 64) + l = &&sc_64; + else if (sc_lsize == 128) + l = &&sc_128; + goto *l; +} + +static void r4k_flush_cache_all(void) +{ + if (!cpu_has_dc_aliases) + return; + + r4k_blast_dcache(); + r4k_blast_icache(); +} + +static void r4k___flush_cache_all(void) +{ + r4k_blast_dcache(); + r4k_blast_icache(); + + switch (current_cpu_data.cputype) { + case CPU_R4000SC: + case CPU_R4000MC: + case CPU_R4400SC: + case CPU_R4400MC: + case CPU_R10000: + case CPU_R12000: + r4k_blast_scache(); + } +} + +static void r4k_flush_cache_range(struct vm_area_struct *vma, + unsigned long start, unsigned long end) +{ + if (cpu_context(smp_processor_id(), vma->vm_mm) != 0) { + r4k_blast_dcache(); + if (vma->vm_flags & VM_EXEC) + r4k_blast_icache(); + } +} + +static void r4k_flush_cache_mm(struct mm_struct *mm) +{ + if (!cpu_has_dc_aliases) + return; + + if (!cpu_context(smp_processor_id(), mm)) + return; + + r4k_blast_dcache(); + r4k_blast_icache(); + + /* + * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we + * only flush the primary caches but R10000 and R12000 behave sane ... + */ + if (current_cpu_data.cputype == CPU_R4000SC || + current_cpu_data.cputype == CPU_R4000MC || + current_cpu_data.cputype == CPU_R4400SC || + current_cpu_data.cputype == CPU_R4400MC) + r4k_blast_scache(); +} + +static void r4k_flush_cache_page(struct vm_area_struct *vma, + unsigned long page) +{ + int exec = vma->vm_flags & VM_EXEC; + struct mm_struct *mm = vma->vm_mm; + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + + /* + * If ownes no valid ASID yet, cannot possibly have gotten + * this page into the cache. + */ + if (cpu_context(smp_processor_id(), mm) == 0) + return; + + page &= PAGE_MASK; + pgdp = pgd_offset(mm, page); + pmdp = pmd_offset(pgdp, page); + ptep = pte_offset(pmdp, page); + + /* + * If the page isn't marked valid, the page cannot possibly be + * in the cache. + */ + if (!(pte_val(*ptep) & _PAGE_PRESENT)) + return; + + /* + * Doing flushes for another ASID than the current one is + * too difficult since stupid R4k caches do a TLB translation + * for every cache flush operation. So we do indexed flushes + * in that case, which doesn't overly flush the cache too much. + */ + if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { + if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) + r4k_blast_dcache_page(page); + if (exec) + r4k_blast_icache_page(page); + + return; + } + + /* + * Do indexed flush, too much work to get the (possible) TLB refills + * to work correctly. + */ + page = (KSEG0 + (page & (dcache_size - 1))); + if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) + r4k_blast_dcache_page_indexed(page); + if (exec) { + if (cpu_has_vtag_icache) { + int cpu = smp_processor_id(); + + if (cpu_context(cpu, vma->vm_mm) != 0) + drop_mmu_context(vma->vm_mm, cpu); + } else + r4k_blast_icache_page_indexed(page); + } +} + +static void r4k_flush_data_cache_page(unsigned long addr) +{ + r4k_blast_dcache_page(addr); +} + +static void r4k_flush_icache_range(unsigned long start, unsigned long end) +{ + unsigned long dc_lsize = current_cpu_data.dcache.linesz; + unsigned long addr, aend; + + if (!cpu_has_ic_fills_f_dc) { + if (end - start > dcache_size) + r4k_blast_dcache(); + else { + addr = start & ~(dc_lsize - 1); + aend = (end - 1) & ~(dc_lsize - 1); + + while (1) { + /* Hit_Writeback_Inv_D */ + protected_writeback_dcache_line(addr); + if (addr == aend) + break; + addr += dc_lsize; + } + } + } + + if (end - start > icache_size) + r4k_blast_icache(); + else { + addr = start & ~(dc_lsize - 1); + aend = (end - 1) & ~(dc_lsize - 1); + while (1) { + /* Hit_Invalidate_I */ + protected_flush_icache_line(addr); + if (addr == aend) + break; + addr += dc_lsize; + } + } +} + +/* + * Ok, this seriously sucks. We use them to flush a user page but don't + * know the virtual address, so we have to blast away the whole icache + * which is significantly more expensive than the real thing. Otoh we at + * least know the kernel address of the page so we can flush it + * selectivly. + */ +static void r4k_flush_icache_page(struct vm_area_struct *vma, + struct page *page) +{ + /* + * If there's no context yet, or the page isn't executable, no icache + * flush is needed. + */ + if (!(vma->vm_flags & VM_EXEC)) + return; + + /* + * Tricky ... Because we don't know the virtual address we've got the + * choice of either invalidating the entire primary and secondary + * caches or invalidating the secondary caches also. With the subset + * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the + * secondary cache will result in any entries in the primary caches + * also getting invalidated which hopefully is a bit more economical. + */ + if (cpu_has_subset_pcaches) { + unsigned long addr = (unsigned long) page_address(page); + r4k_blast_scache_page(addr); + + return; + } + + if (!cpu_has_ic_fills_f_dc) { + unsigned long addr = (unsigned long) page_address(page); + r4k_blast_dcache_page(addr); + } + + /* + * We're not sure of the virtual address(es) involved here, so + * we have to flush the entire I-cache. + */ + if (cpu_has_vtag_icache) { + int cpu = smp_processor_id(); + + if (cpu_context(cpu, vma->vm_mm) != 0) + drop_mmu_context(vma->vm_mm, cpu); + } else + r4k_blast_icache(); +} + +#ifdef CONFIG_NONCOHERENT_IO + +static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + + if (cpu_has_subset_pcaches) { + unsigned long sc_lsize = current_cpu_data.scache.linesz; + + if (size >= scache_size) { + r4k_blast_scache(); + return; + } + + a = addr & ~(sc_lsize - 1); + end = (addr + size - 1) & ~(sc_lsize - 1); + while (1) { + flush_scache_line(a); /* Hit_Writeback_Inv_SD */ + if (a == end) + break; + a += sc_lsize; + } + return; + } + + /* + * Either no secondary cache or the available caches don't have the + * subset property so we have to flush the primary caches + * explicitly + */ + if (size >= dcache_size) { + r4k_blast_dcache(); + } else { + unsigned long dc_lsize = current_cpu_data.dcache.linesz; + + R4600_HIT_CACHEOP_WAR_IMPL; + a = addr & ~(dc_lsize - 1); + end = (addr + size - 1) & ~(dc_lsize - 1); + while (1) { + flush_dcache_line(a); /* Hit_Writeback_Inv_D */ + if (a == end) + break; + a += dc_lsize; + } + } + + bc_wback_inv(addr, size); +} + +static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + + if (cpu_has_subset_pcaches) { + unsigned long sc_lsize = current_cpu_data.scache.linesz; + + if (size >= scache_size) { + r4k_blast_scache(); + return; + } + + a = addr & ~(sc_lsize - 1); + end = (addr + size - 1) & ~(sc_lsize - 1); + while (1) { + flush_scache_line(a); /* Hit_Writeback_Inv_SD */ + if (a == end) + break; + a += sc_lsize; + } + return; + } + + if (size >= dcache_size) { + r4k_blast_dcache(); + } else { + unsigned long dc_lsize = current_cpu_data.dcache.linesz; + + R4600_HIT_CACHEOP_WAR_IMPL; + a = addr & ~(dc_lsize - 1); + end = (addr + size - 1) & ~(dc_lsize - 1); + while (1) { + flush_dcache_line(a); /* Hit_Writeback_Inv_D */ + if (a == end) + break; + a += dc_lsize; + } + } + + bc_inv(addr, size); +} +#endif /* CONFIG_NONCOHERENT_IO */ + +/* + * While we're protected against bad userland addresses we don't care + * very much about what happens in that case. Usually a segmentation + * fault will dump the process later on anyway ... + */ +static void r4k_flush_cache_sigtramp(unsigned long addr) +{ + unsigned long ic_lsize = current_cpu_data.icache.linesz; + unsigned long dc_lsize = current_cpu_data.dcache.linesz; + + R4600_HIT_CACHEOP_WAR_IMPL; + protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); + protected_flush_icache_line(addr & ~(ic_lsize - 1)); +} + +static void r4k_flush_icache_all(void) +{ + if (cpu_has_vtag_icache) + r4k_blast_icache(); +} + +static inline void rm7k_erratum31(void) +{ + const unsigned long ic_lsize = 32; + unsigned long addr; + + /* RM7000 erratum #31. The icache is screwed at startup. */ + write_c0_taglo(0); + write_c0_taghi(0); + + for (addr = KSEG0; addr <= KSEG0 + 4096; addr += ic_lsize) { + __asm__ __volatile__ ( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache\t%1, 0(%0)\n\t" + "cache\t%1, 0x1000(%0)\n\t" + "cache\t%1, 0x2000(%0)\n\t" + "cache\t%1, 0x3000(%0)\n\t" + "cache\t%2, 0(%0)\n\t" + "cache\t%2, 0x1000(%0)\n\t" + "cache\t%2, 0x2000(%0)\n\t" + "cache\t%2, 0x3000(%0)\n\t" + "cache\t%1, 0(%0)\n\t" + "cache\t%1, 0x1000(%0)\n\t" + "cache\t%1, 0x2000(%0)\n\t" + "cache\t%1, 0x3000(%0)\n\t" + ".set\tmips0\n\t" + ".set\treorder\n\t" + : + : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); + } +} + +static char *way_string[] = { NULL, "direct mapped", "2-way", "3-way", "4-way", + "5-way", "6-way", "7-way", "8-way" +}; + +static void __init probe_pcache(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int config = read_c0_config(); + unsigned int prid = read_c0_prid(); + unsigned long config1; + unsigned int lsize; + + switch (current_cpu_data.cputype) { + case CPU_R4600: /* QED style two way caches? */ + case CPU_R4700: + case CPU_R5000: + case CPU_NEVADA: + icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + c->icache.ways = 2; + c->icache.waybit = ffs(icache_size/2) - 1; + + dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + c->dcache.ways = 2; + c->dcache.waybit= ffs(dcache_size/2) - 1; + break; + + case CPU_R5432: + case CPU_R5500: + icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + c->icache.ways = 2; + c->icache.waybit= 0; + + dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + c->dcache.ways = 2; + c->dcache.waybit = 0; + break; + + case CPU_TX49XX: + icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + c->icache.ways = 4; + c->icache.waybit= 0; + + dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + c->dcache.ways = 4; + c->dcache.waybit = 0; + break; + + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: + case CPU_R4400PC: + case CPU_R4400SC: + case CPU_R4400MC: + icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + c->icache.ways = 1; + c->icache.waybit = 0; /* doesn't matter */ + + dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + c->dcache.ways = 1; + c->dcache.waybit = 0; /* does not matter */ + break; + + case CPU_R10000: + case CPU_R12000: + icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); + c->icache.linesz = 64; + c->icache.ways = 2; + c->icache.waybit = 0; + + dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); + c->dcache.linesz = 32; + c->dcache.ways = 2; + c->dcache.waybit = 0; + break; + + case CPU_VR4131: + icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + c->icache.ways = 2; + c->icache.waybit = ffs(icache_size/2) - 1; + + dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + c->dcache.ways = 2; + c->dcache.waybit = ffs(dcache_size/2) - 1; + break; + + case CPU_VR41XX: + case CPU_VR4111: + case CPU_VR4121: + case CPU_VR4122: + case CPU_VR4181: + case CPU_VR4181A: + icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + c->icache.ways = 1; + c->icache.waybit = 0; /* doesn't matter */ + + dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + c->dcache.ways = 1; + c->dcache.waybit = 0; /* does not matter */ + break; + + case CPU_RM7000: + rm7k_erratum31(); + + icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); + c->icache.linesz = 16 << ((config & CONF_IB) >> 5); + c->icache.ways = 4; + c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; + + dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); + c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); + c->dcache.ways = 4; + c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1; + break; + + default: + if (!(config & MIPS_CONF_M)) + panic("Don't know how to probe P-caches on this cpu."); + + /* + * So we seem to be a MIPS32 or MIPS64 CPU + * So let's probe the I-cache ... + */ + config1 = read_c0_config1(); + + if ((lsize = ((config1 >> 19) & 7))) + c->icache.linesz = 2 << lsize; + else + c->icache.linesz = lsize; + c->icache.sets = 64 << ((config1 >> 22) & 7); + c->icache.ways = 1 + ((config1 >> 16) & 7); + + icache_size = c->icache.sets * + c->icache.ways * + c->icache.linesz; + c->icache.waybit = ffs(icache_size/c->icache.ways) - 1; + + /* + * Now probe the MIPS32 / MIPS64 data cache. + */ + c->dcache.flags = 0; + + if ((lsize = ((config1 >> 10) & 7))) + c->dcache.linesz = 2 << lsize; + else + c->dcache.linesz= lsize; + c->dcache.sets = 64 << ((config1 >> 13) & 7); + c->dcache.ways = 1 + ((config1 >> 7) & 7); + + dcache_size = c->dcache.sets * + c->dcache.ways * + c->dcache.linesz; + c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1; + break; + } + + /* + * Processor configuration sanity check for the R4000SC erratum + * #5. With page sizes larger than 32kB there is no possibility + * to get a VCE exception anymore so we don't care about this + * misconfiguration. The case is rather theoretical anyway; + * presumably no vendor is shipping his hardware in the "bad" + * configuration. + */ + if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 && + !(config & CONF_SC) && c->icache.linesz != 16 && + PAGE_SIZE <= 0x8000) + panic("Improper R4000SC processor configuration detected"); + + /* compute a couple of other cache variables */ + icache_way_size = icache_size / c->icache.ways; + dcache_way_size = dcache_size / c->dcache.ways; + + c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways); + c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways); + + /* + * R10000 and R12000 P-caches are odd in a positive way. They're 32kB + * 2-way virtually indexed so normally would suffer from aliases. So + * normally they'd suffer from aliases but magic in the hardware deals + * with that for us so we don't need to take care ourselves. + */ + if (current_cpu_data.cputype != CPU_R10000 && + current_cpu_data.cputype != CPU_R12000) + if (dcache_way_size > PAGE_SIZE) + c->dcache.flags |= MIPS_CACHE_ALIASES; + + if (config & 0x8) /* VI bit */ + c->icache.flags |= MIPS_CACHE_VTAG; + + switch (c->cputype) { + case CPU_20KC: + /* + * Some older 20Kc chips doesn't have the 'VI' bit in + * the config register. + */ + c->icache.flags |= MIPS_CACHE_VTAG; + break; + + case CPU_AU1500: + c->icache.flags |= MIPS_CACHE_IC_F_DC; + break; + } + + printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", + icache_size >> 10, + cpu_has_vtag_icache ? "virtually tagged" : "physically tagged", + way_string[c->icache.ways], c->icache.linesz); + + printk("Primary data cache %ldkB %s, linesize %d bytes.\n", + dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz); +} + +/* + * If you even _breathe_ on this function, look at the gcc output and make sure + * it does not pop things on and off the stack for the cache sizing loop that + * executes in KSEG1 space or else you will crash and burn badly. You have + * been warned. + */ +static int __init probe_scache(void) +{ + extern unsigned long stext; + unsigned long flags, addr, begin, end, pow2; + unsigned int config = read_c0_config(); + struct cpuinfo_mips *c = ¤t_cpu_data; + int tmp; + + if (config & CONF_SC) + return 0; + + begin = (unsigned long) &stext; + begin &= ~((4 * 1024 * 1024) - 1); + end = begin + (4 * 1024 * 1024); + + /* + * This is such a bitch, you'd think they would make it easy to do + * this. Away you daemons of stupidity! + */ + local_irq_save(flags); + + /* Fill each size-multiple cache line with a valid tag. */ + pow2 = (64 * 1024); + for (addr = begin; addr < end; addr = (begin + pow2)) { + unsigned long *p = (unsigned long *) addr; + __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ + pow2 <<= 1; + } + + /* Load first line with zero (therefore invalid) tag. */ + write_c0_taglo(0); + write_c0_taghi(0); + __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ + cache_op(Index_Store_Tag_I, begin); + cache_op(Index_Store_Tag_D, begin); + cache_op(Index_Store_Tag_SD, begin); + + /* Now search for the wrap around point. */ + pow2 = (128 * 1024); + tmp = 0; + for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { + cache_op(Index_Load_Tag_SD, addr); + __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ + if (!read_c0_taglo()) + break; + pow2 <<= 1; + } + local_irq_restore(flags); + addr -= begin; + + c = ¤t_cpu_data; + scache_size = addr; + c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); + c->scache.ways = 1; + c->dcache.waybit = 0; /* does not matter */ + + return 1; +} + +static void __init setup_noscache_funcs(void) +{ + unsigned int prid; + + switch (current_cpu_data.dcache.linesz) { + case 16: + if (cpu_has_64bits) + _clear_page = r4k_clear_page_d16; + else + _clear_page = r4k_clear_page32_d16; + _copy_page = r4k_copy_page_d16; + + break; + case 32: + prid = read_c0_prid() & 0xfff0; + if (prid == 0x2010) { /* R4600 V1.7 */ + _clear_page = r4k_clear_page_r4600_v1; + _copy_page = r4k_copy_page_r4600_v1; + } else if (prid == 0x2020) { /* R4600 V2.0 */ + _clear_page = r4k_clear_page_r4600_v2; + _copy_page = r4k_copy_page_r4600_v2; + } else { + if (cpu_has_64bits) + _clear_page = r4k_clear_page_d32; + else + _clear_page = r4k_clear_page32_d32; + _copy_page = r4k_copy_page_d32; + } + break; + } +} + +static void __init setup_scache_funcs(void) +{ + if (current_cpu_data.dcache.linesz > current_cpu_data.scache.linesz) + panic("Invalid primary cache configuration detected"); + + if (current_cpu_data.cputype == CPU_R10000 || + current_cpu_data.cputype == CPU_R12000) { + _clear_page = andes_clear_page; + _copy_page = andes_copy_page; + return; + } + + switch (current_cpu_data.scache.linesz) { + case 16: + _clear_page = r4k_clear_page_s16; + _copy_page = r4k_copy_page_s16; + break; + case 32: + _clear_page = r4k_clear_page_s32; + _copy_page = r4k_copy_page_s32; + break; + case 64: + _clear_page = r4k_clear_page_s64; + _copy_page = r4k_copy_page_s64; + break; + case 128: + _clear_page = r4k_clear_page_s128; + _copy_page = r4k_copy_page_s128; + break; + } +} + +typedef int (*probe_func_t)(unsigned long); +extern int r5k_sc_init(void); +extern int rm7k_sc_init(void); + +static void __init setup_scache(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int config = read_c0_config(); + probe_func_t probe_scache_kseg1; + int sc_present = 0; + + /* + * Do the probing thing on R4000SC and R4400SC processors. Other + * processors don't have a S-cache that would be relevant to the + * Linux memory managment. + */ + switch (current_cpu_data.cputype) { + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: + case CPU_R4400PC: + case CPU_R4400SC: + case CPU_R4400MC: + probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache)); + sc_present = probe_scache_kseg1(config); + break; + + case CPU_R10000: + case CPU_R12000: + scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); + c->scache.linesz = 64 << ((config >> 13) & 1); + c->scache.ways = 2; + c->scache.waybit= 0; + sc_present = 1; + break; + + case CPU_R5000: + case CPU_NEVADA: + setup_noscache_funcs(); +#ifdef CONFIG_R5000_CPU_SCACHE + r5k_sc_init(); +#endif + return; + + case CPU_RM7000: + setup_noscache_funcs(); +#ifdef CONFIG_RM7000_CPU_SCACHE + rm7k_sc_init(); +#endif + return; + + default: + sc_present = 0; + } + + if (!sc_present) { + setup_noscache_funcs(); + return; + } + + if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32 || + current_cpu_data.isa_level == MIPS_CPU_ISA_M64) && + !(current_cpu_data.scache.flags & MIPS_CACHE_NOT_PRESENT)) + panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); + + printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", + scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); + + current_cpu_data.options |= MIPS_CPU_SUBSET_CACHES; + setup_scache_funcs(); +} + +static inline void coherency_setup(void) +{ + change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); + + /* + * c0_status.cu=0 specifies that updates by the sc instruction use + * the coherency mode specified by the TLB; 1 means cachable + * coherent update on write will be used. Not all processors have + * this bit and; some wire it to zero, others like Toshiba had the + * silly idea of putting something else there ... + */ + switch (current_cpu_data.cputype) { + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: + case CPU_R4400PC: + case CPU_R4400SC: + case CPU_R4400MC: + clear_c0_config(CONF_CU); + break; + } + +} + +void __init ld_mmu_r4xx0(void) +{ + extern char except_vec2_generic; + + /* Default cache error handler for R4000 and R5000 family */ + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80); + memcpy((void *)(KSEG1 + 0x100), &except_vec2_generic, 0x80); + + probe_pcache(); + setup_scache(); + coherency_setup(); + + if (current_cpu_data.dcache.sets * + current_cpu_data.dcache.ways > PAGE_SIZE) + current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES; + + /* + * Some MIPS32 and MIPS64 processors have physically indexed caches. + * This code supports virtually indexed processors and will be + * unnecessarily unefficient on physically indexed processors. + */ + shm_align_mask = max_t(unsigned long, + current_cpu_data.dcache.sets * current_cpu_data.dcache.linesz - 1, + PAGE_SIZE - 1); + + flush_cache_all = r4k_flush_cache_all; + __flush_cache_all = r4k___flush_cache_all; + flush_cache_mm = r4k_flush_cache_mm; + flush_cache_page = r4k_flush_cache_page; + flush_icache_page = r4k_flush_icache_page; + flush_cache_range = r4k_flush_cache_range; + + flush_cache_sigtramp = r4k_flush_cache_sigtramp; + flush_icache_all = r4k_flush_icache_all; + flush_data_cache_page = r4k_flush_data_cache_page; + flush_icache_range = r4k_flush_icache_range; + +#ifdef CONFIG_NONCOHERENT_IO + _dma_cache_wback_inv = r4k_dma_cache_wback_inv; + _dma_cache_wback = r4k_dma_cache_wback_inv; + _dma_cache_inv = r4k_dma_cache_inv; +#endif + + __flush_cache_all(); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/c-sb1.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,611 @@ +/* + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include + +extern void sb1_clear_page(void * page); +extern void sb1_copy_page(void * to, void * from); + +/* These are probed at ld_mmu time */ +static unsigned long icache_size; +static unsigned long dcache_size; + +static unsigned long icache_line_size; +static unsigned long dcache_line_size; + +static unsigned int icache_index_mask; +static unsigned int dcache_index_mask; + +static unsigned long icache_assoc; +static unsigned long dcache_assoc; + +static unsigned int icache_sets; +static unsigned int dcache_sets; + +static unsigned int icache_range_cutoff; +static unsigned int dcache_range_cutoff; + +void pgd_init(unsigned long page) +{ + unsigned long *p = (unsigned long *) page; + int i; + + for (i = 0; i < USER_PTRS_PER_PGD; i+=8) { + p[i + 0] = (unsigned long) invalid_pte_table; + p[i + 1] = (unsigned long) invalid_pte_table; + p[i + 2] = (unsigned long) invalid_pte_table; + p[i + 3] = (unsigned long) invalid_pte_table; + p[i + 4] = (unsigned long) invalid_pte_table; + p[i + 5] = (unsigned long) invalid_pte_table; + p[i + 6] = (unsigned long) invalid_pte_table; + p[i + 7] = (unsigned long) invalid_pte_table; + } +} + +/* + * The dcache is fully coherent to the system, with one + * big caveat: the instruction stream. In other words, + * if we miss in the icache, and have dirty data in the + * L1 dcache, then we'll go out to memory (or the L2) and + * get the not-as-recent data. + * + * So the only time we have to flush the dcache is when + * we're flushing the icache. Since the L2 is fully + * coherent to everything, including I/O, we never have + * to flush it + */ + +/* + * Writeback and invalidate the entire dcache + */ +static inline void __sb1_writeback_inv_dcache_all(void) +{ + __asm__ __volatile__ ( + ".set push \n" + ".set noreorder \n" + ".set noat \n" + ".set mips4 \n" + " move $1, $0 \n" /* Start at index 0 */ + "1: cache %2, 0($1) \n" /* Invalidate this index */ + " cache %2, (1<<13)($1)\n" /* Invalidate this index */ + " cache %2, (2<<13)($1)\n" /* Invalidate this index */ + " cache %2, (3<<13)($1)\n" /* Invalidate this index */ + " addiu %1, %1, -1 \n" /* Decrement loop count */ + " bnez %1, 1b \n" /* loop test */ + " addu $1, $1, %0 \n" /* Next address */ + ".set pop \n" + : + : "r" (dcache_line_size), "r" (dcache_sets), + "i" (Index_Writeback_Inv_D)); +} + +/* + * Writeback and invalidate a range of the dcache. The addresses are + * virtual, and since we're using index ops and bit 12 is part of both + * the virtual frame and physical index, we have to clear both sets + * (bit 12 set and cleared). + */ +static inline void __sb1_writeback_inv_dcache_range(unsigned long start, + unsigned long end) +{ + __asm__ __volatile__ ( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips4 \n" + " and $1, %0, %3 \n" /* mask non-index bits */ + "1: cache %4, (0<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (1<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (2<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (3<<13)($1) \n" /* Index-WB-inval this address */ + " xori $1, $1, 1<<12 \n" /* flip bit 12 (va/pa alias) */ + " cache %4, (0<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (1<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (2<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (3<<13)($1) \n" /* Index-WB-inval this address */ + " addu %0, %0, %2 \n" /* next line */ + " bne %0, %1, 1b \n" /* loop test */ + " and $1, %0, %3 \n" /* mask non-index bits */ + " sync \n" + " .set pop \n" + : + : "r" (start & ~(dcache_line_size - 1)), + "r" ((end + dcache_line_size - 1) & ~(dcache_line_size - 1)), + "r" (dcache_line_size), + "r" (dcache_index_mask), + "i" (Index_Writeback_Inv_D)); +} + +/* + * Writeback and invalidate a range of the dcache. With physical + * addresseses, we don't have to worry about possible bit 12 aliasing. + * XXXKW is it worth turning on KX and using hit ops with xkphys? + */ +static inline void __sb1_writeback_inv_dcache_phys_range(unsigned long start, + unsigned long end) +{ + __asm__ __volatile__ ( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips4 \n" + " and $1, %0, %3 \n" /* mask non-index bits */ + "1: cache %4, (0<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (1<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (2<<13)($1) \n" /* Index-WB-inval this address */ + " cache %4, (3<<13)($1) \n" /* Index-WB-inval this address */ + " addu %0, %0, %2 \n" /* next line */ + " bne %0, %1, 1b \n" /* loop test */ + " and $1, %0, %3 \n" /* mask non-index bits */ + " sync \n" + " .set pop \n" + : + : "r" (start & ~(dcache_line_size - 1)), + "r" ((end + dcache_line_size - 1) & ~(dcache_line_size - 1)), + "r" (dcache_line_size), + "r" (dcache_index_mask), + "i" (Index_Writeback_Inv_D)); +} + + +/* + * Invalidate the entire icache + */ +static inline void __sb1_flush_icache_all(void) +{ + __asm__ __volatile__ ( + ".set push \n" + ".set noreorder \n" + ".set noat \n" + ".set mips4 \n" + " move $1, $0 \n" /* Start at index 0 */ + "1: cache %2, 0($1) \n" /* Invalidate this index */ + " cache %2, (1<<13)($1)\n" /* Invalidate this index */ + " cache %2, (2<<13)($1)\n" /* Invalidate this index */ + " cache %2, (3<<13)($1)\n" /* Invalidate this index */ + " addiu %1, %1, -1 \n" /* Decrement loop count */ + " bnez %1, 1b \n" /* loop test */ + " addu $1, $1, %0 \n" /* Next address */ + " bnezl $0, 2f \n" /* Force mispredict */ + " nop \n" + "2: sync \n" + ".set pop \n" + : + : "r" (icache_line_size), "r" (icache_sets), + "i" (Index_Invalidate_I)); +} + +/* + * Flush the icache for a given physical page. Need to writeback the + * dcache first, then invalidate the icache. If the page isn't + * executable, nothing is required. + */ +static void local_sb1_flush_cache_page(struct vm_area_struct *vma, + unsigned long addr) +{ + int cpu = smp_processor_id(); + +#ifndef CONFIG_SMP + if (!(vma->vm_flags & VM_EXEC)) + return; +#endif + + __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE); + + /* + * Bumping the ASID is probably cheaper than the flush ... + */ + if (cpu_context(cpu, vma->vm_mm) != 0) + drop_mmu_context(vma->vm_mm, cpu); +} + +#ifdef CONFIG_SMP +struct flush_cache_page_args { + struct vm_area_struct *vma; + unsigned long addr; +}; + +static void sb1_flush_cache_page_ipi(void *info) +{ + struct flush_cache_page_args *args = info; + + local_sb1_flush_cache_page(args->vma, args->addr); +} + +/* Dirty dcache could be on another CPU, so do the IPIs */ +static void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr) +{ + struct flush_cache_page_args args; + + if (!(vma->vm_flags & VM_EXEC)) + return; + + args.vma = vma; + args.addr = addr; + on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1); +} +#else +void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr); +asm("sb1_flush_cache_page = local_sb1_flush_cache_page"); +#endif + +/* + * Invalidate a range of the icache. The addresses are virtual, and + * the cache is virtually indexed and tagged. However, we don't + * necessarily have the right ASID context, so use index ops instead + * of hit ops. + */ +static inline void __sb1_flush_icache_range(unsigned long start, + unsigned long end) +{ + __asm__ __volatile__ ( + ".set push \n" + ".set noreorder \n" + ".set noat \n" + ".set mips4 \n" + " and $1, %0, %3 \n" /* mask non-index bits */ + "1: cache %4, (0<<13)($1) \n" /* Index-inval this address */ + " cache %4, (1<<13)($1) \n" /* Index-inval this address */ + " cache %4, (2<<13)($1) \n" /* Index-inval this address */ + " cache %4, (3<<13)($1) \n" /* Index-inval this address */ + " addu %0, %0, %2 \n" /* next line */ + " bne %0, %1, 1b \n" /* loop test */ + " and $1, %0, %3 \n" /* mask non-index bits */ + " bnezl $0, 2f \n" /* Force mispredict */ + " nop \n" + "2: sync \n" + ".set pop \n" + : + : "r" (start & ~(icache_line_size - 1)), + "r" ((end + icache_line_size - 1) & ~(icache_line_size - 1)), + "r" (icache_line_size), + "r" (icache_index_mask), + "i" (Index_Invalidate_I)); +} + + +/* + * Invalidate all caches on this CPU + */ +static void local_sb1___flush_cache_all(void) +{ + __sb1_writeback_inv_dcache_all(); + __sb1_flush_icache_all(); +} + +#ifdef CONFIG_SMP +extern void sb1___flush_cache_all_ipi(void *ignored); +asm("sb1___flush_cache_all_ipi = local_sb1___flush_cache_all"); + +static void sb1___flush_cache_all(void) +{ + on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1); +} +#else +extern void sb1___flush_cache_all(void); +asm("sb1___flush_cache_all = local_sb1___flush_cache_all"); +#endif + +/* + * When flushing a range in the icache, we have to first writeback + * the dcache for the same range, so new ifetches will see any + * data that was dirty in the dcache. + * + * The start/end arguments are Kseg addresses (possibly mapped Kseg). + */ + +static void local_sb1_flush_icache_range(unsigned long start, + unsigned long end) +{ + /* Just wb-inv the whole dcache if the range is big enough */ + if ((end - start) > dcache_range_cutoff) + __sb1_writeback_inv_dcache_all(); + else + __sb1_writeback_inv_dcache_range(start, end); + + /* Just flush the whole icache if the range is big enough */ + if ((end - start) > icache_range_cutoff) + __sb1_flush_icache_all(); + else + __sb1_flush_icache_range(start, end); +} + +#ifdef CONFIG_SMP +struct flush_icache_range_args { + unsigned long start; + unsigned long end; +}; + +static void sb1_flush_icache_range_ipi(void *info) +{ + struct flush_icache_range_args *args = info; + + local_sb1_flush_icache_range(args->start, args->end); +} + +void sb1_flush_icache_range(unsigned long start, unsigned long end) +{ + struct flush_icache_range_args args; + + args.start = start; + args.end = end; + on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1); +} +#else +void sb1_flush_icache_range(unsigned long start, unsigned long end); +asm("sb1_flush_icache_range = local_sb1_flush_icache_range"); +#endif + +/* + * Flush the icache for a given physical page. Need to writeback the + * dcache first, then invalidate the icache. If the page isn't + * executable, nothing is required. + */ +static void local_sb1_flush_icache_page(struct vm_area_struct *vma, + struct page *page) +{ + unsigned long start; + int cpu = smp_processor_id(); + +#ifndef CONFIG_SMP + if (!(vma->vm_flags & VM_EXEC)) + return; +#endif + + /* Need to writeback any dirty data for that page, we have the PA */ + start = (unsigned long)(page-mem_map) << PAGE_SHIFT; + __sb1_writeback_inv_dcache_phys_range(start, start + PAGE_SIZE); + /* + * If there's a context, bump the ASID (cheaper than a flush, + * since we don't know VAs!) + */ + if (cpu_context(cpu, vma->vm_mm) != 0) { + drop_mmu_context(vma->vm_mm, cpu); + } +} + +#ifdef CONFIG_SMP +struct flush_icache_page_args { + struct vm_area_struct *vma; + struct page *page; +}; + +static void sb1_flush_icache_page_ipi(void *info) +{ + struct flush_icache_page_args *args = info; + local_sb1_flush_icache_page(args->vma, args->page); +} + +/* Dirty dcache could be on another CPU, so do the IPIs */ +static void sb1_flush_icache_page(struct vm_area_struct *vma, + struct page *page) +{ + struct flush_icache_page_args args; + + if (!(vma->vm_flags & VM_EXEC)) + return; + args.vma = vma; + args.page = page; + on_each_cpu(sb1_flush_icache_page_ipi, (void *) &args, 1, 1); +} +#else +void sb1_flush_icache_page(struct vm_area_struct *vma, struct page *page); +asm("sb1_flush_icache_page = local_sb1_flush_icache_page"); +#endif + +/* + * A signal trampoline must fit into a single cacheline. + */ +static void local_sb1_flush_cache_sigtramp(unsigned long addr) +{ + __asm__ __volatile__ ( + " .set push \n" + " .set noreorder \n" + " .set noat \n" + " .set mips4 \n" + " cache %2, (0<<13)(%0) \n" /* Index-inval this address */ + " cache %2, (1<<13)(%0) \n" /* Index-inval this address */ + " cache %2, (2<<13)(%0) \n" /* Index-inval this address */ + " cache %2, (3<<13)(%0) \n" /* Index-inval this address */ + " xori $1, %0, 1<<12 \n" /* Flip index bit 12 */ + " cache %2, (0<<13)($1) \n" /* Index-inval this address */ + " cache %2, (1<<13)($1) \n" /* Index-inval this address */ + " cache %2, (2<<13)($1) \n" /* Index-inval this address */ + " cache %2, (3<<13)($1) \n" /* Index-inval this address */ + " cache %3, (0<<13)(%1) \n" /* Index-inval this address */ + " cache %3, (1<<13)(%1) \n" /* Index-inval this address */ + " cache %3, (2<<13)(%1) \n" /* Index-inval this address */ + " cache %3, (3<<13)(%1) \n" /* Index-inval this address */ + " bnezl $0, 1f \n" /* Force mispredict */ + " nop \n" + "1: \n" + " .set pop \n" + : + : "r" (addr & dcache_index_mask), "r" (addr & icache_index_mask), + "i" (Index_Writeback_Inv_D), "i" (Index_Invalidate_I)); +} + +#ifdef CONFIG_SMP +static void sb1_flush_cache_sigtramp_ipi(void *info) +{ + unsigned long iaddr = (unsigned long) info; + local_sb1_flush_cache_sigtramp(iaddr); +} + +static void sb1_flush_cache_sigtramp(unsigned long addr) +{ + on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1); +} +#else +void sb1_flush_cache_sigtramp(unsigned long addr); +asm("sb1_flush_cache_sigtramp = local_sb1_flush_cache_sigtramp"); +#endif + + +/* + * Anything that just flushes dcache state can be ignored, as we're always + * coherent in dcache space. This is just a dummy function that all the + * nop'ed routines point to + */ +static void sb1_nop(void) +{ +} + +/* + * Cache set values (from the mips64 spec) + * 0 - 64 + * 1 - 128 + * 2 - 256 + * 3 - 512 + * 4 - 1024 + * 5 - 2048 + * 6 - 4096 + * 7 - Reserved + */ + +static unsigned int decode_cache_sets(unsigned int config_field) +{ + if (config_field == 7) { + /* JDCXXX - Find a graceful way to abort. */ + return 0; + } + return (1<<(config_field + 6)); +} + +/* + * Cache line size values (from the mips64 spec) + * 0 - No cache present. + * 1 - 4 bytes + * 2 - 8 bytes + * 3 - 16 bytes + * 4 - 32 bytes + * 5 - 64 bytes + * 6 - 128 bytes + * 7 - Reserved + */ + +static unsigned int decode_cache_line_size(unsigned int config_field) +{ + if (config_field == 0) { + return 0; + } else if (config_field == 7) { + /* JDCXXX - Find a graceful way to abort. */ + return 0; + } + return (1<<(config_field + 1)); +} + +/* + * Relevant bits of the config1 register format (from the MIPS32/MIPS64 specs) + * + * 24:22 Icache sets per way + * 21:19 Icache line size + * 18:16 Icache Associativity + * 15:13 Dcache sets per way + * 12:10 Dcache line size + * 9:7 Dcache Associativity + */ + +static __init void probe_cache_sizes(void) +{ + u32 config1; + + config1 = read_c0_config1(); + icache_line_size = decode_cache_line_size((config1 >> 19) & 0x7); + dcache_line_size = decode_cache_line_size((config1 >> 10) & 0x7); + icache_sets = decode_cache_sets((config1 >> 22) & 0x7); + dcache_sets = decode_cache_sets((config1 >> 13) & 0x7); + icache_assoc = ((config1 >> 16) & 0x7) + 1; + dcache_assoc = ((config1 >> 7) & 0x7) + 1; + icache_size = icache_line_size * icache_sets * icache_assoc; + dcache_size = dcache_line_size * dcache_sets * dcache_assoc; + /* Need to remove non-index bits for index ops */ + icache_index_mask = (icache_sets - 1) * icache_line_size; + dcache_index_mask = (dcache_sets - 1) * dcache_line_size; + /* + * These are for choosing range (index ops) versus all. + * icache flushes all ways for each set, so drop icache_assoc. + * dcache flushes all ways and each setting of bit 12 for each + * index, so drop dcache_assoc and halve the dcache_sets. + */ + icache_range_cutoff = icache_sets * icache_line_size; + dcache_range_cutoff = (dcache_sets / 2) * icache_line_size; +} + +/* + * This is called from loadmmu.c. We have to set up all the + * memory management function pointers, as well as initialize + * the caches and tlbs + */ +void ld_mmu_sb1(void) +{ + extern char except_vec2_sb1; + unsigned long temp; + + /* Special cache error handler for SB1 */ + memcpy((void *)(KSEG0 + 0x100), &except_vec2_sb1, 0x80); + memcpy((void *)(KSEG1 + 0x100), &except_vec2_sb1, 0x80); + + probe_cache_sizes(); + + _clear_page = sb1_clear_page; + _copy_page = sb1_copy_page; + + /* + * None of these are needed for the SB1 - the Dcache is + * physically indexed and tagged, so no virtual aliasing can + * occur + */ + flush_cache_range = (void *) sb1_nop; + flush_cache_page = sb1_flush_cache_page; + flush_cache_mm = (void (*)(struct mm_struct *))sb1_nop; + flush_cache_all = sb1_nop; + + /* These routines are for Icache coherence with the Dcache */ + flush_icache_range = sb1_flush_icache_range; + flush_icache_page = sb1_flush_icache_page; + flush_icache_all = __sb1_flush_icache_all; /* local only */ + + flush_cache_sigtramp = sb1_flush_cache_sigtramp; + flush_data_cache_page = (void *) sb1_nop; + + /* Full flush */ + __flush_cache_all = sb1___flush_cache_all; + + change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); + /* + * This is the only way to force the update of K0 to complete + * before subsequent instruction fetch. + */ + __asm__ __volatile__ ( + " .set push \n" + " .set mips4 \n" + " la %0, 1f \n" + " mtc0 %0, $14 \n" + " eret \n" + "1: .set pop \n" + : "=r" (temp)); + flush_cache_all(); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/c-tx39.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,495 @@ +/* + * r2300.c: R2000 and R3000 specific mmu/cache code. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * + * with a lot of changes to make this thing work for R3000s + * Tx39XX R4k style caches added. HK + * Copyright (C) 1998, 1999, 2000 Harald Koerfgen + * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* For R3000 cores with R4000 style caches */ +static unsigned long icache_size, dcache_size; /* Size in bytes */ +static unsigned long icache_way_size, dcache_way_size; /* Size divided by ways */ +#define scache_size 0 +#define scache_way_size 0 + +#include + +extern void r3k_clear_page(void * page); +extern void r3k_copy_page(void * to, void * from); + +extern int r3k_have_wired_reg; /* in r3k-tlb.c */ + +/* This sequence is required to ensure icache is disabled immediately */ +#define TX39_STOP_STREAMING() \ +__asm__ __volatile__( \ + ".set push\n\t" \ + ".set noreorder\n\t" \ + "b 1f\n\t" \ + "nop\n\t" \ + "1:\n\t" \ + ".set pop" \ + ) + +/* TX39H-style cache flush routines. */ +static void tx39h_flush_icache_all(void) +{ + unsigned long start = KSEG0; + unsigned long end = (start + icache_size); + unsigned long flags, config; + + /* disable icache (set ICE#) */ + local_irq_save(flags); + config = read_c0_conf(); + write_c0_conf(config & ~TX39_CONF_ICE); + TX39_STOP_STREAMING(); + + /* invalidate icache */ + while (start < end) { + cache16_unroll32(start, Index_Invalidate_I); + start += 0x200; + } + + write_c0_conf(config); + local_irq_restore(flags); +} + +static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + unsigned long dc_lsize = current_cpu_data.dcache.linesz; + + iob(); + a = addr & ~(dc_lsize - 1); + end = (addr + size - 1) & ~(dc_lsize - 1); + while (1) { + invalidate_dcache_line(a); /* Hit_Invalidate_D */ + if (a == end) break; + a += dc_lsize; + } +} + + +/* TX39H2,TX39H3 */ +static inline void tx39_blast_dcache_page(unsigned long addr) +{ + if (current_cpu_data.cputype != CPU_TX3912) + blast_dcache16_page(addr); +} + +static inline void tx39_blast_dcache_page_indexed(unsigned long addr) +{ + blast_dcache16_page_indexed(addr); +} + +static inline void tx39_blast_dcache(void) +{ + blast_dcache16(); +} + +static inline void tx39_blast_icache_page(unsigned long addr) +{ + unsigned long flags, config; + /* disable icache (set ICE#) */ + local_irq_save(flags); + config = read_c0_conf(); + write_c0_conf(config & ~TX39_CONF_ICE); + TX39_STOP_STREAMING(); + blast_icache16_page(addr); + write_c0_conf(config); + local_irq_restore(flags); +} + +static inline void tx39_blast_icache_page_indexed(unsigned long addr) +{ + unsigned long flags, config; + /* disable icache (set ICE#) */ + local_irq_save(flags); + config = read_c0_conf(); + write_c0_conf(config & ~TX39_CONF_ICE); + TX39_STOP_STREAMING(); + blast_icache16_page_indexed(addr); + write_c0_conf(config); + local_irq_restore(flags); +} + +static inline void tx39_blast_icache(void) +{ + unsigned long flags, config; + /* disable icache (set ICE#) */ + local_irq_save(flags); + config = read_c0_conf(); + write_c0_conf(config & ~TX39_CONF_ICE); + TX39_STOP_STREAMING(); + blast_icache16(); + write_c0_conf(config); + local_irq_restore(flags); +} + +static inline void tx39_flush_cache_all(void) +{ + if (!cpu_has_dc_aliases) + return; + + tx39_blast_dcache(); + tx39_blast_icache(); +} + +static inline void tx39___flush_cache_all(void) +{ + tx39_blast_dcache(); + tx39_blast_icache(); +} + +static void tx39_flush_cache_mm(struct mm_struct *mm) +{ + if (!cpu_has_dc_aliases) + return; + + if (cpu_context(smp_processor_id(), mm) != 0) { + tx39_flush_cache_all(); + } +} + +static void tx39_flush_cache_range(struct vm_area_struct *vma, + unsigned long start, unsigned long end) +{ + struct mm_struct *mm = vma->vm_mm; + + if (!cpu_has_dc_aliases) + return; + + if (cpu_context(smp_processor_id(), mm) != 0) { + tx39_blast_dcache(); + tx39_blast_icache(); + } +} + +static void tx39_flush_cache_page(struct vm_area_struct *vma, + unsigned long page) +{ + int exec = vma->vm_flags & VM_EXEC; + struct mm_struct *mm = vma->vm_mm; + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + + /* + * If ownes no valid ASID yet, cannot possibly have gotten + * this page into the cache. + */ + if (cpu_context(smp_processor_id(), mm) == 0) + return; + + page &= PAGE_MASK; + pgdp = pgd_offset(mm, page); + pmdp = pmd_offset(pgdp, page); + ptep = pte_offset(pmdp, page); + + /* + * If the page isn't marked valid, the page cannot possibly be + * in the cache. + */ + if (!(pte_val(*ptep) & _PAGE_PRESENT)) + return; + + /* + * Doing flushes for another ASID than the current one is + * too difficult since stupid R4k caches do a TLB translation + * for every cache flush operation. So we do indexed flushes + * in that case, which doesn't overly flush the cache too much. + */ + if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { + if (cpu_has_dc_aliases || exec) + tx39_blast_dcache_page(page); + if (exec) + tx39_blast_icache_page(page); + + return; + } + + /* + * Do indexed flush, too much work to get the (possible) TLB refills + * to work correctly. + */ + page = (KSEG0 + (page & (dcache_size - 1))); + if (cpu_has_dc_aliases || exec) + tx39_blast_dcache_page_indexed(page); + if (exec) + tx39_blast_icache_page_indexed(page); +} + +static void tx39_flush_data_cache_page(unsigned long addr) +{ + tx39_blast_dcache_page(addr); +} + +static void tx39_flush_icache_range(unsigned long start, unsigned long end) +{ + unsigned long dc_lsize = current_cpu_data.dcache.linesz; + unsigned long addr, aend; + + if (end - start > dcache_size) + tx39_blast_dcache(); + else { + addr = start & ~(dc_lsize - 1); + aend = (end - 1) & ~(dc_lsize - 1); + + while (1) { + /* Hit_Writeback_Inv_D */ + protected_writeback_dcache_line(addr); + if (addr == aend) + break; + addr += dc_lsize; + } + } + + if (end - start > icache_size) + tx39_blast_icache(); + else { + unsigned long flags, config; + addr = start & ~(dc_lsize - 1); + aend = (end - 1) & ~(dc_lsize - 1); + /* disable icache (set ICE#) */ + local_irq_save(flags); + config = read_c0_conf(); + write_c0_conf(config & ~TX39_CONF_ICE); + TX39_STOP_STREAMING(); + while (1) { + /* Hit_Invalidate_I */ + protected_flush_icache_line(addr); + if (addr == aend) + break; + addr += dc_lsize; + } + write_c0_conf(config); + local_irq_restore(flags); + } +} + +/* + * Ok, this seriously sucks. We use them to flush a user page but don't + * know the virtual address, so we have to blast away the whole icache + * which is significantly more expensive than the real thing. Otoh we at + * least know the kernel address of the page so we can flush it + * selectivly. + */ +static void tx39_flush_icache_page(struct vm_area_struct *vma, struct page *page) +{ + unsigned long addr; + /* + * If there's no context yet, or the page isn't executable, no icache + * flush is needed. + */ + if (!(vma->vm_flags & VM_EXEC)) + return; + + addr = (unsigned long) page_address(page); + tx39_blast_dcache_page(addr); + + /* + * We're not sure of the virtual address(es) involved here, so + * we have to flush the entire I-cache. + */ + tx39_blast_icache(); +} + +static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + + if (((size | addr) & (PAGE_SIZE - 1)) == 0) { + end = addr + size; + do { + tx39_blast_dcache_page(addr); + addr += PAGE_SIZE; + } while(addr != end); + } else if (size > dcache_size) { + tx39_blast_dcache(); + } else { + unsigned long dc_lsize = current_cpu_data.dcache.linesz; + a = addr & ~(dc_lsize - 1); + end = (addr + size - 1) & ~(dc_lsize - 1); + while (1) { + flush_dcache_line(a); /* Hit_Writeback_Inv_D */ + if (a == end) break; + a += dc_lsize; + } + } +} + +static void tx39_dma_cache_inv(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + + if (((size | addr) & (PAGE_SIZE - 1)) == 0) { + end = addr + size; + do { + tx39_blast_dcache_page(addr); + addr += PAGE_SIZE; + } while(addr != end); + } else if (size > dcache_size) { + tx39_blast_dcache(); + } else { + unsigned long dc_lsize = current_cpu_data.dcache.linesz; + a = addr & ~(dc_lsize - 1); + end = (addr + size - 1) & ~(dc_lsize - 1); + while (1) { + invalidate_dcache_line(a); /* Hit_Invalidate_D */ + if (a == end) break; + a += dc_lsize; + } + } +} + +static void tx39_flush_cache_sigtramp(unsigned long addr) +{ + unsigned long ic_lsize = current_cpu_data.icache.linesz; + unsigned long dc_lsize = current_cpu_data.dcache.linesz; + unsigned long config; + unsigned long flags; + + protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); + + /* disable icache (set ICE#) */ + local_irq_save(flags); + config = read_c0_conf(); + write_c0_conf(config & ~TX39_CONF_ICE); + TX39_STOP_STREAMING(); + protected_flush_icache_line(addr & ~(ic_lsize - 1)); + write_c0_conf(config); + local_irq_restore(flags); +} + +static __init void tx39_probe_cache(void) +{ + unsigned long config; + + config = read_c0_conf(); + + icache_size = 1 << (10 + ((config & TX39_CONF_ICS_MASK) >> + TX39_CONF_ICS_SHIFT)); + dcache_size = 1 << (10 + ((config & TX39_CONF_DCS_MASK) >> + TX39_CONF_DCS_SHIFT)); + + current_cpu_data.icache.linesz = 16; + switch (current_cpu_data.cputype) { + case CPU_TX3912: + current_cpu_data.icache.ways = 1; + current_cpu_data.dcache.ways = 1; + current_cpu_data.dcache.linesz = 4; + break; + + case CPU_TX3927: + current_cpu_data.icache.ways = 2; + current_cpu_data.dcache.ways = 2; + current_cpu_data.dcache.linesz = 16; + break; + + case CPU_TX3922: + default: + current_cpu_data.icache.ways = 1; + current_cpu_data.dcache.ways = 1; + current_cpu_data.dcache.linesz = 16; + break; + } +} + +void __init ld_mmu_tx39(void) +{ + unsigned long config; + + _clear_page = r3k_clear_page; + _copy_page = r3k_copy_page; + + config = read_c0_conf(); + config &= ~TX39_CONF_WBON; + write_c0_conf(config); + + tx39_probe_cache(); + + switch (current_cpu_data.cputype) { + case CPU_TX3912: + /* TX39/H core (writethru direct-map cache) */ + flush_cache_all = tx39h_flush_icache_all; + __flush_cache_all = tx39h_flush_icache_all; + flush_cache_mm = (void *) tx39h_flush_icache_all; + flush_cache_range = (void *) tx39h_flush_icache_all; + flush_cache_page = (void *) tx39h_flush_icache_all; + flush_icache_page = (void *) tx39h_flush_icache_all; + flush_icache_range = (void *) tx39h_flush_icache_all; + + flush_cache_sigtramp = (void *) tx39h_flush_icache_all; + flush_data_cache_page = (void *) tx39h_flush_icache_all; + + _dma_cache_wback_inv = tx39h_dma_cache_wback_inv; + + shm_align_mask = PAGE_SIZE - 1; + + break; + + case CPU_TX3922: + case CPU_TX3927: + default: + /* TX39/H2,H3 core (writeback 2way-set-associative cache) */ + r3k_have_wired_reg = 1; + write_c0_wired(0); /* set 8 on reset... */ + /* board-dependent init code may set WBON */ + + flush_cache_all = tx39_flush_cache_all; + __flush_cache_all = tx39___flush_cache_all; + flush_cache_mm = tx39_flush_cache_mm; + flush_cache_range = tx39_flush_cache_range; + flush_cache_page = tx39_flush_cache_page; + flush_icache_page = tx39_flush_icache_page; + flush_icache_range = tx39_flush_icache_range; + + flush_cache_sigtramp = tx39_flush_cache_sigtramp; + flush_data_cache_page = tx39_flush_data_cache_page; + + _dma_cache_wback_inv = tx39_dma_cache_wback_inv; + _dma_cache_wback = tx39_dma_cache_wback_inv; + _dma_cache_inv = tx39_dma_cache_inv; + + shm_align_mask = max_t(unsigned long, + (dcache_size / current_cpu_data.dcache.ways) - 1, + PAGE_SIZE - 1); + + break; + } + + icache_way_size = icache_size / current_cpu_data.icache.ways; + dcache_way_size = dcache_size / current_cpu_data.dcache.ways; + + current_cpu_data.icache.sets = + icache_way_size / current_cpu_data.icache.linesz; + current_cpu_data.dcache.sets = + dcache_way_size / current_cpu_data.dcache.linesz; + + if (dcache_way_size > PAGE_SIZE) + current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES; + + current_cpu_data.icache.waybit = 0; + current_cpu_data.dcache.waybit = 0; + + printk("Primary instruction cache %ldkb, linesize %d bytes\n", + icache_size >> 10, current_cpu_data.icache.linesz); + printk("Primary data cache %ldkb, linesize %d bytes\n", + dcache_size >> 10, current_cpu_data.dcache.linesz); +} --- linux-2.5.73/arch/mips/mm/extable.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/mips/mm/extable.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,62 +1,30 @@ /* - * linux/arch/mips/mm/extable.c + * linux/arch/i386/mm/extable.c */ + #include #include #include #include -extern const struct exception_table_entry __start___ex_table[]; -extern const struct exception_table_entry __stop___ex_table[]; - -static inline unsigned long -search_one_table(const struct exception_table_entry *first, - const struct exception_table_entry *last, - unsigned long value) +/* Simple binary search */ +const struct exception_table_entry * +search_extable(const struct exception_table_entry *first, + const struct exception_table_entry *last, + unsigned long value) { - while (first <= last) { + while (first <= last) { const struct exception_table_entry *mid; long diff; mid = (last - first) / 2 + first; diff = mid->insn - value; - if (diff == 0) - return mid->nextinsn; - else if (diff < 0) - first = mid+1; - else - last = mid-1; - } - return 0; -} - -extern spinlock_t modlist_lock; - -unsigned long -search_exception_table(unsigned long addr) -{ - unsigned long ret = 0; - -#ifndef CONFIG_MODULES - /* There is only the kernel to search. */ - ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr); - return ret; -#else - unsigned long flags; - - /* The kernel is the last "module" -- no need to treat it special. */ - struct module *mp; - - spin_lock_irqsave(&modlist_lock, flags); - for (mp = module_list; mp != NULL; mp = mp->next) { - if (mp->ex_table_start == NULL || !(mp->flags&(MOD_RUNNING|MOD_INITIALIZING))) - continue; - ret = search_one_table(mp->ex_table_start, - mp->ex_table_end - 1, addr); - if (ret) - break; - } - spin_unlock_irqrestore(&modlist_lock, flags); - return ret; -#endif + if (diff == 0) + return mid; + else if (diff < 0) + first = mid+1; + else + last = mid-1; + } + return NULL; } --- linux-2.5.73/arch/mips/mm/fault.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/mips/mm/fault.c 2003-06-27 15:56:23.000000000 -0700 @@ -5,6 +5,7 @@ * * Copyright (C) 1995 - 2000 by Ralf Baechle */ +#include #include #include #include @@ -18,23 +19,50 @@ #include #include #include +#include /* For unblank_screen() */ +#include +#include #include #include #include #include #include +#include #define development_version (LINUX_VERSION_CODE & 0x100) -unsigned long asid_cache = ASID_FIRST_VERSION; - /* * Macro for exception fixup code to access integer registers. */ #define dpf_reg(r) (regs->regs[r]) /* + * Unlock any spinlocks which will prevent us from getting the out + */ +void bust_spinlocks(int yes) +{ + int loglevel_save = console_loglevel; + + if (yes) { + oops_in_progress = 1; + return; + } +#ifdef CONFIG_VT + unblank_screen(); +#endif + oops_in_progress = 0; + /* + * OK, the message is on the console. Now we call printk() + * without oops_in_progress set so that printk will give klogd + * a poke. Hold onto your hats... + */ + console_loglevel = 15; /* NMI oopser may have shut the console up */ + printk(" "); + console_loglevel = loglevel_save; +} + +/* * This routine handles page faults. It determines the address, * and the problem, and then passes it off to one of the appropriate * routines. @@ -45,9 +73,14 @@ asmlinkage void do_page_fault(struct pt_ struct vm_area_struct * vma; struct task_struct *tsk = current; struct mm_struct *mm = tsk->mm; - unsigned long fixup; + const struct exception_table_entry *fixup; siginfo_t info; +#if 0 + printk("Cpu%d[%s:%d:%08lx:%ld:%08lx]\n", smp_processor_id(), + current->comm, current->pid, address, write, regs->cp0_epc); +#endif + /* * We fault-in kernel-space virtual memory on-demand. The * 'reference' page table is init_mm.pgd. @@ -57,7 +90,7 @@ asmlinkage void do_page_fault(struct pt_ * only copy the information from the master page table, * nothing more. */ - if (address >= TASK_SIZE) + if (address >= VMALLOC_START) goto vmalloc_fault; info.si_code = SEGV_MAPERR; @@ -65,12 +98,9 @@ asmlinkage void do_page_fault(struct pt_ * If we're in an interrupt or have no user * context, we must not take the fault.. */ - if (in_interrupt() || !mm) + if (in_atomic() || !mm) goto no_context; -#if 0 - printk("[%s:%d:%08lx:%ld:%08lx]\n", current->comm, current->pid, - address, write, regs->cp0_epc); -#endif + down_read(&mm->mmap_sem); vma = find_vma(mm, address); if (!vma) @@ -96,22 +126,25 @@ good_area: goto bad_area; } +survive: /* * If for any reason at all we couldn't handle the fault, * make sure we exit gracefully rather than endlessly redo * the fault. */ switch (handle_mm_fault(mm, vma, address, write)) { - case 1: + case VM_FAULT_MINOR: tsk->min_flt++; break; - case 2: + case VM_FAULT_MAJOR: tsk->maj_flt++; break; - case 0: + case VM_FAULT_SIGBUS: goto do_sigbus; - default: + case VM_FAULT_OOM: goto out_of_memory; + default: + BUG(); } up_read(&mm->mmap_sem); @@ -124,7 +157,6 @@ good_area: bad_area: up_read(&mm->mmap_sem); -bad_area_nosemaphore: /* User mode accesses just cause a SIGSEGV */ if (user_mode(regs)) { tsk->thread.cp0_badvaddr = address; @@ -148,12 +180,11 @@ bad_area_nosemaphore: no_context: /* Are we prepared to handle this kernel fault? */ - fixup = search_exception_table(regs->cp0_epc); + fixup = search_exception_tables(exception_epc(regs)); if (fixup) { - long new_epc; + unsigned long new_epc = fixup->nextinsn; tsk->thread.cp0_baduaddr = address; - new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc); if (development_version) printk(KERN_DEBUG "%s: Exception at [<%lx>] (%lx)\n", tsk->comm, regs->cp0_epc, new_epc); @@ -165,11 +196,13 @@ no_context: * Oops. The kernel tried to access some bad page. We'll have to * terminate things with extreme prejudice. */ + + bust_spinlocks(1); + printk(KERN_ALERT "Unable to handle kernel paging request at virtual " "address %08lx, epc == %08lx, ra == %08lx\n", address, regs->cp0_epc, regs->regs[31]); die("Oops", regs); - do_exit(SIGKILL); /* * We ran out of memory, or some other thing happened to us that made @@ -177,6 +210,11 @@ no_context: */ out_of_memory: up_read(&mm->mmap_sem); + if (tsk->pid == 1) { + yield(); + down_read(&mm->mmap_sem); + goto survive; + } printk("VM: killing process %s\n", tsk->comm); if (user_mode(regs)) do_exit(SIGKILL); @@ -207,26 +245,31 @@ vmalloc_fault: /* * Synchronize this task's top level page-table * with the 'reference' page table. + * + * Do _not_ use "tsk" here. We might be inside + * an interrupt in the middle of a task switch.. */ - int offset = pgd_index(address); + int offset = __pgd_offset(address); pgd_t *pgd, *pgd_k; pmd_t *pmd, *pmd_k; + pte_t *pte_k; - pgd = tsk->active_mm->pgd + offset; + pgd = (pgd_t *) pgd_current[smp_processor_id()] + offset; pgd_k = init_mm.pgd + offset; - if (!pgd_present(*pgd)) { - if (!pgd_present(*pgd_k)) - goto bad_area_nosemaphore; - set_pgd(pgd, *pgd_k); - return; - } + if (!pgd_present(*pgd_k)) + goto no_context; + set_pgd(pgd, *pgd_k); pmd = pmd_offset(pgd, address); pmd_k = pmd_offset(pgd_k, address); - - if (pmd_present(*pmd) || !pmd_present(*pmd_k)) - goto bad_area_nosemaphore; + if (!pmd_present(*pmd_k)) + goto no_context; set_pmd(pmd, *pmd_k); + + pte_k = pte_offset_kernel(pmd_k, address); + if (!pte_present(*pte_k)) + goto no_context; + return; } } --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/highmem.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,101 @@ +#include +#include +#include + +void *kmap(struct page *page) +{ + void *addr; + + if (in_interrupt()) + BUG(); + + if (page < highmem_start_page) + return page_address(page); + addr = kmap_high(page); + flush_tlb_one((unsigned long)addr); + + return addr; +} + +void kunmap(struct page *page) +{ + if (in_interrupt()) + BUG(); + if (page < highmem_start_page) + return; + kunmap_high(page); +} + +/* + * kmap_atomic/kunmap_atomic is significantly faster than kmap/kunmap because + * no global lock is needed and because the kmap code must perform a global TLB + * invalidation when the kmap pool wraps. + * + * However when holding an atomic kmap is is not legal to sleep, so atomic + * kmaps are appropriate for short, tight code paths only. + */ + +void *kmap_atomic(struct page *page, enum km_type type) +{ + enum fixed_addresses idx; + unsigned long vaddr; + + inc_preempt_count(); + if (page < highmem_start_page) + return page_address(page); + + idx = type + KM_TYPE_NR*smp_processor_id(); + vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); +#ifdef CONFIG_DEBUG_HIGHMEM + if (!pte_none(*(kmap_pte-idx))) + BUG(); +#endif + set_pte(kmap_pte-idx, mk_pte(page, kmap_prot)); + local_flush_tlb_one((unsigned long)vaddr); + + return (void*) vaddr; +} + +void kunmap_atomic(void *kvaddr, enum km_type type) +{ +#ifdef CONFIG_DEBUG_HIGHMEM + unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; + enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id(); + + if (vaddr < FIXADDR_START) { // FIXME + dec_preempt_count(); + return; + } + + if (vaddr != __fix_to_virt(FIX_KMAP_BEGIN+idx)) + BUG(); + + /* + * force other mappings to Oops if they'll try to access + * this pte without first remap it + */ + pte_clear(kmap_pte-idx); + local_flush_tlb_one(vaddr); +#endif + + dec_preempt_count(); +} + +struct page *kmap_atomic_to_page(void *ptr) +{ + unsigned long idx, vaddr = (unsigned long)ptr; + pte_t *pte; + + if (vaddr < FIXADDR_START) + return virt_to_page(ptr); + + idx = virt_to_fix(vaddr); + pte = kmap_pte - (idx - FIX_KMAP_BEGIN); + return pte_page(*pte); +} + +EXPORT_SYMBOL(kmap); +EXPORT_SYMBOL(kunmap); +EXPORT_SYMBOL(kmap_atomic); +EXPORT_SYMBOL(kunmap_atomic); +EXPORT_SYMBOL(kmap_atomic_to_page); --- linux-2.5.73/arch/mips/mm/init.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/mips/mm/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -24,36 +24,23 @@ #include #include #include -#ifdef CONFIG_BLK_DEV_INITRD #include -#endif #include +#include #include #include #include -#include -#include -#include #include -#ifdef CONFIG_SGI_IP22 -#include -#endif #include +#include #include DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); -extern void prom_free_prom_memory(void); - - -asmlinkage int sys_cacheflush(void *addr, int bytes, int cache) -{ - /* This should flush more selectivly ... */ - __flush_cache_all(); - - return 0; -} +unsigned long highstart_pfn, highend_pfn; +static unsigned long totalram_pages; +static unsigned long totalhigh_pages; /* * We have upto 8 empty zeroed pages so we can map one of the right colour @@ -68,9 +55,10 @@ static inline unsigned long setup_zero_p { unsigned long order, size; struct page *page; - if(mips_cpu.options & MIPS_CPU_VCE) + + if (cpu_has_vce) order = 3; - else + else order = 0; empty_zero_page = __get_free_pages(GFP_KERNEL, order); @@ -91,69 +79,109 @@ static inline unsigned long setup_zero_p return 1UL << order; } -int do_check_pgt_cache(int low, int high) +#ifdef CONFIG_HIGHMEM +pte_t *kmap_pte; +pgprot_t kmap_prot; + +#define kmap_get_fixmap_pte(vaddr) \ + pte_offset_kernel(pmd_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)) + +static void __init kmap_init(void) { - int freed = 0; + unsigned long kmap_vstart; + + /* cache the first kmap pte */ + kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN); + kmap_pte = kmap_get_fixmap_pte(kmap_vstart); - if(pgtable_cache_size > high) { - do { - if(pgd_quicklist) - free_pgd_slow(get_pgd_fast()), freed++; - if(pmd_quicklist) - free_pmd_slow(get_pmd_fast()), freed++; - if(pte_quicklist) - free_pte_slow(get_pte_fast()), freed++; - } while(pgtable_cache_size > low); - } - return freed; -} - -void show_mem(void) -{ - int i, free = 0, total = 0, reserved = 0; - int shared = 0, cached = 0; - - printk("Mem-info:\n"); - show_free_areas(); - printk("Free swap: %6dkB\n", nr_swap_pages<<(PAGE_SHIFT-10)); - i = max_mapnr; - while (i-- > 0) { - total++; - if (PageReserved(mem_map+i)) - reserved++; - else if (PageSwapCache(mem_map+i)) - cached++; - else if (!page_count(mem_map + i)) - free++; - else - shared += page_count(mem_map + i) - 1; - } - printk("%d pages of RAM\n", total); - printk("%d reserved pages\n", reserved); - printk("%d pages shared\n", shared); - printk("%d pages swap cached\n",cached); - printk("%ld pages in page table cache\n",pgtable_cache_size); - printk("%d free pages\n", free); + kmap_prot = PAGE_KERNEL; } -/* References to section boundaries */ +#endif /* CONFIG_HIGHMEM */ -extern char _ftext, _etext, _fdata, _edata; -extern char __init_begin, __init_end; +#ifdef CONFIG_HIGHMEM +static void __init fixrange_init (unsigned long start, unsigned long end, + pgd_t *pgd_base) +{ + pgd_t *pgd; + pmd_t *pmd; + pte_t *pte; + int i, j; + unsigned long vaddr; + + vaddr = start; + i = __pgd_offset(vaddr); + j = __pmd_offset(vaddr); + pgd = pgd_base + i; + + for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) { + pmd = (pmd_t *)pgd; + for (; (j < PTRS_PER_PMD) && (vaddr != end); pmd++, j++) { + if (pmd_none(*pmd)) { + pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); + set_pmd(pmd, __pmd(pte)); + if (pte != pte_offset_kernel(pmd, 0)) + BUG(); + } + vaddr += PMD_SIZE; + } + j = 0; + } +} +#endif -void __init paging_init(void) +void __init pagetable_init(void) { - unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0}; - unsigned long max_dma, low; +#ifdef CONFIG_HIGHMEM + unsigned long vaddr; + pgd_t *pgd, *pgd_base; + pmd_t *pmd; + pte_t *pte; +#endif /* Initialize the entire pgd. */ pgd_init((unsigned long)swapper_pg_dir); - pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2); + pgd_init((unsigned long)swapper_pg_dir + + sizeof(pgd_t ) * USER_PTRS_PER_PGD); + +#ifdef CONFIG_HIGHMEM + pgd_base = swapper_pg_dir; + + /* + * Fixed mappings: + */ + vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK; + fixrange_init(vaddr, 0, pgd_base); + + /* + * Permanent kmaps: + */ + vaddr = PKMAP_BASE; + fixrange_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base); + + pgd = swapper_pg_dir + __pgd_offset(vaddr); + pmd = pmd_offset(pgd, vaddr); + pte = pte_offset_kernel(pmd, vaddr); + pkmap_page_table = pte; +#endif +} + +void __init paging_init(void) +{ + unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0}; + unsigned long max_dma, high, low; + + pagetable_init(); + +#ifdef CONFIG_HIGHMEM + kmap_init(); +#endif max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT; low = max_low_pfn; + high = highend_pfn; -#if defined(CONFIG_PCI) || defined(CONFIG_ISA) +#ifdef CONFIG_ISA if (low < max_dma) zones_size[ZONE_DMA] = low; else { @@ -163,6 +191,9 @@ void __init paging_init(void) #else zones_size[ZONE_DMA] = low; #endif +#ifdef CONFIG_HIGHMEM + zones_size[ZONE_HIGHMEM] = high - low; +#endif free_area_init(zones_size); } @@ -197,8 +228,17 @@ void __init mem_init(void) unsigned long codesize, reservedpages, datasize, initsize; unsigned long tmp, ram; +#ifdef CONFIG_HIGHMEM + highstart_pfn = (KSEG1 - KSEG0) >> PAGE_SHIFT; + highmem_start_page = mem_map + highstart_pfn; +#ifdef CONFIG_DISCONTIGMEM +#error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet" +#endif + max_mapnr = num_physpages = highend_pfn; +#else max_mapnr = num_physpages = max_low_pfn; - high_memory = (void *) __va(max_mapnr << PAGE_SHIFT); +#endif + high_memory = (void *) __va(max_low_pfn * PAGE_SIZE); totalram_pages += free_all_bootmem(); totalram_pages -= setup_zero_pages(); /* Setup zeroed pages. */ @@ -211,25 +251,43 @@ void __init mem_init(void) reservedpages++; } - codesize = (unsigned long) &_etext - (unsigned long) &_ftext; - datasize = (unsigned long) &_edata - (unsigned long) &_fdata; +#ifdef CONFIG_HIGHMEM + for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) { + struct page *page = mem_map + tmp; + + if (!page_is_ram(tmp)) { + SetPageReserved(page); + continue; + } + ClearPageReserved(page); + set_bit(PG_highmem, &page->flags); + atomic_set(&page->count, 1); + __free_page(page); + totalhigh_pages++; + } + totalram_pages += totalhigh_pages; +#endif + + codesize = (unsigned long) &_etext - (unsigned long) &_text; + datasize = (unsigned long) &_edata - (unsigned long) &_etext; initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin; - printk("Memory: %luk/%luk available (%ldk kernel code, %ldk reserved, " - "%ldk data, %ldk init)\n", + printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, " + "%ldk reserved, %ldk data, %ldk init, %ldk highmem)\n", (unsigned long) nr_free_pages() << (PAGE_SHIFT-10), ram << (PAGE_SHIFT-10), codesize >> 10, reservedpages << (PAGE_SHIFT-10), datasize >> 10, - initsize >> 10); + initsize >> 10, + (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))); } #ifdef CONFIG_BLK_DEV_INITRD void free_initrd_mem(unsigned long start, unsigned long end) { if (start < end) - printk("Freeing initrd memory: %ldk freed\n", + printk(KERN_INFO "Freeing initrd memory: %ldk freed\n", (end - start) >> 10); for (; start < end; start += PAGE_SIZE) { @@ -242,14 +300,14 @@ void free_initrd_mem(unsigned long start #endif extern char __init_begin, __init_end; -extern void prom_free_prom_memory(void); +extern void prom_free_prom_memory(void) __init; void free_initmem(void) { unsigned long addr; prom_free_prom_memory (); - + addr = (unsigned long) &__init_begin; while (addr < (unsigned long) &__init_end) { ClearPageReserved(virt_to_page(addr)); @@ -258,6 +316,6 @@ void free_initmem(void) totalram_pages++; addr += PAGE_SIZE; } - printk("Freeing unused kernel memory: %dk freed\n", + printk(KERN_INFO "Freeing unused kernel memory: %dk freed\n", (&__init_end - &__init_begin) >> 10); } --- linux-2.5.73/arch/mips/mm/ioremap.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/mips/mm/ioremap.c 2003-06-27 15:56:23.000000000 -0700 @@ -4,20 +4,22 @@ * for more details. * * (C) Copyright 1995 1996 Linus Torvalds - * (C) Copyright 2001 Ralf Baechle + * (C) Copyright 2001, 2002 Ralf Baechle */ #include #include #include #include +#include #include #include +#include -static inline void remap_area_pte(pte_t * pte, unsigned long address, unsigned long size, - unsigned long phys_addr, unsigned long flags) +static inline void remap_area_pte(pte_t * pte, unsigned long address, + phys_t size, phys_t phys_addr, unsigned long flags) { - unsigned long end; + phys_t end; unsigned long pfn; pgprot_t pgprot = __pgprot(_PAGE_GLOBAL | _PAGE_PRESENT | __READABLE | __WRITEABLE | flags); @@ -41,10 +43,10 @@ static inline void remap_area_pte(pte_t } while (address && (address < end)); } -static inline int remap_area_pmd(pmd_t * pmd, unsigned long address, unsigned long size, - unsigned long phys_addr, unsigned long flags) +static inline int remap_area_pmd(pmd_t * pmd, unsigned long address, + phys_t size, phys_t phys_addr, unsigned long flags) { - unsigned long end; + phys_t end; address &= ~PGDIR_MASK; end = address + size; @@ -54,7 +56,7 @@ static inline int remap_area_pmd(pmd_t * if (address >= end) BUG(); do { - pte_t * pte = pte_alloc(&init_mm, pmd, address); + pte_t * pte = pte_alloc_kernel(&init_mm, pmd, address); if (!pte) return -ENOMEM; remap_area_pte(pte, address, end - address, address + phys_addr, flags); @@ -64,8 +66,8 @@ static inline int remap_area_pmd(pmd_t * return 0; } -static int remap_area_pages(unsigned long address, unsigned long phys_addr, - unsigned long size, unsigned long flags) +static int remap_area_pages(unsigned long address, phys_t phys_addr, + phys_t size, unsigned long flags) { int error; pgd_t * dir; @@ -109,13 +111,14 @@ static int remap_area_pages(unsigned lon * caller shouldn't need to know that small detail. */ -#define IS_LOW512(addr) (!((unsigned long)(addr) & ~0x1fffffffUL)) +#define IS_LOW512(addr) (!((phys_t)(addr) & ~0x1fffffffUL)) -void * __ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags) +void * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags) { - void * addr; struct vm_struct * area; - unsigned long offset, last_addr; + unsigned long offset; + phys_t last_addr; + void * addr; /* Don't allow wraparound or zero size */ last_addr = phys_addr + size - 1; @@ -123,10 +126,11 @@ void * __ioremap(unsigned long phys_addr return NULL; /* - * Map objects in the low 512mb of address space using KSEG1, otherwise - * map using page tables. + * Map uncached objects in the low 512mb of address space using KSEG1, + * otherwise map using page tables. */ - if (IS_LOW512(phys_addr) && IS_LOW512(phys_addr + size - 1)) + if (IS_LOW512(phys_addr) && IS_LOW512(last_addr) && + flags == _CACHE_UNCACHED) return (void *) KSEG1ADDR(phys_addr); /* @@ -138,7 +142,7 @@ void * __ioremap(unsigned long phys_addr t_addr = __va(phys_addr); t_end = t_addr + (size - 1); - + for(page = virt_to_page(t_addr); page <= virt_to_page(t_end); page++) if(!PageReserved(page)) return NULL; @@ -159,7 +163,7 @@ void * __ioremap(unsigned long phys_addr return NULL; addr = area->addr; if (remap_area_pages(VMALLOC_VMADDR(addr), phys_addr, size, flags)) { - vfree(addr); + vunmap(addr); return NULL; } @@ -170,8 +174,19 @@ void * __ioremap(unsigned long phys_addr void iounmap(void *addr) { - if (!IS_KSEG1(addr)) - return vfree((void *) (PAGE_MASK & (unsigned long) addr)); + struct vm_struct *p; + + if (IS_KSEG1(addr)) + return; + + vfree((void *) (PAGE_MASK & (unsigned long) addr)); + p = remove_vm_area((void *) (PAGE_MASK & (unsigned long) addr)); + if (!p) { + printk(KERN_ERR "iounmap: bad address %p\n", addr); + return; + } + + kfree(p); } EXPORT_SYMBOL(__ioremap); --- linux-2.5.73/arch/mips/mm/loadmmu.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/mips/mm/loadmmu.c 2003-06-27 15:56:23.000000000 -0700 @@ -1,7 +1,11 @@ /* - * loadmmu.c: Setup cpu/cache specific function ptrs at boot time. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 1999, 2000, 2001, 2002, 2003 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999 Silicon Graphics, Inc. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. */ @@ -10,6 +14,7 @@ #include #include #include +#include #include #include @@ -22,80 +27,93 @@ void (*_clear_page)(void * page); void (*_copy_page)(void * to, void * from); /* Cache operations. */ -void (*_flush_cache_all)(void); -void (*___flush_cache_all)(void); -void (*_flush_cache_mm)(struct mm_struct *mm); -void (*_flush_cache_range)(struct vm_area_struct *vma, unsigned long start, - unsigned long end); -void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page); -void (*_flush_cache_sigtramp)(unsigned long addr); -void (*_flush_page_to_ram)(struct page * page); -void (*_flush_icache_range)(unsigned long start, unsigned long end); -void (*_flush_icache_page)(struct vm_area_struct *vma, struct page *page); +void (*flush_cache_all)(void); +void (*__flush_cache_all)(void); +void (*flush_cache_mm)(struct mm_struct *mm); +void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, + unsigned long end); +void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page); +void (*flush_icache_range)(unsigned long start, unsigned long end); +void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); + +/* MIPS specific cache operations */ +void (*flush_cache_sigtramp)(unsigned long addr); +void (*flush_data_cache_page)(unsigned long addr); +void (*flush_icache_all)(void); + +#ifdef CONFIG_NONCOHERENT_IO /* DMA cache operations. */ void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); void (*_dma_cache_wback)(unsigned long start, unsigned long size); void (*_dma_cache_inv)(unsigned long start, unsigned long size); +EXPORT_SYMBOL(_dma_cache_wback_inv); +EXPORT_SYMBOL(_dma_cache_wback); +EXPORT_SYMBOL(_dma_cache_inv); + +#endif /* CONFIG_NONCOHERENT_IO */ + extern void ld_mmu_r23000(void); extern void ld_mmu_r4xx0(void); -extern void ld_mmu_r5432(void); +extern void ld_mmu_tx39(void); extern void ld_mmu_r6000(void); -extern void ld_mmu_rm7k(void); extern void ld_mmu_tfp(void); extern void ld_mmu_andes(void); extern void ld_mmu_sb1(void); -extern void ld_mmu_mips32(void); +extern void sb1_tlb_init(void); +extern void r3k_tlb_init(void); +extern void r4k_tlb_init(void); +extern void sb1_tlb_init(void); -void __init loadmmu(void) +void __init load_mmu(void) { - - if (mips_cpu.options & MIPS_CPU_4KTLB) { -#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \ - defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \ - defined(CONFIG_CPU_NEVADA) - printk("Loading R4000 MMU routines.\n"); + if (cpu_has_4ktlb) { +#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \ + defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \ + defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \ + defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32) || \ + defined(CONFIG_CPU_MIPS64) || defined(CONFIG_CPU_TX49XX) || \ + defined(CONFIG_CPU_RM7000) ld_mmu_r4xx0(); + r4k_tlb_init(); #endif -#if defined(CONFIG_CPU_RM7000) - printk("Loading RM7000 MMU routines.\n"); - ld_mmu_rm7k(); -#endif -#if defined(CONFIG_CPU_R5432) - printk("Loading R5432 MMU routines.\n"); - ld_mmu_r5432(); -#endif - -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - printk("Loading MIPS32 MMU routines.\n"); - ld_mmu_mips32(); -#endif - } else switch(mips_cpu.cputype) { + } else switch (current_cpu_data.cputype) { #ifdef CONFIG_CPU_R3000 case CPU_R2000: case CPU_R3000: case CPU_R3000A: + case CPU_R3081E: + ld_mmu_r23000(); + r3k_tlb_init(); + break; +#endif +#ifdef CONFIG_CPU_TX39XX case CPU_TX3912: case CPU_TX3922: case CPU_TX3927: - case CPU_R3081E: - printk("Loading R[23]000 MMU routines.\n"); - ld_mmu_r23000(); + ld_mmu_tx39(); + r3k_tlb_init(); break; #endif #ifdef CONFIG_CPU_R10000 case CPU_R10000: - printk("Loading R10000 MMU routines.\n"); - ld_mmu_andes(); + case CPU_R12000: + ld_mmu_r4xx0(); + andes_tlb_init(); break; #endif #ifdef CONFIG_CPU_SB1 case CPU_SB1: - printk("Loading SB1 MMU routines.\n"); ld_mmu_sb1(); + sb1_tlb_init(); break; #endif + + case CPU_R8000: + panic("R8000 is unsupported"); + break; + default: panic("Yeee, unsupported mmu/cache architecture."); } --- linux-2.5.73/arch/mips/mm/Makefile 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/mips/mm/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -2,17 +2,29 @@ # Makefile for the Linux/MIPS-specific parts of the memory manager. # -obj-y += extable.o init.o ioremap.o fault.o loadmmu.o +obj-y += cache.o extable.o init.o ioremap.o fault.o \ + pgtable.o loadmmu.o -obj-$(CONFIG_CPU_R3000) += r2300.o -obj-$(CONFIG_CPU_R4300) += r4xx0.o -obj-$(CONFIG_CPU_R4X00) += r4xx0.o -obj-$(CONFIG_CPU_VR41XX) += r4xx0.o -obj-$(CONFIG_CPU_R5000) += r4xx0.o -obj-$(CONFIG_CPU_NEVADA) += r4xx0.o -obj-$(CONFIG_CPU_R5432) += r5432.o -obj-$(CONFIG_CPU_RM7000) += rm7k.o -obj-$(CONFIG_CPU_MIPS32) += mips32.o -obj-$(CONFIG_CPU_MIPS64) += mips32.o -obj-$(CONFIG_SGI_IP22) += umap.o -obj-$(CONFIG_BAGET_MIPS) += umap.o +obj-$(CONFIG_HIGHMEM) += highmem.o + +obj-$(CONFIG_CPU_R3000) += pg-r3k.o c-r3k.o tlb-r3k.o tlbex-r3k.o +obj-$(CONFIG_CPU_TX39XX) += pg-r3k.o c-tx39.o tlb-r3k.o tlbex-r3k.o +obj-$(CONFIG_CPU_TX49XX) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o +obj-$(CONFIG_CPU_R4300) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o +obj-$(CONFIG_CPU_R4X00) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o +obj-$(CONFIG_CPU_VR41XX) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o +obj-$(CONFIG_CPU_R5000) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o +obj-$(CONFIG_CPU_NEVADA) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o +obj-$(CONFIG_CPU_R5432) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o +obj-$(CONFIG_CPU_RM7000) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o +obj-$(CONFIG_CPU_R10000) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o +obj-$(CONFIG_CPU_MIPS32) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o +obj-$(CONFIG_CPU_MIPS64) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o +obj-$(CONFIG_CPU_SB1) += c-sb1.o cex-sb1.o cerr-sb1.o pg-sb1.o \ + tlb-sb1.o tlbex-r4k.o + +obj-$(CONFIG_CPU_RM7000) += sc-rm7k.o +obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o +obj-$(CONFIG_SGI_IP22) += sc-ip22.o + +EXTRA_AFLAGS := $(CFLAGS) --- linux-2.5.73/arch/mips/mm/mips32.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,1065 +0,0 @@ -/* - * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * MIPS32 CPU variant specific MMU/Cache routines. - */ -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -/* CP0 hazard avoidance. */ -#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ - "nop; nop; nop; nop; nop; nop;\n\t" \ - ".set reorder\n\t") - -/* Primary cache parameters. */ -static int icache_size, dcache_size; /* Size in bytes */ -static int ic_lsize, dc_lsize; /* LineSize in bytes */ - -/* Secondary cache (if present) parameters. */ -static unsigned int scache_size, sc_lsize; /* Again, in bytes */ - -#include -#include - -#undef DEBUG_CACHE - -/* - * Dummy cache handling routines for machines without boardcaches - */ -static void no_sc_noop(void) {} - -static struct bcache_ops no_sc_ops = { - (void *)no_sc_noop, (void *)no_sc_noop, - (void *)no_sc_noop, (void *)no_sc_noop -}; - -struct bcache_ops *bcops = &no_sc_ops; - - -/* - * Zero an entire page. - */ - -static void mips32_clear_page_dc(unsigned long page) -{ - unsigned long i; - - if (mips_cpu.options & MIPS_CPU_CACHE_CDEX) { - for (i=page; ivm_mm; - unsigned long flags; - - if(mm->context == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (vma) { - if(mm->context != current->mm->context) { - mips32_flush_cache_all_sc(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void mips32_flush_cache_range_pc(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - - if(mm->context != 0) { - unsigned long flags; - -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - local_irq_save(flags); - blast_dcache(); blast_icache(); - local_irq_restore(flags); - } -} - -/* - * On architectures like the Sparc, we could get rid of lines in - * the cache created only by a certain context, but on the MIPS - * (and actually certain Sparc's) we cannot. - */ -static void mips32_flush_cache_mm_sc(struct mm_struct *mm) -{ - if(mm->context != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - mips32_flush_cache_all_sc(); - } -} - -static void mips32_flush_cache_mm_pc(struct mm_struct *mm) -{ - if(mm->context != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - mips32_flush_cache_all_pc(); - } -} - - - - - -static void mips32_flush_cache_page_sc(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (mm->context == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if (!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (mm->context != current->active_mm->context) { - /* - * Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache_page_indexed(page); - blast_scache_page_indexed(page); - } else - blast_scache_page(page); -out: - local_irq_restore(flags); -} - -static void mips32_flush_cache_page_pc(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (mm->context == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if (!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since Mips32 caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (mm == current->active_mm) { - blast_dcache_page(page); - } else { - /* Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (dcache_size - 1))); - blast_dcache_page_indexed(page); - } -out: - local_irq_restore(flags); -} - -/* If the addresses passed to these routines are valid, they are - * either: - * - * 1) In KSEG0, so we can do a direct flush of the page. - * 2) In KSEG2, and since every process can translate those - * addresses all the time in kernel mode we can do a direct - * flush. - * 3) In KSEG1, no flush necessary. - */ -static void mips32_flush_page_to_ram_sc(struct page *page) -{ - blast_scache_page((unsigned long)page_address(page)); -} - -static void mips32_flush_page_to_ram_pc(struct page *page) -{ - blast_dcache_page((unsigned long)page_address(page)); -} - -static void -mips32_flush_icache_page_s(struct vm_area_struct *vma, struct page *page) -{ - /* - * We did an scache flush therefore PI is already clean. - */ -} - -static void -mips32_flush_icache_range(unsigned long start, unsigned long end) -{ - flush_cache_all(); -} - -static void -mips32_flush_icache_page(struct vm_area_struct *vma, struct page *page) -{ - int address; - - if (!(vma->vm_flags & VM_EXEC)) - return; - - address = KSEG0 + ((unsigned long)page_address(page) & PAGE_MASK & (dcache_size - 1)); - blast_icache_page_indexed(address); -} - -/* - * Writeback and invalidate the primary cache dcache before DMA. - */ -static void -mips32_dma_cache_wback_inv_pc(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - unsigned int flags; - - if (size >= dcache_size) { - flush_cache_all(); - } else { - local_irq_save(flags); - a = addr & ~(dc_lsize - 1); - end = (addr + size) & ~(dc_lsize - 1); - while (1) { - flush_dcache_line(a); /* Hit_Writeback_Inv_D */ - if (a == end) break; - a += dc_lsize; - } - local_irq_restore(flags); - } - bc_wback_inv(addr, size); -} - -static void -mips32_dma_cache_wback_inv_sc(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - - if (size >= scache_size) { - flush_cache_all(); - return; - } - - a = addr & ~(sc_lsize - 1); - end = (addr + size) & ~(sc_lsize - 1); - while (1) { - flush_scache_line(a); /* Hit_Writeback_Inv_SD */ - if (a == end) break; - a += sc_lsize; - } -} - -static void -mips32_dma_cache_inv_pc(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - unsigned int flags; - - if (size >= dcache_size) { - flush_cache_all(); - } else { - local_irq_save(flags); - a = addr & ~(dc_lsize - 1); - end = (addr + size) & ~(dc_lsize - 1); - while (1) { - flush_dcache_line(a); /* Hit_Writeback_Inv_D */ - if (a == end) break; - a += dc_lsize; - } - local_irq_restore(flags); - } - - bc_inv(addr, size); -} - -static void -mips32_dma_cache_inv_sc(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - - if (size >= scache_size) { - flush_cache_all(); - return; - } - - a = addr & ~(sc_lsize - 1); - end = (addr + size) & ~(sc_lsize - 1); - while (1) { - flush_scache_line(a); /* Hit_Writeback_Inv_SD */ - if (a == end) break; - a += sc_lsize; - } -} - -static void -mips32_dma_cache_wback(unsigned long addr, unsigned long size) -{ - panic("mips32_dma_cache called - should not happen.\n"); -} - -/* - * While we're protected against bad userland addresses we don't care - * very much about what happens in that case. Usually a segmentation - * fault will dump the process later on anyway ... - */ -static void mips32_flush_cache_sigtramp(unsigned long addr) -{ - protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); - protected_flush_icache_line(addr & ~(ic_lsize - 1)); -} - -#undef DEBUG_TLB -#undef DEBUG_TLBUPDATE - -void flush_tlb_all(void) -{ - unsigned long flags; - unsigned long old_ctx; - int entry; - -#ifdef DEBUG_TLB - printk("[tlball]"); -#endif - - local_irq_save(flags); - /* Save old context and create impossible VPN2 value */ - old_ctx = (get_entryhi() & 0xff); - set_entryhi(KSEG0); - set_entrylo0(0); - set_entrylo1(0); - BARRIER; - - entry = get_wired(); - - /* Blast 'em all away. */ - while(entry < mips_cpu.tlbsize) { - /* Make sure all entries differ. */ - set_entryhi(KSEG0+entry*0x2000); - set_index(entry); - BARRIER; - tlb_write_indexed(); - BARRIER; - entry++; - } - BARRIER; - set_entryhi(old_ctx); - local_irq_restore(flags); -} - -void flush_tlb_mm(struct mm_struct *mm) -{ - if (mm->context != 0) { - unsigned long flags; - -#ifdef DEBUG_TLB - printk("[tlbmm<%d>]", mm->context); -#endif - local_irq_save(flags); - get_new_mmu_context(mm, asid_cache); - if (mm == current->active_mm) - set_entryhi(mm->context & 0xff); - local_irq_restore(flags); - } -} - -void flush_tlb_range(struct mm_struct *mm, unsigned long start, - unsigned long end) -{ - if(mm->context != 0) { - unsigned long flags; - int size; - -#ifdef DEBUG_TLB - printk("[tlbrange<%02x,%08lx,%08lx>]", (mm->context & 0xff), - start, end); -#endif - local_irq_save(flags); - size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - size = (size + 1) >> 1; - if(size <= mips_cpu.tlbsize/2) { - int oldpid = (get_entryhi() & 0xff); - int newpid = (mm->context & 0xff); - - start &= (PAGE_MASK << 1); - end += ((PAGE_SIZE << 1) - 1); - end &= (PAGE_MASK << 1); - while(start < end) { - int idx; - - set_entryhi(start | newpid); - start += (PAGE_SIZE << 1); - BARRIER; - tlb_probe(); - BARRIER; - idx = get_index(); - set_entrylo0(0); - set_entrylo1(0); - if(idx < 0) - continue; - /* Make sure all entries differ. */ - set_entryhi(KSEG0+idx*0x2000); - BARRIER; - tlb_write_indexed(); - BARRIER; - } - set_entryhi(oldpid); - } else { - get_new_mmu_context(mm, asid_cache); - if (mm == current->active_mm) - set_entryhi(mm->context & 0xff); - } - local_irq_restore(flags); - } -} - -void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) -{ - if (vma->vm_mm->context != 0) { - unsigned long flags; - int oldpid, newpid, idx; - -#ifdef DEBUG_TLB - printk("[tlbpage<%d,%08lx>]", vma->vm_mm->context, page); -#endif - newpid = (vma->vm_mm->context & 0xff); - page &= (PAGE_MASK << 1); - local_irq_save(flags); - oldpid = (get_entryhi() & 0xff); - set_entryhi(page | newpid); - BARRIER; - tlb_probe(); - BARRIER; - idx = get_index(); - set_entrylo0(0); - set_entrylo1(0); - if(idx < 0) - goto finish; - /* Make sure all entries differ. */ - set_entryhi(KSEG0+idx*0x2000); - BARRIER; - tlb_write_indexed(); - - finish: - BARRIER; - set_entryhi(oldpid); - local_irq_restore(flags); - } -} - -void pgd_init(unsigned long page) -{ - unsigned long *p = (unsigned long *) page; - int i; - - for(i = 0; i < USER_PTRS_PER_PGD; i+=8) { - p[i + 0] = (unsigned long) invalid_pte_table; - p[i + 1] = (unsigned long) invalid_pte_table; - p[i + 2] = (unsigned long) invalid_pte_table; - p[i + 3] = (unsigned long) invalid_pte_table; - p[i + 4] = (unsigned long) invalid_pte_table; - p[i + 5] = (unsigned long) invalid_pte_table; - p[i + 6] = (unsigned long) invalid_pte_table; - p[i + 7] = (unsigned long) invalid_pte_table; - } -} - -/* - * Updates the TLB with the new pte(s). - */ -void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) -{ - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - int idx, pid; - - /* - * Handle debugger faulting in for debugee. - */ - if (current->active_mm != vma->vm_mm) - return; - - pid = get_entryhi() & 0xff; - -#ifdef DEBUG_TLB - if((pid != (vma->vm_mm->context & 0xff)) || (vma->vm_mm->context == 0)) { - printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d tlbpid=%d\n", - (int) (vma->vm_mm->context & 0xff), pid); - } -#endif - - local_irq_save(flags); - address &= (PAGE_MASK << 1); - set_entryhi(address | (pid)); - pgdp = pgd_offset(vma->vm_mm, address); - BARRIER; - tlb_probe(); - BARRIER; - pmdp = pmd_offset(pgdp, address); - idx = get_index(); - ptep = pte_offset(pmdp, address); - BARRIER; - set_entrylo0(pte_val(*ptep++) >> 6); - set_entrylo1(pte_val(*ptep) >> 6); - set_entryhi(address | (pid)); - BARRIER; - if(idx < 0) { - tlb_write_random(); - } else { - tlb_write_indexed(); - } - BARRIER; - set_entryhi(pid); - BARRIER; - local_irq_restore(flags); -} - -void show_regs(struct pt_regs * regs) -{ - /* Saved main processor registers. */ - printk("$0 : %08lx %08lx %08lx %08lx\n", - 0UL, regs->regs[1], regs->regs[2], regs->regs[3]); - printk("$4 : %08lx %08lx %08lx %08lx\n", - regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); - printk("$8 : %08lx %08lx %08lx %08lx\n", - regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11]); - printk("$12: %08lx %08lx %08lx %08lx\n", - regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]); - printk("$16: %08lx %08lx %08lx %08lx\n", - regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19]); - printk("$20: %08lx %08lx %08lx %08lx\n", - regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]); - printk("$24: %08lx %08lx\n", - regs->regs[24], regs->regs[25]); - printk("$28: %08lx %08lx %08lx %08lx\n", - regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]); - - /* Saved cp0 registers. */ - printk("epc : %08lx %s\nStatus: %08lx\nCause : %08lx\n", - regs->cp0_epc, print_tainted(), regs->cp0_status, regs->cp0_cause); -} - -void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask) -{ - unsigned long flags; - unsigned long wired; - unsigned long old_pagemask; - unsigned long old_ctx; - - local_irq_save(flags); - /* Save old context and create impossible VPN2 value */ - old_ctx = (get_entryhi() & 0xff); - old_pagemask = get_pagemask(); - wired = get_wired(); - set_wired (wired + 1); - set_index (wired); - BARRIER; - set_pagemask (pagemask); - set_entryhi(entryhi); - set_entrylo0(entrylo0); - set_entrylo1(entrylo1); - BARRIER; - tlb_write_indexed(); - BARRIER; - - set_entryhi(old_ctx); - BARRIER; - set_pagemask (old_pagemask); - flush_tlb_all(); - local_irq_restore(flags); -} - -/* Detect and size the various caches. */ -static void __init probe_icache(unsigned long config) -{ - unsigned long config1; - unsigned int lsize; - - if (!(config & (1 << 31))) { - /* - * Not a MIPS32 complainant CPU. - * Config 1 register not supported, we assume R4k style. - */ - icache_size = 1 << (12 + ((config >> 9) & 7)); - ic_lsize = 16 << ((config >> 5) & 1); - mips_cpu.icache.linesz = ic_lsize; - - /* - * We cannot infer associativity - assume direct map - * unless probe template indicates otherwise - */ - if(!mips_cpu.icache.ways) mips_cpu.icache.ways = 1; - mips_cpu.icache.sets = - (icache_size / ic_lsize) / mips_cpu.icache.ways; - } else { - config1 = read_mips32_cp0_config1(); - - if ((lsize = ((config1 >> 19) & 7))) - mips_cpu.icache.linesz = 2 << lsize; - else - mips_cpu.icache.linesz = lsize; - mips_cpu.icache.sets = 64 << ((config1 >> 22) & 7); - mips_cpu.icache.ways = 1 + ((config1 >> 16) & 7); - - ic_lsize = mips_cpu.icache.linesz; - icache_size = mips_cpu.icache.sets * mips_cpu.icache.ways * - ic_lsize; - } - printk("Primary instruction cache %dkb, linesize %d bytes (%d ways)\n", - icache_size >> 10, ic_lsize, mips_cpu.icache.ways); -} - -static void __init probe_dcache(unsigned long config) -{ - unsigned long config1; - unsigned int lsize; - - if (!(config & (1 << 31))) { - /* - * Not a MIPS32 complainant CPU. - * Config 1 register not supported, we assume R4k style. - */ - dcache_size = 1 << (12 + ((config >> 6) & 7)); - dc_lsize = 16 << ((config >> 4) & 1); - mips_cpu.dcache.linesz = dc_lsize; - /* - * We cannot infer associativity - assume direct map - * unless probe template indicates otherwise - */ - if(!mips_cpu.dcache.ways) mips_cpu.dcache.ways = 1; - mips_cpu.dcache.sets = - (dcache_size / dc_lsize) / mips_cpu.dcache.ways; - } else { - config1 = read_mips32_cp0_config1(); - - if ((lsize = ((config1 >> 10) & 7))) - mips_cpu.dcache.linesz = 2 << lsize; - else - mips_cpu.dcache.linesz= lsize; - mips_cpu.dcache.sets = 64 << ((config1 >> 13) & 7); - mips_cpu.dcache.ways = 1 + ((config1 >> 7) & 7); - - dc_lsize = mips_cpu.dcache.linesz; - dcache_size = - mips_cpu.dcache.sets * mips_cpu.dcache.ways - * dc_lsize; - } - printk("Primary data cache %dkb, linesize %d bytes (%d ways)\n", - dcache_size >> 10, dc_lsize, mips_cpu.dcache.ways); -} - - -/* If you even _breathe_ on this function, look at the gcc output - * and make sure it does not pop things on and off the stack for - * the cache sizing loop that executes in KSEG1 space or else - * you will crash and burn badly. You have been warned. - */ -static int __init probe_scache(unsigned long config) -{ - extern unsigned long stext; - unsigned long flags, addr, begin, end, pow2; - int tmp; - - if (mips_cpu.scache.flags == MIPS_CACHE_NOT_PRESENT) - return 0; - - tmp = ((config >> 17) & 1); - if(tmp) - return 0; - tmp = ((config >> 22) & 3); - switch(tmp) { - case 0: - sc_lsize = 16; - break; - case 1: - sc_lsize = 32; - break; - case 2: - sc_lsize = 64; - break; - case 3: - sc_lsize = 128; - break; - } - - begin = (unsigned long) &stext; - begin &= ~((4 * 1024 * 1024) - 1); - end = begin + (4 * 1024 * 1024); - - /* This is such a bitch, you'd think they would make it - * easy to do this. Away you daemons of stupidity! - */ - local_irq_save(flags); - - /* Fill each size-multiple cache line with a valid tag. */ - pow2 = (64 * 1024); - for(addr = begin; addr < end; addr = (begin + pow2)) { - unsigned long *p = (unsigned long *) addr; - __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ - pow2 <<= 1; - } - - /* Load first line with zero (therefore invalid) tag. */ - set_taglo(0); - set_taghi(0); - __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ - __asm__ __volatile__("\n\t.set noreorder\n\t" - ".set mips3\n\t" - "cache 8, (%0)\n\t" - ".set mips0\n\t" - ".set reorder\n\t" : : "r" (begin)); - __asm__ __volatile__("\n\t.set noreorder\n\t" - ".set mips3\n\t" - "cache 9, (%0)\n\t" - ".set mips0\n\t" - ".set reorder\n\t" : : "r" (begin)); - __asm__ __volatile__("\n\t.set noreorder\n\t" - ".set mips3\n\t" - "cache 11, (%0)\n\t" - ".set mips0\n\t" - ".set reorder\n\t" : : "r" (begin)); - - /* Now search for the wrap around point. */ - pow2 = (128 * 1024); - tmp = 0; - for(addr = (begin + (128 * 1024)); addr < (end); addr = (begin + pow2)) { - __asm__ __volatile__("\n\t.set noreorder\n\t" - ".set mips3\n\t" - "cache 7, (%0)\n\t" - ".set mips0\n\t" - ".set reorder\n\t" : : "r" (addr)); - __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ - if(!get_taglo()) - break; - pow2 <<= 1; - } - local_irq_restore(flags); - addr -= begin; - printk("Secondary cache sized at %dK linesize %d bytes.\n", - (int) (addr >> 10), sc_lsize); - scache_size = addr; - return 1; -} - -static void __init setup_noscache_funcs(void) -{ - _clear_page = (void *)mips32_clear_page_dc; - _copy_page = (void *)mips32_copy_page_dc; - _flush_cache_all = mips32_flush_cache_all_pc; - ___flush_cache_all = mips32_flush_cache_all_pc; - _flush_cache_mm = mips32_flush_cache_mm_pc; - _flush_cache_range = mips32_flush_cache_range_pc; - _flush_cache_page = mips32_flush_cache_page_pc; - _flush_page_to_ram = mips32_flush_page_to_ram_pc; - - _flush_icache_page = mips32_flush_icache_page; - - _dma_cache_wback_inv = mips32_dma_cache_wback_inv_pc; - _dma_cache_wback = mips32_dma_cache_wback; - _dma_cache_inv = mips32_dma_cache_inv_pc; -} - -static void __init setup_scache_funcs(void) -{ - _flush_cache_all = mips32_flush_cache_all_sc; - ___flush_cache_all = mips32_flush_cache_all_sc; - _flush_cache_mm = mips32_flush_cache_mm_sc; - _flush_cache_range = mips32_flush_cache_range_sc; - _flush_cache_page = mips32_flush_cache_page_sc; - _flush_page_to_ram = mips32_flush_page_to_ram_sc; - _clear_page = (void *)mips32_clear_page_sc; - _copy_page = (void *)mips32_copy_page_sc; - - _flush_icache_page = mips32_flush_icache_page_s; - - _dma_cache_wback_inv = mips32_dma_cache_wback_inv_sc; - _dma_cache_wback = mips32_dma_cache_wback; - _dma_cache_inv = mips32_dma_cache_inv_sc; -} - -typedef int (*probe_func_t)(unsigned long); - -static inline void __init setup_scache(unsigned int config) -{ - probe_func_t probe_scache_kseg1; - int sc_present = 0; - - /* Maybe the cpu knows about a l2 cache? */ - probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache)); - sc_present = probe_scache_kseg1(config); - - if (sc_present) { - mips_cpu.scache.linesz = sc_lsize; - /* - * We cannot infer associativity - assume direct map - * unless probe template indicates otherwise - */ - if(!mips_cpu.scache.ways) mips_cpu.scache.ways = 1; - mips_cpu.scache.sets = - (scache_size / sc_lsize) / mips_cpu.scache.ways; - - setup_scache_funcs(); - return; - } - - setup_noscache_funcs(); -} - -static void __init probe_tlb(unsigned long config) -{ - unsigned long config1; - - if (!(config & (1 << 31))) { - /* - * Not a MIPS32 complainant CPU. - * Config 1 register not supported, we assume R4k style. - */ - mips_cpu.tlbsize = 48; - } else { - config1 = read_mips32_cp0_config1(); - if (!((config >> 7) & 3)) - panic("No MMU present"); - else - mips_cpu.tlbsize = ((config1 >> 25) & 0x3f) + 1; - } - - printk("Number of TLB entries %d.\n", mips_cpu.tlbsize); -} - -void __init ld_mmu_mips32(void) -{ - unsigned long config = read_32bit_cp0_register(CP0_CONFIG); - - printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID)); - -#ifdef CONFIG_MIPS_UNCACHED - change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); -#else - change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); -#endif - - probe_icache(config); - probe_dcache(config); - setup_scache(config); - probe_tlb(config); - - _flush_cache_sigtramp = mips32_flush_cache_sigtramp; - _flush_icache_range = mips32_flush_icache_range; /* Ouch */ - - __flush_cache_all(); - write_32bit_cp0_register(CP0_WIRED, 0); - - /* - * You should never change this register: - * - The entire mm handling assumes the c0_pagemask register to - * be set for 4kb pages. - */ - write_32bit_cp0_register(CP0_PAGEMASK, PM_4K); - flush_tlb_all(); -} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/pg-r3k.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2001 Ralf Baechle (ralf@gnu.org) + */ +#include +#include + +/* page functions */ +void r3k_clear_page(void * page) +{ + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "addiu\t$1,%0,%2\n" + "1:\tsw\t$0,(%0)\n\t" + "sw\t$0,4(%0)\n\t" + "sw\t$0,8(%0)\n\t" + "sw\t$0,12(%0)\n\t" + "addiu\t%0,32\n\t" + "sw\t$0,-16(%0)\n\t" + "sw\t$0,-12(%0)\n\t" + "sw\t$0,-8(%0)\n\t" + "bne\t$1,%0,1b\n\t" + "sw\t$0,-4(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (page) + : "0" (page), "I" (PAGE_SIZE) + : "memory"); +} + +void r3k_copy_page(void * to, void * from) +{ + unsigned long dummy1, dummy2; + unsigned long reg1, reg2, reg3, reg4; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "addiu\t$1,%0,%8\n" + "1:\tlw\t%2,(%1)\n\t" + "lw\t%3,4(%1)\n\t" + "lw\t%4,8(%1)\n\t" + "lw\t%5,12(%1)\n\t" + "sw\t%2,(%0)\n\t" + "sw\t%3,4(%0)\n\t" + "sw\t%4,8(%0)\n\t" + "sw\t%5,12(%0)\n\t" + "lw\t%2,16(%1)\n\t" + "lw\t%3,20(%1)\n\t" + "lw\t%4,24(%1)\n\t" + "lw\t%5,28(%1)\n\t" + "sw\t%2,16(%0)\n\t" + "sw\t%3,20(%0)\n\t" + "sw\t%4,24(%0)\n\t" + "sw\t%5,28(%0)\n\t" + "addiu\t%0,64\n\t" + "addiu\t%1,64\n\t" + "lw\t%2,-32(%1)\n\t" + "lw\t%3,-28(%1)\n\t" + "lw\t%4,-24(%1)\n\t" + "lw\t%5,-20(%1)\n\t" + "sw\t%2,-32(%0)\n\t" + "sw\t%3,-28(%0)\n\t" + "sw\t%4,-24(%0)\n\t" + "sw\t%5,-20(%0)\n\t" + "lw\t%2,-16(%1)\n\t" + "lw\t%3,-12(%1)\n\t" + "lw\t%4,-8(%1)\n\t" + "lw\t%5,-4(%1)\n\t" + "sw\t%2,-16(%0)\n\t" + "sw\t%3,-12(%0)\n\t" + "sw\t%4,-8(%0)\n\t" + "bne\t$1,%0,1b\n\t" + "sw\t%5,-4(%0)\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (dummy1), "=r" (dummy2), + "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) + : "0" (to), "1" (from), + "I" (PAGE_SIZE)); +} + +/* + * Initialize new page directory with pointers to invalid ptes + */ +void pgd_init(unsigned long page) +{ + unsigned long dummy1, dummy2; + + /* + * The plain and boring version for the R3000. No cache flushing + * stuff is implemented since the R3000 has physical caches. + */ + __asm__ __volatile__( + ".set\tnoreorder\n" + "1:\tsw\t%2, (%0)\n\t" + "sw\t%2, 4(%0)\n\t" + "sw\t%2, 8(%0)\n\t" + "sw\t%2, 12(%0)\n\t" + "sw\t%2, 16(%0)\n\t" + "sw\t%2, 20(%0)\n\t" + "sw\t%2, 24(%0)\n\t" + "sw\t%2, 28(%0)\n\t" + "subu\t%1, 1\n\t" + "bnez\t%1, 1b\n\t" + "addiu\t%0, 32\n\t" + ".set\treorder" + :"=r" (dummy1), "=r" (dummy2) + :"r" ((unsigned long) invalid_pte_table), "0" (page), + "1" (USER_PTRS_PER_PGD / 8)); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/pg-r4k.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,803 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * r4xx0.c: R4000 processor variant specific MMU/Cache routines. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org + */ +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_64BIT_PHYS_ADDR +#define PGD_SIZE 0x2000 +#else +#define PGD_SIZE 0x1000 +#endif + + .text + .set noat + +/* + * Zero an entire page. Basically a simple unrolled loop should do the + * job but we want more performance by saving memory bus bandwidth. We + * have five flavours of the routine available for: + * + * - 16byte cachelines and no second level cache + * - 32byte cachelines second level cache + * - a version which handles the buggy R4600 v1.x + * - a version which handles the buggy R4600 v2.0 + * - Finally a last version without fancy cache games for the SC and MC + * versions of R4000 and R4400. + */ + +LEAF(r4k_clear_page32_d16) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_D, (a0) + sw zero, (a0) + sw zero, 4(a0) + sw zero, 8(a0) + sw zero, 12(a0) + addiu a0, 32 + cache Create_Dirty_Excl_D, -16(a0) + sw zero, -16(a0) + sw zero, -12(a0) + sw zero, -8(a0) + sw zero, -4(a0) + bne AT, a0, 1b + jr ra + END(r4k_clear_page32_d16) + +LEAF(r4k_clear_page32_d32) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_D, (a0) + sw zero, (a0) + sw zero, 4(a0) + sw zero, 8(a0) + sw zero, 12(a0) + addiu a0, 32 + sw zero, -16(a0) + sw zero, -12(a0) + sw zero, -8(a0) + sw zero, -4(a0) + bne AT, a0, 1b + jr ra + END(r4k_clear_page32_d32) + +LEAF(r4k_clear_page_d16) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_D, (a0) + sd zero, (a0) + sd zero, 8(a0) + cache Create_Dirty_Excl_D, 16(a0) + sd zero, 16(a0) + sd zero, 24(a0) + addiu a0, 64 + cache Create_Dirty_Excl_D, -32(a0) + sd zero, -32(a0) + sd zero, -24(a0) + cache Create_Dirty_Excl_D, -16(a0) + sd zero, -16(a0) + sd zero, -8(a0) + bne AT, a0, 1b + jr ra + END(r4k_clear_page_d16) + +LEAF(r4k_clear_page_d32) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_D, (a0) + sd zero, (a0) + sd zero, 8(a0) + sd zero, 16(a0) + sd zero, 24(a0) + addiu a0, 64 + cache Create_Dirty_Excl_D, -32(a0) + sd zero, -32(a0) + sd zero, -24(a0) + sd zero, -16(a0) + sd zero, -8(a0) + bne AT, a0, 1b + jr ra + END(r4k_clear_page_d32) + +/* + * This flavour of r4k_clear_page is for the R4600 V1.x. Cite from the + * IDT R4600 V1.7 errata: + * + * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, + * Hit_Invalidate_D and Create_Dirty_Excl_D should only be + * executed if there is no other dcache activity. If the dcache is + * accessed for another instruction immeidately preceding when these + * cache instructions are executing, it is possible that the dcache + * tag match outputs used by these cache instructions will be + * incorrect. These cache instructions should be preceded by at least + * four instructions that are not any kind of load or store + * instruction. + * + * This is not allowed: lw + * nop + * nop + * nop + * cache Hit_Writeback_Invalidate_D + * + * This is allowed: lw + * nop + * nop + * nop + * nop + * cache Hit_Writeback_Invalidate_D + */ + +LEAF(r4k_clear_page_r4600_v1) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: nop + nop + nop + nop + cache Create_Dirty_Excl_D, (a0) + sd zero, (a0) + sd zero, 8(a0) + sd zero, 16(a0) + sd zero, 24(a0) + addiu a0, 64 + nop + nop + nop + cache Create_Dirty_Excl_D, -32(a0) + sd zero, -32(a0) + sd zero, -24(a0) + sd zero, -16(a0) + sd zero, -8(a0) + bne AT, a0, 1b + jr ra + END(r4k_clear_page_r4600_v1) + +LEAF(r4k_clear_page_r4600_v2) + .set mips3 + mfc0 a1, CP0_STATUS + ori AT, a1, 1 + xori AT, 1 + mtc0 AT, CP0_STATUS + nop + nop + nop + + .set volatile + la AT, KSEG1 + lw zero, (AT) + .set novolatile + + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_D, (a0) + sd zero, (a0) + sd zero, 8(a0) + sd zero, 16(a0) + sd zero, 24(a0) + addiu a0, 64 + cache Create_Dirty_Excl_D, -32(a0) + sd zero, -32(a0) + sd zero, -24(a0) + sd zero, -16(a0) + sd zero, -8(a0) + bne AT, a0, 1b + + mfc0 AT, CP0_STATUS # local_irq_restore + andi a1, 1 + ori AT, 1 + xori AT, 1 + or a1, AT + mtc0 a1, CP0_STATUS + nop + nop + nop + + jr ra + END(r4k_clear_page_r4600_v2) + +/* + * The next 4 versions are optimized for all possible scache configurations + * of the SC / MC versions of R4000 and R4400 ... + * + * Todo: For even better performance we should have a routine optimized for + * every legal combination of dcache / scache linesize. When I (Ralf) tried + * this the kernel crashed shortly after mounting the root filesystem. CPU + * bug? Weirdo cache instruction semantics? + */ + +LEAF(r4k_clear_page_s16) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_SD, (a0) + sd zero, (a0) + sd zero, 8(a0) + cache Create_Dirty_Excl_SD, 16(a0) + sd zero, 16(a0) + sd zero, 24(a0) + addiu a0, 64 + cache Create_Dirty_Excl_SD, -32(a0) + sd zero, -32(a0) + sd zero, -24(a0) + cache Create_Dirty_Excl_SD, -16(a0) + sd zero, -16(a0) + sd zero, -8(a0) + bne AT, a0, 1b + jr ra + END(r4k_clear_page_s16) + +LEAF(r4k_clear_page_s32) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_SD, (a0) + sd zero, (a0) + sd zero, 8(a0) + sd zero, 16(a0) + sd zero, 24(a0) + addiu a0, 64 + cache Create_Dirty_Excl_SD, -32(a0) + sd zero, -32(a0) + sd zero, -24(a0) + sd zero, -16(a0) + sd zero, -8(a0) + bne AT, a0, 1b + jr ra + END(r4k_clear_page_s32) + +LEAF(r4k_clear_page_s64) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_SD, (a0) + sd zero, (a0) + sd zero, 8(a0) + sd zero, 16(a0) + sd zero, 24(a0) + addiu a0, 64 + sd zero, -32(a0) + sd zero, -24(a0) + sd zero, -16(a0) + sd zero, -8(a0) + bne AT, a0, 1b + jr ra + END(r4k_clear_page_s64) + +LEAF(r4k_clear_page_s128) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_SD, (a0) + sd zero, (a0) + sd zero, 8(a0) + sd zero, 16(a0) + sd zero, 24(a0) + sd zero, 32(a0) + sd zero, 40(a0) + sd zero, 48(a0) + sd zero, 56(a0) + addiu a0, 128 + sd zero, -64(a0) + sd zero, -56(a0) + sd zero, -48(a0) + sd zero, -40(a0) + sd zero, -32(a0) + sd zero, -24(a0) + sd zero, -16(a0) + sd zero, -8(a0) + bne AT, a0, 1b + jr ra + END(r4k_clear_page_s128) + +/* + * This is suboptimal for 32-bit kernels; we assume that R10000 is only used + * with 64-bit kernels. The prefetch offsets have been experimentally tuned + * an Origin 200. + */ +LEAF(andes_clear_page) + .set mips4 + LONG_ADDIU AT, a0, _PAGE_SIZE +1: pref 7, 512(a0) + sd zero, 0*SZREG(a0) + sd zero, 1*SZREG(a0) + sd zero, 2*SZREG(a0) + sd zero, 3*SZREG(a0) + LONG_ADDIU a0, a0, 8*SZREG + sd zero, -4*SZREG(a0) + sd zero, -3*SZREG(a0) + sd zero, -2*SZREG(a0) + sd zero, -1*SZREG(a0) + bne AT, a0, 1b + j ra + END(andes_clear_page) + .set mips0 + +/* + * This is still inefficient. We only can do better if we know the + * virtual address where the copy will be accessed. + */ + +LEAF(r4k_copy_page_d16) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_D, (a0) + lw a3, (a1) + lw a2, 4(a1) + lw v1, 8(a1) + lw v0, 12(a1) + sw a3, (a0) + sw a2, 4(a0) + sw v1, 8(a0) + sw v0, 12(a0) + cache Create_Dirty_Excl_D, 16(a0) + lw a3, 16(a1) + lw a2, 20(a1) + lw v1, 24(a1) + lw v0, 28(a1) + sw a3, 16(a0) + sw a2, 20(a0) + sw v1, 24(a0) + sw v0, 28(a0) + cache Create_Dirty_Excl_D, 32(a0) + addiu a0, 64 + addiu a1, 64 + lw a3, -32(a1) + lw a2, -28(a1) + lw v1, -24(a1) + lw v0, -20(a1) + sw a3, -32(a0) + sw a2, -28(a0) + sw v1, -24(a0) + sw v0, -20(a0) + cache Create_Dirty_Excl_D, -16(a0) + lw a3, -16(a1) + lw a2, -12(a1) + lw v1, -8(a1) + lw v0, -4(a1) + sw a3, -16(a0) + sw a2, -12(a0) + sw v1, -8(a0) + sw v0, -4(a0) + bne AT, a0, 1b + jr ra + END(r4k_copy_page_d16) + +LEAF(r4k_copy_page_d32) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_D, (a0) + lw a3, (a1) + lw a2, 4(a1) + lw v1, 8(a1) + lw v0, 12(a1) + sw a3, (a0) + sw a2, 4(a0) + sw v1, 8(a0) + sw v0, 12(a0) + lw a3, 16(a1) + lw a2, 20(a1) + lw v1, 24(a1) + lw v0, 28(a1) + sw a3, 16(a0) + sw a2, 20(a0) + sw v1, 24(a0) + sw v0, 28(a0) + cache Create_Dirty_Excl_D, 32(a0) + addiu a0, 64 + addiu a1, 64 + lw a3, -32(a1) + lw a2, -28(a1) + lw v1, -24(a1) + lw v0, -20(a1) + sw a3, -32(a0) + sw a2, -28(a0) + sw v1, -24(a0) + sw v0, -20(a0) + lw a3, -16(a1) + lw a2, -12(a1) + lw v1, -8(a1) + lw v0, -4(a1) + sw a3, -16(a0) + sw a2, -12(a0) + sw v1, -8(a0) + sw v0, -4(a0) + bne AT, a0, 1b + jr ra + END(r4k_copy_page_d32) + +/* + * Again a special version for the R4600 V1.x + */ + +LEAF(r4k_copy_page_r4600_v1) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: nop + nop + nop + nop + cache Create_Dirty_Excl_D, (a0) + lw a3, (a1) + lw a2, 4(a1) + lw v1, 8(a1) + lw v0, 12(a1) + sw a3, (a0) + sw a2, 4(a0) + sw v1, 8(a0) + sw v0, 12(a0) + lw a3, 16(a1) + lw a2, 20(a1) + lw v1, 24(a1) + lw v0, 28(a1) + sw a3, 16(a0) + sw a2, 20(a0) + sw v1, 24(a0) + sw v0, 28(a0) + nop + nop + nop + nop + cache Create_Dirty_Excl_D, 32(a0) + addiu a0, 64 + addiu a1, 64 + lw a3, -32(a1) + lw a2, -28(a1) + lw v1, -24(a1) + lw v0, -20(a1) + sw a3, -32(a0) + sw a2, -28(a0) + sw v1, -24(a0) + sw v0, -20(a0) + lw a3, -16(a1) + lw a2, -12(a1) + lw v1, -8(a1) + lw v0, -4(a1) + sw a3, -16(a0) + sw a2, -12(a0) + sw v1, -8(a0) + sw v0, -4(a0) + bne AT, a0, 1b + jr ra + END(r4k_copy_page_r4600_v1) + +LEAF(r4k_copy_page_r4600_v2) + .set mips3 + mfc0 v1, CP0_STATUS + ori AT, v1, 1 + xori AT, 1 + + mtc0 AT, CP0_STATUS + nop + nop + nop + + addiu AT, a0, _PAGE_SIZE +1: nop + nop + nop + nop + cache Create_Dirty_Excl_D, (a0) + lw t1, (a1) + lw t0, 4(a1) + lw a3, 8(a1) + lw a2, 12(a1) + sw t1, (a0) + sw t0, 4(a0) + sw a3, 8(a0) + sw a2, 12(a0) + lw t1, 16(a1) + lw t0, 20(a1) + lw a3, 24(a1) + lw a2, 28(a1) + sw t1, 16(a0) + sw t0, 20(a0) + sw a3, 24(a0) + sw a2, 28(a0) + nop + nop + nop + nop + cache Create_Dirty_Excl_D, 32(a0) + addiu a0, 64 + addiu a1, 64 + lw t1, -32(a1) + lw t0, -28(a1) + lw a3, -24(a1) + lw a2, -20(a1) + sw t1, -32(a0) + sw t0, -28(a0) + sw a3, -24(a0) + sw a2, -20(a0) + lw t1, -16(a1) + lw t0, -12(a1) + lw a3, -8(a1) + lw a2, -4(a1) + sw t1, -16(a0) + sw t0, -12(a0) + sw a3, -8(a0) + sw a2, -4(a0) + bne AT, a0, 1b + + mfc0 AT, CP0_STATUS # local_irq_restore + andi v1, 1 + ori AT, 1 + xori AT, 1 + or v1, AT + mtc0 v1, CP0_STATUS + nop + nop + nop + jr ra + END(r4k_copy_page_r4600_v2) + +/* + * These are for R4000SC / R4400MC + */ + +LEAF(r4k_copy_page_s16) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_SD, (a0) + lw a3, (a1) + lw a2, 4(a1) + lw v1, 8(a1) + lw v0, 12(a1) + sw a3, (a0) + sw a2, 4(a0) + sw v1, 8(a0) + sw v0, 12(a0) + cache Create_Dirty_Excl_SD, 16(a0) + lw a3, 16(a1) + lw a2, 20(a1) + lw v1, 24(a1) + lw v0, 28(a1) + sw a3, 16(a0) + sw a2, 20(a0) + sw v1, 24(a0) + sw v0, 28(a0) + cache Create_Dirty_Excl_SD, 32(a0) + addiu a0, 64 + addiu a1, 64 + lw a3, -32(a1) + lw a2, -28(a1) + lw v1, -24(a1) + lw v0, -20(a1) + sw a3, -32(a0) + sw a2, -28(a0) + sw v1, -24(a0) + sw v0, -20(a0) + cache Create_Dirty_Excl_SD, -16(a0) + lw a3, -16(a1) + lw a2, -12(a1) + lw v1, -8(a1) + lw v0, -4(a1) + sw a3, -16(a0) + sw a2, -12(a0) + sw v1, -8(a0) + sw v0, -4(a0) + bne AT, a0, 1b + jr ra + END(r4k_copy_page_s16) + +LEAF(r4k_copy_page_s32) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_SD, (a0) + lw a3, (a1) + lw a2, 4(a1) + lw v1, 8(a1) + lw v0, 12(a1) + sw a3, (a0) + sw a2, 4(a0) + sw v1, 8(a0) + sw v0, 12(a0) + lw a3, 16(a1) + lw a2, 20(a1) + lw v1, 24(a1) + lw v0, 28(a1) + sw a3, 16(a0) + sw a2, 20(a0) + sw v1, 24(a0) + sw v0, 28(a0) + cache Create_Dirty_Excl_SD, 32(a0) + addiu a0, 64 + addiu a1, 64 + lw a3, -32(a1) + lw a2, -28(a1) + lw v1, -24(a1) + lw v0, -20(a1) + sw a3, -32(a0) + sw a2, -28(a0) + sw v1, -24(a0) + sw v0, -20(a0) + lw a3, -16(a1) + lw a2, -12(a1) + lw v1, -8(a1) + lw v0, -4(a1) + sw a3, -16(a0) + sw a2, -12(a0) + sw v1, -8(a0) + sw v0, -4(a0) + bne AT, a0, 1b + jr ra + END(r4k_copy_page_s32) + +LEAF(r4k_copy_page_s64) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_SD, (a0) + lw a3, (a1) + lw a2, 4(a1) + lw v1, 8(a1) + lw v0, 12(a1) + sw a3, (a0) + sw a2, 4(a0) + sw v1, 8(a0) + sw v0, 12(a0) + lw a3, 16(a1) + lw a2, 20(a1) + lw v1, 24(a1) + lw v0, 28(a1) + sw a3, 16(a0) + sw a2, 20(a0) + sw v1, 24(a0) + sw v0, 28(a0) + addiu a0, 64 + addiu a1, 64 + lw a3, -32(a1) + lw a2, -28(a1) + lw v1, -24(a1) + lw v0, -20(a1) + sw a3, -32(a0) + sw a2, -28(a0) + sw v1, -24(a0) + sw v0, -20(a0) + lw a3, -16(a1) + lw a2, -12(a1) + lw v1, -8(a1) + lw v0, -4(a1) + sw a3, -16(a0) + sw a2, -12(a0) + sw v1, -8(a0) + sw v0, -4(a0) + bne AT, a0, 1b + jr ra + END(r4k_copy_page_s64) + +LEAF(r4k_copy_page_s128) + .set mips3 + addiu AT, a0, _PAGE_SIZE +1: cache Create_Dirty_Excl_SD, (a0) + lw a3, (a1) + lw a2, 4(a1) + lw v1, 8(a1) + lw v0, 12(a1) + sw a3, (a0) + sw a2, 4(a0) + sw v1, 8(a0) + sw v0, 12(a0) + lw a3, 16(a1) + lw a2, 20(a1) + lw v1, 24(a1) + lw v0, 28(a1) + sw a3, 16(a0) + sw a2, 20(a0) + sw v1, 24(a0) + sw v0, 28(a0) + lw a3, 32(a1) + lw a2, 36(a1) + lw v1, 40(a1) + lw v0, 44(a1) + sw a3, 32(a0) + sw a2, 36(a0) + sw v1, 40(a0) + sw v0, 44(a0) + lw a3, 48(a1) + lw a2, 52(a1) + lw v1, 56(a1) + lw v0, 60(a1) + sw a3, 48(a0) + sw a2, 52(a0) + sw v1, 56(a0) + sw v0, 60(a0) + addiu a0, 128 + addiu a1, 128 + lw a3, -64(a1) + lw a2, -60(a1) + lw v1, -56(a1) + lw v0, -52(a1) + sw a3, -64(a0) + sw a2, -60(a0) + sw v1, -56(a0) + sw v0, -52(a0) + lw a3, -48(a1) + lw a2, -44(a1) + lw v1, -40(a1) + lw v0, -36(a1) + sw a3, -48(a0) + sw a2, -44(a0) + sw v1, -40(a0) + sw v0, -36(a0) + lw a3, -32(a1) + lw a2, -28(a1) + lw v1, -24(a1) + lw v0, -20(a1) + sw a3, -32(a0) + sw a2, -28(a0) + sw v1, -24(a0) + sw v0, -20(a0) + lw a3, -16(a1) + lw a2, -12(a1) + lw v1, -8(a1) + lw v0, -4(a1) + sw a3, -16(a0) + sw a2, -12(a0) + sw v1, -8(a0) + sw v0, -4(a0) + bne AT, a0, 1b + jr ra + END(r4k_copy_page_s128) + + + .text + .set mips4 + .set noat + + +/* + * This is suboptimal for 32-bit kernels; we assume that R10000 is only used + * with 64-bit kernels. The prefetch offsets have been experimentally tuned + * an Origin 200. + */ +LEAF(andes_copy_page) + .set mips4 + LONG_ADDIU AT, a0, _PAGE_SIZE +1: pref 0, 2*128(a1) + pref 1, 2*128(a0) + LONG_L a3, 0*SZREG(a1) + LONG_L a2, 1*SZREG(a1) + LONG_L v1, 2*SZREG(a1) + LONG_L v0, 3*SZREG(a1) + LONG_S a3, 0*SZREG(a0) + LONG_S a2, 1*SZREG(a0) + LONG_S v1, 2*SZREG(a0) + LONG_S v0, 3*SZREG(a0) + LONG_ADDIU a0, a0, 8*SZREG + LONG_ADDIU a1, a1, 8*SZREG + LONG_L a3, -4*SZREG(a1) + LONG_L a2, -3*SZREG(a1) + LONG_L v1, -2*SZREG(a1) + LONG_L v0, -1*SZREG(a1) + LONG_S a3, -4*SZREG(a0) + LONG_S a2, -3*SZREG(a0) + LONG_S v1, -2*SZREG(a0) + LONG_S v0, -1*SZREG(a0) + bne AT, a0,1b + j ra + END(andes_copy_page) + .set mips0 + +/* This one still needs to receive cache optimizations */ +LEAF(pgd_init) + .set mips0 + addiu AT, a0, PGD_SIZE / 2 + la v0, invalid_pte_table +1: sw v0, (a0) + sw v0, 4(a0) + sw v0, 8(a0) + sw v0, 12(a0) + addiu a0, 32 + sw v0, -16(a0) + sw v0, -12(a0) + sw v0, -8(a0) + sw v0, -4(a0) + bne AT, a0, 1b + jr ra + END(pgd_init) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/pg-sb1.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,132 @@ +/* + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 2000 Sibyte + * + * Written by Justin Carlson (carlson@sibyte.com) + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include +#include + +#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS +#define SB1_PREF_LOAD_STREAMED_HINT "0" +#define SB1_PREF_STORE_STREAMED_HINT "1" +#else +#define SB1_PREF_LOAD_STREAMED_HINT "4" +#define SB1_PREF_STORE_STREAMED_HINT "5" +#endif + +/* These are the functions hooked by the memory management function pointers */ +void sb1_clear_page(void *page) +{ + /* + * JDCXXX - This should be bottlenecked by the write buffer, but these + * things tend to be mildly unpredictable...should check this on the + * performance model + * + * We prefetch 4 lines ahead. We're also "cheating" slightly here... + * since we know we're on an SB1, we force the assembler to take + * 64-bit operands to speed things up + */ + __asm__ __volatile__( + ".set push \n" + ".set noreorder \n" + ".set noat \n" + ".set mips4 \n" + " addiu $1, %0, %2 \n" /* Calculate the end of the page to clear */ +#ifdef CONFIG_CPU_HAS_PREFETCH + " pref " SB1_PREF_STORE_STREAMED_HINT ", 0(%0) \n" /* Prefetch the first 4 lines */ + " pref " SB1_PREF_STORE_STREAMED_HINT ", 32(%0) \n" + " pref " SB1_PREF_STORE_STREAMED_HINT ", 64(%0) \n" + " pref " SB1_PREF_STORE_STREAMED_HINT ", 96(%0) \n" +#endif + "1: sd $0, 0(%0) \n" /* Throw out a cacheline of 0's */ + " sd $0, 8(%0) \n" + " sd $0, 16(%0) \n" + " sd $0, 24(%0) \n" +#ifdef CONFIG_CPU_HAS_PREFETCH + " pref " SB1_PREF_STORE_STREAMED_HINT ",128(%0) \n" /* Prefetch 4 lines ahead */ +#endif + " bne $1, %0, 1b \n" + " addiu %0, %0, 32 \n" /* Next cacheline (This instruction better be short piped!) */ + ".set pop \n" + : "=r" (page) + : "0" (page), "I" (PAGE_SIZE-32) + : "memory"); + +} + +void sb1_copy_page(void *to, void *from) +{ + + /* + * This should be optimized in assembly...can't use ld/sd, though, + * because the top 32 bits could be nuked if we took an interrupt + * during the routine. And this is not a good place to be cli()'ing + * + * The pref's used here are using "streaming" hints, which cause the + * copied data to be kicked out of the cache sooner. A page copy often + * ends up copying a lot more data than is commonly used, so this seems + * to make sense in terms of reducing cache pollution, but I've no real + * performance data to back this up + */ + + __asm__ __volatile__( + ".set push \n" + ".set noreorder \n" + ".set noat \n" + ".set mips4 \n" + " addiu $1, %0, %4 \n" /* Calculate the end of the page to copy */ +#ifdef CONFIG_CPU_HAS_PREFETCH + " pref " SB1_PREF_LOAD_STREAMED_HINT ", 0(%0) \n" /* Prefetch the first 3 lines */ + " pref " SB1_PREF_STORE_STREAMED_HINT ", 0(%1) \n" + " pref " SB1_PREF_LOAD_STREAMED_HINT ", 32(%0) \n" + " pref " SB1_PREF_STORE_STREAMED_HINT ", 32(%1) \n" + " pref " SB1_PREF_LOAD_STREAMED_HINT ", 64(%0) \n" + " pref " SB1_PREF_STORE_STREAMED_HINT ", 64(%1) \n" +#endif + "1: lw $2, 0(%0) \n" /* Block copy a cacheline */ + " lw $3, 4(%0) \n" + " lw $4, 8(%0) \n" + " lw $5, 12(%0) \n" + " lw $6, 16(%0) \n" + " lw $7, 20(%0) \n" + " lw $8, 24(%0) \n" + " lw $9, 28(%0) \n" +#ifdef CONFIG_CPU_HAS_PREFETCH + " pref " SB1_PREF_LOAD_STREAMED_HINT ", 96(%0) \n" /* Prefetch ahead */ + " pref " SB1_PREF_STORE_STREAMED_HINT ", 96(%1) \n" +#endif + " sw $2, 0(%1) \n" + " sw $3, 4(%1) \n" + " sw $4, 8(%1) \n" + " sw $5, 12(%1) \n" + " sw $6, 16(%1) \n" + " sw $7, 20(%1) \n" + " sw $8, 24(%1) \n" + " sw $9, 28(%1) \n" + " addiu %1, %1, 32 \n" /* Next cacheline */ + " nop \n" /* Force next add to short pipe */ + " nop \n" /* Force next add to short pipe */ + " bne $1, %0, 1b \n" + " addiu %0, %0, 32 \n" /* Next cacheline */ + ".set pop \n" + : "=r" (to), "=r" (from) + : "0" (from), "1" (to), "I" (PAGE_SIZE-32) + : "$2","$3","$4","$5","$6","$7","$8","$9","memory"); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/pgtable.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,33 @@ +#include +#include +#include + +void show_mem(void) +{ + int pfn, total = 0, reserved = 0; + int shared = 0, cached = 0; + int highmem = 0; + struct page *page; + + printk("Mem-info:\n"); + show_free_areas(); + printk("Free swap: %6dkB\n",nr_swap_pages<<(PAGE_SHIFT-10)); + pfn = max_mapnr; + while (pfn-- > 0) { + page = pfn_to_page(pfn); + total++; + if (PageHighMem(page)) + highmem++; + if (PageReserved(page)) + reserved++; + else if (PageSwapCache(page)) + cached++; + else if (page_count(page)) + shared += page_count(page) - 1; + } + printk("%d pages of RAM\n", total); + printk("%d pages of HIGHMEM\n",highmem); + printk("%d reserved pages\n",reserved); + printk("%d pages shared\n",shared); + printk("%d pages swap cached\n",cached); +} --- linux-2.5.73/arch/mips/mm/r2300.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,804 +0,0 @@ -/* - * r2300.c: R2000 and R3000 specific mmu/cache code. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * - * with a lot of changes to make this thing work for R3000s - * Tx39XX R4k style caches added. HK - * Copyright (C) 1998, 1999, 2000 Harald Koerfgen - * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov - */ -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * According to the paper written by D. Miller about Linux cache & TLB - * flush implementation, DMA/Driver coherence should be done at the - * driver layer. Thus, normally, we don't need flush dcache for R3000. - * Define this if driver does not handle cache consistency during DMA ops. - */ - -/* For R3000 cores with R4000 style caches */ -static unsigned long icache_size, dcache_size; /* Size in bytes */ -static unsigned long icache_lsize, dcache_lsize; /* Size in bytes */ -static unsigned long scache_size; - -#include -#include - -#undef DEBUG_TLB -#undef DEBUG_CACHE - -/* page functions */ -void r3k_clear_page(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "addiu\t$1,%0,%2\n" - "1:\tsw\t$0,(%0)\n\t" - "sw\t$0,4(%0)\n\t" - "sw\t$0,8(%0)\n\t" - "sw\t$0,12(%0)\n\t" - "addiu\t%0,32\n\t" - "sw\t$0,-16(%0)\n\t" - "sw\t$0,-12(%0)\n\t" - "sw\t$0,-8(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sw\t$0,-4(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE) - :"$1","memory"); -} - -static void r3k_copy_page(void * to, void * from) -{ - unsigned long dummy1, dummy2; - unsigned long reg1, reg2, reg3, reg4; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "addiu\t$1,%0,%8\n" - "1:\tlw\t%2,(%1)\n\t" - "lw\t%3,4(%1)\n\t" - "lw\t%4,8(%1)\n\t" - "lw\t%5,12(%1)\n\t" - "sw\t%2,(%0)\n\t" - "sw\t%3,4(%0)\n\t" - "sw\t%4,8(%0)\n\t" - "sw\t%5,12(%0)\n\t" - "lw\t%2,16(%1)\n\t" - "lw\t%3,20(%1)\n\t" - "lw\t%4,24(%1)\n\t" - "lw\t%5,28(%1)\n\t" - "sw\t%2,16(%0)\n\t" - "sw\t%3,20(%0)\n\t" - "sw\t%4,24(%0)\n\t" - "sw\t%5,28(%0)\n\t" - "addiu\t%0,64\n\t" - "addiu\t%1,64\n\t" - "lw\t%2,-32(%1)\n\t" - "lw\t%3,-28(%1)\n\t" - "lw\t%4,-24(%1)\n\t" - "lw\t%5,-20(%1)\n\t" - "sw\t%2,-32(%0)\n\t" - "sw\t%3,-28(%0)\n\t" - "sw\t%4,-24(%0)\n\t" - "sw\t%5,-20(%0)\n\t" - "lw\t%2,-16(%1)\n\t" - "lw\t%3,-12(%1)\n\t" - "lw\t%4,-8(%1)\n\t" - "lw\t%5,-4(%1)\n\t" - "sw\t%2,-16(%0)\n\t" - "sw\t%3,-12(%0)\n\t" - "sw\t%4,-8(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sw\t%5,-4(%0)\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), - "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) - :"0" (to), "1" (from), - "I" (PAGE_SIZE)); -} - -unsigned long __init r3k_cache_size(unsigned long ca_flags) -{ - unsigned long flags, status, dummy, size; - volatile unsigned long *p; - - p = (volatile unsigned long *) KSEG0; - - flags = read_32bit_cp0_register(CP0_STATUS); - - /* isolate cache space */ - write_32bit_cp0_register(CP0_STATUS, (ca_flags|flags)&~ST0_IEC); - - *p = 0xa5a55a5a; - dummy = *p; - status = read_32bit_cp0_register(CP0_STATUS); - - if (dummy != 0xa5a55a5a || (status & ST0_CM)) { - size = 0; - } else { - for (size = 128; size <= 0x40000; size <<= 1) - *(p + size) = 0; - *p = -1; - for (size = 128; - (size <= 0x40000) && (*(p + size) == 0); - size <<= 1) - ; - if (size > 0x40000) - size = 0; - } - - write_32bit_cp0_register(CP0_STATUS, flags); - - return size * sizeof(*p); -} - -unsigned long __init r3k_cache_lsize(unsigned long ca_flags) -{ - unsigned long flags, status, lsize, i, j; - volatile unsigned long *p; - - p = (volatile unsigned long *) KSEG0; - - flags = read_32bit_cp0_register(CP0_STATUS); - - /* isolate cache space */ - write_32bit_cp0_register(CP0_STATUS, (ca_flags|flags)&~ST0_IEC); - - for (i = 0; i < 128; i++) - *(p + i) = 0; - *(volatile unsigned char *)p = 0; - for (lsize = 1; lsize < 128; lsize <<= 1) { - *(p + lsize); - status = read_32bit_cp0_register(CP0_STATUS); - if (!(status & ST0_CM)) - break; - } - for (i = 0; i < 128; i += lsize) - *(volatile unsigned char *)(p + i) = 0; - - write_32bit_cp0_register(CP0_STATUS, flags); - - return lsize * sizeof(*p); -} - -static void __init r3k_probe_cache(void) -{ - dcache_size = r3k_cache_size(ST0_ISC); - if (dcache_size) - dcache_lsize = r3k_cache_lsize(ST0_ISC); - - - icache_size = r3k_cache_size(ST0_ISC|ST0_SWC); - if (icache_size) - icache_lsize = r3k_cache_lsize(ST0_ISC|ST0_SWC); -} - -static void r3k_flush_icache_range(unsigned long start, unsigned long end) -{ - unsigned long size, i, flags; - volatile unsigned char *p = (char *)start; - - size = end - start; - if (size > icache_size) - size = icache_size; - - flags = read_32bit_cp0_register(CP0_STATUS); - - /* isolate cache space */ - write_32bit_cp0_register(CP0_STATUS, (ST0_ISC|ST0_SWC|flags)&~ST0_IEC); - - for (i = 0; i < size; i += 0x080) { - asm ( "sb\t$0,0x000(%0)\n\t" - "sb\t$0,0x004(%0)\n\t" - "sb\t$0,0x008(%0)\n\t" - "sb\t$0,0x00c(%0)\n\t" - "sb\t$0,0x010(%0)\n\t" - "sb\t$0,0x014(%0)\n\t" - "sb\t$0,0x018(%0)\n\t" - "sb\t$0,0x01c(%0)\n\t" - "sb\t$0,0x020(%0)\n\t" - "sb\t$0,0x024(%0)\n\t" - "sb\t$0,0x028(%0)\n\t" - "sb\t$0,0x02c(%0)\n\t" - "sb\t$0,0x030(%0)\n\t" - "sb\t$0,0x034(%0)\n\t" - "sb\t$0,0x038(%0)\n\t" - "sb\t$0,0x03c(%0)\n\t" - "sb\t$0,0x040(%0)\n\t" - "sb\t$0,0x044(%0)\n\t" - "sb\t$0,0x048(%0)\n\t" - "sb\t$0,0x04c(%0)\n\t" - "sb\t$0,0x050(%0)\n\t" - "sb\t$0,0x054(%0)\n\t" - "sb\t$0,0x058(%0)\n\t" - "sb\t$0,0x05c(%0)\n\t" - "sb\t$0,0x060(%0)\n\t" - "sb\t$0,0x064(%0)\n\t" - "sb\t$0,0x068(%0)\n\t" - "sb\t$0,0x06c(%0)\n\t" - "sb\t$0,0x070(%0)\n\t" - "sb\t$0,0x074(%0)\n\t" - "sb\t$0,0x078(%0)\n\t" - "sb\t$0,0x07c(%0)\n\t" - : : "r" (p) ); - p += 0x080; - } - - write_32bit_cp0_register(CP0_STATUS,flags); -} - -static void r3k_flush_dcache_range(unsigned long start, unsigned long end) -{ - unsigned long size, i, flags; - volatile unsigned char *p = (char *)start; - - size = end - start; - if (size > dcache_size) - size = dcache_size; - - flags = read_32bit_cp0_register(CP0_STATUS); - - /* isolate cache space */ - write_32bit_cp0_register(CP0_STATUS, (ST0_ISC|flags)&~ST0_IEC); - - for (i = 0; i < size; i += 0x080) { - asm ( "sb\t$0,0x000(%0)\n\t" - "sb\t$0,0x004(%0)\n\t" - "sb\t$0,0x008(%0)\n\t" - "sb\t$0,0x00c(%0)\n\t" - "sb\t$0,0x010(%0)\n\t" - "sb\t$0,0x014(%0)\n\t" - "sb\t$0,0x018(%0)\n\t" - "sb\t$0,0x01c(%0)\n\t" - "sb\t$0,0x020(%0)\n\t" - "sb\t$0,0x024(%0)\n\t" - "sb\t$0,0x028(%0)\n\t" - "sb\t$0,0x02c(%0)\n\t" - "sb\t$0,0x030(%0)\n\t" - "sb\t$0,0x034(%0)\n\t" - "sb\t$0,0x038(%0)\n\t" - "sb\t$0,0x03c(%0)\n\t" - "sb\t$0,0x040(%0)\n\t" - "sb\t$0,0x044(%0)\n\t" - "sb\t$0,0x048(%0)\n\t" - "sb\t$0,0x04c(%0)\n\t" - "sb\t$0,0x050(%0)\n\t" - "sb\t$0,0x054(%0)\n\t" - "sb\t$0,0x058(%0)\n\t" - "sb\t$0,0x05c(%0)\n\t" - "sb\t$0,0x060(%0)\n\t" - "sb\t$0,0x064(%0)\n\t" - "sb\t$0,0x068(%0)\n\t" - "sb\t$0,0x06c(%0)\n\t" - "sb\t$0,0x070(%0)\n\t" - "sb\t$0,0x074(%0)\n\t" - "sb\t$0,0x078(%0)\n\t" - "sb\t$0,0x07c(%0)\n\t" - : : "r" (p) ); - p += 0x080; - } - - write_32bit_cp0_register(CP0_STATUS,flags); -} - -static inline unsigned long get_phys_page (unsigned long addr, - struct mm_struct *mm) -{ - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - unsigned long physpage; - - pgd = pgd_offset(mm, addr); - pmd = pmd_offset(pgd, addr); - pte = pte_offset(pmd, addr); - - if ((physpage = pte_val(*pte)) & _PAGE_VALID) - return KSEG0ADDR(physpage & PAGE_MASK); - - return 0; -} - -static inline void r3k_flush_cache_all(void) -{ - r3k_flush_icache_range(KSEG0, KSEG0 + icache_size); -} - -static void r3k_flush_cache_mm(struct mm_struct *mm) -{ - if (mm->context != 0) { - -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r3k_flush_cache_all(); - } -} - -static void r3k_flush_cache_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - - if (mm->context == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (mm->context != current->active_mm->context) { - flush_cache_all(); - } else { - unsigned long flags, physpage; - - save_and_cli(flags); - while (start < end) { - if ((physpage = get_phys_page(start, mm))) - r3k_flush_icache_range(physpage, - physpage + PAGE_SIZE); - start += PAGE_SIZE; - } - restore_flags(flags); - } -} - -static void r3k_flush_cache_page(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - - if (mm->context == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - if (vma->vm_flags & VM_EXEC) { - unsigned long physpage; - - if ((physpage = get_phys_page(page, vma->vm_mm))) - r3k_flush_icache_range(physpage, physpage + PAGE_SIZE); - } -} - -static void r3k_flush_page_to_ram(struct page * page) -{ - /* - * Nothing to be done - */ -} - -static void r3k_flush_icache_page(struct vm_area_struct *vma, struct page *page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long physpage; - - if (mm->context == 0) - return; - - if (!(vma->vm_flags & VM_EXEC)) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - - physpage = (unsigned long) page_address(page); - if (physpage) - r3k_flush_icache_range(physpage, physpage + PAGE_SIZE); -} - -static void r3k_flush_cache_sigtramp(unsigned long addr) -{ - unsigned long flags; - -#ifdef DEBUG_CACHE - printk("csigtramp[%08lx]", addr); -#endif - - flags = read_32bit_cp0_register(CP0_STATUS); - - write_32bit_cp0_register(CP0_STATUS, flags&~ST0_IEC); - - /* Fill the TLB to avoid an exception with caches isolated. */ - asm ( "lw\t$0,0x000(%0)\n\t" - "lw\t$0,0x004(%0)\n\t" - : : "r" (addr) ); - - write_32bit_cp0_register(CP0_STATUS, (ST0_ISC|ST0_SWC|flags)&~ST0_IEC); - - asm ( "sb\t$0,0x000(%0)\n\t" - "sb\t$0,0x004(%0)\n\t" - : : "r" (addr) ); - - write_32bit_cp0_register(CP0_STATUS, flags); -} - -static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size) -{ - wbflush(); - r3k_flush_dcache_range(start, start + size); -} - -/* TLB operations. */ -void flush_tlb_all(void) -{ - unsigned long flags; - unsigned long old_ctx; - int entry; - -#ifdef DEBUG_TLB - printk("[tlball]"); -#endif - - save_and_cli(flags); - old_ctx = (get_entryhi() & 0xfc0); - write_32bit_cp0_register(CP0_ENTRYLO0, 0); - for (entry = 8; entry < mips_cpu.tlbsize; entry++) { - write_32bit_cp0_register(CP0_INDEX, entry << 8); - write_32bit_cp0_register(CP0_ENTRYHI, ((entry | 0x80000) << 12)); - __asm__ __volatile__("tlbwi"); - } - set_entryhi(old_ctx); - restore_flags(flags); -} - -void flush_tlb_mm(struct mm_struct *mm) -{ - if (mm->context != 0) { - unsigned long flags; - -#ifdef DEBUG_TLB - printk("[tlbmm<%lu>]", (unsigned long) mm->context); -#endif - save_and_cli(flags); - get_new_mmu_context(mm, asid_cache); - if (mm == current->active_mm) - set_entryhi(mm->context & 0xfc0); - restore_flags(flags); - } -} - -void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - - if (mm->context != 0) { - unsigned long flags; - int size; - -#ifdef DEBUG_TLB - printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", - (mm->context & 0xfc0), start, end); -#endif - save_and_cli(flags); - size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - if(size <= mips_cpu.tlbsize) { - int oldpid = (get_entryhi() & 0xfc0); - int newpid = (mm->context & 0xfc0); - - start &= PAGE_MASK; - end += (PAGE_SIZE - 1); - end &= PAGE_MASK; - while(start < end) { - int idx; - - set_entryhi(start | newpid); - start += PAGE_SIZE; - tlb_probe(); - idx = get_index(); - set_entrylo0(0); - set_entryhi(KSEG0); - if(idx < 0) - continue; - tlb_write_indexed(); - } - set_entryhi(oldpid); - } else { - get_new_mmu_context(mm, asid_cache); - if (mm == current->active_mm) - set_entryhi(mm->context & 0xfc0); - } - restore_flags(flags); - } -} - -void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) -{ - if(vma->vm_mm->context != 0) { - unsigned long flags; - int oldpid, newpid, idx; - -#ifdef DEBUG_TLB - printk("[tlbpage<%lu,0x%08lx>]", vma->vm_mm->context, page); -#endif - newpid = (vma->vm_mm->context & 0xfc0); - page &= PAGE_MASK; - save_and_cli(flags); - oldpid = (get_entryhi() & 0xfc0); - set_entryhi(page | newpid); - tlb_probe(); - idx = get_index(); - set_entrylo0(0); - set_entryhi(KSEG0); - if(idx < 0) - goto finish; - tlb_write_indexed(); - -finish: - set_entryhi(oldpid); - restore_flags(flags); - } -} - -/* - * Initialize new page directory with pointers to invalid ptes - */ -void pgd_init(unsigned long page) -{ - unsigned long dummy1, dummy2; - - /* - * The plain and boring version for the R3000. No cache flushing - * stuff is implemented since the R3000 has physical caches. - */ - __asm__ __volatile__( - ".set\tnoreorder\n" - "1:\tsw\t%2,(%0)\n\t" - "sw\t%2,4(%0)\n\t" - "sw\t%2,8(%0)\n\t" - "sw\t%2,12(%0)\n\t" - "sw\t%2,16(%0)\n\t" - "sw\t%2,20(%0)\n\t" - "sw\t%2,24(%0)\n\t" - "sw\t%2,28(%0)\n\t" - "subu\t%1,1\n\t" - "bnez\t%1,1b\n\t" - "addiu\t%0,32\n\t" - ".set\treorder" - :"=r" (dummy1), - "=r" (dummy2) - :"r" ((unsigned long) invalid_pte_table), - "0" (page), - "1" (PAGE_SIZE/(sizeof(pmd_t)*8))); -} - -void update_mmu_cache(struct vm_area_struct * vma, unsigned long address, - pte_t pte) -{ - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - int idx, pid; - - /* - * Handle debugger faulting in for debugee. - */ - if (current->active_mm != vma->vm_mm) - return; - - pid = get_entryhi() & 0xfc0; - -#ifdef DEBUG_TLB - if((pid != (vma->vm_mm->context & 0xfc0)) || (vma->vm_mm->context == 0)) { - printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%lu tlbpid=%d\n", - (vma->vm_mm->context & 0xfc0), pid); - } -#endif - - save_and_cli(flags); - address &= PAGE_MASK; - set_entryhi(address | (pid)); - pgdp = pgd_offset(vma->vm_mm, address); - tlb_probe(); - pmdp = pmd_offset(pgdp, address); - idx = get_index(); - ptep = pte_offset(pmdp, address); - set_entrylo0(pte_val(*ptep)); - set_entryhi(address | (pid)); - if(idx < 0) { - tlb_write_random(); -#if 0 - printk("[MISS]"); -#endif - } else { - tlb_write_indexed(); -#if 0 - printk("[HIT]"); -#endif - } - set_entryhi(pid); - restore_flags(flags); -} - -void show_regs(struct pt_regs * regs) -{ - /* - * Saved main processor registers - */ - printk("$0 : %08x %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", - 0, (unsigned long) regs->regs[1], (unsigned long) regs->regs[2], - (unsigned long) regs->regs[3], (unsigned long) regs->regs[4], - (unsigned long) regs->regs[5], (unsigned long) regs->regs[6], - (unsigned long) regs->regs[7]); - printk("$8 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", - (unsigned long) regs->regs[8], (unsigned long) regs->regs[9], - (unsigned long) regs->regs[10], (unsigned long) regs->regs[11], - (unsigned long) regs->regs[12], (unsigned long) regs->regs[13], - (unsigned long) regs->regs[14], (unsigned long) regs->regs[15]); - printk("$16: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", - (unsigned long) regs->regs[16], (unsigned long) regs->regs[17], - (unsigned long) regs->regs[18], (unsigned long) regs->regs[19], - (unsigned long) regs->regs[20], (unsigned long) regs->regs[21], - (unsigned long) regs->regs[22], (unsigned long) regs->regs[23]); - printk("$24: %08lx %08lx %08lx %08lx %08lx %08lx\n", - (unsigned long) regs->regs[24], (unsigned long) regs->regs[25], - (unsigned long) regs->regs[28], (unsigned long) regs->regs[29], - (unsigned long) regs->regs[30], (unsigned long) regs->regs[31]); - - /* - * Saved cp0 registers - */ - printk("epc : %08lx %s\nStatus: %08x\nCause : %08x\n", - (unsigned long) regs->cp0_epc, - print_tainted(), - (unsigned int) regs->cp0_status, - (unsigned int) regs->cp0_cause); -} - -/* Todo: handle r4k-style TX39 TLB */ -void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask) -{ - unsigned long flags; - unsigned long old_ctx; - static unsigned long wired = 0; - - if (wired < 8) { - save_and_cli(flags); - old_ctx = get_entryhi() & 0xfc0; - set_entrylo0(entrylo0); - set_entryhi(entryhi); - set_index(wired); - wired++; - tlb_write_indexed(); - set_entryhi(old_ctx); - flush_tlb_all(); - restore_flags(flags); - } -} - -static void tx39_flush_icache_all(void ) -{ - - unsigned long start = KSEG0; - unsigned long end = (start + icache_size); - unsigned long dummy = 0; - - /* disable icache and stop streaming */ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - "mfc0\t%0,$3\n\t" - "xori\t%0,32\n\t" - "mtc0\t%0,$3\n\t" - "j\t1f\n\t" - "nop\n\t" - "1:\t.set\treorder\n\t" - : : "r"(dummy)); - - /* invalidate icache */ - while (start < end) { - cache16_unroll32(start,Index_Invalidate_I); - start += 0x200; - } - - /* enable icache */ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - "mfc0\t%0,$3\n\t" - "xori\t%0,32\n\t" - "mtc0\t%0,$3\n\t" - ".set\treorder\n\t" - : : "r"(dummy)); -} - -static __init void tx39_probe_cache(void) -{ - unsigned long config; - - config = read_32bit_cp0_register(CP0_CONF); - - icache_size = 1 << (10 + ((config >> 19) & 3)); - icache_lsize = 16; - - dcache_size = 1 << (10 + ((config >> 16) & 3)); - dcache_lsize = 4; -} - -void __init ld_mmu_r23000(void) -{ - unsigned long config; - - printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID)); - - _clear_page = r3k_clear_page; - _copy_page = r3k_copy_page; - - switch (mips_cpu.cputype) { - case CPU_R2000: - case CPU_R3000: - case CPU_R3000A: - case CPU_R3081: - case CPU_R3081E: - - r3k_probe_cache(); - - _flush_cache_all = r3k_flush_cache_all; - ___flush_cache_all = r3k_flush_cache_all; - _flush_cache_mm = r3k_flush_cache_mm; - _flush_cache_range = r3k_flush_cache_range; - _flush_cache_page = r3k_flush_cache_page; - _flush_cache_sigtramp = r3k_flush_cache_sigtramp; - _flush_page_to_ram = r3k_flush_page_to_ram; - _flush_icache_page = r3k_flush_icache_page; - _flush_icache_range = r3k_flush_icache_range; - - _dma_cache_wback_inv = r3k_dma_cache_wback_inv; - break; - - case CPU_TX3912: - case CPU_TX3922: - case CPU_TX3927: - - config=read_32bit_cp0_register(CP0_CONF); - config &= ~TX39_CONF_WBON; - write_32bit_cp0_register(CP0_CONF, config); - - tx39_probe_cache(); - - _flush_cache_all = tx39_flush_icache_all; - ___flush_cache_all = tx39_flush_icache_all; - _flush_cache_mm = tx39_flush_icache_all; - _flush_cache_range = tx39_flush_icache_all; - _flush_cache_page = tx39_flush_icache_all; - _flush_cache_sigtramp = tx39_flush_icache_all; - _flush_page_to_ram = r3k_flush_page_to_ram; - _flush_icache_page = tx39_flush_icache_all; - _flush_icache_range = tx39_flush_icache_all; - - _dma_cache_wback_inv = r3k_dma_cache_wback_inv; - - break; - } - - printk("Primary instruction cache %dkb, linesize %d bytes\n", - (int) (icache_size >> 10), (int) icache_lsize); - printk("Primary data cache %dkb, linesize %d bytes\n", - (int) (dcache_size >> 10), (int) dcache_lsize); - - flush_tlb_all(); -} --- linux-2.5.73/arch/mips/mm/r4xx0.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,2712 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * r4xx0.c: R4000 processor variant specific MMU/Cache routines. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org - * - * To do: - * - * - this code is a overbloated pig - * - many of the bug workarounds are not efficient at all, but at - * least they are functional ... - */ -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -/* CP0 hazard avoidance. */ -#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ - "nop; nop; nop; nop; nop; nop;\n\t" \ - ".set reorder\n\t") - -/* Primary cache parameters. */ -static int icache_size, dcache_size; /* Size in bytes */ -static int ic_lsize, dc_lsize; /* LineSize in bytes */ - -/* Secondary cache (if present) parameters. */ -static unsigned int scache_size, sc_lsize; /* Again, in bytes */ - -#include -#include - -#undef DEBUG_CACHE - -/* - * Dummy cache handling routines for machines without boardcaches - */ -static void no_sc_noop(void) {} - -static struct bcache_ops no_sc_ops = { - (void *)no_sc_noop, (void *)no_sc_noop, - (void *)no_sc_noop, (void *)no_sc_noop -}; - -struct bcache_ops *bcops = &no_sc_ops; - -/* - * On processors with QED R4600 style two set assosicative cache - * this is the bit which selects the way in the cache for the - * indexed cachops. - */ -#define icache_waybit (icache_size >> 1) -#define dcache_waybit (dcache_size >> 1) - -/* - * Zero an entire page. Basically a simple unrolled loop should do the - * job but we want more performance by saving memory bus bandwidth. We - * have five flavours of the routine available for: - * - * - 16byte cachelines and no second level cache - * - 32byte cachelines second level cache - * - a version which handles the buggy R4600 v1.x - * - a version which handles the buggy R4600 v2.0 - * - Finally a last version without fancy cache games for the SC and MC - * versions of R4000 and R4400. - */ - -static void r4k_clear_page_d16(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "cache\t%3,16(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "cache\t%3,-32(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "cache\t%3,-16(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D) - :"$1","memory"); -} - -static void r4k_clear_page_d32(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "cache\t%3,-32(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D) - :"$1","memory"); -} - - -/* - * This flavour of r4k_clear_page is for the R4600 V1.x. Cite from the - * IDT R4600 V1.7 errata: - * - * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, - * Hit_Invalidate_D and Create_Dirty_Excl_D should only be - * executed if there is no other dcache activity. If the dcache is - * accessed for another instruction immeidately preceding when these - * cache instructions are executing, it is possible that the dcache - * tag match outputs used by these cache instructions will be - * incorrect. These cache instructions should be preceded by at least - * four instructions that are not any kind of load or store - * instruction. - * - * This is not allowed: lw - * nop - * nop - * nop - * cache Hit_Writeback_Invalidate_D - * - * This is allowed: lw - * nop - * nop - * nop - * nop - * cache Hit_Writeback_Invalidate_D - */ -static void r4k_clear_page_r4600_v1(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tnop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "cache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "cache\t%3,-32(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D) - :"$1","memory"); -} - -/* - * And this one is for the R4600 V2.0 - */ -static void r4k_clear_page_r4600_v2(void * page) -{ - unsigned int flags; - - local_irq_save(flags); - *(volatile unsigned int *)KSEG1; - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "cache\t%3,-32(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D) - :"$1","memory"); - local_irq_restore(flags); -} - -/* - * The next 4 versions are optimized for all possible scache configurations - * of the SC / MC versions of R4000 and R4400 ... - * - * Todo: For even better performance we should have a routine optimized for - * every legal combination of dcache / scache linesize. When I (Ralf) tried - * this the kernel crashed shortly after mounting the root filesystem. CPU - * bug? Weirdo cache instruction semantics? - */ -static void r4k_clear_page_s16(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "cache\t%3,16(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "cache\t%3,-32(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "cache\t%3,-16(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_SD) - :"$1","memory"); -} - -static void r4k_clear_page_s32(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "cache\t%3,-32(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_SD) - :"$1","memory"); -} - -static void r4k_clear_page_s64(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_SD) - :"$1","memory"); -} - -static void r4k_clear_page_s128(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "sd\t$0,32(%0)\n\t" - "sd\t$0,40(%0)\n\t" - "sd\t$0,48(%0)\n\t" - "sd\t$0,56(%0)\n\t" - "daddiu\t%0,128\n\t" - "sd\t$0,-64(%0)\n\t" - "sd\t$0,-56(%0)\n\t" - "sd\t$0,-48(%0)\n\t" - "sd\t$0,-40(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_SD) - :"$1","memory"); -} - - -/* - * This is still inefficient. We only can do better if we know the - * virtual address where the copy will be accessed. - */ - -static void r4k_copy_page_d16(void * to, void * from) -{ - unsigned long dummy1, dummy2; - unsigned long reg1, reg2, reg3, reg4; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%8\n" - "1:\tcache\t%9,(%0)\n\t" - "lw\t%2,(%1)\n\t" - "lw\t%3,4(%1)\n\t" - "lw\t%4,8(%1)\n\t" - "lw\t%5,12(%1)\n\t" - "sw\t%2,(%0)\n\t" - "sw\t%3,4(%0)\n\t" - "sw\t%4,8(%0)\n\t" - "sw\t%5,12(%0)\n\t" - "cache\t%9,16(%0)\n\t" - "lw\t%2,16(%1)\n\t" - "lw\t%3,20(%1)\n\t" - "lw\t%4,24(%1)\n\t" - "lw\t%5,28(%1)\n\t" - "sw\t%2,16(%0)\n\t" - "sw\t%3,20(%0)\n\t" - "sw\t%4,24(%0)\n\t" - "sw\t%5,28(%0)\n\t" - "cache\t%9,32(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "lw\t%2,-32(%1)\n\t" - "lw\t%3,-28(%1)\n\t" - "lw\t%4,-24(%1)\n\t" - "lw\t%5,-20(%1)\n\t" - "sw\t%2,-32(%0)\n\t" - "sw\t%3,-28(%0)\n\t" - "sw\t%4,-24(%0)\n\t" - "sw\t%5,-20(%0)\n\t" - "cache\t%9,-16(%0)\n\t" - "lw\t%2,-16(%1)\n\t" - "lw\t%3,-12(%1)\n\t" - "lw\t%4,-8(%1)\n\t" - "lw\t%5,-4(%1)\n\t" - "sw\t%2,-16(%0)\n\t" - "sw\t%3,-12(%0)\n\t" - "sw\t%4,-8(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sw\t%5,-4(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), - "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) - :"0" (to), "1" (from), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D)); -} - -static void r4k_copy_page_d32(void * to, void * from) -{ - unsigned long dummy1, dummy2; - unsigned long reg1, reg2, reg3, reg4; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%8\n" - "1:\tcache\t%9,(%0)\n\t" - "lw\t%2,(%1)\n\t" - "lw\t%3,4(%1)\n\t" - "lw\t%4,8(%1)\n\t" - "lw\t%5,12(%1)\n\t" - "sw\t%2,(%0)\n\t" - "sw\t%3,4(%0)\n\t" - "sw\t%4,8(%0)\n\t" - "sw\t%5,12(%0)\n\t" - "lw\t%2,16(%1)\n\t" - "lw\t%3,20(%1)\n\t" - "lw\t%4,24(%1)\n\t" - "lw\t%5,28(%1)\n\t" - "sw\t%2,16(%0)\n\t" - "sw\t%3,20(%0)\n\t" - "sw\t%4,24(%0)\n\t" - "sw\t%5,28(%0)\n\t" - "cache\t%9,32(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "lw\t%2,-32(%1)\n\t" - "lw\t%3,-28(%1)\n\t" - "lw\t%4,-24(%1)\n\t" - "lw\t%5,-20(%1)\n\t" - "sw\t%2,-32(%0)\n\t" - "sw\t%3,-28(%0)\n\t" - "sw\t%4,-24(%0)\n\t" - "sw\t%5,-20(%0)\n\t" - "lw\t%2,-16(%1)\n\t" - "lw\t%3,-12(%1)\n\t" - "lw\t%4,-8(%1)\n\t" - "lw\t%5,-4(%1)\n\t" - "sw\t%2,-16(%0)\n\t" - "sw\t%3,-12(%0)\n\t" - "sw\t%4,-8(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sw\t%5,-4(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), - "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) - :"0" (to), "1" (from), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D)); -} - -/* - * Again a special version for the R4600 V1.x - */ -static void r4k_copy_page_r4600_v1(void * to, void * from) -{ - unsigned long dummy1, dummy2; - unsigned long reg1, reg2, reg3, reg4; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%8\n" - "1:\tnop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "\tcache\t%9,(%0)\n\t" - "lw\t%2,(%1)\n\t" - "lw\t%3,4(%1)\n\t" - "lw\t%4,8(%1)\n\t" - "lw\t%5,12(%1)\n\t" - "sw\t%2,(%0)\n\t" - "sw\t%3,4(%0)\n\t" - "sw\t%4,8(%0)\n\t" - "sw\t%5,12(%0)\n\t" - "lw\t%2,16(%1)\n\t" - "lw\t%3,20(%1)\n\t" - "lw\t%4,24(%1)\n\t" - "lw\t%5,28(%1)\n\t" - "sw\t%2,16(%0)\n\t" - "sw\t%3,20(%0)\n\t" - "sw\t%4,24(%0)\n\t" - "sw\t%5,28(%0)\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "cache\t%9,32(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "lw\t%2,-32(%1)\n\t" - "lw\t%3,-28(%1)\n\t" - "lw\t%4,-24(%1)\n\t" - "lw\t%5,-20(%1)\n\t" - "sw\t%2,-32(%0)\n\t" - "sw\t%3,-28(%0)\n\t" - "sw\t%4,-24(%0)\n\t" - "sw\t%5,-20(%0)\n\t" - "lw\t%2,-16(%1)\n\t" - "lw\t%3,-12(%1)\n\t" - "lw\t%4,-8(%1)\n\t" - "lw\t%5,-4(%1)\n\t" - "sw\t%2,-16(%0)\n\t" - "sw\t%3,-12(%0)\n\t" - "sw\t%4,-8(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sw\t%5,-4(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), - "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) - :"0" (to), "1" (from), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D)); -} - -static void r4k_copy_page_r4600_v2(void * to, void * from) -{ - unsigned long dummy1, dummy2; - unsigned long reg1, reg2, reg3, reg4; - unsigned int flags; - - local_irq_save(flags); - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%8\n" - "1:\tnop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "\tcache\t%9,(%0)\n\t" - "lw\t%2,(%1)\n\t" - "lw\t%3,4(%1)\n\t" - "lw\t%4,8(%1)\n\t" - "lw\t%5,12(%1)\n\t" - "sw\t%2,(%0)\n\t" - "sw\t%3,4(%0)\n\t" - "sw\t%4,8(%0)\n\t" - "sw\t%5,12(%0)\n\t" - "lw\t%2,16(%1)\n\t" - "lw\t%3,20(%1)\n\t" - "lw\t%4,24(%1)\n\t" - "lw\t%5,28(%1)\n\t" - "sw\t%2,16(%0)\n\t" - "sw\t%3,20(%0)\n\t" - "sw\t%4,24(%0)\n\t" - "sw\t%5,28(%0)\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "cache\t%9,32(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "lw\t%2,-32(%1)\n\t" - "lw\t%3,-28(%1)\n\t" - "lw\t%4,-24(%1)\n\t" - "lw\t%5,-20(%1)\n\t" - "sw\t%2,-32(%0)\n\t" - "sw\t%3,-28(%0)\n\t" - "sw\t%4,-24(%0)\n\t" - "sw\t%5,-20(%0)\n\t" - "lw\t%2,-16(%1)\n\t" - "lw\t%3,-12(%1)\n\t" - "lw\t%4,-8(%1)\n\t" - "lw\t%5,-4(%1)\n\t" - "sw\t%2,-16(%0)\n\t" - "sw\t%3,-12(%0)\n\t" - "sw\t%4,-8(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sw\t%5,-4(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), - "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) - :"0" (to), "1" (from), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D)); - local_irq_restore(flags); -} - -/* - * These are for R4000SC / R4400MC - */ -static void r4k_copy_page_s16(void * to, void * from) -{ - unsigned long dummy1, dummy2; - unsigned long reg1, reg2, reg3, reg4; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%8\n" - "1:\tcache\t%9,(%0)\n\t" - "lw\t%2,(%1)\n\t" - "lw\t%3,4(%1)\n\t" - "lw\t%4,8(%1)\n\t" - "lw\t%5,12(%1)\n\t" - "sw\t%2,(%0)\n\t" - "sw\t%3,4(%0)\n\t" - "sw\t%4,8(%0)\n\t" - "sw\t%5,12(%0)\n\t" - "cache\t%9,16(%0)\n\t" - "lw\t%2,16(%1)\n\t" - "lw\t%3,20(%1)\n\t" - "lw\t%4,24(%1)\n\t" - "lw\t%5,28(%1)\n\t" - "sw\t%2,16(%0)\n\t" - "sw\t%3,20(%0)\n\t" - "sw\t%4,24(%0)\n\t" - "sw\t%5,28(%0)\n\t" - "cache\t%9,32(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "lw\t%2,-32(%1)\n\t" - "lw\t%3,-28(%1)\n\t" - "lw\t%4,-24(%1)\n\t" - "lw\t%5,-20(%1)\n\t" - "sw\t%2,-32(%0)\n\t" - "sw\t%3,-28(%0)\n\t" - "sw\t%4,-24(%0)\n\t" - "sw\t%5,-20(%0)\n\t" - "cache\t%9,-16(%0)\n\t" - "lw\t%2,-16(%1)\n\t" - "lw\t%3,-12(%1)\n\t" - "lw\t%4,-8(%1)\n\t" - "lw\t%5,-4(%1)\n\t" - "sw\t%2,-16(%0)\n\t" - "sw\t%3,-12(%0)\n\t" - "sw\t%4,-8(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sw\t%5,-4(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), - "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) - :"0" (to), "1" (from), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_SD)); -} - -static void r4k_copy_page_s32(void * to, void * from) -{ - unsigned long dummy1, dummy2; - unsigned long reg1, reg2, reg3, reg4; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%8\n" - "1:\tcache\t%9,(%0)\n\t" - "lw\t%2,(%1)\n\t" - "lw\t%3,4(%1)\n\t" - "lw\t%4,8(%1)\n\t" - "lw\t%5,12(%1)\n\t" - "sw\t%2,(%0)\n\t" - "sw\t%3,4(%0)\n\t" - "sw\t%4,8(%0)\n\t" - "sw\t%5,12(%0)\n\t" - "lw\t%2,16(%1)\n\t" - "lw\t%3,20(%1)\n\t" - "lw\t%4,24(%1)\n\t" - "lw\t%5,28(%1)\n\t" - "sw\t%2,16(%0)\n\t" - "sw\t%3,20(%0)\n\t" - "sw\t%4,24(%0)\n\t" - "sw\t%5,28(%0)\n\t" - "cache\t%9,32(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "lw\t%2,-32(%1)\n\t" - "lw\t%3,-28(%1)\n\t" - "lw\t%4,-24(%1)\n\t" - "lw\t%5,-20(%1)\n\t" - "sw\t%2,-32(%0)\n\t" - "sw\t%3,-28(%0)\n\t" - "sw\t%4,-24(%0)\n\t" - "sw\t%5,-20(%0)\n\t" - "lw\t%2,-16(%1)\n\t" - "lw\t%3,-12(%1)\n\t" - "lw\t%4,-8(%1)\n\t" - "lw\t%5,-4(%1)\n\t" - "sw\t%2,-16(%0)\n\t" - "sw\t%3,-12(%0)\n\t" - "sw\t%4,-8(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sw\t%5,-4(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), - "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) - :"0" (to), "1" (from), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_SD)); -} - -static void r4k_copy_page_s64(void * to, void * from) -{ - unsigned long dummy1, dummy2; - unsigned long reg1, reg2, reg3, reg4; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%8\n" - "1:\tcache\t%9,(%0)\n\t" - "lw\t%2,(%1)\n\t" - "lw\t%3,4(%1)\n\t" - "lw\t%4,8(%1)\n\t" - "lw\t%5,12(%1)\n\t" - "sw\t%2,(%0)\n\t" - "sw\t%3,4(%0)\n\t" - "sw\t%4,8(%0)\n\t" - "sw\t%5,12(%0)\n\t" - "lw\t%2,16(%1)\n\t" - "lw\t%3,20(%1)\n\t" - "lw\t%4,24(%1)\n\t" - "lw\t%5,28(%1)\n\t" - "sw\t%2,16(%0)\n\t" - "sw\t%3,20(%0)\n\t" - "sw\t%4,24(%0)\n\t" - "sw\t%5,28(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "lw\t%2,-32(%1)\n\t" - "lw\t%3,-28(%1)\n\t" - "lw\t%4,-24(%1)\n\t" - "lw\t%5,-20(%1)\n\t" - "sw\t%2,-32(%0)\n\t" - "sw\t%3,-28(%0)\n\t" - "sw\t%4,-24(%0)\n\t" - "sw\t%5,-20(%0)\n\t" - "lw\t%2,-16(%1)\n\t" - "lw\t%3,-12(%1)\n\t" - "lw\t%4,-8(%1)\n\t" - "lw\t%5,-4(%1)\n\t" - "sw\t%2,-16(%0)\n\t" - "sw\t%3,-12(%0)\n\t" - "sw\t%4,-8(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sw\t%5,-4(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), - "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) - :"0" (to), "1" (from), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_SD)); -} - -static void r4k_copy_page_s128(void * to, void * from) -{ - unsigned long dummy1, dummy2; - unsigned long reg1, reg2, reg3, reg4; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%8\n" - "1:\tcache\t%9,(%0)\n\t" - "lw\t%2,(%1)\n\t" - "lw\t%3,4(%1)\n\t" - "lw\t%4,8(%1)\n\t" - "lw\t%5,12(%1)\n\t" - "sw\t%2,(%0)\n\t" - "sw\t%3,4(%0)\n\t" - "sw\t%4,8(%0)\n\t" - "sw\t%5,12(%0)\n\t" - "lw\t%2,16(%1)\n\t" - "lw\t%3,20(%1)\n\t" - "lw\t%4,24(%1)\n\t" - "lw\t%5,28(%1)\n\t" - "sw\t%2,16(%0)\n\t" - "sw\t%3,20(%0)\n\t" - "sw\t%4,24(%0)\n\t" - "sw\t%5,28(%0)\n\t" - "lw\t%2,32(%1)\n\t" - "lw\t%3,36(%1)\n\t" - "lw\t%4,40(%1)\n\t" - "lw\t%5,44(%1)\n\t" - "sw\t%2,32(%0)\n\t" - "sw\t%3,36(%0)\n\t" - "sw\t%4,40(%0)\n\t" - "sw\t%5,44(%0)\n\t" - "lw\t%2,48(%1)\n\t" - "lw\t%3,52(%1)\n\t" - "lw\t%4,56(%1)\n\t" - "lw\t%5,60(%1)\n\t" - "sw\t%2,48(%0)\n\t" - "sw\t%3,52(%0)\n\t" - "sw\t%4,56(%0)\n\t" - "sw\t%5,60(%0)\n\t" - "daddiu\t%0,128\n\t" - "daddiu\t%1,128\n\t" - "lw\t%2,-64(%1)\n\t" - "lw\t%3,-60(%1)\n\t" - "lw\t%4,-56(%1)\n\t" - "lw\t%5,-52(%1)\n\t" - "sw\t%2,-64(%0)\n\t" - "sw\t%3,-60(%0)\n\t" - "sw\t%4,-56(%0)\n\t" - "sw\t%5,-52(%0)\n\t" - "lw\t%2,-48(%1)\n\t" - "lw\t%3,-44(%1)\n\t" - "lw\t%4,-40(%1)\n\t" - "lw\t%5,-36(%1)\n\t" - "sw\t%2,-48(%0)\n\t" - "sw\t%3,-44(%0)\n\t" - "sw\t%4,-40(%0)\n\t" - "sw\t%5,-36(%0)\n\t" - "lw\t%2,-32(%1)\n\t" - "lw\t%3,-28(%1)\n\t" - "lw\t%4,-24(%1)\n\t" - "lw\t%5,-20(%1)\n\t" - "sw\t%2,-32(%0)\n\t" - "sw\t%3,-28(%0)\n\t" - "sw\t%4,-24(%0)\n\t" - "sw\t%5,-20(%0)\n\t" - "lw\t%2,-16(%1)\n\t" - "lw\t%3,-12(%1)\n\t" - "lw\t%4,-8(%1)\n\t" - "lw\t%5,-4(%1)\n\t" - "sw\t%2,-16(%0)\n\t" - "sw\t%3,-12(%0)\n\t" - "sw\t%4,-8(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sw\t%5,-4(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), - "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) - :"0" (to), "1" (from), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_SD)); -} - - -/* - * If you think for one second that this stuff coming up is a lot - * of bulky code eating too many kernel cache lines. Think _again_. - * - * Consider: - * 1) Taken branches have a 3 cycle penalty on R4k - * 2) The branch itself is a real dead cycle on even R4600/R5000. - * 3) Only one of the following variants of each type is even used by - * the kernel based upon the cache parameters we detect at boot time. - * - * QED. - */ - -static inline void r4k_flush_cache_all_s16d16i16(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache16(); blast_icache16(); blast_scache16(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_s32d16i16(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache16(); blast_icache16(); blast_scache32(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_s64d16i16(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache16(); blast_icache16(); blast_scache64(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_s128d16i16(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache16(); blast_icache16(); blast_scache128(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_s32d32i32(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache32(); blast_icache32(); blast_scache32(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_s64d32i32(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache32(); blast_icache32(); blast_scache64(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_s128d32i32(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache32(); blast_icache32(); blast_scache128(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_d16i16(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache16(); blast_icache16(); - local_irq_restore(flags); -} - -static inline void r4k_flush_cache_all_d32i32(void) -{ - unsigned long flags; - - local_irq_save(flags); - blast_dcache32(); blast_icache32(); - local_irq_restore(flags); -} - -static void -r4k_flush_cache_range_s16d16i16(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - - if (mm->context == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (vma) { - if (mm->context != current->active_mm->context) { - r4k_flush_cache_all_s16d16i16(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache16_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void -r4k_flush_cache_range_s32d16i16(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - - if (mm->context == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (vma) { - if (mm->context != current->active_mm->context) { - r4k_flush_cache_all_s32d16i16(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache32_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void r4k_flush_cache_range_s64d16i16(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - - if (mm->context == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if(vma) { - if (mm->context != current->active_mm->context) { - r4k_flush_cache_all_s64d16i16(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache64_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void r4k_flush_cache_range_s128d16i16(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - - if (mm->context == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (vma) { - if (mm->context != current->active_mm->context) { - r4k_flush_cache_all_s128d16i16(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache128_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void r4k_flush_cache_range_s32d32i32(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - - if (mm->context == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (vma) { - if (mm->context != current->active_mm->context) { - r4k_flush_cache_all_s32d32i32(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache32_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void r4k_flush_cache_range_s64d32i32(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - - if (mm->context == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (vma) { - if (mm->context != current->active_mm->context) { - r4k_flush_cache_all_s64d32i32(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache64_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void r4k_flush_cache_range_s128d32i32(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - - if (mm->context == 0) - return; - - start &= PAGE_MASK; -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - if (vma) { - if (mm->context != current->active_mm->context) { - r4k_flush_cache_all_s128d32i32(); - } else { - pgd_t *pgd; - pmd_t *pmd; - pte_t *pte; - - local_irq_save(flags); - while(start < end) { - pgd = pgd_offset(mm, start); - pmd = pmd_offset(pgd, start); - pte = pte_offset(pmd, start); - - if(pte_val(*pte) & _PAGE_VALID) - blast_scache128_page(start); - start += PAGE_SIZE; - } - local_irq_restore(flags); - } - } -} - -static void r4k_flush_cache_range_d16i16(struct mm_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - - if (mm->context != 0) { - unsigned long flags; - -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - local_irq_save(flags); - blast_dcache16(); blast_icache16(); - local_irq_restore(flags); - } -} - -static void r4k_flush_cache_range_d32i32(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - - if (mm->context != 0) { - unsigned long flags; - -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - local_irq_save(flags); - blast_dcache32(); blast_icache32(); - local_irq_restore(flags); - } -} - -/* - * On architectures like the Sparc, we could get rid of lines in - * the cache created only by a certain context, but on the MIPS - * (and actually certain Sparc's) we cannot. - */ -static void r4k_flush_cache_mm_s16d16i16(struct mm_struct *mm) -{ - if (mm->context != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_s16d16i16(); - } -} - -static void r4k_flush_cache_mm_s32d16i16(struct mm_struct *mm) -{ - if (mm->context != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_s32d16i16(); - } -} - -static void r4k_flush_cache_mm_s64d16i16(struct mm_struct *mm) -{ - if (mm->context != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_s64d16i16(); - } -} - -static void r4k_flush_cache_mm_s128d16i16(struct mm_struct *mm) -{ - if (mm->context != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_s128d16i16(); - } -} - -static void r4k_flush_cache_mm_s32d32i32(struct mm_struct *mm) -{ - if (mm->context != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_s32d32i32(); - } -} - -static void r4k_flush_cache_mm_s64d32i32(struct mm_struct *mm) -{ - if (mm->context != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_s64d32i32(); - } -} - -static void r4k_flush_cache_mm_s128d32i32(struct mm_struct *mm) -{ - if (mm->context != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_s128d32i32(); - } -} - -static void r4k_flush_cache_mm_d16i16(struct mm_struct *mm) -{ - if (mm->context != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_d16i16(); - } -} - -static void r4k_flush_cache_mm_d32i32(struct mm_struct *mm) -{ - if (mm->context != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r4k_flush_cache_all_d32i32(); - } -} - -static void r4k_flush_cache_page_s16d16i16(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (mm->context == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if (!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (mm->context != current->active_mm->context) { - /* - * Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache16_page_indexed(page); - blast_scache16_page_indexed(page); - } else - blast_scache16_page(page); -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_s32d16i16(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (mm->context == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if (!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (mm->context != current->active_mm->context) { - /* - * Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache16_page_indexed(page); - blast_scache32_page_indexed(page); - } else - blast_scache32_page(page); -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_s64d16i16(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (mm->context == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if (!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (mm->context != current->active_mm->context) { - /* - * Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache16_page_indexed(page); - blast_scache64_page_indexed(page); - } else - blast_scache64_page(page); -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_s128d16i16(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (mm->context == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if (!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (mm->context != current->active_mm->context) { - /* - * Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache16_page_indexed(page); - blast_scache128_page_indexed(page); - } else - blast_scache128_page(page); -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_s32d32i32(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (mm->context == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if (!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (mm->context != current->active_mm->context) { - /* - * Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache32_page_indexed(page); - blast_scache32_page_indexed(page); - } else - blast_scache32_page(page); -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_s64d32i32(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (mm->context == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if (!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (mm->context != current->active_mm->context) { - /* - * Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache32_page_indexed(page); - blast_scache64_page_indexed(page); - } else - blast_scache64_page(page); -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_s128d32i32(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (mm->context == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if (!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (mm->context != current->active_mm->context) { - /* Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (scache_size - 1))); - blast_dcache32_page_indexed(page); - blast_scache128_page_indexed(page); - } else - blast_scache128_page(page); -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_d16i16(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (mm->context == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if (!(pte_val(*ptep) & _PAGE_VALID)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if (mm == current->active_mm) { - blast_dcache16_page(page); - } else { - /* Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (dcache_size - 1))); - blast_dcache16_page_indexed(page); - } -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_d32i32(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (mm->context == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if (!(pte_val(*ptep) & _PAGE_PRESENT)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { - blast_dcache32_page(page); - } else { - /* - * Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (dcache_size - 1))); - blast_dcache32_page_indexed(page); - } -out: - local_irq_restore(flags); -} - -static void r4k_flush_cache_page_d32i32_r4600(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (mm->context == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - local_irq_save(flags); - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if (!(pte_val(*ptep) & _PAGE_PRESENT)) - goto out; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { - blast_dcache32_page(page); - } else { - /* Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (dcache_size - 1))); - blast_dcache32_page_indexed(page); - blast_dcache32_page_indexed(page ^ dcache_waybit); - } -out: - local_irq_restore(flags); -} - -/* If the addresses passed to these routines are valid, they are - * either: - * - * 1) In KSEG0, so we can do a direct flush of the page. - * 2) In KSEG2, and since every process can translate those - * addresses all the time in kernel mode we can do a direct - * flush. - * 3) In KSEG1, no flush necessary. - */ -static void r4k_flush_page_to_ram_s16(struct page *page) -{ - blast_scache16_page((unsigned long)page_address(page)); -} - -static void r4k_flush_page_to_ram_s32(struct page *page) -{ - blast_scache32_page((unsigned long)page_address(page)); -} - -static void r4k_flush_page_to_ram_s64(struct page *page) -{ - blast_scache64_page((unsigned long)page_address(page)); -} - -static void r4k_flush_page_to_ram_s128(struct page *page) -{ - blast_scache128_page((unsigned long)page_address(page)); -} - -static void r4k_flush_page_to_ram_d16(struct page *page) -{ - blast_dcache16_page((unsigned long)page_address(page)); -} - -static void r4k_flush_page_to_ram_d32(struct page *page) -{ - blast_dcache32_page((unsigned long)page_address(page)); -} - -static void r4k_flush_page_to_ram_d32_r4600(struct page *page) -{ - unsigned long flags; - - local_irq_save(flags); /* For R4600 v1.7 bug. */ - blast_dcache32_page((unsigned long)page_address(page)); - local_irq_restore(flags); -} - -static void -r4k_flush_icache_page_s(struct vm_area_struct *vma, struct page *page) -{ - /* - * We did an scache flush therefore PI is already clean. - */ -} - -static void -r4k_flush_icache_range(unsigned long start, unsigned long end) -{ - flush_cache_all(); -} - -/* - * Ok, this seriously sucks. We use them to flush a user page but don't - * know the virtual address, so we have to blast away the whole icache - * which is significantly more expensive than the real thing. - */ -static void -r4k_flush_icache_page_p(struct vm_area_struct *vma, struct page *page) -{ - if (!(vma->vm_flags & VM_EXEC)) - return; - - flush_cache_all(); -} - -/* - * Writeback and invalidate the primary cache dcache before DMA. - * - * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, - * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only - * operate correctly if the internal data cache refill buffer is empty. These - * CACHE instructions should be separated from any potential data cache miss - * by a load instruction to an uncached address to empty the response buffer." - * (Revision 2.0 device errata from IDT available on http://www.idt.com/ - * in .pdf format.) - */ -static void -r4k_dma_cache_wback_inv_pc(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - unsigned int flags; - - if (size >= dcache_size) { - flush_cache_all(); - } else { - /* Workaround for R4600 bug. See comment above. */ - local_irq_save(flags); - *(volatile unsigned long *)KSEG1; - - a = addr & ~(dc_lsize - 1); - end = (addr + size) & ~(dc_lsize - 1); - while (1) { - flush_dcache_line(a); /* Hit_Writeback_Inv_D */ - if (a == end) break; - a += dc_lsize; - } - local_irq_restore(flags); - } - bc_wback_inv(addr, size); -} - -static void -r4k_dma_cache_wback_inv_sc(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - - if (size >= scache_size) { - flush_cache_all(); - return; - } - - a = addr & ~(sc_lsize - 1); - end = (addr + size) & ~(sc_lsize - 1); - while (1) { - flush_scache_line(a); /* Hit_Writeback_Inv_SD */ - if (a == end) break; - a += sc_lsize; - } -} - -static void -r4k_dma_cache_inv_pc(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - unsigned int flags; - - if (size >= dcache_size) { - flush_cache_all(); - } else { - /* Workaround for R4600 bug. See comment above. */ - local_irq_save(flags); - *(volatile unsigned long *)KSEG1; - - a = addr & ~(dc_lsize - 1); - end = (addr + size) & ~(dc_lsize - 1); - while (1) { - flush_dcache_line(a); /* Hit_Writeback_Inv_D */ - if (a == end) break; - a += dc_lsize; - } - local_irq_restore(flags); - } - - bc_inv(addr, size); -} - -static void -r4k_dma_cache_inv_sc(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - - if (size >= scache_size) { - flush_cache_all(); - return; - } - - a = addr & ~(sc_lsize - 1); - end = (addr + size) & ~(sc_lsize - 1); - while (1) { - flush_scache_line(a); /* Hit_Writeback_Inv_SD */ - if (a == end) break; - a += sc_lsize; - } -} - -static void -r4k_dma_cache_wback(unsigned long addr, unsigned long size) -{ - panic("r4k_dma_cache called - should not happen.\n"); -} - -/* - * While we're protected against bad userland addresses we don't care - * very much about what happens in that case. Usually a segmentation - * fault will dump the process later on anyway ... - */ -static void r4k_flush_cache_sigtramp(unsigned long addr) -{ - __asm__ __volatile__("nop;nop;nop;nop"); /* R4600 V1.7 */ - protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); - protected_flush_icache_line(addr & ~(ic_lsize - 1)); -} - -static void r4600v20k_flush_cache_sigtramp(unsigned long addr) -{ - unsigned int flags; - - local_irq_save(flags); - - /* Clear internal cache refill buffer */ - *(volatile unsigned int *)KSEG1; - - protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); - protected_flush_icache_line(addr & ~(ic_lsize - 1)); - - local_irq_restore(flags); -} - -#undef DEBUG_TLB -#undef DEBUG_TLBUPDATE - -void flush_tlb_all(void) -{ - unsigned long flags; - unsigned long old_ctx; - int entry; - -#ifdef DEBUG_TLB - printk("[tlball]"); -#endif - - local_irq_save(flags); - /* Save old context and create impossible VPN2 value */ - old_ctx = (get_entryhi() & 0xff); - set_entryhi(KSEG0); - set_entrylo0(0); - set_entrylo1(0); - BARRIER; - - entry = get_wired(); - - /* Blast 'em all away. */ - while(entry < mips_cpu.tlbsize) { - set_index(entry); - BARRIER; - tlb_write_indexed(); - BARRIER; - entry++; - } - BARRIER; - set_entryhi(old_ctx); - local_irq_restore(flags); -} - -void flush_tlb_mm(struct mm_struct *mm) -{ - if (mm->context != 0) { - unsigned long flags; - -#ifdef DEBUG_TLB - printk("[tlbmm<%d>]", mm->context); -#endif - local_irq_save(flags); - get_new_mmu_context(mm, asid_cache); - if (mm == current->active_mm) - set_entryhi(mm->context & 0xff); - local_irq_restore(flags); - } -} - -void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - - if (mm->context != 0) { - unsigned long flags; - int size; - -#ifdef DEBUG_TLB - printk("[tlbrange<%02x,%08lx,%08lx>]", (mm->context & 0xff), - start, end); -#endif - local_irq_save(flags); - size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - size = (size + 1) >> 1; - if(size <= mips_cpu.tlbsize/2) { - int oldpid = (get_entryhi() & 0xff); - int newpid = (mm->context & 0xff); - - start &= (PAGE_MASK << 1); - end += ((PAGE_SIZE << 1) - 1); - end &= (PAGE_MASK << 1); - while(start < end) { - int idx; - - set_entryhi(start | newpid); - start += (PAGE_SIZE << 1); - BARRIER; - tlb_probe(); - BARRIER; - idx = get_index(); - set_entrylo0(0); - set_entrylo1(0); - set_entryhi(KSEG0); - BARRIER; - if(idx < 0) - continue; - tlb_write_indexed(); - BARRIER; - } - set_entryhi(oldpid); - } else { - get_new_mmu_context(mm, asid_cache); - if (mm == current->active_mm) - set_entryhi(mm->context & 0xff); - } - local_irq_restore(flags); - } -} - -void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) -{ - if (vma->vm_mm->context != 0) { - unsigned long flags; - int oldpid, newpid, idx; - -#ifdef DEBUG_TLB - printk("[tlbpage<%d,%08lx>]", vma->vm_mm->context, page); -#endif - newpid = (vma->vm_mm->context & 0xff); - page &= (PAGE_MASK << 1); - local_irq_save(flags); - oldpid = (get_entryhi() & 0xff); - set_entryhi(page | newpid); - BARRIER; - tlb_probe(); - BARRIER; - idx = get_index(); - set_entrylo0(0); - set_entrylo1(0); - set_entryhi(KSEG0); - if(idx < 0) - goto finish; - BARRIER; - tlb_write_indexed(); - - finish: - BARRIER; - set_entryhi(oldpid); - local_irq_restore(flags); - } -} - -void pgd_init(unsigned long page) -{ - unsigned long *p = (unsigned long *) page; - int i; - - for(i = 0; i < USER_PTRS_PER_PGD; i+=8) { - p[i + 0] = (unsigned long) invalid_pte_table; - p[i + 1] = (unsigned long) invalid_pte_table; - p[i + 2] = (unsigned long) invalid_pte_table; - p[i + 3] = (unsigned long) invalid_pte_table; - p[i + 4] = (unsigned long) invalid_pte_table; - p[i + 5] = (unsigned long) invalid_pte_table; - p[i + 6] = (unsigned long) invalid_pte_table; - p[i + 7] = (unsigned long) invalid_pte_table; - } -} - -/* We will need multiple versions of update_mmu_cache(), one that just - * updates the TLB with the new pte(s), and another which also checks - * for the R4k "end of page" hardware bug and does the needy. - */ -void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) -{ - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - int idx, pid; - - /* - * Handle debugger faulting in for debugee. - */ - if (current->active_mm != vma->vm_mm) - return; - - pid = get_entryhi() & 0xff; - -#ifdef DEBUG_TLB - if((pid != (vma->vm_mm->context & 0xff)) || (vma->vm_mm->context == 0)) { - printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d tlbpid=%d\n", - (int) (vma->vm_mm->context & 0xff), pid); - } -#endif - - local_irq_save(flags); - address &= (PAGE_MASK << 1); - set_entryhi(address | (pid)); - pgdp = pgd_offset(vma->vm_mm, address); - BARRIER; - tlb_probe(); - BARRIER; - pmdp = pmd_offset(pgdp, address); - idx = get_index(); - ptep = pte_offset(pmdp, address); - BARRIER; - set_entrylo0(pte_val(*ptep++) >> 6); - set_entrylo1(pte_val(*ptep) >> 6); - set_entryhi(address | (pid)); - BARRIER; - if(idx < 0) { - tlb_write_random(); - } else { - tlb_write_indexed(); - } - BARRIER; - set_entryhi(pid); - BARRIER; - local_irq_restore(flags); -} - -#if 0 -static void r4k_update_mmu_cache_hwbug(struct vm_area_struct * vma, - unsigned long address, pte_t pte) -{ - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - int idx; - - local_irq_save(flags); - address &= (PAGE_MASK << 1); - set_entryhi(address | (get_entryhi() & 0xff)); - pgdp = pgd_offset(vma->vm_mm, address); - tlb_probe(); - pmdp = pmd_offset(pgdp, address); - idx = get_index(); - ptep = pte_offset(pmdp, address); - set_entrylo0(pte_val(*ptep++) >> 6); - set_entrylo1(pte_val(*ptep) >> 6); - BARRIER; - if(idx < 0) - tlb_write_random(); - else - tlb_write_indexed(); - BARRIER; - local_irq_restore(flags); -} -#endif - -void show_regs(struct pt_regs * regs) -{ - /* Saved main processor registers. */ - printk("$0 : %08lx %08lx %08lx %08lx\n", - 0UL, regs->regs[1], regs->regs[2], regs->regs[3]); - printk("$4 : %08lx %08lx %08lx %08lx\n", - regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); - printk("$8 : %08lx %08lx %08lx %08lx\n", - regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11]); - printk("$12: %08lx %08lx %08lx %08lx\n", - regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]); - printk("$16: %08lx %08lx %08lx %08lx\n", - regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19]); - printk("$20: %08lx %08lx %08lx %08lx\n", - regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]); - printk("$24: %08lx %08lx\n", - regs->regs[24], regs->regs[25]); - printk("$28: %08lx %08lx %08lx %08lx\n", - regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]); - - /* Saved cp0 registers. */ - printk("epc : %08lx %s\nStatus: %08lx\nCause : %08lx\n", - regs->cp0_epc, print_tainted(), regs->cp0_status, regs->cp0_cause); -} - -void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask) -{ - unsigned long flags; - unsigned long wired; - unsigned long old_pagemask; - unsigned long old_ctx; - - local_irq_save(flags); - /* Save old context and create impossible VPN2 value */ - old_ctx = (get_entryhi() & 0xff); - old_pagemask = get_pagemask(); - wired = get_wired(); - set_wired (wired + 1); - set_index (wired); - BARRIER; - set_pagemask (pagemask); - set_entryhi(entryhi); - set_entrylo0(entrylo0); - set_entrylo1(entrylo1); - BARRIER; - tlb_write_indexed(); - BARRIER; - - set_entryhi(old_ctx); - BARRIER; - set_pagemask (old_pagemask); - flush_tlb_all(); - local_irq_restore(flags); -} - -/* Detect and size the various r4k caches. */ -static void __init probe_icache(unsigned long config) -{ - switch (mips_cpu.cputype) { - case CPU_VR41XX: - icache_size = 1 << (10 + ((config >> 9) & 7)); - break; - default: - icache_size = 1 << (12 + ((config >> 9) & 7)); - break; - } - ic_lsize = 16 << ((config >> 5) & 1); - - printk("Primary instruction cache %dkb, linesize %d bytes.\n", - icache_size >> 10, ic_lsize); -} - -static void __init probe_dcache(unsigned long config) -{ - switch (mips_cpu.cputype) { - case CPU_VR41XX: - dcache_size = 1 << (10 + ((config >> 6) & 7)); - break; - default: - dcache_size = 1 << (12 + ((config >> 6) & 7)); - break; - } - dc_lsize = 16 << ((config >> 4) & 1); - - printk("Primary data cache %dkb, linesize %d bytes.\n", - dcache_size >> 10, dc_lsize); -} - - -/* If you even _breathe_ on this function, look at the gcc output - * and make sure it does not pop things on and off the stack for - * the cache sizing loop that executes in KSEG1 space or else - * you will crash and burn badly. You have been warned. - */ -static int __init probe_scache(unsigned long config) -{ - extern unsigned long stext; - unsigned long flags, addr, begin, end, pow2; - int tmp; - - tmp = ((config >> 17) & 1); - if(tmp) - return 0; - tmp = ((config >> 22) & 3); - switch(tmp) { - case 0: - sc_lsize = 16; - break; - case 1: - sc_lsize = 32; - break; - case 2: - sc_lsize = 64; - break; - case 3: - sc_lsize = 128; - break; - } - - begin = (unsigned long) &stext; - begin &= ~((4 * 1024 * 1024) - 1); - end = begin + (4 * 1024 * 1024); - - /* This is such a bitch, you'd think they would make it - * easy to do this. Away you daemons of stupidity! - */ - local_irq_save(flags); - - /* Fill each size-multiple cache line with a valid tag. */ - pow2 = (64 * 1024); - for(addr = begin; addr < end; addr = (begin + pow2)) { - unsigned long *p = (unsigned long *) addr; - __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ - pow2 <<= 1; - } - - /* Load first line with zero (therefore invalid) tag. */ - set_taglo(0); - set_taghi(0); - __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ - __asm__ __volatile__("\n\t.set noreorder\n\t" - ".set mips3\n\t" - "cache 8, (%0)\n\t" - ".set mips0\n\t" - ".set reorder\n\t" : : "r" (begin)); - __asm__ __volatile__("\n\t.set noreorder\n\t" - ".set mips3\n\t" - "cache 9, (%0)\n\t" - ".set mips0\n\t" - ".set reorder\n\t" : : "r" (begin)); - __asm__ __volatile__("\n\t.set noreorder\n\t" - ".set mips3\n\t" - "cache 11, (%0)\n\t" - ".set mips0\n\t" - ".set reorder\n\t" : : "r" (begin)); - - /* Now search for the wrap around point. */ - pow2 = (128 * 1024); - tmp = 0; - for(addr = (begin + (128 * 1024)); addr < (end); addr = (begin + pow2)) { - __asm__ __volatile__("\n\t.set noreorder\n\t" - ".set mips3\n\t" - "cache 7, (%0)\n\t" - ".set mips0\n\t" - ".set reorder\n\t" : : "r" (addr)); - __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ - if(!get_taglo()) - break; - pow2 <<= 1; - } - local_irq_restore(flags); - addr -= begin; - printk("Secondary cache sized at %dK linesize %d bytes.\n", - (int) (addr >> 10), sc_lsize); - scache_size = addr; - return 1; -} - -static void __init setup_noscache_funcs(void) -{ - unsigned int prid; - - switch(dc_lsize) { - case 16: - _clear_page = r4k_clear_page_d16; - _copy_page = r4k_copy_page_d16; - _flush_cache_all = r4k_flush_cache_all_d16i16; - _flush_cache_mm = r4k_flush_cache_mm_d16i16; - _flush_cache_range = r4k_flush_cache_range_d16i16; - _flush_cache_page = r4k_flush_cache_page_d16i16; - _flush_page_to_ram = r4k_flush_page_to_ram_d16; - break; - case 32: - prid = read_32bit_cp0_register(CP0_PRID) & 0xfff0; - if (prid == 0x2010) { /* R4600 V1.7 */ - _clear_page = r4k_clear_page_r4600_v1; - _copy_page = r4k_copy_page_r4600_v1; - _flush_page_to_ram = r4k_flush_page_to_ram_d32_r4600; - } else if (prid == 0x2020) { /* R4600 V2.0 */ - _clear_page = r4k_clear_page_r4600_v2; - _copy_page = r4k_copy_page_r4600_v2; - _flush_page_to_ram = r4k_flush_page_to_ram_d32; - } else { - _clear_page = r4k_clear_page_d32; - _copy_page = r4k_copy_page_d32; - _flush_page_to_ram = r4k_flush_page_to_ram_d32; - } - _flush_cache_all = r4k_flush_cache_all_d32i32; - _flush_cache_mm = r4k_flush_cache_mm_d32i32; - _flush_cache_range = r4k_flush_cache_range_d32i32; - _flush_cache_page = r4k_flush_cache_page_d32i32; - break; - } - ___flush_cache_all = _flush_cache_all; - - _flush_icache_page = r4k_flush_icache_page_p; - - _dma_cache_wback_inv = r4k_dma_cache_wback_inv_pc; - _dma_cache_wback = r4k_dma_cache_wback; - _dma_cache_inv = r4k_dma_cache_inv_pc; -} - -static void __init setup_scache_funcs(void) -{ - switch(sc_lsize) { - case 16: - switch(dc_lsize) { - case 16: - _flush_cache_all = r4k_flush_cache_all_s16d16i16; - _flush_cache_mm = r4k_flush_cache_mm_s16d16i16; - _flush_cache_range = r4k_flush_cache_range_s16d16i16; - _flush_cache_page = r4k_flush_cache_page_s16d16i16; - break; - case 32: - panic("Invalid cache configuration detected"); - }; - _flush_page_to_ram = r4k_flush_page_to_ram_s16; - _clear_page = r4k_clear_page_s16; - _copy_page = r4k_copy_page_s16; - break; - case 32: - switch(dc_lsize) { - case 16: - _flush_cache_all = r4k_flush_cache_all_s32d16i16; - _flush_cache_mm = r4k_flush_cache_mm_s32d16i16; - _flush_cache_range = r4k_flush_cache_range_s32d16i16; - _flush_cache_page = r4k_flush_cache_page_s32d16i16; - break; - case 32: - _flush_cache_all = r4k_flush_cache_all_s32d32i32; - _flush_cache_mm = r4k_flush_cache_mm_s32d32i32; - _flush_cache_range = r4k_flush_cache_range_s32d32i32; - _flush_cache_page = r4k_flush_cache_page_s32d32i32; - break; - }; - _flush_page_to_ram = r4k_flush_page_to_ram_s32; - _clear_page = r4k_clear_page_s32; - _copy_page = r4k_copy_page_s32; - break; - case 64: - switch(dc_lsize) { - case 16: - _flush_cache_all = r4k_flush_cache_all_s64d16i16; - _flush_cache_mm = r4k_flush_cache_mm_s64d16i16; - _flush_cache_range = r4k_flush_cache_range_s64d16i16; - _flush_cache_page = r4k_flush_cache_page_s64d16i16; - break; - case 32: - _flush_cache_all = r4k_flush_cache_all_s64d32i32; - _flush_cache_mm = r4k_flush_cache_mm_s64d32i32; - _flush_cache_range = r4k_flush_cache_range_s64d32i32; - _flush_cache_page = r4k_flush_cache_page_s64d32i32; - break; - }; - _flush_page_to_ram = r4k_flush_page_to_ram_s64; - _clear_page = r4k_clear_page_s64; - _copy_page = r4k_copy_page_s64; - break; - case 128: - switch(dc_lsize) { - case 16: - _flush_cache_all = r4k_flush_cache_all_s128d16i16; - _flush_cache_mm = r4k_flush_cache_mm_s128d16i16; - _flush_cache_range = r4k_flush_cache_range_s128d16i16; - _flush_cache_page = r4k_flush_cache_page_s128d16i16; - break; - case 32: - _flush_cache_all = r4k_flush_cache_all_s128d32i32; - _flush_cache_mm = r4k_flush_cache_mm_s128d32i32; - _flush_cache_range = r4k_flush_cache_range_s128d32i32; - _flush_cache_page = r4k_flush_cache_page_s128d32i32; - break; - }; - _flush_page_to_ram = r4k_flush_page_to_ram_s128; - _clear_page = r4k_clear_page_s128; - _copy_page = r4k_copy_page_s128; - break; - } - ___flush_cache_all = _flush_cache_all; - _flush_icache_page = r4k_flush_icache_page_s; - _dma_cache_wback_inv = r4k_dma_cache_wback_inv_sc; - _dma_cache_wback = r4k_dma_cache_wback; - _dma_cache_inv = r4k_dma_cache_inv_sc; -} - -typedef int (*probe_func_t)(unsigned long); - -static inline void __init setup_scache(unsigned int config) -{ - probe_func_t probe_scache_kseg1; - int sc_present = 0; - - /* Maybe the cpu knows about a l2 cache? */ - probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache)); - sc_present = probe_scache_kseg1(config); - - if (sc_present) { - setup_scache_funcs(); - return; - } - - setup_noscache_funcs(); -} - -void __init ld_mmu_r4xx0(void) -{ - unsigned long config = read_32bit_cp0_register(CP0_CONFIG); - - printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID)); - -#ifdef CONFIG_MIPS_UNCACHED - change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); -#else - change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); -#endif - - probe_icache(config); - probe_dcache(config); - setup_scache(config); - - switch(mips_cpu.cputype) { - case CPU_R4600: /* QED style two way caches? */ - case CPU_R4700: - case CPU_R5000: - case CPU_NEVADA: - _flush_cache_page = r4k_flush_cache_page_d32i32_r4600; - } - - _flush_cache_sigtramp = r4k_flush_cache_sigtramp; - _flush_icache_range = r4k_flush_icache_range; /* Ouch */ - if ((read_32bit_cp0_register(CP0_PRID) & 0xfff0) == 0x2020) { - _flush_cache_sigtramp = r4600v20k_flush_cache_sigtramp; - } - - __flush_cache_all(); - write_32bit_cp0_register(CP0_WIRED, 0); - - /* - * You should never change this register: - * - On R4600 1.7 the tlbp never hits for pages smaller than - * the value in the c0_pagemask register. - * - The entire mm handling assumes the c0_pagemask register to - * be set for 4kb pages. - */ - set_pagemask(PM_4K); - flush_tlb_all(); -} --- linux-2.5.73/arch/mips/mm/r5432.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,864 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * r5432.c: NEC Vr5432 processor. We cannot use r4xx0.c because of - * its unique way-selection method for indexed operations. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 2000 Jun Sun (jsun@mvista.com) - * - */ - -/* - * [jsun] - * In a sense, this is really silly. We cannot re-use r4xx0.c because - * the lowest-level indexed cache operation does not take way-selection - * into account. So all what I am doing here is to copy all the funcs - * and macros (in r4kcache.h) relavent to R5432 to this file, and then - * modify a few indexed cache operations. *sigh* - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -/* CP0 hazard avoidance. */ -#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ - "nop; nop; nop; nop; nop; nop;\n\t" \ - ".set reorder\n\t") - -#include -#include - -#undef DEBUG_CACHE - -/* Primary cache parameters. */ -static int icache_size, dcache_size; /* Size in bytes */ -static int ic_lsize, dc_lsize; /* LineSize in bytes */ - - -/* -------------------------------------------------------------------- */ -/* #include */ - -extern inline void flush_icache_line_indexed(unsigned long addr) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache %1, (%0)\n\t" - "cache %1, 1(%0)\n\t" - ".set mips0\n\t" - ".set reorder" - : - : "r" (addr), - "i" (Index_Invalidate_I)); -} - -extern inline void flush_dcache_line_indexed(unsigned long addr) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache %1, (%0)\n\t" - "cache %1, 1(%0)\n\t" - ".set mips0\n\t" - ".set reorder" - : - : "r" (addr), - "i" (Index_Writeback_Inv_D)); -} - -extern inline void flush_icache_line(unsigned long addr) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache %1, (%0)\n\t" - ".set mips0\n\t" - ".set reorder" - : - : "r" (addr), - "i" (Hit_Invalidate_I)); -} - -extern inline void flush_dcache_line(unsigned long addr) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache %1, (%0)\n\t" - ".set mips0\n\t" - ".set reorder" - : - : "r" (addr), - "i" (Hit_Writeback_Inv_D)); -} - -extern inline void invalidate_dcache_line(unsigned long addr) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache %1, (%0)\n\t" - ".set mips0\n\t" - ".set reorder" - : - : "r" (addr), - "i" (Hit_Invalidate_D)); -} - - -/* - * The next two are for badland addresses like signal trampolines. - */ -extern inline void protected_flush_icache_line(unsigned long addr) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n" - "1:\tcache %1,(%0)\n" - "2:\t.set mips0\n\t" - ".set reorder\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,2b\n\t" - ".previous" - : - : "r" (addr), - "i" (Hit_Invalidate_I)); -} - -extern inline void protected_writeback_dcache_line(unsigned long addr) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n" - "1:\tcache %1,(%0)\n" - "2:\t.set mips0\n\t" - ".set reorder\n\t" - ".section\t__ex_table,\"a\"\n\t" - STR(PTR)"\t1b,2b\n\t" - ".previous" - : - : "r" (addr), - "i" (Hit_Writeback_D)); -} - - -#define cache32_unroll32(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, 0x000(%0); cache %1, 0x020(%0); \ - cache %1, 0x040(%0); cache %1, 0x060(%0); \ - cache %1, 0x080(%0); cache %1, 0x0a0(%0); \ - cache %1, 0x0c0(%0); cache %1, 0x0e0(%0); \ - cache %1, 0x100(%0); cache %1, 0x120(%0); \ - cache %1, 0x140(%0); cache %1, 0x160(%0); \ - cache %1, 0x180(%0); cache %1, 0x1a0(%0); \ - cache %1, 0x1c0(%0); cache %1, 0x1e0(%0); \ - cache %1, 0x200(%0); cache %1, 0x220(%0); \ - cache %1, 0x240(%0); cache %1, 0x260(%0); \ - cache %1, 0x280(%0); cache %1, 0x2a0(%0); \ - cache %1, 0x2c0(%0); cache %1, 0x2e0(%0); \ - cache %1, 0x300(%0); cache %1, 0x320(%0); \ - cache %1, 0x340(%0); cache %1, 0x360(%0); \ - cache %1, 0x380(%0); cache %1, 0x3a0(%0); \ - cache %1, 0x3c0(%0); cache %1, 0x3e0(%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -extern inline void blast_dcache32(void) -{ - unsigned long start = KSEG0; - unsigned long end = (start + dcache_size/2); - - while(start < end) { - cache32_unroll32(start,Index_Writeback_Inv_D); - cache32_unroll32(start+1,Index_Writeback_Inv_D); - start += 0x400; - } -} - -extern inline void blast_dcache32_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); - - while(start < end) { - cache32_unroll32(start,Hit_Writeback_Inv_D); - start += 0x400; - } -} - -extern inline void blast_dcache32_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); - - while(start < end) { - cache32_unroll32(start,Index_Writeback_Inv_D); - cache32_unroll32(start+1,Index_Writeback_Inv_D); - start += 0x400; - } -} - -extern inline void blast_icache32(void) -{ - unsigned long start = KSEG0; - unsigned long end = (start + icache_size/2); - - while(start < end) { - cache32_unroll32(start,Index_Invalidate_I); - cache32_unroll32(start+1,Index_Invalidate_I); - start += 0x400; - } -} - -extern inline void blast_icache32_page(unsigned long page) -{ - unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); - - while(start < end) { - cache32_unroll32(start,Hit_Invalidate_I); - start += 0x400; - } -} - -extern inline void blast_icache32_page_indexed(unsigned long page) -{ - unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); - - while(start < end) { - cache32_unroll32(start,Index_Invalidate_I); - cache32_unroll32(start+1,Index_Invalidate_I); - start += 0x400; - } -} - -/* -------------------------------------------------------------------- */ - -static void r5432_clear_page_d32(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "cache\t%3,-32(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D) - :"$1","memory"); -} - - - -/* - * This is still inefficient. We only can do better if we know the - * virtual address where the copy will be accessed. - */ - -static void r5432_copy_page_d32(void * to, void * from) -{ - unsigned long dummy1, dummy2; - unsigned long reg1, reg2, reg3, reg4; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%8\n" - "1:\tcache\t%9,(%0)\n\t" - "lw\t%2,(%1)\n\t" - "lw\t%3,4(%1)\n\t" - "lw\t%4,8(%1)\n\t" - "lw\t%5,12(%1)\n\t" - "sw\t%2,(%0)\n\t" - "sw\t%3,4(%0)\n\t" - "sw\t%4,8(%0)\n\t" - "sw\t%5,12(%0)\n\t" - "lw\t%2,16(%1)\n\t" - "lw\t%3,20(%1)\n\t" - "lw\t%4,24(%1)\n\t" - "lw\t%5,28(%1)\n\t" - "sw\t%2,16(%0)\n\t" - "sw\t%3,20(%0)\n\t" - "sw\t%4,24(%0)\n\t" - "sw\t%5,28(%0)\n\t" - "cache\t%9,32(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "lw\t%2,-32(%1)\n\t" - "lw\t%3,-28(%1)\n\t" - "lw\t%4,-24(%1)\n\t" - "lw\t%5,-20(%1)\n\t" - "sw\t%2,-32(%0)\n\t" - "sw\t%3,-28(%0)\n\t" - "sw\t%4,-24(%0)\n\t" - "sw\t%5,-20(%0)\n\t" - "lw\t%2,-16(%1)\n\t" - "lw\t%3,-12(%1)\n\t" - "lw\t%4,-8(%1)\n\t" - "lw\t%5,-4(%1)\n\t" - "sw\t%2,-16(%0)\n\t" - "sw\t%3,-12(%0)\n\t" - "sw\t%4,-8(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sw\t%5,-4(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), - "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) - :"0" (to), "1" (from), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D)); -} - - -/* - * If you think for one second that this stuff coming up is a lot - * of bulky code eating too many kernel cache lines. Think _again_. - * - * Consider: - * 1) Taken branches have a 3 cycle penalty on R4k - * 2) The branch itself is a real dead cycle on even R4600/R5000. - * 3) Only one of the following variants of each type is even used by - * the kernel based upon the cache parameters we detect at boot time. - * - * QED. - */ - -static inline void r5432_flush_cache_all_d32i32(void) -{ - blast_dcache32(); blast_icache32(); -} - -static void r5432_flush_cache_range_d32i32(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - struct mm_struct *mm = vma->vm_mm; - - if (mm->context != 0) { -#ifdef DEBUG_CACHE - printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); -#endif - blast_dcache32(); blast_icache32(); - } -} - -/* - * On architectures like the Sparc, we could get rid of lines in - * the cache created only by a certain context, but on the MIPS - * (and actually certain Sparc's) we cannot. - */ -static void r5432_flush_cache_mm_d32i32(struct mm_struct *mm) -{ - if (mm->context != 0) { -#ifdef DEBUG_CACHE - printk("cmm[%d]", (int)mm->context); -#endif - r5432_flush_cache_all_d32i32(); - } -} - -static void r5432_flush_cache_page_d32i32(struct vm_area_struct *vma, - unsigned long page) -{ - struct mm_struct *mm = vma->vm_mm; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - - /* - * If ownes no valid ASID yet, cannot possibly have gotten - * this page into the cache. - */ - if (mm->context == 0) - return; - -#ifdef DEBUG_CACHE - printk("cpage[%d,%08lx]", (int)mm->context, page); -#endif - page &= PAGE_MASK; - pgdp = pgd_offset(mm, page); - pmdp = pmd_offset(pgdp, page); - ptep = pte_offset(pmdp, page); - - /* - * If the page isn't marked valid, the page cannot possibly be - * in the cache. - */ - if (!(pte_val(*ptep) & _PAGE_PRESENT)) - return; - - /* - * Doing flushes for another ASID than the current one is - * too difficult since stupid R4k caches do a TLB translation - * for every cache flush operation. So we do indexed flushes - * in that case, which doesn't overly flush the cache too much. - */ - if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { - blast_dcache32_page(page); - } else { - /* - * Do indexed flush, too much work to get the (possible) - * tlb refills to work correctly. - */ - page = (KSEG0 + (page & (dcache_size - 1))); - blast_dcache32_page_indexed(page); - } -} - - -/* If the addresses passed to these routines are valid, they are - * either: - * - * 1) In KSEG0, so we can do a direct flush of the page. - * 2) In KSEG2, and since every process can translate those - * addresses all the time in kernel mode we can do a direct - * flush. - * 3) In KSEG1, no flush necessary. - */ -static void r5432_flush_page_to_ram_d32(struct page *page) -{ - blast_dcache32_page((unsigned long)page_address(page)); -} - -static void -r5432_flush_icache_range(unsigned long start, unsigned long end) -{ - r5432_flush_cache_all_d32i32(); -} - -/* - * Ok, this seriously sucks. We use them to flush a user page but don't - * know the virtual address, so we have to blast away the whole icache - * which is significantly more expensive than the real thing. - */ -static void -r5432_flush_icache_page_i32(struct vm_area_struct *vma, struct page *page) -{ - if (!(vma->vm_flags & VM_EXEC)) - return; - - r5432_flush_cache_all_d32i32(); -} - -/* - * Writeback and invalidate the primary cache dcache before DMA. - */ -static void -r5432_dma_cache_wback_inv_pc(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - - if (size >= dcache_size) { - flush_cache_all(); - } else { - a = addr & ~(dc_lsize - 1); - end = (addr + size) & ~(dc_lsize - 1); - while (1) { - flush_dcache_line(a); /* Hit_Writeback_Inv_D */ - if (a == end) break; - a += dc_lsize; - } - } - bc_wback_inv(addr, size); -} - -static void -r5432_dma_cache_inv_pc(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - - if (size >= dcache_size) { - flush_cache_all(); - } else { - a = addr & ~(dc_lsize - 1); - end = (addr + size) & ~(dc_lsize - 1); - while (1) { - flush_dcache_line(a); /* Hit_Writeback_Inv_D */ - if (a == end) break; - a += dc_lsize; - } - } - - bc_inv(addr, size); -} - -static void -r5432_dma_cache_wback(unsigned long addr, unsigned long size) -{ - panic("r5432_dma_cache called - should not happen.\n"); -} - -/* - * While we're protected against bad userland addresses we don't care - * very much about what happens in that case. Usually a segmentation - * fault will dump the process later on anyway ... - */ -static void r5432_flush_cache_sigtramp(unsigned long addr) -{ - protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); - protected_flush_icache_line(addr & ~(ic_lsize - 1)); -} - -#undef DEBUG_TLB -#undef DEBUG_TLBUPDATE - -#define NTLB_ENTRIES 48 /* Fixed on all R4XX0 variants... */ - -#define NTLB_ENTRIES_HALF 24 /* Fixed on all R4XX0 variants... */ - -void flush_tlb_all(void) -{ - unsigned long old_ctx; - int entry; - unsigned long flags; - -#ifdef DEBUG_TLB - printk("[tlball]"); -#endif - - local_irq_save(flags); - /* Save old context and create impossible VPN2 value */ - old_ctx = (get_entryhi() & 0xff); - set_entryhi(KSEG0); - set_entrylo0(0); - set_entrylo1(0); - BARRIER; - - entry = get_wired(); - - /* Blast 'em all away. */ - while(entry < NTLB_ENTRIES) { - set_index(entry); - BARRIER; - tlb_write_indexed(); - BARRIER; - entry++; - } - BARRIER; - set_entryhi(old_ctx); - local_irq_restore(flags); -} - -void flush_tlb_mm(struct mm_struct *mm) -{ - if (mm->context != 0) { - unsigned long flags; - -#ifdef DEBUG_TLB - printk("[tlbmm<%d>]", mm->context); -#endif - local_irq_save(flags); - get_new_mmu_context(mm, asid_cache); - if (mm == current->active_mm) - set_entryhi(mm->context & 0xff); - local_irq_restore(flags); - } -} - -void flush_tlb_range(struct mm_struct *mm, unsigned long start, - unsigned long end) -{ - if(mm->context != 0) { - unsigned long flags; - int size; - -#ifdef DEBUG_TLB - printk("[tlbrange<%02x,%08lx,%08lx>]", (mm->context & 0xff), - start, end); -#endif - local_irq_save(flags); - size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - size = (size + 1) >> 1; - if(size <= NTLB_ENTRIES_HALF) { - int oldpid = (get_entryhi() & 0xff); - int newpid = (mm->context & 0xff); - - start &= (PAGE_MASK << 1); - end += ((PAGE_SIZE << 1) - 1); - end &= (PAGE_MASK << 1); - while(start < end) { - int idx; - - set_entryhi(start | newpid); - start += (PAGE_SIZE << 1); - BARRIER; - tlb_probe(); - BARRIER; - idx = get_index(); - set_entrylo0(0); - set_entrylo1(0); - set_entryhi(KSEG0); - BARRIER; - if(idx < 0) - continue; - tlb_write_indexed(); - BARRIER; - } - set_entryhi(oldpid); - } else { - get_new_mmu_context(mm, asid_cache); - if (mm == current->active_mm) - set_entryhi(mm->context & 0xff); - } - local_irq_restore(flags); - } -} - -void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) -{ - if (vma->vm_mm->context != 0) { - unsigned long flags; - int oldpid, newpid, idx; - -#ifdef DEBUG_TLB - printk("[tlbpage<%d,%08lx>]", vma->vm_mm->context, page); -#endif - newpid = (vma->vm_mm->context & 0xff); - page &= (PAGE_MASK << 1); - local_irq_save(flags); - oldpid = (get_entryhi() & 0xff); - set_entryhi(page | newpid); - BARRIER; - tlb_probe(); - BARRIER; - idx = get_index(); - set_entrylo0(0); - set_entrylo1(0); - set_entryhi(KSEG0); - if(idx < 0) - goto finish; - BARRIER; - tlb_write_indexed(); - - finish: - BARRIER; - set_entryhi(oldpid); - local_irq_restore(flags); - } -} - -void pgd_init(unsigned long page) -{ - unsigned long *p = (unsigned long *) page; - int i; - - for(i = 0; i < USER_PTRS_PER_PGD; i+=8) { - p[i + 0] = (unsigned long) invalid_pte_table; - p[i + 1] = (unsigned long) invalid_pte_table; - p[i + 2] = (unsigned long) invalid_pte_table; - p[i + 3] = (unsigned long) invalid_pte_table; - p[i + 4] = (unsigned long) invalid_pte_table; - p[i + 5] = (unsigned long) invalid_pte_table; - p[i + 6] = (unsigned long) invalid_pte_table; - p[i + 7] = (unsigned long) invalid_pte_table; - } -} - -/* We will need multiple versions of update_mmu_cache(), one that just - * updates the TLB with the new pte(s), and another which also checks - * for the R4k "end of page" hardware bug and does the needy. - */ -void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) -{ - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - int idx, pid; - - /* - * Handle debugger faulting in for debugee. - */ - if (current->active_mm != vma->vm_mm) - return; - - pid = get_entryhi() & 0xff; - -#ifdef DEBUG_TLB - if((pid != (vma->vm_mm->context & 0xff)) || (vma->vm_mm->context == 0)) { - printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d tlbpid=%d\n", - (int) (vma->vm_mm->context & 0xff), pid); - } -#endif - - local_irq_save(flags); - address &= (PAGE_MASK << 1); - set_entryhi(address | (pid)); - pgdp = pgd_offset(vma->vm_mm, address); - BARRIER; - tlb_probe(); - BARRIER; - pmdp = pmd_offset(pgdp, address); - idx = get_index(); - ptep = pte_offset(pmdp, address); - BARRIER; - set_entrylo0(pte_val(*ptep++) >> 6); - set_entrylo1(pte_val(*ptep) >> 6); - set_entryhi(address | (pid)); - BARRIER; - if(idx < 0) { - tlb_write_random(); - } else { - tlb_write_indexed(); - } - BARRIER; - set_entryhi(pid); - BARRIER; - local_irq_restore(flags); -} - -void show_regs(struct pt_regs * regs) -{ - /* Saved main processor registers. */ - printk("$0 : %08lx %08lx %08lx %08lx\n", - 0UL, regs->regs[1], regs->regs[2], regs->regs[3]); - printk("$4 : %08lx %08lx %08lx %08lx\n", - regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); - printk("$8 : %08lx %08lx %08lx %08lx\n", - regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11]); - printk("$12: %08lx %08lx %08lx %08lx\n", - regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]); - printk("$16: %08lx %08lx %08lx %08lx\n", - regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19]); - printk("$20: %08lx %08lx %08lx %08lx\n", - regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]); - printk("$24: %08lx %08lx\n", - regs->regs[24], regs->regs[25]); - printk("$28: %08lx %08lx %08lx %08lx\n", - regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]); - - /* Saved cp0 registers. */ - printk("epc : %08lx %s\nStatus: %08lx\nCause : %08lx\n", - regs->cp0_epc, print_tainted(), regs->cp0_status, regs->cp0_cause); -} - -void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask) -{ - unsigned long flags; - unsigned long wired; - unsigned long old_pagemask; - unsigned long old_ctx; - - local_irq_save(flags); - /* Save old context and create impossible VPN2 value */ - old_ctx = (get_entryhi() & 0xff); - old_pagemask = get_pagemask(); - wired = get_wired(); - set_wired (wired + 1); - set_index (wired); - BARRIER; - set_pagemask (pagemask); - set_entryhi(entryhi); - set_entrylo0(entrylo0); - set_entrylo1(entrylo1); - BARRIER; - tlb_write_indexed(); - BARRIER; - - set_entryhi(old_ctx); - BARRIER; - set_pagemask (old_pagemask); - flush_tlb_all(); - local_irq_restore(flags); -} - -/* Detect and size the various r4k caches. */ -static void __init probe_icache(unsigned long config) -{ - icache_size = 1 << (12 + ((config >> 9) & 7)); - ic_lsize = 16 << ((config >> 5) & 1); - - printk("Primary instruction cache %dkb, linesize %d bytes.\n", - icache_size >> 10, ic_lsize); -} - -static void __init probe_dcache(unsigned long config) -{ - dcache_size = 1 << (12 + ((config >> 6) & 7)); - dc_lsize = 16 << ((config >> 4) & 1); - - printk("Primary data cache %dkb, linesize %d bytes.\n", - dcache_size >> 10, dc_lsize); -} - - -void __init ld_mmu_r5432(void) -{ - unsigned long config = read_32bit_cp0_register(CP0_CONFIG); - - printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID)); - - change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); - - probe_icache(config); - probe_dcache(config); - - _clear_page = r5432_clear_page_d32; - _copy_page = r5432_copy_page_d32; - _flush_cache_all = r5432_flush_cache_all_d32i32; - ___flush_cache_all = r5432_flush_cache_all_d32i32; - _flush_page_to_ram = r5432_flush_page_to_ram_d32; - _flush_cache_mm = r5432_flush_cache_mm_d32i32; - _flush_cache_range = r5432_flush_cache_range_d32i32; - _flush_cache_page = r5432_flush_cache_page_d32i32; - _flush_icache_page = r5432_flush_icache_page_i32; - _dma_cache_wback_inv = r5432_dma_cache_wback_inv_pc; - _dma_cache_wback = r5432_dma_cache_wback; - _dma_cache_inv = r5432_dma_cache_inv_pc; - - _flush_cache_sigtramp = r5432_flush_cache_sigtramp; - _flush_icache_range = r5432_flush_icache_range; /* Ouch */ - - __flush_cache_all(); - write_32bit_cp0_register(CP0_WIRED, 0); - - /* - * You should never change this register: - * - On R4600 1.7 the tlbp never hits for pages smaller than - * the value in the c0_pagemask register. - * - The entire mm handling assumes the c0_pagemask register to - * be set for 4kb pages. - */ - write_32bit_cp0_register(CP0_PAGEMASK, PM_4K); - flush_tlb_all(); -} --- linux-2.5.73/arch/mips/mm/rm7k.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,751 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * r4xx0.c: R4000 processor variant specific MMU/Cache routines. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997, 1998 Ralf Baechle ralf@gnu.org - * - * To do: - * - * - this code is a overbloated pig - * - many of the bug workarounds are not efficient at all, but at - * least they are functional ... - */ -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -/* CP0 hazard avoidance. */ -#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ - "nop; nop; nop; nop; nop; nop;\n\t" \ - ".set reorder\n\t") - -/* Primary cache parameters. */ -static int icache_size, dcache_size; /* Size in bytes */ - -#define ic_lsize 32 /* Fixed to 32 byte on RM7000 */ -#define dc_lsize 32 /* Fixed to 32 byte on RM7000 */ -#define sc_lsize 32 /* Fixed to 32 byte on RM7000 */ -#define tc_pagesize (32*128) - -/* Secondary cache parameters. */ -#define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */ - -#include -#include - -int rm7k_tcache_enabled = 0; - -/* - * Not added to asm/r4kcache.h because it seems to be RM7000-specific. - */ -#define Page_Invalidate_T 0x16 - -static inline void invalidate_tcache_page(unsigned long addr) -{ - __asm__ __volatile__( - ".set\tnoreorder\t\t\t# invalidate_tcache_page\n\t" - ".set\tmips3\n\t" - "cache\t%1, (%0)\n\t" - ".set\tmips0\n\t" - ".set\treorder" - : - : "r" (addr), - "i" (Page_Invalidate_T)); -} - -/* - * Zero an entire page. Note that while the RM7000 has a second level cache - * it doesn't have a Create_Dirty_Excl_SD operation. - */ -static void rm7k_clear_page(void * page) -{ - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%2\n" - "1:\tcache\t%3,(%0)\n\t" - "sd\t$0,(%0)\n\t" - "sd\t$0,8(%0)\n\t" - "sd\t$0,16(%0)\n\t" - "sd\t$0,24(%0)\n\t" - "daddiu\t%0,64\n\t" - "cache\t%3,-32(%0)\n\t" - "sd\t$0,-32(%0)\n\t" - "sd\t$0,-24(%0)\n\t" - "sd\t$0,-16(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sd\t$0,-8(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D) - :"$1","memory"); -} - - -/* - * Copy an entire page. Note that while the RM7000 has a second level cache - * it doesn't have a Create_Dirty_Excl_SD operation. - */ -static void rm7k_copy_page(void * to, void * from) -{ - unsigned long dummy1, dummy2; - unsigned long reg1, reg2, reg3, reg4; - - __asm__ __volatile__( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips3\n\t" - "daddiu\t$1,%0,%8\n" - "1:\tcache\t%9,(%0)\n\t" - "lw\t%2,(%1)\n\t" - "lw\t%3,4(%1)\n\t" - "lw\t%4,8(%1)\n\t" - "lw\t%5,12(%1)\n\t" - "sw\t%2,(%0)\n\t" - "sw\t%3,4(%0)\n\t" - "sw\t%4,8(%0)\n\t" - "sw\t%5,12(%0)\n\t" - "lw\t%2,16(%1)\n\t" - "lw\t%3,20(%1)\n\t" - "lw\t%4,24(%1)\n\t" - "lw\t%5,28(%1)\n\t" - "sw\t%2,16(%0)\n\t" - "sw\t%3,20(%0)\n\t" - "sw\t%4,24(%0)\n\t" - "sw\t%5,28(%0)\n\t" - "cache\t%9,32(%0)\n\t" - "daddiu\t%0,64\n\t" - "daddiu\t%1,64\n\t" - "lw\t%2,-32(%1)\n\t" - "lw\t%3,-28(%1)\n\t" - "lw\t%4,-24(%1)\n\t" - "lw\t%5,-20(%1)\n\t" - "sw\t%2,-32(%0)\n\t" - "sw\t%3,-28(%0)\n\t" - "sw\t%4,-24(%0)\n\t" - "sw\t%5,-20(%0)\n\t" - "lw\t%2,-16(%1)\n\t" - "lw\t%3,-12(%1)\n\t" - "lw\t%4,-8(%1)\n\t" - "lw\t%5,-4(%1)\n\t" - "sw\t%2,-16(%0)\n\t" - "sw\t%3,-12(%0)\n\t" - "sw\t%4,-8(%0)\n\t" - "bne\t$1,%0,1b\n\t" - "sw\t%5,-4(%0)\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - :"=r" (dummy1), "=r" (dummy2), - "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) - :"0" (to), "1" (from), - "I" (PAGE_SIZE), - "i" (Create_Dirty_Excl_D)); -} - -static void __flush_cache_all_d32i32(void) -{ - blast_dcache32(); - blast_icache32(); -} - -static inline void rm7k_flush_cache_all_d32i32(void) -{ - /* Yes! Caches that don't suck ... */ -} - -static void rm7k_flush_cache_range_d32i32(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - /* RM7000 caches are sane ... */ -} - -static void rm7k_flush_cache_mm_d32i32(struct mm_struct *mm) -{ - /* RM7000 caches are sane ... */ -} - -static void rm7k_flush_cache_page_d32i32(struct vm_area_struct *vma, - unsigned long page) -{ - /* RM7000 caches are sane ... */ -} - -static void rm7k_flush_page_to_ram_d32i32(struct page * page) -{ - /* Yes! Caches that don't suck! */ -} - -static void rm7k_flush_icache_range(unsigned long start, unsigned long end) -{ - /* - * FIXME: This is overdoing things and harms performance. - */ - __flush_cache_all_d32i32(); -} - -static void rm7k_flush_icache_page(struct vm_area_struct *vma, - struct page *page) -{ - /* - * FIXME: We should not flush the entire cache but establish some - * temporary mapping and use hit_invalidate operation to flush out - * the line from the cache. - */ - __flush_cache_all_d32i32(); -} - - -/* - * Writeback and invalidate the primary cache dcache before DMA. - * (XXX These need to be fixed ...) - */ -static void -rm7k_dma_cache_wback_inv(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - - a = addr & ~(sc_lsize - 1); - end = (addr + size) & ~(sc_lsize - 1); - while (1) { - flush_dcache_line(a); /* Hit_Writeback_Inv_D */ - flush_icache_line(a); /* Hit_Invalidate_I */ - flush_scache_line(a); /* Hit_Writeback_Inv_SD */ - if (a == end) break; - a += sc_lsize; - } - - if (!rm7k_tcache_enabled) - return; - - a = addr & ~(tc_pagesize - 1); - end = (addr + size) & ~(tc_pagesize - 1); - while(1) { - invalidate_tcache_page(a); /* Page_Invalidate_T */ - if (a == end) break; - a += tc_pagesize; - } -} - -static void -rm7k_dma_cache_inv(unsigned long addr, unsigned long size) -{ - unsigned long end, a; - - a = addr & ~(sc_lsize - 1); - end = (addr + size) & ~(sc_lsize - 1); - while (1) { - invalidate_dcache_line(a); /* Hit_Invalidate_D */ - flush_icache_line(a); /* Hit_Invalidate_I */ - invalidate_scache_line(a); /* Hit_Invalidate_SD */ - if (a == end) break; - a += sc_lsize; - } - - if (!rm7k_tcache_enabled) - return; - - a = addr & ~(tc_pagesize - 1); - end = (addr + size) & ~(tc_pagesize - 1); - while(1) { - invalidate_tcache_page(a); /* Page_Invalidate_T */ - if (a == end) break; - a += tc_pagesize; - } -} - -static void -rm7k_dma_cache_wback(unsigned long addr, unsigned long size) -{ - panic("rm7k_dma_cache_wback called - should not happen.\n"); -} - -/* - * While we're protected against bad userland addresses we don't care - * very much about what happens in that case. Usually a segmentation - * fault will dump the process later on anyway ... - */ -static void rm7k_flush_cache_sigtramp(unsigned long addr) -{ - protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); - protected_flush_icache_line(addr & ~(ic_lsize - 1)); -} - -/* - * Undocumented RM7000: Bit 29 in the info register of the RM7000 v2.0 - * indicates if the TLB has 48 or 64 entries. - * - * 29 1 => 64 entry JTLB - * 0 => 48 entry JTLB - */ -static inline int __attribute__((const)) ntlb_entries(void) -{ - if (get_info() & (1 << 29)) - return 64; - - return 48; -} - -void flush_tlb_all(void) -{ - unsigned long flags; - unsigned long old_ctx; - int entry; - - local_irq_save(flags); - /* Save old context and create impossible VPN2 value */ - old_ctx = get_entryhi() & 0xff; - set_entryhi(KSEG0); - set_entrylo0(0); - set_entrylo1(0); - BARRIER; - - entry = get_wired(); - - /* Blast 'em all away. */ - while (entry < ntlb_entries()) { - set_index(entry); - BARRIER; - tlb_write_indexed(); - BARRIER; - entry++; - } - BARRIER; - set_entryhi(old_ctx); - local_irq_restore(flags); -} - -void flush_tlb_mm(struct mm_struct *mm) -{ - if(mm->context != 0) { - unsigned long flags; - - local_irq_save(flags); - get_new_mmu_context(mm, asid_cache); - if (mm == current->mm) - set_entryhi(mm->context & 0xff); - local_irq_restore(flags); - } -} - -void flush_tlb_range(struct mm_struct *mm, unsigned long start, - unsigned long end) -{ - if(mm->context != 0) { - unsigned long flags; - int size; - - local_irq_save(flags); - size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; - size = (size + 1) >> 1; - if (size <= (ntlb_entries() / 2)) { - int oldpid = (get_entryhi() & 0xff); - int newpid = (mm->context & 0xff); - - start &= (PAGE_MASK << 1); - end += ((PAGE_SIZE << 1) - 1); - end &= (PAGE_MASK << 1); - while(start < end) { - int idx; - - set_entryhi(start | newpid); - start += (PAGE_SIZE << 1); - BARRIER; - tlb_probe(); - BARRIER; - idx = get_index(); - set_entrylo0(0); - set_entrylo1(0); - set_entryhi(KSEG0); - BARRIER; - if(idx < 0) - continue; - tlb_write_indexed(); - BARRIER; - } - set_entryhi(oldpid); - } else { - get_new_mmu_context(mm, asid_cache); - if(mm == current->mm) - set_entryhi(mm->context & 0xff); - } - local_irq_restore(flags); - } -} - -void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) -{ - if(vma->vm_mm->context != 0) { - unsigned long flags; - int oldpid, newpid, idx; - - newpid = (vma->vm_mm->context & 0xff); - page &= (PAGE_MASK << 1); - local_irq_save(flags); - oldpid = (get_entryhi() & 0xff); - set_entryhi(page | newpid); - BARRIER; - tlb_probe(); - BARRIER; - idx = get_index(); - set_entrylo0(0); - set_entrylo1(0); - set_entryhi(KSEG0); - if(idx < 0) - goto finish; - BARRIER; - tlb_write_indexed(); - - finish: - BARRIER; - set_entryhi(oldpid); - local_irq_restore(flags); - } -} - -void pgd_init(unsigned long page) -{ - unsigned long *p = (unsigned long *) page; - int i; - - for (i = 0; i < USER_PTRS_PER_PGD; i+=8) { - p[i + 0] = (unsigned long) invalid_pte_table; - p[i + 1] = (unsigned long) invalid_pte_table; - p[i + 2] = (unsigned long) invalid_pte_table; - p[i + 3] = (unsigned long) invalid_pte_table; - p[i + 4] = (unsigned long) invalid_pte_table; - p[i + 5] = (unsigned long) invalid_pte_table; - p[i + 6] = (unsigned long) invalid_pte_table; - p[i + 7] = (unsigned long) invalid_pte_table; - } -} - -/* - * We will need multiple versions of update_mmu_cache(), one that just - * updates the TLB with the new pte(s), and another which also checks - * for the R4k "end of page" hardware bug and does the needy. - */ -void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t pte) -{ - unsigned long flags; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - int idx, pid; - - /* - * Handle debugger faulting in for debugee. - */ - if (current->active_mm != vma->vm_mm) - return; - - pid = get_entryhi() & 0xff; - - local_irq_save(flags); - address &= (PAGE_MASK << 1); - set_entryhi(address | (pid)); - pgdp = pgd_offset(vma->vm_mm, address); - BARRIER; - tlb_probe(); - BARRIER; - pmdp = pmd_offset(pgdp, address); - idx = get_index(); - ptep = pte_offset(pmdp, address); - BARRIER; - set_entrylo0(pte_val(*ptep++) >> 6); - set_entrylo1(pte_val(*ptep) >> 6); - set_entryhi(address | (pid)); - BARRIER; - if (idx < 0) { - tlb_write_random(); - } else { - tlb_write_indexed(); - } - BARRIER; - set_entryhi(pid); - BARRIER; - local_irq_restore(flags); -} - -void show_regs(struct pt_regs * regs) -{ - /* Saved main processor registers. */ - printk(KERN_INFO "$0 : %08lx %08lx %08lx %08lx\n", - 0UL, regs->regs[1], regs->regs[2], regs->regs[3]); - printk(KERN_INFO "$4 : %08lx %08lx %08lx %08lx\n", - regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); - printk(KERN_INFO "$8 : %08lx %08lx %08lx %08lx\n", - regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11]); - printk(KERN_INFO "$12: %08lx %08lx %08lx %08lx\n", - regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]); - printk(KERN_INFO "$16: %08lx %08lx %08lx %08lx\n", - regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19]); - printk(KERN_INFO "$20: %08lx %08lx %08lx %08lx\n", - regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]); - printk(KERN_INFO "$24: %08lx %08lx\n", - regs->regs[24], regs->regs[25]); - printk(KERN_INFO "$28: %08lx %08lx %08lx %08lx\n", - regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]); - - /* Saved cp0 registers. */ - printk(KERN_INFO "epc : %08lx %s\nStatus: %08lx\nCause : %08lx\n", - regs->cp0_epc, print_tainted(), regs->cp0_status, regs->cp0_cause); -} - -void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask) -{ - unsigned long flags; - unsigned long wired; - unsigned long old_pagemask; - unsigned long old_ctx; - - local_irq_save(flags); - /* Save old context and create impossible VPN2 value */ - old_ctx = (get_entryhi() & 0xff); - old_pagemask = get_pagemask(); - wired = get_wired(); - set_wired (wired + 1); - set_index (wired); - BARRIER; - set_pagemask (pagemask); - set_entryhi(entryhi); - set_entrylo0(entrylo0); - set_entrylo1(entrylo1); - BARRIER; - tlb_write_indexed(); - BARRIER; - - set_entryhi(old_ctx); - BARRIER; - set_pagemask (old_pagemask); - flush_tlb_all(); - local_irq_restore(flags); -} - -/* Used for loading TLB entries before trap_init() has started, when we - don't actually want to add a wired entry which remains throughout the - lifetime of the system */ - -static int temp_tlb_entry __initdata; - -__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, - unsigned long entryhi, unsigned long pagemask) -{ - int ret = 0; - unsigned long flags; - unsigned long wired; - unsigned long old_pagemask; - unsigned long old_ctx; - - local_irq_save(flags); - /* Save old context and create impossible VPN2 value */ - old_ctx = (get_entryhi() & 0xff); - old_pagemask = get_pagemask(); - wired = get_wired(); - if (--temp_tlb_entry < wired) { - printk(KERN_WARNING "No TLB space left for add_temporary_entry\n"); - ret = -ENOSPC; - goto out; - } - - set_index (temp_tlb_entry); - BARRIER; - set_pagemask (pagemask); - set_entryhi(entryhi); - set_entrylo0(entrylo0); - set_entrylo1(entrylo1); - BARRIER; - tlb_write_indexed(); - BARRIER; - - set_entryhi(old_ctx); - BARRIER; - set_pagemask (old_pagemask); - out: - local_irq_restore(flags); - return ret; -} - - - -/* Detect and size the caches. */ -static inline void probe_icache(unsigned long config) -{ - icache_size = 1 << (12 + ((config >> 9) & 7)); - - printk(KERN_INFO "Primary instruction cache %dKiB.\n", icache_size >> 10); -} - -static inline void probe_dcache(unsigned long config) -{ - dcache_size = 1 << (12 + ((config >> 6) & 7)); - - printk(KERN_INFO "Primary data cache %dKiB.\n", dcache_size >> 10); -} - - -/* - * This function is executed in the uncached segment KSEG1. - * It must not touch the stack, because the stack pointer still points - * into KSEG0. - * - * Three options: - * - Write it in assembly and guarantee that we don't use the stack. - * - Disable caching for KSEG0 before calling it. - * - Pray that GCC doesn't randomly start using the stack. - * - * This being Linux, we obviously take the least sane of those options - - * following DaveM's lead in r4xx0.c - * - * It seems we get our kicks from relying on unguaranteed behaviour in GCC - */ -static __init void setup_scache(void) -{ - int register i; - - set_cp0_config(1<<3 /* CONF_SE */); - - set_taglo(0); - set_taghi(0); - - for (i=0; i> 31) & 1) - return; - - printk(KERN_INFO "Secondary cache %dKiB, linesize %d bytes.\n", - (scache_size >> 10), sc_lsize); - - if ((config >> 3) & 1) - return; - - printk(KERN_INFO "Enabling secondary cache..."); - func(); - printk("Done\n"); -} - -static inline void probe_tcache(unsigned long config) -{ - if ((config >> 17) & 1) - return; - - /* We can't enable the L3 cache yet. There may be board-specific - * magic necessary to turn it on, and blindly asking the CPU to - * start using it would may give cache errors. - * - * Also, board-specific knowledge may allow us to use the - * CACHE Flash_Invalidate_T instruction if the tag RAM supports - * it, and may specify the size of the L3 cache so we don't have - * to probe it. - */ - printk(KERN_INFO "Tertiary cache present, %s enabled\n", - config&(1<<12) ? "already" : "not (yet)"); - - if ((config >> 12) & 1) - rm7k_tcache_enabled = 1; -} - -void __init ld_mmu_rm7k(void) -{ - unsigned long config = read_32bit_cp0_register(CP0_CONFIG); - unsigned long addr; - - printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID)); - - change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); - - /* RM7000 erratum #31. The icache is screwed at startup. */ - set_taglo(0); - set_taghi(0); - for (addr = KSEG0; addr <= KSEG0 + 4096; addr += ic_lsize) { - __asm__ __volatile__ ( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache\t%1, 0(%0)\n\t" - "cache\t%1, 0x1000(%0)\n\t" - "cache\t%1, 0x2000(%0)\n\t" - "cache\t%1, 0x3000(%0)\n\t" - "cache\t%2, 0(%0)\n\t" - "cache\t%2, 0x1000(%0)\n\t" - "cache\t%2, 0x2000(%0)\n\t" - "cache\t%2, 0x3000(%0)\n\t" - "cache\t%1, 0(%0)\n\t" - "cache\t%1, 0x1000(%0)\n\t" - "cache\t%1, 0x2000(%0)\n\t" - "cache\t%1, 0x3000(%0)\n\t" - ".set\tmips0\n\t" - ".set\treorder\n\t" - : - : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); - } - -#ifndef CONFIG_MIPS_UNCACHED - change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); -#endif - - probe_icache(config); - probe_dcache(config); - probe_scache(config); - probe_tcache(config); - - printk("TLB has %d entries.\n", ntlb_entries()); - - _clear_page = rm7k_clear_page; - _copy_page = rm7k_copy_page; - - _flush_cache_all = rm7k_flush_cache_all_d32i32; - ___flush_cache_all = __flush_cache_all_d32i32; - _flush_cache_mm = rm7k_flush_cache_mm_d32i32; - _flush_cache_range = rm7k_flush_cache_range_d32i32; - _flush_cache_page = rm7k_flush_cache_page_d32i32; - _flush_page_to_ram = rm7k_flush_page_to_ram_d32i32; - _flush_cache_sigtramp = rm7k_flush_cache_sigtramp; - _flush_icache_range = rm7k_flush_icache_range; - _flush_icache_page = rm7k_flush_icache_page; - - _dma_cache_wback_inv = rm7k_dma_cache_wback_inv; - _dma_cache_wback = rm7k_dma_cache_wback; - _dma_cache_inv = rm7k_dma_cache_inv; - - __flush_cache_all_d32i32(); - write_32bit_cp0_register(CP0_WIRED, 0); - temp_tlb_entry = ntlb_entries() - 1; - write_32bit_cp0_register(CP0_PAGEMASK, PM_4K); - flush_tlb_all(); -} --- linux-2.5.73/arch/mips/mm/sb1.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,436 +0,0 @@ -/* - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 2000 Sibyte - * - * Written by Justin Carlson (carlson@sibyte.com) - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ - - -/* - * In this entire file, I'm not sure what the role of the L2 on the sb1250 - * is. Since it is coherent to the system, we should never need to flush - * it...right?...right??? -JDC - */ - -#include - -/* These are probed at ld_mmu time */ -static unsigned int icache_size; -static unsigned int dcache_size; - -static unsigned int icache_line_size; -static unsigned int dcache_line_size; - -static unsigned int icache_assoc; -static unsigned int dcache_assoc; - -static unsigned int icache_sets; -static unsigned int dcache_sets; -static unsigned int tlb_entries; - -void pgd_init(unsigned long page) -{ - unsigned long *p = (unsigned long *) page; - int i; - - for (i = 0; i < USER_PTRS_PER_PGD; i+=8) { - p[i + 0] = (unsigned long) invalid_pte_table; - p[i + 1] = (unsigned long) invalid_pte_table; - p[i + 2] = (unsigned long) invalid_pte_table; - p[i + 3] = (unsigned long) invalid_pte_table; - p[i + 4] = (unsigned long) invalid_pte_table; - p[i + 5] = (unsigned long) invalid_pte_table; - p[i + 6] = (unsigned long) invalid_pte_table; - p[i + 7] = (unsigned long) invalid_pte_table; - } -} - -void flush_tlb_all(void) -{ - unsigned long flags; - unsigned long old_ctx; - int entry; - - local_irq_save(flags); - /* Save old context and create impossible VPN2 value */ - old_ctx = (get_entryhi() & 0xff); - set_entrylo0(0); - set_entrylo1(0); - for (entry = 0; entry < tlb_entries; entry++) { - set_entryhi(KSEG0 + (PAGE_SIZE << 1) * entry); - set_index(entry); - tlb_write_indexed(); - } - set_entryhi(old_ctx); - local_irq_restore(flags); -} - - - -/* These are the functions hooked by the memory management function pointers */ -static void sb1_clear_page(void *page) -{ - /* JDCXXX - This should be bottlenecked by the write buffer, but these - things tend to be mildly unpredictable...should check this on the - performance model */ - - /* We prefetch 4 lines ahead. We're also "cheating" slightly here... - since we know we're on an SB1, we force the assembler to take - 64-bit operands to speed things up */ - __asm__ __volatile__( - ".set push \n" - ".set noreorder \n" - ".set noat \n" - ".set mips4 \n" - " addiu $1, %0, %2 \n" /* Calculate the end of the page to clear */ - " pref 5, 0(%0) \n" /* Prefetch the first 4 lines */ - " pref 5, 32(%0) \n" - " pref 5, 64(%0) \n" - " pref 5, 96(%0) \n" - "1: sd $0, 0(%0) \n" /* Throw out a cacheline of 0's */ - " sd $0, 8(%0) \n" - " sd $0, 16(%0) \n" - " sd $0, 24(%0) \n" - " pref 5,128(%0) \n" /* Prefetch 4 lines ahead */ - " bne $1, %0, 1b \n" - " addiu %0, %0, 32 \n" /* Next cacheline (This instruction better be short piped!) */ - ".set pop \n" - :"=r" (page) - :"0" (page), - "I" (PAGE_SIZE-32) - :"$1","memory"); - -} - -static void sb1_copy_page(void *to, void *from) -{ - - /* This should be optimized in assembly...can't use ld/sd, though, - * because the top 32 bits could be nuked if we took an interrupt - * during the routine. And this is not a good place to be cli()'ing - */ - - /* The pref's used here are using "streaming" hints, which cause the - * copied data to be kicked out of the cache sooner. A page copy often - * ends up copying a lot more data than is commonly used, so this seems - * to make sense in terms of reducing cache pollution, but I've no real - * performance data to back this up - */ - - __asm__ __volatile__( - ".set push \n" - ".set noreorder \n" - ".set noat \n" - ".set mips4 \n" - " addiu $1, %0, %4 \n" /* Calculate the end of the page to copy */ - " pref 4, 0(%0) \n" /* Prefetch the first 3 lines to be read and copied */ - " pref 5, 0(%1) \n" - " pref 4, 32(%0) \n" - " pref 5, 32(%1) \n" - " pref 4, 64(%0) \n" - " pref 5, 64(%1) \n" - "1: lw $2, 0(%0) \n" /* Block copy a cacheline */ - " lw $3, 4(%0) \n" - " lw $4, 8(%0) \n" - " lw $5, 12(%0) \n" - " lw $6, 16(%0) \n" - " lw $7, 20(%0) \n" - " lw $8, 24(%0) \n" - " lw $9, 28(%0) \n" - " pref 4, 96(%0) \n" /* Prefetch ahead */ - " pref 5, 96(%1) \n" - " sw $2, 0(%1) \n" - " sw $3, 4(%1) \n" - " sw $4, 8(%1) \n" - " sw $5, 12(%1) \n" - " sw $6, 16(%1) \n" - " sw $7, 20(%1) \n" - " sw $8, 24(%1) \n" - " sw $9, 28(%1) \n" - " addiu %1, %1, 32 \n" /* Next cacheline */ - " nop \n" /* Force next add to short pipe */ - " nop \n" /* Force next add to short pipe */ - " bne $1, %0, 1b \n" - " addiu %0, %0, 32 \n" /* Next cacheline */ - ".set pop \n" - :"=r" (to), - "=r" (from) - : - "0" (from), - "1" (to), - "I" (PAGE_SIZE-32) - :"$1","$2","$3","$4","$5","$6","$7","$8","$9","memory"); -/* - unsigned long *src = from; - unsigned long *dest = to; - unsigned long *target = (unsigned long *) (((unsigned long)src) + PAGE_SIZE); - while (src != target) { - *dest++ = *src++; - } -*/ -} - -/* - * The dcache is fully coherent to the system, with one - * big caveat: the instruction stream. In other words, - * if we miss in the icache, and have dirty data in the - * L1 dcache, then we'll go out to memory (or the L2) and - * get the not-as-recent data. - * - * So the only time we have to flush the dcache is when - * we're flushing the icache. Since the L2 is fully - * coherent to everything, including I/O, we never have - * to flush it - */ - -static void sb1_flush_cache_all(void) -{ - - /* - * Haven't worried too much about speed here; given that we're flushing - * the icache, the time to invalidate is dwarfed by the time it's going - * to take to refill it. Register usage: - * - * $1 - moving cache index - * $2 - set count - */ - if (icache_sets) { - __asm__ __volatile__ ( - ".set push \n" - ".set noreorder \n" - ".set noat \n" - ".set mips4 \n" - " move $1, %2 \n" /* Start at index 0 */ - "1: cache 0, 0($1) \n" /* Invalidate this index */ - " addiu %1, %1, -1 \n" /* Decrement loop count */ - " bnez %1, 1b \n" /* loop test */ - " addu $1, $1, %0 \n" /* Next address JDCXXX - Should be short piped */ - ".set pop \n" - ::"r" (icache_line_size), - "r" (icache_sets * icache_assoc), - "r" (KSEG0) - :"$1"); - } - if (dcache_sets) { - __asm__ __volatile__ ( - ".set push \n" - ".set noreorder \n" - ".set noat \n" - ".set mips4 \n" - " move $1, %2 \n" /* Start at index 0 */ - "1: cache 0x1, 0($1) \n" /* WB/Invalidate this index */ - " addiu %1, %1, -1 \n" /* Decrement loop count */ - " bnez %1, 1b \n" /* loop test */ - " addu $1, $1, %0 \n" /* Next address JDCXXX - Should be short piped */ - ".set pop \n" - ::"r" (dcache_line_size), - "r" (dcache_sets * dcache_assoc), - "r" (KSEG0) - :"$1"); - } -} - -/* - * When flushing a range in the icache, we have to first writeback - * the dcache for the same range, so new ifetches will see any - * data that was dirty in the dcache - */ - -static void sb1_flush_icache_range(unsigned long start, unsigned long end) -{ - - /* JDCXXX - Implement me! */ - sb1_flush_cache_all(); -} - -static void sb1_flush_cache_mm(struct mm_struct *mm) -{ - /* Don't need to do this, as the dcache is physically tagged */ -} - -static void sb1_flush_cache_range(struct vm_area_struct *vma, - unsigned long start, - unsigned long end) -{ - /* Don't need to do this, as the dcache is physically tagged */ -} - - -static void sb1_flush_cache_sigtramp(unsigned long page) -{ - /* JDCXXX - Implement me! */ - sb1_flush_cache_all(); -} - - -/* - * This only needs to make sure stores done up to this - * point are visible to other agents outside the CPU. Given - * the coherent nature of the ZBus, all that's required here is - * a sync to make sure the data gets out to the caches and is - * visible to an arbitrary A Phase from an external agent - * - * Actually, I'm not even sure that's necessary; the semantics - * of this function aren't clear. If it's supposed to serve as - * a memory barrier, this is needed. If it's only meant to - * prevent data from being invisible to non-cpu memory accessors - * for some indefinite period of time (e.g. in a non-coherent - * dcache) then this function would be a complete nop. - */ -static void sb1_flush_page_to_ram(struct page *page) -{ - __asm__ __volatile__( - " sync \n" /* Short pipe */ - :::"memory"); -} - - -/* Cribbed from the r2300 code */ -static void sb1_flush_cache_page(struct vm_area_struct *vma, - unsigned long page) -{ - sb1_flush_cache_all(); -#if 0 - struct mm_struct *mm = vma->vm_mm; - unsigned long physpage; - - /* No icache flush needed without context; */ - if (mm->context == 0) - return; - - /* No icache flush needed if the page isn't executable */ - if (!(vma->vm_flags & VM_EXEC)) - return; - - physpage = (unsigned long) page_address(page); - if (physpage) - sb1_flush_icache_range(physpage, physpage + PAGE_SIZE); -#endif -} - - -/* - * Cache set values (from the mips64 spec) - * 0 - 64 - * 1 - 128 - * 2 - 256 - * 3 - 512 - * 4 - 1024 - * 5 - 2048 - * 6 - 4096 - * 7 - Reserved - */ -static unsigned int decode_cache_sets(unsigned int config_field) -{ - if (config_field == 7) { - /* JDCXXX - Find a graceful way to abort. */ - return 0; - } - - return (1<<(config_field + 6)); -} - -/* - * Cache line size values (from the mips64 spec) - * 0 - No cache present. - * 1 - 4 bytes - * 2 - 8 bytes - * 3 - 16 bytes - * 4 - 32 bytes - * 5 - 64 bytes - * 6 - 128 bytes - * 7 - Reserved - */ -static unsigned int decode_cache_line_size(unsigned int config_field) -{ - if (config_field == 0) { - return 0; - } else if (config_field == 7) { - /* JDCXXX - Find a graceful way to abort. */ - return 0; - } - return (1<<(config_field + 1)); -} - -/* - * Relevant bits of the config1 register format (from the MIPS32/MIPS64 specs) - * - * 24:22 Icache sets per way - * 21:19 Icache line size - * 18:16 Icache Associativity - * 15:13 Dcache sets per way - * 12:10 Dcache line size - * 9:7 Dcache Associativity - */ - - -static void probe_cache_sizes(void) -{ - u32 config1; - - __asm__ __volatile__( - ".set push \n" - ".set mips64 \n" - " mfc0 %0, $16, 1 \n" /* Get config1 register */ - ".set pop \n" - :"=r" (config1)); - icache_line_size = decode_cache_line_size((config1 >> 19) & 0x7); - dcache_line_size = decode_cache_line_size((config1 >> 10) & 0x7); - icache_sets = decode_cache_sets((config1 >> 22) & 0x7); - dcache_sets = decode_cache_sets((config1 >> 13) & 0x7); - icache_assoc = ((config1 >> 16) & 0x7) + 1; - dcache_assoc = ((config1 >> 7) & 0x7) + 1; - icache_size = icache_line_size * icache_sets * icache_assoc; - dcache_size = dcache_line_size * dcache_sets * dcache_assoc; - tlb_entries = ((config1 >> 25) & 0x3f) + 1; -} - - -/* This is called from loadmmu.c. We have to set up all the - memory management function pointers, as well as initialize - the caches and tlbs */ -void ld_mmu_sb1(void) -{ - probe_cache_sizes(); - - _clear_page = sb1_clear_page; - _copy_page = sb1_copy_page; - - _flush_cache_all = sb1_flush_cache_all; - _flush_cache_mm = sb1_flush_cache_mm; - _flush_cache_range = sb1_flush_cache_range; - _flush_cache_page = sb1_flush_cache_page; - _flush_cache_sigtramp = sb1_flush_cache_sigtramp; - - _flush_page_to_ram = sb1_flush_page_to_ram; - _flush_icache_page = sb1_flush_cache_page; - _flush_icache_range = sb1_flush_icache_range; - - - /* - * JDCXXX I'm not sure whether these are necessary: is this the right - * place to initialize the tlb? If it is, why is it done - * at this level instead of as common code in loadmmu()? - */ - flush_cache_all(); - flush_tlb_all(); - - /* Turn on caching in kseg0 */ - set_cp0_config(CONF_CM_CMASK, 0); -} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/sc-ip22.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,177 @@ +/* + * sc-ip22.c: Indy cache management functions. + * + * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org), + * derived from r4xx0.c by David S. Miller (dm@engr.sgi.com). + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* Secondary cache size in bytes, if present. */ +static unsigned long scache_size; + +#undef DEBUG_CACHE + +#define SC_SIZE 0x00080000 +#define SC_LINE 32 +#define CI_MASK (SC_SIZE - SC_LINE) +#define SC_INDEX(n) ((n) & CI_MASK) + +static inline void indy_sc_wipe(unsigned long first, unsigned long last) +{ + unsigned long tmp; + + __asm__ __volatile__( + ".set\tpush\t\t\t# indy_sc_wipe\n\t" + ".set\tnoreorder\n\t" + ".set\tmips3\n\t" + ".set\tnoat\n\t" + "mfc0\t%2, $12\n\t" + "li\t$1, 0x80\t\t\t# Go 64 bit\n\t" + "mtc0\t$1, $12\n\t" + + "dli\t$1, 0x9000000080000000\n\t" + "or\t%0, $1\t\t\t# first line to flush\n\t" + "or\t%1, $1\t\t\t# last line to flush\n\t" + ".set\tat\n\t" + + "1:\tsw\t$0, 0(%0)\n\t" + "bne\t%0, %1, 1b\n\t" + " daddu\t%0, 32\n\t" + + "mtc0\t%2, $12\t\t\t# Back to 32 bit\n\t" + "nop; nop; nop; nop;\n\t" + ".set\tpop" + : "=r" (first), "=r" (last), "=&r" (tmp) + : "0" (first), "1" (last)); +} + +static void indy_sc_wback_invalidate(unsigned long addr, unsigned long size) +{ + unsigned long first_line, last_line; + unsigned int flags; + +#ifdef DEBUG_CACHE + printk("indy_sc_wback_invalidate[%08lx,%08lx]", addr, size); +#endif + + if (!size) + return; + + /* Which lines to flush? */ + first_line = SC_INDEX(addr); + last_line = SC_INDEX(addr + size - 1); + + local_irq_save(flags); + if (first_line <= last_line) { + indy_sc_wipe(first_line, last_line); + goto out; + } + + indy_sc_wipe(first_line, SC_SIZE - SC_LINE); + indy_sc_wipe(0, last_line); +out: + local_irq_restore(flags); +} + +static void indy_sc_enable(void) +{ + unsigned long addr, tmp1, tmp2; + + /* This is really cool... */ +#ifdef DEBUG_CACHE + printk("Enabling R4600 SCACHE\n"); +#endif + __asm__ __volatile__( + ".set\tpush\n\t" + ".set\tnoreorder\n\t" + ".set\tmips3\n\t" + "mfc0\t%2, $12\n\t" + "nop; nop; nop; nop;\n\t" + "li\t%1, 0x80\n\t" + "mtc0\t%1, $12\n\t" + "nop; nop; nop; nop;\n\t" + "li\t%0, 0x1\n\t" + "dsll\t%0, 31\n\t" + "lui\t%1, 0x9000\n\t" + "dsll32\t%1, 0\n\t" + "or\t%0, %1, %0\n\t" + "sb\t$0, 0(%0)\n\t" + "mtc0\t$0, $12\n\t" + "nop; nop; nop; nop;\n\t" + "mtc0\t%2, $12\n\t" + "nop; nop; nop; nop;\n\t" + ".set\tpop" + : "=r" (tmp1), "=r" (tmp2), "=r" (addr)); +} + +static void indy_sc_disable(void) +{ + unsigned long tmp1, tmp2, tmp3; + +#ifdef DEBUG_CACHE + printk("Disabling R4600 SCACHE\n"); +#endif + __asm__ __volatile__( + ".set\tpush\n\t" + ".set\tnoreorder\n\t" + ".set\tmips3\n\t" + "li\t%0, 0x1\n\t" + "dsll\t%0, 31\n\t" + "lui\t%1, 0x9000\n\t" + "dsll32\t%1, 0\n\t" + "or\t%0, %1, %0\n\t" + "mfc0\t%2, $12\n\t" + "nop; nop; nop; nop\n\t" + "li\t%1, 0x80\n\t" + "mtc0\t%1, $12\n\t" + "nop; nop; nop; nop\n\t" + "sh\t$0, 0(%0)\n\t" + "mtc0\t$0, $12\n\t" + "nop; nop; nop; nop\n\t" + "mtc0\t%2, $12\n\t" + "nop; nop; nop; nop\n\t" + ".set\tpop" + : "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)); +} + +static inline int __init indy_sc_probe(void) +{ + unsigned int size = ip22_eeprom_read(&sgimc->eeprom, 17); + if (size == 0) + return 0; + + size <<= PAGE_SHIFT; + printk(KERN_INFO "R4600/R5000 SCACHE size %ldK, linesize 32 bytes.\n", + size >> 10); + scache_size = size; + + return 1; +} + +/* XXX Check with wje if the Indy caches can differenciate between + writeback + invalidate and just invalidate. */ +struct bcache_ops indy_sc_ops = { + .bc_enable = indy_sc_enable, + .bc_disable = indy_sc_disable, + .bc_wback_inv = indy_sc_wback_invalidate, + .bc_inv = indy_sc_wback_invalidate +}; + +void __init indy_sc_init(void) +{ + if (indy_sc_probe()) { + indy_sc_enable(); + bcops = &indy_sc_ops; + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/sc-r5k.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,115 @@ +/* + * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org), + * derived from r4xx0.c by David S. Miller (dm@engr.sgi.com). + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* Secondary cache size in bytes, if present. */ +static unsigned long scache_size; + +#define SC_LINE 32 +#define SC_PAGE (128*SC_LINE) + +#define cache_op(base,op) \ +__asm__ __volatile__(" \ + .set noreorder; \ + .set mips3; \ + cache %1, (%0); \ + .set mips0; \ + .set reorder" \ + : \ + : "r" (base), \ + "i" (op)); + +static inline void blast_r5000_scache(void) +{ + unsigned long start = KSEG0; + unsigned long end = KSEG0 + scache_size; + + while(start < end) { + cache_op(start, R5K_Page_Invalidate_S); + start += SC_PAGE; + } +} + +static void r5k_dma_cache_inv_sc(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + + if (size >= scache_size) { + blast_r5000_scache(); + return; + } + + /* On the R5000 secondary cache we cannot + * invalidate less than a page at a time. + * The secondary cache is physically indexed, write-through. + */ + a = addr & ~(SC_PAGE - 1); + end = (addr + size - 1) & ~(SC_PAGE - 1); + while (a <= end) { + cache_op(a, R5K_Page_Invalidate_S); + a += SC_PAGE; + } +} + +static void r5k_sc_enable(void) +{ + unsigned long flags; + + local_irq_save(flags); + change_c0_config(R5K_CONF_SE, R5K_CONF_SE); + blast_r5000_scache(); + local_irq_restore(flags); +} + +static void r5k_sc_disable(void) +{ + unsigned long flags; + + local_irq_save(flags); + blast_r5000_scache(); + change_c0_config(R5K_CONF_SE, 0); + local_irq_restore(flags); +} + +static inline int __init r5k_sc_probe(void) +{ + unsigned long config = read_c0_config(); + + if (config & CONF_SC) + return(0); + + scache_size = (512 * 1024) << ((config & R5K_CONF_SS) >> 20); + + printk("R5000 SCACHE size %ldkB, linesize 32 bytes.\n", + scache_size >> 10); + + return 1; +} + +static struct bcache_ops r5k_sc_ops = { + .bc_enable = r5k_sc_enable, + .bc_disable = r5k_sc_disable, + .bc_wback_inv = r5k_dma_cache_inv_sc, + .bc_inv = r5k_dma_cache_inv_sc +}; + +void __init r5k_sc_init(void) +{ + if (r5k_sc_probe()) { + r5k_sc_enable(); + bcops = &r5k_sc_ops; + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/sc-rm7k.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,191 @@ +/* + * sc-rm7k.c: RM7000 cache management functions. + * + * Copyright (C) 1997, 2001, 2003 Ralf Baechle (ralf@gnu.org), + */ +#include +#include +#include + +#include +#include +#include +#include +#include + +/* Primary cache parameters. */ +#define sc_lsize 32 +#define tc_pagesize (32*128) + +/* Secondary cache parameters. */ +#define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */ + +extern unsigned long icache_way_size, dcache_way_size; + +#include + +int rm7k_tcache_enabled; + +/* + * Writeback and invalidate the primary cache dcache before DMA. + * (XXX These need to be fixed ...) + */ +static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + +#ifdef DEBUG_CACHE + printk("rm7k_sc_wback_inv[%08lx,%08lx]", addr, size); +#endif + + a = addr & ~(sc_lsize - 1); + end = (addr + size - 1) & ~(sc_lsize - 1); + while (1) { + flush_scache_line(a); /* Hit_Writeback_Inv_SD */ + if (a == end) + break; + a += sc_lsize; + } + + if (!rm7k_tcache_enabled) + return; + + a = addr & ~(tc_pagesize - 1); + end = (addr + size - 1) & ~(tc_pagesize - 1); + while(1) { + invalidate_tcache_page(a); /* Page_Invalidate_T */ + if (a == end) + break; + a += tc_pagesize; + } +} + +static void rm7k_sc_inv(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + +#ifdef DEBUG_CACHE + printk("rm7k_sc_inv[%08lx,%08lx]", addr, size); +#endif + + a = addr & ~(sc_lsize - 1); + end = (addr + size - 1) & ~(sc_lsize - 1); + while (1) { + invalidate_scache_line(a); /* Hit_Invalidate_SD */ + if (a == end) + break; + a += sc_lsize; + } + + if (!rm7k_tcache_enabled) + return; + + a = addr & ~(tc_pagesize - 1); + end = (addr + size - 1) & ~(tc_pagesize - 1); + while(1) { + invalidate_tcache_page(a); /* Page_Invalidate_T */ + if (a == end) + break; + a += tc_pagesize; + } +} + +/* + * This function is executed in the uncached segment KSEG1. + * It must not touch the stack, because the stack pointer still points + * into KSEG0. + * + * Three options: + * - Write it in assembly and guarantee that we don't use the stack. + * - Disable caching for KSEG0 before calling it. + * - Pray that GCC doesn't randomly start using the stack. + * + * This being Linux, we obviously take the least sane of those options - + * following DaveM's lead in c-r4k.c + * + * It seems we get our kicks from relying on unguaranteed behaviour in GCC + */ +static __init void rm7k_sc_enable(void) +{ + int i; + + set_c0_config(1<<3); /* CONF_SE */ + + write_c0_taglo(0); + write_c0_taghi(0); + + for (i=0; i> 31) & 1) + return 0; + + printk(KERN_INFO "Secondary cache size %ldK, linesize 32 bytes.\n", + (scache_size >> 10), sc_lsize); + + if ((config >> 3) & 1) + return; + + printk(KERN_INFO "Enabling secondary cache..."); + func(); + printk(" done\n"); + + /* + * While we're at it let's deal with the tertiary cache. + */ + if ((config >> 17) & 1) + return 1; + + /* + * We can't enable the L3 cache yet. There may be board-specific + * magic necessary to turn it on, and blindly asking the CPU to + * start using it would may give cache errors. + * + * Also, board-specific knowledge may allow us to use the + * CACHE Flash_Invalidate_T instruction if the tag RAM supports + * it, and may specify the size of the L3 cache so we don't have + * to probe it. + */ + printk(KERN_INFO "Tertiary cache present, %s enabled\n", + config&(1<<12) ? "already" : "not (yet)"); + + if ((config >> 12) & 1) + rm7k_tcache_enabled = 1; + + return 1; +} + +struct bcache_ops rm7k_sc_ops = { + .bc_enable = rm7k_sc_enable, + .bc_disable = rm7k_sc_disable, + .bc_wback_inv = rm7k_sc_wback_inv, + .bc_inv = rm7k_sc_inv +}; + +void __init rm7k_sc_init(void) +{ + if (rm7k_sc_probe()) { + rm7k_sc_enable(); + bcops = &rm7k_sc_ops; + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/tlbex-r3k.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,225 @@ +/* + * TLB exception handling code for R2000/R3000. + * + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Andreas Busse + * + * Multi-CPU abstraction reworking: + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * + * Further modifications to make this work: + * Copyright (c) 1998 Harald Koerfgen + * Copyright (c) 1998, 1999 Gleb Raiko & Vladimir Roganov + * Copyright (c) 2001 Ralf Baechle + * Copyright (c) 2001 MIPS Technologies, Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TLB_OPTIMIZE /* If you are paranoid, disable this. */ + + .text + .set mips1 + .set noreorder + + __INIT + + /* TLB refill, R[23]00 version */ + LEAF(except_vec0_r2300) + .set noat + .set mips1 + mfc0 k0, CP0_BADVADDR + lw k1, pgd_current # get pgd pointer + srl k0, k0, 22 + sll k0, k0, 2 + addu k1, k1, k0 + mfc0 k0, CP0_CONTEXT + lw k1, (k1) + and k0, k0, 0xffc + addu k1, k1, k0 + lw k0, (k1) + nop + mtc0 k0, CP0_ENTRYLO0 + mfc0 k1, CP0_EPC + tlbwr + jr k1 + rfe + END(except_vec0_r2300) + + __FINIT + + /* ABUSE of CPP macros 101. */ + + /* After this macro runs, the pte faulted on is + * in register PTE, a ptr into the table in which + * the pte belongs is in PTR. + */ +#define LOAD_PTE(pte, ptr) \ + mfc0 pte, CP0_BADVADDR; \ + lw ptr, pgd_current; \ + srl pte, pte, 22; \ + sll pte, pte, 2; \ + addu ptr, ptr, pte; \ + mfc0 pte, CP0_CONTEXT; \ + lw ptr, (ptr); \ + andi pte, pte, 0xffc; \ + addu ptr, ptr, pte; \ + lw pte, (ptr); \ + nop; + + /* This places the even/odd pte pair in the page + * table at PTR into ENTRYLO0 and ENTRYLO1 using + * TMP as a scratch register. + */ +#define PTE_RELOAD(ptr) \ + lw ptr, (ptr) ; \ + nop ; \ + mtc0 ptr, CP0_ENTRYLO0; \ + nop; + +#define DO_FAULT(write) \ + .set noat; \ + .set macro; \ + SAVE_ALL; \ + mfc0 a2, CP0_BADVADDR; \ + KMODE; \ + .set at; \ + move a0, sp; \ + jal do_page_fault; \ + li a1, write; \ + j ret_from_exception; \ + nop; \ + .set noat; \ + .set nomacro; + + /* Check is PTE is present, if not then jump to LABEL. + * PTR points to the page table where this PTE is located, + * when the macro is done executing PTE will be restored + * with it's original value. + */ +#define PTE_PRESENT(pte, ptr, label) \ + andi pte, pte, (_PAGE_PRESENT | _PAGE_READ); \ + xori pte, pte, (_PAGE_PRESENT | _PAGE_READ); \ + bnez pte, label; \ + .set push; \ + .set reorder; \ + lw pte, (ptr); \ + .set pop; + + /* Make PTE valid, store result in PTR. */ +#define PTE_MAKEVALID(pte, ptr) \ + ori pte, pte, (_PAGE_VALID | _PAGE_ACCESSED); \ + sw pte, (ptr); + + /* Check if PTE can be written to, if not branch to LABEL. + * Regardless restore PTE with value from PTR when done. + */ +#define PTE_WRITABLE(pte, ptr, label) \ + andi pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \ + xori pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \ + bnez pte, label; \ + .set push; \ + .set reorder; \ + lw pte, (ptr); \ + .set pop; + + + /* Make PTE writable, update software status bits as well, + * then store at PTR. + */ +#define PTE_MAKEWRITE(pte, ptr) \ + ori pte, pte, (_PAGE_ACCESSED | _PAGE_MODIFIED | \ + _PAGE_VALID | _PAGE_DIRTY); \ + sw pte, (ptr); + +/* + * The index register may have the probe fail bit set, + * because we would trap on access kseg2, i.e. without refill. + */ +#define TLB_WRITE(reg) \ + mfc0 reg, CP0_INDEX; \ + nop; \ + bltz reg, 1f; \ + nop; \ + tlbwi; \ + j 2f; \ + nop; \ +1: tlbwr; \ +2: + +#define RET(reg) \ + mfc0 reg, CP0_EPC; \ + nop; \ + jr reg; \ + rfe + + .set noreorder + + .align 5 +NESTED(handle_tlbl, PT_SIZE, sp) + .set noat + +#ifdef TLB_OPTIMIZE + /* Test present bit in entry. */ + LOAD_PTE(k0, k1) + tlbp + PTE_PRESENT(k0, k1, nopage_tlbl) + PTE_MAKEVALID(k0, k1) + PTE_RELOAD(k1) + TLB_WRITE(k0) + RET(k0) +nopage_tlbl: +#endif + + DO_FAULT(0) +END(handle_tlbl) + +NESTED(handle_tlbs, PT_SIZE, sp) + .set noat + +#ifdef TLB_OPTIMIZE + LOAD_PTE(k0, k1) + tlbp # find faulting entry + PTE_WRITABLE(k0, k1, nopage_tlbs) + PTE_MAKEWRITE(k0, k1) + PTE_RELOAD(k1) + TLB_WRITE(k0) + RET(k0) +nopage_tlbs: +#endif + + DO_FAULT(1) +END(handle_tlbs) + + .align 5 +NESTED(handle_mod, PT_SIZE, sp) + .set noat +#ifdef TLB_OPTIMIZE + LOAD_PTE(k0, k1) + tlbp # find faulting entry + andi k0, k0, _PAGE_WRITE + beqz k0, nowrite_mod + .set push + .set reorder + lw k0, (k1) + .set pop + + /* Present and writable bits set, set accessed and dirty bits. */ + PTE_MAKEWRITE(k0, k1) + + /* Now reload the entry into the tlb. */ + PTE_RELOAD(k1) + tlbwi + RET(k0) +#endif + +nowrite_mod: + DO_FAULT(1) +END(handle_mod) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/tlbex-r4k.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,532 @@ +/* + * TLB exception handling code for r4k. + * + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Andreas Busse + * + * Multi-cpu abstraction and reworking: + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + */ +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TLB_OPTIMIZE /* If you are paranoid, disable this. */ + +#ifdef CONFIG_64BIT_PHYS_ADDR +#define PTE_L ld +#define PTE_S sd +#define PTE_SRL dsrl +#define P_MTC0 dmtc0 +#define PTE_SIZE 8 +#define PTEP_INDX_MSK 0xff0 +#define PTE_INDX_MSK 0xff8 +#define PTE_INDX_SHIFT 9 +#else +#define PTE_L lw +#define PTE_S sw +#define PTE_SRL srl +#define P_MTC0 mtc0 +#define PTE_SIZE 4 +#define PTEP_INDX_MSK 0xff8 +#define PTE_INDX_MSK 0xffc +#define PTE_INDX_SHIFT 10 +#endif + +/* + * ABUSE of CPP macros 101. + * + * After this macro runs, the pte faulted on is + * in register PTE, a ptr into the table in which + * the pte belongs is in PTR. + */ + +#ifdef CONFIG_SMP +#define GET_PGD(scratch, ptr) \ + mfc0 ptr, CP0_CONTEXT; \ + la scratch, pgd_current;\ + srl ptr, 23; \ + sll ptr, 2; \ + addu ptr, scratch, ptr; \ + lw ptr, (ptr); +#else +#define GET_PGD(scratch, ptr) \ + lw ptr, pgd_current; +#endif + +#define LOAD_PTE(pte, ptr) \ + GET_PGD(pte, ptr) \ + mfc0 pte, CP0_BADVADDR; \ + srl pte, pte, _PGDIR_SHIFT; \ + sll pte, pte, 2; \ + addu ptr, ptr, pte; \ + mfc0 pte, CP0_BADVADDR; \ + lw ptr, (ptr); \ + srl pte, pte, PTE_INDX_SHIFT; \ + and pte, pte, PTE_INDX_MSK; \ + addu ptr, ptr, pte; \ + PTE_L pte, (ptr); + + /* This places the even/odd pte pair in the page + * table at PTR into ENTRYLO0 and ENTRYLO1 using + * TMP as a scratch register. + */ +#define PTE_RELOAD(ptr, tmp) \ + ori ptr, ptr, PTE_SIZE; \ + xori ptr, ptr, PTE_SIZE; \ + PTE_L tmp, PTE_SIZE(ptr); \ + PTE_L ptr, 0(ptr); \ + PTE_SRL tmp, tmp, 6; \ + P_MTC0 tmp, CP0_ENTRYLO1; \ + PTE_SRL ptr, ptr, 6; \ + P_MTC0 ptr, CP0_ENTRYLO0; + +#define DO_FAULT(write) \ + .set noat; \ + SAVE_ALL; \ + mfc0 a2, CP0_BADVADDR; \ + KMODE; \ + .set at; \ + move a0, sp; \ + jal do_page_fault; \ + li a1, write; \ + j ret_from_exception; \ + nop; \ + .set noat; + + /* Check is PTE is present, if not then jump to LABEL. + * PTR points to the page table where this PTE is located, + * when the macro is done executing PTE will be restored + * with it's original value. + */ +#define PTE_PRESENT(pte, ptr, label) \ + andi pte, pte, (_PAGE_PRESENT | _PAGE_READ); \ + xori pte, pte, (_PAGE_PRESENT | _PAGE_READ); \ + bnez pte, label; \ + PTE_L pte, (ptr); + + /* Make PTE valid, store result in PTR. */ +#define PTE_MAKEVALID(pte, ptr) \ + ori pte, pte, (_PAGE_VALID | _PAGE_ACCESSED); \ + PTE_S pte, (ptr); + + /* Check if PTE can be written to, if not branch to LABEL. + * Regardless restore PTE with value from PTR when done. + */ +#define PTE_WRITABLE(pte, ptr, label) \ + andi pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \ + xori pte, pte, (_PAGE_PRESENT | _PAGE_WRITE); \ + bnez pte, label; \ + PTE_L pte, (ptr); + + /* Make PTE writable, update software status bits as well, + * then store at PTR. + */ +#define PTE_MAKEWRITE(pte, ptr) \ + ori pte, pte, (_PAGE_ACCESSED | _PAGE_MODIFIED | \ + _PAGE_VALID | _PAGE_DIRTY); \ + PTE_S pte, (ptr); + + __INIT + +#ifdef CONFIG_64BIT_PHYS_ADDR +#define GET_PTE_OFF(reg) +#elif CONFIG_CPU_VR41XX +#define GET_PTE_OFF(reg) srl reg, reg, 3 +#else +#define GET_PTE_OFF(reg) srl reg, reg, 1 +#endif + +/* + * These handlers much be written in a relocatable manner + * because based upon the cpu type an arbitrary one of the + * following pieces of code will be copied to the KSEG0 + * vector location. + */ + /* TLB refill, EXL == 0, R4xx0, non-R4600 version */ + .set noreorder + .set noat + LEAF(except_vec0_r4000) + .set mips3 + GET_PGD(k0, k1) # get pgd pointer + mfc0 k0, CP0_BADVADDR # Get faulting address + srl k0, k0, _PGDIR_SHIFT # get pgd only bits + + sll k0, k0, 2 + addu k1, k1, k0 # add in pgd offset + mfc0 k0, CP0_CONTEXT # get context reg + lw k1, (k1) + GET_PTE_OFF(k0) # get pte offset + and k0, k0, PTEP_INDX_MSK + addu k1, k1, k0 # add in offset + PTE_L k0, 0(k1) # get even pte + PTE_L k1, PTE_SIZE(k1) # get odd pte + PTE_SRL k0, k0, 6 # convert to entrylo0 + P_MTC0 k0, CP0_ENTRYLO0 # load it + PTE_SRL k1, k1, 6 # convert to entrylo1 + P_MTC0 k1, CP0_ENTRYLO1 # load it + b 1f + tlbwr # write random tlb entry +1: + nop + eret # return from trap + END(except_vec0_r4000) + + /* TLB refill, EXL == 0, R4600 version */ + LEAF(except_vec0_r4600) + .set mips3 + GET_PGD(k0, k1) # get pgd pointer + mfc0 k0, CP0_BADVADDR + srl k0, k0, _PGDIR_SHIFT + sll k0, k0, 2 # log2(sizeof(pgd_t) + addu k1, k1, k0 + mfc0 k0, CP0_CONTEXT + lw k1, (k1) + GET_PTE_OFF(k0) # get pte offset + and k0, k0, PTEP_INDX_MSK + addu k1, k1, k0 + PTE_L k0, 0(k1) + PTE_L k1, PTE_SIZE(k1) + PTE_SRL k0, k0, 6 + P_MTC0 k0, CP0_ENTRYLO0 + PTE_SRL k1, k1, 6 + P_MTC0 k1, CP0_ENTRYLO1 + nop + tlbwr + nop + eret + END(except_vec0_r4600) + + /* TLB refill, EXL == 0, R52x0 "Nevada" version */ + /* + * This version has a bug workaround for the Nevada. It seems + * as if under certain circumstances the move from cp0_context + * might produce a bogus result when the mfc0 instruction and + * it's consumer are in a different cacheline or a load instruction, + * probably any memory reference, is between them. This is + * potencially slower than the R4000 version, so we use this + * special version. + */ + .set noreorder + .set noat + LEAF(except_vec0_nevada) + .set mips3 + mfc0 k0, CP0_BADVADDR # Get faulting address + srl k0, k0, _PGDIR_SHIFT # get pgd only bits + lw k1, pgd_current # get pgd pointer + sll k0, k0, 2 # log2(sizeof(pgd_t) + addu k1, k1, k0 # add in pgd offset + lw k1, (k1) + mfc0 k0, CP0_CONTEXT # get context reg + GET_PTE_OFF(k0) # get pte offset + and k0, k0, PTEP_INDX_MSK + addu k1, k1, k0 # add in offset + PTE_L k0, 0(k1) # get even pte + PTE_L k1, PTE_SIZE(k1) # get odd pte + PTE_SRL k0, k0, 6 # convert to entrylo0 + P_MTC0 k0, CP0_ENTRYLO0 # load it + PTE_SRL k1, k1, 6 # convert to entrylo1 + P_MTC0 k1, CP0_ENTRYLO1 # load it + nop # QED specified nops + nop + tlbwr # write random tlb entry + nop # traditional nop + eret # return from trap + END(except_vec0_nevada) + + /* TLB refill, EXL == 0, SB1 with M3 errata handling version */ + LEAF(except_vec0_sb1) +#if BCM1250_M3_WAR + mfc0 k0, CP0_BADVADDR + mfc0 k1, CP0_ENTRYHI + xor k0, k1 + srl k0, k0, PAGE_SHIFT+1 + bnez k0, 1f +#endif + GET_PGD(k0, k1) # get pgd pointer + mfc0 k0, CP0_BADVADDR # Get faulting address + srl k0, k0, _PGDIR_SHIFT # get pgd only bits + sll k0, k0, 2 + addu k1, k1, k0 # add in pgd offset + mfc0 k0, CP0_CONTEXT # get context reg + lw k1, (k1) + GET_PTE_OFF(k0) # get pte offset + and k0, k0, PTEP_INDX_MSK + addu k1, k1, k0 # add in offset + PTE_L k0, 0(k1) # get even pte + PTE_L k1, PTE_SIZE(k1) # get odd pte + PTE_SRL k0, k0, 6 # convert to entrylo0 + P_MTC0 k0, CP0_ENTRYLO0 # load it + PTE_SRL k1, k1, 6 # convert to entrylo1 + P_MTC0 k1, CP0_ENTRYLO1 # load it + tlbwr # write random tlb entry +1: eret # return from trap + END(except_vec0_sb1) + + /* TLB refill, EXL == 0, R4[40]00/R5000 badvaddr hwbug version */ + LEAF(except_vec0_r45k_bvahwbug) + .set mips3 + GET_PGD(k0, k1) # get pgd pointer + mfc0 k0, CP0_BADVADDR + srl k0, k0, _PGDIR_SHIFT + sll k0, k0, 2 # log2(sizeof(pgd_t) + addu k1, k1, k0 + mfc0 k0, CP0_CONTEXT + lw k1, (k1) +#ifndef CONFIG_64BIT_PHYS_ADDR + srl k0, k0, 1 +#endif + and k0, k0, PTEP_INDX_MSK + addu k1, k1, k0 + PTE_L k0, 0(k1) + PTE_L k1, PTE_SIZE(k1) + nop /* XXX */ + tlbp + PTE_SRL k0, k0, 6 + P_MTC0 k0, CP0_ENTRYLO0 + PTE_SRL k1, k1, 6 + mfc0 k0, CP0_INDEX + P_MTC0 k1, CP0_ENTRYLO1 + bltzl k0, 1f + tlbwr +1: + nop + eret + END(except_vec0_r45k_bvahwbug) + +#ifdef CONFIG_SMP + /* TLB refill, EXL == 0, R4000 MP badvaddr hwbug version */ + LEAF(except_vec0_r4k_mphwbug) + .set mips3 + GET_PGD(k0, k1) # get pgd pointer + mfc0 k0, CP0_BADVADDR + srl k0, k0, _PGDIR_SHIFT + sll k0, k0, 2 # log2(sizeof(pgd_t) + addu k1, k1, k0 + mfc0 k0, CP0_CONTEXT + lw k1, (k1) +#ifndef CONFIG_64BIT_PHYS_ADDR + srl k0, k0, 1 +#endif + and k0, k0, PTEP_INDX_MSK + addu k1, k1, k0 + PTE_L k0, 0(k1) + PTE_L k1, PTE_SIZE(k1) + nop /* XXX */ + tlbp + PTE_SRL k0, k0, 6 + P_MTC0 k0, CP0_ENTRYLO0 + PTE_SRL k1, k1, 6 + mfc0 k0, CP0_INDEX + P_MTC0 k1, CP0_ENTRYLO1 + bltzl k0, 1f + tlbwr +1: + nop + eret + END(except_vec0_r4k_mphwbug) +#endif + + /* TLB refill, EXL == 0, R4000 UP 250MHZ entrylo[01] hwbug version */ + LEAF(except_vec0_r4k_250MHZhwbug) + .set mips3 + GET_PGD(k0, k1) # get pgd pointer + mfc0 k0, CP0_BADVADDR + srl k0, k0, _PGDIR_SHIFT + sll k0, k0, 2 # log2(sizeof(pgd_t) + addu k1, k1, k0 + mfc0 k0, CP0_CONTEXT + lw k1, (k1) +#ifndef CONFIG_64BIT_PHYS_ADDR + srl k0, k0, 1 +#endif + and k0, k0, PTEP_INDX_MSK + addu k1, k1, k0 + PTE_L k0, 0(k1) + PTE_L k1, PTE_SIZE(k1) + PTE_SRL k0, k0, 6 + P_MTC0 zero, CP0_ENTRYLO0 + P_MTC0 k0, CP0_ENTRYLO0 + PTE_SRL k1, k1, 6 + P_MTC0 zero, CP0_ENTRYLO1 + P_MTC0 k1, CP0_ENTRYLO1 + b 1f + tlbwr +1: + nop + eret + END(except_vec0_r4k_250MHZhwbug) + +#ifdef CONFIG_SMP + /* TLB refill, EXL == 0, R4000 MP 250MHZ entrylo[01]+badvaddr bug version */ + LEAF(except_vec0_r4k_MP250MHZhwbug) + .set mips3 + GET_PGD(k0, k1) # get pgd pointer + mfc0 k0, CP0_BADVADDR + srl k0, k0, _PGDIR_SHIFT + sll k0, k0, 2 # log2(sizeof(pgd_t) + addu k1, k1, k0 + mfc0 k0, CP0_CONTEXT + lw k1, (k1) +#ifndef CONFIG_64BIT_PHYS_ADDR + srl k0, k0, 1 +#endif + and k0, k0, PTEP_INDX_MSK + addu k1, k1, k0 + PTE_L k0, 0(k1) + PTE_L k1, PTE_SIZE(k1) + nop /* XXX */ + tlbp + PTE_SRL k0, k0, 6 + P_MTC0 zero, CP0_ENTRYLO0 + P_MTC0 k0, CP0_ENTRYLO0 + mfc0 k0, CP0_INDEX + PTE_SRL k1, k1, 6 + P_MTC0 zero, CP0_ENTRYLO1 + P_MTC0 k1, CP0_ENTRYLO1 + bltzl k0, 1f + tlbwr +1: + nop + eret + END(except_vec0_r4k_MP250MHZhwbug) +#endif + + __FINIT + + .set noreorder + +/* + * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: + * 2. A timing hazard exists for the TLBP instruction. + * + * stalling_instruction + * TLBP + * + * The JTLB is being read for the TLBP throughout the stall generated by the + * previous instruction. This is not really correct as the stalling instruction + * can modify the address used to access the JTLB. The failure symptom is that + * the TLBP instruction will use an address created for the stalling instruction + * and not the address held in C0_ENHI and thus report the wrong results. + * + * The software work-around is to not allow the instruction preceding the TLBP + * to stall - make it an NOP or some other instruction guaranteed not to stall. + * + * Errata 2 will not be fixed. This errata is also on the R5000. + * + * As if we MIPS hackers wouldn't know how to nop pipelines happy ... + */ +#define R5K_HAZARD nop + + /* + * Note for many R4k variants tlb probes cannot be executed out + * of the instruction cache else you get bogus results. + */ + .align 5 + NESTED(handle_tlbl, PT_SIZE, sp) + .set noat +#if BCM1250_M3_WAR + mfc0 k0, CP0_BADVADDR + mfc0 k1, CP0_ENTRYHI + xor k0, k1 + srl k0, k0, PAGE_SHIFT+1 + beqz k0, 1f + nop + .set mips3 + eret + .set mips0 +1: +#endif +invalid_tlbl: +#ifdef TLB_OPTIMIZE + /* Test present bit in entry. */ + LOAD_PTE(k0, k1) + R5K_HAZARD + tlbp + PTE_PRESENT(k0, k1, nopage_tlbl) + PTE_MAKEVALID(k0, k1) + PTE_RELOAD(k1, k0) + nop + b 1f + tlbwi +1: + nop + .set mips3 + eret + .set mips0 +#endif + +nopage_tlbl: + DO_FAULT(0) + END(handle_tlbl) + + .align 5 + NESTED(handle_tlbs, PT_SIZE, sp) + .set noat +#ifdef TLB_OPTIMIZE + .set mips3 + li k0,0 + LOAD_PTE(k0, k1) + R5K_HAZARD + tlbp # find faulting entry + PTE_WRITABLE(k0, k1, nopage_tlbs) + PTE_MAKEWRITE(k0, k1) + PTE_RELOAD(k1, k0) + nop + b 1f + tlbwi +1: + nop + .set mips3 + eret + .set mips0 +#endif + +nopage_tlbs: + DO_FAULT(1) + END(handle_tlbs) + + .align 5 + NESTED(handle_mod, PT_SIZE, sp) + .set noat +#ifdef TLB_OPTIMIZE + .set mips3 + LOAD_PTE(k0, k1) + R5K_HAZARD + tlbp # find faulting entry + andi k0, k0, _PAGE_WRITE + beqz k0, nowrite_mod + PTE_L k0, (k1) + + /* Present and writable bits set, set accessed and dirty bits. */ + PTE_MAKEWRITE(k0, k1) + + /* Now reload the entry into the tlb. */ + PTE_RELOAD(k1, k0) + nop + b 1f + tlbwi +1: + nop + .set mips3 + eret + .set mips0 +#endif + +nowrite_mod: + DO_FAULT(1) + END(handle_mod) + --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/tlb-r3k.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,290 @@ +/* + * r2300.c: R2000 and R3000 specific mmu/cache code. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * + * with a lot of changes to make this thing work for R3000s + * Tx39XX R4k style caches added. HK + * Copyright (C) 1998, 1999, 2000 Harald Koerfgen + * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov + * Copyright (C) 2002 Ralf Baechle + * Copyright (C) 2002 Maciej W. Rozycki + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#undef DEBUG_TLB + +extern char except_vec0_r2300; + +/* CP0 hazard avoidance. */ +#define BARRIER \ + __asm__ __volatile__( \ + ".set push\n\t" \ + ".set noreorder\n\t" \ + "nop\n\t" \ + ".set pop\n\t") + +int r3k_have_wired_reg; /* should be in cpu_data? */ + +/* TLB operations. */ +void local_flush_tlb_all(void) +{ + unsigned long flags; + unsigned long old_ctx; + int entry; + +#ifdef DEBUG_TLB + printk("[tlball]"); +#endif + + local_irq_save(flags); + old_ctx = read_c0_entryhi() & ASID_MASK; + write_c0_entrylo0(0); + entry = r3k_have_wired_reg ? read_c0_wired() : 8; + for (; entry < current_cpu_data.tlbsize; entry++) { + write_c0_index(entry << 8); + write_c0_entryhi((entry | 0x80000) << 12); + BARRIER; + tlb_write_indexed(); + } + write_c0_entryhi(old_ctx); + local_irq_restore(flags); +} + +void local_flush_tlb_mm(struct mm_struct *mm) +{ + int cpu = smp_processor_id(); + + if (cpu_context(cpu, mm) != 0) { +#ifdef DEBUG_TLB + printk("[tlbmm<%lu>]", (unsigned long)cpu_context(cpu, mm)); +#endif + drop_mmu_context(mm, cpu); + } +} + +void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end) +{ + struct mm_struct *mm = vma->vm_mm; + int cpu = smp_processor_id(); + + if (cpu_context(cpu, mm) != 0) { + unsigned long flags; + int size; + +#ifdef DEBUG_TLB + printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", + cpu_context(cpu, mm) & ASID_MASK, start, end); +#endif + local_irq_save(flags); + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + if (size <= current_cpu_data.tlbsize) { + int oldpid = read_c0_entryhi() & ASID_MASK; + int newpid = cpu_context(cpu, mm) & ASID_MASK; + + start &= PAGE_MASK; + end += PAGE_SIZE - 1; + end &= PAGE_MASK; + while (start < end) { + int idx; + + write_c0_entryhi(start | newpid); + start += PAGE_SIZE; /* BARRIER */ + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entryhi(KSEG0); + if (idx < 0) /* BARRIER */ + continue; + tlb_write_indexed(); + } + write_c0_entryhi(oldpid); + } else { + drop_mmu_context(mm, cpu); + } + local_irq_restore(flags); + } +} + +void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) +{ + unsigned long flags; + int size; + +#ifdef DEBUG_TLB + printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", start, end); +#endif + local_irq_save(flags); + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + if (size <= current_cpu_data.tlbsize) { + int pid = read_c0_entryhi(); + + start &= PAGE_MASK; + end += PAGE_SIZE - 1; + end &= PAGE_MASK; + + while (start < end) { + int idx; + + write_c0_entryhi(start); + start += PAGE_SIZE; /* BARRIER */ + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entryhi(KSEG0); + if (idx < 0) /* BARRIER */ + continue; + tlb_write_indexed(); + } + write_c0_entryhi(pid); + } else { + local_flush_tlb_all(); + } + local_irq_restore(flags); +} + +void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) +{ + int cpu = smp_processor_id(); + + if (!vma || cpu_context(cpu, vma->vm_mm) != 0) { + unsigned long flags; + int oldpid, newpid, idx; + +#ifdef DEBUG_TLB + printk("[tlbpage<%lu,0x%08lx>]", cpu_context(cpu, vma->vm_mm), page); +#endif + newpid = cpu_context(cpu, vma->vm_mm) & ASID_MASK; + page &= PAGE_MASK; + local_irq_save(flags); + oldpid = read_c0_entryhi() & ASID_MASK; + write_c0_entryhi(page | newpid); + BARRIER; + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entryhi(KSEG0); + if (idx < 0) /* BARRIER */ + goto finish; + tlb_write_indexed(); + +finish: + write_c0_entryhi(oldpid); + local_irq_restore(flags); + } +} + +void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) +{ + unsigned long flags; + int idx, pid; + + /* + * Handle debugger faulting in for debugee. + */ + if (current->active_mm != vma->vm_mm) + return; + + pid = read_c0_entryhi() & ASID_MASK; + +#ifdef DEBUG_TLB + if ((pid != (cpu_context(cpu, vma->vm_mm) & ASID_MASK)) || (cpu_context(cpu, vma->vm_mm) == 0)) { + printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%lu tlbpid=%d\n", + (cpu_context(cpu, vma->vm_mm)), pid); + } +#endif + + local_irq_save(flags); + address &= PAGE_MASK; + write_c0_entryhi(address | pid); + BARRIER; + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(pte_val(pte)); + write_c0_entryhi(address | pid); + if (idx < 0) { /* BARRIER */ + tlb_write_random(); + } else { + tlb_write_indexed(); + } + write_c0_entryhi(pid); + local_irq_restore(flags); +} + +void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask) +{ + unsigned long flags; + unsigned long old_ctx; + static unsigned long wired = 0; + + if (r3k_have_wired_reg) { /* TX39XX */ + unsigned long old_pagemask; + unsigned long w; + +#ifdef DEBUG_TLB + printk("[tlbwired]\n", + entrylo0, entryhi, pagemask); +#endif + + local_irq_save(flags); + /* Save old context and create impossible VPN2 value */ + old_ctx = read_c0_entryhi() & ASID_MASK; + old_pagemask = read_c0_pagemask(); + w = read_c0_wired(); + write_c0_wired(w + 1); + if (read_c0_wired() != w + 1) { + printk("[tlbwired] No WIRED reg?\n"); + return; + } + write_c0_index(w << 8); + write_c0_pagemask(pagemask); + write_c0_entryhi(entryhi); + write_c0_entrylo0(entrylo0); + BARRIER; + tlb_write_indexed(); + + write_c0_entryhi(old_ctx); + write_c0_pagemask(old_pagemask); + local_flush_tlb_all(); + local_irq_restore(flags); + + } else if (wired < 8) { +#ifdef DEBUG_TLB + printk("[tlbwired]\n", + entrylo0, entryhi); +#endif + + local_irq_save(flags); + old_ctx = read_c0_entryhi() & ASID_MASK; + write_c0_entrylo0(entrylo0); + write_c0_entryhi(entryhi); + write_c0_index(wired); + wired++; /* BARRIER */ + tlb_write_indexed(); + write_c0_entryhi(old_ctx); + local_flush_tlb_all(); + local_irq_restore(flags); + } +} + +void __init r3k_tlb_init(void) +{ + local_flush_tlb_all(); + memcpy((void *)KSEG0, &except_vec0_r2300, 0x80); + flush_icache_range(KSEG0, KSEG0 + 0x80); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/tlb-r4k.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,459 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * r4xx0.c: R4000 processor variant specific MMU/Cache routines. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org + * + * To do: + * + * - this code is a overbloated pig + * - many of the bug workarounds are not efficient at all, but at + * least they are functional ... + */ +#include +#include +#include + +#include +#include +#include +#include +#include + +#undef DEBUG_TLB +#undef DEBUG_TLBUPDATE + +extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600; + +/* CP0 hazard avoidance. */ +#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ + "nop; nop; nop; nop; nop; nop;\n\t" \ + ".set reorder\n\t") + +void local_flush_tlb_all(void) +{ + unsigned long flags; + unsigned long old_ctx; + int entry; + +#ifdef DEBUG_TLB + printk("[tlball]"); +#endif + + local_irq_save(flags); + /* Save old context and create impossible VPN2 value */ + old_ctx = (read_c0_entryhi() & ASID_MASK); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + BARRIER; + + entry = read_c0_wired(); + + /* Blast 'em all away. */ + while (entry < current_cpu_data.tlbsize) { + /* + * Make sure all entries differ. If they're not different + * MIPS32 will take revenge ... + */ + write_c0_entryhi(KSEG0 + entry*0x2000); + write_c0_index(entry); + BARRIER; + tlb_write_indexed(); + BARRIER; + entry++; + } + BARRIER; + write_c0_entryhi(old_ctx); + local_irq_restore(flags); +} + +void local_flush_tlb_mm(struct mm_struct *mm) +{ + int cpu = smp_processor_id(); + + if (cpu_context(cpu, mm) != 0) { +#ifdef DEBUG_TLB + printk("[tlbmm<%d>]", cpu_context(cpu, mm)); +#endif + drop_mmu_context(mm,cpu); + } +} + +void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end) +{ + struct mm_struct *mm = vma->vm_mm; + int cpu = smp_processor_id(); + + if (cpu_context(cpu, mm) != 0) { + unsigned long flags; + int size; + +#ifdef DEBUG_TLB + printk("[tlbrange<%02x,%08lx,%08lx>]", cpu_context(cpu, mm) & ASID_MASK, + start, end); +#endif + local_irq_save(flags); + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + size = (size + 1) >> 1; + if (size <= current_cpu_data.tlbsize/2) { + int oldpid = read_c0_entryhi() & ASID_MASK; + int newpid = cpu_context(cpu, mm) & ASID_MASK; + + start &= (PAGE_MASK << 1); + end += ((PAGE_SIZE << 1) - 1); + end &= (PAGE_MASK << 1); + while (start < end) { + int idx; + + write_c0_entryhi(start | newpid); + start += (PAGE_SIZE << 1); + BARRIER; + tlb_probe(); + BARRIER; + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + if (idx < 0) + continue; + /* Make sure all entries differ. */ + write_c0_entryhi(KSEG0 + idx*0x2000); + BARRIER; + tlb_write_indexed(); + BARRIER; + } + write_c0_entryhi(oldpid); + } else { + drop_mmu_context(mm, cpu); + } + local_irq_restore(flags); + } +} + +void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) +{ + unsigned long flags; + int size; + +#ifdef DEBUG_TLB + printk("[tlbkernelrange<%02x,%08lx,%08lx>]", start, end); +#endif + local_irq_save(flags); + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + size = (size + 1) >> 1; + if (size <= current_cpu_data.tlbsize / 2) { + int pid = read_c0_entryhi(); + + start &= (PAGE_MASK << 1); + end += ((PAGE_SIZE << 1) - 1); + end &= (PAGE_MASK << 1); + + while (start < end) { + int idx; + + write_c0_entryhi(start); + start += (PAGE_SIZE << 1); + BARRIER; + tlb_probe(); + BARRIER; + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + if (idx < 0) + continue; + /* Make sure all entries differ. */ + write_c0_entryhi(KSEG0 + idx*0x2000); + BARRIER; + tlb_write_indexed(); + BARRIER; + } + write_c0_entryhi(pid); + } else { + local_flush_tlb_all(); + } + local_irq_restore(flags); +} + +void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) +{ + int cpu = smp_processor_id(); + + if (!vma || cpu_context(cpu, vma->vm_mm) != 0) { + unsigned long flags; + int oldpid, newpid, idx; + +#ifdef DEBUG_TLB + printk("[tlbpage<%d,%08lx>]", cpu_context(cpu, vma->vm_mm), + page); +#endif + newpid = (cpu_context(cpu, vma->vm_mm) & ASID_MASK); + page &= (PAGE_MASK << 1); + local_irq_save(flags); + oldpid = (read_c0_entryhi() & ASID_MASK); + write_c0_entryhi(page | newpid); + BARRIER; + tlb_probe(); + BARRIER; + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + if(idx < 0) + goto finish; + /* Make sure all entries differ. */ + write_c0_entryhi(KSEG0+idx*0x2000); + BARRIER; + tlb_write_indexed(); + + finish: + BARRIER; + write_c0_entryhi(oldpid); + local_irq_restore(flags); + } +} + +/* + * This one is only used for pages with the global bit set so we don't care + * much about the ASID. + */ +void local_flush_tlb_one(unsigned long page) +{ + unsigned long flags; + int oldpid, idx; + + local_irq_save(flags); + page &= (PAGE_MASK << 1); + oldpid = read_c0_entryhi() & 0xff; + write_c0_entryhi(page); + BARRIER; + tlb_probe(); + BARRIER; + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + if (idx >= 0) { + /* Make sure all entries differ. */ + write_c0_entryhi(KSEG0+(idx<<(PAGE_SHIFT+1))); + BARRIER; + tlb_write_indexed(); + } + BARRIER; + write_c0_entryhi(oldpid); + + local_irq_restore(flags); +} + +/* We will need multiple versions of update_mmu_cache(), one that just + * updates the TLB with the new pte(s), and another which also checks + * for the R4k "end of page" hardware bug and does the needy. + */ +void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) +{ + unsigned long flags; + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + int idx, pid; + + /* + * Handle debugger faulting in for debugee. + */ + if (current->active_mm != vma->vm_mm) + return; + + pid = read_c0_entryhi() & ASID_MASK; + +#ifdef DEBUG_TLB + if ((pid != cpu_context(cpu, vma->vm_mm) & ASID_MASK) || + (cpu_context(vma->vm_mm) == 0)) { + printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d " + "tlbpid=%d\n", + (int) (cpu_context(cpu, vma->vm_mm) & ASID_MASK), pid); + } +#endif + + local_irq_save(flags); + address &= (PAGE_MASK << 1); + write_c0_entryhi(address | pid); + pgdp = pgd_offset(vma->vm_mm, address); + BARRIER; + tlb_probe(); + BARRIER; + pmdp = pmd_offset(pgdp, address); + idx = read_c0_index(); + ptep = pte_offset_map(pmdp, address); + BARRIER; + write_c0_entrylo0(pte_val(*ptep++) >> 6); + write_c0_entrylo1(pte_val(*ptep) >> 6); + write_c0_entryhi(address | pid); + BARRIER; + if (idx < 0) { + tlb_write_random(); + } else { + tlb_write_indexed(); + } + BARRIER; + write_c0_entryhi(pid); + BARRIER; + local_irq_restore(flags); +} + +#if 0 +static void r4k_update_mmu_cache_hwbug(struct vm_area_struct * vma, + unsigned long address, pte_t pte) +{ + unsigned long flags; + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + int idx; + + local_irq_save(flags); + address &= (PAGE_MASK << 1); + write_c0_entryhi(address | (read_c0_entryhi() & ASID_MASK)); + pgdp = pgd_offset(vma->vm_mm, address); + tlb_probe(); + pmdp = pmd_offset(pgdp, address); + idx = read_c0_index(); + ptep = pte_offset_map(pmdp, address); + write_c0_entrylo0(pte_val(*ptep++) >> 6); + write_c0_entrylo1(pte_val(*ptep) >> 6); + BARRIER; + if (idx < 0) + tlb_write_random(); + else + tlb_write_indexed(); + BARRIER; + local_irq_restore(flags); +} +#endif + +void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask) +{ + unsigned long flags; + unsigned long wired; + unsigned long old_pagemask; + unsigned long old_ctx; + + local_irq_save(flags); + /* Save old context and create impossible VPN2 value */ + old_ctx = read_c0_entryhi() & ASID_MASK; + old_pagemask = read_c0_pagemask(); + wired = read_c0_wired(); + write_c0_wired(wired + 1); + write_c0_index(wired); + BARRIER; + write_c0_pagemask(pagemask); + write_c0_entryhi(entryhi); + write_c0_entrylo0(entrylo0); + write_c0_entrylo1(entrylo1); + BARRIER; + tlb_write_indexed(); + BARRIER; + + write_c0_entryhi(old_ctx); + BARRIER; + write_c0_pagemask(old_pagemask); + local_flush_tlb_all(); + local_irq_restore(flags); +} + +/* + * Used for loading TLB entries before trap_init() has started, when we + * don't actually want to add a wired entry which remains throughout the + * lifetime of the system + */ + +static int temp_tlb_entry __initdata; + +__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask) +{ + int ret = 0; + unsigned long flags; + unsigned long wired; + unsigned long old_pagemask; + unsigned long old_ctx; + + local_irq_save(flags); + /* Save old context and create impossible VPN2 value */ + old_ctx = read_c0_entryhi() & ASID_MASK; + old_pagemask = read_c0_pagemask(); + wired = read_c0_wired(); + if (--temp_tlb_entry < wired) { + printk(KERN_WARNING "No TLB space left for add_temporary_entry\n"); + ret = -ENOSPC; + goto out; + } + + write_c0_index(temp_tlb_entry); + BARRIER; + write_c0_pagemask(pagemask); + write_c0_entryhi(entryhi); + write_c0_entrylo0(entrylo0); + write_c0_entrylo1(entrylo1); + BARRIER; + tlb_write_indexed(); + BARRIER; + + write_c0_entryhi(old_ctx); + BARRIER; + write_c0_pagemask(old_pagemask); +out: + local_irq_restore(flags); + return ret; +} + +static void __init probe_tlb(unsigned long config) +{ + unsigned int prid, config1; + + prid = read_c0_prid() & ASID_MASK; + if (prid == PRID_IMP_RM7000 || !(config & (1 << 31))) + /* + * Not a MIPS32 complianant CPU. Config 1 register not + * supported, we assume R4k style. Cpu probing already figured + * out the number of tlb entries. + */ + return; + +#if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64) + config1 = read_c0_config1(); + if (!((config >> 7) & 3)) + panic("No MMU present"); + else + current_cpu_data.tlbsize = ((config1 >> 25) & 0x3f) + 1; +#endif +} + +void __init r4k_tlb_init(void) +{ + u32 config = read_c0_config(); + + /* + * You should never change this register: + * - On R4600 1.7 the tlbp never hits for pages smaller than + * the value in the c0_pagemask register. + * - The entire mm handling assumes the c0_pagemask register to + * be set for 4kb pages. + */ + probe_tlb(config); + write_c0_pagemask(PM_4K); + write_c0_wired(0); + temp_tlb_entry = current_cpu_data.tlbsize - 1; + local_flush_tlb_all(); + + if (cpu_has_4kex && cpu_has_4ktlb) { + if (current_cpu_data.cputype == CPU_NEVADA) + memcpy((void *)KSEG0, &except_vec0_nevada, 0x80); + else if (current_cpu_data.cputype == CPU_R4600) + memcpy((void *)KSEG0, &except_vec0_r4600, 0x80); + else + memcpy((void *)KSEG0, &except_vec0_r4000, 0x80); + flush_icache_range(KSEG0, KSEG0 + 0x80); + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/mm/tlb-sb1.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,339 @@ +/* + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include +#include +#include +#include + +extern char except_vec0_sb1[]; + +/* Dump the current entry* and pagemask registers */ +static inline void dump_cur_tlb_regs(void) +{ + unsigned int entryhihi, entryhilo, entrylo0hi, entrylo0lo, entrylo1hi; + unsigned int entrylo1lo, pagemask; + + __asm__ __volatile__ ( + ".set push \n" + ".set noreorder \n" + ".set mips64 \n" + ".set noat \n" + " dmfc0 $1, $10 \n" + " dsrl32 %0, $1, 0 \n" + " sll %1, $1, 0 \n" + " dmfc0 $1, $2 \n" + " dsrl32 %2, $1, 0 \n" + " sll %3, $1, 0 \n" + " dmfc0 $1, $3 \n" + " dsrl32 %4, $1, 0 \n" + " sll %5, $1, 0 \n" + " mfc0 %6, $5 \n" + ".set pop \n" + : "=r" (entryhihi), "=r" (entryhilo), + "=r" (entrylo0hi), "=r" (entrylo0lo), + "=r" (entrylo1hi), "=r" (entrylo1lo), + "=r" (pagemask)); + + printk("%08X%08X %08X%08X %08X%08X %08X", + entryhihi, entryhilo, + entrylo0hi, entrylo0lo, + entrylo1hi, entrylo1lo, + pagemask); +} + +void sb1_dump_tlb(void) +{ + unsigned long old_ctx; + unsigned long flags; + int entry; + local_irq_save(flags); + old_ctx = read_c0_entryhi(); + printk("Current TLB registers state:\n" + " EntryHi EntryLo0 EntryLo1 PageMask Index\n" + "--------------------------------------------------------------------\n"); + dump_cur_tlb_regs(); + printk(" %08X\n", read_c0_index()); + printk("\n\nFull TLB Dump:\n" + "Idx EntryHi EntryLo0 EntryLo1 PageMask\n" + "--------------------------------------------------------------\n"); + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { + write_c0_index(entry); + printk("\n%02i ", entry); + tlb_read(); + dump_cur_tlb_regs(); + } + printk("\n"); + write_c0_entryhi(old_ctx); + local_irq_restore(flags); +} + +void local_flush_tlb_all(void) +{ + unsigned long flags; + unsigned long old_ctx; + int entry; + + local_irq_save(flags); + /* Save old context and create impossible VPN2 value */ + old_ctx = read_c0_entryhi() & ASID_MASK; + write_c0_entrylo0(0); + write_c0_entrylo1(0); + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { + write_c0_entryhi(KSEG0 + (PAGE_SIZE << 1) * entry); + write_c0_index(entry); + tlb_write_indexed(); + } + write_c0_entryhi(old_ctx); + local_irq_restore(flags); +} + + +/* + * Use a bogus region of memory (starting at 0) to sanitize the TLB's. + * Use increments of the maximum page size (16MB), and check for duplicate + * entries before doing a given write. Then, when we're safe from collisions + * with the firmware, go back and give all the entries invalid addresses with + * the normal flush routine. + */ +void sb1_sanitize_tlb(void) +{ + int entry; + long addr = 0; + + long inc = 1<<24; /* 16MB */ + /* Save old context and create impossible VPN2 value */ + write_c0_entrylo0(0); + write_c0_entrylo1(0); + for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { + do { + addr += inc; + write_c0_entryhi(addr); + tlb_probe(); + } while ((int)(read_c0_index()) >= 0); + write_c0_index(entry); + tlb_write_indexed(); + } + /* Now that we know we're safe from collisions, we can safely flush + the TLB with the "normal" routine. */ + local_flush_tlb_all(); +} + +void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end) +{ + struct mm_struct *mm = vma->vm_mm; + unsigned long flags; + int cpu; + + local_irq_save(flags); + cpu = smp_processor_id(); + if (cpu_context(cpu, mm) != 0) { + int size; + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + size = (size + 1) >> 1; + if (size <= (current_cpu_data.tlbsize/2)) { + int oldpid = read_c0_entryhi() & ASID_MASK; + int newpid = cpu_asid(cpu, mm); + + start &= (PAGE_MASK << 1); + end += ((PAGE_SIZE << 1) - 1); + end &= (PAGE_MASK << 1); + while (start < end) { + int idx; + + write_c0_entryhi(start | newpid); + start += (PAGE_SIZE << 1); + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + write_c0_entryhi(KSEG0 + (idx << (PAGE_SHIFT+1))); + if (idx < 0) + continue; + tlb_write_indexed(); + } + write_c0_entryhi(oldpid); + } else { + drop_mmu_context(mm, cpu); + } + } + local_irq_restore(flags); +} + +void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) +{ + unsigned long flags; + int size; + + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + size = (size + 1) >> 1; + + local_irq_save(flags); + if (size <= (current_cpu_data.tlbsize/2)) { + int pid = read_c0_entryhi(); + + start &= (PAGE_MASK << 1); + end += ((PAGE_SIZE << 1) - 1); + end &= (PAGE_MASK << 1); + + while (start < end) { + int idx; + + write_c0_entryhi(start); + start += (PAGE_SIZE << 1); + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + write_c0_entryhi(KSEG0 + (idx << (PAGE_SHIFT+1))); + if (idx < 0) + continue; + tlb_write_indexed(); + } + write_c0_entryhi(pid); + } else { + local_flush_tlb_all(); + } + local_irq_restore(flags); +} + +void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) +{ + unsigned long flags; + int cpu = smp_processor_id(); + + local_irq_save(flags); + if (cpu_context(cpu, vma->vm_mm) != 0) { + int oldpid, newpid, idx; + newpid = cpu_asid(cpu, vma->vm_mm); + page &= (PAGE_MASK << 1); + oldpid = read_c0_entryhi() & ASID_MASK; + write_c0_entryhi(page | newpid); + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + if(idx < 0) + goto finish; + /* Make sure all entries differ. */ + write_c0_entryhi(KSEG0+(idx<<(PAGE_SHIFT+1))); + tlb_write_indexed(); + finish: + write_c0_entryhi(oldpid); + } + local_irq_restore(flags); +} + +/* + * This one is only used for pages with the global bit set so we don't care + * much about the ASID. + */ +void local_flush_tlb_one(unsigned long page) +{ + unsigned long flags; + int oldpid, idx; + + local_irq_save(flags); + page &= (PAGE_MASK << 1); + oldpid = read_c0_entryhi() & ASID_MASK; + write_c0_entryhi(page); + tlb_probe(); + idx = read_c0_index(); + write_c0_entrylo0(0); + write_c0_entrylo1(0); + if (idx >= 0) { + /* Make sure all entries differ. */ + write_c0_entryhi(KSEG0+(idx<<(PAGE_SHIFT+1))); + tlb_write_indexed(); + } + write_c0_entryhi(oldpid); + + local_irq_restore(flags); +} + +/* All entries common to a mm share an asid. To effectively flush + these entries, we just bump the asid. */ +void local_flush_tlb_mm(struct mm_struct *mm) +{ + int cpu = smp_processor_id(); + if (cpu_context(cpu, mm) != 0) { + drop_mmu_context(mm, cpu); + } +} + +/* Stolen from mips32 routines */ + +void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) +{ + unsigned long flags; + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + int idx, pid; + + /* + * Handle debugger faulting in for debugee. + */ + if (current->active_mm != vma->vm_mm) + return; + + local_irq_save(flags); + + pid = read_c0_entryhi() & ASID_MASK; + address &= (PAGE_MASK << 1); + write_c0_entryhi(address | (pid)); + pgdp = pgd_offset(vma->vm_mm, address); + tlb_probe(); + pmdp = pmd_offset(pgdp, address); + idx = read_c0_index(); + ptep = pte_offset_map(pmdp, address); + write_c0_entrylo0(pte_val(*ptep++) >> 6); + write_c0_entrylo1(pte_val(*ptep) >> 6); + if (idx < 0) { + tlb_write_random(); + } else { + tlb_write_indexed(); + } + local_irq_restore(flags); +} + +/* + * This is called from loadmmu.c. We have to set up all the + * memory management function pointers, as well as initialize + * the caches and tlbs + */ +void sb1_tlb_init(void) +{ + u32 config1; + + write_c0_pagemask(PM_4K); + config1 = read_c0_config1(); + current_cpu_data.tlbsize = ((config1 >> 25) & 0x3f) + 1; + + /* + * We don't know what state the firmware left the TLB's in, so this is + * the ultra-conservative way to flush the TLB's and avoid machine + * check exceptions due to duplicate TLB entries + */ + sb1_sanitize_tlb(); + + memcpy((void *)KSEG0, except_vec0_sb1, 0x80); + flush_icache_range(KSEG0, KSEG0 + 0x80); +} --- linux-2.5.73/arch/mips/mm/umap.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,222 +0,0 @@ -/* - * (C) Copyright 1994 Linus Torvalds - * - * Changes: - * - * Modified from Linus source to removing active mappings from any - * task. This is required for implementing the virtual graphics - * interface for direct rendering on the SGI - miguel. - * - * Added a routine to map a vmalloc()ed area into user space, this one - * is required by the /dev/shmiq driver - miguel. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -static inline void -remove_mapping_pte_range (pmd_t *pmd, unsigned long address, unsigned long size) -{ - pte_t *pte; - unsigned long end; - - if (pmd_none (*pmd)) - return; - if (pmd_bad (*pmd)){ - printk ("remove_graphics_pte_range: bad pmd (%08lx)\n", pmd_val (*pmd)); - pmd_clear (pmd); - return; - } - pte = pte_offset (pmd, address); - address &= ~PMD_MASK; - end = address + size; - if (end > PMD_SIZE) - end = PMD_SIZE; - do { - pte_t entry = *pte; - if (pte_present (entry)) - set_pte (pte, pte_modify (entry, PAGE_NONE)); - address += PAGE_SIZE; - pte++; - } while (address < end); - -} - -static inline void -remove_mapping_pmd_range (pgd_t *pgd, unsigned long address, unsigned long size) -{ - pmd_t *pmd; - unsigned long end; - - if (pgd_none (*pgd)) - return; - - if (pgd_bad (*pgd)){ - printk ("remove_graphics_pmd_range: bad pgd (%08lx)\n", pgd_val (*pgd)); - pgd_clear (pgd); - return; - } - pmd = pmd_offset (pgd, address); - address &= ~PGDIR_MASK; - end = address + size; - if (end > PGDIR_SIZE) - end = PGDIR_SIZE; - do { - remove_mapping_pte_range (pmd, address, end - address); - address = (address + PMD_SIZE) & PMD_MASK; - pmd++; - } while (address < end); - -} - -/* - * This routine is called from the page fault handler to remove a - * range of active mappings at this point - */ -void -remove_mapping (struct vm_area_struct *vma, struct task_struct *task, unsigned long start, unsigned long end) -{ - unsigned long beg = start; - pgd_t *dir; - - down_write (&task->mm->mmap_sem); - dir = pgd_offset (task->mm, start); - flush_cache_range (vma, beg, end); - while (start < end){ - remove_mapping_pmd_range (dir, start, end - start); - start = (start + PGDIR_SIZE) & PGDIR_MASK; - dir++; - } - flush_tlb_range (vma, beg, end); - up_write (&task->mm->mmap_sem); -} - -EXPORT_SYMBOL(remove_mapping); - -void *vmalloc_uncached (unsigned long size) -{ - return __vmalloc (size, GFP_KERNEL | __GFP_HIGHMEM, - PAGE_KERNEL_UNCACHED); -} - -static inline void free_pte(pte_t page) -{ - if (pte_present(page)) { - unsigned long pfn = pte_pfn(page); - struct page *ptpage; - if (!pfn_valid(pfn)) - return; - ptpage = pfn_to_page(pfn); - if (PageReserved(ptpage)) - return; - __free_page(ptpage); - if (current->mm->rss <= 0) - return; - current->mm->rss--; - return; - } - swap_free(pte_to_swp_entry(page)); -} - -static inline void forget_pte(pte_t page) -{ - if (!pte_none(page)) { - printk("forget_pte: old mapping existed!\n"); - free_pte(page); - } -} - -/* - * maps a range of vmalloc()ed memory into the requested pages. the old - * mappings are removed. - */ -static inline void -vmap_pte_range (pte_t *pte, unsigned long address, unsigned long size, unsigned long vaddr) -{ - unsigned long end; - pgd_t *vdir; - pmd_t *vpmd; - pte_t *vpte; - - address &= ~PMD_MASK; - end = address + size; - if (end > PMD_SIZE) - end = PMD_SIZE; - do { - pte_t oldpage = *pte; - struct page * page; - pte_clear(pte); - - vdir = pgd_offset_k (vaddr); - vpmd = pmd_offset (vdir, vaddr); - vpte = pte_offset (vpmd, vaddr); - page = pte_page (*vpte); - - set_pte(pte, mk_pte(page, PAGE_USERIO)); - forget_pte(oldpage); - address += PAGE_SIZE; - vaddr += PAGE_SIZE; - pte++; - } while (address < end); -} - -static inline int -vmap_pmd_range (pmd_t *pmd, unsigned long address, unsigned long size, unsigned long vaddr) -{ - unsigned long end; - - address &= ~PGDIR_MASK; - end = address + size; - if (end > PGDIR_SIZE) - end = PGDIR_SIZE; - vaddr -= address; - do { - pte_t * pte = pte_alloc(current->mm, pmd, address); - if (!pte) - return -ENOMEM; - vmap_pte_range(pte, address, end - address, address + vaddr); - address = (address + PMD_SIZE) & PMD_MASK; - pmd++; - } while (address < end); - return 0; -} - -int -vmap_page_range (struct vm_area_struct *vma, unsigned long from, unsigned long size, unsigned long vaddr) -{ - int error = 0; - pgd_t * dir; - unsigned long beg = from; - unsigned long end = from + size; - - vaddr -= from; - dir = pgd_offset(current->mm, from); - flush_cache_range(vma, beg, end); - while (from < end) { - pmd_t *pmd = pmd_alloc(current->mm, dir, from); - error = -ENOMEM; - if (!pmd) - break; - error = vmap_pmd_range(pmd, from, end - from, vaddr + from); - if (error) - break; - from = (from + PGDIR_SIZE) & PGDIR_MASK; - dir++; - } - flush_tlb_range(vma, beg, end); - return error; -} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_c/cpci-irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,154 @@ +/* + * Copyright 2002 Momentum Computer + * Author: mdharm@momenco.com + * + * arch/mips/momentum/ocelot_c/cpci-irq.c + * Interrupt routines for cpci. Interrupt numbers are assigned from + * CPCI_IRQ_BASE to CPCI_IRQ_BASE+8 (8 interrupt sources). + * + * Note that the high-level software will need to be careful about using + * these interrupts. If this board is asserting a cPCI interrupt, it will + * also see the asserted interrupt. Care must be taken to avoid an + * interrupt flood. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ocelot_c_fpga.h" + +#define CPCI_IRQ_BASE 8 + +static inline int ls1bit8(unsigned int x) +{ + int b = 7, s; + + s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s; + s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s; + s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s; + + return b; +} + +/* mask off an interrupt -- 0 is enable, 1 is disable */ +static inline void mask_cpci_irq(unsigned int irq) +{ + uint32_t value; + + value = OCELOT_FPGA_READ(INTMASK); + value |= 1 << (irq - CPCI_IRQ_BASE); + OCELOT_FPGA_WRITE(value, INTMASK); + + /* read the value back to assure that it's really been written */ + value = OCELOT_FPGA_READ(INTMASK); +} + +/* unmask an interrupt -- 0 is enable, 1 is disable */ +static inline void unmask_cpci_irq(unsigned int irq) +{ + uint32_t value; + + value = OCELOT_FPGA_READ(INTMASK); + value &= ~(1 << (irq - CPCI_IRQ_BASE)); + OCELOT_FPGA_WRITE(value, INTMASK); + + /* read the value back to assure that it's really been written */ + value = OCELOT_FPGA_READ(INTMASK); +} + +/* + * Enables the IRQ in the FPGA + */ +static void enable_cpci_irq(unsigned int irq) +{ + unmask_cpci_irq(irq); +} + +/* + * Initialize the IRQ in the FPGA + */ +static unsigned int startup_cpci_irq(unsigned int irq) +{ + unmask_cpci_irq(irq); + return 0; +} + +/* + * Disables the IRQ in the FPGA + */ +static void disable_cpci_irq(unsigned int irq) +{ + mask_cpci_irq(irq); +} + +/* + * Masks and ACKs an IRQ + */ +static void mask_and_ack_cpci_irq(unsigned int irq) +{ + mask_cpci_irq(irq); +} + +/* + * End IRQ processing + */ +static void end_cpci_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + unmask_cpci_irq(irq); +} + +/* + * Interrupt handler for interrupts coming from the FPGA chip. + * It could be built in ethernet ports etc... + */ +void ll_cpci_irq(struct pt_regs *regs) +{ + unsigned int irq_src, irq_mask; + + /* read the interrupt status registers */ + irq_src = OCELOT_FPGA_READ(INTSTAT); + irq_mask = OCELOT_FPGA_READ(INTMASK); + + /* mask for just the interrupts we want */ + irq_src &= ~irq_mask; + + do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE, regs); +} + +#define shutdown_cpci_irq disable_cpci_irq + +struct hw_interrupt_type cpci_irq_type = { + "CPCI/FPGA", + startup_cpci_irq, + shutdown_cpci_irq, + enable_cpci_irq, + disable_cpci_irq, + mask_and_ack_cpci_irq, + end_cpci_irq, + NULL +}; + +void cpci_irq_init(void) +{ + int i; + + /* Reset irq handlers pointers to NULL */ + for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 2; + irq_desc[i].handler = &cpci_irq_type; + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_c/dbg_io.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,126 @@ +#include + +#if defined(CONFIG_KGDB) + +#include /* For the serial port location and base baud */ + +/* --- CONFIG --- */ + +typedef unsigned char uint8; +typedef unsigned int uint32; + +/* --- END OF CONFIG --- */ + +#define UART16550_BAUD_2400 2400 +#define UART16550_BAUD_4800 4800 +#define UART16550_BAUD_9600 9600 +#define UART16550_BAUD_19200 19200 +#define UART16550_BAUD_38400 38400 +#define UART16550_BAUD_57600 57600 +#define UART16550_BAUD_115200 115200 + +#define UART16550_PARITY_NONE 0 +#define UART16550_PARITY_ODD 0x08 +#define UART16550_PARITY_EVEN 0x18 +#define UART16550_PARITY_MARK 0x28 +#define UART16550_PARITY_SPACE 0x38 + +#define UART16550_DATA_5BIT 0x0 +#define UART16550_DATA_6BIT 0x1 +#define UART16550_DATA_7BIT 0x2 +#define UART16550_DATA_8BIT 0x3 + +#define UART16550_STOP_1BIT 0x0 +#define UART16550_STOP_2BIT 0x4 + +/* ----------------------------------------------------- */ + +/* === CONFIG === */ + +/* [jsun] we use the second serial port for kdb */ +#define BASE OCELOT_SERIAL1_BASE +#define MAX_BAUD OCELOT_BASE_BAUD + +/* === END OF CONFIG === */ + +#define REG_OFFSET 4 + +/* register offset */ +#define OFS_RCV_BUFFER 0 +#define OFS_TRANS_HOLD 0 +#define OFS_SEND_BUFFER 0 +#define OFS_INTR_ENABLE (1*REG_OFFSET) +#define OFS_INTR_ID (2*REG_OFFSET) +#define OFS_DATA_FORMAT (3*REG_OFFSET) +#define OFS_LINE_CONTROL (3*REG_OFFSET) +#define OFS_MODEM_CONTROL (4*REG_OFFSET) +#define OFS_RS232_OUTPUT (4*REG_OFFSET) +#define OFS_LINE_STATUS (5*REG_OFFSET) +#define OFS_MODEM_STATUS (6*REG_OFFSET) +#define OFS_RS232_INPUT (6*REG_OFFSET) +#define OFS_SCRATCH_PAD (7*REG_OFFSET) + +#define OFS_DIVISOR_LSB (0*REG_OFFSET) +#define OFS_DIVISOR_MSB (1*REG_OFFSET) + + +/* memory-mapped read/write of the port */ +#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) +#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) + +void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) +{ + /* disable interrupts */ + UART16550_WRITE(OFS_INTR_ENABLE, 0); + + /* set up buad rate */ + { + uint32 divisor; + + /* set DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x80); + + /* set divisor */ + divisor = MAX_BAUD / baud; + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); + + /* clear DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x0); + } + + /* set data format */ + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); +} + +static int remoteDebugInitialized = 0; + +uint8 getDebugChar(void) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(UART16550_BAUD_38400, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); + return UART16550_READ(OFS_RCV_BUFFER); +} + + +int putDebugChar(uint8 byte) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(UART16550_BAUD_38400, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); + UART16550_WRITE(OFS_SEND_BUFFER, byte); + return 1; +} + +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_c/int-handler.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,104 @@ +/* + * Copyright 2002 Momentum Computer Inc. + * Author: Matthew Dharm + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * First-level interrupt dispatcher for Ocelot-CS board. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#define __ASSEMBLY__ +#include +#include +#include +#include +#include +#include +#include "ocelot_c_fpga.h" + +/* + * First level interrupt dispatcher for Ocelot-CS board + */ + .align 5 + NESTED(ocelot_handle_int, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + mfc0 t0, CP0_CAUSE + mfc0 t2, CP0_STATUS + + and t0, t2 + + andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ + bnez t1, ll_sw0_irq + andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ + bnez t1, ll_sw1_irq + andi t1, t0, STATUSF_IP2 /* int0 hardware line */ + bnez t1, ll_scsi_irq + andi t1, t0, STATUSF_IP3 /* int1 hardware line */ + bnez t1, ll_uart_decode_irq + andi t1, t0, STATUSF_IP4 /* int2 hardware line */ + bnez t1, ll_pmc_irq + andi t1, t0, STATUSF_IP5 /* int3 hardware line */ + bnez t1, ll_cpci_decode_irq + andi t1, t0, STATUSF_IP6 /* int4 hardware line */ + bnez t1, ll_mv64340_decode_irq + andi t1, t0, STATUSF_IP7 /* cpu timer */ + bnez t1, ll_cputimer_irq + + .set reorder + + /* wrong alarm or masked ... */ + j spurious_interrupt + nop + END(ocelot_handle_int) + + .align 5 +ll_sw0_irq: + li a0, 0 + move a1, sp + jal do_IRQ + j ret_from_irq +ll_sw1_irq: + li a0, 1 + move a1, sp + jal do_IRQ + j ret_from_irq +ll_scsi_irq: + li a0, 2 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_uart_decode_irq: + move a0, sp + jal ll_uart_irq + j ret_from_irq + +ll_pmc_irq: + li a0, 4 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpci_decode_irq: + move a0, sp + jal ll_cpci_irq + j ret_from_irq + +ll_mv64340_decode_irq: + move a0, sp + jal ll_mv64340_irq + j ret_from_irq + +ll_cputimer_irq: + li a0, 7 + move a1, sp + jal do_IRQ + j ret_from_irq + --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_c/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2000 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +static spinlock_t irq_lock = SPIN_LOCK_UNLOCKED; + +/* Function for careful CP0 interrupt mask access */ +static inline void modify_cp0_intmask(unsigned clr_mask_in, unsigned set_mask_in) +{ + unsigned long status; + unsigned clr_mask; + unsigned set_mask; + + /* do the low 8 bits first */ + clr_mask = 0xff & clr_mask_in; + set_mask = 0xff & set_mask_in; + status = read_c0_status(); + status &= ~((clr_mask & 0xFF) << 8); + status |= (set_mask & 0xFF) << 8; + write_c0_status(status); +} + +static inline void mask_irq(unsigned int irq) +{ + modify_cp0_intmask(irq, 0); +} + +static inline void unmask_irq(unsigned int irq) +{ + modify_cp0_intmask(0, irq); +} + +static void enable_cp7000_irq(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&irq_lock, flags); + unmask_irq(1 << irq); + spin_unlock_irqrestore(&irq_lock, flags); +} + +static unsigned int startup_cp7000_irq(unsigned int irq) +{ + enable_cp7000_irq(irq); + + return 0; /* never anything pending */ +} + +static void disable_cp7000_irq(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&irq_lock, flags); + mask_irq(1 << irq); + spin_unlock_irqrestore(&irq_lock, flags); +} + +#define shutdown_cp7000_irq disable_cp7000_irq + +static void mask_and_ack_cp7000_irq(unsigned int irq) +{ + mask_irq(1 << irq); +} + +static void end_cp7000_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + unmask_irq(1 << irq); +} + +static struct hw_interrupt_type cp7000_hpcdma_irq_type = { +#ifdef CONFIG_CPU_SR71000 + "SR71000", +#else + "RM7000", +#endif + startup_cp7000_irq, + shutdown_cp7000_irq, + enable_cp7000_irq, + disable_cp7000_irq, + mask_and_ack_cp7000_irq, + end_cp7000_irq, + NULL +}; + +extern asmlinkage void ocelot_handle_int(void); +extern void mv64340_irq_init(void); +extern void uart_irq_init(void); +extern void cpci_irq_init(void); + +static struct irqaction cascade_fpga = + { no_action, SA_INTERRUPT, 0, "cascade via FPGA", NULL, NULL }; +static struct irqaction cascade_mv64340 = + { no_action, SA_INTERRUPT, 0, "cascade via MV64340", NULL, NULL }; + +void __init init_IRQ(void) +{ + int i; + + /* + * Clear all of the interrupts while we change the able around a bit. + * int-handler is not on bootstrap + */ + clear_c0_status(ST0_IM | ST0_BEV); + __cli(); + + /* Sets the first-level interrupt dispatcher. */ + set_except_vector(0, ocelot_handle_int); + init_generic_irq(); + + /* set up handler for first 8 IRQs as the CPU */ + for (i = 0; i < 8; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &cp7000_hpcdma_irq_type; + } + + /* set up the cascading interrupts */ + setup_irq(3, &cascade_fpga); + setup_irq(5, &cascade_fpga); + setup_irq(6, &cascade_mv64340); + + mv64340_irq_init(); + uart_irq_init(); + cpci_irq_init(); + +#ifdef CONFIG_KGDB + printk("start kgdb ...\n"); + set_debug_traps(); + breakpoint(); /* you may move this line to whereever you want :-) */ +#endif +#ifdef CONFIG_GDB_CONSOLE + register_gdb_console(); +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_c/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,8 @@ +# +# Makefile for Momentum Computer's Ocelot-C and -CS boards. +# + +obj-y += mv-irq.o cpci-irq.o uart-irq.o int-handler.o irq.o \ + pci-irq.o prom.o reset.o setup.o + +obj-$(CONFIG_KGDB) += dbg_io.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_c/mv-irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,164 @@ +/* + * Copyright 2002 Momentum Computer + * Author: mdharm@momenco.com + * + * arch/mips/momentum/ocelot_c/mv-irq.c + * Interrupt routines for mv64340. Interrupt numbers are assigned from + * MV64340_IRQ_BASE to MV64340_IRQ_BASE+64. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MV64340_IRQ_BASE 16 + +static inline int ls1bit32(unsigned int x) +{ + int b = 31, s; + + s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s; + s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s; + s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s; + s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s; + s = 1; if (x << 1 == 0) s = 0; b -= s; + + return b; +} + +/* mask off an interrupt -- 1 is enable, 0 is disable */ +static inline void mask_mv64340_irq(unsigned int irq) +{ + uint32_t value; + + if (irq < (MV64340_IRQ_BASE + 32)) { + MV_READ(MV64340_INTERRUPT0_MASK_0_LOW, &value); + value &= ~(1 << (irq - MV64340_IRQ_BASE)); + MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value); + } else { + MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH, &value); + value &= ~(1 << (irq - (MV64340_IRQ_BASE - 32))); + MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value); + } +} + +/* unmask an interrupt -- 1 is enable, 0 is disable */ +static inline void unmask_mv64340_irq(unsigned int irq) +{ + uint32_t value; + + if (irq < (MV64340_IRQ_BASE + 32)) { + MV_READ(MV64340_INTERRUPT0_MASK_0_LOW, &value); + value |= 1 << (irq - MV64340_IRQ_BASE); + MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value); + } else { + MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH, &value); + value |= 1 << (irq - (MV64340_IRQ_BASE - 32)); + MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value); + } +} + +/* + * Enables the IRQ on Marvell Chip + */ +static void enable_mv64340_irq(unsigned int irq) +{ + unmask_mv64340_irq(irq); +} + +/* + * Initialize the IRQ on Marvell Chip + */ +static unsigned int startup_mv64340_irq(unsigned int irq) +{ + unmask_mv64340_irq(irq); + return 0; +} + +/* + * Disables the IRQ on Marvell Chip + */ +static void disable_mv64340_irq(unsigned int irq) +{ + mask_mv64340_irq(irq); +} + +/* + * Masks and ACKs an IRQ + */ +static void mask_and_ack_mv64340_irq(unsigned int irq) +{ + mask_mv64340_irq(irq); +} + +/* + * End IRQ processing + */ +static void end_mv64340_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + unmask_mv64340_irq(irq); +} + +/* + * Interrupt handler for interrupts coming from the Marvell chip. + * It could be built in ethernet ports etc... + */ +void ll_mv64340_irq(struct pt_regs *regs) +{ + unsigned int irq_src_low, irq_src_high; + unsigned int irq_mask_low, irq_mask_high; + + /* read the interrupt status registers */ + MV_READ(MV64340_INTERRUPT0_MASK_0_LOW, &irq_mask_low); + MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH, &irq_mask_high); + MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_LOW, &irq_src_low); + MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_HIGH, &irq_src_high); + + /* mask for just the interrupts we want */ + irq_src_low &= irq_mask_low; + irq_src_high &= irq_mask_high; + + if (irq_src_low) + do_IRQ(ls1bit32(irq_src_low) + MV64340_IRQ_BASE, regs); + else + do_IRQ(ls1bit32(irq_src_high) + MV64340_IRQ_BASE + 32, regs); +} + +#define shutdown_mv64340_irq disable_mv64340_irq + +struct hw_interrupt_type mv64340_irq_type = { + "MV-64340", + startup_mv64340_irq, + shutdown_mv64340_irq, + enable_mv64340_irq, + disable_mv64340_irq, + mask_and_ack_mv64340_irq, + end_mv64340_irq, + NULL +}; + +void mv64340_irq_init(void) +{ + int i; + + /* Reset irq handlers pointers to NULL */ + for (i = MV64340_IRQ_BASE; i < (MV64340_IRQ_BASE + 64); i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 2; + irq_desc[i].handler = &mv64340_irq_type; + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,50 @@ +/* + * Ocelot-C Board Register Definitions + * + * (C) 2002 Momentum Computer Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __OCELOT_C_FPGA_H__ +#define __OCELOT_C_FPGA_H__ + +#define OCELOT_C_CS0_ADDR (0xfc000000) + +#define OCELOT_C_REG_BOARDREV 0x0 +#define OCELOT_C_REG_FPGA_REV 0x1 +#define OCELOT_C_REG_FPGA_TYPE 0x2 +#define OCELOT_C_REG_RESET_STATUS 0x3 +#define OCELOT_C_REG_BOARD_STATUS 0x4 +#define OCELOT_C_REG_CPCI_ID 0x5 +#define OCELOT_C_REG_SET 0x6 +#define OCELOT_C_REG_CLR 0x7 +#define OCELOT_C_REG_EEPROM_MODE 0x9 +#define OCELOT_C_REG_INTMASK 0xa +#define OCELOT_C_REG_INTSTAT 0xb +#define OCELOT_C_REG_UART_INTMASK 0xc +#define OCELOT_C_REG_UART_INTSTAT 0xd +#define OCELOT_C_REG_INTSET 0xe +#define OCELOT_C_REG_INTCLR 0xf + +#define OCELOT_FPGA_WRITE(x, y) writeb(x, OCELOT_C_CS0_ADDR + OCELOT_C_REG_##y) +#define OCELOT_FPGA_READ(x) readb(OCELOT_C_CS0_ADDR + OCELOT_C_REG_##x) + +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_c/pci-irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,73 @@ +/* + * Copyright 2002 Momentum Computer Inc. + * Author: Matthew Dharm + * + * Based on work for the Linux port to the Ocelot board, which is + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * arch/mips/momentum/ocelot_g/pci.c + * Board-specific PCI routines for mv64340 controller. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include + + +void __init mv64340_board_pcibios_fixup_bus(struct pci_bus *bus) +{ + struct pci_bus *current_bus = bus; + struct pci_dev *devices; + struct list_head *devices_link; + u16 cmd; + + /* loop over all known devices on this bus */ + list_for_each(devices_link, &(current_bus->devices)) { + + devices = pci_dev_b(devices_link); + if (devices == NULL) + continue; + + if ((current_bus->number == 0) && + (PCI_SLOT(devices->devfn) == 1) && + (PCI_FUNC(devices->devfn) == 0)) { + /* LSI 53C10101R SCSI (A) */ + devices->irq = 2; + } else if ((current_bus->number == 0) && + (PCI_SLOT(devices->devfn) == 1) && + (PCI_FUNC(devices->devfn) == 1)) { + /* LSI 53C10101R SCSI (B) */ + devices->irq = 2; + } else if ((current_bus->number == 1) && + (PCI_SLOT(devices->devfn) == 1)) { + /* Intel 21555 bridge */ + devices->irq = 12; + } else if ((current_bus->number == 1) && + (PCI_SLOT(devices->devfn) == 2)) { + /* PMC Slot */ + devices->irq = 4; + } else { + /* We don't have assign interrupts for other devices. */ + devices->irq = 0xff; + } + + /* Assign an interrupt number for the device */ + bus->ops->write_byte(devices, PCI_INTERRUPT_LINE, devices->irq); + + /* enable master for everything but the MV-64340 */ + if (((current_bus->number != 0) && (current_bus->number != 1)) + || (PCI_SLOT(devices->devfn) != 0)) { + bus->ops->read_word(devices, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + bus->ops->write_word(devices, PCI_COMMAND, cmd); + } + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_c/prom.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,151 @@ +/* + * Copyright 2002 Momentum Computer Inc. + * Author: Matthew Dharm + * + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "ocelot_c_fpga.h" + +struct callvectors { + int (*open) (char*, int, int); + int (*close) (int); + int (*read) (int, void*, int); + int (*write) (int, void*, int); + off_t (*lseek) (int, off_t, int); + int (*printf) (const char*, ...); + void (*cacheflush) (void); + char* (*gets) (char*); +}; + +struct callvectors* debug_vectors; +char arcs_cmdline[CL_SIZE]; + +extern unsigned long mv64340_base; +extern unsigned long cpu_clock; + +#ifdef CONFIG_MV64340_ETH +extern unsigned char prom_mac_addr_base[6]; +#endif + +const char *get_system_type(void) +{ +#ifdef CONFIG_CPU_SR71000 + return "Momentum Ocelot-CS"; +#else + return "Momentum Ocelot-C"; +#endif +} + +#ifdef CONFIG_MV64340_ETH +static void burn_clocks(void) +{ + int i; + + /* this loop should burn at least 1us -- this should be plenty */ + for (i = 0; i < 0x10000; i++) + ; +} + +static u8 exchange_bit(u8 val, u8 cs) +{ + /* place the data */ + OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE); + burn_clocks(); + + /* turn the clock on */ + OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE); + burn_clocks(); + + /* turn the clock off and read-strobe */ + OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); + + /* return the data */ + return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); +} + +void get_mac(char dest[6]) +{ + u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + int i,j; + + for (i = 0; i < 12; i++) + exchange_bit(read_opcode[i], 1); + + for (j = 0; j < 6; j++) { + dest[j] = 0; + for (i = 0; i < 8; i++) { + dest[j] <<= 1; + dest[j] |= exchange_bit(0, 1); + } + } + + /* turn off CS */ + exchange_bit(0,0); +} +#endif + +/* [jsun@junsun.net] PMON passes arguments in C main() style */ +void __init prom_init(int argc, char **arg, char** env, struct callvectors *cv) +{ + int i; + + /* save the PROM vectors for debugging use */ + debug_vectors = cv; + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + for (i = 1; i < argc; i++) { + if (strlen(arcs_cmdline) + strlen(arg[i] + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, arg[i]); + strcat(arcs_cmdline, " "); + } + + mips_machgroup = MACH_GROUP_MOMENCO; + mips_machtype = MACH_MOMENCO_OCELOT_C; + + while (*env) { + if (strncmp("gtbase", *env, strlen("gtbase")) == 0) { + mv64340_base = simple_strtol(*env + strlen("gtbase="), + NULL, 16); + } + if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) { + cpu_clock = simple_strtol(*env + strlen("cpuclock="), + NULL, 10); + } + env++; + } + +#ifdef CONFIG_MV64340_ETH + /* get the base MAC address for on-board ethernet ports */ + get_mac(prom_mac_addr_base); +#endif + + debug_vectors->printf("Booting Linux kernel...\n"); +} + +void __init prom_free_prom_memory(void) +{ +} + +void __init prom_fixup_mem_map(unsigned long start, unsigned long end) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_c/reset.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,50 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 1997, 2001 Ralf Baechle + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright (C) 2002 Momentum Computer Inc. + * Author: Matthew Dharm + */ +#include +#include +#include +#include +#include +#include +#include +#include + +void momenco_ocelot_restart(char *command) +{ + /* base address of timekeeper portion of part */ + void *nvram = (void*) 0xfc807000; + + /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */ + writeb(0x84, nvram + 0xff7); + + /* wait for the watchdog to go off */ + mdelay(100+(1000/16)); + + /* if the watchdog fails for some reason, let people know */ + printk(KERN_NOTICE "Watchdog reset failed\n"); +} + +void momenco_ocelot_halt(void) +{ + printk(KERN_NOTICE "\n** You can safely turn off the power\n"); + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void momenco_ocelot_power_off(void) +{ + momenco_ocelot_halt(); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_c/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,326 @@ +/* + * BRIEF MODULE DESCRIPTION + * Momentum Computer Ocelot-C and -CS board dependent boot routines + * + * Copyright (C) 1996, 1997, 2001 Ralf Baechle + * Copyright (C) 2000 RidgeRun, Inc. + * Copyright (C) 2001 Red Hat, Inc. + * Copyright (C) 2002 Momentum Computer + * + * Author: Matthew Dharm, Momentum Computer + * mdharm@momenco.com + * + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ocelot_c_fpga.h" + +unsigned long mv64340_base; +unsigned long cpu_clock; + +/* These functions are used for rebooting or halting the machine*/ +extern void momenco_ocelot_restart(char *command); +extern void momenco_ocelot_halt(void); +extern void momenco_ocelot_power_off(void); + +void momenco_time_init(void); + +static char reset_reason; + +#define ENTRYLO(x) ((pte_val(mk_pte_phys((x), PAGE_KERNEL_UNCACHED)) >> 6)|1) + +/* setup code for a handoff from a version 2 PMON 2000 PROM */ +void PMON_v2_setup(void) +{ + /* Some wired TLB entries for the MV64340 and perhiperals. The + MV64340 is going to be hit on every IRQ anyway - there's + absolutely no point in letting it be a random TLB entry, as + it'll just cause needless churning of the TLB. And we use + the other half for the serial port, which is just a PITA + otherwise :) + + Device Physical Virtual + MV64340 Internal Regs 0xf4000000 0xf4000000 + Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000 + NVRAM (CS1) 0xfc800000 0xfc800000 + UARTs (CS2) 0xfd000000 0xfd000000 + Internal SRAM 0xfe000000 0xfe000000 + M-Systems DOC (CS3) 0xff000000 0xff000000 + */ + + /* marvell and extra space */ + add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K); + /* fpga, rtc, and uart */ + add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M); + /* m-sys and internal SRAM */ + add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M); + + mv64340_base = 0xf4000000; +} + +unsigned long m48t37y_get_time(void) +{ + unsigned char* rtc_base = (unsigned char*)0xfc800000; + unsigned int year, month, day, hour, min, sec; + + /* stop the update */ + rtc_base[0x7ff8] = 0x40; + + year = BCD2BIN(rtc_base[0x7fff]); + year += BCD2BIN(rtc_base[0x7ff1]) * 100; + + month = BCD2BIN(rtc_base[0x7ffe]); + + day = BCD2BIN(rtc_base[0x7ffd]); + + hour = BCD2BIN(rtc_base[0x7ffb]); + min = BCD2BIN(rtc_base[0x7ffa]); + sec = BCD2BIN(rtc_base[0x7ff9]); + + /* start the update */ + rtc_base[0x7ff8] = 0x00; + + return mktime(year, month, day, hour, min, sec); +} + +int m48t37y_set_time(unsigned long sec) +{ + unsigned char* rtc_base = (unsigned char*)0xfc800000; + struct rtc_time tm; + + /* convert to a more useful format -- note months count from 0 */ + to_tm(sec, &tm); + tm.tm_mon += 1; + + /* enable writing */ + rtc_base[0x7ff8] = 0x80; + + /* year */ + rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100); + rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100); + + /* month */ + rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon); + + /* day */ + rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday); + + /* hour/min/sec */ + rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour); + rtc_base[0x7ffa] = BIN2BCD(tm.tm_min); + rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec); + + /* day of week -- not really used, but let's keep it up-to-date */ + rtc_base[0x7ffc] = CONV_BIN2BCD(tm.tm_wday + 1); + + /* disable writing */ + rtc_base[0x7ff8] = 0x00; + + return 0; +} + +void momenco_timer_setup(struct irqaction *irq) +{ + setup_irq(7, irq); +} + +void momenco_time_init(void) +{ +#ifdef CONFIG_CPU_SR71000 + mips_counter_frequency = cpu_clock; +#elif defined(CONFIG_CPU_RM7000) + mips_counter_frequency = cpu_clock / 2; +#else +#error Unknown CPU for this board +#endif + board_timer_setup = momenco_timer_setup; + + rtc_get_time = m48t37y_get_time; + rtc_set_time = m48t37y_set_time; +} + +void __init momenco_ocelot_c_setup(void) +{ + unsigned int tmpword; + + board_time_init = momenco_time_init; + + _machine_restart = momenco_ocelot_restart; + _machine_halt = momenco_ocelot_halt; + _machine_power_off = momenco_ocelot_power_off; + + /* + * initrd_start = (ulong)ocelot_initrd_start; + * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size; + * initrd_below_start_ok = 1; + */ + + /* do handoff reconfiguration */ + PMON_v2_setup(); + + /* shut down ethernet ports, just to be sure our memory doesn't get + * corrupted by random ethernet traffic. + */ + MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8); + MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8); + MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8); + MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8); + do {} + while (MV_READ_DATA(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff); + do {} + while (MV_READ_DATA(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff); + do {} + while (MV_READ_DATA(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff); + do {} + while (MV_READ_DATA(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff); + MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), MV_READ_DATA(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1); + MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), MV_READ_DATA(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1); + + /* Turn off the Bit-Error LED */ + OCELOT_FPGA_WRITE(0x80, CLR); + + tmpword = OCELOT_FPGA_READ(BOARDREV); +#ifdef CONFIG_CPU_SR71000 + if (tmpword < 26) + printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n", + 'A'+tmpword); + else + printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n", + tmpword); +#else + if (tmpword < 26) + printk("Momenco Ocelot-C: Board Assembly Rev. %c\n", + 'A'+tmpword); + else + printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n", + tmpword); +#endif + + tmpword = OCELOT_FPGA_READ(FPGA_REV); + printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15); + tmpword = OCELOT_FPGA_READ(RESET_STATUS); + printk("Reset reason: 0x%x\n", tmpword); + switch (tmpword) { + case 0x1: + printk(" - Power-up reset\n"); + break; + case 0x2: + printk(" - Push-button reset\n"); + break; + case 0x4: + printk(" - cPCI bus reset\n"); + break; + case 0x8: + printk(" - Watchdog reset\n"); + break; + case 0x10: + printk(" - Software reset\n"); + break; + default: + printk(" - Unknown reset cause\n"); + } + reset_reason = tmpword; + OCELOT_FPGA_WRITE(0xff, RESET_STATUS); + + tmpword = OCELOT_FPGA_READ(CPCI_ID); + printk("cPCI ID register: 0x%02x\n", tmpword); + printk(" - Slot number: %d\n", tmpword & 0x1f); + printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no"); + printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no"); + + tmpword = OCELOT_FPGA_READ(BOARD_STATUS); + printk("Board Status register: 0x%02x\n", tmpword); + printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); + printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); + printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1); + printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3))); + + switch(tmpword &3) { + case 3: + /* 512MiB */ + add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM); + break; + case 2: + /* 256MiB */ + add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM); + break; + case 1: + /* 128MiB */ + add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM); + break; + case 0: + /* 1GiB -- needs CONFIG_HIGHMEM */ + add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM); + break; + } +} + +/* This needs to be one of the first initcalls, because no I/O port access + can work before this */ +static int io_base_ioremap(void) +{ + /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */ + void *io_remap_range = ioremap(0xc0000000, 0x30000000); + + if (!io_remap_range) { + panic("Could not ioremap I/O port range"); + } + printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range); + set_io_port_base(io_remap_range - 0xc0000000); + + return 0; +} + +module_init(io_base_ioremap); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_c/uart-irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,148 @@ +/* + * Copyright 2002 Momentum Computer + * Author: mdharm@momenco.com + * + * arch/mips/momentum/ocelot_c/uart-irq.c + * Interrupt routines for UARTs. Interrupt numbers are assigned from + * 80 to 81 (2 interrupt sources). + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ocelot_c_fpga.h" + +static inline int ls1bit8(unsigned int x) +{ + int b = 7, s; + + s = 4; if (((unsigned char)(x << 4)) == 0) s = 0; b -= s; x <<= s; + s = 2; if (((unsigned char)(x << 2)) == 0) s = 0; b -= s; x <<= s; + s = 1; if (((unsigned char)(x << 1)) == 0) s = 0; b -= s; + + return b; +} + +/* mask off an interrupt -- 0 is enable, 1 is disable */ +static inline void mask_uart_irq(unsigned int irq) +{ + uint8_t value; + + value = OCELOT_FPGA_READ(UART_INTMASK); + value |= 1 << (irq - 74); + OCELOT_FPGA_WRITE(value, UART_INTMASK); + + /* read the value back to assure that it's really been written */ + value = OCELOT_FPGA_READ(UART_INTMASK); +} + +/* unmask an interrupt -- 0 is enable, 1 is disable */ +static inline void unmask_uart_irq(unsigned int irq) +{ + uint8_t value; + + value = OCELOT_FPGA_READ(UART_INTMASK); + value &= ~(1 << (irq - 74)); + OCELOT_FPGA_WRITE(value, UART_INTMASK); + + /* read the value back to assure that it's really been written */ + value = OCELOT_FPGA_READ(UART_INTMASK); +} + +/* + * Enables the IRQ in the FPGA + */ +static void enable_uart_irq(unsigned int irq) +{ + unmask_uart_irq(irq); +} + +/* + * Initialize the IRQ in the FPGA + */ +static unsigned int startup_uart_irq(unsigned int irq) +{ + unmask_uart_irq(irq); + return 0; +} + +/* + * Disables the IRQ in the FPGA + */ +static void disable_uart_irq(unsigned int irq) +{ + mask_uart_irq(irq); +} + +/* + * Masks and ACKs an IRQ + */ +static void mask_and_ack_uart_irq(unsigned int irq) +{ + mask_uart_irq(irq); +} + +/* + * End IRQ processing + */ +static void end_uart_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + unmask_uart_irq(irq); +} + +/* + * Interrupt handler for interrupts coming from the FPGA chip. + */ +void ll_uart_irq(struct pt_regs *regs) +{ + unsigned int irq_src, irq_mask; + + /* read the interrupt status registers */ + irq_src = OCELOT_FPGA_READ(UART_INTSTAT); + irq_mask = OCELOT_FPGA_READ(UART_INTMASK); + + /* mask for just the interrupts we want */ + irq_src &= ~irq_mask; + + do_IRQ(ls1bit8(irq_src) + 74, regs); +} + +#define shutdown_uart_irq disable_uart_irq + +struct hw_interrupt_type uart_irq_type = { + "UART/FPGA", + startup_uart_irq, + shutdown_uart_irq, + enable_uart_irq, + disable_uart_irq, + mask_and_ack_uart_irq, + end_uart_irq, + NULL +}; + +void uart_irq_init(void) +{ + /* Reset irq handlers pointers to NULL */ + irq_desc[80].status = IRQ_DISABLED; + irq_desc[80].action = 0; + irq_desc[80].depth = 2; + irq_desc[80].handler = &uart_irq_type; + + irq_desc[81].status = IRQ_DISABLED; + irq_desc[81].action = 0; + irq_desc[81].depth = 2; + irq_desc[81].handler = &uart_irq_type; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_g/dbg_io.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,126 @@ +#include + +#if defined(CONFIG_KGDB) + +#include /* For the serial port location and base baud */ + +/* --- CONFIG --- */ + +typedef unsigned char uint8; +typedef unsigned int uint32; + +/* --- END OF CONFIG --- */ + +#define UART16550_BAUD_2400 2400 +#define UART16550_BAUD_4800 4800 +#define UART16550_BAUD_9600 9600 +#define UART16550_BAUD_19200 19200 +#define UART16550_BAUD_38400 38400 +#define UART16550_BAUD_57600 57600 +#define UART16550_BAUD_115200 115200 + +#define UART16550_PARITY_NONE 0 +#define UART16550_PARITY_ODD 0x08 +#define UART16550_PARITY_EVEN 0x18 +#define UART16550_PARITY_MARK 0x28 +#define UART16550_PARITY_SPACE 0x38 + +#define UART16550_DATA_5BIT 0x0 +#define UART16550_DATA_6BIT 0x1 +#define UART16550_DATA_7BIT 0x2 +#define UART16550_DATA_8BIT 0x3 + +#define UART16550_STOP_1BIT 0x0 +#define UART16550_STOP_2BIT 0x4 + +/* ----------------------------------------------------- */ + +/* === CONFIG === */ + +/* [jsun] we use the second serial port for kdb */ +#define BASE OCELOT_SERIAL1_BASE +#define MAX_BAUD OCELOT_BASE_BAUD + +/* === END OF CONFIG === */ + +#define REG_OFFSET 4 + +/* register offset */ +#define OFS_RCV_BUFFER 0 +#define OFS_TRANS_HOLD 0 +#define OFS_SEND_BUFFER 0 +#define OFS_INTR_ENABLE (1*REG_OFFSET) +#define OFS_INTR_ID (2*REG_OFFSET) +#define OFS_DATA_FORMAT (3*REG_OFFSET) +#define OFS_LINE_CONTROL (3*REG_OFFSET) +#define OFS_MODEM_CONTROL (4*REG_OFFSET) +#define OFS_RS232_OUTPUT (4*REG_OFFSET) +#define OFS_LINE_STATUS (5*REG_OFFSET) +#define OFS_MODEM_STATUS (6*REG_OFFSET) +#define OFS_RS232_INPUT (6*REG_OFFSET) +#define OFS_SCRATCH_PAD (7*REG_OFFSET) + +#define OFS_DIVISOR_LSB (0*REG_OFFSET) +#define OFS_DIVISOR_MSB (1*REG_OFFSET) + + +/* memory-mapped read/write of the port */ +#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) +#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) + +void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) +{ + /* disable interrupts */ + UART16550_WRITE(OFS_INTR_ENABLE, 0); + + /* set up buad rate */ + { + uint32 divisor; + + /* set DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x80); + + /* set divisor */ + divisor = MAX_BAUD / baud; + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); + + /* clear DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x0); + } + + /* set data format */ + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); +} + +static int remoteDebugInitialized = 0; + +uint8 getDebugChar(void) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(UART16550_BAUD_38400, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); + return UART16550_READ(OFS_RCV_BUFFER); +} + + +int putDebugChar(uint8 byte) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(UART16550_BAUD_38400, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); + UART16550_WRITE(OFS_SEND_BUFFER, byte); + return 1; +} + +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_g/gt64240_dep.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,57 @@ +/*********************************************************************** + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * arch/mips/gt64240/gt64240-dep.h + * Board-dependent definitions for GT-64120 chip. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + *********************************************************************** + */ + +#ifndef _ASM_GT64240_DEP_H +#define _ASM_GT64240_DEP_H + +#include /* for KSEG1ADDR() */ +#include /* for cpu_to_le32() */ + +/* + * PCI address allocation + */ +#if 0 +#define GT_PCI_MEM_BASE (0x22000000) +#define GT_PCI_MEM_SIZE GT_DEF_PCI0_MEM0_SIZE +#define GT_PCI_IO_BASE (0x20000000) +#define GT_PCI_IO_SIZE GT_DEF_PCI0_IO_SIZE +#endif + +extern unsigned long gt64240_base; + +#define GT64240_BASE (gt64240_base) + +/* + * Because of an error/peculiarity in the Galileo chip, we need to swap the + * bytes when running bigendian. + */ + +#define GT_WRITE(ofs, data) \ + *(volatile u32 *)(GT64240_BASE+(ofs)) = cpu_to_le32(data) +#define GT_READ(ofs, data) \ + *(data) = le32_to_cpu(*(volatile u32 *)(GT64240_BASE+(ofs))) +#define GT_READ_DATA(ofs) \ + le32_to_cpu(*(volatile u32 *)(GT64240_BASE+(ofs))) + +#define GT_WRITE_16(ofs, data) \ + *(volatile u16 *)(GT64240_BASE+(ofs)) = cpu_to_le16(data) +#define GT_READ_16(ofs, data) \ + *(data) = le16_to_cpu(*(volatile u16 *)(GT64240_BASE+(ofs))) + +#define GT_WRITE_8(ofs, data) \ + *(volatile u8 *)(GT64240_BASE+(ofs)) = data +#define GT_READ_8(ofs, data) \ + *(data) = *(volatile u8 *)(GT64240_BASE+(ofs)) + +#endif /* _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_g/gt64240.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,1238 @@ +/* gt64240r.h - GT-64240 Internal registers definition file */ + +/* Copyright - Galileo technology. */ + +#ifndef __INCgt64240rh +#define __INCgt64240rh + +#define GTREG(v) (((v) & 0xff) << 24) | (((v) & 0xff00) << 8) | \ + (((v) >> 24) & 0xff) | (((v) >> 8) & 0xff00) + +#if 0 +#define GTREG_SHORT(X) (((X) << 8) | ((X) >> 8)) + +#define LONG_GTREG(X) ((l64) \ + (((X)&0x00000000000000ffULL) << 56) | \ + (((X)&0x000000000000ff00ULL) << 40) | \ + (((X)&0x0000000000ff0000ULL) << 24) | \ + (((X)&0x00000000ff000000ULL) << 8) | \ + (((X)&0x000000ff00000000ULL) >> 8) | \ + (((X)&0x0000ff0000000000ULL) >> 24) | \ + (((X)&0x00ff000000000000ULL) >> 40) | \ + (((X)&0xff00000000000000ULL) >> 56)) +#endif + +#include "gt64240_dep.h" + +/****************************************/ +/* CPU Control Registers */ +/****************************************/ + +#define CPU_CONFIGURATION 0x000 +#define CPU_MODE 0x120 +#define CPU_READ_RESPONSE_CROSSBAR_LOW 0x170 +#define CPU_READ_RESPONSE_CROSSBAR_HIGH 0x178 + +/****************************************/ +/* Processor Address Space */ +/****************************************/ + +/* Sdram's BAR'S */ +#define SCS_0_LOW_DECODE_ADDRESS 0x008 +#define SCS_0_HIGH_DECODE_ADDRESS 0x010 +#define SCS_1_LOW_DECODE_ADDRESS 0x208 +#define SCS_1_HIGH_DECODE_ADDRESS 0x210 +#define SCS_2_LOW_DECODE_ADDRESS 0x018 +#define SCS_2_HIGH_DECODE_ADDRESS 0x020 +#define SCS_3_LOW_DECODE_ADDRESS 0x218 +#define SCS_3_HIGH_DECODE_ADDRESS 0x220 +/* Devices BAR'S */ +#define CS_0_LOW_DECODE_ADDRESS 0x028 +#define CS_0_HIGH_DECODE_ADDRESS 0x030 +#define CS_1_LOW_DECODE_ADDRESS 0x228 +#define CS_1_HIGH_DECODE_ADDRESS 0x230 +#define CS_2_LOW_DECODE_ADDRESS 0x248 +#define CS_2_HIGH_DECODE_ADDRESS 0x250 +#define CS_3_LOW_DECODE_ADDRESS 0x038 +#define CS_3_HIGH_DECODE_ADDRESS 0x040 +#define BOOTCS_LOW_DECODE_ADDRESS 0x238 +#define BOOTCS_HIGH_DECODE_ADDRESS 0x240 + +#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048 +#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050 +#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058 +#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060 +#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080 +#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088 +#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258 +#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260 +#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280 +#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288 + +#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090 +#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098 +#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0 +#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8 +#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0 +#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8 +#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0 +#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8 +#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0 +#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8 + +#define INTERNAL_SPACE_DECODE 0x068 + +#define CPU_0_LOW_DECODE_ADDRESS 0x290 +#define CPU_0_HIGH_DECODE_ADDRESS 0x298 +#define CPU_1_LOW_DECODE_ADDRESS 0x2c0 +#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8 + +#define PCI_0I_O_ADDRESS_REMAP 0x0f0 +#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8 +#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320 +#define PCI_0MEMORY1_ADDRESS_REMAP 0x100 +#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328 +#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8 +#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330 +#define PCI_0MEMORY3_ADDRESS_REMAP 0x300 +#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338 + +#define PCI_1I_O_ADDRESS_REMAP 0x108 +#define PCI_1MEMORY0_ADDRESS_REMAP 0x110 +#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340 +#define PCI_1MEMORY1_ADDRESS_REMAP 0x118 +#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348 +#define PCI_1MEMORY2_ADDRESS_REMAP 0x310 +#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350 +#define PCI_1MEMORY3_ADDRESS_REMAP 0x318 +#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358 + +/****************************************/ +/* CPU Sync Barrier */ +/****************************************/ + +#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0 +#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8 + + +/****************************************/ +/* CPU Access Protect */ +/****************************************/ + +#define CPU_LOW_PROTECT_ADDRESS_0 0X180 +#define CPU_HIGH_PROTECT_ADDRESS_0 0X188 +#define CPU_LOW_PROTECT_ADDRESS_1 0X190 +#define CPU_HIGH_PROTECT_ADDRESS_1 0X198 +#define CPU_LOW_PROTECT_ADDRESS_2 0X1a0 +#define CPU_HIGH_PROTECT_ADDRESS_2 0X1a8 +#define CPU_LOW_PROTECT_ADDRESS_3 0X1b0 +#define CPU_HIGH_PROTECT_ADDRESS_3 0X1b8 +#define CPU_LOW_PROTECT_ADDRESS_4 0X1c0 +#define CPU_HIGH_PROTECT_ADDRESS_4 0X1c8 +#define CPU_LOW_PROTECT_ADDRESS_5 0X1d0 +#define CPU_HIGH_PROTECT_ADDRESS_5 0X1d8 +#define CPU_LOW_PROTECT_ADDRESS_6 0X1e0 +#define CPU_HIGH_PROTECT_ADDRESS_6 0X1e8 +#define CPU_LOW_PROTECT_ADDRESS_7 0X1f0 +#define CPU_HIGH_PROTECT_ADDRESS_7 0X1f8 + + +/****************************************/ +/* Snoop Control */ +/****************************************/ + +#define SNOOP_BASE_ADDRESS_0 0x380 +#define SNOOP_TOP_ADDRESS_0 0x388 +#define SNOOP_BASE_ADDRESS_1 0x390 +#define SNOOP_TOP_ADDRESS_1 0x398 +#define SNOOP_BASE_ADDRESS_2 0x3a0 +#define SNOOP_TOP_ADDRESS_2 0x3a8 +#define SNOOP_BASE_ADDRESS_3 0x3b0 +#define SNOOP_TOP_ADDRESS_3 0x3b8 + +/****************************************/ +/* CPU Error Report */ +/****************************************/ + +#define CPU_ERROR_ADDRESS_LOW 0x070 +#define CPU_ERROR_ADDRESS_HIGH 0x078 +#define CPU_ERROR_DATA_LOW 0x128 +#define CPU_ERROR_DATA_HIGH 0x130 +#define CPU_ERROR_PARITY 0x138 +#define CPU_ERROR_CAUSE 0x140 +#define CPU_ERROR_MASK 0x148 + +/****************************************/ +/* Pslave Debug */ +/****************************************/ + +#define X_0_ADDRESS 0x360 +#define X_0_COMMAND_ID 0x368 +#define X_1_ADDRESS 0x370 +#define X_1_COMMAND_ID 0x378 +#define WRITE_DATA_LOW 0x3c0 +#define WRITE_DATA_HIGH 0x3c8 +#define WRITE_BYTE_ENABLE 0X3e0 +#define READ_DATA_LOW 0x3d0 +#define READ_DATA_HIGH 0x3d8 +#define READ_ID 0x3e8 + + +/****************************************/ +/* SDRAM and Device Address Space */ +/****************************************/ + + +/****************************************/ +/* SDRAM Configuration */ +/****************************************/ + +#define SDRAM_CONFIGURATION 0x448 +#define SDRAM_OPERATION_MODE 0x474 +#define SDRAM_ADDRESS_DECODE 0x47C +#define SDRAM_TIMING_PARAMETERS 0x4b4 +#define SDRAM_UMA_CONTROL 0x4a4 +#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8 +#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac +#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0 + + +/****************************************/ +/* SDRAM Parameters */ +/****************************************/ + +#define SDRAM_BANK0PARAMETERS 0x44C +#define SDRAM_BANK1PARAMETERS 0x450 +#define SDRAM_BANK2PARAMETERS 0x454 +#define SDRAM_BANK3PARAMETERS 0x458 + + +/****************************************/ +/* SDRAM Error Report */ +/****************************************/ + +#define SDRAM_ERROR_DATA_LOW 0x484 +#define SDRAM_ERROR_DATA_HIGH 0x480 +#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490 +#define SDRAM_RECEIVED_ECC 0x488 +#define SDRAM_CALCULATED_ECC 0x48c +#define SDRAM_ECC_CONTROL 0x494 +#define SDRAM_ECC_ERROR_COUNTER 0x498 + + +/****************************************/ +/* SDunit Debug (for internal use) */ +/****************************************/ + +#define X0_ADDRESS 0x500 +#define X0_COMMAND_AND_ID 0x504 +#define X0_WRITE_DATA_LOW 0x508 +#define X0_WRITE_DATA_HIGH 0x50c +#define X0_WRITE_BYTE_ENABLE 0x518 +#define X0_READ_DATA_LOW 0x510 +#define X0_READ_DATA_HIGH 0x514 +#define X0_READ_ID 0x51c +#define X1_ADDRESS 0x520 +#define X1_COMMAND_AND_ID 0x524 +#define X1_WRITE_DATA_LOW 0x528 +#define X1_WRITE_DATA_HIGH 0x52c +#define X1_WRITE_BYTE_ENABLE 0x538 +#define X1_READ_DATA_LOW 0x530 +#define X1_READ_DATA_HIGH 0x534 +#define X1_READ_ID 0x53c +#define X0_SNOOP_ADDRESS 0x540 +#define X0_SNOOP_COMMAND 0x544 +#define X1_SNOOP_ADDRESS 0x548 +#define X1_SNOOP_COMMAND 0x54c + + +/****************************************/ +/* Device Parameters */ +/****************************************/ + +#define DEVICE_BANK0PARAMETERS 0x45c +#define DEVICE_BANK1PARAMETERS 0x460 +#define DEVICE_BANK2PARAMETERS 0x464 +#define DEVICE_BANK3PARAMETERS 0x468 +#define DEVICE_BOOT_BANK_PARAMETERS 0x46c +#define DEVICE_CONTROL 0x4c0 +#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8 +#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc +#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4 + + +/****************************************/ +/* Device Interrupt */ +/****************************************/ + +#define DEVICE_INTERRUPT_CAUSE 0x4d0 +#define DEVICE_INTERRUPT_MASK 0x4d4 +#define DEVICE_ERROR_ADDRESS 0x4d8 + +/****************************************/ +/* DMA Record */ +/****************************************/ + +#define CHANNEL0_DMA_BYTE_COUNT 0x800 +#define CHANNEL1_DMA_BYTE_COUNT 0x804 +#define CHANNEL2_DMA_BYTE_COUNT 0x808 +#define CHANNEL3_DMA_BYTE_COUNT 0x80C +#define CHANNEL4_DMA_BYTE_COUNT 0x900 +#define CHANNEL5_DMA_BYTE_COUNT 0x904 +#define CHANNEL6_DMA_BYTE_COUNT 0x908 +#define CHANNEL7_DMA_BYTE_COUNT 0x90C +#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810 +#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814 +#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818 +#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C +#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910 +#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914 +#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918 +#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C +#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820 +#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824 +#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828 +#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C +#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920 +#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924 +#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928 +#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C +#define CHANNEL0NEXT_RECORD_POINTER 0x830 +#define CHANNEL1NEXT_RECORD_POINTER 0x834 +#define CHANNEL2NEXT_RECORD_POINTER 0x838 +#define CHANNEL3NEXT_RECORD_POINTER 0x83C +#define CHANNEL4NEXT_RECORD_POINTER 0x930 +#define CHANNEL5NEXT_RECORD_POINTER 0x934 +#define CHANNEL6NEXT_RECORD_POINTER 0x938 +#define CHANNEL7NEXT_RECORD_POINTER 0x93C +#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870 +#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874 +#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878 +#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C +#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970 +#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974 +#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978 +#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C +#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890 +#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894 +#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898 +#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c +#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990 +#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994 +#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998 +#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c +#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0 +#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4 +#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8 +#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac +#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0 +#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4 +#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8 +#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac +#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0 +#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4 +#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8 +#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc +#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0 +#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4 +#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8 +#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc + +/****************************************/ +/* DMA Channel Control */ +/****************************************/ + +#define CHANNEL0CONTROL 0x840 +#define CHANNEL0CONTROL_HIGH 0x880 + +#define CHANNEL1CONTROL 0x844 +#define CHANNEL1CONTROL_HIGH 0x884 + +#define CHANNEL2CONTROL 0x848 +#define CHANNEL2CONTROL_HIGH 0x888 + +#define CHANNEL3CONTROL 0x84C +#define CHANNEL3CONTROL_HIGH 0x88C + +#define CHANNEL4CONTROL 0x940 +#define CHANNEL4CONTROL_HIGH 0x980 + +#define CHANNEL5CONTROL 0x944 +#define CHANNEL5CONTROL_HIGH 0x984 + +#define CHANNEL6CONTROL 0x948 +#define CHANNEL6CONTROL_HIGH 0x988 + +#define CHANNEL7CONTROL 0x94C +#define CHANNEL7CONTROL_HIGH 0x98C + + +/****************************************/ +/* DMA Arbiter */ +/****************************************/ + +#define ARBITER_CONTROL_0_3 0x860 +#define ARBITER_CONTROL_4_7 0x960 + + +/****************************************/ +/* DMA Interrupt */ +/****************************************/ + +#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0 +#define CHANELS0_3_INTERRUPT_MASK 0x8c4 +#define CHANELS0_3_ERROR_ADDRESS 0x8c8 +#define CHANELS0_3_ERROR_SELECT 0x8cc +#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0 +#define CHANELS4_7_INTERRUPT_MASK 0x9c4 +#define CHANELS4_7_ERROR_ADDRESS 0x9c8 +#define CHANELS4_7_ERROR_SELECT 0x9cc + + +/****************************************/ +/* DMA Debug (for internal use) */ +/****************************************/ + +#define DMA_X0_ADDRESS 0x8e0 +#define DMA_X0_COMMAND_AND_ID 0x8e4 +#define DMA_X0_WRITE_DATA_LOW 0x8e8 +#define DMA_X0_WRITE_DATA_HIGH 0x8ec +#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8 +#define DMA_X0_READ_DATA_LOW 0x8f0 +#define DMA_X0_READ_DATA_HIGH 0x8f4 +#define DMA_X0_READ_ID 0x8fc +#define DMA_X1_ADDRESS 0x9e0 +#define DMA_X1_COMMAND_AND_ID 0x9e4 +#define DMA_X1_WRITE_DATA_LOW 0x9e8 +#define DMA_X1_WRITE_DATA_HIGH 0x9ec +#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8 +#define DMA_X1_READ_DATA_LOW 0x9f0 +#define DMA_X1_READ_DATA_HIGH 0x9f4 +#define DMA_X1_READ_ID 0x9fc + +/****************************************/ +/* Timer_Counter */ +/****************************************/ + +#define TIMER_COUNTER0 0x850 +#define TIMER_COUNTER1 0x854 +#define TIMER_COUNTER2 0x858 +#define TIMER_COUNTER3 0x85C +#define TIMER_COUNTER_0_3_CONTROL 0x864 +#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 +#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c +#define TIMER_COUNTER4 0x950 +#define TIMER_COUNTER5 0x954 +#define TIMER_COUNTER6 0x958 +#define TIMER_COUNTER7 0x95C +#define TIMER_COUNTER_4_7_CONTROL 0x964 +#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968 +#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c + +/****************************************/ +/* PCI Slave Address Decoding */ +/****************************************/ + +#define PCI_0SCS_0_BANK_SIZE 0xc08 +#define PCI_1SCS_0_BANK_SIZE 0xc88 +#define PCI_0SCS_1_BANK_SIZE 0xd08 +#define PCI_1SCS_1_BANK_SIZE 0xd88 +#define PCI_0SCS_2_BANK_SIZE 0xc0c +#define PCI_1SCS_2_BANK_SIZE 0xc8c +#define PCI_0SCS_3_BANK_SIZE 0xd0c +#define PCI_1SCS_3_BANK_SIZE 0xd8c +#define PCI_0CS_0_BANK_SIZE 0xc10 +#define PCI_1CS_0_BANK_SIZE 0xc90 +#define PCI_0CS_1_BANK_SIZE 0xd10 +#define PCI_1CS_1_BANK_SIZE 0xd90 +#define PCI_0CS_2_BANK_SIZE 0xd18 +#define PCI_1CS_2_BANK_SIZE 0xd98 +#define PCI_0CS_3_BANK_SIZE 0xc14 +#define PCI_1CS_3_BANK_SIZE 0xc94 +#define PCI_0CS_BOOT_BANK_SIZE 0xd14 +#define PCI_1CS_BOOT_BANK_SIZE 0xd94 +#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c +#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c +#define PCI_0P2P_MEM1_BAR_SIZE 0xd20 +#define PCI_1P2P_MEM1_BAR_SIZE 0xda0 +#define PCI_0P2P_I_O_BAR_SIZE 0xd24 +#define PCI_1P2P_I_O_BAR_SIZE 0xda4 +#define PCI_0CPU_BAR_SIZE 0xd28 +#define PCI_1CPU_BAR_SIZE 0xda8 +#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00 +#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80 +#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04 +#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84 +#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08 +#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88 +#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c +#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c +#define PCI_0DAC_CS_0_BANK_SIZE 0xe10 +#define PCI_1DAC_CS_0_BANK_SIZE 0xe90 +#define PCI_0DAC_CS_1_BANK_SIZE 0xe14 +#define PCI_1DAC_CS_1_BANK_SIZE 0xe94 +#define PCI_0DAC_CS_2_BANK_SIZE 0xe18 +#define PCI_1DAC_CS_2_BANK_SIZE 0xe98 +#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c +#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c +#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20 +#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0 +#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24 +#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4 +#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28 +#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8 +#define PCI_0DAC_CPU_BAR_SIZE 0xe2c +#define PCI_1DAC_CPU_BAR_SIZE 0xeac +#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c +#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac +#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c +#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc +#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48 +#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8 +#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48 +#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8 +#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c +#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc +#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c +#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc +#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50 +#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0 +#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50 +#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0 +#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58 +#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8 +#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54 +#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4 +#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54 +#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4 +#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c +#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc +#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60 +#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0 +#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64 +#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4 +#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68 +#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8 +#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c +#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec +#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70 +#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0 +#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00 +#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0 +#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04 +#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84 +#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08 +#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88 +#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c +#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c +#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10 +#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90 +#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14 +#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94 +#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18 +#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98 +#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c +#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c +#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20 +#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0 +#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24 +#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4 +#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28 +#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8 +#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c +#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac +#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30 +#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0 +#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34 +#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4 +#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38 +#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8 +#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c +#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc + +/****************************************/ +/* PCI Control */ +/****************************************/ + +#define PCI_0COMMAND 0xc00 +#define PCI_1COMMAND 0xc80 +#define PCI_0MODE 0xd00 +#define PCI_1MODE 0xd80 +#define PCI_0TIMEOUT_RETRY 0xc04 +#define PCI_1TIMEOUT_RETRY 0xc84 +#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04 +#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84 +#define MSI_0TRIGGER_TIMER 0xc38 +#define MSI_1TRIGGER_TIMER 0xcb8 +#define PCI_0ARBITER_CONTROL 0x1d00 +#define PCI_1ARBITER_CONTROL 0x1d80 +/* changing untill here */ +#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08 +#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c +#define PCI_0CROSS_BAR_TIMEOUT 0x1d04 +#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18 +#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c +#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10 +#define PCI_0P2P_CONFIGURATION 0x1d14 +#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00 +#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04 +#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08 +#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0c1e10 +#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14 +#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18 +#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0c1e20 +#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24 +#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28 +#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0c1e30 +#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34 +#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38 +#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0c1e40 +#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44 +#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48 +#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0c1e50 +#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54 +#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58 +#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0c1e60 +#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64 +#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68 +#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0c1e70 +#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74 +#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78 +#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88 +#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c +#define PCI_1CROSS_BAR_TIMEOUT 0x1d84 +#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98 +#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c +#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90 +#define PCI_1P2P_CONFIGURATION 0x1d94 +#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80 +#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84 +#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88 +#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0c1e90 +#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94 +#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98 +#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0c1ea0 +#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 +#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8 +#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0c1eb0 +#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 +#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8 +#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0c1ec0 +#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 +#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8 +#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0c1ed0 +#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 +#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8 +#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0c1ee0 +#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4 +#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8 +#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0c1ef0 +#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4 +#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8 + +/****************************************/ +/* PCI Snoop Control */ +/****************************************/ + +#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00 +#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04 +#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08 +#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10 +#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14 +#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18 +#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20 +#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24 +#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28 +#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30 +#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34 +#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38 +#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80 +#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84 +#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88 +#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90 +#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94 +#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98 +#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0 +#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4 +#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8 +#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0 +#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4 +#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8 + +/****************************************/ +/* PCI Configuration Address */ +/****************************************/ + +#define PCI_0CONFIGURATION_ADDRESS 0xcf8 +#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc +#define PCI_1CONFIGURATION_ADDRESS 0xc78 +#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c +#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34 +#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4 + +/****************************************/ +/* PCI Error Report */ +/****************************************/ + +#define PCI_0SERR_MASK 0xc28 +#define PCI_0ERROR_ADDRESS_LOW 0x1d40 +#define PCI_0ERROR_ADDRESS_HIGH 0x1d44 +#define PCI_0ERROR_DATA_LOW 0x1d48 +#define PCI_0ERROR_DATA_HIGH 0x1d4c +#define PCI_0ERROR_COMMAND 0x1d50 +#define PCI_0ERROR_CAUSE 0x1d58 +#define PCI_0ERROR_MASK 0x1d5c + +#define PCI_1SERR_MASK 0xca8 +#define PCI_1ERROR_ADDRESS_LOW 0x1dc0 +#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4 +#define PCI_1ERROR_DATA_LOW 0x1dc8 +#define PCI_1ERROR_DATA_HIGH 0x1dcc +#define PCI_1ERROR_COMMAND 0x1dd0 +#define PCI_1ERROR_CAUSE 0x1dd8 +#define PCI_1ERROR_MASK 0x1ddc + + +/****************************************/ +/* Lslave Debug (for internal use) */ +/****************************************/ + +#define L_SLAVE_X0_ADDRESS 0x1d20 +#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24 +#define L_SLAVE_X1_ADDRESS 0x1d28 +#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c +#define L_SLAVE_WRITE_DATA_LOW 0x1d30 +#define L_SLAVE_WRITE_DATA_HIGH 0x1d34 +#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60 +#define L_SLAVE_READ_DATA_LOW 0x1d38 +#define L_SLAVE_READ_DATA_HIGH 0x1d3c +#define L_SLAVE_READ_ID 0x1d64 + +/****************************************/ +/* PCI Configuration Function 0 */ +/****************************************/ + +#define PCI_DEVICE_AND_VENDOR_ID 0x000 +#define PCI_STATUS_AND_COMMAND 0x004 +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C +#define PCI_SCS_0_BASE_ADDRESS 0x010 +#define PCI_SCS_1_BASE_ADDRESS 0x014 +#define PCI_SCS_2_BASE_ADDRESS 0x018 +#define PCI_SCS_3_BASE_ADDRESS 0x01C +#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 +#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 +#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C +#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 +#define PCI_CAPABILTY_LIST_POINTER 0x034 +#define PCI_INTERRUPT_PIN_AND_LINE 0x03C +#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 +#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 +#define PCI_VPD_ADDRESS 0x048 +#define PCI_VPD_DATA 0X04c +#define PCI_MSI_MESSAGE_CONTROL 0x050 +#define PCI_MSI_MESSAGE_ADDRESS 0x054 +#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 +#define PCI_MSI_MESSAGE_DATA 0x05c +#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 + +/****************************************/ +/* PCI Configuration Function 1 */ +/****************************************/ + +#define PCI_CS_0_BASE_ADDRESS 0x110 +#define PCI_CS_1_BASE_ADDRESS 0x114 +#define PCI_CS_2_BASE_ADDRESS 0x118 +#define PCI_CS_3_BASE_ADDRESS 0x11c +#define PCI_BOOTCS_BASE_ADDRESS 0x120 + +/****************************************/ +/* PCI Configuration Function 2 */ +/****************************************/ + +#define PCI_P2P_MEM0_BASE_ADDRESS 0x210 +#define PCI_P2P_MEM1_BASE_ADDRESS 0x214 +#define PCI_P2P_I_O_BASE_ADDRESS 0x218 +#define PCI_CPU_BASE_ADDRESS 0x21c + +/****************************************/ +/* PCI Configuration Function 4 */ +/****************************************/ + +#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 +#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 +#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 +#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c +#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 +#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 + + +/****************************************/ +/* PCI Configuration Function 5 */ +/****************************************/ + +#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 +#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 +#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 +#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c +#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 +#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 + + +/****************************************/ +/* PCI Configuration Function 6 */ +/****************************************/ + +#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 +#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 +#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 +#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c +#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 +#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 + +/****************************************/ +/* PCI Configuration Function 7 */ +/****************************************/ + +#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 +#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 +#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 +#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c +#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 +#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 + +/****************************************/ +/* Interrupts */ +/****************************************/ + +#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18 +#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68 +#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c +#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c +#define CPU_SELECT_CAUSE_REGISTER 0xc70 +#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24 +#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64 +#define PCI_0SELECT_CAUSE 0xc74 +#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4 +#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4 +#define PCI_1SELECT_CAUSE 0xcf4 +#define CPU_INT_0_MASK 0xe60 +#define CPU_INT_1_MASK 0xe64 +#define CPU_INT_2_MASK 0xe68 +#define CPU_INT_3_MASK 0xe6c + +/****************************************/ +/* I20 Support registers */ +/****************************************/ + +#define INBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x010 +#define INBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x014 +#define OUTBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x018 +#define OUTBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x01C +#define INBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x020 +#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x024 +#define INBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x028 +#define OUTBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x02C +#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x030 +#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x034 +#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x040 +#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x044 +#define QUEUE_CONTROL_REGISTER_PCI0_SIDE 0x050 +#define QUEUE_BASE_ADDRESS_REGISTER_PCI0_SIDE 0x054 +#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x060 +#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x064 +#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x068 +#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x06C +#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x070 +#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x074 +#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x0F8 +#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x0FC + +#define INBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x090 +#define INBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x094 +#define OUTBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x098 +#define OUTBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x09C +#define INBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0A0 +#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0A4 +#define INBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0A8 +#define OUTBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0AC +#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0B0 +#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0B4 +#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C0 +#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C4 +#define QUEUE_CONTROL_REGISTER_PCI1_SIDE 0x0D0 +#define QUEUE_BASE_ADDRESS_REGISTER_PCI1_SIDE 0x0D4 +#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E0 +#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0E4 +#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E8 +#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0EC +#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0F0 +#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0F4 +#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x078 +#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x07C + +#define INBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C10 +#define INBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C14 +#define OUTBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C18 +#define OUTBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C1C +#define INBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C20 +#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C24 +#define INBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C28 +#define OUTBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C2C +#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C30 +#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C34 +#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C40 +#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C44 +#define QUEUE_CONTROL_REGISTER_CPU0_SIDE 0X1C50 +#define QUEUE_BASE_ADDRESS_REGISTER_CPU0_SIDE 0X1C54 +#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C60 +#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C64 +#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C68 +#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C6C +#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C70 +#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C74 +#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1CF8 +#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1CFC + +#define INBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C90 +#define INBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C94 +#define OUTBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C98 +#define OUTBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C9C +#define INBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CA0 +#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CA4 +#define INBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CA8 +#define OUTBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CAC +#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CB0 +#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CB4 +#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC0 +#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC4 +#define QUEUE_CONTROL_REGISTER_CPU1_SIDE 0X1CD0 +#define QUEUE_BASE_ADDRESS_REGISTER_CPU1_SIDE 0X1CD4 +#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE0 +#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CE4 +#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE8 +#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CEC +#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CF0 +#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CF4 +#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1C78 +#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1C7C + +/****************************************/ +/* Communication Unit Registers */ +/****************************************/ + +#define ETHERNET_0_ADDRESS_CONTROL_LOW +#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204 +#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208 +#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c +#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210 +#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214 +#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218 +#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220 +#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224 +#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228 +#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c +#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230 +#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234 +#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238 +#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240 +#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244 +#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248 +#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c +#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250 +#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254 +#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258 +#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280 +#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284 +#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288 +#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c +#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290 +#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294 +#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2a0 +#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2a4 +#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2a8 +#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2ac +#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b0 +#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b4 +#define MPSC_2_ADDRESS_CONTROL_LOW 0xf2c0 +#define MPSC_2_ADDRESS_CONTROL_HIGH 0xf2c4 +#define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8 +#define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc +#define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0 +#define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4 +#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320 +#define SERIAL_INIT_LAST_DATA 0xf324 +#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328 +#define COMM_UNIT_ARBITER_CONTROL 0xf300 +#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304 +#define COMM_UNIT_INTERRUPT_CAUSE 0xf310 +#define COMM_UNIT_INTERRUPT_MASK 0xf314 +#define COMM_UNIT_ERROR_ADDRESS 0xf314 + +/****************************************/ +/* Cunit Debug (for internal use) */ +/****************************************/ + +#define CUNIT_ADDRESS 0xf340 +#define CUNIT_COMMAND_AND_ID 0xf344 +#define CUNIT_WRITE_DATA_LOW 0xf348 +#define CUNIT_WRITE_DATA_HIGH 0xf34c +#define CUNIT_WRITE_BYTE_ENABLE 0xf358 +#define CUNIT_READ_DATA_LOW 0xf350 +#define CUNIT_READ_DATA_HIGH 0xf354 +#define CUNIT_READ_ID 0xf35c + +/****************************************/ +/* Fast Ethernet Unit Registers */ +/****************************************/ + +/* Ethernet */ + +#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000 +#define ETHERNET_SMI_REGISTER 0x2010 + +/* Ethernet 0 */ + +#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400 +#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408 +#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410 +#define ETHERNET0_PORT_STATUS_REGISTER 0x2418 +#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420 +#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428 +#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430 +#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438 +#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440 +#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448 +#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450 +#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458 +#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480 +#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484 +#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488 +#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c +#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0 +#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4 +#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8 +#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac +#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0 +#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4 +#define ETHERNET0_MIB_COUNTER_BASE 0x2500 + +/* Ethernet 1 */ + +#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800 +#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808 +#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810 +#define ETHERNET1_PORT_STATUS_REGISTER 0x2818 +#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820 +#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828 +#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830 +#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838 +#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840 +#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848 +#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850 +#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858 +#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880 +#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884 +#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888 +#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c +#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0 +#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4 +#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8 +#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac +#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0 +#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4 +#define ETHERNET1_MIB_COUNTER_BASE 0x2900 + +/* Ethernet 2 */ + +#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00 +#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08 +#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10 +#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18 +#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20 +#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28 +#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30 +#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38 +#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40 +#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48 +#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50 +#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58 +#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80 +#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84 +#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88 +#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c +#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0 +#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4 +#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8 +#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac +#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0 +#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4 +#define ETHERNET2_MIB_COUNTER_BASE 0x2d00 + +/****************************************/ +/* SDMA Registers */ +/****************************************/ + +#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0 +#define CHANNEL0_CONFIGURATION_REGISTER 0x4000 +#define CHANNEL0_COMMAND_REGISTER 0x4008 +#define CHANNEL0_RX_CMD_STATUS 0x4800 +#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804 +#define CHANNEL0_RX_BUFFER_POINTER 0x4808 +#define CHANNEL0_RX_NEXT_POINTER 0x480c +#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810 +#define CHANNEL0_TX_CMD_STATUS 0x4C00 +#define CHANNEL0_TX_PACKET_SIZE 0x4C04 +#define CHANNEL0_TX_BUFFER_POINTER 0x4C08 +#define CHANNEL0_TX_NEXT_POINTER 0x4C0c +#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10 +#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14 +#define CHANNEL1_CONFIGURATION_REGISTER 0x6000 +#define CHANNEL1_COMMAND_REGISTER 0x6008 +#define CHANNEL1_RX_CMD_STATUS 0x6800 +#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x6804 +#define CHANNEL1_RX_BUFFER_POINTER 0x6808 +#define CHANNEL1_RX_NEXT_POINTER 0x680c +#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 +#define CHANNEL1_TX_CMD_STATUS 0x6C00 +#define CHANNEL1_TX_PACKET_SIZE 0x6C04 +#define CHANNEL1_TX_BUFFER_POINTER 0x6C08 +#define CHANNEL1_TX_NEXT_POINTER 0x6C0c +#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 +#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10 +#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x6c14 + +/* SDMA Interrupt */ + +#define SDMA_CAUSE 0xb820 +#define SDMA_MASK 0xb8a0 + + +/****************************************/ +/* Baude Rate Generators Registers */ +/****************************************/ + +/* BRG 0 */ + +#define BRG0_CONFIGURATION_REGISTER 0xb200 +#define BRG0_BAUDE_TUNING_REGISTER 0xb204 + +/* BRG 1 */ + +#define BRG1_CONFIGURATION_REGISTER 0xb208 +#define BRG1_BAUDE_TUNING_REGISTER 0xb20c + +/* BRG 2 */ + +#define BRG2_CONFIGURATION_REGISTER 0xb210 +#define BRG2_BAUDE_TUNING_REGISTER 0xb214 + +/* BRG Interrupts */ + +#define BRG_CAUSE_REGISTER 0xb834 +#define BRG_MASK_REGISTER 0xb8b4 + +/* MISC */ + +#define MAIN_ROUTING_REGISTER 0xb400 +#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404 +#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408 +#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c +#define WATCHDOG_CONFIGURATION_REGISTER 0xb410 +#define WATCHDOG_VALUE_REGISTER 0xb414 + + +/****************************************/ +/* Flex TDM Registers */ +/****************************************/ + +/* FTDM Port */ + +#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800 +#define FLEXTDM_RECEIVE_READ_POINTER 0xa804 +#define FLEXTDM_CONFIGURATION_REGISTER 0xa808 +#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c +#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810 +#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814 +#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818 + +/* FTDM Interrupts */ + +#define FTDM_CAUSE_REGISTER 0xb830 +#define FTDM_MASK_REGISTER 0xb8b0 + + +/****************************************/ +/* GPP Interface Registers */ +/****************************************/ + +#define GPP_IO_CONTROL 0xf100 +#define GPP_LEVEL_CONTROL 0xf110 +#define GPP_VALUE 0xf104 +#define GPP_INTERRUPT_CAUSE 0xf108 +#define GPP_INTERRUPT_MASK 0xf10c + +#define MPP_CONTROL0 0xf000 +#define MPP_CONTROL1 0xf004 +#define MPP_CONTROL2 0xf008 +#define MPP_CONTROL3 0xf00c +#define DEBUG_PORT_MULTIPLEX 0xf014 +#define SERIAL_PORT_MULTIPLEX 0xf010 + +/****************************************/ +/* I2C Registers */ +/****************************************/ + +#define I2C_SLAVE_ADDRESS 0xc000 +#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040 +#define I2C_DATA 0xc004 +#define I2C_CONTROL 0xc008 +#define I2C_STATUS_BAUDE_RATE 0xc00C +#define I2C_SOFT_RESET 0xc01c + +/****************************************/ +/* MPSC Registers */ +/****************************************/ + +/* MPSC0 */ + +#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000 +#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004 +#define MPSC0_PROTOCOL_CONFIGURATION 0x8008 +#define CHANNEL0_REGISTER1 0x800c +#define CHANNEL0_REGISTER2 0x8010 +#define CHANNEL0_REGISTER3 0x8014 +#define CHANNEL0_REGISTER4 0x8018 +#define CHANNEL0_REGISTER5 0x801c +#define CHANNEL0_REGISTER6 0x8020 +#define CHANNEL0_REGISTER7 0x8024 +#define CHANNEL0_REGISTER8 0x8028 +#define CHANNEL0_REGISTER9 0x802c +#define CHANNEL0_REGISTER10 0x8030 +#define CHANNEL0_REGISTER11 0x8034 + +/* MPSC1 */ + +#define MPSC1_MAIN_CONFIGURATION_LOW 0x9000 +#define MPSC1_MAIN_CONFIGURATION_HIGH 0x9004 +#define MPSC1_PROTOCOL_CONFIGURATION 0x9008 +#define CHANNEL1_REGISTER1 0x900c +#define CHANNEL1_REGISTER2 0x9010 +#define CHANNEL1_REGISTER3 0x9014 +#define CHANNEL1_REGISTER4 0x9018 +#define CHANNEL1_REGISTER5 0x901c +#define CHANNEL1_REGISTER6 0x9020 +#define CHANNEL1_REGISTER7 0x9024 +#define CHANNEL1_REGISTER8 0x9028 +#define CHANNEL1_REGISTER9 0x902c +#define CHANNEL1_REGISTER10 0x9030 +#define CHANNEL1_REGISTER11 0x9034 + +/* MPSCs Interupts */ + +#define MPSC0_CAUSE 0xb804 +#define MPSC0_MASK 0xb884 +#define MPSC1_CAUSE 0xb80c +#define MPSC1_MASK 0xb88c + +#endif /* __INCgt64240rh */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_g/gt-irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,294 @@ +/* + * + * Copyright 2002 Momentum Computer + * Author: mdharm@momenco.com + * + * arch/mips/momentum/ocelot_g/gt_irq.c + * Interrupt routines for gt64240. Currently it only handles timer irq. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "gt64240.h" + +unsigned long bus_clock; + +/* + * These are interrupt handlers for the GT on-chip interrupts. They + * all come in to the MIPS on a single interrupt line, and have to + * be handled and ack'ed differently than other MIPS interrupts. + */ + +#if CURRENTLY_UNUSED + +struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH]; +void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr); + +/* + * Hooks IRQ handler to the system. When the system is interrupted + * the interrupt service routine is called. + * + * Inputs : + * int_cause - The interrupt cause number. In EVB64120 two parameters + * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. + * bit_num - Indicates which bit number in the cause register + * isr_ptr - Pointer to the interrupt service routine + */ +void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr) +{ + irq_handlers[int_cause][bit_num].routine = isr_ptr; +} + + +/* + * Enables the IRQ on Galileo Chip + * + * Inputs : + * int_cause - The interrupt cause number. In EVB64120 two parameters + * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. + * bit_num - Indicates which bit number in the cause register + * + * Outputs : + * 1 if succesful, 0 if failure + */ +int enable_galileo_irq(int int_cause, int bit_num) +{ + if (int_cause == INT_CAUSE_MAIN) + SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num)); + else if (int_cause == INT_CAUSE_HIGH) + SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER, + (1 << bit_num)); + else + return 0; + + return 1; +} + +/* + * Disables the IRQ on Galileo Chip + * + * Inputs : + * int_cause - The interrupt cause number. In EVB64120 two parameters + * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. + * bit_num - Indicates which bit number in the cause register + * + * Outputs : + * 1 if succesful, 0 if failure + */ +int disable_galileo_irq(int int_cause, int bit_num) +{ + if (int_cause == INT_CAUSE_MAIN) + RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, + (1 << bit_num)); + else if (int_cause == INT_CAUSE_HIGH) + RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER, + (1 << bit_num)); + else + return 0; + return 1; +} +#endif /* UNUSED */ + +/* + * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#. + * + * We route the timer interrupt to P0_INT# (IRQ 6), and that's all this + * routine can handle, for now. + * + * In the future, we'll route more interrupts to this pin, and that's why + * we keep this particular structure in the function. + */ + +static void gt64240_p0int_irq(int irq, void *dev_id, struct pt_regs *regs) +{ + uint32_t irq_src, irq_src_mask; + int handled; + + /* get the low interrupt cause register */ + GT_READ(LOW_INTERRUPT_CAUSE_REGISTER, &irq_src); + + /* get the mask register for this pin */ + GT_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, &irq_src_mask); + + /* mask off only the interrupts we're interested in */ + irq_src = irq_src & irq_src_mask; + + handled = 0; + + /* Check for timer interrupt */ + if (irq_src & 0x00000100) { + handled = 1; + irq_src &= ~0x00000100; + + /* Clear any pending cause bits */ + GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); + + /* handle the timer call */ + do_timer(regs); + } + + if (irq_src) { + printk(KERN_INFO + "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n", + irq_src); + } +} + +/* + * Interrupt handler for interrupts coming from the Galileo chip. + * It could be built in ethernet ports etc... + */ +static void gt64240_irq(int irq, void *dev_id, struct pt_regs *regs) +{ + unsigned int irq_src, int_high_src, irq_src_mask, + int_high_src_mask; + int handled; + +#if 0 + GT_READ(GT_INTRCAUSE_OFS, &irq_src); + GT_READ(GT_INTRMASK_OFS, &irq_src_mask); + GT_READ(GT_HINTRCAUSE_OFS, &int_high_src); + GT_READ(GT_HINTRMASK_OFS, &int_high_src_mask); +#endif + irq_src = irq_src & irq_src_mask; + int_high_src = int_high_src & int_high_src_mask; + + handled = 0; + + /* Execute all interrupt handlers */ + /* Check for timer interrupt */ + if (irq_src & 0x00000800) { + handled = 1; + irq_src &= ~0x00000800; + // RESET_REG_BITS (INTERRUPT_CAUSE_REGISTER,BIT8); + do_timer(regs); + } + + if (irq_src) { + printk(KERN_INFO + "Other Galileo interrupt received irq_src %x\n", + irq_src); +#if CURRENTLY_UNUSED + for (count = 0; count < MAX_CAUSE_REG_WIDTH; count++) { + if (irq_src & (1 << count)) { + if (irq_handlers[INT_CAUSE_MAIN][count]. + routine) { + queue_task(&irq_handlers + [INT_CAUSE_MAIN][count], + &tq_immediate); + mark_bh(IMMEDIATE_BH); + handled = 1; + } + } + } +#endif /* UNUSED */ + } +#if 0 + GT_WRITE(GT_INTRCAUSE_OFS, 0); + GT_WRITE(GT_HINTRCAUSE_OFS, 0); +#endif + +#undef GALILEO_I2O +#ifdef GALILEO_I2O + /* + * Future I2O support. We currently attach I2O interrupt handlers to + * the Galileo interrupt (int 4) and handle them in do_IRQ. + */ + if (isInBoundDoorBellInterruptSet()) { + printk(KERN_INFO "I2O doorbell interrupt received.\n"); + handled = 1; + } + + if (isInBoundPostQueueInterruptSet()) { + printk(KERN_INFO "I2O Queue interrupt received.\n"); + handled = 1; + } + + /* + * This normally would be outside of the ifdef, but since we're + * handling I2O outside of this handler, this printk shows up every + * time we get a valid I2O interrupt. So turn this off for now. + */ + if (handled == 0) { + if (counter < 50) { + printk("Spurious Galileo interrupt...\n"); + counter++; + } + } +#endif +} + +/* + * Initializes timer using galileo's built in timer. + */ + +/* + * This will ignore the standard MIPS timer interrupt handler + * that is passed in as *irq (=irq0 in ../kernel/time.c). + * We will do our own timer interrupt handling. + */ +void gt64240_time_init(void) +{ + extern irq_desc_t irq_desc[NR_IRQS]; + static struct irqaction timer; + + /* Stop the timer -- we'll use timer #0 */ + GT_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0); + + /* Load timer value for 100 Hz */ + GT_WRITE(TIMER_COUNTER0, bus_clock / 100); + + /* + * Create the IRQ structure entry for the timer. Since we're too early + * in the boot process to use the "request_irq()" call, we'll hard-code + * the values to the correct interrupt line. + */ + timer.handler = >64240_p0int_irq; + timer.flags = SA_SHIRQ | SA_INTERRUPT; + timer.name = "timer"; + timer.dev_id = NULL; + timer.next = NULL; + timer.mask = 0; + irq_desc[6].action = &timer; + + enable_irq(6); + + /* Clear any pending cause bits */ + GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); + + /* Enable the interrupt for timer 0 */ + GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1); + + /* Enable the timer interrupt for GT-64240 pin P0_INT# */ + GT_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100); + + /* Configure and start the timer */ + GT_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3); +} + +void gt64240_irq_init(void) +{ +#if CURRENTLY_UNUSED + int i, j; + + /* Reset irq handlers pointers to NULL */ + for (i = 0; i < MAX_CAUSE_REGS; i++) { + for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) { + irq_handlers[i][j].next = NULL; + irq_handlers[i][j].sync = 0; + irq_handlers[i][j].routine = NULL; + irq_handlers[i][j].data = NULL; + } + } +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_g/int-handler.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,133 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * First-level interrupt dispatcher for ocelot board. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#define __ASSEMBLY__ +#include +#include +#include +#include +#include +#include + +/* + * first level interrupt dispatcher for ocelot board - + * We check for the timer first, then check PCI ints A and D. + * Then check for serial IRQ and fall through. + */ + .align 5 + NESTED(ocelot_handle_int, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + mfc0 t0, CP0_CAUSE + mfc0 t2, CP0_STATUS + + and t0, t2 + + andi t1, t0, STATUSF_IP2 /* int0 hardware line */ + bnez t1, ll_pri_enet_irq + andi t1, t0, STATUSF_IP3 /* int1 hardware line */ + bnez t1, ll_sec_enet_irq + andi t1, t0, STATUSF_IP4 /* int2 hardware line */ + bnez t1, ll_uart_irq + andi t1, t0, STATUSF_IP5 /* int3 hardware line */ + bnez t1, ll_cpci_irq + andi t1, t0, STATUSF_IP6 /* int4 hardware line */ + bnez t1, ll_galileo_p0_irq + andi t1, t0, STATUSF_IP7 /* cpu timer */ + bnez t1, ll_cputimer_irq + + /* now look at the extended interrupts */ + mfc0 t0, CP0_CAUSE + cfc0 t1, CP0_S1_INTCONTROL + + /* shift the mask 8 bits left to line up the bits */ + sll t2, t1, 8 + + and t0, t2 + srl t0, t0, 16 + + andi t1, t0, STATUSF_IP8 /* int6 hardware line */ + bnez t1, ll_galileo_p1_irq + andi t1, t0, STATUSF_IP9 /* int7 hardware line */ + bnez t1, ll_pmc_irq + andi t1, t0, STATUSF_IP10 /* int8 hardware line */ + bnez t1, ll_cpci_abcd_irq + andi t1, t0, STATUSF_IP11 /* int9 hardware line */ + bnez t1, ll_testpoint_irq + + .set reorder + + /* wrong alarm or masked ... */ + j spurious_interrupt + nop + END(ocelot_handle_int) + + .align 5 +ll_pri_enet_irq: + li a0, 2 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_sec_enet_irq: + li a0, 3 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_uart_irq: + li a0, 4 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpci_irq: + li a0, 5 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_galileo_p0_irq: + li a0, 6 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cputimer_irq: + li a0, 7 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_galileo_p1_irq: + li a0, 8 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_pmc_irq: + li a0, 9 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpci_abcd_irq: + li a0, 10 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_testpoint_irq: + li a0, 11 + move a1, sp + jal do_IRQ + j ret_from_irq --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_g/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,172 @@ +/* + * Copyright (C) 2000 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +static spinlock_t rm7000_irq_lock = SPIN_LOCK_UNLOCKED; + +/* Function for careful CP0 interrupt mask access */ +static inline void modify_cp0_intmask(unsigned clr_mask_in, unsigned set_mask_in) +{ + unsigned long status; + unsigned clr_mask; + unsigned set_mask; + + /* do the low 8 bits first */ + clr_mask = 0xff & clr_mask_in; + set_mask = 0xff & set_mask_in; + status = read_c0_status(); + status &= ~((clr_mask & 0xFF) << 8); + status |= (set_mask & 0xFF) << 8; + write_c0_status(status); + + /* do the high 8 bits */ + clr_mask = 0xff & (clr_mask_in >> 8); + set_mask = 0xff & (set_mask_in >> 8); + status = read_c0_intcontrol(); + status &= ~((clr_mask & 0xFF) << 8); + status |= (set_mask & 0xFF) << 8; + write_c0_intrcontrol(status); +} + +static inline void mask_irq(unsigned int irq) +{ + modify_cp0_intmask(irq, 0); +} + +static inline void unmask_irq(unsigned int irq) +{ + modify_cp0_intmask(0, irq); +} + +static void enable_cp7000_irq(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&rm7000_irq_lock, flags); + unmask_irq(1 << irq); + spin_unlock_irqrestore(&rm7000_irq_lock, flags); +} + +static unsigned int startup_cp7000_irq(unsigned int irq) +{ + enable_cp7000_irq(irq); + + return 0; /* never anything pending */ +} + +static void disable_cp7000_irq(unsigned int irq) +{ + unsigned long flags; + + spin_lock_irqsave(&rm7000_irq_lock, flags); + mask_irq(1 << irq); + spin_unlock_irqrestore(&rm7000_irq_lock, flags); +} + +#define shutdown_cp7000_irq disable_cp7000_irq + +static void mask_and_ack_cp7000_irq(unsigned int irq) +{ + mask_irq(1 << irq); +} + +static void end_cp7000_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + unmask_irq(1 << irq); +} + +static struct hw_interrupt_type cp7000_hpcdma_irq_type = { + "CP7000", + startup_cp7000_irq, + shutdown_cp7000_irq, + enable_cp7000_irq, + disable_cp7000_irq, + mask_and_ack_cp7000_irq, + end_cp7000_irq, + NULL +}; + + +extern asmlinkage void ocelot_handle_int(void); +extern void gt64240_irq_init(void); + +void __init init_IRQ(void) +{ + int i; + + /* + * Clear all of the interrupts while we change the able around a bit. + * int-handler is not on bootstrap + */ + clear_c0_status(ST0_IM | ST0_BEV); + local_irq_disable(); + + /* Sets the first-level interrupt dispatcher. */ + set_except_vector(0, ocelot_handle_int); + init_generic_irq(); + + for (i = 0; i <= 15; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &cp7000_hpcdma_irq_type; + } + + gt64240_irq_init(); + +#ifdef CONFIG_KGDB + printk("start kgdb ...\n"); + set_debug_traps(); + breakpoint(); /* you may move this line to whereever you want :-) */ +#endif +#ifdef CONFIG_GDB_CONSOLE + register_gdb_console(); +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_g/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,9 @@ +# +# Makefile for Momentum Computer's Ocelot-G board. +# + +obj-y += gt-irq.o pci-irq.o int-handler.o irq.o prom.o \ + reset.o setup.o +obj-$(CONFIG_KGDB) += dbg_io.o + +EXTRA_AFLAGS := $(CFLAGS) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_g/ocelot_pld.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,30 @@ +/* + * Ocelot Board Register Definitions + * + * (C) 2001 Red Hat, Inc. + * + * GPL'd + */ +#ifndef __MOMENCO_OCELOT_PLD_H__ +#define __MOMENCO_OCELOT_PLD_H__ + +#define OCELOT_CS0_ADDR (0xfc000000) + +#define OCELOT_REG_BOARDREV (0) +#define OCELOT_REG_PLD1_ID (1) +#define OCELOT_REG_PLD2_ID (2) +#define OCELOT_REG_RESET_STATUS (3) +#define OCELOT_REG_BOARD_STATUS (4) +#define OCELOT_REG_CPCI_ID (5) +#define OCELOT_REG_I2C_CTRL (8) +#define OCELOT_REG_EEPROM_MODE (9) +#define OCELOT_REG_INTMASK (10) +#define OCELOT_REG_INTSTATUS (11) +#define OCELOT_REG_INTSET (12) +#define OCELOT_REG_INTCLR (13) + +#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y) +#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x) + + +#endif /* __MOMENCO_OCELOT_PLD_H__ */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_g/pci-irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,74 @@ +/* + * Copyright 2002 Momentum Computer Inc. + * Author: Matthew Dharm + * + * Based on work for the Linux port to the Ocelot board, which is + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * arch/mips/momentum/ocelot_g/pci.c + * Board-specific PCI routines for gt64240 controller. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include + + +void __devinit gt64240_board_pcibios_fixup_bus(struct pci_bus *bus) +{ + struct pci_bus *current_bus = bus; + struct pci_dev *devices; + struct list_head *devices_link; + u16 cmd; + + /* loop over all known devices on this bus */ + list_for_each(devices_link, &(current_bus->devices)) { + + devices = pci_dev_b(devices_link); + if (devices == NULL) + continue; + + if ((current_bus->number == 0) && + PCI_SLOT(devices->devfn) == 1) { + /* Intel 82543 Gigabit MAC */ + devices->irq = 2; /* irq_nr is 2 for INT0 */ + } else if ((current_bus->number == 0) && + PCI_SLOT(devices->devfn) == 2) { + /* Intel 82543 Gigabit MAC */ + devices->irq = 3; /* irq_nr is 3 for INT1 */ + } else if ((current_bus->number == 1) && + PCI_SLOT(devices->devfn) == 3) { + /* Intel 21555 bridge */ + devices->irq = 5; /* irq_nr is 8 for INT6 */ + } else if ((current_bus->number == 1) && + PCI_SLOT(devices->devfn) == 4) { + /* PMC Slot */ + devices->irq = 9; /* irq_nr is 9 for INT7 */ + } else { + /* We don't have assign interrupts for other devices. */ + devices->irq = 0xff; + } + + /* Assign an interrupt number for the device */ + bus->ops->write(current_bus, devices, + PCI_INTERRUPT_LINE, 1, devices->irq); + + /* enable master for everything but the GT-64240 */ + if (((current_bus->number != 0) && (current_bus->number != 1)) + || (PCI_SLOT(devices->devfn) != 0)) { + bus->ops->read(current_bus, devices, + PCI_COMMAND, 2, &cmd); + cmd |= PCI_COMMAND_MASTER; + bus->ops->write(current_bus, devices, + PCI_COMMAND, 2, cmd); + } + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_g/prom.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,100 @@ +/* + * Copyright 2002 Momentum Computer Inc. + * Author: Matthew Dharm + * + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include + +#include +#include + +#include "gt64240.h" +#include "ocelot_pld.h" + +struct callvectors { + int (*open) (char*, int, int); + int (*close) (int); + int (*read) (int, void*, int); + int (*write) (int, void*, int); + off_t (*lseek) (int, off_t, int); + int (*printf) (const char*, ...); + void (*cacheflush) (void); + char* (*gets) (char*); +}; + +struct callvectors* debug_vectors; +char arcs_cmdline[CL_SIZE]; + +extern unsigned long gt64240_base; +extern unsigned long bus_clock; + +#ifdef CONFIG_GALILLEO_GT64240_ETH +extern unsigned char prom_mac_addr_base[6]; +#endif + +const char *get_system_type(void) +{ + return "Momentum Ocelot"; +} + +/* [jsun@junsun.net] PMON passes arguments in C main() style */ +void __init prom_init(int argc, char **arg, char** env, struct callvectors *cv) +{ + int i; + uint32_t tmp; + + /* save the PROM vectors for debugging use */ + debug_vectors = cv; + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + for (i = 1; i < argc; i++) { + if (strlen(arcs_cmdline) + strlen(arg[i] + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, arg[i]); + strcat(arcs_cmdline, " "); + } + + mips_machgroup = MACH_GROUP_MOMENCO; + mips_machtype = MACH_MOMENCO_OCELOT_G; + +#ifdef CONFIG_GALILLEO_GT64240_ETH + /* get the base MAC address for on-board ethernet ports */ + memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6); +#endif + + while (*env) { + if (strncmp("gtbase", *env, strlen("gtbase")) == 0) { + gt64240_base = simple_strtol(*env + strlen("gtbase="), + NULL, 16); + } + if (strncmp("busclock", *env, strlen("busclock")) == 0) { + bus_clock = simple_strtol(*env + strlen("busclock="), + NULL, 10); + } + *env++; + } + + debug_vectors->printf("Booting Linux kernel...\n"); +} + +void __init prom_free_prom_memory(void) +{ +} + +void __init prom_fixup_mem_map(unsigned long start, unsigned long end) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_g/reset.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,47 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 1997, 2001 Ralf Baechle + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + */ +#include +#include +#include +#include +#include +#include +#include +#include + +void momenco_ocelot_restart(char *command) +{ + void *nvram = ioremap_nocache(0x2c807000, 0x1000); + + if (!nvram) { + printk(KERN_NOTICE "ioremap of reset register failed\n"); + return; + } + writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to + assert reset in 1/16 second */ + mdelay(10+(1000/16)); + iounmap(nvram); + printk(KERN_NOTICE "Watchdog reset failed\n"); +} + +void momenco_ocelot_halt(void) +{ + printk(KERN_NOTICE "\n** You can safely turn off the power\n"); + while (1) + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); +} + +void momenco_ocelot_power_off(void) +{ + momenco_ocelot_halt(); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/momentum/ocelot_g/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,265 @@ +/* + * setup.c + * + * BRIEF MODULE DESCRIPTION + * Momentum Computer Ocelot-G (CP7000G) - board dependent boot routines + * + * Copyright (C) 1996, 1997, 2001 Ralf Baechle + * Copyright (C) 2000 RidgeRun, Inc. + * Copyright (C) 2001 Red Hat, Inc. + * Copyright (C) 2002 Momentum Computer + * + * Author: Matthew Dharm, Momentum Computer + * mdharm@momenco.com + * + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gt64240.h" +#include "ocelot_pld.h" + +extern struct rtc_ops no_rtc_ops; + +#ifdef CONFIG_GALILLEO_GT64240_ETH +extern unsigned char prom_mac_addr_base[6]; +#endif + +unsigned long gt64240_base; + +/* These functions are used for rebooting or halting the machine*/ +extern void momenco_ocelot_restart(char *command); +extern void momenco_ocelot_halt(void); +extern void momenco_ocelot_power_off(void); + +extern void gt64240_time_init(void); +extern void momenco_ocelot_irq_setup(void); + +static char reset_reason; + +#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1) + +static void __init setup_l3cache(unsigned long size); + +/* setup code for a handoff from a version 2 PMON 2000 PROM */ +void PMON_v2_setup(void) +{ + /* A wired TLB entry for the GT64240 and the serial port. The + GT64240 is going to be hit on every IRQ anyway - there's + absolutely no point in letting it be a random TLB entry, as + it'll just cause needless churning of the TLB. And we use + the other half for the serial port, which is just a PITA + otherwise :) + + Device Physical Virtual + GT64240 Internal Regs 0xf4000000 0xe0000000 + UARTs (CS2) 0xfd000000 0xe0001000 + */ + add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K); + add_wired_entry(ENTRYLO(0xfd000000), ENTRYLO(0xfd001000), 0xfd000000, PM_4K); + + /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM + in the CS[012] region. We can't use ioremap() yet. The NVRAM + is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. + + Ocelot PLD (CS0) 0xfc000000 0xe0020000 + NVRAM (CS1) 0xfc800000 0xe0030000 + */ + add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000), 0xfc000000, PM_64K); + add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000), 0xfc800000, PM_64K); + + gt64240_base = 0xf4000000; +} + +void __init momenco_ocelot_g_setup(void) +{ + void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache); + unsigned int tmpword; + + board_time_init = gt64240_time_init; + + _machine_restart = momenco_ocelot_restart; + _machine_halt = momenco_ocelot_halt; + _machine_power_off = momenco_ocelot_power_off; + + /* + * initrd_start = (ulong)ocelot_initrd_start; + * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size; + * initrd_below_start_ok = 1; + */ + rtc_ops = &no_rtc_ops; + + /* do handoff reconfiguration */ + PMON_v2_setup(); + +#ifdef CONFIG_GALILLEO_GT64240_ETH + /* get the mac addr */ + memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6); +#endif + + /* Turn off the Bit-Error LED */ + OCELOT_PLD_WRITE(0x80, INTCLR); + + tmpword = OCELOT_PLD_READ(BOARDREV); + if (tmpword < 26) + printk("Momenco Ocelot-G: Board Assembly Rev. %c\n", 'A'+tmpword); + else + printk("Momenco Ocelot-G: Board Assembly Revision #0x%x\n", tmpword); + + tmpword = OCELOT_PLD_READ(PLD1_ID); + printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15); + tmpword = OCELOT_PLD_READ(PLD2_ID); + printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15); + tmpword = OCELOT_PLD_READ(RESET_STATUS); + printk("Reset reason: 0x%x\n", tmpword); + reset_reason = tmpword; + OCELOT_PLD_WRITE(0xff, RESET_STATUS); + + tmpword = OCELOT_PLD_READ(BOARD_STATUS); + printk("Board Status register: 0x%02x\n", tmpword); + printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); + printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); + printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not"); + printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1); + printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3))); + + if (tmpword&12) + l3func((1<<(((tmpword&12) >> 2)+20))); + + switch(tmpword &3) { + case 3: + /* 512MiB -- two banks of 256MiB */ + add_memory_region( 0x0<<20, 0x100<<20, BOOT_MEM_RAM); +/* + add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM); +*/ + break; + case 2: + /* 256MiB -- two banks of 128MiB */ + add_memory_region( 0x0<<20, 0x80<<20, BOOT_MEM_RAM); + add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM); + break; + case 1: + /* 128MiB -- 64MiB per bank */ + add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM); + add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); + break; + case 0: + /* 64MiB */ + add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM); + break; + } + + /* FIXME: Fix up the DiskOnChip mapping */ + GT_WRITE(0x468, 0xfef73); +} + +extern int rm7k_tcache_enabled; +/* + * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache() + */ +#define Page_Invalidate_T 0x16 +static void __init setup_l3cache(unsigned long size) +{ + int register i; + unsigned long tmp; + + printk("Enabling L3 cache..."); + + /* Enable the L3 cache in the GT64120A's CPU Configuration register */ + GT_READ(0, &tmp); + GT_WRITE(0, tmp | (1<<14)); + + /* Enable the L3 cache in the CPU */ + set_c0_config(1<<12 /* CONF_TE */); + + /* Clear the cache */ + write_c0_taglo(0); + write_c0_taghi(0); + + for (i=0; i < size; i+= 4096) { + __asm__ __volatile__ ( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (KSEG0ADDR(i)), + "i" (Page_Invalidate_T)); + } + + /* Let the RM7000 MM code know that the tertiary cache is enabled */ + rm7k_tcache_enabled = 1; + + printk("Done\n"); +} + + +/* This needs to be one of the first initcalls, because no I/O port access + can work before this */ + +static int io_base_ioremap(void) +{ + /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */ + void *io_remap_range = ioremap(0xc0000000, 0x30000000); + + if (!io_remap_range) { + panic("Could not ioremap I/O port range"); + } + printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range); + set_io_port_base(io_remap_range - 0xc0000000); + + return 0; +} + +module_init(io_base_ioremap); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/common.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,69 @@ +void __init pcibios_fixup_bus(struct pci_bus *b) +{ + Dprintk("pcibios_fixup_bus()\n"); +} + +static int pcibios_enable_resources(struct pci_dev *dev, int mask) +{ + u16 cmd, old_cmd; + int idx; + struct resource *r; + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + old_cmd = cmd; + for (idx = 0; idx < 6; idx++) { + /* Only set up the requested stuff */ + if (!(mask & (1 << idx))) + continue; + + r = &dev->resource[idx]; + if (!r->start && r->end) { + printk(KERN_ERR + "PCI: Device %s not available because of resource collisions\n", + dev->slot_name); + return -EINVAL; + } + if (r->flags & IORESOURCE_IO) + cmd |= PCI_COMMAND_IO; + if (r->flags & IORESOURCE_MEM) + cmd |= PCI_COMMAND_MEMORY; + } + if (dev->resource[PCI_ROM_RESOURCE].start) + cmd |= PCI_COMMAND_MEMORY; + if (cmd != old_cmd) { + printk("PCI: Enabling device %s (%04x -> %04x)\n", + dev->slot_name, old_cmd, cmd); + pci_write_config_word(dev, PCI_COMMAND, cmd); + } + return 0; +} + +int pcibios_enable_device(struct pci_dev *dev, int mask) +{ + int err; + + if ((err = pcibios_enable_resources(dev, mask)) < 0) + return err; + + return 0; +} + +void __init pcibios_align_resource(void *data, struct resource *res, + unsigned long size, unsigned long align) +{ + panic("Uhhoh called pcibios_align_resource"); +} + +unsigned __init int pcibios_assign_all_busses(void) +{ + return 1; +} + +char *pcibios_setup(char *str) +{ + return str; +} + +struct pci_fixup pcibios_fixups[] = { + {0} +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/fixup-au1000.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,124 @@ +/* + * BRIEF MODULE DESCRIPTION + * Board specific pci fixups. + * + * Copyright 2001-2003 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include + +#include +//#include +#ifdef CONFIG_MIPS_PB1000 +#include +#endif + +#undef DEBUG +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +static void fixup_resource(int r_num, struct pci_dev *dev); +#ifdef CONFIG_SOC_AU1500 +static unsigned long virt_io_addr; +#endif + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ + /* will need to fixup IO resources */ +} + +void __init pcibios_fixup(void) +{ +#ifdef CONFIG_SOC_AU1500 + int i; + struct pci_dev *dev; + + virt_io_addr = (unsigned long) ioremap(Au1500_PCI_IO_START, + Au1500_PCI_IO_END - + Au1500_PCI_IO_START + 1); + + if (!virt_io_addr) { + printk(KERN_ERR "Unable to ioremap pci space\n"); + return; + } + + set_io_port_base(virt_io_addr); +#endif + +#ifdef CONFIG_MIPS_PB1000 /* This is truly board specific */ + unsigned long pci_mem_start = (unsigned long) PCI_MEM_START; + + au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0 + au_writel(0, SDRAM_MBAR); // set mbar to 0 + au_writel(0x2, SDRAM_CMD); // enable memory accesses + au_sync_delay(1); + + // set extend byte to mbar of ext slot + au_writel(((pci_mem_start >> 24) & 0xff) | + (1 << 8 | 1 << 9 | 1 << 10 | 1 << 27), + PCI_BRIDGE_CONFIG); + DBG("Set bridge config to %x\n", au_readl(PCI_BRIDGE_CONFIG)); +#endif +} + +void __init pcibios_fixup_irqs(void) +{ +#ifdef CONFIG_SOC_AU1500 + unsigned int slot, func; + unsigned char pin; + struct pci_dev *dev = NULL; + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + if (dev->bus->number != 0) + return; + + dev->irq = 0xff; + slot = PCI_SLOT(dev->devfn); + switch (slot) { + case 12: + case 13: + dev->irq = AU1000_PCI_INTA; + break; + + } + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + DBG("slot %d irq %d\n", slot, dev->irq); + } +#endif +} +unsigned int pcibios_assign_all_busses(void) +{ + return 0; +} + +static void fixup_resource(int r_num, struct pci_dev *dev) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/fixup-capcella.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,72 @@ +/* + * FILE NAME + * arch/mips/vr41xx/zao-capcella/pci_fixup.c + * + * BRIEF MODULE DESCRIPTION + * The ZAO Networks Capcella specific PCI fixups. + * + * Copyright 2002 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include + +#include + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ +} + +void __init pcibios_fixup(void) +{ +} + +void __init pcibios_fixup_irqs(void) +{ + struct pci_dev *dev = NULL; + u8 slot, func, pin; + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + slot = PCI_SLOT(dev->devfn); + func = PCI_FUNC(dev->devfn); + dev->irq = 0; + + switch (slot) { + case 11: + dev->irq = RTL8139_1_IRQ; + break; + case 12: + dev->irq = RTL8139_2_IRQ; + break; + case 14: + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); + switch (pin) { + case 1: + dev->irq = PC104PLUS_INTA_IRQ; + break; + case 2: + dev->irq = PC104PLUS_INTB_IRQ; + break; + case 3: + dev->irq = PC104PLUS_INTC_IRQ; + break; + case 4: + dev->irq = PC104PLUS_INTD_IRQ; + break; + } + break; + } + + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + } +} + +unsigned int pcibios_assign_all_busses(void) +{ + return 0; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/fixup-eagle.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,166 @@ +/* + * FILE NAME + * arch/mips/vr41xx/nec-eagle/pci_fixup.c + * + * BRIEF MODULE DESCRIPTION + * The NEC Eagle/Hawk Board specific PCI fixups. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2001,2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Changes: + * MontaVista Software Inc. or + * - Moved mips_pci_channels[] to arch/mips/vr41xx/vr4122/eagle/setup.c. + * - Added support for NEC Hawk. + * + * Paul Mundt + * - Fix empty break statements. + * + * MontaVista Software Inc. or + * - New creation, NEC Eagle is supported. + */ +#include +#include + +#include +#include + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ +} + +void __init pcibios_fixup(void) +{ +} + +void __init pcibios_fixup_irqs(void) +{ + struct pci_dev *dev = NULL; + u8 slot, func, pin; + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + slot = PCI_SLOT(dev->devfn); + func = PCI_FUNC(dev->devfn); + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); + dev->irq = 0; + + switch (slot) { + case 8: + switch (pin) { + case 1: + dev->irq = CP_INTA_IRQ; + break; + case 2: + dev->irq = CP_INTB_IRQ; + break; + case 3: + dev->irq = CP_INTC_IRQ; + break; + case 4: + dev->irq = CP_INTD_IRQ; + break; + } + break; + case 9: + switch (pin) { + case 1: + dev->irq = CP_INTD_IRQ; + break; + case 2: + dev->irq = CP_INTA_IRQ; + break; + case 3: + dev->irq = CP_INTB_IRQ; + break; + case 4: + dev->irq = CP_INTC_IRQ; + break; + } + break; + case 10: + switch (pin) { + case 1: + dev->irq = CP_INTC_IRQ; + break; + case 2: + dev->irq = CP_INTD_IRQ; + break; + case 3: + dev->irq = CP_INTA_IRQ; + break; + case 4: + dev->irq = CP_INTB_IRQ; + break; + } + break; + case 12: + dev->irq = VRC4173_PCMCIA1_IRQ; + break; + case 13: + dev->irq = VRC4173_PCMCIA2_IRQ; + break; + case 28: + dev->irq = LANINTA_IRQ; + break; + case 29: + switch (pin) { + case 1: + dev->irq = PCISLOT_IRQ; + break; + case 2: + dev->irq = CP_INTB_IRQ; + break; + case 3: + dev->irq = CP_INTC_IRQ; + break; + case 4: + dev->irq = CP_INTD_IRQ; + break; + } + break; + case 30: + switch (func) { + case 0: + dev->irq = VRC4173_CASCADE_IRQ; + break; + case 1: + dev->irq = VRC4173_AC97_IRQ; + break; + case 2: + dev->irq = VRC4173_USB_IRQ; + break; + } + break; + } + + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + } +} + +unsigned int pcibios_assign_all_busses(void) +{ + return 0; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/fixup-ite8172g.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,189 @@ +/* + * BRIEF MODULE DESCRIPTION + * Board specific pci fixups. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include + +#include +#include +#include + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ +} + +void __init pcibios_fixup(void) +{ +} + +void __init pcibios_fixup_irqs(void) +{ + unsigned int slot, func; + unsigned char pin; + struct pci_dev *dev = NULL; + + const int internal_func_irqs[7] = { + IT8172_AC97_IRQ, + IT8172_DMA_IRQ, + IT8172_CDMA_IRQ, + IT8172_USB_IRQ, + IT8172_BRIDGE_MASTER_IRQ, + IT8172_IDE_IRQ, + IT8172_MC68K_IRQ + }; + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + if (dev->bus->number != 0) + return; + + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); + slot = PCI_SLOT(dev->devfn); + func = PCI_FUNC(dev->devfn); + + switch (slot) { + case 0x01: + /* + * Internal device 1 is actually 7 different + * internal devices on the IT8172G (a multi- + * function device). + */ + if (func < 7) + dev->irq = internal_func_irqs[func]; + break; + case 0x10: + switch (pin) { + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTA_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + default: + dev->irq = 0xff; + break; + + } + break; + case 0x11: + switch (pin) { + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTA_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + default: + dev->irq = 0xff; + break; + + } + break; + case 0x12: + switch (pin) { + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTA_IRQ; + break; + default: + dev->irq = 0xff; + break; + + } + break; + case 0x13: + switch (pin) { + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTA_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + default: + dev->irq = 0xff; + break; + + } + break; + case 0x14: + switch (pin) { + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTA_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + default: + dev->irq = 0xff; + break; + + } + break; + default: + continue; /* do nothing */ + } +#ifdef DEBUG + printk("irq fixup: slot %d, int line %d, int number %d\n", + slot, pin, dev->irq); +#endif + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/fixup-ivr.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,153 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Globespan IVR board-specific pci fixups. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include + +#include +#include +#include + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ +} + +void __init pcibios_fixup(void) +{ +} + +void __init pcibios_fixup_irqs(void) +{ + unsigned int slot, func; + unsigned char pin; + struct pci_dev *dev = NULL; + + const int internal_func_irqs[7] = { + IT8172_AC97_IRQ, + IT8172_DMA_IRQ, + IT8172_CDMA_IRQ, + IT8172_USB_IRQ, + IT8172_BRIDGE_MASTER_IRQ, + IT8172_IDE_IRQ, + IT8172_MC68K_IRQ + }; + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + if (dev->bus->number != 0) + return; + + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); + slot = PCI_SLOT(dev->devfn); + func = PCI_FUNC(dev->devfn); + + switch (slot) { + case 0x01: + /* + * Internal device 1 is actually 7 different + * internal devices on the IT8172G (multi-function + * device). + */ + if (func < 7) + dev->irq = internal_func_irqs[func]; + break; + case 0x11: // Realtek RTL-8139 + switch (pin) { + case 0: /* pin A, hardware bug */ + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTA_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + default: + dev->irq = 0xff; + break; + + } + break; + case 0x12: // ivr slot + switch (pin) { + case 0: /* pin A, hardware bug */ + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + default: + dev->irq = 0xff; + break; + + } + break; + case 0x13: // expansion slot + switch (pin) { + case 0: /* pin A, hardware bug */ + case 1: /* pin A */ + dev->irq = IT8172_PCI_INTA_IRQ; + break; + case 2: /* pin B */ + dev->irq = IT8172_PCI_INTB_IRQ; + break; + case 3: /* pin C */ + dev->irq = IT8172_PCI_INTC_IRQ; + break; + case 4: /* pin D */ + dev->irq = IT8172_PCI_INTD_IRQ; + break; + default: + dev->irq = 0xff; + break; + + } + break; + default: + break; + } +#ifdef DEBUG + printk("irq fixup: slot %d, int line %d, int number %d\n", + slot, pin, dev->irq); +#endif + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/fixup-jmr3927.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,138 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Board specific pci fixups. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include + +#include + +#undef DEBUG +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ + /* will need to fixup IO resources */ +} + +void __init pcibios_fixup(void) +{ + /* nothing to do here */ +} + +int pci_get_irq(struct pci_dev *dev, int pin) +{ + unsigned char irq = pin; + + /* IRQ rotation (PICMG) */ + irq--; /* 0-3 */ + if (dev->bus->parent == NULL && + PCI_SLOT(dev->devfn) == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) { + /* PCI CardSlot (IDSEL=A23, DevNu=12) */ + /* PCIA => PCIC (IDSEL=A23) */ + /* NOTE: JMR3927 JP1 must be set to OPEN */ + irq = (irq + 2) % 4; + } else if (dev->bus->parent == NULL && + PCI_SLOT(dev->devfn) == + TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) { + /* PCI CardSlot (IDSEL=A22, DevNu=11) */ + /* PCIA => PCIA (IDSEL=A22) */ + /* NOTE: JMR3927 JP1 must be set to OPEN */ + irq = (irq + 0) % 4; + } else { + /* PCI Backplane */ + irq = (irq + 3 + PCI_SLOT(dev->devfn)) % 4; +#if 0 /* ??? */ + for (bus = dev->bus; bus->parent != NULL; + bus = bus->parent) { + irq = (irq + 3 + PCI_SLOT(bus->self->devfn)) % 4; + } +#endif + } + irq++; /* 1-4 */ + + switch (irq) { + case 1: + irq = JMR3927_IRQ_IOC_PCIA; + break; + case 2: + // wrong for backplane irq = JMR3927_IRQ_IOC_PCIB; + irq = JMR3927_IRQ_IOC_PCID; + break; + case 3: + irq = JMR3927_IRQ_IOC_PCIC; + break; + case 4: + // wrong for backplane irq = JMR3927_IRQ_IOC_PCID; + irq = JMR3927_IRQ_IOC_PCIB; + break; + } + + /* Check OnBoard Ethernet (IDSEL=A24, DevNu=13) */ + if (dev->bus->parent == NULL && + PCI_SLOT(dev->devfn) == TX3927_PCIC_IDSEL_AD_TO_SLOT(24)) { + extern int jmr3927_ether1_irq; + /* check this irq line was reserved for ether1 */ + if (jmr3927_ether1_irq != JMR3927_IRQ_ETHER0) + irq = JMR3927_IRQ_ETHER0; + else + irq = 0; /* disable */ + } + return irq; +} + +void __init pcibios_fixup_irqs(void) +{ + unsigned char irq; + struct pci_dev *dev = NULL; + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); + if (irq == 0) + return; + + /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */ + if (!(dev->vendor == PCI_VENDOR_ID_EFAR && + dev->device == PCI_DEVICE_ID_EFAR_SLC90E66_1)) { + irq = pci_get_irq(dev, irq); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + irq); + } + + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); + printk(KERN_INFO "PCI: %02x:%02x IRQ %02x\n", + dev->bus->number, dev->devfn, irq); + dev->irq = irq; + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/fixup-ocelot.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,77 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * arch/mips/gt64120/momenco_ocelot/pci.c + * Board-specific PCI routines for gt64120 controller. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include + + +void __devinit gt64120_board_pcibios_fixup_bus(struct pci_bus *bus) +{ + struct pci_bus *current_bus = bus; + struct pci_dev *devices; + struct list_head *devices_link; + u16 cmd; + + list_for_each(devices_link, &(current_bus->devices)) { + + devices = pci_dev_b(devices_link); + if (devices == NULL) + continue; + + if (PCI_SLOT(devices->devfn) == 1) { + /* + * Slot 1 is primary ether port, i82559 + * we double-check against that assumption + */ + if ((devices->vendor != 0x8086) || + (devices->device != 0x1209)) { + panic + ("gt64120_board_pcibios_fixup_bus: found " + "unexpected PCI device in slot 1."); + } + devices->irq = 2; /* irq_nr is 2 for INT0 */ + } else if (PCI_SLOT(devices->devfn) == 2) { + /* + * Slot 2 is secondary ether port, i21143 + * we double-check against that assumption + */ + if ((devices->vendor != 0x1011) || + (devices->device != 0x19)) { + panic("galileo_pcibios_fixup_bus: " + "found unexpected PCI device in slot 2."); + } + devices->irq = 3; /* irq_nr is 3 for INT1 */ + } else if (PCI_SLOT(devices->devfn) == 4) { + /* PMC Slot 1 */ + devices->irq = 8; /* irq_nr is 8 for INT6 */ + } else if (PCI_SLOT(devices->devfn) == 5) { + /* PMC Slot 1 */ + devices->irq = 9; /* irq_nr is 9 for INT7 */ + } else { + /* We don't have assign interrupts for other devices. */ + devices->irq = 0xff; + } + + /* Assign an interrupt number for the device */ + bus->ops->write_byte(devices, PCI_INTERRUPT_LINE, + devices->irq); + + /* enable master */ + bus->ops->read_word(devices, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + bus->ops->write_word(devices, PCI_COMMAND, cmd); + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/fixups-ev96100.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,91 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * EV96100 Board specific pci fixups. + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include + +#include +#include + +extern unsigned short get_gt_devid(void); + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ +} + +void __init pcibios_fixup(void) +{ +} + +void __init pcibios_fixup_irqs(void) +{ + struct pci_dev *dev = NULL; + unsigned int slot; + u32 vendor; + unsigned short gt_devid = get_gt_devid(); + + /* + ** EV96100/A interrupt routing for pci bus 0 + ** + ** Note: EV96100A board with irq jumper set on 'VxWorks' + ** for EV96100 compatibility. + */ + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + if (dev->bus->number != 0) + return; + + slot = PCI_SLOT(dev->devfn); + pci_read_config_dword(dev, PCI_SUBSYSTEM_VENDOR_ID, + &vendor); + +#ifdef DEBUG + printk("devfn %x, slot %d devid %x\n", + dev->devfn, slot, gt_devid); +#endif + + /* fixup irq line based on slot # */ + if (slot == 8) { + dev->irq = 5; + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + dev->irq); + } else if (slot == 9) { + dev->irq = 2; + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + dev->irq); + } + } +} +unsigned int pcibios_assign_all_busses(void) +{ + return 0; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/fixup-tb0226.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,91 @@ +/* + * FILE NAME + * arch/mips/vr41xx/tanbac-tb0226/pci_fixup.c + * + * BRIEF MODULE DESCRIPTION + * The TANBAC TB0226 specific PCI fixups. + * + * Copyright 2002,2003 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include + +#include + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ +} + +void __init pcibios_fixup(void) +{ +} + +void __init pcibios_fixup_irqs(void) +{ + struct pci_dev *dev = NULL; + u8 slot, pin; + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + slot = PCI_SLOT(dev->devfn); + dev->irq = 0; + + switch (slot) { + case 12: + vr41xx_set_irq_trigger(GD82559_1_PIN, + TRIGGER_LEVEL, + SIGNAL_THROUGH); + vr41xx_set_irq_level(GD82559_1_PIN, LEVEL_LOW); + dev->irq = GD82559_1_IRQ; + break; + case 13: + vr41xx_set_irq_trigger(GD82559_2_PIN, + TRIGGER_LEVEL, + SIGNAL_THROUGH); + vr41xx_set_irq_level(GD82559_2_PIN, LEVEL_LOW); + dev->irq = GD82559_2_IRQ; + break; + case 14: + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); + switch (pin) { + case 1: + vr41xx_set_irq_trigger(UPD720100_INTA_PIN, + TRIGGER_LEVEL, + SIGNAL_THROUGH); + vr41xx_set_irq_level(UPD720100_INTA_PIN, + LEVEL_LOW); + dev->irq = UPD720100_INTA_IRQ; + break; + case 2: + vr41xx_set_irq_trigger(UPD720100_INTB_PIN, + TRIGGER_LEVEL, + SIGNAL_THROUGH); + vr41xx_set_irq_level(UPD720100_INTB_PIN, + LEVEL_LOW); + dev->irq = UPD720100_INTB_IRQ; + break; + case 3: + vr41xx_set_irq_trigger(UPD720100_INTC_PIN, + TRIGGER_LEVEL, + SIGNAL_THROUGH); + vr41xx_set_irq_level(UPD720100_INTC_PIN, + LEVEL_LOW); + dev->irq = UPD720100_INTC_IRQ; + break; + } + break; + } + + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + } +} + +unsigned int pcibios_assign_all_busses(void) +{ + return 0; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/fixup-tb0229.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,77 @@ +/* + * FILE NAME + * arch/mips/vr41xx/tanbac-tb0229/pci_fixup.c + * + * BRIEF MODULE DESCRIPTION + * The TANBAC TB0229(VR4131DIMM) specific PCI fixups. + * + * Copyright 2003 Megasolution Inc. + * matsu@megasolution.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include + +#include + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ +} + +void __init pcibios_fixup(void) +{ +} + +void __init pcibios_fixup_irqs(void) +{ +#ifdef CONFIG_TANBAC_TB0219 + struct pci_dev *dev = NULL; + u8 slot; + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + slot = PCI_SLOT(dev->devfn); + dev->irq = 0; + + switch (slot) { + case 12: + vr41xx_set_irq_trigger(TB0219_PCI_SLOT1_PIN, + TRIGGER_LEVEL, + SIGNAL_THROUGH); + vr41xx_set_irq_level(TB0219_PCI_SLOT1_PIN, + LEVEL_LOW); + dev->irq = TB0219_PCI_SLOT1_IRQ; + break; + case 13: + vr41xx_set_irq_trigger(TB0219_PCI_SLOT2_PIN, + TRIGGER_LEVEL, + SIGNAL_THROUGH); + vr41xx_set_irq_level(TB0219_PCI_SLOT2_PIN, + LEVEL_LOW); + dev->irq = TB0219_PCI_SLOT2_IRQ; + break; + case 14: + vr41xx_set_irq_trigger(TB0219_PCI_SLOT3_PIN, + TRIGGER_LEVEL, + SIGNAL_THROUGH); + vr41xx_set_irq_level(TB0219_PCI_SLOT3_PIN, + LEVEL_LOW); + dev->irq = TB0219_PCI_SLOT3_IRQ; + break; + default: + break; + } + + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + } +#endif +} + +unsigned int pcibios_assign_all_busses(void) +{ + return 0; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/fixup-victor-mpc30x.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,72 @@ +/* + * FILE NAME + * arch/mips/vr41xx/victor-mpc30x/pci_fixup.c + * + * BRIEF MODULE DESCRIPTION + * The Victor MP-C303/304 specific PCI fixups. + * + * Copyright 2002 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include + +#include +#include + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ +} + +void __init pcibios_fixup(void) +{ +} + +void __init pcibios_fixup_irqs(void) +{ + struct pci_dev *dev = NULL; + u8 slot, func; + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + slot = PCI_SLOT(dev->devfn); + func = PCI_FUNC(dev->devfn); + dev->irq = 0; + + switch (slot) { + case 12: /* NEC VRC4173 CARDU1 */ + dev->irq = VRC4173_PCMCIA1_IRQ; + break; + case 13: /* NEC VRC4173 CARDU2 */ + dev->irq = VRC4173_PCMCIA2_IRQ; + break; + case 29: /* mediaQ MQ-200 */ + dev->irq = MQ200_IRQ; + break; + case 30: + switch (func) { + case 0: /* NEC VRC4173 */ + dev->irq = VRC4173_CASCADE_IRQ; + break; + case 1: /* NEC VRC4173 AC97U */ + dev->irq = VRC4173_AC97_IRQ; + break; + case 2: /* NEC VRC4173 USBU */ + dev->irq = VRC4173_USB_IRQ; + break; + } + break; + } + + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + } +} + +unsigned int pcibios_assign_all_busses(void) +{ + return 0; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,36 @@ +# +# Makefile for the PCI specific kernel interface routines under Linux. +# +# This is all organized on a per system base which is horribly wrong and +# really wants a cleanup. You have been warned. +# + +obj-$(CONFIG_NEW_PCI) += pci.o +obj-$(CONFIG_PCI_AUTO) += pci-auto.o +obj-$(CONFIG_DDB5074) += pci-ddb5074.o ops-ddb5074.o +obj-$(CONFIG_DDB5476) += pci-ddb5476.o ops-ddb5476.o +obj-$(CONFIG_DDB5477) += pci-ddb5477.o ops-ddb5477.o +obj-$(CONFIG_HP_LASERJET) += pci-hplj.o +obj-$(CONFIG_ITE_BOARD_GEN) += ops-it8172.o +obj-$(CONFIG_LASAT) += pci-lasat.o +obj-$(CONFIG_MIPS_BOARDS_GEN) += pci-mips.o +obj-$(CONFIG_MIPS_COBALT) += pci-cobalt.o +obj-$(CONFIG_MIPS_EV64120) += ops-ev64120.o +obj-$(CONFIG_MIPS_EV96100) += fixup-ev96100.o ops-ev96100.o +obj-$(CONFIG_MIPS_ITE8172) += fixup-ite8172g.o +obj-$(CONFIG_MIPS_IVR) += fixup-ivr.o +obj-$(CONFIG_MIPS_PB1500) += fixups-au1000.o ops-au1000.o +obj-$(CONFIG_MOMENCO_OCELOT) += fixups-ocelot.o ops-ocelot.o +obj-$(CONFIG_NEC_EAGLE) += fixup-eagle.o ops-vrc4173.o +obj-$(CONFIG_SGI_IP27) += pci-ip27.o +obj-$(CONFIG_SGI_IP32) += pci-ip32.o +obj-$(CONFIG_SIBYTE_SB1250) += pci-sb1250.o +obj-$(CONFIG_SNI_RM200_PCI) += pci-sni.o +obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o +obj-$(CONFIG_TANBAC_TB0229) += fixup-tb0229.o +obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o ops-jmr3927.o +#obj-$(CONFIG_MOMENCO_OCELOT_C) += pci-ocelot-c.o +obj-$(CONFIG_MOMENCO_OCELOT_G) += pci-ocelot-g.o +obj-$(CONFIG_VICTOR_MPC30X) += fixup-capcella.o +obj-$(CONFIG_VR41XX_COMMON) += pci-vr41xx.o +obj-$(CONFIG_ZAO_CAPCELLA) += fixup-victor-mpc30x.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/ops-au1000.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,330 @@ +/* + * BRIEF MODULE DESCRIPTION + * Alchemy/AMD Au1x00 pci support. + * + * Copyright 2001,2002,2003 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * Support for all devices (greater than 16) added by David Gathright. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include + +#include +#ifdef CONFIG_MIPS_PB1000 +#include +#endif +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#undef DEBUG +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +/* TBD */ +static struct resource pci_io_resource = { + "pci IO space", + (u32) PCI_IO_START, + (u32) PCI_IO_END, + IORESOURCE_IO +}; + +static struct resource pci_mem_resource = { + "pci memory space", + (u32) PCI_MEM_START, + (u32) PCI_MEM_END, + IORESOURCE_MEM +}; + +extern struct pci_ops au1x_pci_ops; + +struct pci_channel mips_pci_channels[] = { + {&au1x_pci_ops, &pci_io_resource, &pci_mem_resource, + PCI_FIRST_DEVFN, PCI_LAST_DEVFN}, + {(struct pci_ops *) NULL, (struct resource *) NULL, + (struct resource *) NULL, (int) NULL, (int) NULL} +}; + + +#ifdef CONFIG_MIPS_PB1000 +/* + * "Bus 2" is really the first and only external slot on the pb1000. + * We'll call that bus 0, and limit the accesses to that single + * external slot only. The SDRAM is already initialized in setup.c. + */ +static int config_access(unsigned char access_type, struct pci_dev *dev, + unsigned char where, u32 * data) +{ + unsigned char bus = dev->bus->number; + unsigned char dev_fn = dev->devfn; + unsigned long config; + + if (((dev_fn >> 3) != 0) || (bus != 0)) { + *data = 0xffffffff; + return -1; + } + + config = PCI_CONFIG_BASE | (where & ~0x3); + + if (access_type == PCI_ACCESS_WRITE) { + au_writel(*data, config); + } else { + *data = au_readl(config); + } + au_sync_udelay(1); + + DBG("config_access: %d bus %d dev_fn %x at %x *data %x, conf %x\n", + access_type, bus, dev_fn, where, *data, config); + + DBG("bridge config reg: %x (%x)\n", au_readl(PCI_BRIDGE_CONFIG), + *data); + + if (au_readl(PCI_BRIDGE_CONFIG) & (1 << 16)) { + *data = 0xffffffff; + return -1; + } else { + return PCIBIOS_SUCCESSFUL; + } +} + +#else + +static int config_access(unsigned char access_type, struct pci_bus *bus, + unsigned int devfn, unsigned char where, + u32 * data) +{ +#ifdef CONFIG_SOC_AU1500 + unsigned int device = PCI_SLOT(devfn); + unsigned int function = PCI_FUNC(devfn); + unsigned long config, status; + unsigned long cfg_addr; + + if (device > 19) { + *data = 0xffffffff; + return -1; + } + + au_writel(((0x2000 << 16) | + (au_readl(Au1500_PCI_STATCMD) & 0xffff)), + Au1500_PCI_STATCMD); + //au_writel(au_readl(Au1500_PCI_CFG) & ~PCI_ERROR, Au1500_PCI_CFG); + au_sync_udelay(1); + + /* setup the config window */ + if (bus->number == 0) { + cfg_addr = (unsigned long) ioremap(Au1500_EXT_CFG | + ((1 << device) << 11), + 0x00100000); + } else { + cfg_addr = (unsigned long) ioremap(Au1500_EXT_CFG_TYPE1 | + (bus-> + number << 16) | (device + << + 11), + 0x00100000); + } + + if (!cfg_addr) + panic(KERN_ERR "PCI unable to ioremap cfg space\n"); + + /* setup the lower bits of the 36 bit address */ + config = cfg_addr | (function << 8) | (where & ~0x3); + +#if 0 + if (access_type == PCI_ACCESS_WRITE) { + printk("cfg write: "); + } else { + printk("cfg read: "); + } + printk("devfn %x, device %x func %x \n", devfn, device, function); + if (access_type == PCI_ACCESS_WRITE) { + printk("data %x\n", *data); + } +#endif + + if (access_type == PCI_ACCESS_WRITE) { + au_writel(*data, config); + } else { + *data = au_readl(config); + } + au_sync_udelay(2); + + + DBG("config_access: %d bus %d device %d at %x *data %x, conf %x\n", + access_type, bus->number, device, where, *data, config); + + /* unmap io space */ + iounmap((void *) cfg_addr); + + /* check master abort */ + status = au_readl(Au1500_PCI_STATCMD); +#if 0 + if (access_type == PCI_ACCESS_READ) { + printk("read data: %x\n", *data); + } +#endif + if (status & (1 << 29)) { + *data = 0xffffffff; + return -1; + } else if ((status >> 28) & 0xf) { + printk("PCI ERR detected: status %x\n", status); + *data = 0xffffffff; + return -1; + } else { + return PCIBIOS_SUCCESSFUL; + } +#endif +} +#endif + +static int read_config_byte(struct pci_bus *bus, unsigned int devfn, + int where, u8 * val) +{ + u32 data; + int ret; + + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + if (where & 1) + data >>= 8; + if (where & 2) + data >>= 16; + *val = data & 0xff; + return ret; +} + + +static int read_config_word(struct pci_bus *bus, unsigned int devfn, + int where, u16 * val) +{ + u32 data; + int ret; + + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); + if (where & 2) + data >>= 16; + *val = data & 0xffff; + return ret; +} + +static int read_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, u32 * val) +{ + int ret; + + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val); + return ret; +} + +static int +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, + u8 val) +{ + u32 data = 0; + + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) + return -1; + + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +static int +write_config_word(struct pci_bus *bus, unsigned int devfn, int where, + u16 val) +{ + u32 data = 0; + + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) + return -1; + + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return -1; + + + return PCIBIOS_SUCCESSFUL; +} + +static int +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, + u32 val) +{ + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +static int config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + switch (size) { + case 1: + return read_config_byte(bus, devfn, where, (u8 *) val); + case 2: + return read_config_word(bus, devfn, where, (u16 *) val); + default: + return read_config_dword(bus, devfn, where, val); + } +} + +static int config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + switch (size) { + case 1: + return write_config_byte(bus, devfn, where, (u8) val); + case 2: + return write_config_word(bus, devfn, where, (u16) val); + default: + return write_config_dword(bus, devfn, where, val); + } +} + + +struct pci_ops au1x_pci_ops = { + config_read, + config_write +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/ops-ddb5074.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,335 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * arch/mips/ddb5xxx/ddb5476/pci_ops.c + * Define the pci_ops for DB5477. + * + * Much of the code is derived from the original DDB5074 port by + * Geert Uytterhoeven + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include +#include + +#include +#include + +#include + +/* + * config_swap structure records what set of pdar/pmr are used + * to access pci config space. It also provides a place hold the + * original values for future restoring. + */ +struct pci_config_swap { + u32 pdar; + u32 pmr; + u32 config_base; + u32 config_size; + u32 pdar_backup; + u32 pmr_backup; +}; + +/* + * On DDB5476, we have one set of swap registers + */ +struct pci_config_swap ext_pci_swap = { + DDB_PCIW0, + DDB_PCIINIT0, + DDB_PCI_CONFIG_BASE, + DDB_PCI_CONFIG_SIZE +}; + +static int pci_config_workaround = 1; + +/* + * access config space + */ +static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */ + u32 slot_num) +{ + u32 pci_addr = 0; + u32 pciinit_offset = 0; + u32 virt_addr = swap->config_base; + u32 option; + + if (pci_config_workaround) { + if (slot_num == 5) + slot_num = 14; + } else { + if (slot_num == 5) + return DDB_BASE + DDB_PCI_BASE; + } + + /* minimum pdar (window) size is 2MB */ + db_assert(swap->config_size >= (2 << 20)); + + db_assert(slot_num < (1 << 5)); + db_assert(bus < (1 << 8)); + + /* backup registers */ + swap->pdar_backup = ddb_in32(swap->pdar); + swap->pmr_backup = ddb_in32(swap->pmr); + + /* set the pdar (pci window) register */ + ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */ + 0, /* not on local memory bus */ + 0); /* not visible from PCI bus (N/A) */ + + /* + * calcuate the absolute pci config addr; + * according to the spec, we start scanning from adr:11 (0x800) + */ + if (bus == 0) { + /* type 0 config */ + pci_addr = 0x00040000 << slot_num; + } else { + /* type 1 config */ + pci_addr = 0x00040000 << slot_num; + panic + ("ddb_access_config_base: we don't support type 1 config Yet"); + } + + /* + * if pci_addr is less than pci config window size, we set + * pciinit_offset to 0 and adjust the virt_address. + * Otherwise we will try to adjust pciinit_offset. + */ + if (pci_addr < swap->config_size) { + virt_addr = KSEG1ADDR(swap->config_base + pci_addr); + pciinit_offset = 0; + } else { + db_assert((pci_addr & (swap->config_size - 1)) == 0); + virt_addr = KSEG1ADDR(swap->config_base); + pciinit_offset = pci_addr; + } + + /* set the pmr register */ + option = DDB_PCI_ACCESS_32; + if (bus != 0) + option |= DDB_PCI_CFGTYPE1; + ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option); + + return virt_addr; +} + +static inline void ddb_close_config_base(struct pci_config_swap *swap) +{ + ddb_out32(swap->pdar, swap->pdar_backup); + ddb_out32(swap->pmr, swap->pmr_backup); +} + +static int read_config_dword(struct pci_config_swap *swap, + struct pci_dev *dev, u32 where, u32 * val) +{ + u32 bus, slot_num, func_num; + u32 base; + + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + slot_num = PCI_SLOT(dev->devfn); + func_num = PCI_FUNC(dev->devfn); + base = ddb_access_config_base(swap, bus, slot_num); + *val = *(volatile u32 *) (base + (func_num << 8) + where); + ddb_close_config_base(swap); + return PCIBIOS_SUCCESSFUL; +} + +static int read_config_word(struct pci_config_swap *swap, + struct pci_dev *dev, u32 where, u16 * val) +{ + int status; + u32 result; + + db_assert((where & 1) == 0); + + status = read_config_dword(swap, dev, where & ~3, &result); + if (where & 2) + result >>= 16; + *val = result & 0xffff; + return status; +} + +static int read_config_byte(struct pci_config_swap *swap, + struct pci_dev *dev, u32 where, u8 * val) +{ + int status; + u32 result; + + status = read_config_dword(swap, dev, where & ~3, &result); + if (where & 1) + result >>= 8; + if (where & 2) + result >>= 16; + *val = result & 0xff; + return status; +} + +static int write_config_dword(struct pci_config_swap *swap, + struct pci_dev *dev, u32 where, u32 val) +{ + u32 bus, slot_num, func_num; + u32 base; + + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + slot_num = PCI_SLOT(dev->devfn); + func_num = PCI_FUNC(dev->devfn); + base = ddb_access_config_base(swap, bus, slot_num); + *(volatile u32 *) (base + (func_num << 8) + where) = val; + ddb_close_config_base(swap); + return PCIBIOS_SUCCESSFUL; +} + +static int write_config_word(struct pci_config_swap *swap, + struct pci_dev *dev, u32 where, u16 val) +{ + int status, shift = 0; + u32 result; + + db_assert((where & 1) == 0); + + status = read_config_dword(swap, dev, where & ~3, &result); + if (status != PCIBIOS_SUCCESSFUL) + return status; + + if (where & 2) + shift += 16; + result &= ~(0xffff << shift); + result |= val << shift; + return write_config_dword(swap, dev, where & ~3, result); +} + +static int write_config_byte(struct pci_config_swap *swap, + struct pci_dev *dev, u32 where, u8 val) +{ + int status, shift = 0; + u32 result; + + status = read_config_dword(swap, dev, where & ~3, &result); + if (status != PCIBIOS_SUCCESSFUL) + return status; + + if (where & 2) + shift += 16; + if (where & 1) + shift += 8; + result &= ~(0xff << shift); + result |= val << shift; + return write_config_dword(swap, dev, where & ~3, result); +} + +#define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \ +static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \ +{ \ + return rw##_config_##unitname(pciswap, \ + dev, \ + where, \ + val); \ +} + +MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap) + MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap) + MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap) + + MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap) + MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap) + MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap) + +struct pci_ops ddb5476_ext_pci_ops = { + extpci_read_config_byte, + extpci_read_config_word, + extpci_read_config_dword, + extpci_write_config_byte, + extpci_write_config_word, + extpci_write_config_dword +}; + + +#if defined(CONFIG_RUNTIME_DEBUG) +void jsun_scan_pci_bus(void) +{ + struct pci_bus bus; + struct pci_dev dev; + unsigned int devfn; + int j; + + pci_config_workaround = 0; + + bus.parent = NULL; /* we scan the top level only */ + dev.bus = &bus; + dev.sysdata = NULL; + + /* scan ext pci bus and io pci bus */ + for (j = 0; j < 1; j++) { + printk(KERN_INFO "scan ddb5476 external PCI bus:\n"); + bus.ops = &ddb5476_ext_pci_ops; + + for (devfn = 0; devfn < 0x100; devfn += 8) { + u32 temp; + u16 temp16; + u8 temp8; + int i; + + dev.devfn = devfn; + db_verify(pci_read_config_dword(&dev, 0, &temp), + == PCIBIOS_SUCCESSFUL); + if (temp == 0xffffffff) + continue; + + printk(KERN_INFO "slot %d: (addr %d) \n", + devfn / 8, 11 + devfn / 8); + + /* verify read word and byte */ + db_verify(pci_read_config_word(&dev, 2, &temp16), + == PCIBIOS_SUCCESSFUL); + db_assert(temp16 == (temp >> 16)); + db_verify(pci_read_config_byte(&dev, 3, &temp8), + == PCIBIOS_SUCCESSFUL); + db_assert(temp8 == (temp >> 24)); + db_verify(pci_read_config_byte(&dev, 1, &temp8), + == PCIBIOS_SUCCESSFUL); + db_assert(temp8 == ((temp >> 8) & 0xff)); + + for (i = 0; i < 16; i++) { + if ((i % 4) == 0) + printk(KERN_INFO); + db_verify(pci_read_config_dword + (&dev, i * 4, &temp), + == PCIBIOS_SUCCESSFUL); + printk("\t%08X", temp); + if ((i % 4) == 3) + printk("\n"); + } + } + } + + pci_config_workaround = 1; +} +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/ops-ddb5476.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,350 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * arch/mips/ddb5xxx/ddb5476/pci_ops.c + * Define the pci_ops for DB5477. + * + * Much of the code is derived from the original DDB5074 port by + * Geert Uytterhoeven + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include +#include + +#include +#include + +#include + +/* + * config_swap structure records what set of pdar/pmr are used + * to access pci config space. It also provides a place hold the + * original values for future restoring. + */ +struct pci_config_swap { + u32 pdar; + u32 pmr; + u32 config_base; + u32 config_size; + u32 pdar_backup; + u32 pmr_backup; +}; + +/* + * On DDB5476, we have one set of swap registers + */ +struct pci_config_swap ext_pci_swap = { + DDB_PCIW0, + DDB_PCIINIT0, + DDB_PCI_CONFIG_BASE, + DDB_PCI_CONFIG_SIZE +}; + +static int pci_config_workaround = 1; + +/* + * access config space + */ +static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */ + u32 slot_num) +{ + u32 pci_addr = 0; + u32 pciinit_offset = 0; + u32 virt_addr = swap->config_base; + u32 option; + + if (pci_config_workaround) { + /* [jsun] work around Vrc5476 controller itself, returnning + * slot 0 essentially makes vrc5476 invisible + */ + if (slot_num == 12) + slot_num = 0; + +#if 0 + /* BUG : skip P2P bridge for now */ + if (slot_num == 5) + slot_num = 0; +#endif + + } else { + /* now we have to be hornest, returning the true + * PCI config headers for vrc5476 + */ + if (slot_num == 12) { + swap->pdar_backup = ddb_in32(swap->pdar); + swap->pmr_backup = ddb_in32(swap->pmr); + return DDB_BASE + DDB_PCI_BASE; + } + } + + /* minimum pdar (window) size is 2MB */ + db_assert(swap->config_size >= (2 << 20)); + + db_assert(slot_num < (1 << 5)); + db_assert(bus < (1 << 8)); + + /* backup registers */ + swap->pdar_backup = ddb_in32(swap->pdar); + swap->pmr_backup = ddb_in32(swap->pmr); + + /* set the pdar (pci window) register */ + ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */ + 0, /* not on local memory bus */ + 0); /* not visible from PCI bus (N/A) */ + + /* + * calcuate the absolute pci config addr; + * according to the spec, we start scanning from adr:11 (0x800) + */ + if (bus == 0) { + /* type 0 config */ + pci_addr = 0x800 << slot_num; + } else { + /* type 1 config */ + pci_addr = (bus << 16) | (slot_num << 11); + /* panic("ddb_access_config_base: we don't support type 1 config Yet"); */ + } + + /* + * if pci_addr is less than pci config window size, we set + * pciinit_offset to 0 and adjust the virt_address. + * Otherwise we will try to adjust pciinit_offset. + */ + if (pci_addr < swap->config_size) { + virt_addr = KSEG1ADDR(swap->config_base + pci_addr); + pciinit_offset = 0; + } else { + db_assert((pci_addr & (swap->config_size - 1)) == 0); + virt_addr = KSEG1ADDR(swap->config_base); + pciinit_offset = pci_addr; + } + + /* set the pmr register */ + option = DDB_PCI_ACCESS_32; + if (bus != 0) + option |= DDB_PCI_CFGTYPE1; + ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option); + + return virt_addr; +} + +static inline void ddb_close_config_base(struct pci_config_swap *swap) +{ + ddb_out32(swap->pdar, swap->pdar_backup); + ddb_out32(swap->pmr, swap->pmr_backup); +} + +static int read_config_dword(struct pci_config_swap *swap, + struct pci_dev *dev, u32 where, u32 * val) +{ + u32 bus, slot_num, func_num; + u32 base; + + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + slot_num = PCI_SLOT(dev->devfn); + func_num = PCI_FUNC(dev->devfn); + base = ddb_access_config_base(swap, bus, slot_num); + *val = *(volatile u32 *) (base + (func_num << 8) + where); + ddb_close_config_base(swap); + return PCIBIOS_SUCCESSFUL; +} + +static int read_config_word(struct pci_config_swap *swap, + struct pci_dev *dev, u32 where, u16 * val) +{ + int status; + u32 result; + + db_assert((where & 1) == 0); + + status = read_config_dword(swap, dev, where & ~3, &result); + if (where & 2) + result >>= 16; + *val = result & 0xffff; + return status; +} + +static int read_config_byte(struct pci_config_swap *swap, + struct pci_dev *dev, u32 where, u8 * val) +{ + int status; + u32 result; + + status = read_config_dword(swap, dev, where & ~3, &result); + if (where & 1) + result >>= 8; + if (where & 2) + result >>= 16; + *val = result & 0xff; + return status; +} + +static int write_config_dword(struct pci_config_swap *swap, + struct pci_dev *dev, u32 where, u32 val) +{ + u32 bus, slot_num, func_num; + u32 base; + + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + slot_num = PCI_SLOT(dev->devfn); + func_num = PCI_FUNC(dev->devfn); + base = ddb_access_config_base(swap, bus, slot_num); + *(volatile u32 *) (base + (func_num << 8) + where) = val; + ddb_close_config_base(swap); + return PCIBIOS_SUCCESSFUL; +} + +static int write_config_word(struct pci_config_swap *swap, + struct pci_dev *dev, u32 where, u16 val) +{ + int status, shift = 0; + u32 result; + + db_assert((where & 1) == 0); + + status = read_config_dword(swap, dev, where & ~3, &result); + if (status != PCIBIOS_SUCCESSFUL) + return status; + + if (where & 2) + shift += 16; + result &= ~(0xffff << shift); + result |= val << shift; + return write_config_dword(swap, dev, where & ~3, result); +} + +static int write_config_byte(struct pci_config_swap *swap, + struct pci_dev *dev, u32 where, u8 val) +{ + int status, shift = 0; + u32 result; + + status = read_config_dword(swap, dev, where & ~3, &result); + if (status != PCIBIOS_SUCCESSFUL) + return status; + + if (where & 2) + shift += 16; + if (where & 1) + shift += 8; + result &= ~(0xff << shift); + result |= val << shift; + return write_config_dword(swap, dev, where & ~3, result); +} + +#define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \ +static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \ +{ \ + return rw##_config_##unitname(pciswap, \ + dev, \ + where, \ + val); \ +} + +MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap) + MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap) + MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap) + + MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap) + MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap) + MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap) + +struct pci_ops ddb5476_ext_pci_ops = { + extpci_read_config_byte, + extpci_read_config_word, + extpci_read_config_dword, + extpci_write_config_byte, + extpci_write_config_word, + extpci_write_config_dword +}; + + +#if defined(CONFIG_RUNTIME_DEBUG) +void jsun_scan_pci_bus(void) +{ + struct pci_bus bus; + struct pci_dev dev; + unsigned int devfn; + int j; + + pci_config_workaround = 0; + + bus.parent = NULL; /* we scan the top level only */ + dev.bus = &bus; + dev.sysdata = NULL; + + /* scan ext pci bus and io pci bus */ + for (j = 0; j < 1; j++) { + printk(KERN_INFO "scan ddb5476 external PCI bus:\n"); + bus.ops = &ddb5476_ext_pci_ops; + + for (devfn = 0; devfn < 0x100; devfn += 8) { + u32 temp; + u16 temp16; + u8 temp8; + int i; + + dev.devfn = devfn; + db_verify(pci_read_config_dword(&dev, 0, &temp), + == PCIBIOS_SUCCESSFUL); + if (temp == 0xffffffff) + continue; + + printk(KERN_INFO "slot %d: (addr %d) \n", + devfn / 8, 11 + devfn / 8); + + /* verify read word and byte */ + db_verify(pci_read_config_word(&dev, 2, &temp16), + == PCIBIOS_SUCCESSFUL); + db_assert(temp16 == (temp >> 16)); + db_verify(pci_read_config_byte(&dev, 3, &temp8), + == PCIBIOS_SUCCESSFUL); + db_assert(temp8 == (temp >> 24)); + db_verify(pci_read_config_byte(&dev, 1, &temp8), + == PCIBIOS_SUCCESSFUL); + db_assert(temp8 == ((temp >> 8) & 0xff)); + + for (i = 0; i < 16; i++) { + if ((i % 4) == 0) + printk(KERN_INFO); + db_verify(pci_read_config_dword + (&dev, i * 4, &temp), + == PCIBIOS_SUCCESSFUL); + printk("\t%08X", temp); + if ((i % 4) == 3) + printk("\n"); + } + } + } + + pci_config_workaround = 1; +} +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/ops-ddb5477.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,281 @@ +/*********************************************************************** + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * arch/mips/ddb5xxx/ddb5477/pci_ops.c + * Define the pci_ops for DB5477. + * + * Much of the code is derived from the original DDB5074 port by + * Geert Uytterhoeven + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + *********************************************************************** + */ + +/* + * DDB5477 has two PCI channels, external PCI and IOPIC (internal) + * Therefore we provide two sets of pci_ops. + */ +#include +#include +#include + +#include +#include + +#include + +/* + * config_swap structure records what set of pdar/pmr are used + * to access pci config space. It also provides a place hold the + * original values for future restoring. + */ +struct pci_config_swap { + u32 pdar; + u32 pmr; + u32 config_base; + u32 config_size; + u32 pdar_backup; + u32 pmr_backup; +}; + +/* + * On DDB5477, we have two sets of swap registers, for ext PCI and IOPCI. + */ +struct pci_config_swap ext_pci_swap = { + DDB_PCIW0, + DDB_PCIINIT00, + DDB_PCI0_CONFIG_BASE, + DDB_PCI0_CONFIG_SIZE +}; +struct pci_config_swap io_pci_swap = { + DDB_IOPCIW0, + DDB_PCIINIT01, + DDB_PCI1_CONFIG_BASE, + DDB_PCI1_CONFIG_SIZE +}; + + +/* + * access config space + */ +static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */ + u32 slot_num) +{ + u32 pci_addr = 0; + u32 pciinit_offset = 0; + u32 virt_addr = swap->config_base; + u32 option; + + /* minimum pdar (window) size is 2MB */ + db_assert(swap->config_size >= (2 << 20)); + + db_assert(slot_num < (1 << 5)); + db_assert(bus < (1 << 8)); + + /* backup registers */ + swap->pdar_backup = ddb_in32(swap->pdar); + swap->pmr_backup = ddb_in32(swap->pmr); + + /* set the pdar (pci window) register */ + ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */ + 0, /* not on local memory bus */ + 0); /* not visible from PCI bus (N/A) */ + + /* + * calcuate the absolute pci config addr; + * according to the spec, we start scanning from adr:11 (0x800) + */ + if (bus == 0) { + /* type 0 config */ + pci_addr = 0x800 << slot_num; + } else { + /* type 1 config */ + pci_addr = (bus << 16) | (slot_num << 11); + } + + /* + * if pci_addr is less than pci config window size, we set + * pciinit_offset to 0 and adjust the virt_address. + * Otherwise we will try to adjust pciinit_offset. + */ + if (pci_addr < swap->config_size) { + virt_addr = KSEG1ADDR(swap->config_base + pci_addr); + pciinit_offset = 0; + } else { + db_assert((pci_addr & (swap->config_size - 1)) == 0); + virt_addr = KSEG1ADDR(swap->config_base); + pciinit_offset = pci_addr; + } + + /* set the pmr register */ + option = DDB_PCI_ACCESS_32; + if (bus != 0) + option |= DDB_PCI_CFGTYPE1; + ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option); + + return virt_addr; +} + +static inline void ddb_close_config_base(struct pci_config_swap *swap) +{ + ddb_out32(swap->pdar, swap->pdar_backup); + ddb_out32(swap->pmr, swap->pmr_backup); +} + +static int read_config_dword(struct pci_config_swap *swap, + struct pci_bus *bus, u32 where, u32 * val) +{ + u32 bus, slot_num, func_num; + u32 base; + + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + slot_num = PCI_SLOT(dev->devfn); + func_num = PCI_FUNC(dev->devfn); + base = ddb_access_config_base(swap, bus, slot_num); + *val = *(volatile u32 *) (base + (func_num << 8) + where); + ddb_close_config_base(swap); + return PCIBIOS_SUCCESSFUL; +} + +static int read_config_word(struct pci_config_swap *swap, + struct pci_bus *bus, u32 where, u16 * val) +{ + int status; + u32 result; + + db_assert((where & 1) == 0); + + status = read_config_dword(swap, bus, where & ~3, &result); + if (where & 2) + result >>= 16; + *val = result & 0xffff; + return status; +} + +static int read_config_byte(struct pci_config_swap *swap, + struct pci_bus *bus, unsigned int devfn, + u8 * val) +{ + int status; + u32 result; + + status = read_config_dword(swap, bus, where & ~3, &result); + if (where & 1) + result >>= 8; + if (where & 2) + result >>= 16; + *val = result & 0xff; + + return status; +} + +static int write_config_dword(struct pci_config_swap *swap, + struct pci_bus *bus, unsigned int devfn, + u32 val) +{ + u32 busno, slot_num, func_num; + u32 base; + + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); + + /* check if the bus is top-level */ + if (bus->parent != NULL) { + busno = bus->number; + db_assert(busno != 0); + } else { + busno = 0; + } + + slot_num = PCI_SLOT(devfn); + func_num = PCI_FUNC(devfn); + base = ddb_access_config_base(swap, busno, slot_num); + *(volatile u32 *) (base + (func_num << 8) + where) = val; + ddb_close_config_base(swap); + return PCIBIOS_SUCCESSFUL; +} + +static int write_config_word(struct pci_config_swap *swap, + struct pci_bus *bus, unsigned int devfn, + int where, u16 val) +{ + int status, shift = 0; + u32 result; + + db_assert((where & 1) == 0); + + status = read_config_dword(swap, dev, where & ~3, &result); + if (status != PCIBIOS_SUCCESSFUL) + return status; + + if (where & 2) + shift += 16; + result &= ~(0xffff << shift); + result |= val << shift; + return write_config_dword(swap, dev, where & ~3, result); +} + +static int write_config_byte(struct pci_config_swap *swap, + struct pci_bus *bus, unsigned int devfn, + int where, u8 val) +{ + int status, shift = 0; + u32 result; + + status = read_config_dword(swap, dev, where & ~3, &result); + if (status != PCIBIOS_SUCCESSFUL) + return status; + + if (where & 2) + shift += 16; + if (where & 1) + shift += 8; + result &= ~(0xff << shift); + result |= val << shift; + return write_config_dword(swap, dev, where & ~3, result); +} + +/* + * Dump solution for now so I don't break hw I can't test on ... + */ +#define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \ +static int prefix##_##rw##_config(struct pci_bus *bus, int where, int size, unittype val) \ +{ \ + if (size == 1) \ + return rw##_config_byte(pciswap, bus, where, val); \ + else if (size == 2) \ + return rw##_config_word(pciswap, bus, where, val); \ + /* Size must be 4 */ \ + return rw##_config_dword(pciswap, bus, where, val); \ +} + +MAKE_PCI_OPS(extpci, read, &ext_pci_swap) + MAKE_PCI_OPS(extpci, write, &ext_pci_swap) + + MAKE_PCI_OPS(iopci, read, &io_pci_swap) + MAKE_PCI_OPS(iopci, write, &io_pci_swap) + +struct pci_ops ddb5477_ext_pci_ops = { + .read = extpci_read_config, + .write = extpci_write_config +}; + + +struct pci_ops ddb5477_io_pci_ops = { + .read = iopci_read_config, + .write = iopci_write_config +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/ops-ev64120.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,1201 @@ +/* + * BRIEF MODULE DESCRIPTION + * Galileo Evaluation Boards PCI support. + * + * The general-purpose functions to read/write and configure the GT64120A's + * PCI registers (function names start with pci0 or pci1) are either direct + * copies of functions written by Galileo Technology, or are modifications + * of their functions to work with Linux 2.4 vs Linux 2.2. These functions + * are Copyright - Galileo Technology. + * + * Other functions are derived from other MIPS PCI implementations, or were + * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#undef PCI_DEBUG + +#ifdef PCI_DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +#define SELF 0 + +/* + * These functions and structures provide the BIOS scan and mapping of the PCI + * devices. + */ + +#define MAX_PCI_DEVS 10 + +struct pci_device { + u32 slot; + u32 BARtype[6]; + u32 BARsize[6]; +}; + +static void __init scan_and_initialize_pci(void); +static u32 __init scan_pci_bus(struct pci_device *pci_devices); +static void __init allocate_pci_space(struct pci_device *pci_devices); + +static void __devinit galileo_pcibios_fixup_bus(struct pci_bus *bus); + +/* + * The functions that actually read and write to the controller. + * Copied from or modified from Galileo Technology code. + */ +static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device); +static void pci0WriteConfigReg(unsigned int offset, + struct pci_dev *device, unsigned int data); +static unsigned int pci1ReadConfigReg(int offset, struct pci_dev *device); +static void pci1WriteConfigReg(unsigned int offset, + struct pci_dev *device, unsigned int data); + +static void pci0MapIOspace(unsigned int pci0IoBase, + unsigned int pci0IoLength); +static void pci1MapIOspace(unsigned int pci1IoBase, + unsigned int pci1IoLength); +static void pci0MapMemory0space(unsigned int pci0Mem0Base, + unsigned int pci0Mem0Length); +static void pci1MapMemory0space(unsigned int pci1Mem0Base, + unsigned int pci1Mem0Length); +static void pci0MapMemory1space(unsigned int pci0Mem1Base, + unsigned int pci0Mem1Length); +static void pci1MapMemory1space(unsigned int pci1Mem1Base, + unsigned int pci1Mem1Length); +static unsigned int pci0GetIOspaceBase(void); +static unsigned int pci0GetIOspaceSize(void); +static unsigned int pci0GetMemory0Base(void); +static unsigned int pci0GetMemory0Size(void); +static unsigned int pci0GetMemory1Base(void); +static unsigned int pci0GetMemory1Size(void); +static unsigned int pci1GetIOspaceBase(void); +static unsigned int pci1GetIOspaceSize(void); +static unsigned int pci1GetMemory0Base(void); +static unsigned int pci1GetMemory0Size(void); +static unsigned int pci1GetMemory1Base(void); +static unsigned int pci1GetMemory1Size(void); + + +/* Functions to implement "pci ops" */ +static int galileo_pcibios_read_config_word(struct pci_dev *dev, + int offset, u16 * val); +static int galileo_pcibios_read_config_byte(struct pci_dev *dev, + int offset, u8 * val); +static int galileo_pcibios_read_config_dword(struct pci_dev *dev, + int offset, u32 * val); +static int galileo_pcibios_write_config_byte(struct pci_dev *dev, + int offset, u8 val); +static int galileo_pcibios_write_config_word(struct pci_dev *dev, + int offset, u16 val); +static int galileo_pcibios_write_config_dword(struct pci_dev *dev, + int offset, u32 val); +static void galileo_pcibios_set_master(struct pci_dev *dev); + +/* + * General-purpose PCI functions. + */ + +/* + * pci0MapIOspace - Maps PCI0 IO space for the master. + * Inputs: base and length of pci0Io + */ +static void pci0MapIOspace(unsigned int pci0IoBase, + unsigned int pci0IoLength) +{ + unsigned int pci0IoTop = + (unsigned int) (pci0IoBase + pci0IoLength); + + if (pci0IoLength == 0) + pci0IoTop++; + + pci0IoBase = (unsigned int) (pci0IoBase >> 21); + pci0IoTop = (unsigned int) (((pci0IoTop - 1) & 0x0fffffff) >> 21); + GT_WRITE(GT_PCI0IOLD_OFS, pci0IoBase); + GT_WRITE(GT_PCI0IOHD_OFS, pci0IoTop); +} + +/* + * pci1MapIOspace - Maps PCI1 IO space for the master. + * Inputs: base and length of pci1Io + */ + +static void pci1MapIOspace(unsigned int pci1IoBase, + unsigned int pci1IoLength) +{ + unsigned int pci1IoTop = + (unsigned int) (pci1IoBase + pci1IoLength); + + if (pci1IoLength == 0) + pci1IoTop++; + + pci1IoBase = (unsigned int) (pci1IoBase >> 21); + pci1IoTop = (unsigned int) (((pci1IoTop - 1) & 0x0fffffff) >> 21); + GT_WRITE(GT_PCI1IOLD_OFS, pci1IoBase); + GT_WRITE(GT_PCI1IOHD_OFS, pci1IoTop); +} + +/* + * pci0MapMemory0space - Maps PCI0 memory0 space for the master. + * Inputs: base and length of pci0Mem0 + */ + +static void pci0MapMemory0space(unsigned int pci0Mem0Base, + unsigned int pci0Mem0Length) +{ + unsigned int pci0Mem0Top = pci0Mem0Base + pci0Mem0Length; + + if (pci0Mem0Length == 0) + pci0Mem0Top++; + + pci0Mem0Base = pci0Mem0Base >> 21; + pci0Mem0Top = ((pci0Mem0Top - 1) & 0x0fffffff) >> 21; + GT_WRITE(GT_PCI0M0LD_OFS, pci0Mem0Base); + GT_WRITE(GT_PCI0M0HD_OFS, pci0Mem0Top); +} + +/* + * pci1MapMemory0space - Maps PCI1 memory0 space for the master. + * Inputs: base and length of pci1Mem0 + */ + +static void pci1MapMemory0space(unsigned int pci1Mem0Base, + unsigned int pci1Mem0Length) +{ + unsigned int pci1Mem0Top = pci1Mem0Base + pci1Mem0Length; + + if (pci1Mem0Length == 0) + pci1Mem0Top++; + + pci1Mem0Base = pci1Mem0Base >> 21; + pci1Mem0Top = ((pci1Mem0Top - 1) & 0x0fffffff) >> 21; + GT_WRITE(GT_PCI1M0LD_OFS, pci1Mem0Base); + GT_WRITE(GT_PCI1M0HD_OFS, pci1Mem0Top); +} + +/* + * pci0MapMemory1space - Maps PCI0 memory1 space for the master. + * Inputs: base and length of pci0Mem1 + */ + +static void pci0MapMemory1space(unsigned int pci0Mem1Base, + unsigned int pci0Mem1Length) +{ + unsigned int pci0Mem1Top = pci0Mem1Base + pci0Mem1Length; + + if (pci0Mem1Length == 0) + pci0Mem1Top++; + + pci0Mem1Base = pci0Mem1Base >> 21; + pci0Mem1Top = ((pci0Mem1Top - 1) & 0x0fffffff) >> 21; + GT_WRITE(GT_PCI0M1LD_OFS, pci0Mem1Base); + GT_WRITE(GT_PCI0M1HD_OFS, pci0Mem1Top); + +} + +/* + * pci1MapMemory1space - Maps PCI1 memory1 space for the master. + * Inputs: base and length of pci1Mem1 + */ + +static void pci1MapMemory1space(unsigned int pci1Mem1Base, + unsigned int pci1Mem1Length) +{ + unsigned int pci1Mem1Top = pci1Mem1Base + pci1Mem1Length; + + if (pci1Mem1Length == 0) + pci1Mem1Top++; + + pci1Mem1Base = pci1Mem1Base >> 21; + pci1Mem1Top = ((pci1Mem1Top - 1) & 0x0fffffff) >> 21; + GT_WRITE(GT_PCI1M1LD_OFS, pci1Mem1Base); + GT_WRITE(GT_PCI1M1HD_OFS, pci1Mem1Top); +} + +/* + * pci0GetIOspaceBase - Return PCI0 IO Base Address. + * Inputs: N/A + * Returns: PCI0 IO Base Address. + */ + +static unsigned int pci0GetIOspaceBase(void) +{ + unsigned int base; + GT_READ(GT_PCI0IOLD_OFS, &base); + base = base << 21; + return base; +} + +/* + * pci0GetIOspaceSize - Return PCI0 IO Bar Size. + * Inputs: N/A + * Returns: PCI0 IO Bar Size. + */ +static unsigned int pci0GetIOspaceSize(void) +{ + unsigned int top, base, size; + GT_READ(GT_PCI0IOLD_OFS, &base); + base = base << 21; + GT_READ(GT_PCI0IOHD_OFS, &top); + top = (top << 21); + size = ((top - base) & 0xfffffff); + size = size | 0x1fffff; + return (size + 1); +} + +/* + * pci0GetMemory0Base - Return PCI0 Memory 0 Base Address. + * Inputs: N/A + * Returns: PCI0 Memory 0 Base Address. + */ +static unsigned int pci0GetMemory0Base(void) +{ + unsigned int base; + GT_READ(GT_PCI0M0LD_OFS, &base); + base = base << 21; + return base; +} + +/* + * pci0GetMemory0Size - Return PCI0 Memory 0 Bar Size. + * Inputs: N/A + * Returns: PCI0 Memory 0 Bar Size. + */ +static unsigned int pci0GetMemory0Size(void) +{ + unsigned int top, base, size; + GT_READ(GT_PCI0M0LD_OFS, &base); + base = base << 21; + GT_READ(GT_PCI0M0HD_OFS, &top); + top = (top << 21); + size = ((top - base) & 0xfffffff); + size = size | 0x1fffff; + return (size + 1); +} + +/* + * pci0GetMemory1Base - Return PCI0 Memory 1 Base Address. + * Inputs: N/A + * Returns: PCI0 Memory 1 Base Address. + */ +static unsigned int pci0GetMemory1Base(void) +{ + unsigned int base; + GT_READ(GT_PCI0M1LD_OFS, &base); + base = base << 21; + return base; +} + +/* + * pci0GetMemory1Size - Return PCI0 Memory 1 Bar Size. + * Inputs: N/A + * Returns: PCI0 Memory 1 Bar Size. + */ + +static unsigned int pci0GetMemory1Size(void) +{ + unsigned int top, base, size; + GT_READ(GT_PCI0M1LD_OFS, &base); + base = base << 21; + GT_READ(GT_PCI0M1HD_OFS, &top); + top = (top << 21); + size = ((top - base) & 0xfffffff); + size = size | 0x1fffff; + return (size + 1); +} + +/* + * pci1GetIOspaceBase - Return PCI1 IO Base Address. + * Inputs: N/A + * Returns: PCI1 IO Base Address. + */ + +static unsigned int pci1GetIOspaceBase(void) +{ + unsigned int base; + GT_READ(GT_PCI1IOLD_OFS, &base); + base = base << 21; + return base; +} + +/* + * pci1GetIOspaceSize - Return PCI1 IO Bar Size. + * Inputs: N/A + * Returns: PCI1 IO Bar Size. + */ + +static unsigned int pci1GetIOspaceSize(void) +{ + unsigned int top, base, size; + GT_READ(GT_PCI1IOLD_OFS, &base); + base = base << 21; + GT_READ(GT_PCI1IOHD_OFS, &top); + top = (top << 21); + size = ((top - base) & 0xfffffff); + size = size | 0x1fffff; + return (size + 1); +} + +/* + * pci1GetMemory0Base - Return PCI1 Memory 0 Base Address. + * Inputs: N/A + * Returns: PCI1 Memory 0 Base Address. + */ + +static unsigned int pci1GetMemory0Base(void) +{ + unsigned int base; + GT_READ(GT_PCI1M0LD_OFS, &base); + base = base << 21; + return base; +} + +/* + * pci1GetMemory0Size - Return PCI1 Memory 0 Bar Size. + * Inputs: N/A + * Returns: PCI1 Memory 0 Bar Size. + */ + +static unsigned int pci1GetMemory0Size(void) +{ + unsigned int top, base, size; + GT_READ(GT_PCI1M1LD_OFS, &base); + base = base << 21; + GT_READ(GT_PCI1M1HD_OFS, &top); + top = (top << 21); + size = ((top - base) & 0xfffffff); + size = size | 0x1fffff; + return (size + 1); +} + +/* + * pci1GetMemory1Base - Return PCI1 Memory 1 Base Address. + * Inputs: N/A + * Returns: PCI1 Memory 1 Base Address. + */ + +static unsigned int pci1GetMemory1Base(void) +{ + unsigned int base; + GT_READ(GT_PCI1M1LD_OFS, &base); + base = base << 21; + return base; +} + +/* + * pci1GetMemory1Size - Return PCI1 Memory 1 Bar Size. + * Inputs: N/A + * Returns: PCI1 Memory 1 Bar Size. + */ + +static unsigned int pci1GetMemory1Size(void) +{ + unsigned int top, base, size; + GT_READ(GT_PCI1M1LD_OFS, &base); + base = base << 21; + GT_READ(GT_PCI1M1HD_OFS, &top); + top = (top << 21); + size = ((top - base) & 0xfffffff); + size = size | 0x1fffff; + return (size + 1); +} + + + +/* + * pci_range_ck - + * + * Check if the pci device that are trying to access does really exists + * on the evaluation board. + * + * Inputs : + * bus - bus number (0 for PCI 0 ; 1 for PCI 1) + * dev - number of device on the specific pci bus + * + * Outpus : + * 0 - if OK , 1 - if failure + */ +static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev) +{ + //DBG(KERN_INFO "p_r_c %d %d\n",bus,dev); + if (((bus == 0) || (bus == 1)) && (dev >= 6) && (dev <= 8)) + return 0; // Bus/Device Number OK + return -1; // Bus/Device Number not OK +} + +/* + * pciXReadConfigReg - Read from a PCI configuration register + * - Make sure the GT is configured as a master before + * reading from another device on the PCI. + * - The function takes care of Big/Little endian conversion. + * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI + * spec) + * pciDevNum: The device number needs to be addressed. + * RETURNS: data , if the data == 0xffffffff check the master abort bit in the + * cause register to make sure the data is valid + * + * Configuration Address 0xCF8: + * + * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number + * |congif|Reserved| Bus |Device|Function|Register|00| + * |Enable| |Number|Number| Number | Number | | <=field Name + * + */ +static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device) +{ + unsigned int DataForRegCf8; + unsigned int data; + + DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | + (PCI_FUNC(device->devfn) << 8) | + (offset & ~0x3)) | 0x80000000; + GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); + + /* The casual observer might wonder why the READ is duplicated here, + rather than immediately following the WRITE, and just have the + swap in the "if". That's because there is a latency problem + with trying to read immediately after setting up the address + register. The "if" check gives enough time for the address + to stabilize, so the READ can work. + */ + if (PCI_SLOT(device->devfn) == SELF) { /* This board */ + GT_READ(GT_PCI0_CFGDATA_OFS, &data); + return data; + } else { /* The PCI is working in LE Mode so swap the Data. */ + GT_READ(GT_PCI0_CFGDATA_OFS, &data); + return cpu_to_le32(data); + } +} + +static unsigned int pci1ReadConfigReg(int offset, struct pci_dev *device) +{ + unsigned int DataForRegCf8; + unsigned int data; + + DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | + (PCI_FUNC(device->devfn) << 8) | + (offset & ~0x3)) | 0x80000000; + /* The casual observer might wonder why the READ is duplicated here, + rather than immediately following the WRITE, and just have the + swap in the "if". That's because there is a latency problem + with trying to read immediately after setting up the address + register. The "if" check gives enough time for the address + to stabilize, so the READ can work. + */ + if (PCI_SLOT(device->devfn) == SELF) { /* This board */ + /* when configurating our own PCI 1 L-unit the access is through + the PCI 0 interface with reg number = reg number + 0x80 */ + DataForRegCf8 |= 0x80; + GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); + } else { /* The PCI is working in LE Mode so swap the Data. */ + GT_WRITE(GT_PCI1_CFGADDR_OFS, DataForRegCf8); + } + if (PCI_SLOT(device->devfn) == SELF) { /* This board */ + GT_READ(GT_PCI0_CFGDATA_OFS, &data); + return data; + } else { + GT_READ(GT_PCI1_CFGDATA_OFS, &data); + return cpu_to_le32(data); + } +} + + + +/* + * pciXWriteConfigReg - Write to a PCI configuration register + * - Make sure the GT is configured as a master before + * writingto another device on the PCI. + * - The function takes care of Big/Little endian conversion. + * Inputs: unsigned int regOffset: The register offset as it apears in the + * GT spec + * (or any other PCI device spec) + * pciDevNum: The device number needs to be addressed. + * + * Configuration Address 0xCF8: + * + * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number + * |congif|Reserved| Bus |Device|Function|Register|00| + * |Enable| |Number|Number| Number | Number | | <=field Name + * + */ +static void pci0WriteConfigReg(unsigned int offset, + struct pci_dev *device, unsigned int data) +{ + unsigned int DataForRegCf8; + + DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | + (PCI_FUNC(device->devfn) << 8) | + (offset & ~0x3)) | 0x80000000; + GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); + if (PCI_SLOT(device->devfn) == SELF) { /* This board */ + GT_WRITE(GT_PCI0_CFGDATA_OFS, data); + } else { /* configuration Transaction over the pci. */ + /* The PCI is working in LE Mode so swap the Data. */ + GT_WRITE(GT_PCI0_CFGDATA_OFS, le32_to_cpu(data)); + } +} + +static void pci1WriteConfigReg(unsigned int offset, + struct pci_dev *device, unsigned int data) +{ + unsigned int DataForRegCf8; + + DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | + (PCI_FUNC(device->devfn) << 8) | + (offset & ~0x3)) | 0x80000000; + /* There is a latency problem + with trying to read immediately after setting up the address + register. The "if" check gives enough time for the address + to stabilize, so the WRITE can work. + */ + if (PCI_SLOT(device->devfn) == SELF) { /* This board */ + /* when configurating our own PCI 1 L-unit the access is through + the PCI 0 interface with reg number = reg number + 0x80 */ + DataForRegCf8 |= 0x80; + GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); + } else { /* configuration Transaction over the pci. */ + /* The PCI is working in LE Mode so swap the Data. */ + GT_WRITE(GT_PCI1_CFGADDR_OFS, DataForRegCf8); + } + if (PCI_SLOT(device->devfn) == SELF) { /* This board */ + GT_WRITE(GT_PCI0_CFGDATA_OFS, data); + } else { /* configuration Transaction over the pci. */ + GT_WRITE(GT_PCI1_CFGADDR_OFS, le32_to_cpu(data)); + } +} + + +/* + * galileo_pcibios_(read/write)_config_(dword/word/byte) - + * + * reads/write a dword/word/byte register from the configuration space + * of a device. + * + * Inputs : + * bus - bus number + * dev - device number + * offset - register offset in the configuration space + * val - value to be written / read + * + * Outputs : + * PCIBIOS_SUCCESSFUL when operation was succesfull + * PCIBIOS_DEVICE_NOT_FOUND when the bus or dev is errorneous + * PCIBIOS_BAD_REGISTER_NUMBER when accessing non aligned + */ + +static int galileo_pcibios_read_config_dword(struct pci_dev *device, + int offset, u32 * val) +{ + int dev, bus; + //DBG(KERN_INFO "rcd entry \n",offset,val); + bus = device->bus->number; + dev = PCI_SLOT(device->devfn); + + if (pci_range_ck(bus, dev)) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + if (offset & 0x3) + return PCIBIOS_BAD_REGISTER_NUMBER; + if (bus == 0) + *val = pci0ReadConfigReg(offset, device); +// if (bus == 1) *val = pci1ReadConfigReg (offset,device); + DBG(KERN_INFO "rr: rcd dev %d offset %x %x\n", dev, offset, *val); + + /* + * This is so that the upper PCI layer will get the correct return + * value if we're not attached to anything. + */ + if ((offset == 0) && (*val == 0xffffffff)) { + return PCIBIOS_DEVICE_NOT_FOUND; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int galileo_pcibios_read_config_word(struct pci_dev *device, + int offset, u16 * val) +{ + int dev, bus; + + bus = device->bus->number; + dev = PCI_SLOT(device->devfn); + + if (pci_range_ck(bus, dev)) { + *val = 0xffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + if (offset & 0x1) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (bus == 0) + *val = + (unsigned short) (pci0ReadConfigReg(offset, device) >> + ((offset & ~0x3) * 8)); +// if (bus == 1) *val = (unsigned short) (pci1ReadConfigReg(offset,device) >> ((offset & ~0x3) * 8)); + + DBG(KERN_INFO "rr: rcw dev %d offset %x %x\n", dev, offset, *val); + + return PCIBIOS_SUCCESSFUL; +} + +static int galileo_pcibios_read_config_byte(struct pci_dev *device, + int offset, u8 * val) +{ + int dev, bus; + + bus = device->bus->number; + dev = PCI_SLOT(device->devfn); + + if (pci_range_ck(bus, dev)) { + *val = 0xff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + if (bus == 0) + *val = + (unsigned char) (pci0ReadConfigReg(offset, device) >> + ((offset & ~0x3) * 8)); +// if (bus == 1) *val = (unsigned char) (pci1ReadConfigReg(offset,device) >> ((offset & ~0x3) * 8)); + + DBG(KERN_INFO "rr: rcb dev %d offset %x %x\n", dev, offset, *val); + + /* This is so that the upper PCI layer will get the correct return value if + we're not attached to anything. */ + if ((offset == 0xe) && (*val == 0xff)) { + u32 MasterAbort; + GT_READ(GT_INTRCAUSE_OFS, &MasterAbort); + if (MasterAbort & 0x40000) { + DBG(KERN_INFO "PCI Master Abort, ICR %x\n", + MasterAbort); + GT_WRITE(GT_INTRCAUSE_OFS, + (MasterAbort & 0xfffbffff)); + return PCIBIOS_DEVICE_NOT_FOUND; + } + } + + return PCIBIOS_SUCCESSFUL; +} + +static int galileo_pcibios_write_config_dword(struct pci_dev *device, + int offset, u32 val) +{ + int dev, bus; + + bus = device->bus->number; + dev = PCI_SLOT(device->devfn); + + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + if (offset & 0x3) + return PCIBIOS_BAD_REGISTER_NUMBER; + if (bus == 0) + pci0WriteConfigReg(offset, device, val); +// if (bus == 1) pci1WriteConfigReg (offset,device,val); + + DBG(KERN_INFO "rr: wcd dev %d, offset %x, val %x\n", dev, offset, + val); + return PCIBIOS_SUCCESSFUL; +} + + +static int galileo_pcibios_write_config_word(struct pci_dev *device, + int offset, u16 val) +{ + int dev, bus; + unsigned long tmp; + + bus = device->bus->number; + dev = PCI_SLOT(device->devfn); + + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + if (offset & 0x1) + return PCIBIOS_BAD_REGISTER_NUMBER; + if (bus == 0) + tmp = pci0ReadConfigReg(offset, device); +// if (bus == 1) tmp = pci1ReadConfigReg (offset,device); + + if ((offset % 4) == 0) + tmp = (tmp & 0xffff0000) | (val & 0xffff); + if ((offset % 4) == 2) + tmp = (tmp & 0x0000ffff) | ((val & 0xffff) << 16); + + if (bus == 0) + pci0WriteConfigReg(offset, device, tmp); +// if (bus == 1) pci1WriteConfigReg (offset,device,tmp); + DBG(KERN_INFO "rr: wcw dev %d, offset %x, val %x\n", dev, offset, + val); + return PCIBIOS_SUCCESSFUL; +} + +static int galileo_pcibios_write_config_byte(struct pci_dev *device, + int offset, u8 val) +{ + int dev, bus; + unsigned long tmp; + + bus = device->bus->number; + dev = PCI_SLOT(device->devfn); + + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + if (bus == 0) + tmp = pci0ReadConfigReg(offset, device); +// if (bus == 1) tmp = pci1ReadConfigReg (offset,device); + + if ((offset % 4) == 0) + tmp = (tmp & 0xffffff00) | (val & 0xff); + if ((offset % 4) == 1) + tmp = (tmp & 0xffff00ff) | ((val & 0xff) << 8); + if ((offset % 4) == 2) + tmp = (tmp & 0xff00ffff) | ((val & 0xff) << 16); + if ((offset % 4) == 3) + tmp = (tmp & 0x00ffffff) | ((val & 0xff) << 24); + + if (bus == 0) + pci0WriteConfigReg(offset, device, tmp); +// if (bus == 1) pci1WriteConfigReg (offset,device,tmp); + DBG(KERN_INFO "rr: wcb dev %d, offset %x, val %x\n", dev, offset, + val); + + return PCIBIOS_SUCCESSFUL; +} + +static void galileo_pcibios_set_master(struct pci_dev *dev) +{ + u16 cmd; + + DBG(KERN_INFO "rr: galileo_pcibios_set_master\n"); + + galileo_pcibios_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + galileo_pcibios_write_config_word(dev, PCI_COMMAND, cmd); + DBG("PCI: Enabling device %s (%04x)\n", dev->slot_name, cmd); +} + +/* Externally-expected functions. Do not change function names */ + +int pcibios_enable_resources(struct pci_dev *dev) +{ + u16 cmd, old_cmd; + u16 tmp; + u8 tmp1; + int idx; + struct resource *r; + + DBG(KERN_INFO "rr: pcibios_enable_resources\n"); + + galileo_pcibios_read_config_word(dev, PCI_COMMAND, &cmd); + old_cmd = cmd; + for (idx = 0; idx < 6; idx++) { + r = &dev->resource[idx]; + DBG(KERN_INFO + "rr: BAR %d, start %lx, end %lx, flags %lx\n", idx, + r->start, r->end, r->flags); + if (!r->start && r->end) { + printk(KERN_ERR + "PCI: Device %s not available because of resource collisions\n", + dev->slot_name); + return -EINVAL; + } + if (r->flags & IORESOURCE_IO) + cmd |= PCI_COMMAND_IO; + if (r->flags & IORESOURCE_MEM) + cmd |= PCI_COMMAND_MEMORY; + } + if (cmd != old_cmd) { + DBG(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n", + dev->slot_name, old_cmd, cmd); + galileo_pcibios_write_config_word(dev, PCI_COMMAND, cmd); + } + + /* + Let's fix up the latency timer and cache line size here. Cache line size = + 32 bytes / sizeof dword (4) = 8. + Latency timer must be > 8. 32 is random but appears to work. + */ + galileo_pcibios_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp1); + if (tmp1 != 8) { + DBG(KERN_INFO + "rr: PCI setting cache line size to 8 from %d\n", + tmp1); + galileo_pcibios_write_config_byte(dev, PCI_CACHE_LINE_SIZE, + 8); + } + galileo_pcibios_read_config_byte(dev, PCI_LATENCY_TIMER, &tmp1); + if (tmp1 < 32) { + DBG(KERN_INFO + "rr: PCI setting latency timer to 32 from %d\n", tmp1); + galileo_pcibios_write_config_byte(dev, PCI_LATENCY_TIMER, + 32); + } + + return 0; +} + +int pcibios_enable_device(struct pci_dev *dev, int mask) +{ + DBG(KERN_INFO "rr: pcibios_enable_device\n"); + return pcibios_enable_resources(dev); +} + +void pcibios_align_resource(void *data, struct resource *res, + unsigned long size, unsigned long align) +{ + if (res->flags & IORESOURCE_IO) { + unsigned long start = res->start; + + /* We need to avoid collisions with `mirrored' VGA ports + and other strange ISA hardware, so we always want the + addresses kilobyte aligned. */ + if (size > 0x100) { + DBG(KERN_ERR "PCI: I/O Region %s/%d too large" + " (%ld bytes)\n", dev->slot_name, + dev->resource - res, size); + } + + start = (start + 1024 - 1) & ~(1024 - 1); + res->start = start; + } +} + +/* + * structure galileo_pci_ops + * + * This structure holds the pointers for the PCI configuration space + * access, and the fixup for the interrupts. + * This structure is registered to the operating system in boot time + */ +struct pci_ops galileo_pci_ops = { + galileo_pcibios_read_config_byte, + galileo_pcibios_read_config_word, + galileo_pcibios_read_config_dword, + galileo_pcibios_write_config_byte, + galileo_pcibios_write_config_word, + galileo_pcibios_write_config_dword +}; + +/* + * galileo_pcibios_fixup_bus - + * + * After detecting all agents over the PCI , this function is called + * in order to give an interrupt number for each PCI device starting + * from IRQ 20. It does also enables master for each device. + * + * Inputs : + * mem_start , mem_end are not relevant in MIPS architecture. + * + * Outpus : + * return always mem_start + */ +static void __devinit galileo_pcibios_fixup_bus(struct pci_bus *bus) +{ + unsigned int Current_IRQ = 20; + struct pci_bus *current_bus = bus; + struct pci_dev *devices; + struct list_head *devices_link; + + list_for_each(devices_link, &(current_bus->devices)) { + devices = pci_dev_b(devices_link); + if (devices != NULL) { + devices->irq = Current_IRQ++; + + /* Assign an interrupt number for the device */ + galileo_pcibios_write_config_byte(devices, + PCI_INTERRUPT_LINE, + Current_IRQ); + galileo_pcibios_set_master(devices); + + } + } + +} + +struct pci_fixup pcibios_fixups[] = { +// { PCI_FIXUP_HEADER, 0x4620, 0x11ab, galileo_pcibios_fixup }, + {0} +}; + +void __devinit pcibios_fixup_bus(struct pci_bus *c) +{ + DBG(KERN_INFO "rr: pcibios_fixup_bus\n"); + galileo_pcibios_fixup_bus(c); +} + +/* + * This code was derived from Galileo Technology's example + * and significantly reworked. + * + * This is very simple. It does not scan multiple function devices. It does + * not scan behind bridges. Those would be simple to implement, but we don't + * currently need this. + */ +static void __init scan_and_initialize_pci(void) +{ + struct pci_device pci_devices[MAX_PCI_DEVS]; + + if (scan_pci_bus(pci_devices)) { + allocate_pci_space(pci_devices); + } +} + +/* + * This is your basic PCI scan. It goes through each slot and checks to + * see if there's something that responds. If so, then get the size and + * type of each of the responding BARs. Save them for later. + */ + +static u32 __init scan_pci_bus(struct pci_device *pci_devices) +{ + u32 arrayCounter = 0; + u32 memType; + u32 memSize; + u32 pci_slot, bar; + u32 id; + u32 c18RegValue; + struct pci_dev device; + + DBG(KERN_INFO "rr: scan_pci_bus\n"); + + /* + According to PCI REV 2.1 MAX agents on the bus are 21. + We don't bother scanning ourselves (slot 0). + */ + for (pci_slot = 1; pci_slot < 22; pci_slot++) { + + device.devfn = PCI_DEVFN(pci_slot, 0); + id = pci0ReadConfigReg(PCI_VENDOR_ID, &device); + + /* Check for a PCI Master Abort (nothing responds in the slot) */ + GT_READ(GT_INTRCAUSE_OFS, &c18RegValue); + /* Clearing bit 18 of in the Cause Register 0xc18 by writting 0. */ + GT_WRITE(GT_INTRCAUSE_OFS, (c18RegValue & 0xfffbffff)); + if ((id != 0xffffffff) && !(c18RegValue & 0x40000)) { + DBG(KERN_INFO "rr: found device %x, slot %d\n", id, + pci_slot); + pci_devices[arrayCounter].slot = pci_slot; + for (bar = 0; bar < 6; bar++) { + memType = + pci0ReadConfigReg(PCI_BASE_ADDRESS_0 + + (bar * 4), &device); + pci_devices[arrayCounter].BARtype[bar] = + memType & 1; + pci0WriteConfigReg(PCI_BASE_ADDRESS_0 + + (bar * 4), &device, + 0xffffffff); + memSize = + pci0ReadConfigReg(PCI_BASE_ADDRESS_0 + + (bar * 4), &device); + if (memType & 1) { /* IO space */ + pci_devices[arrayCounter]. + BARsize[bar] = + ~(memSize & 0xfffffffc) + 1; + } else { /* memory space */ + pci_devices[arrayCounter]. + BARsize[bar] = + ~(memSize & 0xfffffff0) + 1; + } + DBG(KERN_INFO + "rr: BAR %d, type %d, size %x\n", bar, + (memType & 1), + pci_devices[arrayCounter]. + BARsize[bar]); + } /* BAR counter */ + + arrayCounter++; + } + /* found a device */ + } /* slot counter */ + + DBG(KERN_INFO "rr: found %d devices\n", arrayCounter); + if (arrayCounter < MAX_PCI_DEVS) { + pci_devices[arrayCounter].slot = -1; + } + return (arrayCounter); +} + +#define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1)) +#define MAX(val1, val2) ((val1) > (val2) ? (val1) : (val2)) + +/* + * This function goes through the list of devices and allocates the BARs in + * either IO or MEM space. It does it in order of size, which will limit the + * amount of fragmentation we have in the IO and MEM spaces. + */ + +static void __init allocate_pci_space(struct pci_device *pci_devices) +{ + u32 count, maxcount, bar; + u32 maxSize, maxDevice, maxBAR; + u32 alignto; + u32 base; + u32 pci0_mem_base = pci0GetMemory0Base(); + u32 pci0_io_base = pci0GetIOspaceBase(); + struct pci_dev device; + + DBG(KERN_INFO "rr: allocate_pci_space\n"); + + DBG(KERN_INFO "pci0_io_base %x\n", pci0_io_base); + DBG(KERN_INFO "pci0_mem_base %x\n", pci0_mem_base); + + /* How many PCI devices do we have? */ + maxcount = MAX_PCI_DEVS; + for (count = 0; count < MAX_PCI_DEVS; count++) { + if (pci_devices[count].slot == -1) { + maxcount = count; + break; + } + } + +// DBG(KERN_INFO "Found %d devices\n", maxcount); + + do { + /* Find the largest size BAR we need to allocate */ + maxSize = 0; + for (count = 0; count < maxcount; count++) { + for (bar = 0; bar < 6; bar++) { + if (pci_devices[count].BARsize[bar] > + maxSize) { + maxSize = + pci_devices[count]. + BARsize[bar]; + maxDevice = count; + maxBAR = bar; + } + } + } + + /* + We've found the largest BAR. Allocate it into IO or + mem space. We don't idiot check the bases to make + sure they haven't overflowed the current size for that aperture. + + Don't bother to enable the device's IO or MEM space here. That will + be done in pci_enable_resources if the device is activated by a driver. + */ + if (maxSize) { + device.devfn = + PCI_DEVFN(pci_devices[maxDevice].slot, 0); + if (pci_devices[maxDevice].BARtype[maxBAR] == 1) { + alignto = MAX(0x1000, maxSize); + base = ALIGN(pci0_io_base, alignto); + pci0WriteConfigReg(PCI_BASE_ADDRESS_0 + + (maxBAR * 4), &device, + base | 0x1); + pci0_io_base = base + alignto; + DBG(KERN_INFO + "Device %d BAR %d address %x\n", + pci_devices[maxDevice].slot, maxBAR, + base); + DBG(KERN_INFO "New IO base %x\n", + pci0_io_base); + } else { + alignto = MAX(0x1000, maxSize); + base = ALIGN(pci0_mem_base, alignto); + pci0WriteConfigReg(PCI_BASE_ADDRESS_0 + + (maxBAR * 4), &device, + base); + pci0_mem_base = base + alignto; + DBG(KERN_INFO + "Device %d BAR %d address %x\n", + pci_devices[maxDevice].slot, maxBAR, + base); + DBG(KERN_INFO "New mem base %x\n", + pci0_mem_base); + } + /* + This entry is finished. Remove it from the list we'll scan. + */ + pci_devices[maxDevice].BARsize[maxBAR] = 0; + } + } while (maxSize); +} + +unsigned __init int pcibios_assign_all_busses(void) +{ + return 1; +} + +static int __init pcibios_init(void) +{ + + u32 tmp; + struct pci_dev controller; + + controller.devfn = SELF; + + DBG(KERN_INFO "rr: pcibios_init\n"); + GT_READ(GT_PCI0_CMD_OFS, &tmp); + DBG(KERN_INFO "rr: PCI0 command - %x\n", tmp); + GT_READ(GT_PCI0_BARE_OFS, &tmp); + DBG(KERN_INFO "rr: BAR0 - %x\n", tmp); + + /* + * You have to enable bus mastering to configure any other + * card on the bus. + */ + tmp = pci0ReadConfigReg(PCI_COMMAND, &controller); + DBG(KERN_INFO "rr: command/status - %x\n", tmp); + tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; + DBG(KERN_INFO "rr: new command/status - %x\n", tmp); + pci0WriteConfigReg(PCI_COMMAND, &controller, tmp); + + /* This scans the PCI bus and sets up initial values. */ + scan_and_initialize_pci(); + + /* + * Reset PCI I/O and PCI MEM values to ones supported by EVM. + */ + ioport_resource.start = 0x10000000; + ioport_resource.end = 0x11ffffff; /* 32 MB */ + iomem_resource.start = 0x12000000; + iomem_resource.end = 0x13ffffff; /* 32 MB */ + + pci_scan_bus(0, &galileo_pci_ops, NULL); + + return 0; +} + +subsys_initcall(pcibios_init); + +char *pcibios_setup(char *str) +{ + printk(KERN_INFO "rr: pcibios_setup\n"); + /* Nothing to do for now. */ + + return str; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/ops-ev96100.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,264 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Galileo EV96100 board specific pci support. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/generic/pci.c + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include + +#include +#include +#include +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#undef DEBUG + +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +#define GT_PCI_MEM_BASE 0x12000000 +#define GT_PCI_MEM_SIZE 0x02000000 +#define GT_PCI_IO_BASE 0x10000000 +#define GT_PCI_IO_SIZE 0x02000000 +static struct resource pci_io_resource = { + "io pci IO space", + 0x10000000, + 0x10000000 + 0x02000000, + IORESOURCE_IO +}; + +static struct resource pci_mem_resource = { + "ext pci memory space", + 0x12000000, + 0x12000000 + 0x02000000, + IORESOURCE_MEM +}; + +extern struct pci_ops gt96100_pci_ops; + +struct pci_channel mips_pci_channels[] = { + {>96100_pci_ops, &pci_io_resource, &pci_mem_resource, 1, 0xff}, + {NULL, NULL, NULL, NULL, NULL} +}; + +int +static gt96100_config_access(unsigned char access_type, + struct pci_dev *dev, unsigned char where, + u32 * data) +{ + unsigned char bus = dev->bus->number; + unsigned char dev_fn = dev->devfn; + u32 intr; + + + if ((bus == 0) && (dev_fn >= PCI_DEVFN(31, 0))) { + return -1; /* Because of a bug in the galileo (for slot 31). */ + } + + /* Clear cause register bits */ + GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | + GT_INTRCAUSE_TARABORT0_BIT)); + + /* Setup address */ + GT_WRITE(GT_PCI0_CFGADDR_OFS, + (bus << GT_PCI0_CFGADDR_BUSNUM_SHF) | + (dev_fn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | + ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | + GT_PCI0_CFGADDR_CONFIGEN_BIT); + udelay(2); + + + if (access_type == PCI_ACCESS_WRITE) { + if (dev_fn != 0) { + *data = le32_to_cpu(*data); + } + GT_WRITE(GT_PCI0_CFGDATA_OFS, *data); + } else { + GT_READ(GT_PCI0_CFGDATA_OFS, *data); + if (dev_fn != 0) { + *data = le32_to_cpu(*data); + } + } + + udelay(2); + + /* Check for master or target abort */ + GT_READ(GT_INTRCAUSE_OFS, intr); + + if (intr & + (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) { + //printk("config access error: %x:%x\n", dev_fn,where); + /* Error occured */ + + /* Clear bits */ + GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | + GT_INTRCAUSE_TARABORT0_BIT)); + + if (access_type == PCI_ACCESS_READ) { + *data = 0xffffffff; + } + return -1; + } + return 0; +} + + +/* + * We can't address 8 and 16 bit words directly. Instead we have to + * read/write a 32bit word and mask/modify the data we actually want. + */ +static int read_config_byte(struct pci_dev *dev, int where, u8 * val) +{ + u32 data = 0; + + if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data)) { + *val = 0xff; + return -1; + } + + *val = (data >> ((where & 3) << 3)) & 0xff; + DBG("cfg read byte: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, *val); + + return PCIBIOS_SUCCESSFUL; +} + + +static int read_config_word(struct pci_dev *dev, int where, u16 * val) +{ + u32 data = 0; + + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data)) { + *val = 0xffff; + return -1; + } + + *val = (data >> ((where & 3) << 3)) & 0xffff; + DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, *val); + + return PCIBIOS_SUCCESSFUL; +} + +static int read_config_dword(struct pci_dev *dev, int where, u32 * val) +{ + u32 data = 0; + + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data)) { + *val = 0xffffffff; + return -1; + } + + *val = data; + DBG("cfg read dword: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, *val); + + return PCIBIOS_SUCCESSFUL; +} + + +static int write_config_byte(struct pci_dev *dev, int where, u8 val) +{ + u32 data = 0; + + if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data)) + return -1; + + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + DBG("cfg write byte: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, val); + + if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +static int write_config_word(struct pci_dev *dev, int where, u16 val) +{ + u32 data = 0; + + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (gt96100_config_access(PCI_ACCESS_READ, dev, where, &data)) + return -1; + + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + DBG("cfg write word: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, val); + + if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &data)) + return -1; + + + return PCIBIOS_SUCCESSFUL; +} + +static int write_config_dword(struct pci_dev *dev, int where, u32 val) +{ + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &val)) + return -1; + DBG("cfg write dword: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, val); + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops gt96100_pci_ops = { + read_config_byte, + read_config_word, + read_config_dword, + write_config_byte, + write_config_word, + write_config_dword +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/ops-it8172.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,219 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * IT8172 system controller specific pci support. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include + +#include +#include +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#undef DEBUG +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +static struct resource pci_mem_resource_1; + +static struct resource pci_io_resource = { + "io pci IO space", + 0x14018000, + 0x17FFFFFF, + IORESOURCE_IO +}; + +static struct resource pci_mem_resource_0 = { + "ext pci memory space 0/1", + 0x10101000, + 0x13FFFFFF, + IORESOURCE_MEM, + &pci_mem_resource_0, + NULL, + &pci_mem_resource_1 +}; + +static struct resource pci_mem_resource_1 = { + "ext pci memory space 2/3", + 0x1A000000, + 0x1FBFFFFF, + IORESOURCE_MEM, + &pci_mem_resource_0, + NULL, + NULL +}; + +extern struct pci_ops it8172_pci_ops; + +struct pci_channel mips_pci_channels[] = { + {&it8172_pci_ops, &pci_io_resource, &pci_mem_resource_0, 0x10, + 0xff}, + {NULL, NULL, NULL, NULL, NULL} +}; + +static int it8172_pcibios_config_access(unsigned char access_type, + struct pci_bus *bus, + unsigned int devfn, int where, + u32 * data) +{ + /* + * config cycles are on 4 byte boundary only + */ + + /* Setup address */ + IT_WRITE(IT_CONFADDR, (bus->number << IT_BUSNUM_SHF) | + (devfn << IT_FUNCNUM_SHF) | (where & ~0x3)); + + if (access_type == PCI_ACCESS_WRITE) { + IT_WRITE(IT_CONFDATA, *data); + } else { + IT_READ(IT_CONFDATA, *data); + } + + /* + * Revisit: check for master or target abort. + */ + return 0; +} + + +/* + * We can't address 8 and 16 bit words directly. Instead we have to + * read/write a 32bit word and mask/modify the data we actually want. + */ +static write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 val) +{ + u32 data = 0; + + switch (size) { + case 1: + if (it8172_pcibios_config_access + (PCI_ACCESS_READ, dev, where, &data)) + return -1; + + *val = (data >> ((where & 3) << 3)) & 0xff; + + return PCIBIOS_SUCCESSFUL; + + case 2: + + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (it8172_pcibios_config_access + (PCI_ACCESS_READ, dev, where, &data)) + return -1; + + *val = (data >> ((where & 3) << 3)) & 0xffff; + DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, *val); + + return PCIBIOS_SUCCESSFUL; + + case 4: + + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (it8172_pcibios_config_access + (PCI_ACCESS_READ, dev, where, &data)) + return -1; + + *val = data; + + return PCIBIOS_SUCCESSFUL; + } +} + + +static write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 val) +{ + u32 data = 0; + + switch (size) { + case 1: + if (it8172_pcibios_config_access + (PCI_ACCESS_READ, dev, where, &data)) + return -1; + + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (it8172_pcibios_config_access + (PCI_ACCESS_WRITE, dev, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; + + case 2: + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (it8172_pcibios_config_access + (PCI_ACCESS_READ, dev, where, &data)) + eturn - 1; + + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (it8172_pcibios_config_access + (PCI_ACCESS_WRITE, dev, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; + + case 4: + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (it8172_pcibios_config_access + (PCI_ACCESS_WRITE, dev, where, &val)) + return -1; + + return PCIBIOS_SUCCESSFUL; + } +} + +struct pci_ops it8172_pci_ops = { + .read = read_config, + .write = write_config, +}; + +unsigned __init int pcibios_assign_all_busses(void) +{ + return 1; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/ops-jmr3927.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,491 @@ +/*********************************************************************** + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c + * + * Define the pci_ops for JMR3927. + * + * Much of the code is derived from the original DDB5074 port by + * Geert Uytterhoeven + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include + +#include +#include +#include +#include + +struct resource pci_io_resource = { + "pci IO space", + 0x1000, /* reserve regacy I/O space */ + 0x1000 + JMR3927_PCIIO_SIZE - 1, + IORESOURCE_IO +}; + +struct resource pci_mem_resource = { + "pci memory space", + JMR3927_PCIMEM, + JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1, + IORESOURCE_MEM +}; + +extern struct pci_ops jmr3927_pci_ops; + +struct pci_channel mips_pci_channels[] = { + {&jmr3927_pci_ops, &pci_io_resource, &pci_mem_resource, 0, 0xff}, + {NULL, NULL, NULL, NULL, NULL} +}; + +unsigned int pcibios_assign_all_busses(void) +{ + return 1; +} + +static int +mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where, + int *flagsp) +{ + if (bus == 0 && dev_fn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0)) + return -1; + + tx3927_pcicptr->ica = ((bus & 0xff) << 0x10) | + ((dev_fn & 0xff) << 0x08) | (where & 0xfc); + /* clear M_ABORT and Disable M_ABORT Int. */ + tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT; + tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT; + return 0; +} + +static int check_abort(int flags) +{ + int code = PCIBIOS_SUCCESSFUL; + if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) { + tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT; + tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT; + code = PCIBIOS_DEVICE_NOT_FOUND; + } + return code; +} + +/* + * We can't address 8 and 16 bit words directly. Instead we have to + * read/write a 32bit word and mask/modify the data we actually want. + */ +static int jmr3927_pcibios_read_config_byte(struct pci_dev *dev, + int where, unsigned char *val) +{ + int flags; + unsigned char bus, func_num; + + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + func_num = PCI_FUNC(dev->devfn); + if (mkaddr(bus, dev->devfn, where, &flags)) + return -1; + *val = + *(volatile u8 *) ((ulong) & tx3927_pcicptr->icd | (where & 3)); + return check_abort(flags); +} + +static int jmr3927_pcibios_read_config_word(struct pci_dev *dev, + int where, unsigned short *val) +{ + int flags; + unsigned char bus, func_num; + + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + func_num = PCI_FUNC(dev->devfn); + if (mkaddr(bus, dev->devfn, where, &flags)) + return -1; + *val = + le16_to_cpu(*(volatile u16 *) + ((ulong) & tx3927_pcicptr->icd | (where & 3))); + return check_abort(flags); +} + +static int jmr3927_pcibios_read_config_dword(struct pci_dev *dev, + int where, unsigned int *val) +{ + int flags; + unsigned char bus, func_num; + + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + func_num = PCI_FUNC(dev->devfn); + if (mkaddr(bus, dev->devfn, where, &flags)) + return -1; + *val = le32_to_cpu(tx3927_pcicptr->icd); + return check_abort(flags); +} + +static int jmr3927_pcibios_write_config_byte(struct pci_dev *dev, + int where, unsigned char val) +{ + int flags; + unsigned char bus, func_num; + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + func_num = PCI_FUNC(dev->devfn); + if (mkaddr(bus, dev->devfn, where, &flags)) + return -1; + *(volatile u8 *) ((ulong) & tx3927_pcicptr->icd | (where & 3)) = + val; + return check_abort(flags); +} + +static int jmr3927_pcibios_write_config_word(struct pci_dev *dev, + int where, unsigned short val) +{ + int flags; + unsigned char bus, func_num; + + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + func_num = PCI_FUNC(dev->devfn); + if (mkaddr(bus, dev->devfn, where, &flags)) + return -1; + *(volatile u16 *) ((ulong) & tx3927_pcicptr->icd | (where & 3)) = + cpu_to_le16(val); + return check_abort(flags); +} + +static int jmr3927_pcibios_write_config_dword(struct pci_dev *dev, + int where, unsigned int val) +{ + int flags; + unsigned char bus, func_num; + + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + func_num = PCI_FUNC(dev->devfn); + if (mkaddr(bus, dev->devfn, where, &flags)) + return -1; + tx3927_pcicptr->icd = cpu_to_le32(val); + return check_abort(flags); +} +struct pci_ops jmr3927_pci_ops = { + jmr3927_pcibios_read_config_byte, + jmr3927_pcibios_read_config_word, + jmr3927_pcibios_read_config_dword, + jmr3927_pcibios_write_config_byte, + jmr3927_pcibios_write_config_word, + jmr3927_pcibios_write_config_dword +}; + +#ifndef JMR3927_INIT_INDIRECT_PCI +inline unsigned long tc_readl(volatile __u32 * addr) +{ + return readl(addr); +} +inline void tc_writel(unsigned long data, volatile __u32 * addr) +{ + writel(data, addr); +} +#else +unsigned long tc_readl(volatile __u32 * addr) +{ + unsigned long val; + + addr = PHYSADDR(addr); + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) addr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = + (PCI_IPCIBE_ICMD_MEMREAD << PCI_IPCIBE_ICMD_SHIFT) | + PCI_IPCIBE_IBE_LONG; + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); + val = + le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr-> + ipcidata); + /* clear by setting */ + tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; + return val; +} +void tc_writel(unsigned long data, volatile __u32 * addr) +{ + addr = PHYSADDR(addr); + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = + cpu_to_le32(data); + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) addr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = + (PCI_IPCIBE_ICMD_MEMWRITE << PCI_IPCIBE_ICMD_SHIFT) | + PCI_IPCIBE_IBE_LONG; + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); + /* clear by setting */ + tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; +} +unsigned char tx_ioinb(unsigned char *addr) +{ + unsigned long val; + __u32 ioaddr; + int offset; + int byte; + + ioaddr = (unsigned long) addr; + offset = ioaddr & 0x3; + if (offset == 0) + byte = 0x7; + else if (offset == 1) + byte = 0xb; + else if (offset == 2) + byte = 0xd; + else if (offset == 3) + byte = 0xe; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) ioaddr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = + (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte; + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); + val = + le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr-> + ipcidata); + val = val & 0xff; + /* clear by setting */ + tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; + return val; +} +void tx_iooutb(unsigned long data, unsigned char *addr) +{ + __u32 ioaddr; + int offset; + int byte; + + data = data | (data << 8) | (data << 16) | (data << 24); + ioaddr = (unsigned long) addr; + offset = ioaddr & 0x3; + if (offset == 0) + byte = 0x7; + else if (offset == 1) + byte = 0xb; + else if (offset == 2) + byte = 0xd; + else if (offset == 3) + byte = 0xe; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = data; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) ioaddr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = + (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte; + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); + /* clear by setting */ + tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; +} +unsigned short tx_ioinw(unsigned short *addr) +{ + unsigned long val; + __u32 ioaddr; + int offset; + int byte; + + ioaddr = (unsigned long) addr; + offset = ioaddr & 0x3; + if (offset == 0) + byte = 0x3; + else if (offset == 2) + byte = 0xc; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) ioaddr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = + (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte; + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); + val = + le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr-> + ipcidata); + val = val & 0xffff; + /* clear by setting */ + tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; + return val; + +} +void tx_iooutw(unsigned long data, unsigned short *addr) +{ + __u32 ioaddr; + int offset; + int byte; + + data = data | (data << 16); + ioaddr = (unsigned long) addr; + offset = ioaddr & 0x3; + if (offset == 0) + byte = 0x3; + else if (offset == 2) + byte = 0xc; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = data; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) ioaddr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = + (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte; + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); + /* clear by setting */ + tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; +} +unsigned long tx_ioinl(unsigned int *addr) +{ + unsigned long val; + __u32 ioaddr; + + ioaddr = (unsigned long) addr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) ioaddr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = + (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | + PCI_IPCIBE_IBE_LONG; + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); + val = + le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr-> + ipcidata); + /* clear by setting */ + tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; + return val; +} +void tx_iooutl(unsigned long data, unsigned int *addr) +{ + __u32 ioaddr; + + ioaddr = (unsigned long) addr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = + cpu_to_le32(data); + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr = + (unsigned long) ioaddr; + *(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe = + (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | + PCI_IPCIBE_IBE_LONG; + while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC)); + /* clear by setting */ + tx3927_pcicptr->istat |= PCI_ISTAT_IDICC; +} +void tx_insbyte(unsigned char *addr, void *buffer, unsigned int count) +{ + unsigned char *ptr = (unsigned char *) buffer; + + while (count--) { + *ptr++ = tx_ioinb(addr); + } +} +void tx_insword(unsigned short *addr, void *buffer, unsigned int count) +{ + unsigned short *ptr = (unsigned short *) buffer; + + while (count--) { + *ptr++ = tx_ioinw(addr); + } +} +void tx_inslong(unsigned int *addr, void *buffer, unsigned int count) +{ + unsigned long *ptr = (unsigned long *) buffer; + + while (count--) { + *ptr++ = tx_ioinl(addr); + } +} +void tx_outsbyte(unsigned char *addr, void *buffer, unsigned int count) +{ + unsigned char *ptr = (unsigned char *) buffer; + + while (count--) { + tx_iooutb(*ptr++, addr); + } +} +void tx_outsword(unsigned short *addr, void *buffer, unsigned int count) +{ + unsigned short *ptr = (unsigned short *) buffer; + + while (count--) { + tx_iooutw(*ptr++, addr); + } +} +void tx_outslong(unsigned int *addr, void *buffer, unsigned int count) +{ + unsigned long *ptr = (unsigned long *) buffer; + + while (count--) { + tx_iooutl(*ptr++, addr); + } +} +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/ops-ocelot.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,1056 @@ +/* + * BRIEF MODULE DESCRIPTION + * Galileo Evaluation Boards PCI support. + * + * The general-purpose functions to read/write and configure the GT64120A's + * PCI registers (function names start with pci0 or pci1) are either direct + * copies of functions written by Galileo Technology, or are modifications + * of their functions to work with Linux 2.4 vs Linux 2.2. These functions + * are Copyright - Galileo Technology. + * + * Other functions are derived from other MIPS PCI implementations, or were + * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define SELF 0 + +/* + * These functions and structures provide the BIOS scan and mapping of the PCI + * devices. + */ + +#define MAX_PCI_DEVS 10 + +struct pci_device { + u32 slot; + u32 BARtype[6]; + u32 BARsize[6]; +}; + +static void __init scan_and_initialize_pci(void); +static u32 __init scan_pci_bus(struct pci_device *pci_devices); +static void __init allocate_pci_space(struct pci_device *pci_devices); + +/* + * The functions that actually read and write to the controller. + * + * Copied from or modified from Galileo Technology code. + */ +static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device); +static void pci0WriteConfigReg(unsigned int offset, + struct pci_dev *device, unsigned int data); +static unsigned int pci1ReadConfigReg(int offset, struct pci_dev *device); +static void pci1WriteConfigReg(unsigned int offset, + struct pci_dev *device, unsigned int data); + +static void pci0MapIOspace(unsigned int pci0IoBase, + unsigned int pci0IoLength); +static void pci1MapIOspace(unsigned int pci1IoBase, + unsigned int pci1IoLength); +static void pci0MapMemory0space(unsigned int pci0Mem0Base, + unsigned int pci0Mem0Length); +static void pci1MapMemory0space(unsigned int pci1Mem0Base, + unsigned int pci1Mem0Length); +static void pci0MapMemory1space(unsigned int pci0Mem1Base, + unsigned int pci0Mem1Length); +static void pci1MapMemory1space(unsigned int pci1Mem1Base, + unsigned int pci1Mem1Length); +static unsigned int pci0GetIOspaceBase(void); +static unsigned int pci0GetIOspaceSize(void); +static unsigned int pci0GetMemory0Base(void); +static unsigned int pci0GetMemory0Size(void); +static unsigned int pci0GetMemory1Base(void); +static unsigned int pci0GetMemory1Size(void); +static unsigned int pci1GetIOspaceBase(void); +static unsigned int pci1GetIOspaceSize(void); +static unsigned int pci1GetMemory0Base(void); +static unsigned int pci1GetMemory0Size(void); +static unsigned int pci1GetMemory1Base(void); +static unsigned int pci1GetMemory1Size(void); + + +/* Functions to implement "pci ops" */ +static int galileo_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int offset, int size, u32 * val); +static int galileo_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int offset, int size, u32 val); +static void galileo_pcibios_set_master(struct pci_dev *dev); + +/* + * General-purpose PCI functions. + */ + +/* + * pci0MapIOspace - Maps PCI0 IO space for the master. + * Inputs: base and length of pci0Io + */ + +static void pci0MapIOspace(unsigned int pci0IoBase, + unsigned int pci0IoLength) +{ + unsigned int pci0IoTop = + (unsigned int) (pci0IoBase + pci0IoLength); + + if (pci0IoLength == 0) + pci0IoTop++; + + pci0IoBase = (unsigned int) (pci0IoBase >> 21); + pci0IoTop = (unsigned int) (((pci0IoTop - 1) & 0x0fffffff) >> 21); + GT_WRITE(GT_PCI0IOLD_OFS, pci0IoBase); + GT_WRITE(GT_PCI0IOHD_OFS, pci0IoTop); +} + +/* + * pci1MapIOspace - Maps PCI1 IO space for the master. + * Inputs: base and length of pci1Io + */ + +static void pci1MapIOspace(unsigned int pci1IoBase, + unsigned int pci1IoLength) +{ + unsigned int pci1IoTop = + (unsigned int) (pci1IoBase + pci1IoLength); + + if (pci1IoLength == 0) + pci1IoTop++; + + pci1IoBase = (unsigned int) (pci1IoBase >> 21); + pci1IoTop = (unsigned int) (((pci1IoTop - 1) & 0x0fffffff) >> 21); + GT_WRITE(GT_PCI1IOLD_OFS, pci1IoBase); + GT_WRITE(GT_PCI1IOHD_OFS, pci1IoTop); +} + +/* + * pci0MapMemory0space - Maps PCI0 memory0 space for the master. + * Inputs: base and length of pci0Mem0 + */ + +static void pci0MapMemory0space(unsigned int pci0Mem0Base, + unsigned int pci0Mem0Length) +{ + unsigned int pci0Mem0Top = pci0Mem0Base + pci0Mem0Length; + + if (pci0Mem0Length == 0) + pci0Mem0Top++; + + pci0Mem0Base = pci0Mem0Base >> 21; + pci0Mem0Top = ((pci0Mem0Top - 1) & 0x0fffffff) >> 21; + GT_WRITE(GT_PCI0M0LD_OFS, pci0Mem0Base); + GT_WRITE(GT_PCI0M0HD_OFS, pci0Mem0Top); +} + +/* + * pci1MapMemory0space - Maps PCI1 memory0 space for the master. + * Inputs: base and length of pci1Mem0 + */ + +static void pci1MapMemory0space(unsigned int pci1Mem0Base, + unsigned int pci1Mem0Length) +{ + unsigned int pci1Mem0Top = pci1Mem0Base + pci1Mem0Length; + + if (pci1Mem0Length == 0) + pci1Mem0Top++; + + pci1Mem0Base = pci1Mem0Base >> 21; + pci1Mem0Top = ((pci1Mem0Top - 1) & 0x0fffffff) >> 21; + GT_WRITE(GT_PCI1M0LD_OFS, pci1Mem0Base); + GT_WRITE(GT_PCI1M0HD_OFS, pci1Mem0Top); +} + +/* + * pci0MapMemory1space - Maps PCI0 memory1 space for the master. + * Inputs: base and length of pci0Mem1 + */ + +static void pci0MapMemory1space(unsigned int pci0Mem1Base, + unsigned int pci0Mem1Length) +{ + unsigned int pci0Mem1Top = pci0Mem1Base + pci0Mem1Length; + + if (pci0Mem1Length == 0) + pci0Mem1Top++; + + pci0Mem1Base = pci0Mem1Base >> 21; + pci0Mem1Top = ((pci0Mem1Top - 1) & 0x0fffffff) >> 21; + GT_WRITE(GT_PCI0M1LD_OFS, pci0Mem1Base); + GT_WRITE(GT_PCI0M1HD_OFS, pci0Mem1Top); + +} + +/* + * pci1MapMemory1space - Maps PCI1 memory1 space for the master. + * Inputs: base and length of pci1Mem1 + */ + +static void pci1MapMemory1space(unsigned int pci1Mem1Base, + unsigned int pci1Mem1Length) +{ + unsigned int pci1Mem1Top = pci1Mem1Base + pci1Mem1Length; + + if (pci1Mem1Length == 0) + pci1Mem1Top++; + + pci1Mem1Base = pci1Mem1Base >> 21; + pci1Mem1Top = ((pci1Mem1Top - 1) & 0x0fffffff) >> 21; + GT_WRITE(GT_PCI1M1LD_OFS, pci1Mem1Base); + GT_WRITE(GT_PCI1M1HD_OFS, pci1Mem1Top); +} + +/* + * pci0GetIOspaceBase - Return PCI0 IO Base Address. + * Inputs: N/A + * Returns: PCI0 IO Base Address. + */ + +static unsigned int pci0GetIOspaceBase(void) +{ + unsigned int base; + GT_READ(GT_PCI0IOLD_OFS, &base); + base = base << 21; + return base; +} + +/* + * pci0GetIOspaceSize - Return PCI0 IO Bar Size. + * Inputs: N/A + * Returns: PCI0 IO Bar Size. + */ + +static unsigned int pci0GetIOspaceSize(void) +{ + unsigned int top, base, size; + GT_READ(GT_PCI0IOLD_OFS, &base); + base = base << 21; + GT_READ(GT_PCI0IOHD_OFS, &top); + top = (top << 21); + size = ((top - base) & 0xfffffff); + size = size | 0x1fffff; + return (size + 1); +} + +/* + * pci0GetMemory0Base - Return PCI0 Memory 0 Base Address. + * Inputs: N/A + * Returns: PCI0 Memory 0 Base Address. + */ + +static unsigned int pci0GetMemory0Base(void) +{ + unsigned int base; + GT_READ(GT_PCI0M0LD_OFS, &base); + base = base << 21; + return base; +} + +/* + * pci0GetMemory0Size - Return PCI0 Memory 0 Bar Size. + * Inputs: N/A + * Returns: PCI0 Memory 0 Bar Size. + */ + +static unsigned int pci0GetMemory0Size(void) +{ + unsigned int top, base, size; + GT_READ(GT_PCI0M0LD_OFS, &base); + base = base << 21; + GT_READ(GT_PCI0M0HD_OFS, &top); + top = (top << 21); + size = ((top - base) & 0xfffffff); + size = size | 0x1fffff; + return (size + 1); +} + +/* + * pci0GetMemory1Base - Return PCI0 Memory 1 Base Address. + * Inputs: N/A + * Returns: PCI0 Memory 1 Base Address. + */ + +static unsigned int pci0GetMemory1Base(void) +{ + unsigned int base; + GT_READ(GT_PCI0M1LD_OFS, &base); + base = base << 21; + return base; +} + +/* + * pci0GetMemory1Size - Return PCI0 Memory 1 Bar Size. + * Inputs: N/A + * Returns: PCI0 Memory 1 Bar Size. + */ + +static unsigned int pci0GetMemory1Size(void) +{ + unsigned int top, base, size; + GT_READ(GT_PCI0M1LD_OFS, &base); + base = base << 21; + GT_READ(GT_PCI0M1HD_OFS, &top); + top = (top << 21); + size = ((top - base) & 0xfffffff); + size = size | 0x1fffff; + return (size + 1); +} + +/* + * pci1GetIOspaceBase - Return PCI1 IO Base Address. + * Inputs: N/A + * Returns: PCI1 IO Base Address. + */ + +static unsigned int pci1GetIOspaceBase(void) +{ + unsigned int base; + GT_READ(GT_PCI1IOLD_OFS, &base); + base = base << 21; + return base; +} + +/* + * pci1GetIOspaceSize - Return PCI1 IO Bar Size. + * Inputs: N/A + * Returns: PCI1 IO Bar Size. + */ + +static unsigned int pci1GetIOspaceSize(void) +{ + unsigned int top, base, size; + GT_READ(GT_PCI1IOLD_OFS, &base); + base = base << 21; + GT_READ(GT_PCI1IOHD_OFS, &top); + top = (top << 21); + size = ((top - base) & 0xfffffff); + size = size | 0x1fffff; + return (size + 1); +} + +/* + * pci1GetMemory0Base - Return PCI1 Memory 0 Base Address. + * Inputs: N/A + * Returns: PCI1 Memory 0 Base Address. + */ + +static unsigned int pci1GetMemory0Base(void) +{ + unsigned int base; + GT_READ(GT_PCI1M0LD_OFS, &base); + base = base << 21; + return base; +} + +/* + * pci1GetMemory0Size - Return PCI1 Memory 0 Bar Size. + * Inputs: N/A + * Returns: PCI1 Memory 0 Bar Size. + */ + +static unsigned int pci1GetMemory0Size(void) +{ + unsigned int top, base, size; + GT_READ(GT_PCI1M1LD_OFS, &base); + base = base << 21; + GT_READ(GT_PCI1M1HD_OFS, &top); + top = (top << 21); + size = ((top - base) & 0xfffffff); + size = size | 0x1fffff; + return (size + 1); +} + +/* + * pci1GetMemory1Base - Return PCI1 Memory 1 Base Address. + * Inputs: N/A + * Returns: PCI1 Memory 1 Base Address. + */ + +static unsigned int pci1GetMemory1Base(void) +{ + unsigned int base; + GT_READ(GT_PCI1M1LD_OFS, &base); + base = base << 21; + return base; +} + +/* + * pci1GetMemory1Size - Return PCI1 Memory 1 Bar Size. + * Inputs: N/A + * Returns: PCI1 Memory 1 Bar Size. + */ + +static unsigned int pci1GetMemory1Size(void) +{ + unsigned int top, base, size; + GT_READ(GT_PCI1M1LD_OFS, &base); + base = base << 21; + GT_READ(GT_PCI1M1HD_OFS, &top); + top = (top << 21); + size = ((top - base) & 0xfffffff); + size = size | 0x1fffff; + return (size + 1); +} + + + +/* + * pci_range_ck - + * + * Check if the pci device that are trying to access does really exists + * on the evaluation board. + * + * Inputs : + * bus - bus number (0 for PCI 0 ; 1 for PCI 1) + * dev - number of device on the specific pci bus + * + * Outpus : + * 0 - if OK , 1 - if failure + */ +static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev) +{ + /* + * We don't even pretend to handle other busses than bus 0 correctly. + * Accessing device 31 crashes the CP7000 for some reason. + */ + if ((bus == 0) && (dev != 31)) + return 0; + return -1; +} + +/* + * pciXReadConfigReg - Read from a PCI configuration register + * - Make sure the GT is configured as a master before + * reading from another device on the PCI. + * - The function takes care of Big/Little endian conversion. + * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI + * spec) + * pciDevNum: The device number needs to be addressed. + * RETURNS: data , if the data == 0xffffffff check the master abort bit in the + * cause register to make sure the data is valid + * + * Configuration Address 0xCF8: + * + * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number + * |congif|Reserved| Bus |Device|Function|Register|00| + * |Enable| |Number|Number| Number | Number | | <=field Name + * + */ +static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device) +{ + unsigned int DataForRegCf8; + unsigned int data; + + DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | + (PCI_FUNC(device->devfn) << 8) | + (offset & ~0x3)) | 0x80000000; + GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); + + /* + * The casual observer might wonder why the READ is duplicated here, + * rather than immediately following the WRITE, and just have the swap + * in the "if". That's because there is a latency problem with trying + * to read immediately after setting up the address register. The "if" + * check gives enough time for the address to stabilize, so the READ + * can work. + */ + if (PCI_SLOT(device->devfn) == SELF) { /* This board */ + GT_READ(GT_PCI0_CFGDATA_OFS, &data); + return data; + } else { /* The PCI is working in LE Mode so swap the Data. */ + GT_READ(GT_PCI0_CFGDATA_OFS, &data); + return cpu_to_le32(data); + } +} + +static unsigned int pci1ReadConfigReg(int offset, struct pci_dev *device) +{ + unsigned int DataForRegCf8; + unsigned int data; + + DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | + (PCI_FUNC(device->devfn) << 8) | + (offset & ~0x3)) | 0x80000000; + /* + * The casual observer might wonder why the READ is duplicated here, + * rather than immediately following the WRITE, and just have the + * swap in the "if". That's because there is a latency problem + * with trying to read immediately after setting up the address + * register. The "if" check gives enough time for the address + * to stabilize, so the READ can work. + */ + if (PCI_SLOT(device->devfn) == SELF) { /* This board */ + /* when configurating our own PCI 1 L-unit the access is through + the PCI 0 interface with reg number = reg number + 0x80 */ + DataForRegCf8 |= 0x80; + GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); + } else { /* The PCI is working in LE Mode so swap the Data. */ + GT_WRITE(GT_PCI1_CFGADDR_OFS, DataForRegCf8); + } + if (PCI_SLOT(device->devfn) == SELF) { /* This board */ + GT_READ(GT_PCI0_CFGDATA_OFS, &data); + return data; + } else { + GT_READ(GT_PCI1_CFGDATA_OFS, &data); + return cpu_to_le32(data); + } +} + + + +/* + * pciXWriteConfigReg - Write to a PCI configuration register + * - Make sure the GT is configured as a master before + * writingto another device on the PCI. + * - The function takes care of Big/Little endian conversion. + * Inputs: unsigned int regOffset: The register offset as it apears in the + * GT spec + * (or any other PCI device spec) + * pciDevNum: The device number needs to be addressed. + * + * Configuration Address 0xCF8: + * + * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number + * |congif|Reserved| Bus |Device|Function|Register|00| + * |Enable| |Number|Number| Number | Number | | <=field Name + * + */ +static void pci0WriteConfigReg(unsigned int offset, + struct pci_dev *device, unsigned int data) +{ + unsigned int DataForRegCf8; + + DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | + (PCI_FUNC(device->devfn) << 8) | + (offset & ~0x3)) | 0x80000000; + GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); + if (PCI_SLOT(device->devfn) == SELF) { /* This board */ + GT_WRITE(GT_PCI0_CFGDATA_OFS, data); + } else { /* configuration Transaction over the pci. */ + /* The PCI is working in LE Mode so swap the Data. */ + GT_WRITE(GT_PCI0_CFGDATA_OFS, le32_to_cpu(data)); + } +} + +static void pci1WriteConfigReg(unsigned int offset, + struct pci_dev *device, unsigned int data) +{ + unsigned int DataForRegCf8; + + DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | + (PCI_FUNC(device->devfn) << 8) | + (offset & ~0x3)) | 0x80000000; + /* + * There is a latency problem + * with trying to read immediately after setting up the address + * register. The "if" check gives enough time for the address + * to stabilize, so the WRITE can work. + */ + if (PCI_SLOT(device->devfn) == SELF) { /* This board */ + /* + * when configurating our own PCI 1 L-unit the access is through + * the PCI 0 interface with reg number = reg number + 0x80 + */ + DataForRegCf8 |= 0x80; + GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); + } else { /* configuration Transaction over the pci. */ + /* The PCI is working in LE Mode so swap the Data. */ + GT_WRITE(GT_PCI1_CFGADDR_OFS, DataForRegCf8); + } + if (PCI_SLOT(device->devfn) == SELF) { /* This board */ + GT_WRITE(GT_PCI0_CFGDATA_OFS, data); + } else { /* configuration Transaction over the pci. */ + GT_WRITE(GT_PCI1_CFGADDR_OFS, le32_to_cpu(data)); + } +} + + +/* + * galileo_pcibios_(read/write) - + * + * reads/write a dword/word/byte register from the configuration space + * of a device. + * + * Inputs : + * bus - bus number + * devfn - device function index + * offset - register offset in the configuration space + * size - size of value (1=byte,2=word,4-dword) + * val - value to be written / read + * + * Outputs : + * PCIBIOS_SUCCESSFUL when operation was succesfull + * PCIBIOS_DEVICE_NOT_FOUND when the bus or dev is errorneous + * PCIBIOS_BAD_REGISTER_NUMBER when accessing non aligned + */ + +static int galileo_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int offset, int size, u32 * val) +{ + int dev, busnum; + + busnum = bus->number; + dev = PCI_SLOT(devfn); + + if (pci_range_ck(busnum, dev)) { + if (size == 1) + *val = (u8) 0xff; + else if (size == 2) + *val = (u16) 0xffff; + else if (size == 4) + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + if ((size == 2) && (offset & 0x1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (offset & 0x3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (busnum == 0) { + if (size == 1) { + *val = (u8) (pci0ReadConfigReg(offset, bus->dev) >> + ((offset & ~0x3) * 8)); + } else if (size == 2) { + *val = + (u16) (pci0ReadConfigReg(offset, bus->dev) >> + ((offset & ~0x3) * 8)); + } else if (size == 4) { + *val = pci0ReadConfigReg(offset, bus->dev); + } + } + + /* + * This is so that the upper PCI layer will get the correct return + * value if we're not attached to anything. + */ + switch (size) { + case 1: + if ((offset == 0xe) && (*val == (u8) 0xff)) { + u32 MasterAbort; + GT_READ(GT_INTRCAUSE_OFS, &MasterAbort); + if (MasterAbort & 0x40000) { + GT_WRITE(GT_INTRCAUSE_OFS, + (MasterAbort & 0xfffbffff)); + return PCIBIOS_DEVICE_NOT_FOUND; + } + } + break; + case 4: + if ((offset == 0) && (*val == 0xffffffff)) { + return PCIBIOS_DEVICE_NOT_FOUND; + } + break} + return PCIBIOS_SUCCESSFUL; +} + +static int galileo_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int offset, int size, u32 val) +{ + int dev, busnum; + unsigned long tmp; + + busnum = bus->number; + dev = PCI_SLOT(devfn); + + if (pci_range_ck(busnum, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + if (size == 4) { + if (offset & 0x3) + return PCIBIOS_BAD_REGISTER_NUMBER; + if (busnum == 0) + pci0WriteConfigReg(offset, bus->dev, val); + //if (busnum == 1) pci1WriteConfigReg (offset,bus->dev,val); + return PCIBIOS_SUCCESSFUL; + } + if ((size == 2) && (offset & 0x1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + if (busnum == 0) { + tmp = pci0ReadConfigReg(offset, bus->dev); + //if (busnum == 1) tmp = pci1ReadConfigReg (offset,bus->dev); + if (size == 1) { + if ((offset % 4) == 0) + tmp = + (tmp & 0xffffff00) | (val & (u8) 0xff); + if ((offset % 4) == 1) + tmp = + (tmp & 0xffff00ff) | ((val & (u8) 0xff) + << 8); + if ((offset % 4) == 2) + tmp = + (tmp & 0xff00ffff) | ((val & (u8) 0xff) + << 16); + if ((offset % 4) == 3) + tmp = + (tmp & 0x00ffffff) | ((val & (u8) 0xff) + << 24); + } else if (size == 2) { + if ((offset % 4) == 0) + tmp = + (tmp & 0xffff0000) | (val & (u16) + 0xffff); + if ((offset % 4) == 2) + tmp = + (tmp & 0x0000ffff) | + ((val & (u16) 0xffff) << 16); + } + if (busnum == 0) + pci0WriteConfigReg(offset, bus->dev, tmp); + //if (busnum == 1) pci1WriteConfigReg (offset,bus->dev,tmp); + } + return PCIBIOS_SUCCESSFUL; +} + +static void galileo_pcibios_set_master(struct pci_dev *dev) +{ + u16 cmd; + + galileo_pcibios_read(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd); + cmd |= PCI_COMMAND_MASTER; + galileo_pcibios_write(dev->bus, dev->devfn, PCI_COMMAND, 2, cmd); +} + +/* Externally-expected functions. Do not change function names */ + +int pcibios_enable_resources(struct pci_dev *dev) +{ + u16 cmd, old_cmd; + u8 tmp1; + int idx; + struct resource *r; + + galileo_pcibios_read(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd); + old_cmd = cmd; + for (idx = 0; idx < 6; idx++) { + r = &dev->resource[idx]; + if (!r->start && r->end) { + printk(KERN_ERR + "PCI: Device %s not available because of " + "resource collisions\n", dev->slot_name); + return -EINVAL; + } + if (r->flags & IORESOURCE_IO) + cmd |= PCI_COMMAND_IO; + if (r->flags & IORESOURCE_MEM) + cmd |= PCI_COMMAND_MEMORY; + } + if (cmd != old_cmd) { + galileo_pcibios_write(dev->bus, dev->devfn, PCI_COMMAND, 2, + cmd); + } + + /* + * Let's fix up the latency timer and cache line size here. Cache + * line size = 32 bytes / sizeof dword (4) = 8. + * Latency timer must be > 8. 32 is random but appears to work. + */ + galileo_pcibios_read(dev->bus, dev->devfn, PCI_CACHE_LINE_SIZE, 1, + &tmp1); + if (tmp1 != 8) { + printk(KERN_WARNING + "PCI setting cache line size to 8 from " "%d\n", + tmp1); + galileo_pcibios_write(dev->bus, dev->devfn, + PCI_CACHE_LINE_SIZE, 1, 8); + } + galileo_pcibios_read(dev->bus, dev->devfn, PCI_LATENCY_TIMER, 1, + &tmp1); + if (tmp1 < 32) { + printk(KERN_WARNING + "PCI setting latency timer to 32 from %d\n", tmp1); + galileo_pcibios_write(dev->bus, dev->devfn, + PCI_LATENCY_TIMER, 1, 32); + } + + return 0; +} + +int pcibios_enable_device(struct pci_dev *dev, int mask) +{ + return pcibios_enable_resources(dev); +} + +void pcibios_align_resource(void *data, struct resource *res, + unsigned long size, unsigned long align) +{ + struct pci_dev *dev = data; + + if (res->flags & IORESOURCE_IO) { + unsigned long start = res->start; + + /* We need to avoid collisions with `mirrored' VGA ports + and other strange ISA hardware, so we always want the + addresses kilobyte aligned. */ + if (size > 0x100) { + printk(KERN_ERR "PCI: I/O Region %s/%d too large" + " (%ld bytes)\n", dev->slot_name, + dev->resource - res, size); + } + + start = (start + 1024 - 1) & ~(1024 - 1); + res->start = start; + } +} + +struct pci_ops galileo_pci_ops = { + .read = galileo_pcibios_read, + .write = galileo_pcibios_write, +}; + +struct pci_fixup pcibios_fixups[] = { + {0} +}; + +void __devinit pcibios_fixup_bus(struct pci_bus *c) +{ + gt64120_board_pcibios_fixup_bus(c); +} + +/* + * This code was derived from Galileo Technology's example + * and significantly reworked. + * + * This is very simple. It does not scan multiple function devices. It does + * not scan behind bridges. Those would be simple to implement, but we don't + * currently need this. + */ + +static void __init scan_and_initialize_pci(void) +{ + struct pci_device pci_devices[MAX_PCI_DEVS]; + + if (scan_pci_bus(pci_devices)) { + allocate_pci_space(pci_devices); + } +} + +/* + * This is your basic PCI scan. It goes through each slot and checks to + * see if there's something that responds. If so, then get the size and + * type of each of the responding BARs. Save them for later. + */ + +static u32 __init scan_pci_bus(struct pci_device *pci_devices) +{ + u32 arrayCounter = 0; + u32 memType; + u32 memSize; + u32 pci_slot, bar; + u32 id; + u32 c18RegValue; + struct pci_dev device; + + /* + * According to PCI REV 2.1 MAX agents on the bus are 21. + * We don't bother scanning ourselves (slot 0). + */ + for (pci_slot = 1; pci_slot < 22; pci_slot++) { + + device.devfn = PCI_DEVFN(pci_slot, 0); + id = pci0ReadConfigReg(PCI_VENDOR_ID, &device); + + /* + * Check for a PCI Master Abort (nothing responds in the + * slot) + */ + GT_READ(GT_INTRCAUSE_OFS, &c18RegValue); + /* + * Clearing bit 18 of in the Cause Register 0xc18 by + * writting 0. + */ + GT_WRITE(GT_INTRCAUSE_OFS, (c18RegValue & 0xfffbffff)); + if ((id != 0xffffffff) && !(c18RegValue & 0x40000)) { + pci_devices[arrayCounter].slot = pci_slot; + for (bar = 0; bar < 6; bar++) { + memType = + pci0ReadConfigReg(PCI_BASE_ADDRESS_0 + + (bar * 4), &device); + pci_devices[arrayCounter].BARtype[bar] = + memType & 1; + pci0WriteConfigReg(PCI_BASE_ADDRESS_0 + + (bar * 4), &device, + 0xffffffff); + memSize = + pci0ReadConfigReg(PCI_BASE_ADDRESS_0 + + (bar * 4), &device); + if (memType & 1) { /* IO space */ + pci_devices[arrayCounter]. + BARsize[bar] = + ~(memSize & 0xfffffffc) + 1; + } else { /* memory space */ + pci_devices[arrayCounter]. + BARsize[bar] = + ~(memSize & 0xfffffff0) + 1; + } + } /* BAR counter */ + + arrayCounter++; + } + /* found a device */ + } /* slot counter */ + + if (arrayCounter < MAX_PCI_DEVS) + pci_devices[arrayCounter].slot = -1; + + return arrayCounter; +} + +/* + * This function goes through the list of devices and allocates the BARs in + * either IO or MEM space. It does it in order of size, which will limit the + * amount of fragmentation we have in the IO and MEM spaces. + */ + +static void __init allocate_pci_space(struct pci_device *pci_devices) +{ + u32 count, maxcount, bar; + u32 maxSize, maxDevice, maxBAR; + u32 alignto; + u32 base; + u32 pci0_mem_base = pci0GetMemory0Base(); + u32 pci0_io_base = pci0GetIOspaceBase(); + struct pci_dev device; + + /* How many PCI devices do we have? */ + maxcount = MAX_PCI_DEVS; + for (count = 0; count < MAX_PCI_DEVS; count++) { + if (pci_devices[count].slot == -1) { + maxcount = count; + break; + } + } + + do { + /* Find the largest size BAR we need to allocate */ + maxSize = 0; + for (count = 0; count < maxcount; count++) { + for (bar = 0; bar < 6; bar++) { + if (pci_devices[count].BARsize[bar] > + maxSize) { + maxSize = + pci_devices[count]. + BARsize[bar]; + maxDevice = count; + maxBAR = bar; + } + } + } + + /* + * We've found the largest BAR. Allocate it into IO or + * mem space. We don't idiot check the bases to make + * sure they haven't overflowed the current size for that + * aperture. + * Don't bother to enable the device's IO or MEM space here. + * That will be done in pci_enable_resources if the device is + * activated by a driver. + */ + if (maxSize) { + device.devfn = + PCI_DEVFN(pci_devices[maxDevice].slot, 0); + if (pci_devices[maxDevice].BARtype[maxBAR] == 1) { + alignto = max(0x1000U, maxSize); + base = ALIGN(pci0_io_base, alignto); + pci0WriteConfigReg(PCI_BASE_ADDRESS_0 + + (maxBAR * 4), &device, + base | 0x1); + pci0_io_base = base + alignto; + } else { + alignto = max(0x1000U, maxSize); + base = ALIGN(pci0_mem_base, alignto); + pci0WriteConfigReg(PCI_BASE_ADDRESS_0 + + (maxBAR * 4), &device, + base); + pci0_mem_base = base + alignto; + } + /* + * This entry is finished. Remove it from the list + * we'll scan. + */ + pci_devices[maxDevice].BARsize[maxBAR] = 0; + } + } while (maxSize); +} + +static int __init pcibios_init(void) +{ + u32 tmp; + struct pci_dev controller; + + controller.devfn = SELF; + + GT_READ(GT_PCI0_CMD_OFS, &tmp); + GT_READ(GT_PCI0_BARE_OFS, &tmp); + + /* + * You have to enable bus mastering to configure any other + * card on the bus. + */ + tmp = pci0ReadConfigReg(PCI_COMMAND, &controller); + tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; + pci0WriteConfigReg(PCI_COMMAND, &controller, tmp); + + /* This scans the PCI bus and sets up initial values. */ + scan_and_initialize_pci(); + + /* + * Reset PCI I/O and PCI MEM values to ones supported by EVM. + */ + ioport_resource.start = GT_PCI_IO_BASE; + ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; + iomem_resource.start = GT_PCI_MEM_BASE; + iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1; + + pci_scan_bus(0, &galileo_pci_ops, NULL); + + return 0; +} + +subsys_initcall(pcibios_init); + +/* + * for parsing "pci=" kernel boot arguments. + */ +char *pcibios_setup(char *str) +{ + printk(KERN_INFO "rr: pcibios_setup\n"); + /* Nothing to do for now. */ + + return str; +} + +unsigned __init int pcibios_assign_all_busses(void) +{ + return 1; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/ops-vrc4173.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,120 @@ +/* + * FILE NAME + * arch/mips/vr41xx/nec-eagle/vrc4173.c + * + * BRIEF MODULE DESCRIPTION + * Pre-setup for NEC VRC4173. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2001,2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include + +#include +#include +#include + +#define PCI_CONFIG_ADDR KSEG1ADDR(0x0f000c18) +#define PCI_CONFIG_DATA KSEG1ADDR(0x0f000c14) + +static inline void config_writeb(u8 reg, u8 val) +{ + u32 data; + int shift; + + writel((1UL << 0x1e) | (reg & 0xfc), PCI_CONFIG_ADDR); + data = readl(PCI_CONFIG_DATA); + + shift = (reg & 3) << 3; + data &= ~(0xff << shift); + data |= (((u32) val) << shift); + + writel(data, PCI_CONFIG_DATA); +} + +static inline u16 config_readw(u8 reg) +{ + u32 data; + + writel(((1UL << 30) | (reg & 0xfc)), PCI_CONFIG_ADDR); + data = readl(PCI_CONFIG_DATA); + + return (u16) (data >> ((reg & 2) << 3)); +} + +static inline u32 config_readl(u8 reg) +{ + writel(((1UL << 30) | (reg & 0xfc)), PCI_CONFIG_ADDR); + + return readl(PCI_CONFIG_DATA); +} + +static inline void config_writel(u8 reg, u32 val) +{ + writel((1UL << 0x1e) | (reg & 0xfc), PCI_CONFIG_ADDR); + writel(val, PCI_CONFIG_DATA); +} + +void __init vrc4173_preinit(void) +{ + u32 cmdsts, base; + u16 cmu_mask; + + + if ((config_readw(PCI_VENDOR_ID) == PCI_VENDOR_ID_NEC) && + (config_readw(PCI_DEVICE_ID) == PCI_DEVICE_ID_NEC_VRC4173)) { + /* + * Initialized NEC VRC4173 Bus Control Unit + */ + cmdsts = config_readl(PCI_COMMAND); + config_writel(PCI_COMMAND, + cmdsts | + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + config_writeb(PCI_LATENCY_TIMER, 0x80); + + config_writel(PCI_BASE_ADDRESS_0, VR41XX_PCI_IO_START); + base = config_readl(PCI_BASE_ADDRESS_0); + base &= PCI_BASE_ADDRESS_IO_MASK; + config_writeb(0x40, 0x01); + + /* CARDU1 IDSEL = AD12, CARDU2 IDSEL = AD13 */ + config_writeb(0x41, 0); + + cmu_mask = 0x1000; + outw(cmu_mask, base + 0x040); + cmu_mask |= 0x0800; + outw(cmu_mask, base + 0x040); + + outw(0x000f, base + 0x042); /* Soft reset of CMU */ + cmu_mask |= 0x05e0; + outw(cmu_mask, base + 0x040); + cmu_mask = inw(base + 0x040); /* dummy read */ + outw(0x0000, base + 0x042); + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-auto.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,518 @@ +/* + * PCI autoconfiguration library + * + * Author: Matt Porter + * + * Copyright 2000, 2001, 2002, 2003 MontaVista Software Inc. + * Copyright 2001 Bradley D. LaRonde + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/* + * Modified for MIPS by Jun Sun, jsun@mvista.com + * + * . Simplify the interface between pci_auto and the rest: a single function. + * . Assign resources from low address to upper address. + * . change most int to u32. + * + * Further modified to include it as mips generic code, ppopov@mvista.com. + * + * 2001-10-26 Bradley D. LaRonde + * - Add a top_bus argument to the "early config" functions so that + * they can set a fake parent bus pointer to convince the underlying + * pci ops to use type 1 configuration for sub busses. + * - Set bridge base and limit registers correctly. + * - Align io and memory base properly before and after bridge setup. + * - Don't fall through to pci_setup_bars for bridge. + * - Reformat the debug output to look more like lspci's output. + * + * 2003-04-09 Yoichi Yuasa, Alice Hennessy, Jun Sun + * - Add cardbus bridge support, mostly copied from PPC + */ + +#include +#include +#include +#include + +#include + +#define DEBUG +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +/* + * These functions are used early on before PCI scanning is done + * and all of the pci_dev and pci_bus structures have been created. + */ +static struct pci_dev *fake_pci_dev(struct pci_channel *hose, + int top_bus, int busnr, int devfn) +{ + static struct pci_dev dev; + static struct pci_bus bus; + + dev.bus = &bus; + dev.sysdata = hose; + dev.devfn = devfn; + bus.number = busnr; + bus.ops = hose->pci_ops; + + if (busnr != top_bus) + /* Fake a parent bus structure. */ + bus.parent = &bus; + else + bus.parent = NULL; + + return &dev; +} + +#define EARLY_PCI_OP(rw, size, type) \ +int early_##rw##_config_##size(struct pci_channel *hose, \ + int top_bus, int bus, int devfn, int offset, type value) \ +{ \ + return pci_##rw##_config_##size( \ + fake_pci_dev(hose, top_bus, bus, devfn), \ + offset, value); \ +} + +EARLY_PCI_OP(read, byte, u8 *) + EARLY_PCI_OP(read, word, u16 *) + EARLY_PCI_OP(read, dword, u32 *) + EARLY_PCI_OP(write, byte, u8) + EARLY_PCI_OP(write, word, u16) + EARLY_PCI_OP(write, dword, u32) + +static struct resource *io_resource_inuse; +static struct resource *mem_resource_inuse; + +static u32 pciauto_lower_iospc; +static u32 pciauto_upper_iospc; + +static u32 pciauto_lower_memspc; +static u32 pciauto_upper_memspc; + +void __init +pciauto_setup_bars(struct pci_channel *hose, + int top_bus, + int current_bus, int pci_devfn, int bar_limit) +{ + u32 bar_response, bar_size, bar_value; + u32 bar, addr_mask, bar_nr = 0; + u32 *upper_limit; + u32 *lower_limit; + int found_mem64 = 0; + + for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar += 4) { + /* Tickle the BAR and get the response */ + early_write_config_dword(hose, top_bus, + current_bus, + pci_devfn, bar, 0xffffffff); + early_read_config_dword(hose, top_bus, + current_bus, + pci_devfn, bar, &bar_response); + + /* If BAR is not implemented go to the next BAR */ + if (!bar_response) + continue; + + /* + * Workaround for a BAR that doesn't use its upper word, + * like the ALi 1535D+ PCI DC-97 Controller Modem (M5457). + * bdl + */ + if (!(bar_response & 0xffff0000)) + bar_response |= 0xffff0000; + + retry: + /* Check the BAR type and set our address mask */ + if (bar_response & PCI_BASE_ADDRESS_SPACE) { + addr_mask = PCI_BASE_ADDRESS_IO_MASK; + upper_limit = &pciauto_upper_iospc; + lower_limit = &pciauto_lower_iospc; + DBG(" I/O"); + } else { + if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) + == PCI_BASE_ADDRESS_MEM_TYPE_64) + found_mem64 = 1; + + addr_mask = PCI_BASE_ADDRESS_MEM_MASK; + upper_limit = &pciauto_upper_memspc; + lower_limit = &pciauto_lower_memspc; + DBG(" Mem"); + } + + + /* Calculate requested size */ + bar_size = ~(bar_response & addr_mask) + 1; + + /* Allocate a base address */ + bar_value = + ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size; + + if ((bar_value + bar_size) > *upper_limit) { + if (bar_response & PCI_BASE_ADDRESS_SPACE) { + if (io_resource_inuse->child) { + io_resource_inuse = + io_resource_inuse->child; + pciauto_lower_iospc = + io_resource_inuse->start; + pciauto_upper_iospc = + io_resource_inuse->end + 1; + goto retry; + } + + } else { + if (mem_resource_inuse->child) { + mem_resource_inuse = + mem_resource_inuse->child; + pciauto_lower_memspc = + mem_resource_inuse->start; + pciauto_upper_memspc = + mem_resource_inuse->end + 1; + goto retry; + } + } + DBG(" unavailable -- skipping\n"); + continue; + } + + /* Write it out and update our limit */ + early_write_config_dword(hose, top_bus, current_bus, + pci_devfn, bar, bar_value); + + *lower_limit = bar_value + bar_size; + + /* + * If we are a 64-bit decoder then increment to the + * upper 32 bits of the bar and force it to locate + * in the lower 4GB of memory. + */ + if (found_mem64) { + bar += 4; + early_write_config_dword(hose, top_bus, + current_bus, + pci_devfn, + bar, 0x00000000); + } + + DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size); + + bar_nr++; + } + +} + +void __init +pciauto_prescan_setup_bridge(struct pci_channel *hose, + int top_bus, + int current_bus, int pci_devfn, int sub_bus) +{ + /* Configure bus number registers */ + early_write_config_byte(hose, top_bus, current_bus, pci_devfn, + PCI_PRIMARY_BUS, current_bus); + early_write_config_byte(hose, top_bus, current_bus, pci_devfn, + PCI_SECONDARY_BUS, sub_bus + 1); + early_write_config_byte(hose, top_bus, current_bus, pci_devfn, + PCI_SUBORDINATE_BUS, 0xff); + + /* Align memory and I/O to 1MB and 4KB boundaries. */ + pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1)) + & ~(0x100000 - 1); + pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1)) + & ~(0x1000 - 1); + + /* Set base (lower limit) of address range behind bridge. */ + early_write_config_word(hose, top_bus, current_bus, pci_devfn, + PCI_MEMORY_BASE, + pciauto_lower_memspc >> 16); + early_write_config_byte(hose, top_bus, current_bus, pci_devfn, + PCI_IO_BASE, + (pciauto_lower_iospc & 0x0000f000) >> 8); + early_write_config_word(hose, top_bus, current_bus, pci_devfn, + PCI_IO_BASE_UPPER16, + pciauto_lower_iospc >> 16); + + /* We don't support prefetchable memory for now, so disable */ + early_write_config_word(hose, top_bus, current_bus, pci_devfn, + PCI_PREF_MEMORY_BASE, 0); + early_write_config_word(hose, top_bus, current_bus, pci_devfn, + PCI_PREF_MEMORY_LIMIT, 0); +} + +void __init +pciauto_postscan_setup_bridge(struct pci_channel *hose, + int top_bus, + int current_bus, int pci_devfn, int sub_bus) +{ + u32 temp; + + /* + * [jsun] we always bump up baselines a little, so that if there + * nothing behind P2P bridge, we don't wind up overlapping IO/MEM + * spaces. + */ + pciauto_lower_memspc += 1; + pciauto_lower_iospc += 1; + + /* Configure bus number registers */ + early_write_config_byte(hose, top_bus, current_bus, pci_devfn, + PCI_SUBORDINATE_BUS, sub_bus); + + /* Set upper limit of address range behind bridge. */ + early_write_config_word(hose, top_bus, current_bus, pci_devfn, + PCI_MEMORY_LIMIT, + pciauto_lower_memspc >> 16); + early_write_config_byte(hose, top_bus, current_bus, pci_devfn, + PCI_IO_LIMIT, + (pciauto_lower_iospc & 0x0000f000) >> 8); + early_write_config_word(hose, top_bus, current_bus, pci_devfn, + PCI_IO_LIMIT_UPPER16, + pciauto_lower_iospc >> 16); + + /* Align memory and I/O to 1MB and 4KB boundaries. */ + pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1)) + & ~(0x100000 - 1); + pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1)) + & ~(0x1000 - 1); + + /* Enable memory and I/O accesses, enable bus master */ + early_read_config_dword(hose, top_bus, current_bus, pci_devfn, + PCI_COMMAND, &temp); + early_write_config_dword(hose, top_bus, current_bus, pci_devfn, + PCI_COMMAND, + temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY + | PCI_COMMAND_MASTER); +} + +void __init +pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose, + int top_bus, + int current_bus, + int pci_devfn, int sub_bus) +{ + /* Configure bus number registers */ + early_write_config_byte(hose, top_bus, current_bus, pci_devfn, + PCI_PRIMARY_BUS, current_bus); + early_write_config_byte(hose, top_bus, current_bus, pci_devfn, + PCI_SECONDARY_BUS, sub_bus + 1); + early_write_config_byte(hose, top_bus, current_bus, pci_devfn, + PCI_SUBORDINATE_BUS, 0xff); + + /* Align memory and I/O to 4KB and 4 byte boundaries. */ + pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1)) + & ~(0x1000 - 1); + pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1)) + & ~(0x4 - 1); + + early_write_config_dword(hose, top_bus, current_bus, pci_devfn, + PCI_CB_MEMORY_BASE_0, + pciauto_lower_memspc); + early_write_config_dword(hose, top_bus, current_bus, pci_devfn, + PCI_CB_IO_BASE_0, pciauto_lower_iospc); +} + +void __init +pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose, + int top_bus, + int current_bus, + int pci_devfn, int sub_bus) +{ + u32 temp; + + /* + * Configure subordinate bus number. The PCI subsystem + * bus scan will renumber buses (reserving three additional + * for this PCI<->CardBus bridge for the case where a CardBus + * adapter contains a P2P or CB2CB bridge. + */ + + early_write_config_byte(hose, top_bus, current_bus, pci_devfn, + PCI_SUBORDINATE_BUS, sub_bus); + + /* + * Reserve an additional 4MB for mem space and 16KB for + * I/O space. This should cover any additional space + * requirement of unusual CardBus devices with + * additional bridges that can consume more address space. + * + * Although pcmcia-cs currently will reprogram bridge + * windows, the goal is to add an option to leave them + * alone and use the bridge window ranges as the regions + * that are searched for free resources upon hot-insertion + * of a device. This will allow a PCI<->CardBus bridge + * configured by this routine to happily live behind a + * P2P bridge in a system. + */ + pciauto_lower_memspc += 0x00400000; + pciauto_lower_iospc += 0x00004000; + + /* Align memory and I/O to 4KB and 4 byte boundaries. */ + pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1)) + & ~(0x1000 - 1); + pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1)) + & ~(0x4 - 1); + /* Set up memory and I/O filter limits, assume 32-bit I/O space */ + early_write_config_dword(hose, top_bus, current_bus, pci_devfn, + PCI_CB_MEMORY_LIMIT_0, + pciauto_lower_memspc - 1); + early_write_config_dword(hose, top_bus, current_bus, pci_devfn, + PCI_CB_IO_LIMIT_0, + pciauto_lower_iospc - 1); + + /* Enable memory and I/O accesses, enable bus master */ + early_read_config_dword(hose, top_bus, current_bus, pci_devfn, + PCI_COMMAND, &temp); + early_write_config_dword(hose, top_bus, current_bus, pci_devfn, + PCI_COMMAND, + temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY + | PCI_COMMAND_MASTER); +} + +#define PCIAUTO_IDE_MODE_MASK 0x05 + +int __init +pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus) +{ + int sub_bus; + u32 pci_devfn, pci_class, cmdstat, found_multi = 0; + unsigned short vid, did; + unsigned char header_type; + int devfn_start = 0; + int devfn_stop = 0xff; + + sub_bus = current_bus; + + if (hose->first_devfn) + devfn_start = hose->first_devfn; + if (hose->last_devfn) + devfn_stop = hose->last_devfn; + + for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { + + if (PCI_FUNC(pci_devfn) && !found_multi) + continue; + + early_read_config_word(hose, top_bus, current_bus, + pci_devfn, PCI_VENDOR_ID, &vid); + + if (vid == 0xffff) + continue; + + early_read_config_byte(hose, top_bus, current_bus, + pci_devfn, PCI_HEADER_TYPE, + &header_type); + + if (!PCI_FUNC(pci_devfn)) + found_multi = header_type & 0x80; + + early_read_config_word(hose, top_bus, current_bus, + pci_devfn, PCI_DEVICE_ID, &did); + + early_read_config_dword(hose, top_bus, current_bus, + pci_devfn, PCI_CLASS_REVISION, + &pci_class); + + DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x", + current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn), + pci_class >> 16, vid, did); + if (pci_class & 0xff) + DBG(" (rev %.2x)", pci_class & 0xff); + DBG("\n"); + + if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) { + DBG(" Bridge: primary=%.2x, secondary=%.2x\n", current_bus, sub_bus + 1); + pciauto_setup_bars(hose, top_bus, current_bus, + pci_devfn, PCI_BASE_ADDRESS_1); + pciauto_prescan_setup_bridge(hose, top_bus, + current_bus, + pci_devfn, sub_bus); + DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n", sub_bus + 1, pciauto_lower_iospc, pciauto_lower_memspc); + sub_bus = + pciauto_bus_scan(hose, top_bus, sub_bus + 1); + DBG("Back to bus %.2x\n", current_bus); + pciauto_postscan_setup_bridge(hose, top_bus, + current_bus, + pci_devfn, sub_bus); + continue; + } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) { + DBG(" CARDBUS Bridge: primary=%.2x, secondary=%.2x\n", current_bus, sub_bus + 1); + DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn)); + /* Place CardBus Socket/ExCA registers */ + pciauto_setup_bars(hose, top_bus, current_bus, + pci_devfn, PCI_BASE_ADDRESS_0); + + pciauto_prescan_setup_cardbus_bridge(hose, top_bus, + current_bus, + pci_devfn, + sub_bus); + + DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n", sub_bus + 1, pciauto_lower_iospc, pciauto_lower_memspc); + sub_bus = + pciauto_bus_scan(hose, top_bus, sub_bus + 1); + DBG("Back to bus %.2x, sub_bus is %x\n", + current_bus, sub_bus); + pciauto_postscan_setup_cardbus_bridge(hose, + top_bus, + current_bus, + pci_devfn, + sub_bus); + continue; + } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) { + + unsigned char prg_iface; + + early_read_config_byte(hose, top_bus, current_bus, + pci_devfn, PCI_CLASS_PROG, + &prg_iface); + if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) { + DBG("Skipping legacy mode IDE controller\n"); + continue; + } + } + + /* + * Found a peripheral, enable some standard + * settings + */ + early_read_config_dword(hose, top_bus, current_bus, + pci_devfn, PCI_COMMAND, &cmdstat); + early_write_config_dword(hose, top_bus, current_bus, + pci_devfn, PCI_COMMAND, + cmdstat | PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + early_write_config_byte(hose, top_bus, current_bus, + pci_devfn, PCI_LATENCY_TIMER, + 0x80); + + /* Allocate PCI I/O and/or memory space */ + pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, + PCI_BASE_ADDRESS_5); + } + return sub_bus; +} + +int __init pciauto_assign_resources(int busno, struct pci_channel *hose) +{ + /* setup resource limits */ + io_resource_inuse = hose->io_resource; + mem_resource_inuse = hose->mem_resource; + + pciauto_lower_iospc = io_resource_inuse->start; + pciauto_upper_iospc = io_resource_inuse->end + 1; + pciauto_lower_memspc = mem_resource_inuse->start; + pciauto_upper_memspc = mem_resource_inuse->end + 1; + DBG("Autoconfig PCI channel 0x%p\n", hose); + DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n", + busno, pciauto_lower_iospc, pciauto_upper_iospc, + pciauto_lower_memspc, pciauto_upper_memspc); + + return pciauto_bus_scan(hose, busno, busno); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,233 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * Modified to be mips generic, ppopov@mvista.com + * arch/mips/kernel/pci.c + * Common MIPS PCI routines. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/* + * This file contains common PCI routines meant to be shared for + * all MIPS machines. + * + * Strategies: + * + * . We rely on pci_auto.c file to assign PCI resources (MEM and IO) + * TODO: this should be optional for some machines where they do have + * a real "pcibios" that does resource assignment. + * + * . We then use pci_scan_bus() to "discover" all the resources for + * later use by Linux. + * + * . We finally reply on a board supplied function, pcibios_fixup_irq(), to + * to assign the interrupts. We may use setup-irq.c under drivers/pci + * later. + * + * . Specifically, we will *NOT* use pci_assign_unassigned_resources(), + * because we assume all PCI devices should have the resources correctly + * assigned and recorded. + * + * Limitations: + * + * . We "collapse" all IO and MEM spaces in sub-buses under a top-level bus + * into a contiguous range. + * + * . In the case of Memory space, the rnage is 1:1 mapping with CPU physical + * address space. + * + * . In the case of IO space, it starts from 0, and the beginning address + * is mapped to KSEG0ADDR(mips_io_port) in the CPU physical address. + * + * . These are the current MIPS limitations (by ioremap, etc). In the + * future, we may remove them. + * + * Credits: + * Most of the code are derived from the pci routines from PPC and Alpha, + * which were mostly writtne by + * Cort Dougan, cort@fsmlabs.com + * Matt Porter, mporter@mvista.com + * Dave Rusling david.rusling@reo.mts.dec.com + * David Mosberger davidm@cs.arizona.edu + */ +#include +#include +#include +#include +#include + +#include + +extern void pcibios_fixup(void); +extern void pcibios_fixup_irqs(void); + +void __init pcibios_fixup_irqs(void) +{ + struct pci_dev *dev = NULL; + int slot_num; + + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + slot_num = PCI_SLOT(dev->devfn); + switch (slot_num) { + case 2: + dev->irq = 3; + break; + case 3: + dev->irq = 4; + break; + case 4: + dev->irq = 5; + break; + default: + break; + } + } +} + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ /* HP-LJ */ + int pos; + int bases; + + printk("adjusting pci device: %s\n", dev->name); + + switch (dev->hdr_type) { + case PCI_HEADER_TYPE_NORMAL: + bases = 6; + break; + case PCI_HEADER_TYPE_BRIDGE: + bases = 2; + break; + case PCI_HEADER_TYPE_CARDBUS: + bases = 1; + break; + default: + bases = 0; + break; + } + for (pos = 0; pos < bases; pos++) { + struct resource *res = &dev->resource[pos]; + if (res->start >= IO_MEM_LOGICAL_START && + res->end <= IO_MEM_LOGICAL_END) { + res->start += IO_MEM_VIRTUAL_OFFSET; + res->end += IO_MEM_VIRTUAL_OFFSET; + } + if (res->start >= IO_PORT_LOGICAL_START && + res->end <= IO_PORT_LOGICAL_END) { + res->start += IO_PORT_VIRTUAL_OFFSET; + res->end += IO_PORT_VIRTUAL_OFFSET; + } + } + +} + +struct pci_fixup pcibios_fixups[] = { + {PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, + pcibios_fixup_resources}, + {0} +}; + +extern int pciauto_assign_resources(int busno, struct pci_channel *hose); + +static int __init pcibios_init(void) +{ + struct pci_channel *p; + struct pci_bus *bus; + int busno; + +#ifdef CONFIG_PCI_AUTO + /* assign resources */ + busno = 0; + for (p = mips_pci_channels; p->pci_ops != NULL; p++) { + busno = pciauto_assign_resources(busno, p) + 1; + } +#endif + + /* scan the buses */ + busno = 0; + for (p = mips_pci_channels; p->pci_ops != NULL; p++) { + bus = pci_scan_bus(busno, p->pci_ops, p); + busno = bus->subordinate + 1; + } + + /* machine dependent fixups */ + pcibios_fixup(); + /* fixup irqs (board specific routines) */ + pcibios_fixup_irqs(); + + return 0; +} + +subsys_initcall(pcibios_init); + +int pcibios_enable_device(struct pci_dev *dev, int mask) +{ + /* pciauto_assign_resources() will enable all devices found */ + return 0; +} + +unsigned long __init pci_bridge_check_io(struct pci_dev *bridge) +{ + u16 io; + + pci_read_config_word(bridge, PCI_IO_BASE, &io); + if (!io) { + pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); + pci_read_config_word(bridge, PCI_IO_BASE, &io); + pci_write_config_word(bridge, PCI_IO_BASE, 0x0); + } + if (io) + return IORESOURCE_IO; + //printk(KERN_WARNING "PCI: bridge %s does not support I/O forwarding!\n", bridge->name); + return 0; +} + +void __devinit pcibios_fixup_bus(struct pci_bus *bus) +{ + /* Propogate hose info into the subordinate devices. */ + + struct pci_channel *hose = bus->sysdata; + struct pci_dev *dev = bus->self; + + if (!dev) { + /* Root bus */ + bus->resource[0] = hose->io_resource; + bus->resource[1] = hose->mem_resource; + } else { + /* This is a bridge. Do not care how it's initialized, + just link its resources to the bus ones */ + int i; + + for (i = 0; i < 3; i++) { + bus->resource[i] = + &dev->resource[PCI_BRIDGE_RESOURCES + i]; + bus->resource[i]->name = bus->name; + } + bus->resource[0]->flags |= pci_bridge_check_io(dev); + bus->resource[1]->flags |= IORESOURCE_MEM; + /* For now, propagate hose limits to the bus; + we'll adjust them later. */ + bus->resource[0]->end = hose->io_resource->end; + bus->resource[1]->end = hose->mem_resource->end; + /* Turn off downstream PF memory address range by default */ + bus->resource[2]->start = 1024 * 1024; + bus->resource[2]->end = bus->resource[2]->start - 1; + } +} + +char *pcibios_setup(char *str) +{ + return str; +} + +void pcibios_align_resource(void *data, struct resource *res, + unsigned long size, unsigned long align) +{ + /* this should not be called */ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-cobalt.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,433 @@ +/* + * Cobalt Qube/Raq PCI support + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1996, 1997, 2002 by Ralf Baechle + * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) + */ +#include +#include +#include +#include + +#include +#include +#include + +#include + +int cobalt_board_id; + +static void qube_expansion_slot_bist(struct pci_dev *dev) +{ + unsigned char ctrl; + int timeout = 100000; + + pci_read_config_byte(dev, PCI_BIST, &ctrl); + if (!(ctrl & PCI_BIST_CAPABLE)) + return; + + pci_write_config_byte(dev, PCI_BIST, ctrl | PCI_BIST_START); + do { + pci_read_config_byte(dev, PCI_BIST, &ctrl); + if (!(ctrl & PCI_BIST_START)) + break; + } while (--timeout > 0); + if ((timeout <= 0) || (ctrl & PCI_BIST_CODE_MASK)) + printk + ("PCI: Expansion slot card failed BIST with code %x\n", + (ctrl & PCI_BIST_CODE_MASK)); +} + +static void qube_expansion_slot_fixup(struct pci_dev *dev) +{ + unsigned short pci_cmd; + unsigned long ioaddr_base = 0x10108000; /* It's magic, ask Doug. */ + unsigned long memaddr_base = 0x12001000; + int i; + + /* Enable bits in COMMAND so driver can talk to it. */ + pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); + pci_cmd |= + (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_write_config_word(dev, PCI_COMMAND, pci_cmd); + + /* Give it a working IRQ. */ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + COBALT_QUBE_SLOT_IRQ); + dev->irq = COBALT_QUBE_SLOT_IRQ; + + ioaddr_base += 0x2000 * PCI_FUNC(dev->devfn); + memaddr_base += 0x2000 * PCI_FUNC(dev->devfn); + + /* Fixup base addresses, we only support I/O at the moment. */ + for (i = 0; i <= 5; i++) { + unsigned int regaddr = (PCI_BASE_ADDRESS_0 + (i * 4)); + unsigned int rval, mask, size, alignme, aspace; + unsigned long *basep = &ioaddr_base; + + /* Check type first, punt if non-IO. */ + pci_read_config_dword(dev, regaddr, &rval); + aspace = (rval & PCI_BASE_ADDRESS_SPACE); + if (aspace != PCI_BASE_ADDRESS_SPACE_IO) + basep = &memaddr_base; + + /* Figure out how much it wants, if anything. */ + pci_write_config_dword(dev, regaddr, 0xffffffff); + pci_read_config_dword(dev, regaddr, &rval); + + /* Unused? */ + if (rval == 0) + continue; + + rval &= PCI_BASE_ADDRESS_IO_MASK; + mask = (~rval << 1) | 0x1; + size = (mask & rval) & 0xffffffff; + alignme = size; + if (alignme < 0x400) + alignme = 0x400; + rval = ((*basep + (alignme - 1)) & ~(alignme - 1)); + *basep = (rval + size); + pci_write_config_dword(dev, regaddr, rval | aspace); + dev->resource[i].start = rval; + dev->resource[i].end = *basep - 1; + if (aspace == PCI_BASE_ADDRESS_SPACE_IO) { + dev->resource[i].start -= 0x10000000; + dev->resource[i].end -= 0x10000000; + } + } + qube_expansion_slot_bist(dev); +} + +static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) +{ + unsigned short cfgword; + unsigned char lt; + + /* Enable Bus Mastering and fast back to back. */ + pci_read_config_word(dev, PCI_COMMAND, &cfgword); + cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER); + pci_write_config_word(dev, PCI_COMMAND, cfgword); + + /* Enable both ide interfaces. ROM only enables primary one. */ + pci_write_config_byte(dev, 0x40, 0xb); + + /* Set latency timer to reasonable value. */ + pci_read_config_byte(dev, PCI_LATENCY_TIMER, <); + if (lt < 64) + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); +} + +static void qube_raq_tulip_fixup(struct pci_dev *dev) +{ + unsigned short pci_cmd; + + /* Fixup the first tulip located at device PCICONF_ETH0 */ + if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH0) { + /* Setup the first Tulip */ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + COBALT_ETH0_IRQ); + dev->irq = COBALT_ETH0_IRQ; + + dev->resource[0].start = 0x100000; + dev->resource[0].end = 0x10007f; + + dev->resource[1].start = 0x12000000; + dev->resource[1].end = dev->resource[1].start + 0x3ff; + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, + dev->resource[1].start); + + /* Fixup the second tulip located at device PCICONF_ETH1 */ + } else if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH1) { + + /* Enable the second Tulip device. */ + pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); + pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MASTER); + pci_write_config_word(dev, PCI_COMMAND, pci_cmd); + + /* Give it it's IRQ. */ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + COBALT_ETH1_IRQ); + dev->irq = COBALT_ETH1_IRQ; + + /* And finally, a usable I/O space allocation, right after what + * the first Tulip uses. + */ + dev->resource[0].start = 0x101000; + dev->resource[0].end = 0x10107f; + + dev->resource[1].start = 0x12000400; + dev->resource[1].end = dev->resource[1].start + 0x3ff; + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, + dev->resource[1].start); + } +} + +static void qube_raq_scsi_fixup(struct pci_dev *dev) +{ + unsigned short pci_cmd; + + /* + * Tell the SCSI device that we expect an interrupt at + * IRQ 7 and not the default 0. + */ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_SCSI_IRQ); + dev->irq = COBALT_SCSI_IRQ; + + if (cobalt_board_id == COBALT_BRD_ID_RAQ2) { + + /* Enable the device. */ + pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); + + pci_cmd |= + (PCI_COMMAND_IO | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE); + pci_write_config_word(dev, PCI_COMMAND, pci_cmd); + + /* Give it it's RAQ IRQ. */ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + COBALT_RAQ_SCSI_IRQ); + dev->irq = COBALT_RAQ_SCSI_IRQ; + + /* And finally, a usable I/O space allocation, right after what + * the second Tulip uses. + */ + dev->resource[0].start = 0x102000; + dev->resource[0].end = dev->resource[0].start + 0xff; + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, + 0x10102000); + + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, + 0x00002000); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, + 0x00100000); + } +} + +static void qube_raq_galileo_fixup(struct pci_dev *dev) +{ + unsigned short galileo_id; + + /* Fix PCI latency-timer and cache-line-size values in Galileo + * host bridge. + */ + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); + + /* On all machines prior to Q2, we had the STOP line disconnected + * from Galileo to VIA on PCI. The new Galileo does not function + * correctly unless we have it connected. + * + * Therefore we must set the disconnect/retry cycle values to + * something sensible when using the new Galileo. + */ + pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id); + galileo_id &= 0xff; /* mask off class info */ + if (galileo_id >= 0x10) { + /* New Galileo, assumes PCI stop line to VIA is connected. */ + GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS); + } else if (galileo_id == 0x1 || galileo_id == 0x2) { + signed int timeo; + /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ + timeo = GALILEO_INL(GT_PCI0_TOR_OFS); + /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ + GALILEO_OUTL(0xffff, GT_PCI0_TOR_OFS); + } +} + +static void qube_pcibios_fixup(struct pci_dev *dev) +{ + if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_PCISLOT) { + unsigned int tmp; + + /* See if there is a device in the expansion slot, if so + * discover its resources and fixup whatever we need to + */ + pci_read_config_dword(dev, PCI_VENDOR_ID, &tmp); + if (tmp != 0xffffffff && tmp != 0x00000000) + qube_expansion_slot_fixup(dev); + } +} + +struct pci_fixup pcibios_fixups[] = { + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, + qube_raq_via_bmIDE_fixup}, + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, + qube_raq_tulip_fixup}, + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_GALILEO, PCI_ANY_ID, + qube_raq_galileo_fixup}, + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, + qube_raq_scsi_fixup}, + {PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, qube_pcibios_fixup} +}; + + +static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn) +{ + if ((bus->number == 0) + && ((PCI_SLOT(devfn) == 0) + || ((PCI_SLOT(devfn) > 6) + && (PCI_SLOT(devfn) <= 12)))) + return 0; /* OK device number */ + + return -1; /* NOT ok device number */ +} + +#define PCI_CFG_SET(devfn,where) \ + GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \ + (PCI_FUNC (devfn) << 8) | (where)), \ + GT_PCI0_CFGADDR_OFS) + + +static int qube_pci_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + switch (size) { + case 4: + if (where & 0x3) + return PCIBIOS_BAD_REGISTER_NUMBER; + if (pci_range_ck(bus, devfn)) { + *val = 0xFFFFFFFF; + return PCIBIOS_DEVICE_NOT_FOUND; + } + PCI_CFG_SET(devfn, where); + *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS); + return PCIBIOS_SUCCESSFUL; + + case 2: + if (where & 0x1) + return PCIBIOS_BAD_REGISTER_NUMBER; + if (pci_range_ck(bus, devfn)) { + *val = 0xffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + PCI_CFG_SET(devfn, (where & ~0x3)); + *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS) + >> ((where & 3) * 8); + return PCIBIOS_SUCCESSFUL; + + case 1: + if (pci_range_ck(bus, devfn)) { + *val = 0xff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + PCI_CFG_SET(devfn, (where & ~0x3)); + *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS) + >> ((where & 3) * 8); + return PCIBIOS_SUCCESSFUL; + } +} + +static int qube_pci_write_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 tmp; + + switch (size) { + case 4: + if (where & 0x3) + return PCIBIOS_BAD_REGISTER_NUMBER; + if (pci_range_ck(bus, devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + PCI_CFG_SET(devfn, where); + GALILEO_OUTL(val, GT_PCI0_CFGDATA_OFS); + + return PCIBIOS_SUCCESSFUL; + + case 2: + if (where & 0x1) + return PCIBIOS_BAD_REGISTER_NUMBER; + if (pci_range_ck(bus, devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + PCI_CFG_SET(devfn, (where & ~0x3)); + tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS); + tmp &= ~(0xffff << ((where & 0x3) * 8)); + tmp |= (val << ((where & 0x3) * 8)); + GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS); + + return PCIBIOS_SUCCESSFUL; + + case 1: + + if (pci_range_ck(bus, devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + PCI_CFG_SET(devfn, (where & ~0x3)); + tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS); + tmp &= ~(0xff << ((where & 0x3) * 8)); + tmp |= (val << ((where & 0x3) * 8)); + GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS); + + return PCIBIOS_SUCCESSFUL; + } +} + +struct pci_ops qube_pci_ops = { + .read = qube_pci_read_config, + .write = qube_pci_write_config, +}; + +static int __init pcibios_init(void) +{ + unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0); + + printk("PCI: Probing PCI hardware\n"); + + /* Read the cobalt id register out of the PCI config space */ + PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3)); + cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS) + >> ((VIA_COBALT_BRD_ID_REG & 3) * 8); + cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id); + + printk("Cobalt Board ID: %d\n", cobalt_board_id); + + ioport_resource.start = 0x00000000; + ioport_resource.end = 0x0fffffff; + + iomem_resource.start = 0x01000000; + iomem_resource.end = 0xffffffff; + + pci_scan_bus(0, &qube_pci_ops, NULL); + + return 0; +} + +subsys_initcall(pcibios_init); + +char *pcibios_setup(char *str) +{ + return str; +} + +int pcibios_enable_device(struct pci_dev *dev, int mask) +{ + u16 cmd, status; + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + pci_read_config_word(dev, PCI_STATUS, &status); + printk("PCI: Enabling device %s (%04x %04x)\n", dev->slot_name, + cmd, status); + /* We'll sort this out when we know it isn't enabled ;) */ + + return 0; +} + +void pcibios_align_resource(void *data, struct resource *res, + unsigned long size, unsigned long align) +{ + + panic("Uhhoh called pcibios_align_resource\n"); +} + +void __devinit pcibios_fixup_bus(struct pci_bus *bus) +{ + /* We don't have sub-busses to fixup here */ +} + +unsigned int __init pcibios_assign_all_busses(void) +{ + return 1; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-ddb5074.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,129 @@ +#include +#include +#include +#include + +#include +#include + +#include + +static struct resource extpci_io_resource = { + "pci IO space", + 0x1000, /* leave some room for ISA bus */ + DDB_PCI_IO_SIZE - 1, + IORESOURCE_IO +}; + +static struct resource extpci_mem_resource = { + "pci memory space", + DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */ + DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1, + IORESOURCE_MEM +}; + +extern struct pci_ops ddb5476_ext_pci_ops; + +struct pci_channel mips_pci_channels[] = { + {&ddb5476_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource}, + {NULL, NULL, NULL} +}; + +#define PCI_EXT_INTA 8 +#define PCI_EXT_INTB 9 +#define PCI_EXT_INTC 10 +#define PCI_EXT_INTD 11 +#define PCI_EXT_INTE 12 + +#define MAX_SLOT_NUM 14 + +static unsigned char irq_map[MAX_SLOT_NUM] = { + /* SLOT: 0 */ nile4_to_irq(PCI_EXT_INTE), + /* SLOT: 1 */ nile4_to_irq(PCI_EXT_INTA), + /* SLOT: 2 */ nile4_to_irq(PCI_EXT_INTA), + /* SLOT: 3 */ nile4_to_irq(PCI_EXT_INTB), + /* SLOT: 4 */ nile4_to_irq(PCI_EXT_INTC), + /* SLOT: 5 */ nile4_to_irq(NILE4_INT_UART), + /* SLOT: 6 */ 0xff, + /* SLOT: 7 */ 0xff, + /* SLOT: 8 */ 0xff, + /* SLOT: 9 */ 0xff, + /* SLOT: 10 */ nile4_to_irq(PCI_EXT_INTE), + /* SLOT: 11 */ 0xff, + /* SLOT: 12 */ 0xff, + /* SLOT: 13 */ nile4_to_irq(PCI_EXT_INTE), +}; + +void __init pcibios_fixup_irqs(void) +{ + + struct pci_dev *dev = NULL; + int slot_num; + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + slot_num = PCI_SLOT(dev->devfn); + db_assert(slot_num < MAX_SLOT_NUM); + printk("irq_map[%d]: %02x\n", slot_num, irq_map[slot_num]); + db_assert(irq_map[slot_num] != 0xff); + + pci_write_config_byte(dev, + PCI_INTERRUPT_LINE, + irq_map[slot_num]); + + dev->irq = irq_map[slot_num]; + } +} + +void __init ddb_pci_reset_bus(void) +{ + u32 temp; + + /* + * I am not sure about the "official" procedure, the following + * steps work as far as I know: + * We first set PCI cold reset bit (bit 31) in PCICTRL-H. + * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. + * The same is true for both PCI channels. + */ + temp = ddb_in32(DDB_PCICTRL + 4); + temp |= 0x80000000; + ddb_out32(DDB_PCICTRL + 4, temp); + temp &= ~0xc0000000; + ddb_out32(DDB_PCICTRL + 4, temp); + +} + +unsigned __init int pcibios_assign_all_busses(void) +{ + /* we hope pci_auto has assigned the bus numbers to all buses */ + return 1; +} + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ +} + +void __init pcibios_fixup(void) +{ + struct pci_dev *dev = NULL; + + while ((dev = pci_find_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, + dev)) != NULL) { + /* + * It's nice to have the LEDs on the GPIO pins + * available for debugging + */ + extern struct pci_dev *pci_pmu; + u8 t8; + + pci_pmu = dev; /* for LEDs D2 and D3 */ + /* Program the lines for LEDs D2 and D3 to output */ + pci_read_config_byte(dev, 0x7d, &t8); + t8 |= 0xc0; + pci_write_config_byte(dev, 0x7d, t8); + /* Turn LEDs D2 and D3 off */ + pci_read_config_byte(dev, 0x7e, &t8); + t8 |= 0xc0; + pci_write_config_byte(dev, 0x7e, t8); + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-ddb5476.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,145 @@ +#include +#include +#include +#include +#include + +#include +#include + +#include + +static struct resource extpci_io_resource = { + "pci IO space", + 0x1000, /* leave some room for ISA bus */ + DDB_PCI_IO_SIZE - 1, + IORESOURCE_IO +}; + +static struct resource extpci_mem_resource = { + "pci memory space", + DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */ + DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1, + IORESOURCE_MEM +}; + +extern struct pci_ops ddb5476_ext_pci_ops; + +struct pci_channel mips_pci_channels[] = { + {&ddb5476_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource}, + {NULL, NULL, NULL} +}; + + +/* + * we fix up irqs based on the slot number. + * The first entry is at AD:11. + * + * This does not work for devices on sub-buses yet. + */ + +/* + * temporary + */ + +#define PCI_EXT_INTA 8 +#define PCI_EXT_INTB 9 +#define PCI_EXT_INTC 10 +#define PCI_EXT_INTD 11 +#define PCI_EXT_INTE 12 + +/* + * based on ddb5477 manual page 11 + */ +#define MAX_SLOT_NUM 21 +static unsigned char irq_map[MAX_SLOT_NUM] = { + /* SLOT: 0, AD:11 */ 0xff, + /* SLOT: 1, AD:12 */ 0xff, + /* SLOT: 2, AD:13 */ 9, + /* USB */ + /* SLOT: 3, AD:14 */ 10, + /* PMU */ + /* SLOT: 4, AD:15 */ 0xff, + /* SLOT: 5, AD:16 */ 0x0, + /* P2P bridge */ + /* SLOT: 6, AD:17 */ nile4_to_irq(PCI_EXT_INTB), + /* SLOT: 7, AD:18 */ nile4_to_irq(PCI_EXT_INTC), + /* SLOT: 8, AD:19 */ nile4_to_irq(PCI_EXT_INTD), + /* SLOT: 9, AD:20 */ nile4_to_irq(PCI_EXT_INTA), + /* SLOT: 10, AD:21 */ 0xff, + /* SLOT: 11, AD:22 */ 0xff, + /* SLOT: 12, AD:23 */ 0xff, + /* SLOT: 13, AD:24 */ 14, + /* HD controller, M5229 */ + /* SLOT: 14, AD:25 */ 0xff, + /* SLOT: 15, AD:26 */ 0xff, + /* SLOT: 16, AD:27 */ 0xff, + /* SLOT: 17, AD:28 */ 0xff, + /* SLOT: 18, AD:29 */ 0xff, + /* SLOT: 19, AD:30 */ 0xff, + /* SLOT: 20, AD:31 */ 0xff +}; + +extern int vrc5477_irq_to_irq(int irq); +void __init pcibios_fixup_irqs(void) +{ + struct pci_dev *dev = NULL; + int slot_num; + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + slot_num = PCI_SLOT(dev->devfn); + + /* we don't do IRQ fixup for sub-bus yet */ + if (dev->bus->parent != NULL) { + db_run(printk + ("Don't know how to fixup irq for PCI device %d on sub-bus %d\n", + slot_num, dev->bus->number)); + continue; + } + + db_assert(slot_num < MAX_SLOT_NUM); + db_assert(irq_map[slot_num] != 0xff); + + pci_write_config_byte(dev, + PCI_INTERRUPT_LINE, + irq_map[slot_num]); + dev->irq = irq_map[slot_num]; + } +} + +#if defined(CONFIG_RUNTIME_DEBUG) +extern void jsun_scan_pci_bus(void); +#endif + +void __init ddb_pci_reset_bus(void) +{ + u32 temp; + + /* + * I am not sure about the "official" procedure, the following + * steps work as far as I know: + * We first set PCI cold reset bit (bit 31) in PCICTRL-H. + * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. + * The same is true for both PCI channels. + */ + temp = ddb_in32(DDB_PCICTRL + 4); + temp |= 0x80000000; + ddb_out32(DDB_PCICTRL + 4, temp); + temp &= ~0xc0000000; + ddb_out32(DDB_PCICTRL + 4, temp); + +} + +unsigned __init int pcibios_assign_all_busses(void) +{ + /* we hope pci_auto has assigned the bus numbers to all buses */ + return 1; +} + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ +} + +void __init pcibios_fixup(void) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-ddb5477.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,299 @@ +/* + * PCI code for DDB5477. + * + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +static struct resource extpci_io_resource = { + "ext pci IO space", + DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000, + DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1, + IORESOURCE_IO +}; + +static struct resource extpci_mem_resource = { + "ext pci memory space", + DDB_PCI0_MEM_BASE + 0x100000, + DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1, + IORESOURCE_MEM +}; + +static struct resource iopci_io_resource = { + "io pci IO space", + DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE, + DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1, + IORESOURCE_IO +}; + +static struct resource iopci_mem_resource = { + "ext pci memory space", + DDB_PCI1_MEM_BASE, + DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1, + IORESOURCE_MEM +}; + +extern struct pci_ops ddb5477_ext_pci_ops; +extern struct pci_ops ddb5477_io_pci_ops; + +struct pci_channel mips_pci_channels[] = { + {&ddb5477_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource}, + {&ddb5477_io_pci_ops, &iopci_io_resource, &iopci_mem_resource}, + {NULL, NULL, NULL} +}; + + +/* + * we fix up irqs based on the slot number. + * The first entry is at AD:11. + * Fortunately this works because, although we have two pci buses, + * they all have different slot numbers (except for rockhopper slot 20 + * which is handled below). + * + */ + +/* + * irq mapping : device -> pci int # -> vrc4377 irq# , + * ddb5477 board manual page 4 and vrc5477 manual page 46 + */ + +/* + * based on ddb5477 manual page 11 + */ +#define MAX_SLOT_NUM 21 +static unsigned char irq_map[MAX_SLOT_NUM] = { + /* SLOT: 0, AD:11 */ 0xff, + /* SLOT: 1, AD:12 */ 0xff, + /* SLOT: 2, AD:13 */ 0xff, + /* SLOT: 3, AD:14 */ 0xff, + /* SLOT: 4, AD:15 */ VRC5477_IRQ_INTA, + /* onboard tulip */ + /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTB, + /* slot 1 */ + /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTC, + /* slot 2 */ + /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, + /* slot 3 */ + /* SLOT: 8, AD:19 */ VRC5477_IRQ_INTE, + /* slot 4 */ + /* SLOT: 9, AD:20 */ 0xff, + /* SLOT: 10, AD:21 */ 0xff, + /* SLOT: 11, AD:22 */ 0xff, + /* SLOT: 12, AD:23 */ 0xff, + /* SLOT: 13, AD:24 */ 0xff, + /* SLOT: 14, AD:25 */ 0xff, + /* SLOT: 15, AD:26 */ 0xff, + /* SLOT: 16, AD:27 */ 0xff, + /* SLOT: 17, AD:28 */ 0xff, + /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, + /* vrc5477 ac97 */ + /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, + /* vrc5477 usb peri */ + /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, + /* vrc5477 usb host */ +}; +static unsigned char rockhopperII_irq_map[MAX_SLOT_NUM] = { + /* SLOT: 0, AD:11 */ 0xff, + /* SLOT: 1, AD:12 */ VRC5477_IRQ_INTB, + /* onboard AMD PCNET */ + /* SLOT: 2, AD:13 */ 0xff, + /* SLOT: 3, AD:14 */ 0xff, + /* SLOT: 4, AD:15 */ 14, + /* M5229 ide ISA irq */ + /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTD, + /* slot 3 */ + /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTA, + /* slot 4 */ + /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, + /* slot 5 */ + /* SLOT: 8, AD:19 */ 0, + /* M5457 modem nop */ + /* SLOT: 9, AD:20 */ VRC5477_IRQ_INTA, + /* slot 2 */ + /* SLOT: 10, AD:21 */ 0xff, + /* SLOT: 11, AD:22 */ 0xff, + /* SLOT: 12, AD:23 */ 0xff, + /* SLOT: 13, AD:24 */ 0xff, + /* SLOT: 14, AD:25 */ 0xff, + /* SLOT: 15, AD:26 */ 0xff, + /* SLOT: 16, AD:27 */ 0xff, + /* SLOT: 17, AD:28 */ 0, + /* M7101 PMU nop */ + /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, + /* vrc5477 ac97 */ + /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, + /* vrc5477 usb peri */ + /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, + /* vrc5477 usb host */ +}; + +void __init pcibios_fixup_irqs(void) +{ + struct pci_dev *dev = NULL; + int slot_num; + unsigned char *slot_irq_map; + unsigned char irq; + + if (mips_machtype == MACH_NEC_ROCKHOPPERII) + slot_irq_map = rockhopperII_irq_map; + else + slot_irq_map = irq_map; + + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + slot_num = PCI_SLOT(dev->devfn); + irq = slot_irq_map[slot_num]; + + db_assert(slot_num < MAX_SLOT_NUM); + + db_assert(irq != 0xff); + + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); + + dev->irq = irq; + + if (mips_machtype == MACH_NEC_ROCKHOPPERII) { + /* hack to distinquish overlapping slot 20s, one + * on bus 0 (ALI USB on the M1535 on the backplane), + * and one on bus 2 (NEC USB controller on the CPU board) + * Make the M1535 USB - ISA IRQ number 9. + */ + if (slot_num == 20 && dev->bus->number == 0) { + pci_write_config_byte(dev, + PCI_INTERRUPT_LINE, + 9); + dev->irq = 9; + } + } + + } +} + +#if defined(CONFIG_RUNTIME_DEBUG) +extern void jsun_scan_pci_bus(void); +extern void jsun_assign_pci_resource(void); +#endif +void ddb_pci_reset_bus(void) +{ + u32 temp; + + /* + * I am not sure about the "official" procedure, the following + * steps work as far as I know: + * We first set PCI cold reset bit (bit 31) in PCICTRL-H. + * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. + * The same is true for both PCI channels. + */ + temp = ddb_in32(DDB_PCICTL0_H); + temp |= 0x80000000; + ddb_out32(DDB_PCICTL0_H, temp); + temp &= ~0xc0000000; + ddb_out32(DDB_PCICTL0_H, temp); + + temp = ddb_in32(DDB_PCICTL1_H); + temp |= 0x80000000; + ddb_out32(DDB_PCICTL1_H, temp); + temp &= ~0xc0000000; + ddb_out32(DDB_PCICTL1_H, temp); +} + +unsigned __init int pcibios_assign_all_busses(void) +{ + /* we hope pci_auto has assigned the bus numbers to all buses */ + return 1; +} + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ +} + +/* + * fixup baseboard AMD chip so that tx does not underflow. + * bcr_18 |= 0x0800 + * This sets NOUFLO bit which makes tx not start until whole pkt + * is fetched to the chip. + */ +#define PCNET32_WIO_RDP 0x10 +#define PCNET32_WIO_RAP 0x12 +#define PCNET32_WIO_RESET 0x14 +#define PCNET32_WIO_BDP 0x16 +void __init fix_amd_lance(struct pci_dev *dev) +{ + unsigned long ioaddr; + u16 temp; + + ioaddr = pci_resource_start(dev, 0); + + inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */ + + /* bcr_18 |= 0x0800 */ + outw(18, ioaddr + PCNET32_WIO_RAP); + temp = inw(ioaddr + PCNET32_WIO_BDP); + temp |= 0x0800; + outw(18, ioaddr + PCNET32_WIO_RAP); + outw(temp, ioaddr + PCNET32_WIO_BDP); +} + +void __init pcibios_fixup(void) +{ + struct pci_dev *dev = NULL; + + if (mips_machtype != MACH_NEC_ROCKHOPPERII) + return; + + +#define M1535_CONFIG_PORT 0x3f0 +#define M1535_INDEX_PORT 0x3f0 +#define M1535_DATA_PORT 0x3f1 + + printk("Configuring ALI M1535 Super I/O mouse irq.\n"); + + request_region(M1535_CONFIG_PORT, 2, "M1535 Super I/O config"); + + /* Enter config mode. */ + outb(0x51, M1535_CONFIG_PORT); + outb(0x23, M1535_CONFIG_PORT); + + /* Select device 0x07. */ + outb(0x07, M1535_INDEX_PORT); + outb(0x07, M1535_DATA_PORT); + + /* Set mouse irq (register 0x72) to 12. */ + outb(0x72, M1535_INDEX_PORT); + outb(0x0c, M1535_DATA_PORT); + + /* Exit config mode. */ + outb(0xbb, M1535_CONFIG_PORT); + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + if (dev->vendor == PCI_VENDOR_ID_AL) + if (dev->device == PCI_DEVICE_ID_AL_M1535 + || dev->device == PCI_DEVICE_ID_AL_M1533) { + u8 old; + printk + ("Enabling ALI M1533/35 PS2 keyboard/mouse.\n"); + pci_read_config_byte(dev, 0x41, &old); + pci_write_config_byte(dev, 0x41, old | 0xd0); + } + + if (dev->vendor == PCI_VENDOR_ID_AMD && + dev->device == PCI_DEVICE_ID_AMD_LANCE) + fix_amd_lance(dev); + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-hplj.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,252 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * SNI specific PCI support for RM200/RM300. + * + * Copyright (C) 1997 - 2000 Ralf Baechle + */ +#include +#include +#include +#include +#include +#include +#include + +volatile u32 *pci_config_address_reg = (volatile u32 *) 0xfdead000; +volatile u32 *pci_config_data_reg = (volatile u32 *) 0xfdead000; + + + +#define cfgaddr(dev, where) (((dev->bus->number & 0xff) << 0x10) | \ + ((dev->devfn & 0xff) << 0x08) | \ + (where & 0xfc)) + +/* + * We can't address 8 and 16 bit words directly. Instead we have to + * read/write a 32bit word and mask/modify the data we actually want. + */ +static int pcimt_read_config_byte(struct pci_dev *dev, + int where, unsigned char *val) +{ + *pci_config_address_reg = cfgaddr(dev, where); + *val = + (le32_to_cpu(*pci_config_data_reg) >> ((where & 3) << 3)) & + 0xff; + //printk("pci_read_byte 0x%x == 0x%x\n", where, *val); + return PCIBIOS_SUCCESSFUL; +} + +static int pcimt_read_config_word(struct pci_dev *dev, + int where, unsigned short *val) +{ + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + *pci_config_address_reg = cfgaddr(dev, where); + *val = + (le32_to_cpu(*pci_config_data_reg) >> ((where & 3) << 3)) & + 0xffff; + //printk("pci_read_word 0x%x == 0x%x\n", where, *val); + return PCIBIOS_SUCCESSFUL; +} + +int pcimt_read_config_dword(struct pci_dev *dev, + int where, unsigned int *val) +{ + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + *pci_config_address_reg = cfgaddr(dev, where); + *val = le32_to_cpu(*pci_config_data_reg); + //printk("pci_read_dword 0x%x == 0x%x\n", where, *val); + return PCIBIOS_SUCCESSFUL; +} + +static int pcimt_write_config_byte(struct pci_dev *dev, + int where, unsigned char val) +{ + *pci_config_address_reg = cfgaddr(dev, where); + *(volatile u8 *) (((int) pci_config_data_reg) + (where & 3)) = val; + //printk("pci_write_byte 0x%x = 0x%x\n", where, val); + return PCIBIOS_SUCCESSFUL; +} + +static int pcimt_write_config_word(struct pci_dev *dev, + int where, unsigned short val) +{ + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + *pci_config_address_reg = cfgaddr(dev, where); + *(volatile u16 *) (((int) pci_config_data_reg) + (where & 2)) = + le16_to_cpu(val); + //printk("pci_write_word 0x%x = 0x%x\n", where, val); + return PCIBIOS_SUCCESSFUL; +} + +int pcimt_write_config_dword(struct pci_dev *dev, + int where, unsigned int val) +{ + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + *pci_config_address_reg = cfgaddr(dev, where); + *pci_config_data_reg = le32_to_cpu(val); + //printk("pci_write_dword 0x%x = 0x%x\n", where, val); + return PCIBIOS_SUCCESSFUL; +} + + + +struct pci_ops hp_pci_ops = { + pcimt_read_config_byte, + pcimt_read_config_word, + pcimt_read_config_dword, + pcimt_write_config_byte, + pcimt_write_config_word, + pcimt_write_config_dword +}; + + +struct pci_channel mips_pci_channels[] = { + {&hp_pci_ops, &ioport_resource, &iomem_resource}, + {NULL, NULL, NULL} +}; + +unsigned __init int pcibios_assign_all_busses(void) +{ + return 1; +} + +void __init pcibios_fixup(void) +{ +} + + +void __init pcibios_fixup_irqs(void) +{ + struct pci_dev *dev = NULL; + int slot_num; + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + slot_num = PCI_SLOT(dev->devfn); + switch (slot_num) { + case 2: + dev->irq = 3; + break; + case 3: + dev->irq = 4; + break; + case 4: + dev->irq = 5; + break; + default: + break; + } + } +} + +#define IO_MEM_LOGICAL_START 0x3e000000 +#define IO_MEM_LOGICAL_END 0x3fefffff + +#define IO_PORT_LOGICAL_START 0x3ff00000 +#define IO_PORT_LOGICAL_END 0x3fffffff + + +#define IO_MEM_VIRTUAL_OFFSET 0xb0000000 +#define IO_PORT_VIRTUAL_OFFSET 0xb0000000 + +#define ONE_MEG (1024 * 1024) + +void __init pci_setup(void) +{ + u32 pci_regs_base_offset = 0xfdead000; + + switch (GetAsicId()) { + case AndrosAsic: + pci_regs_base_offset = 0xbff80000; + break; + case HarmonyAsic: + pci_regs_base_offset = 0xbff70000; + break; + default: + printk("ERROR: PCI does not support %s Asic\n", + GetAsicName()); + while (1); + break; + } + + // set bus stat/command reg + // REVIST this setting may need vary depending on the hardware + *((volatile unsigned int *) (pci_regs_base_offset | 0x0004)) = + 0x38000007; + + + iomem_resource.start = + IO_MEM_LOGICAL_START + IO_MEM_VIRTUAL_OFFSET; + iomem_resource.end = IO_MEM_LOGICAL_END + IO_MEM_VIRTUAL_OFFSET; + + ioport_resource.start = + IO_PORT_LOGICAL_START + IO_PORT_VIRTUAL_OFFSET; + ioport_resource.end = IO_PORT_LOGICAL_END + IO_PORT_VIRTUAL_OFFSET; + + // KLUDGE (mips_io_port_base is screwed up, we've got to work around it here) + // by letting both low (illegal) and high (legal) addresses appear in pci io space + ioport_resource.start = 0x0; + + set_io_port_base(IO_PORT_LOGICAL_START + IO_PORT_VIRTUAL_OFFSET); + + // map the PCI address space + // global map - all levels & processes can access + // except that the range is outside user space + // parameters: lo0, lo1, hi, pagemask + // lo indicates physical page, hi indicates virtual address + add_wired_entry((IO_MEM_LOGICAL_START >> 6) | 0x17, + ((IO_MEM_LOGICAL_START + + (16 * ONE_MEG)) >> 6) | 0x17, 0xee000000, + PM_16M); + + + // These are used in pci r/w routines so need to preceed bus scan + pci_config_data_reg = (u32 *) (((u32) mips_io_port_base) | 0xcfc); + pci_config_address_reg = + (u32 *) (((u32) pci_regs_base_offset) | 0xcf8); + +} + + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ + int pos; + int bases; + + printk("adjusting pci device: %s\n", dev->name); + + switch (dev->hdr_type) { + case PCI_HEADER_TYPE_NORMAL: + bases = 6; + break; + case PCI_HEADER_TYPE_BRIDGE: + bases = 2; + break; + case PCI_HEADER_TYPE_CARDBUS: + bases = 1; + break; + default: + bases = 0; + break; + } + for (pos = 0; pos < bases; pos++) { + struct resource *res = &dev->resource[pos]; + if (res->start >= IO_MEM_LOGICAL_START && + res->end <= IO_MEM_LOGICAL_END) { + res->start += IO_MEM_VIRTUAL_OFFSET; + res->end += IO_MEM_VIRTUAL_OFFSET; + } + if (res->start >= IO_PORT_LOGICAL_START && + res->end <= IO_PORT_LOGICAL_END) { + res->start += IO_PORT_VIRTUAL_OFFSET; + res->end += IO_PORT_VIRTUAL_OFFSET; + } + } + +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-ip27.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,391 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Max #PCI busses we can handle; ie, max #PCI bridges. + */ +#define MAX_PCI_BUSSES 40 + +/* + * Max #PCI devices (like scsi controllers) we handle on a bus. + */ +#define MAX_DEVICES_PER_PCIBUS 8 + +/* + * No locking needed until PCI initialization is done parallely. + */ +int irqstore[MAX_PCI_BUSSES][MAX_DEVICES_PER_PCIBUS]; +int lastirq = BASE_PCI_IRQ; + +/* + * Translate from irq to software PCI bus number and PCI slot. + */ +int irq_to_bus[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS]; +int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS]; + +/* + * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is + * not really documented, so right now I can't write code which uses it. + * Therefore we use type 0 accesses for now even though they won't work + * correcly for PCI-to-PCI bridges. + */ +#define CF0_READ_PCI_CFG(bus,devfn,where,value,bm,mask) \ +do { \ + bridge_t *bridge; \ + int slot = PCI_SLOT(devfn); \ + int fn = PCI_FUNC(devfn); \ + volatile u32 *addr; \ + u32 cf, __bit; \ + unsigned int bus_id = (unsigned) bus->number; \ + \ + bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], \ + bus_to_wid[bus_id]); \ + \ + __bit = (((where) & (bm)) << 3); \ + addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; \ + if (get_dbe(cf, addr)) \ + return PCIBIOS_DEVICE_NOT_FOUND; \ + *value = (cf >> __bit) & (mask); \ + return PCIBIOS_SUCCESSFUL; \ +} while (0) + +static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * value) +{ + u32 vprod; + + CF0_READ_PCI_CFG(bus, devfn, PCI_VENDOR_ID, &vprod, 0, 0xffffffff); + if (vprod == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)) + && ((where >= 0x14 && where < 0x40) || (where >= 0x48))) { + *value = 0; + return PCIBIOS_SUCCESSFUL; + } + + if (size == 1) + CF0_READ_PCI_CFG(bus, devfn, where, (u8 *) value, 3, 0xff); + else if (size == 2) + CF0_READ_PCI_CFG(bus, devfn, where, (u16 *) value, 2, + 0xffff); + else + CF0_READ_PCI_CFG(bus, devfn, where, (u32 *) value, 0, + 0xffffffff); +} + +#define CF0_WRITE_PCI_CFG(bus,devfn,where,value,bm,mask) \ +do { \ + bridge_t *bridge; \ + int slot = PCI_SLOT(devfn); \ + int fn = PCI_FUNC(devfn); \ + volatile u32 *addr; \ + u32 cf, __bit; \ + unsigned int bus_id = (unsigned) bus->number; \ + \ + bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], \ + bus_to_wid[bus_id]); \ + \ + __bit = (((where) & (bm)) << 3); \ + addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; \ + if (get_dbe(cf, addr)) \ + return PCIBIOS_DEVICE_NOT_FOUND; \ + cf &= (~mask); \ + cf |= (value); \ + put_dbe(cf, addr); \ + return PCIBIOS_SUCCESSFUL; \ +} while (0) + +static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + u32 vprod; + + CF0_READ_PCI_CFG(bus, devfn, PCI_VENDOR_ID, &vprod, 0, 0xffffffff); + if (vprod == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)) + && ((where >= 0x14 && where < 0x40) || (where >= 0x48))) { + return PCIBIOS_SUCCESSFUL; + } + + if (size == 1) + CF0_WRITE_PCI_CFG(bus, devfn, where, (u8) value, 3, 0xff); + else if (size == 2) + CF0_WRITE_PCI_CFG(bus, devfn, where, (u16) value, 2, + 0xffff); + else + CF0_WRITE_PCI_CFG(bus, devfn, where, (u32) value, 0, + 0xffffffff); +} + +static struct pci_ops bridge_pci_ops = { + .read = pci_conf0_read_config, + .write = pci_conf0_write_config, +}; + +static int __init pcibios_init(void) +{ + struct pci_ops *ops = &bridge_pci_ops; + int i; + + ioport_resource.end = ~0UL; + + for (i = 0; i < num_bridges; i++) { + printk("PCI: Probing PCI hardware on host bus %2d.\n", i); + pci_scan_bus(i, ops, NULL); + } + + return 0; +} + +subsys_initcall(pcibios_init); + +static inline u8 bridge_swizzle(u8 pin, u8 slot) +{ + return (((pin - 1) + slot) % 4) + 1; +} + +static u8 __devinit pci_swizzle(struct pci_dev *dev, u8 * pinp) +{ + u8 pin = *pinp; + + while (dev->bus->self) { /* Move up the chain of bridges. */ + pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); + dev = dev->bus->self; + } + *pinp = pin; + + return PCI_SLOT(dev->devfn); +} + +/* + * All observed requests have pin == 1. We could have a global here, that + * gets incremented and returned every time - unfortunately, pci_map_irq + * may be called on the same device over and over, and need to return the + * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7]. + * + * A given PCI device, in general, should be able to intr any of the cpus + * on any one of the hubs connected to its xbow. + */ +static int __devinit pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + if ((dev->bus->number >= MAX_PCI_BUSSES) + || (pin != 1) + || (slot >= MAX_DEVICES_PER_PCIBUS)) + panic("Increase supported PCI busses %d,%d,%d", + dev->bus->number, slot, pin); + + /* + * Already assigned? Then return previously assigned value ... + */ + if (irqstore[dev->bus->number][slot]) + return irqstore[dev->bus->number][slot]; + + irq_to_bus[lastirq] = dev->bus->number; + irq_to_slot[lastirq] = slot; + irqstore[dev->bus->number][slot] = lastirq; + lastirq++; + return lastirq - 1; +} + +void __init pcibios_update_irq(struct pci_dev *dev, int irq) +{ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); +} + +void __devinit pcibios_fixup_bus(struct pci_bus *b) +{ + pci_fixup_irqs(pci_swizzle, pci_map_irq); +} + +int pcibios_enable_device(struct pci_dev *dev, int mask) +{ + /* Not needed, since we enable all devices at startup. */ + return 0; +} + +void pcibios_align_resource(void *data, struct resource *res, + unsigned long size, unsigned long align) +{ +} + +unsigned int pcibios_assign_all_busses(void) +{ + return 0; +} + +char *__devinit pcibios_setup(char *str) +{ + /* Nothing to do for now. */ + + return str; +} + +/* + * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses + * to find the slot number in sense of the bridge device register. + * XXX This also means multiple devices might rely on conflicting bridge + * settings. + */ + +static void __init pci_disable_swapping(struct pci_dev *dev) +{ + unsigned int bus_id = (unsigned) dev->bus->number; + bridge_t *bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], + bus_to_wid[bus_id]); + int slot = PCI_SLOT(dev->devfn); + + /* Turn off byte swapping */ + bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR; + bridge->b_widget.w_tflush; /* Flush */ +} + +static void __init pci_enable_swapping(struct pci_dev *dev) +{ + unsigned int bus_id = (unsigned) dev->bus->number; + bridge_t *bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], + bus_to_wid[bus_id]); + int slot = PCI_SLOT(dev->devfn); + + /* Turn on byte swapping */ + bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR; + bridge->b_widget.w_tflush; /* Flush */ +} + +static void __init pci_fixup_ioc3(struct pci_dev *d) +{ + unsigned long bus_id = (unsigned) d->bus->number; + + printk("PCI: Fixing base addresses for IOC3 device %s\n", + d->slot_name); + + d->resource[0].start |= NODE_OFFSET(bus_to_nid[bus_id]); + d->resource[0].end |= NODE_OFFSET(bus_to_nid[bus_id]); + + pci_disable_swapping(d); +} + +static void __init pci_fixup_isp1020(struct pci_dev *d) +{ + unsigned short command; + + d->resource[0].start |= + ((unsigned long) (bus_to_nid[d->bus->number]) << 32); + printk("PCI: Fixing isp1020 in [bus:slot.fn] %s\n", d->slot_name); + + /* + * Configure device to allow bus mastering, i/o and memory mapping. + * Older qlogicisp driver expects to have the IO space enable + * bit set. Things stop working if we program the controllers as not + * having PCI_COMMAND_MEMORY, so we have to fudge the mem_flags. + */ + + pci_set_master(d); + pci_read_config_word(d, PCI_COMMAND, &command); + command |= PCI_COMMAND_MEMORY; + command |= PCI_COMMAND_IO; + pci_write_config_word(d, PCI_COMMAND, command); + d->resource[1].flags |= 1; + + pci_enable_swapping(d); +} + +static void __init pci_fixup_isp2x00(struct pci_dev *d) +{ + unsigned int bus_id = (unsigned) d->bus->number; + bridge_t *bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], + bus_to_wid[bus_id]); + bridgereg_t devreg; + int i; + int slot = PCI_SLOT(d->devfn); + unsigned int start; + unsigned short command; + + printk("PCI: Fixing isp2x00 in [bus:slot.fn] %s\n", d->slot_name); + + /* set the resource struct for this device */ + start = (u32) (u64) bridge; /* yes, we want to lose the upper 32 bits here */ + start |= BRIDGE_DEVIO(slot); + + d->resource[0].start = start; + d->resource[0].end = d->resource[0].start + 0xff; + d->resource[0].flags = IORESOURCE_IO; + + d->resource[1].start = start; + d->resource[1].end = d->resource[0].start + 0xfff; + d->resource[1].flags = IORESOURCE_MEM; + + /* + * set the bridge device(x) reg for this device + */ + devreg = bridge->b_device[slot].reg; + /* point device(x) to it appropriate small window */ + devreg &= ~BRIDGE_DEV_OFF_MASK; + devreg |= (start >> 20) & BRIDGE_DEV_OFF_MASK; + bridge->b_device[slot].reg = devreg; + + pci_enable_swapping(d); + + /* set card's base addr reg */ + //pci_write_config_dword(d, PCI_BASE_ADDRESS_0, 0x500001); + //pci_write_config_dword(d, PCI_BASE_ADDRESS_1, 0x8b00000); + //pci_write_config_dword(d, PCI_ROM_ADDRESS, 0x8b20000); + + /* I got these from booting irix on system... */ + pci_write_config_dword(d, PCI_BASE_ADDRESS_0, 0x200001); + //pci_write_config_dword(d, PCI_BASE_ADDRESS_1, 0xf800000); + pci_write_config_dword(d, PCI_ROM_ADDRESS, 0x10200000); + + pci_write_config_dword(d, PCI_BASE_ADDRESS_1, start); + //pci_write_config_dword(d, PCI_ROM_ADDRESS, (start | 0x20000)); + + /* set cache line size */ + pci_write_config_dword(d, PCI_CACHE_LINE_SIZE, 0xf080); + + /* set pci bus timeout */ + bridge->b_bus_timeout |= BRIDGE_BUS_PCI_RETRY_HLD(0x3); + bridge->b_wid_tflush; + printk("PCI: bridge bus timeout= 0x%x \n", bridge->b_bus_timeout); + + /* set host error field */ + bridge->b_int_host_err = 0x44; + bridge->b_wid_tflush; + + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + for (i = 0; i < 8; i++) + printk("PCI: device(%d)= 0x%x\n", i, + bridge->b_device[i].reg); + + /* configure device to allow bus mastering, i/o and memory mapping */ + pci_set_master(d); + pci_read_config_word(d, PCI_COMMAND, &command); + command |= PCI_COMMAND_MEMORY; + command |= PCI_COMMAND_IO; + pci_write_config_word(d, PCI_COMMAND, command); + /*d->resource[1].flags |= 1; */ +} + +struct pci_fixup pcibios_fixups[] = { + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, + pci_fixup_ioc3}, + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, + PCI_DEVICE_ID_QLOGIC_ISP1020, + pci_fixup_isp1020}, + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, + PCI_DEVICE_ID_QLOGIC_ISP2100, + pci_fixup_isp2x00}, + {PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, + PCI_DEVICE_ID_QLOGIC_ISP2200, + pci_fixup_isp2x00}, + {0} +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-ip32.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,457 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000, 2001 Keith M Wesolowski + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#undef DEBUG_MACE_PCI + +/* + * O2 has up to 5 PCI devices connected into the MACE bridge. The device + * map looks like this: + * + * 0 aic7xxx 0 + * 1 aic7xxx 1 + * 2 expansion slot + * 3 N/C + * 4 N/C + */ + +#define chkslot(_bus,_devfn) \ +do { \ + if ((_bus)->number > 0 || PCI_SLOT (_devfn) < 1 \ + || PCI_SLOT (_devfn) > 3) \ + return PCIBIOS_DEVICE_NOT_FOUND; \ +} while (0) + +#define mkaddr(_devfn, where) \ +((((_devfn) & 0xffUL) << 8) | ((where) & 0xfcUL)) + +void macepci_error(int irq, void *dev, struct pt_regs *regs); + +static int macepci_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + switch (size) { + case 1: + *val = 0xff; + chkslot(bus, devfn); + mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where)); + *val = + mace_read_8(MACEPCI_CONFIG_DATA + + ((where & 3UL) ^ 3UL)); + + return PCIBIOS_SUCCESSFUL; + + case 2: + *val = 0xffff; + chkslot(bus, devfn); + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where)); + *val = + mace_read_16(MACEPCI_CONFIG_DATA + + ((where & 2UL) ^ 2UL)); + + return PCIBIOS_SUCCESSFUL; + + case 4: + *val = 0xffffffff; + chkslot(bus, devfn); + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where)); + *val = mace_read_32(MACEPCI_CONFIG_DATA); + + return PCIBIOS_SUCCESSFUL; + } +} + +static int macepci_write_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + switch (size) { + case 1: + chkslot(bus, devfn); + mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where)); + mace_write_8(MACEPCI_CONFIG_DATA + ((where & 3UL) ^ 3UL), + val); + + return PCIBIOS_SUCCESSFUL; + + case 2: + chkslot(bus, devfn); + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where)); + mace_write_16(MACEPCI_CONFIG_DATA + ((where & 2UL) ^ 2UL), + val); + + return PCIBIOS_SUCCESSFUL; + + case 4: + chkslot(bus, devfn); + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + mace_write_32(MACEPCI_CONFIG_ADDR, mkaddr(devfn, where)); + mace_write_32(MACEPCI_CONFIG_DATA, val); + + return PCIBIOS_SUCCESSFUL; + } +} + +static struct pci_ops macepci_ops = { + .read = macepci_read_config, + .write = macepci_write_config, +}; + +struct pci_fixup pcibios_fixups[] = { {0} }; + +static int __init pcibios_init(void) +{ + struct pci_dev *dev = NULL; + u32 start, size; + u16 cmd; + u32 base_io = 0x3000; /* The first i/o address to assign after SCSI */ + u32 base_mem = 0x80100000; /* Likewise */ + u32 rev = mace_read_32(MACEPCI_REV); + int i; + + printk("MACE: PCI rev %d detected at %016lx\n", rev, + (u64) MACE_BASE + MACE_PCI); + + /* These are *bus* addresses */ + ioport_resource.start = 0; + ioport_resource.end = 0xffffffffUL; + iomem_resource.start = 0x80000000UL; + iomem_resource.end = 0xffffffffUL; + + /* Clear any outstanding errors and enable interrupts */ + mace_write_32(MACEPCI_ERROR_ADDR, 0); + mace_write_32(MACEPCI_ERROR_FLAGS, 0); + mace_write_32(MACEPCI_CONTROL, 0xff008500); + crime_write_64(CRIME_HARD_INT, 0UL); + crime_write_64(CRIME_SOFT_INT, 0UL); + crime_write_64(CRIME_INT_STAT, 0x000000000000ff00UL); + + if (request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0, + "MACE PCI error", NULL)) + panic("PCI bridge can't get interrupt; can't happen."); + + pci_scan_bus(0, &macepci_ops, NULL); + +#ifdef DEBUG_MACE_PCI + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + printk("Device: %d/%d/%d ARCS-assigned bus resource map\n", + dev->bus->number, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn)); + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + if (dev->resource[i].start == 0) + continue; + printk("%d: %016lx - %016lx (flags %04lx)\n", + i, dev->resource[i].start, + dev->resource[i].end, + dev->resource[i].flags); + } + } +#endif + /* + * Assign sane resources to and enable all devices. The requirement + * for the SCSI controllers is well-known: a 256-byte I/O region + * which we must assign, and a 1-page memory region which is + * assigned by the system firmware. + */ + dev = NULL; + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + switch (PCI_SLOT(dev->devfn)) { + case 1: /* SCSI bus 0 */ + dev->resource[0].start = 0x1000UL; + dev->resource[0].end = 0x10ffUL; + break; + case 2: /* SCSI bus 1 */ + dev->resource[0].start = 0x2000UL; + dev->resource[0].end = 0x20ffUL; + break; + default: /* Slots - I guess we have only 1 */ + for (i = 0; i < 6; i++) { + size = dev->resource[i].end + - dev->resource[i].start; + if (!size + || !(dev->resource[i].flags + & (IORESOURCE_IO | + IORESOURCE_MEM))) { + dev->resource[i].start = + dev->resource[i].end = 0UL; + continue; + } + if (dev->resource[i].flags & IORESOURCE_IO) { + dev->resource[i].start = base_io; + base_io += PAGE_ALIGN(size); + } else { + dev->resource[i].start = base_mem; + base_mem += 0x100000UL; + } + dev->resource[i].end = + dev->resource[i].start + size; + } + break; + } + for (i = 0; i < 6; i++) { + if (dev->resource[i].start == 0) + continue; + start = dev->resource[i].start; + if (dev->resource[i].flags & IORESOURCE_IO) + start |= 1; + pci_write_config_dword(dev, + PCI_BASE_ADDRESS_0 + + (i << 2), (u32) start); + } + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x20); + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x30); + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= + (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE | + PCI_COMMAND_PARITY); + pci_write_config_word(dev, PCI_COMMAND, cmd); + pci_set_master(dev); + } + /* + * Fixup O2 PCI slot. Bad hack. + */ +/* devtag = pci_make_tag(0, 0, 3, 0); + + slot = macepci_conf_read(0, devtag, PCI_COMMAND_STATUS_REG); + slot |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; + macepci_conf_write(0, devtag, PCI_COMMAND_STATUS_REG, slot); + + slot = macepci_conf_read(0, devtag, PCI_MAPREG_START); + if (slot == 0xffffffe1) + macepci_conf_write(0, devtag, PCI_MAPREG_START, 0x00001000); + + slot = macepci_conf_read(0, devtag, PCI_MAPREG_START + (2 << 2)); + if ((slot & 0xffff0000) == 0) { + slot += 0x00010000; + macepci_conf_write(0, devtag, PCI_MAPREG_START + (2 << 2), + 0x00000000); + } + */ +#ifdef DEBUG_MACE_PCI + printk("Triggering PCI bridge interrupt...\n"); + mace_write_32(MACEPCI_ERROR_FLAGS, MACEPCI_ERROR_INTERRUPT_TEST); + + dev = NULL; + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + printk("Device: %d/%d/%d final bus resource map\n", + dev->bus->number, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn)); + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + if (dev->resource[i].start == 0) + continue; + printk("%d: %016lx - %016lx (flags %04lx)\n", + i, dev->resource[i].start, + dev->resource[i].end, + dev->resource[i].flags); + } + } +#endif + + return 0; +} + +subsys_initcall(pcibios_init); + +/* + * Given a PCI slot number (a la PCI_SLOT(...)) and the interrupt pin of + * the device (1-4 => A-D), tell what irq to use. Note that we don't + * in theory have slots 4 and 5, and we never normally use the shared + * irqs. I suppose a device without a pin A will thank us for doing it + * right if there exists such a broken piece of crap. + */ +static int __devinit macepci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + chkslot(dev->bus, dev->devfn); + if (pin == 0) + pin = 1; + switch (slot) { + case 1: + return MACEPCI_SCSI0_IRQ; + case 2: + return MACEPCI_SCSI1_IRQ; + case 3: + switch (pin) { + case 2: + return MACEPCI_SHARED0_IRQ; + case 3: + return MACEPCI_SHARED1_IRQ; + case 4: + return MACEPCI_SHARED2_IRQ; + case 1: + default: + return MACEPCI_SLOT0_IRQ; + } + case 4: + switch (pin) { + case 2: + return MACEPCI_SHARED2_IRQ; + case 3: + return MACEPCI_SHARED0_IRQ; + case 4: + return MACEPCI_SHARED1_IRQ; + case 1: + default: + return MACEPCI_SLOT1_IRQ; + } + return MACEPCI_SLOT1_IRQ; + case 5: + switch (pin) { + case 2: + return MACEPCI_SHARED1_IRQ; + case 3: + return MACEPCI_SHARED2_IRQ; + case 4: + return MACEPCI_SHARED0_IRQ; + case 1: + default: + return MACEPCI_SLOT2_IRQ; + } + default: + return 0; + } +} + +/* + * It's not entirely clear what this does in a system with no bridges. + * In any case, bridges are not supported by Linux in O2. + */ +static u8 __init macepci_swizzle(struct pci_dev *dev, u8 * pinp) +{ + if (PCI_SLOT(dev->devfn) == 2) + *pinp = 2; + else + *pinp = 1; + return PCI_SLOT(dev->devfn); +} + +/* All devices are enabled during initialization. */ +int pcibios_enable_device(struct pci_dev *dev, int mask) +{ + return PCIBIOS_SUCCESSFUL; +} + +char *__init pcibios_setup(char *str) +{ + return str; +} + +void pcibios_align_resource(void *data, struct resource *res, + unsigned long size, unsigned long align) +{ +} + +void __init pcibios_update_irq(struct pci_dev *dev, int irq) +{ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); +} + +void __devinit pcibios_fixup_bus(struct pci_bus *b) +{ + pci_fixup_irqs(macepci_swizzle, macepci_map_irq); +} + +/* + * Handle errors from the bridge. This includes master and target aborts, + * various command and address errors, and the interrupt test. This gets + * registered on the bridge error irq. It's conceivable that some of these + * conditions warrant a panic. Anybody care to say which ones? + */ +void macepci_error(int irq, void *dev, struct pt_regs *regs) +{ + u32 flags, error_addr; + char space; + + flags = mace_read_32(MACEPCI_ERROR_FLAGS); + error_addr = mace_read_32(MACEPCI_ERROR_ADDR); + + if (flags & MACEPCI_ERROR_MEMORY_ADDR) + space = 'M'; + else if (flags & MACEPCI_ERROR_CONFIG_ADDR) + space = 'C'; + else + space = 'X'; + + if (flags & MACEPCI_ERROR_MASTER_ABORT) { + printk("MACEPCI: Master abort at 0x%08x (%c)\n", + error_addr, space); + mace_write_32(MACEPCI_ERROR_FLAGS, + flags & ~MACEPCI_ERROR_MASTER_ABORT); + } + if (flags & MACEPCI_ERROR_TARGET_ABORT) { + printk("MACEPCI: Target abort at 0x%08x (%c)\n", + error_addr, space); + mace_write_32(MACEPCI_ERROR_FLAGS, + flags & ~MACEPCI_ERROR_TARGET_ABORT); + } + if (flags & MACEPCI_ERROR_DATA_PARITY_ERR) { + printk("MACEPCI: Data parity error at 0x%08x (%c)\n", + error_addr, space); + mace_write_32(MACEPCI_ERROR_FLAGS, flags + & ~MACEPCI_ERROR_DATA_PARITY_ERR); + } + if (flags & MACEPCI_ERROR_RETRY_ERR) { + printk("MACEPCI: Retry error at 0x%08x (%c)\n", error_addr, + space); + mace_write_32(MACEPCI_ERROR_FLAGS, flags + & ~MACEPCI_ERROR_RETRY_ERR); + } + if (flags & MACEPCI_ERROR_ILLEGAL_CMD) { + printk("MACEPCI: Illegal command at 0x%08x (%c)\n", + error_addr, space); + mace_write_32(MACEPCI_ERROR_FLAGS, + flags & ~MACEPCI_ERROR_ILLEGAL_CMD); + } + if (flags & MACEPCI_ERROR_SYSTEM_ERR) { + printk("MACEPCI: System error at 0x%08x (%c)\n", + error_addr, space); + mace_write_32(MACEPCI_ERROR_FLAGS, flags + & ~MACEPCI_ERROR_SYSTEM_ERR); + } + if (flags & MACEPCI_ERROR_PARITY_ERR) { + printk("MACEPCI: Parity error at 0x%08x (%c)\n", + error_addr, space); + mace_write_32(MACEPCI_ERROR_FLAGS, + flags & ~MACEPCI_ERROR_PARITY_ERR); + } + if (flags & MACEPCI_ERROR_OVERRUN) { + printk("MACEPCI: Overrun error at 0x%08x (%c)\n", + error_addr, space); + mace_write_32(MACEPCI_ERROR_FLAGS, flags + & ~MACEPCI_ERROR_OVERRUN); + } + if (flags & MACEPCI_ERROR_SIG_TABORT) { + printk("MACEPCI: Signaled target abort (clearing)\n"); + mace_write_32(MACEPCI_ERROR_FLAGS, flags + & ~MACEPCI_ERROR_SIG_TABORT); + } + if (flags & MACEPCI_ERROR_INTERRUPT_TEST) { + printk("MACEPCI: Interrupt test triggered (clearing)\n"); + mace_write_32(MACEPCI_ERROR_FLAGS, flags + & ~MACEPCI_ERROR_INTERRUPT_TEST); + } +} + +unsigned int pcibios_assign_all_busses(void) +{ + return 0; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-lasat.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,245 @@ +#include +#include +#include +#include + +#include +#include +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#undef DEBUG_PCI +#ifdef DEBUG_PCI +#define Dprintk(fmt...) printk(fmt) +#else +#define Dprintk(fmt...) +#endif + +static int (*lasat_pcibios_config_access) (unsigned char access_type, + struct pci_bus * bus, + unsigned int devfn, int where, + u32 * val); + +/* + * Because of an error/peculiarity in the Galileo chip, we need to swap the + * bytes when running bigendian. + */ +#define GT_WRITE(ofs, data) \ + *(volatile u32 *)(LASAT_GT_BASE+ofs) = cpu_to_le32(data) +#define GT_READ(ofs, data) \ + data = le32_to_cpu(*(volatile u32 *)(LASAT_GT_BASE+ofs)) + + +static int lasat_pcibios_config_access_100(unsigned char access_type, + struct pci_bus *bus, + unsigned int devfn, int where, + u32 * val) +{ + unsigned char busnum = bus->number; + u32 intr; + + if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0))) + return -1; /* Because of a bug in the Galileo (for slot 31). */ + + /* Clear cause register bits */ + GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | + GT_INTRCAUSE_TARABORT0_BIT)); + + /* Setup address */ + GT_WRITE(GT_PCI0_CFGADDR_OFS, + (busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) | + (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | + ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | + GT_PCI0_CFGADDR_CONFIGEN_BIT); + + if (access_type == PCI_ACCESS_WRITE) { + GT_WRITE(GT_PCI0_CFGDATA_OFS, *val); + } else { + GT_READ(GT_PCI0_CFGDATA_OFS, *val); + } + + /* Check for master or target abort */ + GT_READ(GT_INTRCAUSE_OFS, intr); + + if (intr & + (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) { + /* Error occurred */ + + /* Clear bits */ + GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | + GT_INTRCAUSE_TARABORT0_BIT)); + + return -1; + } + + return 0; +} + +#define LO(reg) (reg / 4) +#define HI(reg) (reg / 4 + 1) + +volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE; + +static int lasat_pcibios_config_access_200(unsigned char access_type, + struct pci_bus *bus, + unsigned int devfn, int where, + u32 * val) +{ + unsigned char busnum = bus->number; + u32 adr, mask, err; + + if ((busnum == 0) && (PCI_SLOT(devfn) > 8)) + /* The addressing scheme chosen leaves room for just + * 8 devices on the first busnum (besides the PCI + * controller itself) */ + return -1; + + if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) { + /* Access controller registers directly */ + if (access_type == PCI_ACCESS_WRITE) { + vrc_pciregs[(0x200 + where) >> 2] = *val; + } else { + *val = vrc_pciregs[(0x200 + where) >> 2]; + } + return 0; + } + + /* Temporarily map PCI Window 1 to config space */ + mask = vrc_pciregs[LO(NILE4_PCIINIT1)]; + vrc_pciregs[LO(NILE4_PCIINIT1)] = + 0x0000001a | (busnum ? 0x200 : 0); + + /* Clear PCI Error register. This also clears the Error Type + * bits in the Control register */ + vrc_pciregs[LO(NILE4_PCIERR)] = 0; + vrc_pciregs[HI(NILE4_PCIERR)] = 0; + + /* Setup address */ + if (busnum == 0) + adr = + KSEG1ADDR(PCI_WINDOW1) + + ((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8) + | (where & ~3)); + else + adr = + KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) + | (where & ~3); + +#ifdef DEBUG_PCI + printk("PCI config %s: adr %x", + access_type == PCI_ACCESS_WRITE ? "write" : "read", adr); +#endif + + if (access_type == PCI_ACCESS_WRITE) { + *(u32 *) adr = *val; + } else { + *val = *(u32 *) adr; + } + +#ifdef DEBUG_PCI + printk(" value = %x\n", *val); +#endif + + /* Check for master or target abort */ + err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7; + + /* Restore PCI Window 1 */ + vrc_pciregs[LO(NILE4_PCIINIT1)] = mask; + + if (err) { + /* Error occured */ +#ifdef DEBUG_PCI + printk("\terror %x at adr %x\n", err, + vrc_pciregs[LO(NILE4_PCIERR)]); +#endif + return -1; + } + + return 0; +} + +static int lasat_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (lasat_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, + &data)) + return -1; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + +static int lasat_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (lasat_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, + &data)) + return -1; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else + data = val; + + if (lasat_pcibios_config_access + (PCI_ACCESS_WRITE, bus, devfn, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops lasat_pci_ops = { + .read = lasat_pcibios_read, + .write = lasat_pcibios_write, +}; + +static int __init pcibios_init(void) +{ + switch (mips_machtype) { + case MACH_LASAT_100: + lasat_pcibios_config_access = + &lasat_pcibios_config_access_100; + break; + case MACH_LASAT_200: + lasat_pcibios_config_access = + &lasat_pcibios_config_access_200; + break; + default: + panic("pcibios_init: mips_machtype incorrect"); + } + + Dprintk("pcibios_init()\n"); + pci_scan_bus(0, &lasat_pci_ops, NULL); + return 0; +} + +unsigned __init int pcibios_assign_all_busses(void) +{ + return 1; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-mips.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,479 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * MIPS boards specific PCI support. + * + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#ifdef CONFIG_MIPS_MALTA +#include +#endif +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +/* + * PCI configuration cycle AD bus definition + */ +/* Type 0 */ +#define PCI_CFG_TYPE0_REG_SHF 0 +#define PCI_CFG_TYPE0_FUNC_SHF 8 + +/* Type 1 */ +#define PCI_CFG_TYPE1_REG_SHF 0 +#define PCI_CFG_TYPE1_FUNC_SHF 8 +#define PCI_CFG_TYPE1_DEV_SHF 11 +#define PCI_CFG_TYPE1_BUS_SHF 16 + +static int mips_pcibios_config_access(unsigned char access_type, + struct pci_bus *bus, + unsigned int devfn, int where, + u32 * data) +{ + unsigned char busnum = bus->number; + unsigned char type; + u32 intr, dummy; + u64 pci_addr; + + switch (mips_revision_corid) { + case MIPS_REVISION_CORID_QED_RM5261: + case MIPS_REVISION_CORID_CORE_LV: + case MIPS_REVISION_CORID_CORE_FPGA: + /* Galileo GT64120 system controller. */ + + if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0))) + return -1; /* Because of a bug in the galileo (for slot 31). */ + + /* Clear cause register bits */ + GT_READ(GT_INTRCAUSE_OFS, intr); + GT_WRITE(GT_INTRCAUSE_OFS, intr & + ~(GT_INTRCAUSE_MASABORT0_BIT | + GT_INTRCAUSE_TARABORT0_BIT)); + + /* Setup address */ + GT_WRITE(GT_PCI0_CFGADDR_OFS, + (busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) | + (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | + ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | + GT_PCI0_CFGADDR_CONFIGEN_BIT); + + if (access_type == PCI_ACCESS_WRITE) { + if (busnum == 0 && devfn == 0) { + /* + * The Galileo system controller is acting + * differently than other devices. + */ + GT_WRITE(GT_PCI0_CFGDATA_OFS, *data); + } else { + GT_PCI_WRITE(GT_PCI0_CFGDATA_OFS, *data); + } + } else { + if (busnum == 0 && devfn == 0) { + /* + * The Galileo system controller is acting + * differently than other devices. + */ + GT_READ(GT_PCI0_CFGDATA_OFS, *data); + } else { + GT_PCI_READ(GT_PCI0_CFGDATA_OFS, *data); + } + } + + /* Check for master or target abort */ + GT_READ(GT_INTRCAUSE_OFS, intr); + + if (intr & (GT_INTRCAUSE_MASABORT0_BIT | + GT_INTRCAUSE_TARABORT0_BIT)) { + /* Error occurred */ + + /* Clear bits */ + GT_READ(GT_INTRCAUSE_OFS, intr); + GT_WRITE(GT_INTRCAUSE_OFS, intr & + ~(GT_INTRCAUSE_MASABORT0_BIT | + GT_INTRCAUSE_TARABORT0_BIT)); + + return -1; + } + + break; + + case MIPS_REVISION_CORID_BONITO64: + case MIPS_REVISION_CORID_CORE_20K: + /* Algorithmics Bonito64 system controller. */ + + if ((busnum == 0) && (PCI_SLOT(devfn) == 0)) { + return -1; + } + + /* Clear cause register bits */ + BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR | + BONITO_PCICMD_MTABORT_CLR); + + /* + * Setup pattern to be used as PCI "address" for + * Type 0 cycle + */ + if (busnum == 0) { + /* IDSEL */ + pci_addr = (u64) 1 << (PCI_SLOT(devfn) + 10); + } else { + /* Bus number */ + pci_addr = busnum << PCI_CFG_TYPE1_BUS_SHF; + + /* Device number */ + pci_addr |= + PCI_SLOT(devfn) << PCI_CFG_TYPE1_DEV_SHF; + } + + /* Function (same for Type 0/1) */ + pci_addr |= PCI_FUNC(devfn) << PCI_CFG_TYPE0_FUNC_SHF; + + /* Register number (same for Type 0/1) */ + pci_addr |= (where & ~0x3) << PCI_CFG_TYPE0_REG_SHF; + + if (busnum == 0) { + /* Type 0 */ + BONITO_PCIMAP_CFG = pci_addr >> 16; + } else { + /* Type 1 */ + BONITO_PCIMAP_CFG = (pci_addr >> 16) | 0x10000; + } + + /* Flush Bonito register block */ + dummy = BONITO_PCIMAP_CFG; + iob(); /* sync */ + + /* Perform access */ + if (access_type == PCI_ACCESS_WRITE) { + *(volatile u32 *) (KSEG1ADDR(BONITO_PCICFG_BASE + + (pci_addr & 0xffff))) + = *(u32 *) data; + + /* Wait till done */ + while (BONITO_PCIMSTAT & 0xF); + } else { + *(u32 *) data = + *(volatile u32 + *) (KSEG1ADDR(BONITO_PCICFG_BASE + + (pci_addr & 0xffff))); + } + + /* Detect Master/Target abort */ + if (BONITO_PCICMD & (BONITO_PCICMD_MABORT_CLR | + BONITO_PCICMD_MTABORT_CLR)) { + /* Error occurred */ + + /* Clear bits */ + BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR | + BONITO_PCICMD_MTABORT_CLR); + + return -1; + } + break; + + case MIPS_REVISION_CORID_CORE_MSC: + /* MIPS system controller. */ + + if ((busnum == 0) && (PCI_SLOT(devfn) == 0)) { + return -1; + } + + /* Clear status register bits. */ + MSC_WRITE(MSC01_PCI_INTSTAT, + (MSC01_PCI_INTCFG_MA_BIT | + MSC01_PCI_INTCFG_TA_BIT)); + + /* Setup address */ + if (busnum == 0) + type = 0; /* Type 0 */ + else + type = 1; /* Type 1 */ + + MSC_WRITE(MSC01_PCI_CFGADDR, + ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) | + (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) + | (PCI_FUNC(devfn) << + MSC01_PCI_CFGADDR_FNUM_SHF) | ((where / + 4) << + MSC01_PCI_CFGADDR_RNUM_SHF) + | (type))); + + /* Perform access */ + if (access_type == PCI_ACCESS_WRITE) { + MSC_WRITE(MSC01_PCI_CFGDATA, *data); + } else { + MSC_READ(MSC01_PCI_CFGDATA, *data); + } + + /* Detect Master/Target abort */ + MSC_READ(MSC01_PCI_INTSTAT, intr); + if (intr & (MSC01_PCI_INTCFG_MA_BIT | + MSC01_PCI_INTCFG_TA_BIT)) { + /* Error occurred */ + + /* Clear bits */ + MSC_READ(MSC01_PCI_INTSTAT, intr); + MSC_WRITE(MSC01_PCI_INTSTAT, + (MSC01_PCI_INTCFG_MA_BIT | + MSC01_PCI_INTCFG_TA_BIT)); + + return -1; + } + break; + default: + printk + ("Unknown Core card, don't know the system controller.\n"); + return -1; + } + + return 0; +} + + +/* + * We can't address 8 and 16 bit words directly. Instead we have to + * read/write a 32bit word and mask/modify the data we actually want. + */ +static int mips_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (mips_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, + &data)) + return -1; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + +static int mips_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (mips_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, + &data)) + return -1; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (mips_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, + &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops mips_pci_ops = { + .read = mips_pcibios_read, + .write = mips_pcibios_write +}; + +int mips_pcibios_iack(void) +{ + int irq; + u32 dummy; + + /* + * Determine highest priority pending interrupt by performing + * a PCI Interrupt Acknowledge cycle. + */ + switch (mips_revision_corid) { + case MIPS_REVISION_CORID_QED_RM5261: + case MIPS_REVISION_CORID_CORE_LV: + case MIPS_REVISION_CORID_CORE_FPGA: + case MIPS_REVISION_CORID_CORE_MSC: + if (mips_revision_corid == MIPS_REVISION_CORID_CORE_MSC) + MSC_READ(MSC01_PCI_IACK, irq); + else + GT_READ(GT_PCI0_IACK_OFS, irq); + irq &= 0xff; + break; + case MIPS_REVISION_CORID_BONITO64: + case MIPS_REVISION_CORID_CORE_20K: + /* The following will generate a PCI IACK cycle on the + * Bonito controller. It's a little bit kludgy, but it + * was the easiest way to implement it in hardware at + * the given time. + */ + BONITO_PCIMAP_CFG = 0x20000; + + /* Flush Bonito register block */ + dummy = BONITO_PCIMAP_CFG; + iob(); /* sync */ + + irq = *(volatile u32 *) (KSEG1ADDR(BONITO_PCICFG_BASE)); + iob(); /* sync */ + irq &= 0xff; + BONITO_PCIMAP_CFG = 0; + break; + default: + printk + ("Unknown Core card, don't know the system controller.\n"); + return -1; + } + return irq; +} + +static int __init pcibios_init(void) +{ +#ifdef CONFIG_MIPS_MALTA + struct pci_dev *pdev = NULL; + unsigned char reg_val; +#endif + + printk("PCI: Probing PCI hardware on host bus 0.\n"); + pci_scan_bus(0, &mips_pci_ops, NULL); + + switch (mips_revision_corid) { + case MIPS_REVISION_CORID_QED_RM5261: + case MIPS_REVISION_CORID_CORE_LV: + case MIPS_REVISION_CORID_CORE_FPGA: + /* + * Due to a bug in the Galileo system controller, we need + * to setup the PCI BAR for the Galileo internal registers. + * This should be done in the bios/bootprom and will be + * fixed in a later revision of YAMON (the MIPS boards + * boot prom). + */ + GT_WRITE(GT_PCI0_CFGADDR_OFS, (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ + (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ + (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0 */ + ((0x20 / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4 */ + GT_PCI0_CFGADDR_CONFIGEN_BIT); + + /* Perform the write */ + GT_WRITE(GT_PCI0_CFGDATA_OFS, PHYSADDR(MIPS_GT_BASE)); + break; + } + +#ifdef CONFIG_MIPS_MALTA + while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) { + if ((pdev->vendor == PCI_VENDOR_ID_INTEL) + && (pdev->device == PCI_DEVICE_ID_INTEL_82371AB) + && (PCI_SLOT(pdev->devfn) == 0x0a)) { + /* + * IDE Decode enable. + */ + pci_read_config_byte(pdev, 0x41, ®_val); + pci_write_config_byte(pdev, 0x41, reg_val | 0x80); + pci_read_config_byte(pdev, 0x43, ®_val); + pci_write_config_byte(pdev, 0x43, reg_val | 0x80); + } + + if ((pdev->vendor == PCI_VENDOR_ID_INTEL) + && (pdev->device == PCI_DEVICE_ID_INTEL_82371AB_0) + && (PCI_SLOT(pdev->devfn) == 0x0a)) { + /* + * Set top of main memory accessible by ISA or DMA + * devices to 16 Mb. + */ + pci_read_config_byte(pdev, 0x69, ®_val); + pci_write_config_byte(pdev, 0x69, reg_val | 0xf0); + } + } + + /* + * Activate Floppy Controller in the SMSC FDC37M817 Super I/O + * Controller. + * This should be done in the bios/bootprom and will be fixed in + * a later revision of YAMON (the MIPS boards boot prom). + */ + /* Entering config state. */ + SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG); + + /* Activate floppy controller. */ + SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG); + SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG); + SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG); + SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG); + + /* Exit config state. */ + SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG); +#endif + + return 0; +} + +subsys_initcall(pcibios_init); + +int pcibios_enable_device(struct pci_dev *dev, int mask) +{ + /* Not needed, since we enable all devices at startup. */ + return 0; +} + +void pcibios_align_resource(void *data, struct resource *res, + unsigned long size, unsigned long align) +{ +} + +char *__init pcibios_setup(char *str) +{ + /* Nothing to do for now. */ + + return str; +} + +struct pci_fixup pcibios_fixups[] = { + {0} +}; + +/* + * Called after each bus is probed, but before its children + * are examined. + */ +void __devinit pcibios_fixup_bus(struct pci_bus *b) +{ + pci_read_bridge_bases(b); +} + +unsigned int pcibios_assign_all_busses(void) +{ + return 1; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-ocelot-c.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,458 @@ +/* + * Copyright 2002 Momentum Computer + * Author: Matthew Dharm + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * These functions and structures provide the BIOS scan and mapping of the PCI + * devices. + */ + +#define MAX_PCI_DEVS 10 + +void mv64340_board_pcibios_fixup_bus(struct pci_bus *c); + +/* Functions to implement "pci ops" */ +static int marvell_pcibios_read_config_word(struct pci_dev *dev, + int offset, u16 * val); +static int marvell_pcibios_read_config_byte(struct pci_dev *dev, + int offset, u8 * val); +static int marvell_pcibios_read_config_dword(struct pci_dev *dev, + int offset, u32 * val); +static int marvell_pcibios_write_config_byte(struct pci_dev *dev, + int offset, u8 val); +static int marvell_pcibios_write_config_word(struct pci_dev *dev, + int offset, u16 val); +static int marvell_pcibios_write_config_dword(struct pci_dev *dev, + int offset, u32 val); +static void marvell_pcibios_set_master(struct pci_dev *dev); + +/* + * General-purpose PCI functions. + */ + + +/* + * pci_range_ck - + * + * Check if the pci device that are trying to access does really exists + * on the evaluation board. + * + * Inputs : + * bus - bus number (0 for PCI 0 ; 1 for PCI 1) + * dev - number of device on the specific pci bus + * + * Outpus : + * 0 - if OK , 1 - if failure + */ +static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev) +{ + /* Accessing device 31 crashes the MV-64340. */ + if (dev < 5) + return 0; + return -1; +} + +/* + * marvell_pcibios_(read/write)_config_(dword/word/byte) - + * + * reads/write a dword/word/byte register from the configuration space + * of a device. + * + * Note that bus 0 and bus 1 are local, and we assume all other busses are + * bridged from bus 1. This is a safe assumption, since any other + * configuration will require major modifications to the CP7000G + * + * Inputs : + * bus - bus number + * dev - device number + * offset - register offset in the configuration space + * val - value to be written / read + * + * Outputs : + * PCIBIOS_SUCCESSFUL when operation was succesfull + * PCIBIOS_DEVICE_NOT_FOUND when the bus or dev is errorneous + * PCIBIOS_BAD_REGISTER_NUMBER when accessing non aligned + */ + +static int marvell_pcibios_read_config_dword(struct pci_dev *device, + int offset, u32 * val) +{ + int dev, bus, func; + uint32_t address_reg, data_reg; + uint32_t address; + + bus = device->bus->number; + dev = PCI_SLOT(device->devfn); + func = PCI_FUNC(device->devfn); + + /* verify the range */ + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* select the MV-64340 registers to communicate with the PCI bus */ + if (bus == 0) { + address_reg = MV64340_PCI_0_CONFIG_ADDR; + data_reg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG; + } else { + address_reg = MV64340_PCI_1_CONFIG_ADDR; + data_reg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG; + } + + address = (bus << 16) | (dev << 11) | (func << 8) | + (offset & 0xfc) | 0x80000000; + + /* start the configuration cycle */ + MV_WRITE(address_reg, address); + + /* read the data */ + MV_READ(data_reg, val); + + return PCIBIOS_SUCCESSFUL; +} + + +static int marvell_pcibios_read_config_word(struct pci_dev *device, + int offset, u16 * val) +{ + int dev, bus, func; + uint32_t address_reg, data_reg; + uint32_t address; + + bus = device->bus->number; + dev = PCI_SLOT(device->devfn); + func = PCI_FUNC(device->devfn); + + /* verify the range */ + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* select the MV-64340 registers to communicate with the PCI bus */ + if (bus == 0) { + address_reg = MV64340_PCI_0_CONFIG_ADDR; + data_reg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG; + } else { + address_reg = MV64340_PCI_1_CONFIG_ADDR; + data_reg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG; + } + + address = (bus << 16) | (dev << 11) | (func << 8) | + (offset & 0xfc) | 0x80000000; + + /* start the configuration cycle */ + MV_WRITE(address_reg, address); + + /* read the data */ + MV_READ_16(data_reg + (offset & 0x3), val); + + return PCIBIOS_SUCCESSFUL; +} + +static int marvell_pcibios_read_config_byte(struct pci_dev *device, + int offset, u8 * val) +{ + int dev, bus, func; + uint32_t address_reg, data_reg; + uint32_t address; + + bus = device->bus->number; + dev = PCI_SLOT(device->devfn); + func = PCI_FUNC(device->devfn); + + /* verify the range */ + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* select the MV-64340 registers to communicate with the PCI bus */ + if (bus == 0) { + address_reg = MV64340_PCI_0_CONFIG_ADDR; + data_reg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG; + } else { + address_reg = MV64340_PCI_1_CONFIG_ADDR; + data_reg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG; + } + + address = (bus << 16) | (dev << 11) | (func << 8) | + (offset & 0xfc) | 0x80000000; + + /* start the configuration cycle */ + MV_WRITE(address_reg, address); + + /* write the data */ + MV_READ_8(data_reg + (offset & 0x3), val); + + return PCIBIOS_SUCCESSFUL; +} + +static int marvell_pcibios_write_config_dword(struct pci_dev *device, + int offset, u32 val) +{ + int dev, bus, func; + uint32_t address_reg, data_reg; + uint32_t address; + + bus = device->bus->number; + dev = PCI_SLOT(device->devfn); + func = PCI_FUNC(device->devfn); + + /* verify the range */ + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* select the MV-64340 registers to communicate with the PCI bus */ + if (bus == 0) { + address_reg = MV64340_PCI_0_CONFIG_ADDR; + data_reg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG; + } else { + address_reg = MV64340_PCI_1_CONFIG_ADDR; + data_reg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG; + } + + address = (bus << 16) | (dev << 11) | (func << 8) | + (offset & 0xfc) | 0x80000000; + + /* start the configuration cycle */ + MV_WRITE(address_reg, address); + + /* write the data */ + MV_WRITE(data_reg, val); + + return PCIBIOS_SUCCESSFUL; +} + + +static int marvell_pcibios_write_config_word(struct pci_dev *device, + int offset, u16 val) +{ + int dev, bus, func; + uint32_t address_reg, data_reg; + uint32_t address; + + bus = device->bus->number; + dev = PCI_SLOT(device->devfn); + func = PCI_FUNC(device->devfn); + + /* verify the range */ + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* select the MV-64340 registers to communicate with the PCI bus */ + if (bus == 0) { + address_reg = MV64340_PCI_0_CONFIG_ADDR; + data_reg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG; + } else { + address_reg = MV64340_PCI_1_CONFIG_ADDR; + data_reg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG; + } + + address = (bus << 16) | (dev << 11) | (func << 8) | + (offset & 0xfc) | 0x80000000; + + /* start the configuration cycle */ + MV_WRITE(address_reg, address); + + /* write the data */ + MV_WRITE_16(data_reg + (offset & 0x3), val); + + return PCIBIOS_SUCCESSFUL; +} + +static int marvell_pcibios_write_config_byte(struct pci_dev *device, + int offset, u8 val) +{ + int dev, bus, func; + uint32_t address_reg, data_reg; + uint32_t address; + + bus = device->bus->number; + dev = PCI_SLOT(device->devfn); + func = PCI_FUNC(device->devfn); + + /* verify the range */ + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* select the MV-64340 registers to communicate with the PCI bus */ + if (bus == 0) { + address_reg = MV64340_PCI_0_CONFIG_ADDR; + data_reg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG; + } else { + address_reg = MV64340_PCI_1_CONFIG_ADDR; + data_reg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG; + } + + address = (bus << 16) | (dev << 11) | (func << 8) | + (offset & 0xfc) | 0x80000000; + + /* start the configuration cycle */ + MV_WRITE(address_reg, address); + + /* write the data */ + MV_WRITE_8(data_reg + (offset & 0x3), val); + + return PCIBIOS_SUCCESSFUL; +} + +static void marvell_pcibios_set_master(struct pci_dev *dev) +{ + u16 cmd; + + marvell_pcibios_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + marvell_pcibios_write_config_word(dev, PCI_COMMAND, cmd); +} + +/* Externally-expected functions. Do not change function names */ + +int pcibios_enable_resources(struct pci_dev *dev) +{ + u16 cmd, old_cmd; + u8 tmp1; + int idx; + struct resource *r; + + marvell_pcibios_read_config_word(dev, PCI_COMMAND, &cmd); + old_cmd = cmd; + for (idx = 0; idx < 6; idx++) { + r = &dev->resource[idx]; + if (!r->start && r->end) { + printk(KERN_ERR + "PCI: Device %s not available because of " + "resource collisions\n", dev->slot_name); + return -EINVAL; + } + if (r->flags & IORESOURCE_IO) + cmd |= PCI_COMMAND_IO; + if (r->flags & IORESOURCE_MEM) + cmd |= PCI_COMMAND_MEMORY; + } + if (cmd != old_cmd) { + marvell_pcibios_write_config_word(dev, PCI_COMMAND, cmd); + } + + /* + * Let's fix up the latency timer and cache line size here. Cache + * line size = 32 bytes / sizeof dword (4) = 8. + * Latency timer must be > 8. 32 is random but appears to work. + */ + marvell_pcibios_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp1); + if (tmp1 != 8) { + printk(KERN_WARNING + "PCI setting cache line size to 8 from " "%d\n", + tmp1); + marvell_pcibios_write_config_byte(dev, PCI_CACHE_LINE_SIZE, + 8); + } + marvell_pcibios_read_config_byte(dev, PCI_LATENCY_TIMER, &tmp1); + if (tmp1 < 32) { + printk(KERN_WARNING + "PCI setting latency timer to 32 from %d\n", tmp1); + marvell_pcibios_write_config_byte(dev, PCI_LATENCY_TIMER, + 32); + } + + return 0; +} + +int pcibios_enable_device(struct pci_dev *dev, int mask) +{ + return pcibios_enable_resources(dev); +} + +void pcibios_align_resource(void *data, struct resource *res, + unsigned long size) +{ + struct pci_dev *dev = data; + + if (res->flags & IORESOURCE_IO) { + unsigned long start = res->start; + + /* We need to avoid collisions with `mirrored' VGA ports + and other strange ISA hardware, so we always want the + addresses kilobyte aligned. */ + if (size > 0x100) { + printk(KERN_ERR "PCI: I/O Region %s/%d too large" + " (%ld bytes)\n", dev->slot_name, + dev->resource - res, size); + } + + start = (start + 1024 - 1) & ~(1024 - 1); + res->start = start; + } +} + +struct pci_ops marvell_pci_ops = { + marvell_pcibios_read_config_byte, + marvell_pcibios_read_config_word, + marvell_pcibios_read_config_dword, + marvell_pcibios_write_config_byte, + marvell_pcibios_write_config_word, + marvell_pcibios_write_config_dword +}; + +struct pci_fixup pcibios_fixups[] = { + {0} +}; + +void __init pcibios_fixup_bus(struct pci_bus *c) +{ + mv64340_board_pcibios_fixup_bus(c); +} + +void __init pcibios_init(void) +{ + /* Reset PCI I/O and PCI MEM values */ + ioport_resource.start = 0xe0000000; + ioport_resource.end = 0xe0000000 + 0x20000000 - 1; + iomem_resource.start = 0xc0000000; + iomem_resource.end = 0xc0000000 + 0x20000000 - 1; + + pci_scan_bus(0, &marvell_pci_ops, NULL); + pci_scan_bus(1, &marvell_pci_ops, NULL); +} + +/* + * for parsing "pci=" kernel boot arguments. + */ +char *pcibios_setup(char *str) +{ + printk(KERN_INFO "rr: pcibios_setup\n"); + /* Nothing to do for now. */ + + return str; +} + +unsigned __init int pcibios_assign_all_busses(void) +{ + return 1; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-ocelot-g.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,572 @@ +/* + * Copyright 2002 Momentum Computer + * Author: Matthew Dharm + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include "gt64240.h" + +#include + +#define SELF 0 +#define MASTER_ABORT_BIT 0x100 + +/* + * These functions and structures provide the BIOS scan and mapping of the PCI + * devices. + */ + +#define MAX_PCI_DEVS 10 + +void gt64240_board_pcibios_fixup_bus(struct pci_bus *c); + +/* Functions to implement "pci ops" */ +static int galileo_pcibios_read_config_word(int bus, int devfn, + int offset, u16 * val); +static int galileo_pcibios_read_config_byte(int bus, int devfn, + int offset, u8 * val); +static int galileo_pcibios_read_config_dword(int bus, int devfn, + int offset, u32 * val); +static int galileo_pcibios_write_config_byte(int bus, int devfn, + int offset, u8 val); +static int galileo_pcibios_write_config_word(int bus, int devfn, + int offset, u16 val); +static int galileo_pcibios_write_config_dword(int bus, int devfn, + int offset, u32 val); +#if 0 +static void galileo_pcibios_set_master(struct pci_dev *dev); +#endif + +static int pci_read(struct pci_bus *bus, unsigned int devfs, int where, + int size, u32 * val); +static int pci_write(struct pci_bus *bus, unsigned int devfs, int where, + int size, u32 val); + +/* + * General-purpose PCI functions. + */ + + +/* + * pci_range_ck - + * + * Check if the pci device that are trying to access does really exists + * on the evaluation board. + * + * Inputs : + * bus - bus number (0 for PCI 0 ; 1 for PCI 1) + * dev - number of device on the specific pci bus + * + * Outpus : + * 0 - if OK , 1 - if failure + */ +static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev) +{ + /* Accessing device 31 crashes the GT-64240. */ + if (dev < 5) + return 0; + return -1; +} + +/* + * galileo_pcibios_(read/write)_config_(dword/word/byte) - + * + * reads/write a dword/word/byte register from the configuration space + * of a device. + * + * Note that bus 0 and bus 1 are local, and we assume all other busses are + * bridged from bus 1. This is a safe assumption, since any other + * configuration will require major modifications to the CP7000G + * + * Inputs : + * bus - bus number + * dev - device number + * offset - register offset in the configuration space + * val - value to be written / read + * + * Outputs : + * PCIBIOS_SUCCESSFUL when operation was succesfull + * PCIBIOS_DEVICE_NOT_FOUND when the bus or dev is errorneous + * PCIBIOS_BAD_REGISTER_NUMBER when accessing non aligned + */ + +static int galileo_pcibios_read_config_dword(int bus, int devfn, + int offset, u32 * val) +{ + int dev, func; + uint32_t address_reg, data_reg; + uint32_t address; + + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + + /* verify the range */ + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* select the GT-64240 registers to communicate with the PCI bus */ + if (bus == 0) { + address_reg = PCI_0CONFIGURATION_ADDRESS; + data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER; + GT_WRITE(PCI_0ERROR_CAUSE, ~MASTER_ABORT_BIT); + } else { + address_reg = PCI_1CONFIGURATION_ADDRESS; + data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER; + GT_WRITE(PCI_1ERROR_CAUSE, ~MASTER_ABORT_BIT); + if (bus == 1) + bus = 0; + } + + address = (bus << 16) | (dev << 11) | (func << 8) | + (offset & 0xfc) | 0x80000000; + + /* start the configuration cycle */ + GT_WRITE(address_reg, address); + + /* read the data */ + GT_READ(data_reg, val); + + return PCIBIOS_SUCCESSFUL; +} + + +static int galileo_pcibios_read_config_word(int bus, int devfn, + int offset, u16 * val) +{ + int dev, func; + uint32_t address_reg, data_reg; + uint32_t address; + + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + + /* verify the range */ + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* select the GT-64240 registers to communicate with the PCI bus */ + if (bus == 0) { + address_reg = PCI_0CONFIGURATION_ADDRESS; + data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER; + GT_WRITE(PCI_0ERROR_CAUSE, ~MASTER_ABORT_BIT); + } else { + address_reg = PCI_1CONFIGURATION_ADDRESS; + data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER; + GT_WRITE(PCI_1ERROR_CAUSE, ~MASTER_ABORT_BIT); + if (bus == 1) + bus = 0; + } + + address = (bus << 16) | (dev << 11) | (func << 8) | + (offset & 0xfc) | 0x80000000; + + /* start the configuration cycle */ + GT_WRITE(address_reg, address); + + /* read the data */ + GT_READ_16(data_reg + (offset & 0x3), val); + + return PCIBIOS_SUCCESSFUL; +} + +static int galileo_pcibios_read_config_byte(int bus, int devfn, + int offset, u8 * val) +{ + int dev, func; + uint32_t address_reg, data_reg; + uint32_t address; + + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + + /* verify the range */ + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* select the GT-64240 registers to communicate with the PCI bus */ + if (bus == 0) { + address_reg = PCI_0CONFIGURATION_ADDRESS; + data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER; + } else { + address_reg = PCI_1CONFIGURATION_ADDRESS; + data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER; + if (bus == 1) + bus = 0; + } + + address = (bus << 16) | (dev << 11) | (func << 8) | + (offset & 0xfc) | 0x80000000; + + /* start the configuration cycle */ + GT_WRITE(address_reg, address); + + /* write the data */ + GT_READ_8(data_reg + (offset & 0x3), val); + + return PCIBIOS_SUCCESSFUL; +} + +static int galileo_pcibios_write_config_dword(int bus, int devfn, + int offset, u32 val) +{ + int dev, func; + uint32_t address_reg, data_reg; + uint32_t address; + + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + + /* verify the range */ + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* select the GT-64240 registers to communicate with the PCI bus */ + if (bus == 0) { + address_reg = PCI_0CONFIGURATION_ADDRESS; + data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER; + } else { + address_reg = PCI_1CONFIGURATION_ADDRESS; + data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER; + if (bus == 1) + bus = 0; + } + + address = (bus << 16) | (dev << 11) | (func << 8) | + (offset & 0xfc) | 0x80000000; + + /* start the configuration cycle */ + GT_WRITE(address_reg, address); + + /* write the data */ + GT_WRITE(data_reg, val); + + return PCIBIOS_SUCCESSFUL; +} + + +static int galileo_pcibios_write_config_word(int bus, int devfn, + int offset, u16 val) +{ + int dev, func; + uint32_t address_reg, data_reg; + uint32_t address; + + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + + /* verify the range */ + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* select the GT-64240 registers to communicate with the PCI bus */ + if (bus == 0) { + address_reg = PCI_0CONFIGURATION_ADDRESS; + data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER; + } else { + address_reg = PCI_1CONFIGURATION_ADDRESS; + data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER; + if (bus == 1) + bus = 0; + } + + address = (bus << 16) | (dev << 11) | (func << 8) | + (offset & 0xfc) | 0x80000000; + + /* start the configuration cycle */ + GT_WRITE(address_reg, address); + + /* write the data */ + GT_WRITE_16(data_reg + (offset & 0x3), val); + + return PCIBIOS_SUCCESSFUL; +} + +static int galileo_pcibios_write_config_byte(int bus, int devfn, + int offset, u8 val) +{ + int dev, func; + uint32_t address_reg, data_reg; + uint32_t address; + + dev = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + + /* verify the range */ + if (pci_range_ck(bus, dev)) + return PCIBIOS_DEVICE_NOT_FOUND; + + /* select the GT-64240 registers to communicate with the PCI bus */ + if (bus == 0) { + address_reg = PCI_0CONFIGURATION_ADDRESS; + data_reg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER; + } else { + address_reg = PCI_1CONFIGURATION_ADDRESS; + data_reg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER; + if (bus == 1) + bus = 0; + } + + address = (bus << 16) | (dev << 11) | (func << 8) | + (offset & 0xfc) | 0x80000000; + + /* start the configuration cycle */ + GT_WRITE(address_reg, address); + + /* write the data */ + GT_WRITE_8(data_reg + (offset & 0x3), val); + + return PCIBIOS_SUCCESSFUL; +} + +#if 0 +static void galileo_pcibios_set_master(struct pci_dev *dev) +{ + u16 cmd; + + galileo_pcibios_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + galileo_pcibios_write_config_word(dev, PCI_COMMAND, cmd); +} +#endif + +/* Externally-expected functions. Do not change function names */ + +int pcibios_enable_resources(struct pci_dev *dev) +{ + u16 cmd, old_cmd; + u8 tmp1; + int idx; + struct resource *r; + + pci_read(dev->bus, dev->devfn, PCI_COMMAND, 2, (u32 *) & cmd); + old_cmd = cmd; + for (idx = 0; idx < 6; idx++) { + r = &dev->resource[idx]; + if (!r->start && r->end) { + printk(KERN_ERR + "PCI: Device %s not available because of " + "resource collisions\n", dev->slot_name); + return -EINVAL; + } + if (r->flags & IORESOURCE_IO) + cmd |= PCI_COMMAND_IO; + if (r->flags & IORESOURCE_MEM) + cmd |= PCI_COMMAND_MEMORY; + } + if (cmd != old_cmd) { + pci_write(dev->bus, dev->devfn, PCI_COMMAND, 2, cmd); + } + + /* + * Let's fix up the latency timer and cache line size here. Cache + * line size = 32 bytes / sizeof dword (4) = 8. + * Latency timer must be > 8. 32 is random but appears to work. + */ + pci_read(dev->bus, dev->devfn, PCI_CACHE_LINE_SIZE, 1, + (u32 *) & tmp1); + if (tmp1 != 8) { + printk(KERN_WARNING + "PCI setting cache line size to 8 from " "%d\n", + tmp1); + pci_write(dev->bus, dev->devfn, PCI_CACHE_LINE_SIZE, 1, 8); + } + pci_read(dev->bus, dev->devfn, PCI_LATENCY_TIMER, 1, + (u32 *) & tmp1); + if (tmp1 < 32) { + printk(KERN_WARNING + "PCI setting latency timer to 32 from %d\n", tmp1); + pci_write(dev->bus, dev->devfn, PCI_LATENCY_TIMER, 1, 32); + } + + return 0; +} + +int pcibios_enable_device(struct pci_dev *dev, int mask) +{ + return pcibios_enable_resources(dev); +} + +void pcibios_align_resource(void *data, struct resource *res, + unsigned long size, unsigned long align) +{ + struct pci_dev *dev = data; + + if (res->flags & IORESOURCE_IO) { + unsigned long start = res->start; + + /* We need to avoid collisions with `mirrored' VGA ports + and other strange ISA hardware, so we always want the + addresses kilobyte aligned. */ + if (size > 0x100) { + printk(KERN_ERR "PCI: I/O Region %s/%d too large" + " (%ld bytes)\n", dev->slot_name, + dev->resource - res, size); + } + + start = (start + 1024 - 1) & ~(1024 - 1); + res->start = start; + } +} + +struct pci_ops galileo_pci_ops = { + .read = pci_read, + .write = pci_write +}; + +static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 * val) +{ + switch (size) { + case 1: + return galileo_pcibios_read_config_byte(bus->number, + devfn, where, + (u8 *) val); + case 2: + return galileo_pcibios_read_config_word(bus->number, + devfn, where, + (u16 *) val); + case 4: + return galileo_pcibios_read_config_dword(bus->number, + devfn, where, + (u32 *) val); + } + return PCIBIOS_FUNC_NOT_SUPPORTED; +} + +static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 val) +{ + switch (size) { + case 1: + return galileo_pcibios_write_config_byte(bus->number, + devfn, where, + val); + case 2: + return galileo_pcibios_write_config_word(bus->number, + devfn, where, + val); + case 4: + return galileo_pcibios_write_config_dword(bus->number, + devfn, where, + val); + } + return PCIBIOS_FUNC_NOT_SUPPORTED; +} + +struct pci_fixup pcibios_fixups[] = { + {0} +}; + +void __devinit pcibios_fixup_bus(struct pci_bus *c) +{ + gt64240_board_pcibios_fixup_bus(c); +} + + +/******************************************************************** +* pci0P2PConfig - This function set the PCI_0 P2P configurate. +* For more information on the P2P read PCI spec. +* +* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower +* Boundry. +* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper +* Boundry. +* unsigned int busNum - The CPI bus number to which the PCI interface +* is connected. +* unsigned int devNum - The PCI interface's device number. +* +* Returns: true. +*/ +void pci0P2PConfig(unsigned int SecondBusLow, unsigned int SecondBusHigh, + unsigned int busNum, unsigned int devNum) +{ + uint32_t regData; + + regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | + ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); + GT_WRITE(PCI_0P2P_CONFIGURATION, regData); +} + +/******************************************************************** +* pci1P2PConfig - This function set the PCI_1 P2P configurate. +* For more information on the P2P read PCI spec. +* +* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower +* Boundry. +* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper +* Boundry. +* unsigned int busNum - The CPI bus number to which the PCI interface +* is connected. +* unsigned int devNum - The PCI interface's device number. +* +* Returns: true. +*/ +void pci1P2PConfig(unsigned int SecondBusLow, unsigned int SecondBusHigh, + unsigned int busNum, unsigned int devNum) +{ + uint32_t regData; + + regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | + ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); + GT_WRITE(PCI_1P2P_CONFIGURATION, regData); +} + +#define PCI0_STATUS_COMMAND_REG 0x4 +#define PCI1_STATUS_COMMAND_REG 0x84 + +static int __init pcibios_init(void) +{ + /* Reset PCI I/O and PCI MEM values */ + ioport_resource.start = 0xe0000000; + ioport_resource.end = 0xe0000000 + 0x20000000 - 1; + iomem_resource.start = 0xc0000000; + iomem_resource.end = 0xc0000000 + 0x20000000 - 1; + + pci_scan_bus(0, &galileo_pci_ops, NULL); + pci_scan_bus(1, &galileo_pci_ops, NULL); + + return 0; +} + +subsys_initcall(pcibios_init); + +/* + * for parsing "pci=" kernel boot arguments. + */ +char *pcibios_setup(char *str) +{ + printk(KERN_INFO "rr: pcibios_setup\n"); + /* Nothing to do for now. */ + + return str; +} + +unsigned __init int pcibios_assign_all_busses(void) +{ + return 1; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-sb1250.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,281 @@ +/* + * Copyright (C) 2001,2002 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * BCM1250-specific PCI support + * + * This module provides the glue between Linux's PCI subsystem + * and the hardware. We basically provide glue for accessing + * configuration space, and set up the translation for I/O + * space accesses. + * + * To access configuration space, we use ioremap. In the 32-bit + * kernel, this consumes either 4 or 8 page table pages, and 16MB of + * kernel mapped memory. Hopefully neither of these should be a huge + * problem. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* + * Macros for calculating offsets into config space given a device + * structure or dev/fun/reg + */ +#define CFGOFFSET(bus,devfn,where) (((bus)<<16) + ((devfn)<<8) + (where)) +#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) + +static void *cfg_space; + +#define PCI_BUS_ENABLED 1 +#define LDT_BUS_ENABLED 2 +#define PCI_DEVICE_MODE 4 + +static int sb1250_bus_status = 0; + +#define PCI_BRIDGE_DEVICE 0 +#define LDT_BRIDGE_DEVICE 1 + +#ifdef CONFIG_SIBYTE_HAS_LDT +/* + * HT's level-sensitive interrupts require EOI, which is generated + * through a 4MB memory-mapped region + */ +unsigned long ldt_eoi_space; +#endif + +/* + * Read/write 32-bit values in config space. + */ +static inline u32 READCFG32(u32 addr) +{ + return *(u32 *) (cfg_space + (addr & ~3)); +} + +static inline void WRITECFG32(u32 addr, u32 data) +{ + *(u32 *) (cfg_space + (addr & ~3)) = data; +} + +/* + * Some checks before doing config cycles: + * In PCI Device Mode, hide everything on bus 0 except the LDT host + * bridge. Otherwise, access is controlled by bridge MasterEn bits. + */ +static int sb1250_pci_can_access(struct pci_bus *bus, int devfn) +{ + u32 devno; + + if (!(sb1250_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE))) + return 0; + + if (bus->number == 0) { + devno = PCI_SLOT(devfn); + if (devno == LDT_BRIDGE_DEVICE) + return (sb1250_bus_status & LDT_BUS_ENABLED) != 0; + else if (sb1250_bus_status & PCI_DEVICE_MODE) + return 0; + else + return 1; + } else + return 1; +} + +/* + * Read/write access functions for various sizes of values + * in config space. Return all 1's for disallowed accesses + * for a kludgy but adequate simulation of master aborts. + */ + +static int sb1250_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (sb1250_pci_can_access(bus, devfn)) + data = READCFG32(CFGADDR(bus, devfn, where)); + else + data = 0xFFFFFFFF; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + +static int sb1250_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 cfgaddr = CFGADDR(bus, devfn, where); + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (!sb1250_pci_can_access(bus, devfn)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + data = READCFG32(cfgaddr); + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + WRITECFG32(cfgaddr, data); + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops sb1250_pci_ops = { + .read = sb1250_pcibios_read, + .write = sb1250_pcibios_write +}; + + +void __init pcibios_init(void) +{ + uint32_t cmdreg; + uint64_t reg; + + cfg_space = + ioremap(A_PHYS_LDTPCI_CFG_MATCH_BITS, 16 * 1024 * 1024); + + /* + * See if the PCI bus has been configured by the firmware. + */ + reg = *((volatile uint64_t *) KSEG1ADDR(A_SCD_SYSTEM_CFG)); + if (!(reg & M_SYS_PCI_HOST)) { + sb1250_bus_status |= PCI_DEVICE_MODE; + } else { + cmdreg = + READCFG32(CFGOFFSET + (0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), + PCI_COMMAND)); + if (!(cmdreg & PCI_COMMAND_MASTER)) { + printk + ("PCI: Skipping PCI probe. Bus is not initialized.\n"); + iounmap(cfg_space); + return; + } + sb1250_bus_status |= PCI_BUS_ENABLED; + } + + /* + * Establish mappings in KSEG2 (kernel virtual) to PCI I/O + * space. Use "match bytes" policy to make everything look + * little-endian. So, you need to also set + * CONFIG_SWAP_IO_SPACE, but this is the combination that + * works correctly with most of Linux's drivers. + * XXX ehs: Should this happen in PCI Device mode? + */ + + set_io_port_base((unsigned long) + ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 65536)); + isa_slot_offset = (unsigned long) + ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES_32, 1024 * 1024); + +#ifdef CONFIG_SIBYTE_HAS_LDT + /* + * Also check the LDT bridge's enable, just in case we didn't + * initialize that one. + */ + + cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(LDT_BRIDGE_DEVICE, 0), + PCI_COMMAND)); + if (cmdreg & PCI_COMMAND_MASTER) { + sb1250_bus_status |= LDT_BUS_ENABLED; + + /* + * Need bits 23:16 to convey vector number. Note that + * this consumes 4MB of kernel-mapped memory + * (Kseg2/Kseg3) for 32-bit kernel. + */ + ldt_eoi_space = (unsigned long) + ioremap(A_PHYS_LDT_SPECIAL_MATCH_BYTES, + 4 * 1024 * 1024); + } +#endif + + /* Probe for PCI hardware */ + + printk("PCI: Probing PCI hardware on host bus 0.\n"); + pci_scan_bus(0, &sb1250_pci_ops, NULL); + +#ifdef CONFIG_VGA_CONSOLE + take_over_console(&vga_con, 0, MAX_NR_CONSOLES - 1, 1); +#endif +} + +int pcibios_enable_device(struct pci_dev *dev, int mask) +{ + /* Not needed, since we enable all devices at startup. */ + return 0; +} + +void pcibios_align_resource(void *data, struct resource *res, + unsigned long size, unsigned long align) +{ +} + +char *__init pcibios_setup(char *str) +{ + /* Nothing to do for now. */ + + return str; +} + +struct pci_fixup pcibios_fixups[] = { + {0} +}; + +/* + * Called after each bus is probed, but before its children + * are examined. + */ +void __devinit pcibios_fixup_bus(struct pci_bus *b) +{ + pci_read_bridge_bases(b); +} + +unsigned int pcibios_assign_all_busses(void) +{ + return 1; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-sni.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,175 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * SNI specific PCI support for RM200/RM300. + * + * Copyright (C) 1997 - 2000 Ralf Baechle + */ +#include +#include +#include +#include +#include +#include + +#define mkaddr(bus, devfn, where) \ +do { \ + if (bus->number == 0) \ + return -1; \ + *(volatile u32 *)PCIMT_CONFIG_ADDRESS = \ + ((bus->number & 0xff) << 0x10) | \ + ((devfn & 0xff) << 0x08) | \ + (where & 0xfc); \ +} while(0) + +#if 0 +/* To do: Bring this uptodate ... */ +static void pcimt_pcibios_fixup(void) +{ + struct pci_dev *dev = NULL; + + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + /* + * TODO: Take care of RM300 revision D boards for where the + * network slot became an ordinary PCI slot. + */ + if (dev->devfn == PCI_DEVFN(1, 0)) { + /* Evil hack ... */ + set_cp0_config(CONF_CM_CMASK, + CONF_CM_CACHABLE_NO_WA); + dev->irq = PCIMT_IRQ_SCSI; + continue; + } + if (dev->devfn == PCI_DEVFN(2, 0)) { + dev->irq = PCIMT_IRQ_ETHERNET; + continue; + } + + switch (dev->irq) { + case 1...4: + dev->irq += PCIMT_IRQ_INTA - 1; + break; + case 0: + break; + default: + printk("PCI device on bus %d, dev %d, function %d " + "impossible interrupt configured.\n", + dev->bus->number, PCI_SLOT(dev->devfn), + PCI_SLOT(dev->devfn)); + } + } +} +#endif + +/* + * We can't address 8 and 16 bit words directly. Instead we have to + * read/write a 32bit word and mask/modify the data we actually want. + */ +static int pcimt_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 * val) +{ + u32 res; + + switch (size) { + case 1: + mkaddr(bus, devfn, where); + res = *(volatile u32 *) PCIMT_CONFIG_DATA; + res = (le32_to_cpu(res) >> ((where & 3) << 3)) & 0xff; + *val = (u8) res; + break; + case 2: + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + mkaddr(bus, devfn, where); + res = *(volatile u32 *) PCIMT_CONFIG_DATA; + res = (le32_to_cpu(res) >> ((where & 3) << 3)) & 0xffff; + *val = (u16) res; + break; + case 4: + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + mkaddr(bus, devfn, where); + res = *(volatile u32 *) PCIMT_CONFIG_DATA; + res = le32_to_cpu(res); + *val = res; + break; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 val) +{ + switch (size) { + case 1: + mkaddr(bus, devfn, where); + *(volatile u8 *) (PCIMT_CONFIG_DATA + (where & 3)) = + (u8) le32_to_cpu(val); + break; + case 2: + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + mkaddr(bus, devfn, where); + *(volatile u16 *) (PCIMT_CONFIG_DATA + (where & 3)) = + (u16) le32_to_cpu(val); + break; + case 4: + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + mkaddr(bus, devfn, where); + *(volatile u32 *) PCIMT_CONFIG_DATA = le32_to_cpu(val); + break; + } + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops sni_pci_ops = { + .read = pcimt_read, + .write = pcimt_write, +}; + +void __devinit pcibios_fixup_bus(struct pci_bus *b) +{ +} + +static int __init pcibios_init(void) +{ + struct pci_ops *ops = &sni_pci_ops; + + pci_scan_bus(0, ops, NULL); + + return 0; +} + +subsys_initcall(pcibios_init); + +int __init pcibios_enable_device(struct pci_dev *dev, int mask) +{ + /* Not needed, since we enable all devices at startup. */ + return 0; +} + +void pcibios_align_resource(void *data, struct resource *res, + unsigned long size, unsigned long align) +{ +} + +unsigned __init int pcibios_assign_all_busses(void) +{ + return 0; +} + +char *__init pcibios_setup(char *str) +{ + /* Nothing to do for now. */ + + return str; +} + +struct pci_fixup pcibios_fixups[] = { + {0} +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-vr41xx.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,233 @@ +/* + * FILE NAME + * arch/mips/vr41xx/common/pciu.c + * + * BRIEF MODULE DESCRIPTION + * PCI Control Unit routines for the NEC VR4100 series. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2001,2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Changes: + * Paul Mundt + * - Fix deadlock-causing PCIU access race for VR4131. + * + * MontaVista Software Inc. or + * - New creation, NEC VR4122 and VR4131 are supported. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "pciu.h" + +extern unsigned long vr41xx_vtclock; + +static inline int vr41xx_pci_config_access(unsigned char bus, + unsigned int devfn, int where) +{ + if (bus == 0) { + /* + * Type 0 configuration + */ + if (PCI_SLOT(devfn) < 11 || where > 255) + return -1; + + writel((1UL << PCI_SLOT(devfn)) | + (PCI_FUNC(devfn) << 8) | + (where & 0xfc), PCICONFAREG); + } else { + /* + * Type 1 configuration + */ + if (where > 255) + return -1; + + writel((bus << 16) | + (devfn << 8) | (where & 0xfc) | 1UL, PCICONFAREG); + } + + return 0; +} + +static int vr41xx_pci_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 * val) +{ + u32 data; + + *val = 0xffffffffUL; + if (vr41xx_pci_config_access(bus->number, devfn, where) < 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + data = readl(PCICONFDREG); + + switch (size) { + case 1: + *val = (data >> ((where & 3) << 3)) & 0xffUL; + break; + case 2: + *val = (data >> ((where & 2) << 3)) & 0xffffUL; + break; + case 4: + *val = data; + break; + default: + return PCIBIOS_FUNC_NOT_SUPPORTED; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int vr41xx_pci_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data; + int shift; + + if (vr41xx_pci_config_access(bus->number, devfn, where) < 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + data = readl(PCICONFDREG); + + switch (size) { + case 1: + shift = (where & 3) << 3; + data &= ~(0xff << shift); + data |= ((val & 0xff) << shift); + break; + case 2: + shift = (where & 2) << 3; + data &= ~(0xffff << shift); + data |= ((val & 0xffff) << shift); + break; + case 4: + data = val; + break; + default: + return PCIBIOS_FUNC_NOT_SUPPORTED; + } + + writel(data, PCICONFDREG); + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops vr41xx_pci_ops = { + .read = vr41xx_pci_config_read, + .write = vr41xx_pci_config_write, +}; + +void __init vr41xx_pciu_init(struct vr41xx_pci_address_map *map) +{ + struct vr41xx_pci_address_space *s; + u32 config; + int n; + + if (!map) + return; + + /* Disable PCI interrupt */ + writew(0, MPCIINTREG); + + /* Supply VTClock to PCIU */ + vr41xx_clock_supply(PCIU_CLOCK); + + /* + * Sleep for 1us after setting MSKPPCIU bit in CMUCLKMSK + * before doing any PCIU access to avoid deadlock on VR4131. + */ + udelay(1); + + /* Select PCI clock */ + if (vr41xx_vtclock < MAX_PCI_CLOCK) + writel(EQUAL_VTCLOCK, PCICLKSELREG); + else if ((vr41xx_vtclock / 2) < MAX_PCI_CLOCK) + writel(HALF_VTCLOCK, PCICLKSELREG); + else if ((vr41xx_vtclock / 4) < MAX_PCI_CLOCK) + writel(QUARTER_VTCLOCK, PCICLKSELREG); + else + printk(KERN_INFO "Warning: PCI Clock is over 33MHz.\n"); + + /* Supply PCI clock by PCI bus */ + vr41xx_clock_supply(PCI_CLOCK); + + /* + * Set PCI memory & I/O space address conversion registers + * for master transaction. + */ + if (map->mem1 != NULL) { + s = map->mem1; + config = (s->internal_base & 0xff000000) | + ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) | + ((s->pci_base & 0xff000000) >> 24); + writel(config, PCIMMAW1REG); + } + if (map->mem2 != NULL) { + s = map->mem2; + config = (s->internal_base & 0xff000000) | + ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) | + ((s->pci_base & 0xff000000) >> 24); + writel(config, PCIMMAW2REG); + } + if (map->io != NULL) { + s = map->io; + config = (s->internal_base & 0xff000000) | + ((s->address_mask & 0x7f000000) >> 11) | (1UL << 12) | + ((s->pci_base & 0xff000000) >> 24); + writel(config, PCIMIOAWREG); + } + + /* Set target memory windows */ + writel(0x00081000, PCITAW1REG); + writel(0UL, PCITAW2REG); + pciu_write_config_dword(PCI_BASE_ADDRESS_0, 0UL); + pciu_write_config_dword(PCI_BASE_ADDRESS_1, 0UL); + + /* Clear bus error */ + n = readl(BUSERRADREG); + + if (current_cpu_data.cputype == CPU_VR4122) { + writel(0UL, PCITRDYVREG); + pciu_write_config_dword(PCI_CACHE_LINE_SIZE, 0x0000f804); + } else { + writel(100UL, PCITRDYVREG); + pciu_write_config_dword(PCI_CACHE_LINE_SIZE, 0x00008004); + } + + writel(CONFIG_DONE, PCIENREG); + pciu_write_config_dword(PCI_COMMAND, + PCI_COMMAND_IO | + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/pci/pci-vr41xx.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,167 @@ +/* + * FILE NAME + * arch/mips/vr41xx/common/pciu.h + * + * BRIEF MODULE DESCRIPTION + * Include file for PCI Control Unit of the NEC VR4100 series. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Changes: + * MontaVista Software Inc. or + * - New creation, NEC VR4122 and VR4131 are supported. + */ +#ifndef __VR41XX_PCIU_H +#define __VR41XX_PCIU_H + +#include +#include + +#define BIT(x) (1 << (x)) + +#define PCIMMAW1REG KSEG1ADDR(0x0f000c00) +#define PCIMMAW2REG KSEG1ADDR(0x0f000c04) +#define PCITAW1REG KSEG1ADDR(0x0f000c08) +#define PCITAW2REG KSEG1ADDR(0x0f000c0c) +#define PCIMIOAWREG KSEG1ADDR(0x0f000c10) +#define INTERNAL_BUS_BASE_ADDRESS 0xff000000 +#define ADDRESS_MASK 0x000fe000 +#define PCI_ACCESS_ENABLE BIT(12) +#define PCI_ADDRESS_SETTING 0x000000ff + +#define PCICONFDREG KSEG1ADDR(0x0f000c14) +#define PCICONFAREG KSEG1ADDR(0x0f000c18) +#define PCIMAILREG KSEG1ADDR(0x0f000c1c) + +#define BUSERRADREG KSEG1ADDR(0x0f000c24) +#define ERROR_ADDRESS 0xfffffffc + +#define INTCNTSTAREG KSEG1ADDR(0x0f000c28) +#define MABTCLR BIT(31) +#define TRDYCLR BIT(30) +#define PARCLR BIT(29) +#define MBCLR BIT(28) +#define SERRCLR BIT(27) + +#define PCIEXACCREG KSEG1ADDR(0x0f000c2c) +#define UNLOCK BIT(1) +#define EAREQ BIT(0) + +#define PCIRECONTREG KSEG1ADDR(0x0f000c30) +#define RTRYCNT 0x000000ff + +#define PCIENREG KSEG1ADDR(0x0f000c34) +#define CONFIG_DONE BIT(2) + +#define PCICLKSELREG KSEG1ADDR(0x0f000c38) +#define EQUAL_VTCLOCK 0x00000002 +#define HALF_VTCLOCK 0x00000000 +#define QUARTER_VTCLOCK 0x00000001 + +#define PCITRDYVREG KSEG1ADDR(0x0f000c3c) + +#define PCICLKRUNREG KSEG1ADDR(0x0f000c60) + +#define PCIU_CONFIGREGS_BASE KSEG1ADDR(0x0f000d00) +#define VENDORIDREG KSEG1ADDR(0x0f000d00) +#define DEVICEIDREG KSEG1ADDR(0x0f000d00) +#define COMMANDREG KSEG1ADDR(0x0f000d04) +#define STATUSREG KSEG1ADDR(0x0f000d04) +#define REVIDREG KSEG1ADDR(0x0f000d08) +#define CLASSREG KSEG1ADDR(0x0f000d08) +#define CACHELSREG KSEG1ADDR(0x0f000d0c) +#define LATTIMEREG KSEG1ADDR(0x0f000d0c) +#define MAILBAREG KSEG1ADDR(0x0f000d10) +#define PCIMBA1REG KSEG1ADDR(0x0f000d14) +#define PCIMBA2REG KSEG1ADDR(0x0f000d18) +#define INTLINEREG KSEG1ADDR(0x0f000d3c) +#define INTPINREG KSEG1ADDR(0x0f000d3c) +#define RETVALREG KSEG1ADDR(0x0f000d40) +#define PCIAPCNTREG KSEG1ADDR(0x0f000d40) + +#define MPCIINTREG KSEG1ADDR(0x0f0000b2) + +#define MAX_PCI_CLOCK 33333333 + +#define PCIU_CLOCK 0x0080 +#define PCI_CLOCK 0x2000 + +static inline int pciu_read_config_byte(int where, u8 * val) +{ + u32 data; + + data = readl(PCIU_CONFIGREGS_BASE + where); + *val = (u8) (data >> ((where & 3) << 3)); + + return PCIBIOS_SUCCESSFUL; +} + +static inline int pciu_read_config_word(int where, u16 * val) +{ + u32 data; + + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + + data = readl(PCIU_CONFIGREGS_BASE + where); + *val = (u16) (data >> ((where & 2) << 3)); + + return PCIBIOS_SUCCESSFUL; +} + +static inline int pciu_read_config_dword(int where, u32 * val) +{ + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + + *val = readl(PCIU_CONFIGREGS_BASE + where); + + return PCIBIOS_SUCCESSFUL; +} + +static inline int pciu_write_config_byte(int where, u8 val) +{ + writel(val, PCIU_CONFIGREGS_BASE + where); + + return 0; +} + +static inline int pciu_write_config_word(int where, u16 val) +{ + writel(val, PCIU_CONFIGREGS_BASE + where); + + return 0; +} + +static inline int pciu_write_config_dword(int where, u32 val) +{ + writel(val, PCIU_CONFIGREGS_BASE + where); + + return 0; +} + +#endif /* __VR41XX_PCIU_H */ --- linux-2.5.73/arch/mips/philips/nino/int-handler.S 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,137 +0,0 @@ -/* - * linux/arch/mips/philips/nino/int-handler.S - * - * Copyright (C) 1999 Harald Koerfgen - * Copyright (C) 2000 Jim Pick (jim@jimpick.com) - * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Interrupt handler for Philips Nino. - */ -#include -#include -#include -#include -#include - - .data - .globl HighPriVect - -HighPriVect: .word spurious # Reserved - .word io_posnegint0 # IOPOSINT(0) or IONEGINT(0) - .word spurious # CHIDMACNTINT - .word spurious # TELDMACNTINT - .word spurious # SNDDMACNTINT - .word spurious # Reserved - .word io_negint56 # IONEGINT(6) or IONEGINT(5) - .word spurious # Reserved - .word io_posint56 # IOPOSINT(6) or IOPOSINT(5) - .word spurious # Reserved - .word spurious # UARTBRXINT - .word uarta_rx # UARTARXINT - .word spurious # Reserved - .word periodic_timer # PERINT - .word spurious # ALARMINT - .word spurious # POSPWROKINT or NEGPWROKINT - -/* - * Here is the entry point to handle all interrupts. - */ - .text - .set noreorder - .align 5 - NESTED(nino_handle_int, PT_SIZE, ra) - .set noat - SAVE_ALL - CLI - .set at - - /* - * Get pending Interrupts - */ - mfc0 t0, CP0_CAUSE # Get pending interrupts - andi t2, t0, IE_IRQ4 # IRQ4 (high priority) - bne t2, IE_IRQ4, low_priority - nop - -/* - * Ok, we've got a high priority interrupt (a.k.a. an external interrupt). - * Read Interrupt Status Register 6 to get vector. - */ -high_priority: - lui t0, %hi(IntStatus6) - lw t1, %lo(IntStatus6)(t0) - andi t1, INT6_INTVECT - la t2, HighPriVect - addu t1, t1, t2 - lw t2, 0(t1) - jr t2 - nop - -/* - * Ok, we've got one of over a hundred other interrupts. - */ -low_priority: - lui t0, %hi(IntStatus1) - lw t1, %lo(IntStatus1)(t0) - j handle_it - li a0, 20 - -/* - * We don't currently handle spurious interrupts. - */ -spurious: - j spurious_interrupt - nop - -/* - * We have the IRQ number, dispatch to the real handler. - */ -handle_it: jal do_IRQ - move a1,sp - j ret_from_irq - nop - -/************************************ - * High priority interrupt mappings * - ************************************/ - -/* - * Periodic timer - IRQ 0 - */ -periodic_timer: - j handle_it - li a0, 0 - -/* - * UARTA RX - IRQ 3 - */ -uarta_rx: - j handle_it - li a0, 3 - -/* - * GPIO Pin 0 transition - IRQ 10 - */ -io_posnegint0: - j handle_it - li a0, 10 - -/* - * GPIO Pin 5 or 6 transition (0-to-1) - IRQ 11 - */ -io_posint56: - j handle_it - li a0, 11 - -/* - * GPIO Pin 5 or 6 transition (1-to-0) - IRQ 12 - */ -io_negint56: - j handle_it - li a0, 12 - - END(nino_handle_int) --- linux-2.5.73/arch/mips/philips/nino/irq.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,319 +0,0 @@ -/* - * linux/arch/mips/philips/nino/irq.c - * - * Copyright (C) 1992 Linus Torvalds - * Copyright (C) 1999 Harald Koerfgen - * Copyright (C) 2000 Pavel Machek (pavel@suse.cz) - * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Generic interrupt handler for Philips Nino. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -unsigned long spurious_count = 0; - -irq_cpustat_t irq_stat [NR_CPUS]; - -static inline void mask_irq(unsigned int irq_nr) -{ - switch (irq_nr) { - case 0: /* Periodic Timer Interrupt */ - IntClear5 = INT5_PERIODICINT; - IntClear6 = INT6_PERIODICINT; - IntEnable6 &= ~INT6_PERIODICINT; - break; - - case 3: - /* Serial port receive interrupt */ - break; - - case 2: - /* Serial port transmit interrupt */ - break; - - default: - printk( "Attempt to mask unknown IRQ %d?\n", irq_nr ); - } -} - -static inline void unmask_irq(unsigned int irq_nr) -{ - switch (irq_nr) { - case 0: - IntEnable6 |= INT6_PERIODICINT; - break; - - case 3: - /* Serial port receive interrupt */ - break; - - case 2: - /* Serial port transmit interrupt */ - break; - - default: - printk( "Attempt to unmask unknown IRQ %d?\n", irq_nr ); - } -} - -void disable_irq(unsigned int irq_nr) -{ - unsigned long flags; - - save_and_cli(flags); - mask_irq(irq_nr); - restore_flags(flags); -} - -void enable_irq(unsigned int irq_nr) -{ - unsigned long flags; - - save_and_cli(flags); - unmask_irq(irq_nr); - restore_flags(flags); -} - -/* - * Pointers to the low-level handlers: first the general ones, then the - * fast ones, then the bad ones. - */ -extern void interrupt(void); - -static struct irqaction *irq_action[NR_IRQS] = -{ - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL -}; - -int show_interrupts(struct seq_file *p, void *v) -{ - int i; - struct irqaction *action; - unsigned long flags; - - for (i = 0; i < NR_IRQS; i++) { - local_irq_save(flags); - action = irq_action[i]; - if (!action) - goto skip; - seq_printf(p, "%2d: %8d %c %s", - i, kstat_cpu(0).irqs[i], - (action->flags & SA_INTERRUPT) ? '+' : ' ', - action->name); - for (action = action->next; action; action = action->next) { - seq_printf(p, ",%s %s", - (action->flags & SA_INTERRUPT) ? " +" : "", - action->name); - } - seq_putc(p, '\n'); -skip: - local_irq_restore(flags); - } - return 0; -} - -atomic_t __mips_bh_counter; - -/* - * do_IRQ handles IRQ's that have been installed without the - * SA_INTERRUPT flag: it uses the full signal-handling return - * and runs with other interrupts enabled. All relatively slow - * IRQ's should use this format: notably the keyboard/timer - * routines. - */ -asmlinkage void do_IRQ(int irq, struct pt_regs *regs) -{ - struct irqaction *action; - int do_random, cpu; - - if (irq == 20) { - if (IntStatus2 & 0xfffff00) { - if (IntStatus2 & 0x0f000000) - return do_IRQ(2, regs); - } - } - - cpu = smp_processor_id(); - irq_enter(cpu, irq); - kstat_cpu(0).irqs[irq]++; - - if (irq == 20) { - printk("20 %08lx %08lx\n %08lx %08lx\n %08lx\n", - IntStatus1, IntStatus2, IntStatus3, - IntStatus4, IntStatus5 ); - printk("20 %08lx %08lx\n %08lx %08lx\n %08lx\n", - IntEnable1, IntEnable2, IntEnable3, - IntEnable4, IntEnable5 ); - - } - - mask_irq(irq); - action = *(irq + irq_action); - if (action) { - if (!(action->flags & SA_INTERRUPT)) - local_irq_enable(); - do_random = 0; - do { - do_random |= action->flags; - action->handler(irq, action->dev_id, regs); - action = action->next; - } while (action); - if (do_random & SA_SAMPLE_RANDOM) - add_interrupt_randomness(irq); - unmask_irq(irq); - local_irq_disable(); - } else { - IntClear1 = ~0; - IntClear3 = ~0; - IntClear4 = ~0; - IntClear5 = ~0; - unmask_irq(irq); - } - irq_exit(cpu, irq); - - /* unmasking and bottom half handling is done magically for us. */ -} - -/* - * Idea is to put all interrupts - * in a single table and differenciate them just by number. - */ -int setup_nino_irq(int irq, struct irqaction *new) -{ - int shared = 0; - struct irqaction *old, **p; - unsigned long flags; - - p = irq_action + irq; - if ((old = *p) != NULL) { - /* Can't share interrupts unless both agree to */ - if (!(old->flags & new->flags & SA_SHIRQ)) - return -EBUSY; - - /* Can't share interrupts unless both are same type */ - if ((old->flags ^ new->flags) & SA_INTERRUPT) - return -EBUSY; - - /* add new interrupt at end of irq queue */ - do { - p = &old->next; - old = *p; - } while (old); - shared = 1; - } - if (new->flags & SA_SAMPLE_RANDOM) - rand_initialize_irq(irq); - - save_and_cli(flags); - *p = new; - - if (!shared) { - unmask_irq(irq); - } - restore_flags(flags); - return 0; -} - -int request_irq(unsigned int irq, - void (*handler) (int, void *, struct pt_regs *), - unsigned long irqflags, - const char *devname, - void *dev_id) -{ - int retval; - struct irqaction *action; - - if (irq >= NR_IRQS) - return -EINVAL; - if (!handler) - return -EINVAL; - - action = (struct irqaction *) kmalloc(sizeof(struct irqaction), GFP_KERNEL); - if (!action) - return -ENOMEM; - - action->handler = handler; - action->flags = irqflags; - action->mask = 0; - action->name = devname; - action->next = NULL; - action->dev_id = dev_id; - - retval = setup_nino_irq(irq, action); - - if (retval) - kfree(action); - return retval; -} - -void free_irq(unsigned int irq, void *dev_id) -{ - struct irqaction *action, **p; - unsigned long flags; - - if (irq >= NR_IRQS) { - printk(KERN_CRIT __FUNCTION__ ": trying to free IRQ%d\n", irq); - return; - } - for (p = irq + irq_action; (action = *p) != NULL; p = &action->next) { - if (action->dev_id != dev_id) - continue; - - /* Found it - now free it */ - save_and_cli(flags); - *p = action->next; - if (!irq[irq_action]) - mask_irq(irq); - restore_flags(flags); - kfree(action); - return; - } - printk(KERN_CRIT __FUNCTION__ ": trying to free free IRQ%d\n", irq); -} - -unsigned long probe_irq_on(void) -{ - /* TODO */ - return 0; -} - -int probe_irq_off(unsigned long irqs) -{ - /* TODO */ - return 0; -} - -void __init init_IRQ(void) -{ - irq_setup(); -} --- linux-2.5.73/arch/mips/philips/nino/kgdb.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,83 +0,0 @@ -/* - * linux/arch/mips/philips/nino/kgdb.c - * - * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Kernel debugging on the Philips Nino. - */ -#include -#include - -static int remoteDebugInitialized = 0; - -void debugInit(void) -{ -/* - * If low-level debugging (before GDB or console operational) is - * configured, then we do not need to re-initialize the UART. - */ -#ifndef CONFIG_DEBUG_LL - earlyInitUartPR31700(); -#endif -} - -char getDebugChar(void) -{ - char buf; - unsigned long int2, flags; - - if (!remoteDebugInitialized) { - debugInit(); - remoteDebugInitialized = 1; - } - - save_and_cli(flags); - - int2 = IntEnable2; - - IntEnable2 = 0; - - while(!(UartA_Ctrl1 & UART_RX_HOLD_FULL)); - - buf = UartA_Data; - - IntEnable2 = int2; - - restore_flags(flags); - - return buf; -} - -int putDebugChar(char c) -{ - int i; - unsigned long int2; - - if (!remoteDebugInitialized) { - debugInit(); - remoteDebugInitialized = 1; - } - - int2 = IntEnable2; - - IntEnable2 &= - ~(INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY); - - for (i = 0; !(IntStatus2 & INT2_UARTATXINT) && (i < 10000); i++); - - IntClear2 = INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY; - - UartA_Data = c; - - for (i = 0; !(IntStatus2 & INT2_UARTATXINT) && (i < 10000); i++); - - IntClear2 = INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY; - - IntEnable2 = int2; - - return 1; -} --- linux-2.5.73/arch/mips/philips/nino/Makefile 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,17 +0,0 @@ -# -# Makefile for the Philips Nino specific parts of the kernel -# - -obj-y := int-handler.o setup.o irq.o time.o reset.o rtc.o prom.o power.o - -obj-$(CONFIG_REMOTE_DEBUG) += kgdb.o - -obj-$(CONFIG_BLK_DEV_INITRD) += ramdisk.o - -ramdisk.o: - $(MAKE) -C ramdisk - mv ramdisk/ramdisk.o ramdisk.o - -clean: - rm -f *.o - --- linux-2.5.73/arch/mips/philips/nino/power.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,36 +0,0 @@ -/* - * linux/arch/mips/philips/nino/power.c - * - * Copyright (C) 2000 Jim Pick - * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Power management routines on the Philips Nino. - */ -#include - -void nino_wait(void) -{ - /* We stop the CPU to conserve power */ - PowerControl |= PWR_STOPCPU; - - /* - * We wait until an interrupt happens... - */ - - /* We resume here */ - PowerControl &= ~PWR_STOPCPU; - - /* Give ourselves a little delay */ - __asm__ __volatile__( - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t"); -} --- linux-2.5.73/arch/mips/philips/nino/prom.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,80 +0,0 @@ -/* - * linux/arch/mips/philips/nino/prom.c - * - * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Early initialization code for the Philips Nino. - */ -#include -#include -#include -#include -#include -#include -#include - -char arcs_cmdline[COMMAND_LINE_SIZE]; - -#ifdef CONFIG_FB_TX3912 -extern u_long tx3912fb_paddr; -extern u_long tx3912fb_vaddr; -extern u_long tx3912fb_size; -#endif - -/* Do basic initialization */ -void __init prom_init(int argc, char **argv, - unsigned long magic, int *prom_vec) -{ - u_long free_end, mem_size; - u_int i; - - /* - * collect args and prepare cmd_line - */ - for (i = 1; i < argc; i++) { - strcat(arcs_cmdline, argv[i]); - if (i < (argc - 1)) - strcat(arcs_cmdline, " "); - } - - mips_machgroup = MACH_GROUP_PHILIPS; - mips_machtype = MACH_PHILIPS_NINO; - -#ifdef CONFIG_NINO_4MB - mem_size = 4 << 20; -#elif CONFIG_NINO_8MB - mem_size = 8 << 20; -#elif CONFIG_NINO_16MB - mem_size = 16 << 20; -#endif - -#ifdef CONFIG_FB_TX3912 - /* - * The LCD controller requires that the framebuffer - * start address fall within a 1MB segment and is - * aligned on a 16 byte boundary. The way to assure - * this is to place the framebuffer at the end of - * memory and mark it as reserved. - */ - free_end = (mem_size - tx3912fb_size) & PAGE_MASK; - add_memory_region(0, free_end, BOOT_MEM_RAM); - add_memory_region(free_end, (mem_size - free_end), BOOT_MEM_RESERVED); - - /* - * Calculate physical and virtual addresses for - * the beginning of the framebuffer. - */ - tx3912fb_paddr = PHYSADDR(free_end); - tx3912fb_vaddr = KSEG1ADDR(free_end); -#else - add_memory_region(0, mem_size, BOOT_MEM_RAM); -#endif -} - -void __init prom_free_prom_memory (void) -{ -} --- linux-2.5.73/arch/mips/philips/nino/ramdisk/ld.script 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,9 +0,0 @@ -OUTPUT_FORMAT("ecoff-littlemips") -OUTPUT_ARCH(mips) -SECTIONS -{ - .initrd : - { - *(.data) - } -} --- linux-2.5.73/arch/mips/philips/nino/ramdisk/Makefile 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,10 +0,0 @@ -# -# Makefile for the Philips Nino ramdisk -# -# Note! Dependencies are done automagically by 'make dep', which also -# removes any old dependencies. DON'T put your own dependencies here -# unless it's something special (ie not a .c file). -# - -ramdisk.o: ramdisk.gz ld.script - $(LD) $(LDFLAGS) -T ld.script -b binary -o $@ ramdisk.gz --- linux-2.5.73/arch/mips/philips/nino/reset.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,37 +0,0 @@ -/* - * linux/arch/mips/philips/nino/reset.c - * - * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Generic restart, halt and power off functions for Philips Nino. - */ -#include -#include - -void (*reset_vector)(void) = (void (*)(void)) 0xBFC00000; - -void nino_machine_restart(char *command) -{ - reset_vector(); -} - -void nino_machine_halt(void) -{ - reset_vector(); -} - -void nino_machine_power_off(void) -{ - reset_vector(); -} - -void __init setup_nino_reset_vectors(void) -{ - _machine_restart = nino_machine_restart; - _machine_halt = nino_machine_halt; - _machine_power_off = nino_machine_power_off; -} --- linux-2.5.73/arch/mips/philips/nino/rtc.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,34 +0,0 @@ -/* - * linux/arch/mips/philips/nino/rtc.c - * - * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Functions to access RTC on the Philips Nino. - */ -#include -#include - -static unsigned char nino_rtc_read_data(unsigned long addr) -{ - return 0; -} - -static void nino_rtc_write_data(unsigned char data, unsigned long addr) -{ -} - -static int nino_rtc_bcd_mode(void) -{ - return 0; -} - -struct rtc_ops nino_rtc_ops = -{ - &nino_rtc_read_data, - &nino_rtc_write_data, - &nino_rtc_bcd_mode -}; --- linux-2.5.73/arch/mips/philips/nino/setup.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,120 +0,0 @@ -/* - * linux/arch/mips/philips/nino/setup.c - * - * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Interrupt and exception initialization for Philips Nino. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern struct rtc_ops nino_rtc_ops; - -extern void nino_wait(void); -extern void setup_nino_reset_vectors(void); -extern asmlinkage void nino_handle_int(void); -extern int setup_nino_irq(int, struct irqaction *); -void (*board_time_init) (struct irqaction * irq); - -#ifdef CONFIG_REMOTE_DEBUG -extern void set_debug_traps(void); -extern void breakpoint(void); -static int remote_debug = 0; -#endif - -static void __init nino_irq_setup(void) -{ - unsigned int tmp; - - /* Turn all interrupts off */ - IntEnable1 = 0; - IntEnable2 = 0; - IntEnable3 = 0; - IntEnable4 = 0; - IntEnable5 = 0; - IntEnable6 = 0; - - /* Clear all interrupts */ - IntClear1 = 0xffffffff; - IntClear2 = 0xffffffff; - IntClear3 = 0xffffffff; - IntClear4 = 0xffffffff; - IntClear5 = 0xffffffff; - IntClear6 = 0xffffffff; - - /* - * Enable only the interrupts for the UART and negative - * edge (1-to-0) triggered multi-function I/O pins. - */ - change_cp0_status(ST0_BEV, 0); - tmp = read_32bit_cp0_register(CP0_STATUS); - change_cp0_status(ST0_IM, tmp | IE_IRQ2 | IE_IRQ4); - - /* Register the global interrupt handler */ - set_except_vector(0, nino_handle_int); - -#ifdef CONFIG_REMOTE_DEBUG - if (remote_debug) { - set_debug_traps(); - breakpoint(); - } -#endif -} - -static __init void nino_time_init(struct irqaction *irq) -{ - unsigned int scratch = 0; - - /* - * Enable periodic interrupts - */ - setup_nino_irq(0, irq); - - RTCperiodTimer = PER_TIMER_COUNT; - RTCtimerControl = TIM_ENPERTIMER; - IntEnable5 |= INT5_PERIODICINT; - - scratch = inl(TX3912_CLK_CTRL_BASE); - scratch |= TX3912_CLK_CTRL_ENTIMERCLK; - outl(scratch, TX3912_CLK_CTRL_BASE); - - /* Enable all interrupts */ - IntEnable6 |= INT6_GLOBALEN | INT6_PERIODICINT; -} - -void __init nino_setup(void) -{ - irq_setup = nino_irq_setup; - - board_time_init = nino_time_init; - - /* Base address to use for PC type I/O accesses */ - mips_io_port_base = KSEG1ADDR(0xB0C00000); - - setup_nino_reset_vectors(); - - /* Function called during process idle (cpu_idle) */ - cpu_wait = nino_wait; - -#ifdef CONFIG_FB - conswitchp = &dummy_con; -#endif - -#ifdef CONFIG_REMOTE_DEBUG - remote_debug = 1; -#endif - - rtc_ops = &nino_rtc_ops; -} --- linux-2.5.73/arch/mips/philips/nino/time.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,218 +0,0 @@ -/* - * linux/arch/mips/philips/nino/time.c - * - * Copyright (C) 1999 Harald Koerfgen - * Copyright (C) 2000 Pavel Machek (pavel@suse.cz) - * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Time handling functinos for Philips Nino. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern volatile unsigned long wall_jiffies; - -static struct timeval xbase; - -#define USECS_PER_JIFFY (1000000/HZ) - -/* - * Poll the Interrupt Status Registers - */ -#undef POLL_STATUS - -static unsigned long do_gettimeoffset(void) -{ - /* - * This is a kludge - */ - return 0; -} - -static -void inline readRTC(unsigned long *high, unsigned long *low) -{ - /* read twice, and keep reading till we find two - * the same pairs. This is needed in case the RTC - * was updating its registers and we read a old - * High but a new Low. */ - do { - *high = RTChigh & RTC_HIGHMASK; - *low = RTClow; - } while (*high != (RTChigh & RTC_HIGHMASK) || RTClow!=*low); -} - -/* - * This version of gettimeofday has near millisecond resolution. - */ -void do_gettimeofday(struct timeval *tv) -{ - unsigned long flags; - unsigned long seq; - unsigned long high, low; - - do { - seq = read_seqbegin_irqsave(&xtime_lock, flags); - - // 40 bit RTC, driven by 32khz source: - // +-----------+-----------------------------------------+ - // | HHHH.HHHH | LLLL.LLLL.LLLL.LLLL.LMMM.MMMM.MMMM.MMMM | - // +-----------+-----------------------------------------+ - readRTC(&high,&low); - tv->tv_sec = (high << 17) | (low >> 15); - tv->tv_usec = (low % 32768) * 1953 / 64; - tv->tv_sec += xbase.tv_sec; - tv->tv_usec += xbase.tv_usec; - - tv->tv_usec += do_gettimeoffset(); - - /* - * xtime is atomically updated in timer_bh. lost_ticks is - * nonzero if the timer bottom half hasnt executed yet. - */ - if (jiffies - wall_jiffies) - tv->tv_usec += USECS_PER_JIFFY; - } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); - - if (tv->tv_usec >= 1000000) { - tv->tv_usec -= 1000000; - tv->tv_sec++; - } -} - -void do_settimeofday(struct timeval *tv) -{ - write_seqlock_irq(&xtime_lock); - /* This is revolting. We need to set the xtime.tv_usec - * correctly. However, the value in this location is - * is value at the last tick. - * Discover what correction gettimeofday - * would have done, and then undo it! - */ - tv->tv_usec -= do_gettimeoffset(); - - if (tv->tv_usec < 0) { - tv->tv_usec += 1000000; - tv->tv_sec--; - } - - /* reset RTC to 0 (real time is xbase + RTC) */ - xbase = *tv; - RTCtimerControl |= TIM_RTCCLEAR; - RTCtimerControl &= ~TIM_RTCCLEAR; - RTCalarmHigh = RTCalarmLow = ~0UL; - - xtime = *tv; - time_state = TIME_BAD; - time_maxerror = MAXPHASE; - time_esterror = MAXPHASE; - write_sequnlock_irq(&xtime_lock); -} - -static int set_rtc_mmss(unsigned long nowtime) -{ - int retval = 0; - - return retval; -} - -/* last time the cmos clock got updated */ -static long last_rtc_update = 0; - -/* - * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "do_timer()" routine every clocktick - */ - -int do_write = 1; - -static void -timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ -#ifdef POLL_STATUS - static unsigned long old_IntStatus1 = 0; - static unsigned long old_IntStatus3 = 0; - static unsigned long old_IntStatus4 = 0; - static unsigned long old_IntStatus5 = 0; - static int counter = 0; - int i; - - new_spircv = SPIData & 0xff; - if ((old_spircv != new_spircv) && (new_spircv != 0xff)) { - printk( "SPIData changed: %x\n", new_spircv ); - } - old_spircv = new_spircv; - if (do_write) - SPIData = 0; -#endif - - if (!user_mode(regs)) { - if (prof_buffer && current->pid) { - extern int _stext; - unsigned long pc = regs->cp0_epc; - - pc -= (unsigned long) &_stext; - pc >>= prof_shift; - /* - * Dont ignore out-of-bounds pc values silently, - * put them into the last histogram slot, so if - * present, they will show up as a sharp peak. - */ - if (pc > prof_len - 1) - pc = prof_len - 1; - atomic_inc((atomic_t *) & prof_buffer[pc]); - } - } - - /* - * aaaand... action! - */ - do_timer(regs); - - /* - * If we have an externally syncronized Linux clock, then update - * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be - * called as close as possible to 500 ms before the new second starts. - */ - if (time_state != TIME_BAD && xtime.tv_sec > last_rtc_update + 660 && - xtime.tv_usec > 500000 - (tick >> 1) && - xtime.tv_usec < 500000 + (tick >> 1)) - { - if (set_rtc_mmss(xtime.tv_sec) == 0) - last_rtc_update = xtime.tv_sec; - else - last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */ - } -} - -static struct irqaction irq0 = {timer_interrupt, SA_INTERRUPT, 0, - "timer", NULL, NULL}; - -void (*board_time_init) (struct irqaction * irq); - -int __init time_init(void) -{ - struct timeval starttime; - - starttime.tv_sec = mktime(2000, 1, 1, 0, 0, 0); - starttime.tv_usec = 0; - do_settimeofday(&starttime); - - board_time_init(&irq0); - - return 0; -} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ramdisk/ld.script 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,9 @@ +OUTPUT_ARCH(mips) +SECTIONS +{ + .initrd : + { + *(.data) + } +} + --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/ramdisk/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,9 @@ +# +# Makefile for a ramdisk image +# + +O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32) +img = $(CONFIG_EMBEDDED_RAMDISK_IMAGE) +ramdisk.o: $(subst ",,$(img)) ld.script + echo "O_FORMAT: " $(O_FORMAT) + $(LD) -T ld.script -b binary --oformat $(O_FORMAT) -o $@ $(img) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip22/ip22-berr.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,91 @@ +/* + * ip22-berr.c: Bus error handling. + * + * Copyright (C) 2002 Ladislav Michl + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + + +static unsigned int cpu_err_stat; /* Status reg for CPU */ +static unsigned int gio_err_stat; /* Status reg for GIO */ +static unsigned int cpu_err_addr; /* Error address reg for CPU */ +static unsigned int gio_err_addr; /* Error address reg for GIO */ + +static void save_and_clear_buserr(void) +{ + /* save memory controler's error status registers */ + cpu_err_addr = sgimc->cerr; + cpu_err_stat = sgimc->cstat; + gio_err_addr = sgimc->gerr; + gio_err_stat = sgimc->gstat; + + sgimc->cstat = sgimc->gstat = 0; +} + +#define GIO_ERRMASK 0xff00 +#define CPU_ERRMASK 0x3f00 + +static void print_buserr(void) +{ + if (cpu_err_stat & CPU_ERRMASK) + printk(KERN_ALERT "CPU error 0x%x<%s%s%s%s%s%s> @ 0x%08x\n", + cpu_err_stat, + cpu_err_stat & SGIMC_CSTAT_RD ? "RD " : "", + cpu_err_stat & SGIMC_CSTAT_PAR ? "PAR " : "", + cpu_err_stat & SGIMC_CSTAT_ADDR ? "ADDR " : "", + cpu_err_stat & SGIMC_CSTAT_SYSAD_PAR ? "SYSAD " : "", + cpu_err_stat & SGIMC_CSTAT_SYSCMD_PAR ? "SYSCMD " : "", + cpu_err_stat & SGIMC_CSTAT_BAD_DATA ? "BAD_DATA " : "", + cpu_err_addr); + if (gio_err_stat & GIO_ERRMASK) + printk(KERN_ALERT "GIO error 0x%x:<%s%s%s%s%s%s%s%s> @ 0x08%x\n", + gio_err_stat, + gio_err_stat & SGIMC_GSTAT_RD ? "RD " : "", + gio_err_stat & SGIMC_GSTAT_WR ? "WR " : "", + gio_err_stat & SGIMC_GSTAT_TIME ? "TIME " : "", + gio_err_stat & SGIMC_GSTAT_PROM ? "PROM " : "", + gio_err_stat & SGIMC_GSTAT_ADDR ? "ADDR " : "", + gio_err_stat & SGIMC_GSTAT_BC ? "BC " : "", + gio_err_stat & SGIMC_GSTAT_PIO_RD ? "PIO_RD " : "", + gio_err_stat & SGIMC_GSTAT_PIO_WR ? "PIO_WR " : "", + gio_err_addr); +} + +/* + * MC sends an interrupt whenever bus or parity errors occur. In addition, + * if the error happened during a CPU read, it also asserts the bus error + * pin on the R4K. Code in bus error handler save the MC bus error registers + * and then clear the interrupt when this happens. + */ + +void ip22_be_interrupt(int irq, struct pt_regs *regs) +{ + save_and_clear_buserr(); + print_buserr(); + panic("Bus error, epc == %08lx, ra == %08lx", + regs->cp0_epc, regs->regs[31]); +} + +int ip22_be_handler(struct pt_regs *regs, int is_fixup) +{ + save_and_clear_buserr(); + if (is_fixup) + return MIPS_BE_FIXUP; + print_buserr(); + return MIPS_BE_FATAL; +} + +void __init ip22_be_init(void) +{ + board_be_handler = ip22_be_handler; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip22/ip22-eisa.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,307 @@ +/* + * Basic EISA bus support for the SGI Indigo-2. + * + * (C) 2002 Pascal Dameme + * and Marc Zyngier + * + * This code is released under both the GPL version 2 and BSD + * licenses. Either license may be used. + * + * This code offers a very basic support for this EISA bus present in + * the SGI Indigo-2. It currently only supports PIO (forget about DMA + * for the time being). This is enough for a low-end ethernet card, + * but forget about your favorite SCSI card... + * + * TODO : + * - Fix bugs... + * - Add ISA support + * - Add DMA (yeah, right...). + * - Fix more bugs. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EISA_MAX_SLOTS 4 +#define EISA_MAX_IRQ 16 + +#define EISA_TO_PHYS(x) (0x00080000 | (x)) +#define EISA_TO_KSEG1(x) ((void *) KSEG1ADDR(EISA_TO_PHYS((x)))) + +#define EIU_MODE_REG 0x0009ffc0 +#define EIU_STAT_REG 0x0009ffc4 +#define EIU_PREMPT_REG 0x0009ffc8 +#define EIU_QUIET_REG 0x0009ffcc +#define EIU_INTRPT_ACK 0x00090004 + +#define EISA_DMA1_STATUS 8 +#define EISA_INT1_CTRL 0x20 +#define EISA_INT1_MASK 0x21 +#define EISA_INT2_CTRL 0xA0 +#define EISA_INT2_MASK 0xA1 +#define EISA_DMA2_STATUS 0xD0 +#define EISA_DMA2_WRITE_SINGLE 0xD4 +#define EISA_EXT_NMI_RESET_CTRL 0x461 +#define EISA_INT1_EDGE_LEVEL 0x4D0 +#define EISA_INT2_EDGE_LEVEL 0x4D1 +#define EISA_VENDOR_ID_OFFSET 0xC80 + +#define EIU_WRITE_32(x,y) { *((u32 *) KSEG1ADDR(x)) = (u32) (y); mb(); } +#define EIU_READ_8(x) *((u8 *) KSEG1ADDR(x)) +#define EISA_WRITE_8(x,y) { *((u8 *) EISA_TO_KSEG1(x)) = (u8) (y); mb(); } +#define EISA_READ_8(x) *((u8 *) EISA_TO_KSEG1(x)) + +static char *decode_eisa_sig(u8 * sig) +{ + static char sig_str[8]; + u16 rev; + + if (sig[0] & 0x80) + return NULL; + + sig_str[0] = ((sig[0] >> 2) & 0x1f) + ('A' - 1); + sig_str[1] = (((sig[0] & 3) << 3) | (sig[1] >> 5)) + ('A' - 1); + sig_str[2] = (sig[1] & 0x1f) + ('A' - 1); + rev = (sig[2] << 8) | sig[3]; + sprintf(sig_str + 3, "%04X", rev); + + return sig_str; +} + +static void ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs) +{ + u8 eisa_irq; + u8 dma1, dma2; + + eisa_irq = EIU_READ_8(EIU_INTRPT_ACK); + dma1 = EISA_READ_8(EISA_DMA1_STATUS); + dma2 = EISA_READ_8(EISA_DMA2_STATUS); + + if (eisa_irq >= EISA_MAX_IRQ) { + /* Oops, Bad Stuff Happened... */ + printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq); + + EISA_WRITE_8(EISA_INT2_CTRL, 0x20); + EISA_WRITE_8(EISA_INT1_CTRL, 0x20); + } else + do_IRQ(eisa_irq, regs); +} + +static void enable_eisa1_irq(unsigned int irq) +{ + unsigned long flags; + u8 mask; + + local_irq_save(flags); + + mask = EISA_READ_8(EISA_INT1_MASK); + mask &= ~((u8) (1 << irq)); + EISA_WRITE_8(EISA_INT1_MASK, mask); + + local_irq_restore(flags); +} + +static unsigned int startup_eisa1_irq(unsigned int irq) +{ + u8 edge; + + /* Only use edge interrupts for EISA */ + + edge = EISA_READ_8(EISA_INT1_EDGE_LEVEL); + edge &= ~((u8) (1 << irq)); + EISA_WRITE_8(EISA_INT1_EDGE_LEVEL, edge); + + enable_eisa1_irq(irq); + return 0; +} + +static void disable_eisa1_irq(unsigned int irq) +{ + u8 mask; + + mask = EISA_READ_8(EISA_INT1_MASK); + mask |= ((u8) (1 << irq)); + EISA_WRITE_8(EISA_INT1_MASK, mask); +} + +#define shutdown_eisa1_irq disable_eisa1_irq + +static void mask_and_ack_eisa1_irq(unsigned int irq) +{ + disable_eisa1_irq(irq); + + EISA_WRITE_8(EISA_INT1_CTRL, 0x20); +} + +static void end_eisa1_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + enable_eisa1_irq(irq); +} + +static struct hw_interrupt_type ip22_eisa1_irq_type = { + .typename = "IP22 EISA", + .startup = startup_eisa1_irq, + .shutdown = shutdown_eisa1_irq, + .enable = enable_eisa1_irq, + .disable = disable_eisa1_irq, + .ack = mask_and_ack_eisa1_irq, + .end = end_eisa1_irq, +}; + +static void enable_eisa2_irq(unsigned int irq) +{ + unsigned long flags; + u8 mask; + + local_irq_save(flags); + + mask = EISA_READ_8(EISA_INT2_MASK); + mask &= ~((u8) (1 << (irq - 8))); + EISA_WRITE_8(EISA_INT2_MASK, mask); + + local_irq_restore(flags); +} + +static unsigned int startup_eisa2_irq(unsigned int irq) +{ + u8 edge; + + /* Only use edge interrupts for EISA */ + + edge = EISA_READ_8(EISA_INT2_EDGE_LEVEL); + edge &= ~((u8) (1 << (irq - 8))); + EISA_WRITE_8(EISA_INT2_EDGE_LEVEL, edge); + + enable_eisa2_irq(irq); + return 0; +} + +static void disable_eisa2_irq(unsigned int irq) +{ + u8 mask; + + mask = EISA_READ_8(EISA_INT2_MASK); + mask |= ((u8) (1 << (irq - 8))); + EISA_WRITE_8(EISA_INT2_MASK, mask); +} + +#define shutdown_eisa2_irq disable_eisa2_irq + +static void mask_and_ack_eisa2_irq(unsigned int irq) +{ + disable_eisa2_irq(irq); + + EISA_WRITE_8(EISA_INT2_CTRL, 0x20); + EISA_WRITE_8(EISA_INT1_CTRL, 0x20); +} + +static void end_eisa2_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + enable_eisa2_irq(irq); +} + +static struct hw_interrupt_type ip22_eisa2_irq_type = { + .typename = "IP22 EISA", + .startup = startup_eisa2_irq, + .shutdown = shutdown_eisa2_irq, + .enable = enable_eisa2_irq, + .disable = disable_eisa2_irq, + .ack = mask_and_ack_eisa2_irq, + .end = end_eisa2_irq, +}; + +static struct irqaction eisa_action = { + .handler = ip22_eisa_intr, + .name = "EISA", +}; + +static struct irqaction cascade_action = { + .handler = no_action, + .name = "EISA cascade", +}; + +int __init ip22_eisa_init(void) +{ + int i, c; + char *str; + u8 *slot_addr; + + if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) { + printk(KERN_INFO "EISA: bus not present.\n"); + return 1; + } + + printk(KERN_INFO "EISA: Probing bus...\n"); + for (c = 0, i = 1; i <= EISA_MAX_SLOTS; i++) { + slot_addr = + (u8 *) EISA_TO_KSEG1((0x1000 * i) + + EISA_VENDOR_ID_OFFSET); + if ((str = decode_eisa_sig(slot_addr))) { + printk(KERN_INFO "EISA: slot %d : %s detected.\n", + i, str); + c++; + } + } + printk(KERN_INFO "EISA: Detected %d card%s.\n", c, c < 2 ? "" : "s"); +#ifdef CONFIG_ISA + printk(KERN_INFO "ISA support compiled in.\n"); +#endif + + /* Warning : BlackMagicAhead(tm). + Please wave your favorite dead chicken over the busses */ + + /* First say hello to the EIU */ + EIU_WRITE_32(EIU_PREMPT_REG, 0x0000FFFF); + EIU_WRITE_32(EIU_QUIET_REG, 1); + EIU_WRITE_32(EIU_MODE_REG, 0x40f3c07F); + + /* Now be nice to the EISA chipset */ + EISA_WRITE_8(EISA_EXT_NMI_RESET_CTRL, 1); + for (i = 0; i < 10000; i++); /* Wait long enough for the dust to settle */ + EISA_WRITE_8(EISA_EXT_NMI_RESET_CTRL, 0); + EISA_WRITE_8(EISA_INT1_CTRL, 0x11); + EISA_WRITE_8(EISA_INT2_CTRL, 0x11); + EISA_WRITE_8(EISA_INT1_MASK, 0); + EISA_WRITE_8(EISA_INT2_MASK, 8); + EISA_WRITE_8(EISA_INT1_MASK, 4); + EISA_WRITE_8(EISA_INT2_MASK, 2); + EISA_WRITE_8(EISA_INT1_MASK, 1); + EISA_WRITE_8(EISA_INT2_MASK, 1); + EISA_WRITE_8(EISA_INT1_MASK, 0xfb); + EISA_WRITE_8(EISA_INT2_MASK, 0xff); + EISA_WRITE_8(EISA_DMA2_WRITE_SINGLE, 0); + + for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + if (i < (SGINT_EISA + 8)) + irq_desc[i].handler = &ip22_eisa1_irq_type; + else + irq_desc[i].handler = &ip22_eisa2_irq_type; + } + + /* Cannot use request_irq because of kmalloc not being ready at such + * an early stage. Yes, I've been bitten... */ + setup_irq(SGI_EISA_IRQ, &eisa_action); + setup_irq(SGINT_EISA + 2, &cascade_action); + + EISA_bus = 1; + return 0; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip22/ip22-hpc.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,53 @@ +/* + * ip22-hpc.c: Routines for generic manipulation of the HPC controllers. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1998 Ralf Baechle + */ + +#include +#include + +#include +#include +#include +#include + +struct hpc3_regs *hpc3c0, *hpc3c1; +struct sgioc_regs *sgioc; + +/* We need software copies of these because they are write only. */ +u8 sgi_ioc_reset, sgi_ioc_write; + +extern char *system_type; + +void __init sgihpc_init(void) +{ + hpc3c0 = (struct hpc3_regs *)(KSEG1 + HPC3_CHIP0_BASE); + hpc3c1 = (struct hpc3_regs *)(KSEG1 + HPC3_CHIP1_BASE); + /* IOC lives in PBUS PIO channel 6 */ + sgioc = (struct sgioc_regs *)hpc3c0->pbus_extregs[6]; + + hpc3c0->pbus_piocfg[6][0] |= HPC3_PIOCFG_DS16; + if (ip22_is_fullhouse()) { + /* Full House comes with INT2 which lives in PBUS PIO + * channel 4 */ + sgint = (struct sgint_regs *)hpc3c0->pbus_extregs[4]; + system_type = "SGI Indigo2"; + } else { + /* Guiness comes with INT3 which is part of IOC */ + sgint = &sgioc->int3; + system_type = "SGI Indy"; + } + + sgi_ioc_reset = (SGIOC_RESET_PPORT | SGIOC_RESET_KBDMOUSE | + SGIOC_RESET_EISA | SGIOC_RESET_ISDN | + SGIOC_RESET_LC0OFF); + + sgi_ioc_write = (SGIOC_WRITE_EASEL | SGIOC_WRITE_NTHRESH | + SGIOC_WRITE_TPSPEED | SGIOC_WRITE_EPSEL | + SGIOC_WRITE_U0AMODE | SGIOC_WRITE_U1AMODE); + + sgioc->reset = sgi_ioc_reset; + sgioc->write = sgi_ioc_write; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip22/ip22-int.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,412 @@ +/* + * ip22-int.c: Routines for generic manipulation of the INT[23] ASIC + * found on INDY and Indigo2 workstations. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) + * - Indigo2 changes + * - Interrupt handling fixes + * Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org) + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +/* #define DEBUG_SGINT */ + +/* So far nothing hangs here */ +#undef USE_LIO3_IRQ + +struct sgint_regs *sgint; + +static char lc0msk_to_irqnr[256]; +static char lc1msk_to_irqnr[256]; +static char lc2msk_to_irqnr[256]; +static char lc3msk_to_irqnr[256]; + +extern asmlinkage void indyIRQ(void); +extern int ip22_eisa_init(void); + +static void enable_local0_irq(unsigned int irq) +{ + unsigned long flags; + + local_irq_save(flags); + /* don't allow mappable interrupt to be enabled from setup_irq, + * we have our own way to do so */ + if (irq != SGI_MAP_0_IRQ) + sgint->imask0 |= (1 << (irq - SGINT_LOCAL0)); + local_irq_restore(flags); +} + +static unsigned int startup_local0_irq(unsigned int irq) +{ + enable_local0_irq(irq); + return 0; /* Never anything pending */ +} + +static void disable_local0_irq(unsigned int irq) +{ + unsigned long flags; + + local_irq_save(flags); + sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0)); + local_irq_restore(flags); +} + +#define shutdown_local0_irq disable_local0_irq +#define mask_and_ack_local0_irq disable_local0_irq + +static void end_local0_irq (unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_local0_irq(irq); +} + +static struct hw_interrupt_type ip22_local0_irq_type = { + .typename = "IP22 local 0", + .startup = startup_local0_irq, + .shutdown = shutdown_local0_irq, + .enable = enable_local0_irq, + .disable = disable_local0_irq, + .ack = mask_and_ack_local0_irq, + .end = end_local0_irq, +}; + +static void enable_local1_irq(unsigned int irq) +{ + unsigned long flags; + + local_irq_save(flags); + /* don't allow mappable interrupt to be enabled from setup_irq, + * we have our own way to do so */ + if (irq != SGI_MAP_1_IRQ) + sgint->imask1 |= (1 << (irq - SGINT_LOCAL1)); + local_irq_restore(flags); +} + +static unsigned int startup_local1_irq(unsigned int irq) +{ + enable_local1_irq(irq); + return 0; /* Never anything pending */ +} + +void disable_local1_irq(unsigned int irq) +{ + unsigned long flags; + + local_irq_save(flags); + sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1)); + local_irq_restore(flags); +} + +#define shutdown_local1_irq disable_local1_irq +#define mask_and_ack_local1_irq disable_local1_irq + +static void end_local1_irq (unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_local1_irq(irq); +} + +static struct hw_interrupt_type ip22_local1_irq_type = { + .typename = "IP22 local 1", + .startup = startup_local1_irq, + .shutdown = shutdown_local1_irq, + .enable = enable_local1_irq, + .disable = disable_local1_irq, + .ack = mask_and_ack_local1_irq, + .end = end_local1_irq, +}; + +static void enable_local2_irq(unsigned int irq) +{ + unsigned long flags; + + local_irq_save(flags); + sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); + sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2)); + local_irq_restore(flags); +} + +static unsigned int startup_local2_irq(unsigned int irq) +{ + enable_local2_irq(irq); + return 0; /* Never anything pending */ +} + +void disable_local2_irq(unsigned int irq) +{ + unsigned long flags; + + local_irq_save(flags); + sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2)); + if (!sgint->cmeimask0) + sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); + local_irq_restore(flags); +} + +#define shutdown_local2_irq disable_local2_irq +#define mask_and_ack_local2_irq disable_local2_irq + +static void end_local2_irq (unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_local2_irq(irq); +} + +static struct hw_interrupt_type ip22_local2_irq_type = { + .typename = "IP22 local 2", + .startup = startup_local2_irq, + .shutdown = shutdown_local2_irq, + .enable = enable_local2_irq, + .disable = disable_local2_irq, + .ack = mask_and_ack_local2_irq, + .end = end_local2_irq, +}; + +static void enable_local3_irq(unsigned int irq) +{ + unsigned long flags; + + local_irq_save(flags); + sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); + sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3)); + local_irq_restore(flags); +} + +static unsigned int startup_local3_irq(unsigned int irq) +{ + enable_local3_irq(irq); + return 0; /* Never anything pending */ +} + +void disable_local3_irq(unsigned int irq) +{ + unsigned long flags; + + local_irq_save(flags); + sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3)); + if (!sgint->cmeimask1) + sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); + local_irq_restore(flags); +} + +#define shutdown_local3_irq disable_local3_irq +#define mask_and_ack_local3_irq disable_local3_irq + +static void end_local3_irq (unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_local3_irq(irq); +} + +static struct hw_interrupt_type ip22_local3_irq_type = { + .typename = "IP22 local 3", + .startup = startup_local3_irq, + .shutdown = shutdown_local3_irq, + .enable = enable_local3_irq, + .disable = disable_local3_irq, + .ack = mask_and_ack_local3_irq, + .end = end_local3_irq, +}; + +void indy_local0_irqdispatch(struct pt_regs *regs) +{ + u8 mask = sgint->istat0 & sgint->imask0; + u8 mask2; + int irq; + + if (mask & SGINT_ISTAT0_LIO2) { + mask2 = sgint->vmeistat & sgint->cmeimask0; + irq = lc2msk_to_irqnr[mask2]; + } else + irq = lc0msk_to_irqnr[mask]; + + /* if irq == 0, then the interrupt has already been cleared */ + if (irq) + do_IRQ(irq, regs); + return; +} + +void indy_local1_irqdispatch(struct pt_regs *regs) +{ + u8 mask = sgint->istat1 & sgint->imask1; + u8 mask2; + int irq; + + if (mask & SGINT_ISTAT1_LIO3) { + mask2 = sgint->vmeistat & sgint->cmeimask1; + irq = lc3msk_to_irqnr[mask2]; + } else + irq = lc1msk_to_irqnr[mask]; + + /* if irq == 0, then the interrupt has already been cleared */ + if (irq) + do_IRQ(irq, regs); + return; +} + +extern void ip22_be_interrupt(int irq, struct pt_regs *regs); + +void indy_buserror_irq(struct pt_regs *regs) +{ + int cpu = smp_processor_id(); + int irq = SGI_BUSERR_IRQ; + + irq_enter(); + kstat_cpu(cpu).irqs[irq]++; + ip22_be_interrupt(irq, regs); + irq_exit(); +} + +static struct irqaction local0_cascade = { + .handler = no_action, + .flags = SA_INTERRUPT, + .name = "local0 cascade", +}; + +static struct irqaction local1_cascade = { + .handler = no_action, + .flags = SA_INTERRUPT, + .name = "local1 cascade", +}; + +static struct irqaction buserr = { + .handler = no_action, + .flags = SA_INTERRUPT, + .name = "Bus Error", +}; + +static struct irqaction map0_cascade = { + .handler = no_action, + .flags = SA_INTERRUPT, + .name = "mapable0 cascade", +}; + +#ifdef USE_LIO3_IRQ +static struct irqaction map1_cascade = { + .handler = no_action, + .flags = SA_INTERRUPT, + .name = "mapable1 cascade", +}; +#define SGI_INTERRUPTS SGINT_END +#else +#define SGI_INTERRUPTS SGINT_LOCAL3 +#endif + +extern void mips_cpu_irq_init(unsigned int irq_base); + +void __init init_IRQ(void) +{ + int i; + + /* Init local mask --> irq tables. */ + for (i = 0; i < 256; i++) { + if (i & 0x80) { + lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7; + lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7; + lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7; + lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7; + } else if (i & 0x40) { + lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6; + lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6; + lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6; + lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6; + } else if (i & 0x20) { + lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5; + lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5; + lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5; + lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5; + } else if (i & 0x10) { + lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4; + lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4; + lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4; + lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4; + } else if (i & 0x08) { + lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3; + lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3; + lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3; + lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3; + } else if (i & 0x04) { + lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2; + lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2; + lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2; + lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2; + } else if (i & 0x02) { + lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1; + lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1; + lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1; + lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1; + } else if (i & 0x01) { + lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0; + lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0; + lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0; + lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0; + } else { + lc0msk_to_irqnr[i] = 0; + lc1msk_to_irqnr[i] = 0; + lc2msk_to_irqnr[i] = 0; + lc3msk_to_irqnr[i] = 0; + } + } + + /* Mask out all interrupts. */ + sgint->imask0 = 0; + sgint->imask1 = 0; + sgint->cmeimask0 = 0; + sgint->cmeimask1 = 0; + + set_except_vector(0, indyIRQ); + + init_generic_irq(); + /* init CPU irqs */ + mips_cpu_irq_init(SGINT_CPU); + + for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) { + hw_irq_controller *handler; + + if (i < SGINT_LOCAL1) + handler = &ip22_local0_irq_type; + else if (i < SGINT_LOCAL2) + handler = &ip22_local1_irq_type; + else if (i < SGINT_LOCAL3) + handler = &ip22_local2_irq_type; + else + handler = &ip22_local3_irq_type; + + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = handler; + } + + /* vector handler. this register the IRQ as non-sharable */ + setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade); + setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade); + setup_irq(SGI_BUSERR_IRQ, &buserr); + + /* cascade in cascade. i love Indy ;-) */ + setup_irq(SGI_MAP_0_IRQ, &map0_cascade); +#ifdef USE_LIO3_IRQ + setup_irq(SGI_MAP_1_IRQ, &map1_cascade); +#endif + +#ifdef CONFIG_EISA + if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */ + ip22_eisa_init (); +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip22/ip22-irq.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,118 @@ +/* + * ip22-irq.S: Interrupt exception dispatch code for FullHouse and + * Guiness. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + */ + +#include +#include +#include +#include + +/* A lot of complication here is taken away because: + * + * 1) We handle one interrupt and return, sitting in a loop and moving across + * all the pending IRQ bits in the cause register is _NOT_ the answer, the + * common case is one pending IRQ so optimize in that direction. + * + * 2) We need not check against bits in the status register IRQ mask, that + * would make this routine slow as hell. + * + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in + * between like BSD spl() brain-damage. + * + * Furthermore, the IRQs on the INDY look basically (barring software IRQs + * which we don't use at all) like: + * + * MIPS IRQ Source + * -------- ------ + * 0 Software (ignored) + * 1 Software (ignored) + * 2 Local IRQ level zero + * 3 Local IRQ level one + * 4 8254 Timer zero + * 5 8254 Timer one + * 6 Bus Error + * 7 R4k timer (what we use) + * + * We handle the IRQ according to _our_ priority which is: + * + * Highest ---- R4k Timer + * Local IRQ zero + * Local IRQ one + * Bus Error + * 8254 Timer zero + * Lowest ---- 8254 Timer one + * + * then we just return, if multiple IRQs are pending then we will just take + * another exception, big deal. + */ + + .text + .set noreorder + .set noat + .align 5 + NESTED(indyIRQ, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + mfc0 s0, CP0_CAUSE # get irq mask + + /* First we check for r4k counter/timer IRQ. */ + andi a0, s0, CAUSEF_IP7 + beq a0, zero, 1f + andi a0, s0, CAUSEF_IP2 # delay slot, check local level zero + + /* Wheee, a timer interrupt. */ + jal indy_r4k_timer_interrupt + move a0, sp # delay slot + j ret_from_irq + nop # delay slot + +1: + beq a0, zero, 1f + andi a0, s0, CAUSEF_IP3 # delay slot, check local level one + + /* Wheee, local level zero interrupt. */ + jal indy_local0_irqdispatch + move a0, sp # delay slot + + j ret_from_irq + nop # delay slot + +1: + beq a0, zero, 1f + andi a0, s0, CAUSEF_IP6 # delay slot, check bus error + + /* Wheee, local level one interrupt. */ + jal indy_local1_irqdispatch + move a0, sp # delay slot + j ret_from_irq + nop # delay slot + +1: + beq a0, zero, 1f + andi a0, s0, (CAUSEF_IP4 | CAUSEF_IP5) # delay slot + + /* Wheee, an asynchronous bus error... */ + jal indy_buserror_irq + move a0, sp # delay slot + j ret_from_irq + nop # delay slot + +1: + /* Here by mistake? It is possible, that by the time we take + * the exception the IRQ pin goes low, so just leave if this + * is the case. + */ + beq a0, zero, 1f + nop # delay slot + + /* Must be one of the 8254 timers... */ + jal indy_8254timer_irq + move a0, sp # delay slot +1: + j ret_from_irq + nop # delay slot + END(indyIRQ) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip22/ip22-ksyms.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,21 @@ +/* + * ip22-ksyms.c: IP22 specific exports + */ + +#include + +#include +#include +#include +#include + +EXPORT_SYMBOL(sgimc); +EXPORT_SYMBOL(hpc3c0); +EXPORT_SYMBOL(hpc3c1); +EXPORT_SYMBOL(sgioc); + +extern void (*indy_volume_button)(int); +EXPORT_SYMBOL(indy_volume_button); + +EXPORT_SYMBOL(ip22_eeprom_read); +EXPORT_SYMBOL(ip22_nvram_read); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip22/ip22-mc.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,201 @@ +/* + * ip22-mc.c: Routines for manipulating SGI Memory Controller. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes + * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org) + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +struct sgimc_regs *sgimc; + +static inline unsigned long get_bank_addr(unsigned int memconfig) +{ + return ((memconfig & SGIMC_MCONFIG_BASEADDR) << + ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22)); +} + +static inline unsigned long get_bank_size(unsigned int memconfig) +{ + return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) << + ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14); +} + +static inline unsigned int get_bank_config(int bank) +{ + unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0; + return bank % 2 ? res & 0xffff : res >> 16; +} + +struct mem { + unsigned long addr; + unsigned long size; +}; + +/* + * Detect installed memory, do some sanity checks and notify kernel about it + */ +static void probe_memory(void) +{ + int i, j, found, cnt = 0; + struct mem bank[4]; + struct mem space[2] = {{SGIMC_SEG0_BADDR, 0}, {SGIMC_SEG1_BADDR, 0}}; + + printk(KERN_INFO "MC: Probing memory configuration:\n"); + for (i = 0; i < ARRAY_SIZE(bank); i++) { + unsigned int tmp = get_bank_config(i); + if (!(tmp & SGIMC_MCONFIG_BVALID)) + continue; + + bank[cnt].size = get_bank_size(tmp); + bank[cnt].addr = get_bank_addr(tmp); + printk(KERN_INFO " bank%d: %3ldM @ %08lx\n", + i, bank[cnt].size / 1024 / 1024, bank[cnt].addr); + cnt++; + } + + /* And you thought bubble sort is dead algorithm... */ + do { + unsigned long addr, size; + + found = 0; + for (i = 1; i < cnt; i++) + if (bank[i-1].addr > bank[i].addr) { + addr = bank[i].addr; + size = bank[i].size; + bank[i].addr = bank[i-1].addr; + bank[i].size = bank[i-1].size; + bank[i-1].addr = addr; + bank[i-1].size = size; + found = 1; + } + } while (found); + + /* Figure out how are memory banks mapped into spaces */ + for (i = 0; i < cnt; i++) { + found = 0; + for (j = 0; j < ARRAY_SIZE(space) && !found; j++) + if (space[j].addr + space[j].size == bank[i].addr) { + space[j].size += bank[i].size; + found = 1; + } + /* There is either hole or overlapping memory */ + if (!found) + printk(KERN_CRIT "MC: Memory configuration mismatch " + "(%08lx), expect Bus Error soon\n", + bank[i].addr); + } + + for (i = 0; i < ARRAY_SIZE(space); i++) + if (space[i].size) + add_memory_region(space[i].addr, space[i].size, + BOOT_MEM_RAM); +} + +void __init sgimc_init(void) +{ + u32 tmp; + + sgimc = (struct sgimc_regs *)(KSEG1 + SGIMC_BASE); + + printk(KERN_INFO "MC: SGI memory controller Revision %d\n", + (int) sgimc->systemid & SGIMC_SYSID_MASKREV); + + /* Place the MC into a known state. This must be done before + * interrupts are first enabled etc. + */ + + /* Step 0: Make sure we turn off the watchdog in case it's + * still running (which might be the case after a + * soft reboot). + */ + tmp = sgimc->cpuctrl0; + tmp &= ~SGIMC_CCTRL0_WDOG; + sgimc->cpuctrl0 = tmp; + + /* Step 1: The CPU/GIO error status registers will not latch + * up a new error status until the register has been + * cleared by the cpu. These status registers are + * cleared by writing any value to them. + */ + sgimc->cstat = sgimc->gstat = 0; + + /* Step 2: Enable all parity checking in cpu control register + * zero. + */ + tmp = sgimc->cpuctrl0; + tmp |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM | + SGIMC_CCTRL0_R4KNOCHKPARR); + sgimc->cpuctrl0 = tmp; + + /* Step 3: Setup the MC write buffer depth, this is controlled + * in cpu control register 1 in the lower 4 bits. + */ + tmp = sgimc->cpuctrl1; + tmp &= ~0xf; + tmp |= 0xd; + sgimc->cpuctrl1 = tmp; + + /* Step 4: Initialize the RPSS divider register to run as fast + * as it can correctly operate. The register is laid + * out as follows: + * + * ---------------------------------------- + * | RESERVED | INCREMENT | DIVIDER | + * ---------------------------------------- + * 31 16 15 8 7 0 + * + * DIVIDER determines how often a 'tick' happens, + * INCREMENT determines by how the RPSS increment + * registers value increases at each 'tick'. Thus, + * for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101 + */ + sgimc->divider = 0x101; + + /* Step 5: Initialize GIO64 arbitrator configuration register. + * + * NOTE: HPC init code in sgihpc_init() must run before us because + * we need to know Guiness vs. FullHouse and the board + * revision on this machine. You have been warned. + */ + + /* First the basic invariants across all GIO64 implementations. */ + tmp = SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */ + tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */ + + if (ip22_is_fullhouse()) { + /* Fullhouse specific settings. */ + if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) { + tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC at 64bits */ + tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp0 pipelines */ + tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */ + tmp |= SGIMC_GIOPAR_RTIMEEXP0; /* exp0 is realtime */ + } else { + tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC 64bits */ + tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */ + tmp |= SGIMC_GIOPAR_PLINEEXP1; + tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */ + tmp |= SGIMC_GIOPAR_GFX64; /* GFX at 64 bits */ + } + } else { + /* Guiness specific settings. */ + tmp |= SGIMC_GIOPAR_EISA64; /* MC talks to EISA at 64bits */ + tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */ + } + sgimc->giopar = tmp; /* poof */ + + probe_memory(); +} + +void __init prom_meminit(void) {} +void __init prom_free_prom_memory (void) {} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip22/ip22-nvram.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,114 @@ +/* + * ip22-nvram.c: NVRAM and serial EEPROM handling. + * + * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org) + */ + +#include +#include + +/* Control opcode for serial eeprom */ +#define EEPROM_READ 0xc000 /* serial memory read */ +#define EEPROM_WEN 0x9800 /* write enable before prog modes */ +#define EEPROM_WRITE 0xa000 /* serial memory write */ +#define EEPROM_WRALL 0x8800 /* write all registers */ +#define EEPROM_WDS 0x8000 /* disable all programming */ +#define EEPROM_PRREAD 0xc000 /* read protect register */ +#define EEPROM_PREN 0x9800 /* enable protect register mode */ +#define EEPROM_PRCLEAR 0xffff /* clear protect register */ +#define EEPROM_PRWRITE 0xa000 /* write protect register */ +#define EEPROM_PRDS 0x8000 /* disable protect register, forever */ + +#define EEPROM_EPROT 0x01 /* Protect register enable */ +#define EEPROM_CSEL 0x02 /* Chip select */ +#define EEPROM_ECLK 0x04 /* EEPROM clock */ +#define EEPROM_DATO 0x08 /* Data out */ +#define EEPROM_DATI 0x10 /* Data in */ + +/* We need to use this functions early... */ +#define delay() ({ \ + int x; \ + for (x=0; x<100000; x++) __asm__ __volatile__(""); }) + +#define eeprom_cs_on(ptr) ({ \ + *ptr &= ~EEPROM_DATO; \ + *ptr &= ~EEPROM_ECLK; \ + *ptr &= ~EEPROM_EPROT; \ + delay(); \ + *ptr |= EEPROM_CSEL; \ + *ptr |= EEPROM_ECLK; }) + + +#define eeprom_cs_off(ptr) ({ \ + *ptr &= ~EEPROM_ECLK; \ + *ptr &= ~EEPROM_CSEL; \ + *ptr |= EEPROM_EPROT; \ + *ptr |= EEPROM_ECLK; }) + +#define BITS_IN_COMMAND 11 +/* + * clock in the nvram command and the register number. For the + * national semiconductor nv ram chip the op code is 3 bits and + * the address is 6/8 bits. + */ +static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd, + unsigned reg) +{ + unsigned short ser_cmd; + int i; + + ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND)); + for (i = 0; i < BITS_IN_COMMAND; i++) { + if (ser_cmd & (1<<15)) /* if high order bit set */ + *ctrl |= EEPROM_DATO; + else + *ctrl &= ~EEPROM_DATO; + *ctrl &= ~EEPROM_ECLK; + *ctrl |= EEPROM_ECLK; + ser_cmd <<= 1; + } + *ctrl &= ~EEPROM_DATO; /* see data sheet timing diagram */ +} + +unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg) +{ + unsigned short res = 0; + int i; + + *ctrl &= ~EEPROM_EPROT; + eeprom_cs_on(ctrl); + eeprom_cmd(ctrl, EEPROM_READ, reg); + + /* clock the data ouf of serial mem */ + for (i = 0; i < 16; i++) { + *ctrl &= ~EEPROM_ECLK; + delay(); + *ctrl |= EEPROM_ECLK; + delay(); + res <<= 1; + if (*ctrl & EEPROM_DATI) + res |= 1; + } + + eeprom_cs_off(ctrl); + + return res; +} + +/* + * Read specified register from main NVRAM + */ +unsigned short ip22_nvram_read(int reg) +{ + if (ip22_is_fullhouse()) + /* IP22 (Indigo2 aka FullHouse) stores env variables into + * 93CS56 Microwire Bus EEPROM 2048 Bit (128x16) */ + return ip22_eeprom_read(&hpc3c0->eeprom, reg); + else { + unsigned short tmp; + /* IP24 (Indy aka Guiness) uses DS1386 8K version */ + reg <<= 1; + tmp = hpc3c0->bbram[reg++] & 0xff; + return (tmp << 8) | (hpc3c0->bbram[reg] & 0xff); + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip22/ip22-reset.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,245 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1997, 1998, 2001, 2003 by Ralf Baechle + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Just powerdown if init hasn't done after POWERDOWN_TIMEOUT seconds. + * I'm not sure if this feature is a good idea, for now it's here just to + * make the power button make behave just like under IRIX. + */ +#define POWERDOWN_TIMEOUT 120 + +/* + * Blink frequency during reboot grace period and when paniced. + */ +#define POWERDOWN_FREQ (HZ / 4) +#define PANIC_FREQ (HZ / 8) + +static struct timer_list power_timer, blink_timer, debounce_timer, volume_timer; + +#define MACHINE_PANICED 1 +#define MACHINE_SHUTTING_DOWN 2 +static int machine_state = 0; + +static void sgi_machine_restart(char *command) __attribute__((noreturn)); +static void sgi_machine_halt(void) __attribute__((noreturn)); +static void sgi_machine_power_off(void) __attribute__((noreturn)); + +/* XXX How to pass the reboot command to the firmware??? */ +static void sgi_machine_restart(char *command) +{ + if (machine_state & MACHINE_SHUTTING_DOWN) + sgi_machine_power_off(); + ArcReboot(); +} + +static void sgi_machine_halt(void) +{ + if (machine_state & MACHINE_SHUTTING_DOWN) + sgi_machine_power_off(); + ArcEnterInteractiveMode(); +} + +static void sgi_machine_power_off(void) +{ + unsigned char val; + + local_irq_disable(); + + /* Disable watchdog */ + val = CMOS_READ(RTC_CMD); + CMOS_WRITE(val | RTC_WAM, RTC_CMD); + CMOS_WRITE(0, RTC_WSEC); + CMOS_WRITE(0, RTC_WHSEC); + + while(1) { + sgioc->panel = ~SGIOC_PANEL_POWERON; + /* Good bye cruel world ... */ + + /* If we're still running, we probably got sent an alarm + interrupt. Read the flag to clear it. */ + val = CMOS_READ(RTC_HOURS_ALARM); + } +} + +static void power_timeout(unsigned long data) +{ + sgi_machine_power_off(); +} + +static void blink_timeout(unsigned long data) +{ + /* XXX fix this for fullhouse */ + sgi_ioc_reset ^= (SGIOC_RESET_LC0OFF|SGIOC_RESET_LC1OFF); + sgioc->reset = sgi_ioc_reset; + + mod_timer(&blink_timer, jiffies+data); +} + +static void debounce(unsigned long data) +{ + del_timer(&debounce_timer); + if (sgint->istat1 & SGINT_ISTAT1_PWR) { + /* Interrupt still being sent. */ + debounce_timer.expires = jiffies + 5; /* 0.05s */ + add_timer(&debounce_timer); + + sgioc->panel = SGIOC_PANEL_POWERON | SGIOC_PANEL_POWERINTR | + SGIOC_PANEL_VOLDNINTR | SGIOC_PANEL_VOLDNHOLD | + SGIOC_PANEL_VOLUPINTR | SGIOC_PANEL_VOLUPHOLD; + + return; + } + + if (machine_state & MACHINE_PANICED) + ArcReboot(); + + enable_irq(SGI_PANEL_IRQ); +} + +static inline void power_button(void) +{ + if (machine_state & MACHINE_PANICED) + return; + + if ((machine_state & MACHINE_SHUTTING_DOWN) || kill_proc(1,SIGINT,1)) { + /* No init process or button pressed twice. */ + sgi_machine_power_off(); + } + + machine_state |= MACHINE_SHUTTING_DOWN; + blink_timer.data = POWERDOWN_FREQ; + blink_timeout(POWERDOWN_FREQ); + + init_timer(&power_timer); + power_timer.function = power_timeout; + power_timer.expires = jiffies + POWERDOWN_TIMEOUT * HZ; + add_timer(&power_timer); +} + +void (*indy_volume_button)(int) = NULL; + +static inline void volume_up_button(unsigned long data) +{ + del_timer(&volume_timer); + + if (indy_volume_button) + indy_volume_button(1); + + if (sgint->istat1 & SGINT_ISTAT1_PWR) { + volume_timer.expires = jiffies + 1; + add_timer(&volume_timer); + } +} + +static inline void volume_down_button(unsigned long data) +{ + del_timer(&volume_timer); + + if (indy_volume_button) + indy_volume_button(-1); + + if (sgint->istat1 & SGINT_ISTAT1_PWR) { + volume_timer.expires = jiffies + 1; + add_timer(&volume_timer); + } +} + +static irqreturn_t panel_int(int irq, void *dev_id, struct pt_regs *regs) +{ + unsigned int buttons; + + buttons = sgioc->panel; + sgioc->panel = SGIOC_PANEL_POWERON | SGIOC_PANEL_POWERINTR; + + if (sgint->istat1 & SGINT_ISTAT1_PWR) { + /* Wait until interrupt goes away */ + disable_irq(SGI_PANEL_IRQ); + init_timer(&debounce_timer); + debounce_timer.function = debounce; + debounce_timer.expires = jiffies + 5; + add_timer(&debounce_timer); + } + + /* Power button was pressed + * + * ioc.ps page 22: "The Panel Register is called Power Control by Full + * House. Only lowest 2 bits are used. Guiness uses upper four bits + * for volume control". This is not true, all bits are pulled high + * on fullhouse + */ + if (ip22_is_fullhouse() || !(buttons & SGIOC_PANEL_POWERINTR)) { + power_button(); + return IRQ_HANDLED; + } + /* TODO: mute/unmute */ + /* Volume up button was pressed */ + if (!(buttons & SGIOC_PANEL_VOLUPINTR)) { + init_timer(&volume_timer); + volume_timer.function = volume_up_button; + volume_timer.expires = jiffies + 1; + add_timer(&volume_timer); + } + /* Volume down button was pressed */ + if (!(buttons & SGIOC_PANEL_VOLDNINTR)) { + init_timer(&volume_timer); + volume_timer.function = volume_down_button; + volume_timer.expires = jiffies + 1; + add_timer(&volume_timer); + } + + return IRQ_HANDLED; +} + +static int panic_event(struct notifier_block *this, unsigned long event, + void *ptr) +{ + if (machine_state & MACHINE_PANICED) + return NOTIFY_DONE; + machine_state |= MACHINE_PANICED; + + blink_timer.data = PANIC_FREQ; + blink_timeout(PANIC_FREQ); + + return NOTIFY_DONE; +} + +static struct notifier_block panic_block = { + .notifier_call = panic_event, +}; + +static int __init reboot_setup(void) +{ + _machine_restart = sgi_machine_restart; + _machine_halt = sgi_machine_halt; + _machine_power_off = sgi_machine_power_off; + + request_irq(SGI_PANEL_IRQ, panel_int, 0, "Front Panel", NULL); + init_timer(&blink_timer); + blink_timer.function = blink_timeout; + notifier_chain_register(&panic_notifier_list, &panic_block); + + return 0; +} + +subsys_initcall(reboot_setup); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip22/ip22-rtc.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,32 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * RTC routines for Indy style attached Dallas chip. + * + * Copyright (C) 1998, 2001 by Ralf Baechle + */ +#include +#include + +static unsigned char ip22_rtc_read_data(unsigned long addr) +{ + return hpc3c0->rtcregs[addr]; +} + +static void ip22_rtc_write_data(unsigned char data, unsigned long addr) +{ + hpc3c0->rtcregs[addr] = data; +} + +static int ip22_rtc_bcd_mode(void) +{ + return 0; +} + +struct rtc_ops ip22_rtc_ops = { + &ip22_rtc_read_data, + &ip22_rtc_write_data, + &ip22_rtc_bcd_mode +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip22/ip22-setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,181 @@ +/* + * ip22-setup.c: SGI specific setup, including init of the feature struct. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org) + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_KGDB +extern void rs_kgdb_hook(int); +extern void breakpoint(void); +static int remote_debug = 0; +#endif + +#if defined(CONFIG_IP22_SERIAL_CONSOLE) || defined(CONFIG_ARC_CONSOLE) +extern void console_setup(char *); +#endif + +extern struct rtc_ops ip22_rtc_ops; + +#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ + +unsigned long sgi_gfxaddr; + +/* + * Stop-A is originally a Sun thing that isn't standard on IP22 so to avoid + * accidents it's disabled by default on IP22. + * + * FIXME: provide a mechanism to change the value of stop_a_enabled. + */ +int serial_console; +int stop_a_enabled; + +void ip22_do_break(void) +{ + if (!stop_a_enabled) + return; + + printk("\n"); + ArcEnterInteractiveMode(); +} + +extern void ip22_be_init(void) __init; +extern void ip22_time_init(void) __init; + +void __init ip22_setup(void) +{ + char *ctype; +#ifdef CONFIG_KGDB + char *kgdb_ttyd; +#endif + + board_be_init = ip22_be_init; + ip22_time_init(); + + /* Init the INDY HPC I/O controller. Need to call this before + * fucking with the memory controller because it needs to know the + * boardID and whether this is a Guiness or a FullHouse machine. + */ + sgihpc_init(); + + /* Init INDY memory controller. */ + sgimc_init(); + +#ifdef CONFIG_BOARD_SCACHE + /* Now enable boardcaches, if any. */ + indy_sc_init(); +#endif +#ifdef CONFIG_VT + conswitchp = NULL; +#endif + /* Set the IO space to some sane value */ + set_io_port_base (KSEG1ADDR (0x00080000)); + + /* ARCS console environment variable is set to "g?" for + * graphics console, it is set to "d" for the first serial + * line and "d2" for the second serial line. + */ + ctype = ArcGetEnvironmentVariable("console"); + if (ctype && *ctype == 'd') { +#ifdef CONFIG_IP22_SERIAL_CONSOLE + if (*(ctype + 1) == '2') + console_setup("ttyS1"); + else + console_setup("ttyS0"); +#endif + } +#ifdef CONFIG_ARC_CONSOLE + else if (!ctype || *ctype != 'g') { + /* Use ARC if we don't want serial ('d') or Newport ('g'). */ + prom_flags |= PROM_FLAG_USE_AS_CONSOLE; + console_setup("arc"); + } +#endif + +#ifdef CONFIG_KGDB + kgdb_ttyd = prom_getcmdline(); + if ((kgdb_ttyd = strstr(kgdb_ttyd, "kgdb=ttyd")) != NULL) { + int line; + kgdb_ttyd += strlen("kgdb=ttyd"); + if (*kgdb_ttyd != '1' && *kgdb_ttyd != '2') + printk(KERN_INFO "KGDB: Uknown serial line /dev/ttyd%c" + ", falling back to /dev/ttyd1\n", *kgdb_ttyd); + line = *kgdb_ttyd == '2' ? 0 : 1; + printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for " + "session\n", line ? 1 : 2); + rs_kgdb_hook(line); + + printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for " + "session, please connect your debugger\n", line ? 1:2); + + remote_debug = 1; + /* Breakpoints and stuff are in sgi_irq_setup() */ + } +#endif + +#ifdef CONFIG_VT +#ifdef CONFIG_SGI_NEWPORT_CONSOLE + if (ctype && *ctype == 'g'){ + unsigned long *gfxinfo; + long (*__vec)(void) = + (void *) *(long *)(long)((PROMBLOCK)->pvector + 0x20); + + gfxinfo = (unsigned long *)__vec(); + sgi_gfxaddr = ((gfxinfo[1] >= 0xa0000000 + && gfxinfo[1] <= 0xc0000000) + ? gfxinfo[1] - 0xa0000000 : 0); + + /* newport addresses? */ + if (sgi_gfxaddr == 0x1f0f0000 || sgi_gfxaddr == 0x1f4f0000) { + conswitchp = &newport_con; + + screen_info = (struct screen_info) { + 0, 0, /* orig-x, orig-y */ + 0, /* unused */ + 0, /* orig_video_page */ + 0, /* orig_video_mode */ + 160, /* orig_video_cols */ + 0, 0, 0, /* unused, ega_bx, unused */ + 64, /* orig_video_lines */ + 0, /* orig_video_isVGA */ + 16 /* orig_video_points */ + }; + } + } +#endif +#ifdef CONFIG_DUMMY_CONSOLE + /* Either if newport console wasn't used or failed to initialize. */ +#ifdef CONFIG_SGI_NEWPORT_CONSOLE + if(conswitchp != &newport_con) +#endif + conswitchp = &dummy_con; +#endif +#endif + rtc_ops = &ip22_rtc_ops; +#ifdef CONFIG_PSMOUSE + aux_device_present = 0xaa; +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip22/ip22-time.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,219 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Time operations for IP22 machines. Original code may come from + * Ralf Baechle or David S. Miller (sorry guys, i'm really not sure) + * + * Copyright (C) 2001 by Ladislav Michl + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * note that mktime uses month from 1 to 12 while to_tm + * uses 0 to 11. + */ +static unsigned long indy_rtc_get_time(void) +{ + unsigned int yrs, mon, day, hrs, min, sec; + unsigned int save_control; + + save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff; + hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE; + + sec = BCD2BIN(hpc3c0->rtcregs[RTC_SECONDS] & 0xff); + min = BCD2BIN(hpc3c0->rtcregs[RTC_MINUTES] & 0xff); + hrs = BCD2BIN(hpc3c0->rtcregs[RTC_HOURS] & 0x1f); + day = BCD2BIN(hpc3c0->rtcregs[RTC_DATE] & 0xff); + mon = BCD2BIN(hpc3c0->rtcregs[RTC_MONTH] & 0x1f); + yrs = BCD2BIN(hpc3c0->rtcregs[RTC_YEAR] & 0xff); + + hpc3c0->rtcregs[RTC_CMD] = save_control; + + if (yrs < 45) + yrs += 30; + if ((yrs += 40) < 70) + yrs += 100; + + return mktime(yrs + 1900, mon, day, hrs, min, sec); +} + +static int indy_rtc_set_time(unsigned long tim) +{ + struct rtc_time tm; + unsigned int save_control; + + to_tm(tim, &tm); + + tm.tm_mon += 1; /* tm_mon starts at zero */ + tm.tm_year -= 1940; + if (tm.tm_year >= 100) + tm.tm_year -= 100; + + save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff; + hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE; + + hpc3c0->rtcregs[RTC_YEAR] = BIN2BCD(tm.tm_sec); + hpc3c0->rtcregs[RTC_MONTH] = BIN2BCD(tm.tm_mon); + hpc3c0->rtcregs[RTC_DATE] = BIN2BCD(tm.tm_mday); + hpc3c0->rtcregs[RTC_HOURS] = BIN2BCD(tm.tm_hour); + hpc3c0->rtcregs[RTC_MINUTES] = BIN2BCD(tm.tm_min); + hpc3c0->rtcregs[RTC_SECONDS] = BIN2BCD(tm.tm_sec); + hpc3c0->rtcregs[RTC_HUNDREDTH_SECOND] = 0; + + hpc3c0->rtcregs[RTC_CMD] = save_control; + + return 0; +} + +static unsigned long dosample(void) +{ + u32 ct0, ct1; + volatile u8 msb, lsb; + + /* Start the counter. */ + sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | + SGINT_TCWORD_MRGEN); + sgint->tcnt2 = (SGINT_TCSAMP_COUNTER & 0xff); + sgint->tcnt2 = (SGINT_TCSAMP_COUNTER >> 8); + + /* Get initial counter invariant */ + ct0 = read_c0_count(); + + /* Latch and spin until top byte of counter2 is zero */ + do { + sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT); + lsb = sgint->tcnt2; + msb = sgint->tcnt2; + ct1 = read_c0_count(); + } while (msb); + + /* Stop the counter. */ + sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | + SGINT_TCWORD_MSWST); + /* + * Return the difference, this is how far the r4k counter increments + * for every 1/HZ seconds. We round off the nearest 1 MHz of master + * clock (= 1000000 / 100 / 2 = 5000 count). + */ + return ((ct1 - ct0) / 5000) * 5000; +} + +/* + * Here we need to calibrate the cycle counter to at least be close. + */ +static __init void indy_time_init(void) +{ + unsigned long r4k_ticks[3]; + unsigned long r4k_tick; + + /* + * Figure out the r4k offset, the algorithm is very simple + * and works in _all_ cases as long as the 8254 counter + * register itself works ok (as an interrupt driving timer + * it does not because of bug, this is why we are using + * the onchip r4k counter/compare register to serve this + * purpose, but for r4k_offset calculation it will work + * ok for us). There are other very complicated ways + * of performing this calculation but this one works just + * fine so I am not going to futz around. ;-) + */ + printk(KERN_INFO "Calibrating system timer... "); + dosample(); /* Prime cache. */ + dosample(); /* Prime cache. */ + /* Zero is NOT an option. */ + do { + r4k_ticks[0] = dosample(); + } while (!r4k_ticks[0]); + do { + r4k_ticks[1] = dosample(); + } while (!r4k_ticks[1]); + + if (r4k_ticks[0] != r4k_ticks[1]) { + printk("warning: timer counts differ, retrying... "); + r4k_ticks[2] = dosample(); + if (r4k_ticks[2] == r4k_ticks[0] + || r4k_ticks[2] == r4k_ticks[1]) + r4k_tick = r4k_ticks[2]; + else { + printk("disagreement, using average... "); + r4k_tick = (r4k_ticks[0] + r4k_ticks[1] + + r4k_ticks[2]) / 3; + } + } else + r4k_tick = r4k_ticks[0]; + + printk("%d [%d.%02d MHz CPU]\n", (int) r4k_tick, + (int) (r4k_tick / 5000), (int) (r4k_tick % 5000) / 50); + + mips_counter_frequency = r4k_tick * HZ; +} + +/* Generic SGI handler for (spurious) 8254 interrupts */ +void indy_8254timer_irq(struct pt_regs *regs) +{ + int cpu = smp_processor_id(); + int irq = SGI_8254_0_IRQ; + ULONG cnt; + char c; + + irq_enter(); + kstat_cpu(cpu).irqs[irq]++; + printk(KERN_ALERT "Oops, got 8254 interrupt.\n"); + ArcRead(0, &c, 1, &cnt); + ArcEnterInteractiveMode(); + irq_exit(); +} + +void indy_r4k_timer_interrupt(struct pt_regs *regs) +{ + int cpu = smp_processor_id(); + int irq = SGI_TIMER_IRQ; + + irq_enter(); + kstat_cpu(cpu).irqs[irq]++; + timer_interrupt(irq, NULL, regs); + irq_exit(); + + if (softirq_pending(cpu)) + do_softirq(); +} + +extern int setup_irq(unsigned int irq, struct irqaction *irqaction); + +static void indy_timer_setup(struct irqaction *irq) +{ + /* over-write the handler, we use our own way */ + irq->handler = no_action; + + /* setup irqaction */ + setup_irq(SGI_TIMER_IRQ, irq); +} + +void __init ip22_time_init(void) +{ + /* setup hookup functions */ + rtc_get_time = indy_rtc_get_time; + rtc_set_time = indy_rtc_set_time; + + board_time_init = indy_time_init; + board_timer_setup = indy_timer_setup; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip22/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,12 @@ +# +# Makefile for the SGI specific kernel interface routines +# under Linux. +# + +obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-irq.o ip22-berr.o \ + ip22-time.o ip22-rtc.o ip22-nvram.o ip22-reset.o \ + ip22-setup.o ip22-ksyms.o + +obj-$(CONFIG_EISA) += ip22-eisa.o + +EXTRA_AFLAGS := $(CFLAGS) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip27/ip27-berr.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,94 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1999, 2000 by Ralf Baechle + * Copyright (C) 1999, 2000 by Silicon Graphics + * Copyright (C) 2002 Maciej W. Rozycki + */ +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +extern void dump_tlb_addr(unsigned long addr); +extern void dump_tlb_all(void); + +static void dump_hub_information(unsigned long errst0, unsigned long errst1) +{ + static char *err_type[2][8] = { + { NULL, "Uncached Partial Read PRERR", "DERR", "Read Timeout", + NULL, NULL, NULL, NULL }, + { "WERR", "Uncached Partial Write", "PWERR", "Write Timeout", + NULL, NULL, NULL, NULL } + }; + int wrb = errst1 & PI_ERR_ST1_WRBRRB_MASK; + + if (!(errst0 & PI_ERR_ST0_VALID_MASK)) { + printk("Hub does not contain valid error information\n"); + return; + } + + + printk("Hub has valid error information:\n"); + if (errst0 & PI_ERR_ST0_OVERRUN_MASK) + printk("Overrun is set. Error stack may contain additional " + "information.\n"); + printk("Hub error address is %08lx\n", + (errst0 & PI_ERR_ST0_ADDR_MASK) >> (PI_ERR_ST0_ADDR_SHFT - 3)); + printk("Incoming message command 0x%lx\n", + (errst0 & PI_ERR_ST0_CMD_MASK) >> PI_ERR_ST0_CMD_SHFT); + printk("Supplemental field of incoming message is 0x%lx\n", + (errst0 & PI_ERR_ST0_SUPPL_MASK) >> PI_ERR_ST0_SUPPL_SHFT); + printk("T5 Rn (for RRB only) is 0x%lx\n", + (errst0 & PI_ERR_ST0_REQNUM_MASK) >> PI_ERR_ST0_REQNUM_SHFT); + printk("Error type is %s\n", err_type[wrb] + [(errst0 & PI_ERR_ST0_TYPE_MASK) >> PI_ERR_ST0_TYPE_SHFT] + ? : "invalid"); +} + +int ip27_be_handler(struct pt_regs *regs, int is_fixup) +{ + unsigned long errst0, errst1; + int data = regs->cp0_cause & 4; + int cpu = LOCAL_HUB_L(PI_CPU_NUM); + + if (is_fixup) + return MIPS_BE_FIXUP; + + printk("Slice %c got %cbe at 0x%lx\n", 'A' + cpu, data ? 'd' : 'i', + regs->cp0_epc); + printk("Hub information:\n"); + printk("ERR_INT_PEND = 0x%06lx\n", LOCAL_HUB_L(PI_ERR_INT_PEND)); + errst0 = LOCAL_HUB_L(cpu ? PI_ERR_STATUS0_B : PI_ERR_STATUS0_A); + errst1 = LOCAL_HUB_L(cpu ? PI_ERR_STATUS1_B : PI_ERR_STATUS1_A); + dump_hub_information(errst0, errst1); + show_regs(regs); + dump_tlb_all(); + while(1); + force_sig(SIGBUS, current); +} + +void __init ip27_be_init(void) +{ + /* XXX Initialize all the Hub & Bridge error handling here. */ + int cpu = LOCAL_HUB_L(PI_CPU_NUM); + int cpuoff = cpu << 8; + + board_be_handler = ip27_be_handler; + + LOCAL_HUB_S(PI_ERR_INT_PEND, + cpu ? PI_ERR_CLEAR_ALL_B : PI_ERR_CLEAR_ALL_A); + LOCAL_HUB_S(PI_ERR_INT_MASK_A + cpuoff, 0); + LOCAL_HUB_S(PI_ERR_STACK_ADDR_A + cpuoff, 0); + LOCAL_HUB_S(PI_ERR_STACK_SIZE, 0); /* Disable error stack */ + LOCAL_HUB_S(PI_SYSAD_ERRCHK_EN, PI_SYSAD_CHECK_ALL); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip27/ip27-console.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,65 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2001, 2002 Ralf Baechle + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IOC3_BAUD (22000000 / (3*16)) +#define IOC3_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) + +static inline struct ioc3_uartregs *console_uart(void) +{ + struct ioc3 *ioc3; + + ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(get_nasid())->memory_base; + + return &ioc3->sregs.uarta; +} + +void prom_putchar(char c) +{ + struct ioc3_uartregs *uart = console_uart(); + + while ((uart->iu_lsr & 0x20) == 0); + uart->iu_thr = c; +} + +char __init prom_getchar(void) +{ + return 0; +} + +static void inline ioc3_console_probe(void) +{ + struct serial_struct req; + + /* Register to interrupt zero because we share the interrupt with + the serial driver which we don't properly support yet. */ + memset(&req, 0, sizeof(req)); + req.irq = 0; + req.flags = IOC3_COM_FLAGS; + req.io_type = SERIAL_IO_MEM; + req.iomem_reg_shift = 0; + req.baud_base = IOC3_BAUD; + + req.iomem_base = (unsigned char *) console_uart(); + register_serial(&req); +} + +__init void ip27_setup_console(void) +{ + ioc3_console_probe(); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip27/ip27-init.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,821 @@ +/* + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file "COPYING" in the main directory of this + * archive for more details. + * + * Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com) + * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc. + */ + +#include +#include +#include +#include +#include /* for numnodes */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CPU_NONE (cpuid_t)-1 + +/* + * The following should work till 64 nodes, ie 128p SN0s. + */ +#define CNODEMASK_CLRALL(p) (p) = 0 +#define CNODEMASK_TSTB(p, bit) ((p) & (1ULL << (bit))) +#define CNODEMASK_SETB(p, bit) ((p) |= 1ULL << (bit)) + +cpumask_t boot_cpumask; +hubreg_t region_mask; +static int fine_mode; +int maxcpus; +static spinlock_t hub_mask_lock = SPIN_LOCK_UNLOCKED; +static cnodemask_t hub_init_mask; +static atomic_t numstarted = ATOMIC_INIT(1); +static int router_distance; +nasid_t master_nasid = INVALID_NASID; + +cnodeid_t nasid_to_compact_node[MAX_NASIDS]; +nasid_t compact_to_nasid_node[MAX_COMPACT_NODES]; +cnodeid_t cpuid_to_compact_node[MAXCPUS]; +char node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES]; + +hubreg_t get_region(cnodeid_t cnode) +{ + if (fine_mode) + return COMPACT_TO_NASID_NODEID(cnode) >> NASID_TO_FINEREG_SHFT; + else + return COMPACT_TO_NASID_NODEID(cnode) >> NASID_TO_COARSEREG_SHFT; +} + +static void gen_region_mask(hubreg_t *region_mask, int maxnodes) +{ + cnodeid_t cnode; + + (*region_mask) = 0; + for (cnode = 0; cnode < maxnodes; cnode++) { + (*region_mask) |= 1ULL << get_region(cnode); + } +} + +int is_fine_dirmode(void) +{ + return (((LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_REGIONSIZE_MASK) + >> NSRI_REGIONSIZE_SHFT) & REGIONSIZE_FINE); +} + +nasid_t get_actual_nasid(lboard_t *brd) +{ + klhub_t *hub; + + if (!brd) + return INVALID_NASID; + + /* find out if we are a completely disabled brd. */ + hub = (klhub_t *)find_first_component(brd, KLSTRUCT_HUB); + if (!hub) + return INVALID_NASID; + if (!(hub->hub_info.flags & KLINFO_ENABLE)) /* disabled node brd */ + return hub->hub_info.physid; + else + return brd->brd_nasid; +} + +/* Tweak this for maximum number of CPUs to activate */ +static int max_cpus = NR_CPUS; + +int do_cpumask(cnodeid_t cnode, nasid_t nasid, cpumask_t *boot_cpumask, + int *highest) +{ + static int tot_cpus_found = 0; + lboard_t *brd; + klcpu_t *acpu; + int cpus_found = 0; + cpuid_t cpuid; + + brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IP27); + + do { + acpu = (klcpu_t *)find_first_component(brd, KLSTRUCT_CPU); + while (acpu) { + cpuid = acpu->cpu_info.virtid; + /* cnode is not valid for completely disabled brds */ + if (get_actual_nasid(brd) == brd->brd_nasid) + cpuid_to_compact_node[cpuid] = cnode; + if (cpuid > *highest) + *highest = cpuid; + /* Only let it join in if it's marked enabled */ + if ((acpu->cpu_info.flags & KLINFO_ENABLE) && + (tot_cpus_found != max_cpus)) { + CPUMASK_SETB(*boot_cpumask, cpuid); + cpus_found++; + tot_cpus_found++; + } + acpu = (klcpu_t *)find_component(brd, (klinfo_t *)acpu, + KLSTRUCT_CPU); + } + brd = KLCF_NEXT(brd); + if (brd) + brd = find_lboard(brd,KLTYPE_IP27); + else + break; + } while (brd); + + return cpus_found; +} + +cpuid_t cpu_node_probe(cpumask_t *boot_cpumask, int *numnodes) +{ + int i, cpus = 0, highest = 0; + gda_t *gdap = GDA; + nasid_t nasid; + + /* + * Initialize the arrays to invalid nodeid (-1) + */ + for (i = 0; i < MAX_COMPACT_NODES; i++) + compact_to_nasid_node[i] = INVALID_NASID; + for (i = 0; i < MAX_NASIDS; i++) + nasid_to_compact_node[i] = INVALID_CNODEID; + for (i = 0; i < MAXCPUS; i++) + cpuid_to_compact_node[i] = INVALID_CNODEID; + + *numnodes = 0; + for (i = 0; i < MAX_COMPACT_NODES; i++) { + if ((nasid = gdap->g_nasidtable[i]) == INVALID_NASID) { + break; + } else { + compact_to_nasid_node[i] = nasid; + nasid_to_compact_node[nasid] = i; + (*numnodes)++; + cpus += do_cpumask(i, nasid, boot_cpumask, &highest); + } + } + + /* + * Cpus are numbered in order of cnodes. Currently, disabled + * cpus are not numbered. + */ + + return highest + 1; +} + +int cpu_enabled(cpuid_t cpu) +{ + if (cpu == CPU_NONE) + return 0; + return CPUMASK_TSTB(boot_cpumask, cpu) != 0; +} + +void mlreset(void) +{ + int i; + void init_topology_matrix(void); + void dump_topology(void); + + + master_nasid = get_nasid(); + fine_mode = is_fine_dirmode(); + + /* + * Probe for all CPUs - this creates the cpumask and + * sets up the mapping tables. + */ + CPUMASK_CLRALL(boot_cpumask); + maxcpus = cpu_node_probe(&boot_cpumask, &numnodes); + printk("Discovered %d cpus on %d nodes\n", maxcpus, numnodes); + + init_topology_matrix(); + dump_topology(); + + gen_region_mask(®ion_mask, numnodes); + CNODEMASK_CLRALL(hub_init_mask); + + setup_replication_mask(numnodes); + + /* + * Set all nodes' calias sizes to 8k + */ + for (i = 0; i < numnodes; i++) { + nasid_t nasid; + + nasid = COMPACT_TO_NASID_NODEID(i); + + /* + * Always have node 0 in the region mask, otherwise + * CALIAS accesses get exceptions since the hub + * thinks it is a node 0 address. + */ + REMOTE_HUB_S(nasid, PI_REGION_PRESENT, (region_mask | 1)); +#ifdef CONFIG_REPLICATE_EXHANDLERS + REMOTE_HUB_S(nasid, PI_CALIAS_SIZE, PI_CALIAS_SIZE_8K); +#else + REMOTE_HUB_S(nasid, PI_CALIAS_SIZE, PI_CALIAS_SIZE_0); +#endif + +#ifdef LATER + /* + * Set up all hubs to have a big window pointing at + * widget 0. Memory mode, widget 0, offset 0 + */ + REMOTE_HUB_S(nasid, IIO_ITTE(SWIN0_BIGWIN), + ((HUB_PIO_MAP_TO_MEM << IIO_ITTE_IOSP_SHIFT) | + (0 << IIO_ITTE_WIDGET_SHIFT))); +#endif + } +} + + +void intr_clear_bits(nasid_t nasid, volatile hubreg_t *pend, int base_level, + char *name) +{ + volatile hubreg_t bits; + int i; + + /* Check pending interrupts */ + if ((bits = HUB_L(pend)) != 0) + for (i = 0; i < N_INTPEND_BITS; i++) + if (bits & (1 << i)) + LOCAL_HUB_CLR_INTR(base_level + i); +} + +void intr_clear_all(nasid_t nasid) +{ + REMOTE_HUB_S(nasid, PI_INT_MASK0_A, 0); + REMOTE_HUB_S(nasid, PI_INT_MASK0_B, 0); + REMOTE_HUB_S(nasid, PI_INT_MASK1_A, 0); + REMOTE_HUB_S(nasid, PI_INT_MASK1_B, 0); + intr_clear_bits(nasid, REMOTE_HUB_ADDR(nasid, PI_INT_PEND0), + INT_PEND0_BASELVL, "INT_PEND0"); + intr_clear_bits(nasid, REMOTE_HUB_ADDR(nasid, PI_INT_PEND1), + INT_PEND1_BASELVL, "INT_PEND1"); +} + +void sn_mp_setup(void) +{ + cnodeid_t cnode; +#if 0 + cpuid_t cpu; +#endif + + for (cnode = 0; cnode < numnodes; cnode++) { +#if 0 + init_platform_nodepda(); +#endif + intr_clear_all(COMPACT_TO_NASID_NODEID(cnode)); + } +#if 0 + for (cpu = 0; cpu < maxcpus; cpu++) { + init_platform_pda(); + } +#endif +} + +void per_hub_init(cnodeid_t cnode) +{ + extern void pcibr_setup(cnodeid_t); + cnodemask_t done; + nasid_t nasid; + + nasid = COMPACT_TO_NASID_NODEID(cnode); + + spin_lock(&hub_mask_lock); + /* Test our bit. */ + if (!(done = CNODEMASK_TSTB(hub_init_mask, cnode))) { + /* Turn our bit on in the mask. */ + CNODEMASK_SETB(hub_init_mask, cnode); + /* + * Do the actual initialization if it hasn't been done yet. + * We don't need to hold a lock for this work. + */ + /* + * Set CRB timeout at 5ms, (< PI timeout of 10ms) + */ + REMOTE_HUB_S(nasid, IIO_ICTP, 0x800); + REMOTE_HUB_S(nasid, IIO_ICTO, 0xff); + hub_rtc_init(cnode); + pcibr_setup(cnode); +#ifdef CONFIG_REPLICATE_EXHANDLERS + /* + * If this is not a headless node initialization, + * copy over the caliased exception handlers. + */ + if (get_compact_nodeid() == cnode) { + extern char except_vec0, except_vec1_r10k; + extern char except_vec2_generic, except_vec3_generic; + + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, + 0x80); + memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, + 0x80); + memcpy((void *)KSEG0, &except_vec0, 0x80); + memcpy((void *)KSEG0 + 0x080, &except_vec1_r10k, 0x80); + memcpy((void *)(KSEG0 + 0x100), (void *) KSEG0, 0x80); + memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, + 0x100); + __flush_cache_all(); + } +#endif + } + spin_unlock(&hub_mask_lock); +} + +/* + * This is similar to hard_smp_processor_id(). + */ +cpuid_t getcpuid(void) +{ + klcpu_t *klcpu; + + klcpu = nasid_slice_to_cpuinfo(get_nasid(),LOCAL_HUB_L(PI_CPU_NUM)); + return klcpu->cpu_info.virtid; +} + +void per_cpu_init(void) +{ + extern void install_cpu_nmi_handler(int slice); + extern void load_mmu(void); + static int is_slave = 0; + int cpu = smp_processor_id(); + cnodeid_t cnode = get_compact_nodeid(); + + TLBMISS_HANDLER_SETUP(); +#if 0 + intr_init(); +#endif + clear_c0_status(ST0_IM); + per_hub_init(cnode); + cpu_time_init(); + if (smp_processor_id()) /* master can't do this early, no kmalloc */ + install_cpuintr(cpu); + /* Install our NMI handler if symmon hasn't installed one. */ + install_cpu_nmi_handler(cputoslice(cpu)); +#if 0 + install_tlbintr(cpu); +#endif + set_c0_status(SRB_DEV0 | SRB_DEV1); + if (is_slave) { + clear_c0_status(ST0_BEV); + if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) + set_c0_status(ST0_XX); + set_c0_status(ST0_KX|ST0_SX|ST0_UX); + local_irq_enable(); + load_mmu(); + atomic_inc(&numstarted); + } else { + is_slave = 1; + } +} + +cnodeid_t get_compact_nodeid(void) +{ + nasid_t nasid; + + nasid = get_nasid(); + /* + * Map the physical node id to a virtual node id (virtual node ids + * are contiguous). + */ + return NASID_TO_COMPACT_NODEID(nasid); +} + +#ifdef CONFIG_SMP + +/* + * Takes as first input the PROM assigned cpu id, and the kernel + * assigned cpu id as the second. + */ +static void alloc_cpupda(cpuid_t cpu, int cpunum) +{ + cnodeid_t node; + nasid_t nasid; + + node = get_cpu_cnode(cpu); + nasid = COMPACT_TO_NASID_NODEID(node); + + cputonasid(cpunum) = nasid; + cputocnode(cpunum) = node; + cputoslice(cpunum) = get_cpu_slice(cpu); + cpu_data[cpunum].p_cpuid = cpu; +} + +static struct task_struct * __init fork_by_hand(void) +{ + struct pt_regs regs; + /* + * don't care about the eip and regs settings since + * we'll never reschedule the forked task. + */ + return copy_process(CLONE_VM|CLONE_IDLETASK, 0, ®s, 0, NULL, NULL); +} + +static int __init do_boot_cpu(int cpu, int num_cpus) +{ + extern void smp_bootstrap(void); + cpuid_t mycpuid = getcpuid(); + struct task_struct *idle; + + if (cpu == mycpuid) { + alloc_cpupda(cpu, num_cpus); + return 1; + } + + /* Skip holes in CPU space */ + if (!CPUMASK_TSTB(boot_cpumask, cpu)) + return 0; + + /* + * The following code is purely to make sure + * Linux can schedule processes on this slave. + */ + idle = fork_by_hand(); + if (IS_ERR(idle)) + panic("failed fork for CPU %d", cpu); + + /* + * We remove it from the pidhash and the runqueue + * once we got the process: + */ + init_idle(idle, cpu); + + alloc_cpupda(cpu, num_cpus); + + unhash_process(idle); + + /* + * Launch a slave into smp_bootstrap(). It doesn't take an + * argument, and we set sp to the kernel stack of the newly + * created idle process, gp to the proc struct so that + * current_thread_info() will work. + */ + LAUNCH_SLAVE(cputonasid(num_cpus),cputoslice(num_cpus), + (launch_proc_t)MAPPED_KERN_RW_TO_K0(smp_bootstrap), + 0, (void *)((unsigned long)idle->thread_info + + KERNEL_STACK_SIZE - 32), (void *)idle); + + /* + * Now optimistically set the mapping arrays. We + * need to wait here, verify the cpu booted up, then + * fire up the next cpu. + */ + __cpu_number_map[cpu] = num_cpus; + __cpu_logical_map[num_cpus] = cpu; + CPUMASK_SETB(cpu_online_map, cpu); + + /* + * Wait this cpu to start up and initialize its hub, + * and discover the io devices it will control. + * + * XXX: We really want to fire up launch all the CPUs + * at once. We have to preserve the order of the + * devices on the bridges first though. + */ + while (atomic_read(&numstarted) != num_cpus); + + return 1; +} + +void __init smp_boot_cpus(void) +{ + int num_cpus = 0; + cpuid_t cpu; + cnodeid_t cnode; + + init_new_context(current, &init_mm); + current_thread_info()->cpu = 0; + smp_tune_scheduling(); + + sn_mp_setup(); + /* Master has already done per_cpu_init() */ + install_cpuintr(smp_processor_id()); +#if 0 + bte_lateinit(); + ecc_init(); +#endif + + replicate_kernel_text(numnodes); + /* Launch slaves. */ + for (cpu = 0; cpu < maxcpus; cpu++) { + num_cpus += do_boot_cpu(cpu, num_cpus); + } + +#ifdef LATER + Wait logic goes here. +#endif + for (cnode = 0; cnode < numnodes; cnode++) { +#if 0 + if (cnodetocpu(cnode) == -1) { + printk("Initializing headless hub,cnode %d", cnode); + per_hub_init(cnode); + } +#endif + } +#if 0 + cpu_io_setup(); + init_mfhi_war(); +#endif +} + +#else /* CONFIG_SMP */ +void __init start_secondary(void) +{ + /* XXX Why do we need this empty definition at all? */ +} +#endif /* CONFIG_SMP */ + + +#define rou_rflag rou_flags + +void router_recurse(klrou_t *router_a, klrou_t *router_b, int depth) +{ + klrou_t *router; + lboard_t *brd; + int port; + + if (router_a->rou_rflag == 1) + return; + + if (depth >= router_distance) + return; + + router_a->rou_rflag = 1; + + for (port = 1; port <= MAX_ROUTER_PORTS; port++) { + if (router_a->rou_port[port].port_nasid == INVALID_NASID) + continue; + + brd = (lboard_t *)NODE_OFFSET_TO_K0( + router_a->rou_port[port].port_nasid, + router_a->rou_port[port].port_offset); + + if (brd->brd_type == KLTYPE_ROUTER) { + router = (klrou_t *)NODE_OFFSET_TO_K0(NASID_GET(brd), brd->brd_compts[0]); + if (router == router_b) { + if (depth < router_distance) + router_distance = depth; + } + else + router_recurse(router, router_b, depth + 1); + } + } + + router_a->rou_rflag = 0; +} + +int node_distance(nasid_t nasid_a, nasid_t nasid_b) +{ + nasid_t nasid; + cnodeid_t cnode; + lboard_t *brd, *dest_brd; + int port; + klrou_t *router, *router_a = NULL, *router_b = NULL; + + /* Figure out which routers nodes in question are connected to */ + for (cnode = 0; cnode < numnodes; cnode++) { + nasid = COMPACT_TO_NASID_NODEID(cnode); + + if (nasid == -1) continue; + + brd = find_lboard_class((lboard_t *)KL_CONFIG_INFO(nasid), + KLTYPE_ROUTER); + + if (!brd) + continue; + + do { + if (brd->brd_flags & DUPLICATE_BOARD) + continue; + + router = (klrou_t *)NODE_OFFSET_TO_K0(NASID_GET(brd), brd->brd_compts[0]); + router->rou_rflag = 0; + + for (port = 1; port <= MAX_ROUTER_PORTS; port++) { + if (router->rou_port[port].port_nasid == INVALID_NASID) + continue; + + dest_brd = (lboard_t *)NODE_OFFSET_TO_K0( + router->rou_port[port].port_nasid, + router->rou_port[port].port_offset); + + if (dest_brd->brd_type == KLTYPE_IP27) { + if (dest_brd->brd_nasid == nasid_a) + router_a = router; + if (dest_brd->brd_nasid == nasid_b) + router_b = router; + } + } + + } while ( (brd = find_lboard_class(KLCF_NEXT(brd), KLTYPE_ROUTER)) ); + } + + if (router_a == NULL) { + printk("node_distance: router_a NULL\n"); + return -1; + } + if (router_b == NULL) { + printk("node_distance: router_b NULL\n"); + return -1; + } + + if (nasid_a == nasid_b) + return 0; + + if (router_a == router_b) + return 1; + + router_distance = 100; + router_recurse(router_a, router_b, 2); + + return router_distance; +} + +void init_topology_matrix(void) +{ + nasid_t nasid, nasid2; + cnodeid_t row, col; + + for (row = 0; row < MAX_COMPACT_NODES; row++) + for (col = 0; col < MAX_COMPACT_NODES; col++) + node_distances[row][col] = -1; + + for (row = 0; row < numnodes; row++) { + nasid = COMPACT_TO_NASID_NODEID(row); + for (col = 0; col < numnodes; col++) { + nasid2 = COMPACT_TO_NASID_NODEID(col); + node_distances[row][col] = node_distance(nasid, nasid2); + } + } +} + +void dump_topology(void) +{ + nasid_t nasid; + cnodeid_t cnode; + lboard_t *brd, *dest_brd; + int port; + int router_num = 0; + klrou_t *router; + cnodeid_t row, col; + + printk("************** Topology ********************\n"); + + printk(" "); + for (col = 0; col < numnodes; col++) + printk("%02d ", col); + printk("\n"); + for (row = 0; row < numnodes; row++) { + printk("%02d ", row); + for (col = 0; col < numnodes; col++) + printk("%2d ", node_distances[row][col]); + printk("\n"); + } + + for (cnode = 0; cnode < numnodes; cnode++) { + nasid = COMPACT_TO_NASID_NODEID(cnode); + + if (nasid == -1) continue; + + brd = find_lboard_class((lboard_t *)KL_CONFIG_INFO(nasid), + KLTYPE_ROUTER); + + if (!brd) + continue; + + do { + if (brd->brd_flags & DUPLICATE_BOARD) + continue; + printk("Router %d:", router_num); + router_num++; + + router = (klrou_t *)NODE_OFFSET_TO_K0(NASID_GET(brd), brd->brd_compts[0]); + + for (port = 1; port <= MAX_ROUTER_PORTS; port++) { + if (router->rou_port[port].port_nasid == INVALID_NASID) + continue; + + dest_brd = (lboard_t *)NODE_OFFSET_TO_K0( + router->rou_port[port].port_nasid, + router->rou_port[port].port_offset); + + if (dest_brd->brd_type == KLTYPE_IP27) + printk(" %d", dest_brd->brd_nasid); + if (dest_brd->brd_type == KLTYPE_ROUTER) + printk(" r"); + } + printk("\n"); + + } while ( (brd = find_lboard_class(KLCF_NEXT(brd), KLTYPE_ROUTER)) ); + } +} + +#if 0 +#define brd_widgetnum brd_slot +#define NODE_OFFSET_TO_KLINFO(n,off) ((klinfo_t*) TO_NODE_CAC(n,off)) +void +dump_klcfg(void) +{ + cnodeid_t cnode; + int i; + nasid_t nasid; + lboard_t *lbptr; + gda_t *gdap; + + gdap = (gda_t *)GDA_ADDR(get_nasid()); + if (gdap->g_magic != GDA_MAGIC) { + printk("dumpklcfg_cmd: Invalid GDA MAGIC\n"); + return; + } + + for (cnode = 0; cnode < MAX_COMPACT_NODES; cnode ++) { + nasid = gdap->g_nasidtable[cnode]; + + if (nasid == INVALID_NASID) + continue; + + printk("\nDumpping klconfig Nasid %d:\n", nasid); + + lbptr = KL_CONFIG_INFO(nasid); + + while (lbptr) { + printk(" %s, Nasid %d, Module %d, widget 0x%x, partition %d, NIC 0x%x lboard 0x%lx", + "board name here", /* BOARD_NAME(lbptr->brd_type), */ + lbptr->brd_nasid, lbptr->brd_module, + lbptr->brd_widgetnum, + lbptr->brd_partition, + (lbptr->brd_nic), lbptr); + if (lbptr->brd_flags & DUPLICATE_BOARD) + printk(" -D"); + printk("\n"); + for (i = 0; i < lbptr->brd_numcompts; i++) { + klinfo_t *kli; + kli = NODE_OFFSET_TO_KLINFO(NASID_GET(lbptr), lbptr->brd_compts[i]); + printk(" type %2d, flags 0x%04x, diagval %3d, physid %4d, virtid %2d: %s\n", + kli->struct_type, + kli->flags, + kli->diagval, + kli->physid, + kli->virtid, + "comp. name here"); + /* COMPONENT_NAME(kli->struct_type)); */ + } + lbptr = KLCF_NEXT(lbptr); + } + } + printk("\n"); + + /* Useful to print router maps also */ + + for (cnode = 0; cnode < MAX_COMPACT_NODES; cnode ++) { + klrou_t *kr; + int i; + + nasid = gdap->g_nasidtable[cnode]; + if (nasid == INVALID_NASID) + continue; + lbptr = KL_CONFIG_INFO(nasid); + + while (lbptr) { + + lbptr = find_lboard_class(lbptr, KLCLASS_ROUTER); + if(!lbptr) + break; + if (!KL_CONFIG_DUPLICATE_BOARD(lbptr)) { + printk("%llx -> \n", lbptr->brd_nic); + kr = (klrou_t *)find_first_component(lbptr, + KLSTRUCT_ROU); + for (i = 1; i <= MAX_ROUTER_PORTS; i++) { + printk("[%d, %llx]; ", + kr->rou_port[i].port_nasid, + kr->rou_port[i].port_offset); + } + printk("\n"); + } + lbptr = KLCF_NEXT(lbptr); + } + printk("\n"); + } + + dump_topology(); +} +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip27/ip27-irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,488 @@ +/* + * ip27-irq.c: Highlevel interrupt handling for IP27 architecture. + * + * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 1999 - 2001 Kanoj Sarcar + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#undef DEBUG_IRQ +#ifdef DEBUG_IRQ +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +/* These should die */ +unsigned char bus_to_wid[256]; /* widget id for linux pci bus */ +unsigned char bus_to_nid[256]; /* nasid for linux pci bus */ +unsigned char num_bridges; /* number of bridges in the system */ + +/* + * Linux has a controller-independent x86 interrupt architecture. + * every controller has a 'controller-template', that is used + * by the main code to do the right thing. Each driver-visible + * interrupt source is transparently wired to the apropriate + * controller. Thus drivers need not be aware of the + * interrupt-controller. + * + * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC, + * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC. + * (IO-APICs assumed to be messaging to Pentium local-APICs) + * + * the code is designed to be easily extended with new/different + * interrupt controllers, without having to do assembly magic. + */ + +extern asmlinkage void ip27_irq(void); + +extern int irq_to_bus[], irq_to_slot[], bus_to_cpu[]; +int intr_connect_level(int cpu, int bit); +int intr_disconnect_level(int cpu, int bit); + +/* + * There is a single intpend register per node, and we want to have + * distinct levels for intercpu intrs for both cpus A and B on a node. + */ +int node_level_to_irq[MAX_COMPACT_NODES][PERNODE_LEVELS]; + +/* + * use these macros to get the encoded nasid and widget id + * from the irq value + */ +#define IRQ_TO_BUS(i) irq_to_bus[(i)] +#define IRQ_TO_CPU(i) bus_to_cpu[IRQ_TO_BUS(i)] +#define NASID_FROM_PCI_IRQ(i) bus_to_nid[IRQ_TO_BUS(i)] +#define WID_FROM_PCI_IRQ(i) bus_to_wid[IRQ_TO_BUS(i)] +#define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i] + +static inline int alloc_level(cpuid_t cpunum, int irq) +{ + cnodeid_t nodenum = CPUID_TO_COMPACT_NODEID(cpunum); + int j = LEAST_LEVEL + 3; /* resched & crosscall entries taken */ + + while (++j < PERNODE_LEVELS) { + if (node_level_to_irq[nodenum][j] == -1) { + node_level_to_irq[nodenum][j] = irq; + return j; + } + } + printk("Cpu %ld flooded with devices\n", cpunum); + while(1); + return -1; +} + +static inline int find_level(cpuid_t *cpunum, int irq) +{ + int j; + cnodeid_t nodenum = INVALID_CNODEID; + + while (++nodenum < MAX_COMPACT_NODES) { + j = LEAST_LEVEL + 3; /* resched & crosscall entries taken */ + while (++j < PERNODE_LEVELS) + if (node_level_to_irq[nodenum][j] == irq) { + *cpunum = 0; /* XXX Fixme */ + return(j); + } + } + printk("Could not identify cpu/level for irq %d\n", irq); + while(1); + return(-1); +} + +/* + * Find first bit set + */ +static int ms1bit(unsigned long x) +{ + int b = 0, s; + + s = 16; if (x >> 16 == 0) s = 0; b += s; x >>= s; + s = 8; if (x >> 8 == 0) s = 0; b += s; x >>= s; + s = 4; if (x >> 4 == 0) s = 0; b += s; x >>= s; + s = 2; if (x >> 2 == 0) s = 0; b += s; x >>= s; + s = 1; if (x >> 1 == 0) s = 0; b += s; + + return b; +} + +/* + * This code is unnecessarily complex, because we do SA_INTERRUPT + * intr enabling. Basically, once we grab the set of intrs we need + * to service, we must mask _all_ these interrupts; firstly, to make + * sure the same intr does not intr again, causing recursion that + * can lead to stack overflow. Secondly, we can not just mask the + * one intr we are do_IRQing, because the non-masked intrs in the + * first set might intr again, causing multiple servicings of the + * same intr. This effect is mostly seen for intercpu intrs. + * Kanoj 05.13.00 + */ +void ip27_do_irq(struct pt_regs *regs) +{ + int irq, swlevel; + hubreg_t pend0, mask0; + cpuid_t thiscpu = smp_processor_id(); + int pi_int_mask0 = ((cputoslice(thiscpu) == 0) ? + PI_INT_MASK0_A : PI_INT_MASK0_B); + + /* copied from Irix intpend0() */ + while (((pend0 = LOCAL_HUB_L(PI_INT_PEND0)) & + (mask0 = LOCAL_HUB_L(pi_int_mask0))) != 0) { + pend0 &= mask0; /* Pick intrs we should look at */ + if (pend0) { + /* Prevent any of the picked intrs from recursing */ + LOCAL_HUB_S(pi_int_mask0, mask0 & ~(pend0)); + do { + swlevel = ms1bit(pend0); + LOCAL_HUB_CLR_INTR(swlevel); + /* "map" swlevel to irq */ + irq = LEVEL_TO_IRQ(thiscpu, swlevel); + do_IRQ(irq, regs); + /* clear bit in pend0 */ + pend0 ^= 1ULL << swlevel; + } while(pend0); + /* Now allow the set of serviced intrs again */ + LOCAL_HUB_S(pi_int_mask0, mask0); + LOCAL_HUB_L(PI_INT_PEND0); + } + } +} + + +/* Startup one of the (PCI ...) IRQs routes over a bridge. */ +static unsigned int startup_bridge_irq(unsigned int irq) +{ + bridgereg_t device; + bridge_t *bridge; + int pin, swlevel; + cpuid_t cpu; + nasid_t master = NASID_FROM_PCI_IRQ(irq); + + if (irq < BASE_PCI_IRQ) + return 0; + + bridge = (bridge_t *) NODE_SWIN_BASE(master, WID_FROM_PCI_IRQ(irq)); + pin = SLOT_FROM_PCI_IRQ(irq); + cpu = IRQ_TO_CPU(irq); + + DBG("bridge_startup(): irq= 0x%x pin=%d\n", irq, pin); + /* + * "map" irq to a swlevel greater than 6 since the first 6 bits + * of INT_PEND0 are taken + */ + swlevel = alloc_level(cpu, irq); + intr_connect_level(cpu, swlevel); + + bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (master << 8)); + bridge->b_int_enable |= (1 << pin); + /* more stuff in int_enable reg */ + bridge->b_int_enable |= 0x7ffffe00; + + /* + * XXX This only works if b_int_device is initialized to 0! + * We program the bridge to have a 1:1 mapping between devices + * (slots) and intr pins. + */ + device = bridge->b_int_device; + device |= (pin << (pin*3)); + bridge->b_int_device = device; + + bridge->b_widget.w_tflush; /* Flush */ + + return 0; /* Never anything pending. */ +} + +/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */ +static unsigned int shutdown_bridge_irq(unsigned int irq) +{ + bridge_t *bridge; + int pin, swlevel; + cpuid_t cpu; + + if (irq < BASE_PCI_IRQ) + return 0; + + bridge = (bridge_t *) NODE_SWIN_BASE(NASID_FROM_PCI_IRQ(irq), + WID_FROM_PCI_IRQ(irq)); + DBG("bridge_shutdown: irq 0x%x\n", irq); + pin = SLOT_FROM_PCI_IRQ(irq); + + /* + * map irq to a swlevel greater than 6 since the first 6 bits + * of INT_PEND0 are taken + */ + swlevel = find_level(&cpu, irq); + intr_disconnect_level(cpu, swlevel); + LEVEL_TO_IRQ(cpu, swlevel) = -1; + + bridge->b_int_enable &= ~(1 << pin); + bridge->b_widget.w_tflush; /* Flush */ + + return 0; /* Never anything pending. */ +} + +static inline void enable_bridge_irq(unsigned int irq) +{ + /* All the braindamage happens magically for us in ip27_do_irq */ +} + +static void disable_bridge_irq(unsigned int irq) +{ + /* All the braindamage happens magically for us in ip27_do_irq */ +} + +static void mask_and_ack_bridge_irq(unsigned int irq) +{ + /* All the braindamage happens magically for us in ip27_do_irq */ +} + +static void end_bridge_irq (unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_bridge_irq(irq); +} + +static struct hw_interrupt_type bridge_irq_type = { + "bridge", + startup_bridge_irq, + shutdown_bridge_irq, + enable_bridge_irq, + disable_bridge_irq, + mask_and_ack_bridge_irq, + end_bridge_irq +}; + +void irq_debug(void) +{ + bridge_t *bridge = (bridge_t *) 0x9200000008000000; + + printk("bridge->b_int_status = 0x%x\n", bridge->b_int_status); + printk("bridge->b_int_enable = 0x%x\n", bridge->b_int_enable); + printk("PI_INT_PEND0 = 0x%lx\n", LOCAL_HUB_L(PI_INT_PEND0)); + printk("PI_INT_MASK0_A = 0x%lx\n", LOCAL_HUB_L(PI_INT_MASK0_A)); +} + +void __init init_IRQ(void) +{ + int i; + + set_except_vector(0, ip27_irq); + + /* + * Right now the bridge irq is our kitchen sink interrupt type + */ + for (i = 0; i <= NR_IRQS; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &bridge_irq_type; + } +} + +/* + * Get values that vary depending on which CPU and bit we're operating on. + */ +static hub_intmasks_t *intr_get_ptrs(cpuid_t cpu, int bit, int *new_bit, + hubreg_t **intpend_masks, int *ip) +{ + hub_intmasks_t *hub_intmasks; + + hub_intmasks = &cpu_data[cpu].p_intmasks; + if (bit < N_INTPEND_BITS) { + *intpend_masks = hub_intmasks->intpend0_masks; + *ip = 0; + *new_bit = bit; + } else { + *intpend_masks = hub_intmasks->intpend1_masks; + *ip = 1; + *new_bit = bit - N_INTPEND_BITS; + } + return hub_intmasks; +} + +int intr_connect_level(int cpu, int bit) +{ + int ip; + int slice = cputoslice(cpu); + volatile hubreg_t *mask_reg; + hubreg_t *intpend_masks; + nasid_t nasid = COMPACT_TO_NASID_NODEID(cputocnode(cpu)); + + (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks, &ip); + + /* Make sure it's not already pending when we connect it. */ + REMOTE_HUB_CLR_INTR(nasid, bit + ip * N_INTPEND_BITS); + + intpend_masks[0] |= (1ULL << (u64)bit); + + if (ip == 0) { + mask_reg = REMOTE_HUB_ADDR(nasid, PI_INT_MASK0_A + + PI_INT_MASK_OFFSET * slice); + } else { + mask_reg = REMOTE_HUB_ADDR(nasid, PI_INT_MASK1_A + + PI_INT_MASK_OFFSET * slice); + } + HUB_S(mask_reg, intpend_masks[0]); + return(0); +} + +int intr_disconnect_level(int cpu, int bit) +{ + int ip; + int slice = cputoslice(cpu); + volatile hubreg_t *mask_reg; + hubreg_t *intpend_masks; + nasid_t nasid = COMPACT_TO_NASID_NODEID(cputocnode(cpu)); + + (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks, &ip); + intpend_masks[0] &= ~(1ULL << (u64)bit); + if (ip == 0) { + mask_reg = REMOTE_HUB_ADDR(nasid, PI_INT_MASK0_A + + PI_INT_MASK_OFFSET * slice); + } else { + mask_reg = REMOTE_HUB_ADDR(nasid, PI_INT_MASK1_A + + PI_INT_MASK_OFFSET * slice); + } + HUB_S(mask_reg, intpend_masks[0]); + return(0); +} + + +irqreturn_t handle_resched_intr(int irq, void *dev_id, struct pt_regs *regs) +{ + /* Nothing, the return from intr will work for us */ + return IRQ_NONE; +} + +#ifdef CONFIG_SMP + +void core_send_ipi(int destid, unsigned int action) +{ + int irq; + +#if (CPUS_PER_NODE == 2) + switch (action) { + case SMP_RESCHEDULE_YOURSELF: + irq = CPU_RESCHED_A_IRQ; + break; + case SMP_CALL_FUNCTION: + irq = CPU_CALL_A_IRQ; + break; + default: + panic("sendintr"); + } + irq += cputoslice(destid); + + /* + * Convert the compact hub number to the NASID to get the correct + * part of the address space. Then set the interrupt bit associated + * with the CPU we want to send the interrupt to. + */ + REMOTE_HUB_SEND_INTR(COMPACT_TO_NASID_NODEID(cputocnode(destid)), + FAST_IRQ_TO_LEVEL(irq)); +#else + << Bomb! Must redefine this for more than 2 CPUS. >> +#endif +} + +#endif + +extern irqreturn_t smp_call_function_interrupt(int irq, void *dev, + struct pt_regs *regs); + +void install_cpuintr(int cpu) +{ +#ifdef CONFIG_SMP +#if (CPUS_PER_NODE == 2) + static int done = 0; + + /* + * This is a hack till we have a pernode irqlist. Currently, + * just have the master cpu set up the handlers for the per + * cpu irqs. + */ + if (done == 0) { + int j; + + if (request_irq(CPU_RESCHED_A_IRQ, handle_resched_intr, + 0, "resched", 0)) + panic("intercpu intr unconnectible"); + if (request_irq(CPU_RESCHED_B_IRQ, handle_resched_intr, + 0, "resched", 0)) + panic("intercpu intr unconnectible"); + if (request_irq(CPU_CALL_A_IRQ, smp_call_function_interrupt, + 0, "callfunc", 0)) + panic("intercpu intr unconnectible"); + if (request_irq(CPU_CALL_B_IRQ, smp_call_function_interrupt, + 0, "callfunc", 0)) + panic("intercpu intr unconnectible"); + + for (j = 0; j < PERNODE_LEVELS; j++) + LEVEL_TO_IRQ(0, j) = -1; + LEVEL_TO_IRQ(0, FAST_IRQ_TO_LEVEL(CPU_RESCHED_A_IRQ)) = + CPU_RESCHED_A_IRQ; + LEVEL_TO_IRQ(0, FAST_IRQ_TO_LEVEL(CPU_RESCHED_B_IRQ)) = + CPU_RESCHED_B_IRQ; + LEVEL_TO_IRQ(0, FAST_IRQ_TO_LEVEL(CPU_CALL_A_IRQ)) = + CPU_CALL_A_IRQ; + LEVEL_TO_IRQ(0, FAST_IRQ_TO_LEVEL(CPU_CALL_B_IRQ)) = + CPU_CALL_B_IRQ; + for (j = 1; j < MAX_COMPACT_NODES; j++) + memcpy(&node_level_to_irq[j][0], + &node_level_to_irq[0][0], + sizeof(node_level_to_irq[0][0])*PERNODE_LEVELS); + + done = 1; + } + + intr_connect_level(cpu, FAST_IRQ_TO_LEVEL(CPU_RESCHED_A_IRQ + + cputoslice(cpu))); + intr_connect_level(cpu, FAST_IRQ_TO_LEVEL(CPU_CALL_A_IRQ + + cputoslice(cpu))); +#else /* CPUS_PER_NODE */ +#error Must redefine this for more than 2 CPUS. +#endif /* CPUS_PER_NODE */ +#endif /* CONFIG_SMP */ +} + +void install_tlbintr(int cpu) +{ +#if 0 + int intr_bit = N_INTPEND_BITS + TLB_INTR_A + cputoslice(cpu); + + intr_connect_level(cpu, intr_bit); +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip27/ip27-irq-glue.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,64 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999 Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#include +#include +#include +#include + + .text + .set noat + .align 5 +NESTED(ip27_irq, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + + /* IP27 may signal interrupt which we're not interested in. + Mask them out. */ + mfc0 s0, CP0_CAUSE + mfc0 t0, CP0_STATUS + and s0, t0 + + /* First check for RT interrupt. */ + andi a0, s0, CAUSEF_IP4 + beqz a0, 1f + + /* Ok, a timer interrupt. */ + move a0, sp + jal rt_timer_interrupt + + j ret_from_irq + +1: andi a0, s0, (CAUSEF_IP2 | CAUSEF_IP3) + beqz a0, 1f + + /* ... a device interrupt ... */ + move a0, sp + jal ip27_do_irq + + j ret_from_irq + +1: +#if 1 + mfc0 a1, CP0_STATUS + srl a1, a1, 8 + andi a1, 0xff + + mfc0 a2, CP0_CAUSE + srl a2, a2, 8 + andi a2, 0xff + + move a3, s0 + PRINT("Spurious interrupt, c0_status = %02x, c0_cause = %02x, pending %02x.\n") + ld a1, PT_EPC(sp) +0: b 0b +#endif + + j ret_from_irq + END(ip27_irq) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip27/ip27-klconfig.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,135 @@ +/* + * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +klinfo_t *find_component(lboard_t *brd, klinfo_t *kli, unsigned char struct_type) +{ + int index, j; + + if (kli == (klinfo_t *)NULL) { + index = 0; + } else { + for (j = 0; j < KLCF_NUM_COMPS(brd); j++) + if (kli == KLCF_COMP(brd, j)) + break; + index = j; + if (index == KLCF_NUM_COMPS(brd)) { + printk("find_component: Bad pointer: 0x%p\n", kli); + return (klinfo_t *)NULL; + } + index++; /* next component */ + } + + for (; index < KLCF_NUM_COMPS(brd); index++) { + kli = KLCF_COMP(brd, index); + if (KLCF_COMP_TYPE(kli) == struct_type) + return kli; + } + + /* Didn't find it. */ + return (klinfo_t *)NULL; +} + +klinfo_t *find_first_component(lboard_t *brd, unsigned char struct_type) +{ + return find_component(brd, (klinfo_t *)NULL, struct_type); +} + +lboard_t * find_lboard(lboard_t *start, unsigned char brd_type) +{ + /* Search all boards stored on this node. */ + while (start) { + if (start->brd_type == brd_type) + return start; + start = KLCF_NEXT(start); + } + /* Didn't find it. */ + return (lboard_t *)NULL; +} + +lboard_t * find_lboard_class(lboard_t *start, unsigned char brd_type) +{ + /* Search all boards stored on this node. */ + while (start) { + if (KLCLASS(start->brd_type) == KLCLASS(brd_type)) + return start; + start = KLCF_NEXT(start); + } + + /* Didn't find it. */ + return (lboard_t *)NULL; +} + +cnodeid_t get_cpu_cnode(cpuid_t cpu) +{ + return CPUID_TO_COMPACT_NODEID(cpu); +} + +klcpu_t * nasid_slice_to_cpuinfo(nasid_t nasid, int slice) +{ + lboard_t *brd; + klcpu_t *acpu; + + if (!(brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IP27))) + return (klcpu_t *)NULL; + + if (!(acpu = (klcpu_t *)find_first_component(brd, KLSTRUCT_CPU))) + return (klcpu_t *)NULL; + + do { + if ((acpu->cpu_info.physid) == slice) + return acpu; + } while ((acpu = (klcpu_t *)find_component(brd, (klinfo_t *)acpu, + KLSTRUCT_CPU))); + return (klcpu_t *)NULL; +} + +klcpu_t * sn_get_cpuinfo(cpuid_t cpu) +{ + nasid_t nasid; + int slice; + klcpu_t *acpu; + gda_t *gdap = GDA; + cnodeid_t cnode; + + if (!(cpu < MAXCPUS)) { + printk("sn_get_cpuinfo: illegal cpuid 0x%lx\n", cpu); + return NULL; + } + + cnode = get_cpu_cnode(cpu); + if (cnode == INVALID_CNODEID) + return NULL; + + if ((nasid = gdap->g_nasidtable[cnode]) == INVALID_NASID) + return NULL; + + for (slice = 0; slice < CPUS_PER_NODE; slice++) { + acpu = nasid_slice_to_cpuinfo(nasid, slice); + if (acpu && acpu->cpu_info.virtid == cpu) + return acpu; + } + return NULL; +} + +int get_cpu_slice(cpuid_t cpu) +{ + klcpu_t *acpu; + + if ((acpu = sn_get_cpuinfo(cpu)) == NULL) + return -1; + return acpu->cpu_info.physid; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip27/ip27-klnuma.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,143 @@ +/* + * Ported from IRIX to Linux by Kanoj Sarcar, 06/08/00. + * Copyright 2000 - 2001 Silicon Graphics, Inc. + * Copyright 2000 - 2001 Kanoj Sarcar (kanoj@sgi.com) + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern char _end; +static cpumask_t ktext_repmask; + +/* + * XXX - This needs to be much smarter about where it puts copies of the + * kernel. For example, we should never put a copy on a headless node, + * and we should respect the topology of the machine. + */ +void __init setup_replication_mask(int maxnodes) +{ + static int numa_kernel_replication_ratio; + cnodeid_t cnode; + + /* Set only the master cnode's bit. The master cnode is always 0. */ + CPUMASK_CLRALL(ktext_repmask); + CPUMASK_SETB(ktext_repmask, 0); + + numa_kernel_replication_ratio = 0; +#ifdef CONFIG_REPLICATE_KTEXT +#ifndef CONFIG_MAPPED_KERNEL +#error Kernel replication works with mapped kernel support. No calias support. +#endif + numa_kernel_replication_ratio = 1; +#endif + + for (cnode = 1; cnode < numnodes; cnode++) { + /* See if this node should get a copy of the kernel */ + if (numa_kernel_replication_ratio && + !(cnode % numa_kernel_replication_ratio)) { + + /* Advertise that we have a copy of the kernel */ + CPUMASK_SETB(ktext_repmask, cnode); + } + } + + /* Set up a GDA pointer to the replication mask. */ + GDA->g_ktext_repmask = &ktext_repmask; +} + + +static __init void set_ktext_source(nasid_t client_nasid, nasid_t server_nasid) +{ + kern_vars_t *kvp; + cnodeid_t client_cnode; + + client_cnode = NASID_TO_COMPACT_NODEID(client_nasid); + + kvp = &(PLAT_NODE_DATA(client_cnode)->kern_vars); + + KERN_VARS_ADDR(client_nasid) = (unsigned long)kvp; + + kvp->kv_magic = KV_MAGIC; + + kvp->kv_ro_nasid = server_nasid; + kvp->kv_rw_nasid = master_nasid; + kvp->kv_ro_baseaddr = NODE_CAC_BASE(server_nasid); + kvp->kv_rw_baseaddr = NODE_CAC_BASE(master_nasid); + printk("REPLICATION: ON nasid %d, ktext from nasid %d, kdata from nasid %d\n", client_nasid, server_nasid, master_nasid); +} + +/* XXX - When the BTE works, we should use it instead of this. */ +static __init void copy_kernel(nasid_t dest_nasid) +{ + extern char _stext, _etext; + unsigned long dest_kern_start, source_start, source_end, kern_size; + + source_start = (unsigned long)&_stext; + source_end = (unsigned long)&_etext; + kern_size = source_end - source_start; + + dest_kern_start = CHANGE_ADDR_NASID(MAPPED_KERN_RO_TO_K0(source_start), + dest_nasid); + memcpy((void *)dest_kern_start, (void *)source_start, kern_size); +} + +void __init replicate_kernel_text(int maxnodes) +{ + cnodeid_t cnode; + nasid_t client_nasid; + nasid_t server_nasid; + + server_nasid = master_nasid; + + /* Record where the master node should get its kernel text */ + set_ktext_source(master_nasid, master_nasid); + + for (cnode = 1; cnode < maxnodes; cnode++) { + client_nasid = COMPACT_TO_NASID_NODEID(cnode); + + /* Check if this node should get a copy of the kernel */ + if (CPUMASK_TSTB(ktext_repmask, cnode)) { + server_nasid = client_nasid; + copy_kernel(server_nasid); + } + + /* Record where this node should get its kernel text */ + set_ktext_source(client_nasid, server_nasid); + } +} + +/* + * Return pfn of first free page of memory on a node. PROM may allocate + * data structures on the first couple of pages of the first slot of each + * node. If this is the case, getfirstfree(node) > getslotstart(node, 0). + */ +pfn_t node_getfirstfree(cnodeid_t cnode) +{ + unsigned long loadbase = CKSEG0; + nasid_t nasid = COMPACT_TO_NASID_NODEID(cnode); + unsigned long offset; + +#ifdef CONFIG_MAPPED_KERNEL + loadbase = CKSSEG + 16777216; +#endif + offset = PAGE_ALIGN((unsigned long)(&_end)) - loadbase; + if ((cnode == 0) || (CPUMASK_TSTB(ktext_repmask, cnode))) + return (TO_NODE(nasid, offset) >> PAGE_SHIFT); + else + return (KDM_TO_PHYS(PAGE_ALIGN(SYMMON_STK_ADDR(nasid, 0))) >> + PAGE_SHIFT); +} + --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip27/ip27-memory.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,337 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 by Ralf Baechle + * Copyright (C) 2000 by Silicon Graphics, Inc. + * + * On SGI IP27 the ARC memory configuration data is completly bogus but + * alternate easier to use mechanisms are available. + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* ip27-klnuma.c */ +extern pfn_t node_getfirstfree(cnodeid_t cnode); + +#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT) +#define SLOT_IGNORED 0xffff + +short slot_lastfilled_cache[MAX_COMPACT_NODES]; +unsigned short slot_psize_cache[MAX_COMPACT_NODES][MAX_MEM_SLOTS]; +static pfn_t numpages; + +plat_pg_data_t *plat_node_data[MAX_COMPACT_NODES]; +bootmem_data_t plat_node_bdata[MAX_COMPACT_NODES]; + +int numa_debug(void) +{ + printk("NUMA debug\n"); + *(int *)0 = 0; + return(0); +} + +/* + * Return the number of pages of memory provided by the given slot + * on the specified node. + */ +pfn_t slot_getsize(cnodeid_t node, int slot) +{ + return (pfn_t) slot_psize_cache[node][slot]; +} + +/* + * Return highest slot filled + */ +int node_getlastslot(cnodeid_t node) +{ + return (int) slot_lastfilled_cache[node]; +} + +/* + * Return the pfn of the last free page of memory on a node. + */ +pfn_t node_getmaxclick(cnodeid_t node) +{ + pfn_t slot_psize; + int slot; + + /* + * Start at the top slot. When we find a slot with memory in it, + * that's the winner. + */ + for (slot = (node_getnumslots(node) - 1); slot >= 0; slot--) { + if ((slot_psize = slot_getsize(node, slot))) { + if (slot_psize == SLOT_IGNORED) + continue; + /* Return the basepfn + the slot size, minus 1. */ + return slot_getbasepfn(node, slot) + slot_psize - 1; + } + } + + /* + * If there's no memory on the node, return 0. This is likely + * to cause problems. + */ + return (pfn_t)0; +} + +static pfn_t slot_psize_compute(cnodeid_t node, int slot) +{ + nasid_t nasid; + lboard_t *brd; + klmembnk_t *banks; + unsigned long size; + + nasid = COMPACT_TO_NASID_NODEID(node); + /* Find the node board */ + brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IP27); + if (!brd) + return 0; + + /* Get the memory bank structure */ + banks = (klmembnk_t *)find_first_component(brd, KLSTRUCT_MEMBNK); + if (!banks) + return 0; + + /* Size in _Megabytes_ */ + size = (unsigned long)banks->membnk_bnksz[slot/4]; + + /* hack for 128 dimm banks */ + if (size <= 128) { + if (slot%4 == 0) { + size <<= 20; /* size in bytes */ + return(size >> PAGE_SHIFT); + } else { + return 0; + } + } else { + size /= 4; + size <<= 20; + return(size >> PAGE_SHIFT); + } +} + +pfn_t szmem(pfn_t fpage, pfn_t maxpmem) +{ + cnodeid_t node; + int slot, numslots; + pfn_t num_pages = 0, slot_psize; + pfn_t slot0sz = 0, nodebytes; /* Hack to detect problem configs */ + int ignore; + + for (node = 0; node < numnodes; node++) { + numslots = node_getnumslots(node); + ignore = nodebytes = 0; + for (slot = 0; slot < numslots; slot++) { + slot_psize = slot_psize_compute(node, slot); + if (slot == 0) slot0sz = slot_psize; + /* + * We need to refine the hack when we have replicated + * kernel text. + */ + nodebytes += SLOT_SIZE; + if ((nodebytes >> PAGE_SHIFT) * (sizeof(struct page)) > + (slot0sz << PAGE_SHIFT)) + ignore = 1; + if (ignore && slot_psize) { + printk("Ignoring slot %d onwards on node %d\n", + slot, node); + slot_psize_cache[node][slot] = SLOT_IGNORED; + slot = numslots; + continue; + } + num_pages += slot_psize; + slot_psize_cache[node][slot] = + (unsigned short) slot_psize; + if (slot_psize) + slot_lastfilled_cache[node] = slot; + } + } + if (maxpmem) + return((maxpmem > num_pages) ? num_pages : maxpmem); + else + return num_pages; +} + +/* + * Currently, the intranode memory hole support assumes that each slot + * contains at least 32 MBytes of memory. We assume all bootmem data + * fits on the first slot. + */ +void __init prom_meminit(void) +{ + extern void mlreset(void); + cnodeid_t node; + pfn_t slot_firstpfn, slot_lastpfn, slot_freepfn; + unsigned long bootmap_size; + int node_datasz; + + node_datasz = PFN_UP(sizeof(plat_pg_data_t)); + mlreset(); + numpages = szmem(0, 0); + for (node = (numnodes - 1); node >= 0; node--) { + slot_firstpfn = slot_getbasepfn(node, 0); + slot_lastpfn = slot_firstpfn + slot_getsize(node, 0); + slot_freepfn = node_getfirstfree(node); + /* Foll line hack for non discontigmem; remove once discontigmem + * becomes the default. */ + max_low_pfn = (slot_lastpfn - slot_firstpfn); + + /* + * Allocate the node data structure on the node first. + */ + plat_node_data[node] = (plat_pg_data_t *)(__va(slot_freepfn \ + << PAGE_SHIFT)); + NODE_DATA(node)->bdata = plat_node_bdata + node; + slot_freepfn += node_datasz; + bootmap_size = init_bootmem_node(NODE_DATA(node), slot_freepfn, + slot_firstpfn, slot_lastpfn); + free_bootmem_node(NODE_DATA(node), slot_firstpfn << PAGE_SHIFT, + (slot_lastpfn - slot_firstpfn) << PAGE_SHIFT); + reserve_bootmem_node(NODE_DATA(node), slot_firstpfn << PAGE_SHIFT, + ((slot_freepfn - slot_firstpfn) << PAGE_SHIFT) + bootmap_size); + } + printk("Total memory probed : 0x%lx pages\n", numpages); +} + +int __init page_is_ram(unsigned long pagenr) +{ + return 1; +} + +void __init +prom_free_prom_memory (void) +{ + /* We got nothing to free here ... */ +} + +#ifdef CONFIG_DISCONTIGMEM + +static pfn_t pagenr; + +void __init paging_init(void) +{ + pmd_t *pmd = kpmdtbl; + pte_t *pte = kptbl; + + cnodeid_t node; + unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0}; + int i; + + /* Initialize the entire pgd. */ + pgd_init((unsigned long)swapper_pg_dir); + pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table); + memset((void *)invalid_pte_table, 0, sizeof(pte_t) * PTRS_PER_PTE); + + /* This is for vmalloc */ + memset((void *)kptbl, 0, PAGE_SIZE << PGD_ORDER); + memset((void *)kpmdtbl, 0, PAGE_SIZE); + set_pgd(swapper_pg_dir, __pgd(kpmdtbl)); + for (i = 0; i < (1 << PGD_ORDER); pmd++,i++,pte+=PTRS_PER_PTE) + pmd_val(*pmd) = (unsigned long)pte; + + for (node = 0; node < numnodes; node++) { + pfn_t start_pfn = slot_getbasepfn(node, 0); + pfn_t end_pfn = node_getmaxclick(node); + + zones_size[ZONE_DMA] = end_pfn + 1 - start_pfn; + free_area_init_node(node, NODE_DATA(node), 0, zones_size, + start_pfn, 0); + } +} + +void __init mem_init(void) +{ + extern char _stext, _etext, _fdata, _edata; + extern char __init_begin, __init_end; + extern unsigned long setup_zero_pages(void); + cnodeid_t nid; + unsigned long tmp; + unsigned long codesize, datasize, initsize; + int slot, numslots; + struct page *pg, *pslot; + + num_physpages = numpages; /* memory already sized by szmem */ + max_mapnr = pagenr; /* already found during paging_init */ + high_memory = (void *) __va(max_mapnr << PAGE_SHIFT); + + for (nid = 0; nid < numnodes; nid++) { + + /* + * Hack till free_area_init_core() zeroes free_pages + */ + for (tmp = 0; tmp < MAX_NR_ZONES; tmp++) + PLAT_NODE_DATA(nid)->gendata.node_zones[tmp].free_pages=0; + /* + * This will free up the bootmem, ie, slot 0 memory. + */ + totalram_pages += free_all_bootmem_node(NODE_DATA(nid)); + + /* + * We need to manually do the other slots. + */ + pg = NODE_DATA(nid)->node_mem_map + slot_getsize(nid, 0); + numslots = node_getlastslot(nid); + for (slot = 1; slot <= numslots; slot++) { + pslot = NODE_DATA(nid)->node_mem_map + + slot_getbasepfn(nid, slot) - slot_getbasepfn(nid, 0); + + /* + * Mark holes in previous slot. May also want to + * free up the pages that hold the memmap entries. + */ + while (pg < pslot) { + pg++; + } + + /* + * Free valid memory in current slot. + */ + pslot += slot_getsize(nid, slot); + while (pg < pslot) { + /* if (!page_is_ram(pgnr)) continue; */ + /* commented out until page_is_ram works */ + ClearPageReserved(pg); + atomic_set(&pg->count, 1); + __free_page(pg); + totalram_pages++; + pg++; pgnr++; + } + } + } + + totalram_pages -= setup_zero_pages(); /* This comes from node 0 */ + + codesize = (unsigned long) &_etext - (unsigned long) &_stext; + datasize = (unsigned long) &_edata - (unsigned long) &_fdata; + initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin; + + tmp = (unsigned long) nr_free_pages(); + printk("Memory: %luk/%luk available (%ldk kernel code, %ldk reserved, " + "%ldk data, %ldk init)\n", + tmp << (PAGE_SHIFT-10), + num_physpages << (PAGE_SHIFT-10), + codesize >> 10, + (num_physpages - tmp) << (PAGE_SHIFT-10), + datasize >> 10, + initsize >> 10); +} + +#endif /* CONFIG_DISCONTIGMEM */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip27/ip27-nmi.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,168 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if 0 +#define NODE_NUM_CPUS(n) CNODE_NUM_CPUS(n) +#else +#define NODE_NUM_CPUS(n) CPUS_PER_NODE +#endif + +#define CNODEID_NONE (cnodeid_t)-1 +#define enter_panic_mode() spin_lock(&nmi_lock) + +typedef unsigned long machreg_t; + +spinlock_t nmi_lock = SPIN_LOCK_UNLOCKED; + +/* + * Lets see what else we need to do here. Set up sp, gp? + */ +void nmi_dump(void) +{ + void cont_nmi_dump(void); + + cont_nmi_dump(); +} + +void install_cpu_nmi_handler(int slice) +{ + nmi_t *nmi_addr; + + nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice); + if (nmi_addr->call_addr) + return; + nmi_addr->magic = NMI_MAGIC; + nmi_addr->call_addr = (void *)nmi_dump; + nmi_addr->call_addr_c = + (void *)(~((unsigned long)(nmi_addr->call_addr))); + nmi_addr->call_parm = 0; +} + +/* + * Copy the cpu registers which have been saved in the IP27prom format + * into the eframe format for the node under consideration. + */ + +void +nmi_cpu_eframe_save(nasid_t nasid, + int slice) +{ + int i, numberof_nmi_cpu_regs; + machreg_t *prom_format; + + /* Get the total number of registers being saved by the prom */ + numberof_nmi_cpu_regs = sizeof(struct reg_struct) / sizeof(machreg_t); + + /* Get the pointer to the current cpu's register set. */ + prom_format = + (machreg_t *)(TO_UNCAC(TO_NODE(nasid, IP27_NMI_KREGS_OFFSET)) + + slice * IP27_NMI_KREGS_CPU_SIZE); + + printk("NMI nasid %d: slice %d\n", nasid, slice); + for (i = 0; i < numberof_nmi_cpu_regs; i++) + printk("0x%lx ", prom_format[i]); + printk("\n\n"); +} + +/* + * Copy the cpu registers which have been saved in the IP27prom format + * into the eframe format for the node under consideration. + */ +void +nmi_node_eframe_save(cnodeid_t cnode) +{ + int cpu; + nasid_t nasid; + + /* Make sure that we have a valid node */ + if (cnode == CNODEID_NONE) + return; + + nasid = COMPACT_TO_NASID_NODEID(cnode); + if (nasid == INVALID_NASID) + return; + + /* Save the registers into eframe for each cpu */ + for(cpu = 0; cpu < NODE_NUM_CPUS(cnode); cpu++) + nmi_cpu_eframe_save(nasid, cpu); +} + +/* + * Save the nmi cpu registers for all cpus in the system. + */ +void +nmi_eframes_save(void) +{ + cnodeid_t cnode; + + for(cnode = 0 ; cnode < numnodes; cnode++) + nmi_node_eframe_save(cnode); +} + +void +cont_nmi_dump(void) +{ +#ifndef REAL_NMI_SIGNAL + static atomic_t nmied_cpus = ATOMIC_INIT(0); + + atomic_inc(&nmied_cpus); +#endif + /* + * Use enter_panic_mode to allow only 1 cpu to proceed + */ + enter_panic_mode(); + +#ifdef REAL_NMI_SIGNAL + /* + * Wait up to 15 seconds for the other cpus to respond to the NMI. + * If a cpu has not responded after 10 sec, send it 1 additional NMI. + * This is for 2 reasons: + * - sometimes a MMSC fail to NMI all cpus. + * - on 512p SN0 system, the MMSC will only send NMIs to + * half the cpus. Unfortunately, we don't know which cpus may be + * NMIed - it depends on how the site chooses to configure. + * + * Note: it has been measure that it takes the MMSC up to 2.3 secs to + * send NMIs to all cpus on a 256p system. + */ + for (i=0; i < 1500; i++) { + for (node=0; node < numnodes; node++) + if (NODEPDA(node)->dump_count == 0) + break; + if (node == numnodes) + break; + if (i == 1000) { + for (node=0; node < numnodes; node++) + if (NODEPDA(node)->dump_count == 0) { + cpu = CNODE_TO_CPU_BASE(node); + for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) { + CPUMASK_SETB(nmied_cpus, cpu); + /* + * cputonasid, cputoslice + * needs kernel cpuid + */ + SEND_NMI((cputonasid(cpu)), (cputoslice(cpu))); + } + } + + } + udelay(10000); + } +#else + while (atomic_read(&nmied_cpus) != num_online_cpus()); +#endif + + /* + * Save the nmi cpu registers for all cpu in the eframe format. + */ + nmi_eframes_save(); + LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip27/ip27-reset.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,80 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Reset an IP27. + * + * Copyright (C) 1997, 1998, 1999, 2000 by Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void machine_restart(char *command) __attribute__((noreturn)); +void machine_halt(void) __attribute__((noreturn)); +void machine_power_off(void) __attribute__((noreturn)); + +#define noreturn while(1); /* Silence gcc. */ + +/* XXX How to pass the reboot command to the firmware??? */ +static void ip27_machine_restart(char *command) +{ +#if 0 + int i; +#endif + + printk("Reboot started from CPU %d\n", smp_processor_id()); +#ifdef CONFIG_SMP + smp_send_stop(); +#endif +#if 0 + for (i = 0; i < numnodes; i++) + REMOTE_HUB_S(COMPACT_TO_NASID_NODEID(i), PROMOP_REG, + PROMOP_REBOOT); +#else + LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET); +#endif + noreturn; +} + +static void ip27_machine_halt(void) +{ + int i; + +#ifdef CONFIG_SMP + smp_send_stop(); +#endif + for (i = 0; i < numnodes; i++) + REMOTE_HUB_S(COMPACT_TO_NASID_NODEID(i), PROMOP_REG, + PROMOP_RESTART); + LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET); + noreturn; +} + +static void ip27_machine_power_off(void) +{ + /* To do ... */ + noreturn; +} + +void ip27_reboot_setup(void) +{ + _machine_restart = ip27_machine_restart; + _machine_halt = ip27_machine_halt; + _machine_power_off = ip27_machine_power_off; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip27/ip27-setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,319 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * SGI IP27 specific setup. + * + * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999, 2000 Silcon Graphics, Inc. + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Check against user dumbness. */ +#ifdef CONFIG_VT +#error CONFIG_VT not allowed for IP27. +#endif + +#undef DEBUG_SETUP +#ifdef DEBUG_SETUP +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +extern void ip27_be_init(void) __init; + +/* + * get_nasid() returns the physical node id number of the caller. + */ +nasid_t +get_nasid(void) +{ + return (nasid_t)((LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_NODEID_MASK) + >> NSRI_NODEID_SHFT); +} + +/* Extracted from the IOC3 meta driver. FIXME. */ +static inline void ioc3_sio_init(void) +{ + struct ioc3 *ioc3; + nasid_t nid; + long loops; + + nid = get_nasid(); + ioc3 = (struct ioc3 *) KL_CONFIG_CH_CONS_INFO(nid)->memory_base; + + ioc3->sscr_a = 0; /* PIO mode for uarta. */ + ioc3->sscr_b = 0; /* PIO mode for uartb. */ + ioc3->sio_iec = ~0; + ioc3->sio_ies = (SIO_IR_SA_INT | SIO_IR_SB_INT); + + loops=1000000; while(loops--); + ioc3->sregs.uarta.iu_fcr = 0; + ioc3->sregs.uartb.iu_fcr = 0; + loops=1000000; while(loops--); +} + +static inline void ioc3_eth_init(void) +{ + struct ioc3 *ioc3; + nasid_t nid; + + nid = get_nasid(); + ioc3 = (struct ioc3 *) KL_CONFIG_CH_CONS_INFO(nid)->memory_base; + + ioc3->eier = 0; +} + +/* Try to catch kernel missconfigurations and give user an indication what + option to select. */ +static void __init verify_mode(void) +{ + int n_mode; + + n_mode = LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_MORENODES_MASK; + printk("Machine is in %c mode.\n", n_mode ? 'N' : 'M'); +#ifdef CONFIG_SGI_SN0_N_MODE + if (!n_mode) + panic("Kernel compiled for M mode."); +#else + if (n_mode) + panic("Kernel compiled for N mode."); +#endif +} + +#define XBOW_WIDGET_PART_NUM 0x0 +#define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */ +#define BASE_XBOW_PORT 8 /* Lowest external port */ + +unsigned int bus_to_cpu[256]; +unsigned long bus_to_baddr[256]; + +void __init pcibr_setup(cnodeid_t nid) +{ + int i, start, num; + unsigned long masterwid; + bridge_t *bridge; + volatile u64 hubreg; + nasid_t nasid, masternasid; + xwidget_part_num_t partnum; + widgetreg_t widget_id; + static spinlock_t pcibr_setup_lock = SPIN_LOCK_UNLOCKED; + + /* + * If the master is doing this for headless node, nothing to do. + * This is because currently we require at least one of the hubs + * (master hub) connected to the xbow to have at least one enabled + * cpu to receive intrs. Else we need an array bus_to_intrnasid[] + * that bridge_startup() needs to use to target intrs. All dma is + * routed thru the widget of the master hub. The master hub wid + * is selectable by WIDGET_A below. + */ + if (nid != get_compact_nodeid()) + return; + /* + * find what's on our local node + */ + spin_lock(&pcibr_setup_lock); + start = num_bridges; /* Remember where we start from */ + nasid = COMPACT_TO_NASID_NODEID(nid); + hubreg = REMOTE_HUB_L(nasid, IIO_LLP_CSR); + if (hubreg & IIO_LLP_CSR_IS_UP) { + /* link is up */ + widget_id = *(volatile widgetreg_t *) + (RAW_NODE_SWIN_BASE(nasid, 0x0) + WIDGET_ID); + partnum = XWIDGET_PART_NUM(widget_id); + printk("Cpu %d, Nasid 0x%x, pcibr_setup(): found partnum= 0x%x", + smp_processor_id(), nasid, partnum); + if (partnum == BRIDGE_WIDGET_PART_NUM) { + /* + * found direct connected bridge so must be Origin200 + */ + printk("...is bridge\n"); + num_bridges = 1; + bus_to_wid[0] = 0x8; + bus_to_nid[0] = 0; + masterwid = 0xa; + bus_to_baddr[0] = 0xa100000000000000UL; + } else if (partnum == XBOW_WIDGET_PART_NUM) { + lboard_t *brd; + klxbow_t *xbow_p; + /* + * found xbow, so may have multiple bridges + * need to probe xbow + */ + printk("...is xbow\n"); + + if ((brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), + KLTYPE_MIDPLANE8)) == NULL) + printk("argh\n"); + else + printk("brd = 0x%lx\n", (unsigned long) brd); + if ((xbow_p = (klxbow_t *) + find_component(brd, NULL, KLSTRUCT_XBOW)) == NULL) + printk("argh\n"); + else { + /* + * Okay, here's a xbow. Lets arbitrate and find + * out if we should initialize it. Set enabled + * hub connected at highest or lowest widget as + * master. + */ +#ifdef WIDGET_A + i = HUB_WIDGET_ID_MAX + 1; + do { + i--; + } while ((!XBOW_PORT_TYPE_HUB(xbow_p, i)) || + (!XBOW_PORT_IS_ENABLED(xbow_p, i))); +#else + i = HUB_WIDGET_ID_MIN - 1; + do { + i++; + } while ((!XBOW_PORT_TYPE_HUB(xbow_p, i)) || + (!XBOW_PORT_IS_ENABLED(xbow_p, i))); +#endif + masterwid = i; + masternasid = XBOW_PORT_NASID(xbow_p, i); + if (nasid == masternasid) + for (i=HUB_WIDGET_ID_MIN; i<=HUB_WIDGET_ID_MAX; i++) { + if (!XBOW_PORT_IS_ENABLED(xbow_p, i)) + continue; + if (XBOW_PORT_TYPE_IO(xbow_p, i)) { + widget_id = *(volatile widgetreg_t *) + (RAW_NODE_SWIN_BASE(nasid, i) + WIDGET_ID); + partnum = XWIDGET_PART_NUM(widget_id); + if (partnum == BRIDGE_WIDGET_PART_NUM) { + printk("widget 0x%x is a bridge\n", i); + bus_to_wid[num_bridges] = i; + bus_to_nid[num_bridges] = nasid; + bus_to_baddr[num_bridges] = ((masterwid << 60) | (1UL << 56)); /* Barrier set */ + num_bridges++; + } + } + } + } + } else if (partnum == XXBOW_WIDGET_PART_NUM) { + /* + * found xbridge, assume ibrick for now + */ + printk("...is xbridge\n"); + bus_to_wid[0] = 0xb; + bus_to_wid[1] = 0xe; + bus_to_wid[2] = 0xf; + + bus_to_nid[0] = 0; + bus_to_nid[1] = 0; + bus_to_nid[2] = 0; + + bus_to_baddr[0] = 0xa100000000000000UL; + bus_to_baddr[1] = 0xa100000000000000UL; + bus_to_baddr[2] = 0xa100000000000000UL; + masterwid = 0xa; + num_bridges = 3; + } + } + num = num_bridges - start; + spin_unlock(&pcibr_setup_lock); + /* + * set bridge registers + */ + for (i = start; i < (start + num); i++) { + + DBG("pcibr_setup: bus= %d bus_to_wid[%2d]= %d bus_to_nid[%2d]= %d\n", + i, i, bus_to_wid[i], i, bus_to_nid[i]); + + bus_to_cpu[i] = smp_processor_id(); + /* + * point to this bridge + */ + bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[i],bus_to_wid[i]); + /* + * Clear all pending interrupts. + */ + bridge->b_int_rst_stat = (BRIDGE_IRR_ALL_CLR); + /* + * Until otherwise set up, assume all interrupts are from slot 0 + */ + bridge->b_int_device = (u32) 0x0; + /* + * swap pio's to pci mem and io space (big windows) + */ + bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP; + bridge->b_wid_control |= BRIDGE_CTRL_MEM_SWAP; + + /* + * Hmm... IRIX sets additional bits in the address which + * are documented as reserved in the bridge docs. + */ + bridge->b_int_mode = 0x0; /* Don't clear ints */ + bridge->b_wid_int_upper = 0x8000 | (masterwid << 16); + bridge->b_wid_int_lower = 0x01800090; /* PI_INT_PEND_MOD off*/ + bridge->b_dir_map = (masterwid << 20); /* DMA */ + bridge->b_int_enable = 0; + + bridge->b_wid_tflush; /* wait until Bridge PIO complete */ + } +} + +extern void ip27_setup_console(void); +extern void ip27_time_init(void); +extern void ip27_reboot_setup(void); + +void __init ip27_setup(void) +{ + nasid_t nid; + hubreg_t p, e; + + ip27_setup_console(); + ip27_reboot_setup(); + + num_bridges = 0; + /* + * hub_rtc init and cpu clock intr enabled for later calibrate_delay. + */ + DBG("ip27_setup(): Entered.\n"); + nid = get_nasid(); + printk("IP27: Running on node %d.\n", nid); + + p = LOCAL_HUB_L(PI_CPU_PRESENT_A) & 1; + e = LOCAL_HUB_L(PI_CPU_ENABLE_A) & 1; + printk("Node %d has %s primary CPU%s.\n", nid, + p ? "a" : "no", + e ? ", CPU is running" : ""); + + p = LOCAL_HUB_L(PI_CPU_PRESENT_B) & 1; + e = LOCAL_HUB_L(PI_CPU_ENABLE_B) & 1; + printk("Node %d has %s secondary CPU%s.\n", nid, + p ? "a" : "no", + e ? ", CPU is running" : ""); + + verify_mode(); + ioc3_sio_init(); + ioc3_eth_init(); + per_cpu_init(); + + mips_io_port_base = IO_BASE; + board_time_init = ip27_time_init; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip27/ip27-timer.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,238 @@ +/* + * Copytight (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) + * Copytight (C) 1999, 2000 Silicon Graphics, Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * This is a hack; we really need to figure these values out dynamically + * + * Since 800 ns works very well with various HUB frequencies, such as + * 360, 380, 390 and 400 MHZ, we use 800 ns rtc cycle time. + * + * Ralf: which clock rate is used to feed the counter? + */ +#define NSEC_PER_CYCLE 800 +#define CYCLES_PER_SEC (NSEC_PER_SEC/NSEC_PER_CYCLE) +#define CYCLES_PER_JIFFY (CYCLES_PER_SEC/HZ) + +#define TICK_SIZE (tick_nsec / 1000) + +static unsigned long ct_cur[NR_CPUS]; /* What counter should be at next timer irq */ +static long last_rtc_update; /* Last time the rtc clock got updated */ + +extern volatile unsigned long wall_jiffies; + + +static int set_rtc_mmss(unsigned long nowtime) +{ + int retval = 0; + int real_seconds, real_minutes, cmos_minutes; + struct m48t35_rtc *rtc; + nasid_t nid; + + nid = get_nasid(); + rtc = (struct m48t35_rtc *)(KL_CONFIG_CH_CONS_INFO(nid)->memory_base + + IOC3_BYTEBUS_DEV0); + + rtc->control |= M48T35_RTC_READ; + cmos_minutes = BCD2BIN(rtc->min); + rtc->control &= ~M48T35_RTC_READ; + + /* + * Since we're only adjusting minutes and seconds, don't interfere with + * hour overflow. This avoids messing with unknown time zones but + * requires your RTC not to be off by more than 15 minutes + */ + real_seconds = nowtime % 60; + real_minutes = nowtime / 60; + if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) + real_minutes += 30; /* correct for half hour time zone */ + real_minutes %= 60; + + if (abs(real_minutes - cmos_minutes) < 30) { + real_seconds = BIN2BCD(real_seconds); + real_minutes = BIN2BCD(real_minutes); + rtc->control |= M48T35_RTC_SET; + rtc->sec = real_seconds; + rtc->min = real_minutes; + rtc->control &= ~M48T35_RTC_SET; + } else { + printk(KERN_WARNING + "set_rtc_mmss: can't update from %d to %d\n", + cmos_minutes, real_minutes); + retval = -1; + } + + return retval; +} + +void rt_timer_interrupt(struct pt_regs *regs) +{ + int cpu = smp_processor_id(); + int cpuA = ((cputoslice(cpu)) == 0); + int irq = 9; /* XXX Assign number */ + + irq_enter(); + write_seqlock(&xtime_lock); + +again: + LOCAL_HUB_S(cpuA ? PI_RT_PEND_A : PI_RT_PEND_B, 0); /* Ack */ + ct_cur[cpu] += CYCLES_PER_JIFFY; + LOCAL_HUB_S(cpuA ? PI_RT_COMPARE_A : PI_RT_COMPARE_B, ct_cur[cpu]); + + if (LOCAL_HUB_L(PI_RT_COUNT) >= ct_cur[cpu]) + goto again; + + kstat_cpu(cpu).irqs[irq]++; /* kstat only for bootcpu? */ + + if (cpu == 0) + do_timer(regs); + +#ifdef CONFIG_SMP + update_process_times(user_mode(regs)); +#endif /* CONFIG_SMP */ + + /* + * If we have an externally synchronized Linux clock, then update + * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be + * called as close as possible to when a second starts. + */ + if ((time_status & STA_UNSYNC) == 0 && + xtime.tv_sec > last_rtc_update + 660 && + (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && + (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { + if (rtc_set_time(xtime.tv_sec) == 0) { + last_rtc_update = xtime.tv_sec; + } else { + last_rtc_update = xtime.tv_sec - 600; + /* do it again in 60 s */ + } + } + + write_sequnlock(&xtime_lock); + irq_exit(); + + if (softirq_pending(cpu)) + do_softirq(); +} + +unsigned long ip27_do_gettimeoffset(void) +{ + unsigned long ct_cur1; + ct_cur1 = REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT) + CYCLES_PER_JIFFY; + return (ct_cur1 - ct_cur[0]) * NSEC_PER_CYCLE / 1000; +} + +/* Includes for ioc3_init(). */ +#include +#include +#include +#include +#include + +static __init unsigned long get_m48t35_time(void) +{ + unsigned int year, month, date, hour, min, sec; + struct m48t35_rtc *rtc; + nasid_t nid; + + nid = get_nasid(); + rtc = (struct m48t35_rtc *)(KL_CONFIG_CH_CONS_INFO(nid)->memory_base + + IOC3_BYTEBUS_DEV0); + + rtc->control |= M48T35_RTC_READ; + sec = rtc->sec; + min = rtc->min; + hour = rtc->hour; + date = rtc->date; + month = rtc->month; + year = rtc->year; + rtc->control &= ~M48T35_RTC_READ; + + sec = BCD2BIN(sec); + min = BCD2BIN(min); + hour = BCD2BIN(hour); + date = BCD2BIN(date); + month = BCD2BIN(month); + year = BCD2BIN(year); + + year += 1970; + + return mktime(year, month, date, hour, min, sec); +} + +void __init ip27_time_init(void) +{ + xtime.tv_sec = get_m48t35_time(); + xtime.tv_nsec = 0; + + do_gettimeoffset = ip27_do_gettimeoffset; +} + +void __init cpu_time_init(void) +{ + lboard_t *board; + klcpu_t *cpu; + int cpuid; + + /* Don't use ARCS. ARCS is fragile. Klconfig is simple and sane. */ + board = find_lboard(KL_CONFIG_INFO(get_nasid()), KLTYPE_IP27); + if (!board) + panic("Can't find board info for myself."); + + cpuid = LOCAL_HUB_L(PI_CPU_NUM) ? IP27_CPU0_INDEX : IP27_CPU1_INDEX; + cpu = (klcpu_t *) KLCF_COMP(board, cpuid); + if (!cpu) + panic("No information about myself?"); + + printk("CPU %d clock is %dMHz.\n", smp_processor_id(), cpu->cpu_speed); + + set_c0_status(SRB_TIMOCLK); +} + +void __init hub_rtc_init(cnodeid_t cnode) +{ + /* + * We only need to initialize the current node. + * If this is not the current node then it is a cpuless + * node and timeouts will not happen there. + */ + if (get_compact_nodeid() == cnode) { + int cpu = smp_processor_id(); + LOCAL_HUB_S(PI_RT_EN_A, 1); + LOCAL_HUB_S(PI_RT_EN_B, 1); + LOCAL_HUB_S(PI_PROF_EN_A, 0); + LOCAL_HUB_S(PI_PROF_EN_B, 0); + ct_cur[cpu] = CYCLES_PER_JIFFY; + LOCAL_HUB_S(PI_RT_COMPARE_A, ct_cur[cpu]); + LOCAL_HUB_S(PI_RT_COUNT, 0); + LOCAL_HUB_S(PI_RT_PEND_A, 0); + LOCAL_HUB_S(PI_RT_COMPARE_B, ct_cur[cpu]); + LOCAL_HUB_S(PI_RT_COUNT, 0); + LOCAL_HUB_S(PI_RT_PEND_B, 0); + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip27/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,9 @@ +# +# Makefile for the IP27 specific kernel interface routines under Linux. +# + +obj-y := ip27-berr.o ip27-console.o ip27-irq.o ip27-init.o ip27-irq-glue.o \ + ip27-klconfig.o ip27-klnuma.o ip27-memory.o ip27-nmi.o ip27-reset.o \ + ip27-setup.o ip27-timer.o + +EXTRA_AFLAGS := $(CFLAGS) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip27/TODO 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,23 @@ +1. Need to figure out why PCI writes to the IOC3 hang, and if it is okay +not to write to the IOC3 ever. +2. Need to figure out RRB allocation in bridge_startup(). +3. Need to figure out why address swaizzling is needed in inw/outw for +Qlogic scsi controllers. +4. Need to integrate ip27-klconfig.c:find_lboard and +ip27-init.c:find_lbaord_real. DONE +5. Is it okay to set calias space on all nodes as 0, instead of 8k as +in irix? +6. Investigate why things do not work without the setup_test() call +being invoked on all nodes in ip27-memory.c. +7. Too many CLIs in the locore handlers : +For the low level handlers set up by set_except_vector(), +__tlb_refill_debug_tramp, __xtlb_refill_debug_tramp and cacheerror, +investigate whether the code should do CLI, STI or KMODE. +8. Too many do_page_faults invoked - investigate. +9. start_thread must turn off UX64 ... and define tlb_refill_debug. +10. Need a bad pmd table, bad pte table. __bad_pmd_table/__bad_pagetable +does not agree with pgd_bad/pmd_bad. +11. All intrs (ip27_do_irq handlers) are targetted at cpu A on the node. +This might need to change later. Only the timer intr is set up to be +received on both Cpu A and B. (ip27_do_irq()/bridge_startup()) +13. Cache flushing (specially the SMP version) has to be investigated. --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip32/crime.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,49 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2001 Keith M Wesolowski + */ +#include +#include +#include +#include +#include + +void __init crime_init (void) +{ + u64 id = crime_read_64 (CRIME_ID); + u64 rev = id & CRIME_ID_REV; + + id = (id & CRIME_ID_IDBITS) >> 4; + + printk ("CRIME id %1lx rev %ld detected at %016lx\n", id, rev, + (unsigned long) CRIME_BASE); +} + +/* XXX Like on Sun, these give us various useful information to printk. */ +void crime_memerr_intr (unsigned int irq, void *dev_id, struct pt_regs *regs) +{ + u64 memerr = crime_read_64 (CRIME_MEM_ERROR_STAT); + u64 addr = crime_read_64 (CRIME_MEM_ERROR_ADDR); + memerr &= CRIME_MEM_ERROR_STAT_MASK; + + printk ("CRIME memory error at physaddr 0x%08lx status %08lx\n", + addr << 2, memerr); + + crime_write_64 (CRIME_MEM_ERROR_STAT, 0); +} + +void crime_cpuerr_intr (unsigned int irq, void *dev_id, struct pt_regs *regs) +{ + u64 cpuerr = crime_read_64 (CRIME_CPU_ERROR_STAT); + u64 addr = crime_read_64 (CRIME_CPU_ERROR_ADDR); + cpuerr &= CRIME_CPU_ERROR_MASK; + addr <<= 2UL; + + printk ("CRIME CPU interface error detected at %09lx status %08lx\n", + addr, cpuerr); + + crime_write_64 (CRIME_CPU_ERROR_STAT, 0); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip32/ip32-berr.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,35 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1999, 2000 by Ralf Baechle + * Copyright (C) 1999, 2000 by Silicon Graphics + * Copyright (C) 2002 Maciej W. Rozycki + */ +#include +#include +#include +#include +#include +#include +#include + +int ip32_be_handler(struct pt_regs *regs, int is_fixup) +{ + int data = regs->cp0_cause & 4; + + if (is_fixup) + return MIPS_BE_FIXUP; + + printk("Got %cbe at 0x%lx\n", data ? 'd' : 'i', regs->cp0_epc); + show_regs(regs); + dump_tlb_all(); + while(1); + force_sig(SIGBUS, current); +} + +void __init ip32_be_init(void) +{ + board_be_handler = ip32_be_handler; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip32/ip32-irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,584 @@ +/* + * Code to handle IP32 IRQs + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Harald Koerfgen + * Copyright (C) 2001 Keith M Wesolowski + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#undef DEBUG_IRQ +#ifdef DEBUG_IRQ +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +/* O2 irq map + * + * IP0 -> software (ignored) + * IP1 -> software (ignored) + * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ??? + * IP3 -> (irq1) X unknown + * IP4 -> (irq2) X unknown + * IP5 -> (irq3) X unknown + * IP6 -> (irq4) X unknown + * IP7 -> (irq5) 0 CPU count/compare timer (system timer) + * + * crime: (C) + * + * CRIME_INT_STAT 31:0: + * + * 0 -> 1 Video in 1 + * 1 -> 2 Video in 2 + * 2 -> 3 Video out + * 3 -> 4 Mace ethernet + * 4 -> S SuperIO sub-interrupt + * 5 -> M Miscellaneous sub-interrupt + * 6 -> A Audio sub-interrupt + * 7 -> 8 PCI bridge errors + * 8 -> 9 PCI SCSI aic7xxx 0 + * 9 -> 10 PCI SCSI aic7xxx 1 + * 10 -> 11 PCI slot 0 + * 11 -> 12 unused (PCI slot 1) + * 12 -> 13 unused (PCI slot 2) + * 13 -> 14 unused (PCI shared 0) + * 14 -> 15 unused (PCI shared 1) + * 15 -> 16 unused (PCI shared 2) + * 16 -> 17 GBE0 (E) + * 17 -> 18 GBE1 (E) + * 18 -> 19 GBE2 (E) + * 19 -> 20 GBE3 (E) + * 20 -> 21 CPU errors + * 21 -> 22 Memory errors + * 22 -> 23 RE empty edge (E) + * 23 -> 24 RE full edge (E) + * 24 -> 25 RE idle edge (E) + * 25 -> 26 RE empty level + * 26 -> 27 RE full level + * 27 -> 28 RE idle level + * 28 -> 29 unused (software 0) (E) + * 29 -> 30 unused (software 1) (E) + * 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E) + * 31 -> 32 VICE + * + * S, M, A: Use the MACE ISA interrupt register + * MACE_ISA_INT_STAT 31:0 + * + * 0-7 -> 33-40 Audio + * 8 -> 41 RTC + * 9 -> 42 Keyboard + * 10 -> X Keyboard polled + * 11 -> 44 Mouse + * 12 -> X Mouse polled + * 13-15 -> 46-48 Count/compare timers + * 16-19 -> 49-52 Parallel (16 E) + * 20-25 -> 53-58 Serial 1 (22 E) + * 26-31 -> 59-64 Serial 2 (28 E) + * + * Note that this means IRQs 5-7, 43, and 45 do not exist. This is a + * different IRQ map than IRIX uses, but that's OK as Linux irq handling + * is quite different anyway. + */ + +/* Some initial interrupts to set up */ +extern void crime_memerr_intr (unsigned int irq, void *dev_id, + struct pt_regs *regs); +extern void crime_cpuerr_intr (unsigned int irq, void *dev_id, + struct pt_regs *regs); + +struct irqaction memerr_irq = { crime_memerr_intr, SA_INTERRUPT, + 0, "CRIME memory error", NULL, + NULL }; +struct irqaction cpuerr_irq = { crime_cpuerr_intr, SA_INTERRUPT, + 0, "CRIME CPU error", NULL, + NULL }; + +extern void ip32_handle_int (void); + +/* + * For interrupts wired from a single device to the CPU. Only the clock + * uses this it seems, which is IRQ 0 and IP7. + */ + +static void enable_cpu_irq(unsigned int irq) +{ + set_c0_status(STATUSF_IP7); +} + +static unsigned int startup_cpu_irq(unsigned int irq) +{ + enable_cpu_irq(irq); + return 0; +} + +static void disable_cpu_irq(unsigned int irq) +{ + clear_c0_status(STATUSF_IP7); +} + +static void end_cpu_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_cpu_irq (irq); +} + +#define shutdown_cpu_irq disable_cpu_irq +#define mask_and_ack_cpu_irq disable_cpu_irq + +static struct hw_interrupt_type ip32_cpu_interrupt = { + "IP32 CPU", + startup_cpu_irq, + shutdown_cpu_irq, + enable_cpu_irq, + disable_cpu_irq, + mask_and_ack_cpu_irq, + end_cpu_irq, + NULL +}; + +/* + * This is for pure CRIME interrupts - ie not MACE. The advantage? + * We get to split the register in half and do faster lookups. + */ + +static void enable_crime_irq(unsigned int irq) +{ + u64 crime_mask; + unsigned long flags; + + local_irq_save(flags); + crime_mask = crime_read_64(CRIME_INT_MASK); + crime_mask |= 1 << (irq - 1); + crime_write_64(CRIME_INT_MASK, crime_mask); + local_irq_restore(flags); +} + +static unsigned int startup_crime_irq(unsigned int irq) +{ + enable_crime_irq(irq); + return 0; /* This is probably not right; we could have pending irqs */ +} + +static void disable_crime_irq(unsigned int irq) +{ + u64 crime_mask; + unsigned long flags; + + local_irq_save(flags); + crime_mask = crime_read_64(CRIME_INT_MASK); + crime_mask &= ~(1 << (irq - 1)); + crime_write_64(CRIME_INT_MASK, crime_mask); + local_irq_restore(flags); +} + +static void mask_and_ack_crime_irq (unsigned int irq) +{ + u64 crime_mask; + unsigned long flags; + + /* Edge triggered interrupts must be cleared. */ + if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ) + || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ) + || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) { + local_irq_save(flags); + crime_mask = crime_read_64(CRIME_HARD_INT); + crime_mask &= ~(1 << (irq - 1)); + crime_write_64(CRIME_HARD_INT, crime_mask); + local_irq_restore(flags); + } + disable_crime_irq(irq); +} + +static void end_crime_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_crime_irq (irq); +} + +#define shutdown_crime_irq disable_crime_irq + +static struct hw_interrupt_type ip32_crime_interrupt = { + "IP32 CRIME", + startup_crime_irq, + shutdown_crime_irq, + enable_crime_irq, + disable_crime_irq, + mask_and_ack_crime_irq, + end_crime_irq, + NULL +}; + +/* + * This is for MACE PCI interrupts. We can decrease bus traffic by masking + * as close to the source as possible. This also means we can take the + * next chunk of the CRIME register in one piece. + */ + +static void enable_macepci_irq(unsigned int irq) +{ + u32 mace_mask; + u64 crime_mask; + unsigned long flags; + + local_irq_save(flags); + mace_mask = mace_read_32(MACEPCI_CONTROL); + mace_mask |= MACEPCI_CONTROL_INT(irq - 9); + mace_write_32(MACEPCI_CONTROL, mace_mask); + /* + * In case the CRIME interrupt isn't enabled, we must enable it; + * however, we never disable interrupts at that level. + */ + crime_mask = crime_read_64(CRIME_INT_MASK); + crime_mask |= 1 << (irq - 1); + crime_write_64(CRIME_INT_MASK, crime_mask); + local_irq_restore(flags); +} + +static unsigned int startup_macepci_irq(unsigned int irq) +{ + enable_macepci_irq (irq); + + return 0; /* XXX */ +} + +static void disable_macepci_irq(unsigned int irq) +{ + u32 mace_mask; + unsigned long flags; + + local_irq_save(flags); + mace_mask = mace_read_32(MACEPCI_CONTROL); + mace_mask &= ~MACEPCI_CONTROL_INT(irq - 9); + mace_write_32(MACEPCI_CONTROL, mace_mask); + local_irq_restore(flags); +} + +static void end_macepci_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_macepci_irq (irq); +} + +#define shutdown_macepci_irq disable_macepci_irq +#define mask_and_ack_macepci_irq disable_macepci_irq + +static struct hw_interrupt_type ip32_macepci_interrupt = { + "IP32 MACE PCI", + startup_macepci_irq, + shutdown_macepci_irq, + enable_macepci_irq, + disable_macepci_irq, + mask_and_ack_macepci_irq, + end_macepci_irq, + NULL +}; + +/* This is used for MACE ISA interrupts. That means bits 4-6 in the + * CRIME register. + */ + +static void enable_maceisa_irq (unsigned int irq) +{ + u64 crime_mask; + u32 mace_mask; + unsigned int crime_int = 0; + unsigned long flags; + + DBG ("maceisa enable: %u\n", irq); + + switch (irq) { + case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: + crime_int = MACE_AUDIO_INT; + break; + case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ: + crime_int = MACE_MISC_INT; + break; + case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ: + crime_int = MACE_SUPERIO_INT; + break; + } + DBG ("crime_int %016lx enabled\n", crime_int); + local_irq_save(flags); + crime_mask = crime_read_64(CRIME_INT_MASK); + crime_mask |= crime_int; + crime_write_64(CRIME_INT_MASK, crime_mask); + mace_mask = mace_read_32(MACEISA_INT_MASK); + mace_mask |= 1 << (irq - 33); + mace_write_32(MACEISA_INT_MASK, mace_mask); + local_irq_restore(flags); +} + +static unsigned int startup_maceisa_irq (unsigned int irq) +{ + enable_maceisa_irq(irq); + return 0; +} + +static void disable_maceisa_irq(unsigned int irq) +{ + u32 mace_mask; + unsigned long flags; + + local_irq_save(flags); + mace_mask = mace_read_32(MACEISA_INT_MASK); + mace_mask &= ~(1 << (irq - 33)); + mace_write_32(MACEISA_INT_MASK, mace_mask); + local_irq_restore(flags); +} + +static void mask_and_ack_maceisa_irq(unsigned int irq) +{ + u32 mace_mask; + unsigned long flags; + + switch (irq) { + case MACEISA_PARALLEL_IRQ: + case MACEISA_SERIAL1_TDMAPR_IRQ: + case MACEISA_SERIAL2_TDMAPR_IRQ: + local_irq_save(flags); + mace_mask = mace_read_32(MACEISA_INT_STAT); + mace_mask &= ~(1 << (irq - 33)); + mace_write_32(MACEISA_INT_STAT, mace_mask); + local_irq_restore(flags); + break; + } + disable_maceisa_irq(irq); +} + +static void end_maceisa_irq(unsigned irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_maceisa_irq (irq); +} + +#define shutdown_maceisa_irq disable_maceisa_irq + +static struct hw_interrupt_type ip32_maceisa_interrupt = { + "IP32 MACE ISA", + startup_maceisa_irq, + shutdown_maceisa_irq, + enable_maceisa_irq, + disable_maceisa_irq, + mask_and_ack_maceisa_irq, + end_maceisa_irq, + NULL +}; + +/* This is used for regular non-ISA, non-PCI MACE interrupts. That means + * bits 0-3 and 7 in the CRIME register. + */ + +static void enable_mace_irq(unsigned int irq) +{ + u64 crime_mask; + unsigned long flags; + + local_irq_save(flags); + crime_mask = crime_read_64 (CRIME_INT_MASK); + crime_mask |= 1 << (irq - 1); + crime_write_64 (CRIME_INT_MASK, crime_mask); + local_irq_restore (flags); +} + +static unsigned int startup_mace_irq(unsigned int irq) +{ + enable_mace_irq(irq); + return 0; +} + +static void disable_mace_irq(unsigned int irq) +{ + u64 crime_mask; + unsigned long flags; + + local_irq_save(flags); + crime_mask = crime_read_64 (CRIME_INT_MASK); + crime_mask &= ~(1 << (irq - 1)); + crime_write_64 (CRIME_INT_MASK, crime_mask); + local_irq_restore(flags); +} + +static void end_mace_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_mace_irq (irq); +} + +#define shutdown_mace_irq disable_mace_irq +#define mask_and_ack_mace_irq disable_mace_irq + +static struct hw_interrupt_type ip32_mace_interrupt = { + "IP32 MACE", + startup_mace_irq, + shutdown_mace_irq, + enable_mace_irq, + disable_mace_irq, + mask_and_ack_mace_irq, + end_mace_irq, + NULL +}; + +static void ip32_unknown_interrupt (struct pt_regs *regs) +{ + u64 crime; + u32 mace; + + printk ("Unknown interrupt occurred!\n"); + printk ("cp0_status: %08x\tcp0_cause: %08x\n", + read_c0_status(), + read_c0_cause()); + crime = crime_read_64 (CRIME_INT_MASK); + printk ("CRIME interrupt mask: %016lx\n", crime); + crime = crime_read_64 (CRIME_INT_STAT); + printk ("CRIME interrupt status: %016lx\n", crime); + crime = crime_read_64 (CRIME_HARD_INT); + printk ("CRIME hardware interrupt register: %016lx\n", crime); + mace = mace_read_32 (MACEISA_INT_MASK); + printk ("MACE ISA interrupt mask: %08x\n", mace); + mace = mace_read_32 (MACEISA_INT_STAT); + printk ("MACE ISA interrupt status: %08x\n", mace); + mace = mace_read_32 (MACEPCI_CONTROL); + printk ("MACE PCI control register: %08x\n", mace); + + printk("Register dump:\n"); + show_regs(regs); + + printk("Please mail this report to linux-mips@oss.sgi.com\n"); + printk("Spinning..."); + while(1) ; +} + +/* CRIME 1.1 appears to deliver all interrupts to this one pin. */ +void ip32_irq0(struct pt_regs *regs) +{ + u64 crime_int; + u64 crime_mask; + int irq = 0; + unsigned long flags; + + local_irq_save(flags); + /* disable crime interrupts */ + crime_mask = crime_read_64(CRIME_INT_MASK); + crime_write_64(CRIME_INT_MASK, 0); + + crime_int = crime_read_64(CRIME_INT_STAT); + + if (crime_int & CRIME_MACE_INT_MASK) { + crime_int &= CRIME_MACE_INT_MASK; + irq = ffs (crime_int); + } else if (crime_int & CRIME_MACEISA_INT_MASK) { + u32 mace_int; + mace_int = mace_read_32 (MACEISA_INT_STAT); + if (mace_int == 0) + irq = 0; + else + irq = ffs (mace_int) + 32; + } else if (crime_int & CRIME_MACEPCI_INT_MASK) { + crime_int &= CRIME_MACEPCI_INT_MASK; + crime_int >>= 8; + irq = ffs (crime_int) + 8; + } else if (crime_int & 0xffff0000) { + crime_int >>= 16; + irq = ffs (crime_int) + 16; + } + if (irq == 0) + ip32_unknown_interrupt(regs); + DBG("*irq %u*\n", irq); + do_IRQ(irq, regs); + + /* enable crime interrupts */ + crime_write_64(CRIME_INT_MASK, crime_mask); + local_irq_restore (flags); +} + +void ip32_irq1(struct pt_regs *regs) +{ + ip32_unknown_interrupt (regs); +} + +void ip32_irq2(struct pt_regs *regs) +{ + ip32_unknown_interrupt (regs); +} + +void ip32_irq3(struct pt_regs *regs) +{ + ip32_unknown_interrupt (regs); +} + +void ip32_irq4(struct pt_regs *regs) +{ + ip32_unknown_interrupt (regs); +} + +void ip32_irq5(struct pt_regs *regs) +{ + do_IRQ (CLOCK_IRQ, regs); +} + +void __init init_IRQ(void) +{ + unsigned int irq; + int i; + + /* Install our interrupt handler, then clear and disable all + * CRIME and MACE interrupts. + */ + crime_write_64(CRIME_INT_MASK, 0); + crime_write_64(CRIME_HARD_INT, 0); + crime_write_64(CRIME_SOFT_INT, 0); + mace_write_32(MACEISA_INT_STAT, 0); + mace_write_32(MACEISA_INT_MASK, 0); + set_except_vector(0, ip32_handle_int); + + for (i = 0; i < NR_IRQS; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].handler = &no_irq_type; + } + + for (irq = 0; irq <= IP32_IRQ_MAX; irq++) { + hw_irq_controller *controller; + + if (irq == CLOCK_IRQ) + controller = &ip32_cpu_interrupt; + else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ) + controller = &ip32_mace_interrupt; + else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ) + controller = &ip32_macepci_interrupt; + else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ) + controller = &ip32_crime_interrupt; + else + controller = &ip32_maceisa_interrupt; + + irq_desc[irq].status = IRQ_DISABLED; + irq_desc[irq].action = 0; + irq_desc[irq].depth = 0; + irq_desc[irq].handler = controller; + } + setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); + setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip32/ip32-irq-glue.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,87 @@ +/* + * Low level interrupt handler for the SGI O2 aka IP32 aka Moosehead + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Harald Koerfgen + * Copyright (C) 2001 Keith M Wesolowski + */ +#include +#include +#include +#include +#include +#include + + .text + .set noreorder + .set noat + .align 5 + NESTED(ip32_handle_int, PT_SIZE, ra) + .set noat + SAVE_ALL + CLI # TEST: interrupts should be off + .set at + .set noreorder + + mfc0 s0,CP0_CAUSE + + andi t1, s0, IE_IRQ0 + bnez t1, handle_irq0 + andi t1, s0, IE_IRQ1 + bnez t1, handle_irq1 + andi t1, s0, IE_IRQ2 + bnez t1, handle_irq2 + andi t1, s0, IE_IRQ3 + bnez t1, handle_irq3 + andi t1, s0, IE_IRQ4 + bnez t1, handle_irq4 + andi t1, s0, IE_IRQ5 + bnez t1, handle_irq5 + nop + + /* Either someone has triggered the "software interrupts" + * or we lost an interrupt somehow. Ignore it. + */ + j ret_from_irq + nop + +handle_irq0: + jal ip32_irq0 + move a0, sp + j ret_from_irq + nop + +handle_irq1: + jal ip32_irq1 + move a0, sp + j ret_from_irq + nop + +handle_irq2: + jal ip32_irq2 + move a0, sp + j ret_from_irq + nop + +handle_irq3: + jal ip32_irq3 + move a0, sp + j ret_from_irq + nop + +handle_irq4: + jal ip32_irq4 + move a0, sp + j ret_from_irq + nop + +handle_irq5: + jal ip32_irq5 + move a0, sp + j ret_from_irq + nop + + END(ip32_handle_int) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip32/ip32-reset.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,208 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2001 Keith M Wesolowski + * Copyright (C) 2001 Paul Mundt + * Copyright (C) 2003 Guido Guenther + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#define POWERDOWN_TIMEOUT 120 +/* + * Blink frequency during reboot grace period and when paniced. + */ +#define POWERDOWN_FREQ (HZ / 4) +#define PANIC_FREQ (HZ / 8) + +static struct timer_list power_timer, blink_timer, debounce_timer; +static int shuting_down = 0, has_paniced = 0; + +static void ip32_machine_restart(char *command) __attribute__((noreturn)); +static void ip32_machine_halt(void) __attribute__((noreturn)); +static void ip32_machine_power_off(void) __attribute__((noreturn)); + +static void ip32_machine_restart(char *cmd) +{ + if (shuting_down) + ip32_machine_power_off(); + ArcReboot(); +} + +static inline void ip32_machine_halt(void) +{ + if (shuting_down) + ip32_machine_power_off(); + ArcEnterInteractiveMode(); +} + +static void ip32_machine_power_off(void) +{ + volatile unsigned char reg_a, xctrl_a, xctrl_b; + + disable_irq(MACEISA_RTC_IRQ); + reg_a = CMOS_READ(RTC_REG_A); + + /* setup for kickstart & wake-up (DS12287 Ref. Man. p. 19) */ + reg_a &= ~DS_REGA_DV2; + reg_a |= DS_REGA_DV1; + + CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A); + wbflush(); + xctrl_b = CMOS_READ(DS_B1_XCTRL4B) + | DS_XCTRL4B_ABE | DS_XCTRL4B_KFE; + CMOS_WRITE(xctrl_b, DS_B1_XCTRL4B); + xctrl_a = CMOS_READ(DS_B1_XCTRL4A) & ~DS_XCTRL4A_IFS; + CMOS_WRITE(xctrl_a, DS_B1_XCTRL4A); + wbflush(); + /* adios amigos... */ + CMOS_WRITE(xctrl_a | DS_XCTRL4A_PAB, DS_B1_XCTRL4A); + CMOS_WRITE(reg_a, RTC_REG_A); + wbflush(); + + while(1) { + printk(KERN_DEBUG "Power off!\n"); + } +} + +static void power_timeout(unsigned long data) +{ + ip32_machine_power_off(); +} + +static void blink_timeout(unsigned long data) +{ + u64 mc_led = mace_read_64(MACEISA_FLASH_NIC_REG); + + mc_led ^= MACEISA_LED_RED; + mace_write_64(MACEISA_FLASH_NIC_REG, mc_led); + mod_timer(&blink_timer, jiffies+data); +} + +static void debounce(unsigned long data) +{ + volatile unsigned char reg_a,reg_c,xctrl_a; + + reg_c = CMOS_READ(RTC_INTR_FLAGS); + CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A); + wbflush(); + xctrl_a = CMOS_READ(DS_B1_XCTRL4A); + if( (xctrl_a & DS_XCTRL4A_IFS ) || ( reg_c & RTC_IRQF ) ) { + /* Interrupt still being sent. */ + debounce_timer.expires = jiffies + 50; + add_timer(&debounce_timer); + + /* clear interrupt source */ + CMOS_WRITE( xctrl_a & ~DS_XCTRL4A_IFS, DS_B1_XCTRL4A); + CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A); + return; + } + CMOS_WRITE(reg_a & ~DS_REGA_DV0, RTC_REG_A); + + if (has_paniced) + ArcReboot(); + + enable_irq(MACEISA_RTC_IRQ); +} + +static inline void ip32_power_button(void) +{ + if (has_paniced) + return; + + if (shuting_down || kill_proc(1, SIGINT, 1)) { + /* No init process or button pressed twice. */ + ip32_machine_power_off(); + } + + shuting_down = 1; + blink_timer.data = POWERDOWN_FREQ; + blink_timeout(POWERDOWN_FREQ); + + init_timer(&power_timer); + power_timer.function = power_timeout; + power_timer.expires = jiffies + POWERDOWN_TIMEOUT * HZ; + add_timer(&power_timer); +} + +static void ip32_rtc_int(int irq, void *dev_id, struct pt_regs *regs) +{ + volatile unsigned char reg_c; + + reg_c = CMOS_READ(RTC_INTR_FLAGS); + if( ! (reg_c & RTC_IRQF) ) { + printk(KERN_WARNING + "%s: RTC IRQ without RTC_IRQF\n", __FUNCTION__); + } + /* Wait until interrupt goes away */ + disable_irq(MACEISA_RTC_IRQ); + init_timer(&debounce_timer); + debounce_timer.function = debounce; + debounce_timer.expires = jiffies + 50; + add_timer(&debounce_timer); + + printk(KERN_DEBUG "Power button pressed\n"); + ip32_power_button(); +} + +static int panic_event(struct notifier_block *this, unsigned long event, + void *ptr) +{ + u64 mc_led; + + if (has_paniced) + return NOTIFY_DONE; + has_paniced = 1; + + /* turn off the green LED */ + mc_led = mace_read_64(MACEISA_FLASH_NIC_REG); + mc_led |= MACEISA_LED_GREEN; + mace_write_64(MACEISA_FLASH_NIC_REG, mc_led); + + blink_timer.data = PANIC_FREQ; + blink_timeout(PANIC_FREQ); + + return NOTIFY_DONE; +} + +static struct notifier_block panic_block = { + .notifier_call = panic_event, +}; + +static __init int ip32_reboot_setup(void) +{ + u64 mc_led = mace_read_64(MACEISA_FLASH_NIC_REG); + + _machine_restart = ip32_machine_restart; + _machine_halt = ip32_machine_halt; + _machine_power_off = ip32_machine_power_off; + request_irq(MACEISA_RTC_IRQ, ip32_rtc_int, 0, "rtc", NULL); + init_timer(&blink_timer); + blink_timer.function = blink_timeout; + notifier_chain_register(&panic_notifier_list, &panic_block); + + /* turn on the green led only */ + mc_led |= MACEISA_LED_RED; + mc_led &= ~MACEISA_LED_GREEN; + mace_write_64(MACEISA_FLASH_NIC_REG, mc_led); + + return 0; +} + +subsys_initcall(ip32_reboot_setup); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip32/ip32-rtc.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,32 @@ +/* + * RTC routines for IP32 style attached Dallas chip. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Harald Koerfgen + */ +#include +#include + +static unsigned char ip32_rtc_read_data(unsigned long addr) +{ + return (unsigned char) mace_read_8 (MACEISA_RTC_BASE + (addr << 8)); +} + +static void ip32_rtc_write_data(unsigned char data, unsigned long addr) +{ + mace_write_8 (MACEISA_RTC_BASE + (addr << 8), data); +} + +static int ip32_rtc_bcd_mode(void) +{ + return 0; +} + +struct rtc_ops ip32_rtc_ops = { + &ip32_rtc_read_data, + &ip32_rtc_write_data, + &ip32_rtc_bcd_mode +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip32/ip32-setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,105 @@ +/* + * IP32 basic setup + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Harald Koerfgen + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern struct rtc_ops ip32_rtc_ops; +extern u32 cc_interval; + +#ifdef CONFIG_SGI_O2MACE_ETH + +/* + * This is taken care of in here 'cause they say using Arc later on is + * problematic + */ +extern char o2meth_eaddr[8]; +static inline unsigned char str2hexnum(unsigned char c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + return 0; /* foo */ +} + +static inline void str2eaddr(unsigned char *ea, unsigned char *str) +{ + int i; + + for (i = 0; i < 6; i++) { + unsigned char num; + + if(*str == ':') + str++; + num = str2hexnum(*str++) << 4; + num |= (str2hexnum(*str++)); + ea[i] = num; + } +} +#endif + +extern void ip32_time_init(void); +extern void ip32_reboot_setup(void); + +void __init ip32_setup(void) +{ +#ifdef CONFIG_SERIAL_CONSOLE + char *ctype; +#endif + TLBMISS_HANDLER_SETUP (); + + mips_io_port_base = UNCACHEDADDR(MACEPCI_HI_IO);; + +#ifdef CONFIG_SERIAL_CONSOLE + ctype = ArcGetEnvironmentVariable("console"); + if (*ctype == 'd') { + if (ctype[1] == '2') + console_setup ("ttyS1"); + else + console_setup ("ttyS0"); + } +#endif +#ifdef CONFIG_SGI_O2MACE_ETH + { + char *mac=ArcGetEnvironmentVariable("eaddr"); + str2eaddr(o2meth_eaddr, mac); + } +#endif + +#ifdef CONFIG_VT + conswitchp = &dummy_con; +#endif + + rtc_ops = &ip32_rtc_ops; + board_be_init = ip32_be_init; + board_time_init = ip32_time_init; + + crime_init (); +} + +int __init page_is_ram (unsigned long pagenr) +{ + /* XXX: to do? */ + return 1; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip32/ip32-timer.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,238 @@ +/* + * IP32 timer calibration + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2001 Keith M Wesolowski + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern volatile unsigned long wall_jiffies; + +u32 cc_interval; + +/* Cycle counter value at the previous timer interrupt.. */ +static unsigned int timerhi, timerlo; + +/* An arbitrary time; this can be decreased if reliability looks good */ +#define WAIT_MS 10 +#define PER_MHZ (1000000 / 2 / HZ) +/* + * Change this if you have some constant time drift + */ +#define USECS_PER_JIFFY (1000000/HZ) + + +void __init ip32_timer_setup (struct irqaction *irq) +{ + u64 crime_time; + u32 cc_tick; + + printk("Calibrating system timer... "); + + crime_time = crime_read_64 (CRIME_TIME) & CRIME_TIME_MASK; + cc_tick = read_c0_count(); + + while ((crime_read_64 (CRIME_TIME) & CRIME_TIME_MASK) - crime_time + < WAIT_MS * 1000000 / CRIME_NS_PER_TICK) + ; + cc_tick = read_c0_count() - cc_tick; + cc_interval = cc_tick / HZ * (1000 / WAIT_MS); + /* The round-off seems unnecessary; in testing, the error of the + * above procedure is < 100 ticks, which means it gets filtered + * out by the HZ adjustment. + */ + cc_interval = (cc_interval / PER_MHZ) * PER_MHZ; + + printk("%d MHz CPU detected\n", (int) (cc_interval / PER_MHZ)); + + setup_irq (CLOCK_IRQ, irq); +} + +struct irqaction irq0 = { NULL, SA_INTERRUPT, 0, + "timer", NULL, NULL}; + +void cc_timer_interrupt(int irq, void *dev_id, struct pt_regs * regs) +{ + u32 count; + + /* + * The cycle counter is only 32 bit which is good for about + * a minute at current count rates of upto 150MHz or so. + */ + count = read_c0_count(); + timerhi += (count < timerlo); /* Wrap around */ + timerlo = count; + + write_c0_compare( + (u32) (count + cc_interval)); + kstat_cpu(0).irqs[irq]++; + do_timer (regs); + + if (!jiffies) + { + /* + * If jiffies has overflowed in this timer_interrupt we must + * update the timer[hi]/[lo] to make do_fast_gettimeoffset() + * quotient calc still valid. -arca + */ + timerhi = timerlo = 0; + } +} + +/* + * On MIPS only R4000 and better have a cycle counter. + * + * FIXME: Does playing with the RP bit in c0_status interfere with this code? + */ +static unsigned long do_gettimeoffset(void) +{ + u32 count; + unsigned long res, tmp; + + /* Last jiffy when do_fast_gettimeoffset() was called. */ + static unsigned long last_jiffies; + u32 quotient; + + /* + * Cached "1/(clocks per usec)*2^32" value. + * It has to be recalculated once each jiffy. + */ + static u32 cached_quotient; + + tmp = jiffies; + + quotient = cached_quotient; + + if (tmp && last_jiffies != tmp) { + last_jiffies = tmp; + __asm__(".set\tnoreorder\n\t" + ".set\tnoat\n\t" + ".set\tmips3\n\t" + "lwu\t%0,%2\n\t" + "dsll32\t$1,%1,0\n\t" + "or\t$1,$1,%0\n\t" + "ddivu\t$0,$1,%3\n\t" + "mflo\t$1\n\t" + "dsll32\t%0,%4,0\n\t" + "nop\n\t" + "ddivu\t$0,%0,$1\n\t" + "mflo\t%0\n\t" + ".set\tmips0\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=&r" (quotient) + :"r" (timerhi), + "m" (timerlo), + "r" (tmp), + "r" (USECS_PER_JIFFY) + :"$1"); + cached_quotient = quotient; + } + + /* Get last timer tick in absolute kernel time */ + count = read_c0_count(); + + /* .. relative to previous jiffy (32 bits is enough) */ + count -= timerlo; + + __asm__("multu\t%1,%2\n\t" + "mfhi\t%0" + :"=r" (res) + :"r" (count), + "r" (quotient)); + + /* + * Due to possible jiffies inconsistencies, we need to check + * the result so that we'll get a timer that is monotonic. + */ + if (res >= USECS_PER_JIFFY) + res = USECS_PER_JIFFY-1; + + return res; +} + +void __init ip32_time_init(void) +{ + unsigned int epoch = 0, year, mon, day, hour, min, sec; + int i; + + /* The Linux interpretation of the CMOS clock register contents: + * When the Update-In-Progress (UIP) flag goes from 1 to 0, the + * RTC registers show the second which has precisely just started. + * Let's hope other operating systems interpret the RTC the same way. + */ + /* read RTC exactly on falling edge of update flag */ + for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */ + if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP) + break; + for (i = 0 ; i < 1000000 ; i++) /* must try at least 2.228 ms */ + if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)) + break; + do { /* Isn't this overkill ? UIP above should guarantee consistency */ + sec = CMOS_READ(RTC_SECONDS); + min = CMOS_READ(RTC_MINUTES); + hour = CMOS_READ(RTC_HOURS); + day = CMOS_READ(RTC_DAY_OF_MONTH); + mon = CMOS_READ(RTC_MONTH); + year = CMOS_READ(RTC_YEAR); + } while (sec != CMOS_READ(RTC_SECONDS)); + if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { + sec = BCD2BIN(sec); + min = BCD2BIN(min); + hour = BCD2BIN(hour); + day = BCD2BIN(day); + mon = BCD2BIN(mon); + year = BCD2BIN(year); + } + + /* Attempt to guess the epoch. This is the same heuristic as in + * rtc.c so no stupid things will happen to timekeeping. Who knows, + * maybe Ultrix also uses 1952 as epoch ... + */ + if (year > 10 && year < 44) + epoch = 1980; + else if (year < 96) + epoch = 1952; + year += epoch; + + write_seqlock_irq(&xtime_lock); + xtime.tv_sec = mktime(year, mon, day, hour, min, sec); + xtime.tv_nsec = 0; + write_sequnlock_irq(&xtime_lock); + + write_c0_count(0); + irq0.handler = cc_timer_interrupt; + + ip32_timer_setup (&irq0); + +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) + /* Set ourselves up for future interrupts */ + write_c0_compare( + read_c0_count() + + cc_interval); + change_c0_status(ST0_IM, ALLINTS); + sti (); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sgi-ip32/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,9 @@ +# +# Makefile for the SGI specific kernel interface routines +# under Linux. +# + +obj-y += ip32-berr.o ip32-rtc.o ip32-setup.o ip32-irq.o ip32-irq-glue.o \ + ip32-timer.o crime.o ip32-reset.o + +EXTRA_AFLAGS := $(CFLAGS) --- linux-2.5.73/arch/mips/sgi/kernel/indy_hpc.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,106 +0,0 @@ -/* $Id: indy_hpc.c,v 1.9 1999/12/04 03:59:00 ralf Exp $ - * - * indy_hpc.c: Routines for generic manipulation of the HPC controllers. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1998 Ralf Baechle - */ -#include -#include - -#include -#include -#include -#include -#include - -/* #define DEBUG_SGIHPC */ - -struct hpc3_regs *hpc3c0, *hpc3c1; -struct hpc3_miscregs *hpc3mregs; - -/* We need software copies of these because they are write only. */ -unsigned int sgi_hpc_write1, sgi_hpc_write2; - -/* Machine specific identifier knobs. */ -int sgi_has_ioc2 = 0; -int sgi_guiness = 0; -int sgi_boardid; - -void __init sgihpc_init(void) -{ - unsigned long sid, crev, brev; - - hpc3c0 = (struct hpc3_regs *) (KSEG1 + HPC3_CHIP0_PBASE); - hpc3c1 = (struct hpc3_regs *) (KSEG1 + HPC3_CHIP1_PBASE); - hpc3mregs = (struct hpc3_miscregs *) (KSEG1 + HPC3_MREGS_PBASE); - sid = hpc3mregs->sysid; - - sid &= 0xff; - crev = (sid & 0xe0) >> 5; - brev = (sid & 0x1e) >> 1; - -#ifdef DEBUG_SGIHPC - prom_printf("sgihpc_init: crev<%2x> brev<%2x>\n", crev, brev); - prom_printf("sgihpc_init: "); -#endif - - /* This test works now thanks to William J. Earl */ - if ((sid & 1) == 0 ) { -#ifdef DEBUG_SGIHPC - prom_printf("GUINESS "); -#endif - sgi_guiness = 1; - mips_machtype = MACH_SGI_INDY; - } else { -#ifdef DEBUG_SGIHPC - prom_printf("FULLHOUSE "); -#endif - mips_machtype = MACH_SGI_INDIGO2; - sgi_guiness = 0; - } - sgi_boardid = brev; - -#ifdef DEBUG_SGIHPC - prom_printf("sgi_boardid<%d> ", sgi_boardid); -#endif - - if(crev == 1) { - if((sid & 1) || (brev >= 2)) { -#ifdef DEBUG_SGIHPC - prom_printf("IOC2 "); -#endif - sgi_has_ioc2 = 1; - } else { -#ifdef DEBUG_SGIHPC - prom_printf("IOC1 revision 1 "); -#endif - } - } else { -#ifdef DEBUG_SGIHPC - prom_printf("IOC1 revision 0 "); -#endif - } -#ifdef DEBUG_SGIHPC - prom_printf("\n"); -#endif - - sgi_hpc_write1 = (HPC3_WRITE1_PRESET | - HPC3_WRITE1_KMRESET | - HPC3_WRITE1_ERESET | - HPC3_WRITE1_LC0OFF); - - sgi_hpc_write2 = (HPC3_WRITE2_EASEL | - HPC3_WRITE2_NTHRESH | - HPC3_WRITE2_TPSPEED | - HPC3_WRITE2_EPSEL | - HPC3_WRITE2_U0AMODE | - HPC3_WRITE2_U1AMODE); - - if(!sgi_guiness) - sgi_hpc_write1 |= HPC3_WRITE1_GRESET; - hpc3mregs->write1 = sgi_hpc_write1; - hpc3mregs->write2 = sgi_hpc_write2; - - hpc3c0->pbus_piocfgs[0][6] |= HPC3_PIOPCFG_HW; -} --- linux-2.5.73/arch/mips/sgi/kernel/indy_int.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,528 +0,0 @@ -/* - * indy_int.c: Routines for generic manipulation of the INT[23] ASIC - * found on INDY workstations.. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org) - * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - * - Indigo2 changes - * - Interrupt handling fixes - */ -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -/* - * Linux has a controller-independent x86 interrupt architecture. - * every controller has a 'controller-template', that is used - * by the main code to do the right thing. Each driver-visible - * interrupt source is transparently wired to the apropriate - * controller. Thus drivers need not be aware of the - * interrupt-controller. - * - * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC, - * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC. - * (IO-APICs assumed to be messaging to Pentium local-APICs) - * - * the code is designed to be easily extended with new/different - * interrupt controllers, without having to do assembly magic. - */ - -/* #define DEBUG_SGINT */ - -struct sgi_int2_regs *sgi_i2regs; -struct sgi_int3_regs *sgi_i3regs; -struct sgi_ioc_ints *ioc_icontrol; -struct sgi_ioc_timers *ioc_timers; -volatile unsigned char *ioc_tclear; - -static char lc0msk_to_irqnr[256]; -static char lc1msk_to_irqnr[256]; -static char lc2msk_to_irqnr[256]; -static char lc3msk_to_irqnr[256]; - -extern asmlinkage void indyIRQ(void); - -/* Local IRQ's are layed out logically like this: - * - * 0 --> 7 == local 0 interrupts - * 8 --> 15 == local 1 interrupts - * 16 --> 23 == vectored level 2 interrupts - * 24 --> 31 == vectored level 3 interrupts (not used) - */ -static void enable_local0_irq(unsigned int irq) -{ - unsigned long flags; - - save_and_cli(flags); - ioc_icontrol->imask0 |= (1 << (irq - SGINT_LOCAL0)); - restore_flags(flags); -} - -static unsigned int startup_local0_irq(unsigned int irq) -{ - enable_local0_irq(irq); - - return 0; /* Never anything pending */ -} - -static void disable_local0_irq(unsigned int irq) -{ - unsigned long flags; - - save_and_cli(flags); - ioc_icontrol->imask0 &= ~(1 << (irq - SGINT_LOCAL0)); - restore_flags(flags); -} - -#define shutdown_local0_irq disable_local0_irq -#define mask_and_ack_local0_irq disable_local0_irq - -static void end_local0_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_local0_irq(irq); -} - -static struct hw_interrupt_type ip22_local0_irq_type = { - "IP22 local 0", - startup_local0_irq, - shutdown_local0_irq, - enable_local0_irq, - disable_local0_irq, - mask_and_ack_local0_irq, - end_local0_irq, - NULL -}; - -static void enable_local1_irq(unsigned int irq) -{ - unsigned long flags; - - save_and_cli(flags); - ioc_icontrol->imask1 |= (1 << (irq - SGINT_LOCAL1)); - restore_flags(flags); -} - -static unsigned int startup_local1_irq(unsigned int irq) -{ - enable_local1_irq(irq); - - return 0; /* Never anything pending */ -} - -void disable_local1_irq(unsigned int irq) -{ - unsigned long flags; - - save_and_cli(flags); - ioc_icontrol->imask1 &= ~(1 << (irq- SGINT_LOCAL1)); - restore_flags(flags); -} - -#define shutdown_local1_irq disable_local1_irq -#define mask_and_ack_local1_irq disable_local1_irq - -static void end_local1_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_local1_irq(irq); -} - -static struct hw_interrupt_type ip22_local1_irq_type = { - "IP22 local 1", - startup_local1_irq, - shutdown_local1_irq, - enable_local1_irq, - disable_local1_irq, - mask_and_ack_local1_irq, - end_local1_irq, - NULL -}; - -static void enable_local2_irq(unsigned int irq) -{ - unsigned long flags; - - save_and_cli(flags); - enable_local0_irq(7); - ioc_icontrol->cmeimask0 |= (1 << (irq - SGINT_LOCAL2)); - restore_flags(flags); -} - -static unsigned int startup_local2_irq(unsigned int irq) -{ - enable_local2_irq(irq); - - return 0; /* Never anything pending */ -} - -void disable_local2_irq(unsigned int irq) -{ - unsigned long flags; - - save_and_cli(flags); - ioc_icontrol->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2)); - restore_flags(flags); -} - -#define shutdown_local2_irq disable_local2_irq -#define mask_and_ack_local2_irq disable_local2_irq - -static void end_local2_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_local2_irq(irq); -} - -static struct hw_interrupt_type ip22_local2_irq_type = { - "IP22 local 2", - startup_local2_irq, - shutdown_local2_irq, - enable_local2_irq, - disable_local2_irq, - mask_and_ack_local2_irq, - end_local2_irq, - NULL -}; - -static void enable_local3_irq(unsigned int irq) -{ - unsigned long flags; - - save_and_cli(flags); - printk("Yeeee, got passed irq_nr %d at enable_local3_irq\n", irq); - panic("INVALID IRQ level!"); - restore_flags(flags); -} - -static unsigned int startup_local3_irq(unsigned int irq) -{ - enable_local3_irq(irq); - - return 0; /* Never anything pending */ -} - -void disable_local3_irq(unsigned int irq) -{ - unsigned long flags; - - save_and_cli(flags); - /* - * This way we'll see if anyone would ever want vectored level 3 - * interrupts. Highly unlikely. - */ - printk("Yeeee, got passed irq_nr %d at disable_local3_irq\n", irq); - panic("INVALID IRQ level!"); - restore_flags(flags); -} - -#define shutdown_local3_irq disable_local3_irq -#define mask_and_ack_local3_irq disable_local3_irq - -static void end_local3_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_local3_irq(irq); -} - -static struct hw_interrupt_type ip22_local3_irq_type = { - "IP22 local 3", - startup_local3_irq, - shutdown_local3_irq, - enable_local3_irq, - disable_local3_irq, - mask_and_ack_local3_irq, - end_local3_irq, - NULL -}; - -void enable_gio_irq(unsigned int irq) -{ - /* XXX TODO XXX */ -} - -static unsigned int startup_gio_irq(unsigned int irq) -{ - enable_gio_irq(irq); - - return 0; /* Never anything pending */ -} - -void disable_gio_irq(unsigned int irq) -{ - /* XXX TODO XXX */ -} - -#define shutdown_gio_irq disable_gio_irq -#define mask_and_ack_gio_irq disable_gio_irq - -static void end_gio_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_gio_irq(irq); -} - -static struct hw_interrupt_type ip22_gio_irq_type = { - "IP22 GIO", - startup_gio_irq, - shutdown_gio_irq, - enable_gio_irq, - disable_gio_irq, - mask_and_ack_gio_irq, - end_gio_irq, - NULL -}; - -void enable_hpcdma_irq(unsigned int irq) -{ - /* XXX TODO XXX */ -} - -static unsigned int startup_hpcdma_irq(unsigned int irq) -{ - enable_hpcdma_irq(irq); - - return 0; /* Never anything pending */ -} - -void disable_hpcdma_irq(unsigned int irq) -{ - /* XXX TODO XXX */ -} - -#define shutdown_hpcdma_irq disable_hpcdma_irq -#define mask_and_ack_hpcdma_irq disable_hpcdma_irq - -static void end_hpcdma_irq (unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_hpcdma_irq(irq); -} - -static struct hw_interrupt_type ip22_hpcdma_irq_type = { - "IP22 HPC DMA", - startup_hpcdma_irq, - shutdown_hpcdma_irq, - enable_hpcdma_irq, - disable_hpcdma_irq, - mask_and_ack_hpcdma_irq, - end_hpcdma_irq, - NULL -}; - -static struct irqaction r4ktimer_action = { - NULL, 0, 0, "R4000 timer/counter", NULL, NULL, -}; - -static struct irqaction indy_berr_action = { - NULL, 0, 0, "IP22 Bus Error", NULL, NULL, -}; - -static struct irqaction *irq_action[16] = { - NULL, NULL, NULL, NULL, - NULL, NULL, &indy_berr_action, &r4ktimer_action, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL -}; - -void indy_local0_irqdispatch(struct pt_regs *regs) -{ - unsigned char mask = ioc_icontrol->istat0; - unsigned char mask2 = 0; - int irq; - - mask &= ioc_icontrol->imask0; - if (mask & ISTAT0_LIO2) { - mask2 = ioc_icontrol->vmeistat; - mask2 &= ioc_icontrol->cmeimask0; - irq = lc2msk_to_irqnr[mask2]; - } else { - irq = lc0msk_to_irqnr[mask]; - } - - /* if irq == 0, then the interrupt has already been cleared */ - if (irq == 0) - goto end; - - do_IRQ(irq, regs); - goto end; - -no_handler: - printk("No handler for local0 irq: %i\n", irq); - -end: - return; -} - -void indy_local1_irqdispatch(struct pt_regs *regs) -{ - unsigned char mask = ioc_icontrol->istat1; - unsigned char mask2 = 0; - int irq; - - mask &= ioc_icontrol->imask1; - if (mask & ISTAT1_LIO3) { - printk("WHee: Got an LIO3 irq, winging it...\n"); - mask2 = ioc_icontrol->vmeistat; - mask2 &= ioc_icontrol->cmeimask1; - irq = lc3msk_to_irqnr[ioc_icontrol->vmeistat]; - } else { - irq = lc1msk_to_irqnr[mask]; - } - - /* if irq == 0, then the interrupt has already been cleared */ - /* not sure if it is needed here, but it is needed for local0 */ - if (irq == 0) - goto end; - - do_IRQ(irq, regs); - goto end; - -no_handler: - printk("No handler for local1 irq: %i\n", irq); - -end: - return; -} - -void indy_buserror_irq(struct pt_regs *regs) -{ - int cpu = smp_processor_id(); - int irq = 6; - - irq_enter(cpu, irq); - kstat_cpu(0).irqs[irq]++; - printk("Got a bus error IRQ, shouldn't happen yet\n"); - show_regs(regs); - printk("Spinning...\n"); - while(1); - irq_exit(cpu, irq); -} - -void __init init_IRQ(void) -{ - int i; - - sgi_i2regs = (struct sgi_int2_regs *) (KSEG1 + SGI_INT2_BASE); - sgi_i3regs = (struct sgi_int3_regs *) (KSEG1 + SGI_INT3_BASE); - - /* Init local mask --> irq tables. */ - for (i = 0; i < 256; i++) { - if (i & 0x80) { - lc0msk_to_irqnr[i] = 7; - lc1msk_to_irqnr[i] = 15; - lc2msk_to_irqnr[i] = 23; - lc3msk_to_irqnr[i] = 31; - } else if (i & 0x40) { - lc0msk_to_irqnr[i] = 6; - lc1msk_to_irqnr[i] = 14; - lc2msk_to_irqnr[i] = 22; - lc3msk_to_irqnr[i] = 30; - } else if (i & 0x20) { - lc0msk_to_irqnr[i] = 5; - lc1msk_to_irqnr[i] = 13; - lc2msk_to_irqnr[i] = 21; - lc3msk_to_irqnr[i] = 29; - } else if (i & 0x10) { - lc0msk_to_irqnr[i] = 4; - lc1msk_to_irqnr[i] = 12; - lc2msk_to_irqnr[i] = 20; - lc3msk_to_irqnr[i] = 28; - } else if (i & 0x08) { - lc0msk_to_irqnr[i] = 3; - lc1msk_to_irqnr[i] = 11; - lc2msk_to_irqnr[i] = 19; - lc3msk_to_irqnr[i] = 27; - } else if (i & 0x04) { - lc0msk_to_irqnr[i] = 2; - lc1msk_to_irqnr[i] = 10; - lc2msk_to_irqnr[i] = 18; - lc3msk_to_irqnr[i] = 26; - } else if (i & 0x02) { - lc0msk_to_irqnr[i] = 1; - lc1msk_to_irqnr[i] = 9; - lc2msk_to_irqnr[i] = 17; - lc3msk_to_irqnr[i] = 25; - } else if (i & 0x01) { - lc0msk_to_irqnr[i] = 0; - lc1msk_to_irqnr[i] = 8; - lc2msk_to_irqnr[i] = 16; - lc3msk_to_irqnr[i] = 24; - } else { - lc0msk_to_irqnr[i] = 0; - lc1msk_to_irqnr[i] = 0; - lc2msk_to_irqnr[i] = 0; - lc3msk_to_irqnr[i] = 0; - } - } - - /* Indy uses an INT3, Indigo2 uses an INT2 */ - if (sgi_guiness) { - ioc_icontrol = &sgi_i3regs->ints; - ioc_timers = &sgi_i3regs->timers; - ioc_tclear = &sgi_i3regs->tclear; - } else { - ioc_icontrol = &sgi_i2regs->ints; - ioc_timers = &sgi_i2regs->timers; - ioc_tclear = &sgi_i2regs->tclear; - } - - /* Mask out all interrupts. */ - ioc_icontrol->imask0 = 0; - ioc_icontrol->imask1 = 0; - ioc_icontrol->cmeimask0 = 0; - ioc_icontrol->cmeimask1 = 0; - - set_except_vector(0, indyIRQ); - - init_generic_irq(); - - for (i = SGINT_LOCAL0; i < SGINT_END; i++) { - hw_irq_controller *handler; - - if (i < SGINT_LOCAL1) - handler = &ip22_local0_irq_type; - else if (i < SGINT_LOCAL2) - handler = &ip22_local1_irq_type; - else if (i < SGINT_LOCAL3) - handler = &ip22_local2_irq_type; - else if (i < SGINT_GIO) - handler = &ip22_local3_irq_type; - else if (i < SGINT_HPCDMA) - handler = &ip22_gio_irq_type; - else if (i < SGINT_END) - handler = &ip22_hpcdma_irq_type; - - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].handler = handler; - } -} --- linux-2.5.73/arch/mips/sgi/kernel/indyIRQ.S 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,126 +0,0 @@ -/* - * indyIRQ.S: Interrupt exception dispatch code for FullHouse and - * Guiness. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ - -#include -#include -#include -#include - - /* A lot of complication here is taken away because: - * - * 1) We handle one interrupt and return, sitting in a loop - * and moving across all the pending IRQ bits in the cause - * register is _NOT_ the answer, the common case is one - * pending IRQ so optimize in that direction. - * - * 2) We need not check against bits in the status register - * IRQ mask, that would make this routine slow as hell. - * - * 3) Linux only thinks in terms of all IRQs on or all IRQs - * off, nothing in between like BSD spl() brain-damage. - * - * Furthermore, the IRQs on the INDY look basically (barring - * software IRQs which we don't use at all) like: - * - * MIPS IRQ Source - * -------- ------ - * 0 Software (ignored) - * 1 Software (ignored) - * 2 Local IRQ level zero - * 3 Local IRQ level one - * 4 8254 Timer zero - * 5 8254 Timer one - * 6 Bus Error - * 7 R4k timer (what we use) - * - * We handle the IRQ according to _our_ priority which is: - * - * Highest ---- R4k Timer - * Local IRQ zero - * Local IRQ one - * Bus Error - * 8254 Timer zero - * Lowest ---- 8254 Timer one - * - * then we just return, if multiple IRQs are pending then - * we will just take another exception, big deal. - */ - - .text - .set noreorder - .set noat - .align 5 - NESTED(indyIRQ, PT_SIZE, sp) - SAVE_ALL - CLI - .set at - mfc0 s0, CP0_CAUSE # get irq mask - - /* First we check for r4k counter/timer IRQ. */ - andi a0, s0, CAUSEF_IP7 - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP2 # delay slot, check local level zero - - /* Wheee, a timer interrupt. */ - move a0, sp - jal indy_r4k_timer_interrupt - nop # delay slot - - j ret_from_irq - nop # delay slot - -1: - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP3 # delay slot, check local level one - - /* Wheee, local level zero interrupt. */ - jal indy_local0_irqdispatch - move a0, sp # delay slot - - j ret_from_irq - nop # delay slot - -1: - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP6 # delay slot, check bus error - - /* Wheee, local level one interrupt. */ - move a0, sp - jal indy_local1_irqdispatch - nop - - j ret_from_irq - nop - -1: - beq a0, zero, 1f - nop - - /* Wheee, an asynchronous bus error... */ - move a0, sp - jal indy_buserror_irq - nop - - j ret_from_irq - nop - -1: - /* Here by mistake? This is possible, what can happen - * is that by the time we take the exception the IRQ - * pin goes low, so just leave if this is the case. - */ - andi a0, s0, (CAUSEF_IP4 | CAUSEF_IP5) - beq a0, zero, 1f - - /* Must be one of the 8254 timers... */ - move a0, sp - jal indy_8254timer_irq - nop -1: - j ret_from_irq - nop - END(indyIRQ) --- linux-2.5.73/arch/mips/sgi/kernel/indy_mc.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,159 +0,0 @@ -/* - * indy_mc.c: Routines for manipulating the INDY memory controller. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes - * - * $Id: indy_mc.c,v 1.7 1999/12/04 03:59:00 ralf Exp $ - */ -#include -#include - -#include -#include -#include -#include -#include - -/* #define DEBUG_SGIMC */ - -struct sgimc_misc_ctrl *mcmisc_regs; -u32 *rpsscounter; -struct sgimc_dma_ctrl *dmactrlregs; - -static inline char *mconfig_string(unsigned long val) -{ - switch(val & SGIMC_MCONFIG_RMASK) { - case SGIMC_MCONFIG_FOURMB: - return "4MB"; - - case SGIMC_MCONFIG_EIGHTMB: - return "8MB"; - - case SGIMC_MCONFIG_SXTEENMB: - return "16MB"; - - case SGIMC_MCONFIG_TTWOMB: - return "32MB"; - - case SGIMC_MCONFIG_SFOURMB: - return "64MB"; - - case SGIMC_MCONFIG_OTEIGHTMB: - return "128MB"; - - default: - return "wheee, unknown"; - }; -} - -void __init sgimc_init(void) -{ - unsigned long tmpreg; - - mcmisc_regs = (struct sgimc_misc_ctrl *)(KSEG1+0x1fa00000); - rpsscounter = (unsigned int *) (KSEG1 + 0x1fa01004); - dmactrlregs = (struct sgimc_dma_ctrl *) (KSEG1+0x1fa02000); - - printk("MC: SGI memory controller Revision %d\n", - (int) mcmisc_regs->systemid & SGIMC_SYSID_MASKREV); - -#if 0 /* XXX Until I figure out what this bit really indicates XXX */ - /* XXX Is this systemid bit reliable? */ - if(mcmisc_regs->systemid & SGIMC_SYSID_EPRESENT) { - EISA_bus = 1; - printk("with EISA\n"); - } else { - EISA_bus = 0; - printk("no EISA\n"); - } -#endif - -#ifdef DEBUG_SGIMC - prom_printf("sgimc_init: memconfig0<%s> mconfig1<%s>\n", - mconfig_string(mcmisc_regs->mconfig0), - mconfig_string(mcmisc_regs->mconfig1)); - - prom_printf("mcdump: cpuctrl0<%08lx> cpuctrl1<%08lx>\n", - mcmisc_regs->cpuctrl0, mcmisc_regs->cpuctrl1); - prom_printf("mcdump: divider<%08lx>, gioparm<%04x>\n", - mcmisc_regs->divider, mcmisc_regs->gioparm); -#endif - - /* Place the MC into a known state. This must be done before - * interrupts are first enabled etc. - */ - - /* Step 1: The CPU/GIO error status registers will not latch - * up a new error status until the register has been - * cleared by the cpu. These status registers are - * cleared by writing any value to them. - */ - mcmisc_regs->cstat = mcmisc_regs->gstat = 0; - - /* Step 2: Enable all parity checking in cpu control register - * zero. - */ - tmpreg = mcmisc_regs->cpuctrl0; - tmpreg |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM | - SGIMC_CCTRL0_R4KNOCHKPARR); - mcmisc_regs->cpuctrl0 = tmpreg; - - /* Step 3: Setup the MC write buffer depth, this is controlled - * in cpu control register 1 in the lower 4 bits. - */ - tmpreg = mcmisc_regs->cpuctrl1; - tmpreg &= ~0xf; - tmpreg |= 0xd; - mcmisc_regs->cpuctrl1 = tmpreg; - - /* Step 4: Initialize the RPSS divider register to run as fast - * as it can correctly operate. The register is laid - * out as follows: - * - * ---------------------------------------- - * | RESERVED | INCREMENT | DIVIDER | - * ---------------------------------------- - * 31 16 15 8 7 0 - * - * DIVIDER determines how often a 'tick' happens, - * INCREMENT determines by how the RPSS increment - * registers value increases at each 'tick'. Thus, - * for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101 - */ - mcmisc_regs->divider = 0x101; - - /* Step 5: Initialize GIO64 arbitrator configuration register. - * - * NOTE: If you dork with startup code the HPC init code in - * sgihpc_init() must run before us because of how we - * need to know Guiness vs. FullHouse and the board - * revision on this machine. You have been warned. - */ - - /* First the basic invariants across all gio64 implementations. */ - tmpreg = SGIMC_GIOPARM_HPC64; /* All 1st HPC's interface at 64bits. */ - tmpreg |= SGIMC_GIOPARM_ONEBUS; /* Only one physical GIO bus exists. */ - - if(sgi_guiness) { - /* Guiness specific settings. */ - tmpreg |= SGIMC_GIOPARM_EISA64; /* MC talks to EISA at 64bits */ - tmpreg |= SGIMC_GIOPARM_MASTEREISA; /* EISA bus can act as master */ - } else { - /* Fullhouse specific settings. */ - if(sgi_boardid < 2) { - tmpreg |= SGIMC_GIOPARM_HPC264; /* 2nd HPC at 64bits */ - tmpreg |= SGIMC_GIOPARM_PLINEEXP0; /* exp0 pipelines */ - tmpreg |= SGIMC_GIOPARM_MASTEREXP1;/* exp1 masters */ - tmpreg |= SGIMC_GIOPARM_RTIMEEXP0; /* exp0 is realtime */ - } else { - tmpreg |= SGIMC_GIOPARM_HPC264; /* 2nd HPC 64bits */ - tmpreg |= SGIMC_GIOPARM_PLINEEXP0; /* exp[01] pipelined */ - tmpreg |= SGIMC_GIOPARM_PLINEEXP1; - tmpreg |= SGIMC_GIOPARM_MASTEREISA;/* EISA masters */ - /* someone forgot this poor little guy... */ - tmpreg |= SGIMC_GIOPARM_GFX64; /* GFX at 64 bits */ - } - } - mcmisc_regs->gioparm = tmpreg; /* poof */ -} --- linux-2.5.73/arch/mips/sgi/kernel/indy_rtc.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,36 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * RTC routines for Indy style attached Dallas chip. - * - * Copyright (C) 1998, 2001 by Ralf Baechle - */ -#include -#include - -static unsigned char indy_rtc_read_data(unsigned long addr) -{ - volatile unsigned int *rtcregs = (void *)INDY_CLOCK_REGS; - - return rtcregs[addr]; -} - -static void indy_rtc_write_data(unsigned char data, unsigned long addr) -{ - volatile unsigned int *rtcregs = (void *)INDY_CLOCK_REGS; - - rtcregs[addr] = data; -} - -static int indy_rtc_bcd_mode(void) -{ - return 0; -} - -struct rtc_ops indy_rtc_ops = { - &indy_rtc_read_data, - &indy_rtc_write_data, - &indy_rtc_bcd_mode -}; --- linux-2.5.73/arch/mips/sgi/kernel/indy_sc.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,226 +0,0 @@ -/* - * indy_sc.c: Indy cache management functions. - * - * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org), - * derived from r4xx0.c by David S. Miller (dm@engr.sgi.com). - */ -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Secondary cache size in bytes, if present. */ -static unsigned long scache_size; - -#undef DEBUG_CACHE - -#define SC_SIZE 0x00080000 -#define SC_LINE 32 -#define CI_MASK (SC_SIZE - SC_LINE) -#define SC_INDEX(n) ((n) & CI_MASK) - -static inline void indy_sc_wipe(unsigned long first, unsigned long last) -{ - unsigned long tmp; - - __asm__ __volatile__( - ".set\tnoreorder\t\t\t# indy_sc_wipe\n\t" - ".set\tmips3\n\t" - ".set\tnoat\n\t" - "mfc0\t%2, $12\n\t" - "li\t$1, 0x80\t\t\t# Go 64 bit\n\t" - "mtc0\t$1, $12\n\t" - - "dli\t$1, 0x9000000080000000\n\t" - "or\t%0, $1\t\t\t# first line to flush\n\t" - "or\t%1, $1\t\t\t# last line to flush\n\t" - ".set\tat\n\t" - - "1:\tsw\t$0, 0(%0)\n\t" - "bne\t%0, %1, 1b\n\t" - "daddu\t%0, 32\n\t" - - "mtc0\t%2, $12\t\t\t# Back to 32 bit\n\t" - "nop; nop; nop; nop;\n\t" - ".set\tmips0\n\t" - ".set\treorder" - : "=r" (first), "=r" (last), "=&r" (tmp) - : "0" (first), "1" (last) - : "$1"); -} - -static void indy_sc_wback_invalidate(unsigned long addr, unsigned long size) -{ - unsigned long first_line, last_line; - unsigned int flags; - -#ifdef DEBUG_CACHE - printk("indy_sc_wback_invalidate[%08lx,%08lx]", addr, size); -#endif - - if (!size) - return; - - /* Which lines to flush? */ - first_line = SC_INDEX(addr); - last_line = SC_INDEX(addr + size - 1); - - local_irq_save(flags); - if (first_line <= last_line) { - indy_sc_wipe(first_line, last_line); - goto out; - } - - indy_sc_wipe(first_line, SC_SIZE - SC_LINE); - indy_sc_wipe(0, last_line); -out: - local_irq_restore(flags); -} - -static void indy_sc_enable(void) -{ - unsigned long addr, tmp1, tmp2; - - /* This is really cool... */ -#ifdef DEBUG_CACHE - printk("Enabling R4600 SCACHE\n"); -#endif - __asm__ __volatile__( - ".set\tpush\n\t" - ".set\tnoreorder\n\t" - ".set\tmips3\n\t" - "mfc0\t%2, $12\n\t" - "nop; nop; nop; nop;\n\t" - "li\t%1, 0x80\n\t" - "mtc0\t%1, $12\n\t" - "nop; nop; nop; nop;\n\t" - "li\t%0, 0x1\n\t" - "dsll\t%0, 31\n\t" - "lui\t%1, 0x9000\n\t" - "dsll32\t%1, 0\n\t" - "or\t%0, %1, %0\n\t" - "sb\t$0, 0(%0)\n\t" - "mtc0\t$0, $12\n\t" - "nop; nop; nop; nop;\n\t" - "mtc0\t%2, $12\n\t" - "nop; nop; nop; nop;\n\t" - ".set\tpop" - : "=r" (tmp1), "=r" (tmp2), "=r" (addr)); -} - -static void indy_sc_disable(void) -{ - unsigned long tmp1, tmp2, tmp3; - -#ifdef DEBUG_CACHE - printk("Disabling R4600 SCACHE\n"); -#endif - __asm__ __volatile__( - ".set\tpush\n\t" - ".set\tnoreorder\n\t" - ".set\tmips3\n\t" - "li\t%0, 0x1\n\t" - "dsll\t%0, 31\n\t" - "lui\t%1, 0x9000\n\t" - "dsll32\t%1, 0\n\t" - "or\t%0, %1, %0\n\t" - "mfc0\t%2, $12\n\t" - "nop; nop; nop; nop\n\t" - "li\t%1, 0x80\n\t" - "mtc0\t%1, $12\n\t" - "nop; nop; nop; nop\n\t" - "sh\t$0, 0(%0)\n\t" - "mtc0\t$0, $12\n\t" - "nop; nop; nop; nop\n\t" - "mtc0\t%2, $12\n\t" - "nop; nop; nop; nop\n\t" - ".set\tpop" - : "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)); -} - -static inline int __init indy_sc_probe(void) -{ - volatile unsigned int *cpu_control; - unsigned short cmd = 0xc220; - unsigned long data = 0; - int i, n; - -#ifdef __MIPSEB__ - cpu_control = (volatile unsigned int *) KSEG1ADDR(0x1fa00034); -#else - cpu_control = (volatile unsigned int *) KSEG1ADDR(0x1fa00030); -#endif -#define DEASSERT(bit) (*(cpu_control) &= (~(bit))) -#define ASSERT(bit) (*(cpu_control) |= (bit)) -#define DELAY for(n = 0; n < 100000; n++) __asm__ __volatile__("") - DEASSERT(SGIMC_EEPROM_PRE); - DEASSERT(SGIMC_EEPROM_SDATAO); - DEASSERT(SGIMC_EEPROM_SECLOCK); - DEASSERT(SGIMC_EEPROM_PRE); - DELAY; - ASSERT(SGIMC_EEPROM_CSEL); ASSERT(SGIMC_EEPROM_SECLOCK); - for(i = 0; i < 11; i++) { - if(cmd & (1<<15)) - ASSERT(SGIMC_EEPROM_SDATAO); - else - DEASSERT(SGIMC_EEPROM_SDATAO); - DEASSERT(SGIMC_EEPROM_SECLOCK); - ASSERT(SGIMC_EEPROM_SECLOCK); - cmd <<= 1; - } - DEASSERT(SGIMC_EEPROM_SDATAO); - for(i = 0; i < (sizeof(unsigned short) * 8); i++) { - unsigned int tmp; - - DEASSERT(SGIMC_EEPROM_SECLOCK); - DELAY; - ASSERT(SGIMC_EEPROM_SECLOCK); - DELAY; - data <<= 1; - tmp = *cpu_control; - if(tmp & SGIMC_EEPROM_SDATAI) - data |= 1; - } - DEASSERT(SGIMC_EEPROM_SECLOCK); - DEASSERT(SGIMC_EEPROM_CSEL); - ASSERT(SGIMC_EEPROM_PRE); - ASSERT(SGIMC_EEPROM_SECLOCK); - - data <<= PAGE_SHIFT; - if (data == 0) - return 0; - - scache_size = data; - - printk("R4600/R5000 SCACHE size %ldK, linesize 32 bytes.\n", - scache_size >> 10); - - return 1; -} - -/* XXX Check with wje if the Indy caches can differenciate between - writeback + invalidate and just invalidate. */ -struct bcache_ops indy_sc_ops = { - indy_sc_enable, - indy_sc_disable, - indy_sc_wback_invalidate, - indy_sc_wback_invalidate -}; - -void __init indy_sc_init(void) -{ - if (indy_sc_probe()) { - indy_sc_enable(); - bcops = &indy_sc_ops; - } -} --- linux-2.5.73/arch/mips/sgi/kernel/Makefile 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,9 +0,0 @@ -# -# Makefile for the SGI specific kernel interface routines -# under Linux. -# - -obj-y += indy_mc.o indy_sc.o indy_hpc.o indy_int.o indy_rtc.o system.o \ - indyIRQ.o reset.o setup.o time.o - -EXTRA_AFLAGS := $(CFLAGS) --- linux-2.5.73/arch/mips/sgi/kernel/reset.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,241 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 1998, 2001 by Ralf Baechle - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Just powerdown if init hasn't done after POWERDOWN_TIMEOUT seconds. - * I'm not shure if this feature is a good idea, for now it's here just to - * make the power button make behave just like under IRIX. - */ -#define POWERDOWN_TIMEOUT 120 - -/* - * Blink frequency during reboot grace period and when paniced. - */ -#define POWERDOWN_FREQ (HZ / 4) -#define PANIC_FREQ (HZ / 8) - -static unsigned char sgi_volume; - -static struct timer_list power_timer, blink_timer, debounce_timer, volume_timer; -static int shuting_down, has_paniced; - -static void sgi_machine_restart(char *command) __attribute__((noreturn)); -static void sgi_machine_halt(void) __attribute__((noreturn)); -static void sgi_machine_power_off(void) __attribute__((noreturn)); - -/* XXX How to pass the reboot command to the firmware??? */ -static void sgi_machine_restart(char *command) -{ - if (shuting_down) - sgi_machine_power_off(); - prom_reboot(); -} - -static void sgi_machine_halt(void) -{ - if (shuting_down) - sgi_machine_power_off(); - ArcEnterInteractiveMode(); -} - -static void sgi_machine_power_off(void) -{ - struct indy_clock *clock = (struct indy_clock *)INDY_CLOCK_REGS; - - cli(); - - clock->cmd |= 0x08; /* Disable watchdog */ - clock->whsec = 0; - clock->wsec = 0; - - while(1) { - hpc3mregs->panel=0xfe; - /* Good bye cruel world ... */ - - /* If we're still running, we probably got sent an alarm - interrupt. Read the flag to clear it. */ - clock->halarm; - } -} - -static void power_timeout(unsigned long data) -{ - sgi_machine_power_off(); -} - -static void blink_timeout(unsigned long data) -{ - /* XXX fix this for fullhouse */ - sgi_hpc_write1 ^= (HPC3_WRITE1_LC0OFF|HPC3_WRITE1_LC1OFF); - hpc3mregs->write1 = sgi_hpc_write1; - - mod_timer(&blink_timer, jiffies+data); -} - -static void debounce(unsigned long data) -{ - del_timer(&debounce_timer); - if (ioc_icontrol->istat1 & 2) { /* Interrupt still being sent. */ - debounce_timer.expires = jiffies + 5; /* 0.05s */ - add_timer(&debounce_timer); - - hpc3mregs->panel = 0xf3; - - return; - } - - if (has_paniced) - prom_reboot(); - - enable_irq(SGI_PANEL_IRQ); -} - -static inline void power_button(void) -{ - if (has_paniced) - return; - - if (shuting_down || kill_proc(1, SIGINT, 1)) { - /* No init process or button pressed twice. */ - sgi_machine_power_off(); - } - - shuting_down = 1; - blink_timer.data = POWERDOWN_FREQ; - blink_timeout(POWERDOWN_FREQ); - - init_timer(&power_timer); - power_timer.function = power_timeout; - power_timer.expires = jiffies + POWERDOWN_TIMEOUT * HZ; - add_timer(&power_timer); -} - -inline void sgi_volume_set(unsigned char volume) -{ - sgi_volume = volume; - - hpc3c0->pbus_extregs[2][0] = sgi_volume; - hpc3c0->pbus_extregs[2][1] = sgi_volume; -} - -inline void sgi_volume_get(unsigned char *volume) -{ - *volume = sgi_volume; -} - -static inline void volume_up_button(unsigned long data) -{ - del_timer(&volume_timer); - - if (sgi_volume < 0xff) - sgi_volume++; - - hpc3c0->pbus_extregs[2][0] = sgi_volume; - hpc3c0->pbus_extregs[2][1] = sgi_volume; - - if (ioc_icontrol->istat1 & 2) { - volume_timer.expires = jiffies + 1; - add_timer(&volume_timer); - } - -} - -static inline void volume_down_button(unsigned long data) -{ - del_timer(&volume_timer); - - if (sgi_volume > 0) - sgi_volume--; - - hpc3c0->pbus_extregs[2][0] = sgi_volume; - hpc3c0->pbus_extregs[2][1] = sgi_volume; - - if (ioc_icontrol->istat1 & 2) { - volume_timer.expires = jiffies + 1; - add_timer(&volume_timer); - } -} - -static void panel_int(int irq, void *dev_id, struct pt_regs *regs) -{ - unsigned int buttons; - - buttons = hpc3mregs->panel; - hpc3mregs->panel = 3; /* power_interrupt | power_supply_on */ - - if (ioc_icontrol->istat1 & 2) { /* Wait until interrupt goes away */ - disable_irq(SGI_PANEL_IRQ); - init_timer(&debounce_timer); - debounce_timer.function = debounce; - debounce_timer.expires = jiffies + 5; - add_timer(&debounce_timer); - } - - if (!(buttons & 2)) /* Power button was pressed */ - power_button(); - if (!(buttons & 0x40)) { /* Volume up button was pressed */ - init_timer(&volume_timer); - volume_timer.function = volume_up_button; - volume_timer.expires = jiffies + 1; - add_timer(&volume_timer); - } - if (!(buttons & 0x10)) { /* Volume down button was pressed */ - init_timer(&volume_timer); - volume_timer.function = volume_down_button; - volume_timer.expires = jiffies + 1; - add_timer(&volume_timer); - } -} - -static int panic_event(struct notifier_block *this, unsigned long event, - void *ptr) -{ - if (has_paniced) - return NOTIFY_DONE; - has_paniced = 1; - - blink_timer.data = PANIC_FREQ; - blink_timeout(PANIC_FREQ); - - return NOTIFY_DONE; -} - -static struct notifier_block panic_block = { - panic_event, - NULL, - 0 -}; - -void indy_reboot_setup(void) -{ - static int setup_done; - - if (setup_done) - return; - setup_done = 1; - - _machine_restart = sgi_machine_restart; - _machine_halt = sgi_machine_halt; - _machine_power_off = sgi_machine_power_off; - - request_irq(SGI_PANEL_IRQ, panel_int, 0, "Front Panel", NULL); - init_timer(&blink_timer); - blink_timer.function = blink_timeout; - notifier_chain_register(&panic_notifier_list, &panic_block); -} --- linux-2.5.73/arch/mips/sgi/kernel/setup.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,308 +0,0 @@ -/* - * setup.c: SGI specific setup, including init of the feature struct. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org) - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_REMOTE_DEBUG -extern void rs_kgdb_hook(int); -extern void breakpoint(void); -static int remote_debug = 0; -#endif - -#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_ARC_CONSOLE) -extern void console_setup(char *); -#endif - -extern unsigned long r4k_interval; /* Cycle counter ticks per 1/HZ seconds */ - -extern struct rtc_ops indy_rtc_ops; -void indy_reboot_setup(void); -void sgi_volume_set(unsigned char); - -#define sgi_kh ((struct hpc_keyb *) (KSEG1 + 0x1fbd9800 + 64)) - -#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ - -static void sgi_request_region(void) -{ - /* No I/O ports are being used on the Indy. */ -} - -static int sgi_request_irq(void (*handler)(int, void *, struct pt_regs *)) -{ - /* Dirty hack, this get's called as a callback from the keyboard - driver. We piggyback the initialization of the front panel - button handling on it even though they're technically not - related with the keyboard driver in any way. Doing it from - indy_setup wouldn't work since kmalloc isn't initialized yet. */ - indy_reboot_setup(); - - return request_irq(SGI_KEYBOARD_IRQ, handler, 0, "keyboard", NULL); -} - -static int sgi_aux_request_irq(void (*handler)(int, void *, struct pt_regs *)) -{ - /* Nothing to do, interrupt is shared with the keyboard hw */ - return 0; -} - -static void sgi_aux_free_irq(void) -{ - /* Nothing to do, interrupt is shared with the keyboard hw */ -} - -static unsigned char sgi_read_input(void) -{ - return sgi_kh->data; -} - -static void sgi_write_output(unsigned char val) -{ - int status; - - do { - status = sgi_kh->command; - } while (status & KBD_STAT_IBF); - sgi_kh->data = val; -} - -static void sgi_write_command(unsigned char val) -{ - int status; - - do { - status = sgi_kh->command; - } while (status & KBD_STAT_IBF); - sgi_kh->command = val; -} - -static unsigned char sgi_read_status(void) -{ - return sgi_kh->command; -} - -struct kbd_ops sgi_kbd_ops = { - sgi_request_region, - sgi_request_irq, - - sgi_aux_request_irq, - sgi_aux_free_irq, - - sgi_read_input, - sgi_write_output, - sgi_write_command, - sgi_read_status -}; - -static unsigned long dosample(volatile unsigned char *tcwp, - volatile unsigned char *tc2p) -{ - unsigned long ct0, ct1; - unsigned char msb, lsb; - - /* Start the counter. */ - *tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MRGEN); - *tc2p = (SGINT_TCSAMP_COUNTER & 0xff); - *tc2p = (SGINT_TCSAMP_COUNTER >> 8); - - /* Get initial counter invariant */ - ct0 = read_32bit_cp0_register(CP0_COUNT); - - /* Latch and spin until top byte of counter2 is zero */ - do { - *tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT); - lsb = *tc2p; - msb = *tc2p; - ct1 = read_32bit_cp0_register(CP0_COUNT); - } while(msb); - - /* Stop the counter. */ - *tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MSWST); - - /* - * Return the difference, this is how far the r4k counter increments - * for every 1/HZ seconds. We round off the nearest 1 MHz of master - * clock (= 1000000 / 100 / 2 = 5000 count). - */ - - return ((ct1 - ct0) / 5000) * 5000; -} - -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) - -void sgi_time_init (struct irqaction *irq) { - /* Here we need to calibrate the cycle counter to at least be close. - * We don't need to actually register the irq handler because that's - * all done in indyIRQ.S. - */ - struct sgi_ioc_timers *p; - volatile unsigned char *tcwp, *tc2p; - unsigned long r4k_ticks[3]; - unsigned long r4k_next; - - /* Figure out the r4k offset, the algorithm is very simple - * and works in _all_ cases as long as the 8254 counter - * register itself works ok (as an interrupt driving timer - * it does not because of bug, this is why we are using - * the onchip r4k counter/compare register to serve this - * purpose, but for r4k_offset calculation it will work - * ok for us). There are other very complicated ways - * of performing this calculation but this one works just - * fine so I am not going to futz around. ;-) - */ - p = ioc_timers; - tcwp = &p->tcword; - tc2p = &p->tcnt2; - - printk("Calibrating system timer... "); - dosample(tcwp, tc2p); /* Prime cache. */ - dosample(tcwp, tc2p); /* Prime cache. */ - /* Zero is NOT an option. */ - do { - r4k_ticks[0] = dosample (tcwp, tc2p); - } while (!r4k_ticks[0]); - do { - r4k_ticks[1] = dosample (tcwp, tc2p); - } while (!r4k_ticks[1]); - - if (r4k_ticks[0] != r4k_ticks[1]) { - printk ("warning: timer counts differ, retrying..."); - r4k_ticks[2] = dosample (tcwp, tc2p); - if (r4k_ticks[2] == r4k_ticks[0] - || r4k_ticks[2] == r4k_ticks[1]) - r4k_interval = r4k_ticks[2]; - else { - printk ("disagreement, using average..."); - r4k_interval = (r4k_ticks[0] + r4k_ticks[1] - + r4k_ticks[2]) / 3; - } - } else - r4k_interval = r4k_ticks[0]; - - printk("%d [%d.%02d MHz CPU]\n", (int) r4k_interval, - (int) (r4k_interval / 5000), (int) (r4k_interval % 5000) / 50); - - /* Set ourselves up for future interrupts */ - r4k_next = (read_32bit_cp0_register(CP0_COUNT) + r4k_interval); - write_32bit_cp0_register(CP0_COMPARE, r4k_next); - change_cp0_status(ST0_IM, ALLINTS); - sti (); -} - -void __init sgi_setup(void) -{ -#ifdef CONFIG_SERIAL_CONSOLE - char *ctype; -#endif -#ifdef CONFIG_REMOTE_DEBUG - char *kgdb_ttyd; -#endif - - board_time_init = sgi_time_init; - - /* Init the INDY HPC I/O controller. Need to call this before - * fucking with the memory controller because it needs to know the - * boardID and whether this is a Guiness or a FullHouse machine. - */ - sgihpc_init(); - - /* Init INDY memory controller. */ - sgimc_init(); - - /* Now enable boardcaches, if any. */ - indy_sc_init(); - -#ifdef CONFIG_SERIAL_CONSOLE - /* ARCS console environment variable is set to "g?" for - * graphics console, it is set to "d" for the first serial - * line and "d2" for the second serial line. - */ - ctype = ArcGetEnvironmentVariable("console"); - if(*ctype == 'd') { - if(*(ctype+1)=='2') - console_setup ("ttyS1"); - else - console_setup ("ttyS0"); - } -#endif - -#ifdef CONFIG_REMOTE_DEBUG - kgdb_ttyd = prom_getcmdline(); - if ((kgdb_ttyd = strstr(kgdb_ttyd, "kgdb=ttyd")) != NULL) { - int line; - kgdb_ttyd += strlen("kgdb=ttyd"); - if (*kgdb_ttyd != '1' && *kgdb_ttyd != '2') - printk("KGDB: Uknown serial line /dev/ttyd%c, " - "falling back to /dev/ttyd1\n", *kgdb_ttyd); - line = *kgdb_ttyd == '2' ? 0 : 1; - printk("KGDB: Using serial line /dev/ttyd%d for session\n", - line ? 1 : 2); - rs_kgdb_hook(line); - - printk("KGDB: Using serial line /dev/ttyd%d for session, " - "please connect your debugger\n", line ? 1 : 2); - - remote_debug = 1; - /* Breakpoints and stuff are in sgi_irq_setup() */ - } -#endif - -#ifdef CONFIG_ARC_CONSOLE - console_setup("ttyS0"); -#endif - - sgi_volume_set(simple_strtoul(ArcGetEnvironmentVariable("volume"), NULL, 10)); - -#ifdef CONFIG_VT -#ifdef CONFIG_SGI_NEWPORT_CONSOLE - conswitchp = &newport_con; - - screen_info = (struct screen_info) { - 0, 0, /* orig-x, orig-y */ - 0, /* unused */ - 0, /* orig_video_page */ - 0, /* orig_video_mode */ - 160, /* orig_video_cols */ - 0, 0, 0, /* unused, ega_bx, unused */ - 64, /* orig_video_lines */ - 0, /* orig_video_isVGA */ - 16 /* orig_video_points */ - }; -#else - conswitchp = &dummy_con; -#endif -#endif - - rtc_ops = &indy_rtc_ops; - kbd_ops = &sgi_kbd_ops; -#ifdef CONFIG_PSMOUSE - aux_device_present = 0xaa; -#endif -#ifdef CONFIG_VIDEO_VINO - init_vino(); -#endif -} --- linux-2.5.73/arch/mips/sgi/kernel/system.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,132 +0,0 @@ -/* - * system.c: Probe the system type using ARCS prom interface library. - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - * - * $Id: system.c,v 1.8 1999/10/09 00:00:59 ralf Exp $ - */ -#include -#include -#include -#include - -#include -#include -#include - -enum sgi_mach sgimach; - -struct smatch { - char *name; - int type; -}; - -static struct smatch sgi_cputable[] = { - { "MIPS-R2000", CPU_R2000 }, - { "MIPS-R3000", CPU_R3000 }, - { "MIPS-R3000A", CPU_R3000A }, - { "MIPS-R4000", CPU_R4000SC }, - { "MIPS-R4400", CPU_R4400SC }, - { "MIPS-R4600", CPU_R4600 }, - { "MIPS-R8000", CPU_R8000 }, - { "MIPS-R5000", CPU_R5000 }, - { "MIPS-R5000A", CPU_R5000A } -}; - -#define NUM_CPUS 9 /* for now */ - -static int __init string_to_cpu(char *s) -{ - int i; - - for(i = 0; i < NUM_CPUS; i++) { - if(!strcmp(s, sgi_cputable[i].name)) - return sgi_cputable[i].type; - } - prom_printf("\nYeee, could not determine MIPS cpu type <%s>\n", s); - prom_printf("press a key to reboot\n"); - prom_getchar(); - romvec->imode(); - return 0; -} - -/* - * We' call this early before loadmmu(). If we do the other way around - * the firmware will crash and burn. - */ -void __init sgi_sysinit(void) -{ - pcomponent *p, *toplev, *cpup = 0; - int cputype = -1; - - - /* The root component tells us what machine architecture we - * have here. - */ - p = prom_getchild(PROM_NULL_COMPONENT); - - /* Now scan for cpu(s). */ - toplev = p = prom_getchild(p); - while(p) { - int ncpus = 0; - - if(p->type == Cpu) { - if(++ncpus > 1) { - prom_printf("\nYeee, SGI MP not ready yet\n"); - prom_printf("press a key to reboot\n"); - prom_getchar(); - romvec->imode(); - } - printk("CPU: %s ", p->iname); - cpup = p; - cputype = string_to_cpu(cpup->iname); - } - p = prom_getsibling(p); - } - if(cputype == -1) { - prom_printf("\nYeee, could not find cpu ARCS component\n"); - prom_printf("press a key to reboot\n"); - prom_getchar(); - romvec->imode(); - } - p = prom_getchild(cpup); - while(p) { - switch(p->class) { - case processor: - switch(p->type) { - case Fpu: - printk("FPU<%s> ", p->iname); - break; - - default: - break; - }; - break; - - case cache: - switch(p->type) { - case picache: - printk("ICACHE "); - break; - - case pdcache: - printk("DCACHE "); - break; - - case sccache: - printk("SCACHE "); - break; - - default: - break; - - }; - break; - - default: - break; - }; - p = prom_getsibling(p); - } - printk("\n"); -} --- linux-2.5.73/arch/mips/sgi/kernel/time.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,21 +0,0 @@ -/* - * time.c: Generic SGI handler for (spurious) 8254 interrupts - * - * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) - */ -#include -#include -#include - -void indy_8254timer_irq(void) -{ - int cpu = smp_processor_id(); - int irq = 4; - - irq_enter(cpu, irq); - kstat_cpu(0).irqs[irq]++; - printk("indy_8254timer_irq: Whoops, should not have gotten this IRQ\n"); - prom_getchar(); - ArcEnterInteractiveMode(); - irq_exit(cpu, irq); -} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/cfe/cfe_api.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,502 @@ +/* + * Copyright (C) 2000, 2001, 2002 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* ********************************************************************* + * + * Broadcom Common Firmware Environment (CFE) + * + * Device Function stubs File: cfe_api.c + * + * This module contains device function stubs (small routines to + * call the standard "iocb" interface entry point to CFE). + * There should be one routine here per iocb function call. + * + * Authors: Mitch Lichtenberg, Chris Demetriou + * + ********************************************************************* */ + +#include "cfe_api.h" +#include "cfe_api_int.h" + +/* Cast from a native pointer to a cfe_xptr_t and back. */ +#define XPTR_FROM_NATIVE(n) ((cfe_xptr_t) (intptr_t) (n)) +#define NATIVE_FROM_XPTR(x) ((void *) (intptr_t) (x)) + +#ifdef CFE_API_IMPL_NAMESPACE +#define cfe_iocb_dispatch(a) __cfe_iocb_dispatch(a) +#endif +int cfe_iocb_dispatch(cfe_xiocb_t * xiocb); + +#if defined(CFE_API_common) || defined(CFE_API_ALL) +/* + * Declare the dispatch function with args of "intptr_t". + * This makes sure whatever model we're compiling in + * puts the pointers in a single register. For example, + * combining -mlong64 and -mips1 or -mips2 would lead to + * trouble, since the handle and IOCB pointer will be + * passed in two registers each, and CFE expects one. + */ + +static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb) = 0; +static cfe_xuint_t cfe_handle = 0; + +int cfe_init(cfe_xuint_t handle, cfe_xuint_t ept) +{ + cfe_dispfunc = NATIVE_FROM_XPTR(ept); + cfe_handle = handle; + return 0; +} + +int cfe_iocb_dispatch(cfe_xiocb_t * xiocb) +{ + if (!cfe_dispfunc) + return -1; + return (*cfe_dispfunc) ((intptr_t) cfe_handle, (intptr_t) xiocb); +} +#endif /* CFE_API_common || CFE_API_ALL */ + +#if defined(CFE_API_close) || defined(CFE_API_ALL) +int cfe_close(int handle) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_CLOSE; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = handle; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = 0; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; + +} +#endif /* CFE_API_close || CFE_API_ALL */ + +#if defined(CFE_API_cpu_start) || defined(CFE_API_ALL) +int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t); + xiocb.plist.xiocb_cpuctl.cpu_number = cpu; + xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_START; + xiocb.plist.xiocb_cpuctl.gp_val = gp; + xiocb.plist.xiocb_cpuctl.sp_val = sp; + xiocb.plist.xiocb_cpuctl.a1_val = a1; + xiocb.plist.xiocb_cpuctl.start_addr = (long) fn; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; +} +#endif /* CFE_API_cpu_start || CFE_API_ALL */ + +#if defined(CFE_API_cpu_stop) || defined(CFE_API_ALL) +int cfe_cpu_stop(int cpu) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t); + xiocb.plist.xiocb_cpuctl.cpu_number = cpu; + xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_STOP; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; +} +#endif /* CFE_API_cpu_stop || CFE_API_ALL */ + +#if defined(CFE_API_enumenv) || defined(CFE_API_ALL) +int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_ENV_SET; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); + xiocb.plist.xiocb_envbuf.enum_idx = idx; + xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); + xiocb.plist.xiocb_envbuf.name_length = namelen; + xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val); + xiocb.plist.xiocb_envbuf.val_length = vallen; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; +} +#endif /* CFE_API_enumenv || CFE_API_ALL */ + +#if defined(CFE_API_enummem) || defined(CFE_API_ALL) +int +cfe_enummem(int idx, int flags, cfe_xuint_t * start, cfe_xuint_t * length, + cfe_xuint_t * type) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = flags; + xiocb.xiocb_psize = sizeof(xiocb_meminfo_t); + xiocb.plist.xiocb_meminfo.mi_idx = idx; + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + + *start = xiocb.plist.xiocb_meminfo.mi_addr; + *length = xiocb.plist.xiocb_meminfo.mi_size; + *type = xiocb.plist.xiocb_meminfo.mi_type; + + return 0; +} +#endif /* CFE_API_enummem || CFE_API_ALL */ + +#if defined(CFE_API_exit) || defined(CFE_API_ALL) +int cfe_exit(int warm, int status) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_FW_RESTART; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = warm ? CFE_FLG_WARMSTART : 0; + xiocb.xiocb_psize = sizeof(xiocb_exitstat_t); + xiocb.plist.xiocb_exitstat.status = status; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; +} +#endif /* CFE_API_exit || CFE_API_ALL */ + +#if defined(CFE_API_flushcache) || defined(CFE_API_ALL) +int cfe_flushcache(int flg) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_FW_FLUSHCACHE; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = flg; + xiocb.xiocb_psize = 0; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; +} +#endif /* CFE_API_flushcache || CFE_API_ALL */ + +#if defined(CFE_API_getdevinfo) || defined(CFE_API_ALL) +int cfe_getdevinfo(char *name) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_GETINFO; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.plist.xiocb_buffer.buf_offset = 0; + xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name); + xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name); + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + return xiocb.plist.xiocb_buffer.buf_devflags; +} +#endif /* CFE_API_getdevinfo || CFE_API_ALL */ + +#if defined(CFE_API_getenv) || defined(CFE_API_ALL) +int cfe_getenv(char *name, char *dest, int destlen) +{ + cfe_xiocb_t xiocb; + + *dest = 0; + + xiocb.xiocb_fcode = CFE_CMD_ENV_GET; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); + xiocb.plist.xiocb_envbuf.enum_idx = 0; + xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); + xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name); + xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(dest); + xiocb.plist.xiocb_envbuf.val_length = destlen; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; +} +#endif /* CFE_API_getenv || CFE_API_ALL */ + +#if defined(CFE_API_getfwinfo) || defined(CFE_API_ALL) +int cfe_getfwinfo(cfe_fwinfo_t * info) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_FW_GETINFO; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_fwinfo_t); + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + + info->fwi_version = xiocb.plist.xiocb_fwinfo.fwi_version; + info->fwi_totalmem = xiocb.plist.xiocb_fwinfo.fwi_totalmem; + info->fwi_flags = xiocb.plist.xiocb_fwinfo.fwi_flags; + info->fwi_boardid = xiocb.plist.xiocb_fwinfo.fwi_boardid; + info->fwi_bootarea_va = xiocb.plist.xiocb_fwinfo.fwi_bootarea_va; + info->fwi_bootarea_pa = xiocb.plist.xiocb_fwinfo.fwi_bootarea_pa; + info->fwi_bootarea_size = + xiocb.plist.xiocb_fwinfo.fwi_bootarea_size; +#if 0 + info->fwi_reserved1 = xiocb.plist.xiocb_fwinfo.fwi_reserved1; + info->fwi_reserved2 = xiocb.plist.xiocb_fwinfo.fwi_reserved2; + info->fwi_reserved3 = xiocb.plist.xiocb_fwinfo.fwi_reserved3; +#endif + + return 0; +} +#endif /* CFE_API_getfwinfo || CFE_API_ALL */ + +#if defined(CFE_API_getstdhandle) || defined(CFE_API_ALL) +int cfe_getstdhandle(int flg) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_GETHANDLE; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = flg; + xiocb.xiocb_psize = 0; + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + return xiocb.xiocb_handle; +} +#endif /* CFE_API_getstdhandle || CFE_API_ALL */ + +#if defined(CFE_API_getticks) || defined(CFE_API_ALL) +int64_t +#ifdef CFE_API_IMPL_NAMESPACE +__cfe_getticks(void) +#else +cfe_getticks(void) +#endif +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_FW_GETTIME; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_time_t); + xiocb.plist.xiocb_time.ticks = 0; + + cfe_iocb_dispatch(&xiocb); + + return xiocb.plist.xiocb_time.ticks; + +} +#endif /* CFE_API_getticks || CFE_API_ALL */ + +#if defined(CFE_API_inpstat) || defined(CFE_API_ALL) +int cfe_inpstat(int handle) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_INPSTAT; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = handle; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_inpstat_t); + xiocb.plist.xiocb_inpstat.inp_status = 0; + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + return xiocb.plist.xiocb_inpstat.inp_status; +} +#endif /* CFE_API_inpstat || CFE_API_ALL */ + +#if defined(CFE_API_ioctl) || defined(CFE_API_ALL) +int +cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, + int length, int *retlen, cfe_xuint_t offset) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_IOCTL; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = handle; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.plist.xiocb_buffer.buf_offset = offset; + xiocb.plist.xiocb_buffer.buf_ioctlcmd = ioctlnum; + xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); + xiocb.plist.xiocb_buffer.buf_length = length; + + cfe_iocb_dispatch(&xiocb); + + if (retlen) + *retlen = xiocb.plist.xiocb_buffer.buf_retlen; + return xiocb.xiocb_status; +} +#endif /* CFE_API_ioctl || CFE_API_ALL */ + +#if defined(CFE_API_open) || defined(CFE_API_ALL) +int cfe_open(char *name) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_OPEN; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.plist.xiocb_buffer.buf_offset = 0; + xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name); + xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name); + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + return xiocb.xiocb_handle; +} +#endif /* CFE_API_open || CFE_API_ALL */ + +#if defined(CFE_API_read) || defined(CFE_API_ALL) +int cfe_read(int handle, unsigned char *buffer, int length) +{ + return cfe_readblk(handle, 0, buffer, length); +} +#endif /* CFE_API_read || CFE_API_ALL */ + +#if defined(CFE_API_readblk) || defined(CFE_API_ALL) +int +cfe_readblk(int handle, cfe_xint_t offset, unsigned char *buffer, + int length) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_READ; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = handle; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.plist.xiocb_buffer.buf_offset = offset; + xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); + xiocb.plist.xiocb_buffer.buf_length = length; + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + return xiocb.plist.xiocb_buffer.buf_retlen; +} +#endif /* CFE_API_readblk || CFE_API_ALL */ + +#if defined(CFE_API_setenv) || defined(CFE_API_ALL) +int cfe_setenv(char *name, char *val) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_ENV_SET; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = 0; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); + xiocb.plist.xiocb_envbuf.enum_idx = 0; + xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); + xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name); + xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val); + xiocb.plist.xiocb_envbuf.val_length = cfe_strlen(val); + + cfe_iocb_dispatch(&xiocb); + + return xiocb.xiocb_status; +} +#endif /* CFE_API_setenv || CFE_API_ALL */ + +#if (defined(CFE_API_strlen) || defined(CFE_API_ALL)) \ + && !defined(CFE_API_STRLEN_CUSTOM) +int cfe_strlen(char *name) +{ + int count = 0; + + while (*name++) + count++; + + return count; +} +#endif /* CFE_API_strlen || CFE_API_ALL */ + +#if defined(CFE_API_write) || defined(CFE_API_ALL) +int cfe_write(int handle, unsigned char *buffer, int length) +{ + return cfe_writeblk(handle, 0, buffer, length); +} +#endif /* CFE_API_write || CFE_API_ALL */ + +#if defined(CFE_API_writeblk) || defined(CFE_API_ALL) +int +cfe_writeblk(int handle, cfe_xint_t offset, unsigned char *buffer, + int length) +{ + cfe_xiocb_t xiocb; + + xiocb.xiocb_fcode = CFE_CMD_DEV_WRITE; + xiocb.xiocb_status = 0; + xiocb.xiocb_handle = handle; + xiocb.xiocb_flags = 0; + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); + xiocb.plist.xiocb_buffer.buf_offset = offset; + xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); + xiocb.plist.xiocb_buffer.buf_length = length; + + cfe_iocb_dispatch(&xiocb); + + if (xiocb.xiocb_status < 0) + return xiocb.xiocb_status; + return xiocb.plist.xiocb_buffer.buf_retlen; +} +#endif /* CFE_API_writeblk || CFE_API_ALL */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/cfe/cfe_api.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2000, 2001, 2002 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* ********************************************************************* + * + * Broadcom Common Firmware Environment (CFE) + * + * Device function prototypes File: cfe_api.h + * + * This file contains declarations for doing callbacks to + * cfe from an application. It should be the only header + * needed by the application to use this library + * + * Authors: Mitch Lichtenberg, Chris Demetriou + * + ********************************************************************* */ + +#ifndef CFE_API_H +#define CFE_API_H + +/* + * Apply customizations here for different OSes. These need to: + * * typedef uint64_t, int64_t, intptr_t, uintptr_t. + * * define cfe_strlen() if use of an existing function is desired. + * * define CFE_API_IMPL_NAMESPACE if API functions are to use + * names in the implementation namespace. + * Also, optionally, if the build environment does not do so automatically, + * CFE_API_* can be defined here as desired. + */ +/* Begin customization. */ +#include +#include + +typedef long intptr_t; + +#define cfe_strlen strlen + +#define CFE_API_ALL +#define CFE_API_STRLEN_CUSTOM +/* End customization. */ + + +/* ********************************************************************* + * Constants + ********************************************************************* */ + +/* Seal indicating CFE's presence, passed to user program. */ +#define CFE_EPTSEAL 0x43464531 + +#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */ +#define CFE_MI_AVAILABLE 1 /* memory is available */ + +#define CFE_FLG_WARMSTART 0x00000001 +#define CFE_FLG_FULL_ARENA 0x00000001 +#define CFE_FLG_ENV_PERMANENT 0x00000001 + +#define CFE_CPU_CMD_START 1 +#define CFE_CPU_CMD_STOP 0 + +#define CFE_STDHANDLE_CONSOLE 0 + +#define CFE_DEV_NETWORK 1 +#define CFE_DEV_DISK 2 +#define CFE_DEV_FLASH 3 +#define CFE_DEV_SERIAL 4 +#define CFE_DEV_CPU 5 +#define CFE_DEV_NVRAM 6 +#define CFE_DEV_CLOCK 7 +#define CFE_DEV_OTHER 8 +#define CFE_DEV_MASK 0x0F + +#define CFE_CACHE_FLUSH_D 1 +#define CFE_CACHE_INVAL_I 2 +#define CFE_CACHE_INVAL_D 4 +#define CFE_CACHE_INVAL_L2 8 + +#define CFE_FWI_64BIT 0x00000001 +#define CFE_FWI_32BIT 0x00000002 +#define CFE_FWI_RELOC 0x00000004 +#define CFE_FWI_UNCACHED 0x00000008 +#define CFE_FWI_MULTICPU 0x00000010 +#define CFE_FWI_FUNCSIM 0x00000020 +#define CFE_FWI_RTLSIM 0x00000040 + +typedef struct { + int64_t fwi_version; /* major, minor, eco version */ + int64_t fwi_totalmem; /* total installed mem */ + int64_t fwi_flags; /* various flags */ + int64_t fwi_boardid; /* board ID */ + int64_t fwi_bootarea_va; /* VA of boot area */ + int64_t fwi_bootarea_pa; /* PA of boot area */ + int64_t fwi_bootarea_size; /* size of boot area */ +} cfe_fwinfo_t; + + +/* + * cfe_strlen is handled specially: If already defined, it has been + * overridden in this environment with a standard strlen-like function. + */ +#ifdef cfe_strlen +# define CFE_API_STRLEN_CUSTOM +#else +# ifdef CFE_API_IMPL_NAMESPACE +# define cfe_strlen(a) __cfe_strlen(a) +# endif +int cfe_strlen(char *name); +#endif + +/* + * Defines and prototypes for functions which take no arguments. + */ +#ifdef CFE_API_IMPL_NAMESPACE +int64_t __cfe_getticks(void); +#define cfe_getticks() __cfe_getticks() +#else +int64_t cfe_getticks(void); +#endif + +/* + * Defines and prototypes for the rest of the functions. + */ +#ifdef CFE_API_IMPL_NAMESPACE +#define cfe_close(a) __cfe_close(a) +#define cfe_cpu_start(a,b,c,d,e) __cfe_cpu_start(a,b,c,d,e) +#define cfe_cpu_stop(a) __cfe_cpu_stop(a) +#define cfe_enumenv(a,b,d,e,f) __cfe_enumenv(a,b,d,e,f) +#define cfe_enummem(a,b,c,d,e) __cfe_enummem(a,b,c,d,e) +#define cfe_exit(a,b) __cfe_exit(a,b) +#define cfe_flushcache(a) __cfe_cacheflush(a) +#define cfe_getdevinfo(a) __cfe_getdevinfo(a) +#define cfe_getenv(a,b,c) __cfe_getenv(a,b,c) +#define cfe_getfwinfo(a) __cfe_getfwinfo(a) +#define cfe_getstdhandle(a) __cfe_getstdhandle(a) +#define cfe_init(a,b) __cfe_init(a,b) +#define cfe_inpstat(a) __cfe_inpstat(a) +#define cfe_ioctl(a,b,c,d,e,f) __cfe_ioctl(a,b,c,d,e,f) +#define cfe_open(a) __cfe_open(a) +#define cfe_read(a,b,c) __cfe_read(a,b,c) +#define cfe_readblk(a,b,c,d) __cfe_readblk(a,b,c,d) +#define cfe_setenv(a,b) __cfe_setenv(a,b) +#define cfe_write(a,b,c) __cfe_write(a,b,c) +#define cfe_writeblk(a,b,c,d) __cfe_writeblk(a,b,c,d) +#endif /* CFE_API_IMPL_NAMESPACE */ + +int cfe_close(int handle); +int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1); +int cfe_cpu_stop(int cpu); +int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen); +int cfe_enummem(int idx, int flags, uint64_t * start, uint64_t * length, + uint64_t * type); +int cfe_exit(int warm, int status); +int cfe_flushcache(int flg); +int cfe_getdevinfo(char *name); +int cfe_getenv(char *name, char *dest, int destlen); +int cfe_getfwinfo(cfe_fwinfo_t * info); +int cfe_getstdhandle(int flg); +int cfe_init(uint64_t handle, uint64_t ept); +int cfe_inpstat(int handle); +int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, + int length, int *retlen, uint64_t offset); +int cfe_open(char *name); +int cfe_read(int handle, unsigned char *buffer, int length); +int cfe_readblk(int handle, int64_t offset, unsigned char *buffer, + int length); +int cfe_setenv(char *name, char *val); +int cfe_write(int handle, unsigned char *buffer, int length); +int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer, + int length); + +#endif /* CFE_API_H */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/cfe/cfe_api_int.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2000, 2001, 2002 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* ********************************************************************* + * + * Broadcom Common Firmware Environment (CFE) + * + * Device function prototypes File: cfe_api_int.h + * + * This header defines all internal types and macros for the + * library. This is stuff that's not exported to an app + * using the library. + * + * Authors: Mitch Lichtenberg, Chris Demetriou + * + ********************************************************************* */ + +#ifndef CFE_API_INT_H +#define CFE_API_INT_H + +/* ********************************************************************* + * Constants + ********************************************************************* */ + +#define CFE_CMD_FW_GETINFO 0 +#define CFE_CMD_FW_RESTART 1 +#define CFE_CMD_FW_BOOT 2 +#define CFE_CMD_FW_CPUCTL 3 +#define CFE_CMD_FW_GETTIME 4 +#define CFE_CMD_FW_MEMENUM 5 +#define CFE_CMD_FW_FLUSHCACHE 6 + +#define CFE_CMD_DEV_GETHANDLE 9 +#define CFE_CMD_DEV_ENUM 10 +#define CFE_CMD_DEV_OPEN 11 +#define CFE_CMD_DEV_INPSTAT 12 +#define CFE_CMD_DEV_READ 13 +#define CFE_CMD_DEV_WRITE 14 +#define CFE_CMD_DEV_IOCTL 15 +#define CFE_CMD_DEV_CLOSE 16 +#define CFE_CMD_DEV_GETINFO 17 + +#define CFE_CMD_ENV_ENUM 20 +#define CFE_CMD_ENV_GET 22 +#define CFE_CMD_ENV_SET 23 +#define CFE_CMD_ENV_DEL 24 + +#define CFE_CMD_MAX 32 + +#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */ + +/* ********************************************************************* + * Structures + ********************************************************************* */ + +typedef uint64_t cfe_xuint_t; +typedef int64_t cfe_xint_t; +typedef int64_t cfe_xptr_t; + +typedef struct xiocb_buffer_s { + cfe_xuint_t buf_offset; /* offset on device (bytes) */ + cfe_xptr_t buf_ptr; /* pointer to a buffer */ + cfe_xuint_t buf_length; /* length of this buffer */ + cfe_xuint_t buf_retlen; /* returned length (for read ops) */ + cfe_xuint_t buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */ +} xiocb_buffer_t; + +#define buf_devflags buf_ioctlcmd /* returned device info flags */ + +typedef struct xiocb_inpstat_s { + cfe_xuint_t inp_status; /* 1 means input available */ +} xiocb_inpstat_t; + +typedef struct xiocb_envbuf_s { + cfe_xint_t enum_idx; /* 0-based enumeration index */ + cfe_xptr_t name_ptr; /* name string buffer */ + cfe_xint_t name_length; /* size of name buffer */ + cfe_xptr_t val_ptr; /* value string buffer */ + cfe_xint_t val_length; /* size of value string buffer */ +} xiocb_envbuf_t; + +typedef struct xiocb_cpuctl_s { + cfe_xuint_t cpu_number; /* cpu number to control */ + cfe_xuint_t cpu_command; /* command to issue to CPU */ + cfe_xuint_t start_addr; /* CPU start address */ + cfe_xuint_t gp_val; /* starting GP value */ + cfe_xuint_t sp_val; /* starting SP value */ + cfe_xuint_t a1_val; /* starting A1 value */ +} xiocb_cpuctl_t; + +typedef struct xiocb_time_s { + cfe_xint_t ticks; /* current time in ticks */ +} xiocb_time_t; + +typedef struct xiocb_exitstat_s { + cfe_xint_t status; +} xiocb_exitstat_t; + +typedef struct xiocb_meminfo_s { + cfe_xint_t mi_idx; /* 0-based enumeration index */ + cfe_xint_t mi_type; /* type of memory block */ + cfe_xuint_t mi_addr; /* physical start address */ + cfe_xuint_t mi_size; /* block size */ +} xiocb_meminfo_t; + +typedef struct xiocb_fwinfo_s { + cfe_xint_t fwi_version; /* major, minor, eco version */ + cfe_xint_t fwi_totalmem; /* total installed mem */ + cfe_xint_t fwi_flags; /* various flags */ + cfe_xint_t fwi_boardid; /* board ID */ + cfe_xint_t fwi_bootarea_va; /* VA of boot area */ + cfe_xint_t fwi_bootarea_pa; /* PA of boot area */ + cfe_xint_t fwi_bootarea_size; /* size of boot area */ + cfe_xint_t fwi_reserved1; + cfe_xint_t fwi_reserved2; + cfe_xint_t fwi_reserved3; +} xiocb_fwinfo_t; + +typedef struct cfe_xiocb_s { + cfe_xuint_t xiocb_fcode; /* IOCB function code */ + cfe_xint_t xiocb_status; /* return status */ + cfe_xint_t xiocb_handle; /* file/device handle */ + cfe_xuint_t xiocb_flags; /* flags for this IOCB */ + cfe_xuint_t xiocb_psize; /* size of parameter list */ + union { + xiocb_buffer_t xiocb_buffer; /* buffer parameters */ + xiocb_inpstat_t xiocb_inpstat; /* input status parameters */ + xiocb_envbuf_t xiocb_envbuf; /* environment function parameters */ + xiocb_cpuctl_t xiocb_cpuctl; /* CPU control parameters */ + xiocb_time_t xiocb_time; /* timer parameters */ + xiocb_meminfo_t xiocb_meminfo; /* memory arena info parameters */ + xiocb_fwinfo_t xiocb_fwinfo; /* firmware information */ + xiocb_exitstat_t xiocb_exitstat; /* Exit Status */ + } plist; +} cfe_xiocb_t; + +#endif /* CFE_API_INT_H */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/cfe/cfe_error.h 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2000, 2001, 2002 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* ********************************************************************* + * + * Broadcom Common Firmware Environment (CFE) + * + * Error codes File: cfe_error.h + * + * CFE's global error code list is here. + * + * Author: Mitch Lichtenberg + * + ********************************************************************* */ + + +#define CFE_OK 0 +#define CFE_ERR -1 /* generic error */ +#define CFE_ERR_INV_COMMAND -2 +#define CFE_ERR_EOF -3 +#define CFE_ERR_IOERR -4 +#define CFE_ERR_NOMEM -5 +#define CFE_ERR_DEVNOTFOUND -6 +#define CFE_ERR_DEVOPEN -7 +#define CFE_ERR_INV_PARAM -8 +#define CFE_ERR_ENVNOTFOUND -9 +#define CFE_ERR_ENVREADONLY -10 + +#define CFE_ERR_NOTELF -11 +#define CFE_ERR_NOT32BIT -12 +#define CFE_ERR_WRONGENDIAN -13 +#define CFE_ERR_BADELFVERS -14 +#define CFE_ERR_NOTMIPS -15 +#define CFE_ERR_BADELFFMT -16 +#define CFE_ERR_BADADDR -17 + +#define CFE_ERR_FILENOTFOUND -18 +#define CFE_ERR_UNSUPPORTED -19 + +#define CFE_ERR_HOSTUNKNOWN -20 + +#define CFE_ERR_TIMEOUT -21 + +#define CFE_ERR_PROTOCOLERR -22 + +#define CFE_ERR_NETDOWN -23 +#define CFE_ERR_NONAMESERVER -24 + +#define CFE_ERR_NOHANDLES -25 +#define CFE_ERR_ALREADYBOUND -26 + +#define CFE_ERR_CANNOTSET -27 +#define CFE_ERR_NOMORE -28 +#define CFE_ERR_BADFILESYS -29 +#define CFE_ERR_FSNOTAVAIL -30 + +#define CFE_ERR_INVBOOTBLOCK -31 +#define CFE_ERR_WRONGDEVTYPE -32 +#define CFE_ERR_BBCHECKSUM -33 +#define CFE_ERR_BOOTPROGCHKSUM -34 + +#define CFE_ERR_LDRNOTAVAIL -35 + +#define CFE_ERR_NOTREADY -36 + +#define CFE_ERR_GETMEM -37 +#define CFE_ERR_SETMEM -38 + +#define CFE_ERR_NOTCONN -39 +#define CFE_ERR_ADDRINUSE -40 --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/cfe/console.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,91 @@ +#include +#include +#include +#include + +#include + +#include "cfe_api.h" +#include "cfe_error.h" + +extern int cfe_cons_handle; +static kdev_t cfe_consdev; + +#define SB1250_DUART_MINOR_BASE 192 + +static void cfe_console_write(struct console *cons, const char *str, + unsigned int count) +{ + int i, last, written; + + for (i=0,last=0; i MAX_RAM_SIZE) + || (initrd_pend > MAX_RAM_SIZE))) { + panic("initrd out of addressable memory"); + } + +#endif /* INITRD */ + + for (idx = 0; cfe_enummem(idx, mem_flags, &addr, &size, &type) != CFE_ERR_NOMORE; + idx++) { + rd_flag = 0; + if (type == CFE_MI_AVAILABLE) { + /* + * See if this block contains (any portion of) the + * ramdisk + */ +#ifdef CONFIG_BLK_DEV_INITRD + if (initrd_start) { + if ((initrd_pstart > addr) && + (initrd_pstart < (addr + size))) { + add_memory_region(addr, + initrd_pstart - addr, + BOOT_MEM_RAM); + rd_flag = 1; + } + if ((initrd_pend > addr) && + (initrd_pend < (addr + size))) { + add_memory_region(initrd_pend, + (addr + size) - initrd_pend, + BOOT_MEM_RAM); + rd_flag = 1; + } + } +#endif + if (!rd_flag) { + if (addr > MAX_RAM_SIZE) + continue; + if (addr+size > MAX_RAM_SIZE) + size = MAX_RAM_SIZE - (addr+size) + 1; + /* + * memcpy/__copy_user prefetch, which + * will cause a bus error for + * KSEG/KUSEG addrs not backed by RAM. + * Hence, reserve some padding for the + * prefetch distance. + */ + if (size > 512) + size -= 512; + add_memory_region(addr, size, BOOT_MEM_RAM); + } + board_mem_region_addrs[board_mem_region_count] = addr; + board_mem_region_sizes[board_mem_region_count] = size; + board_mem_region_count++; + if (board_mem_region_count == + SIBYTE_MAX_MEM_REGIONS) { + /* + * Too many regions. Need to configure more + */ + while(1); + } + } + } +#ifdef CONFIG_BLK_DEV_INITRD + if (initrd_start) { + add_memory_region(initrd_pstart, initrd_pend - initrd_pstart, + BOOT_MEM_RESERVED); + } +#endif +} + +#ifdef CONFIG_BLK_DEV_INITRD +static int __init initrd_setup(char *str) +{ + /* + *Initrd location comes in the form "@" + * e.g. initrd=3abfd@80010000. This is set up by the loader. + */ + char *tmp, *endptr; + unsigned long initrd_size; + for (tmp = str; *tmp != '@'; tmp++) { + if (!*tmp) { + goto fail; + } + } + *tmp = 0; + tmp++; + if (!*tmp) { + goto fail; + } + initrd_size = simple_strtoul(str, &endptr, 16); + if (*endptr) { + *(tmp-1) = '@'; + goto fail; + } + *(tmp-1) = '@'; + initrd_start = simple_strtoul(tmp, &endptr, 16); + if (*endptr) { + goto fail; + } + initrd_end = initrd_start + initrd_size; + printk("Found initrd of %lx@%lx\n", initrd_size, initrd_start); + return 1; + fail: + printk("Bad initrd argument. Disabling initrd\n"); + initrd_start = 0; + initrd_end = 0; + return 1; +} + +#endif + +/* + * prom_init is called just after the cpu type is determined, from init_arch() + */ +__init int prom_init(int argc, char **argv, char **envp, int *prom_vec) +{ + uint64_t cfe_ept, cfe_handle; + unsigned int cfe_eptseal; + + _machine_restart = (void (*)(char *))cfe_linux_exit; + _machine_halt = cfe_linux_exit; + _machine_power_off = cfe_linux_exit; + + /* + * Check if a loader was used; if NOT, the 4 arguments are + * what CFE gives us (handle, 0, EPT and EPTSEAL) + */ + if (argc < 0) { + cfe_handle = (uint64_t)(long)argc; + cfe_ept = (long)envp; + cfe_eptseal = (uint32_t)(unsigned long)prom_vec; + } else { + if ((int32_t)(long)prom_vec < 0) { + /* + * Old loader; all it gives us is the handle, + * so use the "known" entrypoint and assume + * the seal. + */ + cfe_handle = (uint64_t)(long)prom_vec; + cfe_ept = (uint64_t)((int32_t)0x9fc00500); + cfe_eptseal = CFE_EPTSEAL; + } else { + /* + * Newer loaders bundle the handle/ept/eptseal + * Note: prom_vec is in the loader's useg + * which is still alive in the TLB. + */ + cfe_handle = (uint64_t)((int32_t *)prom_vec)[0]; + cfe_ept = (uint64_t)((int32_t *)prom_vec)[2]; + cfe_eptseal = (unsigned int)((uint32_t *)prom_vec)[3]; + } + } + if (cfe_eptseal != CFE_EPTSEAL) { + /* XXXKW what? way too early to panic... */ + } + cfe_init(cfe_handle, cfe_ept); + /* + * Get the handle for (at least) prom_putchar, possibly for + * boot console + */ + cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE); + if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, CL_SIZE) < 0) { + if (argc < 0) { + /* + * It's OK for direct boot to not provide a + * command line + */ + strcpy(arcs_cmdline, "root=/dev/ram0 "); +#ifdef CONFIG_SIBYTE_PTSWARM + strcat(arcs_cmdline, "console=ttyS0,115200 "); +#endif + } else { + /* The loader should have set the command line */ + panic("LINUX_CMDLINE not defined in cfe."); + } + } + +#ifdef CONFIG_BLK_DEV_INITRD + { + char *ptr; + /* Need to find out early whether we've got an initrd. So scan + the list looking now */ + for (ptr = arcs_cmdline; *ptr; ptr++) { + while (*ptr == ' ') { + ptr++; + } + if (!strncmp(ptr, "initrd=", 7)) { + initrd_setup(ptr+7); + break; + } else { + while (*ptr && (*ptr != ' ')) { + ptr++; + } + } + } + } +#endif /* CONFIG_BLK_DEV_INITRD */ + + /* Not sure this is needed, but it's the safe way. */ + arcs_cmdline[CL_SIZE-1] = 0; + + mips_machgroup = MACH_GROUP_SIBYTE; + prom_meminit(); + + return 0; +} + +void prom_free_prom_memory(void) +{ + /* Not sure what I'm supposed to do here. Nothing, I think */ +} + +int page_is_ram(unsigned long pagenr) +{ + phys_t addr = pagenr << PAGE_SHIFT; + int i; + for (i = 0; i < board_mem_region_count; i++) { + if ((addr >= board_mem_region_addrs[i]) + && (addr < (board_mem_region_addrs[i] + board_mem_region_sizes[i]))) { + return 1; + } + } + return 0; +} + +void prom_putchar(char c) +{ + int ret; + + while ((ret = cfe_write(cfe_cons_handle, &c, 1)) == 0) + ; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/cfe/smp.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include + +#include + +#include "cfe_api.h" +#include "cfe_error.h" + +extern void asmlinkage smp_bootstrap(void); + +/* Boot all other cpus in the system, initialize them, and + bring them into the boot fn */ +int prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp) +{ + int retval; + + retval = cfe_cpu_start(cpu, &smp_bootstrap, sp, gp, 0); + if (retval != 0) { + printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval); + return 0; + } else { + return 1; + } +} + +void prom_init_secondary(void) +{ + /* Set up kseg0 to be cachable coherent */ + clear_c0_config(CONF_CM_CMASK); + set_c0_config(0x5); + + /* Enable interrupts for lines 0-4 */ + clear_c0_status(0xe000); + set_c0_status(0x1f01); +} + +/* + * Set up state, return the total number of cpus in the system, including + * the master + */ +void prom_setup_smp(void) +{ + int i; + + /* Use CFE to find out how many CPUs are available */ + for (i=1; i +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct sbprof_tb sbp; + +#define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES) + +/************************************************************************ + * Support for ZBbus sampling using the trace buffer + * + * We use the SCD performance counter interrupt, caused by a Zclk counter + * overflow, to trigger the start of tracing. + * + * We set the trace buffer to sample everything and freeze on + * overflow. + * + * We map the interrupt for trace_buffer_freeze to handle it on CPU 0. + * + ************************************************************************/ + +/* 100 samples per second on a 500 Mhz 1250 (default) */ +static u_int64_t tb_period = 2500000ULL; + +static void arm_tb(void) +{ + u_int64_t scdperfcnt; + u_int64_t next = (1ULL << 40) - tb_period; + /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to + trigger start of trace. XXX vary sampling period */ + out64(0, KSEG1 + A_SCD_PERF_CNT_1); + scdperfcnt = in64(KSEG1 + A_SCD_PERF_CNT_CFG); + /* Unfortunately, in Pass 2 we must clear all counters to knock down + a previous interrupt request. This means that bus profiling + requires ALL of the SCD perf counters. */ + out64((scdperfcnt & ~M_SPC_CFG_SRC1) | // keep counters 0,2,3 as is + M_SPC_CFG_ENABLE | // enable counting + M_SPC_CFG_CLEAR | // clear all counters + V_SPC_CFG_SRC1(1), // counter 1 counts cycles + KSEG1 + A_SCD_PERF_CNT_CFG); + out64(next, KSEG1 + A_SCD_PERF_CNT_1); + /* Reset the trace buffer */ + out64(M_SCD_TRACE_CFG_RESET, KSEG1 + A_SCD_TRACE_CFG); + out64(M_SCD_TRACE_CFG_FREEZE_FULL +#if 0 && defined(M_SCD_TRACE_CFG_FORCECNT) + /* XXXKW may want to expose control to the data-collector */ + | M_SCD_TRACE_CFG_FORCECNT +#endif + , KSEG1 + A_SCD_TRACE_CFG); + sbp.tb_armed = 1; +} + +static void sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs) +{ + int i; + DBG(printk(DEVNAME ": tb_intr\n")); + if (sbp.next_tb_sample < MAX_TB_SAMPLES) { + /* XXX should use XKPHYS to make writes bypass L2 */ + u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++]; + /* Read out trace */ + out64(M_SCD_TRACE_CFG_START_READ, KSEG1 + A_SCD_TRACE_CFG); + __asm__ __volatile__ ("sync" : : : "memory"); + /* Loop runs backwards because bundles are read out in reverse order */ + for (i = 256 * 6; i > 0; i -= 6) { + // Subscripts decrease to put bundle in the order + // t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi + p[i-1] = in64(KSEG1 + A_SCD_TRACE_READ); // read t2 hi + p[i-2] = in64(KSEG1 + A_SCD_TRACE_READ); // read t2 lo + p[i-3] = in64(KSEG1 + A_SCD_TRACE_READ); // read t1 hi + p[i-4] = in64(KSEG1 + A_SCD_TRACE_READ); // read t1 lo + p[i-5] = in64(KSEG1 + A_SCD_TRACE_READ); // read t0 hi + p[i-6] = in64(KSEG1 + A_SCD_TRACE_READ); // read t0 lo + } + if (!sbp.tb_enable) { + DBG(printk(DEVNAME ": tb_intr shutdown\n")); + out64(M_SCD_TRACE_CFG_RESET, KSEG1 + A_SCD_TRACE_CFG); + sbp.tb_armed = 0; + wake_up(&sbp.tb_sync); + } else { + arm_tb(); // knock down current interrupt and get another one later + } + } else { + /* No more trace buffer samples */ + DBG(printk(DEVNAME ": tb_intr full\n")); + out64(M_SCD_TRACE_CFG_RESET, KSEG1 + A_SCD_TRACE_CFG); + sbp.tb_armed = 0; + if (!sbp.tb_enable) { + wake_up(&sbp.tb_sync); + } + wake_up(&sbp.tb_read); + } +} + +static void sbprof_pc_intr(int irq, void *dev_id, struct pt_regs *regs) +{ + printk(DEVNAME ": unexpected pc_intr"); +} + +static int sbprof_zbprof_start(struct file *filp) +{ + u_int64_t scdperfcnt; + + if (sbp.tb_enable) + return -EBUSY; + + DBG(printk(DEVNAME ": starting\n")); + + sbp.tb_enable = 1; + sbp.next_tb_sample = 0; + filp->f_pos = 0; + + if (request_irq + (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, DEVNAME " trace freeze", &sbp)) { + return -EBUSY; + } + /* Make sure there isn't a perf-cnt interrupt waiting */ + scdperfcnt = in64(KSEG1 + A_SCD_PERF_CNT_CFG); + /* Disable and clear counters, override SRC_1 */ + out64((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) | + M_SPC_CFG_ENABLE | + M_SPC_CFG_CLEAR | + V_SPC_CFG_SRC1(1), + KSEG1 + A_SCD_PERF_CNT_CFG); + + /* We grab this interrupt to prevent others from trying to use + it, even though we don't want to service the interrupts + (they only feed into the trace-on-interrupt mechanism) */ + if (request_irq + (K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) { + free_irq(K_INT_TRACE_FREEZE, &sbp); + return -EBUSY; + } + + /* I need the core to mask these, but the interrupt mapper to + pass them through. I am exploiting my knowledge that + cp0_status masks out IP[5]. krw */ + out64(K_INT_MAP_I3, + KSEG1 + A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + (K_INT_PERF_CNT<<3)); + + /* Initialize address traps */ + out64(0, KSEG1 + A_ADDR_TRAP_UP_0); + out64(0, KSEG1 + A_ADDR_TRAP_UP_1); + out64(0, KSEG1 + A_ADDR_TRAP_UP_2); + out64(0, KSEG1 + A_ADDR_TRAP_UP_3); + + out64(0, KSEG1 + A_ADDR_TRAP_DOWN_0); + out64(0, KSEG1 + A_ADDR_TRAP_DOWN_1); + out64(0, KSEG1 + A_ADDR_TRAP_DOWN_2); + out64(0, KSEG1 + A_ADDR_TRAP_DOWN_3); + + out64(0, KSEG1 + A_ADDR_TRAP_CFG_0); + out64(0, KSEG1 + A_ADDR_TRAP_CFG_1); + out64(0, KSEG1 + A_ADDR_TRAP_CFG_2); + out64(0, KSEG1 + A_ADDR_TRAP_CFG_3); + + /* Initialize Trace Event 0-7 */ + // when interrupt + out64(M_SCD_TREVT_INTERRUPT, KSEG1 + A_SCD_TRACE_EVENT_0); + out64(0, KSEG1 + A_SCD_TRACE_EVENT_1); + out64(0, KSEG1 + A_SCD_TRACE_EVENT_2); + out64(0, KSEG1 + A_SCD_TRACE_EVENT_3); + out64(0, KSEG1 + A_SCD_TRACE_EVENT_4); + out64(0, KSEG1 + A_SCD_TRACE_EVENT_5); + out64(0, KSEG1 + A_SCD_TRACE_EVENT_6); + out64(0, KSEG1 + A_SCD_TRACE_EVENT_7); + + /* Initialize Trace Sequence 0-7 */ + // Start on event 0 (interrupt) + out64(V_SCD_TRSEQ_FUNC_START|0x0fff, + KSEG1 + A_SCD_TRACE_SEQUENCE_0); + // dsamp when d used | asamp when a used + out64(M_SCD_TRSEQ_ASAMPLE|M_SCD_TRSEQ_DSAMPLE|K_SCD_TRSEQ_TRIGGER_ALL, + KSEG1 + A_SCD_TRACE_SEQUENCE_1); + out64(0, KSEG1 + A_SCD_TRACE_SEQUENCE_2); + out64(0, KSEG1 + A_SCD_TRACE_SEQUENCE_3); + out64(0, KSEG1 + A_SCD_TRACE_SEQUENCE_4); + out64(0, KSEG1 + A_SCD_TRACE_SEQUENCE_5); + out64(0, KSEG1 + A_SCD_TRACE_SEQUENCE_6); + out64(0, KSEG1 + A_SCD_TRACE_SEQUENCE_7); + + /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */ + out64((1ULL << K_INT_PERF_CNT), KSEG1 + A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)); + + arm_tb(); + + DBG(printk(DEVNAME ": done starting\n")); + + return 0; +} + +static int sbprof_zbprof_stop(void) +{ + DBG(printk(DEVNAME ": stopping\n")); + + if (sbp.tb_enable) { + sbp.tb_enable = 0; + /* XXXKW there is a window here where the intr handler + may run, see the disable, and do the wake_up before + this sleep happens. */ + if (sbp.tb_armed) { + DBG(printk(DEVNAME ": wait for disarm\n")); + interruptible_sleep_on(&sbp.tb_sync); + DBG(printk(DEVNAME ": disarm complete\n")); + } + free_irq(K_INT_TRACE_FREEZE, &sbp); + free_irq(K_INT_PERF_CNT, &sbp); + } + + DBG(printk(DEVNAME ": done stopping\n")); + + return 0; +} + +static int sbprof_tb_open(struct inode *inode, struct file *filp) +{ + int minor; + + minor = MINOR(inode->i_rdev); + if (minor != 0) { + return -ENODEV; + } + if (sbp.open) { + return -EBUSY; + } + + memset(&sbp, 0, sizeof(struct sbprof_tb)); + sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES); + if (!sbp.sbprof_tbbuf) { + return -ENOMEM; + } + memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES); + init_waitqueue_head(&sbp.tb_sync); + init_waitqueue_head(&sbp.tb_read); + sbp.open = 1; + + return 0; +} + +static int sbprof_tb_release(struct inode *inode, struct file *filp) +{ + int minor; + + minor = MINOR(inode->i_rdev); + if (minor != 0 || !sbp.open) { + return -ENODEV; + } + + if (sbp.tb_armed || sbp.tb_enable) { + sbprof_zbprof_stop(); + } + + vfree(sbp.sbprof_tbbuf); + sbp.open = 0; + + return 0; +} + +static ssize_t sbprof_tb_read(struct file *filp, char *buf, + size_t size, loff_t *offp) +{ + int cur_sample, sample_off, cur_count, sample_left; + char *src; + int count = 0; + char *dest = buf; + long cur_off = *offp; + + count = 0; + cur_sample = cur_off / TB_SAMPLE_SIZE; + sample_off = cur_off % TB_SAMPLE_SIZE; + sample_left = TB_SAMPLE_SIZE - sample_off; + while (size && (cur_sample < sbp.next_tb_sample)) { + cur_count = size < sample_left ? size : sample_left; + src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off); + copy_to_user(dest, src, cur_count); + DBG(printk(DEVNAME ": read from sample %d, %d bytes\n", cur_sample, cur_count)); + size -= cur_count; + sample_left -= cur_count; + if (!sample_left) { + cur_sample++; + sample_off = 0; + sample_left = TB_SAMPLE_SIZE; + } else { + sample_off += cur_count; + } + cur_off += cur_count; + dest += cur_count; + count += cur_count; + } + *offp = cur_off; + + return count; +} + +static int sbprof_tb_ioctl(struct inode *inode, + struct file *filp, + unsigned int command, + unsigned long arg) +{ + int error = 0; + + switch (command) { + case SBPROF_ZBSTART: + error = sbprof_zbprof_start(filp); + break; + case SBPROF_ZBSTOP: + error = sbprof_zbprof_stop(); + break; + case SBPROF_ZBWAITFULL: + interruptible_sleep_on(&sbp.tb_read); + /* XXXKW check if interrupted? */ + return put_user(TB_FULL, (int *) arg); + default: + error = -EINVAL; + break; + } + + return error; +} + +static struct file_operations sbprof_tb_fops = { + .owner = THIS_MODULE, + .open = sbprof_tb_open, + .release = sbprof_tb_release, + .read = sbprof_tb_read, + .ioctl = sbprof_tb_ioctl, + .mmap = NULL, +}; + +static devfs_handle_t devfs_handle; + +#define UNDEF 0 +static unsigned long long pll_div_to_mhz[32] = { + UNDEF, + UNDEF, + UNDEF, + UNDEF, + 200, + 250, + 300, + 350, + 400, + 450, + 500, + 550, + 600, + 650, + 700, + 750, + 800, + 850, + 900, + 950, + 1000, + 1050, + 1100, + UNDEF, + UNDEF, + UNDEF, + UNDEF, + UNDEF, + UNDEF, + UNDEF, + UNDEF, + UNDEF +}; + +static int __init sbprof_tb_init(void) +{ + unsigned int pll_div; + + if (devfs_register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) { + printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n", + SBPROF_TB_MAJOR); + return -EIO; + } + devfs_handle = devfs_register(NULL, DEVNAME, + DEVFS_FL_DEFAULT, SBPROF_TB_MAJOR, 0, + S_IFCHR | S_IRUGO | S_IWUGO, + &sbprof_tb_fops, NULL); + sbp.open = 0; + pll_div = pll_div_to_mhz[G_SYS_PLL_DIV(in64(KSEG1 + A_SCD_SYSTEM_CFG))]; + if (pll_div != UNDEF) { + tb_period = (pll_div / 2) * 10000; + } else { + printk(KERN_INFO DEVNAME ": strange PLL divide\n"); + } + printk(KERN_INFO DEVNAME ": initialized - tb_period = %lld\n", tb_period); + return 0; +} + +static void __exit sbprof_tb_cleanup(void) +{ + devfs_unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME); + devfs_unregister(devfs_handle); +} + +module_init(sbprof_tb_init); +module_exit(sbprof_tb_cleanup); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/sb1250/bus_watcher.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,232 @@ +/* + * Copyright (C) 2002,2003 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * The Bus Watcher monitors internal bus transactions and maintains + * counts of transactions with error status, logging details and + * causing one of several interrupts. This driver provides a handler + * for those interrupts which aggregates the counts (to avoid + * saturating the 8-bit counters) and provides a presence in + * /proc/bus_watcher if PROC_FS is on. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +struct bw_stats_struct { + uint64_t status; + uint32_t l2_err; + uint32_t memio_err; + int status_printed; + unsigned long l2_cor_d; + unsigned long l2_bad_d; + unsigned long l2_cor_t; + unsigned long l2_bad_t; + unsigned long mem_cor_d; + unsigned long mem_bad_d; + unsigned long bus_error; +} bw_stats; + + +static void print_summary(uint32_t status, uint32_t l2_err, + uint32_t memio_err) +{ + printk("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); + printk("\nLast recorded signature:\n"); + printk("Request %02x from %d, answered by %d with Dcode %d\n", + (unsigned int)(G_SCD_BERR_TID(status) & 0x3f), + (int)(G_SCD_BERR_TID(status) >> 6), + (int)G_SCD_BERR_RID(status), + (int)G_SCD_BERR_DCODE(status)); +} + +/* + * check_bus_watcher is exported for use in situations where we want + * to see the most recent status of the bus watcher, which might have + * already been destructively read out of the registers. + * + * notes: this is currently used by the cache error handler + * should provide locking against the interrupt handler + */ +void check_bus_watcher(void) +{ + u32 status, l2_err, memio_err; + +#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS + /* Destructive read, clears register and interrupt */ + status = csr_in32(IO_SPACE_BASE | A_SCD_BUS_ERR_STATUS); +#else + /* Use non-destructive register */ + status = csr_in32(IO_SPACE_BASE | A_SCD_BUS_ERR_STATUS_DEBUG); +#endif + if (!(status & 0x7fffffff)) { + printk("Using last values reaped by bus watcher driver\n"); + status = bw_stats.status; + l2_err = bw_stats.l2_err; + memio_err = bw_stats.memio_err; + } else { + l2_err = csr_in32(IO_SPACE_BASE | A_BUS_L2_ERRORS); + memio_err = csr_in32(IO_SPACE_BASE | A_BUS_MEM_IO_ERRORS); + } + if (status & ~(1UL << 31)) + print_summary(status, l2_err, memio_err); + else + printk("Bus watcher indicates no error\n"); +} + +static int bw_print_buffer(char *page, struct bw_stats_struct *stats) +{ + int len; + + len = sprintf(page, "SiByte Bus Watcher statistics\n"); + len += sprintf(page+len, "-----------------------------\n"); + len += sprintf(page+len, "L2-d-cor %8ld\nL2-d-bad %8ld\n", + stats->l2_cor_d, stats->l2_bad_d); + len += sprintf(page+len, "L2-t-cor %8ld\nL2-t-bad %8ld\n", + stats->l2_cor_t, stats->l2_bad_t); + len += sprintf(page+len, "MC-d-cor %8ld\nMC-d-bad %8ld\n", + stats->mem_cor_d, stats->mem_bad_d); + len += sprintf(page+len, "IO-err %8ld\n", stats->bus_error); + len += sprintf(page+len, "\nLast recorded signature:\n"); + len += sprintf(page+len, "Request %02x from %d, answered by %d with Dcode %d\n", + (unsigned int)(G_SCD_BERR_TID(stats->status) & 0x3f), + (int)(G_SCD_BERR_TID(stats->status) >> 6), + (int)G_SCD_BERR_RID(stats->status), + (int)G_SCD_BERR_DCODE(stats->status)); + /* XXXKW indicate multiple errors between printings, or stats + collection (or both)? */ + if (stats->status & M_SCD_BERR_MULTERRS) + len += sprintf(page+len, "Multiple errors observed since last check.\n"); + if (stats->status_printed) { + len += sprintf(page+len, "(no change since last printing)\n"); + } else { + stats->status_printed = 1; + } + + return len; +} + +#ifdef CONFIG_PROC_FS + +/* For simplicity, I want to assume a single read is required each + time */ +static int bw_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + int len; + + if (off == 0) { + len = bw_print_buffer(page, data); + *start = page; + } else { + len = 0; + *eof = 1; + } + return len; +} + +static void create_proc_decoder(struct bw_stats_struct *stats) +{ + struct proc_dir_entry *ent; + + ent = create_proc_read_entry("bus_watcher", S_IWUSR | S_IRUGO, NULL, + bw_read_proc, stats); + if (!ent) { + printk(KERN_INFO "Unable to initialize bus_watcher /proc entry\n"); + return; + } +} + +#endif /* CONFIG_PROC_FS */ + +/* + * sibyte_bw_int - handle bus watcher interrupts and accumulate counts + * + * notes: possible re-entry due to multiple sources + * should check/indicate saturation + */ +static void sibyte_bw_int(int irq, void *data, struct pt_regs *regs) +{ + struct bw_stats_struct *stats = data; + unsigned long cntr; +#ifndef CONFIG_PROC_FS + char bw_buf[1024]; +#endif + + /* Destructive read, clears register and interrupt */ + stats->status = csr_in32(IO_SPACE_BASE | A_SCD_BUS_ERR_STATUS); + stats->status_printed = 0; + + stats->l2_err = cntr = csr_in32(IO_SPACE_BASE | A_BUS_L2_ERRORS); + stats->l2_cor_d += G_SCD_L2ECC_CORR_D(cntr); + stats->l2_bad_d += G_SCD_L2ECC_BAD_D(cntr); + stats->l2_cor_t += G_SCD_L2ECC_CORR_T(cntr); + stats->l2_bad_t += G_SCD_L2ECC_BAD_T(cntr); + csr_out32(0, IO_SPACE_BASE | A_BUS_L2_ERRORS); + + stats->memio_err = cntr = csr_in32(IO_SPACE_BASE | A_BUS_MEM_IO_ERRORS); + stats->mem_cor_d += G_SCD_MEM_ECC_CORR(cntr); + stats->mem_bad_d += G_SCD_MEM_ECC_BAD(cntr); + stats->bus_error += G_SCD_MEM_BUSERR(cntr); + csr_out32(0, IO_SPACE_BASE | A_BUS_MEM_IO_ERRORS); + +#ifndef CONFIG_PROC_FS + bw_print_buffer(bw_buf, stats); + printk(bw_buf); +#endif +} + +int __init sibyte_bus_watcher(void) +{ + memset(&bw_stats, 0, sizeof(struct bw_stats_struct)); + bw_stats.status_printed = 1; + + if (request_irq(K_INT_BAD_ECC, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) { + printk("Failed to register bus watcher BAD_ECC irq\n"); + return -1; + } + if (request_irq(K_INT_COR_ECC, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) { + free_irq(K_INT_BAD_ECC, &bw_stats); + printk("Failed to register bus watcher COR_ECC irq\n"); + return -1; + } + if (request_irq(K_INT_IO_BUS, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) { + free_irq(K_INT_BAD_ECC, &bw_stats); + free_irq(K_INT_COR_ECC, &bw_stats); + printk("Failed to register bus watcher IO_BUS irq\n"); + return -1; + } + +#ifdef CONFIG_PROC_FS + create_proc_decoder(&bw_stats); +#endif + + return 0; +} + +__initcall(sibyte_bus_watcher); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/sb1250/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,419 @@ +/* + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* + * These are the routines that handle all the low level interrupt stuff. + * Actions handled here are: initialization of the interrupt map, requesting of + * interrupt lines by handlers, dispatching if interrupts to handlers, probing + * for interrupt lines + */ + + +#define shutdown_sb1250_irq disable_sb1250_irq +static void end_sb1250_irq(unsigned int irq); +static void enable_sb1250_irq(unsigned int irq); +static void disable_sb1250_irq(unsigned int irq); +static unsigned int startup_sb1250_irq(unsigned int irq); +static void ack_sb1250_irq(unsigned int irq); +#ifdef CONFIG_SMP +static void sb1250_set_affinity(unsigned int irq, unsigned long mask); +#endif + +#ifdef CONFIG_SIBYTE_HAS_LDT +extern unsigned long ldt_eoi_space; +#endif + +#ifdef CONFIG_KGDB +extern void breakpoint(void); +extern void set_debug_traps(void); + +/* kgdb is on when configured. Pass "nokgdb" kernel arg to turn it off */ +static int kgdb_flag = 1; +static int __init nokgdb(char *str) +{ + kgdb_flag = 0; +} +__setup("nokgdb", nokgdb); +#endif + +static struct hw_interrupt_type sb1250_irq_type = { + "SB1250-IMR", + startup_sb1250_irq, + shutdown_sb1250_irq, + enable_sb1250_irq, + disable_sb1250_irq, + ack_sb1250_irq, + end_sb1250_irq, +#ifdef CONFIG_SMP + sb1250_set_affinity +#else + NULL +#endif +}; + +/* Store the CPU id (not the logical number) */ +int sb1250_irq_owner[SB1250_NR_IRQS]; + +spinlock_t sb1250_imr_lock = SPIN_LOCK_UNLOCKED; + +void sb1250_mask_irq(int cpu, int irq) +{ + unsigned long flags; + u64 cur_ints; + + spin_lock_irqsave(&sb1250_imr_lock, flags); + cur_ints = __in64(KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK); + cur_ints |= (((u64) 1) << irq); + __out64(cur_ints, KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK); + spin_unlock_irqrestore(&sb1250_imr_lock, flags); +} + +void sb1250_unmask_irq(int cpu, int irq) +{ + unsigned long flags; + u64 cur_ints; + + spin_lock_irqsave(&sb1250_imr_lock, flags); + cur_ints = __in64(KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK); + cur_ints &= ~(((u64) 1) << irq); + __out64(cur_ints, KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK); + spin_unlock_irqrestore(&sb1250_imr_lock, flags); +} + +#ifdef CONFIG_SMP +static void sb1250_set_affinity(unsigned int irq, unsigned long mask) +{ + int i = 0, old_cpu, cpu, int_on; + u64 cur_ints; + irq_desc_t *desc = irq_desc + irq; + unsigned int flags; + + while (mask) { + if (mask & 1) { + mask >>= 1; + break; + } + mask >>= 1; + i++; + } + + if (mask) { + printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); + return; + } + + /* Convert logical CPU to physical CPU */ + cpu = cpu_logical_map(i); + + /* Protect against other affinity changers and IMR manipulation */ + spin_lock_irqsave(&desc->lock, flags); + spin_lock(&sb1250_imr_lock); + + /* Swizzle each CPU's IMR (but leave the IP selection alone) */ + old_cpu = sb1250_irq_owner[irq]; + cur_ints = __in64(KSEG1 + A_IMR_MAPPER(old_cpu) + R_IMR_INTERRUPT_MASK); + int_on = !(cur_ints & (((u64) 1) << irq)); + if (int_on) { + /* If it was on, mask it */ + cur_ints |= (((u64) 1) << irq); + __out64(cur_ints, KSEG1 + A_IMR_MAPPER(old_cpu) + R_IMR_INTERRUPT_MASK); + } + sb1250_irq_owner[irq] = cpu; + if (int_on) { + /* unmask for the new CPU */ + cur_ints = __in64(KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK); + cur_ints &= ~(((u64) 1) << irq); + __out64(cur_ints, KSEG1 + A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK); + } + spin_unlock(&sb1250_imr_lock); + spin_unlock_irqrestore(&desc->lock, flags); +} +#endif + + +/* Defined in arch/mips/sibyte/sb1250/irq_handler.S */ +extern void sb1250_irq_handler(void); + +/*****************************************************************************/ + +static unsigned int startup_sb1250_irq(unsigned int irq) +{ + sb1250_unmask_irq(sb1250_irq_owner[irq], irq); + + return 0; /* never anything pending */ +} + + +static void disable_sb1250_irq(unsigned int irq) +{ + sb1250_mask_irq(sb1250_irq_owner[irq], irq); +} + +static void enable_sb1250_irq(unsigned int irq) +{ + sb1250_unmask_irq(sb1250_irq_owner[irq], irq); +} + + +static void ack_sb1250_irq(unsigned int irq) +{ +#ifdef CONFIG_SIBYTE_HAS_LDT + u64 pending; + + /* + * If the interrupt was an HT interrupt, now is the time to + * clear it. NOTE: we assume the HT bridge was set up to + * deliver the interrupts to all CPUs (which makes affinity + * changing easier for us) + */ + pending = in64(KSEG1 + A_IMR_REGISTER(sb1250_irq_owner[irq], + R_IMR_LDT_INTERRUPT)); + pending &= ((u64)1 << (irq)); + if (pending) { + int i; + for (i=0; i= SB1250_NR_IRQS) + return -EINVAL; + + spin_lock_irqsave(&desc->lock,flags); + /* Don't allow sharing at all for these */ + if (desc->action != NULL) + retval = -EBUSY; + else { + desc->action = &sb1250_dummy_action; + desc->depth = 0; + } + spin_unlock_irqrestore(&desc->lock,flags); + return 0; +} + +/* + * init_IRQ is called early in the boot sequence from init/main.c. It + * is responsible for setting up the interrupt mapper and installing the + * handler that will be responsible for dispatching interrupts to the + * "right" place. + */ +/* + * For now, map all interrupts to IP[2]. We could save + * some cycles by parceling out system interrupts to different + * IP lines, but keep it simple for bringup. We'll also direct + * all interrupts to a single CPU; we should probably route + * PCI and LDT to one cpu and everything else to the other + * to balance the load a bit. + * + * On the second cpu, everything is set to IP5, which is + * ignored, EXCEPT the mailbox interrupt. That one is + * set to IP[2] so it is handled. This is needed so we + * can do cross-cpu function calls, as requred by SMP + */ + +#define IMR_IP2_VAL K_INT_MAP_I0 +#define IMR_IP3_VAL K_INT_MAP_I1 +#define IMR_IP4_VAL K_INT_MAP_I2 +#define IMR_IP5_VAL K_INT_MAP_I3 +#define IMR_IP6_VAL K_INT_MAP_I4 + +void __init init_IRQ(void) +{ + + unsigned int i; + u64 tmp; + unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | + STATUSF_IP1 | STATUSF_IP0; + + /* Default everything to IP2 */ + for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ + out64(IMR_IP2_VAL, + KSEG1 + A_IMR_REGISTER(0, + R_IMR_INTERRUPT_MAP_BASE) + + (i << 3)); + out64(IMR_IP2_VAL, + KSEG1 + A_IMR_REGISTER(1, + R_IMR_INTERRUPT_MAP_BASE) + + (i << 3)); + } + + init_sb1250_irqs(); + + /* + * Map the high 16 bits of the mailbox registers to IP[3], for + * inter-cpu messages + */ + /* Was I1 */ + out64(IMR_IP3_VAL, KSEG1 + A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + + (K_INT_MBOX_0 << 3)); + out64(IMR_IP3_VAL, KSEG1 + A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + + (K_INT_MBOX_0 << 3)); + + /* Clear the mailboxes. The firmware may leave them dirty */ + out64(0xffffffffffffffff, + KSEG1 + A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)); + out64(0xffffffffffffffff, + KSEG1 + A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)); + + /* Mask everything except the mailbox registers for both cpus */ + tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); + out64(tmp, KSEG1 + A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)); + out64(tmp, KSEG1 + A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)); + + sb1250_steal_irq(K_INT_MBOX_0); + + /* + * Note that the timer interrupts are also mapped, but this is + * done in sb1250_time_init() + */ + +#ifdef CONFIG_BCM1250_PROF + imask |= STATUSF_IP7; +#endif +#ifdef CONFIG_KGDB + imask |= STATUSF_IP6; +#endif + /* Enable necessary IPs, disable the rest */ + change_c0_status(ST0_IM, imask); + set_except_vector(0, sb1250_irq_handler); + +#ifdef CONFIG_KGDB + if (kgdb_flag) { + /* Setup uart 1 settings, mapper */ + out64(M_DUART_IMR_BRK, KSEG1 + A_DUART + R_DUART_IMR_B); + + out64(IMR_IP6_VAL, + KSEG1 + A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + (K_INT_UART_1<<3)); + tmp = in64(KSEG1 + A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)); + tmp &= ~(1< + +extern void set_async_breakpoint(unsigned int epc); + +#define duart_out(reg, val) out64(val, KSEG1 + A_DUART_CHANREG(1,reg)) +#define duart_in(reg) in64(KSEG1 + A_DUART_CHANREG(1,reg)) + +void sb1250_kgdb_interrupt(struct pt_regs *regs) +{ + /* + * Clear break-change status (allow some time for the remote + * host to stop the break, since we would see another + * interrupt on the end-of-break too) + */ + mdelay(500); + duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT | + M_DUART_RX_EN | M_DUART_TX_EN); + if (!user_mode(regs)) + set_async_breakpoint(regs->cp0_epc); +} +#endif /* CONFIG_KGDB */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/sb1250/irq_handler.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,154 @@ +/* + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * sb1250_handle_int() is the routine that is actually called when an interrupt + * occurs. It is installed as the exception vector handler in init_IRQ() in + * arch/mips/sibyte/sb1250/irq.c + * + * In the handle we figure out which interrupts need handling, and use that to + * call the dispatcher, which will take care of actually calling registered + * handlers + * + * Note that we take care of all raised interrupts in one go at the handler. + * This is more BSDish than the Indy code, and also, IMHO, more sane. + */ +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * What a pain. We have to be really careful saving the upper 32 bits of any + * register across function calls if we don't want them trashed--since were + * running in -o32, the calling routing never saves the full 64 bits of a + * register across a function call. Being the interrupt handler, we're + * guaranteed that interrupts are disabled during this code so we don't have + * to worry about random interrupts blasting the high 32 bits. + */ + + .text + .set push + .set noreorder + .set noat + #.set mips64 + .set mips4 + .align 5 + NESTED(sb1250_irq_handler, PT_SIZE, sp) + SAVE_ALL + CLI + +#ifdef CONFIG_SIBYTE_SB1250_PROF + /* Set compare to count to silence count/compare timer interrupts */ + mfc0 t1, CP0_COUNT + mtc0 t1, CP0_COMPARE /* pause to clear IP[7] bit of cause ? */ +#endif + /* Read cause */ + mfc0 s0, CP0_CAUSE + +#ifdef CONFIG_SIBYTE_SB1250_PROF + /* Cpu performance counter interrupt is routed to IP[7] */ + andi t1, s0, CAUSEF_IP7 + beqz t1, 0f + srl t1, s0, (CAUSEB_BD-2) /* Shift BD bit to bit 2 */ + and t1, t1, 0x4 /* mask to get just BD bit */ + mfc0 a0, CP0_EPC + jal sbprof_cpu_intr + addu a0, a0, t1 /* a0 = EPC + (BD ? 4 : 0) */ + /* Re-enable interrupts here so that events due to sbprof_cpu_intr + get charged to ret_from_irq (via a recursive interrupt) + rather than the restart pc. */ + mfc0 t0, CP0_STATUS + or t0, ST0_IE + j ret_from_irq + mtc0 t0, CP0_STATUS # delay slot +0: +#endif + /* Timer interrupt is routed to IP[4] */ + andi t1, s0, CAUSEF_IP4 + beqz t1, 1f + nop + jal sb1250_timer_interrupt + move a0, sp /* Pass the registers along */ + j ret_from_irq + nop # delay slot +1: + +#ifdef CONFIG_SMP + /* Mailbox interrupt is routed to IP[3] */ + andi t1, s0, CAUSEF_IP3 + beqz t1, 2f + nop + jal sb1250_mailbox_interrupt + move a0, sp + j ret_from_irq + nop # delay slot +2: +#endif + +#ifdef CONFIG_KGDB + /* KGDB (uart 1) interrupt is routed to IP[6] */ + andi t1, s0, CAUSEF_IP6 + beqz t1, 1f + nop # delay slot + jal sb1250_kgdb_interrupt + move a0, sp + j ret_from_irq + nop # delay slot +1: +#endif + + and t1, s0, CAUSEF_IP2 + beqz t1, 4f + nop + + /* + * Default...we've hit an IP[2] interrupt, which means we've got to + * check the 1250 interrupt registers to figure out what to do + * Need to detect which CPU we're on, now that smp_affinity is supported. + */ + la v0, KSEG1 + A_IMR_CPU0_BASE +#ifdef CONFIG_SMP + lw t1, TI_CPU($28) + sll t1, IMR_REGISTER_SPACING_SHIFT + addu v0, t1 +#endif + ld s0, R_IMR_INTERRUPT_STATUS_BASE(v0) /* read IP[2] status */ + + beqz s0, 4f /* No interrupts. Return */ + move a1, sp + +3: #dclz s1, s0 /* Find the next interrupt */ + .word 0x72118824 # dclz s1, s0 + dsubu a0, zero, s1 + daddiu a0, a0, 63 + jal do_IRQ + nop + +4: j ret_from_irq + nop + + .set pop + END(sb1250_irq_handler) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/sb1250/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,8 @@ +obj-y := setup.o irq.o irq_handler.o time.o + +obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_SIBYTE_TBPROF) += bcm1250_tbprof.o +obj-$(CONFIG_SIBYTE_STANDALONE) += prom.o +obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o + +EXTRA_AFLAGS := $(CFLAGS) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/sb1250/prom.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +extern char arcs_cmdline[]; + +#ifdef CONFIG_EMBEDDED_RAMDISK +/* These are symbols defined by the ramdisk linker script */ +extern unsigned char __rd_start; +extern unsigned char __rd_end; +#endif + +#define MAX_RAM_SIZE ((CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024) - 1) + +static __init void prom_meminit(void) +{ +#ifdef CONFIG_BLK_DEV_INITRD + unsigned long initrd_pstart; + unsigned long initrd_pend; + +#ifdef CONFIG_EMBEDDED_RAMDISK + /* If we're using an embedded ramdisk, then __rd_start and __rd_end + are defined by the linker to be on either side of the ramdisk + area. Otherwise, initrd_start should be defined by kernel command + line arguments */ + if (initrd_start == 0) { + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; + } +#endif + + initrd_pstart = __pa(initrd_start); + initrd_pend = __pa(initrd_end); + if (initrd_start && + ((initrd_pstart > MAX_RAM_SIZE) + || (initrd_pend > MAX_RAM_SIZE))) { + panic("initrd out of addressable memory"); + } + + add_memory_region(0, initrd_pstart, + BOOT_MEM_RAM); + add_memory_region(initrd_pstart, initrd_pend - initrd_pstart, + BOOT_MEM_RESERVED); + add_memory_region(initrd_pend, + (CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024) - initrd_pend, + BOOT_MEM_RAM); +#else + add_memory_region(0, CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024, + BOOT_MEM_RAM); +#endif +} + +void prom_cpu0_exit(void *unused) +{ + while (1) ; +} + +static void prom_linux_exit(void) +{ +#ifdef CONFIG_SMP + if (smp_processor_id()) { + smp_call_function(prom_cpu0_exit,NULL,1,1); + } +#endif + while(1); +} + +/* + * prom_init is called just after the cpu type is determined, from init_arch() + */ +__init int prom_init(int argc, char **argv, char **envp, int *prom_vec) +{ + _machine_restart = (void (*)(char *))prom_linux_exit; + _machine_halt = prom_linux_exit; + _machine_power_off = prom_linux_exit; + + strcpy(arcs_cmdline, "root=/dev/ram0 "); + + mips_machgroup = MACH_GROUP_SIBYTE; + prom_meminit(); + + return 0; +} + +void prom_free_prom_memory(void) +{ + /* Not sure what I'm supposed to do here. Nothing, I think */ +} + +int page_is_ram(unsigned long pagenr) +{ + phys_t addr = pagenr << PAGE_SHIFT; + return (addr < (CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024)); +} + +void prom_putchar(char c) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/sb1250/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +unsigned int sb1_pass; +unsigned int soc_pass; +unsigned int soc_type; +unsigned int periph_rev; + +static char *soc_str; +static char *pass_str; +static unsigned int war_pass; /* XXXKW don't overload PASS defines? */ + +static inline int setup_bcm1250(void); +static inline int setup_bcm112x(void); + +/* Setup code likely to be common to all SiByte platforms */ + +static inline int sys_rev_decode(void) +{ + int ret = 0; + + war_pass = soc_pass; + switch (soc_type) { + case K_SYS_SOC_TYPE_BCM1250: + case K_SYS_SOC_TYPE_BCM1250_ALT: + case K_SYS_SOC_TYPE_BCM1250_ALT2: + soc_str = "BCM1250"; + ret = setup_bcm1250(); + break; + case K_SYS_SOC_TYPE_BCM1120: + soc_str = "BCM1120"; + ret = setup_bcm112x(); + break; + case K_SYS_SOC_TYPE_BCM1125: + soc_str = "BCM1125"; + ret = setup_bcm112x(); + break; + case K_SYS_SOC_TYPE_BCM1125H: + soc_str = "BCM1125H"; + ret = setup_bcm112x(); + break; + default: + prom_printf("Unknown SOC type %x\n", soc_type); + ret = 1; + break; + } + return ret; +} + +static inline int setup_bcm1250(void) +{ + int ret = 0; + + switch (soc_pass) { + case K_SYS_REVISION_BCM1250_PASS1: + periph_rev = 1; + pass_str = "Pass 1"; + break; + case K_SYS_REVISION_BCM1250_A10: + periph_rev = 2; + pass_str = "A8/A10"; + /* XXXKW different war_pass? */ + war_pass = K_SYS_REVISION_BCM1250_PASS2; + break; + case K_SYS_REVISION_BCM1250_PASS2_2: + periph_rev = 2; + pass_str = "B1"; + break; + case K_SYS_REVISION_BCM1250_B2: + periph_rev = 2; + pass_str = "B2"; + war_pass = K_SYS_REVISION_BCM1250_PASS2_2; + break; + case K_SYS_REVISION_BCM1250_PASS3: + periph_rev = 3; + pass_str = "C0"; + break; + default: + if (soc_pass < K_SYS_REVISION_BCM1250_PASS2_2) { + periph_rev = 2; + pass_str = "A0-A6"; + war_pass = K_SYS_REVISION_BCM1250_PASS2; + } else { + prom_printf("Unknown BCM1250 rev %x\n", soc_pass); + ret = 1; + } + break; + } + return ret; +} + +static inline int setup_bcm112x(void) +{ + int ret = 0; + + switch (soc_pass) { + case 0: + /* Early build didn't have revid set */ + periph_rev = 3; + pass_str = "A1"; + war_pass = K_SYS_REVISION_BCM112x_A1; + break; + case K_SYS_REVISION_BCM112x_A1: + periph_rev = 3; + pass_str = "A1"; + break; + case K_SYS_REVISION_BCM112x_A2: + periph_rev = 3; + pass_str = "A2"; + break; + default: + prom_printf("Unknown %s rev %x\n", soc_str, soc_pass); + ret = 1; + } + return ret; +} + +void sb1250_setup(void) +{ + uint64_t sys_rev; + int bad_config = 0; + + sb1_pass = read_c0_prid() & 0xff; + sys_rev = in64(IO_SPACE_BASE | A_SCD_SYSTEM_REVISION); + soc_type = SYS_SOC_TYPE(sys_rev); + soc_pass = G_SYS_REVISION(sys_rev); + + if (sys_rev_decode()) { + prom_printf("Restart after failure to identify SiByte chip\n"); + machine_restart(NULL); + } + + prom_printf("SiByte %s %s (SB1 rev %d)\n", + soc_str, pass_str, sb1_pass); + prom_printf("Board type: %s\n", get_system_type()); + + switch(war_pass) { + case K_SYS_REVISION_BCM1250_PASS1: +#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS + prom_printf("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n"); + bad_config = 1; +#endif + break; + case K_SYS_REVISION_BCM1250_PASS2: + /* Pass 2 - easiest as default for now - so many numbers */ +#if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) + prom_printf("@@@@ This is a BCM1250 A3-A10 board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n"); + bad_config = 1; +#endif +#ifdef CONFIG_CPU_HAS_PREFETCH + prom_printf("@@@@ Prefetches may be enabled in this kernel, but are buggy on this board. @@@@\n"); + bad_config = 1; +#endif + break; + case K_SYS_REVISION_BCM1250_PASS2_2: +#ifndef CONFIG_SB1_PASS_2_WORKAROUNDS + prom_printf("@@@@ This is a BCM1250 B1/B2. board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n"); + bad_config = 1; +#endif +#if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || !defined(CONFIG_CPU_HAS_PREFETCH) + prom_printf("@@@@ This is a BCM1250 B1/B2, but the kernel is conservatively configured for an 'A' stepping. @@@@\n"); +#endif + break; + default: + break; + } + if (bad_config) { + prom_printf("Invalid configuration for this chip.\n"); + machine_restart(NULL); + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/sb1250/smp.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +extern irqreturn_t smp_call_function_interrupt(int irq, void *dev, + struct pt_regs *regs); +extern void smp_tune_scheduling(void); + +/* + * These are routines for dealing with the sb1250 smp capabilities + * independent of board/firmware + */ + +static u64 mailbox_set_regs[] = { + KSEG1 + A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU, + KSEG1 + A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU +}; + +static u64 mailbox_clear_regs[] = { + KSEG1 + A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU, + KSEG1 + A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU +}; + +static u64 mailbox_regs[] = { + KSEG1 + A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU, + KSEG1 + A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU +}; + + +/* + * Simple enough; everything is set up, so just poke the appropriate mailbox + * register, and we should be set + */ +void core_send_ipi(int cpu, unsigned int action) +{ + out64((((u64)action)<< 48), mailbox_set_regs[cpu]); +} + + +void sb1250_smp_finish(void) +{ + extern void sb1_sanitize_tlb(void); + + sb1_sanitize_tlb(); + sb1250_time_init(); +} + +void sb1250_mailbox_interrupt(struct pt_regs *regs) +{ + int cpu = smp_processor_id(); + unsigned int action; + + kstat_cpu(cpu).irqs[K_INT_MBOX_0]++; + /* Load the mailbox register to figure out what we're supposed to do */ + action = (in64(mailbox_regs[cpu]) >> 48) & 0xffff; + + /* Clear the mailbox to clear the interrupt */ + out64(((u64)action)<<48, mailbox_clear_regs[cpu]); + + /* + * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the + * interrupt will do the reschedule for us + */ + + if (action & SMP_CALL_FUNCTION) { + smp_call_function_interrupt(0, NULL, regs); + } +} + +extern atomic_t cpus_booted; +extern void prom_setup_smp(void); +extern int prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp); + +void __init smp_boot_cpus(void) +{ + int cur_cpu = 0; + int cpu; + + prom_setup_smp(); + init_new_context(current, &init_mm); + current_thread_info()->cpu = 0; + cpu_data[0].udelay_val = loops_per_jiffy; + cpu_data[0].asid_cache = ASID_FIRST_VERSION; + CPUMASK_CLRALL(cpu_online_map); + CPUMASK_SETB(cpu_online_map, 0); + atomic_set(&cpus_booted, 1); /* Master CPU is already booted... */ + smp_tune_scheduling(); + + /* + * This loop attempts to compensate for "holes" in the CPU + * numbering. It's overkill, but general. + */ + for (cpu = 1; cpu < num_online_cpus(); ) { + struct task_struct *idle; + struct pt_regs regs; + int retval; + printk("Starting CPU %d... ", cpu); + + /* Spawn a new process normally. Grab a pointer to + its task struct so we can mess with it */ + idle = copy_process(CLONE_VM | CLONE_IDLETASK, 0, ®s, 0, + NULL, NULL); + if (IS_ERR(idle)) + panic("failed fork for CPU %d", cpu); + + /* + * We remove it from the pidhash and the runqueue + * once we got the process: + */ + init_idle(idle, cpu); + + unhash_process(idle); + + do { + /* Iterate until we find a CPU that comes up */ + cur_cpu++; + retval = prom_boot_secondary(cur_cpu, + (unsigned long)idle + KERNEL_STACK_SIZE - 32, + (unsigned long)idle); + } while (!retval && (cur_cpu < NR_CPUS)); + if (retval) { + cpu++; + } else { + panic("CPU discovery disaster"); + } + } + + /* Wait for everyone to come up */ + while (atomic_read(&cpus_booted) != num_online_cpus()); + smp_threads_ready = 1; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/sb1250/time.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * These are routines to set up and handle interrupts from the + * sb1250 general purpose timer 0. We're using the timer as a + * system clock, so we set it up to run at 100 Hz. On every + * interrupt, we update our idea of what the time of day is, + * then call do_timer() in the architecture-independent kernel + * code to do general bookkeeping (e.g. update jiffies, run + * bottom halves, etc.) + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +#define IMR_IP2_VAL K_INT_MAP_I0 +#define IMR_IP3_VAL K_INT_MAP_I1 +#define IMR_IP4_VAL K_INT_MAP_I2 + +extern int sb1250_steal_irq(int irq); + +void sb1250_time_init(void) +{ + int cpu = smp_processor_id(); + int irq = K_INT_TIMER_0+cpu; + + /* Only have 4 general purpose timers */ + if (cpu > 3) { + BUG(); + } + + if (!cpu) { + /* Use our own gettimeoffset() routine */ + do_gettimeoffset = sb1250_gettimeoffset; + } + + sb1250_mask_irq(cpu, irq); + + /* Map the timer interrupt to ip[4] of this cpu */ + out64(IMR_IP4_VAL, KSEG1 + A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + + (irq<<3)); + + /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */ + /* Disable the timer and set up the count */ + out64(0, KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); + out64( +#ifndef CONFIG_SIMULATION + 1000000/HZ +#else + 50000/HZ +#endif + , KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); + + /* Set the timer running */ + out64(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, + KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); + + sb1250_unmask_irq(cpu, irq); + sb1250_steal_irq(irq); + /* + * This interrupt is "special" in that it doesn't use the request_irq + * way to hook the irq line. The timer interrupt is initialized early + * enough to make this a major pain, and it's also firing enough to + * warrant a bit of special case code. sb1250_timer_interrupt is + * called directly from irq_handler.S when IP[4] is set during an + * interrupt + */ +} + +void sb1250_timer_interrupt(struct pt_regs *regs) +{ + int cpu = smp_processor_id(); + int irq = K_INT_TIMER_0 + cpu; + + kstat_cpu(cpu).irqs[irq]++; + /* Reset the timer */ + out64(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, + KSEG1 + A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); + + /* + * CPU 0 handles the global timer interrupt job + */ + if (cpu == 0) { + ll_timer_interrupt(irq, regs); + } + + /* + * every CPU should do profiling and process accouting + */ + ll_local_timer_interrupt(irq, regs); +} + +/* + * We use our own do_gettimeoffset() instead of the generic one, + * because the generic one does not work for SMP case. + * In addition, since we use general timer 0 for system time, + * we can get accurate intra-jiffy offset without calibration. + */ +unsigned long sb1250_gettimeoffset(void) +{ + unsigned long count = + in64(KSEG1 + A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)); + + return 1000000/HZ - count; + } --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/swarm/cmdline.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +#include + +/* + * The naming of this variable is a remnant of the initial mips port to + * ARC-firmware based SGI consoles. We don't really need to do anything for + * the variable other than provide an instantiation. Everything about + * arcs_cmdline seems more than a little bit hackish... + */ +char arcs_cmdline[CL_SIZE]; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/swarm/dbg_io.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,78 @@ +/* + * kgdb debug routines for swarm board. + * + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +/* -------------------- BEGINNING OF CONFIG --------------------- */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * We use the second serial port for kgdb traffic. + * 115200, 8, N, 1. + */ + +#define BAUD_RATE 115200 +#define CLK_DIVISOR V_DUART_BAUD_RATE(BAUD_RATE) +#define DATA_BITS V_DUART_BITS_PER_CHAR_8 /* or 7 */ +#define PARITY V_DUART_PARITY_MODE_NONE /* or even */ +#define STOP_BITS M_DUART_STOP_BIT_LEN_1 /* or 2 */ + +static int duart_initialized = 0; /* 0: need to be init'ed by kgdb */ + +/* -------------------- END OF CONFIG --------------------- */ + + +#define duart_out(reg, val) out64(val, KSEG1 + A_DUART_CHANREG(1,reg)) +#define duart_in(reg) in64(KSEG1 + A_DUART_CHANREG(1,reg)) + +extern void set_async_breakpoint(unsigned int epc); + +void putDebugChar(unsigned char c); +unsigned char getDebugChar(void); +static void +duart_init(int clk_divisor, int data, int parity, int stop) +{ + duart_out(R_DUART_MODE_REG_1, data | parity); + duart_out(R_DUART_MODE_REG_2, stop); + duart_out(R_DUART_CLK_SEL, clk_divisor); + + duart_out(R_DUART_CMD, M_DUART_RX_EN | M_DUART_TX_EN); /* enable rx and tx */ +} + +void +putDebugChar(unsigned char c) +{ + if (!duart_initialized) { + duart_initialized = 1; + duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS); + } + while ((duart_in(R_DUART_STATUS) & M_DUART_TX_RDY) == 0); + duart_out(R_DUART_TX_HOLD, c); +} + +unsigned char +getDebugChar(void) +{ + if (!duart_initialized) { + duart_initialized = 1; + duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS); + } + while ((duart_in(R_DUART_STATUS) & M_DUART_RX_RDY) == 0) ; + return duart_in(R_DUART_RX_HOLD); +} + --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/swarm/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,3 @@ +lib-y = setup.o cmdline.o rtc_xicor1241.o rtc_m41t81.o + +lib-$(CONFIG_KGDB) += dbg_io.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/swarm/rtc.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * Not really sure what is supposed to be here, yet + */ + +#include +#include + +static unsigned char swarm_rtc_read_data(unsigned long addr) +{ + return 0; +} + +static void swarm_rtc_write_data(unsigned char data, unsigned long addr) +{ +} + +static int swarm_rtc_bcd_mode(void) +{ + return 0; +} + +struct rtc_ops swarm_rtc_ops = { + &swarm_rtc_read_data, + &swarm_rtc_write_data, + &swarm_rtc_bcd_mode +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/swarm/rtc_m41t81.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,222 @@ +/* + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * Copyright (C) 2002 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + + +/* M41T81 definitions */ + +/* + * Register bits + */ + +#define M41T81REG_SC_ST 0x80 /* stop bit */ +#define M41T81REG_HR_CB 0x40 /* century bit */ +#define M41T81REG_HR_CEB 0x80 /* century enable bit */ +#define M41T81REG_CTL_S 0x20 /* sign bit */ +#define M41T81REG_CTL_FT 0x40 /* frequency test bit */ +#define M41T81REG_CTL_OUT 0x80 /* output level */ +#define M41T81REG_WD_RB0 0x01 /* watchdog resolution bit 0 */ +#define M41T81REG_WD_RB1 0x02 /* watchdog resolution bit 1 */ +#define M41T81REG_WD_BMB0 0x04 /* watchdog multiplier bit 0 */ +#define M41T81REG_WD_BMB1 0x08 /* watchdog multiplier bit 1 */ +#define M41T81REG_WD_BMB2 0x10 /* watchdog multiplier bit 2 */ +#define M41T81REG_WD_BMB3 0x20 /* watchdog multiplier bit 3 */ +#define M41T81REG_WD_BMB4 0x40 /* watchdog multiplier bit 4 */ +#define M41T81REG_AMO_ABE 0x20 /* alarm in "battery back-up mode" enable bit */ +#define M41T81REG_AMO_SQWE 0x40 /* square wave enable */ +#define M41T81REG_AMO_AFE 0x80 /* alarm flag enable flag */ +#define M41T81REG_ADT_RPT5 0x40 /* alarm repeat mode bit 5 */ +#define M41T81REG_ADT_RPT4 0x80 /* alarm repeat mode bit 4 */ +#define M41T81REG_AHR_RPT3 0x80 /* alarm repeat mode bit 3 */ +#define M41T81REG_AHR_HT 0x40 /* halt update bit */ +#define M41T81REG_AMN_RPT2 0x80 /* alarm repeat mode bit 2 */ +#define M41T81REG_ASC_RPT1 0x80 /* alarm repeat mode bit 1 */ +#define M41T81REG_FLG_AF 0x40 /* alarm flag (read only) */ +#define M41T81REG_FLG_WDF 0x80 /* watchdog flag (read only) */ +#define M41T81REG_SQW_RS0 0x10 /* sqw frequency bit 0 */ +#define M41T81REG_SQW_RS1 0x20 /* sqw frequency bit 1 */ +#define M41T81REG_SQW_RS2 0x40 /* sqw frequency bit 2 */ +#define M41T81REG_SQW_RS3 0x80 /* sqw frequency bit 3 */ + + +/* + * Register numbers + */ + +#define M41T81REG_TSC 0x00 /* tenths/hundredths of second */ +#define M41T81REG_SC 0x01 /* seconds */ +#define M41T81REG_MN 0x02 /* minute */ +#define M41T81REG_HR 0x03 /* hour/century */ +#define M41T81REG_DY 0x04 /* day of week */ +#define M41T81REG_DT 0x05 /* date of month */ +#define M41T81REG_MO 0x06 /* month */ +#define M41T81REG_YR 0x07 /* year */ +#define M41T81REG_CTL 0x08 /* control */ +#define M41T81REG_WD 0x09 /* watchdog */ +#define M41T81REG_AMO 0x0A /* alarm: month */ +#define M41T81REG_ADT 0x0B /* alarm: date */ +#define M41T81REG_AHR 0x0C /* alarm: hour */ +#define M41T81REG_AMN 0x0D /* alarm: minute */ +#define M41T81REG_ASC 0x0E /* alarm: second */ +#define M41T81REG_FLG 0x0F /* flags */ +#define M41T81REG_SQW 0x13 /* square wave register */ + +#define M41T81_CCR_ADDRESS 0x68 +#define SMB_CSR(reg) (KSEG1 | A_SMB_REGISTER(1, reg)) + +static int m41t81_read(uint8_t addr) +{ + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + out64(addr & 0xff, SMB_CSR(R_SMB_CMD)); + out64((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE), SMB_CSR(R_SMB_START)); + + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + out64((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), SMB_CSR(R_SMB_START)); + + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + if (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + /* Clear error bit by writing a 1 */ + out64(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + return -1; + } + + return (in64(SMB_CSR(R_SMB_DATA)) & 0xff); +} + +static int m41t81_write(uint8_t addr, int b) +{ + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + out64((addr & 0xFF), SMB_CSR(R_SMB_CMD)); + out64((b & 0xff), SMB_CSR(R_SMB_DATA)); + out64(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, + SMB_CSR(R_SMB_START)); + + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + if (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + /* Clear error bit by writing a 1 */ + out64(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + return -1; + } + + /* read the same byte again to make sure it is written */ + out64(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, + SMB_CSR(R_SMB_START)); + + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + return 0; +} + +int m41t81_set_time(unsigned long t) +{ + struct rtc_time tm; + + to_tm(t, &tm); + + /* + * Note the write order matters as it ensures the correctness. + * When we write sec, 10th sec is clear. It is reasonable to + * believe we should finish writing min within a second. + */ + + tm.tm_sec = BIN2BCD(tm.tm_sec); + m41t81_write(M41T81REG_SC, tm.tm_sec); + + tm.tm_min = BIN2BCD(tm.tm_min); + m41t81_write(M41T81REG_MN, tm.tm_min); + + tm.tm_hour = BIN2BCD(tm.tm_hour); + tm.tm_hour = (tm.tm_hour & 0x3f) | (m41t81_read(M41T81REG_HR) & 0xc0); + m41t81_write(M41T81REG_HR, tm.tm_hour); + + /* tm_wday starts from 0 to 6 */ + if (tm.tm_wday == 0) tm.tm_wday = 7; + tm.tm_wday = BIN2BCD(tm.tm_wday); + m41t81_write(M41T81REG_DY, tm.tm_wday); + + tm.tm_mday = BIN2BCD(tm.tm_mday); + m41t81_write(M41T81REG_DT, tm.tm_mday); + + /* tm_mon starts from 0, *ick* */ + tm.tm_mon ++; + tm.tm_mon = BIN2BCD(tm.tm_mon); + m41t81_write(M41T81REG_MO, tm.tm_mon); + + /* we don't do century, everything is beyond 2000 */ + tm.tm_year %= 100; + tm.tm_year = BIN2BCD(tm.tm_year); + m41t81_write(M41T81REG_YR, tm.tm_year); + + return 0; +} + +unsigned long m41t81_get_time(void) +{ + unsigned int year, mon, day, hour, min, sec; + + /* + * min is valid if two reads of sec are the same. + */ + for (;;) { + sec = m41t81_read(M41T81REG_SC); + min = m41t81_read(M41T81REG_MN); + if (sec == m41t81_read(M41T81REG_SC)) break; + } + hour = m41t81_read(M41T81REG_HR) & 0x3f; + day = m41t81_read(M41T81REG_DT); + mon = m41t81_read(M41T81REG_MO); + year = m41t81_read(M41T81REG_YR); + + sec = BCD2BIN(sec); + min = BCD2BIN(min); + hour = BCD2BIN(hour); + day = BCD2BIN(day); + mon = BCD2BIN(mon); + year = BCD2BIN(year); + + year += 2000; + + return mktime(year, mon, day, hour, min, sec); +} + +int m41t81_probe(void) +{ + unsigned int tmp; + + /* enable chip if it is not enabled yet */ + tmp = m41t81_read(M41T81REG_SC); + m41t81_write(M41T81REG_SC, tmp & 0x7f); + + return (m41t81_read(M41T81REG_SC) != -1); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/swarm/rtc_xicor1241.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * Copyright (C) 2002 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + + +/* Xicor 1241 definitions */ + +/* + * Register bits + */ + +#define X1241REG_SR_BAT 0x80 /* currently on battery power */ +#define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */ +#define X1241REG_SR_WEL 0x02 /* r/w latch is unlocked, can enable r/w now */ +#define X1241REG_SR_RTCF 0x01 /* clock failed */ +#define X1241REG_BL_BP2 0x80 /* block protect 2 */ +#define X1241REG_BL_BP1 0x40 /* block protect 1 */ +#define X1241REG_BL_BP0 0x20 /* block protect 0 */ +#define X1241REG_BL_WD1 0x10 +#define X1241REG_BL_WD0 0x08 +#define X1241REG_HR_MIL 0x80 /* military time format */ + +/* + * Register numbers + */ + +#define X1241REG_BL 0x10 /* block protect bits */ +#define X1241REG_INT 0x11 /* */ +#define X1241REG_SC 0x30 /* Seconds */ +#define X1241REG_MN 0x31 /* Minutes */ +#define X1241REG_HR 0x32 /* Hours */ +#define X1241REG_DT 0x33 /* Day of month */ +#define X1241REG_MO 0x34 /* Month */ +#define X1241REG_YR 0x35 /* Year */ +#define X1241REG_DW 0x36 /* Day of Week */ +#define X1241REG_Y2K 0x37 /* Year 2K */ +#define X1241REG_SR 0x3F /* Status register */ + +#define X1241_CCR_ADDRESS 0x6F + +#define SMB_CSR(reg) (KSEG1 | A_SMB_REGISTER(1, reg)) + +static int xicor_read(uint8_t addr) +{ + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + out64((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); + out64((addr & 0xff), SMB_CSR(R_SMB_DATA)); + out64((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), SMB_CSR(R_SMB_START)); + + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + out64((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), SMB_CSR(R_SMB_START)); + + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + if (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + /* Clear error bit by writing a 1 */ + out64(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + return -1; + } + + return (in64(SMB_CSR(R_SMB_DATA)) & 0xff); +} + +static int xicor_write(uint8_t addr, int b) +{ + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + out64(addr, SMB_CSR(R_SMB_CMD)); + out64((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); + out64(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, + SMB_CSR(R_SMB_START)); + + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + if (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + /* Clear error bit by writing a 1 */ + out64(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + return -1; + } else { + return 0; + } +} + +int xicor_set_time(unsigned long t) +{ + struct rtc_time tm; + int tmp; + + to_tm(t, &tm); + + /* unlock writes to the CCR */ + xicor_write(X1241REG_SR, X1241REG_SR_WEL); + xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL); + + /* trivial ones */ + tm.tm_sec = BIN2BCD(tm.tm_sec); + xicor_write(X1241REG_SC, tm.tm_sec); + + tm.tm_min = BIN2BCD(tm.tm_min); + xicor_write(X1241REG_MN, tm.tm_min); + + tm.tm_mday = BIN2BCD(tm.tm_mday); + xicor_write(X1241REG_DT, tm.tm_mday); + + /* tm_mon starts from 0, *ick* */ + tm.tm_mon ++; + tm.tm_mon = BIN2BCD(tm.tm_mon); + xicor_write(X1241REG_MO, tm.tm_mon); + + /* year is split */ + tmp = tm.tm_year / 100; + tm.tm_year %= 100; + xicor_write(X1241REG_YR, tm.tm_year); + xicor_write(X1241REG_Y2K, tmp); + + /* hour is the most tricky one */ + tmp = xicor_read(X1241REG_HR); + if (tmp & X1241REG_HR_MIL) { + /* 24 hour format */ + tm.tm_hour = BIN2BCD(tm.tm_hour); + tmp = (tmp & ~0x3f) | (tm.tm_hour & 0x3f); + } else { + /* 12 hour format, with 0x2 for pm */ + tmp = tmp & ~0x3f; + if (tm.tm_hour >= 12) { + tmp |= 0x20; + tm.tm_hour -= 12; + } + tm.tm_hour = BIN2BCD(tm.tm_hour); + tmp |= tm.tm_hour; + } + xicor_write(X1241REG_HR, tmp); + + xicor_write(X1241REG_SR, 0); + + return 0; +} + +unsigned long xicor_get_time(void) +{ + unsigned int year, mon, day, hour, min, sec, y2k; + + sec = xicor_read(X1241REG_SC); + min = xicor_read(X1241REG_MN); + hour = xicor_read(X1241REG_HR); + + if (hour & X1241REG_HR_MIL) { + hour &= 0x3f; + } else { + if (hour & 0x20) + hour = (hour & 0xf) + 0x12; + } + + day = xicor_read(X1241REG_DT); + mon = xicor_read(X1241REG_MO); + year = xicor_read(X1241REG_YR); + y2k = xicor_read(X1241REG_Y2K); + + sec = BCD2BIN(sec); + min = BCD2BIN(min); + hour = BCD2BIN(hour); + day = BCD2BIN(day); + mon = BCD2BIN(mon); + year = BCD2BIN(year); + y2k = BCD2BIN(y2k); + + year += (y2k * 100); + + return mktime(year, mon, day, hour, min, sec); +} + +int xicor_probe(void) +{ + return (xicor_read(X1241REG_SC) != -1); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/swarm/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * Setup code for the SWARM board + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern struct rtc_ops *rtc_ops; +extern struct rtc_ops swarm_rtc_ops; + +#ifdef CONFIG_BLK_DEV_IDE +extern struct ide_ops sibyte_ide_ops; +#endif + +extern void sb1250_setup(void); + +extern int xicor_probe(void); +extern int xicor_set_time(unsigned long); +extern unsigned long xicor_get_time(void); + +extern int m41t81_probe(void); +extern int m41t81_set_time(unsigned long); +extern unsigned long m41t81_get_time(void); + +const char *get_system_type(void) +{ + return "SiByte " SIBYTE_BOARD_NAME; +} + +void __init swarm_timer_setup(struct irqaction *irq) +{ + /* + * we don't set up irqaction, because we will deliver timer + * interrupts through low-level (direct) meachanism. + */ + + /* We only need to setup the generic timer */ + sb1250_time_init(); +} + +int swarm_be_handler(struct pt_regs *regs, int is_fixup) +{ + if (!is_fixup && (regs->cp0_cause & 4)) { + /* Data bus error - print PA */ +#ifdef CONFIG_MIPS64 + printk("DBE physical address: %010lx\n", + __read_64bit_c0_register($26, 1)); +#else + printk("DBE physical address: %010llx\n", + __read_64bit_c0_split($26, 1)); +#endif + } + return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); +} + +void __init swarm_setup(void) +{ + extern int panic_timeout; + + sb1250_setup(); + + panic_timeout = 5; /* For debug. */ + + board_timer_setup = swarm_timer_setup; + board_be_handler = swarm_be_handler; + + if (xicor_probe()) { + printk("swarm setup: Xicor 1241 RTC detected.\n"); + rtc_get_time = xicor_get_time; + rtc_set_time = xicor_set_time; + } + + if (m41t81_probe()) { + printk("swarm setup: M41T81 RTC detected.\n"); + rtc_get_time = m41t81_get_time; + rtc_set_time = m41t81_set_time; + } + + printk("This kernel optimized for " +#ifdef CONFIG_SIMULATION + "simulation" +#else + "board" +#endif + " runs " +#ifdef CONFIG_SIBYTE_CFE + "with" +#else + "without" +#endif + " CFE\n"); + +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &sibyte_ide_ops; +#endif + +#ifdef CONFIG_VT +#ifdef CONFIG_DUMMY_CONSOLE + conswitchp = &dummy_con; +#endif + screen_info = (struct screen_info) { + 0, 0, /* orig-x, orig-y */ + 0, /* unused */ + 52, /* orig_video_page */ + 3, /* orig_video_mode */ + 80, /* orig_video_cols */ + 4626, 3, 9, /* unused, ega_bx, unused */ + 25, /* orig_video_lines */ + 0x22, /* orig_video_isVGA */ + 16 /* orig_video_points */ + }; + /* XXXKW for CFE, get lines/cols from environment */ +#endif +} + +#ifdef LEDS_PHYS + +#ifdef CONFIG_SIBYTE_CARMEL +/* XXXKW need to detect Monterey/LittleSur/etc */ +#undef LEDS_PHYS +#define LEDS_PHYS MLEDS_PHYS +#endif + +#define setled(index, c) \ + ((unsigned char *)(LEDS_PHYS|IO_SPACE_BASE|0x20))[(3-(index))<<3] = (c) +void setleds(char *str) +{ + int i; + for (i = 0; i < 4; i++) { + if (!str[i]) { + setled(i, ' '); + } else { + setled(i, str[i]); + } + } +} +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/sibyte/swarm/time.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,242 @@ +/* + * Copyright (C) 2000, 2001 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +/* + * Time routines for the swarm board. We pass all the hard stuff + * through to the sb1250 handling code. Only thing we really keep + * track of here is what time of day we think it is. And we don't + * really even do a good job of that... + */ + + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static unsigned long long sec_bias = 0; +static unsigned int usec_bias = 0; + +/* Xicor 1241 definitions */ + +/* + * Register bits + */ + +#define X1241REG_SR_BAT 0x80 /* currently on battery power */ +#define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */ +#define X1241REG_SR_WEL 0x02 /* r/w latch is unlocked, can enable r/w now */ +#define X1241REG_SR_RTCF 0x01 /* clock failed */ +#define X1241REG_BL_BP2 0x80 /* block protect 2 */ +#define X1241REG_BL_BP1 0x40 /* block protect 1 */ +#define X1241REG_BL_BP0 0x20 /* block protect 0 */ +#define X1241REG_BL_WD1 0x10 +#define X1241REG_BL_WD0 0x08 +#define X1241REG_HR_MIL 0x80 /* military time format */ + +/* + * Register numbers + */ + +#define X1241REG_BL 0x10 /* block protect bits */ +#define X1241REG_INT 0x11 /* */ +#define X1241REG_SC 0x30 /* Seconds */ +#define X1241REG_MN 0x31 /* Minutes */ +#define X1241REG_HR 0x32 /* Hours */ +#define X1241REG_DT 0x33 /* Day of month */ +#define X1241REG_MO 0x34 /* Month */ +#define X1241REG_YR 0x35 /* Year */ +#define X1241REG_DW 0x36 /* Day of Week */ +#define X1241REG_Y2K 0x37 /* Year 2K */ +#define X1241REG_SR 0x3F /* Status register */ + +#define X1241_CCR_ADDRESS 0x6F + +#define SMB_CSR(reg) (KSEG1 | A_SMB_REGISTER(1, reg)) + +static int xicor_read(uint8_t addr) +{ + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + out64((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); + out64((addr & 0xff), SMB_CSR(R_SMB_DATA)); + out64((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), SMB_CSR(R_SMB_START)); + + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + out64((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), SMB_CSR(R_SMB_START)); + + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + if (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + /* Clear error bit by writing a 1 */ + out64(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + return -1; + } + + return (in64(SMB_CSR(R_SMB_DATA)) & 0xff); +} + +static int xicor_write(uint8_t addr, int b) +{ + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + out64(addr, SMB_CSR(R_SMB_CMD)); + out64((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); + out64(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, + SMB_CSR(R_SMB_START)); + + while (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) + ; + + if (in64(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { + /* Clear error bit by writing a 1 */ + out64(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); + return -1; + } else { + return 0; + } +} + +/* + * In order to set the CMOS clock precisely, set_rtc_mmss has to be + * called 500 ms after the second nowtime has started, because when + * nowtime is written into the registers of the CMOS clock, it will + * jump to the next second precisely 500 ms later. Check the Motorola + * MC146818A or Dallas DS12887 data sheet for details. + * + * BUG: This routine does not handle hour overflow properly; it just + * sets the minutes. Usually you'll only notice that after reboot! + */ +int set_rtc_mmss(unsigned long nowtime) +{ + int retval = 0; + int real_seconds, real_minutes, cmos_minutes; + + cmos_minutes = xicor_read(X1241REG_MN); + cmos_minutes = BCD2BIN(cmos_minutes); + + /* + * since we're only adjusting minutes and seconds, + * don't interfere with hour overflow. This avoids + * messing with unknown time zones but requires your + * RTC not to be off by more than 15 minutes + */ + real_seconds = nowtime % 60; + real_minutes = nowtime / 60; + if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) + real_minutes += 30; /* correct for half hour time zone */ + real_minutes %= 60; + + /* unlock writes to the CCR */ + xicor_write(X1241REG_SR, X1241REG_SR_WEL); + xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL); + + if (abs(real_minutes - cmos_minutes) < 30) { + real_seconds = BIN2BCD(real_seconds); + real_minutes = BIN2BCD(real_minutes); + xicor_write(X1241REG_SC, real_seconds); + xicor_write(X1241REG_MN, real_minutes); + } else { + printk(KERN_WARNING + "set_rtc_mmss: can't update from %d to %d\n", + cmos_minutes, real_minutes); + retval = -1; + } + + xicor_write(X1241REG_SR, 0); + + printk("set_rtc_mmss: %02d:%02d\n", real_minutes, real_seconds); + + return retval; +} + +static unsigned long __init get_swarm_time(void) +{ + unsigned int year, mon, day, hour, min, sec, y2k; + + sec = xicor_read(X1241REG_SC); + min = xicor_read(X1241REG_MN); + hour = xicor_read(X1241REG_HR); + + if (hour & X1241REG_HR_MIL) { + hour &= 0x3f; + } else { + if (hour & 0x20) + hour = (hour & 0xf) + 0x12; + } + + sec = BCD2BIN(sec); + min = BCD2BIN(min); + hour = BCD2BIN(hour); + + day = xicor_read(X1241REG_DT); + mon = xicor_read(X1241REG_MO); + year = xicor_read(X1241REG_YR); + y2k = xicor_read(X1241REG_Y2K); + + day = BCD2BIN(day); + mon = BCD2BIN(mon); + year = BCD2BIN(year); + y2k = BCD2BIN(y2k); + + year += (y2k * 100); + + return mktime(year, mon, day, hour, min, sec); +} + +/* + * Bring up the timer at 100 Hz. + */ +void __init swarm_time_init(void) +{ + unsigned int flags; + int status; + + /* Set up the scd general purpose timer 0 to cpu 0 */ + sb1250_time_init(); + + /* Establish communication with the Xicor 1241 RTC */ + /* XXXKW how do I share the SMBus with the I2C subsystem? */ + + out64(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); + out64(0, SMB_CSR(R_SMB_CONTROL)); + + if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) { + printk("x1241: couldn't detect on SWARM SMBus 1\n"); + } else { + if (status & X1241REG_SR_RTCF) + printk("x1241: battery failed -- time is probably wrong\n"); + write_seqlock_irqsave(&xtime_lock, flags); + xtime.tv_sec = get_swarm_time(); + xtime.tv_nsec = 0; + write_sequnlock_irqrestore(&xtime_lock, flags); + } +} --- linux-2.5.73/arch/mips/tools/Makefile 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,23 +0,0 @@ -# Makefile for MIPS kernel build tools. -# -# Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) -# Copyright (C) 1997 Ralf Baechle (ralf@gnu.ai.mit.edu) -# -# $Id: Makefile,v 1.2 1997/09/23 06:23:49 ralf Exp $ -# -TARGET := $(TOPDIR)/include/asm-$(ARCH)/offset.h - -$(TARGET): offset.h - cmp -s $^ $@ || (cp $^ $(TARGET).new && mv $(TARGET).new $(TARGET)) - -offset.h: offset.s - sed -n '/^@@@/s///p' $^ >$@ - -offset.s: offset.c $(TOPDIR)/include/linux/autoconf.h - -clean: - rm -f offset.[hs] $(TARGET).new - -mrproper: - rm -f offset.[hs] $(TARGET).new - rm -f $(TARGET) --- linux-2.5.73/arch/mips/tools/offset.c 2003-06-26 22:07:24.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,157 +0,0 @@ -/* - * offset.c: Calculate pt_regs and task_struct offsets. - * - * Copyright (C) 1996 David S. Miller - * Copyright (C) 1997, 1998, 1999 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - * - * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. - */ -#include -#include - -#include -#include - -#define text(t) __asm__("\n@@@" t) -#define _offset(type, member) (&(((type *)NULL)->member)) - -#define offset(string, ptr, member) \ - __asm__("\n@@@" string "%0" : : "i" (_offset(ptr, member))) -#define size(string, size) \ - __asm__("\n@@@" string "%0" : : "i" (sizeof(size))) -#define linefeed text("") - -text("/* DO NOT TOUCH, AUTOGENERATED BY OFFSET.C */"); -linefeed; -text("#ifndef _MIPS_OFFSET_H"); -text("#define _MIPS_OFFSET_H"); -linefeed; - -void output_ptreg_defines(void) -{ - text("/* MIPS pt_regs offsets. */"); - offset("#define PT_R0 ", struct pt_regs, regs[0]); - offset("#define PT_R1 ", struct pt_regs, regs[1]); - offset("#define PT_R2 ", struct pt_regs, regs[2]); - offset("#define PT_R3 ", struct pt_regs, regs[3]); - offset("#define PT_R4 ", struct pt_regs, regs[4]); - offset("#define PT_R5 ", struct pt_regs, regs[5]); - offset("#define PT_R6 ", struct pt_regs, regs[6]); - offset("#define PT_R7 ", struct pt_regs, regs[7]); - offset("#define PT_R8 ", struct pt_regs, regs[8]); - offset("#define PT_R9 ", struct pt_regs, regs[9]); - offset("#define PT_R10 ", struct pt_regs, regs[10]); - offset("#define PT_R11 ", struct pt_regs, regs[11]); - offset("#define PT_R12 ", struct pt_regs, regs[12]); - offset("#define PT_R13 ", struct pt_regs, regs[13]); - offset("#define PT_R14 ", struct pt_regs, regs[14]); - offset("#define PT_R15 ", struct pt_regs, regs[15]); - offset("#define PT_R16 ", struct pt_regs, regs[16]); - offset("#define PT_R17 ", struct pt_regs, regs[17]); - offset("#define PT_R18 ", struct pt_regs, regs[18]); - offset("#define PT_R19 ", struct pt_regs, regs[19]); - offset("#define PT_R20 ", struct pt_regs, regs[20]); - offset("#define PT_R21 ", struct pt_regs, regs[21]); - offset("#define PT_R22 ", struct pt_regs, regs[22]); - offset("#define PT_R23 ", struct pt_regs, regs[23]); - offset("#define PT_R24 ", struct pt_regs, regs[24]); - offset("#define PT_R25 ", struct pt_regs, regs[25]); - offset("#define PT_R26 ", struct pt_regs, regs[26]); - offset("#define PT_R27 ", struct pt_regs, regs[27]); - offset("#define PT_R28 ", struct pt_regs, regs[28]); - offset("#define PT_R29 ", struct pt_regs, regs[29]); - offset("#define PT_R30 ", struct pt_regs, regs[30]); - offset("#define PT_R31 ", struct pt_regs, regs[31]); - offset("#define PT_LO ", struct pt_regs, lo); - offset("#define PT_HI ", struct pt_regs, hi); - offset("#define PT_EPC ", struct pt_regs, cp0_epc); - offset("#define PT_BVADDR ", struct pt_regs, cp0_badvaddr); - offset("#define PT_STATUS ", struct pt_regs, cp0_status); - offset("#define PT_CAUSE ", struct pt_regs, cp0_cause); - size("#define PT_SIZE ", struct pt_regs); - linefeed; -} - -void output_task_defines(void) -{ - text("/* MIPS task_struct offsets. */"); - offset("#define TASK_STATE ", struct task_struct, state); - offset("#define TASK_FLAGS ", struct task_struct, flags); -#error offset("#define TASK_SIGPENDING ", struct task_struct, work.sigpending); -#error offset("#define TASK_NEED_RESCHED ", struct task_struct, work.need_resched); -#error offset("#define TASK_PTRACE ", struct task_struct, ptrace); - offset("#define TASK_COUNTER ", struct task_struct, counter); - offset("#define TASK_NICE ", struct task_struct, nice); - offset("#define TASK_MM ", struct task_struct, mm); - offset("#define TASK_PID ", struct task_struct, pid); - size("#define TASK_STRUCT_SIZE ", struct task_struct); - linefeed; -} - -void output_thread_defines(void) -{ - text("/* MIPS specific thread_struct offsets. */"); - offset("#define THREAD_REG16 ", struct task_struct, thread.reg16); - offset("#define THREAD_REG17 ", struct task_struct, thread.reg17); - offset("#define THREAD_REG18 ", struct task_struct, thread.reg18); - offset("#define THREAD_REG19 ", struct task_struct, thread.reg19); - offset("#define THREAD_REG20 ", struct task_struct, thread.reg20); - offset("#define THREAD_REG21 ", struct task_struct, thread.reg21); - offset("#define THREAD_REG22 ", struct task_struct, thread.reg22); - offset("#define THREAD_REG23 ", struct task_struct, thread.reg23); - offset("#define THREAD_REG29 ", struct task_struct, thread.reg29); - offset("#define THREAD_REG30 ", struct task_struct, thread.reg30); - offset("#define THREAD_REG31 ", struct task_struct, thread.reg31); - offset("#define THREAD_STATUS ", struct task_struct, \ - thread.cp0_status); - offset("#define THREAD_FPU ", struct task_struct, thread.fpu); - offset("#define THREAD_BVADDR ", struct task_struct, \ - thread.cp0_badvaddr); - offset("#define THREAD_BUADDR ", struct task_struct, \ - thread.cp0_baduaddr); - offset("#define THREAD_ECODE ", struct task_struct, \ - thread.error_code); - offset("#define THREAD_TRAPNO ", struct task_struct, thread.trap_no); - offset("#define THREAD_MFLAGS ", struct task_struct, thread.mflags); - offset("#define THREAD_CURDS ", struct task_struct, \ - thread.current_ds); - offset("#define THREAD_TRAMP ", struct task_struct, \ - thread.irix_trampoline); - offset("#define THREAD_OLDCTX ", struct task_struct, \ - thread.irix_oldctx); - offset("#define THREAD_DSEEPC ", struct task_struct, \ - thread.dsemul_epc); - offset("#define THREAD_DSEAERPC ", struct task_struct, \ - thread.dsemul_aerpc); - linefeed; -} - -void output_mm_defines(void) -{ - text("/* Linux mm_struct offsets. */"); - offset("#define MM_USERS ", struct mm_struct, mm_users); - offset("#define MM_PGD ", struct mm_struct, pgd); - offset("#define MM_CONTEXT ", struct mm_struct, context); - linefeed; -} - -void output_sc_defines(void) -{ - text("/* Linux sigcontext offsets. */"); - offset("#define SC_REGS ", struct sigcontext, sc_regs); - offset("#define SC_FPREGS ", struct sigcontext, sc_fpregs); - offset("#define SC_MDHI ", struct sigcontext, sc_mdhi); - offset("#define SC_MDLO ", struct sigcontext, sc_mdlo); - offset("#define SC_PC ", struct sigcontext, sc_pc); - offset("#define SC_STATUS ", struct sigcontext, sc_status); - offset("#define SC_OWNEDFP ", struct sigcontext, sc_ownedfp); - offset("#define SC_FPC_CSR ", struct sigcontext, sc_fpc_csr); - offset("#define SC_FPC_EIR ", struct sigcontext, sc_fpc_eir); - offset("#define SC_CAUSE ", struct sigcontext, sc_cause); - offset("#define SC_BADVADDR ", struct sigcontext, sc_badvaddr); - linefeed; -} - -text("#endif /* !(_MIPS_OFFSET_H) */"); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/tx4927/common/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,14 @@ +# +# Makefile for common code for Toshiba TX4927 based systems +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +obj-y := tx4927_prom.o +obj-y += tx4927_setup.o +obj-y += tx4927_irq.o +obj-y += tx4927_irq_handler.o + +obj-$(CONFIG_KGDB) += tx4927_dbgio.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/tx4927/common/tx4927_dbgio.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,47 @@ +/* + * linux/arch/mips/tx4927/common/tx4927_dbgio.c + * + * kgdb interface for gdb + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +u8 getDebugChar(void) +{ + extern u8 txx9_sio_kdbg_rd(void); + return (txx9_sio_kdbg_rd()); +} + + +int putDebugChar(u8 byte) +{ + extern int txx9_sio_kdbg_wr( u8 ch ); + return (txx9_sio_kdbg_wr(byte)); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/tx4927/common/tx4927_irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,705 @@ +/* + * Common tx4927 irq handler + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * DEBUG + */ +#define TX4927_IRQ_CHECK_CP0 +#define TX4927_IRQ_CHECK_PIC + +#undef TX4927_IRQ_DEBUG + +#ifdef TX4927_IRQ_DEBUG +#define TX4927_IRQ_NONE 0x00000000 + +#define TX4927_IRQ_INFO ( 1 << 0 ) +#define TX4927_IRQ_WARN ( 1 << 1 ) +#define TX4927_IRQ_EROR ( 1 << 2 ) + +#define TX4927_IRQ_INIT ( 1 << 5 ) +#define TX4927_IRQ_NEST1 ( 1 << 6 ) +#define TX4927_IRQ_NEST2 ( 1 << 7 ) +#define TX4927_IRQ_NEST3 ( 1 << 8 ) +#define TX4927_IRQ_NEST4 ( 1 << 9 ) + +#define TX4927_IRQ_CP0_INIT ( 1 << 10 ) +#define TX4927_IRQ_CP0_STARTUP ( 1 << 11 ) +#define TX4927_IRQ_CP0_SHUTDOWN ( 1 << 12 ) +#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 ) +#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 ) +#define TX4927_IRQ_CP0_MASK ( 1 << 15 ) +#define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 ) + +#define TX4927_IRQ_PIC_INIT ( 1 << 20 ) +#define TX4927_IRQ_PIC_STARTUP ( 1 << 21 ) +#define TX4927_IRQ_PIC_SHUTDOWN ( 1 << 22 ) +#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 ) +#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 ) +#define TX4927_IRQ_PIC_MASK ( 1 << 25 ) +#define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 ) + +#define TX4927_IRQ_ALL 0xffffffff +#endif + +#ifdef TX4927_IRQ_DEBUG +static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE + | TX4927_IRQ_INFO + | TX4927_IRQ_WARN | TX4927_IRQ_EROR +// | TX4927_IRQ_CP0_INIT +// | TX4927_IRQ_CP0_STARTUP +// | TX4927_IRQ_CP0_SHUTDOWN +// | TX4927_IRQ_CP0_ENABLE +// | TX4927_IRQ_CP0_DISABLE +// | TX4927_IRQ_CP0_MASK +// | TX4927_IRQ_CP0_ENDIRQ +// | TX4927_IRQ_PIC_INIT +// | TX4927_IRQ_PIC_STARTUP +// | TX4927_IRQ_PIC_SHUTDOWN +// | TX4927_IRQ_PIC_ENABLE +// | TX4927_IRQ_PIC_DISABLE +// | TX4927_IRQ_PIC_MASK +// | TX4927_IRQ_PIC_ENDIRQ +// | TX4927_IRQ_INIT +// | TX4927_IRQ_NEST1 +// | TX4927_IRQ_NEST2 +// | TX4927_IRQ_NEST3 +// | TX4927_IRQ_NEST4 + ); +#endif + +#ifdef TX4927_IRQ_DEBUG +#define TX4927_IRQ_DPRINTK(flag,str...) \ + if ( (tx4927_irq_debug_flag) & (flag) ) \ + { \ + char tmp[100]; \ + sprintf( tmp, str ); \ + printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \ + } +#else +#define TX4927_IRQ_DPRINTK(flag,str...) +#endif + +/* + * Forwad definitions for all pic's + */ + +static unsigned int tx4927_irq_cp0_startup(unsigned int irq); +static void tx4927_irq_cp0_shutdown(unsigned int irq); +static void tx4927_irq_cp0_enable(unsigned int irq); +static void tx4927_irq_cp0_disable(unsigned int irq); +static void tx4927_irq_cp0_mask_and_ack(unsigned int irq); +static void tx4927_irq_cp0_end(unsigned int irq); + +static unsigned int tx4927_irq_pic_startup(unsigned int irq); +static void tx4927_irq_pic_shutdown(unsigned int irq); +static void tx4927_irq_pic_enable(unsigned int irq); +static void tx4927_irq_pic_disable(unsigned int irq); +static void tx4927_irq_pic_mask_and_ack(unsigned int irq); +static void tx4927_irq_pic_end(unsigned int irq); + +/* + * Kernel structs for all pic's + */ + +static spinlock_t tx4927_cp0_lock = SPIN_LOCK_UNLOCKED; +static spinlock_t tx4927_pic_lock = SPIN_LOCK_UNLOCKED; + +#define TX4927_CP0_NAME "TX4927-CP0" +static struct hw_interrupt_type tx4927_irq_cp0_type = { + typename: TX4927_CP0_NAME, + startup: tx4927_irq_cp0_startup, + shutdown: tx4927_irq_cp0_shutdown, + enable: tx4927_irq_cp0_enable, + disable: tx4927_irq_cp0_disable, + ack: tx4927_irq_cp0_mask_and_ack, + end: tx4927_irq_cp0_end, + set_affinity: NULL +}; + +#define TX4927_PIC_NAME "TX4927-PIC" +static struct hw_interrupt_type tx4927_irq_pic_type = { + typename: TX4927_PIC_NAME, + startup: tx4927_irq_pic_startup, + shutdown: tx4927_irq_pic_shutdown, + enable: tx4927_irq_pic_enable, + disable: tx4927_irq_pic_disable, + ack: tx4927_irq_pic_mask_and_ack, + end: tx4927_irq_pic_end, + set_affinity: NULL +}; + +#define TX4927_PIC_ACTION(s) { no_action, 0, 0, s, NULL, NULL } +static struct irqaction tx4927_irq_pic_action = +TX4927_PIC_ACTION(TX4927_PIC_NAME); + +#define CCP0_STATUS 12 +#define CCP0_CAUSE 13 + +/* + * Functions for cp0 + */ + +#define tx4927_irq_cp0_mask(irq) ( 1 << ( irq-TX4927_IRQ_CP0_BEG+8 ) ) + +static void +tx4927_irq_cp0_modify(unsigned cp0_reg, unsigned clr_bits, unsigned set_bits) +{ + unsigned long val = 0; + + switch (cp0_reg) { + case CCP0_STATUS: + val = read_c0_status(); + break; + + case CCP0_CAUSE: + val = read_c0_cause(); + break; + + } + + val &= (~clr_bits); + val |= (set_bits); + + switch (cp0_reg) { + case CCP0_STATUS:{ + write_c0_status(val); + break; + } + case CCP0_CAUSE:{ + write_c0_cause(val); + break; + } + } + + return; +} + +static void __init tx4927_irq_cp0_init(void) +{ + int i; + + TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_INIT, "beg=%d end=%d\n", + TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END); + + for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 1; + irq_desc[i].handler = &tx4927_irq_cp0_type; + } + + return; +} + +static unsigned int tx4927_irq_cp0_startup(unsigned int irq) +{ + TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_STARTUP, "irq=%d \n", irq); + +#ifdef TX4927_IRQ_CHECK_CP0 + { + if (irq < TX4927_IRQ_CP0_BEG || irq > TX4927_IRQ_CP0_END) { + TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR, + "bad irq=%d \n", irq); + panic("\n"); + } + } +#endif + + tx4927_irq_cp0_enable(irq); + + return (0); +} + +static void tx4927_irq_cp0_shutdown(unsigned int irq) +{ + TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_SHUTDOWN, "irq=%d \n", irq); + +#ifdef TX4927_IRQ_CHECK_CP0 + { + if (irq < TX4927_IRQ_CP0_BEG || irq > TX4927_IRQ_CP0_END) { + TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR, + "bad irq=%d \n", irq); + panic("\n"); + } + } +#endif + + tx4927_irq_cp0_disable(irq); + + return; +} + +static void tx4927_irq_cp0_enable(unsigned int irq) +{ + unsigned long flags; + + TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENABLE, "irq=%d \n", irq); + +#ifdef TX4927_IRQ_CHECK_CP0 + { + if (irq < TX4927_IRQ_CP0_BEG || irq > TX4927_IRQ_CP0_END) { + TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR, + "bad irq=%d \n", irq); + panic("\n"); + } + } +#endif + + spin_lock_irqsave(&tx4927_cp0_lock, flags); + + tx4927_irq_cp0_modify(CCP0_STATUS, 0, tx4927_irq_cp0_mask(irq)); + + spin_unlock_irqrestore(&tx4927_cp0_lock, flags); + + return; +} + +static void tx4927_irq_cp0_disable(unsigned int irq) +{ + unsigned long flags; + + TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_DISABLE, "irq=%d \n", irq); + +#ifdef TX4927_IRQ_CHECK_CP0 + { + if (irq < TX4927_IRQ_CP0_BEG || irq > TX4927_IRQ_CP0_END) { + TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR, + "bad irq=%d \n", irq); + panic("\n"); + } + } +#endif + + spin_lock_irqsave(&tx4927_cp0_lock, flags); + + tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0); + + spin_unlock_irqrestore(&tx4927_cp0_lock, flags); + + return; +} + +static void tx4927_irq_cp0_mask_and_ack(unsigned int irq) +{ + TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_MASK, "irq=%d \n", irq); + +#ifdef TX4927_IRQ_CHECK_CP0 + { + if (irq < TX4927_IRQ_CP0_BEG || irq > TX4927_IRQ_CP0_END) { + TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR, + "bad irq=%d \n", irq); + panic("\n"); + } + } +#endif + + tx4927_irq_cp0_disable(irq); + + return; +} + +static void tx4927_irq_cp0_end(unsigned int irq) +{ + TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENDIRQ, "irq=%d \n", irq); + +#ifdef TX4927_IRQ_CHECK_CP0 + { + if (irq < TX4927_IRQ_CP0_BEG || irq > TX4927_IRQ_CP0_END) { + TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR, + "bad irq=%d \n", irq); + panic("\n"); + } + } +#endif + + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + tx4927_irq_cp0_enable(irq); + } + + return; +} + +/* + * Functions for pic + */ +u32 tx4927_irq_pic_addr(int irq) +{ + /* MVMCP -- need to formulize this */ + irq -= TX4927_IRQ_PIC_BEG; + switch (irq) { + case 17: + case 16: + case 1: + case 0: + return (0xff1ff610); + + case 19: + case 18: + case 3: + case 2: + return (0xff1ff614); + + case 21: + case 20: + case 5: + case 4: + return (0xff1ff618); + + case 23: + case 22: + case 7: + case 6: + return (0xff1ff61c); + + case 25: + case 24: + case 9: + case 8: + return (0xff1ff620); + + case 27: + case 26: + case 11: + case 10: + return (0xff1ff624); + + case 29: + case 28: + case 13: + case 12: + return (0xff1ff628); + + case 31: + case 30: + case 15: + case 14: + return (0xff1ff62c); + + } + return (0); +} + +u32 tx4927_irq_pic_mask(int irq) +{ + /* MVMCP -- need to formulize this */ + irq -= TX4927_IRQ_PIC_BEG; + switch (irq) { + case 31: + case 29: + case 27: + case 25: + case 23: + case 21: + case 19: + case 17:{ + return (0x07000000); + } + case 30: + case 28: + case 26: + case 24: + case 22: + case 20: + case 18: + case 16:{ + return (0x00070000); + } + case 15: + case 13: + case 11: + case 9: + case 7: + case 5: + case 3: + case 1:{ + return (0x00000700); + } + case 14: + case 12: + case 10: + case 8: + case 6: + case 4: + case 2: + case 0:{ + return (0x00000007); + } + } + return (0x00000000); +} + +static void tx4927_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, + unsigned set_bits) +{ + unsigned long val = 0; + + val = TX4927_RD(pic_reg); + val &= (~clr_bits); + val |= (set_bits); + TX4927_WR(pic_reg, val); + + return; +} + +static void __init tx4927_irq_pic_init(void) +{ + unsigned long flags; + int i; + + TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n", + TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END); + + for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 2; + irq_desc[i].handler = &tx4927_irq_pic_type; + } + + setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action); + + spin_lock_irqsave(&tx4927_pic_lock, flags); + + TX4927_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ + TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1); /* irq enable */ + + spin_unlock_irqrestore(&tx4927_pic_lock, flags); + + return; +} + +static unsigned int tx4927_irq_pic_startup(unsigned int irq) +{ + TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_STARTUP, "irq=%d\n", irq); + +#ifdef TX4927_IRQ_CHECK_PIC + { + if (irq < TX4927_IRQ_PIC_BEG || irq > TX4927_IRQ_PIC_END) { + TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR, + "bad irq=%d \n", irq); + panic("\n"); + } + } +#endif + + tx4927_irq_pic_enable(irq); + + return (0); +} + +static void tx4927_irq_pic_shutdown(unsigned int irq) +{ + TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_SHUTDOWN, "irq=%d\n", irq); + +#ifdef TX4927_IRQ_CHECK_PIC + { + if (irq < TX4927_IRQ_PIC_BEG || irq > TX4927_IRQ_PIC_END) { + TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR, + "bad irq=%d \n", irq); + panic("\n"); + } + } +#endif + + tx4927_irq_pic_disable(irq); + + return; +} + +static void tx4927_irq_pic_enable(unsigned int irq) +{ + unsigned long flags; + + TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENABLE, "irq=%d\n", irq); + +#ifdef TX4927_IRQ_CHECK_PIC + { + if (irq < TX4927_IRQ_PIC_BEG || irq > TX4927_IRQ_PIC_END) { + TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR, + "bad irq=%d \n", irq); + panic("\n"); + } + } +#endif + + spin_lock_irqsave(&tx4927_pic_lock, flags); + + tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 0, + tx4927_irq_pic_mask(irq)); + + spin_unlock_irqrestore(&tx4927_pic_lock, flags); + + return; +} + +static void tx4927_irq_pic_disable(unsigned int irq) +{ + unsigned long flags; + + TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_DISABLE, "irq=%d\n", irq); + +#ifdef TX4927_IRQ_CHECK_PIC + { + if (irq < TX4927_IRQ_PIC_BEG || irq > TX4927_IRQ_PIC_END) { + TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR, + "bad irq=%d \n", irq); + panic("\n"); + } + } +#endif + + spin_lock_irqsave(&tx4927_pic_lock, flags); + + tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), + tx4927_irq_pic_mask(irq), 0); + + spin_unlock_irqrestore(&tx4927_pic_lock, flags); + + return; +} + +static void tx4927_irq_pic_mask_and_ack(unsigned int irq) +{ + TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_MASK, "irq=%d\n", irq); + +#ifdef TX4927_IRQ_CHECK_PIC + { + if (irq < TX4927_IRQ_PIC_BEG || irq > TX4927_IRQ_PIC_END) { + TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR, + "bad irq=%d \n", irq); + panic("\n"); + } + } +#endif + + tx4927_irq_pic_disable(irq); + + return; +} + +static void tx4927_irq_pic_end(unsigned int irq) +{ + TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENDIRQ, "irq=%d\n", irq); + +#ifdef TX4927_IRQ_CHECK_PIC + { + if (irq < TX4927_IRQ_PIC_BEG || irq > TX4927_IRQ_PIC_END) { + TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR, + "bad irq=%d \n", irq); + panic("\n"); + } + } +#endif + + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + tx4927_irq_pic_enable(irq); + } + + return; +} + +/* + * Main init functions + */ +void __init tx4927_irq_init(void) +{ + extern asmlinkage void tx4927_irq_handler(void); + + TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "-\n"); + + TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "=Calling tx4927_irq_cp0_init()\n"); + tx4927_irq_cp0_init(); + + TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "=Calling tx4927_irq_pic_init()\n"); + tx4927_irq_pic_init(); + + TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, + "=Calling set_except_vector(tx4927_irq_handler)\n"); + set_except_vector(0, tx4927_irq_handler); + + TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "+\n"); + + return; +} + +int tx4927_irq_nested(void) +{ + int sw_irq = 0; + u32 level2; + + TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST1, "-\n"); + + level2 = TX4927_RD(0xff1ff6a0); + TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST2, "=level2a=0x%x\n", level2); + + if ((level2 & 0x10000) == 0) { + level2 &= 0x1f; + TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST3, "=level2b=0x%x\n", level2); + + sw_irq = TX4927_IRQ_PIC_BEG + level2; + TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST3, "=sw_irq=%d\n", sw_irq); + + if (sw_irq == 27) { + TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST4, "=irq-%d\n", + sw_irq); + +#ifdef CONFIG_TOSHIBA_RBTX4927 + { + sw_irq = toshiba_rbtx4927_irq_nested(sw_irq); + } +#endif + + TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST4, "=irq+%d\n", + sw_irq); + } + } + + TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST2, "=sw_irq=%d\n", sw_irq); + + TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST1, "+\n"); + + return (sw_irq); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/tx4927/common/tx4927_irq_handler.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,104 @@ +/* + * linux/arch/mips/tx4927/common/tx4927_irq_handler.S + * + * Primary interrupt handler for tx4927 based systems + * + * Author: MontaVista Software, Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include + + .align 5 + NESTED(tx4927_irq_handler, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + + mfc0 t0, CP0_CAUSE + mfc0 t1, CP0_STATUS + and t0, t1 + + andi t1, t0, STATUSF_IP7 /* cpu timer */ + bnez t1, ll_ip7 + + /* IP6..IP3 multiplexed -- do not use */ + + andi t1, t0, STATUSF_IP2 /* tx4927 pic */ + bnez t1, ll_ip2 + + andi t1, t0, STATUSF_IP0 /* user line 0 */ + bnez t1, ll_ip0 + + andi t1, t0, STATUSF_IP1 /* user line 1 */ + bnez t1, ll_ip1 + + .set reorder + + /* wrong alarm or masked ... */ + j spurious_interrupt + nop + END(tx4927_irq_handler) + + .align 5 + + +ll_ip7: + li a0, TX4927_IRQ_CPU_TIMER + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_ip2: + jal tx4927_irq_nested + nop + beqz v0, goto_spurious_interrupt + nop + move a0, v0 + move a1, sp + jal do_IRQ + j ret_from_irq + +goto_spurious_interrupt: + j spurious_interrupt + nop + +ll_ip1: + li a0, TX4927_IRQ_USER1 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_ip0: + li a0, TX4927_IRQ_USER0 + move a1, sp + jal do_IRQ + j ret_from_irq --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/tx4927/common/tx4927_prom.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,146 @@ +/* + * linux/arch/mips/tx4927/common/tx4927_prom.c + * + * common tx4927 memory interface + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +#include +#include +#include + +static unsigned int __init tx4927_process_sdccr(u64 * addr) +{ + u64 val; + unsigned int sdccr_ce; + unsigned int sdccr_bs; + unsigned int sdccr_rs; + unsigned int sdccr_cs; + unsigned int sdccr_mw; + unsigned int bs = 0; + unsigned int rs = 0; + unsigned int cs = 0; + unsigned int mw = 0; + unsigned int msize = 0; + + val = (*((vu64 *) (addr))); + + /* MVMCP -- need #defs for these bits masks */ + sdccr_ce = ((val & (1 << 10)) >> 10); + sdccr_bs = ((val & (1 << 8)) >> 8); + sdccr_rs = ((val & (3 << 5)) >> 5); + sdccr_cs = ((val & (3 << 2)) >> 2); + sdccr_mw = ((val & (1 << 0)) >> 0); + + if (sdccr_ce) { + switch (sdccr_bs) { + case 0:{ + bs = 2; + break; + } + case 1:{ + bs = 4; + break; + } + } + switch (sdccr_rs) { + case 0:{ + rs = 2048; + break; + } + case 1:{ + rs = 4096; + break; + } + case 2:{ + rs = 8192; + break; + } + case 3:{ + rs = 0; + break; + } + } + switch (sdccr_cs) { + case 0:{ + cs = 256; + break; + } + case 1:{ + cs = 512; + break; + } + case 2:{ + cs = 1024; + break; + } + case 3:{ + cs = 2048; + break; + } + } + switch (sdccr_mw) { + case 0:{ + mw = 8; + break; + } /* 8 bytes = 64 bits */ + case 1:{ + mw = 4; + break; + } /* 4 bytes = 32 bits */ + } + } + + /* bytes per chip MB per chip num chips */ + msize = (((rs * cs * mw) / (1024 * 1024)) * bs); + + return (msize); +} + + +unsigned int __init tx4927_get_mem_size(void) +{ + unsigned int c0; + unsigned int c1; + unsigned int c2; + unsigned int c3; + unsigned int total; + + /* MVMCP -- need #defs for these registers */ + c0 = tx4927_process_sdccr((u64 *) 0xff1f8000); + c1 = tx4927_process_sdccr((u64 *) 0xff1f8008); + c2 = tx4927_process_sdccr((u64 *) 0xff1f8010); + c3 = tx4927_process_sdccr((u64 *) 0xff1f8018); + total = c0 + c1 + c2 + c3; + + return (total); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/tx4927/common/tx4927_setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,251 @@ +/* + * linux/arch/mips/tx4927/common/tx4927_setup.c + * + * common tx4927 setup stuff + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#undef DEBUG + +void __init tx4927_setup(void); +void __init tx4927_time_init(void); +void __init tx4927_timer_setup(struct irqaction *irq); +void dump_cp0(char *key); + + +void (*__wbflush) (void); + +static void tx4927_write_buffer_flush(void) +{ + __asm__ __volatile__ + ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t"); +} + + +void __init tx4927_setup(void) +{ + board_time_init = tx4927_time_init; + board_timer_setup = tx4927_timer_setup; + __wbflush = tx4927_write_buffer_flush; + +#ifdef CONFIG_TOSHIBA_RBTX4927 + { + extern void toshiba_rbtx4927_setup(void); + toshiba_rbtx4927_setup(); + } +#endif + + return; +} + + +void __init tx4927_time_init(void) +{ + +#ifdef CONFIG_TOSHIBA_RBTX4927 + { + extern void toshiba_rbtx4927_time_init(void); + toshiba_rbtx4927_time_init(); + } +#endif + +#ifdef CONFIG_KGDB + { + printk("Calling breakpoint() -- start remote kgdb\n"); + set_debug_traps(); + breakpoint(); + printk("Calling breakpoint() -- done\n"); + } +#endif + + return; +} + + +void __init tx4927_timer_setup(struct irqaction *irq) +{ + u32 count; + u32 c1; + u32 c2; + + setup_irq(TX4927_IRQ_CPU_TIMER, irq); + + /* to generate the first timer interrupt */ + c1 = read_c0_count(); + count = c1 + (mips_counter_frequency / HZ); + write_c0_compare(count); + c2 = read_c0_count(); + +#ifdef CONFIG_TOSHIBA_RBTX4927 + { + extern void toshiba_rbtx4927_timer_setup(struct irqaction + *irq); + toshiba_rbtx4927_timer_setup(irq); + } +#endif + + return; +} + + +#ifdef DEBUG +void print_cp0(char *key, int num, char *name, u32 val) +{ + printk("%s cp0:%02d:%s=0x%08x\n", key, num, name, val); + return; +} + +indent: Standard input:25: Error:Unexpected end of file + +void +dump_cp0(char *key) +{ + if (key == NULL) + key = ""; + + print_cp0(key, 0, "INDEX ", read_c0_index()); + print_cp0(key, 2, "ENTRYLO1", read_c0_entrylo0()); + print_cp0(key, 3, "ENTRYLO2", read_c0_entrylo1()); + print_cp0(key, 4, "CONTEXT ", read_c0_context()); + print_cp0(key, 5, "PAGEMASK", read_c0_pagemask()); + print_cp0(key, 6, "WIRED ", read_c0_wired()); + //print_cp0(key, 8, "BADVADDR", read_c0_badvaddr()); + print_cp0(key, 9, "COUNT ", read_c0_count()); + print_cp0(key, 10, "ENTRYHI ", read_c0_entryhi()); + print_cp0(key, 11, "COMPARE ", read_c0_compare()); + print_cp0(key, 12, "STATUS ", read_c0_status()); + print_cp0(key, 13, "CAUSE ", read_c0_cause() & 0xffff87ff); + print_cp0(key, 16, "CONFIG ", read_c0_config()); + return; +} + +void print_pic(char *key, u32 reg, char *name) +{ + printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name, + TX4927_RD(reg)); + return; +} + + +void dump_pic(char *key) +{ + if (key == NULL) + key = ""; + + print_pic(key, 0xff1ff600, "IRDEN "); + print_pic(key, 0xff1ff604, "IRDM0 "); + print_pic(key, 0xff1ff608, "IRDM1 "); + + print_pic(key, 0xff1ff610, "IRLVL0 "); + print_pic(key, 0xff1ff614, "IRLVL1 "); + print_pic(key, 0xff1ff618, "IRLVL2 "); + print_pic(key, 0xff1ff61c, "IRLVL3 "); + print_pic(key, 0xff1ff620, "IRLVL4 "); + print_pic(key, 0xff1ff624, "IRLVL5 "); + print_pic(key, 0xff1ff628, "IRLVL6 "); + print_pic(key, 0xff1ff62c, "IRLVL7 "); + + print_pic(key, 0xff1ff640, "IRMSK "); + print_pic(key, 0xff1ff660, "IREDC "); + print_pic(key, 0xff1ff680, "IRPND "); + print_pic(key, 0xff1ff6a0, "IRCS "); + + print_pic(key, 0xff1ff514, "IRFLAG1 "); /* don't read IRLAG0 -- it hangs system */ + + print_pic(key, 0xff1ff518, "IRPOL "); + print_pic(key, 0xff1ff51c, "IRRCNT "); + print_pic(key, 0xff1ff520, "IRMASKINT"); + print_pic(key, 0xff1ff524, "IRMASKEXT"); + + return; +} + + +void print_addr(char *hdr, char *key, u32 addr) +{ + printk("%s %s:0x%08x=0x%08x\n", hdr, key, addr, TX4927_RD(addr)); + return; +} + + +void dump_180(char *key) +{ + u32 i; + + for (i = 0x80000180; i < 0x80000180 + 0x80; i += 4) { + print_addr("180", key, i); + } + return; +} + + +void dump_eh0(char *key) +{ + int i; + extern unsigned long exception_handlers[]; + + for (i = (int) exception_handlers; + i < (int) (exception_handlers + 20); i += 4) { + print_addr("eh0", key, i); + } + + return; +} + +void pk0(void) +{ + volatile u32 val; + + __asm__ __volatile__("ori %0, $26, 0":"=r"(val) + ); + printk("k0=[0x%08x]\n", val); +} +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/tx4927/toshiba_rbtx4927/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,8 @@ +obj-y += toshiba_rbtx4927_prom.o +obj-y += toshiba_rbtx4927_setup.o +obj-y += toshiba_rbtx4927_irq.o + +obj-$(CONFIG_PCI) += toshiba_rbtx4927_pci_fixup.o +obj-$(CONFIG_PCI) += toshiba_rbtx4927_pci_ops.o + +EXTRA_AFLAGS := $(CFLAGS) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,795 @@ +/* + * linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c + * + * Toshiba RBTX4927 specific interrupt handlers + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + +/* +IRQ Device +00 RBTX4927-ISA/00 +01 RBTX4927-ISA/01 PS2/Keyboard +02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) +03 RBTX4927-ISA/03 +04 RBTX4927-ISA/04 +05 RBTX4927-ISA/05 +06 RBTX4927-ISA/06 +07 RBTX4927-ISA/07 +08 RBTX4927-ISA/08 +09 RBTX4927-ISA/09 +10 RBTX4927-ISA/10 +11 RBTX4927-ISA/11 +12 RBTX4927-ISA/12 PS2/Mouse (not supported at this time) +13 RBTX4927-ISA/13 +14 RBTX4927-ISA/14 IDE +15 RBTX4927-ISA/15 + +16 TX4927-CP0/00 Software 0 +17 TX4927-CP0/01 Software 1 +18 TX4927-CP0/02 Cascade TX4927-CP0 +19 TX4927-CP0/03 Multiplexed -- do not use +20 TX4927-CP0/04 Multiplexed -- do not use +21 TX4927-CP0/05 Multiplexed -- do not use +22 TX4927-CP0/06 Multiplexed -- do not use +23 TX4927-CP0/07 CPU TIMER + +24 TX4927-PIC/00 +25 TX4927-PIC/01 +26 TX4927-PIC/02 +27 TX4927-PIC/03 Cascade RBTX4927-IOC +28 TX4927-PIC/04 +29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet +30 TX4927-PIC/06 +31 TX4927-PIC/07 +32 TX4927-PIC/08 TX4927 SerialIO Channel 0 +33 TX4927-PIC/09 TX4927 SerialIO Channel 1 +34 TX4927-PIC/10 +35 TX4927-PIC/11 +36 TX4927-PIC/12 +37 TX4927-PIC/13 +38 TX4927-PIC/14 +39 TX4927-PIC/15 +40 TX4927-PIC/16 TX4927 PCI PCI-C +41 TX4927-PIC/17 +42 TX4927-PIC/18 +43 TX4927-PIC/19 +44 TX4927-PIC/20 +45 TX4927-PIC/21 +46 TX4927-PIC/22 TX4927 PCI PCI-ERR +47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) +48 TX4927-PIC/24 +49 TX4927-PIC/25 +50 TX4927-PIC/26 +51 TX4927-PIC/27 +52 TX4927-PIC/28 +53 TX4927-PIC/29 +54 TX4927-PIC/30 +55 TX4927-PIC/31 + +56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4] +57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5] +58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported] +59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6] +60 RBTX4927-IOC/04 +61 RBTX4927-IOC/05 +62 RBTX4927-IOC/06 +63 RBTX4927-IOC/07 + +NOTES: +SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 +SouthBridge/ISA/pin=0 no pci irq used by this device +SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 +SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59 +SouthBridge/PMC/pin=0 no pci irq used by this device +SuperIO/PS2/Keyboard, using INTR via ISA IRQ1 +SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported) +JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6 +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_RTC_DS1742 +#include +#endif +#ifdef CONFIG_TOSHIBA_FPCIB0 +#include +#endif +#include + + +#undef TOSHIBA_RBTX4927_IRQ_DEBUG + +#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG +#define TOSHIBA_RBTX4927_IRQ_NONE 0x00000000 + +#define TOSHIBA_RBTX4927_IRQ_INFO ( 1 << 0 ) +#define TOSHIBA_RBTX4927_IRQ_WARN ( 1 << 1 ) +#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 ) + +#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 ) +#define TOSHIBA_RBTX4927_IRQ_IOC_STARTUP ( 1 << 11 ) +#define TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN ( 1 << 12 ) +#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 ) +#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 ) +#define TOSHIBA_RBTX4927_IRQ_IOC_MASK ( 1 << 15 ) +#define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 ) + +#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 ) +#define TOSHIBA_RBTX4927_IRQ_ISA_STARTUP ( 1 << 21 ) +#define TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN ( 1 << 22 ) +#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 ) +#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 ) +#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 ) +#define TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ ( 1 << 26 ) + +#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff +#endif + + +#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG +static const u32 toshiba_rbtx4927_irq_debug_flag = + (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO | + TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR +// | TOSHIBA_RBTX4927_IRQ_IOC_INIT +// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP +// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN +// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE +// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE +// | TOSHIBA_RBTX4927_IRQ_IOC_MASK +// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ +// | TOSHIBA_RBTX4927_IRQ_ISA_INIT +// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP +// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN +// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE +// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE +// | TOSHIBA_RBTX4927_IRQ_ISA_MASK +// | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ + ); +#endif + + +#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG +#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \ + if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \ + { \ + char tmp[100]; \ + sprintf( tmp, str ); \ + printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \ + } +#else +#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) +#endif + + + + +#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 +#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7 + +#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */ +#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */ + + +#define TOSHIBA_RBTX4927_IRQ_ISA_BEG MI8259_IRQ_ISA_BEG +#define TOSHIBA_RBTX4927_IRQ_ISA_END MI8259_IRQ_ISA_END +#define TOSHIBA_RBTX4927_IRQ_ISA_MID ((TOSHIBA_RBTX4927_IRQ_ISA_BEG+TOSHIBA_RBTX4927_IRQ_ISA_END+1)/2) + + +#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC +#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) +#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA (TOSHIBA_RBTX4927_IRQ_ISA_BEG+2) + +extern int tx4927_using_backplane; + +#ifdef CONFIG_TOSHIBA_FPCIB0 +extern void enable_8259A_irq(unsigned int irq); +extern void disable_8259A_irq(unsigned int irq); +extern void mask_and_ack_8259A(unsigned int irq); +#endif + +static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq); +static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq); +static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); +static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); +static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq); +static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq); + +#ifdef CONFIG_TOSHIBA_FPCIB0 +static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq); +static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq); +static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq); +static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq); +static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq); +static void toshiba_rbtx4927_irq_isa_end(unsigned int irq); +#endif + +static spinlock_t toshiba_rbtx4927_ioc_lock = SPIN_LOCK_UNLOCKED; + + +#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" +static struct hw_interrupt_type toshiba_rbtx4927_irq_ioc_type = { + typename:TOSHIBA_RBTX4927_IOC_NAME, + startup:toshiba_rbtx4927_irq_ioc_startup, + shutdown:toshiba_rbtx4927_irq_ioc_shutdown, + enable:toshiba_rbtx4927_irq_ioc_enable, + disable:toshiba_rbtx4927_irq_ioc_disable, + ack:toshiba_rbtx4927_irq_ioc_mask_and_ack, + end:toshiba_rbtx4927_irq_ioc_end, + set_affinity:NULL +}; +#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000 +#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 + + +#ifdef CONFIG_TOSHIBA_FPCIB0 +#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA" +static struct hw_interrupt_type toshiba_rbtx4927_irq_isa_type = { + typename:TOSHIBA_RBTX4927_ISA_NAME, + startup:toshiba_rbtx4927_irq_isa_startup, + shutdown:toshiba_rbtx4927_irq_isa_shutdown, + enable:toshiba_rbtx4927_irq_isa_enable, + disable:toshiba_rbtx4927_irq_isa_disable, + ack:toshiba_rbtx4927_irq_isa_mask_and_ack, + end:toshiba_rbtx4927_irq_isa_end, + set_affinity:NULL +}; +#endif + + +u32 bit2num(u32 num) +{ + u32 i; + + for (i = 0; i < (sizeof(num) * 8); i++) { + if (num & (1 << i)) { + return (i); + } + } + return (0); +} + +int toshiba_rbtx4927_irq_nested(int sw_irq) +{ + u32 level3; + u32 level4; + u32 level5; + + level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; + if (level3) { + sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3); + if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) { + goto RETURN; + } + } +#ifdef CONFIG_TOSHIBA_FPCIB0 + { + if (tx4927_using_backplane) { + outb(0x0A, 0x20); + level4 = inb(0x20) & 0xff; + if (level4) { + sw_irq = + TOSHIBA_RBTX4927_IRQ_ISA_BEG + + bit2num(level4); + if (sw_irq != + TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA) { + goto RETURN; + } + } + + outb(0x0A, 0xA0); + level5 = inb(0xA0) & 0xff; + if (level5) { + sw_irq = + TOSHIBA_RBTX4927_IRQ_ISA_MID + + bit2num(level5); + goto RETURN; + } + } + } +#endif + + RETURN: + return (sw_irq); +} + +//#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, 0, s, NULL, NULL } +#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, SA_SHIRQ, 0, s, NULL, NULL } +static struct irqaction toshiba_rbtx4927_irq_ioc_action = +TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME); +#ifdef CONFIG_TOSHIBA_FPCIB0 +static struct irqaction toshiba_rbtx4927_irq_isa_master = +TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/M"); +static struct irqaction toshiba_rbtx4927_irq_isa_slave = +TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/S"); +#endif + + +/**********************************************************************************/ +/* Functions for ioc */ +/**********************************************************************************/ + + +static void __init toshiba_rbtx4927_irq_ioc_init(void) +{ + int i; + + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT, + "beg=%d end=%d\n", + TOSHIBA_RBTX4927_IRQ_IOC_BEG, + TOSHIBA_RBTX4927_IRQ_IOC_END); + + for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; + i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = 3; + irq_desc[i].handler = &toshiba_rbtx4927_irq_ioc_type; + } + + setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, + &toshiba_rbtx4927_irq_ioc_action); + + return; +} + +static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq) +{ + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_STARTUP, + "irq=%d\n", irq); + + if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG + || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, + "bad irq=%d\n", irq); + panic("\n"); + } + + toshiba_rbtx4927_irq_ioc_enable(irq); + + return (0); +} + + +static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq) +{ + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN, + "irq=%d\n", irq); + + if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG + || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, + "bad irq=%d\n", irq); + panic("\n"); + } + + toshiba_rbtx4927_irq_ioc_disable(irq); + + return; +} + + +static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) +{ + unsigned long flags; + volatile unsigned char v; + + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE, + "irq=%d\n", irq); + + if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG + || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, + "bad irq=%d\n", irq); + panic("\n"); + } + + spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags); + + v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); + v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); + TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); + + spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags); + + return; +} + + +static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) +{ + unsigned long flags; + volatile unsigned char v; + + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE, + "irq=%d\n", irq); + + if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG + || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, + "bad irq=%d\n", irq); + panic("\n"); + } + + spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags); + + v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); + v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); + TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); + + spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags); + + return; +} + + +static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq) +{ + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_MASK, + "irq=%d\n", irq); + + if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG + || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, + "bad irq=%d\n", irq); + panic("\n"); + } + + toshiba_rbtx4927_irq_ioc_disable(irq); + + return; +} + + +static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq) +{ + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ, + "irq=%d\n", irq); + + if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG + || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) { + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, + "bad irq=%d\n", irq); + panic("\n"); + } + + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + toshiba_rbtx4927_irq_ioc_enable(irq); + } + + return; +} + + +/**********************************************************************************/ +/* Functions for isa */ +/**********************************************************************************/ + + +#ifdef CONFIG_TOSHIBA_FPCIB0 +static void __init toshiba_rbtx4927_irq_isa_init(void) +{ + int i; + + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_INIT, + "beg=%d end=%d\n", + TOSHIBA_RBTX4927_IRQ_ISA_BEG, + TOSHIBA_RBTX4927_IRQ_ISA_END); + + for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG; + i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = 0; + irq_desc[i].depth = + ((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5)); + irq_desc[i].handler = &toshiba_rbtx4927_irq_isa_type; + } + + setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC, + &toshiba_rbtx4927_irq_isa_master); + setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA, + &toshiba_rbtx4927_irq_isa_slave); + + /* make sure we are looking at IRR (not ISR) */ + outb(0x0A, 0x20); + outb(0x0A, 0xA0); + + return; +} +#endif + + +#ifdef CONFIG_TOSHIBA_FPCIB0 +static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq) +{ + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_STARTUP, + "irq=%d\n", irq); + + if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG + || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) { + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, + "bad irq=%d\n", irq); + panic("\n"); + } + + toshiba_rbtx4927_irq_isa_enable(irq); + + return (0); +} +#endif + + +#ifdef CONFIG_TOSHIBA_FPCIB0 +static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq) +{ + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN, + "irq=%d\n", irq); + + if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG + || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) { + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, + "bad irq=%d\n", irq); + panic("\n"); + } + + toshiba_rbtx4927_irq_isa_disable(irq); + + return; +} +#endif + + +#ifdef CONFIG_TOSHIBA_FPCIB0 +static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq) +{ + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENABLE, + "irq=%d\n", irq); + + if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG + || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) { + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, + "bad irq=%d\n", irq); + panic("\n"); + } + + enable_8259A_irq(irq); + + return; +} +#endif + + +#ifdef CONFIG_TOSHIBA_FPCIB0 +static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq) +{ + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_DISABLE, + "irq=%d\n", irq); + + if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG + || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) { + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, + "bad irq=%d\n", irq); + panic("\n"); + } + + disable_8259A_irq(irq); + + return; +} +#endif + + +#ifdef CONFIG_TOSHIBA_FPCIB0 +static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq) +{ + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_MASK, + "irq=%d\n", irq); + + if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG + || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) { + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, + "bad irq=%d\n", irq); + panic("\n"); + } + + mask_and_ack_8259A(irq); + + return; +} +#endif + + +#ifdef CONFIG_TOSHIBA_FPCIB0 +static void toshiba_rbtx4927_irq_isa_end(unsigned int irq) +{ + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ, + "irq=%d\n", irq); + + if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG + || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) { + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR, + "bad irq=%d\n", irq); + panic("\n"); + } + + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + toshiba_rbtx4927_irq_isa_enable(irq); + } + + return; +} +#endif + + +void __init init_IRQ(void) +{ + extern void tx4927_irq_init(void); + + cli(); + + tx4927_irq_init(); + toshiba_rbtx4927_irq_ioc_init(); +#ifdef CONFIG_TOSHIBA_FPCIB0 + { + if (tx4927_using_backplane) { + toshiba_rbtx4927_irq_isa_init(); + } + } +#endif + +#ifdef CONFIG_PCI + { + extern void toshiba_rbtx4927_pci_irq_init(void); + toshiba_rbtx4927_pci_irq_init(); + } +#endif + + wbflush(); + + return; +} + +void toshiba_rbtx4927_irq_dump(char *key) +{ +#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG + { + u32 i, j = 0; + for (i = 0; i < NR_IRQS; i++) { + if (strcmp(irq_desc[i].handler->typename, "none") + == 0) + continue; + + if ((i >= 1) + && (irq_desc[i - 1].handler->typename == + irq_desc[i].handler->typename)) { + j++; + } else { + j = 0; + } + TOSHIBA_RBTX4927_IRQ_DPRINTK + (TOSHIBA_RBTX4927_IRQ_INFO, + "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n", + key, i, i, irq_desc[i].status, + (u32) irq_desc[i].handler, + (u32) irq_desc[i].action, + (u32) (irq_desc[i].action ? irq_desc[i]. + action->handler : 0), + irq_desc[i].depth, + irq_desc[i].handler->typename, j); + } + } +#endif + return; +} + +void toshiba_rbtx4927_irq_dump_pics(char *s) +{ + u32 level0_m; + u32 level0_s; + u32 level1_m; + u32 level1_s; + u32 level2; + u32 level2_p; + u32 level2_s; + u32 level3_m; + u32 level3_s; + u32 level4_m; + u32 level4_s; + u32 level5_m; + u32 level5_s; + + if (s == NULL) + s = "null"; + + level0_m = (read_c0_status() & 0x0000ff00) >> 8; + level0_s = (read_c0_cause() & 0x0000ff00) >> 8; + + level1_m = level0_m; + level1_s = level0_s & 0x87; + + level2 = TX4927_RD(0xff1ff6a0); + level2_p = (((level2 & 0x10000)) ? 0 : 1); + level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f)); + + level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f; + level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; + + level4_m = inb(0x21); + outb(0x0A, 0x20); + level4_s = inb(0x20); + + level5_m = inb(0xa1); + outb(0x0A, 0xa0); + level5_s = inb(0xa0); + + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, + "dump_raw_pic() "); + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, + "cp0:m=0x%02x/s=0x%02x ", level0_m, + level0_s); + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, + "cp0:m=0x%02x/s=0x%02x ", level1_m, + level1_s); + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, + "pic:e=0x%02x/s=0x%02x ", level2_p, + level2_s); + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, + "ioc:m=0x%02x/s=0x%02x ", level3_m, + level3_s); + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, + "sbm:m=0x%02x/s=0x%02x ", level4_m, + level4_s); + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, + "sbs:m=0x%02x/s=0x%02x ", level5_m, + level5_s); + TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n", + s); + + return; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_pci_fixup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,329 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Board specific pci fixups for the Toshiba rbtx4927 + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include + +#include +#include + +#undef DEBUG +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +void __init pcibios_fixup_resources(struct pci_dev *dev) +{ + /* will need to fixup IO resources */ +} + +void __init pcibios_fixup(void) +{ + /* nothing to do here */ +} + +/* look up table for backplane pci irq for slots 17-20 by pin # */ +static unsigned char backplane_pci_irq[4][4] = { + /* PJ6 SLOT: 17, PIN: 1 */ {TX4927_IRQ_IOC_PCIA, + /* PJ6 SLOT: 17, PIN: 2 */ + TX4927_IRQ_IOC_PCIB, + /* PJ6 SLOT: 17, PIN: 3 */ + TX4927_IRQ_IOC_PCIC, + /* PJ6 SLOT: 17, PIN: 4 */ + TX4927_IRQ_IOC_PCID}, + /* SB SLOT: 18, PIN: 1 */ {TX4927_IRQ_IOC_PCIB, + /* SB SLOT: 18, PIN: 2 */ + TX4927_IRQ_IOC_PCIC, + /* SB SLOT: 18, PIN: 3 */ + TX4927_IRQ_IOC_PCID, + /* SB SLOT: 18, PIN: 4 */ + TX4927_IRQ_IOC_PCIA}, + /* PJ5 SLOT: 19, PIN: 1 */ {TX4927_IRQ_IOC_PCIC, + /* PJ5 SLOT: 19, PIN: 2 */ + TX4927_IRQ_IOC_PCID, + /* PJ5 SLOT: 19, PIN: 3 */ + TX4927_IRQ_IOC_PCIA, + /* PJ5 SLOT: 19, PIN: 4 */ + TX4927_IRQ_IOC_PCIB}, + /* PJ4 SLOT: 20, PIN: 1 */ {TX4927_IRQ_IOC_PCID, + /* PJ4 SLOT: 20, PIN: 2 */ + TX4927_IRQ_IOC_PCIA, + /* PJ4 SLOT: 20, PIN: 3 */ + TX4927_IRQ_IOC_PCIB, + /* PJ4 SLOT: 20, PIN: 4 */ + TX4927_IRQ_IOC_PCIC} +}; + +int pci_get_irq(struct pci_dev *dev, int pin) +{ + unsigned char irq = pin; + + DBG("pci_get_irq: pin is %d\n", pin); + /* IRQ rotation */ + irq--; /* 0-3 */ + if (dev->bus->parent == NULL && + PCI_SLOT(dev->devfn) == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) { + printk("Onboard PCI_SLOT(dev->devfn) is %d\n", + PCI_SLOT(dev->devfn)); + /* IDSEL=A23 is tx4927 onboard pci slot */ + irq = (irq + PCI_SLOT(dev->devfn)) % 4; + irq++; /* 1-4 */ + DBG("irq is now %d\n", irq); + + switch (irq) { + case 1: + irq = TX4927_IRQ_IOC_PCIA; + break; + case 2: + irq = TX4927_IRQ_IOC_PCIB; + break; + case 3: + irq = TX4927_IRQ_IOC_PCIC; + break; + case 4: + irq = TX4927_IRQ_IOC_PCID; + break; + } + } else { + /* PCI Backplane */ + DBG("PCI Backplane PCI_SLOT(dev->devfn) is %d\n", + PCI_SLOT(dev->devfn)); + irq = backplane_pci_irq[PCI_SLOT(dev->devfn) - 17][irq]; + } + DBG("assigned irq %d\n", irq); + return irq; +} + + +#ifdef TX4927_SUPPORT_PCI_66 +extern int tx4927_pci66; +extern void tx4927_pci66_setup(void); +#endif +extern void tx4927_pci_setup(void); + +#ifdef TX4927_SUPPORT_PCI_66 +int tx4927_pci66_check(void) +{ + struct pci_dev *dev; + unsigned short stat; + int cap66 = 1; + + if (tx4927_pci66 < 0) + return 0; + + /* check 66MHz capability */ + pci_for_each_dev(dev) { + if (cap66) { + pci_read_config_word(dev, PCI_STATUS, &stat); + if (!(stat & PCI_STATUS_66MHZ)) { + printk(KERN_INFO + "PCI: %02x:%02x not 66MHz capable.\n", + dev->bus->number, dev->devfn); + cap66 = 0; + } + } + } + return cap66; +} +#endif + +#ifdef DEBUG +void do_it(u32 offset, u32 reg) +{ + volatile u32 a1; + volatile u32 a2; + volatile u32 v1; + volatile u32 v2; + + a1 = 0xff1f0000 + offset + reg; + a2 = a1 + 4; + + v1 = *(volatile u32 *) a1; + v2 = *(volatile u32 *) a2; + + if (v1) + printk("TX4927 0x%08x 0x%08x\n", a1, v1); + if (v2) + printk("TX4927 0x%08x 0x%08x\n", a2, v2); +} + +void do_it1(u32 base, u32 r) +{ + do_it(base, r); +} + +void do_it2(u32 base, u32 start, u32 stop) +{ + u32 r; + + for (r = start; r <= stop; r += 8) { + do_it(base, r); + } +} +void dump_config(void) +{ + unsigned long id; + unsigned long j; + struct pci_dev *dev; + + printk("----------------------pci\n"); + pci_for_each_dev(dev) { + for (j = 0; j < 64; j++) { + pci_read_config_dword(dev, j * 4, &id); + if (id == 0) + continue; + printk + ("dev 0x%02x 0x%02x:0x%02x -- 0x%02x-0x%02x 0x%08x\n", + dev->devfn, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn), (j * 4) + 3, (j * 4), + id); + } + printk("dev 0x%02x \n", dev->devfn); + } + printk("----------------------sdram\n"); + do_it2(0x8000, 0x00, 0x18); + do_it1(0x8000, 0x40); + do_it1(0x8000, 0x58); + printk("----------------------ebus\n"); + do_it2(0x9000, 0x00, 0x38); + printk("----------------------ecc\n"); + do_it2(0xa000, 0x00, 0x08); + printk("----------------------dmac\n"); + do_it2(0xb000, 0x00, 0xf8); + /* b1xx */ + printk("----------------------pci\n"); + /* d */ + printk("----------------------cfg\n"); + do_it2(0xe000, 0x00, 0x20); + do_it1(0xe000, 0x30); + do_it1(0xe000, 0x48); + printk("----------------------timers\n"); + do_it2(0xf000, 0x00, 0xf0); + do_it2(0xf100, 0x00, 0xf0); + do_it2(0xf200, 0x00, 0xf0); + printk("----------------------serial\n"); + do_it2(0xf300, 0x00, 0x20); + do_it2(0xf400, 0x00, 0x20); + printk("----------------------parallel\n"); + do_it2(0xf500, 0x00, 0x0c); + printk("----------------------pic\n"); + do_it2(0xf500, 0x10, 0x24); + do_it2(0xf600, 0x00, 0x2c); + do_it1(0xf600, 0x40); + do_it1(0xf600, 0x60); + do_it1(0xf600, 0x80); + do_it1(0xf600, 0xa0); + printk("----------------------aclink\n"); + do_it2(0xf700, 0x00, 0xfc); + printk("----------------------done\n"); +} +#endif + + +void __init pcibios_fixup_irqs(void) +{ + unsigned char pin; + unsigned char irq; + struct pci_dev *dev; + unsigned int id; + +#ifdef TX4927_SUPPORT_PCI_66 + { + if (tx4927_pci66_check()) { + tx4927_pci66_setup(); + tx4927_pci_setup(); /* Reinitialize PCIC */ + } + } +#endif + + pci_for_each_dev(dev) { + DBG("FIXUP:\n"); + DBG(" devfn=0x%02x (0x%02x:0x%02x)\n", + dev->devfn, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn)); + + pci_read_config_dword(dev, PCI_VENDOR_ID, &id); + DBG(" id=0x%08x\n", id); + + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); + DBG(" line=0x%02x/%d\n", irq, irq); + + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); + DBG(" pin=%d\n", pin); + +#ifdef DEBUG + { + unsigned int tmp; + pci_read_config_dword(dev, 0x10, &tmp); + DBG(" bar0:0x10=0x%08x\n", tmp); + pci_read_config_dword(dev, 0x14, &tmp); + DBG(" bar1:0x14=0x%08x\n", tmp); + pci_read_config_dword(dev, 0x1c, &tmp); + DBG(" bar2:0x1c=0x%08x\n", tmp); + pci_read_config_dword(dev, 0x20, &tmp); + DBG(" bar3:0x20=0x%08x\n", tmp); + pci_read_config_dword(dev, 0x24, &tmp); + DBG(" bar4:0x24=0x%08x\n", tmp); + } +#endif + + irq = 0; + + if (id == 0x91301055) { /* ide */ + irq = 14; + } + + if (pin == 0) { + DBG(" auto irq (now=%d) -- skipping pin=0\n", irq); + } else if (irq) { + DBG(" auto irq (now=%d) -- skipping hardcoded irq\n", irq); + } else { + DBG(" auto irq (was=%d)\n", irq); + irq = pci_get_irq(dev, pin); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + irq); + dev->irq = irq; + DBG(" auto irq (now=%d)\n", irq); + } + + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); + printk(KERN_INFO + "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n", + dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn), + PCI_FUNC(dev->devfn), irq); + + } + +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_pci_ops.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,317 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ahennessy@mvista.com + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c + * + * Define the pci_ops for the Toshiba rbtx4927 + * + * Much of the code is derived from the original DDB5074 port by + * Geert Uytterhoeven + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include + +#include +#include +#include +#include + +/* initialize in setup */ +struct resource pci_io_resource = { + "pci IO space", + (PCIBIOS_MIN_IO), + ((PCIBIOS_MIN_IO) + (TX4927_PCIIO_SIZE)) - 1, + IORESOURCE_IO +}; + +/* initialize in setup */ +struct resource pci_mem_resource = { + "pci memory space", + TX4927_PCIMEM, + TX4927_PCIMEM + TX4927_PCIMEM_SIZE - 1, + IORESOURCE_MEM +}; + +extern struct pci_ops tx4927_pci_ops; + +struct pci_channel mips_pci_channels[] = { + /* h/w only supports devices 0x00 to 0x14 */ + {&tx4927_pci_ops, &pci_io_resource, &pci_mem_resource, + PCI_DEVFN(0x00, 0), PCI_DEVFN(0x14, 7)}, + {NULL, NULL, NULL, 0, 0} +}; + +unsigned int pcibios_assign_all_busses(void) +{ + return 1; +} + +static int +mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where, + int *flagsp) +{ + if (bus > 0) { + /* Type 1 configuration */ + tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | + ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1; + } else { + if (dev_fn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0)) + return -1; + + /* Type 0 configuration */ + tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | + ((dev_fn & 0xff) << 0x08) | (where & 0xfc); + } + /* clear M_ABORT and Disable M_ABORT Int. */ + tx4927_pcicptr->pcistatus = + (tx4927_pcicptr->pcistatus & 0x0000ffff) | + (PCI_STATUS_REC_MASTER_ABORT << 16); + tx4927_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT; + return 0; +} + +static int check_abort(int flags) +{ + int code = PCIBIOS_SUCCESSFUL; + if (tx4927_pcicptr-> + pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { + tx4927_pcicptr->pcistatus = + (tx4927_pcicptr-> + pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT + << 16); + tx4927_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; + code = PCIBIOS_DEVICE_NOT_FOUND; + // printk("returning PCIBIOS_DEVICE_NOT_FOUND\n"); + } + return code; +} + +/* + * We can't address 8 and 16 bit words directly. Instead we have to + * read/write a 32bit word and mask/modify the data we actually want. + */ +static int tx4927_pcibios_read_config_byte(struct pci_dev *dev, + int where, unsigned char *val) +{ + int flags, retval; + unsigned char bus, func_num; + + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + func_num = PCI_FUNC(dev->devfn); + if (mkaddr(bus, dev->devfn, where, &flags)) + return -1; +#ifdef __BIG_ENDIAN + *val = + *(volatile u8 *) ((ulong) & tx4927_pcicptr-> + g2pcfgdata | ((where & 3) ^ 3)); +#else + *val = + *(volatile u8 *) ((ulong) & tx4927_pcicptr-> + g2pcfgdata | (where & 3)); +#endif + retval = check_abort(flags); + if (retval == PCIBIOS_DEVICE_NOT_FOUND) + *val = 0xff; +//printk("CFG R1 0x%02x 0x%02x 0x%08x\n", dev->devfn, where, *val ); + return retval; +} + +static int tx4927_pcibios_read_config_word(struct pci_dev *dev, + int where, unsigned short *val) +{ + int flags, retval; + unsigned char bus, func_num; + + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + func_num = PCI_FUNC(dev->devfn); + if (mkaddr(bus, dev->devfn, where, &flags)) + return -1; +#ifdef __BIG_ENDIAN + *val = + *(volatile u16 *) ((ulong) & tx4927_pcicptr-> + g2pcfgdata | ((where & 3) ^ 2)); +#else + *val = + *(volatile u16 *) ((ulong) & tx4927_pcicptr-> + g2pcfgdata | (where & 3)); +#endif + retval = check_abort(flags); + if (retval == PCIBIOS_DEVICE_NOT_FOUND) + *val = 0xffff; +//printk("CFG R2 0x%02x 0x%02x 0x%08x\n", dev->devfn, where, *val ); + return retval; +} + +static int tx4927_pcibios_read_config_dword(struct pci_dev *dev, + int where, unsigned int *val) +{ + int flags, retval; + unsigned char bus, func_num; + + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + + db_assert((where & 3) == 0); + db_assert(where < (1 << 8)); + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + func_num = PCI_FUNC(dev->devfn); + if (mkaddr(bus, dev->devfn, where, &flags)) + return -1; + *val = tx4927_pcicptr->g2pcfgdata; + retval = check_abort(flags); + if (retval == PCIBIOS_DEVICE_NOT_FOUND) + *val = 0xffffffff; + +//printk("CFG R4 0x%02x 0x%02x 0x%08x\n", dev->devfn, where, *val ); + return retval; +} + +static int tx4927_pcibios_write_config_byte(struct pci_dev *dev, + int where, unsigned char val) +{ + int flags; + unsigned char bus, func_num; + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + func_num = PCI_FUNC(dev->devfn); + if (mkaddr(bus, dev->devfn, where, &flags)) + return -1; +#ifdef __BIG_ENDIAN + *(volatile u8 *) ((ulong) & tx4927_pcicptr-> + g2pcfgdata | ((where & 3) ^ 3)) = val; +#else + *(volatile u8 *) ((ulong) & tx4927_pcicptr-> + g2pcfgdata | (where & 3)) = val; +#endif +//printk("CFG W1 0x%02x 0x%02x 0x%08x\n", dev->devfn, where, val ); + return check_abort(flags); +} + +static int tx4927_pcibios_write_config_word(struct pci_dev *dev, + int where, unsigned short val) +{ + int flags; + unsigned char bus, func_num; + + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + func_num = PCI_FUNC(dev->devfn); + if (mkaddr(bus, dev->devfn, where, &flags)) + return -1; +#ifdef __BIG_ENDIAN + *(volatile u16 *) ((ulong) & tx4927_pcicptr-> + g2pcfgdata | ((where & 3) ^ 2)) = val; +#else + *(volatile u16 *) ((ulong) & tx4927_pcicptr-> + g2pcfgdata | (where & 3)) = val; +#endif +//printk("CFG W2 0x%02x 0x%02x 0x%08x\n", dev->devfn, where, val ); + return check_abort(flags); +} + +static int tx4927_pcibios_write_config_dword(struct pci_dev *dev, + int where, unsigned int val) +{ + int flags; + unsigned char bus, func_num; + + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + + /* check if the bus is top-level */ + if (dev->bus->parent != NULL) { + bus = dev->bus->number; + db_assert(bus != 0); + } else { + bus = 0; + } + + func_num = PCI_FUNC(dev->devfn); + if (mkaddr(bus, dev->devfn, where, &flags)) + return -1; + tx4927_pcicptr->g2pcfgdata = val; +//printk("CFG W4 0x%02x 0x%02x 0x%08x\n", dev->devfn, where, val ); + return check_abort(flags); +} + +struct pci_ops tx4927_pci_ops = { + tx4927_pcibios_read_config_byte, + tx4927_pcibios_read_config_word, + tx4927_pcibios_read_config_dword, + tx4927_pcibios_write_config_byte, + tx4927_pcibios_write_config_word, + tx4927_pcibios_write_config_dword +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,96 @@ +/* + * rbtx4927 specific prom routines + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifndef COMMAND_LINE_SIZE +#define COMMAND_LINE_SIZE CL_SIZE +#endif + +char arcs_cmdline[COMMAND_LINE_SIZE] = "console=ttyS0,38400 ip=any root=nfs rw"; + +void __init prom_init_cmdline(int argc, char **argv) +{ + int i; /* Always ignore the "-c" at argv[0] */ + + /* ignore all built-in args if any f/w args given */ + if (argc > 1) { + *arcs_cmdline = '\0'; + } + + for (i = 1; i < argc; i++) { + if (i != 1) { + strcat(arcs_cmdline, " "); + } + strcat(arcs_cmdline, argv[i]); + } +} + +void __init prom_init(int argc, char **argv, char **envp, int *pvec) +{ + extern int tx4927_get_mem_size(void); + int msize; + const char* toshiba_name_list[] = GROUP_TOSHIBA_NAMES; + extern char* toshiba_name; + + prom_init_cmdline(argc, argv); + + mips_machgroup = MACH_GROUP_TOSHIBA; + + if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) + mips_machtype = MACH_TOSHIBA_RBTX4927; + else + mips_machtype = MACH_TOSHIBA_RBTX4937; + + toshiba_name = toshiba_name_list[mips_machtype]; + + msize = tx4927_get_mem_size(); + add_memory_region(0, msize << 20, BOOT_MEM_RAM); +} + +void __init prom_free_prom_memory(void) +{ +} + + +void __init prom_fixup_mem_map(unsigned long start, unsigned long end) +{ +} + +const char *get_system_type(void) +{ + return "Toshiba RBTX4927/RBTX4937"; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,1218 @@ +/* + * Toshiba rbtx4927 specific setup + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * Copyright 2001-2002 MontaVista Software Inc. + * + * Copyright (C) 1996, 1997, 2001 Ralf Baechle + * Copyright (C) 2000 RidgeRun, Inc. + * Author: RidgeRun, Inc. + * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2002 MontaVista Software Inc. + * Author: Michael Pruznick, michael_pruznick@mvista.com + * + * Copyright (C) 2000-2001 Toshiba Corporation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_RTC_DS1742 +#include +#endif +#ifdef CONFIG_TOSHIBA_FPCIB0 +#include +#endif +#include +#ifdef CONFIG_PCI +#include +#include +#include +#include +#include +#include +#endif +#ifdef CONFIG_PC_KEYB +#include +#endif +#ifdef CONFIG_BLK_DEV_IDEPCI +#include +#include +#include +extern struct ide_ops std_ide_ops; +#endif + +#undef TOSHIBA_RBTX4927_SETUP_DEBUG + +#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG +#define TOSHIBA_RBTX4927_SETUP_NONE 0x00000000 + +#define TOSHIBA_RBTX4927_SETUP_INFO ( 1 << 0 ) +#define TOSHIBA_RBTX4927_SETUP_WARN ( 1 << 1 ) +#define TOSHIBA_RBTX4927_SETUP_EROR ( 1 << 2 ) + +#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 ) +#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 ) +#define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 ) +#define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 << 6 ) +#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 ) +#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 ) +#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 ) +#define TOSHIBA_RBTX4927_SETUP_PCI66 ( 1 << 10 ) + +#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff +#endif + +#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG +static const u32 toshiba_rbtx4927_setup_debug_flag = + (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO | + TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR | + TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP | + TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP + | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 | + TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66); +#endif + +#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG +#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \ + if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \ + { \ + char tmp[100]; \ + sprintf( tmp, str ); \ + printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \ + } +#else +#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) +#endif + +/* These functions are used for rebooting or halting the machine*/ +extern void toshiba_rbtx4927_restart(char *command); +extern void toshiba_rbtx4927_halt(void); +extern void toshiba_rbtx4927_power_off(void); + +int tx4927_using_backplane = 0; + +extern void gt64120_time_init(void); +extern void toshiba_rbtx4927_irq_setup(void); + +#ifdef CONFIG_PCI +#define CONFIG_TX4927BUG_WORKAROUND +#undef TX4927_SUPPORT_COMMAND_IO +#undef TX4927_SUPPORT_PCI_66 +int tx4927_cpu_clock = 100000000; /* 100MHz */ +unsigned long mips_pci_io_base; +unsigned long mips_pci_io_size; +unsigned long mips_pci_mem_base; +unsigned long mips_pci_mem_size; +/* for legacy I/O, PCI I/O PCI Bus address must be 0 */ +unsigned long mips_pci_io_pciaddr = 0; +unsigned long mips_memory_upper; +static int tx4927_ccfg_toeon = 1; +static int tx4927_pcic_trdyto = 0; /* default: disabled */ +unsigned long tx4927_ce_base[8]; +void tx4927_pci_setup(void); +void tx4927_reset_pci_pcic(void); +#ifdef TX4927_SUPPORT_PCI_66 +void tx4927_pci66_setup(void); +extern int tx4927_pci66_check(void); +#endif +int tx4927_pci66 = 0; /* 0:auto */ +#endif + +char *toshiba_name = ""; + +#ifdef CONFIG_PCI +void tx4927_dump_pcic_settings(void) +{ + printk("%s pcic settings:",toshiba_name); + { + int i; + unsigned long *preg = (unsigned long *) tx4927_pcicptr; + for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4) { + if (i % 32 == 0) + printk("\n%04x:", i); + if (preg == &tx4927_pcicptr->g2pintack + || preg == &tx4927_pcicptr->g2pspc +#ifdef CONFIG_TX4927BUG_WORKAROUND + || preg == &tx4927_pcicptr->g2pcfgadrs + || preg == &tx4927_pcicptr->g2pcfgdata +#endif + ) { + printk(" XXXXXXXX"); + preg++; + continue; + } + printk(" %08lx", *preg++); + if (preg == &tx4927_pcicptr->g2pcfgadrs) + break; + } + printk("\n"); + } +} + +static void tx4927_pcierr_interrupt(int irq, void *dev_id, + struct pt_regs *regs) +{ + extern void tx4927_dump_pcic_settings(void); + +#ifdef CONFIG_BLK_DEV_IDEPCI + /* ignore MasterAbort for ide probing... */ + if (irq == TX4927_IRQ_IRC_PCIERR && + ((tx4927_pcicptr->pcistatus >> 16) & 0xf900) == + PCI_STATUS_REC_MASTER_ABORT) { + tx4927_pcicptr->pcistatus = + (tx4927_pcicptr-> + pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT + << 16); + + return; + } +#endif + printk("PCI error interrupt (irq 0x%x).\n", irq); + printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n", + (unsigned short) (tx4927_pcicptr->pcistatus >> 16), + tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus); + printk("ccfg:%08lx, tear:%02lx_%08lx\n", + (unsigned long) tx4927_ccfgptr->ccfg, + (unsigned long) (tx4927_ccfgptr->tear >> 32), + (unsigned long) tx4927_ccfgptr->tear); + show_regs(regs); + //tx4927_dump_pcic_settings(); + panic("PCI error at PC:%08lx.", regs->cp0_epc); +} + +static struct irqaction pcic_action = { + tx4927_pcierr_interrupt, 0, 0, "PCI-C", NULL, NULL +}; + +static struct irqaction pcierr_action = { + tx4927_pcierr_interrupt, 0, 0, "PCI-ERR", NULL, NULL +}; + + +void __init toshiba_rbtx4927_pci_irq_init(void) +{ + setup_irq(TX4927_IRQ_IRC_PCIC, &pcic_action); + setup_irq(TX4927_IRQ_IRC_PCIERR, &pcierr_action); + return; +} + +void tx4927_reset_pci_pcic(void) +{ + /* Reset PCI Bus */ + *tx4927_pcireset_ptr = 1; + /* Reset PCIC */ + tx4927_ccfgptr->clkctr |= TX4927_CLKCTR_PCIRST; + udelay(10000); + /* clear PCIC reset */ + tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST; + *tx4927_pcireset_ptr = 0; +} +#endif /* CONFIG_PCI */ + +#ifdef CONFIG_PCI +#ifdef TX4927_SUPPORT_PCI_66 +void tx4927_pci66_setup(void) +{ + int pciclk, pciclkin = 1; + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI66, + "-\n"); + + if (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) + return; + + tx4927_reset_pci_pcic(); + + /* Assert M66EN */ + tx4927_ccfgptr->ccfg |= TX4927_CCFG_PCI66; + /* set PCICLK 66MHz */ + if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { + unsigned int pcidivmode = 0; + pcidivmode = + (unsigned long) tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIDIVMODE_MASK; + if (tx4927_cpu_clock >= 170000000) { + /* CPU 200MHz */ + pcidivmode = TX4927_CCFG_PCIDIVMODE_3; + pciclk = tx4927_cpu_clock / 3; + } else { + /* CPU 166MHz */ + pcidivmode = TX4927_CCFG_PCIDIVMODE_2_5; + pciclk = tx4927_cpu_clock * 2 / 5; + } + tx4927_ccfgptr->ccfg = + (tx4927_ccfgptr->ccfg & ~TX4927_CCFG_PCIDIVMODE_MASK) + | pcidivmode; + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCI66, + ":PCICLK: ccfg:0x%08lx\n", + (unsigned long) tx4927_ccfgptr->ccfg); + } else { + int pciclk_setting = *tx4927_pci_clk_ptr; + pciclkin = 0; + pciclk = 66666666; + pciclk_setting &= ~TX4927_PCI_CLK_MASK; + pciclk_setting |= TX4927_PCI_CLK_66; + *tx4927_pci_clk_ptr = pciclk_setting; + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCI66, + "PCICLK: pci_clk:%02x\n", *tx4927_pci_clk_ptr); + } + + udelay(10000); + + /* clear PCIC reset */ + tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST; + /* clear PCI reset */ + *tx4927_pcireset_ptr = 0; + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI66, + "+\n"); + return; +} +#endif /* TX4927_SUPPORT_PCI_66 */ + +void print_pci_status(void) +{ + printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus); + printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus); +} + +static struct pci_dev *fake_pci_dev(struct pci_channel *hose, + int top_bus, int busnr, int devfn) +{ + static struct pci_dev dev; + static struct pci_bus bus; + + dev.bus = &bus; + dev.sysdata = hose; + dev.devfn = devfn; + bus.number = busnr; + bus.ops = hose->pci_ops; + + if (busnr != top_bus) + /* Fake a parent bus structure. */ + bus.parent = &bus; + else + bus.parent = NULL; + + return &dev; +} + +#define EARLY_PCI_OP(rw, size, type) \ +static int early_##rw##_config_##size(struct pci_channel *hose, \ + int top_bus, int bus, int devfn, int offset, type value) \ +{ \ + return pci_##rw##_config_##size( \ + fake_pci_dev(hose, top_bus, bus, devfn), \ + offset, value); \ +} + +EARLY_PCI_OP(read, byte, u8 *) +EARLY_PCI_OP(read, word, u16 *) +EARLY_PCI_OP(read, dword, u32 *) +EARLY_PCI_OP(write, byte, u8) +EARLY_PCI_OP(write, word, u16) +EARLY_PCI_OP(write, dword, u32) + +static int __init tx4927_pcibios_init(int busno, struct pci_channel *hose) +{ + u32 pci_devfn; + int devfn_start = 0; + int devfn_stop = 0xff; + unsigned int id; + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS, + "-\n"); + + if (hose->first_devfn) + devfn_start = hose->first_devfn; + if (hose->last_devfn) + devfn_stop = hose->last_devfn; + + for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { + early_read_config_dword(hose, busno, busno, pci_devfn, + PCI_VENDOR_ID, &id); + + if (id == 0xffffffff) { + continue; + } + + if (id == 0x94601055) { + u8 v08_64; + u32 v32_b0; + u8 v08_e1; + char *s = " sb/isa --"; + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", + s); + + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x64, &v08_64); + early_read_config_dword(hose, busno, busno, + pci_devfn, 0xb0, &v32_b0); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0xe1, &v08_e1); + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s beg 0x64 = 0x%02x\n", s, v08_64); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s beg 0xb0 = 0x%02x\n", s, v32_b0); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s beg 0xe1 = 0x%02x\n", s, v08_e1); + + /* serial irq control */ + v08_64 = 0xd0; + + /* serial irq pin */ + v32_b0 |= 0x00010000; + + /* ide irq on isa14 */ + v08_e1 &= 0xf0; + v08_e1 |= 0x0d; + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s mid 0x64 = 0x%02x\n", s, v08_64); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s mid 0xb0 = 0x%02x\n", s, v32_b0); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s mid 0xe1 = 0x%02x\n", s, v08_e1); + + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x64, v08_64); + early_write_config_dword(hose, busno, busno, + pci_devfn, 0xb0, v32_b0); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0xe1, v08_e1); + +#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG + { + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x64, + &v08_64); + early_read_config_dword(hose, busno, busno, + pci_devfn, 0xb0, + &v32_b0); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0xe1, + &v08_e1); + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s end 0x64 = 0x%02x\n", s, v08_64); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s end 0xb0 = 0x%02x\n", s, v32_b0); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s end 0xe1 = 0x%02x\n", s, v08_e1); + } +#endif + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n", + s); + } + + if (id == 0x91301055) { + u8 v08_04; + u8 v08_09; + u8 v08_41; + u8 v08_43; + u8 v08_5c; + char *s = " sb/ide --"; + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n", + s); + + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x04, &v08_04); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x09, &v08_09); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x41, &v08_41); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x43, &v08_43); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x5c, &v08_5c); + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s beg 0x04 = 0x%02x\n", s, v08_04); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s beg 0x09 = 0x%02x\n", s, v08_09); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s beg 0x41 = 0x%02x\n", s, v08_41); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s beg 0x43 = 0x%02x\n", s, v08_43); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s beg 0x5c = 0x%02x\n", s, v08_5c); + + /* enable ide master/io */ + v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO); + + /* enable ide native mode */ + v08_09 |= 0x05; + + /* enable primary ide */ + v08_41 |= 0x80; + + /* enable secondary ide */ + v08_43 |= 0x80; + + /* + * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! + * + * This line of code is intended to provide the user with a work + * around solution to the anomalies cited in SMSC's anomaly sheet + * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"". + * + * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! + */ + v08_5c |= 0x01; + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s mid 0x04 = 0x%02x\n", s, v08_04); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s mid 0x09 = 0x%02x\n", s, v08_09); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s mid 0x41 = 0x%02x\n", s, v08_41); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s mid 0x43 = 0x%02x\n", s, v08_43); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s mid 0x5c = 0x%02x\n", s, v08_5c); + + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x5c, v08_5c); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x04, v08_04); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x09, v08_09); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x41, v08_41); + early_write_config_byte(hose, busno, busno, + pci_devfn, 0x43, v08_43); + +#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG + { + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x04, + &v08_04); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x09, + &v08_09); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x41, + &v08_41); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x43, + &v08_43); + early_read_config_byte(hose, busno, busno, + pci_devfn, 0x5c, + &v08_5c); + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s end 0x04 = 0x%02x\n", s, v08_04); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s end 0x09 = 0x%02x\n", s, v08_09); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s end 0x41 = 0x%02x\n", s, v08_41); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s end 0x43 = 0x%02x\n", s, v08_43); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, + ":%s end 0x5c = 0x%02x\n", s, v08_5c); + } +#endif + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n", + s); + } + + } + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS, + "+\n"); + + return (busno); +} + +extern struct resource pci_io_resource; +extern struct resource pci_mem_resource; + +void tx4927_pci_setup(void) +{ + static int called = 0; + extern unsigned int tx4927_get_mem_size(void); + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n"); + +#ifndef TX4927_SUPPORT_PCI_66 + if (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) + printk("PCI 66 current unsupported\n"); +#endif + + mips_memory_upper = tx4927_get_mem_size() << 20; + mips_memory_upper += KSEG0; + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, + "0x%08lx=mips_memory_upper\n", + mips_memory_upper); + mips_pci_io_base = TX4927_PCIIO; + mips_pci_io_size = TX4927_PCIIO_SIZE; + mips_pci_mem_base = TX4927_PCIMEM; + mips_pci_mem_size = TX4927_PCIMEM_SIZE; + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, + "0x%08lx=mips_pci_io_base\n", + mips_pci_io_base); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, + "0x%08lx=mips_pci_io_size\n", + mips_pci_io_size); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, + "0x%08lx=mips_pci_mem_base\n", + mips_pci_mem_base); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, + "0x%08lx=mips_pci_mem_size\n", + mips_pci_mem_size); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, + "0x%08lx=pci_io_resource.start\n", + pci_io_resource.start); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, + "0x%08lx=pci_io_resource.end\n", + pci_io_resource.end); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, + "0x%08lx=pci_mem_resource.start\n", + pci_mem_resource.start); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, + "0x%08lx=pci_mem_resource.end\n", + pci_mem_resource.end); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, + "0x%08lx=mips_io_port_base", + mips_io_port_base); + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, + "setup pci_io_resource to 0x%08lx 0x%08lx\n", + pci_io_resource.start, + pci_io_resource.end); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, + "setup pci_mem_resource to 0x%08lx 0x%08lx\n", + pci_mem_resource.start, + pci_mem_resource.end); + + if (!called) { + printk + ("TX4927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", + (unsigned short) (tx4927_pcicptr->pciid >> 16), + (unsigned short) (tx4927_pcicptr->pciid & 0xffff), + (unsigned short) (tx4927_pcicptr->pciccrev & 0xff), + (!(tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIXARB)) ? "External" : + "Internal"); + called = 1; + } + printk("%s PCIC --%s PCICLK:",toshiba_name, + (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); + if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { + int pciclk = 0; + switch ((unsigned long) tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { + case TX4927_CCFG_PCIDIVMODE_2_5: + pciclk = tx4927_cpu_clock * 2 / 5; + break; + case TX4927_CCFG_PCIDIVMODE_3: + pciclk = tx4927_cpu_clock / 3; + break; + case TX4927_CCFG_PCIDIVMODE_5: + pciclk = tx4927_cpu_clock / 5; + break; + case TX4927_CCFG_PCIDIVMODE_6: + pciclk = tx4927_cpu_clock / 6; + break; + } + printk("Internal(%dMHz)", pciclk / 1000000); + } else { + int pciclk = 0; + int pciclk_setting = *tx4927_pci_clk_ptr; + switch (pciclk_setting & TX4927_PCI_CLK_MASK) { + case TX4927_PCI_CLK_33: + pciclk = 33333333; + break; + case TX4927_PCI_CLK_25: + pciclk = 25000000; + break; + case TX4927_PCI_CLK_66: + pciclk = 66666666; + break; + case TX4927_PCI_CLK_50: + pciclk = 50000000; + break; + } + printk("External(%dMHz)", pciclk / 1000000); + } + printk("\n"); + + + + /* GB->PCI mappings */ + tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4; + tx4927_pcicptr->g2piogbase = mips_pci_io_base | +#ifdef __BIG_ENDIAN + TX4927_PCIC_G2PIOGBASE_ECHG +#else + TX4927_PCIC_G2PIOGBASE_BSDIS +#endif + ; + + tx4927_pcicptr->g2piopbase = 0; + + tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4; + tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base | +#ifdef __BIG_ENDIAN + TX4927_PCIC_G2PMnGBASE_ECHG +#else + TX4927_PCIC_G2PMnGBASE_BSDIS +#endif + ; + tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base; + + tx4927_pcicptr->g2pmmask[1] = 0; + tx4927_pcicptr->g2pmgbase[1] = 0; + tx4927_pcicptr->g2pmpbase[1] = 0; + tx4927_pcicptr->g2pmmask[2] = 0; + tx4927_pcicptr->g2pmgbase[2] = 0; + tx4927_pcicptr->g2pmpbase[2] = 0; + + + /* PCI->GB mappings (I/O 256B) */ + tx4927_pcicptr->p2giopbase = 0; /* 256B */ + + +#ifdef TX4927_SUPPORT_COMMAND_IO + tx4927_pcicptr->p2giogbase = 0 | TX4927_PCIC_P2GIOGBASE_TIOEN | +#ifdef __BIG_ENDIAN + TX4927_PCIC_P2GIOGBASE_TECHG +#else + TX4927_PCIC_P2GIOGBASE_TBSDIS +#endif + ; +#else + tx4927_pcicptr->p2giogbase = 0; +#endif + + /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */ + tx4927_pcicptr->p2gm0plbase = 0; + tx4927_pcicptr->p2gm0pubase = 0; + tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN | +#ifdef __BIG_ENDIAN + TX4927_PCIC_P2GMnGBASE_TECHG +#else + TX4927_PCIC_P2GMnGBASE_TBSDIS +#endif + ; + + /* PCI->GB mappings (MEM 16MB) -not used */ + tx4927_pcicptr->p2gm1plbase = 0xffffffff; +#ifdef CONFIG_TX4927BUG_WORKAROUND + /* + * TX4927-PCIC-BUG: P2GM1PUBASE must be 0 + * if P2GM0PUBASE was 0. + */ + tx4927_pcicptr->p2gm1pubase = 0; +#else + tx4927_pcicptr->p2gm1pubase = 0xffffffff; +#endif + tx4927_pcicptr->p2gmgbase[1] = 0; + + /* PCI->GB mappings (MEM 1MB) -not used */ + tx4927_pcicptr->p2gm2pbase = 0xffffffff; + tx4927_pcicptr->p2gmgbase[2] = 0; + + + /* Enable Initiator Memory 0 Space, I/O Space, Config */ + tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK; + tx4927_pcicptr->pciccfg |= + TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE | + TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR; + + + /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ + tx4927_pcicptr->pcicfg1 = 0; + + if (tx4927_pcic_trdyto >= 0) { + tx4927_pcicptr->g2ptocnt &= ~0xff; + tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff); + //printk("%s PCIC -- TRDYTO:%02lx\n",toshiba_name, + // tx4927_pcicptr->g2ptocnt & 0xff); + } + + /* Clear All Local Bus Status */ + tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL; + /* Enable All Local Bus Interrupts */ + tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL; + /* Clear All Initiator Status */ + tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL; + /* Enable All Initiator Interrupts */ + tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL; + /* Clear All PCI Status Error */ + tx4927_pcicptr->pcistatus = + (tx4927_pcicptr->pcistatus & 0x0000ffff) | + (TX4927_PCIC_PCISTATUS_ALL << 16); + /* Enable All PCI Status Error Interrupts */ + tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL; + + /* PCIC Int => IRC IRQ16 */ + tx4927_pcicptr->pcicfg2 = + (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC; + + if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) { + /* XXX */ + } else { + /* Reset Bus Arbiter */ + tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA; + /* Enable Bus Arbiter */ + tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN; + } + + tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | +#ifdef TX4927_SUPPORT_COMMAND_IO + PCI_COMMAND_IO | +#endif + PCI_COMMAND_PARITY | PCI_COMMAND_SERR; + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, + ":pci setup complete:\n"); + //tx4927_dump_pcic_settings(); + + { + struct pci_channel *p; + int busno; + + busno = 0; + for (p = mips_pci_channels; p->pci_ops != NULL; p++) { + busno = tx4927_pcibios_init(busno, p) + 1; + } + } + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n"); +} + +#endif /* CONFIG_PCI */ + +void toshiba_rbtx4927_restart(char *command) +{ + printk(KERN_NOTICE "System Rebooting...\n"); + + /* enable the s/w reset register */ + reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET); + + /* wait for enable to be seen */ + while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) & + RBTX4927_SW_RESET_ENABLE_SET) == 0x00); + + /* do a s/w reset */ + reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET); + + /* do something passive while waiting for reset */ + cli(); + while (1) + asm_wait(); + + /* no return */ +} + + +void toshiba_rbtx4927_halt(void) +{ + printk(KERN_NOTICE "System Halted\n"); + cli(); + while (1) { + asm_wait(); + } + /* no return */ +} + +void toshiba_rbtx4927_power_off(void) +{ + toshiba_rbtx4927_halt(); + /* no return */ +} + +void __init toshiba_rbtx4927_setup(void) +{ + vu32 cp0_config; + + printk("CPU is %s\n", toshiba_name); + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, + "-\n"); + + /* f/w leaves this on at startup */ + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, + ":Clearing STO_ERL.\n"); + clear_c0_status(ST0_ERL); + + /* enable caches -- HCP5 does this, pmon does not */ + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, + ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n"); + cp0_config = read_c0_config(); + cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); + write_c0_config(cp0_config); + +#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG + { + extern void dump_cp0(char *); + dump_cp0("toshiba_rbtx4927_early_fw_fixup"); + } +#endif + + /* setup irq stuff */ + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, + ":Setting up tx4927 pic.\n"); + TX4927_WR(0xff1ff604, 0x00000400); /* irq trigger */ + TX4927_WR(0xff1ff608, 0x00000000); /* irq trigger */ + + /* setup serial stuff */ + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, + ":Setting up tx4927 sio.\n"); + TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */ + TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */ + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, + "+\n"); + + + + mips_io_port_base = KSEG1 + TBTX4927_ISA_IO_OFFSET; + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, + ":mips_io_port_base=0x%08lx\n", + mips_io_port_base); + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, + ":Resource\n"); + ioport_resource.start = 0; + ioport_resource.end = 0xffffffff; + iomem_resource.start = 0; + iomem_resource.end = 0xffffffff; + + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, + ":ResetRoutines\n"); + _machine_restart = toshiba_rbtx4927_restart; + _machine_halt = toshiba_rbtx4927_halt; + _machine_power_off = toshiba_rbtx4927_power_off; + + +#ifdef CONFIG_BLK_DEV_IDEPCI + { + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":ide_ops=&std_ide_ops(modified)\n"); + ide_ops = &std_ide_ops; + } +#else + { + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":ide_ops=\n"); + } +#endif + +#ifdef CONFIG_FB + { + conswitchp = &dummy_con; + } +#endif + + + + +#ifdef CONFIG_PCI + + /* PCIC */ + /* + * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. + * PCIDIVMODE[12:11]'s initial value are given by S9[4:3] (ON:0, OFF:1). + * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) + * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) + * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) + * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) + * i.e. S9[3]: ON (83MHz), OFF (100MHz) + */ + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1, + "ccfg is %lx, DIV is %x\n", + (unsigned long) tx4927_ccfgptr-> + ccfg, TX4927_CCFG_PCIDIVMODE_MASK); + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1, + "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n", + (unsigned long) tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCI66, + (unsigned long) tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIMIDE, + (unsigned long) tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIXARB); + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1, + "PCIDIVMODE is %lx\n", + (unsigned long) tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIDIVMODE_MASK); + + switch ((unsigned long) tx4927_ccfgptr-> + ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { + case TX4927_CCFG_PCIDIVMODE_2_5: + case TX4927_CCFG_PCIDIVMODE_5: + tx4927_cpu_clock = 166000000; /* 166MHz */ + break; + default: + tx4927_cpu_clock = 200000000; /* 200MHz */ + } + + /* CCFG */ + /* enable Timeout BusError */ + if (tx4927_ccfg_toeon) + tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE; + + /* SDRAMC fixup */ +#ifdef CONFIG_TX4927BUG_WORKAROUND + /* + * TX4927-BUG: INF 01-01-18/ BUG 01-01-22 + * G-bus timeout error detection is incorrect + */ + if (tx4927_ccfg_toeon) + tx4927_sdramcptr->tr |= 0x02000000; /* RCD:3tck */ +#endif + +#ifdef TX4927_SUPPORT_PCI_66 + tx4927_pci66_setup(); +#endif + + tx4927_pci_setup(); +#endif + + + { + u32 id = 0; + early_read_config_dword(&mips_pci_channels[0], 0, 0, 0x90, + PCI_VENDOR_ID, &id); + if (id == 0x94601055) { + tx4927_using_backplane = 1; + printk("backplane board IS installed\n"); + } else { + printk("backplane board NOT installed\n"); + } + } + + + /* this is only done if backplane board installed, so must wait for pci */ +#ifdef CONFIG_PC_KEYB + { + if (tx4927_using_backplane) { + extern struct kbd_ops std_kbd_ops; + kbd_ops = &std_kbd_ops; + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":kbd_ops=&std_kbd_ops\n"); + } else { + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":kbd_ops=\n"); + } + } +#else + { + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":kbd_ops=\n"); + } +#endif + + /* this is on ISA bus behind PCI bus, so need PCI up first */ +#ifdef CONFIG_TOSHIBA_FPCIB0 + { + if (tx4927_using_backplane) { + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":fpcibo=yes\n"); + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":smsc_fdc37m81x_init()\n"); + smsc_fdc37m81x_init(0x3f0); + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":smsc_fdc37m81x_config_beg()\n"); + smsc_fdc37m81x_config_beg(); + + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":smsc_fdc37m81x_config_set(KBD)\n"); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM, + SMSC_FDC37M81X_KBD); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12); + smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE, + 1); + + smsc_fdc37m81x_config_end(); + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":smsc_fdc37m81x_config_end()\n"); + } else { + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, + ":fpcibo=not_found\n"); + } + } +#else + { + TOSHIBA_RBTX4927_SETUP_DPRINTK + (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n"); + } +#endif + + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, + "+\n"); +} + +void __init +toshiba_rbtx4927_time_init(void) +{ + u32 c1; + u32 c2; + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n"); + +#ifdef CONFIG_RTC_DS1742 + + rtc_get_time = rtc_ds1742_get_time; + rtc_set_time = rtc_ds1742_set_time; + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, + ":rtc_ds1742_init()-\n"); + rtc_ds1742_init(0xbc010000); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, + ":rtc_ds1742_init()+\n"); + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, + ":Calibrate mips_counter_frequency-\n"); + rtc_ds1742_wait(); + + /* get the count */ + c1 = read_c0_count(); + + /* wait for the seconds to change again */ + rtc_ds1742_wait(); + + /* get the count again */ + c2 = read_c0_count(); + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, + ":Calibrate mips_counter_frequency+\n"); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, + ":c1=%12u\n", c1); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, + ":c2=%12u\n", c2); + + /* this diff is as close as we are going to get to counter ticks per sec */ + mips_counter_frequency = abs(c2 - c1); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, + ":f1=%12u\n", mips_counter_frequency); + + /* round to 1/10th of a MHz */ + mips_counter_frequency /= (100 * 1000); + mips_counter_frequency *= (100 * 1000); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, + ":f2=%12u\n", mips_counter_frequency); + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_INFO, + ":mips_counter_frequency=%uHz (%uMHz)\n", + mips_counter_frequency, + mips_counter_frequency / 1000000); +#else + mips_counter_frequency = 100000000; +#endif + + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n"); + +} + +void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq) +{ + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP, + "-\n"); + TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP, + "+\n"); +} --- linux-2.5.73/arch/mips/vmlinux.lds.S 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/mips/vmlinux.lds.S 2003-06-27 15:56:23.000000000 -0700 @@ -2,19 +2,20 @@ OUTPUT_ARCH(mips) ENTRY(kernel_entry) +jiffies = JIFFIES32; SECTIONS { - /* Read-only sections, merged into text segment: */ . = LOADADDR; - .init : { *(.init) } =0 - .text : - { - _ftext = . ; + /* read-only */ + _text = .; /* Text and read-only data */ + .text : { *(.text) - /* .gnu.warning sections are handled specially by elf32.em. */ + *(.fixup) *(.gnu.warning) } =0 + _etext = .; /* End of text section */ + . = ALIGN(16); /* Exception table */ __start___ex_table = .; __ex_table : { *(__ex_table) } @@ -25,29 +26,73 @@ SECTIONS __stop___dbe_table = .; RODATA - - _etext = .; - . = ALIGN(8192); - .data.init_task : { *(.data.init_task) } + . = ALIGN(64); + + /* writeable */ + .data : { /* Data */ + *(.data) + + /* Align the initial ramdisk image (INITRD) on page boundaries. */ + . = ALIGN(4096); + __rd_start = .; + *(.initrd) + . = ALIGN(4096); + __rd_end = .; + + CONSTRUCTORS + } + _gp = . + 0x8000; + .lit8 : { *(.lit8) } + .lit4 : { *(.lit4) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata : { *(.sdata) } + + . = ALIGN(4096); + __nosave_begin = .; + .data_nosave : { *(.data.nosave) } + . = ALIGN(4096); + __nosave_end = .; - /* Startup code */ . = ALIGN(4096); + .data.page_aligned : { *(.data.idt) } + + . = ALIGN(32); + .data.cacheline_aligned : { *(.data.cacheline_aligned) } + + _edata = .; /* End of data section */ + + . = ALIGN(8192); /* init_task */ + .data.init_task : { *(.data.init_task) } + + /* will be freed after init */ + . = ALIGN(4096); /* Init code and data */ __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } + /* /DISCARD/ doesn't work for .reginfo */ + .reginfo : { *(.reginfo) } + .init.text : { + _sinittext = .; + *(.init.text) + _einittext = .; + } + .init.data : { *(.init.data) } . = ALIGN(16); __setup_start = .; - .setup.init : { *(.setup.init) } + .init.setup : { *(.init.setup) } __setup_end = .; + __start___param = .; + __param : { *(__param) } + __stop___param = .; __initcall_start = .; .initcall.init : { - *(.initcall1.init) - *(.initcall2.init) - *(.initcall3.init) - *(.initcall4.init) - *(.initcall5.init) - *(.initcall6.init) + *(.initcall1.init) + *(.initcall2.init) + *(.initcall3.init) + *(.initcall4.init) + *(.initcall5.init) + *(.initcall6.init) *(.initcall7.init) } __initcall_end = .; @@ -55,80 +100,35 @@ SECTIONS .con_initcall.init : { *(.con_initcall.init) } __con_initcall_end = .; SECURITY_INIT - . = ALIGN(4096); /* Align double page for init_task_union */ - __init_end = .; - . = ALIGN(4096); - .data.page_aligned : { *(.data.idt) } - + __initramfs_start = .; + .init.ramfs : { *(.init.ramfs) } + __initramfs_end = .; . = ALIGN(32); - .data.cacheline_aligned : { *(.data.cacheline_aligned) } - - .fini : { *(.fini) } =0 - .reginfo : { *(.reginfo) } - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. It would - be more correct to do this: - . = .; - The current expression does not correctly handle the case of a - text segment ending precisely at the end of a page; it causes the - data segment to skip a page. The above expression does not have - this problem, but it will currently (2/95) cause BFD to allocate - a single segment, combining both text and data, for this case. - This will prevent the text segment from being shared among - multiple executions of the program; I think that is more - important than losing a page of the virtual address space (note - that no actual memory is lost; the page which is skipped can not - be referenced). */ - . = .; - .data : - { - _fdata = . ; - *(.data) - - /* Align the initial ramdisk image (INITRD) on page boundaries. */ - . = ALIGN(4096); - __rd_start = .; - *(.initrd) - __rd_end = .; - . = ALIGN(4096); + __per_cpu_start = .; + .data.percpu : { *(.data.percpu) } + __per_cpu_end = .; + . = ALIGN(4096); + __init_end = .; + /* freed after init ends here */ - CONSTRUCTORS + __bss_start = .; /* BSS */ + .sbss : { + *(.sbss) + *(.scommon) } - .data1 : { *(.data1) } - _gp = . + 0x8000; - .lit8 : { *(.lit8) } - .lit4 : { *(.lit4) } - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - .got : { *(.got.plt) *(.got) } - .dynamic : { *(.dynamic) } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata : { *(.sdata) } - . = ALIGN(4); - _edata = .; - PROVIDE (edata = .); - - __bss_start = .; - _fbss = .; - .sbss : { *(.sbss) *(.scommon) } - .bss : - { - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - _end = . ; - PROVIDE (end = .); + .bss : { + *(.bss) + *(COMMON) } + __bss_stop = .; + + _end = . ; /* Sections to be discarded */ - /DISCARD/ : - { - *(.text.exit) - *(.data.exit) + /DISCARD/ : { + *(.exit.text) + *(.exit.data) *(.exitcall.exit) } --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/casio-e55/ide-e55.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,99 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * IDE routines for typical pc-like standard configurations + * for the CASIO CASSIOPEIA E-55/65. + * + * Copyright (C) 1998, 1999, 2001 by Ralf Baechle + */ +/* + * Changes: + * Yoichi Yuasa Sun, 24 Feb 2002 + * - Added CASIO CASSIOPEIA E-55/65 support. + */ +#include +#include +#include +#include +#include +#include + +static int e55_ide_default_irq(ide_ioreg_t base) +{ + return 40; +} + +static ide_ioreg_t e55_ide_default_io_base(int index) +{ + switch (index) { + case 0: return 0xc1f0; + case 1: return 0xc170; + case 2: return 0xc1e8; + case 3: return 0xc168; + case 4: return 0xc1e0; + case 5: return 0xc160; + } + return 0; +} + +static void e55_ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port, + ide_ioreg_t ctrl_port, int *irq) +{ + ide_ioreg_t reg = data_port; + int i; + + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { + hw->io_ports[i] = reg; + reg += 1; + } + if (ctrl_port) { + hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; + } else { + hw->io_ports[IDE_CONTROL_OFFSET] = hw->io_ports[IDE_DATA_OFFSET] + 0x206; + } + if (irq != NULL) + *irq = 0; + hw->io_ports[IDE_IRQ_OFFSET] = 0; +} + +static int e55_ide_request_irq(unsigned int irq, + void (*handler)(int,void *, struct pt_regs *), + unsigned long flags, const char *device, + void *dev_id) +{ + return request_irq(irq, handler, flags, device, dev_id); +} + +static void e55_ide_free_irq(unsigned int irq, void *dev_id) +{ + free_irq(irq, dev_id); +} + +static int e55_ide_check_region(ide_ioreg_t from, unsigned int extent) +{ + return check_region(from, extent); +} + +static void e55_ide_request_region(ide_ioreg_t from, unsigned int extent, + const char *name) +{ + request_region(from, extent, name); +} + +static void e55_ide_release_region(ide_ioreg_t from, unsigned int extent) +{ + release_region(from, extent); +} + +struct ide_ops e55_ide_ops = { + &e55_ide_default_irq, + &e55_ide_default_io_base, + &e55_ide_init_hwif_ports, + &e55_ide_request_irq, + &e55_ide_free_irq, + &e55_ide_check_region, + &e55_ide_request_region, + &e55_ide_release_region +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/casio-e55/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,49 @@ +/* + * FILE NAME + * arch/mips/vr41xx/casio-e55/init.c + * + * BRIEF MODULE DESCRIPTION + * Initialisation code for the CASIO CASSIOPEIA E-55/65. + * + * Copyright 2002 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include + +#include + +char arcs_cmdline[CL_SIZE]; + +const char *get_system_type(void) +{ + return "CASIO CASSIOPEIA E-11/15/55/65"; +} + +void __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec) +{ + int i; + + /* + * collect args and prepare cmd_line + */ + for (i = 1; i < argc; i++) { + strcat(arcs_cmdline, argv[i]); + if (i < (argc - 1)) + strcat(arcs_cmdline, " "); + } + + mips_machgroup = MACH_GROUP_NEC_VR41XX; + mips_machtype = MACH_CASIO_E55; +} + +void __init prom_free_prom_memory (void) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/casio-e55/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,7 @@ +# +# Makefile for the CASIO CASSIOPEIA E-55/65 specific parts of the kernel +# + +obj-y += init.o setup.o + +obj-$(CONFIG_IDE) += ide-e55.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/casio-e55/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,74 @@ +/* + * FILE NAME + * arch/mips/vr41xx/casio-e55/setup.c + * + * BRIEF MODULE DESCRIPTION + * Setup for the CASIO CASSIOPEIA E-11/15/55/65. + * + * Copyright 2002 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_BLK_DEV_INITRD +extern unsigned long initrd_start, initrd_end; +extern void * __rd_start, * __rd_end; +#endif + +#ifdef CONFIG_BLK_DEV_IDE +extern struct ide_ops e55_ide_ops; +#endif + +void __init casio_e55_setup(void) +{ + set_io_port_base(IO_PORT_BASE); + ioport_resource.start = IO_PORT_RESOURCE_START; + ioport_resource.end = IO_PORT_RESOURCE_END; + iomem_resource.start = IO_MEM_RESOURCE_START; + iomem_resource.end = IO_MEM_RESOURCE_END; + +#ifdef CONFIG_BLK_DEV_INITRD + ROOT_DEV = Root_RAM0; + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; +#endif + + _machine_restart = vr41xx_restart; + _machine_halt = vr41xx_halt; + _machine_power_off = vr41xx_power_off; + + board_time_init = vr41xx_time_init; + board_timer_setup = vr41xx_timer_setup; + +#ifdef CONFIG_FB + conswitchp = &dummy_con; +#endif + +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &e55_ide_ops; +#endif + + vr41xx_bcu_init(); + + vr41xx_cmu_init(0); + +#ifdef CONFIG_SERIAL_8250 + vr41xx_siu_init(SIU_RS232C, 0); +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/common/bcu.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,206 @@ +/* + * FILE NAME + * arch/mips/vr41xx/common/bcu.c + * + * BRIEF MODULE DESCRIPTION + * Bus Control Unit routines for the NEC VR4100 series. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Changes: + * MontaVista Software Inc. or + * - Added support for NEC VR4111 and VR4121. + * + * Paul Mundt + * - Calculate mips_counter_frequency properly on VR4131. + * + * MontaVista Software Inc. or + * - New creation, NEC VR4122 and VR4131 are supported. + */ +#include +#include + +#include +#include +#include +#include +#include + +#define VR4111_CLKSPEEDREG KSEG1ADDR(0x0b000014) +#define VR4122_CLKSPEEDREG KSEG1ADDR(0x0f000014) +#define VR4131_CLKSPEEDREG VR4122_CLKSPEEDREG + #define CLKSP(x) ((x) & 0x001f) + + #define DIV2B 0x8000 + #define DIV3B 0x4000 + #define DIV4B 0x2000 + + #define DIVT(x) (((x) & 0xf000) >> 12) + #define DIVVT(x) (((x) & 0x0f00) >> 8) + + #define TDIVMODE(x) (2 << (((x) & 0x1000) >> 12)) + #define VTDIVMODE(x) (((x) & 0x0700) >> 8) + +unsigned long vr41xx_vtclock = 0; + +static inline u16 read_clkspeed(void) +{ + switch (current_cpu_data.cputype) { + case CPU_VR4111: + case CPU_VR4121: return readw(VR4111_CLKSPEEDREG); + case CPU_VR4122: return readw(VR4122_CLKSPEEDREG); + case CPU_VR4131: return readw(VR4131_CLKSPEEDREG); + default: + printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); + break; + } + + return 0; +} + +static inline unsigned long calculate_pclock(u16 clkspeed) +{ + unsigned long pclock = 0; + + switch (current_cpu_data.cputype) { + case CPU_VR4111: + case CPU_VR4121: + pclock = 18432000 * 64; + break; + case CPU_VR4122: + pclock = 18432000 * 98; + break; + case CPU_VR4131: + pclock = 18432000 * 108; + break; + default: + printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); + break; + } + + pclock /= CLKSP(clkspeed); + printk(KERN_INFO "PClock: %ldHz\n", pclock); + + return pclock; +} + +static inline unsigned long calculate_vtclock(u16 clkspeed, unsigned long pclock) +{ + switch (current_cpu_data.cputype) { + case CPU_VR4111: + /* The NEC VR4111 doesn't have the VTClock. */ + break; + case CPU_VR4121: + vr41xx_vtclock = pclock; + /* DIVVT == 9 Divide by 1.5 . VTClock = (PClock * 6) / 9 */ + if (DIVVT(clkspeed) == 9) + vr41xx_vtclock = pclock * 6; + /* DIVVT == 10 Divide by 2.5 . VTClock = (PClock * 4) / 10 */ + else if (DIVVT(clkspeed) == 10) + vr41xx_vtclock = pclock * 4; + vr41xx_vtclock /= DIVVT(clkspeed); + printk(KERN_INFO "VTClock: %ldHz\n", vr41xx_vtclock); + break; + case CPU_VR4122: + if(VTDIVMODE(clkspeed) == 7) + vr41xx_vtclock = pclock / 1; + else if(VTDIVMODE(clkspeed) == 1) + vr41xx_vtclock = pclock / 2; + else + vr41xx_vtclock = pclock / VTDIVMODE(clkspeed); + printk(KERN_INFO "VTClock: %ldHz\n", vr41xx_vtclock); + break; + case CPU_VR4131: + vr41xx_vtclock = pclock / VTDIVMODE(clkspeed); + printk(KERN_INFO "VTClock: %ldHz\n", vr41xx_vtclock); + break; + default: + printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); + break; + } + + return vr41xx_vtclock; +} + +static inline unsigned long calculate_tclock(u16 clkspeed, unsigned long pclock, + unsigned long vtclock) +{ + unsigned long tclock = 0; + + switch (current_cpu_data.cputype) { + case CPU_VR4111: + if (!(clkspeed & DIV2B)) + tclock = pclock / 2; + else if (!(clkspeed & DIV3B)) + tclock = pclock / 3; + else if (!(clkspeed & DIV4B)) + tclock = pclock / 4; + break; + case CPU_VR4121: + tclock = pclock / DIVT(clkspeed); + break; + case CPU_VR4122: + case CPU_VR4131: + tclock = vtclock / TDIVMODE(clkspeed); + break; + default: + printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); + break; + } + + printk(KERN_INFO "TClock: %ldHz\n", tclock); + + return tclock; +} + +static inline unsigned long calculate_mips_counter_frequency(unsigned long tclock) +{ + /* + * VR4131 Revision 2.0 and 2.1 use a value of (tclock / 2). + */ + if ((current_cpu_data.processor_id == PRID_VR4131_REV2_0) || + (current_cpu_data.processor_id == PRID_VR4131_REV2_1)) + tclock /= 2; + else + tclock /= 4; + + return tclock; +} + +void __init vr41xx_bcu_init(void) +{ + unsigned long pclock, vtclock, tclock; + u16 clkspeed; + + clkspeed = read_clkspeed(); + + pclock = calculate_pclock(clkspeed); + vtclock = calculate_vtclock(clkspeed, pclock); + tclock = calculate_tclock(clkspeed, pclock, vtclock); + + mips_counter_frequency = calculate_mips_counter_frequency(tclock); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/common/cmu.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,84 @@ +/* + * FILE NAME + * arch/mips/vr41xx/common/cmu.c + * + * BRIEF MODULE DESCRIPTION + * Clock Mask Unit routines for the NEC VR4100 series. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2001,2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Changes: + * MontaVista Software Inc. or + * - Added support for NEC VR4111 and VR4121. + * + * MontaVista Software Inc. or + * - New creation, NEC VR4122 and VR4131 are supported. + */ +#include +#include + +#include +#include + +#define VR4111_CMUCLKMSK KSEG1ADDR(0x0b000060) +#define VR4122_CMUCLKMSK KSEG1ADDR(0x0f000060) + +static u32 vr41xx_cmu_base = 0; +static u16 cmuclkmsk = 0; + +#define write_cmu(mask) writew((mask), vr41xx_cmu_base) + +void vr41xx_clock_supply(u16 mask) +{ + cmuclkmsk |= mask; + write_cmu(cmuclkmsk); +} + +void vr41xx_clock_mask(u16 mask) +{ + cmuclkmsk &= ~mask; + write_cmu(cmuclkmsk); +} + +void __init vr41xx_cmu_init(u16 mask) +{ + switch (current_cpu_data.cputype) { + case CPU_VR4111: + case CPU_VR4121: + vr41xx_cmu_base = VR4111_CMUCLKMSK; + break; + case CPU_VR4122: + case CPU_VR4131: + vr41xx_cmu_base = VR4122_CMUCLKMSK; + break; + default: + panic("Unexpected CPU of NEC VR4100 series"); + break; + } + + cmuclkmsk = mask; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/common/giu.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,267 @@ +/* + * FILE NAME + * arch/mips/vr41xx/common/giu.c + * + * BRIEF MODULE DESCRIPTION + * General-purpose I/O Unit Interrupt routines for NEC VR4100 series. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Changes: + * MontaVista Software Inc. or + * - New creation, NEC VR4111, VR4121, VR4122 and VR4131 are supported. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define VR4111_GIUIOSELL KSEG1ADDR(0x0b000100) +#define VR4122_GIUIOSELL KSEG1ADDR(0x0f000140) + +#define GIUIOSELL 0x00 +#define GIUIOSELH 0x02 +#define GIUINTSTATL 0x08 +#define GIUINTSTATH 0x0a +#define GIUINTENL 0x0c +#define GIUINTENH 0x0e +#define GIUINTTYPL 0x10 +#define GIUINTTYPH 0x12 +#define GIUINTALSELL 0x14 +#define GIUINTALSELH 0x16 +#define GIUINTHTSELL 0x18 +#define GIUINTHTSELH 0x1a + +u32 vr41xx_giu_base = 0; + +#define read_giuint(offset) readw(vr41xx_giu_base + (offset)) +#define write_giuint(val, offset) writew((val), vr41xx_giu_base + (offset)) + +static inline u16 set_giuint(u16 offset, u16 set) +{ + u16 res; + + res = read_giuint(offset); + res |= set; + write_giuint(res, offset); + + return res; +} + +static inline u16 clear_giuint(u16 offset, u16 clear) +{ + u16 res; + + res = read_giuint(offset); + res &= ~clear; + write_giuint(res, offset); + + return res; +} + +void vr41xx_enable_giuint(int pin) +{ + if (pin < 16) + set_giuint(GIUINTENL, (u16)1 << pin); + else + set_giuint(GIUINTENH, (u16)1 << (pin - 16)); +} + +void vr41xx_disable_giuint(int pin) +{ + if (pin < 16) + clear_giuint(GIUINTENL, (u16)1 << pin); + else + clear_giuint(GIUINTENH, (u16)1 << (pin - 16)); +} + +void vr41xx_clear_giuint(int pin) +{ + if (pin < 16) + write_giuint((u16)1 << pin, GIUINTSTATL); + else + write_giuint((u16)1 << (pin - 16), GIUINTSTATH); +} + +void vr41xx_set_irq_trigger(int pin, int trigger, int hold) +{ + u16 mask; + + if (pin < 16) { + mask = (u16)1 << pin; + if (trigger == TRIGGER_EDGE) { + set_giuint(GIUINTTYPL, mask); + if (hold == SIGNAL_HOLD) + set_giuint(GIUINTHTSELL, mask); + else + clear_giuint(GIUINTHTSELL, mask); + } else { + clear_giuint(GIUINTTYPL, mask); + clear_giuint(GIUINTHTSELL, mask); + } + } else { + mask = (u16)1 << (pin - 16); + if (trigger == TRIGGER_EDGE) { + set_giuint(GIUINTTYPH, mask); + if (hold == SIGNAL_HOLD) + set_giuint(GIUINTHTSELH, mask); + else + clear_giuint(GIUINTHTSELH, mask); + } else { + clear_giuint(GIUINTTYPH, mask); + clear_giuint(GIUINTHTSELH, mask); + } + } + + vr41xx_clear_giuint(pin); +} + +void vr41xx_set_irq_level(int pin, int level) +{ + u16 mask; + + if (pin < 16) { + mask = (u16)1 << pin; + if (level == LEVEL_HIGH) + set_giuint(GIUINTALSELL, mask); + else + clear_giuint(GIUINTALSELL, mask); + } else { + mask = (u16)1 << (pin - 16); + if (level == LEVEL_HIGH) + set_giuint(GIUINTALSELH, mask); + else + clear_giuint(GIUINTALSELH, mask); + } + + vr41xx_clear_giuint(pin); +} + +#define GIUINT_NR_IRQS 32 + +enum { + GIUINT_NO_CASCADE, + GIUINT_CASCADE +}; + +struct vr41xx_giuint_cascade { + unsigned int flag; + int (*get_irq_number)(int irq); +}; + +static struct vr41xx_giuint_cascade giuint_cascade[GIUINT_NR_IRQS]; +static struct irqaction giu_cascade = {no_action, 0, 0, "cascade", NULL, NULL}; + +static int no_irq_number(int irq) +{ + return -EINVAL; +} + +int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq)) +{ + unsigned int pin; + int retval; + + if (irq < GIU_IRQ(0) || irq > GIU_IRQ(31)) + return -EINVAL; + + if(!get_irq_number) + return -EINVAL; + + pin = irq - GIU_IRQ(0); + giuint_cascade[pin].flag = GIUINT_CASCADE; + giuint_cascade[pin].get_irq_number = get_irq_number; + + retval = setup_irq(irq, &giu_cascade); + if (retval) { + giuint_cascade[pin].flag = GIUINT_NO_CASCADE; + giuint_cascade[pin].get_irq_number = no_irq_number; + } + + return retval; +} + +unsigned int giuint_do_IRQ(int pin, struct pt_regs *regs) +{ + struct vr41xx_giuint_cascade *cascade; + unsigned int retval = 0; + int giuint_irq, cascade_irq; + + disable_irq(GIUINT_CASCADE_IRQ); + cascade = &giuint_cascade[pin]; + giuint_irq = pin + GIU_IRQ(0); + if (cascade->flag == GIUINT_CASCADE) { + cascade_irq = cascade->get_irq_number(giuint_irq); + disable_irq(giuint_irq); + if (cascade_irq > 0) + retval = do_IRQ(cascade_irq, regs); + enable_irq(giuint_irq); + } else + retval = do_IRQ(giuint_irq, regs); + enable_irq(GIUINT_CASCADE_IRQ); + + return retval; +} + +void (*board_irq_init)(void) = NULL; + +void __init vr41xx_giuint_init(void) +{ + int i; + + switch (current_cpu_data.cputype) { + case CPU_VR4111: + case CPU_VR4121: + vr41xx_giu_base = VR4111_GIUIOSELL; + break; + case CPU_VR4122: + case CPU_VR4131: + vr41xx_giu_base = VR4122_GIUIOSELL; + break; + default: + panic("GIU: Unexpected CPU of NEC VR4100 series"); + break; + } + + for (i = 0; i < GIUINT_NR_IRQS; i++) { + vr41xx_disable_giuint(i); + giuint_cascade[i].flag = GIUINT_NO_CASCADE; + giuint_cascade[i].get_irq_number = no_irq_number; + } + + if (setup_irq(GIUINT_CASCADE_IRQ, &giu_cascade)) + printk("GIUINT: Can not cascade IRQ %d.\n", GIUINT_CASCADE_IRQ); + + if (board_irq_init) + board_irq_init(); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/common/icu.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,407 @@ +/* + * FILE NAME + * arch/mips/vr41xx/vr4122/common/icu.c + * + * BRIEF MODULE DESCRIPTION + * Interrupt Control Unit routines for the NEC VR4122 and VR4131. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2001,2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Changes: + * MontaVista Software Inc. or + * - Added support for NEC VR4111 and VR4121. + * + * Paul Mundt + * - kgdb support. + * + * MontaVista Software Inc. or + * - New creation, NEC VR4122 and VR4131 are supported. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +extern asmlinkage void vr41xx_handle_interrupt(void); + +extern void __init init_generic_irq(void); +extern void mips_cpu_irq_init(u32 irq_base); + +extern void vr41xx_giuint_init(void); +extern unsigned int giuint_do_IRQ(int pin, struct pt_regs *regs); + +static u32 vr41xx_icu1_base = 0; +static u32 vr41xx_icu2_base = 0; + +#define VR4111_SYSINT1REG KSEG1ADDR(0x0b000080) +#define VR4111_SYSINT2REG KSEG1ADDR(0x0b000200) + +#define VR4122_SYSINT1REG KSEG1ADDR(0x0f000080) +#define VR4122_SYSINT2REG KSEG1ADDR(0x0f0000a0) + +#define SYSINT1REG 0x00 +#define GIUINTLREG 0x08 +#define MSYSINT1REG 0x0c +#define MGIUINTLREG 0x14 +#define NMIREG 0x18 +#define SOFTREG 0x1a + +#define SYSINT2REG 0x00 +#define GIUINTHREG 0x02 +#define MSYSINT2REG 0x06 +#define MGIUINTHREG 0x08 + +#define read_icu1(offset) readw(vr41xx_icu1_base + (offset)) +#define write_icu1(val, offset) writew((val), vr41xx_icu1_base + (offset)) + +#define read_icu2(offset) readw(vr41xx_icu2_base + (offset)) +#define write_icu2(val, offset) writew((val), vr41xx_icu2_base + (offset)) + +static inline u16 set_icu1(u16 offset, u16 set) +{ + u16 res; + + res = read_icu1(offset); + res |= set; + write_icu1(res, offset); + + return res; +} + +static inline u16 clear_icu1(u16 offset, u16 clear) +{ + u16 res; + + res = read_icu1(offset); + res &= ~clear; + write_icu1(res, offset); + + return res; +} + +static inline u16 set_icu2(u16 offset, u16 set) +{ + u16 res; + + res = read_icu2(offset); + res |= set; + write_icu2(res, offset); + + return res; +} + +static inline u16 clear_icu2(u16 offset, u16 clear) +{ + u16 res; + + res = read_icu2(offset); + res &= ~clear; + write_icu2(res, offset); + + return res; +} + +/*=======================================================================*/ + +static void enable_sysint1_irq(unsigned int irq) +{ + set_icu1(MSYSINT1REG, (u16)1 << (irq - SYSINT1_IRQ_BASE)); +} + +static void disable_sysint1_irq(unsigned int irq) +{ + clear_icu1(MSYSINT1REG, (u16)1 << (irq - SYSINT1_IRQ_BASE)); +} + +static unsigned int startup_sysint1_irq(unsigned int irq) +{ + set_icu1(MSYSINT1REG, (u16)1 << (irq - SYSINT1_IRQ_BASE)); + + return 0; /* never anything pending */ +} + +#define shutdown_sysint1_irq disable_sysint1_irq +#define ack_sysint1_irq disable_sysint1_irq + +static void end_sysint1_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + set_icu1(MSYSINT1REG, (u16)1 << (irq - SYSINT1_IRQ_BASE)); +} + +static struct hw_interrupt_type sysint1_irq_type = { + "SYSINT1", + startup_sysint1_irq, + shutdown_sysint1_irq, + enable_sysint1_irq, + disable_sysint1_irq, + ack_sysint1_irq, + end_sysint1_irq, + NULL +}; + +/*=======================================================================*/ + +static void enable_sysint2_irq(unsigned int irq) +{ + set_icu2(MSYSINT2REG, (u16)1 << (irq - SYSINT2_IRQ_BASE)); +} + +static void disable_sysint2_irq(unsigned int irq) +{ + clear_icu2(MSYSINT2REG, (u16)1 << (irq - SYSINT2_IRQ_BASE)); +} + +static unsigned int startup_sysint2_irq(unsigned int irq) +{ + set_icu2(MSYSINT2REG, (u16)1 << (irq - SYSINT2_IRQ_BASE)); + + return 0; /* never anything pending */ +} + +#define shutdown_sysint2_irq disable_sysint2_irq +#define ack_sysint2_irq disable_sysint2_irq + +static void end_sysint2_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + set_icu2(MSYSINT2REG, (u16)1 << (irq - SYSINT2_IRQ_BASE)); +} + +static struct hw_interrupt_type sysint2_irq_type = { + "SYSINT2", + startup_sysint2_irq, + shutdown_sysint2_irq, + enable_sysint2_irq, + disable_sysint2_irq, + ack_sysint2_irq, + end_sysint2_irq, + NULL +}; + +/*=======================================================================*/ + +static void enable_giuint_irq(unsigned int irq) +{ + int pin; + + pin = irq - GIU_IRQ_BASE; + if (pin < 16) + set_icu1(MGIUINTLREG, (u16)1 << pin); + else + set_icu2(MGIUINTHREG, (u16)1 << (pin - 16)); + + vr41xx_enable_giuint(pin); +} + +static void disable_giuint_irq(unsigned int irq) +{ + int pin; + + pin = irq - GIU_IRQ_BASE; + vr41xx_disable_giuint(pin); + + if (pin < 16) + clear_icu1(MGIUINTLREG, (u16)1 << pin); + else + clear_icu2(MGIUINTHREG, (u16)1 << (pin - 16)); +} + +static unsigned int startup_giuint_irq(unsigned int irq) +{ + vr41xx_clear_giuint(irq - GIU_IRQ_BASE); + + enable_giuint_irq(irq); + + return 0; /* never anything pending */ +} + +#define shutdown_giuint_irq disable_giuint_irq + +static void ack_giuint_irq(unsigned int irq) +{ + disable_giuint_irq(irq); + + vr41xx_clear_giuint(irq - GIU_IRQ_BASE); +} + +static void end_giuint_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + enable_giuint_irq(irq); +} + +static struct hw_interrupt_type giuint_irq_type = { + "GIUINT", + startup_giuint_irq, + shutdown_giuint_irq, + enable_giuint_irq, + disable_giuint_irq, + ack_giuint_irq, + end_giuint_irq, + NULL +}; + +/*=======================================================================*/ + +static struct irqaction icu_cascade = {no_action, 0, 0, "cascade", NULL, NULL}; + +static void __init vr41xx_icu_init(void) +{ + int i; + + switch (current_cpu_data.cputype) { + case CPU_VR4111: + case CPU_VR4121: + vr41xx_icu1_base = VR4111_SYSINT1REG; + vr41xx_icu2_base = VR4111_SYSINT2REG; + break; + case CPU_VR4122: + case CPU_VR4131: + vr41xx_icu1_base = VR4122_SYSINT1REG; + vr41xx_icu2_base = VR4122_SYSINT2REG; + break; + default: + panic("Unexpected CPU of NEC VR4100 series"); + break; + } + + write_icu1(0, MSYSINT1REG); + write_icu1(0, MGIUINTLREG); + + write_icu2(0, MSYSINT2REG); + write_icu2(0, MGIUINTHREG); + + for (i = SYSINT1_IRQ_BASE; i <= GIU_IRQ_LAST; i++) { + if (i >= SYSINT1_IRQ_BASE && i <= SYSINT1_IRQ_LAST) + irq_desc[i].handler = &sysint1_irq_type; + else if (i >= SYSINT2_IRQ_BASE && i <= SYSINT2_IRQ_LAST) + irq_desc[i].handler = &sysint2_irq_type; + else if (i >= GIU_IRQ_BASE && i <= GIU_IRQ_LAST) + irq_desc[i].handler = &giuint_irq_type; + } + + setup_irq(ICU_CASCADE_IRQ, &icu_cascade); +} + +void __init init_IRQ(void) +{ + memset(irq_desc, 0, sizeof(irq_desc)); + + init_generic_irq(); + mips_cpu_irq_init(MIPS_CPU_IRQ_BASE); + vr41xx_icu_init(); + + vr41xx_giuint_init(); + + set_except_vector(0, vr41xx_handle_interrupt); + +#ifdef CONFIG_KGDB + printk("Setting debug traps - please connect the remote debugger.\n"); + set_debug_traps(); + breakpoint(); +#endif +} + +/*=======================================================================*/ + +static inline void giuint_irqdispatch(u16 pendl, u16 pendh, struct pt_regs *regs) +{ + int i; + + if (pendl) { + for (i = 0; i < 16; i++) { + if (pendl & (0x0001 << i)) { + giuint_do_IRQ(i, regs); + return; + } + } + } + else if (pendh) { + for (i = 0; i < 16; i++) { + if (pendh & (0x0001 << i)) { + giuint_do_IRQ(i + 16, regs); + return; + } + } + } +} + +asmlinkage void icu_irqdispatch(struct pt_regs *regs) +{ + u16 pend1, pend2, pendl, pendh; + u16 mask1, mask2, maskl, maskh; + int i; + + pend1 = read_icu1(SYSINT1REG); + mask1 = read_icu1(MSYSINT1REG); + + pend2 = read_icu2(SYSINT2REG); + mask2 = read_icu2(MSYSINT2REG); + + pendl = read_icu1(GIUINTLREG); + maskl = read_icu1(MGIUINTLREG); + + pendh = read_icu2(GIUINTHREG); + maskh = read_icu2(MGIUINTHREG); + + pend1 &= mask1; + pend2 &= mask2; + pendl &= maskl; + pendh &= maskh; + + if (pend1) { + if ((pend1 & 0x01ff) == 0x0100) { + giuint_irqdispatch(pendl, pendh, regs); + } + else { + for (i = 0; i < 16; i++) { + if (pend1 & (0x0001 << i)) { + do_IRQ(SYSINT1_IRQ_BASE + i, regs); + break; + } + } + } + return; + } + else if (pend2) { + for (i = 0; i < 16; i++) { + if (pend2 & (0x0001 << i)) { + do_IRQ(SYSINT2_IRQ_BASE + i, regs); + break; + } + } + } +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/common/int-handler.S 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,114 @@ +/* + * FILE NAME + * arch/mips/vr41xx/common/int-handler.S + * + * BRIEF MODULE DESCRIPTION + * Interrupt dispatcher for the NEC VR4100 series. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Changes: + * MontaVista Software Inc. or + * - New creation, NEC VR4100 series are supported. + */ +#include +#include +#include +#include + + .text + .set noreorder + + .align 5 + NESTED(vr41xx_handle_interrupt, PT_SIZE, ra) + .set noat + SAVE_ALL + CLI + .set at + .set noreorder + + /* + * Get the pending interrupts + */ + mfc0 t0, CP0_CAUSE + mfc0 t1, CP0_STATUS + andi t0, 0xff00 + and t0, t0, t1 + + andi t1, t0, CAUSEF_IP7 # timer interrupt + beqz t1, 1f + li a0, 7 + jal ll_timer_interrupt + move a1, sp + j ret_from_irq + +1: + andi t1, t0, 0x7800 # check for IP3-6 + beqz t1, 2f + + andi t1, t0, CAUSEF_IP3 # check for IP3 + bnez t1, handle_it + li a0, 3 + + andi t1, t0, CAUSEF_IP4 # check for IP4 + bnez t1, handle_it + li a0, 4 + + andi t1, t0, CAUSEF_IP5 # check for IP5 + bnez t1, handle_it + li a0, 5 + + andi t1, t0, CAUSEF_IP6 # check for IP6 + bnez t1, handle_it + li a0, 6 + +2: + andi t1, t0, CAUSEF_IP2 # check for IP2 + beqz t1, 3f + move a0, sp + jal icu_irqdispatch + nop + j ret_from_irq + nop + +3: + andi t1, t0, CAUSEF_IP0 # check for IP0 + bnez t1, handle_it + li a0, 0 + + andi t1, t0, CAUSEF_IP1 # check for IP1 + bnez t1, handle_it + li a0, 1 + + j spurious_interrupt + nop + +handle_it: + jal do_IRQ + move a1, sp + j ret_from_irq + END(vr41xx_handle_interrupt) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/common/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,10 @@ +# +# Makefile for common code of the NEC VR4100 series. +# + +obj-y += bcu.o cmu.o giu.o icu.o int-handler.o reset.o +obj-$(CONFIG_SERIAL_8250) += serial.o +obj-$(CONFIG_VR41XX_TIME_C) += time.o +obj-$(CONFIG_VRC4173) += vrc4173.o + +EXTRA_AFLAGS := $(CFLAGS) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/common/reset.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,37 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 1997, 2001 Ralf Baechle + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + */ +#include +#include +#include +#include +#include +#include +#include + +void vr41xx_restart(char *command) +{ + change_c0_status((ST0_BEV | ST0_ERL), (ST0_BEV | ST0_ERL)); + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + flush_cache_all(); + write_c0_wired(0); + __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); +} + +void vr41xx_halt(void) +{ + printk(KERN_NOTICE "\n** You can safely turn off the power\n"); + while (1); +} + +void vr41xx_power_off(void) +{ + vr41xx_halt(); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/common/serial.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,177 @@ +/* + * FILE NAME + * arch/mips/vr41xx/common/serial.c + * + * BRIEF MODULE DESCRIPTION + * Serial Interface Unit routines for NEC VR4100 series. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Changes: + * MontaVista Software Inc. or + * - Added support for NEC VR4111 and VR4121. + * + * MontaVista Software Inc. or + * - New creation, NEC VR4122 and VR4131 are supported. + */ +#include +#include +#include + +#include +#include +#include +#include + +/* VR4111 and VR4121 SIU Registers */ +#define VR4111_SIURB KSEG1ADDR(0x0c000000) +#define VR4111_SIUIRSEL KSEG1ADDR(0x0c000008) + +/* VR4122 and VR4131 SIU Registers */ +#define VR4122_SIURB KSEG1ADDR(0x0f000800) +#define VR4122_SIUIRSEL KSEG1ADDR(0x0f000808) + + #define USE_RS232C 0x00 + #define USE_IRDA 0x01 + #define SIU_USES_IRDA 0x00 + #define FIR_USES_IRDA 0x02 + #define IRDA_MODULE_SHARP 0x00 + #define IRDA_MODULE_TEMIC 0x04 + #define IRDA_MODULE_HP 0x08 + #define TMICTX 0x10 + #define TMICMODE 0x20 + +#define SIU_BASE_BAUD 1152000 +#define SIU_CLOCK 0x0102 + +/* VR4122 and VR4131 DSIU Registers */ +#define DSIURB KSEG1ADDR(0x0f000820) + +#define MDSIUINTREG KSEG1ADDR(0x0f000096) + #define INTDSIU 0x0800 + +#define DSIU_BASE_BAUD 1152000 +#define DSIU_CLOCK 0x0802 + +int vr41xx_serial_ports = 0; + +void vr41xx_siu_ifselect(int interface, int module) +{ + u16 val = USE_RS232C; /* Select RS-232C */ + + /* Select IrDA */ + if (interface == SIU_IRDA) { + switch (module) { + case IRDA_SHARP: + val = IRDA_MODULE_SHARP; + break; + case IRDA_TEMIC: + val = IRDA_MODULE_TEMIC; + break; + case IRDA_HP: + val = IRDA_MODULE_HP; + break; + } + val |= USE_IRDA | SIU_USES_IRDA; + } + + switch (current_cpu_data.cputype) { + case CPU_VR4111: + case CPU_VR4121: + writew(val, VR4111_SIUIRSEL); + break; + case CPU_VR4122: + case CPU_VR4131: + writew(val, VR4122_SIUIRSEL); + break; + default: + printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); + break; + } +} + +void __init vr41xx_siu_init(int interface, int module) +{ + struct serial_struct s; + + vr41xx_siu_ifselect(interface, module); + + memset(&s, 0, sizeof(s)); + + s.line = vr41xx_serial_ports; + s.baud_base = SIU_BASE_BAUD; + s.irq = SIU_IRQ; + s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; + switch (current_cpu_data.cputype) { + case CPU_VR4111: + case CPU_VR4121: + s.iomem_base = (unsigned char *)VR4111_SIURB; + break; + case CPU_VR4122: + case CPU_VR4131: + s.iomem_base = (unsigned char *)VR4122_SIURB; + break; + default: + panic("Unexpected CPU of NEC VR4100 series"); + break; + } + s.iomem_reg_shift = 0; + s.io_type = SERIAL_IO_MEM; + if (early_serial_setup(&s) != 0) + printk(KERN_ERR "SIU setup failed!\n"); + + vr41xx_clock_supply(SIU_CLOCK); + + vr41xx_serial_ports++; +} + +void __init vr41xx_dsiu_init(void) +{ + struct serial_struct s; + + if (current_cpu_data.cputype != CPU_VR4122 && + current_cpu_data.cputype != CPU_VR4131) + return; + + memset(&s, 0, sizeof(s)); + + s.line = vr41xx_serial_ports; + s.baud_base = DSIU_BASE_BAUD; + s.irq = DSIU_IRQ; + s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; + s.iomem_base = (unsigned char *)DSIURB; + s.iomem_reg_shift = 0; + s.io_type = SERIAL_IO_MEM; + if (early_serial_setup(&s) != 0) + printk(KERN_ERR "DSIU setup failed!\n"); + + vr41xx_clock_supply(DSIU_CLOCK); + + writew(INTDSIU, MDSIUINTREG); + + vr41xx_serial_ports++; +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/common/time.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,93 @@ +/* + * FILE NAME + * arch/mips/vr41xx/common/time.c + * + * BRIEF MODULE DESCRIPTION + * Timer routines for the NEC VR4100 series. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2001,2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Changes: + * MontaVista Software Inc. or + * - Added support for NEC VR4100 series RTC Unit. + * + * MontaVista Software Inc. or + * - New creation, NEC VR4100 series are supported. + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define VR4111_ETIMELREG KSEG1ADDR(0x0b0000c0) +#define VR4122_ETIMELREG KSEG1ADDR(0x0f000100) + +u32 vr41xx_rtc_base = 0; + +#ifdef CONFIG_VR41XX_RTC +extern unsigned long vr41xx_rtc_get_time(void); +extern int vr41xx_rtc_set_time(unsigned long sec); +#endif + +void vr41xx_time_init(void) +{ + switch (current_cpu_data.cputype) { + case CPU_VR4111: + case CPU_VR4121: + vr41xx_rtc_base = VR4111_ETIMELREG; + break; + case CPU_VR4122: + case CPU_VR4131: + vr41xx_rtc_base = VR4122_ETIMELREG; + break; + default: + panic("Unexpected CPU of NEC VR4100 series"); + break; + } + +#ifdef CONFIG_VR41XX_RTC + rtc_get_time = vr41xx_rtc_get_time; + rtc_set_time = vr41xx_rtc_set_time; +#endif +} + +void vr41xx_timer_setup(struct irqaction *irq) +{ + u32 count; + + setup_irq(MIPS_COUNTER_IRQ, irq); + + count = read_c0_count(); + write_c0_compare(count + (mips_counter_frequency / HZ)); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/common/vrc4173.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,279 @@ +/* + * FILE NAME + * drivers/char/vrc4173.c + * + * BRIEF MODULE DESCRIPTION + * NEC VRC4173 driver for NEC VR4122/VR4131. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2001,2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +MODULE_DESCRIPTION("NEC VRC4173 driver for NEC VR4122/4131"); +MODULE_AUTHOR("Yoichi Yuasa "); +MODULE_LICENSE("GPL"); + +#define VRC4173_CMUCLKMSK 0x040 +#define VRC4173_CMUSRST 0x042 + +#define VRC4173_SELECTREG 0x09e + +#define VRC4173_SYSINT1REG 0x060 +#define VRC4173_MSYSINT1REG 0x06c + +static struct pci_device_id vrc4173_table[] __devinitdata = { + {PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_VRC4173, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, + {0, } +}; + +unsigned long vrc4173_io_offset = 0; + +EXPORT_SYMBOL(vrc4173_io_offset); + +static u16 vrc4173_cmuclkmsk; +static int vrc4173_initialized; + +void vrc4173_clock_supply(u16 mask) +{ + if (vrc4173_initialized) { + vrc4173_cmuclkmsk |= mask; + vrc4173_outw(vrc4173_cmuclkmsk, VRC4173_CMUCLKMSK); + } +} + +void vrc4173_clock_mask(u16 mask) +{ + if (vrc4173_initialized) { + vrc4173_cmuclkmsk &= ~mask; + vrc4173_outw(vrc4173_cmuclkmsk, VRC4173_CMUCLKMSK); + } +} + +static inline void vrc4173_cmu_init(void) +{ + vrc4173_cmuclkmsk = vrc4173_inw(VRC4173_CMUCLKMSK); +} + +EXPORT_SYMBOL(vrc4173_clock_supply); +EXPORT_SYMBOL(vrc4173_clock_mask); + +void vrc4173_select_function(int func) +{ + u16 val; + + if (vrc4173_initialized) { + val = vrc4173_inw(VRC4173_SELECTREG); + switch(func) { + case PS2CH1_SELECT: + val |= 0x0004; + break; + case PS2CH2_SELECT: + val |= 0x0002; + break; + case TOUCHPANEL_SELECT: + val &= 0x0007; + break; + case KIU8_SELECT: + val &= 0x000e; + break; + case KIU10_SELECT: + val &= 0x000c; + break; + case KIU12_SELECT: + val &= 0x0008; + break; + case GPIO_SELECT: + val |= 0x0008; + break; + } + vrc4173_outw(val, VRC4173_SELECTREG); + } +} + +EXPORT_SYMBOL(vrc4173_select_function); + +static void enable_vrc4173_irq(unsigned int irq) +{ + u16 val; + + val = vrc4173_inw(VRC4173_MSYSINT1REG); + val |= (u16)1 << (irq - VRC4173_IRQ_BASE); + vrc4173_outw(val, VRC4173_MSYSINT1REG); +} + +static void disable_vrc4173_irq(unsigned int irq) +{ + u16 val; + + val = vrc4173_inw(VRC4173_MSYSINT1REG); + val &= ~((u16)1 << (irq - VRC4173_IRQ_BASE)); + vrc4173_outw(val, VRC4173_MSYSINT1REG); +} + +static unsigned int startup_vrc4173_irq(unsigned int irq) +{ + enable_vrc4173_irq(irq); + return 0; /* never anything pending */ +} + +#define shutdown_vrc4173_irq disable_vrc4173_irq +#define ack_vrc4173_irq disable_vrc4173_irq + +static void end_vrc4173_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + enable_vrc4173_irq(irq); +} + +static struct hw_interrupt_type vrc4173_irq_type = { + "VRC4173", + startup_vrc4173_irq, + shutdown_vrc4173_irq, + enable_vrc4173_irq, + disable_vrc4173_irq, + ack_vrc4173_irq, + end_vrc4173_irq, + NULL +}; + +static int vrc4173_get_irq_number(int irq) +{ + u16 status, mask; + int i; + + status = vrc4173_inw(VRC4173_SYSINT1REG); + mask = vrc4173_inw(VRC4173_MSYSINT1REG); + + status &= mask; + if (status) { + for (i = 0; i < 16; i++) + if (status & (0x0001 << i)) + return VRC4173_IRQ_BASE + i; + } + + return -EINVAL; +} + +static inline void vrc4173_icu_init(int cascade_irq) +{ + int i; + + if (cascade_irq < GIU_IRQ(0) || cascade_irq > GIU_IRQ(15)) + return; + + vrc4173_outw(0, VRC4173_MSYSINT1REG); + + vr41xx_set_irq_trigger(cascade_irq - GIU_IRQ(0), TRIGGER_LEVEL, SIGNAL_THROUGH); + vr41xx_set_irq_level(cascade_irq - GIU_IRQ(0), LEVEL_LOW); + + for (i = VRC4173_IRQ_BASE; i <= VRC4173_IRQ_LAST; i++) + irq_desc[i].handler = &vrc4173_irq_type; +} + +static int __devinit vrc4173_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + unsigned long start, flags; + int err; + + if ((err = pci_enable_device(pdev)) < 0) { + printk(KERN_ERR "vrc4173: failed to enable device -- err=%d\n", err); + return err; + } + + pci_set_master(pdev); + + start = pci_resource_start(pdev, 0); + if (!start) { + printk(KERN_ERR "vrc4173:No PCI I/O resources, aborting\n"); + return -ENODEV; + } + + if (!start || (((flags = pci_resource_flags(pdev, 0)) & IORESOURCE_IO) == 0)) { + printk(KERN_ERR "vrc4173: No PCI I/O resources, aborting\n"); + return -ENODEV; + } + + if ((err = pci_request_regions(pdev, "NEC VRC4173")) < 0) { + printk(KERN_ERR "vrc4173: PCI resources are busy, aborting\n"); + return err; + } + + set_vrc4173_io_offset(start); + + vrc4173_cmu_init(); + + vrc4173_icu_init(pdev->irq); + + if ((err = vr41xx_cascade_irq(pdev->irq, vrc4173_get_irq_number)) < 0) { + printk(KERN_ERR + "vrc4173: IRQ resource %d is busy, aborting\n", pdev->irq); + return err; + } + + printk(KERN_INFO + "NEC VRC4173 at 0x%#08lx, IRQ is cascaded to %d\n", start, pdev->irq); + + return 0; +} + +static struct pci_driver vrc4173_driver = { + name: "NEC VRC4173", + probe: vrc4173_probe, + remove: NULL, + id_table: vrc4173_table, +}; + +static int __devinit vrc4173_init(void) +{ + int err; + + if ((err = pci_module_init(&vrc4173_driver)) < 0) + return err; + + vrc4173_initialized = 1; + + return 0; +} + +static void __devexit vrc4173_exit(void) +{ + vrc4173_initialized = 0; + + pci_unregister_driver(&vrc4173_driver); +} + +module_init(vrc4173_init); +module_exit(vrc4173_exit); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/ibm-workpad/ide-workpad.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,98 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * IDE routines for typical pc-like standard configurations for the IBM WorkPad z50. + * + * Copyright (C) 1998, 1999, 2001 by Ralf Baechle + */ +/* + * Changes: + * Yoichi Yuasa Sun, 24 Feb 2002 + * - Added IBM WorkPad z50 support. + */ +#include +#include +#include +#include +#include +#include + +static int workpad_ide_default_irq(ide_ioreg_t base) +{ + return 49; +} + +static ide_ioreg_t workpad_ide_default_io_base(int index) +{ + switch (index) { + case 0: return 0x1f0; + case 1: return 0x170; + case 2: return 0x1e8; + case 3: return 0x168; + case 4: return 0x1e0; + case 5: return 0x160; + } + return 0; +} + +static void workpad_ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port, + ide_ioreg_t ctrl_port, int *irq) +{ + ide_ioreg_t reg = data_port; + int i; + + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { + hw->io_ports[i] = reg; + reg += 1; + } + if (ctrl_port) { + hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; + } else { + hw->io_ports[IDE_CONTROL_OFFSET] = hw->io_ports[IDE_DATA_OFFSET] + 0x206; + } + if (irq != NULL) + *irq = 0; + hw->io_ports[IDE_IRQ_OFFSET] = 0; +} + +static int workpad_ide_request_irq(unsigned int irq, + void (*handler)(int,void *, struct pt_regs *), + unsigned long flags, const char *device, + void *dev_id) +{ + return request_irq(irq, handler, SA_SHIRQ, device, dev_id); +} + +static void workpad_ide_free_irq(unsigned int irq, void *dev_id) +{ + free_irq(irq, dev_id); +} + +static int workpad_ide_check_region(ide_ioreg_t from, unsigned int extent) +{ + return check_region(from, extent); +} + +static void workpad_ide_request_region(ide_ioreg_t from, unsigned int extent, + const char *name) +{ + request_region(from, extent, name); +} + +static void workpad_ide_release_region(ide_ioreg_t from, unsigned int extent) +{ + release_region(from, extent); +} + +struct ide_ops workpad_ide_ops = { + &workpad_ide_default_irq, + &workpad_ide_default_io_base, + &workpad_ide_init_hwif_ports, + &workpad_ide_request_irq, + &workpad_ide_free_irq, + &workpad_ide_check_region, + &workpad_ide_request_region, + &workpad_ide_release_region +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/ibm-workpad/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,49 @@ +/* + * FILE NAME + * arch/mips/vr41xx/ibm-workpad/init.c + * + * BRIEF MODULE DESCRIPTION + * Initialisation code for the IBM WorkPad z50. + * + * Copyright 2002 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include + +#include + +char arcs_cmdline[CL_SIZE]; + +const char *get_system_type(void) +{ + return "IBM WorkPad z50"; +} + +void __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec) +{ + int i; + + /* + * collect args and prepare cmd_line + */ + for (i = 1; i < argc; i++) { + strcat(arcs_cmdline, argv[i]); + if (i < (argc - 1)) + strcat(arcs_cmdline, " "); + } + + mips_machgroup = MACH_GROUP_NEC_VR41XX; + mips_machtype = MACH_IBM_WORKPAD; +} + +void __init prom_free_prom_memory (void) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/ibm-workpad/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,6 @@ +# +# Makefile for the IBM WorkPad z50 specific parts of the kernel +# + +obj-y += init.o setup.o +obj-$(CONFIG_IDE) += ide-workpad.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/ibm-workpad/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,74 @@ +/* + * FILE NAME + * arch/mips/vr41xx/workpad/setup.c + * + * BRIEF MODULE DESCRIPTION + * Setup for the IBM WorkPad z50. + * + * Copyright 2002 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_BLK_DEV_INITRD +extern unsigned long initrd_start, initrd_end; +extern void * __rd_start, * __rd_end; +#endif + +#ifdef CONFIG_BLK_DEV_IDE +extern struct ide_ops workpad_ide_ops; +#endif + +void __init ibm_workpad_setup(void) +{ + set_io_port_base(IO_PORT_BASE); + ioport_resource.start = IO_PORT_RESOURCE_START; + ioport_resource.end = IO_PORT_RESOURCE_END; + iomem_resource.start = IO_MEM_RESOURCE_START; + iomem_resource.end = IO_MEM_RESOURCE_END; + +#ifdef CONFIG_BLK_DEV_INITRD + ROOT_DEV = Root_RAM0; + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; +#endif + + _machine_restart = vr41xx_restart; + _machine_halt = vr41xx_halt; + _machine_power_off = vr41xx_power_off; + + board_time_init = vr41xx_time_init; + board_timer_setup = vr41xx_timer_setup; + +#ifdef CONFIG_FB + conswitchp = &dummy_con; +#endif + +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &workpad_ide_ops; +#endif + + vr41xx_bcu_init(); + + vr41xx_cmu_init(0); + +#ifdef CONFIG_SERIAL_8250 + vr41xx_siu_init(SIU_RS232C, 0); +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/nec-eagle/ide-eagle.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,96 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * IDE routines for typical pc-like standard configurations + * for the NEC Eagle/Hawk board. + * + * Copyright (C) 1998, 1999, 2001 by Ralf Baechle + */ +/* + * Changes: + * MontaVista Software Inc. or + * Fri, 5 Apr 2002 + * - Added support for NEC Hawk. + * + * MontaVista Software Inc. or + * Fri, 1 Mar 2002 + * - Added support for NEC Eagle. + */ +#include +#include +#include +#include +#include +#include + +static int eagle_ide_default_irq(ide_ioreg_t base) +{ + return 0; +} + +static ide_ioreg_t eagle_ide_default_io_base(int index) +{ + return 0; +} + +static void eagle_ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port, + ide_ioreg_t ctrl_port, int *irq) +{ + ide_ioreg_t reg = data_port; + int i; + + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { + hw->io_ports[i] = reg; + reg += 1; + } + if (ctrl_port) { + hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; + } else { + hw->io_ports[IDE_CONTROL_OFFSET] = hw->io_ports[IDE_DATA_OFFSET] + 0x206; + } + if (irq != NULL) + *irq = 0; + hw->io_ports[IDE_IRQ_OFFSET] = 0; +} + +static int eagle_ide_request_irq(unsigned int irq, + void (*handler)(int,void *, struct pt_regs *), + unsigned long flags, const char *device, + void *dev_id) +{ + return request_irq(irq, handler, SA_SHIRQ, device, dev_id); +} + +static void eagle_ide_free_irq(unsigned int irq, void *dev_id) +{ + free_irq(irq, dev_id); +} + +static int eagle_ide_check_region(ide_ioreg_t from, unsigned int extent) +{ + return check_region(from, extent); +} + +static void eagle_ide_request_region(ide_ioreg_t from, unsigned int extent, + const char *name) +{ + request_region(from, extent, name); +} + +static void eagle_ide_release_region(ide_ioreg_t from, unsigned int extent) +{ + release_region(from, extent); +} + +struct ide_ops eagle_ide_ops = { + &eagle_ide_default_irq, + &eagle_ide_default_io_base, + &eagle_ide_init_hwif_ports, + &eagle_ide_request_irq, + &eagle_ide_free_irq, + &eagle_ide_check_region, + &eagle_ide_request_region, + &eagle_ide_release_region +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/nec-eagle/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,74 @@ +/* + * FILE NAME + * arch/mips/vr41xx/nec-eagle/init.c + * + * BRIEF MODULE DESCRIPTION + * Initialisation code for the NEC Eagle/Hawk board. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2001,2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Changes: + * MontaVista Software Inc. or + * - Added support for NEC Hawk. + * + * MontaVista Software Inc. or + * - New creation, NEC Eagle is supported. + */ +#include +#include +#include +#include + +#include + +char arcs_cmdline[CL_SIZE]; + +const char *get_system_type(void) +{ + return "NEC Eagle/Hawk"; +} + +void __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec) +{ + int i; + + /* + * collect args and prepare cmd_line + */ + for (i = 1; i < argc; i++) { + strcat(arcs_cmdline, argv[i]); + if (i < (argc - 1)) + strcat(arcs_cmdline, " "); + } + + mips_machgroup = MACH_GROUP_NEC_VR41XX; + mips_machtype = MACH_NEC_EAGLE; +} + +void __init prom_free_prom_memory (void) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/nec-eagle/irq.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,183 @@ +/* + * FILE NAME + * arch/mips/vr41xx/nec-eagle/irq.c + * + * BRIEF MODULE DESCRIPTION + * Interrupt routines for the NEC Eagle/Hawk board. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Changes: + * MontaVista Software Inc. or + * - Added support for NEC Hawk. + * + * MontaVista Software Inc. or + * - New creation, NEC Eagle is supported. + */ +#include +#include + +#include +#include + +static void enable_pciint_irq(unsigned int irq) +{ + u8 val; + + val = readb(NEC_EAGLE_PCIINTMSKREG); + val |= (u8)1 << (irq - PCIINT_IRQ_BASE); + writeb(val, NEC_EAGLE_PCIINTMSKREG); +} + +static void disable_pciint_irq(unsigned int irq) +{ + u8 val; + + val = readb(NEC_EAGLE_PCIINTMSKREG); + val &= ~((u8)1 << (irq - PCIINT_IRQ_BASE)); + writeb(val, NEC_EAGLE_PCIINTMSKREG); +} + +static unsigned int startup_pciint_irq(unsigned int irq) +{ + enable_pciint_irq(irq); + return 0; /* never anything pending */ +} + +#define shutdown_pciint_irq disable_pciint_irq +#define ack_pciint_irq disable_pciint_irq + +static void end_pciint_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + enable_pciint_irq(irq); +} + +static struct hw_interrupt_type pciint_irq_type = { + "PCIINT", + startup_pciint_irq, + shutdown_pciint_irq, + enable_pciint_irq, + disable_pciint_irq, + ack_pciint_irq, + end_pciint_irq, + NULL +}; + +static void enable_sdbint_irq(unsigned int irq) +{ + u8 val; + + val = readb(NEC_EAGLE_SDBINTMSK); + val |= (u8)1 << (irq - SDBINT_IRQ_BASE); + writeb(val, NEC_EAGLE_SDBINTMSK); +} + +static void disable_sdbint_irq(unsigned int irq) +{ + u8 val; + + val = readb(NEC_EAGLE_SDBINTMSK); + val &= ~((u8)1 << (irq - SDBINT_IRQ_BASE)); + writeb(val, NEC_EAGLE_SDBINTMSK); +} + +static unsigned int startup_sdbint_irq(unsigned int irq) +{ + enable_sdbint_irq(irq); + return 0; /* never anything pending */ +} + +#define shutdown_sdbint_irq disable_sdbint_irq +#define ack_sdbint_irq disable_sdbint_irq + +static void end_sdbint_irq(unsigned int irq) +{ + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + enable_sdbint_irq(irq); +} + +static struct hw_interrupt_type sdbint_irq_type = { + "SDBINT", + startup_sdbint_irq, + shutdown_sdbint_irq, + enable_sdbint_irq, + disable_sdbint_irq, + ack_sdbint_irq, + end_sdbint_irq, + NULL +}; + +static int eagle_get_irq_number(int irq) +{ + u8 sdbint, pciint; + int i; + + sdbint = readb(NEC_EAGLE_SDBINT); + sdbint &= (NEC_EAGLE_SDBINT_DEG | NEC_EAGLE_SDBINT_ENUM | + NEC_EAGLE_SDBINT_SIO1INT | NEC_EAGLE_SDBINT_SIO2INT | + NEC_EAGLE_SDBINT_PARINT); + pciint = readb(NEC_EAGLE_PCIINTREG); + pciint &= (NEC_EAGLE_PCIINT_CP_INTA | NEC_EAGLE_PCIINT_CP_INTB | + NEC_EAGLE_PCIINT_CP_INTC | NEC_EAGLE_PCIINT_CP_INTD | + NEC_EAGLE_PCIINT_LANINT); + + for (i = 1; i < 6; i++) + if (sdbint & (0x01 << i)) + return SDBINT_IRQ_BASE + i; + + for (i = 0; i < 5; i++) + if (pciint & (0x01 << i)) + return PCIINT_IRQ_BASE + i; + + return -EINVAL; +} + +void __init eagle_irq_init(void) +{ + int i; + + writeb(0, NEC_EAGLE_SDBINTMSK); + writeb(0, NEC_EAGLE_PCIINTMSKREG); + + vr41xx_set_irq_trigger(PCISLOT_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH); + vr41xx_set_irq_level(PCISLOT_PIN, LEVEL_HIGH); + + vr41xx_set_irq_trigger(FPGA_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH); + vr41xx_set_irq_level(FPGA_PIN, LEVEL_HIGH); + + vr41xx_set_irq_trigger(DCD_PIN, TRIGGER_EDGE, SIGNAL_HOLD); + vr41xx_set_irq_level(DCD_PIN, LEVEL_LOW); + + for (i = SDBINT_IRQ_BASE; i <= SDBINT_IRQ_LAST; i++) + irq_desc[i].handler = &sdbint_irq_type; + + for (i = PCIINT_IRQ_BASE; i <= PCIINT_IRQ_LAST; i++) + irq_desc[i].handler = &pciint_irq_type; + + vr41xx_cascade_irq(FPGA_CASCADE_IRQ, eagle_get_irq_number); +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/nec-eagle/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,11 @@ +# +# Makefile for the NEC Eagle/Hawk specific parts of the kernel +# +# Author: Yoichi Yuasa +# yyuasa@mvista.com or source@mvista.com +# +# Copyright 2001,2002 MontaVista Software Inc. +# + +obj-y += init.o irq.o setup.o +obj-$(CONFIG_IDE) += ide-eagle.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/nec-eagle/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,162 @@ +/* + * FILE NAME + * arch/mips/vr41xx/nec-eagle/setup.c + * + * BRIEF MODULE DESCRIPTION + * Setup for the NEC Eagle/Hawk board. + * + * Author: Yoichi Yuasa + * yyuasa@mvista.com or source@mvista.com + * + * Copyright 2001,2002 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR + * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +/* + * Changes: + * MontaVista Software Inc. or + * - Moved mips_pci_channels[] from arch/mips/vr41xx/vr4122/eagle/setup.c. + * - Added support for NEC Hawk. + * + * MontaVista Software Inc. or + * - New creation, NEC Eagle is supported. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_BLK_DEV_INITRD +extern unsigned long initrd_start, initrd_end; +extern void * __rd_start, * __rd_end; +#endif + +#ifdef CONFIG_BLK_DEV_IDE +extern struct ide_ops eagle_ide_ops; +#endif + +extern void eagle_irq_init(void); + +#ifdef CONFIG_PCI + +extern void vrc4173_preinit(void); + +static struct resource vr41xx_pci_io_resource = { + "PCI I/O space", + VR41XX_PCI_IO_START, + VR41XX_PCI_IO_END, + IORESOURCE_IO +}; + +static struct resource vr41xx_pci_mem_resource = { + "PCI memory space", + VR41XX_PCI_MEM_START, + VR41XX_PCI_MEM_END, + IORESOURCE_MEM +}; + +extern struct pci_ops vr41xx_pci_ops; + +struct pci_channel mips_pci_channels[] = { + {&vr41xx_pci_ops, &vr41xx_pci_io_resource, &vr41xx_pci_mem_resource, 0, 256}, + {NULL, NULL, NULL, 0, 0} +}; + +struct vr41xx_pci_address_space vr41xx_pci_mem1 = { + VR41XX_PCI_MEM1_BASE, + VR41XX_PCI_MEM1_MASK, + IO_MEM1_RESOURCE_START +}; + +struct vr41xx_pci_address_space vr41xx_pci_mem2 = { + VR41XX_PCI_MEM2_BASE, + VR41XX_PCI_MEM2_MASK, + IO_MEM2_RESOURCE_START +}; + +struct vr41xx_pci_address_space vr41xx_pci_io = { + VR41XX_PCI_IO_BASE, + VR41XX_PCI_IO_MASK, + IO_PORT_RESOURCE_START +}; + +static struct vr41xx_pci_address_map pci_address_map = { + &vr41xx_pci_mem1, + &vr41xx_pci_mem2, + &vr41xx_pci_io +}; +#endif + +void __init nec_eagle_setup(void) +{ + set_io_port_base(IO_PORT_BASE); + ioport_resource.start = IO_PORT_RESOURCE_START; + ioport_resource.end = IO_PORT_RESOURCE_END; + iomem_resource.start = IO_MEM1_RESOURCE_START; + iomem_resource.end = IO_MEM2_RESOURCE_END; + +#ifdef CONFIG_BLK_DEV_INITRD + ROOT_DEV = Root_RAM0; + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; +#endif + + _machine_restart = vr41xx_restart; + _machine_halt = vr41xx_halt; + _machine_power_off = vr41xx_power_off; + + board_time_init = vr41xx_time_init; + board_timer_setup = vr41xx_timer_setup; + + board_irq_init = eagle_irq_init; + +#ifdef CONFIG_FB + conswitchp = &dummy_con; +#endif + +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &eagle_ide_ops; +#endif + + vr41xx_bcu_init(); + + vr41xx_cmu_init(0); + +#ifdef CONFIG_SERIAL_8250 + vr41xx_dsiu_init(); + vr41xx_siu_init(SIU_RS232C, 0); +#endif + +#ifdef CONFIG_PCI + vr41xx_pciu_init(&pci_address_map); + + vrc4173_preinit(); +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/tanbac-tb0226/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,64 @@ +/* + * FILE NAME + * arch/mips/vr41xx/tanbac-tb0226/init.c + * + * BRIEF MODULE DESCRIPTION + * Initialisation code for the TANBAC TB0226. + * + * Copyright 2002,2003 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include + +#include +#include +#include +#include + +char arcs_cmdline[CL_SIZE]; + +const char *get_system_type(void) +{ + return "TANBAC TB0226"; +} + +void __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec) +{ + u32 config; + int i; + + /* + * collect args and prepare cmd_line + */ + for (i = 1; i < argc; i++) { + strcat(arcs_cmdline, argv[i]); + if (i < (argc - 1)) + strcat(arcs_cmdline, " "); + } + + mips_machgroup = MACH_GROUP_NEC_VR41XX; + mips_machtype = MACH_TANBAC_TB0226; + + switch (current_cpu_data.processor_id) { + case PRID_VR4131_REV1_2: + config = read_c0_config(); + config &= ~0x00000030UL; + config |= 0x00410000UL; + write_c0_config(config); + break; + default: + break; + } +} + +void __init prom_free_prom_memory (void) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/tanbac-tb0226/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,5 @@ +# +# Makefile for the TANBAC TB0226 specific parts of the kernel +# + +obj-y += init.o setup.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/tanbac-tb0226/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,121 @@ +/* + * FILE NAME + * arch/mips/vr41xx/tanbac-tb0226/setup.c + * + * BRIEF MODULE DESCRIPTION + * Setup for the TANBAC TB0226. + * + * Copyright 2002,2003 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_BLK_DEV_INITRD +extern unsigned long initrd_start, initrd_end; +extern void * __rd_start, * __rd_end; +#endif + +#ifdef CONFIG_PCI +static struct resource vr41xx_pci_io_resource = { + .name = "PCI I/O space", + .start = VR41XX_PCI_IO_START, + .end = VR41XX_PCI_IO_END, + .flags = IORESOURCE_IO, +}; + +static struct resource vr41xx_pci_mem_resource = { + .name = "PCI memory space", + .start = VR41XX_PCI_MEM_START, + .end = VR41XX_PCI_MEM_END, + .flags = IORESOURCE_MEM, +}; + +extern struct pci_ops vr41xx_pci_ops; + +struct pci_channel mips_pci_channels[] = { + { .pci_ops = &vr41xx_pci_ops, + .io_resource = &vr41xx_pci_io_resource, + .mem_resource = &vr41xx_pci_mem_resource, + .first_devfn = 0, + .last_devfn = 256, }, + { .pci_ops = NULL, + .io_resource = NULL, + .mem_resource = NULL, + .first_devfn = 0, + .last_devfn = 0, }, +}; + +struct vr41xx_pci_address_space vr41xx_pci_mem1 = { + .internal_base = VR41XX_PCI_MEM1_BASE, + .address_mask = VR41XX_PCI_MEM1_MASK, + .pci_base = IO_MEM1_RESOURCE_START, +}; + +struct vr41xx_pci_address_space vr41xx_pci_mem2 = { + .internal_base = VR41XX_PCI_MEM2_BASE, + .address_mask = VR41XX_PCI_MEM2_MASK, + .pci_base = IO_MEM2_RESOURCE_START, +}; + +struct vr41xx_pci_address_space vr41xx_pci_io = { + .internal_base = VR41XX_PCI_IO_BASE, + .address_mask = VR41XX_PCI_IO_MASK, + .pci_base = IO_PORT_RESOURCE_START, +}; + +static struct vr41xx_pci_address_map pci_address_map = { + .mem1 = &vr41xx_pci_mem1, + .mem2 = &vr41xx_pci_mem2, + .io = &vr41xx_pci_io, +}; +#endif + +void __init tanbac_tb0226_setup(void) +{ + set_io_port_base(IO_PORT_BASE); + ioport_resource.start = IO_PORT_RESOURCE_START; + ioport_resource.end = IO_PORT_RESOURCE_END; + iomem_resource.start = IO_MEM1_RESOURCE_START; + iomem_resource.end = IO_MEM2_RESOURCE_END; + +#ifdef CONFIG_BLK_DEV_INITRD + ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; +#endif + + _machine_restart = vr41xx_restart; + _machine_halt = vr41xx_halt; + _machine_power_off = vr41xx_power_off; + + board_time_init = vr41xx_time_init; + board_timer_setup = vr41xx_timer_setup; + +#ifdef CONFIG_FB + conswitchp = &dummy_con; +#endif + + vr41xx_bcu_init(); + + vr41xx_cmu_init(0); + + vr41xx_siu_init(SIU_RS232C, 0); + +#ifdef CONFIG_PCI + vr41xx_pciu_init(&pci_address_map); +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/tanbac-tb0229/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,69 @@ +/* + * FILE NAME + * arch/mips/vr41xx/tanbac-tb0229/init.c + * + * BRIEF MODULE DESCRIPTION + * Initialisation code for the TANBAC TB0229(VR4131DIMM) + * + * Copyright 2002,2003 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * Modified for TANBAC TB0229: + * Copyright 2003 Megasolution Inc. + * matsu@megasolution.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +char arcs_cmdline[CL_SIZE]; + +const char *get_system_type(void) +{ + return "TANBAC TB0229"; +} + +void __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec) +{ + u32 config; + int i; + + /* + * collect args and prepare cmd_line + */ + for (i = 1; i < argc; i++) { + strcat(arcs_cmdline, argv[i]); + if (i < (argc - 1)) + strcat(arcs_cmdline, " "); + } + + mips_machgroup = MACH_GROUP_NEC_VR41XX; + mips_machtype = MACH_TANBAC_TB0229; + + switch (current_cpu_data.processor_id) { + case PRID_VR4131_REV1_2: + config = read_c0_config(); + config &= ~0x00000030UL; + config |= 0x00410000UL; + write_c0_config(config); + break; + default: + break; + } +} + +void __init prom_free_prom_memory (void) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/tanbac-tb0229/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,5 @@ +# +# Makefile for the TANBAC TB0229(VR4131DIMM) specific parts of the kernel +# + +obj-y := init.o reboot.o setup.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/tanbac-tb0229/reboot.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,30 @@ +/* + * FILE NAME + * arch/mips/vr41xx/tanbac-tb0229/reboot.c + * + * BRIEF MODULE DESCRIPTION + * Depending on TANBAC TB0229(VR4131DIMM) of reboot system call. + * + * Copyright 2003 Megasolution Inc. + * matsu@megasolution.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include + +#define tb0229_hard_reset() writew(0, TB0219_RESET_REGS) + +void tanbac_tb0229_restart(char *command) +{ +#ifdef CONFIG_TANBAC_TB0219 + local_irq_disable(); + tb0229_hard_reset(); + while (1); +#else + vr41xx_restart(command); +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/tanbac-tb0229/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,127 @@ +/* + * FILE NAME + * arch/mips/vr41xx/tanbac-tb0229/setup.c + * + * BRIEF MODULE DESCRIPTION + * Setup for the TANBAC TB0229 (VR4131DIMM) + * + * Copyright 2002,2003 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * Modified for TANBAC TB0229: + * Copyright 2003 Megasolution Inc. + * matsu@megasolution.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_BLK_DEV_INITRD +extern void * __rd_start, * __rd_end; +#endif + +#ifdef CONFIG_PCI +static struct resource vr41xx_pci_io_resource = { + .name = "PCI I/O space", + .start = VR41XX_PCI_IO_START, + .end = VR41XX_PCI_IO_END, + .flags = IORESOURCE_IO, +}; + +static struct resource vr41xx_pci_mem_resource = { + .name = "PCI memory space", + .start = VR41XX_PCI_MEM_START, + .end = VR41XX_PCI_MEM_END, + .flags = IORESOURCE_MEM, +}; + +extern struct pci_ops vr41xx_pci_ops; + +struct pci_channel mips_pci_channels[] = { + { .pci_ops = &vr41xx_pci_ops, + .io_resource = &vr41xx_pci_io_resource, + .mem_resource = &vr41xx_pci_mem_resource, + .first_devfn = 0, + .last_devfn = 256, }, + { .pci_ops = NULL, + .io_resource = NULL, + .mem_resource = NULL, + .first_devfn = 0, + .last_devfn = 0, } +}; + +struct vr41xx_pci_address_space vr41xx_pci_mem1 = { + .internal_base = VR41XX_PCI_MEM1_BASE, + .address_mask = VR41XX_PCI_MEM1_MASK, + .pci_base = IO_MEM1_RESOURCE_START, +}; + +struct vr41xx_pci_address_space vr41xx_pci_mem2 = { + .internal_base = VR41XX_PCI_MEM2_BASE, + .address_mask = VR41XX_PCI_MEM2_MASK, + .pci_base = IO_MEM2_RESOURCE_START, +}; + +struct vr41xx_pci_address_space vr41xx_pci_io = { + .internal_base = VR41XX_PCI_IO_BASE, + .address_mask = VR41XX_PCI_IO_MASK, + .pci_base = IO_PORT_RESOURCE_START +}; + +static struct vr41xx_pci_address_map pci_address_map = { + .mem1 = &vr41xx_pci_mem1, + .mem2 = &vr41xx_pci_mem2, + .io = &vr41xx_pci_io, +}; +#endif + +void __init tanbac_tb0229_setup(void) +{ + set_io_port_base(IO_PORT_BASE); + ioport_resource.start = IO_PORT_RESOURCE_START; + ioport_resource.end = IO_PORT_RESOURCE_END; + iomem_resource.start = IO_MEM1_RESOURCE_START; + iomem_resource.end = IO_MEM2_RESOURCE_END; + +#ifdef CONFIG_BLK_DEV_INITRD + ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; +#endif + + _machine_restart = tanbac_tb0229_restart; + _machine_halt = vr41xx_halt; + _machine_power_off = vr41xx_power_off; + + board_time_init = vr41xx_time_init; + board_timer_setup = vr41xx_timer_setup; + +#ifdef CONFIG_FB + conswitchp = &dummy_con; +#endif + + vr41xx_bcu_init(); + + vr41xx_cmu_init(0); + + vr41xx_siu_init(SIU_RS232C, 0); + vr41xx_dsiu_init(); + +#ifdef CONFIG_PCI + vr41xx_pciu_init(&pci_address_map); +#endif +} + --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/victor-mpc30x/ide-mpc30x.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,91 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * IDE routines for typical pc-like standard configurations + * for the ZAO Networks Capcella. + * + * Copyright (C) 1998, 1999, 2001 by Ralf Baechle + */ +/* + * Changes: + * Yoichi Yuasa Fri, 23 Aug 2002 + * - Added Victor MP-C303/304 support. + */ +#include +#include +#include +#include +#include +#include + +static int mpc30x_ide_default_irq(ide_ioreg_t base) +{ + return 0; +} + +static ide_ioreg_t mpc30x_ide_default_io_base(int index) +{ + return 0; +} + +static void mpc30x_ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port, + ide_ioreg_t ctrl_port, int *irq) +{ + ide_ioreg_t reg = data_port; + int i; + + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { + hw->io_ports[i] = reg; + reg += 1; + } + if (ctrl_port) { + hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; + } else { + hw->io_ports[IDE_CONTROL_OFFSET] = hw->io_ports[IDE_DATA_OFFSET] + 0x206; + } + if (irq != NULL) + *irq = 0; + hw->io_ports[IDE_IRQ_OFFSET] = 0; +} + +static int mpc30x_ide_request_irq(unsigned int irq, + void (*handler)(int,void *, struct pt_regs *), + unsigned long flags, const char *device, + void *dev_id) +{ + return request_irq(irq, handler, flags, device, dev_id); +} + +static void mpc30x_ide_free_irq(unsigned int irq, void *dev_id) +{ + free_irq(irq, dev_id); +} + +static int mpc30x_ide_check_region(ide_ioreg_t from, unsigned int extent) +{ + return check_region(from, extent); +} + +static void mpc30x_ide_request_region(ide_ioreg_t from, unsigned int extent, + const char *name) +{ + request_region(from, extent, name); +} + +static void mpc30x_ide_release_region(ide_ioreg_t from, unsigned int extent) +{ + release_region(from, extent); +} + +struct ide_ops mpc30x_ide_ops = { + &mpc30x_ide_default_irq, + &mpc30x_ide_default_io_base, + &mpc30x_ide_init_hwif_ports, + &mpc30x_ide_request_irq, + &mpc30x_ide_free_irq, + &mpc30x_ide_check_region, + &mpc30x_ide_request_region, + &mpc30x_ide_release_region +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/victor-mpc30x/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,54 @@ +/* + * FILE NAME + * arch/mips/vr41xx/victor-mpc30x/init.c + * + * BRIEF MODULE DESCRIPTION + * Initialisation code for the Victor MP-C303/304. + * + * Copyright 2002 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include + +#include +#include +#include +#include + +char arcs_cmdline[CL_SIZE]; + +const char *get_system_type(void) +{ + return "Victor MP-C303/304"; +} + +void __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec) +{ + int i; + + /* + * collect args and prepare cmd_line + */ + for (i = 1; i < argc; i++) { + strcat(arcs_cmdline, argv[i]); + if (i < (argc - 1)) + strcat(arcs_cmdline, " "); + } + + mips_machgroup = MACH_GROUP_NEC_VR41XX; + mips_machtype = MACH_VICTOR_MPC30X; + + add_memory_region(0, 32 << 20, BOOT_MEM_RAM); +} + +void __init prom_free_prom_memory (void) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/victor-mpc30x/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,6 @@ +# +# Makefile for the Victor MP-C303/304 specific parts of the kernel +# + +obj-y += init.o setup.o +obj-$(CONFIG_IDE) += ide-mpc30x.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/victor-mpc30x/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,126 @@ +/* + * FILE NAME + * arch/mips/vr41xx/victor-mpc30x/setup.c + * + * BRIEF MODULE DESCRIPTION + * Setup for the Victor MP-C303/304. + * + * Copyright 2002 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_BLK_DEV_INITRD +extern unsigned long initrd_start, initrd_end; +extern void * __rd_start, * __rd_end; +#endif + +#ifdef CONFIG_BLK_DEV_IDE +extern struct ide_ops mpc30x_ide_ops; +#endif + +#ifdef CONFIG_PCI +static struct resource vr41xx_pci_io_resource = { + "PCI I/O space", + VR41XX_PCI_IO_START, + VR41XX_PCI_IO_END, + IORESOURCE_IO +}; + +static struct resource vr41xx_pci_mem_resource = { + "PCI memory space", + VR41XX_PCI_MEM_START, + VR41XX_PCI_MEM_END, + IORESOURCE_MEM +}; + +extern struct pci_ops vr41xx_pci_ops; + +struct pci_channel mips_pci_channels[] = { + {&vr41xx_pci_ops, &vr41xx_pci_io_resource, &vr41xx_pci_mem_resource, 0, 256}, + {NULL, NULL, NULL, 0, 0} +}; + +struct vr41xx_pci_address_space vr41xx_pci_mem1 = { + VR41XX_PCI_MEM1_BASE, + VR41XX_PCI_MEM1_MASK, + IO_MEM1_RESOURCE_START +}; + +struct vr41xx_pci_address_space vr41xx_pci_mem2 = { + VR41XX_PCI_MEM2_BASE, + VR41XX_PCI_MEM2_MASK, + IO_MEM2_RESOURCE_START +}; + +struct vr41xx_pci_address_space vr41xx_pci_io = { + VR41XX_PCI_IO_BASE, + VR41XX_PCI_IO_MASK, + IO_PORT_RESOURCE_START +}; + +static struct vr41xx_pci_address_map pci_address_map = { + &vr41xx_pci_mem1, + &vr41xx_pci_mem2, + &vr41xx_pci_io +}; +#endif + +void __init victor_mpc30x_setup(void) +{ + set_io_port_base(IO_PORT_BASE); + ioport_resource.start = IO_PORT_RESOURCE_START; + ioport_resource.end = IO_PORT_RESOURCE_END; + iomem_resource.start = IO_MEM1_RESOURCE_START; + iomem_resource.end = IO_MEM2_RESOURCE_END; + +#ifdef CONFIG_BLK_DEV_INITRD + ROOT_DEV = Root_RAM0; + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; +#endif + + _machine_restart = vr41xx_restart; + _machine_halt = vr41xx_halt; + _machine_power_off = vr41xx_power_off; + + board_time_init = vr41xx_time_init; + board_timer_setup = vr41xx_timer_setup; + +#ifdef CONFIG_FB + conswitchp = &dummy_con; +#endif + +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &mpc30x_ide_ops; +#endif + + vr41xx_bcu_init(); + + vr41xx_cmu_init(0); + +#ifdef CONFIG_SERIAL_8250 + vr41xx_siu_init(SIU_RS232C, 0); +#endif + +#ifdef CONFIG_PCI + vr41xx_pciu_init(&pci_address_map); +#endif +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/zao-capcella/ide-capcella.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,99 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * IDE routines for typical pc-like standard configurations + * for the ZAO Networks Capcella. + * + * Copyright (C) 1998, 1999, 2001 by Ralf Baechle + */ +/* + * Changes: + * Yoichi Yuasa Sun, 24 Feb 2002 + * - Added ZAO Networks Capcella support. + */ +#include +#include +#include +#include +#include +#include + +static int capcella_ide_default_irq(ide_ioreg_t base) +{ + switch (base) { + case 0x8300: return 42; + } + + return 0; +} + +static ide_ioreg_t capcella_ide_default_io_base(int index) +{ + switch (index) { + case 0: return 0x8300; + } + + return 0; +} + +static void capcella_ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port, + ide_ioreg_t ctrl_port, int *irq) +{ + ide_ioreg_t reg = data_port; + int i; + + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { + hw->io_ports[i] = reg; + reg += 1; + } + if (ctrl_port) { + hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; + } else { + hw->io_ports[IDE_CONTROL_OFFSET] = hw->io_ports[IDE_DATA_OFFSET] + 0x206; + } + if (irq != NULL) + *irq = 0; + hw->io_ports[IDE_IRQ_OFFSET] = 0; +} + +static int capcella_ide_request_irq(unsigned int irq, + void (*handler)(int,void *, struct pt_regs *), + unsigned long flags, const char *device, + void *dev_id) +{ + return request_irq(irq, handler, flags, device, dev_id); +} + +static void capcella_ide_free_irq(unsigned int irq, void *dev_id) +{ + free_irq(irq, dev_id); +} + +static int capcella_ide_check_region(ide_ioreg_t from, unsigned int extent) +{ + return check_region(from, extent); +} + +static void capcella_ide_request_region(ide_ioreg_t from, unsigned int extent, + const char *name) +{ + request_region(from, extent, name); +} + +static void capcella_ide_release_region(ide_ioreg_t from, unsigned int extent) +{ + release_region(from, extent); +} + +struct ide_ops capcella_ide_ops = { + &capcella_ide_default_irq, + &capcella_ide_default_io_base, + &capcella_ide_init_hwif_ports, + &capcella_ide_request_irq, + &capcella_ide_free_irq, + &capcella_ide_check_region, + &capcella_ide_request_region, + &capcella_ide_release_region +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/zao-capcella/init.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,64 @@ +/* + * FILE NAME + * arch/mips/vr41xx/zao-capcella/init.c + * + * BRIEF MODULE DESCRIPTION + * Initialisation code for the ZAO Networks Capcella. + * + * Copyright 2002 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include + +#include +#include +#include +#include + +char arcs_cmdline[CL_SIZE]; + +const char *get_system_type(void) +{ + return "ZAO Networks Capcella"; +} + +void __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec) +{ + u32 config; + int i; + + /* + * collect args and prepare cmd_line + */ + for (i = 1; i < argc; i++) { + strcat(arcs_cmdline, argv[i]); + if (i < (argc - 1)) + strcat(arcs_cmdline, " "); + } + + mips_machgroup = MACH_GROUP_NEC_VR41XX; + mips_machtype = MACH_ZAO_CAPCELLA; + + switch (current_cpu_data.processor_id) { + case PRID_VR4131_REV1_2: + config = read_c0_config(); + config &= ~0x00000030UL; + config |= 0x00410000UL; + write_c0_config(config); + break; + default: + break; + } +} + +void __init prom_free_prom_memory (void) +{ +} --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/zao-capcella/Makefile 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,6 @@ +# +# Makefile for the ZAO Networks Capcella specific parts of the kernel +# + +obj-y += init.o setup.o +obj-$(CONFIG_IDE) += ide-capcella.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/arch/mips/vr41xx/zao-capcella/setup.c 2003-06-27 15:56:23.000000000 -0700 @@ -0,0 +1,127 @@ +/* + * FILE NAME + * arch/mips/vr41xx/zao-capcella/setup.c + * + * BRIEF MODULE DESCRIPTION + * Setup for the ZAO Networks Capcella. + * + * Copyright 2002 Yoichi Yuasa + * yuasa@hh.iij4u.or.jp + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_BLK_DEV_INITRD +extern unsigned long initrd_start, initrd_end; +extern void * __rd_start, * __rd_end; +#endif + +#ifdef CONFIG_BLK_DEV_IDE +extern struct ide_ops capcella_ide_ops; +#endif + +#ifdef CONFIG_PCI +static struct resource vr41xx_pci_io_resource = { + "PCI I/O space", + VR41XX_PCI_IO_START, + VR41XX_PCI_IO_END, + IORESOURCE_IO +}; + +static struct resource vr41xx_pci_mem_resource = { + "PCI memory space", + VR41XX_PCI_MEM_START, + VR41XX_PCI_MEM_END, + IORESOURCE_MEM +}; + +extern struct pci_ops vr41xx_pci_ops; + +struct pci_channel mips_pci_channels[] = { + {&vr41xx_pci_ops, &vr41xx_pci_io_resource, &vr41xx_pci_mem_resource, 0, 256}, + {NULL, NULL, NULL, 0, 0} +}; + +struct vr41xx_pci_address_space vr41xx_pci_mem1 = { + VR41XX_PCI_MEM1_BASE, + VR41XX_PCI_MEM1_MASK, + IO_MEM1_RESOURCE_START +}; + +struct vr41xx_pci_address_space vr41xx_pci_mem2 = { + VR41XX_PCI_MEM2_BASE, + VR41XX_PCI_MEM2_MASK, + IO_MEM2_RESOURCE_START +}; + +struct vr41xx_pci_address_space vr41xx_pci_io = { + VR41XX_PCI_IO_BASE, + VR41XX_PCI_IO_MASK, + IO_PORT_RESOURCE_START +}; + +static struct vr41xx_pci_address_map pci_address_map = { + &vr41xx_pci_mem1, + &vr41xx_pci_mem2, + &vr41xx_pci_io +}; +#endif + +void __init zao_capcella_setup(void) +{ + set_io_port_base(IO_PORT_BASE); + ioport_resource.start = IO_PORT_RESOURCE_START; + ioport_resource.end = IO_PORT_RESOURCE_END; + iomem_resource.start = IO_MEM1_RESOURCE_START; + iomem_resource.end = IO_MEM2_RESOURCE_END; + +#ifdef CONFIG_BLK_DEV_INITRD + ROOT_DEV = Root_RAM0; + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; +#endif + + _machine_restart = vr41xx_restart; + _machine_halt = vr41xx_halt; + _machine_power_off = vr41xx_power_off; + + board_time_init = vr41xx_time_init; + board_timer_setup = vr41xx_timer_setup; + +#ifdef CONFIG_FB + conswitchp = &dummy_con; +#endif + +#ifdef CONFIG_BLK_DEV_IDE + ide_ops = &capcella_ide_ops; +#endif + + vr41xx_bcu_init(); + + vr41xx_cmu_init(0x0102); + +#ifdef CONFIG_SERIAL_8250 + vr41xx_siu_init(SIU_RS232C, 0); + vr41xx_dsiu_init(); +#endif + +#ifdef CONFIG_PCI + vr41xx_pciu_init(&pci_address_map); +#endif +} --- linux-2.5.73/arch/parisc/Kconfig 2003-06-22 12:04:44.000000000 -0700 +++ 25/arch/parisc/Kconfig 2003-06-27 15:56:24.000000000 -0700 @@ -182,33 +182,7 @@ source "drivers/block/Kconfig" source "drivers/ide/Kconfig" - -menu "SCSI support" - -config SCSI - tristate "SCSI support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - -source drivers/scsi/Kconfig - - -endmenu +source "drivers/scsi/Kconfig" source "drivers/md/Kconfig" --- linux-2.5.73/arch/ppc64/Kconfig 2003-06-22 12:04:44.000000000 -0700 +++ 25/arch/ppc64/Kconfig 2003-06-27 15:56:24.000000000 -0700 @@ -253,33 +253,8 @@ source "drivers/block/Kconfig" source "drivers/ide/Kconfig" - -menu "SCSI device support" - -config SCSI - tristate "SCSI device support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - source "drivers/scsi/Kconfig" -endmenu - source "drivers/md/Kconfig" source "drivers/message/fusion/Kconfig" --- linux-2.5.73/arch/ppc64/kernel/semaphore.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/ppc64/kernel/semaphore.c 2003-06-27 15:56:31.000000000 -0700 @@ -21,6 +21,7 @@ #include #include +#if 0 /* * Atomically update sem->count. * This does the equivalent of the following: @@ -129,3 +130,140 @@ int __down_interruptible(struct semaphor wake_up(&sem->wait); return retval; } +#else + +static __inline__ int atomic_add_negative(int i, atomic_t *v) +{ + if (atomic_add_return(i, v) < 0) + return 1; + else + return 0; +} + +void __up(struct semaphore *sem) +{ + wake_up(&sem->wait); +} + +void __down(struct semaphore * sem) +{ + struct task_struct *tsk = current; + DECLARE_WAITQUEUE(wait, tsk); + unsigned long flags; + + tsk->state = TASK_UNINTERRUPTIBLE; + spin_lock_irqsave(&sem->wait.lock, flags); + add_wait_queue_exclusive_locked(&sem->wait, &wait); + + sem->sleepers++; + for (;;) { + int sleepers = sem->sleepers; + + /* + * Add "everybody else" into it. They aren't + * playing, because we own the spinlock in + * the wait_queue_head. + */ + if (!atomic_add_negative(sleepers - 1, &sem->count)) { + sem->sleepers = 0; + break; + } + sem->sleepers = 1; /* us - see -1 above */ + spin_unlock_irqrestore(&sem->wait.lock, flags); + + schedule(); + + spin_lock_irqsave(&sem->wait.lock, flags); + tsk->state = TASK_UNINTERRUPTIBLE; + } + remove_wait_queue_locked(&sem->wait, &wait); + wake_up_locked(&sem->wait); + spin_unlock_irqrestore(&sem->wait.lock, flags); + tsk->state = TASK_RUNNING; +} + +int __down_interruptible(struct semaphore * sem) +{ + int retval = 0; + struct task_struct *tsk = current; + DECLARE_WAITQUEUE(wait, tsk); + unsigned long flags; + + tsk->state = TASK_INTERRUPTIBLE; + spin_lock_irqsave(&sem->wait.lock, flags); + add_wait_queue_exclusive_locked(&sem->wait, &wait); + + sem->sleepers++; + for (;;) { + int sleepers = sem->sleepers; + + /* + * With signals pending, this turns into + * the trylock failure case - we won't be + * sleeping, and we* can't get the lock as + * it has contention. Just correct the count + * and exit. + */ + if (signal_pending(current)) { + retval = -EINTR; + sem->sleepers = 0; + atomic_add(sleepers, &sem->count); + break; + } + + /* + * Add "everybody else" into it. They aren't + * playing, because we own the spinlock in + * wait_queue_head. The "-1" is because we're + * still hoping to get the semaphore. + */ + if (!atomic_add_negative(sleepers - 1, &sem->count)) { + sem->sleepers = 0; + break; + } + sem->sleepers = 1; /* us - see -1 above */ + spin_unlock_irqrestore(&sem->wait.lock, flags); + + schedule(); + + spin_lock_irqsave(&sem->wait.lock, flags); + tsk->state = TASK_INTERRUPTIBLE; + } + remove_wait_queue_locked(&sem->wait, &wait); + wake_up_locked(&sem->wait); + spin_unlock_irqrestore(&sem->wait.lock, flags); + + tsk->state = TASK_RUNNING; + return retval; +} + +/* + * Trylock failed - make sure we correct for + * having decremented the count. + * + * We could have done the trylock with a + * single "cmpxchg" without failure cases, + * but then it wouldn't work on a 386. + */ +int __down_trylock(struct semaphore * sem) +{ + int sleepers; + unsigned long flags; + + spin_lock_irqsave(&sem->wait.lock, flags); + sleepers = sem->sleepers + 1; + sem->sleepers = 0; + + /* + * Add "everybody else" and us into it. They aren't + * playing, because we own the spinlock in the + * wait_queue_head. + */ + if (!atomic_add_negative(sleepers, &sem->count)) { + wake_up_locked(&sem->wait); + } + + spin_unlock_irqrestore(&sem->wait.lock, flags); + return 1; +} +#endif --- linux-2.5.73/arch/ppc64/kernel/smp.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/ppc64/kernel/smp.c 2003-06-27 15:56:29.000000000 -0700 @@ -57,7 +57,7 @@ unsigned long cpu_online_map = 0; static struct smp_ops_t *smp_ops; -volatile unsigned int cpu_callin_map[NR_CPUS]; +static volatile unsigned int cpu_callin_map[NR_CPUS]; extern unsigned char stab_array[]; --- linux-2.5.73/arch/ppc64/xmon/ppc-opc.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/ppc64/xmon/ppc-opc.c 2003-06-27 15:56:31.000000000 -0700 @@ -394,18 +394,13 @@ const struct powerpc_operand powerpc_ope /*ARGSUSED*/ static unsigned long -insert_bat (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_bat(unsigned long insn, long value, const char **errmsg) { return insn | (((insn >> 21) & 0x1f) << 16); } static long -extract_bat (insn, invalid) - unsigned long insn; - int *invalid; +extract_bat(unsigned long insn, int *invalid) { if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) @@ -421,18 +416,13 @@ extract_bat (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_bba (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_bba(unsigned long insn, long value, const char **errmsg) { return insn | (((insn >> 16) & 0x1f) << 11); } static long -extract_bba (insn, invalid) - unsigned long insn; - int *invalid; +extract_bba(unsigned long insn, int *invalid) { if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) @@ -445,19 +435,14 @@ extract_bba (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_bd (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_bd(unsigned long insn, long value, const char **errmsg) { return insn | (value & 0xfffc); } /*ARGSUSED*/ static long -extract_bd (insn, invalid) - unsigned long insn; - int *invalid; +extract_bd(unsigned long insn, int *invalid) { if ((insn & 0x8000) != 0) return (insn & 0xfffc) - 0x10000; @@ -474,10 +459,7 @@ extract_bd (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_bdm (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_bdm(unsigned long insn, long value, const char **errmsg) { if ((value & 0x8000) != 0) insn |= 1 << 21; @@ -485,9 +467,7 @@ insert_bdm (insn, value, errmsg) } static long -extract_bdm (insn, invalid) - unsigned long insn; - int *invalid; +extract_bdm(unsigned long insn, int *invalid) { if (invalid != (int *) NULL && ((insn & (1 << 21)) == 0 @@ -505,10 +485,7 @@ extract_bdm (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_bdp (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_bdp(unsigned long insn, long value, const char **errmsg) { if ((value & 0x8000) == 0) insn |= 1 << 21; @@ -516,9 +493,7 @@ insert_bdp (insn, value, errmsg) } static long -extract_bdp (insn, invalid) - unsigned long insn; - int *invalid; +extract_bdp(unsigned long insn, int *invalid) { if (invalid != (int *) NULL && ((insn & (1 << 21)) == 0 @@ -561,10 +536,7 @@ valid_bo (long value) the field to an illegal value. */ static unsigned long -insert_bo (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_bo(unsigned long insn, long value, const char **errmsg) { if (errmsg != (const char **) NULL && ! valid_bo (value)) @@ -573,9 +545,7 @@ insert_bo (insn, value, errmsg) } static long -extract_bo (insn, invalid) - unsigned long insn; - int *invalid; +extract_bo(unsigned long insn, int *invalid) { long value; @@ -591,10 +561,7 @@ extract_bo (insn, invalid) extracting it, we force it to be even. */ static unsigned long -insert_boe (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_boe(unsigned long insn, long value, const char **errmsg) { if (errmsg != (const char **) NULL) { @@ -607,9 +574,7 @@ insert_boe (insn, value, errmsg) } static long -extract_boe (insn, invalid) - unsigned long insn; - int *invalid; +extract_boe(unsigned long insn, int *invalid) { long value; @@ -625,19 +590,14 @@ extract_boe (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_ds (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_ds(unsigned long insn, long value, const char **errmsg) { return insn | (value & 0xfffc); } /*ARGSUSED*/ static long -extract_ds (insn, invalid) - unsigned long insn; - int *invalid; +extract_ds(unsigned long insn, int *invalid) { if ((insn & 0x8000) != 0) return (insn & 0xfffc) - 0x10000; @@ -650,19 +610,14 @@ extract_ds (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_li (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_li(unsigned long insn, long value, const char **errmsg) { return insn | (value & 0x3fffffc); } /*ARGSUSED*/ static long -extract_li (insn, invalid) - unsigned long insn; - int *invalid; +extract_li(unsigned long insn, int *invalid) { if ((insn & 0x2000000) != 0) return (insn & 0x3fffffc) - 0x4000000; @@ -676,10 +631,7 @@ extract_li (insn, invalid) instruction which uses a field of this type. */ static unsigned long -insert_mbe (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_mbe(unsigned long insn, long value, const char **errmsg) { unsigned long uval; int mb, me; @@ -718,9 +670,7 @@ insert_mbe (insn, value, errmsg) } static long -extract_mbe (insn, invalid) - unsigned long insn; - int *invalid; +extract_mbe(unsigned long insn, int *invalid) { long ret; int mb, me; @@ -742,19 +692,14 @@ extract_mbe (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_mb6 (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_mb6(unsigned long insn, long value, const char **errmsg) { return insn | ((value & 0x1f) << 6) | (value & 0x20); } /*ARGSUSED*/ static long -extract_mb6 (insn, invalid) - unsigned long insn; - int *invalid; +extract_mb6(unsigned long insn, int *invalid) { return ((insn >> 6) & 0x1f) | (insn & 0x20); } @@ -763,10 +708,7 @@ extract_mb6 (insn, invalid) 0. */ static unsigned long -insert_nb (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_nb(unsigned long insn, long value, const char **errmsg) { if (value < 0 || value > 32) *errmsg = "value out of range"; @@ -777,9 +719,7 @@ insert_nb (insn, value, errmsg) /*ARGSUSED*/ static long -extract_nb (insn, invalid) - unsigned long insn; - int *invalid; +extract_nb(unsigned long insn, int *invalid) { long ret; @@ -796,18 +736,13 @@ extract_nb (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_nsi (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_nsi(unsigned long insn, long value, const char **errmsg) { return insn | ((- value) & 0xffff); } static long -extract_nsi (insn, invalid) - unsigned long insn; - int *invalid; +extract_nsi(unsigned long insn, int *invalid) { if (invalid != (int *) NULL) *invalid = 1; @@ -822,10 +757,7 @@ extract_nsi (insn, invalid) equal the RT field. */ static unsigned long -insert_ral (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_ral(unsigned long insn, long value, const char **errmsg) { if (value == 0 || value == ((insn >> 21) & 0x1f)) @@ -837,10 +769,7 @@ insert_ral (insn, value, errmsg) restrictions. */ static unsigned long -insert_ram (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_ram(unsigned long insn, long value, const char **errmsg) { if (value >= ((insn >> 21) & 0x1f)) *errmsg = "index register in load range"; @@ -852,10 +781,7 @@ insert_ram (insn, value, errmsg) field may not be zero. */ static unsigned long -insert_ras (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_ras(unsigned long insn, long value, const char **errmsg) { if (value == 0) *errmsg = "invalid register operand when updating"; @@ -870,18 +796,13 @@ insert_ras (insn, value, errmsg) /*ARGSUSED*/ static unsigned long -insert_rbs (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_rbs(unsigned long insn, long value, const char **errmsg) { return insn | (((insn >> 21) & 0x1f) << 11); } static long -extract_rbs (insn, invalid) - unsigned long insn; - int *invalid; +extract_rbs(unsigned long insn, int *invalid) { if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) @@ -893,19 +814,14 @@ extract_rbs (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_sh6 (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_sh6(unsigned long insn, long value, const char **errmsg) { return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); } /*ARGSUSED*/ static long -extract_sh6 (insn, invalid) - unsigned long insn; - int *invalid; +extract_sh6(unsigned long insn, int *invalid) { return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); } @@ -914,18 +830,13 @@ extract_sh6 (insn, invalid) lower 5 bits are stored in the upper 5 and vice- versa. */ static unsigned long -insert_spr (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_spr(unsigned long insn, long value, const char **errmsg) { return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); } static long -extract_spr (insn, invalid) - unsigned long insn; - int *invalid; +extract_spr(unsigned long insn, int *invalid) { return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); } @@ -941,10 +852,7 @@ extract_spr (insn, invalid) #define TB (268) static unsigned long -insert_tbr (insn, value, errmsg) - unsigned long insn; - long value; - const char **errmsg; +insert_tbr(unsigned long insn, long value, const char **errmsg) { if (value == 0) value = TB; @@ -952,9 +860,7 @@ insert_tbr (insn, value, errmsg) } static long -extract_tbr (insn, invalid) - unsigned long insn; - int *invalid; +extract_tbr(unsigned long insn, int *invalid) { long ret; --- linux-2.5.73/arch/ppc64/xmon/xmon.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/ppc64/xmon/xmon.c 2003-06-27 15:56:31.000000000 -0700 @@ -448,7 +448,7 @@ at_breakpoint(unsigned long pc) } static void -insert_bpts() +insert_bpts(void) { int i; struct bpt *bp; @@ -476,7 +476,7 @@ insert_bpts() } static void -remove_bpts() +remove_bpts(void) { int i; struct bpt *bp; @@ -1010,7 +1010,7 @@ backtrace(struct pt_regs *excp) } int -getsp() +getsp(void) { int x; @@ -1160,7 +1160,7 @@ print_sysmap(void) } void -super_regs() +super_regs(void) { int i, cmd; unsigned long val; @@ -1351,7 +1351,7 @@ static unsigned long hash_start; static unsigned long hash_end; static void -dump_hash_table() +dump_hash_table(void) { int seg; unsigned seg_start, seg_end; @@ -1535,7 +1535,7 @@ static char *memex_subcmd_help_string = ""; void -memex() +memex(void) { int cmd, inc, i, nslash; unsigned long n; @@ -1686,7 +1686,7 @@ memex() } int -bsesc() +bsesc(void) { int c; @@ -1704,7 +1704,7 @@ bsesc() || ('a' <= (c) && (c) <= 'f') \ || ('A' <= (c) && (c) <= 'F')) void -dump() +dump(void) { int c; @@ -1863,7 +1863,7 @@ static unsigned mend; static unsigned mask; void -memlocate() +memlocate(void) { unsigned a, n; unsigned char val[4]; @@ -1896,7 +1896,7 @@ static unsigned long mskip = 0x1000; static unsigned long mlim = 0xffffffff; void -memzcan() +memzcan(void) { unsigned char v; unsigned a; @@ -1925,7 +1925,7 @@ memzcan() /* Input scanning routines */ int -skipbl() +skipbl(void) { int c; @@ -1950,8 +1950,7 @@ static char *regnames[N_PTREGS] = { }; int -scanhex(vp) -unsigned long *vp; +scanhex(unsigned long *vp) { int c, d; unsigned long v; @@ -2004,7 +2003,7 @@ unsigned long *vp; } void -scannl() +scannl(void) { int c; @@ -2047,13 +2046,13 @@ static char line[256]; static char *lineptr; void -flush_input() +flush_input(void) { lineptr = NULL; } int -inchar() +inchar(void) { if (lineptr == NULL || *lineptr == 0) { if (fgets(line, sizeof(line), stdin) == NULL) { @@ -2066,8 +2065,7 @@ inchar() } void -take_input(str) -char *str; +take_input(char *str) { lineptr = str; } @@ -2180,7 +2178,7 @@ find_tb_table(unsigned long codeaddr, st } void -mem_translate() +mem_translate(void) { int c; unsigned long ea, va, vsid, vpn, page, hpteg_slot_primary, hpteg_slot_secondary, primary_hash, i, *steg, esid, stabl; @@ -2302,7 +2300,7 @@ mem_translate() } } -void mem_check() +void mem_check(void) { unsigned long htab_size_bytes; unsigned long htab_end; @@ -2344,7 +2342,7 @@ void mem_check() printf("\nDone -------------------\n"); } -void mem_find_real() +void mem_find_real(void) { unsigned long htab_size_bytes; unsigned long htab_end; @@ -2380,7 +2378,7 @@ void mem_find_real() printf("\nDone -------------------\n"); } -void mem_find_vsid() +void mem_find_vsid(void) { unsigned long htab_size_bytes; unsigned long htab_end; --- linux-2.5.73/arch/ppc/Kconfig 2003-06-22 12:04:44.000000000 -0700 +++ 25/arch/ppc/Kconfig 2003-06-27 15:56:24.000000000 -0700 @@ -1175,33 +1175,8 @@ source "drivers/md/Kconfig" source "drivers/ide/Kconfig" - -menu "SCSI support" - -config SCSI - tristate "SCSI support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - source "drivers/scsi/Kconfig" -endmenu - source "drivers/message/fusion/Kconfig" source "drivers/ieee1394/Kconfig" @@ -1218,15 +1193,8 @@ source "drivers/isdn/Kconfig" source "drivers/video/Kconfig" -menu "Old CD-ROM drivers (not SCSI, not IDE)" - -config CD_NO_IDESCSI - bool "Support non-SCSI/IDE/ATAPI CDROM drives" - source "drivers/cdrom/Kconfig" -endmenu - source "drivers/input/Kconfig" --- linux-2.5.73/arch/ppc/kernel/entry.S 2003-06-14 12:18:33.000000000 -0700 +++ 25/arch/ppc/kernel/entry.S 2003-06-27 15:56:24.000000000 -0700 @@ -173,8 +173,10 @@ _GLOBAL(DoSyscall) cmpli 0,r0,NR_syscalls bge- 66f rlwinm r10,r1,0,0,18 /* current_thread_info() */ - lwz r10,TI_FLAGS(r10) - andi. r10,r10,_TIF_SYSCALL_TRACE + lwz r11,TI_FLAGS(r10) + rlwinm r11,r11,0,~_TIF_FORCE_NOERROR + stw r11,TI_FLAGS(r10) + andi. r11,r11,_TIF_SYSCALL_TRACE bne- syscall_dotrace syscall_dotrace_cont: lis r10,sys_call_table@h @@ -192,11 +194,12 @@ ret_from_syscall: mr r6,r3 li r11,-_LAST_ERRNO cmpl 0,r3,r11 + rlwinm r12,r1,0,0,18 /* current_thread_info() */ blt+ 30f + lwz r11,TI_FLAGS(r12) + andi. r11,r11,_TIF_FORCE_NOERROR + bne 30f neg r3,r3 - cmpi 0,r3,ERESTARTNOHAND - bne 22f - li r3,EINTR 22: lwz r10,_CCR(r1) /* Set SO bit in CR */ oris r10,r10,0x1000 stw r10,_CCR(r1) @@ -205,7 +208,6 @@ ret_from_syscall: 30: LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */ SYNC MTMSRD(r10) - rlwinm r12,r1,0,0,18 /* current_thread_info() */ lwz r9,TI_FLAGS(r12) andi. r0,r9,(_TIF_SYSCALL_TRACE|_TIF_SIGPENDING|_TIF_NEED_RESCHED) bne- syscall_exit_work --- linux-2.5.73/arch/ppc/kernel/process.c 2003-06-14 12:18:20.000000000 -0700 +++ 25/arch/ppc/kernel/process.c 2003-06-27 15:56:24.000000000 -0700 @@ -69,8 +69,6 @@ struct task_struct init_task = INIT_TASK /* only used to get secondary processor up */ struct task_struct *current_set[NR_CPUS] = {&init_task, }; -static void show_tsk_stack(struct task_struct *tsk, unsigned long sp); - #undef SHOW_TASK_SWITCHES #undef CHECK_STACK @@ -296,7 +294,7 @@ void show_regs(struct pt_regs * regs) break; } printk("\n"); - show_tsk_stack(current, regs->gpr[1]); + show_stack(current, (unsigned long *) regs->gpr[1]); } void exit_thread(void) @@ -494,26 +492,29 @@ out: return error; } -void show_trace_task(struct task_struct *tsk) -{ - show_tsk_stack(tsk, tsk->thread.ksp); -} - void dump_stack(void) { - show_tsk_stack(current, _get_SP()); + show_stack(current, NULL); } -static void show_tsk_stack(struct task_struct *tsk, unsigned long sp) +void show_stack(struct task_struct *tsk, unsigned long *stack) { - unsigned long stack_top, prev_sp, ret; + unsigned long sp, stack_top, prev_sp, ret; int count = 0; unsigned long next_exc = 0; struct pt_regs *regs; extern char ret_from_except, ret_from_except_full, ret_from_syscall; + sp = (unsigned long) stack; if (tsk == NULL) - return; + tsk = current; + if (sp == 0) { + if (tsk == current) + asm("mr %0,1" : "=r" (sp)); + else + sp = tsk->thread.ksp; + } + prev_sp = (unsigned long) (tsk->thread_info + 1); stack_top = (unsigned long) tsk->thread_info + THREAD_SIZE; while (count < 16 && sp > prev_sp && sp < stack_top && (sp & 3) == 0) { --- linux-2.5.73/arch/s390/defconfig 2003-06-14 12:18:31.000000000 -0700 +++ 25/arch/s390/defconfig 2003-06-27 15:56:24.000000000 -0700 @@ -68,6 +68,11 @@ CONFIG_PFAULT=y # CONFIG_PCMCIA is not set # +# Generic Driver Options +# +# CONFIG_FW_LOADER is not set + +# # SCSI support # # CONFIG_SCSI is not set @@ -166,6 +171,7 @@ CONFIG_IPV6=m # CONFIG_INET6_AH is not set # CONFIG_INET6_ESP is not set # CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_TUNNEL is not set # CONFIG_XFRM_USER is not set # --- linux-2.5.73/arch/s390/Kconfig 2003-06-22 12:04:44.000000000 -0700 +++ 25/arch/s390/Kconfig 2003-06-27 15:56:24.000000000 -0700 @@ -231,15 +231,8 @@ config PCMCIA source "drivers/base/Kconfig" -menu "SCSI support" - -config SCSI - tristate "SCSI support" - source "drivers/scsi/Kconfig" -endmenu - source "drivers/s390/Kconfig" source "net/Kconfig" --- linux-2.5.73/arch/s390/kernel/compat_ioctl.c 2003-06-14 12:18:25.000000000 -0700 +++ 25/arch/s390/kernel/compat_ioctl.c 2003-06-27 15:56:24.000000000 -0700 @@ -42,12 +42,15 @@ #include #include #include +#include #include #include #include +#include #include #include +#include #include #include --- linux-2.5.73/arch/s390/kernel/compat_linux.c 2003-06-14 12:18:30.000000000 -0700 +++ 25/arch/s390/kernel/compat_linux.c 2003-06-27 15:56:24.000000000 -0700 @@ -2193,7 +2193,6 @@ done: sorts of things, like timeval and itimerval. */ extern struct timezone sys_tz; -extern int do_sys_settimeofday(struct timeval *tv, struct timezone *tz); asmlinkage int sys32_gettimeofday(struct compat_timeval *tv, struct timezone *tz) { @@ -2210,13 +2209,27 @@ asmlinkage int sys32_gettimeofday(struct return 0; } +static inline long get_ts32(struct timespec *o, struct compat_timeval *i) +{ + long usec; + + if (!access_ok(VERIFY_READ, i, sizeof(*i))) + return -EFAULT; + if (__get_user(o->tv_sec, &i->tv_sec)) + return -EFAULT; + if (__get_user(usec, &i->tv_usec)) + return -EFAULT; + o->tv_nsec = usec * 1000; + return 0; +} + asmlinkage int sys32_settimeofday(struct compat_timeval *tv, struct timezone *tz) { - struct timeval ktv; + struct timespec kts; struct timezone ktz; if (tv) { - if (get_tv32(&ktv, tv)) + if (get_ts32(&kts, tv)) return -EFAULT; } if (tz) { @@ -2224,7 +2237,7 @@ asmlinkage int sys32_settimeofday(struct return -EFAULT; } - return do_sys_settimeofday(tv ? &ktv : NULL, tz ? &ktz : NULL); + return do_sys_settimeofday(tv ? &kts : NULL, tz ? &ktz : NULL); } asmlinkage int sys_utimes(char *, struct timeval *); --- linux-2.5.73/arch/s390/kernel/smp.c 2003-06-14 12:17:56.000000000 -0700 +++ 25/arch/s390/kernel/smp.c 2003-06-27 15:56:24.000000000 -0700 @@ -419,8 +419,6 @@ void __init smp_check_cpus(unsigned int boot_cpu_addr = S390_lowcore.cpu_data.cpu_addr; current_thread_info()->cpu = 0; num_cpus = 1; - cpu_possible_map = 1; - cpu_online_map = 1; for (curr_cpu = 0; curr_cpu <= 65535 && num_cpus < max_cpus; curr_cpu++) { if ((__u16) curr_cpu == boot_cpu_addr) --- linux-2.5.73/arch/s390/kernel/syscalls.S 2003-06-14 12:17:57.000000000 -0700 +++ 25/arch/s390/kernel/syscalls.S 2003-06-27 15:56:24.000000000 -0700 @@ -118,7 +118,7 @@ SYSCALL(sys_newstat,sys_newstat,compat_s SYSCALL(sys_newlstat,sys_newlstat,compat_sys_newlstat_wrapper) SYSCALL(sys_newfstat,sys_newfstat,compat_sys_newfstat_wrapper) NI_SYSCALL /* old uname syscall */ -NI_SYSCALL /* 110 iopl for i386 */ +NI_SYSCALL /* reserved for sys_lookup_dcache */ SYSCALL(sys_vhangup,sys_vhangup,sys_vhangup) NI_SYSCALL /* old "idle" system call */ NI_SYSCALL /* vm86old for i386 */ --- linux-2.5.73/arch/s390/kernel/traps.c 2003-06-14 12:18:07.000000000 -0700 +++ 25/arch/s390/kernel/traps.c 2003-06-27 15:56:24.000000000 -0700 @@ -78,7 +78,7 @@ static int kstack_depth_to_print = 20; #endif /* CONFIG_ARCH_S390X */ -void show_trace(unsigned long * stack) +void show_trace(struct task_struct *task, unsigned long * stack) { unsigned long backchain, low_addr, high_addr, ret_addr; @@ -109,10 +109,10 @@ void show_trace_task(struct task_struct */ if (tsk->state == TASK_RUNNING) return; - show_trace((unsigned long *) tsk->thread.ksp); + show_trace(tsk, (unsigned long *) tsk->thread.ksp); } -void show_stack(unsigned long *sp) +void show_stack(struct task_struct *task, unsigned long *sp) { unsigned long *stack; int i; @@ -132,7 +132,7 @@ void show_stack(unsigned long *sp) printk("%p ", (void *)*stack++); } printk("\n"); - show_trace(sp); + show_trace(task, sp); } /* @@ -140,7 +140,7 @@ void show_stack(unsigned long *sp) */ void dump_stack(void) { - show_stack(0); + show_stack(current, 0); } void show_registers(struct pt_regs *regs) --- linux-2.5.73/arch/sh/Kconfig 2003-06-22 12:04:44.000000000 -0700 +++ 25/arch/sh/Kconfig 2003-06-27 15:56:24.000000000 -0700 @@ -777,69 +777,10 @@ source "drivers/block/Kconfig" source "drivers/ide/Kconfig" - -menu "SCSI device support" - -config SCSI - tristate "SCSI device support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - source "drivers/scsi/Kconfig" -endmenu - - -menu "Old CD-ROM drivers (not SCSI, not IDE)" - -config CD_NO_IDESCSI - bool "Support non-SCSI/IDE/ATAPI CDROM drives" - ---help--- - If you have a CD-ROM drive that is neither SCSI nor IDE/ATAPI, say Y - here, otherwise N. Read the CD-ROM-HOWTO, available from - . - - Note that the answer to this question doesn't directly affect the - kernel: saying N will just cause the configurator to skip all - the questions about these CD-ROM drives. If you are unsure what you - have, say Y and find out whether you have one of the following - drives. - - For each of these drivers, a file Documentation/cdrom/{driver_name} - exists. Especially in cases where you do not know exactly which kind - of drive you have you should read there. Most of these drivers use a - file drivers/cdrom/{driver_name}.h where you can define your - interface parameters and switch some internal goodies. - - All these CD-ROM drivers are also usable as a module ( = code which - can be inserted in and removed from the running kernel whenever you - want). If you want to compile them as module, say M instead of Y and - read . - - If you want to use any of these CD-ROM drivers, you also have to - answer Y or M to "ISO 9660 CD-ROM file system support" below (this - answer will get "defaulted" for you if you enable any of the Linux - CD-ROM drivers). - source "drivers/cdrom/Kconfig" -endmenu - source "drivers/md/Kconfig" source "drivers/ieee1394/Kconfig" --- linux-2.5.73/arch/sparc64/defconfig 2003-06-22 12:04:44.000000000 -0700 +++ 25/arch/sparc64/defconfig 2003-06-27 15:56:24.000000000 -0700 @@ -27,7 +27,7 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set +CONFIG_MODVERSIONS=y CONFIG_KMOD=y # @@ -162,7 +162,9 @@ CONFIG_LOGO_SUN_CLUT224=y # CONFIG_SERIAL_SUNCORE=y CONFIG_SERIAL_SUNZILOG=y +CONFIG_SERIAL_SUNZILOG_CONSOLE=y CONFIG_SERIAL_SUNSU=y +CONFIG_SERIAL_SUNSU_CONSOLE=y CONFIG_SERIAL_SUNSAB=m CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y @@ -197,8 +199,8 @@ CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m CONFIG_MD_RAID1=m -# CONFIG_MD_RAID5 is not set -# CONFIG_MD_MULTIPATH is not set +CONFIG_MD_RAID5=m +CONFIG_MD_MULTIPATH=m CONFIG_BLK_DEV_DM=m # CONFIG_BLK_DEV_RAM is not set @@ -243,26 +245,27 @@ CONFIG_BLK_DEV_ADMA=y # CONFIG_BLK_DEV_AEC62XX is not set CONFIG_BLK_DEV_ALI15X3=y # CONFIG_WDC_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set -# CONFIG_BLK_DEV_CMD64X is not set -# CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_CY82C693 is not set -# CONFIG_BLK_DEV_CS5520 is not set -# CONFIG_BLK_DEV_HPT34X is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_SC1200 is not set -# CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_OPTI621 is not set -# CONFIG_BLK_DEV_PDC202XX_OLD is not set -# CONFIG_BLK_DEV_PDC202XX_NEW is not set -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SIIMAGE is not set -# CONFIG_BLK_DEV_SLC90E66 is not set -# CONFIG_BLK_DEV_TRM290 is not set -# CONFIG_BLK_DEV_VIA82CXXX is not set +CONFIG_BLK_DEV_AMD74XX=m +CONFIG_BLK_DEV_CMD64X=m +CONFIG_BLK_DEV_TRIFLEX=m +CONFIG_BLK_DEV_CY82C693=m +CONFIG_BLK_DEV_CS5520=m +CONFIG_BLK_DEV_HPT34X=m +CONFIG_BLK_DEV_HPT366=m +CONFIG_BLK_DEV_SC1200=m +CONFIG_BLK_DEV_PIIX=m +CONFIG_BLK_DEV_NS87415=m +CONFIG_BLK_DEV_OPTI621=m +CONFIG_BLK_DEV_PDC202XX_OLD=m +CONFIG_BLK_DEV_PDC202XX_NEW=m +CONFIG_BLK_DEV_SVWKS=m +CONFIG_BLK_DEV_SIIMAGE=m +CONFIG_BLK_DEV_SLC90E66=m +CONFIG_BLK_DEV_TRM290=m +CONFIG_BLK_DEV_VIA82CXXX=m CONFIG_IDEDMA_AUTO=y # CONFIG_IDEDMA_IVB is not set +CONFIG_BLK_DEV_PDC202XX=y CONFIG_BLK_DEV_IDE_MODES=y # @@ -408,14 +411,18 @@ CONFIG_NETFILTER=y CONFIG_UNIX=y CONFIG_NET_KEY=m CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set +CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set # CONFIG_IP_PNP is not set CONFIG_NET_IPIP=m CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y CONFIG_ARPD=y CONFIG_INET_ECN=y -# CONFIG_SYN_COOKIES is not set +CONFIG_SYN_COOKIES=y CONFIG_INET_AH=y CONFIG_INET_ESP=y CONFIG_INET_IPCOMP=y @@ -436,6 +443,7 @@ CONFIG_IP_NF_MATCH_PKTTYPE=m CONFIG_IP_NF_MATCH_MARK=m CONFIG_IP_NF_MATCH_MULTIPORT=m CONFIG_IP_NF_MATCH_TOS=m +CONFIG_IP_NF_MATCH_RECENT=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_DSCP=m CONFIG_IP_NF_MATCH_AH_ESP=m @@ -553,9 +561,9 @@ CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_DNAT=m CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_MARK_T=m -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_NET_DIVERT=y # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_NET_FASTROUTE is not set @@ -661,11 +669,13 @@ CONFIG_VIA_RHINE=m # # Ethernet (1000 Mbit) # -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set +CONFIG_DL2K=m +CONFIG_E1000=m +CONFIG_E1000_NAPI=y CONFIG_MYRI_SBUS=m -# CONFIG_NS83820 is not set +CONFIG_NS83820=m CONFIG_HAMACHI=m CONFIG_YELLOWFIN=m CONFIG_R8169=m @@ -710,8 +720,11 @@ CONFIG_NET_RADIO=y # # Wireless 802.11b ISA/PCI cards support # -# CONFIG_AIRO is not set -# CONFIG_HERMES is not set +CONFIG_AIRO=m +CONFIG_HERMES=m +CONFIG_PLX_HERMES=m +CONFIG_TMD_HERMES=m +CONFIG_PCI_HERMES=m CONFIG_NET_WIRELESS=y # @@ -934,7 +947,6 @@ CONFIG_KEYBOARD_SUNKBD=y # CONFIG_KEYBOARD_NEWTON is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_SERIAL=y # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TOUCHSCREEN is not set --- linux-2.5.73/arch/sparc64/Kconfig 2003-06-22 12:04:44.000000000 -0700 +++ 25/arch/sparc64/Kconfig 2003-06-27 15:56:24.000000000 -0700 @@ -675,33 +675,8 @@ endmenu source "drivers/ide/Kconfig" - -menu "SCSI support" - -config SCSI - tristate "SCSI support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - source "drivers/scsi/Kconfig" -endmenu - source "drivers/fc4/Kconfig" if PCI --- linux-2.5.73/arch/sparc64/kernel/devices.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/sparc64/kernel/devices.c 2003-06-27 15:56:46.000000000 -0700 @@ -31,6 +31,8 @@ int linux_num_cpus = 0; extern void cpu_probe(void); extern void central_probe(void); +unsigned long cpu_hz; + void __init device_scan(void) { char node_str[128]; @@ -68,6 +70,8 @@ void __init device_scan(void) prom_getproperty(scan, "portid", (char *) &thismid, sizeof(thismid)); } + if (!cpu_hz) + cpu_hz = prom_getint(scan, "clock-frequency"); linux_cpus[cpu_ctr].mid = thismid; printk("Found CPU %d (node=%08x,mid=%d)\n", cpu_ctr, (unsigned) scan, thismid); --- linux-2.5.73/arch/sparc64/kernel/systbls.S 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/sparc64/kernel/systbls.S 2003-06-27 15:56:24.000000000 -0700 @@ -65,8 +65,8 @@ sys_call_table32: .word sys32_ipc, sys32_sigreturn, sys_clone, sys_nis_syscall, sys32_adjtimex /*220*/ .word compat_sys_sigprocmask, sys_ni_syscall, sys32_delete_module, sys_ni_syscall, sys_getpgid .word sys32_bdflush, sys32_sysfs, sys_nis_syscall, sys32_setfsuid16, sys32_setfsgid16 -/*230*/ .word sys32_select, sys_time, sys_nis_syscall, sys_stime, sys_ni_syscall - .word sys_ni_syscall, sys_llseek, sys_mlock, sys_munlock, sys_mlockall +/*230*/ .word sys32_select, sys_time, sys_nis_syscall, sys_stime, sys_statfs64 + .word sys_fstatfs64, sys_llseek, sys_mlock, sys_munlock, sys_mlockall /*240*/ .word sys_munlockall, sys_sched_setparam, sys_sched_getparam, sys_sched_setscheduler, sys_sched_getscheduler .word sys_sched_yield, sys_sched_get_priority_max, sys_sched_get_priority_min, sys32_sched_rr_get_interval, compat_sys_nanosleep /*250*/ .word sys32_mremap, sys32_sysctl, sys_getsid, sys_fdatasync, sys32_nfsservctl @@ -124,11 +124,8 @@ sys_call_table: .word sys_ipc, sys_nis_syscall, sys_clone, sys_nis_syscall, sys_adjtimex /*220*/ .word sys_nis_syscall, sys_ni_syscall, sys_delete_module, sys_ni_syscall, sys_getpgid .word sys_bdflush, sys_sysfs, sys_nis_syscall, sys_setfsuid, sys_setfsgid - - /* 234 and 235 were for the hugetlb syscalls. They can be reused */ - -/*230*/ .word sys_select, sys_nis_syscall, sys_nis_syscall, sys_stime, sys_nis_syscall - .word sys_nis_syscall, sys_llseek, sys_mlock, sys_munlock, sys_mlockall +/*230*/ .word sys_select, sys_nis_syscall, sys_nis_syscall, sys_stime, sys_statfs64 + .word sys_fstatfs64, sys_llseek, sys_mlock, sys_munlock, sys_mlockall /*240*/ .word sys_munlockall, sys_sched_setparam, sys_sched_getparam, sys_sched_setscheduler, sys_sched_getscheduler .word sys_sched_yield, sys_sched_get_priority_max, sys_sched_get_priority_min, sys_sched_rr_get_interval, sys_nanosleep /*250*/ .word sys64_mremap, sys_sysctl, sys_getsid, sys_fdatasync, sys_nfsservctl --- linux-2.5.73/arch/sparc64/kernel/traps.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/sparc64/kernel/traps.c 2003-06-27 15:56:24.000000000 -0700 @@ -1569,12 +1569,15 @@ void user_instruction_dump (unsigned int printk("\n"); } -void show_trace_raw(struct thread_info *tp, unsigned long ksp) +void show_stack(struct task_struct *tsk, unsigned long *_ksp) { - unsigned long pc, fp, thread_base; + unsigned long pc, fp, thread_base, ksp; + struct thread_info *tp = tsk->thread_info; struct reg_window *rw; int count = 0; + ksp = (unsigned long) _ksp; + if (tp == current_thread_info()) flushw_all(); @@ -1596,17 +1599,17 @@ void show_trace_raw(struct thread_info * void show_trace_task(struct task_struct *tsk) { if (tsk) - show_trace_raw(tsk->thread_info, - tsk->thread_info->ksp); + show_stack(tsk, + (unsigned long *) tsk->thread_info->ksp); } void dump_stack(void) { - unsigned long ksp; + unsigned long *ksp; __asm__ __volatile__("mov %%fp, %0" : "=r" (ksp)); - show_trace_raw(current_thread_info(), ksp); + show_stack(current, ksp); } void die_if_kernel(char *str, struct pt_regs *regs) --- linux-2.5.73/arch/sparc64/lib/rwlock.S 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/sparc64/lib/rwlock.S 2003-06-27 15:56:46.000000000 -0700 @@ -63,5 +63,33 @@ __write_lock: /* %o0 = lock_ptr */ be,pt %icc, 99b membar #StoreLoad | #StoreStore ba,a,pt %xcc, 1b + + .globl __read_trylock +__read_trylock: /* %o0 = lock_ptr */ + ldsw [%o0], %g5 + brlz,pn %g5, 100f + add %g5, 1, %g7 + cas [%o0], %g5, %g7 + cmp %g5, %g7 + bne,pn %icc, __read_trylock + membar #StoreLoad | #StoreStore + retl + mov 1, %o0 + + .globl __write_trylock +__write_trylock: /* %o0 = lock_ptr */ + sethi %hi(0x80000000), %g2 +1: lduw [%o0], %g5 +4: brnz,pn %g5, 100f + or %g5, %g2, %g7 + cas [%o0], %g5, %g7 + cmp %g5, %g7 + bne,pn %icc, 1b + membar #StoreLoad | #StoreStore + retl + mov 1, %o0 +100: retl + mov 0, %o0 + rwlock_impl_end: --- linux-2.5.73/arch/sparc64/mm/fault.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/sparc64/mm/fault.c 2003-06-27 15:56:24.000000000 -0700 @@ -149,16 +149,14 @@ static void unhandled_fault(unsigned lon die_if_kernel("Oops", regs); } -extern void show_trace_raw(struct thread_info *, unsigned long); - static void bad_kernel_pc(struct pt_regs *regs) { - unsigned long ksp; + unsigned long *ksp; printk(KERN_CRIT "OOPS: Bogus kernel PC [%016lx] in fault handler\n", regs->tpc); __asm__("mov %%sp, %0" : "=r" (ksp)); - show_trace_raw(current_thread_info(), ksp); + show_stack(current, ksp); unhandled_fault(regs->tpc, current, regs); } --- linux-2.5.73/arch/sparc64/solaris/fs.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/sparc64/solaris/fs.c 2003-06-27 15:56:24.000000000 -0700 @@ -390,7 +390,7 @@ struct sol_statvfs64 { static int report_statvfs(struct vfsmount *mnt, struct inode *inode, u32 buf) { - struct statfs s; + struct kstatfs s; int error; struct sol_statvfs *ss = (struct sol_statvfs *)A(buf); @@ -424,7 +424,7 @@ static int report_statvfs(struct vfsmoun static int report_statvfs64(struct vfsmount *mnt, struct inode *inode, u32 buf) { - struct statfs s; + struct kstatfs s; int error; struct sol_statvfs64 *ss = (struct sol_statvfs64 *)A(buf); --- linux-2.5.73/arch/sparc/Kconfig 2003-06-22 12:04:44.000000000 -0700 +++ 25/arch/sparc/Kconfig 2003-06-27 15:56:24.000000000 -0700 @@ -481,33 +481,8 @@ endif source "drivers/isdn/Kconfig" - -menu "SCSI support" - -config SCSI - tristate "SCSI support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - source "drivers/scsi/Kconfig" -endmenu - source "drivers/fc4/Kconfig" source "net/Kconfig" --- linux-2.5.73/arch/sparc/kernel/process.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/sparc/kernel/process.c 2003-06-27 15:56:24.000000000 -0700 @@ -287,17 +287,14 @@ void show_regs(struct pt_regs *r) rw->ins[4], rw->ins[5], rw->ins[6], rw->ins[7]); } -void show_trace_task(struct task_struct *tsk) +void show_stack(struct task_struct *tsk, unsigned long *_ksp) { unsigned long pc, fp; unsigned long task_base = (unsigned long) tsk; struct reg_window *rw; int count = 0; - if (!tsk) - return; - - fp = tsk->thread_info->ksp; + fp = (unsigned long) _ksp; do { /* Bogus frame pointer? */ if (fp < (task_base + sizeof(struct task_struct)) || @@ -311,6 +308,13 @@ void show_trace_task(struct task_struct printk("\n"); } +void show_trace_task(struct task_struct *tsk) +{ + if (tsk) + show_stack(tsk, + (unsigned long *) tsk->thread_info->ksp); +} + /* * Note: sparc64 has a pretty intricated thread_saved_pc, check it out. */ --- linux-2.5.73/arch/sparc/kernel/systbls.S 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/sparc/kernel/systbls.S 2003-06-27 15:56:24.000000000 -0700 @@ -64,9 +64,9 @@ sys_call_table: /*215*/ .long sys_ipc, sys_sigreturn, sys_clone, sys_nis_syscall, sys_adjtimex /*220*/ .long sys_sigprocmask, sys_ni_syscall, sys_delete_module, sys_ni_syscall, sys_getpgid /*225*/ .long sys_bdflush, sys_sysfs, sys_nis_syscall, sys_setfsuid16, sys_setfsgid16 -/*230*/ .long sys_select, sys_time, sys_nis_syscall, sys_stime, sys_nis_syscall +/*230*/ .long sys_select, sys_time, sys_nis_syscall, sys_stime, sys_statfs64 /* "We are the Knights of the Forest of Ni!!" */ -/*235*/ .long sys_nis_syscall, sys_llseek, sys_mlock, sys_munlock, sys_mlockall +/*235*/ .long sys_fstatfs64, sys_llseek, sys_mlock, sys_munlock, sys_mlockall /*240*/ .long sys_munlockall, sys_sched_setparam, sys_sched_getparam, sys_sched_setscheduler, sys_sched_getscheduler /*245*/ .long sys_sched_yield, sys_sched_get_priority_max, sys_sched_get_priority_min, sys_sched_rr_get_interval, sys_nanosleep /*250*/ .long sparc_mremap, sys_sysctl, sys_getsid, sys_fdatasync, sys_nfsservctl --- linux-2.5.73/arch/sparc/Makefile 2003-06-14 12:17:58.000000000 -0700 +++ 25/arch/sparc/Makefile 2003-06-27 15:56:24.000000000 -0700 @@ -52,7 +52,9 @@ CORE_Y += kernel/ mm/ fs/ ipc/ security CORE_Y := $(patsubst %/, %/built-in.o, $(CORE_Y)) DRIVERS_Y := $(patsubst %/, %/built-in.o, $(drivers-y)) NET_Y := $(patsubst %/, %/built-in.o, $(net-y)) -LIBS_Y := $(patsubst %/, %/lib.a, $(libs-y)) +LIBS_Y1 := $(patsubst %/, %/lib.a, $(libs-y)) +LIBS_Y2 := $(patsubst %/, %/built-in.o, $(libs-y)) +LIBS_Y := $(LIBS_Y1) $(LIBS_Y2) export INIT_Y CORE_Y DRIVERS_Y NET_Y LIBS_Y HEAD_Y # Default target --- linux-2.5.73/arch/v850/Kconfig 2003-06-22 12:04:44.000000000 -0700 +++ 25/arch/v850/Kconfig 2003-06-27 15:56:24.000000000 -0700 @@ -265,15 +265,6 @@ menu "Disk device support" source "drivers/ide/Kconfig" -config SCSI - tristate "SCSI device support" - help - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - source "drivers/scsi/Kconfig" endmenu --- linux-2.5.73/arch/x86_64/boot/compressed/head.S 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/x86_64/boot/compressed/head.S 2003-06-27 15:56:32.000000000 -0700 @@ -26,6 +26,7 @@ .code32 .text +#define IN_BOOTLOADER #include #include --- linux-2.5.73/arch/x86_64/boot/compressed/misc.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/x86_64/boot/compressed/misc.c 2003-06-27 15:56:32.000000000 -0700 @@ -9,6 +9,7 @@ * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996 */ +#define IN_BOOTLOADER #include "miscsetup.h" #include --- linux-2.5.73/arch/x86_64/ia32/ia32_binfmt.c 2003-06-14 12:17:56.000000000 -0700 +++ 25/arch/x86_64/ia32/ia32_binfmt.c 2003-06-27 15:56:24.000000000 -0700 @@ -30,10 +30,12 @@ #define AT_SYSINFO 32 #define AT_SYSINFO_EHDR 33 +#if 0 /* disabled for now because the code has still problems */ #define ARCH_DLINFO do { \ NEW_AUX_ENT(AT_SYSINFO, (u32)(u64)VSYSCALL32_VSYSCALL); \ NEW_AUX_ENT(AT_SYSINFO_EHDR, VSYSCALL32_BASE); \ } while(0) +#endif struct file; struct elf_phdr; --- linux-2.5.73/arch/x86_64/ia32/ia32_ioctl.c 2003-06-14 12:18:22.000000000 -0700 +++ 25/arch/x86_64/ia32/ia32_ioctl.c 2003-06-27 15:56:24.000000000 -0700 @@ -552,7 +552,7 @@ static int do_usbdevfs_reapurb(unsigned set_fs(old_fs); if (err >= 0 && - put_user(((u32)(long)kptr), compat_ptr(arg))) + put_user((u32)(u64)kptr, (u32 *)arg)) err = -EFAULT; return err; --- linux-2.5.73/arch/x86_64/ia32/ptrace32.c 2003-06-14 12:18:05.000000000 -0700 +++ 25/arch/x86_64/ia32/ptrace32.c 2003-06-27 15:56:24.000000000 -0700 @@ -210,6 +210,7 @@ static struct task_struct *find_target(i return child; } out: + if (child) put_task_struct(child); return NULL; --- linux-2.5.73/arch/x86_64/ia32/sys_ia32.c 2003-06-16 22:32:20.000000000 -0700 +++ 25/arch/x86_64/ia32/sys_ia32.c 2003-06-27 15:56:24.000000000 -0700 @@ -946,10 +946,30 @@ sys32_sysinfo(struct sysinfo32 *info) struct sysinfo s; int ret; mm_segment_t old_fs = get_fs (); + int bitcount = 0; set_fs (KERNEL_DS); ret = sys_sysinfo(&s); set_fs (old_fs); + + /* Check to see if any memory value is too large for 32-bit and scale + * down if needed + */ + if ((s.totalram >> 32) || (s.totalswap >> 32)) { + while (s.mem_unit < PAGE_SIZE) { + s.mem_unit <<= 1; + bitcount++; + } + s.totalram >>= bitcount; + s.freeram >>= bitcount; + s.sharedram >>= bitcount; + s.bufferram >>= bitcount; + s.totalswap >>= bitcount; + s.freeswap >>= bitcount; + s.totalhigh >>= bitcount; + s.freehigh >>= bitcount; + } + if (verify_area(VERIFY_WRITE, info, sizeof(struct sysinfo32)) || __put_user (s.uptime, &info->uptime) || __put_user (s.loads[0], &info->loads[0]) || --- linux-2.5.73/arch/x86_64/Kconfig 2003-06-22 12:04:44.000000000 -0700 +++ 25/arch/x86_64/Kconfig 2003-06-27 15:56:24.000000000 -0700 @@ -407,33 +407,8 @@ source "drivers/block/Kconfig" source "drivers/ide/Kconfig" - -menu "SCSI device support" - -config SCSI - tristate "SCSI device support" - ---help--- - If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or - any other SCSI device under Linux, say Y and make sure that you know - the name of your SCSI host adapter (the card inside your computer - that "speaks" the SCSI protocol, also called SCSI controller), - because you will be asked for it. - - You also need to say Y here if you want support for the parallel - port version of the 100 MB IOMEGA ZIP drive. - - This driver is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module will be called scsi_mod. If you want to compile it as - a module, say M here and read and - . However, do not compile this as a - module if your root file system (the one containing the directory /) - is located on a SCSI device. - source "drivers/scsi/Kconfig" -endmenu - source "drivers/md/Kconfig" source "drivers/telephony/Kconfig" --- linux-2.5.73/arch/x86_64/kernel/acpi/boot.c 2003-06-14 12:18:00.000000000 -0700 +++ 25/arch/x86_64/kernel/acpi/boot.c 2003-06-27 15:56:24.000000000 -0700 @@ -100,7 +100,7 @@ acpi_parse_madt ( if (madt->lapic_address) acpi_lapic_addr = (u64) madt->lapic_address; - printk(KERN_INFO PREFIX "Local APIC address 0x%08x\n", + printk(KERN_INFO PREFIX "Local APIC address 0x%016x\n", madt->lapic_address); return 0; --- linux-2.5.73/arch/x86_64/kernel/i8259.c 2003-06-14 12:17:59.000000000 -0700 +++ 25/arch/x86_64/kernel/i8259.c 2003-06-27 15:56:24.000000000 -0700 @@ -26,9 +26,6 @@ #include -/* When we have things working, we can switch to always use - IOAPIC. --pavel */ - /* * Common place to define all x86 IRQ vectors * --- linux-2.5.73/arch/x86_64/kernel/module.c 2003-06-14 12:18:33.000000000 -0700 +++ 25/arch/x86_64/kernel/module.c 2003-06-27 15:56:24.000000000 -0700 @@ -31,9 +31,6 @@ #define DEBUGP(fmt...) -/* TODO this should be in vmlist, but we must fix get_vm_area first to - handle out of bounds entries properly. - Also need to fix /proc/kcore, /dev/kmem */ static struct vm_struct *mod_vmlist; void module_free(struct module *mod, void *module_region) --- linux-2.5.73/arch/x86_64/kernel/nmi.c 2003-06-16 22:32:20.000000000 -0700 +++ 25/arch/x86_64/kernel/nmi.c 2003-06-27 15:56:24.000000000 -0700 @@ -34,7 +34,7 @@ extern void default_do_nmi(struct pt_regs *); -unsigned int nmi_watchdog = NMI_LOCAL_APIC; +unsigned int nmi_watchdog = NMI_IO_APIC; static unsigned int nmi_hz = HZ; unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */ int nmi_watchdog_disabled; @@ -153,17 +153,19 @@ void enable_lapic_nmi_watchdog(void) #include +static int nmi_pm_active; /* nmi_active before suspend */ + static int lapic_nmi_suspend(struct sys_device *dev, u32 state) { + nmi_pm_active = nmi_active; disable_lapic_nmi_watchdog(); return 0; } static int lapic_nmi_resume(struct sys_device *dev) { -#if 0 + if (nmi_pm_active > 0) enable_lapic_nmi_watchdog(); -#endif return 0; } @@ -235,6 +237,8 @@ void setup_apic_nmi_watchdog (void) case X86_VENDOR_AMD: if (boot_cpu_data.x86 < 6) return; + if (strstr(boot_cpu_data.x86_model_id, "Screwdriver")) + return; setup_k7_watchdog(); break; default: --- linux-2.5.73/arch/x86_64/kernel/pci-gart.c 2003-06-16 22:32:20.000000000 -0700 +++ 25/arch/x86_64/kernel/pci-gart.c 2003-06-27 15:56:24.000000000 -0700 @@ -236,7 +236,7 @@ void dump_leak(void) static int dump; if (dump || !iommu_leak_tab) return; dump = 1; - show_stack(NULL); + show_stack(NULL,NULL); /* Very crude. dump some from the end of the table too */ printk("Dumping %d pages from end of IOMMU:\n", iommu_leak_pages); for (i = 0; i < iommu_leak_pages; i+=2) { --- linux-2.5.73/arch/x86_64/kernel/suspend.c 2003-06-14 12:18:21.000000000 -0700 +++ 25/arch/x86_64/kernel/suspend.c 2003-06-27 15:56:24.000000000 -0700 @@ -121,11 +121,12 @@ void fix_processor_context(void) struct tss_struct * t = init_tss + cpu; set_tss_desc(cpu,t); /* This just modifies memory; should not be neccessary. But... This is neccessary, because 386 hardware has concept of busy TSS or some similar stupidity. */ - ((struct n_desc_struct *) &cpu_gdt_table[cpu][GDT_ENTRY_TSS])->b &= 0xfffffdff; + + cpu_gdt_table[cpu][GDT_ENTRY_TSS].type = 9; syscall_init(); /* This sets MSR_*STAR and related */ load_TR_desc(); /* This does ltr */ - load_LDT(¤t->mm->context); /* This does lldt */ + load_LDT(¤t->active_mm->context); /* This does lldt */ /* * Now maybe reload the debug registers --- linux-2.5.73/arch/x86_64/kernel/time.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/arch/x86_64/kernel/time.c 2003-06-27 15:56:24.000000000 -0700 @@ -47,6 +47,7 @@ unsigned long hpet_period; /* fsecs / unsigned long hpet_tick; /* HPET clocks / interrupt */ unsigned long vxtime_hz = 1193182; int report_lost_ticks; /* command line option */ +unsigned long long monotonic_base; struct vxtime_data __vxtime __section_vxtime; /* for vsyscalls */ @@ -137,6 +138,18 @@ int do_settimeofday(struct timespec *tv) tv->tv_sec--; } + wall_to_monotonic.tv_sec += xtime.tv_sec - tv->tv_sec; + wall_to_monotonic.tv_nsec += xtime.tv_nsec - tv->tv_nsec; + + if (wall_to_monotonic.tv_nsec > NSEC_PER_SEC) { + wall_to_monotonic.tv_nsec -= NSEC_PER_SEC; + wall_to_monotonic.tv_sec++; + } + if (wall_to_monotonic.tv_nsec < 0) { + wall_to_monotonic.tv_nsec += NSEC_PER_SEC; + wall_to_monotonic.tv_sec--; + } + xtime.tv_sec = tv->tv_sec; xtime.tv_nsec = tv->tv_nsec; @@ -219,6 +232,47 @@ static void set_rtc_mmss(unsigned long n spin_unlock(&rtc_lock); } + +/* monotonic_clock(): returns # of nanoseconds passed since time_init() + * Note: This function is required to return accurate + * time even in the absence of multiple timer ticks. + */ +unsigned long long monotonic_clock(void) +{ + unsigned long seq; + u32 last_offset, this_offset, offset; + unsigned long long base; + + if (vxtime.mode == VXTIME_HPET) { + do { + seq = read_seqbegin(&xtime_lock); + + last_offset = vxtime.last; + base = monotonic_base; + this_offset = hpet_readl(HPET_T0_CMP) - hpet_tick; + + } while (read_seqretry(&xtime_lock, seq)); + offset = (this_offset - last_offset); + offset *=(NSEC_PER_SEC/HZ)/hpet_tick; + return base + offset; + }else{ + do { + seq = read_seqbegin(&xtime_lock); + + last_offset = vxtime.last_tsc; + base = monotonic_base; + } while (read_seqretry(&xtime_lock, seq)); + sync_core(); + rdtscll(this_offset); + offset = (this_offset - last_offset)*1000/cpu_khz; + return base + offset; + } + + +} +EXPORT_SYMBOL(monotonic_clock); + + static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) { static unsigned long rtc_update = 0; @@ -253,6 +307,9 @@ static irqreturn_t timer_interrupt(int i lost = (offset - vxtime.last) / hpet_tick - 1; } + monotonic_base += + (offset - vxtime.last)*(NSEC_PER_SEC/HZ) / hpet_tick; + vxtime.last = offset; } else { offset = (((tsc - vxtime.last_tsc) * @@ -266,6 +323,8 @@ static irqreturn_t timer_interrupt(int i offset %= (USEC_PER_SEC / HZ); } + monotonic_base += (tsc - vxtime.last_tsc)*1000000/cpu_khz ; + vxtime.last_tsc = tsc - vxtime.quot * delay / vxtime.tsc_quot; if ((((tsc - vxtime.last_tsc) * @@ -544,6 +603,9 @@ void __init time_init(void) xtime.tv_sec = get_cmos_time(); xtime.tv_nsec = 0; + wall_to_monotonic.tv_sec = -xtime.tv_sec; + wall_to_monotonic.tv_nsec = -xtime.tv_nsec; + if (!hpet_init()) { vxtime_hz = (1000000000000000L + hpet_period / 2) / hpet_period; --- linux-2.5.73/arch/x86_64/kernel/traps.c 2003-06-16 22:32:20.000000000 -0700 +++ 25/arch/x86_64/kernel/traps.c 2003-06-27 15:56:24.000000000 -0700 @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -206,7 +207,7 @@ void show_trace_task(struct task_struct show_trace((unsigned long *)rsp); } -void show_stack(unsigned long * rsp) +void show_stack(struct task_struct *tsk, unsigned long * rsp) { unsigned long *stack; int i; @@ -214,7 +215,7 @@ void show_stack(unsigned long * rsp) unsigned long *irqstack_end = (unsigned long *) (cpu_pda[cpu].irqstackptr); unsigned long *irqstack = (unsigned long *) (cpu_pda[cpu].irqstackptr - IRQSTACKSIZE); - // debugging aid: "show_stack(NULL);" prints the + // debugging aid: "show_stack(NULL, NULL);" prints the // back trace for this cpu. if(rsp==NULL) @@ -269,7 +270,7 @@ void show_registers(struct pt_regs *regs if (in_kernel) { printk("Stack: "); - show_stack((unsigned long*)rsp); + show_stack(NULL, (unsigned long*)rsp); printk("\nCode: "); if(regs->rip < PAGE_OFFSET) @@ -831,3 +832,4 @@ void __init trap_init(void) */ cpu_init(); } + --- linux-2.5.73/Documentation/cpu-freq/user-guide.txt 2003-06-14 12:17:57.000000000 -0700 +++ 25/Documentation/cpu-freq/user-guide.txt 2003-06-27 15:56:22.000000000 -0700 @@ -56,19 +56,15 @@ AMD mobile K6-3+ AMD mobile Duron AMD mobile Athlon Cyrix Media GXm -Intel mobile PIII [*] and Intel mobile PIII-M on certain chipsets +Intel mobile PIII and Intel mobile PIII-M on certain chipsets Intel Pentium 4, Intel Xeon Intel Pentium M (Centrino) National Semiconductors Geode GX Transmeta Crusoe VIA Cyrix 3 / C3 -various processors on some ACPI 2.0-compatible systems [**] +various processors on some ACPI 2.0-compatible systems [*] -[*] only certain Intel mobile PIII processors are supported. If you -know that you own a speedstep-capable processor, pass the option -"speedstep_coppermine=1" to the module speedstep.o - -[**] Only if "ACPI Processor Performance States" are available +[*] Only if "ACPI Processor Performance States" are available to the ACPI<->BIOS interface. --- linux-2.5.73/Documentation/DocBook/gadget.tmpl 2003-06-14 12:18:21.000000000 -0700 +++ 25/Documentation/DocBook/gadget.tmpl 2003-06-27 15:56:22.000000000 -0700 @@ -6,31 +6,32 @@ 02 June 2003 - Permission is granted to copy, distribute, and/or modify - this document under the terms of the GNU Free Documentation - License, version 1.2, or any later version published by the - Free Software Foundation; with the Invariant Sections being - the "GNU Free Documentation License", - no Front-Cover Texts, - and - no Back-Cover Texts. - - - This documentation is distributed in the hope that it will be - useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Free Documentation License for more details. - - - Note that certain sections of this document are merged - into Linux kernel source code. - That content is the bulk of - and - , - where the "GNU Free Documentation License" is identified - as an alternate licence for its documentation. - - + + This documentation is free software; you can redistribute + it and/or modify it under the terms of the GNU General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later + version. + + + + This program is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU General Public License for more details. + + + + You should have received a copy of the GNU General Public + License along with this program; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, + MA 02111-1307 USA + + + + For more details see the file COPYING in the source + distribution of Linux. + 2003 @@ -325,9 +326,10 @@ the "chunky" nature of USB messages: I/ of one or more "packets", and packet boundaries are visible to drivers. Compared to RS-232 serial protocols, USB resembles synchronous protocols like HDLC -(N bytes per frame, multipoint addressing from the host) +(N bytes per frame, multipoint addressing, host as the primary +station and devices as secondary stations) more than asynchronous ones -(tty style, like 8 bytes, no parity, one stop bit). +(tty style: 8 data bits per frame, no parity, one stop bit). So for example the controller drivers won't buffer two single byte writes into a single two-byte USB IN packet, although gadget drivers may do so when they implement @@ -528,438 +530,6 @@ over time, as this driver framework evol - -GNU Free Documentation License -Version 1.2, November 2002 - - - -PREAMBLE - -The purpose of this License is to make a manual, textbook, or -other functional and useful document "free" in the sense of freedom: to -assure everyone the effective freedom to copy and redistribute it, with -or without modifying it, either commercially or noncommercially. -Secondarily, this License preserves for the author and publisher a way -to get credit for their work, while not being considered responsible for -modifications made by others. - -This License is a kind of "copyleft", which means that derivative -works of the document must themselves be free in the same sense. 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- with the Invariant Sections being LIST THEIR TITLES, with the - Front-Cover Texts being LIST, and with the Back-Cover Texts being LIST. -
- -If you have Invariant Sections without Cover Texts, or some other -combination of the three, merge those two alternatives to suit the -situation. - -If your document contains nontrivial examples of program code, we -recommend releasing these examples in parallel under your choice of free -software license, such as the GNU General Public License, to permit -their use in free software. - - - "); - ip->dev->dev_addr[0] = 0x8; - ip->dev->dev_addr[1] = 0x0; - ip->dev->dev_addr[2] = 0x69; - ip->dev->dev_addr[3] = 0x11; - ip->dev->dev_addr[4] = 0x34; - ip->dev->dev_addr[5] = 0x60; - } - else { - long simple_strtol(const char *,char **,unsigned int); - - mac = simple_strtol(io7eaddr, (char **)0, 16); - ip->dev->dev_addr[0] = (mac >> 40) & 0xff; - ip->dev->dev_addr[1] = (mac >> 32) & 0xff; - ip->dev->dev_addr[2] = (mac >> 24) & 0xff; - ip->dev->dev_addr[3] = (mac >> 16) & 0xff; - ip->dev->dev_addr[4] = (mac >> 8) & 0xff; - ip->dev->dev_addr[5] = mac & 0xff; - } -} -#endif - /* * Ok, this is hosed by design. It's necessary to know what machine the * NIC is in in order to know how to read the NIC address. We also have @@ -460,30 +384,15 @@ static void ioc3_get_eaddr_sn(struct ioc */ static void ioc3_get_eaddr(struct ioc3_private *ip) { - void (*do_get_eaddr)(struct ioc3_private *ip) = NULL; int i; - /* - * We should also use this code for PCI cards, no matter what host - * machine but how to know that we're a PCI card? - */ -#ifdef CONFIG_SGI_IP27 - do_get_eaddr = ioc3_get_eaddr_nic; -#endif -#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_SGI_SN2) - do_get_eaddr = ioc3_get_eaddr_sn; -#endif - if (!do_get_eaddr) { - printk(KERN_ERR "Don't know how to read MAC address of this " - "IOC3 NIC\n"); - return; - } + ioc3_get_eaddr_nic(ip); printk("Ethernet address is "); for (i = 0; i < 6; i++) { printk("%02x", ip->dev->dev_addr[i]); - if (i < 7) + if (i < 5) printk(":"); } printk(".\n"); @@ -588,7 +497,7 @@ ioc3_rx(struct ioc3_private *ip) ip->stats.rx_frame_errors++; next: ip->rx_skbs[n_entry] = new_skb; - rxr[n_entry] = cpu_to_be32((0xa5UL << 56) | + rxr[n_entry] = cpu_to_be64((0xa5UL << 56) | ((unsigned long) rxb & TO_PHYS_MASK)); rxb->w0 = 0; /* Clear valid flag */ n_entry = (n_entry + 1) & 511; /* Update erpir */ @@ -1550,7 +1459,7 @@ static int __devinit ioc3_probe(struct p } ip->regs = ioc3; -#ifdef CONFIG_SERIAL +#ifdef CONFIG_SERIAL_8250 ioc3_serial_probe(pdev, ioc3); #endif @@ -1613,6 +1522,7 @@ static void __devexit ioc3_remove_one (s struct ioc3_private *ip = dev->priv; struct ioc3 *ioc3 = ip->regs; + unregister_netdev(dev); iounmap(ioc3); pci_release_regions(pdev); kfree(dev); @@ -1844,9 +1754,6 @@ static int ioc3_ioctl(struct net_device return -EFAULT; return 0; } else if (ecmd.cmd == ETHTOOL_SSET) { - if (!capable(CAP_NET_ADMIN)) - return -EPERM; - /* Verify the settings we care about. */ if (ecmd.autoneg != AUTONEG_ENABLE && ecmd.autoneg != AUTONEG_DISABLE) --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/net/irda/au1k_ir.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,868 @@ +/* + * + * Alchemy Semi Au1000 IrDA driver + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * + */ + +#ifndef __mips__ +#error This driver only works with MIPS architectures! +#endif + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include "net/irda/au1000_ircc.h" + +static int au1k_irda_net_init(struct net_device *); +static int au1k_irda_start(struct net_device *); +static int au1k_irda_stop(struct net_device *dev); +static int au1k_irda_hard_xmit(struct sk_buff *, struct net_device *); +static int au1k_irda_rx(struct net_device *); +static void au1k_irda_interrupt(int, void *, struct pt_regs *); +static void au1k_tx_timeout(struct net_device *); +static struct net_device_stats *au1k_irda_stats(struct net_device *); +static int au1k_irda_ioctl(struct net_device *, struct ifreq *, int); +static int au1k_irda_set_speed(struct net_device *dev, int speed); + +static void *dma_alloc(size_t, dma_addr_t *); +static void dma_free(void *, size_t); + +static int qos_mtt_bits = 0x07; /* 1 ms or more */ +static struct net_device *ir_devs[NUM_IR_IFF]; +static char version[] __devinitdata = + "au1k_ircc:1.0 ppopov@mvista.com\n"; + +#define RUN_AT(x) (jiffies + (x)) + +static spinlock_t ir_lock = SPIN_LOCK_UNLOCKED; + +/* + * IrDA peripheral bug. You have to read the register + * twice to get the right value. + */ +u32 read_ir_reg(u32 addr) +{ + readl(addr); + return readl(addr); +} + + +/* + * Buffer allocation/deallocation routines. The buffer descriptor returned + * has the virtual and dma address of a buffer suitable for + * both, receive and transmit operations. + */ +static db_dest_t *GetFreeDB(struct au1k_private *aup) +{ + db_dest_t *pDB; + pDB = aup->pDBfree; + + if (pDB) { + aup->pDBfree = pDB->pnext; + } + return pDB; +} + +static void ReleaseDB(struct au1k_private *aup, db_dest_t *pDB) +{ + db_dest_t *pDBfree = aup->pDBfree; + if (pDBfree) + pDBfree->pnext = pDB; + aup->pDBfree = pDB; +} + + +/* + DMA memory allocation, derived from pci_alloc_consistent. + However, the Au1000 data cache is coherent (when programmed + so), therefore we return KSEG0 address, not KSEG1. +*/ +static void *dma_alloc(size_t size, dma_addr_t * dma_handle) +{ + void *ret; + int gfp = GFP_ATOMIC | GFP_DMA; + + ret = (void *) __get_free_pages(gfp, get_order(size)); + + if (ret != NULL) { + memset(ret, 0, size); + *dma_handle = virt_to_bus(ret); + ret = KSEG0ADDR(ret); + } + return ret; +} + + +static void dma_free(void *vaddr, size_t size) +{ + vaddr = KSEG0ADDR(vaddr); + free_pages((unsigned long) vaddr, get_order(size)); +} + + +static void +setup_hw_rings(struct au1k_private *aup, u32 rx_base, u32 tx_base) +{ + int i; + for (i=0; irx_ring[i] = (volatile ring_dest_t *) + (rx_base + sizeof(ring_dest_t)*i); + } + for (i=0; itx_ring[i] = (volatile ring_dest_t *) + (tx_base + sizeof(ring_dest_t)*i); + } +} + + +/* + * Device has already been stopped at this point. + */ +static void au1k_irda_net_uninit(struct net_device *dev) +{ + dev->hard_start_xmit = NULL; + dev->open = NULL; + dev->stop = NULL; + dev->do_ioctl = NULL; + dev->get_stats = NULL; + dev->priv = NULL; +} + + +static int au1k_irda_init(void) +{ + static unsigned version_printed = 0; + struct net_device *dev; + int err; + + if (version_printed++ == 0) printk(version); + + rtnl_lock(); + dev = dev_alloc("irda%d", &err); + if (dev) { + dev->irq = AU1000_IRDA_RX_INT; /* TX has its own interrupt */ + dev->init = au1k_irda_net_init; + dev->uninit = au1k_irda_net_uninit; + err = register_netdevice(dev); + + if (err) + kfree(dev); + else + ir_devs[0] = dev; + printk(KERN_INFO "IrDA: Registered device %s\n", dev->name); + } + rtnl_unlock(); + return err; +} + +static int au1k_irda_init_iobuf(iobuff_t *io, int size) +{ + io->head = kmalloc(size, GFP_KERNEL); + if (io->head != NULL) { + io->truesize = size; + io->in_frame = FALSE; + io->state = OUTSIDE_FRAME; + io->data = io->head; + } + return io->head ? 0 : -ENOMEM; +} + +static int au1k_irda_net_init(struct net_device *dev) +{ + struct au1k_private *aup = NULL; + int i, retval = 0, err; + db_dest_t *pDB, *pDBfree; + unsigned long temp; + + dev->priv = kmalloc(sizeof(struct au1k_private), GFP_KERNEL); + if (dev->priv == NULL) { + retval = -ENOMEM; + goto out; + } + memset(dev->priv, 0, sizeof(struct au1k_private)); + aup = dev->priv; + + err = au1k_irda_init_iobuf(&aup->rx_buff, 14384); + if (err) + goto out; + + dev->open = au1k_irda_start; + dev->hard_start_xmit = au1k_irda_hard_xmit; + dev->stop = au1k_irda_stop; + dev->get_stats = au1k_irda_stats; + dev->do_ioctl = au1k_irda_ioctl; + dev->tx_timeout = au1k_tx_timeout; + + irda_device_setup(dev); + irda_init_max_qos_capabilies(&aup->qos); + + /* The only value we must override it the baudrate */ + aup->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| + IR_115200|IR_576000 |(IR_4000000 << 8); + + aup->qos.min_turn_time.bits = qos_mtt_bits; + irda_qos_bits_to_value(&aup->qos); + + + /* Tx ring follows rx ring + 512 bytes */ + /* we need a 1k aligned buffer */ + aup->rx_ring[0] = (ring_dest_t *) + dma_alloc(2*MAX_NUM_IR_DESC*(sizeof(ring_dest_t)), &temp); + + /* allocate the data buffers */ + aup->db[0].vaddr = + (void *)dma_alloc(MAX_BUF_SIZE * 2*NUM_IR_DESC, &temp); + if (!aup->db[0].vaddr || !aup->rx_ring[0]) { + retval = -ENOMEM; + goto out; + } + + setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512); + + pDBfree = NULL; + pDB = aup->db; + for (i=0; i<(2*NUM_IR_DESC); i++) { + pDB->pnext = pDBfree; + pDBfree = pDB; + pDB->vaddr = + (u32 *)((unsigned)aup->db[0].vaddr + MAX_BUF_SIZE*i); + pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); + pDB++; + } + aup->pDBfree = pDBfree; + + /* attach a data buffer to each descriptor */ + for (i=0; irx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); + aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); + aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); + aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); + aup->rx_db_inuse[i] = pDB; + } + for (i=0; itx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); + aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); + aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); + aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); + aup->tx_ring[i]->count_0 = 0; + aup->tx_ring[i]->count_1 = 0; + aup->tx_ring[i]->flags = 0; + aup->tx_db_inuse[i] = pDB; + } + return 0; + +out: + if (aup->db[0].vaddr) + dma_free((void *)aup->db[0].vaddr, + MAX_BUF_SIZE * 2*NUM_IR_DESC); + if (aup->rx_ring[0]) + kfree((void *)aup->rx_ring[0]); + if (aup->rx_buff.head) + kfree(aup->rx_buff.head); + if (dev->priv != NULL) + kfree(dev->priv); + unregister_netdevice(dev); + printk(KERN_ERR "%s: au1k_init_module failed. Returns %d\n", + dev->name, retval); + return retval; +} + + +static int au1k_init(struct net_device *dev) +{ + struct au1k_private *aup = (struct au1k_private *) dev->priv; + int i; + u32 control; + u32 ring_address; + + /* bring the device out of reset */ + control = 0xe; /* coherent, clock enable, one half system clock */ + +#ifndef CONFIG_CPU_LITTLE_ENDIAN + control |= 1; +#endif + aup->tx_head = 0; + aup->tx_tail = 0; + aup->rx_head = 0; + + for (i=0; irx_ring[i]->flags = AU_OWN; + } + + writel(control, IR_INTERFACE_CONFIG); + au_sync_delay(10); + + writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE); /* disable PHY */ + au_sync_delay(1); + + writel(MAX_BUF_SIZE, IR_MAX_PKT_LEN); + + ring_address = (u32)virt_to_phys((void *)aup->rx_ring[0]); + writel(ring_address >> 26, IR_RING_BASE_ADDR_H); + writel((ring_address >> 10) & 0xffff, IR_RING_BASE_ADDR_L); + + writel(RING_SIZE_64<<8 | RING_SIZE_64<<12, IR_RING_SIZE); + + writel(1<<2 | IR_ONE_PIN, IR_CONFIG_2); /* 48MHz */ + writel(0, IR_RING_ADDR_CMPR); + + au1k_irda_set_speed(dev, 9600); + return 0; +} + +static int au1k_irda_start(struct net_device *dev) +{ + int retval; + char hwname[32]; + struct au1k_private *aup = (struct au1k_private *) dev->priv; + + MOD_INC_USE_COUNT; + + if ((retval = au1k_init(dev))) { + printk(KERN_ERR "%s: error in au1k_init\n", dev->name); + MOD_DEC_USE_COUNT; + return retval; + } + + if ((retval = request_irq(AU1000_IRDA_TX_INT, &au1k_irda_interrupt, + 0, dev->name, dev))) { + printk(KERN_ERR "%s: unable to get IRQ %d\n", + dev->name, dev->irq); + MOD_DEC_USE_COUNT; + return retval; + } + if ((retval = request_irq(AU1000_IRDA_RX_INT, &au1k_irda_interrupt, + 0, dev->name, dev))) { + free_irq(AU1000_IRDA_TX_INT, dev); + printk(KERN_ERR "%s: unable to get IRQ %d\n", + dev->name, dev->irq); + MOD_DEC_USE_COUNT; + return retval; + } + + /* Give self a hardware name */ + sprintf(hwname, "Au1000 SIR/FIR"); + aup->irlap = irlap_open(dev, &aup->qos, hwname); + netif_start_queue(dev); + + writel(read_ir_reg(IR_CONFIG_2) | 1<<8, IR_CONFIG_2); /* int enable */ + + aup->timer.expires = RUN_AT((3*HZ)); + aup->timer.data = (unsigned long)dev; + return 0; +} + +static int au1k_irda_stop(struct net_device *dev) +{ + struct au1k_private *aup = (struct au1k_private *) dev->priv; + + /* disable interrupts */ + writel(read_ir_reg(IR_CONFIG_2) & ~(1<<8), IR_CONFIG_2); + writel(0, IR_CONFIG_1); + writel(0, IR_INTERFACE_CONFIG); /* disable clock */ + au_sync(); + + if (aup->irlap) { + irlap_close(aup->irlap); + aup->irlap = NULL; + } + + netif_stop_queue(dev); + del_timer(&aup->timer); + + /* disable the interrupt */ + free_irq(AU1000_IRDA_TX_INT, dev); + free_irq(AU1000_IRDA_RX_INT, dev); + MOD_DEC_USE_COUNT; + return 0; +} + +static void __exit au1k_irda_exit(void) +{ + struct net_device *dev = ir_devs[0]; + struct au1k_private *aup = (struct au1k_private *) dev->priv; + + if (!dev) { + printk(KERN_ERR "au1k_ircc no dev found\n"); + return; + } + if (aup->db[0].vaddr) { + dma_free((void *)aup->db[0].vaddr, + MAX_BUF_SIZE * 2*NUM_IR_DESC); + aup->db[0].vaddr = 0; + } + if (aup->rx_ring[0]) { + dma_free((void *)aup->rx_ring[0], + 2*MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); + aup->rx_ring[0] = 0; + } + rtnl_lock(); + unregister_netdevice(dev); + rtnl_unlock(); + ir_devs[0] = 0; +} + + +static inline void +update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len) +{ + struct au1k_private *aup = (struct au1k_private *) dev->priv; + struct net_device_stats *ps = &aup->stats; + + ps->tx_packets++; + ps->tx_bytes += pkt_len; + + if (status & IR_TX_ERROR) { + ps->tx_errors++; + ps->tx_aborted_errors++; + } +} + + +static void au1k_tx_ack(struct net_device *dev) +{ + struct au1k_private *aup = (struct au1k_private *) dev->priv; + volatile ring_dest_t *ptxd; + + ptxd = aup->tx_ring[aup->tx_tail]; + while (!(ptxd->flags & AU_OWN) && (aup->tx_tail != aup->tx_head)) { + update_tx_stats(dev, ptxd->flags, + ptxd->count_1<<8 | ptxd->count_0); + ptxd->count_0 = 0; + ptxd->count_1 = 0; + au_sync(); + + aup->tx_tail = (aup->tx_tail + 1) & (NUM_IR_DESC - 1); + ptxd = aup->tx_ring[aup->tx_tail]; + + if (aup->tx_full) { + aup->tx_full = 0; + netif_wake_queue(dev); + } + } + + if (aup->tx_tail == aup->tx_head) { + if (aup->newspeed) { + au1k_irda_set_speed(dev, aup->newspeed); + aup->newspeed = 0; + } + else { + writel(read_ir_reg(IR_CONFIG_1) & ~IR_TX_ENABLE, + IR_CONFIG_1); + au_sync(); + writel(read_ir_reg(IR_CONFIG_1) | IR_RX_ENABLE, + IR_CONFIG_1); + writel(0, IR_RING_PROMPT); + au_sync(); + } + } +} + + +/* + * Au1000 transmit routine. + */ +static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct au1k_private *aup = (struct au1k_private *) dev->priv; + int speed = irda_get_next_speed(skb); + volatile ring_dest_t *ptxd; + u32 len; + + u32 flags; + db_dest_t *pDB; + + if (speed != aup->speed && speed != -1) { + aup->newspeed = speed; + } + + if ((skb->len == 0) && (aup->newspeed)) { + if (aup->tx_tail == aup->tx_head) { + au1k_irda_set_speed(dev, speed); + aup->newspeed = 0; + } + dev_kfree_skb(skb); + return 0; + } + + ptxd = aup->tx_ring[aup->tx_head]; + flags = ptxd->flags; + + if (flags & AU_OWN) { + printk(KERN_INFO "%s: tx_full\n", dev->name); + netif_stop_queue(dev); + aup->tx_full = 1; + return 1; + } + else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) { + printk(KERN_INFO "%s: tx_full\n", dev->name); + netif_stop_queue(dev); + aup->tx_full = 1; + return 1; + } + + pDB = aup->tx_db_inuse[aup->tx_head]; + +#if 0 + if (read_ir_reg(IR_RX_BYTE_CNT) != 0) { + printk("tx warning: rx byte cnt %x\n", + read_ir_reg(IR_RX_BYTE_CNT)); + } +#endif + + if (aup->speed == 4000000) { + /* FIR */ + memcpy((void *)pDB->vaddr, skb->data, skb->len); + ptxd->count_0 = skb->len & 0xff; + ptxd->count_1 = (skb->len >> 8) & 0xff; + } + else { + /* SIR */ + len = async_wrap_skb(skb, (u8 *)pDB->vaddr, MAX_BUF_SIZE); + ptxd->count_0 = len & 0xff; + ptxd->count_1 = (len >> 8) & 0xff; + ptxd->flags |= IR_DIS_CRC; + } + ptxd->flags |= AU_OWN; + au_sync(); + + writel(read_ir_reg(IR_CONFIG_1) | IR_TX_ENABLE, IR_CONFIG_1); + writel(0, IR_RING_PROMPT); + au_sync(); + + dev_kfree_skb(skb); + aup->tx_head = (aup->tx_head + 1) & (NUM_IR_DESC - 1); + dev->trans_start = jiffies; + return 0; +} + + +static inline void +update_rx_stats(struct net_device *dev, u32 status, u32 count) +{ + struct au1k_private *aup = (struct au1k_private *) dev->priv; + struct net_device_stats *ps = &aup->stats; + + ps->rx_packets++; + + if (status & IR_RX_ERROR) { + ps->rx_errors++; + if (status & (IR_PHY_ERROR|IR_FIFO_OVER)) + ps->rx_missed_errors++; + if (status & IR_MAX_LEN) + ps->rx_length_errors++; + if (status & IR_CRC_ERROR) + ps->rx_crc_errors++; + } + else + ps->rx_bytes += count; +} + +/* + * Au1000 receive routine. + */ +static int au1k_irda_rx(struct net_device *dev) +{ + struct au1k_private *aup = (struct au1k_private *) dev->priv; + struct sk_buff *skb; + volatile ring_dest_t *prxd; + u32 flags, count; + db_dest_t *pDB; + + prxd = aup->rx_ring[aup->rx_head]; + flags = prxd->flags; + + while (!(flags & AU_OWN)) { + pDB = aup->rx_db_inuse[aup->rx_head]; + count = prxd->count_1<<8 | prxd->count_0; + if (!(flags & IR_RX_ERROR)) { + /* good frame */ + update_rx_stats(dev, flags, count); + skb=alloc_skb(count+1,GFP_ATOMIC); + if (skb == NULL) { + aup->stats.rx_dropped++; + continue; + } + skb_reserve(skb, 1); + if (aup->speed == 4000000) + skb_put(skb, count); + else + skb_put(skb, count-2); + memcpy(skb->data, (void *)pDB->vaddr, count-2); + skb->dev = dev; + skb->mac.raw = skb->data; + skb->protocol = htons(ETH_P_IRDA); + netif_rx(skb); + prxd->count_0 = 0; + prxd->count_1 = 0; + } + prxd->flags |= AU_OWN; + aup->rx_head = (aup->rx_head + 1) & (NUM_IR_DESC - 1); + writel(0, IR_RING_PROMPT); + au_sync(); + + /* next descriptor */ + prxd = aup->rx_ring[aup->rx_head]; + flags = prxd->flags; + dev->last_rx = jiffies; + + } + return 0; +} + + +void au1k_irda_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + struct net_device *dev = (struct net_device *) dev_id; + + if (dev == NULL) { + printk(KERN_ERR "%s: isr: null dev ptr\n", dev->name); + return; + } + + writel(0, IR_INT_CLEAR); /* ack irda interrupts */ + + au1k_irda_rx(dev); + au1k_tx_ack(dev); +} + + +/* + * The Tx ring has been full longer than the watchdog timeout + * value. The transmitter must be hung? + */ +static void au1k_tx_timeout(struct net_device *dev) +{ + u32 speed; + struct au1k_private *aup = (struct au1k_private *) dev->priv; + + printk(KERN_ERR "%s: tx timeout\n", dev->name); + speed = aup->speed; + aup->speed = 0; + au1k_irda_set_speed(dev, speed); + aup->tx_full = 0; + netif_wake_queue(dev); +} + + +/* + * Set the IrDA communications speed. + */ +static int +au1k_irda_set_speed(struct net_device *dev, int speed) +{ + unsigned long flags; + struct au1k_private *aup = (struct au1k_private *) dev->priv; + u32 control; + int ret = 0, timeout = 10, i; + volatile ring_dest_t *ptxd; + + if (speed == aup->speed) + return ret; + + spin_lock_irqsave(&ir_lock, flags); + + /* disable PHY first */ + writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE); + + /* disable RX/TX */ + writel(read_ir_reg(IR_CONFIG_1) & ~(IR_RX_ENABLE|IR_TX_ENABLE), + IR_CONFIG_1); + au_sync_delay(1); + while (read_ir_reg(IR_ENABLE) & (IR_RX_STATUS | IR_TX_STATUS)) { + mdelay(1); + if (!timeout--) { + printk(KERN_ERR "%s: rx/tx disable timeout\n", + dev->name); + break; + } + } + + /* disable DMA */ + writel(read_ir_reg(IR_CONFIG_1) & ~IR_DMA_ENABLE, IR_CONFIG_1); + au_sync_delay(1); + + /* + * After we disable tx/rx. the index pointers + * go back to zero. + */ + aup->tx_head = aup->tx_tail = aup->rx_head = 0; + for (i=0; itx_ring[i]; + ptxd->flags = 0; + ptxd->count_0 = 0; + ptxd->count_1 = 0; + } + + for (i=0; irx_ring[i]; + ptxd->count_0 = 0; + ptxd->count_1 = 0; + ptxd->flags = AU_OWN; + } + + if (speed == 4000000) + writel(1<<13, CPLD_AUX1); + else + writel(readl(CPLD_AUX1) & ~(1<<13), CPLD_AUX1); + + switch (speed) { + case 9600: + writel(11<<10 | 12<<5, IR_WRITE_PHY_CONFIG); + writel(IR_SIR_MODE, IR_CONFIG_1); + break; + case 19200: + writel(5<<10 | 12<<5, IR_WRITE_PHY_CONFIG); + writel(IR_SIR_MODE, IR_CONFIG_1); + break; + case 38400: + writel(2<<10 | 12<<5, IR_WRITE_PHY_CONFIG); + writel(IR_SIR_MODE, IR_CONFIG_1); + break; + case 57600: + writel(1<<10 | 12<<5, IR_WRITE_PHY_CONFIG); + writel(IR_SIR_MODE, IR_CONFIG_1); + break; + case 115200: + writel(12<<5, IR_WRITE_PHY_CONFIG); + writel(IR_SIR_MODE, IR_CONFIG_1); + break; + case 4000000: + writel(0xF, IR_WRITE_PHY_CONFIG); + writel(IR_FIR|IR_DMA_ENABLE|IR_RX_ENABLE, IR_CONFIG_1); + break; + default: + printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed); + ret = -EINVAL; + break; + } + + aup->speed = speed; + writel(read_ir_reg(IR_ENABLE) | 0x8000, IR_ENABLE); + au_sync(); + + control = read_ir_reg(IR_ENABLE); + writel(0, IR_RING_PROMPT); + au_sync(); + + if (control & (1<<14)) { + printk(KERN_ERR "%s: configuration error\n", dev->name); + } + else { + if (control & (1<<11)) + printk(KERN_INFO "%s Valid SIR config\n", dev->name); + if (control & (1<<12)) + printk(KERN_INFO "%s Valid MIR config\n", dev->name); + if (control & (1<<13)) + printk(KERN_INFO "%s Valid FIR config\n", dev->name); + if (control & (1<<10)) + printk(KERN_INFO "%s TX enabled\n", dev->name); + if (control & (1<<9)) + printk(KERN_INFO "%s RX enabled\n", dev->name); + } + + spin_unlock_irqrestore(&ir_lock, flags); + return ret; +} + +static int +au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) +{ + struct if_irda_req *rq = (struct if_irda_req *)ifreq; + struct au1k_private *aup = dev->priv; + int ret = -EOPNOTSUPP; + + switch (cmd) { + case SIOCSBANDWIDTH: + if (capable(CAP_NET_ADMIN)) { + /* + * We are unable to set the speed if the + * device is not running. + */ + if (aup->open) + ret = au1k_irda_set_speed(dev, + rq->ifr_baudrate); + else { + printk(KERN_ERR "%s ioctl: !netif_running\n", + dev->name); + ret = 0; + } + } + break; + + case SIOCSMEDIABUSY: + ret = -EPERM; + if (capable(CAP_NET_ADMIN)) { + irda_device_set_media_busy(dev, TRUE); + ret = 0; + } + break; + + case SIOCGRECEIVING: + rq->ifr_receiving = 0; + break; + default: + break; + } + return ret; +} + + +static struct net_device_stats *au1k_irda_stats(struct net_device *dev) +{ + struct au1k_private *aup = (struct au1k_private *) dev->priv; + return &aup->stats; +} + +#ifdef MODULE +MODULE_AUTHOR("Pete Popov "); +MODULE_DESCRIPTION("Au1000 IrDA Device Driver"); + +module_init(au1k_irda_init); +module_exit(au1k_irda_exit); +#endif /* MODULE */ --- linux-2.5.73/drivers/net/irda/Kconfig 2003-06-14 12:18:29.000000000 -0700 +++ 25/drivers/net/irda/Kconfig 2003-06-27 15:56:24.000000000 -0700 @@ -289,6 +289,10 @@ config TOSHIBA_FIR . The module will be called donauboe. +config AU1000_FIR + tristate "Alchemy Au1000 SIR/FIR" + depends on MIPS_AU1000 && IRDA + config SMC_IRCC_OLD tristate "SMC IrCC (old driver) (EXPERIMENTAL)" depends on EXPERIMENTAL && IRDA --- linux-2.5.73/drivers/net/irda/Makefile 2003-06-14 12:18:09.000000000 -0700 +++ 25/drivers/net/irda/Makefile 2003-06-27 15:56:24.000000000 -0700 @@ -28,6 +28,7 @@ obj-$(CONFIG_LITELINK_DONGLE) += litelin obj-$(CONFIG_OLD_BELKIN_DONGLE) += old_belkin.o obj-$(CONFIG_EP7211_IR) += ep7211_ir.o obj-$(CONFIG_MCP2120_DONGLE) += mcp2120.o +obj-$(CONFIG_AU1000_FIR) += au1k_ir.o obj-$(CONFIG_ACT200L_DONGLE) += act200l.o obj-$(CONFIG_MA600_DONGLE) += ma600.o # New SIR drivers --- linux-2.5.73/drivers/net/irda/vlsi_ir.c 2003-06-14 12:17:56.000000000 -0700 +++ 25/drivers/net/irda/vlsi_ir.c 2003-06-27 15:56:24.000000000 -0700 @@ -2,7 +2,7 @@ * * vlsi_ir.c: VLSI82C147 PCI IrDA controller driver for Linux * - * Copyright (c) 2001-2002 Martin Diehl + * Copyright (c) 2001-2003 Martin Diehl * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -28,7 +28,7 @@ MODULE_AUTHOR("Martin Diehl name, S_IFREG|S_IRUGO, vlsi_proc_root); @@ -1810,11 +1817,11 @@ vlsi_irda_probe(struct pci_dev *pdev, co goto out_unregister; } ent->data = ndev; - ent->proc_fops = &vlsi_proc_fops; + ent->proc_fops = VLSI_PROC_FOPS; ent->size = 0; idev->proc_entry = ent; - } -#endif + } else + idev->proc_entry = NULL; printk(KERN_INFO "%s: registered device %s\n", drivername, ndev->name); @@ -1851,12 +1858,10 @@ static void __devexit vlsi_irda_remove(s down(&idev->sem); pci_set_drvdata(pdev, NULL); pci_disable_device(pdev); -#ifdef CONFIG_PROC_FS if (idev->proc_entry) { remove_proc_entry(ndev->name, vlsi_proc_root); idev->proc_entry = NULL; } -#endif up(&idev->sem); unregister_netdev(ndev); @@ -1993,9 +1998,7 @@ static struct pci_driver vlsi_irda_drive #endif }; -#ifdef CONFIG_PROC_FS #define PROC_DIR ("driver/" DRIVER_NAME) -#endif static int __init vlsi_mod_init(void) { @@ -2025,18 +2028,23 @@ static int __init vlsi_mod_init(void) sirpulse = !!sirpulse; -#ifdef CONFIG_PROC_FS + /* create_proc_entry returns NULL if !CONFIG_PROC_FS. + * Failure to create the procfs entry is handled like running + * without procfs - it's not required for the driver to work. + */ vlsi_proc_root = create_proc_entry(PROC_DIR, S_IFDIR, 0); - if (!vlsi_proc_root) - return -ENOMEM; -#endif + if (vlsi_proc_root) { + /* protect registered procdir against module removal. + * Because we are in the module init path there's no race + * window after create_proc_entry (and no barrier needed). + */ + vlsi_proc_root->owner = THIS_MODULE; + } ret = pci_module_init(&vlsi_irda_driver); -#ifdef CONFIG_PROC_FS - if (ret) + if (ret && vlsi_proc_root) remove_proc_entry(PROC_DIR, 0); -#endif return ret; } @@ -2044,7 +2052,8 @@ static int __init vlsi_mod_init(void) static void __exit vlsi_mod_exit(void) { pci_unregister_driver(&vlsi_irda_driver); - remove_proc_entry(PROC_DIR, 0); + if (vlsi_proc_root) + remove_proc_entry(PROC_DIR, 0); } module_init(vlsi_mod_init); --- linux-2.5.73/drivers/net/ixgb/ixgb_ethtool.c 2003-06-22 12:04:44.000000000 -0700 +++ 25/drivers/net/ixgb/ixgb_ethtool.c 2003-06-27 15:56:24.000000000 -0700 @@ -448,8 +448,6 @@ ixgb_ethtool_ioctl(struct net_device *ne case ETHTOOL_SSET:{ struct ethtool_cmd ecmd; - if (!capable(CAP_NET_ADMIN)) - return -EPERM; if (copy_from_user(&ecmd, addr, sizeof (ecmd))) return -EFAULT; return ixgb_ethtool_sset(adapter, &ecmd); @@ -482,9 +480,6 @@ ixgb_ethtool_ioctl(struct net_device *ne #endif /* ETHTOOL_GREGS */ case ETHTOOL_NWAY_RST:{ IXGB_DBG("ETHTOOL_NWAY_RST\n"); - if (!capable(CAP_NET_ADMIN)) - return -EPERM; - ixgb_down(adapter); ixgb_up(adapter); @@ -539,9 +534,6 @@ ixgb_ethtool_ioctl(struct net_device *ne struct ethtool_eeprom eeprom; IXGB_DBG("ETHTOOL_SEEPROM\n"); - if (!capable(CAP_NET_ADMIN)) - return -EPERM; - if (copy_from_user(&eeprom, addr, sizeof (eeprom))) return -EFAULT; --- linux-2.5.73/drivers/net/Kconfig 2003-06-14 12:18:32.000000000 -0700 +++ 25/drivers/net/Kconfig 2003-06-27 15:56:24.000000000 -0700 @@ -492,16 +492,16 @@ config MIPS_GT96100ETH help Say Y here to support the Ethernet subsystem on your GT96100 card. -config MIPS_AU1000_ENET +config MIPS_AU1X00_ENET bool "MIPS AU1000 Ethernet support" - depends on NET_ETHERNET && MIPS_AU1000 + depends on NET_ETHERNET && SOC_AU1X00 help - If you have an Alchemy Semi AU1000 ethernet controller - on an SGI MIPS system, say Y. Otherwise, say N. + If you have an Alchemy Semi AU1X00 based system + say Y. Otherwise, say N. config NET_SB1250_MAC tristate "SB1250 Ethernet support" - depends on NET_ETHERNET && SIBYTE_SB1250 + depends on NET_ETHERNET && SIBYTE_SB1xxx_SOC config SGI_IOC3_ETH bool "SGI IOC3 Ethernet" @@ -511,6 +511,10 @@ config SGI_IOC3_ETH the Ethernet-HOWTO, available from . +config SGI_O2MACE_ETH + tristate "SGI O2 MACE Fast Ethernet support" + depends on NET_ETHERNET && SGI_IP32=y + config STNIC tristate "National DP83902AV support" depends on NET_ETHERNET && SUPERH @@ -1391,6 +1395,10 @@ config CS89x0 . The module will be called cs89x. +config TC35815 + tristate "TOSHIBA TC35815 Ethernet support" + depends on NET_PCI && PCI + config DGRS tristate "Digi Intl. RightSwitch SE-X support" depends on NET_PCI && (PCI || EISA) @@ -1839,14 +1847,14 @@ config DE620 The module will be called de620. config SGISEEQ - bool "SGI Seeq ethernet controller support" + tristate "SGI Seeq ethernet controller support" depends on NET_ETHERNET && SGI_IP22 help Say Y here if you have an Seeq based Ethernet network card. This is used in many Silicon Graphics machines. config DECLANCE - bool "DEC LANCE ethernet controller support" + tristate "DEC LANCE ethernet controller support" depends on NET_ETHERNET && DECSTATION help This driver is for the series of Ethernet controllers produced by --- linux-2.5.73/drivers/net/Makefile 2003-06-14 12:18:05.000000000 -0700 +++ 25/drivers/net/Makefile 2003-06-27 15:56:24.000000000 -0700 @@ -117,6 +117,7 @@ obj-$(CONFIG_SUN3_82586) += sun3_82586.o obj-$(CONFIG_SUN3LANCE) += sun3lance.o obj-$(CONFIG_DEFXX) += defxx.o obj-$(CONFIG_SGISEEQ) += sgiseeq.o +obj-$(CONFIG_SGI_O2MACE_ETH) += meth.o obj-$(CONFIG_AT1700) += at1700.o obj-$(CONFIG_FMV18X) += fmv18x.o obj-$(CONFIG_EL1) += 3c501.o @@ -156,7 +157,7 @@ obj-$(CONFIG_MVME147_NET) += mvme147.o 7 obj-$(CONFIG_EQUALIZER) += eql.o obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o obj-$(CONFIG_MIPS_GT96100ETH) += gt96100eth.o -obj-$(CONFIG_MIPS_AU1000_ENET) += au1000_eth.o +obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o obj-$(CONFIG_BAGETLANCE) += bagetlance.o obj-$(CONFIG_DECLANCE) += declance.o --- linux-2.5.73/drivers/net/Makefile.lib 2003-06-14 12:18:30.000000000 -0700 +++ 25/drivers/net/Makefile.lib 2003-06-27 15:56:24.000000000 -0700 @@ -24,6 +24,7 @@ obj-$(CONFIG_PCMCIA_FMVJ18X) += crc32.o obj-$(CONFIG_PCMCIA_SMC91C92) += crc32.o obj-$(CONFIG_PCMCIA_XIRTULIP) += crc32.o obj-$(CONFIG_PCNET32) += crc32.o +obj-$(CONFIG_SGI_IOC3_ETH) += crc32.o obj-$(CONFIG_SIS900) += crc32.o obj-$(CONFIG_SMC9194) += crc32.o obj-$(CONFIG_ADAPTEC_STARFIRE) += crc32.o --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/net/meth.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,862 @@ +/* + * meth.c -- O2 Builtin 10/100 Ethernet driver + * + * Copyright (C) 2001 Ilya Volynets + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include + +#include +#include /* printk() */ +#include +#include +#include /* error codes */ +#include /* size_t */ +#include /* mark_bh */ +#include + +#include +#include /* struct device, and other headers */ +#include /* eth_type_trans */ +#include /* struct iphdr */ +#include /* struct tcphdr */ +#include +#include /*MII definitions */ + +#include +#include +#include + +#include "meth.h" + +#include +#include + +#ifndef MFE_DEBUG +#define MFE_DEBUG 0 +#endif + +#if MFE_DEBUG>=1 +#define DPRINTK(str,args...) printk (KERN_DEBUG "meth(%ld): %s: " str, jiffies, __FUNCTION__ , ## args) +#define MFE_RX_DEBUG 2 +#else +#define DPRINTK(str,args...) +#define MFE_RX_DEBUG 0 +#endif + + +static const char *version="meth.c: Ilya Volynets (ilya@theIlya.com)"; +static const char *meth_str="SGI O2 Fast Ethernet"; +MODULE_AUTHOR("Ilya Volynets"); +MODULE_DESCRIPTION("SGI O2 Builtin Fast Ethernet driver"); + +/* This is a load-time options */ +/*static int eth = 0; +MODULE_PARM(eth, "i");*/ + +#define HAVE_TX_TIMEOUT +/* The maximum time waited (in jiffies) before assuming a Tx failed. (400ms) */ +#define TX_TIMEOUT (400*HZ/1000) + +#ifdef HAVE_TX_TIMEOUT +static int timeout = TX_TIMEOUT; +MODULE_PARM(timeout, "i"); +#endif + +int meth_eth; + +/* + * This structure is private to each device. It is used to pass + * packets in and out, so there is place for a packet + */ + +typedef struct meth_private { + struct net_device_stats stats; + volatile struct meth_regs *regs; + u64 mode; /* in-memory copy of MAC control register */ + int phy_addr; /* address of phy, used by mdio_* functions, initialized in mdio_probe*/ + tx_packet *tx_ring; + dma_addr_t tx_ring_dma; + int free_space; + struct sk_buff *tx_skbs[TX_RING_ENTRIES]; + dma_addr_t tx_skb_dmas[TX_RING_ENTRIES]; + int tx_read,tx_write; + int tx_count; + + rx_packet *rx_ring[RX_RING_ENTRIES]; + dma_addr_t rx_ring_dmas[RX_RING_ENTRIES]; + int rx_write; + + spinlock_t meth_lock; +} meth_private; + +extern struct net_device meth_devs[]; +void meth_tx_timeout (struct net_device *dev); +void meth_interrupt(int irq, void *dev_id, struct pt_regs *pregs); + +/* global, initialized in ip32-setup.c */ +char o2meth_eaddr[8]={0,0,0,0,0,0,0,0}; + +static inline void load_eaddr(struct net_device *dev, + volatile struct meth_regs *regs) +{ + int i; + DPRINTK("Loading MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n", + (int)o2meth_eaddr[0]&0xFF,(int)o2meth_eaddr[1]&0xFF,(int)o2meth_eaddr[2]&0xFF, + (int)o2meth_eaddr[3]&0xFF,(int)o2meth_eaddr[4]&0xFF,(int)o2meth_eaddr[5]&0xFF); + //memcpy(dev->dev_addr,o2meth_eaddr+2,6); + for (i=0; i<6; i++) + dev->dev_addr[i]=o2meth_eaddr[i]; + regs->mac_addr= //dev->dev_addr[0]|(dev->dev_addr[1]<<8)| + //dev->dev_addr[2]<<16|(dev->dev_addr[3]<<24)| + //dev->dev_addr[4]<<32|(dev->dev_addr[5]<<40); + (*(u64*)o2meth_eaddr)>>16; + DPRINTK("MAC, finally is %0lx\n",regs->mac_addr); +} + +/* + *Waits for BUSY status of mdio bus to clear + */ +#define WAIT_FOR_PHY(___regs, ___rval) \ + while((___rval=___regs->phy_data)&MDIO_BUSY){ \ + udelay(25); \ + } +/*read phy register, return value read */ +static int mdio_read(meth_private *priv,int phyreg) +{ + volatile meth_regs* regs=priv->regs; + volatile u32 rval; + WAIT_FOR_PHY(regs,rval) + regs->phy_registers=(priv->phy_addr<<5)|(phyreg&0x1f); + udelay(25); + regs->phy_trans_go=1; + udelay(25); + WAIT_FOR_PHY(regs,rval) + return rval&MDIO_DATA_MASK; +} + +/*write phy register */ +static void mdio_write(meth_private* priv,int pfyreg,int val) +{ + volatile meth_regs* regs=priv->regs; + int rval; +/// DPRINTK("Trying to write value %i to reguster %i\n",val, pfyreg); + spin_lock_irq(&priv->meth_lock); + WAIT_FOR_PHY(regs,rval) + regs->phy_registers=(priv->phy_addr<<5)|(pfyreg&0x1f); + regs->phy_data=val; + udelay(25); + WAIT_FOR_PHY(regs,rval) + spin_unlock_irq(&priv->meth_lock); +} + +/* Modify phy register using given mask and value */ +static void mdio_update(meth_private* priv,int phyreg, int val, int mask) +{ + int rval; + DPRINTK("RMW value %i to PHY register %i with mask %i\n",val,phyreg,mask); + rval=mdio_read(priv,phyreg); + rval=(rval&~mask)|(val&mask); + mdio_write(priv,phyreg,rval); +} + +/* handle errata data on MDIO bus */ +//static void mdio_errata(meth_private *priv) +//{ + /* Hmmm... what the hell is phyerrata? does it come from sys init parameters in IRIX */ +//} +static int mdio_probe(meth_private *priv) +{ + int i, p2, p3; + DPRINTK("Detecting PHY kind\n"); + /* check if phy is detected already */ + if(priv->phy_addr>=0&&priv->phy_addr<32) + return 0; + spin_lock_irq(&priv->meth_lock); + for (i=0;i<32;++i){ + priv->phy_addr=(char)i; + p2=mdio_read(priv,2); +#ifdef MFE_DEBUG + p3=mdio_read(priv,3); + switch ((p2<<12)|(p3>>4)){ + case PHY_QS6612X: + DPRINTK("PHY is QS6612X\n"); + break; + case PHY_ICS1889: + DPRINTK("PHY is ICS1889\n"); + break; + case PHY_ICS1890: + DPRINTK("PHY is ICS1890\n"); + break; + case PHY_DP83840: + DPRINTK("PHY is DP83840\n"); + break; + } +#endif + if(p2!=0xffff&&p2!=0x0000){ + DPRINTK("PHY code: %x\n",(p2<<12)|(p3>>4)); + break; + } + } + spin_unlock_irq(&priv->meth_lock); + if(priv->phy_addr<32) { + return 0; + } + DPRINTK("Oopsie! PHY is not known!\n"); + priv->phy_addr=-1; + return -ENODEV; +} + +static void meth_check_link(struct net_device *dev) +{ + struct meth_private *priv = (struct meth_private *) dev->priv; + int mii_partner = mdio_read(priv, 5); + int mii_advertising = mdio_read(priv, 4); + int negotiated = mii_advertising & mii_partner; + int duplex, speed; + + if (mii_partner == 0xffff) + return; + + duplex = ((negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040)?METH_PHY_FDX:0; + speed = (negotiated & 0x0380)?METH_100MBIT:0; + + if ((priv->mode & METH_PHY_FDX) ^ duplex) + { + DPRINTK("Setting %s-duplex\n", duplex ? "full" : "half"); + if (duplex) + priv->mode |= METH_PHY_FDX; + else + priv->mode &= ~METH_PHY_FDX; + priv->regs->mac_ctrl = priv->mode; + } + + if ((priv->mode & METH_100MBIT) ^ speed) + { + DPRINTK("Setting %dMbs mode\n", speed ? 100 : 10); + if (duplex) + priv->mode |= METH_100MBIT; + else + priv->mode &= ~METH_100MBIT; + priv->regs->mac_ctrl = priv->mode; + } +} + + +static int meth_init_tx_ring(meth_private *priv) +{ + /* Init TX ring */ + DPRINTK("Initializing TX ring\n"); + priv->tx_ring = (tx_packet *) pci_alloc_consistent(NULL,TX_RING_BUFFER_SIZE,&(priv->tx_ring_dma)); + if(!priv->tx_ring) + return -ENOMEM; + memset(priv->tx_ring, 0, TX_RING_BUFFER_SIZE); + priv->tx_count = priv->tx_read = priv->tx_write = 0; + priv->regs->tx_ring_base = priv->tx_ring_dma; + priv->free_space = TX_RING_ENTRIES; + /* Now init skb save area */ + memset(priv->tx_skbs,0,sizeof(priv->tx_skbs)); + memset(priv->tx_skb_dmas,0,sizeof(priv->tx_skb_dmas)); + DPRINTK("Done with TX ring init\n"); + return 0; +} + +static int meth_init_rx_ring(meth_private *priv) +{ + int i; + DPRINTK("Initializing RX ring\n"); + for(i=0;irx_ring[i]=get_free_page(GFP_KERNEL))) + return -ENOMEM; + DPRINTK("\t2:\t%i\n",i);*/ + priv->rx_ring[i]=(rx_packet*)pci_alloc_consistent(NULL,METH_RX_BUFF_SIZE,&(priv->rx_ring_dmas[i])); + /* I'll need to re-sync it after each RX */ + DPRINTK("\t%p\n",priv->rx_ring[i]); + priv->regs->rx_fifo=priv->rx_ring_dmas[i]; + } + priv->rx_write = 0; + DPRINTK("Done with RX ring\n"); + return 0; +} +static void meth_free_tx_ring(meth_private *priv) +{ + int i; + + /* Remove any pending skb */ + for (i = 0; i < TX_RING_ENTRIES; i++) { + if (priv->tx_skbs[i]) + dev_kfree_skb(priv->tx_skbs[i]); + priv->tx_skbs[i] = NULL; + } + pci_free_consistent(NULL, + TX_RING_BUFFER_SIZE, + priv->tx_ring, + priv->tx_ring_dma); +} +static void meth_free_rx_ring(meth_private *priv) +{ + int i; + + for(i=0;irx_ring[i], + priv->rx_ring_dmas[i]); +} + +int meth_reset(struct net_device *dev) +{ + struct meth_private *priv = (struct meth_private *) dev->priv; + + /* Reset card */ + priv->regs->mac_ctrl = SGI_MAC_RESET; + priv->regs->mac_ctrl = 0; + udelay(25); + DPRINTK("MAC control after reset: %016lx\n", priv->regs->mac_ctrl); + + /* Load ethernet address */ + load_eaddr(dev, priv->regs); + /* Should load some "errata", but later */ + + /* Check for device */ + if(mdio_probe(priv) < 0) { + DPRINTK("Unable to find PHY\n"); + return -ENODEV; + } + + /* Initial mode -- 10|Half-duplex|Accept normal packets */ + priv->mode=METH_ACCEPT_MCAST|METH_DEFAULT_IPG; + if(dev->flags | IFF_PROMISC) + priv->mode |= METH_PROMISC; + priv->regs->mac_ctrl = priv->mode; + + /* Autonegociate speed and duplex mode */ + meth_check_link(dev); + + /* Now set dma control, but don't enable DMA, yet */ + priv->regs->dma_ctrl= (4 << METH_RX_OFFSET_SHIFT) | + (RX_RING_ENTRIES << METH_RX_DEPTH_SHIFT); + + return(0); +} + +/*============End Helper Routines=====================*/ + +/* + * Open and close + */ + +int meth_open(struct net_device *dev) +{ + meth_private *priv=dev->priv; + volatile meth_regs *regs=priv->regs; + + MOD_INC_USE_COUNT; + + /* Start DMA */ + regs->dma_ctrl|= + METH_DMA_TX_EN|/*METH_DMA_TX_INT_EN|*/ + METH_DMA_RX_EN|METH_DMA_RX_INT_EN; + + if(request_irq(dev->irq,meth_interrupt,SA_SHIRQ,meth_str,dev)){ + printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq); + return -EAGAIN; + } + netif_start_queue(dev); + DPRINTK("Opened... DMA control=0x%08lx\n", regs->dma_ctrl); + return 0; +} + +int meth_release(struct net_device *dev) +{ + netif_stop_queue(dev); /* can't transmit any more */ + /* shut down dma */ + ((meth_private*)(dev->priv))->regs->dma_ctrl&= + ~(METH_DMA_TX_EN|METH_DMA_TX_INT_EN| + METH_DMA_RX_EN|METH_DMA_RX_INT_EN); + free_irq(dev->irq, dev); + MOD_DEC_USE_COUNT; + return 0; +} + +/* + * Configuration changes (passed on by ifconfig) + */ +int meth_config(struct net_device *dev, struct ifmap *map) +{ + if (dev->flags & IFF_UP) /* can't act on a running interface */ + return -EBUSY; + + /* Don't allow changing the I/O address */ + if (map->base_addr != dev->base_addr) { + printk(KERN_WARNING "meth: Can't change I/O address\n"); + return -EOPNOTSUPP; + } + + /* Allow changing the IRQ */ + if (map->irq != dev->irq) { + printk(KERN_WARNING "meth: Can't change IRQ\n"); + return -EOPNOTSUPP; + } + DPRINTK("Configured\n"); + + /* ignore other fields */ + return 0; +} + +/* + * Receive a packet: retrieve, encapsulate and pass over to upper levels + */ +void meth_rx(struct net_device* dev) +{ + struct sk_buff *skb; + struct meth_private *priv = (struct meth_private *) dev->priv; + rx_packet *rxb; + DPRINTK("RX...\n"); + // TEMP while((rxb=priv->rx_ring[priv->rx_write])->status.raw&0x8000000000000000){ + while((rxb=priv->rx_ring[priv->rx_write])->status.raw&0x8000000000000000){ + int len=rxb->status.parsed.rx_len - 4; /* omit CRC */ + DPRINTK("(%i)\n",priv->rx_write); + /* length sanity check */ + if(len < 60 || len > 1518) { + printk(KERN_DEBUG "%s: bogus packet size: %d, status=%#2x.\n", + dev->name, priv->rx_write, rxb->status.raw); + priv->stats.rx_errors++; + priv->stats.rx_length_errors++; + } + if(!(rxb->status.raw&METH_RX_STATUS_ERRORS)){ + skb=alloc_skb(len+2,GFP_ATOMIC);/* Should be atomic -- we are in interrupt */ + if(!skb){ + /* Ouch! No memory! Drop packet on the floor */ + DPRINTK("!!!>>>Ouch! Not enough Memory for RX buffer!\n"); + priv->stats.rx_dropped++; + } else { + skb_reserve(skb, 2); /* align IP on 16B boundary */ + memcpy(skb_put(skb, len), rxb->buf, len); + /* Write metadata, and then pass to the receive level */ + skb->dev = dev; + skb->protocol = eth_type_trans(skb, dev); + //skb->ip_summed = CHECKSUM_UNNECESSARY; /* don't check it */ + + DPRINTK("passing packet\n"); + DPRINTK("len = %d rxb->status = %x\n", + len, rxb->status.raw); + netif_rx(skb); + dev->last_rx = jiffies; + priv->stats.rx_packets++; + priv->stats.rx_bytes+=len; + DPRINTK("There we go... Whew...\n"); + } + } + priv->regs->rx_fifo=priv->rx_ring_dmas[priv->rx_write]; + rxb->status.raw=0; + priv->rx_write=(priv->rx_write+1)&(RX_RING_ENTRIES-1); + } +} + +static int meth_tx_full(struct net_device *dev) +{ + struct meth_private *priv = (struct meth_private *) dev->priv; + + return(priv->tx_count >= TX_RING_ENTRIES-1); +} + +void meth_tx_cleanup(struct net_device* dev, int rptr) +{ + meth_private *priv=dev->priv; + tx_packet* status; + struct sk_buff *skb; + + spin_lock(&priv->meth_lock); + + /* Stop DMA */ + priv->regs->dma_ctrl &= ~(METH_DMA_TX_INT_EN); + + while(priv->tx_read != rptr){ + skb = priv->tx_skbs[priv->tx_read]; + status = &priv->tx_ring[priv->tx_read]; + if(!status->header.res.sent) + break; + if(status->header.raw & METH_TX_STATUS_DONE) { + priv->stats.tx_packets++; + priv->stats.tx_bytes += skb->len; + } + dev_kfree_skb_irq(skb); + priv->tx_skbs[priv->tx_read] = NULL; + status->header.raw = 0; + priv->tx_read = (priv->tx_read+1)&(TX_RING_ENTRIES-1); + priv->tx_count --; + } + + /* wake up queue if it was stopped */ + if (netif_queue_stopped(dev) && ! meth_tx_full(dev)) { + netif_wake_queue(dev); + } + + spin_unlock(priv->meth_lock); +} + +/* + * The typical interrupt entry point + */ +void meth_interrupt(int irq, void *dev_id, struct pt_regs *pregs) +{ + struct meth_private *priv; + union { + u32 reg; /*Whole status register */ + struct { + u32 : 2, + rx_seq : 5, + tx_read : 9, + + rx_read : 8, + int_mask: 8; + } parsed; + } status; + /* + * As usual, check the "device" pointer for shared handlers. + * Then assign "struct device *dev" + */ + struct net_device *dev = (struct net_device *)dev_id; + /* ... and check with hw if it's really ours */ + + if (!dev /*paranoid*/ ) return; + + /* Lock the device */ + priv = (struct meth_private *) dev->priv; + + status.reg = priv->regs->int_flags; + + DPRINTK("Interrupt, status %08x...\n",status.reg); + if (status.parsed.int_mask & METH_INT_RX_THRESHOLD) { + /* send it to meth_rx for handling */ + meth_rx(dev); + } + + if (status.parsed.int_mask & (METH_INT_TX_EMPTY|METH_INT_TX_PKT)) { + /* a transmission is over: free the skb */ + meth_tx_cleanup(dev, status.parsed.tx_read); + } + /* check for errors too... */ + if (status.parsed.int_mask & (METH_INT_TX_LINK_FAIL)) + printk(KERN_WARNING "meth: link failure\n"); + if (status.parsed.int_mask & (METH_INT_MEM_ERROR)) + printk(KERN_WARNING "meth: memory error\n"); + if (status.parsed.int_mask & (METH_INT_TX_ABORT)) + printk(KERN_WARNING "meth: aborted\n"); + DPRINTK("Interrupt handling done...\n"); + + priv->regs->int_flags=status.reg&0xff; /* clear interrupts */ +} + +/* + * Transmits packets that fit into TX descriptor (are <=120B) + */ +static void meth_tx_short_prepare(meth_private* priv, struct sk_buff* skb) +{ + tx_packet *desc=&priv->tx_ring[priv->tx_write]; + int len = (skb->lenlen; + + DPRINTK("preparing short packet\n"); + /* maybe I should set whole thing to 0 first... */ + memcpy(desc->data.dt+(120-len),skb->data,skb->len); + if(skb->len < len) + memset(desc->data.dt+120-len+skb->len,0,len-skb->len); + desc->header.raw=METH_TX_CMD_INT_EN|(len-1)|((128-len)<<16); + DPRINTK("desc=%016lx\n",desc->header.raw); +} +#define TX_CATBUF1 BIT(25) +static void meth_tx_1page_prepare(meth_private* priv, struct sk_buff* skb) +{ + tx_packet *desc=&priv->tx_ring[priv->tx_write]; + void *buffer_data = (void *)(((u64)skb->data + 7ULL) & (~7ULL)); + int unaligned_len = (int)((u64)buffer_data - (u64)skb->data); + int buffer_len = skb->len - unaligned_len; + dma_addr_t catbuf; + + DPRINTK("preparing 1 page...\n"); + DPRINTK("length=%d data=%p\n", skb->len, skb->data); + DPRINTK("unaligned_len=%d\n", unaligned_len); + DPRINTK("buffer_data=%p buffer_len=%d\n", + buffer_data, + buffer_len); + + desc->header.raw=METH_TX_CMD_INT_EN|TX_CATBUF1|(skb->len-1); + + /* unaligned part */ + if(unaligned_len){ + memcpy(desc->data.dt+(120-unaligned_len), + skb->data, unaligned_len); + desc->header.raw |= (128-unaligned_len) << 16; + } + + /* first page */ + catbuf = pci_map_single(NULL, + buffer_data, + buffer_len, + PCI_DMA_TODEVICE); + DPRINTK("catbuf=%x\n", catbuf); + desc->data.cat_buf[0].form.start_addr = catbuf >> 3; + desc->data.cat_buf[0].form.len = buffer_len-1; + DPRINTK("desc=%016lx\n",desc->header.raw); + DPRINTK("cat_buf[0].raw=%016lx\n",desc->data.cat_buf[0].raw); +} +#define TX_CATBUF2 BIT(26) +static void meth_tx_2page_prepare(meth_private* priv, struct sk_buff* skb) +{ + tx_packet *desc=&priv->tx_ring[priv->tx_write]; + void *buffer1_data = (void *)(((u64)skb->data + 7ULL) & (~7ULL)); + void *buffer2_data = (void *)PAGE_ALIGN((u64)skb->data); + int unaligned_len = (int)((u64)buffer1_data - (u64)skb->data); + int buffer1_len = (int)((u64)buffer2_data - (u64)buffer1_data); + int buffer2_len = skb->len - buffer1_len - unaligned_len; + dma_addr_t catbuf1, catbuf2; + + DPRINTK("preparing 2 pages... \n"); + DPRINTK("length=%d data=%p\n", skb->len, skb->data); + DPRINTK("unaligned_len=%d\n", unaligned_len); + DPRINTK("buffer1_data=%p buffer1_len=%d\n", + buffer1_data, + buffer1_len); + DPRINTK("buffer2_data=%p buffer2_len=%d\n", + buffer2_data, + buffer2_len); + + desc->header.raw=METH_TX_CMD_INT_EN|TX_CATBUF1|TX_CATBUF2|(skb->len-1); + /* unaligned part */ + if(unaligned_len){ + memcpy(desc->data.dt+(120-unaligned_len), + skb->data, unaligned_len); + desc->header.raw |= (128-unaligned_len) << 16; + } + + /* first page */ + catbuf1 = pci_map_single(NULL, + buffer1_data, + buffer1_len, + PCI_DMA_TODEVICE); + DPRINTK("catbuf1=%x\n", catbuf1); + desc->data.cat_buf[0].form.start_addr = catbuf1 >> 3; + desc->data.cat_buf[0].form.len = buffer1_len-1; + /* second page */ + catbuf2 = pci_map_single(NULL, + buffer2_data, + buffer2_len, + PCI_DMA_TODEVICE); + DPRINTK("catbuf2=%x\n", catbuf2); + desc->data.cat_buf[1].form.start_addr = catbuf2 >> 3; + desc->data.cat_buf[1].form.len = buffer2_len-1; + DPRINTK("desc=%016lx\n",desc->header.raw); + DPRINTK("cat_buf[0].raw=%016lx\n",desc->data.cat_buf[0].raw); + DPRINTK("cat_buf[1].raw=%016lx\n",desc->data.cat_buf[1].raw); +} + + +void meth_add_to_tx_ring(meth_private *priv, struct sk_buff* skb) +{ + DPRINTK("Transmitting data...\n"); + if(skb->len <= 120) { + /* Whole packet fits into descriptor */ + meth_tx_short_prepare(priv,skb); + } else if(PAGE_ALIGN((u64)skb->data) != + PAGE_ALIGN((u64)skb->data+skb->len-1)) { + /* Packet crosses page boundary */ + meth_tx_2page_prepare(priv,skb); + } else { + /* Packet is in one page */ + meth_tx_1page_prepare(priv,skb); + } + + /* Remember the skb, so we can free it at interrupt time */ + priv->tx_skbs[priv->tx_write] = skb; + priv->tx_write = (priv->tx_write+1) & (TX_RING_ENTRIES-1); + priv->regs->tx_info.wptr = priv->tx_write; + priv->tx_count ++; + /* Enable DMA transfer */ + priv->regs->dma_ctrl |= METH_DMA_TX_INT_EN; +} + +/* + * Transmit a packet (called by the kernel) + */ +int meth_tx(struct sk_buff *skb, struct net_device *dev) +{ + struct meth_private *priv = (struct meth_private *) dev->priv; + + spin_lock_irq(&priv->meth_lock); + + meth_add_to_tx_ring(priv, skb); + dev->trans_start = jiffies; /* save the timestamp */ + + /* If TX ring is full, tell the upper layer to stop sending packets */ + if (meth_tx_full(dev)) { + DPRINTK("TX full: stopping\n"); + netif_stop_queue(dev); + } + + spin_unlock_irq(&priv->meth_lock); + + return 0; +} + +/* + * Deal with a transmit timeout. + */ + +void meth_tx_timeout (struct net_device *dev) +{ + struct meth_private *priv = (struct meth_private *) dev->priv; + + printk(KERN_WARNING "%s: transmit timed out\n", dev->name); + + /* Protect against concurrent rx interrupts */ + spin_lock_irq(&priv->meth_lock); + + /* Try to reset the adaptor. */ + meth_reset(dev); + + priv->stats.tx_errors++; + + /* Clear all rings */ + meth_free_tx_ring(priv); + meth_free_rx_ring(priv); + meth_init_tx_ring(priv); + meth_init_rx_ring(priv); + + /* Restart dma */ + priv->regs->dma_ctrl|=METH_DMA_TX_EN|METH_DMA_RX_EN|METH_DMA_RX_INT_EN; + + /* Enable interrupt */ + spin_unlock_irq(&priv->meth_lock); + + dev->trans_start = jiffies; + netif_wake_queue(dev); + + return; +} + +/* + * Ioctl commands + */ +int meth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + + DPRINTK("ioctl\n"); + return 0; +} + +/* + * Return statistics to the caller + */ +struct net_device_stats *meth_stats(struct net_device *dev) +{ + struct meth_private *priv = (struct meth_private *) dev->priv; + return &priv->stats; +} + +/* + * The init function (sometimes called probe). + * It is invoked by register_netdev() + */ +int meth_init(struct net_device *dev) +{ + meth_private *priv; + int ret; + /* + * Then, assign other fields in dev, using ether_setup() and some + * hand assignments + */ + ether_setup(dev); /* assign some of the fields */ + + dev->open = meth_open; + dev->stop = meth_release; + dev->set_config = meth_config; + dev->hard_start_xmit = meth_tx; + dev->do_ioctl = meth_ioctl; + dev->get_stats = meth_stats; +#ifdef HAVE_TX_TIMEOUT + dev->tx_timeout = meth_tx_timeout; + dev->watchdog_timeo = timeout; +#endif + dev->irq = MACE_ETHERNET_IRQ; + SET_MODULE_OWNER(dev); + + /* + * Then, allocate the priv field. This encloses the statistics + * and a few private fields. + */ + priv = kmalloc(sizeof(struct meth_private), GFP_KERNEL); + if (priv == NULL) + return -ENOMEM; + dev->priv=priv; + memset(priv, 0, sizeof(struct meth_private)); + spin_lock_init(&((struct meth_private *) dev->priv)->meth_lock); + /* + * Make the usual checks: check_region(), probe irq, ... -ENODEV + * should be returned if no device found. No resource should be + * grabbed: this is done on open(). + */ + priv->regs=(meth_regs*)SGI_MFE; + dev->base_addr=SGI_MFE; + priv->phy_addr = -1; /* No phy is known yet... */ + + /* Initialize the hardware */ + if((ret=meth_reset(dev)) < 0) + return ret; + + /* Allocate the ring buffers */ + if((ret=meth_init_tx_ring(priv))<0||(ret=meth_init_rx_ring(priv))<0){ + meth_free_tx_ring(priv); + meth_free_rx_ring(priv); + return ret; + } + + printk("SGI O2 Fast Ethernet rev. %ld\n", priv->regs->mac_ctrl >> 29); + + return 0; +} + +/* + * The devices + */ + +struct net_device meth_devs[1] = { + { init: meth_init, } /* init, nothing more */ +}; + +/* + * Finally, the module stuff + */ + +int meth_init_module(void) +{ + int result, device_present = 0; + + strcpy(meth_devs[0].name, "eth%d"); + + if ( (result = register_netdev(meth_devs)) ) + printk("meth: error %i registering device \"%s\"\n", + result, meth_devs->name); + else device_present++; +#ifndef METH_DEBUG + EXPORT_NO_SYMBOLS; +#endif + + return device_present ? 0 : -ENODEV; +} + +void meth_cleanup(void) +{ + kfree(meth_devs->priv); + unregister_netdev(meth_devs); + return; +} + +module_init(meth_init_module); +module_exit(meth_cleanup); --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/net/meth.h 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,273 @@ + +/* + * snull.h -- definitions for the network module + * + * Copyright (C) 2001 Alessandro Rubini and Jonathan Corbet + * Copyright (C) 2001 O'Reilly & Associates + * + * The source code in this file can be freely used, adapted, + * and redistributed in source or binary form, so long as an + * acknowledgment appears in derived source files. The citation + * should list that the code comes from the book "Linux Device + * Drivers" by Alessandro Rubini and Jonathan Corbet, published + * by O'Reilly & Associates. No warranty is attached; + * we cannot take responsibility for errors or fitness for use. + */ + +/* version dependencies have been confined to a separate file */ + +#define SGI_MFE (MACE_BASE+MACE_ENET) +/* (0xBF280000)*/ + +/* Tunable parameters */ +#define TX_RING_ENTRIES 64 /* 64-512?*/ + +#define RX_RING_ENTRIES 16 /* Do not change */ +/* Internal constants */ +#define TX_RING_BUFFER_SIZE (TX_RING_ENTRIES*sizeof(tx_packet)) +#define RX_BUFFER_SIZE 1546 /* ethenet packet size */ +#define METH_RX_BUFF_SIZE 4096 +#define RX_BUFFER_OFFSET (sizeof(rx_status_vector)+2) /* staus vector + 2 bytes of padding */ +#define RX_BUCKET_SIZE 256 + + + +/* For more detailed explanations of what each field menas, + see Nick's great comments to #defines below (or docs, if + you are lucky enough toget hold of them :)*/ + +/* tx status vector is written over tx command header upon + dma completion. */ + +typedef struct tx_status_vector { + u64 sent:1; /* always set to 1...*/ + u64 pad0:34;/* always set to 0 */ + u64 flags:9; /*I'm too lazy to specify each one separately at the moment*/ + u64 col_retry_cnt:4; /*collision retry count*/ + u64 len:16; /*Transmit length in bytes*/ +} tx_status_vector; + +/* + * Each packet is 128 bytes long. + * It consists of header, 0-3 concatination + * buffer pointers and up to 120 data bytes. + */ +typedef struct tx_packet_hdr { + u64 pad1:36; /*should be filled with 0 */ + u64 cat_ptr3_valid:1, /*Concatination pointer valid flags*/ + cat_ptr2_valid:1, + cat_ptr1_valid:1; + u64 tx_int_flag:1; /*Generate TX intrrupt when packet has been sent*/ + u64 term_dma_flag:1; /*Terminate transmit DMA on transmit abort conditions*/ + u64 data_offset:7; /*Starting byte offset in ring data block*/ + u64 data_len:16; /*Length of valid data in bytes-1*/ +} tx_packet_hdr; +typedef union tx_cat_ptr { + struct { + u64 pad2:16; /* should be 0 */ + u64 len:16; /*length of buffer data - 1*/ + u64 start_addr:29; /*Physical starting address*/ + u64 pad1:3; /* should be zero */ + } form; + u64 raw; +} tx_cat_ptr; + +typedef struct tx_packet { + union { + tx_packet_hdr header; + tx_status_vector res; + u64 raw; + }header; + union { + tx_cat_ptr cat_buf[3]; + char dt[120]; + } data; +} tx_packet; + +typedef union rx_status_vector { + struct { + u64 pad1:1;/*fill it with ones*/ + u64 pad2:15;/*fill with 0*/ + u64 ip_chk_sum:16; + u64 seq_num:5; + u64 mac_addr_match:1; + u64 mcast_addr_match:1; + u64 carrier_event_seen:1; + u64 bad_packet:1; + u64 long_event_seen:1; + u64 invalid_preamble:1; + u64 broadcast:1; + u64 multicast:1; + u64 crc_error:1; + u64 huh:1;/*???*/ + u64 rx_code_violation:1; + u64 rx_len:16; + } parsed; + u64 raw; +} rx_status_vector; + +typedef struct rx_packet { + rx_status_vector status; + u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */ + u16 pad2; + char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */ +} rx_packet; + +typedef struct meth_regs { + u64 mac_ctrl; /*0x00,rw,31:0*/ + u64 int_flags; /*0x08,rw,30:0*/ + u64 dma_ctrl; /*0x10,rw,15:0*/ + u64 timer; /*0x18,rw,5:0*/ + u64 int_tx; /*0x20,wo,0:0*/ + u64 int_rx; /*0x28,wo,9:4*/ + struct { + u32 tx_info_pad; + u32 rptr:16,wptr:16; + } tx_info; /*0x30,rw,31:0*/ + u64 tx_info_al; /*0x38,rw,31:0*/ + struct { + u32 rx_buff_pad1; + u32 rx_buff_pad2:8, + wptr:8, + rptr:8, + depth:8; + } rx_buff; /*0x40,ro,23:0*/ + u64 rx_buff_al1; /*0x48,ro,23:0*/ + u64 rx_buff_al2; /*0x50,ro,23:0*/ + u64 int_update; /*0x58,wo,31:0*/ + u32 phy_data_pad; + u32 phy_data; /*0x60,rw,16:0*/ + u32 phy_reg_pad; + u32 phy_registers; /*0x68,rw,9:0*/ + u64 phy_trans_go; /*0x70,wo,0:0*/ + u64 backoff_seed; /*0x78,wo,10:0*/ + u64 imq_reserved[4];/*0x80,ro,64:0(x4)*/ + /*===================================*/ + u64 mac_addr; /*0xA0,rw,47:0, I think it's MAC address, but I'm not sure*/ + u64 mcast_addr; /*0xA8,rw,47:0, This seems like secondary MAC address*/ + u64 mcast_filter; /*0xB0,rw,63:0*/ + u64 tx_ring_base; /*0xB8,rw,31:13*/ + /* Following are read-only debugging info register */ + u64 tx_pkt1_hdr; /*0xC0,ro,63:0*/ + u64 tx_pkt1_ptr[3]; /*0xC8,ro,63:0(x3)*/ + u64 tx_pkt2_hdr; /*0xE0,ro,63:0*/ + u64 tx_pkt2_ptr[3]; /*0xE8,ro,63:0(x3)*/ + /*===================================*/ + u32 rx_pad; + u32 rx_fifo; + u64 reserved[31]; +}meth_regs; + + /* Bits in METH_MAC */ + +#define SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 core is active */ +#define METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */ +#define METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loops internal MII bus */ + /* selects ignored */ +#define METH_100MBIT BIT(3) /* 0: 10meg mode, 1: 100meg mode */ +#define METH_PHY_MII BIT(4) /* 0: MII selected, 1: SIA selected */ + /* Note: when loopback is set this bit becomes collision control. Setting this bit will */ + /* cause a collision to be reported. */ + + /* Bits 5 and 6 are used to determine the the Destination address filter mode */ +#define METH_ACCEPT_MY 0 /* 00: Accept PHY address only */ +#define METH_ACCEPT_MCAST 0x20 /* 01: Accept physical, broadcast, and multicast filter matches only */ +#define METH_ACCEPT_AMCAST 0x40 /* 10: Accept physical, broadcast, and all multicast packets */ +#define METH_PROMISC 0x60 /* 11: Promiscious mode */ + +#define METH_PHY_LINK_FAIL BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link failure in PHY */ + +#define METH_MAC_IPG 0x1ffff00 + +#define METH_DEFAULT_IPG ((17<<15) | (11<<22) | (21<<8)) + /* 0x172e5c00 */ /* 23, 23, 23 */ /*0x54A9500 *//*21,21,21*/ + /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */ + /* The gap depends on the clock speed of the link, 80ns per increment for 100baseT, 800ns */ + /* per increment for 10BaseT */ + + /* Bits 15 through 21 are used to determine IPGR1 */ + + /* Bits 22 through 28 are used to determine IPGR2 */ + +#define METH_REV_SHIFT 29 /* Bits 29 through 31 are used to determine the revision */ + /* 000: Inital revision */ + /* 001: First revision, Improved TX concatenation */ + + +/* DMA control bits */ +#define METH_RX_OFFSET_SHIFT 12 /* Bits 12:14 of DMA control register indicate starting offset of packet data for RX operation */ +#define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != depth, interrupt is generted */ + +#define METH_DMA_TX_EN BIT(1) /* enable TX DMA */ +#define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */ +#define METH_DMA_RX_EN BIT(15) /* Enable RX */ +#define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */ + + +/* RX status bits */ + +#define METH_RX_ST_RCV_CODE_VIOLATION BIT(16) +#define METH_RX_ST_DRBL_NBL BIT(17) +#define METH_RX_ST_CRC_ERR BIT(18) +#define METH_RX_ST_MCAST_PKT BIT(19) +#define METH_RX_ST_BCAST_PKT BIT(20) +#define METH_RX_ST_INV_PREAMBLE_CTX BIT(21) +#define METH_RX_ST_LONG_EVT_SEEN BIT(22) +#define METH_RX_ST_BAD_PACKET BIT(23) +#define METH_RX_ST_CARRIER_EVT_SEEN BIT(24) +#define METH_RX_ST_MCAST_FILTER_MATCH BIT(25) +#define METH_RX_ST_PHYS_ADDR_MATCH BIT(26) + +#define METH_RX_STATUS_ERRORS \ + ( \ + METH_RX_ST_RCV_CODE_VIOLATION| \ + METH_RX_ST_CRC_ERR| \ + METH_RX_ST_INV_PREAMBLE_CTX| \ + METH_RX_ST_LONG_EVT_SEEN| \ + METH_RX_ST_BAD_PACKET| \ + METH_RX_ST_CARRIER_EVT_SEEN \ + ) + /* Bits in METH_INT */ + /* Write _1_ to corresponding bit to clear */ +#define METH_INT_TX_EMPTY BIT(0) /* 0: No interrupt pending, 1: The TX ring buffer is empty */ +#define METH_INT_TX_PKT BIT(1) /* 0: No interrupt pending */ + /* 1: A TX message had the INT request bit set, the packet has been sent. */ +#define METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure */ +#define METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */ + /* 1: A memory error occurred durring DMA, DMA stopped, Fatal */ +#define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */ +#define METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */ +#define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */ +#define METH_INT_RX_OVERFLOW BIT(7) /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped, FATAL */ + +#define METH_INT_RX_RPTR_MASK 0x0001F00 /* Bits 8 through 12 alias of RX read-pointer */ + + /* Bits 13 through 15 are always 0. */ + +#define METH_INT_TX_RPTR_MASK 0x1FF0000 /* Bits 16 through 24 alias of TX read-pointer */ + +#define METH_INT_SEQ_MASK 0x2E000000 /* Bits 25 through 29 are the starting seq number for the message at the */ + /* top of the queue */ + +#define METH_ERRORS ( \ + METH_INT_RX_OVERFLOW| \ + METH_INT_RX_UNDERFLOW| \ + METH_INT_MEM_ERROR| \ + METH_INT_TX_ABORT) + +#define METH_INT_MCAST_HASH BIT(30) /* If RX DMA is enabled the hash select logic output is latched here */ + +/* TX status bits */ +#define METH_TX_STATUS_DONE BIT(23) /* Packet was transmitted successfully */ + +/* Tx command header bits */ +#define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */ + +/* Phy MDIO interface busy flag */ +#define MDIO_BUSY BIT(16) +#define MDIO_DATA_MASK 0xFFFF +/* PHY defines */ +#define PHY_QS6612X 0x0181441 /* Quality TX */ +#define PHY_ICS1889 0x0015F41 /* ICS FX */ +#define PHY_ICS1890 0x0015F42 /* ICS TX */ +#define PHY_DP83840 0x20005C0 /* National TX */ --- linux-2.5.73/drivers/net/pcmcia/3c574_cs.c 2003-06-14 12:18:03.000000000 -0700 +++ 25/drivers/net/pcmcia/3c574_cs.c 2003-06-27 15:56:24.000000000 -0700 @@ -211,7 +211,6 @@ enum Window4 { /* Window 4: Xcvr/media struct el3_private { dev_link_t link; - struct net_device dev; dev_node_t node; struct net_device_stats stats; u16 advertising, partner; /* NWay media advertisement */ @@ -291,13 +290,12 @@ static dev_link_t *tc574_attach(void) flush_stale_links(); /* Create the PC card device object. */ - lp = kmalloc(sizeof(*lp), GFP_KERNEL); - if (!lp) + dev = alloc_etherdev(sizeof(struct el3_private)); + if (!dev) return NULL; - - memset(lp, 0, sizeof(*lp)); - link = &lp->link; dev = &lp->dev; - link->priv = dev->priv = link->irq.Instance = lp; + lp = dev->priv; + link = &lp->link; + link->priv = dev; init_timer(&link->release); link->release.function = &tc574_release; @@ -312,6 +310,7 @@ static dev_link_t *tc574_attach(void) for (i = 0; i < 4; i++) link->irq.IRQInfo2 |= 1 << irq_list[i]; link->irq.Handler = &el3_interrupt; + link->irq.Instance = dev; link->conf.Attributes = CONF_ENABLE_IRQ; link->conf.Vcc = 50; link->conf.IntType = INT_MEMORY_AND_IO; @@ -323,7 +322,6 @@ static dev_link_t *tc574_attach(void) dev->get_stats = &el3_get_stats; dev->do_ioctl = &el3_ioctl; dev->set_multicast_list = &set_rx_mode; - ether_setup(dev); dev->open = &el3_open; dev->stop = &el3_close; #ifdef HAVE_TX_TIMEOUT @@ -364,7 +362,7 @@ static dev_link_t *tc574_attach(void) static void tc574_detach(dev_link_t *link) { - struct el3_private *lp = link->priv; + struct net_device *dev = link->priv; dev_link_t **linkp; DEBUG(0, "3c574_detach(0x%p)\n", link); @@ -390,8 +388,8 @@ static void tc574_detach(dev_link_t *lin /* Unlink device structure, free bits */ *linkp = link->next; if (link->dev) - unregister_netdev(&lp->dev); - kfree(lp); + unregister_netdev(dev); + kfree(dev); } /* tc574_detach */ @@ -407,8 +405,8 @@ while ((last_ret=CardServices(last_fn=(f static void tc574_config(dev_link_t *link) { client_handle_t handle = link->handle; - struct el3_private *lp = link->priv; - struct net_device *dev = &lp->dev; + struct net_device *dev = link->priv; + struct el3_private *lp = dev->priv; tuple_t tuple; cisparse_t parse; unsigned short buf[32]; @@ -599,8 +597,7 @@ static int tc574_event(event_t event, in event_callback_args_t *args) { dev_link_t *link = args->client_data; - struct el3_private *lp = link->priv; - struct net_device *dev = &lp->dev; + struct net_device *dev = link->priv; DEBUG(1, "3c574_event(0x%06x)\n", event); @@ -856,7 +853,7 @@ static int el3_open(struct net_device *d tc574_reset(dev); lp->media.function = &media_check; - lp->media.data = (unsigned long)lp; + lp->media.data = (unsigned long) dev; lp->media.expires = jiffies + HZ; add_timer(&lp->media); @@ -939,8 +936,8 @@ static int el3_start_xmit(struct sk_buff /* The EL3 interrupt handler. */ static irqreturn_t el3_interrupt(int irq, void *dev_id, struct pt_regs *regs) { - struct el3_private *lp = dev_id; - struct net_device *dev = &lp->dev; + struct net_device *dev = (struct net_device *) dev_id; + struct el3_private *lp = dev->priv; ioaddr_t ioaddr, status; int work_budget = max_interrupt_work; int handled = 0; @@ -1032,8 +1029,8 @@ static irqreturn_t el3_interrupt(int irq */ static void media_check(unsigned long arg) { - struct el3_private *lp = (struct el3_private *)arg; - struct net_device *dev = &lp->dev; + struct net_device *dev = (struct net_device *) arg; + struct el3_private *lp = dev->priv; ioaddr_t ioaddr = dev->base_addr; unsigned long flags; unsigned short /* cable, */ media, partner; --- linux-2.5.73/drivers/net/pcmcia/3c589_cs.c 2003-06-14 12:18:34.000000000 -0700 +++ 25/drivers/net/pcmcia/3c589_cs.c 2003-06-27 15:56:24.000000000 -0700 @@ -106,7 +106,6 @@ enum RxFilter { struct el3_private { dev_link_t link; - struct net_device dev; dev_node_t node; struct net_device_stats stats; /* For transceiver monitoring */ @@ -213,14 +212,14 @@ static dev_link_t *tc589_attach(void) flush_stale_links(); /* Create new ethernet device */ - lp = kmalloc(sizeof(*lp), GFP_KERNEL); - if (!lp) return NULL; - memset(lp, 0, sizeof(*lp)); + dev = alloc_etherdev(sizeof(struct el3_private)); + if (!dev) + return NULL; + lp = dev->priv; + link = &lp->link; + link->priv = dev; + spin_lock_init(&lp->lock); - - link = &lp->link; dev = &lp->dev; - link->priv = dev->priv = link->irq.Instance = lp; - init_timer(&link->release); link->release.function = &tc589_release; link->release.data = (unsigned long)link; @@ -234,6 +233,7 @@ static dev_link_t *tc589_attach(void) for (i = 0; i < 4; i++) link->irq.IRQInfo2 |= 1 << irq_list[i]; link->irq.Handler = &el3_interrupt; + link->irq.Instance = dev; link->conf.Attributes = CONF_ENABLE_IRQ; link->conf.Vcc = 50; link->conf.IntType = INT_MEMORY_AND_IO; @@ -246,7 +246,6 @@ static dev_link_t *tc589_attach(void) dev->set_config = &el3_config; dev->get_stats = &el3_get_stats; dev->set_multicast_list = &set_multicast_list; - ether_setup(dev); dev->open = &el3_open; dev->stop = &el3_close; #ifdef HAVE_TX_TIMEOUT @@ -288,7 +287,7 @@ static dev_link_t *tc589_attach(void) static void tc589_detach(dev_link_t *link) { - struct el3_private *lp = link->priv; + struct net_device *dev = link->priv; dev_link_t **linkp; DEBUG(0, "3c589_detach(0x%p)\n", link); @@ -314,8 +313,8 @@ static void tc589_detach(dev_link_t *lin /* Unlink device structure, free bits */ *linkp = link->next; if (link->dev) - unregister_netdev(&lp->dev); - kfree(lp); + unregister_netdev(dev); + kfree(dev); } /* tc589_detach */ @@ -333,8 +332,8 @@ while ((last_ret=CardServices(last_fn=(f static void tc589_config(dev_link_t *link) { client_handle_t handle = link->handle; - struct el3_private *lp = link->priv; - struct net_device *dev = &lp->dev; + struct net_device *dev = link->priv; + struct el3_private *lp = dev->priv; tuple_t tuple; cisparse_t parse; u16 buf[32], *phys_addr; @@ -487,8 +486,7 @@ static int tc589_event(event_t event, in event_callback_args_t *args) { dev_link_t *link = args->client_data; - struct el3_private *lp = link->priv; - struct net_device *dev = &lp->dev; + struct net_device *dev = link->priv; DEBUG(1, "3c589_event(0x%06x)\n", event); @@ -738,7 +736,7 @@ static int el3_open(struct net_device *d tc589_reset(dev); init_timer(&lp->media); lp->media.function = &media_check; - lp->media.data = (unsigned long)lp; + lp->media.data = (unsigned long) dev; lp->media.expires = jiffies + HZ; add_timer(&lp->media); @@ -818,8 +816,8 @@ static int el3_start_xmit(struct sk_buff /* The EL3 interrupt handler. */ static irqreturn_t el3_interrupt(int irq, void *dev_id, struct pt_regs *regs) { - struct el3_private *lp = dev_id; - struct net_device *dev = &lp->dev; + struct net_device *dev = (struct net_device *) dev_id; + struct el3_private *lp = dev->priv; ioaddr_t ioaddr, status; int i = 0, handled = 1; @@ -903,8 +901,8 @@ static irqreturn_t el3_interrupt(int irq static void media_check(unsigned long arg) { - struct el3_private *lp = (struct el3_private *)(arg); - struct net_device *dev = &lp->dev; + struct net_device *dev = (struct net_device *)(arg); + struct el3_private *lp = dev->priv; ioaddr_t ioaddr = dev->base_addr; u16 media, errs; unsigned long flags; --- linux-2.5.73/drivers/net/pcmcia/fmvj18x_cs.c 2003-06-14 12:18:25.000000000 -0700 +++ 25/drivers/net/pcmcia/fmvj18x_cs.c 2003-06-27 15:56:24.000000000 -0700 @@ -130,7 +130,6 @@ typedef enum { MBH10302, MBH10304, TDK, */ typedef struct local_info_t { dev_link_t link; - struct net_device dev; dev_node_t node; struct net_device_stats stats; long open_time; @@ -273,11 +272,12 @@ static dev_link_t *fmvj18x_attach(void) flush_stale_links(); /* Make up a FMVJ18x specific data structure */ - lp = kmalloc(sizeof(*lp), GFP_KERNEL); - if (!lp) return NULL; - memset(lp, 0, sizeof(*lp)); - link = &lp->link; dev = &lp->dev; - link->priv = dev->priv = link->irq.Instance = lp; + dev = alloc_etherdev(sizeof(local_info_t)); + if (!dev) + return NULL; + lp = dev->priv; + link = &lp->link; + link->priv = dev; init_timer(&link->release); link->release.function = &fmvj18x_release; @@ -297,6 +297,7 @@ static dev_link_t *fmvj18x_attach(void) for (i = 0; i < 4; i++) link->irq.IRQInfo2 |= 1 << irq_list[i]; link->irq.Handler = &fjn_interrupt; + link->irq.Instance = dev; /* General socket configuration */ link->conf.Attributes = CONF_ENABLE_IRQ; @@ -309,7 +310,6 @@ static dev_link_t *fmvj18x_attach(void) dev->set_config = &fjn_config; dev->get_stats = &fjn_get_stats; dev->set_multicast_list = &set_rx_mode; - ether_setup(dev); dev->open = &fjn_open; dev->stop = &fjn_close; #ifdef HAVE_TX_TIMEOUT @@ -344,7 +344,7 @@ static dev_link_t *fmvj18x_attach(void) static void fmvj18x_detach(dev_link_t *link) { - local_info_t *lp = link->priv; + struct net_device *dev = link->priv; dev_link_t **linkp; DEBUG(0, "fmvj18x_detach(0x%p)\n", link); @@ -371,8 +371,8 @@ static void fmvj18x_detach(dev_link_t *l /* Unlink device structure, free pieces */ *linkp = link->next; if (link->dev) - unregister_netdev(&lp->dev); - kfree(lp); + unregister_netdev(dev); + kfree(dev); } /* fmvj18x_detach */ @@ -423,8 +423,8 @@ static int ungermann_try_io_port(dev_lin static void fmvj18x_config(dev_link_t *link) { client_handle_t handle = link->handle; - local_info_t *lp = link->priv; - struct net_device *dev = &lp->dev; + struct net_device *dev = link->priv; + local_info_t *lp = dev->priv; tuple_t tuple; cisparse_t parse; u_short buf[32]; @@ -704,8 +704,7 @@ static int fmvj18x_setup_mfc(dev_link_t memreq_t mem; u_char *base; int i, j; - local_info_t *lp = link->priv; - struct net_device *dev = &lp->dev; + struct net_device *dev = link->priv; ioaddr_t ioaddr; /* Allocate a small memory window */ @@ -776,8 +775,7 @@ static int fmvj18x_event(event_t event, event_callback_args_t *args) { dev_link_t *link = args->client_data; - local_info_t *lp = link->priv; - struct net_device *dev = &lp->dev; + struct net_device *dev = link->priv; DEBUG(1, "fmvj18x_event(0x%06x)\n", event); @@ -847,8 +845,8 @@ module_exit(exit_fmvj18x_cs); static irqreturn_t fjn_interrupt(int irq, void *dev_id, struct pt_regs *regs) { - local_info_t *lp = dev_id; - struct net_device *dev = &lp->dev; + struct net_device *dev = dev_id; + local_info_t *lp = dev->priv; ioaddr_t ioaddr; unsigned short tx_stat, rx_stat; --- linux-2.5.73/drivers/net/pcmcia/nmclan_cs.c 2003-06-14 12:17:57.000000000 -0700 +++ 25/drivers/net/pcmcia/nmclan_cs.c 2003-06-27 15:56:24.000000000 -0700 @@ -359,7 +359,6 @@ typedef struct _mace_statistics { typedef struct _mace_private { dev_link_t link; - struct net_device dev; dev_node_t node; struct net_device_stats linux_stats; /* Linux statistics counters */ mace_statistics mace_stats; /* MACE chip statistics counters */ @@ -476,12 +475,13 @@ static dev_link_t *nmclan_attach(void) flush_stale_links(); /* Create new ethernet device */ - lp = kmalloc(sizeof(*lp), GFP_KERNEL); - if (!lp) return NULL; - memset(lp, 0, sizeof(*lp)); - link = &lp->link; dev = &lp->dev; - link->priv = dev->priv = link->irq.Instance = lp; - + dev = alloc_etherdev(sizeof(mace_private)); + if (!dev) + return NULL; + lp = dev->priv; + link = &lp->link; + link->priv = dev; + init_timer(&link->release); link->release.function = &nmclan_release; link->release.data = (u_long)link; @@ -496,6 +496,7 @@ static dev_link_t *nmclan_attach(void) for (i = 0; i < 4; i++) link->irq.IRQInfo2 |= 1 << irq_list[i]; link->irq.Handler = &mace_interrupt; + link->irq.Instance = dev; link->conf.Attributes = CONF_ENABLE_IRQ; link->conf.Vcc = 50; link->conf.IntType = INT_MEMORY_AND_IO; @@ -510,7 +511,6 @@ static dev_link_t *nmclan_attach(void) dev->get_stats = &mace_get_stats; dev->set_multicast_list = &set_multicast_list; dev->do_ioctl = &mace_ioctl; - ether_setup(dev); dev->open = &mace_open; dev->stop = &mace_close; #ifdef HAVE_TX_TIMEOUT @@ -550,7 +550,7 @@ nmclan_detach static void nmclan_detach(dev_link_t *link) { - mace_private *lp = link->priv; + struct net_device *dev = link->priv; dev_link_t **linkp; DEBUG(0, "nmclan_detach(0x%p)\n", link); @@ -576,8 +576,8 @@ static void nmclan_detach(dev_link_t *li /* Unlink device structure, free bits */ *linkp = link->next; if (link->dev) - unregister_netdev(&lp->dev); - kfree(lp); + unregister_netdev(dev); + kfree(dev); } /* nmclan_detach */ @@ -710,8 +710,8 @@ while ((last_ret=CardServices(last_fn=(f static void nmclan_config(dev_link_t *link) { client_handle_t handle = link->handle; - mace_private *lp = link->priv; - struct net_device *dev = &lp->dev; + struct net_device *dev = link->priv;; + mace_private *lp = dev->priv; tuple_t tuple; cisparse_t parse; u_char buf[64]; @@ -836,8 +836,7 @@ static int nmclan_event(event_t event, i event_callback_args_t *args) { dev_link_t *link = args->client_data; - mace_private *lp = link->priv; - struct net_device *dev = &lp->dev; + struct net_device *dev = link->priv; DEBUG(1, "nmclan_event(0x%06x)\n", event); @@ -1145,8 +1144,8 @@ mace_interrupt ---------------------------------------------------------------------------- */ static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs) { - mace_private *lp = (mace_private *)dev_id; - struct net_device *dev = &lp->dev; + struct net_device *dev = (struct net_device *) dev_id; + mace_private *lp = dev->priv; ioaddr_t ioaddr = dev->base_addr; int status; int IntrCnt = MACE_MAX_IR_ITERATIONS; --- linux-2.5.73/drivers/net/pcmcia/smc91c92_cs.c 2003-06-14 12:18:25.000000000 -0700 +++ 25/drivers/net/pcmcia/smc91c92_cs.c 2003-06-27 15:56:24.000000000 -0700 @@ -113,7 +113,6 @@ static dev_link_t *dev_list; struct smc_private { dev_link_t link; - struct net_device dev; spinlock_t lock; u_short manfid; u_short cardid; @@ -344,10 +343,13 @@ static dev_link_t *smc91c92_attach(void) flush_stale_links(); /* Create new ethernet device */ - smc = kmalloc(sizeof(struct smc_private), GFP_KERNEL); - if (!smc) return NULL; - memset(smc, 0, sizeof(struct smc_private)); - link = &smc->link; dev = &smc->dev; + dev = alloc_etherdev(sizeof(struct smc_private)); + if (!dev) + return NULL; + smc = dev->priv; + link = &smc->link; + link->priv = dev; + spin_lock_init(&smc->lock); init_timer(&link->release); link->release.function = &smc91c92_release; @@ -363,6 +365,7 @@ static dev_link_t *smc91c92_attach(void) for (i = 0; i < 4; i++) link->irq.IRQInfo2 |= 1 << irq_list[i]; link->irq.Handler = &smc_interrupt; + link->irq.Instance = dev; link->conf.Attributes = CONF_ENABLE_IRQ; link->conf.Vcc = 50; link->conf.IntType = INT_MEMORY_AND_IO; @@ -373,7 +376,6 @@ static dev_link_t *smc91c92_attach(void) dev->get_stats = &smc_get_stats; dev->set_config = &s9k_config; dev->set_multicast_list = &set_rx_mode; - ether_setup(dev); dev->open = &smc_open; dev->stop = &smc_close; dev->do_ioctl = &smc_ioctl; @@ -381,7 +383,6 @@ static dev_link_t *smc91c92_attach(void) dev->tx_timeout = smc_tx_timeout; dev->watchdog_timeo = TX_TIMEOUT; #endif - dev->priv = link->priv = link->irq.Instance = smc; smc->mii_if.dev = dev; smc->mii_if.mdio_read = mdio_read; @@ -421,7 +422,7 @@ static dev_link_t *smc91c92_attach(void) static void smc91c92_detach(dev_link_t *link) { - struct smc_private *smc = link->priv; + struct net_device *dev = link->priv; dev_link_t **linkp; DEBUG(0, "smc91c92_detach(0x%p)\n", link); @@ -447,8 +448,8 @@ static void smc91c92_detach(dev_link_t * /* Unlink device structure, free bits */ *linkp = link->next; if (link->dev) - unregister_netdev(&smc->dev); - kfree(smc); + unregister_netdev(dev); + kfree(dev); } /* smc91c92_detach */ @@ -502,7 +503,8 @@ static int get_tuple(int fn, client_hand static int mhz_3288_power(dev_link_t *link) { - struct smc_private *smc = link->priv; + struct net_device *dev = link->priv; + struct smc_private *smc = dev->priv; u_char tmp; /* Read the ISR twice... */ @@ -523,8 +525,8 @@ static int mhz_3288_power(dev_link_t *li static int mhz_mfc_config(dev_link_t *link) { - struct smc_private *smc = link->priv; - struct net_device *dev = &smc->dev; + struct net_device *dev = link->priv; + struct smc_private *smc = dev->priv; tuple_t tuple; cisparse_t parse; u_char buf[255]; @@ -590,8 +592,7 @@ static int mhz_mfc_config(dev_link_t *li static int mhz_setup(dev_link_t *link) { client_handle_t handle = link->handle; - struct smc_private *smc = link->priv; - struct net_device *dev = &smc->dev; + struct net_device *dev = link->priv; tuple_t tuple; cisparse_t parse; u_char buf[255], *station_addr; @@ -638,8 +639,8 @@ static int mhz_setup(dev_link_t *link) static void mot_config(dev_link_t *link) { - struct smc_private *smc = link->priv; - struct net_device *dev = &smc->dev; + struct net_device *dev = link->priv; + struct smc_private *smc = dev->priv; ioaddr_t ioaddr = dev->base_addr; ioaddr_t iouart = link->io.BasePort2; @@ -659,8 +660,7 @@ static void mot_config(dev_link_t *link) static int mot_setup(dev_link_t *link) { - struct smc_private *smc = link->priv; - struct net_device *dev = &smc->dev; + struct net_device *dev = link->priv; ioaddr_t ioaddr = dev->base_addr; int i, wait, loop; u_int addr; @@ -694,8 +694,7 @@ static int mot_setup(dev_link_t *link) static int smc_config(dev_link_t *link) { - struct smc_private *smc = link->priv; - struct net_device *dev = &smc->dev; + struct net_device *dev = link->priv; tuple_t tuple; cisparse_t parse; u_char buf[255]; @@ -727,8 +726,7 @@ static int smc_config(dev_link_t *link) static int smc_setup(dev_link_t *link) { client_handle_t handle = link->handle; - struct smc_private *smc = link->priv; - struct net_device *dev = &smc->dev; + struct net_device *dev = link->priv; tuple_t tuple; cisparse_t parse; cistpl_lan_node_id_t *node_id; @@ -755,7 +753,6 @@ static int smc_setup(dev_link_t *link) return 0; } } - /* Try the third string in the Version 1 Version/ID tuple. */ tuple.DesiredTuple = CISTPL_VERS_1; if (first_tuple(handle, &tuple, &parse) != CS_SUCCESS) @@ -771,8 +768,7 @@ static int smc_setup(dev_link_t *link) static int osi_config(dev_link_t *link) { - struct smc_private *smc = link->priv; - struct net_device *dev = &smc->dev; + struct net_device *dev = link->priv; static ioaddr_t com[4] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; int i, j; @@ -806,8 +802,7 @@ static int osi_config(dev_link_t *link) static int osi_setup(dev_link_t *link, u_short manfid, u_short cardid) { client_handle_t handle = link->handle; - struct smc_private *smc = link->priv; - struct net_device *dev = &smc->dev; + struct net_device *dev = link->priv; tuple_t tuple; u_char buf[255]; int i; @@ -862,8 +857,7 @@ static int osi_setup(dev_link_t *link, u static int check_sig(dev_link_t *link) { - struct smc_private *smc = link->priv; - struct net_device *dev = &smc->dev; + struct net_device *dev = link->priv; ioaddr_t ioaddr = dev->base_addr; int width; u_short s; @@ -921,8 +915,8 @@ if (ret != CS_SUCCESS) { cs_error(link-> static void smc91c92_config(dev_link_t *link) { client_handle_t handle = link->handle; - struct smc_private *smc = link->priv; - struct net_device *dev = &smc->dev; + struct net_device *dev = link->priv; + struct smc_private *smc = dev->priv; tuple_t tuple; cisparse_t parse; u_short buf[32]; @@ -1090,7 +1084,6 @@ config_failed: /* CS_EXIT_TEST() calls static void smc91c92_release(u_long arg) { dev_link_t *link = (dev_link_t *)arg; - struct smc_private *smc = link->priv; DEBUG(0, "smc91c92_release(0x%p)\n", link); @@ -1105,6 +1098,8 @@ static void smc91c92_release(u_long arg) CardServices(ReleaseIO, link->handle, &link->io); CardServices(ReleaseIRQ, link->handle, &link->irq); if (link->win) { + struct net_device *dev = link->priv; + struct smc_private *smc = dev->priv; iounmap(smc->base); CardServices(ReleaseWindow, link->win); } @@ -1126,8 +1121,8 @@ static int smc91c92_event(event_t event, event_callback_args_t *args) { dev_link_t *link = args->client_data; - struct smc_private *smc = link->priv; - struct net_device *dev = &smc->dev; + struct net_device *dev = link->priv; + struct smc_private *smc = dev->priv; int i; DEBUG(1, "smc91c92_event(0x%06x)\n", event); @@ -1302,7 +1297,7 @@ static int smc_open(struct net_device *d smc_reset(dev); init_timer(&smc->media); smc->media.function = &media_check; - smc->media.data = (u_long)smc; + smc->media.data = (u_long) dev; smc->media.expires = jiffies + HZ; add_timer(&smc->media); @@ -1576,8 +1571,8 @@ static void smc_eph_irq(struct net_devic static irqreturn_t smc_interrupt(int irq, void *dev_id, struct pt_regs *regs) { - struct smc_private *smc = dev_id; - struct net_device *dev = &smc->dev; + struct net_device *dev = dev_id; + struct smc_private *smc = dev->priv; ioaddr_t ioaddr; u_short saved_bank, saved_pointer, mask, status; unsigned int handled = 1; @@ -1967,8 +1962,8 @@ static void smc_reset(struct net_device static void media_check(u_long arg) { - struct smc_private *smc = (struct smc_private *)(arg); - struct net_device *dev = &smc->dev; + struct net_device *dev = (struct net_device *) arg; + struct smc_private *smc = dev->priv; ioaddr_t ioaddr = dev->base_addr; u_short i, media, saved_bank; u_short link; --- linux-2.5.73/drivers/net/pppoe.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/net/pppoe.c 2003-06-27 15:56:28.000000000 -0700 @@ -77,27 +77,14 @@ #include -static int __attribute__((unused)) pppoe_debug = 7; #define PPPOE_HASH_BITS 4 #define PPPOE_HASH_SIZE (1<sk , skb)) + if (!__pppoe_xmit( relay_po->sk, skb)) goto abort_put; } else { sock_queue_rcv_skb(sk, skb); @@ -460,12 +444,12 @@ abort: return NET_RX_SUCCESS; /* Lies... :-) */ } -struct packet_type pppoes_ptype = { +static struct packet_type pppoes_ptype = { .type = __constant_htons(ETH_P_PPP_SES), .func = pppoe_rcv, }; -struct packet_type pppoed_ptype = { +static struct packet_type pppoed_ptype = { .type = __constant_htons(ETH_P_PPP_DISC), .func = pppoe_disc_rcv, }; @@ -522,7 +506,7 @@ frees: sk_free(sk); goto out; } -int pppoe_release(struct socket *sock) +static int pppoe_release(struct socket *sock) { struct sock *sk = sock->sk; struct pppox_opt *po; @@ -559,7 +543,7 @@ int pppoe_release(struct socket *sock) } -int pppoe_connect(struct socket *sock, struct sockaddr *uservaddr, +static int pppoe_connect(struct socket *sock, struct sockaddr *uservaddr, int sockaddr_len, int flags) { struct sock *sk = sock->sk; @@ -648,7 +632,7 @@ err_put: } -int pppoe_getname(struct socket *sock, struct sockaddr *uaddr, +static int pppoe_getname(struct socket *sock, struct sockaddr *uaddr, int *usockaddr_len, int peer) { int len = sizeof(struct sockaddr_pppox); @@ -667,7 +651,7 @@ int pppoe_getname(struct socket *sock, s } -int pppoe_ioctl(struct socket *sock, unsigned int cmd, +static int pppoe_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg) { struct sock *sk = sock->sk; @@ -769,7 +753,7 @@ int pppoe_ioctl(struct socket *sock, uns } -int pppoe_sendmsg(struct kiocb *iocb, struct socket *sock, struct msghdr *m, +static int pppoe_sendmsg(struct kiocb *iocb, struct socket *sock, struct msghdr *m, int total_len) { struct sk_buff *skb = NULL; @@ -847,7 +831,7 @@ end: * xmit function for internal use. * ***********************************************************************/ -int __pppoe_xmit(struct sock *sk, struct sk_buff *skb) +static int __pppoe_xmit(struct sock *sk, struct sk_buff *skb) { struct pppox_opt *po = pppox_sk(sk); struct net_device *dev = po->pppoe_dev; @@ -921,16 +905,18 @@ abort: * sends PPP frame over PPPoE socket * ***********************************************************************/ -int pppoe_xmit(struct ppp_channel *chan, struct sk_buff *skb) +static int pppoe_xmit(struct ppp_channel *chan, struct sk_buff *skb) { struct sock *sk = (struct sock *) chan->private; return __pppoe_xmit(sk, skb); } -struct ppp_channel_ops pppoe_chan_ops = { pppoe_xmit , NULL }; +static struct ppp_channel_ops pppoe_chan_ops = { + .start_xmit = pppoe_xmit, +}; -int pppoe_recvmsg(struct kiocb *iocb, struct socket *sock, +static int pppoe_recvmsg(struct kiocb *iocb, struct socket *sock, struct msghdr *m, int total_len, int flags) { struct sock *sk = sock->sk; @@ -1029,8 +1015,9 @@ static void *pppoe_seq_next(struct seq_f goto out; } po = v; - po = po->next; - if (!po) { + if (po->next) + po = po->next; + else { int hash = hash_item(po->pppoe_pa.sid, po->pppoe_pa.remote); while (++hash < PPPOE_HASH_SIZE) { @@ -1071,7 +1058,7 @@ static struct file_operations pppoe_seq_ /* ->ioctl are set at pppox_create */ -struct proto_ops pppoe_ops = { +static struct proto_ops pppoe_ops = { .family = AF_PPPOX, .owner = THIS_MODULE, .release = pppoe_release, @@ -1090,14 +1077,14 @@ struct proto_ops pppoe_ops = { .mmap = sock_no_mmap }; -struct pppox_proto pppoe_proto = { +static struct pppox_proto pppoe_proto = { .create = pppoe_create, .ioctl = pppoe_ioctl, .owner = THIS_MODULE, }; -int __init pppoe_init(void) +static int __init pppoe_init(void) { int err = register_pppox_proto(PX_PROTO_OE, &pppoe_proto); @@ -1125,7 +1112,7 @@ out_unregister: goto out; } -void __exit pppoe_exit(void) +static void __exit pppoe_exit(void) { unregister_pppox_proto(PX_PROTO_OE); dev_remove_pack(&pppoes_ptype); --- linux-2.5.73/drivers/net/sb1250-mac.c 2003-06-14 12:18:33.000000000 -0700 +++ 25/drivers/net/sb1250-mac.c 2003-06-27 15:56:24.000000000 -0700 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2001 Broadcom Corporation + * Copyright (C) 2001,2002,2003 Broadcom Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -17,17 +17,21 @@ */ /* - This driver is designed for the Broadcom BCM12500 SOC chip's built-in + This driver is designed for the Broadcom SiByte SOC built-in Ethernet controllers. - The author may be reached as mpl@broadcom.com + Written by Mitch Lichtenberg at Broadcom Corp. */ + +#define CONFIG_SBMAC_COALESCE + /* A few user-configurable values. These may be modified when a driver module is loaded. */ static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ +static int noisy_mii = 1; /* mii status msgs */ /* Used to pass the media type, etc. Both 'options[]' and 'full_duplex[]' should exist for driver @@ -41,6 +45,10 @@ static int options[MAX_UNITS] = {-1, -1, static int full_duplex[MAX_UNITS] = {-1, -1, -1}; #endif +#ifdef CONFIG_SBMAC_COALESCE +static int int_pktcnt = 0; +static int int_timeout = 0; +#endif /* Operational parameters that usually are not changed. */ @@ -59,22 +67,21 @@ static int full_duplex[MAX_UNITS] = {-1, #include #include #include +#include #include #include #include #include -#include #include #include #include /* Processor type for cache alignment. */ #include #include -#include -#include +#include /* This is only here until the firmware is ready. In that case, the firmware leaves the ethernet address in the register for us. */ -#ifdef CONFIG_SWARM_STANDALONE +#ifdef CONFIG_SIBYTE_STANDALONE #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00" #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01" #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02" @@ -84,23 +91,29 @@ static int full_duplex[MAX_UNITS] = {-1, /* These identify the driver base version and may not be removed. */ #if 0 static char version1[] __devinitdata = -"sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg (mpl@broadcom.com)\n"; +"sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n"; #endif -MODULE_AUTHOR("Mitch Lichtenberg (mpl@broadcom.com)"); -MODULE_DESCRIPTION("Broadcom BCM12500 SOC GB Ethernet driver"); +MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)"); +MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver"); MODULE_PARM(debug, "i"); +MODULE_PARM(noisy_mii, "i"); MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i"); MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i"); +MODULE_PARM(int_pktcnt, "i"); +MODULE_PARM(int_timeout, "i"); +#include #include #include #include #include #include +#include +#include /********************************************************************** @@ -109,8 +122,6 @@ MODULE_PARM(full_duplex, "1-" __MODULE_S typedef unsigned long sbmac_port_t; -typedef uint64_t sbmac_physaddr_t; -typedef uint64_t sbmac_enetaddr_t; typedef enum { sbmac_speed_auto, sbmac_speed_10, sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t; @@ -134,24 +145,19 @@ typedef enum { sbmac_state_uninit, sbmac (d)->sbdma_dscrtable : (d)->f+1) -#define CACHELINESIZE 32 -#define NUMCACHEBLKS(x) (((x)+CACHELINESIZE-1)/CACHELINESIZE) -#define KMALLOC(x) kmalloc((x),GFP_KERNEL) -#define KFREE(x) kfree(x) -#define KVTOPHYS(x) virt_to_bus((void *)(x)) +#define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES) +#define SBMAC_READCSR(t) in64((unsigned long)t) +#define SBMAC_WRITECSR(t,v) out64(v, (unsigned long)t) -#define SBMAC_READCSR(t) (in64((unsigned long)(t))) -#define SBMAC_WRITECSR(t,v) (out64(v, (unsigned long)(t))) - -#define PKSEG1(x) ((sbmac_port_t) KSEG1ADDR(x)) #define SBMAC_MAX_TXDESCR 32 #define SBMAC_MAX_RXDESCR 32 #define ETHER_ALIGN 2 #define ETHER_ADDR_LEN 6 -#define ENET_PACKET_SIZE 1518 +#define ENET_PACKET_SIZE 1518 +/*#define ENET_PACKET_SIZE 9216 */ /********************************************************************** * DMA Descriptor structure @@ -163,7 +169,6 @@ typedef struct sbdmadscr_s { } sbdmadscr_t; typedef unsigned long paddr_t; -typedef unsigned long vaddr_t; /********************************************************************** * DMA Controller structure @@ -178,8 +183,13 @@ typedef struct sbmacdma_s { struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */ int sbdma_channel; /* channel number */ - int sbdma_txdir; /* direction (1=transmit) */ - int sbdma_maxdescr; /* total # of descriptors in ring */ + int sbdma_txdir; /* direction (1=transmit) */ + int sbdma_maxdescr; /* total # of descriptors in ring */ +#ifdef CONFIG_SBMAC_COALESCE + int sbdma_int_pktcnt; /* # descriptors rx/tx before interrupt*/ + int sbdma_int_timeout; /* # usec rx/tx interrupt */ +#endif + sbmac_port_t sbdma_config0; /* DMA config register 0 */ sbmac_port_t sbdma_config1; /* DMA config register 1 */ sbmac_port_t sbdma_dscrbase; /* Descriptor base address */ @@ -198,7 +208,6 @@ typedef struct sbmacdma_s { paddr_t sbdma_dscrtable_phys; /* and also the phys addr */ sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */ sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */ - } sbmacdma_t; @@ -218,10 +227,10 @@ struct sbmac_softc { struct net_device_stats sbm_stats; int sbm_devflags; /* current device flags */ - int sbm_phy_oldbmsr; - int sbm_phy_oldanlpar; - int sbm_phy_oldk1stsr; - int sbm_phy_oldlinkstat; + int sbm_phy_oldbmsr; + int sbm_phy_oldanlpar; + int sbm_phy_oldk1stsr; + int sbm_phy_oldlinkstat; int sbm_buffersize; unsigned char sbm_phys[2]; @@ -230,7 +239,7 @@ struct sbmac_softc { * Controller-specific things */ - sbmac_port_t sbm_base; /* MAC's base address */ + unsigned long sbm_base; /* MAC's base address */ sbmac_state_t sbm_state; /* current state */ sbmac_port_t sbm_macenable; /* MAC Enable Register */ @@ -246,11 +255,12 @@ struct sbmac_softc { sbmac_duplex_t sbm_duplex; /* current duplex */ sbmac_fc_t sbm_fc; /* current flow control setting */ - u_char sbm_hwaddr[ETHER_ADDR_LEN]; + unsigned char sbm_hwaddr[ETHER_ADDR_LEN]; sbmacdma_t sbm_txdma; /* for now, only use channel 0 */ sbmacdma_t sbm_rxdma; - + int rx_hw_checksum; + int sbe_idx; }; @@ -267,7 +277,7 @@ static void sbdma_initctx(sbmacdma_t *d, int chan, int txrx, int maxdescr); -static void sbdma_channel_start(sbmacdma_t *d); +static void sbdma_channel_start(sbmacdma_t *d, int rxtx); static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m); static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m); static void sbdma_emptyring(sbmacdma_t *d); @@ -279,12 +289,11 @@ static void sbmac_channel_start(struct s static void sbmac_channel_stop(struct sbmac_softc *s); static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t); static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff); -/*static void sbmac_init_and_start(struct sbmac_softc *sc);*/ static uint64_t sbmac_addr2reg(unsigned char *ptr); static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs); static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev); static void sbmac_setmulti(struct sbmac_softc *sc); -static int sbmac_init(struct net_device *dev); +static int sbmac_init(struct net_device *dev, int idx); static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed); static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc); @@ -308,6 +317,8 @@ static void sbmac_mii_write(struct sbmac * Globals ********************************************************************* */ +static uint64_t sbmac_orig_hwaddr[MAX_UNITS]; + /********************************************************************** * MDIO constants @@ -328,8 +339,8 @@ static void sbmac_mii_write(struct sbmac #define BMCR_DUPLEX 0x0100 #define BMCR_COLTEST 0x0080 #define BMCR_SPEED1 0x0040 -#define BMCR_SPEED1000 (BMCR_SPEED1|BMCR_SPEED0) -#define BMCR_SPEED100 (BMCR_SPEED0) +#define BMCR_SPEED1000 BMCR_SPEED1 +#define BMCR_SPEED100 BMCR_SPEED0 #define BMCR_SPEED10 0 #define BMSR_100BT4 0x8000 @@ -437,6 +448,8 @@ static void sbmac_mii_write(struct sbmac #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */ +#define ENABLE 1 +#define DISABLE 0 /********************************************************************** * SBMAC_MII_SYNC(s) @@ -490,7 +503,8 @@ static void sbmac_mii_senddata(struct sb curmask = 1 << (bitcnt - 1); for (i = 0; i < bitcnt; i++) { - if (data & curmask) bits |= M_MAC_MDIO_OUT; + if (data & curmask) + bits |= M_MAC_MDIO_OUT; else bits &= ~M_MAC_MDIO_OUT; SBMAC_WRITECSR(s->sbm_mdio,bits); SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC); @@ -571,7 +585,8 @@ static unsigned int sbmac_mii_read(struc regval <<= 1; if (error == 0) { - if (SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN) regval |= 1; + if (SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN) + regval |= 1; } SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | M_MAC_MDC); @@ -581,7 +596,8 @@ static unsigned int sbmac_mii_read(struc /* Switch back to output */ SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT); - if (error == 0) return regval; + if (error == 0) + return regval; return 0; } @@ -651,20 +667,68 @@ static void sbdma_initctx(sbmacdma_t *d, d->sbdma_channel = chan; d->sbdma_txdir = txrx; +#if 0 + /* RMON clearing */ + s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING; +#endif + + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)), 0); + SBMAC_WRITECSR(KSEG1ADDR( + A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)), 0); + /* * initialize register pointers */ d->sbdma_config0 = - PKSEG1(s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0)); + s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0); d->sbdma_config1 = - PKSEG1(s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0)); + s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1); d->sbdma_dscrbase = - PKSEG1(s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE)); + s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE); d->sbdma_dscrcnt = - PKSEG1(s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT)); + s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT); d->sbdma_curdscr = - PKSEG1(s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR)); + s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR); /* * Allocate memory for the ring @@ -673,23 +737,41 @@ static void sbdma_initctx(sbmacdma_t *d, d->sbdma_maxdescr = maxdescr; d->sbdma_dscrtable = (sbdmadscr_t *) - KMALLOC(d->sbdma_maxdescr*sizeof(sbdmadscr_t)); + kmalloc(d->sbdma_maxdescr*sizeof(sbdmadscr_t), GFP_KERNEL); memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t)); d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; - d->sbdma_dscrtable_phys = KVTOPHYS(d->sbdma_dscrtable); + d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable); /* * And context table */ d->sbdma_ctxtable = (struct sk_buff **) - KMALLOC(d->sbdma_maxdescr*sizeof(struct sk_buff *)); + kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL); memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *)); +#ifdef CONFIG_SBMAC_COALESCE + /* + * Setup Rx/Tx DMA coalescing defaults + */ + + if ( int_pktcnt ) { + d->sbdma_int_pktcnt = int_pktcnt; + } else { + d->sbdma_int_pktcnt = 1; + } + + if ( int_timeout ) { + d->sbdma_int_timeout = int_timeout; + } else { + d->sbdma_int_timeout = 0; + } +#endif + } /********************************************************************** @@ -699,33 +781,75 @@ static void sbdma_initctx(sbmacdma_t *d, * * Input parameters: * d - DMA channel to init (context must be previously init'd + * rxtx - DMA_RX or DMA_TX depending on what type of channel * * Return value: * nothing ********************************************************************* */ -static void sbdma_channel_start(sbmacdma_t *d) +static void sbdma_channel_start(sbmacdma_t *d, int rxtx ) { /* * Turn on the DMA channel */ +#ifdef CONFIG_SBMAC_COALESCE + SBMAC_WRITECSR(d->sbdma_config1, + V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) | + 0); + SBMAC_WRITECSR(d->sbdma_config0, + M_DMA_EOP_INT_EN | + V_DMA_RINGSZ(d->sbdma_maxdescr) | + V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) | + 0); +#else SBMAC_WRITECSR(d->sbdma_config1,0); - - SBMAC_WRITECSR(d->sbdma_dscrbase,d->sbdma_dscrtable_phys); - SBMAC_WRITECSR(d->sbdma_config0, V_DMA_RINGSZ(d->sbdma_maxdescr) | 0); - +#endif + + SBMAC_WRITECSR(d->sbdma_dscrbase,d->sbdma_dscrtable_phys); + /* * Initialize ring pointers */ - + d->sbdma_addptr = d->sbdma_dscrtable; d->sbdma_remptr = d->sbdma_dscrtable; } +/********************************************************************** + * SBDMA_CHANNEL_STOP(d) + * + * Initialize the hardware registers for a DMA channel. + * + * Input parameters: + * d - DMA channel to init (context must be previously init'd + * + * Return value: + * nothing + ********************************************************************* */ + +static void sbdma_channel_stop(sbmacdma_t *d) +{ + /* + * Turn off the DMA channel + */ + + SBMAC_WRITECSR(d->sbdma_config1,0); + + SBMAC_WRITECSR(d->sbdma_dscrbase,0); + + SBMAC_WRITECSR(d->sbdma_config0,0); + + /* + * Zero ring pointers + */ + + d->sbdma_addptr = 0; + d->sbdma_remptr = 0; +} static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset) { @@ -777,7 +901,7 @@ static int sbdma_add_rcvbuffer(sbmacdma_ if (nextdsc == d->sbdma_remptr) { return -ENOSPC; } - + /* * Allocate a sk_buff if we don't already have one. * If we do have an sk_buff, reset it so that it's empty. @@ -788,25 +912,25 @@ static int sbdma_add_rcvbuffer(sbmacdma_ * * 1. the data does not start in the middle of a cache line. * 2. The data does not end in the middle of a cache line - * 3. The buffer can be aligned such that the IP addresses are + * 3. The buffer can be aligned such that the IP addresses are * naturally aligned. * - * Remember, the SB1250's MAC writes whole cache lines at a time, + * Remember, the SOCs MAC writes whole cache lines at a time, * without reading the old contents first. So, if the sk_buff's - * data portion starts in the middle of a cache line, the SB1250 + * data portion starts in the middle of a cache line, the SOC * DMA will trash the beginning (and ending) portions. */ if (sb == NULL) { - sb_new = dev_alloc_skb(ENET_PACKET_SIZE + CACHELINESIZE*2 + ETHER_ALIGN); + sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN); if (sb_new == NULL) { printk(KERN_INFO "%s: sk_buff allocation failed\n", d->sbdma_eth->sbm_dev->name); return -ENOBUFS; } - - sbdma_align_skb(sb_new,CACHELINESIZE,ETHER_ALIGN); - + + sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN); + /* mark skbuff owned by our device */ sb_new->dev = d->sbdma_eth->sbm_dev; } @@ -814,7 +938,7 @@ static int sbdma_add_rcvbuffer(sbmacdma_ sb_new = sb; /* * nothing special to reinit buffer, it's already aligned - * and sb->tail already points to a good place. + * and sb->data already points to a good place. */ } @@ -822,10 +946,19 @@ static int sbdma_add_rcvbuffer(sbmacdma_ * fill in the descriptor */ - dsc->dscr_a = KVTOPHYS(sb_new->tail) | +#ifdef CONFIG_SBMAC_COALESCE + /* + * Do not interrupt per DMA transfer. + */ + dsc->dscr_a = virt_to_phys(sb_new->tail) | + V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | + 0; +#else + dsc->dscr_a = virt_to_phys(sb_new->tail) | V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | M_DMA_DSCRA_INTERRUPT; - +#endif + /* receiving: no options */ dsc->dscr_b = 0; @@ -904,12 +1037,14 @@ static int sbdma_add_txbuffer(sbmacdma_t * while doing the calculation. */ - phys = KVTOPHYS(sb->data); - ncb = NUMCACHEBLKS(length+(phys & (CACHELINESIZE-1))); - + phys = virt_to_phys(sb->data); + ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1))); + dsc->dscr_a = phys | V_DMA_DSCRA_A_SIZE(ncb) | +#ifndef CONFIG_SBMAC_COALESCE M_DMA_DSCRA_INTERRUPT | +#endif M_DMA_ETHTX_SOP; /* transmitting: set outbound options and length */ @@ -986,7 +1121,8 @@ static void sbdma_fillring(sbmacdma_t *d int idx; for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) { - if (sbdma_add_rcvbuffer(d,NULL) != 0) break; + if (sbdma_add_rcvbuffer(d,NULL) != 0) + break; } } @@ -1037,7 +1173,8 @@ static void sbdma_rx_process(struct sbma * the hardware is working on right now. */ - if (curidx == hwidx) break; + if (curidx == hwidx) + break; /* * Otherwise, get the packet's sk_buff ptr back @@ -1058,35 +1195,51 @@ static void sbdma_rx_process(struct sbma if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) { /* - * Set length into the packet - */ - skb_put(sb,len); - - /* * Add a new buffer to replace the old one. If we fail * to allocate a buffer, we're going to drop this * packet and put it right back on the receive ring. */ if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) { - sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */ - } - else { - /* - * Buffer has been replaced on the receive ring. - * Pass the buffer to the kernel - */ - sc->sbm_stats.rx_bytes += len; - sc->sbm_stats.rx_packets++; - sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev); - netif_rx(sb); - } - } - else { + sc->sbm_stats.rx_dropped++; + sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */ + } else { + /* + * Set length into the packet + */ + skb_put(sb,len); + + /* + * Buffer has been replaced on the + * receive ring. Pass the buffer to + * the kernel */ + sc->sbm_stats.rx_bytes += len; + sc->sbm_stats.rx_packets++; + sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev); + if (sc->rx_hw_checksum == ENABLE) { + /* if the ip checksum is good + indicate in skb. else set + CHECKSUM_NONE as device + failed to checksum the + packet */ + + if (((dsc->dscr_b) |M_DMA_ETHRX_BADTCPCS) || + ((dsc->dscr_a)| M_DMA_ETHRX_BADIP4CS)) { + sb->ip_summed = CHECKSUM_NONE; + } else { + printk(KERN_DEBUG "hw checksum fail .\n"); + sb->ip_summed = CHECKSUM_UNNECESSARY; + } + } /* rx_hw_checksum */ + + netif_rx(sb); + } + } else { /* * Packet was mangled somehow. Just drop it and * put it back on the receive ring. */ + sc->sbm_stats.rx_errors++; sbdma_add_rcvbuffer(d,sb); } @@ -1143,21 +1296,27 @@ static void sbdma_tx_process(struct sbma curidx = d->sbdma_remptr - d->sbdma_dscrtable; { - /* XXX This is gross, ugly, and only here because justin hacked it - in to fix a problem without really understanding it. - - It seems that, for whatever reason, this routine is invoked immediately upon the enabling of interrupts. - So then the Read below returns zero, making hwidx a negative number, and anti-hilarity - ensues. - - I'm guessing there's a proper fix involving clearing out interrupt state from old packets - before enabling interrupts, but I'm not sure. - - Anyways, this hack seems to work, and is Good Enough for 11 PM. :) - - -Justin - */ - + /* XXX This is gross, ugly, and only here + * because justin hacked it in to fix a + * problem without really understanding it. + * + * It seems that, for whatever reason, this + * routine is invoked immediately upon the + * enabling of interrupts. So then the Read + * below returns zero, making hwidx a negative + * number, and anti-hilarity ensues. + * + * I'm guessing there's a proper fix involving + * clearing out interrupt state from old + * packets before enabling interrupts, but I'm + * not sure. + * + * Anyways, this hack seems to work, and is + * Good Enough for 11 PM. :) + * + * -Justin + */ + uint64_t tmp = SBMAC_READCSR(d->sbdma_curdscr); if (!tmp) { break; @@ -1171,7 +1330,8 @@ static void sbdma_tx_process(struct sbma * the hardware is working on right now. */ - if (curidx == hwidx) break; + if (curidx == hwidx) + break; /* * Otherwise, get the packet's sk_buff ptr back @@ -1238,14 +1398,14 @@ static int sbmac_initctx(struct sbmac_so * figure out the addresses of some ports */ - s->sbm_macenable = PKSEG1(s->sbm_base + R_MAC_ENABLE); - s->sbm_maccfg = PKSEG1(s->sbm_base + R_MAC_CFG); - s->sbm_fifocfg = PKSEG1(s->sbm_base + R_MAC_THRSH_CFG); - s->sbm_framecfg = PKSEG1(s->sbm_base + R_MAC_FRAMECFG); - s->sbm_rxfilter = PKSEG1(s->sbm_base + R_MAC_ADFILTER_CFG); - s->sbm_isr = PKSEG1(s->sbm_base + R_MAC_STATUS); - s->sbm_imr = PKSEG1(s->sbm_base + R_MAC_INT_MASK); - s->sbm_mdio = PKSEG1(s->sbm_base + R_MAC_MDIO); + s->sbm_macenable = s->sbm_base + R_MAC_ENABLE; + s->sbm_maccfg = s->sbm_base + R_MAC_CFG; + s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG; + s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG; + s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG; + s->sbm_isr = s->sbm_base + R_MAC_STATUS; + s->sbm_imr = s->sbm_base + R_MAC_INT_MASK; + s->sbm_mdio = s->sbm_base + R_MAC_MDIO; s->sbm_phys[0] = 1; s->sbm_phys[1] = 0; @@ -1284,12 +1444,12 @@ static int sbmac_initctx(struct sbmac_so static void sbdma_uninitctx(struct sbmacdma_s *d) { if (d->sbdma_dscrtable) { - KFREE(d->sbdma_dscrtable); + kfree(d->sbdma_dscrtable); d->sbdma_dscrtable = NULL; } if (d->sbdma_ctxtable) { - KFREE(d->sbdma_ctxtable); + kfree(d->sbdma_ctxtable); d->sbdma_ctxtable = NULL; } } @@ -1319,13 +1479,14 @@ static void sbmac_channel_start(struct s uint64_t reg; sbmac_port_t port; uint64_t cfg,fifo,framecfg; - int idx; + int idx, th_value; /* * Don't do this if running */ - if (s->sbm_state == sbmac_state_on) return; + if (s->sbm_state == sbmac_state_on) + return; /* * Bring the controller out of reset, but leave it off. @@ -1351,26 +1512,36 @@ static void sbmac_channel_start(struct s M_MAC_SS_EN | 0; + /* + * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars + * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above + * Use a larger RD_THRSH for gigabit + */ + if (periph_rev >= 2) + th_value = 64; + else + th_value = 28; + fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ - V_MAC_TX_RD_THRSH(4) | + ((s->sbm_speed == sbmac_speed_1000) + ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) | V_MAC_TX_RL_THRSH(4) | V_MAC_RX_PL_THRSH(4) | V_MAC_RX_RD_THRSH(4) | /* Must be '4' */ V_MAC_RX_PL_THRSH(4) | V_MAC_RX_RL_THRSH(8) | 0; - + framecfg = V_MAC_MIN_FRAMESZ_DEFAULT | V_MAC_MAX_FRAMESZ_DEFAULT | V_MAC_BACKOFF_SEL(1); - - + /* * Clear out the hash address map */ - port = PKSEG1(s->sbm_base + R_MAC_HASH_BASE); - for (idx = 0; idx < MAC_HASH_COUNT; idx++) { + port = s->sbm_base + R_MAC_HASH_BASE; + for (idx = 0; idx < MAC_HASH_COUNT; idx++) { SBMAC_WRITECSR(port,0); port += sizeof(uint64_t); } @@ -1379,7 +1550,7 @@ static void sbmac_channel_start(struct s * Clear out the exact-match table */ - port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE); + port = s->sbm_base + R_MAC_ADDR_BASE; for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { SBMAC_WRITECSR(port,0); port += sizeof(uint64_t); @@ -1389,14 +1560,14 @@ static void sbmac_channel_start(struct s * Clear out the DMA Channel mapping table registers */ - port = PKSEG1(s->sbm_base + R_MAC_CHUP0_BASE); + port = s->sbm_base + R_MAC_CHUP0_BASE; for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { SBMAC_WRITECSR(port,0); port += sizeof(uint64_t); } - port = PKSEG1(s->sbm_base + R_MAC_CHLO0_BASE); + port = s->sbm_base + R_MAC_CHLO0_BASE; for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { SBMAC_WRITECSR(port,0); port += sizeof(uint64_t); @@ -1409,13 +1580,13 @@ static void sbmac_channel_start(struct s reg = sbmac_addr2reg(s->sbm_hwaddr); - port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE); + port = s->sbm_base + R_MAC_ADDR_BASE; SBMAC_WRITECSR(port,reg); - port = PKSEG1(s->sbm_base + R_MAC_ETHERNET_ADDR); + port = s->sbm_base + R_MAC_ETHERNET_ADDR; #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS /* - * Pass1 SB1250s do not receive packets addressed to the + * Pass1 SOCs do not receive packets addressed to the * destination address in the R_MAC_ETHERNET_ADDR register. * Set the value to zero. */ @@ -1439,8 +1610,8 @@ static void sbmac_channel_start(struct s * Initialize DMA channels (rings should be ok now) */ - sbdma_channel_start(&(s->sbm_rxdma)); - sbdma_channel_start(&(s->sbm_txdma)); + sbdma_channel_start(&(s->sbm_rxdma), DMA_RX); + sbdma_channel_start(&(s->sbm_txdma), DMA_TX); /* * Configure the speed, duplex, and flow control @@ -1467,12 +1638,22 @@ static void sbmac_channel_start(struct s + +#ifdef CONFIG_SBMAC_COALESCE + /* + * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0 + */ + SBMAC_WRITECSR(s->sbm_imr, + ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | + ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0)); +#else /* * Accept any kind of interrupt on TX and RX DMA channel 0 */ SBMAC_WRITECSR(s->sbm_imr, (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)); +#endif /* * Enable receiving unicasts and broadcasts @@ -1517,11 +1698,10 @@ static void sbmac_channel_start(struct s static void sbmac_channel_stop(struct sbmac_softc *s) { - uint64_t ctl; - /* don't do this if already stopped */ - if (s->sbm_state == sbmac_state_off) return; + if (s->sbm_state == sbmac_state_off) + return; /* don't accept any packets, disable all interrupts */ @@ -1534,14 +1714,18 @@ static void sbmac_channel_stop(struct sb /* turn off receiver and transmitter */ - ctl = SBMAC_READCSR(s->sbm_macenable); - ctl &= ~(M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0); - SBMAC_WRITECSR(s->sbm_macenable,ctl); + SBMAC_WRITECSR(s->sbm_macenable,0); /* We're stopped now. */ s->sbm_state = sbmac_state_off; + /* + * Stop DMA channels (rings should be ok now) + */ + + sbdma_channel_stop(&(s->sbm_rxdma)); + sbdma_channel_stop(&(s->sbm_txdma)); /* Empty the receive and transmit rings */ @@ -1610,7 +1794,8 @@ static void sbmac_promiscuous_mode(struc { uint64_t reg; - if (sc->sbm_state != sbmac_state_on) return; + if (sc->sbm_state != sbmac_state_on) + return; if (onoff) { reg = SBMAC_READCSR(sc->sbm_rxfilter); @@ -1624,31 +1809,36 @@ static void sbmac_promiscuous_mode(struc } } - - -#if 0 /********************************************************************** - * SBMAC_INIT_AND_START(sc) + * SBMAC_SETIPHDR_OFFSET(sc,onoff) * - * Stop the channel and restart it. This is generally used - * when we have to do something to the channel that requires - * a swift kick. + * Set the iphdr offset as 15 assuming ethernet encapsulation * * Input parameters: * sc - softc + * + * Return value: + * nothing ********************************************************************* */ -static void sbmac_init_and_start(struct sbmac_softc *sc) +static void sbmac_set_iphdr_offset(struct sbmac_softc *sc) { - unsigned long flags; - - spin_lock_irqsave(&(sc->sbm_lock),flags); + uint64_t reg; - sbmac_set_channel_state(sc,sbmac_state_on); + /* Hard code the off set to 15 for now */ + reg = SBMAC_READCSR(sc->sbm_rxfilter); + reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15); + SBMAC_WRITECSR(sc->sbm_rxfilter,reg); - spin_unlock_irqrestore(&(sc->sbm_lock),flags); + /* read system identification to determine revision */ + if (periph_rev >= 2) { + printk(KERN_INFO "%s: enabling TCP rcv checksum\n", + sc->sbm_dev->name); + sc->rx_hw_checksum = ENABLE; + } else { + sc->rx_hw_checksum = DISABLE; + } } -#endif /********************************************************************** @@ -1712,7 +1902,8 @@ static int sbmac_set_speed(struct sbmac_ s->sbm_speed = speed; - if (s->sbm_state == sbmac_state_on) return 0; /* save for next restart */ + if (s->sbm_state == sbmac_state_on) + return 0; /* save for next restart */ /* * Read current register values @@ -1772,7 +1963,6 @@ static int sbmac_set_speed(struct sbmac_ SBMAC_WRITECSR(s->sbm_maccfg,cfg); return 1; - } /********************************************************************** @@ -1802,7 +1992,8 @@ static int sbmac_set_duplex(struct sbmac s->sbm_duplex = duplex; s->sbm_fc = fc; - if (s->sbm_state == sbmac_state_on) return 0; /* save for next restart */ + if (s->sbm_state == sbmac_state_on) + return 0; /* save for next restart */ /* * Read current register values @@ -1886,7 +2077,7 @@ static int sbmac_set_duplex(struct sbmac * Return value: * nothing ********************************************************************* */ -static void sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs) +static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs) { struct net_device *dev = (struct net_device *) dev_instance; struct sbmac_softc *sc = (struct sbmac_softc *) (dev->priv); @@ -1896,14 +2087,17 @@ static void sbmac_intr(int irq,void *dev for (;;) { /* - * Read the ISR (this clears the bits in the real register) + * Read the ISR (this clears the bits in the real + * register, except for counter addr) */ - isr = SBMAC_READCSR(sc->sbm_isr); + isr = SBMAC_READCSR(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR; if (isr == 0) break; + handled = 1; + /* * Transmits on channel 0 */ @@ -1915,6 +2109,23 @@ static void sbmac_intr(int irq,void *dev /* * Receives on channel 0 */ + + /* + * It's important to test all the bits (or at least the + * EOP_SEEN bit) when deciding to do the RX process + * particularly when coalescing, to make sure we + * take care of the following: + * + * If you have some packets waiting (have been received + * but no interrupt) and get a TX interrupt before + * the RX timer or counter expires, reading the ISR + * above will clear the timer and counter, and you + * won't get another interrupt until a packet shows + * up to start the timer again. Testing + * EOP_SEEN here takes care of this case. + * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0) + */ + if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) { sbdma_rx_process(sc,&(sc->sbm_rxdma)); @@ -1952,6 +2163,9 @@ static int sbmac_start_tx(struct sk_buff if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) { /* XXX save skb that we could not send */ netif_stop_queue(dev); + spin_unlock_irq(&sc->sbm_lock); + + return 1; } dev->trans_start = jiffies; @@ -1990,12 +2204,12 @@ static void sbmac_setmulti(struct sbmac_ */ for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { - port = PKSEG1(sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t))); + port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t)); SBMAC_WRITECSR(port,0); } for (idx = 0; idx < MAC_HASH_COUNT; idx++) { - port = PKSEG1(sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t))); + port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t)); SBMAC_WRITECSR(port,0); } @@ -2032,8 +2246,7 @@ static void sbmac_setmulti(struct sbmac_ mclist = dev->mc_list; while (mclist && (idx < MAC_ADDR_COUNT)) { reg = sbmac_addr2reg(mclist->dmi_addr); - port = PKSEG1(sc->sbm_base + - R_MAC_ADDR_BASE+(idx*sizeof(uint64_t))); + port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t)); SBMAC_WRITECSR(port,reg); idx++; mclist = mclist->next; @@ -2070,10 +2283,14 @@ static int sbmac_parse_xdigit(char str) { int digit; - if ((str >= '0') && (str <= '9')) digit = str - '0'; - else if ((str >= 'a') && (str <= 'f')) digit = str - 'a' + 10; - else if ((str >= 'A') && (str <= 'F')) digit = str - 'A' + 10; - else return -1; + if ((str >= '0') && (str <= '9')) + digit = str - '0'; + else if ((str >= 'a') && (str <= 'f')) + digit = str - 'a' + 10; + else if ((str >= 'A') && (str <= 'F')) + digit = str - 'A' + 10; + else + return -1; return digit; } @@ -2092,16 +2309,18 @@ static int sbmac_parse_xdigit(char str) * 0 if ok, else -1 ********************************************************************* */ -static int sbmac_parse_hwaddr(char *str,u_char *hwaddr) +static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr) { int digit1,digit2; int idx = 6; while (*str && (idx > 0)) { digit1 = sbmac_parse_xdigit(*str); - if (digit1 < 0) return -1; + if (digit1 < 0) + return -1; str++; - if (!*str) return -1; + if (!*str) + return -1; if ((*str == ':') || (*str == '-')) { digit2 = digit1; @@ -2109,20 +2328,32 @@ static int sbmac_parse_hwaddr(char *str, } else { digit2 = sbmac_parse_xdigit(*str); - if (digit2 < 0) return -1; + if (digit2 < 0) + return -1; str++; } *hwaddr++ = (digit1 << 4) | digit2; idx--; - if (*str == '-') str++; - if (*str == ':') str++; + if (*str == '-') + str++; + if (*str == ':') + str++; } return 0; } #endif +static int sb1250_change_mtu(struct net_device *_dev, int new_mtu) +{ + if (new_mtu > ENET_PACKET_SIZE) + return -EINVAL; + _dev->mtu = new_mtu; + printk(KERN_INFO "changing the mtu to %d\n", new_mtu); + return 0; +} + /********************************************************************** * SBMAC_INIT(dev) * @@ -2135,19 +2366,20 @@ static int sbmac_parse_hwaddr(char *str, * status ********************************************************************* */ -static int sbmac_init(struct net_device *dev) +static int sbmac_init(struct net_device *dev, int idx) { struct sbmac_softc *sc; - u_char *eaddr; + unsigned char *eaddr; uint64_t ea_reg; - int idx; + int i; sc = (struct sbmac_softc *)dev->priv; /* Determine controller base address */ - sc->sbm_base = (sbmac_port_t) dev->base_addr; + sc->sbm_base = KSEG1ADDR(dev->base_addr); sc->sbm_dev = dev; + sc->sbe_idx = idx; eaddr = sc->sbm_hwaddr; @@ -2156,16 +2388,15 @@ static int sbmac_init(struct net_device * for us in the ethernet address register for each mac. */ - ea_reg = SBMAC_READCSR(PKSEG1(sc->sbm_base + R_MAC_ETHERNET_ADDR)); - SBMAC_WRITECSR(PKSEG1(sc->sbm_base + R_MAC_ETHERNET_ADDR), 0); - for (idx = 0; idx < 6; idx++) { - eaddr[idx] = (uint8_t) (ea_reg & 0xFF); + ea_reg = SBMAC_READCSR(sc->sbm_base + R_MAC_ETHERNET_ADDR); + SBMAC_WRITECSR(sc->sbm_base + R_MAC_ETHERNET_ADDR, 0); + for (i = 0; i < 6; i++) { + eaddr[i] = (uint8_t) (ea_reg & 0xFF); ea_reg >>= 8; } - - for (idx = 0; idx < 6; idx++) { - dev->dev_addr[idx] = eaddr[idx]; + for (i = 0; i < 6; i++) { + dev->dev_addr[i] = eaddr[i]; } @@ -2173,8 +2404,8 @@ static int sbmac_init(struct net_device * Init packet size */ - sc->sbm_buffersize = ENET_PACKET_SIZE + CACHELINESIZE*2 + ETHER_ALIGN; - + sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN; + /* * Initialize context (get pointers to registers and stuff), then * allocate the memory for the descriptor tables. @@ -2184,13 +2415,13 @@ static int sbmac_init(struct net_device /* - * Display Ethernet address (this is called during the config process - * so we need to finish off the config message that was being displayed) + * Display Ethernet address (this is called during the config + * process so we need to finish off the config message that + * was being displayed) */ printk(KERN_INFO - "%s: SB1250 Ethernet at 0x%08lX, address: %02X-%02X-%02X-%02X-%02X-%02X\n", - dev->name, - (unsigned long) sc->sbm_base, + "%s: SiByte Ethernet at 0x%08lX, address: %02X-%02X-%02X-%02X-%02X-%02X\n", + dev->name, dev->base_addr, eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]); /* @@ -2208,9 +2439,13 @@ static int sbmac_init(struct net_device dev->do_ioctl = sbmac_mii_ioctl; dev->tx_timeout = sbmac_tx_timeout; dev->watchdog_timeo = TX_TIMEOUT; + + dev->change_mtu = sb1250_change_mtu; + + /* This is needed for PASS2 for Rx H/W checksum feature */ + sbmac_set_iphdr_offset(sc); return 0; - } @@ -2237,7 +2472,7 @@ static int sbmac_open(struct net_device * Configure default speed */ - sbmac_mii_poll(sc,1); + sbmac_mii_poll(sc,noisy_mii); /* * Turn on the channel @@ -2319,7 +2554,8 @@ static int sbmac_mii_poll(struct sbmac_s chg = 1; } - if (chg == 0) return 0; + if (chg == 0) + return 0; p += sprintf(p,"Link speed: "); @@ -2371,8 +2607,6 @@ static int sbmac_mii_poll(struct sbmac_s } - - static void sbmac_timer(unsigned long data) { struct net_device *dev = (struct net_device *)data; @@ -2399,19 +2633,19 @@ static void sbmac_timer(unsigned long da * Poll the PHY to see what speed we should be running at */ - if (sbmac_mii_poll(sc,1)) { - if (sc->sbm_state != sbmac_state_off) { - /* - * something changed, restart the channel - */ - if (debug > 1) { - printk("%s: restarting channel because speed changed\n", - sc->sbm_dev->name); - } - sbmac_channel_stop(sc); - sbmac_channel_start(sc); + if (sbmac_mii_poll(sc,noisy_mii)) { + if (sc->sbm_state != sbmac_state_off) { + /* + * something changed, restart the channel + */ + if (debug > 1) { + printk("%s: restarting channel because speed changed\n", + sc->sbm_dev->name); + } + sbmac_channel_stop(sc); + sbmac_channel_start(sc); } - } + } spin_unlock_irq (&sc->sbm_lock); @@ -2479,7 +2713,8 @@ static void sbmac_set_rx_mode(struct net spin_unlock_irqrestore(&sc->sbm_lock, flags); if (msg_flag) { - printk(KERN_NOTICE "%s: Promiscuous mode %sabled.\n", dev->name,(msg_flag==1)?"en":"dis"); + printk(KERN_NOTICE "%s: Promiscuous mode %sabled.\n", + dev->name,(msg_flag==1)?"en":"dis"); } /* @@ -2530,31 +2765,31 @@ static int sbmac_close(struct net_device { struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv; unsigned long flags; - + int irq; + sbmac_set_channel_state(sc,sbmac_state_off); - + del_timer_sync(&sc->sbm_timer); - + spin_lock_irqsave(&sc->sbm_lock, flags); - + netif_stop_queue(dev); - + if (debug > 1) { printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name); } - + spin_unlock_irqrestore(&sc->sbm_lock, flags); - - /* Make sure there is no irq-handler running on a different CPU. */ - synchronize_irq(dev->irq); - - free_irq(dev->irq, dev); - + + irq = dev->irq; + synchronize_irq(irq); + free_irq(irq, dev); + sbdma_emptyring(&(sc->sbm_txdma)); sbdma_emptyring(&(sc->sbm_rxdma)); MOD_DEC_USE_COUNT; - + return 0; } @@ -2571,8 +2806,8 @@ sbmac_setup_hwaddr(int chan,char *addr) port = A_MAC_CHANNEL_BASE(chan); sbmac_parse_hwaddr(addr,eaddr); val = sbmac_addr2reg(eaddr); - SBMAC_WRITECSR(PKSEG1(port+R_MAC_ETHERNET_ADDR),val); - val = SBMAC_READCSR(PKSEG1(port+R_MAC_ETHERNET_ADDR)); + SBMAC_WRITECSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR),val); + val = SBMAC_READCSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR)); } #endif @@ -2585,6 +2820,7 @@ sbmac_init_module(void) int macidx = 0; struct net_device *dev; sbmac_port_t port; + int chip_max_units; /* * For bringup when not using the firmware, we can pre-fill @@ -2605,8 +2841,25 @@ sbmac_init_module(void) * Walk through the Ethernet controllers and find * those who have their MAC addresses set. */ - - for (idx = 0; idx < MAX_UNITS; idx++) { + switch (soc_type) { + case K_SYS_SOC_TYPE_BCM1250: + case K_SYS_SOC_TYPE_BCM1250_ALT: + chip_max_units = 3; + break; + case K_SYS_SOC_TYPE_BCM1120: + case K_SYS_SOC_TYPE_BCM1125: + case K_SYS_SOC_TYPE_BCM1125H: + case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */ + chip_max_units = 2; + break; + default: + chip_max_units = 0; + break; + } + if (chip_max_units > MAX_UNITS) + chip_max_units = MAX_UNITS; + + for (idx = 0; idx < chip_max_units; idx++) { /* * This is the base address of the MAC. @@ -2620,25 +2873,31 @@ sbmac_init_module(void) * If we find a zero, skip this MAC. */ - if (SBMAC_READCSR(PKSEG1(port+R_MAC_ETHERNET_ADDR)) == 0) { + sbmac_orig_hwaddr[idx] = SBMAC_READCSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR)); + if (sbmac_orig_hwaddr[idx] == 0) { + printk(KERN_DEBUG "sbmac: not configuring MAC at " + "%lx\n", port); continue; - } + } /* * Okay, cool. Initialize this MAC. */ dev = init_etherdev(NULL,sizeof(struct sbmac_softc)); - if (!dev) break; /* problems, get out now. */ + if (!dev) + return -ENOMEM; /* return ENOMEM */ + + printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port); + dev->irq = K_INT_MAC_0 + idx; dev->base_addr = port; dev->mem_end = 0; /*dev->init = sbmac_init;*/ - sbmac_init(dev); + sbmac_init(dev, macidx); dev_sbmac[macidx] = dev; macidx++; - } /* @@ -2654,9 +2913,11 @@ sbmac_cleanup_module(void) { int idx; struct net_device *dev; + sbmac_port_t port; for (idx = 0; idx < MAX_UNITS; idx++) { dev = dev_sbmac[idx]; - if (dev == NULL) continue; + if (dev == NULL) + continue; if (dev->priv != NULL) { struct sbmac_softc *sc = (struct sbmac_softc *) dev->priv; @@ -2664,9 +2925,11 @@ sbmac_cleanup_module(void) sbmac_uninitctx(sc); - KFREE(sc); } - KFREE(dev); + + port = A_MAC_CHANNEL_BASE(idx); + SBMAC_WRITECSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR), sbmac_orig_hwaddr[idx] ); + kfree(dev); dev_sbmac[idx] = NULL; } } --- linux-2.5.73/drivers/net/sgiseeq.c 2003-06-14 12:18:33.000000000 -0700 +++ 25/drivers/net/sgiseeq.c 2003-06-27 15:56:24.000000000 -0700 @@ -5,6 +5,7 @@ */ #include #include +#include #include #include #include @@ -25,8 +26,8 @@ #include #include #include -#include -#include +#include +#include #include #include "sgiseeq.h" @@ -90,8 +91,8 @@ struct sgiseeq_init_block { /* Note the struct sgiseeq_private { volatile struct sgiseeq_init_block srings; char *name; - volatile struct hpc3_ethregs *hregs; - volatile struct sgiseeq_regs *sregs; + struct hpc3_ethregs *hregs; + struct sgiseeq_regs *sregs; /* Ring entry counters. */ unsigned int rx_new, tx_new; @@ -102,17 +103,22 @@ struct sgiseeq_private { unsigned char mode; struct net_device_stats stats; + + struct net_device *next_module; }; -static inline void hpc3_eth_reset(volatile struct hpc3_ethregs *hregs) +/* A list of all installed seeq devices, for removing the driver module. */ +static struct net_device *root_sgiseeq_dev; + +static inline void hpc3_eth_reset(struct hpc3_ethregs *hregs) { hregs->rx_reset = (HPC3_ERXRST_CRESET | HPC3_ERXRST_CLRIRQ); udelay(20); hregs->rx_reset = 0; } -static inline void reset_hpc3_and_seeq(volatile struct hpc3_ethregs *hregs, - volatile struct sgiseeq_regs *sregs) +static inline void reset_hpc3_and_seeq(struct hpc3_ethregs *hregs, + struct sgiseeq_regs *sregs) { hregs->rx_ctrl = hregs->tx_ctrl = 0; hpc3_eth_reset(hregs); @@ -122,15 +128,15 @@ static inline void reset_hpc3_and_seeq(v SEEQ_RCMD_IDRIB | SEEQ_RCMD_ICRC) static inline void seeq_go(struct sgiseeq_private *sp, - volatile struct hpc3_ethregs *hregs, - volatile struct sgiseeq_regs *sregs) + struct hpc3_ethregs *hregs, + struct sgiseeq_regs *sregs) { sregs->rstat = sp->mode | RSTAT_GO_BITS; hregs->rx_ctrl = HPC3_ERXCTRL_ACTIVE; } static inline void seeq_load_eaddr(struct net_device *dev, - volatile struct sgiseeq_regs *sregs) + struct sgiseeq_regs *sregs) { int i; @@ -171,7 +177,6 @@ static int seeq_init_ring(struct net_dev return -ENOMEM; ib->tx_desc[i].buf_vaddr = KSEG1ADDR(buffer); ib->tx_desc[i].tdma.pbuf = PHYSADDR(buffer); -// flush_cache_all(); } ib->tx_desc[i].tdma.cntinfo = (TCNTINFO_INIT); } @@ -186,7 +191,6 @@ static int seeq_init_ring(struct net_dev return -ENOMEM; ib->rx_desc[i].buf_vaddr = KSEG1ADDR(buffer); ib->rx_desc[i].rdma.pbuf = PHYSADDR(buffer); -// flush_cache_all(); } ib->rx_desc[i].rdma.cntinfo = (RCNTINFO_INIT); } @@ -203,7 +207,7 @@ void sgiseeq_dump_rings(void) static int once; struct sgiseeq_rx_desc *r = gpriv->srings.rx_desc; struct sgiseeq_tx_desc *t = gpriv->srings.tx_desc; - volatile struct hpc3_ethregs *hregs = gpriv->hregs; + struct hpc3_ethregs *hregs = gpriv->hregs; int i; if(once) @@ -242,9 +246,9 @@ void sgiseeq_dump_rings(void) #define RDMACFG_INIT (HPC3_ERXDCFG_FRXDC | HPC3_ERXDCFG_FEOP | HPC3_ERXDCFG_FIRQ) static int init_seeq(struct net_device *dev, struct sgiseeq_private *sp, - volatile struct sgiseeq_regs *sregs) + struct sgiseeq_regs *sregs) { - volatile struct hpc3_ethregs *hregs = sp->hregs; + struct hpc3_ethregs *hregs = sp->hregs; int err; reset_hpc3_and_seeq(hregs, sregs); @@ -285,8 +289,8 @@ static inline void record_rx_errors(stru } static inline void rx_maybe_restart(struct sgiseeq_private *sp, - volatile struct hpc3_ethregs *hregs, - volatile struct sgiseeq_regs *sregs) + struct hpc3_ethregs *hregs, + struct sgiseeq_regs *sregs) { if (!(hregs->rx_ctrl & HPC3_ERXCTRL_ACTIVE)) { hregs->rx_ndptr = PHYSADDR(&sp->srings.rx_desc[sp->rx_new]); @@ -299,8 +303,8 @@ static inline void rx_maybe_restart(stru (rd) = &(sp)->srings.rx_desc[(sp)->rx_new]) static inline void sgiseeq_rx(struct net_device *dev, struct sgiseeq_private *sp, - volatile struct hpc3_ethregs *hregs, - volatile struct sgiseeq_regs *sregs) + struct hpc3_ethregs *hregs, + struct sgiseeq_regs *sregs) { struct sgiseeq_rx_desc *rd; struct sk_buff *skb = 0; @@ -332,7 +336,7 @@ static inline void sgiseeq_rx(struct net sp->stats.rx_packets++; sp->stats.rx_bytes += len; } else { - printk ("%s: Memory squeeze, deferring packet.\n", + printk (KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", dev->name); sp->stats.rx_dropped++; } @@ -350,7 +354,7 @@ static inline void sgiseeq_rx(struct net } static inline void tx_maybe_reset_collisions(struct sgiseeq_private *sp, - volatile struct sgiseeq_regs *sregs) + struct sgiseeq_regs *sregs) { if (sp->is_edlc) { sregs->rw.wregs.control = sp->control & ~(SEEQ_CTRL_XCNT); @@ -359,7 +363,7 @@ static inline void tx_maybe_reset_collis } static inline void kick_tx(struct sgiseeq_tx_desc *td, - volatile struct hpc3_ethregs *hregs) + struct hpc3_ethregs *hregs) { /* If the HPC aint doin nothin, and there are more packets * with ETXD cleared and XIU set we must make very certain @@ -377,8 +381,8 @@ static inline void kick_tx(struct sgisee } static inline void sgiseeq_tx(struct net_device *dev, struct sgiseeq_private *sp, - volatile struct hpc3_ethregs *hregs, - volatile struct sgiseeq_regs *sregs) + struct hpc3_ethregs *hregs, + struct sgiseeq_regs *sregs) { struct sgiseeq_tx_desc *td; unsigned long status = hregs->tx_ctrl; @@ -420,8 +424,8 @@ static irqreturn_t sgiseeq_interrupt(int { struct net_device *dev = (struct net_device *) dev_id; struct sgiseeq_private *sp = (struct sgiseeq_private *) dev->priv; - volatile struct hpc3_ethregs *hregs = sp->hregs; - volatile struct sgiseeq_regs *sregs = sp->sregs; + struct hpc3_ethregs *hregs = sp->hregs; + struct sgiseeq_regs *sregs = sp->sregs; /* Ack the IRQ and set software state. */ hregs->rx_reset = HPC3_ERXRST_CLRIRQ; @@ -429,7 +433,7 @@ static irqreturn_t sgiseeq_interrupt(int /* Always check for received packets. */ sgiseeq_rx(dev, sp, hregs, sregs); - /* Only check for tx acks iff we have something queued. */ + /* Only check for tx acks if we have something queued. */ if (sp->tx_old != sp->tx_new) sgiseeq_tx(dev, sp, hregs, sregs); @@ -442,47 +446,34 @@ static irqreturn_t sgiseeq_interrupt(int static int sgiseeq_open(struct net_device *dev) { struct sgiseeq_private *sp = (struct sgiseeq_private *)dev->priv; - volatile struct sgiseeq_regs *sregs = sp->sregs; - unsigned long flags; - int err; - - local_irq_save(flags); + struct sgiseeq_regs *sregs = sp->sregs; - err = -EAGAIN; - if (request_irq(dev->irq, sgiseeq_interrupt, 0, sgiseeqstr, dev)) { - printk("Seeq8003: Can't get irq %d\n", dev->irq); - goto out; - } - err = init_seeq(dev, sp, sregs); + int err = init_seeq(dev, sp, sregs); if (err) - goto out; + return err; netif_start_queue(dev); -out: - local_irq_restore(flags); - return err; + return 0; } static int sgiseeq_close(struct net_device *dev) { struct sgiseeq_private *sp = (struct sgiseeq_private *) dev->priv; - volatile struct sgiseeq_regs *sregs = sp->sregs; + struct sgiseeq_regs *sregs = sp->sregs; netif_stop_queue(dev); /* Shutdown the Seeq. */ reset_hpc3_and_seeq(sp->hregs, sregs); - free_irq(dev->irq, dev); - return 0; } static inline int sgiseeq_reset(struct net_device *dev) { struct sgiseeq_private *sp = (struct sgiseeq_private *) dev->priv; - volatile struct sgiseeq_regs *sregs = sp->sregs; + struct sgiseeq_regs *sregs = sp->sregs; int err; err = init_seeq(dev, sp, sregs); @@ -504,12 +495,12 @@ void sgiseeq_my_reset(void) static int sgiseeq_start_xmit(struct sk_buff *skb, struct net_device *dev) { struct sgiseeq_private *sp = (struct sgiseeq_private *) dev->priv; - volatile struct hpc3_ethregs *hregs = sp->hregs; + struct hpc3_ethregs *hregs = sp->hregs; unsigned long flags; struct sgiseeq_tx_desc *td; int skblen, len, entry; - save_and_cli(flags); + local_irq_save(flags); /* Setup... */ skblen = skb->len; @@ -553,14 +544,14 @@ static int sgiseeq_start_xmit(struct sk_ if (!TX_BUFFS_AVAIL(sp)) netif_stop_queue(dev); - restore_flags(flags); + local_irq_restore(flags); return 0; } static void timeout(struct net_device *dev) { - printk("%s: transmit timed out, resetting\n", dev->name); + printk(KERN_NOTICE "%s: transmit timed out, resetting\n", dev->name); sgiseeq_reset(dev); dev->trans_start = jiffies; @@ -603,41 +594,56 @@ static inline void setup_rx_ring(struct buf[i].rdma.pnext = PHYSADDR(&buf[0]); } -static char onboard_eth_addr[6]; - #define ALIGNED(x) ((((unsigned long)(x)) + 0xf) & ~(0xf)) -int sgiseeq_init(struct net_device *dev, struct sgiseeq_regs *sregs, - struct hpc3_ethregs *hregs, int irq) +int sgiseeq_init(struct hpc3_regs* regs, int irq) { - static unsigned version_printed; - int i; + struct net_device *dev; struct sgiseeq_private *sp; - - dev->priv = (struct sgiseeq_private *) get_zeroed_page(GFP_KERNEL); - if (dev->priv == NULL) + int i; + + sp = (struct sgiseeq_private *) get_zeroed_page(GFP_KERNEL); + if (!sp) { + printk (KERN_ERR + "Seeq8003: Could not allocate private data.\n"); return -ENOMEM; + } - if (!version_printed++) - printk(version); - - printk("%s: SGI Seeq8003 ", dev->name); - - for (i = 0; i < 6; i++) - printk("%2.2x%c", - dev->dev_addr[i] = onboard_eth_addr[i], - i == 5 ? ' ': ':'); + dev = init_etherdev(NULL, 0); + if (!dev) { + printk (KERN_ERR + "Seeq8003: Could not allocate memory for device.\n"); + free_page((unsigned long) sp); + return -ENOMEM; + } + if (request_irq(irq, sgiseeq_interrupt, 0, sgiseeqstr, dev)) { + printk(KERN_ERR "Seeq8003: Can't get irq %d\n", dev->irq); + free_page((unsigned long) sp); + unregister_netdev(dev); + return -EAGAIN; + } + + printk(KERN_INFO "%s: SGI Seeq8003 ", dev->name); + +#define EADDR_NVOFS 250 + for (i = 0; i < 3; i++) { + unsigned short tmp = ip22_nvram_read(EADDR_NVOFS / 2 + i); + + printk("%2.2x:%2.2x%c", + dev->dev_addr[2 * i] = tmp >> 8, + dev->dev_addr[2 * i + 1] = tmp & 0xff, + i == 2 ? ' ' : ':'); + } printk("\n"); - sp = (struct sgiseeq_private *) dev->priv; + dev->priv = sp; #ifdef DEBUG gpriv = sp; gdev = dev; #endif - memset((char *)dev->priv, 0, sizeof(struct sgiseeq_private)); - sp->sregs = sregs; - sp->hregs = hregs; + sp->sregs = (struct sgiseeq_regs *) &hpc3c0->eth_ext[0]; + sp->hregs = &hpc3c0->ethregs; sp->name = sgiseeqstr; sp->srings.rx_desc = (struct sgiseeq_rx_desc *) @@ -654,14 +660,13 @@ int sgiseeq_init(struct net_device *dev, setup_tx_ring(sp->srings.tx_desc, SEEQ_TX_BUFFERS); /* Reset the chip. */ - hpc3_eth_reset((volatile struct hpc3_ethregs *) hregs); + hpc3_eth_reset(sp->hregs); - sp->is_edlc = !(sregs->rw.rregs.collision_tx[0] & 0xff); - if (sp->is_edlc) { + sp->is_edlc = !(sp->sregs->rw.rregs.collision_tx[0] & 0xff); + if (sp->is_edlc) sp->control = (SEEQ_CTRL_XCNT | SEEQ_CTRL_ACCNT | SEEQ_CTRL_SFLAG | SEEQ_CTRL_ESHORT | SEEQ_CTRL_ENCARR); - } dev->open = sgiseeq_open; dev->stop = sgiseeq_close; @@ -674,51 +679,37 @@ int sgiseeq_init(struct net_device *dev, dev->dma = 0; ether_setup(dev); + sp->next_module = root_sgiseeq_dev; + root_sgiseeq_dev = dev; + return 0; } -static inline unsigned char str2hexnum(unsigned char c) +static int __init sgiseeq_probe(void) { - if (c >= '0' && c <= '9') - return c - '0'; - if (c >= 'a' && c <= 'f') - return c - 'a' + 10; - return 0; /* foo */ + printk(version); + + /* On board adapter on 1st HPC is always present */ + return sgiseeq_init(hpc3c0, SGI_ENET_IRQ); } -static inline void str2eaddr(unsigned char *ea, unsigned char *str) +static void __exit sgiseeq_exit(void) { - int i; - - for (i = 0; i < 6; i++) { - unsigned char num; + struct sgiseeq_private *sp; + struct net_device *next, *dev = root_sgiseeq_dev; - if(*str == ':') - str++; - num = str2hexnum(*str++) << 4; - num |= (str2hexnum(*str++)); - ea[i] = num; + while (dev) { + sp = (struct sgiseeq_private *) dev->priv; + next = sp->next_module; + free_irq(dev->irq, dev); + free_page((unsigned long) sp); + unregister_netdev(dev); + kfree(dev); + dev = next; } } -int sgiseeq_probe(struct net_device *dev) -{ - static int initialized; - char *ep; - - if (initialized) /* Already initialized? */ - return 1; - initialized++; - - /* First get the ethernet address of the onboard interface from ARCS. - * This is fragile; PROM doesn't like running from cache. - * On MIPS64 it crashes for some other, yet unknown reason ... - */ - ep = ArcGetEnvironmentVariable("eaddr"); - str2eaddr(onboard_eth_addr, ep); - return sgiseeq_init(dev, - (struct sgiseeq_regs *) (KSEG1ADDR(0x1fbd4000)), - &hpc3c0->ethregs, SGI_ENET_IRQ); -} +module_init(sgiseeq_probe); +module_exit(sgiseeq_exit); MODULE_LICENSE("GPL"); --- linux-2.5.73/drivers/net/sgiseeq.h 2003-06-14 12:18:09.000000000 -0700 +++ 25/drivers/net/sgiseeq.h 2003-06-27 15:56:24.000000000 -0700 @@ -1,4 +1,4 @@ -/* $Id: sgiseeq.h,v 1.4 1999/10/09 00:01:24 ralf Exp $ +/* * sgiseeq.h: Defines for the Seeq8003 ethernet controller. * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) --- linux-2.5.73/drivers/net/sk98lin/skge.c 2003-06-14 12:17:58.000000000 -0700 +++ 25/drivers/net/sk98lin/skge.c 2003-06-27 15:56:24.000000000 -0700 @@ -48,6 +48,9 @@ * History: * * $Log: skge.c,v $ + * Revision x.xx.x.x 2003/06/07 02:31:17 romieu@fr.zoreil.com + * pci api style init. + * * Revision 1.29.2.6 2001/05/21 07:59:29 mlindner * fix: MTU init problems * @@ -275,6 +278,10 @@ #include "h/skdrv2nd.h" /* defines ******************************************************************/ + +#define DRV_MODULE_NAME "sk98lin" +#define PFX DRV_MODULE_NAME ": " + /* for debuging on x86 only */ /* #define BREAKPOINT() asm(" int $3"); */ @@ -361,9 +368,7 @@ static void DumpLong(char*, int); /* global variables *********************************************************/ -static const char *BootString = BOOT_STRING; -struct net_device *sk98lin_root_dev = NULL; -static int probed __initdata = 0; +static int boards_found; struct inode_operations SkInodeOps; //static struct file_operations SkFileOps; /* with open/relase */ @@ -371,236 +376,219 @@ struct inode_operations SkInodeOps; static uintptr_t TxQueueAddr[SK_MAX_MACS][2] = {{0x680, 0x600},{0x780, 0x700}}; static uintptr_t RxQueueAddr[SK_MAX_MACS] = {0x400, 0x480}; +spinlock_t sk_devs_lock = SPIN_LOCK_UNLOCKED; + +static int SkGeDevInit(struct net_device *dev) +{ + DEV_NET *pNet = dev->priv; + int ret = 0; + + dev->open = &SkGeOpen; + dev->stop = &SkGeClose; + dev->hard_start_xmit = &SkGeXmit; + dev->get_stats = &SkGeStats; + dev->set_multicast_list = &SkGeSetRxMode; + dev->set_mac_address = &SkGeSetMacAddr; + dev->do_ioctl = &SkGeIoctl; + dev->change_mtu = &SkGeChangeMtu; + + if (register_netdev(dev) != 0) { + printk(KERN_ERR "Unable to register etherdev\n"); + ret = -ENOMEM; + goto out; + } + pNet->proc = create_proc_entry(dev->name, S_IFREG | 0444, pSkRootDir); + if (pNet->proc) { + pNet->proc->data = dev; + pNet->proc->owner = THIS_MODULE; + pNet->proc->proc_fops = &sk_proc_fops; + } +out: + return ret; +} + +static void SkGeDevCleanUp(struct net_device *dev) +{ + DEV_NET *pNet = dev->priv; + + if (pNet->proc) { + spin_lock(&sk_devs_lock); + pNet->proc->data = NULL; + spin_unlock(&sk_devs_lock); + remove_proc_entry(dev->name, pSkRootDir); + } + unregister_netdev(dev); +} /***************************************************************************** * - * skge_probe - find all SK-98xx adapters + * skge_init_one - init a single instance of a SK-98xx adapter * * Description: - * This function scans the PCI bus for SK-98xx adapters. Resources for - * each adapter are allocated and the adapter is brought into Init 1 - * state. + * This function allocates resources for an SK-98xx adapter and brings + * it into Init 1 state. * * Returns: * 0, if everything is ok - * !=0, on error + * <0, on error */ -static int __init skge_probe (void) +static int __devinit skge_init_one(struct pci_dev *pdev, + const struct pci_device_id *ent) { - int proc_root_initialized = 0; - int boards_found = 0; - int version_disp = 0; SK_AC *pAC; - DEV_NET *pNet = NULL; - struct pci_dev *pdev = NULL; - unsigned long base_address; - struct net_device *dev = NULL; - - if (probed) - return -ENODEV; - probed++; - - /* display driver info */ - if (!version_disp) - { - /* set display flag to TRUE so that */ - /* we only display this string ONCE */ - version_disp = 1; - printk("%s\n", BootString); - } + DEV_NET *pNet; + unsigned long base_address; + struct net_device *dev; + int ret; - while((pdev = pci_find_device(PCI_VENDOR_ID_SYSKONNECT, - PCI_DEVICE_ID_SYSKONNECT_GE, pdev)) != NULL) { - - pNet = NULL; +#ifndef MODULE + static int version_disp = 0; - if (pci_enable_device(pdev)) - continue; +if (!version_disp++) + printk(KERN_INFO "%s\n", BOOT_STRING); +#endif + ret = pci_enable_device(pdev); + if (ret) + goto out; - /* Configure DMA attributes. */ - if (pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL) && - pci_set_dma_mask(pdev, (u64) 0xffffffff)) - continue; - - dev = alloc_etherdev(sizeof(DEV_NET)); - if (!dev) { - printk(KERN_ERR "Unable to allocate etherdev " - "structure!\n"); - break; + /* Configure DMA attributes. */ + if (pci_set_dma_mask(pdev, (u64) 0xffffffffffffffff)) { + ret = pci_set_dma_mask(pdev, (u64) 0xffffffff); + if (ret) { + printk(KERN_ERR PFX "No usable DMA configuration\n"); + goto out_disable; } + } - pNet = dev->priv; - pNet->pAC = kmalloc(sizeof(SK_AC), GFP_KERNEL); - if (pNet->pAC == NULL){ - kfree(dev); - printk(KERN_ERR "Unable to allocate adapter " - "structure!\n"); - break; - } + ret = -ENOMEM; - memset(pNet->pAC, 0, sizeof(SK_AC)); - pAC = pNet->pAC; - pAC->PciDev = *pdev; - pAC->PciDevId = pdev->device; - pAC->dev[0] = dev; - pAC->dev[1] = dev; - sprintf(pAC->Name, "SysKonnect SK-98xx"); - pAC->CheckQueue = SK_FALSE; + dev = alloc_etherdev(sizeof(DEV_NET)); + if (!dev) { + printk(KERN_ERR "Unable to allocate etherdev structure!\n"); + goto out_disable; + } + + pNet = dev->priv; + + pAC = kmalloc(sizeof(*pAC), GFP_KERNEL); + if (pAC == NULL){ + printk(KERN_ERR "Unable to allocate adapter structure!\n"); + goto out_free_dev; + } + + memset(pAC, 0, sizeof(SK_AC)); + pNet->pAC = pAC; + pAC->PciDev = *pdev; + pAC->PciDevId = pdev->device; + pAC->dev[0] = dev; + pAC->dev[1] = dev; + sprintf(pAC->Name, "SysKonnect SK-98xx"); + pAC->CheckQueue = SK_FALSE; - pNet->Mtu = 1500; - pNet->Up = 0; - dev->irq = pdev->irq; + pNet->Mtu = 1500; + pNet->Up = 0; + dev->irq = pdev->irq; - SET_MODULE_OWNER(dev); - SET_NETDEV_DEV(dev, &pdev->dev); - dev->open = &SkGeOpen; - dev->stop = &SkGeClose; - dev->hard_start_xmit = &SkGeXmit; - dev->get_stats = &SkGeStats; - dev->set_multicast_list = &SkGeSetRxMode; - dev->set_mac_address = &SkGeSetMacAddr; - dev->do_ioctl = &SkGeIoctl; - dev->change_mtu = &SkGeChangeMtu; - - if(!proc_root_initialized) { - pSkRootDir = create_proc_entry(SK_Root_Dir_entry, - S_IFDIR | S_IWUSR | S_IRUGO | S_IXUGO, proc_net); - pSkRootDir->owner = THIS_MODULE; - proc_root_initialized = 1; - } + SET_MODULE_OWNER(dev); + SET_NETDEV_DEV(dev, &pdev->dev); + ret = SkGeDevInit(dev); + if (ret < 0) + goto out_free_priv; - /* - * Dummy value. - */ - dev->base_addr = 42; - pci_set_master(pdev); - base_address = pci_resource_start (pdev, 0); + /* + * Dummy value. + */ + dev->base_addr = 42; + pci_set_master(pdev); + base_address = pci_resource_start(pdev, 0); #ifdef SK_BIG_ENDIAN - /* - * On big endian machines, we use the adapter's aibility of - * reading the descriptors as big endian. - */ - { + /* + * On big endian machines, we use the adapter's ability of + * reading the descriptors as big endian. + */ + { SK_U32 our2; - SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2); - our2 |= PCI_REV_DESC; - SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2); - } + SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2); + our2 |= PCI_REV_DESC; + SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2); + } #endif /* BIG ENDIAN */ - /* - * Remap the regs into kernel space. - */ + /* + * Remap the regs into kernel space. + */ - pAC->IoBase = (char*)ioremap(base_address, 0x4000); - if (!pAC->IoBase){ - printk(KERN_ERR "%s: Unable to map I/O register, " - "SK 98xx No. %i will be disabled.\n", - dev->name, boards_found); - kfree(dev); - break; - } - pAC->Index = boards_found; + pAC->IoBase = (char*)ioremap(base_address, 0x4000); + if (!pAC->IoBase) { + printk(KERN_ERR PFX "unable to map I/O register. " + "SK 98xx device disabled.\n"); + ret = -EIO; + goto out_dev_uninit; + } + pAC->Index = boards_found++; + + ret = SkGeBoardInit(dev, pAC); + if (ret < 0) + goto out_free_resources; + + memcpy((caddr_t) &dev->dev_addr, + (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6); + + pNet->PortNr = 0; + pNet->NetNr = 0; + + /* More then one port found */ + if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) { + struct net_device *sec_dev; + + sec_dev = alloc_etherdev(sizeof(DEV_NET)); + if (!sec_dev) { + printk(KERN_ERR PFX + "Unable to allocate etherdev structure!\n"); + ret = -ENOMEM; + goto out_free_resources; + } + + pAC->dev[1] = sec_dev; + pNet = sec_dev->priv; + pNet->PortNr = 1; + pNet->NetNr = 1; + pNet->pAC = pAC; + pNet->Mtu = 1500; + pNet->Up = 0; - if (SkGeBoardInit(dev, pAC)) { - FreeResources(dev); - kfree(dev); - continue; - } + ret = SkGeDevInit(sec_dev); + if (ret < 0) + goto out_free_secondary_dev; - memcpy((caddr_t) &dev->dev_addr, + memcpy((caddr_t) &sec_dev->dev_addr, (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6); - pNet->PortNr = 0; - pNet->NetNr = 0; - - if (register_netdev(dev) != 0) { - printk(KERN_ERR "Unable to register etherdev\n"); - sk98lin_root_dev = pAC->Next; - remove_proc_entry(dev->name, pSkRootDir); - FreeResources(dev); - kfree(dev); - continue; - } - - pNet->proc = create_proc_entry(dev->name, - S_IFREG | 0444, pSkRootDir); - if (pNet->proc) { - pNet->proc->data = dev; - pNet->proc->owner = THIS_MODULE; - pNet->proc->proc_fops = &sk_proc_fops; - } - - boards_found++; - - /* More then one port found */ - if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) { - dev = alloc_etherdev(sizeof(DEV_NET)); - if (!dev) { - printk(KERN_ERR "Unable to allocate etherdev " - "structure!\n"); - break; - } - - pAC->dev[1] = dev; - pNet = dev->priv; - pNet->PortNr = 1; - pNet->NetNr = 1; - pNet->pAC = pAC; - pNet->Mtu = 1500; - pNet->Up = 0; - - dev->open = &SkGeOpen; - dev->stop = &SkGeClose; - dev->hard_start_xmit = &SkGeXmit; - dev->get_stats = &SkGeStats; - dev->set_multicast_list = &SkGeSetRxMode; - dev->set_mac_address = &SkGeSetMacAddr; - dev->do_ioctl = &SkGeIoctl; - dev->change_mtu = &SkGeChangeMtu; - - memcpy((caddr_t) &dev->dev_addr, - (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6); - - printk("%s: %s\n", dev->name, pAC->DeviceStr); - printk(" PrefPort:B RlmtMode:Dual Check Link State\n"); - - if (register_netdev(dev) != 0) { - printk(KERN_ERR "Unable to register etherdev\n"); - kfree(dev); - break; - } - - pNet->proc = create_proc_entry(dev->name, - S_IFREG | 0444, pSkRootDir); - if (pNet->proc) { - pNet->proc->data = dev; - pNet->proc->owner = THIS_MODULE; - pNet->proc->proc_fops = &sk_proc_fops; - } - - } - - - /* - * This is bollocks, but we need to tell the net-init - * code that it shall go for the next device. - */ -#ifndef MODULE - dev->base_addr = 0; -#endif + printk("%s: %s\n", sec_dev->name, pAC->DeviceStr); + printk(" PrefPort:B RlmtMode:Dual Check Link State\n"); } + pci_set_drvdata(pdev, dev); - /* - * If we're at this point we're going through skge_probe() for - * the first time. Return success (0) if we've initialized 1 - * or more boards. Otherwise, return failure (-ENODEV). - */ - - return boards_found; -} /* skge_probe */ + ret = 0; +out: + return ret; + +out_free_secondary_dev: + kfree(pAC->dev[1]); +out_free_resources: + FreeResources(dev); +out_dev_uninit: + SkGeDevCleanUp(dev); +out_free_priv: + kfree(pAC); +out_free_dev: + kfree(dev); +out_disable: + pci_disable_device(pdev); + goto out; +} /* skge_init_one */ /***************************************************************************** * @@ -718,39 +706,9 @@ static char *RlmtMode[SK_MAX_CARD_PARAM] static int debug = 0; /* not used */ static int options[SK_MAX_CARD_PARAM] = {0, }; /* not used */ - -/***************************************************************************** - * - * skge_init_module - module initialization function - * - * Description: - * Very simple, only call skge_probe and return approriate result. - * - * Returns: - * 0, if everything is ok - * !=0, on error - */ -static int __init skge_init_module(void) -{ - int cards; - sk98lin_root_dev = NULL; - - /* just to avoid warnings ... */ - debug = 0; - options[0] = 0; - - cards = skge_probe(); - if (cards == 0) { - printk("No adapter found\n"); - } - return cards ? 0 : -ENODEV; -} /* skge_init_module */ - -spinlock_t sk_devs_lock = SPIN_LOCK_UNLOCKED; - /***************************************************************************** * - * skge_cleanup_module - module unload function + * skge_remove_one - remove a single instance of a SK-98xx adapter * * Description: * Disable adapter if it is still running, free resources, @@ -758,82 +716,65 @@ spinlock_t sk_devs_lock = SPIN_LOCK_UNLO * * Returns: N/A */ -static void __exit skge_cleanup_module(void) +static void __devexit skge_remove_one(struct pci_dev *pdev) { -DEV_NET *pNet; -SK_AC *pAC; -struct net_device *next; -unsigned long Flags; -SK_EVPARA EvPara; + struct net_device *dev = pci_get_drvdata(pdev); + DEV_NET *pNet = dev->priv; + SK_AC *pAC = pNet->pAC; + unsigned long Flags; + SK_EVPARA EvPara; - while (sk98lin_root_dev) { - pNet = (DEV_NET*) sk98lin_root_dev->priv; - pAC = pNet->pAC; - next = pAC->Next; - netif_stop_queue(sk98lin_root_dev); - SkGeYellowLED(pAC, pAC->IoBase, 0); - if (pNet->proc) { - spin_lock(&sk_devs_lock); - pNet->proc->data = NULL; - spin_unlock(&sk_devs_lock); - } - - if(pAC->BoardLevel == 2) { - /* board is still alive */ - spin_lock_irqsave(&pAC->SlowPathLock, Flags); - EvPara.Para32[0] = 0; - EvPara.Para32[1] = -1; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); - EvPara.Para32[0] = 1; - EvPara.Para32[1] = -1; - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); - SkEventDispatcher(pAC, pAC->IoBase); - /* disable interrupts */ - SK_OUT32(pAC->IoBase, B0_IMSK, 0); - SkGeDeInit(pAC, pAC->IoBase); - spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); - pAC->BoardLevel = 0; - /* We do NOT check here, if IRQ was pending, of course*/ - } - - if(pAC->BoardLevel == 1) { - /* board is still alive */ - SkGeDeInit(pAC, pAC->IoBase); - pAC->BoardLevel = 0; - } - - if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){ - pNet = (DEV_NET*) pAC->dev[1]->priv; - if (pNet->proc) { - spin_lock(&sk_devs_lock); - pNet->proc->data = NULL; - spin_unlock(&sk_devs_lock); - } - unregister_netdev(pAC->dev[1]); - kfree(pAC->dev[1]); - } + netif_stop_queue(dev); + SkGeYellowLED(pAC, pAC->IoBase, 0); + if (pNet->proc) { + spin_lock(&sk_devs_lock); + pNet->proc->data = NULL; + spin_unlock(&sk_devs_lock); + remove_proc_entry(dev->name, pSkRootDir); + } - FreeResources(sk98lin_root_dev); + if (pAC->BoardLevel == 2) { + /* board is still alive */ + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + EvPara.Para32[0] = 0; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + EvPara.Para32[0] = 1; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + SkEventDispatcher(pAC, pAC->IoBase); + /* disable interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + SkGeDeInit(pAC, pAC->IoBase); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + pAC->BoardLevel = 0; + /* We do NOT check here, if IRQ was pending, of course*/ + } - sk98lin_root_dev->get_stats = NULL; - /* - * otherwise unregister_netdev calls get_stats with - * invalid IO ... :-( - */ - unregister_netdev(sk98lin_root_dev); - kfree(sk98lin_root_dev); - kfree(pAC); - sk98lin_root_dev = next; + if (pAC->BoardLevel == 1) { + /* board is still alive */ + SkGeDeInit(pAC, pAC->IoBase); + pAC->BoardLevel = 0; } - /* clear proc-dir */ - remove_proc_entry(pSkRootDir->name, proc_net); + if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2) { + SkGeDevCleanUp(pAC->dev[1]); + kfree(pAC->dev[1]); + } -} /* skge_cleanup_module */ + FreeResources(dev); -module_init(skge_init_module); -module_exit(skge_cleanup_module); + dev->get_stats = NULL; + /* + * otherwise unregister_netdev calls get_stats with + * invalid IO ... :-( + */ + unregister_netdev(dev); + kfree(dev); + kfree(pAC); + boards_found--; +} /* skge_remove_one */ /***************************************************************************** * @@ -968,12 +909,6 @@ int Ret; /* return code of request_irq SkGeYellowLED(pAC, pAC->IoBase, 1); - /* - * Register the device here - */ - pAC->Next = sk98lin_root_dev; - sk98lin_root_dev = dev; - return (0); } /* SkGeBoardInit */ @@ -4097,9 +4032,62 @@ int l; #endif /* DEBUG */ +static struct pci_device_id skge_pci_tbl[] __devinitdata = { + { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE, + PCI_ANY_ID, PCI_ANY_ID, }, + { 0,} +}; +MODULE_DEVICE_TABLE(pci, skge_pci_tbl); + +static struct pci_driver skge_driver = { + .name = DRV_MODULE_NAME, + .id_table = skge_pci_tbl, + .probe = skge_init_one, + .remove = __devexit_p(skge_remove_one), +}; + +/***************************************************************************** + * + * skge_init - module initialization function + * + * Description: + * root /proc directory allocation and pci driver invocation. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +static int __init skge_init(void) +{ + int ret = -ENOMEM; + + /* just to avoid warnings ... */ + debug = 0; + options[0] = 0; + + pSkRootDir = create_proc_entry(DRV_MODULE_NAME, + S_IFDIR | S_IWUSR | S_IRUGO | S_IXUGO, proc_net); + if (pSkRootDir) { + pSkRootDir->owner = THIS_MODULE; + ret = pci_module_init(&skge_driver); + if (ret) + remove_proc_entry(pSkRootDir->name, proc_net); + } + return ret; +} /* skge_init */ + + +static void __exit skge_cleanup(void) +{ + remove_proc_entry(pSkRootDir->name, proc_net); + pci_unregister_driver(&skge_driver); +} + +module_init(skge_init); +module_exit(skge_cleanup); + /* * Local variables: * compile-command: "make" * End: */ - --- linux-2.5.73/drivers/net/Space.c 2003-06-16 22:32:21.000000000 -0700 +++ 25/drivers/net/Space.c 2003-06-27 15:56:24.000000000 -0700 @@ -82,7 +82,6 @@ extern int sonic_probe(struct net_device extern int SK_init(struct net_device *); extern int seeq8005_probe(struct net_device *); extern int smc_init( struct net_device * ); -extern int sgiseeq_probe(struct net_device *); extern int atarilance_probe(struct net_device *); extern int sun3lance_probe(struct net_device *); extern int sun3_82586_probe(struct net_device *); @@ -343,14 +342,6 @@ static struct devprobe m68k_probes[] __i {NULL, 0}, }; - -static struct devprobe sgi_probes[] __initdata = { -#ifdef CONFIG_SGISEEQ - {sgiseeq_probe, 0}, -#endif - {NULL, 0}, -}; - static struct devprobe mips_probes[] __initdata = { #ifdef CONFIG_MIPS_JAZZ_SONIC {sonic_probe, 0}, @@ -385,8 +376,6 @@ static int __init ethif_probe(struct net return 0; if (probe_list(dev, mips_probes) == 0) return 0; - if (probe_list(dev, sgi_probes) == 0) - return 0; if (probe_list(dev, eisa_probes) == 0) return 0; if (probe_list(dev, mca_probes) == 0) --- linux-2.5.73/drivers/net/sungem.c 2003-06-14 12:18:34.000000000 -0700 +++ 25/drivers/net/sungem.c 2003-06-27 15:56:24.000000000 -0700 @@ -2384,9 +2384,6 @@ static int gem_ethtool_ioctl(struct net_ return 0; case ETHTOOL_SSET: - if (!capable(CAP_NET_ADMIN)) - return -EPERM; - /* Verify the settings we care about. */ if (ecmd.autoneg != AUTONEG_ENABLE && ecmd.autoneg != AUTONEG_DISABLE) --- linux-2.5.73/drivers/net/sunhme.c 2003-06-14 12:18:06.000000000 -0700 +++ 25/drivers/net/sunhme.c 2003-06-27 15:56:24.000000000 -0700 @@ -2481,9 +2481,6 @@ static int happy_meal_ioctl(struct net_d return -EFAULT; return 0; } else if (ecmd.cmd == ETHTOOL_SSET) { - if (!capable(CAP_NET_ADMIN)) - return -EPERM; - /* Verify the settings we care about. */ if (ecmd.autoneg != AUTONEG_ENABLE && ecmd.autoneg != AUTONEG_DISABLE) --- linux-2.5.73/drivers/net/tulip/tulip_core.c 2003-06-14 12:18:23.000000000 -0700 +++ 25/drivers/net/tulip/tulip_core.c 2003-06-27 15:56:24.000000000 -0700 @@ -94,6 +94,8 @@ static int csr0 = 0x01A00000 | 0x8000; static int csr0 = 0x01A00000 | 0x9000; #elif defined(__arm__) || defined(__sh__) static int csr0 = 0x01A00000 | 0x4800; +#elif defined(__mips__) +static int csr0 = 0x00200000 | 0x4000; #else #warning Processor architecture undefined! static int csr0 = 0x00A00000 | 0x4800; @@ -1491,6 +1493,16 @@ static int __devinit tulip_init_one (str tp->flags &= ~HAS_MEDIA_TABLE; } #endif +#ifdef CONFIG_MIPS_COBALT + if ((pdev->bus->number == 0) && + ((PCI_SLOT(pdev->devfn) == 7) || + (PCI_SLOT(pdev->devfn) == 12))) { + /* Cobalt MAC address in first EEPROM locations. */ + sa_offset = 0; + /* No media table either */ + tp->flags &= ~HAS_MEDIA_TABLE; + } +#endif #ifdef __hppa__ /* 3x5 HSC (J3514A) has a broken srom */ if(ee_data[0] == 0x61 && ee_data[1] == 0x10) { --- linux-2.5.73/drivers/net/wan/sdla_chdlc.c 2003-06-14 12:18:21.000000000 -0700 +++ 25/drivers/net/wan/sdla_chdlc.c 2003-06-27 15:56:24.000000000 -0700 @@ -996,13 +996,11 @@ static int if_open(struct net_device* de set_bit(0,&chdlc_priv_area->config_chdlc); chdlc_priv_area->config_chdlc_timeout=jiffies; - del_timer(&chdlc_priv_area->poll_delay_timer); /* Start the CHDLC configuration after 1sec delay. * This will give the interface initilization time * to finish its configuration */ - chdlc_priv_area->poll_delay_timer.expires=jiffies+HZ; - add_timer(&chdlc_priv_area->poll_delay_timer); + mod_timer(&chdlc_priv_area->poll_delay_timer, jiffies + HZ); return err; } --- linux-2.5.73/drivers/net/wan/sdla_fr.c 2003-06-14 12:18:50.000000000 -0700 +++ 25/drivers/net/wan/sdla_fr.c 2003-06-27 15:56:24.000000000 -0700 @@ -4163,9 +4163,7 @@ static void trigger_fr_arp(struct net_de { fr_channel_t* chan = dev->priv; - del_timer(&chan->fr_arp_timer); - chan->fr_arp_timer.expires = jiffies + (chan->inarp_interval * HZ); - add_timer(&chan->fr_arp_timer); + mod_timer(&chan->fr_arp_timer, jiffies + chan->inarp_interval * HZ); return; } --- linux-2.5.73/drivers/net/wan/sdla_ppp.c 2003-06-14 12:18:00.000000000 -0700 +++ 25/drivers/net/wan/sdla_ppp.c 2003-06-27 15:56:24.000000000 -0700 @@ -762,9 +762,7 @@ static int if_open(struct net_device *de /* Start the PPP configuration after 1sec delay. * This will give the interface initilization time * to finish its configuration */ - del_timer(&ppp_priv_area->poll_delay_timer); - ppp_priv_area->poll_delay_timer.expires = jiffies+HZ; - add_timer(&ppp_priv_area->poll_delay_timer); + mod_timer(&ppp_priv_area->poll_delay_timer, jiffies + HZ); return 0; } --- linux-2.5.73/drivers/net/wan/sdla_x25.c 2003-06-14 12:18:25.000000000 -0700 +++ 25/drivers/net/wan/sdla_x25.c 2003-06-27 15:56:24.000000000 -0700 @@ -1235,9 +1235,7 @@ static int if_open(struct net_device* de connect(card); S508_S514_unlock(card, &smp_flags); - del_timer(&card->u.x.x25_timer); - card->u.x.x25_timer.expires=jiffies+HZ; - add_timer(&card->u.x.x25_timer); + mod_timer(&card->u.x.x25_timer, jiffies + HZ); } } /* Device is not up until the we are in connected state */ --- linux-2.5.73/drivers/net/wireless/airo.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/net/wireless/airo.c 2003-06-27 15:56:37.000000000 -0700 @@ -44,6 +44,7 @@ #include #include #include +#include #include #ifdef CONFIG_PCI @@ -2379,20 +2380,26 @@ static u16 setup_card(struct airo_info * static u16 issuecommand(struct airo_info *ai, Cmd *pCmd, Resp *pRsp) { // Im really paranoid about letting it run forever! int max_tries = 600000; + static int max = 0; + int count = 0; if (sendcommand(ai, pCmd) == (u16)ERROR) return ERROR; while (max_tries-- && (IN4500(ai, EVSTAT) & EV_CMD) == 0) { - if (!in_interrupt() && (max_tries & 255) == 0) - schedule(); + udelay(1); + count++; } - if ( max_tries == -1 ) { + if (max_tries == -1) { printk( KERN_ERR "airo: Max tries exceeded waiting for command\n" ); return ERROR; } completecommand(ai, pRsp); + if (count > max) { + max = count; + printk("%s: max delay = %d usec\n", __FUNCTION__, max); + } return SUCCESS; } --- linux-2.5.73/drivers/pci/hotplug/acpiphp_core.c 2003-06-22 12:04:44.000000000 -0700 +++ 25/drivers/pci/hotplug/acpiphp_core.c 2003-06-27 15:56:24.000000000 -0700 @@ -380,6 +380,25 @@ static void make_slot_name (struct slot } /** + * release_slot - free up the memory used by a slot + * @hotplug_slot: slot to free + */ +static void release_slot(struct hotplug_slot *hotplug_slot) +{ + struct slot *slot = get_slot(hotplug_slot, __FUNCTION__); + + if (slot == NULL) + return; + + dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name); + + kfree(slot->hotplug_slot->info); + kfree(slot->hotplug_slot->name); + kfree(slot->hotplug_slot); + kfree(slot); +} + +/** * init_slots - initialize 'struct slot' structures for each slot * */ @@ -422,6 +441,7 @@ static int init_slots (void) slot->number = i; slot->hotplug_slot->private = slot; + slot->hotplug_slot->release = &release_slot; slot->hotplug_slot->ops = &acpi_hotplug_slot_ops; slot->acpi_slot = get_slot_from_id(i); @@ -435,10 +455,7 @@ static int init_slots (void) retval = pci_hp_register(slot->hotplug_slot); if (retval) { err("pci_hp_register failed with error %d\n", retval); - kfree(slot->hotplug_slot->info); - kfree(slot->hotplug_slot->name); - kfree(slot->hotplug_slot); - kfree(slot); + release_slot(slot->hotplug_slot); return retval; } @@ -457,13 +474,10 @@ static void cleanup_slots (void) struct slot *slot; list_for_each_safe (tmp, n, &slot_list) { + /* memory will be freed in release_slot callback */ slot = list_entry(tmp, struct slot, slot_list); list_del(&slot->slot_list); pci_hp_deregister(slot->hotplug_slot); - kfree(slot->hotplug_slot->info); - kfree(slot->hotplug_slot->name); - kfree(slot->hotplug_slot); - kfree(slot); } return; --- linux-2.5.73/drivers/pci/hotplug.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pci/hotplug.c 2003-06-27 15:56:24.000000000 -0700 @@ -12,7 +12,6 @@ static void pci_free_resources(struct pci_dev *dev); -#ifdef CONFIG_HOTPLUG int pci_hotplug (struct device *dev, char **envp, int num_envp, char *buffer, int buffer_size) { @@ -209,16 +208,6 @@ int pci_remove_device_safe(struct pci_de } EXPORT_SYMBOL(pci_remove_device_safe); -#else /* CONFIG_HOTPLUG */ - -int pci_hotplug (struct device *dev, char **envp, int num_envp, - char *buffer, int buffer_size) -{ - return -ENODEV; -} - -#endif /* CONFIG_HOTPLUG */ - static void pci_free_resources(struct pci_dev *dev) { @@ -283,7 +272,5 @@ void pci_remove_behind_bridge(struct pci } } -#ifdef CONFIG_HOTPLUG EXPORT_SYMBOL(pci_remove_bus_device); EXPORT_SYMBOL(pci_remove_behind_bridge); -#endif --- linux-2.5.73/drivers/pci/hotplug/cpci_hotplug_core.c 2003-06-14 12:18:08.000000000 -0700 +++ 25/drivers/pci/hotplug/cpci_hotplug_core.c 2003-06-27 15:56:24.000000000 -0700 @@ -278,6 +278,19 @@ get_adapter_status(struct hotplug_slot * return 0; } +static void release_slot(struct hotplug_slot *hotplug_slot) +{ + struct slot *slot = get_slot(hotplug_slot, __FUNCTION__); + + if(slot == NULL) + return; + + kfree(slot->hotplug_slot->info); + kfree(slot->hotplug_slot->name); + kfree(slot->hotplug_slot); + kfree(slot); +} + #define SLOT_NAME_SIZE 6 static void make_slot_name(struct slot *slot) @@ -346,6 +359,7 @@ cpci_hp_register_bus(struct pci_bus *bus slot->devfn = PCI_DEVFN(i, 0); hotplug_slot->private = slot; + hotplug_slot->release = &release_slot; make_slot_name(slot); hotplug_slot->ops = &cpci_hotplug_slot_ops; @@ -382,6 +396,7 @@ cpci_hp_unregister_bus(struct pci_bus *b { struct slot *slot; struct list_head *tmp; + struct list_head *next; int status; if(!bus) { @@ -393,7 +408,7 @@ cpci_hp_unregister_bus(struct pci_bus *b spin_unlock(&list_lock); return -1; } - list_for_each(tmp, &slot_list) { + list_for_each_safe(tmp, next, &slot_list) { slot = list_entry(tmp, struct slot, slot_list); if(slot->bus == bus) { dbg("deregistering slot %s", slot->hotplug_slot->name); @@ -405,11 +420,6 @@ cpci_hp_unregister_bus(struct pci_bus *b } list_del(&slot->slot_list); - kfree(slot->hotplug_slot->info); - kfree(slot->hotplug_slot->name); - kfree(slot->hotplug_slot); - kfree(slot); - slots--; } } --- linux-2.5.73/drivers/pci/hotplug/cpqphp_core.c 2003-06-14 12:17:55.000000000 -0700 +++ 25/drivers/pci/hotplug/cpqphp_core.c 2003-06-27 15:56:24.000000000 -0700 @@ -312,6 +312,20 @@ static void *get_SMBIOS_entry (void *smb return previous; } +static void release_slot(struct hotplug_slot *hotplug_slot) +{ + struct slot *slot = get_slot (hotplug_slot, __FUNCTION__); + + if (slot == NULL) + return; + + dbg("%s - physical_slot = %s\n", __FUNCTION__, hotplug_slot->name); + + kfree(slot->hotplug_slot->info); + kfree(slot->hotplug_slot->name); + kfree(slot->hotplug_slot); + kfree(slot); +} static int ctrl_slot_setup (struct controller * ctrl, void *smbios_start, void *smbios_table) { @@ -401,6 +415,7 @@ static int ctrl_slot_setup (struct contr new_slot->capabilities |= ((read_slot_enable(ctrl) << 2) >> ctrl_slot) & 0x04; /* register this slot with the hotplug pci core */ + new_slot->hotplug_slot->release = &release_slot; new_slot->hotplug_slot->private = new_slot; make_slot_name (new_slot->hotplug_slot->name, SLOT_NAME_SIZE, new_slot); new_slot->hotplug_slot->ops = &cpqphp_hotplug_slot_ops; @@ -415,10 +430,7 @@ static int ctrl_slot_setup (struct contr result = pci_hp_register (new_slot->hotplug_slot); if (result) { err ("pci_hp_register failed with error %d\n", result); - kfree (new_slot->hotplug_slot->info); - kfree (new_slot->hotplug_slot->name); - kfree (new_slot->hotplug_slot); - kfree (new_slot); + release_slot(new_slot->hotplug_slot); return result; } @@ -430,10 +442,9 @@ static int ctrl_slot_setup (struct contr slot_number++; } - return(0); + return 0; } - static int ctrl_slot_cleanup (struct controller * ctrl) { struct slot *old_slot, *next_slot; @@ -442,12 +453,9 @@ static int ctrl_slot_cleanup (struct con ctrl->slot = NULL; while (old_slot) { + /* memory will be freed by the release_slot callback */ next_slot = old_slot->next; pci_hp_deregister (old_slot->hotplug_slot); - kfree(old_slot->hotplug_slot->info); - kfree(old_slot->hotplug_slot->name); - kfree(old_slot->hotplug_slot); - kfree(old_slot); old_slot = next_slot; } @@ -498,7 +506,7 @@ static int get_slot_mapping (struct pci_ sizeof(struct irq_routing_table)) / sizeof(struct irq_info); // Make sure I got at least one entry if (len == 0) { - if (PCIIRQRoutingInfoLength != NULL) kfree(PCIIRQRoutingInfoLength ); + kfree(PCIIRQRoutingInfoLength); return -1; } @@ -509,9 +517,7 @@ static int get_slot_mapping (struct pci_ if ((tbus == bus_num) && (tdevice == dev_num)) { *slot = tslot; - - if (PCIIRQRoutingInfoLength != NULL) - kfree(PCIIRQRoutingInfoLength); + kfree(PCIIRQRoutingInfoLength); return 0; } else { // Didn't get a match on the target PCI device. Check if the @@ -540,10 +546,10 @@ static int get_slot_mapping (struct pci_ // slot number for the bridge. if (bridgeSlot != 0xFF) { *slot = bridgeSlot; - if (PCIIRQRoutingInfoLength != NULL) kfree(PCIIRQRoutingInfoLength ); + kfree(PCIIRQRoutingInfoLength); return 0; } - if (PCIIRQRoutingInfoLength != NULL) kfree(PCIIRQRoutingInfoLength ); + kfree(PCIIRQRoutingInfoLength); // Couldn't find an entry in the routing table for this PCI device return -1; } --- linux-2.5.73/drivers/pci/hotplug/cpqphp_pci.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pci/hotplug/cpqphp_pci.c 2003-06-27 15:56:24.000000000 -0700 @@ -198,7 +198,7 @@ static int PCI_ScanBusForNonBridge(struc ctrl->pci_bus->number = bus_num; - for (tdevice = 0; tdevice < 0x100; tdevice++) { + for (tdevice = 0; tdevice < 0xFF; tdevice++) { //Scan for access first if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1) continue; @@ -210,7 +210,7 @@ static int PCI_ScanBusForNonBridge(struc return 0; } } - for (tdevice = 0; tdevice < 0x100; tdevice++) { + for (tdevice = 0; tdevice < 0xFF; tdevice++) { //Scan for access first if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1) continue; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/pci/hotplug/fakephp.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,232 @@ +/* + * Fake PCI Hot Plug Controller Driver + * + * Copyright (c) 2003 Greg Kroah-Hartman + * Copyright (c) 2003 IBM Corp. + * Copyright (c) 2003 Rolf Eike Beer + * + * Based on ideas and code from: + * Vladimir Kondratiev + * Rolf Eike Beer + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * Send feedback to + */ + +/* + * + * This driver will "emulate" removing PCI devices from the system. If + * the "power" file is written to with "0" then the specified PCI device + * will be completely removed from the kernel. + * + * WARNING, this does NOT turn off the power to the PCI device. This is + * a "logical" removal, not a physical or electrical removal. + * + * Use this module at your own risk, you have been warned! + * + * Enabling PCI devices is left as an exercise for the reader... + * + */ +#include +#include +#include +#include +#include +#include "pci_hotplug.h" +#include "../pci.h" + +#if !defined(CONFIG_HOTPLUG_PCI_FAKE_MODULE) + #define MY_NAME "fakephp" +#else + #define MY_NAME THIS_MODULE->name +#endif + +#define dbg(format, arg...) \ + do { \ + if (debug) \ + printk(KERN_DEBUG "%s: " format, \ + MY_NAME , ## arg); \ + } while (0) +#define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg) +#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg) + +#define DRIVER_AUTHOR "Greg Kroah-Hartman " +#define DRIVER_DESC "Fake PCI Hot Plug Controller Driver" + +struct dummy_slot { + struct list_head node; + struct hotplug_slot *slot; + struct pci_dev *dev; +}; + +static int debug; +static LIST_HEAD(slot_list); + +static int enable_slot (struct hotplug_slot *slot); +static int disable_slot (struct hotplug_slot *slot); + +static struct hotplug_slot_ops dummy_hotplug_slot_ops = { + .owner = THIS_MODULE, + .enable_slot = enable_slot, + .disable_slot = disable_slot, +}; + +static void dummy_release(struct hotplug_slot *slot) +{ + struct dummy_slot *dslot = slot->private; + + list_del(&dslot->node); + kfree(dslot->slot->info); + kfree(dslot->slot); + pci_dev_put(dslot->dev); + kfree(dslot); +} + +static int add_slot(struct pci_dev *dev) +{ + struct dummy_slot *dslot; + struct hotplug_slot *slot; + int retval = -ENOMEM; + + slot = kmalloc(sizeof(struct hotplug_slot), GFP_KERNEL); + if (!slot) + goto error; + memset(slot, 0, sizeof(*slot)); + + slot->info = kmalloc(sizeof(struct hotplug_slot_info), GFP_KERNEL); + if (!slot->info) + goto error_slot; + memset(slot->info, 0, sizeof(struct hotplug_slot_info)); + + slot->info->power_status = 1; + slot->info->max_bus_speed = PCI_SPEED_UNKNOWN; + slot->info->cur_bus_speed = PCI_SPEED_UNKNOWN; + + slot->name = &dev->dev.bus_id[0]; + dbg("slot->name = %s\n", slot->name); + + dslot = kmalloc(sizeof(struct dummy_slot), GFP_KERNEL); + if (!dslot) + goto error_info; + + slot->ops = &dummy_hotplug_slot_ops; + slot->release = &dummy_release; + slot->private = dslot; + + retval = pci_hp_register(slot); + if (retval) { + err("pci_hp_register failed with error %d\n", retval); + goto error_dslot; + } + + dslot->slot = slot; + dslot->dev = pci_dev_get(dev); + list_add (&dslot->node, &slot_list); + return retval; + +error_dslot: + kfree(dslot); +error_info: + kfree(slot->info); +error_slot: + kfree(slot); +error: + return retval; +} + +static int __init pci_scan_buses(void) +{ + struct pci_dev *dev = NULL; + int retval = 0; + + while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + retval = add_slot(dev); + if (retval) { + pci_dev_put(dev); + break; + } + } + + return retval; +} + +static void remove_slot(struct dummy_slot *dslot) +{ + int retval; + + dbg("removing slot %s\n", dslot->slot->name); + retval = pci_hp_deregister(dslot->slot); + if (retval) + err("Problem unregistering a slot %s\n", dslot->slot->name); +} + +static int enable_slot(struct hotplug_slot *hotplug_slot) +{ + return -ENODEV; +} + +static int disable_slot(struct hotplug_slot *slot) +{ + struct dummy_slot *dslot; + + if (!slot) + return -ENODEV; + dslot = slot->private; + + dbg("%s - physical_slot = %s\n", __FUNCTION__, slot->name); + + /* don't disable bridged devices just yet, we can't handle them easily... */ + if (dslot->dev->subordinate) { + err("Can't remove PCI devices with other PCI devices behind it yet.\n"); + return -ENODEV; + } + + /* remove the device from the pci core */ + pci_remove_bus_device(dslot->dev); + + /* blow away this sysfs entry and other parts. */ + remove_slot(dslot); + + return 0; +} + +static void cleanup_slots (void) +{ + struct list_head *tmp; + struct list_head *next; + struct dummy_slot *dslot; + + list_for_each_safe (tmp, next, &slot_list) { + dslot = list_entry (tmp, struct dummy_slot, node); + remove_slot(dslot); + } + +} + +static int __init dummyphp_init(void) +{ + info(DRIVER_DESC "\n"); + + return pci_scan_buses(); +} + + +static void __exit dummyphp_exit(void) +{ + cleanup_slots(); +} + +module_init(dummyphp_init); +module_exit(dummyphp_exit); + +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL"); +MODULE_PARM(debug, "i"); +MODULE_PARM_DESC(debug, "Debugging mode enabled or not"); + --- linux-2.5.73/drivers/pci/hotplug/ibmphp_core.c 2003-06-14 12:18:52.000000000 -0700 +++ 25/drivers/pci/hotplug/ibmphp_core.c 2003-06-27 15:56:24.000000000 -0700 @@ -3,8 +3,8 @@ * * Written By: Chuck Cole, Jyoti Shah, Tong Yu, Irene Zubarev, IBM Corporation * - * Copyright (c) 2001 Greg Kroah-Hartman (greg@kroah.com) - * Copyright (c) 2001,2002 IBM Corp. + * Copyright (c) 2001,2003 Greg Kroah-Hartman (greg@kroah.com) + * Copyright (c) 2001-2003 IBM Corp. * * All rights reserved. * @@ -739,26 +739,8 @@ static void free_slots (void) debug ("%s -- enter\n", __FUNCTION__); list_for_each_safe (tmp, next, &ibmphp_slot_head) { - slot_cur = list_entry (tmp, struct slot, ibm_slot_list); - pci_hp_deregister (slot_cur->hotplug_slot); - - if (slot_cur->hotplug_slot) { - kfree (slot_cur->hotplug_slot); - slot_cur->hotplug_slot = NULL; - } - - if (slot_cur->ctrl) - slot_cur->ctrl = NULL; - - if (slot_cur->bus_on) - slot_cur->bus_on = NULL; - - ibmphp_unconfigure_card (&slot_cur, -1); /* we don't want to actually remove the resources, since free_resources will do just that */ - - kfree (slot_cur); - slot_cur = NULL; } debug ("%s -- exit\n", __FUNCTION__); } @@ -1221,7 +1203,6 @@ int ibmphp_do_disable_slot (struct slot { int rc; u8 flag; - int parm = 0; debug ("DISABLING SLOT... \n"); @@ -1270,7 +1251,7 @@ int ibmphp_do_disable_slot (struct slot return 0; } - rc = ibmphp_unconfigure_card (&slot_cur, parm); + rc = ibmphp_unconfigure_card (&slot_cur, 0); slot_cur->func = NULL; debug ("in disable_slot. after unconfigure_card\n"); if (rc) { --- linux-2.5.73/drivers/pci/hotplug/ibmphp_ebda.c 2003-06-14 12:17:58.000000000 -0700 +++ 25/drivers/pci/hotplug/ibmphp_ebda.c 2003-06-27 15:56:24.000000000 -0700 @@ -3,8 +3,8 @@ * * Written By: Tong Yu, IBM Corporation * - * Copyright (c) 2001 Greg Kroah-Hartman (greg@kroah.com) - * Copyright (c) 2001,2002 IBM Corp. + * Copyright (c) 2001,2003 Greg Kroah-Hartman (greg@kroah.com) + * Copyright (c) 2001-2003 IBM Corp. * * All rights reserved. * @@ -727,6 +727,64 @@ static char *create_file_name (struct sl return str; } +static int fillslotinfo(struct hotplug_slot *hotplug_slot) +{ + struct slot *slot; + int rc = 0; + + if (!hotplug_slot || !hotplug_slot->private) + return -EINVAL; + + slot = hotplug_slot->private; + rc = ibmphp_hpc_readslot(slot, READ_ALLSTAT, NULL); + if (rc) + return rc; + + // power - enabled:1 not:0 + hotplug_slot->info->power_status = SLOT_POWER(slot->status); + + // attention - off:0, on:1, blinking:2 + hotplug_slot->info->attention_status = SLOT_ATTN(slot->status, slot->ext_status); + + // latch - open:1 closed:0 + hotplug_slot->info->latch_status = SLOT_LATCH(slot->status); + + // pci board - present:1 not:0 + if (SLOT_PRESENT (slot->status)) + hotplug_slot->info->adapter_status = 1; + else + hotplug_slot->info->adapter_status = 0; +/* + if (slot->bus_on->supported_bus_mode + && (slot->bus_on->supported_speed == BUS_SPEED_66)) + hotplug_slot->info->max_bus_speed_status = BUS_SPEED_66PCIX; + else + hotplug_slot->info->max_bus_speed_status = slot->bus_on->supported_speed; +*/ + + return rc; +} + +static void release_slot(struct hotplug_slot *hotplug_slot) +{ + struct slot *slot; + + if (!hotplug_slot || !hotplug_slot->private) + return; + + slot = hotplug_slot->private; + kfree(slot->hotplug_slot->info); + kfree(slot->hotplug_slot->name); + kfree(slot->hotplug_slot); + slot->ctrl = NULL; + slot->bus_on = NULL; + + /* we don't want to actually remove the resources, since free_resources will do just that */ + ibmphp_unconfigure_card(&slot, -1); + + kfree (slot); +} + static struct pci_driver ibmphp_driver; /* @@ -900,32 +958,32 @@ static int __init ebda_rsrc_controller ( // register slots with hpc core as well as create linked list of ibm slot for (index = 0; index < hpc_ptr->slot_count; index++) { - hp_slot_ptr = (struct hotplug_slot *) kmalloc (sizeof (struct hotplug_slot), GFP_KERNEL); + hp_slot_ptr = kmalloc(sizeof(*hp_slot_ptr), GFP_KERNEL); if (!hp_slot_ptr) { rc = -ENOMEM; goto error_no_hp_slot; } - memset (hp_slot_ptr, 0, sizeof (struct hotplug_slot)); + memset(hp_slot_ptr, 0, sizeof(*hp_slot_ptr)); - hp_slot_ptr->info = (struct hotplug_slot_info *) kmalloc (sizeof (struct hotplug_slot_info), GFP_KERNEL); + hp_slot_ptr->info = kmalloc (sizeof(struct hotplug_slot_info), GFP_KERNEL); if (!hp_slot_ptr->info) { rc = -ENOMEM; goto error_no_hp_info; } - memset (hp_slot_ptr->info, 0, sizeof (struct hotplug_slot_info)); + memset(hp_slot_ptr->info, 0, sizeof(struct hotplug_slot_info)); - hp_slot_ptr->name = (char *) kmalloc (30, GFP_KERNEL); + hp_slot_ptr->name = kmalloc(30, GFP_KERNEL); if (!hp_slot_ptr->name) { rc = -ENOMEM; goto error_no_hp_name; } - tmp_slot = kmalloc (sizeof (struct slot), GFP_KERNEL); + tmp_slot = kmalloc(sizeof(*tmp_slot), GFP_KERNEL); if (!tmp_slot) { rc = -ENOMEM; goto error_no_slot; } - memset (tmp_slot, 0, sizeof (*tmp_slot)); + memset(tmp_slot, 0, sizeof(*tmp_slot)); tmp_slot->flag = TRUE; @@ -959,8 +1017,9 @@ static int __init ebda_rsrc_controller ( tmp_slot->hotplug_slot = hp_slot_ptr; hp_slot_ptr->private = tmp_slot; + hp_slot_ptr->release = release_slot; - rc = ibmphp_hpc_fillhpslotinfo (hp_slot_ptr); + rc = fillslotinfo(hp_slot_ptr); if (rc) goto error; --- linux-2.5.73/drivers/pci/hotplug/ibmphp.h 2003-06-14 12:17:58.000000000 -0700 +++ 25/drivers/pci/hotplug/ibmphp.h 2003-06-27 15:56:24.000000000 -0700 @@ -7,7 +7,7 @@ * Written By: Jyoti Shah, Tong Yu, Irene Zubarev, IBM Corporation * * Copyright (c) 2001 Greg Kroah-Hartman (greg@kroah.com) - * Copyright (c) 2001,2002 IBM Corp. + * Copyright (c) 2001-2003 IBM Corp. * * All rights reserved. * @@ -398,7 +398,6 @@ extern int ibmphp_hpc_readslot (struct s extern int ibmphp_hpc_writeslot (struct slot *, u8); extern void ibmphp_lock_operations (void); extern void ibmphp_unlock_operations (void); -extern int ibmphp_hpc_fillhpslotinfo (struct hotplug_slot *); extern int ibmphp_hpc_start_poll_thread (void); extern void ibmphp_hpc_stop_poll_thread (void); --- linux-2.5.73/drivers/pci/hotplug/ibmphp_hpc.c 2003-06-14 12:18:05.000000000 -0700 +++ 25/drivers/pci/hotplug/ibmphp_hpc.c 2003-06-27 15:56:24.000000000 -0700 @@ -3,7 +3,7 @@ * * Written By: Jyoti Shah, IBM Corporation * - * Copyright (c) 2001-2002 IBM Corp. + * Copyright (c) 2001-2003 IBM Corp. * * All rights reserved. * @@ -114,7 +114,6 @@ static u8 hpc_readcmdtoindex (u8, u8); static void get_hpc_access (void); static void free_hpc_access (void); static void poll_hpc (void); -static int update_slot (struct slot *, u8); static int process_changeinstatus (struct slot *, struct slot *); static int process_changeinlatch (u8, u8, struct controller *); static int hpc_poll_thread (void *); @@ -152,11 +151,11 @@ static u8 i2c_ctrl_read (struct controll u8 status; int i; void *wpg_addr; // base addr + offset - ulong wpg_data, // data to/from WPG LOHI format - ultemp, data; // actual data HILO format + unsigned long wpg_data; // data to/from WPG LOHI format + unsigned long ultemp; + unsigned long data; // actual data HILO format - - debug_polling ("%s - Entry WPGBbar[%lx] index[%x] \n", __FUNCTION__, (ulong) WPGBbar, index); + debug_polling ("%s - Entry WPGBbar[%p] index[%x] \n", __FUNCTION__, WPGBbar, index); //-------------------------------------------------------------------- // READ - step 1 @@ -165,17 +164,17 @@ static u8 i2c_ctrl_read (struct controll if (ctlr_ptr->ctlr_type == 0x02) { data = WPG_READATADDR_MASK; // fill in I2C address - ultemp = (ulong) ctlr_ptr->u.wpeg_ctlr.i2c_addr; + ultemp = (unsigned long)ctlr_ptr->u.wpeg_ctlr.i2c_addr; ultemp = ultemp >> 1; data |= (ultemp << 8); // fill in index - data |= (ulong) index; + data |= (unsigned long)index; } else if (ctlr_ptr->ctlr_type == 0x04) { data = WPG_READDIRECT_MASK; // fill in index - ultemp = (ulong) index; + ultemp = (unsigned long)index; ultemp = ultemp << 8; data |= ultemp; } else { @@ -184,14 +183,14 @@ static u8 i2c_ctrl_read (struct controll } wpg_data = swab32 (data); // swap data before writing - (ulong) wpg_addr = (ulong) WPGBbar + (ulong) WPG_I2CMOSUP_OFFSET; + wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET; writel (wpg_data, wpg_addr); //-------------------------------------------------------------------- // READ - step 2 : clear the message buffer data = 0x00000000; wpg_data = swab32 (data); - (ulong) wpg_addr = (ulong) WPGBbar + (ulong) WPG_I2CMBUFL_OFFSET; + wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; writel (wpg_data, wpg_addr); //-------------------------------------------------------------------- @@ -199,7 +198,7 @@ static u8 i2c_ctrl_read (struct controll // 2020 : [20] OR operation at [20] offset 0x20 data = WPG_I2CMCNTL_STARTOP_MASK; wpg_data = swab32 (data); - (ulong) wpg_addr = (ulong) WPGBbar + (ulong) WPG_I2CMCNTL_OFFSET + (ulong) WPG_I2C_OR; + wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR; writel (wpg_data, wpg_addr); //-------------------------------------------------------------------- @@ -207,7 +206,7 @@ static u8 i2c_ctrl_read (struct controll i = CMD_COMPLETE_TOUT_SEC; while (i) { long_delay (1 * HZ / 100); - (ulong) wpg_addr = (ulong) WPGBbar + (ulong) WPG_I2CMCNTL_OFFSET; + wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET; wpg_data = readl (wpg_addr); data = swab32 (wpg_data); if (!(data & WPG_I2CMCNTL_STARTOP_MASK)) @@ -223,7 +222,7 @@ static u8 i2c_ctrl_read (struct controll i = CMD_COMPLETE_TOUT_SEC; while (i) { long_delay (1 * HZ / 100); - (ulong) wpg_addr = (ulong) WPGBbar + (ulong) WPG_I2CSTAT_OFFSET; + wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET; wpg_data = readl (wpg_addr); data = swab32 (wpg_data); if (HPC_I2CSTATUS_CHECK (data)) @@ -237,7 +236,7 @@ static u8 i2c_ctrl_read (struct controll //-------------------------------------------------------------------- // READ - step 6 : get DATA - (ulong) wpg_addr = (ulong) WPGBbar + (ulong) WPG_I2CMBUFL_OFFSET; + wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; wpg_data = readl (wpg_addr); data = swab32 (wpg_data); @@ -259,12 +258,12 @@ static u8 i2c_ctrl_write (struct control { u8 rc; void *wpg_addr; // base addr + offset - ulong wpg_data, // data to/from WPG LOHI format - ultemp, data; // actual data HILO format + unsigned long wpg_data; // data to/from WPG LOHI format + unsigned long ultemp; + unsigned long data; // actual data HILO format int i; - - debug_polling ("%s - Entry WPGBbar[%lx] index[%x] cmd[%x]\n", __FUNCTION__, (ulong) WPGBbar, index, cmd); + debug_polling ("%s - Entry WPGBbar[%p] index[%x] cmd[%x]\n", __FUNCTION__, WPGBbar, index, cmd); rc = 0; //-------------------------------------------------------------------- @@ -276,17 +275,17 @@ static u8 i2c_ctrl_write (struct control if (ctlr_ptr->ctlr_type == 0x02) { data = WPG_WRITEATADDR_MASK; // fill in I2C address - ultemp = (ulong) ctlr_ptr->u.wpeg_ctlr.i2c_addr; + ultemp = (unsigned long)ctlr_ptr->u.wpeg_ctlr.i2c_addr; ultemp = ultemp >> 1; data |= (ultemp << 8); // fill in index - data |= (ulong) index; + data |= (unsigned long)index; } else if (ctlr_ptr->ctlr_type == 0x04) { data = WPG_WRITEDIRECT_MASK; // fill in index - ultemp = (ulong) index; + ultemp = (unsigned long)index; ultemp = ultemp << 8; data |= ultemp; } else { @@ -295,14 +294,14 @@ static u8 i2c_ctrl_write (struct control } wpg_data = swab32 (data); // swap data before writing - (ulong) wpg_addr = (ulong) WPGBbar + (ulong) WPG_I2CMOSUP_OFFSET; + wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET; writel (wpg_data, wpg_addr); //-------------------------------------------------------------------- // WRITE - step 2 : clear the message buffer - data = 0x00000000 | (ulong) cmd; + data = 0x00000000 | (unsigned long)cmd; wpg_data = swab32 (data); - (ulong) wpg_addr = (ulong) WPGBbar + (ulong) WPG_I2CMBUFL_OFFSET; + wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; writel (wpg_data, wpg_addr); //-------------------------------------------------------------------- @@ -310,7 +309,7 @@ static u8 i2c_ctrl_write (struct control // 2020 : [20] OR operation at [20] offset 0x20 data = WPG_I2CMCNTL_STARTOP_MASK; wpg_data = swab32 (data); - (ulong) wpg_addr = (ulong) WPGBbar + (ulong) WPG_I2CMCNTL_OFFSET + (ulong) WPG_I2C_OR; + wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR; writel (wpg_data, wpg_addr); //-------------------------------------------------------------------- @@ -318,7 +317,7 @@ static u8 i2c_ctrl_write (struct control i = CMD_COMPLETE_TOUT_SEC; while (i) { long_delay (1 * HZ / 100); - (ulong) wpg_addr = (ulong) WPGBbar + (ulong) WPG_I2CMCNTL_OFFSET; + wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET; wpg_data = readl (wpg_addr); data = swab32 (wpg_data); if (!(data & WPG_I2CMCNTL_STARTOP_MASK)) @@ -335,7 +334,7 @@ static u8 i2c_ctrl_write (struct control i = CMD_COMPLETE_TOUT_SEC; while (i) { long_delay (1 * HZ / 100); - (ulong) wpg_addr = (ulong) WPGBbar + (ulong) WPG_I2CSTAT_OFFSET; + wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET; wpg_data = readl (wpg_addr); data = swab32 (wpg_data); if (HPC_I2CSTATUS_CHECK (data)) @@ -543,7 +542,7 @@ int ibmphp_hpc_readslot (struct slot * p int rc = 0; int busindex; - debug_polling ("%s - Entry pslot[%lx] cmd[%x] pstatus[%lx]\n", __FUNCTION__, (ulong) pslot, cmd, (ulong) pstatus); + debug_polling ("%s - Entry pslot[%p] cmd[%x] pstatus[%p]\n", __FUNCTION__, pslot, cmd, pstatus); if ((pslot == NULL) || ((pstatus == NULL) && (cmd != READ_ALLSTAT) && (cmd != READ_BUSSTATUS))) { @@ -683,7 +682,7 @@ int ibmphp_hpc_writeslot (struct slot * int rc = 0; int timeout; - debug_polling ("%s - Entry pslot[%lx] cmd[%x]\n", __FUNCTION__, (ulong) pslot, cmd); + debug_polling ("%s - Entry pslot[%p] cmd[%x]\n", __FUNCTION__, pslot, cmd); if (pslot == NULL) { rc = -EINVAL; err ("%s - Error Exit rc[%d]\n", __FUNCTION__, rc); @@ -917,71 +916,6 @@ static void poll_hpc (void) } -/* ---------------------------------------------------------------------- - * Name: ibmphp_hpc_fillhpslotinfo(hotplug_slot * phpslot) - * - * Action: fill out the hotplug_slot info - * - * Input: pointer to hotplug_slot - * - * Return - * Value: 0 or error codes - *-----------------------------------------------------------------------*/ -int ibmphp_hpc_fillhpslotinfo (struct hotplug_slot *phpslot) -{ - int rc = 0; - struct slot *pslot; - - if (phpslot && phpslot->private) { - pslot = (struct slot *) phpslot->private; - rc = update_slot (pslot, (u8) TRUE); - if (!rc) { - - // power - enabled:1 not:0 - phpslot->info->power_status = SLOT_POWER (pslot->status); - - // attention - off:0, on:1, blinking:2 - phpslot->info->attention_status = SLOT_ATTN (pslot->status, pslot->ext_status); - - // latch - open:1 closed:0 - phpslot->info->latch_status = SLOT_LATCH (pslot->status); - - // pci board - present:1 not:0 - if (SLOT_PRESENT (pslot->status)) - phpslot->info->adapter_status = 1; - else - phpslot->info->adapter_status = 0; -/* - if (pslot->bus_on->supported_bus_mode - && (pslot->bus_on->supported_speed == BUS_SPEED_66)) - phpslot->info->max_bus_speed_status = BUS_SPEED_66PCIX; - else - phpslot->info->max_bus_speed_status = pslot->bus_on->supported_speed; -*/ } else - rc = -EINVAL; - } else - rc = -EINVAL; - - return rc; -} - -/*---------------------------------------------------------------------- -* Name: update_slot -* -* Action: fill out slot status and extended status, controller status -* -* Input: pointer to slot struct -*---------------------------------------------------------------------*/ -static int update_slot (struct slot *pslot, u8 update) -{ - int rc = 0; - - debug ("%s - Entry pslot[%lx]\n", __FUNCTION__, (ulong) pslot); - rc = ibmphp_hpc_readslot (pslot, READ_ALLSTAT, NULL); - debug ("%s - Exit rc[%d]\n", __FUNCTION__, rc); - return rc; -} - /*---------------------------------------------------------------------- * Name: process_changeinstatus * @@ -1004,8 +938,7 @@ static int process_changeinstatus (struc u8 disable = FALSE; u8 update = FALSE; - debug ("process_changeinstatus - Entry pslot[%lx], poldslot[%lx]\n", (ulong) pslot, - (ulong) poldslot); + debug ("process_changeinstatus - Entry pslot[%p], poldslot[%p]\n", pslot, poldslot); // bit 0 - HPC_SLOT_POWER if ((pslot->status & 0x01) != (poldslot->status & 0x01)) --- linux-2.5.73/drivers/pci/hotplug/ibmphp_res.c 2003-06-14 12:18:32.000000000 -0700 +++ 25/drivers/pci/hotplug/ibmphp_res.c 2003-06-27 15:56:24.000000000 -0700 @@ -42,7 +42,7 @@ static int remove_ranges (struct bus_nod static int update_bridge_ranges (struct bus_node **); static int add_range (int type, struct range_node *, struct bus_node *); static void fix_resources (struct bus_node *); -static inline struct bus_node *find_bus_wprev (u8, struct bus_node **, u8); +static struct bus_node *find_bus_wprev (u8, struct bus_node **, u8); static LIST_HEAD(gbuses); LIST_HEAD(ibmphp_res_head); @@ -1757,7 +1757,7 @@ struct bus_node *ibmphp_find_res_bus (u8 return find_bus_wprev (bus_number, NULL, 0); } -static inline struct bus_node *find_bus_wprev (u8 bus_number, struct bus_node **prev, u8 flag) +static struct bus_node *find_bus_wprev (u8 bus_number, struct bus_node **prev, u8 flag) { struct bus_node *bus_cur; struct list_head *tmp; --- linux-2.5.73/drivers/pci/hotplug/Kconfig 2003-06-14 12:18:08.000000000 -0700 +++ 25/drivers/pci/hotplug/Kconfig 2003-06-27 15:56:24.000000000 -0700 @@ -21,6 +21,31 @@ config HOTPLUG_PCI When in doubt, say N. +config HOTPLUG_PCI_FAKE + tristate "Fake PCI Hotplug driver" + depends on HOTPLUG_PCI + help + Say Y here if you want to use the fake PCI hotplug driver. It can + be used to simulate PCI hotplug events if even if your system is + not PCI hotplug capable. + + This driver will "emulate" removing PCI devices from the system. + If the "power" file is written to with "0" then the specified PCI + device will be completely removed from the kernel. + + WARNING, this does NOT turn off the power to the PCI device. + This is a "logical" removal, not a physical or electrical + removal. + + Use this module at your own risk. You have been warned! + + This code is also available as a module ( = code which can be + inserted in and removed from the running kernel whenever you want). + The module will be called fakephp. If you want to compile it + as a module, say M here and read . + + When in doubt, say N. + config HOTPLUG_PCI_COMPAQ tristate "Compaq PCI Hotplug driver" depends on HOTPLUG_PCI && X86 --- linux-2.5.73/drivers/pci/hotplug/Makefile 2003-06-14 12:18:28.000000000 -0700 +++ 25/drivers/pci/hotplug/Makefile 2003-06-27 15:56:24.000000000 -0700 @@ -3,6 +3,7 @@ # obj-$(CONFIG_HOTPLUG_PCI) += pci_hotplug.o +obj-$(CONFIG_HOTPLUG_PCI_FAKE) += fakephp.o obj-$(CONFIG_HOTPLUG_PCI_COMPAQ) += cpqphp.o obj-$(CONFIG_HOTPLUG_PCI_IBM) += ibmphp.o obj-$(CONFIG_HOTPLUG_PCI_ACPI) += acpiphp.o --- linux-2.5.73/drivers/pci/hotplug/pci_hotplug_core.c 2003-06-14 12:18:30.000000000 -0700 +++ 25/drivers/pci/hotplug/pci_hotplug_core.c 2003-06-27 15:56:24.000000000 -0700 @@ -74,20 +74,16 @@ static struct subsystem hotplug_slots_su static ssize_t hotplug_slot_attr_show(struct kobject *kobj, struct attribute *attr, char *buf) { - struct hotplug_slot *slot=container_of(kobj, - struct hotplug_slot,kobj); - struct hotplug_slot_attribute *attribute = - container_of(attr, struct hotplug_slot_attribute, attr); + struct hotplug_slot *slot = to_hotplug_slot(kobj); + struct hotplug_slot_attribute *attribute = to_hotplug_attr(attr); return attribute->show ? attribute->show(slot, buf) : 0; } static ssize_t hotplug_slot_attr_store(struct kobject *kobj, struct attribute *attr, const char *buf, size_t len) { - struct hotplug_slot *slot=container_of(kobj, - struct hotplug_slot,kobj); - struct hotplug_slot_attribute *attribute = - container_of(attr, struct hotplug_slot_attribute, attr); + struct hotplug_slot *slot = to_hotplug_slot(kobj); + struct hotplug_slot_attribute *attribute = to_hotplug_attr(attr); return attribute->store ? attribute->store(slot, buf, len) : 0; } @@ -96,8 +92,16 @@ static struct sysfs_ops hotplug_slot_sys .store = hotplug_slot_attr_store, }; +static void hotplug_slot_release(struct kobject *kobj) +{ + struct hotplug_slot *slot = to_hotplug_slot(kobj); + if (slot->release) + slot->release(slot); +} + static struct kobj_type hotplug_slot_ktype = { - .sysfs_ops = &hotplug_slot_sysfs_ops + .sysfs_ops = &hotplug_slot_sysfs_ops, + .release = &hotplug_slot_release, }; static decl_subsys(hotplug_slots, &hotplug_slot_ktype, NULL); --- linux-2.5.73/drivers/pci/hotplug/pci_hotplug.h 2003-06-14 12:18:07.000000000 -0700 +++ 25/drivers/pci/hotplug/pci_hotplug.h 2003-06-27 15:56:24.000000000 -0700 @@ -51,6 +51,8 @@ struct hotplug_slot_attribute { ssize_t (*show)(struct hotplug_slot *, char *); ssize_t (*store)(struct hotplug_slot *, const char *, size_t); }; +#define to_hotplug_attr(n) container_of(n, struct hotplug_slot_attribute, attr); + /** * struct hotplug_slot_ops -the callbacks that the hotplug pci core can use * @owner: The module owner of this structure @@ -130,12 +132,14 @@ struct hotplug_slot { char *name; struct hotplug_slot_ops *ops; struct hotplug_slot_info *info; + void (*release) (struct hotplug_slot *slot); void *private; /* Variables below this are for use only by the hotplug pci core. */ struct list_head slot_list; struct kobject kobj; }; +#define to_hotplug_slot(n) container_of(n, struct hotplug_slot, kobj) extern int pci_hp_register (struct hotplug_slot *slot); extern int pci_hp_deregister (struct hotplug_slot *slot); --- linux-2.5.73/drivers/pci/hotplug/pcihp_skeleton.c 2003-06-14 12:18:22.000000000 -0700 +++ 25/drivers/pci/hotplug/pcihp_skeleton.c 2003-06-27 15:56:24.000000000 -0700 @@ -1,8 +1,8 @@ /* - * PCI Hot Plug Controller Skeleton Driver - 0.1 + * PCI Hot Plug Controller Skeleton Driver - 0.2 * - * Copyright (c) 2001 Greg Kroah-Hartman (greg@kroah.com) - * Copyright (c) 2001 IBM Corp. + * Copyright (c) 2001,2003 Greg Kroah-Hartman (greg@kroah.com) + * Copyright (c) 2001,2003 IBM Corp. * * All rights reserved. * @@ -69,7 +69,7 @@ static LIST_HEAD(slot_list); static int debug; static int num_slots; -#define DRIVER_VERSION "0.1" +#define DRIVER_VERSION "0.2" #define DRIVER_AUTHOR "Greg Kroah-Hartman " #define DRIVER_DESC "Hot Plug PCI Controller Skeleton Driver" @@ -288,6 +288,21 @@ static int get_adapter_status (struct ho return retval; } +static void release_slots(struct hotplug_slot *hotplug_slot) +{ + struct slot *slot = get_slot(hotplug_slot, __FUNCTION__); + int retval = 0; + + if (slot == NULL) + return -ENODEV; + + dbg(__FUNCTION__" - physical_slot = %s\n", hotplug_slot->name); + kfree(slot->hotplug_slot->info); + kfree(slot->hotplug_slot->name); + kfree(slot->hotplug_slot); + kfree(slot); +} + #define SLOT_NAME_SIZE 10 static void make_slot_name (struct slot *slot) { @@ -347,6 +362,7 @@ static int init_slots (void) slot->number = i; hotplug_slot->private = slot; + hotplug_slot->release = &release_slot; make_slot_name (slot); hotplug_slot->ops = &skel_hotplug_slot_ops; @@ -376,27 +392,23 @@ static int init_slots (void) return retval; } - -static void cleanup_slots (void) + +static void cleanup_slots(void) { struct list_head *tmp; + struct list_head *next; struct slot *slot; /* - * Unregister all of our slots with the pci_hotplug subsystem, - * and free up all memory that we had allocated. + * Unregister all of our slots with the pci_hotplug subsystem. + * Memory will be freed in release_slot() callback after slot's + * lifespan is finished. */ - list_for_each (tmp, &slot_list) { + list_for_each_safe (tmp, next, &slot_list) { slot = list_entry (tmp, struct slot, slot_list); list_del (&slot->slot_list); pci_hp_deregister (slot->hotplug_slot); - kfree (slot->hotplug_slot->info); - kfree (slot->hotplug_slot->name); - kfree (slot->hotplug_slot); - kfree (slot); } - - return; } static int __init pcihp_skel_init(void) --- linux-2.5.73/drivers/pci/Makefile 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pci/Makefile 2003-06-27 15:56:24.000000000 -0700 @@ -3,15 +3,16 @@ # obj-y += access.o bus.o probe.o pci.o pool.o quirks.o \ - names.o pci-driver.o search.o hotplug.o \ - pci-sysfs.o + names.o pci-driver.o search.o pci-sysfs.o obj-$(CONFIG_PM) += power.o obj-$(CONFIG_PROC_FS) += proc.o ifndef CONFIG_SPARC64 -obj-$(CONFIG_PCI) += setup-res.o +obj-y += setup-res.o endif +obj-$(CONFIG_HOTPLUG) += hotplug.o + # Build the PCI Hotplug drivers if we were asked to obj-$(CONFIG_HOTPLUG_PCI) += hotplug/ @@ -24,16 +25,11 @@ obj-$(CONFIG_PARISC) += setup-bus.o obj-$(CONFIG_SUPERH) += setup-bus.o setup-irq.o obj-$(CONFIG_PPC32) += setup-irq.o obj-$(CONFIG_PPC64) += setup-bus.o -obj-$(CONFIG_DDB5476) += setup-bus.o obj-$(CONFIG_SGI_IP27) += setup-irq.o +obj-$(CONFIG_SGI_IP32) += setup-irq.o obj-$(CONFIG_X86_VISWS) += setup-irq.o -# CompactPCI hotplug requires the pbus_* functions -ifdef CONFIG_HOTPLUG_PCI_CPCI -obj-y += setup-bus.o -endif - -# Hotplug (eg, cardbus) now requires setup-bus +# Cardbus & CompactPCI use setup-bus obj-$(CONFIG_HOTPLUG) += setup-bus.o ifndef CONFIG_X86 --- linux-2.5.73/drivers/pci/pci.c 2003-06-14 12:18:05.000000000 -0700 +++ 25/drivers/pci/pci.c 2003-06-27 15:56:24.000000000 -0700 @@ -747,6 +747,7 @@ struct pci_dev *isa_bridge; EXPORT_SYMBOL(isa_bridge); #endif +EXPORT_SYMBOL(pci_enable_device_bars); EXPORT_SYMBOL(pci_enable_device); EXPORT_SYMBOL(pci_disable_device); EXPORT_SYMBOL(pci_max_busnr); --- linux-2.5.73/drivers/pci/pci-driver.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pci/pci-driver.c 2003-06-27 15:56:24.000000000 -0700 @@ -486,6 +486,14 @@ void pci_dev_put(struct pci_dev *dev) put_device(&dev->dev); } +#ifndef CONFIG_HOTPLUG +int pci_hotplug (struct device *dev, char **envp, int num_envp, + char *buffer, int buffer_size) +{ + return -ENODEV; +} +#endif + struct bus_type pci_bus_type = { .name = "pci", .match = pci_bus_match, --- linux-2.5.73/drivers/pci/probe.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pci/probe.c 2003-06-27 15:56:31.000000000 -0700 @@ -18,7 +18,10 @@ #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ #define CARDBUS_RESERVE_BUSNR 3 +/* Ugh. Need to stop exporting this to modules. */ LIST_HEAD(pci_root_buses); +EXPORT_SYMBOL(pci_root_buses); + LIST_HEAD(pci_devices); /* @@ -106,7 +109,7 @@ static void pci_read_bases(struct pci_de (((unsigned long) ~sz) << 32); #else if (l) { - printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", dev->slot_name); + printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev)); res->start = 0; res->flags = 0; continue; @@ -173,7 +176,7 @@ void __devinit pci_read_bridge_bases(str limit |= (io_limit_hi << 16); } - if (base && base <= limit) { + if (base <= limit) { res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; res->start = base; res->end = limit + 0xfff; @@ -301,7 +304,7 @@ int __devinit pci_scan_bridge(struct pci pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n", - dev->slot_name, buses & 0xffffff, pass); + pci_name(dev), buses & 0xffffff, pass); if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) { unsigned int cmax; @@ -400,8 +403,9 @@ static int pci_setup_device(struct pci_d { u32 class; - sprintf(dev->slot_name, "%02x:%02x.%d", dev->bus->number, - PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); + dev->slot_name = dev->dev.bus_id; + sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), + dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); sprintf(dev->dev.name, "PCI device %04x:%04x", dev->vendor, dev->device); @@ -449,12 +453,12 @@ static int pci_setup_device(struct pci_d default: /* unknown header */ printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", - dev->slot_name, dev->hdr_type); + pci_name(dev), dev->hdr_type); return -1; bad: printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", - dev->slot_name, class, dev->hdr_type); + pci_name(dev), class, dev->hdr_type); dev->class = PCI_CLASS_NOT_DEFINED; } @@ -528,9 +532,6 @@ pci_scan_device(struct pci_bus *bus, int pci_name_device(dev); - /* now put in global tree */ - sprintf(dev->dev.bus_id, "%04x:%s", pci_domain_nr(bus), - dev->slot_name); dev->dev.dma_mask = &dev->dma_mask; return dev; @@ -643,7 +644,7 @@ int __devinit pci_bus_exists(const struc return 0; } -static struct pci_bus * __devinit pci_alloc_primary_bus_parented(struct device *parent, int bus) +struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata) { struct pci_bus *b; @@ -656,46 +657,39 @@ static struct pci_bus * __devinit pci_al b = pci_alloc_bus(); if (!b) return NULL; - + b->dev = kmalloc(sizeof(*(b->dev)),GFP_KERNEL); if (!b->dev){ kfree(b); return NULL; } - + + b->sysdata = sysdata; + b->ops = ops; + list_add_tail(&b->node, &pci_root_buses); memset(b->dev,0,sizeof(*(b->dev))); - sprintf(b->dev->bus_id,"pci%d",bus); - strcpy(b->dev->name,"Host/PCI Bridge"); b->dev->parent = parent; + sprintf(b->dev->bus_id,"pci%04x:%02x", pci_domain_nr(b), bus); + strcpy(b->dev->name,"Host/PCI Bridge"); device_register(b->dev); b->number = b->secondary = bus; b->resource[0] = &ioport_resource; b->resource[1] = &iomem_resource; - return b; -} -struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata) -{ - struct pci_bus *b = pci_alloc_primary_bus_parented(parent, bus); - if (b) { - b->sysdata = sysdata; - b->ops = ops; - b->subordinate = pci_scan_child_bus(b); - pci_bus_add_devices(b); - } + b->subordinate = pci_scan_child_bus(b); + + pci_bus_add_devices(b); + return b; } EXPORT_SYMBOL(pci_scan_bus_parented); -EXPORT_SYMBOL(pci_root_buses); - #ifdef CONFIG_HOTPLUG EXPORT_SYMBOL(pci_add_new_bus); EXPORT_SYMBOL(pci_do_scan_bus); EXPORT_SYMBOL(pci_scan_slot); -EXPORT_SYMBOL(pci_scan_bus); EXPORT_SYMBOL(pci_scan_bridge); #endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/pcmcia/au1000_generic.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,702 @@ +/* + * + * Alchemy Semi Au1000 pcmcia driver + * + * Copyright 2001 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include "cs_internal.h" + +#include +#include +#include + +#include +#include + +#ifdef PCMCIA_DEBUG +static int pc_debug; +#endif + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Pete Popov, MontaVista Software "); +MODULE_DESCRIPTION("Linux PCMCIA Card Services: Au1x00 Socket Controller"); + +#define MAP_SIZE 0x1000000 + +/* This structure maintains housekeeping state for each socket, such + * as the last known values of the card detect pins, or the Card Services + * callback value associated with the socket: + */ +static struct au1000_pcmcia_socket *pcmcia_socket; +static int socket_count; + + +/* Returned by the low-level PCMCIA interface: */ +static struct pcmcia_low_level *pcmcia_low_level; + +/* Event poll timer structure */ +static struct timer_list poll_timer; + + +/* Prototypes for routines which are used internally: */ + +static int au1000_pcmcia_driver_init(void); +static void au1000_pcmcia_driver_shutdown(void); +static void au1000_pcmcia_task_handler(void *data); +static void au1000_pcmcia_poll_event(unsigned long data); +static void au1000_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs); +static struct tq_struct au1000_pcmcia_task; + +#ifdef CONFIG_PROC_FS +static int au1000_pcmcia_proc_status(char *buf, char **start, + off_t pos, int count, int *eof, void *data); +#endif + + +/* Prototypes for operations which are exported to the + * new-and-impr^H^H^H^H^H^H^H^H^H^H in-kernel PCMCIA core: + */ + +static int au1000_pcmcia_init(u32 sock); +static int au1000_pcmcia_suspend(u32 sock); +static int au1000_pcmcia_register_callback(u32 sock, + void (*handler)(void *, u32), void *info); +static int au1000_pcmcia_inquire_socket(u32 sock, socket_cap_t *cap); +static int au1000_pcmcia_get_status(u32 sock, u_int *value); +static int au1000_pcmcia_get_socket(u32 sock, socket_state_t *state); +static int au1000_pcmcia_set_socket(u32 sock, socket_state_t *state); +static int au1000_pcmcia_get_io_map(u32 sock, struct pccard_io_map *io); +static int au1000_pcmcia_set_io_map(u32 sock, struct pccard_io_map *io); +static int au1000_pcmcia_get_mem_map(u32 sock, struct pccard_mem_map *mem); +static int au1000_pcmcia_set_mem_map(u32 sock, struct pccard_mem_map *mem); +#ifdef CONFIG_PROC_FS +static void au1000_pcmcia_proc_setup(u32 sock, struct proc_dir_entry *base); +#endif + +static struct pccard_operations au1000_pcmcia_operations = { + au1000_pcmcia_init, + au1000_pcmcia_suspend, + au1000_pcmcia_register_callback, + au1000_pcmcia_inquire_socket, + au1000_pcmcia_get_status, + au1000_pcmcia_get_socket, + au1000_pcmcia_set_socket, + au1000_pcmcia_get_io_map, + au1000_pcmcia_set_io_map, + au1000_pcmcia_get_mem_map, + au1000_pcmcia_set_mem_map, +#ifdef CONFIG_PROC_FS + au1000_pcmcia_proc_setup +#endif +}; + +static spinlock_t pcmcia_lock = SPIN_LOCK_UNLOCKED; + +static int __init au1000_pcmcia_driver_init(void) +{ + servinfo_t info; + struct pcmcia_init pcmcia_init; + struct pcmcia_state state; + unsigned int i; + + printk("\nAu1x00 PCMCIA (CS release %s)\n", CS_RELEASE); + +#ifndef CONFIG_64BIT_PHYS_ADDR + printk(KERN_ERR "Au1x00 PCMCIA 36 bit IO support not enabled\n"); + return -1; +#endif + + CardServices(GetCardServicesInfo, &info); + + if(info.Revision!=CS_RELEASE_CODE){ + printk(KERN_ERR "Card Services release codes do not match\n"); + return -1; + } + +#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_PB1500) + pcmcia_low_level=&pb1x00_pcmcia_ops; +#else +#error Unsupported AU1000 board. +#endif + + pcmcia_init.handler=au1000_pcmcia_interrupt; + if((socket_count=pcmcia_low_level->init(&pcmcia_init))<0) { + printk(KERN_ERR "Unable to initialize PCMCIA service.\n"); + return -EIO; + } + + /* NOTE: the chip select must already be setup */ + + pcmcia_socket = + kmalloc(sizeof(struct au1000_pcmcia_socket) * socket_count, + GFP_KERNEL); + if (!pcmcia_socket) { + printk(KERN_ERR "Card Services can't get memory \n"); + return -1; + } + memset(pcmcia_socket, 0, + sizeof(struct au1000_pcmcia_socket) * socket_count); + + /* + * Assuming max of 2 sockets, which the Au1000 supports. + * WARNING: the Pb1000 has two sockets, and both work, but you + * can't use them both at the same time due to glue logic conflicts. + */ + for(i=0; i < socket_count; i++) { + + if(pcmcia_low_level->socket_state(i, &state)<0){ + printk(KERN_ERR "Unable to get PCMCIA status\n"); + return -EIO; + } + pcmcia_socket[i].k_state=state; + pcmcia_socket[i].cs_state.csc_mask=SS_DETECT; + + if (i == 0) { + pcmcia_socket[i].virt_io = + (u32)ioremap((ioaddr_t)0xF00000000, 0x1000); + pcmcia_socket[i].phys_attr = (memaddr_t)0xF40000000; + pcmcia_socket[i].phys_mem = (memaddr_t)0xF80000000; + } + else { + pcmcia_socket[i].virt_io = + (u32)ioremap((ioaddr_t)0xF08000000, 0x1000); + pcmcia_socket[i].phys_attr = (memaddr_t)0xF48000000; + pcmcia_socket[i].phys_mem = (memaddr_t)0xF88000000; + } + } + + /* Only advertise as many sockets as we can detect: */ + if(register_ss_entry(socket_count, &au1000_pcmcia_operations)<0){ + printk(KERN_ERR "Unable to register socket service routine\n"); + return -ENXIO; + } + + /* Start the event poll timer. + * It will reschedule by itself afterwards. + */ + au1000_pcmcia_poll_event(0); + + DEBUG(1, "au1000: initialization complete\n"); + return 0; + +} /* au1000_pcmcia_driver_init() */ + +module_init(au1000_pcmcia_driver_init); + +static void __exit au1000_pcmcia_driver_shutdown(void) +{ + int i; + + del_timer_sync(&poll_timer); + unregister_ss_entry(&au1000_pcmcia_operations); + pcmcia_low_level->shutdown(); + flush_scheduled_tasks(); + for(i=0; i < socket_count; i++) { + if (pcmcia_socket[i].virt_io) + iounmap((void *)pcmcia_socket[i].virt_io); + } + DEBUG(1, "au1000: shutdown complete\n"); +} + +module_exit(au1000_pcmcia_driver_shutdown); + +static int au1000_pcmcia_init(unsigned int sock) { return 0; } + +static int au1000_pcmcia_suspend(unsigned int sock) +{ + return 0; +} + + +static inline unsigned +au1000_pcmcia_events(struct pcmcia_state *state, + struct pcmcia_state *prev_state, + unsigned int mask, unsigned int flags) +{ + unsigned int events=0; + + if(state->detect!=prev_state->detect){ + DEBUG(2, "%s(): card detect value %u\n", + __FUNCTION__, state->detect); + events |= mask&SS_DETECT; + } + + + if(state->ready!=prev_state->ready){ + DEBUG(2, "%s(): card ready value %u\n", + __FUNCTION__, state->ready); + events |= mask&((flags&SS_IOCARD)?0:SS_READY); + } + + *prev_state=*state; + return events; + +} /* au1000_pcmcia_events() */ + + +/* + * Au1000_pcmcia_task_handler() + * Processes socket events. + */ +static void au1000_pcmcia_task_handler(void *data) +{ + struct pcmcia_state state; + int i, events, irq_status; + + for(i=0; isocket_state(i, &state))<0) + printk(KERN_ERR "low-level PCMCIA error\n"); + + events = au1000_pcmcia_events(&state, + &pcmcia_socket[i].k_state, + pcmcia_socket[i].cs_state.csc_mask, + pcmcia_socket[i].cs_state.flags); + if(pcmcia_socket[i].handler!=NULL) { + pcmcia_socket[i].handler(pcmcia_socket[i].handler_info, + events); + } + } + +} /* au1000_pcmcia_task_handler() */ + +static struct tq_struct au1000_pcmcia_task = { + routine: au1000_pcmcia_task_handler +}; + + +static void au1000_pcmcia_poll_event(unsigned long dummy) +{ + poll_timer.function = au1000_pcmcia_poll_event; + poll_timer.expires = jiffies + AU1000_PCMCIA_POLL_PERIOD; + add_timer(&poll_timer); + schedule_task(&au1000_pcmcia_task); +} + + +/* + * au1000_pcmcia_interrupt() + * The actual interrupt work is performed by au1000_pcmcia_task(), + * because the Card Services event handling code performs scheduling + * operations which cannot be executed from within an interrupt context. + */ +static void +au1000_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs) +{ + schedule_task(&au1000_pcmcia_task); +} + + +static int +au1000_pcmcia_register_callback(unsigned int sock, + void (*handler)(void *, unsigned int), void *info) +{ + if(handler==NULL){ + pcmcia_socket[sock].handler=NULL; + MOD_DEC_USE_COUNT; + } else { + MOD_INC_USE_COUNT; + pcmcia_socket[sock].handler=handler; + pcmcia_socket[sock].handler_info=info; + } + return 0; +} + + +/* au1000_pcmcia_inquire_socket() + * + * From the sa1100 socket driver : + * + * Implements the inquire_socket() operation for the in-kernel PCMCIA + * service (formerly SS_InquireSocket in Card Services). We set + * SS_CAP_STATIC_MAP, which disables the memory resource database check. + * (Mapped memory is set up within the socket driver itself.) + * + * In conjunction with the STATIC_MAP capability is a new field, + * `io_offset', recommended by David Hinds. Rather than go through + * the SetIOMap interface (which is not quite suited for communicating + * window locations up from the socket driver), we just pass up + * an offset which is applied to client-requested base I/O addresses + * in alloc_io_space(). + * + * Returns: 0 on success, -1 if no pin has been configured for `sock' + */ +static int au1000_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap) +{ + struct pcmcia_irq_info irq_info; + + if(sock > socket_count){ + printk(KERN_ERR "au1000: socket %u not configured\n", sock); + return -1; + } + + /* from the sa1100_generic driver: */ + + /* SS_CAP_PAGE_REGS: used by setup_cis_mem() in cistpl.c to set the + * force_low argument to validate_mem() in rsrc_mgr.c -- since in + * general, the mapped * addresses of the PCMCIA memory regions + * will not be within 0xffff, setting force_low would be + * undesirable. + * + * SS_CAP_STATIC_MAP: don't bother with the (user-configured) memory + * resource database; we instead pass up physical address ranges + * and allow other parts of Card Services to deal with remapping. + * + * SS_CAP_PCCARD: we can deal with 16-bit PCMCIA & CF cards, but + * not 32-bit CardBus devices. + */ + cap->features=(SS_CAP_PAGE_REGS | SS_CAP_STATIC_MAP | SS_CAP_PCCARD); + + irq_info.sock=sock; + irq_info.irq=-1; + + if(pcmcia_low_level->get_irq_info(&irq_info)<0){ + printk(KERN_ERR "Error obtaining IRQ info socket %u\n", sock); + return -1; + } + + cap->irq_mask=0; + cap->map_size=MAP_SIZE; + cap->pci_irq=irq_info.irq; + cap->io_offset=pcmcia_socket[sock].virt_io; + + return 0; + +} /* au1000_pcmcia_inquire_socket() */ + + +static int +au1000_pcmcia_get_status(unsigned int sock, unsigned int *status) +{ + struct pcmcia_state state; + + + if((pcmcia_low_level->socket_state(sock, &state))<0){ + printk(KERN_ERR "Unable to get PCMCIA status from kernel.\n"); + return -1; + } + + pcmcia_socket[sock].k_state = state; + + *status = state.detect?SS_DETECT:0; + + *status |= state.ready?SS_READY:0; + + *status |= pcmcia_socket[sock].cs_state.Vcc?SS_POWERON:0; + + if(pcmcia_socket[sock].cs_state.flags&SS_IOCARD) + *status |= state.bvd1?SS_STSCHG:0; + else { + if(state.bvd1==0) + *status |= SS_BATDEAD; + else if(state.bvd2 == 0) + *status |= SS_BATWARN; + } + + *status|=state.vs_3v?SS_3VCARD:0; + + *status|=state.vs_Xv?SS_XVCARD:0; + + DEBUG(2, "\tstatus: %s%s%s%s%s%s%s%s\n", + (*status&SS_DETECT)?"DETECT ":"", + (*status&SS_READY)?"READY ":"", + (*status&SS_BATDEAD)?"BATDEAD ":"", + (*status&SS_BATWARN)?"BATWARN ":"", + (*status&SS_POWERON)?"POWERON ":"", + (*status&SS_STSCHG)?"STSCHG ":"", + (*status&SS_3VCARD)?"3VCARD ":"", + (*status&SS_XVCARD)?"XVCARD ":""); + + return 0; + +} /* au1000_pcmcia_get_status() */ + + +static int +au1000_pcmcia_get_socket(unsigned int sock, socket_state_t *state) +{ + *state = pcmcia_socket[sock].cs_state; + return 0; +} + + +static int +au1000_pcmcia_set_socket(unsigned int sock, socket_state_t *state) +{ + struct pcmcia_configure configure; + + DEBUG(2, "\tmask: %s%s%s%s%s%s\n\tflags: %s%s%s%s%s%s\n" + "\tVcc %d Vpp %d irq %d\n", + (state->csc_mask==0)?"":"", + (state->csc_mask&SS_DETECT)?"DETECT ":"", + (state->csc_mask&SS_READY)?"READY ":"", + (state->csc_mask&SS_BATDEAD)?"BATDEAD ":"", + (state->csc_mask&SS_BATWARN)?"BATWARN ":"", + (state->csc_mask&SS_STSCHG)?"STSCHG ":"", + (state->flags==0)?"":"", + (state->flags&SS_PWR_AUTO)?"PWR_AUTO ":"", + (state->flags&SS_IOCARD)?"IOCARD ":"", + (state->flags&SS_RESET)?"RESET ":"", + (state->flags&SS_SPKR_ENA)?"SPKR_ENA ":"", + (state->flags&SS_OUTPUT_ENA)?"OUTPUT_ENA ":"", + state->Vcc, state->Vpp, state->io_irq); + + configure.sock=sock; + configure.vcc=state->Vcc; + configure.vpp=state->Vpp; + configure.output=(state->flags&SS_OUTPUT_ENA)?1:0; + configure.speaker=(state->flags&SS_SPKR_ENA)?1:0; + configure.reset=(state->flags&SS_RESET)?1:0; + + if(pcmcia_low_level->configure_socket(&configure)<0){ + printk(KERN_ERR "Unable to configure socket %u\n", sock); + return -1; + } + + pcmcia_socket[sock].cs_state = *state; + return 0; + +} /* au1000_pcmcia_set_socket() */ + + +static int +au1000_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *map) +{ + DEBUG(1, "au1000_pcmcia_get_io_map: sock %d\n", sock); + if(map->map>=MAX_IO_WIN){ + printk(KERN_ERR "%s(): map (%d) out of range\n", + __FUNCTION__, map->map); + return -1; + } + *map=pcmcia_socket[sock].io_map[map->map]; + return 0; +} + + +int +au1000_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *map) +{ + unsigned int speed; + unsigned long start; + + if(map->map>=MAX_IO_WIN){ + printk(KERN_ERR "%s(): map (%d) out of range\n", + __FUNCTION__, map->map); + return -1; + } + + if(map->flags&MAP_ACTIVE){ + speed=(map->speed>0)?map->speed:AU1000_PCMCIA_IO_SPEED; + pcmcia_socket[sock].speed_io=speed; + } + + start=map->start; + + if(map->stop==1) { + map->stop=PAGE_SIZE-1; + } + + map->start=pcmcia_socket[sock].virt_io; + map->stop=map->start+(map->stop-start); + pcmcia_socket[sock].io_map[map->map]=*map; + DEBUG(3, "set_io_map %d start %x stop %x\n", + map->map, map->start, map->stop); + return 0; + +} /* au1000_pcmcia_set_io_map() */ + + +static int +au1000_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *map) +{ + + if(map->map>=MAX_WIN) { + printk(KERN_ERR "%s(): map (%d) out of range\n", + __FUNCTION__, map->map); + return -1; + } + *map=pcmcia_socket[sock].mem_map[map->map]; + return 0; +} + + +static int +au1000_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *map) +{ + unsigned int speed; + unsigned long start; + u_long flags; + + if(map->map>=MAX_WIN){ + printk(KERN_ERR "%s(): map (%d) out of range\n", + __FUNCTION__, map->map); + return -1; + } + + if(map->flags&MAP_ACTIVE){ + speed=(map->speed>0)?map->speed:AU1000_PCMCIA_MEM_SPEED; + + /* TBD */ + if(map->flags&MAP_ATTRIB){ + pcmcia_socket[sock].speed_attr=speed; + } + else { + pcmcia_socket[sock].speed_mem=speed; + } + } + + spin_lock_irqsave(&pcmcia_lock, flags); + start=map->sys_start; + + if(map->sys_stop==0) + map->sys_stop=MAP_SIZE-1; + + if (map->flags & MAP_ATTRIB) { + map->sys_start = pcmcia_socket[sock].phys_attr + + map->card_start; + } + else { + map->sys_start = pcmcia_socket[sock].phys_mem + + map->card_start; + } + + map->sys_stop=map->sys_start+(map->sys_stop-start); + pcmcia_socket[sock].mem_map[map->map]=*map; + spin_unlock_irqrestore(&pcmcia_lock, flags); + DEBUG(3, "set_mem_map %d start %x stop %x card_start %x\n", + map->map, map->sys_start, map->sys_stop, + map->card_start); + return 0; + +} /* au1000_pcmcia_set_mem_map() */ + + +#if defined(CONFIG_PROC_FS) + +static void +au1000_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base) +{ + struct proc_dir_entry *entry; + + if((entry=create_proc_entry("status", 0, base))==NULL){ + printk(KERN_ERR "Unable to install \"status\" procfs entry\n"); + return; + } + + entry->read_proc=au1000_pcmcia_proc_status; + entry->data=(void *)sock; +} + + +/* au1000_pcmcia_proc_status() + * Implements the /proc/bus/pccard/??/status file. + * + * Returns: the number of characters added to the buffer + */ +static int +au1000_pcmcia_proc_status(char *buf, char **start, off_t pos, + int count, int *eof, void *data) +{ + char *p=buf; + unsigned int sock=(unsigned int)data; + + p+=sprintf(p, "k_flags : %s%s%s%s%s%s%s\n", + pcmcia_socket[sock].k_state.detect?"detect ":"", + pcmcia_socket[sock].k_state.ready?"ready ":"", + pcmcia_socket[sock].k_state.bvd1?"bvd1 ":"", + pcmcia_socket[sock].k_state.bvd2?"bvd2 ":"", + pcmcia_socket[sock].k_state.wrprot?"wrprot ":"", + pcmcia_socket[sock].k_state.vs_3v?"vs_3v ":"", + pcmcia_socket[sock].k_state.vs_Xv?"vs_Xv ":""); + + p+=sprintf(p, "status : %s%s%s%s%s%s%s%s%s\n", + pcmcia_socket[sock].k_state.detect?"SS_DETECT ":"", + pcmcia_socket[sock].k_state.ready?"SS_READY ":"", + pcmcia_socket[sock].cs_state.Vcc?"SS_POWERON ":"", + pcmcia_socket[sock].cs_state.flags&SS_IOCARD?\ + "SS_IOCARD ":"", + (pcmcia_socket[sock].cs_state.flags&SS_IOCARD && + pcmcia_socket[sock].k_state.bvd1)?"SS_STSCHG ":"", + ((pcmcia_socket[sock].cs_state.flags&SS_IOCARD)==0 && + (pcmcia_socket[sock].k_state.bvd1==0))?"SS_BATDEAD ":"", + ((pcmcia_socket[sock].cs_state.flags&SS_IOCARD)==0 && + (pcmcia_socket[sock].k_state.bvd2==0))?"SS_BATWARN ":"", + pcmcia_socket[sock].k_state.vs_3v?"SS_3VCARD ":"", + pcmcia_socket[sock].k_state.vs_Xv?"SS_XVCARD ":""); + + p+=sprintf(p, "mask : %s%s%s%s%s\n", + pcmcia_socket[sock].cs_state.csc_mask&SS_DETECT?\ + "SS_DETECT ":"", + pcmcia_socket[sock].cs_state.csc_mask&SS_READY?\ + "SS_READY ":"", + pcmcia_socket[sock].cs_state.csc_mask&SS_BATDEAD?\ + "SS_BATDEAD ":"", + pcmcia_socket[sock].cs_state.csc_mask&SS_BATWARN?\ + "SS_BATWARN ":"", + pcmcia_socket[sock].cs_state.csc_mask&SS_STSCHG?\ + "SS_STSCHG ":""); + + p+=sprintf(p, "cs_flags : %s%s%s%s%s\n", + pcmcia_socket[sock].cs_state.flags&SS_PWR_AUTO?\ + "SS_PWR_AUTO ":"", + pcmcia_socket[sock].cs_state.flags&SS_IOCARD?\ + "SS_IOCARD ":"", + pcmcia_socket[sock].cs_state.flags&SS_RESET?\ + "SS_RESET ":"", + pcmcia_socket[sock].cs_state.flags&SS_SPKR_ENA?\ + "SS_SPKR_ENA ":"", + pcmcia_socket[sock].cs_state.flags&SS_OUTPUT_ENA?\ + "SS_OUTPUT_ENA ":""); + + p+=sprintf(p, "Vcc : %d\n", pcmcia_socket[sock].cs_state.Vcc); + p+=sprintf(p, "Vpp : %d\n", pcmcia_socket[sock].cs_state.Vpp); + p+=sprintf(p, "irq : %d\n", pcmcia_socket[sock].cs_state.io_irq); + p+=sprintf(p, "I/O : %u\n", pcmcia_socket[sock].speed_io); + p+=sprintf(p, "attribute: %u\n", pcmcia_socket[sock].speed_attr); + p+=sprintf(p, "common : %u\n", pcmcia_socket[sock].speed_mem); + return p-buf; +} + + +#endif /* defined(CONFIG_PROC_FS) */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/pcmcia/au1000_pb1x00.c 2003-06-27 15:56:24.000000000 -0700 @@ -0,0 +1,411 @@ +/* + * + * Alchemy Semi Pb1x00 boards specific pcmcia routines. + * + * Copyright 2002 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include "cs_internal.h" + +#include +#include +#include + +#include +#include + +#ifdef CONFIG_MIPS_PB1000 +#include +#define PCMCIA_IRQ AU1000_GPIO_15 +#elif defined (CONFIG_MIPS_PB1500) +#include +#define PCMCIA_IRQ AU1000_GPIO_11 /* fixme */ +#elif defined (CONFIG_MIPS_PB1100) +#include +#define PCMCIA_IRQ AU1000_GPIO_11 +#endif + +static int pb1x00_pcmcia_init(struct pcmcia_init *init) +{ +#ifdef CONFIG_MIPS_PB1000 + u16 pcr; + pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST; + + au_writel(0x8000, PB1000_MDR); /* clear pcmcia interrupt */ + au_sync_delay(100); + au_writel(0x4000, PB1000_MDR); /* enable pcmcia interrupt */ + au_sync(); + + pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0); + pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1); + au_writel(pcr, PB1000_PCR); + au_sync_delay(20); + + return PCMCIA_NUM_SOCKS; + +#else /* fixme -- take care of the Pb1500 at some point */ + + u16 pcr; + pcr = au_readw(PB1100_MEM_PCMCIA) & ~0xf; /* turn off power */ + pcr &= ~(PB1100_PC_DEASSERT_RST | PB1100_PC_DRV_EN); + au_writew(pcr, PB1100_MEM_PCMCIA); + au_sync_delay(500); + return PCMCIA_NUM_SOCKS; +#endif +} + +static int pb1x00_pcmcia_shutdown(void) +{ +#ifdef CONFIG_MIPS_PB1000 + u16 pcr; + pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST; + pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0); + pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1); + au_writel(pcr, PB1000_PCR); + au_sync_delay(20); + return 0; +#else + u16 pcr; + pcr = au_readw(PB1100_MEM_PCMCIA) & ~0xf; /* turn off power */ + pcr &= ~(PB1100_PC_DEASSERT_RST | PB1100_PC_DRV_EN); + au_writew(pcr, PB1100_MEM_PCMCIA); + au_sync_delay(2); + return 0; +#endif +} + +static int +pb1x00_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state) +{ + u32 inserted0, inserted1; + u16 vs0, vs1; + +#ifdef CONFIG_MIPS_PB1000 + vs0 = vs1 = (u16)au_readl(PB1000_ACR1); + inserted0 = !(vs0 & (ACR1_SLOT_0_CD1 | ACR1_SLOT_0_CD2)); + inserted1 = !(vs1 & (ACR1_SLOT_1_CD1 | ACR1_SLOT_1_CD2)); + vs0 = (vs0 >> 4) & 0x3; + vs1 = (vs1 >> 12) & 0x3; +#else + vs0 = (au_readw(PB1100_BOARD_STATUS) >> 4) & 0x3; + inserted0 = !((au_readl(SYS_PINSTATERD) >> 9) & 0x1); /* gpio 9 */ +#endif + + state->ready = 0; + state->vs_Xv = 0; + state->vs_3v = 0; + state->detect = 0; + + if (sock == 0) { + if (inserted0) { + switch (vs0) { + case 0: + case 2: + state->vs_3v=1; + break; + case 3: /* 5V */ + break; + default: + /* return without setting 'detect' */ + printk(KERN_ERR "pb1x00 bad VS (%d)\n", + vs0); + return; + } + state->detect = 1; + } + } + else { + if (inserted1) { + switch (vs1) { + case 0: + case 2: + state->vs_3v=1; + break; + case 3: /* 5V */ + break; + default: + /* return without setting 'detect' */ + printk(KERN_ERR "pb1x00 bad VS (%d)\n", + vs1); + return; + } + state->detect = 1; + } + } + + if (state->detect) { + state->ready = 1; + } + + state->bvd1=1; + state->bvd2=1; + state->wrprot=0; + return 1; +} + + +static int pb1x00_pcmcia_get_irq_info(struct pcmcia_irq_info *info) +{ + + if(info->sock > PCMCIA_MAX_SOCK) return -1; + + /* + * Even in the case of the Pb1000, both sockets are connected + * to the same irq line. + */ + info->irq = PCMCIA_IRQ; + + return 0; +} + + +static int +pb1x00_pcmcia_configure_socket(const struct pcmcia_configure *configure) +{ + u16 pcr; + + if(configure->sock > PCMCIA_MAX_SOCK) return -1; + +#ifdef CONFIG_MIPS_PB1000 + pcr = au_readl(PB1000_PCR); + + if (configure->sock == 0) { + pcr &= ~(PCR_SLOT_0_VCC0 | PCR_SLOT_0_VCC1 | + PCR_SLOT_0_VPP0 | PCR_SLOT_0_VPP1); + } + else { + pcr &= ~(PCR_SLOT_1_VCC0 | PCR_SLOT_1_VCC1 | + PCR_SLOT_1_VPP0 | PCR_SLOT_1_VPP1); + } + + pcr &= ~PCR_SLOT_0_RST; + DEBUG(KERN_INFO "Vcc %dV Vpp %dV, pcr %x\n", + configure->vcc, configure->vpp, pcr); + switch(configure->vcc){ + case 0: /* Vcc 0 */ + switch(configure->vpp) { + case 0: + pcr |= SET_VCC_VPP(VCC_HIZ,VPP_GND, + configure->sock); + break; + case 12: + pcr |= SET_VCC_VPP(VCC_HIZ,VPP_12V, + configure->sock); + break; + case 50: + pcr |= SET_VCC_VPP(VCC_HIZ,VPP_5V, + configure->sock); + break; + case 33: + pcr |= SET_VCC_VPP(VCC_HIZ,VPP_3V, + configure->sock); + break; + default: + pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ, + configure->sock); + printk("%s: bad Vcc/Vpp (%d:%d)\n", + __FUNCTION__, + configure->vcc, + configure->vpp); + break; + } + break; + case 50: /* Vcc 5V */ + switch(configure->vpp) { + case 0: + pcr |= SET_VCC_VPP(VCC_5V,VPP_GND, + configure->sock); + break; + case 50: + pcr |= SET_VCC_VPP(VCC_5V,VPP_5V, + configure->sock); + break; + case 12: + pcr |= SET_VCC_VPP(VCC_5V,VPP_12V, + configure->sock); + break; + case 33: + pcr |= SET_VCC_VPP(VCC_5V,VPP_3V, + configure->sock); + break; + default: + pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ, + configure->sock); + printk("%s: bad Vcc/Vpp (%d:%d)\n", + __FUNCTION__, + configure->vcc, + configure->vpp); + break; + } + break; + case 33: /* Vcc 3.3V */ + switch(configure->vpp) { + case 0: + pcr |= SET_VCC_VPP(VCC_3V,VPP_GND, + configure->sock); + break; + case 50: + pcr |= SET_VCC_VPP(VCC_3V,VPP_5V, + configure->sock); + break; + case 12: + pcr |= SET_VCC_VPP(VCC_3V,VPP_12V, + configure->sock); + break; + case 33: + pcr |= SET_VCC_VPP(VCC_3V,VPP_3V, + configure->sock); + break; + default: + pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ, + configure->sock); + printk("%s: bad Vcc/Vpp (%d:%d)\n", + __FUNCTION__, + configure->vcc, + configure->vpp); + break; + } + break; + default: /* what's this ? */ + pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,configure->sock); + printk(KERN_ERR "%s: bad Vcc %d\n", + __FUNCTION__, configure->vcc); + break; + } + + if (configure->sock == 0) { + pcr &= ~(PCR_SLOT_0_RST); + if (configure->reset) + pcr |= PCR_SLOT_0_RST; + } + else { + pcr &= ~(PCR_SLOT_1_RST); + if (configure->reset) + pcr |= PCR_SLOT_1_RST; + } + au_writel(pcr, PB1000_PCR); + au_sync_delay(300); + +#else + + pcr = au_readw(PB1100_MEM_PCMCIA) & ~0xf; + + DEBUG(KERN_INFO "Vcc %dV Vpp %dV, pcr %x, reset %d\n", + configure->vcc, configure->vpp, pcr, configure->reset); + + + switch(configure->vcc){ + case 0: /* Vcc 0 */ + pcr |= SET_VCC_VPP(0,0); + break; + case 50: /* Vcc 5V */ + switch(configure->vpp) { + case 0: + pcr |= SET_VCC_VPP(2,0); + break; + case 50: + pcr |= SET_VCC_VPP(2,1); + break; + case 12: + pcr |= SET_VCC_VPP(2,2); + break; + case 33: + default: + pcr |= SET_VCC_VPP(0,0); + printk("%s: bad Vcc/Vpp (%d:%d)\n", + __FUNCTION__, + configure->vcc, + configure->vpp); + break; + } + break; + case 33: /* Vcc 3.3V */ + switch(configure->vpp) { + case 0: + pcr |= SET_VCC_VPP(1,0); + break; + case 12: + pcr |= SET_VCC_VPP(1,2); + break; + case 33: + pcr |= SET_VCC_VPP(1,1); + break; + case 50: + default: + pcr |= SET_VCC_VPP(0,0); + printk("%s: bad Vcc/Vpp (%d:%d)\n", + __FUNCTION__, + configure->vcc, + configure->vpp); + break; + } + break; + default: /* what's this ? */ + pcr |= SET_VCC_VPP(0,0); + printk(KERN_ERR "%s: bad Vcc %d\n", + __FUNCTION__, configure->vcc); + break; + } + + au_writew(pcr, PB1100_MEM_PCMCIA); + au_sync_delay(300); + + if (!configure->reset) { + pcr |= PB1100_PC_DRV_EN; + au_writew(pcr, PB1100_MEM_PCMCIA); + au_sync_delay(100); + pcr |= PB1100_PC_DEASSERT_RST; + au_writew(pcr, PB1100_MEM_PCMCIA); + au_sync_delay(100); + } + else { + pcr &= ~(PB1100_PC_DEASSERT_RST | PB1100_PC_DRV_EN); + au_writew(pcr, PB1100_MEM_PCMCIA); + au_sync_delay(100); + } +#endif + return 0; +} + +struct pcmcia_low_level pb1x00_pcmcia_ops = { + pb1x00_pcmcia_init, + pb1x00_pcmcia_shutdown, + pb1x00_pcmcia_socket_state, + pb1x00_pcmcia_get_irq_info, + pb1x00_pcmcia_configure_socket +}; --- linux-2.5.73/drivers/pcmcia/cs.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pcmcia/cs.c 2003-06-27 15:56:58.000000000 -0700 @@ -231,18 +231,6 @@ static const lookup_t service_table[] = ======================================================================*/ -static int register_callback(struct pcmcia_socket *s, void (*handler)(void *, unsigned int), void * info) -{ - int error; - - if (handler && !try_module_get(s->ss_entry->owner)) - return -ENODEV; - error = s->ss_entry->register_callback(s, handler, info); - if (!handler) - module_put(s->ss_entry->owner); - return error; -} - static int get_socket_status(struct pcmcia_socket *s, int *val) { return s->ss_entry->get_status(s, val); @@ -363,6 +351,7 @@ static int pcmcia_add_socket(struct clas wait_for_completion(&socket->thread_done); BUG_ON(!socket->thread); + pcmcia_parse_events(socket, SS_DETECT); return 0; } @@ -723,6 +712,9 @@ static int socket_insert(struct pcmcia_s { int ret; + if (!try_module_get(skt->owner)) + return CS_NO_CARD; + ret = socket_setup(skt, setup_delay); if (ret == CS_SUCCESS) { #ifdef CONFIG_CARDBUS @@ -733,8 +725,10 @@ static int socket_insert(struct pcmcia_s #endif send_event(skt, CS_EVENT_CARD_INSERTION, CS_EVENT_PRI_LOW); skt->socket.flags &= ~SS_DEBOUNCED; - } else + } else { socket_shutdown(skt); + module_put(skt->owner); + } return ret; } @@ -778,14 +772,55 @@ static int socket_resume(struct pcmcia_s send_event(skt, CS_EVENT_PM_RESUME, CS_EVENT_PRI_LOW); } skt->socket.flags &= ~SS_DEBOUNCED; - } else + } else { + unsigned int old_state = skt->state; socket_shutdown(skt); + if (old_state & SOCKET_PRESENT) + module_put(skt->owner); + } skt->state &= ~SOCKET_SUSPEND; return CS_SUCCESS; } +static void socket_remove(struct pcmcia_socket *skt) +{ + socket_shutdown(skt); + module_put(skt->owner); +} + +/* + * Process a socket card detect status change. + * + * If we don't have a card already present, delay the detect event for + * about 20ms (to be on the safe side) before reading the socket status. + * + * Some i82365-based systems send multiple SS_DETECT events during card + * insertion, and the "card present" status bit seems to bounce. This + * will probably be true with GPIO-based card detection systems after + * the product has aged. + */ +static void socket_detect_change(struct pcmcia_socket *skt) +{ + if (!(skt->state & SOCKET_SUSPEND)) { + int status; + + if (!(skt->state & SOCKET_PRESENT)) { + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(cs_to_timeout(2)); + } + + get_socket_status(skt, &status); + if ((skt->state & SOCKET_PRESENT) && + !(status & SS_DETECT)) + socket_remove(skt); + if (!(skt->state & SOCKET_PRESENT) && + (status & SS_DETECT)) + socket_insert(skt); + } +} + static int pccardd(void *__skt) { struct pcmcia_socket *skt = __skt; @@ -809,17 +844,8 @@ static int pccardd(void *__skt) if (events) { down(&skt->skt_sem); - if (events & SS_DETECT && !(skt->state & SOCKET_SUSPEND)) { - int status; - - get_socket_status(skt, &status); - if ((skt->state & SOCKET_PRESENT) && - !(status & SS_DETECT)) - socket_shutdown(skt); - if (!(skt->state & SOCKET_PRESENT) && - (status & SS_DETECT)) - socket_insert(skt); - } + if (events & SS_DETECT) + socket_detect_change(skt); if (events & SS_BATDEAD) send_event(skt, CS_EVENT_BATTERY_DEAD, CS_EVENT_PRI_LOW); if (events & SS_BATWARN) @@ -839,21 +865,17 @@ static int pccardd(void *__skt) } remove_wait_queue(&skt->thread_wait, &wait); - socket_shutdown(skt); - complete_and_exit(&skt->thread_done, 0); } -static void parse_events(void *info, u_int events) +void pcmcia_parse_events(struct pcmcia_socket *s, u_int events) { - struct pcmcia_socket *s = info; - spin_lock(&s->thread_lock); s->thread_events |= events; spin_unlock(&s->thread_lock); wake_up(&s->thread_wait); -} /* parse_events */ +} /* pcmcia_parse_events */ /*====================================================================== @@ -1114,9 +1136,6 @@ int pcmcia_deregister_client(client_hand handle->event_handler = NULL; } - if (--s->real_clients == 0) - register_callback(s, NULL, NULL); - return CS_SUCCESS; } /* deregister_client */ @@ -1531,11 +1550,6 @@ int pcmcia_register_client(client_handle if (client == NULL) return CS_OUT_OF_RESOURCE; - if (++s->real_clients == 1) { - register_callback(s, &parse_events, s); - parse_events(s, SS_DETECT); - } - *handle = client; client->state &= ~CLIENT_UNBOUND; client->Socket = s; @@ -2213,7 +2227,7 @@ int pcmcia_eject_card(client_handle_t ha if (ret != 0) break; - socket_shutdown(skt); + socket_remove(skt); ret = CS_SUCCESS; } while (0); up(&skt->skt_sem); @@ -2504,6 +2518,7 @@ EXPORT_SYMBOL(pcmcia_write_memory); EXPORT_SYMBOL(dead_socket); EXPORT_SYMBOL(CardServices); EXPORT_SYMBOL(MTDHelperEntry); +EXPORT_SYMBOL(pcmcia_parse_events); struct class pcmcia_socket_class = { .name = "pcmcia_socket", --- linux-2.5.73/drivers/pcmcia/i82092aa.h 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pcmcia/i82092aa.h 2003-06-27 15:56:58.000000000 -0700 @@ -35,7 +35,6 @@ static int i82092aa_set_io_map(struct pc static int i82092aa_set_mem_map(struct pcmcia_socket *socket, struct pccard_mem_map *mem); static int i82092aa_init(struct pcmcia_socket *socket); static int i82092aa_suspend(struct pcmcia_socket *socket); -static int i82092aa_register_callback(struct pcmcia_socket *socket, void (*handler)(void *, unsigned int), void * info); #endif --- linux-2.5.73/drivers/pcmcia/i82092.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pcmcia/i82092.c 2003-06-27 15:56:58.000000000 -0700 @@ -64,10 +64,8 @@ static struct pci_driver i82092aa_pci_dr /* the pccard structure and its functions */ static struct pccard_operations i82092aa_operations = { - .owner = THIS_MODULE, .init = i82092aa_init, .suspend = i82092aa_suspend, - .register_callback = i82092aa_register_callback, .get_status = i82092aa_get_status, .get_socket = i82092aa_get_socket, .set_socket = i82092aa_set_socket, @@ -85,12 +83,6 @@ struct socket_info { 3 = operational card */ int io_base; /* base io address of the socket */ - unsigned int pending_events; /* Pending events on this interface */ - - void (*handler)(void *info, u_int events); - /* callback to the driver of the card */ - void *info; /* to be passed to the handler */ - struct pcmcia_socket socket; struct pci_dev *dev; /* The PCI device for the socket */ }; @@ -142,6 +134,7 @@ static int __init i82092aa_pci_probe(str sockets[i].socket.map_size = 0x1000; sockets[i].socket.irq_mask = 0; sockets[i].socket.pci_irq = dev->irq; + sockets[i].socket.owner = THIS_MODULE; sockets[i].number = i; @@ -324,23 +317,6 @@ static int to_cycles(int ns) /* Interrupt handler functionality */ -static void i82092aa_bh(void *dummy) -{ - unsigned int events; - int i; - - for (i=0; i < socket_count; i++) { - events = xchg(&(sockets[i].pending_events),0); - printk("events = %x \n",events); - if (sockets[i].handler) - sockets[i].handler(sockets[i].info, events); - } -} - - -static DECLARE_WORK(i82092aa_task, i82092aa_bh, NULL); - - static irqreturn_t i82092aa_interrupt(int irq, void *dev, struct pt_regs *regs) { int i; @@ -367,8 +343,7 @@ static irqreturn_t i82092aa_interrupt(in csc = indirect_read(i,I365_CSC); /* card status change register */ - if ((csc==0) || /* no events on this socket */ - (sockets[i].handler==NULL)) /* no way to handle events */ + if (csc==0) /* no events on this socket */ continue; handled = 1; events = 0; @@ -389,8 +364,7 @@ static irqreturn_t i82092aa_interrupt(in } if (events) { - sockets[i].pending_events |= events; - schedule_work(&i82092aa_task); + pcmcia_parse_events(&sockets[i].socket, events); } active |= events; } @@ -475,16 +449,6 @@ static int i82092aa_suspend(struct pcmci return retval; } -static int i82092aa_register_callback(struct pcmcia_socket *socket, void (*handler)(void *, unsigned int), void * info) -{ - unsigned int sock = container_of(socket, struct socket_info, socket)->number; - enter("i82092aa_register_callback"); - sockets[sock].handler = handler; - sockets[sock].info = info; - leave("i82092aa_register_callback"); - return 0; -} /* i82092aa_register_callback */ - static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value) { unsigned int sock = container_of(socket, struct socket_info, socket)->number; --- linux-2.5.73/drivers/pcmcia/i82365.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pcmcia/i82365.c 2003-06-27 15:56:58.000000000 -0700 @@ -164,8 +164,6 @@ struct i82365_socket { ioaddr_t ioaddr; u_short psock; u_char cs_irq, intr; - void (*handler)(void *info, u_int events); - void *info; union { cirrus_state_t cirrus; vg46x_state_t vg46x; @@ -863,35 +861,6 @@ static void __init isa_probe(void) /*====================================================================*/ -static u_int pending_events[8]; -static spinlock_t pending_event_lock = SPIN_LOCK_UNLOCKED; - -static void pcic_bh(void *dummy) -{ - u_int events; - int i; - - for (i=0; i < sockets; i++) { - spin_lock_irq(&pending_event_lock); - events = pending_events[i]; - pending_events[i] = 0; - spin_unlock_irq(&pending_event_lock); - /* - SS_DETECT events need a small delay here. The reason for this is that - the "is there a card" electronics need time to see the card after the - "we have a card coming in" electronics have seen it. - */ - if (events & SS_DETECT) - mdelay(4); - if (socket[i].handler) - socket[i].handler(socket[i].info, events); - } -} - -static DECLARE_WORK(pcic_task, pcic_bh, NULL); - -static unsigned long last_detect_jiffies; - static irqreturn_t pcic_interrupt(int irq, void *dev, struct pt_regs *regs) { @@ -911,26 +880,12 @@ static irqreturn_t pcic_interrupt(int ir handled = 1; ISA_LOCK(i, flags); csc = i365_get(i, I365_CSC); - if ((csc == 0) || (!socket[i].handler) || - (i365_get(i, I365_IDENT) & 0x70)) { + if ((csc == 0) || (i365_get(i, I365_IDENT) & 0x70)) { ISA_UNLOCK(i, flags); continue; } events = (csc & I365_CSC_DETECT) ? SS_DETECT : 0; - - - /* Several sockets will send multiple "new card detected" - events in rapid succession. However, the rest of the pcmcia expects - only one such event. We just ignore these events by having a - timeout */ - - if (events) { - if ((jiffies - last_detect_jiffies)<(HZ/20)) - events = 0; - last_detect_jiffies = jiffies; - - } - + if (i365_get(i, I365_INTCTL) & I365_PC_IOCARD) events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0; else { @@ -941,12 +896,9 @@ static irqreturn_t pcic_interrupt(int ir ISA_UNLOCK(i, flags); DEBUG(2, "i82365: socket %d event 0x%02x\n", i, events); - if (events) { - spin_lock(&pending_event_lock); - pending_events[i] |= events; - spin_unlock(&pending_event_lock); - schedule_work(&pcic_task); - } + if (events) + pcmcia_parse_events(&socket[i].socket, events); + active |= events; } if (!active) break; @@ -968,16 +920,6 @@ static void pcic_interrupt_wrapper(u_lon /*====================================================================*/ -static int pcic_register_callback(struct pcmcia_socket *s, void (*handler)(void *, unsigned int), void * info) -{ - unsigned int sock = container_of(s, struct i82365_socket, socket)->number; - socket[sock].handler = handler; - socket[sock].info = info; - return 0; -} /* pcic_register_callback */ - -/*====================================================================*/ - static int i365_get_status(u_short sock, u_int *value) { u_int status; @@ -1400,10 +1342,8 @@ static int pcic_suspend(struct pcmcia_so } static struct pccard_operations pcic_operations = { - .owner = THIS_MODULE, .init = pcic_init, .suspend = pcic_suspend, - .register_callback = pcic_register_callback, .get_status = pcic_get_status, .get_socket = pcic_get_socket, .set_socket = pcic_set_socket, @@ -1464,6 +1404,7 @@ static int __init init_i82365(void) for (i = 0; i < sockets; i++) { socket[i].socket.dev.dev = &i82365_device.dev; socket[i].socket.ss_entry = &pcic_operations; + socket[i].socket.owner = THIS_MODULE; socket[i].number = i; ret = pcmcia_register_socket(&socket[i].socket); if (ret && i--) { --- linux-2.5.73/drivers/pcmcia/sa11xx_core.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pcmcia/sa11xx_core.c 2003-06-27 15:56:58.000000000 -0700 @@ -38,15 +38,13 @@ #include #include #include -#include #include #include -#include #include #include #include -#include #include +#include #include #include @@ -263,29 +261,27 @@ static int sa1100_pcmcia_suspend(struct return ret; } +static spinlock_t status_lock = SPIN_LOCK_UNLOCKED; -/* sa1100_pcmcia_task_handler() - * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - * Processes serviceable socket events using the "eventd" thread context. - * - * Event processing (specifically, the invocation of the Card Services event - * callback) occurs in this thread rather than in the actual interrupt - * handler due to the use of scheduling operations in the PCMCIA core. +/* sa1100_check_status() + * ^^^^^^^^^^^^^^^^^^^^^ */ -static void sa1100_pcmcia_task_handler(void *data) +static void sa1100_check_status(struct sa1100_pcmcia_socket *skt) { - struct sa1100_pcmcia_socket *skt = data; unsigned int events; DEBUG(4, "%s(): entering PCMCIA monitoring thread\n", __FUNCTION__); do { unsigned int status; + unsigned long flags; status = sa1100_pcmcia_skt_state(skt); + spin_lock_irqsave(&status_lock, flags); events = (status ^ skt->status) & skt->cs_state.csc_mask; skt->status = status; + spin_unlock_irqrestore(&status_lock, flags); DEBUG(2, "events: %s%s%s%s%s%s\n", events == 0 ? "" : "", @@ -295,8 +291,8 @@ static void sa1100_pcmcia_task_handler(v events & SS_BATWARN ? "BATWARN " : "", events & SS_STSCHG ? "STSCHG " : ""); - if (events && skt->handler != NULL) - skt->handler(skt->handler_info, events); + if (events) + pcmcia_parse_events(&skt->socket, events); } while (events); } @@ -311,7 +307,7 @@ static void sa1100_pcmcia_poll_event(uns mod_timer(&skt->poll_timer, jiffies + SA1100_PCMCIA_POLL_PERIOD); - schedule_work(&skt->work); + sa1100_check_status(skt); } @@ -330,44 +326,11 @@ static irqreturn_t sa1100_pcmcia_interru DEBUG(3, "%s(): servicing IRQ %d\n", __FUNCTION__, irq); - schedule_work(&skt->work); + sa1100_check_status(skt); return IRQ_HANDLED; } -/* sa1100_pcmcia_register_callback() - * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - * Implements the register_callback() operation for the in-kernel - * PCMCIA service (formerly SS_RegisterCallback in Card Services). If - * the function pointer `handler' is not NULL, remember the callback - * location in the state for `sock', and increment the usage counter - * for the driver module. (The callback is invoked from the interrupt - * service routine, sa1100_pcmcia_interrupt(), to notify Card Services - * of interesting events.) Otherwise, clear the callback pointer in the - * socket state and decrement the module usage count. - * - * Returns: 0 - */ -static int -sa1100_pcmcia_register_callback(struct pcmcia_socket *sock, - void (*handler)(void *, unsigned int), - void *info) -{ - struct sa1100_pcmcia_socket *skt = to_sa1100_socket(sock); - - if (handler) { - if (!try_module_get(skt->ops->owner)) - return -ENODEV; - skt->handler_info = info; - skt->handler = handler; - } else { - skt->handler = NULL; - module_put(skt->ops->owner); - } - - return 0; -} - /* sa1100_pcmcia_get_status() * ^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -655,10 +618,8 @@ static CLASS_DEVICE_ATTR(status, S_IRUGO static struct pccard_operations sa11xx_pcmcia_operations = { - .owner = THIS_MODULE, .init = sa1100_pcmcia_sock_init, .suspend = sa1100_pcmcia_suspend, - .register_callback = sa1100_pcmcia_register_callback, .get_status = sa1100_pcmcia_get_status, .get_socket = sa1100_pcmcia_get_socket, .set_socket = sa1100_pcmcia_set_socket, @@ -765,10 +726,9 @@ int sa11xx_drv_pcmcia_probe(struct devic memset(skt, 0, sizeof(*skt)); skt->socket.ss_entry = &sa11xx_pcmcia_operations; + skt->socket.owner = ops->owner; skt->socket.dev.dev = dev; - INIT_WORK(&skt->work, sa1100_pcmcia_task_handler, skt); - init_timer(&skt->poll_timer); skt->poll_timer.function = sa1100_pcmcia_poll_event; skt->poll_timer.data = (unsigned long)skt; --- linux-2.5.73/drivers/pcmcia/sa11xx_core.h 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pcmcia/sa11xx_core.h 2003-06-27 15:56:58.000000000 -0700 @@ -59,8 +59,6 @@ struct sa1100_pcmcia_socket { unsigned int status; socket_state_t cs_state; - void (*handler)(void *, unsigned int); - void *handler_info; unsigned short spd_io[MAX_IO_WIN]; unsigned short spd_mem[MAX_WIN]; @@ -75,7 +73,6 @@ struct sa1100_pcmcia_socket { unsigned int irq_state; struct timer_list poll_timer; - struct work_struct work; }; struct pcmcia_low_level { --- linux-2.5.73/drivers/pcmcia/tcic.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pcmcia/tcic.c 2003-06-27 15:56:58.000000000 -0700 @@ -116,8 +116,6 @@ static struct pccard_operations tcic_ope struct tcic_socket { u_short psock; - void (*handler)(void *info, u_int events); - void *info; u_char last_sstat; u_char id; struct pcmcia_socket socket; @@ -433,10 +431,9 @@ static int __init init_tcic(void) for (i = 0; i < sock; i++) { if ((i == ignore) || is_active(i)) continue; socket_table[sockets].psock = i; - socket_table[sockets].handler = NULL; - socket_table[sockets].info = NULL; socket_table[sockets].id = get_tcic_id(); + socket_table[sockets].socket.owner = THIS_MODULE; /* only 16-bit cards, memory windows must be size-aligned */ /* No PCI or CardBus support */ socket_table[sockets].socket.features = SS_CAP_PCCARD | SS_CAP_MEM_ALIGN; @@ -558,26 +555,6 @@ static void __exit exit_tcic(void) /*====================================================================*/ -static u_int pending_events[2]; -static spinlock_t pending_event_lock = SPIN_LOCK_UNLOCKED; - -static void tcic_bh(void *dummy) -{ - u_int events; - int i; - - for (i=0; i < sockets; i++) { - spin_lock_irq(&pending_event_lock); - events = pending_events[i]; - pending_events[i] = 0; - spin_unlock_irq(&pending_event_lock); - if (socket_table[i].handler) - socket_table[i].handler(socket_table[i].info, events); - } -} - -static DECLARE_WORK(tcic_task, tcic_bh, NULL); - static irqreturn_t tcic_interrupt(int irq, void *dev, struct pt_regs *regs) { int i, quick = 0; @@ -605,7 +582,7 @@ static irqreturn_t tcic_interrupt(int ir tcic_setb(TCIC_ICSR, TCIC_ICSR_CLEAR); quick = 1; } - if ((latch == 0) || (socket_table[psock].handler == NULL)) + if (latch == 0) continue; events = (latch & TCIC_SSTAT_CD) ? SS_DETECT : 0; events |= (latch & TCIC_SSTAT_WP) ? SS_WRPROT : 0; @@ -617,10 +594,7 @@ static irqreturn_t tcic_interrupt(int ir events |= (latch & TCIC_SSTAT_LBAT2) ? SS_BATWARN : 0; } if (events) { - spin_lock(&pending_event_lock); - pending_events[i] |= events; - spin_unlock(&pending_event_lock); - schedule_work(&tcic_task); + pcmcia_parse_events(&socket_table[i].socket, events); } } @@ -645,16 +619,6 @@ static void tcic_timer(u_long data) /*====================================================================*/ -static int tcic_register_callback(struct pcmcia_socket *sock, void (*handler)(void *, unsigned int), void * info) -{ - u_short psock = container_of(sock, struct tcic_socket, socket)->psock; - socket_table[psock].handler = handler; - socket_table[psock].info = info; - return 0; -} /* tcic_register_callback */ - -/*====================================================================*/ - static int tcic_get_status(struct pcmcia_socket *sock, u_int *value) { u_short psock = container_of(sock, struct tcic_socket, socket)->psock; @@ -915,10 +879,8 @@ static int tcic_suspend(struct pcmcia_so } static struct pccard_operations tcic_operations = { - .owner = THIS_MODULE, .init = tcic_init, .suspend = tcic_suspend, - .register_callback = tcic_register_callback, .get_status = tcic_get_status, .get_socket = tcic_get_socket, .set_socket = tcic_set_socket, --- linux-2.5.73/drivers/pcmcia/ti113x.h 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pcmcia/ti113x.h 2003-06-27 15:56:24.000000000 -0700 @@ -175,6 +175,27 @@ static int ti_override(struct yenta_sock new = reg & ~I365_INTR_ENA; if (new != reg) exca_writeb(socket, I365_INTCTL, new); + + /* + * If ISA interrupts don't work, then fall back to routing card + * interrupts to the PCI interrupt of the socket. + */ + if (!socket->socket.irq_mask) { + int irqmux, devctl; + + printk (KERN_INFO "ti113x: Routing card interrupts to PCI\n"); + + devctl = config_readb(socket, TI113X_DEVICE_CONTROL); + devctl &= ~TI113X_DCR_IMODE_MASK; + + irqmux = config_readl(socket, TI122X_IRQMUX); + irqmux = (irqmux & ~0x0f) | 0x02; /* route INTA */ + irqmux = (irqmux & ~0xf0) | 0x20; /* route INTB */ + + config_writel(socket, TI122X_IRQMUX, irqmux); + config_writeb(socket, TI113X_DEVICE_CONTROL, devctl); + } + socket->socket.ss_entry->init = ti_init; return 0; } @@ -241,6 +262,17 @@ static int ti1250_override(struct yenta_ return 0; } + +static int ti12xx_override(struct yenta_socket *socket) +{ + /* make sure that memory burst is active */ + ti_sysctl(socket) = config_readl(socket, TI113X_SYSTEM_CONTROL); + ti_sysctl(socket) |= TI122X_SCR_MRBURSTUP; + config_writel(socket, TI113X_SYSTEM_CONTROL, ti_sysctl(socket)); + + return ti113x_override(socket); +} + #endif /* CONFIG_CARDBUS */ #endif /* _LINUX_TI113X_H */ --- linux-2.5.73/drivers/pcmcia/yenta_socket.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pcmcia/yenta_socket.c 2003-06-27 15:56:58.000000000 -0700 @@ -250,7 +250,6 @@ static int yenta_set_socket(struct pcmci if (state->flags & SS_DEBOUNCED) { /* The insertion debounce period has ended. Clear any pending insertion events */ - socket->events &= ~SS_DETECT; state->flags &= ~SS_DEBOUNCED; /* SS_DEBOUNCED is oneshot */ } yenta_set_power(socket, state); @@ -420,19 +419,6 @@ static unsigned int yenta_events(struct } -static void yenta_bh(void *data) -{ - struct yenta_socket *socket = data; - unsigned int events; - - spin_lock_irq(&socket->event_lock); - events = socket->events; - socket->events = 0; - spin_unlock_irq(&socket->event_lock); - if (socket->handler) - socket->handler(socket->info, events); -} - static irqreturn_t yenta_interrupt(int irq, void *dev_id, struct pt_regs *regs) { unsigned int events; @@ -440,10 +426,7 @@ static irqreturn_t yenta_interrupt(int i events = yenta_events(socket); if (events) { - spin_lock(&socket->event_lock); - socket->events |= events; - spin_unlock(&socket->event_lock); - schedule_work(&socket->tq_task); + pcmcia_parse_events(&socket->socket, events); return IRQ_HANDLED; } return IRQ_NONE; @@ -771,21 +754,9 @@ static void yenta_close(struct pci_dev * } -static int yenta_register_callback(struct pcmcia_socket *sock, void (*handler)(void *, unsigned int), void * info) -{ - struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket); - - socket->handler = handler; - socket->info = info; - return 0; -} - - static struct pccard_operations yenta_socket_operations = { - .owner = THIS_MODULE, .init = yenta_init, .suspend = yenta_suspend, - .register_callback = yenta_register_callback, .get_status = yenta_get_status, .get_socket = yenta_get_socket, .set_socket = yenta_set_socket, @@ -807,23 +778,30 @@ struct cardbus_override_struct { unsigned short device; int (*override) (struct yenta_socket *socket); } cardbus_override[] = { - { PD(TI,1130), &ti113x_override }, { PD(TI,1031), &ti_override }, - { PD(TI,1131), &ti113x_override }, - { PD(TI,1250), &ti1250_override }, - { PD(TI,1220), &ti_override }, - { PD(TI,1221), &ti_override }, + + /* TBD: Check if these TI variants can use more + * advanced overrides instead */ { PD(TI,1210), &ti_override }, - { PD(TI,1450), &ti_override }, - { PD(TI,1225), &ti_override }, - { PD(TI,1251A), &ti_override }, { PD(TI,1211), &ti_override }, + { PD(TI,1251A), &ti_override }, { PD(TI,1251B), &ti_override }, - { PD(TI,1410), ti1250_override }, { PD(TI,1420), &ti_override }, + { PD(TI,1450), &ti_override }, { PD(TI,4410), &ti_override }, { PD(TI,4451), &ti_override }, + { PD(TI,1130), &ti113x_override }, + { PD(TI,1131), &ti113x_override }, + + { PD(TI,1220), &ti12xx_override }, + { PD(TI,1221), &ti12xx_override }, + { PD(TI,1225), &ti12xx_override }, + { PD(TI,1520), &ti12xx_override }, + + { PD(TI,1250), &ti1250_override }, + { PD(TI,1410), &ti1250_override }, + { PD(RICOH,RL5C465), &ricoh_override }, { PD(RICOH,RL5C466), &ricoh_override }, { PD(RICOH,RL5C475), &ricoh_override }, @@ -853,11 +831,11 @@ static int __devinit yenta_probe (struct socket->socket.ss_entry = ¥ta_socket_operations; socket->socket.dev.dev = &dev->dev; socket->socket.driver_data = socket; + socket->socket.owner = THIS_MODULE; /* prepare struct yenta_socket */ socket->dev = dev; pci_set_drvdata(dev, socket); - spin_lock_init(&socket->event_lock); /* * Do some basic sanity checking.. @@ -900,8 +878,6 @@ static int __devinit yenta_probe (struct /* We must finish initialization here */ - INIT_WORK(&socket->tq_task, yenta_bh, socket); - if (!socket->cb_irq || request_irq(socket->cb_irq, yenta_interrupt, SA_SHIRQ, socket->dev->dev.name, socket)) { /* No IRQ or request_irq failed. Poll */ socket->cb_irq = 0; /* But zero is a valid IRQ number. */ --- linux-2.5.73/drivers/pcmcia/yenta_socket.h 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pcmcia/yenta_socket.h 2003-06-27 15:56:58.000000000 -0700 @@ -99,11 +99,6 @@ struct yenta_socket { struct pci_dev *dev; int cb_irq, io_irq; void *base; - void (*handler)(void *, unsigned int); - void *info; - spinlock_t event_lock; - unsigned int events; - struct work_struct tq_task; struct timer_list poll_timer; struct pcmcia_socket socket; --- linux-2.5.73/drivers/pnp/interface.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pnp/interface.c 2003-06-27 15:56:24.000000000 -0700 @@ -323,14 +323,14 @@ pnp_set_current_resources(struct device if (!strnicmp(buf,"auto",4)) { if (dev->active) goto done; - pnp_init_resources(&dev->res); + pnp_init_resource_table(&dev->res); retval = pnp_auto_config_dev(dev); goto done; } if (!strnicmp(buf,"clear",5)) { if (dev->active) goto done; - pnp_init_resources(&dev->res); + pnp_init_resource_table(&dev->res); goto done; } if (!strnicmp(buf,"get",3)) { @@ -345,7 +345,7 @@ pnp_set_current_resources(struct device if (dev->active) goto done; buf += 3; - pnp_init_resources(&dev->res); + pnp_init_resource_table(&dev->res); down(&pnp_res_mutex); while (1) { while (isspace(*buf)) --- linux-2.5.73/drivers/pnp/isapnp/core.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pnp/isapnp/core.c 2003-06-27 15:56:24.000000000 -0700 @@ -458,7 +458,7 @@ static struct pnp_dev * __init isapnp_pa dev->capabilities |= PNP_READ; dev->capabilities |= PNP_WRITE; dev->capabilities |= PNP_DISABLE; - pnp_init_resources(&dev->res); + pnp_init_resource_table(&dev->res); return dev; } @@ -1020,7 +1020,7 @@ static int isapnp_read_resources(struct static int isapnp_get_resources(struct pnp_dev *dev, struct pnp_resource_table * res) { int ret; - pnp_init_resources(res); + pnp_init_resource_table(res); isapnp_cfg_begin(dev->card->number, dev->number); ret = isapnp_read_resources(dev, res); isapnp_cfg_end(); --- linux-2.5.73/drivers/pnp/manager.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pnp/manager.c 2003-06-27 15:56:24.000000000 -0700 @@ -190,10 +190,9 @@ static int pnp_assign_dma(struct pnp_dev * @table: pointer to the desired resource table * */ -void pnp_init_resources(struct pnp_resource_table *table) +void pnp_init_resource_table(struct pnp_resource_table *table) { int idx; - down(&pnp_res_mutex); for (idx = 0; idx < PNP_MAX_IRQ; idx++) { table->irq_resource[idx].name = NULL; table->irq_resource[idx].start = -1; @@ -218,7 +217,6 @@ void pnp_init_resources(struct pnp_resou table->mem_resource[idx].end = 0; table->mem_resource[idx].flags = IORESOURCE_AUTO; } - up(&pnp_res_mutex); } /** @@ -226,7 +224,7 @@ void pnp_init_resources(struct pnp_resou * @res - the resources to clean * */ -static void pnp_clean_resources(struct pnp_resource_table * res) +static void pnp_clean_resource_table(struct pnp_resource_table * res) { int idx; for (idx = 0; idx < PNP_MAX_IRQ; idx++) { @@ -278,7 +276,7 @@ int pnp_assign_resources(struct pnp_dev return -ENODEV; down(&pnp_res_mutex); - pnp_clean_resources(&dev->res); /* start with a fresh slate */ + pnp_clean_resource_table(&dev->res); /* start with a fresh slate */ if (dev->independent) { port = dev->independent->port; mem = dev->independent->mem; @@ -351,7 +349,7 @@ int pnp_assign_resources(struct pnp_dev return 1; fail: - pnp_clean_resources(&dev->res); + pnp_clean_resource_table(&dev->res); up(&pnp_res_mutex); return 0; } @@ -510,7 +508,7 @@ int pnp_disable_dev(struct pnp_dev *dev) /* release the resources so that other devices can use them */ down(&pnp_res_mutex); - pnp_clean_resources(&dev->res); + pnp_clean_resource_table(&dev->res); up(&pnp_res_mutex); return 1; @@ -539,4 +537,4 @@ EXPORT_SYMBOL(pnp_auto_config_dev); EXPORT_SYMBOL(pnp_activate_dev); EXPORT_SYMBOL(pnp_disable_dev); EXPORT_SYMBOL(pnp_resource_change); -EXPORT_SYMBOL(pnp_init_resources); +EXPORT_SYMBOL(pnp_init_resource_table); --- linux-2.5.73/drivers/pnp/pnpbios/core.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pnp/pnpbios/core.c 2003-06-27 15:56:24.000000000 -0700 @@ -937,7 +937,7 @@ static int insert_device(struct pnp_dev /* clear out the damaged flags */ if (!dev->active) - pnp_init_resources(&dev->res); + pnp_init_resource_table(&dev->res); pnp_add_device(dev); pnpbios_interface_attach_device(node); --- linux-2.5.73/drivers/pnp/resource.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/pnp/resource.c 2003-06-27 15:56:24.000000000 -0700 @@ -85,7 +85,6 @@ struct pnp_option * pnp_register_depende int pnp_register_irq_resource(struct pnp_option *option, struct pnp_irq *data) { - int i; struct pnp_irq *ptr; if (!option) return -EINVAL; @@ -101,9 +100,13 @@ int pnp_register_irq_resource(struct pnp option->irq = data; #ifdef CONFIG_PCI - for (i=0; i<16; i++) - if (data->map & (1<map & (1< * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 2000, 2001 * - * $Revision: 1.24 $ + * $Revision: 1.25 $ */ #include @@ -221,13 +221,6 @@ dasd_3990_erp_cleanup(struct dasd_ccw_re * Block the given device request queue to prevent from further * processing until the started timer has expired or an related * interrupt was received. - * - * PARAMETER - * erp request to be blocked - * expires time to wait until restart (in jiffies) - * - * RETURN VALUES - * void */ static void dasd_3990_erp_block_queue(struct dasd_ccw_req * erp, int expires) @@ -238,7 +231,9 @@ dasd_3990_erp_block_queue(struct dasd_cc DEV_MESSAGE(KERN_INFO, device, "blocking request queue for %is", expires); - erp->status = DASD_CQR_PENDING; + device->stopped |= DASD_STOPPED_PENDING; + erp->status = DASD_CQR_QUEUED; + dasd_set_timer(device, expires); } @@ -453,9 +448,11 @@ dasd_3990_erp_action_4(struct dasd_ccw_r if (sense[25] == 0x1D) { /* state change pending */ - DEV_MESSAGE(KERN_INFO, device, "%s", - "waiting for state change pending " "int"); - + DEV_MESSAGE(KERN_INFO, device, + "waiting for state change pending " + "interrupt, %d retries left", + erp->retries); + dasd_3990_erp_block_queue(erp, 30*HZ); } else { --- linux-2.5.73/drivers/s390/block/dasd.c 2003-06-14 12:18:09.000000000 -0700 +++ 25/drivers/s390/block/dasd.c 2003-06-27 15:56:24.000000000 -0700 @@ -7,7 +7,7 @@ * Bugreports.to..: * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999-2001 * - * $Revision: 1.99 $ + * $Revision: 1.101 $ */ #include @@ -32,7 +32,7 @@ /* * SECTION: Constant definitions to be used within this file */ -#define DASD_CHANQ_MAX_SIZE 5 +#define DASD_CHANQ_MAX_SIZE 4 /* * SECTION: exported variables of dasd.c @@ -803,24 +803,18 @@ dasd_start_IO(struct dasd_ccw_req * cqr) * 2) delayed start of request where start_IO failed with -EBUSY * 3) timeout for missing state change interrupts * The head of the ccw queue will have status DASD_CQR_IN_IO for 1), - * DASD_CQR_QUEUED for 2) and DASD_CQR_PENDING for 3). + * DASD_CQR_QUEUED for 2) and 3). */ static void dasd_timeout_device(unsigned long ptr) { unsigned long flags; struct dasd_device *device; - struct dasd_ccw_req *cqr; device = (struct dasd_device *) ptr; spin_lock_irqsave(get_ccwdev_lock(device->cdev), flags); /* re-activate first request in queue */ - if (!list_empty(&device->ccw_queue)) { - cqr = list_entry(device->ccw_queue.next, - struct dasd_ccw_req, list); - if (cqr->status == DASD_CQR_PENDING) - cqr->status = DASD_CQR_QUEUED; - } + device->stopped &= ~DASD_STOPPED_PENDING; spin_unlock_irqrestore(get_ccwdev_lock(device->cdev), flags); dasd_schedule_bh(device); } @@ -861,10 +855,6 @@ dasd_clear_timer(struct dasd_device *dev /* * Handles the state change pending interrupt. - * Search for the device related request queue and check if the first - * cqr in queue in in status 'DASD_CQR_PENDING'. - * If so the status is set to 'DASD_CQR_QUEUED' to reactivate - * the device. */ static void do_state_change_pending(void *data) @@ -874,29 +864,12 @@ do_state_change_pending(void *data) struct dasd_device *device; } *p; struct dasd_device *device; - struct dasd_ccw_req *cqr; p = data; device = p->device; DBF_EVENT(DBF_NOTICE, "State change Interrupt for bus_id %s", device->cdev->dev.bus_id); - - spin_lock_irq(get_ccwdev_lock(device->cdev)); - /* re-activate first request in queue */ - if (!list_empty(&device->ccw_queue)) { - cqr = list_entry(device->ccw_queue.next, - struct dasd_ccw_req, list); - if (cqr == NULL) { - MESSAGE (KERN_DEBUG, - "got state change pending interrupt on" - "an idle device: bus_id %s", - device->cdev->dev.bus_id); - return; - } - if (cqr->status == DASD_CQR_PENDING) - cqr->status = DASD_CQR_QUEUED; - } - spin_unlock_irq(get_ccwdev_lock(device->cdev)); + device->stopped &= ~DASD_STOPPED_PENDING; dasd_schedule_bh(device); dasd_put_device(device); kfree(p); @@ -1036,7 +1009,8 @@ dasd_int_handler(struct ccw_device *cdev if (cqr->list.next != &device->ccw_queue) { next = list_entry(cqr->list.next, struct dasd_ccw_req, list); - if (next->status == DASD_CQR_QUEUED) { + if ((next->status == DASD_CQR_QUEUED) && + (!device->stopped)) { if (device->discipline->start_IO(next) == 0) expires = next->expires; else @@ -1264,7 +1238,8 @@ __dasd_start_head(struct dasd_device * d if (list_empty(&device->ccw_queue)) return; cqr = list_entry(device->ccw_queue.next, struct dasd_ccw_req, list); - if (cqr->status == DASD_CQR_QUEUED) { + if ((cqr->status == DASD_CQR_QUEUED) && + (!device->stopped)) { /* try to start the first I/O that can be started */ rc = device->discipline->start_IO(cqr); if (rc == 0) --- linux-2.5.73/drivers/s390/block/dasd_eckd.c 2003-06-14 12:17:56.000000000 -0700 +++ 25/drivers/s390/block/dasd_eckd.c 2003-06-27 15:56:24.000000000 -0700 @@ -7,7 +7,7 @@ * Bugreports.to..: * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999,2000 * - * $Revision: 1.42 $ + * $Revision: 1.46 $ */ #include @@ -80,7 +80,13 @@ static struct ccw_driver dasd_eckd_drive static int dasd_eckd_probe (struct ccw_device *cdev) { - return dasd_generic_probe (cdev, &dasd_eckd_discipline); + int ret; + + ret = dasd_generic_probe (cdev, &dasd_eckd_discipline); + if (ret) + return ret; + ccw_device_set_options(cdev, CCWDEV_DO_PATHGROUP); + return 0; } static int @@ -204,7 +210,7 @@ check_XRC (struct ccw1 *de_ccw, data->ep_sys_time = get_clock (); de_ccw->count = sizeof (struct DE_eckd_data); - de_ccw->flags = CCW_FLAG_SLI; + de_ccw->flags |= CCW_FLAG_SLI; } return; @@ -281,19 +287,11 @@ define_extent(struct ccw1 * ccw, struct /* check for sequential prestage - enhance cylinder range */ if (data->attributes.operation == DASD_SEQ_PRESTAGE || data->attributes.operation == DASD_SEQ_ACCESS) { - - if (end.cyl + private->attrib.nr_cyl < geo.cyl) { + + if (end.cyl + private->attrib.nr_cyl < geo.cyl) end.cyl += private->attrib.nr_cyl; - DBF_DEV_EVENT(DBF_NOTICE, device, - "Enhanced DE Cylinder from %x to %x", - (totrk / geo.head), end.cyl); - } else { + else end.cyl = (geo.cyl - 1); - DBF_DEV_EVENT(DBF_NOTICE, device, - "Enhanced DE Cylinder from %x to " - "End of device %x", - (totrk / geo.head), end.cyl); - } } data->beg_ext.cyl = beg.cyl; @@ -512,12 +510,6 @@ dasd_eckd_check_characteristics(struct d private->rdc_data.cu_type, private->rdc_data.cu_model.model); return 0; - - /* get characteristis via diag to determine the kind of - * minidisk under VM needed beacause XRC is not support - * by VM (jet). Can be removed as soon as VM supports XRC - * FIXME: TBD ??? HUM - */ } static struct dasd_ccw_req * @@ -1130,13 +1122,16 @@ dasd_eckd_release(struct block_device *b return -ENODEV; cqr = dasd_smalloc_request(dasd_eckd_discipline.name, - 1, 0, device); + 1, 32, device); if (cqr == NULL) { MESSAGE(KERN_WARNING, "%s", "No memory to allocate initialization request"); return -ENOMEM; } cqr->cpaddr->cmd_code = DASD_ECKD_CCW_RELEASE; + cqr->cpaddr->flags |= CCW_FLAG_SLI; + cqr->cpaddr->count = 32; + cqr->cpaddr->cda = (__u32)(addr_t) cqr->data; cqr->device = device; cqr->retries = 0; cqr->expires = 10 * HZ; @@ -1145,14 +1140,14 @@ dasd_eckd_release(struct block_device *b rc = dasd_sleep_on_immediatly(cqr); - dasd_kfree_request(cqr, cqr->device); + dasd_sfree_request(cqr, cqr->device); return rc; } /* * Reserve device ioctl. * Options are set to 'synchronous wait for interrupt' and - * 'timeout the request'. This leads to an terminate IO if + * 'timeout the request'. This leads to a terminate IO if * the interrupt is outstanding for a certain time. */ static int @@ -1170,14 +1165,16 @@ dasd_eckd_reserve(struct block_device *b return -ENODEV; cqr = dasd_smalloc_request(dasd_eckd_discipline.name, - 1, 0, device); - + 1, 32, device); if (cqr == NULL) { MESSAGE(KERN_WARNING, "%s", "No memory to allocate initialization request"); return -ENOMEM; } cqr->cpaddr->cmd_code = DASD_ECKD_CCW_RESERVE; + cqr->cpaddr->flags |= CCW_FLAG_SLI; + cqr->cpaddr->count = 32; + cqr->cpaddr->cda = (__u32)(addr_t) cqr->data; cqr->device = device; cqr->retries = 0; cqr->expires = 10 * HZ; @@ -1186,11 +1183,7 @@ dasd_eckd_reserve(struct block_device *b rc = dasd_sleep_on_immediatly(cqr); - if (rc == -EIO) { - /* Request got an error or has been timed out. */ - dasd_eckd_release(bdev, no, args); - } - dasd_kfree_request(cqr, cqr->device); + dasd_sfree_request(cqr, cqr->device); return rc; } @@ -1214,13 +1207,16 @@ dasd_eckd_steal_lock(struct block_device return -ENODEV; cqr = dasd_smalloc_request(dasd_eckd_discipline.name, - 1, 0, device); + 1, 32, device); if (cqr == NULL) { MESSAGE(KERN_WARNING, "%s", "No memory to allocate initialization request"); return -ENOMEM; } cqr->cpaddr->cmd_code = DASD_ECKD_CCW_SLCK; + cqr->cpaddr->flags |= CCW_FLAG_SLI; + cqr->cpaddr->count = 32; + cqr->cpaddr->cda = (__u32)(addr_t) cqr->data; cqr->device = device; cqr->retries = 0; cqr->expires = 10 * HZ; @@ -1229,11 +1225,7 @@ dasd_eckd_steal_lock(struct block_device rc = dasd_sleep_on_immediatly(cqr); - if (rc == -EIO) { - /* Request got an error or has been timed out. */ - dasd_eckd_release(bdev, no, args); - } - dasd_kfree_request(cqr, cqr->device); + dasd_sfree_request(cqr, cqr->device); return rc; } @@ -1330,17 +1322,13 @@ dasd_eckd_set_attrib(struct block_device private = (struct dasd_eckd_private *) device->private; - DBF_DEV_EVENT(DBF_ERR, device, - "cache operation mode got " - "%x (%i cylinder prestage)", - attrib.operation, attrib.nr_cyl); - private->attrib = attrib; DBF_DEV_EVENT(DBF_ERR, device, "cache operation mode set to " "%x (%i cylinder prestage)", private->attrib.operation, private->attrib.nr_cyl); + return 0; } --- linux-2.5.73/drivers/s390/block/dasd_erp.c 2003-06-14 12:17:58.000000000 -0700 +++ 25/drivers/s390/block/dasd_erp.c 2003-06-27 15:56:24.000000000 -0700 @@ -7,7 +7,7 @@ * Bugreports.to..: * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999-2001 * - * $Revision: 1.9 $ + * $Revision: 1.10 $ */ #include @@ -86,48 +86,31 @@ dasd_free_erp_request(struct dasd_ccw_re atomic_dec(&device->ref_count); } + /* - * DESCRIPTION - * sets up the default-ERP struct dasd_ccw_req, namely one, which performs - * a TIC to the original channel program with a retry counter of 16 - * - * PARAMETER - * cqr failed CQR - * - * RETURN VALUES - * erp CQR performing the ERP + * dasd_default_erp_action just retries the current cqr */ struct dasd_ccw_req * dasd_default_erp_action(struct dasd_ccw_req * cqr) { struct dasd_device *device; - struct dasd_ccw_req *erp; - MESSAGE(KERN_DEBUG, "%s", "Default ERP called... "); device = cqr->device; - erp = dasd_alloc_erp_request((char *) &cqr->magic, 1, 0, device); - if (IS_ERR(erp)) { - DEV_MESSAGE(KERN_ERR, device, "%s", - "Unable to allocate request for default ERP"); - cqr->status = DASD_CQR_FAILED; - cqr->stopclk = get_clock(); - return cqr; - } - - erp->cpaddr->cmd_code = CCW_CMD_TIC; - erp->cpaddr->cda = (__u32) (addr_t) cqr->cpaddr; - erp->function = dasd_default_erp_action; - erp->refers = cqr; - erp->device = device; - erp->magic = cqr->magic; - erp->retries = 16; - erp->status = DASD_CQR_FILLED; - - list_add(&erp->list, &device->ccw_queue); - erp->status = DASD_CQR_QUEUED; - - return erp; + /* just retry - there is nothing to save ... I got no sense data.... */ + if (cqr->retries > 0) { + DEV_MESSAGE (KERN_DEBUG, device, + "default ERP called (%i retries left)", + cqr->retries); + cqr->status = DASD_CQR_QUEUED; + } else { + DEV_MESSAGE (KERN_WARNING, device, "%s", + "default ERP called (NO retry left)"); + + cqr->status = DASD_CQR_FAILED; + cqr->stopclk = get_clock (); + } + return cqr; } /* end dasd_default_erp_action */ /* --- linux-2.5.73/drivers/s390/block/dasd_fba.c 2003-06-14 12:18:24.000000000 -0700 +++ 25/drivers/s390/block/dasd_fba.c 2003-06-27 15:56:24.000000000 -0700 @@ -4,7 +4,7 @@ * Bugreports.to..: * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999,2000 * - * $Revision: 1.29 $ + * $Revision: 1.30 $ */ #include @@ -57,7 +57,13 @@ static struct ccw_driver dasd_fba_driver static int dasd_fba_probe(struct ccw_device *cdev) { - return dasd_generic_probe (cdev, &dasd_fba_discipline); + int ret; + + ret = dasd_generic_probe (cdev, &dasd_fba_discipline); + if (ret) + return ret; + ccw_device_set_options(cdev, CCWDEV_DO_PATHGROUP); + return 0; } static int --- linux-2.5.73/drivers/s390/block/dasd_int.h 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/s390/block/dasd_int.h 2003-06-27 15:56:44.000000000 -0700 @@ -6,7 +6,7 @@ * Bugreports.to..: * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999,2000 * - * $Revision: 1.40 $ + * $Revision: 1.42 $ */ #ifndef DASD_INT_H @@ -14,7 +14,8 @@ #ifdef __KERNEL__ -#define DASD_PER_MAJOR ( 1U<<(MINORBITS-DASD_PARTN_BITS)) +#define DASD_MINORBITS 8 +#define DASD_PER_MAJOR ( 1U<<(DASD_MINORBITS-DASD_PARTN_BITS)) #define DASD_PARTN_MASK ((1 << DASD_PARTN_BITS) - 1) /* @@ -188,7 +189,6 @@ struct dasd_ccw_req { #define DASD_CQR_DONE 0x03 /* request is completed successfully */ #define DASD_CQR_ERROR 0x04 /* request is completed with error */ #define DASD_CQR_FAILED 0x05 /* request is finally failed */ -#define DASD_CQR_PENDING 0x06 /* request is waiting for interrupt - ERP only */ /* Signature for error recovery functions. */ typedef struct dasd_ccw_req *(*dasd_erp_fn_t) (struct dasd_ccw_req *); @@ -279,6 +279,7 @@ struct dasd_device { /* Device state and target state. */ int state, target; + int stopped; /* device (ccw_device_start) was stopped */ /* Open and reference count. */ atomic_t ref_count; @@ -306,6 +307,12 @@ struct dasd_device { #endif }; +/* reasons why device (ccw_device_start) was stopped */ +#define DASD_STOPPED_NOT_ACC 1 /* not accessible */ +#define DASD_STOPPED_QUIESCE 2 /* Quiesced */ +#define DASD_STOPPED_PENDING 4 /* long busy */ + + void dasd_put_device_wake(struct dasd_device *); /* --- linux-2.5.73/drivers/s390/block/dasd_ioctl.c 2003-06-14 12:18:23.000000000 -0700 +++ 25/drivers/s390/block/dasd_ioctl.c 2003-06-27 15:56:24.000000000 -0700 @@ -169,6 +169,58 @@ dasd_ioctl_disable(struct block_device * } /* + * Quiesce device. + */ +static int +dasd_ioctl_quiesce(struct block_device *bdev, int no, long args) +{ + struct dasd_device *device; + unsigned long flags; + + if (!capable (CAP_SYS_ADMIN)) + return -EACCES; + + device = bdev->bd_disk->private_data; + if (device == NULL) + return -ENODEV; + + DEV_MESSAGE (KERN_DEBUG, device, "%s", + "Quiesce IO on device"); + spin_lock_irqsave(get_ccwdev_lock(device->cdev), flags); + device->stopped |= DASD_STOPPED_QUIESCE; + spin_unlock_irqrestore(get_ccwdev_lock(device->cdev), flags); + return 0; +} + + +/* + * Quiesce device. + */ +static int +dasd_ioctl_resume(struct block_device *bdev, int no, long args) +{ + struct dasd_device *device; + unsigned long flags; + + if (!capable (CAP_SYS_ADMIN)) + return -EACCES; + + device = bdev->bd_disk->private_data; + if (device == NULL) + return -ENODEV; + + DEV_MESSAGE (KERN_DEBUG, device, "%s", + "resume IO on device"); + + spin_lock_irqsave(get_ccwdev_lock(device->cdev), flags); + device->stopped &= ~DASD_STOPPED_QUIESCE; + spin_unlock_irqrestore(get_ccwdev_lock(device->cdev), flags); + + dasd_schedule_bh (device); + return 0; +} + +/* * performs formatting of _device_ according to _fdata_ * Note: The discipline's format_function is assumed to deliver formatting * commands to format a single unit of the device. In terms of the ECKD @@ -438,6 +490,8 @@ static struct { int no; dasd_ioctl_fn_t { { BIODASDDISABLE, dasd_ioctl_disable }, { BIODASDENABLE, dasd_ioctl_enable }, + { BIODASDQUIESCE, dasd_ioctl_quiesce }, + { BIODASDRESUME, dasd_ioctl_resume }, { BIODASDFMT, dasd_ioctl_format }, { BIODASDINFO, dasd_ioctl_information }, { BIODASDINFO2, dasd_ioctl_information }, --- linux-2.5.73/drivers/s390/block/xpram.c 2003-06-14 12:18:29.000000000 -0700 +++ 25/drivers/s390/block/xpram.c 2003-06-27 15:56:24.000000000 -0700 @@ -487,7 +487,7 @@ static void __exit xpram_exit(void) unregister_blkdev(XPRAM_MAJOR, XPRAM_NAME); devfs_remove("slram"); sys_device_unregister(&xpram_sys_device); - sysdev_class_unregister(&xpram_sys_class); + sysdev_class_unregister(&xpram_sysclass); } static int __init xpram_init(void) @@ -511,7 +511,7 @@ static int __init xpram_init(void) rc = sys_device_register(&xpram_sys_device); if (rc) { - sysdev_class_unregister(&xpram_syclass); + sysdev_class_unregister(&xpram_sysclass); return rc; } rc = xpram_setup_blkdev(); --- linux-2.5.73/drivers/s390/char/con3215.c 2003-06-14 12:18:25.000000000 -0700 +++ 25/drivers/s390/char/con3215.c 2003-06-27 15:56:24.000000000 -0700 @@ -1215,6 +1215,7 @@ tty3215_init(void) return ret; } tty3215_driver = driver; + return 0; } static void __exit --- linux-2.5.73/drivers/s390/char/tape_core.c 2003-06-14 12:18:04.000000000 -0700 +++ 25/drivers/s390/char/tape_core.c 2003-06-27 15:56:24.000000000 -0700 @@ -372,6 +372,8 @@ tape_generic_probe(struct ccw_device *cd device->cdev = cdev; cdev->handler = tape_do_irq; + ccw_device_set_options(cdev, CCWDEV_DO_PATHGROUP); + return 0; } @@ -903,7 +905,7 @@ tape_init (void) { tape_dbf_area = debug_register ( "tape", 1, 2, 3*sizeof(long)); debug_register_view(tape_dbf_area, &debug_sprintf_view); - DBF_EVENT(3, "tape init: ($Revision: 1.25 $)\n"); + DBF_EVENT(3, "tape init: ($Revision: 1.26 $)\n"); tape_proc_init(); tapechar_init (); tapeblock_init (); @@ -928,7 +930,7 @@ tape_exit(void) MODULE_AUTHOR("(C) 2001 IBM Deutschland Entwicklung GmbH by Carsten Otte and " "Michael Holzheu (cotte@de.ibm.com,holzheu@de.ibm.com)"); MODULE_DESCRIPTION("Linux on zSeries channel attached " - "tape device driver ($Revision: 1.25 $)"); + "tape device driver ($Revision: 1.26 $)"); module_init(tape_init); module_exit(tape_exit); --- linux-2.5.73/drivers/s390/cio/ccwgroup.c 2003-06-14 12:18:22.000000000 -0700 +++ 25/drivers/s390/cio/ccwgroup.c 2003-06-27 15:56:24.000000000 -0700 @@ -1,7 +1,7 @@ /* * drivers/s390/cio/ccwgroup.c * bus driver for ccwgroup - * $Revision: 1.6 $ + * $Revision: 1.7 $ * * Copyright (C) 2002 IBM Deutschland Entwicklung GmbH, * IBM Corporation @@ -196,10 +196,12 @@ ccwgroup_online_store (struct device *de value = simple_strtoul(buf, 0, 0); - if (value) + if (value == 1) ccwgroup_set_online(gdev); - else + else if (value == 0) ccwgroup_set_offline(gdev); + else + return -EINVAL; return count; } @@ -211,7 +213,7 @@ ccwgroup_online_show (struct device *dev online = (to_ccwgroupdev(dev)->state == CCWGROUP_ONLINE); - return sprintf(buf, online ? "1\n" : "0\n"); + return sprintf(buf, online ? "yes\n" : "no\n"); } static DEVICE_ATTR(online, 0644, ccwgroup_online_show, ccwgroup_online_store); --- linux-2.5.73/drivers/s390/cio/chsc.c 2003-06-14 12:18:22.000000000 -0700 +++ 25/drivers/s390/cio/chsc.c 2003-06-27 15:56:24.000000000 -0700 @@ -1,7 +1,7 @@ /* * drivers/s390/cio/chsc.c * S/390 common I/O routines -- channel subsystem call - * $Revision: 1.69 $ + * $Revision: 1.73 $ * * Copyright (C) 1999-2002 IBM Deutschland Entwicklung GmbH, * IBM Corporation @@ -322,10 +322,6 @@ s390_set_chpid_offline( __u8 chpid) sprintf(dbf_txt, "chpr%x", chpid); CIO_TRACE_EVENT(2, dbf_txt); - /* - * TODO: the chpid may be not the chpid with the link incident, - * but the chpid the report came in through. How to handle??? - */ clear_bit(chpid, chpids); if (!test_and_clear_bit(chpid, chpids_known)) return; /* we didn't know the chpid anyway */ @@ -469,9 +465,40 @@ s390_process_res_acc (u8 chpid, __u16 fl free_page((unsigned long)page); } +static int +__get_chpid_from_lir(void *data) +{ + struct lir { + u8 iq; + u8 ic; + u16 sci; + /* incident-node descriptor */ + u32 indesc[28]; + /* attached-node descriptor */ + u32 andesc[28]; + /* incident-specific information */ + u32 isinfo[28]; + } *lir; + + lir = (struct lir*) data; + if (!(lir->iq&0x80)) + /* NULL link incident record */ + return -EINVAL; + if (!(lir->indesc[0]&0xc0000000)) + /* node descriptor not valid */ + return -EINVAL; + if (!(lir->indesc[0]&0x10000000)) + /* don't handle device-type nodes - FIXME */ + return -EINVAL; + /* Byte 3 contains the chpid. Could also be CTCA, but we don't care */ + + return (u16) (lir->indesc[0]&0x000000ff); +} + static void do_process_crw(void *ignore) { + int chpid; struct { struct chsc_header request; u32 reserved1; @@ -487,10 +514,8 @@ do_process_crw(void *ignore) u16 rsid; /* reporting source id */ u32 reserved5; u32 reserved6; - u32 ccdf; /* content-code dependent field */ - u32 reserved7; - u32 reserved8; - u32 reserved9; + u32 ccdf[96]; /* content-code dependent field */ + /* ccdf has to be big enough for a link-incident record */ } *sei_area; /* @@ -560,9 +585,14 @@ do_process_crw(void *ignore) case 1: /* link incident*/ CIO_CRW_EVENT(4, "chsc_process_crw: " "channel subsystem reports link incident," - " source is chpid %x\n", sei_area->rsid); - - s390_set_chpid_offline(sei_area->rsid); + " reporting source is chpid %x\n", + sei_area->rsid); + chpid = __get_chpid_from_lir(sei_area->ccdf); + if (chpid < 0) + CIO_CRW_EVENT(4, "%s: Invalid LIR, skipping\n", + __FUNCTION__); + else + s390_set_chpid_offline(chpid); break; case 2: /* i/o resource accessibiliy */ --- linux-2.5.73/drivers/s390/cio/css.h 2003-06-14 12:18:52.000000000 -0700 +++ 25/drivers/s390/cio/css.h 2003-06-27 15:56:24.000000000 -0700 @@ -72,9 +72,9 @@ struct ccw_device_private { struct { unsigned int fast:1; /* post with "channel end" */ unsigned int repall:1; /* report every interrupt status */ + unsigned int pgroup:1; /* do path grouping */ } __attribute__ ((packed)) options; struct { - unsigned int pgid_supp:1; /* "path group ID" supported */ unsigned int pgid_single:1; /* use single path for Set PGID */ unsigned int esid:1; /* Ext. SenseID supported by HW */ unsigned int dosense:1; /* delayed SENSE required */ --- linux-2.5.73/drivers/s390/cio/device.c 2003-06-14 12:18:29.000000000 -0700 +++ 25/drivers/s390/cio/device.c 2003-06-27 15:56:24.000000000 -0700 @@ -1,7 +1,7 @@ /* * drivers/s390/cio/device.c * bus driver for ccw devices - * $Revision: 1.54 $ + * $Revision: 1.57 $ * * Copyright (C) 2002 IBM Deutschland Entwicklung GmbH, * IBM Corporation @@ -298,20 +298,19 @@ static ssize_t online_store (struct device *dev, const char *buf, size_t count) { struct ccw_device *cdev = to_ccwdev(dev); - unsigned int value; + int i; + char *tmp; if (!cdev->drv) return count; - sscanf(buf, "%u", &value); - - if (value) { - if (cdev->drv->set_online) - ccw_device_set_online(cdev); - } else { - if (cdev->drv->set_offline) - ccw_device_set_offline(cdev); - } + i = simple_strtoul(buf, &tmp, 16); + if (i == 0 && cdev->drv->set_online) + ccw_device_set_online(cdev); + else if (i == 1 && cdev->drv->set_offline) + ccw_device_set_offline(cdev); + else + return -EINVAL; return count; } @@ -405,11 +404,14 @@ device_add_files (struct device *dev) * This allows to trigger an unconditional reserve ccw to eckd dasds * (if the device is something else, there should be no problems more than * a command reject; we don't have any means of finding out the device's - * type if it was boxed at ipl/attach). + * type if it was boxed at ipl/attach for older devices and under VM). */ void -ccw_device_add_stlck(struct ccw_device *cdev) +ccw_device_add_stlck(void *data) { + struct ccw_device *cdev; + + cdev = (struct ccw_device *)data; device_create_file(&cdev->dev, &dev_attr_steal_lock); } @@ -470,6 +472,8 @@ io_subchannel_register(void *data) if (ret) printk(KERN_WARNING "%s: could not add attributes to %04x\n", __func__, sch->irq); + if (cdev->private->state == DEV_STATE_BOXED) + device_create_file(&cdev->dev, &dev_attr_steal_lock); out: put_device(&sch->dev); } @@ -493,6 +497,8 @@ io_subchannel_recog_done(struct ccw_devi if (cdev->dev.release) cdev->dev.release(&cdev->dev); break; + case DEV_STATE_BOXED: + /* Device did not respond in time. */ case DEV_STATE_OFFLINE: /* * We can't register the device in interrupt context so @@ -502,9 +508,6 @@ io_subchannel_recog_done(struct ccw_devi io_subchannel_register, (void *) cdev); queue_work(ccw_device_work, &cdev->private->kick_work); break; - case DEV_STATE_BOXED: - /* Device did not respond in time. */ - break; } if (atomic_dec_and_test(&ccw_device_init_count)) wake_up(&ccw_device_init_wq); --- linux-2.5.73/drivers/s390/cio/device_fsm.c 2003-06-14 12:18:21.000000000 -0700 +++ 25/drivers/s390/cio/device_fsm.c 2003-06-27 15:56:24.000000000 -0700 @@ -132,11 +132,11 @@ ccw_device_recog_done(struct ccw_device CIO_DEBUG(KERN_WARNING, 2, "SenseID : boxed device %04X on subchannel %04X\n", sch->schib.pmcw.dev, sch->irq); - ccw_device_add_stlck(cdev); break; } io_subchannel_recog_done(cdev); - wake_up(&cdev->private->wait_q); + if (state != DEV_STATE_NOT_OPER) + wake_up(&cdev->private->wait_q); } /* @@ -159,22 +159,65 @@ ccw_device_sense_id_done(struct ccw_devi } /* + * Finished with online/offline processing. + */ +static void +ccw_device_done(struct ccw_device *cdev, int state) +{ + struct subchannel *sch; + + sch = to_subchannel(cdev->dev.parent); + + if (state != DEV_STATE_ONLINE) + cio_disable_subchannel(sch); + + /* Reset device status. */ + memset(&cdev->private->irb, 0, sizeof(struct irb)); + + cdev->private->state = state; + + + if (state == DEV_STATE_BOXED) { + CIO_DEBUG(KERN_WARNING, 2, + "Boxed device %04X on subchannel %04X\n", + sch->schib.pmcw.dev, sch->irq); + INIT_WORK(&cdev->private->kick_work, + ccw_device_add_stlck, (void *) cdev); + queue_work(ccw_device_work, &cdev->private->kick_work); + } + + wake_up(&cdev->private->wait_q); + + if (state != DEV_STATE_ONLINE) + put_device (&cdev->dev); +} + +/* * Function called from device_pgid.c after sense path ground has completed. */ void ccw_device_sense_pgid_done(struct ccw_device *cdev, int err) { + struct subchannel *sch; + + sch = to_subchannel(cdev->dev.parent); switch (err) { case 0: - cdev->private->state = DEV_STATE_SENSE_ID; - ccw_device_sense_id_start(cdev); + /* Start Path Group verification. */ + sch->vpm = 0; /* Start with no path groups set. */ + cdev->private->state = DEV_STATE_VERIFY; + ccw_device_verify_start(cdev); break; case -ETIME: /* Sense path group id stopped by timeout. */ case -EUSERS: /* device is reserved for someone else. */ - ccw_device_recog_done(cdev, DEV_STATE_BOXED); + ccw_device_done(cdev, DEV_STATE_BOXED); + break; + case -EOPNOTSUPP: /* path grouping not supported, just set online. */ + cdev->private->options.pgroup = 0; + ccw_device_done(cdev, DEV_STATE_ONLINE); break; default: - ccw_device_recog_done(cdev, DEV_STATE_NOT_OPER); + ccw_device_done(cdev, DEV_STATE_NOT_OPER); break; } } @@ -198,11 +241,15 @@ ccw_device_recognition(struct ccw_device ccw_device_set_timeout(cdev, 60*HZ); /* - * First thing we should do is a sensePGID in order to find out how - * we can proceed with the recognition process. + * We used to start here with a sense pgid to find out whether a device + * is locked by someone else. Unfortunately, the sense pgid command + * code has other meanings on devices predating the path grouping + * algorithm, so we start with sense id and box the device after an + * timeout (or if sense pgid during path verification detects the device + * is locked, as may happen on newer devices). */ - cdev->private->state = DEV_STATE_SENSE_PGID; - ccw_device_sense_pgid_start(cdev); + cdev->private->state = DEV_STATE_SENSE_ID; + ccw_device_sense_id_start(cdev); return 0; } @@ -218,29 +265,6 @@ ccw_device_recog_timeout(struct ccw_devi ccw_device_set_timeout(cdev, 3*HZ); } -/* - * Finished with online/offline processing. - */ -static void -ccw_device_done(struct ccw_device *cdev, int state) -{ - struct subchannel *sch; - - sch = to_subchannel(cdev->dev.parent); - - if (state != DEV_STATE_ONLINE) - cio_disable_subchannel(sch); - - /* Reset device status. */ - memset(&cdev->private->irb, 0, sizeof(struct irb)); - - cdev->private->state = state; - - wake_up(&cdev->private->wait_q); - - if (state != DEV_STATE_ONLINE) - put_device (&cdev->dev); -} void ccw_device_verify_done(struct ccw_device *cdev, int err) @@ -276,16 +300,15 @@ ccw_device_online(struct ccw_device *cde dev_fsm_event(cdev, DEV_EVENT_NOTOPER); return -ENODEV; } - /* Is Set Path Group supported? */ - if (!cdev->private->flags.pgid_supp) { + /* Do we want to do path grouping? */ + if (!cdev->private->options.pgroup) { /* No, set state online immediately. */ ccw_device_done(cdev, DEV_STATE_ONLINE); return 0; } - /* Start Path Group verification. */ - sch->vpm = 0; /* Start with no path groups set. */ - cdev->private->state = DEV_STATE_VERIFY; - ccw_device_verify_start(cdev); + /* Do a SensePGID first. */ + cdev->private->state = DEV_STATE_SENSE_PGID; + ccw_device_sense_pgid_start(cdev); return 0; } @@ -321,8 +344,8 @@ ccw_device_offline(struct ccw_device *cd } if (sch->schib.scsw.actl != 0) return -EBUSY; - /* Is Set Path Group supported? */ - if (!cdev->private->flags.pgid_supp) { + /* Are we doing path grouping? */ + if (!cdev->private->options.pgroup) { /* No, set state offline immediately. */ ccw_device_done(cdev, DEV_STATE_OFFLINE); return 0; @@ -643,9 +666,9 @@ fsm_func_t *dev_jumptable[NR_DEV_STATES] [DEV_EVENT_VERIFY] ccw_device_nop, }, [DEV_STATE_SENSE_PGID] { - [DEV_EVENT_NOTOPER] ccw_device_recog_notoper, + [DEV_EVENT_NOTOPER] ccw_device_online_notoper, [DEV_EVENT_INTERRUPT] ccw_device_sense_pgid_irq, - [DEV_EVENT_TIMEOUT] ccw_device_recog_timeout, + [DEV_EVENT_TIMEOUT] ccw_device_onoff_timeout, [DEV_EVENT_VERIFY] ccw_device_nop, }, [DEV_STATE_SENSE_ID] { --- linux-2.5.73/drivers/s390/cio/device.h 2003-06-14 12:18:30.000000000 -0700 +++ 25/drivers/s390/cio/device.h 2003-06-27 15:56:24.000000000 -0700 @@ -95,7 +95,7 @@ void ccw_device_disband_done(struct ccw_ void ccw_device_call_handler(struct ccw_device *); -void ccw_device_add_stlck(struct ccw_device *); +void ccw_device_add_stlck(void *); int ccw_device_stlck(struct ccw_device *); /* qdio needs this. */ --- linux-2.5.73/drivers/s390/cio/device_ops.c 2003-06-14 12:18:29.000000000 -0700 +++ 25/drivers/s390/cio/device_ops.c 2003-06-27 15:56:24.000000000 -0700 @@ -37,6 +37,7 @@ ccw_device_set_options(struct ccw_device return -EINVAL; cdev->private->options.fast = (flags & CCWDEV_EARLY_NOTIFICATION) != 0; cdev->private->options.repall = (flags & CCWDEV_REPORT_ALL) != 0; + cdev->private->options.pgroup = (flags & CCWDEV_DO_PATHGROUP) != 0; return 0; } --- linux-2.5.73/drivers/s390/cio/device_pgid.c 2003-06-14 12:18:22.000000000 -0700 +++ 25/drivers/s390/cio/device_pgid.c 2003-06-27 15:56:24.000000000 -0700 @@ -84,7 +84,6 @@ ccw_device_sense_pgid_start(struct ccw_d cdev->private->state = DEV_STATE_SENSE_PGID; cdev->private->imask = 0x80; cdev->private->iretry = 5; - cdev->private->flags.pgid_supp = 0; memset (&cdev->private->pgid, 0, sizeof (struct pgid)); ret = __ccw_device_sense_pgid_start(cdev); if (ret) @@ -165,14 +164,13 @@ ccw_device_sense_pgid_irq(struct ccw_dev switch (__ccw_device_check_sense_pgid(cdev)) { /* 0, -ETIME, -EOPNOTSUPP, -EAGAIN, -EACCES or -EUSERS */ case 0: /* Sense Path Group ID successful. */ - cdev->private->flags.pgid_supp = 1; opm = sch->schib.pmcw.pim & sch->schib.pmcw.pam & sch->schib.pmcw.pom; for (i=0;i<8;i++) { if (opm == (0x80 << i)) { /* Don't group single path devices. */ - cdev->private->flags.pgid_supp = 0; + cdev->private->options.pgroup = 0; break; } } @@ -181,7 +179,7 @@ ccw_device_sense_pgid_irq(struct ccw_dev sizeof(struct pgid)); /* fall through. */ case -EOPNOTSUPP: /* Sense Path Group ID not supported */ - ccw_device_sense_pgid_done(cdev, 0); + ccw_device_sense_pgid_done(cdev, -EOPNOTSUPP); break; case -ETIME: /* Sense path group id stopped by timeout. */ ccw_device_sense_pgid_done(cdev, -ETIME); --- linux-2.5.73/drivers/s390/cio/qdio.h 2003-06-14 12:18:00.000000000 -0700 +++ 25/drivers/s390/cio/qdio.h 2003-06-27 15:56:24.000000000 -0700 @@ -1,7 +1,7 @@ #ifndef _CIO_QDIO_H #define _CIO_QDIO_H -#define VERSION_CIO_QDIO_H "$Revision: 1.16 $" +#define VERSION_CIO_QDIO_H "$Revision: 1.17 $" //#define QDIO_DBF_LIKE_HELL @@ -21,7 +21,15 @@ #define QDIO_TIMER_POLL_VALUE 1 #define IQDIO_TIMER_POLL_VALUE 1 -#define IQDIO_FILL_LEVEL_TO_POLL (QDIO_MAX_BUFFERS_PER_Q*4/3) +/* + * unfortunately this can't be (QDIO_MAX_BUFFERS_PER_Q*4/3) or so -- as + * we never know, whether we'll get initiative again, e.g. to give the + * transmit skb's back to the stack, however the stack may be waiting for + * them... therefore we define 4 as threshold to start polling (which + * will stop as soon as the asynchronous queue catches up) + * btw, this only applies to the asynchronous HiperSockets queue + */ +#define IQDIO_FILL_LEVEL_TO_POLL 4 #define IQDIO_THININT_ISC 3 #define IQDIO_DELAY_TARGET 0 --- linux-2.5.73/drivers/s390/net/ctcmain.c 2003-06-14 12:18:07.000000000 -0700 +++ 25/drivers/s390/net/ctcmain.c 2003-06-27 15:56:24.000000000 -0700 @@ -1,5 +1,5 @@ /* - * $Id: ctcmain.c,v 1.42 2003/05/23 17:45:57 felfert Exp $ + * $Id: ctcmain.c,v 1.43 2003/05/27 11:34:23 mschwide Exp $ * * CTC / ESCON network driver * @@ -36,7 +36,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * - * RELEASE-TAG: CTC/ESCON network driver $Revision: 1.42 $ + * RELEASE-TAG: CTC/ESCON network driver $Revision: 1.43 $ * */ @@ -272,7 +272,7 @@ static void print_banner(void) { static int printed = 0; - char vbuf[] = "$Revision: 1.42 $"; + char vbuf[] = "$Revision: 1.43 $"; char *version = vbuf; if (printed) @@ -2752,7 +2752,7 @@ ctc_init_netdevice(struct net_device * d dev->type = ARPHRD_SLIP; dev->tx_queue_len = 100; dev->flags = IFF_POINTOPOINT | IFF_NOARP; - SET_MODULE_OWNER(&tun->dev); + SET_MODULE_OWNER(dev); return dev; } --- linux-2.5.73/drivers/s390/net/ctctty.c 2003-06-14 12:18:22.000000000 -0700 +++ 25/drivers/s390/net/ctctty.c 2003-06-27 15:56:24.000000000 -0700 @@ -1,5 +1,5 @@ /* - * $Id: ctctty.c,v 1.11 2003/05/06 09:40:55 mschwide Exp $ + * $Id: ctctty.c,v 1.12 2003/06/17 11:36:44 mschwide Exp $ * * CTC / ESCON network driver, tty interface. * --- linux-2.5.73/drivers/s390/net/lcs.c 2003-06-14 12:17:58.000000000 -0700 +++ 25/drivers/s390/net/lcs.c 2003-06-27 15:56:24.000000000 -0700 @@ -11,7 +11,7 @@ * Frank Pavlic (pavlic@de.ibm.com) and * Martin Schwidefsky * - * $Revision: 1.51 $ $Date: 2003/03/28 08:54:40 $ + * $Revision: 1.53 $ $Date: 2003/06/17 11:36:45 $ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -58,7 +58,7 @@ /** * initialization string for output */ -#define VERSION_LCS_C "$Revision: 1.51 $" +#define VERSION_LCS_C "$Revision: 1.53 $" static char version[] __initdata = "LCS driver ("VERSION_LCS_C "/" VERSION_LCS_H ")"; @@ -1785,7 +1785,7 @@ lcs_new_device(struct ccwgroup_device *c dev->set_multicast_list = lcs_set_multicast_list; #endif dev->get_stats = lcs_getstats; - SET_MODULE_OWNER(&tun->dev); + SET_MODULE_OWNER(dev); if (register_netdev(dev) != 0) goto out; netif_stop_queue(dev); --- linux-2.5.73/drivers/s390/net/netiucv.c 2003-06-14 12:18:23.000000000 -0700 +++ 25/drivers/s390/net/netiucv.c 2003-06-27 15:56:24.000000000 -0700 @@ -1,5 +1,5 @@ /* - * $Id: netiucv.c,v 1.19 2003/04/08 16:00:17 mschwide Exp $ + * $Id: netiucv.c,v 1.20 2003/05/27 11:34:24 mschwide Exp $ * * IUCV network driver * @@ -30,7 +30,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * - * RELEASE-TAG: IUCV network driver $Revision: 1.19 $ + * RELEASE-TAG: IUCV network driver $Revision: 1.20 $ * */ @@ -1631,7 +1631,7 @@ netiucv_init_netdevice(int ifno, char *u dev->type = ARPHRD_SLIP; dev->tx_queue_len = NETIUCV_QUEUELEN_DEFAULT; dev->flags = IFF_POINTOPOINT | IFF_NOARP; - SET_MODULE_OWNER(&tun->dev); + SET_MODULE_OWNER(dev); return dev; } @@ -1717,7 +1717,7 @@ static struct device_driver netiucv_driv static void netiucv_banner(void) { - char vbuf[] = "$Revision: 1.19 $"; + char vbuf[] = "$Revision: 1.20 $"; char *version = vbuf; if ((version = strchr(version, ':'))) { --- linux-2.5.73/drivers/scsi/aha152x.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/scsi/aha152x.c 2003-06-27 15:56:54.000000000 -0700 @@ -941,7 +941,8 @@ static irqreturn_t swintr(int irqno, voi struct Scsi_Host *shpnt = lookup_irq(irqno); if (!shpnt) { - printk(KERN_ERR "aha152x%d: catched software interrupt %d for unknown controller.\n", HOSTNO, irqno); + /* no point using HOSTNO here! */ + printk(KERN_ERR "aha152x: catched software interrupt %d for unknown controller.\n", irqno); return IRQ_NONE; } @@ -1049,6 +1050,10 @@ struct Scsi_Host *aha152x_probe_one(stru printk(KERN_INFO "aha152x%d: trying software interrupt, ", shost->host_no); + + /* need to have host registered before triggering any interrupt */ + aha152x_host[registered_count] = shost; + mb(); SETPORT(DMACNTRL0, SWINT|INTEN); mdelay(1000); free_irq(shost->irq, shost); @@ -1064,7 +1069,7 @@ struct Scsi_Host *aha152x_probe_one(stru printk(KERN_ERR "aha152x%d: IRQ %d possibly wrong. " "Please verify.\n", shost->host_no, shost->irq); - goto out_release_region; + goto out_unregister_host; } printk("ok.\n"); @@ -1077,12 +1082,12 @@ struct Scsi_Host *aha152x_probe_one(stru "aha152x", shost) < 0) { printk(KERN_ERR "aha152x%d: failed to reassign interrupt.\n", shost->host_no); - goto out_release_region; + goto out_unregister_host; } - - aha152x_host[registered_count] = shost; return shost; /* the pcmcia stub needs the return value; */ +out_unregister_host: + aha152x_host[registered_count] = NULL; out_release_region: release_region(shost->io_port, IO_RANGE); out_unregister: --- linux-2.5.73/drivers/scsi/fd_mcs.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/scsi/fd_mcs.c 2003-06-27 15:56:24.000000000 -0700 @@ -589,7 +589,6 @@ static int TOTAL_INTR = 0; static int fd_mcs_proc_info(struct Scsi_Host *shpnt, char *buffer, char **start, off_t offset, int length, int inout) { int len = 0; - int i; if (inout) return (-ENOSYS); --- linux-2.5.73/drivers/scsi/gdth.c 2003-06-26 22:07:24.000000000 -0700 +++ 25/drivers/scsi/gdth.c 2003-06-27 15:56:24.000000000 -0700 @@ -3662,7 +3662,7 @@ static int gdth_sync_event(int hanum,int pci_unmap_single(ha->pdev,scp->SCp.dma_handle, scp->request_bufflen,scp->SCp.Message); if (scp->SCp.buffer) - pci_unmap_single(ha->pdev,(dma_addr_t)(u32)scp->SCp.buffer, + pci_unmap_single(ha->pdev,(dma_addr_t)scp->SCp.buffer, 16,PCI_DMA_FROMDEVICE); #endif if (ha->status == S_OK) { --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/common/isp.c 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,6702 @@ +/* + * Machine and OS Independent (well, as best as possible) + * code for the Qlogic ISP SCSI adapters. + * + * Copyright (c) 1997, 1998, 1999, 2000, 2001 by Matthew Jacob + * Feral Software + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Inspiration and ideas about this driver are from Erik Moe's Linux driver + * (qlogicisp.c) and Dave Miller's SBus version of same (qlogicisp.c). Some + * ideas dredged from the Solaris driver. + */ + +/* + * Include header file appropriate for platform we're building on. + */ + +#ifdef __NetBSD__ +#include +#endif +#ifdef __FreeBSD__ +#include +#endif +#ifdef __OpenBSD__ +#include +#endif +#ifdef __linux__ +#include "isp_linux.h" +#endif +#ifdef __svr4__ +#include "isp_solaris.h" +#endif + +/* + * General defines + */ + +#define MBOX_DELAY_COUNT 1000000 / 100 + +/* + * Local static data + */ +static const char portshift[] = + "Target %d Loop ID 0x%x (Port 0x%x) => Loop 0x%x (Port 0x%x)"; +static const char portdup[] = + "Target %d duplicates Target %d- killing off both"; +static const char retained[] = + "Retaining Loop ID 0x%x for Target %d (Port 0x%x)"; +static const char lretained[] = + "Retained login of Target %d (Loop ID 0x%x) Port 0x%x"; +static const char plogout[] = + "Logging out Target %d at Loop ID 0x%x (Port 0x%x)"; +static const char plogierr[] = + "Command Error in PLOGI for Port 0x%x (0x%x)"; +static const char nopdb[] = + "Could not get PDB for Device @ Port 0x%x"; +static const char pdbmfail1[] = + "PDB Loop ID info for Device @ Port 0x%x does not match up (0x%x)"; +static const char pdbmfail2[] = + "PDB Port info for Device @ Port 0x%x does not match up (0x%x)"; +static const char ldumped[] = + "Target %d (Loop ID 0x%x) Port 0x%x dumped after login info mismatch"; +static const char notresp[] = + "Not RESPONSE in RESPONSE Queue (type 0x%x) @ idx %d (next %d) nlooked %d"; +static const char xact1[] = + "HBA attempted queued transaction with disconnect not set for %d.%d.%d"; +static const char xact2[] = + "HBA attempted queued transaction to target routine %d on target %d bus %d"; +static const char xact3[] = + "HBA attempted queued cmd for %d.%d.%d when queueing disabled"; +static const char pskip[] = + "SCSI phase skipped for target %d.%d.%d"; +static const char topology[] = + "Loop ID %d, AL_PA 0x%x, Port ID 0x%x, Loop State 0x%x, Topology '%s'"; +static const char swrej[] = + "Fabric Nameserver rejected %s (Reason=0x%x Expl=0x%x) for Port ID 0x%x"; +static const char finmsg[] = + "(%d.%d.%d): FIN dl%d resid %d STS 0x%x SKEY %c XS_ERR=0x%x"; +static const char sc0[] = + "%s CHAN %d FTHRSH %d IID %d RESETD %d RETRYC %d RETRYD %d ASD 0x%x"; +static const char sc1[] = + "%s RAAN 0x%x DLAN 0x%x DDMAB 0x%x CDMAB 0x%x SELTIME %d MQD %d"; +static const char sc2[] = "%s CHAN %d TGT %d FLAGS 0x%x 0x%x/0x%x"; +static const char sc3[] = "Generated"; +static const char sc4[] = "NVRAM"; +static const char bun[] = + "bad underrun for %d.%d (count %d, resid %d, status %s)"; + +/* + * Local function prototypes. + */ +static int isp_parse_async(struct ispsoftc *, u_int16_t); +static int isp_handle_other_response(struct ispsoftc *, int, isphdr_t *, + u_int16_t *); +static void +isp_parse_status(struct ispsoftc *, ispstatusreq_t *, XS_T *); +static void isp_fastpost_complete(struct ispsoftc *, u_int16_t); +static int isp_mbox_continue(struct ispsoftc *); +static void isp_scsi_init(struct ispsoftc *); +static void isp_scsi_channel_init(struct ispsoftc *, int); +static void isp_fibre_init(struct ispsoftc *); +static void isp_mark_getpdb_all(struct ispsoftc *); +static int isp_getmap(struct ispsoftc *, fcpos_map_t *); +static int isp_getpdb(struct ispsoftc *, int, isp_pdb_t *); +static u_int64_t isp_get_portname(struct ispsoftc *, int, int); +static int isp_fclink_test(struct ispsoftc *, int); +static char *isp2100_fw_statename(int); +static int isp_pdb_sync(struct ispsoftc *); +static int isp_scan_loop(struct ispsoftc *); +static int isp_fabric_mbox_cmd(struct ispsoftc *, mbreg_t *); +static int isp_scan_fabric(struct ispsoftc *, int); +static void isp_register_fc4_type(struct ispsoftc *); +static void isp_fw_state(struct ispsoftc *); +static void isp_mboxcmd_qnw(struct ispsoftc *, mbreg_t *, int); +static void isp_mboxcmd(struct ispsoftc *, mbreg_t *, int); + +static void isp_update(struct ispsoftc *); +static void isp_update_bus(struct ispsoftc *, int); +static void isp_setdfltparm(struct ispsoftc *, int); +static int isp_read_nvram(struct ispsoftc *); +static void isp_rdnvram_word(struct ispsoftc *, int, u_int16_t *); +static void isp_parse_nvram_1020(struct ispsoftc *, u_int8_t *); +static void isp_parse_nvram_1080(struct ispsoftc *, int, u_int8_t *); +static void isp_parse_nvram_12160(struct ispsoftc *, int, u_int8_t *); +static void isp_parse_nvram_2100(struct ispsoftc *, u_int8_t *); + +/* + * Reset Hardware. + * + * Hit the chip over the head, download new f/w if available and set it running. + * + * Locking done elsewhere. + */ + +void +isp_reset(struct ispsoftc *isp) +{ + mbreg_t mbs; + u_int16_t code_org; + int loops, i, dodnld = 1; + char *btype = "????"; + + isp->isp_state = ISP_NILSTATE; + + /* + * Basic types (SCSI, FibreChannel and PCI or SBus) + * have been set in the MD code. We figure out more + * here. Possibly more refined types based upon PCI + * identification. Chip revision has been gathered. + * + * After we've fired this chip up, zero out the conf1 register + * for SCSI adapters and do other settings for the 2100. + */ + + /* + * Get the current running firmware revision out of the + * chip before we hit it over the head (if this is our + * first time through). Note that we store this as the + * 'ROM' firmware revision- which it may not be. In any + * case, we don't really use this yet, but we may in + * the future. + */ + if (isp->isp_touched == 0) { + /* + * First see whether or not we're sitting in the ISP PROM. + * If we've just been reset, we'll have the string "ISP " + * spread through outgoing mailbox registers 1-3. We do + * this for PCI cards because otherwise we really don't + * know what state the card is in and we could hang if + * we try this command otherwise. + * + * For SBus cards, we just do this because they almost + * certainly will be running firmware by now. + */ + if (ISP_READ(isp, OUTMAILBOX1) != 0x4953 || + ISP_READ(isp, OUTMAILBOX2) != 0x5020 || + ISP_READ(isp, OUTMAILBOX3) != 0x2020) { + /* + * Just in case it was paused... + */ + ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); + mbs.param[0] = MBOX_ABOUT_FIRMWARE; + isp_mboxcmd(isp, &mbs, MBLOGNONE); + if (mbs.param[0] == MBOX_COMMAND_COMPLETE) { + isp->isp_romfw_rev[0] = mbs.param[1]; + isp->isp_romfw_rev[1] = mbs.param[2]; + isp->isp_romfw_rev[2] = mbs.param[3]; + } + } + isp->isp_touched = 1; + } + + DISABLE_INTS(isp); + + /* + * Set up default request/response queue in-pointer/out-pointer + * register indices. + */ + if (IS_23XX(isp)) { + isp->isp_rqstinrp = BIU_REQINP; + isp->isp_rqstoutrp = BIU_REQOUTP; + isp->isp_respinrp = BIU_RSPINP; + isp->isp_respoutrp = BIU_RSPOUTP; + } else { + isp->isp_rqstinrp = INMAILBOX4; + isp->isp_rqstoutrp = OUTMAILBOX4; + isp->isp_respinrp = OUTMAILBOX5; + isp->isp_respoutrp = INMAILBOX5; + } + + /* + * Put the board into PAUSE mode (so we can read the SXP registers + * or write FPM/FBM registers). + */ + ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); + + if (IS_FC(isp)) { + switch (isp->isp_type) { + case ISP_HA_FC_2100: + btype = "2100"; + break; + case ISP_HA_FC_2200: + btype = "2200"; + break; + case ISP_HA_FC_2300: + btype = "2300"; + break; + case ISP_HA_FC_2312: + btype = "2312"; + break; + default: + break; + } + /* + * While we're paused, reset the FPM module and FBM fifos. + */ + ISP_WRITE(isp, BIU2100_CSR, BIU2100_FPM0_REGS); + ISP_WRITE(isp, FPM_DIAG_CONFIG, FPM_SOFT_RESET); + ISP_WRITE(isp, BIU2100_CSR, BIU2100_FB_REGS); + ISP_WRITE(isp, FBM_CMD, FBMCMD_FIFO_RESET_ALL); + ISP_WRITE(isp, BIU2100_CSR, BIU2100_RISC_REGS); + } else if (IS_1240(isp)) { + sdparam *sdp = isp->isp_param; + btype = "1240"; + isp->isp_clock = 60; + sdp->isp_ultramode = 1; + sdp++; + sdp->isp_ultramode = 1; + /* + * XXX: Should probably do some bus sensing. + */ + } else if (IS_ULTRA2(isp)) { + static const char m[] = "bus %d is in %s Mode"; + u_int16_t l; + sdparam *sdp = isp->isp_param; + + isp->isp_clock = 100; + + if (IS_1280(isp)) + btype = "1280"; + else if (IS_1080(isp)) + btype = "1080"; + else if (IS_10160(isp)) + btype = "10160"; + else if (IS_12160(isp)) + btype = "12160"; + else + btype = ""; + + l = ISP_READ(isp, SXP_PINS_DIFF) & ISP1080_MODE_MASK; + switch (l) { + case ISP1080_LVD_MODE: + sdp->isp_lvdmode = 1; + isp_prt(isp, ISP_LOGCONFIG, m, 0, "LVD"); + break; + case ISP1080_HVD_MODE: + sdp->isp_diffmode = 1; + isp_prt(isp, ISP_LOGCONFIG, m, 0, "Differential"); + break; + case ISP1080_SE_MODE: + sdp->isp_ultramode = 1; + isp_prt(isp, ISP_LOGCONFIG, m, 0, "Single-Ended"); + break; + default: + isp_prt(isp, ISP_LOGERR, + "unknown mode on bus %d (0x%x)", 0, l); + break; + } + + if (IS_DUALBUS(isp)) { + sdp++; + l = ISP_READ(isp, SXP_PINS_DIFF|SXP_BANK1_SELECT); + l &= ISP1080_MODE_MASK; + switch(l) { + case ISP1080_LVD_MODE: + sdp->isp_lvdmode = 1; + isp_prt(isp, ISP_LOGCONFIG, m, 1, "LVD"); + break; + case ISP1080_HVD_MODE: + sdp->isp_diffmode = 1; + isp_prt(isp, ISP_LOGCONFIG, + m, 1, "Differential"); + break; + case ISP1080_SE_MODE: + sdp->isp_ultramode = 1; + isp_prt(isp, ISP_LOGCONFIG, + m, 1, "Single-Ended"); + break; + default: + isp_prt(isp, ISP_LOGERR, + "unknown mode on bus %d (0x%x)", 1, l); + break; + } + } + } else { + sdparam *sdp = isp->isp_param; + i = ISP_READ(isp, BIU_CONF0) & BIU_CONF0_HW_MASK; + switch (i) { + default: + isp_prt(isp, ISP_LOGALL, "Unknown Chip Type 0x%x", i); + /* FALLTHROUGH */ + case 1: + btype = "1020"; + isp->isp_type = ISP_HA_SCSI_1020; + isp->isp_clock = 40; + break; + case 2: + /* + * Some 1020A chips are Ultra Capable, but don't + * run the clock rate up for that unless told to + * do so by the Ultra Capable bits being set. + */ + btype = "1020A"; + isp->isp_type = ISP_HA_SCSI_1020A; + isp->isp_clock = 40; + break; + case 3: + btype = "1040"; + isp->isp_type = ISP_HA_SCSI_1040; + isp->isp_clock = 60; + break; + case 4: + btype = "1040A"; + isp->isp_type = ISP_HA_SCSI_1040A; + isp->isp_clock = 60; + break; + case 5: + btype = "1040B"; + isp->isp_type = ISP_HA_SCSI_1040B; + isp->isp_clock = 60; + break; + case 6: + btype = "1040C"; + isp->isp_type = ISP_HA_SCSI_1040C; + isp->isp_clock = 60; + break; + } + /* + * Now, while we're at it, gather info about ultra + * and/or differential mode. + */ + if (ISP_READ(isp, SXP_PINS_DIFF) & SXP_PINS_DIFF_MODE) { + isp_prt(isp, ISP_LOGCONFIG, "Differential Mode"); + sdp->isp_diffmode = 1; + } else { + sdp->isp_diffmode = 0; + } + i = ISP_READ(isp, RISC_PSR); + if (isp->isp_bustype == ISP_BT_SBUS) { + i &= RISC_PSR_SBUS_ULTRA; + } else { + i &= RISC_PSR_PCI_ULTRA; + } + if (i != 0) { + isp_prt(isp, ISP_LOGCONFIG, "Ultra Mode Capable"); + sdp->isp_ultramode = 1; + /* + * If we're in Ultra Mode, we have to be 60Mhz clock- + * even for the SBus version. + */ + isp->isp_clock = 60; + } else { + sdp->isp_ultramode = 0; + /* + * Clock is known. Gronk. + */ + } + + /* + * Machine dependent clock (if set) overrides + * our generic determinations. + */ + if (isp->isp_mdvec->dv_clock) { + if (isp->isp_mdvec->dv_clock < isp->isp_clock) { + isp->isp_clock = isp->isp_mdvec->dv_clock; + } + } + + } + + /* + * Clear instrumentation + */ + isp->isp_intcnt = isp->isp_intbogus = 0; + + /* + * Do MD specific pre initialization + */ + ISP_RESET0(isp); + +again: + + /* + * Hit the chip over the head with hammer, + * and give the ISP a chance to recover. + */ + + if (IS_SCSI(isp)) { + ISP_WRITE(isp, BIU_ICR, BIU_ICR_SOFT_RESET); + /* + * A slight delay... + */ + USEC_DELAY(100); + + /* + * Clear data && control DMA engines. + */ + ISP_WRITE(isp, CDMA_CONTROL, + DMA_CNTRL_CLEAR_CHAN | DMA_CNTRL_RESET_INT); + ISP_WRITE(isp, DDMA_CONTROL, + DMA_CNTRL_CLEAR_CHAN | DMA_CNTRL_RESET_INT); + + + } else { + ISP_WRITE(isp, BIU2100_CSR, BIU2100_SOFT_RESET); + /* + * A slight delay... + */ + USEC_DELAY(100); + + /* + * Clear data && control DMA engines. + */ + ISP_WRITE(isp, CDMA2100_CONTROL, + DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT); + ISP_WRITE(isp, TDMA2100_CONTROL, + DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT); + ISP_WRITE(isp, RDMA2100_CONTROL, + DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT); + } + + /* + * Wait for ISP to be ready to go... + */ + loops = MBOX_DELAY_COUNT; + for (;;) { + if (IS_SCSI(isp)) { + if (!(ISP_READ(isp, BIU_ICR) & BIU_ICR_SOFT_RESET)) + break; + } else { + if (!(ISP_READ(isp, BIU2100_CSR) & BIU2100_SOFT_RESET)) + break; + } + USEC_DELAY(100); + if (--loops < 0) { + ISP_DUMPREGS(isp, "chip reset timed out"); + return; + } + } + + /* + * After we've fired this chip up, zero out the conf1 register + * for SCSI adapters and other settings for the 2100. + */ + + if (IS_SCSI(isp)) { + ISP_WRITE(isp, BIU_CONF1, 0); + } else { + ISP_WRITE(isp, BIU2100_CSR, 0); + } + + /* + * Reset RISC Processor + */ + ISP_WRITE(isp, HCCR, HCCR_CMD_RESET); + USEC_DELAY(100); + /* Clear semaphore register (just to be sure) */ + ISP_WRITE(isp, BIU_SEMA, 0); + + /* + * Establish some initial burst rate stuff. + * (only for the 1XX0 boards). This really should + * be done later after fetching from NVRAM. + */ + if (IS_SCSI(isp)) { + u_int16_t tmp = isp->isp_mdvec->dv_conf1; + /* + * Busted FIFO. Turn off all but burst enables. + */ + if (isp->isp_type == ISP_HA_SCSI_1040A) { + tmp &= BIU_BURST_ENABLE; + } + ISP_SETBITS(isp, BIU_CONF1, tmp); + if (tmp & BIU_BURST_ENABLE) { + ISP_SETBITS(isp, CDMA_CONF, DMA_ENABLE_BURST); + ISP_SETBITS(isp, DDMA_CONF, DMA_ENABLE_BURST); + } +#ifdef PTI_CARDS + if (((sdparam *) isp->isp_param)->isp_ultramode) { + while (ISP_READ(isp, RISC_MTR) != 0x1313) { + ISP_WRITE(isp, RISC_MTR, 0x1313); + ISP_WRITE(isp, HCCR, HCCR_CMD_STEP); + } + } else { + ISP_WRITE(isp, RISC_MTR, 0x1212); + } + /* + * PTI specific register + */ + ISP_WRITE(isp, RISC_EMB, DUAL_BANK) +#else + ISP_WRITE(isp, RISC_MTR, 0x1212); +#endif + } else { + ISP_WRITE(isp, RISC_MTR2100, 0x1212); + if (IS_2200(isp) || IS_23XX(isp)) { + ISP_WRITE(isp, HCCR, HCCR_2X00_DISABLE_PARITY_PAUSE); + } + } + + ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); /* release paused processor */ + + /* + * Do MD specific post initialization + */ + ISP_RESET1(isp); + + /* + * Wait for everything to finish firing up. + * + * Avoid doing this on the 2312 because you can generate a PCI + * parity error (chip breakage). + */ + if (IS_23XX(isp)) { + USEC_DELAY(5); + } else { + loops = MBOX_DELAY_COUNT; + while (ISP_READ(isp, OUTMAILBOX0) == MBOX_BUSY) { + USEC_DELAY(100); + if (--loops < 0) { + isp_prt(isp, ISP_LOGERR, + "MBOX_BUSY never cleared on reset"); + return; + } + } + } + + /* + * Up until this point we've done everything by just reading or + * setting registers. From this point on we rely on at least *some* + * kind of firmware running in the card. + */ + + /* + * Do some sanity checking. + */ + mbs.param[0] = MBOX_NO_OP; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + return; + } + + if (IS_SCSI(isp)) { + mbs.param[0] = MBOX_MAILBOX_REG_TEST; + mbs.param[1] = 0xdead; + mbs.param[2] = 0xbeef; + mbs.param[3] = 0xffff; + mbs.param[4] = 0x1111; + mbs.param[5] = 0xa5a5; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + return; + } + if (mbs.param[1] != 0xdead || mbs.param[2] != 0xbeef || + mbs.param[3] != 0xffff || mbs.param[4] != 0x1111 || + mbs.param[5] != 0xa5a5) { + isp_prt(isp, ISP_LOGERR, + "Register Test Failed (0x%x 0x%x 0x%x 0x%x 0x%x)", + mbs.param[1], mbs.param[2], mbs.param[3], + mbs.param[4], mbs.param[5]); + return; + } + + } + + /* + * Download new Firmware, unless requested not to do so. + * This is made slightly trickier in some cases where the + * firmware of the ROM revision is newer than the revision + * compiled into the driver. So, where we used to compare + * versions of our f/w and the ROM f/w, now we just see + * whether we have f/w at all and whether a config flag + * has disabled our download. + */ + if ((isp->isp_mdvec->dv_ispfw == NULL) || + (isp->isp_confopts & ISP_CFG_NORELOAD)) { + dodnld = 0; + } + + if (IS_23XX(isp)) + code_org = ISP_CODE_ORG_2300; + else + code_org = ISP_CODE_ORG; + + if (dodnld) { + isp->isp_mbxworkp = (void *) &isp->isp_mdvec->dv_ispfw[1]; + isp->isp_mbxwrk0 = isp->isp_mdvec->dv_ispfw[3] - 1; + isp->isp_mbxwrk1 = code_org + 1; + mbs.param[0] = MBOX_WRITE_RAM_WORD; + mbs.param[1] = code_org; + mbs.param[2] = isp->isp_mdvec->dv_ispfw[0]; + isp_mboxcmd(isp, &mbs, MBLOGNONE); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + isp_prt(isp, ISP_LOGERR, + "F/W download failed at word %d", + isp->isp_mbxwrk1 - code_org); + dodnld = 0; + goto again; + } + /* + * Verify that it downloaded correctly. + */ + mbs.param[0] = MBOX_VERIFY_CHECKSUM; + mbs.param[1] = code_org; + isp_mboxcmd(isp, &mbs, MBLOGNONE); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + isp_prt(isp, ISP_LOGERR, "Ram Checksum Failure"); + return; + } + isp->isp_loaded_fw = 1; + } else { + isp->isp_loaded_fw = 0; + isp_prt(isp, ISP_LOGDEBUG2, "skipping f/w download"); + } + + /* + * Now start it rolling. + * + * If we didn't actually download f/w, + * we still need to (re)start it. + */ + + + mbs.param[0] = MBOX_EXEC_FIRMWARE; + mbs.param[1] = code_org; + isp_mboxcmd(isp, &mbs, MBLOGNONE); + /* + * Give it a chance to start. + */ + USEC_DELAY(500); + + if (IS_SCSI(isp)) { + /* + * Set CLOCK RATE, but only if asked to. + */ + if (isp->isp_clock) { + mbs.param[0] = MBOX_SET_CLOCK_RATE; + mbs.param[1] = isp->isp_clock; + isp_mboxcmd(isp, &mbs, MBLOGALL); + /* we will try not to care if this fails */ + } + } + + mbs.param[0] = MBOX_ABOUT_FIRMWARE; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + return; + } + + /* + * The SBus firmware that we are using apparently does not return + * major, minor, micro revisions in the mailbox registers, which + * is really, really, annoying. + */ + if (ISP_SBUS_SUPPORTED && isp->isp_bustype == ISP_BT_SBUS) { + if (dodnld) { +#ifdef ISP_TARGET_MODE + isp->isp_fwrev[0] = 7; + isp->isp_fwrev[1] = 55; +#else + isp->isp_fwrev[0] = 1; + isp->isp_fwrev[1] = 37; +#endif + isp->isp_fwrev[2] = 0; + } + } else { + isp->isp_fwrev[0] = mbs.param[1]; + isp->isp_fwrev[1] = mbs.param[2]; + isp->isp_fwrev[2] = mbs.param[3]; + } + isp_prt(isp, ISP_LOGCONFIG, + "Board Type %s, Chip Revision 0x%x, %s F/W Revision %d.%d.%d", + btype, isp->isp_revision, dodnld? "loaded" : "resident", + isp->isp_fwrev[0], isp->isp_fwrev[1], isp->isp_fwrev[2]); + + if (IS_FC(isp)) { + /* + * We do not believe firmware attributes for 2100 code less + * than 1.17.0, unless it's the firmware we specifically + * are loading. + * + * Note that all 22XX and 23XX f/w is greater than 1.X.0. + */ + if (!(ISP_FW_NEWER_THAN(isp, 1, 17, 0))) { +#ifdef USE_SMALLER_2100_FIRMWARE + FCPARAM(isp)->isp_fwattr = ISP_FW_ATTR_SCCLUN; +#else + FCPARAM(isp)->isp_fwattr = 0; +#endif + } else { + FCPARAM(isp)->isp_fwattr = mbs.param[6]; + isp_prt(isp, ISP_LOGDEBUG0, + "Firmware Attributes = 0x%x", mbs.param[6]); + } + if (ISP_READ(isp, BIU2100_CSR) & BIU2100_PCI64) { + isp_prt(isp, ISP_LOGCONFIG, + "Installed in 64-Bit PCI slot"); + } + } + + if (isp->isp_romfw_rev[0] || isp->isp_romfw_rev[1] || + isp->isp_romfw_rev[2]) { + isp_prt(isp, ISP_LOGCONFIG, "Last F/W revision was %d.%d.%d", + isp->isp_romfw_rev[0], isp->isp_romfw_rev[1], + isp->isp_romfw_rev[2]); + } + + mbs.param[0] = MBOX_GET_FIRMWARE_STATUS; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + return; + } + isp->isp_maxcmds = mbs.param[2]; + isp_prt(isp, ISP_LOGINFO, + "%d max I/O commands supported", mbs.param[2]); + isp_fw_state(isp); + + /* + * Set up DMA for the request and result mailboxes. + */ + if (ISP_MBOXDMASETUP(isp) != 0) { + isp_prt(isp, ISP_LOGERR, "Cannot setup DMA"); + return; + } + isp->isp_state = ISP_RESETSTATE; + + /* + * Okay- now that we have new firmware running, we now (re)set our + * notion of how many luns we support. This is somewhat tricky because + * if we haven't loaded firmware, we sometimes do not have an easy way + * of knowing how many luns we support. + * + * Expanded lun firmware gives you 32 luns for SCSI cards and + * 16384 luns for Fibre Channel cards. + * + * It turns out that even for QLogic 2100s with ROM 1.10 and above + * we do get a firmware attributes word returned in mailbox register 6. + * + * Because the lun is in a different position in the Request Queue + * Entry structure for Fibre Channel with expanded lun firmware, we + * can only support one lun (lun zero) when we don't know what kind + * of firmware we're running. + */ + if (IS_SCSI(isp)) { + if (dodnld) { + if (IS_ULTRA2(isp) || IS_ULTRA3(isp)) { + isp->isp_maxluns = 32; + } else { + isp->isp_maxluns = 8; + } + } else { + isp->isp_maxluns = 8; + } + } else { + if (FCPARAM(isp)->isp_fwattr & ISP_FW_ATTR_SCCLUN) { + isp->isp_maxluns = 16384; + } else { + isp->isp_maxluns = 16; + } + } +} + +/* + * Initialize Parameters of Hardware to a known state. + * + * Locks are held before coming here. + */ + +void +isp_init(struct ispsoftc *isp) +{ + /* + * Must do this first to get defaults established. + */ + isp_setdfltparm(isp, 0); + if (IS_DUALBUS(isp)) { + isp_setdfltparm(isp, 1); + } + if (IS_FC(isp)) { + isp_fibre_init(isp); + } else { + isp_scsi_init(isp); + } +} + +static void +isp_scsi_init(struct ispsoftc *isp) +{ + sdparam *sdp_chan0, *sdp_chan1; + mbreg_t mbs; + + sdp_chan0 = isp->isp_param; + sdp_chan1 = sdp_chan0; + if (IS_DUALBUS(isp)) { + sdp_chan1++; + } + + /* + * If we have no role (neither target nor initiator), return. + */ + if (isp->isp_role == ISP_ROLE_NONE) { + return; + } + + /* First do overall per-card settings. */ + + /* + * If we have fast memory timing enabled, turn it on. + */ + if (sdp_chan0->isp_fast_mttr) { + ISP_WRITE(isp, RISC_MTR, 0x1313); + } + + /* + * Set Retry Delay and Count. + * You set both channels at the same time. + */ + mbs.param[0] = MBOX_SET_RETRY_COUNT; + mbs.param[1] = sdp_chan0->isp_retry_count; + mbs.param[2] = sdp_chan0->isp_retry_delay; + mbs.param[6] = sdp_chan1->isp_retry_count; + mbs.param[7] = sdp_chan1->isp_retry_delay; + + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + return; + } + + /* + * Set ASYNC DATA SETUP time. This is very important. + */ + mbs.param[0] = MBOX_SET_ASYNC_DATA_SETUP_TIME; + mbs.param[1] = sdp_chan0->isp_async_data_setup; + mbs.param[2] = sdp_chan1->isp_async_data_setup; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + return; + } + + /* + * Set ACTIVE Negation State. + */ + mbs.param[0] = MBOX_SET_ACT_NEG_STATE; + mbs.param[1] = + (sdp_chan0->isp_req_ack_active_neg << 4) | + (sdp_chan0->isp_data_line_active_neg << 5); + mbs.param[2] = + (sdp_chan1->isp_req_ack_active_neg << 4) | + (sdp_chan1->isp_data_line_active_neg << 5); + + isp_mboxcmd(isp, &mbs, MBLOGNONE); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + isp_prt(isp, ISP_LOGERR, + "failed to set active negation state (%d,%d), (%d,%d)", + sdp_chan0->isp_req_ack_active_neg, + sdp_chan0->isp_data_line_active_neg, + sdp_chan1->isp_req_ack_active_neg, + sdp_chan1->isp_data_line_active_neg); + /* + * But don't return. + */ + } + + /* + * Set the Tag Aging limit + */ + mbs.param[0] = MBOX_SET_TAG_AGE_LIMIT; + mbs.param[1] = sdp_chan0->isp_tag_aging; + mbs.param[2] = sdp_chan1->isp_tag_aging; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + isp_prt(isp, ISP_LOGERR, "failed to set tag age limit (%d,%d)", + sdp_chan0->isp_tag_aging, sdp_chan1->isp_tag_aging); + return; + } + + /* + * Set selection timeout. + */ + mbs.param[0] = MBOX_SET_SELECT_TIMEOUT; + mbs.param[1] = sdp_chan0->isp_selection_timeout; + mbs.param[2] = sdp_chan1->isp_selection_timeout; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + return; + } + + /* now do per-channel settings */ + isp_scsi_channel_init(isp, 0); + if (IS_DUALBUS(isp)) + isp_scsi_channel_init(isp, 1); + + /* + * Now enable request/response queues + */ + + if (IS_ULTRA2(isp) || IS_1240(isp)) { + mbs.param[0] = MBOX_INIT_RES_QUEUE_A64; + mbs.param[1] = RESULT_QUEUE_LEN(isp); + mbs.param[2] = DMA_WD1(isp->isp_result_dma); + mbs.param[3] = DMA_WD0(isp->isp_result_dma); + mbs.param[4] = 0; + mbs.param[6] = DMA_WD3(isp->isp_result_dma); + mbs.param[7] = DMA_WD2(isp->isp_result_dma); + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + return; + } + isp->isp_residx = mbs.param[5]; + + mbs.param[0] = MBOX_INIT_REQ_QUEUE_A64; + mbs.param[1] = RQUEST_QUEUE_LEN(isp); + mbs.param[2] = DMA_WD1(isp->isp_rquest_dma); + mbs.param[3] = DMA_WD0(isp->isp_rquest_dma); + mbs.param[5] = 0; + mbs.param[6] = DMA_WD3(isp->isp_result_dma); + mbs.param[7] = DMA_WD2(isp->isp_result_dma); + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + return; + } + isp->isp_reqidx = isp->isp_reqodx = mbs.param[4]; + } else { + mbs.param[0] = MBOX_INIT_RES_QUEUE; + mbs.param[1] = RESULT_QUEUE_LEN(isp); + mbs.param[2] = DMA_WD1(isp->isp_result_dma); + mbs.param[3] = DMA_WD0(isp->isp_result_dma); + mbs.param[4] = 0; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + return; + } + isp->isp_residx = mbs.param[5]; + + mbs.param[0] = MBOX_INIT_REQ_QUEUE; + mbs.param[1] = RQUEST_QUEUE_LEN(isp); + mbs.param[2] = DMA_WD1(isp->isp_rquest_dma); + mbs.param[3] = DMA_WD0(isp->isp_rquest_dma); + mbs.param[5] = 0; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + return; + } + isp->isp_reqidx = isp->isp_reqodx = mbs.param[4]; + } + + /* + * Turn on Fast Posting, LVD transitions + * + * Ultra2 F/W always has had fast posting (and LVD transitions) + * + * Ultra and older (i.e., SBus) cards may not. It's just safer + * to assume not for them. + */ + + mbs.param[0] = MBOX_SET_FW_FEATURES; + mbs.param[1] = 0; + if (IS_ULTRA2(isp)) + mbs.param[1] |= FW_FEATURE_LVD_NOTIFY; +#ifndef ISP_NO_RIO + if (IS_ULTRA2(isp) || IS_1240(isp)) + mbs.param[1] |= FW_FEATURE_RIO_16BIT; +#else +#ifndef ISP_NO_FASTPOST + if (IS_ULTRA2(isp) || IS_1240(isp)) + mbs.param[1] |= FW_FEATURE_FAST_POST; +#endif +#endif + if (mbs.param[1] != 0) { + u_int16_t sfeat = mbs.param[1]; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] == MBOX_COMMAND_COMPLETE) { + isp_prt(isp, ISP_LOGINFO, + "Enabled FW features (0x%x)", sfeat); + } + } + + /* + * Let the outer layers decide whether to issue a SCSI bus reset. + */ + isp->isp_state = ISP_INITSTATE; +} + +static void +isp_scsi_channel_init(struct ispsoftc *isp, int channel) +{ + sdparam *sdp; + mbreg_t mbs; + int tgt; + + sdp = isp->isp_param; + sdp += channel; + + /* + * Set (possibly new) Initiator ID. + */ + mbs.param[0] = MBOX_SET_INIT_SCSI_ID; + mbs.param[1] = (channel << 7) | sdp->isp_initiator_id; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + return; + } + isp_prt(isp, ISP_LOGINFO, "Initiator ID is %d on Channel %d", + sdp->isp_initiator_id, channel); + + + /* + * Set current per-target parameters to an initial safe minimum. + */ + for (tgt = 0; tgt < MAX_TARGETS; tgt++) { + int lun; + u_int16_t sdf; + + if (sdp->isp_devparam[tgt].dev_enable == 0) { + continue; + } +#ifndef ISP_TARGET_MODE + sdf = sdp->isp_devparam[tgt].goal_flags; + sdf &= DPARM_SAFE_DFLT; + /* + * It is not quite clear when this changed over so that + * we could force narrow and async for 1000/1020 cards, + * but assume that this is only the case for loaded + * firmware. + */ + if (isp->isp_loaded_fw) { + sdf |= DPARM_NARROW | DPARM_ASYNC; + } +#else + /* + * The !$*!)$!$)* f/w uses the same index into some + * internal table to decide how to respond to negotiations, + * so if we've said "let's be safe" for ID X, and ID X + * selects *us*, the negotiations will back to 'safe' + * (as in narrow/async). What the f/w *should* do is + * use the initiator id settings to decide how to respond. + */ + sdp->isp_devparam[tgt].goal_flags = sdf = DPARM_DEFAULT; +#endif + mbs.param[0] = MBOX_SET_TARGET_PARAMS; + mbs.param[1] = (channel << 15) | (tgt << 8); + mbs.param[2] = sdf; + if ((sdf & DPARM_SYNC) == 0) { + mbs.param[3] = 0; + } else { + mbs.param[3] = + (sdp->isp_devparam[tgt].goal_offset << 8) | + (sdp->isp_devparam[tgt].goal_period); + } + isp_prt(isp, ISP_LOGDEBUG0, + "Initial Settings bus%d tgt%d flags 0x%x off 0x%x per 0x%x", + channel, tgt, mbs.param[2], mbs.param[3] >> 8, + mbs.param[3] & 0xff); + isp_mboxcmd(isp, &mbs, MBLOGNONE); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + sdf = DPARM_SAFE_DFLT; + mbs.param[0] = MBOX_SET_TARGET_PARAMS; + mbs.param[1] = (tgt << 8) | (channel << 15); + mbs.param[2] = sdf; + mbs.param[3] = 0; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + continue; + } + } + + /* + * We don't update any information directly from the f/w + * because we need to run at least one command to cause a + * new state to be latched up. So, we just assume that we + * converge to the values we just had set. + * + * Ensure that we don't believe tagged queuing is enabled yet. + * It turns out that sometimes the ISP just ignores our + * attempts to set parameters for devices that it hasn't + * seen yet. + */ + sdp->isp_devparam[tgt].actv_flags = sdf & ~DPARM_TQING; + for (lun = 0; lun < (int) isp->isp_maxluns; lun++) { + mbs.param[0] = MBOX_SET_DEV_QUEUE_PARAMS; + mbs.param[1] = (channel << 15) | (tgt << 8) | lun; + mbs.param[2] = sdp->isp_max_queue_depth; + mbs.param[3] = sdp->isp_devparam[tgt].exc_throttle; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + break; + } + } + } + for (tgt = 0; tgt < MAX_TARGETS; tgt++) { + if (sdp->isp_devparam[tgt].dev_refresh) { + isp->isp_sendmarker |= (1 << channel); + isp->isp_update |= (1 << channel); + break; + } + } +} + +/* + * Fibre Channel specific initialization. + * + * Locks are held before coming here. + */ +static void +isp_fibre_init(struct ispsoftc *isp) +{ + fcparam *fcp; + isp_icb_t local, *icbp = &local; + mbreg_t mbs; + int loopid; + u_int64_t nwwn, pwwn; + + fcp = isp->isp_param; + + /* + * Do this *before* initializing the firmware. + */ + isp_mark_getpdb_all(isp); + fcp->isp_fwstate = FW_CONFIG_WAIT; + fcp->isp_loopstate = LOOP_NIL; + + /* + * If we have no role (neither target nor initiator), return. + */ + if (isp->isp_role == ISP_ROLE_NONE) { + return; + } + + loopid = fcp->isp_loopid; + MEMZERO(icbp, sizeof (*icbp)); + icbp->icb_version = ICB_VERSION1; + + /* + * Firmware Options are either retrieved from NVRAM or + * are patched elsewhere. We check them for sanity here + * and make changes based on board revision, but otherwise + * let others decide policy. + */ + + /* + * If this is a 2100 < revision 5, we have to turn off FAIRNESS. + */ + if ((isp->isp_type == ISP_HA_FC_2100) && isp->isp_revision < 5) { + fcp->isp_fwoptions &= ~ICBOPT_FAIRNESS; + } + + /* + * We have to use FULL LOGIN even though it resets the loop too much + * because otherwise port database entries don't get updated after + * a LIP- this is a known f/w bug for 2100 f/w less than 1.17.0. + */ + if (!ISP_FW_NEWER_THAN(isp, 1, 17, 0)) { + fcp->isp_fwoptions |= ICBOPT_FULL_LOGIN; + } + + /* + * Insist on Port Database Update Async notifications + */ + fcp->isp_fwoptions |= ICBOPT_PDBCHANGE_AE; + + /* + * Make sure that target role reflects into fwoptions. + */ + if (isp->isp_role & ISP_ROLE_TARGET) { + fcp->isp_fwoptions |= ICBOPT_TGT_ENABLE; + } else { + fcp->isp_fwoptions &= ~ICBOPT_TGT_ENABLE; + } + + /* + * Propagate all of this into the ICB structure. + */ + icbp->icb_fwoptions = fcp->isp_fwoptions; + icbp->icb_maxfrmlen = fcp->isp_maxfrmlen; + if (icbp->icb_maxfrmlen < ICB_MIN_FRMLEN || + icbp->icb_maxfrmlen > ICB_MAX_FRMLEN) { + isp_prt(isp, ISP_LOGERR, + "bad frame length (%d) from NVRAM- using %d", + fcp->isp_maxfrmlen, ICB_DFLT_FRMLEN); + icbp->icb_maxfrmlen = ICB_DFLT_FRMLEN; + } + icbp->icb_maxalloc = fcp->isp_maxalloc; + if (icbp->icb_maxalloc < 1) { + isp_prt(isp, ISP_LOGERR, + "bad maximum allocation (%d)- using 16", fcp->isp_maxalloc); + icbp->icb_maxalloc = 16; + } + icbp->icb_execthrottle = fcp->isp_execthrottle; + if (icbp->icb_execthrottle < 1) { + isp_prt(isp, ISP_LOGERR, + "bad execution throttle of %d- using 16", + fcp->isp_execthrottle); + icbp->icb_execthrottle = ICB_DFLT_THROTTLE; + } + icbp->icb_retry_delay = fcp->isp_retry_delay; + icbp->icb_retry_count = fcp->isp_retry_count; + icbp->icb_hardaddr = loopid; + /* + * Right now we just set extended options to prefer point-to-point + * over loop based upon some soft config options. + * + * NB: for the 2300, ICBOPT_EXTENDED is required. + */ + if (IS_2200(isp) || IS_23XX(isp)) { + icbp->icb_fwoptions |= ICBOPT_EXTENDED; + /* + * Prefer or force Point-To-Point instead Loop? + */ + switch(isp->isp_confopts & ISP_CFG_PORT_PREF) { + case ISP_CFG_NPORT: + icbp->icb_xfwoptions |= ICBXOPT_PTP_2_LOOP; + break; + case ISP_CFG_NPORT_ONLY: + icbp->icb_xfwoptions |= ICBXOPT_PTP_ONLY; + break; + case ISP_CFG_LPORT_ONLY: + icbp->icb_xfwoptions |= ICBXOPT_LOOP_ONLY; + break; + default: + icbp->icb_xfwoptions |= ICBXOPT_LOOP_2_PTP; + break; + } + if (IS_23XX(isp)) { + /* + * QLogic recommends that FAST Posting be turned + * off for 23XX cards and instead allow the HBA + * to write response queue entries and interrupt + * after a delay (ZIO). + * + * If we set ZIO, it will disable fast posting, + * so we don't need to clear it in fwoptions. + */ + icbp->icb_xfwoptions |= ICBXOPT_ZIO; + + if (isp->isp_confopts & ISP_CFG_ONEGB) { + icbp->icb_zfwoptions |= ICBZOPT_RATE_ONEGB; + } else if (isp->isp_confopts & ISP_CFG_TWOGB) { + icbp->icb_zfwoptions |= ICBZOPT_RATE_TWOGB; + } else { + icbp->icb_zfwoptions |= ICBZOPT_RATE_AUTO; + } + } + } + +#ifndef ISP_NO_RIO_FC + /* + * RIO seems to be enabled in 2100s for fw >= 1.17.0. + * + * I've had some questionable problems with RIO on 2200. + * More specifically, on a 2204 I had problems with RIO + * on a Linux system where I was dropping commands right + * and left. It's not clear to me what the actual problem + * was. + * + * 23XX Cards do not support RIO. Instead they support ZIO. + */ +#if 0 + if (!IS_23XX(isp) && ISP_FW_NEWER_THAN(isp, 1, 17, 0)) { + icbp->icb_xfwoptions |= ICBXOPT_RIO_16BIT; + icbp->icb_racctimer = 4; + icbp->icb_idelaytimer = 8; + } +#endif +#endif + + /* + * For 22XX > 2.1.26 && 23XX, set someoptions. + * XXX: Probably okay for newer 2100 f/w too. + */ + if (ISP_FW_NEWER_THAN(isp, 2, 26, 0)) { + /* + * Turn on LIP F8 async event (1) + * Turn on generate AE 8013 on all LIP Resets (2) + * Disable LIP F7 switching (8) + */ + mbs.param[0] = MBOX_SET_FIRMWARE_OPTIONS; + mbs.param[1] = 0xb; + mbs.param[2] = 0; + mbs.param[3] = 0; + isp_mboxcmd(isp, &mbs, MBLOGALL); + } + icbp->icb_logintime = 30; /* 30 second login timeout */ + + if (IS_23XX(isp)) { + ISP_WRITE(isp, isp->isp_rqstinrp, 0); + ISP_WRITE(isp, isp->isp_rqstoutrp, 0); + ISP_WRITE(isp, isp->isp_respinrp, 0); + ISP_WRITE(isp, isp->isp_respoutrp, 0); + } + + nwwn = ISP_NODEWWN(isp); + pwwn = ISP_PORTWWN(isp); + if (nwwn && pwwn) { + icbp->icb_fwoptions |= ICBOPT_BOTH_WWNS; + MAKE_NODE_NAME_FROM_WWN(icbp->icb_nodename, nwwn); + MAKE_NODE_NAME_FROM_WWN(icbp->icb_portname, pwwn); + isp_prt(isp, ISP_LOGDEBUG1, + "Setting ICB Node 0x%08x%08x Port 0x%08x%08x", + ((u_int32_t) (nwwn >> 32)), + ((u_int32_t) (nwwn & 0xffffffff)), + ((u_int32_t) (pwwn >> 32)), + ((u_int32_t) (pwwn & 0xffffffff))); + } else { + isp_prt(isp, ISP_LOGDEBUG1, "Not using any WWNs"); + icbp->icb_fwoptions &= ~(ICBOPT_BOTH_WWNS|ICBOPT_FULL_LOGIN); + } + icbp->icb_rqstqlen = RQUEST_QUEUE_LEN(isp); + icbp->icb_rsltqlen = RESULT_QUEUE_LEN(isp); + icbp->icb_rqstaddr[RQRSP_ADDR0015] = DMA_WD0(isp->isp_rquest_dma); + icbp->icb_rqstaddr[RQRSP_ADDR1631] = DMA_WD1(isp->isp_rquest_dma); + icbp->icb_rqstaddr[RQRSP_ADDR3247] = DMA_WD2(isp->isp_rquest_dma); + icbp->icb_rqstaddr[RQRSP_ADDR4863] = DMA_WD3(isp->isp_rquest_dma); + icbp->icb_respaddr[RQRSP_ADDR0015] = DMA_WD0(isp->isp_result_dma); + icbp->icb_respaddr[RQRSP_ADDR1631] = DMA_WD1(isp->isp_result_dma); + icbp->icb_respaddr[RQRSP_ADDR3247] = DMA_WD2(isp->isp_result_dma); + icbp->icb_respaddr[RQRSP_ADDR4863] = DMA_WD3(isp->isp_result_dma); + isp_prt(isp, ISP_LOGDEBUG0, + "isp_fibre_init: fwopt 0x%x xfwopt 0x%x zfwopt 0x%x", + icbp->icb_fwoptions, icbp->icb_xfwoptions, icbp->icb_zfwoptions); + + FC_SCRATCH_ACQUIRE(isp); + isp_put_icb(isp, icbp, (isp_icb_t *)fcp->isp_scratch); + + /* + * Init the firmware + */ + mbs.param[0] = MBOX_INIT_FIRMWARE; + mbs.param[1] = 0; + mbs.param[2] = DMA_WD1(fcp->isp_scdma); + mbs.param[3] = DMA_WD0(fcp->isp_scdma); + mbs.param[4] = 0; + mbs.param[5] = 0; + mbs.param[6] = DMA_WD3(fcp->isp_scdma); + mbs.param[7] = DMA_WD2(fcp->isp_scdma); + isp_mboxcmd(isp, &mbs, MBLOGALL); + FC_SCRATCH_RELEASE(isp); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + return; + } + isp->isp_reqidx = isp->isp_reqodx = 0; + isp->isp_residx = 0; + isp->isp_sendmarker = 1; + + /* + * Whatever happens, we're now committed to being here. + */ + isp->isp_state = ISP_INITSTATE; +} + +/* + * Fibre Channel Support- get the port database for the id. + * + * Locks are held before coming here. Return 0 if success, + * else failure. + */ + +static int +isp_getmap(struct ispsoftc *isp, fcpos_map_t *map) +{ + fcparam *fcp = (fcparam *) isp->isp_param; + mbreg_t mbs; + + mbs.param[0] = MBOX_GET_FC_AL_POSITION_MAP; + mbs.param[1] = 0; + mbs.param[2] = DMA_WD1(fcp->isp_scdma); + mbs.param[3] = DMA_WD0(fcp->isp_scdma); + /* + * Unneeded. For the 2100, except for initializing f/w, registers + * 4/5 have to not be written to. + * mbs.param[4] = 0; + * mbs.param[5] = 0; + * + */ + mbs.param[6] = 0; + mbs.param[7] = 0; + FC_SCRATCH_ACQUIRE(isp); + isp_mboxcmd(isp, &mbs, MBLOGALL & ~MBOX_COMMAND_PARAM_ERROR); + if (mbs.param[0] == MBOX_COMMAND_COMPLETE) { + MEMCPY(map, fcp->isp_scratch, sizeof (fcpos_map_t)); + map->fwmap = mbs.param[1] != 0; + FC_SCRATCH_RELEASE(isp); + return (0); + } + FC_SCRATCH_RELEASE(isp); + return (-1); +} + +static void +isp_mark_getpdb_all(struct ispsoftc *isp) +{ + fcparam *fcp = (fcparam *) isp->isp_param; + int i; + for (i = 0; i < MAX_FC_TARG; i++) { + fcp->portdb[i].valid = fcp->portdb[i].fabric_dev = 0; + } +} + +static int +isp_getpdb(struct ispsoftc *isp, int id, isp_pdb_t *pdbp) +{ + fcparam *fcp = (fcparam *) isp->isp_param; + mbreg_t mbs; + + mbs.param[0] = MBOX_GET_PORT_DB; + mbs.param[1] = id << 8; + mbs.param[2] = DMA_WD1(fcp->isp_scdma); + mbs.param[3] = DMA_WD0(fcp->isp_scdma); + /* + * Unneeded. For the 2100, except for initializing f/w, registers + * 4/5 have to not be written to. + * mbs.param[4] = 0; + * mbs.param[5] = 0; + * + */ + mbs.param[6] = DMA_WD3(fcp->isp_scdma); + mbs.param[7] = DMA_WD2(fcp->isp_scdma); + FC_SCRATCH_ACQUIRE(isp); + isp_mboxcmd(isp, &mbs, MBLOGALL & ~MBOX_COMMAND_PARAM_ERROR); + if (mbs.param[0] == MBOX_COMMAND_COMPLETE) { + isp_get_pdb(isp, (isp_pdb_t *)fcp->isp_scratch, pdbp); + FC_SCRATCH_RELEASE(isp); + return (0); + } + FC_SCRATCH_RELEASE(isp); + return (-1); +} + +static u_int64_t +isp_get_portname(struct ispsoftc *isp, int loopid, int nodename) +{ + u_int64_t wwn = 0; + mbreg_t mbs; + + mbs.param[0] = MBOX_GET_PORT_NAME; + mbs.param[1] = loopid << 8; + if (nodename) + mbs.param[1] |= 1; + isp_mboxcmd(isp, &mbs, MBLOGALL & ~MBOX_COMMAND_PARAM_ERROR); + if (mbs.param[0] == MBOX_COMMAND_COMPLETE) { + wwn = + (((u_int64_t)(mbs.param[2] & 0xff)) << 56) | + (((u_int64_t)(mbs.param[2] >> 8)) << 48) | + (((u_int64_t)(mbs.param[3] & 0xff)) << 40) | + (((u_int64_t)(mbs.param[3] >> 8)) << 32) | + (((u_int64_t)(mbs.param[6] & 0xff)) << 24) | + (((u_int64_t)(mbs.param[6] >> 8)) << 16) | + (((u_int64_t)(mbs.param[7] & 0xff)) << 8) | + (((u_int64_t)(mbs.param[7] >> 8))); + } + return (wwn); +} + +/* + * Make sure we have good FC link and know our Loop ID. + */ + +static int +isp_fclink_test(struct ispsoftc *isp, int usdelay) +{ + static char *toponames[] = { + "Private Loop", + "FL Port", + "N-Port to N-Port", + "F Port", + "F Port (no FLOGI_ACC response)" + }; + mbreg_t mbs; + int count, check_for_fabric; + u_int8_t lwfs; + fcparam *fcp; + struct lportdb *lp; + isp_pdb_t pdb; + + fcp = isp->isp_param; + + /* + * XXX: Here is where we would start a 'loop dead' timeout + */ + + /* + * Wait up to N microseconds for F/W to go to a ready state. + */ + lwfs = FW_CONFIG_WAIT; + count = 0; + while (count < usdelay) { + u_int64_t enano; + u_int32_t wrk; + NANOTIME_T hra, hrb; + + GET_NANOTIME(&hra); + isp_fw_state(isp); + if (lwfs != fcp->isp_fwstate) { + isp_prt(isp, ISP_LOGINFO, "Firmware State <%s->%s>", + isp2100_fw_statename((int)lwfs), + isp2100_fw_statename((int)fcp->isp_fwstate)); + lwfs = fcp->isp_fwstate; + } + if (fcp->isp_fwstate == FW_READY) { + break; + } + GET_NANOTIME(&hrb); + + /* + * Get the elapsed time in nanoseconds. + * Always guaranteed to be non-zero. + */ + enano = NANOTIME_SUB(&hrb, &hra); + + isp_prt(isp, ISP_LOGDEBUG1, + "usec%d: 0x%lx->0x%lx enano 0x%x%08x", + count, (long) GET_NANOSEC(&hra), (long) GET_NANOSEC(&hrb), + (u_int32_t)(enano >> 32), (u_int32_t)(enano & 0xffffffff)); + + /* + * If the elapsed time is less than 1 millisecond, + * delay a period of time up to that millisecond of + * waiting. + * + * This peculiar code is an attempt to try and avoid + * invoking u_int64_t math support functions for some + * platforms where linkage is a problem. + */ + if (enano < (1000 * 1000)) { + count += 1000; + enano = (1000 * 1000) - enano; + while (enano > (u_int64_t) 4000000000U) { + USEC_SLEEP(isp, 4000000); + enano -= (u_int64_t) 4000000000U; + } + wrk = enano; + wrk /= 1000; + USEC_SLEEP(isp, wrk); + } else { + while (enano > (u_int64_t) 4000000000U) { + count += 4000000; + enano -= (u_int64_t) 4000000000U; + } + wrk = enano; + count += (wrk / 1000); + } + } + + /* + * If we haven't gone to 'ready' state, return. + */ + if (fcp->isp_fwstate != FW_READY) { + return (-1); + } + + /* + * Get our Loop ID (if possible). We really need to have it. + */ + mbs.param[0] = MBOX_GET_LOOP_ID; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + return (-1); + } + fcp->isp_loopid = mbs.param[1]; + if (IS_2200(isp) || IS_23XX(isp)) { + int topo = (int) mbs.param[6]; + if (topo < TOPO_NL_PORT || topo > TOPO_PTP_STUB) + topo = TOPO_PTP_STUB; + fcp->isp_topo = topo; + } else { + fcp->isp_topo = TOPO_NL_PORT; + } + fcp->isp_portid = fcp->isp_alpa = mbs.param[2] & 0xff; + + /* + * Check to see if we're on a fabric by trying to see if we + * can talk to the fabric name server. This can be a bit + * tricky because if we're a 2100, we should check always + * (in case we're connected to a server doing aliasing). + */ + fcp->isp_onfabric = 0; + + if (IS_2100(isp)) { + /* + * Don't bother with fabric if we are using really old + * 2100 firmware. It's just not worth it. + */ + if (ISP_FW_NEWER_THAN(isp, 1, 15, 37)) { + check_for_fabric = 1; + } else { + check_for_fabric = 0; + } + } else if (fcp->isp_topo == TOPO_FL_PORT || + fcp->isp_topo == TOPO_F_PORT) { + check_for_fabric = 1; + } else + check_for_fabric = 0; + + if (check_for_fabric && isp_getpdb(isp, FL_PORT_ID, &pdb) == 0) { + int loopid = FL_PORT_ID; + if (IS_2100(isp)) { + fcp->isp_topo = TOPO_FL_PORT; + } + + if (BITS2WORD(pdb.pdb_portid_bits) == 0) { + /* + * Crock. + */ + fcp->isp_topo = TOPO_NL_PORT; + goto not_on_fabric; + } + fcp->isp_portid = mbs.param[2] | ((int) mbs.param[3] << 16); + + /* + * Save the Fabric controller's port database entry. + */ + lp = &fcp->portdb[loopid]; + lp->node_wwn = + (((u_int64_t)pdb.pdb_nodename[0]) << 56) | + (((u_int64_t)pdb.pdb_nodename[1]) << 48) | + (((u_int64_t)pdb.pdb_nodename[2]) << 40) | + (((u_int64_t)pdb.pdb_nodename[3]) << 32) | + (((u_int64_t)pdb.pdb_nodename[4]) << 24) | + (((u_int64_t)pdb.pdb_nodename[5]) << 16) | + (((u_int64_t)pdb.pdb_nodename[6]) << 8) | + (((u_int64_t)pdb.pdb_nodename[7])); + lp->port_wwn = + (((u_int64_t)pdb.pdb_portname[0]) << 56) | + (((u_int64_t)pdb.pdb_portname[1]) << 48) | + (((u_int64_t)pdb.pdb_portname[2]) << 40) | + (((u_int64_t)pdb.pdb_portname[3]) << 32) | + (((u_int64_t)pdb.pdb_portname[4]) << 24) | + (((u_int64_t)pdb.pdb_portname[5]) << 16) | + (((u_int64_t)pdb.pdb_portname[6]) << 8) | + (((u_int64_t)pdb.pdb_portname[7])); + lp->roles = + (pdb.pdb_prli_svc3 & SVC3_ROLE_MASK) >> SVC3_ROLE_SHIFT; + lp->portid = BITS2WORD(pdb.pdb_portid_bits); + lp->loopid = pdb.pdb_loopid; + lp->loggedin = lp->valid = 1; + fcp->isp_onfabric = 1; + (void) isp_async(isp, ISPASYNC_PROMENADE, &loopid); + isp_register_fc4_type(isp); + } else { +not_on_fabric: + fcp->isp_onfabric = 0; + fcp->portdb[FL_PORT_ID].valid = 0; + } + + fcp->isp_gbspeed = 1; + if (IS_23XX(isp)) { + mbs.param[0] = MBOX_GET_SET_DATA_RATE; + mbs.param[1] = MBGSD_GET_RATE; + /* mbs.param[2] undefined if we're just getting rate */ + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] == MBOX_COMMAND_COMPLETE) { + if (mbs.param[1] == MBGSD_TWOGB) { + isp_prt(isp, ISP_LOGINFO, "2Gb link speed/s"); + fcp->isp_gbspeed = 2; + } + } + } + + isp_prt(isp, ISP_LOGCONFIG, topology, fcp->isp_loopid, fcp->isp_alpa, + fcp->isp_portid, fcp->isp_loopstate, toponames[fcp->isp_topo]); + + /* + * Announce ourselves, too. This involves synthesizing an entry. + */ + if (fcp->isp_iid_set == 0) { + fcp->isp_iid_set = 1; + fcp->isp_iid = fcp->isp_loopid; + lp = &fcp->portdb[fcp->isp_iid]; + } else { + lp = &fcp->portdb[fcp->isp_iid]; + if (fcp->isp_portid != lp->portid || + fcp->isp_loopid != lp->loopid || + fcp->isp_nodewwn != ISP_NODEWWN(isp) || + fcp->isp_portwwn != ISP_PORTWWN(isp)) { + lp->valid = 0; + count = fcp->isp_iid; + (void) isp_async(isp, ISPASYNC_PROMENADE, &count); + } + } + lp->loopid = fcp->isp_loopid; + lp->portid = fcp->isp_portid; + lp->node_wwn = ISP_NODEWWN(isp); + lp->port_wwn = ISP_PORTWWN(isp); + switch (isp->isp_role) { + case ISP_ROLE_NONE: + lp->roles = 0; + break; + case ISP_ROLE_TARGET: + lp->roles = SVC3_TGT_ROLE >> SVC3_ROLE_SHIFT; + break; + case ISP_ROLE_INITIATOR: + lp->roles = SVC3_INI_ROLE >> SVC3_ROLE_SHIFT; + break; + case ISP_ROLE_BOTH: + lp->roles = (SVC3_INI_ROLE|SVC3_TGT_ROLE) >> SVC3_ROLE_SHIFT; + break; + } + lp->loggedin = lp->valid = 1; + count = fcp->isp_iid; + (void) isp_async(isp, ISPASYNC_PROMENADE, &count); + return (0); +} + +static char * +isp2100_fw_statename(int state) +{ + switch(state) { + case FW_CONFIG_WAIT: return "Config Wait"; + case FW_WAIT_AL_PA: return "Waiting for AL_PA"; + case FW_WAIT_LOGIN: return "Wait Login"; + case FW_READY: return "Ready"; + case FW_LOSS_OF_SYNC: return "Loss Of Sync"; + case FW_ERROR: return "Error"; + case FW_REINIT: return "Re-Init"; + case FW_NON_PART: return "Nonparticipating"; + default: return "?????"; + } +} + +/* + * Synchronize our soft copy of the port database with what the f/w thinks + * (with a view toward possibly for a specific target....) + */ + +static int +isp_pdb_sync(struct ispsoftc *isp) +{ + struct lportdb *lp; + fcparam *fcp = isp->isp_param; + isp_pdb_t pdb; + int loopid, base, lim; + + /* + * Make sure we're okay for doing this right now. + */ + if (fcp->isp_loopstate != LOOP_PDB_RCVD && + fcp->isp_loopstate != LOOP_FSCAN_DONE && + fcp->isp_loopstate != LOOP_LSCAN_DONE) { + return (-1); + } + + if (fcp->isp_topo == TOPO_FL_PORT || fcp->isp_topo == TOPO_NL_PORT || + fcp->isp_topo == TOPO_N_PORT) { + if (fcp->isp_loopstate < LOOP_LSCAN_DONE) { + if (isp_scan_loop(isp) != 0) { + return (-1); + } + } + } + fcp->isp_loopstate = LOOP_SYNCING_PDB; + + /* + * If we get this far, we've settled our differences with the f/w + * (for local loop device) and we can say that the loop state is ready. + */ + + if (fcp->isp_topo == TOPO_NL_PORT) { + fcp->loop_seen_once = 1; + fcp->isp_loopstate = LOOP_READY; + return (0); + } + + /* + * Find all Fabric Entities that didn't make it from one scan to the + * next and let the world know they went away. Scan the whole database. + */ + for (lp = &fcp->portdb[0]; lp < &fcp->portdb[MAX_FC_TARG]; lp++) { + if (lp->was_fabric_dev && lp->fabric_dev == 0) { + loopid = lp - fcp->portdb; + lp->valid = 0; /* should already be set */ + (void) isp_async(isp, ISPASYNC_PROMENADE, &loopid); + MEMZERO((void *) lp, sizeof (*lp)); + continue; + } + lp->was_fabric_dev = lp->fabric_dev; + } + + if (fcp->isp_topo == TOPO_FL_PORT) + base = FC_SNS_ID+1; + else + base = 0; + + if (fcp->isp_topo == TOPO_N_PORT) + lim = 1; + else + lim = MAX_FC_TARG; + + /* + * Now log in any fabric devices that the outer layer has + * left for us to see. This seems the most sane policy + * for the moment. + */ + for (lp = &fcp->portdb[base]; lp < &fcp->portdb[lim]; lp++) { + u_int32_t portid; + mbreg_t mbs; + + loopid = lp - fcp->portdb; + if (loopid >= FL_PORT_ID && loopid <= FC_SNS_ID) { + continue; + } + + /* + * Anything here? + */ + if (lp->port_wwn == 0) { + continue; + } + + /* + * Don't try to log into yourself. + */ + if ((portid = lp->portid) == fcp->isp_portid) { + continue; + } + + + /* + * If we'd been logged in- see if we still are and we haven't + * changed. If so, no need to log ourselves out, etc.. + * + * Unfortunately, our charming Qlogic f/w has decided to + * return a valid port database entry for a fabric device + * that has, in fact, gone away. And it hangs trying to + * log it out. + */ + if (lp->loggedin && lp->force_logout == 0 && + isp_getpdb(isp, lp->loopid, &pdb) == 0) { + int nrole; + u_int64_t nwwnn, nwwpn; + nwwnn = + (((u_int64_t)pdb.pdb_nodename[0]) << 56) | + (((u_int64_t)pdb.pdb_nodename[1]) << 48) | + (((u_int64_t)pdb.pdb_nodename[2]) << 40) | + (((u_int64_t)pdb.pdb_nodename[3]) << 32) | + (((u_int64_t)pdb.pdb_nodename[4]) << 24) | + (((u_int64_t)pdb.pdb_nodename[5]) << 16) | + (((u_int64_t)pdb.pdb_nodename[6]) << 8) | + (((u_int64_t)pdb.pdb_nodename[7])); + nwwpn = + (((u_int64_t)pdb.pdb_portname[0]) << 56) | + (((u_int64_t)pdb.pdb_portname[1]) << 48) | + (((u_int64_t)pdb.pdb_portname[2]) << 40) | + (((u_int64_t)pdb.pdb_portname[3]) << 32) | + (((u_int64_t)pdb.pdb_portname[4]) << 24) | + (((u_int64_t)pdb.pdb_portname[5]) << 16) | + (((u_int64_t)pdb.pdb_portname[6]) << 8) | + (((u_int64_t)pdb.pdb_portname[7])); + nrole = (pdb.pdb_prli_svc3 & SVC3_ROLE_MASK) >> + SVC3_ROLE_SHIFT; + if (pdb.pdb_loopid == lp->loopid && lp->portid == + (u_int32_t) BITS2WORD(pdb.pdb_portid_bits) && + nwwnn == lp->node_wwn && nwwpn == lp->port_wwn && + lp->roles == nrole && lp->force_logout == 0) { + lp->loggedin = lp->valid = 1; + isp_prt(isp, ISP_LOGCONFIG, lretained, + (int) (lp - fcp->portdb), + (int) lp->loopid, lp->portid); + continue; + } + } + + if (fcp->isp_fwstate != FW_READY || + fcp->isp_loopstate != LOOP_SYNCING_PDB) { + return (-1); + } + + /* + * Force a logout if we were logged in. + */ + if (lp->loggedin) { + if (lp->force_logout || + isp_getpdb(isp, lp->loopid, &pdb) == 0) { + mbs.param[0] = MBOX_FABRIC_LOGOUT; + mbs.param[1] = lp->loopid << 8; + mbs.param[2] = 0; + mbs.param[3] = 0; + isp_mboxcmd(isp, &mbs, MBLOGNONE); + isp_prt(isp, ISP_LOGINFO, plogout, + (int) (lp - fcp->portdb), lp->loopid, + lp->portid); + } + lp->force_logout = lp->loggedin = 0; + if (fcp->isp_fwstate != FW_READY || + fcp->isp_loopstate != LOOP_SYNCING_PDB) { + return (-1); + } + } + + /* + * And log in.... + */ + loopid = lp - fcp->portdb; + lp->loopid = FL_PORT_ID; + do { + mbs.param[0] = MBOX_FABRIC_LOGIN; + mbs.param[1] = loopid << 8; + mbs.param[2] = portid >> 16; + mbs.param[3] = portid & 0xffff; + isp_mboxcmd(isp, &mbs, MBLOGALL & ~(MBOX_LOOP_ID_USED | + MBOX_PORT_ID_USED | MBOX_COMMAND_ERROR)); + if (fcp->isp_fwstate != FW_READY || + fcp->isp_loopstate != LOOP_SYNCING_PDB) { + return (-1); + } + switch (mbs.param[0]) { + case MBOX_LOOP_ID_USED: + /* + * Try the next available loop id. + */ + loopid++; + break; + case MBOX_PORT_ID_USED: + /* + * This port is already logged in. + * Snaffle the loop id it's using if it's + * nonzero, otherwise we're hosed. + */ + if (mbs.param[1] != 0) { + loopid = mbs.param[1]; + isp_prt(isp, ISP_LOGINFO, retained, + loopid, (int) (lp - fcp->portdb), + lp->portid); + } else { + loopid = MAX_FC_TARG; + break; + } + /* FALLTHROUGH */ + case MBOX_COMMAND_COMPLETE: + lp->loggedin = 1; + lp->loopid = loopid; + break; + case MBOX_COMMAND_ERROR: + isp_prt(isp, ISP_LOGINFO, plogierr, + portid, mbs.param[1]); + /* FALLTHROUGH */ + case MBOX_ALL_IDS_USED: /* We're outta IDs */ + default: + loopid = MAX_FC_TARG; + break; + } + } while (lp->loopid == FL_PORT_ID && loopid < MAX_FC_TARG); + + /* + * If we get here and we haven't set a Loop ID, + * we failed to log into this device. + */ + + if (lp->loopid == FL_PORT_ID) { + lp->loopid = 0; + continue; + } + + /* + * Make sure we can get the approriate port information. + */ + if (isp_getpdb(isp, lp->loopid, &pdb) != 0) { + isp_prt(isp, ISP_LOGWARN, nopdb, lp->portid); + goto dump_em; + } + + if (fcp->isp_fwstate != FW_READY || + fcp->isp_loopstate != LOOP_SYNCING_PDB) { + return (-1); + } + + if (pdb.pdb_loopid != lp->loopid) { + isp_prt(isp, ISP_LOGWARN, pdbmfail1, + lp->portid, pdb.pdb_loopid); + goto dump_em; + } + + if (lp->portid != (u_int32_t) BITS2WORD(pdb.pdb_portid_bits)) { + isp_prt(isp, ISP_LOGWARN, pdbmfail2, + lp->portid, BITS2WORD(pdb.pdb_portid_bits)); + goto dump_em; + } + + lp->roles = + (pdb.pdb_prli_svc3 & SVC3_ROLE_MASK) >> SVC3_ROLE_SHIFT; + lp->node_wwn = + (((u_int64_t)pdb.pdb_nodename[0]) << 56) | + (((u_int64_t)pdb.pdb_nodename[1]) << 48) | + (((u_int64_t)pdb.pdb_nodename[2]) << 40) | + (((u_int64_t)pdb.pdb_nodename[3]) << 32) | + (((u_int64_t)pdb.pdb_nodename[4]) << 24) | + (((u_int64_t)pdb.pdb_nodename[5]) << 16) | + (((u_int64_t)pdb.pdb_nodename[6]) << 8) | + (((u_int64_t)pdb.pdb_nodename[7])); + lp->port_wwn = + (((u_int64_t)pdb.pdb_portname[0]) << 56) | + (((u_int64_t)pdb.pdb_portname[1]) << 48) | + (((u_int64_t)pdb.pdb_portname[2]) << 40) | + (((u_int64_t)pdb.pdb_portname[3]) << 32) | + (((u_int64_t)pdb.pdb_portname[4]) << 24) | + (((u_int64_t)pdb.pdb_portname[5]) << 16) | + (((u_int64_t)pdb.pdb_portname[6]) << 8) | + (((u_int64_t)pdb.pdb_portname[7])); + /* + * Check to make sure this all makes sense. + */ + if (lp->node_wwn && lp->port_wwn) { + lp->valid = 1; + loopid = lp - fcp->portdb; + (void) isp_async(isp, ISPASYNC_PROMENADE, &loopid); + continue; + } +dump_em: + lp->valid = 0; + isp_prt(isp, ISP_LOGINFO, + ldumped, loopid, lp->loopid, lp->portid); + mbs.param[0] = MBOX_FABRIC_LOGOUT; + mbs.param[1] = lp->loopid << 8; + mbs.param[2] = 0; + mbs.param[3] = 0; + isp_mboxcmd(isp, &mbs, MBLOGNONE); + if (fcp->isp_fwstate != FW_READY || + fcp->isp_loopstate != LOOP_SYNCING_PDB) { + return (-1); + } + } + /* + * If we get here, we've for sure seen not only a valid loop + * but know what is or isn't on it, so mark this for usage + * in isp_start. + */ + fcp->loop_seen_once = 1; + fcp->isp_loopstate = LOOP_READY; + return (0); +} + +static int +isp_scan_loop(struct ispsoftc *isp) +{ + struct lportdb *lp; + fcparam *fcp = isp->isp_param; + isp_pdb_t pdb; + int loopid, lim, hival; + + switch (fcp->isp_topo) { + case TOPO_NL_PORT: + hival = FL_PORT_ID; + break; + case TOPO_N_PORT: + hival = 2; + break; + case TOPO_FL_PORT: + hival = FC_PORT_ID; + break; + default: + fcp->isp_loopstate = LOOP_LSCAN_DONE; + return (0); + } + fcp->isp_loopstate = LOOP_SCANNING_LOOP; + + /* + * make sure the temp port database is clean... + */ + MEMZERO((void *)fcp->tport, sizeof (fcp->tport)); + + /* + * Run through the local loop ports and get port database info + * for each loop ID. + * + * There's a somewhat unexplained situation where the f/w passes back + * the wrong database entity- if that happens, just restart (up to + * FL_PORT_ID times). + */ + for (lim = loopid = 0; loopid < hival; loopid++) { + lp = &fcp->tport[loopid]; + + /* + * Don't even try for ourselves... + */ + if (loopid == fcp->isp_loopid) + continue; + + lp->node_wwn = isp_get_portname(isp, loopid, 1); + if (fcp->isp_loopstate < LOOP_SCANNING_LOOP) + return (-1); + if (lp->node_wwn == 0) + continue; + lp->port_wwn = isp_get_portname(isp, loopid, 0); + if (fcp->isp_loopstate < LOOP_SCANNING_LOOP) + return (-1); + if (lp->port_wwn == 0) { + lp->node_wwn = 0; + continue; + } + + /* + * Get an entry.... + */ + if (isp_getpdb(isp, loopid, &pdb) != 0) { + if (fcp->isp_loopstate < LOOP_SCANNING_LOOP) + return (-1); + continue; + } + if (fcp->isp_loopstate < LOOP_SCANNING_LOOP) { + return (-1); + } + + /* + * If the returned database element doesn't match what we + * asked for, restart the process entirely (up to a point...). + */ + if (pdb.pdb_loopid != loopid) { + loopid = 0; + if (lim++ < hival) { + continue; + } + isp_prt(isp, ISP_LOGWARN, + "giving up on synchronizing the port database"); + return (-1); + } + + /* + * Save the pertinent info locally. + */ + lp->node_wwn = + (((u_int64_t)pdb.pdb_nodename[0]) << 56) | + (((u_int64_t)pdb.pdb_nodename[1]) << 48) | + (((u_int64_t)pdb.pdb_nodename[2]) << 40) | + (((u_int64_t)pdb.pdb_nodename[3]) << 32) | + (((u_int64_t)pdb.pdb_nodename[4]) << 24) | + (((u_int64_t)pdb.pdb_nodename[5]) << 16) | + (((u_int64_t)pdb.pdb_nodename[6]) << 8) | + (((u_int64_t)pdb.pdb_nodename[7])); + lp->port_wwn = + (((u_int64_t)pdb.pdb_portname[0]) << 56) | + (((u_int64_t)pdb.pdb_portname[1]) << 48) | + (((u_int64_t)pdb.pdb_portname[2]) << 40) | + (((u_int64_t)pdb.pdb_portname[3]) << 32) | + (((u_int64_t)pdb.pdb_portname[4]) << 24) | + (((u_int64_t)pdb.pdb_portname[5]) << 16) | + (((u_int64_t)pdb.pdb_portname[6]) << 8) | + (((u_int64_t)pdb.pdb_portname[7])); + lp->roles = + (pdb.pdb_prli_svc3 & SVC3_ROLE_MASK) >> SVC3_ROLE_SHIFT; + lp->portid = BITS2WORD(pdb.pdb_portid_bits); + lp->loopid = pdb.pdb_loopid; + } + + /* + * Mark all of the permanent local loop database entries as invalid + * (except our own entry). + */ + for (loopid = 0; loopid < hival; loopid++) { + if (loopid == fcp->isp_iid) { + fcp->portdb[loopid].valid = 1; + fcp->portdb[loopid].loopid = fcp->isp_loopid; + continue; + } + fcp->portdb[loopid].valid = 0; + } + + /* + * Now merge our local copy of the port database into our saved copy. + * Notify the outer layers of new devices arriving. + */ + for (loopid = 0; loopid < hival; loopid++) { + int i; + + /* + * If we don't have a non-zero Port WWN, we're not here. + */ + if (fcp->tport[loopid].port_wwn == 0) { + continue; + } + + /* + * Skip ourselves. + */ + if (loopid == fcp->isp_iid) { + continue; + } + + /* + * For the purposes of deciding whether this is the + * 'same' device or not, we only search for an identical + * Port WWN. Node WWNs may or may not be the same as + * the Port WWN, and there may be multiple different + * Port WWNs with the same Node WWN. It would be chaos + * to have multiple identical Port WWNs, so we don't + * allow that. + */ + + for (i = 0; i < hival; i++) { + int j; + if (fcp->portdb[i].port_wwn == 0) + continue; + if (fcp->portdb[i].port_wwn != + fcp->tport[loopid].port_wwn) + continue; + /* + * We found this WWN elsewhere- it's changed + * loopids then. We don't change it's actual + * position in our cached port database- we + * just change the actual loop ID we'd use. + */ + if (fcp->portdb[i].loopid != loopid) { + isp_prt(isp, ISP_LOGINFO, portshift, i, + fcp->portdb[i].loopid, + fcp->portdb[i].portid, loopid, + fcp->tport[loopid].portid); + } + fcp->portdb[i].portid = fcp->tport[loopid].portid; + fcp->portdb[i].loopid = loopid; + fcp->portdb[i].valid = 1; + fcp->portdb[i].roles = fcp->tport[loopid].roles; + + /* + * Now make sure this Port WWN doesn't exist elsewhere + * in the port database. + */ + for (j = i+1; j < hival; j++) { + if (fcp->portdb[i].port_wwn != + fcp->portdb[j].port_wwn) { + continue; + } + isp_prt(isp, ISP_LOGWARN, portdup, j, i); + /* + * Invalidate the 'old' *and* 'new' ones. + * This is really harsh and not quite right, + * but if this happens, we really don't know + * who is what at this point. + */ + fcp->portdb[i].valid = 0; + fcp->portdb[j].valid = 0; + } + break; + } + + /* + * If we didn't traverse the entire port database, + * then we found (and remapped) an existing entry. + * No need to notify anyone- go for the next one. + */ + if (i < hival) { + isp_prt(isp, ISP_LOGINFO, retained, + fcp->portdb[i].loopid, i, fcp->portdb[i].portid); + continue; + } + + /* + * We've not found this Port WWN anywhere. It's a new entry. + * See if we can leave it where it is (with target == loopid). + */ + if (fcp->portdb[loopid].port_wwn != 0) { + for (lim = 0; lim < hival; lim++) { + if (fcp->portdb[lim].port_wwn == 0) + break; + } + /* "Cannot Happen" */ + if (lim == hival) { + isp_prt(isp, ISP_LOGWARN, "Remap Overflow"); + continue; + } + i = lim; + } else { + i = loopid; + } + + /* + * NB: The actual loopid we use here is loopid- we may + * in fact be at a completely different index (target). + */ + fcp->portdb[i].loopid = loopid; + fcp->portdb[i].port_wwn = fcp->tport[loopid].port_wwn; + fcp->portdb[i].node_wwn = fcp->tport[loopid].node_wwn; + fcp->portdb[i].roles = fcp->tport[loopid].roles; + fcp->portdb[i].portid = fcp->tport[loopid].portid; + fcp->portdb[i].valid = 1; + + /* + * Tell the outside world we've arrived. + */ + (void) isp_async(isp, ISPASYNC_PROMENADE, &i); + } + + /* + * Now find all previously used targets that are now invalid and + * notify the outer layers that they're gone. + */ + for (lp = &fcp->portdb[0]; lp < &fcp->portdb[hival]; lp++) { + if (lp->valid || lp->port_wwn == 0) { + continue; + } + + /* + * Tell the outside world we've gone + * away and erase our pdb entry. + * + */ + loopid = lp - fcp->portdb; + (void) isp_async(isp, ISPASYNC_PROMENADE, &loopid); + MEMZERO((void *) lp, sizeof (*lp)); + } + fcp->isp_loopstate = LOOP_LSCAN_DONE; + return (0); +} + + +static int +isp_fabric_mbox_cmd(struct ispsoftc *isp, mbreg_t *mbp) +{ + isp_mboxcmd(isp, mbp, MBLOGNONE); + if (mbp->param[0] != MBOX_COMMAND_COMPLETE) { + if (FCPARAM(isp)->isp_loopstate == LOOP_SCANNING_FABRIC) { + FCPARAM(isp)->isp_loopstate = LOOP_PDB_RCVD; + } + if (mbp->param[0] == MBOX_COMMAND_ERROR) { + char tbuf[16]; + char *m; + switch (mbp->param[1]) { + case 1: + m = "No Loop"; + break; + case 2: + m = "Failed to allocate IOCB buffer"; + break; + case 3: + m = "Failed to allocate XCB buffer"; + break; + case 4: + m = "timeout or transmit failed"; + break; + case 5: + m = "no fabric loop"; + break; + case 6: + m = "remote device not a target"; + break; + default: + SNPRINTF(tbuf, sizeof tbuf, "%x", + mbp->param[1]); + m = tbuf; + break; + } + isp_prt(isp, ISP_LOGERR, "SNS Failed- %s", m); + } + return (-1); + } + + if (FCPARAM(isp)->isp_fwstate != FW_READY || + FCPARAM(isp)->isp_loopstate < LOOP_SCANNING_FABRIC) { + return (-1); + } + return(0); +} + +#ifdef ISP_USE_GA_NXT +static int +isp_scan_fabric(struct ispsoftc *isp, int ftype) +{ + fcparam *fcp = isp->isp_param; + u_int32_t portid, first_portid, last_portid; + int hicap, last_port_same; + + if (fcp->isp_onfabric == 0) { + fcp->isp_loopstate = LOOP_FSCAN_DONE; + return (0); + } + + FC_SCRATCH_ACQUIRE(isp); + + /* + * Since Port IDs are 24 bits, we can check against having seen + * anything yet with this value. + */ + last_port_same = 0; + last_portid = 0xffffffff; /* not a port */ + first_portid = portid = fcp->isp_portid; + fcp->isp_loopstate = LOOP_SCANNING_FABRIC; + + for (hicap = 0; hicap < GA_NXT_MAX; hicap++) { + mbreg_t mbs; + sns_screq_t *rq; + sns_ga_nxt_rsp_t *rs0, *rs1; + struct lportdb lcl; + u_int8_t sc[SNS_GA_NXT_RESP_SIZE]; + + rq = (sns_screq_t *)sc; + MEMZERO((void *) rq, SNS_GA_NXT_REQ_SIZE); + rq->snscb_rblen = SNS_GA_NXT_RESP_SIZE >> 1; + rq->snscb_addr[RQRSP_ADDR0015] = DMA_WD0(fcp->isp_scdma+0x100); + rq->snscb_addr[RQRSP_ADDR1631] = DMA_WD1(fcp->isp_scdma+0x100); + rq->snscb_addr[RQRSP_ADDR3247] = DMA_WD2(fcp->isp_scdma+0x100); + rq->snscb_addr[RQRSP_ADDR4863] = DMA_WD3(fcp->isp_scdma+0x100); + rq->snscb_sblen = 6; + rq->snscb_data[0] = SNS_GA_NXT; + rq->snscb_data[4] = portid & 0xffff; + rq->snscb_data[5] = (portid >> 16) & 0xff; + isp_put_sns_request(isp, rq, (sns_screq_t *) fcp->isp_scratch); + MEMORYBARRIER(isp, SYNC_SFORDEV, 0, SNS_GA_NXT_REQ_SIZE); + mbs.param[0] = MBOX_SEND_SNS; + mbs.param[1] = SNS_GA_NXT_REQ_SIZE >> 1; + mbs.param[2] = DMA_WD1(fcp->isp_scdma); + mbs.param[3] = DMA_WD0(fcp->isp_scdma); + /* + * Leave 4 and 5 alone + */ + mbs.param[6] = DMA_WD3(fcp->isp_scdma); + mbs.param[7] = DMA_WD2(fcp->isp_scdma); + if (isp_fabric_mbox_cmd(isp, &mbs)) { + if (fcp->isp_loopstate >= LOOP_SCANNING_FABRIC) { + fcp->isp_loopstate = LOOP_PDB_RCVD; + } + FC_SCRATCH_RELEASE(isp); + return (-1); + } + MEMORYBARRIER(isp, SYNC_SFORCPU, 0x100, SNS_GA_NXT_RESP_SIZE); + rs1 = (sns_ga_nxt_rsp_t *) sc; + rs0 = (sns_ga_nxt_rsp_t *) ((u_int8_t *)fcp->isp_scratch+0x100); + isp_get_ga_nxt_response(isp, rs0, rs1); + if (rs1->snscb_cthdr.ct_response != FS_ACC) { + int level; + if (rs1->snscb_cthdr.ct_reason == 9 && + rs1->snscb_cthdr.ct_explanation == 7) + level = ISP_LOGDEBUG0; + else + level = ISP_LOGWARN; + isp_prt(isp, level, swrej, "GA_NXT", + rs1->snscb_cthdr.ct_reason, + rs1->snscb_cthdr.ct_explanation, portid); + FC_SCRATCH_RELEASE(isp); + fcp->isp_loopstate = LOOP_FSCAN_DONE; + return (0); + } + portid = + (((u_int32_t) rs1->snscb_port_id[0]) << 16) | + (((u_int32_t) rs1->snscb_port_id[1]) << 8) | + (((u_int32_t) rs1->snscb_port_id[2])); + + /* + * XXX: We should check to make sure that this entry + * XXX: supports the type(s) we are interested in. + */ + /* + * Okay, we now have information about a fabric object. + * If it is the type we're interested in, tell the outer layers + * about it. The outer layer needs to know: Port ID, WWNN, + * WWPN, FC4 type, and port type. + * + * The lportdb structure is adequate for this. + */ + MEMZERO(&lcl, sizeof (lcl)); + lcl.port_type = rs1->snscb_port_type; + lcl.fc4_type = ftype; + lcl.portid = portid; + lcl.node_wwn = + (((u_int64_t)rs1->snscb_nodename[0]) << 56) | + (((u_int64_t)rs1->snscb_nodename[1]) << 48) | + (((u_int64_t)rs1->snscb_nodename[2]) << 40) | + (((u_int64_t)rs1->snscb_nodename[3]) << 32) | + (((u_int64_t)rs1->snscb_nodename[4]) << 24) | + (((u_int64_t)rs1->snscb_nodename[5]) << 16) | + (((u_int64_t)rs1->snscb_nodename[6]) << 8) | + (((u_int64_t)rs1->snscb_nodename[7])); + lcl.port_wwn = + (((u_int64_t)rs1->snscb_portname[0]) << 56) | + (((u_int64_t)rs1->snscb_portname[1]) << 48) | + (((u_int64_t)rs1->snscb_portname[2]) << 40) | + (((u_int64_t)rs1->snscb_portname[3]) << 32) | + (((u_int64_t)rs1->snscb_portname[4]) << 24) | + (((u_int64_t)rs1->snscb_portname[5]) << 16) | + (((u_int64_t)rs1->snscb_portname[6]) << 8) | + (((u_int64_t)rs1->snscb_portname[7])); + + /* + * Does this fabric object support the type we want? + * If not, skip it. + */ + if (rs1->snscb_fc4_types[ftype >> 5] & (1 << (ftype & 0x1f))) { + if (first_portid == portid) { + lcl.last_fabric_dev = 1; + } else { + lcl.last_fabric_dev = 0; + } + (void) isp_async(isp, ISPASYNC_FABRIC_DEV, &lcl); + } else { + isp_prt(isp, ISP_LOGDEBUG0, + "PortID 0x%x doesn't support FC4 type 0x%x", + portid, ftype); + } + if (first_portid == portid) { + fcp->isp_loopstate = LOOP_FSCAN_DONE; + FC_SCRATCH_RELEASE(isp); + return (0); + } + if (portid == last_portid) { + if (last_port_same++ > 20) { + isp_prt(isp, ISP_LOGWARN, + "tangled fabric database detected"); + break; + } + } else { + last_port_same = 0 ; + last_portid = portid; + } + } + FC_SCRATCH_RELEASE(isp); + if (hicap >= GA_NXT_MAX) { + isp_prt(isp, ISP_LOGWARN, "fabric too big (> %d)", GA_NXT_MAX); + } + fcp->isp_loopstate = LOOP_FSCAN_DONE; + return (0); +} +#else +#define GIDLEN ((ISP2100_SCRLEN >> 1) + 16) +#define NGENT ((GIDLEN - 16) >> 2) + +#define IGPOFF (ISP2100_SCRLEN - GIDLEN) +#define GXOFF (256) + +static int +isp_scan_fabric(struct ispsoftc *isp, int ftype) +{ + fcparam *fcp = FCPARAM(isp); + mbreg_t mbs; + int i; + sns_gid_ft_req_t *rq; + sns_gid_ft_rsp_t *rs0, *rs1; + + if (fcp->isp_onfabric == 0) { + fcp->isp_loopstate = LOOP_FSCAN_DONE; + return (0); + } + + FC_SCRATCH_ACQUIRE(isp); + fcp->isp_loopstate = LOOP_SCANNING_FABRIC; + + rq = (sns_gid_ft_req_t *)fcp->tport; + MEMZERO((void *) rq, SNS_GID_FT_REQ_SIZE); + rq->snscb_rblen = GIDLEN >> 1; + rq->snscb_addr[RQRSP_ADDR0015] = DMA_WD0(fcp->isp_scdma+IGPOFF); + rq->snscb_addr[RQRSP_ADDR1631] = DMA_WD1(fcp->isp_scdma+IGPOFF); + rq->snscb_addr[RQRSP_ADDR3247] = DMA_WD2(fcp->isp_scdma+IGPOFF); + rq->snscb_addr[RQRSP_ADDR4863] = DMA_WD3(fcp->isp_scdma+IGPOFF); + rq->snscb_sblen = 6; + rq->snscb_cmd = SNS_GID_FT; + rq->snscb_mword_div_2 = NGENT; + rq->snscb_fc4_type = ftype; + isp_put_gid_ft_request(isp, rq, (sns_gid_ft_req_t *) fcp->isp_scratch); + MEMORYBARRIER(isp, SYNC_SFORDEV, 0, SNS_GID_FT_REQ_SIZE); + mbs.param[0] = MBOX_SEND_SNS; + mbs.param[1] = SNS_GID_FT_REQ_SIZE >> 1; + mbs.param[2] = DMA_WD1(fcp->isp_scdma); + mbs.param[3] = DMA_WD0(fcp->isp_scdma); + + /* + * Leave 4 and 5 alone + */ + mbs.param[6] = DMA_WD3(fcp->isp_scdma); + mbs.param[7] = DMA_WD2(fcp->isp_scdma); + if (isp_fabric_mbox_cmd(isp, &mbs)) { + if (fcp->isp_loopstate >= LOOP_SCANNING_FABRIC) { + fcp->isp_loopstate = LOOP_PDB_RCVD; + } + FC_SCRATCH_RELEASE(isp); + return (-1); + } + if (fcp->isp_loopstate != LOOP_SCANNING_FABRIC) { + FC_SCRATCH_RELEASE(isp); + return (-1); + } + MEMORYBARRIER(isp, SYNC_SFORCPU, IGPOFF, GIDLEN); + rs1 = (sns_gid_ft_rsp_t *) fcp->tport; + rs0 = (sns_gid_ft_rsp_t *) ((u_int8_t *)fcp->isp_scratch+IGPOFF); + isp_get_gid_ft_response(isp, rs0, rs1, NGENT); + if (rs1->snscb_cthdr.ct_response != FS_ACC) { + int level; + if (rs1->snscb_cthdr.ct_reason == 9 && + rs1->snscb_cthdr.ct_explanation == 7) + level = ISP_LOGDEBUG0; + else + level = ISP_LOGWARN; + isp_prt(isp, level, swrej, "GID_FT", + rs1->snscb_cthdr.ct_reason, + rs1->snscb_cthdr.ct_explanation, 0); + FC_SCRATCH_RELEASE(isp); + fcp->isp_loopstate = LOOP_FSCAN_DONE; + return (0); + } + + /* + * Okay, we now have a list of Port IDs for this class of device. + * Go through the list and for each one get the WWPN/WWNN for it + * and tell the outer layers about it. The outer layer needs to + * know: Port ID, WWNN, WWPN, FC4 type, and (possibly) port type. + * + * The lportdb structure is adequate for this. + */ + i = -1; + do { + sns_gxn_id_req_t grqbuf, *gq = &grqbuf; + sns_gxn_id_rsp_t *gs0, grsbuf, *gs1 = &grsbuf; + struct lportdb lcl; +#if 0 + sns_gff_id_rsp_t *fs0, ffsbuf, *fs1 = &ffsbuf; +#endif + + i++; + MEMZERO(&lcl, sizeof (lcl)); + lcl.fc4_type = ftype; + lcl.portid = + (((u_int32_t) rs1->snscb_ports[i].portid[0]) << 16) | + (((u_int32_t) rs1->snscb_ports[i].portid[1]) << 8) | + (((u_int32_t) rs1->snscb_ports[i].portid[2])); + + MEMZERO((void *) gq, sizeof (sns_gxn_id_req_t)); + gq->snscb_rblen = SNS_GXN_ID_RESP_SIZE >> 1; + gq->snscb_addr[RQRSP_ADDR0015] = DMA_WD0(fcp->isp_scdma+GXOFF); + gq->snscb_addr[RQRSP_ADDR1631] = DMA_WD1(fcp->isp_scdma+GXOFF); + gq->snscb_addr[RQRSP_ADDR3247] = DMA_WD2(fcp->isp_scdma+GXOFF); + gq->snscb_addr[RQRSP_ADDR4863] = DMA_WD3(fcp->isp_scdma+GXOFF); + gq->snscb_sblen = 6; + gq->snscb_cmd = SNS_GPN_ID; + gq->snscb_portid = lcl.portid; + isp_put_gxn_id_request(isp, gq, + (sns_gxn_id_req_t *) fcp->isp_scratch); + MEMORYBARRIER(isp, SYNC_SFORDEV, 0, SNS_GXN_ID_REQ_SIZE); + mbs.param[0] = MBOX_SEND_SNS; + mbs.param[1] = SNS_GXN_ID_REQ_SIZE >> 1; + mbs.param[2] = DMA_WD1(fcp->isp_scdma); + mbs.param[3] = DMA_WD0(fcp->isp_scdma); + /* + * Leave 4 and 5 alone + */ + mbs.param[6] = DMA_WD3(fcp->isp_scdma); + mbs.param[7] = DMA_WD2(fcp->isp_scdma); + if (isp_fabric_mbox_cmd(isp, &mbs)) { + if (fcp->isp_loopstate >= LOOP_SCANNING_FABRIC) { + fcp->isp_loopstate = LOOP_PDB_RCVD; + } + FC_SCRATCH_RELEASE(isp); + return (-1); + } + if (fcp->isp_loopstate != LOOP_SCANNING_FABRIC) { + FC_SCRATCH_RELEASE(isp); + return (-1); + } + MEMORYBARRIER(isp, SYNC_SFORCPU, GXOFF, SNS_GXN_ID_RESP_SIZE); + gs0 = (sns_gxn_id_rsp_t *) ((u_int8_t *)fcp->isp_scratch+GXOFF); + isp_get_gxn_id_response(isp, gs0, gs1); + if (gs1->snscb_cthdr.ct_response != FS_ACC) { + isp_prt(isp, ISP_LOGWARN, swrej, "GPN_ID", + gs1->snscb_cthdr.ct_reason, + gs1->snscb_cthdr.ct_explanation, lcl.portid); + if (fcp->isp_loopstate != LOOP_SCANNING_FABRIC) { + FC_SCRATCH_RELEASE(isp); + return (-1); + } + continue; + } + lcl.port_wwn = + (((u_int64_t)gs1->snscb_wwn[0]) << 56) | + (((u_int64_t)gs1->snscb_wwn[1]) << 48) | + (((u_int64_t)gs1->snscb_wwn[2]) << 40) | + (((u_int64_t)gs1->snscb_wwn[3]) << 32) | + (((u_int64_t)gs1->snscb_wwn[4]) << 24) | + (((u_int64_t)gs1->snscb_wwn[5]) << 16) | + (((u_int64_t)gs1->snscb_wwn[6]) << 8) | + (((u_int64_t)gs1->snscb_wwn[7])); + + MEMZERO((void *) gq, sizeof (sns_gxn_id_req_t)); + gq->snscb_rblen = SNS_GXN_ID_RESP_SIZE >> 1; + gq->snscb_addr[RQRSP_ADDR0015] = DMA_WD0(fcp->isp_scdma+GXOFF); + gq->snscb_addr[RQRSP_ADDR1631] = DMA_WD1(fcp->isp_scdma+GXOFF); + gq->snscb_addr[RQRSP_ADDR3247] = DMA_WD2(fcp->isp_scdma+GXOFF); + gq->snscb_addr[RQRSP_ADDR4863] = DMA_WD3(fcp->isp_scdma+GXOFF); + gq->snscb_sblen = 6; + gq->snscb_cmd = SNS_GNN_ID; + gq->snscb_portid = lcl.portid; + isp_put_gxn_id_request(isp, gq, + (sns_gxn_id_req_t *) fcp->isp_scratch); + MEMORYBARRIER(isp, SYNC_SFORDEV, 0, SNS_GXN_ID_REQ_SIZE); + mbs.param[0] = MBOX_SEND_SNS; + mbs.param[1] = SNS_GXN_ID_REQ_SIZE >> 1; + mbs.param[2] = DMA_WD1(fcp->isp_scdma); + mbs.param[3] = DMA_WD0(fcp->isp_scdma); + /* + * Leave 4 and 5 alone + */ + mbs.param[6] = DMA_WD3(fcp->isp_scdma); + mbs.param[7] = DMA_WD2(fcp->isp_scdma); + if (isp_fabric_mbox_cmd(isp, &mbs)) { + if (fcp->isp_loopstate >= LOOP_SCANNING_FABRIC) { + fcp->isp_loopstate = LOOP_PDB_RCVD; + } + FC_SCRATCH_RELEASE(isp); + return (-1); + } + if (fcp->isp_loopstate != LOOP_SCANNING_FABRIC) { + FC_SCRATCH_RELEASE(isp); + return (-1); + } + MEMORYBARRIER(isp, SYNC_SFORCPU, GXOFF, SNS_GXN_ID_RESP_SIZE); + gs0 = (sns_gxn_id_rsp_t *) ((u_int8_t *)fcp->isp_scratch+GXOFF); + isp_get_gxn_id_response(isp, gs0, gs1); + if (gs1->snscb_cthdr.ct_response != FS_ACC) { + isp_prt(isp, ISP_LOGWARN, swrej, "GNN_ID", + gs1->snscb_cthdr.ct_reason, + gs1->snscb_cthdr.ct_explanation, lcl.portid); + if (fcp->isp_loopstate != LOOP_SCANNING_FABRIC) { + FC_SCRATCH_RELEASE(isp); + return (-1); + } + continue; + } + lcl.node_wwn = + (((u_int64_t)gs1->snscb_wwn[0]) << 56) | + (((u_int64_t)gs1->snscb_wwn[1]) << 48) | + (((u_int64_t)gs1->snscb_wwn[2]) << 40) | + (((u_int64_t)gs1->snscb_wwn[3]) << 32) | + (((u_int64_t)gs1->snscb_wwn[4]) << 24) | + (((u_int64_t)gs1->snscb_wwn[5]) << 16) | + (((u_int64_t)gs1->snscb_wwn[6]) << 8) | + (((u_int64_t)gs1->snscb_wwn[7])); + + /* + * The QLogic f/w is bouncing this with a parameter error. + */ +#if 0 + /* + * Try and get FC4 Features (FC-GS-3 only). + * We can use the sns_gxn_id_req_t for this request. + */ + MEMZERO((void *) gq, sizeof (sns_gxn_id_req_t)); + gq->snscb_rblen = SNS_GFF_ID_RESP_SIZE >> 1; + gq->snscb_addr[RQRSP_ADDR0015] = DMA_WD0(fcp->isp_scdma+GXOFF); + gq->snscb_addr[RQRSP_ADDR1631] = DMA_WD1(fcp->isp_scdma+GXOFF); + gq->snscb_addr[RQRSP_ADDR3247] = DMA_WD2(fcp->isp_scdma+GXOFF); + gq->snscb_addr[RQRSP_ADDR4863] = DMA_WD3(fcp->isp_scdma+GXOFF); + gq->snscb_sblen = 6; + gq->snscb_cmd = SNS_GFF_ID; + gq->snscb_portid = lcl.portid; + isp_put_gxn_id_request(isp, gq, + (sns_gxn_id_req_t *) fcp->isp_scratch); + MEMORYBARRIER(isp, SYNC_SFORDEV, 0, SNS_GXN_ID_REQ_SIZE); + mbs.param[0] = MBOX_SEND_SNS; + mbs.param[1] = SNS_GXN_ID_REQ_SIZE >> 1; + mbs.param[2] = DMA_WD1(fcp->isp_scdma); + mbs.param[3] = DMA_WD0(fcp->isp_scdma); + /* + * Leave 4 and 5 alone + */ + mbs.param[6] = DMA_WD3(fcp->isp_scdma); + mbs.param[7] = DMA_WD2(fcp->isp_scdma); + if (isp_fabric_mbox_cmd(isp, &mbs)) { + if (fcp->isp_loopstate >= LOOP_SCANNING_FABRIC) { + fcp->isp_loopstate = LOOP_PDB_RCVD; + } + FC_SCRATCH_RELEASE(isp); + return (-1); + } + if (fcp->isp_loopstate != LOOP_SCANNING_FABRIC) { + FC_SCRATCH_RELEASE(isp); + return (-1); + } + MEMORYBARRIER(isp, SYNC_SFORCPU, GXOFF, SNS_GFF_ID_RESP_SIZE); + fs0 = (sns_gff_id_rsp_t *) ((u_int8_t *)fcp->isp_scratch+GXOFF); + isp_get_gff_id_response(isp, fs0, fs1); + if (fs1->snscb_cthdr.ct_response != FS_ACC) { + isp_prt(isp, /* ISP_LOGDEBUG0 */ ISP_LOGWARN, + swrej, "GFF_ID", + fs1->snscb_cthdr.ct_reason, + fs1->snscb_cthdr.ct_explanation, lcl.portid); + if (fcp->isp_loopstate != LOOP_SCANNING_FABRIC) { + FC_SCRATCH_RELEASE(isp); + return (-1); + } + } else { + int index = (ftype >> 3); + int bshft = (ftype & 0x7) * 4; + int fc4_fval = + (fs1->snscb_fc4_features[index] >> bshft) & 0xf; + if (fc4_fval & 0x1) { + lcl.roles |= + (SVC3_INI_ROLE >> SVC3_ROLE_SHIFT); + } + if (fc4_fval & 0x2) { + lcl.roles |= + (SVC3_TGT_ROLE >> SVC3_ROLE_SHIFT); + } + } +#endif + + /* + * If we really want to know what kind of port type this is, + * we have to run another CT command. Otherwise, we'll leave + * it as undefined. + * + lcl.port_type = 0; + */ + if (rs1->snscb_ports[i].control & 0x80) { + lcl.last_fabric_dev = 1; + } else { + lcl.last_fabric_dev = 0; + } + (void) isp_async(isp, ISPASYNC_FABRIC_DEV, &lcl); + + } while ((rs1->snscb_ports[i].control & 0x80) == 0 && i < NGENT-1); + + /* + * If we're not at the last entry, our list isn't big enough. + */ + if ((rs1->snscb_ports[i].control & 0x80) == 0) { + isp_prt(isp, ISP_LOGWARN, "fabric too big for scratch area"); + } + + FC_SCRATCH_RELEASE(isp); + fcp->isp_loopstate = LOOP_FSCAN_DONE; + return (0); +} +#endif + +static void +isp_register_fc4_type(struct ispsoftc *isp) +{ + fcparam *fcp = isp->isp_param; + u_int8_t local[SNS_RFT_ID_REQ_SIZE]; + sns_screq_t *reqp = (sns_screq_t *) local; + mbreg_t mbs; + + MEMZERO((void *) reqp, SNS_RFT_ID_REQ_SIZE); + reqp->snscb_rblen = SNS_RFT_ID_RESP_SIZE >> 1; + reqp->snscb_addr[RQRSP_ADDR0015] = DMA_WD0(fcp->isp_scdma + 0x100); + reqp->snscb_addr[RQRSP_ADDR1631] = DMA_WD1(fcp->isp_scdma + 0x100); + reqp->snscb_addr[RQRSP_ADDR3247] = DMA_WD2(fcp->isp_scdma + 0x100); + reqp->snscb_addr[RQRSP_ADDR4863] = DMA_WD3(fcp->isp_scdma + 0x100); + reqp->snscb_sblen = 22; + reqp->snscb_data[0] = SNS_RFT_ID; + reqp->snscb_data[4] = fcp->isp_portid & 0xffff; + reqp->snscb_data[5] = (fcp->isp_portid >> 16) & 0xff; + reqp->snscb_data[6] = (1 << FC4_SCSI); +#if 0 + reqp->snscb_data[6] |= (1 << FC4_IP); /* ISO/IEC 8802-2 LLC/SNAP */ +#endif + FC_SCRATCH_ACQUIRE(isp); + isp_put_sns_request(isp, reqp, (sns_screq_t *) fcp->isp_scratch); + mbs.param[0] = MBOX_SEND_SNS; + mbs.param[1] = SNS_RFT_ID_REQ_SIZE >> 1; + mbs.param[2] = DMA_WD1(fcp->isp_scdma); + mbs.param[3] = DMA_WD0(fcp->isp_scdma); + /* + * Leave 4 and 5 alone + */ + mbs.param[6] = DMA_WD3(fcp->isp_scdma); + mbs.param[7] = DMA_WD2(fcp->isp_scdma); + isp_mboxcmd(isp, &mbs, MBLOGALL); + FC_SCRATCH_RELEASE(isp); + if (mbs.param[0] == MBOX_COMMAND_COMPLETE) { + isp_prt(isp, ISP_LOGDEBUG0, "Register FC4 types succeeded"); + } +} + +/* + * Start a command. Locking is assumed done in the caller. + */ + +int +isp_start(XS_T *xs) +{ + struct ispsoftc *isp; + u_int16_t nxti, optr, handle; + u_int8_t local[QENTRY_LEN]; + ispreq_t *reqp, *qep; + int target, i; + + XS_INITERR(xs); + isp = XS_ISP(xs); + + /* + * Check to make sure we're supporting initiator role. + */ + if ((isp->isp_role & ISP_ROLE_INITIATOR) == 0) { + XS_SETERR(xs, HBA_SELTIMEOUT); + return (CMD_COMPLETE); + } + + /* + * Now make sure we're running. + */ + + if (isp->isp_state != ISP_RUNSTATE) { + isp_prt(isp, ISP_LOGERR, "Adapter not at RUNSTATE"); + XS_SETERR(xs, HBA_BOTCH); + return (CMD_COMPLETE); + } + + /* + * Check command CDB length, etc.. We really are limited to 16 bytes + * for Fibre Channel, but can do up to 44 bytes in parallel SCSI, + * but probably only if we're running fairly new firmware (we'll + * let the old f/w choke on an extended command queue entry). + */ + + if (XS_CDBLEN(xs) > (IS_FC(isp)? 16 : 44) || XS_CDBLEN(xs) == 0) { + isp_prt(isp, ISP_LOGERR, + "unsupported cdb length (%d, CDB[0]=0x%x)", + XS_CDBLEN(xs), XS_CDBP(xs)[0] & 0xff); + XS_SETERR(xs, HBA_BOTCH); + return (CMD_COMPLETE); + } + + /* + * Check to see whether we have good firmware state still or + * need to refresh our port database for this target. + */ + target = XS_TGT(xs); + if (IS_FC(isp)) { + fcparam *fcp = isp->isp_param; + struct lportdb *lp; +#ifdef HANDLE_LOOPSTATE_IN_OUTER_LAYERS + if (fcp->isp_fwstate != FW_READY || + fcp->isp_loopstate != LOOP_READY) { + return (CMD_RQLATER); + } + + /* + * If we're not on a Fabric, we can't have a target + * above FL_PORT_ID-1. + * + * If we're on a fabric and *not* connected as an F-port, + * we can't have a target less than FC_SNS_ID+1. This + * keeps us from having to sort out the difference between + * local public loop devices and those which we might get + * from a switch's database. + */ + if (fcp->isp_onfabric == 0) { + if (target >= FL_PORT_ID) { + XS_SETERR(xs, HBA_SELTIMEOUT); + return (CMD_COMPLETE); + } + } else { + if (target >= FL_PORT_ID && target <= FC_SNS_ID) { + XS_SETERR(xs, HBA_SELTIMEOUT); + return (CMD_COMPLETE); + } + /* + * We used to exclude having local loop ports + * at the same time that we have fabric ports. + * That is, we used to exclude having ports + * at < FL_PORT_ID if we're FL-port. + * + * That's wrong. The only thing that could be + * dicey is if the switch you're connected to + * has these local loop ports appear on the + * fabric and we somehow attach them twice. + */ + } +#else + /* + * Check for f/w being in ready state. If the f/w + * isn't in ready state, then we don't know our + * loop ID and the f/w hasn't completed logging + * into all targets on the loop. If this is the + * case, then bounce the command. We pretend this is + * a SELECTION TIMEOUT error if we've never gone to + * FW_READY state at all- in this case we may not + * be hooked to a loop at all and we shouldn't hang + * the machine for this. Otherwise, defer this command + * until later. + */ + if (fcp->isp_fwstate != FW_READY) { + /* + * Give ourselves at most a 250ms delay. + */ + if (isp_fclink_test(isp, 250000)) { + XS_SETERR(xs, HBA_SELTIMEOUT); + if (fcp->loop_seen_once) { + return (CMD_RQLATER); + } else { + return (CMD_COMPLETE); + } + } + } + + /* + * If we're not on a Fabric, we can't have a target + * above FL_PORT_ID-1. + * + * If we're on a fabric and *not* connected as an F-port, + * we can't have a target less than FC_SNS_ID+1. This + * keeps us from having to sort out the difference between + * local public loop devices and those which we might get + * from a switch's database. + */ + if (fcp->isp_onfabric == 0) { + if (target >= FL_PORT_ID) { + XS_SETERR(xs, HBA_SELTIMEOUT); + return (CMD_COMPLETE); + } + } else { + if (target >= FL_PORT_ID && target <= FC_SNS_ID) { + XS_SETERR(xs, HBA_SELTIMEOUT); + return (CMD_COMPLETE); + } + if (fcp->isp_topo != TOPO_F_PORT && + target < FL_PORT_ID) { + XS_SETERR(xs, HBA_SELTIMEOUT); + return (CMD_COMPLETE); + } + } + + /* + * If our loop state is such that we haven't yet received + * a "Port Database Changed" notification (after a LIP or + * a Loop Reset or firmware initialization), then defer + * sending commands for a little while, but only if we've + * seen a valid loop at one point (otherwise we can get + * stuck at initialization time). + */ + if (fcp->isp_loopstate < LOOP_PDB_RCVD) { + XS_SETERR(xs, HBA_SELTIMEOUT); + if (fcp->loop_seen_once) { + return (CMD_RQLATER); + } else { + return (CMD_COMPLETE); + } + } + + /* + * If we're in the middle of loop or fabric scanning + * or merging the port databases, retry this command later. + */ + if (fcp->isp_loopstate == LOOP_SCANNING_FABRIC || + fcp->isp_loopstate == LOOP_SCANNING_LOOP || + fcp->isp_loopstate == LOOP_SYNCING_PDB) { + return (CMD_RQLATER); + } + + /* + * If our loop state is now such that we've just now + * received a Port Database Change notification, then + * we have to go off and (re)scan the fabric. We back + * out and try again later if this doesn't work. + */ + if (fcp->isp_loopstate == LOOP_PDB_RCVD && fcp->isp_onfabric) { + if (isp_scan_fabric(isp, FC4_SCSI)) { + return (CMD_RQLATER); + } + if (fcp->isp_fwstate != FW_READY || + fcp->isp_loopstate < LOOP_FSCAN_DONE) { + return (CMD_RQLATER); + } + } + + /* + * If our loop state is now such that we've just now + * received a Port Database Change notification, then + * we have to go off and (re)synchronize our port + * database. + */ + if (fcp->isp_loopstate < LOOP_READY) { + if (isp_pdb_sync(isp)) { + return (CMD_RQLATER); + } + if (fcp->isp_fwstate != FW_READY || + fcp->isp_loopstate != LOOP_READY) { + return (CMD_RQLATER); + } + } + + /* + * XXX: Here's were we would cancel any loop_dead flag + * XXX: also cancel in dead_loop timeout that's running + */ +#endif + + /* + * Now check whether we should even think about pursuing this. + */ + lp = &fcp->portdb[target]; + if (lp->valid == 0) { + XS_SETERR(xs, HBA_SELTIMEOUT); + return (CMD_COMPLETE); + } + if ((lp->roles & (SVC3_TGT_ROLE >> SVC3_ROLE_SHIFT)) == 0) { + isp_prt(isp, ISP_LOGDEBUG2, + "Target %d does not have target service", target); + XS_SETERR(xs, HBA_SELTIMEOUT); + return (CMD_COMPLETE); + } + /* + * Now turn target into what the actual Loop ID is. + */ + target = lp->loopid; + } + + /* + * Next check to see if any HBA or Device + * parameters need to be updated. + */ + if (isp->isp_update != 0) { + isp_update(isp); + } + + if (isp_getrqentry(isp, &nxti, &optr, (void *)&qep)) { + isp_prt(isp, ISP_LOGDEBUG0, "Request Queue Overflow"); + XS_SETERR(xs, HBA_BOTCH); + return (CMD_EAGAIN); + } + + /* + * Now see if we need to synchronize the ISP with respect to anything. + * We do dual duty here (cough) for synchronizing for busses other + * than which we got here to send a command to. + */ + reqp = (ispreq_t *) local; + if (isp->isp_sendmarker) { + u_int8_t n = (IS_DUALBUS(isp)? 2: 1); + /* + * Check ports to send markers for... + */ + for (i = 0; i < n; i++) { + if ((isp->isp_sendmarker & (1 << i)) == 0) { + continue; + } + MEMZERO((void *) reqp, QENTRY_LEN); + reqp->req_header.rqs_entry_count = 1; + reqp->req_header.rqs_entry_type = RQSTYPE_MARKER; + reqp->req_modifier = SYNC_ALL; + reqp->req_target = i << 7; /* insert bus number */ + isp_put_request(isp, reqp, qep); + ISP_ADD_REQUEST(isp, nxti); + isp->isp_sendmarker &= ~(1 << i); + if (isp_getrqentry(isp, &nxti, &optr, (void *) &qep)) { + isp_prt(isp, ISP_LOGDEBUG0, + "Request Queue Overflow+"); + XS_SETERR(xs, HBA_BOTCH); + return (CMD_EAGAIN); + } + } + } + + MEMZERO((void *)reqp, QENTRY_LEN); + reqp->req_header.rqs_entry_count = 1; + if (IS_FC(isp)) { + reqp->req_header.rqs_entry_type = RQSTYPE_T2RQS; + } else { + if (XS_CDBLEN(xs) > 12) + reqp->req_header.rqs_entry_type = RQSTYPE_CMDONLY; + else + reqp->req_header.rqs_entry_type = RQSTYPE_REQUEST; + } + /* reqp->req_header.rqs_flags = 0; */ + /* reqp->req_header.rqs_seqno = 0; */ + if (IS_FC(isp)) { + /* + * See comment in isp_intr + */ + /* XS_RESID(xs) = 0; */ + + /* + * Fibre Channel always requires some kind of tag. + * The Qlogic drivers seem be happy not to use a tag, + * but this breaks for some devices (IBM drives). + */ + if (XS_TAG_P(xs)) { + ((ispreqt2_t *)reqp)->req_flags = XS_TAG_TYPE(xs); + } else { + /* + * If we don't know what tag to use, use HEAD OF QUEUE + * for Request Sense or Simple. + */ + if (XS_CDBP(xs)[0] == 0x3) /* REQUEST SENSE */ + ((ispreqt2_t *)reqp)->req_flags = REQFLAG_HTAG; + else + ((ispreqt2_t *)reqp)->req_flags = REQFLAG_STAG; + } + } else { + sdparam *sdp = (sdparam *)isp->isp_param; + sdp += XS_CHANNEL(xs); + if ((sdp->isp_devparam[target].actv_flags & DPARM_TQING) && + XS_TAG_P(xs)) { + reqp->req_flags = XS_TAG_TYPE(xs); + } + } + reqp->req_target = target | (XS_CHANNEL(xs) << 7); + if (IS_SCSI(isp)) { + reqp->req_lun_trn = XS_LUN(xs); + reqp->req_cdblen = XS_CDBLEN(xs); + } else { + if (FCPARAM(isp)->isp_fwattr & ISP_FW_ATTR_SCCLUN) + ((ispreqt2_t *)reqp)->req_scclun = XS_LUN(xs); + else + ((ispreqt2_t *)reqp)->req_lun_trn = XS_LUN(xs); + } + MEMCPY(reqp->req_cdb, XS_CDBP(xs), XS_CDBLEN(xs)); + + reqp->req_time = XS_TIME(xs) / 1000; + if (reqp->req_time == 0 && XS_TIME(xs)) { + reqp->req_time = 1; + } + + if (isp_save_xs(isp, xs, &handle)) { + isp_prt(isp, ISP_LOGDEBUG0, "out of xflist pointers"); + XS_SETERR(xs, HBA_BOTCH); + return (CMD_EAGAIN); + } + reqp->req_handle = handle; + + /* + * Set up DMA and/or do any bus swizzling of the request entry + * so that the Qlogic F/W understands what is being asked of it. + */ + i = ISP_DMASETUP(isp, xs, reqp, &nxti, optr); + if (i != CMD_QUEUED) { + isp_destroy_handle(isp, handle); + /* + * dmasetup sets actual error in packet, and + * return what we were given to return. + */ + return (i); + } + XS_SETERR(xs, HBA_NOERROR); + isp_prt(isp, ISP_LOGDEBUG2, + "START cmd for %d.%d.%d cmd 0x%x datalen %ld", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs), XS_CDBP(xs)[0], + (long) XS_XFRLEN(xs)); + ISP_ADD_REQUEST(isp, nxti); + isp->isp_nactive++; + return (CMD_QUEUED); +} + +/* + * isp control + * Locks (ints blocked) assumed held. + */ + +int +isp_control(struct ispsoftc *isp, ispctl_t ctl, void *arg) +{ + XS_T *xs; + mbreg_t mbs; + int bus, tgt; + u_int16_t handle; + + switch (ctl) { + default: + isp_prt(isp, ISP_LOGERR, "Unknown Control Opcode 0x%x", ctl); + break; + + case ISPCTL_RESET_BUS: + /* + * Issue a bus reset. + */ + mbs.param[0] = MBOX_BUS_RESET; + mbs.param[2] = 0; + if (IS_SCSI(isp)) { + mbs.param[1] = + ((sdparam *) isp->isp_param)->isp_bus_reset_delay; + if (mbs.param[1] < 2) + mbs.param[1] = 2; + bus = *((int *) arg); + if (IS_DUALBUS(isp)) + mbs.param[2] = bus; + } else { + mbs.param[1] = 10; + bus = 0; + } + isp->isp_sendmarker |= (1 << bus); + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + break; + } + isp_prt(isp, ISP_LOGINFO, + "driver initiated bus reset of bus %d", bus); + return (0); + + case ISPCTL_RESET_DEV: + tgt = (*((int *) arg)) & 0xffff; + bus = (*((int *) arg)) >> 16; + mbs.param[0] = MBOX_ABORT_TARGET; + mbs.param[1] = (tgt << 8) | (bus << 15); + mbs.param[2] = 3; /* 'delay', in seconds */ + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + break; + } + isp_prt(isp, ISP_LOGINFO, + "Target %d on Bus %d Reset Succeeded", tgt, bus); + isp->isp_sendmarker |= (1 << bus); + return (0); + + case ISPCTL_ABORT_CMD: + xs = (XS_T *) arg; + tgt = XS_TGT(xs); + handle = isp_find_handle(isp, xs); + if (handle == 0) { + isp_prt(isp, ISP_LOGWARN, + "cannot find handle for command to abort"); + break; + } + bus = XS_CHANNEL(xs); + mbs.param[0] = MBOX_ABORT; + if (IS_FC(isp)) { + if (FCPARAM(isp)->isp_fwattr & ISP_FW_ATTR_SCCLUN) { + mbs.param[1] = tgt << 8; + mbs.param[4] = 0; + mbs.param[5] = 0; + mbs.param[6] = XS_LUN(xs); + } else { + mbs.param[1] = tgt << 8 | XS_LUN(xs); + } + } else { + mbs.param[1] = + (bus << 15) | (XS_TGT(xs) << 8) | XS_LUN(xs); + } + mbs.param[3] = 0; + mbs.param[2] = handle; + isp_mboxcmd(isp, &mbs, MBLOGALL & ~MBOX_COMMAND_ERROR); + if (mbs.param[0] == MBOX_COMMAND_COMPLETE) { + return (0); + } + /* + * XXX: Look for command in the REQUEST QUEUE. That is, + * XXX: It hasen't been picked up by firmware yet. + */ + break; + + case ISPCTL_UPDATE_PARAMS: + + isp_update(isp); + return (0); + + case ISPCTL_FCLINK_TEST: + + if (IS_FC(isp)) { + int usdelay = (arg)? *((int *) arg) : 250000; + return (isp_fclink_test(isp, usdelay)); + } + break; + + case ISPCTL_SCAN_FABRIC: + + if (IS_FC(isp)) { + int ftype = (arg)? *((int *) arg) : FC4_SCSI; + return (isp_scan_fabric(isp, ftype)); + } + break; + + case ISPCTL_SCAN_LOOP: + + if (IS_FC(isp)) { + return (isp_scan_loop(isp)); + } + break; + + case ISPCTL_PDB_SYNC: + + if (IS_FC(isp)) { + return (isp_pdb_sync(isp)); + } + break; + + case ISPCTL_SEND_LIP: + + if (IS_FC(isp)) { + mbs.param[0] = MBOX_INIT_LIP; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] == MBOX_COMMAND_COMPLETE) { + return (0); + } + } + break; + + case ISPCTL_GET_POSMAP: + + if (IS_FC(isp) && arg) { + return (isp_getmap(isp, arg)); + } + break; + + case ISPCTL_RUN_MBOXCMD: + + isp_mboxcmd(isp, arg, MBLOGALL); + return(0); + +#ifdef ISP_TARGET_MODE + case ISPCTL_TOGGLE_TMODE: + { + + /* + * We don't check/set against role here- that's the + * responsibility for the outer layer to coordinate. + */ + if (IS_SCSI(isp)) { + int param = *(int *)arg; + mbs.param[0] = MBOX_ENABLE_TARGET_MODE; + mbs.param[1] = param & 0xffff; + mbs.param[2] = param >> 16; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + break; + } + } + return (0); + } +#endif + } + return (-1); +} + +/* + * Interrupt Service Routine(s). + * + * External (OS) framework has done the appropriate locking, + * and the locking will be held throughout this function. + */ + +/* + * Limit our stack depth by sticking with the max likely number + * of completions on a request queue at any one time. + */ +#ifndef MAX_REQUESTQ_COMPLETIONS +#define MAX_REQUESTQ_COMPLETIONS 64 +#endif + +void +isp_intr(struct ispsoftc *isp, u_int16_t isr, u_int16_t sema, u_int16_t mbox) +{ + XS_T *complist[MAX_REQUESTQ_COMPLETIONS], *xs; + u_int16_t iptr, optr, junk; + int i, nlooked = 0, ndone = 0; + +again: + /* + * Is this a mailbox related interrupt? + * The mailbox semaphore will be nonzero if so. + */ + if (sema) { + if (mbox & 0x4000) { + isp->isp_intmboxc++; + if (isp->isp_mboxbsy) { + int i = 0, obits = isp->isp_obits; + isp->isp_mboxtmp[i++] = mbox; + for (i = 1; i < MAX_MAILBOX; i++) { + if ((obits & (1 << i)) == 0) { + continue; + } + isp->isp_mboxtmp[i] = + ISP_READ(isp, MBOX_OFF(i)); + } + if (isp->isp_mbxwrk0) { + if (isp_mbox_continue(isp) == 0) { + return; + } + } + MBOX_NOTIFY_COMPLETE(isp); + } else { + isp_prt(isp, ISP_LOGWARN, + "Mbox Command Async (0x%x) with no waiters", + mbox); + } + } else if (isp_parse_async(isp, mbox) < 0) { + return; + } + if ((IS_FC(isp) && mbox != ASYNC_RIO_RESP) || + isp->isp_state != ISP_RUNSTATE) { + ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); + ISP_WRITE(isp, BIU_SEMA, 0); + return; + } + } + + /* + * We can't be getting this now. + */ + if (isp->isp_state != ISP_RUNSTATE) { + isp_prt(isp, ISP_LOGWARN, + "interrupt (ISR=%x SEMA=%x) when not ready", isr, sema); + /* + * Thank you very much! *Burrrp*! + */ + WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, + READ_RESPONSE_QUEUE_IN_POINTER(isp)); + + ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); + ISP_WRITE(isp, BIU_SEMA, 0); + return; + } + + /* + * Get the current Response Queue Out Pointer. + * + * If we're a 2300, we can ask what hardware what it thinks. + */ + if (IS_23XX(isp)) { + optr = ISP_READ(isp, isp->isp_respoutrp); + /* + * Debug: to be taken out eventually + */ + if (isp->isp_residx != optr) { + isp_prt(isp, ISP_LOGWARN, "optr %x soft optr %x", + optr, isp->isp_residx); + } + } else { + optr = isp->isp_residx; + } + + /* + * You *must* read the Response Queue In Pointer + * prior to clearing the RISC interrupt. + * + * Debounce the 2300 if revision less than 2. + */ + if (IS_2100(isp) || (IS_2300(isp) && isp->isp_revision < 2)) { + i = 0; + do { + iptr = READ_RESPONSE_QUEUE_IN_POINTER(isp); + junk = READ_RESPONSE_QUEUE_IN_POINTER(isp); + } while (junk != iptr && ++i < 1000); + + if (iptr != junk) { + ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); + isp_prt(isp, ISP_LOGWARN, + "Response Queue Out Pointer Unstable (%x, %x)", + iptr, junk); + return; + } + } else { + iptr = READ_RESPONSE_QUEUE_IN_POINTER(isp); + } + isp->isp_resodx = iptr; + + + if (optr == iptr && sema == 0) { + /* + * There are a lot of these- reasons unknown- mostly on + * faster Alpha machines. + * + * I tried delaying after writing HCCR_CMD_CLEAR_RISC_INT to + * make sure the old interrupt went away (to avoid 'ringing' + * effects), but that didn't stop this from occurring. + */ + if (IS_23XX(isp)) { + USEC_DELAY(100); + iptr = READ_RESPONSE_QUEUE_IN_POINTER(isp); + junk = ISP_READ(isp, BIU_R2HSTSLO); + } else { + junk = ISP_READ(isp, BIU_ISR); + } + if (optr == iptr) { + if (IS_23XX(isp)) { + ; + } else { + sema = ISP_READ(isp, BIU_SEMA); + mbox = ISP_READ(isp, OUTMAILBOX0); + if ((sema & 0x3) && (mbox & 0x8000)) { + goto again; + } + } + isp->isp_intbogus++; + isp_prt(isp, ISP_LOGDEBUG1, + "bogus intr- isr %x (%x) iptr %x optr %x", + isr, junk, iptr, optr); + } + } + isp->isp_resodx = iptr; + ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); + ISP_WRITE(isp, BIU_SEMA, 0); + + if (isp->isp_rspbsy) { + return; + } + isp->isp_rspbsy = 1; + + while (optr != iptr) { + ispstatusreq_t local, *sp = &local; + isphdr_t *hp; + int type; + u_int16_t oop; + int buddaboom = 0; + + hp = (isphdr_t *) ISP_QUEUE_ENTRY(isp->isp_result, optr); + oop = optr; + optr = ISP_NXT_QENTRY(optr, RESULT_QUEUE_LEN(isp)); + nlooked++; + /* + * Synchronize our view of this response queue entry. + */ + MEMORYBARRIER(isp, SYNC_RESULT, oop, QENTRY_LEN); + + type = isp_get_response_type(isp, hp); + + if (type == RQSTYPE_RESPONSE) { + isp_get_response(isp, (ispstatusreq_t *) hp, sp); + } else if (type == RQSTYPE_RIO2) { + isp_rio2_t rio; + isp_get_rio2(isp, (isp_rio2_t *) hp, &rio); + for (i = 0; i < rio.req_header.rqs_seqno; i++) { + isp_fastpost_complete(isp, rio.req_handles[i]); + } + if (isp->isp_fpcchiwater < rio.req_header.rqs_seqno) + isp->isp_fpcchiwater = rio.req_header.rqs_seqno; + MEMZERO(hp, QENTRY_LEN); /* PERF */ + continue; + } else { + /* + * Somebody reachable via isp_handle_other_response + * may have updated the response queue pointers for + * us, so we reload our goal index. + */ + if (isp_handle_other_response(isp, type, hp, &optr)) { + iptr = isp->isp_resodx; + MEMZERO(hp, QENTRY_LEN); /* PERF */ + continue; + } + + /* + * After this point, we'll just look at the header as + * we don't know how to deal with the rest of the + * response. + */ + isp_get_response(isp, (ispstatusreq_t *) hp, sp); + + /* + * It really has to be a bounced request just copied + * from the request queue to the response queue. If + * not, something bad has happened. + */ + if (sp->req_header.rqs_entry_type != RQSTYPE_REQUEST) { + isp_prt(isp, ISP_LOGERR, notresp, + sp->req_header.rqs_entry_type, oop, optr, + nlooked); + if (isp->isp_dblev & ISP_LOGDEBUG0) { + isp_print_bytes(isp, "Queue Entry", + QENTRY_LEN, sp); + } + MEMZERO(hp, QENTRY_LEN); /* PERF */ + continue; + } + buddaboom = 1; + } + + if (sp->req_header.rqs_flags & 0xf) { +#define _RQS_OFLAGS \ + ~(RQSFLAG_CONTINUATION|RQSFLAG_FULL|RQSFLAG_BADHEADER|RQSFLAG_BADPACKET) + if (sp->req_header.rqs_flags & RQSFLAG_CONTINUATION) { + isp_prt(isp, ISP_LOGWARN, + "continuation segment"); + WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, optr); + continue; + } + if (sp->req_header.rqs_flags & RQSFLAG_FULL) { + isp_prt(isp, ISP_LOGDEBUG1, + "internal queues full"); + /* + * We'll synthesize a QUEUE FULL message below. + */ + } + if (sp->req_header.rqs_flags & RQSFLAG_BADHEADER) { + isp_prt(isp, ISP_LOGERR, "bad header flag"); + buddaboom++; + } + if (sp->req_header.rqs_flags & RQSFLAG_BADPACKET) { + isp_prt(isp, ISP_LOGERR, "bad request packet"); + buddaboom++; + } + if (sp->req_header.rqs_flags & _RQS_OFLAGS) { + isp_prt(isp, ISP_LOGERR, + "unknown flags (0x%x) in response", + sp->req_header.rqs_flags); + buddaboom++; + } +#undef _RQS_OFLAGS + } + if (sp->req_handle > isp->isp_maxcmds || sp->req_handle < 1) { + MEMZERO(hp, QENTRY_LEN); /* PERF */ + isp_prt(isp, ISP_LOGERR, + "bad request handle %d (type 0x%x, flags 0x%x)", + sp->req_handle, sp->req_header.rqs_entry_type, + sp->req_header.rqs_flags); + WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, optr); + continue; + } + xs = isp_find_xs(isp, sp->req_handle); + if (xs == NULL) { + u_int8_t ts = sp->req_completion_status & 0xff; + MEMZERO(hp, QENTRY_LEN); /* PERF */ + /* + * Only whine if this isn't the expected fallout of + * aborting the command. + */ + if (sp->req_header.rqs_entry_type != RQSTYPE_RESPONSE) { + isp_prt(isp, ISP_LOGERR, + "cannot find handle 0x%x (type 0x%x)", + sp->req_handle, + sp->req_header.rqs_entry_type); + } else if (ts != RQCS_ABORTED) { + isp_prt(isp, ISP_LOGERR, + "cannot find handle 0x%x (status 0x%x)", + sp->req_handle, ts); + } + WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, optr); + continue; + } + isp_destroy_handle(isp, sp->req_handle); + if (sp->req_status_flags & RQSTF_BUS_RESET) { + XS_SETERR(xs, HBA_BUSRESET); + isp->isp_sendmarker |= (1 << XS_CHANNEL(xs)); + } + if (buddaboom) { + XS_SETERR(xs, HBA_BOTCH); + } + + if (IS_FC(isp) && (sp->req_scsi_status & RQCS_SV)) { + /* + * Fibre Channel F/W doesn't say we got status + * if there's Sense Data instead. I guess they + * think it goes w/o saying. + */ + sp->req_state_flags |= RQSF_GOT_STATUS; + } + if (sp->req_state_flags & RQSF_GOT_STATUS) { + *XS_STSP(xs) = sp->req_scsi_status & 0xff; + } + + switch (sp->req_header.rqs_entry_type) { + case RQSTYPE_RESPONSE: + XS_SET_STATE_STAT(isp, xs, sp); + isp_parse_status(isp, sp, xs); + if ((XS_NOERR(xs) || XS_ERR(xs) == HBA_NOERROR) && + (*XS_STSP(xs) == SCSI_BUSY)) { + XS_SETERR(xs, HBA_TGTBSY); + } + if (IS_SCSI(isp)) { + XS_RESID(xs) = sp->req_resid; + if ((sp->req_state_flags & RQSF_GOT_STATUS) && + (*XS_STSP(xs) == SCSI_CHECK) && + (sp->req_state_flags & RQSF_GOT_SENSE)) { + XS_SAVE_SENSE(xs, sp); + } + /* + * A new synchronous rate was negotiated for + * this target. Mark state such that we'll go + * look up that which has changed later. + */ + if (sp->req_status_flags & RQSTF_NEGOTIATION) { + int t = XS_TGT(xs); + sdparam *sdp = isp->isp_param; + sdp += XS_CHANNEL(xs); + sdp->isp_devparam[t].dev_refresh = 1; + isp->isp_update |= + (1 << XS_CHANNEL(xs)); + } + } else { + if (sp->req_status_flags & RQSF_XFER_COMPLETE) { + XS_RESID(xs) = 0; + } else if (sp->req_scsi_status & RQCS_RESID) { + XS_RESID(xs) = sp->req_resid; + } else { + XS_RESID(xs) = 0; + } + if ((sp->req_state_flags & RQSF_GOT_STATUS) && + (*XS_STSP(xs) == SCSI_CHECK) && + (sp->req_scsi_status & RQCS_SV)) { + XS_SAVE_SENSE(xs, sp); + /* solely for the benefit of debug */ + sp->req_state_flags |= RQSF_GOT_SENSE; + } + } + isp_prt(isp, ISP_LOGDEBUG2, + "asked for %ld got resid %ld", (long) XS_XFRLEN(xs), + (long) sp->req_resid); + break; + case RQSTYPE_REQUEST: + if (sp->req_header.rqs_flags & RQSFLAG_FULL) { + /* + * Force Queue Full status. + */ + *XS_STSP(xs) = SCSI_QFULL; + XS_SETERR(xs, HBA_NOERROR); + } else if (XS_NOERR(xs)) { + /* + * ???? + */ + isp_prt(isp, ISP_LOGDEBUG0, + "Request Queue Entry bounced back"); + XS_SETERR(xs, HBA_BOTCH); + } + XS_RESID(xs) = XS_XFRLEN(xs); + break; + default: + isp_prt(isp, ISP_LOGWARN, + "unhandled response queue type 0x%x", + sp->req_header.rqs_entry_type); + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_BOTCH); + } + break; + } + + /* + * Free any dma resources. As a side effect, this may + * also do any cache flushing necessary for data coherence. */ + if (XS_XFRLEN(xs)) { + ISP_DMAFREE(isp, xs, sp->req_handle); + } + + if (((isp->isp_dblev & (ISP_LOGDEBUG2|ISP_LOGDEBUG3))) || + ((isp->isp_dblev & ISP_LOGDEBUG1) && ((!XS_NOERR(xs)) || + (*XS_STSP(xs) != SCSI_GOOD)))) { + char skey; + if (sp->req_state_flags & RQSF_GOT_SENSE) { + skey = XS_SNSKEY(xs) & 0xf; + if (skey < 10) + skey += '0'; + else + skey += 'a' - 10; + } else if (*XS_STSP(xs) == SCSI_CHECK) { + skey = '?'; + } else { + skey = '.'; + } + isp_prt(isp, ISP_LOGALL, finmsg, XS_CHANNEL(xs), + XS_TGT(xs), XS_LUN(xs), XS_XFRLEN(xs), XS_RESID(xs), + *XS_STSP(xs), skey, XS_ERR(xs)); + } + + if (isp->isp_nactive > 0) + isp->isp_nactive--; + complist[ndone++] = xs; /* defer completion call until later */ + MEMZERO(hp, QENTRY_LEN); /* PERF */ + if (ndone == MAX_REQUESTQ_COMPLETIONS) { + break; + } + } + + /* + * If we looked at any commands, then it's valid to find out + * what the outpointer is. It also is a trigger to update the + * ISP's notion of what we've seen so far. + */ + if (nlooked) { + WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, optr); + /* + * While we're at it, read the requst queue out pointer. + */ + isp->isp_reqodx = READ_REQUEST_QUEUE_OUT_POINTER(isp); + if (isp->isp_rscchiwater < ndone) + isp->isp_rscchiwater = ndone; + } + + isp->isp_residx = optr; + isp->isp_rspbsy = 0; + for (i = 0; i < ndone; i++) { + xs = complist[i]; + if (xs) { + isp->isp_rsltccmplt++; + isp_done(xs); + } + } +} + +/* + * Support routines. + */ + +static int +isp_parse_async(struct ispsoftc *isp, u_int16_t mbox) +{ + int rval = 0; + int bus; + + if (IS_DUALBUS(isp)) { + bus = ISP_READ(isp, OUTMAILBOX6); + } else { + bus = 0; + } + isp_prt(isp, ISP_LOGDEBUG2, "Async Mbox 0x%x", mbox); + + switch (mbox) { + case ASYNC_BUS_RESET: + isp->isp_sendmarker |= (1 << bus); +#ifdef ISP_TARGET_MODE + if (isp_target_async(isp, bus, mbox)) + rval = -1; +#endif + isp_async(isp, ISPASYNC_BUS_RESET, &bus); + break; + case ASYNC_SYSTEM_ERROR: +#ifdef ISP_FW_CRASH_DUMP + /* + * If we have crash dumps enabled, it's up to the handler + * for isp_async to reinit stuff and restart the firmware + * after performing the crash dump. The reason we do things + * this way is that we may need to activate a kernel thread + * to do all the crash dump goop. + */ + isp_async(isp, ISPASYNC_FW_CRASH, NULL); +#else + isp_async(isp, ISPASYNC_FW_CRASH, NULL); + isp_reinit(isp); + isp_async(isp, ISPASYNC_FW_RESTARTED, NULL); +#endif + rval = -1; + break; + + case ASYNC_RQS_XFER_ERR: + isp_prt(isp, ISP_LOGERR, "Request Queue Transfer Error"); + break; + + case ASYNC_RSP_XFER_ERR: + isp_prt(isp, ISP_LOGERR, "Response Queue Transfer Error"); + break; + + case ASYNC_QWAKEUP: + /* + * We've just been notified that the Queue has woken up. + * We don't need to be chatty about this- just unlatch things + * and move on. + */ + mbox = READ_REQUEST_QUEUE_OUT_POINTER(isp); + break; + + case ASYNC_TIMEOUT_RESET: + isp_prt(isp, ISP_LOGWARN, + "timeout initiated SCSI bus reset of bus %d", bus); + isp->isp_sendmarker |= (1 << bus); +#ifdef ISP_TARGET_MODE + if (isp_target_async(isp, bus, mbox)) + rval = -1; +#endif + break; + + case ASYNC_DEVICE_RESET: + isp_prt(isp, ISP_LOGINFO, "device reset on bus %d", bus); + isp->isp_sendmarker |= (1 << bus); +#ifdef ISP_TARGET_MODE + if (isp_target_async(isp, bus, mbox)) + rval = -1; +#endif + break; + + case ASYNC_EXTMSG_UNDERRUN: + isp_prt(isp, ISP_LOGWARN, "extended message underrun"); + break; + + case ASYNC_SCAM_INT: + isp_prt(isp, ISP_LOGINFO, "SCAM interrupt"); + break; + + case ASYNC_HUNG_SCSI: + isp_prt(isp, ISP_LOGERR, + "stalled SCSI Bus after DATA Overrun"); + /* XXX: Need to issue SCSI reset at this point */ + break; + + case ASYNC_KILLED_BUS: + isp_prt(isp, ISP_LOGERR, "SCSI Bus reset after DATA Overrun"); + break; + + case ASYNC_BUS_TRANSIT: + mbox = ISP_READ(isp, OUTMAILBOX2); + switch (mbox & 0x1c00) { + case SXP_PINS_LVD_MODE: + isp_prt(isp, ISP_LOGINFO, "Transition to LVD mode"); + SDPARAM(isp)->isp_diffmode = 0; + SDPARAM(isp)->isp_ultramode = 0; + SDPARAM(isp)->isp_lvdmode = 1; + break; + case SXP_PINS_HVD_MODE: + isp_prt(isp, ISP_LOGINFO, + "Transition to Differential mode"); + SDPARAM(isp)->isp_diffmode = 1; + SDPARAM(isp)->isp_ultramode = 0; + SDPARAM(isp)->isp_lvdmode = 0; + break; + case SXP_PINS_SE_MODE: + isp_prt(isp, ISP_LOGINFO, + "Transition to Single Ended mode"); + SDPARAM(isp)->isp_diffmode = 0; + SDPARAM(isp)->isp_ultramode = 1; + SDPARAM(isp)->isp_lvdmode = 0; + break; + default: + isp_prt(isp, ISP_LOGWARN, + "Transition to Unknown Mode 0x%x", mbox); + break; + } + /* + * XXX: Set up to renegotiate again! + */ + /* Can only be for a 1080... */ + isp->isp_sendmarker |= (1 << bus); + break; + + /* + * We can use bus, which will always be zero for FC cards, + * as a mailbox pattern accumulator to be checked below. + */ + case ASYNC_RIO5: + bus = 0x1ce; /* outgoing mailbox regs 1-3, 6-7 */ + break; + + case ASYNC_RIO4: + bus = 0x14e; /* outgoing mailbox regs 1-3, 6 */ + break; + + case ASYNC_RIO3: + bus = 0x10e; /* outgoing mailbox regs 1-3 */ + break; + + case ASYNC_RIO2: + bus = 0x106; /* outgoing mailbox regs 1-2 */ + break; + + case ASYNC_RIO1: + case ASYNC_CMD_CMPLT: + bus = 0x102; /* outgoing mailbox regs 1 */ + break; + + case ASYNC_RIO_RESP: + return (rval); + + case ASYNC_CTIO_DONE: + { +#ifdef ISP_TARGET_MODE + int handle = + (ISP_READ(isp, OUTMAILBOX2) << 16) | + (ISP_READ(isp, OUTMAILBOX1)); + if (isp_target_async(isp, handle, mbox)) + rval = -1; +#else + isp_prt(isp, ISP_LOGINFO, "Fast Posting CTIO done"); +#endif + isp->isp_fphccmplt++; /* count it as a fast posting intr */ + break; + } + case ASYNC_LIP_F8: + case ASYNC_LIP_OCCURRED: + FCPARAM(isp)->isp_lipseq = + ISP_READ(isp, OUTMAILBOX1); + FCPARAM(isp)->isp_fwstate = FW_CONFIG_WAIT; + FCPARAM(isp)->isp_loopstate = LOOP_LIP_RCVD; + isp->isp_sendmarker = 1; + isp_mark_getpdb_all(isp); + isp_async(isp, ISPASYNC_LIP, NULL); +#ifdef ISP_TARGET_MODE + if (isp_target_async(isp, bus, mbox)) + rval = -1; +#endif + /* + * We've had problems with data corruption occuring on + * commands that complete (with no apparent error) after + * we receive a LIP. This has been observed mostly on + * Local Loop topologies. To be safe, let's just mark + * all active commands as dead. + */ + if (FCPARAM(isp)->isp_topo == TOPO_NL_PORT || + FCPARAM(isp)->isp_topo == TOPO_FL_PORT) { + int i, j; + for (i = j = 0; i < isp->isp_maxcmds; i++) { + XS_T *xs; + xs = isp->isp_xflist[i]; + if (xs != NULL) { + j++; + XS_SETERR(xs, HBA_BUSRESET); + } + } + if (j) { + isp_prt(isp, ISP_LOGERR, + "LIP destroyed %d active commands", j); + } + } + break; + + case ASYNC_LOOP_UP: + isp->isp_sendmarker = 1; + FCPARAM(isp)->isp_fwstate = FW_CONFIG_WAIT; + FCPARAM(isp)->isp_loopstate = LOOP_LIP_RCVD; + isp_mark_getpdb_all(isp); + isp_async(isp, ISPASYNC_LOOP_UP, NULL); +#ifdef ISP_TARGET_MODE + if (isp_target_async(isp, bus, mbox)) + rval = -1; +#endif + break; + + case ASYNC_LOOP_DOWN: + isp->isp_sendmarker = 1; + FCPARAM(isp)->isp_fwstate = FW_CONFIG_WAIT; + FCPARAM(isp)->isp_loopstate = LOOP_NIL; + isp_mark_getpdb_all(isp); + isp_async(isp, ISPASYNC_LOOP_DOWN, NULL); +#ifdef ISP_TARGET_MODE + if (isp_target_async(isp, bus, mbox)) + rval = -1; +#endif + break; + + case ASYNC_LOOP_RESET: + isp->isp_sendmarker = 1; + FCPARAM(isp)->isp_fwstate = FW_CONFIG_WAIT; + FCPARAM(isp)->isp_loopstate = LOOP_NIL; + isp_mark_getpdb_all(isp); + isp_async(isp, ISPASYNC_LOOP_RESET, NULL); +#ifdef ISP_TARGET_MODE + if (isp_target_async(isp, bus, mbox)) + rval = -1; +#endif + break; + + case ASYNC_PDB_CHANGED: + isp->isp_sendmarker = 1; + FCPARAM(isp)->isp_loopstate = LOOP_PDB_RCVD; + isp_mark_getpdb_all(isp); + isp_async(isp, ISPASYNC_CHANGE_NOTIFY, ISPASYNC_CHANGE_PDB); + break; + + case ASYNC_CHANGE_NOTIFY: + /* + * Not correct, but it will force us to rescan the loop. + */ + FCPARAM(isp)->isp_loopstate = LOOP_PDB_RCVD; + isp_mark_getpdb_all(isp); + isp_async(isp, ISPASYNC_CHANGE_NOTIFY, ISPASYNC_CHANGE_SNS); + break; + + case ASYNC_PTPMODE: + if (FCPARAM(isp)->isp_onfabric) + FCPARAM(isp)->isp_topo = TOPO_F_PORT; + else + FCPARAM(isp)->isp_topo = TOPO_N_PORT; + isp_mark_getpdb_all(isp); + isp->isp_sendmarker = 1; + FCPARAM(isp)->isp_fwstate = FW_CONFIG_WAIT; + FCPARAM(isp)->isp_loopstate = LOOP_LIP_RCVD; + isp_async(isp, ISPASYNC_CHANGE_NOTIFY, ISPASYNC_CHANGE_OTHER); +#ifdef ISP_TARGET_MODE + if (isp_target_async(isp, bus, mbox)) + rval = -1; +#endif + isp_prt(isp, ISP_LOGINFO, "Point-to-Point mode"); + break; + + case ASYNC_CONNMODE: + mbox = ISP_READ(isp, OUTMAILBOX1); + isp_mark_getpdb_all(isp); + switch (mbox) { + case ISP_CONN_LOOP: + isp_prt(isp, ISP_LOGINFO, + "Point-to-Point -> Loop mode"); + break; + case ISP_CONN_PTP: + isp_prt(isp, ISP_LOGINFO, + "Loop -> Point-to-Point mode"); + break; + case ISP_CONN_BADLIP: + isp_prt(isp, ISP_LOGWARN, + "Point-to-Point -> Loop mode (BAD LIP)"); + break; + case ISP_CONN_FATAL: + isp_prt(isp, ISP_LOGERR, "FATAL CONNECTION ERROR"); +#ifdef ISP_FW_CRASH_DUMP + isp_async(isp, ISPASYNC_FW_CRASH, NULL); +#else + isp_async(isp, ISPASYNC_FW_CRASH, NULL); + isp_reinit(isp); + isp_async(isp, ISPASYNC_FW_RESTARTED, NULL); +#endif + return (-1); + case ISP_CONN_LOOPBACK: + isp_prt(isp, ISP_LOGWARN, + "Looped Back in Point-to-Point mode"); + break; + default: + isp_prt(isp, ISP_LOGWARN, + "Unknown connection mode (0x%x)", mbox); + break; + } + isp_async(isp, ISPASYNC_CHANGE_NOTIFY, ISPASYNC_CHANGE_OTHER); + isp->isp_sendmarker = 1; + FCPARAM(isp)->isp_fwstate = FW_CONFIG_WAIT; + FCPARAM(isp)->isp_loopstate = LOOP_LIP_RCVD; + break; + + default: + isp_prt(isp, ISP_LOGWARN, "Unknown Async Code 0x%x", mbox); + break; + } + + if (bus & 0x100) { + int i, nh; + u_int16_t handles[5]; + + for (nh = 0, i = 1; i < MAX_MAILBOX; i++) { + if ((bus & (1 << i)) == 0) { + continue; + } + handles[nh++] = ISP_READ(isp, MBOX_OFF(i)); + } + for (i = 0; i < nh; i++) { + isp_fastpost_complete(isp, handles[i]); + isp_prt(isp, ISP_LOGDEBUG3, + "fast post completion of %u", handles[i]); + } + if (isp->isp_fpcchiwater < nh) + isp->isp_fpcchiwater = nh; + } else { + isp->isp_intoasync++; + } + return (rval); +} + +/* + * Handle other response entries. A pointer to the request queue output + * index is here in case we want to eat several entries at once, although + * this is not used currently. + */ + +static int +isp_handle_other_response(struct ispsoftc *isp, int type, + isphdr_t *hp, u_int16_t *optrp) +{ + switch (type) { + case RQSTYPE_STATUS_CONT: + isp_prt(isp, ISP_LOGINFO, "Ignored Continuation Response"); + return (1); + case RQSTYPE_ATIO: + case RQSTYPE_CTIO: + case RQSTYPE_ENABLE_LUN: + case RQSTYPE_MODIFY_LUN: + case RQSTYPE_NOTIFY: + case RQSTYPE_NOTIFY_ACK: + case RQSTYPE_CTIO1: + case RQSTYPE_ATIO2: + case RQSTYPE_CTIO2: + case RQSTYPE_CTIO3: + isp->isp_rsltccmplt++; /* count as a response completion */ +#ifdef ISP_TARGET_MODE + if (isp_target_notify(isp, (ispstatusreq_t *) hp, optrp)) { + return (1); + } +#else + optrp = optrp; + /* FALLTHROUGH */ +#endif + case RQSTYPE_REQUEST: + default: + if (isp_async(isp, ISPASYNC_UNHANDLED_RESPONSE, hp)) { + return (1); + } + isp_prt(isp, ISP_LOGWARN, "Unhandled Response Type 0x%x", + isp_get_response_type(isp, hp)); + return (0); + } +} + +static void +isp_parse_status(struct ispsoftc *isp, ispstatusreq_t *sp, XS_T *xs) +{ + switch (sp->req_completion_status & 0xff) { + case RQCS_COMPLETE: + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_NOERROR); + } + return; + + case RQCS_INCOMPLETE: + if ((sp->req_state_flags & RQSF_GOT_TARGET) == 0) { + isp_prt(isp, ISP_LOGDEBUG1, + "Selection Timeout for %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_SELTIMEOUT); + } + return; + } + isp_prt(isp, ISP_LOGERR, + "command incomplete for %d.%d.%d, state 0x%x", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs), + sp->req_state_flags); + break; + + case RQCS_DMA_ERROR: + isp_prt(isp, ISP_LOGERR, "DMA error for command on %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_TRANSPORT_ERROR: + { + char buf[172]; + SNPRINTF(buf, sizeof (buf), "states=>"); + if (sp->req_state_flags & RQSF_GOT_BUS) { + SNPRINTF(buf, sizeof (buf), "%s GOT_BUS", buf); + } + if (sp->req_state_flags & RQSF_GOT_TARGET) { + SNPRINTF(buf, sizeof (buf), "%s GOT_TGT", buf); + } + if (sp->req_state_flags & RQSF_SENT_CDB) { + SNPRINTF(buf, sizeof (buf), "%s SENT_CDB", buf); + } + if (sp->req_state_flags & RQSF_XFRD_DATA) { + SNPRINTF(buf, sizeof (buf), "%s XFRD_DATA", buf); + } + if (sp->req_state_flags & RQSF_GOT_STATUS) { + SNPRINTF(buf, sizeof (buf), "%s GOT_STS", buf); + } + if (sp->req_state_flags & RQSF_GOT_SENSE) { + SNPRINTF(buf, sizeof (buf), "%s GOT_SNS", buf); + } + if (sp->req_state_flags & RQSF_XFER_COMPLETE) { + SNPRINTF(buf, sizeof (buf), "%s XFR_CMPLT", buf); + } + SNPRINTF(buf, sizeof (buf), "%s\nstatus=>", buf); + if (sp->req_status_flags & RQSTF_DISCONNECT) { + SNPRINTF(buf, sizeof (buf), "%s Disconnect", buf); + } + if (sp->req_status_flags & RQSTF_SYNCHRONOUS) { + SNPRINTF(buf, sizeof (buf), "%s Sync_xfr", buf); + } + if (sp->req_status_flags & RQSTF_PARITY_ERROR) { + SNPRINTF(buf, sizeof (buf), "%s Parity", buf); + } + if (sp->req_status_flags & RQSTF_BUS_RESET) { + SNPRINTF(buf, sizeof (buf), "%s Bus_Reset", buf); + } + if (sp->req_status_flags & RQSTF_DEVICE_RESET) { + SNPRINTF(buf, sizeof (buf), "%s Device_Reset", buf); + } + if (sp->req_status_flags & RQSTF_ABORTED) { + SNPRINTF(buf, sizeof (buf), "%s Aborted", buf); + } + if (sp->req_status_flags & RQSTF_TIMEOUT) { + SNPRINTF(buf, sizeof (buf), "%s Timeout", buf); + } + if (sp->req_status_flags & RQSTF_NEGOTIATION) { + SNPRINTF(buf, sizeof (buf), "%s Negotiation", buf); + } + isp_prt(isp, ISP_LOGERR, "%s", buf); + isp_prt(isp, ISP_LOGERR, "transport error for %d.%d.%d:\n%s", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs), buf); + break; + } + case RQCS_RESET_OCCURRED: + isp_prt(isp, ISP_LOGWARN, + "bus reset destroyed command for %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + isp->isp_sendmarker |= (1 << XS_CHANNEL(xs)); + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_BUSRESET); + } + return; + + case RQCS_ABORTED: + isp_prt(isp, ISP_LOGERR, "command aborted for %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + isp->isp_sendmarker |= (1 << XS_CHANNEL(xs)); + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_ABORTED); + } + return; + + case RQCS_TIMEOUT: + isp_prt(isp, ISP_LOGWARN, "command timed out for %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + /* + * Check to see if we logged out the device. + */ + if (IS_FC(isp)) { + if ((sp->req_completion_status & RQSTF_LOGOUT) && + FCPARAM(isp)->portdb[XS_TGT(xs)].valid && + FCPARAM(isp)->portdb[XS_TGT(xs)].fabric_dev) { + FCPARAM(isp)->portdb[XS_TGT(xs)].relogin = 1; + } + } + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_CMDTIMEOUT); + } + return; + + case RQCS_DATA_OVERRUN: + XS_RESID(xs) = sp->req_resid; + isp_prt(isp, ISP_LOGERR, "data overrun for command on %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_DATAOVR); + } + return; + + case RQCS_COMMAND_OVERRUN: + isp_prt(isp, ISP_LOGERR, + "command overrun for command on %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_STATUS_OVERRUN: + isp_prt(isp, ISP_LOGERR, + "status overrun for command on %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_BAD_MESSAGE: + isp_prt(isp, ISP_LOGERR, + "msg not COMMAND COMPLETE after status %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_NO_MESSAGE_OUT: + isp_prt(isp, ISP_LOGERR, + "No MESSAGE OUT phase after selection on %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_EXT_ID_FAILED: + isp_prt(isp, ISP_LOGERR, "EXTENDED IDENTIFY failed %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_IDE_MSG_FAILED: + isp_prt(isp, ISP_LOGERR, + "INITIATOR DETECTED ERROR rejected by %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_ABORT_MSG_FAILED: + isp_prt(isp, ISP_LOGERR, "ABORT OPERATION rejected by %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_REJECT_MSG_FAILED: + isp_prt(isp, ISP_LOGERR, "MESSAGE REJECT rejected by %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_NOP_MSG_FAILED: + isp_prt(isp, ISP_LOGERR, "NOP rejected by %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_PARITY_ERROR_MSG_FAILED: + isp_prt(isp, ISP_LOGERR, + "MESSAGE PARITY ERROR rejected by %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_DEVICE_RESET_MSG_FAILED: + isp_prt(isp, ISP_LOGWARN, + "BUS DEVICE RESET rejected by %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_ID_MSG_FAILED: + isp_prt(isp, ISP_LOGERR, "IDENTIFY rejected by %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_UNEXP_BUS_FREE: + isp_prt(isp, ISP_LOGERR, "%d.%d.%d had an unexpected bus free", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_DATA_UNDERRUN: + { + if (IS_FC(isp)) { + int ru_marked = (sp->req_scsi_status & RQCS_RU) != 0; + if (!ru_marked || sp->req_resid > XS_XFRLEN(xs)) { + isp_prt(isp, ISP_LOGWARN, bun, XS_TGT(xs), + XS_LUN(xs), XS_XFRLEN(xs), sp->req_resid, + (ru_marked)? "marked" : "not marked"); + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_BOTCH); + } + return; + } + } + XS_RESID(xs) = sp->req_resid; + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_NOERROR); + } + return; + } + + case RQCS_XACT_ERR1: + isp_prt(isp, ISP_LOGERR, xact1, XS_CHANNEL(xs), + XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_XACT_ERR2: + isp_prt(isp, ISP_LOGERR, xact2, + XS_LUN(xs), XS_TGT(xs), XS_CHANNEL(xs)); + break; + + case RQCS_XACT_ERR3: + isp_prt(isp, ISP_LOGERR, xact3, + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_BAD_ENTRY: + isp_prt(isp, ISP_LOGERR, "Invalid IOCB entry type detected"); + break; + + case RQCS_QUEUE_FULL: + isp_prt(isp, ISP_LOGDEBUG0, + "internal queues full for %d.%d.%d status 0x%x", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs), *XS_STSP(xs)); + + /* + * If QFULL or some other status byte is set, then this + * isn't an error, per se. + * + * Unfortunately, some QLogic f/w writers have, in + * some cases, ommitted to *set* status to QFULL. + * + + if (*XS_STSP(xs) != SCSI_GOOD && XS_NOERR(xs)) { + XS_SETERR(xs, HBA_NOERROR); + return; + } + + * + * + */ + + *XS_STSP(xs) = SCSI_QFULL; + XS_SETERR(xs, HBA_NOERROR); + return; + + case RQCS_PHASE_SKIPPED: + isp_prt(isp, ISP_LOGERR, pskip, XS_CHANNEL(xs), + XS_TGT(xs), XS_LUN(xs)); + break; + + case RQCS_ARQS_FAILED: + isp_prt(isp, ISP_LOGERR, + "Auto Request Sense failed for %d.%d.%d", + XS_CHANNEL(xs), XS_TGT(xs), XS_LUN(xs)); + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_ARQFAIL); + } + return; + + case RQCS_WIDE_FAILED: + isp_prt(isp, ISP_LOGERR, + "Wide Negotiation failed for %d.%d.%d", + XS_TGT(xs), XS_LUN(xs), XS_CHANNEL(xs)); + if (IS_SCSI(isp)) { + sdparam *sdp = isp->isp_param; + sdp += XS_CHANNEL(xs); + sdp->isp_devparam[XS_TGT(xs)].goal_flags &= ~DPARM_WIDE; + sdp->isp_devparam[XS_TGT(xs)].dev_update = 1; + isp->isp_update |= (1 << XS_CHANNEL(xs)); + } + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_NOERROR); + } + return; + + case RQCS_SYNCXFER_FAILED: + isp_prt(isp, ISP_LOGERR, + "SDTR Message failed for target %d.%d.%d", + XS_TGT(xs), XS_LUN(xs), XS_CHANNEL(xs)); + if (IS_SCSI(isp)) { + sdparam *sdp = isp->isp_param; + sdp += XS_CHANNEL(xs); + sdp->isp_devparam[XS_TGT(xs)].goal_flags &= ~DPARM_SYNC; + sdp->isp_devparam[XS_TGT(xs)].dev_update = 1; + isp->isp_update |= (1 << XS_CHANNEL(xs)); + } + break; + + case RQCS_LVD_BUSERR: + isp_prt(isp, ISP_LOGERR, + "Bad LVD condition while talking to %d.%d.%d", + XS_TGT(xs), XS_LUN(xs), XS_CHANNEL(xs)); + break; + + case RQCS_PORT_UNAVAILABLE: + /* + * No such port on the loop. Moral equivalent of SELTIMEO + */ + case RQCS_PORT_LOGGED_OUT: + /* + * It was there (maybe)- treat as a selection timeout. + */ + if ((sp->req_completion_status & 0xff) == RQCS_PORT_UNAVAILABLE) + isp_prt(isp, ISP_LOGINFO, + "port unavailable for target %d", XS_TGT(xs)); + else + isp_prt(isp, ISP_LOGINFO, + "port logout for target %d", XS_TGT(xs)); + /* + * If we're on a local loop, force a LIP (which is overkill) + * to force a re-login of this unit. If we're on fabric, + * then we'll have to relogin as a matter of course. + */ + if (FCPARAM(isp)->isp_topo == TOPO_NL_PORT || + FCPARAM(isp)->isp_topo == TOPO_FL_PORT) { + mbreg_t mbs; + mbs.param[0] = MBOX_INIT_LIP; + isp_mboxcmd_qnw(isp, &mbs, 1); + } + + /* + * Probably overkill. + */ + isp->isp_sendmarker = 1; + FCPARAM(isp)->isp_loopstate = LOOP_PDB_RCVD; + isp_mark_getpdb_all(isp); + isp_async(isp, ISPASYNC_CHANGE_NOTIFY, ISPASYNC_CHANGE_OTHER); + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_SELTIMEOUT); + } + return; + + case RQCS_PORT_CHANGED: + isp_prt(isp, ISP_LOGWARN, + "port changed for target %d", XS_TGT(xs)); + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_SELTIMEOUT); + } + return; + + case RQCS_PORT_BUSY: + isp_prt(isp, ISP_LOGWARN, + "port busy for target %d", XS_TGT(xs)); + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_TGTBSY); + } + return; + + default: + isp_prt(isp, ISP_LOGERR, "Unknown Completion Status 0x%x", + sp->req_completion_status); + break; + } + if (XS_NOERR(xs)) { + XS_SETERR(xs, HBA_BOTCH); + } +} + +static void +isp_fastpost_complete(struct ispsoftc *isp, u_int16_t fph) +{ + XS_T *xs; + + if (fph == 0) { + return; + } + xs = isp_find_xs(isp, fph); + if (xs == NULL) { + isp_prt(isp, ISP_LOGWARN, + "Command for fast post handle 0x%x not found", fph); + return; + } + isp_destroy_handle(isp, fph); + + /* + * Since we don't have a result queue entry item, + * we must believe that SCSI status is zero and + * that all data transferred. + */ + XS_SET_STATE_STAT(isp, xs, NULL); + XS_RESID(xs) = 0; + *XS_STSP(xs) = SCSI_GOOD; + if (XS_XFRLEN(xs)) { + ISP_DMAFREE(isp, xs, fph); + } + if (isp->isp_nactive) + isp->isp_nactive--; + isp->isp_fphccmplt++; + isp_done(xs); +} + +static int +isp_mbox_continue(struct ispsoftc *isp) +{ + mbreg_t mbs; + u_int16_t *ptr; + + switch (isp->isp_lastmbxcmd) { + case MBOX_WRITE_RAM_WORD: + case MBOX_READ_RAM_WORD: + case MBOX_READ_RAM_WORD_EXTENDED: + break; + default: + return (1); + } + if (isp->isp_mboxtmp[0] != MBOX_COMMAND_COMPLETE) { + isp->isp_mbxwrk0 = 0; + return (-1); + } + + + /* + * Clear the previous interrupt. + */ + ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); + ISP_WRITE(isp, BIU_SEMA, 0); + + /* + * Continue with next word. + */ + ptr = isp->isp_mbxworkp; + switch (isp->isp_lastmbxcmd) { + case MBOX_WRITE_RAM_WORD: + mbs.param[2] = *ptr++; + mbs.param[1] = isp->isp_mbxwrk1++; + break; + case MBOX_READ_RAM_WORD: + case MBOX_READ_RAM_WORD_EXTENDED: + *ptr++ = isp->isp_mboxtmp[2]; + mbs.param[1] = isp->isp_mbxwrk1++; + break; + } + isp->isp_mbxworkp = ptr; + mbs.param[0] = isp->isp_lastmbxcmd; + isp->isp_mbxwrk0 -= 1; + isp_mboxcmd_qnw(isp, &mbs, 0); + return (0); +} + + +#define HIBYT(x) ((x) >> 0x8) +#define LOBYT(x) ((x) & 0xff) +#define ISPOPMAP(a, b) (((a) << 8) | (b)) +static u_int16_t mbpscsi[] = { + ISPOPMAP(0x01, 0x01), /* 0x00: MBOX_NO_OP */ + ISPOPMAP(0x1f, 0x01), /* 0x01: MBOX_LOAD_RAM */ + ISPOPMAP(0x03, 0x01), /* 0x02: MBOX_EXEC_FIRMWARE */ + ISPOPMAP(0x1f, 0x01), /* 0x03: MBOX_DUMP_RAM */ + ISPOPMAP(0x07, 0x07), /* 0x04: MBOX_WRITE_RAM_WORD */ + ISPOPMAP(0x03, 0x07), /* 0x05: MBOX_READ_RAM_WORD */ + ISPOPMAP(0x3f, 0x3f), /* 0x06: MBOX_MAILBOX_REG_TEST */ + ISPOPMAP(0x03, 0x07), /* 0x07: MBOX_VERIFY_CHECKSUM */ + ISPOPMAP(0x01, 0x0f), /* 0x08: MBOX_ABOUT_FIRMWARE */ + ISPOPMAP(0x00, 0x00), /* 0x09: */ + ISPOPMAP(0x00, 0x00), /* 0x0a: */ + ISPOPMAP(0x00, 0x00), /* 0x0b: */ + ISPOPMAP(0x00, 0x00), /* 0x0c: */ + ISPOPMAP(0x00, 0x00), /* 0x0d: */ + ISPOPMAP(0x01, 0x05), /* 0x0e: MBOX_CHECK_FIRMWARE */ + ISPOPMAP(0x00, 0x00), /* 0x0f: */ + ISPOPMAP(0x1f, 0x1f), /* 0x10: MBOX_INIT_REQ_QUEUE */ + ISPOPMAP(0x3f, 0x3f), /* 0x11: MBOX_INIT_RES_QUEUE */ + ISPOPMAP(0x0f, 0x0f), /* 0x12: MBOX_EXECUTE_IOCB */ + ISPOPMAP(0x03, 0x03), /* 0x13: MBOX_WAKE_UP */ + ISPOPMAP(0x01, 0x3f), /* 0x14: MBOX_STOP_FIRMWARE */ + ISPOPMAP(0x0f, 0x0f), /* 0x15: MBOX_ABORT */ + ISPOPMAP(0x03, 0x03), /* 0x16: MBOX_ABORT_DEVICE */ + ISPOPMAP(0x07, 0x07), /* 0x17: MBOX_ABORT_TARGET */ + ISPOPMAP(0x07, 0x07), /* 0x18: MBOX_BUS_RESET */ + ISPOPMAP(0x03, 0x07), /* 0x19: MBOX_STOP_QUEUE */ + ISPOPMAP(0x03, 0x07), /* 0x1a: MBOX_START_QUEUE */ + ISPOPMAP(0x03, 0x07), /* 0x1b: MBOX_SINGLE_STEP_QUEUE */ + ISPOPMAP(0x03, 0x07), /* 0x1c: MBOX_ABORT_QUEUE */ + ISPOPMAP(0x03, 0x4f), /* 0x1d: MBOX_GET_DEV_QUEUE_STATUS */ + ISPOPMAP(0x00, 0x00), /* 0x1e: */ + ISPOPMAP(0x01, 0x07), /* 0x1f: MBOX_GET_FIRMWARE_STATUS */ + ISPOPMAP(0x01, 0x07), /* 0x20: MBOX_GET_INIT_SCSI_ID */ + ISPOPMAP(0x01, 0x07), /* 0x21: MBOX_GET_SELECT_TIMEOUT */ + ISPOPMAP(0x01, 0xc7), /* 0x22: MBOX_GET_RETRY_COUNT */ + ISPOPMAP(0x01, 0x07), /* 0x23: MBOX_GET_TAG_AGE_LIMIT */ + ISPOPMAP(0x01, 0x03), /* 0x24: MBOX_GET_CLOCK_RATE */ + ISPOPMAP(0x01, 0x07), /* 0x25: MBOX_GET_ACT_NEG_STATE */ + ISPOPMAP(0x01, 0x07), /* 0x26: MBOX_GET_ASYNC_DATA_SETUP_TIME */ + ISPOPMAP(0x01, 0x07), /* 0x27: MBOX_GET_PCI_PARAMS */ + ISPOPMAP(0x03, 0x4f), /* 0x28: MBOX_GET_TARGET_PARAMS */ + ISPOPMAP(0x03, 0x0f), /* 0x29: MBOX_GET_DEV_QUEUE_PARAMS */ + ISPOPMAP(0x01, 0x07), /* 0x2a: MBOX_GET_RESET_DELAY_PARAMS */ + ISPOPMAP(0x00, 0x00), /* 0x2b: */ + ISPOPMAP(0x00, 0x00), /* 0x2c: */ + ISPOPMAP(0x00, 0x00), /* 0x2d: */ + ISPOPMAP(0x00, 0x00), /* 0x2e: */ + ISPOPMAP(0x00, 0x00), /* 0x2f: */ + ISPOPMAP(0x03, 0x03), /* 0x30: MBOX_SET_INIT_SCSI_ID */ + ISPOPMAP(0x07, 0x07), /* 0x31: MBOX_SET_SELECT_TIMEOUT */ + ISPOPMAP(0xc7, 0xc7), /* 0x32: MBOX_SET_RETRY_COUNT */ + ISPOPMAP(0x07, 0x07), /* 0x33: MBOX_SET_TAG_AGE_LIMIT */ + ISPOPMAP(0x03, 0x03), /* 0x34: MBOX_SET_CLOCK_RATE */ + ISPOPMAP(0x07, 0x07), /* 0x35: MBOX_SET_ACT_NEG_STATE */ + ISPOPMAP(0x07, 0x07), /* 0x36: MBOX_SET_ASYNC_DATA_SETUP_TIME */ + ISPOPMAP(0x07, 0x07), /* 0x37: MBOX_SET_PCI_CONTROL_PARAMS */ + ISPOPMAP(0x4f, 0x4f), /* 0x38: MBOX_SET_TARGET_PARAMS */ + ISPOPMAP(0x0f, 0x0f), /* 0x39: MBOX_SET_DEV_QUEUE_PARAMS */ + ISPOPMAP(0x07, 0x07), /* 0x3a: MBOX_SET_RESET_DELAY_PARAMS */ + ISPOPMAP(0x00, 0x00), /* 0x3b: */ + ISPOPMAP(0x00, 0x00), /* 0x3c: */ + ISPOPMAP(0x00, 0x00), /* 0x3d: */ + ISPOPMAP(0x00, 0x00), /* 0x3e: */ + ISPOPMAP(0x00, 0x00), /* 0x3f: */ + ISPOPMAP(0x01, 0x03), /* 0x40: MBOX_RETURN_BIOS_BLOCK_ADDR */ + ISPOPMAP(0x3f, 0x01), /* 0x41: MBOX_WRITE_FOUR_RAM_WORDS */ + ISPOPMAP(0x03, 0x07), /* 0x42: MBOX_EXEC_BIOS_IOCB */ + ISPOPMAP(0x00, 0x00), /* 0x43: */ + ISPOPMAP(0x00, 0x00), /* 0x44: */ + ISPOPMAP(0x03, 0x03), /* 0x45: SET SYSTEM PARAMETER */ + ISPOPMAP(0x01, 0x03), /* 0x46: GET SYSTEM PARAMETER */ + ISPOPMAP(0x00, 0x00), /* 0x47: */ + ISPOPMAP(0x01, 0xcf), /* 0x48: GET SCAM CONFIGURATION */ + ISPOPMAP(0xcf, 0xcf), /* 0x49: SET SCAM CONFIGURATION */ + ISPOPMAP(0x03, 0x03), /* 0x4a: MBOX_SET_FIRMWARE_FEATURES */ + ISPOPMAP(0x01, 0x03), /* 0x4b: MBOX_GET_FIRMWARE_FEATURES */ + ISPOPMAP(0x00, 0x00), /* 0x4c: */ + ISPOPMAP(0x00, 0x00), /* 0x4d: */ + ISPOPMAP(0x00, 0x00), /* 0x4e: */ + ISPOPMAP(0x00, 0x00), /* 0x4f: */ + ISPOPMAP(0xdf, 0xdf), /* 0x50: LOAD RAM A64 */ + ISPOPMAP(0xdf, 0xdf), /* 0x51: DUMP RAM A64 */ + ISPOPMAP(0xdf, 0xff), /* 0x52: INITIALIZE REQUEST QUEUE A64 */ + ISPOPMAP(0xef, 0xff), /* 0x53: INITIALIZE RESPONSE QUEUE A64 */ + ISPOPMAP(0xcf, 0x01), /* 0x54: EXECUTE IOCB A64 */ + ISPOPMAP(0x07, 0x01), /* 0x55: ENABLE TARGET MODE */ + ISPOPMAP(0x03, 0x0f), /* 0x56: GET TARGET STATUS */ + ISPOPMAP(0x00, 0x00), /* 0x57: */ + ISPOPMAP(0x00, 0x00), /* 0x58: */ + ISPOPMAP(0x00, 0x00), /* 0x59: */ + ISPOPMAP(0x03, 0x03), /* 0x5a: SET DATA OVERRUN RECOVERY MODE */ + ISPOPMAP(0x01, 0x03), /* 0x5b: GET DATA OVERRUN RECOVERY MODE */ + ISPOPMAP(0x0f, 0x0f), /* 0x5c: SET HOST DATA */ + ISPOPMAP(0x01, 0x01) /* 0x5d: GET NOST DATA */ +}; + +#ifndef ISP_STRIPPED +static char *scsi_mbcmd_names[] = { + "NO-OP", + "LOAD RAM", + "EXEC FIRMWARE", + "DUMP RAM", + "WRITE RAM WORD", + "READ RAM WORD", + "MAILBOX REG TEST", + "VERIFY CHECKSUM", + "ABOUT FIRMWARE", + NULL, + NULL, + NULL, + NULL, + NULL, + "CHECK FIRMWARE", + NULL, + "INIT REQUEST QUEUE", + "INIT RESULT QUEUE", + "EXECUTE IOCB", + "WAKE UP", + "STOP FIRMWARE", + "ABORT", + "ABORT DEVICE", + "ABORT TARGET", + "BUS RESET", + "STOP QUEUE", + "START QUEUE", + "SINGLE STEP QUEUE", + "ABORT QUEUE", + "GET DEV QUEUE STATUS", + NULL, + "GET FIRMWARE STATUS", + "GET INIT SCSI ID", + "GET SELECT TIMEOUT", + "GET RETRY COUNT", + "GET TAG AGE LIMIT", + "GET CLOCK RATE", + "GET ACT NEG STATE", + "GET ASYNC DATA SETUP TIME", + "GET PCI PARAMS", + "GET TARGET PARAMS", + "GET DEV QUEUE PARAMS", + "GET RESET DELAY PARAMS", + NULL, + NULL, + NULL, + NULL, + NULL, + "SET INIT SCSI ID", + "SET SELECT TIMEOUT", + "SET RETRY COUNT", + "SET TAG AGE LIMIT", + "SET CLOCK RATE", + "SET ACT NEG STATE", + "SET ASYNC DATA SETUP TIME", + "SET PCI CONTROL PARAMS", + "SET TARGET PARAMS", + "SET DEV QUEUE PARAMS", + "SET RESET DELAY PARAMS", + NULL, + NULL, + NULL, + NULL, + NULL, + "RETURN BIOS BLOCK ADDR", + "WRITE FOUR RAM WORDS", + "EXEC BIOS IOCB", + NULL, + NULL, + "SET SYSTEM PARAMETER", + "GET SYSTEM PARAMETER", + NULL, + "GET SCAM CONFIGURATION", + "SET SCAM CONFIGURATION", + "SET FIRMWARE FEATURES", + "GET FIRMWARE FEATURES", + NULL, + NULL, + NULL, + NULL, + "LOAD RAM A64", + "DUMP RAM A64", + "INITIALIZE REQUEST QUEUE A64", + "INITIALIZE RESPONSE QUEUE A64", + "EXECUTE IOCB A64", + "ENABLE TARGET MODE", + "GET TARGET MODE STATE", + NULL, + NULL, + NULL, + "SET DATA OVERRUN RECOVERY MODE", + "GET DATA OVERRUN RECOVERY MODE", + "SET HOST DATA", + "GET NOST DATA", +}; +#endif + +static u_int16_t mbpfc[] = { + ISPOPMAP(0x01, 0x01), /* 0x00: MBOX_NO_OP */ + ISPOPMAP(0x1f, 0x01), /* 0x01: MBOX_LOAD_RAM */ + ISPOPMAP(0x03, 0x01), /* 0x02: MBOX_EXEC_FIRMWARE */ + ISPOPMAP(0xdf, 0x01), /* 0x03: MBOX_DUMP_RAM */ + ISPOPMAP(0x07, 0x07), /* 0x04: MBOX_WRITE_RAM_WORD */ + ISPOPMAP(0x03, 0x07), /* 0x05: MBOX_READ_RAM_WORD */ + ISPOPMAP(0xff, 0xff), /* 0x06: MBOX_MAILBOX_REG_TEST */ + ISPOPMAP(0x03, 0x05), /* 0x07: MBOX_VERIFY_CHECKSUM */ + ISPOPMAP(0x01, 0x4f), /* 0x08: MBOX_ABOUT_FIRMWARE */ + ISPOPMAP(0xdf, 0x01), /* 0x09: LOAD RAM */ + ISPOPMAP(0xdf, 0x01), /* 0x0a: DUMP RAM */ + ISPOPMAP(0x00, 0x00), /* 0x0b: */ + ISPOPMAP(0x00, 0x00), /* 0x0c: */ + ISPOPMAP(0x00, 0x00), /* 0x0d: */ + ISPOPMAP(0x01, 0x05), /* 0x0e: MBOX_CHECK_FIRMWARE */ + ISPOPMAP(0x03, 0x07), /* 0x0f: MBOX_READ_RAM_WORD_EXTENDED(1) */ + ISPOPMAP(0x1f, 0x11), /* 0x10: MBOX_INIT_REQ_QUEUE */ + ISPOPMAP(0x2f, 0x21), /* 0x11: MBOX_INIT_RES_QUEUE */ + ISPOPMAP(0x0f, 0x01), /* 0x12: MBOX_EXECUTE_IOCB */ + ISPOPMAP(0x03, 0x03), /* 0x13: MBOX_WAKE_UP */ + ISPOPMAP(0x01, 0xff), /* 0x14: MBOX_STOP_FIRMWARE */ + ISPOPMAP(0x4f, 0x01), /* 0x15: MBOX_ABORT */ + ISPOPMAP(0x07, 0x01), /* 0x16: MBOX_ABORT_DEVICE */ + ISPOPMAP(0x07, 0x01), /* 0x17: MBOX_ABORT_TARGET */ + ISPOPMAP(0x03, 0x03), /* 0x18: MBOX_BUS_RESET */ + ISPOPMAP(0x07, 0x05), /* 0x19: MBOX_STOP_QUEUE */ + ISPOPMAP(0x07, 0x05), /* 0x1a: MBOX_START_QUEUE */ + ISPOPMAP(0x07, 0x05), /* 0x1b: MBOX_SINGLE_STEP_QUEUE */ + ISPOPMAP(0x07, 0x05), /* 0x1c: MBOX_ABORT_QUEUE */ + ISPOPMAP(0x07, 0x03), /* 0x1d: MBOX_GET_DEV_QUEUE_STATUS */ + ISPOPMAP(0x00, 0x00), /* 0x1e: */ + ISPOPMAP(0x01, 0x07), /* 0x1f: MBOX_GET_FIRMWARE_STATUS */ + ISPOPMAP(0x01, 0x4f), /* 0x20: MBOX_GET_LOOP_ID */ + ISPOPMAP(0x00, 0x00), /* 0x21: */ + ISPOPMAP(0x01, 0x07), /* 0x22: MBOX_GET_RETRY_COUNT */ + ISPOPMAP(0x00, 0x00), /* 0x23: */ + ISPOPMAP(0x00, 0x00), /* 0x24: */ + ISPOPMAP(0x00, 0x00), /* 0x25: */ + ISPOPMAP(0x00, 0x00), /* 0x26: */ + ISPOPMAP(0x00, 0x00), /* 0x27: */ + ISPOPMAP(0x01, 0x03), /* 0x28: MBOX_GET_FIRMWARE_OPTIONS */ + ISPOPMAP(0x03, 0x07), /* 0x29: MBOX_GET_PORT_QUEUE_PARAMS */ + ISPOPMAP(0x00, 0x00), /* 0x2a: */ + ISPOPMAP(0x00, 0x00), /* 0x2b: */ + ISPOPMAP(0x00, 0x00), /* 0x2c: */ + ISPOPMAP(0x00, 0x00), /* 0x2d: */ + ISPOPMAP(0x00, 0x00), /* 0x2e: */ + ISPOPMAP(0x00, 0x00), /* 0x2f: */ + ISPOPMAP(0x00, 0x00), /* 0x30: */ + ISPOPMAP(0x00, 0x00), /* 0x31: */ + ISPOPMAP(0x07, 0x07), /* 0x32: MBOX_SET_RETRY_COUNT */ + ISPOPMAP(0x00, 0x00), /* 0x33: */ + ISPOPMAP(0x00, 0x00), /* 0x34: */ + ISPOPMAP(0x00, 0x00), /* 0x35: */ + ISPOPMAP(0x00, 0x00), /* 0x36: */ + ISPOPMAP(0x00, 0x00), /* 0x37: */ + ISPOPMAP(0x0f, 0x01), /* 0x38: MBOX_SET_FIRMWARE_OPTIONS */ + ISPOPMAP(0x0f, 0x07), /* 0x39: MBOX_SET_PORT_QUEUE_PARAMS */ + ISPOPMAP(0x00, 0x00), /* 0x3a: */ + ISPOPMAP(0x00, 0x00), /* 0x3b: */ + ISPOPMAP(0x00, 0x00), /* 0x3c: */ + ISPOPMAP(0x00, 0x00), /* 0x3d: */ + ISPOPMAP(0x00, 0x00), /* 0x3e: */ + ISPOPMAP(0x00, 0x00), /* 0x3f: */ + ISPOPMAP(0x03, 0x01), /* 0x40: MBOX_LOOP_PORT_BYPASS */ + ISPOPMAP(0x03, 0x01), /* 0x41: MBOX_LOOP_PORT_ENABLE */ + ISPOPMAP(0x03, 0x07), /* 0x42: MBOX_GET_RESOURCE_COUNTS */ + ISPOPMAP(0x01, 0x01), /* 0x43: MBOX_REQUEST_NON_PARTICIPATING_MODE */ + ISPOPMAP(0x00, 0x00), /* 0x44: */ + ISPOPMAP(0x00, 0x00), /* 0x45: */ + ISPOPMAP(0x00, 0x00), /* 0x46: */ + ISPOPMAP(0xcf, 0x03), /* 0x47: GET PORT_DATABASE ENHANCED */ + ISPOPMAP(0x00, 0x00), /* 0x48: */ + ISPOPMAP(0x00, 0x00), /* 0x49: */ + ISPOPMAP(0x00, 0x00), /* 0x4a: */ + ISPOPMAP(0x00, 0x00), /* 0x4b: */ + ISPOPMAP(0x00, 0x00), /* 0x4c: */ + ISPOPMAP(0x00, 0x00), /* 0x4d: */ + ISPOPMAP(0x00, 0x00), /* 0x4e: */ + ISPOPMAP(0x00, 0x00), /* 0x4f: */ + ISPOPMAP(0x00, 0x00), /* 0x50: */ + ISPOPMAP(0x00, 0x00), /* 0x51: */ + ISPOPMAP(0x00, 0x00), /* 0x52: */ + ISPOPMAP(0x00, 0x00), /* 0x53: */ + ISPOPMAP(0xcf, 0x01), /* 0x54: EXECUTE IOCB A64 */ + ISPOPMAP(0x00, 0x00), /* 0x55: */ + ISPOPMAP(0x00, 0x00), /* 0x56: */ + ISPOPMAP(0x00, 0x00), /* 0x57: */ + ISPOPMAP(0x00, 0x00), /* 0x58: */ + ISPOPMAP(0x00, 0x00), /* 0x59: */ + ISPOPMAP(0x00, 0x00), /* 0x5a: */ + ISPOPMAP(0x03, 0x01), /* 0x5b: MBOX_DRIVER_HEARTBEAT */ + ISPOPMAP(0xcf, 0x01), /* 0x5c: MBOX_FW_HEARTBEAT */ + ISPOPMAP(0x07, 0x03), /* 0x5d: MBOX_GET_SET_DATA_RATE */ + ISPOPMAP(0x00, 0x00), /* 0x5e: */ + ISPOPMAP(0x00, 0x00), /* 0x5f: */ + ISPOPMAP(0xfd, 0x31), /* 0x60: MBOX_INIT_FIRMWARE */ + ISPOPMAP(0x00, 0x00), /* 0x61: */ + ISPOPMAP(0x01, 0x01), /* 0x62: MBOX_INIT_LIP */ + ISPOPMAP(0xcd, 0x03), /* 0x63: MBOX_GET_FC_AL_POSITION_MAP */ + ISPOPMAP(0xcf, 0x01), /* 0x64: MBOX_GET_PORT_DB */ + ISPOPMAP(0x07, 0x01), /* 0x65: MBOX_CLEAR_ACA */ + ISPOPMAP(0x07, 0x01), /* 0x66: MBOX_TARGET_RESET */ + ISPOPMAP(0x07, 0x01), /* 0x67: MBOX_CLEAR_TASK_SET */ + ISPOPMAP(0x07, 0x01), /* 0x68: MBOX_ABORT_TASK_SET */ + ISPOPMAP(0x01, 0x07), /* 0x69: MBOX_GET_FW_STATE */ + ISPOPMAP(0x03, 0xcf), /* 0x6a: MBOX_GET_PORT_NAME */ + ISPOPMAP(0xcf, 0x01), /* 0x6b: MBOX_GET_LINK_STATUS */ + ISPOPMAP(0x0f, 0x01), /* 0x6c: MBOX_INIT_LIP_RESET */ + ISPOPMAP(0x00, 0x00), /* 0x6d: */ + ISPOPMAP(0xcf, 0x03), /* 0x6e: MBOX_SEND_SNS */ + ISPOPMAP(0x0f, 0x07), /* 0x6f: MBOX_FABRIC_LOGIN */ + ISPOPMAP(0x03, 0x01), /* 0x70: MBOX_SEND_CHANGE_REQUEST */ + ISPOPMAP(0x03, 0x03), /* 0x71: MBOX_FABRIC_LOGOUT */ + ISPOPMAP(0x0f, 0x0f), /* 0x72: MBOX_INIT_LIP_LOGIN */ + ISPOPMAP(0x00, 0x00), /* 0x73: */ + ISPOPMAP(0x07, 0x01), /* 0x74: LOGIN LOOP PORT */ + ISPOPMAP(0xcf, 0x03), /* 0x75: GET PORT/NODE NAME LIST */ + ISPOPMAP(0x4f, 0x01), /* 0x76: SET VENDOR ID */ + ISPOPMAP(0xcd, 0x01), /* 0x77: INITIALIZE IP MAILBOX */ + ISPOPMAP(0x00, 0x00), /* 0x78: */ + ISPOPMAP(0x00, 0x00), /* 0x79: */ + ISPOPMAP(0x00, 0x00), /* 0x7a: */ + ISPOPMAP(0x00, 0x00), /* 0x7b: */ + ISPOPMAP(0x4f, 0x03), /* 0x7c: Get ID List */ + ISPOPMAP(0xcf, 0x01), /* 0x7d: SEND LFA */ + ISPOPMAP(0x07, 0x01) /* 0x7e: Lun RESET */ +}; +/* + * Footnotes + * + * (1): this sets bits 21..16 in mailbox register #8, which we nominally + * do not access at this time in the core driver. The caller is + * responsible for setting this register first (Gross!). + */ + +#ifndef ISP_STRIPPED +static char *fc_mbcmd_names[] = { + "NO-OP", + "LOAD RAM", + "EXEC FIRMWARE", + "DUMP RAM", + "WRITE RAM WORD", + "READ RAM WORD", + "MAILBOX REG TEST", + "VERIFY CHECKSUM", + "ABOUT FIRMWARE", + "LOAD RAM", + "DUMP RAM", + NULL, + NULL, + "READ RAM WORD EXTENDED", + "CHECK FIRMWARE", + NULL, + "INIT REQUEST QUEUE", + "INIT RESULT QUEUE", + "EXECUTE IOCB", + "WAKE UP", + "STOP FIRMWARE", + "ABORT", + "ABORT DEVICE", + "ABORT TARGET", + "BUS RESET", + "STOP QUEUE", + "START QUEUE", + "SINGLE STEP QUEUE", + "ABORT QUEUE", + "GET DEV QUEUE STATUS", + NULL, + "GET FIRMWARE STATUS", + "GET LOOP ID", + NULL, + "GET RETRY COUNT", + NULL, + NULL, + NULL, + NULL, + NULL, + "GET FIRMWARE OPTIONS", + "GET PORT QUEUE PARAMS", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "SET RETRY COUNT", + NULL, + NULL, + NULL, + NULL, + NULL, + "SET FIRMWARE OPTIONS", + "SET PORT QUEUE PARAMS", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "LOOP PORT BYPASS", + "LOOP PORT ENABLE", + "GET RESOURCE COUNTS", + "REQUEST NON PARTICIPATING MODE", + NULL, + NULL, + NULL, + "GET PORT DATABASE,, ENHANCED", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "EXECUTE IOCB A64", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "DRIVER HEARTBEAT", + NULL, + "GET/SET DATA RATE", + NULL, + NULL, + "INIT FIRMWARE", + NULL, + "INIT LIP", + "GET FC-AL POSITION MAP", + "GET PORT DATABASE", + "CLEAR ACA", + "TARGET RESET", + "CLEAR TASK SET", + "ABORT TASK SET", + "GET FW STATE", + "GET PORT NAME", + "GET LINK STATUS", + "INIT LIP RESET", + NULL, + "SEND SNS", + "FABRIC LOGIN", + "SEND CHANGE REQUEST", + "FABRIC LOGOUT", + "INIT LIP LOGIN", + NULL, + "LOGIN LOOP PORT", + "GET PORT/NODE NAME LIST", + "SET VENDOR ID", + "INITIALIZE IP MAILBOX", + NULL, + NULL, + NULL, + NULL, + "Get ID List", + "SEND LFA", + "Lun RESET" +}; +#endif + +static void +isp_mboxcmd_qnw(struct ispsoftc *isp, mbreg_t *mbp, int nodelay) +{ + unsigned int lim, ibits, obits, box, opcode; + u_int16_t *mcp; + + if (IS_FC(isp)) { + mcp = mbpfc; + lim = (sizeof (mbpfc) / sizeof (mbpfc[0])); + } else { + mcp = mbpscsi; + lim = (sizeof (mbpscsi) / sizeof (mbpscsi[0])); + } + opcode = mbp->param[0]; + ibits = HIBYT(mcp[opcode]) & NMBOX_BMASK(isp); + obits = LOBYT(mcp[opcode]) & NMBOX_BMASK(isp); + for (box = 0; box < MAX_MAILBOX; box++) { + if (ibits & (1 << box)) { + ISP_WRITE(isp, MBOX_OFF(box), mbp->param[box]); + } + if (nodelay == 0) { + isp->isp_mboxtmp[box] = mbp->param[box] = 0; + } + } + if (nodelay == 0) { + isp->isp_lastmbxcmd = opcode; + isp->isp_obits = obits; + isp->isp_mboxbsy = 1; + } + ISP_WRITE(isp, HCCR, HCCR_CMD_SET_HOST_INT); + /* + * Oddly enough, if we're not delaying for an answer, + * delay a bit to give the f/w a chance to pick up the + * command. + */ + if (nodelay) { + USEC_DELAY(1000); + } +} + +static void +isp_mboxcmd(struct ispsoftc *isp, mbreg_t *mbp, int logmask) +{ + char *cname, *xname, tname[16], mname[16]; + unsigned int lim, ibits, obits, box, opcode; + u_int16_t *mcp; + + if (IS_FC(isp)) { + mcp = mbpfc; + lim = (sizeof (mbpfc) / sizeof (mbpfc[0])); + } else { + mcp = mbpscsi; + lim = (sizeof (mbpscsi) / sizeof (mbpscsi[0])); + } + + if ((opcode = mbp->param[0]) >= lim) { + mbp->param[0] = MBOX_INVALID_COMMAND; + isp_prt(isp, ISP_LOGERR, "Unknown Command 0x%x", opcode); + return; + } + + ibits = HIBYT(mcp[opcode]) & NMBOX_BMASK(isp); + obits = LOBYT(mcp[opcode]) & NMBOX_BMASK(isp); + + if (ibits == 0 && obits == 0) { + mbp->param[0] = MBOX_COMMAND_PARAM_ERROR; + isp_prt(isp, ISP_LOGERR, "no parameters for 0x%x", opcode); + return; + } + + /* + * Get exclusive usage of mailbox registers. + */ + MBOX_ACQUIRE(isp); + + for (box = 0; box < MAX_MAILBOX; box++) { + if (ibits & (1 << box)) { + ISP_WRITE(isp, MBOX_OFF(box), mbp->param[box]); + } + isp->isp_mboxtmp[box] = mbp->param[box] = 0; + } + + isp->isp_lastmbxcmd = opcode; + + /* + * We assume that we can't overwrite a previous command. + */ + isp->isp_obits = obits; + isp->isp_mboxbsy = 1; + + /* + * Set Host Interrupt condition so that RISC will pick up mailbox regs. + */ + ISP_WRITE(isp, HCCR, HCCR_CMD_SET_HOST_INT); + + /* + * While we haven't finished the command, spin our wheels here. + */ + MBOX_WAIT_COMPLETE(isp); + + if (isp->isp_mboxbsy) { + /* + * Command timed out. + */ + isp->isp_mboxbsy = 0; + MBOX_RELEASE(isp); + return; + } + + /* + * Copy back output registers. + */ + for (box = 0; box < MAX_MAILBOX; box++) { + if (obits & (1 << box)) { + mbp->param[box] = isp->isp_mboxtmp[box]; + } + } + + MBOX_RELEASE(isp); + + if (logmask == 0 || opcode == MBOX_EXEC_FIRMWARE) { + return; + } +#ifdef ISP_STRIPPED + cname = NULL; +#else + cname = (IS_FC(isp))? fc_mbcmd_names[opcode] : scsi_mbcmd_names[opcode]; +#endif + if (cname == NULL) { + cname = tname; + SNPRINTF(tname, sizeof tname, "opcode %x", opcode); + } + + /* + * Just to be chatty here... + */ + xname = NULL; + switch (mbp->param[0]) { + case MBOX_COMMAND_COMPLETE: + break; + case MBOX_INVALID_COMMAND: + if (logmask & MBLOGMASK(MBOX_COMMAND_COMPLETE)) + xname = "INVALID COMMAND"; + break; + case MBOX_HOST_INTERFACE_ERROR: + if (logmask & MBLOGMASK(MBOX_HOST_INTERFACE_ERROR)) + xname = "HOST INTERFACE ERROR"; + break; + case MBOX_TEST_FAILED: + if (logmask & MBLOGMASK(MBOX_TEST_FAILED)) + xname = "TEST FAILED"; + break; + case MBOX_COMMAND_ERROR: + if (logmask & MBLOGMASK(MBOX_COMMAND_ERROR)) + xname = "COMMAND ERROR"; + break; + case MBOX_COMMAND_PARAM_ERROR: + if (logmask & MBLOGMASK(MBOX_COMMAND_PARAM_ERROR)) + xname = "COMMAND PARAMETER ERROR"; + break; + case MBOX_LOOP_ID_USED: + if (logmask & MBLOGMASK(MBOX_LOOP_ID_USED)) + xname = "LOOP ID ALREADY IN USE"; + break; + case MBOX_PORT_ID_USED: + if (logmask & MBLOGMASK(MBOX_PORT_ID_USED)) + xname = "PORT ID ALREADY IN USE"; + break; + case MBOX_ALL_IDS_USED: + if (logmask & MBLOGMASK(MBOX_ALL_IDS_USED)) + xname = "ALL LOOP IDS IN USE"; + break; + case 0: /* special case */ + xname = "TIMEOUT"; + break; + default: + SNPRINTF(mname, sizeof mname, "error 0x%x", mbp->param[0]); + xname = mname; + break; + } + if (xname) + isp_prt(isp, ISP_LOGALL, "Mailbox Command '%s' failed (%s)", + cname, xname); +} + +static void +isp_fw_state(struct ispsoftc *isp) +{ + if (IS_FC(isp)) { + mbreg_t mbs; + fcparam *fcp = isp->isp_param; + + mbs.param[0] = MBOX_GET_FW_STATE; + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (mbs.param[0] == MBOX_COMMAND_COMPLETE) { + fcp->isp_fwstate = mbs.param[1]; + } + } +} + +static void +isp_update(struct ispsoftc *isp) +{ + int bus, upmask; + + for (bus = 0, upmask = isp->isp_update; upmask != 0; bus++) { + if (upmask & (1 << bus)) { + isp_update_bus(isp, bus); + } + upmask &= ~(1 << bus); + } +} + +static void +isp_update_bus(struct ispsoftc *isp, int bus) +{ + int tgt; + mbreg_t mbs; + sdparam *sdp; + + isp->isp_update &= ~(1 << bus); + if (IS_FC(isp)) { + /* + * There are no 'per-bus' settings for Fibre Channel. + */ + return; + } + sdp = isp->isp_param; + sdp += bus; + + for (tgt = 0; tgt < MAX_TARGETS; tgt++) { + u_int16_t flags, period, offset; + int get; + + if (sdp->isp_devparam[tgt].dev_enable == 0) { + sdp->isp_devparam[tgt].dev_update = 0; + sdp->isp_devparam[tgt].dev_refresh = 0; + isp_prt(isp, ISP_LOGDEBUG0, + "skipping target %d bus %d update", tgt, bus); + continue; + } + /* + * If the goal is to update the status of the device, + * take what's in goal_flags and try and set the device + * toward that. Otherwise, if we're just refreshing the + * current device state, get the current parameters. + */ + + /* + * Refresh overrides set + */ + if (sdp->isp_devparam[tgt].dev_refresh) { + mbs.param[0] = MBOX_GET_TARGET_PARAMS; + sdp->isp_devparam[tgt].dev_refresh = 0; + get = 1; + } else if (sdp->isp_devparam[tgt].dev_update) { + mbs.param[0] = MBOX_SET_TARGET_PARAMS; + /* + * Make sure goal_flags has "Renegotiate on Error" + * on and "Freeze Queue on Error" off. + */ + sdp->isp_devparam[tgt].goal_flags |= DPARM_RENEG; + sdp->isp_devparam[tgt].goal_flags &= ~DPARM_QFRZ; + + mbs.param[2] = sdp->isp_devparam[tgt].goal_flags; + + /* + * Insist that PARITY must be enabled + * if SYNC or WIDE is enabled. + */ + if ((mbs.param[2] & (DPARM_SYNC|DPARM_WIDE)) != 0) { + mbs.param[2] |= DPARM_PARITY; + } + + if ((mbs.param[2] & DPARM_SYNC) == 0) { + mbs.param[3] = 0; + } else { + mbs.param[3] = + (sdp->isp_devparam[tgt].goal_offset << 8) | + (sdp->isp_devparam[tgt].goal_period); + } + /* + * A command completion later that has + * RQSTF_NEGOTIATION set can cause + * the dev_refresh/announce cycle also. + * + * Note: It is really important to update our current + * flags with at least the state of TAG capabilities- + * otherwise we might try and send a tagged command + * when we have it all turned off. So change it here + * to say that current already matches goal. + */ + sdp->isp_devparam[tgt].actv_flags &= ~DPARM_TQING; + sdp->isp_devparam[tgt].actv_flags |= + (sdp->isp_devparam[tgt].goal_flags & DPARM_TQING); + isp_prt(isp, ISP_LOGDEBUG0, + "bus %d set tgt %d flags 0x%x off 0x%x period 0x%x", + bus, tgt, mbs.param[2], mbs.param[3] >> 8, + mbs.param[3] & 0xff); + sdp->isp_devparam[tgt].dev_update = 0; + sdp->isp_devparam[tgt].dev_refresh = 1; + get = 0; + } else { + continue; + } + mbs.param[1] = (bus << 15) | (tgt << 8); + isp_mboxcmd(isp, &mbs, MBLOGALL); + if (get == 0) { + isp->isp_sendmarker |= (1 << bus); + continue; + } + flags = mbs.param[2]; + period = mbs.param[3] & 0xff; + offset = mbs.param[3] >> 8; + sdp->isp_devparam[tgt].actv_flags = flags; + sdp->isp_devparam[tgt].actv_period = period; + sdp->isp_devparam[tgt].actv_offset = offset; + get = (bus << 16) | tgt; + (void) isp_async(isp, ISPASYNC_NEW_TGT_PARAMS, &get); + } + + for (tgt = 0; tgt < MAX_TARGETS; tgt++) { + if (sdp->isp_devparam[tgt].dev_update || + sdp->isp_devparam[tgt].dev_refresh) { + isp->isp_update |= (1 << bus); + break; + } + } +} + +#ifndef DEFAULT_FRAMESIZE +#define DEFAULT_FRAMESIZE(isp) ICB_DFLT_FRMLEN +#endif +#ifndef DEFAULT_EXEC_THROTTLE +#define DEFAULT_EXEC_THROTTLE(isp) ISP_EXEC_THROTTLE +#endif + +static void +isp_setdfltparm(struct ispsoftc *isp, int channel) +{ + int tgt; + mbreg_t mbs; + sdparam *sdp; + + if (IS_FC(isp)) { + fcparam *fcp = (fcparam *) isp->isp_param; + int nvfail; + + fcp += channel; + if (fcp->isp_gotdparms) { + return; + } + fcp->isp_gotdparms = 1; + fcp->isp_maxfrmlen = DEFAULT_FRAMESIZE(isp); + fcp->isp_maxalloc = ICB_DFLT_ALLOC; + fcp->isp_execthrottle = DEFAULT_EXEC_THROTTLE(isp); + fcp->isp_retry_delay = ICB_DFLT_RDELAY; + fcp->isp_retry_count = ICB_DFLT_RCOUNT; + /* Platform specific.... */ + fcp->isp_loopid = DEFAULT_LOOPID(isp); + fcp->isp_nodewwn = DEFAULT_NODEWWN(isp); + fcp->isp_portwwn = DEFAULT_PORTWWN(isp); + fcp->isp_fwoptions = 0; + fcp->isp_fwoptions |= ICBOPT_FAIRNESS; + fcp->isp_fwoptions |= ICBOPT_PDBCHANGE_AE; + fcp->isp_fwoptions |= ICBOPT_HARD_ADDRESS; +#ifndef ISP_NO_FASTPOST_FC + fcp->isp_fwoptions |= ICBOPT_FAST_POST; +#endif + if (isp->isp_confopts & ISP_CFG_FULL_DUPLEX) + fcp->isp_fwoptions |= ICBOPT_FULL_DUPLEX; + + /* + * Make sure this is turned off now until we get + * extended options from NVRAM + */ + fcp->isp_fwoptions &= ~ICBOPT_EXTENDED; + + /* + * Now try and read NVRAM unless told to not do so. + * This will set fcparam's isp_nodewwn && isp_portwwn. + */ + if ((isp->isp_confopts & ISP_CFG_NONVRAM) == 0) { + nvfail = isp_read_nvram(isp); + if (nvfail) + isp->isp_confopts |= ISP_CFG_NONVRAM; + } else { + nvfail = 1; + } + /* + * Set node && port to override platform set defaults + * unless the nvram read failed (or none was done), + * or the platform code wants to use what had been + * set in the defaults. + */ + if (nvfail) { + isp->isp_confopts |= ISP_CFG_OWNWWPN|ISP_CFG_OWNWWNN; + } + if (isp->isp_confopts & ISP_CFG_OWNWWNN) { + isp_prt(isp, ISP_LOGCONFIG, "Using Node WWN 0x%08x%08x", + (u_int32_t) (DEFAULT_NODEWWN(isp) >> 32), + (u_int32_t) (DEFAULT_NODEWWN(isp) & 0xffffffff)); + ISP_NODEWWN(isp) = DEFAULT_NODEWWN(isp); + } else { + /* + * We always start out with values derived + * from NVRAM or our platform default. + */ + ISP_NODEWWN(isp) = fcp->isp_nodewwn; + } + if (isp->isp_confopts & ISP_CFG_OWNWWPN) { + isp_prt(isp, ISP_LOGCONFIG, "Using Port WWN 0x%08x%08x", + (u_int32_t) (DEFAULT_PORTWWN(isp) >> 32), + (u_int32_t) (DEFAULT_PORTWWN(isp) & 0xffffffff)); + ISP_PORTWWN(isp) = DEFAULT_PORTWWN(isp); + } else { + /* + * We always start out with values derived + * from NVRAM or our platform default. + */ + ISP_PORTWWN(isp) = fcp->isp_portwwn; + } + return; + } + + sdp = (sdparam *) isp->isp_param; + sdp += channel; + + /* + * Been there, done that, got the T-shirt... + */ + if (sdp->isp_gotdparms) { + return; + } + sdp->isp_gotdparms = 1; + + /* + * Establish some default parameters. + */ + sdp->isp_cmd_dma_burst_enable = 0; + sdp->isp_data_dma_burst_enabl = 1; + sdp->isp_fifo_threshold = 0; + sdp->isp_initiator_id = DEFAULT_IID(isp); + if (isp->isp_type >= ISP_HA_SCSI_1040) { + sdp->isp_async_data_setup = 9; + } else { + sdp->isp_async_data_setup = 6; + } + sdp->isp_selection_timeout = 250; + sdp->isp_max_queue_depth = MAXISPREQUEST(isp); + sdp->isp_tag_aging = 8; + sdp->isp_bus_reset_delay = 5; + /* + * Don't retry selection, busy or queue full automatically- reflect + * these back to us. + */ + sdp->isp_retry_count = 0; + sdp->isp_retry_delay = 0; + + for (tgt = 0; tgt < MAX_TARGETS; tgt++) { + sdp->isp_devparam[tgt].exc_throttle = ISP_EXEC_THROTTLE; + sdp->isp_devparam[tgt].dev_enable = 1; + } + + /* + * If we've not been told to avoid reading NVRAM, try and read it. + * If we're successful reading it, we can then return because NVRAM + * will tell us what the desired settings are. Otherwise, we establish + * some reasonable 'fake' nvram and goal defaults. + */ + + if ((isp->isp_confopts & ISP_CFG_NONVRAM) == 0) { + if (isp_read_nvram(isp) == 0) { + return; + } + } + + /* + * Now try and see whether we have specific values for them. + */ + if ((isp->isp_confopts & ISP_CFG_NONVRAM) == 0) { + mbs.param[0] = MBOX_GET_ACT_NEG_STATE; + isp_mboxcmd(isp, &mbs, MBLOGNONE); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + sdp->isp_req_ack_active_neg = 1; + sdp->isp_data_line_active_neg = 1; + } else { + sdp->isp_req_ack_active_neg = + (mbs.param[1+channel] >> 4) & 0x1; + sdp->isp_data_line_active_neg = + (mbs.param[1+channel] >> 5) & 0x1; + } + } + + isp_prt(isp, ISP_LOGDEBUG0, sc0, sc3, + 0, sdp->isp_fifo_threshold, sdp->isp_initiator_id, + sdp->isp_bus_reset_delay, sdp->isp_retry_count, + sdp->isp_retry_delay, sdp->isp_async_data_setup); + isp_prt(isp, ISP_LOGDEBUG0, sc1, sc3, + sdp->isp_req_ack_active_neg, sdp->isp_data_line_active_neg, + sdp->isp_data_dma_burst_enabl, sdp->isp_cmd_dma_burst_enable, + sdp->isp_selection_timeout, sdp->isp_max_queue_depth); + + /* + * The trick here is to establish a default for the default (honk!) + * state (goal_flags). Then try and get the current status from + * the card to fill in the current state. We don't, in fact, set + * the default to the SAFE default state- that's not the goal state. + */ + for (tgt = 0; tgt < MAX_TARGETS; tgt++) { + u_int8_t off, per; + sdp->isp_devparam[tgt].actv_offset = 0; + sdp->isp_devparam[tgt].actv_period = 0; + sdp->isp_devparam[tgt].actv_flags = 0; + + sdp->isp_devparam[tgt].goal_flags = + sdp->isp_devparam[tgt].nvrm_flags = DPARM_DEFAULT; + + /* + * We default to Wide/Fast for versions less than a 1040 + * (unless it's SBus). + */ + if (IS_ULTRA3(isp)) { + off = ISP_80M_SYNCPARMS >> 8; + per = ISP_80M_SYNCPARMS & 0xff; + } else if (IS_ULTRA2(isp)) { + off = ISP_40M_SYNCPARMS >> 8; + per = ISP_40M_SYNCPARMS & 0xff; + } else if (IS_1240(isp)) { + off = ISP_20M_SYNCPARMS >> 8; + per = ISP_20M_SYNCPARMS & 0xff; + } else if ((isp->isp_bustype == ISP_BT_SBUS && + isp->isp_type < ISP_HA_SCSI_1020A) || + (isp->isp_bustype == ISP_BT_PCI && + isp->isp_type < ISP_HA_SCSI_1040) || + (isp->isp_clock && isp->isp_clock < 60) || + (sdp->isp_ultramode == 0)) { + off = ISP_10M_SYNCPARMS >> 8; + per = ISP_10M_SYNCPARMS & 0xff; + } else { + off = ISP_20M_SYNCPARMS_1040 >> 8; + per = ISP_20M_SYNCPARMS_1040 & 0xff; + } + sdp->isp_devparam[tgt].goal_offset = + sdp->isp_devparam[tgt].nvrm_offset = off; + sdp->isp_devparam[tgt].goal_period = + sdp->isp_devparam[tgt].nvrm_period = per; + + isp_prt(isp, ISP_LOGDEBUG0, sc2, sc3, + channel, tgt, sdp->isp_devparam[tgt].nvrm_flags, + sdp->isp_devparam[tgt].nvrm_offset, + sdp->isp_devparam[tgt].nvrm_period); + } +} + +/* + * Re-initialize the ISP and complete all orphaned commands + * with a 'botched' notice. The reset/init routines should + * not disturb an already active list of commands. + * + * Locks held prior to coming here. + */ + +void +isp_reinit(struct ispsoftc *isp) +{ + XS_T *xs; + u_int16_t handle; + + isp_reset(isp); + if (isp->isp_state != ISP_RESETSTATE) { + isp_prt(isp, ISP_LOGERR, "isp_reinit cannot reset card"); + } else if (isp->isp_role != ISP_ROLE_NONE) { + isp_init(isp); + if (isp->isp_state == ISP_INITSTATE) { + isp->isp_state = ISP_RUNSTATE; + } + if (isp->isp_state != ISP_RUNSTATE) { + isp_prt(isp, ISP_LOGERR, + "isp_reinit cannot restart card"); + } + } + isp->isp_nactive = 0; + + for (handle = 1; (int) handle <= isp->isp_maxcmds; handle++) { + xs = isp_find_xs(isp, handle); + if (xs == NULL) { + continue; + } + isp_destroy_handle(isp, handle); + if (XS_XFRLEN(xs)) { + ISP_DMAFREE(isp, xs, handle); + XS_RESID(xs) = XS_XFRLEN(xs); + } else { + XS_RESID(xs) = 0; + } + XS_SETERR(xs, HBA_BUSRESET); + isp_done(xs); + } +} + +/* + * NVRAM Routines + */ +static int +isp_read_nvram(struct ispsoftc *isp) +{ + int i, amt; + u_int8_t csum, minversion; + union { + u_int8_t _x[ISP2100_NVRAM_SIZE]; + u_int16_t _s[ISP2100_NVRAM_SIZE>>1]; + } _n; +#define nvram_data _n._x +#define nvram_words _n._s + + if (IS_FC(isp)) { + amt = ISP2100_NVRAM_SIZE; + minversion = 1; + } else if (IS_ULTRA2(isp)) { + amt = ISP1080_NVRAM_SIZE; + minversion = 0; + } else { + amt = ISP_NVRAM_SIZE; + minversion = 2; + } + + /* + * Just read the first two words first to see if we have a valid + * NVRAM to continue reading the rest with. + */ + for (i = 0; i < 2; i++) { + isp_rdnvram_word(isp, i, &nvram_words[i]); + } + if (nvram_data[0] != 'I' || nvram_data[1] != 'S' || + nvram_data[2] != 'P') { + if (isp->isp_bustype != ISP_BT_SBUS) { + isp_prt(isp, ISP_LOGWARN, "invalid NVRAM header"); + isp_prt(isp, ISP_LOGDEBUG0, "%x %x %x", + nvram_data[0], nvram_data[1], nvram_data[2]); + } + return (-1); + } + for (i = 2; i < amt>>1; i++) { + isp_rdnvram_word(isp, i, &nvram_words[i]); + } + for (csum = 0, i = 0; i < amt; i++) { + csum += nvram_data[i]; + } + if (csum != 0) { + isp_prt(isp, ISP_LOGWARN, "invalid NVRAM checksum"); + return (-1); + } + if (ISP_NVRAM_VERSION(nvram_data) < minversion) { + isp_prt(isp, ISP_LOGWARN, "version %d NVRAM not understood", + ISP_NVRAM_VERSION(nvram_data)); + return (-1); + } + + if (IS_ULTRA3(isp)) { + isp_parse_nvram_12160(isp, 0, nvram_data); + if (IS_12160(isp)) + isp_parse_nvram_12160(isp, 1, nvram_data); + } else if (IS_1080(isp)) { + isp_parse_nvram_1080(isp, 0, nvram_data); + } else if (IS_1280(isp) || IS_1240(isp)) { + isp_parse_nvram_1080(isp, 0, nvram_data); + isp_parse_nvram_1080(isp, 1, nvram_data); + } else if (IS_SCSI(isp)) { + isp_parse_nvram_1020(isp, nvram_data); + } else { + isp_parse_nvram_2100(isp, nvram_data); + } + return (0); +#undef nvram_data +#undef nvram_words +} + +static void +isp_rdnvram_word(struct ispsoftc *isp, int wo, u_int16_t *rp) +{ + int i, cbits; + u_int16_t bit, rqst; + + ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT); + USEC_DELAY(2); + ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT|BIU_NVRAM_CLOCK); + USEC_DELAY(2); + + if (IS_FC(isp)) { + wo &= ((ISP2100_NVRAM_SIZE >> 1) - 1); + if (IS_2312(isp) && isp->isp_port) { + wo += 128; + } + rqst = (ISP_NVRAM_READ << 8) | wo; + cbits = 10; + } else if (IS_ULTRA2(isp)) { + wo &= ((ISP1080_NVRAM_SIZE >> 1) - 1); + rqst = (ISP_NVRAM_READ << 8) | wo; + cbits = 10; + } else { + wo &= ((ISP_NVRAM_SIZE >> 1) - 1); + rqst = (ISP_NVRAM_READ << 6) | wo; + cbits = 8; + } + + /* + * Clock the word select request out... + */ + for (i = cbits; i >= 0; i--) { + if ((rqst >> i) & 1) { + bit = BIU_NVRAM_SELECT | BIU_NVRAM_DATAOUT; + } else { + bit = BIU_NVRAM_SELECT; + } + ISP_WRITE(isp, BIU_NVRAM, bit); + USEC_DELAY(2); + ISP_WRITE(isp, BIU_NVRAM, bit | BIU_NVRAM_CLOCK); + USEC_DELAY(2); + ISP_WRITE(isp, BIU_NVRAM, bit); + USEC_DELAY(2); + } + /* + * Now read the result back in (bits come back in MSB format). + */ + *rp = 0; + for (i = 0; i < 16; i++) { + u_int16_t rv; + *rp <<= 1; + ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT|BIU_NVRAM_CLOCK); + USEC_DELAY(2); + rv = ISP_READ(isp, BIU_NVRAM); + if (rv & BIU_NVRAM_DATAIN) { + *rp |= 1; + } + USEC_DELAY(2); + ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT); + USEC_DELAY(2); + } + ISP_WRITE(isp, BIU_NVRAM, 0); + USEC_DELAY(2); + ISP_SWIZZLE_NVRAM_WORD(isp, rp); +} + +static void +isp_parse_nvram_1020(struct ispsoftc *isp, u_int8_t *nvram_data) +{ + sdparam *sdp = (sdparam *) isp->isp_param; + int tgt; + + sdp->isp_fifo_threshold = + ISP_NVRAM_FIFO_THRESHOLD(nvram_data) | + (ISP_NVRAM_FIFO_THRESHOLD_128(nvram_data) << 2); + + if ((isp->isp_confopts & ISP_CFG_OWNLOOPID) == 0) + sdp->isp_initiator_id = + ISP_NVRAM_INITIATOR_ID(nvram_data); + + sdp->isp_bus_reset_delay = + ISP_NVRAM_BUS_RESET_DELAY(nvram_data); + + sdp->isp_retry_count = + ISP_NVRAM_BUS_RETRY_COUNT(nvram_data); + + sdp->isp_retry_delay = + ISP_NVRAM_BUS_RETRY_DELAY(nvram_data); + + sdp->isp_async_data_setup = + ISP_NVRAM_ASYNC_DATA_SETUP_TIME(nvram_data); + + if (isp->isp_type >= ISP_HA_SCSI_1040) { + if (sdp->isp_async_data_setup < 9) { + sdp->isp_async_data_setup = 9; + } + } else { + if (sdp->isp_async_data_setup != 6) { + sdp->isp_async_data_setup = 6; + } + } + + sdp->isp_req_ack_active_neg = + ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(nvram_data); + + sdp->isp_data_line_active_neg = + ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(nvram_data); + + sdp->isp_data_dma_burst_enabl = + ISP_NVRAM_DATA_DMA_BURST_ENABLE(nvram_data); + + sdp->isp_cmd_dma_burst_enable = + ISP_NVRAM_CMD_DMA_BURST_ENABLE(nvram_data); + + sdp->isp_tag_aging = + ISP_NVRAM_TAG_AGE_LIMIT(nvram_data); + + sdp->isp_selection_timeout = + ISP_NVRAM_SELECTION_TIMEOUT(nvram_data); + + sdp->isp_max_queue_depth = + ISP_NVRAM_MAX_QUEUE_DEPTH(nvram_data); + + sdp->isp_fast_mttr = ISP_NVRAM_FAST_MTTR_ENABLE(nvram_data); + + isp_prt(isp, ISP_LOGDEBUG0, sc0, sc4, + 0, sdp->isp_fifo_threshold, sdp->isp_initiator_id, + sdp->isp_bus_reset_delay, sdp->isp_retry_count, + sdp->isp_retry_delay, sdp->isp_async_data_setup); + isp_prt(isp, ISP_LOGDEBUG0, sc1, sc4, + sdp->isp_req_ack_active_neg, sdp->isp_data_line_active_neg, + sdp->isp_data_dma_burst_enabl, sdp->isp_cmd_dma_burst_enable, + sdp->isp_selection_timeout, sdp->isp_max_queue_depth); + + for (tgt = 0; tgt < MAX_TARGETS; tgt++) { + sdp->isp_devparam[tgt].dev_enable = + ISP_NVRAM_TGT_DEVICE_ENABLE(nvram_data, tgt); + sdp->isp_devparam[tgt].exc_throttle = + ISP_NVRAM_TGT_EXEC_THROTTLE(nvram_data, tgt); + sdp->isp_devparam[tgt].nvrm_offset = + ISP_NVRAM_TGT_SYNC_OFFSET(nvram_data, tgt); + sdp->isp_devparam[tgt].nvrm_period = + ISP_NVRAM_TGT_SYNC_PERIOD(nvram_data, tgt); + /* + * We probably shouldn't lie about this, but it + * it makes it much safer if we limit NVRAM values + * to sanity. + */ + if (isp->isp_type < ISP_HA_SCSI_1040) { + /* + * If we're not ultra, we can't possibly + * be a shorter period than this. + */ + if (sdp->isp_devparam[tgt].nvrm_period < 0x19) { + sdp->isp_devparam[tgt].nvrm_period = 0x19; + } + if (sdp->isp_devparam[tgt].nvrm_offset > 0xc) { + sdp->isp_devparam[tgt].nvrm_offset = 0x0c; + } + } else { + if (sdp->isp_devparam[tgt].nvrm_offset > 0x8) { + sdp->isp_devparam[tgt].nvrm_offset = 0x8; + } + } + sdp->isp_devparam[tgt].nvrm_flags = 0; + if (ISP_NVRAM_TGT_RENEG(nvram_data, tgt)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_RENEG; + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_ARQ; + if (ISP_NVRAM_TGT_TQING(nvram_data, tgt)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_TQING; + if (ISP_NVRAM_TGT_SYNC(nvram_data, tgt)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_SYNC; + if (ISP_NVRAM_TGT_WIDE(nvram_data, tgt)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_WIDE; + if (ISP_NVRAM_TGT_PARITY(nvram_data, tgt)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_PARITY; + if (ISP_NVRAM_TGT_DISC(nvram_data, tgt)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_DISC; + sdp->isp_devparam[tgt].actv_flags = 0; /* we don't know */ + isp_prt(isp, ISP_LOGDEBUG0, sc2, sc4, + 0, tgt, sdp->isp_devparam[tgt].nvrm_flags, + sdp->isp_devparam[tgt].nvrm_offset, + sdp->isp_devparam[tgt].nvrm_period); + sdp->isp_devparam[tgt].goal_offset = + sdp->isp_devparam[tgt].nvrm_offset; + sdp->isp_devparam[tgt].goal_period = + sdp->isp_devparam[tgt].nvrm_period; + sdp->isp_devparam[tgt].goal_flags = + sdp->isp_devparam[tgt].nvrm_flags; + } +} + +static void +isp_parse_nvram_1080(struct ispsoftc *isp, int bus, u_int8_t *nvram_data) +{ + sdparam *sdp = (sdparam *) isp->isp_param; + int tgt; + + sdp += bus; + + sdp->isp_fifo_threshold = + ISP1080_NVRAM_FIFO_THRESHOLD(nvram_data); + + if ((isp->isp_confopts & ISP_CFG_OWNLOOPID) == 0) + sdp->isp_initiator_id = + ISP1080_NVRAM_INITIATOR_ID(nvram_data, bus); + + sdp->isp_bus_reset_delay = + ISP1080_NVRAM_BUS_RESET_DELAY(nvram_data, bus); + + sdp->isp_retry_count = + ISP1080_NVRAM_BUS_RETRY_COUNT(nvram_data, bus); + + sdp->isp_retry_delay = + ISP1080_NVRAM_BUS_RETRY_DELAY(nvram_data, bus); + + sdp->isp_async_data_setup = + ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(nvram_data, bus); + + sdp->isp_req_ack_active_neg = + ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(nvram_data, bus); + + sdp->isp_data_line_active_neg = + ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(nvram_data, bus); + + sdp->isp_data_dma_burst_enabl = + ISP1080_NVRAM_BURST_ENABLE(nvram_data); + + sdp->isp_cmd_dma_burst_enable = + ISP1080_NVRAM_BURST_ENABLE(nvram_data); + + sdp->isp_selection_timeout = + ISP1080_NVRAM_SELECTION_TIMEOUT(nvram_data, bus); + + sdp->isp_max_queue_depth = + ISP1080_NVRAM_MAX_QUEUE_DEPTH(nvram_data, bus); + + isp_prt(isp, ISP_LOGDEBUG0, sc0, sc4, + bus, sdp->isp_fifo_threshold, sdp->isp_initiator_id, + sdp->isp_bus_reset_delay, sdp->isp_retry_count, + sdp->isp_retry_delay, sdp->isp_async_data_setup); + isp_prt(isp, ISP_LOGDEBUG0, sc1, sc4, + sdp->isp_req_ack_active_neg, sdp->isp_data_line_active_neg, + sdp->isp_data_dma_burst_enabl, sdp->isp_cmd_dma_burst_enable, + sdp->isp_selection_timeout, sdp->isp_max_queue_depth); + + + for (tgt = 0; tgt < MAX_TARGETS; tgt++) { + sdp->isp_devparam[tgt].dev_enable = + ISP1080_NVRAM_TGT_DEVICE_ENABLE(nvram_data, tgt, bus); + sdp->isp_devparam[tgt].exc_throttle = + ISP1080_NVRAM_TGT_EXEC_THROTTLE(nvram_data, tgt, bus); + sdp->isp_devparam[tgt].nvrm_offset = + ISP1080_NVRAM_TGT_SYNC_OFFSET(nvram_data, tgt, bus); + sdp->isp_devparam[tgt].nvrm_period = + ISP1080_NVRAM_TGT_SYNC_PERIOD(nvram_data, tgt, bus); + sdp->isp_devparam[tgt].nvrm_flags = 0; + if (ISP1080_NVRAM_TGT_RENEG(nvram_data, tgt, bus)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_RENEG; + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_ARQ; + if (ISP1080_NVRAM_TGT_TQING(nvram_data, tgt, bus)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_TQING; + if (ISP1080_NVRAM_TGT_SYNC(nvram_data, tgt, bus)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_SYNC; + if (ISP1080_NVRAM_TGT_WIDE(nvram_data, tgt, bus)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_WIDE; + if (ISP1080_NVRAM_TGT_PARITY(nvram_data, tgt, bus)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_PARITY; + if (ISP1080_NVRAM_TGT_DISC(nvram_data, tgt, bus)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_DISC; + sdp->isp_devparam[tgt].actv_flags = 0; + isp_prt(isp, ISP_LOGDEBUG0, sc2, sc4, + bus, tgt, sdp->isp_devparam[tgt].nvrm_flags, + sdp->isp_devparam[tgt].nvrm_offset, + sdp->isp_devparam[tgt].nvrm_period); + sdp->isp_devparam[tgt].goal_offset = + sdp->isp_devparam[tgt].nvrm_offset; + sdp->isp_devparam[tgt].goal_period = + sdp->isp_devparam[tgt].nvrm_period; + sdp->isp_devparam[tgt].goal_flags = + sdp->isp_devparam[tgt].nvrm_flags; + } +} + +static void +isp_parse_nvram_12160(struct ispsoftc *isp, int bus, u_int8_t *nvram_data) +{ + sdparam *sdp = (sdparam *) isp->isp_param; + int tgt; + + sdp += bus; + + sdp->isp_fifo_threshold = + ISP12160_NVRAM_FIFO_THRESHOLD(nvram_data); + + if ((isp->isp_confopts & ISP_CFG_OWNLOOPID) == 0) + sdp->isp_initiator_id = + ISP12160_NVRAM_INITIATOR_ID(nvram_data, bus); + + sdp->isp_bus_reset_delay = + ISP12160_NVRAM_BUS_RESET_DELAY(nvram_data, bus); + + sdp->isp_retry_count = + ISP12160_NVRAM_BUS_RETRY_COUNT(nvram_data, bus); + + sdp->isp_retry_delay = + ISP12160_NVRAM_BUS_RETRY_DELAY(nvram_data, bus); + + sdp->isp_async_data_setup = + ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME(nvram_data, bus); + + sdp->isp_req_ack_active_neg = + ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION(nvram_data, bus); + + sdp->isp_data_line_active_neg = + ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION(nvram_data, bus); + + sdp->isp_data_dma_burst_enabl = + ISP12160_NVRAM_BURST_ENABLE(nvram_data); + + sdp->isp_cmd_dma_burst_enable = + ISP12160_NVRAM_BURST_ENABLE(nvram_data); + + sdp->isp_selection_timeout = + ISP12160_NVRAM_SELECTION_TIMEOUT(nvram_data, bus); + + sdp->isp_max_queue_depth = + ISP12160_NVRAM_MAX_QUEUE_DEPTH(nvram_data, bus); + + isp_prt(isp, ISP_LOGDEBUG0, sc0, sc4, + bus, sdp->isp_fifo_threshold, sdp->isp_initiator_id, + sdp->isp_bus_reset_delay, sdp->isp_retry_count, + sdp->isp_retry_delay, sdp->isp_async_data_setup); + isp_prt(isp, ISP_LOGDEBUG0, sc1, sc4, + sdp->isp_req_ack_active_neg, sdp->isp_data_line_active_neg, + sdp->isp_data_dma_burst_enabl, sdp->isp_cmd_dma_burst_enable, + sdp->isp_selection_timeout, sdp->isp_max_queue_depth); + + for (tgt = 0; tgt < MAX_TARGETS; tgt++) { + sdp->isp_devparam[tgt].dev_enable = + ISP12160_NVRAM_TGT_DEVICE_ENABLE(nvram_data, tgt, bus); + sdp->isp_devparam[tgt].exc_throttle = + ISP12160_NVRAM_TGT_EXEC_THROTTLE(nvram_data, tgt, bus); + sdp->isp_devparam[tgt].nvrm_offset = + ISP12160_NVRAM_TGT_SYNC_OFFSET(nvram_data, tgt, bus); + sdp->isp_devparam[tgt].nvrm_period = + ISP12160_NVRAM_TGT_SYNC_PERIOD(nvram_data, tgt, bus); + sdp->isp_devparam[tgt].nvrm_flags = 0; + if (ISP12160_NVRAM_TGT_RENEG(nvram_data, tgt, bus)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_RENEG; + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_ARQ; + if (ISP12160_NVRAM_TGT_TQING(nvram_data, tgt, bus)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_TQING; + if (ISP12160_NVRAM_TGT_SYNC(nvram_data, tgt, bus)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_SYNC; + if (ISP12160_NVRAM_TGT_WIDE(nvram_data, tgt, bus)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_WIDE; + if (ISP12160_NVRAM_TGT_PARITY(nvram_data, tgt, bus)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_PARITY; + if (ISP12160_NVRAM_TGT_DISC(nvram_data, tgt, bus)) + sdp->isp_devparam[tgt].nvrm_flags |= DPARM_DISC; + sdp->isp_devparam[tgt].actv_flags = 0; + isp_prt(isp, ISP_LOGDEBUG0, sc2, sc4, + bus, tgt, sdp->isp_devparam[tgt].nvrm_flags, + sdp->isp_devparam[tgt].nvrm_offset, + sdp->isp_devparam[tgt].nvrm_period); + sdp->isp_devparam[tgt].goal_offset = + sdp->isp_devparam[tgt].nvrm_offset; + sdp->isp_devparam[tgt].goal_period = + sdp->isp_devparam[tgt].nvrm_period; + sdp->isp_devparam[tgt].goal_flags = + sdp->isp_devparam[tgt].nvrm_flags; + } +} + +static void +isp_parse_nvram_2100(struct ispsoftc *isp, u_int8_t *nvram_data) +{ + fcparam *fcp = (fcparam *) isp->isp_param; + u_int64_t wwn; + + /* + * There is NVRAM storage for both Port and Node entities- + * but the Node entity appears to be unused on all the cards + * I can find. However, we should account for this being set + * at some point in the future. + * + * Qlogic WWNs have an NAA of 2, but usually nothing shows up in + * bits 48..60. In the case of the 2202, it appears that they do + * use bit 48 to distinguish between the two instances on the card. + * The 2204, which I've never seen, *probably* extends this method. + */ + wwn = ISP2100_NVRAM_PORT_NAME(nvram_data); + if (wwn) { + isp_prt(isp, ISP_LOGCONFIG, "NVRAM Port WWN 0x%08x%08x", + (u_int32_t) (wwn >> 32), (u_int32_t) (wwn & 0xffffffff)); + if ((wwn >> 60) == 0) { + wwn |= (((u_int64_t) 2)<< 60); + } + } + fcp->isp_portwwn = wwn; + if (IS_2200(isp) || IS_23XX(isp)) { + wwn = ISP2200_NVRAM_NODE_NAME(nvram_data); + if (wwn) { + isp_prt(isp, ISP_LOGCONFIG, "NVRAM Node WWN 0x%08x%08x", + (u_int32_t) (wwn >> 32), + (u_int32_t) (wwn & 0xffffffff)); + if ((wwn >> 60) == 0) { + wwn |= (((u_int64_t) 2)<< 60); + } + } + } else { + wwn &= ~((u_int64_t) 0xfff << 48); + } + fcp->isp_nodewwn = wwn; + + /* + * Make sure we have both Node and Port as non-zero values. + */ + if (fcp->isp_nodewwn != 0 && fcp->isp_portwwn == 0) { + fcp->isp_portwwn = fcp->isp_nodewwn; + } else if (fcp->isp_nodewwn == 0 && fcp->isp_portwwn != 0) { + fcp->isp_nodewwn = fcp->isp_portwwn; + } + + /* + * Make the Node and Port values sane if they're NAA == 2. + * This means to clear bits 48..56 for the Node WWN and + * make sure that there's some non-zero value in 48..56 + * for the Port WWN. + */ + if (fcp->isp_nodewwn && fcp->isp_portwwn) { + if ((fcp->isp_nodewwn & (((u_int64_t) 0xfff) << 48)) != 0 && + (fcp->isp_nodewwn >> 60) == 2) { + fcp->isp_nodewwn &= ~((u_int64_t) 0xfff << 48); + } + if ((fcp->isp_portwwn & (((u_int64_t) 0xfff) << 48)) == 0 && + (fcp->isp_portwwn >> 60) == 2) { + fcp->isp_portwwn |= ((u_int64_t) 1 << 56); + } + } + + isp_prt(isp, ISP_LOGDEBUG0, + "NVRAM: maxfrmlen %d execthrottle %d fwoptions 0x%x loopid %x", + ISP2100_NVRAM_MAXFRAMELENGTH(nvram_data), + ISP2100_NVRAM_EXECUTION_THROTTLE(nvram_data), + ISP2100_NVRAM_OPTIONS(nvram_data), + ISP2100_NVRAM_HARDLOOPID(nvram_data)); + + fcp->isp_maxalloc = + ISP2100_NVRAM_MAXIOCBALLOCATION(nvram_data); + if ((isp->isp_confopts & ISP_CFG_OWNFSZ) == 0) + fcp->isp_maxfrmlen = + ISP2100_NVRAM_MAXFRAMELENGTH(nvram_data); + fcp->isp_retry_delay = + ISP2100_NVRAM_RETRY_DELAY(nvram_data); + fcp->isp_retry_count = + ISP2100_NVRAM_RETRY_COUNT(nvram_data); + if ((isp->isp_confopts & ISP_CFG_OWNLOOPID) == 0) + fcp->isp_loopid = + ISP2100_NVRAM_HARDLOOPID(nvram_data); + if ((isp->isp_confopts & ISP_CFG_OWNEXCTHROTTLE) == 0) + fcp->isp_execthrottle = + ISP2100_NVRAM_EXECUTION_THROTTLE(nvram_data); + fcp->isp_fwoptions = ISP2100_NVRAM_OPTIONS(nvram_data); +} + +#ifdef ISP_FW_CRASH_DUMP +static void isp2200_fw_dump(struct ispsoftc *); +static void isp2300_fw_dump(struct ispsoftc *); + +static void +isp2200_fw_dump(struct ispsoftc *isp) +{ + int i, j; + mbreg_t mbs; + u_int16_t *ptr; + + ptr = FCPARAM(isp)->isp_dump_data; + if (ptr == NULL) { + isp_prt(isp, ISP_LOGERR, + "No place to dump RISC registers and SRAM"); + return; + } + if (*ptr++) { + isp_prt(isp, ISP_LOGERR, + "dump area for RISC registers and SRAM already used"); + return; + } + ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); + for (i = 0; i < 100; i++) { + USEC_DELAY(100); + if (ISP_READ(isp, HCCR) & HCCR_PAUSE) { + break; + } + } + if (ISP_READ(isp, HCCR) & HCCR_PAUSE) { + /* + * PBIU Registers + */ + for (i = 0; i < 8; i++) { + *ptr++ = ISP_READ(isp, BIU_BLOCK + (i << 1)); + } + + /* + * Mailbox Registers + */ + for (i = 0; i < 8; i++) { + *ptr++ = ISP_READ(isp, MBOX_BLOCK + (i << 1)); + } + + /* + * DMA Registers + */ + for (i = 0; i < 48; i++) { + *ptr++ = ISP_READ(isp, DMA_BLOCK + 0x20 + (i << 1)); + } + + /* + * RISC H/W Registers + */ + ISP_WRITE(isp, BIU2100_CSR, 0); + for (i = 0; i < 16; i++) { + *ptr++ = ISP_READ(isp, BIU_BLOCK + 0xA0 + (i << 1)); + } + + /* + * RISC GP Registers + */ + for (j = 0; j < 8; j++) { + ISP_WRITE(isp, BIU_BLOCK + 0xA4, 0x2000 + (j << 8)); + for (i = 0; i < 16; i++) { + *ptr++ = + ISP_READ(isp, BIU_BLOCK + 0x80 + (i << 1)); + } + } + + /* + * Frame Buffer Hardware Registers + */ + ISP_WRITE(isp, BIU2100_CSR, 0x10); + for (i = 0; i < 16; i++) { + *ptr++ = ISP_READ(isp, BIU_BLOCK + 0x80 + (i << 1)); + } + + /* + * Fibre Protocol Module 0 Hardware Registers + */ + ISP_WRITE(isp, BIU2100_CSR, 0x20); + for (i = 0; i < 64; i++) { + *ptr++ = ISP_READ(isp, BIU_BLOCK + 0x80 + (i << 1)); + } + + /* + * Fibre Protocol Module 1 Hardware Registers + */ + ISP_WRITE(isp, BIU2100_CSR, 0x30); + for (i = 0; i < 64; i++) { + *ptr++ = ISP_READ(isp, BIU_BLOCK + 0x80 + (i << 1)); + } + } else { + isp_prt(isp, ISP_LOGERR, "RISC Would Not Pause"); + return; + } + isp_prt(isp, ISP_LOGALL, + "isp_fw_dump: RISC registers dumped successfully"); + ISP_WRITE(isp, BIU2100_CSR, BIU2100_SOFT_RESET); + for (i = 0; i < 100; i++) { + USEC_DELAY(100); + if (ISP_READ(isp, OUTMAILBOX0) == 0) { + break; + } + } + if (ISP_READ(isp, OUTMAILBOX0) != 0) { + isp_prt(isp, ISP_LOGERR, "Board Would Not Reset"); + return; + } + ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); + for (i = 0; i < 100; i++) { + USEC_DELAY(100); + if (ISP_READ(isp, HCCR) & HCCR_PAUSE) { + break; + } + } + if ((ISP_READ(isp, HCCR) & HCCR_PAUSE) == 0) { + isp_prt(isp, ISP_LOGERR, "RISC Would Not Pause After Reset"); + return; + } + ISP_WRITE(isp, RISC_EMB, 0xf2); + ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); + for (i = 0; i < 100; i++) { + USEC_DELAY(100); + if ((ISP_READ(isp, HCCR) & HCCR_PAUSE) == 0) { + break; + } + } + ENABLE_INTS(isp); + mbs.param[0] = MBOX_READ_RAM_WORD; + mbs.param[1] = 0x1000; + isp->isp_mbxworkp = (void *) ptr; + isp->isp_mbxwrk0 = 0xefff; /* continuation count */ + isp->isp_mbxwrk1 = 0x1001; /* next SRAM address */ + isp_control(isp, ISPCTL_RUN_MBOXCMD, &mbs); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + isp_prt(isp, ISP_LOGWARN, + "RAM DUMP FAILED @ WORD %x", isp->isp_mbxwrk1); + return; + } + ptr = isp->isp_mbxworkp; /* finish fetch of final word */ + *ptr++ = isp->isp_mboxtmp[2]; + isp_prt(isp, ISP_LOGALL, "isp_fw_dump: SRAM dumped succesfully"); + FCPARAM(isp)->isp_dump_data[0] = isp->isp_type; /* now used */ + (void) isp_async(isp, ISPASYNC_FW_DUMPED, 0); +} + +static void +isp2300_fw_dump(struct ispsoftc *isp) +{ + int i, j; + mbreg_t mbs; + u_int16_t *ptr; + + ptr = FCPARAM(isp)->isp_dump_data; + if (ptr == NULL) { + isp_prt(isp, ISP_LOGERR, + "No place to dump RISC registers and SRAM"); + return; + } + if (*ptr++) { + isp_prt(isp, ISP_LOGERR, + "dump area for RISC registers and SRAM already used"); + return; + } + ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); + for (i = 0; i < 100; i++) { + USEC_DELAY(100); + if (ISP_READ(isp, HCCR) & HCCR_PAUSE) { + break; + } + } + if (ISP_READ(isp, HCCR) & HCCR_PAUSE) { + /* + * PBIU registers + */ + for (i = 0; i < 8; i++) { + *ptr++ = ISP_READ(isp, BIU_BLOCK + (i << 1)); + } + + /* + * ReqQ-RspQ-Risc2Host Status registers + */ + for (i = 0; i < 8; i++) { + *ptr++ = ISP_READ(isp, BIU_BLOCK + 0x10 + (i << 1)); + } + + /* + * Mailbox Registers + */ + for (i = 0; i < 32; i++) { + *ptr++ = + ISP_READ(isp, PCI_MBOX_REGS2300_OFF + (i << 1)); + } + + /* + * Auto Request Response DMA registers + */ + ISP_WRITE(isp, BIU2100_CSR, 0x40); + for (i = 0; i < 32; i++) { + *ptr++ = ISP_READ(isp, BIU_BLOCK + 0x80 + (i << 1)); + } + + /* + * DMA registers + */ + ISP_WRITE(isp, BIU2100_CSR, 0x50); + for (i = 0; i < 48; i++) { + *ptr++ = ISP_READ(isp, BIU_BLOCK + 0x80 + (i << 1)); + } + + /* + * RISC hardware registers + */ + ISP_WRITE(isp, BIU2100_CSR, 0); + for (i = 0; i < 16; i++) { + *ptr++ = ISP_READ(isp, BIU_BLOCK + 0xA0 + (i << 1)); + } + + /* + * RISC GP? registers + */ + for (j = 0; j < 8; j++) { + ISP_WRITE(isp, BIU_BLOCK + 0xA4, 0x2000 + (j << 9)); + for (i = 0; i < 16; i++) { + *ptr++ = + ISP_READ(isp, BIU_BLOCK + 0x80 + (i << 1)); + } + } + + /* + * frame buffer hardware registers + */ + ISP_WRITE(isp, BIU2100_CSR, 0x10); + for (i = 0; i < 64; i++) { + *ptr++ = ISP_READ(isp, BIU_BLOCK + 0x80 + (i << 1)); + } + + /* + * FPM B0 hardware registers + */ + ISP_WRITE(isp, BIU2100_CSR, 0x20); + for (i = 0; i < 64; i++) { + *ptr++ = ISP_READ(isp, BIU_BLOCK + 0x80 + (i << 1)); + } + + /* + * FPM B1 hardware registers + */ + ISP_WRITE(isp, BIU2100_CSR, 0x30); + for (i = 0; i < 64; i++) { + *ptr++ = ISP_READ(isp, BIU_BLOCK + 0x80 + (i << 1)); + } + } else { + isp_prt(isp, ISP_LOGERR, "RISC Would Not Pause"); + return; + } + isp_prt(isp, ISP_LOGALL, + "isp_fw_dump: RISC registers dumped successfully"); + ISP_WRITE(isp, BIU2100_CSR, BIU2100_SOFT_RESET); + for (i = 0; i < 100; i++) { + USEC_DELAY(100); + if (ISP_READ(isp, OUTMAILBOX0) == 0) { + break; + } + } + if (ISP_READ(isp, OUTMAILBOX0) != 0) { + isp_prt(isp, ISP_LOGERR, "Board Would Not Reset"); + return; + } + ENABLE_INTS(isp); + mbs.param[0] = MBOX_READ_RAM_WORD; + mbs.param[1] = 0x800; + isp->isp_mbxworkp = (void *) ptr; + isp->isp_mbxwrk0 = 0xf7ff; /* continuation count */ + isp->isp_mbxwrk1 = 0x801; /* next SRAM address */ + isp_control(isp, ISPCTL_RUN_MBOXCMD, &mbs); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + isp_prt(isp, ISP_LOGWARN, + "RAM DUMP FAILED @ WORD %x", isp->isp_mbxwrk1); + return; + } + ptr = isp->isp_mbxworkp; /* finish fetch of final word */ + *ptr++ = isp->isp_mboxtmp[2]; + + /* + * We don't have access to mailbox registers 8.. onward + * in our 'common' device model- so we have to set it + * here and hope it stays the same! + */ + ISP_WRITE(isp, PCI_MBOX_REGS2300_OFF + (8 << 1), 0x1); + + mbs.param[0] = MBOX_READ_RAM_WORD_EXTENDED; + mbs.param[1] = 0; + isp->isp_mbxworkp = (void *) ptr; + isp->isp_mbxwrk0 = 0xffff; /* continuation count */ + isp->isp_mbxwrk1 = 0x1; /* next SRAM address */ + isp_control(isp, ISPCTL_RUN_MBOXCMD, &mbs); + if (mbs.param[0] != MBOX_COMMAND_COMPLETE) { + isp_prt(isp, ISP_LOGWARN, + "RAM DUMP FAILED @ WORD %x", 0x10000 + isp->isp_mbxwrk1); + return; + } + ptr = isp->isp_mbxworkp; /* finish final word */ + *ptr++ = mbs.param[2]; + isp_prt(isp, ISP_LOGALL, "isp_fw_dump: SRAM dumped succesfully"); + FCPARAM(isp)->isp_dump_data[0] = isp->isp_type; /* now used */ + (void) isp_async(isp, ISPASYNC_FW_DUMPED, 0); +} + +void +isp_fw_dump(struct ispsoftc *isp) +{ + if (IS_2200(isp)) + isp2200_fw_dump(isp); + else if (IS_23XX(isp)) + isp2300_fw_dump(isp); +} +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/common/isp_inline.h 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,1494 @@ +/* + * Qlogic Host Adapter Inline Functions + * + * Copyright (c) 1999, 2000, 2001 by Matthew Jacob + * Feral Software + * All rights reserved. + * mjacob@feral.com + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#ifndef _ISP_INLINE_H +#define _ISP_INLINE_H + +/* + * Handle Functions. + * For each outstanding command there will be a non-zero handle. + * There will be at most isp_maxcmds handles, and isp_lasthdls + * will be a seed for the last handled allocated. + */ + +static INLINE int isp_save_xs(struct ispsoftc *, XS_T *, u_int16_t *); +static INLINE XS_T *isp_find_xs(struct ispsoftc *, u_int16_t); +static INLINE u_int16_t isp_find_handle(struct ispsoftc *, XS_T *); +static INLINE int isp_handle_index(u_int16_t); +static INLINE void isp_destroy_handle(struct ispsoftc *, u_int16_t); +static INLINE void isp_remove_handle(struct ispsoftc *, XS_T *); + +static INLINE int +isp_save_xs(struct ispsoftc *isp, XS_T *xs, u_int16_t *handlep) +{ + int i, j; + + for (j = isp->isp_lasthdls, i = 0; i < (int) isp->isp_maxcmds; i++) { + if (isp->isp_xflist[j] == NULL) { + break; + } + if (++j == isp->isp_maxcmds) { + j = 0; + } + } + if (i == isp->isp_maxcmds) { + return (-1); + } + isp->isp_xflist[j] = xs; + *handlep = j+1; + if (++j == isp->isp_maxcmds) + j = 0; + isp->isp_lasthdls = (u_int16_t)j; + return (0); +} + +static INLINE XS_T * +isp_find_xs(struct ispsoftc *isp, u_int16_t handle) +{ + if (handle < 1 || handle > (u_int16_t) isp->isp_maxcmds) { + return (NULL); + } else { + return (isp->isp_xflist[handle - 1]); + } +} + +static INLINE u_int16_t +isp_find_handle(struct ispsoftc *isp, XS_T *xs) +{ + int i; + if (xs != NULL) { + for (i = 0; i < isp->isp_maxcmds; i++) { + if (isp->isp_xflist[i] == xs) { + return ((u_int16_t) i+1); + } + } + } + return (0); +} + +static INLINE int +isp_handle_index(u_int16_t handle) +{ + return (handle-1); +} + +static INLINE void +isp_destroy_handle(struct ispsoftc *isp, u_int16_t handle) +{ + if (handle > 0 && handle <= (u_int16_t) isp->isp_maxcmds) { + isp->isp_xflist[isp_handle_index(handle)] = NULL; + } +} + +static INLINE void +isp_remove_handle(struct ispsoftc *isp, XS_T *xs) +{ + isp_destroy_handle(isp, isp_find_handle(isp, xs)); +} + +static INLINE int +isp_getrqentry(struct ispsoftc *, u_int16_t *, u_int16_t *, void **); + +static INLINE int +isp_getrqentry(struct ispsoftc *isp, u_int16_t *iptrp, + u_int16_t *optrp, void **resultp) +{ + volatile u_int16_t iptr, optr; + + optr = isp->isp_reqodx = READ_REQUEST_QUEUE_OUT_POINTER(isp); + iptr = isp->isp_reqidx; + *resultp = ISP_QUEUE_ENTRY(isp->isp_rquest, iptr); + iptr = ISP_NXT_QENTRY(iptr, RQUEST_QUEUE_LEN(isp)); + if (iptr == optr) { + return (1); + } + if (optrp) + *optrp = optr; + if (iptrp) + *iptrp = iptr; + return (0); +} + +static INLINE void isp_print_qentry (struct ispsoftc *, char *, int, void *); + + +#define TBA (4 * (((QENTRY_LEN >> 2) * 3) + 1) + 1) +static INLINE void +isp_print_qentry(struct ispsoftc *isp, char *msg, int idx, void *arg) +{ + char buf[TBA]; + int amt, i, j; + u_int8_t *ptr = arg; + + isp_prt(isp, ISP_LOGALL, "%s index %d=>", msg, idx); + for (buf[0] = 0, amt = i = 0; i < 4; i++) { + buf[0] = 0; + SNPRINTF(buf, TBA, " "); + for (j = 0; j < (QENTRY_LEN >> 2); j++) { + SNPRINTF(buf, TBA, "%s %02x", buf, ptr[amt++] & 0xff); + } + isp_prt(isp, ISP_LOGALL, buf); + } +} + +static INLINE void isp_print_bytes(struct ispsoftc *, char *, int, void *); + +static INLINE void +isp_print_bytes(struct ispsoftc *isp, char *msg, int amt, void *arg) +{ + char buf[128]; + u_int8_t *ptr = arg; + int off; + + if (msg) + isp_prt(isp, ISP_LOGALL, "%s:", msg); + off = 0; + buf[0] = 0; + while (off < amt) { + int j, to; + to = off; + for (j = 0; j < 16; j++) { + SNPRINTF(buf, 128, "%s %02x", buf, ptr[off++] & 0xff); + if (off == amt) + break; + } + isp_prt(isp, ISP_LOGALL, "0x%08x:%s", to, buf); + buf[0] = 0; + } +} + +/* + * Do the common path to try and ensure that link is up, we've scanned + * the fabric (if we're on a fabric), and that we've synchronized this + * all with our own database and done the appropriate logins. + * + * We repeatedly check for firmware state and loop state after each + * action because things may have changed while we were doing this. + * Any failure or change of state causes us to return a nonzero value. + * + * We honor HBA roles in that if we're not in Initiator mode, we don't + * attempt to sync up the database (that's for somebody else to do, + * if ever). + * + * We assume we enter here with any locks held. + */ + +static INLINE int isp_fc_runstate(struct ispsoftc *, int); + +static INLINE int +isp_fc_runstate(struct ispsoftc *isp, int tval) +{ + fcparam *fcp; + int *tptr; + + if (IS_SCSI(isp)) + return (0); + + tptr = tval? &tval : NULL; + if (isp_control(isp, ISPCTL_FCLINK_TEST, tptr) != 0) { + return (-1); + } + fcp = FCPARAM(isp); + if (fcp->isp_fwstate != FW_READY || fcp->isp_loopstate < LOOP_PDB_RCVD) + return (-1); + if (isp_control(isp, ISPCTL_SCAN_FABRIC, NULL) != 0) { + return (-1); + } + if (isp_control(isp, ISPCTL_SCAN_LOOP, NULL) != 0) { + return (-1); + } + if ((isp->isp_role & ISP_ROLE_INITIATOR) == 0) { + return (0); + } + if (isp_control(isp, ISPCTL_PDB_SYNC, NULL) != 0) { + return (-1); + } + if (fcp->isp_fwstate != FW_READY || fcp->isp_loopstate != LOOP_READY) { + return (-1); + } + return (0); +} + +/* + * Functions to move stuff to a form that the QLogic RISC engine understands + * and functions to move stuff back to a form the processor understands. + * + * Each platform is required to provide the 8, 16 and 32 bit + * swizzle and unswizzle macros (ISP_IOX{PUT|GET}_{8,16,32}) + * + * The assumption is that swizzling and unswizzling is mostly done 'in place' + * (with a few exceptions for efficiency). + */ + +static INLINE void isp_copy_out_hdr(struct ispsoftc *, isphdr_t *, isphdr_t *); +static INLINE void isp_copy_in_hdr(struct ispsoftc *, isphdr_t *, isphdr_t *); +static INLINE int isp_get_response_type(struct ispsoftc *, isphdr_t *); + +static INLINE void +isp_put_request(struct ispsoftc *, ispreq_t *, ispreq_t *); +static INLINE void +isp_put_request_t2(struct ispsoftc *, ispreqt2_t *, ispreqt2_t *); +static INLINE void +isp_put_request_t3(struct ispsoftc *, ispreqt3_t *, ispreqt3_t *); +static INLINE void +isp_put_extended_request(struct ispsoftc *, ispextreq_t *, ispextreq_t *); +static INLINE void +isp_put_cont_req(struct ispsoftc *, ispcontreq_t *, ispcontreq_t *); +static INLINE void +isp_put_cont64_req(struct ispsoftc *, ispcontreq64_t *, ispcontreq64_t *); +static INLINE void +isp_get_response(struct ispsoftc *, ispstatusreq_t *, ispstatusreq_t *); +static INLINE void +isp_get_response_x(struct ispsoftc *, ispstatus_cont_t *, ispstatus_cont_t *); +static INLINE void +isp_get_rio2(struct ispsoftc *, isp_rio2_t *, isp_rio2_t *); +static INLINE void +isp_put_icb(struct ispsoftc *, isp_icb_t *, isp_icb_t *); +static INLINE void +isp_get_pdb(struct ispsoftc *, isp_pdb_t *, isp_pdb_t *); +static INLINE void +isp_get_ct_hdr(struct ispsoftc *isp, ct_hdr_t *, ct_hdr_t *); +static INLINE void +isp_put_sns_request(struct ispsoftc *, sns_screq_t *, sns_screq_t *); +static INLINE void +isp_put_gid_ft_request(struct ispsoftc *, sns_gid_ft_req_t *, + sns_gid_ft_req_t *); +static INLINE void +isp_put_gxn_id_request(struct ispsoftc *, sns_gxn_id_req_t *, + sns_gxn_id_req_t *); +static INLINE void +isp_get_sns_response(struct ispsoftc *, sns_scrsp_t *, sns_scrsp_t *, int); +static INLINE void +isp_get_gid_ft_response(struct ispsoftc *, sns_gid_ft_rsp_t *, + sns_gid_ft_rsp_t *, int); +static INLINE void +isp_get_gxn_id_response(struct ispsoftc *, sns_gxn_id_rsp_t *, + sns_gxn_id_rsp_t *); +static INLINE void +isp_get_gff_id_response(struct ispsoftc *, sns_gff_id_rsp_t *, + sns_gff_id_rsp_t *); +static INLINE void +isp_get_ga_nxt_response(struct ispsoftc *, sns_ga_nxt_rsp_t *, + sns_ga_nxt_rsp_t *); +#ifdef ISP_TARGET_MODE +#ifndef _ISP_TARGET_H +#include "isp_target.h" +#endif +static INLINE void +isp_put_atio(struct ispsoftc *, at_entry_t *, at_entry_t *); +static INLINE void +isp_get_atio(struct ispsoftc *, at_entry_t *, at_entry_t *); +static INLINE void +isp_put_atio2(struct ispsoftc *, at2_entry_t *, at2_entry_t *); +static INLINE void +isp_get_atio2(struct ispsoftc *, at2_entry_t *, at2_entry_t *); +static INLINE void +isp_put_ctio(struct ispsoftc *, ct_entry_t *, ct_entry_t *); +static INLINE void +isp_get_ctio(struct ispsoftc *, ct_entry_t *, ct_entry_t *); +static INLINE void +isp_put_ctio2(struct ispsoftc *, ct2_entry_t *, ct2_entry_t *); +static INLINE void +isp_get_ctio2(struct ispsoftc *, ct2_entry_t *, ct2_entry_t *); +static INLINE void +isp_put_enable_lun(struct ispsoftc *, lun_entry_t *, lun_entry_t *); +static INLINE void +isp_get_enable_lun(struct ispsoftc *, lun_entry_t *, lun_entry_t *); +static INLINE void +isp_put_notify(struct ispsoftc *, in_entry_t *, in_entry_t *); +static INLINE void +isp_get_notify(struct ispsoftc *, in_entry_t *, in_entry_t *); +static INLINE void +isp_put_notify_fc(struct ispsoftc *, in_fcentry_t *, in_fcentry_t *); +static INLINE void +isp_get_notify_fc(struct ispsoftc *, in_fcentry_t *, in_fcentry_t *); +static INLINE void +isp_put_notify_ack(struct ispsoftc *, na_entry_t *, na_entry_t *); +static INLINE void +isp_get_notify_ack(struct ispsoftc *, na_entry_t *, na_entry_t *); +static INLINE void +isp_put_notify_ack_fc(struct ispsoftc *, na_fcentry_t *, na_fcentry_t *); +static INLINE void +isp_get_notify_ack_fc(struct ispsoftc *, na_fcentry_t *, na_fcentry_t *); +#endif + +#define ISP_IS_SBUS(isp) \ + (ISP_SBUS_SUPPORTED && (isp)->isp_bustype == ISP_BT_SBUS) + +/* + * Swizzle/Copy Functions + */ +static INLINE void +isp_copy_out_hdr(struct ispsoftc *isp, isphdr_t *hpsrc, isphdr_t *hpdst) +{ + if (ISP_IS_SBUS(isp)) { + ISP_IOXPUT_8(isp, hpsrc->rqs_entry_type, + &hpdst->rqs_entry_count); + ISP_IOXPUT_8(isp, hpsrc->rqs_entry_count, + &hpdst->rqs_entry_type); + ISP_IOXPUT_8(isp, hpsrc->rqs_seqno, + &hpdst->rqs_flags); + ISP_IOXPUT_8(isp, hpsrc->rqs_flags, + &hpdst->rqs_seqno); + } else { + ISP_IOXPUT_8(isp, hpsrc->rqs_entry_type, + &hpdst->rqs_entry_type); + ISP_IOXPUT_8(isp, hpsrc->rqs_entry_count, + &hpdst->rqs_entry_count); + ISP_IOXPUT_8(isp, hpsrc->rqs_seqno, + &hpdst->rqs_seqno); + ISP_IOXPUT_8(isp, hpsrc->rqs_flags, + &hpdst->rqs_flags); + } +} + +static INLINE void +isp_copy_in_hdr(struct ispsoftc *isp, isphdr_t *hpsrc, isphdr_t *hpdst) +{ + if (ISP_IS_SBUS(isp)) { + ISP_IOXGET_8(isp, &hpsrc->rqs_entry_type, + hpdst->rqs_entry_count); + ISP_IOXGET_8(isp, &hpsrc->rqs_entry_count, + hpdst->rqs_entry_type); + ISP_IOXGET_8(isp, &hpsrc->rqs_seqno, + hpdst->rqs_flags); + ISP_IOXGET_8(isp, &hpsrc->rqs_flags, + hpdst->rqs_seqno); + } else { + ISP_IOXGET_8(isp, &hpsrc->rqs_entry_type, + hpdst->rqs_entry_type); + ISP_IOXGET_8(isp, &hpsrc->rqs_entry_count, + hpdst->rqs_entry_count); + ISP_IOXGET_8(isp, &hpsrc->rqs_seqno, + hpdst->rqs_seqno); + ISP_IOXGET_8(isp, &hpsrc->rqs_flags, + hpdst->rqs_flags); + } +} + +static INLINE int +isp_get_response_type(struct ispsoftc *isp, isphdr_t *hp) +{ + u_int8_t type; + if (ISP_IS_SBUS(isp)) { + ISP_IOXGET_8(isp, &hp->rqs_entry_count, type); + } else { + ISP_IOXGET_8(isp, &hp->rqs_entry_type, type); + } + return ((int)type); +} + +static INLINE void +isp_put_request(struct ispsoftc *isp, ispreq_t *rqsrc, ispreq_t *rqdst) +{ + int i; + isp_copy_out_hdr(isp, &rqsrc->req_header, &rqdst->req_header); + ISP_IOXPUT_32(isp, rqsrc->req_handle, &rqdst->req_handle); + if (ISP_IS_SBUS(isp)) { + ISP_IOXPUT_8(isp, rqsrc->req_lun_trn, &rqdst->req_target); + ISP_IOXPUT_8(isp, rqsrc->req_target, &rqdst->req_lun_trn); + } else { + ISP_IOXPUT_8(isp, rqsrc->req_lun_trn, &rqdst->req_lun_trn); + ISP_IOXPUT_8(isp, rqsrc->req_target, &rqdst->req_target); + } + ISP_IOXPUT_16(isp, rqsrc->req_cdblen, &rqdst->req_cdblen); + ISP_IOXPUT_16(isp, rqsrc->req_flags, &rqdst->req_flags); + ISP_IOXPUT_16(isp, rqsrc->req_time, &rqdst->req_time); + ISP_IOXPUT_16(isp, rqsrc->req_seg_count, &rqdst->req_seg_count); + for (i = 0; i < 12; i++) { + ISP_IOXPUT_8(isp, rqsrc->req_cdb[i], &rqdst->req_cdb[i]); + } + for (i = 0; i < ISP_RQDSEG; i++) { + ISP_IOXPUT_32(isp, rqsrc->req_dataseg[i].ds_base, + &rqdst->req_dataseg[i].ds_base); + ISP_IOXPUT_32(isp, rqsrc->req_dataseg[i].ds_count, + &rqdst->req_dataseg[i].ds_count); + } +} + +static INLINE void +isp_put_request_t2(struct ispsoftc *isp, ispreqt2_t *tqsrc, ispreqt2_t *tqdst) +{ + int i; + isp_copy_out_hdr(isp, &tqsrc->req_header, &tqdst->req_header); + ISP_IOXPUT_32(isp, tqsrc->req_handle, &tqdst->req_handle); + ISP_IOXPUT_8(isp, tqsrc->req_lun_trn, &tqdst->req_lun_trn); + ISP_IOXPUT_8(isp, tqsrc->req_target, &tqdst->req_target); + ISP_IOXPUT_16(isp, tqsrc->req_scclun, &tqdst->req_scclun); + ISP_IOXPUT_16(isp, tqsrc->req_flags, &tqdst->req_flags); + ISP_IOXPUT_16(isp, tqsrc->_res2, &tqdst->_res2); + ISP_IOXPUT_16(isp, tqsrc->req_time, &tqdst->req_time); + ISP_IOXPUT_16(isp, tqsrc->req_seg_count, &tqdst->req_seg_count); + for (i = 0; i < 16; i++) { + ISP_IOXPUT_8(isp, tqsrc->req_cdb[i], &tqdst->req_cdb[i]); + } + ISP_IOXPUT_32(isp, tqsrc->req_totalcnt, &tqdst->req_totalcnt); + for (i = 0; i < ISP_RQDSEG_T2; i++) { + ISP_IOXPUT_32(isp, tqsrc->req_dataseg[i].ds_base, + &tqdst->req_dataseg[i].ds_base); + ISP_IOXPUT_32(isp, tqsrc->req_dataseg[i].ds_count, + &tqdst->req_dataseg[i].ds_count); + } +} + +static INLINE void +isp_put_request_t3(struct ispsoftc *isp, ispreqt3_t *tqsrc, ispreqt3_t *tqdst) +{ + int i; + isp_copy_out_hdr(isp, &tqsrc->req_header, &tqdst->req_header); + ISP_IOXPUT_32(isp, tqsrc->req_handle, &tqdst->req_handle); + ISP_IOXPUT_8(isp, tqsrc->req_lun_trn, &tqdst->req_lun_trn); + ISP_IOXPUT_8(isp, tqsrc->req_target, &tqdst->req_target); + ISP_IOXPUT_16(isp, tqsrc->req_scclun, &tqdst->req_scclun); + ISP_IOXPUT_16(isp, tqsrc->req_flags, &tqdst->req_flags); + ISP_IOXPUT_16(isp, tqsrc->_res2, &tqdst->_res2); + ISP_IOXPUT_16(isp, tqsrc->req_time, &tqdst->req_time); + ISP_IOXPUT_16(isp, tqsrc->req_seg_count, &tqdst->req_seg_count); + for (i = 0; i < 16; i++) { + ISP_IOXPUT_8(isp, tqsrc->req_cdb[i], &tqdst->req_cdb[i]); + } + ISP_IOXPUT_32(isp, tqsrc->req_totalcnt, &tqdst->req_totalcnt); + for (i = 0; i < ISP_RQDSEG_T3; i++) { + ISP_IOXPUT_32(isp, tqsrc->req_dataseg[i].ds_base, + &tqdst->req_dataseg[i].ds_base); + ISP_IOXPUT_32(isp, tqsrc->req_dataseg[i].ds_basehi, + &tqdst->req_dataseg[i].ds_basehi); + ISP_IOXPUT_32(isp, tqsrc->req_dataseg[i].ds_count, + &tqdst->req_dataseg[i].ds_count); + } +} + +static INLINE void +isp_put_extended_request(struct ispsoftc *isp, ispextreq_t *xqsrc, + ispextreq_t *xqdst) +{ + int i; + isp_copy_out_hdr(isp, &xqsrc->req_header, &xqdst->req_header); + ISP_IOXPUT_32(isp, xqsrc->req_handle, &xqdst->req_handle); + if (ISP_IS_SBUS(isp)) { + ISP_IOXPUT_8(isp, xqsrc->req_lun_trn, &xqdst->req_target); + ISP_IOXPUT_8(isp, xqsrc->req_target, &xqdst->req_lun_trn); + } else { + ISP_IOXPUT_8(isp, xqsrc->req_lun_trn, &xqdst->req_lun_trn); + ISP_IOXPUT_8(isp, xqsrc->req_target, &xqdst->req_target); + } + ISP_IOXPUT_16(isp, xqsrc->req_cdblen, &xqdst->req_cdblen); + ISP_IOXPUT_16(isp, xqsrc->req_flags, &xqdst->req_flags); + ISP_IOXPUT_16(isp, xqsrc->req_time, &xqdst->req_time); + ISP_IOXPUT_16(isp, xqsrc->req_seg_count, &xqdst->req_seg_count); + for (i = 0; i < 44; i++) { + ISP_IOXPUT_8(isp, xqsrc->req_cdb[i], &xqdst->req_cdb[i]); + } +} + +static INLINE void +isp_put_cont_req(struct ispsoftc *isp, ispcontreq_t *cqsrc, ispcontreq_t *cqdst) +{ + int i; + isp_copy_out_hdr(isp, &cqsrc->req_header, &cqdst->req_header); + for (i = 0; i < ISP_CDSEG; i++) { + ISP_IOXPUT_32(isp, cqsrc->req_dataseg[i].ds_base, + &cqdst->req_dataseg[i].ds_base); + ISP_IOXPUT_32(isp, cqsrc->req_dataseg[i].ds_count, + &cqdst->req_dataseg[i].ds_count); + } +} + +static INLINE void +isp_put_cont64_req(struct ispsoftc *isp, ispcontreq64_t *cqsrc, + ispcontreq64_t *cqdst) +{ + int i; + isp_copy_out_hdr(isp, &cqsrc->req_header, &cqdst->req_header); + for (i = 0; i < ISP_CDSEG64; i++) { + ISP_IOXPUT_32(isp, cqsrc->req_dataseg[i].ds_base, + &cqdst->req_dataseg[i].ds_base); + ISP_IOXPUT_32(isp, cqsrc->req_dataseg[i].ds_basehi, + &cqdst->req_dataseg[i].ds_basehi); + ISP_IOXPUT_32(isp, cqsrc->req_dataseg[i].ds_count, + &cqdst->req_dataseg[i].ds_count); + } +} + +static INLINE void +isp_get_response(struct ispsoftc *isp, ispstatusreq_t *spsrc, + ispstatusreq_t *spdst) +{ + int i; + isp_copy_in_hdr(isp, &spsrc->req_header, &spdst->req_header); + ISP_IOXGET_32(isp, &spsrc->req_handle, spdst->req_handle); + ISP_IOXGET_16(isp, &spsrc->req_scsi_status, spdst->req_scsi_status); + ISP_IOXGET_16(isp, &spsrc->req_completion_status, + spdst->req_completion_status); + ISP_IOXGET_16(isp, &spsrc->req_state_flags, spdst->req_state_flags); + ISP_IOXGET_16(isp, &spsrc->req_status_flags, spdst->req_status_flags); + ISP_IOXGET_16(isp, &spsrc->req_time, spdst->req_time); + ISP_IOXGET_16(isp, &spsrc->req_sense_len, spdst->req_sense_len); + ISP_IOXGET_32(isp, &spsrc->req_resid, spdst->req_resid); + for (i = 0; i < 8; i++) { + ISP_IOXGET_8(isp, &spsrc->req_response[i], + spdst->req_response[i]); + } + for (i = 0; i < 32; i++) { + ISP_IOXGET_8(isp, &spsrc->req_sense_data[i], + spdst->req_sense_data[i]); + } +} + +static INLINE void +isp_get_response_x(struct ispsoftc *isp, ispstatus_cont_t *cpsrc, + ispstatus_cont_t *cpdst) +{ + int i; + isp_copy_in_hdr(isp, &cpsrc->req_header, &cpdst->req_header); + for (i = 0; i < 60; i++) { + ISP_IOXGET_8(isp, &cpsrc->req_sense_data[i], + cpdst->req_sense_data[i]); + } +} + +static INLINE void +isp_get_rio2(struct ispsoftc *isp, isp_rio2_t *r2src, isp_rio2_t *r2dst) +{ + int i; + isp_copy_in_hdr(isp, &r2src->req_header, &r2dst->req_header); + if (r2dst->req_header.rqs_seqno > 30) + r2dst->req_header.rqs_seqno = 30; + for (i = 0; i < r2dst->req_header.rqs_seqno; i++) { + ISP_IOXGET_16(isp, &r2src->req_handles[i], + r2dst->req_handles[i]); + } + while (i < 30) { + r2dst->req_handles[i++] = 0; + } +} + +static INLINE void +isp_put_icb(struct ispsoftc *isp, isp_icb_t *Is, isp_icb_t *Id) +{ + int i; + ISP_SWAP8(Is->icb_version, Is->_reserved0); + ISP_IOXPUT_8(isp, Is->icb_version, &Id->icb_version); + ISP_IOXPUT_8(isp, Is->_reserved0, &Id->_reserved0); + ISP_IOXPUT_16(isp, Is->icb_fwoptions, &Id->icb_fwoptions); + ISP_IOXPUT_16(isp, Is->icb_maxfrmlen, &Id->icb_maxfrmlen); + ISP_IOXPUT_16(isp, Is->icb_maxalloc, &Id->icb_maxalloc); + ISP_IOXPUT_16(isp, Is->icb_execthrottle, &Id->icb_execthrottle); + ISP_SWAP8(Is->icb_retry_count, Is->icb_retry_delay); + ISP_IOXPUT_8(isp, Is->icb_retry_count, &Id->icb_retry_count); + ISP_IOXPUT_8(isp, Is->icb_retry_delay, &Id->icb_retry_delay); + for (i = 0; i < 8; i++) { + ISP_IOXPUT_8(isp, Is->icb_portname[i], &Id->icb_portname[i]); + } + ISP_IOXPUT_16(isp, Is->icb_hardaddr, &Id->icb_hardaddr); + ISP_SWAP8(Is->icb_iqdevtype, Is->icb_logintime); + ISP_IOXPUT_8(isp, Is->icb_iqdevtype, &Id->icb_iqdevtype); + ISP_IOXPUT_8(isp, Is->icb_logintime, &Id->icb_logintime); + for (i = 0; i < 8; i++) { + ISP_IOXPUT_8(isp, Is->icb_nodename[i], &Id->icb_nodename[i]); + } + ISP_IOXPUT_16(isp, Is->icb_rqstout, &Id->icb_rqstout); + ISP_IOXPUT_16(isp, Is->icb_rspnsin, &Id->icb_rspnsin); + ISP_IOXPUT_16(isp, Is->icb_rqstqlen, &Id->icb_rqstqlen); + ISP_IOXPUT_16(isp, Is->icb_rsltqlen, &Id->icb_rsltqlen); + for (i = 0; i < 4; i++) { + ISP_IOXPUT_16(isp, Is->icb_rqstaddr[i], &Id->icb_rqstaddr[i]); + } + for (i = 0; i < 4; i++) { + ISP_IOXPUT_16(isp, Is->icb_respaddr[i], &Id->icb_respaddr[i]); + } + ISP_IOXPUT_16(isp, Is->icb_lunenables, &Id->icb_lunenables); + ISP_SWAP8(Is->icb_ccnt, Is->icb_icnt); + ISP_IOXPUT_8(isp, Is->icb_ccnt, &Id->icb_ccnt); + ISP_IOXPUT_8(isp, Is->icb_icnt, &Id->icb_icnt); + ISP_IOXPUT_16(isp, Is->icb_lunetimeout, &Id->icb_lunetimeout); + ISP_IOXPUT_16(isp, Is->icb_xfwoptions, &Id->icb_xfwoptions); + ISP_SWAP8(Is->icb_racctimer, Is->icb_idelaytimer); + ISP_IOXPUT_8(isp, Is->icb_racctimer, &Id->icb_racctimer); + ISP_IOXPUT_8(isp, Is->icb_idelaytimer, &Id->icb_idelaytimer); + ISP_IOXPUT_16(isp, Is->icb_zfwoptions, &Id->icb_zfwoptions); +} + +static INLINE void +isp_get_pdb(struct ispsoftc *isp, isp_pdb_t *src, isp_pdb_t *dst) +{ + int i; + ISP_IOXGET_16(isp, &src->pdb_options, dst->pdb_options); + ISP_IOXGET_8(isp, &src->pdb_mstate, dst->pdb_mstate); + ISP_IOXGET_8(isp, &src->pdb_sstate, dst->pdb_sstate); + for (i = 0; i < 4; i++) { + ISP_IOXGET_8(isp, &src->pdb_hardaddr_bits[i], + dst->pdb_hardaddr_bits[i]); + } + for (i = 0; i < 4; i++) { + ISP_IOXGET_8(isp, &src->pdb_portid_bits[i], + dst->pdb_portid_bits[i]); + } + for (i = 0; i < 8; i++) { + ISP_IOXGET_8(isp, &src->pdb_nodename[i], dst->pdb_nodename[i]); + } + for (i = 0; i < 8; i++) { + ISP_IOXGET_8(isp, &src->pdb_portname[i], dst->pdb_portname[i]); + } + ISP_IOXGET_16(isp, &src->pdb_execthrottle, dst->pdb_execthrottle); + ISP_IOXGET_16(isp, &src->pdb_exec_count, dst->pdb_exec_count); + ISP_IOXGET_8(isp, &src->pdb_retry_count, dst->pdb_retry_count); + ISP_IOXGET_8(isp, &src->pdb_retry_delay, dst->pdb_retry_delay); + ISP_IOXGET_16(isp, &src->pdb_resalloc, dst->pdb_resalloc); + ISP_IOXGET_16(isp, &src->pdb_curalloc, dst->pdb_curalloc); + ISP_IOXGET_16(isp, &src->pdb_qhead, dst->pdb_qhead); + ISP_IOXGET_16(isp, &src->pdb_qtail, dst->pdb_qtail); + ISP_IOXGET_16(isp, &src->pdb_tl_next, dst->pdb_tl_next); + ISP_IOXGET_16(isp, &src->pdb_tl_last, dst->pdb_tl_last); + ISP_IOXGET_16(isp, &src->pdb_features, dst->pdb_features); + ISP_IOXGET_16(isp, &src->pdb_pconcurrnt, dst->pdb_pconcurrnt); + ISP_IOXGET_16(isp, &src->pdb_roi, dst->pdb_roi); + ISP_IOXGET_8(isp, &src->pdb_target, dst->pdb_target); + ISP_IOXGET_8(isp, &src->pdb_initiator, dst->pdb_initiator); + ISP_IOXGET_16(isp, &src->pdb_rdsiz, dst->pdb_rdsiz); + ISP_IOXGET_16(isp, &src->pdb_ncseq, dst->pdb_ncseq); + ISP_IOXGET_16(isp, &src->pdb_noseq, dst->pdb_noseq); + ISP_IOXGET_16(isp, &src->pdb_labrtflg, dst->pdb_labrtflg); + ISP_IOXGET_16(isp, &src->pdb_lstopflg, dst->pdb_lstopflg); + ISP_IOXGET_16(isp, &src->pdb_sqhead, dst->pdb_sqhead); + ISP_IOXGET_16(isp, &src->pdb_sqtail, dst->pdb_sqtail); + ISP_IOXGET_16(isp, &src->pdb_ptimer, dst->pdb_ptimer); + ISP_IOXGET_16(isp, &src->pdb_nxt_seqid, dst->pdb_nxt_seqid); + ISP_IOXGET_16(isp, &src->pdb_fcount, dst->pdb_fcount); + ISP_IOXGET_16(isp, &src->pdb_prli_len, dst->pdb_prli_len); + ISP_IOXGET_16(isp, &src->pdb_prli_svc0, dst->pdb_prli_svc0); + ISP_IOXGET_16(isp, &src->pdb_prli_svc3, dst->pdb_prli_svc3); + ISP_IOXGET_16(isp, &src->pdb_loopid, dst->pdb_loopid); + ISP_IOXGET_16(isp, &src->pdb_il_ptr, dst->pdb_il_ptr); + ISP_IOXGET_16(isp, &src->pdb_sl_ptr, dst->pdb_sl_ptr); +} + + +/* + * CT_HDR canonicalization- only needed for SNS responses + */ +static INLINE void +isp_get_ct_hdr(struct ispsoftc *isp, ct_hdr_t *src, ct_hdr_t *dst) +{ + ISP_IOXGET_8(isp, &src->ct_revision, dst->ct_revision); + ISP_IOXGET_8(isp, &src->ct_portid[0], dst->ct_portid[0]); + ISP_IOXGET_8(isp, &src->ct_portid[1], dst->ct_portid[1]); + ISP_IOXGET_8(isp, &src->ct_portid[2], dst->ct_portid[2]); + ISP_IOXGET_8(isp, &src->ct_fcs_type, dst->ct_fcs_type); + ISP_IOXGET_8(isp, &src->ct_fcs_subtype, dst->ct_fcs_subtype); + ISP_IOXGET_8(isp, &src->ct_options, dst->ct_options); + ISP_IOXGET_8(isp, &src->ct_res0, dst->ct_res0); + ISP_IOXGET_16(isp, &src->ct_response, dst->ct_response); + dst->ct_response = (dst->ct_response << 8) | (dst->ct_response >> 8); + ISP_IOXGET_16(isp, &src->ct_resid, dst->ct_resid); + dst->ct_resid = (dst->ct_resid << 8) | (dst->ct_resid >> 8); + ISP_IOXGET_8(isp, &src->ct_res1, dst->ct_res1); + ISP_IOXGET_8(isp, &src->ct_reason, dst->ct_reason); + ISP_IOXGET_8(isp, &src->ct_explanation, dst->ct_explanation); + ISP_IOXGET_8(isp, &src->ct_vunique, dst->ct_vunique); +} + +/* + * Generic SNS request - not particularly useful since the per-command data + * isn't always 16 bit words. + */ +static INLINE void +isp_put_sns_request(struct ispsoftc *isp, sns_screq_t *src, sns_screq_t *dst) +{ + int i, nw = (int) src->snscb_sblen; + ISP_IOXPUT_16(isp, src->snscb_rblen, &dst->snscb_rblen); + for (i = 0; i < 4; i++) { + ISP_IOXPUT_16(isp, src->snscb_addr[i], &dst->snscb_addr[i]); + } + ISP_IOXPUT_16(isp, src->snscb_sblen, &dst->snscb_sblen); + for (i = 0; i < nw; i++) { + ISP_IOXPUT_16(isp, src->snscb_data[i], &dst->snscb_data[i]); + } + +} + +static INLINE void +isp_put_gid_ft_request(struct ispsoftc *isp, sns_gid_ft_req_t *src, + sns_gid_ft_req_t *dst) +{ + ISP_IOXPUT_16(isp, src->snscb_rblen, &dst->snscb_rblen); + ISP_IOXPUT_16(isp, src->snscb_res0, &dst->snscb_res0); + ISP_IOXPUT_16(isp, src->snscb_addr[0], &dst->snscb_addr[0]); + ISP_IOXPUT_16(isp, src->snscb_addr[1], &dst->snscb_addr[1]); + ISP_IOXPUT_16(isp, src->snscb_addr[2], &dst->snscb_addr[2]); + ISP_IOXPUT_16(isp, src->snscb_addr[3], &dst->snscb_addr[3]); + ISP_IOXPUT_16(isp, src->snscb_sblen, &dst->snscb_sblen); + ISP_IOXPUT_16(isp, src->snscb_res1, &dst->snscb_res1); + ISP_IOXPUT_16(isp, src->snscb_cmd, &dst->snscb_cmd); + ISP_IOXPUT_16(isp, src->snscb_mword_div_2, &dst->snscb_mword_div_2); + ISP_IOXPUT_32(isp, src->snscb_res3, &dst->snscb_res3); + ISP_IOXPUT_32(isp, src->snscb_fc4_type, &dst->snscb_fc4_type); +} + +static INLINE void +isp_put_gxn_id_request(struct ispsoftc *isp, sns_gxn_id_req_t *src, + sns_gxn_id_req_t *dst) +{ + ISP_IOXPUT_16(isp, src->snscb_rblen, &dst->snscb_rblen); + ISP_IOXPUT_16(isp, src->snscb_res0, &dst->snscb_res0); + ISP_IOXPUT_16(isp, src->snscb_addr[0], &dst->snscb_addr[0]); + ISP_IOXPUT_16(isp, src->snscb_addr[1], &dst->snscb_addr[1]); + ISP_IOXPUT_16(isp, src->snscb_addr[2], &dst->snscb_addr[2]); + ISP_IOXPUT_16(isp, src->snscb_addr[3], &dst->snscb_addr[3]); + ISP_IOXPUT_16(isp, src->snscb_sblen, &dst->snscb_sblen); + ISP_IOXPUT_16(isp, src->snscb_res1, &dst->snscb_res1); + ISP_IOXPUT_16(isp, src->snscb_cmd, &dst->snscb_cmd); + ISP_IOXPUT_16(isp, src->snscb_res2, &dst->snscb_res2); + ISP_IOXPUT_32(isp, src->snscb_res3, &dst->snscb_res3); + ISP_IOXPUT_32(isp, src->snscb_portid, &dst->snscb_portid); +} + +/* + * Generic SNS response - not particularly useful since the per-command data + * isn't always 16 bit words. + */ +static INLINE void +isp_get_sns_response(struct ispsoftc *isp, sns_scrsp_t *src, + sns_scrsp_t *dst, int nwords) +{ + int i; + isp_get_ct_hdr(isp, &src->snscb_cthdr, &dst->snscb_cthdr); + ISP_IOXGET_8(isp, &src->snscb_port_type, dst->snscb_port_type); + for (i = 0; i < 3; i++) { + ISP_IOXGET_8(isp, &src->snscb_port_id[i], + dst->snscb_port_id[i]); + } + for (i = 0; i < 8; i++) { + ISP_IOXGET_8(isp, &src->snscb_portname[i], + dst->snscb_portname[i]); + } + for (i = 0; i < nwords; i++) { + ISP_IOXGET_16(isp, &src->snscb_data[i], dst->snscb_data[i]); + } +} + +static INLINE void +isp_get_gid_ft_response(struct ispsoftc *isp, sns_gid_ft_rsp_t *src, + sns_gid_ft_rsp_t *dst, int nwords) +{ + int i; + isp_get_ct_hdr(isp, &src->snscb_cthdr, &dst->snscb_cthdr); + for (i = 0; i < nwords; i++) { + int j; + ISP_IOXGET_8(isp, + &src->snscb_ports[i].control, + dst->snscb_ports[i].control); + for (j = 0; j < 3; j++) { + ISP_IOXGET_8(isp, + &src->snscb_ports[i].portid[j], + dst->snscb_ports[i].portid[j]); + } + if (dst->snscb_ports[i].control & 0x80) { + break; + } + } +} + +static INLINE void +isp_get_gxn_id_response(struct ispsoftc *isp, sns_gxn_id_rsp_t *src, + sns_gxn_id_rsp_t *dst) +{ + int i; + isp_get_ct_hdr(isp, &src->snscb_cthdr, &dst->snscb_cthdr); + for (i = 0; i < 8; i++) + ISP_IOXGET_8(isp, &src->snscb_wwn[i], dst->snscb_wwn[i]); +} + +static INLINE void +isp_get_gff_id_response(struct ispsoftc *isp, sns_gff_id_rsp_t *src, + sns_gff_id_rsp_t *dst) +{ + int i; + isp_get_ct_hdr(isp, &src->snscb_cthdr, &dst->snscb_cthdr); + for (i = 0; i < 32; i++) { + ISP_IOXGET_32(isp, &src->snscb_fc4_features[i], + dst->snscb_fc4_features[i]); + } +} + +static INLINE void +isp_get_ga_nxt_response(struct ispsoftc *isp, sns_ga_nxt_rsp_t *src, + sns_ga_nxt_rsp_t *dst) +{ + int i; + isp_get_ct_hdr(isp, &src->snscb_cthdr, &dst->snscb_cthdr); + ISP_IOXGET_8(isp, &src->snscb_port_type, dst->snscb_port_type); + for (i = 0; i < 3; i++) { + ISP_IOXGET_8(isp, &src->snscb_port_id[i], + dst->snscb_port_id[i]); + } + for (i = 0; i < 8; i++) { + ISP_IOXGET_8(isp, &src->snscb_portname[i], + dst->snscb_portname[i]); + } + ISP_IOXGET_8(isp, &src->snscb_pnlen, dst->snscb_pnlen); + for (i = 0; i < 255; i++) { + ISP_IOXGET_8(isp, &src->snscb_pname[i], dst->snscb_pname[i]); + } + for (i = 0; i < 8; i++) { + ISP_IOXGET_8(isp, &src->snscb_nodename[i], + dst->snscb_nodename[i]); + } + ISP_IOXGET_8(isp, &src->snscb_nnlen, dst->snscb_nnlen); + for (i = 0; i < 255; i++) { + ISP_IOXGET_8(isp, &src->snscb_nname[i], dst->snscb_nname[i]); + } + for (i = 0; i < 8; i++) { + ISP_IOXGET_8(isp, &src->snscb_ipassoc[i], + dst->snscb_ipassoc[i]); + } + for (i = 0; i < 16; i++) { + ISP_IOXGET_8(isp, &src->snscb_ipaddr[i], dst->snscb_ipaddr[i]); + } + for (i = 0; i < 4; i++) { + ISP_IOXGET_8(isp, &src->snscb_svc_class[i], + dst->snscb_svc_class[i]); + } + for (i = 0; i < 32; i++) { + ISP_IOXGET_8(isp, &src->snscb_fc4_types[i], + dst->snscb_fc4_types[i]); + } + for (i = 0; i < 8; i++) { + ISP_IOXGET_8(isp, &src->snscb_fpname[i], dst->snscb_fpname[i]); + } + ISP_IOXGET_8(isp, &src->snscb_reserved, dst->snscb_reserved); + for (i = 0; i < 3; i++) { + ISP_IOXGET_8(isp, &src->snscb_hardaddr[i], + dst->snscb_hardaddr[i]); + } +} + +#ifdef ISP_TARGET_MODE +static INLINE void +isp_put_atio(struct ispsoftc *isp, at_entry_t *atsrc, at_entry_t *atdst) +{ + int i; + isp_copy_out_hdr(isp, &atsrc->at_header, &atdst->at_header); + ISP_IOXPUT_16(isp, atsrc->at_reserved, &atdst->at_reserved); + ISP_IOXPUT_16(isp, atsrc->at_handle, &atdst->at_handle); + if (ISP_IS_SBUS(isp)) { + ISP_IOXPUT_8(isp, atsrc->at_lun, &atdst->at_iid); + ISP_IOXPUT_8(isp, atsrc->at_iid, &atdst->at_lun); + ISP_IOXPUT_8(isp, atsrc->at_cdblen, &atdst->at_tgt); + ISP_IOXPUT_8(isp, atsrc->at_tgt, &atdst->at_cdblen); + ISP_IOXPUT_8(isp, atsrc->at_status, &atdst->at_scsi_status); + ISP_IOXPUT_8(isp, atsrc->at_scsi_status, &atdst->at_status); + ISP_IOXPUT_8(isp, atsrc->at_tag_val, &atdst->at_tag_type); + ISP_IOXPUT_8(isp, atsrc->at_tag_type, &atdst->at_tag_val); + } else { + ISP_IOXPUT_8(isp, atsrc->at_lun, &atdst->at_lun); + ISP_IOXPUT_8(isp, atsrc->at_iid, &atdst->at_iid); + ISP_IOXPUT_8(isp, atsrc->at_cdblen, &atdst->at_cdblen); + ISP_IOXPUT_8(isp, atsrc->at_tgt, &atdst->at_tgt); + ISP_IOXPUT_8(isp, atsrc->at_status, &atdst->at_status); + ISP_IOXPUT_8(isp, atsrc->at_scsi_status, + &atdst->at_scsi_status); + ISP_IOXPUT_8(isp, atsrc->at_tag_val, &atdst->at_tag_val); + ISP_IOXPUT_8(isp, atsrc->at_tag_type, &atdst->at_tag_type); + } + ISP_IOXPUT_32(isp, atsrc->at_flags, &atdst->at_flags); + for (i = 0; i < ATIO_CDBLEN; i++) { + ISP_IOXPUT_8(isp, atsrc->at_cdb[i], &atdst->at_cdb[i]); + } + for (i = 0; i < QLTM_SENSELEN; i++) { + ISP_IOXPUT_8(isp, atsrc->at_sense[i], &atdst->at_sense[i]); + } +} + +static INLINE void +isp_get_atio(struct ispsoftc *isp, at_entry_t *atsrc, at_entry_t *atdst) +{ + int i; + isp_copy_in_hdr(isp, &atsrc->at_header, &atdst->at_header); + ISP_IOXGET_16(isp, &atsrc->at_reserved, atdst->at_reserved); + ISP_IOXGET_16(isp, &atsrc->at_handle, atdst->at_handle); + if (ISP_IS_SBUS(isp)) { + ISP_IOXGET_8(isp, &atsrc->at_lun, atdst->at_iid); + ISP_IOXGET_8(isp, &atsrc->at_iid, atdst->at_lun); + ISP_IOXGET_8(isp, &atsrc->at_cdblen, atdst->at_tgt); + ISP_IOXGET_8(isp, &atsrc->at_tgt, atdst->at_cdblen); + ISP_IOXGET_8(isp, &atsrc->at_status, atdst->at_scsi_status); + ISP_IOXGET_8(isp, &atsrc->at_scsi_status, atdst->at_status); + ISP_IOXGET_8(isp, &atsrc->at_tag_val, atdst->at_tag_type); + ISP_IOXGET_8(isp, &atsrc->at_tag_type, atdst->at_tag_val); + } else { + ISP_IOXGET_8(isp, &atsrc->at_lun, atdst->at_lun); + ISP_IOXGET_8(isp, &atsrc->at_iid, atdst->at_iid); + ISP_IOXGET_8(isp, &atsrc->at_cdblen, atdst->at_cdblen); + ISP_IOXGET_8(isp, &atsrc->at_tgt, atdst->at_tgt); + ISP_IOXGET_8(isp, &atsrc->at_status, atdst->at_status); + ISP_IOXGET_8(isp, &atsrc->at_scsi_status, + atdst->at_scsi_status); + ISP_IOXGET_8(isp, &atsrc->at_tag_val, atdst->at_tag_val); + ISP_IOXGET_8(isp, &atsrc->at_tag_type, atdst->at_tag_type); + } + ISP_IOXGET_32(isp, &atsrc->at_flags, atdst->at_flags); + for (i = 0; i < ATIO_CDBLEN; i++) { + ISP_IOXGET_8(isp, &atsrc->at_cdb[i], atdst->at_cdb[i]); + } + for (i = 0; i < QLTM_SENSELEN; i++) { + ISP_IOXGET_8(isp, &atsrc->at_sense[i], atdst->at_sense[i]); + } +} + +static INLINE void +isp_put_atio2(struct ispsoftc *isp, at2_entry_t *atsrc, at2_entry_t *atdst) +{ + int i; + isp_copy_out_hdr(isp, &atsrc->at_header, &atdst->at_header); + ISP_IOXPUT_32(isp, atsrc->at_reserved, &atdst->at_reserved); + ISP_IOXPUT_8(isp, atsrc->at_lun, &atdst->at_lun); + ISP_IOXPUT_8(isp, atsrc->at_iid, &atdst->at_iid); + ISP_IOXPUT_16(isp, atsrc->at_rxid, &atdst->at_rxid); + ISP_IOXPUT_16(isp, atsrc->at_flags, &atdst->at_flags); + ISP_IOXPUT_16(isp, atsrc->at_status, &atdst->at_status); + ISP_IOXPUT_8(isp, atsrc->at_reserved1, &atdst->at_reserved1); + ISP_IOXPUT_8(isp, atsrc->at_taskcodes, &atdst->at_taskcodes); + ISP_IOXPUT_8(isp, atsrc->at_taskflags, &atdst->at_taskflags); + ISP_IOXPUT_8(isp, atsrc->at_execodes, &atdst->at_execodes); + for (i = 0; i < ATIO2_CDBLEN; i++) { + ISP_IOXPUT_8(isp, atsrc->at_cdb[i], &atdst->at_cdb[i]); + } + ISP_IOXPUT_32(isp, atsrc->at_datalen, &atdst->at_datalen); + ISP_IOXPUT_16(isp, atsrc->at_scclun, &atdst->at_scclun); + for (i = 0; i < 4; i++) { + ISP_IOXPUT_16(isp, atsrc->at_wwpn[i], &atdst->at_wwpn[i]); + } + for (i = 0; i < 6; i++) { + ISP_IOXPUT_16(isp, atsrc->at_reserved2[i], + &atdst->at_reserved2[i]); + } + ISP_IOXPUT_16(isp, atsrc->at_oxid, &atdst->at_oxid); +} + +static INLINE void +isp_get_atio2(struct ispsoftc *isp, at2_entry_t *atsrc, at2_entry_t *atdst) +{ + int i; + isp_copy_in_hdr(isp, &atsrc->at_header, &atdst->at_header); + ISP_IOXGET_32(isp, &atsrc->at_reserved, atdst->at_reserved); + ISP_IOXGET_8(isp, &atsrc->at_lun, atdst->at_lun); + ISP_IOXGET_8(isp, &atsrc->at_iid, atdst->at_iid); + ISP_IOXGET_16(isp, &atsrc->at_rxid, atdst->at_rxid); + ISP_IOXGET_16(isp, &atsrc->at_flags, atdst->at_flags); + ISP_IOXGET_16(isp, &atsrc->at_status, atdst->at_status); + ISP_IOXGET_8(isp, &atsrc->at_reserved1, atdst->at_reserved1); + ISP_IOXGET_8(isp, &atsrc->at_taskcodes, atdst->at_taskcodes); + ISP_IOXGET_8(isp, &atsrc->at_taskflags, atdst->at_taskflags); + ISP_IOXGET_8(isp, &atsrc->at_execodes, atdst->at_execodes); + for (i = 0; i < ATIO2_CDBLEN; i++) { + ISP_IOXGET_8(isp, &atsrc->at_cdb[i], atdst->at_cdb[i]); + } + ISP_IOXGET_32(isp, &atsrc->at_datalen, atdst->at_datalen); + ISP_IOXGET_16(isp, &atsrc->at_scclun, atdst->at_scclun); + for (i = 0; i < 4; i++) { + ISP_IOXGET_16(isp, &atsrc->at_wwpn[i], atdst->at_wwpn[i]); + } + for (i = 0; i < 6; i++) { + ISP_IOXGET_16(isp, &atsrc->at_reserved2[i], + atdst->at_reserved2[i]); + } + ISP_IOXGET_16(isp, &atsrc->at_oxid, atdst->at_oxid); +} + +static INLINE void +isp_put_ctio(struct ispsoftc *isp, ct_entry_t *ctsrc, ct_entry_t *ctdst) +{ + int i; + isp_copy_out_hdr(isp, &ctsrc->ct_header, &ctdst->ct_header); + ISP_IOXPUT_16(isp, ctsrc->ct_reserved, &ctdst->ct_reserved); + ISP_IOXPUT_16(isp, ctsrc->ct_fwhandle, &ctdst->ct_fwhandle); + if (ISP_IS_SBUS(isp)) { + ISP_IOXPUT_8(isp, ctsrc->ct_iid, &ctdst->ct_lun); + ISP_IOXPUT_8(isp, ctsrc->ct_lun, &ctdst->ct_iid); + ISP_IOXPUT_8(isp, ctsrc->ct_tgt, &ctdst->ct_reserved2); + ISP_IOXPUT_8(isp, ctsrc->ct_reserved2, &ctdst->ct_tgt); + ISP_IOXPUT_8(isp, ctsrc->ct_status, &ctdst->ct_scsi_status); + ISP_IOXPUT_8(isp, ctsrc->ct_scsi_status, &ctdst->ct_status); + ISP_IOXPUT_8(isp, ctsrc->ct_tag_type, &ctdst->ct_tag_val); + ISP_IOXPUT_8(isp, ctsrc->ct_tag_val, &ctdst->ct_tag_type); + } else { + ISP_IOXPUT_8(isp, ctsrc->ct_iid, &ctdst->ct_iid); + ISP_IOXPUT_8(isp, ctsrc->ct_lun, &ctdst->ct_lun); + ISP_IOXPUT_8(isp, ctsrc->ct_tgt, &ctdst->ct_tgt); + ISP_IOXPUT_8(isp, ctsrc->ct_reserved2, &ctdst->ct_reserved2); + ISP_IOXPUT_8(isp, ctsrc->ct_scsi_status, + &ctdst->ct_scsi_status); + ISP_IOXPUT_8(isp, ctsrc->ct_status, &ctdst->ct_status); + ISP_IOXPUT_8(isp, ctsrc->ct_tag_type, &ctdst->ct_tag_type); + ISP_IOXPUT_8(isp, ctsrc->ct_tag_val, &ctdst->ct_tag_val); + } + ISP_IOXPUT_32(isp, ctsrc->ct_flags, &ctdst->ct_flags); + ISP_IOXPUT_32(isp, ctsrc->ct_xfrlen, &ctdst->ct_xfrlen); + ISP_IOXPUT_32(isp, ctsrc->ct_resid, &ctdst->ct_resid); + ISP_IOXPUT_16(isp, ctsrc->ct_timeout, &ctdst->ct_timeout); + ISP_IOXPUT_16(isp, ctsrc->ct_seg_count, &ctdst->ct_seg_count); + for (i = 0; i < ISP_RQDSEG; i++) { + ISP_IOXPUT_32(isp, ctsrc->ct_dataseg[i].ds_base, + &ctdst->ct_dataseg[i].ds_base); + ISP_IOXPUT_32(isp, ctsrc->ct_dataseg[i].ds_count, + &ctdst->ct_dataseg[i].ds_count); + } +} + +static INLINE void +isp_get_ctio(struct ispsoftc *isp, ct_entry_t *ctsrc, ct_entry_t *ctdst) +{ + int i; + isp_copy_in_hdr(isp, &ctsrc->ct_header, &ctdst->ct_header); + ISP_IOXGET_16(isp, &ctsrc->ct_reserved, ctdst->ct_reserved); + ISP_IOXGET_16(isp, &ctsrc->ct_fwhandle, ctdst->ct_fwhandle); + if (ISP_IS_SBUS(isp)) { + ISP_IOXGET_8(isp, &ctsrc->ct_lun, ctdst->ct_iid); + ISP_IOXGET_8(isp, &ctsrc->ct_iid, ctdst->ct_lun); + ISP_IOXGET_8(isp, &ctsrc->ct_reserved2, ctdst->ct_tgt); + ISP_IOXGET_8(isp, &ctsrc->ct_tgt, ctdst->ct_reserved2); + ISP_IOXGET_8(isp, &ctsrc->ct_status, ctdst->ct_scsi_status); + ISP_IOXGET_8(isp, &ctsrc->ct_scsi_status, ctdst->ct_status); + ISP_IOXGET_8(isp, &ctsrc->ct_tag_val, ctdst->ct_tag_type); + ISP_IOXGET_8(isp, &ctsrc->ct_tag_type, ctdst->ct_tag_val); + } else { + ISP_IOXGET_8(isp, &ctsrc->ct_lun, ctdst->ct_lun); + ISP_IOXGET_8(isp, &ctsrc->ct_iid, ctdst->ct_iid); + ISP_IOXGET_8(isp, &ctsrc->ct_reserved2, ctdst->ct_reserved2); + ISP_IOXGET_8(isp, &ctsrc->ct_tgt, ctdst->ct_tgt); + ISP_IOXGET_8(isp, &ctsrc->ct_status, ctdst->ct_status); + ISP_IOXGET_8(isp, &ctsrc->ct_scsi_status, + ctdst->ct_scsi_status); + ISP_IOXGET_8(isp, &ctsrc->ct_tag_val, ctdst->ct_tag_val); + ISP_IOXGET_8(isp, &ctsrc->ct_tag_type, ctdst->ct_tag_type); + } + ISP_IOXGET_32(isp, &ctsrc->ct_flags, ctdst->ct_flags); + ISP_IOXGET_32(isp, &ctsrc->ct_xfrlen, ctdst->ct_xfrlen); + ISP_IOXGET_32(isp, &ctsrc->ct_resid, ctdst->ct_resid); + ISP_IOXGET_16(isp, &ctsrc->ct_timeout, ctdst->ct_timeout); + ISP_IOXGET_16(isp, &ctsrc->ct_seg_count, ctdst->ct_seg_count); + for (i = 0; i < ISP_RQDSEG; i++) { + ISP_IOXGET_32(isp, + &ctsrc->ct_dataseg[i].ds_base, + ctdst->ct_dataseg[i].ds_base); + ISP_IOXGET_32(isp, + &ctsrc->ct_dataseg[i].ds_count, + ctdst->ct_dataseg[i].ds_count); + } +} + +static INLINE void +isp_put_ctio2(struct ispsoftc *isp, ct2_entry_t *ctsrc, ct2_entry_t *ctdst) +{ + int i; + isp_copy_out_hdr(isp, &ctsrc->ct_header, &ctdst->ct_header); + ISP_IOXPUT_16(isp, ctsrc->ct_reserved, &ctdst->ct_reserved); + ISP_IOXPUT_16(isp, ctsrc->ct_fwhandle, &ctdst->ct_fwhandle); + ISP_IOXPUT_8(isp, ctsrc->ct_lun, &ctdst->ct_lun); + ISP_IOXPUT_8(isp, ctsrc->ct_iid, &ctdst->ct_iid); + ISP_IOXPUT_16(isp, ctsrc->ct_rxid, &ctdst->ct_rxid); + ISP_IOXPUT_16(isp, ctsrc->ct_flags, &ctdst->ct_flags); + ISP_IOXPUT_16(isp, ctsrc->ct_timeout, &ctdst->ct_timeout); + ISP_IOXPUT_16(isp, ctsrc->ct_seg_count, &ctdst->ct_seg_count); + ISP_IOXPUT_32(isp, ctsrc->ct_resid, &ctdst->ct_resid); + ISP_IOXPUT_32(isp, ctsrc->ct_reloff, &ctdst->ct_reloff); + if ((ctsrc->ct_flags & CT2_FLAG_MMASK) == CT2_FLAG_MODE0) { + ISP_IOXPUT_32(isp, ctsrc->rsp.m0._reserved, + &ctdst->rsp.m0._reserved); + ISP_IOXPUT_16(isp, ctsrc->rsp.m0._reserved2, + &ctdst->rsp.m0._reserved2); + ISP_IOXPUT_16(isp, ctsrc->rsp.m0.ct_scsi_status, + &ctdst->rsp.m0.ct_scsi_status); + ISP_IOXPUT_32(isp, ctsrc->rsp.m0.ct_xfrlen, + &ctdst->rsp.m0.ct_xfrlen); + if (ctsrc->ct_header.rqs_entry_type == RQSTYPE_CTIO2) { + for (i = 0; i < ISP_RQDSEG_T2; i++) { + ISP_IOXPUT_32(isp, + ctsrc->rsp.m0.ct_dataseg[i].ds_base, + &ctdst->rsp.m0.ct_dataseg[i].ds_base); + ISP_IOXPUT_32(isp, + ctsrc->rsp.m0.ct_dataseg[i].ds_count, + &ctdst->rsp.m0.ct_dataseg[i].ds_count); + } + } else if (ctsrc->ct_header.rqs_entry_type == RQSTYPE_CTIO3) { + for (i = 0; i < ISP_RQDSEG_T3; i++) { + ISP_IOXPUT_32(isp, + ctsrc->rsp.m0.ct_dataseg64[i].ds_base, + &ctdst->rsp.m0.ct_dataseg64[i].ds_base); + ISP_IOXPUT_32(isp, + ctsrc->rsp.m0.ct_dataseg64[i].ds_basehi, + &ctdst->rsp.m0.ct_dataseg64[i].ds_basehi); + ISP_IOXPUT_32(isp, + ctsrc->rsp.m0.ct_dataseg64[i].ds_count, + &ctdst->rsp.m0.ct_dataseg64[i].ds_count); + } + } else if (ctsrc->ct_header.rqs_entry_type == RQSTYPE_CTIO4) { + ISP_IOXPUT_16(isp, ctsrc->rsp.m0.ct_dslist.ds_type, + &ctdst->rsp.m0.ct_dslist.ds_type); + ISP_IOXPUT_32(isp, ctsrc->rsp.m0.ct_dslist.ds_segment, + &ctdst->rsp.m0.ct_dslist.ds_segment); + ISP_IOXPUT_32(isp, ctsrc->rsp.m0.ct_dslist.ds_base, + &ctdst->rsp.m0.ct_dslist.ds_base); + } + } else if ((ctsrc->ct_flags & CT2_FLAG_MMASK) == CT2_FLAG_MODE1) { + ISP_IOXPUT_16(isp, ctsrc->rsp.m1._reserved, + &ctdst->rsp.m1._reserved); + ISP_IOXPUT_16(isp, ctsrc->rsp.m1._reserved2, + &ctdst->rsp.m1._reserved2); + ISP_IOXPUT_16(isp, ctsrc->rsp.m1.ct_senselen, + &ctdst->rsp.m1.ct_senselen); + ISP_IOXPUT_16(isp, ctsrc->rsp.m1.ct_scsi_status, + &ctdst->rsp.m1.ct_scsi_status); + ISP_IOXPUT_16(isp, ctsrc->rsp.m1.ct_resplen, + &ctdst->rsp.m1.ct_resplen); + for (i = 0; i < MAXRESPLEN; i++) { + ISP_IOXPUT_8(isp, ctsrc->rsp.m1.ct_resp[i], + &ctdst->rsp.m1.ct_resp[i]); + } + } else { + ISP_IOXPUT_32(isp, ctsrc->rsp.m2._reserved, + &ctdst->rsp.m2._reserved); + ISP_IOXPUT_16(isp, ctsrc->rsp.m2._reserved2, + &ctdst->rsp.m2._reserved2); + ISP_IOXPUT_16(isp, ctsrc->rsp.m2._reserved3, + &ctdst->rsp.m2._reserved3); + ISP_IOXPUT_32(isp, ctsrc->rsp.m2.ct_datalen, + &ctdst->rsp.m2.ct_datalen); + ISP_IOXPUT_32(isp, ctsrc->rsp.m2.ct_fcp_rsp_iudata.ds_base, + &ctdst->rsp.m2.ct_fcp_rsp_iudata.ds_base); + ISP_IOXPUT_32(isp, ctsrc->rsp.m2.ct_fcp_rsp_iudata.ds_count, + &ctdst->rsp.m2.ct_fcp_rsp_iudata.ds_count); + } +} + +static INLINE void +isp_get_ctio2(struct ispsoftc *isp, ct2_entry_t *ctsrc, ct2_entry_t *ctdst) +{ + int i; + isp_copy_in_hdr(isp, &ctsrc->ct_header, &ctdst->ct_header); + ISP_IOXGET_16(isp, &ctsrc->ct_reserved, ctdst->ct_reserved); + ISP_IOXGET_16(isp, &ctsrc->ct_fwhandle, ctdst->ct_fwhandle); + ISP_IOXGET_8(isp, &ctsrc->ct_lun, ctdst->ct_lun); + ISP_IOXGET_8(isp, &ctsrc->ct_iid, ctdst->ct_iid); + ISP_IOXGET_16(isp, &ctsrc->ct_rxid, ctdst->ct_rxid); + ISP_IOXGET_16(isp, &ctsrc->ct_flags, ctdst->ct_flags); + ISP_IOXGET_16(isp, &ctsrc->ct_status, ctdst->ct_status); + ISP_IOXGET_16(isp, &ctsrc->ct_timeout, ctdst->ct_timeout); + ISP_IOXGET_16(isp, &ctsrc->ct_seg_count, ctdst->ct_seg_count); + ISP_IOXGET_32(isp, &ctsrc->ct_reloff, ctdst->ct_reloff); + ISP_IOXGET_32(isp, &ctsrc->ct_resid, ctdst->ct_resid); + for (i = 0; i < 4; i++) { + ISP_IOXGET_32(isp, &ctsrc->rsp.fw._reserved[i], + ctdst->rsp.fw._reserved[i]); + } + ISP_IOXGET_16(isp, &ctsrc->rsp.fw.ct_scsi_status, + ctdst->rsp.fw.ct_scsi_status); + for (i = 0; i < QLTM_SENSELEN; i++) { + ISP_IOXGET_8(isp, &ctsrc->rsp.fw.ct_sense[i], + ctdst->rsp.fw.ct_sense[i]); + } +} + +static INLINE void +isp_put_enable_lun(struct ispsoftc *isp, lun_entry_t *lesrc, lun_entry_t *ledst) +{ + int i; + isp_copy_out_hdr(isp, &lesrc->le_header, &ledst->le_header); + ISP_IOXPUT_32(isp, lesrc->le_reserved, &ledst->le_reserved); + if (ISP_IS_SBUS(isp)) { + ISP_IOXPUT_8(isp, lesrc->le_lun, &ledst->le_rsvd); + ISP_IOXPUT_8(isp, lesrc->le_rsvd, &ledst->le_lun); + ISP_IOXPUT_8(isp, lesrc->le_ops, &ledst->le_tgt); + ISP_IOXPUT_8(isp, lesrc->le_tgt, &ledst->le_ops); + ISP_IOXPUT_8(isp, lesrc->le_status, &ledst->le_reserved2); + ISP_IOXPUT_8(isp, lesrc->le_reserved2, &ledst->le_status); + ISP_IOXPUT_8(isp, lesrc->le_cmd_count, &ledst->le_in_count); + ISP_IOXPUT_8(isp, lesrc->le_in_count, &ledst->le_cmd_count); + ISP_IOXPUT_8(isp, lesrc->le_cdb6len, &ledst->le_cdb7len); + ISP_IOXPUT_8(isp, lesrc->le_cdb7len, &ledst->le_cdb6len); + } else { + ISP_IOXPUT_8(isp, lesrc->le_lun, &ledst->le_lun); + ISP_IOXPUT_8(isp, lesrc->le_rsvd, &ledst->le_rsvd); + ISP_IOXPUT_8(isp, lesrc->le_ops, &ledst->le_ops); + ISP_IOXPUT_8(isp, lesrc->le_tgt, &ledst->le_tgt); + ISP_IOXPUT_8(isp, lesrc->le_status, &ledst->le_status); + ISP_IOXPUT_8(isp, lesrc->le_reserved2, &ledst->le_reserved2); + ISP_IOXPUT_8(isp, lesrc->le_cmd_count, &ledst->le_cmd_count); + ISP_IOXPUT_8(isp, lesrc->le_in_count, &ledst->le_in_count); + ISP_IOXPUT_8(isp, lesrc->le_cdb6len, &ledst->le_cdb6len); + ISP_IOXPUT_8(isp, lesrc->le_cdb7len, &ledst->le_cdb7len); + } + ISP_IOXPUT_32(isp, lesrc->le_flags, &ledst->le_flags); + ISP_IOXPUT_16(isp, lesrc->le_timeout, &ledst->le_timeout); + for (i = 0; i < 20; i++) { + ISP_IOXPUT_8(isp, lesrc->le_reserved3[i], + &ledst->le_reserved3[i]); + } +} + +static INLINE void +isp_get_enable_lun(struct ispsoftc *isp, lun_entry_t *lesrc, lun_entry_t *ledst) +{ + int i; + isp_copy_in_hdr(isp, &lesrc->le_header, &ledst->le_header); + ISP_IOXGET_32(isp, &lesrc->le_reserved, ledst->le_reserved); + if (ISP_IS_SBUS(isp)) { + ISP_IOXGET_8(isp, &lesrc->le_lun, ledst->le_rsvd); + ISP_IOXGET_8(isp, &lesrc->le_rsvd, ledst->le_lun); + ISP_IOXGET_8(isp, &lesrc->le_ops, ledst->le_tgt); + ISP_IOXGET_8(isp, &lesrc->le_tgt, ledst->le_ops); + ISP_IOXGET_8(isp, &lesrc->le_status, ledst->le_reserved2); + ISP_IOXGET_8(isp, &lesrc->le_reserved2, ledst->le_status); + ISP_IOXGET_8(isp, &lesrc->le_cmd_count, ledst->le_in_count); + ISP_IOXGET_8(isp, &lesrc->le_in_count, ledst->le_cmd_count); + ISP_IOXGET_8(isp, &lesrc->le_cdb6len, ledst->le_cdb7len); + ISP_IOXGET_8(isp, &lesrc->le_cdb7len, ledst->le_cdb6len); + } else { + ISP_IOXGET_8(isp, &lesrc->le_lun, ledst->le_lun); + ISP_IOXGET_8(isp, &lesrc->le_rsvd, ledst->le_rsvd); + ISP_IOXGET_8(isp, &lesrc->le_ops, ledst->le_ops); + ISP_IOXGET_8(isp, &lesrc->le_tgt, ledst->le_tgt); + ISP_IOXGET_8(isp, &lesrc->le_status, ledst->le_status); + ISP_IOXGET_8(isp, &lesrc->le_reserved2, ledst->le_reserved2); + ISP_IOXGET_8(isp, &lesrc->le_cmd_count, ledst->le_cmd_count); + ISP_IOXGET_8(isp, &lesrc->le_in_count, ledst->le_in_count); + ISP_IOXGET_8(isp, &lesrc->le_cdb6len, ledst->le_cdb6len); + ISP_IOXGET_8(isp, &lesrc->le_cdb7len, ledst->le_cdb7len); + } + ISP_IOXGET_32(isp, &lesrc->le_flags, ledst->le_flags); + ISP_IOXGET_16(isp, &lesrc->le_timeout, ledst->le_timeout); + for (i = 0; i < 20; i++) { + ISP_IOXGET_8(isp, &lesrc->le_reserved3[i], + ledst->le_reserved3[i]); + } +} + +static INLINE void +isp_put_notify(struct ispsoftc *isp, in_entry_t *insrc, in_entry_t *indst) +{ + int i; + isp_copy_out_hdr(isp, &insrc->in_header, &indst->in_header); + ISP_IOXPUT_32(isp, insrc->in_reserved, &indst->in_reserved); + if (ISP_IS_SBUS(isp)) { + ISP_IOXPUT_8(isp, insrc->in_lun, &indst->in_iid); + ISP_IOXPUT_8(isp, insrc->in_iid, &indst->in_lun); + ISP_IOXPUT_8(isp, insrc->in_reserved2, &indst->in_tgt); + ISP_IOXPUT_8(isp, insrc->in_tgt, &indst->in_reserved2); + ISP_IOXPUT_8(isp, insrc->in_status, &indst->in_rsvd2); + ISP_IOXPUT_8(isp, insrc->in_rsvd2, &indst->in_status); + ISP_IOXPUT_8(isp, insrc->in_tag_val, &indst->in_tag_type); + ISP_IOXPUT_8(isp, insrc->in_tag_type, &indst->in_tag_val); + } else { + ISP_IOXPUT_8(isp, insrc->in_lun, &indst->in_lun); + ISP_IOXPUT_8(isp, insrc->in_iid, &indst->in_iid); + ISP_IOXPUT_8(isp, insrc->in_reserved2, &indst->in_reserved2); + ISP_IOXPUT_8(isp, insrc->in_tgt, &indst->in_tgt); + ISP_IOXPUT_8(isp, insrc->in_status, &indst->in_status); + ISP_IOXPUT_8(isp, insrc->in_rsvd2, &indst->in_rsvd2); + ISP_IOXPUT_8(isp, insrc->in_tag_val, &indst->in_tag_val); + ISP_IOXPUT_8(isp, insrc->in_tag_type, &indst->in_tag_type); + } + ISP_IOXPUT_32(isp, insrc->in_flags, &indst->in_flags); + ISP_IOXPUT_16(isp, insrc->in_seqid, &indst->in_seqid); + for (i = 0; i < IN_MSGLEN; i++) { + ISP_IOXPUT_8(isp, insrc->in_msg[i], &indst->in_msg[i]); + } + for (i = 0; i < IN_RSVDLEN; i++) { + ISP_IOXPUT_8(isp, insrc->in_reserved3[i], + &indst->in_reserved3[i]); + } + for (i = 0; i < QLTM_SENSELEN; i++) { + ISP_IOXPUT_8(isp, insrc->in_sense[i], + &indst->in_sense[i]); + } +} + +static INLINE void +isp_get_notify(struct ispsoftc *isp, in_entry_t *insrc, in_entry_t *indst) +{ + int i; + isp_copy_in_hdr(isp, &insrc->in_header, &indst->in_header); + ISP_IOXGET_32(isp, &insrc->in_reserved, indst->in_reserved); + if (ISP_IS_SBUS(isp)) { + ISP_IOXGET_8(isp, &insrc->in_lun, indst->in_iid); + ISP_IOXGET_8(isp, &insrc->in_iid, indst->in_lun); + ISP_IOXGET_8(isp, &insrc->in_reserved2, indst->in_tgt); + ISP_IOXGET_8(isp, &insrc->in_tgt, indst->in_reserved2); + ISP_IOXGET_8(isp, &insrc->in_status, indst->in_rsvd2); + ISP_IOXGET_8(isp, &insrc->in_rsvd2, indst->in_status); + ISP_IOXGET_8(isp, &insrc->in_tag_val, indst->in_tag_type); + ISP_IOXGET_8(isp, &insrc->in_tag_type, indst->in_tag_val); + } else { + ISP_IOXGET_8(isp, &insrc->in_lun, indst->in_lun); + ISP_IOXGET_8(isp, &insrc->in_iid, indst->in_iid); + ISP_IOXGET_8(isp, &insrc->in_reserved2, indst->in_reserved2); + ISP_IOXGET_8(isp, &insrc->in_tgt, indst->in_tgt); + ISP_IOXGET_8(isp, &insrc->in_status, indst->in_status); + ISP_IOXGET_8(isp, &insrc->in_rsvd2, indst->in_rsvd2); + ISP_IOXGET_8(isp, &insrc->in_tag_val, indst->in_tag_val); + ISP_IOXGET_8(isp, &insrc->in_tag_type, indst->in_tag_type); + } + ISP_IOXGET_32(isp, &insrc->in_flags, indst->in_flags); + ISP_IOXGET_16(isp, &insrc->in_seqid, indst->in_seqid); + for (i = 0; i < IN_MSGLEN; i++) { + ISP_IOXGET_8(isp, &insrc->in_msg[i], indst->in_msg[i]); + } + for (i = 0; i < IN_RSVDLEN; i++) { + ISP_IOXGET_8(isp, &insrc->in_reserved3[i], + indst->in_reserved3[i]); + } + for (i = 0; i < QLTM_SENSELEN; i++) { + ISP_IOXGET_8(isp, &insrc->in_sense[i], + indst->in_sense[i]); + } +} + +static INLINE void +isp_put_notify_fc(struct ispsoftc *isp, in_fcentry_t *insrc, + in_fcentry_t *indst) +{ + isp_copy_out_hdr(isp, &insrc->in_header, &indst->in_header); + ISP_IOXPUT_32(isp, insrc->in_reserved, &indst->in_reserved); + ISP_IOXPUT_8(isp, insrc->in_lun, &indst->in_lun); + ISP_IOXPUT_8(isp, insrc->in_iid, &indst->in_iid); + ISP_IOXPUT_16(isp, insrc->in_scclun, &indst->in_scclun); + ISP_IOXPUT_32(isp, insrc->in_reserved2, &indst->in_reserved2); + ISP_IOXPUT_16(isp, insrc->in_status, &indst->in_status); + ISP_IOXPUT_16(isp, insrc->in_task_flags, &indst->in_task_flags); + ISP_IOXPUT_16(isp, insrc->in_seqid, &indst->in_seqid); +} + +static INLINE void +isp_get_notify_fc(struct ispsoftc *isp, in_fcentry_t *insrc, + in_fcentry_t *indst) +{ + isp_copy_in_hdr(isp, &insrc->in_header, &indst->in_header); + ISP_IOXGET_32(isp, &insrc->in_reserved, indst->in_reserved); + ISP_IOXGET_8(isp, &insrc->in_lun, indst->in_lun); + ISP_IOXGET_8(isp, &insrc->in_iid, indst->in_iid); + ISP_IOXGET_16(isp, &insrc->in_scclun, indst->in_scclun); + ISP_IOXGET_32(isp, &insrc->in_reserved2, indst->in_reserved2); + ISP_IOXGET_16(isp, &insrc->in_status, indst->in_status); + ISP_IOXGET_16(isp, &insrc->in_task_flags, indst->in_task_flags); + ISP_IOXGET_16(isp, &insrc->in_seqid, indst->in_seqid); +} + +static INLINE void +isp_put_notify_ack(struct ispsoftc *isp, na_entry_t *nasrc, na_entry_t *nadst) +{ + int i; + isp_copy_out_hdr(isp, &nasrc->na_header, &nadst->na_header); + ISP_IOXPUT_32(isp, nasrc->na_reserved, &nadst->na_reserved); + if (ISP_IS_SBUS(isp)) { + ISP_IOXPUT_8(isp, nasrc->na_lun, &nadst->na_iid); + ISP_IOXPUT_8(isp, nasrc->na_iid, &nadst->na_lun); + ISP_IOXPUT_8(isp, nasrc->na_status, &nadst->na_event); + ISP_IOXPUT_8(isp, nasrc->na_event, &nadst->na_status); + } else { + ISP_IOXPUT_8(isp, nasrc->na_lun, &nadst->na_lun); + ISP_IOXPUT_8(isp, nasrc->na_iid, &nadst->na_iid); + ISP_IOXPUT_8(isp, nasrc->na_status, &nadst->na_status); + ISP_IOXPUT_8(isp, nasrc->na_event, &nadst->na_event); + } + ISP_IOXPUT_32(isp, nasrc->na_flags, &nadst->na_flags); + for (i = 0; i < NA_RSVDLEN; i++) { + ISP_IOXPUT_16(isp, nasrc->na_reserved3[i], + &nadst->na_reserved3[i]); + } +} + +static INLINE void +isp_get_notify_ack(struct ispsoftc *isp, na_entry_t *nasrc, na_entry_t *nadst) +{ + int i; + isp_copy_in_hdr(isp, &nasrc->na_header, &nadst->na_header); + ISP_IOXGET_32(isp, &nasrc->na_reserved, nadst->na_reserved); + if (ISP_IS_SBUS(isp)) { + ISP_IOXGET_8(isp, &nasrc->na_lun, nadst->na_iid); + ISP_IOXGET_8(isp, &nasrc->na_iid, nadst->na_lun); + ISP_IOXGET_8(isp, &nasrc->na_status, nadst->na_event); + ISP_IOXGET_8(isp, &nasrc->na_event, nadst->na_status); + } else { + ISP_IOXGET_8(isp, &nasrc->na_lun, nadst->na_lun); + ISP_IOXGET_8(isp, &nasrc->na_iid, nadst->na_iid); + ISP_IOXGET_8(isp, &nasrc->na_status, nadst->na_status); + ISP_IOXGET_8(isp, &nasrc->na_event, nadst->na_event); + } + ISP_IOXGET_32(isp, &nasrc->na_flags, nadst->na_flags); + for (i = 0; i < NA_RSVDLEN; i++) { + ISP_IOXGET_16(isp, &nasrc->na_reserved3[i], + nadst->na_reserved3[i]); + } +} + +static INLINE void +isp_put_notify_ack_fc(struct ispsoftc *isp, na_fcentry_t *nasrc, + na_fcentry_t *nadst) +{ + int i; + isp_copy_out_hdr(isp, &nasrc->na_header, &nadst->na_header); + ISP_IOXPUT_32(isp, nasrc->na_reserved, &nadst->na_reserved); + ISP_IOXPUT_8(isp, nasrc->na_lun, &nadst->na_lun); + ISP_IOXPUT_8(isp, nasrc->na_iid, &nadst->na_iid); + ISP_IOXPUT_16(isp, nasrc->na_scclun, &nadst->na_scclun); + ISP_IOXPUT_16(isp, nasrc->na_flags, &nadst->na_flags); + ISP_IOXPUT_16(isp, nasrc->na_reserved2, &nadst->na_reserved2); + ISP_IOXPUT_16(isp, nasrc->na_status, &nadst->na_status); + ISP_IOXPUT_16(isp, nasrc->na_task_flags, &nadst->na_task_flags); + ISP_IOXPUT_16(isp, nasrc->na_seqid, &nadst->na_seqid); + for (i = 0; i < NA2_RSVDLEN; i++) { + ISP_IOXPUT_16(isp, nasrc->na_reserved3[i], + &nadst->na_reserved3[i]); + } +} + +static INLINE void +isp_get_notify_ack_fc(struct ispsoftc *isp, na_fcentry_t *nasrc, + na_fcentry_t *nadst) +{ + int i; + isp_copy_in_hdr(isp, &nasrc->na_header, &nadst->na_header); + ISP_IOXGET_32(isp, &nasrc->na_reserved, nadst->na_reserved); + ISP_IOXGET_8(isp, &nasrc->na_lun, nadst->na_lun); + ISP_IOXGET_8(isp, &nasrc->na_iid, nadst->na_iid); + ISP_IOXGET_16(isp, &nasrc->na_scclun, nadst->na_scclun); + ISP_IOXGET_16(isp, &nasrc->na_flags, nadst->na_flags); + ISP_IOXGET_16(isp, &nasrc->na_reserved2, nadst->na_reserved2); + ISP_IOXGET_16(isp, &nasrc->na_status, nadst->na_status); + ISP_IOXGET_16(isp, &nasrc->na_task_flags, nadst->na_task_flags); + ISP_IOXGET_16(isp, &nasrc->na_seqid, nadst->na_seqid); + for (i = 0; i < NA2_RSVDLEN; i++) { + ISP_IOXGET_16(isp, &nasrc->na_reserved3[i], + nadst->na_reserved3[i]); + } +} +#endif +#endif /* _ISP_INLINE_H */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/common/ispmbox.h 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,933 @@ +/* + * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters. + * + * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#ifndef _ISPMBOX_H +#define _ISPMBOX_H + +/* + * Mailbox Command Opcodes + */ +#define MBOX_NO_OP 0x0000 +#define MBOX_LOAD_RAM 0x0001 +#define MBOX_EXEC_FIRMWARE 0x0002 +#define MBOX_DUMP_RAM 0x0003 +#define MBOX_WRITE_RAM_WORD 0x0004 +#define MBOX_READ_RAM_WORD 0x0005 +#define MBOX_MAILBOX_REG_TEST 0x0006 +#define MBOX_VERIFY_CHECKSUM 0x0007 +#define MBOX_ABOUT_FIRMWARE 0x0008 + /* 9 */ + /* a */ + /* b */ + /* c */ + /* d */ +#define MBOX_CHECK_FIRMWARE 0x000e +#define MBOX_READ_RAM_WORD_EXTENDED 0x000f +#define MBOX_INIT_REQ_QUEUE 0x0010 +#define MBOX_INIT_RES_QUEUE 0x0011 +#define MBOX_EXECUTE_IOCB 0x0012 +#define MBOX_WAKE_UP 0x0013 +#define MBOX_STOP_FIRMWARE 0x0014 +#define MBOX_ABORT 0x0015 +#define MBOX_ABORT_DEVICE 0x0016 +#define MBOX_ABORT_TARGET 0x0017 +#define MBOX_BUS_RESET 0x0018 +#define MBOX_STOP_QUEUE 0x0019 +#define MBOX_START_QUEUE 0x001a +#define MBOX_SINGLE_STEP_QUEUE 0x001b +#define MBOX_ABORT_QUEUE 0x001c +#define MBOX_GET_DEV_QUEUE_STATUS 0x001d + /* 1e */ +#define MBOX_GET_FIRMWARE_STATUS 0x001f +#define MBOX_GET_INIT_SCSI_ID 0x0020 +#define MBOX_GET_SELECT_TIMEOUT 0x0021 +#define MBOX_GET_RETRY_COUNT 0x0022 +#define MBOX_GET_TAG_AGE_LIMIT 0x0023 +#define MBOX_GET_CLOCK_RATE 0x0024 +#define MBOX_GET_ACT_NEG_STATE 0x0025 +#define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 +#define MBOX_GET_SBUS_PARAMS 0x0027 +#define MBOX_GET_PCI_PARAMS MBOX_GET_SBUS_PARAMS +#define MBOX_GET_TARGET_PARAMS 0x0028 +#define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 +#define MBOX_GET_RESET_DELAY_PARAMS 0x002a + /* 2b */ + /* 2c */ + /* 2d */ + /* 2e */ + /* 2f */ +#define MBOX_SET_INIT_SCSI_ID 0x0030 +#define MBOX_SET_SELECT_TIMEOUT 0x0031 +#define MBOX_SET_RETRY_COUNT 0x0032 +#define MBOX_SET_TAG_AGE_LIMIT 0x0033 +#define MBOX_SET_CLOCK_RATE 0x0034 +#define MBOX_SET_ACT_NEG_STATE 0x0035 +#define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 +#define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 +#define MBOX_SET_PCI_PARAMETERS 0x0037 +#define MBOX_SET_TARGET_PARAMS 0x0038 +#define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 +#define MBOX_SET_RESET_DELAY_PARAMS 0x003a + /* 3b */ + /* 3c */ + /* 3d */ + /* 3e */ + /* 3f */ +#define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 +#define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 +#define MBOX_EXEC_BIOS_IOCB 0x0042 +#define MBOX_SET_FW_FEATURES 0x004a +#define MBOX_GET_FW_FEATURES 0x004b +#define FW_FEATURE_FAST_POST 0x1 +#define FW_FEATURE_LVD_NOTIFY 0x2 +#define FW_FEATURE_RIO_32BIT 0x4 +#define FW_FEATURE_RIO_16BIT 0x8 + +#define MBOX_INIT_REQ_QUEUE_A64 0x0052 +#define MBOX_INIT_RES_QUEUE_A64 0x0053 + +#define MBOX_ENABLE_TARGET_MODE 0x0055 +#define ENABLE_TARGET_FLAG 0x8000 +#define ENABLE_TQING_FLAG 0x0004 +#define ENABLE_MANDATORY_DISC 0x0002 +#define MBOX_GET_TARGET_STATUS 0x0056 + +/* These are for the ISP2X00 FC cards */ +#define MBOX_GET_LOOP_ID 0x0020 +#define MBOX_GET_FIRMWARE_OPTIONS 0x0028 +#define MBOX_SET_FIRMWARE_OPTIONS 0x0038 +#define MBOX_GET_RESOURCE_COUNT 0x0042 +#define MBOX_ENHANCED_GET_PDB 0x0047 +#define MBOX_EXEC_COMMAND_IOCB_A64 0x0054 +#define MBOX_INIT_FIRMWARE 0x0060 +#define MBOX_GET_INIT_CONTROL_BLOCK 0x0061 +#define MBOX_INIT_LIP 0x0062 +#define MBOX_GET_FC_AL_POSITION_MAP 0x0063 +#define MBOX_GET_PORT_DB 0x0064 +#define MBOX_CLEAR_ACA 0x0065 +#define MBOX_TARGET_RESET 0x0066 +#define MBOX_CLEAR_TASK_SET 0x0067 +#define MBOX_ABORT_TASK_SET 0x0068 +#define MBOX_GET_FW_STATE 0x0069 +#define MBOX_GET_PORT_NAME 0x006A +#define MBOX_GET_LINK_STATUS 0x006B +#define MBOX_INIT_LIP_RESET 0x006C +#define MBOX_SEND_SNS 0x006E +#define MBOX_FABRIC_LOGIN 0x006F +#define MBOX_SEND_CHANGE_REQUEST 0x0070 +#define MBOX_FABRIC_LOGOUT 0x0071 +#define MBOX_INIT_LIP_LOGIN 0x0072 + +#define MBOX_DRIVER_HEARTBEAT 0x005B +#define MBOX_FW_HEARTBEAT 0x005C + +#define MBOX_GET_SET_DATA_RATE 0x005D /* 23XX only */ +#define MBGSD_GET_RATE 0 +#define MBGSD_SET_RATE 1 +#define MBGSD_ONEGB 0 +#define MBGSD_TWOGB 1 +#define MBGSD_AUTO 2 + + +#define ISP2100_SET_PCI_PARAM 0x00ff + +#define MBOX_BUSY 0x04 + +typedef struct { + u_int16_t param[8]; +} mbreg_t; + +/* + * Mailbox Command Complete Status Codes + */ +#define MBOX_COMMAND_COMPLETE 0x4000 +#define MBOX_INVALID_COMMAND 0x4001 +#define MBOX_HOST_INTERFACE_ERROR 0x4002 +#define MBOX_TEST_FAILED 0x4003 +#define MBOX_COMMAND_ERROR 0x4005 +#define MBOX_COMMAND_PARAM_ERROR 0x4006 +#define MBOX_PORT_ID_USED 0x4007 +#define MBOX_LOOP_ID_USED 0x4008 +#define MBOX_ALL_IDS_USED 0x4009 +#define MBOX_NOT_LOGGED_IN 0x400A +#define MBLOGALL 0x000f +#define MBLOGNONE 0x0000 +#define MBLOGMASK(x) ((x) & 0xf) + +/* + * Asynchronous event status codes + */ +#define ASYNC_BUS_RESET 0x8001 +#define ASYNC_SYSTEM_ERROR 0x8002 +#define ASYNC_RQS_XFER_ERR 0x8003 +#define ASYNC_RSP_XFER_ERR 0x8004 +#define ASYNC_QWAKEUP 0x8005 +#define ASYNC_TIMEOUT_RESET 0x8006 +#define ASYNC_DEVICE_RESET 0x8007 +#define ASYNC_EXTMSG_UNDERRUN 0x800A +#define ASYNC_SCAM_INT 0x800B +#define ASYNC_HUNG_SCSI 0x800C +#define ASYNC_KILLED_BUS 0x800D +#define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ +#define ASYNC_LIP_OCCURRED 0x8010 +#define ASYNC_LOOP_UP 0x8011 +#define ASYNC_LOOP_DOWN 0x8012 +#define ASYNC_LOOP_RESET 0x8013 +#define ASYNC_PDB_CHANGED 0x8014 +#define ASYNC_CHANGE_NOTIFY 0x8015 +#define ASYNC_LIP_F8 0x8016 +#define ASYNC_CMD_CMPLT 0x8020 +#define ASYNC_CTIO_DONE 0x8021 +#define ASYNC_IP_XMIT_DONE 0x8022 +#define ASYNC_IP_RECV_DONE 0x8023 +#define ASYNC_IP_BROADCAST 0x8024 +#define ASYNC_IP_RCVQ_LOW 0x8025 +#define ASYNC_IP_RCVQ_EMPTY 0x8026 +#define ASYNC_IP_RECV_DONE_ALIGNED 0x8027 +#define ASYNC_PTPMODE 0x8030 +#define ASYNC_RIO1 0x8031 +#define ASYNC_RIO2 0x8032 +#define ASYNC_RIO3 0x8033 +#define ASYNC_RIO4 0x8034 +#define ASYNC_RIO5 0x8035 +#define ASYNC_CONNMODE 0x8036 +#define ISP_CONN_LOOP 1 +#define ISP_CONN_PTP 2 +#define ISP_CONN_BADLIP 3 +#define ISP_CONN_FATAL 4 +#define ISP_CONN_LOOPBACK 5 +#define ASYNC_RIO_RESP 0x8040 +#define ASYNC_RIO_COMP 0x8042 +/* + * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options + * mailbox command to enable this. + */ +#define ASYNC_QFULL_SENT 0x8049 + +/* + * Mailbox Usages + */ + +#define WRITE_REQUEST_QUEUE_IN_POINTER(isp, value) \ + ISP_WRITE(isp, isp->isp_rqstinrp, value) + +#define READ_REQUEST_QUEUE_OUT_POINTER(isp) \ + ISP_READ(isp, isp->isp_rqstoutrp) + +#define READ_RESPONSE_QUEUE_IN_POINTER(isp) \ + ISP_READ(isp, isp->isp_respinrp) + +#define WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, value) \ + ISP_WRITE(isp, isp->isp_respoutrp, value) + +/* + * Command Structure Definitions + */ + +typedef struct { + u_int32_t ds_base; + u_int32_t ds_count; +} ispds_t; + +typedef struct { + u_int32_t ds_base; + u_int32_t ds_basehi; + u_int32_t ds_count; +} ispds64_t; + +#define DSTYPE_32BIT 0 +#define DSTYPE_64BIT 1 +typedef struct { + u_int16_t ds_type; /* 0-> ispds_t, 1-> ispds64_t */ + u_int32_t ds_segment; /* unused */ + u_int32_t ds_base; /* 32 bit address of DSD list */ +} ispdslist_t; + + +/* + * These elements get swizzled around for SBus instances. + */ +#define ISP_SWAP8(a, b) { \ + u_int8_t tmp; \ + tmp = a; \ + a = b; \ + b = tmp; \ +} +typedef struct { + u_int8_t rqs_entry_type; + u_int8_t rqs_entry_count; + u_int8_t rqs_seqno; + u_int8_t rqs_flags; +} isphdr_t; + +/* RQS Flag definitions */ +#define RQSFLAG_CONTINUATION 0x01 +#define RQSFLAG_FULL 0x02 +#define RQSFLAG_BADHEADER 0x04 +#define RQSFLAG_BADPACKET 0x08 + +/* RQS entry_type definitions */ +#define RQSTYPE_REQUEST 0x01 +#define RQSTYPE_DATASEG 0x02 +#define RQSTYPE_RESPONSE 0x03 +#define RQSTYPE_MARKER 0x04 +#define RQSTYPE_CMDONLY 0x05 +#define RQSTYPE_ATIO 0x06 /* Target Mode */ +#define RQSTYPE_CTIO 0x07 /* Target Mode */ +#define RQSTYPE_SCAM 0x08 +#define RQSTYPE_A64 0x09 +#define RQSTYPE_A64_CONT 0x0a +#define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */ +#define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */ +#define RQSTYPE_NOTIFY 0x0d /* Target Mode */ +#define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ +#define RQSTYPE_CTIO1 0x0f /* Target Mode */ +#define RQSTYPE_STATUS_CONT 0x10 +#define RQSTYPE_T2RQS 0x11 +#define RQSTYPE_IP_XMIT 0x13 +#define RQSTYPE_T4RQS 0x15 +#define RQSTYPE_ATIO2 0x16 /* Target Mode */ +#define RQSTYPE_CTIO2 0x17 /* Target Mode */ +#define RQSTYPE_CSET0 0x18 +#define RQSTYPE_T3RQS 0x19 +#define RQSTYPE_IP_XMIT_64 0x1b +#define RQSTYPE_CTIO4 0x1e /* Target Mode */ +#define RQSTYPE_CTIO3 0x1f /* Target Mode */ +#define RQSTYPE_RIO1 0x21 +#define RQSTYPE_RIO2 0x22 +#define RQSTYPE_IP_RECV 0x23 +#define RQSTYPE_IP_RECV_CONT 0x24 + + +#define ISP_RQDSEG 4 +typedef struct { + isphdr_t req_header; + u_int32_t req_handle; + u_int8_t req_lun_trn; + u_int8_t req_target; + u_int16_t req_cdblen; +#define req_modifier req_cdblen /* marker packet */ + u_int16_t req_flags; + u_int16_t req_reserved; + u_int16_t req_time; + u_int16_t req_seg_count; + u_int8_t req_cdb[12]; + ispds_t req_dataseg[ISP_RQDSEG]; +} ispreq_t; + +#define ispreq64_t ispreqt3_t /* same as.... */ +#define ISP_RQDSEG_A64 2 + +/* + * A request packet can also be a marker packet. + */ +#define SYNC_DEVICE 0 +#define SYNC_TARGET 1 +#define SYNC_ALL 2 + +#define ISP_RQDSEG_T2 3 +typedef struct { + isphdr_t req_header; + u_int32_t req_handle; + u_int8_t req_lun_trn; + u_int8_t req_target; + u_int16_t req_scclun; + u_int16_t req_flags; + u_int16_t _res2; + u_int16_t req_time; + u_int16_t req_seg_count; + u_int8_t req_cdb[16]; + u_int32_t req_totalcnt; + ispds_t req_dataseg[ISP_RQDSEG_T2]; +} ispreqt2_t; + +#define ISP_RQDSEG_T3 2 +typedef struct { + isphdr_t req_header; + u_int32_t req_handle; + u_int8_t req_lun_trn; + u_int8_t req_target; + u_int16_t req_scclun; + u_int16_t req_flags; + u_int16_t _res2; + u_int16_t req_time; + u_int16_t req_seg_count; + u_int8_t req_cdb[16]; + u_int32_t req_totalcnt; + ispds64_t req_dataseg[ISP_RQDSEG_T3]; +} ispreqt3_t; + +/* req_flag values */ +#define REQFLAG_NODISCON 0x0001 +#define REQFLAG_HTAG 0x0002 +#define REQFLAG_OTAG 0x0004 +#define REQFLAG_STAG 0x0008 +#define REQFLAG_TARGET_RTN 0x0010 + +#define REQFLAG_NODATA 0x0000 +#define REQFLAG_DATA_IN 0x0020 +#define REQFLAG_DATA_OUT 0x0040 +#define REQFLAG_DATA_UNKNOWN 0x0060 + +#define REQFLAG_DISARQ 0x0100 +#define REQFLAG_FRC_ASYNC 0x0200 +#define REQFLAG_FRC_SYNC 0x0400 +#define REQFLAG_FRC_WIDE 0x0800 +#define REQFLAG_NOPARITY 0x1000 +#define REQFLAG_STOPQ 0x2000 +#define REQFLAG_XTRASNS 0x4000 +#define REQFLAG_PRIORITY 0x8000 + +typedef struct { + isphdr_t req_header; + u_int32_t req_handle; + u_int8_t req_lun_trn; + u_int8_t req_target; + u_int16_t req_cdblen; + u_int16_t req_flags; + u_int16_t _res1; + u_int16_t req_time; + u_int16_t req_seg_count; + u_int8_t req_cdb[44]; +} ispextreq_t; + +#define ISP_CDSEG 7 +typedef struct { + isphdr_t req_header; + u_int32_t _res1; + ispds_t req_dataseg[ISP_CDSEG]; +} ispcontreq_t; + +#define ISP_CDSEG64 5 +typedef struct { + isphdr_t req_header; + ispds64_t req_dataseg[ISP_CDSEG64]; +} ispcontreq64_t; + +typedef struct { + isphdr_t req_header; + u_int32_t req_handle; + u_int16_t req_scsi_status; + u_int16_t req_completion_status; + u_int16_t req_state_flags; + u_int16_t req_status_flags; + u_int16_t req_time; +#define req_response_len req_time /* FC only */ + u_int16_t req_sense_len; + u_int32_t req_resid; + u_int8_t req_response[8]; /* FC only */ + u_int8_t req_sense_data[32]; +} ispstatusreq_t; + +typedef struct { + isphdr_t req_header; + u_int8_t req_sense_data[60]; +} ispstatus_cont_t; + +/* + * For Qlogic 2X00, the high order byte of SCSI status has + * additional meaning. + */ +#define RQCS_RU 0x800 /* Residual Under */ +#define RQCS_RO 0x400 /* Residual Over */ +#define RQCS_RESID (RQCS_RU|RQCS_RO) +#define RQCS_SV 0x200 /* Sense Length Valid */ +#define RQCS_RV 0x100 /* FCP Response Length Valid */ + +/* + * Completion Status Codes. + */ +#define RQCS_COMPLETE 0x0000 +#define RQCS_DMA_ERROR 0x0002 +#define RQCS_RESET_OCCURRED 0x0004 +#define RQCS_ABORTED 0x0005 +#define RQCS_TIMEOUT 0x0006 +#define RQCS_DATA_OVERRUN 0x0007 +#define RQCS_DATA_UNDERRUN 0x0015 +#define RQCS_QUEUE_FULL 0x001C + +/* 1X00 Only Completion Codes */ +#define RQCS_INCOMPLETE 0x0001 +#define RQCS_TRANSPORT_ERROR 0x0003 +#define RQCS_COMMAND_OVERRUN 0x0008 +#define RQCS_STATUS_OVERRUN 0x0009 +#define RQCS_BAD_MESSAGE 0x000a +#define RQCS_NO_MESSAGE_OUT 0x000b +#define RQCS_EXT_ID_FAILED 0x000c +#define RQCS_IDE_MSG_FAILED 0x000d +#define RQCS_ABORT_MSG_FAILED 0x000e +#define RQCS_REJECT_MSG_FAILED 0x000f +#define RQCS_NOP_MSG_FAILED 0x0010 +#define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 +#define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 +#define RQCS_ID_MSG_FAILED 0x0013 +#define RQCS_UNEXP_BUS_FREE 0x0014 +#define RQCS_XACT_ERR1 0x0018 +#define RQCS_XACT_ERR2 0x0019 +#define RQCS_XACT_ERR3 0x001A +#define RQCS_BAD_ENTRY 0x001B +#define RQCS_PHASE_SKIPPED 0x001D +#define RQCS_ARQS_FAILED 0x001E +#define RQCS_WIDE_FAILED 0x001F +#define RQCS_SYNCXFER_FAILED 0x0020 +#define RQCS_LVD_BUSERR 0x0021 + +/* 2X00 Only Completion Codes */ +#define RQCS_PORT_UNAVAILABLE 0x0028 +#define RQCS_PORT_LOGGED_OUT 0x0029 +#define RQCS_PORT_CHANGED 0x002A +#define RQCS_PORT_BUSY 0x002B + +/* + * 1X00 specific State Flags + */ +#define RQSF_GOT_BUS 0x0100 +#define RQSF_GOT_TARGET 0x0200 +#define RQSF_SENT_CDB 0x0400 +#define RQSF_XFRD_DATA 0x0800 +#define RQSF_GOT_STATUS 0x1000 +#define RQSF_GOT_SENSE 0x2000 +#define RQSF_XFER_COMPLETE 0x4000 + +/* + * 2X00 specific State Flags + * (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available) + */ +#define RQSF_DATA_IN 0x0020 +#define RQSF_DATA_OUT 0x0040 +#define RQSF_STAG 0x0008 +#define RQSF_OTAG 0x0004 +#define RQSF_HTAG 0x0002 +/* + * 1X00 Status Flags + */ +#define RQSTF_DISCONNECT 0x0001 +#define RQSTF_SYNCHRONOUS 0x0002 +#define RQSTF_PARITY_ERROR 0x0004 +#define RQSTF_BUS_RESET 0x0008 +#define RQSTF_DEVICE_RESET 0x0010 +#define RQSTF_ABORTED 0x0020 +#define RQSTF_TIMEOUT 0x0040 +#define RQSTF_NEGOTIATION 0x0080 + +/* + * 2X00 specific state flags + */ +/* RQSF_SENT_CDB */ +/* RQSF_XFRD_DATA */ +/* RQSF_GOT_STATUS */ +/* RQSF_XFER_COMPLETE */ + +/* + * 2X00 specific status flags + */ +/* RQSTF_ABORTED */ +/* RQSTF_TIMEOUT */ +#define RQSTF_DMA_ERROR 0x0080 +#define RQSTF_LOGOUT 0x2000 + +/* + * Miscellaneous + */ +#ifndef ISP_EXEC_THROTTLE +#define ISP_EXEC_THROTTLE 16 +#endif + +/* + * About Firmware returns an 'attribute' word in mailbox 6. + */ +#define ISP_FW_ATTR_TMODE 0x01 +#define ISP_FW_ATTR_SCCLUN 0x02 +#define ISP_FW_ATTR_FABRIC 0x04 +#define ISP_FW_ATTR_CLASS2 0x08 +#define ISP_FW_ATTR_FCTAPE 0x10 +#define ISP_FW_ATTR_IP 0x20 + +/* + * Reduced Interrupt Operation Response Queue Entreis + */ + +typedef struct { + isphdr_t req_header; + u_int32_t req_handles[15]; +} isp_rio1_t; + +typedef struct { + isphdr_t req_header; + u_int16_t req_handles[30]; +} isp_rio2_t; + +/* + * FC (ISP2100) specific data structures + */ + +/* + * Initialization Control Block + * + * Version One (prime) format. + */ +typedef struct isp_icb { + u_int8_t icb_version; + u_int8_t _reserved0; + u_int16_t icb_fwoptions; + u_int16_t icb_maxfrmlen; + u_int16_t icb_maxalloc; + u_int16_t icb_execthrottle; + u_int8_t icb_retry_count; + u_int8_t icb_retry_delay; + u_int8_t icb_portname[8]; + u_int16_t icb_hardaddr; + u_int8_t icb_iqdevtype; + u_int8_t icb_logintime; + u_int8_t icb_nodename[8]; + u_int16_t icb_rqstout; + u_int16_t icb_rspnsin; + u_int16_t icb_rqstqlen; + u_int16_t icb_rsltqlen; + u_int16_t icb_rqstaddr[4]; + u_int16_t icb_respaddr[4]; + u_int16_t icb_lunenables; + u_int8_t icb_ccnt; + u_int8_t icb_icnt; + u_int16_t icb_lunetimeout; + u_int16_t _reserved1; + u_int16_t icb_xfwoptions; + u_int8_t icb_racctimer; + u_int8_t icb_idelaytimer; + u_int16_t icb_zfwoptions; + u_int16_t _reserved2[13]; +} isp_icb_t; +#define ICB_VERSION1 1 + +#define ICBOPT_HARD_ADDRESS 0x0001 +#define ICBOPT_FAIRNESS 0x0002 +#define ICBOPT_FULL_DUPLEX 0x0004 +#define ICBOPT_FAST_POST 0x0008 +#define ICBOPT_TGT_ENABLE 0x0010 +#define ICBOPT_INI_DISABLE 0x0020 +#define ICBOPT_INI_ADISC 0x0040 +#define ICBOPT_INI_TGTTYPE 0x0080 +#define ICBOPT_PDBCHANGE_AE 0x0100 +#define ICBOPT_NOLIP 0x0200 +#define ICBOPT_SRCHDOWN 0x0400 +#define ICBOPT_PREVLOOP 0x0800 +#define ICBOPT_STOP_ON_QFULL 0x1000 +#define ICBOPT_FULL_LOGIN 0x2000 +#define ICBOPT_BOTH_WWNS 0x4000 +#define ICBOPT_EXTENDED 0x8000 + +#define ICBXOPT_CLASS2_ACK0 0x0200 +#define ICBXOPT_CLASS2 0x0100 +#define ICBXOPT_LOOP_ONLY (0 << 4) +#define ICBXOPT_PTP_ONLY (1 << 4) +#define ICBXOPT_LOOP_2_PTP (2 << 4) +#define ICBXOPT_PTP_2_LOOP (3 << 4) + +#define ICBXOPT_RIO_OFF 0 +#define ICBXOPT_RIO_16BIT 1 +#define ICBXOPT_RIO_32BIT 2 +#define ICBXOPT_RIO_16BIT_IOCB 3 +#define ICBXOPT_RIO_32BIT_IOCB 4 +#define ICBXOPT_ZIO 5 + +#define ICBZOPT_ENA_RDXFR_RDY 0x01 +#define ICBZOPT_ENA_OOF (1 << 6) /* out of order frame handling */ +/* These 3 only apply to the 2300 */ +#define ICBZOPT_RATE_ONEGB (MBGSD_ONEGB << 14) +#define ICBZOPT_RATE_TWOGB (MBGSD_TWOGB << 14) +#define ICBZOPT_RATE_AUTO (MBGSD_AUTO << 14) + + +#define ICB_MIN_FRMLEN 256 +#define ICB_MAX_FRMLEN 2112 +#define ICB_DFLT_FRMLEN 1024 +#define ICB_DFLT_ALLOC 256 +#define ICB_DFLT_THROTTLE 16 +#define ICB_DFLT_RDELAY 5 +#define ICB_DFLT_RCOUNT 3 + + +#define RQRSP_ADDR0015 0 +#define RQRSP_ADDR1631 1 +#define RQRSP_ADDR3247 2 +#define RQRSP_ADDR4863 3 + + +#define ICB_NNM0 7 +#define ICB_NNM1 6 +#define ICB_NNM2 5 +#define ICB_NNM3 4 +#define ICB_NNM4 3 +#define ICB_NNM5 2 +#define ICB_NNM6 1 +#define ICB_NNM7 0 + +#define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ + array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \ + array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \ + array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \ + array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \ + array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \ + array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \ + array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \ + array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff) + +/* + * FC-AL Position Map + * + * This is an at most 128 byte map that returns either + * the LILP or Firmware generated list of ports. + * + * We deviate a bit from the returned qlogic format to + * use an extra bit to say whether this was a LILP or + * f/w generated map. + */ +typedef struct { + u_int8_t fwmap : 1, + count : 7; + u_int8_t map[127]; +} fcpos_map_t; + +/* + * Port Data Base Element + */ + +typedef struct { + u_int16_t pdb_options; + u_int8_t pdb_mstate; + u_int8_t pdb_sstate; +#define BITS2WORD(x) ((x)[0] << 16 | (x)[3] << 8 | (x)[2]) + u_int8_t pdb_hardaddr_bits[4]; + u_int8_t pdb_portid_bits[4]; + u_int8_t pdb_nodename[8]; + u_int8_t pdb_portname[8]; + u_int16_t pdb_execthrottle; + u_int16_t pdb_exec_count; + u_int8_t pdb_retry_count; + u_int8_t pdb_retry_delay; + u_int16_t pdb_resalloc; + u_int16_t pdb_curalloc; + u_int16_t pdb_qhead; + u_int16_t pdb_qtail; + u_int16_t pdb_tl_next; + u_int16_t pdb_tl_last; + u_int16_t pdb_features; /* PLOGI, Common Service */ + u_int16_t pdb_pconcurrnt; /* PLOGI, Common Service */ + u_int16_t pdb_roi; /* PLOGI, Common Service */ + u_int8_t pdb_target; + u_int8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */ + u_int16_t pdb_rdsiz; /* PLOGI, Class 3 */ + u_int16_t pdb_ncseq; /* PLOGI, Class 3 */ + u_int16_t pdb_noseq; /* PLOGI, Class 3 */ + u_int16_t pdb_labrtflg; + u_int16_t pdb_lstopflg; + u_int16_t pdb_sqhead; + u_int16_t pdb_sqtail; + u_int16_t pdb_ptimer; + u_int16_t pdb_nxt_seqid; + u_int16_t pdb_fcount; + u_int16_t pdb_prli_len; + u_int16_t pdb_prli_svc0; + u_int16_t pdb_prli_svc3; + u_int16_t pdb_loopid; + u_int16_t pdb_il_ptr; + u_int16_t pdb_sl_ptr; +} isp_pdb_t; + +#define PDB_OPTIONS_XMITTING (1<<11) +#define PDB_OPTIONS_LNKXMIT (1<<10) +#define PDB_OPTIONS_ABORTED (1<<9) +#define PDB_OPTIONS_ADISC (1<<1) + +#define PDB_STATE_DISCOVERY 0 +#define PDB_STATE_WDISC_ACK 1 +#define PDB_STATE_PLOGI 2 +#define PDB_STATE_PLOGI_ACK 3 +#define PDB_STATE_PRLI 4 +#define PDB_STATE_PRLI_ACK 5 +#define PDB_STATE_LOGGED_IN 6 +#define PDB_STATE_PORT_UNAVAIL 7 +#define PDB_STATE_PRLO 8 +#define PDB_STATE_PRLO_ACK 9 +#define PDB_STATE_PLOGO 10 +#define PDB_STATE_PLOG_ACK 11 + +#define SVC3_TGT_ROLE 0x10 +#define SVC3_INI_ROLE 0x20 +#define SVC3_ROLE_MASK 0x30 +#define SVC3_ROLE_SHIFT 4 + +/* + * CT definition + * + * This is as the QLogic f/w documentations defines it- which is just opposite, + * bit wise, from what the specification defines it as. Additionally, the + * ct_response and ct_resid (really from FC-GS-2) need to be byte swapped. + */ + +typedef struct { + u_int8_t ct_revision; + u_int8_t ct_portid[3]; + u_int8_t ct_fcs_type; + u_int8_t ct_fcs_subtype; + u_int8_t ct_options; + u_int8_t ct_res0; + u_int16_t ct_response; + u_int16_t ct_resid; + u_int8_t ct_res1; + u_int8_t ct_reason; + u_int8_t ct_explanation; + u_int8_t ct_vunique; +} ct_hdr_t; +#define FS_ACC 0x8002 +#define FS_RJT 0x8001 + +#define FC4_IP 5 /* ISO/EEC 8802-2 LLC/SNAP "Out of Order Delivery" */ +#define FC4_SCSI 8 /* SCSI-3 via Fivre Channel Protocol (FCP) */ +#define FC4_FC_SVC 0x20 /* Fibre Channel Services */ + +#define SNS_GA_NXT 0x100 +#define SNS_GPN_ID 0x112 +#define SNS_GNN_ID 0x113 +#define SNS_GFF_ID 0x11F +#define SNS_GID_FT 0x171 +#define SNS_RFT_ID 0x217 +typedef struct { + u_int16_t snscb_rblen; /* response buffer length (words) */ + u_int16_t snscb_res0; + u_int16_t snscb_addr[4]; /* response buffer address */ + u_int16_t snscb_sblen; /* subcommand buffer length (words) */ + u_int16_t snscb_res1; + u_int16_t snscb_data[1]; /* variable data */ +} sns_screq_t; /* Subcommand Request Structure */ + +typedef struct { + u_int16_t snscb_rblen; /* response buffer length (words) */ + u_int16_t snscb_res0; + u_int16_t snscb_addr[4]; /* response buffer address */ + u_int16_t snscb_sblen; /* subcommand buffer length (words) */ + u_int16_t snscb_res1; + u_int16_t snscb_cmd; + u_int16_t snscb_res2; + u_int32_t snscb_res3; + u_int32_t snscb_port; +} sns_ga_nxt_req_t; +#define SNS_GA_NXT_REQ_SIZE (sizeof (sns_ga_nxt_req_t)) + +typedef struct { + u_int16_t snscb_rblen; /* response buffer length (words) */ + u_int16_t snscb_res0; + u_int16_t snscb_addr[4]; /* response buffer address */ + u_int16_t snscb_sblen; /* subcommand buffer length (words) */ + u_int16_t snscb_res1; + u_int16_t snscb_cmd; + u_int16_t snscb_res2; + u_int32_t snscb_res3; + u_int32_t snscb_portid; +} sns_gxn_id_req_t; +#define SNS_GXN_ID_REQ_SIZE (sizeof (sns_gxn_id_req_t)) + +typedef struct { + u_int16_t snscb_rblen; /* response buffer length (words) */ + u_int16_t snscb_res0; + u_int16_t snscb_addr[4]; /* response buffer address */ + u_int16_t snscb_sblen; /* subcommand buffer length (words) */ + u_int16_t snscb_res1; + u_int16_t snscb_cmd; + u_int16_t snscb_mword_div_2; + u_int32_t snscb_res3; + u_int32_t snscb_fc4_type; +} sns_gid_ft_req_t; +#define SNS_GID_FT_REQ_SIZE (sizeof (sns_gid_ft_req_t)) + +typedef struct { + u_int16_t snscb_rblen; /* response buffer length (words) */ + u_int16_t snscb_res0; + u_int16_t snscb_addr[4]; /* response buffer address */ + u_int16_t snscb_sblen; /* subcommand buffer length (words) */ + u_int16_t snscb_res1; + u_int16_t snscb_cmd; + u_int16_t snscb_res2; + u_int32_t snscb_res3; + u_int32_t snscb_port; + u_int32_t snscb_fc4_types[8]; +} sns_rft_id_req_t; +#define SNS_RFT_ID_REQ_SIZE (sizeof (sns_rft_id_req_t)) + +typedef struct { + ct_hdr_t snscb_cthdr; + u_int8_t snscb_port_type; + u_int8_t snscb_port_id[3]; + u_int8_t snscb_portname[8]; + u_int16_t snscb_data[1]; /* variable data */ +} sns_scrsp_t; /* Subcommand Response Structure */ + +typedef struct { + ct_hdr_t snscb_cthdr; + u_int8_t snscb_port_type; + u_int8_t snscb_port_id[3]; + u_int8_t snscb_portname[8]; + u_int8_t snscb_pnlen; /* symbolic port name length */ + u_int8_t snscb_pname[255]; /* symbolic port name */ + u_int8_t snscb_nodename[8]; + u_int8_t snscb_nnlen; /* symbolic node name length */ + u_int8_t snscb_nname[255]; /* symbolic node name */ + u_int8_t snscb_ipassoc[8]; + u_int8_t snscb_ipaddr[16]; + u_int8_t snscb_svc_class[4]; + u_int8_t snscb_fc4_types[32]; + u_int8_t snscb_fpname[8]; + u_int8_t snscb_reserved; + u_int8_t snscb_hardaddr[3]; +} sns_ga_nxt_rsp_t; /* Subcommand Response Structure */ +#define SNS_GA_NXT_RESP_SIZE (sizeof (sns_ga_nxt_rsp_t)) + +typedef struct { + ct_hdr_t snscb_cthdr; + u_int8_t snscb_wwn[8]; +} sns_gxn_id_rsp_t; +#define SNS_GXN_ID_RESP_SIZE (sizeof (sns_gxn_id_rsp_t)) + +typedef struct { + ct_hdr_t snscb_cthdr; + u_int32_t snscb_fc4_features[32]; +} sns_gff_id_rsp_t; +#define SNS_GFF_ID_RESP_SIZE (sizeof (sns_gff_id_rsp_t)) + +typedef struct { + ct_hdr_t snscb_cthdr; + struct { + u_int8_t control; + u_int8_t portid[3]; + } snscb_ports[1]; +} sns_gid_ft_rsp_t; +#define SNS_GID_FT_RESP_SIZE(x) ((sizeof (sns_gid_ft_rsp_t)) + ((x - 1) << 2)) + +#define SNS_RFT_ID_RESP_SIZE (sizeof (ct_hdr_t)) + +#endif /* _ISPMBOX_H */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/common/ispreg.h 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,1010 @@ +/* + * Machine Independent (well, as best as possible) register + * definitions for Qlogic ISP SCSI adapters. + * + * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#ifndef _ISPREG_H +#define _ISPREG_H + +/* + * Hardware definitions for the Qlogic ISP registers. + */ + +/* + * This defines types of access to various registers. + * + * R: Read Only + * W: Write Only + * RW: Read/Write + * + * R*, W*, RW*: Read Only, Write Only, Read/Write, but only + * if RISC processor in ISP is paused. + */ + +/* + * Offsets for various register blocks. + * + * Sad but true, different architectures have different offsets. + * + * Don't be alarmed if none of this makes sense. The original register + * layout set some defines in a certain pattern. Everything else has been + * grafted on since. For example, the ISP1080 manual will state that DMA + * registers start at 0x80 from the base of the register address space. + * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080 + * to start at offset 0x60 because the DMA registers are all defined to + * be DMA_BLOCK+0x20 and so on. Clear? + */ + +#define BIU_REGS_OFF 0x00 + +#define PCI_MBOX_REGS_OFF 0x70 +#define PCI_MBOX_REGS2100_OFF 0x10 +#define PCI_MBOX_REGS2300_OFF 0x40 +#define SBUS_MBOX_REGS_OFF 0x80 + +#define PCI_SXP_REGS_OFF 0x80 +#define SBUS_SXP_REGS_OFF 0x200 + +#define PCI_RISC_REGS_OFF 0x80 +#define SBUS_RISC_REGS_OFF 0x400 + +/* Bless me! Chip designers have putzed it again! */ +#define ISP1080_DMA_REGS_OFF 0x60 +#define DMA_REGS_OFF 0x00 /* same as BIU block */ + +#define SBUS_REGSIZE 0x450 +#define PCI_REGSIZE 0x100 + +/* + * NB: The *_BLOCK definitions have no specific hardware meaning. + * They serve simply to note to the MD layer which block of + * registers offsets are being accessed. + */ +#define _NREG_BLKS 5 +#define _BLK_REG_SHFT 13 +#define _BLK_REG_MASK (7 << _BLK_REG_SHFT) +#define BIU_BLOCK (0 << _BLK_REG_SHFT) +#define MBOX_BLOCK (1 << _BLK_REG_SHFT) +#define SXP_BLOCK (2 << _BLK_REG_SHFT) +#define RISC_BLOCK (3 << _BLK_REG_SHFT) +#define DMA_BLOCK (4 << _BLK_REG_SHFT) + +/* + * Bus Interface Block Register Offsets + */ + +#define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */ +#define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0) +#define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */ +#define BIU2100_FLASH_DATA (BIU_BLOCK+0x2) +#define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */ +#define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */ +#define BIU2100_CSR (BIU_BLOCK+0x6) +#define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */ +#define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */ +#define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */ +#define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */ +/* + * These are specific to the 2300. + * + * They *claim* you can read BIU_R2HSTSLO with a full 32 bit access + * and get both registers, but I'm a bit dubious about that. But the + * point here is that the top 16 bits are firmware defined bits that + * the RISC processor uses to inform the host about something- usually + * something which was nominally in a mailbox register. + */ +#define BIU_REQINP (BIU_BLOCK+0x10) /* Request Queue In */ +#define BIU_REQOUTP (BIU_BLOCK+0x12) /* Request Queue Out */ +#define BIU_RSPINP (BIU_BLOCK+0x14) /* Response Queue In */ +#define BIU_RSPOUTP (BIU_BLOCK+0x16) /* Response Queue Out */ + +#define BIU_R2HSTSLO (BIU_BLOCK+0x18) +#define BIU_R2HSTSHI (BIU_BLOCK+0x1A) + +#define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */ +#define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */ +#define BIU_R2HST_ISTAT_MASK 0x3f /* intr information && status */ +#define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */ +#define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */ +#define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */ +#define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ +#define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */ +#define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ +#define ISPR2HST_RQST_UPDATE 0x14 /* Resquest Queue Update */ +#define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */ +#define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */ +#define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */ + +#define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */ +#define RDMA2100_CONTROL DFIFO_COMMAND +#define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */ + +/* + * Putzed DMA register layouts. + */ +#define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */ +#define CDMA2100_CONTROL CDMA_CONF +#define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */ +#define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */ +#define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */ +#define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */ +#define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */ +#define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */ +#define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */ +#define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */ + +#define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */ +#define TDMA2100_CONTROL DDMA_CONF +#define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */ +#define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */ +#define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */ +#define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */ +#define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */ +#define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */ +#define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */ +/* these are for the 1040A cards */ +#define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */ +#define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */ + + +/* + * Bus Interface Block Register Definitions + */ +/* BUS CONFIGURATION REGISTER #0 */ +#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */ +/* BUS CONFIGURATION REGISTER #1 */ + +#define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */ +#define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */ + +#define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */ +#define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */ +#define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */ +#define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */ +#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */ +#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */ +#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */ +#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */ +#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */ +#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */ +#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */ + +#define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */ +#define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */ +#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */ + +/* ISP2100 Bus Control/Status Register */ + +#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */ +#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */ +#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */ +#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */ +#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */ +#define BIU2100_PCI64 0x04 /* R: 64 Bit PCI slot */ +#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */ +#define BIU2100_SOFT_RESET 0x01 +/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */ + + +/* BUS CONTROL REGISTER */ +#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */ +#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */ +#define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */ +#define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */ +#define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */ +#define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */ + +#define BIU2100_ICR_ENABLE_ALL_INTS 0x8000 +#define BIU2100_ICR_ENA_FPM_INT 0x0020 +#define BIU2100_ICR_ENA_FB_INT 0x0010 +#define BIU2100_ICR_ENA_RISC_INT 0x0008 +#define BIU2100_ICR_ENA_CDMA_INT 0x0004 +#define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002 +#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001 +#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000 + +#define ENABLE_INTS(isp) (IS_SCSI(isp))? \ + ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ + ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) + +#define INTS_ENABLED(isp) ((IS_SCSI(isp))? \ + (ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\ + (ISP_READ(isp, BIU_ICR) & \ + (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS))) + +#define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0) + +/* BUS STATUS REGISTER */ +#define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */ +#define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */ +#define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */ +#define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */ +#define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */ + +#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */ +#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */ +#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */ +#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */ +#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */ +#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */ +#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */ + +#define INT_PENDING(isp, isr) (IS_FC(isp)? \ + ((isr & BIU2100_ISR_RISC_INT) != 0) : ((isr & BIU_ISR_RISC_INT) != 0)) + +#define INT_PENDING_MASK(isp) \ + (IS_FC(isp)? BIU2100_ISR_RISC_INT: BIU_ISR_RISC_INT) + +/* BUS SEMAPHORE REGISTER */ +#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */ +#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */ + +/* NVRAM SEMAPHORE REGISTER */ +#define BIU_NVRAM_CLOCK 0x0001 +#define BIU_NVRAM_SELECT 0x0002 +#define BIU_NVRAM_DATAOUT 0x0004 +#define BIU_NVRAM_DATAIN 0x0008 +#define ISP_NVRAM_READ 6 + +/* COMNMAND && DATA DMA CONFIGURATION REGISTER */ +#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */ +#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */ +#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */ +#define DMA_DMA_DIRECTION 0x0001 /* + * Set DMA direction: + * 0 - DMA FIFO to host + * 1 - Host to DMA FIFO + */ + +/* COMMAND && DATA DMA CONTROL REGISTER */ +#define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */ +#define DMA_CNTRL_CLEAR_CHAN 0x0008 /* + * Clear FIFO and DMA Channel, + * reset DMA registers + */ +#define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */ +#define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */ +#define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */ + +/* + * Variants of same for 2100 + */ +#define DMA_CNTRL2100_CLEAR_CHAN 0x0004 +#define DMA_CNTRL2100_RESET_INT 0x0002 + + + +/* DMA STATUS REGISTER */ +#define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */ +#define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */ +#define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */ +#define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */ +#define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */ +#define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */ + +#define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */ +#define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */ +#define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */ +#define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */ +#define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */ +#define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */ +#define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */ +#define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */ +#define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */ +#define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */ +#define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */ + +/* DMA Status Register, pipeline status bits */ +#define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */ +#define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */ +#define DMA_SBUS_PIPE_STAGE1 0x0040 /* + * Pipeline stage 1 Loaded, + * stage 2 empty + */ +#define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */ +#define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */ +#define DMA_PCI_PIPE_STAGE1 0x0001 /* + * Pipeline stage 1 Loaded, + * stage 2 empty + */ +#define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */ + +/* DMA Status Register, channel status bits */ +#define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */ +#define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */ +#define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */ +#define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */ +#define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */ +#define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */ +#define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */ + + +/* DMA FIFO STATUS REGISTER */ +#define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */ +#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */ +#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */ +#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */ + +/* + * Mailbox Block Register Offsets + */ + +#define INMAILBOX0 (MBOX_BLOCK+0x0) +#define INMAILBOX1 (MBOX_BLOCK+0x2) +#define INMAILBOX2 (MBOX_BLOCK+0x4) +#define INMAILBOX3 (MBOX_BLOCK+0x6) +#define INMAILBOX4 (MBOX_BLOCK+0x8) +#define INMAILBOX5 (MBOX_BLOCK+0xA) +#define INMAILBOX6 (MBOX_BLOCK+0xC) +#define INMAILBOX7 (MBOX_BLOCK+0xE) + +#define OUTMAILBOX0 (MBOX_BLOCK+0x0) +#define OUTMAILBOX1 (MBOX_BLOCK+0x2) +#define OUTMAILBOX2 (MBOX_BLOCK+0x4) +#define OUTMAILBOX3 (MBOX_BLOCK+0x6) +#define OUTMAILBOX4 (MBOX_BLOCK+0x8) +#define OUTMAILBOX5 (MBOX_BLOCK+0xA) +#define OUTMAILBOX6 (MBOX_BLOCK+0xC) +#define OUTMAILBOX7 (MBOX_BLOCK+0xE) + +#define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) +#define NMBOX(isp) \ + (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ + ((isp)->isp_type & ISP_HA_FC))? 8 : 6) +#define NMBOX_BMASK(isp) \ + (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \ + ((isp)->isp_type & ISP_HA_FC))? 0xff : 0x3f) + +#define MAX_MAILBOX 8 + +/* + * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00). + * NB: The RISC processor must be paused and the appropriate register + * bank selected via BIU2100_CSR bits. + */ + +#define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96) +#define FPM_SOFT_RESET 0x0100 + +#define FBM_CMD (BIU_BLOCK + 0xB8) +#define FBMCMD_FIFO_RESET_ALL 0xA000 + + +/* + * SXP Block Register Offsets + */ +#define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ +#define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ +#define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ +#define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ +#define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ +#define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ +#define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ +#define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ +#define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ +#define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ +#define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ +#define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ +#define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ +#define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ +#define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ +#define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ +#define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ +#define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ +#define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ +#define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ +#define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ +#define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ +#define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ +#define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ +#define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ +#define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ +#define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ +#define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ +#define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ +#define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ +#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */ +#define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ +#define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ +#define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ +#define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ +#define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ +#define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ +#define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ +#define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ + +/* for 1080/1280/1240 only */ +#define SXP_BANK1_SELECT 0x100 + + +/* SXP CONF1 REGISTER */ +#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ +#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ +#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ +#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ +#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ + +/* SXP CONF2 REGISTER */ +#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ +#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ +#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ +#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ +#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ +#define SXP_CONF2_SELECT 0x0001 /* Enable selection */ + +/* SXP INTERRUPT REGISTER */ +#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ +#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ +#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ +#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ +#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ +#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ +#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ +#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ +#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ +#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ + + +/* SXP GROSS ERROR REGISTER */ +#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ +#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ +#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ +#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ +#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ +#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ +#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ + +/* SXP EXCEPTION REGISTER */ +#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ +#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ +#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ +#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ +#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ +#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ +#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ +#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ +#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ +#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ + + /* SXP OVERRIDE REGISTER */ +#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ +#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ +#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ +#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ +#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ +#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ +#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ +#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ +#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ +#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ +#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ +#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ +#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ + +/* SXP COMMANDS */ +#define SXP_RESET_BUS_CMD 0x300b + +/* SXP SCSI ID REGISTER */ +#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ +#define SXP_SELECT_ID 0x000F /* Select id */ + +/* SXP DEV CONFIG1 REGISTER */ +#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ +#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ +#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ + + +/* SXP DEV CONFIG2 REGISTER */ +#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ +#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ +#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ +#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ +#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ + + +/* SXP PHASE POINTER REGISTER */ +#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ +#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ +#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ +#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ + + +/* SXP FIFO STATUS REGISTER */ +#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ +#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ +#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ +#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ + + +/* SXP CONTROL PINS REGISTER */ +#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ +#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ +#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ +#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ +#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ +#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ +#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ +#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ +#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ +#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ +#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ +#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ + +/* + * Set the hold time for the SCSI Bus Reset to be 250 ms + */ +#define SXP_SCSI_BUS_RESET_HOLD_TIME 250 + +/* SXP DIFF PINS REGISTER */ +#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ +#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ +#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ +#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ +#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ +#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ + +/* Ultra2 only */ +#define SXP_PINS_LVD_MODE 0x1000 +#define SXP_PINS_HVD_MODE 0x0800 +#define SXP_PINS_SE_MODE 0x0400 + +/* The above have to be put together with the DIFFM pin to make sense */ +#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) +#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) +#define ISP1080_SE_MODE (SXP_PINS_SE_MODE) +#define ISP1080_MODE_MASK \ + (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE|SXP_PINS_DIFF_MODE) + +/* + * RISC and Host Command and Control Block Register Offsets + */ + +#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ +#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ +#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ +#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ +#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ +#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ +#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ +#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ +#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ +#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ +#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ +#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ +#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ +#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ +#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ +#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ +#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ +#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ +#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ +#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ +#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ +#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ +#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ +#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ +#define RISC_MTR2100 RISC_BLOCK+0x30 + +#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ +#define DUAL_BANK 8 +#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ +#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ +#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ +#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ +#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ +#define TCR RISC_BLOCK+0x46 /* W : Test Control */ +#define TMR RISC_BLOCK+0x48 /* W : Test Mode */ + + +/* PROCESSOR STATUS REGISTER */ +#define RISC_PSR_FORCE_TRUE 0x8000 +#define RISC_PSR_LOOP_COUNT_DONE 0x4000 +#define RISC_PSR_RISC_INT 0x2000 +#define RISC_PSR_TIMER_ROLLOVER 0x1000 +#define RISC_PSR_ALU_OVERFLOW 0x0800 +#define RISC_PSR_ALU_MSB 0x0400 +#define RISC_PSR_ALU_CARRY 0x0200 +#define RISC_PSR_ALU_ZERO 0x0100 + +#define RISC_PSR_PCI_ULTRA 0x0080 +#define RISC_PSR_SBUS_ULTRA 0x0020 + +#define RISC_PSR_DMA_INT 0x0010 +#define RISC_PSR_SXP_INT 0x0008 +#define RISC_PSR_HOST_INT 0x0004 +#define RISC_PSR_INT_PENDING 0x0002 +#define RISC_PSR_FORCE_FALSE 0x0001 + + +/* Host Command and Control */ +#define HCCR_CMD_NOP 0x0000 /* NOP */ +#define HCCR_CMD_RESET 0x1000 /* Reset RISC */ +#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ +#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ +#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ +#define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /* + * Disable RISC pause on FPM + * parity error. + */ +#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ +#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ +#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ +#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ +#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ +#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ +#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ +#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ + +#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 +#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 +#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 +#define ISP2100_HCCR_PARITY 0x0001 + +#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ +#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ +#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ + +#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ +#define HCCR_RESET 0x0040 /* R : reset in progress */ +#define HCCR_PAUSE 0x0020 /* R : RISC paused */ + +#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ + +/* + * NVRAM Definitions (PCI cards only) + */ + +#define ISPBSMX(c, byte, shift, mask) \ + (((c)[(byte)] >> (shift)) & (mask)) +/* + * Qlogic 1020/1040 NVRAM is an array of 128 bytes. + * + * Some portion of the front of this is for general host adapter properties + * This is followed by an array of per-target parameters, and is tailed off + * with a checksum xor byte at offset 127. For non-byte entities data is + * stored in Little Endian order. + */ + +#define ISP_NVRAM_SIZE 128 + +#define ISP_NVRAM_VERSION(c) (c)[4] +#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) +#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) +#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) +#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) +#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] +#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] +#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] +#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) +#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) +#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) +#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) +#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) +#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] +#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) +#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) +#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) +#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) +#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) +#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) +#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) +#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) +#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) +#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) +#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) +#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) +#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) +#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) +#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) +#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) + +#define ISP_NVRAM_TARGOFF 28 +#define ISP_NVARM_TARGSIZE 6 +#define _IxT(tgt, tidx) \ + (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx)) +#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) +#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) +#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) +#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) +#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) +#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) +#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) +#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) +#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) +#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) +#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) +#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) +#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) + +/* + * Qlogic 1080/1240 NVRAM is an array of 256 bytes. + * + * Some portion of the front of this is for general host adapter properties + * This is followed by an array of per-target parameters, and is tailed off + * with a checksum xor byte at offset 256. For non-byte entities data is + * stored in Little Endian order. + */ + +#define ISP1080_NVRAM_SIZE 256 + +#define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) + +/* Offset 5 */ +/* + u_int8_t bios_configuration_mode :2; + u_int8_t bios_disable :1; + u_int8_t selectable_scsi_boot_enable :1; + u_int8_t cd_rom_boot_enable :1; + u_int8_t disable_loading_risc_code :1; + u_int8_t enable_64bit_addressing :1; + u_int8_t unused_7 :1; + */ + +/* Offsets 6, 7 */ +/* + u_int8_t boot_lun_number :5; + u_int8_t scsi_bus_number :1; + u_int8_t unused_6 :1; + u_int8_t unused_7 :1; + u_int8_t boot_target_number :4; + u_int8_t unused_12 :1; + u_int8_t unused_13 :1; + u_int8_t unused_14 :1; + u_int8_t unused_15 :1; + */ + +#define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) + +#define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) +#define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) + +#define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) +#define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) +#define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) + +#define ISP1080_ISP_PARAMETER(c) \ + (((c)[18]) | ((c)[19] << 8)) + +#define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01) +#define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01) + +#define ISP1080_BUS1_OFF 112 + +#define ISP1080_NVRAM_INITIATOR_ID(c, b) \ + ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) +#define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ + (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] +#define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ + (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] +#define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ + (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] + +#define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ + ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) +#define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ + ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) +#define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ + ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) +#define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ + (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ + ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) +#define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ + (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ + ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) + +#define ISP1080_NVRAM_TARGOFF(b) \ + ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) +#define ISP1080_NVRAM_TARGSIZE 6 +#define _IxT8(tgt, tidx, b) \ + (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) + +#define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ + ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) +#define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ + ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) +#define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ + ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) +#define ISP1080_NVRAM_TGT_TQING(c, t, b) \ + ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) +#define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ + ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) +#define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ + ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) +#define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ + ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) +#define ISP1080_NVRAM_TGT_DISC(c, t, b) \ + ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) +#define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ + ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) +#define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ + ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) +#define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ + ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) +#define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ + ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) +#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ + ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) + +#define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE +#define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE +#define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD +#define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT +#define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE +#define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE +#define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER +#define ISP12160_FAST_POST ISP1080_FAST_POST +#define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION + +#define ISP12160_NVRAM_INITIATOR_ID \ + ISP1080_NVRAM_INITIATOR_ID +#define ISP12160_NVRAM_BUS_RESET_DELAY \ + ISP1080_NVRAM_BUS_RESET_DELAY +#define ISP12160_NVRAM_BUS_RETRY_COUNT \ + ISP1080_NVRAM_BUS_RETRY_COUNT +#define ISP12160_NVRAM_BUS_RETRY_DELAY \ + ISP1080_NVRAM_BUS_RETRY_DELAY +#define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \ + ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME +#define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \ + ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION +#define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \ + ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION +#define ISP12160_NVRAM_SELECTION_TIMEOUT \ + ISP1080_NVRAM_SELECTION_TIMEOUT +#define ISP12160_NVRAM_MAX_QUEUE_DEPTH \ + ISP1080_NVRAM_MAX_QUEUE_DEPTH + + +#define ISP12160_BUS0_OFF 24 +#define ISP12160_BUS1_OFF 136 + +#define ISP12160_NVRAM_TARGOFF(b) \ + (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16) + +#define ISP12160_NVRAM_TARGSIZE 6 +#define _IxT16(tgt, tidx, b) \ + (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx)) + +#define ISP12160_NVRAM_TGT_RENEG(c, t, b) \ + ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01) +#define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \ + ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01) +#define ISP12160_NVRAM_TGT_ARQ(c, t, b) \ + ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01) +#define ISP12160_NVRAM_TGT_TQING(c, t, b) \ + ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01) +#define ISP12160_NVRAM_TGT_SYNC(c, t, b) \ + ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01) +#define ISP12160_NVRAM_TGT_WIDE(c, t, b) \ + ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01) +#define ISP12160_NVRAM_TGT_PARITY(c, t, b) \ + ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01) +#define ISP12160_NVRAM_TGT_DISC(c, t, b) \ + ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01) + +#define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ + ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff) +#define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ + ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff) + +#define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ + ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f) +#define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ + ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01) + +#define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \ + ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f) +#define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \ + ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03) +#define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \ + ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) + +/* + * Qlogic 2XXX NVRAM is an array of 256 bytes. + * + * Some portion of the front of this is for general RISC engine parameters, + * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. + * + * This is followed by some general host adapter parameters, and ends with + * a checksum xor byte at offset 255. For non-byte entities data is stored + * in Little Endian order. + */ +#define ISP2100_NVRAM_SIZE 256 +/* ISP_NVRAM_VERSION is in same overall place */ +#define ISP2100_NVRAM_RISCVER(c) (c)[6] +#define ISP2100_NVRAM_OPTIONS(c) (c)[8] +#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) +#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) +#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) +#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] +#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] + +#define ISP2100_NVRAM_PORT_NAME(c) (\ + (((u_int64_t)(c)[18]) << 56) | \ + (((u_int64_t)(c)[19]) << 48) | \ + (((u_int64_t)(c)[20]) << 40) | \ + (((u_int64_t)(c)[21]) << 32) | \ + (((u_int64_t)(c)[22]) << 24) | \ + (((u_int64_t)(c)[23]) << 16) | \ + (((u_int64_t)(c)[24]) << 8) | \ + (((u_int64_t)(c)[25]) << 0)) + +#define ISP2100_NVRAM_HARDLOOPID(c) (c)[26] + +#define ISP2200_NVRAM_NODE_NAME(c) (\ + (((u_int64_t)(c)[30]) << 56) | \ + (((u_int64_t)(c)[31]) << 48) | \ + (((u_int64_t)(c)[32]) << 40) | \ + (((u_int64_t)(c)[33]) << 32) | \ + (((u_int64_t)(c)[34]) << 24) | \ + (((u_int64_t)(c)[35]) << 16) | \ + (((u_int64_t)(c)[36]) << 8) | \ + (((u_int64_t)(c)[37]) << 0)) + +#define ISP2100_NVRAM_HBA_OPTIONS(c) (c)[70] +#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) +#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) +#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) +#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) +#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) +#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) + +#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ + (((u_int64_t)(c)[72]) << 56) | \ + (((u_int64_t)(c)[73]) << 48) | \ + (((u_int64_t)(c)[74]) << 40) | \ + (((u_int64_t)(c)[75]) << 32) | \ + (((u_int64_t)(c)[76]) << 24) | \ + (((u_int64_t)(c)[77]) << 16) | \ + (((u_int64_t)(c)[78]) << 8) | \ + (((u_int64_t)(c)[79]) << 0)) + +#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] + +#define ISP2200_HBA_FEATURES(c) (c)[232] | ((c)[233] << 8) + +/* + * Firmware Crash Dump + * + * QLogic needs specific information format when they look at firmware crashes. + * + * This is incredibly kernel memory consumptive (to say the least), so this + * code is only compiled in when needed. + */ + +#define QLA2200_RISC_IMAGE_DUMP_SIZE \ + (1 * sizeof (u_int16_t)) + /* 'used' flag (also HBA type) */ \ + (352 * sizeof (u_int16_t)) + /* RISC registers */ \ + (61440 * sizeof (u_int16_t)) /* RISC SRAM (offset 0x1000..0xffff) */ +#define QLA2300_RISC_IMAGE_DUMP_SIZE \ + (1 * sizeof (u_int16_t)) + /* 'used' flag (also HBA type) */ \ + (464 * sizeof (u_int16_t)) + /* RISC registers */ \ + (63488 * sizeof (u_int16_t)) + /* RISC SRAM (0x0800..0xffff) */ \ + (4096 * sizeof (u_int16_t)) + /* RISC SRAM (0x10000..0x10FFF) */ \ + (61440 * sizeof (u_int16_t)) /* RISC SRAM (0x11000..0x1FFFF) */ +/* the larger of the two */ +#define ISP_CRASH_IMAGE_SIZE QLA2300_RISC_IMAGE_DUMP_SIZE +#endif /* _ISPREG_H */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/common/isp_target.c 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,1187 @@ +/* + * Machine and OS Independent Target Mode Code for the Qlogic SCSI/FC adapters. + * + * Copyright (c) 1999, 2000, 2001 by Matthew Jacob + * All rights reserved. + * mjacob@feral.com + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Bug fixes gratefully acknowledged from: + * Oded Kedem + */ +/* + * Include header file appropriate for platform we're building on. + */ + +#ifdef __NetBSD__ +#include +#endif +#ifdef __FreeBSD__ +#include +#endif +#ifdef __OpenBSD__ +#include +#endif +#ifdef __linux__ +#include "isp_linux.h" +#endif + +#ifdef ISP_TARGET_MODE +static const char atiocope[] = + "ATIO returned for lun %d because it was in the middle of Bus Device Reset " + "on bus %d"; +static const char atior[] = + "ATIO returned on for lun %d on from IID %d because a Bus Reset occurred " + "on bus %d"; + +static void isp_got_msg(struct ispsoftc *, int, in_entry_t *); +static void isp_got_msg_fc(struct ispsoftc *, int, in_fcentry_t *); +static void isp_notify_ack(struct ispsoftc *, void *); +static void isp_handle_atio(struct ispsoftc *, at_entry_t *); +static void isp_handle_atio2(struct ispsoftc *, at2_entry_t *); +static void isp_handle_ctio(struct ispsoftc *, ct_entry_t *); +static void isp_handle_ctio2(struct ispsoftc *, ct2_entry_t *); + +/* + * The Qlogic driver gets an interrupt to look at response queue entries. + * Some of these are status completions for initiatior mode commands, but + * if target mode is enabled, we get a whole wad of response queue entries + * to be handled here. + * + * Basically the split into 3 main groups: Lun Enable/Modification responses, + * SCSI Command processing, and Immediate Notification events. + * + * You start by writing a request queue entry to enable target mode (and + * establish some resource limitations which you can modify later). + * The f/w responds with a LUN ENABLE or LUN MODIFY response with + * the status of this action. If the enable was successful, you can expect... + * + * Response queue entries with SCSI commands encapsulate show up in an ATIO + * (Accept Target IO) type- sometimes with enough info to stop the command at + * this level. Ultimately the driver has to feed back to the f/w's request + * queue a sequence of CTIOs (continue target I/O) that describe data to + * be moved and/or status to be sent) and finally finishing with sending + * to the f/w's response queue an ATIO which then completes the handshake + * with the f/w for that command. There's a lot of variations on this theme, + * including flags you can set in the CTIO for the Qlogic 2X00 fibre channel + * cards that 'auto-replenish' the f/w's ATIO count, but this is the basic + * gist of it. + * + * The third group that can show up in the response queue are Immediate + * Notification events. These include things like notifications of SCSI bus + * resets, or Bus Device Reset messages or other messages received. This + * a classic oddbins area. It can get a little weird because you then turn + * around and acknowledge the Immediate Notify by writing an entry onto the + * request queue and then the f/w turns around and gives you an acknowledgement + * to *your* acknowledgement on the response queue (the idea being to let + * the f/w tell you when the event is *really* over I guess). + * + */ + + +/* + * A new response queue entry has arrived. The interrupt service code + * has already swizzled it into the platform dependent from canonical form. + * + * Because of the way this driver is designed, unfortunately most of the + * actual synchronization work has to be done in the platform specific + * code- we have no synchroniation primitives in the common code. + */ + +int +isp_target_notify(struct ispsoftc *isp, void *vptr, u_int16_t *optrp) +{ + u_int16_t status, seqid; + union { + at_entry_t *atiop; + at2_entry_t *at2iop; + ct_entry_t *ctiop; + ct2_entry_t *ct2iop; + lun_entry_t *lunenp; + in_entry_t *inotp; + in_fcentry_t *inot_fcp; + na_entry_t *nackp; + na_fcentry_t *nack_fcp; + isphdr_t *hp; + void * *vp; +#define atiop unp.atiop +#define at2iop unp.at2iop +#define ctiop unp.ctiop +#define ct2iop unp.ct2iop +#define lunenp unp.lunenp +#define inotp unp.inotp +#define inot_fcp unp.inot_fcp +#define nackp unp.nackp +#define nack_fcp unp.nack_fcp +#define hdrp unp.hp + } unp; + u_int8_t local[QENTRY_LEN]; + int bus, type, rval = 1; + + type = isp_get_response_type(isp, (isphdr_t *)vptr); + unp.vp = vptr; + + ISP_TDQE(isp, "isp_target_notify", (int) *optrp, vptr); + + switch(type) { + case RQSTYPE_ATIO: + isp_get_atio(isp, atiop, (at_entry_t *) local); + isp_handle_atio(isp, (at_entry_t *) local); + break; + case RQSTYPE_CTIO: + isp_get_ctio(isp, ctiop, (ct_entry_t *) local); + isp_handle_ctio(isp, (ct_entry_t *) local); + break; + case RQSTYPE_ATIO2: + isp_get_atio2(isp, at2iop, (at2_entry_t *) local); + isp_handle_atio2(isp, (at2_entry_t *) local); + break; + case RQSTYPE_CTIO2: + isp_get_ctio2(isp, ct2iop, (ct2_entry_t *) local); + isp_handle_ctio2(isp, (ct2_entry_t *) local); + break; + case RQSTYPE_ENABLE_LUN: + case RQSTYPE_MODIFY_LUN: + isp_get_enable_lun(isp, lunenp, (lun_entry_t *) local); + (void) isp_async(isp, ISPASYNC_TARGET_ACTION, local); + break; + + case RQSTYPE_NOTIFY: + /* + * Either the ISP received a SCSI message it can't + * handle, or it's returning an Immed. Notify entry + * we sent. We can send Immed. Notify entries to + * increment the firmware's resource count for them + * (we set this initially in the Enable Lun entry). + */ + bus = 0; + if (IS_FC(isp)) { + isp_get_notify_fc(isp, inot_fcp, (in_fcentry_t *)local); + inot_fcp = (in_fcentry_t *) local; + status = inot_fcp->in_status; + seqid = inot_fcp->in_seqid; + } else { + isp_get_notify(isp, inotp, (in_entry_t *)local); + inotp = (in_entry_t *) local; + status = inotp->in_status & 0xff; + seqid = inotp->in_seqid; + if (IS_DUALBUS(isp)) { + bus = GET_BUS_VAL(inotp->in_iid); + SET_BUS_VAL(inotp->in_iid, 0); + } + } + isp_prt(isp, ISP_LOGTDEBUG0, + "Immediate Notify On Bus %d, status=0x%x seqid=0x%x", + bus, status, seqid); + + /* + * ACK it right away. + */ + isp_notify_ack(isp, (status == IN_RESET)? NULL : local); + switch (status) { + case IN_RESET: + (void) isp_async(isp, ISPASYNC_BUS_RESET, &bus); + break; + case IN_MSG_RECEIVED: + case IN_IDE_RECEIVED: + if (IS_FC(isp)) { + isp_got_msg_fc(isp, bus, (in_fcentry_t *)local); + } else { + isp_got_msg(isp, bus, (in_entry_t *)local); + } + break; + case IN_RSRC_UNAVAIL: + isp_prt(isp, ISP_LOGWARN, "Firmware out of ATIOs"); + break; + case IN_PORT_LOGOUT: + case IN_ABORT_TASK: + case IN_PORT_CHANGED: + case IN_GLOBAL_LOGO: + (void) isp_async(isp, ISPASYNC_TARGET_ACTION, &local); + break; + default: + isp_prt(isp, ISP_LOGERR, + "bad status (0x%x) in isp_target_notify", status); + break; + } + break; + + case RQSTYPE_NOTIFY_ACK: + /* + * The ISP is acknowledging our acknowledgement of an + * Immediate Notify entry for some asynchronous event. + */ + if (IS_FC(isp)) { + isp_get_notify_ack_fc(isp, nack_fcp, + (na_fcentry_t *)local); + nack_fcp = (na_fcentry_t *)local; + isp_prt(isp, ISP_LOGTDEBUG1, + "Notify Ack status=0x%x seqid 0x%x", + nack_fcp->na_status, nack_fcp->na_seqid); + } else { + isp_get_notify_ack(isp, nackp, (na_entry_t *)local); + nackp = (na_entry_t *)local; + isp_prt(isp, ISP_LOGTDEBUG1, + "Notify Ack event 0x%x status=0x%x seqid 0x%x", + nackp->na_event, nackp->na_status, nackp->na_seqid); + } + break; + default: + isp_prt(isp, ISP_LOGERR, + "Unknown entry type 0x%x in isp_target_notify", type); + rval = 0; + break; + } +#undef atiop +#undef at2iop +#undef ctiop +#undef ct2iop +#undef lunenp +#undef inotp +#undef inot_fcp +#undef nackp +#undef nack_fcp +#undef hdrp + return (rval); +} + + +/* + * Toggle (on/off) target mode for bus/target/lun + * + * The caller has checked for overlap and legality. + * + * Note that not all of bus, target or lun can be paid attention to. + * Note also that this action will not be complete until the f/w writes + * response entry. The caller is responsible for synchronizing this. + */ +int +isp_lun_cmd(struct ispsoftc *isp, int cmd, int bus, int tgt, int lun, + int cmd_cnt, int inot_cnt, u_int32_t opaque) +{ + lun_entry_t el; + u_int16_t nxti, optr; + void *outp; + + + MEMZERO(&el, sizeof (el)); + if (IS_DUALBUS(isp)) { + el.le_rsvd = (bus & 0x1) << 7; + } + el.le_cmd_count = cmd_cnt; + el.le_in_count = inot_cnt; + if (cmd == RQSTYPE_ENABLE_LUN) { + if (IS_SCSI(isp)) { + el.le_flags = LUN_TQAE|LUN_DISAD; + el.le_cdb6len = 12; + el.le_cdb7len = 12; + } + } else if (cmd == -RQSTYPE_ENABLE_LUN) { + cmd = RQSTYPE_ENABLE_LUN; + el.le_cmd_count = 0; + el.le_in_count = 0; + } else if (cmd == -RQSTYPE_MODIFY_LUN) { + cmd = RQSTYPE_MODIFY_LUN; + el.le_ops = LUN_CCDECR | LUN_INDECR; + } else { + el.le_ops = LUN_CCINCR | LUN_ININCR; + } + el.le_header.rqs_entry_type = cmd; + el.le_header.rqs_entry_count = 1; + el.le_reserved = opaque; + if (IS_SCSI(isp)) { + el.le_tgt = tgt; + el.le_lun = lun; + } else if ((FCPARAM(isp)->isp_fwattr & ISP_FW_ATTR_SCCLUN) == 0) { + el.le_lun = lun; + } + el.le_timeout = 2; + + if (isp_getrqentry(isp, &nxti, &optr, &outp)) { + isp_prt(isp, ISP_LOGERR, + "Request Queue Overflow in isp_lun_cmd"); + return (-1); + } + ISP_TDQE(isp, "isp_lun_cmd", (int) optr, &el); + isp_put_enable_lun(isp, &el, outp); + ISP_ADD_REQUEST(isp, nxti); + return (0); +} + + +int +isp_target_put_entry(struct ispsoftc *isp, void *ap) +{ + void *outp; + u_int16_t nxti, optr; + u_int8_t etype = ((isphdr_t *) ap)->rqs_entry_type; + + if (isp_getrqentry(isp, &nxti, &optr, &outp)) { + isp_prt(isp, ISP_LOGWARN, + "Request Queue Overflow in isp_target_put_entry"); + return (-1); + } + switch (etype) { + case RQSTYPE_ATIO: + isp_put_atio(isp, (at_entry_t *) ap, (at_entry_t *) outp); + break; + case RQSTYPE_ATIO2: + isp_put_atio2(isp, (at2_entry_t *) ap, (at2_entry_t *) outp); + break; + case RQSTYPE_CTIO: + isp_put_ctio(isp, (ct_entry_t *) ap, (ct_entry_t *) outp); + break; + case RQSTYPE_CTIO2: + isp_put_ctio2(isp, (ct2_entry_t *) ap, (ct2_entry_t *) outp); + break; + default: + isp_prt(isp, ISP_LOGERR, + "Unknown type 0x%x in isp_put_entry", etype); + return (-1); + } + + ISP_TDQE(isp, "isp_target_put_entry", (int) optr, ap);; + ISP_ADD_REQUEST(isp, nxti); + return (0); +} + +int +isp_target_put_atio(struct ispsoftc *isp, void *arg) +{ + union { + at_entry_t _atio; + at2_entry_t _atio2; + } atun; + + MEMZERO(&atun, sizeof atun); + if (IS_FC(isp)) { + at2_entry_t *aep = arg; + atun._atio2.at_header.rqs_entry_type = RQSTYPE_ATIO2; + atun._atio2.at_header.rqs_entry_count = 1; + if (FCPARAM(isp)->isp_fwattr & ISP_FW_ATTR_SCCLUN) { + atun._atio2.at_scclun = (u_int16_t) aep->at_scclun; + } else { + atun._atio2.at_lun = (u_int8_t) aep->at_lun; + } + atun._atio2.at_iid = aep->at_iid; + atun._atio2.at_rxid = aep->at_rxid; + atun._atio2.at_status = CT_OK; + } else { + at_entry_t *aep = arg; + atun._atio.at_header.rqs_entry_type = RQSTYPE_ATIO; + atun._atio.at_header.rqs_entry_count = 1; + atun._atio.at_handle = aep->at_handle; + atun._atio.at_iid = aep->at_iid; + atun._atio.at_tgt = aep->at_tgt; + atun._atio.at_lun = aep->at_lun; + atun._atio.at_tag_type = aep->at_tag_type; + atun._atio.at_tag_val = aep->at_tag_val; + atun._atio.at_status = (aep->at_flags & AT_TQAE); + atun._atio.at_status |= CT_OK; + } + return (isp_target_put_entry(isp, &atun)); +} + +/* + * Command completion- both for handling cases of no resources or + * no blackhole driver, or other cases where we have to, inline, + * finish the command sanely, or for normal command completion. + * + * The 'completion' code value has the scsi status byte in the low 8 bits. + * If status is a CHECK CONDITION and bit 8 is nonzero, then bits 12..15 have + * the sense key and bits 16..23 have the ASCQ and bits 24..31 have the ASC + * values. + * + * NB: the key, asc, ascq, cannot be used for parallel SCSI as it doesn't + * NB: inline SCSI sense reporting. As such, we lose this information. XXX. + * + * For both parallel && fibre channel, we use the feature that does + * an automatic resource autoreplenish so we don't have then later do + * put of an atio to replenish the f/w's resource count. + */ + +int +isp_endcmd(struct ispsoftc *isp, void *arg, u_int32_t code, u_int16_t hdl) +{ + int sts; + union { + ct_entry_t _ctio; + ct2_entry_t _ctio2; + } un; + + MEMZERO(&un, sizeof un); + sts = code & 0xff; + + if (IS_FC(isp)) { + at2_entry_t *aep = arg; + ct2_entry_t *cto = &un._ctio2; + + cto->ct_header.rqs_entry_type = RQSTYPE_CTIO2; + cto->ct_header.rqs_entry_count = 1; + cto->ct_iid = aep->at_iid; + if ((FCPARAM(isp)->isp_fwattr & ISP_FW_ATTR_SCCLUN) == 0) { + cto->ct_lun = aep->at_lun; + } + cto->ct_rxid = aep->at_rxid; + cto->rsp.m1.ct_scsi_status = sts & 0xff; + cto->ct_flags = CT2_SENDSTATUS | CT2_NO_DATA | CT2_FLAG_MODE1; + if (hdl == 0) { + cto->ct_flags |= CT2_CCINCR; + } + if (aep->at_datalen) { + cto->ct_resid = aep->at_datalen; + cto->rsp.m1.ct_scsi_status |= CT2_DATA_UNDER; + } + if ((sts & 0xff) == SCSI_CHECK && (sts & ECMD_SVALID)) { + cto->rsp.m1.ct_resp[0] = 0xf0; + cto->rsp.m1.ct_resp[2] = (code >> 12) & 0xf; + cto->rsp.m1.ct_resp[7] = 8; + cto->rsp.m1.ct_resp[12] = (code >> 24) & 0xff; + cto->rsp.m1.ct_resp[13] = (code >> 16) & 0xff; + cto->rsp.m1.ct_senselen = 16; + cto->rsp.m1.ct_scsi_status |= CT2_SNSLEN_VALID; + } + cto->ct_syshandle = hdl; + } else { + at_entry_t *aep = arg; + ct_entry_t *cto = &un._ctio; + + cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; + cto->ct_header.rqs_entry_count = 1; + cto->ct_fwhandle = aep->at_handle; + cto->ct_iid = aep->at_iid; + cto->ct_tgt = aep->at_tgt; + cto->ct_lun = aep->at_lun; + cto->ct_tag_type = aep->at_tag_type; + cto->ct_tag_val = aep->at_tag_val; + if (aep->at_flags & AT_TQAE) { + cto->ct_flags |= CT_TQAE; + } + cto->ct_flags = CT_SENDSTATUS | CT_NO_DATA; + if (hdl == 0) { + cto->ct_flags |= CT_CCINCR; + } + cto->ct_scsi_status = sts; + cto->ct_syshandle = hdl; + } + return (isp_target_put_entry(isp, &un)); +} + +int +isp_target_async(struct ispsoftc *isp, int bus, int event) +{ + tmd_event_t evt; + tmd_msg_t msg; + + switch (event) { + /* + * These three we handle here to propagate an effective bus reset + * upstream, but these do not require any immediate notify actions + * so we return when done. + */ + case ASYNC_LIP_F8: + case ASYNC_LIP_OCCURRED: + case ASYNC_LOOP_UP: + case ASYNC_LOOP_DOWN: + case ASYNC_LOOP_RESET: + case ASYNC_PTPMODE: + /* + * These don't require any immediate notify actions. We used + * treat them like SCSI Bus Resets, but that was just plain + * wrong. Let the normal CTIO completion report what occurred. + */ + return (0); + + case ASYNC_BUS_RESET: + case ASYNC_TIMEOUT_RESET: + if (IS_FC(isp)) { + return (0); /* we'll be getting an inotify instead */ + } + evt.ev_bus = bus; + evt.ev_event = event; + (void) isp_async(isp, ISPASYNC_TARGET_EVENT, &evt); + break; + case ASYNC_DEVICE_RESET: + /* + * Bus Device Reset resets a specific target, so + * we pass this as a synthesized message. + */ + MEMZERO(&msg, sizeof msg); + if (IS_FC(isp)) { + msg.nt_iid = FCPARAM(isp)->isp_loopid; + } else { + msg.nt_iid = SDPARAM(isp)->isp_initiator_id; + } + msg.nt_bus = bus; + msg.nt_msg[0] = MSG_BUS_DEV_RESET; + (void) isp_async(isp, ISPASYNC_TARGET_MESSAGE, &msg); + break; + default: + isp_prt(isp, ISP_LOGERR, + "isp_target_async: unknown event 0x%x", event); + break; + } + if (isp->isp_state == ISP_RUNSTATE) + isp_notify_ack(isp, NULL); + return(0); +} + + +/* + * Process a received message. + * The ISP firmware can handle most messages, there are only + * a few that we need to deal with: + * - abort: clean up the current command + * - abort tag and clear queue + */ + +static void +isp_got_msg(struct ispsoftc *isp, int bus, in_entry_t *inp) +{ + u_int8_t status = inp->in_status & ~QLTM_SVALID; + + if (status == IN_IDE_RECEIVED || status == IN_MSG_RECEIVED) { + tmd_msg_t msg; + + MEMZERO(&msg, sizeof (msg)); + msg.nt_bus = bus; + msg.nt_iid = inp->in_iid; + msg.nt_tgt = inp->in_tgt; + msg.nt_lun = inp->in_lun; + msg.nt_tagtype = inp->in_tag_type; + msg.nt_tagval = inp->in_tag_val; + MEMCPY(msg.nt_msg, inp->in_msg, IN_MSGLEN); + (void) isp_async(isp, ISPASYNC_TARGET_MESSAGE, &msg); + } else { + isp_prt(isp, ISP_LOGERR, + "unknown immediate notify status 0x%x", inp->in_status); + } +} + +/* + * Synthesize a message from the task management flags in a FCP_CMND_IU. + */ +static void +isp_got_msg_fc(struct ispsoftc *isp, int bus, in_fcentry_t *inp) +{ + int lun; + static const char f1[] = "%s from iid %d lun %d seq 0x%x"; + static const char f2[] = + "unknown %s 0x%x lun %d iid %d task flags 0x%x seq 0x%x\n"; + + if (FCPARAM(isp)->isp_fwattr & ISP_FW_ATTR_SCCLUN) { + lun = inp->in_scclun; + } else { + lun = inp->in_lun; + } + + if (inp->in_status != IN_MSG_RECEIVED) { + isp_prt(isp, ISP_LOGINFO, f2, "immediate notify status", + inp->in_status, lun, inp->in_iid, + inp->in_task_flags, inp->in_seqid); + } else { + tmd_msg_t msg; + + MEMZERO(&msg, sizeof (msg)); + msg.nt_bus = bus; + msg.nt_iid = inp->in_iid; + msg.nt_tagval = inp->in_seqid; + msg.nt_lun = lun; + + if (inp->in_task_flags & TASK_FLAGS_ABORT_TASK) { + isp_prt(isp, ISP_LOGINFO, f1, "ABORT TASK", + inp->in_iid, lun, inp->in_seqid); + msg.nt_msg[0] = MSG_ABORT_TAG; + } else if (inp->in_task_flags & TASK_FLAGS_CLEAR_TASK_SET) { + isp_prt(isp, ISP_LOGINFO, f1, "CLEAR TASK SET", + inp->in_iid, lun, inp->in_seqid); + msg.nt_msg[0] = MSG_CLEAR_QUEUE; + } else if (inp->in_task_flags & TASK_FLAGS_TARGET_RESET) { + isp_prt(isp, ISP_LOGINFO, f1, "TARGET RESET", + inp->in_iid, lun, inp->in_seqid); + msg.nt_msg[0] = MSG_BUS_DEV_RESET; + } else if (inp->in_task_flags & TASK_FLAGS_CLEAR_ACA) { + isp_prt(isp, ISP_LOGINFO, f1, "CLEAR ACA", + inp->in_iid, lun, inp->in_seqid); + /* ???? */ + msg.nt_msg[0] = MSG_REL_RECOVERY; + } else if (inp->in_task_flags & TASK_FLAGS_TERMINATE_TASK) { + isp_prt(isp, ISP_LOGINFO, f1, "TERMINATE TASK", + inp->in_iid, lun, inp->in_seqid); + msg.nt_msg[0] = MSG_TERM_IO_PROC; + } else { + isp_prt(isp, ISP_LOGWARN, f2, "task flag", + inp->in_status, lun, inp->in_iid, + inp->in_task_flags, inp->in_seqid); + } + if (msg.nt_msg[0]) { + (void) isp_async(isp, ISPASYNC_TARGET_MESSAGE, &msg); + } + } +} + +static void +isp_notify_ack(struct ispsoftc *isp, void *arg) +{ + char storage[QENTRY_LEN]; + u_int16_t nxti, optr; + void *outp; + + if (isp_getrqentry(isp, &nxti, &optr, &outp)) { + isp_prt(isp, ISP_LOGWARN, + "Request Queue Overflow For isp_notify_ack"); + return; + } + + MEMZERO(storage, QENTRY_LEN); + + if (IS_FC(isp)) { + na_fcentry_t *na = (na_fcentry_t *) storage; + if (arg) { + in_fcentry_t *inp = arg; + MEMCPY(storage, arg, sizeof (isphdr_t)); + na->na_iid = inp->in_iid; + if (FCPARAM(isp)->isp_fwattr & ISP_FW_ATTR_SCCLUN) { + na->na_lun = inp->in_scclun; + } else { + na->na_lun = inp->in_lun; + } + na->na_task_flags = inp->in_task_flags; + na->na_seqid = inp->in_seqid; + na->na_flags = NAFC_RCOUNT; + na->na_status = inp->in_status; + if (inp->in_status == IN_RESET) { + na->na_flags |= NAFC_RST_CLRD; + } + } else { + na->na_flags = NAFC_RST_CLRD; + } + na->na_header.rqs_entry_type = RQSTYPE_NOTIFY_ACK; + na->na_header.rqs_entry_count = 1; + isp_put_notify_ack_fc(isp, na, (na_fcentry_t *)outp); + } else { + na_entry_t *na = (na_entry_t *) storage; + if (arg) { + in_entry_t *inp = arg; + MEMCPY(storage, arg, sizeof (isphdr_t)); + na->na_iid = inp->in_iid; + na->na_lun = inp->in_lun; + na->na_tgt = inp->in_tgt; + na->na_seqid = inp->in_seqid; + if (inp->in_status == IN_RESET) { + na->na_event = NA_RST_CLRD; + } + } else { + na->na_event = NA_RST_CLRD; + } + na->na_header.rqs_entry_type = RQSTYPE_NOTIFY_ACK; + na->na_header.rqs_entry_count = 1; + isp_put_notify_ack(isp, na, (na_entry_t *)outp); + } + ISP_TDQE(isp, "isp_notify_ack", (int) optr, storage); + ISP_ADD_REQUEST(isp, nxti); +} + +static void +isp_handle_atio(struct ispsoftc *isp, at_entry_t *aep) +{ + int lun; + lun = aep->at_lun; + /* + * The firmware status (except for the QLTM_SVALID bit) indicates + * why this ATIO was sent to us. + * + * If QLTM_SVALID is set, the firware has recommended Sense Data. + * + * If the DISCONNECTS DISABLED bit is set in the flags field, + * we're still connected on the SCSI bus - i.e. the initiator + * did not set DiscPriv in the identify message. We don't care + * about this so it's ignored. + */ + + switch(aep->at_status & ~QLTM_SVALID) { + case AT_PATH_INVALID: + /* + * ATIO rejected by the firmware due to disabled lun. + */ + isp_prt(isp, ISP_LOGERR, + "rejected ATIO for disabled lun %d", lun); + break; + case AT_NOCAP: + /* + * Requested Capability not available + * We sent an ATIO that overflowed the firmware's + * command resource count. + */ + isp_prt(isp, ISP_LOGERR, + "rejected ATIO for lun %d because of command count" + " overflow", lun); + break; + + case AT_BDR_MSG: + /* + * If we send an ATIO to the firmware to increment + * its command resource count, and the firmware is + * recovering from a Bus Device Reset, it returns + * the ATIO with this status. We set the command + * resource count in the Enable Lun entry and do + * not increment it. Therefore we should never get + * this status here. + */ + isp_prt(isp, ISP_LOGERR, atiocope, lun, + GET_BUS_VAL(aep->at_iid)); + break; + + case AT_CDB: /* Got a CDB */ + case AT_PHASE_ERROR: /* Bus Phase Sequence Error */ + /* + * Punt to platform specific layer. + */ + (void) isp_async(isp, ISPASYNC_TARGET_ACTION, aep); + break; + + case AT_RESET: + /* + * A bus reset came along and blew away this command. Why + * they do this in addition the async event code stuff, + * I dunno. + * + * Ignore it because the async event will clear things + * up for us. + */ + isp_prt(isp, ISP_LOGWARN, atior, lun, + GET_IID_VAL(aep->at_iid), GET_BUS_VAL(aep->at_iid)); + break; + + + default: + isp_prt(isp, ISP_LOGERR, + "Unknown ATIO status 0x%x from initiator %d for lun %d", + aep->at_status, aep->at_iid, lun); + (void) isp_target_put_atio(isp, aep); + break; + } +} + +static void +isp_handle_atio2(struct ispsoftc *isp, at2_entry_t *aep) +{ + int lun; + + if (FCPARAM(isp)->isp_fwattr & ISP_FW_ATTR_SCCLUN) { + lun = aep->at_scclun; + } else { + lun = aep->at_lun; + } + + /* + * The firmware status (except for the QLTM_SVALID bit) indicates + * why this ATIO was sent to us. + * + * If QLTM_SVALID is set, the firware has recommended Sense Data. + * + * If the DISCONNECTS DISABLED bit is set in the flags field, + * we're still connected on the SCSI bus - i.e. the initiator + * did not set DiscPriv in the identify message. We don't care + * about this so it's ignored. + */ + + switch(aep->at_status & ~QLTM_SVALID) { + case AT_PATH_INVALID: + /* + * ATIO rejected by the firmware due to disabled lun. + */ + isp_prt(isp, ISP_LOGERR, + "rejected ATIO2 for disabled lun %d", lun); + break; + case AT_NOCAP: + /* + * Requested Capability not available + * We sent an ATIO that overflowed the firmware's + * command resource count. + */ + isp_prt(isp, ISP_LOGERR, + "rejected ATIO2 for lun %d- command count overflow", lun); + break; + + case AT_BDR_MSG: + /* + * If we send an ATIO to the firmware to increment + * its command resource count, and the firmware is + * recovering from a Bus Device Reset, it returns + * the ATIO with this status. We set the command + * resource count in the Enable Lun entry and no + * not increment it. Therefore we should never get + * this status here. + */ + isp_prt(isp, ISP_LOGERR, atiocope, lun, 0); + break; + + case AT_CDB: /* Got a CDB */ + /* + * Punt to platform specific layer. + */ + (void) isp_async(isp, ISPASYNC_TARGET_ACTION, aep); + break; + + case AT_RESET: + /* + * A bus reset came along an blew away this command. Why + * they do this in addition the async event code stuff, + * I dunno. + * + * Ignore it because the async event will clear things + * up for us. + */ + isp_prt(isp, ISP_LOGERR, atior, lun, aep->at_iid, 0); + break; + + + default: + isp_prt(isp, ISP_LOGERR, + "Unknown ATIO2 status 0x%x from initiator %d for lun %d", + aep->at_status, aep->at_iid, lun); + (void) isp_target_put_atio(isp, aep); + break; + } +} + +static void +isp_handle_ctio(struct ispsoftc *isp, ct_entry_t *ct) +{ + void *xs; + int pl = ISP_LOGTDEBUG2; + char *fmsg = NULL; + + if (ct->ct_syshandle) { + xs = isp_find_xs(isp, ct->ct_syshandle); + if (xs == NULL) + pl = ISP_LOGALL; + } else { + xs = NULL; + } + + switch(ct->ct_status & ~QLTM_SVALID) { + case CT_OK: + /* + * There are generally 3 possibilities as to why we'd get + * this condition: + * We disconnected after receiving a CDB. + * We sent or received data. + * We sent status & command complete. + */ + + if (ct->ct_flags & CT_SENDSTATUS) { + break; + } else if ((ct->ct_flags & CT_DATAMASK) == CT_NO_DATA) { + /* + * Nothing to do in this case. + */ + isp_prt(isp, pl, "CTIO- iid %d disconnected OK", + ct->ct_iid); + return; + } + break; + + case CT_BDR_MSG: + /* + * Bus Device Reset message received or the SCSI Bus has + * been Reset; the firmware has gone to Bus Free. + * + * The firmware generates an async mailbox interupt to + * notify us of this and returns outstanding CTIOs with this + * status. These CTIOs are handled in that same way as + * CT_ABORTED ones, so just fall through here. + */ + fmsg = "Bus Device Reset"; + /*FALLTHROUGH*/ + case CT_RESET: + if (fmsg == NULL) + fmsg = "Bus Reset"; + /*FALLTHROUGH*/ + case CT_ABORTED: + /* + * When an Abort message is received the firmware goes to + * Bus Free and returns all outstanding CTIOs with the status + * set, then sends us an Immediate Notify entry. + */ + if (fmsg == NULL) + fmsg = "ABORT TAG message sent by Initiator"; + + isp_prt(isp, ISP_LOGWARN, "CTIO destroyed by %s", fmsg); + break; + + case CT_INVAL: + /* + * CTIO rejected by the firmware due to disabled lun. + * "Cannot Happen". + */ + isp_prt(isp, ISP_LOGERR, + "Firmware rejected CTIO for disabled lun %d", + ct->ct_lun); + break; + + case CT_NOPATH: + /* + * CTIO rejected by the firmware due "no path for the + * nondisconnecting nexus specified". This means that + * we tried to access the bus while a non-disconnecting + * command is in process. + */ + isp_prt(isp, ISP_LOGERR, + "Firmware rejected CTIO for bad nexus %d/%d/%d", + ct->ct_iid, ct->ct_tgt, ct->ct_lun); + break; + + case CT_RSELTMO: + fmsg = "Reselection"; + /*FALLTHROUGH*/ + case CT_TIMEOUT: + if (fmsg == NULL) + fmsg = "Command"; + isp_prt(isp, ISP_LOGERR, "Firmware timed out on %s", fmsg); + break; + + case CT_PANIC: + if (fmsg == NULL) + fmsg = "Unrecoverable Error"; + /*FALLTHROUGH*/ + case CT_ERR: + if (fmsg == NULL) + fmsg = "Completed with Error"; + /*FALLTHROUGH*/ + case CT_PHASE_ERROR: + if (fmsg == NULL) + fmsg = "Phase Sequence Error"; + /*FALLTHROUGH*/ + case CT_TERMINATED: + if (fmsg == NULL) + fmsg = "terminated by TERMINATE TRANSFER"; + /*FALLTHROUGH*/ + case CT_NOACK: + if (fmsg == NULL) + fmsg = "unacknowledged Immediate Notify pending"; + isp_prt(isp, ISP_LOGERR, "CTIO returned by f/w- %s", fmsg); + break; + default: + isp_prt(isp, ISP_LOGERR, "Unknown CTIO status 0x%x", + ct->ct_status & ~QLTM_SVALID); + break; + } + + if (xs == NULL) { + /* + * There may be more than one CTIO for a data transfer, + * or this may be a status CTIO we're not monitoring. + * + * The assumption is that they'll all be returned in the + * order we got them. + */ + if (ct->ct_syshandle == 0) { + if ((ct->ct_flags & CT_SENDSTATUS) == 0) { + isp_prt(isp, pl, + "intermediate CTIO completed ok"); + } else { + isp_prt(isp, pl, + "unmonitored CTIO completed ok"); + } + } else { + isp_prt(isp, pl, + "NO xs for CTIO (handle 0x%x) status 0x%x", + ct->ct_syshandle, ct->ct_status & ~QLTM_SVALID); + } + } else { + /* + * Final CTIO completed. Release DMA resources and + * notify platform dependent layers. + */ + if ((ct->ct_flags & CT_DATAMASK) != CT_NO_DATA) { + ISP_DMAFREE(isp, xs, ct->ct_syshandle); + } + isp_prt(isp, pl, "final CTIO complete"); + /* + * The platform layer will destroy the handle if appropriate. + */ + (void) isp_async(isp, ISPASYNC_TARGET_ACTION, ct); + } +} + +static void +isp_handle_ctio2(struct ispsoftc *isp, ct2_entry_t *ct) +{ + XS_T *xs; + int pl = ISP_LOGTDEBUG2; + char *fmsg = NULL; + + if (ct->ct_syshandle) { + xs = isp_find_xs(isp, ct->ct_syshandle); + if (xs == NULL) + pl = ISP_LOGALL; + } else { + xs = NULL; + } + + switch(ct->ct_status & ~QLTM_SVALID) { + case CT_BUS_ERROR: + isp_prt(isp, ISP_LOGERR, "PCI DMA Bus Error"); + /* FALL Through */ + case CT_DATA_OVER: + case CT_DATA_UNDER: + case CT_OK: + /* + * There are generally 2 possibilities as to why we'd get + * this condition: + * We sent or received data. + * We sent status & command complete. + */ + + break; + + case CT_BDR_MSG: + /* + * Target Reset function received. + * + * The firmware generates an async mailbox interupt to + * notify us of this and returns outstanding CTIOs with this + * status. These CTIOs are handled in that same way as + * CT_ABORTED ones, so just fall through here. + */ + fmsg = "TARGET RESET Task Management Function Received"; + /*FALLTHROUGH*/ + case CT_RESET: + if (fmsg == NULL) + fmsg = "LIP Reset"; + /*FALLTHROUGH*/ + case CT_ABORTED: + /* + * When an Abort message is received the firmware goes to + * Bus Free and returns all outstanding CTIOs with the status + * set, then sends us an Immediate Notify entry. + */ + if (fmsg == NULL) + fmsg = "ABORT Task Management Function Received"; + + isp_prt(isp, ISP_LOGERR, "CTIO2 destroyed by %s", fmsg); + break; + + case CT_INVAL: + /* + * CTIO rejected by the firmware - invalid data direction. + */ + isp_prt(isp, ISP_LOGERR, "CTIO2 had wrong data directiond"); + break; + + case CT_RSELTMO: + fmsg = "failure to reconnect to initiator"; + /*FALLTHROUGH*/ + case CT_TIMEOUT: + if (fmsg == NULL) + fmsg = "command"; + isp_prt(isp, ISP_LOGERR, "Firmware timed out on %s", fmsg); + break; + + case CT_ERR: + fmsg = "Completed with Error"; + /*FALLTHROUGH*/ + case CT_LOGOUT: + if (fmsg == NULL) + fmsg = "Port Logout"; + /*FALLTHROUGH*/ + case CT_PORTNOTAVAIL: + if (fmsg == NULL) + fmsg = "Port not available"; + case CT_PORTCHANGED: + if (fmsg == NULL) + fmsg = "Port Changed"; + case CT_NOACK: + if (fmsg == NULL) + fmsg = "unacknowledged Immediate Notify pending"; + isp_prt(isp, ISP_LOGERR, "CTIO returned by f/w- %s", fmsg); + break; + + case CT_INVRXID: + /* + * CTIO rejected by the firmware because an invalid RX_ID. + * Just print a message. + */ + isp_prt(isp, ISP_LOGERR, + "CTIO2 completed with Invalid RX_ID 0x%x", ct->ct_rxid); + break; + + default: + isp_prt(isp, ISP_LOGERR, "Unknown CTIO2 status 0x%x", + ct->ct_status & ~QLTM_SVALID); + break; + } + + if (xs == NULL) { + /* + * There may be more than one CTIO for a data transfer, + * or this may be a status CTIO we're not monitoring. + * + * The assumption is that they'll all be returned in the + * order we got them. + */ + if (ct->ct_syshandle == 0) { + if ((ct->ct_flags & CT_SENDSTATUS) == 0) { + isp_prt(isp, pl, + "intermediate CTIO completed ok"); + } else { + isp_prt(isp, pl, + "unmonitored CTIO completed ok"); + } + } else { + isp_prt(isp, pl, + "NO xs for CTIO (handle 0x%x) status 0x%x", + ct->ct_syshandle, ct->ct_status & ~QLTM_SVALID); + } + } else { + if ((ct->ct_flags & CT2_DATAMASK) != CT2_NO_DATA) { + ISP_DMAFREE(isp, xs, ct->ct_syshandle); + } + if (ct->ct_flags & CT_SENDSTATUS) { + /* + * Sent status and command complete. + * + * We're now really done with this command, so we + * punt to the platform dependent layers because + * only there can we do the appropriate command + * complete thread synchronization. + */ + isp_prt(isp, pl, "status CTIO complete"); + } else { + /* + * Final CTIO completed. Release DMA resources and + * notify platform dependent layers. + */ + isp_prt(isp, pl, "data CTIO complete"); + } + (void) isp_async(isp, ISPASYNC_TARGET_ACTION, ct); + /* + * The platform layer will destroy the handle if appropriate. + */ + } +} +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/common/isp_target.h 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,557 @@ +/* + * Qlogic Target Mode Structure and Flag Definitions + * + * Copyright (c) 1997, 1998 + * Patrick Stirling + * pms@psconsult.com + * All rights reserved. + * + * Additional Copyright (c) 1999, 2000, 2001 + * Matthew Jacob + * mjacob@feral.com + * All rights reserved. + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#ifndef _ISP_TARGET_H +#define _ISP_TARGET_H + +/* + * Defines for all entry types + */ +#define QLTM_SVALID 0x80 +#define QLTM_SENSELEN 18 + +/* + * Structure for Enable Lun and Modify Lun queue entries + */ +typedef struct { + isphdr_t le_header; + u_int32_t le_reserved; + u_int8_t le_lun; + u_int8_t le_rsvd; + u_int8_t le_ops; /* Modify LUN only */ + u_int8_t le_tgt; /* Not for FC */ + u_int32_t le_flags; /* Not for FC */ + u_int8_t le_status; + u_int8_t le_reserved2; + u_int8_t le_cmd_count; + u_int8_t le_in_count; + u_int8_t le_cdb6len; /* Not for FC */ + u_int8_t le_cdb7len; /* Not for FC */ + u_int16_t le_timeout; + u_int16_t le_reserved3[20]; +} lun_entry_t; + +/* + * le_flags values + */ +#define LUN_TQAE 0x00000002 /* bit1 Tagged Queue Action Enable */ +#define LUN_DSSM 0x01000000 /* bit24 Disable Sending SDP Message */ +#define LUN_DISAD 0x02000000 /* bit25 Disable autodisconnect */ +#define LUN_DM 0x40000000 /* bit30 Disconnects Mandatory */ + +/* + * le_ops values + */ +#define LUN_CCINCR 0x01 /* increment command count */ +#define LUN_CCDECR 0x02 /* decrement command count */ +#define LUN_ININCR 0x40 /* increment immed. notify count */ +#define LUN_INDECR 0x80 /* decrement immed. notify count */ + +/* + * le_status values + */ +#define LUN_OK 0x01 /* we be rockin' */ +#define LUN_ERR 0x04 /* request completed with error */ +#define LUN_INVAL 0x06 /* invalid request */ +#define LUN_NOCAP 0x16 /* can't provide requested capability */ +#define LUN_ENABLED 0x3E /* LUN already enabled */ + +/* + * Immediate Notify Entry structure + */ +#define IN_MSGLEN 8 /* 8 bytes */ +#define IN_RSVDLEN 8 /* 8 words */ +typedef struct { + isphdr_t in_header; + u_int32_t in_reserved; + u_int8_t in_lun; /* lun */ + u_int8_t in_iid; /* initiator */ + u_int8_t in_reserved2; + u_int8_t in_tgt; /* target */ + u_int32_t in_flags; + u_int8_t in_status; + u_int8_t in_rsvd2; + u_int8_t in_tag_val; /* tag value */ + u_int8_t in_tag_type; /* tag type */ + u_int16_t in_seqid; /* sequence id */ + u_int8_t in_msg[IN_MSGLEN]; /* SCSI message bytes */ + u_int16_t in_reserved3[IN_RSVDLEN]; + u_int8_t in_sense[QLTM_SENSELEN];/* suggested sense data */ +} in_entry_t; + +typedef struct { + isphdr_t in_header; + u_int32_t in_reserved; + u_int8_t in_lun; /* lun */ + u_int8_t in_iid; /* initiator */ + u_int16_t in_scclun; + u_int32_t in_reserved2; + u_int16_t in_status; + u_int16_t in_task_flags; + u_int16_t in_seqid; /* sequence id */ +} in_fcentry_t; + +/* + * Values for the in_status field + */ +#define IN_REJECT 0x0D /* Message Reject message received */ +#define IN_RESET 0x0E /* Bus Reset occurred */ +#define IN_NO_RCAP 0x16 /* requested capability not available */ +#define IN_IDE_RECEIVED 0x33 /* Initiator Detected Error msg received */ +#define IN_RSRC_UNAVAIL 0x34 /* resource unavailable */ +#define IN_MSG_RECEIVED 0x36 /* SCSI message received */ +#define IN_ABORT_TASK 0x20 /* task named in RX_ID is being aborted (FC) */ +#define IN_PORT_LOGOUT 0x29 /* port has logged out (FC) */ +#define IN_PORT_CHANGED 0x2A /* port changed */ +#define IN_GLOBAL_LOGO 0x2E /* all ports logged out */ +#define IN_NO_NEXUS 0x3B /* Nexus not established */ + +/* + * Values for the in_task_flags field- should only get one at a time! + */ +#define TASK_FLAGS_ABORT_TASK (1<<9) +#define TASK_FLAGS_CLEAR_TASK_SET (1<<10) +#define TASK_FLAGS_TARGET_RESET (1<<13) +#define TASK_FLAGS_CLEAR_ACA (1<<14) +#define TASK_FLAGS_TERMINATE_TASK (1<<15) + +#ifndef MSG_ABORT_TAG +#define MSG_ABORT_TAG 0x06 +#endif +#ifndef MSG_CLEAR_QUEUE +#define MSG_CLEAR_QUEUE 0x0e +#endif +#ifndef MSG_BUS_DEV_RESET +#define MSG_BUS_DEV_RESET 0x0b +#endif +#ifndef MSG_REL_RECOVERY +#define MSG_REL_RECOVERY 0x10 +#endif +#ifndef MSG_TERM_IO_PROC +#define MSG_TERM_IO_PROC 0x11 +#endif + + +/* + * Notify Acknowledge Entry structure + */ +#define NA_RSVDLEN 22 +typedef struct { + isphdr_t na_header; + u_int32_t na_reserved; + u_int8_t na_lun; /* lun */ + u_int8_t na_iid; /* initiator */ + u_int8_t na_reserved2; + u_int8_t na_tgt; /* target */ + u_int32_t na_flags; + u_int8_t na_status; + u_int8_t na_event; + u_int16_t na_seqid; /* sequence id */ + u_int16_t na_reserved3[NA_RSVDLEN]; +} na_entry_t; + +/* + * Value for the na_event field + */ +#define NA_RST_CLRD 0x80 /* Clear an async event notification */ +#define NA_OK 0x01 /* Notify Acknowledge Succeeded */ +#define NA_INVALID 0x06 /* Invalid Notify Acknowledge */ + +#define NA2_RSVDLEN 21 +typedef struct { + isphdr_t na_header; + u_int32_t na_reserved; + u_int8_t na_lun; /* lun */ + u_int8_t na_iid; /* initiator */ + u_int16_t na_scclun; + u_int16_t na_flags; + u_int16_t na_reserved2; + u_int16_t na_status; + u_int16_t na_task_flags; + u_int16_t na_seqid; /* sequence id */ + u_int16_t na_reserved3[NA2_RSVDLEN]; +} na_fcentry_t; +#define NAFC_RCOUNT 0x80 /* increment resource count */ +#define NAFC_RST_CLRD 0x20 /* Clear LIP Reset */ +/* + * Accept Target I/O Entry structure + */ +#define ATIO_CDBLEN 26 + +typedef struct { + isphdr_t at_header; + u_int16_t at_reserved; + u_int16_t at_handle; + u_int8_t at_lun; /* lun */ + u_int8_t at_iid; /* initiator */ + u_int8_t at_cdblen; /* cdb length */ + u_int8_t at_tgt; /* target */ + u_int32_t at_flags; + u_int8_t at_status; /* firmware status */ + u_int8_t at_scsi_status; /* scsi status */ + u_int8_t at_tag_val; /* tag value */ + u_int8_t at_tag_type; /* tag type */ + u_int8_t at_cdb[ATIO_CDBLEN]; /* received CDB */ + u_int8_t at_sense[QLTM_SENSELEN];/* suggested sense data */ +} at_entry_t; + +/* + * at_flags values + */ +#define AT_NODISC 0x00008000 /* disconnect disabled */ +#define AT_TQAE 0x00000002 /* Tagged Queue Action enabled */ + +/* + * at_status values + */ +#define AT_PATH_INVALID 0x07 /* ATIO sent to firmware for disabled lun */ +#define AT_RESET 0x0E /* SCSI Bus Reset Occurred */ +#define AT_PHASE_ERROR 0x14 /* Bus phase sequence error */ +#define AT_NOCAP 0x16 /* Requested capability not available */ +#define AT_BDR_MSG 0x17 /* Bus Device Reset msg received */ +#define AT_CDB 0x3D /* CDB received */ + +/* + * Macros to create and fetch and test concatenated handle and tag value macros + */ + +#define AT_MAKE_TAGID(tid, aep) \ + tid = ((aep)->at_handle << 16); \ + if ((aep)->at_flags & AT_TQAE) \ + (tid) |= ((aep)->at_tag_val + 1) + +#define CT_MAKE_TAGID(tid, ct) \ + tid = ((ct)->ct_fwhandle << 16); \ + if ((ct)->ct_flags & CT_TQAE) \ + (tid) |= ((ct)->ct_tag_val + 1) + +#define AT_HAS_TAG(val) ((val) & 0xffff) +#define AT_GET_TAG(val) AT_HAS_TAG(val) - 1 +#define AT_GET_HANDLE(val) ((val) >> 16) + +/* + * Accept Target I/O Entry structure, Type 2 + */ +#define ATIO2_CDBLEN 16 + +typedef struct { + isphdr_t at_header; + u_int32_t at_reserved; + u_int8_t at_lun; /* lun or reserved */ + u_int8_t at_iid; /* initiator */ + u_int16_t at_rxid; /* response ID */ + u_int16_t at_flags; + u_int16_t at_status; /* firmware status */ + u_int8_t at_reserved1; + u_int8_t at_taskcodes; + u_int8_t at_taskflags; + u_int8_t at_execodes; + u_int8_t at_cdb[ATIO2_CDBLEN]; /* received CDB */ + u_int32_t at_datalen; /* allocated data len */ + u_int16_t at_scclun; /* SCC Lun or reserved */ + u_int16_t at_wwpn[4]; /* WWPN of initiator */ + u_int16_t at_reserved2[6]; + u_int16_t at_oxid; +} at2_entry_t; + +#define ATIO2_WWPN_OFFSET 0x2A +#define ATIO2_OXID_OFFSET 0x3E + +#define ATIO2_TC_ATTR_MASK 0x7 +#define ATIO2_TC_ATTR_SIMPLEQ 0 +#define ATIO2_TC_ATTR_HEADOFQ 1 +#define ATIO2_TC_ATTR_ORDERED 2 +#define ATIO2_TC_ATTR_ACAQ 4 +#define ATIO2_TC_ATTR_UNTAGGED 5 + +/* + * Continue Target I/O Entry structure + * Request from driver. The response from the + * ISP firmware is the same except that the last 18 + * bytes are overwritten by suggested sense data if + * the 'autosense valid' bit is set in the status byte. + */ +typedef struct { + isphdr_t ct_header; + u_int16_t ct_reserved; +#define ct_syshandle ct_reserved /* we use this */ + u_int16_t ct_fwhandle; /* required by f/w */ + u_int8_t ct_lun; /* lun */ + u_int8_t ct_iid; /* initiator id */ + u_int8_t ct_reserved2; + u_int8_t ct_tgt; /* our target id */ + u_int32_t ct_flags; + u_int8_t ct_status; /* isp status */ + u_int8_t ct_scsi_status; /* scsi status */ + u_int8_t ct_tag_val; /* tag value */ + u_int8_t ct_tag_type; /* tag type */ + u_int32_t ct_xfrlen; /* transfer length */ + u_int32_t ct_resid; /* residual length */ + u_int16_t ct_timeout; + u_int16_t ct_seg_count; + /* + * This is so we can share tag name space with + * CTIO{2,3,4} with the minimum of pain. + */ + union { + ispds_t ct_a[ISP_RQDSEG]; + } _u; +#define ct_dataseg _u.ct_a +} ct_entry_t; + +/* + * For some of the dual port SCSI adapters, port (bus #) is reported + * in the MSbit of ct_iid. Bit fields are a bit too awkward here. + * + * Note that this does not apply to FC adapters at all which can and + * do report IIDs between 129 && 255 (these represent devices that have + * logged in across a SCSI fabric). + */ +#define GET_IID_VAL(x) (x & 0x3f) +#define GET_BUS_VAL(x) ((x >> 7) & 0x1) +#define SET_IID_VAL(y, x) y = ((y & ~0x3f) | (x & 0x3f)) +#define SET_BUS_VAL(y, x) y = ((y & 0x3f) | ((x & 0x1) << 7)) + +/* + * ct_flags values + */ +#define CT_TQAE 0x00000002 /* bit 1, Tagged Queue Action enable */ +#define CT_DATA_IN 0x00000040 /* bits 6&7, Data direction */ +#define CT_DATA_OUT 0x00000080 /* bits 6&7, Data direction */ +#define CT_NO_DATA 0x000000C0 /* bits 6&7, Data direction */ +#define CT_CCINCR 0x00000100 /* bit 8, autoincrement atio count */ +#define CT_DATAMASK 0x000000C0 /* bits 6&7, Data direction */ +#define CT_INISYNCWIDE 0x00004000 /* bit 14, Do Sync/Wide Negotiation */ +#define CT_NODISC 0x00008000 /* bit 15, Disconnects disabled */ +#define CT_DSDP 0x01000000 /* bit 24, Disable Save Data Pointers */ +#define CT_SENDRDP 0x04000000 /* bit 26, Send Restore Pointers msg */ +#define CT_SENDSTATUS 0x80000000 /* bit 31, Send SCSI status byte */ + +/* + * ct_status values + * - set by the firmware when it returns the CTIO + */ +#define CT_OK 0x01 /* completed without error */ +#define CT_ABORTED 0x02 /* aborted by host */ +#define CT_ERR 0x04 /* see sense data for error */ +#define CT_INVAL 0x06 /* request for disabled lun */ +#define CT_NOPATH 0x07 /* invalid ITL nexus */ +#define CT_INVRXID 0x08 /* (FC only) Invalid RX_ID */ +#define CT_DATA_OVER 0x09 /* (FC only) Data Overrun */ +#define CT_RSELTMO 0x0A /* reselection timeout after 2 tries */ +#define CT_TIMEOUT 0x0B /* timed out */ +#define CT_RESET 0x0E /* SCSI Bus Reset occurred */ +#define CT_PARITY 0x0F /* Uncorrectable Parity Error */ +#define CT_BUS_ERROR 0x10 /* (FC Only) DMA PCI Error */ +#define CT_PANIC 0x13 /* Unrecoverable Error */ +#define CT_PHASE_ERROR 0x14 /* Bus phase sequence error */ +#define CT_BDR_MSG 0x17 /* Bus Device Reset msg received */ +#define CT_DATA_UNDER 0x15 /* (FC only) Data Underrun */ +#define CT_TERMINATED 0x19 /* due to Terminate Transfer mbox cmd */ +#define CT_PORTNOTAVAIL 0x28 /* port not available */ +#define CT_LOGOUT 0x29 /* port logout */ +#define CT_PORTCHANGED 0x2A /* port changed */ +#define CT_IDE 0x33 /* Initiator Detected Error */ +#define CT_NOACK 0x35 /* Outstanding Immed. Notify. entry */ + +/* + * When the firmware returns a CTIO entry, it may overwrite the last + * part of the structure with sense data. This starts at offset 0x2E + * into the entry, which is in the middle of ct_dataseg[1]. Rather + * than define a new struct for this, I'm just using the sense data + * offset. + */ +#define CTIO_SENSE_OFFSET 0x2E + +/* + * Entry length in u_longs. All entries are the same size so + * any one will do as the numerator. + */ +#define UINT32_ENTRY_SIZE (sizeof(at_entry_t)/sizeof(u_int32_t)) + +/* + * QLA2100 CTIO (type 2) entry + */ +#define MAXRESPLEN 26 +typedef struct { + isphdr_t ct_header; + u_int16_t ct_reserved; + u_int16_t ct_fwhandle; /* just to match CTIO */ + u_int8_t ct_lun; /* lun */ + u_int8_t ct_iid; /* initiator id */ + u_int16_t ct_rxid; /* response ID */ + u_int16_t ct_flags; + u_int16_t ct_status; /* isp status */ + u_int16_t ct_timeout; + u_int16_t ct_seg_count; + u_int32_t ct_reloff; /* relative offset */ + int32_t ct_resid; /* residual length */ + union { + /* + * The three different modes that the target driver + * can set the CTIO{2,3,4} up as. + * + * The first is for sending FCP_DATA_IUs as well as + * (optionally) sending a terminal SCSI status FCP_RSP_IU. + * + * The second is for sending SCSI sense data in an FCP_RSP_IU. + * Note that no FCP_DATA_IUs will be sent. + * + * The third is for sending FCP_RSP_IUs as built specifically + * in system memory as located by the isp_dataseg. + */ + struct { + u_int32_t _reserved; + u_int16_t _reserved2; + u_int16_t ct_scsi_status; + u_int32_t ct_xfrlen; + union { + ispds_t ct_a[ISP_RQDSEG_T2]; /* CTIO2 */ + ispds64_t ct_b[ISP_RQDSEG_T3]; /* CTIO3 */ + ispdslist_t ct_c; /* CTIO4 */ + } _u; +#define ct_dataseg _u.ct_a +#define ct_dataseg64 _u.ct_b +#define ct_dslist _u.ct_c + } m0; + struct { + u_int16_t _reserved; + u_int16_t _reserved2; + u_int16_t ct_senselen; + u_int16_t ct_scsi_status; + u_int16_t ct_resplen; + u_int8_t ct_resp[MAXRESPLEN]; + } m1; + struct { + u_int32_t _reserved; + u_int16_t _reserved2; + u_int16_t _reserved3; + u_int32_t ct_datalen; + ispds_t ct_fcp_rsp_iudata; + } m2; + /* + * CTIO2 returned from F/W... + */ + struct { + u_int32_t _reserved[4]; + u_int16_t ct_scsi_status; + u_int8_t ct_sense[QLTM_SENSELEN]; + } fw; + } rsp; +} ct2_entry_t; + +/* + * ct_flags values for CTIO2 + */ +#define CT2_FLAG_MMASK 0x0003 +#define CT2_FLAG_MODE0 0x0000 +#define CT2_FLAG_MODE1 0x0001 +#define CT2_FLAG_MODE2 0x0002 +#define CT2_DATA_IN CT_DATA_IN +#define CT2_DATA_OUT CT_DATA_OUT +#define CT2_NO_DATA CT_NO_DATA +#define CT2_DATAMASK CT_DATAMASK +#define CT2_CCINCR 0x0100 +#define CT2_FASTPOST 0x0200 +#define CT2_SENDSTATUS 0x8000 + +/* + * ct_status values are (mostly) the same as that for ct_entry. + */ + +/* + * ct_scsi_status values- the low 8 bits are the normal SCSI status + * we know and love. The upper 8 bits are validity markers for FCP_RSP_IU + * fields. + */ +#define CT2_RSPLEN_VALID 0x0100 +#define CT2_SNSLEN_VALID 0x0200 +#define CT2_DATA_OVER 0x0400 +#define CT2_DATA_UNDER 0x0800 + +/* + * Debug macros + */ + +#define ISP_TDQE(isp, msg, idx, arg) \ + if (isp->isp_dblev & ISP_LOGTDEBUG2) isp_print_qentry(isp, msg, idx, arg) + +#ifdef ISP_TARGET_FUNCTIONS +/* + * The functions below are for the publicly available + * target mode functions that are internal to the Qlogic driver. + */ + +/* + * This function handles new response queue entry appropriate for target mode. + */ +int isp_target_notify(struct ispsoftc *, void *, u_int16_t *); + +/* + * Enable/Disable/Modify a logical unit. + * (softc, cmd, bus, tgt, lun, cmd_cnt, inotify_cnt, opaque) + */ +#define DFLT_CMND_CNT 0xfe /* unmonitored */ +#define DFLT_INOT_CNT 16 +int isp_lun_cmd(struct ispsoftc *, int, int, int, int, int, int, u_int32_t); + +/* + * General request queue 'put' routine for target mode entries. + */ +int isp_target_put_entry(struct ispsoftc *isp, void *); + +/* + * General routine to put back an ATIO entry- + * used for replenishing f/w resource counts. + * The argument is a pointer to a source ATIO + * or ATIO2. + */ +int isp_target_put_atio(struct ispsoftc *, void *); + +/* + * General routine to send a final CTIO for a command- used mostly for + * local responses. + */ +int isp_endcmd(struct ispsoftc *, void *, u_int32_t, u_int16_t); +#define ECMD_SVALID 0x100 + +/* + * Handle an asynchronous event + * + * Return nonzero if the interrupt that generated this event has been dismissed. + */ + +int isp_target_async(struct ispsoftc *, int, int); +#endif +#endif /* _ISP_TARGET_H */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/common/isp_tpublic.h 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,334 @@ +/* + * Qlogic ISP Host Adapter Public Target Interface Structures && Routines + *--------------------------------------- + * Copyright (c) 2000 by Matthew Jacob + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification, immediately at the beginning of the file. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Matthew Jacob + * Feral Software + * mjacob@feral.com + */ + +/* + * Required software target mode message and event handling structures. + * + * The message and event structures are used by the MI layer + * to propagate messages and events upstream. + */ + +#ifndef IN_MSGLEN +#define IN_MSGLEN 8 +#endif +typedef struct { + void * nt_hba; /* HBA tag */ + u_int64_t nt_iid; /* inititator id */ + u_int64_t nt_tgt; /* target id */ + u_int64_t nt_lun; /* logical unit */ + u_int8_t nt_bus; /* bus */ + u_int8_t nt_tagtype; /* tag type */ + u_int16_t nt_tagval; /* tag value */ + u_int8_t nt_msg[IN_MSGLEN]; /* message content */ +} tmd_msg_t; + +typedef struct { + void * ev_hba; /* HBA tag */ + u_int16_t ev_bus; /* bus */ + u_int16_t ev_event; /* type of async event */ +} tmd_event_t; + +/* + * Suggested Software Target Mode Command Handling structure. + * + * A note about terminology: + * + * MD stands for "Machine Dependent". + * + * This driver is structured in three layers: Outer MD, core, and inner MD. + * The latter also is bus dependent (i.e., is cognizant of PCI bus issues + * as well as platform issues). + * + * + * "Outer Layer" means "Other Module" + * + * Some additional module that actually implements SCSI target command + * policy is the recipient of incoming commands and the source of the + * disposition for them. + * + * The command structure below is one suggested possible MD command structure, + * but since the handling of thbis is entirely in the MD layer, there is + * no explicit or implicit requirement that it be used. + * + * The cd_private tag should be used by the MD layer to keep a free list + * of these structures. Code outside of this driver can then use this + * to identify it's own unit structures. That is, when not on the MD + * layer's freelist, the MD layer should shove into it the identifier + * that the outer layer has for it- passed in on an initial QIN_HBA_REG + * call (see below). + * + * The cd_hba tag is a tag that uniquely identifies the HBA this target + * mode command is coming from. The outer layer has to pass this back + * unchanged to avoid chaos. + * + * The cd_iid, cd_tgt, cd_lun and cd_bus tags are used to identify the + * id of the initiator who sent us a command, the target claim to be, the + * lun on the target we claim to be, and the bus instance (for multiple + * bus host adapters) that this applies to (consider it an extra Port + * parameter). The iid, tgt and lun values are deliberately chosen to be + * fat so that, for example, World Wide Names can be used instead of + * the units that the Qlogic firmware uses (in the case where the MD + * layer maintains a port database, for example). + * + * The cd_tagtype field specifies what kind of command tag has been + * sent with the command. The cd_tagval is the tag's value (low 16 + * bits). It also contains (in the upper 16 bits) any command handle. + * + * + * N.B.: when the MD layer sends this command to outside software + * the outside software likely *MUST* return the same cd_tagval that + * was in place because this value is likely what the Qlogic f/w uses + * to identify a command. + * + * The cd_cdb contains storage for the passed in command descriptor block. + * This is the maximum size we can get out of the Qlogic f/w. There's no + * passed in length because whoever decodes the command to act upon it + * will know what the appropriate length is. + * + * The tag cd_lflags are the flags set by the MD driver when it gets + * command incoming or when it needs to inform any outside entities + * that the last requested action failed. + * + * The tag cd_hflags should be set by any outside software to indicate + * the validity of sense and status fields (defined below) and to indicate + * the direction data is expected to move. It is an error to have both + * CDFH_DATA_IN and CDFH_DATA_OUT set. + * + * If the CDFH_STSVALID flag is set, the command should be completed (after + * sending any data and/or status). If CDFH_SNSVALID is set and the MD layer + * can also handle sending the associated sense data (either back with an + * FCP RESPONSE IU for Fibre Channel or otherwise automatically handling a + * REQUEST SENSE from the initator for this target/lun), the MD layer will + * set the CDFL_SENTSENSE flag on successful transmission of the sense data. + * It is an error for the CDFH_SNSVALID bit to be set and CDFH_STSVALID not + * to be set. It is an error for the CDFH_SNSVALID be set and the associated + * SCSI status (cd_scsi_status) not be set to CHECK CONDITON. + * + * The tag cd_data points to a data segment to either be filled or + * read from depending on the direction of data movement. The tag + * is undefined if no data direction is set. The MD layer and outer + * layers must agree on the meaning of cd_data. + * + * The tag cd_totlen is the total data amount expected to be moved + * over the life of the command. It *may* be set by the MD layer, possibly + * from the datalen field of an FCP CMND IU unit. If it shows up in the outer + * layers set to zero and the CDB indicates data should be moved, the outer + * layer should set it to the amount expected to be moved. + * + * The tag cd_resid should be the total residual of data not transferred. + * The outer layers need to set this at the begining of command processing + * to equal cd_totlen. As data is successfully moved, this value is decreased. + * At the end of a command, any nonzero residual indicates the number of bytes + * requested but not moved. XXXXXXXXXXXXXXXXXXXXXXX TOO VAGUE!!! + * + * The tag cd_xfrlen is the length of the currently active data transfer. + * This allows several interations between any outside software and the + * MD layer to move data. + * + * The reason that total length and total residual have to be tracked + * is that fibre channel FCP DATA IU units have to have a relative + * offset field. + * + * N.B.: there is no necessary 1-to-1 correspondence between any one + * data transfer segment and the number of CTIOs that will be generated + * satisfy the current data transfer segment. It's not also possible to + * predict how big a transfer can be before it will be 'too big'. Be + * reasonable- a 64KB transfer is 'reasonable'. A 1MB transfer may not + * be. A 32MB transfer is unreasonable. The problem here has to do with + * how CTIOs can be used to map passed data pointers. In systems which + * have page based scatter-gather requirements, each PAGESIZEd chunk will + * consume one data segment descriptor- you get 3 or 4 of them per CTIO. + * The size of the REQUEST QUEUE you drop a CTIO onto is finite (typically + * it's 256, but on some systems it's even smaller, and note you have to + * sure this queue with the initiator side of this driver). + * + * The tags cd_sense and cd_scsi_status are pretty obvious. + * + * The tag cd_error is to communicate between the MD layer and outer software + * the current error conditions. + * + * The tag cd_reserved pads out the structure to 128 bytes. The first + * half of the pad area is reserved to the MD layer, and the second half + * may be used by outer layers, for scratch purposes. + */ + +#ifndef _LP64 +#if defined(__alpha__) || defined(__sparcv9cpu) || defined(__sparc_v9__) ||\ + defined(__ia64__) +#define _LP64 +#endif +#endif + +#ifndef _TMD_PAD_LEN +#ifdef _LP64 +#define _TMD_PAD_LEN 12 +#else +#define _TMD_PAD_LEN 24 +#endif +#endif +#ifndef ATIO_CDBLEN +#define ATIO_CDBLEN 26 +#endif +#ifndef QLTM_SENSELEN +#define QLTM_SENSELEN 18 +#endif +typedef struct tmd_cmd { + void * cd_private; /* layer private data */ + void * cd_hba; /* HBA tag */ + void * cd_data; /* 'pointer' to data */ + u_int64_t cd_iid; /* initiator ID */ + u_int64_t cd_tgt; /* target id */ + u_int64_t cd_lun; /* logical unit */ + u_int8_t cd_bus; /* bus */ + u_int8_t cd_tagtype; /* tag type */ + u_int32_t cd_tagval; /* tag value */ + u_int8_t cd_cdb[ATIO_CDBLEN]; /* Command */ + u_int8_t cd_lflags; /* flags lower level sets */ + u_int8_t cd_hflags; /* flags higher level sets */ + u_int32_t cd_totlen; /* total data requirement */ + u_int32_t cd_resid; /* total data residual */ + u_int32_t cd_xfrlen; /* current data requirement */ + int32_t cd_error; /* current error */ + u_int8_t cd_sense[QLTM_SENSELEN]; + u_int16_t cd_scsi_status; /* closing SCSI status */ + u_int8_t cd_reserved[_TMD_PAD_LEN]; +} tmd_cmd_t; + +#define CDFL_SNSVALID 0x01 /* sense data (from f/w) valid */ +#define CDFL_NODISC 0x02 /* disconnects disabled */ +#define CDFL_SENTSENSE 0x04 /* last action sent sense data */ +#define CDFL_SENTSTATUS 0x08 /* last action sent status */ +#define CDFL_ERROR 0x10 /* last action ended in error */ +#define CDFL_BUSY 0x40 /* this command is not on a free list */ +#define CDFL_PRIVATE_0 0x80 /* private layer flags */ + +#define CDFH_SNSVALID 0x01 /* sense data valid */ +#define CDFH_STSVALID 0x02 /* status valid */ +#define CDFH_NODATA 0x00 /* no data transfer expected */ +#define CDFH_DATA_IN 0x04 /* target (us) -> initiator (them) */ +#define CDFH_DATA_OUT 0x08 /* initiator (them) -> target (us) */ +#define CDFH_DATA_MASK 0x0C /* mask to cover data direction */ +#define CDFH_PRIVATE_0 0x80 /* private layer flags */ + +/* + * Action codes set by the Qlogic MD target driver for + * the external layer to figure out what to do with. + */ +typedef enum { + QOUT_HBA_REG=0, /* the argument is a pointer to a hba_register_t */ + QOUT_TMD_START, /* the argument is a pointer to a tmd_cmd_t */ + QOUT_TMD_DONE, /* the argument is a pointer to a tmd_cmd_t */ + QOUT_TEVENT, /* the argument is a pointer to a tmd_event_t */ + QOUT_TMSG, /* the argument is a pointer to a tmd_msg_t */ + QOUT_HBA_UNREG /* the argument is a pointer to a hba_register_t */ +} tact_e; + +/* + * Action codes set by the external layer for the + * MD Qlogic driver to figure out what to do with. + */ +typedef enum { + QIN_HBA_REG=6, /* the argument is a pointer to a hba_register_t */ + QIN_ENABLE, /* the argument is a pointer to a tmd_cmd_t */ + QIN_DISABLE, /* the argument is a pointer to a tmd_cmd_t */ + QIN_TMD_CONT, /* the argument is a pointer to a tmd_cmd_t */ + QIN_TMD_FIN, /* the argument is a pointer to a done tmd_cmd_t */ + QIN_HBA_UNREG /* the argument is a pointer to a hba_register_t */ +} qact_e; + +/* + * A word about the START/CONT/DONE/FIN dance: + * + * When the HBA is enabled for receiving commands, one may show up + * without notice. When that happens, the Qlogic target mode driver + * gets a tmd_cmd_t, fills it with the info that just arrived, and + * calls the outer layer with a QOUT_TMD_START code and pointer to + * the tmd_cmd_t. + * + * The outer layer decodes the command, fetches data, prepares stuff, + * whatever, and starts by passing back the pointer with a QIN_TMD_CONT + * code which causes the Qlogic target mode driver to generate CTIOs to + * satisfy whatever action needs to be taken. When those CTIOs complete, + * the Qlogic target driver sends the pointer to the cmd_tmd_t back with + * a QOUT_TMD_DONE code. This repeats for as long as necessary. + * + * The outer layer signals it wants to end the command by settings within + * the tmd_cmd_t itself. When the final QIN_TMD_CONT is reported completed, + * the outer layer frees the tmd_cmd_t by sending the pointer to it + * back with a QIN_TMD_FIN code. + * + * The graph looks like: + * + * QOUT_TMD_START -> [ QIN_TMD_CONT -> QOUT_TMD_DONE ] * -> QIN_TMD_FIN. + * + */ + +/* + * A word about ENABLE/DISABLE: the argument is a pointer to a tmd_cmd_t + * with cd_hba, cd_bus, cd_tgt and cd_lun filled out. If an error occurs + * in either enabling or disabling the described lun, cd_lflags is set + * with CDFL_ERROR. + * + * Logical unit zero must be the first enabled and the last disabled. + */ + +/* + * Target handler functions. + * The MD target handler function (the outer layer calls this) + * should be be prototyped like: + * + * void target_action(qact_e, void *arg) + * + * The outer layer target handler function (the MD layer calls this) + * should be be prototyped like: + * + * void system_action(tact_e, void *arg) + */ + +/* + * This structure is used to register to other software modules the + * binding of an HBA identifier, driver name and instance and the + * lun width capapbilities of this target driver. It's up to each + * platform to figure out how it wants to do this, but a typical + * sequence would be for the MD layer to find some external module's + * entry point and start by sending a QOUT_HBA_REG with info filled + * in, and the external module to call back with a QIN_HBA_REG that + * passes back the corresponding information. + */ +typedef struct { + void * r_identity; + char r_name[8]; + int r_inst; + int r_lunwidth; + int r_buswidth; + void (*r_action)(int, void *); +} hba_register_t; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/common/ispvar.h 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,901 @@ +/* + * Soft Definitions for for Qlogic ISP SCSI adapters. + * + * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice immediately at the beginning of the file, without modification, + * this list of conditions, and the following disclaimer. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef _ISPVAR_H +#define _ISPVAR_H + +#if defined(__NetBSD__) || defined(__OpenBSD__) +#include +#ifdef ISP_TARGET_MODE +#include +#include +#endif +#endif +#ifdef __FreeBSD__ +#include +#ifdef ISP_TARGET_MODE +#include +#include +#endif +#endif +#ifdef __linux__ +#include "ispmbox.h" +#ifdef ISP_TARGET_MODE +#include "isp_target.h" +#include "isp_tpublic.h" +#endif +#endif + +#define ISP_CORE_VERSION_MAJOR 2 +#define ISP_CORE_VERSION_MINOR 7 + +/* + * Vector for bus specific code to provide specific services. + */ +struct ispsoftc; +struct ispmdvec { + int (*dv_rd_isr) + (struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); + u_int16_t (*dv_rd_reg) (struct ispsoftc *, int); + void (*dv_wr_reg) (struct ispsoftc *, int, u_int16_t); + int (*dv_mbxdma) (struct ispsoftc *); + int (*dv_dmaset) (struct ispsoftc *, + XS_T *, ispreq_t *, u_int16_t *, u_int16_t); + void (*dv_dmaclr) + (struct ispsoftc *, XS_T *, u_int16_t); + void (*dv_reset0) (struct ispsoftc *); + void (*dv_reset1) (struct ispsoftc *); + void (*dv_dregs) (struct ispsoftc *, const char *); + u_int16_t *dv_ispfw; /* ptr to f/w */ + u_int16_t dv_conf1; + u_int16_t dv_clock; /* clock frequency */ +}; + +/* + * Overall parameters + */ +#define MAX_TARGETS 16 +#define MAX_FC_TARG 256 +#define ISP_MAX_TARGETS(isp) (IS_FC(isp)? MAX_FC_TARG : MAX_TARGETS) +#define ISP_MAX_LUNS(isp) (isp)->isp_maxluns + +/* + * 'Types' + */ +#ifdef ISP_DAC_SUPPORTED +typedef u_int64_t isp_dma_addr_t; +#else +typedef u_int32_t isp_dma_addr_t; +#endif + +/* + * Macros to access ISP registers through bus specific layers- + * mostly wrappers to vector through the mdvec structure. + */ +#define ISP_READ_ISR(isp, isrp, semap, mbox0p) \ + (*(isp)->isp_mdvec->dv_rd_isr)(isp, isrp, semap, mbox0p) + +#define ISP_READ(isp, reg) \ + (*(isp)->isp_mdvec->dv_rd_reg)((isp), (reg)) + +#define ISP_WRITE(isp, reg, val) \ + (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), (val)) + +#define ISP_MBOXDMASETUP(isp) \ + (*(isp)->isp_mdvec->dv_mbxdma)((isp)) + +#define ISP_DMASETUP(isp, xs, req, iptrp, optr) \ + (*(isp)->isp_mdvec->dv_dmaset)((isp), (xs), (req), (iptrp), (optr)) + +#define ISP_DMAFREE(isp, xs, hndl) \ + if ((isp)->isp_mdvec->dv_dmaclr) \ + (*(isp)->isp_mdvec->dv_dmaclr)((isp), (xs), (hndl)) + +#define ISP_RESET0(isp) \ + if ((isp)->isp_mdvec->dv_reset0) (*(isp)->isp_mdvec->dv_reset0)((isp)) +#define ISP_RESET1(isp) \ + if ((isp)->isp_mdvec->dv_reset1) (*(isp)->isp_mdvec->dv_reset1)((isp)) +#define ISP_DUMPREGS(isp, m) \ + if ((isp)->isp_mdvec->dv_dregs) (*(isp)->isp_mdvec->dv_dregs)((isp),(m)) + +#define ISP_SETBITS(isp, reg, val) \ + (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) | (val)) + +#define ISP_CLRBITS(isp, reg, val) \ + (*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) & ~(val)) + +/* + * The MEMORYBARRIER macro is defined per platform (to provide synchronization + * on Request and Response Queues, Scratch DMA areas, and Registers) + * + * Defined Memory Barrier Synchronization Types + */ +#define SYNC_REQUEST 0 /* request queue synchronization */ +#define SYNC_RESULT 1 /* result queue synchronization */ +#define SYNC_SFORDEV 2 /* scratch, sync for ISP */ +#define SYNC_SFORCPU 3 /* scratch, sync for CPU */ +#define SYNC_REG 4 /* for registers */ + +/* + * Request/Response Queue defines and macros. + * The maximum is defined per platform (and can be based on board type). + */ +/* This is the size of a queue entry (request and response) */ +#define QENTRY_LEN 64 +/* Both request and result queue length must be a power of two */ +#define RQUEST_QUEUE_LEN(x) MAXISPREQUEST(x) +#ifdef ISP_TARGET_MODE +#define RESULT_QUEUE_LEN(x) MAXISPREQUEST(x) +#else +#define RESULT_QUEUE_LEN(x) \ + (((MAXISPREQUEST(x) >> 2) < 64)? 64 : MAXISPREQUEST(x) >> 2) +#endif +#define ISP_QUEUE_ENTRY(q, idx) ((q) + ((idx) * QENTRY_LEN)) +#define ISP_QUEUE_SIZE(n) ((n) * QENTRY_LEN) +#define ISP_NXT_QENTRY(idx, qlen) (((idx) + 1) & ((qlen)-1)) +#define ISP_QFREE(in, out, qlen) \ + ((in == out)? (qlen - 1) : ((in > out)? \ + ((qlen - 1) - (in - out)) : (out - in - 1))) +#define ISP_QAVAIL(isp) \ + ISP_QFREE(isp->isp_reqidx, isp->isp_reqodx, RQUEST_QUEUE_LEN(isp)) + +#define ISP_ADD_REQUEST(isp, nxti) \ + MEMORYBARRIER(isp, SYNC_REQUEST, isp->isp_reqidx, QENTRY_LEN); \ + WRITE_REQUEST_QUEUE_IN_POINTER(isp, nxti); \ + isp->isp_reqidx = nxti + +/* + * SCSI Specific Host Adapter Parameters- per bus, per target + */ + +typedef struct { + u_int isp_gotdparms : 1, + isp_req_ack_active_neg : 1, + isp_data_line_active_neg: 1, + isp_cmd_dma_burst_enable: 1, + isp_data_dma_burst_enabl: 1, + isp_fifo_threshold : 3, + isp_ultramode : 1, + isp_diffmode : 1, + isp_lvdmode : 1, + isp_fast_mttr : 1, /* fast sram */ + isp_initiator_id : 4, + isp_async_data_setup : 4; + u_int16_t isp_selection_timeout; + u_int16_t isp_max_queue_depth; + u_int8_t isp_tag_aging; + u_int8_t isp_bus_reset_delay; + u_int8_t isp_retry_count; + u_int8_t isp_retry_delay; + struct { + u_int32_t + exc_throttle : 8, + : 1, + dev_enable : 1, /* ignored */ + dev_update : 1, + dev_refresh : 1, + actv_offset : 4, + goal_offset : 4, + nvrm_offset : 4; + u_int8_t actv_period; /* current sync period */ + u_int8_t goal_period; /* goal sync period */ + u_int8_t nvrm_period; /* nvram sync period */ + u_int16_t actv_flags; /* current device flags */ + u_int16_t goal_flags; /* goal device flags */ + u_int16_t nvrm_flags; /* nvram device flags */ + } isp_devparam[MAX_TARGETS]; +} sdparam; + +/* + * Device Flags + */ +#define DPARM_DISC 0x8000 +#define DPARM_PARITY 0x4000 +#define DPARM_WIDE 0x2000 +#define DPARM_SYNC 0x1000 +#define DPARM_TQING 0x0800 +#define DPARM_ARQ 0x0400 +#define DPARM_QFRZ 0x0200 +#define DPARM_RENEG 0x0100 +#define DPARM_NARROW 0x0080 +#define DPARM_ASYNC 0x0040 +#define DPARM_PPR 0x0020 +#define DPARM_DEFAULT (0xFF00 & ~DPARM_QFRZ) +#define DPARM_SAFE_DFLT (DPARM_DEFAULT & ~(DPARM_WIDE|DPARM_SYNC|DPARM_TQING)) + + +/* technically, not really correct, as they need to be rated based upon clock */ +#define ISP_80M_SYNCPARMS 0x0c09 +#define ISP_40M_SYNCPARMS 0x0c0a +#define ISP_20M_SYNCPARMS 0x0c0c +#define ISP_20M_SYNCPARMS_1040 0x080c +#define ISP_10M_SYNCPARMS 0x0c19 +#define ISP_08M_SYNCPARMS 0x0c25 +#define ISP_05M_SYNCPARMS 0x0c32 +#define ISP_04M_SYNCPARMS 0x0c41 + +/* + * Fibre Channel Specifics + */ +#define FL_PORT_ID 0x7e /* FL_Port Special ID */ +#define FC_PORT_ID 0x7f /* Fabric Controller Special ID */ +#define FC_SNS_ID 0x80 /* SNS Server Special ID */ + +/* #define ISP_USE_GA_NXT 1 */ /* Use GA_NXT with switches */ +#ifndef GA_NXT_MAX +#define GA_NXT_MAX 256 +#endif + +typedef struct { + u_int32_t isp_fwoptions : 16, + isp_gbspeed : 2, + isp_iid_set : 1, + loop_seen_once : 1, + isp_loopstate : 4, /* Current Loop State */ + isp_fwstate : 3, /* ISP F/W state */ + isp_gotdparms : 1, + isp_topo : 3, + isp_onfabric : 1; + u_int8_t isp_iid; /* 'initiator' id */ + u_int8_t isp_loopid; /* hard loop id */ + u_int8_t isp_alpa; /* ALPA */ + u_int32_t isp_portid; + volatile u_int16_t isp_lipseq; /* LIP sequence # */ + u_int16_t isp_fwattr; /* firmware attributes */ + u_int8_t isp_execthrottle; + u_int8_t isp_retry_delay; + u_int8_t isp_retry_count; + u_int8_t isp_reserved; + u_int16_t isp_maxalloc; + u_int16_t isp_maxfrmlen; + u_int64_t isp_nodewwn; + u_int64_t isp_portwwn; + /* + * Port Data Base. This is indexed by 'target', which is invariate. + * However, elements within can move around due to loop changes, + * so the actual loop ID passed to the F/W is in this structure. + * The first time the loop is seen up, loopid will match the index + * (except for fabric nodes which are above mapped above FC_SNS_ID + * and are completely virtual), but subsequent LIPs can cause things + * to move around. + */ + struct lportdb { + u_int32_t + port_type : 8, + loopid : 8, + fc4_type : 4, + last_fabric_dev : 1, + : 2, + relogin : 1, + force_logout : 1, + was_fabric_dev : 1, + fabric_dev : 1, + loggedin : 1, + roles : 2, + valid : 1; + u_int32_t portid; + u_int64_t node_wwn; + u_int64_t port_wwn; + } portdb[MAX_FC_TARG], tport[FC_PORT_ID]; + + /* + * Scratch DMA mapped in area to fetch Port Database stuff, etc. + */ + caddr_t isp_scratch; + isp_dma_addr_t isp_scdma; +#ifdef ISP_FW_CRASH_DUMP + u_int16_t *isp_dump_data; +#endif +} fcparam; + +#define FW_CONFIG_WAIT 0 +#define FW_WAIT_AL_PA 1 +#define FW_WAIT_LOGIN 2 +#define FW_READY 3 +#define FW_LOSS_OF_SYNC 4 +#define FW_ERROR 5 +#define FW_REINIT 6 +#define FW_NON_PART 7 + +#define LOOP_NIL 0 +#define LOOP_LIP_RCVD 1 +#define LOOP_PDB_RCVD 2 +#define LOOP_SCANNING_FABRIC 3 +#define LOOP_FSCAN_DONE 4 +#define LOOP_SCANNING_LOOP 5 +#define LOOP_LSCAN_DONE 6 +#define LOOP_SYNCING_PDB 7 +#define LOOP_READY 8 + +#define TOPO_NL_PORT 0 +#define TOPO_FL_PORT 1 +#define TOPO_N_PORT 2 +#define TOPO_F_PORT 3 +#define TOPO_PTP_STUB 4 + +/* + * Soft Structure per host adapter + */ +typedef struct ispsoftc { + /* + * Platform (OS) specific data + */ + struct isposinfo isp_osinfo; + + /* + * Pointer to bus specific functions and data + */ + struct ispmdvec * isp_mdvec; + + /* + * (Mostly) nonvolatile state. Board specific parameters + * may contain some volatile state (e.g., current loop state). + */ + + void * isp_param; /* type specific */ + u_int16_t isp_fwrev[3]; /* Loaded F/W revision */ + u_int16_t isp_romfw_rev[3]; /* PROM F/W revision */ + u_int16_t isp_maxcmds; /* max possible I/O cmds */ + u_int8_t isp_type; /* HBA Chip Type */ + u_int8_t isp_revision; /* HBA Chip H/W Revision */ + u_int32_t isp_maxluns; /* maximum luns supported */ + + u_int32_t isp_clock : 8, /* input clock */ + : 4, + isp_port : 1, /* 23XX only */ + isp_failed : 1, /* board failed */ + isp_open : 1, /* opened (ioctl) */ + isp_touched : 1, /* board ever seen? */ + isp_bustype : 1, /* SBus or PCI */ + isp_loaded_fw : 1, /* loaded firmware */ + isp_role : 2, /* roles supported */ + isp_dblev : 12; /* debug log mask */ + + u_int32_t isp_confopts; /* config options */ + + u_int16_t isp_rqstinrp; /* register for REQINP */ + u_int16_t isp_rqstoutrp; /* register for REQOUTP */ + u_int16_t isp_respinrp; /* register for RESINP */ + u_int16_t isp_respoutrp; /* register for RESOUTP */ + + /* + * Instrumentation + */ + u_int64_t isp_intcnt; /* total int count */ + u_int64_t isp_intbogus; /* spurious int count */ + u_int64_t isp_intmboxc; /* mbox completions */ + u_int64_t isp_intoasync; /* other async */ + u_int64_t isp_rsltccmplt; /* CMDs on result q */ + u_int64_t isp_fphccmplt; /* CMDs via fastpost */ + u_int16_t isp_rscchiwater; + u_int16_t isp_fpcchiwater; + + /* + * Volatile state + */ + + volatile u_int32_t + isp_obits : 8, /* mailbox command output */ + isp_mboxbsy : 1, /* mailbox command active */ + isp_state : 3, + isp_sendmarker : 2, /* send a marker entry */ + isp_update : 2, /* update parameters */ + isp_nactive : 16; /* how many commands active */ + volatile u_int16_t isp_reqodx; /* index of last ISP pickup */ + volatile u_int16_t isp_reqidx; /* index of next request */ + volatile u_int16_t isp_residx; /* index of next result */ + volatile u_int16_t isp_resodx; /* index of next result */ + volatile u_int16_t isp_rspbsy; + volatile u_int16_t isp_lasthdls; /* last handle seed */ + volatile u_int16_t isp_mboxtmp[MAX_MAILBOX]; + volatile u_int16_t isp_lastmbxcmd; /* last mbox command sent */ + volatile u_int16_t isp_mbxwrk0; + volatile u_int16_t isp_mbxwrk1; + volatile u_int16_t isp_mbxwrk2; + void * isp_mbxworkp; + + /* + * Active commands are stored here, indexed by handle functions. + */ + XS_T **isp_xflist; + + /* + * request/result queue pointers and dma handles for them. + */ + caddr_t isp_rquest; + caddr_t isp_result; + isp_dma_addr_t isp_rquest_dma; + isp_dma_addr_t isp_result_dma; +} ispsoftc_t; + +#define SDPARAM(isp) ((sdparam *) (isp)->isp_param) +#define FCPARAM(isp) ((fcparam *) (isp)->isp_param) + +/* + * ISP Driver Run States + */ +#define ISP_NILSTATE 0 +#define ISP_RESETSTATE 1 +#define ISP_INITSTATE 2 +#define ISP_RUNSTATE 3 + +/* + * ISP Configuration Options + */ +#define ISP_CFG_NORELOAD 0x80 /* don't download f/w */ +#define ISP_CFG_NONVRAM 0x40 /* ignore NVRAM */ +#define ISP_CFG_TWOGB 0x20 /* force 2GB connection (23XX only) */ +#define ISP_CFG_ONEGB 0x10 /* force 1GB connection (23XX only) */ +#define ISP_CFG_FULL_DUPLEX 0x01 /* Full Duplex (Fibre Channel only) */ +#define ISP_CFG_PORT_PREF 0x0C /* Mask for Port Prefs (2200 only) */ +#define ISP_CFG_LPORT 0x00 /* prefer {N/F}L-Port connection */ +#define ISP_CFG_NPORT 0x04 /* prefer {N/F}-Port connection */ +#define ISP_CFG_NPORT_ONLY 0x08 /* insist on {N/F}-Port connection */ +#define ISP_CFG_LPORT_ONLY 0x0C /* insist on {N/F}L-Port connection */ +#define ISP_CFG_OWNWWPN 0x100 /* override NVRAM wwpn */ +#define ISP_CFG_OWNWWNN 0x200 /* override NVRAM wwnn */ +#define ISP_CFG_OWNFSZ 0x400 /* override NVRAM frame size */ +#define ISP_CFG_OWNLOOPID 0x800 /* override NVRAM loopid */ +#define ISP_CFG_OWNEXCTHROTTLE 0x1000 /* override NVRAM execution throttle */ + +/* + * Prior to calling isp_reset for the first time, the outer layer + * should set isp_role to one of NONE, INITIATOR, TARGET, BOTH. + * + * If you set ISP_ROLE_NONE, the cards will be reset, new firmware loaded, + * NVRAM read, and defaults set, but any further initialization (e.g. + * INITIALIZE CONTROL BLOCK commands for 2X00 cards) won't be done. + * + * If INITIATOR MODE isn't set, attempts to run commands will be stopped + * at isp_start and completed with the moral equivalent of SELECTION TIMEOUT. + * + * If TARGET MODE is set, it doesn't mean that the rest of target mode support + * needs to be enabled, or will even work. What happens with the 2X00 cards + * here is that if you have enabled it with TARGET MODE as part of the ICB + * options, but you haven't given the f/w any ram resources for ATIOs or + * Immediate Notifies, the f/w just handles what it can and you never see + * anything. Basically, it sends a single byte of data (the first byte, + * which you can set as part of the INITIALIZE CONTROL BLOCK command) for + * INQUIRY, and sends back QUEUE FULL status for any other command. + * + */ +#define ISP_ROLE_NONE 0x0 +#define ISP_ROLE_INITIATOR 0x1 +#define ISP_ROLE_TARGET 0x2 +#define ISP_ROLE_BOTH (ISP_ROLE_TARGET|ISP_ROLE_INITIATOR) +#define ISP_ROLE_EITHER ISP_ROLE_BOTH +#ifndef ISP_DEFAULT_ROLES +#define ISP_DEFAULT_ROLES ISP_ROLE_INITIATOR +#endif + + +/* + * Firmware related defines + */ +#define ISP_CODE_ORG 0x1000 /* default f/w code start */ +#define ISP_CODE_ORG_2300 0x0800 /* ..except for 2300s */ +#define ISP_FW_REV(maj, min, mic) ((maj << 24) | (min << 16) | mic) +#define ISP_FW_MAJOR(code) ((code >> 24) & 0xff) +#define ISP_FW_MINOR(code) ((code >> 16) & 0xff) +#define ISP_FW_MICRO(code) ((code >> 8) & 0xff) +#define ISP_FW_REVX(xp) ((xp[0]<<24) | (xp[1] << 16) | xp[2]) +#define ISP_FW_MAJORX(xp) (xp[0]) +#define ISP_FW_MINORX(xp) (xp[1]) +#define ISP_FW_MICROX(xp) (xp[2]) +#define ISP_FW_NEWER_THAN(i, major, minor, micro) \ + (ISP_FW_REVX((i)->isp_fwrev) > ISP_FW_REV(major, minor, micro)) + +/* + * Bus (implementation) types + */ +#define ISP_BT_PCI 0 /* PCI Implementations */ +#define ISP_BT_SBUS 1 /* SBus Implementations */ + +/* + * If we have not otherwise defined SBus support away make sure + * it is defined here such that the code is included as default + */ +#ifndef ISP_SBUS_SUPPORTED +#define ISP_SBUS_SUPPORTED 1 +#endif + +/* + * Chip Types + */ +#define ISP_HA_SCSI 0xf +#define ISP_HA_SCSI_UNKNOWN 0x1 +#define ISP_HA_SCSI_1020 0x2 +#define ISP_HA_SCSI_1020A 0x3 +#define ISP_HA_SCSI_1040 0x4 +#define ISP_HA_SCSI_1040A 0x5 +#define ISP_HA_SCSI_1040B 0x6 +#define ISP_HA_SCSI_1040C 0x7 +#define ISP_HA_SCSI_1240 0x8 +#define ISP_HA_SCSI_1080 0x9 +#define ISP_HA_SCSI_1280 0xa +#define ISP_HA_SCSI_10160 0xb +#define ISP_HA_SCSI_12160 0xc +#define ISP_HA_FC 0xf0 +#define ISP_HA_FC_2100 0x10 +#define ISP_HA_FC_2200 0x20 +#define ISP_HA_FC_2300 0x30 +#define ISP_HA_FC_2312 0x40 + +#define IS_SCSI(isp) (isp->isp_type & ISP_HA_SCSI) +#define IS_1240(isp) (isp->isp_type == ISP_HA_SCSI_1240) +#define IS_1080(isp) (isp->isp_type == ISP_HA_SCSI_1080) +#define IS_1280(isp) (isp->isp_type == ISP_HA_SCSI_1280) +#define IS_10160(isp) (isp->isp_type == ISP_HA_SCSI_10160) +#define IS_12160(isp) (isp->isp_type == ISP_HA_SCSI_12160) + +#define IS_12X0(isp) (IS_1240(isp) || IS_1280(isp)) +#define IS_1X160(isp) (IS_10160(isp) || IS_12160(isp)) +#define IS_DUALBUS(isp) (IS_12X0(isp) || IS_12160(isp)) +#define IS_ULTRA2(isp) (IS_1080(isp) || IS_1280(isp) || IS_1X160(isp)) +#define IS_ULTRA3(isp) (IS_1X160(isp)) + +#define IS_FC(isp) ((isp)->isp_type & ISP_HA_FC) +#define IS_2100(isp) ((isp)->isp_type == ISP_HA_FC_2100) +#define IS_2200(isp) ((isp)->isp_type == ISP_HA_FC_2200) +#define IS_23XX(isp) ((isp)->isp_type >= ISP_HA_FC_2300) +#define IS_2300(isp) ((isp)->isp_type == ISP_HA_FC_2300) +#define IS_2312(isp) ((isp)->isp_type == ISP_HA_FC_2312) + +/* + * DMA cookie macros + */ +#ifdef ISP_DAC_SUPPORTRED +#define DMA_WD3(x) (((x) >> 48) & 0xffff) +#define DMA_WD2(x) (((x) >> 32) & 0xffff) +#else +#define DMA_WD3(x) 0 +#define DMA_WD2(x) 0 +#endif +#define DMA_WD1(x) (((x) >> 16) & 0xffff) +#define DMA_WD0(x) (((x) & 0xffff)) + +/* + * Core System Function Prototypes + */ + +/* + * Reset Hardware. Totally. Assumes that you'll follow this with + * a call to isp_init. + */ +void isp_reset(struct ispsoftc *); + +/* + * Initialize Hardware to known state + */ +void isp_init(struct ispsoftc *); + +/* + * Reset the ISP and call completion for any orphaned commands. + */ +void isp_reinit(struct ispsoftc *); + +#ifdef ISP_FW_CRASH_DUMP +/* + * Dump firmware entry point. + */ +void isp_fw_dump(struct ispsoftc *isp); +#endif + +/* + * Internal Interrupt Service Routine + * + * The outer layers do the spade work to get the appropriate status register, + * semaphore register and first mailbox register (if appropriate). This also + * means that most spurious/bogus interrupts not for us can be filtered first. + */ +void isp_intr(struct ispsoftc *, u_int16_t, u_int16_t, u_int16_t); + + +/* + * Command Entry Point- Platform Dependent layers call into this + */ +int isp_start(XS_T *); +/* these values are what isp_start returns */ +#define CMD_COMPLETE 101 /* command completed */ +#define CMD_EAGAIN 102 /* busy- maybe retry later */ +#define CMD_QUEUED 103 /* command has been queued for execution */ +#define CMD_RQLATER 104 /* requeue this command later */ + +/* + * Command Completion Point- Core layers call out from this with completed cmds + */ +void isp_done(XS_T *); + +/* + * Platform Dependent to External to Internal Control Function + * + * Assumes locks are held on entry. You should note that with many of + * these commands and locks may be released while this is occurring. + * + * A few notes about some of these functions: + * + * ISPCTL_FCLINK_TEST tests to make sure we have good fibre channel link. + * The argument is a pointer to an integer which is the time, in microseconds, + * we should wait to see whether we have good link. This test, if successful, + * lets us know our connection topology and our Loop ID/AL_PA and so on. + * You can't get anywhere without this. + * + * ISPCTL_SCAN_FABRIC queries the name server (if we're on a fabric) for + * all entities using the FC Generic Services subcommand GET ALL NEXT. + * For each found entity, an ISPASYNC_FABRICDEV event is generated (see + * below). + * + * ISPCTL_SCAN_LOOP does a local loop scan. This is only done if the connection + * topology is NL or FL port (private or public loop). Since the Qlogic f/w + * 'automatically' manages local loop connections, this function essentially + * notes the arrival, departure, and possible shuffling around of local loop + * entities. Thus for each arrival and departure this generates an isp_async + * event of ISPASYNC_PROMENADE (see below). + * + * ISPCTL_PDB_SYNC is somewhat misnamed. It actually is the final step, in + * order, of ISPCTL_FCLINK_TEST, ISPCTL_SCAN_FABRIC, and ISPCTL_SCAN_LOOP. + * The main purpose of ISPCTL_PDB_SYNC is to complete management of logging + * and logging out of fabric devices (if one is on a fabric) and then marking + * the 'loop state' as being ready to now be used for sending commands to + * devices. Originally fabric name server and local loop scanning were + * part of this function. It's now been separated to allow for finer control. + */ +typedef enum { + ISPCTL_RESET_BUS, /* Reset Bus */ + ISPCTL_RESET_DEV, /* Reset Device */ + ISPCTL_ABORT_CMD, /* Abort Command */ + ISPCTL_UPDATE_PARAMS, /* Update Operating Parameters (SCSI) */ + ISPCTL_FCLINK_TEST, /* Test FC Link Status */ + ISPCTL_SCAN_FABRIC, /* (Re)scan Fabric Name Server */ + ISPCTL_SCAN_LOOP, /* (Re)scan Local Loop */ + ISPCTL_PDB_SYNC, /* Synchronize Port Database */ + ISPCTL_SEND_LIP, /* Send a LIP */ + ISPCTL_GET_POSMAP, /* Get FC-AL position map */ + ISPCTL_RUN_MBOXCMD, /* run a mailbox command */ + ISPCTL_TOGGLE_TMODE /* toggle target mode */ +} ispctl_t; +int isp_control(struct ispsoftc *, ispctl_t, void *); + + +/* + * Platform Dependent to Internal to External Control Function + * (each platform must provide such a function) + * + * Assumes locks are held. + * + * A few notes about some of these functions: + * + * ISPASYNC_CHANGE_NOTIFY notifies the outer layer that a change has + * occurred that invalidates the list of fabric devices known and/or + * the list of known loop devices. The argument passed is a pointer + * whose values are defined below (local loop change, name server + * change, other). 'Other' may simply be a LIP, or a change in + * connection topology. + * + * ISPASYNC_FABRIC_DEV announces the next element in a list of + * fabric device names we're getting out of the name server. The + * argument points to a GET ALL NEXT response structure. The list + * is known to terminate with an entry that refers to ourselves. + * One of the main purposes of this function is to allow outer + * layers, which are OS dependent, to set policy as to which fabric + * devices might actually be logged into (and made visible) later + * at ISPCTL_PDB_SYNC time. Since there's a finite number of fabric + * devices that we can log into (256 less 3 'reserved' for F-port + * topologies), and fabrics can grow up to 8 million or so entries + * (24 bits of Port Address, less a wad of reserved spaces), clearly + * we had better let the OS determine login policy. + * + * ISPASYNC_PROMENADE has an argument that is a pointer to an integer which + * is an index into the portdb in the softc ('target'). Whether that entry's + * valid tag is set or not says whether something has arrived or departed. + * The name refers to a favorite pastime of many city dwellers- watching + * people come and go, talking of Michaelangelo, and so on.. + * + * ISPASYNC_UNHANDLED_RESPONSE gives outer layers a chance to parse a + * response queue entry not otherwise handled. The outer layer should + * return non-zero if it handled it. The 'arg' points to an unmassaged + * response queue entry. + */ + +typedef enum { + ISPASYNC_NEW_TGT_PARAMS, /* New Target Parameters Negotiated */ + ISPASYNC_BUS_RESET, /* Bus Was Reset */ + ISPASYNC_LOOP_DOWN, /* FC Loop Down */ + ISPASYNC_LOOP_UP, /* FC Loop Up */ + ISPASYNC_LIP, /* LIP Received */ + ISPASYNC_LOOP_RESET, /* Loop Reset Received */ + ISPASYNC_CHANGE_NOTIFY, /* FC Change Notification */ + ISPASYNC_FABRIC_DEV, /* FC Fabric Device Arrival */ + ISPASYNC_PROMENADE, /* FC Objects coming && going */ + ISPASYNC_TARGET_MESSAGE, /* target message */ + ISPASYNC_TARGET_EVENT, /* target asynchronous event */ + ISPASYNC_TARGET_ACTION, /* other target command action */ + ISPASYNC_CONF_CHANGE, /* Platform Configuration Change */ + ISPASYNC_UNHANDLED_RESPONSE, /* Unhandled Response Entry */ + ISPASYNC_FW_CRASH, /* Firmware has crashed */ + ISPASYNC_FW_DUMPED, /* Firmware crashdump taken */ + ISPASYNC_FW_RESTARTED /* Firmware has been restarted */ +} ispasync_t; +int isp_async(struct ispsoftc *, ispasync_t, void *); + +#define ISPASYNC_CHANGE_PDB ((void *) 0) +#define ISPASYNC_CHANGE_SNS ((void *) 1) +#define ISPASYNC_CHANGE_OTHER ((void *) 2) + +/* + * Platform Dependent Error and Debug Printout + */ +#ifdef __GNUC__ +void isp_prt(struct ispsoftc *, int level, const char *, ...) + __attribute__((__format__(__printf__,3,4))); +#else +void isp_prt(struct ispsoftc *, int level, const char *, ...); +#endif + +#define ISP_LOGALL 0x0 /* log always */ +#define ISP_LOGCONFIG 0x1 /* log configuration messages */ +#define ISP_LOGINFO 0x2 /* log informational messages */ +#define ISP_LOGWARN 0x4 /* log warning messages */ +#define ISP_LOGERR 0x8 /* log error messages */ +#define ISP_LOGDEBUG0 0x10 /* log simple debug messages */ +#define ISP_LOGDEBUG1 0x20 /* log intermediate debug messages */ +#define ISP_LOGDEBUG2 0x40 /* log most debug messages */ +#define ISP_LOGDEBUG3 0x80 /* log high frequency debug messages */ +#define ISP_LOGDEBUG4 0x100 /* log high frequency debug messages */ +#define ISP_LOGTDEBUG0 0x200 /* log simple debug messages (target mode) */ +#define ISP_LOGTDEBUG1 0x400 /* log intermediate debug messages (target) */ +#define ISP_LOGTDEBUG2 0x800 /* log all debug messages (target) */ + +/* + * Each Platform provides it's own isposinfo substructure of the ispsoftc + * defined above. + * + * Each platform must also provide the following macros/defines: + * + * + * INLINE - platform specific define for 'inline' functions + * + * ISP_DAC_SUPPORTED - Is DAC (Dual Address Cycle) is supported? + * Basically means whether or not DMA for PCI + * PCI cards (Ultra2 or better or FC) works + * above 4GB. + * + * ISP2100_SCRLEN - length for the Fibre Channel scratch DMA area + * + * MEMZERO(dst, src) platform zeroing function + * MEMCPY(dst, src, count) platform copying function + * SNPRINTF(buf, bufsize, fmt, ...) snprintf + * USEC_DELAY(usecs) microsecond spindelay function + * USEC_SLEEP(isp, usecs) microsecond sleep function + * + * NANOTIME_T nanosecond time type + * + * GET_NANOTIME(NANOTIME_T *) get current nanotime. + * + * GET_NANOSEC(NANOTIME_T *) get u_int64_t from NANOTIME_T + * + * NANOTIME_SUB(NANOTIME_T *, NANOTIME_T *) + * subtract two NANOTIME_T values + * + * + * MAXISPREQUEST(struct ispsoftc *) maximum request queue size + * for this particular board type + * + * MEMORYBARRIER(struct ispsoftc *, barrier_type, offset, size) + * + * Function/Macro the provides memory synchronization on + * various objects so that the ISP's and the system's view + * of the same object is consistent. + * + * MBOX_ACQUIRE(struct ispsoftc *) acquire lock on mailbox regs + * MBOX_WAIT_COMPLETE(struct ispsoftc *) wait for mailbox cmd to be done + * MBOX_NOTIFY_COMPLETE(struct ispsoftc *) notification of mbox cmd donee + * MBOX_RELEASE(struct ispsoftc *) release lock on mailbox regs + * + * FC_SCRATCH_ACQUIRE(struct ispsoftc *) acquire lock on FC scratch area + * FC_SCRATCH_RELEASE(struct ispsoftc *) acquire lock on FC scratch area + * + * SCSI_GOOD SCSI 'Good' Status + * SCSI_CHECK SCSI 'Check Condition' Status + * SCSI_BUSY SCSI 'Busy' Status + * SCSI_QFULL SCSI 'Queue Full' Status + * + * XS_T Platform SCSI transaction type (i.e., command for HBA) + * XS_ISP(xs) gets an instance out of an XS_T + * XS_CHANNEL(xs) gets the channel (bus # for DUALBUS cards) "" + * XS_TGT(xs) gets the target "" + * XS_LUN(xs) gets the lun "" + * XS_CDBP(xs) gets a pointer to the scsi CDB "" + * XS_CDBLEN(xs) gets the CDB's length "" + * XS_XFRLEN(xs) gets the associated data transfer length "" + * XS_TIME(xs) gets the time (in milliseconds) for this command + * XS_RESID(xs) gets the current residual count + * XS_STSP(xs) gets a pointer to the SCSI status byte "" + * XS_SNSP(xs) gets a pointer to the associate sense data + * XS_SNSLEN(xs) gets the length of sense data storage + * XS_SNSKEY(xs) dereferences XS_SNSP to get the current stored Sense Key + * XS_TAG_P(xs) predicate of whether this command should be tagged + * XS_TAG_TYPE(xs) which type of tag to use + * XS_SETERR(xs) set error state + * + * HBA_NOERROR command has no erros + * HBA_BOTCH hba botched something + * HBA_CMDTIMEOUT command timed out + * HBA_SELTIMEOUT selection timed out (also port logouts for FC) + * HBA_TGTBSY target returned a BUSY status + * HBA_BUSRESET bus reset destroyed command + * HBA_ABORTED command was aborted (by request) + * HBA_DATAOVR a data overrun was detected + * HBA_ARQFAIL Automatic Request Sense failed + * + * XS_ERR(xs) return current error state + * XS_NOERR(xs) there is no error currently set + * XS_INITERR(xs) initialize error state + * + * XS_SAVE_SENSE(xs, sp) save sense data + * + * XS_SET_STATE_STAT(isp, sp, xs) platform dependent interpreter of + * response queue entry status bits + * + * + * DEFAULT_IID(struct ispsoftc *) Default SCSI initiator ID + * DEFAULT_LOOPID(struct ispsoftc *) Default FC Loop ID + * DEFAULT_NODEWWN(struct ispsoftc *) Default Node WWN + * DEFAULT_PORTWWN(struct ispsoftc *) Default Port WWN + * DEFAULT_FRAMESIZE(struct ispsoftc *) Default Frame Size + * DEFAULT_EXEC_THROTTLE(struct ispsoftc *) Default Execution Throttle + * These establish reasonable defaults for each platform. + * These must be available independent of card NVRAM and are + * to be used should NVRAM not be readable. + * + * ISP_NODEWWN(struct ispsoftc *) FC Node WWN to use + * ISP_PORTWWN(struct ispsoftc *) FC Port WWN to use + * + * These are to be used after NVRAM is read. The tags + * in fcparam.isp_{node,port}wwn reflect the values + * read from NVRAM (possibly corrected for card botches). + * Each platform can take that information and override + * it or ignore and return the Node and Port WWNs to be + * used when sending the Qlogic f/w the Initialization Control + * Block. + * + * (XXX these do endian specific transformations- in transition XXX) + * + * ISP_IOXPUT_8(struct ispsoftc *, u_int8_t srcval, u_int8_t *dstptr) + * ISP_IOXPUT_16(struct ispsoftc *, u_int16_t srcval, u_int16_t *dstptr) + * ISP_IOXPUT_32(struct ispsoftc *, u_int32_t srcval, u_int32_t *dstptr) + * + * ISP_IOXGET_8(struct ispsoftc *, u_int8_t *srcptr, u_int8_t dstrval) + * ISP_IOXGET_16(struct ispsoftc *, u_int16_t *srcptr, u_int16_t dstrval) + * ISP_IOXGET_32(struct ispsoftc *, u_int32_t *srcptr, u_int32_t dstrval) + * + * ISP_SWIZZLE_NVRAM_WORD(struct ispsoftc *, u_int16_t *) + */ + +#endif /* _ISPVAR_H */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/Config.in 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,47 @@ +# %W% +# +# Copyright (c) 2000 by Matthew Jacob +# +# This software is free software; you can redistribute it and/or +# modify it under the terms of the GNU Library General Public +# License as published by the Free Software Foundation; version 2. +# +# This software is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Library General Public License for more details. +# +# You should have received a copy of the GNU Library General Public +# License along with this software; if not, write to the Free +# Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# The author may be reached via electronic communications at +# +# mjacob@feral.com +# +# or, via United States Postal Address +# +# Matthew Jacob +# Feral Software +# PMB #825 +# 5214-F Diamond Hts. Blvd +# San Francisco, CA, 94131 +# +# +if [ "$CONFIG_PCI" = "y" ]; then + dep_tristate 'Single Driver Qlogic FC/SCSI support' CONFIG_SCSI_NEWISP $CONFIG_SCSI + if [ "$CONFIG_SCSI_NEWISP" != "n" ]; then +# +# Eventually we'll put some more options in. +# + if [ "$CONFIG_SCSI_QLOGIC_ISP" = "y" ]; then + define_tristate CONFIG_SCSI_QLOGIC_ISP n + fi + if [ "$CONFIG_SCSI_QLOGIC_FC" = "y" ]; then + define_tristate CONFIG_SCSI_QLOGIC_FC n + fi + if [ "$CONFIG_SCSI_QLOGIC_1280" = "y" ]; then + define_tristate CONFIG_SCSI_QLOGIC_1280 n + fi + fi +fi --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/firmware/asm_1000.h 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,3224 @@ +/* @(#)asm_1000.h 1.2 */ +/* + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Qlogic, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted provided + * that the following conditions are met: + * 1. Redistribution of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistribution in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ISP_TARGET_MODE +/* + * Firmware Version 1.37.00 (11:28 Aug 28, 2000) + */ +static const u_int16_t isp_1000_risc_code[] = { + 0x0078, 0x1041, 0x0000, 0x2757, 0x0000, 0x12ff, 0x2043, 0x4f50, + 0x5952, 0x4947, 0x4854, 0x2031, 0x3939, 0x312c, 0x3139, 0x3932, + 0x2c31, 0x3939, 0x332c, 0x3139, 0x3934, 0x2051, 0x4c4f, 0x4749, + 0x4320, 0x434f, 0x5250, 0x4f52, 0x4154, 0x494f, 0x4e00, 0x2049, + 0x5350, 0x3130, 0x3030, 0x2046, 0x6972, 0x6d77, 0x6172, 0x6520, + 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, 0x312e, 0x3337, 0x2020, + 0x2043, 0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, 0x3135, + 0x2050, 0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2000, 0x3030, + 0x2024, 0x20b9, 0x1212, 0x20c1, 0x0008, 0x2071, 0x0010, 0x70c3, + 0x0004, 0x20c9, 0x5cff, 0x2089, 0x10ee, 0x70c7, 0x4953, 0x70cb, + 0x5020, 0x70cf, 0x2020, 0x70d3, 0x0001, 0x3f00, 0x70d6, 0x2031, + 0x0030, 0x2079, 0x3800, 0x7863, 0x0000, 0x2fa0, 0x2009, 0x031b, + 0x2011, 0x0000, 0x20a9, 0x0040, 0x42a4, 0x8109, 0x00c0, 0x1062, + 0x789b, 0x0101, 0x780b, 0x0002, 0x780f, 0x0002, 0x784f, 0x0bb8, + 0x2009, 0x3835, 0x200b, 0x0003, 0x78bb, 0x0000, 0x78bf, 0x0000, + 0x78c3, 0x0000, 0x2069, 0x3840, 0x00a8, 0x1085, 0x681b, 0x003c, + 0x2009, 0x1313, 0x21b8, 0x0078, 0x1087, 0x681b, 0x0028, 0x6807, + 0x0007, 0x680b, 0x00fa, 0x680f, 0x0008, 0x6813, 0x0005, 0x681f, + 0x0000, 0x6823, 0x0006, 0x6817, 0x0008, 0x6827, 0x0000, 0x2069, + 0x3a80, 0x2011, 0x0020, 0x2009, 0x0010, 0x680b, 0x0c19, 0x680f, + 0x0019, 0x6803, 0xdd00, 0x6807, 0x001a, 0x6a1a, 0x2d00, 0xa0e8, + 0x0008, 0xa290, 0x0004, 0x8109, 0x00c0, 0x109d, 0x2069, 0x3b00, + 0x2009, 0x0002, 0x20a9, 0x0100, 0x683f, 0x0000, 0x2001, 0x0008, + 0x8007, 0x6832, 0x6837, 0x000a, 0x680b, 0x0040, 0x6817, 0x0100, + 0x681f, 0x0064, 0xade8, 0x0010, 0x0070, 0x10c8, 0x0078, 0x10b4, + 0x8109, 0x00c0, 0x10b2, 0x1078, 0x1b64, 0x1078, 0x31c0, 0x1078, + 0x1747, 0x1078, 0x368b, 0x3200, 0xa085, 0x000d, 0x2090, 0x70c3, + 0x0000, 0x0090, 0x10e2, 0x70c0, 0xa086, 0x0002, 0x00c0, 0x10e2, + 0x1078, 0x11e0, 0x1078, 0x1112, 0x1078, 0x18f2, 0x1078, 0x1aaf, + 0x1078, 0x34fd, 0x1078, 0x184d, 0x0078, 0x10e2, 0x10f6, 0x10f8, + 0x1d05, 0x1d05, 0x321e, 0x321e, 0x1d05, 0x1d05, 0x0078, 0x10f6, + 0x0078, 0x10f8, 0x0078, 0x10fa, 0x0078, 0x10fc, 0x7008, 0x800c, + 0x00c8, 0x110d, 0x7007, 0x0002, 0xa08c, 0x000c, 0x00c0, 0x110e, + 0x8004, 0x8004, 0x00c8, 0x110d, 0x087a, 0x097a, 0x70c3, 0x4002, + 0x0078, 0x11e3, 0x7814, 0xa005, 0x00c0, 0x111a, 0x0010, 0x1156, + 0x0078, 0x1155, 0x2009, 0x3868, 0x2104, 0xa005, 0x00c0, 0x1155, + 0x7814, 0xa086, 0x0001, 0x00c0, 0x1127, 0x1078, 0x15ae, 0x7817, + 0x0000, 0x2009, 0x386f, 0x2104, 0xa065, 0x0040, 0x1143, 0x2009, + 0x386a, 0x211c, 0x8108, 0x2114, 0x8108, 0x2104, 0xa210, 0xa399, + 0x0000, 0x2009, 0x0018, 0x6083, 0x0103, 0x1078, 0x16d7, 0x00c0, + 0x114f, 0x1078, 0x173e, 0x2009, 0x386f, 0x200b, 0x0000, 0x2009, + 0x3869, 0x2104, 0x200b, 0x0000, 0xa005, 0x0040, 0x1153, 0x2001, + 0x4005, 0x0078, 0x11e2, 0x0078, 0x11e0, 0x007c, 0x2061, 0x0000, + 0x6018, 0xa084, 0x0001, 0x0040, 0x115e, 0x007c, 0x70c3, 0x0000, + 0x70c7, 0x0000, 0x70cb, 0x0000, 0x70cf, 0x0000, 0x70c0, 0xa0bc, + 0xffc0, 0x00c0, 0x11ae, 0x2038, 0x0079, 0x116e, 0x11e0, 0x122e, + 0x11fc, 0x122e, 0x127f, 0x127f, 0x11f3, 0x1608, 0x128a, 0x11ef, + 0x1200, 0x1202, 0x1204, 0x1206, 0x160d, 0x11ef, 0x1292, 0x12ba, + 0x15bc, 0x1602, 0x1208, 0x14e3, 0x1505, 0x151f, 0x1548, 0x149c, + 0x14aa, 0x14be, 0x14d2, 0x1357, 0x1332, 0x12e2, 0x12e9, 0x12ee, + 0x12f3, 0x12f9, 0x12fe, 0x1303, 0x1308, 0x130d, 0x1311, 0x1326, + 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x1363, 0x136c, 0x137b, + 0x13a1, 0x13ab, 0x13b2, 0x13d8, 0x13e7, 0x13f6, 0x1408, 0x147a, + 0x11ef, 0x148a, 0x11ef, 0x11ef, 0x11ef, 0x1491, 0xa0bc, 0xffa0, + 0x00c0, 0x11ef, 0x2038, 0xa084, 0x001f, 0x0079, 0x11b7, 0x11ef, + 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, + 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x1665, 0x1674, 0x11ef, + 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, 0x11ef, + 0x11ef, 0x16b3, 0x16bd, 0x16c1, 0x16cf, 0x167f, 0x169c, 0x72ca, + 0x71c6, 0x2001, 0x4006, 0x0078, 0x11e2, 0x73ce, 0x72ca, 0x71c6, + 0x2001, 0x4000, 0x70c2, 0x2061, 0x0000, 0x601b, 0x0001, 0x2091, + 0x5000, 0x2091, 0x4080, 0x007c, 0x71c6, 0x0078, 0x11e2, 0x70c3, + 0x4001, 0x0078, 0x11e3, 0x2099, 0x0041, 0x20a1, 0x0041, 0x20a9, + 0x0005, 0x53a3, 0x0078, 0x11e0, 0x70c4, 0x70c3, 0x0004, 0x007a, + 0x0078, 0x11e0, 0x0078, 0x11e0, 0x0078, 0x11e0, 0x0078, 0x11e0, + 0x2091, 0x8000, 0x70c3, 0x0000, 0x70c7, 0x4953, 0x70cb, 0x5020, + 0x70cf, 0x2020, 0x70d3, 0x0001, 0x3f00, 0x70d6, 0x2079, 0x0000, + 0x781b, 0x0001, 0x2031, 0x0030, 0x2059, 0x1000, 0x2029, 0x0457, + 0x2051, 0x0470, 0x2061, 0x0472, 0x20b9, 0xffff, 0x20c1, 0x0000, + 0x2091, 0x5000, 0x2091, 0x4080, 0x0078, 0x0455, 0x71d0, 0x72c8, + 0x73cc, 0x70c4, 0x20a0, 0x2098, 0x2031, 0x0030, 0x81ff, 0x0040, + 0x11e0, 0x7007, 0x0004, 0x731a, 0x721e, 0x2051, 0x0012, 0x2049, + 0x125d, 0x2041, 0x11e0, 0x7003, 0x0002, 0xa786, 0x0001, 0x00c0, + 0x124f, 0x2049, 0x126b, 0x2041, 0x1277, 0x7003, 0x0003, 0x7017, + 0x0000, 0x810b, 0x7112, 0x00c8, 0x1257, 0x7017, 0x0001, 0x7007, + 0x0001, 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0x2069, 0x3840, 0x6800, 0xa005, + 0x0040, 0x35d6, 0x683c, 0xac06, 0x0040, 0x3640, 0x6710, 0x6fb6, + 0x1078, 0x1758, 0x6808, 0xa084, 0x0020, 0x00c0, 0x363d, 0x2009, + 0x382b, 0x2104, 0xa005, 0x0040, 0x35e9, 0x6023, 0x0001, 0x0078, + 0x363d, 0x6808, 0xa084, 0xffef, 0xa085, 0x0021, 0x6017, 0x0006, + 0x60b0, 0xa084, 0x3f00, 0x601a, 0x601c, 0xa084, 0x00ff, 0xa085, + 0x0060, 0x601e, 0x6000, 0x2042, 0x6710, 0x6fb6, 0x1078, 0x1758, + 0x6818, 0xa005, 0x0040, 0x3606, 0x8001, 0x681a, 0x6808, 0xa084, + 0xffef, 0x680a, 0x6810, 0x8001, 0x00d0, 0x3610, 0x1078, 0x1ce7, + 0x6812, 0x602f, 0x0000, 0x602b, 0x0000, 0x2c68, 0x1078, 0x18b6, + 0x2069, 0x3840, 0x6710, 0xa784, 0x0f00, 0x68b6, 0x2001, 0x0002, + 0x1078, 0x1b44, 0x2041, 0x0021, 0x2049, 0x0005, 0x2051, 0x0030, + 0x1078, 0x1765, 0x2011, 0x3835, 0x2214, 0x6a3e, 0x8738, 0xa784, + 0x001f, 0x00c0, 0x3622, 0x2009, 0x382b, 0x200b, 0x0008, 0x2009, + 0x382c, 0x2069, 0x3840, 0x68b4, 0x200a, 0x2091, 0x8001, 0x007c, + 0x2009, 0x384f, 0x2164, 0x2069, 0x0100, 0x1078, 0x1c97, 0x6017, + 0x0006, 0x6858, 0xa084, 0x3f00, 0x601a, 0x601c, 0xa084, 0x00ff, + 0xa085, 0x0048, 0x601e, 0x602f, 0x0000, 0x602b, 0x0000, 0x6830, + 0xa084, 0x0040, 0x0040, 0x367c, 0x684b, 0x0004, 0x20a9, 0x0014, + 0x6848, 0xa084, 0x0004, 0x0040, 0x3669, 0x0070, 0x3669, 0x0078, + 0x3660, 0x684b, 0x0009, 0x20a9, 0x0014, 0x6848, 0xa084, 0x0001, + 0x0040, 0x3676, 0x0070, 0x3676, 0x0078, 0x366d, 0x20a9, 0x00fa, + 0x0070, 0x367c, 0x0078, 0x3678, 0x6808, 0xa084, 0xfffd, 0x680a, + 0x681b, 0x0046, 0x2009, 0x3868, 0x200b, 0x0007, 0x784c, 0x784a, + 0x2091, 0x8001, 0x007c, 0x2079, 0x3800, 0x1078, 0x36de, 0x1078, + 0x36a6, 0x1078, 0x36b4, 0x1078, 0x36c9, 0x1078, 0x36f3, 0x2009, + 0x3833, 0x200b, 0x0000, 0x2009, 0x3834, 0x200b, 0x0000, 0x7833, + 0x0000, 0x7847, 0x0000, 0x784b, 0x0000, 0x007c, 0x2019, 0x0003, + 0x2011, 0x3846, 0x2204, 0xa086, 0x003c, 0x0040, 0x36b1, 0x2019, + 0x0002, 0x7b2a, 0x7b2e, 0x007c, 0x2019, 0x0030, 0x2011, 0x3846, + 0x2204, 0xa086, 0x0032, 0x0040, 0x36c6, 0x2019, 0x0039, 0x2204, + 0xa086, 0x003c, 0x0040, 0x36c6, 0x2019, 0x0027, 0x7b36, 0x7b3a, + 0x007c, 0x2019, 0x000f, 0x2011, 0x3846, 0x2204, 0xa086, 0x003c, + 0x0040, 0x36db, 0x2019, 0x000d, 0x2204, 0xa086, 0x0032, 0x0040, + 0x36db, 0x2019, 0x000a, 0x7b3e, 0x7b42, 0x007c, 0x2019, 0x2faf, + 0x2011, 0x3846, 0x2204, 0xa086, 0x0032, 0x0040, 0x36f0, 0x2019, + 0x3971, 0x2204, 0xa086, 0x003c, 0x0040, 0x36f0, 0x2019, 0x2626, + 0x7b22, 0x7b26, 0x007c, 0x2019, 0x0001, 0x2011, 0x3846, 0x2204, + 0xa086, 0x003c, 0x0040, 0x36fe, 0x2019, 0x0001, 0x017e, 0x2009, + 0x3831, 0x230a, 0x2009, 0x3832, 0x230a, 0x017f, 0x007c, 0x2009, + 0x3831, 0x2104, 0x8001, 0x200a, 0xa005, 0x00c0, 0x3755, 0x2009, + 0x3832, 0x2104, 0x2009, 0x3831, 0x200a, 0x2009, 0x3833, 0x2104, + 0xa005, 0x00c0, 0x371d, 0x2001, 0x0200, 0x8001, 0x200a, 0x8003, + 0x8003, 0x8003, 0x8003, 0xa090, 0x3b00, 0x2208, 0xa298, 0x0002, + 0x2304, 0xa084, 0x0200, 0x0040, 0x3755, 0xa290, 0x000e, 0x2204, + 0xa005, 0x0040, 0x3740, 0x8001, 0x0040, 0x3740, 0x8001, 0x0040, + 0x3740, 0x8001, 0x0040, 0x3740, 0x8001, 0x2012, 0x00c0, 0x3755, + 0x2012, 0x2304, 0xa084, 0xfdff, 0xa085, 0x0400, 0x201a, 0xa188, + 0x000c, 0x2104, 0x007e, 0xa084, 0x00ff, 0x8001, 0x027f, 0xa294, + 0xff00, 0xa205, 0x200a, 0x1078, 0x1b49, 0x007c, 0x6ed0 +}; +#else +/* + * Flakey, not quite functional, target mode code for ISP1000 + * hacked out of PCI 7.55 initiator/target mode code. + */ +static const u_int16_t isp_1000_risc_code[] = { + 0x0078, 0x103a, 0x0000, 0x3c1f, 0x0000, 0x2043, 0x4f50, 0x5952, + 0x4947, 0x4854, 0x2031, 0x3939, 0x3520, 0x514c, 0x4f47, 0x4943, + 0x2043, 0x4f52, 0x504f, 0x5241, 0x5449, 0x4f4e, 0x2049, 0x5350, + 0x3130, 0x3030, 0x2049, 0x2f54, 0x2046, 0x6972, 0x6d77, 0x6172, + 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, 0x372e, 0x3535, + 0x2020, 0x2043, 0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, + 0x3030, 0x2050, 0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2020, + 0x3031, 0x2024, 0x3700, 0xa086, 0xffff, 0x0040, 0x1043, 0x2079, + 0x4d00, 0x7803, 0x0001, 0x20c1, 0x0008, 0x2071, 0x0010, 0x70c3, + 0x0004, 0x20c9, 0x73ff, 0x2089, 0x116f, 0x70c7, 0x4953, 0x70cb, + 0x5020, 0x70cf, 0x2020, 0x70d3, 0x0007, 0x3f00, 0x70d6, 0x20c1, + 0x0008, 0x2019, 0x0000, 0x2009, 0xfeff, 0x2100, 0x200b, 0xa5a5, + 0xa1ec, 0x7fff, 0x2d64, 0x206b, 0x0a0a, 0xaddc, 0x3fff, 0x2b54, + 0x205b, 0x5050, 0x2114, 0xa286, 0xa5a5, 0x0040, 0x10b5, 0xa386, + 0x000f, 0x0040, 0x107b, 0x2c6a, 0x2a5a, 0x20c1, 0x0000, 0x2019, + 0x000f, 0x0078, 0x105b, 0x2c6a, 0x2a5a, 0x20c1, 0x0008, 0x2009, + 0x7fff, 0x2148, 0x2944, 0x204b, 0x0a0a, 0xa9bc, 0x3fff, 0x2734, + 0x203b, 0x5050, 0x2114, 0xa286, 0x0a0a, 0x0040, 0x109f, 0x284a, + 0x263a, 0x20c1, 0x0004, 0x2009, 0x3fff, 0x2134, 0x200b, 0x5050, + 0x2114, 0xa286, 0x5050, 0x0040, 0x10a0, 0x0078, 0x1177, 0x284a, + 0x263a, 0x98c0, 0xa188, 0x1000, 0x212c, 0x200b, 0xa5a5, 0x2114, + 0xa286, 0xa5a5, 0x0040, 0x10b2, 0x250a, 0xa18a, 0x1000, 0x98c1, + 0x0078, 0x10b7, 0x250a, 0x0078, 0x10b7, 0x2c6a, 0x2a5a, 0x2130, + 0xa18a, 0x0040, 0x2128, 0xa1a2, 0x4d00, 0x8424, 0x8424, 0x8424, + 0x8424, 0x8424, 0x8424, 0xa192, 0x7400, 0x2009, 0x0000, 0x2001, + 0x0031, 0x1078, 0x1bd8, 0x2218, 0x2079, 0x4d00, 0x2fa0, 0x2408, + 0x2011, 0x0000, 0x20a9, 0x0040, 0x42a4, 0x8109, 0x00c0, 0x10d2, + 0x7ef2, 0x8528, 0x7de6, 0x7cea, 0x7bee, 0x7883, 0x0000, 0x2031, + 0x0030, 0x78cf, 0x0101, 0x780b, 0x0002, 0x780f, 0x0002, 0x784f, + 0x0003, 0x2069, 0x4d40, 0x00a8, 0x10f1, 0x681b, 0x003c, 0x0078, + 0x10f3, 0x681b, 0x0028, 0x6807, 0x0007, 0x680b, 0x00fa, 0x680f, + 0x0008, 0x6813, 0x0005, 0x6823, 0x0000, 0x6827, 0x0006, 0x6817, + 0x0008, 0x682b, 0x0000, 0x681f, 0x0019, 0x2069, 0x4f80, 0x2011, + 0x0020, 0x2009, 0x0010, 0x680b, 0x080c, 0x680f, 0x0019, 0x6803, + 0xfd00, 0x6807, 0x0018, 0x6a1a, 0x2d00, 0xa0e8, 0x0008, 0xa290, + 0x0004, 0x8109, 0x00c0, 0x110b, 0x2069, 0x5000, 0x2009, 0x0002, + 0x20a9, 0x0100, 0x6837, 0x0000, 0x680b, 0x0040, 0x7bf0, 0xa386, + 0xfeff, 0x00c0, 0x1131, 0x6817, 0x0100, 0x681f, 0x0064, 0x0078, + 0x1135, 0x6817, 0x0064, 0x681f, 0x0002, 0xade8, 0x0010, 0x0070, + 0x113b, 0x0078, 0x1122, 0x8109, 0x00c0, 0x1120, 0x1078, 0x20d8, + 0x1078, 0x43d1, 0x1078, 0x18a9, 0x1078, 0x48d9, 0x3200, 0xa085, + 0x000d, 0x2090, 0x70c3, 0x0000, 0x0090, 0x1155, 0x70c0, 0xa086, + 0x0002, 0x00c0, 0x1155, 0x1078, 0x126d, 0x1078, 0x117f, 0x78cc, + 0xa005, 0x00c0, 0x1163, 0x1078, 0x1c01, 0x0010, 0x1169, 0x0068, + 0x1169, 0x1078, 0x1fbd, 0x0010, 0x1169, 0x0068, 0x1169, 0x1078, + 0x198e, 0x00e0, 0x1155, 0x1078, 0x4760, 0x0078, 0x1155, 0x1177, + 0x1179, 0x22cc, 0x22cc, 0x4452, 0x4452, 0x22cc, 0x22cc, 0x0078, + 0x1177, 0x0078, 0x1179, 0x0078, 0x117b, 0x0078, 0x117d, 0x0068, + 0x11ea, 0x2061, 0x0000, 0x6018, 0xa084, 0x0001, 0x00c0, 0x11ea, + 0x7814, 0xa005, 0x00c0, 0x1190, 0x0010, 0x11eb, 0x0078, 0x11ea, + 0x2009, 0x4d5b, 0x2104, 0xa005, 0x00c0, 0x11ea, 0x2009, 0x4d64, + 0x200b, 0x0000, 0x7914, 0xa186, 0x0042, 0x00c0, 0x11b5, 0x7816, + 0x2009, 0x4d62, 0x2164, 0x200b, 0x0000, 0x6018, 0x70c6, 0x6014, + 0x70ca, 0x611c, 0xa18c, 0xff00, 0x6020, 0xa084, 0x00ff, 0xa105, + 0x70ce, 0x1078, 0x188e, 0x0078, 0x11e8, 0x7814, 0xa086, 0x0018, + 0x00c0, 0x11bc, 0x1078, 0x15e0, 0x7817, 0x0000, 0x2009, 0x4d62, + 0x2104, 0xa065, 0x0040, 0x11d8, 0x0c7e, 0x609c, 0x2060, 0x1078, + 0x18f9, 0x0c7f, 0x609f, 0x0000, 0x1078, 0x16a2, 0x2009, 0x000e, + 0x6007, 0x0103, 0x1078, 0x186a, 0x00c0, 0x11e4, 0x1078, 0x188e, + 0x2009, 0x4d62, 0x200b, 0x0000, 0x2009, 0x4d5c, 0x2104, 0x200b, + 0x0000, 0xa005, 0x0040, 0x11e8, 0x2001, 0x4005, 0x0078, 0x126f, + 0x0078, 0x126d, 0x007c, 0x70c3, 0x0000, 0x70c7, 0x0000, 0x70cb, + 0x0000, 0x70cf, 0x0000, 0x70c0, 0xa0bc, 0xffc0, 0x00c0, 0x123b, + 0x2038, 0x0079, 0x11fb, 0x126d, 0x12c4, 0x1292, 0x12d3, 0x12e2, + 0x12e8, 0x1289, 0x16ba, 0x12ec, 0x1281, 0x1296, 0x1298, 0x129a, + 0x129c, 0x16bf, 0x1281, 0x12f4, 0x1313, 0x15ee, 0x16b4, 0x129e, + 0x1517, 0x1533, 0x154f, 0x157a, 0x14d0, 0x14de, 0x14f2, 0x1506, + 0x1384, 0x1281, 0x1332, 0x1338, 0x133d, 0x1342, 0x1348, 0x134d, + 0x1352, 0x1357, 0x135c, 0x1360, 0x1375, 0x1381, 0x1281, 0x1281, + 0x1281, 0x1281, 0x1390, 0x1399, 0x13a8, 0x13ce, 0x13d8, 0x13df, + 0x141a, 0x1429, 0x1438, 0x144a, 0x14b0, 0x14c0, 0x1281, 0x1281, + 0x1281, 0x1281, 0x14c5, 0xa0bc, 0xffa0, 0x00c0, 0x1281, 0x2038, + 0xa084, 0x001f, 0x0079, 0x1244, 0x16f8, 0x16fb, 0x170b, 0x1281, + 0x1281, 0x1846, 0x1858, 0x1281, 0x1281, 0x1281, 0x185c, 0x1864, + 0x1281, 0x1281, 0x1281, 0x1281, 0x1281, 0x1281, 0x1281, 0x1281, + 0x1281, 0x16d6, 0x16ea, 0x1281, 0x1797, 0x1281, 0x1822, 0x182c, + 0x1830, 0x183e, 0x1281, 0x1281, 0x72ca, 0x71c6, 0x2001, 0x4006, + 0x0078, 0x126f, 0x73ce, 0x72ca, 0x71c6, 0x2001, 0x4000, 0x70c2, + 0x0068, 0x1270, 0x2061, 0x0000, 0x601b, 0x0001, 0x2091, 0x5000, + 0x00e0, 0x1278, 0x00e0, 0x127a, 0x0068, 0x127a, 0x2091, 0x4080, + 0x007c, 0x70c3, 0x4001, 0x0078, 0x1270, 0x70c3, 0x4006, 0x0078, + 0x1270, 0x2099, 0x0041, 0x20a1, 0x0041, 0x20a9, 0x0005, 0x53a3, + 0x0078, 0x126d, 0x70c4, 0x70c3, 0x0004, 0x007a, 0x0078, 0x126d, + 0x0078, 0x126d, 0x0078, 0x126d, 0x0078, 0x126d, 0x2091, 0x8000, + 0x70c3, 0x0000, 0x70c7, 0x4953, 0x70cb, 0x5020, 0x70cf, 0x2020, + 0x70d3, 0x0007, 0x3f00, 0x70d6, 0x2079, 0x0000, 0x781b, 0x0001, + 0x2031, 0x0030, 0x2059, 0x1000, 0x2029, 0x0457, 0x2051, 0x0470, + 0x2061, 0x0472, 0x20b9, 0xffff, 0x20c1, 0x0000, 0x2091, 0x5000, + 0x2091, 0x4080, 0x0078, 0x0455, 0x2029, 0x0000, 0x2520, 0x71d0, + 0x73c8, 0x72cc, 0x70c4, 0x1078, 0x19d3, 0x0040, 0x126d, 0x70c3, + 0x4002, 0x0078, 0x126d, 0x2029, 0x0000, 0x2520, 0x71d0, 0x73c8, + 0x72cc, 0x70c4, 0x1078, 0x1a1f, 0x0040, 0x126d, 0x70c3, 0x4002, + 0x0078, 0x126d, 0x71c4, 0x70c8, 0x2114, 0x200a, 0x0078, 0x126b, + 0x71c4, 0x2114, 0x0078, 0x126b, 0x70c7, 0x0007, 0x70cb, 0x0037, + 0x70cf, 0x0000, 0x0078, 0x126d, 0x2029, 0x0000, 0x2530, 0x70c4, + 0x72c8, 0x73cc, 0x74d0, 0x70c6, 0x72ca, 0x73ce, 0x74d2, 0xa005, + 0x0040, 0x130d, 0x8001, 0x7892, 0x7a9a, 0x7b9e, 0x7c96, 0x78cc, + 0xa084, 0xfffc, 0x78ce, 0x0078, 0x1311, 0x78cc, 0xa085, 0x0001, + 0x78ce, 0x0078, 0x126d, 0x2029, 0x0000, 0x2530, 0x70c4, 0x72c8, + 0x73cc, 0x74d4, 0x70c6, 0x72ca, 0x73ce, 0x74d6, 0xa005, 0x0040, + 0x132c, 0x8001, 0x78ae, 0x7ab6, 0x7bba, 0x7cb2, 0x78cc, 0xa084, + 0xfcff, 0x78ce, 0x0078, 0x1330, 0x78cc, 0xa085, 0x0100, 0x78ce, + 0x0078, 0x126d, 0x2009, 0x4d61, 0x210c, 0x7aec, 0x0078, 0x126b, + 0x2009, 0x4d41, 0x210c, 0x0078, 0x126c, 0x2009, 0x4d42, 0x210c, + 0x0078, 0x126c, 0x2061, 0x4d40, 0x610c, 0x6210, 0x0078, 0x126b, + 0x2009, 0x4d45, 0x210c, 0x0078, 0x126c, 0x2009, 0x4d46, 0x210c, + 0x0078, 0x126c, 0x2009, 0x4d48, 0x210c, 0x0078, 0x126c, 0x2009, + 0x4d49, 0x210c, 0x0078, 0x126c, 0x7908, 0x7a0c, 0x0078, 0x126b, + 0x71c4, 0x8107, 0xa084, 0x000f, 0x8003, 0x8003, 0x8003, 0xa0e8, + 0x4f80, 0x6a00, 0x6804, 0xa084, 0x0008, 0x0040, 0x1372, 0x6b08, + 0x0078, 0x1373, 0x6b0c, 0x0078, 0x126a, 0x77c4, 0x1078, 0x18b9, + 0x2091, 0x8000, 0x6b1c, 0x6a14, 0x2091, 0x8001, 0x2708, 0x0078, + 0x126a, 0x794c, 0x0078, 0x126c, 0x77c4, 0x1078, 0x18b9, 0x2091, + 0x8000, 0x6908, 0x6a18, 0x6b10, 0x2091, 0x8001, 0x0078, 0x126a, + 0x71c4, 0xa182, 0x0010, 0x00c8, 0x1265, 0x1078, 0x21a3, 0x0078, + 0x126a, 0x71c4, 0xa182, 0x0010, 0x00c8, 0x1265, 0x2011, 0x4d41, + 0x2204, 0x007e, 0x2112, 0x1078, 0x215c, 0x017f, 0x0078, 0x126c, + 0x71c4, 0x2011, 0x13c6, 0x20a9, 0x0008, 0x2204, 0xa106, 0x0040, + 0x13b8, 0x8210, 0x0070, 0x13b6, 0x0078, 0x13ad, 0x0078, 0x1265, + 0xa292, 0x13c6, 0x027e, 0x2011, 0x4d42, 0x2204, 0x2112, 0x017f, + 0x007e, 0x1078, 0x2168, 0x017f, 0x0078, 0x126c, 0x03e8, 0x00fa, + 0x01f4, 0x02ee, 0x0064, 0x0019, 0x0032, 0x004b, 0x2061, 0x4d40, + 0x610c, 0x6210, 0x70c4, 0x600e, 0x70c8, 0x6012, 0x0078, 0x126b, + 0x2061, 0x4d40, 0x6114, 0x70c4, 0x6016, 0x0078, 0x126c, 0x2061, + 0x4d40, 0x71c4, 0x2011, 0x0004, 0x601f, 0x0019, 0x2019, 0x1212, + 0xa186, 0x0028, 0x0040, 0x1400, 0x2011, 0x0005, 0x601f, 0x0019, + 0x2019, 0x1212, 0xa186, 0x0032, 0x0040, 0x1400, 0x2011, 0x0006, + 0x601f, 0x000c, 0x2019, 0x2222, 0xa186, 0x003c, 0x00c0, 0x1265, + 0x6018, 0x007e, 0x611a, 0x7800, 0xa084, 0x0001, 0x00c0, 0x1410, + 0x0028, 0x140c, 0x0078, 0x1410, 0x2019, 0x2222, 0x0078, 0x1412, + 0x2019, 0x1212, 0x23b8, 0x1078, 0x2179, 0x1078, 0x48d9, 0x017f, + 0x0078, 0x126c, 0x71c4, 0xa184, 0xffcf, 0x00c0, 0x1265, 0x2011, + 0x4d48, 0x2204, 0x2112, 0x007e, 0x1078, 0x219b, 0x017f, 0x0078, + 0x126c, 0x71c4, 0xa182, 0x0010, 0x00c8, 0x1265, 0x2011, 0x4d49, + 0x2204, 0x007e, 0x2112, 0x1078, 0x218a, 0x017f, 0x0078, 0x126c, + 0x71c4, 0x72c8, 0xa184, 0xfffd, 0x00c0, 0x1264, 0xa284, 0xfffd, + 0x00c0, 0x1264, 0x2100, 0x7908, 0x780a, 0x2200, 0x7a0c, 0x780e, + 0x0078, 0x126b, 0x71c4, 0x8107, 0xa084, 0x000f, 0x8003, 0x8003, + 0x8003, 0xa0e8, 0x4f80, 0x2019, 0x0000, 0x72c8, 0x6800, 0x007e, + 0xa226, 0x0040, 0x1479, 0x6a02, 0xa484, 0x2000, 0x0040, 0x1462, + 0xa39d, 0x0010, 0xa484, 0x1000, 0x0040, 0x1468, 0xa39d, 0x0008, + 0xa484, 0x4000, 0x0040, 0x1479, 0x810f, 0xa284, 0x4000, 0x0040, + 0x1475, 0x1078, 0x21bd, 0x0078, 0x1479, 0x1078, 0x21af, 0x0078, + 0x1479, 0x72cc, 0x6808, 0xa206, 0x0040, 0x14a8, 0xa2a4, 0x00ff, + 0x2061, 0x4d40, 0x6118, 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0x4832, 0x782c, 0x782a, 0x7830, 0xa005, 0x00c0, 0x4811, 0x2001, + 0x0200, 0x8001, 0x7832, 0x8003, 0x8003, 0x8003, 0x8003, 0xa090, + 0x5000, 0xa298, 0x0002, 0x2304, 0xa084, 0x0008, 0x0040, 0x4832, + 0xa290, 0x0009, 0x2204, 0xa005, 0x0040, 0x482a, 0x8001, 0x2012, + 0x00c0, 0x4832, 0x2304, 0xa084, 0xfff7, 0xa085, 0x0080, 0x201a, + 0x1078, 0x20a0, 0x007c, 0x2069, 0x4d40, 0x6800, 0xa005, 0x0040, + 0x483d, 0x6848, 0xac06, 0x0040, 0x487a, 0x601b, 0x0006, 0x60b4, + 0xa084, 0x3f00, 0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, 0x0060, + 0x6022, 0x6000, 0x2042, 0x6714, 0x6f82, 0x1078, 0x18b9, 0x6818, + 0xa005, 0x0040, 0x4855, 0x8001, 0x681a, 0x6808, 0xa084, 0xffef, + 0x680a, 0x6810, 0x8001, 0x00d0, 0x485f, 0x1078, 0x22ac, 0x6812, + 0x6033, 0x0000, 0x602f, 0x0000, 0x2c68, 0x1078, 0x1b8e, 0x2069, + 0x4d40, 0x7944, 0xa184, 0x0100, 0x2001, 0x0006, 0x686e, 0x00c0, + 0x4875, 0x6986, 0x2001, 0x0004, 0x686e, 0x1078, 0x209b, 0x2091, + 0x8001, 0x007c, 0x2069, 0x0100, 0x2009, 0x4d40, 0x2104, 0xa084, + 0x0007, 0x0040, 0x48d6, 0xa086, 0x0007, 0x00c0, 0x4890, 0x0d7e, + 0x2009, 0x4d52, 0x216c, 0x1078, 0x385e, 0x0d7f, 0x0078, 0x48d6, + 0x2009, 0x4d52, 0x2164, 0x1078, 0x2257, 0x601b, 0x0006, 0x6858, + 0xa084, 0x3f00, 0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, 0x0048, + 0x6022, 0x6033, 0x0000, 0x602f, 0x0000, 0x6830, 0xa084, 0x0040, + 0x0040, 0x48ca, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848, 0xa084, + 0x0004, 0x0040, 0x48b7, 0x0070, 0x48b7, 0x0078, 0x48ae, 0x684b, + 0x0009, 0x20a9, 0x0014, 0x6848, 0xa084, 0x0001, 0x0040, 0x48c4, + 0x0070, 0x48c4, 0x0078, 0x48bb, 0x20a9, 0x00fa, 0x0070, 0x48ca, + 0x0078, 0x48c6, 0x6808, 0xa084, 0xfffd, 0x680a, 0x681b, 0x0048, + 0x2009, 0x4d5b, 0x200b, 0x0007, 0x784c, 0x784a, 0x2091, 0x8001, + 0x007c, 0x2079, 0x4d00, 0x1078, 0x4904, 0x1078, 0x48e8, 0x1078, + 0x48f6, 0x7833, 0x0000, 0x7847, 0x0000, 0x784b, 0x0000, 0x007c, + 0x2019, 0x0003, 0x2011, 0x4d46, 0x2204, 0xa086, 0x003c, 0x0040, + 0x48f3, 0x2019, 0x0002, 0x7b2a, 0x7b2e, 0x007c, 0x2019, 0x0039, + 0x2011, 0x4d46, 0x2204, 0xa086, 0x003c, 0x0040, 0x4901, 0x2019, + 0x0027, 0x7b36, 0x7b3a, 0x007c, 0x2019, 0x3971, 0x2011, 0x4d46, + 0x2204, 0xa086, 0x003c, 0x0040, 0x490f, 0x2019, 0x2626, 0x7b22, + 0x7b26, 0x783f, 0x0000, 0x7843, 0x000a, 0x007c, 0x0020, 0x002b, + 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, + 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, + 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, + 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, + 0x0000, 0x0014, 0x0014, 0x9849, 0x0014, 0x0014, 0x0014, 0x0014, + 0x0014, 0x0014, 0x0014, 0x0080, 0x000f, 0x0000, 0x0201, 0x0604, + 0x0c08, 0x2120, 0x4022, 0xf880, 0x0018, 0x300b, 0xa201, 0x0014, + 0xa200, 0x0014, 0xa200, 0x0214, 0x0000, 0x006c, 0x0002, 0x0014, + 0x98e1, 0x009e, 0x00ab, 0xa202, 0x8838, 0x8180, 0x842a, 0x84a0, + 0x3806, 0x8839, 0x28c2, 0x9cc1, 0x985d, 0x0864, 0x9891, 0x28c1, + 0x9cc1, 0xa203, 0x300c, 0x2847, 0x8161, 0x846a, 0x8000, 0x84a4, + 0x1856, 0x883a, 0x986d, 0x28e2, 0x9c9e, 0x985d, 0x0864, 0x9891, + 0x300c, 0x28e1, 0x9c9e, 0x2809, 0xa206, 0x64c0, 0x67a0, 0x6fc0, + 0x1814, 0x883b, 0x782c, 0x786d, 0x9881, 0x282b, 0xa207, 0x64a0, + 0x67a0, 0x6fc0, 0x1814, 0x883b, 0x7822, 0x883e, 0x9885, 0x8576, + 0x8677, 0x206b, 0x28c1, 0x9cc1, 0x2044, 0x2103, 0x20a2, 0x2081, + 0x986d, 0xa209, 0x2901, 0x989a, 0x0014, 0xa205, 0x8000, 0x85a4, + 0x1872, 0x879a, 0x883c, 0x1fe2, 0xc601, 0xa20a, 0x856e, 0x0704, + 0x9c9e, 0x0014, 0xa204, 0x8000, 0x85a4, 0x84a8, 0x3009, 0x19e2, + 0xf868, 0x8176, 0x86eb, 0x85eb, 0x872e, 0x87a9, 0x883f, 0x08e6, + 0x989e, 0xf881, 0x9899, 0xc801, 0x0014, 0xf8c1, 0x0016, 0x85b2, + 0x80f0, 0x9532, 0xfb02, 0x1de2, 0x0014, 0x8532, 0xf241, 0x0014, + 0x1de2, 0x84a8, 0xd7a0, 0x1fe6, 0x0014, 0xa208, 0x6043, 0x8008, + 0x1dc1, 0x0016, 0x8000, 0x84a4, 0x8160, 0x842a, 0xf041, 0x3008, + 0x84a8, 0x11d6, 0x7042, 0x20dd, 0x0011, 0x20d4, 0x8822, 0x0016, + 0x8000, 0x2847, 0x1011, 0x98d4, 0x8000, 0xa000, 0x2802, 0x1011, + 0x98da, 0x986d, 0x283e, 0x1011, 0x98de, 0xa20b, 0x0017, 0x300c, + 0x8000, 0x85a4, 0x1de2, 0xdb81, 0x0014, 0x0210, 0x98ec, 0x0014, + 0x26e0, 0x873a, 0xfb02, 0x19f2, 0x1fe2, 0x0014, 0xa20d, 0x8180, + 0x842a, 0x84a0, 0x3806, 0x0210, 0x9cc6, 0x0704, 0x0000, 0x006c, + 0x0002, 0x984f, 0x0014, 0x009e, 0x00a3, 0x0017, 0x60ff, 0x300c, + 0x8720, 0xa211, 0x9cc7, 0x8772, 0x8837, 0x2007, 0x10d2, 0x78e2, + 0x9ccb, 0x9858, 0xd984, 0xf0e2, 0xf0a1, 0x98c4, 0x0014, 0x8831, + 0xd167, 0x8830, 0x8830, 0x800f, 0x9401, 0xb520, 0xc802, 0x8820, + 0x9878, 0x2301, 0x9878, 0x10d2, 0x78e2, 0x9ccb, 0x986d, 0xf123, + 0xf142, 0xf101, 0x98bd, 0x10d2, 0x70f8, 0x8832, 0x8203, 0x6001, + 0x0014, 0x6845, 0x0214, 0xa21b, 0x9cc7, 0x2001, 0x98bc, 0x8202, + 0x1852, 0xd184, 0xd163, 0x8834, 0x8001, 0x9889, 0x3027, 0x84a8, + 0x1856, 0x8833, 0x0014, 0xa218, 0x6981, 0x9cb3, 0x6b2a, 0x6902, + 0x1834, 0x9899, 0x1814, 0x8010, 0x8592, 0x8026, 0x84b9, 0x7021, + 0x0014, 0x8000, 0x85a4, 0x84a8, 0x6946, 0xa213, 0x1462, 0xa213, + 0x8000, 0x16e1, 0x98ac, 0x6969, 0xa214, 0x61c2, 0x8002, 0x14e1, + 0x8004, 0x16e1, 0x0101, 0x300a, 0x8827, 0x0014, 0xa217, 0x9cb3, + 0x0014, 0x8000, 0x85a4, 0x8181, 0x842a, 0x84a8, 0x1ce6, 0x0016, + 0xa212, 0x9cc7, 0x10d2, 0x70e4, 0x0004, 0x8007, 0x9424, 0xcc1a, + 0x9ccb, 0x98bc, 0x8827, 0x300a, 0x0013, 0x8000, 0x84a4, 0x84a8, + 0x0016, 0x2002, 0x10d2, 0x98cb, 0x870e, 0xa21d, 0x0012, 0x878e, + 0x85b2, 0x80f8, 0x9424, 0xa532, 0x84a4, 0x8000, 0x84a8, 0x0016, + 0xa21c, 0x1035, 0x988d, 0xa210, 0x8180, 0x842a, 0x84a0, 0xa000, + 0x8010, 0x8592, 0x853b, 0xd044, 0x8022, 0x3807, 0x84bb, 0x98ed, + 0x8021, 0x3807, 0x84b9, 0x300c, 0x817e, 0x872b, 0x8772, 0x988d, + 0x0000, 0x0020, 0x002b, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, + 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, + 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, + 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, + 0x0020, 0x0000, 0x0020, 0x0000, 0x0014, 0x0014, 0x9849, 0x0014, + 0x0014, 0x98ee, 0x98d9, 0x0014, 0x0014, 0x0014, 0x0080, 0x013d, + 0x0000, 0x0201, 0x0604, 0x0c08, 0x2120, 0x4022, 0xf880, 0x0018, + 0x300b, 0xa201, 0x0014, 0xa200, 0x0014, 0xa200, 0x0214, 0xa202, + 0x8838, 0x3806, 0x8839, 0x28c2, 0x9cba, 0xa804, 0x0864, 0xa835, + 0x28c1, 0x9cba, 0xa203, 0x300c, 0x2846, 0x8161, 0x846a, 0x8300, + 0x1856, 0x883a, 0xa806, 0x28e2, 0x9c99, 0xa8f4, 0x0864, 0xa825, + 0x300c, 0x28e1, 0x9c99, 0x2809, 0xa206, 0x64c0, 0x67a0, 0x6fc0, + 0x1814, 0x883b, 0x782c, 0x786d, 0xa808, 0x282b, 0xa207, 0x64a0, + 0x67a0, 0x6fc0, 0x1814, 0x883b, 0x7822, 0x883e, 0xa802, 0x8576, + 0x8677, 0x206b, 0x28c1, 0x9cba, 0x2044, 0x2103, 0x20a2, 0x2081, + 0xa8e0, 0xa209, 0x2901, 0xa809, 0x0014, 0xa205, 0xa300, 0x1872, + 0x879a, 0x883c, 0x1fe2, 0xc601, 0xa20a, 0x856e, 0x0704, 0x9c99, + 0x0014, 0xa204, 0xa300, 0x3009, 0x19e2, 0xf868, 0x8176, 0x86eb, + 0x85eb, 0x872e, 0x87a9, 0x883f, 0x08e6, 0xa8f3, 0xf881, 0xa8ec, + 0xc801, 0x0014, 0xf8c1, 0x0016, 0x85b2, 0x80f0, 0x9532, 0xfb02, + 0x1de2, 0x0014, 0x8532, 0xf241, 0x0014, 0x1de2, 0x84a8, 0xd7a0, + 0x1fe6, 0x0014, 0xa208, 0x6043, 0x8008, 0x1dc1, 0x0016, 0x8300, + 0x8160, 0x842a, 0xf041, 0x3008, 0x84a8, 0x11d6, 0x7042, 0x20dd, + 0x0011, 0x20d5, 0x8822, 0x0016, 0x8000, 0x2847, 0x1011, 0xa8fc, + 0x8000, 0xa000, 0x2802, 0x1011, 0xa8fd, 0xa893, 0x283e, 0x1011, + 0xa8fd, 0xa20b, 0x0017, 0x300c, 0xa300, 0x1de2, 0xdb81, 0x0014, + 0x0210, 0xa801, 0x0014, 0x26e0, 0x873a, 0xfb02, 0x19f2, 0x1fe2, + 0x0014, 0xa20d, 0x3806, 0x0210, 0x9cbf, 0x0704, 0x0017, 0x60ff, + 0x300c, 0x8720, 0xa211, 0x9d63, 0x8772, 0x8837, 0x2007, 0x10d2, + 0x78e2, 0x9d66, 0xa8fc, 0xd984, 0xf0e2, 0xf0a1, 0xa861, 0x0014, + 0x8831, 0xd167, 0x8830, 0x8830, 0x800f, 0x9401, 0xb520, 0xc802, + 0x8820, 0xa80d, 0x2301, 0xa80b, 0x10d2, 0x78e2, 0x9d66, 0xa8fc, + 0xf123, 0xf142, 0xf101, 0xa845, 0x10d2, 0x70f8, 0x8832, 0x8203, + 0x6001, 0x0014, 0x6845, 0x0214, 0xa21b, 0x9d63, 0x2001, 0xa838, + 0x8202, 0x1852, 0xd184, 0xd163, 0x8834, 0x8001, 0xa801, 0x3027, + 0x84a8, 0x1856, 0x8833, 0x0014, 0xa218, 0x6981, 0x9d50, 0x6b2a, + 0x6902, 0x1834, 0xa805, 0x1814, 0x8010, 0x8592, 0x8026, 0x84b9, + 0x7021, 0x0014, 0xa300, 0x6946, 0xa213, 0x1462, 0xa213, 0x8000, + 0x16e1, 0xa807, 0x6969, 0xa214, 0x61c2, 0x8002, 0x14e1, 0x8004, + 0x16e1, 0x0101, 0x300a, 0x8827, 0x0014, 0xa217, 0x9d50, 0x0014, + 0xa300, 0x8181, 0x842a, 0x84a8, 0x1ce6, 0x0016, 0xa212, 0x9d63, + 0x10d2, 0x70e4, 0x0004, 0x8007, 0x9424, 0xcc1a, 0x9d66, 0xa8f8, + 0x8827, 0x300a, 0x0013, 0x8000, 0x84a4, 0x0016, 0x2002, 0x10d2, + 0xa8fd, 0x870e, 0xa21d, 0x0012, 0x878e, 0x85b2, 0x80f8, 0x9424, + 0xa532, 0x84a4, 0x0016, 0xa21c, 0x1035, 0xa8b6, 0xa210, 0x3807, + 0x300c, 0x817e, 0x872b, 0x8772, 0xa8af, 0x0000, 0xd66f +}; +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/firmware/asm_1040.h 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,3545 @@ +/* @(#)asm_1040.h 1.2 */ +/* + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Qlogic, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted provided + * that the following conditions are met: + * 1. Redistribution of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistribution in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/************************************************************************ + * * + * --- ISP1040 Initiator Firmware --- * + * 32 LUN Support * + * * + ************************************************************************/ +#ifndef ISP_TARGET_MODE +/* + * Firmware Version 4.66.00 (14:49 Sep 05, 2000) + */ +static const u_int16_t isp_1040_risc_code[] = { + 0x0078, 0x1041, 0x0000, 0x2cd0, 0x0000, 0x2043, 0x4f50, 0x5952, + 0x4947, 0x4854, 0x2031, 0x3939, 0x312c, 0x3139, 0x3932, 0x2c31, + 0x3939, 0x332c, 0x3139, 0x3934, 0x2051, 0x4c4f, 0x4749, 0x4320, + 0x434f, 0x5250, 0x4f52, 0x4154, 0x494f, 0x4e00, 0x2049, 0x5350, + 0x3130, 0x3230, 0x2046, 0x6972, 0x6d77, 0x6172, 0x6520, 0x2056, + 0x6572, 0x7369, 0x6f6e, 0x2030, 0x342e, 0x3636, 0x2020, 0x2043, + 0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, 0x3030, 0x2050, + 0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2020, 0x3030, 0x2020, + 0x2400, 0x2001, 0x04fd, 0x2004, 0xa082, 0x0005, 0x0048, 0x104c, + 0x0038, 0x1052, 0x0078, 0x104e, 0x0028, 0x1052, 0x20b9, 0x1212, + 0x0078, 0x1054, 0x20b9, 0x1313, 0x2071, 0x0010, 0x70c3, 0x0004, + 0x20c9, 0x62ff, 0x2089, 0x1185, 0x70c7, 0x4953, 0x70cb, 0x5020, + 0x70cf, 0x2020, 0x70d3, 0x0004, 0x3f00, 0x70d6, 0x20c1, 0x0008, + 0x2019, 0x0000, 0x2009, 0xfeff, 0x2100, 0x200b, 0xa5a5, 0xa1ec, + 0x7fff, 0x2d64, 0x206b, 0x0a0a, 0xaddc, 0x3fff, 0x2b54, 0x205b, + 0x5050, 0x2114, 0xa286, 0xa5a5, 0x0040, 0x10c4, 0xa386, 0x000f, + 0x0040, 0x108a, 0x2c6a, 0x2a5a, 0x20c1, 0x0000, 0x2019, 0x000f, + 0x0078, 0x106a, 0x2c6a, 0x2a5a, 0x20c1, 0x0008, 0x2009, 0x7fff, + 0x2148, 0x2944, 0x204b, 0x0a0a, 0xa9bc, 0x3fff, 0x2734, 0x203b, + 0x5050, 0x2114, 0xa286, 0x0a0a, 0x0040, 0x10ae, 0x284a, 0x263a, + 0x20c1, 0x0004, 0x2009, 0x3fff, 0x2134, 0x200b, 0x5050, 0x2114, + 0xa286, 0x5050, 0x0040, 0x10af, 0x0078, 0x118d, 0x284a, 0x263a, + 0x98c0, 0xa188, 0x1000, 0x212c, 0x200b, 0xa5a5, 0x2114, 0xa286, + 0xa5a5, 0x0040, 0x10c1, 0x250a, 0xa18a, 0x1000, 0x98c1, 0x0078, + 0x10c6, 0x250a, 0x0078, 0x10c6, 0x2c6a, 0x2a5a, 0x2130, 0xa18a, + 0x0040, 0x2128, 0xa1a2, 0x3d00, 0x8424, 0x8424, 0x8424, 0x8424, + 0x8424, 0x8424, 0xa192, 0x6300, 0x2009, 0x0000, 0x2001, 0x002f, + 0x1078, 0x1bc9, 0x2218, 0x2079, 0x3d00, 0x2fa0, 0x2408, 0x2011, + 0x0000, 0x20a9, 0x0040, 0x42a4, 0x8109, 0x00c0, 0x10e1, 0x7ee6, + 0x8528, 0x7dda, 0x7cde, 0x7be2, 0x787b, 0x0000, 0x2031, 0x0030, + 0x78c3, 0x0101, 0x780b, 0x0002, 0x780f, 0x0002, 0x784f, 0x0003, + 0x7803, 0x0002, 0x2069, 0x3d40, 0x2001, 0x04fd, 0x2004, 0xa082, + 0x0005, 0x0048, 0x1107, 0x0038, 0x1109, 0x0078, 0x110d, 0x00a8, + 0x110d, 0x681b, 0x003c, 0x0078, 0x110f, 0x681b, 0x0028, 0x6807, + 0x0007, 0x680b, 0x00fa, 0x680f, 0x0008, 0x6813, 0x0005, 0x681f, + 0x0000, 0x6823, 0x0006, 0x6817, 0x0008, 0x6827, 0x0000, 0x2069, + 0x3f80, 0x2011, 0x0020, 0x2009, 0x0010, 0x680b, 0x0c19, 0x680f, + 0x0019, 0x6803, 0xfd00, 0x6807, 0x0018, 0x6a1a, 0x2d00, 0xa0e8, + 0x0008, 0xa290, 0x0004, 0x8109, 0x00c0, 0x1125, 0x2069, 0x4000, + 0x2009, 0x0002, 0x20a9, 0x0100, 0x6837, 0x0000, 0x680b, 0x0040, + 0x7be4, 0xa386, 0xfeff, 0x00c0, 0x114b, 0x6817, 0x0100, 0x681f, + 0x0064, 0x0078, 0x114f, 0x6817, 0x0064, 0x681f, 0x0002, 0xade8, + 0x0010, 0x0070, 0x1155, 0x0078, 0x113c, 0x8109, 0x00c0, 0x113a, + 0x1078, 0x1f20, 0x1078, 0x3792, 0x1078, 0x19e0, 0x1078, 0x3c4a, + 0x3200, 0xa085, 0x000d, 0x2090, 0x70c3, 0x0000, 0x0090, 0x116f, + 0x70c0, 0xa086, 0x0002, 0x00c0, 0x116f, 0x1078, 0x12a4, 0x1078, + 0x11b6, 0x78c0, 0xa005, 0x00c0, 0x117b, 0x1078, 0x1bf2, 0x0068, + 0x117f, 0x1078, 0x1e44, 0x0068, 0x117f, 0x1078, 0x1adf, 0x00e0, + 0x116f, 0x1078, 0x3ac1, 0x0078, 0x116f, 0x118d, 0x1192, 0x20e8, + 0x20e8, 0x380c, 0x380c, 0x20e8, 0x20e8, 0x0088, 0x118d, 0x2091, + 0x8001, 0x007c, 0x0088, 0x1192, 0x2091, 0x8001, 0x007c, 0x0078, + 0x1197, 0x0078, 0x1199, 0x2009, 0x0022, 0x2104, 0xa086, 0x4000, + 0x0040, 0x11b1, 0x7008, 0x800b, 0x00c8, 0x11b1, 0x7007, 0x0002, + 0xa08c, 0x01e0, 0x00c0, 0x11b2, 0xa084, 0x0008, 0x0040, 0x11b1, + 0x087a, 0x097a, 0x70c3, 0x4002, 0x0078, 0x12a7, 0x0068, 0x1221, + 0x2061, 0x0000, 0x6018, 0xa084, 0x0001, 0x00c0, 0x1221, 0x7814, + 0xa005, 0x00c0, 0x11c7, 0x0010, 0x1222, 0x0078, 0x1221, 0x2009, + 0x3d68, 0x2104, 0xa005, 0x00c0, 0x1221, 0x2009, 0x3d71, 0x200b, + 0x0000, 0x7914, 0xa186, 0x0042, 0x00c0, 0x11ec, 0x7816, 0x2009, + 0x3d6f, 0x2164, 0x200b, 0x0000, 0x6018, 0x70c6, 0x6014, 0x70ca, + 0x611c, 0xa18c, 0xff00, 0x6020, 0xa084, 0x00ff, 0xa105, 0x70ce, + 0x1078, 0x19d2, 0x0078, 0x121f, 0x7814, 0xa086, 0x0018, 0x00c0, + 0x11f3, 0x1078, 0x16cd, 0x7817, 0x0000, 0x2009, 0x3d6f, 0x2104, + 0xa065, 0x0040, 0x120f, 0x0c7e, 0x609c, 0x2060, 0x1078, 0x1a30, + 0x0c7f, 0x609f, 0x0000, 0x1078, 0x17b3, 0x2009, 0x0018, 0x6087, + 0x0103, 0x1078, 0x1959, 0x00c0, 0x121b, 0x1078, 0x19d2, 0x2009, + 0x3d6f, 0x200b, 0x0000, 0x2009, 0x3d69, 0x2104, 0x200b, 0x0000, + 0xa005, 0x0040, 0x121f, 0x2001, 0x4005, 0x0078, 0x12a6, 0x0078, + 0x12a4, 0x007c, 0x70c3, 0x0000, 0x70c7, 0x0000, 0x70cb, 0x0000, + 0x70cf, 0x0000, 0x70c0, 0xa0bc, 0xffc0, 0x00c0, 0x1272, 0x2038, + 0x0079, 0x1232, 0x12a4, 0x12ff, 0x12c3, 0x12ff, 0x1368, 0x1368, + 0x12ba, 0x17cb, 0x1373, 0x12b2, 0x12c7, 0x12c9, 0x12cb, 0x12cd, + 0x17d0, 0x12b2, 0x1385, 0x13c1, 0x16e5, 0x17c5, 0x12cf, 0x15fa, + 0x161c, 0x163a, 0x1667, 0x15b3, 0x15c1, 0x15d5, 0x15e9, 0x1445, + 0x12b2, 0x13f3, 0x13f9, 0x13fe, 0x1403, 0x1409, 0x140e, 0x1413, + 0x1418, 0x141d, 0x1421, 0x1436, 0x1442, 0x12b2, 0x12b2, 0x12b2, + 0x12b2, 0x1451, 0x145a, 0x1469, 0x148f, 0x1499, 0x14a0, 0x14e0, + 0x14ef, 0x14fe, 0x1510, 0x1593, 0x15a3, 0x12b2, 0x12b2, 0x12b2, + 0x12b2, 0x15a8, 0xa0bc, 0xffa0, 0x00c0, 0x12b2, 0x2038, 0xa084, + 0x001f, 0x0079, 0x127b, 0x17e7, 0x17ea, 0x17fa, 0x189f, 0x18d8, + 0x1914, 0x1931, 0x1886, 0x12b2, 0x12b2, 0x1935, 0x193d, 0x12b2, + 0x12b2, 0x12b2, 0x12b2, 0x12f5, 0x135e, 0x137b, 0x13b7, 0x16db, + 0x12b2, 0x12b2, 0x12b2, 0x12b2, 0x1943, 0x18f0, 0x18fa, 0x18fe, + 0x190c, 0x12b2, 0x12b2, 0x72ca, 0x71c6, 0x2001, 0x4006, 0x0078, + 0x12a6, 0x73ce, 0x72ca, 0x71c6, 0x2001, 0x4000, 0x70c2, 0x0068, + 0x12a7, 0x2061, 0x0000, 0x601b, 0x0001, 0x2091, 0x5000, 0x2091, + 0x4080, 0x007c, 0x70c3, 0x4001, 0x0078, 0x12a7, 0x70c3, 0x4006, + 0x0078, 0x12a7, 0x2099, 0x0041, 0x20a1, 0x0041, 0x20a9, 0x0005, + 0x53a3, 0x0078, 0x12a4, 0x70c4, 0x70c3, 0x0004, 0x007a, 0x0078, + 0x12a4, 0x0078, 0x12a4, 0x0078, 0x12a4, 0x0078, 0x12a4, 0x2091, + 0x8000, 0x70c3, 0x0000, 0x70c7, 0x4953, 0x70cb, 0x5020, 0x70cf, + 0x2020, 0x70d3, 0x0004, 0x3f00, 0x70d6, 0x2079, 0x0000, 0x781b, + 0x0001, 0x2031, 0x0030, 0x2059, 0x1000, 0x2029, 0x0457, 0x2051, + 0x0470, 0x2061, 0x0472, 0x20b9, 0xffff, 0x20c1, 0x0000, 0x2091, + 0x5000, 0x2091, 0x4080, 0x0078, 0x0455, 0x1078, 0x1b4c, 0x00c0, + 0x12b6, 0x75d8, 0x74dc, 0x75da, 0x74de, 0x0078, 0x1302, 0x2029, + 0x0000, 0x2520, 0x71d0, 0x72c8, 0x73cc, 0x70c4, 0x20a0, 0x2098, + 0x2031, 0x0030, 0x81ff, 0x0040, 0x12a4, 0x7007, 0x0004, 0x731a, + 0x721e, 0x7422, 0x7526, 0x2051, 0x0012, 0x2049, 0x133d, 0x2041, + 0x12a4, 0x7003, 0x0002, 0xa786, 0x0001, 0x0040, 0x1325, 0xa786, + 0x0050, 0x0040, 0x1325, 0x0078, 0x132b, 0x2049, 0x134a, 0x2041, + 0x1356, 0x7003, 0x0003, 0x7017, 0x0000, 0x810b, 0x7112, 0x00c8, + 0x1333, 0x7017, 0x0001, 0x7007, 0x0001, 0xa786, 0x0001, 0x0040, + 0x134a, 0xa786, 0x0050, 0x0040, 0x134a, 0x700c, 0xa084, 0x007f, + 0x2009, 0x0040, 0xa102, 0x8004, 0x094a, 0x20a8, 0x26a0, 0x53a6, + 0x0078, 0x119b, 0x700c, 0xa084, 0x007f, 0x0040, 0x134a, 0x80ac, + 0x0048, 0x134a, 0x2698, 0x53a5, 0x0078, 0x119b, 0x700c, 0xa084, + 0x007f, 0x80ac, 0x2698, 0x53a5, 0x0078, 0x12a4, 0x1078, 0x1b4c, + 0x00c0, 0x12b6, 0x75d8, 0x74dc, 0x75da, 0x74de, 0x0078, 0x1302, + 0x71c4, 0x70c8, 0x2114, 0xa79e, 0x0004, 0x00c0, 0x1370, 0x200a, + 0x72ca, 0x0078, 0x12a3, 0x70c7, 0x0004, 0x70cb, 0x0042, 0x70cf, + 0x0000, 0x0078, 0x12a4, 0x1078, 0x1b4c, 0x00c0, 0x12b6, 0x75d8, + 0x76dc, 0x75da, 0x76de, 0x0078, 0x1388, 0x2029, 0x0000, 0x2530, + 0x70c4, 0x72c8, 0x73cc, 0x74d0, 0x70c6, 0x72ca, 0x73ce, 0x74d2, + 0xa005, 0x0040, 0x13b1, 0xa40a, 0x0040, 0x1398, 0x00c8, 0x13a2, + 0x8001, 0x788a, 0xa084, 0xfc00, 0x0040, 0x13a6, 0x78c0, 0xa085, + 0x0001, 0x78c2, 0x2001, 0x4005, 0x0078, 0x12a6, 0x7a92, 0x7b96, + 0x7d9a, 0x7e9e, 0x7c8e, 0x78c0, 0xa084, 0xfffc, 0x78c2, 0x0078, + 0x13b5, 0x78c0, 0xa085, 0x0001, 0x78c2, 0x0078, 0x12a4, 0x1078, + 0x1b4c, 0x00c0, 0x12b6, 0x75d8, 0x76dc, 0x75da, 0x76de, 0x0078, + 0x13c4, 0x2029, 0x0000, 0x2530, 0x70c4, 0x72c8, 0x73cc, 0x74d4, + 0x70c6, 0x72ca, 0x73ce, 0x74d6, 0xa005, 0x0040, 0x13ed, 0xa40a, + 0x0040, 0x13d4, 0x00c8, 0x13de, 0x8001, 0x78a6, 0xa084, 0xfc00, + 0x0040, 0x13e2, 0x78c0, 0xa085, 0x0100, 0x78c2, 0x2001, 0x4005, + 0x0078, 0x12a6, 0x7aae, 0x7bb2, 0x7db6, 0x7eba, 0x7caa, 0x78c0, + 0xa084, 0xfcff, 0x78c2, 0x0078, 0x13f1, 0x78c0, 0xa085, 0x0100, + 0x78c2, 0x0078, 0x12a4, 0x2009, 0x3d5f, 0x210c, 0x7ae0, 0x0078, + 0x12a2, 0x2009, 0x3d41, 0x210c, 0x0078, 0x12a3, 0x2009, 0x3d42, + 0x210c, 0x0078, 0x12a3, 0x2061, 0x3d40, 0x610c, 0x6210, 0x0078, + 0x12a2, 0x2009, 0x3d45, 0x210c, 0x0078, 0x12a3, 0x2009, 0x3d46, + 0x210c, 0x0078, 0x12a3, 0x2009, 0x3d47, 0x210c, 0x0078, 0x12a3, + 0x2009, 0x3d48, 0x210c, 0x0078, 0x12a3, 0x7908, 0x7a0c, 0x0078, + 0x12a2, 0x71c4, 0x8107, 0xa084, 0x000f, 0x8003, 0x8003, 0x8003, + 0xa0e8, 0x3f80, 0x6a00, 0x6804, 0xa084, 0x0008, 0x0040, 0x1433, + 0x6b08, 0x0078, 0x1434, 0x6b0c, 0x0078, 0x12a1, 0x77c4, 0x1078, + 0x19f0, 0x2091, 0x8000, 0x6b1c, 0x6a14, 0x2091, 0x8001, 0x2708, + 0x0078, 0x12a1, 0x794c, 0x0078, 0x12a3, 0x77c4, 0x1078, 0x19f0, + 0x2091, 0x8000, 0x6908, 0x6a18, 0x6b10, 0x2091, 0x8001, 0x0078, + 0x12a1, 0x71c4, 0xa182, 0x0010, 0x00c8, 0x129c, 0x1078, 0x1fb7, + 0x0078, 0x12a1, 0x71c4, 0xa182, 0x0010, 0x00c8, 0x129c, 0x2011, + 0x3d41, 0x2204, 0x007e, 0x2112, 0x1078, 0x1f70, 0x017f, 0x0078, + 0x12a3, 0x71c4, 0x2011, 0x1487, 0x20a9, 0x0008, 0x2204, 0xa106, + 0x0040, 0x1479, 0x8210, 0x0070, 0x1477, 0x0078, 0x146e, 0x0078, + 0x129c, 0xa292, 0x1487, 0x027e, 0x2011, 0x3d42, 0x2204, 0x2112, + 0x017f, 0x007e, 0x1078, 0x1f7c, 0x017f, 0x0078, 0x12a3, 0x03e8, + 0x00fa, 0x01f4, 0x02ee, 0x0064, 0x0019, 0x0032, 0x004b, 0x2061, + 0x3d40, 0x610c, 0x6210, 0x70c4, 0x600e, 0x70c8, 0x6012, 0x0078, + 0x12a2, 0x2061, 0x3d40, 0x6114, 0x70c4, 0x6016, 0x0078, 0x12a3, + 0x71c4, 0x2011, 0x0004, 0x2019, 0x1212, 0xa186, 0x0028, 0x0040, + 0x14b9, 0x2011, 0x0005, 0x2019, 0x1212, 0xa186, 0x0032, 0x0040, + 0x14b9, 0x2011, 0x0006, 0x2019, 0x1313, 0xa186, 0x003c, 0x00c0, + 0x129c, 0x2061, 0x3d40, 0x6018, 0x007e, 0x611a, 0x7800, 0xa084, + 0x0001, 0x00c0, 0x14d6, 0x2001, 0x04fd, 0x2004, 0xa082, 0x0005, + 0x0048, 0x14ce, 0x0038, 0x14d2, 0x0078, 0x14d6, 0x0028, 0x14d2, + 0x0078, 0x14d6, 0x2019, 0x1313, 0x0078, 0x14d8, 0x2019, 0x1212, + 0x23b8, 0x1078, 0x1f8d, 0x1078, 0x3c4a, 0x017f, 0x0078, 0x12a3, + 0x71c4, 0xa184, 0xffcf, 0x00c0, 0x129c, 0x2011, 0x3d47, 0x2204, + 0x2112, 0x007e, 0x1078, 0x1faf, 0x017f, 0x0078, 0x12a3, 0x71c4, + 0xa182, 0x0010, 0x00c8, 0x129c, 0x2011, 0x3d48, 0x2204, 0x007e, + 0x2112, 0x1078, 0x1f9e, 0x017f, 0x0078, 0x12a3, 0x71c4, 0x72c8, + 0xa184, 0xfffd, 0x00c0, 0x129b, 0xa284, 0xfffd, 0x00c0, 0x129b, + 0x2100, 0x7908, 0x780a, 0x2200, 0x7a0c, 0x780e, 0x0078, 0x12a2, + 0x71c4, 0x8107, 0xa084, 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0xa0bc, 0x000f, 0xa7b8, 0x3772, 0x273c, 0x87fb, 0x00c0, + 0x3a04, 0x0048, 0x39fd, 0x1078, 0x20c8, 0x709c, 0xa075, 0x2060, + 0x0040, 0x3a32, 0x0078, 0x39f0, 0x2704, 0xae68, 0x6808, 0xa422, + 0x680c, 0xa31b, 0x0048, 0x3a1f, 0x8a51, 0x00c0, 0x3a11, 0x1078, + 0x20c8, 0x8738, 0x2704, 0xa005, 0x00c0, 0x3a05, 0x709c, 0xa075, + 0x2060, 0x0040, 0x3a32, 0x2039, 0x3764, 0x0078, 0x39f0, 0x8422, + 0x8420, 0x831a, 0xa399, 0x0000, 0x6908, 0x2400, 0xa122, 0x690c, + 0x2300, 0xa11b, 0x00c8, 0x3a2e, 0x1078, 0x20c8, 0x2071, 0x0020, + 0x0078, 0x3955, 0x127f, 0x2000, 0x007c, 0x7008, 0xa084, 0x0003, + 0xa086, 0x0003, 0x0040, 0x3a5d, 0x2704, 0xac08, 0x2104, 0x701a, + 0x8108, 0x2104, 0x701e, 0x8108, 0x2104, 0x7012, 0x8108, 0x2104, + 0x7016, 0x6004, 0xa084, 0x0008, 0x0040, 0x3a54, 0x8108, 0x2104, + 0x7022, 0x8108, 0x2104, 0x7026, 0x7602, 0x7004, 0xa084, 0x0010, + 0xa085, 0x0001, 0x7006, 0x1078, 0x38fb, 0x007c, 0x127e, 0x007e, + 0x0d7e, 0x2091, 0x2200, 0x2049, 0x3a5e, 0x0d7f, 0x087f, 0x7108, + 0xa184, 0x0003, 0x00c0, 0x3a72, 0x6828, 0xa005, 0x0040, 0x3a80, + 0x0078, 0x3701, 0x00a0, 0x3a79, 0x7108, 0x1078, 0x381c, 0x0078, + 0x3a67, 0x7007, 0x0010, 0x00a0, 0x3a7b, 0x7108, 0x1078, 0x381c, + 0x7008, 0xa086, 0x0008, 0x00c0, 0x3a67, 0x7000, 0xa005, 0x00c0, + 0x3a67, 0x7003, 0x0000, 0x2049, 0x0000, 0x127f, 0x2000, 0x007c, + 0x127e, 0x147e, 0x137e, 0x157e, 0x0c7e, 0x0d7e, 0x2091, 0x2200, + 0x0d7f, 0x2049, 0x3a90, 0xad80, 0x0011, 0x20a0, 0x2099, 0x0031, + 0x700c, 0xa084, 0x00ff, 0x682a, 0x7007, 0x0008, 0x7007, 0x0002, + 0x7003, 0x0001, 0x0040, 0x3aaf, 0x8000, 0x80ac, 0x53a5, 0x7007, + 0x0004, 0x7004, 0xa084, 0x0004, 0x00c0, 0x3ab1, 0x0c7f, 0x2049, + 0x0000, 0x7003, 0x0000, 0x157f, 0x137f, 0x147f, 0x127f, 0x2000, + 0x007c, 0x2091, 0x6000, 0x2091, 0x8000, 0x78c0, 0xa005, 0x00c0, + 0x3ad8, 0x798c, 0x70d0, 0xa106, 0x00c0, 0x3ad8, 0x7804, 0xa005, + 0x0040, 0x3ad8, 0x7807, 0x0000, 0x0068, 0x3ad8, 0x2091, 0x4080, + 0x7820, 0x8001, 0x7822, 0x00c0, 0x3b5d, 0x7824, 0x7822, 0x783c, + 0xa005, 0x0040, 0x3ae9, 0x8001, 0x783e, 0x00c0, 0x3ae9, 0x1078, + 0x3c87, 0x78ec, 0xa005, 0x0040, 0x3b0d, 0x78d4, 0xa005, 0x00c0, + 0x3b0d, 0x3a10, 0xa284, 0x0002, 0x00c0, 0x3afd, 0x78d7, 0x0007, + 0x2009, 0xff01, 0x200a, 0x0078, 0x3b0d, 0xa284, 0x0001, 0x00c0, + 0x3b05, 0x78eb, 0x0000, 0x0078, 0x3b0d, 0x78e8, 0xa005, 0x00c0, + 0x3b0d, 0x78d7, 0x0008, 0x78eb, 0x0001, 0x2069, 0x3d40, 0x6800, + 0xa084, 0x0007, 0x0040, 0x3b24, 0xa086, 0x0002, 0x0040, 0x3b24, + 0x6830, 0xa00d, 0x0040, 0x3b24, 0x2104, 0xa005, 0x0040, 0x3b24, + 0x8001, 0x200a, 0x0040, 0x3bff, 0x7848, 0xa005, 0x0040, 0x3b2e, + 0x8001, 0x784a, 0x00c0, 0x3b2e, 0x1078, 0x1f05, 0x68c4, 0xa005, + 0x0040, 0x3b3a, 0x8001, 0x68c6, 0x00c0, 0x3b3a, 0x68a3, 0x0000, + 0x68a7, 0x0001, 0x2061, 0x4000, 0x2009, 0x0002, 0x20a9, 0x0100, + 0x6034, 0xa005, 0x0040, 0x3b50, 0x8001, 0x6036, 0x00c0, 0x3b50, + 0x6010, 0xa005, 0x0040, 0x3b50, 0x017e, 0x1078, 0x1f05, 0x017f, + 0xace0, 0x0010, 0x0070, 0x3b56, 0x0078, 0x3b40, 0x8109, 0x0040, + 0x3b5d, 0x20a9, 0x0100, 0x0078, 0x3b40, 0x1078, 0x3b64, 0x1078, + 0x3b89, 0x2091, 0x8001, 0x007c, 0x7834, 0x8001, 0x7836, 0x00c0, + 0x3b88, 0x7838, 0x7836, 0x2091, 0x8000, 0x7844, 0xa005, 0x00c0, + 0x3b73, 0x2001, 0x0101, 0x8001, 0x7846, 0xa080, 0x6000, 0x2040, + 0x2004, 0xa065, 0x0040, 0x3b88, 0x6024, 0xa005, 0x0040, 0x3b84, + 0x8001, 0x6026, 0x0040, 0x3bb8, 0x6000, 0x2c40, 0x0078, 0x3b79, + 0x007c, 0x7828, 0x8001, 0x782a, 0x00c0, 0x3bb7, 0x782c, 0x782a, + 0x7830, 0xa005, 0x00c0, 0x3b96, 0x2001, 0x0200, 0x8001, 0x7832, + 0x8003, 0x8003, 0x8003, 0x8003, 0xa090, 0x4000, 0xa298, 0x0002, + 0x2304, 0xa084, 0x0008, 0x0040, 0x3bb7, 0xa290, 0x0009, 0x2204, + 0xa005, 0x0040, 0x3baf, 0x8001, 0x2012, 0x00c0, 0x3bb7, 0x2304, + 0xa084, 0xfff7, 0xa085, 0x0080, 0x201a, 0x1078, 0x1f05, 0x007c, + 0x2069, 0x3d40, 0x6800, 0xa005, 0x0040, 0x3bc2, 0x683c, 0xac06, + 0x0040, 0x3bff, 0x601b, 0x0006, 0x60b4, 0xa084, 0x3f00, 0x601e, + 0x6020, 0xa084, 0x00ff, 0xa085, 0x0060, 0x6022, 0x6000, 0x2042, + 0x6714, 0x6fb6, 0x1078, 0x19f0, 0x6818, 0xa005, 0x0040, 0x3bda, + 0x8001, 0x681a, 0x6808, 0xa084, 0xffef, 0x680a, 0x6810, 0x8001, + 0x00d0, 0x3be4, 0x1078, 0x20c8, 0x6812, 0x602f, 0x0000, 0x6033, + 0x0000, 0x2c68, 0x1078, 0x1b7f, 0x2069, 0x3d40, 0x7944, 0xa184, + 0x0100, 0x2001, 0x0006, 0x68a2, 0x00c0, 0x3bfa, 0x69ba, 0x2001, + 0x0004, 0x68a2, 0x1078, 0x1f00, 0x2091, 0x8001, 0x007c, 0x2009, + 0x3d4f, 0x2164, 0x2069, 0x0100, 0x1078, 0x2073, 0x601b, 0x0006, + 0x6858, 0xa084, 0x3f00, 0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, + 0x0048, 0x6022, 0x602f, 0x0000, 0x6033, 0x0000, 0x6830, 0xa084, + 0x0040, 0x0040, 0x3c3b, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848, + 0xa084, 0x0004, 0x0040, 0x3c28, 0x0070, 0x3c28, 0x0078, 0x3c1f, + 0x684b, 0x0009, 0x20a9, 0x0014, 0x6848, 0xa084, 0x0001, 0x0040, + 0x3c35, 0x0070, 0x3c35, 0x0078, 0x3c2c, 0x20a9, 0x00fa, 0x0070, + 0x3c3b, 0x0078, 0x3c37, 0x6808, 0xa084, 0xfffd, 0x680a, 0x681b, + 0x0047, 0x2009, 0x3d68, 0x200b, 0x0007, 0x784c, 0x784a, 0x2091, + 0x8001, 0x007c, 0x2079, 0x3d00, 0x1078, 0x3c75, 0x1078, 0x3c59, + 0x1078, 0x3c67, 0x7833, 0x0000, 0x7847, 0x0000, 0x784b, 0x0000, + 0x007c, 0x2019, 0x0003, 0x2011, 0x3d46, 0x2204, 0xa086, 0x003c, + 0x0040, 0x3c64, 0x2019, 0x0002, 0x7b2a, 0x7b2e, 0x007c, 0x2019, + 0x0039, 0x2011, 0x3d46, 0x2204, 0xa086, 0x003c, 0x0040, 0x3c72, + 0x2019, 0x0027, 0x7b36, 0x7b3a, 0x007c, 0x2019, 0x3971, 0x2011, + 0x3d46, 0x2204, 0xa086, 0x003c, 0x0040, 0x3c80, 0x2019, 0x2626, + 0x7b22, 0x7b26, 0x783f, 0x0000, 0x7843, 0x000a, 0x007c, 0x2069, + 0x3d40, 0x6a40, 0xa285, 0x0000, 0x0040, 0x3cce, 0x6944, 0xa080, + 0x3d80, 0x2164, 0x6304, 0x83ff, 0x00c0, 0x3ca1, 0x8211, 0x0040, + 0x3ca4, 0x8108, 0xa11a, 0x0048, 0x3c91, 0x2009, 0x3d80, 0x0078, + 0x3c91, 0x7940, 0x793e, 0x007c, 0x2011, 0x0002, 0x2039, 0x0000, + 0x20a9, 0x0100, 0x1078, 0x19f0, 0x2d00, 0xa088, 0x0002, 0x2168, + 0x682b, 0x0000, 0x682f, 0x0000, 0x2104, 0xa085, 0x0040, 0x200a, + 0x2100, 0xa088, 0x0010, 0x0070, 0x3cbf, 0x0078, 0x3caf, 0x8211, + 0x0040, 0x3cc6, 0x20a9, 0x0100, 0x0078, 0x3caf, 0x2009, 0x3d51, + 0x200b, 0x3d7f, 0x2009, 0x3d50, 0x200b, 0x0000, 0x007c, 0x4de2 +}; +#else +/************************************************************************ + * * + * --- ISP1040 Initiator/Target Firmware --- * + * 32 LUN Support * + * * + ************************************************************************/ +/* + * Firmware Version 7.65.00 (14:17 Jul 20, 1999) + */ +static const u_int16_t isp_1040_risc_code[] = { + 0x0078, 0x103a, 0x0000, 0x4057, 0x0000, 0x2043, 0x4f50, 0x5952, + 0x4947, 0x4854, 0x2031, 0x3939, 0x3520, 0x514c, 0x4f47, 0x4943, + 0x2043, 0x4f52, 0x504f, 0x5241, 0x5449, 0x4f4e, 0x2049, 0x5350, + 0x3130, 0x3230, 0x2049, 0x2f54, 0x2046, 0x6972, 0x6d77, 0x6172, + 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, 0x372e, 0x3635, + 0x2020, 0x2043, 0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, + 0x3030, 0x2050, 0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2020, + 0x3031, 0x2024, 0x2001, 0x04fd, 0x2004, 0xa082, 0x0005, 0x0048, + 0x1045, 0x0038, 0x104b, 0x0078, 0x1047, 0x0028, 0x104b, 0x20b9, + 0x1212, 0x0078, 0x104d, 0x20b9, 0x2222, 0x20c1, 0x0008, 0x2071, + 0x0010, 0x70c3, 0x0004, 0x20c9, 0x77ff, 0x2089, 0x1186, 0x70c7, + 0x4953, 0x70cb, 0x5020, 0x70cf, 0x2020, 0x70d3, 0x0007, 0x3f00, + 0x70d6, 0x20c1, 0x0008, 0x2019, 0x0000, 0x2009, 0xfeff, 0x2100, + 0x200b, 0xa5a5, 0xa1ec, 0x7fff, 0x2d64, 0x206b, 0x0a0a, 0xaddc, + 0x3fff, 0x2b54, 0x205b, 0x5050, 0x2114, 0xa286, 0xa5a5, 0x0040, + 0x10bf, 0xa386, 0x000f, 0x0040, 0x1085, 0x2c6a, 0x2a5a, 0x20c1, + 0x0000, 0x2019, 0x000f, 0x0078, 0x1065, 0x2c6a, 0x2a5a, 0x20c1, + 0x0008, 0x2009, 0x7fff, 0x2148, 0x2944, 0x204b, 0x0a0a, 0xa9bc, + 0x3fff, 0x2734, 0x203b, 0x5050, 0x2114, 0xa286, 0x0a0a, 0x0040, + 0x10a9, 0x284a, 0x263a, 0x20c1, 0x0004, 0x2009, 0x3fff, 0x2134, + 0x200b, 0x5050, 0x2114, 0xa286, 0x5050, 0x0040, 0x10aa, 0x0078, + 0x118e, 0x284a, 0x263a, 0x98c0, 0xa188, 0x1000, 0x212c, 0x200b, + 0xa5a5, 0x2114, 0xa286, 0xa5a5, 0x0040, 0x10bc, 0x250a, 0xa18a, + 0x1000, 0x98c1, 0x0078, 0x10c1, 0x250a, 0x0078, 0x10c1, 0x2c6a, + 0x2a5a, 0x2130, 0xa18a, 0x0040, 0x2128, 0xa1a2, 0x5100, 0x8424, + 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, 0xa192, 0x7800, 0x2009, + 0x0000, 0x2001, 0x0031, 0x1078, 0x1cba, 0x2218, 0x2079, 0x5100, + 0x2fa0, 0x2408, 0x2011, 0x0000, 0x20a9, 0x0040, 0x42a4, 0x8109, + 0x00c0, 0x10dc, 0x7ef2, 0x8528, 0x7de6, 0x7cea, 0x7bee, 0x7883, + 0x0000, 0x2031, 0x0030, 0x78cf, 0x0101, 0x780b, 0x0002, 0x780f, + 0x0002, 0x784f, 0x0003, 0x2069, 0x5140, 0x2001, 0x04fd, 0x2004, + 0xa082, 0x0005, 0x0048, 0x1104, 0x0038, 0x1100, 0x0078, 0x1108, + 0x681b, 0x003c, 0x0078, 0x110a, 0x00a8, 0x1108, 0x681b, 0x003c, + 0x681b, 0x0028, 0x6807, 0x0007, 0x680b, 0x00fa, 0x680f, 0x0008, + 0x6813, 0x0005, 0x6823, 0x0000, 0x6827, 0x0006, 0x6817, 0x0008, + 0x682b, 0x0000, 0x681f, 0x0019, 0x2069, 0x5380, 0x2011, 0x0020, + 0x2009, 0x0010, 0x680b, 0x080c, 0x680f, 0x0019, 0x6803, 0xfd00, + 0x6807, 0x0018, 0x6a1a, 0x2d00, 0xa0e8, 0x0008, 0xa290, 0x0004, + 0x8109, 0x00c0, 0x1122, 0x2069, 0x5400, 0x2009, 0x0002, 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0x0014, 0xa200, 0x0214, 0xa202, 0x8838, 0x3806, + 0x8839, 0x20c3, 0x0864, 0xa82e, 0x28c1, 0x9cb1, 0xa203, 0x300c, + 0x2846, 0x8161, 0x846a, 0x8300, 0x1856, 0x883a, 0xa804, 0x28f2, + 0x9c90, 0xa8f4, 0x300c, 0x28e1, 0x9c90, 0x2802, 0xa206, 0x64c3, + 0x282d, 0xa207, 0x64a0, 0x67a0, 0x6fc0, 0x1814, 0x883b, 0x7824, + 0x68c1, 0x7864, 0x883e, 0xa802, 0x8576, 0x8677, 0x206b, 0x28c1, + 0x9cb1, 0x2044, 0x2103, 0x20a2, 0x2081, 0xa8e5, 0xa209, 0x2901, + 0xa809, 0x0014, 0xa205, 0xa300, 0x1872, 0x879a, 0x883c, 0x1fe2, + 0xc601, 0xa20a, 0x856e, 0x0704, 0x9c90, 0x0014, 0xa204, 0xa300, + 0x3009, 0x19e2, 0xf868, 0x8176, 0x86eb, 0x85eb, 0x872e, 0x87a9, + 0x883f, 0x08e6, 0xa8f3, 0xf881, 0xa8ec, 0xc801, 0x0014, 0xf8c1, + 0x0016, 0x85b2, 0x80f0, 0x9532, 0xfb02, 0x1de2, 0x0014, 0x8532, + 0xf241, 0x0014, 0x1de2, 0x84a8, 0xd7a0, 0x1fe6, 0x0014, 0xa208, + 0x6043, 0x8008, 0x1dc1, 0x0016, 0x8300, 0x8160, 0x842a, 0xf041, + 0x3008, 0x84a8, 0x11d6, 0x7042, 0x20dd, 0x0011, 0x20d5, 0x8822, + 0x0016, 0x8000, 0x2847, 0x1011, 0xa8fc, 0x8000, 0xa000, 0x2802, + 0x1011, 0xa8fd, 0xa898, 0x283e, 0x1011, 0xa8fd, 0xa20b, 0x0017, + 0x300c, 0xa300, 0x1de2, 0xdb81, 0x0014, 0x0210, 0xa801, 0x0014, + 0x26e0, 0x873a, 0xfb02, 0x19f2, 0x1fe2, 0x0014, 0xa20d, 0x3806, + 0x0210, 0x9cb6, 0x0704, 0x0017, 0x60ff, 0x300c, 0x8720, 0xa211, + 0x9d6b, 0x8772, 0x8837, 0x2101, 0xa821, 0x10d2, 0x78e2, 0x9d6e, + 0xa8fc, 0xd984, 0xf0e2, 0xf0a1, 0xa871, 0x0014, 0x8831, 0xd166, + 0x8830, 0x800f, 0x9401, 0xb520, 0xc802, 0x8820, 0xa80f, 0x2301, + 0xa80d, 0x10d2, 0x78e4, 0x9d6e, 0x8821, 0x8820, 0xa8e6, 0xf123, + 0xf142, 0xf101, 0xa854, 0x10d2, 0x70f6, 0x8832, 0x8203, 0x870c, + 0xd99e, 0x6001, 0x0014, 0x6845, 0x0214, 0xa21b, 0x9d6b, 0x2001, + 0xa845, 0x8201, 0x1852, 0xd184, 0xd163, 0x8834, 0x8001, 0xa801, + 0x3027, 0x84a8, 0x1a56, 0x8833, 0x0014, 0xa218, 0x6981, 0x9d57, + 0x692a, 0x6902, 0x1834, 0xa805, 0x1a14, 0x8010, 0x8592, 0x8026, + 0x84b9, 0x7021, 0x0014, 0xa300, 0x69e1, 0x9d40, 0x694c, 0xa213, + 0x9d50, 0x1462, 0xa213, 0x8000, 0x16e1, 0xa80a, 0x8023, 0x16e1, + 0x8001, 0x10f1, 0x0016, 0x6968, 0xa214, 0x9d50, 0x8004, 0x16e1, + 0x0101, 0x300a, 0x8827, 0x0014, 0x9d50, 0x0014, 0x61c2, 0x8002, + 0x14e1, 0x0016, 0xa217, 0x9d57, 0x0014, 0xa300, 0x8181, 0x842a, + 0x84a8, 0x1ce6, 0x882c, 0x0016, 0xa212, 0x9d6b, 0x10d2, 0x70e4, + 0x0004, 0x8007, 0x9424, 0xcc1a, 0x9d6e, 0xa8f8, 0x8827, 0x300a, + 0x0013, 0x8000, 0x84a4, 0x0016, 0x11c2, 0x211e, 0x870e, 0xa21d, + 0x0014, 0x878e, 0x0016, 0xa21c, 0x1035, 0xa8af, 0xa210, 0x3807, + 0x300c, 0x817e, 0x872b, 0x8772, 0xa8a8, 0x0000, 0xdf21 +}; +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/firmware/asm_1080.h 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,4554 @@ +/* @(#)asm_1080.h 1.2 */ +/* + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Qlogic, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted provided + * that the following conditions are met: + * 1. Redistribution of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistribution in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ISP_TARGET_MODE +/************************************************************************ + * * + * --- ISP1240/ISP1080/ISP1280 Initiator Firmware --- * + * 32 LUN Support * + * * + ************************************************************************/ +/* + * Firmware Version 8.15.00 (14:35 Aug 22, 2000) + */ +static const u_int16_t isp_1080_risc_code[] = { + 0x0078, 0x1041, 0x0000, 0x3d3b, 0x0000, 0x2043, 0x4f50, 0x5952, + 0x4947, 0x4854, 0x2031, 0x3939, 0x312c, 0x3139, 0x3932, 0x2c31, + 0x3939, 0x332c, 0x3139, 0x3934, 0x2051, 0x4c4f, 0x4749, 0x4320, + 0x434f, 0x5250, 0x4f52, 0x4154, 0x494f, 0x4e00, 0x2049, 0x5350, + 0x3132, 0x3430, 0x2046, 0x6972, 0x6d77, 0x6172, 0x6520, 0x2056, + 0x6572, 0x7369, 0x6f6e, 0x2030, 0x382e, 0x3135, 0x2020, 0x2043, + 0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, 0x3030, 0x2050, + 0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2020, 0x3030, 0x2020, + 0x2400, 0x20c9, 0x97ff, 0x2001, 0x04fc, 0x2004, 0xa086, 0x1080, + 0x00c0, 0x1054, 0x2071, 0x0100, 0x70a0, 0x70a2, 0x20c1, 0x0010, + 0x2089, 0x1374, 0x0078, 0x106d, 0x2001, 0x04fc, 0x2004, 0xa086, + 0x1280, 0x00c0, 0x1069, 0x2071, 0x0200, 0x70a0, 0x70a2, 0x2071, + 0x0100, 0x70a0, 0x70a2, 0x20c1, 0x0010, 0x2089, 0x13f8, 0x0078, + 0x106d, 0x20c1, 0x0020, 0x2089, 0x131c, 0x2071, 0x0010, 0x70c3, + 0x0004, 0x70c7, 0x4953, 0x70cb, 0x5020, 0x70cf, 0x2020, 0x70d3, + 0x0008, 0x2001, 0x04fe, 0x70d6, 0x20c1, 0x0021, 0x2019, 0x0000, + 0x2009, 0xfeff, 0x2100, 0x200b, 0xa5a5, 0xa1ec, 0x7fff, 0x2d64, + 0x206b, 0x0a0a, 0xaddc, 0x3fff, 0x2b54, 0x205b, 0x5050, 0x2114, + 0xa286, 0xa5a5, 0x0040, 0x10a4, 0xa386, 0x000f, 0x0040, 0x10a0, + 0x2c6a, 0x2a5a, 0x20c1, 0x0020, 0x2019, 0x000f, 0x0078, 0x1080, + 0x2c6a, 0x2a5a, 0x0078, 0x10a2, 0x2c6a, 0x2a5a, 0x2130, 0x2128, + 0xa1a2, 0x4e00, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, + 0xa192, 0x9800, 0x2009, 0x0000, 0x2001, 0x0032, 0x1078, 0x207a, + 0x2218, 0x2079, 0x4e00, 0x2fa0, 0x2408, 0x2011, 0x0000, 0x20a9, + 0x0040, 0x42a4, 0x8109, 0x00c0, 0x10bf, 0x2009, 0xff00, 0x3400, + 0xa102, 0x0048, 0x10cf, 0x0040, 0x10cf, 0x20a8, 0x42a4, 0x2001, + 0x04fc, 0x2004, 0xa086, 0x1080, 0x00c0, 0x10e5, 0x2071, 0x0100, + 0x0d7e, 0x2069, 0x4e40, 0x1078, 0x4cdd, 0x0d7f, 0x7810, 0xc0ed, + 0x7812, 0x781b, 0x0064, 0x0078, 0x110a, 0x2001, 0x04fc, 0x2004, + 0xa086, 0x1280, 0x00c0, 0x1105, 0x7814, 0xc0ed, 0xc0d5, 0x7816, + 0x781b, 0x0064, 0x2071, 0x0200, 0x0d7e, 0x2069, 0x4e40, 0x1078, + 0x4cdd, 0x2069, 0x4e80, 0x2071, 0x0100, 0x1078, 0x4cdd, 0x7814, + 0xc0d4, 0x7816, 0x0d7f, 0x0078, 0x110a, 0x7814, 0xc0e5, 0x7816, + 0x781b, 0x003c, 0x7eca, 0x7cc2, 0x7bc6, 0x7867, 0x0000, 0x7800, + 0xc08d, 0x7802, 0x2031, 0x0030, 0x78af, 0x0101, 0x7823, 0x0002, + 0x7827, 0x0002, 0x2009, 0x0002, 0x2069, 0x4e40, 0x681b, 0x0003, + 0x6823, 0x0007, 0x6827, 0x00fa, 0x682b, 0x0008, 0x682f, 0x0028, + 0x6837, 0x0000, 0x683b, 0x0006, 0x6833, 0x0008, 0x683f, 0x0000, + 0x8109, 0x0040, 0x115e, 0x68d3, 0x000a, 0x68c3, 0x4ec0, 0x2079, + 0x4e00, 0x7814, 0xd0e4, 0x00c0, 0x1144, 0xd0ec, 0x00c0, 0x1148, + 0x68d7, 0x7329, 0x0078, 0x114a, 0x68d7, 0x730d, 0x0078, 0x114a, + 0x68d7, 0x732d, 0x68c7, 0x53c0, 0x68cb, 0x52c0, 0x68cf, 0x93c0, + 0x68ab, 0x9644, 0x68af, 0x9649, 0x68b3, 0x9644, 0x68b7, 0x9644, + 0x68a7, 0x0001, 0x2069, 0x4e80, 0x0078, 0x111e, 0x68d3, 0x000a, + 0x68c3, 0x50c0, 0x7814, 0xd0e4, 0x00c0, 0x116a, 0x68d7, 0x7439, + 0x0078, 0x116c, 0x68d7, 0x7419, 0x68c7, 0x73c0, 0x68cb, 0x5340, + 0x68cf, 0x94d0, 0x68ab, 0x9649, 0x68af, 0x964e, 0x68b3, 0x9649, + 0x68b7, 0x9649, 0x68a7, 0x0001, 0x7810, 0xd0ec, 0x00c0, 0x11c2, + 0x7814, 0xd0e4, 0x00c0, 0x11b4, 0x0e7e, 0x2069, 0x52c0, 0x2071, + 0x0200, 0x70ec, 0xd0e4, 0x00c0, 0x1195, 0x2019, 0x0c0c, 0x2021, + 0x000c, 0x1078, 0x2009, 0x0078, 0x119b, 0x2019, 0x0c0a, 0x2021, + 0x000a, 0x1078, 0x2009, 0x2069, 0x5340, 0x2071, 0x0100, 0x70ec, + 0xd0e4, 0x00c0, 0x11ab, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x1078, + 0x2009, 0x0078, 0x11b1, 0x2019, 0x0c0a, 0x2021, 0x000a, 0x1078, + 0x2009, 0x0e7f, 0x0078, 0x11db, 0x2019, 0x0c0c, 0x2021, 0x000c, + 0x2069, 0x52c0, 0x1078, 0x2009, 0x2069, 0x5340, 0x1078, 0x2009, + 0x0078, 0x11db, 0x2069, 0x52c0, 0x0e7e, 0x2071, 0x0100, 0x70ec, + 0xd0e4, 0x00c0, 0x11d4, 0x2019, 0x0c0c, 0x2021, 0x000c, 0x1078, + 0x2009, 0x0e7f, 0x0078, 0x11db, 0x2019, 0x0c0a, 0x2021, 0x000a, + 0x1078, 0x2009, 0x0e7f, 0x2011, 0x0002, 0x2069, 0x53c0, 0x2009, + 0x0002, 0x20a9, 0x0100, 0x6837, 0x0000, 0x680b, 0x0040, 0x7bc8, + 0xa386, 0xfeff, 0x00c0, 0x11f2, 0x6817, 0x0100, 0x681f, 0x0064, + 0x0078, 0x11f6, 0x6817, 0x0064, 0x681f, 0x0002, 0xade8, 0x0010, + 0x00f0, 0x11e3, 0x8109, 0x00c0, 0x11e1, 0x8211, 0x0040, 0x1204, + 0x2069, 0x73c0, 0x0078, 0x11df, 0x1078, 0x265b, 0x1078, 0x468e, + 0x1078, 0x1dd4, 0x1078, 0x4c6f, 0x2091, 0x2100, 0x2079, 0x4e00, + 0x7810, 0xd0ec, 0x0040, 0x1218, 0x2071, 0x0020, 0x0078, 0x121a, + 0x2071, 0x0050, 0x2091, 0x2200, 0x2079, 0x4e00, 0x2071, 0x0020, + 0x2091, 0x2300, 0x2079, 0x4e00, 0x7810, 0xd0ec, 0x0040, 0x122c, + 0x2079, 0x0100, 0x0078, 0x122e, 0x2079, 0x0200, 0x2071, 0x4e40, + 0x2091, 0x2400, 0x2079, 0x0100, 0x2071, 0x4e80, 0x2091, 0x2000, + 0x2079, 0x4e00, 0x2071, 0x0010, 0x3200, 0xa085, 0x303d, 0x2090, + 0x2071, 0x0010, 0x70c3, 0x0000, 0x0090, 0x124d, 0x70c0, 0xa086, + 0x0002, 0x00c0, 0x124d, 0x1078, 0x15ba, 0x2039, 0x0000, 0x7810, + 0xd0ec, 0x00c0, 0x12cf, 0x1078, 0x148e, 0x78ac, 0xa005, 0x00c0, + 0x126b, 0x0068, 0x1261, 0x786c, 0xa065, 0x0040, 0x1261, 0x1078, + 0x2395, 0x1078, 0x20a1, 0x0068, 0x1278, 0x786c, 0xa065, 0x0040, + 0x126b, 0x1078, 0x2395, 0x0068, 0x1278, 0x2009, 0x4e47, 0x2011, + 0x4e87, 0x2104, 0x220c, 0xa105, 0x0040, 0x1278, 0x1078, 0x1f0a, + 0x2071, 0x4e40, 0x70a4, 0xa005, 0x0040, 0x129d, 0x7450, 0xa485, + 0x0000, 0x0040, 0x129d, 0x2079, 0x0200, 0x2091, 0x8000, 0x72d4, + 0xa28c, 0x303d, 0x2190, 0x1078, 0x2b6a, 0x2091, 0x8000, 0x2091, + 0x303d, 0x0068, 0x129d, 0x2079, 0x4e00, 0x786c, 0xa065, 0x0040, + 0x129d, 0x2071, 0x0010, 0x1078, 0x2395, 0x00e0, 0x12a5, 0x2079, + 0x4e00, 0x2071, 0x0010, 0x1078, 0x4a43, 0x2071, 0x4e80, 0x70a4, + 0xa005, 0x0040, 0x12bd, 0x7050, 0xa025, 0x0040, 0x12bd, 0x2079, + 0x0100, 0x2091, 0x8000, 0x72d4, 0xa28c, 0x303d, 0x2190, 0x1078, + 0x2b6a, 0x2091, 0x8000, 0x2091, 0x303d, 0x2079, 0x4e00, 0x2071, + 0x0010, 0x0068, 0x12c9, 0x786c, 0xa065, 0x0040, 0x12c9, 0x1078, + 0x2395, 0x00e0, 0x1253, 0x1078, 0x4a43, 0x0078, 0x1253, 0x1078, + 0x148e, 0x78ac, 0xa005, 0x00c0, 0x12e7, 0x0068, 0x12dd, 0x786c, + 0xa065, 0x0040, 0x12dd, 0x1078, 0x2395, 0x1078, 0x20a1, 0x0068, + 0x12f1, 0x786c, 0xa065, 0x0040, 0x12e7, 0x1078, 0x2395, 0x0068, + 0x12f1, 0x2009, 0x4e47, 0x2104, 0xa005, 0x0040, 0x12f1, 0x1078, + 0x1f0a, 0x2071, 0x4e40, 0x70a4, 0xa005, 0x0040, 0x130c, 0x7450, + 0xa485, 0x0000, 0x0040, 0x130c, 0x2079, 0x0100, 0x2091, 0x8000, + 0x72d4, 0xa28c, 0x303d, 0x2190, 0x1078, 0x2b6a, 0x2091, 0x8000, + 0x2091, 0x303d, 0x2079, 0x4e00, 0x2071, 0x0010, 0x0068, 0x1316, + 0x786c, 0xa065, 0x0040, 0x1316, 0x1078, 0x2395, 0x00e0, 0x12cf, + 0x1078, 0x4a43, 0x0078, 0x12cf, 0x133c, 0x133c, 0x133e, 0x133e, + 0x134b, 0x134b, 0x134b, 0x134b, 0x1356, 0x1356, 0x1363, 0x1363, + 0x134b, 0x134b, 0x134b, 0x134b, 0x133c, 0x133c, 0x133e, 0x133e, + 0x134b, 0x134b, 0x134b, 0x134b, 0x1356, 0x1356, 0x1363, 0x1363, + 0x134b, 0x134b, 0x134b, 0x134b, 0x0078, 0x133c, 0x007e, 0x107e, + 0x127e, 0x2091, 0x2400, 0x1078, 0x298a, 0x127f, 0x107f, 0x007f, + 0x2091, 0x8001, 0x007c, 0x007e, 0x107e, 0x127e, 0x1078, 0x13c8, + 0x127f, 0x107f, 0x007f, 0x2091, 0x8001, 0x007c, 0x007e, 0x107e, + 0x127e, 0x2091, 0x2300, 0x1078, 0x298a, 0x127f, 0x107f, 0x007f, + 0x2091, 0x8001, 0x007c, 0x007e, 0x107e, 0x127e, 0x2091, 0x2300, + 0x1078, 0x298a, 0x2091, 0x2400, 0x1078, 0x298a, 0x127f, 0x107f, + 0x007f, 0x2091, 0x8001, 0x007c, 0x1394, 0x1394, 0x1396, 0x1396, + 0x13a3, 0x13a3, 0x13a3, 0x13a3, 0x13ae, 0x13ae, 0x1396, 0x1396, + 0x13a3, 0x13a3, 0x13a3, 0x13a3, 0x13af, 0x13af, 0x13af, 0x13af, + 0x13af, 0x13af, 0x13af, 0x13af, 0x13af, 0x13af, 0x13af, 0x13af, + 0x13af, 0x13af, 0x13af, 0x13af, 0x0078, 0x1394, 0x007e, 0x107e, + 0x127e, 0x2091, 0x2300, 0x1078, 0x298a, 0x127f, 0x107f, 0x007f, + 0x2091, 0x8001, 0x007c, 0x007e, 0x107e, 0x127e, 0x1078, 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0x0040, 0x4a89, 0x6844, 0xa00d, 0x0040, + 0x4a89, 0x2104, 0xa005, 0x0040, 0x4a89, 0x8001, 0x200a, 0x0040, + 0x4c23, 0x6814, 0xa005, 0x0040, 0x4aae, 0x8001, 0x6816, 0x00c0, + 0x4aae, 0x68a7, 0x0001, 0x0f7e, 0xd7fc, 0x00c0, 0x4aa3, 0x7810, + 0xd0ec, 0x0040, 0x4a9f, 0x2079, 0x0100, 0x0078, 0x4aa5, 0x2079, + 0x0200, 0x0078, 0x4aa5, 0x2079, 0x0100, 0x1078, 0x4383, 0x0f7f, + 0x6864, 0xa005, 0x0040, 0x4aae, 0x1078, 0x2628, 0x6880, 0xa005, + 0x0040, 0x4abb, 0x8001, 0x6882, 0x00c0, 0x4abb, 0x6867, 0x0000, + 0x68d4, 0xc0dd, 0x68d6, 0x68d4, 0xd0fc, 0x0040, 0x4ad8, 0xc0fc, + 0x68d6, 0x20a9, 0x0200, 0x6034, 0xa005, 0x0040, 0x4ad4, 0x8001, + 0x6036, 0x68d4, 0xc0fd, 0x68d6, 0x00c0, 0x4ad4, 0x6010, 0xa005, + 0x0040, 0x4ad4, 0x1078, 0x2628, 0xace0, 0x0010, 0x00f0, 0x4ac3, + 0xd7fc, 0x0040, 0x4ae2, 0x2061, 0x53c0, 0x2069, 0x4e40, 0xc7fc, + 0x0078, 0x4a6a, 0x1078, 0x4b1e, 0x7838, 0x8001, 0x783a, 0x00c0, + 0x4b04, 0x783c, 0x783a, 0x2061, 0x53c0, 0x2069, 0x4e40, 0xc7fc, + 0x680c, 0xa005, 0x0040, 0x4af6, 0x1078, 0x4b88, 0xd7fc, 0x00c0, + 0x4b04, 0x7810, 0xd0ec, 0x00c0, 0x4b04, 0x2061, 0x73c0, 0x2069, + 0x4e80, 0xc7fd, 0x0078, 0x4af0, 0x7814, 0xd0e4, 0x00c0, 0x4b08, + 0x7810, 0xd0cc, 0x0040, 0x4b1b, 0xd0ac, 0x00c0, 0x4b14, 0xd0a4, + 0x0040, 0x4b1b, 0xc0ad, 0x7812, 0x2091, 0x8001, 0x0068, 0x4b1a, + 0x1078, 0x2395, 0x007c, 0x2091, 0x8001, 0x007c, 0x7840, 0x8001, + 0x7842, 0x00c0, 0x4b87, 0x7844, 0x7842, 0x2069, 0x4e40, 0xc7fc, + 0x7810, 0x2079, 0x0200, 0xd0ec, 0x0040, 0x4b30, 0x2079, 0x0100, + 0x68d8, 0xa005, 0x0040, 0x4b3c, 0x7de0, 0xa504, 0x00c0, 0x4b3c, + 0x68da, 0x68d4, 0xc0bc, 0x68d6, 0x2079, 0x4e00, 0x6810, 0xa005, + 0x00c0, 0x4b44, 0x2001, 0x0101, 0x8001, 0x6812, 0xd7fc, 0x0040, + 0x4b4d, 0xa080, 0x94d0, 0x0078, 0x4b4f, 0xa080, 0x93c0, 0x2040, + 0x2004, 0xa065, 0x0040, 0x4b79, 0x6024, 0xa005, 0x0040, 0x4b75, + 0x8001, 0x6026, 0x00c0, 0x4b75, 0x6800, 0xa005, 0x0040, 0x4b68, + 0x684c, 0xac06, 0x00c0, 0x4b68, 0x1078, 0x4c23, 0x0078, 0x4b79, + 0x6864, 0xa005, 0x0040, 0x4b70, 0x6027, 0x0001, 0x0078, 0x4b75, + 0x1078, 0x4bd6, 0x2804, 0x0078, 0x4b51, 0x6000, 0x2c40, 0x0078, + 0x4b51, 0xd7fc, 0x00c0, 0x4b87, 0x7810, 0xd0ec, 0x00c0, 0x4b87, + 0x2069, 0x4e80, 0xc7fd, 0x2079, 0x0100, 0x0078, 0x4b30, 0x007c, + 0x2009, 0x0000, 0x20a9, 0x0200, 0x6008, 0xd09c, 0x0040, 0x4bc2, + 0x6024, 0xa005, 0x0040, 0x4b98, 0x8001, 0x6026, 0x0078, 0x4bc0, + 0x6008, 0xc09c, 0xd084, 0x00c0, 0x4ba0, 0xd0ac, 0x0040, 0x4bba, + 0x600a, 0x6004, 0xa005, 0x0040, 0x4bc2, 0x0d7e, 0x0c7e, 0x017e, + 0x2068, 0x6010, 0x8001, 0x6012, 0x1078, 0x3dd0, 0x2d00, 0x2c68, + 0x2060, 0x1078, 0x1e5b, 0x1078, 0x201d, 0x017f, 0x0c7f, 0x0d7f, + 0x0078, 0x4bc2, 0xc0bd, 0x600a, 0xa18d, 0x0001, 0x0078, 0x4bc2, + 0xa18d, 0x0100, 0xace0, 0x0010, 0x00f0, 0x4b8c, 0xa184, 0x0001, + 0x0040, 0x4bd1, 0xa18c, 0xfffe, 0x690e, 0x1078, 0x2628, 0x0078, + 0x4bd2, 0x690e, 0x007c, 0x00c0, 0x4bd2, 0x786c, 0x2c00, 0x687e, + 0x6714, 0x6f76, 0x6017, 0x0000, 0x602b, 0x0000, 0x601b, 0x0006, + 0x60b4, 0xa084, 0x3f00, 0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, + 0x0060, 0x6022, 0x6000, 0x2042, 0x1078, 0x1de4, 0x6818, 0xa005, + 0x0040, 0x4bf4, 0x8001, 0x681a, 0x6808, 0xc0a4, 0x680a, 0x6810, + 0x7908, 0x8109, 0x790a, 0x8001, 0x00d0, 0x4c00, 0x1078, 0x296b, + 0x6812, 0x00c0, 0x4c06, 0x7910, 0xc1a5, 0x7912, 0x602f, 0x0000, + 0x6033, 0x0000, 0x2c68, 0x1078, 0x202c, 0xd7fc, 0x00c0, 0x4c14, + 0x2069, 0x4e40, 0x0078, 0x4c16, 0x2069, 0x4e80, 0x6910, 0xa184, + 0x0100, 0x2001, 0x0006, 0x00c0, 0x4c20, 0x697a, 0x2001, 0x0004, + 0x1078, 0x261c, 0x007c, 0x0d7e, 0x694c, 0x2160, 0xd7fc, 0x00c0, + 0x4c35, 0x7810, 0xd0ec, 0x0040, 0x4c31, 0x2069, 0x0100, 0x0078, + 0x4c37, 0x2069, 0x0200, 0x0078, 0x4c37, 0x2069, 0x0100, 0x1078, + 0x28df, 0x601b, 0x0006, 0x6858, 0xa084, 0x3f00, 0x601e, 0x6020, + 0xa084, 0x00ff, 0xa085, 0x0048, 0x6022, 0x602f, 0x0000, 0x6033, + 0x0000, 0x6808, 0xa084, 0xfffd, 0x680a, 0x6830, 0xd0b4, 0x0040, + 0x4c69, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848, 0xd094, 0x0040, + 0x4c5b, 0x00f0, 0x4c55, 0x684b, 0x0009, 0x20a9, 0x0014, 0x6848, + 0xd084, 0x0040, 0x4c65, 0x00f0, 0x4c5f, 0x20a9, 0x00fa, 0x00f0, + 0x4c67, 0x681b, 0x0047, 0x0d7f, 0x6867, 0x0007, 0x007c, 0x2079, + 0x4e00, 0x1078, 0x4ca3, 0x1078, 0x4c89, 0x1078, 0x4c96, 0x2009, + 0x0002, 0x2069, 0x4e80, 0x680f, 0x0000, 0x6813, 0x0000, 0x6817, + 0x0000, 0x8109, 0x0040, 0x4c88, 0x2069, 0x4e40, 0x0078, 0x4c7b, + 0x007c, 0x7810, 0xd0ec, 0x0040, 0x4c91, 0x2019, 0x00cc, 0x0078, + 0x4c93, 0x2019, 0x007b, 0x7b3a, 0x7b3e, 0x007c, 0x7814, 0xd0e4, + 0x00c0, 0x4c9e, 0x2019, 0x0040, 0x0078, 0x4ca0, 0x2019, 0x0026, + 0x7b42, 0x7b46, 0x007c, 0x7814, 0xd0e4, 0x00c0, 0x4cab, 0x2019, + 0x3f94, 0x0078, 0x4cad, 0x2019, 0x2624, 0x7b32, 0x7b36, 0x007c, + 0x6a50, 0xa285, 0x0000, 0x0040, 0x4cdc, 0x6954, 0x6bc0, 0xa300, + 0x0c7e, 0x2164, 0x6304, 0x83ff, 0x00c0, 0x4cc8, 0x8211, 0x0040, + 0x4ccc, 0x8108, 0xa11a, 0x0048, 0x4cb9, 0x69c0, 0x0078, 0x4cb9, + 0x68d3, 0x000a, 0x0c7f, 0x007c, 0x6950, 0x6ac0, 0x2264, 0x602b, + 0x0000, 0x602f, 0x0000, 0x6008, 0xc0b5, 0x600a, 0x8210, 0x8109, + 0x00c0, 0x4cce, 0x6952, 0x0c7f, 0x007c, 0x00e0, 0x4cdd, 0x2091, + 0x6000, 0x00e0, 0x4ce1, 0x2091, 0x6000, 0x70ec, 0xd0dc, 0x00c0, + 0x4cee, 0xd0d4, 0x0040, 0x4d17, 0x0078, 0x4d1a, 0x2008, 0x7810, + 0xd0ec, 0x0040, 0x4d01, 0xd1c4, 0x00c0, 0x4d39, 0x7814, 0xc0c5, + 0x7816, 0x7810, 0xc0f5, 0x7812, 0xd0ec, 0x0040, 0x4d35, 0x0078, + 0x4d31, 0xae8e, 0x0100, 0x0040, 0x4d0e, 0x7814, 0xc0f5, 0xc0c5, + 0x7816, 0xd0d4, 0x00c0, 0x4d35, 0x0078, 0x4d31, 0x7814, 0xc0fd, + 0xc0c5, 0x7816, 0xd0d4, 0x00c0, 0x4d35, 0x0078, 0x4d31, 0xd0e4, + 0x0040, 0x4d37, 0x00e0, 0x4d1a, 0x2091, 0x6000, 0x2009, 0x000c, + 0x00e0, 0x4d20, 0x2091, 0x6000, 0x8109, 0x00c0, 0x4d20, 0x70e4, + 0xa084, 0x01ff, 0xa086, 0x01ff, 0x00c0, 0x4d31, 0x70ec, 0x0078, + 0x4cee, 0x7804, 0xd08c, 0x0040, 0x4d37, 0x681f, 0x000c, 0x70a0, + 0x70a2, 0x007c, 0x205b +}; +#else +/************************************************************************ + * * + * --- ISP1240/ISP1080/ISP1280 Initiator/Target Firmware --- * + * 32 LUN Support * + * * + ************************************************************************/ +/* + * Firmware Version 9.11.01 (15:46 May 23, 2000) + */ + +static const u_int16_t isp_1080_risc_code[] = { + 0x0078, 0x103a, 0x0000, 0x4f62, 0x0000, 0x2043, 0x4f50, 0x5952, + 0x4947, 0x4854, 0x2031, 0x3939, 0x3520, 0x514c, 0x4f47, 0x4943, + 0x2043, 0x4f52, 0x504f, 0x5241, 0x5449, 0x4f4e, 0x2049, 0x5350, + 0x3132, 0x3430, 0x2049, 0x2f54, 0x2046, 0x6972, 0x6d77, 0x6172, + 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, 0x392e, 0x3131, + 0x2020, 0x2043, 0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, + 0x3030, 0x2050, 0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2020, + 0x3031, 0x2024, 0x20c9, 0xabff, 0x2001, 0x04fc, 0x2004, 0xa086, + 0x1080, 0x00c0, 0x104d, 0x2071, 0x0100, 0x70a0, 0x70a2, 0x20c1, + 0x0010, 0x2089, 0x136f, 0x0078, 0x1066, 0x2001, 0x04fc, 0x2004, + 0xa086, 0x1280, 0x00c0, 0x1062, 0x2071, 0x0200, 0x70a0, 0x70a2, + 0x2071, 0x0100, 0x70a0, 0x70a2, 0x20c1, 0x0010, 0x2089, 0x13f3, + 0x0078, 0x1066, 0x20c1, 0x0020, 0x2089, 0x1317, 0x2071, 0x0010, + 0x70c3, 0x0004, 0x70c7, 0x4953, 0x70cb, 0x5020, 0x70cf, 0x2020, + 0x70d3, 0x0009, 0x2001, 0x04fd, 0x70d6, 0x20c1, 0x0021, 0x2019, + 0x0000, 0x2009, 0xfeff, 0x2100, 0x200b, 0xa5a5, 0xa1ec, 0x7fff, + 0x2d64, 0x206b, 0x0a0a, 0xaddc, 0x3fff, 0x2b54, 0x205b, 0x5050, + 0x2114, 0xa286, 0xa5a5, 0x0040, 0x109d, 0xa386, 0x000f, 0x0040, + 0x1099, 0x2c6a, 0x2a5a, 0x20c1, 0x0020, 0x2019, 0x000f, 0x0078, + 0x1079, 0x2c6a, 0x2a5a, 0x0078, 0x109b, 0x2c6a, 0x2a5a, 0x2130, + 0x2128, 0xa1a2, 0x6000, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, + 0x8424, 0xa192, 0xac00, 0x2009, 0x0000, 0x2001, 0x0037, 0x1078, + 0x22c0, 0x2218, 0x2079, 0x6000, 0x2fa0, 0x2408, 0x2011, 0x0000, + 0x20a9, 0x0040, 0x42a4, 0x8109, 0x00c0, 0x10b8, 0x2009, 0xff00, + 0x3400, 0xa102, 0x0048, 0x10c8, 0x0040, 0x10c8, 0x20a8, 0x42a4, + 0x2001, 0x04fc, 0x2004, 0xa086, 0x1080, 0x00c0, 0x10e0, 0x2071, + 0x0100, 0x0d7e, 0x2069, 0x6040, 0x1078, 0x5d94, 0x0d7f, 0x7808, + 0xc0ed, 0x780a, 0x7813, 0x0064, 0x2011, 0x000a, 0x0078, 0x1107, + 0x2001, 0x04fc, 0x2004, 0xa086, 0x1280, 0x00c0, 0x1100, 0x780c, + 0xc0ed, 0xc0d5, 0x780e, 0x7813, 0x0064, 0x2071, 0x0200, 0x0d7e, + 0x2069, 0x6040, 0x1078, 0x5d94, 0x2069, 0x6080, 0x2071, 0x0100, + 0x1078, 0x5d94, 0x780c, 0xc0d4, 0x780e, 0x0d7f, 0x0078, 0x1107, + 0x780c, 0xc0e5, 0x780e, 0x7813, 0x003c, 0x2011, 0x000c, 0x2009, + 0x604c, 0x220a, 0x2009, 0x608c, 0x220a, 0x7ece, 0x7cc6, 0x7bca, + 0x785f, 0x0000, 0x7800, 0xc08d, 0x7802, 0x2031, 0x0030, 0x78b3, + 0x0101, 0x781b, 0x0002, 0x781f, 0x0002, 0x2009, 0x0002, 0x2069, + 0x6040, 0x6817, 0x0003, 0x681f, 0x0007, 0x6823, 0x00fa, 0x6827, + 0x0008, 0x682b, 0x0028, 0x6837, 0x0006, 0x682f, 0x0008, 0x683b, + 0x0000, 0x8109, 0x0040, 0x1158, 0x68ef, 0x000a, 0x68df, 0x60c0, + 0x2079, 0x6000, 0x780c, 0xd0e4, 0x00c0, 0x1142, 0x68f3, 0x7329, + 0x0078, 0x1144, 0x68f3, 0x730d, 0x68e3, 0x65c0, 0x68e7, 0x64c0, + 0x68eb, 0xa5c0, 0x68c7, 0xaa8e, 0x68cb, 0xaa93, 0x68cf, 0xaa8e, + 0x68d3, 0xaa8e, 0x68c3, 0x0001, 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0x007c, 0x2c00, 0x6882, 0x6714, 0x6f7a, + 0x6017, 0x0000, 0x602b, 0x0000, 0x601b, 0x0006, 0x60b4, 0xa084, + 0x5f00, 0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, 0x0060, 0x6022, + 0x6000, 0x2042, 0x6860, 0xac06, 0x00c0, 0x5c98, 0x2800, 0x6862, + 0x1078, 0x1e6e, 0x6818, 0xa005, 0x0040, 0x5cc8, 0x8001, 0x681a, + 0x681a, 0x6808, 0xc0a4, 0x680a, 0x6810, 0x8001, 0x0050, 0x5cc8, + 0x6812, 0x602f, 0x0000, 0x6033, 0x0000, 0x2c68, 0x1078, 0x2251, + 0xd7fc, 0x00c0, 0x5cb7, 0x2069, 0x6040, 0x0078, 0x5cb9, 0x2069, + 0x6080, 0x690c, 0xa184, 0x0100, 0x2001, 0x0006, 0x00c0, 0x5cc5, + 0x6883, 0x0000, 0x697e, 0x2001, 0x0004, 0x2708, 0x1078, 0x2845, + 0x007c, 0x0d7e, 0x0e7e, 0x2d70, 0xd7fc, 0x00c0, 0x5cdb, 0x7808, + 0xd0ec, 0x0040, 0x5cd7, 0x2069, 0x0100, 0x0078, 0x5cdd, 0x2069, + 0x0200, 0x0078, 0x5cdd, 0x2069, 0x0100, 0x7000, 0xa084, 0x000f, + 0x0040, 0x5d27, 0xa086, 0x0007, 0x00c0, 0x5cef, 0x0f7e, 0x2d78, + 0x7094, 0x2068, 0x1078, 0x4694, 0x0f7f, 0x0078, 0x5d27, 0x7050, + 0x2060, 0x1078, 0x2b67, 0x601b, 0x0006, 0x6858, 0xa084, 0x5f00, + 0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, 0x0048, 0x6022, 0x602f, + 0x0000, 0x6033, 0x0000, 0x6808, 0xa084, 0xfffd, 0x680a, 0x6830, + 0xd0b4, 0x0040, 0x5d23, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848, + 0xd094, 0x0040, 0x5d15, 0x00f0, 0x5d0f, 0x684b, 0x0009, 0x20a9, + 0x0014, 0x6848, 0xd084, 0x0040, 0x5d1f, 0x00f0, 0x5d19, 0x20a9, + 0x00fa, 0x00f0, 0x5d21, 0x681b, 0x0048, 0x706b, 0x0007, 0x0e7f, + 0x0d7f, 0x007c, 0x2079, 0x6000, 0x1078, 0x5d5e, 0x1078, 0x5d44, + 0x1078, 0x5d51, 0x2009, 0x0002, 0x2069, 0x6080, 0x680b, 0x0000, + 0x680f, 0x0000, 0x6813, 0x0000, 0x8109, 0x0040, 0x5d43, 0x2069, + 0x6040, 0x0078, 0x5d36, 0x007c, 0x7808, 0xd0ec, 0x0040, 0x5d4c, + 0x2019, 0x00cc, 0x0078, 0x5d4e, 0x2019, 0x007b, 0x7b32, 0x7b36, + 0x007c, 0x780c, 0xd0e4, 0x00c0, 0x5d59, 0x2019, 0x0040, 0x0078, + 0x5d5b, 0x2019, 0x0026, 0x7b3a, 0x7b3e, 0x007c, 0x780c, 0xd0e4, + 0x00c0, 0x5d66, 0x2019, 0x3f94, 0x0078, 0x5d68, 0x2019, 0x2626, + 0x7b2a, 0x7b2e, 0x007c, 0x6a54, 0xa285, 0x0000, 0x0040, 0x5d93, + 0x6958, 0x6bdc, 0xa300, 0x0c7e, 0x2164, 0x6304, 0x83ff, 0x00c0, + 0x5d83, 0x8211, 0x0040, 0x5d87, 0x8108, 0xa11a, 0x0048, 0x5d74, + 0x69dc, 0x0078, 0x5d74, 0x68ef, 0x000a, 0x0c7f, 0x007c, 0x6954, + 0x6adc, 0x2264, 0x6008, 0xc0b5, 0x600a, 0x8210, 0x8109, 0x00c0, + 0x5d89, 0x6956, 0x0c7f, 0x007c, 0x00e0, 0x5d94, 0x2091, 0x6000, + 0x00e0, 0x5d98, 0x2091, 0x6000, 0x70ec, 0xd0dc, 0x00c0, 0x5da5, + 0xd0d4, 0x0040, 0x5dce, 0x0078, 0x5dd1, 0x2008, 0x7808, 0xd0ec, + 0x0040, 0x5db8, 0xd1c4, 0x00c0, 0x5df0, 0x780c, 0xc0c5, 0x780e, + 0x7808, 0xc0f5, 0x780a, 0xd0ec, 0x0040, 0x5dec, 0x0078, 0x5de8, + 0xae8e, 0x0100, 0x0040, 0x5dc5, 0x780c, 0xc0f5, 0xc0c5, 0x780e, + 0xd0d4, 0x00c0, 0x5dec, 0x0078, 0x5de8, 0x780c, 0xc0fd, 0xc0c5, + 0x780e, 0xd0d4, 0x00c0, 0x5dec, 0x0078, 0x5de8, 0xd0e4, 0x0040, + 0x5dee, 0x00e0, 0x5dd1, 0x2091, 0x6000, 0x2009, 0x000c, 0x00e0, + 0x5dd7, 0x2091, 0x6000, 0x8109, 0x00c0, 0x5dd7, 0x70e4, 0xa084, + 0x01ff, 0xa086, 0x01ff, 0x00c0, 0x5de8, 0x70ec, 0x0078, 0x5da5, + 0x7804, 0xd08c, 0x0040, 0x5dee, 0x681b, 0x000c, 0x70a0, 0x70a2, + 0x007c, 0x0020, 0x002b, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, + 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, + 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, + 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, + 0x0020, 0x0000, 0x0020, 0x0000, 0x0014, 0x0014, 0x9849, 0x0014, + 0x0014, 0x98ec, 0x98d6, 0x0014, 0x0014, 0x0014, 0x0080, 0x0140, + 0x0000, 0x0201, 0x0604, 0x0c08, 0x2120, 0x4022, 0xf880, 0x0018, + 0x300b, 0xa201, 0x0014, 0xa200, 0x0014, 0xa200, 0x0214, 0xa202, + 0x3806, 0x7102, 0x805f, 0x9481, 0x8839, 0x20c3, 0x0864, 0xa834, + 0x28c1, 0x9cb9, 0xa203, 0x300c, 0x2846, 0x8161, 0x846a, 0x8300, + 0x1856, 0x883a, 0xa804, 0x28f2, 0x9c9d, 0xa8f4, 0x300c, 0x28e1, + 0x9c9d, 0x2822, 0xa207, 0x64a4, 0x2001, 0xa811, 0xa206, 0x64c0, + 0x6de0, 0x67a0, 0x6fc0, 0x882b, 0x1814, 0x883b, 0x7824, 0x68c1, + 0x7864, 0x883e, 0xa802, 0x8576, 0x8677, 0x80df, 0x94a1, 0x206c, + 0x28c1, 0x9cb9, 0x2045, 0x2104, 0x20a1, 0x2080, 0x7961, 0xa8df, + 0xa209, 0x0904, 0xa20e, 0xa808, 0xa205, 0xa300, 0x1872, 0x879a, + 0x883c, 0x1fe2, 0xc601, 0xa20a, 0x8000, 0x85a1, 0x806f, 0x9422, + 0x84a2, 0x856e, 0x0704, 0x9c9d, 0x0014, 0xa204, 0xa300, 0x3009, + 0x19e2, 0xf864, 0x856e, 0x883f, 0x08e6, 0xa8f7, 0xf881, 0xa8eb, + 0xc007, 0xf8c1, 0x0016, 0x85b2, 0x80f0, 0x9532, 0xfb02, 0x1de2, + 0x0014, 0x8532, 0xf241, 0x0014, 0x1de2, 0x84a8, 0xd7a0, 0x1fe6, + 0x0014, 0xa208, 0x6043, 0x8008, 0x1dc1, 0x0016, 0x8300, 0x8160, + 0x842a, 0xf041, 0x3008, 0x84a8, 0x11d6, 0x7042, 0x20dd, 0x0011, + 0x20d5, 0x8822, 0x0016, 0x3008, 0x2845, 0x1011, 0xa8fd, 0x2802, + 0x1011, 0xa8fd, 0xa894, 0x283e, 0x1011, 0xa8fd, 0xa20b, 0x7102, + 0x805f, 0x9481, 0x0017, 0x300c, 0xa300, 0x1de2, 0xd387, 0x0210, + 0xa800, 0x26e0, 0x873a, 0xfb02, 0x19f2, 0x1fe2, 0x0014, 0xa20d, + 0x3806, 0x0210, 0x9cbe, 0x0704, 0x0017, 0x60ff, 0x300c, 0x8720, + 0xa211, 0x7102, 0x805f, 0x9481, 0x8000, 0x8300, 0x8772, 0x8837, + 0x2101, 0xa821, 0x10d2, 0x78e2, 0x9d5c, 0xa8fc, 0xd984, 0xf0e2, + 0xf0a1, 0xa820, 0x0014, 0x8831, 0xd166, 0x8830, 0x800f, 0x9401, + 0xb520, 0xc802, 0x8820, 0xa80f, 0x2301, 0xa80d, 0x10d2, 0x78e4, + 0x9d5c, 0x8821, 0x8820, 0xa8e6, 0xf123, 0xf142, 0xf101, 0xa855, + 0x10d2, 0x70f6, 0x8832, 0x8203, 0x870c, 0xd99e, 0x6001, 0x0014, + 0x6848, 0x0214, 0x8827, 0x300a, 0x0013, 0xa21b, 0x8300, 0x2001, + 0xa843, 0x8201, 0x1852, 0xd183, 0x8834, 0x8001, 0xa801, 0x3027, + 0x84a8, 0x1a56, 0x8833, 0x0014, 0xa218, 0x6981, 0x9d63, 0x692b, + 0x6902, 0x1a34, 0xa806, 0x8080, 0x9521, 0xc002, 0x1a94, 0xa801, + 0x1a14, 0x7021, 0x0014, 0xa300, 0x69e4, 0x8023, 0x16e1, 0x8001, + 0x10f1, 0x6946, 0xa213, 0x1462, 0xa213, 0x8000, 0x16e1, 0xa808, + 0x6161, 0x0014, 0xa214, 0x61c2, 0x8002, 0x14e1, 0x8004, 0x16e1, + 0x0101, 0x300a, 0x8827, 0x0014, 0x11c2, 0x211e, 0x870e, 0xa21d, + 0x0014, 0x9d63, 0x0014, 0xa300, 0x8181, 0x842a, 0x84a8, 0x1ce6, + 0x882c, 0x0016, 0xa212, 0x8300, 0x10d2, 0x70e4, 0x0004, 0x8007, + 0x9424, 0xcc1a, 0x9d5c, 0xa8f8, 0x878e, 0x0016, 0xa21c, 0x1035, + 0xa8bb, 0xa210, 0x3807, 0x300c, 0x817e, 0x872b, 0x8772, 0x0014, + 0x0000, 0xd27a +}; +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/firmware/asm_12160.h 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,4198 @@ +/* @(#)asm_12160.h 1.3 */ +/* + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Qlogic, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted provided + * that the following conditions are met: + * 1. Redistribution of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistribution in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/************************************************************************ + * * + * --- ISP12160A Initiator/Target RISC Firmware --- * + * 32 LUN Support * + * * + ************************************************************************/ +#ifndef ISP_TARGET_MODE +/* + * Firmware Version 10.04.32 (12:03 May 09, 2001) + */ +static const u_int16_t isp_12160_risc_code[] = { + 0x0804, 0x1041, 0x0000, 0x35e6, 0x0000, 0x2043, 0x4f50, 0x5952, + 0x4947, 0x4854, 0x2031, 0x3939, 0x312c, 0x3139, 0x3932, 0x2c31, + 0x3939, 0x332c, 0x3139, 0x3934, 0x2051, 0x4c4f, 0x4749, 0x4320, + 0x434f, 0x5250, 0x4f52, 0x4154, 0x494f, 0x4e00, 0x2049, 0x5350, + 0x3132, 0x3136, 0x2046, 0x6972, 0x6d77, 0x6172, 0x6520, 0x2056, + 0x6572, 0x7369, 0x6f6e, 0x2031, 0x302e, 0x3034, 0x2020, 0x2043, + 0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, 0x3030, 0x2050, + 0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2020, 0x3030, 0x2020, + 0x2400, 0x20c9, 0x8fff, 0x2071, 0x0200, 0x70a0, 0x70a2, 0x2001, + 0x01ff, 0x2004, 0xd0fc, 0x1120, 0x2071, 0x0100, 0x70a0, 0x70a2, + 0x20c1, 0x0020, 0x2089, 0x1221, 0x2071, 0x0010, 0x70c3, 0x0004, + 0x70c7, 0x4953, 0x70cb, 0x5020, 0x70cf, 0x2020, 0x70d3, 0x000a, + 0x2001, 0x04fd, 0x2004, 0x70d6, 0x2009, 0xfeff, 0x2130, 0x2128, + 0xa1a2, 0x4600, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, 0x8424, + 0xa192, 0x9000, 0x2009, 0x0000, 0x2001, 0x0032, 0x080c, 0x1de8, + 0x2218, 0x2079, 0x4600, 0x2fa0, 0x2408, 0x2011, 0x0000, 0x20a9, + 0x0040, 0x42a4, 0x8109, 0x1dd8, 0x2009, 0xff00, 0x3400, 0xa102, + 0x0218, 0x0110, 0x20a8, 0x42a4, 0x781b, 0x0064, 0x7814, 0xc0cd, + 0xc0d5, 0x7816, 0x2071, 0x0200, 0x00d6, 0x2069, 0x4640, 0x080c, + 0x459a, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1130, 0x2069, 0x4680, + 0x2071, 0x0100, 0x080c, 0x459a, 0x7814, 0xc0d4, 0x7816, 0x00de, + 0x7eca, 0x7cc2, 0x7bc6, 0x7867, 0x0000, 0x7800, 0xc08d, 0x7802, + 0x2031, 0x0030, 0x78af, 0x0101, 0x7823, 0x0002, 0x7827, 0x0002, + 0x2009, 0x0002, 0x2069, 0x4640, 0x681b, 0x0003, 0x6823, 0x0007, + 0x6827, 0x00fa, 0x682b, 0x0008, 0x682f, 0x0028, 0x6837, 0x0006, + 0x6833, 0x0008, 0x683b, 0x0000, 0x8109, 0x0500, 0x68cf, 0x000a, + 0x68bf, 0x46c0, 0x2079, 0x4600, 0x68d3, 0x762d, 0x68c3, 0x4bc0, + 0x68c7, 0x4ac0, 0x68cb, 0x8bc0, 0x68a7, 0x8e44, 0x68ab, 0x8e49, + 0x68af, 0x8e44, 0x68b3, 0x8e44, 0x68a3, 0x0001, 0x2001, 0x01ff, + 0x2004, 0xd0fc, 0x11c8, 0x2069, 0x4680, 0x0870, 0x68cf, 0x000a, + 0x68bf, 0x48c0, 0x68d3, 0x7839, 0x68c3, 0x6bc0, 0x68c7, 0x4b40, + 0x68cb, 0x8cd0, 0x68a7, 0x8e49, 0x68ab, 0x8e4e, 0x68af, 0x8e49, + 0x68b3, 0x8e49, 0x68a3, 0x0001, 0x00e6, 0x2069, 0x4ac0, 0x2071, + 0x0200, 0x70ec, 0xd0e4, 0x2019, 0x1809, 0x2021, 0x0009, 0x1120, + 0x2019, 0x180c, 0x2021, 0x000c, 0x080c, 0x1d58, 0x2001, 0x01ff, + 0x2004, 0xd0fc, 0x1188, 0x2069, 0x4b40, 0x2071, 0x0100, 0x70ec, + 0xd0e4, 0x2019, 0x1809, 0x2021, 0x0009, 0x1120, 0x2019, 0x180c, + 0x2021, 0x000c, 0x080c, 0x1d58, 0x00ee, 0x2011, 0x0002, 0x2069, + 0x4bc0, 0x2009, 0x0002, 0x20a9, 0x0100, 0x6837, 0x0000, 0x680b, + 0x0040, 0x7bc8, 0xa386, 0xfeff, 0x1128, 0x6817, 0x0100, 0x681f, + 0x0064, 0x0020, 0x6817, 0x0064, 0x681f, 0x0002, 0xade8, 0x0010, + 0x1f04, 0x1135, 0x8109, 0x1d38, 0x2001, 0x01ff, 0x2004, 0xd0fc, + 0x1128, 0x8211, 0x0118, 0x2069, 0x6bc0, 0x08d8, 0x080c, 0x22cf, + 0x080c, 0x4015, 0x080c, 0x1b6d, 0x080c, 0x4553, 0x2091, 0x2200, + 0x2079, 0x4600, 0x2071, 0x0050, 0x2091, 0x2400, 0x2079, 0x4600, + 0x2071, 0x0020, 0x2091, 0x2600, 0x2079, 0x0200, 0x2071, 0x4640, + 0x2091, 0x2800, 0x2079, 0x0100, 0x2071, 0x4680, 0x2091, 0x2000, + 0x2079, 0x4600, 0x2071, 0x0010, 0x3200, 0xa085, 0x303d, 0x2090, + 0x2071, 0x0010, 0x70c3, 0x0000, 0x1004, 0x118c, 0x70c0, 0xa086, + 0x0002, 0x1110, 0x080c, 0x13ba, 0x2039, 0x0000, 0x080c, 0x12ab, + 0x78ac, 0xa005, 0x1180, 0x0e04, 0x119a, 0x786c, 0xa065, 0x0110, + 0x080c, 0x207a, 0x080c, 0x1e09, 0x0e04, 0x11af, 0x786c, 0xa065, + 0x0110, 0x080c, 0x207a, 0x0e04, 0x11af, 0x2009, 0x4647, 0x2011, + 0x4687, 0x2104, 0x220c, 0xa105, 0x0110, 0x080c, 0x1c7c, 0x2071, + 0x4640, 0x70a0, 0xa005, 0x01e8, 0x744c, 0xa485, 0x0000, 0x01c8, + 0x2079, 0x0200, 0x2091, 0x8000, 0x72d0, 0xa28c, 0x303d, 0x2190, + 0x080c, 0x2720, 0x2091, 0x8000, 0x2091, 0x303d, 0x0e04, 0x11d1, + 0x2079, 0x4600, 0x786c, 0xa065, 0x0120, 0x2071, 0x0010, 0x080c, + 0x207a, 0x1d04, 0x11d9, 0x2079, 0x4600, 0x2071, 0x0010, 0x080c, + 0x4370, 0x2071, 0x4680, 0x70a0, 0xa005, 0x0188, 0x704c, 0xa025, + 0x0170, 0x2079, 0x0100, 0x2091, 0x8000, 0x72d0, 0xa28c, 0x303d, + 0x2190, 0x080c, 0x2720, 0x2091, 0x8000, 0x2091, 0x303d, 0x2079, + 0x4600, 0x2071, 0x0010, 0x0e04, 0x11fa, 0x786c, 0xa065, 0x0110, + 0x080c, 0x207a, 0x1d04, 0x118e, 0x080c, 0x4370, 0x0804, 0x118e, + 0x3c00, 0xa084, 0x0007, 0x0002, 0x120c, 0x120c, 0x120e, 0x120e, + 0x1213, 0x1213, 0x1218, 0x1218, 0x080c, 0x254c, 0x2091, 0x2400, + 0x080c, 0x40ad, 0x0005, 0x2091, 0x2200, 0x080c, 0x40ad, 0x0005, + 0x2091, 0x2200, 0x080c, 0x40ad, 0x2091, 0x2400, 0x080c, 0x40ad, + 0x0005, 0x1241, 0x1241, 0x1242, 0x1242, 0x124d, 0x124d, 0x124d, + 0x124d, 0x1256, 0x1256, 0x1261, 0x1261, 0x124d, 0x124d, 0x124d, + 0x124d, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, + 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, 0x1270, + 0x1270, 0x0cf8, 0x0006, 0x0106, 0x0126, 0x2091, 0x2800, 0x080c, + 0x2569, 0x012e, 0x010e, 0x000e, 0x000d, 0x0006, 0x0106, 0x0126, + 0x080c, 0x1200, 0x012e, 0x010e, 0x000e, 0x000d, 0x0006, 0x0106, + 0x0126, 0x2091, 0x2600, 0x080c, 0x2569, 0x012e, 0x010e, 0x000e, + 0x000d, 0x0006, 0x0106, 0x0126, 0x2091, 0x2600, 0x080c, 0x2569, + 0x2091, 0x2800, 0x080c, 0x2569, 0x012e, 0x010e, 0x000e, 0x000d, + 0x0006, 0x0106, 0x0126, 0x00d6, 0x00e6, 0x00f6, 0x2079, 0x4600, + 0x2071, 0x0200, 0x2069, 0x4640, 0x3d00, 0xd08c, 0x0130, 0x70ec, + 0xa084, 0x1c00, 0x78e2, 0x080c, 0x459a, 0x3d00, 0xd084, 0x0150, + 0x2069, 0x4680, 0x2071, 0x0100, 0x70ec, 0xa084, 0x1c00, 0x78e6, + 0x080c, 0x459a, 0x080c, 0x24fd, 0x00fe, 0x00ee, 0x00de, 0x012e, + 0x010e, 0x000e, 0x000d, 0x7008, 0x800b, 0x1240, 0x7007, 0x0002, + 0xa08c, 0x01e0, 0x1120, 0xd09c, 0x0108, 0x0887, 0x0897, 0x70c3, + 0x4002, 0x0804, 0x13bd, 0x0e04, 0x131e, 0x2061, 0x0000, 0x6018, + 0xd084, 0x1904, 0x131e, 0x7828, 0xa005, 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0xa184, 0x01e0, + 0x0118, 0x080c, 0x40e6, 0x00b0, 0x7007, 0x0012, 0x7007, 0x0008, + 0x7004, 0xd09c, 0x1de8, 0x7108, 0x7008, 0xa106, 0x1de0, 0xa184, + 0x01e0, 0x0118, 0x080c, 0x40e6, 0x0028, 0x7007, 0x0012, 0x7108, + 0x8103, 0x0e88, 0x7003, 0x0008, 0x0005, 0x7108, 0xa184, 0x01e0, + 0x15a8, 0x7108, 0xa184, 0x01e0, 0x1588, 0xa184, 0x0007, 0x0002, + 0x40c2, 0x40d0, 0x40c0, 0x40d0, 0x40c0, 0x4120, 0x40c0, 0x411e, + 0x080c, 0x254c, 0x7004, 0xa084, 0x0010, 0xc08d, 0x7006, 0x8aff, + 0x1118, 0x2049, 0x0000, 0x0005, 0x080c, 0x426b, 0x1de8, 0x0005, + 0x7004, 0xa084, 0x0010, 0xc08d, 0x7006, 0x7004, 0xd084, 0x1140, + 0x7108, 0x7008, 0xa106, 0x1de0, 0xa184, 0x0003, 0x0108, 0x0030, + 0x8aff, 0x0118, 0x080c, 0x426b, 0x1de8, 0x0005, 0x7007, 0x0012, + 0x7108, 0x1d04, 0x40e9, 0x2091, 0x6000, 0x1d04, 0x40ed, 0x2091, + 0x6000, 0x7007, 0x0012, 0x7007, 0x0008, 0x7004, 0xd09c, 0x1de8, + 0x7007, 0x0012, 0x7108, 0xd1fc, 0x1dd8, 0x7003, 0x0000, 0x7000, + 0xa005, 0x1130, 0x7004, 0xa005, 0x1118, 0x700c, 0xa005, 0x0108, + 0x0c40, 0x2049, 0x0000, 0xb284, 0x0200, 0x0118, 0x2001, 0x0000, + 0x0010, 0x2001, 0x0001, 0x080c, 0x3b81, 0x681b, 0x0002, 0x2051, + 0x0000, 0x0005, 0x080c, 0x254c, 0x080c, 0x254c, 0x080c, 0x415f, + 0x7210, 0x7114, 0x700c, 0xa09c, 0x07ff, 0x2800, 0xa300, 0xa211, + 0xa189, 0x0000, 0x04a1, 0x2704, 0x2c58, 0xac60, 0x6308, 0x2200, + 0xa322, 0x630c, 0x2100, 0xa31b, 0x2400, 0xa305, 0x0140, 0x1238, + 0x8412, 0x8210, 0x830a, 0xa189, 0x0000, 0x2b60, 0x0c58, 0x2b60, + 0x8a07, 0x0006, 0x6004, 0xd09c, 0x0118, 0xa7ba, 0x3fef, 0x0010, + 0xa7ba, 0x3fe7, 0x000e, 0xa73d, 0x2c00, 0x6886, 0x6f8a, 0x6c92, + 0x6b8e, 0x7108, 0x7008, 0xa106, 0x1de0, 0xa184, 0x01e0, 0x0110, + 0x080c, 0x40e6, 0x7007, 0x0012, 0x080c, 0x4034, 0x0005, 0x8a50, + 0x8739, 0x2704, 0xa004, 0x1168, 0x6000, 0xa064, 0x1108, 0x2d60, + 0x6004, 0xa084, 0x000f, 0xa080, 0x4005, 0x203c, 0x87fb, 0x090c, + 0x254c, 0x0005, 0x0126, 0x00d6, 0x70d0, 0xa084, 0x4c00, 0x8004, + 0x2090, 0x00de, 0x6884, 0x2060, 0x6888, 0x6b8c, 0x6c90, 0x8057, + 0xaad4, 0x00ff, 0xa084, 0x00ff, 0x0006, 0x6804, 0xa084, 0x0008, + 0x000e, 0x0118, 0xa0b8, 0x3fef, 0x0010, 0xa0b8, 0x3fe7, 0xb284, + 0x0200, 0x0110, 0x7e20, 0x0008, 0x7e24, 0xa6b5, 0x000c, 0x681c, + 0xd0b4, 0x0108, 0xc685, 0x2400, 0xa305, 0x0518, 0x2c58, 0x2704, + 0x6104, 0xac60, 0x6000, 0xa400, 0x701a, 0x6004, 0xa301, 0x701e, + 0xd19c, 0x0140, 0x6010, 0xa081, 0x0000, 0x7022, 0x6014, 0xa081, + 0x0000, 0x7026, 0x6208, 0x2400, 0xa202, 0x7012, 0x620c, 0x2300, + 0xa203, 0x7016, 0x7602, 0x7007, 0x0001, 0x2b60, 0x080c, 0x4292, + 0x0010, 0x080c, 0x426b, 0x1de8, 0x012e, 0x2000, 0x0005, 0x0126, + 0x00d6, 0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, 0x00de, 0x7007, + 0x0004, 0x7004, 0xd094, 0x1de8, 0x7003, 0x0008, 0x012e, 0x2000, + 0x0005, 0x0126, 0x00d6, 0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, + 0x00de, 0x7e20, 0xb284, 0x0200, 0x1108, 0x7e24, 0xa6b5, 0x000c, + 0x681c, 0xd0ac, 0x1118, 0xc685, 0x7003, 0x0000, 0x6828, 0x2050, + 0x2d60, 0x6004, 0xa0bc, 0x000f, 0xa7b8, 0x3ff5, 0x273c, 0x87fb, + 0x1138, 0x0210, 0x080c, 0x254c, 0x689c, 0xa065, 0x0120, 0x0c88, + 0x080c, 0x426b, 0x1de8, 0x012e, 0x2000, 0x0005, 0x0126, 0x0006, + 0x0016, 0x00d6, 0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, 0x7e20, + 0xb284, 0x0200, 0x1108, 0x7e24, 0x00de, 0x003e, 0x004e, 0xa6b5, + 0x000c, 0x681c, 0xd0b4, 0x0128, 0xc685, 0x7003, 0x0000, 0x7007, + 0x0004, 0x2049, 0x4206, 0x6828, 0xa055, 0x00d6, 0x0904, 0x4267, + 0x2d70, 0x2e60, 0x7004, 0xa0bc, 0x000f, 0xa7b8, 0x3ff5, 0x273c, + 0x87fb, 0x1140, 0x0210, 0x080c, 0x254c, 0x709c, 0xa075, 0x2060, + 0x0570, 0x0c80, 0x2704, 0xae68, 0x6808, 0xa422, 0x680c, 0xa31b, + 0x0268, 0x8a51, 0x1110, 0x080c, 0x254c, 0x8738, 0x2704, 0xa005, + 0x1d90, 0x709c, 0xa075, 0x2060, 0x01d0, 0x08e0, 0x8422, 0x8420, + 0x831a, 0xa399, 0x0000, 0x6908, 0x2400, 0xa122, 0x690c, 0x2300, + 0xa11b, 0x1210, 0x080c, 0x254c, 0xb284, 0x0200, 0x0118, 0x2071, + 0x0050, 0x0010, 0x2071, 0x0020, 0x00de, 0x0804, 0x419b, 0x00de, + 0x012e, 0x2000, 0x0005, 0x7008, 0x0006, 0xa084, 0x01e0, 0x000e, + 0x0110, 0xa006, 0x0005, 0xa084, 0x0003, 0xa086, 0x0003, 0x1108, + 0x0005, 0x2704, 0xac78, 0x7800, 0x701a, 0x7804, 0x701e, 0x7808, + 0x7012, 0x780c, 0x7016, 0x6004, 0xd09c, 0x0120, 0x7810, 0x7022, + 0x7814, 0x7026, 0x7602, 0x7004, 0xa084, 0x0010, 0xc085, 0x7006, + 0x2079, 0x4600, 0x8a51, 0x01e8, 0x8738, 0x2704, 0xa005, 0x1168, + 0x609c, 0xa005, 0x01b8, 0x2060, 0x6004, 0xa084, 0x000f, 0xa080, + 0x3ff5, 0x203c, 0x87fb, 0x090c, 0x254c, 0x7008, 0x0006, 0xa084, + 0x01e0, 0x000e, 0x0110, 0xa006, 0x0028, 0xa084, 0x0003, 0xa086, + 0x0003, 0x0005, 0x2051, 0x0000, 0x0005, 0x0126, 0x0006, 0x00d6, + 0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, 0x00de, 0x008e, 0x7108, + 0xa184, 0x0003, 0x1128, 0x6828, 0xa005, 0x0178, 0x0804, 0x3f45, + 0x7108, 0xd1fc, 0x0118, 0x080c, 0x40ae, 0x0c88, 0x7007, 0x0010, + 0x7108, 0xd1fc, 0x0de8, 0x080c, 0x40ae, 0x7008, 0xa086, 0x0008, + 0x1d30, 0x7000, 0xa005, 0x1d18, 0x7003, 0x0000, 0x2049, 0x0000, + 0x0006, 0x2001, 0x4601, 0x2004, 0xd0cc, 0x0110, 0x080c, 0x4328, + 0x000e, 0x012e, 0x2000, 0x0005, 0x0126, 0x0146, 0x0136, 0x0156, + 0x00c6, 0x00d6, 0x70d0, 0xa084, 0x4c00, 0x8004, 0x2090, 0x00de, + 0x2049, 0x42ec, 0xad80, 0x0011, 0x20a0, 0xb284, 0x0200, 0x0118, + 0x2099, 0x0032, 0x0010, 0x2099, 0x0031, 0x700c, 0xa084, 0x07ff, + 0x682a, 0x7007, 0x0008, 0x7007, 0x0002, 0x7003, 0x0001, 0x0118, + 0x8000, 0x80ac, 0x53a5, 0x700c, 0xa084, 0x07ff, 0x0130, 0x7007, + 0x0004, 0x7004, 0xa084, 0x0004, 0x1de0, 0x00ce, 0x2049, 0x0000, + 0x7003, 0x0000, 0x015e, 0x013e, 0x014e, 0x012e, 0x2000, 0x0005, + 0x6814, 0xd0fc, 0x0904, 0x436b, 0x7000, 0xd084, 0x05e0, 0x7e24, + 0xa6b5, 0x0004, 0x7007, 0x0004, 0x7004, 0xa084, 0x0004, 0x1de0, + 0x7118, 0x0016, 0x711c, 0x0016, 0x7120, 0x0016, 0x7124, 0x0016, + 0x701b, 0x0000, 0x701f, 0x3fff, 0x7023, 0x0000, 0x7027, 0x0000, + 0x7013, 0x0004, 0x7017, 0x0000, 0x7602, 0x7007, 0x0001, 0x2001, + 0xffff, 0x2009, 0x0031, 0x200a, 0x200a, 0x7108, 0x7008, 0xa106, + 0x1de0, 0xd1fc, 0x0dd0, 0x002e, 0x7226, 0x002e, 0x7222, 0x002e, + 0x721e, 0x002e, 0x721a, 0x7007, 0x0002, 0x7008, 0xa086, 0x0008, + 0x0110, 0x0804, 0x40e6, 0x7007, 0x0004, 0x7003, 0x0000, 0x0005, + 0x2091, 0x8000, 0x2091, 0x6000, 0x78ac, 0xa005, 0x1168, 0x7974, + 0x70d0, 0xa106, 0x1148, 0x781c, 0xa005, 0x0130, 0x781f, 0x0000, + 0x0e04, 0x4384, 0x2091, 0x4080, 0x2069, 0x4680, 0xd7fc, 0x1110, + 0x2069, 0x4640, 0x6800, 0xa084, 0x000f, 0x1198, 0x68d0, 0xd0b4, + 0x0180, 0xd0bc, 0x1170, 0x00f6, 0x2079, 0x0100, 0xd7fc, 0x1110, + 0x2079, 0x0200, 0x7830, 0xa084, 0x00c0, 0x1110, 0x080c, 0x22ae, + 0x00fe, 0x7830, 0x8001, 0x7832, 0x1904, 0x440b, 0x7834, 0x7832, + 0x2061, 0x6bc0, 0x2069, 0x4680, 0xc7fd, 0x68cc, 0xa005, 0x0128, + 0x8001, 0x68ce, 0x1110, 0x080c, 0x4577, 0x6800, 0xa084, 0x000f, + 0x0168, 0xa086, 0x0001, 0x0150, 0x6840, 0xa00d, 0x0138, 0x2104, + 0xa005, 0x0120, 0x8001, 0x200a, 0x0904, 0x4514, 0x6814, 0xa005, + 0x01a8, 0x8001, 0x6816, 0x1190, 0x68a3, 0x0001, 0x00f6, 0xd7fc, + 0x1118, 0x2079, 0x0200, 0x0010, 0x2079, 0x0100, 0x080c, 0x3c46, + 0x00fe, 0x6860, 0xa005, 0x0110, 0x080c, 0x22ae, 0x687c, 0xa005, + 0x0140, 0x8001, 0x687e, 0x1128, 0x6863, 0x0000, 0x68d0, 0xc0c5, + 0x68d2, 0x68d0, 0xd0fc, 0x01b0, 0xc0fc, 0x68d2, 0x20a9, 0x0200, + 0x6034, 0xa005, 0x0158, 0x8001, 0x6036, 0x68d0, 0xc0fd, 0x68d2, + 0x1128, 0x6010, 0xa005, 0x0110, 0x080c, 0x22ae, 0xace0, 0x0010, + 0x1f04, 0x43f0, 0xd7fc, 0x0138, 0x2061, 0x4bc0, 0x2069, 0x4640, + 0xc7fc, 0x0804, 0x43ad, 0x0459, 0x7838, 0x8001, 0x783a, 0x11a0, + 0x783c, 0x783a, 0x2061, 0x4bc0, 0x2069, 0x4640, 0xc7fc, 0x680c, + 0xa005, 0x0110, 0x080c, 0x4487, 0xd7fc, 0x1130, 0x2061, 0x6bc0, + 0x2069, 0x4680, 0xc7fd, 0x0c98, 0x7810, 0xd0cc, 0x0168, 0xd0ac, + 0x1120, 0xd0a4, 0x0148, 0xc0ad, 0x7812, 0x2091, 0x8001, 0x0e04, + 0x4433, 0x080c, 0x207a, 0x0005, 0x2091, 0x8001, 0x0005, 0x7840, + 0x8001, 0x7842, 0x1904, 0x4486, 0x7844, 0x7842, 0x2069, 0x4640, + 0xc7fc, 0x2079, 0x0200, 0x68d4, 0xa005, 0x0138, 0x7de0, 0xa504, + 0x1120, 0x68d6, 0x68d0, 0xc0bc, 0x68d2, 0x2079, 0x4600, 0x6810, + 0xa005, 0x1110, 0x2001, 0x0101, 0x8001, 0x6812, 0xd7fc, 0x0118, + 0xa080, 0x8cd0, 0x0010, 0xa080, 0x8bc0, 0x2040, 0x2004, 0xa065, + 0x01e0, 0x6024, 0xa005, 0x01b0, 0x8001, 0x6026, 0x1198, 0x6800, + 0xa005, 0x0130, 0x6848, 0xac06, 0x1118, 0x080c, 0x4514, 0x0068, + 0x6860, 0xa005, 0x0118, 0x6027, 0x0001, 0x0020, 0x080c, 0x44c8, + 0x2804, 0x0c28, 0x6000, 0x2c40, 0x0c10, 0xd7fc, 0x1138, 0x2069, + 0x4680, 0xc7fd, 0x2079, 0x0100, 0x0804, 0x4443, 0x0005, 0x2009, + 0x0000, 0x20a9, 0x0200, 0x6008, 0xd09c, 0x0558, 0x6024, 0xa005, + 0x0118, 0x8001, 0x6026, 0x0418, 0x6008, 0xc09c, 0xd084, 0x1110, + 0xd0ac, 0x01c0, 0x600a, 0x6004, 0xa005, 0x01d8, 0x00d6, 0x00c6, + 0x0016, 0x2068, 0x6010, 0x8001, 0x6012, 0x080c, 0x37a4, 0x2d00, + 0x2c68, 0x2060, 0x080c, 0x1be3, 0x080c, 0x1d95, 0x001e, 0x00ce, + 0x00de, 0x0038, 0xc0bd, 0x600a, 0xa18d, 0x0001, 0x0010, 0xa18d, + 0x0100, 0xace0, 0x0010, 0x1f04, 0x448b, 0xa184, 0x0001, 0x0130, + 0xa18c, 0xfffe, 0x690e, 0x080c, 0x22ae, 0x0008, 0x690e, 0x0005, + 0x2c00, 0x687a, 0x6714, 0x6f72, 0x6017, 0x0000, 0x602b, 0x0000, + 0x601b, 0x0006, 0x60b4, 0xa084, 0x5f00, 0x601e, 0x6020, 0xa084, + 0x00ff, 0xa085, 0x0060, 0x6022, 0x6000, 0x2042, 0x6858, 0xac06, + 0x1110, 0x2800, 0x685a, 0x080c, 0x1b7b, 0x6818, 0xa005, 0x0110, + 0x8001, 0x681a, 0x6808, 0xc0a4, 0x680a, 0x6810, 0x7908, 0x8109, + 0x790a, 0x8001, 0x1310, 0x080c, 0x254c, 0x6812, 0x1118, 0x7910, + 0xc1a5, 0x7912, 0x602f, 0x0000, 0x6033, 0x0000, 0x2c68, 0x080c, + 0x1da2, 0xd7fc, 0x1118, 0x2069, 0x4640, 0x0010, 0x2069, 0x4680, + 0x6910, 0xa184, 0x0100, 0x2001, 0x0006, 0x1118, 0x6976, 0x2001, + 0x0004, 0x080c, 0x22a4, 0x0005, 0x00d6, 0x6948, 0x2160, 0xd7fc, + 0x1118, 0x2069, 0x0200, 0x0010, 0x2069, 0x0100, 0x080c, 0x2467, + 0x601b, 0x0006, 0x6858, 0xa084, 0x5f00, 0x601e, 0x6020, 0xa084, + 0x00ff, 0xa085, 0x0048, 0x6022, 0x602f, 0x0000, 0x6033, 0x0000, + 0x6808, 0xa084, 0xfffd, 0x680a, 0x6830, 0xd0b4, 0x01b0, 0x684b, + 0x0004, 0x20a9, 0x0014, 0x6848, 0xd094, 0x0110, 0x1f04, 0x453b, + 0x684b, 0x0009, 0x20a9, 0x0014, 0x6848, 0xd084, 0x0110, 0x1f04, + 0x4544, 0x20a9, 0x00fa, 0x1f04, 0x454b, 0x681b, 0x0054, 0x00de, + 0x6863, 0x0007, 0x0005, 0x2079, 0x4600, 0x00e1, 0x0089, 0x00a9, + 0x2009, 0x0002, 0x2069, 0x4680, 0x680f, 0x0000, 0x6813, 0x0000, + 0x6817, 0x0000, 0x8109, 0x0118, 0x2069, 0x4640, 0x0ca8, 0x0005, + 0x2019, 0x00a3, 0x7b3a, 0x7b3e, 0x0005, 0x2019, 0x0033, 0x7b42, + 0x7b46, 0x0005, 0x2019, 0x32dd, 0x7b32, 0x7b36, 0x0005, 0x6a4c, + 0xa285, 0x0000, 0x01f0, 0x6950, 0x6bbc, 0xa300, 0x00c6, 0x2164, + 0x6304, 0x83ff, 0x1138, 0x8211, 0x0148, 0x8108, 0xa11a, 0x0eb8, + 0x69bc, 0x0ca8, 0x68cf, 0x000a, 0x00ce, 0x0005, 0x694c, 0x6abc, + 0x2264, 0x6008, 0xc0b5, 0x600a, 0x8210, 0x8109, 0x1dc8, 0x694e, + 0x00ce, 0x0005, 0x1d04, 0x459a, 0x2091, 0x6000, 0x1d04, 0x459e, + 0x2091, 0x6000, 0x70ec, 0xd0dc, 0x1118, 0xd0d4, 0x0190, 0x0098, + 0xae8e, 0x0100, 0x0138, 0x7814, 0xc0f5, 0xc0c5, 0x7816, 0xd0d4, + 0x1578, 0x0458, 0x7814, 0xc0fd, 0xc0c5, 0x7816, 0xd0d4, 0x1540, + 0x0420, 0xd0e4, 0x0538, 0x1d04, 0x45bb, 0x2091, 0x6000, 0x2009, + 0x000c, 0x1d04, 0x45c1, 0x2091, 0x6000, 0x8109, 0x1dd0, 0x70e4, + 0xa084, 0x01ff, 0xa086, 0x01ff, 0x1110, 0x70ec, 0x08c8, 0xae8e, + 0x0100, 0x0128, 0x7814, 0xc0f4, 0xd0fc, 0x1130, 0x0020, 0x7814, + 0xc0fc, 0xd0f4, 0x1108, 0xc0c4, 0x7816, 0x7804, 0xd08c, 0x0110, + 0x681f, 0x000c, 0x70a0, 0x70a2, 0x0005, 0x7c12 +}; +#else +/* + * Firmware Version 11.12.01 (12:37 May 24, 2000) + */ +static const u_int16_t isp_12160_risc_code[] = { + 0x0804, 0x103a, 0x0000, 0x4bd8, 0x0000, 0x2043, 0x4f50, 0x5952, + 0x4947, 0x4854, 0x2031, 0x3939, 0x3520, 0x514c, 0x4f47, 0x4943, + 0x2043, 0x4f52, 0x504f, 0x5241, 0x5449, 0x4f4e, 0x2049, 0x5350, + 0x3132, 0x3430, 0x2049, 0x2f54, 0x2046, 0x6972, 0x6d77, 0x6172, + 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2031, 0x312e, 0x3132, + 0x2020, 0x2043, 0x7573, 0x746f, 0x6d65, 0x7220, 0x4e6f, 0x2e20, + 0x3030, 0x2050, 0x726f, 0x6475, 0x6374, 0x204e, 0x6f2e, 0x2020, + 0x3031, 0x2024, 0x2071, 0x0200, 0x70a0, 0x70a2, 0x2001, 0x01ff, + 0x2004, 0xd0fc, 0x1120, 0x2071, 0x0100, 0x70a0, 0x70a2, 0x20c1, + 0x0020, 0x2089, 0x128f, 0x0030, 0x2001, 0x04fc, 0x2004, 0xa086, + 0x1216, 0x0d40, 0x2071, 0x0010, 0x70c3, 0x0004, 0x70c7, 0x4953, + 0x70cb, 0x5020, 0x70cf, 0x2020, 0x70d3, 0x000b, 0x2001, 0x04fd, + 0x70d6, 0x20c1, 0x0022, 0x20c9, 0x10ff, 0x2009, 0xfeff, 0x200b, + 0xa5a5, 0xe000, 0xe000, 0x2114, 0xa286, 0xa5a5, 0x0120, 0x20c1, + 0x0020, 0x20c9, 0x5cff, 0x2009, 0x0200, 0xa18e, 0x0400, 0x1168, + 0x3808, 0xa18e, 0x0020, 0x1148, 0x70c3, 0x8010, 0x2061, 0x0000, + 0x601b, 0x0001, 0x2091, 0x4080, 0x0cf8, 0x2009, 0xfeff, 0x2130, + 0x2128, 0x3800, 0xa084, 0x0003, 0x0006, 0x0118, 0xa1a2, 0x1100, + 0x0010, 0xa1a2, 0x5cff, 0x000e, 0x8424, 0x8424, 0x8424, 0x8424, + 0x8424, 0x8424, 0x2009, 0xb33f, 0xa005, 0x0128, 0x2079, 0x1100, + 0xa192, 0x1100, 0x0020, 0x2079, 0x5d00, 0xa192, 0x5d00, 0x2009, + 0x0000, 0x2001, 0x0037, 0x080c, 0x20ea, 0x2218, 0x2fa0, 0x2408, + 0x2011, 0x0000, 0x20a9, 0x0040, 0x42a4, 0x8109, 0x1dd8, 0x2079, + 0xb340, 0x2001, 0x04fc, 0x2004, 0xa086, 0x1280, 0x11e8, 0x780c, + 0xc0ed, 0xc0d5, 0x780e, 0x7813, 0x0064, 0x2071, 0x0200, 0x00d6, + 0x2069, 0xb380, 0x080c, 0x59b8, 0x2001, 0x01ff, 0x2004, 0xd0fc, + 0x1130, 0x2069, 0xb3c0, 0x2071, 0x0100, 0x080c, 0x59b8, 0x780c, + 0xc0d4, 0x780e, 0x00de, 0x0090, 0x2001, 0x04fc, 0x2004, 0xa086, + 0x1216, 0x1128, 0x7813, 0x0064, 0x780c, 0xc0cd, 0x08c8, 0x780c, + 0xc0e5, 0x780e, 0x7813, 0x003c, 0x2011, 0x000c, 0x2009, 0xb38c, + 0x220a, 0x2009, 0xb3cc, 0x220a, 0x7eca, 0x7cc2, 0x7bc6, 0x785b, + 0x0000, 0x7800, 0xc08d, 0x7802, 0x2031, 0x0030, 0x78af, 0x0101, + 0x781b, 0x0002, 0x781f, 0x0002, 0x2009, 0x0002, 0x2069, 0xb380, + 0x6817, 0x0003, 0x681f, 0x0007, 0x6823, 0x00fa, 0x6827, 0x0008, + 0x682b, 0x0028, 0x6837, 0x0006, 0x682f, 0x0008, 0x683b, 0x0000, + 0x8109, 0x0508, 0x68ef, 0x000a, 0x68df, 0xb400, 0x2079, 0xb340, + 0x780c, 0xd0e4, 0x1118, 0x68f3, 0x7629, 0x0010, 0x68f3, 0x760d, + 0x68e3, 0xba00, 0x68e7, 0xb800, 0x68eb, 0xfa00, 0x68c7, 0xfece, + 0x68cb, 0xfed3, 0x68cf, 0xfece, 0x68d3, 0xfece, 0x68c3, 0x0001, + 0x2069, 0xb3c0, 0x0868, 0x68ef, 0x000a, 0x68df, 0xb600, 0x68f3, + 0x7819, 0x68e3, 0xda00, 0x68e7, 0xb900, 0x68eb, 0xfb10, 0x68c7, + 0xfed3, 0x68cb, 0xfed8, 0x68cf, 0xfed3, 0x68d3, 0xfed3, 0x68c3, + 0x0001, 0x00e6, 0x2069, 0xb800, 0x2071, 0x0200, 0x70ec, 0xd0e4, + 0x2019, 0x1c09, 0x2021, 0x0009, 0x1120, 0x2019, 0x1c0c, 0x2021, + 0x000c, 0x080c, 0x200a, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1188, + 0x2069, 0xb900, 0x2071, 0x0100, 0x70ec, 0xd0e4, 0x2019, 0x1c09, + 0x2021, 0x0009, 0x1120, 0x2019, 0x1c0c, 0x2021, 0x000c, 0x080c, + 0x200a, 0x00ee, 0x2011, 0x0002, 0x2069, 0xba00, 0x2009, 0x0002, + 0x20a9, 0x0100, 0x6837, 0x0000, 0x680b, 0x0040, 0x7bc8, 0xa386, + 0xfeff, 0x1128, 0x6817, 0x0100, 0x681f, 0x0064, 0x0020, 0x6817, + 0x0064, 0x681f, 0x0002, 0xade8, 0x0010, 0x1f04, 0x1182, 0x8109, + 0x1d38, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1128, 0x8211, 0x0118, + 0x2069, 0xda00, 0x08d8, 0x080c, 0x2680, 0x080c, 0x53c4, 0x080c, + 0x1caf, 0x080c, 0x595f, 0x2091, 0x2200, 0x2079, 0xb340, 0x7808, + 0xd0ec, 0x0118, 0x2071, 0x0020, 0x0010, 0x2071, 0x0050, 0x2091, + 0x2400, 0x2079, 0xb340, 0x2071, 0x0020, 0x2091, 0x2600, 0x2079, + 0xb340, 0x7808, 0xd0ec, 0x0118, 0x2079, 0x0100, 0x0010, 0x2079, + 0x0200, 0x2071, 0xb380, 0x2091, 0x2800, 0x2079, 0x0100, 0x2071, + 0xb3c0, 0x2091, 0x2000, 0x2079, 0xb340, 0x2071, 0x0010, 0x3200, + 0xa085, 0x303d, 0x2090, 0x70c3, 0x0000, 0x1004, 0x11e5, 0x70c0, + 0xa086, 0x0002, 0x1110, 0x080c, 0x142c, 0x2039, 0x0000, 0x080c, + 0x130a, 0x78ac, 0xa005, 0x11a0, 0x0e04, 0x11f5, 0x7864, 0xa065, + 0x0120, 0x2029, 0x0000, 0x080c, 0x252c, 0x080c, 0x210b, 0x0e04, + 0x120c, 0x7864, 0xa065, 0x0120, 0x2029, 0x0000, 0x080c, 0x252c, + 0x0e04, 0x120c, 0x2009, 0xb386, 0x2011, 0xb3c6, 0x2104, 0x220c, + 0xa105, 0x0110, 0x080c, 0x1dd0, 0x00e6, 0x00f6, 0x2071, 0xb380, + 0x70c0, 0xa005, 0x01f8, 0x7454, 0xa485, 0x0000, 0x01d8, 0x2079, + 0x0200, 0x2091, 0x8000, 0x72f0, 0xa28c, 0x303d, 0x2190, 0x080c, + 0x2b7f, 0x2091, 0x8000, 0x2091, 0x303d, 0x0e04, 0x1232, 0x00fe, + 0x7864, 0xa065, 0x0130, 0x00ee, 0x2029, 0x0000, 0x080c, 0x252c, + 0x00e6, 0x00f6, 0x1d04, 0x123a, 0x00fe, 0x00ee, 0x080c, 0x577e, + 0x00e6, 0x00f6, 0x2071, 0xb3c0, 0x70c0, 0xa005, 0x0190, 0x7454, + 0xa485, 0x0000, 0x0170, 0x2079, 0x0100, 0x2091, 0x8000, 0x72f0, + 0xa28c, 0x303d, 0x2190, 0x080c, 0x2b7f, 0x2091, 0x8000, 0x2091, + 0x303d, 0x00fe, 0x00ee, 0x0e04, 0x125b, 0x7864, 0xa065, 0x0118, + 0xa02e, 0x080c, 0x252c, 0x1d04, 0x11e7, 0x080c, 0x577e, 0x0804, + 0x11e7, 0x3c00, 0xa084, 0x0007, 0x0002, 0x1275, 0x1275, 0x1277, + 0x1277, 0x127c, 0x127c, 0x1281, 0x1281, 0x3c00, 0xa084, 0x0003, + 0x0002, 0x1275, 0x1275, 0x128a, 0x128a, 0x080c, 0x297f, 0x2091, + 0x2400, 0x080c, 0x547f, 0x0005, 0x2091, 0x2200, 0x080c, 0x547f, + 0x0005, 0x2091, 0x2200, 0x080c, 0x547f, 0x2091, 0x2400, 0x080c, + 0x547f, 0x0005, 0x2091, 0x2200, 0x080c, 0x547f, 0x0005, 0x12af, + 0x12af, 0x12b0, 0x12b0, 0x12bb, 0x12bb, 0x12bb, 0x12bb, 0x12c4, + 0x12c4, 0x12cf, 0x12cf, 0x12bb, 0x12bb, 0x12bb, 0x12bb, 0x12de, + 0x12de, 0x12de, 0x12de, 0x12de, 0x12de, 0x12de, 0x12de, 0x12de, + 0x12de, 0x12de, 0x12de, 0x12de, 0x12de, 0x12de, 0x12de, 0x0cf8, + 0x0006, 0x0106, 0x0126, 0x2091, 0x2800, 0x080c, 0x299c, 0x012e, + 0x010e, 0x000e, 0x000d, 0x0006, 0x0106, 0x0126, 0x080c, 0x1261, + 0x012e, 0x010e, 0x000e, 0x000d, 0x0006, 0x0106, 0x0126, 0x2091, + 0x2600, 0x080c, 0x299c, 0x012e, 0x010e, 0x000e, 0x000d, 0x0006, + 0x0106, 0x0126, 0x2091, 0x2600, 0x080c, 0x299c, 0x2091, 0x2800, + 0x080c, 0x299c, 0x012e, 0x010e, 0x000e, 0x000d, 0x0006, 0x0106, + 0x0126, 0x00d6, 0x00e6, 0x00f6, 0x2079, 0xb340, 0x2071, 0x0200, + 0x2069, 0xb380, 0x3d00, 0xd08c, 0x0130, 0x70ec, 0xa084, 0x1c00, + 0x78e2, 0x080c, 0x59b8, 0x3d00, 0xd084, 0x0150, 0x2069, 0xb3c0, + 0x2071, 0x0100, 0x70ec, 0xa084, 0x1c00, 0x78e6, 0x080c, 0x59b8, + 0x080c, 0x2930, 0x00fe, 0x00ee, 0x00de, 0x012e, 0x010e, 0x000e, + 0x000d, 0x0005, 0x0e04, 0x1381, 0x2061, 0x0000, 0x6018, 0xa084, + 0x0001, 0x1904, 0x1381, 0x7820, 0xa005, 0x1120, 0x0004, 0x1382, + 0x0804, 0x1381, 0x7908, 0xd1f4, 0x0120, 0x2001, 0x4007, 0x0804, + 0x142e, 0x790c, 0xd1ec, 0x01a0, 0xd0fc, 0x0148, 0x0006, 0x080c, + 0x1c2f, 0x000e, 0x0168, 0x2001, 0x4007, 0x0804, 0x142e, 0x0006, + 0x080c, 0x1c25, 0x000e, 0x0120, 0x2001, 0x4007, 0x0804, 0x142e, + 0x7908, 0xd0fc, 0x1128, 0x2061, 0xb380, 0xc19c, 0xc7fc, 0x0020, + 0x2061, 0xb3c0, 0xc19d, 0xc7fd, 0x6068, 0xa005, 0x15d0, 0x790a, + 0x6087, 0x0000, 0x7820, 0xc0fc, 0xa086, 0x0018, 0x1120, 0x00c6, + 0x080c, 0x196b, 0x00ce, 0x7823, 0x0000, 0x6080, 0xa065, 0x0190, + 0x00c6, 0x609c, 0x080c, 0x1d24, 0x00ce, 0x609f, 0x0000, 0x080c, + 0x1a81, 0x2009, 0x000c, 0x6007, 0x0103, 0x080c, 0x1c39, 0x1198, + 0x080c, 0x1c95, 0x7808, 0xd09c, 0x1118, 0x2061, 0xb380, 0x0018, + 0x2061, 0xb3c0, 0xc09c, 0x6083, 0x0000, 0x780a, 0x60f0, 0xd0c4, + 0x0130, 0xc0c4, 0x60f2, 0x2001, 0x4005, 0x0804, 0x142e, 0x0804, + 0x142c, 0x0005, 0x7808, 0xd0f4, 0x0120, 0x2001, 0x4007, 0x0804, + 0x142e, 0x70c3, 0x0000, 0x70c7, 0x0000, 0x70cb, 0x0000, 0x70cf, + 0x0000, 0x70db, 0x0000, 0x71c4, 0x7a08, 0xd2ec, 0x0108, 0xc1fc, + 0x70c0, 0xa03d, 0xa092, 0x0030, 0x1208, 0x0032, 0x2200, 0xa092, + 0x0050, 0x1a04, 0x143a, 0x0482, 0x142c, 0x14a7, 0x1448, 0x14bb, + 0x14ca, 0x14d0, 0x1440, 0x1a99, 0x14d4, 0x143a, 0x144c, 0x144d, + 0x144e, 0x144f, 0x1a9d, 0x143a, 0x14e1, 0x1532, 0x1988, 0x1a93, + 0x1450, 0x17f5, 0x182e, 0x1863, 0x18a8, 0x17b0, 0x17be, 0x17d1, + 0x17e4, 0x1600, 0x143a, 0x155f, 0x1563, 0x1571, 0x157f, 0x1596, + 0x15a4, 0x15a7, 0x15b5, 0x15c3, 0x15cd, 0x15e6, 0x15f2, 0x143a, + 0x143a, 0x143a, 0x143a, 0x160d, 0x1618, 0x1631, 0x1665, 0x168e, + 0x16a0, 0x16a3, 0x16cd, 0x1705, 0x1717, 0x1784, 0x1794, 0x143a, + 0x1475, 0x143a, 0x143a, 0x17a6, 0x143a, 0x143a, 0x143a, 0x143a, + 0x143a, 0x1bc9, 0x1bcf, 0x143a, 0x143a, 0x143a, 0x1bd3, 0x1be2, + 0x143a, 0x143a, 0x143a, 0x143a, 0x14a2, 0x14b6, 0x14dc, 0x152d, + 0x1983, 0x1ab1, 0x1ad3, 0x1950, 0x1ae9, 0x1bf0, 0x1bbb, 0x1bc5, + 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, + 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, + 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, + 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, 0x143a, + 0x143a, 0x143a, 0x143a, 0x143a, 0x72ca, 0x71c6, 0x2001, 0x4006, + 0x0028, 0x73ce, 0x72ca, 0x71c6, 0x2001, 0x4000, 0x70c2, 0x0e04, + 0x142f, 0x2061, 0x0000, 0x601b, 0x0001, 0x2091, 0x5000, 0x2091, + 0x4080, 0x0005, 0x70c3, 0x4001, 0x0c90, 0x70c3, 0x4006, 0x0c78, + 0x2099, 0x0041, 0x20a1, 0x0041, 0x20a9, 0x0005, 0x53a3, 0x0c20, + 0x70c4, 0x70c3, 0x0004, 0x0807, 0x08f8, 0x08f0, 0x08e8, 0x08e0, + 0x2091, 0x8000, 0x70c3, 0x0000, 0x70c7, 0x4953, 0x70cb, 0x5020, + 0x70cf, 0x2020, 0x70d3, 0x000b, 0x2001, 0x000c, 0x70d6, 0x2079, + 0x0000, 0x781b, 0x0001, 0x2031, 0x0030, 0x2059, 0x1000, 0x2029, + 0x041a, 0x2051, 0x0445, 0x2061, 0x0447, 0x20c1, 0x0020, 0x2091, + 0x5000, 0x2091, 0x4080, 0x0804, 0x0418, 0x00d6, 0x70c4, 0x7904, + 0xd19c, 0x0180, 0x70c7, 0x0001, 0x2069, 0xfed8, 0x2d14, 0x72ca, + 0x8d68, 0x2d14, 0x72ce, 0x8d68, 0x2d14, 0x72da, 0x8d68, 0x2d14, + 0x72de, 0x0010, 0x70c7, 0x0000, 0xa005, 0x0178, 0xc19d, 0x72c8, + 0x2069, 0xfed8, 0x226a, 0x72cc, 0x8d68, 0x226a, 0x72d8, 0x8d68, + 0x226a, 0x72dc, 0x8d68, 0x226a, 0x0008, 0xc19c, 0x7906, 0x00de, + 0x0804, 0x142c, 0x75d8, 0x74dc, 0x75da, 0x74de, 0x0018, 0x2029, + 0x0000, 0x2520, 0x71d0, 0x73c8, 0x72cc, 0x70c4, 0x080c, 0x1e1f, + 0x0904, 0x142c, 0x70c3, 0x4002, 0x0804, 0x142c, 0x75d8, 0x74dc, + 0x75da, 0x74de, 0x0018, 0x2029, 0x0000, 0x2520, 0x71d0, 0x73c8, + 0x72cc, 0x70c4, 0x080c, 0x1e5e, 0x0904, 0x142c, 0x70c3, 0x4002, + 0x0804, 0x142c, 0x71c4, 0x70c8, 0x2114, 0x200a, 0x0804, 0x142a, + 0x71c4, 0x2114, 0x0804, 0x142a, 0x70c7, 0x000b, 0x70cb, 0x000c, + 0x70cf, 0x0001, 0x0804, 0x142c, 0x75d8, 0x76dc, 0x75da, 0x76de, + 0x0018, 0x2029, 0x0000, 0x2530, 0x70c4, 0x72c8, 0x73cc, 0x74d0, + 0x70c6, 0x72ca, 0x73ce, 0x74d2, 0xa005, 0x05c8, 0xa40a, 0x0110, + 0x1a04, 0x142e, 0x8001, 0x786a, 0xa084, 0xfc00, 0x0138, 0x78ac, + 0xc085, 0x78ae, 0x2001, 0x4005, 0x0804, 0x142e, 0x7a72, 0x7b76, + 0x7d7a, 0x7e7e, 0x7c6e, 0xa48c, 0xff00, 0x0170, 0x8407, 0x8004, + 0x8004, 0x810c, 0x810c, 0x810f, 0xa118, 0xa291, 0x0000, 0xa6b1, + 0x0000, 0xa5a9, 0x0000, 0x0050, 0x8407, 0x8004, 0x8004, 0xa318, + 0xa291, 0x0000, 0xa6b1, 0x0000, 0xa5a9, 0x0000, 0x731a, 0x721e, + 0x7622, 0x7526, 0x78ac, 0xa084, 0xfffc, 0x78ae, 0x0020, 0x78ac, + 0xa085, 0x0001, 0x78ae, 0x0804, 0x142c, 0x75d8, 0x76dc, 0x75da, + 0x76de, 0x0018, 0x2029, 0x0000, 0x2530, 0x70c4, 0x72c8, 0x73cc, + 0x74d4, 0x70c6, 0x72ca, 0x73ce, 0x74d6, 0xa005, 0x01d0, 0xa40a, + 0x0110, 0x1a04, 0x142e, 0x8001, 0x788e, 0xa084, 0xfc00, 0x0138, + 0x78ac, 0xc0c5, 0x78ae, 0x2001, 0x4005, 0x0804, 0x142e, 0x7a96, + 0x7b9a, 0x7d9e, 0x7ea2, 0x7c92, 0x78ac, 0xa084, 0xfcff, 0x78ae, + 0x0020, 0x78ac, 0xa085, 0x0100, 0x78ae, 0x0804, 0x142c, 0x795c, + 0x7ac4, 0x0804, 0x142a, 0x2009, 0xb387, 0x210c, 0x2001, 0x01ff, + 0x2004, 0xd0fc, 0x1904, 0x142b, 0x2011, 0xb3c7, 0x2214, 0x0804, + 0x142a, 0x2009, 0xb388, 0x210c, 0x2001, 0x01ff, 0x2004, 0xd0fc, + 0x1904, 0x142b, 0x2011, 0xb3c8, 0x2214, 0x0804, 0x142a, 0x2061, + 0xb380, 0x6124, 0x6228, 0x8214, 0x8214, 0x8214, 0x2001, 0x01ff, + 0x2004, 0xd0fc, 0x1148, 0x2061, 0xb3c0, 0x6324, 0x73da, 0x6328, + 0x831c, 0x831c, 0x831c, 0x73de, 0x0804, 0x142a, 0x2009, 0xb38b, + 0x210c, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904, 0x142b, 0x2011, + 0xb3cb, 0x2214, 0x0804, 0x142a, 0x7910, 0x0804, 0x142b, 0x2009, + 0x0202, 0x210c, 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904, 0x142b, + 0x2011, 0x0102, 0x2214, 0x0804, 0x142a, 0x2009, 0xb38d, 0x210c, + 0x2001, 0x01ff, 0x2004, 0xd0fc, 0x1904, 0x142b, 0x2011, 0xb3cd, + 0x2214, 0x0804, 0x142a, 0x7918, 0x2001, 0x01ff, 0x2004, 0xd0fc, + 0x1904, 0x142b, 0x7a1c, 0x0804, 0x142a, 0x2011, 0xb900, 0x71c4, + 0xd1fc, 0x1110, 0x2011, 0xb800, 0x8107, 0xa084, 0x000f, 0x8003, + 0x8003, 0x8003, 0x8003, 0xa268, 0x6a00, 0x6b08, 0x6c1c, 0x74da, + 0xd29c, 0x0110, 0x6820, 0x70de, 0x0804, 0x1429, 0x2138, 0x080c, + 0x1cc4, 0x2091, 0x8000, 0x6b1c, 0x6a14, 0x2091, 0x8001, 0x2708, + 0x0804, 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0x00d6, 0x00c6, + 0x0016, 0x2068, 0x6010, 0x8001, 0x6012, 0x080c, 0x3be8, 0x2d00, + 0x2c68, 0x2060, 0x080c, 0x1d3b, 0x080c, 0x2076, 0x001e, 0x00ce, + 0x00de, 0x0038, 0xc0bd, 0x600a, 0xa18d, 0x0001, 0x0010, 0xa18d, + 0x0100, 0xace0, 0x0010, 0x1f04, 0x5883, 0xa184, 0x0001, 0x0130, + 0xa18c, 0xfffe, 0x690a, 0x080c, 0x260c, 0x0008, 0x690a, 0x0005, + 0x2c00, 0x6882, 0x6714, 0x6f7a, 0x6017, 0x0000, 0x602b, 0x0000, + 0x601b, 0x0006, 0x60b4, 0xa084, 0x5f00, 0x601e, 0x6020, 0xa084, + 0x00ff, 0xa085, 0x0060, 0x6022, 0x6000, 0x2042, 0x6860, 0xac06, + 0x1110, 0x2800, 0x6862, 0x080c, 0x1cc4, 0x6818, 0xa005, 0x0530, + 0x8001, 0x681a, 0x681a, 0x6808, 0xc0a4, 0x680a, 0x6810, 0x8001, + 0x03e8, 0x6812, 0x602f, 0x0000, 0x6033, 0x0000, 0x2c68, 0x080c, + 0x2085, 0xd7fc, 0x1118, 0x2069, 0xb380, 0x0010, 0x2069, 0xb3c0, + 0x690c, 0xa184, 0x0100, 0x2001, 0x0006, 0x1128, 0x6883, 0x0000, + 0x697e, 0x2001, 0x0004, 0x2708, 0x080c, 0x2601, 0x0005, 0x00d6, + 0x00e6, 0x2d70, 0xd7fc, 0x1148, 0x7808, 0xd0ec, 0x0118, 0x2069, + 0x0100, 0x0028, 0x2069, 0x0200, 0x0010, 0x2069, 0x0100, 0x7000, + 0xa084, 0x000f, 0x0904, 0x595c, 0xa086, 0x0007, 0x1140, 0x00f6, + 0x2d78, 0x7094, 0x2068, 0x080c, 0x4361, 0x00fe, 0x04a8, 0x7050, + 0x2060, 0x080c, 0x2899, 0x601b, 0x0006, 0x6858, 0xa084, 0x5f00, + 0x601e, 0x6020, 0xa084, 0x00ff, 0xa085, 0x0048, 0x6022, 0x602f, + 0x0000, 0x6033, 0x0000, 0x6808, 0xa084, 0xfffd, 0x680a, 0x6830, + 0xd0b4, 0x01b0, 0x684b, 0x0004, 0x20a9, 0x0014, 0x6848, 0xd094, + 0x0110, 0x1f04, 0x5946, 0x684b, 0x0009, 0x20a9, 0x0014, 0x6848, + 0xd084, 0x0110, 0x1f04, 0x594f, 0x20a9, 0x00fa, 0x1f04, 0x5956, + 0x681b, 0x0050, 0x706b, 0x0007, 0x00ee, 0x00de, 0x0005, 0x2079, + 0xb340, 0x0441, 0x0089, 0x00d9, 0x2009, 0x0002, 0x2069, 0xb3c0, + 0x680b, 0x0000, 0x680f, 0x0000, 0x6813, 0x0000, 0x8109, 0x0118, + 0x2069, 0xb380, 0x0ca8, 0x0005, 0x7808, 0xd0ec, 0x0118, 0x2019, + 0x00cc, 0x0010, 0x2019, 0x007b, 0x7b2e, 0x7b32, 0x0005, 0x780c, + 0xd0e4, 0x1118, 0x2019, 0x0040, 0x0010, 0x2019, 0x0026, 0x7b36, + 0x7b3a, 0x0005, 0x780c, 0xd0e4, 0x1118, 0x2019, 0x3f94, 0x0010, + 0x2019, 0x2624, 0x7b26, 0x7b2a, 0x0005, 0x6a54, 0xa285, 0x0000, + 0x01f0, 0x6958, 0x6bdc, 0xa300, 0x00c6, 0x2164, 0x6304, 0x83ff, + 0x1138, 0x8211, 0x0148, 0x8108, 0xa11a, 0x0eb8, 0x69dc, 0x0ca8, + 0x68ef, 0x000a, 0x00ce, 0x0005, 0x6954, 0x6adc, 0x2264, 0x6008, + 0xc0b5, 0x600a, 0x8210, 0x8109, 0x1dc8, 0x6956, 0x00ce, 0x0005, + 0x1d04, 0x59b8, 0x2091, 0x6000, 0x1d04, 0x59bc, 0x2091, 0x6000, + 0x70ec, 0xd0dc, 0x1118, 0xd0d4, 0x0508, 0x0410, 0x2008, 0x7808, + 0xd0ec, 0x0158, 0xd1c4, 0x15b8, 0x780c, 0xc0c5, 0x780e, 0x7808, + 0xc0f5, 0x780a, 0xd0ec, 0x0558, 0x0438, 0xae8e, 0x0100, 0x0138, + 0x780c, 0xc0f5, 0xc0c5, 0x780e, 0xd0d4, 0x1508, 0x00e8, 0x780c, + 0xc0fd, 0xc0c5, 0x780e, 0xd0d4, 0x11d0, 0x00b0, 0xd0e4, 0x01c8, + 0x1d04, 0x59e8, 0x2091, 0x6000, 0x2009, 0x000c, 0x1d04, 0x59ee, + 0x2091, 0x6000, 0x8109, 0x1dd0, 0x70e4, 0xa084, 0x01ff, 0xa086, + 0x01ff, 0x1110, 0x70ec, 0x0850, 0x7804, 0xd08c, 0x0110, 0x681b, + 0x000c, 0x70a0, 0x70a2, 0x0005, 0x0020, 0x002b, 0x0000, 0x0020, + 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, + 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, + 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, + 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0020, 0x0000, 0x0014, + 0x0014, 0x9851, 0x0014, 0x0014, 0x98f4, 0x98e1, 0x0014, 0x0014, + 0x0014, 0x0080, 0x01a3, 0x0000, 0x0201, 0x0604, 0x0c08, 0x2120, + 0x4022, 0xf880, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x300b, 0xa201, 0x0014, 0xa200, 0x0014, + 0xa200, 0x0214, 0xa202, 0x3806, 0x8839, 0x20c3, 0x0864, 0xa838, + 0x28c1, 0x9cc2, 0xa203, 0x300c, 0x2846, 0x8161, 0x846a, 0x8300, + 0x1856, 0x883a, 0xa804, 0x28f2, 0x9ca6, 0xa8f4, 0x300c, 0x28e1, + 0x9ca6, 0x28a2, 0x7162, 0xa820, 0x2822, 0xa207, 0x64a7, 0x2882, + 0x7163, 0xa81a, 0x2001, 0xa80f, 0xa206, 0x64c0, 0x6de0, 0x67a0, + 0x6fc0, 0x882b, 0x1814, 0x883b, 0x7824, 0x68c1, 0x7864, 0x883e, + 0xa802, 0x8576, 0x8677, 0x206c, 0x28c1, 0x9cc2, 0x2045, 0x2104, + 0x20a1, 0x2080, 0x7961, 0xa8db, 0xa209, 0x0904, 0xa20e, 0xa808, + 0xa205, 0xa300, 0x1872, 0x879a, 0x883c, 0x1fe2, 0xc601, 0xa20a, + 0x8000, 0x85a1, 0x806f, 0x9422, 0x84a2, 0x856e, 0x0704, 0x9ca6, + 0x0014, 0xa204, 0xa300, 0x3009, 0x19e2, 0xf864, 0x856e, 0x883f, + 0x08e6, 0xa8f7, 0xf881, 0xa8eb, 0xc007, 0xf8c1, 0x0016, 0x85b2, + 0x80f0, 0x9532, 0xfb02, 0x1de2, 0x0014, 0x8532, 0xf241, 0x0014, + 0x1de2, 0x84a8, 0xd7a0, 0x1fe6, 0x0014, 0xa208, 0x6043, 0x8008, + 0x1dc1, 0x0016, 0x8160, 0x842a, 0x8190, 0xf041, 0x3008, 0x84a8, + 0x11d7, 0x7042, 0x20dd, 0x0011, 0x20d5, 0x8822, 0x0016, 0x3008, + 0x2846, 0x1011, 0xa8fd, 0x2081, 0x2802, 0x1011, 0xa8fc, 0xa88f, + 0x20a1, 0x283d, 0x1011, 0xa8fc, 0xa20b, 0x0017, 0x300c, 0xa300, + 0x1de2, 0xd387, 0x0210, 0xa800, 0x26e0, 0x873a, 0xfb02, 0x19f2, + 0x1fe2, 0x0014, 0xa20d, 0x3806, 0x0210, 0x9cc7, 0x0704, 0x0017, + 0x60ff, 0x300c, 0x807f, 0x9521, 0x85a1, 0x806f, 0x9422, 0x84a2, + 0x8720, 0xa211, 0x9d72, 0x8772, 0x8837, 0x2101, 0xa821, 0x10d3, + 0x78e2, 0x9d76, 0xa8fc, 0xd984, 0xf0e2, 0xf0a1, 0xa820, 0x0014, + 0x8831, 0xd166, 0x8830, 0x800f, 0x9401, 0xb520, 0xc802, 0x8820, + 0xa80f, 0x2301, 0xa80d, 0x10d3, 0x78e4, 0x9d76, 0x8821, 0x8820, + 0xa8e6, 0xf123, 0xf142, 0xf101, 0xa865, 0x10d3, 0x70f6, 0x8832, + 0x8203, 0x870c, 0xd99e, 0x6001, 0x0014, 0x6848, 0x0214, 0x8827, + 0x300a, 0x0013, 0xa21b, 0x9d72, 0x2001, 0xa853, 0x8201, 0x1852, + 0xd183, 0x8834, 0x8001, 0xa801, 0x3027, 0x84a8, 0x1a56, 0x8833, + 0x0014, 0xa218, 0x6981, 0x9d7d, 0x6926, 0x6908, 0x8080, 0x9521, + 0xc003, 0x1ab4, 0xa809, 0xa80a, 0x1a34, 0xa806, 0x8080, 0x9521, + 0xc002, 0x1a94, 0xa801, 0x1a14, 0x7021, 0x0014, 0xa300, 0x69e4, + 0x8023, 0x16e1, 0x8001, 0x10f1, 0x6946, 0xa213, 0x1462, 0xa213, + 0x8000, 0x16e1, 0xa808, 0x6161, 0x0014, 0xa214, 0x61c2, 0x8002, + 0x14e1, 0x8004, 0x16e1, 0x0101, 0x300a, 0x8827, 0x0012, 0x8080, + 0x940c, 0xc81d, 0x8001, 0x8492, 0x0013, 0x8000, 0x84a4, 0x8190, + 0x0016, 0x11c3, 0x211e, 0x870e, 0xa21d, 0x0014, 0x9d7d, 0x0014, + 0xa300, 0x8181, 0x842a, 0x84a8, 0x1ce6, 0x882c, 0x0016, 0xa212, + 0x9d72, 0x10d3, 0x70e4, 0x0004, 0x800f, 0x9426, 0xcc1a, 0x9d76, + 0xa8f8, 0x878e, 0x0016, 0xa21c, 0x1035, 0x7965, 0x8001, 0x9405, + 0xc001, 0xa817, 0xa82f, 0xa8a5, 0xa210, 0x3807, 0x300c, 0x807f, + 0x9521, 0x85a1, 0x806f, 0x9422, 0x84a2, 0x817e, 0x872b, 0x8772, + 0x7965, 0x8001, 0x9405, 0xc001, 0xa804, 0xa81c, 0xa892, 0x0014, + 0xa8a6, 0xa21f, 0x8080, 0xa521, 0x85a1, 0x8090, 0xa422, 0x84a2, + 0x6981, 0x9d7d, 0x6923, 0x6903, 0x18b4, 0xa802, 0xa809, 0x1894, + 0x807f, 0x9521, 0x85a1, 0x806f, 0x9422, 0x84a2, 0x7021, 0x0014, + 0xa300, 0x0014, 0xa220, 0x8080, 0xa521, 0x85a1, 0x8090, 0xa422, + 0x84a2, 0x6981, 0x9d7d, 0x6923, 0x6903, 0x18b4, 0xa802, 0xa80c, + 0x1894, 0x807f, 0x9521, 0x85a1, 0x806f, 0x9422, 0x84a2, 0x80fd, + 0x9405, 0x8485, 0x7021, 0x0014, 0xa300, 0xa8ca, 0x0000, 0x0710 +}; +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/firmware/asm_2100.h 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,8147 @@ +/* @(#)asm_2100.h 1.5 */ +/* + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Qlogic, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted provided + * that the following conditions are met: + * 1. Redistribution of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistribution in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Some very early boards have problems loading firmware that is larger than + * 0x8000 words. In order to be able to provide at least *some* support + * for such ancient cards, an alternate firmware set is provided. This firmware + * isn't all that great, but, hey, it's better than nothing. + * + * Define USE_SMALLER_2100_FIRMWARE to select this. + */ +#ifndef USE_SMALLER_2100_FIRMWARE +/************************************************************************ + * * + * --- ISP2100 Fabric Initiator/Target Firmware --- * + * with expanded LUN addressing * + * and FcTape (FCP-2) support * + * * + ************************************************************************/ +/* + * Firmware Version 1.19.24 (14:02 Jul 16, 2002) + */ +static const u_int16_t isp_2100_risc_code[] = { + 0x0078, 0x102d, 0x0000, 0x95f1, 0x0000, 0x0001, 0x0013, 0x0018, + 0x0017, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2032, 0x3030, + 0x3120, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241, + 0x5449, 0x4f4e, 0x2049, 0x5350, 0x3231, 0x3030, 0x2046, 0x6972, + 0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, + 0x312e, 0x3139, 0x2020, 0x2020, 0x2400, 0x2091, 0x2000, 0x20c1, + 0x0021, 0x2039, 0xffff, 0x2019, 0xaaaa, 0x2760, 0x2069, 0x7fff, + 0x20c1, 0x0020, 0x2c2c, 0x2d34, 0x2762, 0x236a, 0x2c24, 0x2d04, + 0x266a, 0x2562, 0xa406, 0x00c0, 0x1052, 0x20c1, 0x0021, 0x2c2c, + 0x2362, 0x2c04, 0x2562, 0xa306, 0x0040, 0x1052, 0x20c1, 0x0020, + 0x2039, 0x8fff, 0x20a1, 0xad00, 0x2708, 0x810d, 0x810d, 0x810d, + 0x810d, 0xa18c, 0x000f, 0x2001, 0x000a, 0xa112, 0xa00e, 0x21a8, + 0x41a4, 0x3400, 0x8211, 0x00c0, 0x105f, 0x2708, 0x3400, 0xa102, + 0x0040, 0x106f, 0x0048, 0x106f, 0x20a8, 0xa00e, 0x41a4, 0x20a1, + 0xa5f1, 0x2009, 0x0000, 0x20a9, 0x070f, 0x41a4, 0x3400, 0x20c9, + 0xaaff, 0x2059, 0x0000, 0x2b78, 0x7823, 0x0004, 0x2089, 0x25c7, + 0x2051, 0xa600, 0x2a70, 0x7762, 0xa786, 0x8fff, 0x0040, 0x1092, + 0x705f, 0xcd00, 0x705b, 0xccf1, 0x7067, 0x0200, 0x706b, 0x0200, + 0x0078, 0x109a, 0x705b, 0xbd01, 0x7067, 0x0100, 0x706b, 0x0100, + 0x705f, 0xbd00, 0x1078, 0x12df, 0x1078, 0x13ca, 0x1078, 0x1577, + 0x1078, 0x1ce9, 0x1078, 0x42ec, 0x1078, 0x76bf, 0x1078, 0x1355, + 0x1078, 0x2ac0, 0x1078, 0x4e93, 0x1078, 0x49a3, 0x1078, 0x594a, + 0x1078, 0x2263, 0x1078, 0x5c43, 0x1078, 0x5485, 0x1078, 0x2162, + 0x1078, 0x2240, 0x2091, 0x3009, 0x7823, 0x0000, 0x0090, 0x10cf, + 0x7820, 0xa086, 0x0002, 0x00c0, 0x10cf, 0x7823, 0x4000, 0x0068, + 0x10c7, 0x781b, 0x0001, 0x2091, 0x5000, 0x2091, 0x4080, 0x2a70, + 0x7003, 0x0000, 0x2001, 0x017f, 0x2003, 0x0000, 0x2a70, 0x7000, + 0xa08e, 0x0003, 0x00c0, 0x10ef, 0x1078, 0x365e, 0x1078, 0x2ae8, + 0x1078, 0x4ee3, 0x1078, 0x4b66, 0x2009, 0x0100, 0x2104, 0xa082, + 0x0002, 0x0048, 0x10f3, 0x1078, 0x5966, 0x0078, 0x10d6, 0x1079, + 0x10f7, 0x0078, 0x10dc, 0x1078, 0x7197, 0x0078, 0x10eb, 0x1101, + 0x1102, 0x11be, 0x10ff, 0x1246, 0x12dc, 0x12dd, 0x12de, 0x1078, + 0x1332, 0x007c, 0x127e, 0x0f7e, 0x2091, 0x8000, 0x7000, 0xa086, + 0x0001, 0x00c0, 0x1198, 0x1078, 0x3aec, 0x2079, 0x0100, 0x7844, + 0xa005, 0x00c0, 0x1198, 0x2011, 0x41dc, 0x1078, 0x5a45, 0x1078, + 0x1adf, 0x780f, 0x00ff, 0x7840, 0xa084, 0xfffb, 0x7842, 0x2011, + 0x8010, 0x73c4, 0x1078, 0x361b, 0x2001, 0xffff, 0x1078, 0x5ae6, + 0x723c, 0xc284, 0x723e, 0x2001, 0xa60c, 0x2014, 0xc2ac, 0x2202, + 0x1078, 0x6f9f, 0x2011, 0x0004, 0x1078, 0x8d1b, 0x1078, 0x489e, + 0x1078, 0x42d4, 0x0040, 0x1144, 0x7087, 0x0001, 0x70bf, 0x0000, + 0x1078, 0x3c9e, 0x0078, 0x1198, 0x1078, 0x4967, 0x0040, 0x114d, + 0x7a0c, 0xc2b4, 0x7a0e, 0x0078, 0x1159, 0x1078, 0x90a6, 0x70cc, + 0xd09c, 0x00c0, 0x1159, 0x7098, 0xa005, 0x0040, 0x1159, 0x1078, + 0x42b8, 0x70d7, 0x0000, 0x70d3, 0x0000, 0x72cc, 0x2079, 0xa652, + 0x7804, 0xd0ac, 0x0040, 0x1165, 0xc295, 0x72ce, 0xa296, 0x0004, + 0x0040, 0x1186, 0x2011, 0x0001, 0x1078, 0x8d1b, 0x7093, 0x0000, + 0x7097, 0xffff, 0x7003, 0x0002, 0x0f7f, 0x1078, 0x2677, 0x2011, + 0x0005, 0x1078, 0x70e0, 0x1078, 0x62d1, 0x0c7e, 0x2061, 0x0100, + 0x60e3, 0x0008, 0x0c7f, 0x127f, 0x0078, 0x119a, 0x7093, 0x0000, + 0x7097, 0xffff, 0x7003, 0x0002, 0x2011, 0x0005, 0x1078, 0x70e0, + 0x1078, 0x62d1, 0x0c7e, 0x2061, 0x0100, 0x60e3, 0x0008, 0x0c7f, + 0x0f7f, 0x127f, 0x007c, 0x0c7e, 0x20a9, 0x0082, 0x2009, 0x007e, + 0x017e, 0x027e, 0x037e, 0x2110, 0x027e, 0x2019, 0x0029, 0x1078, + 0x73d0, 0x027f, 0x1078, 0xa4f1, 0x037f, 0x027f, 0x017f, 0x1078, + 0x298e, 0x8108, 0x00f0, 0x11a0, 0x0c7f, 0x706f, 0x0000, 0x7070, + 0xa084, 0x00ff, 0x7072, 0x709b, 0x0000, 0x007c, 0x127e, 0x2091, + 0x8000, 0x7000, 0xa086, 0x0002, 0x00c0, 0x1244, 0x7094, 0xa086, + 0xffff, 0x0040, 0x11d1, 0x1078, 0x2677, 0x1078, 0x62d1, 0x0078, + 0x1244, 0x70cc, 0xd09c, 0x0040, 0x11fd, 0xd084, 0x0040, 0x11fd, + 0x0f7e, 0x2079, 0x0100, 0x790c, 0xc1b5, 0x790e, 0x0f7f, 0xd08c, + 0x0040, 0x11fd, 0x70d0, 0xa086, 0xffff, 0x0040, 0x11f9, 0x1078, + 0x27f7, 0x1078, 0x62d1, 0x70cc, 0xd094, 0x00c0, 0x1244, 0x2011, + 0x0001, 0x2019, 0x0000, 0x1078, 0x282f, 0x1078, 0x62d1, 0x0078, + 0x1244, 0x70d4, 0xa005, 0x00c0, 0x1244, 0x7090, 0xa005, 0x00c0, + 0x1244, 0x1078, 0x4967, 0x00c0, 0x1244, 0x2001, 0xa653, 0x2004, + 0xd0ac, 0x0040, 0x1227, 0x157e, 0x0c7e, 0x20a9, 0x007f, 0x2009, + 0x0000, 0x017e, 0x1078, 0x45c4, 0x00c0, 0x121a, 0x6000, 0xd0ec, + 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0xf000, 0x0040, 0xa471, + 0xa080, 0x0013, 0x200c, 0xd1ec, 0x0040, 0xa471, 0x2001, 0xa672, + 0x2004, 0xd0ec, 0x0040, 0xa471, 0x6003, 0x0002, 0x6024, 0xc0e5, + 0x6026, 0xd1ac, 0x0040, 0xa44f, 0x0f7e, 0x2c78, 0x1078, 0x495f, + 0x0f7f, 0x0040, 0xa44f, 0x2001, 0xa8a4, 0x2004, 0x603e, 0x2009, + 0xa672, 0x210c, 0xd1f4, 0x00c0, 0xa46f, 0x0078, 0xa461, 0x2009, + 0xa672, 0x210c, 0xd1f4, 0x0040, 0xa45b, 0x6024, 0xc0e4, 0x6026, + 0xa006, 0x0078, 0xa471, 0x2001, 0xa8a4, 0x200c, 0x8103, 0xa100, + 0x603e, 0x6018, 0xa088, 0x002b, 0x2104, 0xa005, 0x0040, 0xa46c, + 0xa088, 0x0003, 0x0078, 0xa464, 0x2c0a, 0x600f, 0x0000, 0xa085, + 0x0001, 0x007c, 0x017e, 0x0c7e, 0x0e7e, 0x6120, 0xa2f0, 0x002b, + 0x2e04, 0x2060, 0x8cff, 0x0040, 0xa491, 0x84ff, 0x00c0, 0xa484, + 0x6020, 0xa106, 0x00c0, 0xa48c, 0x600c, 0x2072, 0x1078, 0x5bc1, + 0x1078, 0x772d, 0x0078, 0xa48e, 0xacf0, 0x0003, 0x2e64, 0x0078, + 0xa47a, 0x0e7f, 0x0c7f, 0x017f, 0x007c, 0x0d7e, 0x6018, 0xa0e8, + 0x002b, 0x2d04, 0xa005, 0x0040, 0xa4a7, 0xac06, 0x0040, 0xa4a5, + 0x2d04, 0xa0e8, 0x0003, 0x0078, 0xa499, 0x600c, 0x206a, 0x0d7f, + 0x007c, 0x027e, 0x037e, 0x157e, 0x2011, 0xa626, 0x2204, 0xa084, + 0x00ff, 0x2019, 0xab8e, 0x2334, 0xa636, 0x00c0, 0xa4d5, 0x8318, + 0x2334, 0x2204, 0xa084, 0xff00, 0xa636, 0x00c0, 0xa4d5, 0x2011, + 0xab90, 0x6018, 0xa098, 0x000a, 0x20a9, 0x0004, 0x1078, 0x80de, + 0x00c0, 0xa4d5, 0x2011, 0xab94, 0x6018, 0xa098, 0x0006, 0x20a9, + 0x0004, 0x1078, 0x80de, 0x00c0, 0xa4d5, 0x157f, 0x037f, 0x027f, + 0x007c, 0x0e7e, 0x2071, 0xa600, 0x1078, 0x42b8, 0x1078, 0x2677, + 0x0e7f, 0x007c, 0x0e7e, 0x6018, 0x2070, 0x7000, 0xd0fc, 0x0040, + 0xa4eb, 0x1078, 0xa4ed, 0x0e7f, 0x007c, 0x6850, 0xc0e5, 0x6852, + 0x007c, 0x0e7e, 0x0c7e, 0x077e, 0x067e, 0x057e, 0x047e, 0x027e, + 0x017e, 0x127e, 0x2091, 0x8000, 0x2029, 0xa8ba, 0x252c, 0x2021, + 0xa8c0, 0x2424, 0x2061, 0xad00, 0x2071, 0xa600, 0x7648, 0x7064, + 0xa606, 0x0040, 0xa545, 0x671c, 0xa786, 0x0001, 0x0040, 0xa514, + 0xa786, 0x0008, 0x00c0, 0xa53b, 0x2500, 0xac06, 0x0040, 0xa53b, + 0x2400, 0xac06, 0x0040, 0xa53b, 0x1078, 0xa242, 0x0040, 0xa53b, + 0x1078, 0xa256, 0x00c0, 0xa53b, 0x6000, 0xa086, 0x0004, 0x00c0, + 0xa52d, 0x017e, 0x1078, 0x1757, 0x017f, 0x1078, 0x8eec, 0x00c0, + 0xa533, 0x1078, 0x28a6, 0x1078, 0x8f00, 0x00c0, 0xa539, 0x1078, + 0x7c83, 0x1078, 0x8ec6, 0xace0, 0x0010, 0x2001, 0xa616, 0x2004, + 0xac02, 0x00c8, 0xa545, 0x0078, 0xa504, 0x127f, 0x017f, 0x027f, + 0x047f, 0x057f, 0x067f, 0x077f, 0x0c7f, 0x0e7f, 0x007c, 0x127e, + 0x007e, 0x0e7e, 0x017e, 0x2091, 0x8000, 0x2071, 0xa640, 0xd5a4, + 0x0040, 0xa55d, 0x7034, 0x8000, 0x7036, 0xd5b4, 0x0040, 0xa563, + 0x7030, 0x8000, 0x7032, 0xd5ac, 0x0040, 0xa579, 0x2500, 0xa084, + 0x0007, 0xa08e, 0x0003, 0x0040, 0xa579, 0xa08e, 0x0004, 0x0040, + 0xa579, 0xa08e, 0x0005, 0x0040, 0xa579, 0x2071, 0xa64a, 0x1078, + 0xa5ba, 0x017f, 0x0e7f, 0x007f, 0x127f, 0x007c, 0x127e, 0x007e, + 0x0e7e, 0x017e, 0x2091, 0x8000, 0x2071, 0xa640, 0xd5a4, 0x0040, + 0xa58c, 0x7034, 0x8000, 0x7036, 0xd5b4, 0x0040, 0xa592, 0x7030, + 0x8000, 0x7032, 0xd5ac, 0x0040, 0xa5a8, 0x2500, 0xa084, 0x0007, + 0xa08e, 0x0003, 0x0040, 0xa5a8, 0xa08e, 0x0004, 0x0040, 0xa5a8, + 0xa08e, 0x0005, 0x0040, 0xa5a8, 0x2071, 0xa64a, 0x1078, 0xa5ba, + 0x017f, 0x0e7f, 0x007f, 0x127f, 0x007c, 0x127e, 0x007e, 0x0e7e, + 0x2091, 0x8000, 0x2071, 0xa642, 0x1078, 0xa5ba, 0x0e7f, 0x007f, + 0x127f, 0x007c, 0x2e04, 0x8000, 0x2072, 0x00c8, 0xa5c3, 0x8e70, + 0x2e04, 0x8000, 0x2072, 0x007c, 0x0e7e, 0x2071, 0xa640, 0x1078, + 0xa5ba, 0x0e7f, 0x007c, 0x0e7e, 0x2071, 0xa644, 0x1078, 0xa5ba, + 0x0e7f, 0x007c, 0x127e, 0x007e, 0x0e7e, 0x2091, 0x8000, 0x2071, + 0xa640, 0x7044, 0x8000, 0x7046, 0x0e7f, 0x007f, 0x127f, 0x007c, + 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, + 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, + 0xa50c +}; +#else +/* + * Firmware Version 1.15.37 (15:36 May 03, 1999) + */ +static const u_int16_t isp_2100_risc_code[] = { + 0x0078, 0x1029, 0x0000, 0x66e6, 0x0000, 0x2043, 0x4f50, 0x5952, + 0x4947, 0x4854, 0x2031, 0x3939, 0x3620, 0x514c, 0x4f47, 0x4943, + 0x2043, 0x4f52, 0x504f, 0x5241, 0x5449, 0x4f4e, 0x2049, 0x5350, + 0x3231, 0x3030, 0x2046, 0x6972, 0x6d77, 0x6172, 0x6520, 0x2056, + 0x6572, 0x7369, 0x6f6e, 0x2030, 0x312e, 0x3135, 0x2020, 0x2020, + 0x2400, 0x20c1, 0x0021, 0x20a1, 0x76e6, 0x2009, 0x0000, 0x20a9, + 0x071a, 0x41a4, 0x3400, 0x20c9, 0x7bff, 0x2091, 0x2000, 0x2059, + 0x0000, 0x2b78, 0x7823, 0x0004, 0x2089, 0x209a, 0x2051, 0x7700, + 0x2a70, 0x705b, 0x9600, 0x705f, 0xffff, 0x7057, 0x95f9, 0x7063, + 0x0300, 0x1078, 0x127a, 0x20a1, 0x7e00, 0x715c, 0x810d, 0x810d, + 0x810d, 0x810d, 0xa18c, 0x000f, 0x2001, 0x0007, 0xa112, 0xa00e, + 0x21a8, 0x41a4, 0x3400, 0x8211, 0x00c0, 0x1058, 0x715c, 0x3400, + 0xa102, 0x0040, 0x1068, 0x0048, 0x1068, 0x20a8, 0xa00e, 0x41a4, + 0x1078, 0x1241, 0x1078, 0x1366, 0x1078, 0x14eb, 0x1078, 0x19c0, + 0x1078, 0x362b, 0x1078, 0x5cac, 0x1078, 0x12f1, 0x1078, 0x2429, + 0x1078, 0x3d6e, 0x1078, 0x3b46, 0x1078, 0x45af, 0x1078, 0x1e55, + 0x1078, 0x47ef, 0x1078, 0x428f, 0x1078, 0x1d74, 0x1078, 0x1e34, + 0x2091, 0x3009, 0x7823, 0x0000, 0x0090, 0x109d, 0x7820, 0xa086, + 0x0002, 0x00c0, 0x109d, 0x7823, 0x4000, 0x0068, 0x1095, 0x781b, + 0x0001, 0x2091, 0x5000, 0x2091, 0x4080, 0x2a70, 0x7003, 0x0000, + 0x2001, 0x017f, 0x2003, 0x0000, 0x2a70, 0x7000, 0xa08e, 0x0003, + 0x00c0, 0x10bd, 0x1078, 0x2d9c, 0x1078, 0x2451, 0x1078, 0x3dbe, + 0x1078, 0x3c31, 0x2009, 0x0100, 0x2104, 0xa082, 0x0002, 0x0048, + 0x10c1, 0x1078, 0x45c7, 0x0078, 0x10a4, 0x1079, 0x10c5, 0x0078, + 0x10aa, 0x1078, 0x597e, 0x0078, 0x10b9, 0x10cf, 0x10d0, 0x1143, + 0x10cd, 0x11be, 0x123e, 0x123f, 0x1240, 0x1078, 0x12cd, 0x007c, + 0x127e, 0x0f7e, 0x2091, 0x8000, 0x1078, 0x2ec1, 0x2079, 0x0100, + 0x7844, 0xa005, 0x00c0, 0x1134, 0x2011, 0x3558, 0x1078, 0x4689, + 0x780f, 0x00ff, 0x7840, 0xa084, 0xfffb, 0x7842, 0x2011, 0x8010, + 0x73b8, 0x1078, 0x2d59, 0x1078, 0x57c9, 0x2011, 0x0004, 0x1078, + 0x6a6d, 0x1078, 0x3ae0, 0x70c7, 0x0000, 0x70c3, 0x0000, 0x1078, + 0x1137, 0x72bc, 0x2079, 0x7751, 0x7804, 0xd0ac, 0x0040, 0x1101, + 0xc295, 0x72be, 0xa296, 0x0004, 0x0040, 0x1122, 0x2011, 0x0001, + 0x1078, 0x6a6d, 0x708b, 0x0000, 0x708f, 0xffff, 0x7003, 0x0002, + 0x0f7f, 0x1078, 0x214a, 0x2011, 0x0005, 0x1078, 0x58d8, 0x1078, + 0x4d96, 0x0c7e, 0x2061, 0x0100, 0x60e3, 0x0008, 0x0c7f, 0x127f, + 0x0078, 0x1136, 0x708b, 0x0000, 0x708f, 0xffff, 0x7003, 0x0002, + 0x2011, 0x0005, 0x1078, 0x58d8, 0x1078, 0x4d96, 0x0c7e, 0x2061, + 0x0100, 0x60e3, 0x0008, 0x0c7f, 0x0f7f, 0x127f, 0x007c, 0x0c7e, + 0x20a9, 0x0082, 0x2009, 0x007e, 0x1078, 0x3834, 0x8108, 0x00f0, + 0x113c, 0x0c7f, 0x007c, 0x127e, 0x2091, 0x8000, 0x708c, 0xa086, + 0xffff, 0x0040, 0x1151, 0x1078, 0x214a, 0x1078, 0x4d96, 0x0078, + 0x11bc, 0x70bc, 0xd09c, 0x0040, 0x1179, 0xd084, 0x0040, 0x1179, + 0x0f7e, 0x2079, 0x0100, 0x790c, 0xc1b5, 0x790e, 0x0f7f, 0xd08c, + 0x0040, 0x1179, 0x70c0, 0xa086, 0xffff, 0x0040, 0x1175, 0x1078, + 0x223f, 0x1078, 0x4d96, 0x2011, 0x0001, 0x2019, 0x0000, 0x1078, + 0x2277, 0x1078, 0x4d96, 0x0078, 0x11bc, 0x70c4, 0xa005, 0x00c0, + 0x11bc, 0x7088, 0xa005, 0x00c0, 0x11bc, 0x2001, 0x7752, 0x2004, + 0xd0ac, 0x0040, 0x119f, 0x157e, 0x0c7e, 0x20a9, 0x007f, 0x2009, + 0x0000, 0x017e, 0x1078, 0x384c, 0x00c0, 0x1192, 0x6000, 0xd0ec, + 0x00c0, 0x119a, 0x017f, 0x8108, 0x00f0, 0x1189, 0x0c7f, 0x157f, + 0x0078, 0x119f, 0x017f, 0x0c7f, 0x157f, 0x0078, 0x11bc, 0x7003, + 0x0003, 0x708f, 0xffff, 0x2001, 0x0000, 0x1078, 0x2025, 0x1078, + 0x2dd7, 0x2001, 0x7937, 0x2004, 0xa086, 0x0005, 0x00c0, 0x11b4, + 0x2011, 0x0000, 0x1078, 0x58d8, 0x2011, 0x0000, 0x1078, 0x58e2, + 0x1078, 0x4d96, 0x1078, 0x4e56, 0x127f, 0x007c, 0x017e, 0x0f7e, + 0x127e, 0x2091, 0x8000, 0x2079, 0x0100, 0x7940, 0xa18c, 0x0010, + 0x7942, 0x7924, 0xd1b4, 0x0040, 0x11cf, 0x7827, 0x0040, 0xd19c, + 0x0040, 0x11d4, 0x7827, 0x0008, 0x007e, 0x037e, 0x157e, 0x7900, + 0xa18a, 0x0003, 0x0050, 0x11fa, 0x7954, 0xd1ac, 0x00c0, 0x11fa, + 0x2009, 0x00f8, 0x1078, 0x35fa, 0x7843, 0x0090, 0x7843, 0x0010, + 0x20a9, 0x09c4, 0x7820, 0xd09c, 0x00c0, 0x11f2, 0x7824, 0xd0ac, + 0x00c0, 0x122e, 0x00f0, 0x11ea, 0x2001, 0x0001, 0x1078, 0x2025, + 0x0078, 0x1237, 0x7853, 0x0000, 0x782f, 0x0020, 0x20a9, 0x0008, + 0x00e0, 0x1200, 0x2091, 0x6000, 0x00f0, 0x1200, 0x7853, 0x0400, + 0x782f, 0x0000, 0x2009, 0x00f8, 0x1078, 0x35fa, 0x20a9, 0x000e, + 0x0005, 0x00f0, 0x1210, 0x7853, 0x1400, 0x7843, 0x0090, 0x7843, + 0x0010, 0x2019, 0x61a8, 0x7854, 0x0005, 0x0005, 0xd08c, 0x0040, + 0x1225, 0x7824, 0xd0ac, 0x00c0, 0x122e, 0x8319, 0x00c0, 0x121b, + 0x2001, 0x0001, 0x1078, 0x2025, 0x0078, 0x1235, 0x7828, 0xc09d, + 0x782a, 0x7827, 0x0008, 0x7827, 0x0040, 0x7853, 0x0400, 0x157f, + 0x037f, 0x007f, 0x127f, 0x0f7f, 0x017f, 0x007c, 0x007c, 0x007c, + 0x007c, 0x2a70, 0x2009, 0x0100, 0x2104, 0xa082, 0x0002, 0x0048, + 0x124d, 0x704f, 0xffff, 0x0078, 0x124f, 0x704f, 0x0000, 0x7053, + 0xffff, 0x7067, 0x0000, 0x706b, 0x0000, 0x2061, 0x7920, 0x6003, + 0x0909, 0x6007, 0x0000, 0x600b, 0x8800, 0x600f, 0x0200, 0x6013, + 0x00ff, 0x6017, 0x0003, 0x601b, 0x0000, 0x601f, 0x07d0, 0x2061, + 0x7928, 0x6003, 0x8000, 0x6007, 0x0000, 0x600b, 0x0000, 0x600f, + 0x0200, 0x6013, 0x00ff, 0x6017, 0x0000, 0x601b, 0x0001, 0x601f, + 0x0000, 0x007c, 0x1078, 0x12a0, 0x2011, 0x0000, 0x81ff, 0x0040, + 0x129f, 0xa186, 0x0001, 0x00c0, 0x128f, 0x705f, 0x8fff, 0x7057, + 0x8601, 0x7063, 0x0100, 0x705b, 0x8600, 0x0078, 0x129d, 0xa186, + 0x0002, 0x00c0, 0x1297, 0x2011, 0x0000, 0x0078, 0x129d, 0xa186, + 0x0005, 0x00c0, 0x129d, 0x2011, 0x0001, 0x1078, 0x12c7, 0x007c, + 0x2009, 0x0000, 0x2011, 0x0000, 0x1078, 0x12c7, 0x2019, 0xaaaa, + 0x2061, 0xffff, 0x2362, 0x2c24, 0x2061, 0x7fff, 0x2c04, 0xa406, + 0x0040, 0x12b5, 0xc18d, 0x0078, 0x12c2, 0xc185, 0x2011, 0x0001, + 0x1078, 0x12c7, 0x2061, 0xffff, 0x2362, 0x2c04, 0xa306, 0x00c0, + 0x12c2, 0xc195, 0x2011, 0x0001, 0x1078, 0x12c7, 0x007c, 0x3800, + 0xa084, 0xfffc, 0xa205, 0x20c0, 0x007c, 0x2091, 0x8000, 0x0068, + 0x12cf, 0x007e, 0x017e, 0x2079, 0x0000, 0x7818, 0xa084, 0x0000, + 0x00c0, 0x12d5, 0x017f, 0x792e, 0x007f, 0x782a, 0x007f, 0x7826, + 0x3900, 0x783a, 0x7823, 0x8002, 0x781b, 0x0001, 0x2091, 0x5000, + 0x2091, 0x4080, 0x2079, 0x7700, 0x7803, 0x0005, 0x0078, 0x12ee, + 0x007c, 0x2071, 0x7700, 0x7158, 0x712e, 0x2021, 0x0001, 0xa190, + 0x002d, 0xa298, 0x002d, 0x0048, 0x1307, 0x705c, 0xa302, 0x00c8, + 0x1307, 0x220a, 0x2208, 0x2310, 0x8420, 0x0078, 0x12f9, 0x200b, + 0x0000, 0x749e, 0x74a2, 0x007c, 0x0e7e, 0x127e, 0x2091, 0x8000, + 0x2071, 0x7700, 0x70a0, 0xa0ea, 0x0010, 0x00c8, 0x131a, 0xa06e, + 0x0078, 0x1324, 0x8001, 0x70a2, 0x702c, 0x2068, 0x2d04, 0x702e, + 0x206b, 0x0000, 0x6807, 0x0000, 0x127f, 0x0e7f, 0x007c, 0x0e7e, + 0x2071, 0x7700, 0x127e, 0x2091, 0x8000, 0x70a0, 0x8001, 0x00c8, + 0x1334, 0xa06e, 0x0078, 0x133d, 0x70a2, 0x702c, 0x2068, 0x2d04, + 0x702e, 0x206b, 0x0000, 0x6807, 0x0000, 0x127f, 0x0e7f, 0x007c, + 0x0e7e, 0x127e, 0x2091, 0x8000, 0x2071, 0x7700, 0x702c, 0x206a, + 0x2d00, 0x702e, 0x70a0, 0x8000, 0x70a2, 0x127f, 0x0e7f, 0x007c, + 0x8dff, 0x0040, 0x135c, 0x6804, 0x6807, 0x0000, 0x007e, 0x1078, + 0x1340, 0x0d7f, 0x0078, 0x1350, 0x007c, 0x0e7e, 0x2071, 0x7700, + 0x70a0, 0xa08a, 0x0010, 0xa00d, 0x0e7f, 0x007c, 0x0e7e, 0x2071, + 0x7959, 0x7007, 0x0000, 0x701b, 0x0000, 0x701f, 0x0000, 0x2071, + 0x0000, 0x7010, 0xa085, 0x8004, 0x7012, 0x0e7f, 0x007c, 0x0e7e, + 0x2270, 0x700b, 0x0000, 0x2071, 0x7959, 0x7018, 0xa088, 0x7962, + 0x220a, 0x8000, 0xa084, 0x0007, 0x701a, 0x7004, 0xa005, 0x00c0, + 0x138f, 0x0f7e, 0x2079, 0x0010, 0x1078, 0x13a0, 0x0f7f, 0x0e7f, + 0x007c, 0x0e7e, 0x2071, 0x7959, 0x7004, 0xa005, 0x00c0, 0x139e, + 0x0f7e, 0x2079, 0x0010, 0x1078, 0x13a0, 0x0f7f, 0x0e7f, 0x007c, + 0x7000, 0x0079, 0x13a3, 0x13a7, 0x1411, 0x142e, 0x142e, 0x7018, + 0x711c, 0xa106, 0x00c0, 0x13af, 0x7007, 0x0000, 0x007c, 0x0d7e, + 0xa180, 0x7962, 0x2004, 0x700a, 0x2068, 0x8108, 0xa18c, 0x0007, + 0x711e, 0x7803, 0x0026, 0x6824, 0x7832, 0x6828, 0x7836, 0x682c, + 0x783a, 0x6830, 0x783e, 0x6810, 0x700e, 0x680c, 0x7016, 0x6804, + 0x0d7f, 0xd084, 0x0040, 0x13d1, 0x7007, 0x0001, 0x1078, 0x13d6, + 0x007c, 0x7007, 0x0002, 0x1078, 0x13ec, 0x007c, 0x017e, 0x027e, + 0x710c, 0x2011, 0x0040, 0xa182, 0x0040, 0x00c8, 0x13e1, 0x2110, + 0xa006, 0x700e, 0x7212, 0x8203, 0x7822, 0x7803, 0x0020, 0x7803, + 0x0041, 0x027f, 0x017f, 0x007c, 0x017e, 0x027e, 0x137e, 0x147e, + 0x157e, 0x7014, 0x2098, 0x20a1, 0x0014, 0x7803, 0x0026, 0x710c, + 0x2011, 0x0040, 0xa182, 0x0040, 0x00c8, 0x1400, 0x2110, 0xa006, + 0x700e, 0x22a8, 0x53a6, 0x8203, 0x7822, 0x7803, 0x0020, 0x7803, + 0x0001, 0x3300, 0x7016, 0x157f, 0x147f, 0x137f, 0x027f, 0x017f, + 0x007c, 0x137e, 0x147e, 0x157e, 0x2099, 0x77e5, 0x20a1, 0x0018, + 0x20a9, 0x0008, 0x53a3, 0x7803, 0x0020, 0x127e, 0x2091, 0x8000, + 0x7803, 0x0041, 0x7007, 0x0003, 0x7000, 0xc084, 0x7002, 0x700b, + 0x77e0, 0x127f, 0x157f, 0x147f, 0x137f, 0x007c, 0x137e, 0x147e, + 0x157e, 0x2001, 0x7814, 0x209c, 0x20a1, 0x0014, 0x7803, 0x0026, + 0x2001, 0x7815, 0x20ac, 0x53a6, 0x2099, 0x7816, 0x20a1, 0x0018, + 0x20a9, 0x0008, 0x53a3, 0x7803, 0x0020, 0x127e, 0x2091, 0x8000, + 0x7803, 0x0001, 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0x75ad, 0x047e, 0x1078, 0x75fd, 0x047f, 0x0d7f, 0x1078, 0x6bb6, + 0x88ff, 0x00c0, 0x75c6, 0xace0, 0x0008, 0x2001, 0x7715, 0x2004, + 0xac02, 0x00c8, 0x75bd, 0x0078, 0x756f, 0xa006, 0x127f, 0x027f, + 0x067f, 0x077f, 0x0c7f, 0x0e7f, 0x0f7f, 0x007c, 0xa8c5, 0x0001, + 0x0078, 0x75be, 0x087e, 0x2041, 0x0000, 0x2c20, 0x2019, 0x0002, + 0x6218, 0x1078, 0x5a2d, 0x1078, 0x5ace, 0x1078, 0x7562, 0x087f, + 0x007c, 0x027e, 0x047e, 0x087e, 0x0c7e, 0x157e, 0x2c20, 0x20a9, + 0x007f, 0x2009, 0x0000, 0x017e, 0x037e, 0x1078, 0x384c, 0x00c0, + 0x75f2, 0x2c10, 0x2041, 0x0000, 0x1078, 0x5a2d, 0x1078, 0x5ace, + 0x1078, 0x7562, 0x037f, 0x017f, 0x8108, 0x00f0, 0x75e3, 0x157f, + 0x0c7f, 0x087f, 0x047f, 0x027f, 0x007c, 0x017e, 0x0f7e, 0x8dff, + 0x0040, 0x7611, 0x6800, 0xa07d, 0x0040, 0x760e, 0x6803, 0x0000, + 0x6b52, 0x1078, 0x3b92, 0x2f68, 0x0078, 0x7602, 0x6b52, 0x1078, + 0x3b92, 0x0f7f, 0x017f, 0x007c, 0x0e7e, 0x047e, 0x037e, 0x2061, + 0x7e00, 0x2071, 0x7700, 0x7444, 0x7060, 0x8001, 0xa402, 0x00c8, + 0x763c, 0x2100, 0xac06, 0x0040, 0x762e, 0x6000, 0xa086, 0x0000, + 0x0040, 0x762e, 0x6008, 0xa206, 0x0040, 0x7638, 0xace0, 0x0008, + 0x2001, 0x7715, 0x2004, 0xac02, 0x00c8, 0x763c, 0x0078, 0x7619, + 0xa085, 0x0001, 0x0078, 0x763d, 0xa006, 0x037f, 0x047f, 0x0e7f, + 0x007c, 0x0d7e, 0x007e, 0x1078, 0x1327, 0x007f, 0x1040, 0x12cd, + 0x6837, 0x010d, 0x6803, 0x0000, 0x683b, 0x0000, 0x685b, 0x0000, + 0x685e, 0x6956, 0x6c46, 0x684f, 0x0000, 0x1078, 0x3b92, 0x0d7f, + 0x007c, 0x6700, 0xa786, 0x0000, 0x0040, 0x766c, 0xa786, 0x0001, + 0x0040, 0x766c, 0xa786, 0x000a, 0x0040, 0x766c, 0xa786, 0x0009, + 0x0040, 0x766c, 0xa085, 0x0001, 0x007c, 0x0e7e, 0x6018, 0x2070, + 0x70a0, 0xa206, 0x0e7f, 0x007c, 0x127e, 0x007e, 0x0e7e, 0x2091, + 0x8000, 0x2071, 0x7740, 0xd5a4, 0x0040, 0x7681, 0x7034, 0x8000, + 0x7036, 0xd5b4, 0x0040, 0x7687, 0x7030, 0x8000, 0x7032, 0xd5ac, + 0x0040, 0x768e, 0x2071, 0x774a, 0x1078, 0x76bd, 0x0e7f, 0x007f, + 0x127f, 0x007c, 0x127e, 0x007e, 0x0e7e, 0x2091, 0x8000, 0x2071, + 0x7740, 0xd5a4, 0x0040, 0x769f, 0x7034, 0x8000, 0x7036, 0xd5b4, + 0x0040, 0x76a5, 0x7030, 0x8000, 0x7032, 0xd5ac, 0x0040, 0x76ac, + 0x2071, 0x774a, 0x1078, 0x76bd, 0x0e7f, 0x007f, 0x127f, 0x007c, + 0x127e, 0x007e, 0x0e7e, 0x2091, 0x8000, 0x2071, 0x7742, 0x1078, + 0x76bd, 0x0e7f, 0x007f, 0x127f, 0x007c, 0x2e04, 0x8000, 0x2072, + 0x00c8, 0x76c6, 0x8e70, 0x2e04, 0x8000, 0x2072, 0x007c, 0x0e7e, + 0x2071, 0x7740, 0x1078, 0x76bd, 0x0e7f, 0x007c, 0x0e7e, 0x2071, + 0x7744, 0x1078, 0x76bd, 0x0e7f, 0x007c, 0x0001, 0x0002, 0x0004, + 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 0x0100, 0x0200, 0x0400, + 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, 0x687d +}; +#endif --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/firmware/asm_2200.h 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,5286 @@ +/* @(#)asm_2200.h 1.5 */ +/* + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 by Qlogic, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted provided + * that the following conditions are met: + * 1. Redistribution of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistribution in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/************************************************************************ + * * + * --- ISP2200 Initiator/Target Firmware --- * + * with Fabric (Public Loop), Point-point, and * + * expanded LUN addressing for FCTAPE * + * * + ************************************************************************/ +/* + * Firmware Version 2.02.03 (08:58 May 02, 2002) + */ +static const u_int16_t isp_2200_risc_code[] = { + 0x0470, 0x0000, 0x0000, 0xa3f2, 0x0000, 0x0002, 0x0002, 0x0003, + 0x0017, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2032, 0x3030, + 0x3120, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241, + 0x5449, 0x4f4e, 0x2049, 0x5350, 0x3232, 0x3030, 0x2046, 0x6972, + 0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, + 0x322e, 0x3032, 0x2e30, 0x3320, 0x2020, 0x2020, 0x2400, 0x20c1, + 0x0005, 0x2001, 0x017f, 0x2003, 0x0000, 0x20c9, 0xb9ff, 0x2091, + 0x2000, 0x2059, 0x0000, 0x2b78, 0x7823, 0x0004, 0x2089, 0x2930, + 0x2051, 0xb400, 0x2a70, 0x2029, 0xec00, 0x2031, 0xffff, 0x2039, + 0xebe9, 0x2021, 0x0200, 0x0804, 0x1464, 0x20a1, 0xb3f2, 0xa00e, + 0x20a9, 0x080e, 0x41a4, 0x3400, 0x7562, 0x7666, 0x775e, 0x746a, + 0x746e, 0x20a1, 0xbc00, 0x7164, 0x810d, 0x810d, 0x810d, 0x810d, + 0xa18c, 0x000f, 0x2001, 0x000b, 0xa112, 0xa00e, 0x21a8, 0x41a4, + 0x3400, 0x8211, 0x1dd8, 0x7164, 0x3400, 0xa102, 0x0120, 0x0218, + 0x20a8, 0xa00e, 0x41a4, 0x3800, 0xd08c, 0x01d8, 0x2009, 0xb400, + 0x810d, 0x810d, 0x810d, 0x810d, 0xa18c, 0x000f, 0x2001, 0x0001, + 0xa112, 0x20a1, 0x1000, 0xa00e, 0x21a8, 0x41a4, 0x8211, 0x1de0, + 0x2009, 0xb400, 0x3400, 0xa102, 0x0120, 0x0218, 0x20a8, 0xa00e, + 0x41a4, 0x080c, 0x140d, 0x080c, 0x162e, 0x080c, 0x17c7, 0x080c, + 0x1f73, 0x080c, 0x4bb9, 0x080c, 0x8562, 0x080c, 0x15b7, 0x080c, + 0x2e88, 0x080c, 0x5d4b, 0x080c, 0x5302, 0x080c, 0x6893, 0x080c, + 0x24d9, 0x080c, 0x6b26, 0x080c, 0x637c, 0x080c, 0x239b, 0x080c, + 0x24a7, 0x2091, 0x3009, 0x7823, 0x0000, 0x1004, 0x10c5, 0x7820, + 0xa086, 0x0002, 0x1150, 0x7823, 0x4000, 0x0e04, 0x10bd, 0x781b, + 0x0001, 0x2091, 0x5000, 0x2091, 0x4080, 0x2a70, 0x7003, 0x0000, + 0x2a70, 0x7000, 0xa08e, 0x0003, 0x1158, 0x080c, 0x3ec6, 0x080c, + 0x2eaf, 0x080c, 0x5d99, 0x080c, 0x54b1, 0x080c, 0x68be, 0x0c80, + 0x000b, 0x0c98, 0x10e4, 0x10e5, 0x1210, 0x10e2, 0x12d9, 0x140a, + 0x140b, 0x140c, 0x080c, 0x1511, 0x0005, 0x0126, 0x00f6, 0x2091, + 0x8000, 0x7000, 0xa086, 0x0001, 0x1904, 0x11ed, 0x080c, 0x1584, + 0x080c, 0x5a90, 0x0150, 0x080c, 0x5ab6, 0x15c0, 0x2079, 0x0100, + 0x7828, 0xa085, 0x1800, 0x782a, 0x0488, 0x080c, 0x59c8, 0x7000, + 0xa086, 0x0001, 0x1904, 0x11ed, 0x708c, 0xa086, 0x0028, 0x1904, + 0x11ed, 0x2001, 0x0161, 0x2003, 0x0001, 0x2079, 0x0100, 0x7827, + 0xffff, 0x7a28, 0xa295, 0x1e2f, 0x7a2a, 0x2011, 0x5963, 0x080c, + 0x6961, 0x2011, 0x5956, 0x080c, 0x6a21, 0x2011, 0x59a5, 0x080c, + 0x6961, 0x2011, 0x4a96, 0x080c, 0x6961, 0x2011, 0x8030, 0x2019, + 0x0000, 0x708b, 0x0000, 0x080c, 0x1db8, 0x00e8, 0x080c, 0x4449, + 0x2079, 0x0100, 0x7844, 0xa005, 0x1904, 0x11ed, 0x2011, 0x4a96, + 0x080c, 0x6961, 0x2011, 0x59a5, 0x080c, 0x6961, 0x080c, 0x1db8, + 0x2001, 0xb68d, 0x2004, 0x780e, 0x7840, 0xa084, 0xfffb, 0x7842, + 0x2011, 0x8010, 0x73cc, 0x080c, 0x3e8a, 0x723c, 0xc284, 0x723e, + 0x2001, 0xb40c, 0x200c, 0xc1ac, 0x2102, 0x080c, 0x7edf, 0x2011, + 0x0004, 0x080c, 0x9bf1, 0x080c, 0x520e, 0x080c, 0x5a90, 0x0158, + 0x080c, 0x4ba2, 0x0140, 0x708b, 0x0001, 0x70c7, 0x0000, 0x080c, + 0x45e6, 0x0804, 0x11ed, 0x080c, 0x52ca, 0x0120, 0x7a0c, 0xc2b4, + 0x7a0e, 0x0060, 0x7073, 0x0000, 0x080c, 0x9f99, 0x70d4, 0xd09c, + 0x1128, 0x70a0, 0xa005, 0x0110, 0x080c, 0x4b80, 0x70df, 0x0000, + 0x70db, 0x0000, 0x72d4, 0x080c, 0x5a90, 0x1178, 0x2011, 0x0000, + 0x0016, 0x080c, 0x28b1, 0x2019, 0xb68f, 0x211a, 0x001e, 0x7053, + 0xffff, 0x7057, 0x00ef, 0x7077, 0x0000, 0x2079, 0xb452, 0x7804, + 0xd0ac, 0x0108, 0xc295, 0x72d6, 0x080c, 0x5a90, 0x0118, 0xa296, + 0x0004, 0x0548, 0x2011, 0x0001, 0x080c, 0x9bf1, 0x709b, 0x0000, + 0x709f, 0xffff, 0x7003, 0x0002, 0x2079, 0x0100, 0x7827, 0x0003, + 0x7828, 0xa085, 0x0003, 0x782a, 0x00fe, 0x080c, 0x2a7e, 0x2011, + 0x0005, 0x080c, 0x801f, 0x080c, 0x7134, 0x080c, 0x5a90, 0x0148, + 0x00c6, 0x2061, 0x0100, 0x0016, 0x080c, 0x28b1, 0x61e2, 0x001e, + 0x00ce, 0x012e, 0x0420, 0x709b, 0x0000, 0x709f, 0xffff, 0x7003, + 0x0002, 0x00f6, 0x2079, 0x0100, 0x7827, 0x0003, 0x7828, 0xa085, + 0x0003, 0x782a, 0x00fe, 0x2011, 0x0005, 0x080c, 0x801f, 0x080c, + 0x7134, 0x080c, 0x5a90, 0x0148, 0x00c6, 0x2061, 0x0100, 0x0016, + 0x080c, 0x28b1, 0x61e2, 0x001e, 0x00ce, 0x00fe, 0x012e, 0x0005, + 0x00c6, 0x080c, 0x5a90, 0x1118, 0x20a9, 0x0100, 0x0010, 0x20a9, + 0x0082, 0x080c, 0x5a90, 0x1118, 0x2009, 0x0000, 0x0010, 0x2009, + 0x007e, 0x080c, 0x2d5b, 0x8108, 0x1f04, 0x1201, 0x00ce, 0x7073, + 0x0000, 0x7074, 0xa084, 0x00ff, 0x7076, 0x70a3, 0x0000, 0x0005, + 0x0126, 0x2091, 0x8000, 0x7000, 0xa086, 0x0002, 0x1904, 0x12d7, + 0x709c, 0xa086, 0xffff, 0x0130, 0x080c, 0x2a7e, 0x080c, 0x7134, + 0x0804, 0x12d7, 0x70d4, 0xd0ac, 0x1110, 0xd09c, 0x0540, 0xd084, + 0x0530, 0x0006, 0x0016, 0x2001, 0x0103, 0x2009, 0xb68d, 0x210c, + 0x2102, 0x001e, 0x000e, 0xd08c, 0x01d0, 0x70d8, 0xa086, 0xffff, + 0x0190, 0x080c, 0x2bdd, 0x080c, 0x7134, 0x70d4, 0xd094, 0x1904, + 0x12d7, 0x2011, 0x0001, 0x2019, 0x0000, 0x080c, 0x2c13, 0x080c, + 0x7134, 0x0804, 0x12d7, 0x70dc, 0xa005, 0x1904, 0x12d7, 0x7098, + 0xa005, 0x1904, 0x12d7, 0x70d4, 0xd0a4, 0x0118, 0xd0b4, 0x0904, + 0x12d7, 0x080c, 0x52ca, 0x1904, 0x12d7, 0x2001, 0xb453, 0x2004, + 0xd0ac, 0x01c8, 0x0156, 0x00c6, 0x20a9, 0x007f, 0x2009, 0x0000, + 0x0016, 0x080c, 0x4f6a, 0x1118, 0x6000, 0xd0ec, 0x1138, 0x001e, + 0x8108, 0x1f04, 0x1268, 0x00ce, 0x015e, 0x0028, 0x001e, 0x00ce, + 0x015e, 0x0804, 0x12d7, 0x0006, 0x0016, 0x2001, 0x0103, 0x2009, + 0xb68d, 0x210c, 0x2102, 0x001e, 0x000e, 0xa006, 0x2009, 0x0700, + 0x20a9, 0x0002, 0x20a1, 0xb6ce, 0x40a1, 0x7070, 0x8007, 0x7174, + 0x810f, 0x20a9, 0x0002, 0x40a1, 0x2009, 0x0000, 0x080c, 0x14f7, + 0x2001, 0x0000, 0x810f, 0x20a9, 0x0002, 0x40a1, 0xa006, 0x2009, + 0x0200, 0x20a9, 0x0002, 0x20a1, 0xb6de, 0x40a1, 0x7030, 0xc08c, + 0x7032, 0x7003, 0x0003, 0x709f, 0xffff, 0x080c, 0x157d, 0xa006, + 0x080c, 0x2789, 0x080c, 0x3efc, 0x00f6, 0x2079, 0x0100, 0x080c, + 0x5ab6, 0x0150, 0x080c, 0x5a90, 0x7828, 0x0118, 0xa084, 0xe1ff, + 0x0010, 0xa084, 0xffdf, 0x782a, 0x00fe, 0x2001, 0xb6e1, 0x2004, + 0xa086, 0x0005, 0x1120, 0x2011, 0x0000, 0x080c, 0x801f, 0x2011, + 0x0000, 0x080c, 0x8029, 0x080c, 0x7134, 0x080c, 0x71f1, 0x012e, + 0x0005, 0x0016, 0x0046, 0x00f6, 0x0126, 0x2091, 0x8000, 0x2079, + 0x0100, 0x2009, 0xb434, 0x2104, 0xa005, 0x1110, 0x080c, 0x28dd, + 0x2009, 0x00f7, 0x080c, 0x4b69, 0x7940, 0xa18c, 0x0010, 0x7942, + 0x7924, 0xd1b4, 0x0110, 0x7827, 0x0040, 0xd19c, 0x0110, 0x7827, + 0x0008, 0x0006, 0x0036, 0x0156, 0x7954, 0xd1ac, 0x1904, 0x1347, + 0x080c, 0x5aa2, 0x0158, 0x080c, 0x5ab6, 0x1128, 0x2001, 0xb69e, + 0x2003, 0x0000, 0x0070, 0x080c, 0x5a98, 0x0dc0, 0x2001, 0xb69e, + 0x2003, 0xaaaa, 0x2001, 0xb69f, 0x2003, 0x0001, 0x080c, 0x59c8, + 0x0058, 0x080c, 0x5a90, 0x0140, 0x2009, 0x00f8, 0x080c, 0x4b69, + 0x7843, 0x0090, 0x7843, 0x0010, 0x20a9, 0x09c4, 0x7820, 0xd09c, + 0x1138, 0x080c, 0x5a90, 0x0138, 0x7824, 0xd0ac, 0x1904, 0x13f1, + 0x1f04, 0x1326, 0x0070, 0x7824, 0x080c, 0x5aac, 0x0118, 0xd0ac, + 0x1904, 0x13f1, 0xa084, 0x1800, 0x0d98, 0x7003, 0x0001, 0x0804, + 0x13f1, 0x2001, 0x0001, 0x080c, 0x2789, 0x0804, 0x1400, 0x7850, + 0xa084, 0x0180, 0x7852, 0x782f, 0x0020, 0x20a9, 0x0046, 0x1d04, + 0x134f, 0x080c, 0x6a09, 0x1f04, 0x134f, 0x7850, 0xa084, 0x0180, + 0xa085, 0x0400, 0x7852, 0x782f, 0x0000, 0x080c, 0x5aa2, 0x0158, + 0x080c, 0x5ab6, 0x1128, 0x2001, 0xb69e, 0x2003, 0x0000, 0x0070, + 0x080c, 0x5a98, 0x0dc0, 0x2001, 0xb69e, 0x2003, 0xaaaa, 0x2001, + 0xb69f, 0x2003, 0x0001, 0x080c, 0x59c8, 0x0020, 0x2009, 0x00f8, + 0x080c, 0x4b69, 0x20a9, 0x000e, 0xe000, 0x1f04, 0x137c, 0x7850, + 0xa084, 0x0180, 0xa085, 0x1400, 0x7852, 0x080c, 0x5a90, 0x0120, + 0x7843, 0x0090, 0x7843, 0x0010, 0x2021, 0xe678, 0x2019, 0xea60, + 0x7820, 0xd09c, 0x1558, 0x080c, 0x5a90, 0x05d8, 0x7824, 0xd0ac, + 0x1904, 0x13f1, 0x080c, 0x5ab6, 0x1508, 0x0046, 0x2021, 0x0190, + 0x8421, 0x1df0, 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0x1178, 0x080c, 0x7055, 0x0036, 0x00d6, 0x6010, 0x2068, + 0x2019, 0x0004, 0x080c, 0xb01c, 0x00de, 0x003e, 0x080c, 0x7134, + 0x0005, 0xa186, 0x0014, 0x0d70, 0x080c, 0x8606, 0x0005, 0xb218, + 0xb216, 0xb216, 0xb216, 0xb216, 0xb216, 0xb218, 0x080c, 0x1511, + 0x080c, 0x7055, 0x6003, 0x000c, 0x080c, 0x7134, 0x0005, 0xa182, + 0x008c, 0x1220, 0xa182, 0x0085, 0x0208, 0x001a, 0x080c, 0x8606, + 0x0005, 0xb230, 0xb230, 0xb230, 0xb230, 0xb232, 0xb250, 0xb230, + 0x080c, 0x1511, 0x00d6, 0x2c68, 0x080c, 0x856a, 0x01a0, 0x6003, + 0x0001, 0x6007, 0x001e, 0x2009, 0xba8e, 0x210c, 0x6136, 0x2009, + 0xba8f, 0x210c, 0x613a, 0x600b, 0xffff, 0x6918, 0x611a, 0x601f, + 0x0004, 0x080c, 0x6c52, 0x2d60, 0x080c, 0x85c0, 0x00de, 0x0005, + 0x080c, 0x85c0, 0x0005, 0x00e6, 0x6018, 0x2070, 0x7000, 0xd0ec, + 0x00ee, 0x0005, 0x6010, 0xa08c, 0xf000, 0x0904, 0xb29e, 0xa080, + 0x0013, 0x200c, 0xd1ec, 0x05d0, 0x2001, 0xb472, 0x2004, 0xd0ec, + 0x05a8, 0x6003, 0x0002, 0x6020, 0xc0e5, 0x6022, 0xd1ac, 0x0180, + 0x00f6, 0x2c78, 0x080c, 0x52c2, 0x00fe, 0x0150, 0x2001, 0xb6b8, + 0x2004, 0x603e, 0x2009, 0xb472, 0x210c, 0xd1f4, 0x11e8, 0x0080, + 0x2009, 0xb472, 0x210c, 0xd1f4, 0x0128, 0x6020, 0xc0e4, 0x6022, + 0xa006, 0x00a0, 0x2001, 0xb6b8, 0x200c, 0x8103, 0xa100, 0x603e, + 0x6018, 0xa088, 0x002b, 0x2104, 0xa005, 0x0118, 0xa088, 0x0003, + 0x0cd0, 0x2c0a, 0x600f, 0x0000, 0xa085, 0x0001, 0x0005, 0x0016, + 0x00c6, 0x00e6, 0x6150, 0xa2f0, 0x002b, 0x2e04, 0x2060, 0x8cff, + 0x0180, 0x84ff, 0x1118, 0x6050, 0xa106, 0x1138, 0x600c, 0x2072, + 0x080c, 0x6ab4, 0x080c, 0x85c0, 0x0010, 0xacf0, 0x0003, 0x2e64, + 0x0c70, 0x00ee, 0x00ce, 0x001e, 0x0005, 0x00d6, 0x6018, 0xa0e8, + 0x002b, 0x2d04, 0xa005, 0x0140, 0xac06, 0x0120, 0x2d04, 0xa0e8, + 0x0003, 0x0cb8, 0x600c, 0x206a, 0x00de, 0x0005, 0x0026, 0x0036, + 0x0156, 0x2011, 0xb428, 0x2204, 0xa084, 0x00ff, 0x2019, 0xba8e, + 0x2334, 0xa636, 0x11d8, 0x8318, 0x2334, 0x2204, 0xa084, 0xff00, + 0xa636, 0x11a0, 0x2011, 0xba90, 0x6018, 0xa098, 0x000a, 0x20a9, + 0x0004, 0x080c, 0x907a, 0x1150, 0x2011, 0xba94, 0x6018, 0xa098, + 0x0006, 0x20a9, 0x0004, 0x080c, 0x907a, 0x1100, 0x015e, 0x003e, + 0x002e, 0x0005, 0x00e6, 0x2071, 0xb400, 0x080c, 0x4b80, 0x080c, + 0x2a7e, 0x00ee, 0x0005, 0x00e6, 0x6018, 0x2070, 0x7000, 0xd0fc, + 0x0108, 0x0011, 0x00ee, 0x0005, 0x6850, 0xc0e5, 0x6852, 0x0005, + 0x00e6, 0x00c6, 0x0076, 0x0066, 0x0056, 0x0046, 0x0026, 0x0016, + 0x0126, 0x2091, 0x8000, 0x2029, 0xb6e9, 0x252c, 0x2021, 0xb6ef, + 0x2424, 0x2061, 0xbc00, 0x2071, 0xb400, 0x7648, 0x7068, 0xa606, + 0x0578, 0x671c, 0xa786, 0x0001, 0x0118, 0xa786, 0x0008, 0x1500, + 0x2500, 0xac06, 0x01e8, 0x2400, 0xac06, 0x01d0, 0x080c, 0xb093, + 0x01b8, 0x080c, 0xb0a3, 0x11a0, 0x6000, 0xa086, 0x0004, 0x1120, + 0x0016, 0x080c, 0x1944, 0x001e, 0x080c, 0x9dd8, 0x1110, 0x080c, + 0x2c86, 0x080c, 0x9de9, 0x1110, 0x080c, 0x8bbc, 0x080c, 0x9dae, + 0xace0, 0x0018, 0x2001, 0xb417, 0x2004, 0xac02, 0x1208, 0x0858, + 0x012e, 0x001e, 0x002e, 0x004e, 0x005e, 0x006e, 0x007e, 0x00ce, + 0x00ee, 0x0005, 0x0126, 0x0006, 0x00e6, 0x0016, 0x2091, 0x8000, + 0x2071, 0xb440, 0xd5a4, 0x0118, 0x7034, 0x8000, 0x7036, 0xd5b4, + 0x0118, 0x7030, 0x8000, 0x7032, 0xd5ac, 0x0178, 0x2500, 0xa084, + 0x0007, 0xa08e, 0x0003, 0x0148, 0xa08e, 0x0004, 0x0130, 0xa08e, + 0x0005, 0x0118, 0x2071, 0xb44a, 0x04c9, 0x001e, 0x00ee, 0x000e, + 0x012e, 0x0005, 0x0126, 0x0006, 0x00e6, 0x0016, 0x2091, 0x8000, + 0x2071, 0xb440, 0xd5a4, 0x0118, 0x7034, 0x8000, 0x7036, 0xd5b4, + 0x0118, 0x7030, 0x8000, 0x7032, 0xd5ac, 0x0178, 0x2500, 0xa084, + 0x0007, 0xa08e, 0x0003, 0x0148, 0xa08e, 0x0004, 0x0130, 0xa08e, + 0x0005, 0x0118, 0x2071, 0xb44a, 0x0089, 0x001e, 0x00ee, 0x000e, + 0x012e, 0x0005, 0x0126, 0x0006, 0x00e6, 0x2091, 0x8000, 0x2071, + 0xb442, 0x0021, 0x00ee, 0x000e, 0x012e, 0x0005, 0x2e04, 0x8000, + 0x2072, 0x1220, 0x8e70, 0x2e04, 0x8000, 0x2072, 0x0005, 0x00e6, + 0x2071, 0xb440, 0x0c99, 0x00ee, 0x0005, 0x00e6, 0x2071, 0xb444, + 0x0c69, 0x00ee, 0x0005, 0x0126, 0x0006, 0x00e6, 0x2091, 0x8000, + 0x2071, 0xb440, 0x7044, 0x8000, 0x7046, 0x00ee, 0x000e, 0x012e, + 0x0005, 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, + 0x0080, 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, + 0x8000, 0x622c +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/firmware/asm_2300.h 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,6195 @@ +/* @(#)asm_2300.h 1.6 */ +/* + * Copyright (C) 2001 Qlogic, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted provided + * that the following conditions are met: + * 1. Redistribution of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistribution in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/************************************************************************ + * * + * --- ISP2300 Initiator/Target Firmware --- * + * with Fabric (Public Loop), Point-point, and * + * expanded LUN addressing for FCTAPE * + * * + ************************************************************************/ +/* + * Firmware Version 3.01.20 (15:30 Dec 19, 2002) + */ +static const u_int16_t isp_2300_risc_code[] = { + 0x0470, 0x0000, 0x0000, 0xc060, 0x0000, 0x0003, 0x0001, 0x0014, + 0x0017, 0x2043, 0x4f50, 0x5952, 0x4947, 0x4854, 0x2032, 0x3030, + 0x3120, 0x514c, 0x4f47, 0x4943, 0x2043, 0x4f52, 0x504f, 0x5241, + 0x5449, 0x4f4e, 0x2049, 0x5350, 0x3233, 0x3030, 0x2046, 0x6972, + 0x6d77, 0x6172, 0x6520, 0x2056, 0x6572, 0x7369, 0x6f6e, 0x2030, + 0x332e, 0x3031, 0x2e32, 0x3020, 0x2020, 0x2020, 0x2400, 0x20a9, + 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2200, 0x20a9, 0x000f, + 0x2001, 0x0000, 0x400f, 0x2091, 0x2400, 0x20a9, 0x000f, 0x2001, + 0x0000, 0x400f, 0x2091, 0x2600, 0x20a9, 0x000f, 0x2001, 0x0000, + 0x400f, 0x2091, 0x2800, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, + 0x2091, 0x2a00, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, + 0x2c00, 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2e00, + 0x20a9, 0x000f, 0x2001, 0x0000, 0x400f, 0x2091, 0x2000, 0x2001, + 0x0000, 0x20c1, 0x0004, 0x2001, 0x017f, 0x2003, 0x0000, 0x20c9, + 0x14ff, 0x2059, 0x0000, 0x2b78, 0x7883, 0x0004, 0x2089, 0x240d, + 0x2051, 0x1100, 0x2a70, 0x20e1, 0x0001, 0x20e9, 0x0001, 0x2029, + 0x45c0, 0x2031, 0xffff, 0x2039, 0x45a9, 0x2021, 0x0200, 0x20e9, + 0x0001, 0x20a1, 0x1000, 0x900e, 0x20a9, 0x05c0, 0x4104, 0x7566, + 0x766a, 0x7762, 0x746e, 0x7472, 0x00e6, 0x2071, 0x13a1, 0x2472, + 0x00ee, 0x20a1, 0x15c0, 0x7168, 0x810d, 0x810d, 0x810d, 0x810d, + 0x918c, 0x000f, 0x2001, 0x0001, 0x9112, 0x900e, 0x21a8, 0x4104, + 0x8211, 0x1de0, 0x7168, 0x3400, 0x8001, 0x9102, 0x0120, 0x0218, + 0x20a8, 0x900e, 0x4104, 0x2009, 0x1100, 0x810d, 0x810d, 0x810d, + 0x810d, 0x810d, 0x918c, 0x001f, 0x2001, 0x0001, 0x9112, 0x20e9, + 0x0001, 0x20a1, 0x0800, 0x900e, 0x20a9, 0x0800, 0x4104, 0x8211, + 0x1dd8, 0x2009, 0x1100, 0x3400, 0x9102, 0x0120, 0x0218, 0x20a8, + 0x900e, 0x4104, 0x080c, 0x0f11, 0x080c, 0x10cf, 0x080c, 0x15fe, + 0x080c, 0x0d19, 0x080c, 0x50f4, 0x080c, 0x8e7a, 0x080c, 0x0e85, + 0x080c, 0x2a8c, 0x080c, 0x65b0, 0x080c, 0x58d0, 0x080c, 0x7133, + 0x080c, 0x1c09, 0x080c, 0x7420, 0x080c, 0x6bb9, 0x080c, 0x19df, + 0x080c, 0x1b7a, 0x080c, 0x1bfe, 0x2091, 0x3009, 0x7883, 0x0000, + 0x1004, 0x0910, 0x7880, 0x9086, 0x0002, 0x1190, 0x7883, 0x4000, + 0x7837, 0x4000, 0x7833, 0x0010, 0x0e04, 0x0904, 0x2091, 0x5000, + 0x2091, 0x4080, 0x2001, 0x0089, 0x2004, 0xd084, 0x190c, 0x0fcd, + 0x2a70, 0x7003, 0x0000, 0x2a70, 0x7000, 0x908e, 0x0003, 0x1168, + 0x080c, 0x3fa0, 0x080c, 0x2aa2, 0x080c, 0x6610, 0x080c, 0x5dab, + 0x080c, 0x715a, 0x080c, 0x23a5, 0x0c70, 0x000b, 0x0c88, 0x0931, + 0x0932, 0x0a98, 0x092f, 0x0b68, 0x0d18, 0x0d18, 0x0d18, 0x080c, + 0x0d7e, 0x0005, 0x0126, 0x00f6, 0x2091, 0x8000, 0x7000, 0x9086, + 0x0001, 0x1904, 0x0a76, 0x7034, 0xd0b4, 0x1130, 0x0026, 0x2011, + 0x0080, 0x080c, 0x0e3a, 0x002e, 0x080c, 0x62e4, 0x0150, 0x080c, + 0x630a, 0x1580, 0x2079, 0x0100, 0x7828, 0x9085, 0x1800, 0x782a, + 0x0448, 0x080c, 0x621a, 0x7000, 0x9086, 0x0001, 0x1904, 0x0a76, + 0x7090, 0x9086, 0x0028, 0x1904, 0x0a76, 0x2001, 0x0161, 0x2003, + 0x0001, 0x2079, 0x0100, 0x7827, 0xffff, 0x7a28, 0x9295, 0x1e2f, + 0x7a2a, 0x2011, 0x61aa, 0x080c, 0x71fa, 0x2011, 0x619d, 0x080c, + 0x72bf, 0x2011, 0x4f57, 0x080c, 0x71fa, 0x2011, 0x8030, 0x901e, + 0x738e, 0x00d8, 0x080c, 0x483b, 0x2079, 0x0100, 0x7844, 0x9005, + 0x1904, 0x0a76, 0x2011, 0x4f57, 0x080c, 0x71fa, 0x2001, 0x0265, + 0x2001, 0x0205, 0x2003, 0x0000, 0x780f, 0x006b, 0x7840, 0x9084, + 0xfffb, 0x7842, 0x2011, 0x8010, 0x73d4, 0x080c, 0x2261, 0x080c, + 0x3f23, 0x7240, 0xc284, 0x7242, 0x2001, 0x110c, 0x200c, 0xc1ac, + 0xc1cc, 0x2102, 0x080c, 0x877f, 0x2011, 0x0004, 0x080c, 0xa948, + 0x080c, 0x57d9, 0x080c, 0x62e4, 0x1120, 0x080c, 0x22a5, 0x02f0, + 0x0410, 0x080c, 0x50b1, 0x0140, 0x708f, 0x0001, 0x70cf, 0x0000, + 0x080c, 0x49f2, 0x0804, 0x0a76, 0x2001, 0x1153, 0x2004, 0xd094, + 0x0190, 0x2011, 0x110c, 0x2204, 0xc0cd, 0x2012, 0x2001, 0x1172, + 0x2004, 0xd0d4, 0x1118, 0x080c, 0x22a5, 0x1278, 0x2011, 0x110c, + 0x2204, 0xc0bc, 0x00b0, 0x2001, 0x1172, 0x2004, 0xd0d4, 0x1db0, + 0x2011, 0x110c, 0x2204, 0xc0bd, 0x0060, 0x2011, 0x110c, 0x2204, + 0xc0bd, 0x2012, 0x080c, 0x58c6, 0x1128, 0xd0a4, 0x0118, 0x2204, + 0xc0fd, 0x2012, 0x080c, 0x588e, 0x0120, 0x7a0c, 0xc2b4, 0x7a0e, + 0x00a8, 0x7077, 0x0000, 0x080c, 0x62e4, 0x1130, 0x70a8, 0x9005, + 0x1168, 0x080c, 0xad47, 0x0050, 0x080c, 0xad47, 0x70d8, 0xd09c, + 0x1128, 0x70a8, 0x9005, 0x0110, 0x080c, 0x5092, 0x70e3, 0x0000, + 0x70df, 0x0000, 0x709f, 0x0000, 0x72d8, 0x080c, 0x62e4, 0x1170, + 0x9016, 0x0016, 0x080c, 0x205d, 0x2019, 0x1298, 0x211a, 0x001e, + 0x7057, 0xffff, 0x705b, 0x00ef, 0x707b, 0x0000, 0x2079, 0x1152, + 0x7804, 0xd0ac, 0x0108, 0xc295, 0x72da, 0x080c, 0x62e4, 0x0118, + 0x9296, 0x0004, 0x0548, 0x2011, 0x0001, 0x080c, 0xa948, 0x70a3, + 0x0000, 0x70a7, 0xffff, 0x7003, 0x0002, 0x2079, 0x0100, 0x7827, + 0x0003, 0x7828, 0x9085, 0x0003, 0x782a, 0x00fe, 0x080c, 0x2679, + 0x2011, 0x0005, 0x080c, 0x88e2, 0x080c, 0x7aa4, 0x080c, 0x62e4, + 0x0148, 0x00c6, 0x2061, 0x0100, 0x0016, 0x080c, 0x205d, 0x61e2, + 0x001e, 0x00ce, 0x012e, 0x0420, 0x70a3, 0x0000, 0x70a7, 0xffff, + 0x7003, 0x0002, 0x00f6, 0x2079, 0x0100, 0x7827, 0x0003, 0x7828, + 0x9085, 0x0003, 0x782a, 0x00fe, 0x2011, 0x0005, 0x080c, 0x88e2, + 0x080c, 0x7aa4, 0x080c, 0x62e4, 0x0148, 0x00c6, 0x2061, 0x0100, + 0x0016, 0x080c, 0x205d, 0x61e2, 0x001e, 0x00ce, 0x00fe, 0x012e, + 0x0005, 0x00c6, 0x080c, 0x62e4, 0x1118, 0x20a9, 0x0100, 0x0010, + 0x20a9, 0x0082, 0x080c, 0x62e4, 0x1110, 0x900e, 0x0010, 0x2009, + 0x007e, 0x080c, 0x2955, 0x8108, 0x1f04, 0x0a89, 0x00ce, 0x7077, + 0x0000, 0x7078, 0x9084, 0x00ff, 0x707a, 0x70ab, 0x0000, 0x0005, + 0x0126, 0x2091, 0x8000, 0x7000, 0x9086, 0x0002, 0x1904, 0x0b66, + 0x70a4, 0x9086, 0xffff, 0x0130, 0x080c, 0x2679, 0x080c, 0x7aa4, + 0x0804, 0x0b66, 0x70d8, 0xd0ac, 0x1110, 0xd09c, 0x0518, 0xd084, + 0x0508, 0x0006, 0x2001, 0x0103, 0x2003, 0x002b, 0x000e, 0xd08c, + 0x01c8, 0x70dc, 0x9086, 0xffff, 0x0188, 0x080c, 0x27da, 0x080c, + 0x7aa4, 0x70d8, 0xd094, 0x1904, 0x0b66, 0x2011, 0x0001, 0x901e, + 0x080c, 0x2811, 0x080c, 0x7aa4, 0x0804, 0x0b66, 0x70e0, 0x9005, + 0x1904, 0x0b66, 0x70a0, 0x9005, 0x1904, 0x0b66, 0x70d8, 0xd0a4, + 0x0118, 0xd0b4, 0x0904, 0x0b66, 0x080c, 0x588e, 0x1904, 0x0b66, + 0x080c, 0x58c6, 0x01c0, 0x0156, 0x00c6, 0x20a9, 0x007f, 0x900e, + 0x0016, 0x080c, 0x5608, 0x1118, 0x6000, 0xd0ec, 0x1138, 0x001e, + 0x8108, 0x1f04, 0x0ae8, 0x00ce, 0x015e, 0x0028, 0x001e, 0x00ce, + 0x015e, 0x0804, 0x0b66, 0x0006, 0x2001, 0x0103, 0x2003, 0x006b, + 0x000e, 0x20e9, 0x0001, 0x71b0, 0x81ff, 0x11b0, 0x9006, 0x2009, + 0x0200, 0x20a9, 0x0002, 0x20a1, 0x1302, 0x4001, 0x2009, 0x0700, + 0x20a9, 0x0002, 0x20a1, 0x12f2, 0x4001, 0x7074, 0x8007, 0x7178, + 0x810f, 0x20a9, 0x0002, 0x4001, 0x20a1, 0x12f6, 0x900e, 0x080c, + 0x0d65, 0x9006, 0x810f, 0x20a9, 0x0002, 0x4001, 0x7030, 0xc08c, + 0x7032, 0x7003, 0x0003, 0x70a7, 0xffff, 0x7034, 0xd0b4, 0x1130, + 0x0026, 0x2011, 0x0040, 0x080c, 0x0e3a, 0x002e, 0x9006, 0x080c, + 0x1f11, 0x0036, 0x0046, 0x2019, 0xffff, 0x2021, 0x0006, 0x080c, + 0x4026, 0x004e, 0x003e, 0x00f6, 0x2079, 0x0100, 0x080c, 0x630a, + 0x0150, 0x080c, 0x62e4, 0x7828, 0x0118, 0x9084, 0xe1ff, 0x0010, + 0x9084, 0xffdf, 0x782a, 0x00fe, 0x2001, 0x1305, 0x2004, 0x9086, + 0x0005, 0x1120, 0x2011, 0x0000, 0x080c, 0x88e2, 0x2011, 0x0000, + 0x080c, 0x88ec, 0x080c, 0x7aa4, 0x080c, 0x7b72, 0x012e, 0x0005, + 0x0016, 0x0046, 0x00f6, 0x0126, 0x2091, 0x8000, 0x2079, 0x0100, + 0x7904, 0x918c, 0xfffd, 0x7906, 0x2009, 0x00f7, 0x080c, 0x507b, + 0x7940, 0x918c, 0x0010, 0x7942, 0x7924, 0xd1b4, 0x0110, 0x7827, + 0x0040, 0xd19c, 0x0110, 0x7827, 0x0008, 0x0006, 0x0036, 0x0156, + 0x7954, 0xd1ac, 0x1904, 0x0bf6, 0x080c, 0x2328, 0x1148, 0x2001, + 0x0001, 0x080c, 0x2290, 0x2001, 0x0001, 0x080c, 0x2273, 0x00b8, + 0x080c, 0x2330, 0x1138, 0x9006, 0x080c, 0x2290, 0x9006, 0x080c, + 0x2273, 0x0068, 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0x9082, 0x0085, 0x0072, 0x9186, + 0x0027, 0x0120, 0x9186, 0x0014, 0x190c, 0x0d7e, 0x080c, 0x79ab, + 0x080c, 0x8f09, 0x080c, 0x7aa4, 0x0005, 0xa3f2, 0xa3f4, 0xa3f4, + 0xa3f2, 0xa3f2, 0xa3f2, 0xa3f2, 0xa3f2, 0xa3f2, 0xa3f2, 0xa3f2, + 0xa3f2, 0xa3f2, 0x080c, 0x0d7e, 0x080c, 0x79ab, 0x080c, 0x8f09, + 0x080c, 0x7aa4, 0x0005, 0x9186, 0x0013, 0x1128, 0x6004, 0x9082, + 0x0085, 0x2008, 0x04a8, 0x9186, 0x0027, 0x11e8, 0x080c, 0x79ab, + 0x080c, 0x2862, 0x00d6, 0x6014, 0x2068, 0x080c, 0xa942, 0x0150, + 0x6867, 0x0103, 0x6877, 0x0000, 0x687b, 0x0029, 0x080c, 0x5b76, + 0x080c, 0xab11, 0x00de, 0x080c, 0x8ed9, 0x080c, 0x7aa4, 0x0005, + 0x080c, 0x8f6e, 0x0ce0, 0x9186, 0x0014, 0x1dd0, 0x080c, 0x79ab, + 0x00d6, 0x6014, 0x2068, 0x080c, 0xa942, 0x0d60, 0x6867, 0x0103, + 0x6877, 0x0000, 0x687b, 0x0006, 0x6880, 0xc0ec, 0x6882, 0x08f0, + 0x0002, 0xa448, 0xa446, 0xa446, 0xa446, 0xa446, 0xa446, 0xa460, + 0xa446, 0xa446, 0xa446, 0xa446, 0xa446, 0xa446, 0x080c, 0x0d7e, + 0x080c, 0x79ab, 0x6034, 0x908c, 0xff00, 0x810f, 0x9186, 0x0039, + 0x0118, 0x9186, 0x0035, 0x1118, 0x2001, 0x12c0, 0x0010, 0x2001, + 0x12c1, 0x2004, 0x601a, 0x6003, 0x000c, 0x080c, 0x7aa4, 0x0005, + 0x080c, 0x79ab, 0x6034, 0x908c, 0xff00, 0x810f, 0x9186, 0x0039, + 0x0118, 0x9186, 0x0035, 0x1118, 0x2001, 0x12c0, 0x0010, 0x2001, + 0x12c1, 0x2004, 0x601a, 0x6003, 0x000e, 0x080c, 0x7aa4, 0x0005, + 0x9182, 0x0092, 0x1220, 0x9182, 0x0085, 0x0208, 0x001a, 0x080c, + 0x8f6e, 0x0005, 0xa48f, 0xa48f, 0xa48f, 0xa48f, 0xa491, 0xa4ea, + 0xa48f, 0xa48f, 0xa48f, 0xa48f, 0xa48f, 0xa48f, 0xa48f, 0x080c, + 0x0d7e, 0x00d6, 0x6010, 0x2004, 0xd0bc, 0x0168, 0x6034, 0x908c, + 0xff00, 0x810f, 0x9186, 0x0039, 0x0118, 0x9186, 0x0035, 0x1118, + 0x00de, 0x0804, 0xa4fb, 0x080c, 0xa942, 0x1118, 0x080c, 0xab11, + 0x00f0, 0x6014, 0x2068, 0x687c, 0xd0e4, 0x1110, 0x080c, 0xab11, + 0x6867, 0x0103, 0x6880, 0xd0b4, 0x0128, 0x687b, 0x0006, 0xc0ec, + 0x6882, 0x0048, 0xd0bc, 0x0118, 0x687b, 0x0002, 0x0020, 0x687b, + 0x0005, 0x080c, 0xac07, 0x6877, 0x0000, 0x080c, 0x5b76, 0x2c68, + 0x080c, 0x8e83, 0x01d0, 0x6003, 0x0001, 0x6007, 0x001e, 0x600b, + 0xffff, 0x2009, 0x026e, 0x210c, 0x613a, 0x2009, 0x026f, 0x210c, + 0x613e, 0x6910, 0x6112, 0x080c, 0xad70, 0x6954, 0x6156, 0x6023, + 0x0001, 0x080c, 0x756e, 0x080c, 0x7aa4, 0x2d60, 0x080c, 0x8ed9, + 0x00de, 0x0005, 0x6010, 0x2004, 0xd0bc, 0x0598, 0x6034, 0x908c, + 0xff00, 0x810f, 0x9186, 0x0035, 0x0130, 0x9186, 0x001e, 0x0118, + 0x9186, 0x0039, 0x1530, 0x00d6, 0x2c68, 0x080c, 0xaf4e, 0x1904, + 0xa540, 0x080c, 0x8e83, 0x01d8, 0x6106, 0x6003, 0x0001, 0x6023, + 0x0001, 0x6910, 0x6112, 0x692c, 0x612e, 0x6930, 0x6132, 0x6934, + 0x918c, 0x00ff, 0x6136, 0x6938, 0x613a, 0x693c, 0x613e, 0x6954, + 0x6156, 0x080c, 0xad70, 0x080c, 0x756e, 0x080c, 0x7aa4, 0x2d60, + 0x00f8, 0x00d6, 0x6014, 0x2068, 0x080c, 0xa942, 0x01c8, 0x6867, + 0x0103, 0x6880, 0xd0b4, 0x0128, 0xc0ec, 0x6882, 0x687b, 0x0006, + 0x0048, 0xd0bc, 0x0118, 0x687b, 0x0002, 0x0020, 0x687b, 0x0005, + 0x080c, 0xac07, 0x6877, 0x0000, 0x080c, 0x5b76, 0x080c, 0xab11, + 0x00de, 0x080c, 0x8ed9, 0x0005, 0x0016, 0x00d6, 0x6014, 0x2068, + 0x080c, 0xa942, 0x0140, 0x6867, 0x0103, 0x687b, 0x0028, 0x6877, + 0x0000, 0x080c, 0x5b76, 0x00de, 0x001e, 0x9186, 0x0013, 0x0148, + 0x9186, 0x0014, 0x0130, 0x9186, 0x0027, 0x0118, 0x080c, 0x8f6e, + 0x0030, 0x080c, 0x79ab, 0x080c, 0x8f09, 0x080c, 0x7aa4, 0x0005, + 0x0056, 0x0066, 0x00d6, 0x00f6, 0x2029, 0x0001, 0x9182, 0x0101, + 0x1208, 0x0010, 0x2009, 0x0100, 0x2130, 0x8304, 0x9098, 0x0018, + 0x2009, 0x0020, 0x9f90, 0x0029, 0x080c, 0xa5c9, 0x96b2, 0x0020, + 0x7804, 0x906d, 0x0110, 0x080c, 0x0edf, 0x080c, 0x0eb6, 0x0520, + 0x8528, 0x6867, 0x0110, 0x686b, 0x0000, 0x2d20, 0x7c06, 0x968a, + 0x003d, 0x1228, 0x2608, 0x9d90, 0x001b, 0x0499, 0x00a8, 0x96b2, + 0x003c, 0x2009, 0x003c, 0x2d78, 0x9d90, 0x001b, 0x0451, 0x0c28, + 0x2079, 0x0200, 0x7817, 0x0000, 0x00fe, 0x852f, 0x95ad, 0x0003, + 0x7d66, 0x95ac, 0x0000, 0x0048, 0x2079, 0x0200, 0x7817, 0x0000, + 0x00fe, 0x852f, 0x95ad, 0x0003, 0x7d66, 0x00de, 0x006e, 0x005e, + 0x0005, 0x00f6, 0x8dff, 0x0158, 0x6804, 0x907d, 0x0130, 0x6807, + 0x0000, 0x080c, 0x5b76, 0x2f68, 0x0cb8, 0x080c, 0x5b76, 0x00fe, + 0x0005, 0x00f6, 0x0156, 0x2079, 0x0200, 0x9184, 0x0001, 0x0108, + 0x8108, 0x810c, 0x21a8, 0x2300, 0x9e00, 0x2004, 0x8007, 0x2012, + 0x8318, 0x9386, 0x0020, 0x1120, 0x2018, 0x7814, 0x8000, 0x7816, + 0x8210, 0x1f04, 0xa5d3, 0x015e, 0x00fe, 0x0005, 0x0066, 0x0126, + 0x2091, 0x8000, 0x2031, 0x0001, 0x6020, 0x9084, 0x000f, 0x0083, + 0x012e, 0x006e, 0x0005, 0x0126, 0x2091, 0x8000, 0x0066, 0x2031, + 0x0000, 0x6020, 0x9084, 0x000f, 0x001b, 0x006e, 0x012e, 0x0005, + 0xa621, 0xa621, 0xa61c, 0xa643, 0xa60f, 0xa61c, 0xa643, 0xa61c, + 0xa60f, 0xa60f, 0xa61c, 0xa61c, 0xa61c, 0xa60f, 0xa60f, 0x080c, + 0x0d7e, 0x0036, 0x2019, 0x0010, 0x080c, 0xbd23, 0x6023, 0x0006, + 0x6003, 0x0007, 0x003e, 0x0005, 0x9006, 0x0005, 0x9085, 0x0001, + 0x0005, 0x00d6, 0x86ff, 0x11d8, 0x6014, 0x2068, 0x080c, 0xa942, + 0x01c0, 0x6864, 0x9086, 0x0139, 0x1128, 0x687b, 0x0005, 0x6883, + 0x0000, 0x0028, 0x900e, 0x2001, 0x0005, 0x080c, 0x5d95, 0x080c, + 0xac07, 0x080c, 0x5b76, 0x080c, 0x8f09, 0x9085, 0x0001, 0x00de, + 0x0005, 0x9006, 0x0ce0, 0x6000, 0x908a, 0x0016, 0x1a0c, 0x0d7e, + 0x000b, 0x0005, 0xa65a, 0xa67b, 0xa65c, 0xa69a, 0xa678, 0xa65a, + 0xa61c, 0xa621, 0xa621, 0xa61c, 0xa61c, 0xa61c, 0xa61c, 0xa61c, + 0xa61c, 0xa61c, 0x080c, 0x0d7e, 0x86ff, 0x11b8, 0x6020, 0x9086, + 0x0006, 0x0198, 0x00d6, 0x6014, 0x2068, 0x080c, 0xa942, 0x0110, + 0x080c, 0xac07, 0x00de, 0x6007, 0x0085, 0x6003, 0x000b, 0x6023, + 0x0002, 0x080c, 0x756e, 0x080c, 0x7aa4, 0x9085, 0x0001, 0x0005, + 0x080c, 0x1509, 0x0c08, 0x00e6, 0x2071, 0x1304, 0x7024, 0x9c06, + 0x1110, 0x080c, 0x87a2, 0x6020, 0x9084, 0x000f, 0x9086, 0x0006, + 0x1150, 0x0086, 0x0096, 0x2049, 0x0001, 0x2c40, 0x080c, 0x8968, + 0x009e, 0x008e, 0x0010, 0x080c, 0x86b8, 0x00ee, 0x1928, 0x080c, + 0xa61c, 0x0005, 0x0036, 0x00e6, 0x2071, 0x1304, 0x703c, 0x9c06, + 0x1138, 0x901e, 0x080c, 0x8847, 0x00ee, 0x003e, 0x0804, 0xa65c, + 0x080c, 0x8a8d, 0x00ee, 0x003e, 0x1904, 0xa65c, 0x080c, 0xa61c, + 0x0005, 0x00c6, 0x6020, 0x9084, 0x000f, 0x0013, 0x00ce, 0x0005, + 0xa6ce, 0xa759, 0xa8a3, 0xa6d9, 0x8f09, 0xa6ce, 0xbd15, 0x8ed9, + 0xa759, 0xa6c7, 0xa90e, 0xa6c7, 0xa6c7, 0xa6c7, 0xa6c7, 0x080c, + 0x0d7e, 0x080c, 0xab2e, 0x1110, 0x080c, 0x97dc, 0x0005, 0x080c, + 0x79ab, 0x080c, 0x7aa4, 0x080c, 0x8ed9, 0x0005, 0x601b, 0x0001, + 0x0005, 0x080c, 0xa942, 0x0120, 0x6014, 0x9080, 0x0025, 0x2c02, + 0x6000, 0x908a, 0x0016, 0x1a0c, 0x0d7e, 0x000b, 0x0005, 0xa6f7, + 0xa6f9, 0xa719, 0xa72b, 0xa738, 0xa6f7, 0xa6ce, 0xa6ce, 0xa6ce, + 0xa72b, 0xa72b, 0xa6f7, 0xa6f7, 0xa6f7, 0xa6f7, 0xa735, 0x080c, + 0x0d7e, 0x00e6, 0x6014, 0x2070, 0x7080, 0xc0b5, 0x7082, 0x2071, + 0x1304, 0x7024, 0x9c06, 0x0190, 0x080c, 0x86b8, 0x6007, 0x0085, + 0x6003, 0x000b, 0x6023, 0x0002, 0x2001, 0x12c1, 0x2004, 0x601a, + 0x080c, 0x756e, 0x080c, 0x7aa4, 0x00ee, 0x0005, 0x601b, 0x0001, + 0x0cd8, 0x00d6, 0x6014, 0x2068, 0x6880, 0xc0b5, 0x6882, 0x00de, + 0x6007, 0x0085, 0x6003, 0x000b, 0x6023, 0x0002, 0x080c, 0x756e, + 0x080c, 0x7aa4, 0x0005, 0x00d6, 0x601b, 0x0001, 0x6014, 0x2068, + 0x6880, 0xc0b5, 0x6882, 0x00de, 0x0005, 0x080c, 0x8ed9, 0x0005, + 0x6014, 0x9005, 0x01d8, 0x9088, 0x001f, 0x210c, 0xd1e4, 0x01b0, + 0x9080, 0x0021, 0x2004, 0x8003, 0x800b, 0x810b, 0x9108, 0x611a, + 0x2001, 0x0037, 0x2c08, 0x080c, 0x130c, 0x6000, 0x9086, 0x0004, + 0x1120, 0x2009, 0x0048, 0x080c, 0x8f53, 0x0005, 0x080c, 0x1509, + 0x0800, 0x6000, 0x908a, 0x0016, 0x1a0c, 0x0d7e, 0x000b, 0x0005, + 0xa770, 0xa6d6, 0xa772, 0xa770, 0xa772, 0xa772, 0xa6cf, 0xa770, + 0xa6c9, 0xa6c9, 0xa770, 0xa770, 0xa770, 0xa770, 0xa770, 0xa770, + 0x080c, 0x0d7e, 0x6010, 0x00d6, 0x2068, 0x6804, 0x9084, 0x00ff, + 0x00de, 0x908a, 0x000c, 0x1a0c, 0x0d7e, 0x000b, 0x0005, 0xa78b, + 0xa849, 0xa78d, 0xa7cb, 0xa78d, 0xa7cb, 0xa78d, 0xa79b, 0xa78b, + 0xa7cb, 0xa78b, 0xa7b7, 0x080c, 0x0d7e, 0x6004, 0x908e, 0x0016, + 0x05a8, 0x908e, 0x0004, 0x0590, 0x908e, 0x0002, 0x0578, 0x908e, + 0x0052, 0x0904, 0xa845, 0x6004, 0x080c, 0xab2e, 0x0904, 0xa862, + 0x908e, 0x0021, 0x0904, 0xa866, 0x908e, 0x0022, 0x0904, 0xa862, + 0x908e, 0x003d, 0x0904, 0xa866, 0x908e, 0x0039, 0x0904, 0xa86a, + 0x908e, 0x0035, 0x0904, 0xa86a, 0x908e, 0x001e, 0x0188, 0x908e, + 0x0001, 0x1150, 0x6010, 0x00d6, 0x2068, 0x6804, 0x9084, 0x00ff, + 0x00de, 0x9086, 0x0006, 0x0110, 0x080c, 0x2862, 0x080c, 0x97dc, + 0x080c, 0x8f09, 0x0005, 0x00c6, 0x00d6, 0x6104, 0x9186, 0x0016, + 0x0904, 0xa836, 0x9186, 0x0002, 0x15b8, 0x2001, 0x1136, 0x2004, + 0xd08c, 0x1178, 0x080c, 0x62e4, 0x1160, 0x2001, 0x12a8, 0x2003, + 0x0001, 0x2001, 0x1100, 0x2003, 0x0001, 0x080c, 0x621a, 0x0804, + 0xa88c, 0x6010, 0x2068, 0x2001, 0x1136, 0x2004, 0xd0ac, 0x1904, + 0xa88c, 0x68a0, 0xd0bc, 0x1904, 0xa88c, 0x6840, 0x9084, 0x00ff, + 0x9005, 0x0190, 0x8001, 0x6842, 0x6017, 0x0000, 0x6023, 0x0007, + 0x601b, 0x0398, 0x6043, 0x0000, 0x080c, 0x8e83, 0x0128, 0x2d00, + 0x6012, 0x6023, 0x0001, 0x0450, 0x00de, 0x00ce, 0x6004, 0x908e, + 0x0002, 0x11a8, 0x6010, 0x9080, 0x0028, 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0x0008, 0x0007, 0x0000, 0x0191, 0x0004, 0x1810, 0x0000, 0x0191, + 0x0004, 0x01d9, 0x000b, 0x0188, 0x000c, 0x8010, 0x0008, 0x001b, + 0x0008, 0x0191, 0x0004, 0x1810, 0x0000, 0x0191, 0x0004, 0x8074, + 0x0000, 0xf080, 0x0000, 0x0d30, 0x0000, 0x0007, 0x0003, 0x8010, + 0x0008, 0x0009, 0x0008, 0x01cf, 0x0003, 0x8010, 0x0008, 0x0005, + 0x0008, 0x01cf, 0x0003, 0x808c, 0x0008, 0x0001, 0x0000, 0x8010, + 0x0008, 0x0004, 0x0000, 0x4143, 0x000a, 0x0853, 0x0003, 0x3a44, + 0x0002, 0x0c07, 0x0003, 0x0d2a, 0x0008, 0x01cf, 0x0003, 0x8010, + 0x0008, 0x0003, 0x0008, 0x01d1, 0x0003, 0x8010, 0x0008, 0x000b, + 0x0000, 0x01d1, 0x0003, 0x8010, 0x0008, 0x0002, 0x0000, 0x01d1, + 0x0003, 0x3a47, 0x0002, 0x0cd7, 0x000b, 0x8010, 0x0008, 0x0006, + 0x0008, 0x01d1, 0x0003, 0x8074, 0x0000, 0xf000, 0x0008, 0x0191, + 0x0004, 0x0194, 0x0004, 0x3a40, 0x000a, 0x0807, 0x000b, 0x8010, + 0x0008, 0x000c, 0x0008, 0x0191, 0x0004, 0x0007, 0x0003, 0x8074, + 0x0000, 0xf080, 0x0000, 0x0d30, 0x0000, 0x2e4d, 0x0002, 0x2e4d, + 0x0002, 0x09e2, 0x000b, 0x8054, 0x0008, 0x0019, 0x0000, 0x0007, + 0x0003, 0x8054, 0x0008, 0x0009, 0x0008, 0x0007, 0x0003, 0x3a44, + 0x0002, 0x0c07, 0x0003, 0x01c4, 0x000b, 0xde59, 0xf666, 0x0001, + 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 0x0100, + 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, 0xfe91 +}; --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/isp_linux.c 2003-06-27 15:56:37.000000000 -0700 @@ -0,0 +1,3162 @@ +/* + * Qlogic ISP Host Adapter Common Bus Linux routies + *--------------------------------------- + * + * Copyright (c) 1998, 1999, 2000, 2001 by Matthew Jacob + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification, immediately at the beginning of the file. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * the GNU Public License ("GPL"). + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Matthew Jacob + * Feral Software + * PMB #825 + * 5214-F Diamond Hts Blvd + * San Francisco, CA, 94131 + * mjacob@feral.com + * + *-------- + * Bug fixes from Janice McLaughlin (janus@somemore.com) + * gratefully acknowledged. + * + * + *---- + * proc safe pretty print code courtesy of Gerard Roudier (groudier@free.fr) + * + */ + +#define ISP_MODULE 1 +#include "isp_linux.h" +#include "linux/smp_lock.h" + + +extern void scsi_add_timer(Scsi_Cmnd *, int, void ((*)(Scsi_Cmnd *))); +extern int scsi_delete_timer(Scsi_Cmnd *); + +static int isp_task_thread(void *); +struct ispsoftc *isplist = NULL; +int isp_debug = 0; +int isp_throttle = 0; +int isp_cmd_per_lun = 0; +int isp_unit_seed = 0; +int isp_disable = 0; +int isp_nofwreload = 0; +int isp_nonvram = 0; +int isp_maxluns = 8; +int isp_fcduplex = 0; +int isp_nport_only = 0; +int isp_loop_only = 0; +int isp_deadloop_time = 30; /* how long to wait before assume loop dead */ +int isp_xtime = 0; +int isp_default_frame_size; +int isp_default_exec_throttle; +static char *isp_roles; +static char *isp_wwpns; +static char *isp_wwnns; + +#ifdef LINUX_ISP_TARGET_MODE +#ifndef ISP_PARENT_TARGET +#define ISP_PARENT_TARGET scsi_target_handler +#endif +extern void ISP_PARENT_TARGET (qact_e, void *); +static void isp_taction(qact_e, void *); +static INLINE int nolunsenabled(struct ispsoftc *, int); +static void isp_target_start_ctio(struct ispsoftc *, tmd_cmd_t *); +static int isp_handle_platform_atio(struct ispsoftc *, at_entry_t *); +static int isp_handle_platform_atio2(struct ispsoftc *, at2_entry_t *); +static int isp_handle_platform_ctio(struct ispsoftc *, void *); +static void isp_target_putback_atio(struct ispsoftc *, tmd_cmd_t *); +static void isp_complete_ctio(struct ispsoftc *, tmd_cmd_t *); +static int isp_en_dis_lun(struct ispsoftc *, int, int, int, int); +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,27) +struct proc_dir_entry proc_scsi_qlc = { + PROC_SCSI_QLOGICISP, 3, "isp", S_IFDIR | S_IRUGO | S_IXUGO, 2 +}; +#endif +static const char *class3_roles[4] = { + "None", "Target", "Initiator", "Target/Initiator" +}; + +extern int isplinux_pci_detect(Scsi_Host_Template *); +extern void isplinux_pci_release(struct Scsi_Host *); + +struct info_str { + char *buffer; + int length; + off_t offset; + int pos; +}; + +static void +copy_mem_info(struct info_str *info, char *data, int len) +{ + if (info->pos + len > info->offset + info->length) + len = info->offset + info->length - info->pos; + + if (info->pos + len < info->offset) { + info->pos += len; + return; + } + + if (info->pos < info->offset) { + off_t partial; + + partial = info->offset - info->pos; + data += partial; + info->pos += partial; + len -= partial; + } + + if (len > 0) { + memcpy(info->buffer, data, len); + info->pos += len; + info->buffer += len; + } +} + +static int +copy_info(struct info_str *info, char *fmt, ...) +{ + va_list args; + char buf[256]; + int len; + + va_start(args, fmt); + len = vsprintf(buf, fmt, args); + va_end(args); + + copy_mem_info(info, buf, len); + return (len); +} + + +int +isplinux_proc_info(char *buf, char **st, off_t off, int len, int host, int io) +{ + int i; + struct info_str info; + struct ispsoftc *isp; + + isp = isplist; + while (isp) { + if (isp->isp_host->host_no == host) { + break; + } + isp = isp->isp_next; + } + if (isp == NULL) { + return (-ENODEV); + } + + if (io) { + buf[len] = 0; + io = -ENOSYS; + if (strncmp(buf, "debug=", 6) == 0) { + unsigned long debug; + char *p = &buf[6], *q; + debug = simple_strtoul(p, &q, 16); + if (q == &buf[6]) { + isp_prt(isp, ISP_LOGERR, "Garbled Debug Line '%s'", buf); + return (-EINVAL); + } + isp_prt(isp, ISP_LOGINFO, "setting debug level to 0x%lx", debug); + ISP_LOCKU_SOFTC(isp); + isp->isp_dblev = debug; + ISP_UNLKU_SOFTC(isp); + io = len; + } else if (strncmp(buf, "rescan", 6) == 0) { + if (IS_FC(isp)) { + SEND_THREAD_EVENT(isp, ISP_THREAD_FC_RESCAN, 1); + io = len; + } + } else if (strncmp(buf, "lip", 3) == 0) { + if (IS_FC(isp)) { + ISP_LOCKU_SOFTC(isp); + (void) isp_control(isp, ISPCTL_SEND_LIP, 0); + ISP_UNLKU_SOFTC(isp); + io = len; + } + } else if (strncmp(buf, "busreset=", 9) == 0) { + char *p = &buf[6], *q; + int bus = (int) simple_strtoul(p, &q, 16); + if (q == &buf[6]) { + isp_prt(isp, ISP_LOGERR, "Garbled Bus Reset Line '%s'", buf); + return (-EINVAL); + } + ISP_LOCKU_SOFTC(isp); + (void) isp_control(isp, ISPCTL_RESET_BUS, &bus); + ISP_UNLKU_SOFTC(isp); + io = len; + } else if (strncmp(buf, "devreset=", 9) == 0) { + char *p = &buf[6], *q; + int dev = (int) simple_strtoul(p, &q, 16); + if (q == &buf[6]) { + isp_prt(isp, ISP_LOGERR, "Garbled Dev Reset Line '%s'", buf); + return (-EINVAL); + } + /* always bus 0 */ + ISP_LOCKU_SOFTC(isp); + (void) isp_control(isp, ISPCTL_RESET_DEV, &dev); + ISP_UNLKU_SOFTC(isp); + io = len; + } else if (strncmp(buf, "reset", 5) == 0) { + ISP_LOCKU_SOFTC(isp); + io = isp_drain_reset(isp, "proc_reset"); + ISP_UNLKU_SOFTC(isp); + if (io == 0) + io = len; + else + io = -EIO; + } else if (strncmp(buf, "drain", 5) == 0) { + ISP_LOCKU_SOFTC(isp); + io = isp_drain(isp, "proc_reset"); + ISP_UNLKU_SOFTC(isp); + if (io == 0) + io = len; + else + io = -EIO; + } +#ifdef LINUX_ISP_TARGET_MODE + /* + * Note that this cannot enable or disable luns on other than bus 0. + */ + else if (strncmp(buf, "enable_lun=", 11) == 0) { + unsigned long lun; + char *p = &buf[11], *q; + lun = simple_strtoul(p, &q, 10); + if (q == &buf[11]) { + isp_prt(isp, ISP_LOGERR, + "attempted enable of invalid lun (%s)", buf); + return (-EINVAL); + } + io = isp_en_dis_lun(isp, 1, 0, -1, (int) lun); + if (io >= 0) + io = len; + } else if (strncmp(buf, "disable_lun=", 12) == 0) { + unsigned long lun; + char *p = &buf[12], *q; + lun = simple_strtoul(p, &q, 10); + if (q == &buf[12]) { + isp_prt(isp, ISP_LOGERR, + "attempted disable of invalid lun (%s)", buf); + return (-EINVAL); + } + io = isp_en_dis_lun(isp, 0, 0, -1, (int) lun); + if (io >= 0) + io = len; + } +#endif +#ifdef ISP_FW_CRASH_DUMP + else if (strncmp(buf, "fwcrash", 7) == 0) { + if (IS_FC(isp)) { + ISP_LOCKU_SOFTC(isp); + SEND_THREAD_EVENT(isp, ISP_THREAD_FW_CRASH_DUMP, 0); + ISP_UNLKU_SOFTC(isp); + io = len; + } + } +#endif + return (io); + } + + ISP_LOCKU_SOFTC(isp); + if (st) + *st = buf; + info.buffer = buf; + info.length = len; + info.offset = off; + info.pos = 0; + + copy_info(&info, (char *)isplinux_info(isp->isp_host)); +#ifdef HBA_VERSION + copy_info(&info, "\n HBA Version %s, built %s, %s", + HBA_VERSION, __DATE__, __TIME__); +#endif + copy_info(&info, "\n DEVID %x role %d\n", + isp->isp_osinfo.device_id, isp->isp_role); + copy_info(&info, + " Interrupt Stats:\n" + " total=0x%08x%08x bogus=0x%08x%08x\n" + " MboxC=0x%08x%08x async=0x%08x%08x\n" + " CRslt=0x%08x%08x CPost=0x%08x%08x\n" + " RspnsCHiWater=0x%04x FastPostC_Hiwater=0x%04x\n", + (u_int32_t) (isp->isp_intcnt >> 32), + (u_int32_t) (isp->isp_intcnt & 0xffffffff), + (u_int32_t) (isp->isp_intbogus >> 32), + (u_int32_t) (isp->isp_intbogus & 0xffffffff), + (u_int32_t) (isp->isp_intmboxc >> 32), + (u_int32_t) (isp->isp_intmboxc & 0xffffffff), + (u_int32_t) (isp->isp_intoasync >> 32), + (u_int32_t) (isp->isp_intoasync & 0xffffffff), + (u_int32_t) (isp->isp_rsltccmplt >> 32), + (u_int32_t) (isp->isp_rsltccmplt & 0xffffffff), + (u_int32_t) (isp->isp_fphccmplt >> 32), + (u_int32_t) (isp->isp_fphccmplt & 0xffffffff), + isp->isp_rscchiwater, isp->isp_fpcchiwater); + copy_info(&info, + " Request In %d Request Out %d Result %d Nactv %d" + " HiWater %u QAVAIL %d WtQHi %d\n", + isp->isp_reqidx, isp->isp_reqodx, isp->isp_residx, isp->isp_nactive, + isp->isp_osinfo.hiwater, ISP_QAVAIL(isp), + isp->isp_osinfo.wqhiwater); + for (i = 0; i < isp->isp_maxcmds; i++) { + if (isp->isp_xflist[i]) { + copy_info(&info, " %d:%p", i, isp->isp_xflist[i]); + } + } + copy_info(&info, "\n"); + if (isp->isp_osinfo.wqnext) { + Scsi_Cmnd *f = isp->isp_osinfo.wqnext; + copy_info(&info, "WaitQ(%d)", isp->isp_osinfo.wqcnt); + while (f) { + copy_info(&info, "->%p", f); + f = (Scsi_Cmnd *) f->host_scribble; + } + copy_info(&info, "\n"); + } + if (isp->isp_osinfo.dqnext) { + Scsi_Cmnd *f = isp->isp_osinfo.dqnext; + copy_info(&info, "DoneQ"); + while (f) { + copy_info(&info, "->%p", f); + f = (Scsi_Cmnd *) f->host_scribble; + } + copy_info(&info, "\n"); + } + if (IS_FC(isp)) { + fcparam *fcp = isp->isp_param; + copy_info(&info, + "Loop ID: %d AL_PA 0x%x Port ID 0x%x FW State %x Loop State %x\n", + fcp->isp_loopid, fcp->isp_alpa, fcp->isp_portid, fcp->isp_fwstate, + fcp->isp_loopstate); + copy_info(&info, "Port WWN 0x%08x%08x Node WWN 0x%08x%08x\n", + (unsigned int) (ISP_PORTWWN(isp) >> 32), + (unsigned int) (ISP_PORTWWN(isp) & 0xffffffff), + (unsigned int) (ISP_NODEWWN(isp) >> 32), + (unsigned int) (ISP_NODEWWN(isp) & 0xffffffff)); + for (i = 0; i < MAX_FC_TARG; i++) { + if (fcp->portdb[i].valid == 0 && i < FL_PORT_ID) + continue; + if (fcp->portdb[i].port_wwn == 0) + continue; + copy_info(&info, "TGT % 3d Loop ID % 3d Port id 0x%04x, role %s" + "\n Port WWN 0x%08x%08x Node WWN 0x%08x%08x\n\n", i, + fcp->portdb[i].loopid, + fcp->portdb[i].portid, class3_roles[fcp->portdb[i].roles], + (unsigned int) (fcp->portdb[i].port_wwn >> 32), + (unsigned int) (fcp->portdb[i].port_wwn & 0xffffffff), + (unsigned int) (fcp->portdb[i].node_wwn >> 32), + (unsigned int) (fcp->portdb[i].node_wwn & 0xffffffff)); + } + } else { + sdparam *sdp = (sdparam *)isp->isp_param; + + copy_info(&info, "Initiator ID: %d\n", sdp->isp_initiator_id); + copy_info(&info, "Target Flag Period Offset\n"); + for (i = 0; i < MAX_TARGETS; i++) { + copy_info(&info, "%6d: 0x%04x 0x%04x 0x%x\n", + i, sdp->isp_devparam[i].actv_flags, + sdp->isp_devparam[i].actv_offset, + sdp->isp_devparam[i].actv_period); + } + if (IS_DUALBUS(isp)) { + sdp++; + copy_info(&info, "\nInitiator ID: %d, Channel B\n", + sdp->isp_initiator_id); + copy_info(&info, + "Target CurFlag DevFlag Period Offset B-Channel\n"); + for (i = 0; i < MAX_TARGETS; i++) { + copy_info(&info, "%6d: 0x%04x 0x%04x 0x%x\n", + i, sdp->isp_devparam[i].actv_flags, + sdp->isp_devparam[i].actv_offset, + sdp->isp_devparam[i].actv_period); + } + } + } + ISP_UNLKU_SOFTC(isp); + return (info.pos > info.offset ? info.pos - info.offset : 0); +} + +int +isplinux_detect(Scsi_Host_Template *tmpt) +{ + int rval; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) + tmpt->proc_dir = &proc_scsi_qlc; +#else + tmpt->proc_name = "isp"; +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + spin_unlock_irq(&io_request_lock); + rval = isplinux_pci_detect(tmpt); + spin_lock_irq(&io_request_lock); +#else + rval = isplinux_pci_detect(tmpt); +#endif + return (rval); +} + +/* io_request_lock *not* held here */ +int +isplinux_release(struct Scsi_Host *host) +{ + struct ispsoftc *isp = (struct ispsoftc *) host->hostdata; +#ifdef ISP_TARGET_MODE + isp_detach_target(isp); +#endif + if (isp->isp_osinfo.task_thread) { + SEND_THREAD_EVENT(isp, ISP_THREAD_EXIT, 1); + } + ISP_LOCKU_SOFTC(isp); + isp->isp_role = ISP_ROLE_NONE; + ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); + if (IS_FC(isp)) { + ISP_WRITE(isp, BIU2100_CSR, BIU2100_FPM0_REGS); + ISP_WRITE(isp, FPM_DIAG_CONFIG, FPM_SOFT_RESET); + ISP_WRITE(isp, BIU2100_CSR, BIU2100_FB_REGS); + ISP_WRITE(isp, FBM_CMD, FBMCMD_FIFO_RESET_ALL); + ISP_WRITE(isp, BIU2100_CSR, BIU2100_RISC_REGS); + } + isp->dogactive = 0; + del_timer(&isp->isp_osinfo.timer); + DISABLE_INTS(isp); + if (isp->isp_bustype == ISP_BT_PCI) { + isplinux_pci_release(host); + } + ISP_UNLKU_SOFTC(isp); +#ifdef ISP_FW_CRASH_DUMP + if (FCPARAM(isp)->isp_dump_data) { + isp_prt(isp, ISP_LOGCONFIG, "freeing crash dump area"); + vfree(FCPARAM(isp)->isp_dump_data); + FCPARAM(isp)->isp_dump_data = 0; + } +#endif + return (1); +} + +const char * +isplinux_info(struct Scsi_Host *host) +{ + struct ispsoftc *isp = (struct ispsoftc *) host->hostdata; + if (IS_FC(isp)) { + static char *foo = "Driver for a Qlogic ISP 2X00 Host Adapter"; + foo[26] = '0'; + foo[27] = '0'; + if (isp->isp_type == ISP_HA_FC_2100) + foo[25] = '1'; + else if (isp->isp_type == ISP_HA_FC_2200) + foo[25] = '2'; + else if (isp->isp_type == ISP_HA_FC_2300) + foo[25] = '3'; + else if (isp->isp_type == ISP_HA_FC_2312) { + foo[25] = '3'; + foo[26] = '1'; + foo[27] = '2'; + } + return (foo); + } else if (IS_1240(isp)) { + return ("Driver for a Qlogic ISP 1240 Host Adapter"); + } else if (IS_1080(isp)) { + return ("Driver for a Qlogic ISP 1080 Host Adapter"); + } else if (IS_1280(isp)) { + return ("Driver for a Qlogic ISP 1280 Host Adapter"); + } else if (IS_10160(isp)) { + return ("Driver for a Qlogic ISP 10160 Host Adapter"); + } else if (IS_12160(isp)) { + return ("Driver for a Qlogic ISP 12160 Host Adapter"); + } else { + return ("Driver for a Qlogic ISP 1020/1040 Host Adapter"); + } +} + +static INLINE void +isplinux_append_to_waitq(struct ispsoftc *isp, Scsi_Cmnd *Cmnd) +{ + /* + * If we're a fibre channel card and we consider the loop to be + * down, we just finish the command here and now. + */ + if (IS_FC(isp) && isp->isp_deadloop) { + XS_INITERR(Cmnd); + XS_SETERR(Cmnd, DID_NO_CONNECT); + + /* + * Add back a timer else scsi_done drops this on the floor. + */ + scsi_add_timer(Cmnd, Cmnd->timeout_per_command, Cmnd->done); + isp_prt(isp, ISP_LOGDEBUG0, "giving up on target %d", XS_TGT(Cmnd)); + ISP_UNLK_SOFTC(isp); + ISP_LOCK_SCSI_DONE(isp); + (*Cmnd->scsi_done)(Cmnd); + ISP_UNLK_SCSI_DONE(isp); + ISP_LOCK_SOFTC(isp); + return; + } + + isp->isp_osinfo.wqcnt++; + if (isp->isp_osinfo.wqhiwater < isp->isp_osinfo.wqcnt) + isp->isp_osinfo.wqhiwater = isp->isp_osinfo.wqcnt; + if (isp->isp_osinfo.wqnext == NULL) { + isp->isp_osinfo.wqtail = isp->isp_osinfo.wqnext = Cmnd; + } else { + isp->isp_osinfo.wqtail->host_scribble = (unsigned char *) Cmnd; + isp->isp_osinfo.wqtail = Cmnd; + } + Cmnd->host_scribble = NULL; + + + /* + * Stop the clock for this command. + */ + (void) scsi_delete_timer(Cmnd); +} + +static INLINE void +isplinux_insert_head_waitq(struct ispsoftc *isp, Scsi_Cmnd *Cmnd) +{ + isp->isp_osinfo.wqcnt++; + if (isp->isp_osinfo.wqnext == NULL) { + isp->isp_osinfo.wqtail = isp->isp_osinfo.wqnext = Cmnd; + Cmnd->host_scribble = NULL; + } else { + Cmnd->host_scribble = (unsigned char *) isp->isp_osinfo.wqnext; + isp->isp_osinfo.wqnext = Cmnd; + } +} + +static INLINE Scsi_Cmnd * +isp_remove_from_waitq(Scsi_Cmnd *Cmnd) +{ + struct ispsoftc *isp; + Scsi_Cmnd *f; + if (Cmnd == NULL) + return (Cmnd); + isp = XS_ISP(Cmnd); + if ((f = isp->isp_osinfo.wqnext) == Cmnd) { + isp->isp_osinfo.wqnext = (Scsi_Cmnd *) Cmnd->host_scribble; + } else { + Scsi_Cmnd *b = f; + while (f) { + f = (Scsi_Cmnd *) b->host_scribble; + if (f == Cmnd) { + b->host_scribble = f->host_scribble; + if (isp->isp_osinfo.wqtail == Cmnd) + isp->isp_osinfo.wqtail = b; + break; + } + b = f; + } + } + if (f) { + f->host_scribble = NULL; + isp->isp_osinfo.wqcnt -= 1; + } + return (f); +} + +static INLINE void +isplinux_runwaitq(struct ispsoftc *isp) +{ + Scsi_Cmnd *f; + if (isp->isp_blocked || isp->isp_draining) + return; + while ((f = isp_remove_from_waitq(isp->isp_osinfo.wqnext)) != NULL) { + int result = isp_start(f); + /* + * Restart the timer for this command if it is queued or completing. + */ + if (result == CMD_QUEUED || result == CMD_COMPLETE) { + int ntime = f->timeout_per_command * (isp_xtime? isp_xtime : 1); + scsi_add_timer(f, ntime, f->done); + } + if (result == CMD_QUEUED) { + if (isp->isp_osinfo.hiwater < isp->isp_nactive) + isp->isp_osinfo.hiwater = isp->isp_nactive; + continue; + } + + /* + * If we cannot start a command on a fibre channel card, it means + * that loop state isn't ready for us to do so. Activate the FC + * thread to rediscover loop and fabric residency- but not if + * we consider the loop to be dead. If the loop is considered dead, + * we wait until a PDB Changed after a Loop UP activates the FC + * thread. + */ + if (result == CMD_RQLATER && IS_FC(isp) && isp->isp_deadloop == 0) { + SEND_THREAD_EVENT(isp, ISP_THREAD_FC_RESCAN, 0); + } + + /* + * Put the command back on the wait queue. Don't change any + * timer parameters for it because they were established + * when we originally put the command on the waitq in the first + * place. + */ + if (result == CMD_EAGAIN || result == CMD_RQLATER) { + isplinux_insert_head_waitq(isp, f); + break; + } + if (result == CMD_COMPLETE) { + isp_done(f); + } else { + panic("isplinux_runwaitq: result %d", result); + } + } +} + +static INLINE void +isplinux_flushwaitq(struct ispsoftc *isp) +{ + Scsi_Cmnd *Cmnd, *Ncmnd; + + if ((Cmnd = isp->isp_osinfo.wqnext) == NULL) { + return; + } + isp->isp_osinfo.wqnext = isp->isp_osinfo.wqtail = NULL; + isp->isp_osinfo.wqcnt = 0; + ISP_UNLK_SOFTC(isp); + do { + Ncmnd = (Scsi_Cmnd *) Cmnd->host_scribble; + Cmnd->host_scribble = NULL; + XS_INITERR(Cmnd); + XS_SETERR(Cmnd, DID_NO_CONNECT); + /* + * Add back a timer else scsi_done drops this on the floor. + */ + scsi_add_timer(Cmnd, Cmnd->timeout_per_command, Cmnd->done); + ISP_LOCK_SCSI_DONE(isp); + (*Cmnd->scsi_done)(Cmnd); + ISP_UNLK_SCSI_DONE(isp); + } while ((Cmnd = Ncmnd) != NULL); + ISP_LOCK_SOFTC(isp); +} + +static INLINE Scsi_Cmnd * +isplinux_remove_from_doneq(Scsi_Cmnd *Cmnd) +{ + Scsi_Cmnd *f; + struct ispsoftc *isp; + + if (Cmnd == NULL) + return (NULL); + isp = XS_ISP(Cmnd); + if (isp->isp_osinfo.dqnext == NULL) + return (NULL); + if ((f = isp->isp_osinfo.dqnext) == Cmnd) { + isp->isp_osinfo.dqnext = (Scsi_Cmnd *) Cmnd->host_scribble; + } else { + Scsi_Cmnd *b = f; + while (f) { + f = (Scsi_Cmnd *) b->host_scribble; + if (f == Cmnd) { + b->host_scribble = f->host_scribble; + if (isp->isp_osinfo.dqtail == Cmnd) + isp->isp_osinfo.dqtail = b; + break; + } + b = f; + } + } + if (f) { + f->host_scribble = NULL; + } + return (f); +} + +int +isplinux_queuecommand(Scsi_Cmnd *Cmnd, void (*donecmd)(Scsi_Cmnd *)) +{ + struct Scsi_Host *host = XS_HOST(Cmnd); + struct ispsoftc *isp = (struct ispsoftc *) (host->hostdata); + int result; + + + Cmnd->scsi_done = donecmd; + Cmnd->sense_buffer[0] = 0; + if (isp_xtime) { + Cmnd->timeout *= isp_xtime; + } + + ISP_DRIVER_ENTRY_LOCK(isp); + ISP_LOCK_SOFTC(isp); + + /* + * First off, see whether we need to (re)init the HBA. + * If we need to and fail to, pretend that this was a selection timeout. + */ + if (isp->isp_state != ISP_RUNSTATE) { + if (isp->isp_role != ISP_ROLE_NONE) { + isplinux_reinit(isp); + } + if (isp->isp_state != ISP_RUNSTATE) { + ISP_UNLK_SOFTC(isp); + ISP_DRIVER_EXIT_LOCK(isp); + XS_INITERR(Cmnd); + XS_SETERR(Cmnd, DID_NO_CONNECT); + donecmd(Cmnd); + return (0); + } + } + + + /* + * See if we're currently blocked. If we are, just queue up the command + * to be run later. + */ + if (isp->isp_blocked || isp->isp_draining) { + isplinux_append_to_waitq(isp, Cmnd); + ISP_UNLK_SOFTC(isp); + ISP_DRIVER_EXIT_LOCK(isp); + return (0); + } + + /* + * Next see if we have any stored up commands to run. If so, run them. + * If we get back from this with commands still ready to run, put the + * current command at the tail of waiting commands to be run later. + */ + + isplinux_runwaitq(isp); + if (isp->isp_osinfo.wqnext) { + isplinux_append_to_waitq(isp, Cmnd); + ISP_UNLK_SOFTC(isp); + ISP_DRIVER_EXIT_LOCK(isp); + return (0); + } + + /* + * Finally, try and run this command. + */ + + result = isp_start(Cmnd); + if (result == CMD_QUEUED) { + if (isp->isp_osinfo.hiwater < isp->isp_nactive) + isp->isp_osinfo.hiwater = isp->isp_nactive; + result = 0; + if (isp_xtime) { + int ntime = isp_xtime * Cmnd->timeout_per_command; + scsi_delete_timer(Cmnd); + scsi_add_timer(Cmnd, ntime, Cmnd->done); + } + } else if (result == CMD_EAGAIN) { + /* + * We ran out of request queue space (or could not + * get DMA resources). Tell the upper layer to try + * later. + */ + result = 1; + } else if (result == CMD_RQLATER) { + /* + * Temporarily hold off on this one. + * Typically this means for fibre channel + * that the loop is down or we're processing + * some other change (e.g., fabric membership + * change) + */ + isplinux_append_to_waitq(isp, Cmnd); + if (IS_FC(isp) && isp->isp_deadloop == 0) { + SEND_THREAD_EVENT(isp, ISP_THREAD_FC_RESCAN, 0); + } + result = 0; + } else if (result == CMD_COMPLETE) { + result = -1; + } else { + panic("unknown return code %d from isp_start", result); + } + ISP_UNLK_SOFTC(isp); + ISP_DRIVER_EXIT_LOCK(isp); + if (result == -1) { + Cmnd->result &= ~0xff; + Cmnd->result |= Cmnd->SCp.Status; + Cmnd->host_scribble = NULL; + (*Cmnd->scsi_done)(Cmnd); + result = 0; + } + return (result); +} + +static INLINE void isplinux_scsi_probe_done(Scsi_Cmnd *); + +static INLINE void +isplinux_scsi_probe_done(Scsi_Cmnd *Cmnd) +{ + struct ispsoftc *isp = XS_ISP(Cmnd); + + /* + * If we haven't seen this target yet, check the command result. If + * it was an inquiry and it succeeded okay, then we can update our + * notions about this target's capabilities. + * + * If the command did *not* succeed, we also update our notions about + * this target's capabilities (pessimistically) - it's probably not there. + * All of this so we can know when we're done so we stop wasting cycles + * seeing whether we can enable sync mode or not. + */ + + if (isp->isp_psco[XS_CHANNEL(Cmnd)][XS_TGT(Cmnd)] == 0) { + int i, b; + caddr_t iqd; + sdparam *sdp = (sdparam *) isp->isp_param; + + sdp += XS_CHANNEL(Cmnd); + if (Cmnd->cmnd[0] == 0x12 && host_byte(Cmnd->result) == DID_OK) { + if (Cmnd->use_sg == 0) { + iqd = (caddr_t) Cmnd->buffer; + } else { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + iqd = ((struct scatterlist *) Cmnd->request_buffer)->address; +#else + struct scatterlist *sg; + sg = (struct scatterlist *) Cmnd->request_buffer; + iqd = page_address(sg->page) + sg->offset; +#endif + } + sdp->isp_devparam[XS_TGT(Cmnd)].goal_flags &= + ~(DPARM_TQING|DPARM_SYNC|DPARM_WIDE); + if (iqd[7] & 0x2) { + sdp->isp_devparam[XS_TGT(Cmnd)].goal_flags |= DPARM_TQING; + } + if (iqd[7] & 0x10) { + sdp->isp_devparam[XS_TGT(Cmnd)].goal_flags |= DPARM_SYNC; + } + if (iqd[7] & 0x20) { + sdp->isp_devparam[XS_TGT(Cmnd)].goal_flags |= DPARM_WIDE; + } + sdp->isp_devparam[XS_TGT(Cmnd)].dev_update = 1; + isp->isp_psco[XS_CHANNEL(Cmnd)][XS_TGT(Cmnd)] = 1; + } else if (host_byte(Cmnd->result) != DID_OK) { + isp->isp_psco[XS_CHANNEL(Cmnd)][XS_TGT(Cmnd)] = 1; + } + + isp->isp_dutydone = 1; + for (b = 0; b < (IS_DUALBUS(isp)?2 : 1) && isp->isp_dutydone; b++) { + for (i = 0; i < MAX_TARGETS; i++) { + if (i != sdp->isp_initiator_id) { + if (isp->isp_psco[b][i] == 0) { + isp->isp_dutydone = 0; + break; + } + } + } + } + + /* + * Have we scanned all busses and all targets? You only get + * one chance (per reset) to see what devices on this bus have + * to offer. + */ + if (isp->isp_dutydone) { + for (b = 0; b < (IS_DUALBUS(isp)?2 : 1) && isp->isp_dutydone; b++) { + for (i = 0; i < MAX_TARGETS; i++) { + isp->isp_psco[b][i] = 0; + } + isp->isp_update |= (1 << b); + } + } + } +} + +void +isp_done(Scsi_Cmnd *Cmnd) +{ + struct ispsoftc *isp = XS_ISP(Cmnd); + + if (IS_SCSI(isp) && isp->isp_dutydone == 0) { + isplinux_scsi_probe_done(Cmnd); + } + + Cmnd->result &= ~0xff; + Cmnd->result |= Cmnd->SCp.Status; + + if (Cmnd->SCp.Status != GOOD) { + isp_prt(isp, ISP_LOGDEBUG0, "%d.%d.%d: cmd finishes with status 0x%x", + XS_CHANNEL(Cmnd), XS_TGT(Cmnd), XS_LUN(Cmnd), Cmnd->SCp.Status); + } + + /* + * If we had a way handling residuals, this is where we'd do it + */ + + /* + * Queue command on completion queue. + */ + if (isp->isp_osinfo.dqnext == NULL) { + isp->isp_osinfo.dqnext = Cmnd; + } else { + isp->isp_osinfo.dqtail->host_scribble = (unsigned char *) Cmnd; + } + isp->isp_osinfo.dqtail = Cmnd; + Cmnd->host_scribble = NULL; +} + +/* + * Error handling routines + */ + +int +isplinux_abort(Scsi_Cmnd *Cmnd) +{ + struct ispsoftc *isp; + u_int16_t handle; + + if (Cmnd == NULL || XS_HOST(Cmnd) == NULL) { + return (FAILED); + } + + isp = XS_ISP(Cmnd); + if (Cmnd->serial_number != Cmnd->serial_number_at_timeout) { + isp_prt(isp, ISP_LOGWARN, "isplinux_abort: serial number mismatch"); + return (FAILED); + } + ISP_DRIVER_ENTRY_LOCK(isp); + ISP_LOCKU_SOFTC(isp); + handle = isp_find_handle(isp, Cmnd); + if (handle == 0) { + int wqfnd = 0; + Scsi_Cmnd *NewCmnd = isp_remove_from_waitq(Cmnd); + if (NewCmnd == NULL) { + NewCmnd = isplinux_remove_from_doneq(Cmnd); + wqfnd++; + } + ISP_UNLK_SOFTC(isp); + isp_prt(isp, ISP_LOGINFO, + "isplinux_abort: found %d:%p for non-running cmd for %d.%d.%d", + wqfnd, NewCmnd, XS_CHANNEL(Cmnd), XS_TGT(Cmnd), XS_LUN(Cmnd)); + if (NewCmnd == NULL) { + ISP_DRIVER_EXIT_LOCK(isp); + return (FAILED); + } + } else { + if (isp_control(isp, ISPCTL_ABORT_CMD, Cmnd)) { + ISP_UNLK_SOFTC(isp); + ISP_DRIVER_EXIT_LOCK(isp); + return (FAILED); + } + if (isp->isp_nactive > 0) + isp->isp_nactive--; + isp_destroy_handle(isp, handle); + ISP_UNLK_SOFTC(isp); + ISP_DRIVER_EXIT_LOCK(isp); + isp_prt(isp, ISP_LOGINFO, + "isplinux_abort: aborted running cmd (handle 0x%x) for %d.%d.%d", + handle, XS_CHANNEL(Cmnd), XS_TGT(Cmnd), XS_LUN(Cmnd)); + } + Cmnd->result = DID_ABORT << 16; + (*Cmnd->scsi_done)(Cmnd); + return (SUCCESS); +} + +/* + * XXX: What does the midlayer expect for commands in process? + * XXX: Are we supposed to clean up dead commands ourselves? + */ +int +isplinux_bdr(Scsi_Cmnd *Cmnd) +{ + struct ispsoftc *isp; + int arg; + + if (Cmnd == NULL || XS_HOST(Cmnd) == NULL) { + return (FAILED); + } + + isp = XS_ISP(Cmnd); + arg = XS_CHANNEL(Cmnd) << 16 | XS_TGT(Cmnd); + ISP_DRIVER_ENTRY_LOCK(isp); + ISP_LOCK_SOFTC(isp); + arg = isp_control(isp, ISPCTL_RESET_DEV, &arg); + ISP_UNLK_SOFTC(isp); + ISP_DRIVER_EXIT_LOCK(isp); + isp_prt(isp, ISP_LOGINFO, "Bus Device Reset %succesfully sent to %d.%d.%d", + arg == 0? "s" : "uns", XS_CHANNEL(Cmnd), XS_TGT(Cmnd), XS_LUN(Cmnd)); + return ((arg == 0)? SUCCESS : FAILED); +} + +/* + * XXX: What does the midlayer expect for commands in process? + */ +int +isplinux_sreset(Scsi_Cmnd *Cmnd) +{ + struct ispsoftc *isp; + int arg; + + if (Cmnd == NULL || XS_HOST(Cmnd) == NULL) + return (FAILED); + + isp = XS_ISP(Cmnd); + arg = XS_CHANNEL(Cmnd); + ISP_DRIVER_ENTRY_LOCK(isp); + ISP_LOCK_SOFTC(isp); + arg = isp_control(isp, ISPCTL_RESET_BUS, &arg); + ISP_UNLK_SOFTC(isp); + ISP_DRIVER_EXIT_LOCK(isp); + isp_prt(isp, ISP_LOGINFO, "SCSI Bus Reset on Channel %d %succesful", + XS_CHANNEL(Cmnd), arg == 0? "s" : "uns"); + return ((arg == 0)? SUCCESS : FAILED); +} + +/* + * We call completion on any commands owned here- + * except the one we were called with. + */ +int +isplinux_hreset(Scsi_Cmnd *Cmnd) +{ + Scsi_Cmnd *tmp, *dq, *wq, *xqf, *xql; + struct ispsoftc *isp; + u_int16_t handle; + + if (Cmnd == NULL || XS_HOST(Cmnd) == NULL) + return (FAILED); + + isp = XS_ISP(Cmnd); + + isp_prt(isp, ISP_LOGINFO, "Resetting Host Adapter"); + + ISP_DRIVER_ENTRY_LOCK(isp); + ISP_LOCK_SOFTC(isp); + + /* + * Save pending, running, and completed commands. + */ + xql = xqf = NULL; + for (handle = 1; handle <= isp->isp_maxcmds; handle++) { + tmp = isp_find_xs(isp, handle); + if (tmp == NULL) { + continue; + } + isp_destroy_handle(isp, handle); + tmp->host_scribble = NULL; + if (xqf) { + xql->host_scribble = (unsigned char *) tmp; + } else { + xqf = xql = tmp; + } + xql = tmp; + } + dq = isp->isp_osinfo.dqnext; + isp->isp_osinfo.dqnext = NULL; + wq = isp->isp_osinfo.wqnext; + isp->isp_osinfo.wqnext = NULL; + isp->isp_nactive = 0; + + isplinux_reinit(isp); + + ISP_UNLK_SOFTC(isp); + ISP_DRIVER_EXIT_LOCK(isp); + + /* + * Call completion on the detritus, skipping the one we were called with. + */ + while ((tmp = xqf) != NULL) { + xqf = (Scsi_Cmnd *) tmp->host_scribble; + tmp->host_scribble = NULL; + if (tmp == Cmnd) + continue; + tmp->result = DID_RESET << 16; + /* + * Get around silliness in midlayer. + */ + tmp->flags |= IS_RESETTING; + if (tmp->scsi_done) + (*tmp->scsi_done)(tmp); + } + while ((tmp = wq) != NULL) { + wq = (Scsi_Cmnd *) tmp->host_scribble; + tmp->host_scribble = NULL; + if (tmp == Cmnd) + continue; + tmp->result = DID_RESET << 16; + /* + * Get around silliness in midlayer. + */ + tmp->flags |= IS_RESETTING; + if (tmp->scsi_done) + (*tmp->scsi_done)(tmp); + } + while ((tmp = dq) != NULL) { + dq = (Scsi_Cmnd *) tmp->host_scribble; + tmp->host_scribble = NULL; + if (tmp == Cmnd) + continue; + tmp->result = DID_RESET << 16; + /* + * Get around silliness in midlayer. + */ + tmp->flags |= IS_RESETTING; + if (tmp->scsi_done) + (*tmp->scsi_done)(tmp); + } + Cmnd->result = DID_RESET << 16; + return (SUCCESS); +} + + +#ifdef LINUX_ISP_TARGET_MODE +void +isp_attach_target(struct ispsoftc *isp) +{ + int i; + hba_register_t hba; + + hba.r_identity = isp; + sprintf(hba.r_name, "isp"); + hba.r_inst = isp->isp_unit; + if (IS_DUALBUS(isp)) + hba.r_buswidth = 2; + else + hba.r_buswidth = 1; + hba.r_lunwidth = IS_FC(isp)? TM_MAX_LUN_FC : TM_MAX_LUN_SCSI; + for (i = 0; i < NTGT_CMDS-1; i++) { + isp->isp_osinfo.pool[i].cd_private = &isp->isp_osinfo.pool[i+1]; + } + isp->isp_osinfo.pending_t = NULL; + isp->isp_osinfo.tfreelist = isp->isp_osinfo.pool; + hba.r_action = (void (*)(int, void *))isp_taction; + ISP_UNLKU_SOFTC(isp); + ISP_PARENT_TARGET (QOUT_HBA_REG, &hba); + ISP_LOCKU_SOFTC(isp); +} + +void +isp_detach_target(struct ispsoftc *isp) +{ + tmd_cmd_t tmd; + tmd.cd_hba = isp; + tmd.cd_private = isp->isp_osinfo.hcb_token; + ISP_PARENT_TARGET (QOUT_HBA_UNREG, &tmd); +} + +static void +isp_taction(qact_e action, void *arg) +{ + tmd_cmd_t *tmd = arg; + struct ispsoftc *isp = (tmd != NULL)? tmd->cd_hba : NULL; + + switch (action) { + case QIN_HBA_REG: + { + hba_register_t *hp = tmd->cd_data; + isp_prt(isp, ISP_LOGINFO, "completed target registration"); + isp->isp_osinfo.hcb = hp->r_action; + isp->isp_osinfo.hcb_token = hp->r_identity; + break; + } + + case QIN_ENABLE: + case QIN_DISABLE: + { + int r, bus, lun, tgt; + + bus = (int) tmd->cd_bus; + lun = (int) tmd->cd_lun; + tgt = (int) tmd->cd_tgt; + r = isp_en_dis_lun(isp, (action == QIN_ENABLE)? 1 : 0, bus, tgt, lun); + if (r) { + tmd->cd_error = r; + tmd->cd_lflags |= CDFL_ERROR; + } + break; + } + + case QIN_TMD_CONT: + isp_target_start_ctio(isp, tmd); + break; + + case QIN_TMD_FIN: + MEMZERO(tmd, sizeof (tmd_cmd_t)); + ISP_LOCK_SOFTC(isp); + tmd->cd_private = isp->isp_osinfo.tfreelist; + isp->isp_osinfo.tfreelist = tmd; + ISP_UNLK_SOFTC(isp); + break; + + case QIN_HBA_UNREG: + isp->isp_osinfo.hcb = NULL; + break; + + default: + break; + } +} + +static INLINE int +nolunsenabled(struct ispsoftc *isp, int port) +{ + int i, wbase, wend; + + if (IS_FC(isp)) { + wbase = 0; + wend = TM_MAX_LUN_FC >> 5; + } else { + if (port) { + wend = TM_MAX_LUN_FC >> 5; + wbase = wend >> 1; + } else { + wend = (TM_MAX_LUN_FC >> 5) >> 1; + wbase = 0; + } + } + for (i = wbase; i < wend; i++) { + if (isp->isp_osinfo.lunbmap[i]) { + return (0); + } + } + return (1); +} + + + +static void +isp_target_start_ctio(struct ispsoftc *isp, tmd_cmd_t *tmd) +{ + void *qe; + u_int16_t *hp, save_handle; + u_int32_t *rp; + u_int16_t nxti, optr; + u_int8_t local[QENTRY_LEN]; + + /* + * If the transfer length is zero, we have to be sending status. + * If we're sending data, we have to have one and only one data + * direction set. + */ + if (tmd->cd_xfrlen == 0) { + if ((tmd->cd_hflags & CDFH_STSVALID) == 0) { + isp_prt(isp, ISP_LOGERR, "CTIO, no data, and no status is wrong"); + tmd->cd_error = -EINVAL; + tmd->cd_lflags |= CDFL_ERROR; + return; + } + } else { + if ((tmd->cd_hflags & CDFH_DATA_MASK) == 0) { + isp_prt(isp, ISP_LOGERR, "data CTIO with no direction is wrong"); + tmd->cd_error = -EINVAL; + tmd->cd_lflags |= CDFL_ERROR; + return; + } + if ((tmd->cd_hflags & CDFH_DATA_MASK) == CDFH_DATA_MASK) { + isp_prt(isp, ISP_LOGERR, "data CTIO with both directions is wrong"); + tmd->cd_error = -EINVAL; + tmd->cd_lflags |= CDFL_ERROR; + return; + } + } + tmd->cd_lflags &= ~CDFL_ERROR; + MEMZERO(local, QENTRY_LEN); + + ISP_LOCK_SOFTC(isp); + if (isp_getrqentry(isp, &nxti, &optr, &qe)) { + isp_prt(isp, ISP_LOGWARN, + "isp_target_start_ctio: request queue overflow"); + tmd->cd_error = -ENOMEM; + tmd->cd_lflags |= CDFL_ERROR; + ISP_UNLK_SOFTC(isp); + return; + } + + /* + * We're either moving data or completing a command here (or both). + */ + + if (IS_FC(isp)) { + ct2_entry_t *cto = (ct2_entry_t *) local; + u_int16_t *ssptr = NULL; + + cto->ct_header.rqs_entry_type = RQSTYPE_CTIO2; + cto->ct_header.rqs_entry_count = 1; + cto->ct_iid = tmd->cd_iid; + if ((FCPARAM(isp)->isp_fwattr & ISP_FW_ATTR_SCCLUN) == 0) + cto->ct_lun = tmd->cd_lun; + else + cto->ct_lun = 0; + cto->ct_rxid = tmd->cd_tagval; + if (cto->ct_rxid == 0) { + isp_prt(isp, ISP_LOGERR, "a tagval of zero is not acceptable"); + tmd->cd_error = -EINVAL; + tmd->cd_lflags |= CDFL_ERROR; + ISP_UNLK_SOFTC(isp); + return; + } + cto->ct_flags = 0; + + if (tmd->cd_xfrlen == 0) { + cto->ct_flags |= CT2_FLAG_MODE1 | CT2_NO_DATA | + CT2_SENDSTATUS | CT2_CCINCR; + ssptr = &cto->rsp.m1.ct_scsi_status; + *ssptr = tmd->cd_scsi_status; + if ((tmd->cd_hflags & CDFH_SNSVALID) != 0) { + MEMCPY(cto->rsp.m1.ct_resp, tmd->cd_sense, QLTM_SENSELEN); + cto->rsp.m1.ct_senselen = QLTM_SENSELEN; + cto->rsp.m1.ct_scsi_status |= CT2_SNSLEN_VALID; + } + } else { + cto->ct_flags |= CT2_FLAG_MODE0; + if (tmd->cd_hflags & CDFH_DATA_IN) { + cto->ct_flags |= CT2_DATA_IN; + } else { + cto->ct_flags |= CT2_DATA_OUT; + } + if (tmd->cd_hflags & CDFH_STSVALID) { + ssptr = &cto->rsp.m0.ct_scsi_status; + cto->ct_flags |= CT2_SENDSTATUS | CT2_CCINCR; + cto->rsp.m0.ct_scsi_status = tmd->cd_scsi_status; + if ((tmd->cd_hflags & CDFH_SNSVALID) && + tmd->cd_scsi_status == SCSI_CHECK) { + MEMCPY(cto->rsp.m0.ct_dataseg, tmd->cd_sense, + QLTM_SENSELEN); + cto->rsp.m0.ct_scsi_status |= CT2_SNSLEN_VALID; + } + } + /* + * We assume we'll transfer what we say we'll transfer. + * Otherwise, the command is dead. + */ + tmd->cd_resid -= tmd->cd_xfrlen; + } + + if (ssptr && tmd->cd_resid) { + cto->ct_resid = tmd->cd_resid; + *ssptr |= CT2_DATA_UNDER; + } else { + cto->ct_resid = 0; + } + isp_prt(isp, ISP_LOGTDEBUG0, + "CTIO2[%x] ssts %x flags %x resid %d", + cto->ct_rxid, tmd->cd_scsi_status, cto->ct_flags, cto->ct_resid); + hp = &cto->ct_syshandle; + rp = &cto->ct_resid; + if (cto->ct_flags & CT2_SENDSTATUS) + cto->ct_flags |= CT2_CCINCR; + } else { + ct_entry_t *cto = (ct_entry_t *) local; + + cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; + cto->ct_header.rqs_entry_count = 1; + cto->ct_iid = tmd->cd_iid; + cto->ct_tgt = tmd->cd_tgt; + cto->ct_lun = tmd->cd_lun; + cto->ct_flags = 0; + cto->ct_fwhandle = AT_GET_HANDLE(tmd->cd_tagval); + if (AT_HAS_TAG(tmd->cd_tagval)) { + cto->ct_tag_val = AT_GET_TAG(tmd->cd_tagval); + cto->ct_flags |= CT_TQAE; + } + if (tmd->cd_lflags & CDFL_NODISC) { + cto->ct_flags |= CT_NODISC; + } + if (tmd->cd_xfrlen == 0) { + cto->ct_flags |= CT_NO_DATA | CT_SENDSTATUS; + cto->ct_scsi_status = tmd->cd_scsi_status; + cto->ct_resid = 0; + } else { + if (tmd->cd_hflags & CDFH_STSVALID) { + cto->ct_flags |= CT_SENDSTATUS; + } + if (tmd->cd_hflags & CDFH_DATA_IN) { + cto->ct_flags |= CT_DATA_IN; + } else { + cto->ct_flags |= CT_DATA_OUT; + } + /* + * We assume we'll transfer what we say we'll transfer. + * Otherwise, the command is dead. + */ + tmd->cd_resid -= tmd->cd_xfrlen; + if (tmd->cd_hflags & CDFH_STSVALID) { + cto->ct_resid = tmd->cd_resid; + } + } + isp_prt(isp, ISP_LOGTDEBUG0, "CTIO[%x] ssts %x resid %d cd_hflags %x", + AT_GET_HANDLE(tmd->cd_tagval), tmd->cd_scsi_status, tmd->cd_resid, + tmd->cd_hflags); + hp = &cto->ct_syshandle; + rp = &cto->ct_resid; + if (cto->ct_flags & CT_SENDSTATUS) + cto->ct_flags |= CT_CCINCR; + } + + if (isp_save_xs(isp, (XS_T *)tmd, hp)) { + isp_prt(isp, ISP_LOGERR, "isp_target_start_ctio: No XFLIST pointers"); + tmd->cd_error = -ENOMEM; + tmd->cd_lflags |= CDFL_ERROR; + ISP_UNLK_SOFTC(isp); + tmd->cd_private = isp->isp_osinfo.hcb_token; + (*isp->isp_osinfo.hcb)(QOUT_TMD_DONE, tmd); + return; + } + + /* + * Call the dma setup routines for this entry (and any subsequent + * CTIOs) if there's data to move, and then tell the f/w it's got + * new things to play with. As with isp_start's usage of DMA setup, + * any swizzling is done in the machine dependent layer. Because + * of this, we put the request onto the queue area first in native + * format. + */ + + save_handle = *hp; + switch (ISP_DMASETUP(isp, (XS_T *)tmd, (ispreq_t *) local, &nxti, optr)) { + case CMD_QUEUED: + ISP_ADD_REQUEST(isp, nxti); + ISP_UNLK_SOFTC(isp); + return; + + case CMD_EAGAIN: + tmd->cd_error = -ENOMEM; + tmd->cd_lflags |= CDFL_ERROR; + isp_destroy_handle(isp, save_handle); + break; + + case CMD_COMPLETE: + tmd->cd_error = *rp; /* propagated back */ + tmd->cd_lflags |= CDFL_ERROR; + isp_destroy_handle(isp, save_handle); + break; + + default: + tmd->cd_error = -EFAULT; /* probably dma mapping failure */ + tmd->cd_lflags |= CDFL_ERROR; + isp_destroy_handle(isp, save_handle); + break; + } + ISP_UNLK_SOFTC(isp); + tmd->cd_private = isp->isp_osinfo.hcb_token; + (*isp->isp_osinfo.hcb)(QOUT_TMD_DONE, tmd); +} + +/* + * Handle ATIO stuff that the generic code can't. + * This means handling CDBs. + */ + +static int +isp_handle_platform_atio(struct ispsoftc *isp, at_entry_t *aep) +{ + tmd_cmd_t *tmd; + int status; + + /* + * The firmware status (except for the QLTM_SVALID bit) + * indicates why this ATIO was sent to us. + * + * If QLTM_SVALID is set, the firware has recommended Sense Data. + * + * If the DISCONNECTS DISABLED bit is set in the flags field, + * we're still connected on the SCSI bus. + */ + status = aep->at_status; + + if ((status & ~QLTM_SVALID) == AT_PHASE_ERROR) { + /* + * Bus Phase Sequence error. We should have sense data + * suggested by the f/w. I'm not sure quite yet what + * to do about this. + */ + isp_prt(isp, ISP_LOGERR, "PHASE ERROR in atio"); + isp_endcmd(isp, aep, SCSI_BUSY, 0); + return (0); + } + + if ((status & ~QLTM_SVALID) != AT_CDB) { + isp_prt(isp, ISP_LOGERR, "bad atio (0x%x) leaked to platform", status); + isp_endcmd(isp, aep, SCSI_BUSY, 0); + return (0); + } + + if ((tmd = isp->isp_osinfo.tfreelist) == NULL) { + /* + * We're out of resources. + * + * Because we can't autofeed sense data back with a command for + * parallel SCSI, we can't give back a CHECK CONDITION. We'll give + * back a QUEUE FULL or BUSY status instead. + */ + isp_prt(isp, ISP_LOGERR, + "no ATIOS for lun %d from initiator %d on channel %d", + aep->at_lun, GET_IID_VAL(aep->at_iid), GET_BUS_VAL(aep->at_iid)); + if (aep->at_flags & AT_TQAE) + isp_endcmd(isp, aep, SCSI_QFULL, 0); + else + isp_endcmd(isp, aep, SCSI_BUSY, 0); + return (0); + } + isp->isp_osinfo.tfreelist = tmd->cd_private; + tmd->cd_lflags = CDFL_BUSY; + tmd->cd_bus = GET_BUS_VAL(aep->at_iid); + tmd->cd_iid = GET_IID_VAL(aep->at_iid); + tmd->cd_tgt = aep->at_tgt; + tmd->cd_lun = aep->at_lun; + if (aep->at_flags & AT_NODISC) { + tmd->cd_lflags |= CDFL_NODISC; + } + if (status & QLTM_SVALID) { + MEMCPY(tmd->cd_sense, aep->at_sense, QLTM_SENSELEN); + tmd->cd_lflags |= CDFL_SNSVALID; + } + MEMCPY(tmd->cd_cdb, aep->at_cdb, ATIO_CDBLEN); + AT_MAKE_TAGID(tmd->cd_tagval, aep); + tmd->cd_tagtype = aep->at_tag_type; + tmd->cd_hba = isp; + tmd->cd_data = NULL; + tmd->cd_hflags = 0; + tmd->cd_totlen = tmd->cd_resid = tmd->cd_xfrlen = tmd->cd_error = 0; + tmd->cd_scsi_status = 0; + isp_prt(isp, ISP_LOGTDEBUG1, + "ATIO[%x] CDB=0x%x bus %d iid%d->lun%d tag 0x%x ttype 0x%x %s", + aep->at_handle, aep->at_cdb[0] & 0xff, GET_BUS_VAL(aep->at_iid), + GET_IID_VAL(aep->at_iid), aep->at_lun, aep->at_tag_val & 0xff, + aep->at_tag_type, (aep->at_flags & AT_NODISC)? + "nondisc" : "disconnecting"); + if (isp->isp_osinfo.hcb == NULL) { + isp_endcmd(isp, aep, SCSI_BUSY, 0); + } else { + tmd->cd_reserved[0] = QOUT_TMD_START; + tmd->cd_private = isp->isp_osinfo.pending_t; + isp->isp_osinfo.pending_t = tmd; + } + return (0); +} + +static int +isp_handle_platform_atio2(struct ispsoftc *isp, at2_entry_t *aep) +{ + tmd_cmd_t *tmd; + int lun; + + /* + * The firmware status (except for the QLTM_SVALID bit) + * indicates why this ATIO was sent to us. + * + * If QLTM_SVALID is set, the firware has recommended Sense Data. + */ + if ((aep->at_status & ~QLTM_SVALID) != AT_CDB) { + isp_prt(isp, ISP_LOGERR, "bad atio (0x%x) leaked to platform", + aep->at_status); + isp_endcmd(isp, aep, SCSI_BUSY, 0); + return (0); + } + if (FCPARAM(isp)->isp_fwattr & ISP_FW_ATTR_SCCLUN) + lun = aep->at_scclun; + else + lun = aep->at_lun; + + /* + * If we're out of resources, just send a QFULL status back. + */ + if ((tmd = isp->isp_osinfo.tfreelist) == NULL) { + isp_endcmd(isp, aep, SCSI_QFULL, 0); + return (0); + } + tmd->cd_lflags = CDFL_BUSY; + tmd->cd_iid = aep->at_iid; + tmd->cd_tgt = ((fcparam *)isp->isp_param)->isp_loopid; + tmd->cd_lun = lun; + tmd->cd_bus = 0; + MEMCPY(tmd->cd_cdb, aep->at_cdb, ATIO_CDBLEN); + switch (aep->at_taskflags & ATIO2_TC_ATTR_MASK) { + case ATIO2_TC_ATTR_SIMPLEQ: + tmd->cd_tagtype = MSG_SIMPLE_Q_TAG; + break; + case ATIO2_TC_ATTR_HEADOFQ: + tmd->cd_tagtype = MSG_HEAD_OF_Q_TAG; + break; + case ATIO2_TC_ATTR_ORDERED: + tmd->cd_tagtype = MSG_ORDERED_Q_TAG; + break; + case ATIO2_TC_ATTR_ACAQ: /* ?? */ + case ATIO2_TC_ATTR_UNTAGGED: + default: + tmd->cd_tagtype = 0; + break; + } + tmd->cd_tagval = aep->at_rxid; + tmd->cd_hba = isp; + tmd->cd_data = NULL; + tmd->cd_hflags = 0; + tmd->cd_totlen = aep->at_datalen; + tmd->cd_resid = tmd->cd_xfrlen = tmd->cd_error = 0; + tmd->cd_scsi_status = 0; + if ((isp->isp_dblev & ISP_LOGTDEBUG0) || isp->isp_osinfo.hcb == NULL) { + isp_prt(isp, ISP_LOGALL, + "ATIO2[%x] CDB=0x%x iid %d for lun %d tcode 0x%x dlen %d", + aep->at_rxid, aep->at_cdb[0] & 0xff, aep->at_iid, + lun, aep->at_taskcodes, aep->at_datalen); + } + if (isp->isp_osinfo.hcb == NULL) { + if (aep->at_cdb[0] == INQUIRY && lun == 0) { + if (aep->at_cdb[1] == 0 && aep->at_cdb[2] == 0) { + static u_int8_t inqdata[] = { + DEFAULT_DEVICE_TYPE, 0x0, 0x2, 0x2, 32, 0, 0, 0x40, + 'L', 'I', 'N', 'U', 'X', ' ', ' ', ' ', + 'T', 'A', 'R', 'G', 'E', 'T', ' ', 'D', + 'D', 'E', 'V', 'I', 'C', 'E', ' ', ' ', + '0', '0', '0', '1' + }; + struct scatterlist single, *dp = &single; + dp->address = inqdata; + dp->length = sizeof (inqdata); + tmd->cd_data = dp; + tmd->cd_resid = tmd->cd_xfrlen = sizeof (inqdata); + tmd->cd_hflags |= CDFH_DATA_IN|CDFH_STSVALID; + ISP_DROP_LK_SOFTC(isp); + isp_target_start_ctio(isp, tmd); + ISP_IGET_LK_SOFTC(isp); + } else { + /* + * Illegal field in CDB + * 0x24 << 24 | 0x5 << 12 | ECMD_SVALID | SCSI_CHECK + */ + isp_endcmd(isp, aep, 0x24005102, 0); + } + } else if (lun == 0) { + /* + * Not Ready, Cause Not Reportable + * + * 0x4 << 24 | 0x2 << 12 | ECMD_SVALID | SCSI_CHECK + */ + isp_endcmd(isp, aep, 0x04002102, 0); + } else { + /* + * Logical Unit Not Supported: + * 0x25 << 24 | 0x5 << 12 | ECMD_SVALID | SCSI_CHECK + */ + isp_endcmd(isp, aep, 0x25005102, 0); + } + MEMZERO(tmd, sizeof (tmd_cmd_t)); + return (0); + } + tmd->cd_reserved[0] = QOUT_TMD_START; + isp->isp_osinfo.tfreelist = tmd->cd_private; + tmd->cd_private = isp->isp_osinfo.pending_t; + isp->isp_osinfo.pending_t = tmd; + return (0); +} + +static int +isp_handle_platform_ctio(struct ispsoftc *isp, void *arg) +{ + tmd_cmd_t *tmd; + int sentstatus, ok, resid = 0, sts; + + /* + * CTIO and CTIO2 are close enough.... + */ + tmd = (tmd_cmd_t *) isp_find_xs(isp, ((ct_entry_t *)arg)->ct_syshandle); + if (tmd == NULL) { + isp_prt(isp, ISP_LOGERR, "isp_handle_platform_ctio: null tmd"); + return (0); + } + isp_destroy_handle(isp, ((ct_entry_t *)arg)->ct_syshandle); + + if (IS_FC(isp)) { + ct2_entry_t *ct = arg; + sentstatus = ct->ct_flags & CT2_SENDSTATUS; + if (sentstatus) { + tmd->cd_lflags |= CDFL_SENTSTATUS; + } + sts = ct->ct_status & ~QLTM_SVALID; + ok = (ct->ct_status & ~QLTM_SVALID) == CT_OK; + if (ok && sentstatus && (tmd->cd_hflags & CDFH_SNSVALID)) { + tmd->cd_lflags |= CDFL_SENTSENSE; + } + isp_prt(isp, ISP_LOGTDEBUG1, + "CTIO2[%x] sts 0x%x flg 0x%x sns %d %s", + ct->ct_rxid, ct->ct_status, ct->ct_flags, + (tmd->cd_lflags & CDFL_SENTSENSE) != 0, + sentstatus? "FIN" : "MID"); + if ((ct->ct_flags & CT2_DATAMASK) != CT2_NO_DATA) { + resid = ct->ct_resid; + } + } else { + ct_entry_t *ct = arg; + sts = ct->ct_status & ~QLTM_SVALID; + sentstatus = ct->ct_flags & CT_SENDSTATUS; + if (sentstatus) { + tmd->cd_lflags |= CDFL_SENTSTATUS; + } + ok = (ct->ct_status & ~QLTM_SVALID) == CT_OK; + if (ok && sentstatus && (tmd->cd_hflags & CDFH_SNSVALID)) { + tmd->cd_lflags |= CDFL_SENTSENSE; + } + isp_prt(isp, ISP_LOGTDEBUG1, + "CTIO[%x] tag %x iid %x tgt %d lun %d sts 0x%x flg %x %s", + ct->ct_fwhandle, ct->ct_tag_val, ct->ct_iid, ct->ct_tgt, + ct->ct_lun, ct->ct_status, ct->ct_flags, + sentstatus? "FIN" : "MID"); + if (ct->ct_status & QLTM_SVALID) { + char *sp = (char *)ct; + sp += CTIO_SENSE_OFFSET; + MEMCPY(tmd->cd_sense, sp, QLTM_SENSELEN); + tmd->cd_lflags |= CDFL_SNSVALID; + } + if ((ct->ct_flags & CT_DATAMASK) != CT_NO_DATA) { + resid = ct->ct_resid; + } + } + tmd->cd_resid += resid; + + /* + * We're here either because intermediate data transfers are done + * and/or the final status CTIO (which may have joined with a + * Data Transfer) is done. + * + * In any case, for this platform, the upper layers figure out + * what to do next, so all we do here is collect status and + * pass information along. + */ + isp_prt(isp, ISP_LOGTDEBUG0, "%s CTIO done (resid %d)", + (sentstatus)? " FINAL " : "MIDTERM ", tmd->cd_resid); + + if (!ok) { + isp_prt(isp, ISP_LOGERR, "CTIO ended with badstate (0x%x)", sts); + tmd->cd_lflags |= CDFL_ERROR; + tmd->cd_error = -EIO; + isp_target_putback_atio(isp, tmd); + } else { + isp_complete_ctio(isp, tmd); + } + return (0); +} + +static void +isp_target_putback_atio(struct ispsoftc *isp, tmd_cmd_t *tmd) +{ + u_int16_t nxti; + u_int8_t local[QENTRY_LEN]; + void *qe; + + if (isp_getrqentry(isp, &nxti, NULL, &qe)) { + isp_prt(isp, ISP_LOGWARN, + "isp_target_putback_atio: Request Queue Overflow"); + /* XXXX */ + isp_complete_ctio(isp, tmd); + return; + } + MEMZERO(local, sizeof (local)); + if (IS_FC(isp)) { + at2_entry_t *at = (at2_entry_t *) local; + at->at_header.rqs_entry_type = RQSTYPE_ATIO2; + at->at_header.rqs_entry_count = 1; + if (FCPARAM(isp)->isp_fwattr & ISP_FW_ATTR_SCCLUN) + at->at_scclun = (uint16_t) tmd->cd_lun; + else + at->at_lun = (uint8_t) tmd->cd_lun; + at->at_status = CT_OK; + at->at_rxid = tmd->cd_tagval; + isp_put_atio2(isp, at, qe); + } else { + at_entry_t *at = (at_entry_t *)local; + at->at_header.rqs_entry_type = RQSTYPE_ATIO; + at->at_header.rqs_entry_count = 1; + at->at_iid = tmd->cd_iid; + at->at_iid |= tmd->cd_bus << 7; + at->at_tgt = tmd->cd_tgt; + at->at_lun = tmd->cd_lun; + at->at_status = CT_OK; + at->at_tag_val = AT_GET_TAG(tmd->cd_tagval); + at->at_handle = AT_GET_HANDLE(tmd->cd_tagval); + isp_put_atio(isp, at, qe); + } + ISP_TDQE(isp, "isp_target_putback_atio", isp->isp_reqidx, qe); + ISP_ADD_REQUEST(isp, nxti); + isp_complete_ctio(isp, tmd); +} + +static void +isp_complete_ctio(struct ispsoftc *isp, tmd_cmd_t *tmd) +{ + if (isp->isp_osinfo.hcb == NULL) { + isp_prt(isp, ISP_LOGWARN, "nobody to tell about completing command"); + MEMZERO(tmd, sizeof (tmd_cmd_t)); + tmd->cd_private = isp->isp_osinfo.tfreelist; + isp->isp_osinfo.tfreelist = tmd; + } else { + tmd->cd_reserved[0] = QOUT_TMD_DONE; + tmd->cd_private = isp->isp_osinfo.pending_t; + isp->isp_osinfo.pending_t = tmd; + } +} + +static int +isp_en_dis_lun(struct ispsoftc *isp, int enable, int bus, int tgt, int lun) +{ + DECLARE_MUTEX_LOCKED(rsem); + u_int16_t rstat; + int rv, enabled, cmd; + + /* + * First, we can't do anything unless we have an upper + * level target driver to route commands to. + */ + if (isp->isp_osinfo.hcb == NULL) { + return (-EINVAL); + } + + /* + * Second, check for sanity of enable argument. + */ + enabled = ((isp->isp_osinfo.tmflags & (1 << bus)) != 0); + if (enable == 0 && enabled == 0) { + return (-EINVAL); + } + + /* + * Third, check to see if we're enabling on fibre channel + * and don't yet have a notion of who the heck we are (no + * loop yet). + */ + if (IS_FC(isp) && !enabled) { + ISP_LOCK_SOFTC(isp); + if ((isp->isp_role & ISP_ROLE_TARGET) == 0) { + isp->isp_role |= ISP_ROLE_TARGET; + if (isp_drain_reset(isp, "lun enables")) { + return (-EIO); + } + } + ISP_UNLK_SOFTC(isp); + SEND_THREAD_EVENT(isp, ISP_THREAD_FC_RESCAN, 1); + } + + /* + * If this is a wildcard target, select our initiator + * id/loop id for use as what we enable as. + */ + + if (tgt == -1) { + if (IS_FC(isp)) { + tgt = ((fcparam *)isp->isp_param)->isp_loopid; + } else { + tgt = ((sdparam *)isp->isp_param)->isp_initiator_id; + } + } + + /* + * Do some sanity checking on lun arguments. + */ + + if (lun < 0 || lun >= (IS_FC(isp)? TM_MAX_LUN_FC : TM_MAX_LUN_SCSI)) { + return (-EINVAL); + } + + /* + * Snag the semaphore on the return state value on enables/disables. + */ + if (down_interruptible(&isp->isp_osinfo.tgt_inisem)) { + return (-EINTR); + } + + if (enable && LUN_BTST(isp, bus, lun)) { + up(&isp->isp_osinfo.tgt_inisem); + return (-EEXIST); + } + if (!enable && !LUN_BTST(isp, bus, lun)) { + up(&isp->isp_osinfo.tgt_inisem); + return (-NODEV); + } + + if (enable && nolunsenabled(isp, bus)) { + int av = (bus << 31) | ENABLE_TARGET_FLAG; + ISP_LOCK_SOFTC(isp); + rv = isp_control(isp, ISPCTL_TOGGLE_TMODE, &av); + ISP_UNLK_SOFTC(isp); + if (rv) { + up(&isp->isp_osinfo.tgt_inisem); + return (-EIO); + } + } + + ISP_LOCK_SOFTC(isp); + isp->isp_osinfo.rsemap = &rsem; + if (enable) { + u_int32_t seq = isp->isp_osinfo.rollinfo++; + int n, ulun = lun; + + cmd = RQSTYPE_ENABLE_LUN; + n = DFLT_INOT_CNT; + if (IS_FC(isp) && lun != 0) { + cmd = RQSTYPE_MODIFY_LUN; + n = 0; + /* + * For SCC firmware, we only deal with setting + * (enabling or modifying) lun 0. + */ + ulun = 0; + } + rstat = LUN_ERR; + if (isp_lun_cmd(isp, cmd, bus, tgt, ulun, DFLT_CMND_CNT, n, seq)) { + isp_prt(isp, ISP_LOGERR, "isp_lun_cmd failed"); + goto out; + } + ISP_UNLK_SOFTC(isp); + down(isp->isp_osinfo.rsemap); + ISP_LOCK_SOFTC(isp); + isp->isp_osinfo.rsemap = NULL; + rstat = isp->isp_osinfo.rstatus; + if (rstat != LUN_OK) { + isp_prt(isp, ISP_LOGERR, "MODIFY/ENABLE LUN returned 0x%x", rstat); + goto out; + } + } else { + int n, ulun = lun; + u_int32_t seq; + + rstat = LUN_ERR; + seq = isp->isp_osinfo.rollinfo++; + cmd = -RQSTYPE_MODIFY_LUN; + + n = DFLT_INOT_CNT; + if (IS_FC(isp) && lun != 0) { + n = 0; + /* + * For SCC firmware, we only deal with setting + * (enabling or modifying) lun 0. + */ + ulun = 0; + } + if (isp_lun_cmd(isp, cmd, bus, tgt, ulun, DFLT_CMND_CNT, n, seq)) { + isp_prt(isp, ISP_LOGERR, "isp_lun_cmd failed"); + goto out; + } + ISP_UNLK_SOFTC(isp); + down(isp->isp_osinfo.rsemap); + ISP_LOCK_SOFTC(isp); + isp->isp_osinfo.rsemap = NULL; + rstat = isp->isp_osinfo.rstatus; + if (rstat != LUN_OK) { + isp_prt(isp, ISP_LOGERR, "MODIFY LUN returned 0x%x", rstat); + goto out; + } + if (IS_FC(isp) && lun) { + goto out; + } + seq = isp->isp_osinfo.rollinfo++; + isp->isp_osinfo.rsemap = &rsem; + + rstat = LUN_ERR; + cmd = -RQSTYPE_ENABLE_LUN; + if (isp_lun_cmd(isp, cmd, bus, tgt, lun, 0, 0, seq)) { + isp_prt(isp, ISP_LOGERR, "isp_lun_cmd failed"); + goto out; + } + ISP_UNLK_SOFTC(isp); + down(isp->isp_osinfo.rsemap); + ISP_LOCK_SOFTC(isp); + isp->isp_osinfo.rsemap = NULL; + rstat = isp->isp_osinfo.rstatus; + if (rstat != LUN_OK) { + isp_prt(isp, ISP_LOGERR, "DISABLE LUN returned 0x%x", rstat); + goto out; + } + } +out: + + if (rstat != LUN_OK) { + isp_prt(isp, ISP_LOGERR, "lun %d %sable failed", lun, + (enable) ? "en" : "dis"); + ISP_UNLK_SOFTC(isp); + up(&isp->isp_osinfo.tgt_inisem); + return (-EIO); + } else { + isp_prt(isp, ISP_LOGINFO, + "lun %d now %sabled for target mode on channel %d", lun, + (enable)? "en" : "dis", bus); + if (enable == 0) { + LUN_BCLR(isp, bus, lun); + if (nolunsenabled(isp, bus)) { + int av = bus << 31; + rv = isp_control(isp, ISPCTL_TOGGLE_TMODE, &av); + if (rv) { + isp_prt(isp, ISP_LOGERR, + "failed to disable target mode on channel %d", bus); + /* but proceed */ + ISP_UNLK_SOFTC(isp); + return (-EIO); + } + isp->isp_osinfo.tmflags &= ~(1 << bus); + isp->isp_role &= ~ISP_ROLE_TARGET; + if (IS_FC(isp)) { + if (isp_drain_reset(isp, "lun disables")) { + return (-EIO); + } + if ((isp->isp_role & ISP_ROLE_INITIATOR) != 0) { + ISP_UNLK_SOFTC(isp); + SEND_THREAD_EVENT(isp, ISP_THREAD_FC_RESCAN, 1); + ISP_LOCK_SOFTC(isp); + } + } + } + } else { + isp->isp_osinfo.tmflags |= (1 << bus); + LUN_BSET(isp, bus, lun); + } + ISP_UNLK_SOFTC(isp); + up(&isp->isp_osinfo.tgt_inisem); + return (0); + } +} +#endif + +#ifdef ISP_PRIVATE_ASYNC +#define ISP_ASYNC isp_async_level1 +#else +#define ISP_ASYNC isp_async +#endif + +int +ISP_ASYNC(struct ispsoftc *isp, ispasync_t cmd, void *arg) +{ + switch (cmd) { + case ISPASYNC_NEW_TGT_PARAMS: + if (IS_SCSI(isp)) { + sdparam *sdp = isp->isp_param; + char *wt; + int mhz, flags, bus, tgt, period; + + tgt = *((int *) arg); + bus = (tgt >> 16) & 0xffff; + tgt &= 0xffff; + + sdp += bus; + flags = sdp->isp_devparam[tgt].actv_flags; + period = sdp->isp_devparam[tgt].actv_period; + if ((flags & DPARM_SYNC) && period && + (sdp->isp_devparam[tgt].actv_offset) != 0) { + if (sdp->isp_lvdmode || period < 0xc) { + switch (period) { + case 0x9: + mhz = 80; + break; + case 0xa: + mhz = 40; + break; + case 0xb: + mhz = 33; + break; + case 0xc: + mhz = 25; + break; + default: + mhz = 1000 / (period * 4); + break; + } + } else { + mhz = 1000 / (period * 4); + } + } else { + mhz = 0; + } + switch (flags & (DPARM_WIDE|DPARM_TQING)) { + case DPARM_WIDE: + wt = ", 16 bit wide"; + break; + case DPARM_TQING: + wt = ", Tagged Queueing Enabled"; + break; + case DPARM_WIDE|DPARM_TQING: + wt = ", 16 bit wide, Tagged Queueing Enabled"; + break; + default: + wt = " "; + break; + } + if (mhz) { + isp_prt(isp, ISP_LOGINFO, + "Channel %d Target %d at %dMHz Max Offset %d%s", + bus, tgt, mhz, sdp->isp_devparam[tgt].actv_offset, wt); + } else { + isp_prt(isp, ISP_LOGINFO, "Channel %d Target %d Async Mode%s", + bus, tgt, wt); + } + } + break; + case ISPASYNC_LIP: + isp_prt(isp, ISP_LOGINFO, "LIP Received"); + break; + case ISPASYNC_LOOP_RESET: + isp_prt(isp, ISP_LOGINFO, "Loop Reset Received"); + break; + case ISPASYNC_BUS_RESET: + isp_prt(isp, ISP_LOGINFO, "SCSI bus %d reset detected", *((int *) arg)); + break; + case ISPASYNC_LOOP_DOWN: + isp_prt(isp, ISP_LOGINFO, "Loop DOWN"); + break; + case ISPASYNC_LOOP_UP: + isp_prt(isp, ISP_LOGINFO, "Loop UP"); + break; + case ISPASYNC_PROMENADE: + { + fcparam *fcp = isp->isp_param; + struct lportdb *lp; + int tgt; + + tgt = *((int *) arg); + lp = &fcp->portdb[tgt]; + + if (lp->valid) { + isp_prt(isp, ISP_LOGINFO, + "ID %d (Loop 0x%x) Port WWN 0x%08x%08x @ 0x%x arrived, role %s", + tgt, lp->loopid, (unsigned int) (lp->port_wwn >> 32), + (unsigned int) (lp->port_wwn & 0xffffffff), lp->portid, + class3_roles[fcp->portdb[tgt].roles]); + } else { + isp_prt(isp, ISP_LOGINFO, + "ID %d (Loop 0x%x) Port WWN 0x%08x%08x @ 0x%x departed", tgt, + lp->loopid, (unsigned int) (lp->port_wwn >> 32), + (unsigned int) (lp->port_wwn & 0xffffffff), lp->portid); +#ifdef DEVICE_POLICY_IS_FLUID + MEMZERO((void *) lp, sizeof (*lp)); +#endif + } + break; + } + case ISPASYNC_CHANGE_NOTIFY: + if (arg == ISPASYNC_CHANGE_PDB) { + isp_prt(isp, ISP_LOGINFO, + "Port Database Changed"); + } else if (arg == ISPASYNC_CHANGE_SNS) { + isp_prt(isp, ISP_LOGINFO, + "Name Server Database Changed"); + } + SEND_THREAD_EVENT(isp, ISP_THREAD_FC_RESCAN, 0); + break; + case ISPASYNC_FABRIC_DEV: + { + int target, base, lim; + fcparam *fcp = isp->isp_param; + struct lportdb *lp = NULL; + struct lportdb *clp = (struct lportdb *) arg; + char *pt; + + switch (clp->port_type) { + case 1: + pt = " N_Port"; + break; + case 2: + pt = " NL_Port"; + break; + case 3: + pt = "F/NL_Port"; + break; + case 0x7f: + pt = " Nx_Port"; + break; + case 0x81: + pt = " F_port"; + break; + case 0x82: + pt = " FL_Port"; + break; + case 0x84: + pt = " E_port"; + break; + default: + pt = " "; + break; + } + + isp_prt(isp, ISP_LOGINFO, + "%s Fabric Device @ PortID 0x%x", pt, clp->portid); + + /* + * If we don't have an initiator role we bail. + * + * We just use ISPASYNC_FABRIC_DEV for announcement purposes. + */ + + if ((isp->isp_role & ISP_ROLE_INITIATOR) == 0) { + break; + } + + /* + * Is this entry for us? If so, we bail. + */ + + if (fcp->isp_portid == clp->portid) { + break; + } + + /* + * Else, the default policy is to find room for it in + * our local port database. Later, when we execute + * the call to isp_pdb_sync either this newly arrived + * or already logged in device will be (re)announced. + */ + + if (fcp->isp_topo == TOPO_FL_PORT) + base = FC_SNS_ID+1; + else + base = 0; + + if (fcp->isp_topo == TOPO_N_PORT) + lim = 1; + else + lim = MAX_FC_TARG; + + /* + * Is it already in our list? + */ + for (target = base; target < lim; target++) { + if (target >= FL_PORT_ID && target <= FC_SNS_ID) { + continue; + } + lp = &fcp->portdb[target]; + if (lp->port_wwn == clp->port_wwn && + lp->node_wwn == clp->node_wwn) { + lp->fabric_dev = 1; + /* + * Propagate possibly new port id. + */ + lp->portid = clp->portid; + break; + } + } + if (target < lim) { + break; + } + for (target = base; target < lim; target++) { + if (target >= FL_PORT_ID && target <= FC_SNS_ID) { + continue; + } + lp = &fcp->portdb[target]; + if (lp->port_wwn == 0) { + break; + } + } + if (target == lim) { + isp_prt(isp, ISP_LOGWARN, + "out of space for fabric devices"); + break; + } + lp->port_type = clp->port_type; + lp->fc4_type = clp->fc4_type; + lp->node_wwn = clp->node_wwn; + lp->port_wwn = clp->port_wwn; + lp->portid = clp->portid; + lp->fabric_dev = 1; + break; + } +#ifdef LINUX_ISP_TARGET_MODE + case ISPASYNC_TARGET_MESSAGE: + { + tmd_msg_t *mp = arg; + isp_prt(isp, ISP_LOGTDEBUG2, + "bus %d iid %d tgt %d lun %d ttype %x tval %x msg[0]=%x", + mp->nt_bus, (int) mp->nt_iid, (int) mp->nt_tgt, (int) mp->nt_lun, + mp->nt_tagtype, mp->nt_tagval, mp->nt_msg[0]); + break; + } + case ISPASYNC_TARGET_EVENT: + { + tmd_event_t *ep = arg; + isp_prt(isp, ISP_LOGTDEBUG2, + "bus %d event code 0x%x", ep->ev_bus, ep->ev_event); + break; + } + case ISPASYNC_TARGET_ACTION: + switch (((isphdr_t *)arg)->rqs_entry_type) { + default: + isp_prt(isp, ISP_LOGWARN, "event 0x%x for unhandled target action", + ((isphdr_t *)arg)->rqs_entry_type); + break; + case RQSTYPE_ATIO: + (void) isp_handle_platform_atio(isp, (at_entry_t *) arg); + break; + case RQSTYPE_ATIO2: + (void) isp_handle_platform_atio2(isp, (at2_entry_t *)arg); + break; + case RQSTYPE_CTIO2: + case RQSTYPE_CTIO: + (void) isp_handle_platform_ctio(isp, arg); + break; + case RQSTYPE_ENABLE_LUN: + case RQSTYPE_MODIFY_LUN: + isp->isp_osinfo.rstatus = ((lun_entry_t *)arg)->le_status; + if (isp->isp_osinfo.rsemap) { + up(isp->isp_osinfo.rsemap); + } + break; + } + break; +#endif + case ISPASYNC_UNHANDLED_RESPONSE: + break; + case ISPASYNC_FW_CRASH: + { + u_int16_t mbox1, mbox6; + mbox1 = ISP_READ(isp, OUTMAILBOX1); + if (IS_DUALBUS(isp)) { + mbox6 = ISP_READ(isp, OUTMAILBOX6); + } else { + mbox6 = 0; + } + isp_prt(isp, ISP_LOGERR, + "Internal F/W Error on bus %d @ RISC Address 0x%x", mbox6, mbox1); +#ifdef ISP_FW_CRASH_DUMP + if (IS_FC(isp)) { + isp->isp_blocked = 1; + SEND_THREAD_EVENT(isp, ISP_THREAD_FW_CRASH_DUMP, 0); + } else { + isp_reinit(isp); + isp_async(isp, ISPASYNC_FW_RESTARTED, NULL); + } +#endif + break; + } + case ISPASYNC_FW_RESTARTED: + { + if (IS_FC(isp)) { + SEND_THREAD_EVENT(isp, ISP_THREAD_FC_RESCAN, 0); + } + break; + } + default: + return (-1); + } + return (0); +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#include "sd.h" +int +isplinux_biosparam(Disk *disk, kdev_t n, int ip[]) +{ + int size = disk->capacity; + ip[0] = 64; + ip[1] = 32; + ip[2] = size >> 11; + if (ip[2] > 1024) { + ip[0] = 255; + ip[1] = 63; + ip[2] = size / (ip[0] * ip[1]); + } + return (0); +} + +/* + * Set the queue depth for this device. + */ + +void +isplinux_sqd(struct Scsi_Host *host, Scsi_Device *devs) +{ + while (devs) { + if (devs->host == host && devs->tagged_supported == 0) { + /* + * If this device doesn't support tagged operations, don't waste + * queue space for it, even if it has multiple luns. + */ + devs->queue_depth = 2; + } else if (devs->host == host) { + int depth = 2; + struct ispsoftc *isp = (struct ispsoftc *) host->hostdata; + + if (IS_SCSI(isp)) { + sdparam *sdp = isp->isp_param; + sdp += devs->channel; + depth = sdp->isp_devparam[devs->id].exc_throttle; + } else { + depth = FCPARAM(isp)->isp_execthrottle; + } + if (isp_throttle) { + /* + * This limit is due to the size of devs->queue_depth + */ + depth = (unsigned char) min(isp_throttle, 255);; + } + if (depth < 4) { + depth = 4; + } + devs->queue_depth = depth; + } + devs = devs->next; + } +} + +#else +int +isplinux_biosparam(struct scsi_device *sdev, struct block_device *n, + sector_t capacity, int ip[]) +{ + int size = capacity; + ip[0] = 64; + ip[1] = 32; + ip[2] = size >> 11; + if (ip[2] > 1024) { + ip[0] = 255; + ip[1] = 63; + ip[2] = size / (ip[0] * ip[1]); + } + return (0); +} + +static int +isplinux_slave_configure(Scsi_Device * device) +{ + if (device->tagged_supported) { + /* + * FIX LATER + */ + scsi_adjust_queue_depth(device, MSG_ORDERED_TAG, 63); + } + return 0; +} +#endif + +/* + * Periodic watchdog timer.. the main purpose here is to restart + * commands that were pegged on resources, etc... + */ +void +isplinux_timer(unsigned long arg) +{ + Scsi_Cmnd *Cmnd; + struct ispsoftc *isp = (struct ispsoftc *) arg; + + ISP_ILOCK_SOFTC(isp); + if (IS_FC(isp)) { + int rql; + if (isp->isp_role & ISP_ROLE_INITIATOR) + rql = LOOP_READY; + else + rql = LOOP_LSCAN_DONE; + if (isp->isp_fcrswdog || FCPARAM(isp)->isp_fwstate != FW_READY || + FCPARAM(isp)->isp_loopstate < rql) { + isp->isp_fcrswdog = 0; + if (isp->isp_deadloop == 0 && isp->isp_role != ISP_ROLE_NONE) { + SEND_THREAD_EVENT(isp, ISP_THREAD_FC_RESCAN, 0); + } + } + } + isplinux_runwaitq(isp); + if ((Cmnd = isp->isp_osinfo.dqnext) != NULL) { + isp->isp_osinfo.dqnext = isp->isp_osinfo.dqtail = NULL; + } + if (isp->dogactive) { + isp->isp_osinfo.timer.expires = jiffies + ISP_WATCH_TIME; + add_timer(&isp->isp_osinfo.timer); + } + ISP_IUNLK_SOFTC(isp); + if (Cmnd) { + ISP_LOCK_SCSI_DONE(isp); + while (Cmnd) { + Scsi_Cmnd *f = (Scsi_Cmnd *) Cmnd->host_scribble; + Cmnd->host_scribble = NULL; + /* + * Get around silliness in midlayer. + */ + if (host_byte(Cmnd->result) == DID_RESET) { + Cmnd->flags |= IS_RESETTING; + } + (*Cmnd->scsi_done)(Cmnd); + Cmnd = f; + } + ISP_UNLK_SCSI_DONE(isp); + } +} + +void +isplinux_mbtimer(unsigned long arg) +{ + struct ispsoftc *isp = (struct ispsoftc *) arg; + ISP_ILOCK_SOFTC(isp); + if (isp->mbox_waiting) { + isp->mbox_waiting = 0; + up(&isp->mbox_c_sem); + } + ISP_IUNLK_SOFTC(isp); +} + +irqreturn_t +isplinux_intr(int irq, void *arg, struct pt_regs *pt) +{ + struct ispsoftc *isp = arg; + u_int16_t isr, sema, mbox; + Scsi_Cmnd *Cmnd; + + ISP_ILOCK_SOFTC(isp); + isp->isp_intcnt++; + if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { + isp->isp_intbogus++; + ISP_IUNLK_SOFTC(isp); + return IRQ_NONE; + } + isp_intr(isp, isr, sema, mbox); + isplinux_runwaitq(isp); + if ((Cmnd = isp->isp_osinfo.dqnext) != NULL) { + isp->isp_osinfo.dqnext = isp->isp_osinfo.dqtail = NULL; + } +#ifdef LINUX_ISP_TARGET_MODE + if (isp->isp_osinfo.pending_t) { + struct tmd_cmd *tmd = isp->isp_osinfo.pending_t; + isp->isp_osinfo.pending_t = NULL; + ISP_IUNLK_SOFTC(isp); + do { + struct tmd_cmd *next = tmd->cd_private; + tmd->cd_private = isp->isp_osinfo.hcb_token; + (*isp->isp_osinfo.hcb)(tmd->cd_reserved[0], tmd); + tmd = next; + } while (tmd != NULL); + } else { + ISP_IUNLK_SOFTC(isp); + } +#else + ISP_IUNLK_SOFTC(isp); +#endif + if (Cmnd) { + ISP_LOCK_SCSI_DONE(isp); + while (Cmnd) { + Scsi_Cmnd *f = (Scsi_Cmnd *) Cmnd->host_scribble; + Cmnd->host_scribble = NULL; + /* + * Get around silliness in midlayer. + */ + if (host_byte(Cmnd->result) == DID_RESET) { + Cmnd->flags |= IS_RESETTING; + } + (*Cmnd->scsi_done)(Cmnd); + Cmnd = f; + } + ISP_UNLK_SCSI_DONE(isp); + } + return IRQ_HANDLED; +} + +static INLINE int +isp_parse_rolearg(struct ispsoftc *isp, char *roles) +{ + char *role = roles; + + while (role && *role) { + unsigned int id; + char *eqtok, *commatok, *p, *q; + + eqtok = role; + eqtok = strchr(role, '='); + if (eqtok == NULL) + break; + *eqtok = 0; + commatok = strchr(eqtok+1, ','); + if (commatok) + *commatok = 0; + if (strncmp(role, "0x", 2) == 0) + q = role + 2; + else + q = role; + id = simple_strtoul(q, &p, 16); + *eqtok = '='; + if (p != q && id == isp->isp_osinfo.device_id) { + p = eqtok + 1; + if (strcmp(p, "none") == 0) { + if (commatok) { + *commatok = ','; + } + return (ISP_ROLE_NONE); + } + if (strcmp(p, "target") == 0) { + if (commatok) { + *commatok = ','; + } + return (ISP_ROLE_TARGET); + } + if (strcmp(p, "initiator") == 0) { + if (commatok) { + *commatok = ','; + } + return (ISP_ROLE_INITIATOR); + } + if (strcmp(p, "both") == 0) { + if (commatok) { + *commatok = ','; + } + return (ISP_ROLE_BOTH); + } + break; + } + if (commatok) { + role = commatok+1; + *commatok = ','; + } else { + break; + } + } + return (ISP_DEFAULT_ROLES); +} + +static INLINE u_int64_t +isp_parse_wwnarg(struct ispsoftc *isp, char *wwns) +{ + char *wwnt = wwns; + u_int64_t wwn = 0; + + while (wwn == 0 && wwnt && *wwnt) { + unsigned int id; + char *eqtok, *commatok, *p, *q; + + eqtok = wwnt; + eqtok = strchr(wwnt, '='); + if (eqtok == NULL) + break; + *eqtok = 0; + commatok = strchr(eqtok+1, ','); + if (commatok) + *commatok = 0; + if (strncmp(wwnt, "0x", 2) == 0) + q = wwnt + 2; + else + q = wwnt; + id = simple_strtoul(q, &p, 16); + if (p != q && id == isp->isp_osinfo.device_id) { + unsigned long t, t2; + p = eqtok + 1; + while (*p) { + p++; + } + p -= 8; + if (p > eqtok + 1) { + char *q; + char c; + q = p; + t = simple_strtoul(p, &q, 16); + c = *p; + *p = 0; + t2 = simple_strtoul(eqtok+1, NULL, 16); + *p = c; + } else { + t = simple_strtoul(eqtok+1, NULL, 16); + t2 = 0; + } + wwn = (((u_int64_t) t2) << 32) | (u_int64_t) t; + } + *eqtok = '='; + if (commatok) { + wwnt = commatok+1; + *commatok = ','; + } else { + break; + } + } + return (wwn); +} + +void +isplinux_common_init(struct ispsoftc *isp) +{ + /* + * Set up config options, etc... + */ + if (isp_debug) { + isp->isp_dblev = isp_debug; + } else { + isp->isp_dblev = ISP_LOGCONFIG|ISP_LOGWARN|ISP_LOGERR; + } + + if (isp_nofwreload & (1 << isp->isp_unit)) { + isp->isp_confopts |= ISP_CFG_NORELOAD; + } + if (isp_nonvram & (1 << isp->isp_unit)) { + isp->isp_confopts |= ISP_CFG_NONVRAM; + } + if (IS_FC(isp)) { + if (isp_fcduplex & (1 << isp->isp_unit)) { + isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; + } + isp->isp_defwwpn = isp_parse_wwnarg(isp, isp_wwpns); + if (isp->isp_defwwpn == 0) { + isp->isp_defwwpn = (u_int64_t) 0x400000007F7F7F01; + } else { + isp->isp_confopts |= ISP_CFG_OWNWWPN; + } + isp->isp_defwwnn = isp_parse_wwnarg(isp, isp_wwnns); + if (isp->isp_defwwnn == 0) { + isp->isp_defwwnn = (u_int64_t) 0x400000007F7F7F02; + } else { + isp->isp_confopts |= ISP_CFG_OWNWWNN; + } + isp->isp_osinfo.host->max_id = MAX_FC_TARG; + if (IS_2200(isp) || IS_2300(isp)) { + if (isp_nport_only & (1 << isp->isp_unit)) { + isp->isp_confopts |= ISP_CFG_NPORT_ONLY; + } else if (isp_loop_only & (1 << isp->isp_unit)) { + isp->isp_confopts |= ISP_CFG_LPORT_ONLY; + } else { + isp->isp_confopts |= ISP_CFG_NPORT; + } + } + isp->isp_osinfo.host->this_id = MAX_FC_TARG+1; +#ifdef ISP_FW_CRASH_DUMP + if (IS_2200(isp)) + FCPARAM(isp)->isp_dump_data = vmalloc(QLA2200_RISC_IMAGE_DUMP_SIZE); + else if (IS_23XX(isp)) + FCPARAM(isp)->isp_dump_data = vmalloc(QLA2300_RISC_IMAGE_DUMP_SIZE); + if (FCPARAM(isp)->isp_dump_data) { + isp_prt(isp, ISP_LOGCONFIG, "f/w crash dump area allocated"); + FCPARAM(isp)->isp_dump_data[0] = 0; + } +#endif + if (isp_default_frame_size) { + if (isp_default_frame_size != 512 && + isp_default_frame_size != 1024 && + isp_default_frame_size != 2048) { + isp_prt(isp, ISP_LOGERR, + "bad frame size (%d), defaulting to (%d)", + isp_default_frame_size, ICB_DFLT_FRMLEN); + isp_default_frame_size = 0; + } + } + if (isp_default_frame_size) { + isp->isp_confopts |= ISP_CFG_OWNFSZ; + isp->isp_osinfo.storep->fibre_scsi.default_frame_size = + isp_default_frame_size; + } else { + isp->isp_osinfo.storep->fibre_scsi.default_frame_size = + isp_default_frame_size = ICB_DFLT_FRMLEN; + } + if (isp_default_exec_throttle) { + if (isp_default_exec_throttle < 16 || + isp_default_exec_throttle > 255) { + isp_prt(isp, ISP_LOGERR, + "bad execution throttle size (%d), defaulting to (%d)", + isp_default_exec_throttle, ICB_DFLT_THROTTLE); + isp_default_exec_throttle = 0; + } + } + if (isp_default_exec_throttle) { + isp->isp_confopts |= ISP_CFG_OWNEXCTHROTTLE; + isp->isp_osinfo.storep->fibre_scsi.default_exec_throttle = + isp_default_exec_throttle; + } else { + isp->isp_osinfo.storep->fibre_scsi.default_exec_throttle = + ICB_DFLT_THROTTLE; + } + } else { + isp->isp_osinfo.host->max_id = MAX_TARGETS; + isp->isp_osinfo.host->this_id = 7; /* temp default */ + } + isp->isp_role = isp_parse_rolearg(isp, isp_roles); + + + /* + * Initialize locks + */ + ISP_LOCK_INIT(isp); + ISP_TLOCK_INIT(isp); + sema_init(&isp->mbox_sem, 1); + sema_init(&isp->mbox_c_sem, 0); + sema_init(&isp->fcs_sem, 1); + + /* + * Start watchdog timer + */ + ISP_LOCK_SOFTC(isp); + init_timer(&isp->isp_osinfo.timer); + isp->isp_osinfo.timer.data = (unsigned long) isp; + isp->isp_osinfo.timer.function = isplinux_timer; + isp->isp_osinfo.timer.expires = jiffies + ISP_WATCH_TIME; + add_timer(&isp->isp_osinfo.timer); + isp->dogactive = 1; + if (IS_FC(isp)) { + DECLARE_MUTEX_LOCKED(sem); + ISP_UNLK_SOFTC(isp); + isp->isp_osinfo.task_ctl_sem = &sem; + kernel_thread(isp_task_thread, isp, 0); + down(&sem); + isp->isp_osinfo.task_ctl_sem = NULL; + ISP_LOCK_SOFTC(isp); + } + isplinux_reinit(isp); +#ifdef LINUX_ISP_TARGET_MODE + sema_init(&isp->isp_osinfo.tgt_inisem, 1); +#endif +#ifdef ISP_TARGET_MODE + isp_attach_target(isp); +#endif + ISP_UNLK_SOFTC(isp); +} + +void +isplinux_reinit(struct ispsoftc *isp) +{ + int maxluns = isp_maxluns; + isp_reset(isp); + if (isp->isp_state != ISP_RESETSTATE) { + isp_prt(isp, ISP_LOGERR, "failed to enter RESET state"); + return; + } + /* + * Until the midlayer starts using REPORT LUNS to dertermine how many + * luns there are for SCSI-3 devices and sets a reasonable limit for + * SCSI-2 devices, we'll follow this ruleset: + * + * If our isp_maxluns parameter is unchanged from its default, we + * limit ourselves to 8 luns for parallel SCSI, 256 for FC-SCSI. + * + * If somebody has set isp_maxluns away from the fefault, we follow that. + * + * We filter any value through the HBA maximum + */ + if (isp_maxluns == 8) { + if (IS_FC(isp)) { + maxluns = 256; + } + } + isp->isp_osinfo.host->max_lun = min(maxluns, ISP_MAX_LUNS(isp)); + isp_init(isp); + if (isp->isp_role == ISP_ROLE_NONE) { + return; + } + if (isp->isp_state != ISP_INITSTATE) { + isp_prt(isp, ISP_LOGERR, "failed to enter INIT state"); + return; + } + isp->isp_state = ISP_RUNSTATE; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + isp->isp_osinfo.host->can_queue = isp->isp_maxcmds; +#else + isp->isp_osinfo.host->can_queue = min(255, isp->isp_maxcmds); +#endif + if (isp->isp_osinfo.host->can_queue == 0) + isp->isp_osinfo.host->can_queue = 1; + + if (IS_FC(isp)) { + isp->isp_osinfo.host->this_id = MAX_FC_TARG; + /* + * This is *not* the same as execution throttle- that is set + * in isplinux_sqd and is per-device. + * + * What we try and do here is take how much we can queue at + * a given time and spread it, reasonably, over all the luns + * we expect to run at a time. + */ + if (isp_cmd_per_lun) { + isp->isp_osinfo.host->cmd_per_lun = isp_cmd_per_lun; + } else { + /* + * JAWAG. + */ + isp->isp_osinfo.host->cmd_per_lun = isp->isp_maxcmds >> 3; + } + + /* + * We seem to need a bit of settle time. + */ + USEC_DELAY(1 * 1000000); + } else { + int bus; + + if (isp_cmd_per_lun) { + isp->isp_osinfo.host->cmd_per_lun = isp_cmd_per_lun; + } else { + /* + * Maximum total commands spread over either 8 targets, + * or 4 targets, 2 luns, etc. + */ + isp->isp_osinfo.host->cmd_per_lun = isp->isp_maxcmds >> 3; + } + + /* + * No way to give different ID's for the second bus. + */ + isp->isp_osinfo.host->this_id = SDPARAM(isp)->isp_initiator_id; + bus = 0; + (void) isp_control(isp, ISPCTL_RESET_BUS, &bus); + if (IS_DUALBUS(isp)) { + bus = 1; + (void) isp_control(isp, ISPCTL_RESET_BUS, &bus); + } + /* + * Bus Reset delay handled by firmware. + */ + } +} + +int +isp_drain_reset(struct ispsoftc *isp, char *msg) +{ + isp->isp_blocked = 1; + /* + * Drain active commands. + */ + if (isp_drain(isp, msg)) { + isp->isp_failed = 1; + isp->isp_blocked = 0; + return (-1); + } + isp_reinit(isp); + if ((isp->isp_role == ISP_ROLE_NONE && isp->isp_state < ISP_RESETSTATE) || + (isp->isp_role != ISP_ROLE_NONE && isp->isp_state < ISP_RUNSTATE)) { + isp->isp_blocked = 0; + return (-1); + } + isp->isp_failed = 0; + isp->isp_blocked = 0; + return (0); +} + +int +isp_drain(struct ispsoftc *isp, char *whom) +{ + int nslept; + + if (isp->isp_nactive == 0) + return (0); + + isp->isp_draining = 1; + nslept = 0; + isp_prt(isp, ISP_LOGDEBUG0, "draining %d commands", isp->isp_nactive); + while (isp->isp_nactive) { + USEC_SLEEP(isp, 100000); /* drops lock */ + if (++nslept >= (60 * 10)) { /* 60 seconds */ + isp_prt(isp, ISP_LOGERR, "%s: command drain timed out", whom); + isp->isp_draining = 0; + return (-1); + } + } + isp_prt(isp, ISP_LOGDEBUG0, "done draining commands"); + isp->isp_draining = 0; + isplinux_runwaitq(isp); + return (0); +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +#define ISP_THREAD_CAN_EXIT isp->isp_host->loaded_as_module +#else +#define ISP_THREAD_CAN_EXIT 0 +#endif + +static int +isp_task_thread(void *arg) +{ + DECLARE_MUTEX_LOCKED(thread_sleep_semaphore); + struct ispsoftc *isp = arg; + unsigned long flags; + int action, nactions, exit_thread = 0; + isp_thread_action_t curactions[MAX_THREAD_ACTION]; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + /* XXX: Not really sure why the 2.5.X changes do this */ + if (ISP_THREAD_CAN_EXIT) { + siginitsetinv(¤t->blocked, sigmask(SIGHUP)); + } else { + siginitsetinv(¤t->blocked, 0); + } + lock_kernel(); + daemonize(); + sprintf(current->comm, "isp_thrd%d", isp->isp_unit); +#else + lock_kernel(); + daemonize("isp_thrd%d", isp->isp_unit); +#endif + isp->isp_osinfo.task_thread = current; + isp->isp_osinfo.task_request = &thread_sleep_semaphore; + unlock_kernel(); + + if (isp->isp_osinfo.task_ctl_sem) { + up(isp->isp_osinfo.task_ctl_sem); + } + isp_prt(isp, ISP_LOGDEBUG1, "isp_task_thread starting"); + + while (exit_thread == 0) { + isp_prt(isp, ISP_LOGDEBUG1, "isp_task_thread sleeping"); + down_interruptible(&thread_sleep_semaphore); + if (ISP_THREAD_CAN_EXIT) { + if (signal_pending(current)) + break; + } + isp_prt(isp, ISP_LOGDEBUG1, "isp_task_thread running"); + + spin_lock_irqsave(&isp->isp_osinfo.tlock, flags); + nactions = isp->isp_osinfo.nt_actions; + isp->isp_osinfo.nt_actions = 0; + for (action = 0; action < nactions; action++) { + curactions[action] = isp->isp_osinfo.t_actions[action]; + isp->isp_osinfo.t_actions[action].thread_action = 0; + isp->isp_osinfo.t_actions[action].thread_waiter = 0; + } + spin_unlock_irqrestore(&isp->isp_osinfo.tlock, flags); + + for (action = 0; action < nactions; action++) { + isp_thread_action_t *tap = &curactions[action]; + isp_prt(isp, ISP_LOGDEBUG1, "isp_task_thread[%d]: action %d (%p)", + action, tap->thread_action, tap->thread_waiter); + switch (tap->thread_action) { + case ISP_THREAD_NIL: + break; +#ifdef ISP_FW_CRASH_DUMP + case ISP_THREAD_FW_CRASH_DUMP: + ISP_LOCKU_SOFTC(isp); + FCPARAM(isp)->isp_fwstate = FW_CONFIG_WAIT; + FCPARAM(isp)->isp_loopstate = LOOP_NIL; + isp_fw_dump(isp); + SEND_THREAD_EVENT(isp, ISP_THREAD_REINIT, 0); + ISP_UNLKU_SOFTC(isp); + break; +#endif + case ISP_THREAD_REINIT: + { + int level; + ISP_LOCKU_SOFTC(isp); + level = (isp->isp_role == ISP_ROLE_NONE)? + ISP_RESETSTATE : ISP_INITSTATE; + isp_reinit(isp); + if (isp->isp_state >= level) { + isp_async(isp, ISPASYNC_FW_RESTARTED, NULL); + } else { + SEND_THREAD_EVENT(isp, ISP_THREAD_REINIT, 0); + } + ISP_UNLKU_SOFTC(isp); + break; + } + case ISP_THREAD_FC_RESCAN: + ISP_LOCKU_SOFTC(isp); + if (isp_fc_runstate(isp, 250000) == 0) { + isp->isp_deadloop = 0; + isp->isp_downcnt = 0; + isp->isp_fcrspend = 0; + isp->isp_blocked = 0; + isplinux_runwaitq(isp); + } else { + /* + * Try again in a little while. + */ + isp->isp_fcrspend = 0; + if (++isp->isp_downcnt == isp_deadloop_time) { + isp_prt(isp, ISP_LOGWARN, "assuming loop is dead"); + FCPARAM(isp)->loop_seen_once = 0; + isp->isp_deadloop = 1; + isp->isp_downcnt = 0; + isp->isp_blocked = 0; /* unblock anyway */ + isplinux_flushwaitq(isp); + } else { + isp->isp_fcrswdog = 1; + } + } + ISP_UNLKU_SOFTC(isp); + break; + case ISP_THREAD_EXIT: + if (ISP_THREAD_CAN_EXIT) { + exit_thread = 1; + } + break; + default: + break; + } + if (tap->thread_waiter) { + isp_prt(isp, ISP_LOGDEBUG1, "isp_task_thread signalling %p", + tap->thread_waiter); + up(tap->thread_waiter); + } + } + } + isp_prt(isp, ISP_LOGDEBUG1, "isp_task_thread exiting"); + isp->isp_osinfo.task_request = NULL; + return (0); +} + +void +isp_prt(struct ispsoftc *isp, int level, const char *fmt, ...) +{ + char buf[256]; + char *prefl; + va_list ap; + + if (level != ISP_LOGALL && (level & isp->isp_dblev) == 0) { + return; + } + if (level & ISP_LOGERR) { + prefl = KERN_ERR "%s: "; + } else if (level & ISP_LOGWARN) { + prefl = KERN_WARNING "%s: "; + } else if (level & ISP_LOGINFO) { + prefl = KERN_NOTICE "%s: "; + } else if (level & ISP_LOGCONFIG) { + prefl = KERN_INFO "%s: "; + } else { + prefl = "%s: "; + } + printk(prefl, isp->isp_name); + va_start(ap, fmt); + vsprintf(buf, fmt, ap); + va_end(ap); + printk("%s\n", buf); +} + +char * +isp_snprintf(char *buf, size_t amt, const char *fmt, ...) +{ + va_list ap; + ARGSUSED(amt); + va_start(ap, fmt); + (void) vsprintf(buf, fmt, ap); + va_end(ap); + return (buf); +} + +#ifdef MODULE +#ifndef ISP_LICENSE +#define ISP_LICENSE "Dual BSD/GPL" +#endif +#ifdef MODULE_LICENSE +MODULE_LICENSE( ISP_LICENSE ); +#endif +MODULE_PARM(isp_debug, "i"); +MODULE_PARM(isp_disable, "i"); +MODULE_PARM(isp_nonvram, "i"); +MODULE_PARM(isp_nofwreload, "i"); +MODULE_PARM(isp_maxluns, "i"); +MODULE_PARM(isp_throttle, "i"); +MODULE_PARM(isp_cmd_per_lun, "i"); +MODULE_PARM(isp_roles, "s"); +MODULE_PARM(isp_fcduplex, "i"); +MODULE_PARM(isp_wwpns, "s"); +MODULE_PARM(isp_wwnns, "s"); +MODULE_PARM(isp_nport_only, "i"); +MODULE_PARM(isp_loop_only, "i"); +MODULE_PARM(isp_deadloop_time, "i"); +MODULE_PARM(isp_xtime, "i"); +MODULE_PARM(isp_default_frame_size, "i"); +MODULE_PARM(isp_default_exec_throttle, "i"); +#endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) || defined(MODULE) +Scsi_Host_Template driver_template = QLOGICISP; +#include "scsi_module.c" +#endif +/* + * mode: c + * Local variables: + * c-indent-level: 4 + * c-brace-imaginary-offset: 0 + * c-brace-offset: -4 + * c-argdecl-indent: 4 + * c-label-offset: -4 + * c-continued-statement-offset: 4 + * c-continued-brace-offset: 0 + * End: + */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/isp_linux.h 2003-06-27 15:56:37.000000000 -0700 @@ -0,0 +1,970 @@ +/* + * Qlogic ISP SCSI Host Adapter Linux Wrapper Definitions + *--------------------------------------- + * Copyright (c) 1998, 1999, 2000, 2001 by Matthew Jacob + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification, immediately at the beginning of the file. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * the GNU Public License ("GPL"). + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Matthew Jacob + * Feral Software + * PMB #825 + * 5214-F Diamond Hts Blvd + * San Francisco, CA, 94131 + * mjacob@feral.com + */ + +#ifndef _ISP_LINUX_H +#define _ISP_LINUX_H + +#ifndef ISP_MODULE +#define __NO_VERSION__ +#endif +#ifdef LINUX_ISP_TARGET_MODE +#define EXPORT_SYMTAB +#endif + +#include +#ifndef KERNEL_VERSION +#define KERNEL_VERSION(v,p,s) (((v)<<16)+(p<<8)+s) +#endif +#define _KVC KERNEL_VERSION + +#if LINUX_VERSION_CODE <= _KVC(2,2,0) +#error "Linux 2.0 and 2.1 kernels are not supported anymore" +#endif +#if LINUX_VERSION_CODE >= _KVC(2,3,0) && LINUX_VERSION_CODE < _KVC(2,4,0) +#error "Linux 2.3 kernels are not supported" +#endif + +#ifndef UNUSED_PARAMETER +#define UNUSED_PARAMETER(x) (void) x +#endif + +#include +#ifdef CONFIG_SMP +#define __SMP__ 1 +#endif + + +/* + * Be nice and get ourselves out of the way of other drivers. + * Note that if all the other drivers are there, then the only + * thing we'd attach to that they wouldn't would be the obsolete + * and unavailable 1240 or the 23XX. + */ +#ifdef CONFIG_SCSI_QLOGIC_ISP +#define ISP_DISABLE_1020_SUPPORT 1 +#endif +#ifdef CONFIG_SCSI_QLOGIC_FC +#define ISP_DISABLE_2100_SUPPORT 1 +#define ISP_DISABLE_2200_SUPPORT 1 +#endif +#ifdef CONFIG_SCSI_QLOGIC_1280 +#define ISP_DISABLE_1080_SUPPORT 1 +#define ISP_DISABLE_12160_SUPPORT 1 +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) +#include +#include +#else +#include +#endif +#include +#include +#include +#include "scsi.h" +#include "hosts.h" + +/* + * These bits and pieces of keeping track of Linux versions + * and some of the various foo items for locking/unlocking + * gratefully borrowed from (amongst others) Doug Ledford + * and Gerard Roudier. + */ + +#define PWRB(p, o, r) pci_write_config_byte(p->pci_dev, o, r) +#define PWRW(p, o, r) pci_write_config_word(p->pci_dev, o, r) +#define PWRL(p, o, r) pci_write_config_dword(p->pci_dev, o, r) +#define PRDW(p, o, r) pci_read_config_word(p->pci_dev, o, r) +#define PRDD(p, o, r) pci_read_config_dword(p->pci_dev, o, r) +#define PRDB(p, o, r) pci_read_config_byte(p->pci_dev, o, r) + +#ifndef bus_dvma_to_mem +#if defined (__alpha__) +#define bus_dvma_to_mem(p) ((p) & 0xfffffffful) +#else +#define bus_dvma_to_mem(p) (p) +#endif +#endif + +#if defined (__powerpc__) +#undef __pa +#define __pa(x) x +#endif +#if defined (__i386__) && LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) +#undef __pa +#define __pa(x) x +#endif +#if defined (__sparc__) && LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) +#undef __pa +#define __pa(x) x +#endif +#if defined (__alpha__) && LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) +#undef __pa +#define __pa(x) x +#endif + +/* + * Efficiency- get rid of SBus code && tests unless we need them. + */ +#if defined(__sparcv9__ ) || defined(__sparc__) +#define ISP_SBUS_SUPPORTED 1 +#else +#define ISP_SBUS_SUPPORTED 0 +#endif + +#define ISP_PLATFORM_VERSION_MAJOR 2 +#define ISP_PLATFORM_VERSION_MINOR 1 + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 4321 +#endif +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 1234 +#endif + +#ifdef __BIG_ENDIAN +#define BYTE_ORDER BIG_ENDIAN +#endif +#ifdef __LITTLE_ENDIAN +#define BYTE_ORDER LITTLE_ENDIAN +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +#define DMA_ADDR_T unsigned long +#define QLA_SG_C(sg) sg->length +#define QLA_SG_A(sg) virt_to_bus(sg->address) +#else +#define DMA_ADDR_T dma_addr_t +#define QLA_SG_C(sg) sg_dma_len(sg) +#define QLA_SG_A(sg) sg_dma_address(sg) +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,16) +#define DMA_HTYPE_T char * +#define QLA_HANDLE(cmd) (cmd)->SCp.ptr +#else +#define DMA_HTYPE_T dma_addr_t +#define QLA_HANDLE(cmd) (cmd)->SCp.dma_handle +#endif +#endif + +#define HANDLE_LOOPSTATE_IN_OUTER_LAYERS 1 +#ifdef min +#undef min +#endif +#ifdef max +#undef max +#endif + + +/* + * Normally this should be taken care of by typedefs, + * but linux includes are a complete dog's breakfast. + */ + +#define u_int8_t unsigned char +#define u_int16_t unsigned short +#define u_int32_t unsigned int +#if BITS_PER_LONG == 64 +#define u_int64_t unsigned long +#else +#define u_int64_t unsigned long long +#endif +#define int8_t char +#define int16_t short +#define int32_t int +#define u_long unsigned long +#define u_int unsigned int +#define u_char unsigned char +typedef u_long vm_offset_t; + +#ifdef LINUX_ISP_TARGET_MODE +#define DEFAULT_DEVICE_TYPE 3 +#define NTGT_CMDS 256 + +#define _WIX(isp, b, ix) (((b << 6)) | (ix >> 5)) +#define _BIX(isp, ix) (1 << (ix & 0x1f)) + +#define LUN_BTST(isp, b, ix) \ + (((isp)->isp_osinfo.lunbmap[_WIX(isp, b, ix)] & _BIX(isp, ix)) != 0) + +#define LUN_BSET(isp, b, ix) \ + isp->isp_osinfo.lunbmap[_WIX(isp, b, ix)] |= _BIX(isp, ix) + +#define LUN_BCLR(isp, b, ix) \ + isp->isp_osinfo.lunbmap[_WIX(isp, b, ix)] &= ~_BIX(isp, ix) + +#if defined(__alpha__) || defined(__sparc_v9__) +#define _TMD_PAD_LEN 12 +#else +#define _TMD_PAD_LEN 24 +#endif +#endif + +typedef struct { + enum { + ISP_THREAD_NIL=1, + ISP_THREAD_FC_RESCAN, + ISP_THREAD_REINIT, + ISP_THREAD_FW_CRASH_DUMP, + ISP_THREAD_EXIT + } thread_action; + struct semaphore * thread_waiter; +} isp_thread_action_t; +#define MAX_THREAD_ACTION 10 + +union pstore; +struct isposinfo { + struct ispsoftc * isp_next; + struct Scsi_Host * host; + Scsi_Cmnd *wqnext, *wqtail; + Scsi_Cmnd *dqnext, *dqtail; + union pstore *storep; + char hbaname[16]; + unsigned short instance; + unsigned short wqcnt; + unsigned short wqhiwater; + unsigned short hiwater; + struct timer_list timer; + struct timer_list _mbtimer; + struct semaphore _mbox_sem; + struct semaphore _mbox_c_sem; + struct semaphore _fcs_sem; + spinlock_t slock; + unsigned volatile int + _downcnt : 8, + : 16, + _deadloop : 1, + _draining : 1, + _blocked : 1, + _fcrswdog : 1, + _fcrspend : 1, + _dogactive : 1, + _mbox_waiting : 1, + _mbintsok : 1; + void * misc[8]; /* private platform variant usage */ + unsigned long _iflags; + struct task_struct * task_thread; + struct semaphore * task_request; + struct semaphore * task_ctl_sem; + spinlock_t tlock; + unsigned int nt_actions; + unsigned int device_id; + isp_thread_action_t t_actions[MAX_THREAD_ACTION]; +#ifdef LINUX_ISP_TARGET_MODE +#define TM_WANTED 0x08 +#define TM_BUSY 0x04 +#define TM_TMODE_ENABLED 0x03 + u_int32_t rollinfo : 16, + rstatus : 8, + : 4, + tmflags : 4; + struct semaphore tgt_inisem; + struct semaphore * rsemap; + /* + * This is very inefficient, but is in fact big enough + * to cover a complete bitmap for Fibre Channel, as well + * as the dual bus SCSI cards. This works out without + * overflow easily because the most you can enable + * for the SCSI cards is 64 luns (x 2 busses). + * + * For Fibre Channel, we can run the max luns up to 16384 + * but we'll default to the minimum we can support here. + */ +#define TM_MAX_LUN_FC 128 +#define TM_MAX_LUN_SCSI 64 + u_int32_t lunbmap[TM_MAX_LUN_FC >> 5]; + struct tmd_cmd * pending_t; + struct tmd_cmd * tfreelist; + struct tmd_cmd * pool; + void (*hcb)(int, void *); + void *hcb_token; +#endif +}; +#define mbtimer isp_osinfo._mbtimer +#define dogactive isp_osinfo._dogactive +#define mbox_sem isp_osinfo._mbox_sem +#define mbox_c_sem isp_osinfo._mbox_c_sem +#define fcs_sem isp_osinfo._fcs_sem +#define mbintsok isp_osinfo._mbintsok +#define mbox_waiting isp_osinfo._mbox_waiting +#define isp_pbuf isp_osinfo._pbuf +#define isp_fcrspend isp_osinfo._fcrspend +#define isp_fcrswdog isp_osinfo._fcrswdog +#define isp_blocked isp_osinfo._blocked +#define isp_draining isp_osinfo._draining +#define isp_downcnt isp_osinfo._downcnt +#define isp_deadloop isp_osinfo._deadloop + +#define iflags isp_osinfo._iflags + +#define SEND_THREAD_EVENT(isp, action, dowait) \ +if (isp->isp_osinfo.task_request) { \ + unsigned long flags; \ + spin_lock_irqsave(&isp->isp_osinfo.tlock, flags); \ + if (isp->isp_osinfo.nt_actions >= MAX_THREAD_ACTION) { \ + spin_unlock_irqrestore(&isp->isp_osinfo.tlock, flags); \ + isp_prt(isp, ISP_LOGERR, "thread event overflow"); \ + } else if (action == ISP_THREAD_FC_RESCAN && isp->isp_fcrspend) { \ + spin_unlock_irqrestore(&isp->isp_osinfo.tlock, flags); \ + } else { \ + DECLARE_MUTEX_LOCKED(sem); \ + isp_thread_action_t *tap; \ + tap = &isp->isp_osinfo.t_actions[isp->isp_osinfo.nt_actions++]; \ + tap->thread_action = action; \ + if (dowait) \ + tap->thread_waiter = &sem; \ + else \ + tap->thread_waiter = 0; \ + if (action == ISP_THREAD_FC_RESCAN) \ + isp->isp_fcrspend = 1; \ + up(isp->isp_osinfo.task_request); \ + spin_unlock_irqrestore(&isp->isp_osinfo.tlock, flags); \ + if (dowait) { \ + down(&sem); \ + isp_prt(isp, ISP_LOGDEBUG1, \ + "action %d done from %p", action, &sem); \ + } else { \ + isp_prt(isp, ISP_LOGDEBUG1, \ + "action %d sent", action); \ + } \ + } \ +} + +/* + * Locking macros... + */ +#define ISP_LOCK_INIT(isp) spin_lock_init(&isp->isp_osinfo.slock) +#define ISP_LOCK_SOFTC(isp) { \ + unsigned long _flags; \ + spin_lock_irqsave(&isp->isp_osinfo.slock, _flags); \ + isp->iflags = _flags; \ + } +#define ISP_UNLK_SOFTC(isp) { \ + unsigned long _flags = isp->iflags; \ + spin_unlock_irqrestore(&isp->isp_osinfo.slock, _flags); \ + } + +#define ISP_ILOCK_SOFTC ISP_LOCK_SOFTC +#define ISP_IUNLK_SOFTC ISP_UNLK_SOFTC +#define ISP_IGET_LK_SOFTC ISP_LOCK_SOFTC +#define ISP_DROP_LK_SOFTC ISP_UNLK_SOFTC +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +#define ISP_LOCK_SCSI_DONE(isp) { \ + unsigned long _flags; \ + spin_lock_irqsave(&io_request_lock, _flags); \ + isp->iflags = _flags; \ + } +#define ISP_UNLK_SCSI_DONE(isp) { \ + unsigned long _flags = isp->iflags; \ + spin_unlock_irqrestore(&io_request_lock, _flags); \ + } +#else +#define ISP_LOCK_SCSI_DONE(isp) do { } while(0) +#define ISP_UNLK_SCSI_DONE(isp) do { } while(0) +#endif +#define ISP_LOCKU_SOFTC ISP_ILOCK_SOFTC +#define ISP_UNLKU_SOFTC ISP_IUNLK_SOFTC +#define ISP_TLOCK_INIT(isp) spin_lock_init(&isp->isp_osinfo.tlock) +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#define ISP_DRIVER_ENTRY_LOCK(isp) spin_unlock_irq(&io_request_lock) +#define ISP_DRIVER_EXIT_LOCK(isp) spin_lock_irq(&io_request_lock) +#else +#define ISP_DRIVER_ENTRY_LOCK(isp) \ + spin_unlock_irq(isp->isp_osinfo.host->host_lock) +#define ISP_DRIVER_EXIT_LOCK(isp) \ + spin_lock_irq(isp->isp_osinfo.host->host_lock) +#endif + +#define ISP_MUST_POLL(isp) (in_interrupt() || isp->mbintsok == 0) +/* + * Misc SCSI defines + */ +#define MSG_SIMPLE_Q_TAG 0x21 +#define MSG_HEAD_OF_Q_TAG 0x22 +#define MSG_ORDERED_Q_TAG 0x23 + +/* + * Required Macros/Defines + */ + +#define INLINE __inline + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,18) && \ + defined(CONFIG_HIGHMEM) && !defined(LINUX_ISP_TARGET_MODE) +#define ISP_DAC_SUPPORTED 1 +#else +#define ISP_DAC_SUPPORTED 0 +#endif + +#define ISP2100_SCRLEN 0x800 + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +#define MEMZERO _isp_memzero +#define MEMCPY _isp_memcpy +#else +#define MEMZERO(b, a) memset(b, 0, a) +#define MEMCPY memcpy +#endif +#define SNPRINTF isp_snprintf +#define USEC_DELAY _isp_usec_delay +#define USEC_SLEEP(isp, x) \ + ISP_DROP_LK_SOFTC(isp); \ + __set_current_state(TASK_UNINTERRUPTIBLE); \ + (void) schedule_timeout(_usec_to_jiffies(x)); \ + ISP_IGET_LK_SOFTC(isp) + +#define NANOTIME_T struct timeval +/* for prior to 2.2.19, use do_gettimeofday, and, well, it'll be inaccurate */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,18) +#define GET_NANOTIME(ptr) \ + (ptr)->tv_sec = 0, (ptr)->tv_usec = 0, get_fast_time(ptr) +#else +#define GET_NANOTIME(ptr) \ + (ptr)->tv_sec = 0, (ptr)->tv_usec = 0, do_gettimeofday(ptr) +#endif +#define GET_NANOSEC(x) \ + ((u_int64_t) ((((u_int64_t)(x)->tv_sec) * 1000000 + (x)->tv_usec))) +#define NANOTIME_SUB _isp_microtime_sub + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +#define MAXISPREQUEST(isp) 256 +#else +#define MAXISPREQUEST(isp) ((IS_FC(isp) || IS_ULTRA2(isp))? 1024 : 256) +#endif + +#if defined(__i386__) +#define MEMORYBARRIER(isp, type, offset, size) barrier() +#elif defined(__alpha__) +#define MEMORYBARRIER(isp, type, offset, size) mb() +#elif defined(__sparc__) +#define MEMORYBARRIER(isp, type, offset, size) mb() +#elif defined(__powerpc__) +#define MEMORYBARRIER(isp, type, offset, size) \ + __asm__ __volatile__("eieio" ::: "memory") +#else +# ifdef mb +# define MEMORYBARRIER(isp, type, offset, size) mb() +# else +# define MEMORYBARRIER(isp, type, offset, size) barrier() +# endif +#endif + +#define MBOX_ACQUIRE(isp) \ + /* \ + * Try and acquire semaphore the easy way first- \ + * with our lock already held. \ + */ \ + if (down_trylock(&isp->mbox_sem)) { \ + if (in_interrupt()) { \ + mbp->param[0] = MBOX_HOST_INTERFACE_ERROR; \ + isp_prt(isp, ISP_LOGERR, "cannot acquire MBOX sema"); \ + return; \ + } \ + ISP_DROP_LK_SOFTC(isp); \ + down(&isp->mbox_sem); \ + ISP_IGET_LK_SOFTC(isp); \ + } + +#define MBOX_WAIT_COMPLETE(isp) \ + if (ISP_MUST_POLL(isp)) { \ + int j, lim = 5000000; \ + if (isp->isp_mbxwrk0) { \ + lim *= 12; \ + } \ + for (j = 0; j < 5000000; j += 100) { \ + u_int16_t isr, sema, mbox; \ + if (isp->isp_mboxbsy == 0) { \ + break; \ + } \ + if (ISP_READ_ISR(isp, &isr, &sema, &mbox)) { \ + isp_intr(isp, isr, sema, mbox); \ + if (isp->isp_mboxbsy == 0) { \ + break; \ + } \ + } \ + ISP_DROP_LK_SOFTC(isp); \ + udelay(100); \ + ISP_IGET_LK_SOFTC(isp); \ + } \ + if (isp->isp_mboxbsy != 0) { \ + isp_prt(isp, ISP_LOGWARN, \ + "Polled Mailbox Command (0x%x) Timeout", \ + isp->isp_lastmbxcmd); \ + isp->isp_mboxbsy = 0; \ + } \ + } else { \ + int lim = (isp->isp_mbxwrk0)? 60 : 5; \ + init_timer(&isp->mbtimer); \ + isp->mbtimer.data = (unsigned long) isp; \ + isp->mbtimer.function = isplinux_mbtimer; \ + isp->mbtimer.expires = jiffies + (lim * HZ); \ + add_timer(&isp->mbtimer); \ + isp->mbox_waiting = 1; \ + ISP_DROP_LK_SOFTC(isp); \ + down(&isp->mbox_c_sem); \ + ISP_IGET_LK_SOFTC(isp); \ + isp->mbox_waiting = 0; \ + del_timer(&isp->mbtimer); \ + if (isp->isp_mboxbsy != 0) { \ + isp_prt(isp, ISP_LOGWARN, \ + "Interrupting Mailbox Command (0x%x) Timeout",\ + isp->isp_lastmbxcmd); \ + isp->isp_mboxbsy = 0; \ + } \ + } + +#define MBOX_NOTIFY_COMPLETE(isp) \ + if (isp->mbox_waiting) { \ + isp->mbox_waiting = 0; \ + up(&isp->mbox_c_sem); \ + } \ + isp->isp_mboxbsy = 0 + +#define MBOX_RELEASE(isp) up(&isp->mbox_sem) + +#define FC_SCRATCH_ACQUIRE(isp) \ + /* \ + * Try and acquire semaphore the easy way first- \ + * with our lock already held. \ + */ \ + if (in_interrupt()) { \ + while (down_trylock(&isp->fcs_sem)) { \ + ISP_DROP_LK_SOFTC(isp); \ + USEC_DELAY(5000); \ + ISP_IGET_LK_SOFTC(isp); \ + } \ + } else { \ + ISP_DROP_LK_SOFTC(isp); \ + down(&isp->fcs_sem); \ + ISP_IGET_LK_SOFTC(isp); \ + } + +#define FC_SCRATCH_RELEASE(isp) up(&isp->fcs_sem) + + +#ifndef SCSI_GOOD +#define SCSI_GOOD 0x0 +#endif +#ifndef SCSI_CHECK +#define SCSI_CHECK 0x2 +#endif +#ifndef SCSI_BUSY +#define SCSI_BUSY 0x8 +#endif +#ifndef SCSI_QFULL +#define SCSI_QFULL 0x28 +#endif + +#define XS_T Scsi_Cmnd +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#define XS_HOST(Cmnd) Cmnd->device->host +#define XS_ISP(Cmnd) ((struct ispsoftc *) (Cmnd)->host->hostdata) +#define XS_CHANNEL(Cmnd) (Cmnd)->channel +#define XS_TGT(Cmnd) (Cmnd)->target +#define XS_LUN(Cmnd) (Cmnd)->lun +#else +#define XS_HOST(Cmnd) Cmnd->device->host +#define XS_ISP(Cmnd) \ + ((struct ispsoftc *) (Cmnd)->device->host->hostdata) +#define XS_CHANNEL(Cmnd) (Cmnd)->device->channel +#define XS_TGT(Cmnd) (Cmnd)->device->id +#define XS_LUN(Cmnd) (Cmnd)->device->lun +#endif +#define XS_CDBP(Cmnd) (Cmnd)->cmnd +#define XS_CDBLEN(Cmnd) (Cmnd)->cmd_len +#define XS_XFRLEN(Cmnd) (Cmnd)->request_bufflen +#define XS_TIME(Cmnd) (Cmnd)->timeout +#define XS_RESID(Cmnd) (Cmnd)->SCp.this_residual +#define XS_STSP(Cmnd) (&(Cmnd)->SCp.Status) +#define XS_SNSP(Cmnd) (Cmnd)->sense_buffer +#define XS_SNSLEN(Cmnd) (sizeof (Cmnd)->sense_buffer) +#define XS_SNSKEY(Cmnd) ((Cmnd)->sense_buffer[2] & 0xf) +#define XS_TAG_P(Cmnd) (Cmnd->device->tagged_supported != 0) +#define XS_TAG_TYPE(xs) REQFLAG_STAG + +#define XS_SETERR(xs, v) \ + if ((v) == HBA_TGTBSY) { \ + (xs)->SCp.Status = SCSI_BUSY; \ + } else { \ + (xs)->result &= ~0xff0000; \ + (xs)->result |= ((v) << 16); \ + } + +# define HBA_NOERROR DID_OK +# define HBA_BOTCH DID_ERROR +# define HBA_CMDTIMEOUT DID_TIME_OUT +# define HBA_SELTIMEOUT DID_NO_CONNECT +# define HBA_TGTBSY 123456 /* special handling */ +# define HBA_BUSRESET DID_RESET +# define HBA_ABORTED DID_ABORT +# define HBA_DATAOVR DID_ERROR +# define HBA_ARQFAIL DID_ERROR + +#define XS_ERR(xs) host_byte((xs)->result) + +#define XS_NOERR(xs) host_byte((xs)->result) == DID_OK + +#define XS_INITERR(xs) (xs)->result = 0, (xs)->SCp.Status = 0 + +#define XS_SAVE_SENSE(Cmnd, sp) \ + MEMCPY(&Cmnd->sense_buffer, sp->req_sense_data, \ + min(sizeof Cmnd->sense_buffer, sp->req_sense_len)) + +#define XS_SET_STATE_STAT(a, b, c) + +#define DEFAULT_IID(x) 7 +#define DEFAULT_LOOPID(x) 111 +#define DEFAULT_NODEWWN(isp) (isp)->isp_defwwnn +#define DEFAULT_PORTWWN(isp) (isp)->isp_defwwpn +#define DEFAULT_FRAME_SIZE(isp) \ + (IS_SCSI(isp)? 0 : isp->isp_osinfo.storep->fibre_scsi.default_frame_size) +#define DEFAULT_EXEC_ALLOC(isp) \ + (IS_SCSI(isp)? 0 : isp->isp_osinfo.storep->fibre_scsi.default_exec_alloc) +#define ISP_NODEWWN(isp) (isp)->isp_nvramwwnn +#define ISP_PORTWWN(isp) (isp)->isp_nvramwwpn + +#define ISP_IOXPUT_8(isp, s, d) *(d) = s +#define ISP_IOXPUT_16(isp, s, d) *(d) = cpu_to_le16(s) +#define ISP_IOXPUT_32(isp, s, d) *(d) = cpu_to_le32(s) + +#define ISP_IOXGET_8(isp, s, d) d = *(s) +#define ISP_IOXGET_16(isp, s, d) d = le16_to_cpu(*((u_int16_t *)s)) +#define ISP_IOXGET_32(isp, s, d) d = le32_to_cpu(*((u_int32_t *)s)) + +#define ISP_SWIZZLE_NVRAM_WORD(isp, rp) *rp = le16_to_cpu(*rp) + + +/* + * Includes of common header files + */ +#include "ispreg.h" +#include "ispvar.h" +#include "ispmbox.h" + +/* + * isp_osinfo definitions, extensions and shorthand. + */ + +/* + * Parameter storage. The order of tags is important- sdparam && fcp + * must come first because isp->isp_params is set to point there... + */ +union pstore { + struct { + sdparam _sdp[2]; /* they need to be sequential */ + u_char psc_opts[2][MAX_TARGETS]; + u_char dutydone; + } parallel_scsi; + struct { + fcparam fcp; + u_int64_t wwnn; + u_int64_t wwpn; + u_int64_t nvram_wwnn; + u_int64_t nvram_wwpn; + u_int16_t default_frame_size; + u_int16_t default_exec_throttle; + } fibre_scsi; +}; +#define isp_next isp_osinfo.isp_next +#define isp_name isp_osinfo.hbaname +#define isp_host isp_osinfo.host +#define isp_unit isp_osinfo.instance +#define isp_psco isp_osinfo.storep->parallel_scsi.psc_opts +#define isp_dutydone isp_osinfo.storep->parallel_scsi.dutydone +#define isp_defwwnn isp_osinfo.storep->fibre_scsi.wwnn +#define isp_defwwpn isp_osinfo.storep->fibre_scsi.wwpn +#define isp_nvramwwnn isp_osinfo.storep->fibre_scsi.nvram_wwnn +#define isp_nvramwwpn isp_osinfo.storep->fibre_scsi.nvram_wwpn + +/* + * Driver prototypes.. + */ +void isplinux_timer(unsigned long); +void isplinux_mbtimer(unsigned long); +irqreturn_t isplinux_intr(int, void *, struct pt_regs *); +void isplinux_common_init(struct ispsoftc *); +void isplinux_reinit(struct ispsoftc *); +void isplinux_sqd(struct Scsi_Host *, Scsi_Device *); + +int isp_drain_reset(struct ispsoftc *, char *); +int isp_drain(struct ispsoftc *, char *); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +static INLINE void _isp_memcpy(void *, void *, size_t); +static INLINE void _isp_memzero(void *, size_t); +#endif +static INLINE u_int64_t _isp_microtime_sub(struct timeval *, struct timeval *); +static INLINE void _isp_usec_delay(unsigned int); +static INLINE unsigned long _usec_to_jiffies(unsigned int); + +int isplinux_proc_info(char *, char **, off_t, int, int, int); +int isplinux_detect(Scsi_Host_Template *); +int isplinux_release(struct Scsi_Host *); +#define ISPLINUX_RELEASE isplinux_release +const char *isplinux_info(struct Scsi_Host *); +int isplinux_queuecommand(Scsi_Cmnd *, void (* done)(Scsi_Cmnd *)); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +int isplinux_biosparam(Disk *, kdev_t, int[]); +#else +int isplinux_biosparam(struct scsi_device *, struct block_device *, + sector_t, int[]); +#endif + + +/* + * Driver wide data... + */ +extern int isp_debug; +extern int isp_unit_seed; +extern int isp_disable; +extern int isp_nofwreload; +extern int isp_nonvram; +extern int isp_fcduplex; +extern struct ispsoftc *isplist; + +/* + * Platform private flags + */ +#ifndef NULL +#define NULL ((void *) 0) +#endif + +#define ISP_WATCH_TIME HZ + +#ifndef min +#define min(a,b) (((a)<(b))?(a):(b)) +#endif +#ifndef max +#define max(a, b) (((a) > (b)) ? (a) : (b)) +#endif +#ifndef roundup +#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) +#endif +#ifndef ARGSUSED +#define ARGSUSED(x) x = x +#endif + + + + +/* + * Platform specific 'inline' or support functions + */ + +#ifdef __sparc__ +#define _SBSWAP(isp, b, c) \ + if (isp->isp_bustype == ISP_BT_SBUS) { \ + u_int8_t tmp = b; \ + b = c; \ + c = tmp; \ + } +#else +#define _SBSWAP(a, b, c) +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +static INLINE void +_isp_memcpy(void *to, void *from, size_t amt) +{ + unsigned char *x = to; unsigned char *y = from; + while (amt-- != 0) *x++ = *y++; +} + +static INLINE void +_isp_memzero(void *to, size_t amt) +{ + unsigned char *x = to; + while (amt-- != 0) *x++ = 0; +} + +static INLINE unsigned long IspOrder(int); +static INLINE unsigned long +IspOrder(int nelem) +{ + unsigned long order, rsize; + + order = 0; + rsize = PAGE_SIZE; + while (rsize < (unsigned long) ISP_QUEUE_SIZE(nelem)) { + order++; + rsize <<= 1; + } + return (order); +} +#endif + +static INLINE u_int64_t +_isp_microtime_sub(struct timeval *b, struct timeval *a) +{ + u_int64_t elapsed; + struct timeval x = *b; + x.tv_sec -= a->tv_sec; + x.tv_usec -= a->tv_usec; + if (x.tv_usec < 0) { + x.tv_sec--; + x.tv_usec += 1000000; + } + if (x.tv_usec >= 1000000) { + x.tv_sec++; + x.tv_usec -= 1000000; + } + elapsed = GET_NANOSEC(&x); + if (elapsed == 0) + elapsed++; + if ((int64_t) elapsed < 0) /* !!!! */ + return (1000); + return (elapsed * 1000); +} + +static INLINE void +_isp_usec_delay(unsigned int usecs) +{ + while (usecs > 1000) { + mdelay(1); + usecs -= 1000; + } + if (usecs) + udelay(usecs); +} + +static INLINE unsigned long +_usec_to_jiffies(unsigned int usecs) +{ + struct timespec lt; + if (usecs == 0) + usecs++; + lt.tv_sec = 0; + lt.tv_nsec = usecs * 1000; + return (timespec_to_jiffies(<)); +} + +#define GetPages(a) __get_dma_pages(GFP_ATOMIC|GFP_DMA, a) +#define RlsPages(a, b) free_pages((unsigned long) a, b) + +char *isp_snprintf(char *, size_t, const char *, ...); + +/* + * Common inline functions + */ + +#include "isp_inline.h" + +#ifdef ISP_TARGET_MODE +void isp_attach_target(ispsoftc_t *); +void isp_detach_target(ispsoftc_t *); +int isp_target_async(struct ispsoftc *, int, int); +int isp_target_notify(struct ispsoftc *, void *, u_int16_t *); +#endif +/* + * Config data + */ + +int isplinux_abort(Scsi_Cmnd *); +int isplinux_bdr(Scsi_Cmnd *); +int isplinux_sreset(Scsi_Cmnd *); +int isplinux_hreset(Scsi_Cmnd *); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#define QLOGICISP { \ + next: NULL, \ + module: NULL, \ + proc_info: isplinux_proc_info, \ + name: "Qlogic ISP 10X0/2X00", \ + detect: isplinux_detect, \ + release: ISPLINUX_RELEASE, \ + info: isplinux_info, \ + queuecommand: isplinux_queuecommand, \ + use_new_eh_code: 1, \ + eh_abort_handler: isplinux_abort, \ + eh_device_reset_handler: isplinux_bdr, \ + eh_bus_reset_handler: isplinux_sreset, \ + eh_host_reset_handler: isplinux_hreset, \ + bios_param: isplinux_biosparam, \ + can_queue: 1, \ + sg_tablesize: SG_ALL, \ + use_clustering: ENABLE_CLUSTERING, \ + cmd_per_lun: 1 \ +} +#else +#define QLOGICISP { \ + module: NULL, \ + proc_info: isplinux_proc_info, \ + name: "Qlogic ISP 10X0/2X00", \ + detect: isplinux_detect, \ + release: ISPLINUX_RELEASE, \ + info: isplinux_info, \ + queuecommand: isplinux_queuecommand, \ + eh_abort_handler: isplinux_abort, \ + eh_device_reset_handler: isplinux_bdr, \ + eh_bus_reset_handler: isplinux_sreset, \ + eh_host_reset_handler: isplinux_hreset, \ + bios_param: isplinux_biosparam, \ + can_queue: 1, \ + sg_tablesize: SG_ALL, \ + use_clustering: ENABLE_CLUSTERING, \ + cmd_per_lun: 1, \ + slave_configure: isplinux_slave_configure, \ +} +#endif +/* + * mode: c + * Local variables: + * c-indent-level: 4 + * c-brace-imaginary-offset: 0 + * c-brace-offset: -4 + * c-argdecl-indent: 4 + * c-label-offset: -4 + * c-continued-statement-offset: 4 + * c-continued-brace-offset: 0 + * End: + */ +#endif /* _ISP_LINUX_H */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/isp_pci.c 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,2404 @@ +/* + * Qlogic ISP Host Adapter PCI specific probe and attach routines + *--------------------------------------- + * Copyright (c) 1998, 1999, 2000, 2001 by Matthew Jacob + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification, immediately at the beginning of the file. + * 2. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * the GNU Public License ("GPL"). + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Matthew Jacob + * Feral Software + * PMB #825 + * 5214-F Diamond Hts Blvd + * San Francisco, CA, 94131 + * mjacob@feral.com + */ + +#include "isp_linux.h" +#if defined(__powerpc__) || defined(__sparc__) +static int isp_pci_mapmem = 0xffffffff; +#else +static int isp_pci_mapmem = 0; +#endif +#if defined(__sparc__) +#undef ioremap_nocache +#define ioremap_nocache ioremap +#endif +static int isplinux_pci_init(struct Scsi_Host *); +static u_int16_t isp_pci_rd_reg(struct ispsoftc *, int); +static void isp_pci_wr_reg(struct ispsoftc *, int, u_int16_t); +#if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) +static u_int16_t isp_pci_rd_reg_1080(struct ispsoftc *, int); +static void isp_pci_wr_reg_1080(struct ispsoftc *, int, u_int16_t); +#endif +static int +isp_pci_rd_isr(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); +#ifndef ISP_DISABLE_2300_SUPPORT +static int +isp_pci_rd_isr_2300(struct ispsoftc *, u_int16_t *, u_int16_t *, u_int16_t *); +#endif +static int isp_pci_mbxdma(struct ispsoftc *); +static int +isp_pci_dmasetup(struct ispsoftc *, XS_T *, ispreq_t *, u_int16_t *, u_int16_t); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) +static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, u_int16_t); +#define IS_HIGH_ISP_ADDR(addr) (addr >= (u_int64_t) 0x100000000) +#else +#define isp_pci_dmateardown NULL +#define IS_HIGH_ISP_ADDR(addr) 0 +#endif + +#if ISP_DAC_SUPPORTED == 1 +#define ISP_A64 1 +#define HIWD(x) ((x) >> 32) +#else +#define ISP_A64 0 +#define HIWD(x) 0 +#endif +#define LOWD(x) x + +static void isp_pci_reset1(struct ispsoftc *); +static void isp_pci_dumpregs(struct ispsoftc *, const char *); + +#ifndef ISP_CODE_ORG +#define ISP_CODE_ORG 0x1000 +#endif + +#ifndef ISP_DISABLE_1020_SUPPORT +#include "asm_1040.h" +#define ISP_1040_RISC_CODE (u_int16_t *) isp_1040_risc_code +#else +#define ISP_1040_RISC_CODE NULL +#endif + +#ifndef ISP_DISABLE_1080_SUPPORT +#include "asm_1080.h" +#define ISP_1080_RISC_CODE (u_int16_t *) isp_1080_risc_code +#else +#define ISP_1080_RISC_CODE NULL +#endif + +#ifndef ISP_DISABLE_12160_SUPPORT +#include "asm_12160.h" +#define ISP_12160_RISC_CODE (u_int16_t *) isp_12160_risc_code +#else +#define ISP_12160_RISC_CODE NULL +#endif + +#ifndef ISP_DISABLE_2100_SUPPORT +#include "asm_2100.h" +#define ISP_2100_RISC_CODE (u_int16_t *) isp_2100_risc_code +#else +#define ISP_2100_RISC_CODE NULL +#endif + +#ifndef ISP_DISABLE_2200_SUPPORT +#include "asm_2200.h" +#define ISP_2200_RISC_CODE (u_int16_t *) isp_2200_risc_code +#else +#define ISP_2200_RISC_CODE NULL +#endif + +#ifndef ISP_DISABLE_2300_SUPPORT +#include "asm_2300.h" +#define ISP_2300_RISC_CODE (u_int16_t *) isp_2300_risc_code +#else +#define ISP_2300_RISC_CODE NULL +#endif + +#ifndef ISP_DISABLE_1020_SUPPORT +static struct ispmdvec mdvec = { + isp_pci_rd_isr, + isp_pci_rd_reg, + isp_pci_wr_reg, + isp_pci_mbxdma, + isp_pci_dmasetup, + isp_pci_dmateardown, + NULL, + isp_pci_reset1, + isp_pci_dumpregs, + ISP_1040_RISC_CODE, + BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 +}; +#endif + +#ifndef ISP_DISABLE_1080_SUPPORT +static struct ispmdvec mdvec_1080 = { + isp_pci_rd_isr, + isp_pci_rd_reg_1080, + isp_pci_wr_reg_1080, + isp_pci_mbxdma, + isp_pci_dmasetup, + isp_pci_dmateardown, + NULL, + isp_pci_reset1, + isp_pci_dumpregs, + ISP_1080_RISC_CODE, + BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_128 +}; +#endif + +#ifndef ISP_DISABLE_12160_SUPPORT +static struct ispmdvec mdvec_12160 = { + isp_pci_rd_isr, + isp_pci_rd_reg_1080, + isp_pci_wr_reg_1080, + isp_pci_mbxdma, + isp_pci_dmasetup, + isp_pci_dmateardown, + NULL, + isp_pci_reset1, + isp_pci_dumpregs, + ISP_12160_RISC_CODE, + BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_128 +}; +#endif + +#ifndef ISP_DISABLE_2100_SUPPORT +static struct ispmdvec mdvec_2100 = { + isp_pci_rd_isr, + isp_pci_rd_reg, + isp_pci_wr_reg, + isp_pci_mbxdma, + isp_pci_dmasetup, + isp_pci_dmateardown, + NULL, + isp_pci_reset1, + isp_pci_dumpregs, + ISP_2100_RISC_CODE +}; +#endif + +#ifndef ISP_DISABLE_2200_SUPPORT +static struct ispmdvec mdvec_2200 = { + isp_pci_rd_isr, + isp_pci_rd_reg, + isp_pci_wr_reg, + isp_pci_mbxdma, + isp_pci_dmasetup, + isp_pci_dmateardown, + NULL, + isp_pci_reset1, + isp_pci_dumpregs, + ISP_2200_RISC_CODE +}; +#endif + +#ifndef ISP_DISABLE_2300_SUPPORT +static struct ispmdvec mdvec_2300 = { + isp_pci_rd_isr_2300, + isp_pci_rd_reg, + isp_pci_wr_reg, + isp_pci_mbxdma, + isp_pci_dmasetup, + isp_pci_dmateardown, + NULL, + isp_pci_reset1, + isp_pci_dumpregs, + ISP_2300_RISC_CODE +}; +#endif + +#ifndef PCI_DEVICE_ID_QLOGIC_ISP1020 +#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 +#endif + +#ifndef PCI_DEVICE_ID_QLOGIC_ISP1020 +#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 +#endif + +#ifndef PCI_DEVICE_ID_QLOGIC_ISP1080 +#define PCI_DEVICE_ID_QLOGIC_ISP1080 0x1080 +#endif + +#ifndef PCI_DEVICE_ID_QLOGIC_ISP10160 +#define PCI_DEVICE_ID_QLOGIC_ISP10160 0x1016 +#endif + +#ifndef PCI_DEVICE_ID_QLOGIC_ISP12160 +#define PCI_DEVICE_ID_QLOGIC_ISP12160 0x1216 +#endif + +#ifndef PCI_DEVICE_ID_QLOGIC_ISP1240 +#define PCI_DEVICE_ID_QLOGIC_ISP1240 0x1240 +#endif + +#ifndef PCI_DEVICE_ID_QLOGIC_ISP1280 +#define PCI_DEVICE_ID_QLOGIC_ISP1280 0x1280 +#endif + +#ifndef PCI_DEVICE_ID_QLOGIC_ISP2100 +#define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100 +#endif + +#ifndef PCI_DEVICE_ID_QLOGIC_ISP2200 +#define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200 +#endif + +#ifndef PCI_DEVICE_ID_QLOGIC_ISP2300 +#define PCI_DEVICE_ID_QLOGIC_ISP2300 0x2300 +#endif + +#ifndef PCI_DEVICE_ID_QLOGIC_ISP2312 +#define PCI_DEVICE_ID_QLOGIC_ISP2312 0x2312 +#endif + +#define PCI_DFLT_LTNCY 0x40 +#define PCI_DFLT_LNSZ 0x10 +#define PCI_CMD_ISP \ + (PCI_COMMAND_MASTER|PCI_COMMAND_INVALIDATE|PCI_COMMAND_PARITY|PCI_COMMAND_SERR) + +/* + * Encapsulating softc... Order of elements is important. The tag + * pci_isp must come first because of multiple structure punning + * (Scsi_Host * == struct isp_pcisoftc * == struct ispsofct *). + */ +struct isp_pcisoftc { + struct ispsoftc pci_isp; + struct pci_dev * pci_dev; + vm_offset_t port; /* I/O port address */ + vm_offset_t paddr; /* Physical Memory Address */ + vm_offset_t vaddr; /* Mapped Memory Address */ + vm_offset_t poff[_NREG_BLKS]; + union pstore params; +#ifdef LINUX_ISP_TARGET_MODE + tmd_cmd_t rpool[NTGT_CMDS]; +#endif +}; + +/* + * Gratefully borrowed from Gerard Roudier's sym53c8xx driver + */ +static INLINE vm_offset_t +map_pci_mem(u_long base, u_long size) +{ + u_long page_base = ((u_long) base) & PAGE_MASK; + u_long page_offs = ((u_long) base) - page_base; + u_long map_size = roundup(page_offs+size, PAGE_SIZE); + u_long page_remapped = (u_long) ioremap_nocache(page_base, map_size); + (void) map_size; + return (vm_offset_t) (page_remapped ? (page_remapped + page_offs) : 0); +} + +static INLINE +void unmap_pci_mem(vm_offset_t vaddr, u_long size) +{ + if (vaddr) + iounmap((void *) (vaddr & PAGE_MASK)); +} + +static INLINE int +map_isp_mem(struct isp_pcisoftc *isp_pci, u_short cmd, vm_offset_t mem_base) +{ + if (cmd & PCI_COMMAND_MEMORY) { + isp_pci->paddr = __pa(mem_base); + isp_pci->paddr &= PCI_BASE_ADDRESS_MEM_MASK; + isp_pci->vaddr = map_pci_mem(isp_pci->paddr, 0xff); + return (isp_pci->vaddr != (vm_offset_t) 0); + } + return (0); +} + +static INLINE int +map_isp_io(struct isp_pcisoftc *isp_pci, u_short cmd, vm_offset_t io_base) +{ + if ((cmd & PCI_COMMAND_IO) && (io_base & 3) == 1) { + isp_pci->port = io_base & PCI_BASE_ADDRESS_IO_MASK; +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0) + if (check_region(isp_pci->port, 0xff)) { + return (0); + } +#endif + request_region(isp_pci->port, 0xff, "isp"); + return (1); + } + return (0); +} + +#define ISP_PCI_BUS pcidev->bus->number +#define ISP_PCI_DEVICE pcidev->devfn +#define ISEARCH_RESET pcidev = NULL +#define ISEARCH(x) \ + (pcidev = pci_find_device(PCI_VENDOR_ID_QLOGIC, x, pcidev)) != NULL +#define ISEARCH_NEXT +#define ISTORE_ARGS struct pci_dev *pcidev +#define ISTORE_FNDARGS ISTORE_ARGS +#define ISTORE_FNCARGS pcidev +#define ISTORE_ISP_INFO(x) (x)->pci_dev = pcidev + +static INLINE struct isp_pcisoftc * +isplinux_pci_addhost(Scsi_Host_Template *tmpt, ISTORE_FNDARGS) +{ + struct Scsi_Host *host; + struct ispsoftc *isp; + struct isp_pcisoftc *pci_isp; + + host = scsi_register(tmpt, sizeof(struct isp_pcisoftc)); + if (host == NULL) { + printk("isplinux_pci_addhost: scsi_register failed\n"); + return (NULL); + } + pci_isp = (struct isp_pcisoftc *) host->hostdata; + if (pci_isp == NULL) { + printk("isplinux_pci_addhost: cannot get softc out of scsi_register\n"); + return (NULL); + } + ISTORE_ISP_INFO(pci_isp); + isp = (struct ispsoftc *) pci_isp; + isp->isp_host = host; + isp->isp_osinfo.storep = &pci_isp->params; + if (isplinux_pci_init(host)) { + scsi_unregister(host); + return (NULL); + } + isp->isp_next = isplist; + isplist = isp; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,4) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,61) + scsi_set_device(host, &pci_isp->pci_dev->dev); +#else + scsi_set_pci_device(host, pci_isp->pci_dev); +#endif +#endif + return (pci_isp); +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,18) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#include +static int +isp_notify_reboot(struct notifier_block *ispnb, unsigned long Event, void *b) +{ + struct ispsoftc *isp; + switch (Event) { + case SYS_RESTART: + case SYS_HALT: + case SYS_POWER_OFF: + break; + default: + return (NOTIFY_DONE); + } + for (isp = isplist; isp != NULL; isp = isp->isp_next) { + ISP_LOCKU_SOFTC(isp); + ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); + if (IS_FC(isp)) { + ISP_WRITE(isp, BIU2100_CSR, BIU2100_FPM0_REGS); + ISP_WRITE(isp, FPM_DIAG_CONFIG, FPM_SOFT_RESET); + ISP_WRITE(isp, BIU2100_CSR, BIU2100_FB_REGS); + ISP_WRITE(isp, FBM_CMD, FBMCMD_FIFO_RESET_ALL); + ISP_WRITE(isp, BIU2100_CSR, BIU2100_RISC_REGS); + } + ISP_UNLKU_SOFTC(isp); + } + return (NOTIFY_OK); +} +static struct notifier_block isp_notifier = { + notifier_call: isp_notify_reboot, + next: NULL, + priority: 0 +}; +#endif + +static int isp_nfound = 0; +int +isplinux_pci_detect(Scsi_Host_Template *tmpt) +{ + static const char *fmt = + "ISP SCSI and Fibre Channel Host Adapter Driver\n" + " Linux Platform Version %d.%d\n" + " Common Core Code Version %d.%d\n" + " Built on %s, %s\n"; + struct isp_pcisoftc *pci_isp; + ISTORE_ARGS; + + if (pci_find_device(PCI_ANY_ID, PCI_ANY_ID, NULL) == NULL) { + return (0); + } + + printk(fmt, ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, + ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR, __DATE__ , __TIME__ ); + +#ifndef ISP_DISABLE_1020_SUPPORT + for (ISEARCH_RESET; ISEARCH(PCI_DEVICE_ID_QLOGIC_ISP1020); ISEARCH_NEXT) { + pci_isp = isplinux_pci_addhost(tmpt, ISTORE_FNCARGS); + if (pci_isp) { + isp_nfound++; + } + } +#endif + +#ifndef ISP_DISABLE_1080_SUPPORT + for (ISEARCH_RESET; ISEARCH(PCI_DEVICE_ID_QLOGIC_ISP1240); ISEARCH_NEXT) { + pci_isp = isplinux_pci_addhost(tmpt, ISTORE_FNCARGS); + if (pci_isp) { + isp_nfound++; + } + } + for (ISEARCH_RESET; ISEARCH(PCI_DEVICE_ID_QLOGIC_ISP1080); ISEARCH_NEXT) { + pci_isp = isplinux_pci_addhost(tmpt, ISTORE_FNCARGS); + if (pci_isp) { + isp_nfound++; + } + } + for (ISEARCH_RESET; ISEARCH(PCI_DEVICE_ID_QLOGIC_ISP1280); ISEARCH_NEXT) { + pci_isp = isplinux_pci_addhost(tmpt, ISTORE_FNCARGS); + if (pci_isp) { + isp_nfound++; + } + } +#endif + +#ifndef ISP_DISABLE_12160_SUPPORT + for (ISEARCH_RESET; ISEARCH(PCI_DEVICE_ID_QLOGIC_ISP10160); ISEARCH_NEXT) { + pci_isp = isplinux_pci_addhost(tmpt, ISTORE_FNCARGS); + if (pci_isp) { + isp_nfound++; + } + } + for (ISEARCH_RESET; ISEARCH(PCI_DEVICE_ID_QLOGIC_ISP12160); ISEARCH_NEXT) { + pci_isp = isplinux_pci_addhost(tmpt, ISTORE_FNCARGS); + if (pci_isp) { + isp_nfound++; + } + } +#endif + +#ifndef ISP_DISABLE_2100_SUPPORT + for (ISEARCH_RESET; ISEARCH(PCI_DEVICE_ID_QLOGIC_ISP2100); ISEARCH_NEXT) { + pci_isp = isplinux_pci_addhost(tmpt, ISTORE_FNCARGS); + if (pci_isp) { + isp_nfound++; + } + } +#endif + +#ifndef ISP_DISABLE_2200_SUPPORT + for (ISEARCH_RESET; ISEARCH(PCI_DEVICE_ID_QLOGIC_ISP2200); ISEARCH_NEXT) { + pci_isp = isplinux_pci_addhost(tmpt, ISTORE_FNCARGS); + if (pci_isp) { + isp_nfound++; + } + } +#endif + +#ifndef ISP_DISABLE_2300_SUPPORT + for (ISEARCH_RESET; ISEARCH(PCI_DEVICE_ID_QLOGIC_ISP2300); ISEARCH_NEXT) { + pci_isp = isplinux_pci_addhost(tmpt, ISTORE_FNCARGS); + if (pci_isp) { + isp_nfound++; + } + } + for (ISEARCH_RESET; ISEARCH(PCI_DEVICE_ID_QLOGIC_ISP2312); ISEARCH_NEXT) { + pci_isp = isplinux_pci_addhost(tmpt, ISTORE_FNCARGS); + if (pci_isp) { + isp_nfound++; + } + } +#endif + /* + * Don't do reboot notifier stuff for 2.5.X yet + */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,18) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + if (isp_nfound) { + register_reboot_notifier(&isp_notifier); + } +#endif + return (isp_nfound); +} + +void +isplinux_pci_release(struct Scsi_Host *host) +{ + struct ispsoftc *isp = (struct ispsoftc *) host->hostdata; + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) host->hostdata; + free_irq(host->irq, pcs); + if (pcs->vaddr != 0) { + unmap_pci_mem(pcs->vaddr, 0xff); + pcs->vaddr = 0; + } else { + release_region(pcs->port, 0xff); + pcs->port = 0; + } + kfree(isp->isp_xflist); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + pci_free_consistent(pcs->pci_dev, RQUEST_QUEUE_LEN(isp) * QENTRY_LEN, + isp->isp_rquest, isp->isp_rquest_dma); + pci_free_consistent(pcs->pci_dev, RESULT_QUEUE_LEN(isp) * QENTRY_LEN, + isp->isp_result, isp->isp_result_dma); + if (IS_FC(isp)) { + pci_free_consistent(pcs->pci_dev, ISP2100_SCRLEN, + FCPARAM(isp)->isp_scratch, FCPARAM(isp)->isp_scdma); + } +#else + RlsPages(isp->isp_rquest, IspOrder(RQUEST_QUEUE_LEN(isp))); + RlsPages(isp->isp_result, IspOrder(RESULT_QUEUE_LEN(isp))); + if (IS_FC(isp) && FCPARAM(isp)->isp_scratch) { + RlsPages(FCPARAM(isp)->isp_scratch, 1); + } +#endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,18) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + if (--isp_nfound <= 0) { + unregister_reboot_notifier(&isp_notifier); + } +#endif +} + +static int +isplinux_pci_init(struct Scsi_Host *host) +{ + static char *nomap = "cannot map either memory or I/O space"; + unsigned long io_base, mem_base; + unsigned int irq, pci_cmd_isp = PCI_CMD_ISP; + struct isp_pcisoftc *isp_pci; + u_char rev, lnsz, timer; + u_short vid, did, cmd; + char loc[32]; + struct ispsoftc *isp; + + isp_pci = (struct isp_pcisoftc *) host->hostdata; + isp = (struct ispsoftc *) isp_pci; + sprintf(loc, "isp@", isp_pci->pci_dev->bus->number, + PCI_SLOT(isp_pci->pci_dev->devfn), PCI_FUNC(isp_pci->pci_dev->devfn)); + if (PRDW(isp_pci, PCI_COMMAND, &cmd) || + PRDB(isp_pci, PCI_CACHE_LINE_SIZE, &lnsz) || + PRDB(isp_pci, PCI_LATENCY_TIMER, &timer) || + PRDB(isp_pci, PCI_CLASS_REVISION, &rev)) { + printk("%s: error reading PCI configuration", loc); + return (1); + } + vid = isp_pci->pci_dev->vendor; + did = isp_pci->pci_dev->device; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + io_base = pci_resource_start(isp_pci->pci_dev, 0); + if (pci_resource_flags(isp_pci->pci_dev, 0) & PCI_BASE_ADDRESS_MEM_TYPE_64) + irq = 2; + else + irq = 1; + mem_base = pci_resource_start(isp_pci->pci_dev, irq); + if (pci_resource_flags(isp_pci->pci_dev, irq) & + PCI_BASE_ADDRESS_MEM_TYPE_64) { +#if BITS_PER_LONG == 64 + mem_base |= pci_resource_start(isp_pci->pci_dev, irq+1) << 32; +#else + isp_pci_mapmem &= ~(1 << isp->isp_unit); +#endif + } +#else /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) */ + io_base = isp_pci->pci_dev->base_address[0]; + mem_base = isp_pci->pci_dev->base_address[1]; + if (mem_base & PCI_BASE_ADDRESS_MEM_TYPE_64) { +#if BITS_PER_LONG == 64 + mem_base |= isp_pci->pci_dev->base_address[2] << 32; +#else + isp_pci_mapmem &= ~(1 << isp->isp_unit); +#endif + } +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) */ + irq = isp_pci->pci_dev->irq; + + if (vid != PCI_VENDOR_ID_QLOGIC) { + printk("%s: 0x%04x is not QLogic's PCI Vendor ID\n", loc, vid); + return (1); + } + + isp_pci->poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; + isp_pci->poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; + isp_pci->poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; + isp_pci->poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; + isp_pci->poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; + switch (did) { + case PCI_DEVICE_ID_QLOGIC_ISP1020: + break; + case PCI_DEVICE_ID_QLOGIC_ISP1080: + case PCI_DEVICE_ID_QLOGIC_ISP1240: + case PCI_DEVICE_ID_QLOGIC_ISP1280: + case PCI_DEVICE_ID_QLOGIC_ISP10160: + case PCI_DEVICE_ID_QLOGIC_ISP12160: + isp_pci->poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; + break; + case PCI_DEVICE_ID_QLOGIC_ISP2200: + case PCI_DEVICE_ID_QLOGIC_ISP2100: + isp_pci->poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; + break; + case PCI_DEVICE_ID_QLOGIC_ISP2300: + pci_cmd_isp &= ~PCI_COMMAND_INVALIDATE; /* per errata */ + isp_pci->poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; + break; + case PCI_DEVICE_ID_QLOGIC_ISP2312: + isp->isp_port = PCI_FUNC(isp_pci->pci_dev->devfn); + isp_pci->poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; + break; + default: + printk("%s: Device ID 0x%04x is not a known Qlogic Device", loc, did); + return (1); + } + + /* + * Bump unit seed- we're here, whether we complete the attachment or not. + */ + isp->isp_unit = isp_unit_seed++; + sprintf(isp->isp_name, "isp%d", isp->isp_unit); + + isp->isp_osinfo.device_id = + ((isp_pci->pci_dev->bus->number) << 16) | + (PCI_SLOT(isp_pci->pci_dev->devfn) << 8) | + (PCI_FUNC(isp_pci->pci_dev->devfn)); + + if (isp_disable & (1 << isp->isp_unit)) { + isp_prt(isp, ISP_LOGALL, "disabled at user request"); + return (1); + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + if (pci_enable_device(isp_pci->pci_dev)) { + printk("%s: fails to be PCI_ENABLEd\n", loc); + return (1); + } + (void) PRDW(isp_pci, PCI_COMMAND, &cmd); +#endif + + if ((cmd & PCI_CMD_ISP) != pci_cmd_isp) { + if (isp_debug & ISP_LOGINFO) + printk("%s: rewriting command register from 0x%x to 0x%x\n", + loc, cmd, (cmd & ~PCI_CMD_ISP) | pci_cmd_isp); + cmd &= ~PCI_CMD_ISP; + cmd |= pci_cmd_isp; + PWRW(isp_pci, PCI_COMMAND, cmd); + } + + if (lnsz != PCI_DFLT_LNSZ) { + if (isp_debug & ISP_LOGINFO) + printk("%s: rewriting cache line size from 0x%x to 0x%x\n", + loc, lnsz, PCI_DFLT_LNSZ); + lnsz = PCI_DFLT_LNSZ; + PWRB(isp_pci, PCI_CACHE_LINE_SIZE, lnsz); + } + +#ifdef __sparc__ + if (PRDB(isp_pci, PCI_MIN_GNT, &rev)) { + printk("%s: unable to read min grant\n", loc); + return (1); + } + if (rev) { + rev = (rev << 3) & 0xff; + } + if (rev == 0) { + rev = 64; + } + if (isp_debug & ISP_LOGINFO) { + printk("%s: rewriting latency timer from 0x%x to 0x%x\n", + loc, timer, rev); + } + PWRB(isp_pci, PCI_LATENCY_TIMER, rev); +#else + if (timer < PCI_DFLT_LTNCY) { + if (isp_debug & ISP_LOGINFO) + printk("%s: rewriting latency timer from 0x%x to 0x%x\n", + loc, timer, PCI_DFLT_LTNCY); + timer = PCI_DFLT_LTNCY; + PWRB(isp_pci, PCI_LATENCY_TIMER, timer); + } +#endif + + if ((cmd & (PCI_COMMAND_MEMORY|PCI_COMMAND_IO)) == 0) { +#ifdef __powerpc__ + if (io_base == 0 && mem_base == 0) { + printk("%s: you lose- no register access defined.\n", loc); + return (1); + } + if (io_base) + cmd |= PCI_COMMAND_IO; + if (mem_base) + cmd |= PCI_COMMAND_MEMORY; + PWRW(isp_pci, PCI_COMMAND, cmd); +#else + printk("%s: you lose- no register access defined.\n", loc); + return (1); +#endif + } + + /* + * Disable the ROM. + */ + PWRL(isp_pci, PCI_ROM_ADDRESS, 0); + + /* + * Set up stuff... + */ + isp_pci->port = isp_pci->vaddr = 0; + + /* + * If we prefer to map memory space over I/O, try that first. + */ + if (isp_pci_mapmem & (1 << isp->isp_unit)) { + if (map_isp_mem(isp_pci, cmd, mem_base) == 0) { + if (map_isp_io(isp_pci, cmd, io_base) == 0) { + isp_prt(isp, ISP_LOGERR, nomap); + return (1); + } + } + } else { + if (map_isp_io(isp_pci, cmd, io_base) == 0) { + if (map_isp_mem(isp_pci, cmd, mem_base) == 0) { + isp_prt(isp, ISP_LOGERR, nomap); + return (1); + } + } + } + if (isp_pci->vaddr) { + isp_prt(isp, ISP_LOGCONFIG, + "mapped memory 0x%lx at 0x%lx\n", isp_pci->paddr, isp_pci->vaddr); + host->io_port = isp_pci->paddr; + } else { + isp_prt(isp, ISP_LOGCONFIG, + "mapped I/O space at 0x%lx\n", isp_pci->port); + host->io_port = isp_pci->port; + } + host->irq = 0; + isp_pci->pci_isp.isp_revision = rev; +#ifndef ISP_DISABLE_1020_SUPPORT + if (did == PCI_DEVICE_ID_QLOGIC_ISP1020) { + isp_pci->pci_isp.isp_mdvec = &mdvec; + isp_pci->pci_isp.isp_type = ISP_HA_SCSI_UNKNOWN; + } +#endif +#ifndef ISP_DISABLE_1080_SUPPORT + if (did == PCI_DEVICE_ID_QLOGIC_ISP1080) { + isp_pci->pci_isp.isp_mdvec = &mdvec_1080; + isp_pci->pci_isp.isp_type = ISP_HA_SCSI_1080; + } + if (did == PCI_DEVICE_ID_QLOGIC_ISP1240) { + isp_pci->pci_isp.isp_mdvec = &mdvec_1080; + isp_pci->pci_isp.isp_type = ISP_HA_SCSI_1240; + host->max_channel = 1; + } + if (did == PCI_DEVICE_ID_QLOGIC_ISP1280) { + isp_pci->pci_isp.isp_mdvec = &mdvec_1080; + isp_pci->pci_isp.isp_type = ISP_HA_SCSI_1280; + host->max_channel = 1; + } +#endif +#ifndef ISP_DISABLE_12160_SUPPORT + if (did == PCI_DEVICE_ID_QLOGIC_ISP10160) { + isp_pci->pci_isp.isp_mdvec = &mdvec_12160; + isp_pci->pci_isp.isp_type = ISP_HA_SCSI_12160; + } + if (did == PCI_DEVICE_ID_QLOGIC_ISP12160) { + isp_pci->pci_isp.isp_mdvec = &mdvec_12160; + isp_pci->pci_isp.isp_type = ISP_HA_SCSI_12160; + host->max_channel = 1; + } +#endif +#ifndef ISP_DISABLE_2100_SUPPORT + if (did == PCI_DEVICE_ID_QLOGIC_ISP2100) { + isp_pci->pci_isp.isp_mdvec = &mdvec_2100; + isp_pci->pci_isp.isp_type = ISP_HA_FC_2100; + } +#endif +#ifndef ISP_DISABLE_2200_SUPPORT + if (did == PCI_DEVICE_ID_QLOGIC_ISP2200) { + isp_pci->pci_isp.isp_mdvec = &mdvec_2200; + isp_pci->pci_isp.isp_type = ISP_HA_FC_2200; + } +#endif +#ifndef ISP_DISABLE_2300_SUPPORT + if (did == PCI_DEVICE_ID_QLOGIC_ISP2300) { + isp_pci->pci_isp.isp_mdvec = &mdvec_2300; + isp_pci->pci_isp.isp_type = ISP_HA_FC_2300; + } + if (did == PCI_DEVICE_ID_QLOGIC_ISP2312) { + isp_pci->pci_isp.isp_mdvec = &mdvec_2300; + isp_pci->pci_isp.isp_type = ISP_HA_FC_2312; + } +#endif + + if (request_irq(irq, isplinux_intr, SA_SHIRQ, isp->isp_name, isp_pci)) { + isp_prt(isp, ISP_LOGERR, "could not snag irq %u (0x%x)", irq, irq); + goto bad; + } + host->irq = irq; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) + host->select_queue_depths = isplinux_sqd; +#endif + isp->isp_param = &isp_pci->params; +#ifdef LINUX_ISP_TARGET_MODE + isp->isp_osinfo.pool = isp_pci->rpool; +#endif +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,19) + host->highmem_io = 0; + if (ISP_A64 && (IS_FC(isp) || IS_ULTRA2(isp) || IS_1240(isp))) { + if (pci_set_dma_mask(isp_pci->pci_dev, (u64) 0xffffffffffffffffULL)) { + if (pci_set_dma_mask(isp_pci->pci_dev, (u64)0xffffffff)) { + isp_prt(isp, ISP_LOGERR, "cannot set 32 bit dma mask"); + goto bad; + } + } else { + isp_prt(isp, ISP_LOGCONFIG, "enabling 64 bit DMA"); + } + host->highmem_io = 1; + } +#endif + + /* + * At this point, we're committed to keeping this adapter around. + */ + isplinux_common_init(isp); + return (0); +bad: + if (host->irq) { + DISABLE_INTS(isp); + free_irq(host->irq, isp_pci); + host->irq = 0; + } + if (isp_pci->vaddr != 0) { + unmap_pci_mem(isp_pci->vaddr, 0xff); + isp_pci->vaddr = 0; + } else { + release_region(isp_pci->port, 0xff); + isp_pci->port = 0; + } + return (1); +} + +static INLINE u_int16_t +ispregrd(struct isp_pcisoftc *pcs, vm_offset_t offset) +{ + u_int16_t rv; + if (pcs->vaddr) { + offset += pcs->vaddr; + rv = readw(offset); + } else { + offset += pcs->port; + rv = inw(offset); + } + return (rv); +} + +static INLINE void +ispregwr(struct isp_pcisoftc *pcs, vm_offset_t offset, u_int16_t val) +{ + if (pcs->vaddr) { + offset += pcs->vaddr; + writew(val, offset); + } else { + offset += pcs->port; + outw(val, offset); + } + MEMORYBARRIER(isp, SYNC_REG, offset, 2); +} + +static INLINE int +isp_pci_rd_debounced(struct isp_pcisoftc *pcs, vm_offset_t off, u_int16_t *rp) +{ + u_int16_t val0, val1; + int i = 0; + do { + val0 = ispregrd(pcs, off); + val1 = ispregrd(pcs, off); + } while (val0 != val1 && ++i < 1000); + if (val0 != val1) { + return (1); + } + *rp = val0; + return (0); +} + +#define IspVirt2Off(a, x) \ + ((a)->poff[((x) & _BLK_REG_MASK) >> _BLK_REG_SHFT] + ((x) & 0xff)) + +static int +isp_pci_rd_isr(struct ispsoftc *isp, u_int16_t *isrp, + u_int16_t *semap, u_int16_t *mbp) +{ + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; + u_int16_t isr, sema; + + if (IS_2100(isp)) { + if (isp_pci_rd_debounced(pcs, IspVirt2Off(pcs, BIU_ISR), &isr)) { + return (0); + } + if (isp_pci_rd_debounced(pcs, IspVirt2Off(pcs, BIU_SEMA), &sema)) { + return (0); + } + } else { + isr = ispregrd(pcs, IspVirt2Off(pcs, BIU_ISR)); + sema = ispregrd(pcs, IspVirt2Off(pcs, BIU_SEMA)); + } + isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); + isr &= INT_PENDING_MASK(isp); + sema &= BIU_SEMA_LOCK; + if (isr == 0 && sema == 0) { + return (0); + } + *isrp = isr; + if ((*semap = sema) != 0) { + if (IS_2100(isp)) { + if (isp_pci_rd_debounced(pcs, IspVirt2Off(pcs, OUTMAILBOX0), mbp)) { + return (0); + } + } else { + *mbp = ispregrd(pcs, IspVirt2Off(pcs, OUTMAILBOX0)); + } + } + return (1); +} + +#ifndef ISP_DISABLE_2300_SUPPORT +static INLINE u_int32_t +ispregrd32(struct isp_pcisoftc *pcs, vm_offset_t offset) +{ + u_int32_t rv; + if (pcs->vaddr) { + offset += pcs->vaddr; + rv = readl(offset); + } else { + offset += pcs->port; + rv = inl(offset); + } + return (rv); +} + +static int +isp_pci_rd_isr_2300(struct ispsoftc *isp, u_int16_t *isrp, + u_int16_t *semap, u_int16_t *mbox0p) +{ + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; + u_int32_t r2hisr; + + /* + * Avoid parity errors on the 2312. + */ + if (!(ispregrd(pcs, IspVirt2Off(pcs, BIU_ISR)) & BIU2100_ISR_RISC_INT)) { + *isrp = 0; + return (0); + } + + r2hisr = ispregrd32(pcs, IspVirt2Off(pcs, BIU_R2HSTSLO)); + isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); + if ((r2hisr & BIU_R2HST_INTR) == 0) { + *isrp = 0; + return (0); + } + switch (r2hisr & BIU_R2HST_ISTAT_MASK) { + case ISPR2HST_ROM_MBX_OK: + case ISPR2HST_ROM_MBX_FAIL: + case ISPR2HST_MBX_OK: + case ISPR2HST_MBX_FAIL: + case ISPR2HST_ASYNC_EVENT: + *isrp = r2hisr & 0xffff; + *mbox0p = (r2hisr >> 16); + *semap = 1; + return (1); + case ISPR2HST_RIO_16: + *isrp = r2hisr & 0xffff; + *mbox0p = ASYNC_RIO1; + *semap = 1; + return (1); + case ISPR2HST_FPOST: + *isrp = r2hisr & 0xffff; + *mbox0p = ASYNC_CMD_CMPLT; + *semap = 1; + return (1); + case ISPR2HST_FPOST_CTIO: + *isrp = r2hisr & 0xffff; + *mbox0p = ASYNC_CTIO_DONE; + *semap = 1; + return (1); + case ISPR2HST_RSPQ_UPDATE: + *isrp = r2hisr & 0xffff; + *mbox0p = 0; + *semap = 0; + return (1); + default: + return (0); + } +} +#endif + +static u_int16_t +isp_pci_rd_reg(struct ispsoftc *isp, int regoff) +{ + u_int16_t rv, oldconf = 0; + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; + + if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { + /* + * We will assume that someone has paused the RISC processor. + */ + oldconf = ispregrd(pcs, IspVirt2Off(pcs, BIU_CONF1)); + ispregwr(pcs, IspVirt2Off(pcs, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); + } + rv = ispregrd(pcs, IspVirt2Off(pcs, regoff)); + if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { + ispregwr(pcs, IspVirt2Off(pcs, BIU_CONF1), oldconf); + } + return (rv); +} + +static void +isp_pci_wr_reg(struct ispsoftc *isp, int regoff, u_int16_t val) +{ + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; + u_int16_t oldconf = 0; + if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { + /* + * We will assume that someone has paused the RISC processor. + */ + oldconf = ispregrd(pcs, IspVirt2Off(pcs, BIU_CONF1)); + ispregwr(pcs, IspVirt2Off(pcs, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); + } + ispregwr(pcs, IspVirt2Off(pcs, regoff), val); + if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { + ispregwr(pcs, IspVirt2Off(pcs, BIU_CONF1), oldconf); + } +} + +#if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) +static u_int16_t +isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) +{ + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; + u_int16_t rv, oldconf = 0; + + if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || + (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { + u_int16_t tmpconf; + /* + * We will assume that someone has paused the RISC processor. + */ + oldconf = ispregrd(pcs, IspVirt2Off(pcs, BIU_CONF1)); + tmpconf = oldconf & ~BIU_PCI1080_CONF1_DMA; + if (IS_1280(isp)) { + if (regoff & SXP_BANK1_SELECT) { + tmpconf |= BIU_PCI1080_CONF1_SXP0; + } else { + tmpconf |= BIU_PCI1080_CONF1_SXP1; + } + } else { + tmpconf |= BIU_PCI1080_CONF1_SXP0; + } + ispregwr(pcs, IspVirt2Off(pcs, BIU_CONF1), tmpconf); + } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { + oldconf = ispregrd(pcs, IspVirt2Off(pcs, BIU_CONF1)); + ispregwr(pcs, IspVirt2Off(pcs, BIU_CONF1), + oldconf | BIU_PCI1080_CONF1_DMA); + } + rv = ispregrd(pcs, IspVirt2Off(pcs, regoff)); + if (oldconf) { + ispregwr(pcs, IspVirt2Off(pcs, BIU_CONF1), oldconf); + } + return (rv); +} + +static void +isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, u_int16_t val) +{ + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; + u_int16_t oldconf = 0; + + if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || + (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { + u_int16_t tmpconf; + /* + * We will assume that someone has paused the RISC processor. + */ + oldconf = ispregrd(pcs, IspVirt2Off(pcs, BIU_CONF1)); + tmpconf = oldconf & ~BIU_PCI1080_CONF1_DMA; + if (IS_1280(isp)) { + if (regoff & SXP_BANK1_SELECT) { + tmpconf |= BIU_PCI1080_CONF1_SXP0; + } else { + tmpconf |= BIU_PCI1080_CONF1_SXP1; + } + } else { + tmpconf |= BIU_PCI1080_CONF1_SXP0; + } + ispregwr(pcs, IspVirt2Off(pcs, BIU_CONF1), tmpconf); + } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { + oldconf = ispregrd(pcs, IspVirt2Off(pcs, BIU_CONF1)); + ispregwr(pcs, IspVirt2Off(pcs, BIU_CONF1), + oldconf | BIU_PCI1080_CONF1_DMA); + } + ispregwr(pcs, IspVirt2Off(pcs, regoff), val); + if (oldconf) { + ispregwr(pcs, IspVirt2Off(pcs, BIU_CONF1), oldconf); + } +} +#endif + +static int +isp_pci_mbxdma(struct ispsoftc *isp) +{ + if (isp->isp_xflist == NULL) { + size_t amt = isp->isp_maxcmds * sizeof (XS_T **); + isp->isp_xflist = kmalloc(amt, GFP_KERNEL); + if (isp->isp_xflist == NULL) { + isp_prt(isp, ISP_LOGERR, "unable to allocate xflist array"); + return (1); + } + MEMZERO(isp->isp_xflist, amt); + } + if (isp->isp_rquest == NULL) { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; + dma_addr_t busaddr; + isp->isp_rquest = + pci_alloc_consistent(pcs->pci_dev, + RQUEST_QUEUE_LEN(isp) * QENTRY_LEN, &busaddr); + if (isp->isp_rquest == NULL) { + isp_prt(isp, ISP_LOGERR, "unable to allocate request queue"); + return (1); + } + isp->isp_rquest_dma = busaddr; +#else + isp->isp_rquest = (caddr_t) GetPages(IspOrder(RQUEST_QUEUE_LEN(isp))); + if (isp->isp_rquest == NULL) { + isp_prt(isp, ISP_LOGERR, "unable to allocate request queue"); + return (1); + } + /* + * Map the Request queue. + */ + isp->isp_rquest_dma = virt_to_bus(isp->isp_rquest); +#endif + if (isp->isp_rquest_dma & 0x3f) { + isp_prt(isp, ISP_LOGERR, "Request Queue not on 64 byte boundary"); + return (1); + } + MEMZERO(isp->isp_rquest, ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp))); + } + + if (isp->isp_result == NULL) { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; + dma_addr_t busaddr; + isp->isp_result = + pci_alloc_consistent(pcs->pci_dev, + RESULT_QUEUE_LEN(isp) * QENTRY_LEN, &busaddr); + if (isp->isp_result == NULL) { + isp_prt(isp, ISP_LOGERR, "unable to allocate result queue"); + return (1); + } + isp->isp_result_dma = busaddr; +#else + isp->isp_result = (caddr_t) GetPages(IspOrder(RESULT_QUEUE_LEN(isp))); + if (isp->isp_result == NULL) { + isp_prt(isp, ISP_LOGERR, "unable to allocate result queue"); + free_pages((unsigned long)isp->isp_rquest, + IspOrder(RQUEST_QUEUE_LEN(isp))); + return (1); + } + /* + * Map the result queue. + */ + isp->isp_result_dma = virt_to_bus(isp->isp_result); +#endif + if (isp->isp_rquest_dma & 0x3f) { + isp_prt(isp, ISP_LOGERR, "Result Queue not on 64 byte boundary"); + return (1); + } + MEMZERO(isp->isp_result, ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp))); + } + + if (IS_FC(isp)) { + fcparam *fcp = isp->isp_param; + if (fcp->isp_scratch == NULL) { +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,3,92) + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; + dma_addr_t busaddr; + fcp->isp_scratch = + pci_alloc_consistent(pcs->pci_dev, ISP2100_SCRLEN, &busaddr); + if (fcp->isp_scratch == NULL) { + isp_prt(isp, ISP_LOGERR, "unable to allocate scratch space"); + return (1); + } + fcp->isp_scdma = busaddr; +#else + /* + * Just get a page.... + */ + fcp->isp_scratch = (void *) GetPages(1); + if (fcp->isp_scratch == NULL) { + isp_prt(isp, ISP_LOGERR, "unable to allocate scratch space"); + return (1); + } + fcp->isp_scdma = virt_to_bus((void *)fcp->isp_scratch); +#endif + MEMZERO(fcp->isp_scratch, ISP2100_SCRLEN); + if (fcp->isp_scdma & 0x7) { + isp_prt(isp, ISP_LOGERR, "scratch space not 8 byte aligned"); + return (1); + } + } + } + return (0); +} + +#ifdef LINUX_ISP_TARGET_MODE +/* + * We need to handle DMA for target mode differently from initiator mode. + * + * DMA mapping and construction and submission of CTIO Request Entries + * and rendevous for completion are very tightly coupled because we start + * out by knowing (per platform) how much data we have to move, but we + * don't know, up front, how many DMA mapping segments will have to be used + * cover that data, so we don't know how many CTIO Request Entries we + * will end up using. Further, for performance reasons we may want to + * (on the last CTIO for Fibre Channel), send status too (if all went well). + * + * The standard vector still goes through isp_pci_dmasetup, but the callback + * for the DMA mapping routines comes here instead with the whole transfer + * mapped and a pointer to a partially filled in already allocated request + * queue entry. We finish the job. + */ +static int tdma_mk(struct ispsoftc *, tmd_cmd_t *, ct_entry_t *, + u_int16_t *, u_int16_t); +static int tdma_mkfc(struct ispsoftc *, tmd_cmd_t *, ct2_entry_t *, + u_int16_t *, u_int16_t); + +#define STATUS_WITH_DATA 1 + +static int +tdma_mk(struct ispsoftc *isp, tmd_cmd_t *tcmd, ct_entry_t *cto, + u_int16_t *nxtip, u_int16_t optr) +{ + static const char ctx[] = + "CTIO[%x] lun %d for iid%d flgs 0x%x sts 0x%x ssts 0x%x res %u %s"; + struct scatterlist *sg; + ct_entry_t *qe; + u_int8_t scsi_status; + u_int16_t curi, nxti, handle; + u_int32_t sflags; + int32_t resid; + int nth_ctio, nctios, send_status, nseg; + + + curi = isp->isp_reqidx; + qe = (ct_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, isp->isp_reqidx); + + cto->ct_xfrlen = 0; + cto->ct_seg_count = 0; + cto->ct_header.rqs_entry_count = 1; + MEMZERO(cto->ct_dataseg, sizeof (cto->ct_dataseg)); + + if (tcmd->cd_xfrlen == 0) { + ISP_TDQE(isp, "tdma_mk[no data]", curi, cto); + isp_prt(isp, ISP_LOGTDEBUG1, ctx, cto->ct_fwhandle, (int) tcmd->cd_lun, + (int) cto->ct_iid, cto->ct_flags, cto->ct_status, + cto->ct_scsi_status, cto->ct_resid, ""); + isp_put_ctio(isp, cto, qe); + return (CMD_QUEUED); + } + + sg = tcmd->cd_data; + nseg = 0; + resid = (int32_t) tcmd->cd_xfrlen; + while (resid > 0) { + nseg++; + resid -= sg->length; + sg++; + } + sg = tcmd->cd_data; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + { + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; + int new_seg_cnt; + new_seg_cnt = pci_map_sg(pcs->pci_dev, sg, nseg, + (cto->ct_flags & CT_DATA_IN)? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE); + if (new_seg_cnt == 0) { + isp_prt(isp, ISP_LOGWARN, "unable to dma map request"); + cto->ct_resid = -ENOMEM; + return (CMD_COMPLETE); + } + if (new_seg_cnt != nseg) { + isp_prt(isp, ISP_LOGERR, "new seg cnt != old"); + cto->ct_resid = -EINVAL; + return (CMD_COMPLETE); + } + } +#endif + nctios = nseg / ISP_RQDSEG; + if (nseg % ISP_RQDSEG) { + nctios++; + } + + /* + * Save handle, and potentially any SCSI status, which + * we'll reinsert on the last CTIO we're going to send. + */ + handle = cto->ct_syshandle; + cto->ct_syshandle = 0; + cto->ct_header.rqs_seqno = 0; + send_status = (cto->ct_flags & CT_SENDSTATUS) != 0; + + if (send_status) { + sflags = cto->ct_flags & (CT_SENDSTATUS | CT_CCINCR); + cto->ct_flags &= ~(CT_SENDSTATUS|CT_CCINCR); + /* + * Preserve residual. + */ + resid = cto->ct_resid; + + /* + * Save actual SCSI status. + */ + scsi_status = cto->ct_scsi_status; + +#ifndef STATUS_WITH_DATA + sflags |= CT_NO_DATA; + /* + * We can't do a status at the same time as a data CTIO, so + * we need to synthesize an extra CTIO at this level. + */ + nctios++; +#endif + } else { + sflags = scsi_status = resid = 0; + } + + cto->ct_resid = 0; + cto->ct_scsi_status = 0; + + nxti = *nxtip; + + for (nth_ctio = 0; nth_ctio < nctios; nth_ctio++) { + int seglim; + + seglim = nseg; + if (seglim) { + int seg; + + if (seglim > ISP_RQDSEG) + seglim = ISP_RQDSEG; + + for (seg = 0; seg < seglim; seg++, nseg--) { + /* + * Unlike normal initiator commands, we don't do + * any swizzling here. + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) + cto->ct_dataseg[seg].ds_base = virt_to_bus(sg->address); +#else + cto->ct_dataseg[seg].ds_base = (u_int32_t) sg_dma_address(sg); +#endif + cto->ct_dataseg[seg].ds_count = (u_int32_t) sg->length; + cto->ct_xfrlen += sg->length; + sg++; + } + cto->ct_seg_count = seg; + } else { + /* + * This case should only happen when we're + * sending an extra CTIO with final status. + */ + if (send_status == 0) { + isp_prt(isp, ISP_LOGERR, + "tdma_mk ran out of segments, no status to send"); + return (CMD_EAGAIN); + } + } + + /* + * At this point, the fields ct_lun, ct_iid, ct_tagval, ct_tagtype, and + * ct_timeout have been carried over unchanged from what our caller had + * set. + * + * The dataseg fields and the seg_count fields we just got through + * setting. The data direction we've preserved all along and only + * clear it if we're now sending status. + */ + + if (nth_ctio == nctios - 1) { + /* + * We're the last in a sequence of CTIOs, so mark this + * CTIO and save the handle to the command such that when + * this CTIO completes we can free dma resources and + * do whatever else we need to do to finish the rest + * of the command. + */ + cto->ct_syshandle = handle; + cto->ct_header.rqs_seqno = 1; + + if (send_status) { + cto->ct_scsi_status = scsi_status; + cto->ct_flags |= sflags; + cto->ct_resid = resid; + } + if (send_status) { + isp_prt(isp, ISP_LOGTDEBUG1, ctx, + cto->ct_fwhandle, (int) tcmd->cd_lun, (int) cto->ct_iid, + cto->ct_flags, cto->ct_status, cto->ct_scsi_status, + cto->ct_resid, ""); + } else { + isp_prt(isp, ISP_LOGTDEBUG1, ctx, + cto->ct_fwhandle, (int) tcmd->cd_lun, (int) cto->ct_iid, + cto->ct_flags, cto->ct_status, cto->ct_scsi_status, + cto->ct_resid, ""); + } + isp_put_ctio(isp, cto, qe); + ISP_TDQE(isp, "last tdma_mk", curi, cto); + if (nctios > 1) { + MEMORYBARRIER(isp, SYNC_REQUEST, curi, QENTRY_LEN); + } + } else { + ct_entry_t *oqe = qe; + + /* + * Make sure handle fields are clean + */ + cto->ct_syshandle = 0; + cto->ct_header.rqs_seqno = 0; + + isp_prt(isp, ISP_LOGTDEBUG1, + "CTIO[%x] lun%d for ID%d ct_flags 0x%x", + cto->ct_fwhandle, (int) tcmd->cd_lun, + (int) cto->ct_iid, cto->ct_flags); + + /* + * Get a new CTIO + */ + qe = (ct_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); + nxti = ISP_NXT_QENTRY(nxti, RQUEST_QUEUE_LEN(isp)); + if (nxti == optr) { + isp_prt(isp, ISP_LOGERR, "queue overflow in tdma_mk"); + return (CMD_EAGAIN); + } + + /* + * Now that we're done with the old CTIO, + * flush it out to the request queue. + */ + ISP_TDQE(isp, "tdma_mk", curi, cto); + isp_put_ctio(isp, cto, oqe); + if (nth_ctio != 0) { + MEMORYBARRIER(isp, SYNC_REQUEST, curi, QENTRY_LEN); + } + curi = ISP_NXT_QENTRY(curi, RQUEST_QUEUE_LEN(isp)); + + /* + * Reset some fields in the CTIO so we can reuse + * for the next one we'll flush to the request + * queue. + */ + cto->ct_header.rqs_entry_type = RQSTYPE_CTIO; + cto->ct_header.rqs_entry_count = 1; + cto->ct_header.rqs_flags = 0; + cto->ct_status = 0; + cto->ct_scsi_status = 0; + cto->ct_xfrlen = 0; + cto->ct_resid = 0; + cto->ct_seg_count = 0; + MEMZERO(cto->ct_dataseg, sizeof (cto->ct_dataseg)); + } + } + *nxtip = nxti; + return (CMD_QUEUED); +} + +static int +tdma_mkfc(struct ispsoftc *isp, tmd_cmd_t *tcmd, ct2_entry_t *cto, + u_int16_t *nxtip, u_int16_t optr) +{ + static const char ctx[] = + "CTIO2[%x] lun %d for iid %d flgs 0x%x sts 0x%x ssts 0x%x res %d %s"; + u_int8_t sense[QLTM_SENSELEN]; + struct scatterlist *sg; + ct2_entry_t *qe; + u_int16_t send_status, scsi_status, send_sense, handle; + u_int16_t curi, nxti; + int32_t resid; + int nth_ctio, nctios, nseg; + + curi = isp->isp_reqidx; + qe = (ct2_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curi); + + if (tcmd->cd_xfrlen == 0) { + if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE1) { + isp_prt(isp, ISP_LOGERR, + "tdma_mkfc, a status CTIO2 without MODE1 set (0x%x)", + cto->ct_flags); + cto->ct_resid = -EINVAL; + return (CMD_COMPLETE); + } + cto->ct_header.rqs_entry_count = 1; + cto->ct_header.rqs_seqno = 1; + + /* ct_syshandle contains the synchronization handle set by caller */ + /* + * We preserve ct_lun, ct_iid, ct_rxid. We set the data movement + * flags to NO DATA and clear relative offset flags. We preserve + * ct_resid and the response area. + */ + cto->ct_flags |= CT2_NO_DATA; + if (cto->ct_resid > 0) + cto->rsp.m1.ct_scsi_status |= CT2_DATA_UNDER; + else if (cto->ct_resid < 0) + cto->rsp.m1.ct_scsi_status |= CT2_DATA_OVER; + cto->ct_seg_count = 0; + cto->ct_reloff = 0; + isp_prt(isp, ISP_LOGTDEBUG1, ctx, cto->ct_rxid, (int) tcmd->cd_lun, + cto->ct_iid, cto->ct_flags, cto->ct_status, + cto->rsp.m1.ct_scsi_status, cto->ct_resid, ""); + isp_put_ctio2(isp, cto, qe); + ISP_TDQE(isp, "tdma_mkfc[no data]", curi, qe); + return (CMD_QUEUED); + } + + if ((cto->ct_flags & CT2_FLAG_MMASK) != CT2_FLAG_MODE0) { + isp_prt(isp, ISP_LOGERR, + "tdma_mkfc, a data CTIO2 without MODE0 set (0x%x)", cto->ct_flags); + cto->ct_resid = -EINVAL; + return (CMD_COMPLETE); + } + + sg = tcmd->cd_data; + nseg = 0; + resid = (int32_t) tcmd->cd_xfrlen; + while (resid > 0) { + nseg++; + resid -= sg->length; + sg++; + } + sg = tcmd->cd_data; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) + { + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; + int new_seg_cnt; + new_seg_cnt = pci_map_sg(pcs->pci_dev, sg, nseg, + (cto->ct_flags & CT2_DATA_IN)? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE); + if (new_seg_cnt == 0) { + isp_prt(isp, ISP_LOGWARN, "unable to dma map request"); + cto->ct_resid = -ENOMEM; + return (CMD_COMPLETE); + } + if (new_seg_cnt != nseg) { + isp_prt(isp, ISP_LOGERR, "new seg cnt != old"); + cto->ct_resid = -EINVAL; + return (CMD_COMPLETE); + } + } +#endif + nctios = nseg / ISP_RQDSEG_T2; + if (nseg % ISP_RQDSEG_T2) { + nctios++; + } + + /* + * Save the handle, status, reloff, and residual. We'll reinsert the + * handle into the last CTIO2 we're going to send, and reinsert status + * and residual (and possibly sense data) if that's to be sent as well. + * + * We preserve ct_reloff and adjust it for each data CTIO2 we send past + * the first one. This is needed so that the FCP DATA IUs being sent out + * have the correct offset (they can arrive at the other end out of order). + */ + + handle = cto->ct_syshandle; + cto->ct_syshandle = 0; + send_status = (cto->ct_flags & CT2_SENDSTATUS) != 0; + + if (send_status) { + cto->ct_flags &= ~(CT2_SENDSTATUS|CT2_CCINCR); + + /* + * Preserve residual. + */ + resid = cto->ct_resid; + + /* + * Save actual SCSI status. We'll reinsert the CT2_SNSLEN_VALID + * later if appropriate. + */ + scsi_status = cto->rsp.m0.ct_scsi_status & 0xff; + send_sense = cto->rsp.m0.ct_scsi_status & CT2_SNSLEN_VALID; + + /* + * If we're sending status and have a CHECK CONDTION and + * have sense data, we send one more CTIO2 with just the + * status and sense data. The upper layers have stashed + * the sense data in the dataseg structure for us. + */ + + if ((scsi_status & 0xf) == SCSI_CHECK && send_sense) { + MEMCPY(sense, cto->rsp.m0.ct_dataseg, QLTM_SENSELEN); + nctios++; + } + } else { + scsi_status = send_sense = resid = 0; + } + + cto->ct_resid = 0; + cto->rsp.m0.ct_scsi_status = 0; + MEMZERO(&cto->rsp, sizeof (cto->rsp)); + + nxti = *nxtip; + + for (nth_ctio = 0; nth_ctio < nctios; nth_ctio++) { + u_int32_t oxfrlen; + int seglim; + + seglim = nseg; + if (seglim) { + int seg; + + if (seglim > ISP_RQDSEG_T2) + seglim = ISP_RQDSEG_T2; + + for (seg = 0; seg < seglim; seg++, nseg--) { + /* + * Unlike normal initiator commands, we don't do + * any swizzling here. + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) + cto->rsp.m0.ct_dataseg[seg].ds_base = virt_to_bus(sg->address); +#else + cto->rsp.m0.ct_dataseg[seg].ds_base = + (u_int32_t) sg_dma_address(sg); +#endif + cto->rsp.m0.ct_dataseg[seg].ds_count = (u_int32_t) sg->length; + cto->rsp.m0.ct_xfrlen += sg->length; + sg++; + } + cto->ct_seg_count = seg; + oxfrlen = cto->rsp.m0.ct_xfrlen; + } else { + /* + * This case should only happen when we're sending a synthesized + * MODE1 final status with sense data. + */ + if (send_sense == 0) { + isp_prt(isp, ISP_LOGERR, + "tdma_mkfc ran out of segments, no SENSE DATA"); + cto->ct_resid = -EINVAL; + return (CMD_COMPLETE); + } + oxfrlen = 0; + } + + /* + * At this point, the fields ct_lun, ct_iid, ct_rxid, ct_timeout + * have been carried over unchanged from what our caller had set. + * + * The field ct_reloff is either what the caller set, or what we've + * added to below. + * + * The dataseg fields and the seg_count fields we just got through + * setting. The data direction we've preserved all along and only + * clear it if we're sending a MODE1 status as the last CTIO. + * + */ + + if (nth_ctio == nctios - 1) { + /* + * We're the last in a sequence of CTIO2s, so mark this + * CTIO2 and save the handle to the CCB such that when + * this CTIO2 completes we can free dma resources and + * do whatever else we need to do to finish the rest + * of the command. + */ + + cto->ct_syshandle = handle; + cto->ct_header.rqs_seqno = 1; + + if (send_status) { + /* + * Get 'real' residual and set flags based on it. + */ + cto->ct_resid = resid; + if (send_sense) { + MEMCPY(cto->rsp.m1.ct_resp, sense, QLTM_SENSELEN); + cto->rsp.m1.ct_senselen = QLTM_SENSELEN; + scsi_status |= CT2_SNSLEN_VALID; + cto->rsp.m1.ct_scsi_status = scsi_status; + cto->ct_flags &= CT2_FLAG_MMASK; + cto->ct_flags |= CT2_FLAG_MODE1 | CT2_NO_DATA | + CT2_SENDSTATUS | CT2_CCINCR; + if (cto->ct_resid > 0) + cto->rsp.m1.ct_scsi_status |= CT2_DATA_UNDER; + else if (cto->ct_resid < 0) + cto->rsp.m1.ct_scsi_status |= CT2_DATA_OVER; + } else { + cto->rsp.m0.ct_scsi_status = scsi_status; + cto->ct_flags |= CT2_SENDSTATUS | CT2_CCINCR; + if (cto->ct_resid > 0) + cto->rsp.m0.ct_scsi_status |= CT2_DATA_UNDER; + else if (cto->ct_resid < 0) + cto->rsp.m0.ct_scsi_status |= CT2_DATA_OVER; + } + } + isp_prt(isp, ISP_LOGTDEBUG1, ctx, cto->ct_rxid, (int) tcmd->cd_lun, + cto->ct_iid, cto->ct_flags, cto->ct_status, + cto->rsp.m1.ct_scsi_status, cto->ct_resid, ""); + isp_put_ctio2(isp, cto, qe); + ISP_TDQE(isp, "last tdma_mkfc", curi, cto); + if (nctios > 1) { + MEMORYBARRIER(isp, SYNC_REQUEST, curi, QENTRY_LEN); + } + } else { + ct2_entry_t *oqe = qe; + + /* + * Make sure handle fields are clean + */ + cto->ct_syshandle = 0; + cto->ct_header.rqs_seqno = 0; + + isp_prt(isp, ISP_LOGTDEBUG1, ctx, cto->ct_rxid, (int) tcmd->cd_lun, + cto->ct_iid, cto->ct_flags, cto->ct_status, + cto->rsp.m1.ct_scsi_status, cto->ct_resid, ""); + /* + * Get a new CTIO2 entry from the request queue. + */ + qe = (ct2_entry_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, nxti); + nxti = ISP_NXT_QENTRY(nxti, RQUEST_QUEUE_LEN(isp)); + if (nxti == optr) { + isp_prt(isp, ISP_LOGERR, "queue overflow in tdma_mkfc"); + return (CMD_EAGAIN); + } + + /* + * Now that we're done with the old CTIO2, + * flush it out to the request queue. + */ + ISP_TDQE(isp, "tdma_mkfc", curi, cto); + isp_put_ctio2(isp, cto, oqe); + if (nth_ctio != 0) { + MEMORYBARRIER(isp, SYNC_REQUEST, curi, QENTRY_LEN); + } + curi = ISP_NXT_QENTRY(curi, RQUEST_QUEUE_LEN(isp)); + + /* + * Reset some fields in the CTIO2 so we can reuse + * for the next one we'll flush to the request + * queue. + */ + cto->ct_header.rqs_entry_type = RQSTYPE_CTIO2; + cto->ct_header.rqs_entry_count = 1; + cto->ct_header.rqs_flags = 0; + cto->ct_status = 0; + cto->ct_resid = 0; + cto->ct_seg_count = 0; + /* + * Adjust the new relative offset by the amount which is + * recorded in the data segment of the old CTIO2 we just + * finished filling out. + */ + cto->ct_reloff += oxfrlen; + MEMZERO(&cto->rsp, sizeof (cto->rsp)); + } + } + *nxtip = nxti; + return (CMD_QUEUED); +} +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) +#define FOURG_SEG(x) (((u64) (x)) & 0xffffffff00000000ULL) + +static int +isp_pci_dmasetup(struct ispsoftc *isp, Scsi_Cmnd *Cmnd, ispreq_t *rq, + u_int16_t *nxi, u_int16_t optr) +{ + struct scatterlist *sg, *savesg; + DMA_ADDR_T one_shot_addr, last_synthetic_addr; + unsigned int one_shot_length, last_synthetic_count; + int segcnt, seg, ovseg, seglim; + void *h; + u_int16_t nxti; + + +#ifdef LINUX_ISP_TARGET_MODE + if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO || + rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { + int s; + if (IS_SCSI(isp)) + s = tdma_mk(isp, (tmd_cmd_t *)Cmnd, (ct_entry_t *)rq, nxi, optr); + else + s = tdma_mkfc(isp, (tmd_cmd_t *)Cmnd, (ct2_entry_t *)rq, nxi, optr); + return (s); + } +#endif + + nxti = *nxi; + h = (void *) ISP_QUEUE_ENTRY(isp->isp_rquest, isp->isp_reqidx); + + if (Cmnd->sc_data_direction == SCSI_DATA_NONE || + Cmnd->request_bufflen == 0) { + rq->req_seg_count = 1; + goto mbxsync; + } + + if (IS_FC(isp)) { + seglim = ISP_RQDSEG_T2; + ((ispreqt2_t *)rq)->req_totalcnt = Cmnd->request_bufflen; + if (Cmnd->sc_data_direction == SCSI_DATA_WRITE) { + ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; + } else if (Cmnd->sc_data_direction == SCSI_DATA_READ) { + ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; + } else { + isp_prt(isp, ISP_LOGERR, + "unkown data direction (%x) for %d byte request (opcode 0x%x)", + Cmnd->sc_data_direction, Cmnd->request_bufflen, Cmnd->cmnd[0]); + XS_SETERR(Cmnd, HBA_BOTCH); + return (CMD_COMPLETE); + } + } else { + if (Cmnd->cmd_len > 12) + seglim = 0; + else + seglim = ISP_RQDSEG; + if (Cmnd->sc_data_direction == SCSI_DATA_WRITE) { + rq->req_flags |= REQFLAG_DATA_OUT; + } else if (Cmnd->sc_data_direction == SCSI_DATA_READ) { + rq->req_flags |= REQFLAG_DATA_IN; + } else { + isp_prt(isp, ISP_LOGERR, + "unkown data direction (%x) for %d byte request (opcode 0x%x)", + Cmnd->sc_data_direction, Cmnd->request_bufflen, Cmnd->cmnd[0]); + XS_SETERR(Cmnd, HBA_BOTCH); + return (CMD_COMPLETE); + } + } + + one_shot_addr = (DMA_ADDR_T) 0; + one_shot_length = 0; + if ((segcnt = Cmnd->use_sg) == 0) { + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; + segcnt = 1; + sg = NULL; + one_shot_length = Cmnd->request_bufflen; + one_shot_addr = pci_map_single(pcs->pci_dev, + Cmnd->request_buffer, Cmnd->request_bufflen, + scsi_to_pci_dma_dir(Cmnd->sc_data_direction)); + QLA_HANDLE(Cmnd) = (DMA_HTYPE_T) one_shot_addr; + } else { + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; + sg = (struct scatterlist *) Cmnd->request_buffer; + segcnt = pci_map_sg(pcs->pci_dev, sg, Cmnd->use_sg, + scsi_to_pci_dma_dir(Cmnd->sc_data_direction)); + } + if (segcnt == 0) { + isp_prt(isp, ISP_LOGWARN, "unable to dma map request"); + XS_SETERR(Cmnd, HBA_BOTCH); + return (CMD_EAGAIN); + } + savesg = sg; + +again: + last_synthetic_count = 0; + last_synthetic_addr = 0; + for (seg = 0, rq->req_seg_count = 0; + seg < segcnt && rq->req_seg_count < seglim; + seg++, rq->req_seg_count++) { + DMA_ADDR_T addr; + unsigned int length; + + if (sg) { + length = QLA_SG_C(sg); + addr = QLA_SG_A(sg); + sg++; + } else { + length = one_shot_length; + addr = one_shot_addr; + } + + if (ISP_A64 && IS_HIGH_ISP_ADDR(addr)) { + if (IS_FC(isp)) { + if (rq->req_header.rqs_entry_type != RQSTYPE_T3RQS) { + rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; + seglim = ISP_RQDSEG_T3; + sg = savesg; + goto again; + } + } else { + if (rq->req_header.rqs_entry_type != RQSTYPE_A64) { + rq->req_header.rqs_entry_type = RQSTYPE_A64; + seglim = ISP_RQDSEG_A64; + sg = savesg; + goto again; + } + } + } + if (ISP_A64 && rq->req_header.rqs_entry_type == RQSTYPE_T3RQS) { + ispreqt3_t *rq3 = (ispreqt3_t *)rq; + rq3->req_dataseg[rq3->req_seg_count].ds_count = length; + rq3->req_dataseg[rq3->req_seg_count].ds_base = LOWD(addr); + rq3->req_dataseg[rq3->req_seg_count].ds_basehi = HIWD(addr); + /* + * Make sure we don't cross a 4GB boundary. + */ + if (FOURG_SEG(addr) != FOURG_SEG(addr + length)) { + isp_prt(isp, ISP_LOGDEBUG1, "seg0[%d]%llx:%u (TRUNC'd)", + rq->req_seg_count, (long long)addr, length); + rq3->req_dataseg[rq3->req_seg_count].ds_count = + (unsigned int) (FOURG_SEG(addr + length) - addr); + addr += rq3->req_dataseg[rq3->req_seg_count].ds_count; + length -= rq3->req_dataseg[rq3->req_seg_count].ds_count; + /* + * Do we have space to split it here? + */ + if (rq3->req_seg_count == seglim - 1) { + last_synthetic_count = length; + last_synthetic_addr = addr; + } else { + rq3->req_seg_count++; + rq3->req_dataseg[rq3->req_seg_count].ds_count = length; + rq3->req_dataseg[rq3->req_seg_count].ds_base = LOWD(addr); + rq3->req_dataseg[rq3->req_seg_count].ds_basehi = HIWD(addr); + } + } + } else if (ISP_A64 && rq->req_header.rqs_entry_type == RQSTYPE_A64) { + ispreq64_t *rq6 = (ispreq64_t *)rq; + rq6->req_dataseg[rq6->req_seg_count].ds_count = length; + rq6->req_dataseg[rq6->req_seg_count].ds_base = LOWD(addr); + rq6->req_dataseg[rq6->req_seg_count].ds_basehi = HIWD(addr); + /* + * Make sure we don't cross a 4GB boundary. + */ + if (FOURG_SEG(addr) != FOURG_SEG(addr + length)) { + isp_prt(isp, ISP_LOGDEBUG1, "seg0[%d]%llx:%u (TRUNC'd)", + rq->req_seg_count, (long long)addr, length); + rq6->req_dataseg[rq6->req_seg_count].ds_count = + (unsigned int) (FOURG_SEG(addr + length) - addr); + addr += rq6->req_dataseg[rq6->req_seg_count].ds_count; + length -= rq6->req_dataseg[rq6->req_seg_count].ds_count; + /* + * Do we have space to split it here? + */ + if (rq6->req_seg_count == seglim - 1) { + last_synthetic_count = length; + last_synthetic_addr = LOWD(addr); + } else { + rq6->req_seg_count++; + rq6->req_dataseg[rq6->req_seg_count].ds_count = length; + rq6->req_dataseg[rq6->req_seg_count].ds_base = LOWD(addr); + rq6->req_dataseg[rq6->req_seg_count].ds_basehi = HIWD(addr); + } + } + } else if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { + ispreqt2_t *rq2 = (ispreqt2_t *)rq; + rq2->req_dataseg[rq2->req_seg_count].ds_count = length; + rq2->req_dataseg[rq2->req_seg_count].ds_base = addr; + } else { + rq->req_dataseg[rq->req_seg_count].ds_count = length; + rq->req_dataseg[rq->req_seg_count].ds_base = addr; + } + isp_prt(isp, ISP_LOGDEBUG1, "seg0[%d]%llx:%u", + rq->req_seg_count, (long long)addr, length); + } + + if (seg == segcnt && last_synthetic_count == 0) { + goto mbxsync; + } + + do { + int lim; + u_int16_t curip; + ispcontreq_t local, *crq = &local, *qep; + + curip = nxti; + qep = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curip); + nxti = ISP_NXT_QENTRY((curip), RQUEST_QUEUE_LEN(isp)); + if (nxti == optr) { + isp_pci_dmateardown(isp, Cmnd, 0); + isp_prt(isp, ISP_LOGDEBUG0, "out of space for continuations"); + XS_SETERR(Cmnd, HBA_BOTCH); + return (CMD_EAGAIN); + } + rq->req_header.rqs_entry_count++; + MEMZERO((void *)crq, sizeof (*crq)); + crq->req_header.rqs_entry_count = 1; + if (rq->req_header.rqs_entry_type == RQSTYPE_T3RQS || + rq->req_header.rqs_entry_type == RQSTYPE_A64) { + crq->req_header.rqs_entry_type = RQSTYPE_A64_CONT; + lim = ISP_CDSEG64; + } else { + crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; + lim = ISP_CDSEG; + } + + for (ovseg = 0; (seg < segcnt || last_synthetic_count) && ovseg < lim; + rq->req_seg_count++, seg++, ovseg++, sg++) { + DMA_ADDR_T addr; + unsigned int length; + + if (last_synthetic_count) { + addr = last_synthetic_addr; + length = last_synthetic_count; + last_synthetic_count = 0; + sg--; + seg--; + } else { + addr = QLA_SG_A(sg); + length = QLA_SG_C(sg); + } + + if (length == 0) { + panic("zero length s-g element at line %d", __LINE__); + } + isp_prt(isp, ISP_LOGDEBUG1, "seg%d[%d]%llx:%u", + rq->req_header.rqs_entry_count-1, ovseg, + (unsigned long long) addr, length); + + if (crq->req_header.rqs_entry_type == RQSTYPE_A64_CONT) { + ispcontreq64_t *xrq = (ispcontreq64_t *) crq; + xrq->req_dataseg[ovseg].ds_count = length; + xrq->req_dataseg[ovseg].ds_base = LOWD(addr); + xrq->req_dataseg[ovseg].ds_basehi = HIWD(addr); + /* + * Make sure we don't cross a 4GB boundary. + */ + if (FOURG_SEG(addr) != FOURG_SEG(addr + length)) { + isp_prt(isp, ISP_LOGDEBUG1, "seg0[%d]%llx:%u (TRUNC'd)", + rq->req_seg_count, (long long)addr, length); + xrq->req_dataseg[ovseg].ds_count = + (unsigned int) (FOURG_SEG(addr + length) - addr); + addr += xrq->req_dataseg[ovseg].ds_count; + length -= xrq->req_dataseg[ovseg].ds_count; + /* + * Do we have space to split it here? + */ + if (ovseg == lim - 1) { + last_synthetic_count = length; + last_synthetic_addr = addr; + } else { + ovseg++; + xrq->req_dataseg[ovseg].ds_count = length; + xrq->req_dataseg[ovseg].ds_base = LOWD(addr); + xrq->req_dataseg[ovseg].ds_basehi = HIWD(addr); + } + } + continue; + } + /* + * We get here if we're a 32 bit continuation entry. + * We also check for being over 32 bits with our PCI + * address. If we are, we set ourselves up to do 64 + * bit addressing and start the whole mapping process + * all over again- we apparently can't really mix types + */ + if (ISP_A64 && IS_HIGH_ISP_ADDR(addr)) { + if (IS_FC(isp)) { + rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; + seglim = ISP_RQDSEG_T3; + } else { + rq->req_header.rqs_entry_type = RQSTYPE_A64; + seglim = ISP_RQDSEG_A64; + } + sg = savesg; + nxti = *nxi; + rq->req_header.rqs_entry_count = 1; + goto again; + } + crq->req_dataseg[ovseg].ds_count = length; + crq->req_dataseg[ovseg].ds_base = addr; + } + MEMORYBARRIER(isp, SYNC_REQUEST, curip, QENTRY_LEN); + if (crq->req_header.rqs_entry_type == RQSTYPE_A64_CONT) { + isp_put_cont64_req(isp, + (ispcontreq64_t *)crq, (ispcontreq64_t *)qep); + } else { + isp_put_cont_req(isp, crq, qep); + } + } while (seg < segcnt || last_synthetic_count); +mbxsync: + if (rq->req_header.rqs_entry_type == RQSTYPE_T3RQS) { + isp_put_request_t3(isp, (ispreqt3_t *) rq, (ispreqt3_t *) h); + } else if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { + isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) h); + } else { + isp_put_request(isp, (ispreq_t *) rq, (ispreq_t *) h); + } + *nxi = nxti; + return (CMD_QUEUED); +} + +static void +isp_pci_dmateardown(struct ispsoftc *isp, Scsi_Cmnd *Cmnd, u_int16_t handle) +{ +#ifdef LINUX_ISP_TARGET_MODE + if (Cmnd->sc_magic != SCSI_CMND_MAGIC) { + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; + tmd_cmd_t *tcmd = (tmd_cmd_t *) Cmnd; + struct scatterlist *sg = tcmd->cd_data; + int nseg = 0; + + while (sg->address) { + nseg++; + sg++; + } + pci_unmap_sg(pcs->pci_dev, tcmd->cd_data, nseg, + (tcmd->cd_hflags & CDFH_DATA_IN)? PCI_DMA_TODEVICE : + PCI_DMA_FROMDEVICE); + } else +#endif + if (Cmnd->sc_data_direction != SCSI_DATA_NONE) { + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; + if (Cmnd->use_sg) { + pci_unmap_sg(pcs->pci_dev, (struct scatterlist *)Cmnd->buffer, + Cmnd->use_sg, scsi_to_pci_dma_dir(Cmnd->sc_data_direction)); + } else if (Cmnd->request_bufflen) { + DMA_ADDR_T handle = (DMA_ADDR_T) QLA_HANDLE(Cmnd); + pci_unmap_single(pcs->pci_dev, handle, Cmnd->request_bufflen, + scsi_to_pci_dma_dir(Cmnd->sc_data_direction)); + } + } +} + +#else + +static int +isp_pci_dmasetup(struct ispsoftc *isp, Scsi_Cmnd *Cmnd, ispreq_t *rq, + u_int16_t *nxi, u_int16_t optr) +{ + struct scatterlist *sg; + DMA_ADDR_T one_shot_addr; + unsigned int one_shot_length; + int segcnt, seg, ovseg, seglim; + void *h; + u_int16_t nxti; + +#ifdef LINUX_ISP_TARGET_MODE + if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO || + rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { + int s; + if (IS_SCSI(isp)) + s = tdma_mk(isp, (tmd_cmd_t *)Cmnd, (ct_entry_t *)rq, nxi, optr); + else + s = tdma_mkfc(isp, (tmd_cmd_t *)Cmnd, (ct2_entry_t *)rq, nxi, optr); + return (s); + } +#endif + + nxti = *nxi; + h = (void *) ISP_QUEUE_ENTRY(isp->isp_rquest, isp->isp_reqidx); + + if (Cmnd->request_bufflen == 0) { + rq->req_seg_count = 1; + goto mbxsync; + } + + if (IS_FC(isp)) { + if (rq->req_header.rqs_entry_type == RQSTYPE_T3RQS) + seglim = ISP_RQDSEG_T3; + else + seglim = ISP_RQDSEG_T2; + ((ispreqt2_t *)rq)->req_totalcnt = Cmnd->request_bufflen; + /* + * Linux doesn't make it easy to tell which direction + * the data is expected to go, and you really need to + * know this for FC. We'll have to assume that some + * of these commands that might be used for writes + * our outbounds and all else are inbound. + */ + switch (Cmnd->cmnd[0]) { + case FORMAT_UNIT: + case WRITE_6: + case MODE_SELECT: + case SEND_DIAGNOSTIC: + case WRITE_10: + case WRITE_BUFFER: + case WRITE_LONG: + case WRITE_SAME: + case MODE_SELECT_10: + case WRITE_12: + case WRITE_VERIFY_12: + case SEND_VOLUME_TAG: + ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_OUT; + break; + default: + ((ispreqt2_t *)rq)->req_flags |= REQFLAG_DATA_IN; + } + } else { + if (Cmnd->cmd_len > 12) + seglim = 0; + else + seglim = ISP_RQDSEG; + rq->req_flags |= REQFLAG_DATA_OUT | REQFLAG_DATA_IN; + } + + one_shot_addr = (DMA_ADDR_T) 0; + one_shot_length = 0; + if ((segcnt = Cmnd->use_sg) == 0) { + segcnt = 1; + sg = NULL; + one_shot_length = Cmnd->request_bufflen; + one_shot_addr = virt_to_bus(Cmnd->request_buffer); + } else { + sg = (struct scatterlist *) Cmnd->request_buffer; + } + if (segcnt == 0) { + isp_prt(isp, ISP_LOGWARN, "unable to dma map request"); + XS_SETERR(Cmnd, HBA_BOTCH); + return (CMD_EAGAIN); + } + + for (seg = 0, rq->req_seg_count = 0; + seg < segcnt && rq->req_seg_count < seglim; + seg++, rq->req_seg_count++) { + DMA_ADDR_T addr; + unsigned int length; + + if (sg) { + length = QLA_SG_C(sg); + addr = QLA_SG_A(sg); + sg++; + } else { + length = one_shot_length; + addr = one_shot_addr; + } + + if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { + ispreqt2_t *rq2 = (ispreqt2_t *)rq; + rq2->req_dataseg[rq2->req_seg_count].ds_count = length; + rq2->req_dataseg[rq2->req_seg_count].ds_base = addr; + } else { + rq->req_dataseg[rq->req_seg_count].ds_count = length; + rq->req_dataseg[rq->req_seg_count].ds_base = addr; + } + isp_prt(isp, ISP_LOGDEBUG1, "seg0[%d]%llx:%u from %p", seg, + (long long)addr, length, sg? sg->address : Cmnd->request_buffer); + } + + if (seg == segcnt) { + goto mbxsync; + } + + do { + int lim; + u_int16_t curip; + ispcontreq_t local, *crq = &local, *qep; + + curip = nxti; + qep = (ispcontreq_t *) ISP_QUEUE_ENTRY(isp->isp_rquest, curip); + nxti = ISP_NXT_QENTRY((curip), RQUEST_QUEUE_LEN(isp)); + if (nxti == optr) { + isp_prt(isp, ISP_LOGDEBUG0, "out of space for continuations"); + XS_SETERR(Cmnd, HBA_BOTCH); + return (CMD_EAGAIN); + } + rq->req_header.rqs_entry_count++; + MEMZERO((void *)crq, sizeof (*crq)); + crq->req_header.rqs_entry_count = 1; + if (rq->req_header.rqs_entry_type == RQSTYPE_T3RQS) { + lim = ISP_CDSEG64; + crq->req_header.rqs_entry_type = RQSTYPE_A64_CONT; + } else { + lim = ISP_CDSEG; + crq->req_header.rqs_entry_type = RQSTYPE_DATASEG; + } + + for (ovseg = 0; seg < segcnt && ovseg < lim; + rq->req_seg_count++, seg++, ovseg++, sg++) { + if (sg->length == 0) { + panic("zero length s-g element at line %d", __LINE__); + } + crq->req_dataseg[ovseg].ds_count = QLA_SG_C(sg); + crq->req_dataseg[ovseg].ds_base = QLA_SG_A(sg); + isp_prt(isp, ISP_LOGDEBUG1, "seg%d[%d]%llx:%u from %p", + rq->req_header.rqs_entry_count-1, ovseg, + (unsigned long long) QLA_SG_A(sg), QLA_SG_C(sg), sg->address); + } + MEMORYBARRIER(isp, SYNC_REQUEST, curip, QENTRY_LEN); + isp_put_cont_req(isp, crq, qep); + } while (seg < segcnt); +mbxsync: + if (rq->req_header.rqs_entry_type == RQSTYPE_T3RQS) { + isp_put_request_t3(isp, (ispreqt3_t *) rq, (ispreqt3_t *) h); + } else if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { + isp_put_request_t2(isp, (ispreqt2_t *) rq, (ispreqt2_t *) h); + } else { + isp_put_request(isp, (ispreq_t *) rq, (ispreq_t *) h); + } + *nxi = nxti; + return (CMD_QUEUED); +} +#endif + +static void +isp_pci_reset1(struct ispsoftc *isp) +{ + isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); + ENABLE_INTS(isp); + isp->mbintsok = 1; +} + +static void +isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) +{ + struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; + u_int16_t csr; + + pci_read_config_word(pcs->pci_dev, PCI_COMMAND, &csr); + printk("%s: ", isp->isp_name); + if (msg) + printk("%s\n", msg); + if (IS_SCSI(isp)) + printk(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); + else + printk(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); + printk(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), + ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); + printk("risc_hccr=%x\n", ISP_READ(isp, HCCR)); + if (IS_SCSI(isp)) { + ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); + printk(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", + ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), + ISP_READ(isp, CDMA_FIFO_STS)); + printk(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", + ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), + ISP_READ(isp, DDMA_FIFO_STS)); + printk(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", + ISP_READ(isp, SXP_INTERRUPT), + ISP_READ(isp, SXP_GROSS_ERR), + ISP_READ(isp, SXP_PINS_CTRL)); + ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); + } + printk(" mbox regs: %x %x %x %x %x\n", + ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), + ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), + ISP_READ(isp, OUTMAILBOX4)); + printk(" PCI Status Command/Status=%x\n", csr); +} + +#ifdef MODULE +MODULE_PARM(isp_pci_mapmem, "i"); +#endif +/* + * mode: c + * Local variables: + * c-indent-level: 4 + * c-brace-imaginary-offset: 0 + * c-brace-offset: -4 + * c-argdecl-indent: 4 + * c-label-offset: -4 + * c-continued-statement-offset: 4 + * c-continued-brace-offset: 0 + * End: + */ --- /dev/null 2002-08-30 16:31:37.000000000 -0700 +++ 25/drivers/scsi/isp/Makefile 2003-06-27 15:56:36.000000000 -0700 @@ -0,0 +1,37 @@ +# +# %W% +# +# Copyright (c) 2001 by Matthew Jacob +# +# This software is free software; you can redistribute it and/or +# modify it under the terms of the GNU Library General Public +# License as published by the Free Software Foundation; version 2. +# +# This software is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Library General Public License for more details. +# +# You should have received a copy of the GNU Library General Public +# License along with this software; if not, write to the Free +# Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# The author may be reached via electronic communications at +# +# mjacob@feral.com +# +# or, via United States Postal Address +# +# Matthew Jacob +# Feral Software +# PMB #825 +# 5214-F Diamond Hts. Blvd +# San Francisco, CA, 94131 +# +# +EXTRA_CFLAGS += -Idrivers/scsi/isp -Idrivers/scsi/isp/common \ + -Idrivers/scsi/isp/firmware -Idrivers/scsi + +isp-objs := isp_pci.o isp_linux.o common/isp.o common/isp_target.o + +obj-$(CONFIG_SCSI_QLOGIC_ISP_NEW) += isp.o --- linux-2.5.73/drivers/scsi/Kconfig 2003-06-26 22:07:25.000000000 -0700 +++ 25/drivers/scsi/Kconfig 2003-06-27 15:56:36.000000000 -0700 @@ -1,3 +1,27 @@ +menu "SCSI device support" + +config SCSI + tristate "SCSI device support" + ---help--- + If you want to use a SCSI hard disk, SCSI tape drive, SCSI CD-ROM or + any other SCSI device under Linux, say Y and make sure that you know + the name of your SCSI host adapter (the card inside your computer + that "speaks" the SCSI protocol, also called SCSI controller), + because you will be asked for it. + + You also need to say Y here if you have a device which speaks + the SCSI protocol. Examples of this include the parallel port + version of the IOMEGA ZIP drive, USB storage devices, Fibre + Channel, FireWire storage and the IDE-SCSI emulation driver. + + This driver is also available as a module ( = code which can be + inserted in and removed from the running kernel whenever you want). + The module will be called scsi_mod. If you want to compile it as + a module, say M here and read and + . However, do not compile this as a + module if your root file system (the one containing the directory /) + is located on a SCSI device. + comment "SCSI support type (disk, tape, CD-ROM)" depends on SCSI @@ -5,9 +29,10 @@ config BLK_DEV_SD tristate "SCSI disk support" depends on SCSI ---help--- - If you want to use a SCSI hard disk or the SCSI or parallel port - version of the IOMEGA ZIP drive under Linux, say Y and read the - SCSI-HOWTO, the Disk-HOWTO and the Multi-Disk-HOWTO, available from + If you want to use SCSI hard disks, Fibre Channel disks, + USB storage or the SCSI or parallel port version of + the IOMEGA ZIP drive, say Y and read the SCSI-HOWTO, + the Disk-HOWTO and the Multi-Disk-HOWTO, available from . This is NOT for SCSI CD-ROMs. @@ -65,10 +90,10 @@ config BLK_DEV_SR tristate "SCSI CDROM support" depends on SCSI ---help--- - If you want to use a SCSI CD-ROM under Linux, say Y and read the - SCSI-HOWTO and the CD-ROM-HOWTO at - . Also make sure to say Y - or M to "ISO 9660 CD-ROM file system support" later. + If you want to use a SCSI or FireWire CD-ROM under Linux, + say Y and read the SCSI-HOWTO and the CDROM-HOWTO at + . Also make sure to say + Y or M to "ISO 9660 CD-ROM file system support" later. This driver is also available as a module ( = code which can be inserted in and removed from the running kernel whenever you want). @@ -1253,6 +1278,16 @@ config SCSI_QLOGIC_ISP The module will be called qlogicisp. If you want to compile it as a module, say M here and read . +config SCSI_QLOGIC_ISP_NEW + tristate "Qlogic ISP FC/SCSI support - new driver" + depends on PCI && SCSI + help + New driver for QLogic Fibre Channel and SCSI cards. + Drives all 1XX0, 1X160 SCSI cards as well as all + 2XXX Fibre Channel cards. Can be safely configured + with older drivers (it just won't claim hardware + driven by the other drivers). + config SCSI_QLOGIC_FC tristate "Qlogic ISP FC SCSI support" depends on PCI && SCSI @@ -1823,3 +1858,4 @@ endmenu source "drivers/scsi/pcmcia/Kconfig" +endmenu --- linux-2.5.73/drivers/scsi/Makefile 2003-06-26 22:07:25.000000000 -0700 +++ 25/drivers/scsi/Makefile 2003-06-27 15:56:36.000000000 -0700 @@ -113,6 +113,7 @@ obj-$(CONFIG_SCSI_FCAL) += fcal.o obj-$(CONFIG_SCSI_CPQFCTS) += cpqfc.o obj-$(CONFIG_SCSI_LASI700) += lasi700.o 53c700.o obj-$(CONFIG_SCSI_NSP32) += nsp32.o +obj-$(CONFIG_SCSI_QLOGIC_ISP_NEW) += isp/ obj-$(CONFIG_ARM) += arm/ --- linux-2.5.73/drivers/scsi/NCR53C9x.c 2003-06-14 12:18:03.000000000 -0700 +++ 25/drivers/scsi/NCR53C9x.c 2003-06-27 15:56:24.000000000 -0700 @@ -893,7 +893,7 @@ static int esp_host_info(struct NCR_ESP int esp_proc_info(struct Scsi_Host *shost, char *buffer, char **start, off_t offset, int length, int inout) { - struct NCR_ESP *esp = (struct NCR_ESP *) SCpnt->device->host->hostdata; + struct NCR_ESP *esp = (struct NCR_ESP *)shost->hostdata; if(inout) return -EINVAL; /* not yet */ --- linux-2.5.73/drivers/scsi/sg.c 2003-06-26 22:07:25.000000000 -0700 +++ 25/drivers/scsi/sg.c 2003-06-27 15:56:44.000000000 -0700 @@ -82,7 +82,7 @@ static void sg_proc_cleanup(void); #define SG_ALLOW_DIO_DEF 0 #define SG_ALLOW_DIO_CODE /* compile out by commenting this define */ -#define SG_MAX_DEVS_MASK ((1U << KDEV_MINOR_BITS) - 1) +#define SG_MAX_DEVS_MASK 255 /* * Suppose you want to calculate the formula muldiv(x,m,d)=int(x * m / d) --- linux-2.5.73/drivers/scsi/sr.c 2003-06-26 22:07:25.000000000 -0700 +++ 25/drivers/scsi/sr.c 2003-06-27 16:30:32.000000000 -0700 @@ -57,7 +57,7 @@ MODULE_PARM(xa_test, "i"); /* see sr_ioctl.c */ -#define SR_DISKS (1 << KDEV_MINOR_BITS) +#define SR_DISKS 256 #define MAX_RETRIES 3 #define SR_TIMEOUT (30 * HZ) @@ -65,7 +65,7 @@ MODULE_PARM(xa_test, "i"); /* see sr_ioc (CDC_CLOSE_TRAY|CDC_OPEN_TRAY|CDC_LOCK|CDC_SELECT_SPEED| \ CDC_SELECT_DISC|CDC_MULTI_SESSION|CDC_MCN|CDC_MEDIA_CHANGED| \ CDC_PLAY_AUDIO|CDC_RESET|CDC_IOCTLS|CDC_DRIVE_STATUS| \ - CDC_CD_R|CDC_CD_RW|CDC_DVD|CDC_DVD_R|CDC_GENERIC_PACKET) + CDC_CD_R|CDC_CD_RW|CDC_DVD|CDC_DVD_R|CDC_DVD_RAM|CDC_GENERIC_PACKET) static int sr_probe(struct device *); static int sr_remove(struct device *); --- linux-2.5.73/drivers/scsi/sym53c8xx_2/sym_glue.c 2003-06-26 22:07:25.000000000 -0700 +++ 25/drivers/scsi/sym53c8xx_2/sym_glue.c 2003-06-27 15:56:58.000000000 -0700 @@ -295,12 +295,8 @@ struct host_data { #ifndef SYM_LINUX_DYNAMIC_DMA_MAPPING typedef u_long bus_addr_t; #else -#if SYM_CONF_DMA_ADDRESSING_MODE > 0 -typedef dma64_addr_t bus_addr_t; -#else typedef dma_addr_t bus_addr_t; #endif -#endif /* * Used by the eh thread to wait for command completion. @@ -2753,14 +2749,6 @@ if (sym53c8xx) /* This one is guaranteed by AC to do nothing :-) */ if (pci_enable_device(pcidev)) continue; - /* Some HW as the HP LH4 may report twice PCI devices */ - for (i = 0; i < count ; i++) { - if (devtbl[i].s.bus == PciBusNumber(pcidev) && - devtbl[i].s.device_fn == PciDeviceFn(pcidev)) - break; - } - if (i != count) /* Ignore this device if we already have it */ - continue; devp = &devtbl[count]; devp->host_id = SYM_SETUP_HOST_ID; devp->attach_done = 0; --- linux-2.5.73/drivers/scsi/sym53c8xx_2/sym_hipd.c 2003-06-26 22:07:25.000000000 -0700 +++ 25/drivers/scsi/sym53c8xx_2/sym_hipd.c 2003-06-27 15:56:31.000000000 -0700 @@ -800,7 +800,8 @@ static int sym_prepare_setting(hcb_p np, * Btw, 'period' is in tenths of nanoseconds. */ period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz; - if (period <= 250) np->minsync = 10; + if (period == 250) np->minsync = 9; + else if (period <= 250) np->minsync = 10; else if (period <= 303) np->minsync = 11; else if (period <= 500) np->minsync = 12; else np->minsync = (period + 40 - 1) / 40; --- linux-2.5.73/drivers/serial/8250.c 2003-06-26 22:07:25.000000000 -0700 +++ 25/drivers/serial/8250.c 2003-06-27 15:56:27.000000000 -0700 @@ -122,13 +122,13 @@ struct uart_8250_port { struct uart_port port; struct timer_list timer; /* "no irq" timer */ struct list_head list; /* ports on this IRQ */ + unsigned short rev; unsigned char acr; unsigned char ier; - unsigned char rev; unsigned char lcr; unsigned char mcr_mask; /* mask of user bits */ unsigned char mcr_force; /* mask of forced bits */ - unsigned int lsr_break_flag; + unsigned char lsr_break_flag; /* * We provide a per-port pm hook. @@ -823,7 +823,7 @@ receive_chars(struct uart_8250_port *up, if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) { tty->flip.work.func((void *)tty); if (tty->flip.count >= TTY_FLIPBUF_SIZE) - return; // if TTY_DONT_FLIP is set + return; /* if TTY_DONT_FLIP is set */ } ch = serial_inp(up, UART_RX); *tty->flip.char_buf_ptr = ch; @@ -1183,13 +1183,20 @@ static void serial8250_break_ctl(struct serial_out(up, UART_LCR, up->lcr); spin_unlock_irqrestore(&up->port.lock, flags); } +#ifdef CONFIG_KGDB +static int kgdb_irq = -1; +#endif static int serial8250_startup(struct uart_port *port) { struct uart_8250_port *up = (struct uart_8250_port *)port; unsigned long flags; int retval; - +#ifdef CONFIG_KGDB + if ( up->port.irq == kgdb_irq){ + return -EBUSY; + } +#endif if (up->port.type == PORT_16C950) { /* Wake up and initialize UART */ up->acr = 0; @@ -1853,6 +1860,11 @@ static void __init serial8250_register_p for (i = 0; i < UART_NR; i++) { struct uart_8250_port *up = &serial8250_ports[i]; +#ifdef CONFIG_KGDB + if(up->port.irq == kgdb_irq){ + up->port.iobase = up->port.mapbase = 0; + } +#endif up->port.line = i; up->port.ops = &serial8250_pops; init_timer(&up->timer); @@ -2116,7 +2128,31 @@ void serial8250_resume_port(int line, u3 { uart_resume_port(&serial8250_reg, &serial8250_ports[line].port, level); } - +#ifdef CONFIG_KGDB +/* + * Find all the ports using the given irq and shut them down. + * Result should be that the irq will be released. + */ +void shutdown_for_kgdb(struct async_struct * info) +{ + int irq = info->state->irq; + struct uart_8250_port *up; + int ttyS; + + kgdb_irq = irq; /* save for later init */ + for (ttyS = 0; ttyS < UART_NR; ttyS++){ + up = &serial8250_ports[ttyS]; + if( up->port.irq == irq && (irq_lists + irq)->head){ +#ifdef CONFIG_DEBUG_SPINLOCK /* ugly business... */ + if(up->port.lock.magic != SPINLOCK_MAGIC){ + spin_lock_init(&up->port.lock); + } +#endif + serial8250_shutdown(&up->port); + } + } +} +#endif static int __init serial8250_init(void) { int ret, i; --- linux-2.5.73/drivers/serial/8250_cs.c 2003-06-14 12:18:21.000000000 -0700 +++ 25/drivers/serial/8250_cs.c 2003-06-27 15:56:24.000000000 -0700 @@ -2,7 +2,7 @@ A driver for PCMCIA serial devices - serial_cs.c 1.123 2000/08/24 18:46:38 + serial_cs.c 1.134 2002/05/04 05:48:53 The contents of this file are subject to the Mozilla Public License Version 1.1 (the "License"); you may not use this file @@ -43,7 +43,6 @@ #include #include #include -#include #include #include @@ -59,7 +58,7 @@ static int pc_debug = PCMCIA_DEBUG; MODULE_PARM(pc_debug, "i"); #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args) -static char *version = "serial_cs.c 1.123 2000/08/24 18:46:38 (David Hinds)"; +static char *version = "serial_cs.c 1.134 2002/05/04 05:48:53 (David Hinds)"; #else #define DEBUG(n, args...) #endif @@ -74,10 +73,13 @@ static int irq_list[4] = { -1 }; /* Enable the speaker? */ static int do_sound = 1; +/* Skip strict UART tests? */ +static int buggy_uart; MODULE_PARM(irq_mask, "i"); MODULE_PARM(irq_list, "1-4i"); MODULE_PARM(do_sound, "i"); +MODULE_PARM(buggy_uart, "i"); /*====================================================================*/ @@ -100,7 +102,7 @@ static struct multi_id multi_id[] = { }; #define MULTI_COUNT (sizeof(multi_id)/sizeof(struct multi_id)) -typedef struct serial_info { +struct serial_info { dev_link_t link; int ndev; int multi; @@ -108,8 +110,7 @@ typedef struct serial_info { int manfid; dev_node_t node[4]; int line[4]; - struct work_struct remove; -} serial_info_t; +}; static void serial_config(dev_link_t * link); static int serial_event(event_t event, int priority, @@ -124,20 +125,19 @@ static dev_link_t *dev_list = NULL; /*====================================================================== - After a card is removed, do_serial_release() will unregister + After a card is removed, serial_remove() will unregister the serial device(s), and release the PCMCIA configuration. ======================================================================*/ -/* - * This always runs in process context. - */ -static void do_serial_release(void *arg) +static void serial_remove(dev_link_t *link) { - struct serial_info *info = arg; - int i; + struct serial_info *info = link->priv; + int i, ret; - DEBUG(0, "serial_release(0x%p)\n", &info->link); + link->state &= ~DEV_PRESENT; + + DEBUG(0, "serial_release(0x%p)\n", link); /* * Recheck to see if the device is still configured. @@ -158,25 +158,6 @@ static void do_serial_release(void *arg) } } -/* - * This may be called from IRQ context. - */ -static void serial_remove(dev_link_t *link) -{ - struct serial_info *info = link->priv; - - link->state &= ~DEV_PRESENT; - - /* - * FIXME: Since the card has probably been removed, - * we should call into the serial layer and hang up - * the ports on the card immediately. - */ - - if (link->state & DEV_CONFIG) - schedule_work(&info->remove); -} - /*====================================================================== serial_attach() creates an "instance" of the driver, allocating @@ -187,7 +168,7 @@ static void serial_remove(dev_link_t *li static dev_link_t *serial_attach(void) { - serial_info_t *info; + struct serial_info *info; client_reg_t client_reg; dev_link_t *link; int i, ret; @@ -202,8 +183,6 @@ static dev_link_t *serial_attach(void) link = &info->link; link->priv = info; - INIT_WORK(&info->remove, do_serial_release, info); - link->io.Attributes1 = IO_DATA_PATH_WIDTH_8; link->io.NumPorts1 = 8; link->irq.Attributes = IRQ_TYPE_EXCLUSIVE; @@ -214,7 +193,6 @@ static dev_link_t *serial_attach(void) for (i = 0; i < 4; i++) link->irq.IRQInfo2 |= 1 << irq_list[i]; link->conf.Attributes = CONF_ENABLE_IRQ; - link->conf.Vcc = 50; if (do_sound) { link->conf.Attributes |= CONF_ENABLE_SPKR; link->conf.Status = CCSR_AUDIO_ENA; @@ -254,7 +232,7 @@ static dev_link_t *serial_attach(void) static void serial_detach(dev_link_t * link) { - serial_info_t *info = link->priv; + struct serial_info *info = link->priv; dev_link_t **linkp; int ret; @@ -275,7 +253,7 @@ static void serial_detach(dev_link_t * l /* * Ensure that the ports have been released. */ - do_serial_release(info); + serial_remove(link); if (link->handle) { ret = CardServices(DeregisterClient, link->handle); @@ -290,7 +268,7 @@ static void serial_detach(dev_link_t * l /*====================================================================*/ -static int setup_serial(serial_info_t * info, ioaddr_t port, int irq) +static int setup_serial(struct serial_info * info, ioaddr_t port, int irq) { struct serial_struct serial; int line; @@ -299,11 +277,13 @@ static int setup_serial(serial_info_t * serial.port = port; serial.irq = irq; serial.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ; + if (buggy_uart) + serial.flags |= UPF_BUGGY_UART; line = register_serial(&serial); if (line < 0) { printk(KERN_NOTICE "serial_cs: register_serial() at 0x%04lx," " irq %d failed\n", (u_long) serial.port, serial.irq); - return -1; + return -EINVAL; } info->line[info->ndev] = line; @@ -341,7 +321,7 @@ static int simple_config(dev_link_t * li { static ioaddr_t base[5] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, 0x0 }; client_handle_t handle = link->handle; - serial_info_t *info = link->priv; + struct serial_info *info = link->priv; tuple_t tuple; u_char buf[256]; cisparse_t parse; @@ -445,13 +425,21 @@ static int simple_config(dev_link_t * li static int multi_config(dev_link_t * link) { client_handle_t handle = link->handle; - serial_info_t *info = link->priv; + struct serial_info *info = link->priv; tuple_t tuple; u_char buf[256]; cisparse_t parse; cistpl_cftable_entry_t *cf = &parse.cftable_entry; + config_info_t config; int i, base2 = 0; + i = CardServices(GetConfigurationInfo, handle, &config); + if (i != CS_SUCCESS) { + cs_error(handle, GetConfigurationInfo, i); + return -1; + } + link->conf.Vcc = config.Vcc; + tuple.TupleData = (cisdata_t *) buf; tuple.TupleOffset = 0; tuple.TupleDataMax = 255; @@ -524,6 +512,19 @@ static int multi_config(dev_link_t * lin return -1; } + /* The Oxford Semiconductor OXCF950 cards are in fact single-port: + 8 registers are for the UART, the others are extra registers */ + if (info->manfid == MANFID_OXSEMI) { + if (cf->index == 1 || cf->index == 3) { + setup_serial(info, base2, link->irq.AssignedIRQ); + outb(12, link->io.BasePort1 + 1); + } else { + setup_serial(info, link->io.BasePort1, link->irq.AssignedIRQ); + outb(12, base2 + 1); + } + return 0; + } + setup_serial(info, link->io.BasePort1, link->irq.AssignedIRQ); /* The Nokia cards are not really multiport cards */ if (info->manfid == MANFID_NOKIA) @@ -548,7 +549,7 @@ while ((last_ret=CardServices(last_fn=(f void serial_config(dev_link_t * link) { client_handle_t handle = link->handle; - serial_info_t *info = link->priv; + struct serial_info *info = link->priv; tuple_t tuple; u_short buf[128]; cisparse_t parse; @@ -631,7 +632,8 @@ void serial_config(dev_link_t * link) cs_failed: cs_error(link->handle, last_fn, last_ret); failed: - do_serial_release(info); + serial_remove(link); + link->state &= ~DEV_CONFIG_PENDING; } /*====================================================================== @@ -647,7 +649,7 @@ static int serial_event(event_t event, int priority, event_callback_args_t * args) { dev_link_t *link = args->client_data; - serial_info_t *info = link->priv; + struct serial_info *info = link->priv; DEBUG(1, "serial_event(0x%06x)\n", event); --- linux-2.5.73/drivers/serial/8250_pci.c 2003-06-14 12:18:29.000000000 -0700 +++ 25/drivers/serial/8250_pci.c 2003-06-27 15:56:24.000000000 -0700 @@ -322,7 +322,7 @@ static void __devexit pci_plx9050_exit(s * hope) because it doesn't touch EEPROM settings to prevent conflicts * with other OSes (like M$ DOS). * - * SIIG support added by Andrey Panin , 10/1999 + * SIIG support added by Andrey Panin , 10/1999 * * There is two family of SIIG serial cards with different PCI * interface chip and different configuration methods: --- linux-2.5.73/drivers/serial/Kconfig 2003-06-22 12:04:44.000000000 -0700 +++ 25/drivers/serial/Kconfig 2003-06-27 15:56:24.000000000 -0700 @@ -80,14 +80,14 @@ config SERIAL_8250_CS config SERIAL_8250_ACPI bool "8250/16550 device discovery via ACPI namespace" default y if IA64 - depends on ACPI_BUS + depends on ACPI_BUS && SERIAL_8250 ---help--- If you wish to enable serial port discovery via the ACPI namespace, say Y here. If unsure, say N. config SERIAL_8250_HCDP bool "8250/16550 device discovery support via EFI HCDP table" - depends on IA64 + depends on IA64 && SERIAL_8250 ---help--- If you wish to make the serial console port described by the EFI HCDP table available for use as serial console or general @@ -326,6 +326,14 @@ config SERIAL_SUNZILOG This driver supports the Zilog8530 serial ports found on many Sparc systems. Say Y or M if you want to be able to these serial ports. +config SERIAL_SUNZILOG_CONSOLE + bool "Console on Sun Zilog8530 serial port" + depends on SERIAL_SUNZILOG=y + help + If you would like to be able to use the Zilog8530 serial port + on your Sparc system as the console, you can do so by answering + Y to this option. + config SERIAL_SUNSU tristate "Sun SU serial support" depends on (SPARC32 || SPARC64) && PCI @@ -334,6 +342,14 @@ config SERIAL_SUNSU mouse on (PCI) UltraSPARC systems. Say Y or M if you want to be able to these serial ports. +config SERIAL_SUNSU_CONSOLE + bool "Console on Sun SU serial port" + depends on SERIAL_SUNSU=y + help + If you would like to be able to use the SU serial port + on your Sparc system as the console, you can do so by answering + Y to this option. + config SERIAL_MUX tristate "Serial MUX support" depends on PARISC @@ -380,6 +396,14 @@ config SERIAL_SUNSAB (PCI) UltraSPARC systems. Say Y or M if you want to be able to these serial ports. +config SERIAL_SUNSAB_CONSOLE + bool "Console on Sun Siemens SAB82532 serial port" + depends on SERIAL_SUNSAB=y + help + If you would like to be able to use the SAB82532 serial port + on your Sparc system as the console, you can do so by answering + Y to this option. + config V850E_NB85E_UART bool "NEC V850E on-chip UART support" depends on V850E_NB85E || V850E2_ANNA || V850E_AS85EP1 @@ -407,7 +431,7 @@ config SERIAL_CORE config SERIAL_CORE_CONSOLE bool - depends on SERIAL_AMBA_CONSOLE || SERIAL_CLPS711X_CONSOLE || SERIAL_21285_CONSOLE || SERIAL_SA1100_CONSOLE || SERIAL_ANAKIN_CONSOLE || SERIAL_UART00_CONSOLE || SERIAL_8250_CONSOLE || SERIAL_MUX_CONSOLE || SERIAL_SUNCORE || V850E_NB85E_UART_CONSOLE || SERIAL98_CONSOLE + depends on SERIAL_AMBA_CONSOLE || SERIAL_CLPS711X_CONSOLE || SERIAL_21285_CONSOLE || SERIAL_SA1100_CONSOLE || SERIAL_ANAKIN_CONSOLE || SERIAL_UART00_CONSOLE || SERIAL_8250_CONSOLE || SERIAL_MUX_CONSOLE || SERIAL_SUNZILOG_CONSOLE || SERIAL_SUNSU_CONSOLE || SERIAL_SUNSAB_CONSOLE || V850E_NB85E_UART_CONSOLE || SERIAL98_CONSOLE default y config SERIAL_68328 --- linux-2.5.73/drivers/serial/sunsab.c 2003-06-14 12:18:07.000000000 -0700 +++ 25/drivers/serial/sunsab.c 2003-06-27 15:56:24.000000000 -0700 @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -38,6 +39,10 @@ #include #include +#if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + #include #include "suncore.h" @@ -838,6 +843,8 @@ static struct uart_driver sunsab_reg = { static struct uart_sunsab_port *sunsab_ports; static int num_channels; +#ifdef CONFIG_SERIAL_SUNSAB_CONSOLE + static __inline__ void sunsab_console_putchar(struct uart_sunsab_port *up, char c) { unsigned long flags; @@ -929,6 +936,7 @@ static struct console sunsab_console = { .index = -1, .data = &sunsab_reg, }; +#define SUNSAB_CONSOLE (&sunsab_console) static void __init sunsab_console_init(void) { @@ -949,6 +957,10 @@ static void __init sunsab_console_init(v sunsab_console.index = i; register_console(&sunsab_console); } +#else +#define SUNSAB_CONSOLE (NULL) +#define sunsab_console_init() do { } while (0) +#endif static void __init for_each_sab_edev(void (*callback)(struct linux_ebus_device *, void *), void *arg) { @@ -1091,7 +1103,7 @@ static int __init sunsab_init(void) sunsab_reg.minor = sunserial_current_minor; sunsab_reg.nr = num_channels; - sunsab_reg.cons = &sunsab_console; + sunsab_reg.cons = SUNSAB_CONSOLE; ret = uart_register_driver(&sunsab_reg); if (ret < 0) { --- linux-2.5.73/drivers/serial/sunsu.c 2003-06-14 12:18:00.000000000 -0700 +++ 25/drivers/serial/sunsu.c 2003-06-27 15:56:24.000000000 -0700 @@ -46,8 +46,7 @@ #include #endif -/* #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) */ -#if defined(CONFIG_MAGIC_SYSRQ) +#if defined(CONFIG_SERIAL_SUNSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) #define SUPPORT_SYSRQ #endif @@ -1347,6 +1346,8 @@ static int __init sunsu_kbd_ms_init(void * ------------------------------------------------------------ */ +#ifdef CONFIG_SERIAL_SUNSU_CONSOLE + #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) /* @@ -1465,6 +1466,7 @@ static struct console sunsu_cons = { .index = -1, .data = &sunsu_reg, }; +#define SUNSU_CONSOLE (&sunsu_cons) /* * Register console. @@ -1492,6 +1494,10 @@ static int __init sunsu_serial_console_i register_console(&sunsu_cons); return 0; } +#else +#define SUNSU_CONSOLE (NULL) +#define sunsu_serial_console_init() do { } while (0) +#endif static int __init sunsu_serial_init(void) { @@ -1522,7 +1528,7 @@ static int __init sunsu_serial_init(void sunserial_current_minor += instance; sunsu_reg.nr = instance; - sunsu_reg.cons = &sunsu_cons; + sunsu_reg.cons = SUNSU_CONSOLE; ret = uart_register_driver(&sunsu_reg); if (ret < 0) --- linux-2.5.73/drivers/serial/sunzilog.c 2003-06-14 12:18:50.000000000 -0700 +++ 25/drivers/serial/sunzilog.c 2003-06-27 15:56:24.000000000 -0700 @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #ifdef CONFIG_SERIO @@ -42,6 +43,10 @@ #endif #include +#if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + #include #include "suncore.h" @@ -1331,6 +1336,7 @@ static void sunzilog_serio_close(struct #endif /* CONFIG_SERIO */ +#ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE static void sunzilog_console_write(struct console *con, const char *s, unsigned int count) { @@ -1400,6 +1406,7 @@ static struct console sunzilog_console = .index = -1, .data = &sunzilog_reg, }; +#define SUNZILOG_CONSOLE (&sunzilog_console) static int __init sunzilog_console_init(void) { @@ -1422,6 +1429,10 @@ static int __init sunzilog_console_init( register_console(&sunzilog_console); return 0; } +#else +#define SUNZILOG_CONSOLE (NULL) +#define sunzilog_console_init() do { } while (0) +#endif /* * We scan the PROM tree recursively. This is the most reliable way @@ -1639,7 +1650,7 @@ static int __init sunzilog_ports_init(vo * in the system. */ sunzilog_reg.nr = NUM_CHANNELS; - sunzilog_reg.cons = &sunzilog_console; + sunzilog_reg.cons = SUNZILOG_CONSOLE; sunzilog_reg.minor = sunserial_current_minor; sunserial_current_minor += NUM_CHANNELS; --- linux-2.5.73/drivers/sgi/char/ds1286.c 2003-06-26 22:07:25.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,521 +0,0 @@ -/* - * DS1286 Real Time Clock interface for Linux - * - * Copyright (C) 1998, 1999, 2000 Ralf Baechle - * - * Based on code written by Paul Gortmaker. - * - * This driver allows use of the real time clock (built into nearly all - * computers) from user space. It exports the /dev/rtc interface supporting - * various ioctl() and also the /proc/rtc pseudo-file for status - * information. - * - * The ioctls can be used to set the interrupt behaviour and generation rate - * from the RTC via IRQ 8. Then the /dev/rtc interface can be used to make - * use of these timer interrupts, be they interval or alarm based. - * - * The /dev/rtc interface will block on reads until an interrupt has been - * received. If a RTC interrupt has already happened, it will output an - * unsigned long and then block. The output value contains the interrupt - * status in the low byte and the number of interrupts since the last read - * in the remaining high bytes. The /dev/rtc interface can also be used with - * the select(2) call. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#define DS1286_VERSION "1.0" - -/* - * We sponge a minor off of the misc major. No need slurping - * up another valuable major dev number for this. If you add - * an ioctl, make sure you don't conflict with SPARC's RTC - * ioctls. - */ - -static DECLARE_WAIT_QUEUE_HEAD(ds1286_wait); - -static ssize_t ds1286_read(struct file *file, char *buf, - size_t count, loff_t *ppos); - -static int ds1286_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg); - -static unsigned int ds1286_poll(struct file *file, poll_table *wait); - -void get_rtc_time (struct rtc_time *rtc_tm); -void get_rtc_alm_time (struct rtc_time *alm_tm); - -void set_rtc_irq_bit(unsigned char bit); -void clear_rtc_irq_bit(unsigned char bit); - -static inline unsigned char ds1286_is_updating(void); - -static spinlock_t ds1286_lock = SPIN_LOCK_UNLOCKED; - -/* - * Bits in rtc_status. (7 bits of room for future expansion) - */ - -#define RTC_IS_OPEN 0x01 /* means /dev/rtc is in use */ -#define RTC_TIMER_ON 0x02 /* missed irq timer active */ - -unsigned char ds1286_status; /* bitmapped status byte. */ -unsigned long ds1286_freq; /* Current periodic IRQ rate */ - -unsigned char days_in_mo[] = -{0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; - -/* - * Now all the various file operations that we export. - */ - -static ssize_t ds1286_read(struct file *file, char *buf, - size_t count, loff_t *ppos) -{ - return -EIO; -} - -static int ds1286_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) -{ - - struct rtc_time wtime; - - switch (cmd) { - case RTC_AIE_OFF: /* Mask alarm int. enab. bit */ - { - unsigned int flags; - unsigned char val; - - if (!capable(CAP_SYS_TIME)) - return -EACCES; - - spin_lock_irqsave(&ds1286_lock, flags); - val = CMOS_READ(RTC_CMD); - val |= RTC_TDM; - CMOS_WRITE(val, RTC_CMD); - spin_unlock_irqrestore(&ds1286_lock, flags); - - return 0; - } - case RTC_AIE_ON: /* Allow alarm interrupts. */ - { - unsigned int flags; - unsigned char val; - - if (!capable(CAP_SYS_TIME)) - return -EACCES; - - spin_lock_irqsave(&ds1286_lock, flags); - val = CMOS_READ(RTC_CMD); - val &= ~RTC_TDM; - CMOS_WRITE(val, RTC_CMD); - spin_unlock_irqrestore(&ds1286_lock, flags); - - return 0; - } - case RTC_WIE_OFF: /* Mask watchdog int. enab. bit */ - { - unsigned int flags; - unsigned char val; - - if (!capable(CAP_SYS_TIME)) - return -EACCES; - - spin_lock_irqsave(&ds1286_lock, flags); - val = CMOS_READ(RTC_CMD); - val |= RTC_WAM; - CMOS_WRITE(val, RTC_CMD); - spin_unlock_irqrestore(&ds1286_lock, flags); - - return 0; - } - case RTC_WIE_ON: /* Allow watchdog interrupts. */ - { - unsigned int flags; - unsigned char val; - - if (!capable(CAP_SYS_TIME)) - return -EACCES; - - spin_lock_irqsave(&ds1286_lock, flags); - val = CMOS_READ(RTC_CMD); - val &= ~RTC_WAM; - CMOS_WRITE(val, RTC_CMD); - spin_unlock_irqrestore(&ds1286_lock, flags); - - return 0; - } - case RTC_ALM_READ: /* Read the present alarm time */ - { - /* - * This returns a struct rtc_time. Reading >= 0xc0 - * means "don't care" or "match all". Only the tm_hour, - * tm_min, and tm_sec values are filled in. - */ - - get_rtc_alm_time(&wtime); - break; - } - case RTC_ALM_SET: /* Store a time into the alarm */ - { - /* - * This expects a struct rtc_time. Writing 0xff means - * "don't care" or "match all". Only the tm_hour, - * tm_min and tm_sec are used. - */ - unsigned char hrs, min, sec; - struct rtc_time alm_tm; - - if (!capable(CAP_SYS_TIME)) - return -EACCES; - - if (copy_from_user(&alm_tm, (struct rtc_time*)arg, - sizeof(struct rtc_time))) - return -EFAULT; - - hrs = alm_tm.tm_hour; - min = alm_tm.tm_min; - - if (hrs >= 24) - hrs = 0xff; - - if (min >= 60) - min = 0xff; - - BIN_TO_BCD(sec); - BIN_TO_BCD(min); - BIN_TO_BCD(hrs); - - spin_lock(&ds1286_lock); - CMOS_WRITE(hrs, RTC_HOURS_ALARM); - CMOS_WRITE(min, RTC_MINUTES_ALARM); - spin_unlock(&ds1286_lock); - - return 0; - } - case RTC_RD_TIME: /* Read the time/date from RTC */ - { - get_rtc_time(&wtime); - break; - } - case RTC_SET_TIME: /* Set the RTC */ - { - struct rtc_time rtc_tm; - unsigned char mon, day, hrs, min, sec, leap_yr; - unsigned char save_control; - unsigned int yrs, flags; - - if (!capable(CAP_SYS_TIME)) - return -EACCES; - - if (copy_from_user(&rtc_tm, (struct rtc_time*)arg, - sizeof(struct rtc_time))) - return -EFAULT; - - yrs = rtc_tm.tm_year + 1900; - mon = rtc_tm.tm_mon + 1; /* tm_mon starts at zero */ - day = rtc_tm.tm_mday; - hrs = rtc_tm.tm_hour; - min = rtc_tm.tm_min; - sec = rtc_tm.tm_sec; - - if (yrs < 1970) - return -EINVAL; - - leap_yr = ((!(yrs % 4) && (yrs % 100)) || !(yrs % 400)); - - if ((mon > 12) || (day == 0)) - return -EINVAL; - - if (day > (days_in_mo[mon] + ((mon == 2) && leap_yr))) - return -EINVAL; - - if ((hrs >= 24) || (min >= 60) || (sec >= 60)) - return -EINVAL; - - if ((yrs -= 1940) > 255) /* They are unsigned */ - return -EINVAL; - - if (yrs >= 100) - yrs -= 100; - - BIN_TO_BCD(sec); - BIN_TO_BCD(min); - BIN_TO_BCD(hrs); - BIN_TO_BCD(day); - BIN_TO_BCD(mon); - BIN_TO_BCD(yrs); - - spin_lock_irqsave(&ds1286_lock, flags); - save_control = CMOS_READ(RTC_CMD); - CMOS_WRITE((save_control|RTC_TE), RTC_CMD); - - CMOS_WRITE(yrs, RTC_YEAR); - CMOS_WRITE(mon, RTC_MONTH); - CMOS_WRITE(day, RTC_DATE); - CMOS_WRITE(hrs, RTC_HOURS); - CMOS_WRITE(min, RTC_MINUTES); - CMOS_WRITE(sec, RTC_SECONDS); - CMOS_WRITE(0, RTC_HUNDREDTH_SECOND); - - CMOS_WRITE(save_control, RTC_CMD); - spin_unlock_irqrestore(&ds1286_lock, flags); - - return 0; - } - default: - return -EINVAL; - } - return copy_to_user((void *)arg, &wtime, sizeof wtime) ? -EFAULT : 0; -} - -/* - * We enforce only one user at a time here with the open/close. - * Also clear the previous interrupt data on an open, and clean - * up things on a close. - */ - -static int ds1286_open(struct inode *inode, struct file *file) -{ - spin_lock_irq(&ds1286_lock); - - if (ds1286_status & RTC_IS_OPEN) - goto out_busy; - - ds1286_status |= RTC_IS_OPEN; - - spin_lock_irq(&ds1286_lock); - return 0; - -out_busy: - spin_lock_irq(&ds1286_lock); - return -EBUSY; -} - -static int ds1286_release(struct inode *inode, struct file *file) -{ - ds1286_status &= ~RTC_IS_OPEN; - - return 0; -} - -static unsigned int ds1286_poll(struct file *file, poll_table *wait) -{ - poll_wait(file, &ds1286_wait, wait); - - return 0; -} - -/* - * The various file operations we support. - */ - -static struct file_operations ds1286_fops = { - .llseek = no_llseek, - .read = ds1286_read, - .poll = ds1286_poll, - .ioctl = ds1286_ioctl, - .open = ds1286_open, - .release = ds1286_release, -}; - -static struct miscdevice ds1286_dev= -{ - RTC_MINOR, - "rtc", - &ds1286_fops -}; - -int __init ds1286_init(void) -{ - printk(KERN_INFO "DS1286 Real Time Clock Driver v%s\n", DS1286_VERSION); - return misc_register(&ds1286_dev); -} - -static char *days[] = { - "***", "Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat" -}; - -/* - * Info exported via "/proc/rtc". - */ -int get_ds1286_status(char *buf) -{ - char *p, *s; - struct rtc_time tm; - unsigned char hundredth, month, cmd, amode; - - p = buf; - - get_rtc_time(&tm); - hundredth = CMOS_READ(RTC_HUNDREDTH_SECOND); - BCD_TO_BIN(hundredth); - - p += sprintf(p, - "rtc_time\t: %02d:%02d:%02d.%02d\n" - "rtc_date\t: %04d-%02d-%02d\n", - tm.tm_hour, tm.tm_min, tm.tm_sec, hundredth, - tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday); - - /* - * We implicitly assume 24hr mode here. Alarm values >= 0xc0 will - * match any value for that particular field. Values that are - * greater than a valid time, but less than 0xc0 shouldn't appear. - */ - get_rtc_alm_time(&tm); - p += sprintf(p, "alarm\t\t: %s ", days[tm.tm_wday]); - if (tm.tm_hour <= 24) - p += sprintf(p, "%02d:", tm.tm_hour); - else - p += sprintf(p, "**:"); - - if (tm.tm_min <= 59) - p += sprintf(p, "%02d\n", tm.tm_min); - else - p += sprintf(p, "**\n"); - - month = CMOS_READ(RTC_MONTH); - p += sprintf(p, - "oscillator\t: %s\n" - "square_wave\t: %s\n", - (month & RTC_EOSC) ? "disabled" : "enabled", - (month & RTC_ESQW) ? "disabled" : "enabled"); - - amode = ((CMOS_READ(RTC_MINUTES_ALARM) & 0x80) >> 5) | - ((CMOS_READ(RTC_HOURS_ALARM) & 0x80) >> 6) | - ((CMOS_READ(RTC_DAY_ALARM) & 0x80) >> 7); - if (amode == 7) s = "each minute"; - else if (amode == 3) s = "minutes match"; - else if (amode == 1) s = "hours and minutes match"; - else if (amode == 0) s = "days, hours and minutes match"; - else s = "invalid"; - p += sprintf(p, "alarm_mode\t: %s\n", s); - - cmd = CMOS_READ(RTC_CMD); - p += sprintf(p, - "alarm_enable\t: %s\n" - "wdog_alarm\t: %s\n" - "alarm_mask\t: %s\n" - "wdog_alarm_mask\t: %s\n" - "interrupt_mode\t: %s\n" - "INTB_mode\t: %s_active\n" - "interrupt_pins\t: %s\n", - (cmd & RTC_TDF) ? "yes" : "no", - (cmd & RTC_WAF) ? "yes" : "no", - (cmd & RTC_TDM) ? "disabled" : "enabled", - (cmd & RTC_WAM) ? "disabled" : "enabled", - (cmd & RTC_PU_LVL) ? "pulse" : "level", - (cmd & RTC_IBH_LO) ? "low" : "high", - (cmd & RTC_IPSW) ? "unswapped" : "swapped"); - - return p - buf; -} - -/* - * Returns true if a clock update is in progress - */ -static inline unsigned char ds1286_is_updating(void) -{ - return CMOS_READ(RTC_CMD) & RTC_TE; -} - -void get_rtc_time(struct rtc_time *rtc_tm) -{ - unsigned long uip_watchdog = jiffies; - unsigned char save_control; - unsigned int flags; - - /* - * read RTC once any update in progress is done. The update - * can take just over 2ms. We wait 10 to 20ms. There is no need to - * to poll-wait (up to 1s - eeccch) for the falling edge of RTC_UIP. - * If you need to know *exactly* when a second has started, enable - * periodic update complete interrupts, (via ioctl) and then - * immediately read /dev/rtc which will block until you get the IRQ. - * Once the read clears, read the RTC time (again via ioctl). Easy. - */ - - if (ds1286_is_updating() != 0) - while (jiffies - uip_watchdog < 2*HZ/100) - barrier(); - - /* - * Only the values that we read from the RTC are set. We leave - * tm_wday, tm_yday and tm_isdst untouched. Even though the - * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated - * by the RTC when initially set to a non-zero value. - */ - spin_lock_irqsave(&ds1286_lock, flags); - save_control = CMOS_READ(RTC_CMD); - CMOS_WRITE((save_control|RTC_TE), RTC_CMD); - - rtc_tm->tm_sec = CMOS_READ(RTC_SECONDS); - rtc_tm->tm_min = CMOS_READ(RTC_MINUTES); - rtc_tm->tm_hour = CMOS_READ(RTC_HOURS) & 0x1f; - rtc_tm->tm_mday = CMOS_READ(RTC_DATE); - rtc_tm->tm_mon = CMOS_READ(RTC_MONTH) & 0x1f; - rtc_tm->tm_year = CMOS_READ(RTC_YEAR); - - CMOS_WRITE(save_control, RTC_CMD); - spin_unlock_irqrestore(&ds1286_lock, flags); - - BCD_TO_BIN(rtc_tm->tm_sec); - BCD_TO_BIN(rtc_tm->tm_min); - BCD_TO_BIN(rtc_tm->tm_hour); - BCD_TO_BIN(rtc_tm->tm_mday); - BCD_TO_BIN(rtc_tm->tm_mon); - BCD_TO_BIN(rtc_tm->tm_year); - - /* - * Account for differences between how the RTC uses the values - * and how they are defined in a struct rtc_time; - */ - if (rtc_tm->tm_year < 45) - rtc_tm->tm_year += 30; - if ((rtc_tm->tm_year += 40) < 70) - rtc_tm->tm_year += 100; - - rtc_tm->tm_mon--; -} - -void get_rtc_alm_time(struct rtc_time *alm_tm) -{ - unsigned char cmd; - unsigned int flags; - - /* - * Only the values that we read from the RTC are set. That - * means only tm_wday, tm_hour, tm_min. - */ - spin_lock_irqsave(&ds1286_lock, flags); - alm_tm->tm_min = CMOS_READ(RTC_MINUTES_ALARM) & 0x7f; - alm_tm->tm_hour = CMOS_READ(RTC_HOURS_ALARM) & 0x1f; - alm_tm->tm_wday = CMOS_READ(RTC_DAY_ALARM) & 0x07; - cmd = CMOS_READ(RTC_CMD); - spin_unlock_irqrestore(&ds1286_lock, flags); - - BCD_TO_BIN(alm_tm->tm_min); - BCD_TO_BIN(alm_tm->tm_hour); - alm_tm->tm_sec = 0; -} --- linux-2.5.73/drivers/sgi/char/gconsole.h 2003-06-26 22:07:25.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,33 +0,0 @@ -/* - * This is a temporary measure, we should eventually migrate to - * Gert's generic graphic console code. - */ - -#define cmapsz 8192 -#define CHAR_HEIGHT 16 - -struct console_ops { - void (*set_origin)(unsigned short offset); - void (*hide_cursor)(void); - void (*set_cursor)(int currcons); - void (*get_scrmem)(int currcons); - void (*set_scrmem)(int currcons, long offset); - int (*set_get_cmap)(unsigned char *arg, int set); - void (*blitc)(unsigned short charattr, unsigned long addr); - void (*memsetw)(void *s, unsigned short c, unsigned int count); - void (*memcpyw)(unsigned short *to, unsigned short *from, unsigned int count); -}; - -void register_gconsole (struct console_ops *); - -/* This points to the system console */ -extern struct console_ops *gconsole; - -extern void gfx_init (const char **name); - -extern void __set_origin (unsigned short offset); -extern void hide_cursor (void); -extern unsigned char vga_font[]; - -extern void disable_gconsole (void); -extern void enable_gconsole (void); --- linux-2.5.73/drivers/sgi/char/graphics.c 2003-06-26 22:07:25.000000000 -0700 +++ /dev/null 2002-08-30 16:31:37.000000000 -0700 @@ -1,377 +0,0 @@ -/* - * gfx.c: support for SGI's /dev/graphics, /dev/opengl - * - * Author: Miguel de Icaza (miguel@nuclecu.unam.mx) - * Ralf Baechle (ralf@gnu.org) - * Ulf Carlsson (ulfc@bun.falkenberg.se) - * - * On IRIX, /dev/graphics is [10, 146] - * /dev/opengl is [10, 147] - * - * From a mail with Mark J. Kilgard, /dev/opengl and /dev/graphics are - * the same thing, the use of /dev/graphics seems deprecated though. - * - * The reason that the original SGI programmer had to use only one - * device for all the graphic cards on the system will remain a - * mistery for the rest of our lives. Why some ioctls take a board - * number and some others not? Mistery. Why do they map the hardware - * registers into the user address space with an ioctl instead of - * mmap? Mistery too. Why they did not use the standard way of - * making ioctl constants and instead sticked a random constant? - * Mistery too. - * - * We implement those misterious things, and tried not to think about - * the reasons behind them. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "gconsole.h" -#include "graphics.h" -#include "usema.h" -#include -#include -#include -#include -#include