diff -ur stock/linux-2.4.0-test11-pre5/arch/i386/kernel/bluesmoke.c linux-2.4.0-test11-pre5/arch/i386/kernel/bluesmoke.c
--- stock/linux-2.4.0-test11-pre5/arch/i386/kernel/bluesmoke.c	Wed Nov 15 11:24:19 2000
+++ linux-2.4.0-test11-pre5/arch/i386/kernel/bluesmoke.c	Wed Nov 15 13:23:02 2000
@@ -1,7 +1,9 @@
 /*
- *	Machine Check Handler For PII/PIII
+ * 	Machine Check Exception handler.  If the machine supports
+ *	Machine Check Architecture, give further information.
  */
 
+
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
@@ -12,53 +14,66 @@
 
 void do_machine_check(struct pt_regs * regs, long error_code)
 {
+	struct cpuinfo_x86 *c = current_cpu_data;
 	int recover=1;
 	u32 alow, ahigh, high, low;
 	u32 mcgstl, mcgsth;
 	int i;
 	
-	rdmsr(0x17a, mcgstl, mcgsth);
-	if(mcgstl&(1<<0))	/* Recoverable ? */
-		recover=0;
-
-	printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n", smp_processor_id(), mcgsth, mcgstl);
-	
-	for(i=0;i<banks;i++)
+	if( test_bit(X86_FEATURE_MCA, &c->x86_capability) )
 	{
-		rdmsr(0x401+i*4,low, high);
-		if(high&(1<<31))
+		/* MCA available; at least we can figure out what just hit us */
+
+		rdmsr(0x17a, mcgstl, mcgsth);
+		if(mcgstl&(1<<0))	/* Recoverable ? */
+			recover=0;
+		
+		printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
+		       smp_processor_id(), mcgsth, mcgstl);
+		
+		for(i=0;i<banks;i++)
 		{
-			if(high&(1<<29))
-				recover|=1;
-			if(high&(1<<25))
-				recover|=2;
-			printk(KERN_EMERG "Bank %d: %08x%08x", i, high, low);
-			high&=~(1<<31);
-			if(high&(1<<27))
+			rdmsr(0x401+i*4,low, high);
+			if(high&(1<<31))
 			{
-				rdmsr(0x402+i*4, alow, ahigh);
-				printk("[%08x%08x]", alow, ahigh);
+				if(high&(1<<29))
+					recover|=1;
+				if(high&(1<<25))
+					recover|=2;
+				printk(KERN_EMERG "Bank %d: %08x%08x", i, high, low);
+				high&=~(1<<31);
+				if(high&(1<<27))
+				{
+					rdmsr(0x402+i*4, alow, ahigh);
+					printk("[%08x%08x]", alow, ahigh);
+				}
+				if(high&(1<<26))
+				{
+					rdmsr(0x402+i*4, alow, ahigh);
+					printk(" at %08x%08x", 
+					       high, low);
+				}
+				/* Clear it */
+				wrmsr(0x401+i*4, 0UL, 0UL);
+				/* Serialize */
+				wmb();
 			}
-			if(high&(1<<26))
-			{
-				rdmsr(0x402+i*4, alow, ahigh);
-				printk(" at %08x%08x", 
-					high, low);
-			}
-			/* Clear it */
-			wrmsr(0x401+i*4, 0UL, 0UL);
-			/* Serialize */
-			wmb();
 		}
-	}
 	
-	if(recover&2)
-		panic("CPU context corrupt");
-	if(recover&1)
+		if(recover&2)
+			panic("CPU context corrupt");
+		if(recover&1)
+			panic("Unable to continue");
+		printk(KERN_EMERG "Attempting to continue.\n");
+		mcgstl&=~(1<<2);
+		wrmsr(0x17a,mcgstl, mcgsth);
+	} else {
+		/* No MCA available; we have to assume the worst */
+
+		printk(KERN_EMERG "CPU %d: Machine Check Exception (no data available)\n",
+		       smp_processor_id());
 		panic("Unable to continue");
-	printk(KERN_EMERG "Attempting to continue.\n");
-	mcgstl&=~(1<<2);
-	wrmsr(0x17a,mcgstl, mcgsth);
+	}
 }
 
 
@@ -70,37 +85,38 @@
 {
 	u32 l, h;
 	int i;
-	static int done;
-
-	if( c->x86_vendor != X86_VENDOR_INTEL )
-		return;
+	char *what;
 	
-	if( !test_bit(X86_FEATURE_TSC, &c->x86_capability) )
-		return;
-		
-	if( !test_bit(X86_FEATURE_MCA, &c->x86_capability) )
+	/* We should not check for vendor here.  The MCA capability
+	   bit, below, should only be set if the CPU has the Machine
+	   Check Architecture as specified by Intel.  It's up to
+	   identify_cpu() to make sure that is true! */
+
+	if( !test_bit(X86_FEATURE_MCE, &c->x86_capability) )
 		return;
-		
-	/* Ok machine check is available */
 	
-	if(done==0)
-		printk(KERN_INFO "Intel machine check architecture supported.\n");
-	rdmsr(0x179, l, h);
-	if(l&(1<<8))
-		wrmsr(0x17b, 0xffffffff, 0xffffffff);
-	banks = l&0xff;
-	for(i=1;i<banks;i++)
-	{
-		wrmsr(0x400+4*i, 0xffffffff, 0xffffffff); 
-	}
-	for(i=0;i<banks;i++)
+	if( test_bit(X86_FEATURE_MCA, &c->x86_capability) )
 	{
-		wrmsr(0x401+4*i, 0x0, 0x0); 
+		/* Ok, Machine Check Architecture is available */
+		
+		rdmsr(0x179, l, h);
+		if(l&(1<<8))
+			wrmsr(0x17b, 0xffffffff, 0xffffffff);
+		banks = l&0xff;
+		for(i=1;i<banks;i++)
+			wrmsr(0x400+4*i, 0xffffffff, 0xffffffff); 
+		for(i=0;i<banks;i++)
+			wrmsr(0x401+4*i, 0x0, 0x0); 
+		what = "reporting";
+	} else {
+		/* We have MCE but no MCA. */
+		what = "exception";
 	}
+	
 	__asm__ __volatile__ (
 		"movl %%cr4, %%eax\n\t"
 		"orl $0x40, %%eax\n\t"
 		"movl %%eax, %%cr4\n\t" : : : "eax");
-	printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n", smp_processor_id());
-	done=1;
+	printk(KERN_INFO "Machine check %s enabled on CPU#%d.\n",
+	       what, smp_processor_id());
 }
diff -ur stock/linux-2.4.0-test11-pre5/arch/i386/kernel/setup.c linux-2.4.0-test11-pre5/arch/i386/kernel/setup.c
--- stock/linux-2.4.0-test11-pre5/arch/i386/kernel/setup.c	Wed Nov 15 11:24:19 2000
+++ linux-2.4.0-test11-pre5/arch/i386/kernel/setup.c	Wed Nov 15 11:37:38 2000
@@ -1483,7 +1483,6 @@
 #ifndef CONFIG_M686
 	static int f00f_workaround_enabled = 0;
 #endif
-	extern void mcheck_init(struct cpuinfo_x86 *c);
 	char *p = NULL;
 
 #ifndef CONFIG_M686
@@ -1575,9 +1574,6 @@
 
 	if ( p )
 		strcpy(c->x86_model_id, p);
-
-	/* Enable MCA if available */
-	mcheck_init(c);
 }
 
 void __init get_cpu_vendor(struct cpuinfo_x86 *c)
@@ -1797,6 +1793,8 @@
 	return have_cpuid_p();	/* Check to see if CPUID now enabled? */
 }
 
+extern void mcheck_init(struct cpuinfo_x86 *c);
+
 /*
  * This does the hard work of actually picking apart the CPU stuff...
  */
@@ -1919,6 +1917,9 @@
 	 * The vendor-specific functions might have changed features.  Now
 	 * we do "generic changes."
 	 */
+
+	/* Enable Machine Check Architecture if appropriate */
+	mcheck_init(c);
 
 	/* TSC disabled? */
 #ifdef CONFIG_TSC
diff -ur stock/linux-2.4.0-test11-pre5/include/asm-i386/cpufeature.h linux-2.4.0-test11-pre5/include/asm-i386/cpufeature.h
--- stock/linux-2.4.0-test11-pre5/include/asm-i386/cpufeature.h	Wed Nov 15 11:24:21 2000
+++ linux-2.4.0-test11-pre5/include/asm-i386/cpufeature.h	Wed Nov 15 11:35:10 2000
@@ -20,7 +20,7 @@
 #define X86_FEATURE_TSC		(0*32+ 4) /* Time Stamp Counter */
 #define X86_FEATURE_MSR		(0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
 #define X86_FEATURE_PAE		(0*32+ 6) /* Physical Address Extensions */
-#define X86_FEATURE_MCE		(0*32+ 7) /* Machine Check Architecture */
+#define X86_FEATURE_MCE		(0*32+ 7) /* Machine Check Exception */
 #define X86_FEATURE_CX8		(0*32+ 8) /* CMPXCHG8 instruction */
 #define X86_FEATURE_APIC	(0*32+ 9) /* Onboard APIC */
 #define X86_FEATURE_SEP		(0*32+11) /* SYSENTER/SYSEXIT */